Sat Dec 18 06:48:10 UTC 2021 I: starting to build yosys/buster/amd64 on jenkins on '2021-12-18 06:48' Sat Dec 18 06:48:10 UTC 2021 I: The jenkins build log is/was available at https://jenkins.debian.net/userContent/reproducible/debian/build_service/amd64_19/95214/console.log Sat Dec 18 06:48:10 UTC 2021 I: Downloading source for buster/yosys=0.8-1 --2021-12-18 06:48:11-- http://deb.debian.org/debian/pool/main/y/yosys/yosys_0.8-1.dsc Connecting to 78.137.99.97:3128... connected. Proxy request sent, awaiting response... 200 OK Length: 2611 (2.5K) Saving to: ‘yosys_0.8-1.dsc’ 0K .. 100% 25.5M=0s 2021-12-18 06:48:11 (25.5 MB/s) - ‘yosys_0.8-1.dsc’ saved [2611/2611] Sat Dec 18 06:48:11 UTC 2021 I: yosys_0.8-1.dsc -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA512 Format: 3.0 (quilt) Source: yosys Binary: yosys, yosys-dev, yosys-doc Architecture: any all Version: 0.8-1 Maintainer: Debian Science Maintainers Uploaders: Ruben Undheim , Sebastian Kuzminsky Homepage: http://www.clifford.at/yosys Standards-Version: 4.2.1 Vcs-Browser: https://salsa.debian.org/science-team/yosys Vcs-Git: https://salsa.debian.org/science-team/yosys.git Testsuite: autopkgtest Build-Depends: debhelper (>= 11), dh-python, tcl-dev, libreadline-dev, bison, flex, gawk, libffi-dev, pkg-config, txt2man, iverilog (>= 10.1), python3, berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg) Build-Depends-Indep: texlive-base, texlive-generic-recommended, texlive-fonts-recommended, texlive-fonts-extra, texlive-latex-base, texlive-latex-extra, texlive-font-utils, texlive-science, texlive-publishers, texlive-bibtex-extra, lmodern, graphviz Package-List: yosys deb electronics optional arch=any yosys-dev deb electronics optional arch=any yosys-doc deb doc optional arch=all Checksums-Sha1: 4fd01d1ecc47a22b2f539964aa9d73aed2feca09 1118433 yosys_0.8.orig.tar.gz a23fefe071d8aedbf821bc030fafd28d6759aa1d 17232 yosys_0.8-1.debian.tar.xz Checksums-Sha256: 07760fe732003585b26d97f9e02bcddf242ff7fc33dbd415446ac7c70e85c66f 1118433 yosys_0.8.orig.tar.gz d6f64b2fc65249e869f6132e1001d966eb76dd35f7486ebe0e58c7ced4dccf3c 17232 yosys_0.8-1.debian.tar.xz Files: 58dfa0e964583dcdec4df95b9736875e 1118433 yosys_0.8.orig.tar.gz bc3143e06c81684f21166708c8980575 17232 yosys_0.8-1.debian.tar.xz Dgit: fb968be4a2708c23d5245b8c53fad6b3cb0c7115 debian archive/debian/0.8-1 https://git.dgit.debian.org/yosys -----BEGIN PGP SIGNATURE----- iQJMBAEBCgA2FiEENHTECWcp7QxRgH085pgix+ApWM0FAlvHZ0IYHHJ1YmVuLnVu ZGhlaW1AZ21haWwuY29tAAoJEOaYIsfgKVjNWcgP/0gyp5mZ9h7YOdCinFNywYFY z/iQ2XH1A3etlZT6Xt0Cx3JJyoqrLFU80+o/0egRn3GS0VT1NJC5jEFjcpx1r+Ri qFdhNPNJVMnBtGdy+73A0HdU15ywe+AHvaatYxlLfrw374A7mhWs13XsYnmqFeP8 nf39uhTILSwdqFkAElqwPm5MiQWAT63ge787Yui8Onh6VBtPvRUfDjLP4jobrabU 4CgTe6qy4iNUmDr4ieb4ZX7OukGVAfQl58oRTQLDxqMdzhrNbScWJvGYf6usUnAo Bmp/7IwAIQRCsAxt2T6GFRsev4pdaDwj2QZ/Aovx4U028eoYpP+x4AqvxGJiBhxj VKYrgnH4KX9Zhfa97dim9UfjNPbyTlhjHGHIaVRoyGbknlbqzURcrVKx3ms/SCXr ndS7BYmv9dgat/o+DIcGfhRlV16fdxU1eHQnEjCNwqMvlXsHfhBG+xgqjOE7MY4k 4s/Q2rcLOVJ9+6vPVTtmGxboZREv9VpYwIZK+Z6iiXxgdJ/CpkvocGBEZHb1ntV4 yuYMFfzxhSQIeXDDEzoNuEIr41hh9k3+Y+0vC+mPXH7c8WhPZtO5s9wCMcjCmyCA ivpu8shgSrdpVI0/wQ14hsRUCowurVNqWLUT4vUErW4eQIYEFjoXb8ThTBabpbGk ULLcRSw7Yo4FQQBAWcZY =7Nv+ -----END PGP SIGNATURE----- Sat Dec 18 06:48:11 UTC 2021 I: Checking whether the package is not for us Sat Dec 18 06:48:11 UTC 2021 I: Starting 1st build on remote node ionos1-amd64.debian.net. Sat Dec 18 06:48:11 UTC 2021 I: Preparing to do remote build '1' on ionos1-amd64.debian.net. Sat Dec 18 07:18:00 UTC 2021 I: Deleting $TMPDIR on ionos1-amd64.debian.net. I: pbuilder: network access will be disabled during build I: Current time: Fri Dec 17 18:48:13 -12 2021 I: pbuilder-time-stamp: 1639810093 I: Building the build Environment I: extracting base tarball [/var/cache/pbuilder/buster-reproducible-base.tgz] I: copying local configuration I: mounting /proc filesystem I: mounting /sys filesystem I: creating /{dev,run}/shm I: mounting /dev/pts filesystem I: redirecting /dev/ptmx to /dev/pts/ptmx I: policy-rc.d already exists I: Copying source file I: copying [yosys_0.8-1.dsc] I: copying [./yosys_0.8.orig.tar.gz] I: copying [./yosys_0.8-1.debian.tar.xz] I: Extracting source gpgv: unknown type of key resource 'trustedkeys.kbx' gpgv: keyblock resource '/root/.gnupg/trustedkeys.kbx': General error gpgv: Signature made Wed Oct 17 04:45:54 2018 -12 gpgv: using RSA key 3474C4096729ED0C51807D3CE69822C7E02958CD gpgv: issuer "ruben.undheim@gmail.com" gpgv: Can't check signature: No public key dpkg-source: warning: failed to verify signature on ./yosys_0.8-1.dsc dpkg-source: info: extracting yosys in yosys-0.8 dpkg-source: info: unpacking yosys_0.8.orig.tar.gz dpkg-source: info: unpacking yosys_0.8-1.debian.tar.xz dpkg-source: info: using patch list from debian/patches/series dpkg-source: info: applying 01_gitrevision.patch dpkg-source: info: applying 02_removeabc.patch dpkg-source: info: applying 05_abc_executable.patch dpkg-source: info: applying switch-to-free-font.patch dpkg-source: info: applying manual-build.patch dpkg-source: info: applying kfreebsd-support.patch dpkg-source: info: applying 0007-Disable-pretty-build.patch dpkg-source: info: applying 0009-Some-spelling-errors-fixed.patch dpkg-source: info: applying 0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch dpkg-source: info: applying 0010-Fix-adding-of-sys.path-in-yosys-smtbmc.patch dpkg-source: info: applying 0011-Do-not-show-g-build-flags-in-Version-string.patch dpkg-source: info: applying 0012-Skip-non-deterministic-test-causing-random-FTBFS-on-.patch dpkg-source: info: applying 0013-Let-dpkg-buildpackage-handle-stripping-of-binaries.patch I: using fakeroot in build. I: Installing the build-deps I: user script /srv/workspace/pbuilder/1299452/tmp/hooks/D02_print_environment starting I: set BUILDDIR='/build' BUILDUSERGECOS='first user,first room,first work-phone,first home-phone,first other' BUILDUSERNAME='pbuilder1' BUILD_ARCH='amd64' DEBIAN_FRONTEND='noninteractive' DEB_BUILD_OPTIONS='buildinfo=+all reproducible=+all parallel=15' DISTRIBUTION='' HOME='/root' HOST_ARCH='amd64' IFS=' ' INVOCATION_ID='22bc4b474617453f9d2ed9fd435ee147' LANG='C' LANGUAGE='en_US:en' LC_ALL='C' MAIL='/var/mail/root' OPTIND='1' PATH='/usr/sbin:/usr/bin:/sbin:/bin:/usr/games' PBCURRENTCOMMANDLINEOPERATION='build' PBUILDER_OPERATION='build' PBUILDER_PKGDATADIR='/usr/share/pbuilder' PBUILDER_PKGLIBDIR='/usr/lib/pbuilder' PBUILDER_SYSCONFDIR='/etc' PPID='1299452' PS1='# ' PS2='> ' PS4='+ ' PWD='/' SHELL='/bin/bash' SHLVL='2' SUDO_COMMAND='/usr/bin/timeout -k 18.1h 18h /usr/bin/ionice -c 3 /usr/bin/nice /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/pbuilderrc_qy1Q --hookdir /etc/pbuilder/first-build-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/buster-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/b1 --logfile b1/build.log yosys_0.8-1.dsc' SUDO_GID='110' SUDO_UID='105' SUDO_USER='jenkins' TERM='unknown' TZ='/usr/share/zoneinfo/Etc/GMT+12' USER='root' _='/usr/bin/systemd-run' http_proxy='http://78.137.99.97:3128' I: uname -a Linux ionos1-amd64 5.10.0-9-amd64 #1 SMP Debian 5.10.70-1 (2021-09-30) x86_64 GNU/Linux I: ls -l /bin total 5116 -rwxr-xr-x 1 root root 1168776 Apr 17 2019 bash -rwxr-xr-x 3 root root 38984 Jul 10 2019 bunzip2 -rwxr-xr-x 3 root root 38984 Jul 10 2019 bzcat lrwxrwxrwx 1 root root 6 Jul 10 2019 bzcmp -> bzdiff -rwxr-xr-x 1 root root 2227 Jul 10 2019 bzdiff lrwxrwxrwx 1 root root 6 Jul 10 2019 bzegrep -> bzgrep -rwxr-xr-x 1 root root 4877 Jun 24 2019 bzexe lrwxrwxrwx 1 root root 6 Jul 10 2019 bzfgrep -> bzgrep -rwxr-xr-x 1 root root 3641 Jul 10 2019 bzgrep -rwxr-xr-x 3 root root 38984 Jul 10 2019 bzip2 -rwxr-xr-x 1 root root 14328 Jul 10 2019 bzip2recover lrwxrwxrwx 1 root root 6 Jul 10 2019 bzless -> bzmore -rwxr-xr-x 1 root root 1297 Jul 10 2019 bzmore -rwxr-xr-x 1 root root 43744 Feb 28 2019 cat -rwxr-xr-x 1 root root 64320 Feb 28 2019 chgrp -rwxr-xr-x 1 root root 64288 Feb 28 2019 chmod -rwxr-xr-x 1 root root 72512 Feb 28 2019 chown -rwxr-xr-x 1 root root 146880 Feb 28 2019 cp -rwxr-xr-x 1 root root 121464 Jan 17 2019 dash -rwxr-xr-x 1 root root 109408 Feb 28 2019 date -rwxr-xr-x 1 root root 76712 Feb 28 2019 dd -rwxr-xr-x 1 root root 93744 Feb 28 2019 df -rwxr-xr-x 1 root root 138856 Feb 28 2019 dir -rwxr-xr-x 1 root root 84288 Jan 9 2019 dmesg lrwxrwxrwx 1 root root 8 Sep 26 2018 dnsdomainname -> hostname lrwxrwxrwx 1 root root 8 Sep 26 2018 domainname -> hostname -rwxr-xr-x 1 root root 39520 Feb 28 2019 echo -rwxr-xr-x 1 root root 28 Jan 7 2019 egrep -rwxr-xr-x 1 root root 35424 Feb 28 2019 false -rwxr-xr-x 1 root root 28 Jan 7 2019 fgrep -rwxr-xr-x 1 root root 68880 Jan 9 2019 findmnt -rwsr-xr-x 1 root root 34896 Apr 22 2020 fusermount -rwxr-xr-x 1 root root 198976 Jan 7 2019 grep -rwxr-xr-x 2 root root 2345 Jan 5 2019 gunzip -rwxr-xr-x 1 root root 6375 Jan 5 2019 gzexe -rwxr-xr-x 1 root root 98048 Jan 5 2019 gzip -rwxr-xr-x 1 root root 26696 Sep 26 2018 hostname -rwxr-xr-x 1 root root 68552 Feb 28 2019 ln -rwxr-xr-x 1 root root 56760 Jul 26 2018 login -rwxr-xr-x 1 root root 138856 Feb 28 2019 ls -rwxr-xr-x 1 root root 108624 Jan 9 2019 lsblk -rwxr-xr-x 1 root root 89088 Feb 28 2019 mkdir -rwxr-xr-x 1 root root 68544 Feb 28 2019 mknod -rwxr-xr-x 1 root root 43808 Feb 28 2019 mktemp -rwxr-xr-x 1 root root 43008 Jan 9 2019 more -rwsr-xr-x 1 root root 51280 Jan 9 2019 mount -rwxr-xr-x 1 root root 14408 Jan 9 2019 mountpoint -rwxr-xr-x 1 root root 138728 Feb 28 2019 mv lrwxrwxrwx 1 root root 8 Sep 26 2018 nisdomainname -> hostname lrwxrwxrwx 1 root root 14 Feb 14 2019 pidof -> /sbin/killall5 -rwxr-xr-x 1 root root 39616 Feb 28 2019 pwd lrwxrwxrwx 1 root root 4 Apr 17 2019 rbash -> bash -rwxr-xr-x 1 root root 47776 Feb 28 2019 readlink -rwxr-xr-x 1 root root 68416 Feb 28 2019 rm -rwxr-xr-x 1 root root 47776 Feb 28 2019 rmdir -rwxr-xr-x 1 root root 23312 Jan 21 2019 run-parts -rwxr-xr-x 1 root root 122224 Dec 22 2018 sed lrwxrwxrwx 1 root root 4 Nov 7 09:58 sh -> dash -rwxr-xr-x 1 root root 39552 Feb 28 2019 sleep -rwxr-xr-x 1 root root 80672 Feb 28 2019 stty -rwsr-xr-x 1 root root 63568 Jan 9 2019 su -rwxr-xr-x 1 root root 35488 Feb 28 2019 sync -rwxr-xr-x 1 root root 445560 Apr 23 2019 tar -rwxr-xr-x 1 root root 14440 Jan 21 2019 tempfile -rwxr-xr-x 1 root root 97152 Feb 28 2019 touch -rwxr-xr-x 1 root root 35424 Feb 28 2019 true -rwxr-xr-x 1 root root 14328 Apr 22 2020 ulockmgr_server -rwsr-xr-x 1 root root 34888 Jan 9 2019 umount -rwxr-xr-x 1 root root 39584 Feb 28 2019 uname -rwxr-xr-x 2 root root 2345 Jan 5 2019 uncompress -rwxr-xr-x 1 root root 138856 Feb 28 2019 vdir -rwxr-xr-x 1 root root 34896 Jan 9 2019 wdctl -rwxr-xr-x 1 root root 946 Jan 21 2019 which lrwxrwxrwx 1 root root 8 Sep 26 2018 ypdomainname -> hostname -rwxr-xr-x 1 root root 1983 Jan 5 2019 zcat -rwxr-xr-x 1 root root 1677 Jan 5 2019 zcmp -rwxr-xr-x 1 root root 5879 Jan 5 2019 zdiff -rwxr-xr-x 1 root root 29 Jan 5 2019 zegrep -rwxr-xr-x 1 root root 29 Jan 5 2019 zfgrep -rwxr-xr-x 1 root root 2080 Jan 5 2019 zforce -rwxr-xr-x 1 root root 7584 Jan 5 2019 zgrep -rwxr-xr-x 1 root root 2205 Jan 5 2019 zless -rwxr-xr-x 1 root root 1841 Jan 5 2019 zmore -rwxr-xr-x 1 root root 4552 Jan 5 2019 znew I: user script /srv/workspace/pbuilder/1299452/tmp/hooks/D02_print_environment finished -> Attempting to satisfy build-dependencies -> Creating pbuilder-satisfydepends-dummy package Package: pbuilder-satisfydepends-dummy Version: 0.invalid.0 Architecture: amd64 Maintainer: Debian Pbuilder Team Description: Dummy package to satisfy dependencies with aptitude - created by pbuilder This package was created automatically by pbuilder to satisfy the build-dependencies of the package being currently built. Depends: debhelper (>= 11), dh-python, tcl-dev, libreadline-dev, bison, flex, gawk, libffi-dev, pkg-config, txt2man, iverilog (>= 10.1), python3, berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg), texlive-base, texlive-generic-recommended, texlive-fonts-recommended, texlive-fonts-extra, texlive-latex-base, texlive-latex-extra, texlive-font-utils, texlive-science, texlive-publishers, texlive-bibtex-extra, lmodern, graphviz dpkg-deb: building package 'pbuilder-satisfydepends-dummy' in '/tmp/satisfydepends-aptitude/pbuilder-satisfydepends-dummy.deb'. Selecting previously unselected package pbuilder-satisfydepends-dummy. (Reading database ... 19195 files and directories currently installed.) Preparing to unpack .../pbuilder-satisfydepends-dummy.deb ... Unpacking pbuilder-satisfydepends-dummy (0.invalid.0) ... dpkg: pbuilder-satisfydepends-dummy: dependency problems, but configuring anyway as you requested: pbuilder-satisfydepends-dummy depends on debhelper (>= 11); however: Package debhelper is not installed. pbuilder-satisfydepends-dummy depends on dh-python; however: Package dh-python is not installed. pbuilder-satisfydepends-dummy depends on tcl-dev; however: Package tcl-dev is not installed. pbuilder-satisfydepends-dummy depends on libreadline-dev; however: Package libreadline-dev is not installed. pbuilder-satisfydepends-dummy depends on bison; however: Package bison is not installed. pbuilder-satisfydepends-dummy depends on flex; however: Package flex is not installed. pbuilder-satisfydepends-dummy depends on gawk; however: Package gawk is not installed. pbuilder-satisfydepends-dummy depends on libffi-dev; however: Package libffi-dev is not installed. pbuilder-satisfydepends-dummy depends on pkg-config; however: Package pkg-config is not installed. pbuilder-satisfydepends-dummy depends on txt2man; however: Package txt2man is not installed. pbuilder-satisfydepends-dummy depends on iverilog (>= 10.1); however: Package iverilog is not installed. pbuilder-satisfydepends-dummy depends on python3; however: Package python3 is not installed. pbuilder-satisfydepends-dummy depends on berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg); however: Package berkeley-abc is not installed. pbuilder-satisfydepends-dummy depends on texlive-base; however: Package texlive-base is not installed. pbuilder-satisfydepends-dummy depends on texlive-generic-recommended; however: Package texlive-generic-recommended is not installed. pbuilder-satisfydepends-dummy depends on texlive-fonts-recommended; however: Package texlive-fonts-recommended is not installed. pbuilder-satisfydepends-dummy depends on texlive-fonts-extra; however: Package texlive-fonts-extra is not installed. pbuilder-satisfydepends-dummy depends on texlive-latex-base; however: Package texlive-latex-base is not installed. pbuilder-satisfydepends-dummy depends on texlive-latex-extra; however: Package texlive-latex-extra is not installed. pbuilder-satisfydepends-dummy depends on texlive-font-utils; however: Package texlive-font-utils is not installed. pbuilder-satisfydepends-dummy depends on texlive-science; however: Package texlive-science is not installed. pbuilder-satisfydepends-dummy depends on texlive-publishers; however: Package texlive-publishers is not installed. pbuilder-satisfydepends-dummy depends on texlive-bibtex-extra; however: Package texlive-bibtex-extra is not installed. pbuilder-satisfydepends-dummy depends on lmodern; however: Package lmodern is not installed. pbuilder-satisfydepends-dummy depends on graphviz; however: Package graphviz is not installed. Setting up pbuilder-satisfydepends-dummy (0.invalid.0) ... Reading package lists... Building dependency tree... Reading state information... Initializing package states... Writing extended state information... Building tag database... pbuilder-satisfydepends-dummy is already installed at the requested version (0.invalid.0) pbuilder-satisfydepends-dummy is already installed at the requested version (0.invalid.0) The following NEW packages will be installed: autoconf{a} automake{a} autopoint{a} autotools-dev{a} berkeley-abc{a} bison{a} bsdmainutils{a} debhelper{a} dh-autoreconf{a} dh-python{a} dh-strip-nondeterminism{a} dwz{a} file{a} flex{a} fontconfig{a} fontconfig-config{a} fonts-dejavu-core{a} fonts-gfs-baskerville{a} fonts-gfs-porson{a} fonts-lmodern{a} gawk{a} gettext{a} gettext-base{a} graphviz{a} groff-base{a} intltool-debian{a} iverilog{a} libarchive-zip-perl{a} libavahi-client3{a} libavahi-common-data{a} libavahi-common3{a} libbison-dev{a} libbrotli1{a} libbsd0{a} libcairo2{a} libcdt5{a} libcgraph6{a} libcroco3{a} libcups2{a} libcupsimage2{a} libdatrie1{a} libdbus-1-3{a} libelf1{a} libexpat1{a} libffi-dev{a} libfile-stripnondeterminism-perl{a} libfontconfig1{a} libfontenc1{a} libfreetype6{a} libfribidi0{a} libgd3{a} libglib2.0-0{a} libgraphite2-3{a} libgs9{a} libgs9-common{a} libgssapi-krb5-2{a} libgts-0.7-5{a} libgvc6{a} libgvpr2{a} libharfbuzz-icu0{a} libharfbuzz0b{a} libice6{a} libicu63{a} libidn11{a} libijs-0.35{a} libjbig0{a} libjbig2dec0{a} libjpeg62-turbo{a} libk5crypto3{a} libkeyutils1{a} libkpathsea6{a} libkrb5-3{a} libkrb5support0{a} liblab-gamut1{a} liblcms2-2{a} libltdl7{a} libmagic-mgc{a} libmagic1{a} libmpdec2{a} libncurses-dev{a} libncurses6{a} libopenjp2-7{a} libpango-1.0-0{a} libpangocairo-1.0-0{a} libpangoft2-1.0-0{a} libpaper-utils{a} libpaper1{a} libpathplan4{a} libpipeline1{a} libpixman-1-0{a} libpng16-16{a} libpotrace0{a} libptexenc1{a} libpython-stdlib{a} libpython2-stdlib{a} libpython2.7-minimal{a} libpython2.7-stdlib{a} libpython3-stdlib{a} libpython3.7-minimal{a} libpython3.7-stdlib{a} libreadline-dev{a} libreadline7{a} libsigsegv2{a} libsm6{a} libssl1.1{a} libsynctex2{a} libtcl8.6{a} libteckit0{a} libtexlua52{a} libtexlua53{a} libtexluajit2{a} libthai-data{a} libthai0{a} libtiff5{a} libtool{a} libuchardet0{a} libwebp6{a} libwoff1{a} libx11-6{a} libx11-data{a} libxau6{a} libxaw7{a} libxcb-render0{a} libxcb-shm0{a} libxcb1{a} libxdmcp6{a} libxdot4{a} libxext6{a} libxi6{a} libxml2{a} libxmu6{a} libxpm4{a} libxrender1{a} libxt6{a} libxxhash0{a} libzzip-0-13{a} lmodern{a} lsb-base{a} m4{a} man-db{a} mime-support{a} pkg-config{a} po-debconf{a} poppler-data{a} preview-latex-style{a} python{a} python-minimal{a} python2{a} python2-minimal{a} python2.7{a} python2.7-minimal{a} python3{a} python3-distutils{a} python3-lib2to3{a} python3-minimal{a} python3.7{a} python3.7-minimal{a} readline-common{a} sensible-utils{a} t1utils{a} tcl{a} tcl-dev{a} tcl8.6{a} tcl8.6-dev{a} tex-common{a} texlive-base{a} texlive-bibtex-extra{a} texlive-binaries{a} texlive-font-utils{a} texlive-fonts-extra{a} texlive-fonts-recommended{a} texlive-generic-recommended{a} texlive-lang-greek{a} texlive-latex-base{a} texlive-latex-extra{a} texlive-latex-recommended{a} texlive-pictures{a} texlive-plain-generic{a} texlive-publishers{a} texlive-science{a} txt2man{a} ucf{a} x11-common{a} xdg-utils{a} xfonts-encodings{a} xfonts-utils{a} zlib1g-dev{a} The following packages are RECOMMENDED but will NOT be installed: curl dbus fonts-adf-accanthis fonts-adf-berenis fonts-adf-gillius fonts-adf-universalis fonts-cabin fonts-comfortaa fonts-croscore fonts-crosextra-caladea fonts-crosextra-carlito fonts-dejavu-extra fonts-droid-fallback fonts-ebgaramond fonts-ebgaramond-extra fonts-font-awesome fonts-freefont-otf fonts-freefont-ttf fonts-gfs-artemisia fonts-gfs-complutum fonts-gfs-didot fonts-gfs-neohellenic fonts-gfs-olga fonts-gfs-solomos fonts-go fonts-junicode fonts-lato fonts-liberation fonts-linuxlibertine fonts-lobstertwo fonts-noto-hinted fonts-noto-mono fonts-oflb-asana-math fonts-open-sans fonts-roboto-unhinted fonts-sil-gentium fonts-sil-gentium-basic fonts-sil-gentiumplus fonts-sil-gentiumplus-compact fonts-stix ghostscript krb5-locales libarchive-cpio-perl libcupsfilters1 libfile-mimeinfo-perl libfl-dev libglib2.0-data libgpm2 libgts-bin libltdl-dev libmail-sendmail-perl libnet-dbus-perl libx11-protocol-perl lynx ps2eps ruby shared-mime-info tex-gyre texlive-fonts-extra-links tipa tk wget x11-utils x11-xserver-utils xdg-user-dirs 0 packages upgraded, 187 newly installed, 0 to remove and 0 not upgraded. Need to get 748 MB of archives. After unpacking 1991 MB will be used. Writing extended state information... Get: 1 http://deb.debian.org/debian buster/main amd64 libbsd0 amd64 0.9.1-2+deb10u1 [99.5 kB] Get: 2 http://deb.debian.org/debian buster/main amd64 bsdmainutils amd64 11.1.2+b1 [191 kB] Get: 3 http://deb.debian.org/debian buster/main amd64 libuchardet0 amd64 0.0.6-3 [64.9 kB] Get: 4 http://deb.debian.org/debian buster/main amd64 groff-base amd64 1.22.4-3+deb10u1 [916 kB] Get: 5 http://deb.debian.org/debian buster/main amd64 libpipeline1 amd64 1.5.1-2 [31.2 kB] Get: 6 http://deb.debian.org/debian buster/main amd64 man-db amd64 2.8.5-2 [1274 kB] Get: 7 http://deb.debian.org/debian buster/main amd64 libpython2.7-minimal amd64 2.7.16-2+deb10u1 [395 kB] Get: 8 http://deb.debian.org/debian buster/main amd64 python2.7-minimal amd64 2.7.16-2+deb10u1 [1369 kB] Get: 9 http://deb.debian.org/debian buster/main amd64 python2-minimal amd64 2.7.16-1 [41.4 kB] Get: 10 http://deb.debian.org/debian buster/main amd64 python-minimal amd64 2.7.16-1 [21.0 kB] Get: 11 http://deb.debian.org/debian buster/main amd64 libssl1.1 amd64 1.1.1d-0+deb10u7 [1539 kB] Get: 12 http://deb.debian.org/debian buster/main amd64 mime-support all 3.62 [37.2 kB] Get: 13 http://deb.debian.org/debian buster/main amd64 libexpat1 amd64 2.2.6-2+deb10u1 [106 kB] Get: 14 http://deb.debian.org/debian buster/main amd64 readline-common all 7.0-5 [70.6 kB] Get: 15 http://deb.debian.org/debian buster/main amd64 libreadline7 amd64 7.0-5 [151 kB] Get: 16 http://deb.debian.org/debian buster/main amd64 libpython2.7-stdlib amd64 2.7.16-2+deb10u1 [1912 kB] Get: 17 http://deb.debian.org/debian buster/main amd64 python2.7 amd64 2.7.16-2+deb10u1 [305 kB] Get: 18 http://deb.debian.org/debian buster/main amd64 libpython2-stdlib amd64 2.7.16-1 [20.8 kB] Get: 19 http://deb.debian.org/debian buster/main amd64 libpython-stdlib amd64 2.7.16-1 [20.8 kB] Get: 20 http://deb.debian.org/debian buster/main amd64 python2 amd64 2.7.16-1 [41.6 kB] Get: 21 http://deb.debian.org/debian buster/main amd64 python amd64 2.7.16-1 [22.8 kB] Get: 22 http://deb.debian.org/debian buster/main amd64 libsigsegv2 amd64 2.12-2 [32.8 kB] Get: 23 http://deb.debian.org/debian buster/main amd64 m4 amd64 1.4.18-2 [203 kB] Get: 24 http://deb.debian.org/debian buster/main amd64 flex amd64 2.6.4-6.2 [456 kB] Get: 25 http://deb.debian.org/debian buster/main amd64 gawk amd64 1:4.2.1+dfsg-1 [660 kB] Get: 26 http://deb.debian.org/debian buster/main amd64 poppler-data all 0.4.9-2 [1473 kB] Get: 27 http://deb.debian.org/debian buster/main amd64 libpython3.7-minimal amd64 3.7.3-2+deb10u3 [589 kB] Get: 28 http://deb.debian.org/debian buster/main amd64 python3.7-minimal amd64 3.7.3-2+deb10u3 [1737 kB] Get: 29 http://deb.debian.org/debian buster/main amd64 python3-minimal amd64 3.7.3-1 [36.6 kB] Get: 30 http://deb.debian.org/debian buster/main amd64 libmpdec2 amd64 2.4.2-2 [87.2 kB] Get: 31 http://deb.debian.org/debian buster/main amd64 libpython3.7-stdlib amd64 3.7.3-2+deb10u3 [1734 kB] Get: 32 http://deb.debian.org/debian buster/main amd64 python3.7 amd64 3.7.3-2+deb10u3 [330 kB] Get: 33 http://deb.debian.org/debian buster/main amd64 libpython3-stdlib amd64 3.7.3-1 [20.0 kB] Get: 34 http://deb.debian.org/debian buster/main amd64 python3 amd64 3.7.3-1 [61.5 kB] Get: 35 http://deb.debian.org/debian buster/main amd64 sensible-utils all 0.0.12 [15.8 kB] Get: 36 http://deb.debian.org/debian buster/main amd64 ucf all 3.0038+nmu1 [69.0 kB] Get: 37 http://deb.debian.org/debian buster/main amd64 tex-common all 6.11 [53.1 kB] Get: 38 http://deb.debian.org/debian buster/main amd64 libmagic-mgc amd64 1:5.35-4+deb10u2 [242 kB] Get: 39 http://deb.debian.org/debian buster/main amd64 libmagic1 amd64 1:5.35-4+deb10u2 [118 kB] Get: 40 http://deb.debian.org/debian buster/main amd64 file amd64 1:5.35-4+deb10u2 [66.4 kB] Get: 41 http://deb.debian.org/debian buster/main amd64 gettext-base amd64 0.19.8.1-9 [123 kB] Get: 42 http://deb.debian.org/debian buster/main amd64 autoconf all 2.69-11 [341 kB] Get: 43 http://deb.debian.org/debian buster/main amd64 autotools-dev all 20180224.1 [77.0 kB] Get: 44 http://deb.debian.org/debian buster/main amd64 automake all 1:1.16.1-4 [771 kB] Get: 45 http://deb.debian.org/debian buster/main amd64 autopoint all 0.19.8.1-9 [434 kB] Get: 46 http://deb.debian.org/debian buster/main amd64 berkeley-abc amd64 1.01+20181130git163bba5+dfsg-1 [5403 kB] Get: 47 http://deb.debian.org/debian buster/main amd64 libbison-dev amd64 2:3.3.2.dfsg-1 [500 kB] Get: 48 http://deb.debian.org/debian buster/main amd64 bison amd64 2:3.3.2.dfsg-1 [871 kB] Get: 49 http://deb.debian.org/debian buster/main amd64 libtool all 2.4.6-9 [547 kB] Get: 50 http://deb.debian.org/debian buster/main amd64 dh-autoreconf all 19 [16.9 kB] Get: 51 http://deb.debian.org/debian buster/main amd64 libarchive-zip-perl all 1.64-1 [96.8 kB] Get: 52 http://deb.debian.org/debian buster/main amd64 libfile-stripnondeterminism-perl all 1.1.2-1 [19.8 kB] Get: 53 http://deb.debian.org/debian buster/main amd64 dh-strip-nondeterminism all 1.1.2-1 [13.0 kB] Get: 54 http://deb.debian.org/debian buster/main amd64 libelf1 amd64 0.176-1.1 [161 kB] Get: 55 http://deb.debian.org/debian buster/main amd64 dwz amd64 0.12-3 [78.0 kB] Get: 56 http://deb.debian.org/debian buster/main amd64 libglib2.0-0 amd64 2.58.3-2+deb10u3 [1259 kB] Get: 57 http://deb.debian.org/debian buster/main amd64 libicu63 amd64 63.1-6+deb10u1 [8300 kB] Get: 58 http://deb.debian.org/debian buster/main amd64 libxml2 amd64 2.9.4+dfsg1-7+deb10u2 [689 kB] Get: 59 http://deb.debian.org/debian buster/main amd64 libcroco3 amd64 0.6.12-3 [145 kB] Get: 60 http://deb.debian.org/debian buster/main amd64 libncurses6 amd64 6.1+20181013-2+deb10u2 [102 kB] Get: 61 http://deb.debian.org/debian buster/main amd64 gettext amd64 0.19.8.1-9 [1303 kB] Get: 62 http://deb.debian.org/debian buster/main amd64 intltool-debian all 0.35.0+20060710.5 [26.8 kB] Get: 63 http://deb.debian.org/debian buster/main amd64 po-debconf all 1.0.21 [248 kB] Get: 64 http://deb.debian.org/debian buster/main amd64 debhelper all 12.1.1 [1016 kB] Get: 65 http://deb.debian.org/debian buster/main amd64 python3-lib2to3 all 3.7.3-1 [76.7 kB] Get: 66 http://deb.debian.org/debian buster/main amd64 python3-distutils all 3.7.3-1 [142 kB] Get: 67 http://deb.debian.org/debian buster/main amd64 dh-python all 3.20190308 [99.3 kB] Get: 68 http://deb.debian.org/debian buster/main amd64 libpng16-16 amd64 1.6.36-6 [292 kB] Get: 69 http://deb.debian.org/debian buster/main amd64 libfreetype6 amd64 2.9.1-3+deb10u2 [380 kB] Get: 70 http://deb.debian.org/debian buster/main amd64 fonts-dejavu-core all 2.37-1 [1068 kB] Get: 71 http://deb.debian.org/debian buster/main amd64 fontconfig-config all 2.13.1-2 [280 kB] Get: 72 http://deb.debian.org/debian buster/main amd64 libfontconfig1 amd64 2.13.1-2 [346 kB] Get: 73 http://deb.debian.org/debian buster/main amd64 fontconfig amd64 2.13.1-2 [405 kB] Get: 74 http://deb.debian.org/debian buster/main amd64 fonts-gfs-baskerville all 1.1-5 [43.4 kB] Get: 75 http://deb.debian.org/debian buster/main amd64 fonts-gfs-porson all 1.1-6 [33.5 kB] Get: 76 http://deb.debian.org/debian buster/main amd64 fonts-lmodern all 2.004.5-6 [4539 kB] Get: 77 http://deb.debian.org/debian buster/main amd64 libpixman-1-0 amd64 0.36.0-1 [537 kB] Get: 78 http://deb.debian.org/debian buster/main amd64 libxau6 amd64 1:1.0.8-1+b2 [19.9 kB] Get: 79 http://deb.debian.org/debian buster/main amd64 libxdmcp6 amd64 1:1.1.2-3 [26.3 kB] Get: 80 http://deb.debian.org/debian buster/main amd64 libxcb1 amd64 1.13.1-2 [137 kB] Get: 81 http://deb.debian.org/debian buster/main amd64 libx11-data all 2:1.6.7-1+deb10u2 [299 kB] Get: 82 http://deb.debian.org/debian buster/main amd64 libx11-6 amd64 2:1.6.7-1+deb10u2 [757 kB] Get: 83 http://deb.debian.org/debian buster/main amd64 libxcb-render0 amd64 1.13.1-2 [109 kB] Get: 84 http://deb.debian.org/debian buster/main amd64 libxcb-shm0 amd64 1.13.1-2 [99.2 kB] Get: 85 http://deb.debian.org/debian buster/main amd64 libxext6 amd64 2:1.3.3-1+b2 [52.5 kB] Get: 86 http://deb.debian.org/debian buster/main amd64 libxrender1 amd64 1:0.9.10-1 [33.0 kB] Get: 87 http://deb.debian.org/debian buster/main amd64 libcairo2 amd64 1.16.0-4+deb10u1 [688 kB] Get: 88 http://deb.debian.org/debian buster/main amd64 libcdt5 amd64 2.40.1-6+deb10u1 [60.7 kB] Get: 89 http://deb.debian.org/debian buster/main amd64 libcgraph6 amd64 2.40.1-6+deb10u1 [84.2 kB] Get: 90 http://deb.debian.org/debian buster/main amd64 libjpeg62-turbo amd64 1:1.5.2-2+deb10u1 [133 kB] Get: 91 http://deb.debian.org/debian buster/main amd64 libjbig0 amd64 2.1-3.1+b2 [31.0 kB] Get: 92 http://deb.debian.org/debian buster/main amd64 libwebp6 amd64 0.6.1-2+deb10u1 [261 kB] Get: 93 http://deb.debian.org/debian buster/main amd64 libtiff5 amd64 4.1.0+git191117-2~deb10u2 [271 kB] Get: 94 http://deb.debian.org/debian buster/main amd64 libxpm4 amd64 1:3.5.12-1 [49.1 kB] Get: 95 http://deb.debian.org/debian buster/main amd64 libgd3 amd64 2.2.5-5.2 [136 kB] Get: 96 http://deb.debian.org/debian buster/main amd64 libgts-0.7-5 amd64 0.7.6+darcs121130-4 [158 kB] Get: 97 http://deb.debian.org/debian buster/main amd64 libltdl7 amd64 2.4.6-9 [390 kB] Get: 98 http://deb.debian.org/debian buster/main amd64 libfribidi0 amd64 1.0.5-3.1+deb10u1 [63.7 kB] Get: 99 http://deb.debian.org/debian buster/main amd64 libthai-data all 0.1.28-2 [170 kB] Get: 100 http://deb.debian.org/debian buster/main amd64 libdatrie1 amd64 0.2.12-2 [39.3 kB] Get: 101 http://deb.debian.org/debian buster/main amd64 libthai0 amd64 0.1.28-2 [54.1 kB] Get: 102 http://deb.debian.org/debian buster/main amd64 libpango-1.0-0 amd64 1.42.4-8~deb10u1 [186 kB] Get: 103 http://deb.debian.org/debian buster/main amd64 libgraphite2-3 amd64 1.3.13-7 [80.7 kB] Get: 104 http://deb.debian.org/debian buster/main amd64 libharfbuzz0b amd64 2.3.1-1 [1187 kB] Get: 105 http://deb.debian.org/debian buster/main amd64 libpangoft2-1.0-0 amd64 1.42.4-8~deb10u1 [68.3 kB] Get: 106 http://deb.debian.org/debian buster/main amd64 libpangocairo-1.0-0 amd64 1.42.4-8~deb10u1 [55.7 kB] Get: 107 http://deb.debian.org/debian buster/main amd64 libpathplan4 amd64 2.40.1-6+deb10u1 [63.6 kB] Get: 108 http://deb.debian.org/debian buster/main amd64 libxdot4 amd64 2.40.1-6+deb10u1 [57.0 kB] Get: 109 http://deb.debian.org/debian buster/main amd64 libgvc6 amd64 2.40.1-6+deb10u1 [646 kB] Get: 110 http://deb.debian.org/debian buster/main amd64 libgvpr2 amd64 2.40.1-6+deb10u1 [213 kB] Get: 111 http://deb.debian.org/debian buster/main amd64 lsb-base all 10.2019051400 [28.4 kB] Get: 112 http://deb.debian.org/debian buster/main amd64 x11-common all 1:7.7+19 [251 kB] Get: 113 http://deb.debian.org/debian buster/main amd64 libice6 amd64 2:1.0.9-2 [58.7 kB] Get: 114 http://deb.debian.org/debian buster/main amd64 liblab-gamut1 amd64 2.40.1-6+deb10u1 [220 kB] Get: 115 http://deb.debian.org/debian buster/main amd64 libsm6 amd64 2:1.2.3-1 [35.1 kB] Get: 116 http://deb.debian.org/debian buster/main amd64 libxt6 amd64 1:1.1.5-1+b3 [190 kB] Get: 117 http://deb.debian.org/debian buster/main amd64 libxmu6 amd64 2:1.1.2-2+b3 [60.8 kB] Get: 118 http://deb.debian.org/debian buster/main amd64 libxaw7 amd64 2:1.0.13-1+b2 [201 kB] Get: 119 http://deb.debian.org/debian buster/main amd64 graphviz amd64 2.40.1-6+deb10u1 [596 kB] Get: 120 http://deb.debian.org/debian buster/main amd64 iverilog amd64 10.2-1.1 [1841 kB] Get: 121 http://deb.debian.org/debian buster/main amd64 libavahi-common-data amd64 0.7-4+deb10u1 [122 kB] Get: 122 http://deb.debian.org/debian buster/main amd64 libavahi-common3 amd64 0.7-4+deb10u1 [54.4 kB] Get: 123 http://deb.debian.org/debian buster/main amd64 libdbus-1-3 amd64 1.12.20-0+deb10u1 [215 kB] Get: 124 http://deb.debian.org/debian buster/main amd64 libavahi-client3 amd64 0.7-4+deb10u1 [58.2 kB] Get: 125 http://deb.debian.org/debian buster/main amd64 libbrotli1 amd64 1.0.7-2+deb10u1 [269 kB] Get: 126 http://deb.debian.org/debian buster/main amd64 libkeyutils1 amd64 1.6-6 [15.0 kB] Get: 127 http://deb.debian.org/debian buster/main amd64 libkrb5support0 amd64 1.17-3+deb10u3 [65.8 kB] Get: 128 http://deb.debian.org/debian buster/main amd64 libk5crypto3 amd64 1.17-3+deb10u3 [122 kB] Get: 129 http://deb.debian.org/debian buster/main amd64 libkrb5-3 amd64 1.17-3+deb10u3 [370 kB] Get: 130 http://deb.debian.org/debian buster/main amd64 libgssapi-krb5-2 amd64 1.17-3+deb10u3 [158 kB] Get: 131 http://deb.debian.org/debian buster/main amd64 libcups2 amd64 2.2.10-6+deb10u4 [324 kB] Get: 132 http://deb.debian.org/debian buster/main amd64 libcupsimage2 amd64 2.2.10-6+deb10u4 [133 kB] Get: 133 http://deb.debian.org/debian buster/main amd64 libffi-dev amd64 3.2.1-9 [156 kB] Get: 134 http://deb.debian.org/debian buster/main amd64 libfontenc1 amd64 1:1.1.3-1+b2 [24.4 kB] Get: 135 http://deb.debian.org/debian buster/main amd64 libgs9-common all 9.27~dfsg-2+deb10u4 [5136 kB] Get: 136 http://deb.debian.org/debian buster/main amd64 libidn11 amd64 1.33-2.2 [116 kB] Get: 137 http://deb.debian.org/debian buster/main amd64 libijs-0.35 amd64 0.35-14 [18.3 kB] Get: 138 http://deb.debian.org/debian buster/main amd64 libjbig2dec0 amd64 0.16-1 [62.0 kB] Get: 139 http://deb.debian.org/debian buster/main amd64 liblcms2-2 amd64 2.9-3 [145 kB] Get: 140 http://deb.debian.org/debian buster/main amd64 libopenjp2-7 amd64 2.3.0-2+deb10u2 [158 kB] Get: 141 http://deb.debian.org/debian buster/main amd64 libpaper1 amd64 1.1.28 [21.3 kB] Get: 142 http://deb.debian.org/debian buster/main amd64 libgs9 amd64 9.27~dfsg-2+deb10u4 [2195 kB] Get: 143 http://deb.debian.org/debian buster/main amd64 libharfbuzz-icu0 amd64 2.3.1-1 [834 kB] Get: 144 http://deb.debian.org/debian buster/main amd64 libkpathsea6 amd64 2018.20181218.49446-1 [167 kB] Get: 145 http://deb.debian.org/debian buster/main amd64 libncurses-dev amd64 6.1+20181013-2+deb10u2 [333 kB] Get: 146 http://deb.debian.org/debian buster/main amd64 libpaper-utils amd64 1.1.28 [18.0 kB] Get: 147 http://deb.debian.org/debian buster/main amd64 libpotrace0 amd64 1.15-1 [26.3 kB] Get: 148 http://deb.debian.org/debian buster/main amd64 libptexenc1 amd64 2018.20181218.49446-1 [61.0 kB] Get: 149 http://deb.debian.org/debian buster/main amd64 libreadline-dev amd64 7.0-5 [133 kB] Get: 150 http://deb.debian.org/debian buster/main amd64 libsynctex2 amd64 2018.20181218.49446-1 [80.5 kB] Get: 151 http://deb.debian.org/debian buster/main amd64 libtcl8.6 amd64 8.6.9+dfsg-2 [1005 kB] Get: 152 http://deb.debian.org/debian buster/main amd64 libteckit0 amd64 2.5.8+ds2-5 [318 kB] Get: 153 http://deb.debian.org/debian buster/main amd64 libtexlua52 amd64 2018.20181218.49446-1 [112 kB] Get: 154 http://deb.debian.org/debian buster/main amd64 libtexlua53 amd64 2018.20181218.49446-1 [126 kB] Get: 155 http://deb.debian.org/debian buster/main amd64 libtexluajit2 amd64 2018.20181218.49446-1 [256 kB] Get: 156 http://deb.debian.org/debian buster/main amd64 libwoff1 amd64 1.0.2-1 [43.2 kB] Get: 157 http://deb.debian.org/debian buster/main amd64 libxi6 amd64 2:1.7.9-1 [82.6 kB] Get: 158 http://deb.debian.org/debian buster/main amd64 libxxhash0 amd64 0.6.5-2 [7156 B] Get: 159 http://deb.debian.org/debian buster/main amd64 libzzip-0-13 amd64 0.13.62-3.2 [55.4 kB] Get: 160 http://deb.debian.org/debian buster/main amd64 xfonts-encodings all 1:1.0.4-2 [574 kB] Get: 161 http://deb.debian.org/debian buster/main amd64 xfonts-utils amd64 1:7.7+6 [93.0 kB] Get: 162 http://deb.debian.org/debian buster/main amd64 lmodern all 2.004.5-6 [9488 kB] Get: 163 http://deb.debian.org/debian buster/main amd64 pkg-config amd64 0.29-6 [63.5 kB] Get: 164 http://deb.debian.org/debian buster/main amd64 preview-latex-style all 11.91-2 [201 kB] Get: 165 http://deb.debian.org/debian buster/main amd64 t1utils amd64 1.41-3 [62.3 kB] Get: 166 http://deb.debian.org/debian buster/main amd64 tcl8.6 amd64 8.6.9+dfsg-2 [123 kB] Get: 167 http://deb.debian.org/debian buster/main amd64 tcl amd64 8.6.9+1 [5636 B] Get: 168 http://deb.debian.org/debian buster/main amd64 zlib1g-dev amd64 1:1.2.11.dfsg-1 [214 kB] Get: 169 http://deb.debian.org/debian buster/main amd64 tcl8.6-dev amd64 8.6.9+dfsg-2 [1001 kB] Get: 170 http://deb.debian.org/debian buster/main amd64 tcl-dev amd64 8.6.9+1 [8204 B] Get: 171 http://deb.debian.org/debian buster/main amd64 texlive-binaries amd64 2018.20181218.49446-1 [11.3 MB] Get: 172 http://deb.debian.org/debian buster/main amd64 xdg-utils all 1.1.3-1+deb10u1 [73.7 kB] Get: 173 http://deb.debian.org/debian buster/main amd64 texlive-base all 2018.20190227-2 [19.7 MB] Get: 174 http://deb.debian.org/debian buster/main amd64 texlive-latex-base all 2018.20190227-2 [984 kB] Get: 175 http://deb.debian.org/debian buster/main amd64 texlive-bibtex-extra all 2018.20190227-2 [61.7 MB] Get: 176 http://deb.debian.org/debian buster/main amd64 texlive-font-utils all 2018.20190227-2 [1746 kB] Get: 177 http://deb.debian.org/debian buster/main amd64 texlive-fonts-extra all 2018.20190227-2 [412 MB] Get: 178 http://deb.debian.org/debian buster/main amd64 texlive-fonts-recommended all 2018.20190227-2 [5228 kB] Get: 179 http://deb.debian.org/debian buster/main amd64 texlive-plain-generic all 2018.20190227-2 [24.3 MB] Get: 180 http://deb.debian.org/debian buster/main amd64 texlive-generic-recommended all 2018.20190227-2 [32.2 kB] Get: 181 http://deb.debian.org/debian buster/main amd64 texlive-lang-greek all 2018.20190227-2 [76.3 MB] Get: 182 http://deb.debian.org/debian buster/main amd64 texlive-latex-recommended all 2018.20190227-2 [15.2 MB] Get: 183 http://deb.debian.org/debian buster/main amd64 texlive-pictures all 2018.20190227-2 [8201 kB] Get: 184 http://deb.debian.org/debian buster/main amd64 texlive-latex-extra all 2018.20190227-2 [12.3 MB] Get: 185 http://deb.debian.org/debian buster/main amd64 texlive-publishers all 2018.20190227-2 [13.2 MB] Get: 186 http://deb.debian.org/debian buster/main amd64 texlive-science all 2018.20190227-2 [3168 kB] Get: 187 http://deb.debian.org/debian buster/main amd64 txt2man all 1.6.0-5 [29.7 kB] Fetched 748 MB in 14s (52.3 MB/s) debconf: delaying package configuration, since apt-utils is not installed Selecting previously unselected package libbsd0:amd64. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 19195 files and directories currently installed.) Preparing to unpack .../00-libbsd0_0.9.1-2+deb10u1_amd64.deb ... Unpacking libbsd0:amd64 (0.9.1-2+deb10u1) ... Selecting previously unselected package bsdmainutils. Preparing to unpack .../01-bsdmainutils_11.1.2+b1_amd64.deb ... Unpacking bsdmainutils (11.1.2+b1) ... Selecting previously unselected package libuchardet0:amd64. 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Selecting previously unselected package python2-minimal. Preparing to unpack .../08-python2-minimal_2.7.16-1_amd64.deb ... Unpacking python2-minimal (2.7.16-1) ... Selecting previously unselected package python-minimal. Preparing to unpack .../09-python-minimal_2.7.16-1_amd64.deb ... Unpacking python-minimal (2.7.16-1) ... Selecting previously unselected package libssl1.1:amd64. Preparing to unpack .../10-libssl1.1_1.1.1d-0+deb10u7_amd64.deb ... Unpacking libssl1.1:amd64 (1.1.1d-0+deb10u7) ... Selecting previously unselected package mime-support. Preparing to unpack .../11-mime-support_3.62_all.deb ... Unpacking mime-support (3.62) ... Selecting previously unselected package libexpat1:amd64. Preparing to unpack .../12-libexpat1_2.2.6-2+deb10u1_amd64.deb ... Unpacking libexpat1:amd64 (2.2.6-2+deb10u1) ... Selecting previously unselected package readline-common. Preparing to unpack .../13-readline-common_7.0-5_all.deb ... Unpacking readline-common (7.0-5) ... Selecting previously unselected package libreadline7:amd64. Preparing to unpack .../14-libreadline7_7.0-5_amd64.deb ... Unpacking libreadline7:amd64 (7.0-5) ... Selecting previously unselected package libpython2.7-stdlib:amd64. Preparing to unpack .../15-libpython2.7-stdlib_2.7.16-2+deb10u1_amd64.deb ... Unpacking libpython2.7-stdlib:amd64 (2.7.16-2+deb10u1) ... Selecting previously unselected package python2.7. Preparing to unpack .../16-python2.7_2.7.16-2+deb10u1_amd64.deb ... Unpacking python2.7 (2.7.16-2+deb10u1) ... Selecting previously unselected package libpython2-stdlib:amd64. Preparing to unpack .../17-libpython2-stdlib_2.7.16-1_amd64.deb ... Unpacking libpython2-stdlib:amd64 (2.7.16-1) ... Selecting previously unselected package libpython-stdlib:amd64. Preparing to unpack .../18-libpython-stdlib_2.7.16-1_amd64.deb ... Unpacking libpython-stdlib:amd64 (2.7.16-1) ... Setting up libpython2.7-minimal:amd64 (2.7.16-2+deb10u1) ... Setting up python2.7-minimal (2.7.16-2+deb10u1) ... Setting up python2-minimal (2.7.16-1) ... Selecting previously unselected package python2. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 20658 files and directories currently installed.) Preparing to unpack .../python2_2.7.16-1_amd64.deb ... Unpacking python2 (2.7.16-1) ... Setting up python-minimal (2.7.16-1) ... Selecting previously unselected package python. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 20691 files and directories currently installed.) Preparing to unpack .../python_2.7.16-1_amd64.deb ... Unpacking python (2.7.16-1) ... Selecting previously unselected package libsigsegv2:amd64. Preparing to unpack .../libsigsegv2_2.12-2_amd64.deb ... Unpacking libsigsegv2:amd64 (2.12-2) ... Selecting previously unselected package m4. Preparing to unpack .../archives/m4_1.4.18-2_amd64.deb ... Unpacking m4 (1.4.18-2) ... Selecting previously unselected package flex. Preparing to unpack .../flex_2.6.4-6.2_amd64.deb ... Unpacking flex (2.6.4-6.2) ... Setting up readline-common (7.0-5) ... Setting up libreadline7:amd64 (7.0-5) ... Setting up libsigsegv2:amd64 (2.12-2) ... Selecting previously unselected package gawk. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 20872 files and directories currently installed.) Preparing to unpack .../gawk_1%3a4.2.1+dfsg-1_amd64.deb ... Unpacking gawk (1:4.2.1+dfsg-1) ... Selecting previously unselected package poppler-data. Preparing to unpack .../poppler-data_0.4.9-2_all.deb ... Unpacking poppler-data (0.4.9-2) ... Selecting previously unselected package libpython3.7-minimal:amd64. Preparing to unpack .../libpython3.7-minimal_3.7.3-2+deb10u3_amd64.deb ... Unpacking libpython3.7-minimal:amd64 (3.7.3-2+deb10u3) ... Selecting previously unselected package python3.7-minimal. Preparing to unpack .../python3.7-minimal_3.7.3-2+deb10u3_amd64.deb ... Unpacking python3.7-minimal (3.7.3-2+deb10u3) ... Setting up libssl1.1:amd64 (1.1.1d-0+deb10u7) ... Setting up libpython3.7-minimal:amd64 (3.7.3-2+deb10u3) ... Setting up libexpat1:amd64 (2.2.6-2+deb10u1) ... Setting up python3.7-minimal (3.7.3-2+deb10u3) ... Selecting previously unselected package python3-minimal. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 21799 files and directories currently installed.) Preparing to unpack .../python3-minimal_3.7.3-1_amd64.deb ... Unpacking python3-minimal (3.7.3-1) ... Selecting previously unselected package libmpdec2:amd64. Preparing to unpack .../libmpdec2_2.4.2-2_amd64.deb ... Unpacking libmpdec2:amd64 (2.4.2-2) ... Selecting previously unselected package libpython3.7-stdlib:amd64. Preparing to unpack .../libpython3.7-stdlib_3.7.3-2+deb10u3_amd64.deb ... Unpacking libpython3.7-stdlib:amd64 (3.7.3-2+deb10u3) ... Selecting previously unselected package python3.7. Preparing to unpack .../python3.7_3.7.3-2+deb10u3_amd64.deb ... Unpacking python3.7 (3.7.3-2+deb10u3) ... Selecting previously unselected package libpython3-stdlib:amd64. Preparing to unpack .../libpython3-stdlib_3.7.3-1_amd64.deb ... Unpacking libpython3-stdlib:amd64 (3.7.3-1) ... Setting up python3-minimal (3.7.3-1) ... Selecting previously unselected package python3. (Reading database ... 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Moving old data out of the way Unpacking ucf (3.0038+nmu1) ... Selecting previously unselected package tex-common. Preparing to unpack .../003-tex-common_6.11_all.deb ... Unpacking tex-common (6.11) ... Selecting previously unselected package libmagic-mgc. Preparing to unpack .../004-libmagic-mgc_1%3a5.35-4+deb10u2_amd64.deb ... Unpacking libmagic-mgc (1:5.35-4+deb10u2) ... Selecting previously unselected package libmagic1:amd64. Preparing to unpack .../005-libmagic1_1%3a5.35-4+deb10u2_amd64.deb ... Unpacking libmagic1:amd64 (1:5.35-4+deb10u2) ... Selecting previously unselected package file. Preparing to unpack .../006-file_1%3a5.35-4+deb10u2_amd64.deb ... Unpacking file (1:5.35-4+deb10u2) ... Selecting previously unselected package gettext-base. Preparing to unpack .../007-gettext-base_0.19.8.1-9_amd64.deb ... Unpacking gettext-base (0.19.8.1-9) ... Selecting previously unselected package autoconf. Preparing to unpack .../008-autoconf_2.69-11_all.deb ... Unpacking autoconf (2.69-11) ... Selecting previously unselected package autotools-dev. Preparing to unpack .../009-autotools-dev_20180224.1_all.deb ... Unpacking autotools-dev (20180224.1) ... Selecting previously unselected package automake. Preparing to unpack .../010-automake_1%3a1.16.1-4_all.deb ... Unpacking automake (1:1.16.1-4) ... Selecting previously unselected package autopoint. Preparing to unpack .../011-autopoint_0.19.8.1-9_all.deb ... Unpacking autopoint (0.19.8.1-9) ... Selecting previously unselected package berkeley-abc. Preparing to unpack .../012-berkeley-abc_1.01+20181130git163bba5+dfsg-1_amd64.deb ... Unpacking berkeley-abc (1.01+20181130git163bba5+dfsg-1) ... Selecting previously unselected package libbison-dev:amd64. Preparing to unpack .../013-libbison-dev_2%3a3.3.2.dfsg-1_amd64.deb ... Unpacking libbison-dev:amd64 (2:3.3.2.dfsg-1) ... Selecting previously unselected package bison. Preparing to unpack .../014-bison_2%3a3.3.2.dfsg-1_amd64.deb ... Unpacking bison (2:3.3.2.dfsg-1) ... Selecting previously unselected package libtool. Preparing to unpack .../015-libtool_2.4.6-9_all.deb ... Unpacking libtool (2.4.6-9) ... Selecting previously unselected package dh-autoreconf. Preparing to unpack .../016-dh-autoreconf_19_all.deb ... Unpacking dh-autoreconf (19) ... Selecting previously unselected package libarchive-zip-perl. Preparing to unpack .../017-libarchive-zip-perl_1.64-1_all.deb ... Unpacking libarchive-zip-perl (1.64-1) ... Selecting previously unselected package libfile-stripnondeterminism-perl. Preparing to unpack .../018-libfile-stripnondeterminism-perl_1.1.2-1_all.deb ... Unpacking libfile-stripnondeterminism-perl (1.1.2-1) ... Selecting previously unselected package dh-strip-nondeterminism. Preparing to unpack .../019-dh-strip-nondeterminism_1.1.2-1_all.deb ... Unpacking dh-strip-nondeterminism (1.1.2-1) ... Selecting previously unselected package libelf1:amd64. Preparing to unpack .../020-libelf1_0.176-1.1_amd64.deb ... Unpacking libelf1:amd64 (0.176-1.1) ... Selecting previously unselected package dwz. Preparing to unpack .../021-dwz_0.12-3_amd64.deb ... Unpacking dwz (0.12-3) ... Selecting previously unselected package libglib2.0-0:amd64. Preparing to unpack .../022-libglib2.0-0_2.58.3-2+deb10u3_amd64.deb ... Unpacking libglib2.0-0:amd64 (2.58.3-2+deb10u3) ... Selecting previously unselected package libicu63:amd64. Preparing to unpack .../023-libicu63_63.1-6+deb10u1_amd64.deb ... Unpacking libicu63:amd64 (63.1-6+deb10u1) ... Selecting previously unselected package libxml2:amd64. Preparing to unpack .../024-libxml2_2.9.4+dfsg1-7+deb10u2_amd64.deb ... Unpacking libxml2:amd64 (2.9.4+dfsg1-7+deb10u2) ... Selecting previously unselected package libcroco3:amd64. Preparing to unpack .../025-libcroco3_0.6.12-3_amd64.deb ... Unpacking libcroco3:amd64 (0.6.12-3) ... Selecting previously unselected package libncurses6:amd64. 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I: Building the package I: Running cd /build/yosys-0.8/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-genchanges -S > ../yosys_0.8-1_source.changes dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.8-1 dpkg-buildpackage: info: source distribution unstable dpkg-buildpackage: info: source changed by Ruben Undheim dpkg-source --before-build . dpkg-buildpackage: info: host architecture amd64 fakeroot debian/rules clean PREFIX=/usr dh clean --with=python3 debian/rules override_dh_auto_clean make[1]: Entering directory '/build/yosys-0.8' dh_auto_clean make -j15 clean make[2]: Entering directory '/build/yosys-0.8' rm -rf share if test -d manual; then cd manual && sh clean.sh; fi find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f rm -f kernel/version_5706e90.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/verific/verific.o frontends/json/jsonparse.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/liberty/liberty.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o backends/firrtl/firrtl.o backends/simplec/simplec.o backends/edif/edif.o backends/aiger/aiger.o backends/smt2/smt2.o backends/table/table.o backends/btor/btor.o backends/intersynth/intersynth.o backends/ilang/ilang_backend.o backends/json/json.o backends/verilog/verilog_backend.o backends/smv/smv.o backends/blif/blif.o backends/spice/spice.o techlibs/easic/synth_easic.o techlibs/xilinx/synth_xilinx.o techlibs/gowin/synth_gowin.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/ecp5/synth_ecp5.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/achronix/synth_achronix.o techlibs/common/synth.o techlibs/common/prep.o frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh frontends/ilang/ilang_parser.output frontends/ilang/ilang_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/techmap/techmap.inc techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc yosys yosys-config yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/sha1/sha1.h share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/backends/ilang/ilang_backend.h share/python3/smtio.py share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/brams.txt share/xilinx/brams_map.v share/xilinx/brams_bb.v share/xilinx/drams.txt share/xilinx/drams_map.v share/xilinx/arith_map.v share/xilinx/lut2lut.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams.txt share/intel/common/brams_map.v share/intel/max10/cells_sim.v share/intel/a10gx/cells_sim.v share/intel/cyclonev/cells_sim.v share/intel/cyclone10/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/a10gx/cells_map.v share/intel/cyclonev/cells_map.v share/intel/cyclone10/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/drams_map.v share/ecp5/dram.txt share/ecp5/arith_map.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/cells.lib passes/techmap/filterlib.o techlibs/xilinx/brams_init.mk techlibs/ice40/brams_init.mk rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/tools/cmp_tbdata make[2]: Leaving directory '/build/yosys-0.8' rm -f debian/man/*.1 rm -f Makefile.conf make[1]: Leaving directory '/build/yosys-0.8' dh_clean debian/rules build PREFIX=/usr dh build --with=python3 dh_update_autotools_config dh_autoreconf debian/rules override_dh_auto_configure make[1]: Entering directory '/build/yosys-0.8' make config-gcc make[2]: Entering directory '/build/yosys-0.8' rm -rf share if test -d manual; then cd manual && sh clean.sh; fi find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f rm -f kernel/version_5706e90.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/verific/verific.o frontends/json/jsonparse.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/liberty/liberty.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o backends/firrtl/firrtl.o backends/simplec/simplec.o backends/edif/edif.o backends/aiger/aiger.o backends/smt2/smt2.o backends/table/table.o backends/btor/btor.o backends/intersynth/intersynth.o backends/ilang/ilang_backend.o backends/json/json.o backends/verilog/verilog_backend.o backends/smv/smv.o backends/blif/blif.o backends/spice/spice.o techlibs/easic/synth_easic.o techlibs/xilinx/synth_xilinx.o techlibs/gowin/synth_gowin.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/ecp5/synth_ecp5.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/achronix/synth_achronix.o techlibs/common/synth.o techlibs/common/prep.o frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh frontends/ilang/ilang_parser.output frontends/ilang/ilang_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/techmap/techmap.inc techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc yosys yosys-config yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/sha1/sha1.h share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/backends/ilang/ilang_backend.h share/python3/smtio.py share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/brams.txt share/xilinx/brams_map.v share/xilinx/brams_bb.v share/xilinx/drams.txt share/xilinx/drams_map.v share/xilinx/arith_map.v share/xilinx/lut2lut.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams.txt share/intel/common/brams_map.v share/intel/max10/cells_sim.v share/intel/a10gx/cells_sim.v share/intel/cyclonev/cells_sim.v share/intel/cyclone10/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/a10gx/cells_map.v share/intel/cyclonev/cells_map.v share/intel/cyclone10/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/drams_map.v share/ecp5/dram.txt share/ecp5/arith_map.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/cells.lib passes/techmap/filterlib.o techlibs/xilinx/brams_init.mk techlibs/ice40/brams_init.mk rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/tools/cmp_tbdata echo 'CONFIG := gcc' > Makefile.conf make[2]: Leaving directory '/build/yosys-0.8' make[1]: Leaving directory '/build/yosys-0.8' debian/rules override_dh_auto_build-arch make[1]: Entering directory '/build/yosys-0.8' dh_auto_build --parallel -- all make -j15 "INSTALL=install --strip-program=true" all make[2]: Entering directory '/build/yosys-0.8' [Makefile.conf] CONFIG := gcc rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc mkdir -p kernel/ mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.8 (git sha1 5706e90)\"; }" > kernel/version_5706e90.cc gcc -o kernel/driver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new mkdir -p kernel/ gcc -o kernel/rtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc mkdir -p kernel/ mkdir -p kernel/ gcc -o kernel/log.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc gcc -o kernel/calc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc mkdir -p kernel/ gcc -o kernel/yosys.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_DATDIR='"/usr/share/yosys"' kernel/yosys.cc mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc mkdir -p kernel/ gcc -o kernel/cellaigs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc mkdir -p kernel/ gcc -o kernel/celledges.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc mkdir -p libs/bigint/ mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc gcc -o libs/bigint/BigIntegerAlgorithms.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigInteger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerUtils.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsigned.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsignedInABase.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc mkdir -p libs/sha1/ mkdir -p libs/subcircuit/ gcc -o libs/sha1/sha1.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp gcc -o libs/subcircuit/subcircuit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezminisat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Options.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc mkdir -p libs/minisat/ gcc -o libs/minisat/SimpSolver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Solver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc mkdir -p libs/minisat/ gcc -o libs/minisat/System.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc mkdir -p frontends/ilang/ bison -o frontends/ilang/ilang_parser.tab.cc -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y frontends/ilang/ilang_parser.y:46.1-38: warning: deprecated directive, use '%define api.prefix {rtlil_frontend_ilang_yy}' [-Wdeprecated] %name-prefix "rtlil_frontend_ilang_yy" ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]': libs/minisat/Vec.h:119:5: required from 'void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]' libs/minisat/IntMap.h:48:48: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SolverTypes.h:338:37: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SimpSolver.cc:92:28: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here class vec { ^~~ mkdir -p frontends/ilang/ flex -o frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_lexer.l mkdir -p frontends/ilang/ gcc -o frontends/ilang/ilang_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_frontend.cc frontends/ilang/ilang_parser.y: warning: fix-its can be applied. Rerun with option '--update'. [-Wother] mkdir -p frontends/verific/ gcc -o frontends/verific/verific.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]': libs/minisat/Vec.h:119:5: required from 'void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]' libs/minisat/IntMap.h:48:48: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' libs/minisat/SolverTypes.h:338:37: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' libs/minisat/Solver.cc:134:35: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here class vec { ^~~ mkdir -p frontends/json/ gcc -o frontends/json/jsonparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc mkdir -p frontends/verilog/ bison -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y frontends/verilog/verilog_parser.y:95.1-34: warning: deprecated directive, use '%define api.prefix {frontend_verilog_yy}' [-Wdeprecated] %name-prefix "frontend_verilog_yy" ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ mkdir -p frontends/verilog/ flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l mkdir -p frontends/verilog/ gcc -o frontends/verilog/preproc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc frontends/verilog/verilog_parser.y: warning: fix-its can be applied. Rerun with option '--update'. [-Wother] mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc frontends/verific/verific.cc:1679:6: warning: 'bool {anonymous}::check_noverific_env()' defined but not used [-Wunused-function] bool check_noverific_env() ^~~~~~~~~~~~~~~~~~~ mkdir -p frontends/verilog/ mkdir -p frontends/ast/ gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc gcc -o frontends/ast/ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc mkdir -p frontends/ast/ gcc -o frontends/ast/simplify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc mkdir -p frontends/ast/ gcc -o frontends/ast/genrtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc mkdir -p frontends/ast/ gcc -o frontends/ast/dpicall.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc mkdir -p frontends/blif/ gcc -o frontends/blif/blifparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc mkdir -p frontends/liberty/ gcc -o frontends/liberty/liberty.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc mkdir -p passes/tests/ gcc -o passes/tests/test_autotb.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc mkdir -p passes/tests/ gcc -o passes/tests/test_cell.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc mkdir -p passes/tests/ gcc -o passes/tests/test_abcloop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc mkdir -p passes/sat/ gcc -o passes/sat/sat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc mkdir -p passes/sat/ gcc -o passes/sat/freduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc mkdir -p passes/sat/ gcc -o passes/sat/eval.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc mkdir -p passes/sat/ gcc -o passes/sat/sim.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc mkdir -p passes/sat/ gcc -o passes/sat/miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc mkdir -p passes/sat/ gcc -o passes/sat/expose.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc mkdir -p passes/sat/ gcc -o passes/sat/assertpmux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc mkdir -p passes/sat/ gcc -o passes/sat/clk2fflogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc mkdir -p passes/sat/ gcc -o passes/sat/async2sync.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc mkdir -p passes/opt/ gcc -o passes/opt/opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_merge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_muxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_rmdff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_rmdff.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_expr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc mkdir -p passes/opt/ gcc -o passes/opt/share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc mkdir -p passes/opt/ gcc -o passes/opt/wreduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_demorgan.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc mkdir -p passes/opt/ gcc -o passes/opt/rmports.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc mkdir -p passes/memory/ gcc -o passes/memory/memory.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_collect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_unpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_bram.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_memx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_nordff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc mkdir -p passes/techmap/ echo "// autogenerated from techlibs/common/techmap.v" > passes/techmap/techmap.inc.new echo "static char stdcells_code[] = {" >> passes/techmap/techmap.inc.new od -v -td1 -An techlibs/common/techmap.v | sed -e 's/[0-9][0-9]*/&,/g' >> passes/techmap/techmap.inc.new echo "0};" >> passes/techmap/techmap.inc.new mv passes/techmap/techmap.inc.new passes/techmap/techmap.inc mkdir -p passes/techmap/ gcc -o passes/techmap/simplemap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflibmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/maccmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/libparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/iopadmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/hilomap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_fa.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_counter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc mkdir -p passes/techmap/ gcc -o passes/techmap/alumacc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dff2dffe.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dff2dffe.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc mkdir -p passes/techmap/ gcc -o passes/techmap/muxcover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc mkdir -p passes/techmap/ gcc -o passes/techmap/aigmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/tribuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/lut2mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc mkdir -p passes/techmap/ gcc -o passes/techmap/nlutmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffsr2dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffsr2dff.cc mkdir -p passes/techmap/ gcc -o passes/techmap/shregmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/deminout.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc mkdir -p passes/techmap/ gcc -o passes/techmap/insbuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmvcp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/zinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dff2dffs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dff2dffs.cc mkdir -p passes/cmds/ gcc -o passes/cmds/add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc mkdir -p passes/cmds/ gcc -o passes/cmds/delete.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc mkdir -p passes/cmds/ gcc -o passes/cmds/design.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc mkdir -p passes/cmds/ gcc -o passes/cmds/select.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc mkdir -p passes/cmds/ gcc -o passes/cmds/show.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc mkdir -p passes/cmds/ gcc -o passes/cmds/rename.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scatter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setundef.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splitnets.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc mkdir -p passes/cmds/ gcc -o passes/cmds/stat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setattr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc mkdir -p passes/cmds/ gcc -o passes/cmds/copy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc mkdir -p passes/cmds/ gcc -o passes/cmds/torder.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logcmd.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc mkdir -p passes/cmds/ gcc -o passes/cmds/tee.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc mkdir -p passes/cmds/ gcc -o passes/cmds/write_file.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connwrappers.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc mkdir -p passes/cmds/ gcc -o passes/cmds/cover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc mkdir -p passes/cmds/ gcc -o passes/cmds/trace.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc mkdir -p passes/cmds/ gcc -o passes/cmds/plugin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc mkdir -p passes/cmds/ gcc -o passes/cmds/check.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc mkdir -p passes/cmds/ gcc -o passes/cmds/qwp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/qwp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/edgetypes.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chformal.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chtype.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc mkdir -p passes/cmds/ gcc -o passes/cmds/blackbox.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc mkdir -p passes/cmds/ gcc -o passes/cmds/ltp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/hierarchy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/uniquify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/submod.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_make.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_simple.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_status.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_remove.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_induct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_struct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_purge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_mark.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_detect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_expand.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_recode.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_info.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_export.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc mkdir -p passes/proc/ gcc -o passes/proc/proc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_rmdead.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_arst.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dlatch.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc mkdir -p backends/firrtl/ gcc -o backends/firrtl/firrtl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc mkdir -p backends/simplec/ gcc -o backends/simplec/simplec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc mkdir -p backends/edif/ gcc -o backends/edif/edif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc mkdir -p backends/aiger/ gcc -o backends/aiger/aiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc backends/firrtl/firrtl.cc: In member function 'void {anonymous}::FirrtlWorker::process_instance(Yosys::RTLIL::Cell*, std::vector >&)': backends/firrtl/firrtl.cc:197:18: warning: this statement may fall through [-Wimplicit-fallthrough=] log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second)); ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ backends/firrtl/firrtl.cc:198:6: note: here case FD_OUT: ^~~~ backends/firrtl/firrtl.cc:203:18: warning: this statement may fall through [-Wimplicit-fallthrough=] log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second)); ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ backends/firrtl/firrtl.cc:205:6: note: here case FD_IN: ^~~~ mkdir -p backends/smt2/ gcc -o backends/smt2/smt2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc mkdir -p backends/table/ gcc -o backends/table/table.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc mkdir -p backends/btor/ gcc -o backends/btor/btor.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc mkdir -p backends/intersynth/ gcc -o backends/intersynth/intersynth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc mkdir -p backends/ilang/ gcc -o backends/ilang/ilang_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/ilang/ilang_backend.cc mkdir -p backends/json/ gcc -o backends/json/json.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc mkdir -p backends/verilog/ gcc -o backends/verilog/verilog_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc mkdir -p backends/smv/ gcc -o backends/smv/smv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc mkdir -p backends/blif/ gcc -o backends/blif/blif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc mkdir -p backends/spice/ gcc -o backends/spice/spice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc mkdir -p techlibs/easic/ gcc -o techlibs/easic/synth_easic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/synth_xilinx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc mkdir -p techlibs/gowin/ gcc -o techlibs/gowin/synth_gowin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/synth_ice40.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_ffssr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_ffssr.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_ffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_ffinit.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc mkdir -p techlibs/intel/ gcc -o techlibs/intel/synth_intel.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/synth_ecp5.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/synth_coolrunner2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_sop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/synth_greenpak4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/greenpak4_dffinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc mkdir -p techlibs/achronix/ gcc -o techlibs/achronix/synth_achronix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc mkdir -p techlibs/common/ gcc -o techlibs/common/synth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc mkdir -p techlibs/common/ gcc -o techlibs/common/prep.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc sed -e 's#@CXXFLAGS@#-g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \ -e 's#@CXX@#gcc#;' -e 's#@LDFLAGS@#-Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic#;' -e 's#@LDLIBS@#-lstdc++ -lm -lrt -lreadline -lffi -ldl -ltcl8.6 -ltclstub8.6#;' \ -e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config chmod +x yosys-config mkdir -p passes/techmap/ gcc -o passes/techmap/filterlib.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc sed 's|##yosys-sys-path##|sys.path += ["/usr/share/yosys"]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new chmod +x yosys-smtbmc.new mv yosys-smtbmc.new yosys-smtbmc mkdir -p share/include/kernel/ cp "./"/kernel/yosys.h share/include/kernel/yosys.h mkdir -p share/include/kernel/ cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h mkdir -p share/include/kernel/ cp "./"/kernel/log.h share/include/kernel/log.h mkdir -p share/include/kernel/ cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h mkdir -p share/include/kernel/ cp "./"/kernel/register.h share/include/kernel/register.h mkdir -p share/include/kernel/ cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h mkdir -p share/include/kernel/ cp "./"/kernel/celledges.h share/include/kernel/celledges.h mkdir -p share/include/kernel/ cp "./"/kernel/consteval.h share/include/kernel/consteval.h mkdir -p share/include/kernel/ cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h mkdir -p share/include/kernel/ cp "./"/kernel/modtools.h share/include/kernel/modtools.h mkdir -p share/include/kernel/ cp "./"/kernel/macc.h share/include/kernel/macc.h mkdir -p share/include/kernel/ cp "./"/kernel/utils.h share/include/kernel/utils.h mkdir -p share/include/kernel/ cp "./"/kernel/satgen.h share/include/kernel/satgen.h mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h mkdir -p share/include/libs/sha1/ cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h mkdir -p share/include/passes/fsm/ cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h mkdir -p share/include/backends/ilang/ cp "./"/backends/ilang/ilang_backend.h share/include/backends/ilang/ilang_backend.h mkdir -p share/python3 cp "./"/backends/smt2/smtio.py share/python3/smtio.py mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v cp "./"/techlibs/xilinx/brams.txt share/xilinx/brams.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_map.v share/xilinx/brams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_bb.v share/xilinx/brams_bb.v cp "./"/techlibs/xilinx/drams.txt share/xilinx/drams.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/drams_map.v share/xilinx/drams_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/lut2lut.v share/xilinx/lut2lut.v mkdir -p techlibs/xilinx python3 techlibs/xilinx/brams_init.py mkdir -p share/gowin cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v mkdir -p share/ice40 cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v touch techlibs/xilinx/brams_init.mk mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v mkdir -p share/ice40 cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt mkdir -p share/ice40 cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v mkdir -p techlibs/ice40 python3 techlibs/ice40/brams_init.py mkdir -p share/intel/common cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams.txt share/intel/common/brams.txt mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_map.v share/intel/common/brams_map.v mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v mkdir -p share/intel/a10gx cp "./"/techlibs/intel/a10gx/cells_sim.v share/intel/a10gx/cells_sim.v mkdir -p share/intel/cyclonev cp "./"/techlibs/intel/cyclonev/cells_sim.v share/intel/cyclonev/cells_sim.v touch techlibs/ice40/brams_init.mk mkdir -p share/intel/cyclone10 cp "./"/techlibs/intel/cyclone10/cells_sim.v share/intel/cyclone10/cells_sim.v mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v mkdir -p share/intel/a10gx cp "./"/techlibs/intel/a10gx/cells_map.v share/intel/a10gx/cells_map.v mkdir -p share/intel/cyclonev cp "./"/techlibs/intel/cyclonev/cells_map.v share/intel/cyclonev/cells_map.v mkdir -p share/intel/cyclone10 cp "./"/techlibs/intel/cyclone10/cells_map.v share/intel/cyclone10/cells_map.v mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/drams_map.v share/ecp5/drams_map.v cp "./"/techlibs/ecp5/dram.txt share/ecp5/dram.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v mkdir -p share/greenpak4 mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib mkdir -p share/achronix/speedster22i/ mkdir -p share/achronix/speedster22i/ cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v mkdir -p share cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v cp "./"/techlibs/common/simlib.v share/simlib.v mkdir -p share mkdir -p share cp "./"/techlibs/common/simcells.v share/simcells.v mkdir -p share cp "./"/techlibs/common/techmap.v share/techmap.v cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v mkdir -p share cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share mkdir -p share cp "./"/techlibs/common/dff2ff.v share/dff2ff.v cp "./"/techlibs/common/cells.lib share/cells.lib mkdir -p kernel/ gcc -o kernel/version_5706e90.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_5706e90.cc mkdir -p kernel/ gcc -o kernel/register.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc mkdir -p frontends/ilang/ gcc -o frontends/ilang/ilang_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_parser.tab.cc mkdir -p frontends/ilang/ gcc -o frontends/ilang/ilang_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_lexer.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_parser.tab.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc mkdir -p passes/techmap/ gcc -o passes/techmap/techmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.8=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc mkdir -p share/xilinx cp techlibs/xilinx/brams_init_36.vh share/xilinx/brams_init_36.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_32.vh share/xilinx/brams_init_32.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_18.vh share/xilinx/brams_init_18.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_16.vh share/xilinx/brams_init_16.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init1.vh share/ice40/brams_init1.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init2.vh share/ice40/brams_init2.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init3.vh share/ice40/brams_init3.vh mkdir -p ./ gcc -o yosys-filterlib -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -ltcl8.6 -ltclstub8.6 gcc -o yosys -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic kernel/version_5706e90.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/verific/verific.o frontends/json/jsonparse.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/liberty/liberty.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o backends/firrtl/firrtl.o backends/simplec/simplec.o backends/edif/edif.o backends/aiger/aiger.o backends/smt2/smt2.o backends/table/table.o backends/btor/btor.o backends/intersynth/intersynth.o backends/ilang/ilang_backend.o backends/json/json.o backends/verilog/verilog_backend.o backends/smv/smv.o backends/blif/blif.o backends/spice/spice.o techlibs/easic/synth_easic.o techlibs/xilinx/synth_xilinx.o techlibs/gowin/synth_gowin.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/ecp5/synth_ecp5.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/achronix/synth_achronix.o techlibs/common/synth.o techlibs/common/prep.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -ltcl8.6 -ltclstub8.6 Build successful. make[2]: Leaving directory '/build/yosys-0.8' make[1]: Leaving directory '/build/yosys-0.8' debian/rules override_dh_auto_build-indep make[1]: Entering directory '/build/yosys-0.8' sed -i 's/REPLACEWITHDATE/October 17, 2018/' manual/presentation.tex PDF_DATE=D:20181017163613Z dh_auto_build --parallel -- all manual make -j15 "INSTALL=install --strip-program=true" all manual make[2]: Entering directory '/build/yosys-0.8' [Makefile.conf] CONFIG := gcc cd manual && PDF_DATE=D:20181017163613Z bash appnotes.sh + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_010_Verilog_to_BLIF.ok -a APPNOTE_010_Verilog_to_BLIF.ok -nt APPNOTE_010_Verilog_to_BLIF.tex ']' + '[' -f APPNOTE_010_Verilog_to_BLIF/make.sh ']' Build successful. ++ '[' -f APPNOTE_010_Verilog_to_BLIF.aux ']' ++ true + old_md5= + pdflatex -shell-escape -halt-on-error '\pdfinfo{/CreationDate(D:20181017163613Z)/ModDate(D:20181017163613Z)}\input{APPNOTE_010_Verilog_to_BLIF.tex}' This is pdfTeX, Version 3.14159265-2.6-1.40.19 (TeX Live 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Transcript written on APPNOTE_010_Verilog_to_BLIF.log. ++ md5sum + new_md5='e4f58725f25bb1063228898ab18828de -' + '[' 'e4f58725f25bb1063228898ab18828de -' '!=' 'e4f58725f25bb1063228898ab18828de -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_010_Verilog_to_BLIF.pdf + mv -f APPNOTE_010_Verilog_to_BLIF.pdf.without_pdf_id APPNOTE_010_Verilog_to_BLIF.pdf + touch APPNOTE_010_Verilog_to_BLIF.ok + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_011_Design_Investigation.ok -a APPNOTE_011_Design_Investigation.ok -nt APPNOTE_011_Design_Investigation.tex ']' + '[' -f APPNOTE_011_Design_Investigation/make.sh ']' + cd APPNOTE_011_Design_Investigation + bash make.sh + false + for dot_file in *.dot + pdf_file=cmos_00.pdf + dot -Tpdf -o cmos_00.pdf cmos_00.dot + for dot_file in *.dot + pdf_file=cmos_01.pdf + dot -Tpdf -o cmos_01.pdf cmos_01.dot + for dot_file in *.dot + pdf_file=example_00.pdf + dot -Tpdf -o example_00.pdf example_00.dot + for dot_file in *.dot + pdf_file=example_01.pdf + dot -Tpdf -o example_01.pdf example_01.dot + for dot_file in *.dot + pdf_file=example_02.pdf + dot -Tpdf -o example_02.pdf example_02.dot + for dot_file in *.dot + pdf_file=example_03.pdf + dot -Tpdf -o example_03.pdf example_03.dot + for dot_file in *.dot + pdf_file=memdemo_00.pdf + dot -Tpdf -o memdemo_00.pdf memdemo_00.dot + for dot_file in *.dot + pdf_file=memdemo_01.pdf + dot -Tpdf -o memdemo_01.pdf memdemo_01.dot + for dot_file in *.dot + pdf_file=splice.pdf + dot -Tpdf -o splice.pdf splice.dot + for dot_file in *.dot + pdf_file=submod_00.pdf + dot -Tpdf -o submod_00.pdf submod_00.dot + for dot_file in *.dot + pdf_file=submod_01.pdf + dot -Tpdf -o submod_01.pdf submod_01.dot + for dot_file in *.dot + pdf_file=submod_02.pdf + dot -Tpdf -o submod_02.pdf submod_02.dot + for dot_file in *.dot + pdf_file=submod_03.pdf + dot -Tpdf -o submod_03.pdf submod_03.dot + for dot_file in *.dot + pdf_file=sumprod_00.pdf + dot -Tpdf -o sumprod_00.pdf sumprod_00.dot + for dot_file in *.dot + pdf_file=sumprod_01.pdf + dot -Tpdf -o sumprod_01.pdf sumprod_01.dot + for dot_file in *.dot + pdf_file=sumprod_02.pdf + dot -Tpdf -o sumprod_02.pdf sumprod_02.dot + for dot_file in *.dot + pdf_file=sumprod_03.pdf + dot -Tpdf -o sumprod_03.pdf sumprod_03.dot + for dot_file in *.dot + pdf_file=sumprod_04.pdf + dot -Tpdf -o sumprod_04.pdf sumprod_04.dot + for dot_file in *.dot + pdf_file=sumprod_05.pdf + dot -Tpdf -o sumprod_05.pdf sumprod_05.dot + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20181017163613Z)#' cmos_00.pdf cmos_01.pdf example_00.pdf example_01.pdf example_02.pdf example_03.pdf memdemo_00.pdf memdemo_01.pdf splice.pdf submod_00.pdf submod_01.pdf submod_02.pdf submod_03.pdf sumprod_00.pdf sumprod_01.pdf sumprod_02.pdf sumprod_03.pdf sumprod_04.pdf sumprod_05.pdf + cd .. ++ '[' -f APPNOTE_011_Design_Investigation.aux ']' ++ true + old_md5= + pdflatex -shell-escape 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[6pdfTeX wa rning (ext4): destination with the same identifier (name{figure.15}) has been a lready used, duplicate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.726 pdfTeX warning (ext4): destination with the same identifier (name{figure. 16}) has been already used, duplicate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.726 <./APPNOTE_011_Design_Investigation/memdemo_00.pdf> <./APPNOTE_011_Desig n_Investigation/memdemo_01.pdf pdfTeX warning: pdflatex (file ./APPNOTE_011_Design_Investigation/memdemo_01.pd f): PDF inclusion: multiple pdfs with page group included in a single page >] (./APPNOTE_011_Design_Investigation/primetest.v) [7pdfTeX warning (ext4): de stination with the same identifier (name{figure.17}) has been already used, dup licate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.889 pdfTeX warning (ext4): destination with the same identifier (name{figure. 18}) has been already used, duplicate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.889 <./APPNOTE_011_Design_Investigation/submod_00.pdf> <./APPNOTE_011_Design _Investigation/submod_01.pdf pdfTeX warning: pdflatex (file ./APPNOTE_011_Design_Investigation/submod_01.pdf ): PDF inclusion: multiple pdfs with page group included in a single page > <./APPNOTE_011_Design_Investigation/submod_02.pdf pdfTeX warning: pdflatex (file ./APPNOTE_011_Design_Investigation/submod_02.pdf ): PDF inclusion: multiple pdfs with page group included in a single page > <./APPNOTE_011_Design_Investigation/submod_03.pdf pdfTeX warning: pdflatex (file ./APPNOTE_011_Design_Investigation/submod_03.pdf ): PDF inclusion: multiple pdfs with page group included in a single page >] Underfull \vbox (badness 10000) has occurred while \output is active Underfull \vbox (badness 10000) has occurred while \output is active [8pdfTeX w arning (ext4): destination with the same identifier (name{figure.19}) has been already used, duplicate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.988 ] (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsa.fd) (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsb.fd) [9pdfTeX warning (ex t4): destination with the same identifier (name{figure.20}) has been already us ed, duplicate ignored \AtBegShi@Output ...ipout \box \AtBeginShipoutBox \fi \fi l.1070 \end{document} ] (./APPNOTE_011_Design_Investigation.aux) ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/base/8r.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/ inconsolata/i4-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsola ta/i4-t1-0.enc} Output written on APPNOTE_011_Design_Investigation.pdf (9 pages, 323990 bytes). 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Transcript written on APPNOTE_012_Verilog_to_BTOR.log. ++ md5sum + new_md5='76d09b2b1901f48363789b3853551bed -' + '[' '76d09b2b1901f48363789b3853551bed -' '!=' '76d09b2b1901f48363789b3853551bed -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_012_Verilog_to_BTOR.pdf + mv -f APPNOTE_012_Verilog_to_BTOR.pdf.without_pdf_id APPNOTE_012_Verilog_to_BTOR.pdf + touch APPNOTE_012_Verilog_to_BTOR.ok cd manual && PDF_DATE=D:20181017163613Z bash presentation.sh + false + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux '*.snm' '*.nav' '*.toc' md5sum: '*.snm': No such file or directory md5sum: '*.nav': No such file or directory md5sum: '*.toc': No such file or directory + make -C PRESENTATION_Intro make[3]: Entering directory '/build/yosys-0.8/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys counter.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `counter.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `counter.v' to AST representation. Generating RTLIL representation for module `\counter'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \counter 2.2. Analyzing design hierarchy.. Top module: \counter Removed 0 unused modules. 3. Generating Graphviz representation of design. Writing dot description to `counter_00.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_00.dot' > 'counter_00.pdf.new' && mv 'counter_00.pdf.new' 'counter_00.pdf' 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\counter.$proc$counter.v:6$1'. 1/1: $0\count[1:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. created $dff cell `$procdff$9' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. Removing empty process `counter.$proc$counter.v:6$1'. Cleaned up 2 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$7 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. removed 3 unused temporary wires. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Finished OPT passes. (There is nothing left to do.) 6. Executing MEMORY pass. 6.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 6.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 6.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 6.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 6.5. Executing MEMORY_COLLECT pass (generating $mem cells). 6.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 7. Executing OPT pass (performing simple optimizations). 7.1. Executing OPT_EXPR pass (perform const folding). 7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$7 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.6. Executing OPT_RMDFF pass (remove dff with constant values). 7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 7.8. Executing OPT_EXPR pass (perform const folding). 7.9. Finished OPT passes. (There is nothing left to do.) 8. Executing FSM pass (extract and optimize FSM). 8.1. Executing FSM_DETECT pass (finding FSMs in design). 8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 9. Executing OPT pass (performing simple optimizations). 9.1. Executing OPT_EXPR pass (perform const folding). 9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$7 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.6. Executing OPT_RMDFF pass (remove dff with constant values). 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 9.8. Executing OPT_EXPR pass (perform const folding). 9.9. Finished OPT passes. (There is nothing left to do.) 10. Generating Graphviz representation of design. Writing dot description to `counter_01.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_01.dot' > 'counter_01.pdf.new' && mv 'counter_01.pdf.new' 'counter_01.pdf' 11. Executing TECHMAP pass (map to technology primitives). 11.1. Executing Verilog-2005 frontend. Parsing Verilog input from `' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. 11.2. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47: creating $macc model for $add ($add). creating $alu model for $macc $add. creating $alu cell for $add: $auto$alumacc.cc:474:replace_alu$54 created 1 $alu and 0 $macc cells. 11.3. Continuing TECHMAP pass. Mapping counter.$add$counter.v:10$2 using $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Mapping counter.$procmux$4 ($mux) with simplemap. Mapping counter.$procmux$7 ($mux) with simplemap. Mapping counter.$procdff$9 ($dff) with simplemap. 11.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 2 Parameter \B_WIDTH = 2 Parameter \Y_WIDTH = 2 Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. 11.5. Continuing TECHMAP pass. Mapping counter.$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:262$66 ($xor) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:263$67 ($xor) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$and$:260$65 ($and) with simplemap. 11.6. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_lcu'. Parameter \WIDTH = 2 Generating RTLIL representation for module `$paramod\_90_lcu\WIDTH=2'. 11.7. Executing PROC pass (convert processes to netlists). 11.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 11.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 11.7.3. Executing PROC_INIT pass (extract init attributes). 11.7.4. Executing PROC_ARST pass (detect async resets in processes). 11.7.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\_90_lcu\WIDTH=2.$proc$:207$78'. 1/4: $0\p[1:0] [1] 2/4: $0\g[1:0] [1] 3/4: $0\g[1:0] [0] 4/4: $0\p[1:0] [0] 11.7.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\_90_lcu\WIDTH=2.\p' from process `$paramod\_90_lcu\WIDTH=2.$proc$:207$78'. No latch inferred for signal `$paramod\_90_lcu\WIDTH=2.\g' from process `$paramod\_90_lcu\WIDTH=2.$proc$:207$78'. 11.7.7. Executing PROC_DFF pass (convert process syncs to FFs). 11.7.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\_90_lcu\WIDTH=2.$proc$:207$78'. Cleaned up 0 empty switches. 11.8. Executing OPT pass (performing simple optimizations). 11.8.1. Executing OPT_EXPR pass (perform const folding). 11.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod\_90_lcu\WIDTH=2'. Removed a total of 0 cells. 11.8.3. Executing OPT_RMDFF pass (remove dff with constant values). 11.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod\_90_lcu\WIDTH=2.. removing unused `$and' cell `$and$:222$83'. removing unused non-port wire \j. removing unused non-port wire \i. removed 7 unused temporary wires. Removed 1 unused cells and 10 unused wires. 11.8.5. Finished fast OPT passes. 11.9. Continuing TECHMAP pass. Mapping counter.$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu using $paramod\_90_lcu\WIDTH=2. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$ternary$:258$64 ($mux) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$not$:258$63 ($not) with simplemap. Mapping counter.$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.B_conv ($pos) with simplemap. Mapping counter.$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.A_conv ($pos) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$and$:212$79 ($and) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$and$:221$81 ($and) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$or$:212$80 ($or) with simplemap. Mapping counter.$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$or$:221$82 ($or) with simplemap. No more expansions possible. 12. Executing OPT pass (performing simple optimizations). 12.1. Executing OPT_EXPR pass (perform const folding). Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$87' (0) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$not$:258$63_Y [1] = 1'1'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$85' (010) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$ternary$:258$64_Y [1] = 1'0'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$69' (?0) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:262$66_Y [1] = \count [1]'. Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$86' (1) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$not$:258$63_Y [0] = 1'0'. Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$84' (100) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$ternary$:258$64_Y [0] = 1'1'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$73' (and_or_buffer) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$and$:260$65_Y [0] = \count [0]'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$88' (const_and) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$and$:212$79_Y = 1'0'. Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$90' (and_or_buffer) in module `\counter' with constant driver `$techmap$add$counter.v:10$2.$auto$alumacc.cc:491:replace_alu$56 [0] = \count [0]'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$70' (?0) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:263$67_Y [0] = $techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:262$66_Y [0]'. Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$74' (const_and) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$and$:260$65_Y [1] = 1'0'. Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$91' (and_or_buffer) in module `\counter' with constant driver `$techmap$add$counter.v:10$2.$auto$alumacc.cc:491:replace_alu$56 [1] = $techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$and$:221$81_Y'. Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$72' (0?) in module `\counter' with constant driver `$techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.$xor$:263$67_Y [2] = $techmap$techmap$add$counter.v:10$2.$auto$alumacc.cc:474:replace_alu$54.lcu.$and$:221$81_Y'. 12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.6. Executing OPT_RMDFF pass (remove dff with constant values). 12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$89'. removed 30 unused temporary wires. Removed 2 unused cells and 40 unused wires. 12.8. Executing OPT_EXPR pass (perform const folding). 12.9. Rerunning OPT passes. (Maybe there is more to do..) 12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.13. Executing OPT_RMDFF pass (remove dff with constant values). 12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 2 unused cells and 40 unused wires. 12.15. Executing OPT_EXPR pass (perform const folding). 12.16. Finished OPT passes. (There is nothing left to do.) 13. Executing SPLITNETS pass (splitting up multi-bit signals). 14. Generating Graphviz representation of design. Writing dot description to `counter_02.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_02.dot' > 'counter_02.pdf.new' && mv 'counter_02.pdf.new' 'counter_02.pdf' 15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. create mapping for $_DFF_N_ from mapping for $_DFF_P_. final dff cell mappings: DFF _DFF_N_ (.C(~C), .D( D), .Q( Q)); DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ Mapping DFF cells in module `\counter': mapped 2 $_DFF_P_ cells to \DFF cells. 16. Executing ABC pass (technology mapping using ABC). 16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. Extracted 6 gates and 12 wires to a netlist network with 4 inputs and 2 outputs. 16.1.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_Intro/mycells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Library "demo" from "/manual/PRESENTATION_Intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 16.1.2. Re-integrating ABC results. ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: internal signals: 6 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 2 Removing temp directory. Removed 0 unused cells and 10 unused wires. 17. Generating Graphviz representation of design. 17.1. Executing Verilog-2005 frontend. Parsing Verilog input from `mycells.v' to AST representation. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Successfully finished Verilog frontend. 17.2. Continuing show pass. Writing dot description to `counter_03.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_03.dot' > 'counter_03.pdf.new' && mv 'counter_03.pdf.new' 'counter_03.pdf' End of script. Logfile hash: 3a8e2bfd0d CPU: user 0.08s system 0.01s, MEM: 19.15 MB total, 10.01 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 21% 4x read_verilog (0 sec), 13% 9x opt_clean (0 sec), ... make[3]: Leaving directory '/build/yosys-0.8/manual/PRESENTATION_Intro' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20181017163613Z)#' PRESENTATION_Intro/counter_00.pdf PRESENTATION_Intro/counter_01.pdf PRESENTATION_Intro/counter_02.pdf PRESENTATION_Intro/counter_03.pdf + make -C PRESENTATION_ExSyn make[3]: Entering directory '/build/yosys-0.8/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format pdf' -- -- Executing script file `proc_01.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `proc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_01.v:2$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_01.v:2$1'. 1/1: $0\Q[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. created $adff cell `$procdff$2' with positive edge clock and positive level reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_01.v:2$1'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_01.dot' > 'proc_01.pdf.new' && mv 'proc_01.pdf.new' 'proc_01.pdf' End of script. Logfile hash: ee303b4063 CPU: user 0.00s system 0.01s, MEM: 18.00 MB total, 8.62 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 31% 1x show (0 sec), 24% 1x clean (0 sec), ... ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format pdf' -- -- Executing script file `proc_02.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `proc_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_02.v:3$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_02.v:3$1'. 1/1: $0\Q[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. Warning: Async reset value `\RV' is not constant! created $dffsr cell `$procdff$2' with positive edge clock and positive level non-const reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_02.v:3$1'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_02.dot' > 'proc_02.pdf.new' && mv 'proc_02.pdf.new' 'proc_02.pdf' Warnings: 1 unique messages, 1 total End of script. Logfile hash: 3f6df400d3 CPU: user 0.00s system 0.01s, MEM: 18.00 MB total, 8.73 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 35% 1x show (0 sec), 25% 1x clean (0 sec), ... ../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format pdf' -- -- Executing script file `proc_03.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `proc_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_03.v:3$1'. 1/1: $0\Y[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. 3.7. Executing PROC_DFF pass (convert process syncs to FFs). 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. Removing empty process `test.$proc$proc_03.v:3$1'. Cleaned up 2 empty switches. Removed 0 unused cells and 4 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_03.dot' > 'proc_03.pdf.new' && mv 'proc_03.pdf.new' 'proc_03.pdf' End of script. Logfile hash: 067274c34b CPU: user 0.00s system 0.01s, MEM: 18.00 MB total, 8.73 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 30% 1x show (0 sec), 26% 1x clean (0 sec), ... ../../yosys -p 'script opt_01.ys; show -notitle -prefix opt_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script opt_01.ys; show -notitle -prefix opt_01 -format pdf' -- -- Executing script file `opt_01.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `opt_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $ternary$opt_01.v:2$2 (pure) Analyzing evaluation results. dead port 2/2 on $mux $ternary$opt_01.v:2$1. Removed 1 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. New ctrl vector for $mux cell $ternary$opt_01.v:2$2: { } Optimizing cells in module \test. Performed a total of 1 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 2 unused temporary wires. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_RMDFF pass (remove dff with constant values). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.15. Executing OPT_EXPR pass (perform const folding). 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_01.dot' > 'opt_01.pdf.new' && mv 'opt_01.pdf.new' 'opt_01.pdf' End of script. Logfile hash: c5c67e3040 CPU: user 0.01s system 0.00s, MEM: 17.99 MB total, 8.77 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 29% 3x opt_expr (0 sec), 19% 3x opt_merge (0 sec), ... ../../yosys -p 'script opt_02.ys; show -notitle -prefix opt_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script opt_02.ys; show -notitle -prefix opt_02 -format pdf' -- -- Executing script file `opt_02.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `opt_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$eq$opt_02.v:2$1' (empty) in module `\test' with constant driver `$eq$opt_02.v:2$1_Y = 1'1'. Replacing $ne cell `$ne$opt_02.v:2$2' (empty) in module `\test' with constant driver `$ne$opt_02.v:2$2_Y = 1'0'. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 2 unused temporary wires. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). 3.9. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_02.dot' > 'opt_02.pdf.new' && mv 'opt_02.pdf.new' 'opt_02.pdf' End of script. Logfile hash: 3a67810dfe CPU: user 0.00s system 0.01s, MEM: 18.00 MB total, 8.87 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 30% 2x opt_expr (0 sec), 18% 2x opt_merge (0 sec), ... ../../yosys -p 'script opt_03.ys; show -notitle -prefix opt_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script opt_03.ys; show -notitle -prefix opt_03 -format pdf' -- -- Executing script file `opt_03.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `opt_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Cell `$add$opt_03.v:3$1' is identical to cell `$add$opt_03.v:3$2'. Redirecting output \Y: $add$opt_03.v:3$1_Y = $add$opt_03.v:3$2_Y Removing $add cell `$add$opt_03.v:3$1' from module `\test'. Removed a total of 1 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 2 unused temporary wires. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). 3.9. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_03.dot' > 'opt_03.pdf.new' && mv 'opt_03.pdf.new' 'opt_03.pdf' End of script. Logfile hash: 1d5aa542b8 CPU: user 0.01s system 0.00s, MEM: 18.01 MB total, 8.74 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 25% 2x opt_expr (0 sec), 18% 1x opt_clean (0 sec), ... ../../yosys -p 'script opt_04.ys; show -notitle -prefix opt_04 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script opt_04.ys; show -notitle -prefix opt_04 -format pdf' -- -- Executing script file `opt_04.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `opt_04.v' to AST representation. Generating RTLIL representation for module `\test'. Warning: wire '\Q1' is assigned in a block at opt_04.v:8. Warning: wire '\Q2' is assigned in a block at opt_04.v:12. Warning: wire '\Q2' is assigned in a block at opt_04.v:14. Warning: wire '\Q3' is assigned in a block at opt_04.v:17. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \ARST in `\test.$proc$opt_04.v:10$2'. Found async reset \ARST in `\test.$proc$opt_04.v:6$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$opt_04.v:16$3'. 1/1: $0\Q3[7:0] Creating decoders for process `\test.$proc$opt_04.v:10$2'. 1/1: $0\Q2[7:0] Creating decoders for process `\test.$proc$opt_04.v:6$1'. 1/1: $0\Q1[7:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q3' using process `\test.$proc$opt_04.v:16$3'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\Q2' using process `\test.$proc$opt_04.v:10$2'. created $adff cell `$procdff$5' with positive edge clock and positive level reset. Creating register for signal `\test.\Q1' using process `\test.$proc$opt_04.v:6$1'. created $adff cell `$procdff$6' with positive edge clock and positive level reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$opt_04.v:16$3'. Removing empty process `test.$proc$opt_04.v:10$2'. Removing empty process `test.$proc$opt_04.v:6$1'. Cleaned up 0 empty switches. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $procdff$6 ($adff) from module test. Removing $procdff$5 ($adff) from module test. Removing $procdff$4 ($dff) from module test. Replaced 3 DFF cells. 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removing unused non-port wire \NO_CLK. removed 4 unused temporary wires. Removed 0 unused cells and 4 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_RMDFF pass (remove dff with constant values). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 4 unused wires. 4.15. Executing OPT_EXPR pass (perform const folding). 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `opt_04.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_04.dot' > 'opt_04.pdf.new' && mv 'opt_04.pdf.new' 'opt_04.pdf' Warnings: 4 unique messages, 4 total End of script. Logfile hash: 22f9ac9c39 CPU: user 0.02s system 0.00s, MEM: 18.02 MB total, 8.42 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 20% 3x opt_expr (0 sec), 18% 2x opt_clean (0 sec), ... ../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format pdf' -- -- Executing script file `memory_01.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `memory_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_01.v:5$2'. 1/4: $0\DOUT[7:0] 2/4: $0$memwr$\mem$memory_01.v:6$1_EN[7:0]$5 3/4: $0$memwr$\mem$memory_01.v:6$1_DATA[7:0]$4 4/4: $0$memwr$\mem$memory_01.v:6$1_ADDR[0:0]$3 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$9' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$10' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$11' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_01.v:5$2'. Cleaned up 0 empty switches. Removed 0 unused cells and 4 unused wires. 4. Executing MEMORY pass. 4.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$memwr$\mem$memory_01.v:6$7' in module `\test': merged $dff to cell. Checking cell `$memrd$\mem$memory_01.v:7$6' in module `\test': merged data $dff to cell. 4.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removing unused `$dff' cell `$procdff$9'. removing unused `$dff' cell `$procdff$8'. removing unused `$dff' cell `$procdff$10'. removing unused `$dff' cell `$procdff$11'. removed 5 unused temporary wires. Removed 4 unused cells and 9 unused wires. 4.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 4 unused cells and 9 unused wires. 4.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\test': $memwr$\mem$memory_01.v:6$7 ($memwr) $memrd$\mem$memory_01.v:7$6 ($memrd) 4.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). Mapping memory cell \mem in module \test: created 2 $dff cells and 0 static cells of width 8. read interface: 1 $dff and 1 $mux cells. write interface: 2 write mux blocks. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$23' in module `test' with inverter. Replacing $eq cell `$auto$memory_map.cc:65:addr_decode$27' (1) in module `\test' with constant driver `$auto$rtlil.cc:1709:Eq$28 = \ADDR'. Optimizing away select inverter for $mux cell `$memory\mem$wrmux[0][0][0]$25' in module `test'. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $memory\mem$wrmux[0][0][0]$25 (pure) Root of a mux tree: $memory\mem$rdmux[0][0][0]$20 (pure) Root of a mux tree: $memory\mem$wrmux[1][0][0]$29 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removing unused `$not' cell `$auto$memory_map.cc:65:addr_decode$23'. removed 6 unused temporary wires. Removed 5 unused cells and 15 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $memory\mem$rdmux[0][0][0]$20 (pure) Root of a mux tree: $memory\mem$wrmux[0][0][0]$25 (pure) Root of a mux tree: $memory\mem$wrmux[1][0][0]$29 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_RMDFF pass (remove dff with constant values). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 5 unused cells and 15 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). 5.16. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_01.dot' > 'memory_01.pdf.new' && mv 'memory_01.pdf.new' 'memory_01.pdf' End of script. Logfile hash: 0e54316c35 CPU: user 0.02s system 0.00s, MEM: 18.02 MB total, 8.85 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 22% 4x opt_clean (0 sec), 17% 3x opt_expr (0 sec), ... ../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format pdf' -- -- Executing script file `memory_02.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `memory_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_02.v:24$13'. 1/1: $0\RD2_DATA[7:0] Creating decoders for process `\test.$proc$memory_02.v:21$11'. 1/1: $0\RD1_DATA[7:0] Creating decoders for process `\test.$proc$memory_02.v:17$7'. 1/3: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 2/3: $0$memwr$\memory$memory_02.v:19$2_DATA[7:0]$9 3/3: $0$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$8 Creating decoders for process `\test.$proc$memory_02.v:13$3'. 1/3: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 2/3: $0$memwr$\memory$memory_02.v:15$1_DATA[7:0]$5 3/3: $0$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$4 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$13'. created $dff cell `$procdff$35' with positive edge clock. Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$11'. created $dff cell `$procdff$36' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$37' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$38' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$39' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$40' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$41' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$42' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_02.v:24$13'. Removing empty process `test.$proc$memory_02.v:21$11'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$7'. Removing empty process `test.$proc$memory_02.v:17$7'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. Removing empty process `test.$proc$memory_02.v:13$3'. Cleaned up 2 empty switches. Removed 0 unused cells and 14 unused wires. 4. Executing MEMORY pass. 4.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$memwr$\memory$memory_02.v:15$15' in module `\test': merged $dff to cell. Checking cell `$memwr$\memory$memory_02.v:19$16' in module `\test': merged $dff to cell. Checking cell `$memrd$\memory$memory_02.v:22$12' in module `\test': merged data $dff to cell. Checking cell `$memrd$\memory$memory_02.v:25$14' in module `\test': merged data $dff to cell. 4.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removing unused `$dff' cell `$procdff$36'. removing unused `$dff' cell `$procdff$35'. removing unused `$dff' cell `$procdff$37'. removing unused `$dff' cell `$procdff$38'. removing unused `$dff' cell `$procdff$39'. removing unused `$dff' cell `$procdff$40'. removing unused `$dff' cell `$procdff$41'. removing unused `$dff' cell `$procdff$42'. removed 10 unused temporary wires. Removed 8 unused cells and 24 unused wires. 4.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory test.memory by address: New clock domain: posedge \WR1_CLK Port 0 ($memwr$\memory$memory_02.v:15$15) has addr \WR1_ADDR. Active bits: 11111111 New clock domain: posedge \WR2_CLK Port 1 ($memwr$\memory$memory_02.v:19$16) has addr \WR2_ADDR. Active bits: 11111111 Consolidating write ports of memory test.memory using sat-based resource sharing: Port 0 ($memwr$\memory$memory_02.v:15$15) on posedge \WR1_CLK: considered Port 1 ($memwr$\memory$memory_02.v:19$16) on posedge \WR2_CLK: considered No two subsequent ports in same clock domain considered -> nothing to consolidate. 4.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 8 unused cells and 24 unused wires. 4.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\test': $memwr$\memory$memory_02.v:15$15 ($memwr) $memwr$\memory$memory_02.v:19$16 ($memwr) $memrd$\memory$memory_02.v:22$12 ($memrd) $memrd$\memory$memory_02.v:25$14 ($memrd) 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Replacing $mux cell `$procmux$21' (mux_empty) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:19$2_DATA[7:0]$9 = \WR2_DATA'. Replacing $mux cell `$procmux$24' (mux_empty) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$8 = \WR2_ADDR'. Replacing $mux cell `$procmux$30' (mux_empty) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:15$1_DATA[7:0]$5 = \WR1_DATA'. Replacing $mux cell `$procmux$33' (mux_empty) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$4 = \WR1_ADDR'. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$27 (pure) Root of a mux tree: $procmux$18 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Consolidated identical input bits for $mux cell $procmux$27: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } Consolidated identical input bits for $mux cell $procmux$18: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] } Optimizing cells in module \test. Performed a total of 2 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 4 unused temporary wires. Removed 8 unused cells and 28 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Replacing $mux cell `$procmux$18' (mux_bool) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [7] = \WR2_WEN'. Replacing $mux cell `$procmux$27' (mux_bool) in module `\test' with constant driver `$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7] = \WR1_WEN'. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_RMDFF pass (remove dff with constant values). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 2 unused temporary wires. Removed 8 unused cells and 30 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). 5.16. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_02.dot' > 'memory_02.pdf.new' && mv 'memory_02.pdf.new' 'memory_02.pdf' End of script. Logfile hash: ec4746bb24 CPU: user 0.02s system 0.01s, MEM: 18.10 MB total, 8.93 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 24% 4x opt_clean (0 sec), 14% 3x opt_expr (0 sec), ... ../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' -- -- Executing script file `techmap_01.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 32 Parameter \B_WIDTH = 32 Parameter \Y_WIDTH = 32 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32'. 3.3. Continuing TECHMAP pass. Mapping test.$add$techmap_01.v:3$1 using $paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32. 3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 16 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 17 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=17'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=17' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 1 Parameter \Y_WIDTH = 16 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=1\Y_WIDTH=16'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=1\Y_WIDTH=16' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.7. Continuing TECHMAP pass. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `techmap_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'techmap_01.dot' > 'techmap_01.pdf.new' && mv 'techmap_01.pdf.new' 'techmap_01.pdf' End of script. Logfile hash: 75ac20ff0b CPU: user 0.01s system 0.00s, MEM: 18.14 MB total, 9.13 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 39% 1x techmap (0 sec), 19% 1x clean (0 sec), ... ../../yosys -p 'script abc_01.ys; show -notitle -prefix abc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Running command `script abc_01.ys; show -notitle -prefix abc_01 -format pdf' -- -- Executing script file `abc_01.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `abc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend. Parsing Verilog input from `abc_01_cells.v' to AST representation. Generating RTLIL representation for module `\BUF'. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Generating RTLIL representation for module `\DFFSR'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$abc_01.v:5$1'. 1/3: $0\y[0:0] 2/3: $0\q2[2:0] 3/3: $0\q1[2:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\y' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$3' with positive edge clock. Creating register for signal `\test.\q1' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\q2' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$5' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$abc_01.v:5$1'. Cleaned up 0 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removed 3 unused temporary wires. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Finished OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend. Parsing Verilog input from `' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. Mapping test.$reduce_xor$abc_01.v:8$2 ($reduce_xor) with simplemap. Mapping test.$procdff$3 ($dff) with simplemap. Mapping test.$procdff$4 ($dff) with simplemap. Mapping test.$procdff$5 ($dff) with simplemap. No more expansions possible. 7. Executing ABC pass (technology mapping using ABC). 7.1. Summary of detected clock domains: 9 cells in clk=\clk, en={ } 7.2. Extracting gate netlist of module `\test' to `/input.blif'.. Found matching posedge clock domain: \clk Extracted 9 gates and 12 wires to a netlist network with 3 inputs and 1 outputs. 7.2.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_ExSyn/abc_01_cells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR". ABC: Library "demo" from "/manual/PRESENTATION_ExSyn/abc_01_cells.lib" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: 7 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 7.2.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 3 ABC RESULTS: NAND cells: 2 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 3 ABC RESULTS: _dff_ cells: 3 ABC RESULTS: internal signals: 8 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 1 Removing temp directory. Removed 0 unused cells and 9 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `abc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'abc_01.dot' > 'abc_01.pdf.new' && mv 'abc_01.pdf.new' 'abc_01.pdf' End of script. Logfile hash: 46ca4260bf CPU: user 0.04s system 0.00s, MEM: 18.93 MB total, 9.81 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 52% 5x read_verilog (0 sec), 10% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-0.8/manual/PRESENTATION_ExSyn' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20181017163613Z)#' PRESENTATION_ExSyn/abc_01.pdf PRESENTATION_ExSyn/memory_01.pdf PRESENTATION_ExSyn/memory_02.pdf PRESENTATION_ExSyn/opt_01.pdf PRESENTATION_ExSyn/opt_02.pdf PRESENTATION_ExSyn/opt_03.pdf PRESENTATION_ExSyn/opt_04.pdf PRESENTATION_ExSyn/proc_01.pdf PRESENTATION_ExSyn/proc_02.pdf PRESENTATION_ExSyn/proc_03.pdf PRESENTATION_ExSyn/techmap_01.pdf + make -C PRESENTATION_ExAdv make[3]: Entering directory '/build/yosys-0.8/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys select.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `select.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `select.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$select.v:7$1'. 1/2: $0\c[15:0] 2/2: $0\b[15:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\b' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.\c' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$9' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$select.v:7$1'. Cleaned up 0 empty switches. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing away select inverter for $mux cell `$ternary$select.v:14$7' in module `test'. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Cell `$xor$select.v:12$2' is identical to cell `$xor$select.v:13$4'. Redirecting output \Y: $xor$select.v:12$2_Y = $xor$select.v:13$4_Y Removing $xor cell `$xor$select.v:12$2' from module `\test'. Removed a total of 1 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $ternary$select.v:14$7 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_RMDFF pass (remove dff with constant values). 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. removing unused `$logic_not' cell `$logic_not$select.v:14$6'. removed 7 unused temporary wires. Removed 1 unused cells and 7 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $ternary$select.v:14$7 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_RMDFF pass (remove dff with constant values). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 7 unused wires. 4.15. Executing OPT_EXPR pass (perform const folding). 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `select.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'select.dot' > 'select.pdf.new' && mv 'select.pdf.new' 'select.pdf' End of script. Logfile hash: 9830ce54b4 CPU: user 0.02s system 0.00s, MEM: 18.00 MB total, 9.15 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 21% 3x opt_expr (0 sec), 18% 2x opt_clean (0 sec), ... ../../yosys red_or3x1_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `red_or3x1_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `red_or3x1_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `red_or3x1_map.v' to AST representation. Generating RTLIL representation for module `\$reduce_or'. Successfully finished Verilog frontend. 3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$reduce_or'. Parameter \A_SIGNED = 0 Parameter \A_WIDTH = 7 Parameter \Y_WIDTH = 1 Generating RTLIL representation for module `$paramod\$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'. 3.3. Continuing TECHMAP pass. Mapping test.$reduce_or$red_or3x1_test.v:4$1 using $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1. 3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$reduce_or'. Parameter \A_SIGNED = 0 Parameter \A_WIDTH = 1 Parameter \Y_WIDTH = 1 Generating RTLIL representation for module `$paramod\$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'. 3.5. Continuing TECHMAP pass. Mapping test.$techmap$reduce_or$red_or3x1_test.v:4$1.$reduce_or$red_or3x1_map.v:43$10 using $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1. 3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$reduce_or'. Parameter \A_SIGNED = 0 Parameter \A_WIDTH = 3 Parameter \Y_WIDTH = 1 Generating RTLIL representation for module `$paramod\$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'. 3.7. Continuing TECHMAP pass. Mapping test.$techmap$reduce_or$red_or3x1_test.v:4$1.$reduce_or$red_or3x1_map.v:43$9 using $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1. Mapping test.$techmap$reduce_or$red_or3x1_test.v:4$1.$reduce_or$red_or3x1_map.v:43$8 using $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1. Mapping test.$techmap$reduce_or$red_or3x1_test.v:4$1.$reduce_or$red_or3x1_map.v:45$11 using $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1. No more expansions possible. Removed 0 unused cells and 18 unused wires. 4. Executing SPLITNETS pass (splitting up multi-bit signals). 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend. Parsing Verilog input from `red_or3x1_cells.v' to AST representation. Generating RTLIL representation for module `\OR3X1'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `red_or3x1.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'red_or3x1.dot' > 'red_or3x1.pdf.new' && mv 'red_or3x1.pdf.new' 'red_or3x1.pdf' End of script. Logfile hash: 27736701b7 CPU: user 0.01s system 0.00s, MEM: 18.14 MB total, 9.02 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 42% 1x techmap (0 sec), 25% 4x read_verilog (0 sec), ... ../../yosys sym_mul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `sym_mul_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$mul'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Generating RTLIL representation for module `$paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. 3.3. Continuing TECHMAP pass. Mapping test.$mul$sym_mul_test.v:3$1 using $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8. 3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$mul'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 16 Generating RTLIL representation for module `$paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=16'. Not using module `$paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=16' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.5. Continuing TECHMAP pass. No more expansions possible. Removed 0 unused cells and 6 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `sym_mul.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'sym_mul.dot' > 'sym_mul.pdf.new' && mv 'sym_mul.pdf.new' 'sym_mul.pdf' End of script. Logfile hash: c3b5467500 CPU: user 0.00s system 0.01s, MEM: 18.02 MB total, 8.93 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 28% 4x read_verilog (0 sec), 27% 1x show (0 sec), ... ../../yosys mymul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `mymul_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend. Parsing Verilog input from `mymul_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\$mul'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 2 Parameter \B_WIDTH = 2 Parameter \Y_WIDTH = 2 Generating RTLIL representation for module `$paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'. 3.4. Continuing TECHMAP pass. Mapping test.$mul$mymul_test.v:3$1 using $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2. 3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\MYMUL'. Parameter \WIDTH = 2 Generating RTLIL representation for module `$paramod\MYMUL\WIDTH=2'. 3.6. Executing PROC pass (convert processes to netlists). 3.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.6.3. Executing PROC_INIT pass (extract init attributes). 3.6.4. Executing PROC_ARST pass (detect async resets in processes). 3.6.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\MYMUL\WIDTH=2.$proc$mymul_map.v:9$8'. 1/3: $2\Y[1:0] 2/3: $1\Y[1:0] 3/3: $0\Y[1:0] 3.6.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\MYMUL\WIDTH=2.\Y' from process `$paramod\MYMUL\WIDTH=2.$proc$mymul_map.v:9$8'. 3.6.7. Executing PROC_DFF pass (convert process syncs to FFs). 3.6.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `$paramod\MYMUL\WIDTH=2.$proc$mymul_map.v:9$8'. Removing empty process `$paramod\MYMUL\WIDTH=2.$proc$mymul_map.v:9$8'. Cleaned up 2 empty switches. Removed 0 unused cells and 7 unused wires. 3.7. Continuing TECHMAP pass. Mapping test.$mul$mymul_test.v:3$1.g using $paramod\MYMUL\WIDTH=2. No more expansions possible. Removed 0 unused cells and 9 unused wires. Renaming module \test to \test_mapped. 4. Executing Verilog-2005 frontend. Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 5. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". 6. Executing FLATTEN pass (flatten design). Mapping miter.gate using test_mapped. Mapping miter.gold using test. No more expansions possible. 7. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 9 cells to SAT database. Import proof-constraint: \trigger = 1'0 Final proof equation: \trigger = 1'0 Solving problem with 127 variables and 335 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ 8. Executing SPLITNETS pass (splitting up multi-bit signals). 9. Generating Graphviz representation of design. Writing dot description to `mymul.dot'. Dumping module test_mapped to page 1. Exec: dot -Tpdf 'mymul.dot' > 'mymul.pdf.new' && mv 'mymul.pdf.new' 'mymul.pdf' End of script. Logfile hash: 9fe419e02d CPU: user 0.02s system 0.01s, MEM: 18.18 MB total, 9.09 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 23% 2x clean (0 sec), 23% 1x techmap (0 sec), ... ../../yosys mulshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `mulshift_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `mulshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend. Parsing Verilog input from `mulshift_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\$mul'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Generating RTLIL representation for module `$paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8'. 3.4. Continuing TECHMAP pass. Mapping test.$mul$mulshift_test.v:3$1 using $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8. Mapping test.$mul$mulshift_test.v:4$2 using $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8. 3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\MYMUL'. Parameter \WIDTH = 8 Parameter \_TECHMAP_CONSTVAL_A_ = 8'xxxxxxxx Parameter \_TECHMAP_CONSTVAL_B_ = 8'00000110 Generating RTLIL representation for module `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL'. 3.6. Executing PROC pass (convert processes to netlists). 3.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 16 empty switches in `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL.$proc$mulshift_map.v:13$13'. Cleaned up 16 empty switches. 3.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.6.3. Executing PROC_INIT pass (extract init attributes). 3.6.4. Executing PROC_ARST pass (detect async resets in processes). 3.6.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL.$proc$mulshift_map.v:13$13'. 1/1: $0\_TECHMAP_FAIL_[0:0] 3.6.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL.\_TECHMAP_FAIL_' from process `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL.$proc$mulshift_map.v:13$13'. 3.6.7. Executing PROC_DFF pass (convert process syncs to FFs). 3.6.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL.$proc$mulshift_map.v:13$13'. Cleaned up 0 empty switches. Removed 0 unused cells and 2 unused wires. Not using module `$paramod$1b0b600112208fff86ad008ae0eb578639bae2db\MYMUL' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\MYMUL'. Parameter \WIDTH = 8 Parameter \_TECHMAP_CONSTVAL_A_ = 8'xxxxxxxx Parameter \_TECHMAP_CONSTVAL_B_ = 8'00001000 Generating RTLIL representation for module `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL'. 3.8. Executing PROC pass (convert processes to netlists). 3.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 16 empty switches in `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.$proc$mulshift_map.v:13$22'. Cleaned up 16 empty switches. 3.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.8.3. Executing PROC_INIT pass (extract init attributes). 3.8.4. Executing PROC_ARST pass (detect async resets in processes). 3.8.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.$proc$mulshift_map.v:13$22'. 1/2: $0\_TECHMAP_FAIL_[0:0] 2/2: $0\Y[7:0] 3.8.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.\Y' from process `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.$proc$mulshift_map.v:13$22'. No latch inferred for signal `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.\_TECHMAP_FAIL_' from process `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.$proc$mulshift_map.v:13$22'. 3.8.7. Executing PROC_DFF pass (convert process syncs to FFs). 3.8.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL.$proc$mulshift_map.v:13$22'. Cleaned up 0 empty switches. Removed 0 unused cells and 4 unused wires. 3.9. Continuing TECHMAP pass. Mapping test.$mul$mulshift_test.v:4$2.g using $paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL. No more expansions possible. Removed 0 unused cells and 15 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend. Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `mulshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'mulshift.dot' > 'mulshift.pdf.new' && mv 'mulshift.pdf.new' 'mulshift.pdf' End of script. Logfile hash: 5a565601a1 CPU: user 0.02s system 0.01s, MEM: 18.28 MB total, 9.13 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 35% 1x techmap (0 sec), 30% 3x clean (0 sec), ... ../../yosys addshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `addshift_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `addshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `addshift_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Parameter \_TECHMAP_BITS_CONNMAP_ = 4 Parameter \_TECHMAP_CONNMAP_A_ = 839974620 Parameter \_TECHMAP_CONNMAP_B_ = 32'10111010100110000111011001010100 Generating RTLIL representation for module `$paramod$0e8d90b8a6e51673a0516c26bc09ecf59532e668\$add'. Not using module `$paramod$0e8d90b8a6e51673a0516c26bc09ecf59532e668\$add' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 8 Parameter \B_WIDTH = 8 Parameter \Y_WIDTH = 8 Parameter \_TECHMAP_BITS_CONNMAP_ = 3 Parameter \_TECHMAP_CONNMAP_A_ = 24'011010001000111110101100 Parameter \_TECHMAP_CONNMAP_B_ = 24'011010001000111110101100 Generating RTLIL representation for module `$paramod$f9d15d41450676d24e4cd1a1cce4370f40b165ac\$add'. 3.4. Continuing TECHMAP pass. Mapping test.$add$addshift_test.v:4$2 using $paramod$f9d15d41450676d24e4cd1a1cce4370f40b165ac\$add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `addshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'addshift.dot' > 'addshift.pdf.new' && mv 'addshift.pdf.new' 'addshift.pdf' End of script. Logfile hash: f5437c9a24 CPU: user 0.01s system 0.00s, MEM: 18.02 MB total, 8.98 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 28% 3x read_verilog (0 sec), 27% 1x techmap (0 sec), ... ../../yosys macc_simple_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `macc_simple_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 3. Generating Graphviz representation of design. 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 3.2. Continuing show pass. Writing dot description to `macc_simple_test_00a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00a.dot' > 'macc_simple_test_00a.pdf.new' && mv 'macc_simple_test_00a.pdf.new' 'macc_simple_test_00a.pdf' 4. Executing EXTRACT pass (map subcircuits to cells). 4.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.2.3. Executing PROC_INIT pass (extract init attributes). 4.2.4. Executing PROC_ARST pass (detect async resets in processes). 4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. removed 1 unused temporary wires. Removed 0 unused cells and 2 unused wires. 4.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 4.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 4.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$8 Removed 0 unused cells and 1 unused wires. 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `macc_simple_test_00b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00b.dot' > 'macc_simple_test_00b.pdf.new' && mv 'macc_simple_test_00b.pdf.new' 'macc_simple_test_00b.pdf' 6. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_test_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 7. Executing HIERARCHY pass (managing design hierarchy). 7.1. Analyzing design hierarchy.. Top module: \test 7.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 8. Generating Graphviz representation of design. 8.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 8.2. Continuing show pass. Writing dot description to `macc_simple_test_01a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01a.dot' > 'macc_simple_test_01a.pdf.new' && mv 'macc_simple_test_01a.pdf.new' 'macc_simple_test_01a.pdf' 9. Executing EXTRACT pass (map subcircuits to cells). 9.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 9.2. Executing PROC pass (convert processes to netlists). 9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 9.2.3. Executing PROC_INIT pass (extract init attributes). 9.2.4. Executing PROC_ARST pass (detect async resets in processes). 9.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 9.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 9.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 9.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. removed 1 unused temporary wires. Removed 0 unused cells and 2 unused wires. 9.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 9.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 9.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$19 Removed 0 unused cells and 1 unused wires. 10. Generating Graphviz representation of design. 10.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 10.2. Continuing show pass. Writing dot description to `macc_simple_test_01b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01b.dot' > 'macc_simple_test_01b.pdf.new' && mv 'macc_simple_test_01b.pdf.new' 'macc_simple_test_01b.pdf' 11. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_test_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 12. Executing HIERARCHY pass (managing design hierarchy). 12.1. Analyzing design hierarchy.. Top module: \test 12.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 13. Generating Graphviz representation of design. 13.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 13.2. Continuing show pass. Writing dot description to `macc_simple_test_02a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02a.dot' > 'macc_simple_test_02a.pdf.new' && mv 'macc_simple_test_02a.pdf.new' 'macc_simple_test_02a.pdf' 14. Executing EXTRACT pass (map subcircuits to cells). 14.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 14.2. Executing PROC pass (convert processes to netlists). 14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 14.2.3. Executing PROC_INIT pass (extract init attributes). 14.2.4. Executing PROC_ARST pass (detect async resets in processes). 14.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 14.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 14.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 14.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. removed 1 unused temporary wires. Removed 0 unused cells and 2 unused wires. 14.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 14.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 2 matches. 14.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$23 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$30 Match #1: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$31 Removed 0 unused cells and 2 unused wires. 15. Generating Graphviz representation of design. 15.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 15.2. Continuing show pass. Writing dot description to `macc_simple_test_02b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02b.dot' > 'macc_simple_test_02b.pdf.new' && mv 'macc_simple_test_02b.pdf.new' 'macc_simple_test_02b.pdf' 16. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 17. Executing HIERARCHY pass (managing design hierarchy). 17.1. Analyzing design hierarchy.. Top module: \macc_16_16_32 17.2. Analyzing design hierarchy.. Top module: \macc_16_16_32 Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_simple_xmap.dot'. Dumping module macc_16_16_32 to page 1. Exec: dot -Tpdf 'macc_simple_xmap.dot' > 'macc_simple_xmap.pdf.new' && mv 'macc_simple_xmap.pdf.new' 'macc_simple_xmap.pdf' End of script. Logfile hash: 1046f45c0f CPU: user 0.05s system 0.00s, MEM: 18.12 MB total, 8.91 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 23% 3x extract (0 sec), 23% 7x clean (0 sec), ... ../../yosys macc_xilinx_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `macc_xilinx_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_test.v' to AST representation. Generating RTLIL representation for module `\test1'. Generating RTLIL representation for module `\test2'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `$__mul_wrapper'. Generating RTLIL representation for module `$__add_wrapper'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 4. Executing HIERARCHY pass (managing design hierarchy). Removed 0 unused cells and 2 unused wires. 5. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1a.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1a.dot' > 'macc_xilinx_test1a.pdf.new' && mv 'macc_xilinx_test1a.pdf.new' 'macc_xilinx_test1a.pdf' 6. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2a.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2a.dot' > 'macc_xilinx_test2a.pdf.new' && mv 'macc_xilinx_test2a.pdf.new' 'macc_xilinx_test2a.pdf' 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 7.2. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_swap_ports'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 20 Parameter \B_WIDTH = 20 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42'. Not using module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 7.3. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_swap_ports'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 20 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=16\Y_WIDTH=42'. 7.4. Continuing TECHMAP pass. Mapping test1.$mul$macc_xilinx_test.v:5$2 using $paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=16\Y_WIDTH=42. 7.5. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_swap_ports'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42'. Not using module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 7.6. Continuing TECHMAP pass. 7.7. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_swap_ports'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 20 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42'. Not using module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 7.8. Continuing TECHMAP pass. Mapping test2.$mul$macc_xilinx_test.v:12$7 using $paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=16\Y_WIDTH=42. No more expansions possible. Removed 0 unused cells and 8 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1b.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1b.dot' > 'macc_xilinx_test1b.pdf.new' && mv 'macc_xilinx_test1b.pdf.new' 'macc_xilinx_test1b.pdf' 9. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2b.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2b.dot' > 'macc_xilinx_test2b.pdf.new' && mv 'macc_xilinx_test2b.pdf.new' 'macc_xilinx_test2b.pdf' 10. Executing TECHMAP pass (map to technology primitives). 10.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 10.2. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 20 Parameter \B_WIDTH = 20 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42'. 10.3. Executing PROC pass (convert processes to netlists). 10.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 4 empty switches in `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$15'. Cleaned up 4 empty switches. 10.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 10.3.3. Executing PROC_INIT pass (extract init attributes). 10.3.4. Executing PROC_ARST pass (detect async resets in processes). 10.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$15'. 1/1: $0\_TECHMAP_FAIL_[0:0] 10.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42.\_TECHMAP_FAIL_' from process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$15'. 10.3.7. Executing PROC_DFF pass (convert process syncs to FFs). 10.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$15'. Cleaned up 0 empty switches. Warning: Driver-driver conflict for \B_25 [20] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [21] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [22] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [23] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [24] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Removed 0 unused cells and 1 unused wires. Not using module `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=20\Y_WIDTH=42' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 10.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 20 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42'. 10.5. Executing PROC pass (convert processes to netlists). 10.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 4 empty switches in `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$16'. Cleaned up 4 empty switches. 10.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 10.5.3. Executing PROC_INIT pass (extract init attributes). 10.5.4. Executing PROC_ARST pass (detect async resets in processes). 10.5.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$16'. 1/1: $0\_TECHMAP_FAIL_[0:0] 10.5.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42.\_TECHMAP_FAIL_' from process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$16'. 10.5.7. Executing PROC_DFF pass (convert process syncs to FFs). 10.5.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$16'. Cleaned up 0 empty switches. Warning: Driver-driver conflict for \B_25 [20] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [21] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [22] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [23] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [24] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_18 [16] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_18 [17] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42: Resolved using constant. Removed 0 unused cells and 1 unused wires. 10.6. Continuing TECHMAP pass. Mapping test1.$mul$macc_xilinx_test.v:5$2 using $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42. 10.7. Executing AST frontend in derive mode using pre-parsed AST for module `\add_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 42 Parameter \B_WIDTH = 42 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42'. 10.8. Executing PROC pass (convert processes to netlists). 10.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:69$18'. Cleaned up 2 empty switches. 10.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 10.8.3. Executing PROC_INIT pass (extract init attributes). 10.8.4. Executing PROC_ARST pass (detect async resets in processes). 10.8.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:69$18'. 1/1: $0\_TECHMAP_FAIL_[0:0] 10.8.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42.\_TECHMAP_FAIL_' from process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:69$18'. 10.8.7. Executing PROC_DFF pass (convert process syncs to FFs). 10.8.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:69$18'. Cleaned up 0 empty switches. Warning: Driver-driver conflict for \B_48 [42] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_48 [43] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_48 [44] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_48 [45] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_48 [46] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_48 [47] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [42] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [43] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [44] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [45] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [46] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_48 [47] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42: Resolved using constant. Removed 0 unused cells and 1 unused wires. 10.9. Continuing TECHMAP pass. Mapping test1.$add$macc_xilinx_test.v:5$3 using $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42. 10.10. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42'. 10.11. Executing PROC pass (convert processes to netlists). 10.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 4 empty switches in `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$20'. Cleaned up 4 empty switches. 10.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 10.11.3. Executing PROC_INIT pass (extract init attributes). 10.11.4. Executing PROC_ARST pass (detect async resets in processes). 10.11.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$20'. 1/1: $0\_TECHMAP_FAIL_[0:0] 10.11.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42.\_TECHMAP_FAIL_' from process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$20'. 10.11.7. Executing PROC_DFF pass (convert process syncs to FFs). 10.11.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42.$proc$macc_xilinx_wrap_map.v:22$20'. Cleaned up 0 empty switches. Warning: Driver-driver conflict for \B_25 [16] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [17] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [18] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [19] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [20] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [21] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [22] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [23] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \B_25 [24] between cell _TECHMAP_REPLACE_.B and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_18 [16] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Warning: Driver-driver conflict for \A_18 [17] between cell _TECHMAP_REPLACE_.A and constant 1'0 in $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42: Resolved using constant. Removed 0 unused cells and 1 unused wires. 10.12. Continuing TECHMAP pass. Mapping test1.$mul$macc_xilinx_test.v:5$4 using $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42. Mapping test1.$add$macc_xilinx_test.v:5$5 using $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42. Mapping test2.$mul$macc_xilinx_test.v:12$7 using $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42. Mapping test2.$mul$macc_xilinx_test.v:12$8 using $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42. Mapping test2.$add$macc_xilinx_test.v:12$9 using $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42. Mapping test2.$add$macc_xilinx_test.v:12$10 using $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42. No more expansions possible. 11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap19$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap21$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap17$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap25$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap23$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap24$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } Removed 0 unused cells and 56 unused wires. 12. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1c.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1c.dot' > 'macc_xilinx_test1c.pdf.new' && mv 'macc_xilinx_test1c.pdf.new' 'macc_xilinx_test1c.pdf' 13. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2c.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2c.dot' > 'macc_xilinx_test2c.pdf.new' && mv 'macc_xilinx_test2c.pdf.new' 'macc_xilinx_test2c.pdf' 14. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 15. Executing TECHMAP pass (map to technology primitives). 15.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 15.2. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_swap_ports'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 18 Parameter \B_WIDTH = 25 Parameter \Y_WIDTH = 48 Generating RTLIL representation for module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48'. Not using module `$paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 15.3. Continuing TECHMAP pass. No more expansions possible. 16. Executing TECHMAP pass (map to technology primitives). 16.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 16.2. Executing AST frontend in derive mode using pre-parsed AST for module `\mul_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 18 Parameter \B_WIDTH = 25 Parameter \Y_WIDTH = 48 Generating RTLIL representation for module `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48'. 16.3. Executing PROC pass (convert processes to netlists). 16.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 4 empty switches in `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:22$31'. Cleaned up 4 empty switches. 16.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 16.3.3. Executing PROC_INIT pass (extract init attributes). 16.3.4. Executing PROC_ARST pass (detect async resets in processes). 16.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:22$31'. 1/1: $0\_TECHMAP_FAIL_[0:0] 16.3.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48.\_TECHMAP_FAIL_' from process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:22$31'. 16.3.7. Executing PROC_DFF pass (convert process syncs to FFs). 16.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:22$31'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 16.4. Continuing TECHMAP pass. Mapping DSP48_MACC.$mul$macc_xilinx_xmap.v:8$27 using $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48. 16.5. Executing AST frontend in derive mode using pre-parsed AST for module `\add_wrap'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 48 Parameter \B_WIDTH = 48 Parameter \Y_WIDTH = 48 Generating RTLIL representation for module `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48'. 16.6. Executing PROC pass (convert processes to netlists). 16.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:69$33'. Cleaned up 2 empty switches. 16.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 16.6.3. Executing PROC_INIT pass (extract init attributes). 16.6.4. Executing PROC_ARST pass (detect async resets in processes). 16.6.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:69$33'. 1/1: $0\_TECHMAP_FAIL_[0:0] 16.6.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48.\_TECHMAP_FAIL_' from process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:69$33'. 16.6.7. Executing PROC_DFF pass (convert process syncs to FFs). 16.6.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48.$proc$macc_xilinx_wrap_map.v:69$33'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 16.7. Continuing TECHMAP pass. Mapping DSP48_MACC.$add$macc_xilinx_xmap.v:8$28 using $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48. No more expansions possible. Removed 0 unused cells and 17 unused wires. 17. Executing EXTRACT pass (map subcircuits to cells). 17.1. Creating graphs for SubCircuit library. Creating needle graph needle_DSP48_MACC. Creating haystack graph haystack_$__add_wrapper. Creating haystack graph haystack_$__mul_wrapper. Creating haystack graph haystack_DSP48_MACC. Creating haystack graph haystack_test1. Creating haystack graph haystack_test2. 17.2. Running solver from SubCircuit library. Solving for needle_DSP48_MACC in haystack_$__add_wrapper. Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. Solving for needle_DSP48_MACC in haystack_DSP48_MACC. Solving for needle_DSP48_MACC in haystack_test1. Solving for needle_DSP48_MACC in haystack_test2. Found 3 matches. 17.3. Substitute SubCircuits with cells. Match #0: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$35 Match #1: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$36 Match #2: (needle_DSP48_MACC in haystack_test2) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$37 Removed 0 unused cells and 6 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1d.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1d.dot' > 'macc_xilinx_test1d.pdf.new' && mv 'macc_xilinx_test1d.pdf.new' 'macc_xilinx_test1d.pdf' 19. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2d.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2d.dot' > 'macc_xilinx_test2d.pdf.new' && mv 'macc_xilinx_test2d.pdf.new' 'macc_xilinx_test2d.pdf' 20. Executing TECHMAP pass (map to technology primitives). 20.1. Executing Verilog-2005 frontend. Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `\$__mul_wrapper'. Generating RTLIL representation for module `\$__add_wrapper'. Successfully finished Verilog frontend. 20.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$__mul_wrapper'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\$__mul_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42'. 20.3. Continuing TECHMAP pass. Mapping test2.$mul$macc_xilinx_test.v:12$8 using $paramod\$__mul_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42. 20.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$__add_wrapper'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 42 Parameter \B_WIDTH = 42 Parameter \Y_WIDTH = 42 Generating RTLIL representation for module `$paramod\$__add_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42'. 20.5. Continuing TECHMAP pass. Mapping test2.$add$macc_xilinx_test.v:12$10 using $paramod\$__add_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42. No more expansions possible. Removed 0 unused cells and 14 unused wires. 21. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1e.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1e.dot' > 'macc_xilinx_test1e.pdf.new' && mv 'macc_xilinx_test1e.pdf.new' 'macc_xilinx_test1e.pdf' 22. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2e.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2e.dot' > 'macc_xilinx_test2e.pdf.new' && mv 'macc_xilinx_test2e.pdf.new' 'macc_xilinx_test2e.pdf' 23. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_xmap.dot'. Dumping module DSP48_MACC to page 1. Exec: dot -Tpdf 'macc_xilinx_xmap.dot' > 'macc_xilinx_xmap.pdf.new' && mv 'macc_xilinx_xmap.pdf.new' 'macc_xilinx_xmap.pdf' Warnings: 35 unique messages, 35 total End of script. Logfile hash: b22ff3d5d3 CPU: user 0.11s system 0.02s, MEM: 18.85 MB total, 9.41 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 34% 12x clean (0 sec), 23% 5x techmap (0 sec), ... make[3]: Leaving directory '/build/yosys-0.8/manual/PRESENTATION_ExAdv' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20181017163613Z)#' PRESENTATION_ExAdv/addshift.pdf PRESENTATION_ExAdv/macc_simple_test_00a.pdf PRESENTATION_ExAdv/macc_simple_test_00b.pdf PRESENTATION_ExAdv/macc_simple_test_01a.pdf PRESENTATION_ExAdv/macc_simple_test_01b.pdf PRESENTATION_ExAdv/macc_simple_test_02a.pdf PRESENTATION_ExAdv/macc_simple_test_02b.pdf PRESENTATION_ExAdv/macc_simple_xmap.pdf PRESENTATION_ExAdv/macc_xilinx_test1a.pdf PRESENTATION_ExAdv/macc_xilinx_test1b.pdf PRESENTATION_ExAdv/macc_xilinx_test1c.pdf PRESENTATION_ExAdv/macc_xilinx_test1d.pdf PRESENTATION_ExAdv/macc_xilinx_test1e.pdf PRESENTATION_ExAdv/macc_xilinx_test2a.pdf PRESENTATION_ExAdv/macc_xilinx_test2b.pdf PRESENTATION_ExAdv/macc_xilinx_test2c.pdf PRESENTATION_ExAdv/macc_xilinx_test2d.pdf PRESENTATION_ExAdv/macc_xilinx_test2e.pdf PRESENTATION_ExAdv/macc_xilinx_xmap.pdf PRESENTATION_ExAdv/mulshift.pdf PRESENTATION_ExAdv/mymul.pdf PRESENTATION_ExAdv/red_or3x1.pdf PRESENTATION_ExAdv/select.pdf PRESENTATION_ExAdv/sym_mul.pdf + make -C PRESENTATION_ExOth make[3]: Entering directory '/build/yosys-0.8/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys scrambler.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `scrambler.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'. 1/3: $1\xs[31:0] 2/3: $0\out_bit[0:0] 3/3: $0\xs[31:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$12' with positive edge clock. Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$13' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'. Removing empty process `scrambler.$proc$scrambler.v:6$1'. Cleaned up 1 empty switch. Removed 0 unused cells and 4 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \scrambler.. Removed 0 unused cells and 4 unused wires. 4.2. Continuing SUBMOD pass. Creating submodule xorshift32 (\xorshift32) of module \scrambler. signal $shl$scrambler.v:11$6_Y: internal signal $0\xs[31:0]: output \n1 signal $shl$scrambler.v:9$2_Y: internal signal $1\xs[31:0]: input \n2 signal $xor$scrambler.v:9$3_Y: internal signal $shr$scrambler.v:10$4_Y: internal signal $xor$scrambler.v:10$5_Y: internal cell $xor$scrambler.v:9$3 ($xor) cell $shl$scrambler.v:9$2 ($shl) cell $shr$scrambler.v:10$4 ($shr) cell $xor$scrambler.v:10$5 ($xor) cell $shl$scrambler.v:11$6 ($shl) cell $xor$scrambler.v:11$7 ($xor) 5. Generating Graphviz representation of design. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. Exec: dot -Tpdf 'scrambler_p01.dot' > 'scrambler_p01.pdf.new' && mv 'scrambler_p01.pdf.new' 'scrambler_p01.pdf' 6. Generating Graphviz representation of design. Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. Exec: dot -Tpdf 'scrambler_p02.dot' > 'scrambler_p02.pdf.new' && mv 'scrambler_p02.pdf.new' 'scrambler_p02.pdf' echo on yosys> cd xorshift32 yosys [xorshift32]> rename n2 in Renaming wire n2 to in in module xorshift32. yosys [xorshift32]> rename n1 out Renaming wire n1 to out in module xorshift32. yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out 8. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 67634689. yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Import set-constraint: \out = 632435482 Final constraint equation: \out = 632435482 Imported 6 cells to SAT database. Solving problem with 1119 variables and 2905 clauses.. SAT solving finished - model found: Signal Name Dec Hex Bin --------------- ----------- --------- ----------------------------------- \in 745495504 2c6f5bd0 00101100011011110101101111010000 \out 632435482 25b2331a 00100101101100100011001100011010 End of script. Logfile hash: 981af5d4c2 CPU: user 0.03s system 0.01s, MEM: 18.88 MB total, 9.71 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 47% 1x sat (0 sec), 11% 1x submod (0 sec), ... ../../yosys -l equiv.log_new equiv.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `equiv.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Renaming module \test to \test_mapped. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend. Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 32 Parameter \B_WIDTH = 32 Parameter \Y_WIDTH = 32 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32'. 3.3. Continuing TECHMAP pass. Mapping test_mapped.$add$../PRESENTATION_ExSyn/techmap_01.v:3$1 using $paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32. 3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 16 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=16' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 16 Parameter \Y_WIDTH = 17 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=17'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=17' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$add'. Parameter \A_SIGNED = 0 Parameter \B_SIGNED = 0 Parameter \A_WIDTH = 16 Parameter \B_WIDTH = 1 Parameter \Y_WIDTH = 16 Generating RTLIL representation for module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=1\Y_WIDTH=16'. Not using module `$paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=1\Y_WIDTH=16' from techmap as it contains a _TECHMAP_FAIL_ marker wire with non-zero value 1'1. 3.7. Continuing TECHMAP pass. No more expansions possible. 4. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test_orig" and gate cell "test_mapped". 5. Executing FLATTEN pass (flatten design). Mapping miter.gate using test_mapped. Mapping miter.gold using test_orig. No more expansions possible. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof for assert: $auto$miter.cc:211:create_miter_equiv$6 when 1'1. Import show expression: \in_b Import show expression: \in_a Import show expression: \trigger Import show expression: \gate_y Import show expression: \gold_y Solving problem with 945 variables and 2505 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ End of script. Logfile hash: 46f1f38ced CPU: user 0.03s system 0.01s, MEM: 19.07 MB total, 9.94 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 80% 1x sat (0 sec), 12% 1x techmap (0 sec), ... mv equiv.log_new equiv.log ../../yosys -l axis_test.log_new axis_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2018 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.8 (git sha1 5706e90) -- Executing script file `axis_test.ys' -- 1. Executing Verilog-2005 frontend. Parsing SystemVerilog input from `axis_master.v' to AST representation. Generating RTLIL representation for module `\axis_master'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend. Parsing SystemVerilog input from `axis_test.v' to AST representation. Generating RTLIL representation for module `\axis_test'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master 3.2. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master Removed 0 unused modules. Module axis_test directly or indirectly contains $assert cells -> setting "keep" attribute. Mapping positional arguments of cell axis_test.uut (axis_master). 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\axis_test.$proc$axis_test.v:22$98'. Set init value: $formal$axis_test.v:22$23_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:21$96'. Set init value: $formal$axis_test.v:21$22_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:20$94'. Set init value: $formal$axis_test.v:20$21_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:19$92'. Set init value: $formal$axis_test.v:19$20_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:18$90'. Set init value: $formal$axis_test.v:18$19_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:17$88'. Set init value: $formal$axis_test.v:17$18_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:16$86'. Set init value: $formal$axis_test.v:16$17_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:15$84'. Set init value: $formal$axis_test.v:15$16_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:14$82'. Set init value: $formal$axis_test.v:14$15_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:13$80'. Set init value: $formal$axis_test.v:13$14_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:7$79'. Set init value: \aresetn = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:6$78'. Set init value: \counter = 0 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\axis_test.$proc$axis_test.v:22$98'. 1/1: $0$formal$axis_test.v:22$23_EN[0:0]$99 Creating decoders for process `\axis_test.$proc$axis_test.v:21$96'. 1/1: $0$formal$axis_test.v:21$22_EN[0:0]$97 Creating decoders for process `\axis_test.$proc$axis_test.v:20$94'. 1/1: $0$formal$axis_test.v:20$21_EN[0:0]$95 Creating decoders for process `\axis_test.$proc$axis_test.v:19$92'. 1/1: $0$formal$axis_test.v:19$20_EN[0:0]$93 Creating decoders for process `\axis_test.$proc$axis_test.v:18$90'. 1/1: $0$formal$axis_test.v:18$19_EN[0:0]$91 Creating decoders for process `\axis_test.$proc$axis_test.v:17$88'. 1/1: $0$formal$axis_test.v:17$18_EN[0:0]$89 Creating decoders for process `\axis_test.$proc$axis_test.v:16$86'. 1/1: $0$formal$axis_test.v:16$17_EN[0:0]$87 Creating decoders for process `\axis_test.$proc$axis_test.v:15$84'. 1/1: $0$formal$axis_test.v:15$16_EN[0:0]$85 Creating decoders for process `\axis_test.$proc$axis_test.v:14$82'. 1/1: $0$formal$axis_test.v:14$15_EN[0:0]$83 Creating decoders for process `\axis_test.$proc$axis_test.v:13$80'. 1/1: $0$formal$axis_test.v:13$14_EN[0:0]$81 Creating decoders for process `\axis_test.$proc$axis_test.v:7$79'. 1/1: $1\aresetn[0:0] Creating decoders for process `\axis_test.$proc$axis_test.v:6$78'. 1/1: $1\counter[31:0] Creating decoders for process `\axis_test.$proc$axis_test.v:11$24'. 1/22: $0\aresetn[0:0] 2/22: $0$formal$axis_test.v:13$14_EN[0:0]$26 3/22: $0$formal$axis_test.v:13$14_CHECK[0:0]$25 4/22: $0$formal$axis_test.v:14$15_EN[0:0]$28 5/22: $0$formal$axis_test.v:14$15_CHECK[0:0]$27 6/22: $0$formal$axis_test.v:15$16_EN[0:0]$30 7/22: $0$formal$axis_test.v:15$16_CHECK[0:0]$29 8/22: $0$formal$axis_test.v:16$17_EN[0:0]$32 9/22: $0$formal$axis_test.v:16$17_CHECK[0:0]$31 10/22: $0$formal$axis_test.v:17$18_EN[0:0]$34 11/22: $0$formal$axis_test.v:17$18_CHECK[0:0]$33 12/22: $0$formal$axis_test.v:18$19_EN[0:0]$36 13/22: $0$formal$axis_test.v:18$19_CHECK[0:0]$35 14/22: $0$formal$axis_test.v:19$20_EN[0:0]$38 15/22: $0$formal$axis_test.v:19$20_CHECK[0:0]$37 16/22: $0$formal$axis_test.v:20$21_EN[0:0]$40 17/22: $0$formal$axis_test.v:20$21_CHECK[0:0]$39 18/22: $0$formal$axis_test.v:21$22_EN[0:0]$42 19/22: $0$formal$axis_test.v:21$22_CHECK[0:0]$41 20/22: $0$formal$axis_test.v:22$23_EN[0:0]$44 21/22: $0$formal$axis_test.v:22$23_CHECK[0:0]$43 22/22: $0\counter[31:0] Creating decoders for process `\axis_master.$proc$axis_master.v:7$1'. 1/5: $2\state[31:0] 2/5: $1\state[31:0] 3/5: $0\state[31:0] 4/5: $0\tdata[7:0] 5/5: $0\tvalid[0:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\axis_test.\aresetn' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$253' with positive edge clock. Creating register for signal `\axis_test.\counter' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$254' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$255' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$256' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$257' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$258' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$259' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$260' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$261' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$262' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$263' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$264' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$265' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$266' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$267' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$268' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$269' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$270' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$271' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$272' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$273' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$274' with positive edge clock. Creating register for signal `\axis_master.\tvalid' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$275' with positive edge clock. Creating register for signal `\axis_master.\tdata' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$276' with positive edge clock. Creating register for signal `\axis_master.\state' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$277' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `axis_test.$proc$axis_test.v:22$98'. Removing empty process `axis_test.$proc$axis_test.v:21$96'. Removing empty process `axis_test.$proc$axis_test.v:20$94'. Removing empty process `axis_test.$proc$axis_test.v:19$92'. Removing empty process `axis_test.$proc$axis_test.v:18$90'. Removing empty process `axis_test.$proc$axis_test.v:17$88'. Removing empty process `axis_test.$proc$axis_test.v:16$86'. Removing empty process `axis_test.$proc$axis_test.v:15$84'. Removing empty process `axis_test.$proc$axis_test.v:14$82'. Removing empty process `axis_test.$proc$axis_test.v:13$80'. Removing empty process `axis_test.$proc$axis_test.v:7$79'. Removing empty process `axis_test.$proc$axis_test.v:6$78'. Found and cleaned up 11 empty switches in `\axis_test.$proc$axis_test.v:11$24'. Removing empty process `axis_test.$proc$axis_test.v:11$24'. Found and cleaned up 4 empty switches in `\axis_master.$proc$axis_master.v:7$1'. Removing empty process `axis_master.$proc$axis_master.v:7$1'. Cleaned up 15 empty switches. 5. Executing FLATTEN pass (flatten design). Mapping axis_test.uut using axis_master. No more expansions possible. Deleting now unused module axis_master. Removed 0 unused cells and 90 unused wires. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up time step 1: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import set-constraint from init attribute: $formal$axis_test.v:13$14_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:14$15_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:15$16_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:16$17_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:17$18_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:18$19_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:19$20_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:20$21_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:21$22_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:22$23_EN = 1'0 Import set-constraint from init attribute: \aresetn = 1'0 Import set-constraint from init attribute: \counter = 0 Final init constraint equation: { \counter \aresetn $formal$axis_test.v:22$23_EN $formal$axis_test.v:21$22_EN $formal$axis_test.v:20$21_EN $formal$axis_test.v:19$20_EN $formal$axis_test.v:18$19_EN $formal$axis_test.v:17$18_EN $formal$axis_test.v:16$17_EN $formal$axis_test.v:15$16_EN $formal$axis_test.v:14$15_EN $formal$axis_test.v:13$14_EN } = 43'0000000000000000000000000000000000000000000 Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 2: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 3: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 4: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 5: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 6: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 7: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 8: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 9: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 10: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 11: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 12: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 13: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 14: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 15: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 16: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 17: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 18: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 19: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 20: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 21: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 22: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 23: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 24: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 25: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 26: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 27: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 28: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 29: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 30: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 31: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 32: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 33: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 34: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 35: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 36: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 37: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 38: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 39: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 40: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 41: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 42: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 43: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 44: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 45: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 46: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 47: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 48: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 49: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 50: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Solving problem with 159344 variables and 442126 clauses.. SAT proof finished - model found: FAIL! ______ ___ ___ _ _ _ _ (_____ \ / __) / __) (_) | | | | _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | | | ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_| | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ |_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_| Time Signal Name Dec Hex Bin ---- ------------------------------------ ----------- --------- ----------------------------------- init $formal$axis_test.v:13$14_CHECK 0 0 0 init $formal$axis_test.v:13$14_EN 0 0 0 init $formal$axis_test.v:14$15_CHECK 0 0 0 init $formal$axis_test.v:14$15_EN 0 0 0 init $formal$axis_test.v:15$16_CHECK 0 0 0 init $formal$axis_test.v:15$16_EN 0 0 0 init $formal$axis_test.v:16$17_CHECK 0 0 0 init $formal$axis_test.v:16$17_EN 0 0 0 init $formal$axis_test.v:17$18_CHECK 0 0 0 init $formal$axis_test.v:17$18_EN 0 0 0 init $formal$axis_test.v:18$19_CHECK 0 0 0 init $formal$axis_test.v:18$19_EN 0 0 0 init $formal$axis_test.v:19$20_CHECK 0 0 0 init $formal$axis_test.v:19$20_EN 0 0 0 init $formal$axis_test.v:20$21_CHECK 0 0 0 init $formal$axis_test.v:20$21_EN 0 0 0 init $formal$axis_test.v:21$22_CHECK 0 0 0 init $formal$axis_test.v:21$22_EN 0 0 0 init $formal$axis_test.v:22$23_CHECK 0 0 0 init $formal$axis_test.v:22$23_EN 0 0 0 init \aresetn 0 0 0 init \counter 0 0 00000000000000000000000000000000 init \uut.state 0 0 00000000000000000000000000000000 init \uut.tdata 184 b8 10111000 init \uut.tvalid 1 1 1 End of script. Logfile hash: 531cf11786 CPU: user 2.79s system 0.13s, MEM: 122.63 MB total, 112.42 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 98% 1x sat (2 sec), 0% 3x read_verilog (0 sec), ... mv axis_test.log_new axis_test.log make[3]: Leaving directory '/build/yosys-0.8/manual/PRESENTATION_ExOth' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20181017163613Z)#' PRESENTATION_ExOth/scrambler_p01.pdf PRESENTATION_ExOth/scrambler_p02.pdf + make -C PRESENTATION_Prog make[3]: Entering directory '/build/yosys-0.8/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys-config --exec --cxx --cxxflags -I../.. --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs my_cmd.cc: In member function 'virtual void {anonymous}::MyPass::execute(std::vector >, Yosys::RTLIL::Design*)': my_cmd.cc:17:17: warning: format '%zd' expects argument of type 'signed size_t', but argument 3 has type 'int' [-Wformat=] log(" %s (%zd wires, %zd cells)\n", log_id(mod), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GetSize(mod->wires()), GetSize(mod->cells())); ~~~~~~~~~~~~~~~~~~~~~ my_cmd.cc:17:17: warning: format '%zd' expects argument of type 'signed size_t', but argument 4 has type 'int' [-Wformat=] ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v -- Parsing `absval_ref.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `absval_ref.v' to AST representation. Generating RTLIL representation for module `\absval_ref'. Successfully finished Verilog frontend. -- Running command `my_cmd foo bar' -- Arguments to my_cmd: my_cmd foo bar Modules in current design: absval_ref (4 wires, 2 cells) End of script. Logfile hash: 835f6eeb34 CPU: user 0.01s system 0.00s, MEM: 17.93 MB total, 8.16 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 96% 1x read_verilog (0 sec), 3% 1x my_cmd (0 sec) mv test0.log_new test0.log ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v -- Parsing `absval_ref.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `absval_ref.v' to AST representation. Generating RTLIL representation for module `\absval_ref'. Successfully finished Verilog frontend. -- Running command `clean; test1; dump' -- Removed 0 unused cells and 1 unused wires. Name of this module: absval autoidx 6 module \absval wire width 4 $auto$my_cmd.cc:41:execute$3 wire width 4 output 2 \y wire width 4 input 1 \a cell $mux $auto$my_cmd.cc:43:execute$5 parameter \WIDTH 4 connect \Y \y connect \S \a [3] connect \B $auto$my_cmd.cc:41:execute$3 connect \A \a end cell $neg $auto$my_cmd.cc:42:execute$4 parameter \Y_WIDTH 4 parameter \A_WIDTH 4 parameter \A_SIGNED 1 connect \Y $auto$my_cmd.cc:41:execute$3 connect \A \a end end attribute \src "absval_ref.v:1" module \absval_ref attribute \src "absval_ref.v:2" wire width 4 $neg$absval_ref.v:2$1_Y attribute \src "absval_ref.v:1" wire width 4 input 1 \a attribute \src "absval_ref.v:1" wire width 4 output 2 \y attribute \src "absval_ref.v:2" cell $neg $neg$absval_ref.v:2$1 parameter \A_SIGNED 1 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \a connect \Y $neg$absval_ref.v:2$1_Y end attribute \src "absval_ref.v:2" cell $mux $ternary$absval_ref.v:2$2 parameter \WIDTH 4 connect \A \a connect \B $neg$absval_ref.v:2$1_Y connect \S \a [3] connect \Y \y end end End of script. Logfile hash: 32f400d5d5 CPU: user 0.00s system 0.01s, MEM: 17.93 MB total, 8.38 MB resident Yosys 0.8 (git sha1 5706e90) Time spent: 59% 1x clean (0 sec), 30% 1x read_verilog (0 sec), ... mv test1.log_new test1.log ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v -- Parsing `sigmap_test.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `sigmap_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. -- Running command `test2' -- 0 0 0 1 1 1 Mapped signal x: \a 2. Doing important stuff! Log message #0. Log message #1. Log message #2. Log message #3. Log message #4. Log message #5. Log message #6. Log message #7. Log message #8. Log message #9. End of script. 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Rerun to get cross-references right. ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/lm /lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.enc}{/usr/share/texmf /fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-ts1.enc}{ /usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}< /usr/share/texlive/texmf-dist/fonts/type1/public/amsfonts/cm/cmmi9.pfb> Output written on manual.pdf (186 pages, 1628003 bytes). Transcript written on manual.log. + false + bibtex manual.aux This is BibTeX, Version 0.99d (TeX Live 2019/dev/Debian) The top-level auxiliary file: manual.aux A level-1 auxiliary file: CHAPTER_Intro.aux A level-1 auxiliary file: CHAPTER_Basics.aux A level-1 auxiliary file: CHAPTER_Approach.aux A level-1 auxiliary file: CHAPTER_Overview.aux A level-1 auxiliary file: CHAPTER_CellLib.aux A level-1 auxiliary file: CHAPTER_Prog.aux A level-1 auxiliary file: CHAPTER_Verilog.aux A level-1 auxiliary file: CHAPTER_Optimize.aux A level-1 auxiliary file: CHAPTER_Techmap.aux A level-1 auxiliary file: CHAPTER_Auxlibs.aux A level-1 auxiliary file: CHAPTER_Auxprogs.aux A level-1 auxiliary file: CHAPTER_Appnotes.aux The style file: alphadin.bst Database file #1: literature.bib Warning--to sort, need author or key in Verilog2005 Warning--to sort, need author or key in VerilogSynth Warning--to sort, need author or key in VHDL Warning--to sort, need author or key in VHDLSynth Warning--to sort, need author or key in IP-XACT Warning--empty pages in Cummings00 Warning--empty pages in intersynthFdlBookChapter Warning--empty author in IP-XACT Warning--empty author in VerilogSynth Warning--empty author in Verilog2005 Warning--empty author in VHDLSynth Warning--empty author in VHDL (There were 12 warnings) + bibtex weblink.aux This is BibTeX, Version 0.99d (TeX Live 2019/dev/Debian) The top-level auxiliary file: weblink.aux The style file: abbrv.bst Database file #1: weblinks.bib Warning--to sort, need author or key in C_to_Verilog Warning--to sort, need author or key in LegUp Warning--to sort, need author or key in flex Warning--to sort, need author or key in bison Warning--to sort, need author or key in LibertyFormat Warning--to sort, need author or key in OR1200 Warning--to sort, need author or key in openMSP430 Warning--to sort, need author or key in i2cmaster Warning--to sort, need author or key in k68 Warning--to sort, need author or key in Formality (There were 10 warnings) + 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LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/ i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.enc}{/usr/share/texmf /fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-ts1.enc}{ /usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}< /usr/share/texlive/texmf-dist/fonts/type1/public/amsfonts/cm/cmmi9.pfb> Output written on manual.pdf (196 pages, 1711479 bytes). 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(./command-reference-manual.tex [72] [73] [74] [75] [76] [77] [78] [79] [80] Overfull \hbox (32.63736pt too wide) in paragraph at lines 507--507 []\T1/lmr/bx/n/14.4 coolrunner2_sop -- break $sop cells into ANDTER-M/ORTERM [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [91] [92] [93] [94] [95] [96] [97] [98] [99] [100] [101] [102] [103] [104] [105] [106] [107] [108] [109] Overfull \hbox (10.39832pt too wide) in paragraph at lines 1978--1978 []\T1/lmr/bx/n/14.4 opt_demorgan -- Op-ti-mize re-duc-tions with De-Mor-gan equ iv- [110] [111] [112] [113] [114] [115] [116] [117] [118] [119] [120] [121] [122] [123] [124] [125] [126] [127] [128] [129] [130] [131] [132] [133] [134] [135] [136] [137] [138] Overfull \hbox (1.04004pt too wide) in paragraph at lines 3518--3518 []\T1/lmr/bx/n/14.4 synth_achronix -- syn-the-sis for Acrhonix Speed-ster22i FP - [139] [140] Overfull \hbox (163.0737pt too wide) in paragraph at lines 3656--3657 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][][][][][] [141] [142] [143] [144] [145] [146] [147] Overfull \hbox (273.47517pt too wide) in paragraph at lines 3994--3995 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][][][][][] [148] [149] [150] [151] [152] [153] [154] [155] [156] [157] [158] [159] [160] [161] [162] [163] [164] [165] [166] [167] [168] [169] [170] [171] [172] [173] [174] [175]) [176] (./CHAPTER_Appnotes.tex Appendix D. [177] [178 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [179 <./APPNOTE_010_Verilog_to_ BLIF.pdf>] [180 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [181 <./APPNOTE_011_Design _Investigation.pdf>] [182 <./APPNOTE_011_Design_Investigation.pdf>] [183 <./APP NOTE_011_Design_Investigation.pdf>] [184 <./APPNOTE_011_Design_Investigation.pd f>] [185 <./APPNOTE_011_Design_Investigation.pdf>] [186 <./APPNOTE_011_Design_I nvestigation.pdf>] [187 <./APPNOTE_011_Design_Investigation.pdf>] [188 <./APPNO TE_011_Design_Investigation.pdf>] [189 <./APPNOTE_011_Design_Investigation.pdf> ] [190 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [191 <./APPNOTE_012_Verilog_to_BTOR .pdf>] [192 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [193 <./APPNOTE_012_Verilog_to _BTOR.pdf>]) (./manual.bbl [194]) (./weblink.bbl [195]) [196] (./manual.aux (./CHAPTER_Intro.aux) (./CHAPTER_Basics.aux) (./CHAPTER_Approach.aux) (./CHAPTER_Overview.aux) (./CHAPTER_CellLib.aux) (./CHAPTER_Prog.aux) (./CHAPTER_Verilog.aux) (./CHAPTER_Optimize.aux) (./CHAPTER_Techmap.aux) (./CHAPTER_Auxlibs.aux) (./CHAPTER_Auxprogs.aux) (./CHAPTER_Appnotes.aux)) LaTeX Font Warning: Some font shapes were not available, defaults substituted. LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/ i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.enc}{/usr/share/texmf /fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-ts1.enc}{ /usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}< /usr/share/texlive/texmf-dist/fonts/type1/public/amsfonts/cm/cmmi9.pfb> Output written on manual.pdf (196 pages, 1711479 bytes). Transcript written on manual.log. + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg weblink.blg + cmp autoloop.old autoloop.new + rm -f autoloop.old + rm -f autoloop.new + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' manual.pdf + mv -f manual.pdf.without_pdf_id manual.pdf make[2]: Leaving directory '/build/yosys-0.8' make[1]: Leaving directory '/build/yosys-0.8' dh_auto_test make -j15 test make[1]: Entering directory '/build/yosys-0.8' [Makefile.conf] CONFIG := gcc cd tests/simple && bash run-test.sh "" make[2]: Entering directory '/build/yosys-0.8/tests/simple' Test: always02 -> ok Test: constpower -> ok Test: always01 -> ok Test: forgen01 -> ok Test: carryadd -> ok Test: always03 -> ok Test: arrays01 -> ok Test: arraycells -> ok Test: forgen02 -> ok Test: fiedler-cooley -> ok Test: hierarchy -> ok Test: aes_kexp128 -> ok Test: fsm -> ok Test: graphtest -> ok Test: omsp_dbg_uart -> ok Test: i2c_master_tests -> ok Test: macros -> ok Test: hierdefparam -> ok Test: generate -> ok Test: loops -> ok Test: dff_different_styles -> ok Test: realexpr -> ok Test: mem_arst -> ok Test: muxtree -> ok Test: constmuldivmod -> ok Test: specify -> ok Test: paramods -> ok Test: signedexpr -> ok Test: scopes -> ok Test: multiplier -> ok Test: undef_eqx_nex -> ok Test: process -> ok Test: mem2reg -> ok Test: usb_phy_tests -> ok Test: subbytes -> ok Test: repwhile -> ok Test: values -> ok Test: task_func -> ok Test: vloghammer -> ok Test: wreduce -> ok Test: sincos -> ok Test: partsel -> ok Test: rotate -> ok Test: operators -> ok Test: memory -> ok make[2]: Leaving directory '/build/yosys-0.8/tests/simple' cd tests/hana && bash run-test.sh "" make[2]: Entering directory '/build/yosys-0.8/tests/hana' Test: test_simulation_buffer -> ok Test: test_simulation_seq -> ok Test: test_parse2synthtrans -> ok Test: test_simulation_nor -> ok Test: test_simulation_nand -> ok Test: test_simulation_or -> ok Test: test_simulation_and -> ok Test: test_simulation_vlib -> ok Test: test_parser -> ok Test: test_simulation_sop -> ok Test: test_simulation_inc -> ok Test: test_simulation_xnor -> ok Test: test_simulation_xor -> ok Test: test_simulation_always -> ok Test: test_simulation_mux -> ok Test: test_simulation_techmap -> ok Test: test_simulation_decoder -> ok Test: test_simulation_techmap_tech -> ok Test: test_simulation_shifter -> ok Test: test_intermout -> ok make[2]: Leaving directory '/build/yosys-0.8/tests/hana' cd tests/asicworld && bash run-test.sh "" make[2]: Entering directory '/build/yosys-0.8/tests/asicworld' Test: code_hdl_models_dff_async_reset -> ok Test: code_hdl_models_d_latch_gates -> ok Test: code_hdl_models_decoder_2to4_gates -> ok Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_encoder_4to2_gates -> ok Test: code_hdl_models_dff_sync_reset -> ok Test: code_hdl_models_clk_div -> ok Test: code_hdl_models_decoder_using_assign -> ok Test: code_hdl_models_GrayCounter -> ok Test: code_hdl_models_arbiter -> ok Test: code_hdl_models_encoder_using_case -> ok Test: code_hdl_models_decoder_using_case -> ok Test: code_hdl_models_clk_div_45 -> ok Test: code_hdl_models_full_adder_gates -> ok Test: code_hdl_models_encoder_using_if -> ok Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_mux21_switch -> ok Test: code_hdl_models_full_subtracter_gates -> ok Test: code_hdl_models_misc1 -> ok Test: code_hdl_models_mux_2to1_gates -> ok Test: code_hdl_models_lfsr -> ok Test: code_hdl_models_gray_counter -> ok Test: code_hdl_models_nand_switch -> ok Test: code_hdl_models_lfsr_updown -> ok Test: code_hdl_models_mux_using_case -> ok Test: code_hdl_models_mux_using_if -> ok Test: code_hdl_models_mux_using_assign -> ok Test: code_hdl_models_parity_using_assign -> ok Test: code_hdl_models_one_hot_cnt -> ok Test: code_hdl_models_parity_using_bitwise -> ok Test: code_hdl_models_parity_using_function -> ok Test: code_hdl_models_t_gate_switch -> ok Test: code_hdl_models_pri_encoder_using_assign -> ok Test: code_hdl_models_parallel_crc -> ok Test: code_hdl_models_tff_async_reset -> ok Test: code_tidbits_asyn_reset -> ok Test: code_hdl_models_rom_using_case -> ok Test: code_hdl_models_serial_crc -> ok Test: code_tidbits_blocking -> ok Test: code_hdl_models_tff_sync_reset -> ok Test: code_hdl_models_up_counter -> ok Test: code_hdl_models_up_counter_load -> ok Test: code_hdl_models_up_down_counter -> ok Test: code_tidbits_fsm_using_always -> ok Test: code_tidbits_reg_seq_example -> ok Test: code_tidbits_nonblocking -> ok Test: code_tidbits_reg_combo_example -> ok Test: code_verilog_tutorial_always_example -> ok Test: code_tidbits_fsm_using_function -> ok Test: code_tidbits_wire_example -> ok Test: code_tidbits_syn_reset -> ok Test: code_verilog_tutorial_bus_con -> ok Test: code_tidbits_fsm_using_single_always -> ok Test: code_verilog_tutorial_addbit -> ok Test: code_verilog_tutorial_comment -> ok Test: code_verilog_tutorial_counter -> ok Test: code_verilog_tutorial_escape_id -> ok Test: code_verilog_tutorial_d_ff -> ok Test: code_specman_switch_fabric -> ok Test: code_verilog_tutorial_decoder_always -> ok Test: code_verilog_tutorial_decoder -> ok Test: code_verilog_tutorial_if_else -> ok Test: code_verilog_tutorial_first_counter -> ok Test: code_verilog_tutorial_multiply -> ok Test: code_verilog_tutorial_good_code -> ok Test: code_verilog_tutorial_n_out_primitive -> ok Test: code_verilog_tutorial_flip_flop -> ok Test: code_verilog_tutorial_parallel_if -> ok Test: code_verilog_tutorial_explicit -> ok Test: code_verilog_tutorial_fsm_full -> ok Test: code_hdl_models_uart -> ok Test: code_verilog_tutorial_simple_function -> ok Test: code_verilog_tutorial_task_global -> ok Test: code_verilog_tutorial_mux_21 -> ok Test: code_verilog_tutorial_simple_if -> ok Test: code_verilog_tutorial_v2k_reg -> ok Test: code_verilog_tutorial_parity -> ok Test: code_verilog_tutorial_which_clock -> ok Test: code_verilog_tutorial_tri_buf -> ok Test: code_hdl_models_cam -> ok make[2]: Leaving directory '/build/yosys-0.8/tests/asicworld' #+cd tests/realmath && bash run-test.sh "" cd tests/share && bash run-test.sh "" generating tests.. running tests.. [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] cd tests/fsm && bash run-test.sh "" generating tests.. running tests.. make[2]: Entering directory '/build/yosys-0.8/tests/fsm' [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14]K[15]K[16]K[17]K[18]K[19]K[20]K[21]K[22]K[23]K[24]K[25]K[26]K[27]K[28]K[29]K[30]K[31]K[32]K[33]K[34]K[35]K[36]K[37]K[38]K[39]K[40]K[41]K[42]K[43]K[44]K[45]K[46]K[47]K[48]K[49]K[50]K[51]K[52]K[53]K[54]K[55]K[56]K[57]K[58]K[59]K[60]K[61]K[62]K[63]K[64]K[65]K[66]K[67]K[68]K[69]K[70]K[71]K[72]KK[73][74]K[75]K[76]K[77]K[78]K[79]K[80]K[81]K[82]T[83]K[84]K[85]K[86]K[87]K[88]K[89]K[90]K[91]K[92]K[93]K[94]KK[95][96]K[97]K[98]K[99]KKKKKKKKKKKKTKK make[2]: Leaving directory '/build/yosys-0.8/tests/fsm' cd tests/techmap && bash run-test.sh Running mem_simple_4x1_runtest.sh.. cd tests/memories && bash run-test.sh "" Test: amber23_sram_byte_en -> ok Test: implicit_en -> ok Test: no_implicit_en -> ok Test: shared_ports -> ok Test: simple_sram_byte_en -> ok Testing expectations for amber23_sram_byte_en.v .. ok. Testing expectations for implicit_en.v .. ok. Testing expectations for no_implicit_en.v .. ok. Testing expectations for shared_ports.v .. ok. Testing expectations for simple_sram_byte_en.v .. ok. cd tests/bram && bash run-test.sh "" generating tests.. PRNG seed: 897171 running tests.. make[2]: Entering directory '/build/yosys-0.8/tests/bram' Passed memory_bram test 00_01. Passed memory_bram test 01_00. Passed memory_bram test 02_03. Passed memory_bram test 00_04. Passed memory_bram test 02_01. Passed memory_bram test 02_00. Passed memory_bram test 00_02. Passed memory_bram test 03_01. Passed memory_bram test 03_00. Passed memory_bram test 00_03. Passed memory_bram test 03_02. Passed memory_bram test 01_02. Passed memory_bram test 04_01. Passed memory_bram test 02_04. Passed memory_bram test 04_00. Passed memory_bram test 04_03. Passed memory_bram test 03_04. Passed memory_bram test 01_03. Passed memory_bram test 04_02. Passed memory_bram test 01_04. make[2]: Leaving directory '/build/yosys-0.8/tests/bram' cd tests/various && bash run-test.sh Running constmsk_test.ys.. constmsk_testmap.v:45: Warning: Range select out of bounds on signal `\tmp': Setting 1 MSB bits to undef. Running muxcover.ys.. Warning: Yosys has only limited support for tri-state logic at the moment. (/build/yosys-0.8/share/simcells.v:437) Running reg_wire_error.ys.. Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26. Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29. Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35. Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62. Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69. Warning: Blocking assignment to memory in line reg_wire_error.sv:61 is handled like a non-blocking assignment. Warning: Blocking assignment to memory in line reg_wire_error.sv:63 is handled like a non-blocking assignment. Running submod_extract.ys.. cd tests/sat && bash run-test.sh Running asserts.ys.. Running asserts_seq.ys.. Running counters.ys.. Running expose_dff.ys.. Running initval.ys.. Warning: ignoring initial value on non-register: \bar [1:0] Running share.ys.. Running sizebits.ys.. Running splice.ys.. Passed "make test". make[1]: Leaving directory '/build/yosys-0.8' create-stamp debian/debhelper-build-stamp fakeroot debian/rules binary PREFIX=/usr dh binary --with=python3 dh_testroot dh_prep debian/rules override_dh_auto_install make[1]: Entering directory '/build/yosys-0.8' dh_auto_install make -j15 install DESTDIR=/build/yosys-0.8/debian/tmp AM_UPDATE_INFO_DIR=no "INSTALL=install --strip-program=true" make[2]: Entering directory '/build/yosys-0.8' [Makefile.conf] CONFIG := gcc mkdir -p /build/yosys-0.8/debian/tmp/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc /build/yosys-0.8/debian/tmp/usr/bin mkdir -p /build/yosys-0.8/debian/tmp/usr/share/yosys cp -r share/. /build/yosys-0.8/debian/tmp/usr/share/yosys/. make[2]: Leaving directory '/build/yosys-0.8' chmod a-x debian/tmp/usr/share/yosys/achronix/speedster22i/cells*.v make[1]: Leaving directory '/build/yosys-0.8' debian/rules override_dh_install make[1]: Entering directory '/build/yosys-0.8' dh_install --fail-missing dh_install: Please use dh_missing --list-missing/--fail-missing instead dh_install: This feature will be removed in compat 12. make[1]: Leaving directory '/build/yosys-0.8' dh_installdocs dh_installchangelogs debian/rules override_dh_installman make[1]: Entering directory '/build/yosys-0.8' cd debian/man ; CHANGELOG_DATE="17 October 2018" ./genmanpages.sh dh_installman make[1]: Leaving directory '/build/yosys-0.8' dh_python3 I: dh_python3 tools:114: replacing shebang in debian/yosys/usr/bin/yosys-smtbmc dh_lintian dh_perl dh_link dh_strip_nondeterminism debian/rules override_dh_compress make[1]: Entering directory '/build/yosys-0.8' dh_compress --exclude=.pdf make[1]: Leaving directory '/build/yosys-0.8' dh_fixperms dh_missing dh_strip dh_makeshlibs dh_shlibdeps dh_installdeb dh_gencontrol dpkg-gencontrol: warning: Depends field of package yosys-dev: substitution variable ${shlibs:Depends} used, but is not defined dpkg-gencontrol: warning: Depends field of package yosys-dev: substitution variable ${python3:Depends} used, but is not defined dh_md5sums dh_builddeb dpkg-deb: building package 'yosys-doc' in '../yosys-doc_0.8-1_all.deb'. dpkg-deb: building package 'yosys-dbgsym' in '../yosys-dbgsym_0.8-1_amd64.deb'. dpkg-deb: building package 'yosys-dev' in '../yosys-dev_0.8-1_amd64.deb'. dpkg-deb: building package 'yosys' in '../yosys_0.8-1_amd64.deb'. dpkg-genbuildinfo --build=binary dpkg-genchanges --build=binary >../yosys_0.8-1_amd64.changes dpkg-genchanges: info: binary-only upload (no source code included) dpkg-source --after-build . dpkg-buildpackage: info: binary-only upload (no source included) dpkg-genchanges: info: including full source code in upload I: copying local configuration I: unmounting dev/ptmx filesystem I: unmounting dev/pts filesystem I: unmounting dev/shm filesystem I: unmounting proc filesystem I: unmounting sys filesystem I: cleaning the build env I: removing directory /srv/workspace/pbuilder/1299452 and its subdirectories I: Current time: Fri Dec 17 19:17:58 -12 2021 I: pbuilder-time-stamp: 1639811878 Sat Dec 18 07:18:01 UTC 2021 I: 1st build successful. Starting 2nd build on remote node ionos15-amd64.debian.net. Sat Dec 18 07:18:01 UTC 2021 I: Preparing to do remote build '2' on ionos15-amd64.debian.net. Sat Dec 18 08:12:24 UTC 2021 I: Deleting $TMPDIR on ionos15-amd64.debian.net. Sat Dec 18 08:12:25 UTC 2021 I: yosys_0.8-1_amd64.changes: Format: 1.8 Date: Wed, 17 Oct 2018 18:36:13 +0200 Source: yosys Binary: yosys yosys-dbgsym yosys-dev yosys-doc Architecture: amd64 all Version: 0.8-1 Distribution: unstable Urgency: medium Maintainer: Debian Science Maintainers Changed-By: Ruben Undheim Description: yosys - Framework for Verilog RTL synthesis yosys-dev - Framework for Verilog RTL synthesis (development files) yosys-doc - Documentation for Yosys Changes: yosys (0.8-1) unstable; urgency=medium . * New upstream release * debian/control: - New standards version 4.2.1 - no changes * debian/copyright: - New copyright years - Some new copyright holders for certain files * debian/patches: Fix patches after importing new version * d/patches/0013-Let-dpkg-buildpackage-handle-stripping-of-binaries.patch: - Fix issue with empty -dbgsym package * debian/rules: - Enable hardening - Remove redundant '--parallel' - Override dh_auto_install and remove executable permission on some files - Delete one more file in override_dh_auto_clean * debian/yosys.1: Updated man page for new version * debian/yosys.install: Install new files * debian/yosys.lintian-overrides: - Waive a 'spelling error' which is in fact not an error. Checksums-Sha1: 30b23b44ff3ba12a7ce8fd86e9b906d7801199c4 56060252 yosys-dbgsym_0.8-1_amd64.deb dc0e577e4797db170b863eb3375a9d7b86bc72b4 58248 yosys-dev_0.8-1_amd64.deb a1e77e82a7be1e93af115b38d0c4bad98c2582c4 2446956 yosys-doc_0.8-1_all.deb 7c86d46e75521d2239c8fa4f7437a79500217837 10379 yosys_0.8-1_amd64.buildinfo da988071941e6a09d25f207c722044b615bc1399 1898288 yosys_0.8-1_amd64.deb Checksums-Sha256: 8a66d3a4895ac5d92fad84efa66b61a510e200336d961b29414daff53eecd82d 56060252 yosys-dbgsym_0.8-1_amd64.deb 0eae73c44b4a896ffddf275a66e3ec93818671a9eca2634e4ae90cdbcb63da13 58248 yosys-dev_0.8-1_amd64.deb 40311479ed560a3510dfad05047c78d82fed3e824caabb2e2771e7a8792788dc 2446956 yosys-doc_0.8-1_all.deb 321182f3db93b0e8aad23f4397c997afe0fabef96a13b9c3d4179649c7078c7e 10379 yosys_0.8-1_amd64.buildinfo 73b37a2fb2fe37c747070d8186d137c1ff928c1132b1ea154828a3387824bd1c 1898288 yosys_0.8-1_amd64.deb Files: e298dbf9bc575c6c8e27a75c27f60489 56060252 debug optional yosys-dbgsym_0.8-1_amd64.deb 7c8c563b1951861905d8c09c535c9b3b 58248 electronics optional yosys-dev_0.8-1_amd64.deb 9349b0010b844644527edf1d46109eec 2446956 doc optional yosys-doc_0.8-1_all.deb 2a5d36a0f2840ba88705cb9676c391cf 10379 electronics optional yosys_0.8-1_amd64.buildinfo 28fc4d4f3d23d78ca49965c60eba7816 1898288 electronics optional yosys_0.8-1_amd64.deb Sat Dec 18 08:12:26 UTC 2021 I: will be used to compare the two builds: # Profiling output for: /usr/bin/diffoscope --html /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/yosys_0.8-1.diffoscope.html --text /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/yosys_0.8-1.diffoscope.txt --json /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/yosys_0.8-1.diffoscope.json --profile=- /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/b1/yosys_0.8-1_amd64.changes /srv/reproducible-results/rbuild-debian/tmp.rmWec8ynN1/b2/yosys_0.8-1_amd64.changes ## command (total time: 0.000s) 0.000s 1 call cmp (internal) ## has_same_content_as (total time: 0.000s) 0.000s 1 call abc.DotChangesFile ## main (total time: 2.322s) 2.322s 2 calls outputs 0.000s 1 call cleanup ## recognizes (total time: 1.762s) 1.762s 10 calls diffoscope.comparators.binary.FilesystemFile 0.000s 8 calls abc.DotChangesFile ## specialize (total time: 0.000s) 0.000s 1 call specialize Sat Dec 18 08:12:29 UTC 2021 I: found no differences in the changes files, and a .buildinfo file also exists. Sat Dec 18 08:12:29 UTC 2021 I: yosys from buster built successfully and reproducibly on amd64. Sat Dec 18 08:12:39 UTC 2021 I: Submitting .buildinfo files to external archives: Sat Dec 18 08:12:39 UTC 2021 I: Submitting 12K b1/yosys_0.8-1_amd64.buildinfo.asc Sat Dec 18 08:12:40 UTC 2021 I: Submitting 12K b2/yosys_0.8-1_amd64.buildinfo.asc Sat Dec 18 08:12:41 UTC 2021 I: Done submitting .buildinfo files to http://buildinfo.debian.net/api/submit. Sat Dec 18 08:12:41 UTC 2021 I: Done submitting .buildinfo files. Sat Dec 18 08:12:41 UTC 2021 I: Removing signed yosys_0.8-1_amd64.buildinfo.asc files: removed './b1/yosys_0.8-1_amd64.buildinfo.asc' removed './b2/yosys_0.8-1_amd64.buildinfo.asc'