I: pbuilder: network access will be disabled during build I: Current time: Thu Jul 4 01:31:56 -12 2024 I: pbuilder-time-stamp: 1720099916 I: Building the build Environment I: extracting base tarball [/var/cache/pbuilder/bookworm-reproducible-base.tgz] tar: ./usr/share/doc/adduser/examples/adduser.local.conf.examples/skel: time stamp 2025-08-04 08:27:04 is 34239303.365920732 s in the future tar: ./usr/share/doc/adduser/examples/adduser.local.conf.examples/skel.other: time stamp 2025-08-04 08:27:04 is 34239303.365762061 s in the future tar: ./usr/share/doc/adduser/examples/adduser.local.conf.examples: time stamp 2025-08-04 08:27:04 is 34239303.365737383 s in the future tar: ./usr/share/doc/adduser/examples: time stamp 2025-08-04 08:27:04 is 34239303.36571495 s in the future tar: ./usr/share/doc/adduser: time stamp 2025-08-04 08:27:04 is 34239303.365693503 s in the future tar: ./usr/share/locale/ca/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.234027802 s in the future tar: ./usr/share/locale/cs/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.219963054 s in the future tar: ./usr/share/locale/da/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.20600942 s in the future tar: ./usr/share/locale/de/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.191144043 s in the future tar: ./usr/share/locale/es/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.169492993 s in the future tar: ./usr/share/locale/eu/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.166001004 s in the future tar: ./usr/share/locale/fr/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.136483278 s in the future tar: ./usr/share/locale/gl/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.131112981 s in the future tar: ./usr/share/locale/hu/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.120715148 s in the future tar: ./usr/share/locale/it/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.108409518 s in the future tar: ./usr/share/locale/ja/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.093400626 s in the future tar: ./usr/share/locale/ko/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.083918854 s in the future tar: ./usr/share/locale/nb/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.074446156 s in the future tar: ./usr/share/locale/nl/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.060170459 s in the future tar: ./usr/share/locale/pl/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.047349636 s in the future tar: ./usr/share/locale/pt/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.029693354 s in the future tar: ./usr/share/locale/pt_BR/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239303.011519715 s in the future tar: ./usr/share/locale/ru/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.967091958 s in the future tar: ./usr/share/locale/sk/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.957986876 s in the future tar: ./usr/share/locale/sv/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.927284854 s in the future tar: ./usr/share/locale/uk/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.882459966 s in the future tar: ./usr/share/locale/vi/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.854315691 s in the future tar: ./usr/share/locale/zh_CN/LC_MESSAGES: time stamp 2025-08-04 08:27:04 is 34239302.832976469 s in the future tar: ./usr/share/man/de/man5: time stamp 2025-08-04 08:27:04 is 34239302.571572763 s in the future tar: ./usr/share/man/fr/man5: time stamp 2025-08-04 08:27:04 is 34239302.565349839 s in the future tar: ./usr/share/man/man5: time stamp 2025-08-04 08:27:04 is 34239302.558094525 s in the future tar: ./usr/share/man/nl/man5: time stamp 2025-08-04 08:27:04 is 34239302.550074991 s in the future tar: ./usr/share/man/nl/man8: time stamp 2025-08-04 08:27:04 is 34239302.54930039 s in the future tar: ./usr/share/man/pt/man5: time stamp 2025-08-04 08:27:04 is 34239302.545576077 s in the future tar: ./usr/share/man/pt/man8: time stamp 2025-08-04 08:27:04 is 34239302.544792119 s in the future tar: ./usr/share/perl5/Debian: time stamp 2025-08-04 08:27:04 is 34239302.50045549 s in the future tar: ./var/lib/dpkg/info/adduser.list: time stamp 2025-08-04 08:27:04 is 34239300.340938007 s in the future tar: ./usr/sbin: time stamp 2025-08-04 08:27:04 is 34239300.061484134 s in the future tar: ./usr/share/man/man8: time stamp 2025-08-04 08:27:04 is 34239300.060108528 s in the future tar: ./usr/share/man/fr/man8: time stamp 2025-08-04 08:27:04 is 34239300.060046876 s in the future tar: ./usr/share/man/de/man8: time stamp 2025-08-04 08:27:04 is 34239300.059962929 s in the future I: copying local configuration W: --override-config is not set; not updating apt.conf Read the manpage for details. I: mounting /proc filesystem I: mounting /sys filesystem I: creating /{dev,run}/shm I: mounting /dev/pts filesystem I: redirecting /dev/ptmx to /dev/pts/ptmx I: policy-rc.d already exists I: Copying source file I: copying [yosys_0.23-6.dsc] I: copying [./yosys_0.23.orig.tar.gz] I: copying [./yosys_0.23-6.debian.tar.xz] I: Extracting source gpgv: Signature made Sat Dec 3 10:16:42 2022 -12 gpgv: using RSA key 57A1BF15B4F6F99B89EDB29FD39481AE1E79ACF7 gpgv: Can't check signature: No public key dpkg-source: warning: cannot verify inline signature for ./yosys_0.23-6.dsc: no acceptable signature found dpkg-source: info: extracting yosys in yosys-0.23 dpkg-source: info: unpacking yosys_0.23.orig.tar.gz dpkg-source: info: unpacking yosys_0.23-6.debian.tar.xz dpkg-source: info: using patch list from debian/patches/series dpkg-source: info: applying switch-to-free-font.patch dpkg-source: info: applying kfreebsd-support.patch dpkg-source: info: applying 0007-Disable-pretty-build.patch dpkg-source: info: applying 0009-Some-spelling-errors-fixed.patch dpkg-source: info: applying 0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch dpkg-source: info: applying 0010-Fix-adding-of-sys.path-in-yosys-smtbmc.patch dpkg-source: info: applying 0011-Do-not-show-g-build-flags-in-Version-string.patch dpkg-source: info: applying 0012-Skip-non-deterministic-test-causing-random-FTBFS-on-.patch dpkg-source: info: applying 0014-Set-path-to-berkeley-abc-instead-of-relative-path-to.patch dpkg-source: info: applying 0017-Support-plugin-loading-from-libdir.patch dpkg-source: info: applying 0018-Fix-blhc-CLFAGS-warning.patch dpkg-source: info: applying 0019-Fix-fstapi-mips64el-crash.patch dpkg-source: info: applying 0020-autotest-Print-log-on-error.patch I: Not using root during the build. I: Installing the build-deps I: user script /srv/workspace/pbuilder/1398977/tmp/hooks/D02_print_environment starting I: set BUILDDIR='/build' BUILDUSERGECOS='first user,first room,first work-phone,first home-phone,first other' BUILDUSERNAME='pbuilder1' BUILD_ARCH='amd64' DEBIAN_FRONTEND='noninteractive' DEB_BUILD_OPTIONS='buildinfo=+all reproducible=+all parallel=16 ' DISTRIBUTION='bookworm' HOME='/root' HOST_ARCH='amd64' IFS=' ' INVOCATION_ID='c87bb252eea44746931c749380b26da5' LANG='C' LANGUAGE='en_US:en' LC_ALL='C' MAIL='/var/mail/root' OPTIND='1' PATH='/usr/sbin:/usr/bin:/sbin:/bin:/usr/games' PBCURRENTCOMMANDLINEOPERATION='build' PBUILDER_OPERATION='build' PBUILDER_PKGDATADIR='/usr/share/pbuilder' PBUILDER_PKGLIBDIR='/usr/lib/pbuilder' PBUILDER_SYSCONFDIR='/etc' PPID='1398977' PS1='# ' PS2='> ' PS4='+ ' PWD='/' SHELL='/bin/bash' SHLVL='2' SUDO_COMMAND='/usr/bin/timeout -k 18.1h 18h /usr/bin/ionice -c 3 /usr/bin/nice /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/r-b-build.Bh2zd5r1/pbuilderrc_WYyK --distribution bookworm --hookdir /etc/pbuilder/first-build-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/bookworm-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/r-b-build.Bh2zd5r1/b1 --logfile b1/build.log yosys_0.23-6.dsc' SUDO_GID='111' SUDO_UID='106' SUDO_USER='jenkins' TERM='unknown' TZ='/usr/share/zoneinfo/Etc/GMT+12' USER='root' _='/usr/bin/systemd-run' http_proxy='http://85.184.249.68:3128' I: uname -a Linux ionos15-amd64 6.1.0-0.deb11.7-amd64 #1 SMP PREEMPT_DYNAMIC Debian 6.1.20-2~bpo11+1 (2023-04-23) x86_64 GNU/Linux I: ls -l /bin total 5632 -rwxr-xr-x 1 root root 1265648 Apr 23 2023 bash -rwxr-xr-x 3 root root 39224 Sep 18 2022 bunzip2 -rwxr-xr-x 3 root root 39224 Sep 18 2022 bzcat lrwxrwxrwx 1 root root 6 Sep 18 2022 bzcmp -> bzdiff -rwxr-xr-x 1 root root 2225 Sep 18 2022 bzdiff lrwxrwxrwx 1 root root 6 Sep 18 2022 bzegrep -> bzgrep -rwxr-xr-x 1 root root 4893 Nov 27 2021 bzexe lrwxrwxrwx 1 root root 6 Sep 18 2022 bzfgrep -> bzgrep -rwxr-xr-x 1 root root 3775 Sep 18 2022 bzgrep -rwxr-xr-x 3 root root 39224 Sep 18 2022 bzip2 -rwxr-xr-x 1 root root 14568 Sep 18 2022 bzip2recover lrwxrwxrwx 1 root root 6 Sep 18 2022 bzless -> bzmore -rwxr-xr-x 1 root root 1297 Sep 18 2022 bzmore -rwxr-xr-x 1 root root 44016 Sep 20 2022 cat -rwxr-xr-x 1 root root 68656 Sep 20 2022 chgrp -rwxr-xr-x 1 root root 64496 Sep 20 2022 chmod -rwxr-xr-x 1 root root 72752 Sep 20 2022 chown -rwxr-xr-x 1 root root 151152 Sep 20 2022 cp -rwxr-xr-x 1 root root 125640 Jan 5 2023 dash -rwxr-xr-x 1 root root 121904 Sep 20 2022 date -rwxr-xr-x 1 root root 89240 Sep 20 2022 dd -rwxr-xr-x 1 root root 102200 Sep 20 2022 df -rwxr-xr-x 1 root root 151344 Sep 20 2022 dir -rwxr-xr-x 1 root root 88656 Mar 22 2023 dmesg lrwxrwxrwx 1 root root 8 Dec 19 2022 dnsdomainname -> hostname lrwxrwxrwx 1 root root 8 Dec 19 2022 domainname -> hostname -rwxr-xr-x 1 root root 43856 Sep 20 2022 echo -rwxr-xr-x 1 root root 41 Jan 24 2023 egrep -rwxr-xr-x 1 root root 35664 Sep 20 2022 false -rwxr-xr-x 1 root root 41 Jan 24 2023 fgrep -rwxr-xr-x 1 root root 85600 Mar 22 2023 findmnt -rwsr-xr-x 1 root root 35128 Mar 22 2023 fusermount -rwxr-xr-x 1 root root 203152 Jan 24 2023 grep -rwxr-xr-x 2 root root 2346 Apr 9 2022 gunzip -rwxr-xr-x 1 root root 6447 Apr 9 2022 gzexe -rwxr-xr-x 1 root root 98136 Apr 9 2022 gzip -rwxr-xr-x 1 root root 22680 Dec 19 2022 hostname -rwxr-xr-x 1 root root 72824 Sep 20 2022 ln -rwxr-xr-x 1 root root 53024 Mar 23 2023 login -rwxr-xr-x 1 root root 151344 Sep 20 2022 ls -rwxr-xr-x 1 root root 207168 Mar 22 2023 lsblk -rwxr-xr-x 1 root root 97552 Sep 20 2022 mkdir -rwxr-xr-x 1 root root 72912 Sep 20 2022 mknod -rwxr-xr-x 1 root root 43952 Sep 20 2022 mktemp -rwxr-xr-x 1 root root 59712 Mar 22 2023 more -rwsr-xr-x 1 root root 59704 Mar 22 2023 mount -rwxr-xr-x 1 root root 18744 Mar 22 2023 mountpoint -rwxr-xr-x 1 root root 142968 Sep 20 2022 mv lrwxrwxrwx 1 root root 8 Dec 19 2022 nisdomainname -> hostname lrwxrwxrwx 1 root root 14 Apr 2 2023 pidof -> /sbin/killall5 -rwxr-xr-x 1 root root 43952 Sep 20 2022 pwd lrwxrwxrwx 1 root root 4 Apr 23 2023 rbash -> bash -rwxr-xr-x 1 root root 52112 Sep 20 2022 readlink -rwxr-xr-x 1 root root 72752 Sep 20 2022 rm -rwxr-xr-x 1 root root 56240 Sep 20 2022 rmdir -rwxr-xr-x 1 root root 27560 Nov 2 2022 run-parts -rwxr-xr-x 1 root root 126424 Jan 5 2023 sed lrwxrwxrwx 1 root root 4 Jan 5 2023 sh -> dash -rwxr-xr-x 1 root root 43888 Sep 20 2022 sleep -rwxr-xr-x 1 root root 85008 Sep 20 2022 stty -rwsr-xr-x 1 root root 72000 Mar 22 2023 su -rwxr-xr-x 1 root root 39824 Sep 20 2022 sync -rwxr-xr-x 1 root root 531984 Apr 6 2023 tar -rwxr-xr-x 1 root root 14520 Nov 2 2022 tempfile -rwxr-xr-x 1 root root 109616 Sep 20 2022 touch -rwxr-xr-x 1 root root 35664 Sep 20 2022 true -rwxr-xr-x 1 root root 14568 Mar 22 2023 ulockmgr_server -rwsr-xr-x 1 root root 35128 Mar 22 2023 umount -rwxr-xr-x 1 root root 43888 Sep 20 2022 uname -rwxr-xr-x 2 root root 2346 Apr 9 2022 uncompress -rwxr-xr-x 1 root root 151344 Sep 20 2022 vdir -rwxr-xr-x 1 root root 72024 Mar 22 2023 wdctl lrwxrwxrwx 1 root root 8 Dec 19 2022 ypdomainname -> hostname -rwxr-xr-x 1 root root 1984 Apr 9 2022 zcat -rwxr-xr-x 1 root root 1678 Apr 9 2022 zcmp -rwxr-xr-x 1 root root 6460 Apr 9 2022 zdiff -rwxr-xr-x 1 root root 29 Apr 9 2022 zegrep -rwxr-xr-x 1 root root 29 Apr 9 2022 zfgrep -rwxr-xr-x 1 root root 2081 Apr 9 2022 zforce -rwxr-xr-x 1 root root 8103 Apr 9 2022 zgrep -rwxr-xr-x 1 root root 2206 Apr 9 2022 zless -rwxr-xr-x 1 root root 1842 Apr 9 2022 zmore -rwxr-xr-x 1 root root 4577 Apr 9 2022 znew I: user script /srv/workspace/pbuilder/1398977/tmp/hooks/D02_print_environment finished -> Attempting to satisfy build-dependencies -> Creating pbuilder-satisfydepends-dummy package Package: pbuilder-satisfydepends-dummy Version: 0.invalid.0 Architecture: amd64 Maintainer: Debian Pbuilder Team Description: Dummy package to satisfy dependencies with aptitude - created by pbuilder This package was created automatically by pbuilder to satisfy the build-dependencies of the package being currently built. Depends: debhelper-compat (= 13), dh-python, tcl-dev, libreadline-dev, bison, flex, gawk, libffi-dev, pkg-config, txt2man, iverilog (>= 10.1), python3, berkeley-abc (>= 1.01+20221019git70cb339+dfsg-3), texlive-base, texlive-plain-generic, texlive-fonts-recommended, texlive-fonts-extra, texlive-latex-base, texlive-latex-extra, texlive-font-utils, texlive-science, texlive-publishers, texlive-bibtex-extra, lmodern, graphviz dpkg-deb: building package 'pbuilder-satisfydepends-dummy' in '/tmp/satisfydepends-aptitude/pbuilder-satisfydepends-dummy.deb'. Selecting previously unselected package pbuilder-satisfydepends-dummy. (Reading database ... 19591 files and directories currently installed.) Preparing to unpack .../pbuilder-satisfydepends-dummy.deb ... Unpacking pbuilder-satisfydepends-dummy (0.invalid.0) ... dpkg: pbuilder-satisfydepends-dummy: dependency problems, but configuring anyway as you requested: pbuilder-satisfydepends-dummy depends on debhelper-compat (= 13); however: Package debhelper-compat is not installed. pbuilder-satisfydepends-dummy depends on dh-python; however: Package dh-python is not installed. pbuilder-satisfydepends-dummy depends on tcl-dev; however: Package tcl-dev is not installed. pbuilder-satisfydepends-dummy depends on libreadline-dev; however: Package libreadline-dev is not installed. pbuilder-satisfydepends-dummy depends on bison; however: Package bison is not installed. pbuilder-satisfydepends-dummy depends on flex; however: Package flex is not installed. pbuilder-satisfydepends-dummy depends on gawk; however: Package gawk is not installed. pbuilder-satisfydepends-dummy depends on libffi-dev; however: Package libffi-dev is not installed. pbuilder-satisfydepends-dummy depends on pkg-config; however: Package pkg-config is not installed. pbuilder-satisfydepends-dummy depends on txt2man; however: Package txt2man is not installed. pbuilder-satisfydepends-dummy depends on iverilog (>= 10.1); however: Package iverilog is not installed. pbuilder-satisfydepends-dummy depends on python3; however: Package python3 is not installed. pbuilder-satisfydepends-dummy depends on berkeley-abc (>= 1.01+20221019git70cb339+dfsg-3); however: Package berkeley-abc is not installed. pbuilder-satisfydepends-dummy depends on texlive-base; however: Package texlive-base is not installed. pbuilder-satisfydepends-dummy depends on texlive-plain-generic; however: Package texlive-plain-generic is not installed. pbuilder-satisfydepends-dummy depends on texlive-fonts-recommended; however: Package texlive-fonts-recommended is not installed. pbuilder-satisfydepends-dummy depends on texlive-fonts-extra; however: Package texlive-fonts-extra is not installed. pbuilder-satisfydepends-dummy depends on texlive-latex-base; however: Package texlive-latex-base is not installed. pbuilder-satisfydepends-dummy depends on texlive-latex-extra; however: Package texlive-latex-extra is not installed. pbuilder-satisfydepends-dummy depends on texlive-font-utils; however: Package texlive-font-utils is not installed. pbuilder-satisfydepends-dummy depends on texlive-science; however: Package texlive-science is not installed. pbuilder-satisfydepends-dummy depends on texlive-publishers; however: Package texlive-publishers is not installed. pbuilder-satisfydepends-dummy depends on texlive-bibtex-extra; however: Package texlive-bibtex-extra is not installed. pbuilder-satisfydepends-dummy depends on lmodern; however: Package lmodern is not installed. pbuilder-satisfydepends-dummy depends on graphviz; however: Package graphviz is not installed. Setting up pbuilder-satisfydepends-dummy (0.invalid.0) ... Reading package lists... Building dependency tree... Reading state information... Initializing package states... Writing extended state information... Building tag database... pbuilder-satisfydepends-dummy is already installed at the requested version (0.invalid.0) pbuilder-satisfydepends-dummy is already installed at the requested version (0.invalid.0) The following NEW packages will be installed: autoconf{a} automake{a} autopoint{a} autotools-dev{a} berkeley-abc{a} bison{a} bsdextrautils{a} debhelper{a} dh-autoreconf{a} dh-python{a} dh-strip-nondeterminism{a} dwz{a} file{a} flex{a} fontconfig{a} fontconfig-config{a} fonts-dejavu-core{a} fonts-gfs-baskerville{a} fonts-gfs-porson{a} fonts-lmodern{a} gawk{a} gettext{a} gettext-base{a} graphviz{a} groff-base{a} intltool-debian{a} iverilog{a} libabsl20220623{a} libann0{a} libaom3{a} libapache-pom-java{a} libarchive-zip-perl{a} libavif15{a} libbrotli1{a} libbsd0{a} libcairo2{a} libcdt5{a} libcgraph6{a} libcommons-logging-java{a} libcommons-parent-java{a} libdatrie1{a} libdav1d6{a} libde265-0{a} libdebhelper-perl{a} libdeflate0{a} libelf1{a} libexpat1{a} libffi-dev{a} libfile-stripnondeterminism-perl{a} libfontbox-java{a} libfontconfig1{a} libfontenc1{a} libfreetype6{a} libfribidi0{a} libgav1-1{a} libgd3{a} libglib2.0-0{a} libgraphite2-3{a} libgts-0.7-5{a} libgvc6{a} libgvpr2{a} libharfbuzz0b{a} libheif1{a} libice6{a} libicu72{a} libjbig0{a} libjpeg62-turbo{a} libkpathsea6{a} liblab-gamut1{a} liblerc4{a} libltdl7{a} libmagic-mgc{a} libmagic1{a} libncurses-dev{a} libncurses6{a} libnuma1{a} libpango-1.0-0{a} libpangocairo-1.0-0{a} libpangoft2-1.0-0{a} libpaper-utils{a} libpaper1{a} libpathplan4{a} libpdfbox-java{a} libpipeline1{a} libpixman-1-0{a} libpkgconf3{a} libpng16-16{a} libptexenc1{a} libpython3-stdlib{a} libpython3.11-minimal{a} libpython3.11-stdlib{a} librav1e0{a} libreadline-dev{a} libreadline8{a} libsigsegv2{a} libsm6{a} libsub-override-perl{a} libsvtav1enc1{a} libsynctex2{a} libtcl8.6{a} libteckit0{a} libtexlua53-5{a} libtexluajit2{a} libthai-data{a} libthai0{a} libtiff6{a} libtool{a} libuchardet0{a} libwebp7{a} libx11-6{a} libx11-data{a} libx265-199{a} libxau6{a} libxaw7{a} libxcb-render0{a} libxcb-shm0{a} libxcb1{a} libxdmcp6{a} libxext6{a} libxi6{a} libxml2{a} libxmu6{a} libxpm4{a} libxrender1{a} libxt6{a} libyuv0{a} libzzip-0-13{a} lmodern{a} m4{a} man-db{a} media-types{a} pkg-config{a} pkgconf{a} pkgconf-bin{a} po-debconf{a} preview-latex-style{a} python3{a} python3-distutils{a} python3-lib2to3{a} python3-minimal{a} python3.11{a} python3.11-minimal{a} readline-common{a} sensible-utils{a} t1utils{a} tcl{a} tcl-dev{a} tcl8.6{a} tcl8.6-dev{a} tex-common{a} texlive-base{a} texlive-bibtex-extra{a} texlive-binaries{a} texlive-font-utils{a} texlive-fonts-extra{a} texlive-fonts-recommended{a} texlive-lang-greek{a} texlive-latex-base{a} texlive-latex-extra{a} texlive-latex-recommended{a} texlive-pictures{a} texlive-plain-generic{a} texlive-publishers{a} texlive-science{a} txt2man{a} ucf{a} x11-common{a} xdg-utils{a} xfonts-encodings{a} xfonts-utils{a} zlib1g-dev{a} The following packages are RECOMMENDED but will NOT be installed: ca-certificates cm-super curl default-jre dvisvgm fonts-adf-accanthis fonts-adf-berenis fonts-adf-gillius fonts-adf-universalis fonts-cabin fonts-cantarell fonts-clear-sans fonts-comfortaa fonts-comic-neue fonts-croscore fonts-crosextra-caladea fonts-crosextra-carlito fonts-dejavu-extra fonts-ebgaramond-extra fonts-font-awesome fonts-freefont-otf fonts-freefont-ttf fonts-gfs-artemisia fonts-gfs-complutum fonts-gfs-didot fonts-gfs-neohellenic fonts-gfs-olga fonts-gfs-solomos fonts-go fonts-inter fonts-junicode fonts-lato fonts-liberation2 fonts-linuxlibertine fonts-lobstertwo fonts-noto-color-emoji fonts-noto-core fonts-noto-mono fonts-oflb-asana-math fonts-open-sans fonts-paratype fonts-roboto-slab fonts-roboto-unhinted fonts-sil-andika fonts-sil-charis fonts-sil-gentium fonts-sil-gentium-basic fonts-sil-gentiumplus fonts-sil-gentiumplus-compact fonts-stix ghostscript libarchive-cpio-perl libfile-mimeinfo-perl libfl-dev libglib2.0-data libgpm2 libgts-bin libltdl-dev libmail-sendmail-perl libnet-dbus-perl libspreadsheet-parseexcel-perl libx11-protocol-perl lynx ps2eps ruby shared-mime-info tex-gyre texlive-fonts-extra-links tipa tk wget x11-utils x11-xserver-utils xdg-user-dirs 0 packages upgraded, 171 newly installed, 0 to remove and 0 not upgraded. Need to get 885 MB of archives. After unpacking 2427 MB will be used. Writing extended state information... Get: 1 http://deb.debian.org/debian bookworm/main amd64 m4 amd64 1.4.19-3 [287 kB] Get: 2 http://deb.debian.org/debian bookworm/main amd64 flex amd64 2.6.4-8.2 [422 kB] Get: 3 http://deb.debian.org/debian bookworm/main amd64 readline-common all 8.2-1.3 [69.0 kB] Get: 4 http://deb.debian.org/debian bookworm/main amd64 libreadline8 amd64 8.2-1.3 [166 kB] Get: 5 http://deb.debian.org/debian bookworm/main amd64 libsigsegv2 amd64 2.14-1 [37.2 kB] Get: 6 http://deb.debian.org/debian bookworm/main amd64 gawk amd64 1:5.2.1-2 [673 kB] Get: 7 http://deb.debian.org/debian bookworm/main amd64 libpython3.11-minimal amd64 3.11.2-6 [813 kB] Get: 8 http://deb.debian.org/debian bookworm/main amd64 libexpat1 amd64 2.5.0-1 [99.3 kB] Get: 9 http://deb.debian.org/debian bookworm/main amd64 python3.11-minimal amd64 3.11.2-6 [2064 kB] Get: 10 http://deb.debian.org/debian bookworm/main amd64 python3-minimal amd64 3.11.2-1+b1 [26.3 kB] Get: 11 http://deb.debian.org/debian bookworm/main amd64 media-types all 10.0.0 [26.1 kB] Get: 12 http://deb.debian.org/debian bookworm/main amd64 libpython3.11-stdlib amd64 3.11.2-6 [1796 kB] Get: 13 http://deb.debian.org/debian bookworm/main amd64 python3.11 amd64 3.11.2-6 [572 kB] Get: 14 http://deb.debian.org/debian bookworm/main amd64 libpython3-stdlib amd64 3.11.2-1+b1 [9312 B] Get: 15 http://deb.debian.org/debian bookworm/main amd64 python3 amd64 3.11.2-1+b1 [26.3 kB] Get: 16 http://deb.debian.org/debian bookworm/main amd64 sensible-utils all 0.0.17+nmu1 [19.0 kB] Get: 17 http://deb.debian.org/debian bookworm/main amd64 libmagic-mgc amd64 1:5.44-3 [305 kB] Get: 18 http://deb.debian.org/debian bookworm/main amd64 libmagic1 amd64 1:5.44-3 [104 kB] Get: 19 http://deb.debian.org/debian bookworm/main amd64 file amd64 1:5.44-3 [42.5 kB] Get: 20 http://deb.debian.org/debian bookworm/main amd64 gettext-base amd64 0.21-12 [160 kB] Get: 21 http://deb.debian.org/debian bookworm/main amd64 libuchardet0 amd64 0.0.7-1 [67.8 kB] Get: 22 http://deb.debian.org/debian bookworm/main amd64 groff-base amd64 1.22.4-10 [916 kB] Get: 23 http://deb.debian.org/debian bookworm/main amd64 bsdextrautils amd64 2.38.1-5+b1 [86.6 kB] Get: 24 http://deb.debian.org/debian bookworm/main amd64 libpipeline1 amd64 1.5.7-1 [38.5 kB] Get: 25 http://deb.debian.org/debian bookworm/main amd64 man-db amd64 2.11.2-2 [1386 kB] Get: 26 http://deb.debian.org/debian bookworm/main amd64 ucf all 3.0043+nmu1 [55.2 kB] Get: 27 http://deb.debian.org/debian bookworm/main amd64 autoconf all 2.71-3 [332 kB] Get: 28 http://deb.debian.org/debian bookworm/main amd64 autotools-dev all 20220109.1 [51.6 kB] Get: 29 http://deb.debian.org/debian bookworm/main amd64 automake all 1:1.16.5-1.3 [823 kB] Get: 30 http://deb.debian.org/debian bookworm/main amd64 autopoint all 0.21-12 [495 kB] Get: 31 http://deb.debian.org/debian bookworm/main amd64 berkeley-abc amd64 1.01+20221019git70cb339+dfsg-4 [5688 kB] Get: 32 http://deb.debian.org/debian bookworm/main amd64 bison amd64 2:3.8.2+dfsg-1+b1 [1175 kB] Get: 33 http://deb.debian.org/debian bookworm/main amd64 libdebhelper-perl all 13.11.4 [81.2 kB] Get: 34 http://deb.debian.org/debian bookworm/main amd64 libtool all 2.4.7-5 [517 kB] Get: 35 http://deb.debian.org/debian bookworm/main amd64 dh-autoreconf all 20 [17.1 kB] Get: 36 http://deb.debian.org/debian bookworm/main amd64 libarchive-zip-perl all 1.68-1 [104 kB] Get: 37 http://deb.debian.org/debian bookworm/main amd64 libsub-override-perl all 0.09-4 [9304 B] Get: 38 http://deb.debian.org/debian bookworm/main amd64 libfile-stripnondeterminism-perl all 1.13.1-1 [19.4 kB] Get: 39 http://deb.debian.org/debian bookworm/main amd64 dh-strip-nondeterminism all 1.13.1-1 [8620 B] Get: 40 http://deb.debian.org/debian bookworm/main amd64 libelf1 amd64 0.188-2.1 [174 kB] Get: 41 http://deb.debian.org/debian bookworm/main amd64 dwz amd64 0.15-1 [109 kB] Get: 42 http://deb.debian.org/debian bookworm/main amd64 libicu72 amd64 72.1-3 [9376 kB] Get: 43 http://deb.debian.org/debian bookworm/main amd64 libxml2 amd64 2.9.14+dfsg-1.2 [687 kB] Get: 44 http://deb.debian.org/debian bookworm/main amd64 gettext amd64 0.21-12 [1300 kB] Get: 45 http://deb.debian.org/debian bookworm/main amd64 intltool-debian all 0.35.0+20060710.6 [22.9 kB] Get: 46 http://deb.debian.org/debian bookworm/main amd64 po-debconf all 1.0.21+nmu1 [248 kB] Get: 47 http://deb.debian.org/debian bookworm/main amd64 debhelper all 13.11.4 [942 kB] Get: 48 http://deb.debian.org/debian bookworm/main amd64 python3-lib2to3 all 3.11.2-3 [76.3 kB] Get: 49 http://deb.debian.org/debian bookworm/main amd64 python3-distutils all 3.11.2-3 [131 kB] Get: 50 http://deb.debian.org/debian bookworm/main amd64 dh-python all 5.20230130 [104 kB] Get: 51 http://deb.debian.org/debian bookworm/main amd64 libbrotli1 amd64 1.0.9-2+b6 [275 kB] Get: 52 http://deb.debian.org/debian bookworm/main amd64 libpng16-16 amd64 1.6.39-2 [276 kB] Get: 53 http://deb.debian.org/debian bookworm/main amd64 libfreetype6 amd64 2.12.1+dfsg-5 [399 kB] Get: 54 http://deb.debian.org/debian bookworm/main amd64 fonts-dejavu-core all 2.37-6 [1068 kB] Get: 55 http://deb.debian.org/debian bookworm/main amd64 fontconfig-config amd64 2.14.1-4 [315 kB] Get: 56 http://deb.debian.org/debian bookworm/main amd64 libfontconfig1 amd64 2.14.1-4 [386 kB] Get: 57 http://deb.debian.org/debian bookworm/main amd64 fontconfig amd64 2.14.1-4 [449 kB] Get: 58 http://deb.debian.org/debian bookworm/main amd64 fonts-gfs-baskerville all 1.1-6 [43.7 kB] Get: 59 http://deb.debian.org/debian bookworm/main amd64 fonts-gfs-porson all 1.1-7 [33.8 kB] Get: 60 http://deb.debian.org/debian bookworm/main amd64 fonts-lmodern all 2.005-1 [4540 kB] Get: 61 http://deb.debian.org/debian bookworm/main amd64 libann0 amd64 1.1.2+doc-9+b1 [25.1 kB] Get: 62 http://deb.debian.org/debian bookworm/main amd64 libcdt5 amd64 2.42.2-7+b3 [39.8 kB] Get: 63 http://deb.debian.org/debian bookworm/main amd64 libcgraph6 amd64 2.42.2-7+b3 [63.2 kB] Get: 64 http://deb.debian.org/debian bookworm/main amd64 libaom3 amd64 3.6.0-1 [1851 kB] Get: 65 http://deb.debian.org/debian bookworm/main amd64 libdav1d6 amd64 1.0.0-2 [495 kB] Get: 66 http://deb.debian.org/debian bookworm/main amd64 libabsl20220623 amd64 20220623.1-1 [391 kB] Get: 67 http://deb.debian.org/debian bookworm/main amd64 libgav1-1 amd64 0.18.0-1+b1 [332 kB] Get: 68 http://deb.debian.org/debian bookworm/main amd64 librav1e0 amd64 0.5.1-6 [763 kB] Get: 69 http://deb.debian.org/debian bookworm/main amd64 libsvtav1enc1 amd64 1.4.1+dfsg-1 [2121 kB] Get: 70 http://deb.debian.org/debian bookworm/main amd64 libjpeg62-turbo amd64 1:2.1.5-2 [166 kB] Get: 71 http://deb.debian.org/debian bookworm/main amd64 libyuv0 amd64 0.0~git20230123.b2528b0-1 [168 kB] Get: 72 http://deb.debian.org/debian bookworm/main amd64 libavif15 amd64 0.11.1-1 [93.8 kB] Get: 73 http://deb.debian.org/debian bookworm/main amd64 libde265-0 amd64 1.0.11-1 [185 kB] Get: 74 http://deb.debian.org/debian bookworm/main amd64 libnuma1 amd64 2.0.16-1 [21.0 kB] Get: 75 http://deb.debian.org/debian bookworm/main amd64 libx265-199 amd64 3.5-2+b1 [1150 kB] Get: 76 http://deb.debian.org/debian bookworm/main amd64 libheif1 amd64 1.15.1-1 [215 kB] Get: 77 http://deb.debian.org/debian bookworm/main amd64 libdeflate0 amd64 1.14-1 [61.4 kB] Get: 78 http://deb.debian.org/debian bookworm/main amd64 libjbig0 amd64 2.1-6.1 [31.7 kB] Get: 79 http://deb.debian.org/debian bookworm/main amd64 liblerc4 amd64 4.0.0+ds-2 [170 kB] Get: 80 http://deb.debian.org/debian bookworm/main amd64 libwebp7 amd64 1.2.4-0.2 [285 kB] Get: 81 http://deb.debian.org/debian bookworm/main amd64 libtiff6 amd64 4.5.0-6 [316 kB] Get: 82 http://deb.debian.org/debian bookworm/main amd64 libxau6 amd64 1:1.0.9-1 [19.7 kB] Get: 83 http://deb.debian.org/debian bookworm/main amd64 libbsd0 amd64 0.11.7-2 [117 kB] Get: 84 http://deb.debian.org/debian bookworm/main amd64 libxdmcp6 amd64 1:1.1.2-3 [26.3 kB] Get: 85 http://deb.debian.org/debian bookworm/main amd64 libxcb1 amd64 1.15-1 [144 kB] Get: 86 http://deb.debian.org/debian bookworm/main amd64 libx11-data all 2:1.8.4-2 [292 kB] Get: 87 http://deb.debian.org/debian bookworm/main amd64 libx11-6 amd64 2:1.8.4-2 [759 kB] Get: 88 http://deb.debian.org/debian bookworm/main amd64 libxpm4 amd64 1:3.5.12-1.1 [48.4 kB] Get: 89 http://deb.debian.org/debian bookworm/main amd64 libgd3 amd64 2.3.3-9 [124 kB] Get: 90 http://deb.debian.org/debian bookworm/main amd64 libglib2.0-0 amd64 2.74.6-2 [1398 kB] Get: 91 http://deb.debian.org/debian bookworm/main amd64 libgts-0.7-5 amd64 0.7.6+darcs121130-5+b1 [160 kB] Get: 92 http://deb.debian.org/debian bookworm/main amd64 libpixman-1-0 amd64 0.42.2-1 [546 kB] Get: 93 http://deb.debian.org/debian bookworm/main amd64 libxcb-render0 amd64 1.15-1 [115 kB] Get: 94 http://deb.debian.org/debian bookworm/main amd64 libxcb-shm0 amd64 1.15-1 [105 kB] Get: 95 http://deb.debian.org/debian bookworm/main amd64 libxext6 amd64 2:1.3.4-1+b1 [52.9 kB] Get: 96 http://deb.debian.org/debian bookworm/main amd64 libxrender1 amd64 1:0.9.10-1.1 [33.2 kB] Get: 97 http://deb.debian.org/debian bookworm/main amd64 libcairo2 amd64 1.16.0-7 [575 kB] Get: 98 http://deb.debian.org/debian bookworm/main amd64 libltdl7 amd64 2.4.7-5 [393 kB] Get: 99 http://deb.debian.org/debian bookworm/main amd64 libfribidi0 amd64 1.0.8-2.1 [65.0 kB] Get: 100 http://deb.debian.org/debian bookworm/main amd64 libgraphite2-3 amd64 1.3.14-1 [81.2 kB] Get: 101 http://deb.debian.org/debian bookworm/main amd64 libharfbuzz0b amd64 6.0.0+dfsg-3 [1945 kB] Get: 102 http://deb.debian.org/debian bookworm/main amd64 libthai-data all 0.1.29-1 [176 kB] Get: 103 http://deb.debian.org/debian bookworm/main amd64 libdatrie1 amd64 0.2.13-2+b1 [43.3 kB] Get: 104 http://deb.debian.org/debian bookworm/main amd64 libthai0 amd64 0.1.29-1 [57.5 kB] Get: 105 http://deb.debian.org/debian bookworm/main amd64 libpango-1.0-0 amd64 1.50.12+ds-1 [212 kB] Get: 106 http://deb.debian.org/debian bookworm/main amd64 libpangoft2-1.0-0 amd64 1.50.12+ds-1 [47.4 kB] Get: 107 http://deb.debian.org/debian bookworm/main amd64 libpangocairo-1.0-0 amd64 1.50.12+ds-1 [34.2 kB] Get: 108 http://deb.debian.org/debian bookworm/main amd64 libpathplan4 amd64 2.42.2-7+b3 [42.2 kB] Get: 109 http://deb.debian.org/debian bookworm/main amd64 libgvc6 amd64 2.42.2-7+b3 [678 kB] Get: 110 http://deb.debian.org/debian bookworm/main amd64 libgvpr2 amd64 2.42.2-7+b3 [189 kB] Get: 111 http://deb.debian.org/debian bookworm/main amd64 liblab-gamut1 amd64 2.42.2-7+b3 [198 kB] Get: 112 http://deb.debian.org/debian bookworm/main amd64 x11-common all 1:7.7+23 [252 kB] Get: 113 http://deb.debian.org/debian bookworm/main amd64 libice6 amd64 2:1.0.10-1 [58.5 kB] Get: 114 http://deb.debian.org/debian bookworm/main amd64 libsm6 amd64 2:1.2.3-1 [35.1 kB] Get: 115 http://deb.debian.org/debian bookworm/main amd64 libxt6 amd64 1:1.2.1-1.1 [186 kB] Get: 116 http://deb.debian.org/debian bookworm/main amd64 libxmu6 amd64 2:1.1.3-3 [60.1 kB] Get: 117 http://deb.debian.org/debian bookworm/main amd64 libxaw7 amd64 2:1.0.14-1 [201 kB] Get: 118 http://deb.debian.org/debian bookworm/main amd64 graphviz amd64 2.42.2-7+b3 [611 kB] Get: 119 http://deb.debian.org/debian bookworm/main amd64 iverilog amd64 11.0-1.1+b1 [2023 kB] Get: 120 http://deb.debian.org/debian bookworm/main amd64 libapache-pom-java all 29-2 [5276 B] Get: 121 http://deb.debian.org/debian bookworm/main amd64 libcommons-parent-java all 56-1 [10.8 kB] Get: 122 http://deb.debian.org/debian bookworm/main amd64 libcommons-logging-java all 1.2-3 [62.4 kB] Get: 123 http://deb.debian.org/debian bookworm/main amd64 libffi-dev amd64 3.4.4-1 [59.4 kB] Get: 124 http://deb.debian.org/debian bookworm/main amd64 libfontbox-java all 1:1.8.16-2 [211 kB] Get: 125 http://deb.debian.org/debian bookworm/main amd64 libfontenc1 amd64 1:1.1.4-1 [24.3 kB] Get: 126 http://deb.debian.org/debian bookworm/main amd64 libkpathsea6 amd64 2022.20220321.62855-5.1 [152 kB] Get: 127 http://deb.debian.org/debian bookworm/main amd64 libncurses6 amd64 6.4-4 [103 kB] Get: 128 http://deb.debian.org/debian bookworm/main amd64 libncurses-dev amd64 6.4-4 [349 kB] Get: 129 http://deb.debian.org/debian bookworm/main amd64 libpaper1 amd64 1.1.29 [12.5 kB] Get: 130 http://deb.debian.org/debian bookworm/main amd64 libpaper-utils amd64 1.1.29 [8868 B] Get: 131 http://deb.debian.org/debian bookworm/main amd64 libpdfbox-java all 1:1.8.16-2 [5205 kB] Get: 132 http://deb.debian.org/debian bookworm/main amd64 libpkgconf3 amd64 1.8.1-1 [36.1 kB] Get: 133 http://deb.debian.org/debian bookworm/main amd64 libptexenc1 amd64 2022.20220321.62855-5.1 [43.6 kB] Get: 134 http://deb.debian.org/debian bookworm/main amd64 libreadline-dev amd64 8.2-1.3 [151 kB] Get: 135 http://deb.debian.org/debian bookworm/main amd64 libsynctex2 amd64 2022.20220321.62855-5.1 [59.7 kB] Get: 136 http://deb.debian.org/debian bookworm/main amd64 libtcl8.6 amd64 8.6.13+dfsg-2 [1035 kB] Get: 137 http://deb.debian.org/debian bookworm/main amd64 libteckit0 amd64 2.5.11+ds1-1+b1 [335 kB] Get: 138 http://deb.debian.org/debian bookworm/main amd64 libtexlua53-5 amd64 2022.20220321.62855-5.1 [110 kB] Get: 139 http://deb.debian.org/debian bookworm/main amd64 libtexluajit2 amd64 2022.20220321.62855-5.1 [246 kB] Get: 140 http://deb.debian.org/debian bookworm/main amd64 libxi6 amd64 2:1.8-1+b1 [84.2 kB] Get: 141 http://deb.debian.org/debian bookworm/main amd64 libzzip-0-13 amd64 0.13.72+dfsg.1-1.1 [58.3 kB] Get: 142 http://deb.debian.org/debian bookworm/main amd64 tex-common all 6.18 [32.5 kB] Get: 143 http://deb.debian.org/debian bookworm/main amd64 xfonts-encodings all 1:1.0.4-2.2 [577 kB] Get: 144 http://deb.debian.org/debian bookworm/main amd64 xfonts-utils amd64 1:7.7+6 [93.0 kB] Get: 145 http://deb.debian.org/debian bookworm/main amd64 lmodern all 2.005-1 [9480 kB] Get: 146 http://deb.debian.org/debian bookworm/main amd64 pkgconf-bin amd64 1.8.1-1 [29.5 kB] Get: 147 http://deb.debian.org/debian bookworm/main amd64 pkgconf amd64 1.8.1-1 [25.9 kB] Get: 148 http://deb.debian.org/debian bookworm/main amd64 pkg-config amd64 1.8.1-1 [13.7 kB] Get: 149 http://deb.debian.org/debian bookworm/main amd64 preview-latex-style all 12.2-1 [201 kB] Get: 150 http://deb.debian.org/debian bookworm/main amd64 t1utils amd64 1.41-4 [62.1 kB] Get: 151 http://deb.debian.org/debian bookworm/main amd64 tcl8.6 amd64 8.6.13+dfsg-2 [120 kB] Get: 152 http://deb.debian.org/debian bookworm/main amd64 tcl amd64 8.6.13 [4016 B] Get: 153 http://deb.debian.org/debian bookworm/main amd64 zlib1g-dev amd64 1:1.2.13.dfsg-1 [916 kB] Get: 154 http://deb.debian.org/debian bookworm/main amd64 tcl8.6-dev amd64 8.6.13+dfsg-2 [1023 kB] Get: 155 http://deb.debian.org/debian bookworm/main amd64 tcl-dev amd64 8.6.13 [6560 B] Get: 156 http://deb.debian.org/debian bookworm/main amd64 texlive-binaries amd64 2022.20220321.62855-5.1 [10.5 MB] Get: 157 http://deb.debian.org/debian bookworm/main amd64 xdg-utils all 1.1.3-4.1 [75.5 kB] Get: 158 http://deb.debian.org/debian bookworm/main amd64 texlive-base all 2022.20230122-3 [21.9 MB] Get: 159 http://deb.debian.org/debian bookworm/main amd64 texlive-latex-base all 2022.20230122-3 [1182 kB] Get: 160 http://deb.debian.org/debian bookworm/main amd64 texlive-bibtex-extra all 2022.20230122-4 [75.6 MB] Get: 161 http://deb.debian.org/debian bookworm/main amd64 texlive-font-utils all 2022.20230122-4 [4129 kB] Get: 162 http://deb.debian.org/debian bookworm/main amd64 texlive-fonts-extra all 2022.20230122-4 [509 MB] Get: 163 http://deb.debian.org/debian bookworm/main amd64 texlive-fonts-recommended all 2022.20230122-3 [4988 kB] Get: 164 http://deb.debian.org/debian bookworm/main amd64 texlive-lang-greek all 2022.20230122-1 [78.1 MB] Get: 165 http://deb.debian.org/debian bookworm/main amd64 texlive-latex-recommended all 2022.20230122-3 [8880 kB] Get: 166 http://deb.debian.org/debian bookworm/main amd64 texlive-pictures all 2022.20230122-3 [15.8 MB] Get: 167 http://deb.debian.org/debian bookworm/main amd64 texlive-latex-extra all 2022.20230122-4 [19.2 MB] Get: 168 http://deb.debian.org/debian bookworm/main amd64 texlive-plain-generic all 2022.20230122-4 [28.9 MB] Get: 169 http://deb.debian.org/debian bookworm/main amd64 texlive-publishers all 2022.20230122-4 [21.1 MB] Get: 170 http://deb.debian.org/debian bookworm/main amd64 texlive-science all 2022.20230122-4 [3722 kB] Get: 171 http://deb.debian.org/debian bookworm/main amd64 txt2man all 1.7.1-4 [35.4 kB] Fetched 885 MB in 9s (96.3 MB/s) debconf: delaying package configuration, since apt-utils is not installed Selecting previously unselected package m4. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 19591 files and directories currently installed.) Preparing to unpack .../archives/m4_1.4.19-3_amd64.deb ... Unpacking m4 (1.4.19-3) ... Selecting previously unselected package flex. Preparing to unpack .../flex_2.6.4-8.2_amd64.deb ... Unpacking flex (2.6.4-8.2) ... Selecting previously unselected package readline-common. Preparing to unpack .../readline-common_8.2-1.3_all.deb ... Unpacking readline-common (8.2-1.3) ... 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Building tag database... -> Finished parsing the build-deps I: Building the package I: Running cd /build/yosys-0.23/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-genchanges -S > ../yosys_0.23-6_source.changes dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.23-6 dpkg-buildpackage: info: source distribution unstable dpkg-buildpackage: info: source changed by Daniel Gröber dpkg-source --before-build . dpkg-buildpackage: info: host architecture amd64 debian/rules clean PREFIX=/usr dh clean --with=python3 debian/rules override_dh_auto_clean make[1]: Entering directory '/build/yosys-0.23' dh_auto_clean make -j16 clean make[2]: Entering directory '/build/yosys-0.23' rm -rf share rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f rm -f kernel/version_7ce5011c24b.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/qbfsat.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/machxo2/synth_machxo2.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/rtlil/rtlil_parser.tab.cc frontends/rtlil/rtlil_parser.tab.hh frontends/rtlil/rtlil_parser.output frontends/rtlil/rtlil_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc yosys-witness share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/binding.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/constids.inc share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/kernel/qcsat.h share/include/kernel/ff.h share/include/kernel/ffinit.h share/include/kernel/fstdata.h share/include/kernel/mem.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/fst/fstapi.h share/include/libs/sha1/sha1.h share/include/libs/json11/json11.hpp share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/frontends/ast/ast_binding.h share/include/frontends/blif/blifparse.h share/include/backends/rtlil/rtlil_backend.h share/include/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.h share/python3/smtio.py share/python3/ywio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/lutrams.txt share/anlogic/lutrams_map.v share/anlogic/brams.txt share/anlogic/brams_map.v share/simlib.v share/simcells.v share/techmap.v share/smtmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/mul2dsp.v share/abc9_model.v share/abc9_map.v share/abc9_unmap.v share/cmp2lcu.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/cells_counter_map.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_ff.vh share/ecp5/cells_io.vh share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/lutrams_map.v share/ecp5/lutrams.txt share/ecp5/brams_map.v share/ecp5/brams.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/dsp_map.v share/efinix/cells_map.v share/efinix/arith_map.v share/efinix/cells_sim.v share/efinix/brams_map.v share/efinix/gbuf_map.v share/efinix/brams.txt share/gatemate/reg_map.v share/gatemate/mux_map.v share/gatemate/lut_map.v share/gatemate/mul_map.v share/gatemate/arith_map.v share/gatemate/cells_sim.v share/gatemate/cells_bb.v share/gatemate/brams_map.v share/gatemate/brams.txt share/gatemate/brams_init_20.vh share/gatemate/brams_init_40.vh share/gatemate/inv_map.v share/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_map.v share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/brams.txt share/gowin/lutrams_map.v share/gowin/lutrams.txt share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/ff_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/spram.txt share/ice40/spram_map.v share/ice40/dsp_map.v share/ice40/abc9_model.v share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams_m9k.txt share/intel/common/brams_map_m9k.v share/intel/common/ff_map.v share/intel/max10/cells_sim.v share/intel/cyclone10lp/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/cyclone10lp/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_model.v share/intel_alm/common/alm_map.v share/intel_alm/common/alm_sim.v share/intel_alm/common/arith_alm_map.v share/intel_alm/common/dff_map.v share/intel_alm/common/dff_sim.v share/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_map.v share/intel_alm/common/mem_sim.v share/intel_alm/common/misc_sim.v share/intel_alm/cyclonev/cells_sim.v share/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k_map.v share/intel_alm/common/lutram_mlab.txt share/intel_alm/common/megafunction_bb.v share/intel_alm/common/quartus_rename.v share/machxo2/cells_map.v share/machxo2/cells_sim.v share/machxo2/lutrams.txt share/machxo2/lutrams_map.v share/machxo2/brams.txt share/machxo2/brams_map.v share/nexus/cells_map.v share/nexus/cells_sim.v share/nexus/parse_init.vh share/nexus/cells_xtra.v share/nexus/lutrams_map.v share/nexus/lutrams.txt share/nexus/brams_map.v share/nexus/brams.txt share/nexus/lrams_map.v share/nexus/lrams.txt share/nexus/arith_map.v share/nexus/latches_map.v share/nexus/dsp_map.v share/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_lut_map.v share/quicklogic/pp3_latches_map.v share/quicklogic/pp3_cells_map.v share/quicklogic/cells_sim.v share/quicklogic/lut_sim.v share/quicklogic/pp3_cells_sim.v share/quicklogic/abc9_model.v share/quicklogic/abc9_map.v share/quicklogic/abc9_unmap.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xc5v_map.v share/xilinx/brams_xcv.txt share/xilinx/brams_xcv_map.v share/xilinx/brams_defs.vh share/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v_map.v share/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v_map.v share/xilinx/brams_xc5v_map.v share/xilinx/brams_xc6v_map.v share/xilinx/brams_xcu_map.v share/xilinx/urams.txt share/xilinx/urams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/mux_map.v share/xilinx/xc3s_mult_map.v share/xilinx/xc3sda_dsp_map.v share/xilinx/xc6s_dsp_map.v share/xilinx/xc4v_dsp_map.v share/xilinx/xc5v_dsp_map.v share/xilinx/xc7_dsp_map.v share/xilinx/xcu_dsp_map.v share/xilinx/abc9_model.v passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h passes/techmap/filterlib.o techlibs/gatemate/lut_tree_lib.mk .cc rm -f kernel/version_*.o kernel/version_*.cc rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp tests/various/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata make[2]: Leaving directory '/build/yosys-0.23' rm -f debian/man/*.1 rm -f Makefile.conf make[1]: Leaving directory '/build/yosys-0.23' dh_clean debian/rules binary PREFIX=/usr dh binary --with=python3 dh_update_autotools_config dh_autoreconf debian/rules override_dh_auto_configure make[1]: Entering directory '/build/yosys-0.23' printf '%s\n' \ 'CONFIG := gcc' \ 'ABCEXTERNAL=berkeley-abc' \ 'ABCPULL=0' \ 'STRIP=:' \ > Makefile.conf make[1]: Leaving directory '/build/yosys-0.23' debian/rules override_dh_auto_build-arch make[1]: Entering directory '/build/yosys-0.23' dh_auto_build -- all make -j16 "INSTALL=install --strip-program=true" all make[2]: Entering directory '/build/yosys-0.23' [Makefile.conf] CONFIG := gcc [Makefile.conf] ABCEXTERNAL=berkeley-abc [Makefile.conf] ABCPULL=0 [Makefile.conf] STRIP=: rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc mkdir -p kernel/ mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.23 (git sha1 7ce5011c24b)\"; }" > kernel/version_7ce5011c24b.cc gcc -o kernel/driver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new mkdir -p kernel/ gcc -o kernel/rtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc mkdir -p kernel/ gcc -o kernel/log.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc mkdir -p kernel/ gcc -o kernel/calc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc mkdir -p kernel/ gcc -o kernel/yosys.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' -DYOSYS_DATDIR='"/usr/share/yosys"' -DYOSYS_PROGRAM_PREFIX='""' kernel/yosys.cc mkdir -p kernel/ mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc gcc -o kernel/binding.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/binding.cc mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc mkdir -p kernel/ gcc -o kernel/cellaigs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc mkdir -p kernel/ gcc -o kernel/celledges.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc mkdir -p kernel/ gcc -o kernel/satgen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/satgen.cc mkdir -p kernel/ gcc -o kernel/qcsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/qcsat.cc mkdir -p kernel/ gcc -o kernel/mem.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/mem.cc mkdir -p kernel/ gcc -o kernel/ffmerge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ffmerge.cc mkdir -p kernel/ gcc -o kernel/ff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ff.cc mkdir -p kernel/ gcc -o kernel/fstdata.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fstdata.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerAlgorithms.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigInteger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerUtils.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsigned.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsignedInABase.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc mkdir -p libs/sha1/ gcc -o libs/sha1/sha1.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp mkdir -p libs/json11/ gcc -o libs/json11/json11.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp mkdir -p libs/subcircuit/ gcc -o libs/subcircuit/subcircuit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezminisat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Options.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc mkdir -p libs/minisat/ gcc -o libs/minisat/SimpSolver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:119:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]' libs/minisat/SimpSolver.cc:92:26: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ mkdir -p libs/minisat/ gcc -o libs/minisat/Solver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of 'void Minisat::vec::capacity(Size) [with T = Minisat::vec; _Size = int; Size = int]': libs/minisat/Vec.h:119:13: required from 'void Minisat::vec::growTo(Size) [with T = Minisat::vec; _Size = int; Size = int]' libs/minisat/IntMap.h:48:58: required from 'void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]' libs/minisat/SolverTypes.h:338:49: required from 'void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]' libs/minisat/Solver.cc:134:19: required from here libs/minisat/Vec.h:103:33: warning: 'void* realloc(void*, size_t)' moving an object of non-trivially copyable type 'class Minisat::vec'; use 'new' and 'delete' instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ libs/minisat/Vec.h:39:7: note: 'class Minisat::vec' declared here 39 | class vec { | ^~~ mkdir -p libs/minisat/ gcc -o libs/minisat/System.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc mkdir -p libs/fst/ gcc -o libs/fst/fstapi.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fstapi.cc mkdir -p libs/fst/ gcc -o libs/fst/fastlz.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fastlz.cc mkdir -p libs/fst/ gcc -o libs/fst/lz4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/lz4.cc mkdir -p frontends/aiger/ gcc -o frontends/aiger/aigerparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger/aigerparse.cc mkdir -p frontends/ast/ gcc -o frontends/ast/ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc mkdir -p frontends/ast/ gcc -o frontends/ast/simplify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc mkdir -p frontends/ast/ gcc -o frontends/ast/genrtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc mkdir -p frontends/ast/ gcc -o frontends/ast/dpicall.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc mkdir -p frontends/ast/ gcc -o frontends/ast/ast_binding.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast_binding.cc mkdir -p frontends/blif/ gcc -o frontends/blif/blifparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc mkdir -p frontends/json/ gcc -o frontends/json/jsonparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc mkdir -p frontends/liberty/ gcc -o frontends/liberty/liberty.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc mkdir -p frontends/rpc/ gcc -o frontends/rpc/rpc_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rpc/rpc_frontend.cc mkdir -p frontends/rtlil/ bison -o frontends/rtlil/rtlil_parser.tab.cc -d -r all -b frontends/rtlil/rtlil_parser frontends/rtlil/rtlil_parser.y mkdir -p frontends/rtlil/ flex -o frontends/rtlil/rtlil_lexer.cc frontends/rtlil/rtlil_lexer.l mkdir -p frontends/rtlil/ gcc -o frontends/rtlil/rtlil_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_frontend.cc mkdir -p frontends/verific/ gcc -o frontends/verific/verific.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc mkdir -p frontends/verilog/ bison -Wall -Werror -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y mkdir -p frontends/verilog/ gcc -o frontends/verilog/preproc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc mkdir -p passes/cmds/ gcc -o passes/cmds/exec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/exec.cc mkdir -p passes/cmds/ gcc -o passes/cmds/add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc mkdir -p passes/cmds/ gcc -o passes/cmds/delete.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc mkdir -p passes/cmds/ gcc -o passes/cmds/design.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc mkdir -p passes/cmds/ gcc -o passes/cmds/select.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc mkdir -p passes/cmds/ gcc -o passes/cmds/show.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc mkdir -p passes/cmds/ gcc -o passes/cmds/rename.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc mkdir -p passes/cmds/ gcc -o passes/cmds/autoname.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/autoname.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scatter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setundef.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splitnets.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc mkdir -p passes/cmds/ gcc -o passes/cmds/stat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setattr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc mkdir -p passes/cmds/ gcc -o passes/cmds/copy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc mkdir -p passes/cmds/ gcc -o passes/cmds/glift.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/glift.cc mkdir -p passes/cmds/ gcc -o passes/cmds/torder.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logcmd.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc mkdir -p passes/cmds/ gcc -o passes/cmds/tee.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc mkdir -p passes/cmds/ gcc -o passes/cmds/write_file.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connwrappers.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc kernel/satgen.cc: In member function 'bool Yosys::SatGen::importCell(Yosys::RTLIL::Cell*, int)': kernel/satgen.cc:1237:67: warning: 'undef_srst' may be used uninitialized [-Wmaybe-uninitialized] 1237 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1228:37: note: 'undef_srst' was declared here 1228 | int undef_srst; | ^~~~~~~~~~ kernel/satgen.cc:1223:67: warning: 'undef_ce' may be used uninitialized [-Wmaybe-uninitialized] 1223 | std::tie(d, undef_d) = mux(ce, undef_ce, d, undef_d, old_q, undef_old_q); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1214:37: note: 'undef_ce' was declared here 1214 | int undef_ce; | ^~~~~~~~ kernel/satgen.cc:1209:67: warning: 'undef_srst' may be used uninitialized [-Wmaybe-uninitialized] 1209 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1200:37: note: 'undef_srst' was declared here 1200 | int undef_srst; | ^~~~~~~~~~ mkdir -p passes/cmds/ gcc -o passes/cmds/cover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc mkdir -p passes/cmds/ gcc -o passes/cmds/trace.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc mkdir -p passes/cmds/ gcc -o passes/cmds/plugin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc mkdir -p passes/cmds/ gcc -o passes/cmds/check.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc mkdir -p passes/cmds/ gcc -o passes/cmds/qwp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/qwp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/edgetypes.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc mkdir -p passes/cmds/ gcc -o passes/cmds/portlist.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/portlist.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chformal.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chtype.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc mkdir -p passes/cmds/ gcc -o passes/cmds/blackbox.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc mkdir -p passes/cmds/ gcc -o passes/cmds/ltp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/bugpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/bugpoint.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scratchpad.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scratchpad.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logger.cc mkdir -p passes/cmds/ gcc -o passes/cmds/printattrs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/printattrs.cc mkdir -p passes/cmds/ gcc -o passes/cmds/sta.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/sta.cc mkdir -p passes/cmds/ gcc -o passes/cmds/clean_zerowidth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/clean_zerowidth.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_make.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_simple.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_status.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_remove.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_induct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_struct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_purge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_mark.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_detect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_expand.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_recode.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_info.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_export.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/hierarchy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/uniquify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/submod.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc mkdir -p passes/memory/ gcc -o passes/memory/memory.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_collect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_unpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_bram.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_memx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_nordff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_narrow.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_narrow.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_libmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_libmap.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_bmux2rom.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bmux2rom.cc mkdir -p passes/memory/ gcc -o passes/memory/memlib.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memlib.cc mkdir -p passes/opt/ gcc -o passes/opt/opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_merge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_feedback.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_feedback.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_priority.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_priority.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_widen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_widen.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_muxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_dff.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_share.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_expr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc mkdir -p passes/opt/ gcc -o passes/opt/share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc mkdir -p passes/opt/ gcc -o passes/opt/wreduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_demorgan.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc mkdir -p passes/opt/ gcc -o passes/opt/rmports.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_lut.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_lut_ins.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut_ins.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_ffinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_ffinv.cc mkdir -p passes/opt/ gcc -o passes/opt/pmux2shiftx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/pmux2shiftx.cc mkdir -p passes/opt/ gcc -o passes/opt/muxpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/muxpack.cc mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/test_pmgen_pm.h -p test_pmgen passes/pmgen/test_pmgen.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_dsp_pm.h -p ice40_dsp passes/pmgen/ice40_dsp.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/peepopt_pm.h -p peepopt passes/pmgen/peepopt_shiftmul.pmg passes/pmgen/peepopt_muldiv.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_srl_pm.h -p xilinx_srl passes/pmgen/xilinx_srl.pmg mkdir -p passes/pmgen/ gcc -o passes/pmgen/ice40_dsp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_dsp.cc mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_wrapcarry_pm.h -p ice40_wrapcarry passes/pmgen/ice40_wrapcarry.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_pm.h -p xilinx_dsp passes/pmgen/xilinx_dsp.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp48a_pm.h -p xilinx_dsp48a passes/pmgen/xilinx_dsp48a.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_CREG_pm.h -p xilinx_dsp_CREG passes/pmgen/xilinx_dsp_CREG.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_cascade_pm.h -p xilinx_dsp_cascade passes/pmgen/xilinx_dsp_cascade.pmg mkdir -p passes/pmgen/ gcc -o passes/pmgen/peepopt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/peepopt.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/xilinx_srl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_srl.cc mkdir -p passes/proc/ gcc -o passes/proc/proc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_prune.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_prune.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_rmdead.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_arst.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_rom.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rom.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dlatch.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_memwr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_memwr.cc mkdir -p passes/sat/ gcc -o passes/sat/sat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc mkdir -p passes/sat/ gcc -o passes/sat/freduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc mkdir -p passes/sat/ gcc -o passes/sat/eval.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc mkdir -p passes/sat/ gcc -o passes/sat/sim.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc mkdir -p passes/sat/ gcc -o passes/sat/miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc mkdir -p passes/sat/ gcc -o passes/sat/expose.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc mkdir -p passes/sat/ gcc -o passes/sat/assertpmux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc mkdir -p passes/sat/ gcc -o passes/sat/clk2fflogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc mkdir -p passes/sat/ gcc -o passes/sat/async2sync.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc mkdir -p passes/sat/ gcc -o passes/sat/formalff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/formalff.cc mkdir -p passes/sat/ gcc -o passes/sat/supercover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/supercover.cc mkdir -p passes/sat/ gcc -o passes/sat/fmcombine.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fmcombine.cc mkdir -p passes/sat/ gcc -o passes/sat/mutate.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/mutate.cc mkdir -p passes/sat/ gcc -o passes/sat/cutpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/cutpoint.cc mkdir -p passes/sat/ gcc -o passes/sat/fminit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fminit.cc mkdir -p passes/sat/ gcc -o passes/sat/qbfsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/qbfsat.cc mkdir -p passes/techmap/ gcc -o passes/techmap/flatten.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flatten.cc mkdir -p passes/techmap/ gcc -o passes/techmap/techmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/simplemap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflibmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/maccmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/libparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc9.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9_exe.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc9_exe.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9_ops.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc9_ops.cc mkdir -p passes/techmap/ gcc -o passes/techmap/iopadmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/clkbufmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/clkbufmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/hilomap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_fa.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_counter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc mkdir -p passes/techmap/ gcc -o passes/techmap/alumacc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc mkdir -p passes/techmap/ gcc -o passes/techmap/bmuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bmuxmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/demuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/demuxmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/muxcover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc mkdir -p passes/techmap/ gcc -o passes/techmap/aigmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/tribuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/lut2mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc mkdir -p passes/techmap/ gcc -o passes/techmap/nlutmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/shregmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/deminout.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc mkdir -p passes/techmap/ gcc -o passes/techmap/insbuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmvcp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/zinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflegalize.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflegalize.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffunmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffunmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/flowmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flowmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extractinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extractinv.cc mkdir -p passes/tests/ gcc -o passes/tests/test_autotb.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc mkdir -p passes/tests/ gcc -o passes/tests/test_cell.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc mkdir -p passes/tests/ gcc -o passes/tests/test_abcloop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc mkdir -p backends/aiger/ gcc -o backends/aiger/aiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc mkdir -p backends/aiger/ gcc -o backends/aiger/xaiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/xaiger.cc mkdir -p backends/blif/ gcc -o backends/blif/blif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc mkdir -p backends/btor/ gcc -o backends/btor/btor.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc mkdir -p backends/cxxrtl/ gcc -o backends/cxxrtl/cxxrtl_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/cxxrtl/cxxrtl_backend.cc mkdir -p backends/edif/ gcc -o backends/edif/edif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc passes/techmap/abc.cc: In member function 'virtual void {anonymous}::AbcPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/techmap/abc.cc:1953:50: warning: 'g_argidx' may be used uninitialized [-Wmaybe-uninitialized] 1953 | cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str())); | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ passes/techmap/abc.cc:1671:32: note: 'g_argidx' was declared here 1671 | size_t argidx, g_argidx; | ^~~~~~~~ mkdir -p backends/firrtl/ gcc -o backends/firrtl/firrtl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc mkdir -p backends/intersynth/ gcc -o backends/intersynth/intersynth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc mkdir -p backends/jny/ gcc -o backends/jny/jny.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/jny/jny.cc mkdir -p backends/json/ gcc -o backends/json/json.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc mkdir -p backends/rtlil/ gcc -o backends/rtlil/rtlil_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/rtlil/rtlil_backend.cc mkdir -p backends/simplec/ gcc -o backends/simplec/simplec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc mkdir -p backends/smt2/ gcc -o backends/smt2/smt2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc mkdir -p backends/smv/ gcc -o backends/smv/smv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc mkdir -p backends/spice/ gcc -o backends/spice/spice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc mkdir -p backends/table/ gcc -o backends/table/table.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc mkdir -p backends/verilog/ gcc -o backends/verilog/verilog_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc mkdir -p techlibs/achronix/ gcc -o techlibs/achronix/synth_achronix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/synth_anlogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/synth_anlogic.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_eqn.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_eqn.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_fixcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_fixcarry.cc mkdir -p techlibs/common/ gcc -o techlibs/common/synth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc mkdir -p techlibs/common/ gcc -o techlibs/common/prep.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/synth_coolrunner2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_sop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_fixup.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_fixup.cc mkdir -p techlibs/easic/ gcc -o techlibs/easic/synth_easic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/synth_ecp5.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/ecp5_gsr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/ecp5_gsr.cc mkdir -p techlibs/efinix/ gcc -o techlibs/efinix/synth_efinix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/synth_efinix.cc mkdir -p techlibs/efinix/ gcc -o techlibs/efinix/efinix_fixcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/efinix_fixcarry.cc mkdir -p techlibs/gatemate/ gcc -o techlibs/gatemate/synth_gatemate.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/synth_gatemate.cc mkdir -p techlibs/gatemate/ gcc -o techlibs/gatemate/gatemate_foldinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/gatemate_foldinv.cc mkdir -p techlibs/gowin/ gcc -o techlibs/gowin/synth_gowin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/synth_greenpak4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/greenpak4_dffinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/synth_ice40.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_braminit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_braminit.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc mkdir -p techlibs/intel/ gcc -o techlibs/intel/synth_intel.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc mkdir -p techlibs/intel_alm/ gcc -o techlibs/intel_alm/synth_intel_alm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel_alm/synth_intel_alm.cc mkdir -p techlibs/machxo2/ gcc -o techlibs/machxo2/synth_machxo2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/machxo2/synth_machxo2.cc mkdir -p techlibs/nexus/ gcc -o techlibs/nexus/synth_nexus.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nexus/synth_nexus.cc mkdir -p techlibs/quicklogic/ gcc -o techlibs/quicklogic/synth_quicklogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/synth_quicklogic.cc mkdir -p techlibs/sf2/ gcc -o techlibs/sf2/synth_sf2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/synth_sf2.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/synth_xilinx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/xilinx_dffopt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dffopt.cc sed -e 's#@CXXFLAGS@#-g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \ -e 's#@CXX@#gcc#;' -e 's#@LDFLAGS@#-Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic#;' -e 's#@LDLIBS@#-lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6#;' \ -e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config chmod +x yosys-config mkdir -p passes/techmap/ gcc -o passes/techmap/filterlib.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc sed 's|##yosys-sys-path##|sys.path += ["/usr/share/yosys"]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new chmod +x yosys-smtbmc.new mv yosys-smtbmc.new yosys-smtbmc sed 's|##yosys-sys-path##|sys.path += ["/usr/share/yosys"]|;' < backends/smt2/witness.py > yosys-witness.new chmod +x yosys-witness.new mv yosys-witness.new yosys-witness mkdir -p share/include/kernel/ cp "./"/kernel/yosys.h share/include/kernel/yosys.h mkdir -p share/include/kernel/ cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h mkdir -p share/include/kernel/ cp "./"/kernel/log.h share/include/kernel/log.h mkdir -p share/include/kernel/ cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h mkdir -p share/include/kernel/ cp "./"/kernel/binding.h share/include/kernel/binding.h mkdir -p share/include/kernel/ cp "./"/kernel/register.h share/include/kernel/register.h mkdir -p share/include/kernel/ cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h mkdir -p share/include/kernel/ cp "./"/kernel/celledges.h share/include/kernel/celledges.h mkdir -p share/include/kernel/ cp "./"/kernel/consteval.h share/include/kernel/consteval.h mkdir -p share/include/kernel/ cp "./"/kernel/constids.inc share/include/kernel/constids.inc mkdir -p share/include/kernel/ cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h mkdir -p share/include/kernel/ cp "./"/kernel/modtools.h share/include/kernel/modtools.h mkdir -p share/include/kernel/ cp "./"/kernel/macc.h share/include/kernel/macc.h mkdir -p share/include/kernel/ cp "./"/kernel/utils.h share/include/kernel/utils.h mkdir -p share/include/kernel/ cp "./"/kernel/satgen.h share/include/kernel/satgen.h mkdir -p share/include/kernel/ cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h mkdir -p share/include/kernel/ cp "./"/kernel/ff.h share/include/kernel/ff.h mkdir -p share/include/kernel/ cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h mkdir -p share/include/kernel/ cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h mkdir -p share/include/kernel/ cp "./"/kernel/mem.h share/include/kernel/mem.h mkdir -p share/include/libs/ezsat/ mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h mkdir -p share/include/libs/fst/ cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h mkdir -p share/include/libs/sha1/ cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h mkdir -p share/include/libs/json11/ cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp mkdir -p share/include/passes/fsm/ mkdir -p share/include/frontends/ast/ cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h mkdir -p share/include/frontends/blif/ cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h mkdir -p share/include/backends/rtlil/ cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h mkdir -p share/python3 cp "./"/backends/smt2/smtio.py share/python3/smtio.py mkdir -p share/python3 cp "./"/backends/smt2/ywio.py share/python3/ywio.py mkdir -p share/achronix/speedster22i/ mkdir -p share/achronix/speedster22i/ cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt mkdir -p share/anlogic cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt mkdir -p share/anlogic cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v mkdir -p share cp "./"/techlibs/common/simlib.v share/simlib.v mkdir -p share cp "./"/techlibs/common/simcells.v share/simcells.v mkdir -p share cp "./"/techlibs/common/techmap.v share/techmap.v mkdir -p share cp "./"/techlibs/common/smtmap.v share/smtmap.v mkdir -p share cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v mkdir -p share cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share cp "./"/techlibs/common/dff2ff.v share/dff2ff.v mkdir -p share cp "./"/techlibs/common/gate2lut.v share/gate2lut.v mkdir -p share cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v mkdir -p share cp "./"/techlibs/common/cells.lib share/cells.lib mkdir -p share cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v mkdir -p share cp "./"/techlibs/common/abc9_model.v share/abc9_model.v mkdir -p share cp "./"/techlibs/common/abc9_map.v share/abc9_map.v mkdir -p share cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v mkdir -p share cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v mkdir -p share/coolrunner2 mkdir -p share/ecp5 cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v mkdir -p share/efinix cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt mkdir -p share/gatemate mkdir -p share/gatemate cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v mkdir -p techlibs/gatemate python3 techlibs/gatemate/make_lut_tree_lib.py mkdir -p share/gowin cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v mkdir -p share/gowin touch techlibs/gatemate/lut_tree_lib.mk cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt mkdir -p share/gowin cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib mkdir -p share/ice40 cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v mkdir -p share/ice40 cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt mkdir -p share/ice40 cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v mkdir -p share/intel/cyclone10lp cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v mkdir -p share/intel/max10 mkdir -p share/intel/cyclone10lp cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v mkdir -p share/intel/cycloneiv mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v mkdir -p share/intel_alm/cyclonev cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v mkdir -p share/machxo2 cp "./"/techlibs/machxo2/cells_map.v share/machxo2/cells_map.v mkdir -p share/machxo2 cp "./"/techlibs/machxo2/cells_sim.v share/machxo2/cells_sim.v mkdir -p share/machxo2 cp "./"/techlibs/machxo2/lutrams.txt share/machxo2/lutrams.txt mkdir -p share/machxo2 cp "./"/techlibs/machxo2/lutrams_map.v share/machxo2/lutrams_map.v mkdir -p share/machxo2 cp "./"/techlibs/machxo2/brams.txt share/machxo2/brams.txt mkdir -p share/machxo2 cp "./"/techlibs/machxo2/brams_map.v share/machxo2/brams_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt mkdir -p share/nexus cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt mkdir -p share/nexus cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v mkdir -p share/quicklogic mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v mkdir -p share/quicklogic mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v mkdir -p share/quicklogic mkdir -p share/sf2 cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v mkdir -p share/sf2 cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v mkdir -p share/sf2 mkdir -p share/xilinx cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v mkdir -p kernel/ mkdir -p kernel/ gcc -o kernel/version_7ce5011c24b.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_7ce5011c24b.cc gcc -o kernel/register.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc mkdir -p frontends/rtlil/ mkdir -p frontends/rtlil/ gcc -o frontends/rtlil/rtlil_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc gcc -o frontends/rtlil/rtlil_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc mkdir -p frontends/verilog/ mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l mkdir -p passes/pmgen/ mkdir -p passes/pmgen/ gcc -o passes/pmgen/test_pmgen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc gcc -o passes/pmgen/ice40_wrapcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_wrapcarry.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/xilinx_dsp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_dsp.cc mkdir -p ./ gcc -o yosys-filterlib -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 mkdir -p share/gatemate cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib mkdir -p share/gatemate cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc gcc -o yosys -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic kernel/version_7ce5011c24b.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o 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passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/qbfsat.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/machxo2/synth_machxo2.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 Build successful. make[2]: Leaving directory '/build/yosys-0.23' make[1]: Leaving directory '/build/yosys-0.23' debian/rules override_dh_auto_build-indep make[1]: Entering directory '/build/yosys-0.23' sed -i 's/REPLACEWITHDATE/December 03, 2022/' manual/presentation.tex PDF_DATE=D:20221203221520Z dh_auto_build -- all manual make -j16 "INSTALL=install --strip-program=true" all manual make[2]: Entering directory '/build/yosys-0.23' [Makefile.conf] CONFIG := gcc [Makefile.conf] ABCEXTERNAL=berkeley-abc [Makefile.conf] ABCPULL=0 [Makefile.conf] STRIP=: cd manual && PDF_DATE=D:20221203221520Z bash appnotes.sh Build successful. + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f 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(/usr/share/texlive/texmf-dist/tex/latex/upquote/upquote.sty) (/usr/share/texlive/texmf-dist/tex/context/base/mkii/supp-pdf.mkii [Loading MPS to PDF converter (version 2006.09.02).] ) (/usr/share/texlive/texmf-dist/tex/latex/epstopdf-pkg/epstopdf-base.sty (/usr/share/texlive/texmf-dist/tex/latex/latexconfig/epstopdf-sys.cfg)) (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsa.fd) (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsb.fd) (/usr/share/texlive/texmf-dist/tex/latex/inconsolata/t1zi4.fd) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) Underfull \hbox (badness 2221) in paragraph at lines 157--162 []\T1/ptm/m/n/9 The 2nd line checks the de-sign hi-er-ar-chy and in-stan-ti-ate s [1{/var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map} pdfTeX warning (ext4): destination with the same identifier (name{figure.1}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.211 pdfTeX warning (ext4): destination with the same identifier (name{figure.2}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.211 pdfTeX warning (ext4): destination with the same identifier (name{figure.3}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.211 ] (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang2.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang3.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstmisc.sty) [2 pdfTeX warning (ext4): destination with the same identifier (name{figure.4}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure.5}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure.6}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure.7}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.403 ] [3 pdfTeX warning (ext4): destination with the same identifier (name{figure.8}) ha s been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box \__shipout_drop_firstpage_... l.466 \end{document} ] (./APPNOTE_010_Verilog_to_BLIF.aux) ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}{/usr/share/texlive/texmf-dist/font s/enc/dvips/base/8r.enc} Output written on APPNOTE_010_Verilog_to_BLIF.pdf (3 pages, 121559 bytes). Transcript written on APPNOTE_010_Verilog_to_BLIF.log. ++ md5sum + new_md5='ca27aa4b209c6fbe385aed042119c12e -' + '[' 'ca27aa4b209c6fbe385aed042119c12e -' '!=' 'ca27aa4b209c6fbe385aed042119c12e -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_010_Verilog_to_BLIF.pdf + mv -f APPNOTE_010_Verilog_to_BLIF.pdf.without_pdf_id APPNOTE_010_Verilog_to_BLIF.pdf + touch APPNOTE_010_Verilog_to_BLIF.ok + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_011_Design_Investigation.ok -a APPNOTE_011_Design_Investigation.ok -nt APPNOTE_011_Design_Investigation.tex ']' + '[' -f APPNOTE_011_Design_Investigation/make.sh ']' + cd APPNOTE_011_Design_Investigation + bash make.sh + false + for dot_file in *.dot + pdf_file=cmos_00.pdf + dot -Tpdf -o cmos_00.pdf cmos_00.dot + for dot_file in *.dot + pdf_file=cmos_01.pdf + dot -Tpdf -o cmos_01.pdf cmos_01.dot + for dot_file in *.dot + pdf_file=example_00.pdf + dot -Tpdf -o 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Transcript written on APPNOTE_012_Verilog_to_BTOR.log. ++ md5sum + new_md5='76b15ab3a97e2a59fd8d034e4394c74b -' + '[' '76b15ab3a97e2a59fd8d034e4394c74b -' '!=' '76b15ab3a97e2a59fd8d034e4394c74b -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_012_Verilog_to_BTOR.pdf + mv -f APPNOTE_012_Verilog_to_BTOR.pdf.without_pdf_id APPNOTE_012_Verilog_to_BTOR.pdf + touch APPNOTE_012_Verilog_to_BTOR.ok cd manual && PDF_DATE=D:20221203221520Z bash presentation.sh + false + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux '*.snm' '*.nav' '*.toc' md5sum: '*.snm': No such file or directory md5sum: '*.nav': No such file or directory md5sum: '*.toc': No such file or directory + make -C PRESENTATION_Intro make[3]: Entering directory '/build/yosys-0.23/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys counter.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `counter.ys' -- 1. Executing Verilog-2005 frontend: counter.v Parsing Verilog input from `counter.v' to AST representation. Generating RTLIL representation for module `\counter'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \counter 2.2. Analyzing design hierarchy.. Top module: \counter Removed 0 unused modules. 3. Generating Graphviz representation of design. Writing dot description to `counter_00.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_00.dot' > 'counter_00.pdf.new' && mv 'counter_00.pdf.new' 'counter_00.pdf' 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\counter.$proc$counter.v:6$1'. 1/1: $0\count[1:0] 4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. created $dff cell `$procdff$8' with positive edge clock. 4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. Removing empty process `counter.$proc$counter.v:6$1'. Cleaned up 2 empty switches. 4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 2 unused cells and 5 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Executing MEMORY pass. 6.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 6.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 6.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 6.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 6.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 6.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.10. Executing MEMORY_COLLECT pass (generating $mem cells). 6.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 7. Executing OPT pass (performing simple optimizations). 7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.6. Executing OPT_DFF pass (perform DFF optimizations). 7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.9. Finished OPT passes. (There is nothing left to do.) 8. Executing FSM pass (extract and optimize FSM). 8.1. Executing FSM_DETECT pass (finding FSMs in design). 8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 9. Executing OPT pass (performing simple optimizations). 9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.6. Executing OPT_DFF pass (perform DFF optimizations). 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.9. Finished OPT passes. (There is nothing left to do.) 10. Generating Graphviz representation of design. Writing dot description to `counter_01.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_01.dot' > 'counter_01.pdf.new' && mv 'counter_01.pdf.new' 'counter_01.pdf' 11. Executing TECHMAP pass (map to technology primitives). 11.1. Executing Verilog-2005 frontend: /build/yosys-0.23/share/techmap.v Parsing Verilog input from `/build/yosys-0.23/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 11.2. Continuing TECHMAP pass. Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. No more expansions possible. 12. Executing OPT pass (performing simple optimizations). 12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.6. Executing OPT_DFF pass (perform DFF optimizations). 12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 1 unused cells and 32 unused wires. 12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.9. Rerunning OPT passes. (Maybe there is more to do..) 12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.13. Executing OPT_DFF pass (perform DFF optimizations). 12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.16. Finished OPT passes. (There is nothing left to do.) 13. Executing SPLITNETS pass (splitting up multi-bit signals). Removed 0 unused cells and 2 unused wires. 14. Generating Graphviz representation of design. Writing dot description to `counter_02.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_02.dot' > 'counter_02.pdf.new' && mv 'counter_02.pdf.new' 'counter_02.pdf' 15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\counter': mapped 2 $_DFF_P_ cells to \DFF cells. 16. Executing ABC pass (technology mapping using ABC). 16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. 16.1.1. Executing ABC. Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_Intro/mycells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Library "demo" from "/manual/PRESENTATION_Intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 16.1.2. Re-integrating ABC results. ABC RESULTS: NOT cells: 3 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 4 ABC RESULTS: internal signals: 5 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 2 Removing temp directory. Removed 0 unused cells and 10 unused wires. 17. Generating Graphviz representation of design. 17.1. Executing Verilog-2005 frontend: mycells.v Parsing Verilog input from `mycells.v' to AST representation. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Successfully finished Verilog frontend. 17.2. Continuing show pass. Writing dot description to `counter_03.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_03.dot' > 'counter_03.pdf.new' && mv 'counter_03.pdf.new' 'counter_03.pdf' End of script. Logfile hash: a1e6cccca1, CPU: user 0.08s system 0.02s, MEM: 14.25 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 85% 4x show (0 sec), 7% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_Intro' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_Intro/counter_00.pdf PRESENTATION_Intro/counter_01.pdf PRESENTATION_Intro/counter_02.pdf PRESENTATION_Intro/counter_03.pdf + make -C PRESENTATION_ExSyn make[3]: Entering directory '/build/yosys-0.23/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format pdf' -- -- Executing script file `proc_01.ys' -- 1. Executing Verilog-2005 frontend: proc_01.v Parsing Verilog input from `proc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_01.v:2$1'. 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_01.v:2$1'. 1/1: $0\Q[0:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. created $adff cell `$procdff$2' with positive edge clock and positive level reset. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_01.v:2$1'. Cleaned up 0 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_01.dot' > 'proc_01.pdf.new' && mv 'proc_01.pdf.new' 'proc_01.pdf' End of script. Logfile hash: c6fd6e6895, CPU: user 0.00s system 0.01s, MEM: 11.92 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format pdf' -- -- Executing script file `proc_02.ys' -- 1. Executing Verilog-2005 frontend: proc_02.v Parsing Verilog input from `proc_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_02.v:3$1'. 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_02.v:3$1'. 1/1: $0\Q[0:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. Warning: Async reset value `\RV' is not constant! created $aldff cell `$procdff$2' with positive edge clock and positive level non-const reset. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_02.v:3$1'. Cleaned up 0 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_02.dot' > 'proc_02.pdf.new' && mv 'proc_02.pdf.new' 'proc_02.pdf' Warnings: 1 unique messages, 1 total End of script. Logfile hash: 6c9c8edaef, CPU: user 0.00s system 0.01s, MEM: 12.12 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format pdf' -- -- Executing script file `proc_03.ys' -- 1. Executing Verilog-2005 frontend: proc_03.v Parsing Verilog input from `proc_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_03.v:3$1'. 1/1: $0\Y[0:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. 3.9. Executing PROC_DFF pass (convert process syncs to FFs). 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. Removing empty process `test.$proc$proc_03.v:3$1'. Cleaned up 2 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 4 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_03.dot' > 'proc_03.pdf.new' && mv 'proc_03.pdf.new' 'proc_03.pdf' End of script. Logfile hash: 13c48860df, CPU: user 0.01s system 0.00s, MEM: 12.02 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script opt_01.ys; show -notitle -prefix opt_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script opt_01.ys; show -notitle -prefix opt_01 -format pdf' -- -- Executing script file `opt_01.ys' -- 1. Executing Verilog-2005 frontend: opt_01.v Parsing Verilog input from `opt_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $ternary$opt_01.v:2$1. Removed 1 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Optimizing cells in module \test. Performed a total of 1 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_01.dot' > 'opt_01.pdf.new' && mv 'opt_01.pdf.new' 'opt_01.pdf' End of script. Logfile hash: 9f52b2c276, CPU: user 0.01s system 0.01s, MEM: 12.10 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 1x show (0 sec), 1% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_02.ys; show -notitle -prefix opt_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script opt_02.ys; show -notitle -prefix opt_02 -format pdf' -- -- Executing script file `opt_02.ys' -- 1. Executing Verilog-2005 frontend: opt_02.v Parsing Verilog input from `opt_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_02.dot' > 'opt_02.pdf.new' && mv 'opt_02.pdf.new' 'opt_02.pdf' End of script. Logfile hash: 5a4000bb43, CPU: user 0.02s system 0.00s, MEM: 12.07 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 1x show (0 sec), 1% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_03.ys; show -notitle -prefix opt_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script opt_03.ys; show -notitle -prefix opt_03 -format pdf' -- -- Executing script file `opt_03.ys' -- 1. Executing Verilog-2005 frontend: opt_03.v Parsing Verilog input from `opt_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_03.dot' > 'opt_03.pdf.new' && mv 'opt_03.pdf.new' 'opt_03.pdf' End of script. Logfile hash: 0cd024bc02, CPU: user 0.01s system 0.00s, MEM: 12.03 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 95% 1x show (0 sec), 1% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_04.ys; show -notitle -prefix opt_04 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script opt_04.ys; show -notitle -prefix opt_04 -format pdf' -- -- Executing script file `opt_04.ys' -- 1. Executing Verilog-2005 frontend: opt_04.v Parsing Verilog input from `opt_04.v' to AST representation. Generating RTLIL representation for module `\test'. Warning: wire '\Q1' is assigned in a block at opt_04.v:8.3-8.11. Warning: wire '\Q2' is assigned in a block at opt_04.v:12.3-12.11. Warning: wire '\Q2' is assigned in a block at opt_04.v:14.3-14.11. Warning: wire '\Q3' is assigned in a block at opt_04.v:17.2-17.10. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$opt_04.v:10$2 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \ARST in `\test.$proc$opt_04.v:10$2'. Found async reset \ARST in `\test.$proc$opt_04.v:6$1'. 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$opt_04.v:16$3'. Creating decoders for process `\test.$proc$opt_04.v:10$2'. 1/1: $0\Q2[7:0] Creating decoders for process `\test.$proc$opt_04.v:6$1'. 1/1: $0\Q1[7:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q3' using process `\test.$proc$opt_04.v:16$3'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\Q2' using process `\test.$proc$opt_04.v:10$2'. created $adff cell `$procdff$5' with positive edge clock and positive level reset. Creating register for signal `\test.\Q1' using process `\test.$proc$opt_04.v:6$1'. created $adff cell `$procdff$6' with positive edge clock and positive level reset. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$opt_04.v:16$3'. Removing empty process `test.$proc$opt_04.v:10$2'. Removing empty process `test.$proc$opt_04.v:6$1'. Cleaned up 0 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_DFF pass (perform DFF optimizations). Handling const CLK on $procdff$5 ($adff) from module test (removing D path). Handling D = Q on $procdff$6 ($adff) from module test (removing D path). Setting constant 0-bit at position 0 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 1 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 2 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 3 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 4 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 5 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 6 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 7 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 0 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 1 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 2 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 3 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 4 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 5 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 6 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 7 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 0 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 1 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 2 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 3 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 4 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 5 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 6 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 7 on $procdff$4 ($dff) from module test. 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `opt_04.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_04.dot' > 'opt_04.pdf.new' && mv 'opt_04.pdf.new' 'opt_04.pdf' Warnings: 4 unique messages, 4 total End of script. Logfile hash: 350e16de2a, CPU: user 0.01s system 0.01s, MEM: 12.07 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 95% 1x show (0 sec), 1% 4x opt_expr (0 sec), ... ../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format pdf' -- -- Executing script file `memory_01.ys' -- 1. Executing Verilog-2005 frontend: memory_01.v Parsing Verilog input from `memory_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_01.v:5$2'. 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$7' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$9' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$10' with positive edge clock. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_01.v:5$2'. Cleaned up 0 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 3 unused cells and 7 unused wires. 4. Executing MEMORY pass. 4.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing test.mem write port 0. 4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\mem'[0] in module `\test': merging output FF to cell. Write port 0: non-transparent. 4.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 9 unused wires. 4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \mem in module \test: created 2 $dff cells and 0 static cells of width 8. Extracted data FF from read port 0 of test.mem: $\mem$rdreg[0] read interface: 1 $dff and 1 $mux cells. write interface: 2 write mux blocks. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 6 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\mem[1]$23 ($dff) from module test (D = \DIN, Q = \mem[1]). Adding EN signal on $memory\mem[0]$21 ($dff) from module test (D = \DIN, Q = \mem[0]). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 2 unused cells and 2 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Rerunning OPT passes. (Maybe there is more to do..) 5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.20. Executing OPT_DFF pass (perform DFF optimizations). 5.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.22. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.23. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_01.dot' > 'memory_01.pdf.new' && mv 'memory_01.pdf.new' 'memory_01.pdf' End of script. Logfile hash: d4215140a5, CPU: user 0.03s system 0.00s, MEM: 12.18 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 91% 1x show (0 sec), 2% 5x opt_expr (0 sec), ... ../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format pdf' -- -- Executing script file `memory_02.ys' -- 1. Executing Verilog-2005 frontend: memory_02.v Parsing Verilog input from `memory_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$memory_02.v:17$10 in module test. Marked 1 switch rules as full_case in process $proc$memory_02.v:13$3 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 8 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_02.v:24$19'. Creating decoders for process `\test.$proc$memory_02.v:21$17'. Creating decoders for process `\test.$proc$memory_02.v:17$10'. 1/3: $1$memwr$\memory$memory_02.v:19$2_EN[7:0]$16 2/3: $1$memwr$\memory$memory_02.v:19$2_DATA[7:0]$15 3/3: $1$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$14 Creating decoders for process `\test.$proc$memory_02.v:13$3'. 1/3: $1$memwr$\memory$memory_02.v:15$1_EN[7:0]$9 2/3: $1$memwr$\memory$memory_02.v:15$1_DATA[7:0]$8 3/3: $1$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$7 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$19'. created $dff cell `$procdff$39' with positive edge clock. Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$17'. created $dff cell `$procdff$40' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$41' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$42' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$43' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$44' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$45' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$46' with positive edge clock. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_02.v:24$19'. Removing empty process `test.$proc$memory_02.v:21$17'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$10'. Removing empty process `test.$proc$memory_02.v:17$10'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. Removing empty process `test.$proc$memory_02.v:13$3'. Cleaned up 2 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 6 unused cells and 26 unused wires. 4. Executing MEMORY pass. 4.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing test.memory write port 0. Analyzing test.memory write port 1. 4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\memory'[0] in module `\test': merging output FF to cell. Checking read port `\memory'[1] in module `\test': merging output FF to cell. 4.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 2 unused cells and 18 unused wires. 4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory test.memory by address: Consolidating write ports of memory test.memory by address: Consolidating write ports of memory test.memory using sat-based resource sharing: 4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.10. Executing MEMORY_COLLECT pass (generating $mem cells). 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Consolidated identical input bits for $mux cell $procmux$31: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } Consolidated identical input bits for $mux cell $procmux$22: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] } Optimizing cells in module \test. Performed a total of 2 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 4 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Rerunning OPT passes. (Maybe there is more to do..) 5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.20. Executing OPT_DFF pass (perform DFF optimizations). 5.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.22. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.23. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_02.dot'. Dumping module test to page 1. Warning: WIDTHLABEL { \RD1_ADDR \RD2_ADDR } 16 Warning: WIDTHLABEL { \RD1_CLK \RD2_CLK } 2 Warning: WIDTHLABEL { \RD1_DATA \RD2_DATA } 16 Warning: WIDTHLABEL { \WR1_ADDR \WR2_ADDR } 16 Warning: WIDTHLABEL { \WR1_CLK \WR2_CLK } 2 Warning: WIDTHLABEL { \WR1_DATA \WR2_DATA } 16 Warning: WIDTHLABEL { \WR1_WEN \WR1_WEN \WR1_WEN \WR1_WEN \WR1_WEN \WR1_WEN \WR1_WEN \WR1_WEN \WR2_WEN \WR2_WEN \WR2_WEN \WR2_WEN \WR2_WEN \WR2_WEN \WR2_WEN \WR2_WEN } 16 Exec: dot -Tpdf 'memory_02.dot' > 'memory_02.pdf.new' && mv 'memory_02.pdf.new' 'memory_02.pdf' Warnings: 7 unique messages, 7 total End of script. Logfile hash: 38542be5e8, CPU: user 0.03s system 0.01s, MEM: 12.27 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 89% 1x show (0 sec), 2% 5x opt_expr (0 sec), ... ../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' -- -- Executing script file `techmap_01.ys' -- 1. Executing Verilog-2005 frontend: techmap_01.v Parsing Verilog input from `techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: techmap_01_map.v Parsing Verilog input from `techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `techmap_01.dot'. Dumping module test to page 1. Warning: WIDTHLABEL \a [15:0] 16 Warning: WIDTHLABEL \b [15:0] 16 Warning: WIDTHLABEL { $add$techmap_01.v:3$1.genblk1.S1 [16] \y [15:0] } 17 Warning: WIDTHLABEL \a [31:16] 16 Warning: WIDTHLABEL \b [31:16] 16 Warning: WIDTHLABEL $add$techmap_01.v:3$1.genblk1.S1 [16] 1 Warning: WIDTHLABEL \y [31:16] 16 Exec: dot -Tpdf 'techmap_01.dot' > 'techmap_01.pdf.new' && mv 'techmap_01.pdf.new' 'techmap_01.pdf' Warnings: 7 unique messages, 7 total End of script. Logfile hash: f7cde0dc8c, CPU: user 0.01s system 0.01s, MEM: 12.12 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 1% 1x techmap (0 sec), ... ../../yosys -p 'script abc_01.ys; show -notitle -prefix abc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Running command `script abc_01.ys; show -notitle -prefix abc_01 -format pdf' -- -- Executing script file `abc_01.ys' -- 1. Executing Verilog-2005 frontend: abc_01.v Parsing Verilog input from `abc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: abc_01_cells.v Parsing Verilog input from `abc_01_cells.v' to AST representation. Generating RTLIL representation for module `\BUF'. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Generating RTLIL representation for module `\DFFSR'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 3 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$abc_01.v:5$1'. 4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\y' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$3' with positive edge clock. Creating register for signal `\test.\q1' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\q2' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$5' with positive edge clock. 4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$abc_01.v:5$1'. Cleaned up 0 empty switches. 4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend: /build/yosys-0.23/share/techmap.v Parsing Verilog input from `/build/yosys-0.23/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 6.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $reduce_xor. Using extmapper simplemap for cells of type $dff. No more expansions possible. 7. Executing ABC pass (technology mapping using ABC). 7.1. Summary of detected clock domains: 9 cells in clk=\clk, en={ }, arst={ }, srst={ } 7.2. Extracting gate netlist of module `\test' to `/input.blif'.. Found matching posedge clock domain: \clk Extracted 9 gates and 12 wires to a netlist network with 3 inputs and 1 outputs. 7.2.1. Executing ABC. Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_ExSyn/abc_01_cells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR". ABC: Library "demo" from "/manual/PRESENTATION_ExSyn/abc_01_cells.lib" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + &get -n ABC: Warning: 7 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 7.2.2. Re-integrating ABC results. ABC RESULTS: _dff_ cells: 3 ABC RESULTS: NOT cells: 3 ABC RESULTS: NAND cells: 2 ABC RESULTS: NOR cells: 5 ABC RESULTS: BUF cells: 3 ABC RESULTS: internal signals: 8 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 1 Removing temp directory. Removed 0 unused cells and 9 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `abc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'abc_01.dot' > 'abc_01.pdf.new' && mv 'abc_01.pdf.new' 'abc_01.pdf' End of script. Logfile hash: 12acbed0ed, CPU: user 0.05s system 0.01s, MEM: 14.18 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 72% 1x show (0 sec), 15% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_ExSyn' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_ExSyn/abc_01.pdf PRESENTATION_ExSyn/memory_01.pdf PRESENTATION_ExSyn/memory_02.pdf PRESENTATION_ExSyn/opt_01.pdf PRESENTATION_ExSyn/opt_02.pdf PRESENTATION_ExSyn/opt_03.pdf PRESENTATION_ExSyn/opt_04.pdf PRESENTATION_ExSyn/proc_01.pdf PRESENTATION_ExSyn/proc_02.pdf PRESENTATION_ExSyn/proc_03.pdf PRESENTATION_ExSyn/techmap_01.pdf + make -C PRESENTATION_ExAdv make[3]: Entering directory '/build/yosys-0.23/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys select.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `select.ys' -- 1. Executing Verilog-2005 frontend: select.v Parsing Verilog input from `select.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 2 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$select.v:7$1'. 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\b' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.\c' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$9' with positive edge clock. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$select.v:7$1'. Cleaned up 0 empty switches. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_DFF pass (perform DFF optimizations). 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 7 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `select.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'select.dot' > 'select.pdf.new' && mv 'select.pdf.new' 'select.pdf' End of script. Logfile hash: 75f2ae3a3a, CPU: user 0.02s system 0.01s, MEM: 12.17 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 94% 1x show (0 sec), 1% 4x opt_expr (0 sec), ... ../../yosys red_or3x1_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `red_or3x1_test.ys' -- 1. Executing Verilog-2005 frontend: red_or3x1_test.v Parsing Verilog input from `red_or3x1_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: red_or3x1_map.v Parsing Verilog input from `red_or3x1_map.v' to AST representation. Generating RTLIL representation for module `\$reduce_or'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$53153ae57fdb25b25475408a64760d7986ecfb0e\$reduce_or for cells of type $reduce_or. Using template $paramod$fe2472242c070f3b22e97f6c8c19c3569e575d97\$reduce_or for cells of type $reduce_or. Using template $paramod$1a3ccc6b2ad940e0a4ee2fb765a3adeb638fb7f0\$reduce_or for cells of type $reduce_or. No more expansions possible. Removed 0 unused cells and 18 unused wires. 4. Executing SPLITNETS pass (splitting up multi-bit signals). 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v Parsing Verilog input from `red_or3x1_cells.v' to AST representation. Generating RTLIL representation for module `\OR3X1'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `red_or3x1.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'red_or3x1.dot' > 'red_or3x1.pdf.new' && mv 'red_or3x1.pdf.new' 'red_or3x1.pdf' End of script. Logfile hash: 129023a082, CPU: user 0.01s system 0.00s, MEM: 11.98 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 1% 1x techmap (0 sec), ... ../../yosys sym_mul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `sym_mul_test.ys' -- 1. Executing Verilog-2005 frontend: sym_mul_test.v Parsing Verilog input from `sym_mul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. No more expansions possible. Removed 0 unused cells and 6 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `sym_mul.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'sym_mul.dot' > 'sym_mul.pdf.new' && mv 'sym_mul.pdf.new' 'sym_mul.pdf' End of script. Logfile hash: 772afb568b, CPU: user 0.01s system 0.00s, MEM: 12.03 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys mymul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `mymul_test.ys' -- 1. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mymul_map.v Parsing Verilog input from `mymul_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\$mul for cells of type $mul. Using template $paramod\MYMUL\WIDTH=32'00000000000000000000000000000010 for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 10 unused wires. Renaming module \test to \test_mapped. 4. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 5. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". 6. Executing FLATTEN pass (flatten design). 7. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof-constraint: \trigger = 1'0 Final proof equation: \trigger = 1'0 Solving problem with 107 variables and 283 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ 8. Executing SPLITNETS pass (splitting up multi-bit signals). 9. Generating Graphviz representation of design. Writing dot description to `mymul.dot'. Dumping module test_mapped to page 1. Warning: WIDTHLABEL { \B [0] 1'0 } 2 Exec: dot -Tpdf 'mymul.dot' > 'mymul.pdf.new' && mv 'mymul.pdf.new' 'mymul.pdf' Warnings: 1 unique messages, 1 total End of script. Logfile hash: 126d691da5, CPU: user 0.01s system 0.01s, MEM: 12.62 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 94% 1x show (0 sec), 1% 2x clean (0 sec), ... ../../yosys mulshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `mulshift_test.ys' -- 1. Executing Verilog-2005 frontend: mulshift_test.v Parsing Verilog input from `mulshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mulshift_map.v Parsing Verilog input from `mulshift_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. Using template $paramod$fb3c811cfd9dc2fc74fe40190dfcd365f04584f7\MYMUL for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 16 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `mulshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'mulshift.dot' > 'mulshift.pdf.new' && mv 'mulshift.pdf.new' 'mulshift.pdf' End of script. Logfile hash: e867b57f97, CPU: user 0.02s system 0.01s, MEM: 12.50 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 92% 1x show (0 sec), 2% 3x clean (0 sec), ... ../../yosys addshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `addshift_test.ys' -- 1. Executing Verilog-2005 frontend: addshift_test.v Parsing Verilog input from `addshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: addshift_map.v Parsing Verilog input from `addshift_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$ba28896eb640c0d0dd7116971c6c5dc347170a6c\$add for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `addshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'addshift.dot' > 'addshift.pdf.new' && mv 'addshift.pdf.new' 'addshift.pdf' End of script. Logfile hash: d1e94967df, CPU: user 0.01s system 0.00s, MEM: 11.83 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys macc_simple_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `macc_simple_test.ys' -- 1. Executing Verilog-2005 frontend: macc_simple_test.v Parsing Verilog input from `macc_simple_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 3. Generating Graphviz representation of design. 3.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 3.2. Continuing show pass. Writing dot description to `macc_simple_test_00a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00a.dot' > 'macc_simple_test_00a.pdf.new' && mv 'macc_simple_test_00a.pdf.new' 'macc_simple_test_00a.pdf' 4. Executing EXTRACT pass (map subcircuits to cells). 4.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 4.2.4. Executing PROC_INIT pass (extract init attributes). 4.2.5. Executing PROC_ARST pass (detect async resets in processes). 4.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 4.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 4.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 4.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 4.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$8 Removed 0 unused cells and 1 unused wires. 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `macc_simple_test_00b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00b.dot' > 'macc_simple_test_00b.pdf.new' && mv 'macc_simple_test_00b.pdf.new' 'macc_simple_test_00b.pdf' 6. Executing Verilog-2005 frontend: macc_simple_test_01.v Parsing Verilog input from `macc_simple_test_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 7. Executing HIERARCHY pass (managing design hierarchy). 7.1. Analyzing design hierarchy.. Top module: \test 7.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 8. Generating Graphviz representation of design. 8.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 8.2. Continuing show pass. Writing dot description to `macc_simple_test_01a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01a.dot' > 'macc_simple_test_01a.pdf.new' && mv 'macc_simple_test_01a.pdf.new' 'macc_simple_test_01a.pdf' 9. Executing EXTRACT pass (map subcircuits to cells). 9.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 9.2. Executing PROC pass (convert processes to netlists). 9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 9.2.4. Executing PROC_INIT pass (extract init attributes). 9.2.5. Executing PROC_ARST pass (detect async resets in processes). 9.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 9.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 9.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 9.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 9.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 9.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 9.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 9.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 9.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 9.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$19 Removed 0 unused cells and 1 unused wires. 10. Generating Graphviz representation of design. 10.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 10.2. Continuing show pass. Writing dot description to `macc_simple_test_01b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01b.dot' > 'macc_simple_test_01b.pdf.new' && mv 'macc_simple_test_01b.pdf.new' 'macc_simple_test_01b.pdf' 11. Executing Verilog-2005 frontend: macc_simple_test_02.v Parsing Verilog input from `macc_simple_test_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 12. Executing HIERARCHY pass (managing design hierarchy). 12.1. Analyzing design hierarchy.. Top module: \test 12.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 13. Generating Graphviz representation of design. 13.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 13.2. Continuing show pass. Writing dot description to `macc_simple_test_02a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02a.dot' > 'macc_simple_test_02a.pdf.new' && mv 'macc_simple_test_02a.pdf.new' 'macc_simple_test_02a.pdf' 14. Executing EXTRACT pass (map subcircuits to cells). 14.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 14.2. Executing PROC pass (convert processes to netlists). 14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 14.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 14.2.4. Executing PROC_INIT pass (extract init attributes). 14.2.5. Executing PROC_ARST pass (detect async resets in processes). 14.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 14.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 14.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 14.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 14.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 14.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 14.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 14.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 14.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 2 matches. 14.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$23 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$30 Match #1: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$31 Removed 0 unused cells and 2 unused wires. 15. Generating Graphviz representation of design. 15.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 15.2. Continuing show pass. Writing dot description to `macc_simple_test_02b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02b.dot' > 'macc_simple_test_02b.pdf.new' && mv 'macc_simple_test_02b.pdf.new' 'macc_simple_test_02b.pdf' 16. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 17. Executing HIERARCHY pass (managing design hierarchy). 17.1. Analyzing design hierarchy.. Top module: \macc_16_16_32 17.2. Analyzing design hierarchy.. Top module: \macc_16_16_32 Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_simple_xmap.dot'. Dumping module macc_16_16_32 to page 1. Exec: dot -Tpdf 'macc_simple_xmap.dot' > 'macc_simple_xmap.pdf.new' && mv 'macc_simple_xmap.pdf.new' 'macc_simple_xmap.pdf' End of script. Logfile hash: 4903010725, CPU: user 0.05s system 0.00s, MEM: 12.14 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 7x show (1 sec), 0% 7x clean (0 sec), ... ../../yosys macc_xilinx_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `macc_xilinx_test.ys' -- 1. Executing Verilog-2005 frontend: macc_xilinx_test.v Parsing Verilog input from `macc_xilinx_test.v' to AST representation. Generating RTLIL representation for module `\test1'. Generating RTLIL representation for module `\test2'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `$__mul_wrapper'. Generating RTLIL representation for module `$__add_wrapper'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 4. Executing HIERARCHY pass (managing design hierarchy). Removed 0 unused cells and 2 unused wires. 5. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1a.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1a.dot' > 'macc_xilinx_test1a.pdf.new' && mv 'macc_xilinx_test1a.pdf.new' 'macc_xilinx_test1a.pdf' 6. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2a.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2a.dot' > 'macc_xilinx_test2a.pdf.new' && mv 'macc_xilinx_test2a.pdf.new' 'macc_xilinx_test2a.pdf' 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 7.2. Continuing TECHMAP pass. Using template $paramod$cb31b7e2c27e209b1e5fc8ca3c6ec22d65eb4c07\mul_swap_ports for cells of type $mul. No more expansions possible. Removed 0 unused cells and 8 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1b.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1b.dot' > 'macc_xilinx_test1b.pdf.new' && mv 'macc_xilinx_test1b.pdf.new' 'macc_xilinx_test1b.pdf' 9. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2b.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2b.dot' > 'macc_xilinx_test2b.pdf.new' && mv 'macc_xilinx_test2b.pdf.new' 'macc_xilinx_test2b.pdf' 10. Executing TECHMAP pass (map to technology primitives). 10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 10.2. Continuing TECHMAP pass. Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\mul_wrap for cells of type $mul. Using template $paramod$48197a291a9e3825142389e9d2e41385cae2467c\mul_wrap for cells of type $mul. Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\add_wrap for cells of type $add. No more expansions possible. 11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } Removed 0 unused cells and 56 unused wires. 12. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1c.dot'. Dumping module test1 to page 1. Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:5$1_Y } 48 Warning: WIDTHLABEL { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } 48 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } 48 Warning: WIDTHLABEL { $techmap26$add$macc_xilinx_test.v:5$5.Y_48 [47:42] \y } 48 Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } 48 Warning: WIDTHLABEL { 2'00 \e } 18 Warning: WIDTHLABEL { 9'000000000 \f } 25 Warning: WIDTHLABEL { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } 48 Exec: dot -Tpdf 'macc_xilinx_test1c.dot' > 'macc_xilinx_test1c.pdf.new' && mv 'macc_xilinx_test1c.pdf.new' 'macc_xilinx_test1c.pdf' 13. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2c.dot'. Dumping module test2 to page 1. Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:12$6_Y } 48 Warning: WIDTHLABEL { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } 48 Warning: WIDTHLABEL { $techmap22$add$macc_xilinx_test.v:12$10.Y_48 [47:42] \y } 48 Warning: WIDTHLABEL { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } 48 Warning: WIDTHLABEL { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } 48 Warning: WIDTHLABEL { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } 48 Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } 48 Warning: WIDTHLABEL { 2'00 \e } 18 Warning: WIDTHLABEL { 9'000000000 \f } 25 Warning: WIDTHLABEL { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } 48 Exec: dot -Tpdf 'macc_xilinx_test2c.dot' > 'macc_xilinx_test2c.pdf.new' && mv 'macc_xilinx_test2c.pdf.new' 'macc_xilinx_test2c.pdf' 14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 15. Executing TECHMAP pass (map to technology primitives). 15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 15.2. Continuing TECHMAP pass. No more expansions possible. 16. Executing TECHMAP pass (map to technology primitives). 16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 16.2. Continuing TECHMAP pass. Using template $paramod$81421da67e3cf07e7ac8b39f28efc75ee750e82a\mul_wrap for cells of type $mul. Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\add_wrap for cells of type $add. No more expansions possible. Removed 0 unused cells and 17 unused wires. 17. Executing EXTRACT pass (map subcircuits to cells). 17.1. Creating graphs for SubCircuit library. Creating needle graph needle_DSP48_MACC. Creating haystack graph haystack_$__add_wrapper. Creating haystack graph haystack_$__mul_wrapper. Creating haystack graph haystack_DSP48_MACC. Creating haystack graph haystack_test1. Creating haystack graph haystack_test2. 17.2. Running solver from SubCircuit library. Solving for needle_DSP48_MACC in haystack_$__add_wrapper. Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. Solving for needle_DSP48_MACC in haystack_DSP48_MACC. Solving for needle_DSP48_MACC in haystack_test1. Solving for needle_DSP48_MACC in haystack_test2. Found 3 matches. 17.3. Substitute SubCircuits with cells. Match #0: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$35 Match #1: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$36 Match #2: (needle_DSP48_MACC in haystack_test2) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$37 Removed 0 unused cells and 6 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1d.dot'. Dumping module test1 to page 1. Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:5$1_Y } 48 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { 2'00 \e } 18 Warning: WIDTHLABEL { 9'000000000 \f } 25 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { $techmap26$add$macc_xilinx_test.v:5$5.Y_48 [47:42] \y } 48 Exec: dot -Tpdf 'macc_xilinx_test1d.dot' > 'macc_xilinx_test1d.pdf.new' && mv 'macc_xilinx_test1d.pdf.new' 'macc_xilinx_test1d.pdf' 19. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2d.dot'. Dumping module test2 to page 1. Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:12$6_Y } 48 Warning: WIDTHLABEL { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } 48 Warning: WIDTHLABEL { $techmap22$add$macc_xilinx_test.v:12$10.Y_48 [47:42] \y } 48 Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } 48 Warning: WIDTHLABEL { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } 48 Warning: WIDTHLABEL { 2'00 \e } 18 Warning: WIDTHLABEL { 9'000000000 \f } 25 Warning: WIDTHLABEL { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } 48 Exec: dot -Tpdf 'macc_xilinx_test2d.dot' > 'macc_xilinx_test2d.pdf.new' && mv 'macc_xilinx_test2d.pdf.new' 'macc_xilinx_test2d.pdf' 20. Executing TECHMAP pass (map to technology primitives). 20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `\$__mul_wrapper'. Generating RTLIL representation for module `\$__add_wrapper'. Successfully finished Verilog frontend. 20.2. Continuing TECHMAP pass. Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\$__mul_wrapper for cells of type $__mul_wrapper. Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\$__add_wrapper for cells of type $__add_wrapper. No more expansions possible. Removed 0 unused cells and 14 unused wires. 21. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1e.dot'. Dumping module test1 to page 1. Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:5$1_Y } 48 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { 2'00 \e } 18 Warning: WIDTHLABEL { 9'000000000 \f } 25 Warning: WIDTHLABEL { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } 48 Warning: WIDTHLABEL { $techmap26$add$macc_xilinx_test.v:5$5.Y_48 [47:42] \y } 48 Exec: dot -Tpdf 'macc_xilinx_test1e.dot' > 'macc_xilinx_test1e.pdf.new' && mv 'macc_xilinx_test1e.pdf.new' 'macc_xilinx_test1e.pdf' 22. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2e.dot'. Dumping module test2 to page 1. Warning: WIDTHLABEL { 2'00 \d } 18 Warning: WIDTHLABEL { 5'00000 \c } 25 Warning: WIDTHLABEL { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } 48 Warning: WIDTHLABEL { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } 48 Exec: dot -Tpdf 'macc_xilinx_test2e.dot' > 'macc_xilinx_test2e.pdf.new' && mv 'macc_xilinx_test2e.pdf.new' 'macc_xilinx_test2e.pdf' 23. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_xmap.dot'. Dumping module DSP48_MACC to page 1. Exec: dot -Tpdf 'macc_xilinx_xmap.dot' > 'macc_xilinx_xmap.pdf.new' && mv 'macc_xilinx_xmap.pdf.new' 'macc_xilinx_xmap.pdf' Warnings: 15 unique messages, 54 total End of script. Logfile hash: 1adef8c574, CPU: user 0.11s system 0.01s, MEM: 13.29 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 11x show (2 sec), 1% 12x clean (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_ExAdv' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_ExAdv/addshift.pdf PRESENTATION_ExAdv/macc_simple_test_00a.pdf PRESENTATION_ExAdv/macc_simple_test_00b.pdf PRESENTATION_ExAdv/macc_simple_test_01a.pdf PRESENTATION_ExAdv/macc_simple_test_01b.pdf PRESENTATION_ExAdv/macc_simple_test_02a.pdf PRESENTATION_ExAdv/macc_simple_test_02b.pdf PRESENTATION_ExAdv/macc_simple_xmap.pdf PRESENTATION_ExAdv/macc_xilinx_test1a.pdf PRESENTATION_ExAdv/macc_xilinx_test1b.pdf PRESENTATION_ExAdv/macc_xilinx_test1c.pdf PRESENTATION_ExAdv/macc_xilinx_test1d.pdf PRESENTATION_ExAdv/macc_xilinx_test1e.pdf PRESENTATION_ExAdv/macc_xilinx_test2a.pdf PRESENTATION_ExAdv/macc_xilinx_test2b.pdf PRESENTATION_ExAdv/macc_xilinx_test2c.pdf PRESENTATION_ExAdv/macc_xilinx_test2d.pdf PRESENTATION_ExAdv/macc_xilinx_test2e.pdf PRESENTATION_ExAdv/macc_xilinx_xmap.pdf PRESENTATION_ExAdv/mulshift.pdf PRESENTATION_ExAdv/mymul.pdf PRESENTATION_ExAdv/red_or3x1.pdf PRESENTATION_ExAdv/select.pdf PRESENTATION_ExAdv/sym_mul.pdf + make -C PRESENTATION_ExOth make[3]: Entering directory '/build/yosys-0.23/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys scrambler.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `scrambler.ys' -- 1. Executing Verilog-2005 frontend: scrambler.v Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 2 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'. 1/1: $1\xs[31:0] 3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$12' with positive edge clock. Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$13' with positive edge clock. 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'. Removing empty process `scrambler.$proc$scrambler.v:6$1'. Cleaned up 1 empty switch. 3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module scrambler. Removed 0 unused cells and 5 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \scrambler.. 4.2. Continuing SUBMOD pass. Creating submodule xorshift32 (\xorshift32) of module \scrambler. signal $xor$scrambler.v:9$3_Y: internal signal $shr$scrambler.v:10$4_Y: internal signal $xor$scrambler.v:10$5_Y: internal signal $shl$scrambler.v:11$6_Y: internal signal $0\xs[31:0]: output \n1 signal $1\xs[31:0]: input \n2 cell $xor$scrambler.v:9$3 ($xor) cell $xor$scrambler.v:11$7 ($xor) cell $xor$scrambler.v:10$5 ($xor) 5. Generating Graphviz representation of design. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. Warning: WIDTHLABEL $0\xs[31:0] [0] 1 Exec: dot -Tpdf 'scrambler_p01.dot' > 'scrambler_p01.pdf.new' && mv 'scrambler_p01.pdf.new' 'scrambler_p01.pdf' 6. Generating Graphviz representation of design. Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. Warning: WIDTHLABEL { $shr$scrambler.v:10$4_Y [14:0] $xor$scrambler.v:9$3_Y [16:0] } 32 Warning: WIDTHLABEL { 17'00000000000000000 $shr$scrambler.v:10$4_Y [14:0] } 32 Warning: WIDTHLABEL { $xor$scrambler.v:10$5_Y [31:27] $shl$scrambler.v:11$6_Y [31:5] } 32 Warning: WIDTHLABEL { $xor$scrambler.v:10$5_Y [31:27] $shl$scrambler.v:11$6_Y [31:5] } 32 Warning: WIDTHLABEL { $shl$scrambler.v:11$6_Y [31:5] 5'00000 } 32 Warning: WIDTHLABEL { \n2 [18:0] 13'0000000000000 } 32 Warning: WIDTHLABEL { $shr$scrambler.v:10$4_Y [14:0] $xor$scrambler.v:9$3_Y [16:0] } 32 Exec: dot -Tpdf 'scrambler_p02.dot' > 'scrambler_p02.pdf.new' && mv 'scrambler_p02.pdf.new' 'scrambler_p02.pdf' echo on yosys> cd xorshift32 yosys [xorshift32]> rename n2 in Renaming wire n2 to in in module xorshift32. yosys [xorshift32]> rename n1 out Renaming wire n1 to out in module xorshift32. yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out 8. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 67634689. yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Import set-constraint: \out = 632435482 Final constraint equation: \out = 632435482 Imported 3 cells to SAT database. Solving problem with 665 variables and 1735 clauses.. SAT solving finished - model found: Signal Name Dec Hex Bin --------------- ----------- --------- ----------------------------------- \in 745495504 2c6f5bd0 00101100011011110101101111010000 \out 632435482 25b2331a 00100101101100100011001100011010 Warnings: 6 unique messages, 8 total End of script. Logfile hash: cb8ee0bc24, CPU: user 0.03s system 0.00s, MEM: 12.54 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 2x show (0 sec), 1% 1x sat (0 sec), ... ../../yosys -l equiv.log_new equiv.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `equiv.ys' -- 1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Renaming module \test to \test_mapped. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01_map.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. No more expansions possible. 4. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test_orig" and gate cell "test_mapped". 5. Executing FLATTEN pass (flatten design). 6. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof for assert: $auto$miter.cc:229:create_miter_equiv$6 when 1'1. Import show expression: \in_b Import show expression: \in_a Import show expression: \trigger Import show expression: \gate_y Import show expression: \gold_y Solving problem with 945 variables and 2505 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ End of script. Logfile hash: 40f4b7a027, CPU: user 0.02s system 0.00s, MEM: 12.88 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 77% 1x sat (0 sec), 13% 1x techmap (0 sec), ... mv equiv.log_new equiv.log ../../yosys -l axis_test.log_new axis_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.23 (git sha1 7ce5011c24b) -- Executing script file `axis_test.ys' -- 1. Executing Verilog-2005 frontend: axis_master.v Parsing SystemVerilog input from `axis_master.v' to AST representation. Generating RTLIL representation for module `\axis_master'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: axis_test.v Parsing SystemVerilog input from `axis_test.v' to AST representation. Generating RTLIL representation for module `\axis_test'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master 3.2. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master Removed 0 unused modules. Module axis_test directly or indirectly contains formal properties -> setting "keep" attribute. Mapping positional arguments of cell axis_test.uut (axis_master). 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$axis_master.v:7$1 in module axis_master. Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 14 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\axis_test.$proc$axis_test.v:0$98'. Set init value: $formal$axis_test.v:22$23_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$96'. Set init value: $formal$axis_test.v:21$22_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$94'. Set init value: $formal$axis_test.v:20$21_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$92'. Set init value: $formal$axis_test.v:19$20_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$90'. Set init value: $formal$axis_test.v:18$19_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$88'. Set init value: $formal$axis_test.v:17$18_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$86'. Set init value: $formal$axis_test.v:16$17_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$84'. Set init value: $formal$axis_test.v:15$16_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$82'. Set init value: $formal$axis_test.v:14$15_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$80'. Set init value: $formal$axis_test.v:13$14_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:7$79'. Set init value: \aresetn = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:6$78'. Set init value: \counter = 0 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\axis_test.$proc$axis_test.v:0$98'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$96'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$94'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$92'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$90'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$88'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$86'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$84'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$82'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$80'. Creating decoders for process `\axis_test.$proc$axis_test.v:7$79'. Creating decoders for process `\axis_test.$proc$axis_test.v:6$78'. Creating decoders for process `\axis_test.$proc$axis_test.v:11$24'. 1/21: $0$formal$axis_test.v:13$14_EN[0:0]$26 2/21: $0$formal$axis_test.v:13$14_CHECK[0:0]$25 3/21: $0$formal$axis_test.v:14$15_EN[0:0]$28 4/21: $0$formal$axis_test.v:14$15_CHECK[0:0]$27 5/21: $0$formal$axis_test.v:15$16_EN[0:0]$30 6/21: $0$formal$axis_test.v:15$16_CHECK[0:0]$29 7/21: $0$formal$axis_test.v:16$17_EN[0:0]$32 8/21: $0$formal$axis_test.v:16$17_CHECK[0:0]$31 9/21: $0$formal$axis_test.v:17$18_EN[0:0]$34 10/21: $0$formal$axis_test.v:17$18_CHECK[0:0]$33 11/21: $0$formal$axis_test.v:18$19_EN[0:0]$36 12/21: $0$formal$axis_test.v:18$19_CHECK[0:0]$35 13/21: $0$formal$axis_test.v:19$20_EN[0:0]$38 14/21: $0$formal$axis_test.v:19$20_CHECK[0:0]$37 15/21: $0$formal$axis_test.v:20$21_EN[0:0]$40 16/21: $0$formal$axis_test.v:20$21_CHECK[0:0]$39 17/21: $0$formal$axis_test.v:21$22_EN[0:0]$42 18/21: $0$formal$axis_test.v:21$22_CHECK[0:0]$41 19/21: $0$formal$axis_test.v:22$23_EN[0:0]$44 20/21: $0$formal$axis_test.v:22$23_CHECK[0:0]$43 21/21: $0\counter[31:0] Creating decoders for process `\axis_master.$proc$axis_master.v:7$1'. 1/4: $2\state[31:0] 2/4: $1\state[31:0] 3/4: $0\tdata[7:0] 4/4: $0\tvalid[0:0] 4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\axis_test.\aresetn' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$209' with positive edge clock. Creating register for signal `\axis_test.\counter' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$210' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$211' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$212' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$213' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$214' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$215' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$216' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$217' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$218' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$219' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$220' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$221' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$222' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$223' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$224' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$225' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$226' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$227' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$228' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$229' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$230' with positive edge clock. Creating register for signal `\axis_master.\tvalid' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$231' with positive edge clock. Creating register for signal `\axis_master.\tdata' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$232' with positive edge clock. Creating register for signal `\axis_master.\state' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$233' with positive edge clock. 4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `axis_test.$proc$axis_test.v:0$98'. Removing empty process `axis_test.$proc$axis_test.v:0$96'. Removing empty process `axis_test.$proc$axis_test.v:0$94'. Removing empty process `axis_test.$proc$axis_test.v:0$92'. Removing empty process `axis_test.$proc$axis_test.v:0$90'. Removing empty process `axis_test.$proc$axis_test.v:0$88'. Removing empty process `axis_test.$proc$axis_test.v:0$86'. Removing empty process `axis_test.$proc$axis_test.v:0$84'. Removing empty process `axis_test.$proc$axis_test.v:0$82'. Removing empty process `axis_test.$proc$axis_test.v:0$80'. Removing empty process `axis_test.$proc$axis_test.v:7$79'. Removing empty process `axis_test.$proc$axis_test.v:6$78'. Found and cleaned up 11 empty switches in `\axis_test.$proc$axis_test.v:11$24'. Removing empty process `axis_test.$proc$axis_test.v:11$24'. Found and cleaned up 4 empty switches in `\axis_master.$proc$axis_master.v:7$1'. Removing empty process `axis_master.$proc$axis_master.v:7$1'. Cleaned up 15 empty switches. 4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module axis_test. Optimizing module axis_master. 5. Executing FLATTEN pass (flatten design). Deleting now unused module axis_master. Removed 1 unused cells and 92 unused wires. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up time step 1: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import set-constraint from init attribute: $formal$axis_test.v:13$14_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:14$15_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:15$16_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:16$17_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:17$18_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:18$19_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:19$20_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:20$21_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:21$22_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:22$23_EN = 1'0 Import set-constraint from init attribute: \aresetn = 1'0 Import set-constraint from init attribute: \counter = 0 Final init constraint equation: { \counter \aresetn $formal$axis_test.v:22$23_EN $formal$axis_test.v:21$22_EN $formal$axis_test.v:20$21_EN $formal$axis_test.v:19$20_EN $formal$axis_test.v:18$19_EN $formal$axis_test.v:17$18_EN $formal$axis_test.v:16$17_EN $formal$axis_test.v:15$16_EN $formal$axis_test.v:14$15_EN $formal$axis_test.v:13$14_EN } = 43'0000000000000000000000000000000000000000000 Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 2: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 3: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 4: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 5: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 6: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 7: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 8: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 9: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 10: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 11: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 12: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 13: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 14: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 15: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 16: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 17: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 18: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 19: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 20: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 21: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 22: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 23: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 24: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 25: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 26: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 27: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 28: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 29: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 30: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 31: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 32: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 33: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 34: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 35: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 36: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 37: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 38: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 39: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 40: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 41: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 42: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 43: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 44: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 45: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 46: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 47: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 48: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 49: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 50: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Solving problem with 135995 variables and 381779 clauses.. SAT proof finished - model found: FAIL! ______ ___ ___ _ _ _ _ (_____ \ / __) / __) (_) | | | | _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | | | ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_| | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ |_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_| Time Signal Name Dec Hex Bin ---- ------------------------------------ ----------- --------- ----------------------------------- init $formal$axis_test.v:13$14_CHECK 0 0 0 init $formal$axis_test.v:13$14_EN 0 0 0 init $formal$axis_test.v:14$15_CHECK 0 0 0 init $formal$axis_test.v:14$15_EN 0 0 0 init $formal$axis_test.v:15$16_CHECK 0 0 0 init $formal$axis_test.v:15$16_EN 0 0 0 init $formal$axis_test.v:16$17_CHECK 0 0 0 init $formal$axis_test.v:16$17_EN 0 0 0 init $formal$axis_test.v:17$18_CHECK 0 0 0 init $formal$axis_test.v:17$18_EN 0 0 0 init $formal$axis_test.v:18$19_CHECK 0 0 0 init $formal$axis_test.v:18$19_EN 0 0 0 init $formal$axis_test.v:19$20_CHECK 0 0 0 init $formal$axis_test.v:19$20_EN 0 0 0 init $formal$axis_test.v:20$21_CHECK 0 0 0 init $formal$axis_test.v:20$21_EN 0 0 0 init $formal$axis_test.v:21$22_CHECK 0 0 0 init $formal$axis_test.v:21$22_EN 0 0 0 init $formal$axis_test.v:22$23_CHECK 0 0 0 init $formal$axis_test.v:22$23_EN 0 0 0 init \aresetn 0 0 0 init \counter 0 0 00000000000000000000000000000000 init \uut.state 0 0 00000000000000000000000000000000 init \uut.tdata 64 40 01000000 init \uut.tvalid 1 1 1 End of script. Logfile hash: 47aa44b032, CPU: user 1.74s system 0.13s, MEM: 129.12 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x sat (1 sec), 0% 3x read_verilog (0 sec), ... mv axis_test.log_new axis_test.log make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_ExOth' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_ExOth/scrambler_p01.pdf PRESENTATION_ExOth/scrambler_p02.pdf + make -C PRESENTATION_Prog make[3]: Entering directory '/build/yosys-0.23/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys-config --exec --cxx -g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I../../share/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs my_cmd.cc: In member function 'virtual void {anonymous}::MyPass::execute(std::vector >, Yosys::RTLIL::Design*)': my_cmd.cc:17:26: warning: format '%zd' expects argument of type 'signed size_t', but argument 3 has type 'int' [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int my_cmd.cc:17:37: warning: format '%zd' expects argument of type 'signed size_t', but argument 4 has type 'int' [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v -- Parsing `absval_ref.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Storing AST representation for module `$abstract\absval_ref'. Successfully finished Verilog frontend. -- Running command `my_cmd foo bar' -- Arguments to my_cmd: my_cmd foo bar Modules in current design: $abstract\absval_ref (0 wires, 0 cells) End of script. Logfile hash: a25069ff9d, CPU: user 0.00s system 0.01s, MEM: 11.93 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 95% 2x read_verilog (0 sec), 2% 1x my_cmd (0 sec), ... mv test0.log_new test0.log ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v -- Parsing `absval_ref.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Storing AST representation for module `$abstract\absval_ref'. Successfully finished Verilog frontend. -- Running command `clean; test1; dump' -- Name of this module: absval autoidx 4 module \absval wire width 4 $auto$my_cmd.cc:41:execute$1 wire width 4 output 2 \y wire width 4 input 1 \a cell $mux $auto$my_cmd.cc:43:execute$3 parameter \WIDTH 4 connect \Y \y connect \S \a [3] connect \B $auto$my_cmd.cc:41:execute$1 connect \A \a end cell $neg $auto$my_cmd.cc:42:execute$2 parameter \Y_WIDTH 4 parameter \A_WIDTH 4 parameter \A_SIGNED 1 connect \Y $auto$my_cmd.cc:41:execute$1 connect \A \a end end attribute \cells_not_processed 1 attribute \src "absval_ref.v:1.1-3.10" module $abstract\absval_ref end End of script. Logfile hash: 01cda1039c, CPU: user 0.00s system 0.01s, MEM: 12.11 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 75% 1x clean (0 sec), 19% 2x read_verilog (0 sec), ... mv test1.log_new test1.log ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v -- Parsing `sigmap_test.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: sigmap_test.v Parsing Verilog input from `sigmap_test.v' to AST representation. Storing AST representation for module `$abstract\test'. Successfully finished Verilog frontend. -- Running command `hierarchy -top test; test2' -- 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing AST frontend in derive mode using pre-parsed AST for module `\test'. Generating RTLIL representation for module `\test'. 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removing unused module `$abstract\test'. Removed 1 unused modules. 0 0 0 1 1 1 Mapped signal x: \a 4. Doing important stuff! Log message #0. Log message #1. Log message #2. Log message #3. Log message #4. Log message #5. Log message #6. Log message #7. Log message #8. Log message #9. End of script. Logfile hash: 8350de3c5a, CPU: user 0.01s system 0.01s, MEM: 11.90 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 53% 2x read_verilog (0 sec), 36% 1x hierarchy (0 sec), ... mv test2.log_new test2.log make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_Prog' + set -ex + echo D:20221203221520Z D:20221203221520Z + pdflatex -shell-escape -halt-on-error '\pdfinfo{/CreationDate(D:20221203221520Z)/ModDate(D:20221203221520Z)}\input{presentation.tex}' This is pdfTeX, Version 3.141592653-2.6-1.40.24 (TeX Live 2022/Debian) (preloaded format=pdflatex) \write18 enabled. entering extended mode LaTeX2e <2022-11-01> patch level 1 L3 programming layer <2023-01-16> (./presentation.tex (/usr/share/texlive/texmf-dist/tex/latex/beamer/beamer.cls Document Class: beamer 2022/09/13 v3.68 A class for typesetting presentations (/usr/share/texlive/texmf-dist/tex/latex/beamer/beamerbasemodes.sty (/usr/share/texlive/texmf-dist/tex/latex/etoolbox/etoolbox.sty) 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(./PRESENTATION_ExSyn/memory_01.ys) (./PRESENTATION_ExSyn/memory_01.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [76 <./PRESENTATION_ExSyn/memory_01.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/memory_02.v) (./PRESENTATION_ExSyn/memory_02.ys)) Overfull \vbox (4.767pt too high) detected at line 290 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [77 <./PRESENTATION_ExSyn/memory_02.pdf>] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [78] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [79] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/techmap_01_map.v) Overfull \vbox (167.4641pt too high) detected at line 362 (./PRESENTATION_ExSyn/techmap_01.v) (./PRESENTATION_ExSyn/techmap_01.ys) Overfull \vbox (77.37361pt too high) detected at line 362 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [80 <./PRESENTATION_ExSyn/techmap_01.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [81] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [82] (./presentation.vrb (./PRESENTATION_ExSyn/abc_01.v) (./PRESENTATION_ExSyn/abc_01.ys) libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [83 <./PRESENTATION_ExSyn/abc_01.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [84] (./presentation.vrb Overfull \hbox (12.91054pt too wide) in paragraph at lines 6--7 [][][][][][][][][][][][][][][] Overfull \hbox (30.19075pt too wide) in paragraph at lines 24--25 [][][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (35.95082pt too wide) in paragraph at lines 28--29 [][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (44.59093pt too wide) in paragraph at lines 29--31 [][][][][][][][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [85] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [86]) (./PRESENTATION_ExAdv.tex Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [87] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [88] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [89] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [90] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [91] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [92] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [93] (./presentation.vrb Overfull \hbox (2.03467pt too wide) in paragraph at lines 7--8 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][] [][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [94] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [95] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [96] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [97] (./presentation.vrb (./PRESENTATION_ExAdv/select.v) (./PRESENTATION_ExAdv/select.ys) libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [98 <./PRESENTATION_ExAdv/select.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [99] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [100] (./PRESENTATION_ExAdv/red_or3x1_map.v) (./PRESENTATION_ExAdv/red_or3x1_map.v consecutive: ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [101] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... 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(./PRESENTATION_ExAdv/sym_mul_map.v) (./PRESENTATION_ExAdv/sym_mul_test.v ) (./PRESENTATION_ExAdv/sym_mul_test.ys) Overfull \vbox (2.16698pt too high) detected at line 321 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [104 <./PRESENTATION_ExAdv/sym_mul.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [105] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... 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(./PRESENTATION_ExSyn/proc_02.v) (./PRESENTATION_ExSyn/proc_02.ys)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [67 <./PRESENTATION_ExSyn/proc_02.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/proc_03.ys) (./PRESENTATION_ExSyn/proc_03.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [68 <./PRESENTATION_ExSyn/proc_03.pdf>] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [69] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/opt_01.ys) (./PRESENTATION_ExSyn/opt_01.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [70 <./PRESENTATION_ExSyn/opt_01.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/opt_02.ys) (./PRESENTATION_ExSyn/opt_02.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [71 <./PRESENTATION_ExSyn/opt_02.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/opt_03.ys) (./PRESENTATION_ExSyn/opt_03.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [72 <./PRESENTATION_ExSyn/opt_03.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/opt_04.v Overfull \hbox (3.65782pt too wide) in paragraph at lines 10--11 [][][][][][][][][][][][][][][] ) (./PRESENTATION_ExSyn/opt_04.ys)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [73 <./PRESENTATION_ExSyn/opt_04.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [74] (./presentation.vrb) Overfull \vbox (2.12932pt too high) detected at line 268 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [75] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/memory_01.ys) (./PRESENTATION_ExSyn/memory_01.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [76 <./PRESENTATION_ExSyn/memory_01.pdf>] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/memory_02.v) (./PRESENTATION_ExSyn/memory_02.ys)) Overfull \vbox (4.767pt too high) detected at line 290 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [77 <./PRESENTATION_ExSyn/memory_02.pdf>] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [78] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [79] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExSyn/techmap_01_map.v) Overfull \vbox (167.4641pt too high) detected at line 362 (./PRESENTATION_ExSyn/techmap_01.v) (./PRESENTATION_ExSyn/techmap_01.ys) Overfull \vbox (77.37361pt too high) detected at line 362 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [80 <./PRESENTATION_ExSyn/techmap_01.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [81] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [82] (./presentation.vrb (./PRESENTATION_ExSyn/abc_01.v) (./PRESENTATION_ExSyn/abc_01.ys) libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [83 <./PRESENTATION_ExSyn/abc_01.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [84] (./presentation.vrb Overfull \hbox (12.91054pt too wide) in paragraph at lines 6--7 [][][][][][][][][][][][][][][] Overfull \hbox (30.19075pt too wide) in paragraph at lines 24--25 [][][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (35.95082pt too wide) in paragraph at lines 28--29 [][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (44.59093pt too wide) in paragraph at lines 29--31 [][][][][][][][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [85] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [86]) (./PRESENTATION_ExAdv.tex Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [87] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [88] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [89] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [90] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [91] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [92] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [93] (./presentation.vrb Overfull \hbox (2.03467pt too wide) in paragraph at lines 7--8 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][] [][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [94] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [95] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [96] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [97] (./presentation.vrb (./PRESENTATION_ExAdv/select.v) (./PRESENTATION_ExAdv/select.ys) libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [98 <./PRESENTATION_ExAdv/select.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [99] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [100] (./PRESENTATION_ExAdv/red_or3x1_map.v) (./PRESENTATION_ExAdv/red_or3x1_map.v consecutive: ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [101] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/red_or3x1_test.ys consecutive: ) Overfull \hbox (1.39024pt too wide) in paragraph at lines 4--285 [][][][][][][][][][][] (./PRESENTATION_ExAdv/red_or3x1_test.v) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [102 <./PRESENTATION_ExAdv/red_or3x1.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [103] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/sym_mul_map.v) (./PRESENTATION_ExAdv/sym_mul_test.v ) (./PRESENTATION_ExAdv/sym_mul_test.ys) Overfull \vbox (2.16698pt too high) detected at line 321 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [104 <./PRESENTATION_ExAdv/sym_mul.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [105] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/mymul_map.v Overfull \hbox (9.76546pt too wide) in paragraph at lines 6--8 [][][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/mymul_test.v) (./PRESENTATION_ExAdv/mymul_test.ys) (./PRESENTATION_ExAdv/mymul_test.ys consecutive: ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [106 <./PRESENTATION_ExAdv/mymul.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [107] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/mulshift_map.v Overfull \hbox (34.2463pt too wide) in paragraph at lines 16--17 [][][][][][][][][][][][][][][][][][][][] Overfull \hbox (34.2463pt too wide) in paragraph at lines 20--21 [][][][][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/mulshift_test.v) (./PRESENTATION_ExAdv/mulshift_test.ys ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [108 <./PRESENTATION_ExAdv/mulshift.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [109] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/addshift_map.v Overfull \hbox (51.04654pt too wide) in paragraph at lines 16--17 [][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (54.40659pt too wide) in paragraph at lines 17--19 [][][][][][][][][] ) (./PRESENTATION_ExAdv/addshift_test.v) (./PRESENTATION_ExAdv/addshift_test.ys ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [110 <./PRESENTATION_ExAdv/addshift.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [111] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [112] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [113] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [114] (./presentation.vrb libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... (./PRESENTATION_ExAdv/macc_simple_test.v) (./PRESENTATION_ExAdv/macc_simple_xmap.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [115 <./PRESENTATION_ExAdv/macc_simple_test_00a.pdf> <./PRESENTATION_ExAdv/macc _simple_test_00b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_00b.pdf): PDF inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb (./PRESENTATION_ExAdv/macc_simple_test_01.v) Underfull \hbox (badness 10000) detected at line 3 []| (./PRESENTATION_ExAdv/macc_simple_test_02.v) Underfull \hbox (badness 10000) detected at line 4 []| libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [116 <./PRESENTATION_ExAdv/macc_simple_test_01a.pdf> <./PRESENTATION_ExAdv/macc _simple_test_02a.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_02a.pdf): PDF inclusion: multiple pdfs with page group included in a single page > <./PRESENTATION_ExAdv/macc_simple_test_01b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_01b.pdf): PDF inclusion: multiple pdfs with page group included in a single page > <./PRESENTATION_ExAdv/macc_simple_test_02b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_02b.pdf): PDF inclusion: multiple pdfs with page group included in a single page >] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [117] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_swap_map.v) (./PRESENTATION_ExAdv/macc_xilinx_swap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [118] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v Overfull \hbox (2.21822pt too wide) in paragraph at lines 19--21 [][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v consecutive: )) Overfull \vbox (1.21974pt too high) detected at line 610 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [119] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v consecutive: ) Overfull \hbox (2.21822pt too wide) in paragraph at lines 66--6 [][][][][][][][][][][][][][][][][] (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [120] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_xmap.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [121] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v) (./PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [122] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v consecutive: ) (./PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [123] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_test.v) Underfull \hbox (badness 10000) detected at line 4 []| (./PRESENTATION_ExAdv/macc_xilinx_test.v consecutive: ) Underfull \hbox (badness 10000) detected at line 5 []| Overfull \hbox (84.2987pt too wide) in paragraph at lines 10--11 [][][][][][][][] Overfull \hbox (26.69807pt too wide) in paragraph at lines 11--12 [][][][][][][] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [124 <./PRESENTATION_ExAdv/macc_xilinx_test1a.pdf> <./PRESENTATION_ExAdv/macc_x ilinx_test2a.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_xilinx_test2a.pdf): PD F inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb Overfull \hbox (99.65887pt too wide) in paragraph at lines 10--11 [][][][][][][][][][][][][] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [125 <./PRESENTATION_ExAdv/macc_xilinx_test1b.pdf> <./PRESENTATION_ExAdv/macc_x ilinx_test2b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_xilinx_test2b.pdf): PD F inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb Overfull \hbox (7.49786pt too wide) in paragraph at lines 10--11 [][][][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 11--12 [][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 12--13 [][][][][][][][][] Overfull \hbox (11.3379pt too wide) in paragraph at lines 13--14 [][][][][][][][] libxpdf: Syntax Error: Couldn't read xref table libxpdf: Syntax Warning: PDF file is damaged - attempting to reconstruct xref table... ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] 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Output written on tctt1000.600gf (128 characters, 19540 bytes). Transcript written on tctt1000.log. mktexpk: /build/yosys-0.23/debian/.debhelper/generated/_source/home/.texlive2022/texmf-var/fonts/pk/ljfour/jknappen/ec/tctt1000.600pk: successfully generated. {/usr/s hare/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/texm f/fonts/enc/dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.e nc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/d vips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i 4-t1-0.enc} Output written on manual.pdf (273 pages, 1771255 bytes). Transcript written on manual.log. + false + bibtex manual.aux This is BibTeX, Version 0.99d (TeX Live 2022/Debian) The top-level auxiliary file: manual.aux The style file: alphadin.bst Database file #1: literature.bib Warning--to sort, need author or key in Verilog2005 Warning--to sort, need author or key in VerilogSynth Warning--to sort, need author or key in VHDL Warning--to sort, need author or key in VHDLSynth Warning--to sort, need author or key in IP-XACT Warning--empty pages in Cummings00 Warning--empty pages in intersynthFdlBookChapter Warning--empty author in IP-XACT Warning--empty author in VerilogSynth Warning--empty author in Verilog2005 Warning--empty author in VHDLSynth Warning--empty author in VHDL (There were 12 warnings) + bibtex weblink.aux This is BibTeX, Version 0.99d (TeX Live 2022/Debian) The top-level auxiliary file: weblink.aux The style file: abbrv.bst Database file #1: weblinks.bib Warning--to sort, need author or key in C_to_Verilog Warning--to sort, need author or key in LegUp Warning--to sort, need author or key in flex Warning--to sort, need author or key in bison Warning--to sort, need author or key in LibertyFormat Warning--to sort, need author or key in OR1200 Warning--to sort, need author or key in openMSP430 Warning--to sort, need author or key in i2cmaster Warning--to sort, need author or key in k68 Warning--to sort, need author or key in Formality (There were 10 warnings) + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_TextRtlil.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg 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[19] (/usr/share/texmf/tex/latex/lm/ts1lmr.fd) [20] [21] LaTeX Warning: Reference `sec:blocking_nonblocking' on page 22 undefined on inp ut line 363. [22] LaTeX Warning: Reference `fig:StateOfTheArt_for' on page 23 undefined on input line 390. LaTeX Warning: Reference `fig:StateOfTheArt_gen' on page 23 undefined on input line 391. LaTeX Warning: Reference `chapter:sota' on page 23 undefined on input line 391. [23] [24] [25] [26]) [27] (./CHAPTER_Approach.tex Chapter 3. [28] (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) [29]) [30] (./CHAPTER_Overview.tex Chapter 4. [31] [32] [33] [34] (/usr/share/texlive/texmf-dist/tex/latex/inconsolata/ts1zi4.fd) Overfull \hbox (20.05457pt too wide) in paragraph at lines 292--294 []\T1/lmr/m/n/10 The RTLIL::SigSpec data type is used to rep-re-sent sig-nals. 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(../guidelines/GettingStarted [56] [57] [58] [59] (/usr/share/texlive/texmf-dist/tex/latex/base/t1cmtt.fd) (/usr/share/texlive/texmf-dist/tex/latex/base/ts1cmtt.fd) [60]) (../guidelines/CodingStyle) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstmisc.sty) (./CHAPTER_Prog/stubnets.cc [61] [62] LaTeX Font Warning: Font shape `TS1/zi4/m/it' undefined (Font) using `TS1/zi4/m/n' instead (Font) for symbol `textquotesingle' on input line 74. [63]) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang2.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstmisc.sty) (./CHAPTER_Prog/Makefile) (./CHAPTER_Prog/test.v)) [64] (./CHAPTER_Verilog.tex Chapter 7. LaTeX Font Warning: Font shape `T1/cmtt/b/n' undefined (Font) using `T1/cmtt/m/n' instead on input line 83. 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[81]) [82] (./CHAPTER_Auxlibs.tex Appendix A. ) [83] (./CHAPTER_Auxprogs.tex Appendix B. ) [84] Appendix C. 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LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathsy.enc} {/usr/share/texlive/texmf-dist/fonts/en c/dvips/inconsolata/i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.e nc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/d vips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i 4-t1-0.enc} Output written on manual.pdf (286 pages, 1874692 bytes). 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[][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][][][][] Overfull \hbox (100.67287pt too wide) in paragraph at lines 7504--7505 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][ ][][][][][][][][][][][][][][][][] Overfull \hbox (4.67159pt too wide) in paragraph at lines 7510--7511 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][] [225] [226] [227] [228] [229] [230] [231] [232] [233] [234] [235] [236] [237] [238] [239] [240] [241] [242] [243] [244] [245] [246] [247] Overfull \hbox (4.67159pt too wide) in paragraph at lines 8705--8706 [][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][][] [248] [249] [250] [251] [252] [253] [254] [255] [256] [257] [258] [259] [260]) [261] (./CHAPTER_TextRtlil.tex Appendix D. [262] [263] [264] [265] [266]) [267] (./CHAPTER_Appnotes.tex Appendix E. [268] [269 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [270 <./APPNOTE_010_Verilog_to_ BLIF.pdf>] [271 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [272 <./APPNOTE_011_Design _Investigation.pdf>] [273 <./APPNOTE_011_Design_Investigation.pdf>] [274 <./APP NOTE_011_Design_Investigation.pdf>] [275 <./APPNOTE_011_Design_Investigation.pd f>] [276 <./APPNOTE_011_Design_Investigation.pdf>] [277 <./APPNOTE_011_Design_I nvestigation.pdf>] [278 <./APPNOTE_011_Design_Investigation.pdf>] [279 <./APPNO TE_011_Design_Investigation.pdf>] [280 <./APPNOTE_011_Design_Investigation.pdf> ] [281 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [282 <./APPNOTE_012_Verilog_to_BTOR .pdf>] [283 <./APPNOTE_012_Verilog_to_BTOR.pdf>]) (./manual.bbl [284]) (./weblink.bbl [285]) [286] (./manual.aux (./CHAPTER_Intro.aux) (./CHAPTER_Basics.aux) (./CHAPTER_Approach.aux) (./CHAPTER_Overview.aux) (./CHAPTER_CellLib.aux) (./CHAPTER_Prog.aux) (./CHAPTER_Verilog.aux) (./CHAPTER_Optimize.aux) (./CHAPTER_Techmap.aux) (./CHAPTER_Auxlibs.aux) (./CHAPTER_Auxprogs.aux) (./CHAPTER_TextRtlil.aux) (./CHAPTER_Appnotes.aux)) LaTeX Font Warning: Some font shapes were not available, defaults substituted. LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathsy.enc} {/usr/share/texlive/texmf-dist/fonts/en c/dvips/inconsolata/i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathit.e nc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texmf/fonts/enc/d vips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i 4-t1-0.enc} Output written on manual.pdf (286 pages, 1874692 bytes). Transcript written on manual.log. + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_TextRtlil.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg weblink.blg + cmp autoloop.old autoloop.new + rm -f autoloop.old + rm -f autoloop.new + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' manual.pdf + mv -f manual.pdf.without_pdf_id manual.pdf make[2]: Leaving directory '/build/yosys-0.23' make[1]: Leaving directory '/build/yosys-0.23' debian/rules override_dh_auto_test make[1]: Entering directory '/build/yosys-0.23' dh_auto_test make -j16 test make[2]: Entering directory '/build/yosys-0.23' [Makefile.conf] CONFIG := gcc [Makefile.conf] ABCEXTERNAL=berkeley-abc [Makefile.conf] ABCPULL=0 [Makefile.conf] STRIP=: cd tests/simple && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/simple' + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c Test: unnamed_block_decl -> ok Test: local_loop_var -> ok Test: matching_end_labels -> ok Test: case_expr_query -> ok Test: memwr_port_connection -> ok Test: case_expr_extend -> ok Test: always01 -> ok Test: always02 -> ok Test: implicit_ports -> ok Test: lesser_size_cast -> ok Test: arrays02 -> ok Test: aes_kexp128 -> ok Test: always03 -> ok Test: defvalue -> ok Test: macro_arg_spaces -> ok Test: case_expr_const -> ok Test: arrays01 -> ok Test: attrib02_port_decl -> ok Test: attrib01_module -> ok Test: case_expr_non_const -> ok Test: arraycells -> ok Test: attrib08_mod_inst -> ok Test: const_branch_finish -> ok Test: attrib06_operator_suffix -> ok Test: attrib03_parameter -> ok Test: attrib09_case -> ok Test: carryadd -> ok Test: attrib04_net_var -> ok Test: constpower -> ok Test: const_fold_func -> ok Test: forgen01 -> ok Test: fiedler-cooley -> ok Test: forgen02 -> ok Test: func_recurse -> ok Test: const_func_shadow -> ok Test: genblk_collide -> ok Test: forloops -> ok Test: genblk_dive -> ok Test: genblk_order -> ok Test: dff_init -> ok Test: fsm -> ok Test: genblk_port_shadow -> ok Test: func_block -> ok Test: func_width_scope -> ok Test: hierarchy -> ok Test: ifdef_1 -> ok Test: ifdef_2 -> ok Test: graphtest -> ok Test: localparam_attr -> ok Test: macro_arg_surrounding_spaces -> ok Test: loop_var_shadow -> ok Test: loop_prefix_case -> ok Test: dff_different_styles -> ok Test: asgn_binop -> ok Test: hierdefparam -> ok Test: i2c_master_tests -> ok Test: macros -> ok Test: mem2reg_bounds_tern -> ok Test: module_scope_case -> ok Test: loops -> ok Test: module_scope -> ok Test: named_genblk -> ok Test: nested_genblk_resolve -> ok Test: param_attr -> ok Test: omsp_dbg_uart -> ok Test: muxtree -> ok Test: constmuldivmod -> ok Test: dynslice -> ok Test: retime -> ok Test: realexpr -> ok Test: multiplier -> ok Test: paramods -> ok Test: repwhile -> ok Test: mem_arst -> ok Test: signedexpr -> ok Test: process -> ok Test: specify -> ok Test: string_format -> ok Test: signed_full_slice -> ok Test: scopes -> ok Test: undef_eqx_nex -> ok Test: mem2reg -> ok Test: usb_phy_tests -> ok Test: verilog_primitives -> ok Test: subbytes -> ok Test: values -> ok Test: wandwor -> ok Test: generate -> ok Test: task_func -> ok Test: vloghammer -> ok Test: wreduce -> ok Test: sincos -> ok Test: operators -> ok Test: partsel -> ok Test: case_large -> ok Test: rotate -> ok Test: memory -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/simple' cd tests/simple_abc9 && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/simple_abc9' Test: case_expr_const -> ok Test: always03 -> ok Test: always01 -> ok Test: arrays01 -> ok Test: always02 -> ok Test: attrib04_net_var -> ok Test: attrib09_case -> ok Test: attrib02_port_decl -> ok Test: carryadd -> ok Test: attrib01_module -> ok Test: attrib08_mod_inst -> ok Test: aes_kexp128 -> ok Test: arraycells -> ok Test: const_branch_finish -> ok Test: attrib03_parameter -> ok Test: case_expr_non_const -> ok Test: attrib06_operator_suffix -> ok Test: const_fold_func -> ok Test: constpower -> ok Test: forgen01 -> ok Test: forgen02 -> ok Test: fiedler-cooley -> ok Test: dff_init -> ok Test: func_recurse -> ok Test: genblk_collide -> ok Test: func_block -> ok Test: forloops -> ok Test: fsm -> ok Test: genblk_dive -> ok Test: genblk_order -> ok Test: const_func_shadow -> ok Test: genblk_port_shadow -> ok Test: func_width_scope -> ok Test: dff_different_styles -> ok Test: graphtest -> ok Test: hierarchy -> ok Test: ifdef_2 -> ok Test: ifdef_1 -> ok Test: localparam_attr -> ok Test: loop_prefix_case -> ok Test: loop_var_shadow -> ok Test: macro_arg_surrounding_spaces -> ok Test: i2c_master_tests -> ok Test: macros -> ok Test: module_scope_case -> ok Test: hierdefparam -> ok Test: loops -> ok Test: mem2reg_bounds_tern -> ok Test: named_genblk -> ok Test: nested_genblk_resolve -> ok Test: mem_arst -> ok Test: module_scope -> ok Test: muxtree -> ok Test: omsp_dbg_uart -> ok Test: param_attr -> ok Test: mem2reg -> ok Test: multiplier -> ok Test: retime -> ok Test: realexpr -> ok Test: repwhile -> ok Test: process -> ok Test: paramods -> ok Test: scopes -> ok Test: string_format -> ok Test: signed_full_slice -> ok Test: constmuldivmod -> ok Test: signedexpr -> ok Test: undef_eqx_nex -> ok Test: subbytes -> ok Test: usb_phy_tests -> ok Test: verilog_primitives -> ok Test: abc9 -> ok Test: generate -> ok Test: values -> ok Test: case_expr_extend -> ok Test: arrays02 -> ok Test: task_func -> ok Test: vloghammer -> ok Test: case_expr_query -> ok Test: wandwor -> ok Test: rotate -> ok Test: lesser_size_cast -> ok Test: implicit_ports -> ok Test: local_loop_var -> ok Test: matching_end_labels -> ok Test: defvalue -> ok Test: memwr_port_connection -> ok Test: unnamed_block_decl -> ok Test: macro_arg_spaces -> ok Test: asgn_binop -> ok Test: wreduce -> ok Test: memory -> ok Test: sincos -> ok Test: partsel -> ok Test: operators -> ok Test: dynslice -> ok Test: case_large -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/simple_abc9' cd tests/hana && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/hana' Test: test_simulation_buffer -> ok Test: test_simulation_seq -> ok Test: test_simulation_nor -> ok Test: test_parse2synthtrans -> ok Test: test_simulation_nand -> ok Test: test_simulation_or -> ok Test: test_simulation_vlib -> ok Test: test_simulation_and -> ok Test: test_parser -> ok Test: test_simulation_inc -> ok Test: test_simulation_sop -> ok Test: test_simulation_xnor -> ok Test: test_simulation_decoder -> ok Test: test_simulation_xor -> ok Test: test_simulation_always -> ok Test: test_simulation_mux -> ok Test: test_simulation_techmap -> ok Test: test_simulation_shifter -> ok Test: test_simulation_techmap_tech -> ok Test: test_intermout -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/hana' cd tests/asicworld && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/asicworld' Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_d_latch_gates -> ok Test: code_hdl_models_GrayCounter -> ok Test: code_hdl_models_decoder_2to4_gates -> ok Test: code_hdl_models_clk_div -> ok Test: code_hdl_models_decoder_using_case -> ok Test: code_hdl_models_dff_async_reset -> ok Test: code_hdl_models_decoder_using_assign -> ok Test: code_hdl_models_full_adder_gates -> ok Test: code_hdl_models_dff_sync_reset -> ok Test: code_hdl_models_encoder_4to2_gates -> ok Test: code_hdl_models_arbiter -> ok Test: code_hdl_models_encoder_using_if -> ok Test: code_hdl_models_encoder_using_case -> ok Test: code_hdl_models_clk_div_45 -> ok Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_full_subtracter_gates -> ok Test: code_hdl_models_lfsr -> ok Test: code_hdl_models_mux_2to1_gates -> ok Test: code_hdl_models_gray_counter -> ok Test: code_hdl_models_mux_using_if -> ok Test: code_hdl_models_mux_using_case -> ok Test: code_hdl_models_one_hot_cnt -> ok Test: code_hdl_models_lfsr_updown -> ok Test: code_hdl_models_parity_using_bitwise -> ok Test: code_hdl_models_mux_using_assign -> ok Test: code_hdl_models_parity_using_assign -> ok Test: code_hdl_models_parity_using_function -> ok Test: code_hdl_models_parallel_crc -> ok Test: code_hdl_models_rom_using_case -> ok Test: code_hdl_models_tff_async_reset -> ok Test: code_hdl_models_pri_encoder_using_assign -> ok Test: code_hdl_models_tff_sync_reset -> ok Test: code_hdl_models_up_counter -> ok Test: code_hdl_models_serial_crc -> ok Test: code_tidbits_asyn_reset -> ok Test: code_tidbits_blocking -> ok Test: code_hdl_models_up_counter_load -> ok Test: code_tidbits_fsm_using_always -> ok Test: code_hdl_models_up_down_counter -> ok Test: code_tidbits_reg_combo_example -> ok Test: code_specman_switch_fabric -> ok Test: code_tidbits_nonblocking -> ok Test: code_tidbits_fsm_using_function -> ok Test: code_tidbits_reg_seq_example -> ok Test: code_tidbits_wire_example -> ok Test: code_tidbits_syn_reset -> ok Test: code_verilog_tutorial_bus_con -> ok Test: code_verilog_tutorial_always_example -> ok Test: code_tidbits_fsm_using_single_always -> ok Test: code_verilog_tutorial_comment -> ok Test: code_verilog_tutorial_addbit -> ok Test: code_verilog_tutorial_escape_id -> ok Test: code_verilog_tutorial_counter -> ok Test: code_verilog_tutorial_multiply -> ok Test: code_verilog_tutorial_d_ff -> ok Test: code_verilog_tutorial_if_else -> ok Test: code_verilog_tutorial_first_counter -> ok Test: code_verilog_tutorial_decoder_always -> ok Test: code_verilog_tutorial_good_code -> ok Test: code_verilog_tutorial_decoder -> ok Test: code_verilog_tutorial_explicit -> ok Test: code_verilog_tutorial_flip_flop -> ok Test: code_verilog_tutorial_mux_21 -> ok Test: code_verilog_tutorial_n_out_primitive -> ok Test: code_verilog_tutorial_parallel_if -> ok Test: code_verilog_tutorial_simple_function -> ok Test: code_verilog_tutorial_v2k_reg -> ok Test: code_verilog_tutorial_simple_if -> ok Test: code_verilog_tutorial_parity -> ok Test: code_verilog_tutorial_task_global -> ok Test: code_verilog_tutorial_fsm_full -> ok Test: code_verilog_tutorial_tri_buf -> ok Test: code_verilog_tutorial_which_clock -> ok Test: code_hdl_models_uart -> ok Test: code_hdl_models_cam -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/asicworld' #+cd tests/realmath && bash run-test.sh "" cd tests/share && bash run-test.sh "" generating tests.. running tests.. [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] cd tests/opt_share && bash run-test.sh "" generating tests.. running tests.. make[3]: Entering directory '/build/yosys-0.23/tests/opt_share' [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[3]: Leaving directory '/build/yosys-0.23/tests/opt_share' cd tests/fsm && bash run-test.sh "" generating tests.. PRNG seed: 122977797236495718 running tests.. make[3]: Entering directory '/build/yosys-0.23/tests/fsm' [0][1][2][3][4][5][6][7][8][9][10][11][12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! [13][14][15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[16]K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[20]K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[22]K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[25]K[26]K[27]K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[29]K[30]K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[32]K[33]K[34]K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[36]K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[39]K[40]K[41]K[42]K[43]K[44]K[45]K[46]K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! KKKKKKKKKKKKKKTT make[3]: Leaving directory '/build/yosys-0.23/tests/fsm' cd tests/techmap && bash run-test.sh make[3]: Entering directory '/build/yosys-0.23/tests/techmap' Warning: wire '\Q' is assigned in a block at < ok Test: firrtl_938 -> ok Test: no_implicit_en -> ok Test: simple_sram_byte_en -> ok Test: shared_ports -> ok Test: read_two_mux -> ok Test: wide_read_mixed -> ok Test: read_arst -> ok Test: amber23_sram_byte_en -> ok Test: wide_read_async -> ok Test: issue00710 -> ok Test: trans_sdp -> ok Test: wide_all -> ok Test: trans_addr_enable -> ok Test: wide_thru_priority -> ok Test: trans_sp -> ok Test: wide_read_sync -> ok Test: wide_write -> ok Test: wide_read_trans -> ok Test: issue00335 -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/memories' Testing expectations for amber23_sram_byte_en.v .. ok. Testing expectations for implicit_en.v .. ok. Testing expectations for issue00335.v .. ok. Testing expectations for issue00710.v .. ok. Testing expectations for no_implicit_en.v .. ok. Testing expectations for read_arst.v .. ok. Testing expectations for read_two_mux.v .. ok. Testing expectations for shared_ports.v .. ok. Testing expectations for simple_sram_byte_en.v .. ok. Testing expectations for trans_addr_enable.v .. ok. Testing expectations for trans_sdp.v .. ok. Testing expectations for trans_sp.v .. ok. Testing expectations for wide_all.v .. ok. Testing expectations for wide_read_async.v .. ok. Testing expectations for wide_read_mixed.v .. ok. Testing expectations for wide_read_sync.v .. ok. Testing expectations for wide_read_trans.v .. ok. Testing expectations for wide_thru_priority.v .. ok. Testing expectations for wide_write.v .. ok. cd tests/memlib && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/memlib' Test: t_sync_small_block -> ok Test: t_sync_small_block_attr -> ok Test: t_sync_trans_old_old -> ok Test: t_sync_trans_old_new -> ok Test: t_async_small -> ok Test: t_sync_2clk -> ok Test: t_sync_shared -> ok Test: t_sync_small -> ok Test: t_tdp -> ok Test: t_sync_big -> ok Test: t_sync_big_sdp -> ok Test: t_async_small_block -> ok Test: t_sync_2clk_shared -> ok Test: t_sync_trans_new_old -> ok Test: t_sp_new_none -> ok Test: t_sync_trans_old_none -> ok Test: t_sync_trans_new_none -> ok Test: t_sp_nc_none -> ok Test: t_sync_trans_new_new -> ok Test: t_sp_new_nc -> ok Test: t_sp_nc_nc -> ok Test: t_sp_old_none -> ok Test: t_sp_nc_new -> ok Test: t_sp_old_nc -> ok Test: t_sp_new_new -> ok Test: t_sp_old_old -> ok Test: t_sp_new_old -> ok Test: t_sp_nc_old -> ok Test: t_sp_new_new_only -> ok Test: t_sp_new_new_only_be -> ok Test: t_sp_nc_new_only -> ok Test: t_sp_old_new -> ok Test: t_sp_nc_new_only_be -> ok Test: t_sp_old_new_only -> ok Test: t_sp_nc_new_be -> ok Test: t_sp_new_new_be -> ok Test: t_sp_old_new_only_be -> ok Test: t_sp_new_old_be -> ok Test: t_sp_old_old_be -> ok Test: t_sp_old_new_be -> ok Test: t_sp_nc_old_be -> ok Test: t_sp_nc_auto -> ok Test: t_sp_new_nc_be -> ok Test: t_sp_nc_nc_be -> ok Test: t_sp_new_auto -> ok Test: t_sp_old_auto -> ok Test: t_sp_old_nc_be -> ok Test: t_sp_new_auto_be -> ok Test: t_sp_old_auto_be -> ok Test: t_sp_nc_auto_be -> ok Test: t_sp_init_0_0_re -> ok Test: t_sp_init_x_x_ce -> ok Test: t_sp_init_x_x_re -> ok Test: t_sp_init_x_x -> ok Test: t_sp_init_0_x -> ok Test: t_sp_init_0_0 -> ok Test: t_sp_init_0_any -> ok Test: t_sp_init_0_x_re -> ok Test: t_sp_init_v_x -> ok Test: t_sp_init_v_x_re -> ok Test: t_sp_init_0_any_re -> ok Test: t_sp_init_v_0 -> ok Test: t_sp_init_v_0_re -> ok Test: t_sp_init_v_any -> ok Test: t_sp_init_v_any_re -> ok Test: t_sp_arst_x_x -> ok Test: t_sp_arst_x_x_re -> ok Test: t_sp_arst_0_0 -> ok Test: t_sp_arst_0_0_re -> ok Test: t_sp_arst_0_x -> ok Test: t_sp_arst_0_x_re -> ok Test: t_sp_arst_0_any_re -> ok Test: t_sp_arst_0_any -> ok Test: t_sp_arst_0_init -> ok Test: t_sp_arst_0_init_re -> ok Test: t_sp_arst_v_0_re -> ok Test: t_sp_arst_v_x -> ok Test: t_sp_arst_v_x_re -> ok Test: t_sp_arst_v_0 -> ok Test: t_sp_arst_v_any -> ok Test: t_sp_arst_v_any_re -> ok Test: t_sp_arst_v_init -> ok Test: t_sp_arst_v_init_re -> ok Test: t_sp_arst_e_x -> ok Test: t_sp_arst_e_x_re -> ok Test: t_sp_arst_e_0 -> ok Test: t_sp_arst_e_any -> ok Test: t_sp_arst_e_0_re -> ok Test: t_sp_arst_n_x -> ok Test: t_sp_arst_e_init -> ok Test: t_sp_arst_e_any_re -> ok Test: t_sp_arst_e_init_re -> ok Test: t_sp_arst_n_0 -> ok Test: t_sp_arst_n_x_re -> ok Test: t_sp_arst_n_any -> ok Test: t_sp_arst_n_0_re -> ok Test: t_sp_arst_n_init_re -> ok Test: t_sp_arst_n_any_re -> ok Test: t_sp_arst_n_init -> ok Test: t_sp_srst_x_x -> ok Test: t_sp_srst_x_x_re -> ok Test: t_sp_srst_0_x_re -> ok Test: t_sp_srst_0_0 -> ok Test: t_sp_srst_0_any -> ok Test: t_sp_srst_0_x -> ok Test: t_sp_srst_0_0_re -> ok Test: t_sp_srst_0_init -> ok Test: t_sp_srst_0_init_re -> ok Test: t_sp_srst_0_any_re -> ok Test: t_sp_srst_v_x -> ok Test: t_sp_srst_v_any -> ok Test: t_sp_srst_v_0 -> ok Test: t_sp_srst_v_x_re -> ok Test: t_sp_srst_v_0_re -> ok Test: t_sp_srst_v_any_re -> ok Test: t_sp_srst_v_any_ce_gated -> ok Test: t_sp_srst_v_any_ce -> ok Test: t_sp_srst_v_init -> ok Test: t_sp_srst_v_any_re_gated -> ok Test: t_sp_srst_v_init_re -> ok Test: t_sp_srst_e_x_re -> ok Test: t_sp_srst_e_x -> ok Test: t_sp_srst_e_any -> ok Test: t_sp_srst_e_0 -> ok Test: t_sp_srst_e_init -> ok Test: t_sp_srst_e_any_re -> ok Test: t_sp_srst_e_0_re -> ok Test: t_sp_srst_e_init_re -> ok Test: t_sp_srst_n_x_re -> ok Test: t_sp_srst_n_x -> ok Test: t_sp_srst_n_0_re -> ok Test: t_sp_srst_n_any_re -> ok Test: t_sp_srst_n_any -> ok Test: t_sp_srst_n_0 -> ok Test: t_sp_srst_n_init -> ok Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_gv_0 -> ok Test: t_sp_srst_gv_x_re -> ok Test: t_sp_srst_gv_any -> ok Test: t_sp_srst_gv_x -> ok Test: t_sp_srst_gv_0_re -> ok Test: t_sp_srst_gv_any_re -> ok Test: t_sp_srst_gv_any_re_gated -> ok Test: t_sp_srst_gv_any_ce -> ok Test: t_sp_srst_gv_any_ce_gated -> ok Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_sp_srst_gv_init_re -> ok Test: t_sp_srst_gv_init -> ok Test: t_async_big -> ok Test: t_wide_sdp_a7r1w1b1x1 -> ok Test: t_wide_sdp_a6r2w0b0x0 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok Test: t_wide_sdp_a8r1w1b1x1 -> ok Test: t_wide_sdp_a6r1w0b0x0 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b1x0 -> ok Test: t_sync_big_lut -> ok Test: t_wide_sdp_a6r0w1b0x0 -> ok Test: t_wide_sdp_a6r4w0b0x0 -> ok Test: t_wide_sdp_a6r0w2b0x0 -> ok Test: t_wide_sdp_a6r0w2b2x0 -> ok Test: t_wide_sdp_a6r0w3b2x0 -> ok Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_wide_sdp_a7r0w0b0x0 -> ok Test: t_wide_sdp_a7r2w0b0x0 -> ok Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_wide_sdp_a7r0w1b0x0 -> ok Test: t_wide_sdp_a7r0w2b2x0 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_wide_sp_mix_a8r1w1b1 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok Test: t_wide_sp_mix_a6r1w0b0 -> ok Test: t_wide_sp_mix_a7r1w1b1 -> ok Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok Test: t_wide_sp_mix_a6r4w0b0 -> ok Test: t_wide_sp_mix_a6r0w2b2 -> ok Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok Test: t_wide_sp_mix_a6r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w0b0 -> ok Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok Test: t_wide_sp_mix_a7r4w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b1 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w2b2 -> ok Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w3b2 -> ok Test: t_wide_sp_mix_a6r0w5b2 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok Test: t_wide_sp_tied_a6r0w0b0 -> ok Test: t_wide_sp_mix_a7r0w4b2 -> ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b0 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_mix_a7r0w5b2 -> ok Test: t_wide_sp_tied_a6r0w2b0 -> ok Test: t_wide_sp_tied_a6r0w2b2 -> ok Test: t_wide_sp_tied_a6r4w0b0 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok Test: t_wide_sp_tied_a6r5w0b0 -> ok Test: t_wide_sp_tied_a7r3w0b0 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok Test: t_wide_sp_tied_a7r4w0b0 -> ok Test: t_wide_sp_tied_a7r0w1b0 -> ok Test: t_wide_sp_tied_a7r0w2b2 -> ok Test: t_wide_sp_tied_a7r0w2b0 -> ok Test: t_wide_sp_tied_a7r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_sp_tied_a7r5w0b0 -> ok Test: t_wide_sp_tied_a7r0w3b2 -> ok Test: t_wide_read_a6r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_write_a6r1w1b1 -> ok Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_read_a7r1w1b1 -> ok Test: t_wide_write_a7r1w1b1 -> ok Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_read_a6r0w0b0 -> ok Test: t_wide_sp_tied_a7r0w5b2 -> ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_write_a6r1w0b0 -> ok Test: t_wide_write_a6r2w0b0 -> ok Test: t_wide_write_a6r0w0b0 -> ok Test: t_wide_read_a6r3w0b0 -> ok Test: t_wide_read_a6r2w0b0 -> ok Test: t_wide_write_a6r3w0b0 -> ok Test: t_wide_read_a6r4w0b0 -> ok Test: t_wide_read_a6r0w1b0 -> ok Test: t_wide_write_a6r4w0b0 -> ok Test: t_wide_write_a6r0w1b0 -> ok Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_read_a6r5w0b0 -> ok Test: t_wide_write_a6r0w1b1 -> ok Test: t_wide_read_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b2 -> ok Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_read_a6r0w2b2 -> ok Test: t_wide_write_a6r0w3b2 -> ok Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_read_a7r1w0b0 -> ok Test: t_wide_read_a7r0w0b0 -> ok Test: t_wide_read_a6r0w4b2 -> ok Test: t_wide_write_a7r0w0b0 -> ok Test: t_wide_read_a7r2w0b0 -> ok Test: t_wide_write_a7r1w0b0 -> ok Test: t_wide_read_a6r0w5b2 -> ok Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_read_a7r3w0b0 -> ok Test: t_wide_read_a7r4w0b0 -> ok Test: t_wide_write_a6r0w5b2 -> ok Test: t_wide_write_a7r3w0b0 -> ok Test: t_wide_read_a7r0w1b0 -> ok Test: t_wide_read_a7r5w0b0 -> ok Test: t_wide_write_a7r4w0b0 -> ok Test: t_wide_read_a7r0w1b1 -> ok Test: t_wide_write_a7r0w1b0 -> ok Test: t_async_big_block -> ok Test: t_wide_read_a7r0w2b0 -> ok Test: t_wide_write_a7r0w2b0 -> ok Test: t_wide_write_a7r0w1b1 -> ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_write_a7r0w2b2 -> ok Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w3b2 -> ok Test: t_wide_write_a7r0w4b2 -> ok Test: t_wide_read_a7r0w4b2 -> ok Test: t_wide_write_a7r0w5b2 -> ok Test: t_wide_read_a7r0w5b2 -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/memlib' cd tests/bram && bash run-test.sh "" generating tests.. PRNG seed: 997518 running tests.. make[3]: Entering directory '/build/yosys-0.23/tests/bram' ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 00_01. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 00_03. Passed memory_bram test 03_01. Passed memory_bram test 00_04. Passed memory_bram test 02_00. Passed memory_bram test 02_03. Passed memory_bram test 02_01. Passed memory_bram test 03_00. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 02_04. Passed memory_bram test 03_02. Passed memory_bram test 01_03. Passed memory_bram test 01_04. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 01_02. Passed memory_bram test 04_01. Passed memory_bram test 04_03. Passed memory_bram test 00_02. Passed memory_bram test 01_00. Passed memory_bram test 04_00. Passed memory_bram test 04_02. Passed memory_bram test 03_04. make[3]: Leaving directory '/build/yosys-0.23/tests/bram' cd tests/various && bash run-test.sh make[3]: Entering directory '/build/yosys-0.23/tests/various' Passed aiger_dff.ys Passed attrib05_port_conn.ys Passed attrib07_func_call.ys Passed autoname.ys Passed blackbox_wb.ys Passed bug1496.ys Passed bug1614.ys Passed bug1710.ys Warning: Yosys has only limited support for tri-state logic at the moment. (< ok Test: svinterface_at_top -> ok Test: load_and_derive ->ok cd tests/svtypes && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/svtypes' < ok Test ../../techlibs/anlogic/cells_sim.v -> ok Test ../../techlibs/coolrunner2/cells_sim.v -> ok Test ../../techlibs/ecp5/cells_sim.v -> ok Test ../../techlibs/efinix/cells_sim.v -> ok Test ../../techlibs/gatemate/cells_sim.v -> ok Test ../../techlibs/gowin/cells_sim.v -> ok Test ../../techlibs/greenpak4/cells_sim.v -> ok Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2231: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2233: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2233: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2235: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2235: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2237: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2237: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2239: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2239: warning: choosing typ expression. ok Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2295: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2297: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2299: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2301: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2303: warning: choosing typ expression. ok Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2359: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2361: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2363: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2365: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: choosing typ expression. ../../techlibs/ice40/cells_sim.v:2367: warning: choosing typ expression. ok Test ../../techlibs/intel/max10/cells_sim.v -> ok Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok Test ../../techlibs/machxo2/cells_sim.v -> ok Test ../../techlibs/nexus/cells_sim.v -> ok Test ../../techlibs/quicklogic/cells_sim.v -> ok Test ../../techlibs/sf2/cells_sim.v -> ok Test ../../techlibs/xilinx/cells_sim.v -> ok Test ../../techlibs/common/simcells.v -> ok Test ../../techlibs/common/simlib.v ->../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ok cd tests/arch/ice40 && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/ice40' Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. Passed ice40_wrapcarry.ys Passed ice40_dsp.ys Passed bug2061.ys Passed bug1626.ys Passed add_sub.ys Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. Passed bug1598.ys Passed logic.ys Passed bug1597.ys Passed counter.ys Passed ice40_opt.ys Passed fsm.ys Passed rom.ys Passed mul.ys Passed shifter.ys Passed dffs.ys Passed tribuf.ys Passed latches.ys Passed adffs.ys Passed mux.ys Passed macc.ys Passed dpram.ys Passed bug1644.ys Passed memories.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/ice40' cd tests/arch/xilinx && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/xilinx' Warning: Wire top.\t is used but has no driver. Warning: Wire top.\in is used but has no driver. Warning: Shift register inference not yet supported for family xc3s. Passed bug1605.ys Passed bug1480.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. Passed dsp_fastfir.ys Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. Passed bug1460.ys Passed bug1462.ys Passed bug1598.ys Passed counter.ys Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 Passed add_sub.ys Passed dsp_simd.ys Warning: Shift register inference not yet supported for family xc3se. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. Warning: Shift register inference not yet supported for family xc3se. Passed logic.ys Passed fsm.ys Passed dsp_abc9.ys Passed opt_lut_ins.ys /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Passed mul.ys Passed macc.ys Passed latches.ys /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. /build/yosys-0.23/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. Passed xilinx_dsp.ys Passed shifter.ys Passed xilinx_srl.ys Passed nosrl.ys Passed adffs.ys Passed xilinx_dffopt.ys Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Passed tribuf.ys Passed mul_unsigned.ys Passed dffs.ys Passed pmgen_xilinx_srl.ys Passed mux_lut4.ys Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. Passed tribuf.sh Passed mux.ys Passed macc.sh Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. Passed attributes_test.ys Passed abc9_dff.ys Warning: Shift register inference not yet supported for family xc3s. Passed lutram.ys Passed blockram.ys Passed dsp_cascade.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/xilinx' cd tests/arch/ecp5 && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/ecp5' Passed bug1630.ys Passed counter.ys Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. Passed latches_abc9.ys Passed macc.ys Passed bug2731.ys Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15. Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16. Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21. Passed bug2409.ys Passed opt_lut_ins.ys Passed logic.ys Passed add_sub.ys Passed bug1459.ys Passed bug1598.ys Passed fsm.ys Passed mul.ys Passed dffs.ys Passed shifter.ys Passed tribuf.ys Passed rom.ys Passed latches.ys Passed dpram.ys Passed adffs.ys Passed mux.ys Passed lutram.ys Passed memories.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/ecp5' cd tests/arch/machxo2 && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/machxo2' Passed add_sub.ys Passed shifter.ys Passed dffs.ys Passed tribuf.ys Passed logic.ys Passed fsm.ys Passed mux.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/machxo2' cd tests/arch/efinix && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/efinix' Passed counter.ys Passed lutram.ys Passed dffs.ys Passed shifter.ys Passed add_sub.ys Passed tribuf.ys Passed logic.ys Passed adffs.ys Passed fsm.ys Passed latches.ys Passed mux.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/efinix' cd tests/arch/anlogic && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/anlogic' Passed tribuf.ys Passed counter.ys Passed shifter.ys Passed logic.ys Passed add_sub.ys Passed dffs.ys Passed lutram.ys Passed fsm.ys Passed latches.ys Passed mux.ys Passed blockram.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/anlogic' cd tests/arch/gowin && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/gowin' ERROR: FF myDFFP.$auto$ff.cc:266:slice$662 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination Expected error pattern 'unsupported initial value and async reset value combination' found !!! Passed init-error.ys Passed counter.ys Passed add_sub.ys Passed shifter.ys Passed logic.ys Passed tribuf.ys Passed dffs.ys Passed fsm.ys Passed init.ys Passed mux.ys Passed adffs.ys Passed lutram.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/gowin' cd tests/arch/intel_alm && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/intel_alm' Passed blockram.ys Passed quartus_ice.ys Passed logic.ys Passed shifter.ys Passed add_sub.ys Passed counter.ys Passed tribuf.ys Passed dffs.ys Passed adffs.ys Passed mux.ys Passed mul.ys Passed fsm.ys Passed lutram.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/intel_alm' cd tests/arch/nexus && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/nexus' Passed tribuf.ys Passed counter.ys Passed shifter.ys Passed fsm.ys Passed logic.ys Passed dffs.ys Passed blockram.ys Passed add_sub.ys Passed lutram.ys Passed mul.ys Passed adffs.ys Passed mux.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/nexus' cd tests/arch/quicklogic && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/quicklogic' Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: Complex async reset for dff `\Q'. Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock. Warning: Complex async reset for dff `\Q'. Passed logic.ys Passed add_sub.ys Passed tribuf.ys Passed counter.ys Passed dffs.ys Passed fsm.ys Passed latches.ys Passed mux.ys Passed adffs.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/quicklogic' cd tests/arch/gatemate && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/arch/gatemate' Passed memory.ys Passed counter.ys Passed shifter.ys Passed fsm.ys Passed logic.ys Passed tribuf.ys Passed add_sub.ys Passed luttrees.ys Passed dffs.ys Passed mul.ys Passed latches.ys Passed mux.ys Passed adffs.ys make[3]: Leaving directory '/build/yosys-0.23/tests/arch/gatemate' cd tests/rpc && bash run-test.sh Running exec.ys.. cd tests/memfile && bash run-test.sh Running from the parent directory with content1.dat Running from the parent directory with temp/content2.dat Running from the parent directory with memfile/temp/content2.dat Running from the same directory with content1.dat Running from the same directory with temp/content2.dat Running from a child directory with content1.dat Running from a child directory with temp/content2.dat Running from a child directory with content2.dat Checking a failure when zero length filename is provided memory.v:0: ERROR: Can not open file `` for \$readmemb. Execution failed, which is OK. Checking a failure when not existing filename is provided memory.v:0: ERROR: Can not open file `content3.dat` for \$readmemb. Execution failed, which is OK. cd tests/verilog && bash run-test.sh make[3]: Entering directory '/build/yosys-0.23/tests/verilog' <