{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/r-b-build.W3uJCBtC/b1/rdma-core_52.0-2_amd64.changes", "source2": "/srv/reproducible-results/rbuild-debian/r-b-build.W3uJCBtC/b2/rdma-core_52.0-2_amd64.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -3,27 +3,27 @@\n b0477dc6740846fe405fbf6716b5b747 85124 net optional ibacm_52.0-2_amd64.deb\n 77c85c43b47f3863532a41682d345c14 2284200 debug optional ibverbs-providers-dbgsym_52.0-2_amd64.deb\n 2beb8dcbf266969cf072d0a116d1b6b6 342776 net optional ibverbs-providers_52.0-2_amd64.deb\n b9e0aab3008d795e0adf89404266b5d0 201200 debug optional ibverbs-utils-dbgsym_52.0-2_amd64.deb\n d0796148ebf00dee6281334d45077979 56612 net optional ibverbs-utils_52.0-2_amd64.deb\n 82ff8e0f6cfca1e103354dc784203e74 843792 debug optional infiniband-diags-dbgsym_52.0-2_amd64.deb\n f8f2c905907eb4bcfd063779bb684237 229536 net optional infiniband-diags_52.0-2_amd64.deb\n- 9a529290e0b557700dacad449ddd16d4 53340 libdevel optional libibmad-dev_52.0-2_amd64.deb\n+ 1b8139ec1b62bd6b49271842c20700bf 53496 libdevel optional libibmad-dev_52.0-2_amd64.deb\n b3daa3f2dab4668ed46721f794cb1a1d 106624 debug optional libibmad5-dbgsym_52.0-2_amd64.deb\n cce7cc35f14294f7655051a73a612d86 43132 libs optional libibmad5_52.0-2_amd64.deb\n- 33ca6550c303caeefc44d925f8501948 45448 libdevel optional libibnetdisc-dev_52.0-2_amd64.deb\n+ 1fff2db124b16ba41224bd4c3a9148f1 45492 libdevel optional libibnetdisc-dev_52.0-2_amd64.deb\n 28645e7b817cd16148097822c381a3a8 85904 debug optional libibnetdisc5t64-dbgsym_52.0-2_amd64.deb\n 8c83816b791035bf93c22f0cb1583e5b 34048 libs optional libibnetdisc5t64_52.0-2_amd64.deb\n e36db925aebd9aafdaee0a62cb602416 56016 libdevel optional libibumad-dev_52.0-2_amd64.deb\n b5e15d396739e58768f3d863f6d4de50 38660 debug optional libibumad3-dbgsym_52.0-2_amd64.deb\n e4f859f45607e63493626bae21e154c2 27884 libs optional libibumad3_52.0-2_amd64.deb\n- 4a8f53046087df5becf1761f843b9a98 636224 libdevel optional libibverbs-dev_52.0-2_amd64.deb\n+ 264d5e37f8d1bf53c3811b4d158261ee 636096 libdevel optional libibverbs-dev_52.0-2_amd64.deb\n b7255df868742727dee8b4aa996bf9e2 243340 debug optional libibverbs1-dbgsym_52.0-2_amd64.deb\n 9810ef8ac0da67c2fb1e8306d75af99f 61884 libs optional libibverbs1_52.0-2_amd64.deb\n- e2e0d5ac61efb9031ca2b8bcfac09d01 125572 libdevel optional librdmacm-dev_52.0-2_amd64.deb\n+ 492b8b384f64a5c912b15a0465a81aae 125540 libdevel optional librdmacm-dev_52.0-2_amd64.deb\n 0e7736c8dcc582dbecd550d492c737b3 231452 debug optional librdmacm1t64-dbgsym_52.0-2_amd64.deb\n d8c9d96547959596dc05b7667daf7f99 70092 libs optional librdmacm1t64_52.0-2_amd64.deb\n 7531a1b4ed64c9bfe562626e32fd0735 6890876 debug optional python3-pyverbs-dbgsym_52.0-2_amd64.deb\n 41e42d092d713752717abf6f953d8342 1573920 python optional python3-pyverbs_52.0-2_amd64.deb\n 6f43723ab2547a9523f6e12bc877ebaf 76056 debug optional rdma-core-dbgsym_52.0-2_amd64.deb\n 50fa8bdc80638119da79ea3bc2df57e9 59924 net optional rdma-core_52.0-2_amd64.deb\n ff8e2369da38f7f007be4bbae20e5a04 289728 debug optional rdmacm-utils-dbgsym_52.0-2_amd64.deb\n"}, {"source1": "libibmad-dev_52.0-2_amd64.deb", "source2": "libibmad-dev_52.0-2_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2024-06-27 11:49:34.000000 debian-binary\n -rw-r--r-- 0 0 0 920 2024-06-27 11:49:34.000000 control.tar.xz\n--rw-r--r-- 0 0 0 52228 2024-06-27 11:49:34.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 52384 2024-06-27 11:49:34.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/x86_64-linux-gnu/libibmad.a", "source2": "./usr/lib/x86_64-linux-gnu/libibmad.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,34 +1,73 @@\n \n Archive index:\n+mad_get_field in fields.c.o\n+mad_set_field in fields.c.o\n+mad_get_field64 in fields.c.o\n+mad_set_field64 in fields.c.o\n+mad_set_array in fields.c.o\n+mad_get_array in fields.c.o\n+mad_decode_field in fields.c.o\n+mad_encode_field in fields.c.o\n+mad_print_field in fields.c.o\n+mad_dump_field in fields.c.o\n+mad_dump_val in fields.c.o\n+mad_field_name in fields.c.o\n+smp_mkey_set in smp.c.o\n+smp_mkey_get in smp.c.o\n+smp_set_status_via in smp.c.o\n+smp_set_via in smp.c.o\n+smp_set in smp.c.o\n+smp_query_status_via in smp.c.o\n+smp_query_via in smp.c.o\n+smp_query in smp.c.o\n+bm_call_via in bm.c.o\n+ibdebug in rpc.c.o\n+madrpc_show_errors in rpc.c.o\n+madrpc_save_mad in rpc.c.o\n+madrpc_set_retries in rpc.c.o\n+rdmacore52_0_madrpc_retries in rpc.c.o\n+madrpc_set_timeout in rpc.c.o\n+rdmacore52_0_madrpc_timeout in rpc.c.o\n+mad_rpc_set_retries in rpc.c.o\n+mad_rpc_set_timeout in rpc.c.o\n+madrpc_portid in rpc.c.o\n+rdmacore52_0_ibmp in rpc.c.o\n+mad_rpc_portid in rpc.c.o\n+mad_rpc_class_agent in rpc.c.o\n+mad_rpc in rpc.c.o\n+mad_rpc_rmpp in rpc.c.o\n+madrpc in rpc.c.o\n+madrpc_rmpp in rpc.c.o\n+madrpc_init in rpc.c.o\n+mad_rpc_open_port in rpc.c.o\n+mad_rpc_close_port in rpc.c.o\n+portid2portnum in portid.c.o\n+portid2str in portid.c.o\n+str2drpath in portid.c.o\n+drpath2str in portid.c.o\n+pma_query_via in gs.c.o\n+performance_reset_via in gs.c.o\n+cc_query_status_via in cc.c.o\n+cc_config_status_via in cc.c.o\n mad_trid in mad.c.o\n mad_get_timeout in mad.c.o\n mad_get_retries in mad.c.o\n mad_encode in mad.c.o\n mad_build_pkt in mad.c.o\n+ib_resolve_smlid_via in resolve.c.o\n+ib_resolve_smlid in resolve.c.o\n+ib_resolve_gid_via in resolve.c.o\n+ib_resolve_guid_via in resolve.c.o\n+ib_resolve_self_via in resolve.c.o\n+ib_resolve_portid_str_via in resolve.c.o\n+ib_resolve_portid_str in resolve.c.o\n+ib_resolve_self in resolve.c.o\n ib_vendor_call in vendor.c.o\n ib_vendor_call_via in vendor.c.o\n-sa_rpc_call in sa.c.o\n-sa_call in sa.c.o\n-ib_path_query_via in sa.c.o\n-ib_path_query in sa.c.o\n-ib_node_query_via in sa.c.o\n-portid2portnum in portid.c.o\n-portid2str in portid.c.o\n-str2drpath in portid.c.o\n-drpath2str in portid.c.o\n-mad_send_via in serv.c.o\n-mad_send in serv.c.o\n-mad_respond_via in serv.c.o\n-mad_respond in serv.c.o\n-mad_receive in serv.c.o\n-mad_receive_via in serv.c.o\n-mad_alloc in serv.c.o\n-mad_free in serv.c.o\n-bm_call_via in bm.c.o\n mad_dump_int in dump.c.o\n mad_dump_uint in dump.c.o\n mad_dump_hex in dump.c.o\n mad_dump_rhex in dump.c.o\n mad_dump_linkwidth in dump.c.o\n mad_dump_linkwidthsup in dump.c.o\n mad_dump_linkwidthen in dump.c.o\n@@ -97,145 +136,211 @@\n mad_dump_cc_cacongestionentry in dump.c.o\n mad_dump_cc_congestioncontroltable in dump.c.o\n mad_dump_cc_congestioncontroltableentry in dump.c.o\n mad_dump_cc_timestamp in dump.c.o\n mad_dump_classportinfo in dump.c.o\n mad_dump_portinfo_ext in dump.c.o\n xdump in dump.c.o\n-cc_query_status_via in cc.c.o\n-cc_config_status_via in cc.c.o\n-ib_resolve_smlid_via in resolve.c.o\n-ib_resolve_smlid in resolve.c.o\n-ib_resolve_gid_via in resolve.c.o\n-ib_resolve_guid_via in resolve.c.o\n-ib_resolve_self_via in resolve.c.o\n-ib_resolve_portid_str_via in resolve.c.o\n-ib_resolve_portid_str in resolve.c.o\n-ib_resolve_self in resolve.c.o\n-smp_mkey_set in smp.c.o\n-smp_mkey_get in smp.c.o\n-smp_set_status_via in smp.c.o\n-smp_set_via in smp.c.o\n-smp_set in smp.c.o\n-smp_query_status_via in smp.c.o\n-smp_query_via in smp.c.o\n-smp_query in smp.c.o\n+mad_send_via in serv.c.o\n+mad_send in serv.c.o\n+mad_respond_via in serv.c.o\n+mad_respond in serv.c.o\n+mad_receive in serv.c.o\n+mad_receive_via in serv.c.o\n+mad_alloc in serv.c.o\n+mad_free in serv.c.o\n mad_class_agent in register.c.o\n rdmacore52_0_mad_register_port_client in register.c.o\n mad_register_client in register.c.o\n mad_register_client_via in register.c.o\n mad_register_server in register.c.o\n mad_register_server_via in register.c.o\n-ibdebug in rpc.c.o\n-madrpc_show_errors in rpc.c.o\n-madrpc_save_mad in rpc.c.o\n-madrpc_set_retries in rpc.c.o\n-rdmacore52_0_madrpc_retries in rpc.c.o\n-madrpc_set_timeout in rpc.c.o\n-rdmacore52_0_madrpc_timeout in rpc.c.o\n-mad_rpc_set_retries in rpc.c.o\n-mad_rpc_set_timeout in rpc.c.o\n-madrpc_portid in rpc.c.o\n-rdmacore52_0_ibmp in rpc.c.o\n-mad_rpc_portid in rpc.c.o\n-mad_rpc_class_agent in rpc.c.o\n-mad_rpc in rpc.c.o\n-mad_rpc_rmpp in rpc.c.o\n-madrpc in rpc.c.o\n-madrpc_rmpp in rpc.c.o\n-madrpc_init in rpc.c.o\n-mad_rpc_open_port in rpc.c.o\n-mad_rpc_close_port in rpc.c.o\n-pma_query_via in gs.c.o\n-performance_reset_via in gs.c.o\n-mad_get_field in fields.c.o\n-mad_set_field in fields.c.o\n-mad_get_field64 in fields.c.o\n-mad_set_field64 in fields.c.o\n-mad_set_array in fields.c.o\n-mad_get_array in fields.c.o\n-mad_decode_field in fields.c.o\n-mad_encode_field in fields.c.o\n-mad_print_field in fields.c.o\n-mad_dump_field in fields.c.o\n-mad_dump_val in fields.c.o\n-mad_field_name in fields.c.o\n+sa_rpc_call in sa.c.o\n+sa_call in sa.c.o\n+ib_path_query_via in sa.c.o\n+ib_path_query in sa.c.o\n+ib_node_query_via in sa.c.o\n \n-mad.c.o:\n+fields.c.o:\n 0000000000000000 r .LC0\n-0000000000000038 r .LC1\n- U __errno_location\n+0000000000000006 r .LC1\n+ U __memset_chk\n+ U __printf_chk\n+ U __snprintf_chk\n+ U __stack_chk_fail\n+0000000000000000 t _mad_dump\n+0000000000000000 d ib_mad_f\n+0000000000000540 T mad_decode_field\n+ U mad_dump_array\n+0000000000000980 T mad_dump_field\n+ U mad_dump_hex\n+ U mad_dump_linkdowndefstate\n+ U mad_dump_linkspeed\n+ U mad_dump_linkspeeden\n+ U mad_dump_linkspeedext\n+ U mad_dump_linkspeedexten\n+ U mad_dump_linkspeedextsup\n+ U mad_dump_linkspeedsup\n+ U mad_dump_linkwidth\n+ U mad_dump_linkwidthen\n+ U mad_dump_linkwidthsup\n+ U mad_dump_mtu\n+ U mad_dump_node_type\n+ U mad_dump_opervls\n+ U mad_dump_physportstate\n+ U mad_dump_portcapmask\n+ U mad_dump_portcapmask2\n+ U mad_dump_portstate\n+ U mad_dump_rhex\n+ U mad_dump_string\n+ U mad_dump_uint\n+0000000000000ab0 T mad_dump_val\n+ U mad_dump_vlcap\n+0000000000000720 T mad_encode_field\n+0000000000000b20 T mad_field_name\n+00000000000004d0 T mad_get_array\n+0000000000000120 T mad_get_field\n+00000000000003e0 T mad_get_field64\n+0000000000000920 T mad_print_field\n+0000000000000460 T mad_set_array\n+0000000000000280 T mad_set_field\n+0000000000000420 T mad_set_field64\n+ U memcpy\n+ U rdmacore52_0_mad_dump_linkspeedext2\n+ U rdmacore52_0_mad_dump_linkspeedexten2\n+ U rdmacore52_0_mad_dump_linkspeedextsup2\n+ U strlen\n+\n+smp.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n U __fprintf_chk\n 0000000000000000 r __func__.0\n+0000000000000020 r __func__.1\n U __stack_chk_fail\n U getpid\n-0000000000000460 T mad_build_pkt\n-0000000000000090 T mad_encode\n-0000000000000070 T mad_get_retries\n-0000000000000050 T mad_get_timeout\n- U mad_set_array\n- U mad_set_field\n- U mad_set_field64\n-0000000000000000 T mad_trid\n- U memcpy\n- U random\n- U rdmacore52_0_madrpc_retries\n- U rdmacore52_0_madrpc_timeout\n- U srandom\n+ U ibdebug\n+ U mad_rpc\n+ U portid2str\n+ U rdmacore52_0_ibmp\n+0000000000000010 T smp_mkey_get\n+0000000000000000 T smp_mkey_set\n+00000000000006f0 T smp_query\n+0000000000000430 T smp_query_status_via\n+00000000000005a0 T smp_query_via\n+00000000000002e0 T smp_set\n+0000000000000020 T smp_set_status_via\n+0000000000000190 T smp_set_via\n U stderr\n- U time\n-0000000000000000 b trid.1\n- U umad_get_mad\n- U umad_set_addr\n- U umad_set_grh\n- U umad_set_pkey\n \n-vendor.c.o:\n+bm.c.o:\n 0000000000000000 r .LC0\n 0000000000000028 r .LC1\n- U __errno_location\n+0000000000000000 r .LC2\n+0000000000000058 r .LC3\n U __fprintf_chk\n 0000000000000000 r __func__.0\n U __stack_chk_fail\n+0000000000000000 T bm_call_via\n U getpid\n-0000000000000000 T ib_vendor_call\n-0000000000000270 T ib_vendor_call_via\n U ibdebug\n- U mad_rpc_rmpp\n+ U mad_rpc\n U mad_send_via\n U portid2str\n- U rdmacore52_0_ibmp\n U stderr\n \n-sa.c.o:\n+rpc.c.o:\n 0000000000000000 r .LC0\n-0000000000000030 r .LC1\n-0000000000000000 r .LC2\n-0000000000000008 r .LC4\n-0000000000000060 r .LC6\n-0000000000000090 r .LC8\n+0000000000000000 r .LC1\n+0000000000000140 r .LC10\n+0000000000000180 r .LC11\n+00000000000001c8 r .LC12\n+0000000000000210 r .LC13\n+0000000000000238 r .LC14\n+0000000000000260 r .LC15\n+000000000000002e r .LC16\n+0000000000000290 r .LC17\n+00000000000002c0 r .LC18\n+00000000000002f8 r .LC19\n+0000000000000030 r .LC2\n+0000000000000330 r .LC20\n+0000000000000370 r .LC21\n+00000000000003a0 r .LC22\n+0000000000000034 r .LC23\n+00000000000003d0 r .LC24\n+0000000000000400 r .LC25\n+0000000000000058 r .LC3\n+0000000000000088 r .LC4\n+00000000000000b0 r .LC5\n+000000000000000a r .LC6\n+0000000000000025 r .LC7\n+00000000000000d8 r .LC8\n+0000000000000110 r .LC9\n+ U __errno_location\n U __fprintf_chk\n 0000000000000000 r __func__.0\n-0000000000000020 r __func__.1\n-0000000000000038 r __func__.2\n+0000000000000018 r __func__.1\n+0000000000000028 r __func__.2\n+0000000000000038 r __func__.3\n+0000000000000048 r __func__.4\n+0000000000000058 r __func__.5\n+ U __memset_chk\n U __stack_chk_fail\n+0000000000000000 t _do_madrpc\n+ U calloc\n+ U exit\n+ U free\n+ U getenv\n U getpid\n-0000000000000590 T ib_node_query_via\n-0000000000000570 T ib_path_query\n-0000000000000320 T ib_path_query_via\n- U ibdebug\n- U mad_decode_field\n- U mad_encode_field\n- U mad_rpc_rmpp\n- U mad_trid\n+0000000000000000 B ibdebug\n+0000000000000010 b iberrs\n+ U mad_build_pkt\n+ U mad_get_field\n+ U mad_get_field64\n+ U mad_get_retries\n+ U mad_get_timeout\n+0000000000000020 b mad_port\n+ U mad_register_client_via\n+00000000000004d0 T mad_rpc\n+00000000000004a0 T mad_rpc_class_agent\n+0000000000001010 T mad_rpc_close_port\n+0000000000000db0 T mad_rpc_open_port\n+0000000000000490 T mad_rpc_portid\n+0000000000000850 T mad_rpc_rmpp\n+0000000000000460 T mad_rpc_set_retries\n+0000000000000470 T mad_rpc_set_timeout\n+0000000000000bf0 T madrpc\n+0000000000000c30 T madrpc_init\n+0000000000000480 T madrpc_portid\n+0000000000000c10 T madrpc_rmpp\n+0000000000000410 T madrpc_save_mad\n+0000000000000430 T madrpc_set_retries\n+0000000000000450 T madrpc_set_timeout\n+0000000000000400 T madrpc_show_errors\n+ U memcpy\n U portid2str\n- U rdmacore52_0_ibmp\n-0000000000000190 T sa_call\n-0000000000000000 T sa_rpc_call\n+0000000000000000 D rdmacore52_0_ibmp\n+0000000000000008 D rdmacore52_0_madrpc_retries\n+0000000000000004 D rdmacore52_0_madrpc_timeout\n+0000000000000008 b save_mad\n+0000000000000000 d save_mad_len\n U stderr\n+ U strerror\n+ U strtol\n+ U umad_addr_dump\n+ U umad_close_port\n+ U umad_get_mad\n+ U umad_get_mad_addr\n+ U umad_init\n+ U umad_open_port\n+ U umad_recv\n+ U umad_send\n+ U umad_size\n+ U umad_status\n+ U xdump\n \n portid.c.o:\n 0000000000000000 r .LC0\n 0000000000000007 r .LC1\n 000000000000000f r .LC2\n 0000000000000024 r .LC3\n 0000000000000028 r .LC4\n@@ -254,71 +359,119 @@\n 0000000000000030 T portid2str\n U stderr\n 0000000000000230 T str2drpath\n U strchr\n U strdup\n U strtol\n \n-serv.c.o:\n+gs.c.o:\n 0000000000000000 r .LC0\n 0000000000000028 r .LC1\n 0000000000000000 r .LC2\n-0000000000000050 r .LC3\n-000000000000000f r .LC4\n-0000000000000078 r .LC5\n-0000000000000029 r .LC6\n-00000000000000d8 r .LC7\n+0000000000000008 r .LC3\n+0000000000000058 r .LC5\n+0000000000000010 r .LC6\n U __errno_location\n U __fprintf_chk\n 0000000000000000 r __func__.0\n-0000000000000010 r __func__.1\n-0000000000000020 r __func__.2\n- U __memset_chk\n+0000000000000018 r __func__.1\n U __stack_chk_fail\n- U calloc\n- U free\n U getpid\n U ibdebug\n-00000000000008a0 T mad_alloc\n- U mad_build_pkt\n-00000000000008d0 T mad_free\n- U mad_get_field\n- U mad_get_field64\n- U mad_get_timeout\n-0000000000000640 T mad_receive\n-0000000000000770 T mad_receive_via\n-0000000000000630 T mad_respond\n-0000000000000200 T mad_respond_via\n-00000000000001f0 T mad_send\n-0000000000000000 T mad_send_via\n+ U mad_rpc\n+ U mad_set_field\n+00000000000001a0 T performance_reset_via\n+0000000000000000 T pma_query_via\n+ U stderr\n+\n+cc.c.o:\n+0000000000000000 r .LC0\n+ U __fprintf_chk\n+0000000000000000 r __func__.0\n+0000000000000020 r __func__.1\n+ U __stack_chk_fail\n+0000000000000170 T cc_config_status_via\n+0000000000000000 T cc_query_status_via\n+ U getpid\n+ U ibdebug\n+ U mad_rpc\n U portid2str\n- U rdmacore52_0_ibmp\n U stderr\n- U strerror\n+\n+mad.c.o:\n+0000000000000000 r .LC0\n+0000000000000038 r .LC1\n+ U __errno_location\n+ U __fprintf_chk\n+0000000000000000 r __func__.0\n+ U __stack_chk_fail\n+ U getpid\n+0000000000000460 T mad_build_pkt\n+0000000000000090 T mad_encode\n+0000000000000070 T mad_get_retries\n+0000000000000050 T mad_get_timeout\n+ U mad_set_array\n+ U mad_set_field\n+ U mad_set_field64\n+0000000000000000 T mad_trid\n+ U memcpy\n+ U random\n+ U rdmacore52_0_madrpc_retries\n+ U rdmacore52_0_madrpc_timeout\n+ U srandom\n+ U stderr\n+ U time\n+0000000000000000 b trid.1\n U umad_get_mad\n- U umad_get_mad_addr\n- U umad_recv\n- U umad_send\n- U umad_size\n- U xdump\n+ U umad_set_addr\n+ U umad_set_grh\n+ U umad_set_pkey\n \n-bm.c.o:\n+resolve.c.o:\n+0000000000000000 r .LC0\n+ U __errno_location\n+ U __fprintf_chk\n+0000000000000020 r __func__.0\n+ U __stack_chk_fail\n+ U getpid\n+ U ib_path_query_via\n+0000000000000200 T ib_resolve_gid_via\n+0000000000000320 T ib_resolve_guid_via\n+00000000000009e0 T ib_resolve_portid_str\n+00000000000006c0 T ib_resolve_portid_str_via\n+00000000000009f0 T ib_resolve_self\n+0000000000000560 T ib_resolve_self_via\n+0000000000000100 T ib_resolve_smlid\n+0000000000000000 T ib_resolve_smlid_via\n+ U inet_pton\n+ U mad_decode_field\n+ U mad_encode_field\n+ U mad_set_field64\n+ U rdmacore52_0_ibmp\n+ U smp_query_via\n+ U stderr\n+ U str2drpath\n+ U strtol\n+ U strtoull\n+\n+vendor.c.o:\n 0000000000000000 r .LC0\n 0000000000000028 r .LC1\n-0000000000000000 r .LC2\n-0000000000000058 r .LC3\n+ U __errno_location\n U __fprintf_chk\n 0000000000000000 r __func__.0\n U __stack_chk_fail\n-0000000000000000 T bm_call_via\n U getpid\n+0000000000000000 T ib_vendor_call\n+0000000000000270 T ib_vendor_call_via\n U ibdebug\n- U mad_rpc\n+ U mad_rpc_rmpp\n U mad_send_via\n U portid2str\n+ U rdmacore52_0_ibmp\n U stderr\n \n dump.c.o:\n 0000000000000000 r .LC0\n 0000000000000003 r .LC1\n 000000000000002f r .LC10\n 0000000000000160 r .LC100\n@@ -577,76 +730,56 @@\n 00000000000010f0 T rdmacore52_0_mad_dump_linkspeedextsup2\n U snprintf\n U stderr\n U strlen\n U strncpy\n 0000000000004ff0 T xdump\n \n-cc.c.o:\n-0000000000000000 r .LC0\n- U __fprintf_chk\n-0000000000000000 r __func__.0\n-0000000000000020 r __func__.1\n- U __stack_chk_fail\n-0000000000000170 T cc_config_status_via\n-0000000000000000 T cc_query_status_via\n- U getpid\n- U ibdebug\n- U mad_rpc\n- U portid2str\n- U stderr\n-\n-resolve.c.o:\n+serv.c.o:\n 0000000000000000 r .LC0\n+0000000000000028 r .LC1\n+0000000000000000 r .LC2\n+0000000000000050 r .LC3\n+000000000000000f r .LC4\n+0000000000000078 r .LC5\n+0000000000000029 r .LC6\n+00000000000000d8 r .LC7\n U __errno_location\n U __fprintf_chk\n-0000000000000020 r __func__.0\n- U __stack_chk_fail\n- U getpid\n- U ib_path_query_via\n-0000000000000200 T ib_resolve_gid_via\n-0000000000000320 T ib_resolve_guid_via\n-00000000000009e0 T ib_resolve_portid_str\n-00000000000006c0 T ib_resolve_portid_str_via\n-00000000000009f0 T ib_resolve_self\n-0000000000000560 T ib_resolve_self_via\n-0000000000000100 T ib_resolve_smlid\n-0000000000000000 T ib_resolve_smlid_via\n- U inet_pton\n- U mad_decode_field\n- U mad_encode_field\n- U mad_set_field64\n- U rdmacore52_0_ibmp\n- U smp_query_via\n- U stderr\n- U str2drpath\n- U strtol\n- U strtoull\n-\n-smp.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n- U __fprintf_chk\n 0000000000000000 r __func__.0\n-0000000000000020 r __func__.1\n+0000000000000010 r __func__.1\n+0000000000000020 r __func__.2\n+ U __memset_chk\n U __stack_chk_fail\n+ U calloc\n+ U free\n U getpid\n U ibdebug\n- U mad_rpc\n+00000000000008a0 T mad_alloc\n+ U mad_build_pkt\n+00000000000008d0 T mad_free\n+ U mad_get_field\n+ U mad_get_field64\n+ U mad_get_timeout\n+0000000000000640 T mad_receive\n+0000000000000770 T mad_receive_via\n+0000000000000630 T mad_respond\n+0000000000000200 T mad_respond_via\n+00000000000001f0 T mad_send\n+0000000000000000 T mad_send_via\n U portid2str\n U rdmacore52_0_ibmp\n-0000000000000010 T smp_mkey_get\n-0000000000000000 T smp_mkey_set\n-00000000000006f0 T smp_query\n-0000000000000430 T smp_query_status_via\n-00000000000005a0 T smp_query_via\n-00000000000002e0 T smp_set\n-0000000000000020 T smp_set_status_via\n-0000000000000190 T smp_set_via\n U stderr\n+ U strerror\n+ U umad_get_mad\n+ U umad_get_mad_addr\n+ U umad_recv\n+ U umad_send\n+ U umad_size\n+ U xdump\n \n register.c.o:\n 0000000000000000 r .LC0\n 0000000000000030 r .LC1\n 0000000000000068 r .LC2\n 00000000000000a0 r .LC3\n U __fprintf_chk\n@@ -663,166 +796,33 @@\n U mad_rpc_portid\n U rdmacore52_0_ibmp\n 0000000000000030 T rdmacore52_0_mad_register_port_client\n U stderr\n U umad_register\n U umad_register_oui\n \n-rpc.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n-0000000000000140 r .LC10\n-0000000000000180 r .LC11\n-00000000000001c8 r .LC12\n-0000000000000210 r .LC13\n-0000000000000238 r .LC14\n-0000000000000260 r .LC15\n-000000000000002e r .LC16\n-0000000000000290 r .LC17\n-00000000000002c0 r .LC18\n-00000000000002f8 r .LC19\n-0000000000000030 r .LC2\n-0000000000000330 r .LC20\n-0000000000000370 r .LC21\n-00000000000003a0 r .LC22\n-0000000000000034 r .LC23\n-00000000000003d0 r .LC24\n-0000000000000400 r .LC25\n-0000000000000058 r .LC3\n-0000000000000088 r .LC4\n-00000000000000b0 r .LC5\n-000000000000000a r .LC6\n-0000000000000025 r .LC7\n-00000000000000d8 r .LC8\n-0000000000000110 r .LC9\n- U __errno_location\n- U __fprintf_chk\n-0000000000000000 r __func__.0\n-0000000000000018 r __func__.1\n-0000000000000028 r __func__.2\n-0000000000000038 r __func__.3\n-0000000000000048 r __func__.4\n-0000000000000058 r __func__.5\n- U __memset_chk\n- U __stack_chk_fail\n-0000000000000000 t _do_madrpc\n- U calloc\n- U exit\n- U free\n- U getenv\n- U getpid\n-0000000000000000 B ibdebug\n-0000000000000010 b iberrs\n- U mad_build_pkt\n- U mad_get_field\n- U mad_get_field64\n- U mad_get_retries\n- U mad_get_timeout\n-0000000000000020 b mad_port\n- U mad_register_client_via\n-00000000000004d0 T mad_rpc\n-00000000000004a0 T mad_rpc_class_agent\n-0000000000001010 T mad_rpc_close_port\n-0000000000000db0 T mad_rpc_open_port\n-0000000000000490 T mad_rpc_portid\n-0000000000000850 T mad_rpc_rmpp\n-0000000000000460 T mad_rpc_set_retries\n-0000000000000470 T mad_rpc_set_timeout\n-0000000000000bf0 T madrpc\n-0000000000000c30 T madrpc_init\n-0000000000000480 T madrpc_portid\n-0000000000000c10 T madrpc_rmpp\n-0000000000000410 T madrpc_save_mad\n-0000000000000430 T madrpc_set_retries\n-0000000000000450 T madrpc_set_timeout\n-0000000000000400 T madrpc_show_errors\n- U memcpy\n- U portid2str\n-0000000000000000 D rdmacore52_0_ibmp\n-0000000000000008 D rdmacore52_0_madrpc_retries\n-0000000000000004 D rdmacore52_0_madrpc_timeout\n-0000000000000008 b save_mad\n-0000000000000000 d save_mad_len\n- U stderr\n- U strerror\n- U strtol\n- U umad_addr_dump\n- U umad_close_port\n- U umad_get_mad\n- U umad_get_mad_addr\n- U umad_init\n- U umad_open_port\n- U umad_recv\n- U umad_send\n- U umad_size\n- U umad_status\n- U xdump\n-\n-gs.c.o:\n+sa.c.o:\n 0000000000000000 r .LC0\n-0000000000000028 r .LC1\n+0000000000000030 r .LC1\n 0000000000000000 r .LC2\n-0000000000000008 r .LC3\n-0000000000000058 r .LC5\n-0000000000000010 r .LC6\n- U __errno_location\n+0000000000000008 r .LC4\n+0000000000000060 r .LC6\n+0000000000000090 r .LC8\n U __fprintf_chk\n 0000000000000000 r __func__.0\n-0000000000000018 r __func__.1\n+0000000000000020 r __func__.1\n+0000000000000038 r __func__.2\n U __stack_chk_fail\n U getpid\n+0000000000000590 T ib_node_query_via\n+0000000000000570 T ib_path_query\n+0000000000000320 T ib_path_query_via\n U ibdebug\n- U mad_rpc\n- U mad_set_field\n-00000000000001a0 T performance_reset_via\n-0000000000000000 T pma_query_via\n+ U mad_decode_field\n+ U mad_encode_field\n+ U mad_rpc_rmpp\n+ U mad_trid\n+ U portid2str\n+ U rdmacore52_0_ibmp\n+0000000000000190 T sa_call\n+0000000000000000 T sa_rpc_call\n U stderr\n-\n-fields.c.o:\n-0000000000000000 r .LC0\n-0000000000000006 r .LC1\n- U __memset_chk\n- U __printf_chk\n- U __snprintf_chk\n- U __stack_chk_fail\n-0000000000000000 t _mad_dump\n-0000000000000000 d ib_mad_f\n-0000000000000540 T mad_decode_field\n- U mad_dump_array\n-0000000000000980 T mad_dump_field\n- U mad_dump_hex\n- U mad_dump_linkdowndefstate\n- U mad_dump_linkspeed\n- U mad_dump_linkspeeden\n- U mad_dump_linkspeedext\n- U mad_dump_linkspeedexten\n- U mad_dump_linkspeedextsup\n- U mad_dump_linkspeedsup\n- U mad_dump_linkwidth\n- U mad_dump_linkwidthen\n- U mad_dump_linkwidthsup\n- U mad_dump_mtu\n- U mad_dump_node_type\n- U mad_dump_opervls\n- U mad_dump_physportstate\n- U mad_dump_portcapmask\n- U mad_dump_portcapmask2\n- U mad_dump_portstate\n- U mad_dump_rhex\n- U mad_dump_string\n- U mad_dump_uint\n-0000000000000ab0 T mad_dump_val\n- U mad_dump_vlcap\n-0000000000000720 T mad_encode_field\n-0000000000000b20 T mad_field_name\n-00000000000004d0 T mad_get_array\n-0000000000000120 T mad_get_field\n-00000000000003e0 T mad_get_field64\n-0000000000000920 T mad_print_field\n-0000000000000460 T mad_set_array\n-0000000000000280 T mad_set_field\n-0000000000000420 T mad_set_field64\n- U memcpy\n- U rdmacore52_0_mad_dump_linkspeedext2\n- U rdmacore52_0_mad_dump_linkspeedexten2\n- U rdmacore52_0_mad_dump_linkspeedextsup2\n- U strlen\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,15 +1,15 @@\n ---------- 0 0 0 4042 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 6128 1970-01-01 00:00:00.000000 mad.c.o\n-?rw-r--r-- 0 0 0 4296 1970-01-01 00:00:00.000000 vendor.c.o\n-?rw-r--r-- 0 0 0 6896 1970-01-01 00:00:00.000000 sa.c.o\n-?rw-r--r-- 0 0 0 5232 1970-01-01 00:00:00.000000 portid.c.o\n-?rw-r--r-- 0 0 0 8536 1970-01-01 00:00:00.000000 serv.c.o\n+?rw-r--r-- 0 0 0 54872 1970-01-01 00:00:00.000000 fields.c.o\n+?rw-r--r-- 0 0 0 6504 1970-01-01 00:00:00.000000 smp.c.o\n ?rw-r--r-- 0 0 0 3624 1970-01-01 00:00:00.000000 bm.c.o\n-?rw-r--r-- 0 0 0 59096 1970-01-01 00:00:00.000000 dump.c.o\n+?rw-r--r-- 0 0 0 16872 1970-01-01 00:00:00.000000 rpc.c.o\n+?rw-r--r-- 0 0 0 5232 1970-01-01 00:00:00.000000 portid.c.o\n+?rw-r--r-- 0 0 0 4232 1970-01-01 00:00:00.000000 gs.c.o\n ?rw-r--r-- 0 0 0 3168 1970-01-01 00:00:00.000000 cc.c.o\n+?rw-r--r-- 0 0 0 6128 1970-01-01 00:00:00.000000 mad.c.o\n ?rw-r--r-- 0 0 0 6992 1970-01-01 00:00:00.000000 resolve.c.o\n-?rw-r--r-- 0 0 0 6504 1970-01-01 00:00:00.000000 smp.c.o\n+?rw-r--r-- 0 0 0 4296 1970-01-01 00:00:00.000000 vendor.c.o\n+?rw-r--r-- 0 0 0 59096 1970-01-01 00:00:00.000000 dump.c.o\n+?rw-r--r-- 0 0 0 8536 1970-01-01 00:00:00.000000 serv.c.o\n ?rw-r--r-- 0 0 0 6832 1970-01-01 00:00:00.000000 register.c.o\n-?rw-r--r-- 0 0 0 16872 1970-01-01 00:00:00.000000 rpc.c.o\n-?rw-r--r-- 0 0 0 4232 1970-01-01 00:00:00.000000 gs.c.o\n-?rw-r--r-- 0 0 0 54872 1970-01-01 00:00:00.000000 fields.c.o\n+?rw-r--r-- 0 0 0 6896 1970-01-01 00:00:00.000000 sa.c.o\n"}]}]}]}]}, {"source1": "libibnetdisc-dev_52.0-2_amd64.deb", "source2": "libibnetdisc-dev_52.0-2_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2024-06-27 11:49:34.000000 debian-binary\n--rw-r--r-- 0 0 0 1072 2024-06-27 11:49:34.000000 control.tar.xz\n--rw-r--r-- 0 0 0 44184 2024-06-27 11:49:34.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 1068 2024-06-27 11:49:34.000000 control.tar.xz\n+-rw-r--r-- 0 0 0 44232 2024-06-27 11:49:34.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/x86_64-linux-gnu/libibnetdisc.a", "source2": "./usr/lib/x86_64-linux-gnu/libibnetdisc.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "comments": ["error from `nm -s {}`:", "nm: mmio.c.o: no symbols"], "unified_diff": "@@ -1,15 +1,9 @@\n \n Archive index:\n-rdmacore52_0_issue_smp in query_smp.c.o\n-rdmacore52_0_smp_engine_init in query_smp.c.o\n-rdmacore52_0_smp_engine_destroy in query_smp.c.o\n-rdmacore52_0_process_mads in query_smp.c.o\n-ibnd_load_fabric in ibnetdisc_cache.c.o\n-ibnd_cache_fabric in ibnetdisc_cache.c.o\n ibnd_find_node_guid in ibnetdisc.c.o\n rdmacore52_0_add_to_nodeguid_hash in ibnetdisc.c.o\n rdmacore52_0_add_to_portguid_hash in ibnetdisc.c.o\n rdmacore52_0_create_lid2guid in ibnetdisc.c.o\n rdmacore52_0_destroy_lid2guid in ibnetdisc.c.o\n rdmacore52_0_add_to_portlid_hash in ibnetdisc.c.o\n rdmacore52_0_add_to_type_list in ibnetdisc.c.o\n@@ -36,160 +30,51 @@\n ibnd_get_chassis_type in chassis.c.o\n ibnd_get_chassis_slot_str in chassis.c.o\n ibnd_is_xsigo_guid in chassis.c.o\n ibnd_is_xsigo_hca in chassis.c.o\n ibnd_is_xsigo_tca in chassis.c.o\n ibnd_get_chassis_guid in chassis.c.o\n rdmacore52_0_group_nodes in chassis.c.o\n-rdmacore52_0_bitmap_find_first_bit in bitmap.c.o\n-rdmacore52_0_bitmap_zero_region in bitmap.c.o\n-rdmacore52_0_bitmap_fill_region in bitmap.c.o\n-rdmacore52_0_bitmap_find_free_region in bitmap.c.o\n+rdmacore52_0_issue_smp in query_smp.c.o\n+rdmacore52_0_smp_engine_init in query_smp.c.o\n+rdmacore52_0_smp_engine_destroy in query_smp.c.o\n+rdmacore52_0_process_mads in query_smp.c.o\n+ibnd_load_fabric in ibnetdisc_cache.c.o\n+ibnd_cache_fabric in ibnetdisc_cache.c.o\n rdmacore52_0_cl_qmap_init in cl_map.c.o\n rdmacore52_0_cl_qmap_get in cl_map.c.o\n rdmacore52_0_cl_qmap_get_next in cl_map.c.o\n rdmacore52_0_cl_qmap_apply_func in cl_map.c.o\n rdmacore52_0_cl_qmap_insert in cl_map.c.o\n rdmacore52_0_cl_qmap_remove_item in cl_map.c.o\n rdmacore52_0_cl_qmap_remove in cl_map.c.o\n rdmacore52_0_cl_qmap_merge in cl_map.c.o\n rdmacore52_0_cl_qmap_delta in cl_map.c.o\n-rdmacore52_0_set_fd_nonblock in util.c.o\n-rdmacore52_0_get_random in util.c.o\n-rdmacore52_0_check_env in util.c.o\n-rdmacore52_0_xorshift32 in util.c.o\n+rdmacore52_0_rdmanl_socket_alloc in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_copy_on_fork in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_devices in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_chardev in rdma_nl.c.o\n+rdmacore52_0_rdmanl_policy in rdma_nl.c.o\n+rdmacore52_0_open_cdev in open_cdev.c.o\n rdmacore52_0_close_node_name_map in node_name_map.c.o\n rdmacore52_0_remap_node_name in node_name_map.c.o\n rdmacore52_0_clean_nodedesc in node_name_map.c.o\n rdmacore52_0_open_node_name_map in node_name_map.c.o\n rdmacore52_0_iset_create in interval_set.c.o\n rdmacore52_0_iset_destroy in interval_set.c.o\n rdmacore52_0_iset_insert_range in interval_set.c.o\n rdmacore52_0_iset_alloc_range in interval_set.c.o\n-rdmacore52_0_rdmanl_socket_alloc in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_copy_on_fork in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_devices in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_chardev in rdma_nl.c.o\n-rdmacore52_0_rdmanl_policy in rdma_nl.c.o\n-rdmacore52_0_open_cdev in open_cdev.c.o\n-\n-query_smp.c.o:\n-0000000000000000 r .LC0\n-000000000000001b r .LC1\n-000000000000007a r .LC10\n-00000000000000c8 r .LC11\n-00000000000000f0 r .LC12\n-0000000000000120 r .LC13\n-0000000000000093 r .LC14\n-0000000000000158 r .LC15\n-0000000000000000 r .LC2\n-0000000000000039 r .LC3\n-0000000000000051 r .LC4\n-0000000000000028 r .LC5\n-0000000000000060 r .LC6\n-0000000000000098 r .LC7\n-000000000000006e r .LC8\n-0000000000000000 r .LC9\n- U __fprintf_chk\n- U __memset_chk\n- U __stack_chk_fail\n- U calloc\n- U free\n- U mad_build_pkt\n- U mad_get_field\n- U mad_get_field64\n- U mad_trid\n- U portid2str\n-0000000000000180 t process_one_recv\n- U rdmacore52_0_cl_qmap_init\n- U rdmacore52_0_cl_qmap_insert\n- U rdmacore52_0_cl_qmap_remove\n- U rdmacore52_0_cl_qmap_remove_item\n-0000000000000460 T rdmacore52_0_issue_smp\n- U rdmacore52_0_mlnx_ext_port_info_err\n-0000000000000940 T rdmacore52_0_process_mads\n-0000000000000830 T rdmacore52_0_smp_engine_destroy\n-00000000000006a0 T rdmacore52_0_smp_engine_init\n-0000000000000000 t send_smp\n- U stderr\n- U strerror\n- U umad_close_port\n- U umad_get_mad\n- U umad_init\n- U umad_open_port\n- U umad_recv\n- U umad_register\n- U umad_send\n- U umad_size\n- U umad_status\n-\n-ibnetdisc_cache.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n-000000000000007e r .LC10\n-0000000000000090 r .LC11\n-0000000000000000 r .LC12\n-00000000000000a2 r .LC13\n-00000000000000be r .LC14\n-00000000000000cf r .LC15\n-00000000000000e9 r .LC16\n-00000000000000a0 r .LC17\n-00000000000000d0 r .LC18\n-00000000000000fd r .LC19\n-0000000000000011 r .LC2\n-0000000000000120 r .LC20\n-0000000000000148 r .LC21\n-0000000000000180 r .LC22\n-00000000000001d0 r .LC23\n-00000000000001f8 r .LC24\n-0000000000000116 r .LC25\n-0000000000000228 r .LC26\n-0000000000000248 r .LC27\n-0000000000000134 r .LC28\n-000000000000002a r .LC3\n-000000000000003c r .LC4\n-0000000000000054 r .LC5\n-0000000000000028 r .LC6\n-0000000000000050 r .LC7\n-0000000000000078 r .LC8\n-0000000000000066 r .LC9\n- U __errno_location\n- U __printf_chk\n- U __stack_chk_fail\n-0000000000000990 t _cache_header_counts\n-0000000000000b30 t _cache_header_info.isra.0\n-0000000000000c20 t _cache_node\n-00000000000000e0 t _cache_port\n-0000000000000250 t _destroy_ibnd_fabric_cache\n-00000000000006a0 t _load_header_info.constprop.0\n-00000000000002f0 t _load_node\n-00000000000007b0 t _load_port\n- U calloc\n- U close\n- U free\n- U ibdebug\n-00000000000015b0 T ibnd_cache_fabric\n- U ibnd_destroy_fabric\n-0000000000000e80 T ibnd_load_fabric\n-0000000000000000 t ibnd_read\n- U lseek\n- U malloc\n- U open\n- U rdmacore52_0_add_to_nodeguid_hash\n- U rdmacore52_0_add_to_portguid_hash\n- U rdmacore52_0_add_to_portlid_hash\n- U rdmacore52_0_add_to_type_list\n- U rdmacore52_0_allocate_fabric_internal\n- U rdmacore52_0_destroy_node\n- U rdmacore52_0_group_nodes\n- U read\n- U stat\n- U strerror\n- U unlink\n- U write\n+rdmacore52_0_bitmap_find_first_bit in bitmap.c.o\n+rdmacore52_0_bitmap_zero_region in bitmap.c.o\n+rdmacore52_0_bitmap_fill_region in bitmap.c.o\n+rdmacore52_0_bitmap_find_free_region in bitmap.c.o\n+rdmacore52_0_set_fd_nonblock in util.c.o\n+rdmacore52_0_get_random in util.c.o\n+rdmacore52_0_check_env in util.c.o\n+rdmacore52_0_xorshift32 in util.c.o\n \n ibnetdisc.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000128 r .LC10\n 0000000000000150 r .LC11\n 0000000000000180 r .LC12\n@@ -371,43 +256,183 @@\n 00000000000005e0 r spine12_slot_2_slb\n 0000000000000520 r spine18_slot_2_slb\n 00000000000005e0 r spine4_slot_2_slb\n U stderr\n U strncpy\n U strtol\n \n-bitmap.c.o:\n- U memset\n-0000000000000160 T rdmacore52_0_bitmap_fill_region\n-0000000000000000 T rdmacore52_0_bitmap_find_first_bit\n-0000000000000220 T rdmacore52_0_bitmap_find_free_region\n-0000000000000090 T rdmacore52_0_bitmap_zero_region\n+query_smp.c.o:\n+0000000000000000 r .LC0\n+000000000000001b r .LC1\n+000000000000007a r .LC10\n+00000000000000c8 r .LC11\n+00000000000000f0 r .LC12\n+0000000000000120 r .LC13\n+0000000000000093 r .LC14\n+0000000000000158 r .LC15\n+0000000000000000 r .LC2\n+0000000000000039 r .LC3\n+0000000000000051 r .LC4\n+0000000000000028 r .LC5\n+0000000000000060 r .LC6\n+0000000000000098 r .LC7\n+000000000000006e r .LC8\n+0000000000000000 r .LC9\n+ U __fprintf_chk\n+ U __memset_chk\n+ U __stack_chk_fail\n+ U calloc\n+ U free\n+ U mad_build_pkt\n+ U mad_get_field\n+ U mad_get_field64\n+ U mad_trid\n+ U portid2str\n+0000000000000180 t process_one_recv\n+ U rdmacore52_0_cl_qmap_init\n+ U rdmacore52_0_cl_qmap_insert\n+ U rdmacore52_0_cl_qmap_remove\n+ U rdmacore52_0_cl_qmap_remove_item\n+0000000000000460 T rdmacore52_0_issue_smp\n+ U rdmacore52_0_mlnx_ext_port_info_err\n+0000000000000940 T rdmacore52_0_process_mads\n+0000000000000830 T rdmacore52_0_smp_engine_destroy\n+00000000000006a0 T rdmacore52_0_smp_engine_init\n+0000000000000000 t send_smp\n+ U stderr\n+ U strerror\n+ U umad_close_port\n+ U umad_get_mad\n+ U umad_init\n+ U umad_open_port\n+ U umad_recv\n+ U umad_register\n+ U umad_send\n+ U umad_size\n+ U umad_status\n+\n+ibnetdisc_cache.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n+000000000000007e r .LC10\n+0000000000000090 r .LC11\n+0000000000000000 r .LC12\n+00000000000000a2 r .LC13\n+00000000000000be r .LC14\n+00000000000000cf r .LC15\n+00000000000000e9 r .LC16\n+00000000000000a0 r .LC17\n+00000000000000d0 r .LC18\n+00000000000000fd r .LC19\n+0000000000000011 r .LC2\n+0000000000000120 r .LC20\n+0000000000000148 r .LC21\n+0000000000000180 r .LC22\n+00000000000001d0 r .LC23\n+00000000000001f8 r .LC24\n+0000000000000116 r .LC25\n+0000000000000228 r .LC26\n+0000000000000248 r .LC27\n+0000000000000134 r .LC28\n+000000000000002a r .LC3\n+000000000000003c r .LC4\n+0000000000000054 r .LC5\n+0000000000000028 r .LC6\n+0000000000000050 r .LC7\n+0000000000000078 r .LC8\n+0000000000000066 r .LC9\n+ U __errno_location\n+ U __printf_chk\n+ U __stack_chk_fail\n+0000000000000990 t _cache_header_counts\n+0000000000000b30 t _cache_header_info.isra.0\n+0000000000000c20 t _cache_node\n+00000000000000e0 t _cache_port\n+0000000000000250 t _destroy_ibnd_fabric_cache\n+00000000000006a0 t _load_header_info.constprop.0\n+00000000000002f0 t _load_node\n+00000000000007b0 t _load_port\n+ U calloc\n+ U close\n+ U free\n+ U ibdebug\n+00000000000015b0 T ibnd_cache_fabric\n+ U ibnd_destroy_fabric\n+0000000000000e80 T ibnd_load_fabric\n+0000000000000000 t ibnd_read\n+ U lseek\n+ U malloc\n+ U open\n+ U rdmacore52_0_add_to_nodeguid_hash\n+ U rdmacore52_0_add_to_portguid_hash\n+ U rdmacore52_0_add_to_portlid_hash\n+ U rdmacore52_0_add_to_type_list\n+ U rdmacore52_0_allocate_fabric_internal\n+ U rdmacore52_0_destroy_node\n+ U rdmacore52_0_group_nodes\n+ U read\n+ U stat\n+ U strerror\n+ U unlink\n+ U write\n+\n+mmio.c.o:\n \n cl_map.c.o:\n 0000000000000120 T rdmacore52_0_cl_qmap_apply_func\n 0000000000000e00 T rdmacore52_0_cl_qmap_delta\n 0000000000000060 T rdmacore52_0_cl_qmap_get\n 00000000000000c0 T rdmacore52_0_cl_qmap_get_next\n 0000000000000000 T rdmacore52_0_cl_qmap_init\n 0000000000000170 T rdmacore52_0_cl_qmap_insert\n 0000000000000940 T rdmacore52_0_cl_qmap_merge\n 00000000000008e0 T rdmacore52_0_cl_qmap_remove\n 0000000000000460 T rdmacore52_0_cl_qmap_remove_item\n \n-util.c.o:\n- U fcntl\n- U getenv\n- U getrandom\n- U rand_r\n-00000000000000d0 T rdmacore52_0_check_env\n-0000000000000050 T rdmacore52_0_get_random\n-0000000000000000 T rdmacore52_0_set_fd_nonblock\n-0000000000000110 T rdmacore52_0_xorshift32\n-0000000000000000 b seed.0\n- U time\n+rdma_nl.c.o:\n+ U __stack_chk_fail\n+ U nl_connect\n+ U nl_recvmsgs_default\n+ U nl_send_auto\n+ U nl_send_simple\n+ U nl_socket_alloc\n+ U nl_socket_disable_auto_ack\n+ U nl_socket_disable_msg_peek\n+ U nl_socket_free\n+ U nl_socket_modify_cb\n+ U nl_socket_modify_err_cb\n+ U nla_put\n+ U nlmsg_alloc_simple\n+ U nlmsg_free\n+0000000000000200 T rdmacore52_0_rdmanl_get_chardev\n+0000000000000060 T rdmacore52_0_rdmanl_get_copy_on_fork\n+0000000000000130 T rdmacore52_0_rdmanl_get_devices\n+0000000000000000 D rdmacore52_0_rdmanl_policy\n+0000000000000010 T rdmacore52_0_rdmanl_socket_alloc\n+0000000000000000 t rdmanl_saw_err_cb\n+ U strlen\n+\n+open_cdev.c.o:\n+0000000000000000 r .LC0\n+0000000000000010 r .LC1\n+000000000000001b r .LC2\n+ U __asprintf_chk\n+ U __stack_chk_fail\n+ U close\n+ U free\n+ U fstat\n+ U inotify_add_watch\n+ U inotify_init1\n+ U open\n+0000000000000000 t open_cdev_robust.isra.0\n+ U poll\n+0000000000000380 T rdmacore52_0_open_cdev\n+ U read\n+ U timerfd_create\n+ U timerfd_settime\n \n node_name_map.c.o:\n 0000000000000000 r .LC0\n 000000000000001b r .LC1\n 000000000000001d r .LC2\n 0000000000000000 r .LC3\n 0000000000000020 r .LC4\n@@ -446,50 +471,25 @@\n U pthread_mutex_lock\n U pthread_mutex_unlock\n 00000000000002c0 T rdmacore52_0_iset_alloc_range\n 0000000000000000 T rdmacore52_0_iset_create\n 0000000000000050 T rdmacore52_0_iset_destroy\n 0000000000000090 T rdmacore52_0_iset_insert_range\n \n-rdma_nl.c.o:\n- U __stack_chk_fail\n- U nl_connect\n- U nl_recvmsgs_default\n- U nl_send_auto\n- U nl_send_simple\n- U nl_socket_alloc\n- U nl_socket_disable_auto_ack\n- U nl_socket_disable_msg_peek\n- U nl_socket_free\n- U nl_socket_modify_cb\n- U nl_socket_modify_err_cb\n- U nla_put\n- U nlmsg_alloc_simple\n- U nlmsg_free\n-0000000000000200 T rdmacore52_0_rdmanl_get_chardev\n-0000000000000060 T rdmacore52_0_rdmanl_get_copy_on_fork\n-0000000000000130 T rdmacore52_0_rdmanl_get_devices\n-0000000000000000 D rdmacore52_0_rdmanl_policy\n-0000000000000010 T rdmacore52_0_rdmanl_socket_alloc\n-0000000000000000 t rdmanl_saw_err_cb\n- U strlen\n-\n-mmio.c.o:\n+bitmap.c.o:\n+ U memset\n+0000000000000160 T rdmacore52_0_bitmap_fill_region\n+0000000000000000 T rdmacore52_0_bitmap_find_first_bit\n+0000000000000220 T rdmacore52_0_bitmap_find_free_region\n+0000000000000090 T rdmacore52_0_bitmap_zero_region\n \n-open_cdev.c.o:\n-0000000000000000 r .LC0\n-0000000000000010 r .LC1\n-000000000000001b r .LC2\n- U __asprintf_chk\n- U __stack_chk_fail\n- U close\n- U free\n- U fstat\n- U inotify_add_watch\n- U inotify_init1\n- U open\n-0000000000000000 t open_cdev_robust.isra.0\n- U poll\n-0000000000000380 T rdmacore52_0_open_cdev\n- U read\n- U timerfd_create\n- U timerfd_settime\n+util.c.o:\n+ U fcntl\n+ U getenv\n+ U getrandom\n+ U rand_r\n+00000000000000d0 T rdmacore52_0_check_env\n+0000000000000050 T rdmacore52_0_get_random\n+0000000000000000 T rdmacore52_0_set_fd_nonblock\n+0000000000000110 T rdmacore52_0_xorshift32\n+0000000000000000 b seed.0\n+ U time\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,14 +1,14 @@\n ---------- 0 0 0 2206 1970-01-01 00:00:00.000000 /\n ---------- 0 0 0 0 1970-01-01 00:00:00.000000 //\n-?rw-r--r-- 0 0 0 8696 1970-01-01 00:00:00.000000 query_smp.c.o\n-?rw-r--r-- 0 0 0 16608 1970-01-01 00:00:00.000000 ibnetdisc_cache.c.o\n ?rw-r--r-- 0 0 0 32992 1970-01-01 00:00:00.000000 ibnetdisc.c.o\n ?rw-r--r-- 0 0 0 22800 1970-01-01 00:00:00.000000 chassis.c.o\n-?rw-r--r-- 0 0 0 2504 1970-01-01 00:00:00.000000 bitmap.c.o\n+?rw-r--r-- 0 0 0 8696 1970-01-01 00:00:00.000000 query_smp.c.o\n+?rw-r--r-- 0 0 0 16608 1970-01-01 00:00:00.000000 ibnetdisc_cache.c.o\n+?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 mmio.c.o\n ?rw-r--r-- 0 0 0 6272 1970-01-01 00:00:00.000000 cl_map.c.o\n-?rw-r--r-- 0 0 0 2264 1970-01-01 00:00:00.000000 util.c.o\n-?rw-r--r-- 0 0 0 5472 1970-01-01 00:00:00.000000 node_name_map.c.o\n-?rw-r--r-- 0 0 0 3400 1970-01-01 00:00:00.000000 interval_set.c.o\n ?rw-r--r-- 0 0 0 4472 1970-01-01 00:00:00.000000 rdma_nl.c.o\n-?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 mmio.c.o\n ?rw-r--r-- 0 0 0 3952 1970-01-01 00:00:00.000000 open_cdev.c.o\n+?rw-r--r-- 0 0 0 5472 1970-01-01 00:00:00.000000 node_name_map.c.o\n+?rw-r--r-- 0 0 0 3400 1970-01-01 00:00:00.000000 interval_set.c.o\n+?rw-r--r-- 0 0 0 2504 1970-01-01 00:00:00.000000 bitmap.c.o\n+?rw-r--r-- 0 0 0 2264 1970-01-01 00:00:00.000000 util.c.o\n"}]}]}]}]}, {"source1": "libibverbs-dev_52.0-2_amd64.deb", "source2": "libibverbs-dev_52.0-2_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2024-06-27 11:49:34.000000 debian-binary\n -rw-r--r-- 0 0 0 5684 2024-06-27 11:49:34.000000 control.tar.xz\n--rw-r--r-- 0 0 0 630348 2024-06-27 11:49:34.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 630220 2024-06-27 11:49:34.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/x86_64-linux-gnu/libbnxt_re-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libbnxt_re-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,13 +1,9 @@\n \n Archive index:\n-rdmacore52_0_bnxt_re_free_mem in memory.c.o\n-rdmacore52_0_bnxt_re_alloc_mem in memory.c.o\n-rdmacore52_0_bnxt_re_get_obj in memory.c.o\n-rdmacore52_0_bnxt_re_get_ring in memory.c.o\n rdmacore52_0_bnxt_re_ring_rq_db in db.c.o\n rdmacore52_0_bnxt_re_ring_sq_db in db.c.o\n rdmacore52_0_bnxt_re_ring_srq_db in db.c.o\n rdmacore52_0_bnxt_re_ring_srq_arm in db.c.o\n rdmacore52_0_bnxt_re_ring_cq_db in db.c.o\n rdmacore52_0_bnxt_re_ring_cq_arm_db in db.c.o\n rdmacore52_0_bnxt_re_ring_pstart_db in db.c.o\n@@ -43,26 +39,18 @@\n rdmacore52_0_bnxt_re_create_srq in verbs.c.o\n rdmacore52_0_bnxt_re_modify_srq in verbs.c.o\n rdmacore52_0_bnxt_re_destroy_srq in verbs.c.o\n rdmacore52_0_bnxt_re_query_srq in verbs.c.o\n rdmacore52_0_bnxt_re_post_srq_recv in verbs.c.o\n rdmacore52_0_bnxt_re_create_ah in verbs.c.o\n rdmacore52_0_bnxt_re_destroy_ah in verbs.c.o\n-\n-memory.c.o:\n- U calloc\n- U free\n- U ibv_dofork_range\n- U ibv_dontfork_range\n- U mmap\n- U munmap\n-0000000000000030 T rdmacore52_0_bnxt_re_alloc_mem\n-0000000000000000 T rdmacore52_0_bnxt_re_free_mem\n-00000000000000d0 T rdmacore52_0_bnxt_re_get_obj\n-0000000000000100 T rdmacore52_0_bnxt_re_get_ring\n+rdmacore52_0_bnxt_re_free_mem in memory.c.o\n+rdmacore52_0_bnxt_re_alloc_mem in memory.c.o\n+rdmacore52_0_bnxt_re_get_obj in memory.c.o\n+rdmacore52_0_bnxt_re_get_ring in memory.c.o\n \n db.c.o:\n U __stack_chk_fail\n 0000000000000000 t bnxt_re_do_pacing\n U calloc\n U clock_gettime\n U free\n@@ -212,7 +200,19 @@\n U rdmacore52_0_ibv_cmd_query_device_any\n U rdmacore52_0_ibv_cmd_query_port\n U rdmacore52_0_ibv_cmd_query_qp\n U rdmacore52_0_ibv_cmd_query_srq\n U rdmacore52_0_ibv_cmd_reg_dmabuf_mr\n U rdmacore52_0_ibv_cmd_reg_mr\n U rdmacore52_0_ibv_cmd_resize_cq\n+\n+memory.c.o:\n+ U calloc\n+ U free\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U mmap\n+ U munmap\n+0000000000000030 T rdmacore52_0_bnxt_re_alloc_mem\n+0000000000000000 T rdmacore52_0_bnxt_re_free_mem\n+00000000000000d0 T rdmacore52_0_bnxt_re_get_obj\n+0000000000000100 T rdmacore52_0_bnxt_re_get_ring\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,5 +1,5 @@\n ---------- 0 0 0 1688 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 2176 1970-01-01 00:00:00.000000 memory.c.o\n ?rw-r--r-- 0 0 0 5600 1970-01-01 00:00:00.000000 db.c.o\n ?rw-r--r-- 0 0 0 8632 1970-01-01 00:00:00.000000 main.c.o\n ?rw-r--r-- 0 0 0 28016 1970-01-01 00:00:00.000000 verbs.c.o\n+?rw-r--r-- 0 0 0 2176 1970-01-01 00:00:00.000000 memory.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libcxgb4-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libcxgb4-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,22 +1,29 @@\n \n Archive index:\n-rdmacore52_0_c4iw_copy_wr_to_srq in qp.c.o\n-rdmacore52_0_c4iw_post_send in qp.c.o\n-rdmacore52_0_c4iw_post_srq_recv in qp.c.o\n-rdmacore52_0_c4iw_post_receive in qp.c.o\n-rdmacore52_0_c4iw_flush_qp in qp.c.o\n-rdmacore52_0_c4iw_flush_qps in qp.c.o\n+rdmacore52_0_c4iw_flush_rq in cq.c.o\n+rdmacore52_0_c4iw_flush_sq in cq.c.o\n+rdmacore52_0_c4iw_flush_hw_cq in cq.c.o\n+rdmacore52_0_c4iw_count_rcqes in cq.c.o\n+rdmacore52_0_c4iw_poll_cq in cq.c.o\n+rdmacore52_0_c4iw_arm_cq in cq.c.o\n+rdmacore52_0_c4iw_flush_srqidx in cq.c.o\n rdmacore52_0_c4iw_page_size in dev.c.o\n rdmacore52_0_c4iw_page_shift in dev.c.o\n rdmacore52_0_c4iw_page_mask in dev.c.o\n rdmacore52_0_c4iw_abi_version in dev.c.o\n rdmacore52_0_ma_wr in dev.c.o\n rdmacore52_0_t5_en_wc in dev.c.o\n verbs_provider_cxgb4 in dev.c.o\n+rdmacore52_0_c4iw_copy_wr_to_srq in qp.c.o\n+rdmacore52_0_c4iw_post_send in qp.c.o\n+rdmacore52_0_c4iw_post_srq_recv in qp.c.o\n+rdmacore52_0_c4iw_post_receive in qp.c.o\n+rdmacore52_0_c4iw_flush_qp in qp.c.o\n+rdmacore52_0_c4iw_flush_qps in qp.c.o\n rdmacore52_0_c4iw_query_device in verbs.c.o\n rdmacore52_0_c4iw_query_port in verbs.c.o\n rdmacore52_0_c4iw_alloc_pd in verbs.c.o\n rdmacore52_0_c4iw_free_pd in verbs.c.o\n rdmacore52_0_c4iw_reg_mr in verbs.c.o\n rdmacore52_0_c4iw_dereg_mr in verbs.c.o\n rdmacore52_0_c4iw_create_cq in verbs.c.o\n@@ -29,44 +36,45 @@\n rdmacore52_0_c4iw_create_qp in verbs.c.o\n rdmacore52_0_c4iw_modify_qp in verbs.c.o\n rdmacore52_0_c4iw_destroy_qp in verbs.c.o\n rdmacore52_0_c4iw_query_qp in verbs.c.o\n rdmacore52_0_c4iw_attach_mcast in verbs.c.o\n rdmacore52_0_c4iw_detach_mcast in verbs.c.o\n rdmacore52_0_c4iw_async_event in verbs.c.o\n-rdmacore52_0_c4iw_flush_rq in cq.c.o\n-rdmacore52_0_c4iw_flush_sq in cq.c.o\n-rdmacore52_0_c4iw_flush_hw_cq in cq.c.o\n-rdmacore52_0_c4iw_count_rcqes in cq.c.o\n-rdmacore52_0_c4iw_poll_cq in cq.c.o\n-rdmacore52_0_c4iw_arm_cq in cq.c.o\n-rdmacore52_0_c4iw_flush_srqidx in cq.c.o\n \n-qp.c.o:\n-0000000000000000 r .LC1\n+cq.c.o:\n+0000000000000000 r .LC0\n+000000000000001e r .LC1\n 0000000000000000 r .LC2\n+0000000000000038 r .LC3\n+0000000000000070 r .LC4\n+00000000000000a0 r .LC5\n+00000000000000d8 r .LC6\n+ U __errno_location\n+ U __fprintf_chk\n+0000000000000060 r __func__.0\n+0000000000000070 r __func__.1\n U __stack_chk_fail\n- U memset\n+ U __syslog_chk\n+0000000000000000 t flush_completed_wrs\n U pthread_spin_lock\n U pthread_spin_unlock\n- U rdmacore52_0_c4iw_abi_version\n-0000000000000000 T rdmacore52_0_c4iw_copy_wr_to_srq\n- U rdmacore52_0_c4iw_count_rcqes\n- U rdmacore52_0_c4iw_flush_hw_cq\n-0000000000002190 T rdmacore52_0_c4iw_flush_qp\n-00000000000023f0 T rdmacore52_0_c4iw_flush_qps\n- U rdmacore52_0_c4iw_flush_rq\n- U rdmacore52_0_c4iw_flush_sq\n- U rdmacore52_0_c4iw_flush_srqidx\n-0000000000001b60 T rdmacore52_0_c4iw_post_receive\n-0000000000000080 T rdmacore52_0_c4iw_post_send\n-00000000000015f0 T rdmacore52_0_c4iw_post_srq_recv\n- U rdmacore52_0_ibv_cmd_modify_qp\n- U rdmacore52_0_ma_wr\n+0000000000002370 T rdmacore52_0_c4iw_arm_cq\n+ U rdmacore52_0_c4iw_copy_wr_to_srq\n+0000000000000df0 T rdmacore52_0_c4iw_count_rcqes\n+0000000000000630 T rdmacore52_0_c4iw_flush_hw_cq\n+ U rdmacore52_0_c4iw_flush_qps\n+0000000000000160 T rdmacore52_0_c4iw_flush_rq\n+00000000000002f0 T rdmacore52_0_c4iw_flush_sq\n+0000000000002440 T rdmacore52_0_c4iw_flush_srqidx\n+0000000000000ef0 T rdmacore52_0_c4iw_poll_cq\n+ U rdmacore52_0_ibv_cmd_modify_srq\n+ U rdmacore52_0_is_64b_cqe\n U rdmacore52_0_t5_en_wc\n+ U stderr\n \n dev.c.o:\n 0000000000000000 r .LC0\n 000000000000000c r .LC1\n 0000000000000000 r .LC2\n U __fprintf_chk\n U __stack_chk_fail\n@@ -122,14 +130,37 @@\n U rdmacore52_0_verbs_set_ops\n U rdmacore52_0_verbs_uninit_context\n U stderr\n U strtol\n U sysconf\n 0000000000000000 D verbs_provider_cxgb4\n \n+qp.c.o:\n+0000000000000000 r .LC1\n+0000000000000000 r .LC2\n+ U __stack_chk_fail\n+ U memset\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_c4iw_abi_version\n+0000000000000000 T rdmacore52_0_c4iw_copy_wr_to_srq\n+ U rdmacore52_0_c4iw_count_rcqes\n+ U rdmacore52_0_c4iw_flush_hw_cq\n+0000000000002190 T rdmacore52_0_c4iw_flush_qp\n+00000000000023f0 T rdmacore52_0_c4iw_flush_qps\n+ U rdmacore52_0_c4iw_flush_rq\n+ U rdmacore52_0_c4iw_flush_sq\n+ U rdmacore52_0_c4iw_flush_srqidx\n+0000000000001b60 T rdmacore52_0_c4iw_post_receive\n+0000000000000080 T rdmacore52_0_c4iw_post_send\n+00000000000015f0 T rdmacore52_0_c4iw_post_srq_recv\n+ U rdmacore52_0_ibv_cmd_modify_qp\n+ U rdmacore52_0_ma_wr\n+ U rdmacore52_0_t5_en_wc\n+\n verbs.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n U __errno_location\n U __snprintf_chk\n U __stack_chk_fail\n U calloc\n@@ -181,38 +212,7 @@\n U rdmacore52_0_ibv_cmd_query_port\n U rdmacore52_0_ibv_cmd_query_qp\n U rdmacore52_0_ibv_cmd_query_srq\n U rdmacore52_0_ibv_cmd_reg_mr\n 0000000000000000 B rdmacore52_0_is_64b_cqe\n U rdmacore52_0_ma_wr\n U stderr\n-\n-cq.c.o:\n-0000000000000000 r .LC0\n-000000000000001e r .LC1\n-0000000000000000 r .LC2\n-0000000000000038 r .LC3\n-0000000000000070 r .LC4\n-00000000000000a0 r .LC5\n-00000000000000d8 r .LC6\n- U __errno_location\n- U __fprintf_chk\n-0000000000000060 r __func__.0\n-0000000000000070 r __func__.1\n- U __stack_chk_fail\n- U __syslog_chk\n-0000000000000000 t flush_completed_wrs\n- U pthread_spin_lock\n- U pthread_spin_unlock\n-0000000000002370 T rdmacore52_0_c4iw_arm_cq\n- U rdmacore52_0_c4iw_copy_wr_to_srq\n-0000000000000df0 T rdmacore52_0_c4iw_count_rcqes\n-0000000000000630 T rdmacore52_0_c4iw_flush_hw_cq\n- U rdmacore52_0_c4iw_flush_qps\n-0000000000000160 T rdmacore52_0_c4iw_flush_rq\n-00000000000002f0 T rdmacore52_0_c4iw_flush_sq\n-0000000000002440 T rdmacore52_0_c4iw_flush_srqidx\n-0000000000000ef0 T rdmacore52_0_c4iw_poll_cq\n- U rdmacore52_0_ibv_cmd_modify_srq\n- U rdmacore52_0_is_64b_cqe\n- U rdmacore52_0_t5_en_wc\n- U stderr\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,5 +1,5 @@\n ---------- 0 0 0 1282 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 13928 1970-01-01 00:00:00.000000 qp.c.o\n+?rw-r--r-- 0 0 0 16200 1970-01-01 00:00:00.000000 cq.c.o\n ?rw-r--r-- 0 0 0 12328 1970-01-01 00:00:00.000000 dev.c.o\n+?rw-r--r-- 0 0 0 13928 1970-01-01 00:00:00.000000 qp.c.o\n ?rw-r--r-- 0 0 0 16152 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 16200 1970-01-01 00:00:00.000000 cq.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/liberdma-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/liberdma-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,9 +1,10 @@\n \n Archive index:\n+verbs_provider_erdma in erdma.c.o\n rdmacore52_0_erdma_query_device in erdma_verbs.c.o\n rdmacore52_0_erdma_query_port in erdma_verbs.c.o\n rdmacore52_0_erdma_query_qp in erdma_verbs.c.o\n rdmacore52_0_erdma_alloc_pd in erdma_verbs.c.o\n rdmacore52_0_erdma_free_pd in erdma_verbs.c.o\n rdmacore52_0_erdma_reg_mr in erdma_verbs.c.o\n rdmacore52_0_erdma_dereg_mr in erdma_verbs.c.o\n@@ -16,15 +17,53 @@\n rdmacore52_0_erdma_post_send in erdma_verbs.c.o\n rdmacore52_0_erdma_post_recv in erdma_verbs.c.o\n rdmacore52_0_erdma_cq_event in erdma_verbs.c.o\n rdmacore52_0_erdma_poll_cq in erdma_verbs.c.o\n rdmacore52_0_erdma_free_context in erdma_verbs.c.o\n rdmacore52_0_erdma_alloc_dbrecords in erdma_db.c.o\n rdmacore52_0_erdma_dealloc_dbrecords in erdma_db.c.o\n-verbs_provider_erdma in erdma.c.o\n+\n+erdma.c.o:\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t drv__register_driver\n+0000000000000030 t erdma_alloc_context\n+0000000000000000 d erdma_context_ops\n+0000000000000000 d erdma_dev_ops\n+0000000000000010 t erdma_device_alloc\n+0000000000000000 t erdma_device_free\n+ U free\n+0000000000000000 r match_table\n+ U mmap\n+ U munmap\n+ U pthread_mutex_init\n+ U rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_erdma_alloc_pd\n+ U rdmacore52_0_erdma_cq_event\n+ U rdmacore52_0_erdma_create_cq\n+ U rdmacore52_0_erdma_create_qp\n+ U rdmacore52_0_erdma_dereg_mr\n+ U rdmacore52_0_erdma_destroy_cq\n+ U rdmacore52_0_erdma_destroy_qp\n+ U rdmacore52_0_erdma_free_context\n+ U rdmacore52_0_erdma_free_pd\n+ U rdmacore52_0_erdma_modify_qp\n+ U rdmacore52_0_erdma_notify_cq\n+ U rdmacore52_0_erdma_poll_cq\n+ U rdmacore52_0_erdma_post_recv\n+ U rdmacore52_0_erdma_post_send\n+ U rdmacore52_0_erdma_query_device\n+ U rdmacore52_0_erdma_query_port\n+ U rdmacore52_0_erdma_query_qp\n+ U rdmacore52_0_erdma_reg_mr\n+ U rdmacore52_0_ibv_cmd_get_context\n+ U rdmacore52_0_verbs_register_driver_34\n+ U rdmacore52_0_verbs_set_ops\n+ U rdmacore52_0_verbs_uninit_context\n+0000000000000000 D verbs_provider_erdma\n \n erdma_verbs.c.o:\n 0000000000000000 r .LC0\n U __errno_location\n U __snprintf_chk\n U __stack_chk_fail\n U calloc\n@@ -83,46 +122,7 @@\n U memset\n U posix_memalign\n U pthread_mutex_lock\n U pthread_mutex_unlock\n U rdmacore52_0_bitmap_find_first_bit\n 0000000000000000 T rdmacore52_0_erdma_alloc_dbrecords\n 0000000000000180 T rdmacore52_0_erdma_dealloc_dbrecords\n-\n-erdma.c.o:\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t drv__register_driver\n-0000000000000030 t erdma_alloc_context\n-0000000000000000 d erdma_context_ops\n-0000000000000000 d erdma_dev_ops\n-0000000000000010 t erdma_device_alloc\n-0000000000000000 t erdma_device_free\n- U free\n-0000000000000000 r match_table\n- U mmap\n- U munmap\n- U pthread_mutex_init\n- U rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_erdma_alloc_pd\n- U rdmacore52_0_erdma_cq_event\n- U rdmacore52_0_erdma_create_cq\n- U rdmacore52_0_erdma_create_qp\n- U rdmacore52_0_erdma_dereg_mr\n- U rdmacore52_0_erdma_destroy_cq\n- U rdmacore52_0_erdma_destroy_qp\n- U rdmacore52_0_erdma_free_context\n- U rdmacore52_0_erdma_free_pd\n- U rdmacore52_0_erdma_modify_qp\n- U rdmacore52_0_erdma_notify_cq\n- U rdmacore52_0_erdma_poll_cq\n- U rdmacore52_0_erdma_post_recv\n- U rdmacore52_0_erdma_post_send\n- U rdmacore52_0_erdma_query_device\n- U rdmacore52_0_erdma_query_port\n- U rdmacore52_0_erdma_query_qp\n- U rdmacore52_0_erdma_reg_mr\n- U rdmacore52_0_ibv_cmd_get_context\n- U rdmacore52_0_verbs_register_driver_34\n- U rdmacore52_0_verbs_set_ops\n- U rdmacore52_0_verbs_uninit_context\n-0000000000000000 D verbs_provider_erdma\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,4 +1,4 @@\n ---------- 0 0 0 702 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 6272 1970-01-01 00:00:00.000000 erdma.c.o\n ?rw-r--r-- 0 0 0 14480 1970-01-01 00:00:00.000000 erdma_verbs.c.o\n ?rw-r--r-- 0 0 0 2592 1970-01-01 00:00:00.000000 erdma_db.c.o\n-?rw-r--r-- 0 0 0 6272 1970-01-01 00:00:00.000000 erdma.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libhns.a", "source2": "./usr/lib/x86_64-linux-gnu/libhns.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,19 +1,16 @@\n \n Archive index:\n-rdmacore52_0_is_hns_dev in hns_roce_u.c.o\n-hnsdv_is_supported in hns_roce_u.c.o\n-verbs_provider_hns in hns_roce_u.c.o\n-rdmacore52_0_hns_roce_alloc_db in hns_roce_u_db.c.o\n-rdmacore52_0_hns_roce_free_db in hns_roce_u_db.c.o\n rdmacore52_0_hns_roce_u_v2_post_send in hns_roce_u_hw_v2.c.o\n rdmacore52_0_hns_roce_v2_clear_qp in hns_roce_u_hw_v2.c.o\n rdmacore52_0_hns_roce_attach_cq_ex_ops in hns_roce_u_hw_v2.c.o\n rdmacore52_0_hns_roce_attach_qp_ex_ops in hns_roce_u_hw_v2.c.o\n rdmacore52_0_hns_roce_u_hw_v2 in hns_roce_u_hw_v2.c.o\n+rdmacore52_0_hns_roce_alloc_buf in hns_roce_u_buf.c.o\n+rdmacore52_0_hns_roce_free_buf in hns_roce_u_buf.c.o\n rdmacore52_0_hns_roce_init_qp_indices in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_query_device in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_query_port in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_alloc_pd in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_free_pd in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_open_xrcd in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_close_xrcd in hns_roce_u_verbs.c.o\n@@ -40,87 +37,19 @@\n rdmacore52_0_hns_roce_u_create_qp_ex in hns_roce_u_verbs.c.o\n hnsdv_create_qp in hns_roce_u_verbs.c.o\n hnsdv_query_device in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_open_qp in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_query_qp in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_create_ah in hns_roce_u_verbs.c.o\n rdmacore52_0_hns_roce_u_destroy_ah in hns_roce_u_verbs.c.o\n-rdmacore52_0_hns_roce_alloc_buf in hns_roce_u_buf.c.o\n-rdmacore52_0_hns_roce_free_buf in hns_roce_u_buf.c.o\n-\n-hns_roce_u.c.o:\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t drv__register_driver\n- U free\n-0000000000000260 d hca_table\n-0000000000000000 d hns_common_ops\n-0000000000000010 t hns_device_alloc\n-0000000000000070 t hns_roce_alloc_context\n-0000000000000000 d hns_roce_dev_ops\n-00000000000003d0 t hns_roce_free_context\n-0000000000000000 t hns_uninit_device\n-0000000000000460 T hnsdv_is_supported\n- U mmap\n- U munmap\n- U pthread_mutex_destroy\n- U pthread_mutex_init\n- U pthread_spin_destroy\n- U pthread_spin_init\n- U rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_hns_roce_u_alloc_mw\n- U rdmacore52_0_hns_roce_u_alloc_pd\n- U rdmacore52_0_hns_roce_u_bind_mw\n- U rdmacore52_0_hns_roce_u_close_xrcd\n- U rdmacore52_0_hns_roce_u_cq_event\n- U rdmacore52_0_hns_roce_u_create_ah\n- U rdmacore52_0_hns_roce_u_create_cq\n- U rdmacore52_0_hns_roce_u_create_cq_ex\n- U rdmacore52_0_hns_roce_u_create_qp\n- U rdmacore52_0_hns_roce_u_create_qp_ex\n- U rdmacore52_0_hns_roce_u_create_srq\n- U rdmacore52_0_hns_roce_u_create_srq_ex\n- U rdmacore52_0_hns_roce_u_dealloc_mw\n- U rdmacore52_0_hns_roce_u_dereg_mr\n- U rdmacore52_0_hns_roce_u_destroy_ah\n- U rdmacore52_0_hns_roce_u_destroy_cq\n- U rdmacore52_0_hns_roce_u_destroy_srq\n- U rdmacore52_0_hns_roce_u_free_pd\n- U rdmacore52_0_hns_roce_u_get_srq_num\n- U rdmacore52_0_hns_roce_u_hw_v2\n- U rdmacore52_0_hns_roce_u_modify_cq\n- U rdmacore52_0_hns_roce_u_modify_srq\n- U rdmacore52_0_hns_roce_u_open_qp\n- U rdmacore52_0_hns_roce_u_open_xrcd\n- U rdmacore52_0_hns_roce_u_query_device\n- U rdmacore52_0_hns_roce_u_query_port\n- U rdmacore52_0_hns_roce_u_query_qp\n- U rdmacore52_0_hns_roce_u_query_srq\n- U rdmacore52_0_hns_roce_u_reg_mr\n- U rdmacore52_0_hns_roce_u_rereg_mr\n- U rdmacore52_0_ibv_cmd_get_context\n-0000000000000440 T rdmacore52_0_is_hns_dev\n- U rdmacore52_0_verbs_register_driver_34\n- U rdmacore52_0_verbs_set_ops\n- U rdmacore52_0_verbs_uninit_context\n- U sysconf\n-0000000000000000 D verbs_provider_hns\n-\n-hns_roce_u_db.c.o:\n- U calloc\n-0000000000000000 r db_size\n- U free\n- U memset\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0_bitmap_find_first_bit\n- U rdmacore52_0_hns_roce_alloc_buf\n-0000000000000000 T rdmacore52_0_hns_roce_alloc_db\n- U rdmacore52_0_hns_roce_free_buf\n-00000000000001b0 T rdmacore52_0_hns_roce_free_db\n+rdmacore52_0_is_hns_dev in hns_roce_u.c.o\n+hnsdv_is_supported in hns_roce_u.c.o\n+verbs_provider_hns in hns_roce_u.c.o\n+rdmacore52_0_hns_roce_alloc_db in hns_roce_u_db.c.o\n+rdmacore52_0_hns_roce_free_db in hns_roce_u_db.c.o\n \n hns_roce_u_hw_v2.c.o:\n 0000000000000000 r .LC0\n 0000000000001420 t __hns_roce_v2_cq_clean\n U __stack_chk_fail\n 0000000000000530 t fill_ext_sge_inl_data\n 0000000000000a90 t fill_recv_sge_to_wqe.isra.0\n@@ -191,14 +120,23 @@\n 00000000000003f0 t wr_set_sge_list_ud\n 0000000000000180 t wr_set_sge_rc\n 0000000000000370 t wr_set_sge_ud\n 0000000000001320 t wr_set_ud_addr\n 0000000000000340 t wr_set_xrc_srqn\n 0000000000000780 t wr_start\n \n+hns_roce_u_buf.c.o:\n+ U __errno_location\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U mmap\n+ U munmap\n+0000000000000000 T rdmacore52_0_hns_roce_alloc_buf\n+0000000000000090 T rdmacore52_0_hns_roce_free_buf\n+\n hns_roce_u_verbs.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000028 r .LC2\n 0000000000000050 r .LC4\n 0000000000000080 r .LC5\n U __errno_location\n@@ -288,15 +226,77 @@\n U rdmacore52_0_ibv_cmd_query_qp\n U rdmacore52_0_ibv_cmd_query_srq\n U rdmacore52_0_ibv_cmd_reg_mr\n U rdmacore52_0_ibv_cmd_rereg_mr\n U rdmacore52_0_ibv_query_gid_type\n U rdmacore52_0_is_hns_dev\n \n-hns_roce_u_buf.c.o:\n- U __errno_location\n- U ibv_dofork_range\n- U ibv_dontfork_range\n+hns_roce_u.c.o:\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t drv__register_driver\n+ U free\n+0000000000000260 d hca_table\n+0000000000000000 d hns_common_ops\n+0000000000000010 t hns_device_alloc\n+0000000000000070 t hns_roce_alloc_context\n+0000000000000000 d hns_roce_dev_ops\n+00000000000003d0 t hns_roce_free_context\n+0000000000000000 t hns_uninit_device\n+0000000000000460 T hnsdv_is_supported\n U mmap\n U munmap\n-0000000000000000 T rdmacore52_0_hns_roce_alloc_buf\n-0000000000000090 T rdmacore52_0_hns_roce_free_buf\n+ U pthread_mutex_destroy\n+ U pthread_mutex_init\n+ U pthread_spin_destroy\n+ U pthread_spin_init\n+ U rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_hns_roce_u_alloc_mw\n+ U rdmacore52_0_hns_roce_u_alloc_pd\n+ U rdmacore52_0_hns_roce_u_bind_mw\n+ U rdmacore52_0_hns_roce_u_close_xrcd\n+ U rdmacore52_0_hns_roce_u_cq_event\n+ U rdmacore52_0_hns_roce_u_create_ah\n+ U rdmacore52_0_hns_roce_u_create_cq\n+ U rdmacore52_0_hns_roce_u_create_cq_ex\n+ U rdmacore52_0_hns_roce_u_create_qp\n+ U rdmacore52_0_hns_roce_u_create_qp_ex\n+ U rdmacore52_0_hns_roce_u_create_srq\n+ U rdmacore52_0_hns_roce_u_create_srq_ex\n+ U rdmacore52_0_hns_roce_u_dealloc_mw\n+ U rdmacore52_0_hns_roce_u_dereg_mr\n+ U rdmacore52_0_hns_roce_u_destroy_ah\n+ U rdmacore52_0_hns_roce_u_destroy_cq\n+ U rdmacore52_0_hns_roce_u_destroy_srq\n+ U rdmacore52_0_hns_roce_u_free_pd\n+ U rdmacore52_0_hns_roce_u_get_srq_num\n+ U rdmacore52_0_hns_roce_u_hw_v2\n+ U rdmacore52_0_hns_roce_u_modify_cq\n+ U rdmacore52_0_hns_roce_u_modify_srq\n+ U rdmacore52_0_hns_roce_u_open_qp\n+ U rdmacore52_0_hns_roce_u_open_xrcd\n+ U rdmacore52_0_hns_roce_u_query_device\n+ U rdmacore52_0_hns_roce_u_query_port\n+ U rdmacore52_0_hns_roce_u_query_qp\n+ U rdmacore52_0_hns_roce_u_query_srq\n+ U rdmacore52_0_hns_roce_u_reg_mr\n+ U rdmacore52_0_hns_roce_u_rereg_mr\n+ U rdmacore52_0_ibv_cmd_get_context\n+0000000000000440 T rdmacore52_0_is_hns_dev\n+ U rdmacore52_0_verbs_register_driver_34\n+ U rdmacore52_0_verbs_set_ops\n+ U rdmacore52_0_verbs_uninit_context\n+ U sysconf\n+0000000000000000 D verbs_provider_hns\n+\n+hns_roce_u_db.c.o:\n+ U calloc\n+0000000000000000 r db_size\n+ U free\n+ U memset\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0_bitmap_find_first_bit\n+ U rdmacore52_0_hns_roce_alloc_buf\n+0000000000000000 T rdmacore52_0_hns_roce_alloc_db\n+ U rdmacore52_0_hns_roce_free_buf\n+00000000000001b0 T rdmacore52_0_hns_roce_free_db\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,7 +1,7 @@\n ---------- 0 0 0 1686 1970-01-01 00:00:00.000000 /\n ---------- 0 0 0 0 1970-01-01 00:00:00.000000 //\n-?rw-r--r-- 0 0 0 9088 1970-01-01 00:00:00.000000 hns_roce_u.c.o\n-?rw-r--r-- 0 0 0 2936 1970-01-01 00:00:00.000000 hns_roce_u_db.c.o\n ?rw-r--r-- 0 0 0 33872 1970-01-01 00:00:00.000000 hns_roce_u_hw_v2.c.o\n-?rw-r--r-- 0 0 0 25352 1970-01-01 00:00:00.000000 hns_roce_u_verbs.c.o\n ?rw-r--r-- 0 0 0 1808 1970-01-01 00:00:00.000000 hns_roce_u_buf.c.o\n+?rw-r--r-- 0 0 0 25352 1970-01-01 00:00:00.000000 hns_roce_u_verbs.c.o\n+?rw-r--r-- 0 0 0 9088 1970-01-01 00:00:00.000000 hns_roce_u.c.o\n+?rw-r--r-- 0 0 0 2936 1970-01-01 00:00:00.000000 hns_roce_u_db.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libibverbs.a", "source2": "./usr/lib/x86_64-linux-gnu/libibverbs.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "comments": ["error from `nm -s {}`:", "nm: dynamic_driver.c.o: no symbols", "nm: compat-1_0.c.o: no symbols", "nm: mmio.c.o: no symbols"], "unified_diff": "@@ -4,114 +4,88 @@\n rdmacore52_0__execute_ioctl_fallback in cmd_fallback.c.o\n rdmacore52_0__write_get_req in cmd_fallback.c.o\n rdmacore52_0__write_get_req_ex in cmd_fallback.c.o\n rdmacore52_0__write_get_resp in cmd_fallback.c.o\n rdmacore52_0__write_get_resp_ex in cmd_fallback.c.o\n rdmacore52_0__execute_cmd_write in cmd_fallback.c.o\n rdmacore52_0__execute_cmd_write_ex in cmd_fallback.c.o\n-rdmacore52_0_ibv_cmd_dealloc_pd in cmd_pd.c.o\n-rdmacore52_0_ibv_cmd_create_qp in cmd_qp.c.o\n-rdmacore52_0_ibv_cmd_create_qp_ex in cmd_qp.c.o\n-rdmacore52_0_ibv_cmd_create_qp_ex2 in cmd_qp.c.o\n-rdmacore52_0_ibv_cmd_destroy_qp in cmd_qp.c.o\n-ibv_static_providers in static_driver.c.o\n-verbs_provider_none in static_driver.c.o\n-rdmacore52_0_ibv_cmd_create_cq in cmd_cq.c.o\n-rdmacore52_0_ibv_cmd_create_cq_ex in cmd_cq.c.o\n-rdmacore52_0_ibv_cmd_destroy_cq in cmd_cq.c.o\n ibv_get_sysfs_path in sysfs.c.o\n rdmacore52_0_ibv_read_sysfs_file_at in sysfs.c.o\n ibv_read_sysfs_file in sysfs.c.o\n rdmacore52_0_ibv_read_ibdev_sysfs_file in sysfs.c.o\n-rdmacore52_0_ibv_cmd_close_xrcd in cmd_xrcd.c.o\n-ibv_fork_init in memory.c.o\n-ibv_is_fork_initialized in memory.c.o\n-ibv_dontfork_range in memory.c.o\n-ibv_dofork_range in memory.c.o\n-rdmacore52_0___ioctl_final_num_attrs in cmd_ioctl.c.o\n-rdmacore52_0_execute_ioctl in cmd_ioctl.c.o\n-rdmacore52_0__write_set_uhw in cmd_ioctl.c.o\n-rdmacore52_0_ibv_cmd_create_counters in cmd_counters.c.o\n-rdmacore52_0_ibv_cmd_destroy_counters in cmd_counters.c.o\n-rdmacore52_0_ibv_cmd_read_counters in cmd_counters.c.o\n-rdmacore52_0_ibv_cmd_destroy_rwq_ind_table in cmd_rwq_ind.c.o\n-rdmacore52_0_ibv_cmd_alloc_dm in cmd_dm.c.o\n-rdmacore52_0_ibv_cmd_free_dm in cmd_dm.c.o\n-rdmacore52_0_ibv_cmd_reg_dm_mr in cmd_dm.c.o\n-rdmacore52_0_ibv_cmd_advise_mr in cmd_mr.c.o\n-rdmacore52_0_ibv_cmd_dereg_mr in cmd_mr.c.o\n-rdmacore52_0_ibv_cmd_query_mr in cmd_mr.c.o\n-rdmacore52_0_ibv_cmd_reg_dmabuf_mr in cmd_mr.c.o\n-verbs_provider_all in all_providers.c.o\n-rdmacore52_0_neigh_get_oif_from_src in neigh.c.o\n-rdmacore52_0_neigh_init_resources in neigh.c.o\n-rdmacore52_0_neigh_get_vlan_id_from_dev in neigh.c.o\n-rdmacore52_0_neigh_set_vlan_id in neigh.c.o\n-rdmacore52_0_neigh_set_dst in neigh.c.o\n-rdmacore52_0_neigh_set_src in neigh.c.o\n-rdmacore52_0_neigh_set_oif in neigh.c.o\n-rdmacore52_0_neigh_get_ll in neigh.c.o\n-rdmacore52_0_neigh_free_resources in neigh.c.o\n-rdmacore52_0_process_get_neigh in neigh.c.o\n-ibv_get_device_list in device.c.o\n-ibv_free_device_list in device.c.o\n-ibv_get_device_name in device.c.o\n-ibv_get_device_guid in device.c.o\n-ibv_get_device_index in device.c.o\n-rdmacore52_0_verbs_init_cq in device.c.o\n-rdmacore52_0_verbs_init_context in device.c.o\n-rdmacore52_0__verbs_init_and_alloc_context in device.c.o\n-rdmacore52_0_verbs_open_device in device.c.o\n-ibv_open_device in device.c.o\n-ibv_import_device in device.c.o\n-rdmacore52_0_verbs_uninit_context in device.c.o\n-ibv_close_device in device.c.o\n-ibv_get_async_event in device.c.o\n-ibv_ack_async_event in device.c.o\n-rdmacore52_0_find_sysfs_devs_nl in ibdev_nl.c.o\n-rdmacore52_0_get_copy_on_fork in ibdev_nl.c.o\n-rdmacore52_0_verbs_set_ops in dummy_ops.c.o\n-rdmacore52_0_verbs_dummy_ops in dummy_ops.c.o\n-rdmacore52_0_ibv_cmd_query_port in cmd_device.c.o\n-rdmacore52_0_ibv_cmd_alloc_async_fd in cmd_device.c.o\n-rdmacore52_0_ibv_cmd_get_context in cmd_device.c.o\n-rdmacore52_0_ibv_cmd_query_context in cmd_device.c.o\n-rdmacore52_0___ibv_query_gid_ex in cmd_device.c.o\n-_ibv_query_gid_ex in cmd_device.c.o\n-_ibv_query_gid_table in cmd_device.c.o\n-rdmacore52_0_ibv_cmd_query_device_any in cmd_device.c.o\n-ibv_copy_ah_attr_from_kern in marshall.c.o\n-ibv_copy_qp_attr_from_kern in marshall.c.o\n-ibv_copy_path_rec_from_kern in marshall.c.o\n-ibv_copy_path_rec_to_kern in marshall.c.o\n+rdmacore52_0_ibv_cmd_destroy_ah in cmd_ah.c.o\n+ibv_node_type_str in enum_strs.c.o\n+ibv_port_state_str in enum_strs.c.o\n+ibv_event_type_str in enum_strs.c.o\n+ibv_wc_status_str in enum_strs.c.o\n+rdmacore52_0_ibv_wr_opcode_str in enum_strs.c.o\n+rdmacore52_0_ibv_cmd_create_srq in cmd_srq.c.o\n+rdmacore52_0_ibv_cmd_create_srq_ex in cmd_srq.c.o\n+rdmacore52_0_ibv_cmd_destroy_srq in cmd_srq.c.o\n rdmacore52_0___verbs_log in init.c.o\n rdmacore52_0_try_access_device in init.c.o\n rdmacore52_0_decode_knode_type in init.c.o\n rdmacore52_0_setup_sysfs_uverbs in init.c.o\n rdmacore52_0_verbs_register_driver_34 in init.c.o\n rdmacore52_0_ibverbs_get_device_list in init.c.o\n rdmacore52_0_abi_ver in init.c.o\n rdmacore52_0_ibverbs_init in init.c.o\n rdmacore52_0_ibverbs_device_hold in init.c.o\n rdmacore52_0_ibverbs_device_put in init.c.o\n+rdmacore52_0_ibv_cmd_alloc_pd in cmd.c.o\n+rdmacore52_0_ibv_cmd_open_xrcd in cmd.c.o\n+rdmacore52_0_ibv_cmd_reg_mr in cmd.c.o\n+rdmacore52_0_ibv_cmd_rereg_mr in cmd.c.o\n+rdmacore52_0_ibv_cmd_alloc_mw in cmd.c.o\n+rdmacore52_0_ibv_cmd_poll_cq in cmd.c.o\n+rdmacore52_0_ibv_cmd_req_notify_cq in cmd.c.o\n+rdmacore52_0_ibv_cmd_resize_cq in cmd.c.o\n+rdmacore52_0_ibv_cmd_modify_srq in cmd.c.o\n+rdmacore52_0_ibv_cmd_query_srq in cmd.c.o\n+rdmacore52_0_ibv_cmd_open_qp in cmd.c.o\n+rdmacore52_0_ibv_cmd_query_qp in cmd.c.o\n+rdmacore52_0_ibv_cmd_modify_qp in cmd.c.o\n+rdmacore52_0_ibv_cmd_modify_qp_ex in cmd.c.o\n+rdmacore52_0_ibv_cmd_post_send in cmd.c.o\n+rdmacore52_0_ibv_cmd_post_recv in cmd.c.o\n+rdmacore52_0_ibv_cmd_post_srq_recv in cmd.c.o\n+rdmacore52_0_ibv_cmd_create_ah in cmd.c.o\n+rdmacore52_0_ibv_cmd_attach_mcast in cmd.c.o\n+rdmacore52_0_ibv_cmd_detach_mcast in cmd.c.o\n+rdmacore52_0_verbs_allow_disassociate_destroy in cmd.c.o\n+rdmacore52_0_ibv_cmd_create_flow in cmd.c.o\n+rdmacore52_0_ibv_cmd_modify_wq in cmd.c.o\n+rdmacore52_0_ibv_cmd_create_rwq_ind_table in cmd.c.o\n+rdmacore52_0_ibv_cmd_modify_cq in cmd.c.o\n+rdmacore52_0_ibv_cmd_destroy_flow in cmd_flow.c.o\n+rdmacore52_0_ibv_cmd_create_counters in cmd_counters.c.o\n+rdmacore52_0_ibv_cmd_destroy_counters in cmd_counters.c.o\n+rdmacore52_0_ibv_cmd_read_counters in cmd_counters.c.o\n+rdmacore52_0_ibv_cmd_close_xrcd in cmd_xrcd.c.o\n+rdmacore52_0___ioctl_final_num_attrs in cmd_ioctl.c.o\n+rdmacore52_0_execute_ioctl in cmd_ioctl.c.o\n+rdmacore52_0__write_set_uhw in cmd_ioctl.c.o\n+rdmacore52_0_ibv_cmd_create_cq in cmd_cq.c.o\n+rdmacore52_0_ibv_cmd_create_cq_ex in cmd_cq.c.o\n+rdmacore52_0_ibv_cmd_destroy_cq in cmd_cq.c.o\n rdmacore52_0_ibv_cmd_create_wq in cmd_wq.c.o\n rdmacore52_0_ibv_cmd_destroy_wq in cmd_wq.c.o\n rdmacore52_0_ibv_cmd_create_flow_action_esp in cmd_flow_action.c.o\n rdmacore52_0_ibv_cmd_modify_flow_action_esp in cmd_flow_action.c.o\n rdmacore52_0_ibv_cmd_destroy_flow_action in cmd_flow_action.c.o\n-rdmacore52_0_ibv_cmd_dealloc_mw in cmd_mw.c.o\n-rdmacore52_0_ibv_cmd_create_srq in cmd_srq.c.o\n-rdmacore52_0_ibv_cmd_create_srq_ex in cmd_srq.c.o\n-rdmacore52_0_ibv_cmd_destroy_srq in cmd_srq.c.o\n-ibv_node_type_str in enum_strs.c.o\n-ibv_port_state_str in enum_strs.c.o\n-ibv_event_type_str in enum_strs.c.o\n-ibv_wc_status_str in enum_strs.c.o\n-rdmacore52_0_ibv_wr_opcode_str in enum_strs.c.o\n-rdmacore52_0_ibv_cmd_destroy_flow in cmd_flow.c.o\n+rdmacore52_0_ibv_cmd_query_port in cmd_device.c.o\n+rdmacore52_0_ibv_cmd_alloc_async_fd in cmd_device.c.o\n+rdmacore52_0_ibv_cmd_get_context in cmd_device.c.o\n+rdmacore52_0_ibv_cmd_query_context in cmd_device.c.o\n+rdmacore52_0___ibv_query_gid_ex in cmd_device.c.o\n+_ibv_query_gid_ex in cmd_device.c.o\n+_ibv_query_gid_table in cmd_device.c.o\n+rdmacore52_0_ibv_cmd_query_device_any in cmd_device.c.o\n+rdmacore52_0_find_sysfs_devs_nl in ibdev_nl.c.o\n+rdmacore52_0_get_copy_on_fork in ibdev_nl.c.o\n ibv_rate_to_mult in verbs.c.o\n mult_to_ibv_rate in verbs.c.o\n ibv_rate_to_mbps in verbs.c.o\n mbps_to_ibv_rate in verbs.c.o\n ibv_query_device in verbs.c.o\n rdmacore52_0___lib_query_port in verbs.c.o\n ibv_query_port in verbs.c.o\n@@ -155,71 +129,97 @@\n ibv_create_ah_from_wc in verbs.c.o\n ibv_destroy_ah in verbs.c.o\n ibv_attach_mcast in verbs.c.o\n ibv_detach_mcast in verbs.c.o\n ibv_resolve_eth_l2_from_gid in verbs.c.o\n ibv_set_ece in verbs.c.o\n ibv_query_ece in verbs.c.o\n-rdmacore52_0_ibv_cmd_alloc_pd in cmd.c.o\n-rdmacore52_0_ibv_cmd_open_xrcd in cmd.c.o\n-rdmacore52_0_ibv_cmd_reg_mr in cmd.c.o\n-rdmacore52_0_ibv_cmd_rereg_mr in cmd.c.o\n-rdmacore52_0_ibv_cmd_alloc_mw in cmd.c.o\n-rdmacore52_0_ibv_cmd_poll_cq in cmd.c.o\n-rdmacore52_0_ibv_cmd_req_notify_cq in cmd.c.o\n-rdmacore52_0_ibv_cmd_resize_cq in cmd.c.o\n-rdmacore52_0_ibv_cmd_modify_srq in cmd.c.o\n-rdmacore52_0_ibv_cmd_query_srq in cmd.c.o\n-rdmacore52_0_ibv_cmd_open_qp in cmd.c.o\n-rdmacore52_0_ibv_cmd_query_qp in cmd.c.o\n-rdmacore52_0_ibv_cmd_modify_qp in cmd.c.o\n-rdmacore52_0_ibv_cmd_modify_qp_ex in cmd.c.o\n-rdmacore52_0_ibv_cmd_post_send in cmd.c.o\n-rdmacore52_0_ibv_cmd_post_recv in cmd.c.o\n-rdmacore52_0_ibv_cmd_post_srq_recv in cmd.c.o\n-rdmacore52_0_ibv_cmd_create_ah in cmd.c.o\n-rdmacore52_0_ibv_cmd_attach_mcast in cmd.c.o\n-rdmacore52_0_ibv_cmd_detach_mcast in cmd.c.o\n-rdmacore52_0_verbs_allow_disassociate_destroy in cmd.c.o\n-rdmacore52_0_ibv_cmd_create_flow in cmd.c.o\n-rdmacore52_0_ibv_cmd_modify_wq in cmd.c.o\n-rdmacore52_0_ibv_cmd_create_rwq_ind_table in cmd.c.o\n-rdmacore52_0_ibv_cmd_modify_cq in cmd.c.o\n-rdmacore52_0_ibv_cmd_destroy_ah in cmd_ah.c.o\n-rdmacore52_0_bitmap_find_first_bit in bitmap.c.o\n-rdmacore52_0_bitmap_zero_region in bitmap.c.o\n-rdmacore52_0_bitmap_fill_region in bitmap.c.o\n-rdmacore52_0_bitmap_find_free_region in bitmap.c.o\n+rdmacore52_0_ibv_cmd_dealloc_mw in cmd_mw.c.o\n+ibv_fork_init in memory.c.o\n+ibv_is_fork_initialized in memory.c.o\n+ibv_dontfork_range in memory.c.o\n+ibv_dofork_range in memory.c.o\n+ibv_copy_ah_attr_from_kern in marshall.c.o\n+ibv_copy_qp_attr_from_kern in marshall.c.o\n+ibv_copy_path_rec_from_kern in marshall.c.o\n+ibv_copy_path_rec_to_kern in marshall.c.o\n+rdmacore52_0_ibv_cmd_dealloc_pd in cmd_pd.c.o\n+rdmacore52_0_verbs_set_ops in dummy_ops.c.o\n+rdmacore52_0_verbs_dummy_ops in dummy_ops.c.o\n+ibv_get_device_list in device.c.o\n+ibv_free_device_list in device.c.o\n+ibv_get_device_name in device.c.o\n+ibv_get_device_guid in device.c.o\n+ibv_get_device_index in device.c.o\n+rdmacore52_0_verbs_init_cq in device.c.o\n+rdmacore52_0_verbs_init_context in device.c.o\n+rdmacore52_0__verbs_init_and_alloc_context in device.c.o\n+rdmacore52_0_verbs_open_device in device.c.o\n+ibv_open_device in device.c.o\n+ibv_import_device in device.c.o\n+rdmacore52_0_verbs_uninit_context in device.c.o\n+ibv_close_device in device.c.o\n+ibv_get_async_event in device.c.o\n+ibv_ack_async_event in device.c.o\n+rdmacore52_0_ibv_cmd_create_qp in cmd_qp.c.o\n+rdmacore52_0_ibv_cmd_create_qp_ex in cmd_qp.c.o\n+rdmacore52_0_ibv_cmd_create_qp_ex2 in cmd_qp.c.o\n+rdmacore52_0_ibv_cmd_destroy_qp in cmd_qp.c.o\n+rdmacore52_0_ibv_cmd_destroy_rwq_ind_table in cmd_rwq_ind.c.o\n+verbs_provider_all in all_providers.c.o\n+rdmacore52_0_ibv_cmd_advise_mr in cmd_mr.c.o\n+rdmacore52_0_ibv_cmd_dereg_mr in cmd_mr.c.o\n+rdmacore52_0_ibv_cmd_query_mr in cmd_mr.c.o\n+rdmacore52_0_ibv_cmd_reg_dmabuf_mr in cmd_mr.c.o\n+rdmacore52_0_ibv_cmd_alloc_dm in cmd_dm.c.o\n+rdmacore52_0_ibv_cmd_free_dm in cmd_dm.c.o\n+rdmacore52_0_ibv_cmd_reg_dm_mr in cmd_dm.c.o\n+rdmacore52_0_neigh_get_oif_from_src in neigh.c.o\n+rdmacore52_0_neigh_init_resources in neigh.c.o\n+rdmacore52_0_neigh_get_vlan_id_from_dev in neigh.c.o\n+rdmacore52_0_neigh_set_vlan_id in neigh.c.o\n+rdmacore52_0_neigh_set_dst in neigh.c.o\n+rdmacore52_0_neigh_set_src in neigh.c.o\n+rdmacore52_0_neigh_set_oif in neigh.c.o\n+rdmacore52_0_neigh_get_ll in neigh.c.o\n+rdmacore52_0_neigh_free_resources in neigh.c.o\n+rdmacore52_0_process_get_neigh in neigh.c.o\n+ibv_static_providers in static_driver.c.o\n+verbs_provider_none in static_driver.c.o\n rdmacore52_0_cl_qmap_init in cl_map.c.o\n rdmacore52_0_cl_qmap_get in cl_map.c.o\n rdmacore52_0_cl_qmap_get_next in cl_map.c.o\n rdmacore52_0_cl_qmap_apply_func in cl_map.c.o\n rdmacore52_0_cl_qmap_insert in cl_map.c.o\n rdmacore52_0_cl_qmap_remove_item in cl_map.c.o\n rdmacore52_0_cl_qmap_remove in cl_map.c.o\n rdmacore52_0_cl_qmap_merge in cl_map.c.o\n rdmacore52_0_cl_qmap_delta in cl_map.c.o\n-rdmacore52_0_set_fd_nonblock in util.c.o\n-rdmacore52_0_get_random in util.c.o\n-rdmacore52_0_check_env in util.c.o\n-rdmacore52_0_xorshift32 in util.c.o\n+rdmacore52_0_rdmanl_socket_alloc in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_copy_on_fork in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_devices in rdma_nl.c.o\n+rdmacore52_0_rdmanl_get_chardev in rdma_nl.c.o\n+rdmacore52_0_rdmanl_policy in rdma_nl.c.o\n+rdmacore52_0_open_cdev in open_cdev.c.o\n rdmacore52_0_close_node_name_map in node_name_map.c.o\n rdmacore52_0_remap_node_name in node_name_map.c.o\n rdmacore52_0_clean_nodedesc in node_name_map.c.o\n rdmacore52_0_open_node_name_map in node_name_map.c.o\n rdmacore52_0_iset_create in interval_set.c.o\n rdmacore52_0_iset_destroy in interval_set.c.o\n rdmacore52_0_iset_insert_range in interval_set.c.o\n rdmacore52_0_iset_alloc_range in interval_set.c.o\n-rdmacore52_0_rdmanl_socket_alloc in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_copy_on_fork in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_devices in rdma_nl.c.o\n-rdmacore52_0_rdmanl_get_chardev in rdma_nl.c.o\n-rdmacore52_0_rdmanl_policy in rdma_nl.c.o\n-rdmacore52_0_open_cdev in open_cdev.c.o\n+rdmacore52_0_bitmap_find_first_bit in bitmap.c.o\n+rdmacore52_0_bitmap_zero_region in bitmap.c.o\n+rdmacore52_0_bitmap_fill_region in bitmap.c.o\n+rdmacore52_0_bitmap_find_free_region in bitmap.c.o\n+rdmacore52_0_set_fd_nonblock in util.c.o\n+rdmacore52_0_get_random in util.c.o\n+rdmacore52_0_check_env in util.c.o\n+rdmacore52_0_xorshift32 in util.c.o\n \n cmd_fallback.c.o:\n U __errno_location\n U __stack_chk_fail\n 0000000000000000 t ioctl_write\n U memcpy\n U memset\n@@ -230,70 +230,14 @@\n 0000000000000580 T rdmacore52_0__write_get_req\n 00000000000005d0 T rdmacore52_0__write_get_req_ex\n 0000000000000610 T rdmacore52_0__write_get_resp\n 0000000000000650 T rdmacore52_0__write_get_resp_ex\n U rdmacore52_0_execute_ioctl\n U write\n \n-cmd_pd.c.o:\n- U __stack_chk_fail\n- U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_dealloc_pd\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-cmd_qp.c.o:\n- U __errno_location\n- U __stack_chk_fail\n-0000000000000000 t ibv_icmd_create_qp\n- U pthread_cond_init\n- U pthread_cond_wait\n- U pthread_mutex_init\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0___ioctl_final_num_attrs\n- U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_cmd_write_ex\n- U rdmacore52_0__execute_ioctl_fallback\n- U rdmacore52_0__write_get_req\n- U rdmacore52_0__write_get_req_ex\n- U rdmacore52_0__write_get_resp\n- U rdmacore52_0__write_get_resp_ex\n- U rdmacore52_0__write_set_uhw\n- U rdmacore52_0_abi_ver\n-0000000000000c10 T rdmacore52_0_ibv_cmd_create_qp\n-0000000000000d80 T rdmacore52_0_ibv_cmd_create_qp_ex\n-0000000000000e80 T rdmacore52_0_ibv_cmd_create_qp_ex2\n-0000000000000f80 T rdmacore52_0_ibv_cmd_destroy_qp\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-static_driver.c.o:\n-0000000000000000 T ibv_static_providers\n-0000000000000000 R verbs_provider_none\n-\n-cmd_cq.c.o:\n- U __stack_chk_fail\n-0000000000000000 t ibv_icmd_create_cq\n- U pthread_cond_wait\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0___ioctl_final_num_attrs\n- U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_cmd_write_ex\n- U rdmacore52_0__execute_ioctl_fallback\n- U rdmacore52_0__write_get_req\n- U rdmacore52_0__write_get_req_ex\n- U rdmacore52_0__write_get_resp\n- U rdmacore52_0__write_get_resp_ex\n- U rdmacore52_0__write_set_uhw\n-0000000000000510 T rdmacore52_0_ibv_cmd_create_cq\n-0000000000000610 T rdmacore52_0_ibv_cmd_create_cq_ex\n-0000000000000730 T rdmacore52_0_ibv_cmd_destroy_cq\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n sysfs.c.o:\n 0000000000000000 r .LC0\n 0000000000000005 r .LC1\n 0000000000000010 r .LC2\n U __asprintf_chk\n U __errno_location\n U __stack_chk_fail\n@@ -309,437 +253,56 @@\n 0000000000000240 T rdmacore52_0_ibv_read_ibdev_sysfs_file\n 00000000000000c0 T rdmacore52_0_ibv_read_sysfs_file_at\n U read\n U strlen\n U strndup\n 0000000000000000 b sysfs_path\n \n-dynamic_driver.c.o:\n-\n-cmd_xrcd.c.o:\n+cmd_ah.c.o:\n U __stack_chk_fail\n U rdmacore52_0__execute_cmd_write\n U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_close_xrcd\n+0000000000000000 T rdmacore52_0_ibv_cmd_destroy_ah\n U rdmacore52_0_verbs_allow_disassociate_destroy\n \n-memory.c.o:\n+enum_strs.c.o:\n 0000000000000000 r .LC0\n-000000000000000f r .LC1\n-0000000000000012 r .LC2\n-000000000000001a r .LC3\n-000000000000002a r .LC4\n-0000000000000032 r .LC7\n-0000000000000000 r .LC8\n- U __errno_location\n- U __isoc99_sscanf\n-0000000000000000 t __mm_remove\n- U __snprintf_chk\n- U __stack_chk_fail\n- U fclose\n- U fgets\n- U fopen\n- U free\n-00000000000005a0 t get_page_size\n- U getenv\n- U getpid\n-0000000000000004 b huge_page_enabled\n-00000000000011b0 T ibv_dofork_range\n-0000000000001170 T ibv_dontfork_range\n-0000000000000fc0 T ibv_fork_init\n-0000000000001140 T ibv_is_fork_initialized\n-0000000000000a50 t ibv_madvise_range.part.0\n-000000000000000a t ibv_madvise_range.part.0.cold\n- U madvise\n- U malloc\n-0000000000000020 b mm_mutex\n-0000000000000048 b mm_root\n-0000000000000008 b page_size\n- U posix_memalign\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0_get_copy_on_fork\n-0000000000000710 t split_range\n-0000000000000000 t split_range.cold\n- U strstr\n- U sysconf\n-0000000000000000 b too_late\n-\n-cmd_ioctl.c.o:\n- U __errno_location\n- U __stack_chk_fail\n- U ioctl\n-0000000000000000 T rdmacore52_0___ioctl_final_num_attrs\n-0000000000000370 T rdmacore52_0__write_set_uhw\n-0000000000000040 T rdmacore52_0_execute_ioctl\n-\n-compat-1_0.c.o:\n-\n-cmd_counters.c.o:\n- U __stack_chk_fail\n- U rdmacore52_0___ioctl_final_num_attrs\n- U rdmacore52_0_execute_ioctl\n-0000000000000000 T rdmacore52_0_ibv_cmd_create_counters\n-0000000000000190 T rdmacore52_0_ibv_cmd_destroy_counters\n-0000000000000240 T rdmacore52_0_ibv_cmd_read_counters\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-cmd_rwq_ind.c.o:\n- U __stack_chk_fail\n- U rdmacore52_0__execute_cmd_write_ex\n- U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_destroy_rwq_ind_table\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-cmd_dm.c.o:\n- U __errno_location\n- U __stack_chk_fail\n- U rdmacore52_0___ioctl_final_num_attrs\n- U rdmacore52_0_execute_ioctl\n-0000000000000000 T rdmacore52_0_ibv_cmd_alloc_dm\n-00000000000001e0 T rdmacore52_0_ibv_cmd_free_dm\n-0000000000000290 T rdmacore52_0_ibv_cmd_reg_dm_mr\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-cmd_mr.c.o:\n-0000000000000000 r .LC5\n- U __errno_location\n- U __stack_chk_fail\n- U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_ioctl_fallback\n- U rdmacore52_0_execute_ioctl\n-0000000000000000 T rdmacore52_0_ibv_cmd_advise_mr\n-0000000000000130 T rdmacore52_0_ibv_cmd_dereg_mr\n-0000000000000230 T rdmacore52_0_ibv_cmd_query_mr\n-0000000000000360 T rdmacore52_0_ibv_cmd_reg_dmabuf_mr\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-all_providers.c.o:\n-0000000000000000 d all_providers\n-0000000000000000 D verbs_provider_all\n- U verbs_provider_bnxt_re\n- U verbs_provider_cxgb4\n- U verbs_provider_efa\n- U verbs_provider_erdma\n- U verbs_provider_hfi1verbs\n- U verbs_provider_hns\n- U verbs_provider_ipathverbs\n- U verbs_provider_irdma\n- U verbs_provider_mana\n- U verbs_provider_mlx4\n- U verbs_provider_mlx5\n- U verbs_provider_mthca\n- U verbs_provider_ocrdma\n- U verbs_provider_qedr\n- U verbs_provider_rxe\n- U verbs_provider_siw\n- U verbs_provider_vmw_pvrdma\n-\n-neigh.c.o:\n- U __errno_location\n- U __fdelt_chk\n- U __stack_chk_fail\n- U bind\n- U close\n-0000000000000000 d encoded_prefixes\n- U freeaddrinfo\n- U freeifaddrs\n-0000000000000110 t get_link_local_mac_ipv6\n-0000000000000080 t get_mcast_mac_ipv4\n-0000000000000000 t get_mcast_mac_ipv6\n-00000000000001b0 t get_neigh_cb\n-00000000000001e0 t get_neigh_cb_event\n-0000000000000670 t get_route_cb\n-0000000000000240 t get_route_cb_parser\n- U getifaddrs\n- U if_nametoindex\n- U memcmp\n- U memcpy\n- U nl_addr_build\n- U nl_addr_clone\n- U nl_addr_fill_sockaddr\n- U nl_addr_get_binary_addr\n- U nl_addr_get_family\n- U nl_addr_get_len\n- U nl_addr_get_prefixlen\n- U nl_addr_info\n- U nl_addr_put\n- U nl_addr_set_prefixlen\n- U nl_cache_free\n- U nl_cache_mngt_provide\n- U nl_cache_mngt_unprovide\n- U nl_cache_refill\n- U nl_connect\n- U nl_msg_parse\n- U nl_object_match_filter\n- U nl_recvmsgs_default\n- U nl_send_auto\n- U nl_socket_add_membership\n- U nl_socket_alloc\n- U nl_socket_disable_seq_check\n- U nl_socket_free\n- U nl_socket_get_fd\n- U nl_socket_modify_cb\n- U nla_put\n- U nlmsg_alloc_simple\n- U nlmsg_append\n- U nlmsg_free\n-00000000000010d0 T rdmacore52_0_neigh_free_resources\n-0000000000001070 T rdmacore52_0_neigh_get_ll\n-0000000000000d00 T rdmacore52_0_neigh_get_oif_from_src\n-0000000000000f70 T rdmacore52_0_neigh_get_vlan_id_from_dev\n-0000000000000e20 T rdmacore52_0_neigh_init_resources\n-0000000000001000 T rdmacore52_0_neigh_set_dst\n-0000000000001060 T rdmacore52_0_neigh_set_oif\n-0000000000001030 T rdmacore52_0_neigh_set_src\n-0000000000000fe0 T rdmacore52_0_neigh_set_vlan_id\n-00000000000011b0 T rdmacore52_0_process_get_neigh\n- U read\n- U rtnl_link_alloc_cache\n- U rtnl_link_get\n- U rtnl_link_get_addr\n- U rtnl_link_is_vlan\n- U rtnl_link_put\n- U rtnl_link_vlan_get_id\n- U rtnl_neigh_alloc\n- U rtnl_neigh_alloc_cache\n- U rtnl_neigh_get\n- U rtnl_neigh_get_lladdr\n- U rtnl_neigh_put\n- U rtnl_neigh_set_dst\n- U rtnl_neigh_set_ifindex\n- U rtnl_route_alloc_cache\n- U rtnl_route_get_pref_src\n- U rtnl_route_get_type\n- U rtnl_route_nexthop_n\n- U rtnl_route_nh_get_gateway\n- U rtnl_route_nh_get_ifindex\n- U select\n- U sendto\n- U socket\n- U timerfd_create\n- U timerfd_settime\n+0000000000000140 d event_type_str.2\n+0000000000000050 T ibv_event_type_str\n+0000000000000000 T ibv_node_type_str\n+0000000000000030 T ibv_port_state_str\n+0000000000000070 T ibv_wc_status_str\n+0000000000000220 d node_type_str.4\n+00000000000001e0 d port_state_str.3\n+0000000000000090 T rdmacore52_0_ibv_wr_opcode_str\n+0000000000000080 d wc_status_str.1\n+0000000000000000 d wr_opcode_str.0\n \n-device.c.o:\n-0000000000000000 r .LC0\n-000000000000000a r .LC1\n- U _GLOBAL_OFFSET_TABLE_\n+cmd_srq.c.o:\n U __errno_location\n- U __isoc23_sscanf\n-0000000000000000 t __lib_ibv_create_cq_ex\n U __stack_chk_fail\n- U calloc\n- U close\n-0000000000000020 b dev_list_lock\n-0000000000000000 d device_list\n- U free\n- U fstat\n-0000000000000d00 T ibv_ack_async_event\n-0000000000000c30 T ibv_close_device\n-00000000000001e0 T ibv_free_device_list\n-0000000000000c50 T ibv_get_async_event\n-0000000000000230 T ibv_get_device_guid\n-0000000000000360 T ibv_get_device_index\n-00000000000000d0 T ibv_get_device_list\n-0000000000000220 T ibv_get_device_name\n-00000000000009c0 T ibv_import_device\n-00000000000008b0 T ibv_open_device\n- U ibv_query_device\n- U ibv_query_port\n-0000000000000000 b initialized.0\n+0000000000000000 t ibv_icmd_create_srq\n U pthread_cond_init\n- U pthread_cond_signal\n+ U pthread_cond_wait\n U pthread_mutex_init\n U pthread_mutex_lock\n U pthread_mutex_unlock\n- U rdmacore52_0___lib_query_port\n-00000000000005a0 T rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_execute_ioctl\n- U rdmacore52_0_ibv_cmd_alloc_async_fd\n- U rdmacore52_0_ibv_read_ibdev_sysfs_file\n- U rdmacore52_0_ibverbs_device_hold\n- U rdmacore52_0_ibverbs_device_put\n- U rdmacore52_0_ibverbs_get_device_list\n- U rdmacore52_0_ibverbs_init\n- U rdmacore52_0_open_cdev\n- U rdmacore52_0_verbs_dummy_ops\n-00000000000003e0 T rdmacore52_0_verbs_init_context\n-0000000000000380 T rdmacore52_0_verbs_init_cq\n-00000000000007a0 T rdmacore52_0_verbs_open_device\n- U rdmacore52_0_verbs_set_ops\n-0000000000000be0 T rdmacore52_0_verbs_uninit_context\n- U read\n-\n-ibdev_nl.c.o:\n-0000000000000000 r .LC0\n-0000000000000003 r .LC1\n-000000000000001a r .LC2\n-0000000000000021 r .LC3\n- U __snprintf_chk\n- U __stack_chk_fail\n- U calloc\n- U close\n- U closedir\n- U dirfd\n-0000000000000090 t find_sysfs_devs_nl_cb\n-0000000000000250 t find_uverbs_nl_cb\n- U free\n-0000000000000000 t get_copy_on_fork_cb\n- U ibv_get_sysfs_path\n- U nl_socket_free\n- U nla_get_string\n- U nla_get_u32\n- U nla_get_u64\n- U nla_get_u8\n- U nlmsg_hdr\n- U nlmsg_parse\n- U openat\n- U opendir\n- U rdmacore52_0_abi_ver\n- U rdmacore52_0_decode_knode_type\n-0000000000000370 T rdmacore52_0_find_sysfs_devs_nl\n-00000000000005b0 T rdmacore52_0_get_copy_on_fork\n- U rdmacore52_0_rdmanl_get_chardev\n- U rdmacore52_0_rdmanl_get_copy_on_fork\n- U rdmacore52_0_rdmanl_get_devices\n- U rdmacore52_0_rdmanl_policy\n- U rdmacore52_0_rdmanl_socket_alloc\n- U rdmacore52_0_setup_sysfs_uverbs\n- U rdmacore52_0_try_access_device\n- U readdir\n- U snprintf\n-\n-dummy_ops.c.o:\n- U __errno_location\n-0000000000000000 t advise_mr\n-00000000000001d0 t alloc_dm\n-00000000000001b0 t alloc_mw\n-0000000000000190 t alloc_null_mr\n-0000000000000450 t alloc_parent_domain\n-0000000000000650 t alloc_pd\n-0000000000000470 t alloc_td\n-0000000000000010 t async_event\n-0000000000000020 t attach_counters_point_flow\n-0000000000000030 t attach_mcast\n-00000000000002a0 t bind_mw\n-0000000000000040 t close_xrcd\n-0000000000000050 t cq_event\n-0000000000000490 t create_ah\n-00000000000004b0 t create_counters\n-0000000000000170 t create_cq\n-00000000000004d0 t create_cq_ex\n-00000000000004f0 t create_flow\n-0000000000000510 t create_flow_action_esp\n-0000000000000530 t create_qp\n-0000000000000550 t create_qp_ex\n-0000000000000570 t create_rwq_ind_table\n-0000000000000590 t create_srq\n-00000000000005b0 t create_srq_ex\n-00000000000005d0 t create_wq\n-0000000000000350 t dealloc_mw\n-0000000000000360 t dealloc_pd\n-0000000000000370 t dealloc_td\n-0000000000000380 t dereg_mr\n-0000000000000390 t destroy_ah\n-00000000000003a0 t destroy_counters\n-00000000000003b0 t destroy_cq\n-00000000000003c0 t destroy_flow\n-00000000000003d0 t destroy_flow_action\n-00000000000003e0 t destroy_qp\n-00000000000003f0 t destroy_rwq_ind_table\n-0000000000000400 t destroy_srq\n-0000000000000410 t destroy_wq\n-0000000000000240 t detach_mcast\n-0000000000000420 t free_context\n-0000000000000230 t free_dm\n-0000000000000060 t get_srq_num\n-0000000000000610 t import_dm\n-0000000000000630 t import_mr\n-0000000000000260 t import_pd\n-00000000000002e0 t modify_cq\n-00000000000002f0 t modify_flow_action_esp\n-0000000000000070 t modify_qp\n-0000000000000300 t modify_qp_rate_limit\n-0000000000000200 t modify_srq\n-0000000000000310 t modify_wq\n-00000000000005f0 t open_qp\n-0000000000000280 t open_xrcd\n-0000000000000080 t poll_cq\n-00000000000002b0 t post_recv\n-00000000000002c0 t post_send\n-00000000000002d0 t post_srq_ops\n-0000000000000250 t post_srq_recv\n-0000000000000090 t query_device_ex\n-0000000000000320 t query_ece\n-00000000000000b0 t query_port\n-00000000000000c0 t query_qp\n-00000000000000a0 t query_qp_data_in_order\n-0000000000000330 t query_rt_values\n-0000000000000340 t query_srq\n-0000000000000000 D rdmacore52_0_verbs_dummy_ops\n-0000000000000670 T rdmacore52_0_verbs_set_ops\n-00000000000000d0 t read_counters\n-0000000000000150 t reg_dm_mr\n-0000000000000130 t reg_dmabuf_mr\n-0000000000000110 t reg_mr\n-00000000000000e0 t req_notify_cq\n-00000000000000f0 t rereg_mr\n-00000000000001f0 t resize_cq\n-0000000000000210 t set_ece\n-0000000000000430 t unimport_dm\n-0000000000000440 t unimport_mr\n-0000000000000220 t unimport_pd\n-\n-cmd_device.c.o:\n-0000000000000000 r .LC0\n-000000000000001c r .LC1\n-0000000000000022 r .LC2\n-000000000000002f r .LC3\n-0000000000000039 r .LC4\n-000000000000004c r .LC6\n-000000000000005d r .LC7\n-0000000000000061 r .LC8\n-0000000000000000 r .LC9\n- U __asprintf_chk\n- U __errno_location\n- U __isoc23_sscanf\n- U __stack_chk_fail\n-00000000000010e0 T _ibv_query_gid_ex\n-0000000000001550 T _ibv_query_gid_table\n- U closedir\n- U free\n- U ibv_query_device\n- U ibv_query_port\n- U if_nametoindex\n- U memset\n- U opendir\n-0000000000000180 t query_gid_table_fb\n-0000000000000000 t query_sysfs_gid_type.isra.0\n-0000000000000c60 T rdmacore52_0___ibv_query_gid_ex\n U rdmacore52_0___ioctl_final_num_attrs\n U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_cmd_write_ex\n U rdmacore52_0__execute_ioctl_fallback\n U rdmacore52_0__write_get_req\n U rdmacore52_0__write_get_resp\n U rdmacore52_0__write_set_uhw\n- U rdmacore52_0_execute_ioctl\n-0000000000000740 T rdmacore52_0_ibv_cmd_alloc_async_fd\n-00000000000007f0 T rdmacore52_0_ibv_cmd_get_context\n-0000000000000ad0 T rdmacore52_0_ibv_cmd_query_context\n-0000000000001740 T rdmacore52_0_ibv_cmd_query_device_any\n-0000000000000500 T rdmacore52_0_ibv_cmd_query_port\n- U rdmacore52_0_ibv_read_ibdev_sysfs_file\n- U strcmp\n+ U rdmacore52_0_abi_ver\n+00000000000007e0 T rdmacore52_0_ibv_cmd_create_srq\n+0000000000000900 T rdmacore52_0_ibv_cmd_create_srq_ex\n+0000000000000a10 T rdmacore52_0_ibv_cmd_destroy_srq\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n \n-marshall.c.o:\n-0000000000000000 T ibv_copy_ah_attr_from_kern\n-0000000000000100 T ibv_copy_path_rec_from_kern\n-00000000000001a0 T ibv_copy_path_rec_to_kern\n-0000000000000040 T ibv_copy_qp_attr_from_kern\n+compat-1_0.c.o:\n \n init.c.o:\n 0000000000000000 r .LC0\n 0000000000000010 r .LC1\n 000000000000006f r .LC10\n 000000000000007b r .LC11\n 0000000000000095 r .LC12\n@@ -820,14 +383,105 @@\n U strcmp\n U strcpy\n 0000000000000450 t try_all_drivers\n 0000000000000000 t try_driver\n 0000000000000008 b verbs_log_fp\n 0000000000000010 b verbs_log_level\n \n+cmd.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+ U free\n+0000000000000000 t ibv_cmd_modify_srq_v3\n+ U malloc\n+ U memcmp\n+ U memcpy\n+ U memset\n+ U pthread_cond_init\n+ U pthread_mutex_init\n+ U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_cmd_write_ex\n+ U rdmacore52_0_abi_ver\n+00000000000003c0 T rdmacore52_0_ibv_cmd_alloc_mw\n+0000000000000120 T rdmacore52_0_ibv_cmd_alloc_pd\n+00000000000018b0 T rdmacore52_0_ibv_cmd_attach_mcast\n+00000000000017d0 T rdmacore52_0_ibv_cmd_create_ah\n+00000000000019b0 T rdmacore52_0_ibv_cmd_create_flow\n+0000000000002090 T rdmacore52_0_ibv_cmd_create_rwq_ind_table\n+0000000000001920 T rdmacore52_0_ibv_cmd_detach_mcast\n+0000000000002200 T rdmacore52_0_ibv_cmd_modify_cq\n+0000000000000a80 T rdmacore52_0_ibv_cmd_modify_qp\n+0000000000000d00 T rdmacore52_0_ibv_cmd_modify_qp_ex\n+0000000000000650 T rdmacore52_0_ibv_cmd_modify_srq\n+0000000000001fe0 T rdmacore52_0_ibv_cmd_modify_wq\n+0000000000000740 T rdmacore52_0_ibv_cmd_open_qp\n+0000000000000170 T rdmacore52_0_ibv_cmd_open_xrcd\n+0000000000000450 T rdmacore52_0_ibv_cmd_poll_cq\n+0000000000001320 T rdmacore52_0_ibv_cmd_post_recv\n+0000000000000f90 T rdmacore52_0_ibv_cmd_post_send\n+0000000000001570 T rdmacore52_0_ibv_cmd_post_srq_recv\n+0000000000000880 T rdmacore52_0_ibv_cmd_query_qp\n+00000000000006c0 T rdmacore52_0_ibv_cmd_query_srq\n+0000000000000210 T rdmacore52_0_ibv_cmd_reg_mr\n+0000000000000580 T rdmacore52_0_ibv_cmd_req_notify_cq\n+00000000000002e0 T rdmacore52_0_ibv_cmd_rereg_mr\n+00000000000005f0 T rdmacore52_0_ibv_cmd_resize_cq\n+0000000000000000 B rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+cmd_flow.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0__execute_cmd_write_ex\n+ U rdmacore52_0__execute_ioctl_fallback\n+0000000000000000 T rdmacore52_0_ibv_cmd_destroy_flow\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+cmd_counters.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0___ioctl_final_num_attrs\n+ U rdmacore52_0_execute_ioctl\n+0000000000000000 T rdmacore52_0_ibv_cmd_create_counters\n+0000000000000190 T rdmacore52_0_ibv_cmd_destroy_counters\n+0000000000000240 T rdmacore52_0_ibv_cmd_read_counters\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+cmd_xrcd.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_ioctl_fallback\n+0000000000000000 T rdmacore52_0_ibv_cmd_close_xrcd\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+cmd_ioctl.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+ U ioctl\n+0000000000000000 T rdmacore52_0___ioctl_final_num_attrs\n+0000000000000370 T rdmacore52_0__write_set_uhw\n+0000000000000040 T rdmacore52_0_execute_ioctl\n+\n+cmd_cq.c.o:\n+ U __stack_chk_fail\n+0000000000000000 t ibv_icmd_create_cq\n+ U pthread_cond_wait\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0___ioctl_final_num_attrs\n+ U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_cmd_write_ex\n+ U rdmacore52_0__execute_ioctl_fallback\n+ U rdmacore52_0__write_get_req\n+ U rdmacore52_0__write_get_req_ex\n+ U rdmacore52_0__write_get_resp\n+ U rdmacore52_0__write_get_resp_ex\n+ U rdmacore52_0__write_set_uhw\n+0000000000000510 T rdmacore52_0_ibv_cmd_create_cq\n+0000000000000610 T rdmacore52_0_ibv_cmd_create_cq_ex\n+0000000000000730 T rdmacore52_0_ibv_cmd_destroy_cq\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n cmd_wq.c.o:\n 0000000000000000 r .LC0\n U __errno_location\n U __stack_chk_fail\n U pthread_cond_wait\n U pthread_mutex_lock\n U pthread_mutex_unlock\n@@ -837,72 +491,107 @@\n U rdmacore52_0__write_get_req_ex\n U rdmacore52_0__write_get_resp_ex\n U rdmacore52_0__write_set_uhw\n 0000000000000000 T rdmacore52_0_ibv_cmd_create_wq\n 0000000000000550 T rdmacore52_0_ibv_cmd_destroy_wq\n U rdmacore52_0_verbs_allow_disassociate_destroy\n \n+dynamic_driver.c.o:\n+\n cmd_flow_action.c.o:\n U __errno_location\n U __stack_chk_fail\n U memcpy\n U rdmacore52_0___ioctl_final_num_attrs\n U rdmacore52_0_execute_ioctl\n 0000000000000000 T rdmacore52_0_ibv_cmd_create_flow_action_esp\n 0000000000000610 T rdmacore52_0_ibv_cmd_destroy_flow_action\n 0000000000000320 T rdmacore52_0_ibv_cmd_modify_flow_action_esp\n U rdmacore52_0_verbs_allow_disassociate_destroy\n \n-cmd_mw.c.o:\n- U __stack_chk_fail\n- U rdmacore52_0__execute_cmd_write\n- U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_dealloc_mw\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n-\n-cmd_srq.c.o:\n+cmd_device.c.o:\n+0000000000000000 r .LC0\n+000000000000001c r .LC1\n+0000000000000022 r .LC2\n+000000000000002f r .LC3\n+0000000000000039 r .LC4\n+000000000000004c r .LC6\n+000000000000005d r .LC7\n+0000000000000061 r .LC8\n+0000000000000000 r .LC9\n+ U __asprintf_chk\n U __errno_location\n+ U __isoc23_sscanf\n U __stack_chk_fail\n-0000000000000000 t ibv_icmd_create_srq\n- U pthread_cond_init\n- U pthread_cond_wait\n- U pthread_mutex_init\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n+00000000000010e0 T _ibv_query_gid_ex\n+0000000000001550 T _ibv_query_gid_table\n+ U closedir\n+ U free\n+ U ibv_query_device\n+ U ibv_query_port\n+ U if_nametoindex\n+ U memset\n+ U opendir\n+0000000000000180 t query_gid_table_fb\n+0000000000000000 t query_sysfs_gid_type.isra.0\n+0000000000000c60 T rdmacore52_0___ibv_query_gid_ex\n U rdmacore52_0___ioctl_final_num_attrs\n U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_cmd_write_ex\n U rdmacore52_0__execute_ioctl_fallback\n U rdmacore52_0__write_get_req\n U rdmacore52_0__write_get_resp\n U rdmacore52_0__write_set_uhw\n- U rdmacore52_0_abi_ver\n-00000000000007e0 T rdmacore52_0_ibv_cmd_create_srq\n-0000000000000900 T rdmacore52_0_ibv_cmd_create_srq_ex\n-0000000000000a10 T rdmacore52_0_ibv_cmd_destroy_srq\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n+ U rdmacore52_0_execute_ioctl\n+0000000000000740 T rdmacore52_0_ibv_cmd_alloc_async_fd\n+00000000000007f0 T rdmacore52_0_ibv_cmd_get_context\n+0000000000000ad0 T rdmacore52_0_ibv_cmd_query_context\n+0000000000001740 T rdmacore52_0_ibv_cmd_query_device_any\n+0000000000000500 T rdmacore52_0_ibv_cmd_query_port\n+ U rdmacore52_0_ibv_read_ibdev_sysfs_file\n+ U strcmp\n \n-enum_strs.c.o:\n+ibdev_nl.c.o:\n 0000000000000000 r .LC0\n-0000000000000140 d event_type_str.2\n-0000000000000050 T ibv_event_type_str\n-0000000000000000 T ibv_node_type_str\n-0000000000000030 T ibv_port_state_str\n-0000000000000070 T ibv_wc_status_str\n-0000000000000220 d node_type_str.4\n-00000000000001e0 d port_state_str.3\n-0000000000000090 T rdmacore52_0_ibv_wr_opcode_str\n-0000000000000080 d wc_status_str.1\n-0000000000000000 d wr_opcode_str.0\n-\n-cmd_flow.c.o:\n+0000000000000003 r .LC1\n+000000000000001a r .LC2\n+0000000000000021 r .LC3\n+ U __snprintf_chk\n U __stack_chk_fail\n- U rdmacore52_0__execute_cmd_write_ex\n- U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_destroy_flow\n- U rdmacore52_0_verbs_allow_disassociate_destroy\n+ U calloc\n+ U close\n+ U closedir\n+ U dirfd\n+0000000000000090 t find_sysfs_devs_nl_cb\n+0000000000000250 t find_uverbs_nl_cb\n+ U free\n+0000000000000000 t get_copy_on_fork_cb\n+ U ibv_get_sysfs_path\n+ U nl_socket_free\n+ U nla_get_string\n+ U nla_get_u32\n+ U nla_get_u64\n+ U nla_get_u8\n+ U nlmsg_hdr\n+ U nlmsg_parse\n+ U openat\n+ U opendir\n+ U rdmacore52_0_abi_ver\n+ U rdmacore52_0_decode_knode_type\n+0000000000000370 T rdmacore52_0_find_sysfs_devs_nl\n+00000000000005b0 T rdmacore52_0_get_copy_on_fork\n+ U rdmacore52_0_rdmanl_get_chardev\n+ U rdmacore52_0_rdmanl_get_copy_on_fork\n+ U rdmacore52_0_rdmanl_get_devices\n+ U rdmacore52_0_rdmanl_policy\n+ U rdmacore52_0_rdmanl_socket_alloc\n+ U rdmacore52_0_setup_sysfs_uverbs\n+ U rdmacore52_0_try_access_device\n+ U readdir\n+ U snprintf\n \n verbs.c.o:\n 0000000000000000 r .LC0\n 0000000000000012 r .LC1\n 0000000000000140 r CSWTCH.38\n 00000000000000e0 r CSWTCH.41\n U __errno_location\n@@ -984,90 +673,426 @@\n U rdmacore52_0_neigh_set_oif\n U rdmacore52_0_neigh_set_src\n U rdmacore52_0_neigh_set_vlan_id\n U rdmacore52_0_process_get_neigh\n U rdmacore52_0_verbs_init_cq\n U read\n \n-cmd.c.o:\n+cmd_mw.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_ioctl_fallback\n+0000000000000000 T rdmacore52_0_ibv_cmd_dealloc_mw\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+memory.c.o:\n+0000000000000000 r .LC0\n+000000000000000f r .LC1\n+0000000000000012 r .LC2\n+000000000000001a r .LC3\n+000000000000002a r .LC4\n+0000000000000032 r .LC7\n+0000000000000000 r .LC8\n U __errno_location\n+ U __isoc99_sscanf\n+0000000000000000 t __mm_remove\n+ U __snprintf_chk\n U __stack_chk_fail\n+ U fclose\n+ U fgets\n+ U fopen\n U free\n-0000000000000000 t ibv_cmd_modify_srq_v3\n+00000000000005a0 t get_page_size\n+ U getenv\n+ U getpid\n+0000000000000004 b huge_page_enabled\n+00000000000011b0 T ibv_dofork_range\n+0000000000001170 T ibv_dontfork_range\n+0000000000000fc0 T ibv_fork_init\n+0000000000001140 T ibv_is_fork_initialized\n+0000000000000a50 t ibv_madvise_range.part.0\n+000000000000000a t ibv_madvise_range.part.0.cold\n+ U madvise\n U malloc\n- U memcmp\n- U memcpy\n- U memset\n+0000000000000020 b mm_mutex\n+0000000000000048 b mm_root\n+0000000000000008 b page_size\n+ U posix_memalign\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0_get_copy_on_fork\n+0000000000000710 t split_range\n+0000000000000000 t split_range.cold\n+ U strstr\n+ U sysconf\n+0000000000000000 b too_late\n+\n+marshall.c.o:\n+0000000000000000 T ibv_copy_ah_attr_from_kern\n+0000000000000100 T ibv_copy_path_rec_from_kern\n+00000000000001a0 T ibv_copy_path_rec_to_kern\n+0000000000000040 T ibv_copy_qp_attr_from_kern\n+\n+cmd_pd.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0__execute_cmd_write\n+ U rdmacore52_0__execute_ioctl_fallback\n+0000000000000000 T rdmacore52_0_ibv_cmd_dealloc_pd\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+dummy_ops.c.o:\n+ U __errno_location\n+0000000000000000 t advise_mr\n+00000000000001d0 t alloc_dm\n+00000000000001b0 t alloc_mw\n+0000000000000190 t alloc_null_mr\n+0000000000000450 t alloc_parent_domain\n+0000000000000650 t alloc_pd\n+0000000000000470 t alloc_td\n+0000000000000010 t async_event\n+0000000000000020 t attach_counters_point_flow\n+0000000000000030 t attach_mcast\n+00000000000002a0 t bind_mw\n+0000000000000040 t close_xrcd\n+0000000000000050 t cq_event\n+0000000000000490 t create_ah\n+00000000000004b0 t create_counters\n+0000000000000170 t create_cq\n+00000000000004d0 t create_cq_ex\n+00000000000004f0 t create_flow\n+0000000000000510 t create_flow_action_esp\n+0000000000000530 t create_qp\n+0000000000000550 t create_qp_ex\n+0000000000000570 t create_rwq_ind_table\n+0000000000000590 t create_srq\n+00000000000005b0 t create_srq_ex\n+00000000000005d0 t create_wq\n+0000000000000350 t dealloc_mw\n+0000000000000360 t dealloc_pd\n+0000000000000370 t dealloc_td\n+0000000000000380 t dereg_mr\n+0000000000000390 t destroy_ah\n+00000000000003a0 t destroy_counters\n+00000000000003b0 t destroy_cq\n+00000000000003c0 t destroy_flow\n+00000000000003d0 t destroy_flow_action\n+00000000000003e0 t destroy_qp\n+00000000000003f0 t destroy_rwq_ind_table\n+0000000000000400 t destroy_srq\n+0000000000000410 t destroy_wq\n+0000000000000240 t detach_mcast\n+0000000000000420 t free_context\n+0000000000000230 t free_dm\n+0000000000000060 t get_srq_num\n+0000000000000610 t import_dm\n+0000000000000630 t import_mr\n+0000000000000260 t import_pd\n+00000000000002e0 t modify_cq\n+00000000000002f0 t modify_flow_action_esp\n+0000000000000070 t modify_qp\n+0000000000000300 t modify_qp_rate_limit\n+0000000000000200 t modify_srq\n+0000000000000310 t modify_wq\n+00000000000005f0 t open_qp\n+0000000000000280 t open_xrcd\n+0000000000000080 t poll_cq\n+00000000000002b0 t post_recv\n+00000000000002c0 t post_send\n+00000000000002d0 t post_srq_ops\n+0000000000000250 t post_srq_recv\n+0000000000000090 t query_device_ex\n+0000000000000320 t query_ece\n+00000000000000b0 t query_port\n+00000000000000c0 t query_qp\n+00000000000000a0 t query_qp_data_in_order\n+0000000000000330 t query_rt_values\n+0000000000000340 t query_srq\n+0000000000000000 D rdmacore52_0_verbs_dummy_ops\n+0000000000000670 T rdmacore52_0_verbs_set_ops\n+00000000000000d0 t read_counters\n+0000000000000150 t reg_dm_mr\n+0000000000000130 t reg_dmabuf_mr\n+0000000000000110 t reg_mr\n+00000000000000e0 t req_notify_cq\n+00000000000000f0 t rereg_mr\n+00000000000001f0 t resize_cq\n+0000000000000210 t set_ece\n+0000000000000430 t unimport_dm\n+0000000000000440 t unimport_mr\n+0000000000000220 t unimport_pd\n+\n+device.c.o:\n+0000000000000000 r .LC0\n+000000000000000a r .LC1\n+ U _GLOBAL_OFFSET_TABLE_\n+ U __errno_location\n+ U __isoc23_sscanf\n+0000000000000000 t __lib_ibv_create_cq_ex\n+ U __stack_chk_fail\n+ U calloc\n+ U close\n+0000000000000020 b dev_list_lock\n+0000000000000000 d device_list\n+ U free\n+ U fstat\n+0000000000000d00 T ibv_ack_async_event\n+0000000000000c30 T ibv_close_device\n+00000000000001e0 T ibv_free_device_list\n+0000000000000c50 T ibv_get_async_event\n+0000000000000230 T ibv_get_device_guid\n+0000000000000360 T ibv_get_device_index\n+00000000000000d0 T ibv_get_device_list\n+0000000000000220 T ibv_get_device_name\n+00000000000009c0 T ibv_import_device\n+00000000000008b0 T ibv_open_device\n+ U ibv_query_device\n+ U ibv_query_port\n+0000000000000000 b initialized.0\n U pthread_cond_init\n+ U pthread_cond_signal\n U pthread_mutex_init\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0___lib_query_port\n+00000000000005a0 T rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_execute_ioctl\n+ U rdmacore52_0_ibv_cmd_alloc_async_fd\n+ U rdmacore52_0_ibv_read_ibdev_sysfs_file\n+ U rdmacore52_0_ibverbs_device_hold\n+ U rdmacore52_0_ibverbs_device_put\n+ U rdmacore52_0_ibverbs_get_device_list\n+ U rdmacore52_0_ibverbs_init\n+ U rdmacore52_0_open_cdev\n+ U rdmacore52_0_verbs_dummy_ops\n+00000000000003e0 T rdmacore52_0_verbs_init_context\n+0000000000000380 T rdmacore52_0_verbs_init_cq\n+00000000000007a0 T rdmacore52_0_verbs_open_device\n+ U rdmacore52_0_verbs_set_ops\n+0000000000000be0 T rdmacore52_0_verbs_uninit_context\n+ U read\n+\n+cmd_qp.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+0000000000000000 t ibv_icmd_create_qp\n+ U pthread_cond_init\n+ U pthread_cond_wait\n+ U pthread_mutex_init\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0___ioctl_final_num_attrs\n U rdmacore52_0__execute_cmd_write\n U rdmacore52_0__execute_cmd_write_ex\n+ U rdmacore52_0__execute_ioctl_fallback\n+ U rdmacore52_0__write_get_req\n+ U rdmacore52_0__write_get_req_ex\n+ U rdmacore52_0__write_get_resp\n+ U rdmacore52_0__write_get_resp_ex\n+ U rdmacore52_0__write_set_uhw\n U rdmacore52_0_abi_ver\n-00000000000003c0 T rdmacore52_0_ibv_cmd_alloc_mw\n-0000000000000120 T rdmacore52_0_ibv_cmd_alloc_pd\n-00000000000018b0 T rdmacore52_0_ibv_cmd_attach_mcast\n-00000000000017d0 T rdmacore52_0_ibv_cmd_create_ah\n-00000000000019b0 T rdmacore52_0_ibv_cmd_create_flow\n-0000000000002090 T rdmacore52_0_ibv_cmd_create_rwq_ind_table\n-0000000000001920 T rdmacore52_0_ibv_cmd_detach_mcast\n-0000000000002200 T rdmacore52_0_ibv_cmd_modify_cq\n-0000000000000a80 T rdmacore52_0_ibv_cmd_modify_qp\n-0000000000000d00 T rdmacore52_0_ibv_cmd_modify_qp_ex\n-0000000000000650 T rdmacore52_0_ibv_cmd_modify_srq\n-0000000000001fe0 T rdmacore52_0_ibv_cmd_modify_wq\n-0000000000000740 T rdmacore52_0_ibv_cmd_open_qp\n-0000000000000170 T rdmacore52_0_ibv_cmd_open_xrcd\n-0000000000000450 T rdmacore52_0_ibv_cmd_poll_cq\n-0000000000001320 T rdmacore52_0_ibv_cmd_post_recv\n-0000000000000f90 T rdmacore52_0_ibv_cmd_post_send\n-0000000000001570 T rdmacore52_0_ibv_cmd_post_srq_recv\n-0000000000000880 T rdmacore52_0_ibv_cmd_query_qp\n-00000000000006c0 T rdmacore52_0_ibv_cmd_query_srq\n-0000000000000210 T rdmacore52_0_ibv_cmd_reg_mr\n-0000000000000580 T rdmacore52_0_ibv_cmd_req_notify_cq\n-00000000000002e0 T rdmacore52_0_ibv_cmd_rereg_mr\n-00000000000005f0 T rdmacore52_0_ibv_cmd_resize_cq\n-0000000000000000 B rdmacore52_0_verbs_allow_disassociate_destroy\n+0000000000000c10 T rdmacore52_0_ibv_cmd_create_qp\n+0000000000000d80 T rdmacore52_0_ibv_cmd_create_qp_ex\n+0000000000000e80 T rdmacore52_0_ibv_cmd_create_qp_ex2\n+0000000000000f80 T rdmacore52_0_ibv_cmd_destroy_qp\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n \n-cmd_ah.c.o:\n+cmd_rwq_ind.c.o:\n+ U __stack_chk_fail\n+ U rdmacore52_0__execute_cmd_write_ex\n+ U rdmacore52_0__execute_ioctl_fallback\n+0000000000000000 T rdmacore52_0_ibv_cmd_destroy_rwq_ind_table\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+all_providers.c.o:\n+0000000000000000 d all_providers\n+0000000000000000 D verbs_provider_all\n+ U verbs_provider_bnxt_re\n+ U verbs_provider_cxgb4\n+ U verbs_provider_efa\n+ U verbs_provider_erdma\n+ U verbs_provider_hfi1verbs\n+ U verbs_provider_hns\n+ U verbs_provider_ipathverbs\n+ U verbs_provider_irdma\n+ U verbs_provider_mana\n+ U verbs_provider_mlx4\n+ U verbs_provider_mlx5\n+ U verbs_provider_mthca\n+ U verbs_provider_ocrdma\n+ U verbs_provider_qedr\n+ U verbs_provider_rxe\n+ U verbs_provider_siw\n+ U verbs_provider_vmw_pvrdma\n+\n+cmd_mr.c.o:\n+0000000000000000 r .LC5\n+ U __errno_location\n U __stack_chk_fail\n U rdmacore52_0__execute_cmd_write\n U rdmacore52_0__execute_ioctl_fallback\n-0000000000000000 T rdmacore52_0_ibv_cmd_destroy_ah\n+ U rdmacore52_0_execute_ioctl\n+0000000000000000 T rdmacore52_0_ibv_cmd_advise_mr\n+0000000000000130 T rdmacore52_0_ibv_cmd_dereg_mr\n+0000000000000230 T rdmacore52_0_ibv_cmd_query_mr\n+0000000000000360 T rdmacore52_0_ibv_cmd_reg_dmabuf_mr\n U rdmacore52_0_verbs_allow_disassociate_destroy\n \n-bitmap.c.o:\n- U memset\n-0000000000000160 T rdmacore52_0_bitmap_fill_region\n-0000000000000000 T rdmacore52_0_bitmap_find_first_bit\n-0000000000000220 T rdmacore52_0_bitmap_find_free_region\n-0000000000000090 T rdmacore52_0_bitmap_zero_region\n+cmd_dm.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+ U rdmacore52_0___ioctl_final_num_attrs\n+ U rdmacore52_0_execute_ioctl\n+0000000000000000 T rdmacore52_0_ibv_cmd_alloc_dm\n+00000000000001e0 T rdmacore52_0_ibv_cmd_free_dm\n+0000000000000290 T rdmacore52_0_ibv_cmd_reg_dm_mr\n+ U rdmacore52_0_verbs_allow_disassociate_destroy\n+\n+neigh.c.o:\n+ U __errno_location\n+ U __fdelt_chk\n+ U __stack_chk_fail\n+ U bind\n+ U close\n+0000000000000000 d encoded_prefixes\n+ U freeaddrinfo\n+ U freeifaddrs\n+0000000000000110 t get_link_local_mac_ipv6\n+0000000000000080 t get_mcast_mac_ipv4\n+0000000000000000 t get_mcast_mac_ipv6\n+00000000000001b0 t get_neigh_cb\n+00000000000001e0 t get_neigh_cb_event\n+0000000000000670 t get_route_cb\n+0000000000000240 t get_route_cb_parser\n+ U getifaddrs\n+ U if_nametoindex\n+ U memcmp\n+ U memcpy\n+ U nl_addr_build\n+ U nl_addr_clone\n+ U nl_addr_fill_sockaddr\n+ U nl_addr_get_binary_addr\n+ U nl_addr_get_family\n+ U nl_addr_get_len\n+ U nl_addr_get_prefixlen\n+ U nl_addr_info\n+ U nl_addr_put\n+ U nl_addr_set_prefixlen\n+ U nl_cache_free\n+ U nl_cache_mngt_provide\n+ U nl_cache_mngt_unprovide\n+ U nl_cache_refill\n+ U nl_connect\n+ U nl_msg_parse\n+ U nl_object_match_filter\n+ U nl_recvmsgs_default\n+ U nl_send_auto\n+ U nl_socket_add_membership\n+ U nl_socket_alloc\n+ U nl_socket_disable_seq_check\n+ U nl_socket_free\n+ U nl_socket_get_fd\n+ U nl_socket_modify_cb\n+ U nla_put\n+ U nlmsg_alloc_simple\n+ U nlmsg_append\n+ U nlmsg_free\n+00000000000010d0 T rdmacore52_0_neigh_free_resources\n+0000000000001070 T rdmacore52_0_neigh_get_ll\n+0000000000000d00 T rdmacore52_0_neigh_get_oif_from_src\n+0000000000000f70 T rdmacore52_0_neigh_get_vlan_id_from_dev\n+0000000000000e20 T rdmacore52_0_neigh_init_resources\n+0000000000001000 T rdmacore52_0_neigh_set_dst\n+0000000000001060 T rdmacore52_0_neigh_set_oif\n+0000000000001030 T rdmacore52_0_neigh_set_src\n+0000000000000fe0 T rdmacore52_0_neigh_set_vlan_id\n+00000000000011b0 T rdmacore52_0_process_get_neigh\n+ U read\n+ U rtnl_link_alloc_cache\n+ U rtnl_link_get\n+ U rtnl_link_get_addr\n+ U rtnl_link_is_vlan\n+ U rtnl_link_put\n+ U rtnl_link_vlan_get_id\n+ U rtnl_neigh_alloc\n+ U rtnl_neigh_alloc_cache\n+ U rtnl_neigh_get\n+ U rtnl_neigh_get_lladdr\n+ U rtnl_neigh_put\n+ U rtnl_neigh_set_dst\n+ U rtnl_neigh_set_ifindex\n+ U rtnl_route_alloc_cache\n+ U rtnl_route_get_pref_src\n+ U rtnl_route_get_type\n+ U rtnl_route_nexthop_n\n+ U rtnl_route_nh_get_gateway\n+ U rtnl_route_nh_get_ifindex\n+ U select\n+ U sendto\n+ U socket\n+ U timerfd_create\n+ U timerfd_settime\n+\n+static_driver.c.o:\n+0000000000000000 T ibv_static_providers\n+0000000000000000 R verbs_provider_none\n+\n+mmio.c.o:\n \n cl_map.c.o:\n 0000000000000120 T rdmacore52_0_cl_qmap_apply_func\n 0000000000000e00 T rdmacore52_0_cl_qmap_delta\n 0000000000000060 T rdmacore52_0_cl_qmap_get\n 00000000000000c0 T rdmacore52_0_cl_qmap_get_next\n 0000000000000000 T rdmacore52_0_cl_qmap_init\n 0000000000000170 T rdmacore52_0_cl_qmap_insert\n 0000000000000940 T rdmacore52_0_cl_qmap_merge\n 00000000000008e0 T rdmacore52_0_cl_qmap_remove\n 0000000000000460 T rdmacore52_0_cl_qmap_remove_item\n \n-util.c.o:\n- U fcntl\n- U getenv\n- U getrandom\n- U rand_r\n-00000000000000d0 T rdmacore52_0_check_env\n-0000000000000050 T rdmacore52_0_get_random\n-0000000000000000 T rdmacore52_0_set_fd_nonblock\n-0000000000000110 T rdmacore52_0_xorshift32\n-0000000000000000 b seed.0\n- U time\n+rdma_nl.c.o:\n+ U __stack_chk_fail\n+ U nl_connect\n+ U nl_recvmsgs_default\n+ U nl_send_auto\n+ U nl_send_simple\n+ U nl_socket_alloc\n+ U nl_socket_disable_auto_ack\n+ U nl_socket_disable_msg_peek\n+ U nl_socket_free\n+ U nl_socket_modify_cb\n+ U nl_socket_modify_err_cb\n+ U nla_put\n+ U nlmsg_alloc_simple\n+ U nlmsg_free\n+0000000000000200 T rdmacore52_0_rdmanl_get_chardev\n+0000000000000060 T rdmacore52_0_rdmanl_get_copy_on_fork\n+0000000000000130 T rdmacore52_0_rdmanl_get_devices\n+0000000000000000 D rdmacore52_0_rdmanl_policy\n+0000000000000010 T rdmacore52_0_rdmanl_socket_alloc\n+0000000000000000 t rdmanl_saw_err_cb\n+ U strlen\n+\n+open_cdev.c.o:\n+0000000000000000 r .LC0\n+0000000000000010 r .LC1\n+000000000000001b r .LC2\n+ U __asprintf_chk\n+ U __stack_chk_fail\n+ U close\n+ U free\n+ U fstat\n+ U inotify_add_watch\n+ U inotify_init1\n+ U open\n+0000000000000000 t open_cdev_robust.isra.0\n+ U poll\n+0000000000000380 T rdmacore52_0_open_cdev\n+ U read\n+ U timerfd_create\n+ U timerfd_settime\n \n node_name_map.c.o:\n 0000000000000000 r .LC0\n 000000000000001b r .LC1\n 000000000000001d r .LC2\n 0000000000000000 r .LC3\n 0000000000000020 r .LC4\n@@ -1106,50 +1131,25 @@\n U pthread_mutex_lock\n U pthread_mutex_unlock\n 00000000000002c0 T rdmacore52_0_iset_alloc_range\n 0000000000000000 T rdmacore52_0_iset_create\n 0000000000000050 T rdmacore52_0_iset_destroy\n 0000000000000090 T rdmacore52_0_iset_insert_range\n \n-rdma_nl.c.o:\n- U __stack_chk_fail\n- U nl_connect\n- U nl_recvmsgs_default\n- U nl_send_auto\n- U nl_send_simple\n- U nl_socket_alloc\n- U nl_socket_disable_auto_ack\n- U nl_socket_disable_msg_peek\n- U nl_socket_free\n- U nl_socket_modify_cb\n- U nl_socket_modify_err_cb\n- U nla_put\n- U nlmsg_alloc_simple\n- U nlmsg_free\n-0000000000000200 T rdmacore52_0_rdmanl_get_chardev\n-0000000000000060 T rdmacore52_0_rdmanl_get_copy_on_fork\n-0000000000000130 T rdmacore52_0_rdmanl_get_devices\n-0000000000000000 D rdmacore52_0_rdmanl_policy\n-0000000000000010 T rdmacore52_0_rdmanl_socket_alloc\n-0000000000000000 t rdmanl_saw_err_cb\n- U strlen\n-\n-mmio.c.o:\n+bitmap.c.o:\n+ U memset\n+0000000000000160 T rdmacore52_0_bitmap_fill_region\n+0000000000000000 T rdmacore52_0_bitmap_find_first_bit\n+0000000000000220 T rdmacore52_0_bitmap_find_free_region\n+0000000000000090 T rdmacore52_0_bitmap_zero_region\n \n-open_cdev.c.o:\n-0000000000000000 r .LC0\n-0000000000000010 r .LC1\n-000000000000001b r .LC2\n- U __asprintf_chk\n- U __stack_chk_fail\n- U close\n- U free\n- U fstat\n- U inotify_add_watch\n- U inotify_init1\n- U open\n-0000000000000000 t open_cdev_robust.isra.0\n- U poll\n-0000000000000380 T rdmacore52_0_open_cdev\n- U read\n- U timerfd_create\n- U timerfd_settime\n+util.c.o:\n+ U fcntl\n+ U getenv\n+ U getrandom\n+ U rand_r\n+00000000000000d0 T rdmacore52_0_check_env\n+0000000000000050 T rdmacore52_0_get_random\n+0000000000000000 T rdmacore52_0_set_fd_nonblock\n+0000000000000110 T rdmacore52_0_xorshift32\n+0000000000000000 b seed.0\n+ U time\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,42 +1,42 @@\n ---------- 0 0 0 6648 1970-01-01 00:00:00.000000 /\n ---------- 0 0 0 0 1970-01-01 00:00:00.000000 //\n ?rw-r--r-- 0 0 0 5152 1970-01-01 00:00:00.000000 cmd_fallback.c.o\n-?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_pd.c.o\n-?rw-r--r-- 0 0 0 7928 1970-01-01 00:00:00.000000 cmd_qp.c.o\n-?rw-r--r-- 0 0 0 1288 1970-01-01 00:00:00.000000 static_driver.c.o\n-?rw-r--r-- 0 0 0 5144 1970-01-01 00:00:00.000000 cmd_cq.c.o\n ?rw-r--r-- 0 0 0 3824 1970-01-01 00:00:00.000000 sysfs.c.o\n-?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 dynamic_driver.c.o\n-?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_xrcd.c.o\n-?rw-r--r-- 0 0 0 10040 1970-01-01 00:00:00.000000 memory.c.o\n-?rw-r--r-- 0 0 0 2680 1970-01-01 00:00:00.000000 cmd_ioctl.c.o\n+?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_ah.c.o\n+?rw-r--r-- 0 0 0 6152 1970-01-01 00:00:00.000000 enum_strs.c.o\n+?rw-r--r-- 0 0 0 6048 1970-01-01 00:00:00.000000 cmd_srq.c.o\n ?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 compat-1_0.c.o\n-?rw-r--r-- 0 0 0 2944 1970-01-01 00:00:00.000000 cmd_counters.c.o\n-?rw-r--r-- 0 0 0 1792 1970-01-01 00:00:00.000000 cmd_rwq_ind.c.o\n-?rw-r--r-- 0 0 0 3352 1970-01-01 00:00:00.000000 cmd_dm.c.o\n-?rw-r--r-- 0 0 0 3640 1970-01-01 00:00:00.000000 cmd_mr.c.o\n-?rw-r--r-- 0 0 0 2624 1970-01-01 00:00:00.000000 all_providers.c.o\n-?rw-r--r-- 0 0 0 14928 1970-01-01 00:00:00.000000 neigh.c.o\n-?rw-r--r-- 0 0 0 11832 1970-01-01 00:00:00.000000 device.c.o\n-?rw-r--r-- 0 0 0 6016 1970-01-01 00:00:00.000000 ibdev_nl.c.o\n-?rw-r--r-- 0 0 0 14048 1970-01-01 00:00:00.000000 dummy_ops.c.o\n-?rw-r--r-- 0 0 0 12760 1970-01-01 00:00:00.000000 cmd_device.c.o\n-?rw-r--r-- 0 0 0 1960 1970-01-01 00:00:00.000000 marshall.c.o\n ?rw-r--r-- 0 0 0 14800 1970-01-01 00:00:00.000000 init.c.o\n+?rw-r--r-- 0 0 0 18608 1970-01-01 00:00:00.000000 cmd.c.o\n+?rw-r--r-- 0 0 0 1784 1970-01-01 00:00:00.000000 cmd_flow.c.o\n+?rw-r--r-- 0 0 0 2944 1970-01-01 00:00:00.000000 cmd_counters.c.o\n+?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_xrcd.c.o\n+?rw-r--r-- 0 0 0 2680 1970-01-01 00:00:00.000000 cmd_ioctl.c.o\n+?rw-r--r-- 0 0 0 5144 1970-01-01 00:00:00.000000 cmd_cq.c.o\n ?rw-r--r-- 0 0 0 4256 1970-01-01 00:00:00.000000 cmd_wq.c.o\n+?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 dynamic_driver.c.o\n ?rw-r--r-- 0 0 0 3808 1970-01-01 00:00:00.000000 cmd_flow_action.c.o\n-?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_mw.c.o\n-?rw-r--r-- 0 0 0 6048 1970-01-01 00:00:00.000000 cmd_srq.c.o\n-?rw-r--r-- 0 0 0 6152 1970-01-01 00:00:00.000000 enum_strs.c.o\n-?rw-r--r-- 0 0 0 1784 1970-01-01 00:00:00.000000 cmd_flow.c.o\n+?rw-r--r-- 0 0 0 12760 1970-01-01 00:00:00.000000 cmd_device.c.o\n+?rw-r--r-- 0 0 0 6016 1970-01-01 00:00:00.000000 ibdev_nl.c.o\n ?rw-r--r-- 0 0 0 18584 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 18608 1970-01-01 00:00:00.000000 cmd.c.o\n-?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_ah.c.o\n-?rw-r--r-- 0 0 0 2504 1970-01-01 00:00:00.000000 bitmap.c.o\n+?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_mw.c.o\n+?rw-r--r-- 0 0 0 10040 1970-01-01 00:00:00.000000 memory.c.o\n+?rw-r--r-- 0 0 0 1960 1970-01-01 00:00:00.000000 marshall.c.o\n+?rw-r--r-- 0 0 0 1760 1970-01-01 00:00:00.000000 cmd_pd.c.o\n+?rw-r--r-- 0 0 0 14048 1970-01-01 00:00:00.000000 dummy_ops.c.o\n+?rw-r--r-- 0 0 0 11832 1970-01-01 00:00:00.000000 device.c.o\n+?rw-r--r-- 0 0 0 7928 1970-01-01 00:00:00.000000 cmd_qp.c.o\n+?rw-r--r-- 0 0 0 1792 1970-01-01 00:00:00.000000 cmd_rwq_ind.c.o\n+?rw-r--r-- 0 0 0 2624 1970-01-01 00:00:00.000000 all_providers.c.o\n+?rw-r--r-- 0 0 0 3640 1970-01-01 00:00:00.000000 cmd_mr.c.o\n+?rw-r--r-- 0 0 0 3352 1970-01-01 00:00:00.000000 cmd_dm.c.o\n+?rw-r--r-- 0 0 0 14928 1970-01-01 00:00:00.000000 neigh.c.o\n+?rw-r--r-- 0 0 0 1288 1970-01-01 00:00:00.000000 static_driver.c.o\n+?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 mmio.c.o\n ?rw-r--r-- 0 0 0 6272 1970-01-01 00:00:00.000000 cl_map.c.o\n-?rw-r--r-- 0 0 0 2264 1970-01-01 00:00:00.000000 util.c.o\n-?rw-r--r-- 0 0 0 5472 1970-01-01 00:00:00.000000 node_name_map.c.o\n-?rw-r--r-- 0 0 0 3400 1970-01-01 00:00:00.000000 interval_set.c.o\n ?rw-r--r-- 0 0 0 4472 1970-01-01 00:00:00.000000 rdma_nl.c.o\n-?rw-r--r-- 0 0 0 608 1970-01-01 00:00:00.000000 mmio.c.o\n ?rw-r--r-- 0 0 0 3952 1970-01-01 00:00:00.000000 open_cdev.c.o\n+?rw-r--r-- 0 0 0 5472 1970-01-01 00:00:00.000000 node_name_map.c.o\n+?rw-r--r-- 0 0 0 3400 1970-01-01 00:00:00.000000 interval_set.c.o\n+?rw-r--r-- 0 0 0 2504 1970-01-01 00:00:00.000000 bitmap.c.o\n+?rw-r--r-- 0 0 0 2264 1970-01-01 00:00:00.000000 util.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libipathverbs-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libipathverbs-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,10 +1,9 @@\n \n Archive index:\n-verbs_provider_ipathverbs in ipathverbs.c.o\n rdmacore52_0_ipath_query_device in verbs.c.o\n rdmacore52_0_ipath_query_port in verbs.c.o\n rdmacore52_0_ipath_alloc_pd in verbs.c.o\n rdmacore52_0_ipath_free_pd in verbs.c.o\n rdmacore52_0_ipath_reg_mr in verbs.c.o\n rdmacore52_0_ipath_dereg_mr in verbs.c.o\n rdmacore52_0_ipath_create_cq in verbs.c.o\n@@ -28,71 +27,15 @@\n rdmacore52_0_ipath_modify_srq_v1 in verbs.c.o\n rdmacore52_0_ipath_query_srq in verbs.c.o\n rdmacore52_0_ipath_destroy_srq in verbs.c.o\n rdmacore52_0_ipath_destroy_srq_v1 in verbs.c.o\n rdmacore52_0_ipath_post_srq_recv in verbs.c.o\n rdmacore52_0_ipath_create_ah in verbs.c.o\n rdmacore52_0_ipath_destroy_ah in verbs.c.o\n-\n-ipathverbs.c.o:\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t drv__register_driver\n- U free\n-0000000000000000 r hca_table\n-0000000000000060 t ipath_alloc_context\n-0000000000000260 d ipath_ctx_common_ops\n-0000000000000000 d ipath_ctx_v1_ops\n-0000000000000000 d ipath_dev_ops\n-0000000000000010 t ipath_device_alloc\n-0000000000000040 t ipath_free_context\n-0000000000000000 t ipath_uninit_device\n- U rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_ibv_cmd_attach_mcast\n- U rdmacore52_0_ibv_cmd_detach_mcast\n- U rdmacore52_0_ibv_cmd_get_context\n- U rdmacore52_0_ibv_cmd_poll_cq\n- U rdmacore52_0_ibv_cmd_post_recv\n- U rdmacore52_0_ibv_cmd_post_srq_recv\n- U rdmacore52_0_ibv_cmd_req_notify_cq\n- U rdmacore52_0_ipath_alloc_pd\n- U rdmacore52_0_ipath_create_ah\n- U rdmacore52_0_ipath_create_cq\n- U rdmacore52_0_ipath_create_cq_v1\n- U rdmacore52_0_ipath_create_qp\n- U rdmacore52_0_ipath_create_qp_v1\n- U rdmacore52_0_ipath_create_srq\n- U rdmacore52_0_ipath_create_srq_v1\n- U rdmacore52_0_ipath_dereg_mr\n- U rdmacore52_0_ipath_destroy_ah\n- U rdmacore52_0_ipath_destroy_cq\n- U rdmacore52_0_ipath_destroy_cq_v1\n- U rdmacore52_0_ipath_destroy_qp\n- U rdmacore52_0_ipath_destroy_qp_v1\n- U rdmacore52_0_ipath_destroy_srq\n- U rdmacore52_0_ipath_destroy_srq_v1\n- U rdmacore52_0_ipath_free_pd\n- U rdmacore52_0_ipath_modify_qp\n- U rdmacore52_0_ipath_modify_srq\n- U rdmacore52_0_ipath_modify_srq_v1\n- U rdmacore52_0_ipath_poll_cq\n- U rdmacore52_0_ipath_post_recv\n- U rdmacore52_0_ipath_post_send\n- U rdmacore52_0_ipath_post_srq_recv\n- U rdmacore52_0_ipath_query_device\n- U rdmacore52_0_ipath_query_port\n- U rdmacore52_0_ipath_query_qp\n- U rdmacore52_0_ipath_query_srq\n- U rdmacore52_0_ipath_reg_mr\n- U rdmacore52_0_ipath_resize_cq\n- U rdmacore52_0_ipath_resize_cq_v1\n- U rdmacore52_0_verbs_register_driver_34\n- U rdmacore52_0_verbs_set_ops\n- U rdmacore52_0_verbs_uninit_context\n-0000000000000000 D verbs_provider_ipathverbs\n+verbs_provider_ipathverbs in ipathverbs.c.o\n \n verbs.c.o:\n 0000000000000000 r .LC0\n U __errno_location\n U __snprintf_chk\n U __stack_chk_fail\n U free\n@@ -150,7 +93,64 @@\n 0000000000000100 T rdmacore52_0_ipath_query_device\n 00000000000001a0 T rdmacore52_0_ipath_query_port\n 00000000000009a0 T rdmacore52_0_ipath_query_qp\n 0000000000000f70 T rdmacore52_0_ipath_query_srq\n 00000000000002b0 T rdmacore52_0_ipath_reg_mr\n 0000000000000520 T rdmacore52_0_ipath_resize_cq\n 0000000000000620 T rdmacore52_0_ipath_resize_cq_v1\n+\n+ipathverbs.c.o:\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t drv__register_driver\n+ U free\n+0000000000000000 r hca_table\n+0000000000000060 t ipath_alloc_context\n+0000000000000260 d ipath_ctx_common_ops\n+0000000000000000 d ipath_ctx_v1_ops\n+0000000000000000 d ipath_dev_ops\n+0000000000000010 t ipath_device_alloc\n+0000000000000040 t ipath_free_context\n+0000000000000000 t ipath_uninit_device\n+ U rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_ibv_cmd_attach_mcast\n+ U rdmacore52_0_ibv_cmd_detach_mcast\n+ U rdmacore52_0_ibv_cmd_get_context\n+ U rdmacore52_0_ibv_cmd_poll_cq\n+ U rdmacore52_0_ibv_cmd_post_recv\n+ U rdmacore52_0_ibv_cmd_post_srq_recv\n+ U rdmacore52_0_ibv_cmd_req_notify_cq\n+ U rdmacore52_0_ipath_alloc_pd\n+ U rdmacore52_0_ipath_create_ah\n+ U rdmacore52_0_ipath_create_cq\n+ U rdmacore52_0_ipath_create_cq_v1\n+ U rdmacore52_0_ipath_create_qp\n+ U rdmacore52_0_ipath_create_qp_v1\n+ U rdmacore52_0_ipath_create_srq\n+ U rdmacore52_0_ipath_create_srq_v1\n+ U rdmacore52_0_ipath_dereg_mr\n+ U rdmacore52_0_ipath_destroy_ah\n+ U rdmacore52_0_ipath_destroy_cq\n+ U rdmacore52_0_ipath_destroy_cq_v1\n+ U rdmacore52_0_ipath_destroy_qp\n+ U rdmacore52_0_ipath_destroy_qp_v1\n+ U rdmacore52_0_ipath_destroy_srq\n+ U rdmacore52_0_ipath_destroy_srq_v1\n+ U rdmacore52_0_ipath_free_pd\n+ U rdmacore52_0_ipath_modify_qp\n+ U rdmacore52_0_ipath_modify_srq\n+ U rdmacore52_0_ipath_modify_srq_v1\n+ U rdmacore52_0_ipath_poll_cq\n+ U rdmacore52_0_ipath_post_recv\n+ U rdmacore52_0_ipath_post_send\n+ U rdmacore52_0_ipath_post_srq_recv\n+ U rdmacore52_0_ipath_query_device\n+ U rdmacore52_0_ipath_query_port\n+ U rdmacore52_0_ipath_query_qp\n+ U rdmacore52_0_ipath_query_srq\n+ U rdmacore52_0_ipath_reg_mr\n+ U rdmacore52_0_ipath_resize_cq\n+ U rdmacore52_0_ipath_resize_cq_v1\n+ U rdmacore52_0_verbs_register_driver_34\n+ U rdmacore52_0_verbs_set_ops\n+ U rdmacore52_0_verbs_uninit_context\n+0000000000000000 D verbs_provider_ipathverbs\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n ---------- 0 0 0 1092 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 8264 1970-01-01 00:00:00.000000 ipathverbs.c.o\n ?rw-r--r-- 0 0 0 13736 1970-01-01 00:00:00.000000 verbs.c.o\n+?rw-r--r-- 0 0 0 8264 1970-01-01 00:00:00.000000 ipathverbs.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libirdma-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libirdma-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,38 +1,9 @@\n \n Archive index:\n-rdmacore52_0_irdma_clr_wqes in uk.c.o\n-rdmacore52_0_irdma_uk_qp_post_wr in uk.c.o\n-rdmacore52_0_irdma_qp_push_wqe in uk.c.o\n-rdmacore52_0_irdma_qp_get_next_send_wqe in uk.c.o\n-rdmacore52_0_irdma_qp_get_next_recv_wqe in uk.c.o\n-rdmacore52_0_irdma_uk_rdma_write in uk.c.o\n-rdmacore52_0_irdma_uk_rdma_read in uk.c.o\n-rdmacore52_0_irdma_uk_send in uk.c.o\n-rdmacore52_0_irdma_uk_inline_rdma_write in uk.c.o\n-rdmacore52_0_irdma_uk_inline_send in uk.c.o\n-rdmacore52_0_irdma_uk_stag_local_invalidate in uk.c.o\n-rdmacore52_0_irdma_uk_mw_bind in uk.c.o\n-rdmacore52_0_irdma_uk_post_receive in uk.c.o\n-rdmacore52_0_irdma_uk_cq_resize in uk.c.o\n-rdmacore52_0_irdma_uk_cq_set_resized_cnt in uk.c.o\n-rdmacore52_0_irdma_uk_cq_request_notification in uk.c.o\n-rdmacore52_0_irdma_uk_cq_poll_cmpl in uk.c.o\n-rdmacore52_0_irdma_get_wqe_shift in uk.c.o\n-rdmacore52_0_irdma_get_sqdepth in uk.c.o\n-rdmacore52_0_irdma_get_rqdepth in uk.c.o\n-rdmacore52_0_irdma_uk_calc_depth_shift_sq in uk.c.o\n-rdmacore52_0_irdma_uk_calc_depth_shift_rq in uk.c.o\n-rdmacore52_0_irdma_uk_qp_init in uk.c.o\n-rdmacore52_0_irdma_uk_cq_init in uk.c.o\n-rdmacore52_0_irdma_uk_clean_cq in uk.c.o\n-rdmacore52_0_irdma_nop in uk.c.o\n-rdmacore52_0_irdma_fragcnt_to_quanta_sq in uk.c.o\n-rdmacore52_0_irdma_fragcnt_to_wqesize_rq in uk.c.o\n-verbs_provider_irdma in umain.c.o\n rdmacore52_0_irdma_uquery_device_ex in uverbs.c.o\n rdmacore52_0_irdma_uquery_port in uverbs.c.o\n rdmacore52_0_irdma_ualloc_pd in uverbs.c.o\n rdmacore52_0_irdma_ufree_pd in uverbs.c.o\n rdmacore52_0_irdma_ureg_mr in uverbs.c.o\n rdmacore52_0_irdma_ureg_mr_dmabuf in uverbs.c.o\n rdmacore52_0_irdma_urereg_mr in uverbs.c.o\n@@ -56,108 +27,43 @@\n rdmacore52_0_irdma_ubind_mw in uverbs.c.o\n rdmacore52_0_irdma_upost_recv in uverbs.c.o\n rdmacore52_0_irdma_ucreate_ah in uverbs.c.o\n rdmacore52_0_irdma_udestroy_ah in uverbs.c.o\n rdmacore52_0_irdma_uattach_mcast in uverbs.c.o\n rdmacore52_0_irdma_udetach_mcast in uverbs.c.o\n rdmacore52_0_irdma_uresize_cq in uverbs.c.o\n-\n-uk.c.o:\n- U __stack_chk_fail\n-0000000000000070 t irdma_copy_inline_data\n-0000000000000170 t irdma_copy_inline_data_gen_1\n-0000000000000014 t irdma_fragcnt_to_quanta_sq.cold\n-00000000000002c0 t irdma_inline_data_size_to_quanta\n-0000000000000030 t irdma_inline_data_size_to_quanta_gen_1\n-0000000000000220 t irdma_set_fragment\n-0000000000000280 t irdma_set_fragment_gen_1\n-0000000000000040 t irdma_set_mw_bind_wqe\n-0000000000000000 t irdma_set_mw_bind_wqe_gen_1\n-0000000000000000 t irdma_uk_rdma_write.cold\n-000000000000000a t irdma_uk_send.cold\n- U memcpy\n-0000000000000320 T rdmacore52_0_irdma_clr_wqes\n-0000000000003130 T rdmacore52_0_irdma_fragcnt_to_quanta_sq\n-00000000000031d0 T rdmacore52_0_irdma_fragcnt_to_wqesize_rq\n-00000000000029a0 T rdmacore52_0_irdma_get_rqdepth\n-0000000000002940 T rdmacore52_0_irdma_get_sqdepth\n-00000000000028c0 T rdmacore52_0_irdma_get_wqe_shift\n-0000000000002f90 T rdmacore52_0_irdma_nop\n-00000000000006c0 T rdmacore52_0_irdma_qp_get_next_recv_wqe\n-0000000000000440 T rdmacore52_0_irdma_qp_get_next_send_wqe\n-00000000000003b0 T rdmacore52_0_irdma_qp_push_wqe\n-0000000000002b10 T rdmacore52_0_irdma_uk_calc_depth_shift_rq\n-0000000000002a00 T rdmacore52_0_irdma_uk_calc_depth_shift_sq\n-0000000000002e60 T rdmacore52_0_irdma_uk_clean_cq\n-0000000000002e00 T rdmacore52_0_irdma_uk_cq_init\n-0000000000002270 T rdmacore52_0_irdma_uk_cq_poll_cmpl\n-0000000000002220 T rdmacore52_0_irdma_uk_cq_request_notification\n-00000000000021d0 T rdmacore52_0_irdma_uk_cq_resize\n-00000000000021f0 T rdmacore52_0_irdma_uk_cq_set_resized_cnt\n-00000000000015a0 T rdmacore52_0_irdma_uk_inline_rdma_write\n-0000000000001880 T rdmacore52_0_irdma_uk_inline_send\n-0000000000001dd0 T rdmacore52_0_irdma_uk_mw_bind\n-0000000000002010 T rdmacore52_0_irdma_uk_post_receive\n-0000000000002c10 T rdmacore52_0_irdma_uk_qp_init\n-0000000000000390 T rdmacore52_0_irdma_uk_qp_post_wr\n-0000000000000c00 T rdmacore52_0_irdma_uk_rdma_read\n-0000000000000740 T rdmacore52_0_irdma_uk_rdma_write\n-0000000000001070 T rdmacore52_0_irdma_uk_send\n-0000000000001ba0 T rdmacore52_0_irdma_uk_stag_local_invalidate\n-\n-umain.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t drv__register_driver\n- U free\n-0000000000000000 r hca_table\n-0000000000000010 t irdma_device_alloc\n-0000000000000030 t irdma_ualloc_context\n-0000000000000000 d irdma_uctx_ops\n-0000000000000000 d irdma_udev_ops\n-0000000000000270 t irdma_ufree_context\n-0000000000000000 t irdma_uninit_device\n- U rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_ibv_cmd_get_context\n- U rdmacore52_0_irdma_cq_event\n- U rdmacore52_0_irdma_mmap\n- U rdmacore52_0_irdma_munmap\n- U rdmacore52_0_irdma_ualloc_mw\n- U rdmacore52_0_irdma_ualloc_pd\n- U rdmacore52_0_irdma_uarm_cq\n- U rdmacore52_0_irdma_uattach_mcast\n- U rdmacore52_0_irdma_ubind_mw\n- U rdmacore52_0_irdma_ucreate_ah\n- U rdmacore52_0_irdma_ucreate_cq\n- U rdmacore52_0_irdma_ucreate_cq_ex\n- U rdmacore52_0_irdma_ucreate_qp\n- U rdmacore52_0_irdma_udealloc_mw\n- U rdmacore52_0_irdma_udereg_mr\n- U rdmacore52_0_irdma_udestroy_ah\n- U rdmacore52_0_irdma_udestroy_cq\n- U rdmacore52_0_irdma_udestroy_qp\n- U rdmacore52_0_irdma_udetach_mcast\n- U rdmacore52_0_irdma_ufree_pd\n- U rdmacore52_0_irdma_umodify_qp\n- U rdmacore52_0_irdma_upoll_cq\n- U rdmacore52_0_irdma_upost_recv\n- U rdmacore52_0_irdma_upost_send\n- U rdmacore52_0_irdma_uquery_device_ex\n- U rdmacore52_0_irdma_uquery_port\n- U rdmacore52_0_irdma_uquery_qp\n- U rdmacore52_0_irdma_ureg_mr\n- U rdmacore52_0_irdma_ureg_mr_dmabuf\n- U rdmacore52_0_irdma_urereg_mr\n- U rdmacore52_0_irdma_uresize_cq\n- U rdmacore52_0_verbs_register_driver_34\n- U rdmacore52_0_verbs_set_ops\n- U rdmacore52_0_verbs_uninit_context\n-0000000000000000 D verbs_provider_irdma\n+rdmacore52_0_irdma_clr_wqes in uk.c.o\n+rdmacore52_0_irdma_uk_qp_post_wr in uk.c.o\n+rdmacore52_0_irdma_qp_push_wqe in uk.c.o\n+rdmacore52_0_irdma_qp_get_next_send_wqe in uk.c.o\n+rdmacore52_0_irdma_qp_get_next_recv_wqe in uk.c.o\n+rdmacore52_0_irdma_uk_rdma_write in uk.c.o\n+rdmacore52_0_irdma_uk_rdma_read in uk.c.o\n+rdmacore52_0_irdma_uk_send in uk.c.o\n+rdmacore52_0_irdma_uk_inline_rdma_write in uk.c.o\n+rdmacore52_0_irdma_uk_inline_send in uk.c.o\n+rdmacore52_0_irdma_uk_stag_local_invalidate in uk.c.o\n+rdmacore52_0_irdma_uk_mw_bind in uk.c.o\n+rdmacore52_0_irdma_uk_post_receive in uk.c.o\n+rdmacore52_0_irdma_uk_cq_resize in uk.c.o\n+rdmacore52_0_irdma_uk_cq_set_resized_cnt in uk.c.o\n+rdmacore52_0_irdma_uk_cq_request_notification in uk.c.o\n+rdmacore52_0_irdma_uk_cq_poll_cmpl in uk.c.o\n+rdmacore52_0_irdma_get_wqe_shift in uk.c.o\n+rdmacore52_0_irdma_get_sqdepth in uk.c.o\n+rdmacore52_0_irdma_get_rqdepth in uk.c.o\n+rdmacore52_0_irdma_uk_calc_depth_shift_sq in uk.c.o\n+rdmacore52_0_irdma_uk_calc_depth_shift_rq in uk.c.o\n+rdmacore52_0_irdma_uk_qp_init in uk.c.o\n+rdmacore52_0_irdma_uk_cq_init in uk.c.o\n+rdmacore52_0_irdma_uk_clean_cq in uk.c.o\n+rdmacore52_0_irdma_nop in uk.c.o\n+rdmacore52_0_irdma_fragcnt_to_quanta_sq in uk.c.o\n+rdmacore52_0_irdma_fragcnt_to_wqesize_rq in uk.c.o\n+verbs_provider_irdma in umain.c.o\n \n uverbs.c.o:\n 0000000000000000 r .LC0\n 00000000000000e0 r CSWTCH.35\n U __errno_location\n 0000000000000500 t __irdma_upoll_cq.constprop.0\n U __snprintf_chk\n@@ -262,7 +168,101 @@\n 0000000000002520 T rdmacore52_0_irdma_uquery_qp\n 0000000000000a70 T rdmacore52_0_irdma_ureg_mr\n 0000000000000b40 T rdmacore52_0_irdma_ureg_mr_dmabuf\n 0000000000000be0 T rdmacore52_0_irdma_urereg_mr\n 00000000000030e0 T rdmacore52_0_irdma_uresize_cq\n U sysconf\n 0000000000001710 t ucreate_cq\n+\n+uk.c.o:\n+ U __stack_chk_fail\n+0000000000000070 t irdma_copy_inline_data\n+0000000000000170 t irdma_copy_inline_data_gen_1\n+0000000000000014 t irdma_fragcnt_to_quanta_sq.cold\n+00000000000002c0 t irdma_inline_data_size_to_quanta\n+0000000000000030 t irdma_inline_data_size_to_quanta_gen_1\n+0000000000000220 t irdma_set_fragment\n+0000000000000280 t irdma_set_fragment_gen_1\n+0000000000000040 t irdma_set_mw_bind_wqe\n+0000000000000000 t irdma_set_mw_bind_wqe_gen_1\n+0000000000000000 t irdma_uk_rdma_write.cold\n+000000000000000a t irdma_uk_send.cold\n+ U memcpy\n+0000000000000320 T rdmacore52_0_irdma_clr_wqes\n+0000000000003130 T rdmacore52_0_irdma_fragcnt_to_quanta_sq\n+00000000000031d0 T rdmacore52_0_irdma_fragcnt_to_wqesize_rq\n+00000000000029a0 T rdmacore52_0_irdma_get_rqdepth\n+0000000000002940 T rdmacore52_0_irdma_get_sqdepth\n+00000000000028c0 T rdmacore52_0_irdma_get_wqe_shift\n+0000000000002f90 T rdmacore52_0_irdma_nop\n+00000000000006c0 T rdmacore52_0_irdma_qp_get_next_recv_wqe\n+0000000000000440 T rdmacore52_0_irdma_qp_get_next_send_wqe\n+00000000000003b0 T rdmacore52_0_irdma_qp_push_wqe\n+0000000000002b10 T rdmacore52_0_irdma_uk_calc_depth_shift_rq\n+0000000000002a00 T rdmacore52_0_irdma_uk_calc_depth_shift_sq\n+0000000000002e60 T rdmacore52_0_irdma_uk_clean_cq\n+0000000000002e00 T rdmacore52_0_irdma_uk_cq_init\n+0000000000002270 T rdmacore52_0_irdma_uk_cq_poll_cmpl\n+0000000000002220 T rdmacore52_0_irdma_uk_cq_request_notification\n+00000000000021d0 T rdmacore52_0_irdma_uk_cq_resize\n+00000000000021f0 T rdmacore52_0_irdma_uk_cq_set_resized_cnt\n+00000000000015a0 T rdmacore52_0_irdma_uk_inline_rdma_write\n+0000000000001880 T rdmacore52_0_irdma_uk_inline_send\n+0000000000001dd0 T rdmacore52_0_irdma_uk_mw_bind\n+0000000000002010 T rdmacore52_0_irdma_uk_post_receive\n+0000000000002c10 T rdmacore52_0_irdma_uk_qp_init\n+0000000000000390 T rdmacore52_0_irdma_uk_qp_post_wr\n+0000000000000c00 T rdmacore52_0_irdma_uk_rdma_read\n+0000000000000740 T rdmacore52_0_irdma_uk_rdma_write\n+0000000000001070 T rdmacore52_0_irdma_uk_send\n+0000000000001ba0 T rdmacore52_0_irdma_uk_stag_local_invalidate\n+\n+umain.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t drv__register_driver\n+ U free\n+0000000000000000 r hca_table\n+0000000000000010 t irdma_device_alloc\n+0000000000000030 t irdma_ualloc_context\n+0000000000000000 d irdma_uctx_ops\n+0000000000000000 d irdma_udev_ops\n+0000000000000270 t irdma_ufree_context\n+0000000000000000 t irdma_uninit_device\n+ U rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_ibv_cmd_get_context\n+ U rdmacore52_0_irdma_cq_event\n+ U rdmacore52_0_irdma_mmap\n+ U rdmacore52_0_irdma_munmap\n+ U rdmacore52_0_irdma_ualloc_mw\n+ U rdmacore52_0_irdma_ualloc_pd\n+ U rdmacore52_0_irdma_uarm_cq\n+ U rdmacore52_0_irdma_uattach_mcast\n+ U rdmacore52_0_irdma_ubind_mw\n+ U rdmacore52_0_irdma_ucreate_ah\n+ U rdmacore52_0_irdma_ucreate_cq\n+ U rdmacore52_0_irdma_ucreate_cq_ex\n+ U rdmacore52_0_irdma_ucreate_qp\n+ U rdmacore52_0_irdma_udealloc_mw\n+ U rdmacore52_0_irdma_udereg_mr\n+ U rdmacore52_0_irdma_udestroy_ah\n+ U rdmacore52_0_irdma_udestroy_cq\n+ U rdmacore52_0_irdma_udestroy_qp\n+ U rdmacore52_0_irdma_udetach_mcast\n+ U rdmacore52_0_irdma_ufree_pd\n+ U rdmacore52_0_irdma_umodify_qp\n+ U rdmacore52_0_irdma_upoll_cq\n+ U rdmacore52_0_irdma_upost_recv\n+ U rdmacore52_0_irdma_upost_send\n+ U rdmacore52_0_irdma_uquery_device_ex\n+ U rdmacore52_0_irdma_uquery_port\n+ U rdmacore52_0_irdma_uquery_qp\n+ U rdmacore52_0_irdma_ureg_mr\n+ U rdmacore52_0_irdma_ureg_mr_dmabuf\n+ U rdmacore52_0_irdma_urereg_mr\n+ U rdmacore52_0_irdma_uresize_cq\n+ U rdmacore52_0_verbs_register_driver_34\n+ U rdmacore52_0_verbs_set_ops\n+ U rdmacore52_0_verbs_uninit_context\n+0000000000000000 D verbs_provider_irdma\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,4 +1,4 @@\n ---------- 0 0 0 2180 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 31424 1970-01-01 00:00:00.000000 uverbs.c.o\n ?rw-r--r-- 0 0 0 21944 1970-01-01 00:00:00.000000 uk.c.o\n ?rw-r--r-- 0 0 0 8480 1970-01-01 00:00:00.000000 umain.c.o\n-?rw-r--r-- 0 0 0 31424 1970-01-01 00:00:00.000000 uverbs.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libmana.a", "source2": "./usr/lib/x86_64-linux-gnu/libmana.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,9 +1,15 @@\n \n Archive index:\n+manadv_set_context_attr in manadv.c.o\n+manadv_init_obj in manadv.c.o\n+rdmacore52_0_mana_create_qp in qp.c.o\n+rdmacore52_0_mana_modify_qp in qp.c.o\n+rdmacore52_0_mana_destroy_qp in qp.c.o\n+rdmacore52_0_mana_create_qp_ex in qp.c.o\n rdmacore52_0_mana_modify_wq in wq.c.o\n rdmacore52_0_mana_create_wq in wq.c.o\n rdmacore52_0_mana_destroy_wq in wq.c.o\n rdmacore52_0_mana_create_rwq_ind_table in wq.c.o\n rdmacore52_0_mana_destroy_rwq_ind_table in wq.c.o\n rdmacore52_0_mana_query_device_ex in mana.c.o\n rdmacore52_0_mana_query_port in mana.c.o\n@@ -12,20 +18,58 @@\n rdmacore52_0_mana_dealloc_pd in mana.c.o\n rdmacore52_0_mana_reg_mr in mana.c.o\n rdmacore52_0_mana_create_cq in mana.c.o\n rdmacore52_0_mana_destroy_cq in mana.c.o\n rdmacore52_0_mana_dereg_mr in mana.c.o\n rdmacore52_0_to_mctx in mana.c.o\n verbs_provider_mana in mana.c.o\n-rdmacore52_0_mana_create_qp in qp.c.o\n-rdmacore52_0_mana_modify_qp in qp.c.o\n-rdmacore52_0_mana_destroy_qp in qp.c.o\n-rdmacore52_0_mana_create_qp_ex in qp.c.o\n-manadv_set_context_attr in manadv.c.o\n-manadv_init_obj in manadv.c.o\n+\n+manadv.c.o:\n+0000000000000000 r .LC0\n+ U __errno_location\n+0000000000000000 r __func__.0\n+00000000000000b0 T manadv_init_obj\n+0000000000000000 T manadv_set_context_attr\n+0000000000000000 t manadv_set_context_attr.cold\n+ U rdmacore52_0___verbs_log\n+ U rdmacore52_0_to_mctx\n+\n+qp.c.o:\n+0000000000000000 r .LC0\n+0000000000000038 r .LC1\n+000000000000001d r .LC10\n+0000000000000060 r .LC2\n+0000000000000080 r .LC4\n+00000000000000b8 r .LC5\n+0000000000000000 r .LC6\n+00000000000000f0 r .LC7\n+0000000000000118 r .LC9\n+ U __errno_location\n+0000000000000000 r __func__.0\n+0000000000000020 r __func__.1\n+0000000000000040 r __func__.2\n+0000000000000050 r __func__.3\n+0000000000000068 r __func__.4\n+ U __stack_chk_fail\n+ U calloc\n+ U free\n+0000000000000014 t mana_create_qp.cold\n+0000000000000046 t mana_create_qp_ex.cold\n+0000000000000000 t mana_create_qp_ex_raw\n+0000000000000000 t mana_create_qp_ex_raw.cold\n+0000000000000032 t mana_destroy_qp.cold\n+ U rdmacore52_0___verbs_log\n+ U rdmacore52_0_ibv_cmd_create_qp\n+ U rdmacore52_0_ibv_cmd_create_qp_ex2\n+ U rdmacore52_0_ibv_cmd_destroy_qp\n+0000000000000280 T rdmacore52_0_mana_create_qp\n+0000000000000730 T rdmacore52_0_mana_create_qp_ex\n+0000000000000610 T rdmacore52_0_mana_destroy_qp\n+0000000000000600 T rdmacore52_0_mana_modify_qp\n+ U rdmacore52_0_to_mctx\n \n wq.c.o:\n 0000000000000000 r .LC0\n 0000000000000038 r .LC1\n 0000000000000058 r .LC3\n 0000000000000088 r .LC4\n 00000000000000b0 r .LC6\n@@ -133,51 +177,7 @@\n 0000000000000100 T rdmacore52_0_mana_query_port\n 00000000000003c0 T rdmacore52_0_mana_reg_mr\n 0000000000000a70 T rdmacore52_0_to_mctx\n U rdmacore52_0_verbs_register_driver_34\n U rdmacore52_0_verbs_set_ops\n U rdmacore52_0_verbs_uninit_context\n 0000000000000000 D verbs_provider_mana\n-\n-qp.c.o:\n-0000000000000000 r .LC0\n-0000000000000038 r .LC1\n-000000000000001d r .LC10\n-0000000000000060 r .LC2\n-0000000000000080 r .LC4\n-00000000000000b8 r .LC5\n-0000000000000000 r .LC6\n-00000000000000f0 r .LC7\n-0000000000000118 r .LC9\n- U __errno_location\n-0000000000000000 r __func__.0\n-0000000000000020 r __func__.1\n-0000000000000040 r __func__.2\n-0000000000000050 r __func__.3\n-0000000000000068 r __func__.4\n- U __stack_chk_fail\n- U calloc\n- U free\n-0000000000000014 t mana_create_qp.cold\n-0000000000000046 t mana_create_qp_ex.cold\n-0000000000000000 t mana_create_qp_ex_raw\n-0000000000000000 t mana_create_qp_ex_raw.cold\n-0000000000000032 t mana_destroy_qp.cold\n- U rdmacore52_0___verbs_log\n- U rdmacore52_0_ibv_cmd_create_qp\n- U rdmacore52_0_ibv_cmd_create_qp_ex2\n- U rdmacore52_0_ibv_cmd_destroy_qp\n-0000000000000280 T rdmacore52_0_mana_create_qp\n-0000000000000730 T rdmacore52_0_mana_create_qp_ex\n-0000000000000610 T rdmacore52_0_mana_destroy_qp\n-0000000000000600 T rdmacore52_0_mana_modify_qp\n- U rdmacore52_0_to_mctx\n-\n-manadv.c.o:\n-0000000000000000 r .LC0\n- U __errno_location\n-0000000000000000 r __func__.0\n-00000000000000b0 T manadv_init_obj\n-0000000000000000 T manadv_set_context_attr\n-0000000000000000 t manadv_set_context_attr.cold\n- U rdmacore52_0___verbs_log\n- U rdmacore52_0_to_mctx\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,5 +1,5 @@\n ---------- 0 0 0 720 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 2664 1970-01-01 00:00:00.000000 manadv.c.o\n+?rw-r--r-- 0 0 0 7304 1970-01-01 00:00:00.000000 qp.c.o\n ?rw-r--r-- 0 0 0 6464 1970-01-01 00:00:00.000000 wq.c.o\n ?rw-r--r-- 0 0 0 14944 1970-01-01 00:00:00.000000 mana.c.o\n-?rw-r--r-- 0 0 0 7304 1970-01-01 00:00:00.000000 qp.c.o\n-?rw-r--r-- 0 0 0 2664 1970-01-01 00:00:00.000000 manadv.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libmlx4.a", "source2": "./usr/lib/x86_64-linux-gnu/libmlx4.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,28 +1,35 @@\n \n Archive index:\n+rdmacore52_0_mlx4_poll_cq in cq.c.o\n+rdmacore52_0_mlx4_cq_fill_pfns in cq.c.o\n+rdmacore52_0_mlx4_arm_cq in cq.c.o\n+rdmacore52_0_mlx4_cq_event in cq.c.o\n+rdmacore52_0___mlx4_cq_clean in cq.c.o\n+rdmacore52_0_mlx4_cq_clean in cq.c.o\n+rdmacore52_0_mlx4_get_outstanding_cqes in cq.c.o\n+rdmacore52_0_mlx4_cq_resize_copy_cqes in cq.c.o\n+rdmacore52_0_mlx4_alloc_cq_buf in cq.c.o\n rdmacore52_0_mlx4_alloc_db in dbrec.c.o\n rdmacore52_0_mlx4_free_db in dbrec.c.o\n-rdmacore52_0_mlx4_alloc_buf in buf.c.o\n-rdmacore52_0_mlx4_free_buf in buf.c.o\n-mlx4dv_init_obj in mlx4.c.o\n-mlx4dv_query_device in mlx4.c.o\n-mlx4dv_set_context_attr in mlx4.c.o\n-verbs_provider_mlx4 in mlx4.c.o\n rdmacore52_0_mlx4_init_qp_indices in qp.c.o\n rdmacore52_0_mlx4_qp_init_sq_ownership in qp.c.o\n rdmacore52_0_mlx4_post_send in qp.c.o\n rdmacore52_0_mlx4_post_recv in qp.c.o\n rdmacore52_0_mlx4_post_wq_recv in qp.c.o\n rdmacore52_0_mlx4_calc_sq_wqe_size in qp.c.o\n rdmacore52_0_mlx4_alloc_qp_buf in qp.c.o\n rdmacore52_0_mlx4_set_sq_sizes in qp.c.o\n rdmacore52_0_mlx4_find_qp in qp.c.o\n rdmacore52_0_mlx4_store_qp in qp.c.o\n rdmacore52_0_mlx4_clear_qp in qp.c.o\n+mlx4dv_init_obj in mlx4.c.o\n+mlx4dv_query_device in mlx4.c.o\n+mlx4dv_set_context_attr in mlx4.c.o\n+verbs_provider_mlx4 in mlx4.c.o\n rdmacore52_0_mlx4_free_srq_wqe in srq.c.o\n rdmacore52_0_mlx4_post_srq_recv in srq.c.o\n rdmacore52_0_mlx4_alloc_srq_buf in srq.c.o\n rdmacore52_0_mlx4_init_xsrq_table in srq.c.o\n rdmacore52_0_mlx4_find_xsrq in srq.c.o\n rdmacore52_0_mlx4_store_xsrq in srq.c.o\n rdmacore52_0_mlx4_clear_xsrq in srq.c.o\n@@ -65,44 +72,91 @@\n rdmacore52_0_mlx4_modify_wq in verbs.c.o\n rdmacore52_0_mlx4_create_flow in verbs.c.o\n rdmacore52_0_mlx4_destroy_flow in verbs.c.o\n rdmacore52_0_mlx4_destroy_wq in verbs.c.o\n rdmacore52_0_mlx4_create_rwq_ind_table in verbs.c.o\n rdmacore52_0_mlx4_destroy_rwq_ind_table in verbs.c.o\n rdmacore52_0_mlx4_modify_cq in verbs.c.o\n-rdmacore52_0_mlx4_poll_cq in cq.c.o\n-rdmacore52_0_mlx4_cq_fill_pfns in cq.c.o\n-rdmacore52_0_mlx4_arm_cq in cq.c.o\n-rdmacore52_0_mlx4_cq_event in cq.c.o\n-rdmacore52_0___mlx4_cq_clean in cq.c.o\n-rdmacore52_0_mlx4_cq_clean in cq.c.o\n-rdmacore52_0_mlx4_get_outstanding_cqes in cq.c.o\n-rdmacore52_0_mlx4_cq_resize_copy_cqes in cq.c.o\n-rdmacore52_0_mlx4_alloc_cq_buf in cq.c.o\n+rdmacore52_0_mlx4_alloc_buf in buf.c.o\n+rdmacore52_0_mlx4_free_buf in buf.c.o\n+\n+cq.c.o:\n+0000000000000000 r .LC0\n+00000000000000c0 r CSWTCH.35\n+0000000000000080 r CSWTCH.43\n+ U __printf_chk\n+ U __stack_chk_fail\n+ U memcpy\n+ U memset\n+00000000000001c0 t mlx4_cq_read_wc_byte_len\n+0000000000000130 t mlx4_cq_read_wc_completion_ts\n+00000000000000a0 t mlx4_cq_read_wc_dlid_path_bits\n+00000000000001e0 t mlx4_cq_read_wc_flags\n+00000000000001a0 t mlx4_cq_read_wc_imm_data\n+0000000000000000 t mlx4_cq_read_wc_opcode\n+0000000000000180 t mlx4_cq_read_wc_qp_num\n+0000000000000060 t mlx4_cq_read_wc_sl\n+00000000000000c0 t mlx4_cq_read_wc_slid\n+0000000000000160 t mlx4_cq_read_wc_src_qp\n+0000000000000050 t mlx4_cq_read_wc_vendor_err\n+0000000000000110 t mlx4_end_poll\n+00000000000000e0 t mlx4_end_poll_lock\n+0000000000000600 t mlx4_next_poll\n+0000000000000920 t mlx4_start_poll\n+0000000000000270 t mlx4_start_poll_lock\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+0000000000001390 T rdmacore52_0___mlx4_cq_clean\n+ U rdmacore52_0_mlx4_alloc_buf\n+00000000000018b0 T rdmacore52_0_mlx4_alloc_cq_buf\n+0000000000001310 T rdmacore52_0_mlx4_arm_cq\n+0000000000001690 T rdmacore52_0_mlx4_cq_clean\n+0000000000001380 T rdmacore52_0_mlx4_cq_event\n+0000000000001200 T rdmacore52_0_mlx4_cq_fill_pfns\n+00000000000017b0 T rdmacore52_0_mlx4_cq_resize_copy_cqes\n+ U rdmacore52_0_mlx4_find_qp\n+ U rdmacore52_0_mlx4_find_xsrq\n+ U rdmacore52_0_mlx4_free_srq_wqe\n+00000000000016e0 T rdmacore52_0_mlx4_get_outstanding_cqes\n+0000000000000c70 T rdmacore52_0_mlx4_poll_cq\n \n dbrec.c.o:\n 0000000000000000 r db_size\n U free\n U malloc\n U memset\n U pthread_mutex_lock\n U pthread_mutex_unlock\n U rdmacore52_0_mlx4_alloc_buf\n 0000000000000000 T rdmacore52_0_mlx4_alloc_db\n U rdmacore52_0_mlx4_free_buf\n 00000000000001c0 T rdmacore52_0_mlx4_free_db\n \n-buf.c.o:\n- U __errno_location\n- U ibv_dofork_range\n- U ibv_dontfork_range\n- U mmap\n- U munmap\n-0000000000000000 T rdmacore52_0_mlx4_alloc_buf\n-0000000000000120 T rdmacore52_0_mlx4_free_buf\n+qp.c.o:\n+0000000000000000 r .LC0\n+ U calloc\n+ U free\n+ U malloc\n+ U memcpy\n+ U memset\n+0000000000000040 r mlx4_ib_opcode\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_mlx4_alloc_buf\n+0000000000001410 T rdmacore52_0_mlx4_alloc_qp_buf\n+00000000000012a0 T rdmacore52_0_mlx4_calc_sq_wqe_size\n+0000000000001760 T rdmacore52_0_mlx4_clear_qp\n+0000000000001680 T rdmacore52_0_mlx4_find_qp\n+0000000000000000 T rdmacore52_0_mlx4_init_qp_indices\n+0000000000000ec0 T rdmacore52_0_mlx4_post_recv\n+0000000000000210 T rdmacore52_0_mlx4_post_send\n+00000000000010a0 T rdmacore52_0_mlx4_post_wq_recv\n+0000000000000020 T rdmacore52_0_mlx4_qp_init_sq_ownership\n+0000000000001600 T rdmacore52_0_mlx4_set_sq_sizes\n+00000000000016d0 T rdmacore52_0_mlx4_store_qp\n \n mlx4.c.o:\n 0000000000000000 r .LC0\n U __stack_chk_fail\n U calloc\n 0000000000000000 t drv__register_driver\n U free\n@@ -175,37 +229,14 @@\n U rdmacore52_0_verbs_register_driver_34\n U rdmacore52_0_verbs_set_ops\n U rdmacore52_0_verbs_uninit_context\n U stderr\n U sysconf\n 0000000000000000 D verbs_provider_mlx4\n \n-qp.c.o:\n-0000000000000000 r .LC0\n- U calloc\n- U free\n- U malloc\n- U memcpy\n- U memset\n-0000000000000040 r mlx4_ib_opcode\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_mlx4_alloc_buf\n-0000000000001410 T rdmacore52_0_mlx4_alloc_qp_buf\n-00000000000012a0 T rdmacore52_0_mlx4_calc_sq_wqe_size\n-0000000000001760 T rdmacore52_0_mlx4_clear_qp\n-0000000000001680 T rdmacore52_0_mlx4_find_qp\n-0000000000000000 T rdmacore52_0_mlx4_init_qp_indices\n-0000000000000ec0 T rdmacore52_0_mlx4_post_recv\n-0000000000000210 T rdmacore52_0_mlx4_post_send\n-00000000000010a0 T rdmacore52_0_mlx4_post_wq_recv\n-0000000000000020 T rdmacore52_0_mlx4_qp_init_sq_ownership\n-0000000000001600 T rdmacore52_0_mlx4_set_sq_sizes\n-00000000000016d0 T rdmacore52_0_mlx4_store_qp\n-\n srq.c.o:\n 0000000000000000 r .LC0\n U __stack_chk_fail\n U calloc\n U free\n U malloc\n U memset\n@@ -347,46 +378,15 @@\n 0000000000000be0 T rdmacore52_0_mlx4_reg_mr\n 0000000000000c90 T rdmacore52_0_mlx4_rereg_mr\n 0000000000001350 T rdmacore52_0_mlx4_resize_cq\n U rdmacore52_0_mlx4_set_sq_sizes\n U rdmacore52_0_mlx4_store_qp\n U stderr\n \n-cq.c.o:\n-0000000000000000 r .LC0\n-00000000000000c0 r CSWTCH.35\n-0000000000000080 r CSWTCH.43\n- U __printf_chk\n- U __stack_chk_fail\n- U memcpy\n- U memset\n-00000000000001c0 t mlx4_cq_read_wc_byte_len\n-0000000000000130 t mlx4_cq_read_wc_completion_ts\n-00000000000000a0 t mlx4_cq_read_wc_dlid_path_bits\n-00000000000001e0 t mlx4_cq_read_wc_flags\n-00000000000001a0 t mlx4_cq_read_wc_imm_data\n-0000000000000000 t mlx4_cq_read_wc_opcode\n-0000000000000180 t mlx4_cq_read_wc_qp_num\n-0000000000000060 t mlx4_cq_read_wc_sl\n-00000000000000c0 t mlx4_cq_read_wc_slid\n-0000000000000160 t mlx4_cq_read_wc_src_qp\n-0000000000000050 t mlx4_cq_read_wc_vendor_err\n-0000000000000110 t mlx4_end_poll\n-00000000000000e0 t mlx4_end_poll_lock\n-0000000000000600 t mlx4_next_poll\n-0000000000000920 t mlx4_start_poll\n-0000000000000270 t mlx4_start_poll_lock\n- U pthread_spin_lock\n- U pthread_spin_unlock\n-0000000000001390 T rdmacore52_0___mlx4_cq_clean\n- U rdmacore52_0_mlx4_alloc_buf\n-00000000000018b0 T rdmacore52_0_mlx4_alloc_cq_buf\n-0000000000001310 T rdmacore52_0_mlx4_arm_cq\n-0000000000001690 T rdmacore52_0_mlx4_cq_clean\n-0000000000001380 T rdmacore52_0_mlx4_cq_event\n-0000000000001200 T rdmacore52_0_mlx4_cq_fill_pfns\n-00000000000017b0 T rdmacore52_0_mlx4_cq_resize_copy_cqes\n- U rdmacore52_0_mlx4_find_qp\n- U rdmacore52_0_mlx4_find_xsrq\n- U rdmacore52_0_mlx4_free_srq_wqe\n-00000000000016e0 T rdmacore52_0_mlx4_get_outstanding_cqes\n-0000000000000c70 T rdmacore52_0_mlx4_poll_cq\n+buf.c.o:\n+ U __errno_location\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U mmap\n+ U munmap\n+0000000000000000 T rdmacore52_0_mlx4_alloc_buf\n+0000000000000120 T rdmacore52_0_mlx4_free_buf\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,8 +1,8 @@\n ---------- 0 0 0 2590 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 13152 1970-01-01 00:00:00.000000 cq.c.o\n ?rw-r--r-- 0 0 0 2736 1970-01-01 00:00:00.000000 dbrec.c.o\n-?rw-r--r-- 0 0 0 2160 1970-01-01 00:00:00.000000 buf.c.o\n-?rw-r--r-- 0 0 0 11264 1970-01-01 00:00:00.000000 mlx4.c.o\n ?rw-r--r-- 0 0 0 10160 1970-01-01 00:00:00.000000 qp.c.o\n+?rw-r--r-- 0 0 0 11264 1970-01-01 00:00:00.000000 mlx4.c.o\n ?rw-r--r-- 0 0 0 6824 1970-01-01 00:00:00.000000 srq.c.o\n ?rw-r--r-- 0 0 0 27472 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 13152 1970-01-01 00:00:00.000000 cq.c.o\n+?rw-r--r-- 0 0 0 2160 1970-01-01 00:00:00.000000 buf.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libmlx5.a", "source2": "./usr/lib/x86_64-linux-gnu/libmlx5.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,148 +1,25 @@\n \n Archive index:\n-rdmacore52_0_dr_devx_query_esw_vport_context in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_gvmi in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_esw_caps in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_device in dr_devx.c.o\n-rdmacore52_0_dr_devx_sync_steering in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_flow_table in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_flow_table in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_always_hit_ft in dr_devx.c.o\n-rdmacore52_0_dr_devx_destroy_always_hit_ft in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_flow_sampler in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_flow_sampler in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_definer in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_reformat_ctx in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_meter in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_meter in dr_devx.c.o\n-rdmacore52_0_dr_devx_modify_meter in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_qp in dr_devx.c.o\n-rdmacore52_0_dr_devx_modify_qp_rst2init in dr_devx.c.o\n-rdmacore52_0_dr_devx_modify_qp_init2rtr in dr_devx.c.o\n-rdmacore52_0_dr_devx_modify_qp_rtr2rts in dr_devx.c.o\n-rdmacore52_0_dr_devx_query_gid in dr_devx.c.o\n-rdmacore52_0_dr_devx_create_modify_header_arg in dr_devx.c.o\n-mlx5dv_dump_dr_domain in dr_dbg.c.o\n-mlx5dv_dump_dr_table in dr_dbg.c.o\n-mlx5dv_dump_dr_matcher in dr_dbg.c.o\n-mlx5dv_dump_dr_rule in dr_dbg.c.o\n-rdmacore52_0_dr_arg_get_object_id in dr_arg.c.o\n-rdmacore52_0_dr_arg_get_obj in dr_arg.c.o\n-rdmacore52_0_dr_arg_put_obj in dr_arg.c.o\n-rdmacore52_0_dr_arg_mngr_create in dr_arg.c.o\n-rdmacore52_0_dr_arg_mngr_destroy in dr_arg.c.o\n-rdmacore52_0_mlx5_alloc_dbrec in dbrec.c.o\n-rdmacore52_0_mlx5_free_db in dbrec.c.o\n-rdmacore52_0_dr_rule_send_update_list in dr_rule.c.o\n-rdmacore52_0_dr_rule_rehash_matcher_s_anchor in dr_rule.c.o\n-rdmacore52_0_dr_rule_set_last_member in dr_rule.c.o\n-rdmacore52_0_dr_rule_get_reverse_rule_members in dr_rule.c.o\n-mlx5dv_dr_rule_create in dr_rule.c.o\n-mlx5dv_dr_rule_destroy in dr_rule.c.o\n-rdmacore52_0_dr_ste_get_ctx_v2 in dr_ste_v2.c.o\n-rdmacore52_0_mlx5_free_buf_extern in buf.c.o\n-rdmacore52_0_mlx5_alloc_buf_extern in buf.c.o\n-rdmacore52_0_mlx5_free_actual_buf in buf.c.o\n-rdmacore52_0_mlx5_is_custom_alloc in buf.c.o\n-rdmacore52_0_mlx5_is_extern_alloc in buf.c.o\n-rdmacore52_0_mlx5_get_alloc_type in buf.c.o\n-rdmacore52_0_mlx5_alloc_buf_contig in buf.c.o\n-rdmacore52_0_mlx5_alloc_prefered_buf in buf.c.o\n-rdmacore52_0_mlx5_free_buf_contig in buf.c.o\n-rdmacore52_0_mlx5_alloc_buf in buf.c.o\n-rdmacore52_0_mlx5_free_buf in buf.c.o\n-mlx5dv_vfio_get_events_fd in mlx5_vfio.c.o\n-mlx5dv_vfio_process_events in mlx5_vfio.c.o\n-mlx5dv_get_vfio_device_list in mlx5_vfio.c.o\n-rdmacore52_0_is_mlx5_vfio_dev in mlx5_vfio.c.o\n-rdmacore52_0_dr_ste_calc_hash_index in dr_ste.c.o\n-rdmacore52_0_dr_ste_conv_bit_to_byte_mask in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_bit_mask in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_miss_addr in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_hit_addr in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_hit_gvmi in dr_ste.c.o\n-rdmacore52_0_dr_ste_get_icm_addr in dr_ste.c.o\n-rdmacore52_0_dr_ste_get_mr_addr in dr_ste.c.o\n-rdmacore52_0_dr_ste_get_miss_list in dr_ste.c.o\n-rdmacore52_0_dr_ste_get_miss_list_top in dr_ste.c.o\n-rdmacore52_0_dr_ste_is_last_in_rule in dr_ste.c.o\n-rdmacore52_0_dr_ste_equal_tag in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl in dr_ste.c.o\n-rdmacore52_0_dr_ste_prepare_for_postsend in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_formated_ste in dr_ste.c.o\n-rdmacore52_0_dr_ste_free in dr_ste.c.o\n-rdmacore52_0_dr_ste_htbl_init_and_postsend in dr_ste.c.o\n-rdmacore52_0_dr_ste_htbl_alloc in dr_ste.c.o\n-rdmacore52_0_dr_ste_create_next_htbl in dr_ste.c.o\n-rdmacore52_0_dr_ste_htbl_free in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_actions_tx in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_actions_rx in dr_ste.c.o\n-rdmacore52_0_dr_ste_conv_modify_hdr_sw_field in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_action_set in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_action_add in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_action_copy in dr_ste.c.o\n-rdmacore52_0_dr_ste_set_action_decap_l3_list in dr_ste.c.o\n-rdmacore52_0_dr_ste_alloc_modify_hdr in dr_ste.c.o\n-rdmacore52_0_dr_ste_free_modify_hdr in dr_ste.c.o\n-rdmacore52_0_dr_ste_alloc_encap in dr_ste.c.o\n-rdmacore52_0_dr_ste_free_encap in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_pre_check in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_ste_arr in dr_ste.c.o\n-rdmacore52_0_dr_ste_copy_param in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l2_src_dst in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l3_ipv6_src in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l2_src in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l2_dst in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l2_tnl in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_empty_always_hit in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_mpls in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_gre in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_mpls_over_gre in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_mpls_over_udp in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_icmp in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_general_purpose in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_eth_l4_misc in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_vxlan_gpe in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_geneve in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_gtpu in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_register_0 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_register_1 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_src_gvmi_qpn in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_flex_parser_0 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_flex_parser_1 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_tunnel_header in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_ib_l4 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def0 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def2 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def6 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def16 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def22 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def24 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def25 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def26 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def28 in dr_ste.c.o\n-rdmacore52_0_dr_ste_build_def33 in dr_ste.c.o\n-rdmacore52_0_dr_ste_get_ctx in dr_ste.c.o\n-mlx5dv_dr_aso_other_domain_link in dr_ste.c.o\n-mlx5dv_dr_aso_other_domain_unlink in dr_ste.c.o\n-rdmacore52_0_dr_vports_table_get_vport_cap in dr_vports.c.o\n-rdmacore52_0_dr_vports_table_get_ib_port_cap in dr_vports.c.o\n-rdmacore52_0_dr_vports_table_add_wire in dr_vports.c.o\n-rdmacore52_0_dr_vports_table_del_wire in dr_vports.c.o\n-rdmacore52_0_dr_vports_table_create in dr_vports.c.o\n-rdmacore52_0_dr_vports_table_destroy in dr_vports.c.o\n+rdmacore52_0_dr_ste_get_ctx_v0 in dr_ste_v0.c.o\n+rdmacore52_0_mlx5_stall_cq_poll_min in cq.c.o\n+rdmacore52_0_mlx5_stall_cq_dec_step in cq.c.o\n+rdmacore52_0_mlx5_stall_cq_poll_max in cq.c.o\n+rdmacore52_0_mlx5_stall_cq_inc_step in cq.c.o\n+rdmacore52_0_mlx5_stall_num_loop in cq.c.o\n+rdmacore52_0_mlx5_poll_cq in cq.c.o\n+rdmacore52_0_mlx5_poll_cq_v1 in cq.c.o\n+rdmacore52_0_mlx5_cq_fill_pfns in cq.c.o\n+rdmacore52_0_mlx5_arm_cq in cq.c.o\n+rdmacore52_0_mlx5_cq_event in cq.c.o\n+rdmacore52_0___mlx5_cq_clean in cq.c.o\n+rdmacore52_0_mlx5_cq_clean in cq.c.o\n+rdmacore52_0_mlx5_cq_resize_copy_cqes in cq.c.o\n+rdmacore52_0_mlx5_alloc_cq_buf in cq.c.o\n+rdmacore52_0_mlx5_free_cq_buf in cq.c.o\n rdmacore52_0_dr_actions_build_ste_arr in dr_action.c.o\n rdmacore52_0_dr_actions_build_attr in dr_action.c.o\n mlx5dv_dr_action_create_drop in dr_action.c.o\n mlx5dv_dr_action_create_default_miss in dr_action.c.o\n mlx5dv_dr_action_create_dest_ibv_qp in dr_action.c.o\n mlx5dv_dr_action_create_dest_devx_tir in dr_action.c.o\n mlx5dv_dr_action_create_dest_table in dr_action.c.o\n@@ -159,27 +36,24 @@\n mlx5dv_dr_action_modify_flow_meter in dr_action.c.o\n mlx5dv_dr_action_create_flow_meter in dr_action.c.o\n mlx5dv_dr_action_create_dest_vport in dr_action.c.o\n mlx5dv_dr_action_create_dest_ib_port in dr_action.c.o\n mlx5dv_dr_action_create_dest_array in dr_action.c.o\n mlx5dv_dr_action_destroy in dr_action.c.o\n mlx5dv_dr_action_create_flow_sampler in dr_action.c.o\n-rdmacore52_0_dr_domain_is_support_sw_encap in dr_domain.c.o\n-rdmacore52_0_dr_domain_is_support_modify_hdr_cache in dr_domain.c.o\n-rdmacore52_0_dr_domain_is_support_ste_icm_size in dr_domain.c.o\n-rdmacore52_0_dr_domain_set_max_ste_icm_size in dr_domain.c.o\n-mlx5dv_dr_domain_create in dr_domain.c.o\n-mlx5dv_dr_domain_sync in dr_domain.c.o\n-mlx5dv_dr_domain_set_reclaim_device_memory in dr_domain.c.o\n-mlx5dv_dr_domain_allow_duplicate_rules in dr_domain.c.o\n-mlx5dv_dr_domain_destroy in dr_domain.c.o\n+rdmacore52_0_dr_ste_v1_set_aso_ct in dr_ste_v1.c.o\n+rdmacore52_0_dr_ste_get_ctx_v1 in dr_ste_v1.c.o\n rdmacore52_0_dr_buddy_init in dr_buddy.c.o\n rdmacore52_0_dr_buddy_cleanup in dr_buddy.c.o\n rdmacore52_0_dr_buddy_alloc_mem in dr_buddy.c.o\n rdmacore52_0_dr_buddy_free_mem in dr_buddy.c.o\n+mlx5dv_vfio_get_events_fd in mlx5_vfio.c.o\n+mlx5dv_vfio_process_events in mlx5_vfio.c.o\n+mlx5dv_get_vfio_device_list in mlx5_vfio.c.o\n+rdmacore52_0_is_mlx5_vfio_dev in mlx5_vfio.c.o\n rdmacore52_0_mlx5_debug_mask in mlx5.c.o\n rdmacore52_0_mlx5_freeze_on_error_cqe in mlx5.c.o\n rdmacore52_0_mlx5_cmd_status_to_err in mlx5.c.o\n rdmacore52_0_mlx5_get_cmd_status_err in mlx5.c.o\n rdmacore52_0_mlx5_store_uidx in mlx5.c.o\n rdmacore52_0_mlx5_clear_uidx in mlx5.c.o\n rdmacore52_0_mlx5_find_mkey in mlx5.c.o\n@@ -211,26 +85,28 @@\n mlx5dv_set_context_attr in mlx5.c.o\n mlx5dv_get_clock_info in mlx5.c.o\n mlx5dv_is_supported in mlx5.c.o\n mlx5dv_open_device in mlx5.c.o\n rdmacore52_0_mlx5_get_dv_ops in mlx5.c.o\n rdmacore52_0_mlx5_hca_table in mlx5.c.o\n verbs_provider_mlx5 in mlx5.c.o\n-mlx5dv_dr_matcher_set_layout in dr_matcher.c.o\n-mlx5dv_dr_matcher_create in dr_matcher.c.o\n-mlx5dv_dr_matcher_destroy in dr_matcher.c.o\n-rdmacore52_0_dr_icm_pool_sync_pool in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_alloc_chunk in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_free_chunk in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_get_chunk_icm_addr in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_get_chunk_mr_addr in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_get_chunk_rkey in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_create in dr_icm_pool.c.o\n-rdmacore52_0_dr_icm_pool_destroy in dr_icm_pool.c.o\n+rdmacore52_0_dr_rule_send_update_list in dr_rule.c.o\n+rdmacore52_0_dr_rule_rehash_matcher_s_anchor in dr_rule.c.o\n+rdmacore52_0_dr_rule_set_last_member in dr_rule.c.o\n+rdmacore52_0_dr_rule_get_reverse_rule_members in dr_rule.c.o\n+mlx5dv_dr_rule_create in dr_rule.c.o\n+mlx5dv_dr_rule_destroy in dr_rule.c.o\n+rdmacore52_0_mlx5_alloc_dbrec in dbrec.c.o\n+rdmacore52_0_mlx5_free_db in dbrec.c.o\n+rdmacore52_0_dr_arg_get_object_id in dr_arg.c.o\n+rdmacore52_0_dr_arg_get_obj in dr_arg.c.o\n+rdmacore52_0_dr_arg_put_obj in dr_arg.c.o\n+rdmacore52_0_dr_arg_mngr_create in dr_arg.c.o\n+rdmacore52_0_dr_arg_mngr_destroy in dr_arg.c.o\n+rdmacore52_0_dr_ste_get_ctx_v2 in dr_ste_v2.c.o\n rdmacore52_0_mlx5_copy_to_recv_wqe in qp.c.o\n rdmacore52_0_mlx5_copy_to_send_wqe in qp.c.o\n rdmacore52_0_mlx5_get_send_wqe in qp.c.o\n rdmacore52_0_mlx5_init_rwq_indices in qp.c.o\n rdmacore52_0_mlx5_init_qp_indices in qp.c.o\n rdmacore52_0_mlx5_get_atomic_laddr in qp.c.o\n rdmacore52_0_mlx5_post_send in qp.c.o\n@@ -242,36 +118,116 @@\n rdmacore52_0_mlx5_post_recv in qp.c.o\n rdmacore52_0_mlx5_post_srq_ops in qp.c.o\n rdmacore52_0_mlx5_use_huge in qp.c.o\n rdmacore52_0_mlx5_find_qp in qp.c.o\n rdmacore52_0_mlx5_store_qp in qp.c.o\n rdmacore52_0_mlx5_clear_qp in qp.c.o\n mlx5dv_qp_cancel_posted_send_wrs in qp.c.o\n-rdmacore52_0_dr_send_fill_and_append_ste_send_info in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_ste in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_htbl in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_formated_htbl in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_action in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_pattern in dr_send.c.o\n-rdmacore52_0_dr_send_postsend_args in dr_send.c.o\n-rdmacore52_0_dr_send_allow_fl in dr_send.c.o\n-rdmacore52_0_dr_send_ring_free in dr_send.c.o\n-rdmacore52_0_dr_send_ring_alloc in dr_send.c.o\n-rdmacore52_0_dr_send_ring_force_drain in dr_send.c.o\n+rdmacore52_0_dr_vports_table_get_vport_cap in dr_vports.c.o\n+rdmacore52_0_dr_vports_table_get_ib_port_cap in dr_vports.c.o\n+rdmacore52_0_dr_vports_table_add_wire in dr_vports.c.o\n+rdmacore52_0_dr_vports_table_del_wire in dr_vports.c.o\n+rdmacore52_0_dr_vports_table_create in dr_vports.c.o\n+rdmacore52_0_dr_vports_table_destroy in dr_vports.c.o\n+rdmacore52_0_dr_ste_calc_hash_index in dr_ste.c.o\n+rdmacore52_0_dr_ste_conv_bit_to_byte_mask in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_bit_mask in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_miss_addr in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_hit_addr in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_hit_gvmi in dr_ste.c.o\n+rdmacore52_0_dr_ste_get_icm_addr in dr_ste.c.o\n+rdmacore52_0_dr_ste_get_mr_addr in dr_ste.c.o\n+rdmacore52_0_dr_ste_get_miss_list in dr_ste.c.o\n+rdmacore52_0_dr_ste_get_miss_list_top in dr_ste.c.o\n+rdmacore52_0_dr_ste_is_last_in_rule in dr_ste.c.o\n+rdmacore52_0_dr_ste_equal_tag in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl in dr_ste.c.o\n+rdmacore52_0_dr_ste_prepare_for_postsend in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_formated_ste in dr_ste.c.o\n+rdmacore52_0_dr_ste_free in dr_ste.c.o\n+rdmacore52_0_dr_ste_htbl_init_and_postsend in dr_ste.c.o\n+rdmacore52_0_dr_ste_htbl_alloc in dr_ste.c.o\n+rdmacore52_0_dr_ste_create_next_htbl in dr_ste.c.o\n+rdmacore52_0_dr_ste_htbl_free in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_actions_tx in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_actions_rx in dr_ste.c.o\n+rdmacore52_0_dr_ste_conv_modify_hdr_sw_field in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_action_set in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_action_add in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_action_copy in dr_ste.c.o\n+rdmacore52_0_dr_ste_set_action_decap_l3_list in dr_ste.c.o\n+rdmacore52_0_dr_ste_alloc_modify_hdr in dr_ste.c.o\n+rdmacore52_0_dr_ste_free_modify_hdr in dr_ste.c.o\n+rdmacore52_0_dr_ste_alloc_encap in dr_ste.c.o\n+rdmacore52_0_dr_ste_free_encap in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_pre_check in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_ste_arr in dr_ste.c.o\n+rdmacore52_0_dr_ste_copy_param in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l2_src_dst in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l3_ipv6_src in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l2_src in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l2_dst in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l2_tnl in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_empty_always_hit in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_mpls in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_gre in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_mpls_over_gre in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_mpls_over_udp in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_icmp in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_general_purpose in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_eth_l4_misc in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_vxlan_gpe in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_geneve in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_gtpu in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_register_0 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_register_1 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_src_gvmi_qpn in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_flex_parser_0 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_flex_parser_1 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_tunnel_header in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_ib_l4 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def0 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def2 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def6 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def16 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def22 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def24 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def25 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def26 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def28 in dr_ste.c.o\n+rdmacore52_0_dr_ste_build_def33 in dr_ste.c.o\n+rdmacore52_0_dr_ste_get_ctx in dr_ste.c.o\n+mlx5dv_dr_aso_other_domain_link in dr_ste.c.o\n+mlx5dv_dr_aso_other_domain_unlink in dr_ste.c.o\n rdmacore52_0_mlx5_copy_to_recv_srq in srq.c.o\n rdmacore52_0_mlx5_free_srq_wqe in srq.c.o\n rdmacore52_0_srq_cooldown_wqe in srq.c.o\n rdmacore52_0_mlx5_complete_odp_fault in srq.c.o\n rdmacore52_0_mlx5_post_srq_recv in srq.c.o\n rdmacore52_0_mlx5_alloc_srq_buf in srq.c.o\n rdmacore52_0_mlx5_find_srq in srq.c.o\n rdmacore52_0_mlx5_store_srq in srq.c.o\n rdmacore52_0_mlx5_clear_srq in srq.c.o\n-mlx5dv_dr_table_create in dr_table.c.o\n-mlx5dv_dr_table_destroy in dr_table.c.o\n+rdmacore52_0_dr_domain_is_support_sw_encap in dr_domain.c.o\n+rdmacore52_0_dr_domain_is_support_modify_hdr_cache in dr_domain.c.o\n+rdmacore52_0_dr_domain_is_support_ste_icm_size in dr_domain.c.o\n+rdmacore52_0_dr_domain_set_max_ste_icm_size in dr_domain.c.o\n+mlx5dv_dr_domain_create in dr_domain.c.o\n+mlx5dv_dr_domain_sync in dr_domain.c.o\n+mlx5dv_dr_domain_set_reclaim_device_memory in dr_domain.c.o\n+mlx5dv_dr_domain_allow_duplicate_rules in dr_domain.c.o\n+mlx5dv_dr_domain_destroy in dr_domain.c.o\n rdmacore52_0_mlx5_single_threaded in verbs.c.o\n rdmacore52_0__mlx5dv_create_flow in verbs.c.o\n rdmacore52_0_mlx5_query_rt_values in verbs.c.o\n rdmacore52_0_mlx5_query_port in verbs.c.o\n rdmacore52_0_mlx5_async_event in verbs.c.o\n rdmacore52_0_mlx5_alloc_pd in verbs.c.o\n rdmacore52_0_mlx5_alloc_td in verbs.c.o\n@@ -403,289 +359,490 @@\n mlx5dv_pp_alloc in verbs.c.o\n mlx5dv_pp_free in verbs.c.o\n mlx5dv_devx_alloc_msi_vector in verbs.c.o\n mlx5dv_devx_free_msi_vector in verbs.c.o\n mlx5dv_devx_create_eq in verbs.c.o\n mlx5dv_devx_destroy_eq in verbs.c.o\n rdmacore52_0_mlx5_set_dv_ctx_ops in verbs.c.o\n-rdmacore52_0_dr_ste_v1_set_aso_ct in dr_ste_v1.c.o\n-rdmacore52_0_dr_ste_get_ctx_v1 in dr_ste_v1.c.o\n-rdmacore52_0_dr_ste_get_ctx_v0 in dr_ste_v0.c.o\n+rdmacore52_0_dr_send_fill_and_append_ste_send_info in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_ste in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_htbl in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_formated_htbl in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_action in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_pattern in dr_send.c.o\n+rdmacore52_0_dr_send_postsend_args in dr_send.c.o\n+rdmacore52_0_dr_send_allow_fl in dr_send.c.o\n+rdmacore52_0_dr_send_ring_free in dr_send.c.o\n+rdmacore52_0_dr_send_ring_alloc in dr_send.c.o\n+rdmacore52_0_dr_send_ring_force_drain in dr_send.c.o\n+mlx5dv_dump_dr_domain in dr_dbg.c.o\n+mlx5dv_dump_dr_table in dr_dbg.c.o\n+mlx5dv_dump_dr_matcher in dr_dbg.c.o\n+mlx5dv_dump_dr_rule in dr_dbg.c.o\n+rdmacore52_0_dr_devx_query_esw_vport_context in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_gvmi in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_esw_caps in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_device in dr_devx.c.o\n+rdmacore52_0_dr_devx_sync_steering in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_flow_table in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_flow_table in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_always_hit_ft in dr_devx.c.o\n+rdmacore52_0_dr_devx_destroy_always_hit_ft in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_flow_sampler in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_flow_sampler in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_definer in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_reformat_ctx in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_meter in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_meter in dr_devx.c.o\n+rdmacore52_0_dr_devx_modify_meter in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_qp in dr_devx.c.o\n+rdmacore52_0_dr_devx_modify_qp_rst2init in dr_devx.c.o\n+rdmacore52_0_dr_devx_modify_qp_init2rtr in dr_devx.c.o\n+rdmacore52_0_dr_devx_modify_qp_rtr2rts in dr_devx.c.o\n+rdmacore52_0_dr_devx_query_gid in dr_devx.c.o\n+rdmacore52_0_dr_devx_create_modify_header_arg in dr_devx.c.o\n+rdmacore52_0_dr_icm_pool_sync_pool in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_alloc_chunk in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_free_chunk in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_get_chunk_icm_addr in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_get_chunk_mr_addr in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_get_chunk_rkey in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_create in dr_icm_pool.c.o\n+rdmacore52_0_dr_icm_pool_destroy in dr_icm_pool.c.o\n+mlx5dv_dr_matcher_set_layout in dr_matcher.c.o\n+mlx5dv_dr_matcher_create in dr_matcher.c.o\n+mlx5dv_dr_matcher_destroy in dr_matcher.c.o\n+mlx5dv_dr_table_create in dr_table.c.o\n+mlx5dv_dr_table_destroy in dr_table.c.o\n+rdmacore52_0_mlx5_free_buf_extern in buf.c.o\n+rdmacore52_0_mlx5_alloc_buf_extern in buf.c.o\n+rdmacore52_0_mlx5_free_actual_buf in buf.c.o\n+rdmacore52_0_mlx5_is_custom_alloc in buf.c.o\n+rdmacore52_0_mlx5_is_extern_alloc in buf.c.o\n+rdmacore52_0_mlx5_get_alloc_type in buf.c.o\n+rdmacore52_0_mlx5_alloc_buf_contig in buf.c.o\n+rdmacore52_0_mlx5_alloc_prefered_buf in buf.c.o\n+rdmacore52_0_mlx5_free_buf_contig in buf.c.o\n+rdmacore52_0_mlx5_alloc_buf in buf.c.o\n+rdmacore52_0_mlx5_free_buf in buf.c.o\n+rdmacore52_0_dr_crc32_init_table in dr_crc32.c.o\n+rdmacore52_0_dr_crc32_slice8_calc in dr_crc32.c.o\n rdmacore52_0_dr_ptrn_sync_pool in dr_ptrn.c.o\n rdmacore52_0_dr_ptrn_cache_get_pattern in dr_ptrn.c.o\n rdmacore52_0_dr_ptrn_cache_put_pattern in dr_ptrn.c.o\n rdmacore52_0_dr_ptrn_mngr_create in dr_ptrn.c.o\n rdmacore52_0_dr_ptrn_mngr_destroy in dr_ptrn.c.o\n-rdmacore52_0_mlx5_stall_cq_poll_min in cq.c.o\n-rdmacore52_0_mlx5_stall_cq_dec_step in cq.c.o\n-rdmacore52_0_mlx5_stall_cq_poll_max in cq.c.o\n-rdmacore52_0_mlx5_stall_cq_inc_step in cq.c.o\n-rdmacore52_0_mlx5_stall_num_loop in cq.c.o\n-rdmacore52_0_mlx5_poll_cq in cq.c.o\n-rdmacore52_0_mlx5_poll_cq_v1 in cq.c.o\n-rdmacore52_0_mlx5_cq_fill_pfns in cq.c.o\n-rdmacore52_0_mlx5_arm_cq in cq.c.o\n-rdmacore52_0_mlx5_cq_event in cq.c.o\n-rdmacore52_0___mlx5_cq_clean in cq.c.o\n-rdmacore52_0_mlx5_cq_clean in cq.c.o\n-rdmacore52_0_mlx5_cq_resize_copy_cqes in cq.c.o\n-rdmacore52_0_mlx5_alloc_cq_buf in cq.c.o\n-rdmacore52_0_mlx5_free_cq_buf in cq.c.o\n-rdmacore52_0_dr_crc32_init_table in dr_crc32.c.o\n-rdmacore52_0_dr_crc32_slice8_calc in dr_crc32.c.o\n \n-dr_devx.c.o:\n-0000000000000000 r .LC0\n-0000000000000008 r .LC1\n-0000000000000040 r .LC10\n-0000000000000010 r .LC3\n-0000000000000018 r .LC5\n-0000000000000020 r .LC6\n-0000000000000028 r .LC7\n-0000000000000030 r .LC8\n-0000000000000038 r .LC9\n+dr_ste_v0.c.o:\n U __errno_location\n U __stack_chk_fail\n- U calloc\n- U free\n- U memcpy\n- U mlx5dv_devx_general_cmd\n- U mlx5dv_devx_obj_create\n- U mlx5dv_devx_obj_destroy\n- U mlx5dv_devx_obj_modify\n- U mlx5dv_devx_obj_query\n-0000000000000ca0 T rdmacore52_0_dr_devx_create_always_hit_ft\n-0000000000001400 T rdmacore52_0_dr_devx_create_definer\n-0000000000001230 T rdmacore52_0_dr_devx_create_flow_sampler\n-0000000000000a20 T rdmacore52_0_dr_devx_create_flow_table\n-00000000000015f0 T rdmacore52_0_dr_devx_create_meter\n-0000000000001e10 T rdmacore52_0_dr_devx_create_modify_header_arg\n-00000000000018d0 T rdmacore52_0_dr_devx_create_qp\n-00000000000014d0 T rdmacore52_0_dr_devx_create_reformat_ctx\n-0000000000001200 T rdmacore52_0_dr_devx_destroy_always_hit_ft\n-00000000000017e0 T rdmacore52_0_dr_devx_modify_meter\n-0000000000001b40 T rdmacore52_0_dr_devx_modify_qp_init2rtr\n-0000000000001a70 T rdmacore52_0_dr_devx_modify_qp_rst2init\n-0000000000001c70 T rdmacore52_0_dr_devx_modify_qp_rtr2rts\n-00000000000002c0 T rdmacore52_0_dr_devx_query_device\n-00000000000001a0 T rdmacore52_0_dr_devx_query_esw_caps\n-0000000000000000 T rdmacore52_0_dr_devx_query_esw_vport_context\n-0000000000001330 T rdmacore52_0_dr_devx_query_flow_sampler\n-0000000000000b50 T rdmacore52_0_dr_devx_query_flow_table\n-0000000000001d40 T rdmacore52_0_dr_devx_query_gid\n-00000000000000e0 T rdmacore52_0_dr_devx_query_gvmi\n-0000000000001710 T rdmacore52_0_dr_devx_query_meter\n-0000000000000990 T rdmacore52_0_dr_devx_sync_steering\n- U rdmacore52_0_mlx5_get_cmd_status_err\n+0000000000000000 r dr_ste_v0_action_modify_field_arr\n+0000000000001e80 t dr_ste_v0_build_eth_ipv6_l3_l4_init\n+00000000000008f0 t dr_ste_v0_build_eth_ipv6_l3_l4_tag\n+0000000000003c40 t dr_ste_v0_build_eth_l2_dst_init\n+0000000000001140 t dr_ste_v0_build_eth_l2_dst_tag\n+0000000000002350 t dr_ste_v0_build_eth_l2_src_dst_init\n+0000000000001510 t dr_ste_v0_build_eth_l2_src_dst_tag\n+0000000000002040 t dr_ste_v0_build_eth_l2_src_init\n+0000000000000df0 t dr_ste_v0_build_eth_l2_src_or_dst_tag\n+00000000000011a0 t dr_ste_v0_build_eth_l2_src_tag\n+0000000000001ed0 t dr_ste_v0_build_eth_l2_tnl_init\n+0000000000000c20 t dr_ste_v0_build_eth_l2_tnl_tag\n+0000000000003f50 t dr_ste_v0_build_eth_l3_ipv4_5_tuple_init\n+00000000000011f0 t dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag\n+00000000000028d0 t dr_ste_v0_build_eth_l3_ipv4_misc_init\n+0000000000000bc0 t dr_ste_v0_build_eth_l3_ipv4_misc_tag\n+00000000000029b0 t dr_ste_v0_build_eth_l3_ipv6_dst_init\n+0000000000001450 t dr_ste_v0_build_eth_l3_ipv6_dst_tag\n+0000000000002a50 t dr_ste_v0_build_eth_l3_ipv6_src_init\n+00000000000014b0 t dr_ste_v0_build_eth_l3_ipv6_src_tag\n+00000000000026d0 t dr_ste_v0_build_eth_l4_misc_init\n+0000000000002650 t dr_ste_v0_build_eth_l4_misc_tag\n+0000000000003430 t dr_ste_v0_build_flex_parser_0_init\n+00000000000033e0 t dr_ste_v0_build_flex_parser_1_init\n+0000000000003090 t dr_ste_v0_build_flex_parser_tag\n+0000000000002af0 t dr_ste_v0_build_flex_parser_tnl_geneve_init\n+00000000000005c0 t dr_ste_v0_build_flex_parser_tnl_geneve_tag\n+0000000000001cb0 t dr_ste_v0_build_flex_parser_tnl_geneve_tlv_opt_init\n+00000000000018d0 t dr_ste_v0_build_flex_parser_tnl_geneve_tlv_opt_tag\n+0000000000002780 t dr_ste_v0_build_flex_parser_tnl_gtpu_init\n+0000000000000550 t dr_ste_v0_build_flex_parser_tnl_gtpu_tag\n+0000000000002820 t dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init\n+00000000000025d0 t dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag\n+0000000000001d10 t dr_ste_v0_build_general_purpose_init\n+0000000000000650 t dr_ste_v0_build_general_purpose_tag\n+0000000000002bb0 t dr_ste_v0_build_icmp_init\n+0000000000001910 t dr_ste_v0_build_icmp_tag\n+0000000000003480 t dr_ste_v0_build_mpls_init\n+0000000000000750 t dr_ste_v0_build_mpls_tag\n+0000000000001c20 t dr_ste_v0_build_register_0_init\n+00000000000004e0 t dr_ste_v0_build_register_0_tag\n+0000000000001b90 t dr_ste_v0_build_register_1_init\n+0000000000000470 t dr_ste_v0_build_register_1_tag\n+0000000000001b20 t dr_ste_v0_build_src_gvmi_qpn_init\n+00000000000024d0 t dr_ste_v0_build_src_gvmi_qpn_tag\n+0000000000002f90 t dr_ste_v0_build_tnl_gre_init\n+0000000000000670 t dr_ste_v0_build_tnl_gre_tag\n+0000000000002d40 t dr_ste_v0_build_tnl_gtpu_flex_parser_0_init\n+00000000000017d0 t dr_ste_v0_build_tnl_gtpu_flex_parser_0_tag\n+0000000000002e70 t dr_ste_v0_build_tnl_gtpu_flex_parser_1_init\n+00000000000016e0 t dr_ste_v0_build_tnl_gtpu_flex_parser_1_tag\n+0000000000001df0 t dr_ste_v0_build_tnl_mpls_over_gre_init\n+0000000000001a50 t dr_ste_v0_build_tnl_mpls_over_gre_tag\n+0000000000001d60 t dr_ste_v0_build_tnl_mpls_over_udp_init\n+00000000000019e0 t dr_ste_v0_build_tnl_mpls_over_udp_tag\n+0000000000001ac0 t dr_ste_v0_build_tunnel_header_0_1_init\n+0000000000000430 t dr_ste_v0_build_tunnel_header_0_1_tag\n+0000000000002580 t dr_ste_v0_get_action_hw_field\n+0000000000000010 t dr_ste_v0_get_byte_mask\n+0000000000000020 t dr_ste_v0_get_miss_addr\n+0000000000000000 t dr_ste_v0_get_next_lu_type\n+0000000000002ce0 t dr_ste_v0_init\n+0000000000000240 t dr_ste_v0_set_action_add\n+00000000000001e0 t dr_ste_v0_set_action_copy\n+0000000000000040 t dr_ste_v0_set_action_decap_l3_list\n+0000000000000280 t dr_ste_v0_set_action_set\n+00000000000039b0 t dr_ste_v0_set_actions_rx\n+0000000000003650 t dr_ste_v0_set_actions_tx\n+00000000000002e0 t dr_ste_v0_set_byte_mask\n+00000000000003e0 t dr_ste_v0_set_ctrl_always_hit_htbl\n+00000000000003a0 t dr_ste_v0_set_ctrl_always_miss\n+0000000000000300 t dr_ste_v0_set_hit_addr\n+00000000000002c0 t dr_ste_v0_set_hit_gvmi\n+0000000000000340 t dr_ste_v0_set_miss_addr\n+0000000000000380 t dr_ste_v0_set_next_lu_type\n+ U rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n+00000000000041e0 T rdmacore52_0_dr_ste_get_ctx_v0\n+ U rdmacore52_0_dr_vports_table_get_vport_cap\n+0000000000000000 d ste_ctx_v0\n \n-dr_dbg.c.o:\n+cq.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n-0000000000000070 r .LC10\n-0000000000000058 r .LC11\n-000000000000008a r .LC12\n-00000000000000a2 r .LC13\n-00000000000000b5 r .LC14\n-00000000000000ba r .LC15\n-00000000000000ca r .LC16\n-00000000000000e5 r .LC17\n-00000000000000fa r .LC18\n-0000000000000080 r .LC19\n-0000000000000005 r .LC2\n-0000000000000110 r .LC20\n-0000000000000112 r .LC21\n-00000000000000a8 r .LC22\n-00000000000000d0 r .LC23\n-0000000000000100 r .LC24\n-000000000000011c r .LC25\n-0000000000000132 r .LC26\n-000000000000013c r .LC27\n-0000000000000140 r .LC28\n-0000000000000142 r .LC29\n-0000000000000030 r .LC3\n-0000000000000146 r .LC30\n-0000000000000149 r .LC31\n-0000000000000018 r .LC4\n-0000000000000021 r .LC5\n-0000000000000033 r .LC6\n-0000000000000051 r .LC7\n-000000000000005a r .LC8\n-0000000000000065 r .LC9\n- U __fprintf_chk\n- U __sprintf_chk\n+0000000000000058 r .LC10\n+0000000000000000 r .LC2\n+0000000000000090 r .LC3\n+0000000000000015 r .LC4\n+0000000000000032 r .LC7\n+00000000000000b8 r .LC8\n+0000000000000050 r .LC9\n+0000000000000980 r CSWTCH.104\n+00000000000007a0 t __mlx5_cq_clean.part.0\n U __stack_chk_fail\n-0000000000000000 t dr_dump_domain\n-0000000000001100 t dr_dump_matcher\n-0000000000000c40 t dr_dump_matcher_mask\n-0000000000000340 t dr_dump_matcher_rx_tx\n-00000000000005e0 t dr_dump_rule\n-0000000000000480 t dr_dump_rule_rx_tx.isra.0\n-0000000000000b40 t dr_dump_table\n- U fputc\n- U getpid\n-00000000000011c0 T mlx5dv_dump_dr_domain\n-00000000000015c0 T mlx5dv_dump_dr_matcher\n-0000000000001750 T mlx5dv_dump_dr_rule\n-00000000000013f0 T mlx5dv_dump_dr_table\n+ U __vfprintf_chk\n+ U abort\n+0000000000000560 t dump_cqe\n+ U fwrite\n+0000000000000b40 t handle_tag_matching\n+ U memcpy\n+ U memset\n+0000000000000b20 t mlx5_cq_read_flow_tag\n+00000000000002a0 t mlx5_cq_read_wc_byte_len\n+0000000000000180 t mlx5_cq_read_wc_completion_ts\n+00000000000001a0 t mlx5_cq_read_wc_completion_wallclock_ns\n+00000000000005c0 t mlx5_cq_read_wc_cvlan\n+0000000000000030 t mlx5_cq_read_wc_dlid_path_bits\n+00000000000002c0 t mlx5_cq_read_wc_flags\n+0000000000000280 t mlx5_cq_read_wc_imm_data\n+0000000000000050 t mlx5_cq_read_wc_opcode\n+0000000000000260 t mlx5_cq_read_wc_qp_num\n+0000000000000010 t mlx5_cq_read_wc_sl\n+00000000000005e0 t mlx5_cq_read_wc_slid\n+0000000000000240 t mlx5_cq_read_wc_src_qp\n+0000000000000220 t mlx5_cq_read_wc_tm_info\n+0000000000000000 t mlx5_cq_read_wc_vendor_err\n+0000000000000480 t mlx5_end_poll\n+0000000000000380 t mlx5_end_poll_adaptive_stall\n+0000000000000600 t mlx5_end_poll_adaptive_stall_lock\n+0000000000000760 t mlx5_end_poll_lock\n+0000000000000440 t mlx5_end_poll_stall\n+00000000000006f0 t mlx5_end_poll_stall_lock\n+00000000000004a0 t mlx5_err\n+0000000000003f90 t mlx5_next_poll_adaptive_v0\n+0000000000005570 t mlx5_next_poll_adaptive_v1\n+00000000000034d0 t mlx5_next_poll_v0\n+0000000000004a60 t mlx5_next_poll_v1\n+0000000000009880 t mlx5_start_poll_adaptive_stall_v0\n+000000000000bad0 t mlx5_start_poll_adaptive_stall_v0_clock_update\n+0000000000010e20 t mlx5_start_poll_adaptive_stall_v0_lock\n+00000000000132c0 t mlx5_start_poll_adaptive_stall_v0_lock_clock_update\n+0000000000011ae0 t mlx5_start_poll_adaptive_stall_v1\n+0000000000013f90 t mlx5_start_poll_adaptive_stall_v1_clock_update\n+00000000000028a0 t mlx5_start_poll_adaptive_stall_v1_lock\n+0000000000000ef0 t mlx5_start_poll_adaptive_stall_v1_lock_clock_update\n+0000000000007650 t mlx5_start_poll_stall_v0\n+0000000000008180 t mlx5_start_poll_stall_v0_clock_update\n+000000000000d1c0 t mlx5_start_poll_stall_v0_lock\n+000000000000e9f0 t mlx5_start_poll_stall_v0_lock_clock_update\n+000000000000de40 t mlx5_start_poll_stall_v1\n+000000000000f680 t mlx5_start_poll_stall_v1_clock_update\n+0000000000014bc0 t mlx5_start_poll_stall_v1_lock\n+0000000000001bf0 t mlx5_start_poll_stall_v1_lock_clock_update\n+0000000000006070 t mlx5_start_poll_v0\n+0000000000006b60 t mlx5_start_poll_v0_clock_update\n+0000000000008cd0 t mlx5_start_poll_v0_lock\n+000000000000af10 t mlx5_start_poll_v0_lock_clock_update\n+000000000000a3f0 t mlx5_start_poll_v1\n+000000000000c670 t mlx5_start_poll_v1_clock_update\n+0000000000010250 t mlx5_start_poll_v1_lock\n+00000000000126c0 t mlx5_start_poll_v1_lock_clock_update\n+ U mlx5dv_get_clock_info\n+0000000000000000 d ops\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n U pthread_spin_lock\n U pthread_spin_unlock\n- U rdmacore52_0_dr_actions_reformat_get_id\n- U rdmacore52_0_dr_arg_get_object_id\n- U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n- U rdmacore52_0_dr_rule_get_reverse_rule_members\n- U rdmacore52_0_dr_ste_get_icm_addr\n+00000000000178e0 T rdmacore52_0___mlx5_cq_clean\n+0000000000017cf0 T rdmacore52_0_mlx5_alloc_cq_buf\n+ U rdmacore52_0_mlx5_alloc_prefered_buf\n+0000000000017860 T rdmacore52_0_mlx5_arm_cq\n+ U rdmacore52_0_mlx5_complete_odp_fault\n+ U rdmacore52_0_mlx5_copy_to_recv_srq\n+ U rdmacore52_0_mlx5_copy_to_recv_wqe\n+ U rdmacore52_0_mlx5_copy_to_send_wqe\n+0000000000017910 T rdmacore52_0_mlx5_cq_clean\n+00000000000178d0 T rdmacore52_0_mlx5_cq_event\n+0000000000017660 T rdmacore52_0_mlx5_cq_fill_pfns\n+00000000000179d0 T rdmacore52_0_mlx5_cq_resize_copy_cqes\n+ U rdmacore52_0_mlx5_find_mkey\n+ U rdmacore52_0_mlx5_find_qp\n+ U rdmacore52_0_mlx5_find_srq\n+ U rdmacore52_0_mlx5_free_actual_buf\n+0000000000017e50 T rdmacore52_0_mlx5_free_cq_buf\n+ U rdmacore52_0_mlx5_free_srq_wqe\n+ U rdmacore52_0_mlx5_freeze_on_error_cqe\n+ U rdmacore52_0_mlx5_get_alloc_type\n+0000000000015810 T rdmacore52_0_mlx5_poll_cq\n+0000000000016690 T rdmacore52_0_mlx5_poll_cq_v1\n+0000000000000000 D rdmacore52_0_mlx5_stall_cq_dec_step\n+0000000000000004 D rdmacore52_0_mlx5_stall_cq_inc_step\n+0000000000000008 D rdmacore52_0_mlx5_stall_cq_poll_max\n+000000000000000c D rdmacore52_0_mlx5_stall_cq_poll_min\n+0000000000000010 D rdmacore52_0_mlx5_stall_num_loop\n+ U rdmacore52_0_mlx5_use_huge\n+ U sleep\n+ U stderr\n \n-dr_arg.c.o:\n+dr_action.c.o:\n+0000000000000000 r .LC0\n U __errno_location\n U __stack_chk_fail\n U calloc\n-0000000000000000 t dr_arg_pool_alloc_objs\n+0000000000000000 t dr_action_aso_flow_meter_init\n+00000000000001e0 t dr_action_convert_to_fte_dest\n+0000000000000090 t dr_action_create_sampler\n U free\n+ U memcpy\n+ U mlx5dv_create_flow_action_modify_header\n+ U mlx5dv_create_flow_action_packet_reformat\n+ U mlx5dv_create_steering_anchor\n+ U mlx5dv_destroy_steering_anchor\n U mlx5dv_devx_obj_destroy\n- U pthread_mutex_destroy\n- U pthread_mutex_init\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n-00000000000001c0 T rdmacore52_0_dr_arg_get_obj\n-00000000000001b0 T rdmacore52_0_dr_arg_get_object_id\n-0000000000000390 T rdmacore52_0_dr_arg_mngr_create\n-0000000000000500 T rdmacore52_0_dr_arg_mngr_destroy\n-0000000000000330 T rdmacore52_0_dr_arg_put_obj\n- U rdmacore52_0_dr_devx_create_modify_header_arg\n- U rdmacore52_0_dr_domain_is_support_modify_hdr_cache\n+0000000000001820 T mlx5dv_dr_action_create_aso\n+0000000000001410 T mlx5dv_dr_action_create_default_miss\n+00000000000028e0 T mlx5dv_dr_action_create_dest_array\n+00000000000014b0 T mlx5dv_dr_action_create_dest_devx_tir\n+0000000000002840 T mlx5dv_dr_action_create_dest_ib_port\n+0000000000001450 T mlx5dv_dr_action_create_dest_ibv_qp\n+0000000000001580 T mlx5dv_dr_action_create_dest_root_table\n+0000000000001510 T mlx5dv_dr_action_create_dest_table\n+0000000000002790 T mlx5dv_dr_action_create_dest_vport\n+00000000000013d0 T mlx5dv_dr_action_create_drop\n+00000000000017b0 T mlx5dv_dr_action_create_flow_counter\n+0000000000002670 T mlx5dv_dr_action_create_flow_meter\n+0000000000002f00 T mlx5dv_dr_action_create_flow_sampler\n+0000000000001f70 T mlx5dv_dr_action_create_modify_header\n+0000000000001b80 T mlx5dv_dr_action_create_packet_reformat\n+0000000000001ea0 T mlx5dv_dr_action_create_pop_vlan\n+0000000000001ee0 T mlx5dv_dr_action_create_push_vlan\n+0000000000001b20 T mlx5dv_dr_action_create_tag\n+0000000000002c70 T mlx5dv_dr_action_destroy\n+00000000000019f0 T mlx5dv_dr_action_modify_aso\n+0000000000002630 T mlx5dv_dr_action_modify_flow_meter\n+ U mlx5dv_dr_matcher_create\n+ U mlx5dv_dr_matcher_destroy\n+ U mlx5dv_dr_rule_create\n+ U mlx5dv_dr_rule_destroy\n+ U mlx5dv_dr_table_create\n+ U mlx5dv_dr_table_destroy\n+00000000000001a0 r next_action_state\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+0000000000001260 T rdmacore52_0_dr_actions_build_attr\n+00000000000004b0 T rdmacore52_0_dr_actions_build_ste_arr\n+0000000000001f50 T rdmacore52_0_dr_actions_reformat_get_id\n+ U rdmacore52_0_dr_arg_get_object_id\n+ U rdmacore52_0_dr_devx_create_always_hit_ft\n+ U rdmacore52_0_dr_devx_create_flow_sampler\n+ U rdmacore52_0_dr_devx_create_meter\n+ U rdmacore52_0_dr_devx_create_reformat_ctx\n+ U rdmacore52_0_dr_devx_destroy_always_hit_ft\n+ U rdmacore52_0_dr_devx_modify_meter\n+ U rdmacore52_0_dr_devx_query_flow_sampler\n+ U rdmacore52_0_dr_devx_query_flow_table\n+ U rdmacore52_0_dr_devx_query_meter\n+ U rdmacore52_0_dr_domain_is_support_sw_encap\n+ U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n U rdmacore52_0_dr_send_postsend_args\n+ U rdmacore52_0_dr_ste_alloc_encap\n+ U rdmacore52_0_dr_ste_alloc_modify_hdr\n+ U rdmacore52_0_dr_ste_conv_modify_hdr_sw_field\n+ U rdmacore52_0_dr_ste_free_encap\n+ U rdmacore52_0_dr_ste_free_modify_hdr\n+ U rdmacore52_0_dr_ste_set_action_add\n+ U rdmacore52_0_dr_ste_set_action_copy\n+ U rdmacore52_0_dr_ste_set_action_decap_l3_list\n+ U rdmacore52_0_dr_ste_set_action_set\n+ U rdmacore52_0_dr_ste_set_actions_rx\n+ U rdmacore52_0_dr_ste_set_actions_tx\n+ U rdmacore52_0_dr_vports_table_get_ib_port_cap\n+ U rdmacore52_0_dr_vports_table_get_vport_cap\n+ U rdmacore52_0_mlx5_destroy_flow_action\n \n-dbrec.c.o:\n- U free\n- U malloc\n- U memset\n-0000000000000000 t mlx5_alloc_dbrec.cold\n-000000000000000a t mlx5_free_db.cold\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0_cl_qmap_get\n- U rdmacore52_0_cl_qmap_insert\n- U rdmacore52_0_cl_qmap_remove_item\n- U rdmacore52_0_mlx5_alloc_buf\n- U rdmacore52_0_mlx5_alloc_buf_extern\n-0000000000000000 T rdmacore52_0_mlx5_alloc_dbrec\n- U rdmacore52_0_mlx5_free_buf\n- U rdmacore52_0_mlx5_free_buf_extern\n-0000000000000270 T rdmacore52_0_mlx5_free_db\n- U rdmacore52_0_mlx5_is_custom_alloc\n- U rdmacore52_0_mlx5_is_extern_alloc\n-\n-dr_rule.c.o:\n-0000000000000000 r .LC0\n+dr_ste_v1.c.o:\n U __errno_location\n- U __memcpy_chk\n U __stack_chk_fail\n U calloc\n-0000000000000000 t dr_rule_clean_rule_members\n-0000000000001e80 t dr_rule_create_rule\n-0000000000000df0 t dr_rule_create_rule_nic\n-00000000000000d0 t dr_rule_rehash_htbl_common\n+0000000000000060 r dr_ste_v1_action_modify_field_arr\n+0000000000000000 r dr_ste_v1_action_modify_flex_field_arr\n+0000000000004be0 t dr_ste_v1_alloc_modify_hdr_ptrn_arg\n+00000000000054d0 t dr_ste_v1_aso_other_domain_link\n+0000000000004ca0 t dr_ste_v1_aso_other_domain_unlink\n+0000000000004ba0 t dr_ste_v1_build_def0_init\n+0000000000001d30 t dr_ste_v1_build_def0_tag\n+0000000000006520 t dr_ste_v1_build_def16_init\n+0000000000003b50 t dr_ste_v1_build_def16_tag\n+00000000000078b0 t dr_ste_v1_build_def22_init\n+0000000000001370 t dr_ste_v1_build_def22_tag\n+0000000000007bf0 t dr_ste_v1_build_def24_init\n+0000000000001070 t dr_ste_v1_build_def24_tag\n+0000000000007f30 t dr_ste_v1_build_def25_init\n+0000000000000d50 t dr_ste_v1_build_def25_tag\n+0000000000004b50 t dr_ste_v1_build_def26_init\n+0000000000000980 t dr_ste_v1_build_def26_tag\n+0000000000004af0 t dr_ste_v1_build_def28_init\n+00000000000005a0 t dr_ste_v1_build_def28_tag\n+0000000000001cf0 t dr_ste_v1_build_def2_init\n+00000000000018b0 t dr_ste_v1_build_def2_tag\n+0000000000004ab0 t dr_ste_v1_build_def33_init\n+00000000000001a0 t dr_ste_v1_build_def33_tag\n+0000000000006a80 t dr_ste_v1_build_def6_init\n+0000000000001640 t dr_ste_v1_build_def6_tag\n+00000000000041d0 t dr_ste_v1_build_eth_ipv6_l3_l4_init\n+0000000000002720 t dr_ste_v1_build_eth_ipv6_l3_l4_tag\n+0000000000004380 t dr_ste_v1_build_eth_l2_dst_init\n+00000000000038f0 t dr_ste_v1_build_eth_l2_dst_tag\n+0000000000004670 t dr_ste_v1_build_eth_l2_src_dst_init\n+00000000000039a0 t dr_ste_v1_build_eth_l2_src_dst_tag\n+0000000000006790 t dr_ste_v1_build_eth_l2_src_init\n+00000000000035b0 t dr_ste_v1_build_eth_l2_src_or_dst_tag\n+0000000000003950 t dr_ste_v1_build_eth_l2_src_tag\n+0000000000004210 t dr_ste_v1_build_eth_l2_tnl_init\n+00000000000033f0 t dr_ste_v1_build_eth_l2_tnl_tag\n+0000000000008ad0 t dr_ste_v1_build_eth_l3_ipv4_5_tuple_init\n+0000000000002a80 t dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag\n+00000000000052f0 t dr_ste_v1_build_eth_l3_ipv4_misc_init\n+0000000000002a20 t dr_ste_v1_build_eth_l3_ipv4_misc_tag\n+00000000000053b0 t dr_ste_v1_build_eth_l3_ipv6_dst_init\n+0000000000002ce0 t dr_ste_v1_build_eth_l3_ipv6_dst_tag\n+0000000000005440 t dr_ste_v1_build_eth_l3_ipv6_src_init\n+0000000000002d40 t dr_ste_v1_build_eth_l3_ipv6_src_tag\n+0000000000004e10 t dr_ste_v1_build_eth_l4_misc_init\n+0000000000004930 t dr_ste_v1_build_eth_l4_misc_tag\n+0000000000005f50 t dr_ste_v1_build_felx_parser_tag\n+0000000000006300 t dr_ste_v1_build_flex_parser_0_init\n+00000000000062b0 t dr_ste_v1_build_flex_parser_1_init\n+0000000000005b40 t dr_ste_v1_build_flex_parser_tnl_geneve_init\n+0000000000002340 t dr_ste_v1_build_flex_parser_tnl_geneve_tag\n+0000000000003fa0 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init\n+0000000000002300 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag\n+0000000000004000 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init\n+0000000000003100 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_tag\n+0000000000004f90 t dr_ste_v1_build_flex_parser_tnl_gtpu_init\n+0000000000002290 t dr_ste_v1_build_flex_parser_tnl_gtpu_tag\n+00000000000051a0 t dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init\n+00000000000048b0 t dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag\n+0000000000004060 t dr_ste_v1_build_general_purpose_init\n+00000000000023d0 t dr_ste_v1_build_general_purpose_tag\n+0000000000005250 t dr_ste_v1_build_ib_l4_init\n+00000000000047b0 t dr_ste_v1_build_ib_l4_tag\n+0000000000005030 t dr_ste_v1_build_icmp_init\n+00000000000023f0 t dr_ste_v1_build_icmp_tag\n+0000000000006350 t dr_ste_v1_build_mpls_init\n+0000000000002570 t dr_ste_v1_build_mpls_tag\n+0000000000003f10 t dr_ste_v1_build_register_0_init\n+0000000000002220 t dr_ste_v1_build_register_0_tag\n+0000000000003e80 t dr_ste_v1_build_register_1_init\n+00000000000021b0 t dr_ste_v1_build_register_1_tag\n+0000000000003e10 t dr_ste_v1_build_src_gvmi_qpn_init\n+0000000000003d60 t dr_ste_v1_build_src_gvmi_qpn_tag\n+0000000000005e50 t dr_ste_v1_build_tnl_gre_init\n+0000000000002490 t dr_ste_v1_build_tnl_gre_tag\n+0000000000005c00 t dr_ste_v1_build_tnl_gtpu_flex_parser_0_init\n+0000000000003000 t dr_ste_v1_build_tnl_gtpu_flex_parser_0_tag\n+0000000000005d30 t dr_ste_v1_build_tnl_gtpu_flex_parser_1_init\n+0000000000002f10 t dr_ste_v1_build_tnl_gtpu_flex_parser_1_tag\n+0000000000004140 t dr_ste_v1_build_tnl_mpls_over_gre_init\n+00000000000031b0 t dr_ste_v1_build_tnl_mpls_over_gre_tag\n+00000000000040b0 t dr_ste_v1_build_tnl_mpls_over_udp_init\n+0000000000003140 t dr_ste_v1_build_tnl_mpls_over_udp_tag\n+0000000000004eb0 t dr_ste_v1_build_tunnel_header_init\n+0000000000004830 t dr_ste_v1_build_tunnel_header_tag\n+00000000000032a0 t dr_ste_v1_dealloc_modify_hdr_ptrn_arg\n+0000000000004a30 t dr_ste_v1_get_action_hw_field\n+0000000000002ee0 t dr_ste_v1_get_byte_mask\n+0000000000002ef0 t dr_ste_v1_get_miss_addr\n+0000000000000000 t dr_ste_v1_get_next_lu_type\n+0000000000002e50 t dr_ste_v1_init\n+0000000000003270 t dr_ste_v1_prepare_for_postsend\n+0000000000000080 t dr_ste_v1_set_action_add\n+0000000000000020 t dr_ste_v1_set_action_copy\n+00000000000032d0 t dr_ste_v1_set_action_decap_l3_list\n+00000000000000c0 t dr_ste_v1_set_action_set\n+0000000000006d00 t dr_ste_v1_set_actions_rx\n+00000000000083c0 t dr_ste_v1_set_actions_tx\n+0000000000003220 t dr_ste_v1_set_aso_ct_cross_dmn\n+0000000000004c80 t dr_ste_v1_set_byte_mask\n+00000000000050f0 t dr_ste_v1_set_ctrl_always_hit_htbl\n+0000000000002de0 t dr_ste_v1_set_ctrl_always_miss\n+0000000000000120 t dr_ste_v1_set_hit_addr\n+0000000000000100 t dr_ste_v1_set_hit_gvmi\n+0000000000000160 t dr_ste_v1_set_miss_addr\n+0000000000002da0 t dr_ste_v1_set_next_lu_type\n+00000000000049b0 t dr_ste_v1_set_rewrite_actions\n U free\n-00000000000025b0 T mlx5dv_dr_rule_create\n-00000000000027b0 T mlx5dv_dr_rule_destroy\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0__mlx5dv_create_flow\n- U rdmacore52_0_dr_actions_build_attr\n- U rdmacore52_0_dr_actions_build_ste_arr\n- U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n-0000000000002550 T rdmacore52_0_dr_rule_get_reverse_rule_members\n-0000000000002470 T rdmacore52_0_dr_rule_rehash_matcher_s_anchor\n-0000000000000b40 T rdmacore52_0_dr_rule_send_update_list\n-0000000000002530 T rdmacore52_0_dr_rule_set_last_member\n+ U malloc\n+ U memcpy\n+ U mlx5dv_dr_domain_sync\n+ U rdmacore52_0_dr_arg_get_obj\n+ U rdmacore52_0_dr_arg_put_obj\n+ U rdmacore52_0_dr_ptrn_cache_get_pattern\n+ U rdmacore52_0_dr_ptrn_cache_put_pattern\n+ U rdmacore52_0_dr_rule_send_update_list\n U rdmacore52_0_dr_send_fill_and_append_ste_send_info\n- U rdmacore52_0_dr_send_postsend_htbl\n- U rdmacore52_0_dr_send_postsend_ste\n- U rdmacore52_0_dr_ste_build_ste_arr\n- U rdmacore52_0_dr_ste_calc_hash_index\n- U rdmacore52_0_dr_ste_copy_param\n- U rdmacore52_0_dr_ste_create_next_htbl\n- U rdmacore52_0_dr_ste_equal_tag\n- U rdmacore52_0_dr_ste_free\n- U rdmacore52_0_dr_ste_get_icm_addr\n+ U rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n+0000000000008da0 T rdmacore52_0_dr_ste_get_ctx_v1\n U rdmacore52_0_dr_ste_get_miss_list\n- U rdmacore52_0_dr_ste_get_miss_list_top\n U rdmacore52_0_dr_ste_htbl_alloc\n U rdmacore52_0_dr_ste_htbl_free\n- U rdmacore52_0_dr_ste_is_last_in_rule\n- U rdmacore52_0_dr_ste_set_bit_mask\n- U rdmacore52_0_dr_ste_set_formated_ste\n- U rdmacore52_0_dr_ste_set_hit_addr\n U rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl\n- U rdmacore52_0_dr_ste_set_hit_gvmi\n- U rdmacore52_0_dr_ste_set_miss_addr\n-\n-dr_ste_v2.c.o:\n-0000000000000000 b ctx_mutex\n-0000000000000000 r dr_ste_v2_action_modify_field_arr\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0_dr_ste_get_ctx_v1\n-0000000000000000 T rdmacore52_0_dr_ste_get_ctx_v2\n-0000000000000040 b ste_ctx_v2\n+0000000000008d50 T rdmacore52_0_dr_ste_v1_set_aso_ct\n+ U rdmacore52_0_dr_vports_table_get_vport_cap\n+0000000000000000 d ste_ctx_v1\n \n-buf.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n-000000000000006b r .LC10\n-0000000000000084 r .LC11\n-0000000000000015 r .LC2\n-0000000000000023 r .LC3\n-0000000000000028 r .LC4\n-000000000000002d r .LC5\n-0000000000000034 r .LC6\n-0000000000000042 r .LC7\n-000000000000004e r .LC8\n-0000000000000052 r .LC9\n+dr_buddy.c.o:\n U __errno_location\n- U __snprintf_chk\n- U __sprintf_chk\n- U __stack_chk_fail\n- U __vfprintf_chk\n- U abort\n U calloc\n U free\n- U fwrite\n- U getenv\n- U ibv_dofork_range\n- U ibv_dontfork_range\n- U malloc\n-0000000000000000 t mlx5_err\n- U mmap\n- U munmap\n- U posix_memalign\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_bitmap_fill_region\n- U rdmacore52_0_bitmap_find_free_region\n- U rdmacore52_0_bitmap_zero_region\n-0000000000000f50 T rdmacore52_0_mlx5_alloc_buf\n-00000000000005f0 T rdmacore52_0_mlx5_alloc_buf_contig\n-0000000000000100 T rdmacore52_0_mlx5_alloc_buf_extern\n-0000000000000840 T rdmacore52_0_mlx5_alloc_prefered_buf\n-0000000000000180 T rdmacore52_0_mlx5_free_actual_buf\n-0000000000000fd0 T rdmacore52_0_mlx5_free_buf\n-0000000000000f20 T rdmacore52_0_mlx5_free_buf_contig\n-00000000000000c0 T rdmacore52_0_mlx5_free_buf_extern\n-0000000000000450 T rdmacore52_0_mlx5_get_alloc_type\n-0000000000000400 T rdmacore52_0_mlx5_is_custom_alloc\n-0000000000000430 T rdmacore52_0_mlx5_is_extern_alloc\n- U shmat\n- U shmctl\n- U shmdt\n- U shmget\n- U stderr\n- U strcasecmp\n- U strerror\n- U strtol\n+ U rdmacore52_0_bitmap_find_first_bit\n+0000000000000260 T rdmacore52_0_dr_buddy_alloc_mem\n+00000000000001f0 T rdmacore52_0_dr_buddy_cleanup\n+0000000000000400 T rdmacore52_0_dr_buddy_free_mem\n+0000000000000000 T rdmacore52_0_dr_buddy_init\n \n mlx5_vfio.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000089 r .LC10\n 0000000000000093 r .LC11\n 00000000000000a0 r .LC12\n@@ -849,272 +1006,14 @@\n 0000000000000000 t vfio_devx_query_eqn\n 00000000000066c0 t vfio_devx_umem_dereg\n 00000000000068f0 t vfio_devx_umem_reg\n 0000000000003ef0 t vfio_devx_umem_reg_ex\n 0000000000000020 t vfio_init_obj\n U write\n \n-dr_ste.c.o:\n-0000000000000000 r .LC0\n- U __errno_location\n- U __memcpy_chk\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t dr_ste_build_empty_always_hit_tag\n-0000000000000010 t dr_ste_copy_mask_spec\n-0000000000000000 t dr_ste_free.cold\n- U free\n- U memcmp\n- U memcpy\n-0000000000003470 T mlx5dv_dr_aso_other_domain_link\n-00000000000034b0 T mlx5dv_dr_aso_other_domain_unlink\n- U rdmacore52_0_dr_crc32_slice8_calc\n- U rdmacore52_0_dr_icm_alloc_chunk\n- U rdmacore52_0_dr_icm_free_chunk\n- U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n- U rdmacore52_0_dr_icm_pool_get_chunk_mr_addr\n- U rdmacore52_0_dr_rule_set_last_member\n- U rdmacore52_0_dr_send_fill_and_append_ste_send_info\n- U rdmacore52_0_dr_send_postsend_action\n- U rdmacore52_0_dr_send_postsend_formated_htbl\n- U rdmacore52_0_dr_send_postsend_ste\n-0000000000001640 T rdmacore52_0_dr_ste_alloc_encap\n-0000000000001550 T rdmacore52_0_dr_ste_alloc_modify_hdr\n-00000000000030e0 T rdmacore52_0_dr_ste_build_def0\n-00000000000031e0 T rdmacore52_0_dr_ste_build_def16\n-0000000000003130 T rdmacore52_0_dr_ste_build_def2\n-0000000000003240 T rdmacore52_0_dr_ste_build_def22\n-0000000000003290 T rdmacore52_0_dr_ste_build_def24\n-00000000000032e0 T rdmacore52_0_dr_ste_build_def25\n-0000000000003330 T rdmacore52_0_dr_ste_build_def26\n-0000000000003380 T rdmacore52_0_dr_ste_build_def28\n-00000000000033d0 T rdmacore52_0_dr_ste_build_def33\n-0000000000003190 T rdmacore52_0_dr_ste_build_def6\n-0000000000002de0 T rdmacore52_0_dr_ste_build_empty_always_hit\n-0000000000002dc0 T rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4\n-0000000000002d60 T rdmacore52_0_dr_ste_build_eth_l2_dst\n-0000000000002d40 T rdmacore52_0_dr_ste_build_eth_l2_src\n-0000000000002cc0 T rdmacore52_0_dr_ste_build_eth_l2_src_dst\n-0000000000002d80 T rdmacore52_0_dr_ste_build_eth_l2_tnl\n-0000000000002d20 T rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple\n-0000000000002da0 T rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc\n-0000000000002ce0 T rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst\n-0000000000002d00 T rdmacore52_0_dr_ste_build_eth_l3_ipv6_src\n-0000000000002f10 T rdmacore52_0_dr_ste_build_eth_l4_misc\n-0000000000003050 T rdmacore52_0_dr_ste_build_flex_parser_0\n-0000000000003070 T rdmacore52_0_dr_ste_build_flex_parser_1\n-0000000000002ef0 T rdmacore52_0_dr_ste_build_general_purpose\n-00000000000030b0 T rdmacore52_0_dr_ste_build_ib_l4\n-0000000000002ed0 T rdmacore52_0_dr_ste_build_icmp\n-0000000000002e10 T rdmacore52_0_dr_ste_build_mpls\n-0000000000001700 T rdmacore52_0_dr_ste_build_pre_check\n-0000000000002ff0 T rdmacore52_0_dr_ste_build_register_0\n-0000000000003010 T rdmacore52_0_dr_ste_build_register_1\n-0000000000003030 T rdmacore52_0_dr_ste_build_src_gvmi_qpn\n-00000000000017d0 T rdmacore52_0_dr_ste_build_ste_arr\n-0000000000002f50 T rdmacore52_0_dr_ste_build_tnl_geneve\n-0000000000002f70 T rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt\n-0000000000002e90 T rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist\n-0000000000002e30 T rdmacore52_0_dr_ste_build_tnl_gre\n-0000000000002f90 T rdmacore52_0_dr_ste_build_tnl_gtpu\n-0000000000002fb0 T rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0\n-0000000000002fd0 T rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1\n-0000000000002e50 T rdmacore52_0_dr_ste_build_tnl_mpls_over_gre\n-0000000000002e70 T rdmacore52_0_dr_ste_build_tnl_mpls_over_udp\n-0000000000002f30 T rdmacore52_0_dr_ste_build_tnl_vxlan_gpe\n-0000000000003090 T rdmacore52_0_dr_ste_build_tunnel_header\n-0000000000000540 T rdmacore52_0_dr_ste_calc_hash_index\n-00000000000006a0 T rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n-0000000000001440 T rdmacore52_0_dr_ste_conv_modify_hdr_sw_field\n-0000000000001920 T rdmacore52_0_dr_ste_copy_param\n-0000000000001220 T rdmacore52_0_dr_ste_create_next_htbl\n-00000000000008a0 T rdmacore52_0_dr_ste_equal_tag\n-00000000000009f0 T rdmacore52_0_dr_ste_free\n-00000000000016f0 T rdmacore52_0_dr_ste_free_encap\n-0000000000001610 T rdmacore52_0_dr_ste_free_modify_hdr\n-0000000000003420 T rdmacore52_0_dr_ste_get_ctx\n- U rdmacore52_0_dr_ste_get_ctx_v0\n- U rdmacore52_0_dr_ste_get_ctx_v1\n- U rdmacore52_0_dr_ste_get_ctx_v2\n-00000000000007e0 T rdmacore52_0_dr_ste_get_icm_addr\n-0000000000000820 T rdmacore52_0_dr_ste_get_miss_list\n-0000000000000840 T rdmacore52_0_dr_ste_get_miss_list_top\n-0000000000000800 T rdmacore52_0_dr_ste_get_mr_addr\n-00000000000010c0 T rdmacore52_0_dr_ste_htbl_alloc\n-00000000000013d0 T rdmacore52_0_dr_ste_htbl_free\n-0000000000000f90 T rdmacore52_0_dr_ste_htbl_init_and_postsend\n-0000000000000890 T rdmacore52_0_dr_ste_is_last_in_rule\n-0000000000000910 T rdmacore52_0_dr_ste_prepare_for_postsend\n-0000000000001490 T rdmacore52_0_dr_ste_set_action_add\n-00000000000014c0 T rdmacore52_0_dr_ste_set_action_copy\n-0000000000001500 T rdmacore52_0_dr_ste_set_action_decap_l3_list\n-0000000000001460 T rdmacore52_0_dr_ste_set_action_set\n-0000000000001420 T rdmacore52_0_dr_ste_set_actions_rx\n-0000000000001400 T rdmacore52_0_dr_ste_set_actions_tx\n-0000000000000760 T rdmacore52_0_dr_ste_set_bit_mask\n-0000000000000940 T rdmacore52_0_dr_ste_set_formated_ste\n-00000000000007a0 T rdmacore52_0_dr_ste_set_hit_addr\n-00000000000008d0 T rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl\n-00000000000007c0 T rdmacore52_0_dr_ste_set_hit_gvmi\n-0000000000000780 T rdmacore52_0_dr_ste_set_miss_addr\n-\n-dr_vports.c.o:\n- U __errno_location\n- U __stack_chk_fail\n- U _mlx5dv_query_port\n- U calloc\n- U free\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_dr_devx_query_esw_vport_context\n- U rdmacore52_0_dr_devx_query_gvmi\n-00000000000003d0 T rdmacore52_0_dr_vports_table_add_wire\n-00000000000004c0 T rdmacore52_0_dr_vports_table_create\n-0000000000000420 T rdmacore52_0_dr_vports_table_del_wire\n-00000000000004f0 T rdmacore52_0_dr_vports_table_destroy\n-00000000000001b0 T rdmacore52_0_dr_vports_table_get_ib_port_cap\n-0000000000000000 T rdmacore52_0_dr_vports_table_get_vport_cap\n-\n-dr_action.c.o:\n-0000000000000000 r .LC0\n- U __errno_location\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t dr_action_aso_flow_meter_init\n-00000000000001e0 t dr_action_convert_to_fte_dest\n-0000000000000090 t dr_action_create_sampler\n- U free\n- U memcpy\n- U mlx5dv_create_flow_action_modify_header\n- U mlx5dv_create_flow_action_packet_reformat\n- U mlx5dv_create_steering_anchor\n- U mlx5dv_destroy_steering_anchor\n- U mlx5dv_devx_obj_destroy\n-0000000000001820 T mlx5dv_dr_action_create_aso\n-0000000000001410 T mlx5dv_dr_action_create_default_miss\n-00000000000028e0 T mlx5dv_dr_action_create_dest_array\n-00000000000014b0 T mlx5dv_dr_action_create_dest_devx_tir\n-0000000000002840 T mlx5dv_dr_action_create_dest_ib_port\n-0000000000001450 T mlx5dv_dr_action_create_dest_ibv_qp\n-0000000000001580 T mlx5dv_dr_action_create_dest_root_table\n-0000000000001510 T mlx5dv_dr_action_create_dest_table\n-0000000000002790 T mlx5dv_dr_action_create_dest_vport\n-00000000000013d0 T mlx5dv_dr_action_create_drop\n-00000000000017b0 T mlx5dv_dr_action_create_flow_counter\n-0000000000002670 T mlx5dv_dr_action_create_flow_meter\n-0000000000002f00 T mlx5dv_dr_action_create_flow_sampler\n-0000000000001f70 T mlx5dv_dr_action_create_modify_header\n-0000000000001b80 T mlx5dv_dr_action_create_packet_reformat\n-0000000000001ea0 T mlx5dv_dr_action_create_pop_vlan\n-0000000000001ee0 T mlx5dv_dr_action_create_push_vlan\n-0000000000001b20 T mlx5dv_dr_action_create_tag\n-0000000000002c70 T mlx5dv_dr_action_destroy\n-00000000000019f0 T mlx5dv_dr_action_modify_aso\n-0000000000002630 T mlx5dv_dr_action_modify_flow_meter\n- U mlx5dv_dr_matcher_create\n- U mlx5dv_dr_matcher_destroy\n- U mlx5dv_dr_rule_create\n- U mlx5dv_dr_rule_destroy\n- U mlx5dv_dr_table_create\n- U mlx5dv_dr_table_destroy\n-00000000000001a0 r next_action_state\n- U pthread_spin_lock\n- U pthread_spin_unlock\n-0000000000001260 T rdmacore52_0_dr_actions_build_attr\n-00000000000004b0 T rdmacore52_0_dr_actions_build_ste_arr\n-0000000000001f50 T rdmacore52_0_dr_actions_reformat_get_id\n- U rdmacore52_0_dr_arg_get_object_id\n- U rdmacore52_0_dr_devx_create_always_hit_ft\n- U rdmacore52_0_dr_devx_create_flow_sampler\n- U rdmacore52_0_dr_devx_create_meter\n- U rdmacore52_0_dr_devx_create_reformat_ctx\n- U rdmacore52_0_dr_devx_destroy_always_hit_ft\n- U rdmacore52_0_dr_devx_modify_meter\n- U rdmacore52_0_dr_devx_query_flow_sampler\n- U rdmacore52_0_dr_devx_query_flow_table\n- U rdmacore52_0_dr_devx_query_meter\n- U rdmacore52_0_dr_domain_is_support_sw_encap\n- U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n- U rdmacore52_0_dr_send_postsend_args\n- U rdmacore52_0_dr_ste_alloc_encap\n- U rdmacore52_0_dr_ste_alloc_modify_hdr\n- U rdmacore52_0_dr_ste_conv_modify_hdr_sw_field\n- U rdmacore52_0_dr_ste_free_encap\n- U rdmacore52_0_dr_ste_free_modify_hdr\n- U rdmacore52_0_dr_ste_set_action_add\n- U rdmacore52_0_dr_ste_set_action_copy\n- U rdmacore52_0_dr_ste_set_action_decap_l3_list\n- U rdmacore52_0_dr_ste_set_action_set\n- U rdmacore52_0_dr_ste_set_actions_rx\n- U rdmacore52_0_dr_ste_set_actions_tx\n- U rdmacore52_0_dr_vports_table_get_ib_port_cap\n- U rdmacore52_0_dr_vports_table_get_vport_cap\n- U rdmacore52_0_mlx5_destroy_flow_action\n-\n-dr_domain.c.o:\n- U __errno_location\n- U __stack_chk_fail\n- U calloc\n- U free\n- U ibv_alloc_pd\n- U ibv_dealloc_pd\n- U ibv_get_device_name\n- U ibv_query_device\n- U ibv_query_port\n- U mlx5dv_devx_alloc_uar\n- U mlx5dv_devx_free_uar\n-0000000000000c60 T mlx5dv_dr_domain_allow_duplicate_rules\n-00000000000000a0 T mlx5dv_dr_domain_create\n-0000000000000d30 T mlx5dv_dr_domain_destroy\n-0000000000000b90 T mlx5dv_dr_domain_set_reclaim_device_memory\n-0000000000000ab0 T mlx5dv_dr_domain_sync\n- U mlx5dv_init_obj\n- U pthread_spin_destroy\n- U pthread_spin_init\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_dr_arg_mngr_create\n- U rdmacore52_0_dr_arg_mngr_destroy\n- U rdmacore52_0_dr_crc32_init_table\n- U rdmacore52_0_dr_devx_query_device\n- U rdmacore52_0_dr_devx_query_esw_caps\n- U rdmacore52_0_dr_devx_query_esw_vport_context\n- U rdmacore52_0_dr_devx_sync_steering\n-0000000000000010 T rdmacore52_0_dr_domain_is_support_modify_hdr_cache\n-0000000000000030 T rdmacore52_0_dr_domain_is_support_ste_icm_size\n-0000000000000000 T rdmacore52_0_dr_domain_is_support_sw_encap\n-0000000000000050 T rdmacore52_0_dr_domain_set_max_ste_icm_size\n- U rdmacore52_0_dr_icm_pool_create\n- U rdmacore52_0_dr_icm_pool_destroy\n- U rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz\n- U rdmacore52_0_dr_icm_pool_sync_pool\n- U rdmacore52_0_dr_ptrn_mngr_create\n- U rdmacore52_0_dr_ptrn_mngr_destroy\n- U rdmacore52_0_dr_ptrn_sync_pool\n- U rdmacore52_0_dr_send_allow_fl\n- U rdmacore52_0_dr_send_ring_alloc\n- U rdmacore52_0_dr_send_ring_force_drain\n- U rdmacore52_0_dr_send_ring_free\n- U rdmacore52_0_dr_ste_get_ctx\n- U rdmacore52_0_dr_vports_table_add_wire\n- U rdmacore52_0_dr_vports_table_create\n- U rdmacore52_0_dr_vports_table_del_wire\n- U rdmacore52_0_dr_vports_table_destroy\n- U rdmacore52_0_dr_vports_table_get_ib_port_cap\n-\n-dr_buddy.c.o:\n- U __errno_location\n- U calloc\n- U free\n- U rdmacore52_0_bitmap_find_first_bit\n-0000000000000260 T rdmacore52_0_dr_buddy_alloc_mem\n-00000000000001f0 T rdmacore52_0_dr_buddy_cleanup\n-0000000000000400 T rdmacore52_0_dr_buddy_free_mem\n-0000000000000000 T rdmacore52_0_dr_buddy_init\n-\n mlx5.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000018 r .LC10\n 0000000000000012 r .LC11\n 0000000000000022 r .LC12\n 0000000000000026 r .LC13\n@@ -1343,121 +1242,107 @@\n U stderr\n U strchr\n U strncpy\n U strrchr\n U sysconf\n 0000000000000000 D verbs_provider_mlx5\n \n-dr_matcher.c.o:\n+dr_rule.c.o:\n+0000000000000000 r .LC0\n U __errno_location\n+ U __memcpy_chk\n U __stack_chk_fail\n U calloc\n-0000000000000320 t dr_matcher_connect\n-0000000000000000 t dr_matcher_copy_mask\n-0000000000002a80 t dr_matcher_init_nic\n-00000000000004a0 t dr_matcher_is_mask_consumed\n-00000000000001b0 t dr_matcher_set_nic_matcher_layout\n-0000000000000980 t dr_matcher_set_ste_builders\n-00000000000008e0 t dr_matcher_uninit_nic\n+0000000000000000 t dr_rule_clean_rule_members\n+0000000000001e80 t dr_rule_create_rule\n+0000000000000df0 t dr_rule_create_rule_nic\n+00000000000000d0 t dr_rule_rehash_htbl_common\n U free\n- U memcpy\n- U mlx5dv_create_flow_matcher\n- U mlx5dv_destroy_flow_matcher\n- U mlx5dv_devx_obj_destroy\n-0000000000002c20 T mlx5dv_dr_matcher_create\n-0000000000003380 T mlx5dv_dr_matcher_destroy\n-0000000000002b70 T mlx5dv_dr_matcher_set_layout\n+00000000000025b0 T mlx5dv_dr_rule_create\n+00000000000027b0 T mlx5dv_dr_rule_destroy\n U pthread_spin_lock\n U pthread_spin_unlock\n- U rdmacore52_0_dr_devx_create_definer\n- U rdmacore52_0_dr_domain_is_support_ste_icm_size\n- U rdmacore52_0_dr_domain_set_max_ste_icm_size\n+ U rdmacore52_0__mlx5dv_create_flow\n+ U rdmacore52_0_dr_actions_build_attr\n+ U rdmacore52_0_dr_actions_build_ste_arr\n U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n- U rdmacore52_0_dr_rule_rehash_matcher_s_anchor\n- U rdmacore52_0_dr_send_ring_force_drain\n- U rdmacore52_0_dr_ste_build_def0\n- U rdmacore52_0_dr_ste_build_def16\n- U rdmacore52_0_dr_ste_build_def2\n- U rdmacore52_0_dr_ste_build_def22\n- U rdmacore52_0_dr_ste_build_def24\n- U rdmacore52_0_dr_ste_build_def25\n- U rdmacore52_0_dr_ste_build_def26\n- U rdmacore52_0_dr_ste_build_def28\n- U rdmacore52_0_dr_ste_build_def33\n- U rdmacore52_0_dr_ste_build_def6\n- U rdmacore52_0_dr_ste_build_empty_always_hit\n- U rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4\n- U rdmacore52_0_dr_ste_build_eth_l2_dst\n- U rdmacore52_0_dr_ste_build_eth_l2_src\n- U rdmacore52_0_dr_ste_build_eth_l2_src_dst\n- U rdmacore52_0_dr_ste_build_eth_l2_tnl\n- U rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple\n- U rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc\n- U rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst\n- U rdmacore52_0_dr_ste_build_eth_l3_ipv6_src\n- U rdmacore52_0_dr_ste_build_eth_l4_misc\n- U rdmacore52_0_dr_ste_build_flex_parser_0\n- U rdmacore52_0_dr_ste_build_flex_parser_1\n- U rdmacore52_0_dr_ste_build_general_purpose\n- U rdmacore52_0_dr_ste_build_ib_l4\n- U rdmacore52_0_dr_ste_build_icmp\n- U rdmacore52_0_dr_ste_build_mpls\n- U rdmacore52_0_dr_ste_build_pre_check\n- U rdmacore52_0_dr_ste_build_register_0\n- U rdmacore52_0_dr_ste_build_register_1\n- U rdmacore52_0_dr_ste_build_src_gvmi_qpn\n- U rdmacore52_0_dr_ste_build_tnl_geneve\n- U rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt\n- U rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist\n- U rdmacore52_0_dr_ste_build_tnl_gre\n- U rdmacore52_0_dr_ste_build_tnl_gtpu\n- U rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0\n- U rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1\n- U rdmacore52_0_dr_ste_build_tnl_mpls_over_gre\n- U rdmacore52_0_dr_ste_build_tnl_mpls_over_udp\n- U rdmacore52_0_dr_ste_build_tnl_vxlan_gpe\n- U rdmacore52_0_dr_ste_build_tunnel_header\n+0000000000002550 T rdmacore52_0_dr_rule_get_reverse_rule_members\n+0000000000002470 T rdmacore52_0_dr_rule_rehash_matcher_s_anchor\n+0000000000000b40 T rdmacore52_0_dr_rule_send_update_list\n+0000000000002530 T rdmacore52_0_dr_rule_set_last_member\n+ U rdmacore52_0_dr_send_fill_and_append_ste_send_info\n+ U rdmacore52_0_dr_send_postsend_htbl\n+ U rdmacore52_0_dr_send_postsend_ste\n+ U rdmacore52_0_dr_ste_build_ste_arr\n+ U rdmacore52_0_dr_ste_calc_hash_index\n U rdmacore52_0_dr_ste_copy_param\n+ U rdmacore52_0_dr_ste_create_next_htbl\n+ U rdmacore52_0_dr_ste_equal_tag\n+ U rdmacore52_0_dr_ste_free\n+ U rdmacore52_0_dr_ste_get_icm_addr\n+ U rdmacore52_0_dr_ste_get_miss_list\n+ U rdmacore52_0_dr_ste_get_miss_list_top\n U rdmacore52_0_dr_ste_htbl_alloc\n U rdmacore52_0_dr_ste_htbl_free\n- U rdmacore52_0_dr_ste_htbl_init_and_postsend\n+ U rdmacore52_0_dr_ste_is_last_in_rule\n+ U rdmacore52_0_dr_ste_set_bit_mask\n+ U rdmacore52_0_dr_ste_set_formated_ste\n+ U rdmacore52_0_dr_ste_set_hit_addr\n+ U rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl\n+ U rdmacore52_0_dr_ste_set_hit_gvmi\n+ U rdmacore52_0_dr_ste_set_miss_addr\n \n-dr_icm_pool.c.o:\n-0000000000000000 r .LC0\n-0000000000000008 r .LC1\n+dbrec.c.o:\n+ U free\n+ U malloc\n+ U memset\n+0000000000000000 t mlx5_alloc_dbrec.cold\n+000000000000000a t mlx5_free_db.cold\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0_cl_qmap_get\n+ U rdmacore52_0_cl_qmap_insert\n+ U rdmacore52_0_cl_qmap_remove_item\n+ U rdmacore52_0_mlx5_alloc_buf\n+ U rdmacore52_0_mlx5_alloc_buf_extern\n+0000000000000000 T rdmacore52_0_mlx5_alloc_dbrec\n+ U rdmacore52_0_mlx5_free_buf\n+ U rdmacore52_0_mlx5_free_buf_extern\n+0000000000000270 T rdmacore52_0_mlx5_free_db\n+ U rdmacore52_0_mlx5_is_custom_alloc\n+ U rdmacore52_0_mlx5_is_extern_alloc\n+\n+dr_arg.c.o:\n U __errno_location\n U __stack_chk_fail\n U calloc\n-0000000000000000 t dr_icm_buddy_destroy\n-0000000000000160 t dr_icm_pool_sync_pool_buddies\n+0000000000000000 t dr_arg_pool_alloc_objs\n U free\n- U ibv_dereg_mr\n- U malloc\n- U memset\n- U mlx5dv_alloc_dm\n- U pthread_spin_destroy\n- U pthread_spin_init\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_dr_buddy_alloc_mem\n- U rdmacore52_0_dr_buddy_cleanup\n- U rdmacore52_0_dr_buddy_free_mem\n- U rdmacore52_0_dr_buddy_init\n- U rdmacore52_0_dr_devx_sync_steering\n-00000000000003f0 T rdmacore52_0_dr_icm_alloc_chunk\n-0000000000000a20 T rdmacore52_0_dr_icm_free_chunk\n-0000000000000b90 T rdmacore52_0_dr_icm_pool_create\n-0000000000000ce0 T rdmacore52_0_dr_icm_pool_destroy\n-0000000000000ae0 T rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n-0000000000000b30 T rdmacore52_0_dr_icm_pool_get_chunk_mr_addr\n-0000000000000b70 T rdmacore52_0_dr_icm_pool_get_chunk_rkey\n-0000000000000ab0 T rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz\n-00000000000003a0 T rdmacore52_0_dr_icm_pool_sync_pool\n- U rdmacore52_0_dr_send_ring_force_drain\n- U rdmacore52_0_mlx5_free_dm\n+ U mlx5dv_devx_obj_destroy\n+ U pthread_mutex_destroy\n+ U pthread_mutex_init\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+00000000000001c0 T rdmacore52_0_dr_arg_get_obj\n+00000000000001b0 T rdmacore52_0_dr_arg_get_object_id\n+0000000000000390 T rdmacore52_0_dr_arg_mngr_create\n+0000000000000500 T rdmacore52_0_dr_arg_mngr_destroy\n+0000000000000330 T rdmacore52_0_dr_arg_put_obj\n+ U rdmacore52_0_dr_devx_create_modify_header_arg\n+ U rdmacore52_0_dr_domain_is_support_modify_hdr_cache\n+ U rdmacore52_0_dr_send_postsend_args\n+\n+dr_ste_v2.c.o:\n+0000000000000000 b ctx_mutex\n+0000000000000000 r dr_ste_v2_action_modify_field_arr\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0_dr_ste_get_ctx_v1\n+0000000000000000 T rdmacore52_0_dr_ste_get_ctx_v2\n+0000000000000040 b ste_ctx_v2\n \n qp.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC23\n 0000000000000090 r .LC3\n 0000000000000000 r .LC4\n 0000000000000158 r CSWTCH.147\n@@ -1546,61 +1431,134 @@\n 0000000000009070 T rdmacore52_0_mlx5_qp_fill_wr_complete_real\n 0000000000009090 T rdmacore52_0_mlx5_qp_fill_wr_pfns\n 000000000000a7a0 T rdmacore52_0_mlx5_store_qp\n 000000000000a730 T rdmacore52_0_mlx5_use_huge\n U stderr\n 0000000000006970 t umr_wqe_finalize\n \n-dr_send.c.o:\n-0000000000000000 r .LC0\n-0000000000000008 r .LC1\n-0000000000000010 r .LC2\n-0000000000000018 r .LC3\n+dr_vports.c.o:\n U __errno_location\n U __stack_chk_fail\n+ U _mlx5dv_query_port\n U calloc\n-0000000000000290 t dr_postsend_icm_data\n-0000000000000000 t dr_rdma_segments\n U free\n- U ibv_create_cq\n- U ibv_dereg_mr\n- U ibv_destroy_cq\n- U ibv_reg_mr\n- U malloc\n- U memcpy\n- U memset\n- U mlx5dv_devx_obj_destroy\n- U mlx5dv_devx_umem_dereg\n- U mlx5dv_devx_umem_reg\n- U mlx5dv_init_obj\n- U posix_memalign\n- U pthread_spin_init\n U pthread_spin_lock\n U pthread_spin_unlock\n- U rdmacore52_0_dr_devx_create_qp\n- U rdmacore52_0_dr_devx_modify_qp_init2rtr\n- U rdmacore52_0_dr_devx_modify_qp_rst2init\n- U rdmacore52_0_dr_devx_modify_qp_rtr2rts\n- U rdmacore52_0_dr_devx_query_gid\n+ U rdmacore52_0_dr_devx_query_esw_vport_context\n+ U rdmacore52_0_dr_devx_query_gvmi\n+00000000000003d0 T rdmacore52_0_dr_vports_table_add_wire\n+00000000000004c0 T rdmacore52_0_dr_vports_table_create\n+0000000000000420 T rdmacore52_0_dr_vports_table_del_wire\n+00000000000004f0 T rdmacore52_0_dr_vports_table_destroy\n+00000000000001b0 T rdmacore52_0_dr_vports_table_get_ib_port_cap\n+0000000000000000 T rdmacore52_0_dr_vports_table_get_vport_cap\n+\n+dr_ste.c.o:\n+0000000000000000 r .LC0\n+ U __errno_location\n+ U __memcpy_chk\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t dr_ste_build_empty_always_hit_tag\n+0000000000000010 t dr_ste_copy_mask_spec\n+0000000000000000 t dr_ste_free.cold\n+ U free\n+ U memcmp\n+ U memcpy\n+0000000000003470 T mlx5dv_dr_aso_other_domain_link\n+00000000000034b0 T mlx5dv_dr_aso_other_domain_unlink\n+ U rdmacore52_0_dr_crc32_slice8_calc\n+ U rdmacore52_0_dr_icm_alloc_chunk\n+ U rdmacore52_0_dr_icm_free_chunk\n+ U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n U rdmacore52_0_dr_icm_pool_get_chunk_mr_addr\n- U rdmacore52_0_dr_icm_pool_get_chunk_rkey\n-00000000000012a0 T rdmacore52_0_dr_send_allow_fl\n-0000000000000620 T rdmacore52_0_dr_send_fill_and_append_ste_send_info\n-0000000000000fc0 T rdmacore52_0_dr_send_postsend_action\n-00000000000011b0 T rdmacore52_0_dr_send_postsend_args\n-0000000000000ce0 T rdmacore52_0_dr_send_postsend_formated_htbl\n-0000000000000760 T rdmacore52_0_dr_send_postsend_htbl\n-00000000000010d0 T rdmacore52_0_dr_send_postsend_pattern\n-0000000000000690 T rdmacore52_0_dr_send_postsend_ste\n-00000000000013a0 T rdmacore52_0_dr_send_ring_alloc\n-0000000000001ce0 T rdmacore52_0_dr_send_ring_force_drain\n-00000000000012c0 T rdmacore52_0_dr_send_ring_free\n- U rdmacore52_0_dr_ste_get_mr_addr\n- U rdmacore52_0_dr_ste_prepare_for_postsend\n- U sysconf\n+ U rdmacore52_0_dr_rule_set_last_member\n+ U rdmacore52_0_dr_send_fill_and_append_ste_send_info\n+ U rdmacore52_0_dr_send_postsend_action\n+ U rdmacore52_0_dr_send_postsend_formated_htbl\n+ U rdmacore52_0_dr_send_postsend_ste\n+0000000000001640 T rdmacore52_0_dr_ste_alloc_encap\n+0000000000001550 T rdmacore52_0_dr_ste_alloc_modify_hdr\n+00000000000030e0 T rdmacore52_0_dr_ste_build_def0\n+00000000000031e0 T rdmacore52_0_dr_ste_build_def16\n+0000000000003130 T rdmacore52_0_dr_ste_build_def2\n+0000000000003240 T rdmacore52_0_dr_ste_build_def22\n+0000000000003290 T rdmacore52_0_dr_ste_build_def24\n+00000000000032e0 T rdmacore52_0_dr_ste_build_def25\n+0000000000003330 T rdmacore52_0_dr_ste_build_def26\n+0000000000003380 T rdmacore52_0_dr_ste_build_def28\n+00000000000033d0 T rdmacore52_0_dr_ste_build_def33\n+0000000000003190 T rdmacore52_0_dr_ste_build_def6\n+0000000000002de0 T rdmacore52_0_dr_ste_build_empty_always_hit\n+0000000000002dc0 T rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4\n+0000000000002d60 T rdmacore52_0_dr_ste_build_eth_l2_dst\n+0000000000002d40 T rdmacore52_0_dr_ste_build_eth_l2_src\n+0000000000002cc0 T rdmacore52_0_dr_ste_build_eth_l2_src_dst\n+0000000000002d80 T rdmacore52_0_dr_ste_build_eth_l2_tnl\n+0000000000002d20 T rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple\n+0000000000002da0 T rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc\n+0000000000002ce0 T rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst\n+0000000000002d00 T rdmacore52_0_dr_ste_build_eth_l3_ipv6_src\n+0000000000002f10 T rdmacore52_0_dr_ste_build_eth_l4_misc\n+0000000000003050 T rdmacore52_0_dr_ste_build_flex_parser_0\n+0000000000003070 T rdmacore52_0_dr_ste_build_flex_parser_1\n+0000000000002ef0 T rdmacore52_0_dr_ste_build_general_purpose\n+00000000000030b0 T rdmacore52_0_dr_ste_build_ib_l4\n+0000000000002ed0 T rdmacore52_0_dr_ste_build_icmp\n+0000000000002e10 T rdmacore52_0_dr_ste_build_mpls\n+0000000000001700 T rdmacore52_0_dr_ste_build_pre_check\n+0000000000002ff0 T rdmacore52_0_dr_ste_build_register_0\n+0000000000003010 T rdmacore52_0_dr_ste_build_register_1\n+0000000000003030 T rdmacore52_0_dr_ste_build_src_gvmi_qpn\n+00000000000017d0 T rdmacore52_0_dr_ste_build_ste_arr\n+0000000000002f50 T rdmacore52_0_dr_ste_build_tnl_geneve\n+0000000000002f70 T rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt\n+0000000000002e90 T rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist\n+0000000000002e30 T rdmacore52_0_dr_ste_build_tnl_gre\n+0000000000002f90 T rdmacore52_0_dr_ste_build_tnl_gtpu\n+0000000000002fb0 T rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0\n+0000000000002fd0 T rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1\n+0000000000002e50 T rdmacore52_0_dr_ste_build_tnl_mpls_over_gre\n+0000000000002e70 T rdmacore52_0_dr_ste_build_tnl_mpls_over_udp\n+0000000000002f30 T rdmacore52_0_dr_ste_build_tnl_vxlan_gpe\n+0000000000003090 T rdmacore52_0_dr_ste_build_tunnel_header\n+0000000000000540 T rdmacore52_0_dr_ste_calc_hash_index\n+00000000000006a0 T rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n+0000000000001440 T rdmacore52_0_dr_ste_conv_modify_hdr_sw_field\n+0000000000001920 T rdmacore52_0_dr_ste_copy_param\n+0000000000001220 T rdmacore52_0_dr_ste_create_next_htbl\n+00000000000008a0 T rdmacore52_0_dr_ste_equal_tag\n+00000000000009f0 T rdmacore52_0_dr_ste_free\n+00000000000016f0 T rdmacore52_0_dr_ste_free_encap\n+0000000000001610 T rdmacore52_0_dr_ste_free_modify_hdr\n+0000000000003420 T rdmacore52_0_dr_ste_get_ctx\n+ U rdmacore52_0_dr_ste_get_ctx_v0\n+ U rdmacore52_0_dr_ste_get_ctx_v1\n+ U rdmacore52_0_dr_ste_get_ctx_v2\n+00000000000007e0 T rdmacore52_0_dr_ste_get_icm_addr\n+0000000000000820 T rdmacore52_0_dr_ste_get_miss_list\n+0000000000000840 T rdmacore52_0_dr_ste_get_miss_list_top\n+0000000000000800 T rdmacore52_0_dr_ste_get_mr_addr\n+00000000000010c0 T rdmacore52_0_dr_ste_htbl_alloc\n+00000000000013d0 T rdmacore52_0_dr_ste_htbl_free\n+0000000000000f90 T rdmacore52_0_dr_ste_htbl_init_and_postsend\n+0000000000000890 T rdmacore52_0_dr_ste_is_last_in_rule\n+0000000000000910 T rdmacore52_0_dr_ste_prepare_for_postsend\n+0000000000001490 T rdmacore52_0_dr_ste_set_action_add\n+00000000000014c0 T rdmacore52_0_dr_ste_set_action_copy\n+0000000000001500 T rdmacore52_0_dr_ste_set_action_decap_l3_list\n+0000000000001460 T rdmacore52_0_dr_ste_set_action_set\n+0000000000001420 T rdmacore52_0_dr_ste_set_actions_rx\n+0000000000001400 T rdmacore52_0_dr_ste_set_actions_tx\n+0000000000000760 T rdmacore52_0_dr_ste_set_bit_mask\n+0000000000000940 T rdmacore52_0_dr_ste_set_formated_ste\n+00000000000007a0 T rdmacore52_0_dr_ste_set_hit_addr\n+00000000000008d0 T rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl\n+00000000000007c0 T rdmacore52_0_dr_ste_set_hit_gvmi\n+0000000000000780 T rdmacore52_0_dr_ste_set_miss_addr\n \n srq.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000000 r .LC2\n U __errno_location\n U __stack_chk_fail\n@@ -1623,32 +1581,64 @@\n 00000000000000a0 T rdmacore52_0_mlx5_free_srq_wqe\n U rdmacore52_0_mlx5_get_alloc_type\n 0000000000000450 T rdmacore52_0_mlx5_post_srq_recv\n 0000000000000c60 T rdmacore52_0_mlx5_store_srq\n 0000000000000160 T rdmacore52_0_srq_cooldown_wqe\n U stderr\n \n-dr_table.c.o:\n+dr_domain.c.o:\n U __errno_location\n U __stack_chk_fail\n U calloc\n-0000000000000000 t dr_table_init_nic\n-00000000000000b0 t dr_table_uninit\n U free\n- U mlx5dv_devx_obj_destroy\n-0000000000000100 T mlx5dv_dr_table_create\n-0000000000000440 T mlx5dv_dr_table_destroy\n+ U ibv_alloc_pd\n+ U ibv_dealloc_pd\n+ U ibv_get_device_name\n+ U ibv_query_device\n+ U ibv_query_port\n+ U mlx5dv_devx_alloc_uar\n+ U mlx5dv_devx_free_uar\n+0000000000000c60 T mlx5dv_dr_domain_allow_duplicate_rules\n+00000000000000a0 T mlx5dv_dr_domain_create\n+0000000000000d30 T mlx5dv_dr_domain_destroy\n+0000000000000b90 T mlx5dv_dr_domain_set_reclaim_device_memory\n+0000000000000ab0 T mlx5dv_dr_domain_sync\n+ U mlx5dv_init_obj\n+ U pthread_spin_destroy\n+ U pthread_spin_init\n U pthread_spin_lock\n U pthread_spin_unlock\n- U rdmacore52_0_dr_devx_create_flow_table\n- U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n+ U rdmacore52_0_dr_arg_mngr_create\n+ U rdmacore52_0_dr_arg_mngr_destroy\n+ U rdmacore52_0_dr_crc32_init_table\n+ U rdmacore52_0_dr_devx_query_device\n+ U rdmacore52_0_dr_devx_query_esw_caps\n+ U rdmacore52_0_dr_devx_query_esw_vport_context\n+ U rdmacore52_0_dr_devx_sync_steering\n+0000000000000010 T rdmacore52_0_dr_domain_is_support_modify_hdr_cache\n+0000000000000030 T rdmacore52_0_dr_domain_is_support_ste_icm_size\n+0000000000000000 T rdmacore52_0_dr_domain_is_support_sw_encap\n+0000000000000050 T rdmacore52_0_dr_domain_set_max_ste_icm_size\n+ U rdmacore52_0_dr_icm_pool_create\n+ U rdmacore52_0_dr_icm_pool_destroy\n+ U rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz\n+ U rdmacore52_0_dr_icm_pool_sync_pool\n+ U rdmacore52_0_dr_ptrn_mngr_create\n+ U rdmacore52_0_dr_ptrn_mngr_destroy\n+ U rdmacore52_0_dr_ptrn_sync_pool\n+ U rdmacore52_0_dr_send_allow_fl\n+ U rdmacore52_0_dr_send_ring_alloc\n U rdmacore52_0_dr_send_ring_force_drain\n- U rdmacore52_0_dr_ste_htbl_alloc\n- U rdmacore52_0_dr_ste_htbl_free\n- U rdmacore52_0_dr_ste_htbl_init_and_postsend\n+ U rdmacore52_0_dr_send_ring_free\n+ U rdmacore52_0_dr_ste_get_ctx\n+ U rdmacore52_0_dr_vports_table_add_wire\n+ U rdmacore52_0_dr_vports_table_create\n+ U rdmacore52_0_dr_vports_table_del_wire\n+ U rdmacore52_0_dr_vports_table_destroy\n+ U rdmacore52_0_dr_vports_table_get_ib_port_cap\n \n verbs.c.o:\n 0000000000000000 r .LC19\n 0000000000000000 r .LC23\n 0000000000000008 r .LC24\n 000000000000000e r .LC27\n 0000000000000021 r .LC28\n@@ -2007,227 +1997,350 @@\n U rdmacore52_0_verbs_allow_disassociate_destroy\n U rdmacore52_0_verbs_init_cq\n U read\n 0000000000000000 t sq_overhead\n U stderr\n U strtol\n \n-dr_ste_v1.c.o:\n+dr_send.c.o:\n+0000000000000000 r .LC0\n+0000000000000008 r .LC1\n+0000000000000010 r .LC2\n+0000000000000018 r .LC3\n U __errno_location\n U __stack_chk_fail\n U calloc\n-0000000000000060 r dr_ste_v1_action_modify_field_arr\n-0000000000000000 r dr_ste_v1_action_modify_flex_field_arr\n-0000000000004be0 t dr_ste_v1_alloc_modify_hdr_ptrn_arg\n-00000000000054d0 t dr_ste_v1_aso_other_domain_link\n-0000000000004ca0 t dr_ste_v1_aso_other_domain_unlink\n-0000000000004ba0 t dr_ste_v1_build_def0_init\n-0000000000001d30 t dr_ste_v1_build_def0_tag\n-0000000000006520 t dr_ste_v1_build_def16_init\n-0000000000003b50 t dr_ste_v1_build_def16_tag\n-00000000000078b0 t dr_ste_v1_build_def22_init\n-0000000000001370 t dr_ste_v1_build_def22_tag\n-0000000000007bf0 t dr_ste_v1_build_def24_init\n-0000000000001070 t dr_ste_v1_build_def24_tag\n-0000000000007f30 t dr_ste_v1_build_def25_init\n-0000000000000d50 t dr_ste_v1_build_def25_tag\n-0000000000004b50 t dr_ste_v1_build_def26_init\n-0000000000000980 t dr_ste_v1_build_def26_tag\n-0000000000004af0 t dr_ste_v1_build_def28_init\n-00000000000005a0 t dr_ste_v1_build_def28_tag\n-0000000000001cf0 t dr_ste_v1_build_def2_init\n-00000000000018b0 t dr_ste_v1_build_def2_tag\n-0000000000004ab0 t dr_ste_v1_build_def33_init\n-00000000000001a0 t dr_ste_v1_build_def33_tag\n-0000000000006a80 t dr_ste_v1_build_def6_init\n-0000000000001640 t dr_ste_v1_build_def6_tag\n-00000000000041d0 t dr_ste_v1_build_eth_ipv6_l3_l4_init\n-0000000000002720 t dr_ste_v1_build_eth_ipv6_l3_l4_tag\n-0000000000004380 t dr_ste_v1_build_eth_l2_dst_init\n-00000000000038f0 t dr_ste_v1_build_eth_l2_dst_tag\n-0000000000004670 t dr_ste_v1_build_eth_l2_src_dst_init\n-00000000000039a0 t dr_ste_v1_build_eth_l2_src_dst_tag\n-0000000000006790 t dr_ste_v1_build_eth_l2_src_init\n-00000000000035b0 t dr_ste_v1_build_eth_l2_src_or_dst_tag\n-0000000000003950 t dr_ste_v1_build_eth_l2_src_tag\n-0000000000004210 t dr_ste_v1_build_eth_l2_tnl_init\n-00000000000033f0 t dr_ste_v1_build_eth_l2_tnl_tag\n-0000000000008ad0 t dr_ste_v1_build_eth_l3_ipv4_5_tuple_init\n-0000000000002a80 t dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag\n-00000000000052f0 t dr_ste_v1_build_eth_l3_ipv4_misc_init\n-0000000000002a20 t dr_ste_v1_build_eth_l3_ipv4_misc_tag\n-00000000000053b0 t dr_ste_v1_build_eth_l3_ipv6_dst_init\n-0000000000002ce0 t dr_ste_v1_build_eth_l3_ipv6_dst_tag\n-0000000000005440 t dr_ste_v1_build_eth_l3_ipv6_src_init\n-0000000000002d40 t dr_ste_v1_build_eth_l3_ipv6_src_tag\n-0000000000004e10 t dr_ste_v1_build_eth_l4_misc_init\n-0000000000004930 t dr_ste_v1_build_eth_l4_misc_tag\n-0000000000005f50 t dr_ste_v1_build_felx_parser_tag\n-0000000000006300 t dr_ste_v1_build_flex_parser_0_init\n-00000000000062b0 t dr_ste_v1_build_flex_parser_1_init\n-0000000000005b40 t dr_ste_v1_build_flex_parser_tnl_geneve_init\n-0000000000002340 t dr_ste_v1_build_flex_parser_tnl_geneve_tag\n-0000000000003fa0 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init\n-0000000000002300 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_tag\n-0000000000004000 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init\n-0000000000003100 t dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_tag\n-0000000000004f90 t dr_ste_v1_build_flex_parser_tnl_gtpu_init\n-0000000000002290 t dr_ste_v1_build_flex_parser_tnl_gtpu_tag\n-00000000000051a0 t dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init\n-00000000000048b0 t dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag\n-0000000000004060 t dr_ste_v1_build_general_purpose_init\n-00000000000023d0 t dr_ste_v1_build_general_purpose_tag\n-0000000000005250 t dr_ste_v1_build_ib_l4_init\n-00000000000047b0 t dr_ste_v1_build_ib_l4_tag\n-0000000000005030 t dr_ste_v1_build_icmp_init\n-00000000000023f0 t dr_ste_v1_build_icmp_tag\n-0000000000006350 t dr_ste_v1_build_mpls_init\n-0000000000002570 t dr_ste_v1_build_mpls_tag\n-0000000000003f10 t dr_ste_v1_build_register_0_init\n-0000000000002220 t dr_ste_v1_build_register_0_tag\n-0000000000003e80 t dr_ste_v1_build_register_1_init\n-00000000000021b0 t dr_ste_v1_build_register_1_tag\n-0000000000003e10 t dr_ste_v1_build_src_gvmi_qpn_init\n-0000000000003d60 t dr_ste_v1_build_src_gvmi_qpn_tag\n-0000000000005e50 t dr_ste_v1_build_tnl_gre_init\n-0000000000002490 t dr_ste_v1_build_tnl_gre_tag\n-0000000000005c00 t dr_ste_v1_build_tnl_gtpu_flex_parser_0_init\n-0000000000003000 t dr_ste_v1_build_tnl_gtpu_flex_parser_0_tag\n-0000000000005d30 t dr_ste_v1_build_tnl_gtpu_flex_parser_1_init\n-0000000000002f10 t dr_ste_v1_build_tnl_gtpu_flex_parser_1_tag\n-0000000000004140 t dr_ste_v1_build_tnl_mpls_over_gre_init\n-00000000000031b0 t dr_ste_v1_build_tnl_mpls_over_gre_tag\n-00000000000040b0 t dr_ste_v1_build_tnl_mpls_over_udp_init\n-0000000000003140 t dr_ste_v1_build_tnl_mpls_over_udp_tag\n-0000000000004eb0 t dr_ste_v1_build_tunnel_header_init\n-0000000000004830 t dr_ste_v1_build_tunnel_header_tag\n-00000000000032a0 t dr_ste_v1_dealloc_modify_hdr_ptrn_arg\n-0000000000004a30 t dr_ste_v1_get_action_hw_field\n-0000000000002ee0 t dr_ste_v1_get_byte_mask\n-0000000000002ef0 t dr_ste_v1_get_miss_addr\n-0000000000000000 t dr_ste_v1_get_next_lu_type\n-0000000000002e50 t dr_ste_v1_init\n-0000000000003270 t dr_ste_v1_prepare_for_postsend\n-0000000000000080 t dr_ste_v1_set_action_add\n-0000000000000020 t dr_ste_v1_set_action_copy\n-00000000000032d0 t dr_ste_v1_set_action_decap_l3_list\n-00000000000000c0 t dr_ste_v1_set_action_set\n-0000000000006d00 t dr_ste_v1_set_actions_rx\n-00000000000083c0 t dr_ste_v1_set_actions_tx\n-0000000000003220 t dr_ste_v1_set_aso_ct_cross_dmn\n-0000000000004c80 t dr_ste_v1_set_byte_mask\n-00000000000050f0 t dr_ste_v1_set_ctrl_always_hit_htbl\n-0000000000002de0 t dr_ste_v1_set_ctrl_always_miss\n-0000000000000120 t dr_ste_v1_set_hit_addr\n-0000000000000100 t dr_ste_v1_set_hit_gvmi\n-0000000000000160 t dr_ste_v1_set_miss_addr\n-0000000000002da0 t dr_ste_v1_set_next_lu_type\n-00000000000049b0 t dr_ste_v1_set_rewrite_actions\n+0000000000000290 t dr_postsend_icm_data\n+0000000000000000 t dr_rdma_segments\n U free\n+ U ibv_create_cq\n+ U ibv_dereg_mr\n+ U ibv_destroy_cq\n+ U ibv_reg_mr\n U malloc\n U memcpy\n- U mlx5dv_dr_domain_sync\n- U rdmacore52_0_dr_arg_get_obj\n- U rdmacore52_0_dr_arg_put_obj\n- U rdmacore52_0_dr_ptrn_cache_get_pattern\n- U rdmacore52_0_dr_ptrn_cache_put_pattern\n- U rdmacore52_0_dr_rule_send_update_list\n- U rdmacore52_0_dr_send_fill_and_append_ste_send_info\n- U rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n-0000000000008da0 T rdmacore52_0_dr_ste_get_ctx_v1\n- U rdmacore52_0_dr_ste_get_miss_list\n+ U memset\n+ U mlx5dv_devx_obj_destroy\n+ U mlx5dv_devx_umem_dereg\n+ U mlx5dv_devx_umem_reg\n+ U mlx5dv_init_obj\n+ U posix_memalign\n+ U pthread_spin_init\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_dr_devx_create_qp\n+ U rdmacore52_0_dr_devx_modify_qp_init2rtr\n+ U rdmacore52_0_dr_devx_modify_qp_rst2init\n+ U rdmacore52_0_dr_devx_modify_qp_rtr2rts\n+ U rdmacore52_0_dr_devx_query_gid\n+ U rdmacore52_0_dr_icm_pool_get_chunk_mr_addr\n+ U rdmacore52_0_dr_icm_pool_get_chunk_rkey\n+00000000000012a0 T rdmacore52_0_dr_send_allow_fl\n+0000000000000620 T rdmacore52_0_dr_send_fill_and_append_ste_send_info\n+0000000000000fc0 T rdmacore52_0_dr_send_postsend_action\n+00000000000011b0 T rdmacore52_0_dr_send_postsend_args\n+0000000000000ce0 T rdmacore52_0_dr_send_postsend_formated_htbl\n+0000000000000760 T rdmacore52_0_dr_send_postsend_htbl\n+00000000000010d0 T rdmacore52_0_dr_send_postsend_pattern\n+0000000000000690 T rdmacore52_0_dr_send_postsend_ste\n+00000000000013a0 T rdmacore52_0_dr_send_ring_alloc\n+0000000000001ce0 T rdmacore52_0_dr_send_ring_force_drain\n+00000000000012c0 T rdmacore52_0_dr_send_ring_free\n+ U rdmacore52_0_dr_ste_get_mr_addr\n+ U rdmacore52_0_dr_ste_prepare_for_postsend\n+ U sysconf\n+\n+dr_dbg.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n+0000000000000070 r .LC10\n+0000000000000058 r .LC11\n+000000000000008a r .LC12\n+00000000000000a2 r .LC13\n+00000000000000b5 r .LC14\n+00000000000000ba r .LC15\n+00000000000000ca r .LC16\n+00000000000000e5 r .LC17\n+00000000000000fa r .LC18\n+0000000000000080 r .LC19\n+0000000000000005 r .LC2\n+0000000000000110 r .LC20\n+0000000000000112 r .LC21\n+00000000000000a8 r .LC22\n+00000000000000d0 r .LC23\n+0000000000000100 r .LC24\n+000000000000011c r .LC25\n+0000000000000132 r .LC26\n+000000000000013c r .LC27\n+0000000000000140 r .LC28\n+0000000000000142 r .LC29\n+0000000000000030 r .LC3\n+0000000000000146 r .LC30\n+0000000000000149 r .LC31\n+0000000000000018 r .LC4\n+0000000000000021 r .LC5\n+0000000000000033 r .LC6\n+0000000000000051 r .LC7\n+000000000000005a r .LC8\n+0000000000000065 r .LC9\n+ U __fprintf_chk\n+ U __sprintf_chk\n+ U __stack_chk_fail\n+0000000000000000 t dr_dump_domain\n+0000000000001100 t dr_dump_matcher\n+0000000000000c40 t dr_dump_matcher_mask\n+0000000000000340 t dr_dump_matcher_rx_tx\n+00000000000005e0 t dr_dump_rule\n+0000000000000480 t dr_dump_rule_rx_tx.isra.0\n+0000000000000b40 t dr_dump_table\n+ U fputc\n+ U getpid\n+00000000000011c0 T mlx5dv_dump_dr_domain\n+00000000000015c0 T mlx5dv_dump_dr_matcher\n+0000000000001750 T mlx5dv_dump_dr_rule\n+00000000000013f0 T mlx5dv_dump_dr_table\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_dr_actions_reformat_get_id\n+ U rdmacore52_0_dr_arg_get_object_id\n+ U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n+ U rdmacore52_0_dr_rule_get_reverse_rule_members\n+ U rdmacore52_0_dr_ste_get_icm_addr\n+\n+dr_devx.c.o:\n+0000000000000000 r .LC0\n+0000000000000008 r .LC1\n+0000000000000040 r .LC10\n+0000000000000010 r .LC3\n+0000000000000018 r .LC5\n+0000000000000020 r .LC6\n+0000000000000028 r .LC7\n+0000000000000030 r .LC8\n+0000000000000038 r .LC9\n+ U __errno_location\n+ U __stack_chk_fail\n+ U calloc\n+ U free\n+ U memcpy\n+ U mlx5dv_devx_general_cmd\n+ U mlx5dv_devx_obj_create\n+ U mlx5dv_devx_obj_destroy\n+ U mlx5dv_devx_obj_modify\n+ U mlx5dv_devx_obj_query\n+0000000000000ca0 T rdmacore52_0_dr_devx_create_always_hit_ft\n+0000000000001400 T rdmacore52_0_dr_devx_create_definer\n+0000000000001230 T rdmacore52_0_dr_devx_create_flow_sampler\n+0000000000000a20 T rdmacore52_0_dr_devx_create_flow_table\n+00000000000015f0 T rdmacore52_0_dr_devx_create_meter\n+0000000000001e10 T rdmacore52_0_dr_devx_create_modify_header_arg\n+00000000000018d0 T rdmacore52_0_dr_devx_create_qp\n+00000000000014d0 T rdmacore52_0_dr_devx_create_reformat_ctx\n+0000000000001200 T rdmacore52_0_dr_devx_destroy_always_hit_ft\n+00000000000017e0 T rdmacore52_0_dr_devx_modify_meter\n+0000000000001b40 T rdmacore52_0_dr_devx_modify_qp_init2rtr\n+0000000000001a70 T rdmacore52_0_dr_devx_modify_qp_rst2init\n+0000000000001c70 T rdmacore52_0_dr_devx_modify_qp_rtr2rts\n+00000000000002c0 T rdmacore52_0_dr_devx_query_device\n+00000000000001a0 T rdmacore52_0_dr_devx_query_esw_caps\n+0000000000000000 T rdmacore52_0_dr_devx_query_esw_vport_context\n+0000000000001330 T rdmacore52_0_dr_devx_query_flow_sampler\n+0000000000000b50 T rdmacore52_0_dr_devx_query_flow_table\n+0000000000001d40 T rdmacore52_0_dr_devx_query_gid\n+00000000000000e0 T rdmacore52_0_dr_devx_query_gvmi\n+0000000000001710 T rdmacore52_0_dr_devx_query_meter\n+0000000000000990 T rdmacore52_0_dr_devx_sync_steering\n+ U rdmacore52_0_mlx5_get_cmd_status_err\n+\n+dr_icm_pool.c.o:\n+0000000000000000 r .LC0\n+0000000000000008 r .LC1\n+ U __errno_location\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t dr_icm_buddy_destroy\n+0000000000000160 t dr_icm_pool_sync_pool_buddies\n+ U free\n+ U ibv_dereg_mr\n+ U malloc\n+ U memset\n+ U mlx5dv_alloc_dm\n+ U pthread_spin_destroy\n+ U pthread_spin_init\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_dr_buddy_alloc_mem\n+ U rdmacore52_0_dr_buddy_cleanup\n+ U rdmacore52_0_dr_buddy_free_mem\n+ U rdmacore52_0_dr_buddy_init\n+ U rdmacore52_0_dr_devx_sync_steering\n+00000000000003f0 T rdmacore52_0_dr_icm_alloc_chunk\n+0000000000000a20 T rdmacore52_0_dr_icm_free_chunk\n+0000000000000b90 T rdmacore52_0_dr_icm_pool_create\n+0000000000000ce0 T rdmacore52_0_dr_icm_pool_destroy\n+0000000000000ae0 T rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n+0000000000000b30 T rdmacore52_0_dr_icm_pool_get_chunk_mr_addr\n+0000000000000b70 T rdmacore52_0_dr_icm_pool_get_chunk_rkey\n+0000000000000ab0 T rdmacore52_0_dr_icm_pool_set_pool_max_log_chunk_sz\n+00000000000003a0 T rdmacore52_0_dr_icm_pool_sync_pool\n+ U rdmacore52_0_dr_send_ring_force_drain\n+ U rdmacore52_0_mlx5_free_dm\n+\n+dr_matcher.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000320 t dr_matcher_connect\n+0000000000000000 t dr_matcher_copy_mask\n+0000000000002a80 t dr_matcher_init_nic\n+00000000000004a0 t dr_matcher_is_mask_consumed\n+00000000000001b0 t dr_matcher_set_nic_matcher_layout\n+0000000000000980 t dr_matcher_set_ste_builders\n+00000000000008e0 t dr_matcher_uninit_nic\n+ U free\n+ U memcpy\n+ U mlx5dv_create_flow_matcher\n+ U mlx5dv_destroy_flow_matcher\n+ U mlx5dv_devx_obj_destroy\n+0000000000002c20 T mlx5dv_dr_matcher_create\n+0000000000003380 T mlx5dv_dr_matcher_destroy\n+0000000000002b70 T mlx5dv_dr_matcher_set_layout\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_dr_devx_create_definer\n+ U rdmacore52_0_dr_domain_is_support_ste_icm_size\n+ U rdmacore52_0_dr_domain_set_max_ste_icm_size\n+ U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n+ U rdmacore52_0_dr_rule_rehash_matcher_s_anchor\n+ U rdmacore52_0_dr_send_ring_force_drain\n+ U rdmacore52_0_dr_ste_build_def0\n+ U rdmacore52_0_dr_ste_build_def16\n+ U rdmacore52_0_dr_ste_build_def2\n+ U rdmacore52_0_dr_ste_build_def22\n+ U rdmacore52_0_dr_ste_build_def24\n+ U rdmacore52_0_dr_ste_build_def25\n+ U rdmacore52_0_dr_ste_build_def26\n+ U rdmacore52_0_dr_ste_build_def28\n+ U rdmacore52_0_dr_ste_build_def33\n+ U rdmacore52_0_dr_ste_build_def6\n+ U rdmacore52_0_dr_ste_build_empty_always_hit\n+ U rdmacore52_0_dr_ste_build_eth_ipv6_l3_l4\n+ U rdmacore52_0_dr_ste_build_eth_l2_dst\n+ U rdmacore52_0_dr_ste_build_eth_l2_src\n+ U rdmacore52_0_dr_ste_build_eth_l2_src_dst\n+ U rdmacore52_0_dr_ste_build_eth_l2_tnl\n+ U rdmacore52_0_dr_ste_build_eth_l3_ipv4_5_tuple\n+ U rdmacore52_0_dr_ste_build_eth_l3_ipv4_misc\n+ U rdmacore52_0_dr_ste_build_eth_l3_ipv6_dst\n+ U rdmacore52_0_dr_ste_build_eth_l3_ipv6_src\n+ U rdmacore52_0_dr_ste_build_eth_l4_misc\n+ U rdmacore52_0_dr_ste_build_flex_parser_0\n+ U rdmacore52_0_dr_ste_build_flex_parser_1\n+ U rdmacore52_0_dr_ste_build_general_purpose\n+ U rdmacore52_0_dr_ste_build_ib_l4\n+ U rdmacore52_0_dr_ste_build_icmp\n+ U rdmacore52_0_dr_ste_build_mpls\n+ U rdmacore52_0_dr_ste_build_pre_check\n+ U rdmacore52_0_dr_ste_build_register_0\n+ U rdmacore52_0_dr_ste_build_register_1\n+ U rdmacore52_0_dr_ste_build_src_gvmi_qpn\n+ U rdmacore52_0_dr_ste_build_tnl_geneve\n+ U rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt\n+ U rdmacore52_0_dr_ste_build_tnl_geneve_tlv_opt_exist\n+ U rdmacore52_0_dr_ste_build_tnl_gre\n+ U rdmacore52_0_dr_ste_build_tnl_gtpu\n+ U rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_0\n+ U rdmacore52_0_dr_ste_build_tnl_gtpu_flex_parser_1\n+ U rdmacore52_0_dr_ste_build_tnl_mpls_over_gre\n+ U rdmacore52_0_dr_ste_build_tnl_mpls_over_udp\n+ U rdmacore52_0_dr_ste_build_tnl_vxlan_gpe\n+ U rdmacore52_0_dr_ste_build_tunnel_header\n+ U rdmacore52_0_dr_ste_copy_param\n U rdmacore52_0_dr_ste_htbl_alloc\n U rdmacore52_0_dr_ste_htbl_free\n- U rdmacore52_0_dr_ste_set_hit_addr_by_next_htbl\n-0000000000008d50 T rdmacore52_0_dr_ste_v1_set_aso_ct\n- U rdmacore52_0_dr_vports_table_get_vport_cap\n-0000000000000000 d ste_ctx_v1\n+ U rdmacore52_0_dr_ste_htbl_init_and_postsend\n \n-dr_ste_v0.c.o:\n+dr_table.c.o:\n U __errno_location\n U __stack_chk_fail\n-0000000000000000 r dr_ste_v0_action_modify_field_arr\n-0000000000001e80 t dr_ste_v0_build_eth_ipv6_l3_l4_init\n-00000000000008f0 t dr_ste_v0_build_eth_ipv6_l3_l4_tag\n-0000000000003c40 t dr_ste_v0_build_eth_l2_dst_init\n-0000000000001140 t dr_ste_v0_build_eth_l2_dst_tag\n-0000000000002350 t dr_ste_v0_build_eth_l2_src_dst_init\n-0000000000001510 t dr_ste_v0_build_eth_l2_src_dst_tag\n-0000000000002040 t dr_ste_v0_build_eth_l2_src_init\n-0000000000000df0 t dr_ste_v0_build_eth_l2_src_or_dst_tag\n-00000000000011a0 t dr_ste_v0_build_eth_l2_src_tag\n-0000000000001ed0 t dr_ste_v0_build_eth_l2_tnl_init\n-0000000000000c20 t dr_ste_v0_build_eth_l2_tnl_tag\n-0000000000003f50 t dr_ste_v0_build_eth_l3_ipv4_5_tuple_init\n-00000000000011f0 t dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag\n-00000000000028d0 t dr_ste_v0_build_eth_l3_ipv4_misc_init\n-0000000000000bc0 t dr_ste_v0_build_eth_l3_ipv4_misc_tag\n-00000000000029b0 t dr_ste_v0_build_eth_l3_ipv6_dst_init\n-0000000000001450 t dr_ste_v0_build_eth_l3_ipv6_dst_tag\n-0000000000002a50 t dr_ste_v0_build_eth_l3_ipv6_src_init\n-00000000000014b0 t dr_ste_v0_build_eth_l3_ipv6_src_tag\n-00000000000026d0 t dr_ste_v0_build_eth_l4_misc_init\n-0000000000002650 t dr_ste_v0_build_eth_l4_misc_tag\n-0000000000003430 t dr_ste_v0_build_flex_parser_0_init\n-00000000000033e0 t dr_ste_v0_build_flex_parser_1_init\n-0000000000003090 t dr_ste_v0_build_flex_parser_tag\n-0000000000002af0 t dr_ste_v0_build_flex_parser_tnl_geneve_init\n-00000000000005c0 t dr_ste_v0_build_flex_parser_tnl_geneve_tag\n-0000000000001cb0 t dr_ste_v0_build_flex_parser_tnl_geneve_tlv_opt_init\n-00000000000018d0 t dr_ste_v0_build_flex_parser_tnl_geneve_tlv_opt_tag\n-0000000000002780 t dr_ste_v0_build_flex_parser_tnl_gtpu_init\n-0000000000000550 t dr_ste_v0_build_flex_parser_tnl_gtpu_tag\n-0000000000002820 t dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init\n-00000000000025d0 t dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag\n-0000000000001d10 t dr_ste_v0_build_general_purpose_init\n-0000000000000650 t dr_ste_v0_build_general_purpose_tag\n-0000000000002bb0 t dr_ste_v0_build_icmp_init\n-0000000000001910 t dr_ste_v0_build_icmp_tag\n-0000000000003480 t dr_ste_v0_build_mpls_init\n-0000000000000750 t dr_ste_v0_build_mpls_tag\n-0000000000001c20 t dr_ste_v0_build_register_0_init\n-00000000000004e0 t dr_ste_v0_build_register_0_tag\n-0000000000001b90 t dr_ste_v0_build_register_1_init\n-0000000000000470 t dr_ste_v0_build_register_1_tag\n-0000000000001b20 t dr_ste_v0_build_src_gvmi_qpn_init\n-00000000000024d0 t dr_ste_v0_build_src_gvmi_qpn_tag\n-0000000000002f90 t dr_ste_v0_build_tnl_gre_init\n-0000000000000670 t dr_ste_v0_build_tnl_gre_tag\n-0000000000002d40 t dr_ste_v0_build_tnl_gtpu_flex_parser_0_init\n-00000000000017d0 t dr_ste_v0_build_tnl_gtpu_flex_parser_0_tag\n-0000000000002e70 t dr_ste_v0_build_tnl_gtpu_flex_parser_1_init\n-00000000000016e0 t dr_ste_v0_build_tnl_gtpu_flex_parser_1_tag\n-0000000000001df0 t dr_ste_v0_build_tnl_mpls_over_gre_init\n-0000000000001a50 t dr_ste_v0_build_tnl_mpls_over_gre_tag\n-0000000000001d60 t dr_ste_v0_build_tnl_mpls_over_udp_init\n-00000000000019e0 t dr_ste_v0_build_tnl_mpls_over_udp_tag\n-0000000000001ac0 t dr_ste_v0_build_tunnel_header_0_1_init\n-0000000000000430 t dr_ste_v0_build_tunnel_header_0_1_tag\n-0000000000002580 t dr_ste_v0_get_action_hw_field\n-0000000000000010 t dr_ste_v0_get_byte_mask\n-0000000000000020 t dr_ste_v0_get_miss_addr\n-0000000000000000 t dr_ste_v0_get_next_lu_type\n-0000000000002ce0 t dr_ste_v0_init\n-0000000000000240 t dr_ste_v0_set_action_add\n-00000000000001e0 t dr_ste_v0_set_action_copy\n-0000000000000040 t dr_ste_v0_set_action_decap_l3_list\n-0000000000000280 t dr_ste_v0_set_action_set\n-00000000000039b0 t dr_ste_v0_set_actions_rx\n-0000000000003650 t dr_ste_v0_set_actions_tx\n-00000000000002e0 t dr_ste_v0_set_byte_mask\n-00000000000003e0 t dr_ste_v0_set_ctrl_always_hit_htbl\n-00000000000003a0 t dr_ste_v0_set_ctrl_always_miss\n-0000000000000300 t dr_ste_v0_set_hit_addr\n-00000000000002c0 t dr_ste_v0_set_hit_gvmi\n-0000000000000340 t dr_ste_v0_set_miss_addr\n-0000000000000380 t dr_ste_v0_set_next_lu_type\n- U rdmacore52_0_dr_ste_conv_bit_to_byte_mask\n-00000000000041e0 T rdmacore52_0_dr_ste_get_ctx_v0\n- U rdmacore52_0_dr_vports_table_get_vport_cap\n-0000000000000000 d ste_ctx_v0\n+ U calloc\n+0000000000000000 t dr_table_init_nic\n+00000000000000b0 t dr_table_uninit\n+ U free\n+ U mlx5dv_devx_obj_destroy\n+0000000000000100 T mlx5dv_dr_table_create\n+0000000000000440 T mlx5dv_dr_table_destroy\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_dr_devx_create_flow_table\n+ U rdmacore52_0_dr_icm_pool_get_chunk_icm_addr\n+ U rdmacore52_0_dr_send_ring_force_drain\n+ U rdmacore52_0_dr_ste_htbl_alloc\n+ U rdmacore52_0_dr_ste_htbl_free\n+ U rdmacore52_0_dr_ste_htbl_init_and_postsend\n+\n+buf.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n+000000000000006b r .LC10\n+0000000000000084 r .LC11\n+0000000000000015 r .LC2\n+0000000000000023 r .LC3\n+0000000000000028 r .LC4\n+000000000000002d r .LC5\n+0000000000000034 r .LC6\n+0000000000000042 r .LC7\n+000000000000004e r .LC8\n+0000000000000052 r .LC9\n+ U __errno_location\n+ U __snprintf_chk\n+ U __sprintf_chk\n+ U __stack_chk_fail\n+ U __vfprintf_chk\n+ U abort\n+ U calloc\n+ U free\n+ U fwrite\n+ U getenv\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U malloc\n+0000000000000000 t mlx5_err\n+ U mmap\n+ U munmap\n+ U posix_memalign\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_bitmap_fill_region\n+ U rdmacore52_0_bitmap_find_free_region\n+ U rdmacore52_0_bitmap_zero_region\n+0000000000000f50 T rdmacore52_0_mlx5_alloc_buf\n+00000000000005f0 T rdmacore52_0_mlx5_alloc_buf_contig\n+0000000000000100 T rdmacore52_0_mlx5_alloc_buf_extern\n+0000000000000840 T rdmacore52_0_mlx5_alloc_prefered_buf\n+0000000000000180 T rdmacore52_0_mlx5_free_actual_buf\n+0000000000000fd0 T rdmacore52_0_mlx5_free_buf\n+0000000000000f20 T rdmacore52_0_mlx5_free_buf_contig\n+00000000000000c0 T rdmacore52_0_mlx5_free_buf_extern\n+0000000000000450 T rdmacore52_0_mlx5_get_alloc_type\n+0000000000000400 T rdmacore52_0_mlx5_is_custom_alloc\n+0000000000000430 T rdmacore52_0_mlx5_is_extern_alloc\n+ U shmat\n+ U shmctl\n+ U shmdt\n+ U shmget\n+ U stderr\n+ U strcasecmp\n+ U strerror\n+ U strtol\n+\n+dr_crc32.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 b dr_ste_crc_tab32\n+0000000000000000 T rdmacore52_0_dr_crc32_init_table\n+0000000000000380 T rdmacore52_0_dr_crc32_slice8_calc\n \n dr_ptrn.c.o:\n U __errno_location\n U calloc\n U free\n U ibv_get_device_name\n U memcpy\n@@ -2242,120 +2355,7 @@\n U rdmacore52_0_dr_icm_pool_sync_pool\n 0000000000000010 T rdmacore52_0_dr_ptrn_cache_get_pattern\n 0000000000000370 T rdmacore52_0_dr_ptrn_cache_put_pattern\n 00000000000003d0 T rdmacore52_0_dr_ptrn_mngr_create\n 0000000000000470 T rdmacore52_0_dr_ptrn_mngr_destroy\n 0000000000000000 T rdmacore52_0_dr_ptrn_sync_pool\n U rdmacore52_0_dr_send_postsend_pattern\n-\n-cq.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n-0000000000000058 r .LC10\n-0000000000000000 r .LC2\n-0000000000000090 r .LC3\n-0000000000000015 r .LC4\n-0000000000000032 r .LC7\n-00000000000000b8 r .LC8\n-0000000000000050 r .LC9\n-0000000000000980 r CSWTCH.104\n-00000000000007a0 t __mlx5_cq_clean.part.0\n- U __stack_chk_fail\n- U __vfprintf_chk\n- U abort\n-0000000000000560 t dump_cqe\n- U fwrite\n-0000000000000b40 t handle_tag_matching\n- U memcpy\n- U memset\n-0000000000000b20 t mlx5_cq_read_flow_tag\n-00000000000002a0 t mlx5_cq_read_wc_byte_len\n-0000000000000180 t mlx5_cq_read_wc_completion_ts\n-00000000000001a0 t mlx5_cq_read_wc_completion_wallclock_ns\n-00000000000005c0 t mlx5_cq_read_wc_cvlan\n-0000000000000030 t mlx5_cq_read_wc_dlid_path_bits\n-00000000000002c0 t mlx5_cq_read_wc_flags\n-0000000000000280 t mlx5_cq_read_wc_imm_data\n-0000000000000050 t mlx5_cq_read_wc_opcode\n-0000000000000260 t mlx5_cq_read_wc_qp_num\n-0000000000000010 t mlx5_cq_read_wc_sl\n-00000000000005e0 t mlx5_cq_read_wc_slid\n-0000000000000240 t mlx5_cq_read_wc_src_qp\n-0000000000000220 t mlx5_cq_read_wc_tm_info\n-0000000000000000 t mlx5_cq_read_wc_vendor_err\n-0000000000000480 t mlx5_end_poll\n-0000000000000380 t mlx5_end_poll_adaptive_stall\n-0000000000000600 t mlx5_end_poll_adaptive_stall_lock\n-0000000000000760 t mlx5_end_poll_lock\n-0000000000000440 t mlx5_end_poll_stall\n-00000000000006f0 t mlx5_end_poll_stall_lock\n-00000000000004a0 t mlx5_err\n-0000000000003f90 t mlx5_next_poll_adaptive_v0\n-0000000000005570 t mlx5_next_poll_adaptive_v1\n-00000000000034d0 t mlx5_next_poll_v0\n-0000000000004a60 t mlx5_next_poll_v1\n-0000000000009880 t mlx5_start_poll_adaptive_stall_v0\n-000000000000bad0 t mlx5_start_poll_adaptive_stall_v0_clock_update\n-0000000000010e20 t mlx5_start_poll_adaptive_stall_v0_lock\n-00000000000132c0 t mlx5_start_poll_adaptive_stall_v0_lock_clock_update\n-0000000000011ae0 t mlx5_start_poll_adaptive_stall_v1\n-0000000000013f90 t mlx5_start_poll_adaptive_stall_v1_clock_update\n-00000000000028a0 t mlx5_start_poll_adaptive_stall_v1_lock\n-0000000000000ef0 t mlx5_start_poll_adaptive_stall_v1_lock_clock_update\n-0000000000007650 t mlx5_start_poll_stall_v0\n-0000000000008180 t mlx5_start_poll_stall_v0_clock_update\n-000000000000d1c0 t mlx5_start_poll_stall_v0_lock\n-000000000000e9f0 t mlx5_start_poll_stall_v0_lock_clock_update\n-000000000000de40 t mlx5_start_poll_stall_v1\n-000000000000f680 t mlx5_start_poll_stall_v1_clock_update\n-0000000000014bc0 t mlx5_start_poll_stall_v1_lock\n-0000000000001bf0 t mlx5_start_poll_stall_v1_lock_clock_update\n-0000000000006070 t mlx5_start_poll_v0\n-0000000000006b60 t mlx5_start_poll_v0_clock_update\n-0000000000008cd0 t mlx5_start_poll_v0_lock\n-000000000000af10 t mlx5_start_poll_v0_lock_clock_update\n-000000000000a3f0 t mlx5_start_poll_v1\n-000000000000c670 t mlx5_start_poll_v1_clock_update\n-0000000000010250 t mlx5_start_poll_v1_lock\n-00000000000126c0 t mlx5_start_poll_v1_lock_clock_update\n- U mlx5dv_get_clock_info\n-0000000000000000 d ops\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U pthread_spin_lock\n- U pthread_spin_unlock\n-00000000000178e0 T rdmacore52_0___mlx5_cq_clean\n-0000000000017cf0 T rdmacore52_0_mlx5_alloc_cq_buf\n- U rdmacore52_0_mlx5_alloc_prefered_buf\n-0000000000017860 T rdmacore52_0_mlx5_arm_cq\n- U rdmacore52_0_mlx5_complete_odp_fault\n- U rdmacore52_0_mlx5_copy_to_recv_srq\n- U rdmacore52_0_mlx5_copy_to_recv_wqe\n- U rdmacore52_0_mlx5_copy_to_send_wqe\n-0000000000017910 T rdmacore52_0_mlx5_cq_clean\n-00000000000178d0 T rdmacore52_0_mlx5_cq_event\n-0000000000017660 T rdmacore52_0_mlx5_cq_fill_pfns\n-00000000000179d0 T rdmacore52_0_mlx5_cq_resize_copy_cqes\n- U rdmacore52_0_mlx5_find_mkey\n- U rdmacore52_0_mlx5_find_qp\n- U rdmacore52_0_mlx5_find_srq\n- U rdmacore52_0_mlx5_free_actual_buf\n-0000000000017e50 T rdmacore52_0_mlx5_free_cq_buf\n- U rdmacore52_0_mlx5_free_srq_wqe\n- U rdmacore52_0_mlx5_freeze_on_error_cqe\n- U rdmacore52_0_mlx5_get_alloc_type\n-0000000000015810 T rdmacore52_0_mlx5_poll_cq\n-0000000000016690 T rdmacore52_0_mlx5_poll_cq_v1\n-0000000000000000 D rdmacore52_0_mlx5_stall_cq_dec_step\n-0000000000000004 D rdmacore52_0_mlx5_stall_cq_inc_step\n-0000000000000008 D rdmacore52_0_mlx5_stall_cq_poll_max\n-000000000000000c D rdmacore52_0_mlx5_stall_cq_poll_min\n-0000000000000010 D rdmacore52_0_mlx5_stall_num_loop\n- U rdmacore52_0_mlx5_use_huge\n- U sleep\n- U stderr\n-\n-dr_crc32.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 b dr_ste_crc_tab32\n-0000000000000000 T rdmacore52_0_dr_crc32_init_table\n-0000000000000380 T rdmacore52_0_dr_crc32_slice8_calc\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,27 +1,27 @@\n ---------- 0 0 0 15454 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 15752 1970-01-01 00:00:00.000000 dr_devx.c.o\n-?rw-r--r-- 0 0 0 15752 1970-01-01 00:00:00.000000 dr_dbg.c.o\n-?rw-r--r-- 0 0 0 4728 1970-01-01 00:00:00.000000 dr_arg.c.o\n-?rw-r--r-- 0 0 0 3888 1970-01-01 00:00:00.000000 dbrec.c.o\n-?rw-r--r-- 0 0 0 19264 1970-01-01 00:00:00.000000 dr_rule.c.o\n-?rw-r--r-- 0 0 0 3320 1970-01-01 00:00:00.000000 dr_ste_v2.c.o\n-?rw-r--r-- 0 0 0 11424 1970-01-01 00:00:00.000000 buf.c.o\n-?rw-r--r-- 0 0 0 84992 1970-01-01 00:00:00.000000 mlx5_vfio.c.o\n-?rw-r--r-- 0 0 0 26976 1970-01-01 00:00:00.000000 dr_ste.c.o\n-?rw-r--r-- 0 0 0 4280 1970-01-01 00:00:00.000000 dr_vports.c.o\n+?rw-r--r-- 0 0 0 30456 1970-01-01 00:00:00.000000 dr_ste_v0.c.o\n+?rw-r--r-- 0 0 0 152640 1970-01-01 00:00:00.000000 cq.c.o\n ?rw-r--r-- 0 0 0 33672 1970-01-01 00:00:00.000000 dr_action.c.o\n-?rw-r--r-- 0 0 0 10592 1970-01-01 00:00:00.000000 dr_domain.c.o\n+?rw-r--r-- 0 0 0 56032 1970-01-01 00:00:00.000000 dr_ste_v1.c.o\n ?rw-r--r-- 0 0 0 3672 1970-01-01 00:00:00.000000 dr_buddy.c.o\n+?rw-r--r-- 0 0 0 84992 1970-01-01 00:00:00.000000 mlx5_vfio.c.o\n ?rw-r--r-- 0 0 0 48824 1970-01-01 00:00:00.000000 mlx5.c.o\n-?rw-r--r-- 0 0 0 22784 1970-01-01 00:00:00.000000 dr_matcher.c.o\n-?rw-r--r-- 0 0 0 8600 1970-01-01 00:00:00.000000 dr_icm_pool.c.o\n+?rw-r--r-- 0 0 0 19264 1970-01-01 00:00:00.000000 dr_rule.c.o\n+?rw-r--r-- 0 0 0 3888 1970-01-01 00:00:00.000000 dbrec.c.o\n+?rw-r--r-- 0 0 0 4728 1970-01-01 00:00:00.000000 dr_arg.c.o\n+?rw-r--r-- 0 0 0 3320 1970-01-01 00:00:00.000000 dr_ste_v2.c.o\n ?rw-r--r-- 0 0 0 64528 1970-01-01 00:00:00.000000 qp.c.o\n-?rw-r--r-- 0 0 0 15488 1970-01-01 00:00:00.000000 dr_send.c.o\n+?rw-r--r-- 0 0 0 4280 1970-01-01 00:00:00.000000 dr_vports.c.o\n+?rw-r--r-- 0 0 0 26976 1970-01-01 00:00:00.000000 dr_ste.c.o\n ?rw-r--r-- 0 0 0 7456 1970-01-01 00:00:00.000000 srq.c.o\n-?rw-r--r-- 0 0 0 4288 1970-01-01 00:00:00.000000 dr_table.c.o\n+?rw-r--r-- 0 0 0 10592 1970-01-01 00:00:00.000000 dr_domain.c.o\n ?rw-r--r-- 0 0 0 119424 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 56032 1970-01-01 00:00:00.000000 dr_ste_v1.c.o\n-?rw-r--r-- 0 0 0 30456 1970-01-01 00:00:00.000000 dr_ste_v0.c.o\n-?rw-r--r-- 0 0 0 4536 1970-01-01 00:00:00.000000 dr_ptrn.c.o\n-?rw-r--r-- 0 0 0 152640 1970-01-01 00:00:00.000000 cq.c.o\n+?rw-r--r-- 0 0 0 15488 1970-01-01 00:00:00.000000 dr_send.c.o\n+?rw-r--r-- 0 0 0 15752 1970-01-01 00:00:00.000000 dr_dbg.c.o\n+?rw-r--r-- 0 0 0 15752 1970-01-01 00:00:00.000000 dr_devx.c.o\n+?rw-r--r-- 0 0 0 8600 1970-01-01 00:00:00.000000 dr_icm_pool.c.o\n+?rw-r--r-- 0 0 0 22784 1970-01-01 00:00:00.000000 dr_matcher.c.o\n+?rw-r--r-- 0 0 0 4288 1970-01-01 00:00:00.000000 dr_table.c.o\n+?rw-r--r-- 0 0 0 11424 1970-01-01 00:00:00.000000 buf.c.o\n ?rw-r--r-- 0 0 0 2832 1970-01-01 00:00:00.000000 dr_crc32.c.o\n+?rw-r--r-- 0 0 0 4536 1970-01-01 00:00:00.000000 dr_ptrn.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libmthca-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libmthca-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,33 +1,39 @@\n \n Archive index:\n+rdmacore52_0_mthca_poll_cq in cq.c.o\n+rdmacore52_0_mthca_tavor_arm_cq in cq.c.o\n+rdmacore52_0_mthca_arbel_arm_cq in cq.c.o\n+rdmacore52_0_mthca_arbel_cq_event in cq.c.o\n+rdmacore52_0___mthca_cq_clean in cq.c.o\n+rdmacore52_0_mthca_cq_clean in cq.c.o\n+rdmacore52_0_mthca_cq_resize_copy_cqes in cq.c.o\n+rdmacore52_0_mthca_alloc_cq_buf in cq.c.o\n+rdmacore52_0_mthca_alloc_db in memfree.c.o\n+rdmacore52_0_mthca_set_db_qn in memfree.c.o\n+rdmacore52_0_mthca_free_db in memfree.c.o\n+rdmacore52_0_mthca_alloc_db_tab in memfree.c.o\n+rdmacore52_0_mthca_free_db_tab in memfree.c.o\n rdmacore52_0_mthca_alloc_av in ah.c.o\n rdmacore52_0_mthca_free_av in ah.c.o\n-verbs_provider_mthca in mthca.c.o\n-rdmacore52_0_mthca_alloc_buf in buf.c.o\n-rdmacore52_0_mthca_free_buf in buf.c.o\n rdmacore52_0_mthca_init_qp_indices in qp.c.o\n rdmacore52_0_mthca_tavor_post_send in qp.c.o\n rdmacore52_0_mthca_tavor_post_recv in qp.c.o\n rdmacore52_0_mthca_arbel_post_send in qp.c.o\n rdmacore52_0_mthca_arbel_post_recv in qp.c.o\n rdmacore52_0_mthca_alloc_qp_buf in qp.c.o\n rdmacore52_0_mthca_find_qp in qp.c.o\n rdmacore52_0_mthca_store_qp in qp.c.o\n rdmacore52_0_mthca_clear_qp in qp.c.o\n rdmacore52_0_mthca_free_err_wqe in qp.c.o\n-rdmacore52_0_mthca_alloc_db in memfree.c.o\n-rdmacore52_0_mthca_set_db_qn in memfree.c.o\n-rdmacore52_0_mthca_free_db in memfree.c.o\n-rdmacore52_0_mthca_alloc_db_tab in memfree.c.o\n-rdmacore52_0_mthca_free_db_tab in memfree.c.o\n rdmacore52_0_mthca_free_srq_wqe in srq.c.o\n rdmacore52_0_mthca_tavor_post_srq_recv in srq.c.o\n rdmacore52_0_mthca_arbel_post_srq_recv in srq.c.o\n rdmacore52_0_mthca_alloc_srq_buf in srq.c.o\n+verbs_provider_mthca in mthca.c.o\n rdmacore52_0_mthca_query_device in verbs.c.o\n rdmacore52_0_mthca_query_port in verbs.c.o\n rdmacore52_0_mthca_alloc_pd in verbs.c.o\n rdmacore52_0_mthca_free_pd in verbs.c.o\n rdmacore52_0_mthca_reg_mr in verbs.c.o\n rdmacore52_0_mthca_dereg_mr in verbs.c.o\n rdmacore52_0_mthca_create_cq in verbs.c.o\n@@ -39,36 +45,100 @@\n rdmacore52_0_mthca_destroy_srq in verbs.c.o\n rdmacore52_0_mthca_create_qp in verbs.c.o\n rdmacore52_0_mthca_query_qp in verbs.c.o\n rdmacore52_0_mthca_modify_qp in verbs.c.o\n rdmacore52_0_mthca_destroy_qp in verbs.c.o\n rdmacore52_0_mthca_create_ah in verbs.c.o\n rdmacore52_0_mthca_destroy_ah in verbs.c.o\n-rdmacore52_0_mthca_poll_cq in cq.c.o\n-rdmacore52_0_mthca_tavor_arm_cq in cq.c.o\n-rdmacore52_0_mthca_arbel_arm_cq in cq.c.o\n-rdmacore52_0_mthca_arbel_cq_event in cq.c.o\n-rdmacore52_0___mthca_cq_clean in cq.c.o\n-rdmacore52_0_mthca_cq_clean in cq.c.o\n-rdmacore52_0_mthca_cq_resize_copy_cqes in cq.c.o\n-rdmacore52_0_mthca_alloc_cq_buf in cq.c.o\n+rdmacore52_0_mthca_alloc_buf in buf.c.o\n+rdmacore52_0_mthca_free_buf in buf.c.o\n+\n+cq.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC1\n+ U __printf_chk\n+ U __stack_chk_fail\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+0000000000000890 T rdmacore52_0___mthca_cq_clean\n+ U rdmacore52_0_mthca_alloc_buf\n+0000000000000c50 T rdmacore52_0_mthca_alloc_cq_buf\n+00000000000007f0 T rdmacore52_0_mthca_arbel_arm_cq\n+0000000000000880 T rdmacore52_0_mthca_arbel_cq_event\n+0000000000000b60 T rdmacore52_0_mthca_cq_clean\n+0000000000000bb0 T rdmacore52_0_mthca_cq_resize_copy_cqes\n+ U rdmacore52_0_mthca_find_qp\n+ U rdmacore52_0_mthca_free_err_wqe\n+ U rdmacore52_0_mthca_free_srq_wqe\n+0000000000000000 T rdmacore52_0_mthca_poll_cq\n+00000000000007b0 T rdmacore52_0_mthca_tavor_arm_cq\n+\n+memfree.c.o:\n+ U free\n+ U malloc\n+ U pthread_mutex_init\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdmacore52_0_mthca_alloc_buf\n+0000000000000000 T rdmacore52_0_mthca_alloc_db\n+0000000000000460 T rdmacore52_0_mthca_alloc_db_tab\n+ U rdmacore52_0_mthca_free_buf\n+00000000000003c0 T rdmacore52_0_mthca_free_db\n+00000000000004e0 T rdmacore52_0_mthca_free_db_tab\n+00000000000003a0 T rdmacore52_0_mthca_set_db_qn\n \n ah.c.o:\n U free\n U malloc\n U memset\n U pthread_mutex_lock\n U pthread_mutex_unlock\n 0000000000000000 T rdmacore52_0_mthca_alloc_av\n U rdmacore52_0_mthca_alloc_buf\n U rdmacore52_0_mthca_dereg_mr\n 0000000000000360 T rdmacore52_0_mthca_free_av\n U rdmacore52_0_mthca_free_buf\n U rdmacore52_0_mthca_reg_mr\n \n+qp.c.o:\n+0000000000000000 r .LC0\n+0000000000000008 r .LC1\n+ U calloc\n+ U free\n+ U malloc\n+ U memcpy\n+ U memset\n+0000000000000000 r mthca_opcode\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_mthca_alloc_buf\n+00000000000010f0 T rdmacore52_0_mthca_alloc_qp_buf\n+0000000000000f00 T rdmacore52_0_mthca_arbel_post_recv\n+0000000000000900 T rdmacore52_0_mthca_arbel_post_send\n+00000000000015a0 T rdmacore52_0_mthca_clear_qp\n+00000000000014c0 T rdmacore52_0_mthca_find_qp\n+0000000000001600 T rdmacore52_0_mthca_free_err_wqe\n+0000000000000000 T rdmacore52_0_mthca_init_qp_indices\n+0000000000001510 T rdmacore52_0_mthca_store_qp\n+0000000000000630 T rdmacore52_0_mthca_tavor_post_recv\n+0000000000000090 T rdmacore52_0_mthca_tavor_post_send\n+\n+srq.c.o:\n+0000000000000000 r .LC0\n+ U free\n+ U malloc\n+ U memset\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_mthca_alloc_buf\n+0000000000000450 T rdmacore52_0_mthca_alloc_srq_buf\n+00000000000002b0 T rdmacore52_0_mthca_arbel_post_srq_recv\n+0000000000000000 T rdmacore52_0_mthca_free_srq_wqe\n+0000000000000070 T rdmacore52_0_mthca_tavor_post_srq_recv\n+\n mthca.c.o:\n U __stack_chk_fail\n U calloc\n 0000000000000000 t drv__register_driver\n U free\n 0000000000000000 r hca_table\n U mmap\n@@ -120,73 +190,14 @@\n U rdmacore52_0_mthca_tavor_post_srq_recv\n U rdmacore52_0_verbs_register_driver_34\n U rdmacore52_0_verbs_set_ops\n U rdmacore52_0_verbs_uninit_context\n U sysconf\n 0000000000000000 D verbs_provider_mthca\n \n-buf.c.o:\n- U __errno_location\n- U ibv_dofork_range\n- U ibv_dontfork_range\n- U mmap\n- U munmap\n-0000000000000000 T rdmacore52_0_mthca_alloc_buf\n-0000000000000090 T rdmacore52_0_mthca_free_buf\n-\n-qp.c.o:\n-0000000000000000 r .LC0\n-0000000000000008 r .LC1\n- U calloc\n- U free\n- U malloc\n- U memcpy\n- U memset\n-0000000000000000 r mthca_opcode\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_mthca_alloc_buf\n-00000000000010f0 T rdmacore52_0_mthca_alloc_qp_buf\n-0000000000000f00 T rdmacore52_0_mthca_arbel_post_recv\n-0000000000000900 T rdmacore52_0_mthca_arbel_post_send\n-00000000000015a0 T rdmacore52_0_mthca_clear_qp\n-00000000000014c0 T rdmacore52_0_mthca_find_qp\n-0000000000001600 T rdmacore52_0_mthca_free_err_wqe\n-0000000000000000 T rdmacore52_0_mthca_init_qp_indices\n-0000000000001510 T rdmacore52_0_mthca_store_qp\n-0000000000000630 T rdmacore52_0_mthca_tavor_post_recv\n-0000000000000090 T rdmacore52_0_mthca_tavor_post_send\n-\n-memfree.c.o:\n- U free\n- U malloc\n- U pthread_mutex_init\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdmacore52_0_mthca_alloc_buf\n-0000000000000000 T rdmacore52_0_mthca_alloc_db\n-0000000000000460 T rdmacore52_0_mthca_alloc_db_tab\n- U rdmacore52_0_mthca_free_buf\n-00000000000003c0 T rdmacore52_0_mthca_free_db\n-00000000000004e0 T rdmacore52_0_mthca_free_db_tab\n-00000000000003a0 T rdmacore52_0_mthca_set_db_qn\n-\n-srq.c.o:\n-0000000000000000 r .LC0\n- U free\n- U malloc\n- U memset\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_mthca_alloc_buf\n-0000000000000450 T rdmacore52_0_mthca_alloc_srq_buf\n-00000000000002b0 T rdmacore52_0_mthca_arbel_post_srq_recv\n-0000000000000000 T rdmacore52_0_mthca_free_srq_wqe\n-0000000000000070 T rdmacore52_0_mthca_tavor_post_srq_recv\n-\n verbs.c.o:\n 0000000000000000 r .LC0\n U __snprintf_chk\n U __stack_chk_fail\n U free\n U malloc\n U pthread_mutex_init\n@@ -243,26 +254,15 @@\n 0000000000001210 T rdmacore52_0_mthca_query_qp\n 0000000000000c60 T rdmacore52_0_mthca_query_srq\n 00000000000001e0 T rdmacore52_0_mthca_reg_mr\n 0000000000000660 T rdmacore52_0_mthca_resize_cq\n U rdmacore52_0_mthca_set_db_qn\n U rdmacore52_0_mthca_store_qp\n \n-cq.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC1\n- U __printf_chk\n- U __stack_chk_fail\n- U pthread_spin_lock\n- U pthread_spin_unlock\n-0000000000000890 T rdmacore52_0___mthca_cq_clean\n- U rdmacore52_0_mthca_alloc_buf\n-0000000000000c50 T rdmacore52_0_mthca_alloc_cq_buf\n-00000000000007f0 T rdmacore52_0_mthca_arbel_arm_cq\n-0000000000000880 T rdmacore52_0_mthca_arbel_cq_event\n-0000000000000b60 T rdmacore52_0_mthca_cq_clean\n-0000000000000bb0 T rdmacore52_0_mthca_cq_resize_copy_cqes\n- U rdmacore52_0_mthca_find_qp\n- U rdmacore52_0_mthca_free_err_wqe\n- U rdmacore52_0_mthca_free_srq_wqe\n-0000000000000000 T rdmacore52_0_mthca_poll_cq\n-00000000000007b0 T rdmacore52_0_mthca_tavor_arm_cq\n+buf.c.o:\n+ U __errno_location\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U mmap\n+ U munmap\n+0000000000000000 T rdmacore52_0_mthca_alloc_buf\n+0000000000000090 T rdmacore52_0_mthca_free_buf\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,9 +1,9 @@\n ---------- 0 0 0 1762 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 8152 1970-01-01 00:00:00.000000 cq.c.o\n+?rw-r--r-- 0 0 0 3600 1970-01-01 00:00:00.000000 memfree.c.o\n ?rw-r--r-- 0 0 0 3200 1970-01-01 00:00:00.000000 ah.c.o\n-?rw-r--r-- 0 0 0 9600 1970-01-01 00:00:00.000000 mthca.c.o\n-?rw-r--r-- 0 0 0 1808 1970-01-01 00:00:00.000000 buf.c.o\n ?rw-r--r-- 0 0 0 9408 1970-01-01 00:00:00.000000 qp.c.o\n-?rw-r--r-- 0 0 0 3600 1970-01-01 00:00:00.000000 memfree.c.o\n ?rw-r--r-- 0 0 0 3872 1970-01-01 00:00:00.000000 srq.c.o\n+?rw-r--r-- 0 0 0 9600 1970-01-01 00:00:00.000000 mthca.c.o\n ?rw-r--r-- 0 0 0 15016 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 8152 1970-01-01 00:00:00.000000 cq.c.o\n+?rw-r--r-- 0 0 0 1808 1970-01-01 00:00:00.000000 buf.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libocrdma-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libocrdma-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,9 +1,10 @@\n \n Archive index:\n+verbs_provider_ocrdma in ocrdma_main.c.o\n rdmacore52_0_ocrdma_query_device in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_query_port in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_init_ahid_tbl in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_alloc_pd in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_free_pd in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_reg_mr in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_dereg_mr in ocrdma_verbs.c.o\n@@ -23,15 +24,67 @@\n rdmacore52_0_ocrdma_poll_cq in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_arm_cq in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_post_srq_recv in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_create_ah in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_destroy_ah in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_attach_mcast in ocrdma_verbs.c.o\n rdmacore52_0_ocrdma_detach_mcast in ocrdma_verbs.c.o\n-verbs_provider_ocrdma in ocrdma_main.c.o\n+\n+ocrdma_main.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r __func__.0\n+ U __printf_chk\n+ U __stack_chk_fail\n+ U calloc\n+0000000000000000 t drv__register_driver\n+ U free\n+ U mmap\n+ U munmap\n+00000000000000c0 t ocrdma_alloc_context\n+0000000000000000 d ocrdma_ctx_ops\n+0000000000000000 d ocrdma_dev_ops\n+0000000000000010 t ocrdma_device_alloc\n+0000000000000080 t ocrdma_free_context\n+0000000000000000 t ocrdma_uninit_device\n+ U pthread_mutex_init\n+ U pthread_spin_init\n+ U rdmacore52_0__verbs_init_and_alloc_context\n+ U rdmacore52_0_ibv_cmd_get_context\n+ U rdmacore52_0_ocrdma_alloc_pd\n+ U rdmacore52_0_ocrdma_arm_cq\n+ U rdmacore52_0_ocrdma_attach_mcast\n+ U rdmacore52_0_ocrdma_create_ah\n+ U rdmacore52_0_ocrdma_create_cq\n+ U rdmacore52_0_ocrdma_create_qp\n+ U rdmacore52_0_ocrdma_create_srq\n+ U rdmacore52_0_ocrdma_dereg_mr\n+ U rdmacore52_0_ocrdma_destroy_ah\n+ U rdmacore52_0_ocrdma_destroy_cq\n+ U rdmacore52_0_ocrdma_destroy_qp\n+ U rdmacore52_0_ocrdma_destroy_srq\n+ U rdmacore52_0_ocrdma_detach_mcast\n+ U rdmacore52_0_ocrdma_free_pd\n+ U rdmacore52_0_ocrdma_init_ahid_tbl\n+ U rdmacore52_0_ocrdma_modify_qp\n+ U rdmacore52_0_ocrdma_modify_srq\n+ U rdmacore52_0_ocrdma_poll_cq\n+ U rdmacore52_0_ocrdma_post_recv\n+ U rdmacore52_0_ocrdma_post_send\n+ U rdmacore52_0_ocrdma_post_srq_recv\n+ U rdmacore52_0_ocrdma_query_device\n+ U rdmacore52_0_ocrdma_query_port\n+ U rdmacore52_0_ocrdma_query_qp\n+ U rdmacore52_0_ocrdma_query_srq\n+ U rdmacore52_0_ocrdma_reg_mr\n+ U rdmacore52_0_ocrdma_resize_cq\n+ U rdmacore52_0_verbs_register_driver_34\n+ U rdmacore52_0_verbs_set_ops\n+ U rdmacore52_0_verbs_uninit_context\n+0000000000000020 r ucna_table\n+0000000000000000 D verbs_provider_ocrdma\n \n ocrdma_verbs.c.o:\n 0000000000000000 r .LC0\n 0000000000000000 r .LC1\n 0000000000000038 r .LC3\n 0000000000000068 r .LC4\n 0000000000000008 r .LC5\n@@ -104,60 +157,7 @@\n 0000000000003220 T rdmacore52_0_ocrdma_post_srq_recv\n 0000000000000600 T rdmacore52_0_ocrdma_query_device\n 0000000000000680 T rdmacore52_0_ocrdma_query_port\n 00000000000010c0 T rdmacore52_0_ocrdma_query_qp\n 0000000000000f40 T rdmacore52_0_ocrdma_query_srq\n 0000000000000890 T rdmacore52_0_ocrdma_reg_mr\n 0000000000000ba0 T rdmacore52_0_ocrdma_resize_cq\n-\n-ocrdma_main.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r __func__.0\n- U __printf_chk\n- U __stack_chk_fail\n- U calloc\n-0000000000000000 t drv__register_driver\n- U free\n- U mmap\n- U munmap\n-00000000000000c0 t ocrdma_alloc_context\n-0000000000000000 d ocrdma_ctx_ops\n-0000000000000000 d ocrdma_dev_ops\n-0000000000000010 t ocrdma_device_alloc\n-0000000000000080 t ocrdma_free_context\n-0000000000000000 t ocrdma_uninit_device\n- U pthread_mutex_init\n- U pthread_spin_init\n- U rdmacore52_0__verbs_init_and_alloc_context\n- U rdmacore52_0_ibv_cmd_get_context\n- U rdmacore52_0_ocrdma_alloc_pd\n- U rdmacore52_0_ocrdma_arm_cq\n- U rdmacore52_0_ocrdma_attach_mcast\n- U rdmacore52_0_ocrdma_create_ah\n- U rdmacore52_0_ocrdma_create_cq\n- U rdmacore52_0_ocrdma_create_qp\n- U rdmacore52_0_ocrdma_create_srq\n- U rdmacore52_0_ocrdma_dereg_mr\n- U rdmacore52_0_ocrdma_destroy_ah\n- U rdmacore52_0_ocrdma_destroy_cq\n- U rdmacore52_0_ocrdma_destroy_qp\n- U rdmacore52_0_ocrdma_destroy_srq\n- U rdmacore52_0_ocrdma_detach_mcast\n- U rdmacore52_0_ocrdma_free_pd\n- U rdmacore52_0_ocrdma_init_ahid_tbl\n- U rdmacore52_0_ocrdma_modify_qp\n- U rdmacore52_0_ocrdma_modify_srq\n- U rdmacore52_0_ocrdma_poll_cq\n- U rdmacore52_0_ocrdma_post_recv\n- U rdmacore52_0_ocrdma_post_send\n- U rdmacore52_0_ocrdma_post_srq_recv\n- U rdmacore52_0_ocrdma_query_device\n- U rdmacore52_0_ocrdma_query_port\n- U rdmacore52_0_ocrdma_query_qp\n- U rdmacore52_0_ocrdma_query_srq\n- U rdmacore52_0_ocrdma_reg_mr\n- U rdmacore52_0_ocrdma_resize_cq\n- U rdmacore52_0_verbs_register_driver_34\n- U rdmacore52_0_verbs_set_ops\n- U rdmacore52_0_verbs_uninit_context\n-0000000000000020 r ucna_table\n-0000000000000000 D verbs_provider_ocrdma\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,4 +1,4 @@\n ---------- 0 0 0 960 1970-01-01 00:00:00.000000 /\n ---------- 0 0 0 0 1970-01-01 00:00:00.000000 //\n-?rw-r--r-- 0 0 0 26392 1970-01-01 00:00:00.000000 ocrdma_verbs.c.o\n ?rw-r--r-- 0 0 0 7600 1970-01-01 00:00:00.000000 ocrdma_main.c.o\n+?rw-r--r-- 0 0 0 26392 1970-01-01 00:00:00.000000 ocrdma_verbs.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libqedr-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libqedr-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,9 +1,13 @@\n \n Archive index:\n+rdmacore52_0_qelr_chain_get_last_elem in qelr_chain.c.o\n+rdmacore52_0_qelr_chain_reset in qelr_chain.c.o\n+rdmacore52_0_qelr_chain_alloc in qelr_chain.c.o\n+rdmacore52_0_qelr_chain_free in qelr_chain.c.o\n rdmacore52_0_qelr_query_device in qelr_verbs.c.o\n rdmacore52_0_qelr_query_port in qelr_verbs.c.o\n rdmacore52_0_qelr_alloc_pd in qelr_verbs.c.o\n rdmacore52_0_qelr_dealloc_pd in qelr_verbs.c.o\n rdmacore52_0_qelr_reg_mr in qelr_verbs.c.o\n rdmacore52_0_qelr_dereg_mr in qelr_verbs.c.o\n rdmacore52_0_qelr_create_cq in qelr_verbs.c.o\n@@ -25,18 +29,25 @@\n rdmacore52_0_qelr_open_xrcd in qelr_verbs.c.o\n rdmacore52_0_qelr_close_xrcd in qelr_verbs.c.o\n rdmacore52_0_qelr_get_srq_num in qelr_verbs.c.o\n rdmacore52_0_qelr_create_srq_ex in qelr_verbs.c.o\n rdmacore52_0_qelr_create_qp_ex in qelr_verbs.c.o\n rdmacore52_0_qelr_create_qp in qelr_verbs.c.o\n verbs_provider_qedr in qelr_main.c.o\n-rdmacore52_0_qelr_chain_get_last_elem in qelr_chain.c.o\n-rdmacore52_0_qelr_chain_reset in qelr_chain.c.o\n-rdmacore52_0_qelr_chain_alloc in qelr_chain.c.o\n-rdmacore52_0_qelr_chain_free in qelr_chain.c.o\n+\n+qelr_chain.c.o:\n+ U __errno_location\n+ U ibv_dofork_range\n+ U ibv_dontfork_range\n+ U mmap\n+ U munmap\n+0000000000000040 T rdmacore52_0_qelr_chain_alloc\n+0000000000000130 T rdmacore52_0_qelr_chain_free\n+0000000000000000 T rdmacore52_0_qelr_chain_get_last_elem\n+0000000000000020 T rdmacore52_0_qelr_chain_reset\n \n qelr_verbs.c.o:\n 0000000000000000 r .LC0\n 0000000000000038 r .LC1\n 0000000000000288 r .LC10\n 0000000000000300 r .LC11\n 0000000000000340 r .LC12\n@@ -272,18 +283,7 @@\n U rdmacore52_0_qelr_query_srq\n U rdmacore52_0_qelr_reg_mr\n U rdmacore52_0_verbs_register_driver_34\n U rdmacore52_0_verbs_set_ops\n U rdmacore52_0_verbs_uninit_context\n U sysconf\n 0000000000000000 D verbs_provider_qedr\n-\n-qelr_chain.c.o:\n- U __errno_location\n- U ibv_dofork_range\n- U ibv_dontfork_range\n- U mmap\n- U munmap\n-0000000000000040 T rdmacore52_0_qelr_chain_alloc\n-0000000000000130 T rdmacore52_0_qelr_chain_free\n-0000000000000000 T rdmacore52_0_qelr_chain_get_last_elem\n-0000000000000020 T rdmacore52_0_qelr_chain_reset\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,4 +1,4 @@\n ---------- 0 0 0 1082 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 2184 1970-01-01 00:00:00.000000 qelr_chain.c.o\n ?rw-r--r-- 0 0 0 51088 1970-01-01 00:00:00.000000 qelr_verbs.c.o\n ?rw-r--r-- 0 0 0 9408 1970-01-01 00:00:00.000000 qelr_main.c.o\n-?rw-r--r-- 0 0 0 2184 1970-01-01 00:00:00.000000 qelr_chain.c.o\n"}]}, {"source1": "./usr/lib/x86_64-linux-gnu/libvmw_pvrdma-rdmav34.a", "source2": "./usr/lib/x86_64-linux-gnu/libvmw_pvrdma-rdmav34.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,9 +1,16 @@\n \n Archive index:\n+rdmacore52_0_pvrdma_alloc_cq_buf in cq.c.o\n+rdmacore52_0_pvrdma_poll_cq in cq.c.o\n+rdmacore52_0_pvrdma_cq_clean_int in cq.c.o\n+rdmacore52_0_pvrdma_cq_clean in cq.c.o\n+rdmacore52_0_pvrdma_create_cq in cq.c.o\n+rdmacore52_0_pvrdma_destroy_cq in cq.c.o\n+rdmacore52_0_pvrdma_req_notify_cq in cq.c.o\n rdmacore52_0_pvrdma_alloc_buf in pvrdma_main.c.o\n rdmacore52_0_pvrdma_free_buf in pvrdma_main.c.o\n verbs_provider_vmw_pvrdma in pvrdma_main.c.o\n rdmacore52_0_pvrdma_alloc_qp_buf in qp.c.o\n rdmacore52_0_pvrdma_init_srq_queue in qp.c.o\n rdmacore52_0_pvrdma_modify_srq in qp.c.o\n rdmacore52_0_pvrdma_query_srq in qp.c.o\n@@ -21,21 +28,34 @@\n rdmacore52_0_pvrdma_query_port in verbs.c.o\n rdmacore52_0_pvrdma_alloc_pd in verbs.c.o\n rdmacore52_0_pvrdma_free_pd in verbs.c.o\n rdmacore52_0_pvrdma_reg_mr in verbs.c.o\n rdmacore52_0_pvrdma_dereg_mr in verbs.c.o\n rdmacore52_0_pvrdma_create_ah in verbs.c.o\n rdmacore52_0_pvrdma_destroy_ah in verbs.c.o\n-rdmacore52_0_pvrdma_alloc_cq_buf in cq.c.o\n-rdmacore52_0_pvrdma_poll_cq in cq.c.o\n-rdmacore52_0_pvrdma_cq_clean_int in cq.c.o\n-rdmacore52_0_pvrdma_cq_clean in cq.c.o\n-rdmacore52_0_pvrdma_create_cq in cq.c.o\n-rdmacore52_0_pvrdma_destroy_cq in cq.c.o\n-rdmacore52_0_pvrdma_req_notify_cq in cq.c.o\n+\n+cq.c.o:\n+ U __stack_chk_fail\n+ U free\n+ U malloc\n+ U memset\n+ U pthread_spin_init\n+ U pthread_spin_lock\n+ U pthread_spin_unlock\n+ U rdmacore52_0_ibv_cmd_create_cq\n+ U rdmacore52_0_ibv_cmd_destroy_cq\n+ U rdmacore52_0_pvrdma_alloc_buf\n+0000000000000000 T rdmacore52_0_pvrdma_alloc_cq_buf\n+0000000000000300 T rdmacore52_0_pvrdma_cq_clean\n+00000000000001e0 T rdmacore52_0_pvrdma_cq_clean_int\n+0000000000000430 T rdmacore52_0_pvrdma_create_cq\n+00000000000005d0 T rdmacore52_0_pvrdma_destroy_cq\n+ U rdmacore52_0_pvrdma_free_buf\n+0000000000000060 T rdmacore52_0_pvrdma_poll_cq\n+0000000000000610 T rdmacore52_0_pvrdma_req_notify_cq\n \n pvrdma_main.c.o:\n U __errno_location\n U __stack_chk_fail\n U calloc\n 0000000000000000 t drv__register_driver\n U free\n@@ -143,27 +163,7 @@\n 00000000000002a0 T rdmacore52_0_pvrdma_create_ah\n 0000000000000270 T rdmacore52_0_pvrdma_dereg_mr\n 0000000000000480 T rdmacore52_0_pvrdma_destroy_ah\n 0000000000000190 T rdmacore52_0_pvrdma_free_pd\n 0000000000000000 T rdmacore52_0_pvrdma_query_device\n 00000000000000a0 T rdmacore52_0_pvrdma_query_port\n 00000000000001c0 T rdmacore52_0_pvrdma_reg_mr\n-\n-cq.c.o:\n- U __stack_chk_fail\n- U free\n- U malloc\n- U memset\n- U pthread_spin_init\n- U pthread_spin_lock\n- U pthread_spin_unlock\n- U rdmacore52_0_ibv_cmd_create_cq\n- U rdmacore52_0_ibv_cmd_destroy_cq\n- U rdmacore52_0_pvrdma_alloc_buf\n-0000000000000000 T rdmacore52_0_pvrdma_alloc_cq_buf\n-0000000000000300 T rdmacore52_0_pvrdma_cq_clean\n-00000000000001e0 T rdmacore52_0_pvrdma_cq_clean_int\n-0000000000000430 T rdmacore52_0_pvrdma_create_cq\n-00000000000005d0 T rdmacore52_0_pvrdma_destroy_cq\n- U rdmacore52_0_pvrdma_free_buf\n-0000000000000060 T rdmacore52_0_pvrdma_poll_cq\n-0000000000000610 T rdmacore52_0_pvrdma_req_notify_cq\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,5 +1,5 @@\n ---------- 0 0 0 1114 1970-01-01 00:00:00.000000 /\n+?rw-r--r-- 0 0 0 4432 1970-01-01 00:00:00.000000 cq.c.o\n ?rw-r--r-- 0 0 0 7640 1970-01-01 00:00:00.000000 pvrdma_main.c.o\n ?rw-r--r-- 0 0 0 11840 1970-01-01 00:00:00.000000 qp.c.o\n ?rw-r--r-- 0 0 0 4520 1970-01-01 00:00:00.000000 verbs.c.o\n-?rw-r--r-- 0 0 0 4432 1970-01-01 00:00:00.000000 cq.c.o\n"}]}]}]}]}, {"source1": "librdmacm-dev_52.0-2_amd64.deb", "source2": "librdmacm-dev_52.0-2_amd64.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2024-06-27 11:49:34.000000 debian-binary\n--rw-r--r-- 0 0 0 2648 2024-06-27 11:49:34.000000 control.tar.xz\n--rw-r--r-- 0 0 0 122732 2024-06-27 11:49:34.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 2652 2024-06-27 11:49:34.000000 control.tar.xz\n+-rw-r--r-- 0 0 0 122696 2024-06-27 11:49:34.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "./usr/lib/x86_64-linux-gnu/librdmacm.a", "source2": "./usr/lib/x86_64-linux-gnu/librdmacm.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "unified_diff": "@@ -1,47 +1,14 @@\n \n Archive index:\n-rbind in rsocket.c.o\n-rlisten in rsocket.c.o\n-rconnect in rsocket.c.o\n-rrecv in rsocket.c.o\n-rrecvmsg in rsocket.c.o\n-rread in rsocket.c.o\n-rreadv in rsocket.c.o\n-rsend in rsocket.c.o\n-rsendto in rsocket.c.o\n-rsendmsg in rsocket.c.o\n-rwrite in rsocket.c.o\n-rwritev in rsocket.c.o\n-rpoll in rsocket.c.o\n-rselect in rsocket.c.o\n-rshutdown in rsocket.c.o\n-rgetpeername in rsocket.c.o\n-raccept in rsocket.c.o\n-rrecvfrom in rsocket.c.o\n-rgetsockname in rsocket.c.o\n-rsetsockopt in rsocket.c.o\n-rgetsockopt in rsocket.c.o\n-rfcntl in rsocket.c.o\n-riomap in rsocket.c.o\n-riounmap in rsocket.c.o\n-rsocket in rsocket.c.o\n-rclose in rsocket.c.o\n-riowrite in rsocket.c.o\n rdmacore52_0_idx_insert in indexer.c.o\n rdmacore52_0_idx_remove in indexer.c.o\n rdmacore52_0_idx_replace in indexer.c.o\n rdmacore52_0_idm_set in indexer.c.o\n rdmacore52_0_idm_clear in indexer.c.o\n-rdmacore52_0_ucma_ib_init in acm.c.o\n-rdmacore52_0_ucma_ib_cleanup in acm.c.o\n-rdmacore52_0_ucma_ib_resolve in acm.c.o\n-rdmacore52_0_ucma_set_sid in addrinfo.c.o\n-rdma_freeaddrinfo in addrinfo.c.o\n-rdma_getaddrinfo in addrinfo.c.o\n rdma_free_devices in cma.c.o\n rdma_destroy_event_channel in cma.c.o\n rdma_destroy_id in cma.c.o\n rdmacore52_0_ucma_addrlen in cma.c.o\n rdmacore52_0_af_ib_support in cma.c.o\n rdma_bind_addr in cma.c.o\n rdmacore52_0_ucma_init in cma.c.o\n@@ -80,14 +47,283 @@\n rdma_create_ep in cma.c.o\n rdmacore52_0_ucma_max_qpsize in cma.c.o\n rdmacore52_0_ucma_get_port in cma.c.o\n rdma_get_src_port in cma.c.o\n rdma_get_dst_port in cma.c.o\n rdma_set_local_ece in cma.c.o\n rdma_get_remote_ece in cma.c.o\n+rdmacore52_0_ucma_set_sid in addrinfo.c.o\n+rdma_freeaddrinfo in addrinfo.c.o\n+rdma_getaddrinfo in addrinfo.c.o\n+rdmacore52_0_ucma_ib_init in acm.c.o\n+rdmacore52_0_ucma_ib_cleanup in acm.c.o\n+rdmacore52_0_ucma_ib_resolve in acm.c.o\n+rbind in rsocket.c.o\n+rlisten in rsocket.c.o\n+rconnect in rsocket.c.o\n+rrecv in rsocket.c.o\n+rrecvmsg in rsocket.c.o\n+rread in rsocket.c.o\n+rreadv in rsocket.c.o\n+rsend in rsocket.c.o\n+rsendto in rsocket.c.o\n+rsendmsg in rsocket.c.o\n+rwrite in rsocket.c.o\n+rwritev in rsocket.c.o\n+rpoll in rsocket.c.o\n+rselect in rsocket.c.o\n+rshutdown in rsocket.c.o\n+rgetpeername in rsocket.c.o\n+raccept in rsocket.c.o\n+rrecvfrom in rsocket.c.o\n+rgetsockname in rsocket.c.o\n+rsetsockopt in rsocket.c.o\n+rgetsockopt in rsocket.c.o\n+rfcntl in rsocket.c.o\n+riomap in rsocket.c.o\n+riounmap in rsocket.c.o\n+rsocket in rsocket.c.o\n+rclose in rsocket.c.o\n+riowrite in rsocket.c.o\n+\n+indexer.c.o:\n+0000000000000000 r .LC0\n+ U __errno_location\n+ U calloc\n+0000000000000250 T rdmacore52_0_idm_clear\n+00000000000001c0 T rdmacore52_0_idm_set\n+0000000000000000 T rdmacore52_0_idx_insert\n+0000000000000170 T rdmacore52_0_idx_remove\n+00000000000001a0 T rdmacore52_0_idx_replace\n+\n+cma.c.o:\n+0000000000000000 r .LC0\n+0000000000000000 r .LC10\n+000000000000000b r .LC11\n+0000000000000027 r .LC12\n+0000000000000040 r .LC13\n+000000000000005d r .LC14\n+0000000000000077 r .LC15\n+0000000000000048 r .LC16\n+0000000000000095 r .LC17\n+00000000000000b1 r .LC18\n+00000000000000cb r .LC19\n+00000000000000e2 r .LC20\n+00000000000000fc r .LC21\n+0000000000000117 r .LC22\n+0000000000000134 r .LC23\n+0000000000000151 r .LC24\n+000000000000016f r .LC25\n+0000000000000189 r .LC26\n+00000000000001a5 r .LC27\n+0000000000000068 r .LC28\n+0000000000000003 r .LC4\n+0000000000000000 r .LC5\n+0000000000000020 r .LC6\n+0000000000000000 r .LC7\n+ U __errno_location\n+ U __memcpy_chk\n+ U __stack_chk_fail\n+ U __syslog_chk\n+ U calloc\n+0000000000000540 t check_abi_version_nl_cb\n+ U close\n+0000000000000000 d cma_dev_list\n+0000000000000260 b dev_cdev\n+0000000000000000 t dev_cmp\n+00000000000002a8 b dev_list\n+0000000000000000 d dev_name\n+ U free\n+ U ibv_alloc_pd\n+ U ibv_attach_mcast\n+ U ibv_close_device\n+ U ibv_copy_ah_attr_from_kern\n+ U ibv_copy_path_rec_from_kern\n+ U ibv_copy_qp_attr_from_kern\n+ U ibv_create_comp_channel\n+ U ibv_create_cq\n+ U ibv_create_qp\n+ U ibv_create_srq\n+ U ibv_dealloc_pd\n+ U ibv_destroy_comp_channel\n+ U ibv_destroy_cq\n+ U ibv_destroy_qp\n+ U ibv_destroy_srq\n+ U ibv_detach_mcast\n+ U ibv_free_device_list\n+ U ibv_get_device_guid\n+ U ibv_get_device_index\n+ U ibv_get_device_list\n+ U ibv_get_pkey_index\n+ U ibv_get_sysfs_path\n+ U ibv_modify_qp\n+ U ibv_open_device\n+ U ibv_query_device\n+ U ibv_query_ece\n+ U ibv_query_port\n+ U ibv_read_sysfs_file\n+ U ibv_set_ece\n+0000000000000020 b idm_lock\n+0000000000000860 t insert_cma_dev.isra.0\n+ U malloc\n+ U memcmp\n+ U memcpy\n+0000000000000280 b mut\n+ U nl_socket_free\n+ U nla_get_string\n+ U nla_get_u64\n+ U nlmsg_hdr\n+ U nlmsg_parse\n+ U pthread_cond_destroy\n+ U pthread_cond_init\n+ U pthread_cond_signal\n+ U pthread_cond_wait\n+ U pthread_mutex_destroy\n+ U pthread_mutex_init\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U qsort\n+0000000000005c50 T rdma_accept\n+0000000000003c50 T rdma_ack_cm_event\n+00000000000018f0 T rdma_bind_addr\n+00000000000010c0 t rdma_bind_addr2\n+00000000000058e0 T rdma_connect\n+0000000000006c70 T rdma_create_ep\n+00000000000020c0 T rdma_create_event_channel\n+0000000000002090 T rdma_create_id\n+0000000000001e20 t rdma_create_id2\n+00000000000035c0 T rdma_create_qp\n+0000000000002fb0 T rdma_create_qp_ex\n+0000000000002be0 T rdma_create_srq\n+0000000000002880 T rdma_create_srq_ex\n+00000000000069c0 T rdma_destroy_ep\n+0000000000001750 T rdma_destroy_event_channel\n+0000000000001770 T rdma_destroy_id\n+0000000000003680 T rdma_destroy_qp\n+0000000000002f00 T rdma_destroy_srq\n+00000000000061b0 T rdma_disconnect\n+0000000000003d10 T rdma_establish\n+0000000000003d40 T rdma_event_str\n+0000000000001590 T rdma_free_devices\n+0000000000000014 t rdma_free_devices.cold\n+ U rdma_freeaddrinfo\n+0000000000004240 T rdma_get_cm_event\n+0000000000001ca0 T rdma_get_devices\n+00000000000070f0 T rdma_get_dst_port\n+0000000000007180 T rdma_get_remote_ece\n+0000000000006770 T rdma_get_request\n+00000000000070b0 T rdma_get_src_port\n+ U rdma_getaddrinfo\n+0000000000002330 T rdma_init_qp_attr\n+00000000000066f0 T rdma_join_multicast\n+00000000000062e0 t rdma_join_multicast2\n+0000000000006630 T rdma_join_multicast_ex\n+00000000000039c0 T rdma_leave_multicast\n+0000000000003740 T rdma_listen\n+0000000000003f10 T rdma_migrate_id\n+0000000000003830 T rdma_notify\n+0000000000003800 T rdma_reject\n+0000000000003810 T rdma_reject_ece\n+0000000000005350 T rdma_resolve_addr\n+0000000000005240 t rdma_resolve_addr2\n+0000000000005680 T rdma_resolve_route\n+0000000000007130 T rdma_set_local_ece\n+0000000000003e60 T rdma_set_option\n+0000000000000040 d rdmacore52_0_abi_ver\n+0000000000000000 B rdmacore52_0_af_ib_support\n+ U rdmacore52_0_idm_clear\n+ U rdmacore52_0_idm_set\n+ U rdmacore52_0_open_cdev\n+ U rdmacore52_0_rdmanl_get_chardev\n+ U rdmacore52_0_rdmanl_policy\n+ U rdmacore52_0_rdmanl_socket_alloc\n+00000000000018a0 T rdmacore52_0_ucma_addrlen\n+0000000000005100 T rdmacore52_0_ucma_complete\n+0000000000007070 T rdmacore52_0_ucma_get_port\n+0000000000001a70 T rdmacore52_0_ucma_init\n+0000000000006f90 T rdmacore52_0_ucma_max_qpsize\n+00000000000038d0 T rdmacore52_0_ucma_shutdown\n+0000000000000710 t reject_with_reason\n+ U sem_destroy\n+ U sem_init\n+ U sem_post\n+ U sem_wait\n+ U snprintf\n+ U strtol\n+0000000000000ab0 t sync_devices_list\n+000000000000000a t sync_devices_list.cold\n+0000000000000630 t ucma_destroy_kern_id\n+0000000000000940 t ucma_free_id\n+0000000000000000 t ucma_free_id.cold\n+0000000000000d10 t ucma_get_device\n+0000000000000060 b ucma_idm\n+00000000000013c0 t ucma_init_conn_qp\n+0000000000000020 t ucma_init_device\n+0000000000002450 t ucma_init_ud_qp\n+00000000000025d0 t ucma_modify_qp_rtr\n+0000000000002700 t ucma_process_conn_resp\n+0000000000000f40 t ucma_query_addr\n+0000000000000200 t ucma_query_gid\n+0000000000000320 t ucma_query_path\n+00000000000011a0 t ucma_query_route\n+ U write\n+\n+addrinfo.c.o:\n+ U __errno_location\n+ U __stack_chk_fail\n+ U calloc\n+ U free\n+ U freeaddrinfo\n+ U getaddrinfo\n+ U malloc\n+ U memcpy\n+0000000000000000 b nohints\n+0000000000000160 T rdma_freeaddrinfo\n+0000000000000210 T rdma_getaddrinfo\n+ U rdmacore52_0_ucma_get_port\n+ U rdmacore52_0_ucma_ib_resolve\n+ U rdmacore52_0_ucma_init\n+00000000000000d0 T rdmacore52_0_ucma_set_sid\n+ U strdup\n+0000000000000000 t ucma_convert_in6.isra.0\n+\n+acm.c.o:\n+0000000000000000 r .LC0\n+0000000000000003 r .LC1\n+0000000000000013 r .LC2\n+0000000000000000 r .LC3\n+0000000000000000 r .LC5\n+ U __errno_location\n+ U __isoc99_fscanf\n+ U __stack_chk_fail\n+0000000000000020 b acm_lock\n+ U calloc\n+ U close\n+ U connect\n+ U fclose\n+ U fopen\n+ U free\n+0000000000000000 b init.0\n+ U memcpy\n+ U pthread_mutex_lock\n+ U pthread_mutex_unlock\n+ U rdma_freeaddrinfo\n+ U rdmacore52_0_af_ib_support\n+0000000000000200 T rdmacore52_0_ucma_ib_cleanup\n+00000000000001e0 T rdmacore52_0_ucma_ib_init\n+0000000000000230 T rdmacore52_0_ucma_ib_resolve\n+ U rdmacore52_0_ucma_set_sid\n+ U recv\n+ U send\n+0000000000000004 b server_port\n+ U shutdown\n+0000000000000000 d sock\n+ U socket\n+ U strdup\n+0000000000000000 t ucma_ib_init.part.0\n \n rsocket.c.o:\n 0000000000000000 r .LC1\n 0000000000000000 r .LC13\n 0000000000000000 r .LC14\n 0000000000000002 r .LC15\n 0000000000000028 r .LC17\n@@ -272,243 +508,7 @@\n U tfind\n U tsearch\n 00000000000000c0 d udp_svc\n 0000000000000818 b udp_svc_fds\n 0000000000005740 t udp_svc_run\n 0000000000000000 d wake_up_interval\n U write\n-\n-indexer.c.o:\n-0000000000000000 r .LC0\n- U __errno_location\n- U calloc\n-0000000000000250 T rdmacore52_0_idm_clear\n-00000000000001c0 T rdmacore52_0_idm_set\n-0000000000000000 T rdmacore52_0_idx_insert\n-0000000000000170 T rdmacore52_0_idx_remove\n-00000000000001a0 T rdmacore52_0_idx_replace\n-\n-acm.c.o:\n-0000000000000000 r .LC0\n-0000000000000003 r .LC1\n-0000000000000013 r .LC2\n-0000000000000000 r .LC3\n-0000000000000000 r .LC5\n- U __errno_location\n- U __isoc99_fscanf\n- U __stack_chk_fail\n-0000000000000020 b acm_lock\n- U calloc\n- U close\n- U connect\n- U fclose\n- U fopen\n- U free\n-0000000000000000 b init.0\n- U memcpy\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U rdma_freeaddrinfo\n- U rdmacore52_0_af_ib_support\n-0000000000000200 T rdmacore52_0_ucma_ib_cleanup\n-00000000000001e0 T rdmacore52_0_ucma_ib_init\n-0000000000000230 T rdmacore52_0_ucma_ib_resolve\n- U rdmacore52_0_ucma_set_sid\n- U recv\n- U send\n-0000000000000004 b server_port\n- U shutdown\n-0000000000000000 d sock\n- U socket\n- U strdup\n-0000000000000000 t ucma_ib_init.part.0\n-\n-addrinfo.c.o:\n- U __errno_location\n- U __stack_chk_fail\n- U calloc\n- U free\n- U freeaddrinfo\n- U getaddrinfo\n- U malloc\n- U memcpy\n-0000000000000000 b nohints\n-0000000000000160 T rdma_freeaddrinfo\n-0000000000000210 T rdma_getaddrinfo\n- U rdmacore52_0_ucma_get_port\n- U rdmacore52_0_ucma_ib_resolve\n- U rdmacore52_0_ucma_init\n-00000000000000d0 T rdmacore52_0_ucma_set_sid\n- U strdup\n-0000000000000000 t ucma_convert_in6.isra.0\n-\n-cma.c.o:\n-0000000000000000 r .LC0\n-0000000000000000 r .LC10\n-000000000000000b r .LC11\n-0000000000000027 r .LC12\n-0000000000000040 r .LC13\n-000000000000005d r .LC14\n-0000000000000077 r .LC15\n-0000000000000048 r .LC16\n-0000000000000095 r .LC17\n-00000000000000b1 r .LC18\n-00000000000000cb r .LC19\n-00000000000000e2 r .LC20\n-00000000000000fc r .LC21\n-0000000000000117 r .LC22\n-0000000000000134 r .LC23\n-0000000000000151 r .LC24\n-000000000000016f r .LC25\n-0000000000000189 r .LC26\n-00000000000001a5 r .LC27\n-0000000000000068 r .LC28\n-0000000000000003 r .LC4\n-0000000000000000 r .LC5\n-0000000000000020 r .LC6\n-0000000000000000 r .LC7\n- U __errno_location\n- U __memcpy_chk\n- U __stack_chk_fail\n- U __syslog_chk\n- U calloc\n-0000000000000540 t check_abi_version_nl_cb\n- U close\n-0000000000000000 d cma_dev_list\n-0000000000000260 b dev_cdev\n-0000000000000000 t dev_cmp\n-00000000000002a8 b dev_list\n-0000000000000000 d dev_name\n- U free\n- U ibv_alloc_pd\n- U ibv_attach_mcast\n- U ibv_close_device\n- U ibv_copy_ah_attr_from_kern\n- U ibv_copy_path_rec_from_kern\n- U ibv_copy_qp_attr_from_kern\n- U ibv_create_comp_channel\n- U ibv_create_cq\n- U ibv_create_qp\n- U ibv_create_srq\n- U ibv_dealloc_pd\n- U ibv_destroy_comp_channel\n- U ibv_destroy_cq\n- U ibv_destroy_qp\n- U ibv_destroy_srq\n- U ibv_detach_mcast\n- U ibv_free_device_list\n- U ibv_get_device_guid\n- U ibv_get_device_index\n- U ibv_get_device_list\n- U ibv_get_pkey_index\n- U ibv_get_sysfs_path\n- U ibv_modify_qp\n- U ibv_open_device\n- U ibv_query_device\n- U ibv_query_ece\n- U ibv_query_port\n- U ibv_read_sysfs_file\n- U ibv_set_ece\n-0000000000000020 b idm_lock\n-0000000000000860 t insert_cma_dev.isra.0\n- U malloc\n- U memcmp\n- U memcpy\n-0000000000000280 b mut\n- U nl_socket_free\n- U nla_get_string\n- U nla_get_u64\n- U nlmsg_hdr\n- U nlmsg_parse\n- U pthread_cond_destroy\n- U pthread_cond_init\n- U pthread_cond_signal\n- U pthread_cond_wait\n- U pthread_mutex_destroy\n- U pthread_mutex_init\n- U pthread_mutex_lock\n- U pthread_mutex_unlock\n- U qsort\n-0000000000005c50 T rdma_accept\n-0000000000003c50 T rdma_ack_cm_event\n-00000000000018f0 T rdma_bind_addr\n-00000000000010c0 t rdma_bind_addr2\n-00000000000058e0 T rdma_connect\n-0000000000006c70 T rdma_create_ep\n-00000000000020c0 T rdma_create_event_channel\n-0000000000002090 T rdma_create_id\n-0000000000001e20 t rdma_create_id2\n-00000000000035c0 T rdma_create_qp\n-0000000000002fb0 T rdma_create_qp_ex\n-0000000000002be0 T rdma_create_srq\n-0000000000002880 T rdma_create_srq_ex\n-00000000000069c0 T rdma_destroy_ep\n-0000000000001750 T rdma_destroy_event_channel\n-0000000000001770 T rdma_destroy_id\n-0000000000003680 T rdma_destroy_qp\n-0000000000002f00 T rdma_destroy_srq\n-00000000000061b0 T rdma_disconnect\n-0000000000003d10 T rdma_establish\n-0000000000003d40 T rdma_event_str\n-0000000000001590 T rdma_free_devices\n-0000000000000014 t rdma_free_devices.cold\n- U rdma_freeaddrinfo\n-0000000000004240 T rdma_get_cm_event\n-0000000000001ca0 T rdma_get_devices\n-00000000000070f0 T rdma_get_dst_port\n-0000000000007180 T rdma_get_remote_ece\n-0000000000006770 T rdma_get_request\n-00000000000070b0 T rdma_get_src_port\n- U rdma_getaddrinfo\n-0000000000002330 T rdma_init_qp_attr\n-00000000000066f0 T rdma_join_multicast\n-00000000000062e0 t rdma_join_multicast2\n-0000000000006630 T rdma_join_multicast_ex\n-00000000000039c0 T rdma_leave_multicast\n-0000000000003740 T rdma_listen\n-0000000000003f10 T rdma_migrate_id\n-0000000000003830 T rdma_notify\n-0000000000003800 T rdma_reject\n-0000000000003810 T rdma_reject_ece\n-0000000000005350 T rdma_resolve_addr\n-0000000000005240 t rdma_resolve_addr2\n-0000000000005680 T rdma_resolve_route\n-0000000000007130 T rdma_set_local_ece\n-0000000000003e60 T rdma_set_option\n-0000000000000040 d rdmacore52_0_abi_ver\n-0000000000000000 B rdmacore52_0_af_ib_support\n- U rdmacore52_0_idm_clear\n- U rdmacore52_0_idm_set\n- U rdmacore52_0_open_cdev\n- U rdmacore52_0_rdmanl_get_chardev\n- U rdmacore52_0_rdmanl_policy\n- U rdmacore52_0_rdmanl_socket_alloc\n-00000000000018a0 T rdmacore52_0_ucma_addrlen\n-0000000000005100 T rdmacore52_0_ucma_complete\n-0000000000007070 T rdmacore52_0_ucma_get_port\n-0000000000001a70 T rdmacore52_0_ucma_init\n-0000000000006f90 T rdmacore52_0_ucma_max_qpsize\n-00000000000038d0 T rdmacore52_0_ucma_shutdown\n-0000000000000710 t reject_with_reason\n- U sem_destroy\n- U sem_init\n- U sem_post\n- U sem_wait\n- U snprintf\n- U strtol\n-0000000000000ab0 t sync_devices_list\n-000000000000000a t sync_devices_list.cold\n-0000000000000630 t ucma_destroy_kern_id\n-0000000000000940 t ucma_free_id\n-0000000000000000 t ucma_free_id.cold\n-0000000000000d10 t ucma_get_device\n-0000000000000060 b ucma_idm\n-00000000000013c0 t ucma_init_conn_qp\n-0000000000000020 t ucma_init_device\n-0000000000002450 t ucma_init_ud_qp\n-00000000000025d0 t ucma_modify_qp_rtr\n-0000000000002700 t ucma_process_conn_resp\n-0000000000000f40 t ucma_query_addr\n-0000000000000200 t ucma_query_gid\n-0000000000000320 t ucma_query_path\n-00000000000011a0 t ucma_query_route\n- U write\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,6 +1,6 @@\n ---------- 0 0 0 1684 1970-01-01 00:00:00.000000 /\n-?rw-r--r-- 0 0 0 83232 1970-01-01 00:00:00.000000 rsocket.c.o\n ?rw-r--r-- 0 0 0 2520 1970-01-01 00:00:00.000000 indexer.c.o\n-?rw-r--r-- 0 0 0 6768 1970-01-01 00:00:00.000000 acm.c.o\n-?rw-r--r-- 0 0 0 4992 1970-01-01 00:00:00.000000 addrinfo.c.o\n ?rw-r--r-- 0 0 0 59528 1970-01-01 00:00:00.000000 cma.c.o\n+?rw-r--r-- 0 0 0 4992 1970-01-01 00:00:00.000000 addrinfo.c.o\n+?rw-r--r-- 0 0 0 6768 1970-01-01 00:00:00.000000 acm.c.o\n+?rw-r--r-- 0 0 0 83232 1970-01-01 00:00:00.000000 rsocket.c.o\n"}]}]}]}]}]}