Diff of the two buildlogs: -- --- b1/build.log 2023-04-14 08:27:32.605918855 +0000 +++ b2/build.log 2023-04-14 11:01:56.478448273 +0000 @@ -1,6 +1,6 @@ I: pbuilder: network access will be disabled during build -I: Current time: Thu May 16 01:31:18 -12 2024 -I: pbuilder-time-stamp: 1715866278 +I: Current time: Fri Apr 14 22:27:46 +14 2023 +I: pbuilder-time-stamp: 1681460866 I: Building the build Environment I: extracting base tarball [/var/cache/pbuilder/bookworm-reproducible-base.tgz] I: copying local configuration @@ -16,7 +16,7 @@ I: copying [./yosys_0.23.orig.tar.gz] I: copying [./yosys_0.23-6.debian.tar.xz] I: Extracting source -gpgv: Signature made Sat Dec 3 10:16:42 2022 -12 +gpgv: Signature made Sun Dec 4 12:16:42 2022 +14 gpgv: using RSA key 57A1BF15B4F6F99B89EDB29FD39481AE1E79ACF7 gpgv: Can't check signature: No public key dpkg-source: warning: cannot verify inline signature for ./yosys_0.23-6.dsc: no acceptable signature found @@ -39,11 +39,20 @@ dpkg-source: info: applying 0020-autotest-Print-log-on-error.patch I: Not using root during the build. I: Installing the build-deps -I: user script /srv/workspace/pbuilder/14408/tmp/hooks/D02_print_environment starting +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/D01_modify_environment starting +debug: Running on codethink16-arm64. +I: Changing host+domainname to test build reproducibility +I: Adding a custom variable just for the fun of it... +I: Changing /bin/sh to bash +lrwxrwxrwx 1 root root 4 Jan 6 03:20 /bin/sh -> dash +I: Setting pbuilder2's login shell to /bin/bash +I: Setting pbuilder2's GECOS to second user,second room,second work-phone,second home-phone,second other +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/D01_modify_environment finished +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/D02_print_environment starting I: set BUILDDIR='/build' - BUILDUSERGECOS='first user,first room,first work-phone,first home-phone,first other' - BUILDUSERNAME='pbuilder1' + BUILDUSERGECOS='second user,second room,second work-phone,second home-phone,second other' + BUILDUSERNAME='pbuilder2' BUILD_ARCH='arm64' DEBIAN_FRONTEND='noninteractive' DEB_BUILD_OPTIONS='buildinfo=+all reproducible=+all parallel=8' @@ -53,38 +62,38 @@ IFS=' ' LANG='C' - LANGUAGE='en_US:en' + LANGUAGE='nl_BE:nl' LC_ALL='C' MAIL='/var/mail/root' OPTIND='1' - PATH='/usr/sbin:/usr/bin:/sbin:/bin:/usr/games' + PATH='/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path' PBCURRENTCOMMANDLINEOPERATION='build' PBUILDER_OPERATION='build' PBUILDER_PKGDATADIR='/usr/share/pbuilder' PBUILDER_PKGLIBDIR='/usr/lib/pbuilder' PBUILDER_SYSCONFDIR='/etc' - PPID='14408' + PPID='16396' PS1='# ' PS2='> ' PS4='+ ' PWD='/' SHELL='/bin/bash' SHLVL='2' - SUDO_COMMAND='/usr/bin/timeout -k 18.1h 18h /usr/bin/ionice -c 3 /usr/bin/nice /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/r-b-build.g5m4RmqA/pbuilderrc_T1hT --distribution bookworm --hookdir /etc/pbuilder/first-build-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/bookworm-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/r-b-build.g5m4RmqA/b1 --logfile b1/build.log yosys_0.23-6.dsc' + SUDO_COMMAND='/usr/bin/timeout -k 24.1h 24h /usr/bin/ionice -c 3 /usr/bin/nice -n 11 /usr/bin/unshare --uts -- /usr/sbin/pbuilder --build --configfile /srv/reproducible-results/rbuild-debian/r-b-build.g5m4RmqA/pbuilderrc_iBYP --distribution bookworm --hookdir /etc/pbuilder/rebuild-hooks --debbuildopts -b --basetgz /var/cache/pbuilder/bookworm-reproducible-base.tgz --buildresult /srv/reproducible-results/rbuild-debian/r-b-build.g5m4RmqA/b2 --logfile b2/build.log --extrapackages usrmerge yosys_0.23-6.dsc' SUDO_GID='117' SUDO_UID='110' SUDO_USER='jenkins' TERM='unknown' - TZ='/usr/share/zoneinfo/Etc/GMT+12' + TZ='/usr/share/zoneinfo/Etc/GMT-14' USER='root' USERNAME='root' _='/usr/bin/systemd-run' http_proxy='http://192.168.101.16:3128' I: uname -a - Linux codethink13-arm64 4.15.0-208-generic #220-Ubuntu SMP Mon Mar 20 14:28:12 UTC 2023 aarch64 GNU/Linux + Linux i-capture-the-hostname 4.15.0-208-generic #220-Ubuntu SMP Mon Mar 20 14:28:12 UTC 2023 aarch64 GNU/Linux I: ls -l /bin - lrwxrwxrwx 1 root root 7 May 13 04:48 /bin -> usr/bin -I: user script /srv/workspace/pbuilder/14408/tmp/hooks/D02_print_environment finished + lrwxrwxrwx 1 root root 7 Apr 12 00:26 /bin -> usr/bin +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/D02_print_environment finished -> Attempting to satisfy build-dependencies -> Creating pbuilder-satisfydepends-dummy package Package: pbuilder-satisfydepends-dummy @@ -338,7 +347,7 @@ Get: 168 http://deb.debian.org/debian bookworm/main arm64 texlive-publishers all 2022.20230122-3 [21.1 MB] Get: 169 http://deb.debian.org/debian bookworm/main arm64 texlive-science all 2022.20230122-3 [3722 kB] Get: 170 http://deb.debian.org/debian bookworm/main arm64 txt2man all 1.7.1-4 [35.4 kB] -Fetched 877 MB in 1min 25s (10.4 MB/s) +Fetched 877 MB in 1min 22s (10.7 MB/s) debconf: delaying package configuration, since apt-utils is not installed Selecting previously unselected package m4. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 19616 files and directories currently installed.) @@ -1056,8 +1065,17 @@ Writing extended state information... Building tag database... -> Finished parsing the build-deps +Reading package lists... +Building dependency tree... +Reading state information... +usrmerge is already the newest version (35). +0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. I: Building the package -I: Running cd /build/yosys-0.23/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games" HOME="/nonexistent/first-build" dpkg-genchanges -S > ../yosys_0.23-6_source.changes +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/A99_set_merged_usr starting +Re-configuring usrmerge... +I: user script /srv/workspace/pbuilder/16396/tmp/hooks/A99_set_merged_usr finished +hostname: Temporary failure in name resolution +I: Running cd /build/yosys-0.23/ && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path" HOME="/nonexistent/second-build" dpkg-buildpackage -us -uc -b && env PATH="/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/i/capture/the/path" HOME="/nonexistent/second-build" dpkg-genchanges -S > ../yosys_0.23-6_source.changes dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.23-6 dpkg-buildpackage: info: source distribution unstable @@ -1142,8 +1160,8 @@ mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.23 (git sha1 7ce5011c24b)\"; }" > kernel/version_7ce5011c24b.cc gcc -o kernel/driver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc mkdir -p techlibs/common -mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new +mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new mkdir -p kernel/ gcc -o kernel/rtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc @@ -1155,10 +1173,10 @@ gcc -o kernel/yosys.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' -DYOSYS_DATDIR='"/usr/share/yosys"' -DYOSYS_PROGRAM_PREFIX='""' kernel/yosys.cc mkdir -p kernel/ gcc -o kernel/binding.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/binding.cc -mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc +mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc mkdir -p kernel/ gcc -o kernel/cellaigs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc -mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc +mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc mkdir -p kernel/ gcc -o kernel/celledges.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc mkdir -p kernel/ @@ -1186,8 +1204,8 @@ mkdir -p libs/sha1/ gcc -o libs/sha1/sha1.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp mkdir -p libs/json11/ -gcc -o libs/json11/json11.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp mkdir -p libs/subcircuit/ +gcc -o libs/json11/json11.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp gcc -o libs/subcircuit/subcircuit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc @@ -1265,6 +1283,10 @@ bison -Wall -Werror -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y mkdir -p frontends/verilog/ gcc -o frontends/verilog/preproc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc +mkdir -p frontends/verilog/ +gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc +mkdir -p frontends/verilog/ +gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc kernel/satgen.cc: In member function 'bool Yosys::SatGen::importCell(Yosys::RTLIL::Cell*, int)': kernel/satgen.cc:1237:67: warning: 'undef_srst' may be used uninitialized [-Wmaybe-uninitialized] 1237 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); @@ -1284,10 +1306,6 @@ kernel/satgen.cc:1200:37: note: 'undef_srst' was declared here 1200 | int undef_srst; | ^~~~~~~~~~ -mkdir -p frontends/verilog/ -gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc -mkdir -p frontends/verilog/ -gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc mkdir -p passes/cmds/ gcc -o passes/cmds/exec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/exec.cc mkdir -p passes/cmds/ @@ -1589,8 +1607,6 @@ gcc -o passes/techmap/alumacc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc -mkdir -p passes/techmap/ -gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc passes/techmap/abc.cc: In member function 'virtual void {anonymous}::AbcPass::execute(std::vector >, Yosys::RTLIL::Design*)': passes/techmap/abc.cc:1953:50: warning: 'g_argidx' may be used uninitialized [-Wmaybe-uninitialized] 1953 | cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str())); @@ -1599,6 +1615,8 @@ 1671 | size_t argidx, g_argidx; | ^~~~~~~~ mkdir -p passes/techmap/ +gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc +mkdir -p passes/techmap/ gcc -o passes/techmap/bmuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bmuxmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/demuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/demuxmap.cc @@ -1757,8 +1775,8 @@ mkdir -p share/include/kernel/ cp "./"/kernel/register.h share/include/kernel/register.h mkdir -p share/include/kernel/ -cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h mkdir -p share/include/kernel/ +cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h cp "./"/kernel/celledges.h share/include/kernel/celledges.h mkdir -p share/include/kernel/ cp "./"/kernel/consteval.h share/include/kernel/consteval.h @@ -1781,8 +1799,8 @@ mkdir -p share/include/kernel/ cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h mkdir -p share/include/kernel/ -cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h mkdir -p share/include/kernel/ +cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h cp "./"/kernel/mem.h share/include/kernel/mem.h mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h @@ -1797,14 +1815,14 @@ mkdir -p share/include/passes/fsm/ cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h mkdir -p share/include/frontends/ast/ -mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h +mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h mkdir -p share/include/frontends/blif/ cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h mkdir -p share/include/backends/rtlil/ -cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h mkdir -p share/include/backends/cxxrtl/ +cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h @@ -1845,8 +1863,8 @@ mkdir -p share cp "./"/techlibs/common/simcells.v share/simcells.v mkdir -p share -mkdir -p share cp "./"/techlibs/common/techmap.v share/techmap.v +mkdir -p share cp "./"/techlibs/common/smtmap.v share/smtmap.v mkdir -p share cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v @@ -1871,8 +1889,8 @@ mkdir -p share cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v mkdir -p share/coolrunner2 -cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v mkdir -p share/coolrunner2 +cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v @@ -1881,14 +1899,14 @@ mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib mkdir -p share/ecp5 -cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh mkdir -p share/ecp5 +cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v mkdir -p share/ecp5 -cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v mkdir -p share/ecp5 +cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v @@ -1899,8 +1917,8 @@ mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt mkdir -p share/ecp5 -cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v mkdir -p share/ecp5 +cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v @@ -1917,12 +1935,12 @@ mkdir -p share/efinix cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt mkdir -p share/gatemate -mkdir -p share/gatemate cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v -cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v mkdir -p share/gatemate +cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v +mkdir -p share/gatemate cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v @@ -1933,8 +1951,8 @@ mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v mkdir -p share/gatemate -cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt mkdir -p share/gatemate +cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh @@ -1956,9 +1974,9 @@ cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt -touch techlibs/gatemate/lut_tree_lib.mk mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v +touch techlibs/gatemate/lut_tree_lib.mk mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v mkdir -p share/greenpak4 @@ -2008,8 +2026,8 @@ mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v mkdir -p share/intel/cyclone10lp -mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v +mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v @@ -2106,8 +2124,8 @@ mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v mkdir -p share/quicklogic -mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v +mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v @@ -2132,8 +2150,8 @@ mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v mkdir -p share/xilinx -cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt mkdir -p share/xilinx +cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt @@ -2154,8 +2172,8 @@ mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt mkdir -p share/xilinx -cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v mkdir -p share/xilinx +cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v @@ -2180,8 +2198,8 @@ cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v mkdir -p share/xilinx -mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v +mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v @@ -2236,9 +2254,9 @@ [Makefile.conf] ABCPULL=0 [Makefile.conf] STRIP=: +cd manual && PDF_DATE=D:20221203221520Z bash appnotes.sh Build successful. -cd manual && PDF_DATE=D:20221203221520Z bash appnotes.sh + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_010_Verilog_to_BLIF.ok -a APPNOTE_010_Verilog_to_BLIF.ok -nt APPNOTE_010_Verilog_to_BLIF.tex ']' + '[' -f APPNOTE_010_Verilog_to_BLIF/make.sh ']' @@ -5254,9 +5272,9 @@ Dumping module counter to page 1. Exec: dot -Tpdf 'counter_03.dot' > 'counter_03.pdf.new' && mv 'counter_03.pdf.new' 'counter_03.pdf' -End of script. Logfile hash: a1e6cccca1, CPU: user 0.19s system 0.01s, MEM: 13.50 MB peak +End of script. Logfile hash: a1e6cccca1, CPU: user 0.20s system 0.01s, MEM: 13.47 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 79% 4x show (1 sec), 9% 1x abc (0 sec), ... +Time spent: 78% 4x show (1 sec), 9% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_Intro' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_Intro/counter_00.pdf PRESENTATION_Intro/counter_01.pdf PRESENTATION_Intro/counter_02.pdf PRESENTATION_Intro/counter_03.pdf + make -C PRESENTATION_ExSyn @@ -5351,7 +5369,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'proc_01.dot' > 'proc_01.pdf.new' && mv 'proc_01.pdf.new' 'proc_01.pdf' -End of script. Logfile hash: c6fd6e6895, CPU: user 0.01s system 0.01s, MEM: 11.26 MB peak +End of script. Logfile hash: c6fd6e6895, CPU: user 0.01s system 0.01s, MEM: 11.27 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' @@ -5445,7 +5463,7 @@ Exec: dot -Tpdf 'proc_02.dot' > 'proc_02.pdf.new' && mv 'proc_02.pdf.new' 'proc_02.pdf' Warnings: 1 unique messages, 1 total -End of script. Logfile hash: 6c9c8edaef, CPU: user 0.01s system 0.01s, MEM: 11.23 MB peak +End of script. Logfile hash: 6c9c8edaef, CPU: user 0.02s system 0.00s, MEM: 11.21 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format pdf' @@ -5536,7 +5554,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'proc_03.dot' > 'proc_03.pdf.new' && mv 'proc_03.pdf.new' 'proc_03.pdf' -End of script. Logfile hash: 13c48860df, CPU: user 0.01s system 0.01s, MEM: 11.21 MB peak +End of script. Logfile hash: 13c48860df, CPU: user 0.01s system 0.01s, MEM: 11.17 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 0% 1x clean (0 sec), ... ../../yosys -p 'script opt_01.ys; show -notitle -prefix opt_01 -format pdf' @@ -5650,7 +5668,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'opt_01.dot' > 'opt_01.pdf.new' && mv 'opt_01.pdf.new' 'opt_01.pdf' -End of script. Logfile hash: 9f52b2c276, CPU: user 0.03s system 0.01s, MEM: 11.37 MB peak +End of script. Logfile hash: 9f52b2c276, CPU: user 0.03s system 0.00s, MEM: 11.27 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 93% 1x show (0 sec), 2% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_02.ys; show -notitle -prefix opt_02 -format pdf' @@ -5761,7 +5779,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'opt_02.dot' > 'opt_02.pdf.new' && mv 'opt_02.pdf.new' 'opt_02.pdf' -End of script. Logfile hash: 5a4000bb43, CPU: user 0.03s system 0.00s, MEM: 11.34 MB peak +End of script. Logfile hash: 5a4000bb43, CPU: user 0.03s system 0.00s, MEM: 11.32 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 93% 1x show (0 sec), 2% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_03.ys; show -notitle -prefix opt_03 -format pdf' @@ -5872,7 +5890,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'opt_03.dot' > 'opt_03.pdf.new' && mv 'opt_03.pdf.new' 'opt_03.pdf' -End of script. Logfile hash: 0cd024bc02, CPU: user 0.04s system 0.00s, MEM: 11.30 MB peak +End of script. Logfile hash: 0cd024bc02, CPU: user 0.03s system 0.01s, MEM: 11.30 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 92% 1x show (0 sec), 2% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_04.ys; show -notitle -prefix opt_04 -format pdf' @@ -6063,7 +6081,7 @@ Exec: dot -Tpdf 'opt_04.dot' > 'opt_04.pdf.new' && mv 'opt_04.pdf.new' 'opt_04.pdf' Warnings: 4 unique messages, 4 total -End of script. Logfile hash: 350e16de2a, CPU: user 0.03s system 0.01s, MEM: 11.32 MB peak +End of script. Logfile hash: 350e16de2a, CPU: user 0.04s system 0.00s, MEM: 11.23 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 91% 1x show (0 sec), 2% 4x opt_expr (0 sec), ... ../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format pdf' @@ -6291,7 +6309,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'memory_01.dot' > 'memory_01.pdf.new' && mv 'memory_01.pdf.new' 'memory_01.pdf' -End of script. Logfile hash: d4215140a5, CPU: user 0.06s system 0.01s, MEM: 11.32 MB peak +End of script. Logfile hash: d4215140a5, CPU: user 0.07s system 0.00s, MEM: 11.32 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 85% 1x show (0 sec), 3% 5x opt_expr (0 sec), ... ../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format pdf' @@ -6553,9 +6571,9 @@ Exec: dot -Tpdf 'memory_02.dot' > 'memory_02.pdf.new' && mv 'memory_02.pdf.new' 'memory_02.pdf' Warnings: 7 unique messages, 7 total -End of script. Logfile hash: 38542be5e8, CPU: user 0.07s system 0.01s, MEM: 11.43 MB peak +End of script. Logfile hash: 38542be5e8, CPU: user 0.08s system 0.00s, MEM: 11.49 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 82% 1x show (0 sec), 3% 5x opt_clean (0 sec), ... +Time spent: 83% 1x show (0 sec), 3% 5x opt_clean (0 sec), ... ../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' /----------------------------------------------------------------------------\ @@ -6625,7 +6643,7 @@ Exec: dot -Tpdf 'techmap_01.dot' > 'techmap_01.pdf.new' && mv 'techmap_01.pdf.new' 'techmap_01.pdf' Warnings: 7 unique messages, 7 total -End of script. Logfile hash: f7cde0dc8c, CPU: user 0.02s system 0.00s, MEM: 11.36 MB peak +End of script. Logfile hash: f7cde0dc8c, CPU: user 0.02s system 0.01s, MEM: 11.32 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 1x show (0 sec), 1% 1x techmap (0 sec), ... ../../yosys -p 'script abc_01.ys; show -notitle -prefix abc_01 -format pdf' @@ -6877,7 +6895,7 @@ End of script. Logfile hash: 12acbed0ed, CPU: user 0.10s system 0.00s, MEM: 13.21 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 64% 1x show (0 sec), 20% 1x abc (0 sec), ... +Time spent: 64% 1x show (0 sec), 19% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_ExSyn' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20221203221520Z)#' PRESENTATION_ExSyn/abc_01.pdf PRESENTATION_ExSyn/memory_01.pdf PRESENTATION_ExSyn/memory_02.pdf PRESENTATION_ExSyn/opt_01.pdf PRESENTATION_ExSyn/opt_02.pdf PRESENTATION_ExSyn/opt_03.pdf PRESENTATION_ExSyn/opt_04.pdf PRESENTATION_ExSyn/proc_01.pdf PRESENTATION_ExSyn/proc_02.pdf PRESENTATION_ExSyn/proc_03.pdf PRESENTATION_ExSyn/techmap_01.pdf + make -C PRESENTATION_ExAdv @@ -7033,9 +7051,9 @@ Dumping module test to page 1. Exec: dot -Tpdf 'select.dot' > 'select.pdf.new' && mv 'select.pdf.new' 'select.pdf' -End of script. Logfile hash: 75f2ae3a3a, CPU: user 0.05s system 0.00s, MEM: 11.30 MB peak +End of script. Logfile hash: 75f2ae3a3a, CPU: user 0.04s system 0.01s, MEM: 11.32 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 88% 1x show (0 sec), 3% 4x opt_expr (0 sec), ... +Time spent: 89% 1x show (0 sec), 3% 4x opt_expr (0 sec), ... ../../yosys red_or3x1_test.ys /----------------------------------------------------------------------------\ @@ -7106,9 +7124,9 @@ Dumping module test to page 1. Exec: dot -Tpdf 'red_or3x1.dot' > 'red_or3x1.pdf.new' && mv 'red_or3x1.pdf.new' 'red_or3x1.pdf' -End of script. Logfile hash: 129023a082, CPU: user 0.02s system 0.01s, MEM: 11.32 MB peak +End of script. Logfile hash: 129023a082, CPU: user 0.03s system 0.00s, MEM: 11.15 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 96% 1x show (0 sec), 2% 1x techmap (0 sec), ... +Time spent: 95% 1x show (0 sec), 2% 1x techmap (0 sec), ... ../../yosys sym_mul_test.ys /----------------------------------------------------------------------------\ @@ -7175,7 +7193,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'sym_mul.dot' > 'sym_mul.pdf.new' && mv 'sym_mul.pdf.new' 'sym_mul.pdf' -End of script. Logfile hash: 772afb568b, CPU: user 0.01s system 0.01s, MEM: 11.04 MB peak +End of script. Logfile hash: 772afb568b, CPU: user 0.02s system 0.00s, MEM: 11.17 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 1% 1x clean (0 sec), ... ../../yosys mymul_test.ys @@ -7282,7 +7300,7 @@ Warnings: 1 unique messages, 1 total End of script. Logfile hash: 126d691da5, CPU: user 0.05s system 0.00s, MEM: 11.69 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 91% 1x show (0 sec), 2% 2x clean (0 sec), ... +Time spent: 90% 1x show (0 sec), 2% 2x clean (0 sec), ... ../../yosys mulshift_test.ys /----------------------------------------------------------------------------\ @@ -7355,9 +7373,9 @@ Dumping module test to page 1. Exec: dot -Tpdf 'mulshift.dot' > 'mulshift.pdf.new' && mv 'mulshift.pdf.new' 'mulshift.pdf' -End of script. Logfile hash: e867b57f97, CPU: user 0.05s system 0.01s, MEM: 11.86 MB peak +End of script. Logfile hash: e867b57f97, CPU: user 0.05s system 0.00s, MEM: 11.86 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 87% 1x show (0 sec), 3% 3x clean (0 sec), ... +Time spent: 88% 1x show (0 sec), 3% 3x clean (0 sec), ... ../../yosys addshift_test.ys /----------------------------------------------------------------------------\ @@ -7417,7 +7435,7 @@ Dumping module test to page 1. Exec: dot -Tpdf 'addshift.dot' > 'addshift.pdf.new' && mv 'addshift.pdf.new' 'addshift.pdf' -End of script. Logfile hash: d1e94967df, CPU: user 0.01s system 0.01s, MEM: 11.25 MB peak +End of script. Logfile hash: d1e94967df, CPU: user 0.02s system 0.00s, MEM: 11.16 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 97% 1x show (0 sec), 1% 1x clean (0 sec), ... ../../yosys macc_simple_test.ys @@ -7776,7 +7794,7 @@ Dumping module macc_16_16_32 to page 1. Exec: dot -Tpdf 'macc_simple_xmap.dot' > 'macc_simple_xmap.pdf.new' && mv 'macc_simple_xmap.pdf.new' 'macc_simple_xmap.pdf' -End of script. Logfile hash: 4903010725, CPU: user 0.09s system 0.01s, MEM: 11.37 MB peak +End of script. Logfile hash: 4903010725, CPU: user 0.09s system 0.01s, MEM: 11.21 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 96% 7x show (2 sec), 1% 7x clean (0 sec), ... ../../yosys macc_xilinx_test.ys @@ -8067,7 +8085,7 @@ Exec: dot -Tpdf 'macc_xilinx_xmap.dot' > 'macc_xilinx_xmap.pdf.new' && mv 'macc_xilinx_xmap.pdf.new' 'macc_xilinx_xmap.pdf' Warnings: 15 unique messages, 54 total -End of script. Logfile hash: 1adef8c574, CPU: user 0.24s system 0.01s, MEM: 12.52 MB peak +End of script. Logfile hash: 1adef8c574, CPU: user 0.24s system 0.02s, MEM: 12.62 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 94% 11x show (3 sec), 2% 12x clean (0 sec), ... make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_ExAdv' @@ -8226,7 +8244,7 @@ \out 632435482 25b2331a 00100101101100100011001100011010 Warnings: 6 unique messages, 8 total -End of script. Logfile hash: cb8ee0bc24, CPU: user 0.05s system 0.01s, MEM: 11.80 MB peak +End of script. Logfile hash: cb8ee0bc24, CPU: user 0.06s system 0.00s, MEM: 11.90 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 94% 2x show (0 sec), 1% 1x sat (0 sec), ... ../../yosys -l equiv.log_new equiv.ys @@ -8314,9 +8332,9 @@ \____ $$$|__/|________/|__/|_______/|__/ \__/ -End of script. Logfile hash: 40f4b7a027, CPU: user 0.04s system 0.01s, MEM: 12.00 MB peak +End of script. Logfile hash: 40f4b7a027, CPU: user 0.05s system 0.00s, MEM: 12.10 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 74% 1x sat (0 sec), 15% 1x techmap (0 sec), ... +Time spent: 73% 1x sat (0 sec), 16% 1x techmap (0 sec), ... mv equiv.log_new equiv.log ../../yosys -l axis_test.log_new axis_test.ys @@ -9294,7 +9312,7 @@ init \uut.tdata 64 40 01000000 init \uut.tvalid 1 1 1 -End of script. Logfile hash: 47aa44b032, CPU: user 3.79s system 0.13s, MEM: 125.46 MB peak +End of script. Logfile hash: 47aa44b032, CPU: user 3.80s system 0.11s, MEM: 125.47 MB peak Yosys 0.23 (git sha1 7ce5011c24b) Time spent: 98% 1x sat (3 sec), 0% 3x read_verilog (0 sec), ... mv axis_test.log_new axis_test.log @@ -9342,9 +9360,9 @@ Modules in current design: $abstract\absval_ref (0 wires, 0 cells) -End of script. Logfile hash: a25069ff9d, CPU: user 0.00s system 0.01s, MEM: 11.25 MB peak +End of script. Logfile hash: a25069ff9d, CPU: user 0.01s system 0.00s, MEM: 11.30 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 93% 2x read_verilog (0 sec), 4% 1x my_cmd (0 sec), ... +Time spent: 93% 2x read_verilog (0 sec), 3% 1x my_cmd (0 sec), ... mv test0.log_new test0.log ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v @@ -9390,9 +9408,9 @@ module $abstract\absval_ref end -End of script. Logfile hash: 01cda1039c, CPU: user 0.01s system 0.00s, MEM: 11.47 MB peak +End of script. Logfile hash: 01cda1039c, CPU: user 0.01s system 0.01s, MEM: 11.27 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 73% 1x clean (0 sec), 19% 2x read_verilog (0 sec), ... +Time spent: 70% 1x clean (0 sec), 21% 2x read_verilog (0 sec), ... mv test1.log_new test1.log ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v @@ -9433,9 +9451,9 @@ Log message #8. Log message #9. -End of script. Logfile hash: 8350de3c5a, CPU: user 0.00s system 0.01s, MEM: 11.32 MB peak +End of script. Logfile hash: 8350de3c5a, CPU: user 0.00s system 0.01s, MEM: 11.54 MB peak Yosys 0.23 (git sha1 7ce5011c24b) -Time spent: 50% 2x read_verilog (0 sec), 37% 1x hierarchy (0 sec), ... +Time spent: 53% 2x read_verilog (0 sec), 35% 1x hierarchy (0 sec), ... mv test2.log_new test2.log make[3]: Leaving directory '/build/yosys-0.23/manual/PRESENTATION_Prog' + set -ex @@ -16182,122 +16200,122 @@ + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c + gcc -Wall -g -O2 -ffile-prefix-map=/build/yosys-0.23=. -fstack-protector-strong -Wformat -Werror=format-security -o /build/yosys-0.23/tests/tools/cmp_tbdata /build/yosys-0.23/tests/tools/cmp_tbdata.c Test: case_expr_extend -> ok -Test: local_loop_var -> ok Test: case_expr_query -> ok +Test: local_loop_var -> ok Test: lesser_size_cast -> ok -Test: implicit_ports -> ok Test: arrays02 -> ok Test: matching_end_labels -> ok Test: memwr_port_connection -> ok -Test: defvalue -> ok +Test: implicit_ports -> ok Test: unnamed_block_decl -> ok Test: always01 -> ok +Test: defvalue -> ok Test: always02 -> ok Test: aes_kexp128 -> ok -Test: macro_arg_spaces -> ok Test: always03 -> ok Test: arraycells -> ok -Test: arrays01 -> ok Test: attrib01_module -> ok +Test: macro_arg_spaces -> ok +Test: arrays01 -> ok Test: attrib02_port_decl -> ok -Test: attrib04_net_var -> ok Test: attrib03_parameter -> ok Test: case_expr_const -> ok Test: attrib06_operator_suffix -> ok Test: attrib08_mod_inst -> ok +Test: attrib04_net_var -> ok Test: carryadd -> ok Test: attrib09_case -> ok Test: case_expr_non_const -> ok Test: const_branch_finish -> ok -Test: constpower -> ok Test: const_fold_func -> ok +Test: constpower -> ok Test: const_func_shadow -> ok -Test: fiedler-cooley -> ok Test: dff_init -> ok -Test: asgn_binop -> ok +Test: fiedler-cooley -> ok Test: forgen01 -> ok Test: forgen02 -> ok +Test: asgn_binop -> ok Test: dff_different_styles -> ok Test: forloops -> ok Test: genblk_collide -> ok -Test: func_recurse -> ok Test: fsm -> ok -Test: func_block -> ok -Test: genblk_dive -> ok +Test: func_recurse -> ok Test: genblk_order -> ok Test: genblk_port_shadow -> ok +Test: genblk_dive -> ok +Test: func_block -> ok Test: func_width_scope -> ok -Test: graphtest -> ok Test: hierarchy -> ok -Test: ifdef_2 -> ok +Test: graphtest -> ok Test: ifdef_1 -> ok -Test: hierdefparam -> ok -Test: constmuldivmod -> ok +Test: ifdef_2 -> ok Test: localparam_attr -> ok Test: loop_prefix_case -> ok -Test: i2c_master_tests -> ok +Test: hierdefparam -> ok Test: loop_var_shadow -> ok Test: macro_arg_surrounding_spaces -> ok +Test: i2c_master_tests -> ok +Test: constmuldivmod -> ok Test: macros -> ok -Test: dynslice -> ok Test: mem2reg_bounds_tern -> ok Test: loops -> ok +Test: dynslice -> ok Test: module_scope_case -> ok Test: module_scope -> ok Test: named_genblk -> ok Test: nested_genblk_resolve -> ok -Test: mem_arst -> ok Test: muxtree -> ok -Test: multiplier -> ok +Test: mem_arst -> ok Test: omsp_dbg_uart -> ok -Test: mem2reg -> ok Test: param_attr -> ok +Test: multiplier -> ok +Test: mem2reg -> ok Test: realexpr -> ok Test: paramods -> ok -Test: generate -> ok -Test: process -> ok Test: retime -> ok +Test: process -> ok Test: repwhile -> ok -Test: signed_full_slice -> ok Test: scopes -> ok +Test: signed_full_slice -> ok +Test: generate -> ok Test: signedexpr -> ok Test: specify -> ok Test: string_format -> ok Test: subbytes -> ok Test: undef_eqx_nex -> ok Test: usb_phy_tests -> ok -Test: sincos -> ok Test: task_func -> ok -Test: case_large -> ok Test: verilog_primitives -> ok +Test: sincos -> ok Test: values -> ok Test: wandwor -> ok Test: vloghammer -> ok +Test: case_large -> ok Test: wreduce -> ok -Test: partsel -> ok Test: operators -> ok +Test: partsel -> ok Test: rotate -> ok Test: memory -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/simple' cd tests/simple_abc9 && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/simple_abc9' -Test: always01 -> ok Test: arrays01 -> ok Test: always02 -> ok -Test: attrib01_module -> ok +Test: always01 -> ok Test: always03 -> ok +Test: attrib01_module -> ok Test: aes_kexp128 -> ok Test: arraycells -> ok Test: attrib02_port_decl -> ok -Test: attrib09_case -> ok Test: attrib08_mod_inst -> ok -Test: attrib03_parameter -> ok Test: attrib04_net_var -> ok +Test: attrib09_case -> ok +Test: attrib03_parameter -> ok Test: attrib06_operator_suffix -> ok -Test: case_expr_non_const -> ok -Test: carryadd -> ok Test: case_expr_const -> ok +Test: carryadd -> ok Test: const_branch_finish -> ok +Test: case_expr_non_const -> ok Test: const_fold_func -> ok Test: constpower -> ok Test: dff_init -> ok @@ -16307,54 +16325,54 @@ Test: forgen01 -> ok Test: forgen02 -> ok Test: forloops -> ok -Test: fsm -> ok Test: func_block -> ok +Test: fsm -> ok Test: func_recurse -> ok Test: genblk_collide -> ok Test: genblk_dive -> ok Test: genblk_order -> ok -Test: func_width_scope -> ok Test: genblk_port_shadow -> ok +Test: func_width_scope -> ok Test: graphtest -> ok Test: hierarchy -> ok Test: ifdef_1 -> ok -Test: abc9 -> ok -Test: i2c_master_tests -> ok Test: ifdef_2 -> ok -Test: hierdefparam -> ok +Test: i2c_master_tests -> ok +Test: abc9 -> ok Test: localparam_attr -> ok Test: loop_prefix_case -> ok +Test: hierdefparam -> ok Test: loop_var_shadow -> ok Test: macro_arg_surrounding_spaces -> ok -Test: constmuldivmod -> ok -Test: loops -> ok Test: macros -> ok +Test: loops -> ok Test: mem2reg_bounds_tern -> ok +Test: constmuldivmod -> ok Test: module_scope_case -> ok -Test: module_scope -> ok Test: mem_arst -> ok +Test: module_scope -> ok Test: mem2reg -> ok Test: named_genblk -> ok Test: nested_genblk_resolve -> ok -Test: omsp_dbg_uart -> ok Test: muxtree -> ok -Test: multiplier -> ok +Test: omsp_dbg_uart -> ok Test: param_attr -> ok +Test: multiplier -> ok Test: generate -> ok Test: paramods -> ok Test: process -> ok Test: realexpr -> ok Test: retime -> ok Test: repwhile -> ok -Test: signed_full_slice -> ok Test: scopes -> ok +Test: signed_full_slice -> ok Test: signedexpr -> ok Test: string_format -> ok Test: subbytes -> ok -Test: rotate -> ok -Test: task_func -> ok Test: memory -> ok +Test: task_func -> ok Test: undef_eqx_nex -> ok +Test: rotate -> ok Test: usb_phy_tests -> ok Test: verilog_primitives -> ok Test: values -> ok @@ -16365,17 +16383,17 @@ Test: case_expr_query -> ok Test: defvalue -> ok Test: implicit_ports -> ok -Test: sincos -> ok Test: lesser_size_cast -> ok +Test: sincos -> ok Test: local_loop_var -> ok -Test: asgn_binop -> ok Test: matching_end_labels -> ok -Test: dynslice -> ok +Test: asgn_binop -> ok Test: memwr_port_connection -> ok Test: unnamed_block_decl -> ok Test: wreduce -> ok Test: partsel -> ok Test: macro_arg_spaces -> ok +Test: dynslice -> ok Test: operators -> ok Test: case_large -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/simple_abc9' @@ -16383,56 +16401,56 @@ make[3]: Entering directory '/build/yosys-0.23/tests/hana' Test: test_simulation_buffer -> ok Test: test_parse2synthtrans -> ok -Test: test_parser -> ok Test: test_simulation_and -> ok +Test: test_parser -> ok Test: test_simulation_inc -> ok -Test: test_simulation_seq -> ok Test: test_simulation_nand -> ok -Test: test_simulation_decoder -> ok +Test: test_simulation_seq -> ok Test: test_simulation_nor -> ok +Test: test_simulation_decoder -> ok Test: test_simulation_always -> ok Test: test_simulation_or -> ok Test: test_simulation_vlib -> ok Test: test_simulation_mux -> ok -Test: test_simulation_sop -> ok -Test: test_simulation_xnor -> ok Test: test_simulation_xor -> ok +Test: test_simulation_xnor -> ok +Test: test_simulation_sop -> ok Test: test_simulation_techmap -> ok Test: test_simulation_shifter -> ok -Test: test_intermout -> ok Test: test_simulation_techmap_tech -> ok +Test: test_intermout -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/hana' cd tests/asicworld && bash run-test.sh "" make[3]: Entering directory '/build/yosys-0.23/tests/asicworld' -Test: code_hdl_models_clk_div -> ok Test: code_hdl_models_d_latch_gates -> ok -Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_decoder_2to4_gates -> ok +Test: code_hdl_models_clk_div -> ok +Test: code_hdl_models_d_ff_gates -> ok Test: code_hdl_models_GrayCounter -> ok Test: code_hdl_models_arbiter -> ok Test: code_hdl_models_clk_div_45 -> ok -Test: code_hdl_models_decoder_using_assign -> ok Test: code_hdl_models_dff_async_reset -> ok -Test: code_hdl_models_dff_sync_reset -> ok +Test: code_hdl_models_decoder_using_assign -> ok Test: code_hdl_models_decoder_using_case -> ok +Test: code_hdl_models_dff_sync_reset -> ok Test: code_hdl_models_encoder_4to2_gates -> ok -Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_full_adder_gates -> ok Test: code_hdl_models_full_subtracter_gates -> ok +Test: code_hdl_models_half_adder_gates -> ok Test: code_hdl_models_encoder_using_case -> ok -Test: code_hdl_models_gray_counter -> ok Test: code_hdl_models_lfsr -> ok +Test: code_hdl_models_gray_counter -> ok Test: code_hdl_models_encoder_using_if -> ok Test: code_hdl_models_mux_2to1_gates -> ok +Test: code_hdl_models_lfsr_updown -> ok Test: code_hdl_models_mux_using_assign -> ok -Test: code_hdl_models_mux_using_if -> ok Test: code_hdl_models_mux_using_case -> ok -Test: code_hdl_models_lfsr_updown -> ok +Test: code_hdl_models_mux_using_if -> ok Test: code_hdl_models_one_hot_cnt -> ok Test: code_hdl_models_parity_using_bitwise -> ok Test: code_hdl_models_parity_using_assign -> ok -Test: code_hdl_models_parallel_crc -> ok Test: code_hdl_models_parity_using_function -> ok +Test: code_hdl_models_parallel_crc -> ok Test: code_hdl_models_rom_using_case -> ok Test: code_hdl_models_tff_async_reset -> ok Test: code_hdl_models_serial_crc -> ok @@ -16440,29 +16458,29 @@ Test: code_hdl_models_tff_sync_reset -> ok Test: code_hdl_models_up_counter -> ok Test: code_hdl_models_up_counter_load -> ok -Test: code_tidbits_asyn_reset -> ok Test: code_tidbits_blocking -> ok +Test: code_tidbits_asyn_reset -> ok +Test: code_tidbits_fsm_using_always -> ok Test: code_tidbits_fsm_using_function -> ok -Test: code_tidbits_nonblocking -> ok Test: code_hdl_models_up_down_counter -> ok -Test: code_tidbits_fsm_using_always -> ok -Test: code_specman_switch_fabric -> ok +Test: code_tidbits_nonblocking -> ok Test: code_tidbits_reg_combo_example -> ok -Test: code_tidbits_syn_reset -> ok +Test: code_tidbits_fsm_using_single_always -> ok +Test: code_specman_switch_fabric -> ok Test: code_tidbits_reg_seq_example -> ok +Test: code_tidbits_syn_reset -> ok Test: code_tidbits_wire_example -> ok -Test: code_tidbits_fsm_using_single_always -> ok -Test: code_verilog_tutorial_addbit -> ok Test: code_verilog_tutorial_always_example -> ok Test: code_verilog_tutorial_bus_con -> ok +Test: code_verilog_tutorial_addbit -> ok Test: code_verilog_tutorial_comment -> ok Test: code_verilog_tutorial_d_ff -> ok -Test: code_hdl_models_uart -> ok Test: code_verilog_tutorial_counter -> ok -Test: code_verilog_tutorial_escape_id -> ok Test: code_verilog_tutorial_decoder -> ok -Test: code_verilog_tutorial_first_counter -> ok +Test: code_verilog_tutorial_escape_id -> ok Test: code_verilog_tutorial_decoder_always -> ok +Test: code_verilog_tutorial_first_counter -> ok +Test: code_hdl_models_uart -> ok Test: code_verilog_tutorial_flip_flop -> ok Test: code_verilog_tutorial_explicit -> ok Test: code_verilog_tutorial_multiply -> ok @@ -16470,8 +16488,8 @@ Test: code_verilog_tutorial_good_code -> ok Test: code_verilog_tutorial_n_out_primitive -> ok Test: code_verilog_tutorial_mux_21 -> ok -Test: code_verilog_tutorial_simple_function -> ok Test: code_verilog_tutorial_parallel_if -> ok +Test: code_verilog_tutorial_simple_function -> ok Test: code_verilog_tutorial_simple_if -> ok Test: code_verilog_tutorial_fsm_full -> ok Test: code_verilog_tutorial_task_global -> ok @@ -16494,7 +16512,7 @@ cd tests/fsm && bash run-test.sh "" generating tests.. -PRNG seed: 5805331875371951350 +PRNG seed: 4989710189443309376 running tests.. make[3]: Entering directory '/build/yosys-0.23/tests/fsm' [0][1][2][3][4][5][6][7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: @@ -16512,34 +16530,34 @@ Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -KK[8][9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[10]K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[10]K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[12]K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[14]K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[15]K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[17]K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[19]K[20]K[21]K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[19]K[20]K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: @@ -16548,65 +16566,79 @@ K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[24]K[25]K[26]K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[28]K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[26]K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[28]K[29]K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -KK[30]K[31][32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[34]K[35]K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[34]K[35]K[36]K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[38]K[39]K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[42]K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[44]T[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[43]K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -K[47]K[48]K[49]KKWarning: Regarding the user-specified fsm_encoding attribute on gate.state: +K[47]K[48]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: + Users of state reg look like FSM recoding might result in larger circuit. + Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! +K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: Users of state reg look like FSM recoding might result in larger circuit. Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! -KKKKKK +KKKKKKKK make[3]: Leaving directory '/build/yosys-0.23/tests/fsm' cd tests/techmap && bash run-test.sh make[3]: Entering directory '/build/yosys-0.23/tests/techmap' Warning: wire '\Q' is assigned in a block at < ok -Test: implicit_en -> ok Test: no_implicit_en -> ok -Test: shared_ports -> ok -Test: read_two_mux -> ok +Test: implicit_en -> ok +Test: firrtl_938 -> ok Test: simple_sram_byte_en -> ok +Test: shared_ports -> ok Test: read_arst -> ok Test: amber23_sram_byte_en -> ok +Test: read_two_mux -> ok Test: issue00710 -> ok -Test: issue00335 -> ok Test: trans_addr_enable -> ok -Test: wide_all -> ok -Test: wide_read_async -> ok +Test: issue00335 -> ok Test: trans_sdp -> ok Test: trans_sp -> ok -Test: wide_read_sync -> ok +Test: wide_all -> ok Test: wide_read_mixed -> ok +Test: wide_read_async -> ok Test: wide_thru_priority -> ok +Test: wide_read_sync -> ok Test: wide_read_trans -> ok Test: wide_write -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/memories' @@ -16878,184 +16911,183 @@ Test: t_sync_big -> ok Test: t_sync_big_sdp -> ok Test: t_async_small_block -> ok +Test: t_sync_2clk -> ok Test: t_sync_small_block -> ok Test: t_sync_small_block_attr -> ok -Test: t_sync_2clk -> ok Test: t_tdp -> ok Test: t_sync_shared -> ok Test: t_sync_trans_old_old -> ok Test: t_sync_trans_old_new -> ok Test: t_sync_trans_old_none -> ok +Test: t_sync_trans_new_old -> ok Test: t_sync_2clk_shared -> ok +Test: t_sp_nc_none -> ok Test: t_sync_trans_new_none -> ok Test: t_sync_trans_new_new -> ok -Test: t_sync_trans_new_old -> ok Test: t_sp_new_none -> ok -Test: t_sp_nc_none -> ok -Test: t_sp_nc_nc -> ok Test: t_sp_new_nc -> ok +Test: t_sp_nc_nc -> ok Test: t_sp_old_none -> ok -Test: t_sp_nc_new -> ok Test: t_sp_old_nc -> ok -Test: t_sp_old_new -> ok +Test: t_sp_nc_new -> ok Test: t_sp_new_new -> ok +Test: t_sp_old_new -> ok Test: t_sp_nc_old -> ok Test: t_sp_new_old -> ok Test: t_sp_old_old -> ok -Test: t_sp_new_new_only -> ok Test: t_sp_nc_new_only -> ok -Test: t_sp_old_new_only -> ok +Test: t_sp_new_new_only -> ok Test: t_sp_nc_new_only_be -> ok +Test: t_sp_old_new_only -> ok Test: t_sp_new_new_only_be -> ok -Test: t_sp_nc_new_be -> ok Test: t_sp_old_new_only_be -> ok +Test: t_sp_nc_new_be -> ok Test: t_sp_new_new_be -> ok -Test: t_sp_new_old_be -> ok +Test: t_sp_nc_old_be -> ok Test: t_sp_old_new_be -> ok +Test: t_sp_new_old_be -> ok Test: t_sp_old_old_be -> ok -Test: t_sp_nc_old_be -> ok -Test: t_sp_nc_nc_be -> ok -Test: t_sp_new_auto -> ok -Test: t_sp_old_auto -> ok Test: t_sp_new_nc_be -> ok +Test: t_sp_nc_nc_be -> ok Test: t_sp_old_nc_be -> ok Test: t_sp_nc_auto -> ok -Test: t_async_big -> ok -Test: t_sp_old_auto_be -> ok +Test: t_sp_new_auto -> ok +Test: t_sp_old_auto -> ok Test: t_sp_nc_auto_be -> ok Test: t_sp_new_auto_be -> ok Test: t_sp_init_x_x -> ok -Test: t_sync_big_lut -> ok +Test: t_sp_old_auto_be -> ok Test: t_sp_init_x_x_re -> ok -Test: t_sp_init_0_x_re -> ok Test: t_sp_init_x_x_ce -> ok Test: t_sp_init_0_x -> ok -Test: t_sp_init_0_0_re -> ok +Test: t_sp_init_0_any -> ok +Test: t_sp_init_0_x_re -> ok Test: t_sp_init_0_0 -> ok +Test: t_sp_init_0_0_re -> ok Test: t_sp_init_0_any_re -> ok -Test: t_sp_init_v_x -> ok -Test: t_sp_init_0_any -> ok Test: t_sp_init_v_x_re -> ok +Test: t_sp_init_v_x -> ok Test: t_sp_init_v_0 -> ok -Test: t_sp_init_v_any -> ok Test: t_sp_init_v_0_re -> ok +Test: t_sp_init_v_any -> ok Test: t_sp_arst_x_x -> ok Test: t_sp_init_v_any_re -> ok Test: t_sp_arst_x_x_re -> ok -Test: t_sp_arst_0_x_re -> ok Test: t_sp_arst_0_x -> ok -Test: t_sp_arst_0_init -> ok -Test: t_sp_arst_0_any_re -> ok +Test: t_sp_arst_0_x_re -> ok Test: t_sp_arst_0_0 -> ok -Test: t_sp_arst_0_any -> ok Test: t_sp_arst_0_0_re -> ok -Test: t_sp_arst_0_init_re -> ok +Test: t_sp_arst_0_any -> ok +Test: t_sp_arst_0_any_re -> ok +Test: t_sp_arst_0_init -> ok Test: t_sp_arst_v_x -> ok +Test: t_sp_arst_0_init_re -> ok Test: t_sp_arst_v_x_re -> ok -Test: t_sp_arst_v_any_re -> ok +Test: t_sync_big_lut -> ok +Test: t_sp_arst_v_0 -> ok +Test: t_async_big -> ok Test: t_sp_arst_v_0_re -> ok -Test: t_sp_arst_v_init -> ok Test: t_sp_arst_v_any -> ok -Test: t_sp_arst_v_0 -> ok +Test: t_sp_arst_v_any_re -> ok Test: t_sp_arst_v_init_re -> ok -Test: t_sp_arst_e_0_re -> ok -Test: t_sp_arst_e_any -> ok +Test: t_sp_arst_v_init -> ok Test: t_sp_arst_e_x -> ok -Test: t_sp_arst_e_any_re -> ok -Test: t_sp_arst_e_0 -> ok Test: t_sp_arst_e_x_re -> ok +Test: t_sp_arst_e_0 -> ok +Test: t_sp_arst_e_0_re -> ok Test: t_sp_arst_e_init -> ok -Test: t_sp_arst_n_x -> ok +Test: t_sp_arst_e_any -> ok +Test: t_sp_arst_e_any_re -> ok Test: t_sp_arst_e_init_re -> ok -Test: t_sp_arst_n_0_re -> ok +Test: t_sp_arst_n_x -> ok Test: t_sp_arst_n_x_re -> ok Test: t_sp_arst_n_0 -> ok Test: t_sp_arst_n_any -> ok +Test: t_sp_arst_n_0_re -> ok Test: t_sp_arst_n_any_re -> ok Test: t_sp_arst_n_init -> ok -Test: t_sp_srst_x_x -> ok Test: t_sp_arst_n_init_re -> ok Test: t_sp_srst_x_x_re -> ok +Test: t_sp_srst_x_x -> ok Test: t_sp_srst_0_x -> ok -Test: t_sp_srst_0_x_re -> ok Test: t_sp_srst_0_0 -> ok Test: t_sp_srst_0_0_re -> ok -Test: t_sp_srst_0_any_re -> ok -Test: t_sp_srst_0_any -> ok +Test: t_sp_srst_0_x_re -> ok Test: t_sp_srst_0_init -> ok +Test: t_sp_srst_0_any -> ok +Test: t_sp_srst_0_any_re -> ok Test: t_sp_srst_0_init_re -> ok -Test: t_sp_srst_v_x -> ok -Test: t_sp_srst_v_x_re -> ok Test: t_sp_srst_v_0 -> ok +Test: t_sp_srst_v_x_re -> ok +Test: t_sp_srst_v_x -> ok Test: t_sp_srst_v_0_re -> ok +Test: t_sp_srst_v_any_re -> ok Test: t_sp_srst_v_any -> ok -Test: t_sp_srst_v_any_ce -> ok Test: t_sp_srst_v_any_re_gated -> ok -Test: t_sp_srst_v_any_re -> ok Test: t_sp_srst_v_any_ce_gated -> ok -Test: t_sp_srst_e_x -> ok +Test: t_sp_srst_v_any_ce -> ok +Test: t_sp_srst_v_init -> ok Test: t_sp_srst_v_init_re -> ok -Test: t_sp_srst_e_0_re -> ok Test: t_sp_srst_e_x_re -> ok +Test: t_sp_srst_e_x -> ok Test: t_sp_srst_e_0 -> ok -Test: t_sp_srst_v_init -> ok +Test: t_sp_srst_e_0_re -> ok Test: t_sp_srst_e_any -> ok -Test: t_sp_srst_n_x -> ok -Test: t_sp_srst_e_init_re -> ok Test: t_sp_srst_e_any_re -> ok -Test: t_sp_srst_n_x_re -> ok Test: t_sp_srst_e_init -> ok -Test: t_sp_srst_n_0 -> ok +Test: t_sp_srst_e_init_re -> ok +Test: t_sp_srst_n_x -> ok +Test: t_sp_srst_n_x_re -> ok Test: t_sp_srst_n_0_re -> ok +Test: t_sp_srst_n_0 -> ok Test: t_sp_srst_n_any -> ok +Test: t_sp_srst_n_any_re -> ok Test: t_sp_srst_n_init -> ok +Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_gv_x -> ok -Test: t_sp_srst_n_any_re -> ok Test: t_sp_srst_gv_x_re -> ok -Test: t_sp_srst_n_init_re -> ok Test: t_sp_srst_gv_0 -> ok Test: t_sp_srst_gv_0_re -> ok -Test: t_sp_srst_gv_any_ce -> ok -Test: t_sp_srst_gv_any_re -> ok Test: t_sp_srst_gv_any -> ok +Test: t_sp_srst_gv_any_re -> ok Test: t_sp_srst_gv_any_re_gated -> ok +Test: t_sp_srst_gv_any_ce -> ok Test: t_sp_srst_gv_init -> ok -Test: t_sp_srst_gv_any_ce_gated -> ok Test: t_sp_srst_gv_init_re -> ok -Test: t_wide_sdp_a7r1w1b1x1 -> ok -Test: t_wide_sdp_a6r1w0b0x0 -> ok +Test: t_sp_srst_gv_any_ce_gated -> ok +Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_wide_sdp_a8r1w1b1x1 -> ok -Test: t_wide_sdp_a6r2w0b0x0 -> ok +Test: t_wide_sdp_a7r1w1b1x1 -> ok Test: t_wide_sdp_a6r0w0b0x0 -> ok -Test: t_wide_sdp_a6r1w1b1x1 -> ok Test: t_wide_sdp_a6r3w0b0x0 -> ok +Test: t_wide_sdp_a6r1w0b0x0 -> ok +Test: t_wide_sdp_a6r2w0b0x0 -> ok Test: t_wide_sdp_a6r4w0b0x0 -> ok -Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b0x0 -> ok +Test: t_wide_sdp_a6r5w0b0x0 -> ok Test: t_wide_sdp_a6r0w1b1x0 -> ok -Test: t_wide_sdp_a6r0w2b0x0 -> ok Test: t_wide_sdp_a6r0w2b2x0 -> ok -Test: t_async_big_block -> ok +Test: t_wide_sdp_a6r0w2b0x0 -> ok Test: t_wide_sdp_a6r0w3b2x0 -> ok -Test: t_wide_sdp_a6r0w4b2x0 -> ok -Test: t_wide_sdp_a7r2w0b0x0 -> ok -Test: t_wide_sdp_a7r1w0b0x0 -> ok Test: t_wide_sdp_a7r0w0b0x0 -> ok +Test: t_wide_sdp_a7r1w0b0x0 -> ok +Test: t_wide_sdp_a7r2w0b0x0 -> ok +Test: t_wide_sdp_a6r0w4b2x0 -> ok Test: t_wide_sdp_a7r3w0b0x0 -> ok Test: t_wide_sdp_a6r0w5b2x0 -> ok Test: t_wide_sdp_a7r4w0b0x0 -> ok Test: t_wide_sdp_a7r0w1b0x0 -> ok +Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_wide_sdp_a7r0w1b1x0 -> ok Test: t_wide_sdp_a7r5w0b0x0 -> ok Test: t_wide_sdp_a7r0w2b2x0 -> ok -Test: t_wide_sdp_a7r0w2b0x0 -> ok Test: t_wide_sdp_a7r0w3b2x0 -> ok -Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r1w1b1 -> ok Test: t_wide_sp_mix_a7r1w1b1 -> ok -Test: t_wide_sdp_a7r0w5b2x0 -> ok -Test: t_wide_sp_mix_a8r1w1b1 -> ok +Test: t_wide_sdp_a7r0w4b2x0 -> ok Test: t_wide_sp_mix_a6r0w0b0 -> ok +Test: t_wide_sp_mix_a8r1w1b1 -> ok +Test: t_wide_sdp_a7r0w5b2x0 -> ok Test: t_wide_sp_mix_a6r1w0b0 -> ok Test: t_wide_sp_mix_a6r2w0b0 -> ok Test: t_wide_sp_mix_a6r3w0b0 -> ok @@ -17063,115 +17095,116 @@ Test: t_wide_sp_mix_a6r0w1b0 -> ok Test: t_wide_sp_mix_a6r0w1b1 -> ok Test: t_wide_sp_mix_a6r5w0b0 -> ok -Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sp_mix_a6r0w2b2 -> ok +Test: t_wide_sp_mix_a6r0w2b0 -> ok Test: t_wide_sp_mix_a6r0w3b2 -> ok -Test: t_wide_sp_mix_a7r0w0b0 -> ok -Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a6r0w4b2 -> ok +Test: t_wide_sp_mix_a7r1w0b0 -> ok Test: t_wide_sp_mix_a7r2w0b0 -> ok +Test: t_wide_sp_mix_a7r0w0b0 -> ok +Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a7r4w0b0 -> ok Test: t_wide_sp_mix_a6r0w5b2 -> ok -Test: t_wide_sp_mix_a7r3w0b0 -> ok Test: t_wide_sp_mix_a7r0w1b0 -> ok Test: t_wide_sp_mix_a7r0w1b1 -> ok -Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w2b0 -> ok Test: t_wide_sp_mix_a7r0w2b2 -> ok +Test: t_wide_sp_mix_a7r5w0b0 -> ok Test: t_wide_sp_mix_a7r0w3b2 -> ok -Test: t_wide_sp_mix_a7r0w4b2 -> ok -Test: t_wide_sp_tied_a6r0w0b0 -> ok -Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_tied_a7r1w1b1 -> ok Test: t_wide_sp_tied_a6r1w1b1 -> ok -Test: t_wide_sp_mix_a7r0w5b2 -> ok +Test: t_wide_sp_mix_a7r0w4b2 -> ok +Test: t_wide_sp_tied_a6r0w0b0 -> ok Test: t_wide_sp_tied_a8r1w1b1 -> ok +Test: t_wide_sp_mix_a7r0w5b2 -> ok +Test: t_wide_sp_tied_a6r1w0b0 -> ok Test: t_wide_sp_tied_a6r2w0b0 -> ok Test: t_wide_sp_tied_a6r3w0b0 -> ok Test: t_wide_sp_tied_a6r4w0b0 -> ok Test: t_wide_sp_tied_a6r0w1b0 -> ok -Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w2b2 -> ok +Test: t_wide_sp_tied_a6r0w1b1 -> ok Test: t_wide_sp_tied_a6r0w2b0 -> ok Test: t_wide_sp_tied_a6r5w0b0 -> ok Test: t_wide_sp_tied_a6r0w3b2 -> ok -Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a7r1w0b0 -> ok +Test: t_wide_sp_tied_a7r0w0b0 -> ok Test: t_wide_sp_tied_a6r0w4b2 -> ok Test: t_wide_sp_tied_a7r2w0b0 -> ok -Test: t_wide_sp_tied_a6r0w5b2 -> ok +Test: t_async_big_block -> ok Test: t_wide_sp_tied_a7r3w0b0 -> ok -Test: t_wide_sp_tied_a7r4w0b0 -> ok +Test: t_wide_sp_tied_a6r0w5b2 -> ok Test: t_wide_sp_tied_a7r0w1b0 -> ok Test: t_wide_sp_tied_a7r0w1b1 -> ok +Test: t_wide_sp_tied_a7r4w0b0 -> ok Test: t_wide_sp_tied_a7r0w2b0 -> ok Test: t_wide_sp_tied_a7r5w0b0 -> ok Test: t_wide_sp_tied_a7r0w2b2 -> ok -Test: t_wide_sp_tied_a7r0w3b2 -> ok -Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_read_a6r1w1b1 -> ok +Test: t_wide_sp_tied_a7r0w3b2 -> ok Test: t_wide_write_a6r1w1b1 -> ok +Test: t_wide_sp_tied_a7r0w4b2 -> ok Test: t_wide_write_a7r1w1b1 -> ok +Test: t_wide_read_a7r1w1b1 -> ok Test: t_wide_read_a8r1w1b1 -> ok Test: t_wide_sp_tied_a7r0w5b2 -> ok -Test: t_wide_read_a7r1w1b1 -> ok -Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_read_a6r0w0b0 -> ok +Test: t_wide_write_a8r1w1b1 -> ok Test: t_wide_write_a6r0w0b0 -> ok Test: t_wide_read_a6r1w0b0 -> ok Test: t_wide_read_a6r2w0b0 -> ok -Test: t_wide_read_a6r3w0b0 -> ok -Test: t_wide_write_a6r1w0b0 -> ok Test: t_wide_write_a6r2w0b0 -> ok +Test: t_wide_write_a6r1w0b0 -> ok +Test: t_wide_read_a6r3w0b0 -> ok Test: t_wide_write_a6r3w0b0 -> ok Test: t_wide_read_a6r4w0b0 -> ok +Test: t_wide_write_a6r0w1b0 -> ok Test: t_wide_write_a6r4w0b0 -> ok -Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_read_a6r0w1b0 -> ok -Test: t_wide_write_a6r0w1b0 -> ok +Test: t_wide_read_a6r0w1b1 -> ok Test: t_wide_read_a6r5w0b0 -> ok -Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_write_a6r0w1b1 -> ok -Test: t_wide_write_a6r0w2b0 -> ok +Test: t_wide_write_a6r5w0b0 -> ok Test: t_wide_read_a6r0w2b0 -> ok +Test: t_wide_write_a6r0w2b0 -> ok Test: t_wide_write_a6r0w2b2 -> ok -Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_read_a6r0w2b2 -> ok +Test: t_wide_read_a6r0w3b2 -> ok Test: t_wide_write_a6r0w3b2 -> ok -Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_read_a6r0w4b2 -> ok -Test: t_wide_read_a7r0w0b0 -> ok Test: t_wide_write_a7r0w0b0 -> ok +Test: t_wide_read_a7r1w0b0 -> ok +Test: t_wide_read_a7r0w0b0 -> ok +Test: t_wide_write_a6r0w4b2 -> ok Test: t_wide_write_a7r1w0b0 -> ok +Test: t_wide_read_a7r2w0b0 -> ok Test: t_wide_write_a6r0w5b2 -> ok -Test: t_wide_read_a7r1w0b0 -> ok Test: t_wide_read_a6r0w5b2 -> ok -Test: t_wide_read_a7r2w0b0 -> ok -Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_read_a7r3w0b0 -> ok -Test: t_wide_read_a7r4w0b0 -> ok +Test: t_wide_write_a7r2w0b0 -> ok Test: t_wide_write_a7r3w0b0 -> ok +Test: t_wide_read_a7r4w0b0 -> ok Test: t_wide_write_a7r4w0b0 -> ok -Test: t_wide_read_a7r5w0b0 -> ok +Test: t_wide_read_a7r0w1b1 -> ok Test: t_wide_read_a7r0w1b0 -> ok -Test: t_wide_read_a7r0w2b0 -> ok -Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_write_a7r0w1b0 -> ok Test: t_wide_write_a7r0w1b1 -> ok -Test: t_wide_read_a7r0w1b1 -> ok +Test: t_wide_read_a7r5w0b0 -> ok +Test: t_wide_read_a7r0w2b0 -> ok Test: t_wide_write_a7r0w2b0 -> ok +Test: t_wide_write_a7r5w0b0 -> ok Test: t_wide_read_a7r0w2b2 -> ok Test: t_wide_write_a7r0w2b2 -> ok -Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_read_a7r0w3b2 -> ok -Test: t_wide_read_a7r0w4b2 -> ok +Test: t_wide_write_a7r0w3b2 -> ok Test: t_wide_write_a7r0w4b2 -> ok +Test: t_wide_read_a7r0w4b2 -> ok Test: t_wide_write_a7r0w5b2 -> ok Test: t_wide_read_a7r0w5b2 -> ok make[3]: Leaving directory '/build/yosys-0.23/tests/memlib' cd tests/bram && bash run-test.sh "" generating tests.. -PRNG seed: 769350 +PRNG seed: 775341 running tests.. make[3]: Entering directory '/build/yosys-0.23/tests/bram' ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. @@ -17184,16 +17217,19 @@ ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 01_03. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 01_02. +Passed memory_bram test 00_04. +Passed memory_bram test 00_03. +../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. +../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. +Passed memory_bram test 01_03. Passed memory_bram test 00_02. -Passed memory_bram test 01_04. +Passed memory_bram test 00_01. Passed memory_bram test 01_00. +Passed memory_bram test 01_02. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 00_03. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. @@ -17205,40 +17241,37 @@ ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 02_01. Passed memory_bram test 03_00. -Passed memory_bram test 00_01. +Passed memory_bram test 01_04. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. +Passed memory_bram test 02_04. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 03_01. +Passed memory_bram test 03_04. Passed memory_bram test 03_02. +Passed memory_bram test 04_00. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 03_04. -Passed memory_bram test 04_01. +Passed memory_bram test 03_01. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 00_04. -Passed memory_bram test 04_00. +Passed memory_bram test 04_03. +Passed memory_bram test 04_01. ../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. ../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. Passed memory_bram test 02_03. -../../techlibs/common/simlib.v:1373: warning: Port 1 (A) of $bmux expects 1 bits, got 32. -../../techlibs/common/simlib.v:1373: : Pruning (signed) 31 high bits of the expression. -Passed memory_bram test 04_03. Passed memory_bram test 04_02. -Passed memory_bram test 02_04. make[3]: Leaving directory '/build/yosys-0.23/tests/bram' cd tests/various && bash run-test.sh make[3]: Entering directory '/build/yosys-0.23/tests/various' -Passed aiger_dff.ys Passed attrib05_port_conn.ys +Passed aiger_dff.ys Passed attrib07_func_call.ys Passed autoname.ys Passed blackbox_wb.ys @@ -17249,13 +17282,15 @@ Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!! Passed bug1710.ys Passed bug1745.ys +Passed bug1781.ys Passed bug1876.ys -Passed bug3462.ys -Passed bug2014.ys < ok @@ -17527,19 +17560,19 @@ make[3]: Entering directory '/build/yosys-0.23/tests/svtypes' <