{"diffoscope-json-version": 1, "source1": "/srv/reproducible-results/rbuild-debian/r-b-build.SqtPYgBk/b1/libgridxc_2.0.1-1_armhf.changes", "source2": "/srv/reproducible-results/rbuild-debian/r-b-build.SqtPYgBk/b2/libgridxc_2.0.1-1_armhf.changes", "unified_diff": null, "details": [{"source1": "Files", "source2": "Files", "unified_diff": "@@ -1,2 +1,2 @@\n \n- a88229856617eab8b0178b1fcc1461d6 288400 libdevel optional libgridxc-dev_2.0.1-1_armhf.deb\n+ c38bf46211275a40e46a06006635d56e 283268 libdevel optional libgridxc-dev_2.0.1-1_armhf.deb\n"}, {"source1": "libgridxc-dev_2.0.1-1_armhf.deb", "source2": "libgridxc-dev_2.0.1-1_armhf.deb", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,3 +1,3 @@\n -rw-r--r-- 0 0 0 4 2023-12-29 18:51:33.000000 debian-binary\n--rw-r--r-- 0 0 0 1828 2023-12-29 18:51:33.000000 control.tar.xz\n--rw-r--r-- 0 0 0 286380 2023-12-29 18:51:33.000000 data.tar.xz\n+-rw-r--r-- 0 0 0 1824 2023-12-29 18:51:33.000000 control.tar.xz\n+-rw-r--r-- 0 0 0 281252 2023-12-29 18:51:33.000000 data.tar.xz\n"}, {"source1": "control.tar.xz", "source2": "control.tar.xz", "unified_diff": null, "details": [{"source1": "control.tar", "source2": "control.tar", "unified_diff": null, "details": [{"source1": "./control", "source2": "./control", "unified_diff": "@@ -1,13 +1,13 @@\n Package: libgridxc-dev\n Source: libgridxc\n Version: 2.0.1-1\n Architecture: armhf\n Maintainer: Debichem Team \n-Installed-Size: 633\n+Installed-Size: 638\n Section: libdevel\n Priority: optional\n Homepage: https://gitlab.com/siesta-project/libraries/libgridxc\n Description: Library to compute exchange/correlation energies (development files)\n libGridXC is a library for the computation of exchange and correlation\n energies and potentials in radial and 3D grids.\n .\n"}, {"source1": "./md5sums", "source2": "./md5sums", "unified_diff": null, "details": [{"source1": "./md5sums", "source2": "./md5sums", "comments": ["Files differ"], "unified_diff": null}]}]}]}, {"source1": "data.tar.xz", "source2": "data.tar.xz", "unified_diff": null, "details": [{"source1": "data.tar", "source2": "data.tar", "unified_diff": null, "details": [{"source1": "file list", "source2": "file list", "unified_diff": "@@ -41,15 +41,15 @@\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/libgridxc/\n -rw-r--r-- 0 root (0) root (0) 1861 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/libgridxc/libgridxc-config-version.cmake\n -rw-r--r-- 0 root (0) root (0) 1412 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/libgridxc/libgridxc-config.cmake\n -rw-r--r-- 0 root (0) root (0) 972 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/libgridxc/libgridxc-targets-relwithdebinfo.cmake\n -rw-r--r-- 0 root (0) root (0) 4954 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/cmake/libgridxc/libgridxc-targets.cmake\n--rw-r--r-- 0 root (0) root (0) 538892 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/libgridxc.a\n+-rw-r--r-- 0 root (0) root (0) 544692 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/libgridxc.a\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/pkgconfig/\n -rw-r--r-- 0 root (0) root (0) 251 2023-12-29 18:51:33.000000 ./usr/lib/arm-linux-gnueabihf/pkgconfig/libgridxc.pc\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/share/\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/share/doc/\n drwxr-xr-x 0 root (0) root (0) 0 2023-12-29 18:51:33.000000 ./usr/share/doc/libgridxc-dev/\n -rw-r--r-- 0 root (0) root (0) 193 2023-12-29 18:51:33.000000 ./usr/share/doc/libgridxc-dev/changelog.Debian.gz\n -rw-r--r-- 0 root (0) root (0) 3351 2023-12-13 08:26:16.000000 ./usr/share/doc/libgridxc-dev/changelog.gz\n"}, {"source1": "./usr/lib/arm-linux-gnueabihf/libgridxc.a", "source2": "./usr/lib/arm-linux-gnueabihf/libgridxc.a", "unified_diff": null, "details": [{"source1": "nm -s {}", "source2": "nm -s {}", "comments": ["error from `nm -s {}`:", "nm: gridxc.F90.o: no symbols", "nm: precision.F90.o: no symbols"], "unified_diff": "@@ -336,72 +336,74 @@\n 000001a8 r .LC29\n 000001ac r .LC30\n 00000068 r .LC4\n 0000007c r .LC5\n 0000008c r .LC7\n 000000a4 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n+ U __aeabi_idiv\n+ U __aeabi_uidiv\n 00000000 T __gridxc_alloc_MOD___copy_gridxc_alloc_Allocdefaults\n 00000018 R __gridxc_alloc_MOD___def_init_gridxc_alloc_Allocdefaults\n 00000000 D __gridxc_alloc_MOD___vtab_gridxc_alloc_Allocdefaults\n-00000eb8 t __gridxc_alloc_MOD_alloc_count.constprop.0\n-00009830 T __gridxc_alloc_MOD_alloc_default\n-000009c4 t __gridxc_alloc_MOD_alloc_err.constprop.1\n+00000e50 t __gridxc_alloc_MOD_alloc_count.constprop.0\n+00009098 T __gridxc_alloc_MOD_alloc_default\n+0000098c t __gridxc_alloc_MOD_alloc_err.constprop.1\n 00000000 D __gridxc_alloc_MOD_alloc_error_report\n 00000004 D __gridxc_alloc_MOD_alloc_memory_event\n 00000000 B __gridxc_alloc_MOD_associated_array\n-00001a7c T __gridxc_alloc_MOD_dealloc_d1\n-000019a0 T __gridxc_alloc_MOD_dealloc_d2\n-000018b8 T __gridxc_alloc_MOD_dealloc_d3\n-000017c0 T __gridxc_alloc_MOD_dealloc_d4\n-00001ec8 T __gridxc_alloc_MOD_dealloc_e1\n-00002154 T __gridxc_alloc_MOD_dealloc_i1\n-00002078 T __gridxc_alloc_MOD_dealloc_i2\n-00001f90 T __gridxc_alloc_MOD_dealloc_i3\n-00001550 T __gridxc_alloc_MOD_dealloc_l1\n-00001474 T __gridxc_alloc_MOD_dealloc_l2\n-0000138c T __gridxc_alloc_MOD_dealloc_l3\n-00001e00 T __gridxc_alloc_MOD_dealloc_r1\n-00001d24 T __gridxc_alloc_MOD_dealloc_r2\n-00001c3c T __gridxc_alloc_MOD_dealloc_r3\n-00001b44 T __gridxc_alloc_MOD_dealloc_r4\n-000012a0 T __gridxc_alloc_MOD_dealloc_s1\n-000016f4 T __gridxc_alloc_MOD_dealloc_z1\n-00001618 T __gridxc_alloc_MOD_dealloc_z2\n+00001a18 T __gridxc_alloc_MOD_dealloc_d1\n+00001940 T __gridxc_alloc_MOD_dealloc_d2\n+00001858 T __gridxc_alloc_MOD_dealloc_d3\n+00001760 T __gridxc_alloc_MOD_dealloc_d4\n+00001e60 T __gridxc_alloc_MOD_dealloc_e1\n+000020e8 T __gridxc_alloc_MOD_dealloc_i1\n+00002010 T __gridxc_alloc_MOD_dealloc_i2\n+00001f28 T __gridxc_alloc_MOD_dealloc_i3\n+000014f4 T __gridxc_alloc_MOD_dealloc_l1\n+0000141c T __gridxc_alloc_MOD_dealloc_l2\n+00001334 T __gridxc_alloc_MOD_dealloc_l3\n+00001d98 T __gridxc_alloc_MOD_dealloc_r1\n+00001cc0 T __gridxc_alloc_MOD_dealloc_r2\n+00001bd8 T __gridxc_alloc_MOD_dealloc_r3\n+00001ae0 T __gridxc_alloc_MOD_dealloc_r4\n+00001248 T __gridxc_alloc_MOD_dealloc_s1\n+00001694 T __gridxc_alloc_MOD_dealloc_z1\n+000015bc T __gridxc_alloc_MOD_dealloc_z2\n 00000000 D __gridxc_alloc_MOD_default\n 00000028 t __gridxc_alloc_MOD_dummy_alloc_error_report\n 00000024 t __gridxc_alloc_MOD_dummy_alloc_memory_event\n 00000010 B __gridxc_alloc_MOD_ierr\n 00000004 B __gridxc_alloc_MOD_needs_alloc\n 0000000c B __gridxc_alloc_MOD_needs_copy\n 00000008 B __gridxc_alloc_MOD_needs_dealloc\n-000000f4 t __gridxc_alloc_MOD_options.constprop.0\n-000001fc t __gridxc_alloc_MOD_options.constprop.1\n+000000ec t __gridxc_alloc_MOD_options.constprop.0\n+000001ec t __gridxc_alloc_MOD_options.constprop.1\n 000003cc t __gridxc_alloc_MOD_options.constprop.2\n-00000644 t __gridxc_alloc_MOD_options.constprop.3\n-00005c5c T __gridxc_alloc_MOD_realloc_d1\n-000056f0 T __gridxc_alloc_MOD_realloc_d2\n-00005028 T __gridxc_alloc_MOD_realloc_d3\n-00004648 T __gridxc_alloc_MOD_realloc_d4\n-00007f48 T __gridxc_alloc_MOD_realloc_e1\n-00009314 T __gridxc_alloc_MOD_realloc_i1\n-00008c70 T __gridxc_alloc_MOD_realloc_i2\n-00008460 T __gridxc_alloc_MOD_realloc_i3\n-00003674 T __gridxc_alloc_MOD_realloc_l1\n-00002fb0 T __gridxc_alloc_MOD_realloc_l2\n-00002780 T __gridxc_alloc_MOD_realloc_l3\n-00007a34 T __gridxc_alloc_MOD_realloc_r1\n-00007370 T __gridxc_alloc_MOD_realloc_r2\n-00006b40 T __gridxc_alloc_MOD_realloc_r3\n-00006170 T __gridxc_alloc_MOD_realloc_r4\n-0000221c T __gridxc_alloc_MOD_realloc_s1\n-00004114 T __gridxc_alloc_MOD_realloc_z1\n-00003b90 T __gridxc_alloc_MOD_realloc_z2\n-00009a30 T __gridxc_alloc_MOD_set_alloc_error_handler\n-00009a3c T __gridxc_alloc_MOD_set_alloc_event_handler\n+00000618 t __gridxc_alloc_MOD_options.constprop.3\n+00005868 T __gridxc_alloc_MOD_realloc_d1\n+00005358 T __gridxc_alloc_MOD_realloc_d2\n+00004ce4 T __gridxc_alloc_MOD_realloc_d3\n+00004350 T __gridxc_alloc_MOD_realloc_d4\n+00007958 T __gridxc_alloc_MOD_realloc_e1\n+00008c08 T __gridxc_alloc_MOD_realloc_i1\n+000085c8 T __gridxc_alloc_MOD_realloc_i2\n+00007dec T __gridxc_alloc_MOD_realloc_i3\n+000034f4 T __gridxc_alloc_MOD_realloc_l1\n+00002e94 T __gridxc_alloc_MOD_realloc_l2\n+000026b0 T __gridxc_alloc_MOD_realloc_l3\n+000074cc T __gridxc_alloc_MOD_realloc_r1\n+00006e6c T __gridxc_alloc_MOD_realloc_r2\n+00006688 T __gridxc_alloc_MOD_realloc_r3\n+00005cf8 T __gridxc_alloc_MOD_realloc_r4\n+000021b0 T __gridxc_alloc_MOD_realloc_s1\n+00003ea4 T __gridxc_alloc_MOD_realloc_z1\n+00003984 T __gridxc_alloc_MOD_realloc_z2\n+0000929c T __gridxc_alloc_MOD_set_alloc_error_handler\n+000092a8 T __gridxc_alloc_MOD_set_alloc_event_handler\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_compare_string\n U _gfortran_concat_string\n U _gfortran_st_write\n U _gfortran_st_write_done\n U _gfortran_stop_string\n@@ -414,23 +416,23 @@\n U memcpy\n U memmove\n U memset\n \n am05.F90.o:\n 00000000 r .LC0\n U _GLOBAL_OFFSET_TABLE_\n-00000978 T __gridxc_am05_MOD_am05_xscss\n-00000978 t __gridxc_am05_MOD_am05_xscss.localalias\n+00000990 T __gridxc_am05_MOD_am05_xscss\n+00000990 t __gridxc_am05_MOD_am05_xscss.localalias\n 00000000 T __gridxc_am05_MOD_am05_xscss_lambertw\n 00000000 t __gridxc_am05_MOD_am05_xscss_lambertw.localalias\n 00000470 T __gridxc_am05_MOD_am05_xscss_ldapwc\n 00000470 t __gridxc_am05_MOD_am05_xscss_ldapwc.localalias\n-00000938 T __gridxc_am05_MOD_am05_xscss_ldax\n-000012b0 T __gridxc_am05_MOD_am05wbs\n-00001474 T __gridxc_am05_MOD_saferecp\n+00000950 T __gridxc_am05_MOD_am05_xscss_ldax\n+00001420 T __gridxc_am05_MOD_am05wbs\n+000015ec T __gridxc_am05_MOD_saferecp\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n U cbrt\n U exp\n U log\n \n@@ -492,47 +494,47 @@\n 000005c0 r .LC58\n 000005dc r .LC59\n 00000088 r .LC6\n 000000a0 r .LC7\n 000000b4 r .LC8\n 000000cc r .LC9\n U _GLOBAL_OFFSET_TABLE_\n-00001f28 T __gridxc_array_MOD_aa_1d_2d_dp\n-00002168 T __gridxc_array_MOD_aa_1d_2d_ip\n-00002048 T __gridxc_array_MOD_aa_1d_2d_sp\n-00001aa8 T __gridxc_array_MOD_aa_1d_3d_dp\n-00001d98 T __gridxc_array_MOD_aa_1d_3d_ip\n-00001c20 T __gridxc_array_MOD_aa_1d_3d_sp\n-00001550 T __gridxc_array_MOD_aa_1d_4d_dp\n-000018d8 T __gridxc_array_MOD_aa_1d_4d_ip\n-00001714 T __gridxc_array_MOD_aa_1d_4d_sp\n-00001048 T __gridxc_array_MOD_aa_2d_1d_dp\n-0000137c T __gridxc_array_MOD_aa_2d_1d_ip\n-00001194 T __gridxc_array_MOD_aa_2d_1d_sp\n-00000900 T __gridxc_array_MOD_aa_3d_1d_dp\n-00000da0 T __gridxc_array_MOD_aa_3d_1d_ip\n-00000ae4 T __gridxc_array_MOD_aa_3d_1d_sp\n+00001aa0 T __gridxc_array_MOD_aa_1d_2d_dp\n+00001ce8 T __gridxc_array_MOD_aa_1d_2d_ip\n+00001bc4 T __gridxc_array_MOD_aa_1d_2d_sp\n+00001614 T __gridxc_array_MOD_aa_1d_3d_dp\n+0000190c T __gridxc_array_MOD_aa_1d_3d_ip\n+00001790 T __gridxc_array_MOD_aa_1d_3d_sp\n+000010b4 T __gridxc_array_MOD_aa_1d_4d_dp\n+00001444 T __gridxc_array_MOD_aa_1d_4d_ip\n+0000127c T __gridxc_array_MOD_aa_1d_4d_sp\n+00000ccc T __gridxc_array_MOD_aa_2d_1d_dp\n+00000f64 T __gridxc_array_MOD_aa_2d_1d_ip\n+00000e18 T __gridxc_array_MOD_aa_2d_1d_sp\n+0000071c T __gridxc_array_MOD_aa_3d_1d_dp\n+00000aec T __gridxc_array_MOD_aa_3d_1d_ip\n+00000904 T __gridxc_array_MOD_aa_3d_1d_sp\n 00000000 T __gridxc_array_MOD_aa_4d_1d_dp\n-000005b0 T __gridxc_array_MOD_aa_4d_1d_ip\n-00000258 T __gridxc_array_MOD_aa_4d_1d_sp\n-00003750 T __gridxc_array_MOD_ac_1d_2d_dp\n-00003974 T __gridxc_array_MOD_ac_1d_2d_ip\n-00003864 T __gridxc_array_MOD_ac_1d_2d_sp\n-00003320 T __gridxc_array_MOD_ac_1d_3d_dp\n-000035f4 T __gridxc_array_MOD_ac_1d_3d_ip\n-00003488 T __gridxc_array_MOD_ac_1d_3d_sp\n-00002f30 T __gridxc_array_MOD_ac_2d_1d_dp\n-000031d0 T __gridxc_array_MOD_ac_2d_1d_ip\n-00003080 T __gridxc_array_MOD_ac_2d_1d_sp\n-000029a8 T __gridxc_array_MOD_ac_3d_1d_dp\n-00002d58 T __gridxc_array_MOD_ac_3d_1d_ip\n-00002b80 T __gridxc_array_MOD_ac_3d_1d_sp\n-00002298 T __gridxc_array_MOD_ac_4d_1d_dp\n-00002748 T __gridxc_array_MOD_ac_4d_1d_ip\n-000024f0 T __gridxc_array_MOD_ac_4d_1d_sp\n+000004b8 T __gridxc_array_MOD_aa_4d_1d_ip\n+0000025c T __gridxc_array_MOD_aa_4d_1d_sp\n+000032c0 T __gridxc_array_MOD_ac_1d_2d_dp\n+000034e8 T __gridxc_array_MOD_ac_1d_2d_ip\n+000033d4 T __gridxc_array_MOD_ac_1d_2d_sp\n+00002e88 T __gridxc_array_MOD_ac_1d_3d_dp\n+00003160 T __gridxc_array_MOD_ac_1d_3d_ip\n+00002ff4 T __gridxc_array_MOD_ac_1d_3d_sp\n+00002ab0 T __gridxc_array_MOD_ac_2d_1d_dp\n+00002d40 T __gridxc_array_MOD_ac_2d_1d_ip\n+00002bf8 T __gridxc_array_MOD_ac_2d_1d_sp\n+00002528 T __gridxc_array_MOD_ac_3d_1d_dp\n+000028d8 T __gridxc_array_MOD_ac_3d_1d_ip\n+00002700 T __gridxc_array_MOD_ac_3d_1d_sp\n+00001e18 T __gridxc_array_MOD_ac_4d_1d_dp\n+000022c8 T __gridxc_array_MOD_ac_4d_1d_ip\n+00002070 T __gridxc_array_MOD_ac_4d_1d_sp\n U __gridxc_sys_MOD_die\n U memcpy\n \n atomxc.F90.o:\n 00000000 r .LC0\n 00000018 r .LC1\n 0000005c r .LC10\n@@ -634,15 +636,15 @@\n U _gfortran_transfer_character_write\n U _gfortran_transfer_integer_write\n U _gfortran_transfer_real_write\n U free\n U sincos\n \n cellsubs.F90.o:\n-00000050 T __gridxc_cellsubs_MOD_reclat\n+00000058 T __gridxc_cellsubs_MOD_reclat\n 00000000 T __gridxc_cellsubs_MOD_volcel\n \n cellxc.F90.o:\n 00000000 r .LC0\n 00000028 r .LC10\n 00000060 r .LC11\n 00000084 r .LC12\n@@ -691,26 +693,27 @@\n 00000414 r .LC55\n 00000420 r .LC56\n 00000018 r .LC6\n 0000001c r .LC7\n 00000020 r .LC8\n 00000024 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n+ U __aeabi_idiv\n U __gridxc_alloc_MOD_alloc_default\n U __gridxc_alloc_MOD_dealloc_d1\n U __gridxc_alloc_MOD_dealloc_d2\n U __gridxc_alloc_MOD_dealloc_d3\n U __gridxc_alloc_MOD_dealloc_d4\n U __gridxc_alloc_MOD_dealloc_l3\n U __gridxc_alloc_MOD_realloc_d1\n U __gridxc_alloc_MOD_realloc_d2\n U __gridxc_alloc_MOD_realloc_d3\n U __gridxc_alloc_MOD_realloc_d4\n U __gridxc_alloc_MOD_realloc_l3\n-000005dc T __gridxc_cell_MOD_cellxc\n+00000614 T __gridxc_cell_MOD_cellxc\n U __gridxc_cellsubs_MOD_reclat\n U __gridxc_cellsubs_MOD_volcel\n U __gridxc_chkgmx_MOD_meshkcut\n U __gridxc_config_MOD_gridxc_totnodes\n U __gridxc_fftr_MOD_fftk2r\n U __gridxc_fftr_MOD_fftr2k\n U __gridxc_gga_MOD_ggaxc\n@@ -781,40 +784,40 @@\n 00000504 b nonempty.22\n 00000008 d oldmesh.47\n 00000600 b phi.16\n 00000060 d rght2my.2\n 00000020 d timeavge.45\n 00000018 d timedisp.46\n 00000630 b tk.15\n-00000718 b tq.9\n+00000714 b tq.9\n 00000654 b tr.14\n 00000678 b tvac.13\n 000006e4 b tvdw.10\n 000006c0 b uk.11\n-00000790 b uq.7\n+0000078c b uq.7\n 0000069c b ur.12\n-00000760 b uvdw.8\n-000007d8 b vj.4\n-000007fc b vleft.6\n+0000075c b uvdw.8\n+000007d4 b vj.4\n+000007f8 b vleft.6\n 000002c4 b vleft1.32\n 00000354 b vleft2.30\n 000003e4 b vleft3.28\n-00000844 b vrght.5\n+00000840 b vrght.5\n 0000030c b vrght1.31\n 0000039c b vrght2.29\n 0000042c b vrght3.27\n 000001f8 b workload.43\n \n chkgmx.F90.o:\n 00000000 r .LC0\n U _GLOBAL_OFFSET_TABLE_\n U __gridxc_cellsubs_MOD_reclat\n 00000000 T __gridxc_chkgmx_MOD_chkgmx\n 00000000 t __gridxc_chkgmx_MOD_chkgmx.localalias\n-000003a0 T __gridxc_chkgmx_MOD_meshkcut\n+000004c8 T __gridxc_chkgmx_MOD_meshkcut\n U __gridxc_minvec_MOD_minvec\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n \n debugxc.F90.o:\n 00000000 r .LC0\n@@ -859,37 +862,38 @@\n U __gridxc_sys_MOD_gridxc_timer_stop\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_associated\n U _gfortran_internal_pack\n U _gfortran_internal_unpack\n 00000024 d a2my.2\n-00000088 b adat.0\n+00000084 b adat.0\n 00000000 d adistr.6\n U free\n 00000010 d io2my.5\n 00000018 d my2a.3\n 00000014 d my2io.4\n-00000040 b mydat.1\n+0000003c b mydat.1\n 0000000c d mydistr.7\n 00000000 b oldmesh.9\n-00000010 b trigs.8\n+0000000c b trigs.8\n \n fftr.F90.o:\n 00000000 r .LC0\n 00000030 r .LC1\n 0000003c r .LC4\n 00000048 r .LC6\n 00000078 r .LC7\n U _GLOBAL_OFFSET_TABLE_\n+ U __aeabi_idiv\n U __gridxc_alloc_MOD_dealloc_d4\n U __gridxc_alloc_MOD_realloc_d4\n U __gridxc_fft3d_MOD_fft3d\n 00000000 T __gridxc_fftr_MOD_fftk2r\n-00000d78 T __gridxc_fftr_MOD_fftr2k\n+00000e58 T __gridxc_fftr_MOD_fftr2k\n 00000004 D __gridxc_fftr_MOD_k2r\n 00000000 D __gridxc_fftr_MOD_kdistr\n 00000008 D __gridxc_fftr_MOD_mk2k\n 0000000c D __gridxc_fftr_MOD_r2k\n 000000d8 B __gridxc_fftr_MOD_themesh\n U __gridxc_mesh3d_MOD_associatemeshtask\n U __gridxc_mesh3d_MOD_copymeshdata\n@@ -954,52 +958,52 @@\n 000001d8 r .LC57\n 000001e0 r .LC58\n 000001e8 r .LC59\n 00000000 r .LC8\n 00000028 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n U __gridxc_am05_MOD_am05wbs\n-00001b00 T __gridxc_gga_MOD_am05xc\n-00001b00 t __gridxc_gga_MOD_am05xc.localalias\n-00000b78 t __gridxc_gga_MOD_b88formx.constprop.0\n-00001330 T __gridxc_gga_MOD_b88kbmx\n-00001330 t __gridxc_gga_MOD_b88kbmx.localalias\n-00001414 T __gridxc_gga_MOD_b88x\n-00001414 t __gridxc_gga_MOD_b88x.localalias\n-000014fc T __gridxc_gga_MOD_bhx\n-000014fc t __gridxc_gga_MOD_bhx.localalias\n-00002d68 T __gridxc_gga_MOD_blypxc\n-00002d68 t __gridxc_gga_MOD_blypxc.localalias\n-00000f48 T __gridxc_gga_MOD_c09x\n-00000f48 t __gridxc_gga_MOD_c09x.localalias\n-0000479c T __gridxc_gga_MOD_ggaxc\n-000003c0 t __gridxc_gga_MOD_pbeformxc\n-00004300 T __gridxc_gga_MOD_pbegcgxhegxc\n-00004300 t __gridxc_gga_MOD_pbegcgxhegxc.localalias\n-000043ac T __gridxc_gga_MOD_pbegcgxloxc\n-000043ac t __gridxc_gga_MOD_pbegcgxloxc.localalias\n-00004454 T __gridxc_gga_MOD_pbejsjrhegxc\n-00004454 t __gridxc_gga_MOD_pbejsjrhegxc.localalias\n-000044fc T __gridxc_gga_MOD_pbejsjrloxc\n-000044fc t __gridxc_gga_MOD_pbejsjrloxc.localalias\n-000045a4 T __gridxc_gga_MOD_pbesolxc\n-000045a4 t __gridxc_gga_MOD_pbesolxc.localalias\n-000046f4 T __gridxc_gga_MOD_pbexc\n+00001ca8 T __gridxc_gga_MOD_am05xc\n+00001ca8 t __gridxc_gga_MOD_am05xc.localalias\n+00000c70 t __gridxc_gga_MOD_b88formx.constprop.0\n+000014a8 T __gridxc_gga_MOD_b88kbmx\n+000014a8 t __gridxc_gga_MOD_b88kbmx.localalias\n+0000158c T __gridxc_gga_MOD_b88x\n+0000158c t __gridxc_gga_MOD_b88x.localalias\n+00001674 T __gridxc_gga_MOD_bhx\n+00001674 t __gridxc_gga_MOD_bhx.localalias\n+00003098 T __gridxc_gga_MOD_blypxc\n+00003098 t __gridxc_gga_MOD_blypxc.localalias\n+00001088 T __gridxc_gga_MOD_c09x\n+00001088 t __gridxc_gga_MOD_c09x.localalias\n+00004ccc T __gridxc_gga_MOD_ggaxc\n+000003f8 t __gridxc_gga_MOD_pbeformxc\n+00004830 T __gridxc_gga_MOD_pbegcgxhegxc\n+00004830 t __gridxc_gga_MOD_pbegcgxhegxc.localalias\n+000048dc T __gridxc_gga_MOD_pbegcgxloxc\n+000048dc t __gridxc_gga_MOD_pbegcgxloxc.localalias\n+00004984 T __gridxc_gga_MOD_pbejsjrhegxc\n+00004984 t __gridxc_gga_MOD_pbejsjrhegxc.localalias\n+00004a2c T __gridxc_gga_MOD_pbejsjrloxc\n+00004a2c t __gridxc_gga_MOD_pbejsjrloxc.localalias\n+00004ad4 T __gridxc_gga_MOD_pbesolxc\n+00004ad4 t __gridxc_gga_MOD_pbesolxc.localalias\n+00004c24 T __gridxc_gga_MOD_pbexc\n 00000000 t __gridxc_gga_MOD_pw86formx\n-00001a18 T __gridxc_gga_MOD_pw86rx\n-00001a18 t __gridxc_gga_MOD_pw86rx.localalias\n-00001a8c T __gridxc_gga_MOD_pw86x\n-00001a8c t __gridxc_gga_MOD_pw86x.localalias\n-00003838 T __gridxc_gga_MOD_pw91xc\n-00003838 t __gridxc_gga_MOD_pw91xc.localalias\n-0000464c T __gridxc_gga_MOD_revpbexc\n-000025d8 T __gridxc_gga_MOD_rpbexc\n-000025d8 t __gridxc_gga_MOD_rpbexc.localalias\n-00001dac T __gridxc_gga_MOD_wcxc\n-00001dac t __gridxc_gga_MOD_wcxc.localalias\n+00001bc0 T __gridxc_gga_MOD_pw86rx\n+00001bc0 t __gridxc_gga_MOD_pw86rx.localalias\n+00001c34 T __gridxc_gga_MOD_pw86x\n+00001c34 t __gridxc_gga_MOD_pw86x.localalias\n+00003c60 T __gridxc_gga_MOD_pw91xc\n+00003c60 t __gridxc_gga_MOD_pw91xc.localalias\n+00004b7c T __gridxc_gga_MOD_revpbexc\n+00002858 T __gridxc_gga_MOD_rpbexc\n+00002858 t __gridxc_gga_MOD_rpbexc.localalias\n+00001f7c T __gridxc_gga_MOD_wcxc\n+00001f7c t __gridxc_gga_MOD_wcxc.localalias\n U __gridxc_hybrids_MOD_hsexc\n U __gridxc_hybrids_MOD_pbe0xc\n U __gridxc_lda_MOD_exchng\n U __gridxc_lda_MOD_pw92c\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n@@ -1038,33 +1042,36 @@\n 00000070 r .LC4\n 0000008c r .LC5\n 000000ec r .LC6\n 000000f4 r .LC7\n 0000011c r .LC8\n 00000174 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n-000116a0 T __gridxc_fft_gpfa_MOD_fft_gpfa_dp\n-000118f0 T __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n-000119dc T __gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp\n-000117c8 T __gridxc_fft_gpfa_MOD_fft_gpfa_sp\n+ U __aeabi_idiv\n+ U __aeabi_idivmod\n+ U __aeabi_uidiv\n+000123ac T __gridxc_fft_gpfa_MOD_fft_gpfa_dp\n+000125fc T __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n+000126d8 T __gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp\n+000124d4 T __gridxc_fft_gpfa_MOD_fft_gpfa_sp\n 00000000 B __gridxc_fft_gpfa_MOD_msg\n-00011acc T __gridxc_fft_gpfa_MOD_nfft\n+000127b4 T __gridxc_fft_gpfa_MOD_nfft\n 00000000 D __gridxc_fft_gpfa_MOD_nold\n-00010fbc T __gridxc_fft_gpfa_MOD_setgpfa\n-000114e0 t __gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0\n-00011248 T __gridxc_fft_gpfa_MOD_setgpfa_check\n-00011248 t __gridxc_fft_gpfa_MOD_setgpfa_check.localalias\n-00000018 B __gridxc_fft_gpfa_MOD_trigs\n+00011cd4 T __gridxc_fft_gpfa_MOD_setgpfa\n+00012210 t __gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0\n+00011f68 T __gridxc_fft_gpfa_MOD_setgpfa_check\n+00011f68 t __gridxc_fft_gpfa_MOD_setgpfa_check.localalias\n+00000014 B __gridxc_fft_gpfa_MOD_trigs\n 00000000 t __gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0\n-000030a0 t __gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0\n-0000dd28 T __gridxc_gpfa_core_dp_MOD_gpfa_\n-0000dd28 t __gridxc_gpfa_core_dp_MOD_gpfa_.localalias\n-000048d0 t __gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0\n-000086ec T __gridxc_gpfa_core_sp_MOD_gpfa_\n-000086ec t __gridxc_gpfa_core_sp_MOD_gpfa_.localalias\n+00003338 t __gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0\n+0000e7b8 T __gridxc_gpfa_core_dp_MOD_gpfa_\n+0000e7b8 t __gridxc_gpfa_core_dp_MOD_gpfa_.localalias\n+00004bb8 t __gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0\n+00008adc T __gridxc_gpfa_core_sp_MOD_gpfa_\n+00008adc t __gridxc_gpfa_core_sp_MOD_gpfa_.localalias\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_concat_string\n U _gfortran_os_error_at\n U _gfortran_pow_i4_i4\n U _gfortran_runtime_error\n@@ -1090,29 +1097,31 @@\n 000000ac r .LC4\n 000000d4 r .LC5\n 000000d8 r .LC6\n 0000010c r .LC7\n 00000144 r .LC8\n 00000148 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n-00000318 T __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n+ U __aeabi_idiv\n+ U __aeabi_idivmod\n+0000033c T __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n 00000008 R __gridxc_interpolation_MOD___def_init_gridxc_interpolation_Spline_t\n 00000000 T __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n 00000000 D __gridxc_interpolation_MOD___vtab_gridxc_interpolation_Spline_t\n-000003c0 T __gridxc_interpolation_MOD_clean_spline\n-00001114 T __gridxc_interpolation_MOD_evaluate_spline\n-0000091c T __gridxc_interpolation_MOD_evaluate_spline_dx\n-00000d9c T __gridxc_interpolation_MOD_evaluate_spline_n\n-00000a84 T __gridxc_interpolation_MOD_evaluate_spline_x\n-00001cac T __gridxc_interpolation_MOD_generate_spline_dx\n-000013fc T __gridxc_interpolation_MOD_generate_spline_master\n-000013fc t __gridxc_interpolation_MOD_generate_spline_master.localalias\n-00001b44 T __gridxc_interpolation_MOD_generate_spline_x\n-00001b44 t __gridxc_interpolation_MOD_generate_spline_x.localalias\n-00000418 T __gridxc_interpolation_MOD_polint\n+000003e4 T __gridxc_interpolation_MOD_clean_spline\n+00001144 T __gridxc_interpolation_MOD_evaluate_spline\n+00000948 T __gridxc_interpolation_MOD_evaluate_spline_dx\n+00000ddc T __gridxc_interpolation_MOD_evaluate_spline_n\n+00000aac T __gridxc_interpolation_MOD_evaluate_spline_x\n+00001d04 T __gridxc_interpolation_MOD_generate_spline_dx\n+00001414 T __gridxc_interpolation_MOD_generate_spline_master\n+00001414 t __gridxc_interpolation_MOD_generate_spline_master.localalias\n+00001b9c T __gridxc_interpolation_MOD_generate_spline_x\n+00001b9c t __gridxc_interpolation_MOD_generate_spline_x.localalias\n+0000043c T __gridxc_interpolation_MOD_polint\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_os_error_at\n U _gfortran_runtime_error\n U _gfortran_runtime_error_at\n U _gfortran_select_string\n@@ -1131,20 +1140,20 @@\n 00000044 r .LC4\n 00000048 r .LC5\n 0000004c r .LC6\n 00000050 r .LC7\n 00000058 r .LC8\n 00000060 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n-00000ea8 T __gridxc_lda_MOD_exchng\n-00000ea8 t __gridxc_lda_MOD_exchng.localalias\n-00001098 T __gridxc_lda_MOD_ldaxc\n-000007c8 T __gridxc_lda_MOD_pw92c\n-000007c8 t __gridxc_lda_MOD_pw92c.localalias\n-00000ca8 T __gridxc_lda_MOD_pw92xc\n+00001010 T __gridxc_lda_MOD_exchng\n+00001010 t __gridxc_lda_MOD_exchng.localalias\n+00001218 T __gridxc_lda_MOD_ldaxc\n+000008a0 T __gridxc_lda_MOD_pw92c\n+000008a0 t __gridxc_lda_MOD_pw92c.localalias\n+00000df8 T __gridxc_lda_MOD_pw92xc\n 00000000 T __gridxc_lda_MOD_pzxc\n 00000000 t __gridxc_lda_MOD_pzxc.localalias\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n U __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n U __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n@@ -1179,15 +1188,15 @@\n 000004bc T __gridxc_io_MOD_io_geterr\n 000004ac T __gridxc_io_MOD_io_getout\n 000002d4 T __gridxc_io_MOD_io_reserve\n 000004dc T __gridxc_io_MOD_io_seterr\n 000004cc T __gridxc_io_MOD_io_setout\n 00000000 T __gridxc_io_MOD_io_status\n 00000004 B __gridxc_io_MOD_iostat\n-00000008 D __gridxc_io_MOD_lun_is_free\n+00000004 D __gridxc_io_MOD_lun_is_free\n 0000000c B __gridxc_io_MOD_named\n 00000008 B __gridxc_io_MOD_opened\n 00000054 B __gridxc_io_MOD_stderr\n 00000000 D __gridxc_io_MOD_stdout\n 00000050 B __gridxc_io_MOD_used\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n@@ -1265,35 +1274,35 @@\n U __gridxc_interpolation_MOD_evaluate_spline_dx\n U __gridxc_interpolation_MOD_generate_spline_dx\n U __gridxc_interpolation_MOD_polint\n 00000038 B __gridxc_mesh1d_MOD_aa\n 00000030 B __gridxc_mesh1d_MOD_b\n 00000028 B __gridxc_mesh1d_MOD_d\n 00000000 B __gridxc_mesh1d_MOD_defined_mesh\n-000021f0 T __gridxc_mesh1d_MOD_derivative\n-000021f0 t __gridxc_mesh1d_MOD_derivative.localalias\n+00002230 T __gridxc_mesh1d_MOD_derivative\n+00002230 t __gridxc_mesh1d_MOD_derivative.localalias\n 00000388 T __gridxc_mesh1d_MOD_get_mesh\n 00000388 t __gridxc_mesh1d_MOD_get_mesh.localalias\n-000037a0 T __gridxc_mesh1d_MOD_get_n\n-000029f4 T __gridxc_mesh1d_MOD_integral\n-000029f4 t __gridxc_mesh1d_MOD_integral.localalias\n-00001ef4 T __gridxc_mesh1d_MOD_interpolation_local\n+000037c0 T __gridxc_mesh1d_MOD_get_n\n+000029fc T __gridxc_mesh1d_MOD_integral\n+000029fc t __gridxc_mesh1d_MOD_integral.localalias\n+00001f1c T __gridxc_mesh1d_MOD_interpolation_local\n 0000000c D __gridxc_mesh1d_MOD_interpolation_method\n 00000040 B __gridxc_mesh1d_MOD_ivec\n 00000000 T __gridxc_mesh1d_MOD_locate\n 00000000 t __gridxc_mesh1d_MOD_locate.localalias\n 00000000 D __gridxc_mesh1d_MOD_mesh_type\n-00002e18 T __gridxc_mesh1d_MOD_numerov\n-00000120 B __gridxc_mesh1d_MOD_s0\n-00000148 B __gridxc_mesh1d_MOD_s1\n-00000170 B __gridxc_mesh1d_MOD_s2\n+00002e38 T __gridxc_mesh1d_MOD_numerov\n+00000118 B __gridxc_mesh1d_MOD_s0\n+0000013c B __gridxc_mesh1d_MOD_s1\n+00000160 B __gridxc_mesh1d_MOD_s2\n 000006ec T __gridxc_mesh1d_MOD_set_interpolation\n 00000808 T __gridxc_mesh1d_MOD_set_mesh\n 00000808 t __gridxc_mesh1d_MOD_set_mesh.localalias\n-000000f8 B __gridxc_mesh1d_MOD_sqrxp\n+000000f4 B __gridxc_mesh1d_MOD_sqrxp\n 00000004 B __gridxc_mesh1d_MOD_xi\n 00000064 B __gridxc_mesh1d_MOD_xp1\n 00000088 B __gridxc_mesh1d_MOD_xp2\n 000000ac B __gridxc_mesh1d_MOD_xp3\n 000000d0 B __gridxc_mesh1d_MOD_xp4\n 00000018 D __gridxc_mesh1d_MOD_yp1\n 00000020 D __gridxc_mesh1d_MOD_ypn\n@@ -1308,14 +1317,15 @@\n U _gfortran_st_write_done\n U _gfortran_string_trim\n U _gfortran_transfer_character_write\n U _gfortran_transfer_real_write\n U exp\n U free\n U log\n+ U lround\n U malloc\n U memcpy\n U memset\n \n mesh3d.F90.o:\n 00000000 r .LC0\n 00000044 r .LC1\n@@ -1373,51 +1383,54 @@\n 00000168 r .LC6\n 00000d00 r .LC61\n 00000d20 r .LC62\n 0000019c r .LC7\n 000001d8 r .LC8\n 00000214 r .LC9\n U _GLOBAL_OFFSET_TABLE_\n+ U __aeabi_idiv\n+ U __aeabi_idivmod\n+ U __aeabi_uidiv\n U __gridxc_alloc_MOD_dealloc_d4\n U __gridxc_alloc_MOD_realloc_d4\n U __gridxc_config_MOD_gridxc_mynode\n U __gridxc_config_MOD_gridxc_totnodes\n 00000020 T __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Distrtype\n 00000000 T __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Tasktype\n 00000110 R __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Distrtype\n 00000010 R __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Tasktype\n 0000001c D __gridxc_mesh3d_MOD___vtab_gridxc_mesh3d_Distrtype\n 00000000 D __gridxc_mesh3d_MOD___vtab_gridxc_mesh3d_Tasktype\n-00005648 T __gridxc_mesh3d_MOD_addmeshdata\n-0000477c T __gridxc_mesh3d_MOD_associatemeshtask\n-0000477c t __gridxc_mesh3d_MOD_associatemeshtask.localalias\n-00004ef8 T __gridxc_mesh3d_MOD_copymeshdata\n-00004ef8 t __gridxc_mesh3d_MOD_copymeshdata.localalias\n-00000ed8 t __gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0\n-00000934 t __gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0\n-000040f8 T __gridxc_mesh3d_MOD_fftmeshdistr\n-00002b24 T __gridxc_mesh3d_MOD_freemeshdistr\n-00002b24 t __gridxc_mesh3d_MOD_freemeshdistr.localalias\n-000028bc T __gridxc_mesh3d_MOD_freemeshtask\n-000028bc t __gridxc_mesh3d_MOD_freemeshtask.localalias\n+000052d0 T __gridxc_mesh3d_MOD_addmeshdata\n+00004470 T __gridxc_mesh3d_MOD_associatemeshtask\n+00004470 t __gridxc_mesh3d_MOD_associatemeshtask.localalias\n+00004b88 T __gridxc_mesh3d_MOD_copymeshdata\n+00004b88 t __gridxc_mesh3d_MOD_copymeshdata.localalias\n+00000d24 t __gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0\n+00000904 t __gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0\n+00003df4 T __gridxc_mesh3d_MOD_fftmeshdistr\n+0000292c T __gridxc_mesh3d_MOD_freemeshdistr\n+0000292c t __gridxc_mesh3d_MOD_freemeshdistr.localalias\n+000026c8 T __gridxc_mesh3d_MOD_freemeshtask\n+000026c8 t __gridxc_mesh3d_MOD_freemeshtask.localalias\n 00000040 t __gridxc_mesh3d_MOD_initdistr.part.0\n-00002874 T __gridxc_mesh3d_MOD_mymeshbox\n+00002680 T __gridxc_mesh3d_MOD_mymeshbox\n 00000000 B __gridxc_mesh3d_MOD_ndistrid\n-0000283c T __gridxc_mesh3d_MOD_nodemeshbox\n-000024c8 t __gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0\n+00002648 T __gridxc_mesh3d_MOD_nodemeshbox\n+000022d4 t __gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0\n 0000004c B __gridxc_mesh3d_MOD_ntaskid\n-000005dc t __gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0\n-00000250 t __gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0\n-000051a0 T __gridxc_mesh3d_MOD_redistributemeshdata\n-00001058 t __gridxc_mesh3d_MOD_reducedata.isra.0\n-00002cf8 t __gridxc_mesh3d_MOD_reducedistr\n-0000260c T __gridxc_mesh3d_MOD_samemeshdistr\n-0000260c t __gridxc_mesh3d_MOD_samemeshdistr.localalias\n-00002fb4 T __gridxc_mesh3d_MOD_setmeshdistr\n-00002fb4 t __gridxc_mesh3d_MOD_setmeshdistr.localalias\n+000005a4 t __gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0\n+00000208 t __gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0\n+00004e34 T __gridxc_mesh3d_MOD_redistributemeshdata\n+00000dec t __gridxc_mesh3d_MOD_reducedata.isra.0\n+00002b00 t __gridxc_mesh3d_MOD_reducedistr\n+00002418 T __gridxc_mesh3d_MOD_samemeshdistr\n+00002418 t __gridxc_mesh3d_MOD_samemeshdistr.localalias\n+00002dbc T __gridxc_mesh3d_MOD_setmeshdistr\n+00002dbc t __gridxc_mesh3d_MOD_setmeshdistr.localalias\n 00006400 D __gridxc_mesh3d_MOD_storedmeshdistr\n 00000000 D __gridxc_mesh3d_MOD_storedmeshtask\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_internal_pack\n U _gfortran_internal_unpack\n@@ -1440,14 +1453,15 @@\n U __gridxc_cellsubs_MOD_volcel\n 00000000 T __gridxc_minvec_MOD_minvec\n U __gridxc_sorting_MOD_order\n U __gridxc_sorting_MOD_ordix\n U __gridxc_sys_MOD_die\n U __stack_chk_fail\n U __stack_chk_guard\n+ U lround\n U memcpy\n \n moreParallelSubs.F90.o:\n 00000000 r .LC0\n 00000008 r .LC1\n 000000c4 r .LC10\n 000000d0 r .LC11\n@@ -1535,36 +1549,36 @@\n U _GLOBAL_OFFSET_TABLE_\n 00000160 T __gridxc_sorting_MOD_iorder\n 00000160 t __gridxc_sorting_MOD_iorder.localalias\n 00000264 T __gridxc_sorting_MOD_order\n 00000264 t __gridxc_sorting_MOD_order.localalias\n 00000364 T __gridxc_sorting_MOD_ordix\n 00000364 t __gridxc_sorting_MOD_ordix.localalias\n-0000056c T __gridxc_sorting_MOD_ordvec\n+00000534 T __gridxc_sorting_MOD_ordvec\n U __stack_chk_fail\n U __stack_chk_guard\n U memcpy\n 00000000 t siftdown.1.isra.0\n \n sys.F90.o:\n 00000000 r .LC0\n 00000038 r .LC1\n 00000040 r .LC2\n 00000064 r .LC3\n 00000068 r .LC4\n U _GLOBAL_OFFSET_TABLE_\n 00000008 D __gridxc_sys_MOD_die\n 00000000 T __gridxc_sys_MOD_dummy_timer_start\n-0000017c T __gridxc_sys_MOD_dummy_timer_stop\n-000001a8 T __gridxc_sys_MOD_exit\n+0000016c T __gridxc_sys_MOD_dummy_timer_stop\n+00000198 T __gridxc_sys_MOD_exit\n 00000004 D __gridxc_sys_MOD_gridxc_timer_start\n 00000000 D __gridxc_sys_MOD_gridxc_timer_stop\n-000001ac T __gridxc_sys_MOD_set_die_routine\n-00000194 T __gridxc_sys_MOD_set_timer_start_routine\n-00000180 T __gridxc_sys_MOD_set_timer_stop_routine\n+0000019c T __gridxc_sys_MOD_set_die_routine\n+00000184 T __gridxc_sys_MOD_set_timer_start_routine\n+00000170 T __gridxc_sys_MOD_set_timer_stop_routine\n 00000004 T __gridxc_sys_MOD_simple_die_routine\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_concat_string\n U _gfortran_st_write\n U _gfortran_st_write_done\n U _gfortran_string_len_trim\n@@ -1627,44 +1641,44 @@\n U __gridxc_lda_MOD_ldaxc\n U __gridxc_mesh1d_MOD_get_mesh\n U __gridxc_mesh1d_MOD_get_n\n U __gridxc_mesh1d_MOD_integral\n U __gridxc_mesh1d_MOD_set_mesh\n U __gridxc_radfft_MOD_radfft\n U __gridxc_sys_MOD_die\n-00000288 B __gridxc_vdwxc_MOD_d2phidk2\n-00000248 B __gridxc_vdwxc_MOD_d2phidr2\n-000002d0 B __gridxc_vdwxc_MOD_dk\n+00000278 B __gridxc_vdwxc_MOD_d2phidk2\n+0000023c B __gridxc_vdwxc_MOD_d2phidr2\n+000002c0 B __gridxc_vdwxc_MOD_dk\n 00000000 B __gridxc_vdwxc_MOD_dmesh\n 00000000 t __gridxc_vdwxc_MOD_dphi.isra.0\n-000002c8 B __gridxc_vdwxc_MOD_dr\n-00000800 t __gridxc_vdwxc_MOD_iofd.isra.0\n+000002b8 B __gridxc_vdwxc_MOD_dr\n+00000868 t __gridxc_vdwxc_MOD_iofd.isra.0\n 000001b8 B __gridxc_vdwxc_MOD_kcut\n-000002dc B __gridxc_vdwxc_MOD_kcut_set\n-000002d8 B __gridxc_vdwxc_MOD_nk\n-000011dc t __gridxc_vdwxc_MOD_phi_soft.isra.0\n-00005748 B __gridxc_vdwxc_MOD_phi_table\n+000002cc B __gridxc_vdwxc_MOD_kcut_set\n+000002c8 B __gridxc_vdwxc_MOD_nk\n+00001290 t __gridxc_vdwxc_MOD_phi_soft.isra.0\n+00005738 B __gridxc_vdwxc_MOD_phi_table\n 000001b0 B __gridxc_vdwxc_MOD_phi_table_set\n-00000b34 t __gridxc_vdwxc_MOD_phi_val.isra.0\n-00000208 B __gridxc_vdwxc_MOD_phik\n-000001c8 B __gridxc_vdwxc_MOD_phir\n-000008d0 t __gridxc_vdwxc_MOD_pofq\n+00000bb4 t __gridxc_vdwxc_MOD_phi_val.isra.0\n+00000200 B __gridxc_vdwxc_MOD_phik\n+000001c4 B __gridxc_vdwxc_MOD_phir\n+00000940 t __gridxc_vdwxc_MOD_pofq\n 000000b0 B __gridxc_vdwxc_MOD_qmesh\n 000001c0 B __gridxc_vdwxc_MOD_qmesh_set\n-00002270 t __gridxc_vdwxc_MOD_qofrho.isra.0\n-00002578 t __gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0\n-000012e0 t __gridxc_vdwxc_MOD_set_phi_table\n+00002220 t __gridxc_vdwxc_MOD_qofrho.isra.0\n+00002540 t __gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0\n+00001388 t __gridxc_vdwxc_MOD_set_phi_table\n 00000018 D __gridxc_vdwxc_MOD_vdw_author\n-00004e88 T __gridxc_vdwxc_MOD_vdw_decusp\n-00004c34 T __gridxc_vdwxc_MOD_vdw_get_qmesh\n-000045c0 T __gridxc_vdwxc_MOD_vdw_localxc\n-00004014 T __gridxc_vdwxc_MOD_vdw_phi\n-00003ef0 T __gridxc_vdwxc_MOD_vdw_set_author\n-00003018 T __gridxc_vdwxc_MOD_vdw_set_kcut\n-0000276c T __gridxc_vdwxc_MOD_vdw_theta\n+00004e74 T __gridxc_vdwxc_MOD_vdw_decusp\n+00004c28 T __gridxc_vdwxc_MOD_vdw_get_qmesh\n+000045b4 T __gridxc_vdwxc_MOD_vdw_localxc\n+00003fec T __gridxc_vdwxc_MOD_vdw_phi\n+00003ec8 T __gridxc_vdwxc_MOD_vdw_set_author\n+00002fd8 T __gridxc_vdwxc_MOD_vdw_set_kcut\n+0000272c T __gridxc_vdwxc_MOD_vdw_theta\n 00000010 D __gridxc_vdwxc_MOD_zab\n U __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n U __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n U __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n U __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n U __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n U __stack_chk_fail\n@@ -1688,28 +1702,28 @@\n U _gfortran_transfer_integer\n U _gfortran_transfer_integer_write\n 000000a8 b a.3\n 000001a8 b a.9\n 000000a0 b b.2\n 000001a0 b b.8\n U cbrt\n-00001f08 b d2pdq2.11\n+00001ef8 b d2pdq2.11\n U exp\n 00000008 d first_call.10\n 00000004 d first_call.13\n 00000000 d first_call.4\n U free\n-000002e0 b initialized.1\n+000002d0 b initialized.1\n U log\n U malloc\n U memcpy\n U memset\n-00003b28 b p.12\n+00003b18 b p.12\n U sincos\n-000002e8 b table.0\n+000002d8 b table.0\n 00000030 r wt.7\n \n vv_vdwxc.F90.o:\n 0000004c r .LC10\n 00000068 r .LC12\n 00000084 r .LC13\n 000000a4 r .LC14\n@@ -1728,67 +1742,67 @@\n U __gridxc_alloc_MOD_realloc_d3\n U __gridxc_interpolation_MOD_generate_spline_dx\n U __gridxc_interpolation_MOD_generate_spline_x\n U __gridxc_mesh1d_MOD_get_mesh\n U __gridxc_mesh1d_MOD_set_mesh\n U __gridxc_radfft_MOD_radfft\n U __gridxc_sys_MOD_die\n-00000130 B __gridxc_vv_vdwxc_MOD_d2phidk2\n-000000f0 B __gridxc_vv_vdwxc_MOD_d2phidr2\n-00000178 B __gridxc_vv_vdwxc_MOD_dk\n+00000124 B __gridxc_vv_vdwxc_MOD_d2phidk2\n+000000e8 B __gridxc_vv_vdwxc_MOD_d2phidr2\n+00000170 B __gridxc_vv_vdwxc_MOD_dk\n 00000068 B __gridxc_vv_vdwxc_MOD_dr\n-00000180 B __gridxc_vv_vdwxc_MOD_kcut\n+00000178 B __gridxc_vv_vdwxc_MOD_kcut\n 00000064 B __gridxc_vv_vdwxc_MOD_kcut_set\n 00000000 B __gridxc_vv_vdwxc_MOD_kfmesh\n 00000038 B __gridxc_vv_vdwxc_MOD_kgmesh\n-00000170 B __gridxc_vv_vdwxc_MOD_kmax\n+00000168 B __gridxc_vv_vdwxc_MOD_kmax\n 00000060 B __gridxc_vv_vdwxc_MOD_kmesh_set\n-0000016c B __gridxc_vv_vdwxc_MOD_nk\n-00000188 B __gridxc_vv_vdwxc_MOD_phi_table_set\n-000000b0 B __gridxc_vv_vdwxc_MOD_phik\n+00000160 B __gridxc_vv_vdwxc_MOD_nk\n+00000180 B __gridxc_vv_vdwxc_MOD_phi_table_set\n+000000ac B __gridxc_vv_vdwxc_MOD_phik\n 00000070 B __gridxc_vv_vdwxc_MOD_phir\n-00000134 t __gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0\n+00000104 t __gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0\n 00000000 t __gridxc_vv_vdwxc_MOD_set_kmesh.part.0\n-000001fc t __gridxc_vv_vdwxc_MOD_set_phi_table.part.0\n-000027d0 T __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n-00002634 T __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n-000020cc T __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n-00001ff0 T __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n-00000e68 T __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n+000001cc t __gridxc_vv_vdwxc_MOD_set_phi_table.part.0\n+0000296c T __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n+000027d0 T __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n+0000223c T __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n+0000215c T __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n+00000e2c T __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_internal_pack\n U _gfortran_internal_unpack\n U _gfortran_st_close\n U _gfortran_st_open\n U _gfortran_st_write\n U _gfortran_st_write_done\n U _gfortran_transfer_array_write\n U _gfortran_transfer_real_write\n-00000630 b akf.3\n-00000638 b akg.2\n-00000640 b bkf.1\n-00000648 b bkg.0\n+00000628 b akf.3\n+00000630 b akg.2\n+00000638 b bkf.1\n+00000640 b bkg.0\n U cbrt\n-00000318 b d2pkfdkf2.7\n-00000568 b d2pkgdkg2.5\n+00000310 b d2pkfdkf2.7\n+00000560 b d2pkgdkg2.5\n U exp\n 00000004 d first_call.4\n 00000000 d first_call.9\n U free\n U log\n U memcpy\n U memset\n-00000190 b pkf.8\n-000004a0 b pkg.6\n+00000188 b pkf.8\n+00000498 b pkg.6\n U pow\n \n xc_hybrids.F90.o:\n U _GLOBAL_OFFSET_TABLE_\n-000007e0 T __gridxc_hybrids_MOD_hsexc\n+00000880 T __gridxc_hybrids_MOD_hsexc\n 00000000 T __gridxc_hybrids_MOD_pbe0xc\n U __gridxc_lda_MOD_exchng\n U __gridxc_lda_MOD_pw92c\n U __gridxc_xwpbe_MOD_xwpbe\n U __stack_chk_fail\n U __stack_chk_guard\n U cbrt\n@@ -1798,33 +1812,34 @@\n xc_xwpbe.F90.o:\n 00000000 r .LC0\n 0000003c r .LC1\n 00000050 r .LC2\n 0000007c r .LC3\n U _GLOBAL_OFFSET_TABLE_\n 00000000 t __gridxc_xwpbe_MOD_calerf.constprop.0.isra.0\n-00000770 t __gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0\n-000006b4 t __gridxc_xwpbe_MOD_d2exeirhondrho.isra.0\n-000005d4 t __gridxc_xwpbe_MOD_exer.isra.0\n-000003a0 t __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0\n-00008928 T __gridxc_xwpbe_MOD_xwpbe\n-00001560 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0\n-00000820 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0\n-00006748 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0\n-00004b78 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0\n-00003664 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0\n-00002590 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0\n+00000778 t __gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0\n+000006bc t __gridxc_xwpbe_MOD_d2exeirhondrho.isra.0\n+000005dc t __gridxc_xwpbe_MOD_exer.isra.0\n+000003a8 t __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0\n+00008e08 T __gridxc_xwpbe_MOD_xwpbe\n+000015a8 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0\n+00000828 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0\n+00006ad8 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0\n+00004dc8 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0\n+000037d4 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0\n+00002670 t __gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0\n U __stack_chk_fail\n U __stack_chk_guard\n U _gfortran_st_write\n U _gfortran_st_write_done\n U _gfortran_transfer_character_write\n U cbrt\n U exp\n U log\n+ U trunc\n \n xcmod.F90.o:\n 00000000 r .LC0\n 00000004 r .LC1\n 000000c0 r .LC10\n 000000c4 r .LC11\n 000000c8 r .LC12\n@@ -1847,23 +1862,23 @@\n 000000a8 r .LC8\n 000000ac r .LC9\n 00000000 r A.88.1\n 00000010 r A.90.0\n U _GLOBAL_OFFSET_TABLE_\n U __gridxc_sys_MOD_die\n U __gridxc_vdwxc_MOD_vdw_set_author\n-0000064c T __gridxc_xcmod_MOD_getxc\n+00000658 T __gridxc_xcmod_MOD_getxc\n 00000000 B __gridxc_xcmod_MOD_nxcfunc\n 00000000 t __gridxc_xcmod_MOD_process_libxc_spec.constprop.0\n-000009e0 T __gridxc_xcmod_MOD_setxc\n-000009e0 t __gridxc_xcmod_MOD_setxc.localalias\n-00000d90 T __gridxc_xcmod_MOD_setxc_family_authors\n-00000fb0 T __gridxc_xcmod_MOD_setxc_libxc_ids\n-000003f0 B __gridxc_xcmod_MOD_xcauth\n-00000008 B __gridxc_xcmod_MOD_xcfunc\n+000009ec T __gridxc_xcmod_MOD_setxc\n+000009ec t __gridxc_xcmod_MOD_setxc.localalias\n+00000d74 T __gridxc_xcmod_MOD_setxc_family_authors\n+00000f94 T __gridxc_xcmod_MOD_setxc_libxc_ids\n+000003ec B __gridxc_xcmod_MOD_xcauth\n+00000004 B __gridxc_xcmod_MOD_xcfunc\n 00000878 B __gridxc_xcmod_MOD_xcweightc\n 000007d8 B __gridxc_xcmod_MOD_xcweightx\n U __stack_chk_fail\n U __stack_chk_guard\n U __xc_f03_lib_m_MOD_xc_f03_family_from_id\n U __xc_f03_lib_m_MOD_xc_f03_func_end\n U __xc_f03_lib_m_MOD_xc_f03_func_get_info\n"}, {"source1": "file list", "source2": "file list", "unified_diff": "@@ -1,34 +1,34 @@\n ---------- 0 0 0 10886 1970-01-01 00:00:00.000000 /\n ---------- 0 0 0 0 1970-01-01 00:00:00.000000 //\n-?rw-r--r-- 0 0 0 52432 1970-01-01 00:00:00.000000 alloc.F90.o\n-?rw-r--r-- 0 0 0 7364 1970-01-01 00:00:00.000000 am05.F90.o\n-?rw-r--r-- 0 0 0 22296 1970-01-01 00:00:00.000000 array.F90.o\n-?rw-r--r-- 0 0 0 20532 1970-01-01 00:00:00.000000 atomxc.F90.o\n-?rw-r--r-- 0 0 0 2084 1970-01-01 00:00:00.000000 bessph.F90.o\n-?rw-r--r-- 0 0 0 1028 1970-01-01 00:00:00.000000 cellsubs.F90.o\n-?rw-r--r-- 0 0 0 41476 1970-01-01 00:00:00.000000 cellxc.F90.o\n-?rw-r--r-- 0 0 0 2436 1970-01-01 00:00:00.000000 chkgmx.F90.o\n-?rw-r--r-- 0 0 0 2156 1970-01-01 00:00:00.000000 debugxc.F90.o\n-?rw-r--r-- 0 0 0 5940 1970-01-01 00:00:00.000000 fft3d.F90.o\n-?rw-r--r-- 0 0 0 8132 1970-01-01 00:00:00.000000 fftr.F90.o\n-?rw-r--r-- 0 0 0 32676 1970-01-01 00:00:00.000000 ggaxc.F90.o\n-?rw-r--r-- 0 0 0 444 1970-01-01 00:00:00.000000 gridxc.F90.o\n-?rw-r--r-- 0 0 0 928 1970-01-01 00:00:00.000000 gridxc_config.F90.o\n-?rw-r--r-- 0 0 0 78180 1970-01-01 00:00:00.000000 gridxc_fft_gpfa.F90.o\n-?rw-r--r-- 0 0 0 12604 1970-01-01 00:00:00.000000 interpolation.F90.o\n-?rw-r--r-- 0 0 0 8672 1970-01-01 00:00:00.000000 ldaxc.F90.o\n-?rw-r--r-- 0 0 0 4776 1970-01-01 00:00:00.000000 m_io.F90.o\n-?rw-r--r-- 0 0 0 1584 1970-01-01 00:00:00.000000 m_walltime.F90.o\n-?rw-r--r-- 0 0 0 23588 1970-01-01 00:00:00.000000 mesh1d.F90.o\n-?rw-r--r-- 0 0 0 67612 1970-01-01 00:00:00.000000 mesh3d.F90.o\n-?rw-r--r-- 0 0 0 3148 1970-01-01 00:00:00.000000 minvec.F90.o\n-?rw-r--r-- 0 0 0 8024 1970-01-01 00:00:00.000000 moreParallelSubs.F90.o\n-?rw-r--r-- 0 0 0 444 1970-01-01 00:00:00.000000 precision.F90.o\n-?rw-r--r-- 0 0 0 4956 1970-01-01 00:00:00.000000 radfft.F90.o\n-?rw-r--r-- 0 0 0 3436 1970-01-01 00:00:00.000000 sorting.F90.o\n-?rw-r--r-- 0 0 0 2908 1970-01-01 00:00:00.000000 sys.F90.o\n-?rw-r--r-- 0 0 0 34840 1970-01-01 00:00:00.000000 vdwxc.F90.o\n-?rw-r--r-- 0 0 0 15876 1970-01-01 00:00:00.000000 vv_vdwxc.F90.o\n-?rw-r--r-- 0 0 0 4888 1970-01-01 00:00:00.000000 xc_hybrids.F90.o\n-?rw-r--r-- 0 0 0 40140 1970-01-01 00:00:00.000000 xc_xwpbe.F90.o\n-?rw-r--r-- 0 0 0 10232 1970-01-01 00:00:00.000000 xcmod.F90.o\n+?rw-r--r-- 0 0 0 50020 1970-01-01 00:00:00.000000 alloc.F90.o\n+?rw-r--r-- 0 0 0 7732 1970-01-01 00:00:00.000000 am05.F90.o\n+?rw-r--r-- 0 0 0 21120 1970-01-01 00:00:00.000000 array.F90.o\n+?rw-r--r-- 0 0 0 20360 1970-01-01 00:00:00.000000 atomxc.F90.o\n+?rw-r--r-- 0 0 0 2068 1970-01-01 00:00:00.000000 bessph.F90.o\n+?rw-r--r-- 0 0 0 1064 1970-01-01 00:00:00.000000 cellsubs.F90.o\n+?rw-r--r-- 0 0 0 41148 1970-01-01 00:00:00.000000 cellxc.F90.o\n+?rw-r--r-- 0 0 0 2728 1970-01-01 00:00:00.000000 chkgmx.F90.o\n+?rw-r--r-- 0 0 0 2140 1970-01-01 00:00:00.000000 debugxc.F90.o\n+?rw-r--r-- 0 0 0 5816 1970-01-01 00:00:00.000000 fft3d.F90.o\n+?rw-r--r-- 0 0 0 8864 1970-01-01 00:00:00.000000 fftr.F90.o\n+?rw-r--r-- 0 0 0 34168 1970-01-01 00:00:00.000000 ggaxc.F90.o\n+?rw-r--r-- 0 0 0 440 1970-01-01 00:00:00.000000 gridxc.F90.o\n+?rw-r--r-- 0 0 0 924 1970-01-01 00:00:00.000000 gridxc_config.F90.o\n+?rw-r--r-- 0 0 0 83080 1970-01-01 00:00:00.000000 gridxc_fft_gpfa.F90.o\n+?rw-r--r-- 0 0 0 12800 1970-01-01 00:00:00.000000 interpolation.F90.o\n+?rw-r--r-- 0 0 0 9076 1970-01-01 00:00:00.000000 ldaxc.F90.o\n+?rw-r--r-- 0 0 0 4764 1970-01-01 00:00:00.000000 m_io.F90.o\n+?rw-r--r-- 0 0 0 1580 1970-01-01 00:00:00.000000 m_walltime.F90.o\n+?rw-r--r-- 0 0 0 23680 1970-01-01 00:00:00.000000 mesh1d.F90.o\n+?rw-r--r-- 0 0 0 67188 1970-01-01 00:00:00.000000 mesh3d.F90.o\n+?rw-r--r-- 0 0 0 3344 1970-01-01 00:00:00.000000 minvec.F90.o\n+?rw-r--r-- 0 0 0 8020 1970-01-01 00:00:00.000000 moreParallelSubs.F90.o\n+?rw-r--r-- 0 0 0 440 1970-01-01 00:00:00.000000 precision.F90.o\n+?rw-r--r-- 0 0 0 4884 1970-01-01 00:00:00.000000 radfft.F90.o\n+?rw-r--r-- 0 0 0 3284 1970-01-01 00:00:00.000000 sorting.F90.o\n+?rw-r--r-- 0 0 0 2884 1970-01-01 00:00:00.000000 sys.F90.o\n+?rw-r--r-- 0 0 0 34788 1970-01-01 00:00:00.000000 vdwxc.F90.o\n+?rw-r--r-- 0 0 0 16352 1970-01-01 00:00:00.000000 vv_vdwxc.F90.o\n+?rw-r--r-- 0 0 0 5228 1970-01-01 00:00:00.000000 xc_hybrids.F90.o\n+?rw-r--r-- 0 0 0 41468 1970-01-01 00:00:00.000000 xc_xwpbe.F90.o\n+?rw-r--r-- 0 0 0 10180 1970-01-01 00:00:00.000000 xcmod.F90.o\n"}, {"source1": "alloc.F90.o", "source2": "alloc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 51792 (bytes into file)\n+ Start of section headers: 49380 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 16\n Section header string table index: 15\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,25 +1,25 @@\n-There are 16 section headers, starting at offset 0xca50:\n+There are 16 section headers, starting at offset 0xc0e4:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 009a48 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 00b5bc 0013e8 08 I 13 1 4\n- [ 3] .data PROGBITS 00000000 009a80 00002c 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 009aac 000014 00 WA 0 0 4\n- [ 5] .rodata.str1.4 PROGBITS 00000000 009aac 0001cd 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 009c7c 000044 00 A 0 0 4\n- [ 7] .data.rel PROGBITS 00000000 009cc0 00001c 00 WA 0 0 4\n- [ 8] .rel.data.rel REL 00000000 00c9a4 000010 08 I 13 7 4\n- [ 9] .data.rel.local PROGBITS 00000000 009cdc 000008 00 WA 0 0 4\n- [10] .rel.data.rel.local REL 00000000 00c9b4 000010 08 I 13 9 4\n- [11] .note.GNU-stack PROGBITS 00000000 009ce4 000000 00 0 0 1\n- [12] .ARM.attributes ARM_ATTRIBUTES 00000000 009ce4 000033 00 0 0 1\n- [13] .symtab SYMTAB 00000000 009d18 000f30 10 14 176 4\n- [14] .strtab STRTAB 00000000 00ac48 000972 00 0 0 1\n- [15] .shstrtab STRTAB 00000000 00c9c4 000089 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0092b4 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 00ac00 001438 08 I 13 1 4\n+ [ 3] .data PROGBITS 00000000 0092ec 00002c 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 009318 000014 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 009318 0001cd 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 0094e8 000044 00 A 0 0 4\n+ [ 7] .data.rel PROGBITS 00000000 00952c 00001c 00 WA 0 0 4\n+ [ 8] .rel.data.rel REL 00000000 00c038 000010 08 I 13 7 4\n+ [ 9] .data.rel.local PROGBITS 00000000 009548 000008 00 WA 0 0 4\n+ [10] .rel.data.rel.local REL 00000000 00c048 000010 08 I 13 9 4\n+ [11] .note.GNU-stack PROGBITS 00000000 009550 000000 00 0 0 1\n+ [12] .ARM.attributes ARM_ATTRIBUTES 00000000 009550 00002d 00 0 0 1\n+ [13] .symtab SYMTAB 00000000 009580 000cf0 10 14 138 4\n+ [14] .strtab STRTAB 00000000 00a270 00098d 00 0 0 1\n+ [15] .shstrtab STRTAB 00000000 00c058 000089 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,246 +1,210 @@\n \n-Symbol table '.symtab' contains 243 entries:\n+Symbol table '.symtab' contains 207 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 3: 00000000 0 NOTYPE LOCAL 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_gfortran_st_write_done\n+ 146: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_stop_string\n+ 147: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 148: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 149: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 150: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n+ 151: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n+ 152: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n+ 153: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 154: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 155: 00001249 236 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_dealloc_s1\n+ 156: 00001335 232 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_dealloc_l3\n+ 157: 0000141d 216 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_dealloc_l2\n+ 158: 000014f5 200 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_dealloc_l1\n+ 159: 000015bd 216 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_dealloc_z2\n+ 160: 00001695 204 FUNC GLOBAL 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00000000 0 NOTYPE GLOBAL DEFAULT UND memmove\n+ 175: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_uidiv\n+ 176: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idiv\n+ 177: 000026b1 2020 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_l3\n+ 178: 00002e95 1632 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_l2\n+ 179: 000034f5 1168 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_l1\n+ 180: 00003985 1312 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_z2\n+ 181: 00003ea5 1196 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_z1\n+ 182: 00004351 2452 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_d4\n+ 183: 00004ce5 1652 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_d3\n+ 184: 00005359 1296 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_d2\n+ 185: 00005869 1168 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_d1\n+ 186: 00005cf9 2448 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_r4\n+ 187: 00006689 2018 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_r3\n+ 188: 00006e6d 1632 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_r2\n+ 189: 000074cd 1164 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_r1\n+ 190: 00007959 1172 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_e1\n+ 191: 00007ded 2012 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_i3\n+ 192: 000085c9 1600 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_i2\n+ 193: 00008c09 1168 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_realloc_i1\n+ 194: 00009099 516 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_alloc_default\n+ 195: 0000929d 12 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_set_alloc_error_handler\n+ 196: 000092a9 12 FUNC GLOBAL DEFAULT 1 __gridxc_alloc_MOD_set_alloc_event_handler\n+ 197: 00000008 4 OBJECT GLOBAL HIDDEN 4 __gridxc_alloc_MOD_needs_dealloc\n+ 198: 0000000c 4 OBJECT GLOBAL HIDDEN 4 __gridxc_alloc_MOD_needs_copy\n+ 199: 00000004 4 OBJECT GLOBAL HIDDEN 4 __gridxc_alloc_MOD_needs_alloc\n+ 200: 00000010 4 OBJECT GLOBAL HIDDEN 4 __gridxc_alloc_MOD_ierr\n+ 201: 00000000 44 OBJECT GLOBAL HIDDEN 3 __gridxc_alloc_MOD_default\n+ 202: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_alloc_MOD_associated_array\n+ 203: 00000004 4 OBJECT GLOBAL HIDDEN 9 __gridxc_alloc_MOD_alloc_memory_event\n+ 204: 00000000 4 OBJECT GLOBAL HIDDEN 9 __gridxc_alloc_MOD_alloc_error_report\n+ 205: 00000000 28 OBJECT GLOBAL DEFAULT 7 __gridxc_alloc_MOD___vtab_gridxc_alloc_Allocdefaults\n+ 206: 00000018 44 OBJECT GLOBAL DEFAULT 6 __gridxc_alloc_MOD___def_init_gridxc_alloc_Allocdefaults\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,650 +1,660 @@\n \n-Relocation section '.rel.text' at offset 0xb5bc contains 637 entries:\n+Relocation section '.rel.text' at offset 0xac00 contains 647 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000068 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000070 0000b20a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-0000007e 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00000092 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000009c 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000000a2 0000b60a R_ARM_THM_CALL 00000000 free\n-000000a8 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-000000ce 0000b80a R_ARM_THM_CALL 00000000 _gfortran_stop_string\n-000000d2 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000000e0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000000e4 00000603 R_ARM_REL32 00000000 .LC0\n-000000e8 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000000ec 00000703 R_ARM_REL32 00000038 .LC1\n-000000f0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000001dc 00000203 R_ARM_REL32 00000000 .bss\n+00000068 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000070 00008c0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+0000007e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00000092 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000009c 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+000000a2 0000900a R_ARM_THM_CALL 00000000 free\n+000000a8 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000000ce 0000920a R_ARM_THM_CALL 00000000 _gfortran_stop_string\n+000000d2 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000000d8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000000dc 00000603 R_ARM_REL32 00000000 .LC0\n+000000e0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000000e4 00000703 R_ARM_REL32 00000038 .LC1\n+000000e8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000001cc 00000203 R_ARM_REL32 00000000 .bss\n+000001d0 00000203 R_ARM_REL32 00000000 .bss\n+000001d4 00000203 R_ARM_REL32 00000000 .bss\n+000001d8 00000203 R_ARM_REL32 00000000 .bss\n+000001dc 00000103 R_ARM_REL32 00000000 .data\n 000001e0 00000203 R_ARM_REL32 00000000 .bss\n-000001e4 00000203 R_ARM_REL32 00000000 .bss\n-000001e8 00000203 R_ARM_REL32 00000000 .bss\n-000001ec 00000103 R_ARM_REL32 00000000 .data\n-000001f0 00000203 R_ARM_REL32 00000000 .bss\n-000001f4 00000103 R_ARM_REL32 00000000 .data\n-000001f8 00000103 R_ARM_REL32 00000000 .data\n+000001e4 00000103 R_ARM_REL32 00000000 .data\n+000001e8 00000103 R_ARM_REL32 00000000 .data\n 000003a4 00000203 R_ARM_REL32 00000000 .bss\n 000003a8 00000203 R_ARM_REL32 00000000 .bss\n 000003ac 00000203 R_ARM_REL32 00000000 .bss\n 000003b0 00000203 R_ARM_REL32 00000000 .bss\n 000003b4 00000103 R_ARM_REL32 00000000 .data\n 000003b8 00000203 R_ARM_REL32 00000000 .bss\n 000003bc 00000203 R_ARM_REL32 00000000 .bss\n 000003c0 00000103 R_ARM_REL32 00000000 .data\n 000003c4 00000103 R_ARM_REL32 00000000 .data\n 000003c8 00000103 R_ARM_REL32 00000000 .data\n-00000620 00000203 R_ARM_REL32 00000000 .bss\n-00000624 00000203 R_ARM_REL32 00000000 .bss\n-00000628 00000203 R_ARM_REL32 00000000 .bss\n-0000062c 00000203 R_ARM_REL32 00000000 .bss\n-00000630 00000103 R_ARM_REL32 00000000 .data\n-00000634 00000203 R_ARM_REL32 00000000 .bss\n-00000638 00000203 R_ARM_REL32 00000000 .bss\n-0000063c 00000103 R_ARM_REL32 00000000 .data\n-00000640 00000103 R_ARM_REL32 00000000 .data\n-000009a4 00000203 R_ARM_REL32 00000000 .bss\n-000009a8 00000203 R_ARM_REL32 00000000 .bss\n-000009ac 00000203 R_ARM_REL32 00000000 .bss\n-000009b0 00000203 R_ARM_REL32 00000000 .bss\n-000009b4 00000103 R_ARM_REL32 00000000 .data\n-000009b8 00000103 R_ARM_REL32 00000000 .data\n-000009bc 00000203 R_ARM_REL32 00000000 .bss\n-000009c0 00000103 R_ARM_REL32 00000000 .data\n-00000a80 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000a8c 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000a98 0000bc0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00000a9e 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000aae 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000b0a 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000b16 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000b20 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000b2c 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000b32 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000b3e 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000b94 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000ba0 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000ba6 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000bb2 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000bd6 0000b60a R_ARM_THM_CALL 00000000 free\n-00000c3a 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000c44 0000bc0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00000c50 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000c5a 0000bc0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00000c66 0000bc0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00000c6c 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000c78 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000c98 0000b60a R_ARM_THM_CALL 00000000 free\n-00000cf8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000cfc 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000d00 00000203 R_ARM_REL32 00000000 .bss\n-00000d04 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d08 00000603 R_ARM_REL32 00000000 .LC0\n-00000d0c 00001603 R_ARM_REL32 00000044 .LC2\n-00000d10 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000d14 0000a903 R_ARM_REL32 00000000 .rodata\n-00000d18 00000603 R_ARM_REL32 00000000 .LC0\n-00000d1c 00001703 R_ARM_REL32 00000068 .LC4\n-00000d20 00001903 R_ARM_REL32 0000008c .LC7\n-00000d24 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000d28 0000a903 R_ARM_REL32 00000000 .rodata\n-00000d2c 00000603 R_ARM_REL32 00000000 .LC0\n-00000d30 00001c03 R_ARM_REL32 000000e0 .LC13\n-00000d34 00001d03 R_ARM_REL32 000000e4 .LC14\n-00000d38 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000d3c 0000a903 R_ARM_REL32 00000000 .rodata\n-00000d40 0000a903 R_ARM_REL32 00000000 .rodata\n-00000d44 00000603 R_ARM_REL32 00000000 .LC0\n-00000d48 00001e03 R_ARM_REL32 00000104 .LC16\n-00000d4c 00001f03 R_ARM_REL32 00000110 .LC17\n-00000d50 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000d54 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d58 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000d5c 0000a903 R_ARM_REL32 00000000 .rodata\n-00000d60 00001b03 R_ARM_REL32 000000c0 .LC12\n-00000d66 0000b60a R_ARM_THM_CALL 00000000 free\n-00000da2 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000dae 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000db8 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000dc4 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000dce 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000dd4 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000de0 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000e06 0000b60a R_ARM_THM_CALL 00000000 free\n-00000e32 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000e3e 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000e4a 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000e54 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000e5a 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000e66 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000e80 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000e90 00000603 R_ARM_REL32 00000000 .LC0\n-00000e94 00001703 R_ARM_REL32 00000068 .LC4\n-00000e98 00001803 R_ARM_REL32 0000007c .LC5\n-00000e9c 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000ea0 0000a903 R_ARM_REL32 00000000 .rodata\n-00000ea4 00000603 R_ARM_REL32 00000000 .LC0\n-00000ea8 00001a03 R_ARM_REL32 000000a4 .LC9\n-00000eac 00001803 R_ARM_REL32 0000007c .LC5\n-00000eb0 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00000eb4 0000a903 R_ARM_REL32 00000000 .rodata\n-00000f08 0000be0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000f16 0000b20a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-00000f24 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00000f40 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000f4e 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00000f60 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000f66 0000b60a R_ARM_THM_CALL 00000000 free\n-00000f86 0000b60a R_ARM_THM_CALL 00000000 free\n-00000fe0 0000b10a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000fec 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000ff6 0000b50a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000ffe 0000b70a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0000100a 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00001042 0000bd0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00001080 0000b20a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-0000108e 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000010a8 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000010ae 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000010c6 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000010cc 0000b60a R_ARM_THM_CALL 00000000 free\n-000010de 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-000010e8 0000c00a R_ARM_THM_CALL 00000000 memset\n-0000111a 0000b20a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-00001128 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00001146 0000b30a R_ARM_THM_CALL 00000000 malloc\n-0000115c 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000117a 0000b60a R_ARM_THM_CALL 00000000 free\n-00001182 0000b60a R_ARM_THM_CALL 00000000 free\n-0000119a 0000be0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000011a4 0000b20a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-000011b2 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000011ce 0000b40a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000011d4 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000011e8 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-000011f6 0000c00a R_ARM_THM_CALL 00000000 memset\n-00001202 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-00001210 0000c00a R_ARM_THM_CALL 00000000 memset\n-00001238 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001248 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000124c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001250 00000103 R_ARM_REL32 00000000 .data\n-00001254 00002603 R_ARM_REL32 00000118 .LC19\n-00001258 00002503 R_ARM_REL32 00000114 .LC18\n-0000125c 00000603 R_ARM_REL32 00000000 .LC0\n-00001260 00002a03 R_ARM_REL32 0000016c .LC23\n-00001264 00002b03 R_ARM_REL32 00000174 .LC24\n-00001268 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-0000126c 0000a903 R_ARM_REL32 00000000 .rodata\n-00001270 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00001274 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001278 00002503 R_ARM_REL32 00000114 .LC18\n-0000127c 00002803 R_ARM_REL32 0000013c .LC21\n-00001280 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001284 00002503 R_ARM_REL32 00000114 .LC18\n-00001288 00002703 R_ARM_REL32 00000128 .LC20\n-0000128c 00000103 R_ARM_REL32 00000000 .data\n-00001290 00002603 R_ARM_REL32 00000118 .LC19\n-00001294 00002503 R_ARM_REL32 00000114 .LC18\n-00001298 00002803 R_ARM_REL32 0000013c .LC21\n-0000129c 00002903 R_ARM_REL32 0000014c .LC22\n-0000131e 0000b60a R_ARM_THM_CALL 00000000 free\n-00001370 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001374 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001378 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000137c 00003103 R_ARM_REL32 00000198 .LC25\n-00001380 00000203 R_ARM_REL32 00000000 .bss\n-00001384 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001388 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001424 0000b60a R_ARM_THM_CALL 00000000 free\n-0000145c 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001460 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001464 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001468 00003403 R_ARM_REL32 0000019c .LC26\n-0000146c 00000203 R_ARM_REL32 00000000 .bss\n-00001470 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000014fe 0000b60a R_ARM_THM_CALL 00000000 free\n-00001536 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0000153c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001540 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001544 00003403 R_ARM_REL32 0000019c .LC26\n-00001548 00000203 R_ARM_REL32 00000000 .bss\n-0000154c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000015c8 0000b60a R_ARM_THM_CALL 00000000 free\n-00001600 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001604 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001608 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000160c 00003403 R_ARM_REL32 0000019c .LC26\n-00001610 00000203 R_ARM_REL32 00000000 .bss\n-00001614 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000016a2 0000b60a R_ARM_THM_CALL 00000000 free\n-000016da 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000016e0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000016e4 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000016e8 00003b03 R_ARM_REL32 000001a0 .LC27\n-000016ec 00000203 R_ARM_REL32 00000000 .bss\n-000016f0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001770 0000b60a R_ARM_THM_CALL 00000000 free\n-000017a8 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000017ac 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000017b0 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000017b4 00003b03 R_ARM_REL32 000001a0 .LC27\n-000017b8 00000203 R_ARM_REL32 00000000 .bss\n-000017bc 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001868 0000b60a R_ARM_THM_CALL 00000000 free\n-000018a0 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000018a4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000018a8 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000018ac 00003b03 R_ARM_REL32 000001a0 .LC27\n-000018b0 00000203 R_ARM_REL32 00000000 .bss\n-000018b4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001950 0000b60a R_ARM_THM_CALL 00000000 free\n-00001988 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0000198c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001990 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001994 00003b03 R_ARM_REL32 000001a0 .LC27\n-00001998 00000203 R_ARM_REL32 00000000 .bss\n-0000199c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001a2a 0000b60a R_ARM_THM_CALL 00000000 free\n-00001a62 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001a68 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001a6c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001a70 00003b03 R_ARM_REL32 000001a0 .LC27\n-00001a74 00000203 R_ARM_REL32 00000000 .bss\n-00001a78 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001af4 0000b60a R_ARM_THM_CALL 00000000 free\n-00001b2c 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001b30 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001b34 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001b38 00003b03 R_ARM_REL32 000001a0 .LC27\n-00001b3c 00000203 R_ARM_REL32 00000000 .bss\n-00001b40 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001bec 0000b60a R_ARM_THM_CALL 00000000 free\n-00001c24 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001c28 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001c2c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001c30 00004803 R_ARM_REL32 000001a4 .LC28\n-00001c34 00000203 R_ARM_REL32 00000000 .bss\n-00001c38 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001cd4 0000b60a R_ARM_THM_CALL 00000000 free\n-00001d0c 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001d10 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001d14 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001d18 00004803 R_ARM_REL32 000001a4 .LC28\n-00001d1c 00000203 R_ARM_REL32 00000000 .bss\n-00001d20 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001dae 0000b60a R_ARM_THM_CALL 00000000 free\n-00001de6 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001dec 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001df0 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001df4 00004803 R_ARM_REL32 000001a4 .LC28\n-00001df8 00000203 R_ARM_REL32 00000000 .bss\n-00001dfc 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001e78 0000b60a R_ARM_THM_CALL 00000000 free\n-00001eb0 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001eb4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001eb8 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001ebc 00004803 R_ARM_REL32 000001a4 .LC28\n-00001ec0 00000203 R_ARM_REL32 00000000 .bss\n-00001ec4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001f40 0000b60a R_ARM_THM_CALL 00000000 free\n-00001f78 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001f7c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001f80 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001f84 00005103 R_ARM_REL32 000001a8 .LC29\n-00001f88 00000203 R_ARM_REL32 00000000 .bss\n-00001f8c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002028 0000b60a R_ARM_THM_CALL 00000000 free\n-00002060 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002064 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002068 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000206c 00005103 R_ARM_REL32 000001a8 .LC29\n-00002070 00000203 R_ARM_REL32 00000000 .bss\n-00002074 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002102 0000b60a R_ARM_THM_CALL 00000000 free\n-0000213a 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002140 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002144 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002148 00005103 R_ARM_REL32 000001a8 .LC29\n-0000214c 00000203 R_ARM_REL32 00000000 .bss\n-00002150 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000021cc 0000b60a R_ARM_THM_CALL 00000000 free\n-00002204 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002208 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000220c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002210 00005103 R_ARM_REL32 000001a8 .LC29\n-00002214 00000203 R_ARM_REL32 00000000 .bss\n-00002218 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000023d0 0000b60a R_ARM_THM_CALL 00000000 free\n-00002454 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00002546 0000c00a R_ARM_THM_CALL 00000000 memset\n-000025a8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000025ac 00000203 R_ARM_REL32 00000000 .bss\n-000025b0 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000025b4 00000203 R_ARM_REL32 00000000 .bss\n-000025b8 00003103 R_ARM_REL32 00000198 .LC25\n-000025bc 00000203 R_ARM_REL32 00000000 .bss\n-000025c0 00000203 R_ARM_REL32 00000000 .bss\n-000025c4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000025c8 00000203 R_ARM_REL32 00000000 .bss\n-000025cc 00003103 R_ARM_REL32 00000198 .LC25\n-00002628 0000d40a R_ARM_THM_CALL 00000000 memmove\n-00002664 0000d40a R_ARM_THM_CALL 00000000 memmove\n-000026ce 0000b60a R_ARM_THM_CALL 00000000 free\n-0000273e 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00002752 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002778 00003103 R_ARM_REL32 00000198 .LC25\n-0000277c 00000203 R_ARM_REL32 00000000 .bss\n-00002a5a 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00002bd8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002bdc 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002be0 00000203 R_ARM_REL32 00000000 .bss\n-00002be4 00000203 R_ARM_REL32 00000000 .bss\n-00002be8 00000203 R_ARM_REL32 00000000 .bss\n-00002bec 00000203 R_ARM_REL32 00000000 .bss\n-00002bf0 00003403 R_ARM_REL32 0000019c .LC26\n-00002d24 0000b60a R_ARM_THM_CALL 00000000 free\n-00002e24 0000b60a R_ARM_THM_CALL 00000000 free\n-00002f6e 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002f98 00000203 R_ARM_REL32 00000000 .bss\n-00002f9c 00003403 R_ARM_REL32 0000019c .LC26\n-00002fa0 00000203 R_ARM_REL32 00000000 .bss\n-00002fa4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002fa8 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002fac 00003403 R_ARM_REL32 0000019c .LC26\n-00003208 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000033b8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000033bc 00000203 R_ARM_REL32 00000000 .bss\n-000033c0 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000033c4 00000203 R_ARM_REL32 00000000 .bss\n-000033c8 00000203 R_ARM_REL32 00000000 .bss\n-000033cc 00000203 R_ARM_REL32 00000000 .bss\n-000033d0 00003403 R_ARM_REL32 0000019c .LC26\n-000033d4 00000203 R_ARM_REL32 00000000 .bss\n-000034f8 0000b60a R_ARM_THM_CALL 00000000 free\n-000035dc 0000b60a R_ARM_THM_CALL 00000000 free\n-00003634 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00003660 00003403 R_ARM_REL32 0000019c .LC26\n-00003664 00000203 R_ARM_REL32 00000000 .bss\n-00003668 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000366c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003670 00003403 R_ARM_REL32 0000019c .LC26\n-00003826 0000b60a R_ARM_THM_CALL 00000000 free\n-000038b4 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00003a08 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003a0c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003a10 00000203 R_ARM_REL32 00000000 .bss\n-00003a14 00000203 R_ARM_REL32 00000000 .bss\n-00003a18 00003403 R_ARM_REL32 0000019c .LC26\n-00003a1c 00000203 R_ARM_REL32 00000000 .bss\n-00003a20 00000203 R_ARM_REL32 00000000 .bss\n-00003a24 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003a28 00000203 R_ARM_REL32 00000000 .bss\n-00003a2c 00003403 R_ARM_REL32 0000019c .LC26\n-00003af6 0000b60a R_ARM_THM_CALL 00000000 free\n-00003b5a 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00003b88 00003403 R_ARM_REL32 0000019c .LC26\n-00003b8c 00000203 R_ARM_REL32 00000000 .bss\n-00003d90 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00003f60 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003f64 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003f68 00000203 R_ARM_REL32 00000000 .bss\n-00003f6c 00000203 R_ARM_REL32 00000000 .bss\n-00003f70 00000203 R_ARM_REL32 00000000 .bss\n-00003f74 00000203 R_ARM_REL32 00000000 .bss\n-00003f78 00003b03 R_ARM_REL32 000001a0 .LC27\n-00003f7c 00000203 R_ARM_REL32 00000000 .bss\n-00003fda 0000b60a R_ARM_THM_CALL 00000000 free\n-000040a4 0000b60a R_ARM_THM_CALL 00000000 free\n-000040e4 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004100 00003b03 R_ARM_REL32 000001a0 .LC27\n-00004104 00000203 R_ARM_REL32 00000000 .bss\n-00004108 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000410c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004110 00003b03 R_ARM_REL32 000001a0 .LC27\n-000042ca 0000b60a R_ARM_THM_CALL 00000000 free\n-00004358 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000044b0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000044b4 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000044b8 00000203 R_ARM_REL32 00000000 .bss\n-000044bc 00000203 R_ARM_REL32 00000000 .bss\n-000044c0 00003b03 R_ARM_REL32 000001a0 .LC27\n-000044c4 00000203 R_ARM_REL32 00000000 .bss\n-000044c8 00000203 R_ARM_REL32 00000000 .bss\n-000044cc 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000044d0 00000203 R_ARM_REL32 00000000 .bss\n-000044d4 00003b03 R_ARM_REL32 000001a0 .LC27\n-000045ae 0000b60a R_ARM_THM_CALL 00000000 free\n-00004612 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004640 00003b03 R_ARM_REL32 000001a0 .LC27\n-00004644 00000203 R_ARM_REL32 00000000 .bss\n-000046d6 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-000049c0 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00004b08 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004b0c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004b10 00000203 R_ARM_REL32 00000000 .bss\n+000005f4 00000203 R_ARM_REL32 00000000 .bss\n+000005f8 00000203 R_ARM_REL32 00000000 .bss\n+000005fc 00000203 R_ARM_REL32 00000000 .bss\n+00000600 00000203 R_ARM_REL32 00000000 .bss\n+00000604 00000103 R_ARM_REL32 00000000 .data\n+00000608 00000203 R_ARM_REL32 00000000 .bss\n+0000060c 00000203 R_ARM_REL32 00000000 .bss\n+00000610 00000103 R_ARM_REL32 00000000 .data\n+00000614 00000103 R_ARM_REL32 00000000 .data\n+0000096c 00000203 R_ARM_REL32 00000000 .bss\n+00000970 00000203 R_ARM_REL32 00000000 .bss\n+00000974 00000203 R_ARM_REL32 00000000 .bss\n+00000978 00000203 R_ARM_REL32 00000000 .bss\n+0000097c 00000103 R_ARM_REL32 00000000 .data\n+00000980 00000103 R_ARM_REL32 00000000 .data\n+00000984 00000203 R_ARM_REL32 00000000 .bss\n+00000988 00000103 R_ARM_REL32 00000000 .data\n+00000a3e 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000a4a 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000a56 0000960a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000a5c 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000a6e 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000ad0 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000adc 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000ae6 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000af2 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000af8 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000b04 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000b5c 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000b68 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000b6e 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000b7a 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000b9c 0000900a R_ARM_THM_CALL 00000000 free\n+00000c0c 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000c16 0000960a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000c22 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000c2c 0000960a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000c38 0000960a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000c3e 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000c4a 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000c6c 0000900a R_ARM_THM_CALL 00000000 free\n+00000cb4 0000900a R_ARM_THM_CALL 00000000 free\n+00000cbc 0000900a R_ARM_THM_CALL 00000000 free\n+00000cee 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000cfa 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d06 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d10 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d16 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000d22 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000d60 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000d6c 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d76 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d82 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d8c 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000d92 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000d9e 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000db6 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000dbc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000dc0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000dc4 00000203 R_ARM_REL32 00000000 .bss\n+00000dc8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000dcc 00000603 R_ARM_REL32 00000000 .LC0\n+00000dd0 00001603 R_ARM_REL32 00000044 .LC2\n+00000dd4 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000dd8 00008303 R_ARM_REL32 00000000 .rodata\n+00000ddc 00000603 R_ARM_REL32 00000000 .LC0\n+00000de0 00001703 R_ARM_REL32 00000068 .LC4\n+00000de4 00001903 R_ARM_REL32 0000008c .LC7\n+00000de8 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000dec 00008303 R_ARM_REL32 00000000 .rodata\n+00000df0 00000603 R_ARM_REL32 00000000 .LC0\n+00000df4 00001c03 R_ARM_REL32 000000e0 .LC13\n+00000df8 00001d03 R_ARM_REL32 000000e4 .LC14\n+00000dfc 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000e00 00008303 R_ARM_REL32 00000000 .rodata\n+00000e04 00008303 R_ARM_REL32 00000000 .rodata\n+00000e08 00000603 R_ARM_REL32 00000000 .LC0\n+00000e0c 00001e03 R_ARM_REL32 00000104 .LC16\n+00000e10 00001f03 R_ARM_REL32 00000110 .LC17\n+00000e14 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000e18 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000e1c 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000e20 00008303 R_ARM_REL32 00000000 .rodata\n+00000e24 00001b03 R_ARM_REL32 000000c0 .LC12\n+00000e28 00000603 R_ARM_REL32 00000000 .LC0\n+00000e2c 00001a03 R_ARM_REL32 000000a4 .LC9\n+00000e30 00001803 R_ARM_REL32 0000007c .LC5\n+00000e34 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000e38 00008303 R_ARM_REL32 00000000 .rodata\n+00000e3c 00000603 R_ARM_REL32 00000000 .LC0\n+00000e40 00001703 R_ARM_REL32 00000068 .LC4\n+00000e44 00001803 R_ARM_REL32 0000007c .LC5\n+00000e48 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00000e4c 00008303 R_ARM_REL32 00000000 .rodata\n+00000ea0 0000980a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000eae 00008c0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+00000ebc 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00000ed8 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000ee4 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00000efa 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000f00 0000900a R_ARM_THM_CALL 00000000 free\n+00000f1c 0000900a R_ARM_THM_CALL 00000000 free\n+00000f7a 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000f88 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000f92 00008f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000f98 0000910a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000fa4 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000fda 0000970a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00001018 00008c0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+00001026 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00001040 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00001046 00008d0a R_ARM_THM_CALL 00000000 malloc\n+0000105e 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00001064 0000900a R_ARM_THM_CALL 00000000 free\n+00001084 0000900a R_ARM_THM_CALL 00000000 free\n+000010b6 00008c0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+000010c4 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000010e0 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000010fa 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00001108 0000990a R_ARM_THM_CALL 00000000 memcpy\n+00001114 00009a0a R_ARM_THM_CALL 00000000 memset\n+0000111c 0000900a R_ARM_THM_CALL 00000000 free\n+00001134 0000980a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001140 00008c0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+0000114e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00001168 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000116e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00001186 00008e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000118c 0000900a R_ARM_THM_CALL 00000000 free\n+000011a2 0000990a R_ARM_THM_CALL 00000000 memcpy\n+000011ae 00009a0a R_ARM_THM_CALL 00000000 memset\n+000011da 0000990a R_ARM_THM_CALL 00000000 memcpy\n+000011e6 00009a0a R_ARM_THM_CALL 00000000 memset\n+000011ec 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000011f0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000011f4 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000011f8 00000103 R_ARM_REL32 00000000 .data\n+000011fc 00002403 R_ARM_REL32 00000118 .LC19\n+00001200 00002303 R_ARM_REL32 00000114 .LC18\n+00001204 00000603 R_ARM_REL32 00000000 .LC0\n+00001208 00002803 R_ARM_REL32 0000016c .LC23\n+0000120c 00002903 R_ARM_REL32 00000174 .LC24\n+00001210 00008803 R_ARM_REL32 00000000 .data.rel.local\n+00001214 00008303 R_ARM_REL32 00000000 .rodata\n+00001218 00008803 R_ARM_REL32 00000000 .data.rel.local\n+0000121c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001220 00002303 R_ARM_REL32 00000114 .LC18\n+00001224 00002603 R_ARM_REL32 0000013c .LC21\n+00001228 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000122c 00002303 R_ARM_REL32 00000114 .LC18\n+00001230 00002503 R_ARM_REL32 00000128 .LC20\n+00001234 00000103 R_ARM_REL32 00000000 .data\n+00001238 00002403 R_ARM_REL32 00000118 .LC19\n+0000123c 00002303 R_ARM_REL32 00000114 .LC18\n+00001240 00002603 R_ARM_REL32 0000013c .LC21\n+00001244 00002703 R_ARM_REL32 0000014c .LC22\n+000012c4 0000900a R_ARM_THM_CALL 00000000 free\n+00001316 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000131c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001320 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001324 00002f03 R_ARM_REL32 00000198 .LC25\n+00001328 00000203 R_ARM_REL32 00000000 .bss\n+0000132c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001330 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000013ca 0000900a R_ARM_THM_CALL 00000000 free\n+00001402 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001408 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000140c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001410 00003203 R_ARM_REL32 0000019c .LC26\n+00001414 00000203 R_ARM_REL32 00000000 .bss\n+00001418 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000014a4 0000900a R_ARM_THM_CALL 00000000 free\n+000014dc 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000014e0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000014e4 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000014e8 00003203 R_ARM_REL32 0000019c .LC26\n+000014ec 00000203 R_ARM_REL32 00000000 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R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001750 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001754 00003903 R_ARM_REL32 000001a0 .LC27\n+00001758 00000203 R_ARM_REL32 00000000 .bss\n+0000175c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001806 0000900a R_ARM_THM_CALL 00000000 free\n+0000183e 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001844 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001848 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000184c 00003903 R_ARM_REL32 000001a0 .LC27\n+00001850 00000203 R_ARM_REL32 00000000 .bss\n+00001854 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000018ee 0000900a R_ARM_THM_CALL 00000000 free\n+00001926 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000192c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001930 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001934 00003903 R_ARM_REL32 000001a0 .LC27\n+00001938 00000203 R_ARM_REL32 00000000 .bss\n+0000193c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000019c8 0000900a R_ARM_THM_CALL 00000000 free\n+00001a00 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001a04 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001a08 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001a0c 00003903 R_ARM_REL32 000001a0 .LC27\n+00001a10 00000203 R_ARM_REL32 00000000 .bss\n+00001a14 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001a8e 0000900a R_ARM_THM_CALL 00000000 free\n+00001ac6 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001acc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001ad0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001ad4 00003903 R_ARM_REL32 000001a0 .LC27\n+00001ad8 00000203 R_ARM_REL32 00000000 .bss\n+00001adc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001b86 0000900a R_ARM_THM_CALL 00000000 free\n+00001bbe 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001bc4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001bc8 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001bcc 00004603 R_ARM_REL32 000001a4 .LC28\n+00001bd0 00000203 R_ARM_REL32 00000000 .bss\n+00001bd4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001c6e 0000900a R_ARM_THM_CALL 00000000 free\n+00001ca6 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001cac 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001cb0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001cb4 00004603 R_ARM_REL32 000001a4 .LC28\n+00001cb8 00000203 R_ARM_REL32 00000000 .bss\n+00001cbc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001d48 0000900a R_ARM_THM_CALL 00000000 free\n+00001d80 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001d84 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001d88 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001d8c 00004603 R_ARM_REL32 000001a4 .LC28\n+00001d90 00000203 R_ARM_REL32 00000000 .bss\n+00001d94 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001e0e 0000900a R_ARM_THM_CALL 00000000 free\n+00001e46 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001e4c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001e50 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001e54 00004603 R_ARM_REL32 000001a4 .LC28\n+00001e58 00000203 R_ARM_REL32 00000000 .bss\n+00001e5c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001ed6 0000900a R_ARM_THM_CALL 00000000 free\n+00001f0e 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001f14 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001f18 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001f1c 00004f03 R_ARM_REL32 000001a8 .LC29\n+00001f20 00000203 R_ARM_REL32 00000000 .bss\n+00001f24 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001fbe 0000900a R_ARM_THM_CALL 00000000 free\n+00001ff6 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001ffc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002000 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002004 00004f03 R_ARM_REL32 000001a8 .LC29\n+00002008 00000203 R_ARM_REL32 00000000 .bss\n+0000200c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002098 0000900a R_ARM_THM_CALL 00000000 free\n+000020d0 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000020d4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000020d8 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000020dc 00004f03 R_ARM_REL32 000001a8 .LC29\n+000020e0 00000203 R_ARM_REL32 00000000 .bss\n+000020e4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000215e 0000900a R_ARM_THM_CALL 00000000 free\n+00002196 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000219c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000021a0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000021a4 00004f03 R_ARM_REL32 000001a8 .LC29\n+000021a8 00000203 R_ARM_REL32 00000000 .bss\n+000021ac 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002352 0000900a R_ARM_THM_CALL 00000000 free\n+000023d4 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000024bc 00009a0a R_ARM_THM_CALL 00000000 memset\n+00002558 0000ae0a R_ARM_THM_CALL 00000000 memmove\n+00002594 0000ae0a R_ARM_THM_CALL 00000000 memmove\n+000025fe 0000900a R_ARM_THM_CALL 00000000 free\n+00002662 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00002676 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002680 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002684 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002688 00000203 R_ARM_REL32 00000000 .bss\n+0000268c 00000203 R_ARM_REL32 00000000 .bss\n+00002690 00002f03 R_ARM_REL32 00000198 .LC25\n+00002694 00000203 R_ARM_REL32 00000000 .bss\n+00002698 00000203 R_ARM_REL32 00000000 .bss\n+0000269c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000026a0 00000203 R_ARM_REL32 00000000 .bss\n+000026a4 00002f03 R_ARM_REL32 00000198 .LC25\n+000026a8 00002f03 R_ARM_REL32 00000198 .LC25\n+000026ac 00000203 R_ARM_REL32 00000000 .bss\n+000028f4 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000292c 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00002976 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00002c0e 0000900a R_ARM_THM_CALL 00000000 free\n+00002d08 0000900a R_ARM_THM_CALL 00000000 free\n+00002e52 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002e64 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e68 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002e6c 00000203 R_ARM_REL32 00000000 .bss\n+00002e70 00000203 R_ARM_REL32 00000000 .bss\n+00002e74 00000203 R_ARM_REL32 00000000 .bss\n+00002e78 00000203 R_ARM_REL32 00000000 .bss\n+00002e7c 00003203 R_ARM_REL32 0000019c .LC26\n+00002e80 00000203 R_ARM_REL32 00000000 .bss\n+00002e84 00003203 R_ARM_REL32 0000019c .LC26\n+00002e88 00000203 R_ARM_REL32 00000000 .bss\n+00002e8c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e90 00003203 R_ARM_REL32 0000019c .LC26\n+000030a6 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000030ce 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00003380 0000900a R_ARM_THM_CALL 00000000 free\n+0000345e 0000900a R_ARM_THM_CALL 00000000 free\n+000034b2 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000034c4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000034c8 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000034cc 00000203 R_ARM_REL32 00000000 .bss\n+000034d0 00000203 R_ARM_REL32 00000000 .bss\n+000034d4 00000203 R_ARM_REL32 00000000 .bss\n+000034d8 00000203 R_ARM_REL32 00000000 .bss\n+000034dc 00003203 R_ARM_REL32 0000019c .LC26\n+000034e0 00000203 R_ARM_REL32 00000000 .bss\n+000034e4 00003203 R_ARM_REL32 0000019c .LC26\n+000034e8 00000203 R_ARM_REL32 00000000 .bss\n+000034ec 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000034f0 00003203 R_ARM_REL32 0000019c .LC26\n+0000368c 0000900a R_ARM_THM_CALL 00000000 free\n+0000370a 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000038e8 0000900a R_ARM_THM_CALL 00000000 free\n+00003942 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003954 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003958 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000395c 00000203 R_ARM_REL32 00000000 .bss\n+00003960 00000203 R_ARM_REL32 00000000 .bss\n+00003964 00003203 R_ARM_REL32 0000019c .LC26\n+00003968 00000203 R_ARM_REL32 00000000 .bss\n+0000396c 00000203 R_ARM_REL32 00000000 .bss\n+00003970 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003974 00000203 R_ARM_REL32 00000000 .bss\n+00003978 00003203 R_ARM_REL32 0000019c .LC26\n+0000397c 00003203 R_ARM_REL32 0000019c .LC26\n+00003980 00000203 R_ARM_REL32 00000000 .bss\n+00003b46 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003b6c 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00003d7a 0000900a R_ARM_THM_CALL 00000000 free\n+00003e30 0000900a R_ARM_THM_CALL 00000000 free\n+00003e70 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003e74 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003e78 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003e7c 00000203 R_ARM_REL32 00000000 .bss\n+00003e80 00000203 R_ARM_REL32 00000000 .bss\n+00003e84 00000203 R_ARM_REL32 00000000 .bss\n+00003e88 00000203 R_ARM_REL32 00000000 .bss\n+00003e8c 00003903 R_ARM_REL32 000001a0 .LC27\n+00003e90 00000203 R_ARM_REL32 00000000 .bss\n+00003e94 00003903 R_ARM_REL32 000001a0 .LC27\n+00003e98 00000203 R_ARM_REL32 00000000 .bss\n+00003e9c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003ea0 00003903 R_ARM_REL32 000001a0 .LC27\n+00004040 0000900a R_ARM_THM_CALL 00000000 free\n+000040be 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000042b4 0000900a R_ARM_THM_CALL 00000000 free\n+0000430e 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004320 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004324 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004328 00000203 R_ARM_REL32 00000000 .bss\n+0000432c 00000203 R_ARM_REL32 00000000 .bss\n+00004330 00003903 R_ARM_REL32 000001a0 .LC27\n+00004334 00000203 R_ARM_REL32 00000000 .bss\n+00004338 00000203 R_ARM_REL32 00000000 .bss\n+0000433c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004340 00000203 R_ARM_REL32 00000000 .bss\n+00004344 00003903 R_ARM_REL32 000001a0 .LC27\n+00004348 00003903 R_ARM_REL32 000001a0 .LC27\n+0000434c 00000203 R_ARM_REL32 00000000 .bss\n+000043da 0000990a R_ARM_THM_CALL 00000000 memcpy\n+000045fa 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000462c 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00004666 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000046be 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000049d8 0000900a R_ARM_THM_CALL 00000000 free\n+00004ae0 0000900a R_ARM_THM_CALL 00000000 free\n+00004af8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004afc 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004b00 00000203 R_ARM_REL32 00000000 .bss\n+00004b04 00000203 R_ARM_REL32 00000000 .bss\n+00004b08 00000203 R_ARM_REL32 00000000 .bss\n+00004b0c 00000203 R_ARM_REL32 00000000 .bss\n+00004b10 00003903 R_ARM_REL32 000001a0 .LC27\n 00004b14 00000203 R_ARM_REL32 00000000 .bss\n-00004b18 00000203 R_ARM_REL32 00000000 .bss\n+00004b18 00003903 R_ARM_REL32 000001a0 .LC27\n 00004b1c 00000203 R_ARM_REL32 00000000 .bss\n-00004b20 00003b03 R_ARM_REL32 000001a0 .LC27\n-00004d14 0000b60a R_ARM_THM_CALL 00000000 free\n-00004e26 0000b60a R_ARM_THM_CALL 00000000 free\n-00004fe8 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00005010 00000203 R_ARM_REL32 00000000 .bss\n-00005014 00003b03 R_ARM_REL32 000001a0 .LC27\n-00005018 00000203 R_ARM_REL32 00000000 .bss\n-0000501c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005020 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005024 00003b03 R_ARM_REL32 000001a0 .LC27\n-000052cc 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00005460 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005464 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005468 00000203 R_ARM_REL32 00000000 .bss\n-0000546c 00000203 R_ARM_REL32 00000000 .bss\n-00005470 00000203 R_ARM_REL32 00000000 .bss\n-00005474 00000203 R_ARM_REL32 00000000 .bss\n-00005478 00003b03 R_ARM_REL32 000001a0 .LC27\n-000055b6 0000b60a R_ARM_THM_CALL 00000000 free\n-0000569c 0000b60a R_ARM_THM_CALL 00000000 free\n-000056ba 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000056d8 00000203 R_ARM_REL32 00000000 .bss\n-000056dc 00003b03 R_ARM_REL32 000001a0 .LC27\n-000056e0 00000203 R_ARM_REL32 00000000 .bss\n-000056e4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000056e8 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000056ec 00003b03 R_ARM_REL32 000001a0 .LC27\n-000058f0 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00005aa8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005aac 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005ab0 00000203 R_ARM_REL32 00000000 .bss\n-00005ab4 00000203 R_ARM_REL32 00000000 .bss\n-00005ab8 00000203 R_ARM_REL32 00000000 .bss\n-00005abc 00000203 R_ARM_REL32 00000000 .bss\n-00005ac0 00003b03 R_ARM_REL32 000001a0 .LC27\n-00005ac4 00000203 R_ARM_REL32 00000000 .bss\n-00005b20 0000b60a R_ARM_THM_CALL 00000000 free\n-00005be6 0000b60a R_ARM_THM_CALL 00000000 free\n-00005c26 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00005c48 00003b03 R_ARM_REL32 000001a0 .LC27\n-00005c4c 00000203 R_ARM_REL32 00000000 .bss\n-00005c50 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005c54 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005c58 00003b03 R_ARM_REL32 000001a0 .LC27\n-00005e0e 0000b60a R_ARM_THM_CALL 00000000 free\n-00005e9c 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00005ff0 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005ff4 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005ff8 00000203 R_ARM_REL32 00000000 .bss\n-00005ffc 00000203 R_ARM_REL32 00000000 .bss\n-00006000 00003b03 R_ARM_REL32 000001a0 .LC27\n-00006004 00000203 R_ARM_REL32 00000000 .bss\n-00006008 00000203 R_ARM_REL32 00000000 .bss\n-0000600c 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00006010 00000203 R_ARM_REL32 00000000 .bss\n-00006014 00003b03 R_ARM_REL32 000001a0 .LC27\n-000060dc 0000b60a R_ARM_THM_CALL 00000000 free\n-00006140 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00006168 00003b03 R_ARM_REL32 000001a0 .LC27\n-0000616c 00000203 R_ARM_REL32 00000000 .bss\n-000061fe 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-000064e2 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00006618 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000661c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00006620 00000203 R_ARM_REL32 00000000 .bss\n-00006624 00000203 R_ARM_REL32 00000000 .bss\n-00006628 00000203 R_ARM_REL32 00000000 .bss\n-0000662c 00000203 R_ARM_REL32 00000000 .bss\n-00006630 00004803 R_ARM_REL32 000001a4 .LC28\n-0000682e 0000b60a R_ARM_THM_CALL 00000000 free\n-00006944 0000b60a R_ARM_THM_CALL 00000000 free\n-00006b02 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00006b28 00000203 R_ARM_REL32 00000000 .bss\n-00006b2c 00004803 R_ARM_REL32 000001a4 .LC28\n-00006b30 00000203 R_ARM_REL32 00000000 .bss\n-00006b34 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00006b38 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00006b3c 00004803 R_ARM_REL32 000001a4 .LC28\n-00006e1a 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00006f98 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00006f9c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00006fa0 00000203 R_ARM_REL32 00000000 .bss\n-00006fa4 00000203 R_ARM_REL32 00000000 .bss\n-00006fa8 00000203 R_ARM_REL32 00000000 .bss\n-00006fac 00000203 R_ARM_REL32 00000000 .bss\n-00006fb0 00004803 R_ARM_REL32 000001a4 .LC28\n-000070e4 0000b60a R_ARM_THM_CALL 00000000 free\n-000071e4 0000b60a R_ARM_THM_CALL 00000000 free\n-0000732e 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00007358 00000203 R_ARM_REL32 00000000 .bss\n-0000735c 00004803 R_ARM_REL32 000001a4 .LC28\n-00007360 00000203 R_ARM_REL32 00000000 .bss\n-00007364 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00007368 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000736c 00004803 R_ARM_REL32 000001a4 .LC28\n-000075c8 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00007778 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000777c 00000203 R_ARM_REL32 00000000 .bss\n-00007780 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00007784 00000203 R_ARM_REL32 00000000 .bss\n-00007788 00000203 R_ARM_REL32 00000000 .bss\n-0000778c 00000203 R_ARM_REL32 00000000 .bss\n-00007790 00004803 R_ARM_REL32 000001a4 .LC28\n-00007794 00000203 R_ARM_REL32 00000000 .bss\n-000078b8 0000b60a R_ARM_THM_CALL 00000000 free\n-0000799c 0000b60a R_ARM_THM_CALL 00000000 free\n-000079f4 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00007a20 00004803 R_ARM_REL32 000001a4 .LC28\n-00007a24 00000203 R_ARM_REL32 00000000 .bss\n-00007a28 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00007a2c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00007a30 00004803 R_ARM_REL32 000001a4 .LC28\n-00007be6 0000b60a R_ARM_THM_CALL 00000000 free\n-00007c74 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00007dc8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00007dcc 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004b20 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004b24 00003903 R_ARM_REL32 000001a0 .LC27\n+00004cda 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004ef0 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00004f28 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00004f76 00008d0a R_ARM_THM_CALL 00000000 malloc\n+0000522a 0000900a R_ARM_THM_CALL 00000000 free\n+000052fe 0000900a R_ARM_THM_CALL 00000000 free\n+0000531c 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005328 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000532c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00005330 00000203 R_ARM_REL32 00000000 .bss\n+00005334 00000203 R_ARM_REL32 00000000 .bss\n+00005338 00000203 R_ARM_REL32 00000000 .bss\n+0000533c 00000203 R_ARM_REL32 00000000 .bss\n+00005340 00003903 R_ARM_REL32 000001a0 .LC27\n+00005344 00000203 R_ARM_REL32 00000000 .bss\n+00005348 00003903 R_ARM_REL32 000001a0 .LC27\n+0000534c 00000203 R_ARM_REL32 00000000 .bss\n+00005350 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005354 00003903 R_ARM_REL32 000001a0 .LC27\n+0000551a 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00005540 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00005742 0000900a R_ARM_THM_CALL 00000000 free\n+000057f4 0000900a R_ARM_THM_CALL 00000000 free\n+00005834 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005838 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000583c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00005840 00000203 R_ARM_REL32 00000000 .bss\n+00005844 00000203 R_ARM_REL32 00000000 .bss\n+00005848 00000203 R_ARM_REL32 00000000 .bss\n+0000584c 00000203 R_ARM_REL32 00000000 .bss\n+00005850 00003903 R_ARM_REL32 000001a0 .LC27\n+00005854 00000203 R_ARM_REL32 00000000 .bss\n+00005858 00003903 R_ARM_REL32 000001a0 .LC27\n+0000585c 00000203 R_ARM_REL32 00000000 .bss\n+00005860 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005864 00003903 R_ARM_REL32 000001a0 .LC27\n+00005a00 0000900a R_ARM_THM_CALL 00000000 free\n+00005a7e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00005c5e 0000900a R_ARM_THM_CALL 00000000 free\n+00005cb8 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005cc8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005ccc 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00005cd0 00000203 R_ARM_REL32 00000000 .bss\n+00005cd4 00000203 R_ARM_REL32 00000000 .bss\n+00005cd8 00003903 R_ARM_REL32 000001a0 .LC27\n+00005cdc 00000203 R_ARM_REL32 00000000 .bss\n+00005ce0 00000203 R_ARM_REL32 00000000 .bss\n+00005ce4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005ce8 00000203 R_ARM_REL32 00000000 .bss\n+00005cec 00003903 R_ARM_REL32 000001a0 .LC27\n+00005cf0 00003903 R_ARM_REL32 000001a0 .LC27\n+00005cf4 00000203 R_ARM_REL32 00000000 .bss\n+00005d82 0000990a R_ARM_THM_CALL 00000000 memcpy\n+00005fa2 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00005fd4 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000600e 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00006066 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00006386 0000900a R_ARM_THM_CALL 00000000 free\n+0000648e 0000900a R_ARM_THM_CALL 00000000 free\n+000064a0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000064a4 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000064a8 00000203 R_ARM_REL32 00000000 .bss\n+000064ac 00000203 R_ARM_REL32 00000000 .bss\n+000064b0 00000203 R_ARM_REL32 00000000 .bss\n+000064b4 00000203 R_ARM_REL32 00000000 .bss\n+000064b8 00004603 R_ARM_REL32 000001a4 .LC28\n+000064bc 00000203 R_ARM_REL32 00000000 .bss\n+000064c0 00004603 R_ARM_REL32 000001a4 .LC28\n+000064c4 00000203 R_ARM_REL32 00000000 .bss\n+000064c8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000064cc 00004603 R_ARM_REL32 000001a4 .LC28\n+0000667e 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000068c0 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000068f8 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00006942 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00006be2 0000900a R_ARM_THM_CALL 00000000 free\n+00006cdc 0000900a R_ARM_THM_CALL 00000000 free\n+00006d8c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00006d90 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00006d94 00000203 R_ARM_REL32 00000000 .bss\n+00006d98 00000203 R_ARM_REL32 00000000 .bss\n+00006d9c 00000203 R_ARM_REL32 00000000 .bss\n+00006da0 00000203 R_ARM_REL32 00000000 .bss\n+00006da4 00004603 R_ARM_REL32 000001a4 .LC28\n+00006da8 00000203 R_ARM_REL32 00000000 .bss\n+00006dac 00004603 R_ARM_REL32 000001a4 .LC28\n+00006db0 00000203 R_ARM_REL32 00000000 .bss\n+00006db4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00006db8 00004603 R_ARM_REL32 000001a4 .LC28\n+00006e5a 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000707e 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000070a6 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00007358 0000900a R_ARM_THM_CALL 00000000 free\n+00007436 0000900a R_ARM_THM_CALL 00000000 free\n+0000748a 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000749c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000074a0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000074a4 00000203 R_ARM_REL32 00000000 .bss\n+000074a8 00000203 R_ARM_REL32 00000000 .bss\n+000074ac 00000203 R_ARM_REL32 00000000 .bss\n+000074b0 00000203 R_ARM_REL32 00000000 .bss\n+000074b4 00004603 R_ARM_REL32 000001a4 .LC28\n+000074b8 00000203 R_ARM_REL32 00000000 .bss\n+000074bc 00004603 R_ARM_REL32 000001a4 .LC28\n+000074c0 00000203 R_ARM_REL32 00000000 .bss\n+000074c4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000074c8 00004603 R_ARM_REL32 000001a4 .LC28\n+00007664 0000900a R_ARM_THM_CALL 00000000 free\n+000076e2 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000078bc 0000900a R_ARM_THM_CALL 00000000 free\n+00007916 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00007928 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000792c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00007930 00000203 R_ARM_REL32 00000000 .bss\n+00007934 00000203 R_ARM_REL32 00000000 .bss\n+00007938 00004603 R_ARM_REL32 000001a4 .LC28\n+0000793c 00000203 R_ARM_REL32 00000000 .bss\n+00007940 00000203 R_ARM_REL32 00000000 .bss\n+00007944 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00007948 00000203 R_ARM_REL32 00000000 .bss\n+0000794c 00004603 R_ARM_REL32 000001a4 .LC28\n+00007950 00004603 R_ARM_REL32 000001a4 .LC28\n+00007954 00000203 R_ARM_REL32 00000000 .bss\n+00007af0 0000900a R_ARM_THM_CALL 00000000 free\n+00007b6e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00007d50 0000900a R_ARM_THM_CALL 00000000 free\n+00007daa 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00007dbc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00007dc0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00007dc4 00000203 R_ARM_REL32 00000000 .bss\n+00007dc8 00000203 R_ARM_REL32 00000000 .bss\n+00007dcc 00004f03 R_ARM_REL32 000001a8 .LC29\n 00007dd0 00000203 R_ARM_REL32 00000000 .bss\n 00007dd4 00000203 R_ARM_REL32 00000000 .bss\n-00007dd8 00004803 R_ARM_REL32 000001a4 .LC28\n+00007dd8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00007ddc 00000203 R_ARM_REL32 00000000 .bss\n-00007de0 00000203 R_ARM_REL32 00000000 .bss\n-00007de4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00007de0 00004f03 R_ARM_REL32 000001a8 .LC29\n+00007de4 00004f03 R_ARM_REL32 000001a8 .LC29\n 00007de8 00000203 R_ARM_REL32 00000000 .bss\n-00007dec 00004803 R_ARM_REL32 000001a4 .LC28\n-00007eb2 0000b60a R_ARM_THM_CALL 00000000 free\n-00007f16 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00007f40 00004803 R_ARM_REL32 000001a4 .LC28\n-00007f44 00000203 R_ARM_REL32 00000000 .bss\n-000080fa 0000b60a R_ARM_THM_CALL 00000000 free\n-00008188 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000082d8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000082dc 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000082e0 00000203 R_ARM_REL32 00000000 .bss\n-000082e4 00000203 R_ARM_REL32 00000000 .bss\n-000082e8 00005103 R_ARM_REL32 000001a8 .LC29\n-000082ec 00000203 R_ARM_REL32 00000000 .bss\n-000082f0 00000203 R_ARM_REL32 00000000 .bss\n-000082f4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000082f8 00000203 R_ARM_REL32 00000000 .bss\n-000082fc 00005103 R_ARM_REL32 000001a8 .LC29\n-000083c6 0000b60a R_ARM_THM_CALL 00000000 free\n-0000842a 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00008458 00005103 R_ARM_REL32 000001a8 .LC29\n-0000845c 00000203 R_ARM_REL32 00000000 .bss\n-00008738 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000088a8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000088ac 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000088b0 00000203 R_ARM_REL32 00000000 .bss\n-000088b4 00000203 R_ARM_REL32 00000000 .bss\n-000088b8 00000203 R_ARM_REL32 00000000 .bss\n-000088bc 00000203 R_ARM_REL32 00000000 .bss\n-000088c0 00005103 R_ARM_REL32 000001a8 .LC29\n-00008a5a 0000b60a R_ARM_THM_CALL 00000000 free\n-00008b5a 0000b60a R_ARM_THM_CALL 00000000 free\n-00008c2e 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00008c58 00000203 R_ARM_REL32 00000000 .bss\n-00008c5c 00005103 R_ARM_REL32 000001a8 .LC29\n-00008c60 00000203 R_ARM_REL32 00000000 .bss\n-00008c64 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008c68 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00008c6c 00005103 R_ARM_REL32 000001a8 .LC29\n-00008eb8 0000b30a R_ARM_THM_CALL 00000000 malloc\n-00009058 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000905c 00000203 R_ARM_REL32 00000000 .bss\n-00009060 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00009064 00000203 R_ARM_REL32 00000000 .bss\n-00009068 00000203 R_ARM_REL32 00000000 .bss\n-0000906c 00000203 R_ARM_REL32 00000000 .bss\n-00009070 00005103 R_ARM_REL32 000001a8 .LC29\n+0000802c 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00008064 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000080ae 00008d0a R_ARM_THM_CALL 00000000 malloc\n+000083b0 0000900a R_ARM_THM_CALL 00000000 free\n+000084aa 0000900a R_ARM_THM_CALL 00000000 free\n+00008588 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00008598 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000859c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000085a0 00000203 R_ARM_REL32 00000000 .bss\n+000085a4 00000203 R_ARM_REL32 00000000 .bss\n+000085a8 00000203 R_ARM_REL32 00000000 .bss\n+000085ac 00000203 R_ARM_REL32 00000000 .bss\n+000085b0 00004f03 R_ARM_REL32 000001a8 .LC29\n+000085b4 00000203 R_ARM_REL32 00000000 .bss\n+000085b8 00004f03 R_ARM_REL32 000001a8 .LC29\n+000085bc 00000203 R_ARM_REL32 00000000 .bss\n+000085c0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000085c4 00004f03 R_ARM_REL32 000001a8 .LC29\n+000087ca 0000b00a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000087f8 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00008a96 0000900a R_ARM_THM_CALL 00000000 free\n+00008b74 0000900a R_ARM_THM_CALL 00000000 free\n+00008bc8 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00008bd8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00008bdc 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00008be0 00000203 R_ARM_REL32 00000000 .bss\n+00008be4 00000203 R_ARM_REL32 00000000 .bss\n+00008be8 00000203 R_ARM_REL32 00000000 .bss\n+00008bec 00000203 R_ARM_REL32 00000000 .bss\n+00008bf0 00004f03 R_ARM_REL32 000001a8 .LC29\n+00008bf4 00000203 R_ARM_REL32 00000000 .bss\n+00008bf8 00004f03 R_ARM_REL32 000001a8 .LC29\n+00008bfc 00000203 R_ARM_REL32 00000000 .bss\n+00008c00 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00008c04 00004f03 R_ARM_REL32 000001a8 .LC29\n+00008da0 0000900a R_ARM_THM_CALL 00000000 free\n+00008e1e 00008d0a R_ARM_THM_CALL 00000000 malloc\n+00008ffc 0000900a R_ARM_THM_CALL 00000000 free\n+00009056 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00009068 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000906c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00009070 00000203 R_ARM_REL32 00000000 .bss\n 00009074 00000203 R_ARM_REL32 00000000 .bss\n-0000919a 0000b60a R_ARM_THM_CALL 00000000 free\n-0000927e 0000b60a R_ARM_THM_CALL 00000000 free\n-000092d8 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00009300 00005103 R_ARM_REL32 000001a8 .LC29\n-00009304 00000203 R_ARM_REL32 00000000 .bss\n-00009308 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000930c 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00009310 00005103 R_ARM_REL32 000001a8 .LC29\n-000094c6 0000b60a R_ARM_THM_CALL 00000000 free\n-00009554 0000b30a R_ARM_THM_CALL 00000000 malloc\n-000096a8 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000096ac 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000096b0 00000203 R_ARM_REL32 00000000 .bss\n-000096b4 00000203 R_ARM_REL32 00000000 .bss\n-000096b8 00005103 R_ARM_REL32 000001a8 .LC29\n-000096bc 00000203 R_ARM_REL32 00000000 .bss\n-000096c0 00000203 R_ARM_REL32 00000000 .bss\n-000096c4 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000096c8 00000203 R_ARM_REL32 00000000 .bss\n-000096cc 00005103 R_ARM_REL32 000001a8 .LC29\n-00009796 0000b60a R_ARM_THM_CALL 00000000 free\n-000097fa 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00009828 00005103 R_ARM_REL32 000001a8 .LC29\n-0000982c 00000203 R_ARM_REL32 00000000 .bss\n-0000999c 0000bf0a R_ARM_THM_CALL 00000000 memcpy\n-000099ac 0000c00a R_ARM_THM_CALL 00000000 memset\n-000099f6 0000b90a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000099fc 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00009a00 0000bb1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00009a04 0000a203 R_ARM_REL32 000001ac .LC30\n-00009a08 00000103 R_ARM_REL32 00000000 .data\n-00009a0c 00000103 R_ARM_REL32 00000000 .data\n-00009a10 00000103 R_ARM_REL32 00000000 .data\n-00009a14 00000103 R_ARM_REL32 00000000 .data\n-00009a18 00000103 R_ARM_REL32 00000000 .data\n-00009a1c 00000103 R_ARM_REL32 00000000 .data\n-00009a20 00000103 R_ARM_REL32 00000000 .data\n-00009a24 0000ba19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00009a28 00000103 R_ARM_REL32 00000000 .data\n-00009a2c 0000a203 R_ARM_REL32 000001ac .LC30\n-00009a38 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00009a44 0000ae03 R_ARM_REL32 00000000 .data.rel.local\n-00001114 0000b61e R_ARM_THM_JUMP24 00000000 free\n+00009078 00004f03 R_ARM_REL32 000001a8 .LC29\n+0000907c 00000203 R_ARM_REL32 00000000 .bss\n+00009080 00000203 R_ARM_REL32 00000000 .bss\n+00009084 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00009088 00000203 R_ARM_REL32 00000000 .bss\n+0000908c 00004f03 R_ARM_REL32 000001a8 .LC29\n+00009090 00004f03 R_ARM_REL32 000001a8 .LC29\n+00009094 00000203 R_ARM_REL32 00000000 .bss\n+00009200 0000990a R_ARM_THM_CALL 00000000 memcpy\n+00009210 00009a0a R_ARM_THM_CALL 00000000 memset\n+0000925a 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00009268 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000926c 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00009270 00007c03 R_ARM_REL32 000001ac .LC30\n+00009274 00000103 R_ARM_REL32 00000000 .data\n+00009278 00000103 R_ARM_REL32 00000000 .data\n+0000927c 00000103 R_ARM_REL32 00000000 .data\n+00009280 00000103 R_ARM_REL32 00000000 .data\n+00009284 00000103 R_ARM_REL32 00000000 .data\n+00009288 00000103 R_ARM_REL32 00000000 .data\n+0000928c 00000103 R_ARM_REL32 00000000 .data\n+00009290 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00009294 00000103 R_ARM_REL32 00000000 .data\n+00009298 00007c03 R_ARM_REL32 000001ac .LC30\n+000092a4 00008803 R_ARM_REL32 00000000 .data.rel.local\n+000092b0 00008803 R_ARM_REL32 00000000 .data.rel.local\n+000010b0 0000901e R_ARM_THM_JUMP24 00000000 free\n \n-Relocation section '.rel.data.rel' at offset 0xc9a4 contains 2 entries:\n+Relocation section '.rel.data.rel' at offset 0xc038 contains 2 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000000c 0000f202 R_ARM_ABS32 00000018 __gridxc_alloc_MOD___def_init_gridxc_alloc_Allocdefaults\n-00000010 0000b002 R_ARM_ABS32 00000001 __gridxc_alloc_MOD___copy_gridxc_alloc_Allocdefaults\n+0000000c 0000ce02 R_ARM_ABS32 00000018 __gridxc_alloc_MOD___def_init_gridxc_alloc_Allocdefaults\n+00000010 00008a02 R_ARM_ABS32 00000001 __gridxc_alloc_MOD___copy_gridxc_alloc_Allocdefaults\n \n-Relocation section '.rel.data.rel.local' at offset 0xc9b4 contains 2 entries:\n+Relocation section '.rel.data.rel.local' at offset 0xc048 contains 2 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000000 00000802 R_ARM_ABS32 00000029 __gridxc_alloc_MOD_dummy_alloc_error_report\n 00000004 00000402 R_ARM_ABS32 00000025 __gridxc_alloc_MOD_dummy_alloc_memory_event\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,25 +1,19 @@\n-SF:FAFXF\n-2FSFAFXF\n-:FSFAFXF\n-\"%I{D%HyDxD\n-SFJFAFXF\n-SF2FAFXF\n-CFJF9F0F\n-K=h F{D6h*F1F[h\n-FRF{DAF F\n-dAhi1F;j\"F&D\n-(0|a|k;b\n-0{bzK{D[h\n-0{b{K{D[h\n-0{bzK{D[h\n-(0|a|k;b\n-0{bzK{D[h\n-0{byK{D[h\n-5M8h}Dyh\n+[FJFAF8F\n+2F[FAF8F\n+JF[FAF8F\n+\"aI{DaHyDxD\n+[F2FAF8F\n+KFRF9F(F\n+I{D,h>hyD\n+K.h F{D=h1F*F[h\n+B;fkh;aV\n+B;fkh;aV\n+hzh}l|`)\n+\tldr\tr1, [pc, #152]\t@ (d8 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xb0>)\n \tmov\tr6, r2\n-\tldr\tr3, [pc, #160]\t@ (e4 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xbc>)\n+\tldr\tr3, [pc, #152]\t@ (dc <__gridxc_alloc_MOD_dummy_alloc_error_report+0xb4>)\n \tadd\tr4, sp, #8\n-\tldr\tr2, [pc, #160]\t@ (e8 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xc0>)\n+\tldr\tr2, [pc, #152]\t@ (e0 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xb8>)\n \tadd\tr1, pc\n-\tvldr\td16, [pc, #140]\t@ d8 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xb0>\n \tadd\tr3, pc\n \tstr\tr3, [sp, #16]\n \tmov\tr5, r0\n \tmov\tr0, r4\n \tmovw\tr3, #257\t@ 0x101\n-\tvstr\td16, [sp, #8]\n \tldr\tr2, [r1, r2]\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #356]\t@ 0x164\n \tmov.w\tr2, #0\n+\tmovs\tr2, #128\t@ 0x80\n \tstr\tr3, [sp, #20]\n+\tmovs\tr3, #6\n+\tstrd\tr2, r3, [sp, #8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n \tmov\tr1, r5\n \tmov\tr0, r6\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tr6, r0, r0, asr #31\n \tadd.w\tr8, r6, #8\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #104]\t@ (ec <__gridxc_alloc_MOD_dummy_alloc_error_report+0xc4>)\n+\tldr\tr3, [pc, #96]\t@ (e4 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xbc>)\n \tmov\tr1, r0\n \tmovs\tr2, #8\n \tadd\tr3, pc\n \tstr\tr5, [sp, #4]\n \tstr\tr6, [sp, #0]\n \tmov\tr5, r0\n \tmov\tr0, r8\n@@ -78,16 +79,16 @@\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tldr\tr2, [r7, #0]\n \tcbz\tr2, ca <__gridxc_alloc_MOD_dummy_alloc_error_report+0xa2>\n-\tldr\tr2, [pc, #60]\t@ (f0 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xc8>)\n-\tldr\tr3, [pc, #52]\t@ (e8 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xc0>)\n+\tldr\tr2, [pc, #52]\t@ (e8 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xc0>)\n+\tldr\tr3, [pc, #44]\t@ (e0 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #356]\t@ 0x164\n \teors\tr2, r3\n \tmov.w\tr3, #0\n \tbne.n\td2 <__gridxc_alloc_MOD_dummy_alloc_error_report+0xaa>\n@@ -96,536 +97,524 @@\n \tmov\tr1, r2\n \tmov\tr0, r2\n \tbl\t0 <_gfortran_stop_string>\n R_ARM_THM_CALL\t_gfortran_stop_string\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x00000080\n-\t.word\t0x00000006\n-\t.word\t0x00000096\n+\t.word\t0x0000008e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000094\n+\t.word\t0x00000090\n R_ARM_REL32\t.LC0\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000060\n+\t.word\t0x00000058\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000038\n+\t.word\t0x00000030\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000000f4 <__gridxc_alloc_MOD_options.constprop.0>:\n+000000ec <__gridxc_alloc_MOD_options.constprop.0>:\n __gridxc_alloc_MOD_options.constprop.0():\n-\tldr.w\tip, [pc, #228]\t@ 1dc <__gridxc_alloc_MOD_options.constprop.0+0xe8>\n \tldr\tr3, [r3, #0]\n-\tadd\tip, pc\n-\tpush\t{r4, r5, r6, r7}\n-\tldr\tr0, [r0, #0]\n-\tldr\tr4, [r1, #0]\n-\tsub\tsp, #8\n-\tvld1.32\t{d7}, [r3]\n-\tldr.w\tr3, [ip]\n-\tldr\tr2, [r2, #0]\n-\tcbz\tr3, 136 <__gridxc_alloc_MOD_options.constprop.0+0x42>\n-\tvmov\tr1, s14\n-\tldr\tr3, [r2, #0]\n-\tvmov.32\tip, d7[1]\n-\tldr\tr2, [r2, #4]\n-\tcmp\tr1, r3\n-\tbne.n\t14a <__gridxc_alloc_MOD_options.constprop.0+0x56>\n-\tcmp\tip, r2\n-\tbne.n\t14a <__gridxc_alloc_MOD_options.constprop.0+0x56>\n-\tldr\tr3, [pc, #184]\t@ (1e0 <__gridxc_alloc_MOD_options.constprop.0+0xec>)\n+\tstmdb\tsp!, {r4, r5, r6, r7, r8, lr}\n+\tldr\tr5, [r2, #0]\n+\tldr\tr6, [r1, #0]\n+\tldrd\tr2, r1, [r3]\n+\tldr\tr3, [pc, #208]\t@ (1cc <__gridxc_alloc_MOD_options.constprop.0+0xe0>)\n+\tldr\tr4, [r0, #0]\n+\tadd\tr3, pc\n+\tldr\tr0, [r3, #0]\n+\tcbz\tr0, 124 <__gridxc_alloc_MOD_options.constprop.0+0x38>\n+\tldrd\tr3, r0, [r5]\n+\tmov\tip, r2\n+\tmov\tr7, r1\n+\tcmp\tr2, r3\n+\tbne.n\t134 <__gridxc_alloc_MOD_options.constprop.0+0x48>\n+\tcmp\tr1, r0\n+\tbne.n\t134 <__gridxc_alloc_MOD_options.constprop.0+0x48>\n+\tldr\tr3, [pc, #184]\t@ (1d0 <__gridxc_alloc_MOD_options.constprop.0+0xe4>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstrd\tr2, r2, [r3, #4]\n \tstr\tr2, [r3, #12]\n-\tadd\tsp, #8\n-\tpop\t{r4, r5, r6, r7}\n-\tbx\tlr\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n+\tstr\tr2, [r4, #0]\n \tmovs\tr2, #1\n-\tstr.w\tr3, [ip, #12]\n-\tstrd\tr2, r3, [ip, #4]\n-\tvst1.32\t{d7}, [r0]\n-\tadd\tsp, #8\n-\tpop\t{r4, r5, r6, r7}\n-\tbx\tlr\n+\tstrd\tr0, r0, [r3, #8]\n+\tstr\tr1, [r4, #4]\n+\tstr\tr2, [r3, #4]\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n \tldr\tr5, [sp, #28]\n-\tcbz\tr5, 198 <__gridxc_alloc_MOD_options.constprop.0+0xa4>\n-\tldr\tr6, [r5, #0]\n-\tcmp\tr1, r3\n-\teor.w\tr5, r6, #1\n-\tand.w\tr5, r5, #1\n-\tit\tlt\n+\tcbz\tr5, 18c <__gridxc_alloc_MOD_options.constprop.0+0xa0>\n+\tldr.w\tlr, [r5]\n+\teor.w\tr5, lr, #1\n+\tcmp\tr2, r3\n+\tite\tlt\n \tmovlt\tr5, #0\n-\tcmp\tip, r2\n-\tbgt.n\t1a0 <__gridxc_alloc_MOD_options.constprop.0+0xac>\n+\tandge.w\tr5, r5, #1\n+\tcmp\tr1, r0\n+\tbgt.n\t196 <__gridxc_alloc_MOD_options.constprop.0+0xaa>\n \tcmp\tr5, #0\n-\tbne.n\t124 <__gridxc_alloc_MOD_options.constprop.0+0x30>\n-\tldr\tr5, [pc, #124]\t@ (1e4 <__gridxc_alloc_MOD_options.constprop.0+0xf0>)\n-\tmovs\tr7, #1\n+\tbne.n\t114 <__gridxc_alloc_MOD_options.constprop.0+0x28>\n+\tldr\tr5, [pc, #128]\t@ (1d4 <__gridxc_alloc_MOD_options.constprop.0+0xe8>)\n+\tmov.w\tr8, #1\n \tadd\tr5, pc\n-\tstrd\tr7, r7, [r5, #4]\n+\tstrd\tr8, r8, [r5, #4]\n \tldr\tr5, [sp, #24]\n-\tcbz\tr5, 1ce <__gridxc_alloc_MOD_options.constprop.0+0xda>\n-\tldr\tr7, [r5, #0]\n-\tldr\tr5, [pc, #112]\t@ (1e8 <__gridxc_alloc_MOD_options.constprop.0+0xf4>)\n+\tcbz\tr5, 1be <__gridxc_alloc_MOD_options.constprop.0+0xd2>\n+\tldr.w\tr8, [r5]\n+\tldr\tr5, [pc, #112]\t@ (1d8 <__gridxc_alloc_MOD_options.constprop.0+0xec>)\n \tadd\tr5, pc\n-\tstr\tr7, [r5, #12]\n-\tcbz\tr6, 1b6 <__gridxc_alloc_MOD_options.constprop.0+0xc2>\n-\tcmp\tr2, ip\n+\tstr.w\tr8, [r5, #12]\n+\tcmp.w\tlr, #0\n+\tbeq.n\t1ac <__gridxc_alloc_MOD_options.constprop.0+0xc0>\n+\tcmp\tr0, r1\n \tit\tge\n-\tmovge\tr2, ip\n-\tcmp\tr3, r1\n+\tmovge\tr0, r1\n+\tcmp\tr3, r2\n \tit\tlt\n-\tmovlt\tr3, r1\n-\tstrd\tr3, r2, [r4]\n-\tvst1.32\t{d7}, [r0]\n-\tadd\tsp, #8\n-\tpop\t{r4, r5, r6, r7}\n-\tbx\tlr\n-\tldr\tr5, [pc, #80]\t@ (1ec <__gridxc_alloc_MOD_options.constprop.0+0xf8>)\n+\tmovlt\tr3, r2\n+\tstrd\tip, r7, [r4]\n+\tstrd\tr3, r0, [r6]\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n+\tldr\tr5, [pc, #76]\t@ (1dc <__gridxc_alloc_MOD_options.constprop.0+0xf0>)\n \tadd\tr5, pc\n-\tldr\tr6, [r5, #4]\n-\tb.n\t150 <__gridxc_alloc_MOD_options.constprop.0+0x5c>\n+\tldr.w\tlr, [r5, #4]\n+\tb.n\t13c <__gridxc_alloc_MOD_options.constprop.0+0x50>\n \tcmp\tr5, #0\n-\tbeq.n\t166 <__gridxc_alloc_MOD_options.constprop.0+0x72>\n-\tldr\tr5, [pc, #72]\t@ (1f0 <__gridxc_alloc_MOD_options.constprop.0+0xfc>)\n-\tmovs\tr6, #1\n+\tbeq.n\t152 <__gridxc_alloc_MOD_options.constprop.0+0x66>\n+\tldr\tr5, [pc, #68]\t@ (1e0 <__gridxc_alloc_MOD_options.constprop.0+0xf4>)\n+\tmovs\tr7, #1\n \tadd\tr5, pc\n-\tstrd\tr6, r6, [r5, #4]\n-\tldr\tr6, [sp, #24]\n-\tcbz\tr6, 1d4 <__gridxc_alloc_MOD_options.constprop.0+0xe0>\n-\tldr\tr6, [r6, #0]\n-\tstr\tr6, [r5, #12]\n-\tcmp\tr1, r3\n+\tstrd\tr7, r7, [r5, #4]\n+\tldr\tr7, [sp, #24]\n+\tcbz\tr7, 1c4 <__gridxc_alloc_MOD_options.constprop.0+0xd8>\n+\tldr\tr7, [r7, #0]\n+\tstr\tr7, [r5, #12]\n+\tcmp\tr2, r3\n \tit\tge\n-\tmovge\tr1, r3\n-\tcmp\tip, r2\n-\tstr\tr1, [sp, #0]\n-\tmov\tr1, ip\n+\tmovge\tr2, r3\n+\tcmp\tr1, r0\n \tit\tlt\n-\tmovlt\tr1, r2\n-\tstr\tr1, [sp, #4]\n-\tvldr\td7, [sp]\n-\tb.n\t18a <__gridxc_alloc_MOD_options.constprop.0+0x96>\n-\tldr\tr5, [pc, #36]\t@ (1f4 <__gridxc_alloc_MOD_options.constprop.0+0x100>)\n+\tmovlt\tr1, r0\n+\tmov\tip, r2\n+\tmov\tr7, r1\n+\tb.n\t180 <__gridxc_alloc_MOD_options.constprop.0+0x94>\n+\tldr\tr5, [pc, #36]\t@ (1e4 <__gridxc_alloc_MOD_options.constprop.0+0xf8>)\n \tadd\tr5, pc\n-\tb.n\t174 <__gridxc_alloc_MOD_options.constprop.0+0x80>\n-\tldr\tr6, [pc, #32]\t@ (1f8 <__gridxc_alloc_MOD_options.constprop.0+0x104>)\n-\tadd\tr6, pc\n-\tb.n\t1b2 <__gridxc_alloc_MOD_options.constprop.0+0xbe>\n+\tb.n\t162 <__gridxc_alloc_MOD_options.constprop.0+0x76>\n+\tldr\tr7, [pc, #32]\t@ (1e8 <__gridxc_alloc_MOD_options.constprop.0+0xfc>)\n+\tadd\tr7, pc\n+\tb.n\t1a8 <__gridxc_alloc_MOD_options.constprop.0+0xbc>\n \tnop\n-\t.word\t0x000000de\n+\t.word\t0x000000ca\n R_ARM_REL32\t.bss\n \t.word\t0x000000b4\n R_ARM_REL32\t.bss\n-\t.word\t0x00000076\n+\t.word\t0x00000078\n R_ARM_REL32\t.bss\n \t.word\t0x0000006c\n R_ARM_REL32\t.bss\n-\t.word\t0x0000004e\n+\t.word\t0x0000004a\n R_ARM_REL32\t.data\n-\t.word\t0x00000044\n+\t.word\t0x0000003e\n R_ARM_REL32\t.bss\n \t.word\t0x00000020\n R_ARM_REL32\t.data\n \t.word\t0x0000001e\n R_ARM_REL32\t.data\n \n-000001fc <__gridxc_alloc_MOD_options.constprop.1>:\n+000001ec <__gridxc_alloc_MOD_options.constprop.1>:\n __gridxc_alloc_MOD_options.constprop.1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr\tr7, [r0, #0]\n-\tldr\tr0, [r2, #0]\n-\tsub\tsp, #60\t@ 0x3c\n-\tldr\tr2, [pc, #412]\t@ (3a4 <__gridxc_alloc_MOD_options.constprop.1+0x1a8>)\n-\tldr.w\tr8, [r1]\n-\tadd\tr2, pc\n-\tldr\tr3, [r3, #0]\n-\tldr\tr1, [r2, #0]\n-\tldr\tr6, [r3, #4]\n-\tldr\tr4, [r3, #12]\n-\tldr\tr5, [r3, #0]\n-\tcbz\tr1, 24e <__gridxc_alloc_MOD_options.constprop.1+0x52>\n-\tldrd\tr1, ip, [r0]\n-\tldr\tr2, [r0, #12]\n-\tcmp\tr5, r1\n-\tstr\tr2, [sp, #4]\n-\tbne.n\t272 <__gridxc_alloc_MOD_options.constprop.1+0x76>\n-\tcmp\tip, r6\n-\tbne.w\t36a <__gridxc_alloc_MOD_options.constprop.1+0x16e>\n-\tldr.w\tr9, [r3, #8]\n-\tldr.w\tlr, [r0, #8]\n-\tcmp\tr9, lr\n-\tbne.n\t272 <__gridxc_alloc_MOD_options.constprop.1+0x76>\n-\tcmp\tr2, r4\n-\tbne.n\t272 <__gridxc_alloc_MOD_options.constprop.1+0x76>\n-\tldr\tr3, [pc, #360]\t@ (3a8 <__gridxc_alloc_MOD_options.constprop.1+0x1ac>)\n+\tldr\tr4, [pc, #432]\t@ (3a4 <__gridxc_alloc_MOD_options.constprop.1+0x1b8>)\n+\tldr.w\tip, [r3]\n+\tsub\tsp, #20\n+\tadd\tr4, pc\n+\tldr\tr3, [r0, #0]\n+\tldr.w\tfp, [r2]\n+\tldr\tr5, [r1, #0]\n+\tldr\tr6, [r4, #0]\n+\tldr.w\tr2, [ip]\n+\tldr.w\tr1, [ip, #4]\n+\tldr.w\tr0, [ip, #12]\n+\tcbz\tr6, 24c <__gridxc_alloc_MOD_options.constprop.1+0x60>\n+\tldrd\tr6, r7, [fp]\n+\tmov\tlr, r2\n+\tldr.w\tr4, [fp, #12]\n+\tmov\tr8, r1\n+\tcmp\tr2, r6\n+\tstr\tr4, [sp, #4]\n+\tbne.n\t266 <__gridxc_alloc_MOD_options.constprop.1+0x7a>\n+\tcmp\tr1, r7\n+\tbne.w\t362 <__gridxc_alloc_MOD_options.constprop.1+0x176>\n+\tldr.w\tsl, [ip, #8]\n+\tldr.w\tr9, [fp, #8]\n+\tcmp\tsl, r9\n+\tbne.n\t266 <__gridxc_alloc_MOD_options.constprop.1+0x7a>\n+\tcmp\tr4, r0\n+\tbne.n\t266 <__gridxc_alloc_MOD_options.constprop.1+0x7a>\n+\tldr\tr3, [pc, #364]\t@ (3a8 <__gridxc_alloc_MOD_options.constprop.1+0x1bc>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstrd\tr2, r2, [r3, #4]\n \tstr\tr2, [r3, #12]\n-\tadd\tsp, #60\t@ 0x3c\n+\tadd\tsp, #20\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tstrd\tr5, r6, [sp, #8]\n-\tstrd\tr1, r1, [r2, #8]\n-\tldr\tr3, [r3, #8]\n-\tstrd\tr3, r4, [sp, #16]\n+\tstrd\tr2, r1, [r3]\n+\tldr.w\tr2, [ip, #8]\n+\tstr\tr2, [r3, #8]\n+\tstr\tr0, [r3, #12]\n \tmovs\tr3, #1\n-\tvldr\td16, [sp, #8]\n-\tvldr\td17, [sp, #16]\n-\tstr\tr3, [r2, #4]\n-\tvst1.32\t{d16-d17}, [r7]\n-\tadd\tsp, #60\t@ 0x3c\n+\tstrd\tr6, r6, [r4, #8]\n+\tstr\tr3, [r4, #4]\n+\tadd\tsp, #20\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tcmp\tr2, #0\n-\tbeq.n\t318 <__gridxc_alloc_MOD_options.constprop.1+0x11c>\n-\tldr.w\tsl, [r2]\n-\tcmp\tr5, r1\n-\tblt.n\t37c <__gridxc_alloc_MOD_options.constprop.1+0x180>\n-\tldr.w\tfp, [r3, #8]\n-\tldr\tr3, [r0, #8]\n-\teor.w\tr0, sl, #1\n-\tand.w\tr0, r0, #1\n+\tldr\tr4, [sp, #60]\t@ 0x3c\n+\tcmp\tr4, #0\n+\tbeq.n\t304 <__gridxc_alloc_MOD_options.constprop.1+0x118>\n+\tldr\tr4, [r4, #0]\n+\tstr\tr4, [sp, #8]\n+\tcmp\tr2, r6\n+\tblt.w\t378 <__gridxc_alloc_MOD_options.constprop.1+0x18c>\n+\tldr\tr4, [sp, #8]\n+\tldr.w\tip, [ip, #8]\n+\tldr.w\tfp, [fp, #8]\n+\teor.w\tr9, r4, #1\n+\tmov\tr4, r9\n+\tmov\tsl, ip\n+\tcmp\tip, fp\n+\tite\tlt\n+\tmovlt\tr4, #0\n+\tandge.w\tr4, r4, #1\n \tmov\tr9, fp\n-\tcmp\tfp, r3\n-\tmov\tlr, r3\n-\tit\tlt\n-\tmovlt\tr0, #0\n-\tcmp\tip, r6\n-\tblt.n\t324 <__gridxc_alloc_MOD_options.constprop.1+0x128>\n-\tldr\tr2, [sp, #4]\n-\tcmp\tr2, r4\n-\tblt.n\t324 <__gridxc_alloc_MOD_options.constprop.1+0x128>\n-\tcmp\tr0, #0\n-\tbne.n\t23c <__gridxc_alloc_MOD_options.constprop.1+0x40>\n+\tcmp\tr1, r7\n+\tstr\tr4, [sp, #12]\n+\tbgt.n\t312 <__gridxc_alloc_MOD_options.constprop.1+0x126>\n+\tldr\tr4, [sp, #4]\n+\tcmp\tr4, r0\n+\tldr\tr4, [sp, #12]\n+\tblt.n\t312 <__gridxc_alloc_MOD_options.constprop.1+0x126>\n+\tcmp\tr4, #0\n+\tbne.n\t23a <__gridxc_alloc_MOD_options.constprop.1+0x4e>\n+\tmov\tip, sl\n \tmov\tfp, r9\n-\tmov\tr3, lr\n-\tldr\tr0, [pc, #256]\t@ (3ac <__gridxc_alloc_MOD_options.constprop.1+0x1b0>)\n-\tmov.w\tlr, #1\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tadd\tr0, pc\n-\tstrd\tlr, lr, [r0, #4]\n-\tcmp\tr2, #0\n-\tbeq.n\t360 <__gridxc_alloc_MOD_options.constprop.1+0x164>\n-\tldr.w\tlr, [r2]\n-\tldr\tr0, [pc, #236]\t@ (3b0 <__gridxc_alloc_MOD_options.constprop.1+0x1b4>)\n-\tadd\tr0, pc\n-\tstr.w\tlr, [r0, #12]\n-\tcmp.w\tsl, #0\n-\tbeq.n\t344 <__gridxc_alloc_MOD_options.constprop.1+0x148>\n-\tcmp\tip, r6\n+\tldr.w\tr9, [pc, #256]\t@ 3ac <__gridxc_alloc_MOD_options.constprop.1+0x1c0>\n+\tmov.w\tsl, #1\n+\tldr\tr4, [sp, #56]\t@ 0x38\n+\tadd\tr9, pc\n+\tstrd\tsl, sl, [r9, #4]\n+\tcmp\tr4, #0\n+\tbeq.n\t356 <__gridxc_alloc_MOD_options.constprop.1+0x16a>\n+\tldr.w\tsl, [r4]\n+\tldr.w\tr9, [pc, #236]\t@ 3b0 <__gridxc_alloc_MOD_options.constprop.1+0x1c4>\n+\tldr\tr4, [sp, #8]\n+\tadd\tr9, pc\n+\tstr.w\tsl, [r9, #12]\n+\tcbz\tr4, 336 <__gridxc_alloc_MOD_options.constprop.1+0x14a>\n+\tcmp\tr7, r1\n \tit\tge\n-\tmovge\tip, r6\n-\tcmp\tr1, r5\n+\tmovge\tr7, r1\n+\tcmp\tr6, r2\n \tit\tlt\n-\tmovlt\tr1, r5\n-\tstrd\tr5, r6, [sp, #40]\t@ 0x28\n-\tcmp\tr3, fp\n-\tstr.w\tfp, [sp, #48]\t@ 0x30\n-\tit\tlt\n-\tmovlt\tr3, fp\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td17, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #4]\n-\tcmp\tr2, r4\n-\tvst1.32\t{d16-d17}, [r7]\n+\tmovlt\tr6, r2\n+\tldr\tr4, [sp, #4]\n+\tcmp\tfp, ip\n+\tmov\tr2, fp\n+\tit\tlt\n+\tmovlt\tr2, ip\n+\tcmp\tr4, r0\n+\tstrd\tlr, r8, [r3]\n \tit\tge\n-\tmovge\tr2, r4\n-\tstrd\tr1, ip, [sp, #24]\n-\tstrd\tr3, r2, [sp, #32]\n-\tvldr\td16, [sp, #24]\n-\tvldr\td17, [sp, #32]\n-\tvst1.32\t{d16-d17}, [r8]\n-\tadd\tsp, #60\t@ 0x3c\n+\tmovge\tr4, r0\n+\tstrd\tr6, r7, [r5]\n+\tstr.w\tip, [r3, #8]\n+\tstr\tr0, [r3, #12]\n+\tstrd\tr2, r4, [r5, #8]\n+\tadd\tsp, #20\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr.w\tlr, [pc, #152]\t@ 3b4 <__gridxc_alloc_MOD_options.constprop.1+0x1b8>\n-\tadd\tlr, pc\n-\tldr.w\tsl, [lr, #4]\n-\tb.n\t27c <__gridxc_alloc_MOD_options.constprop.1+0x80>\n-\tcmp\tr0, #0\n-\tbeq.n\t2aa <__gridxc_alloc_MOD_options.constprop.1+0xae>\n-\tldr\tr0, [pc, #140]\t@ (3b8 <__gridxc_alloc_MOD_options.constprop.1+0x1bc>)\n-\tmov.w\tlr, #1\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tadd\tr0, pc\n-\tstrd\tlr, lr, [r0, #4]\n-\tcbz\tr2, 374 <__gridxc_alloc_MOD_options.constprop.1+0x178>\n-\tldr\tr0, [r2, #0]\n-\tldr.w\tlr, [pc, #128]\t@ 3bc <__gridxc_alloc_MOD_options.constprop.1+0x1c0>\n+\tldr.w\tr9, [pc, #172]\t@ 3b4 <__gridxc_alloc_MOD_options.constprop.1+0x1c8>\n+\tadd\tr9, pc\n+\tldr.w\tr4, [r9, #4]\n+\tstr\tr4, [sp, #8]\n+\tb.n\t270 <__gridxc_alloc_MOD_options.constprop.1+0x84>\n+\tcmp\tr4, #0\n+\tbeq.n\t2aa <__gridxc_alloc_MOD_options.constprop.1+0xbe>\n+\tldr.w\tlr, [pc, #160]\t@ 3b8 <__gridxc_alloc_MOD_options.constprop.1+0x1cc>\n+\tmov.w\tr8, #1\n+\tldr\tr4, [sp, #56]\t@ 0x38\n \tadd\tlr, pc\n-\tstr.w\tr0, [lr, #12]\n-\tcmp\tr5, r1\n-\tldr\tr2, [sp, #4]\n+\tstrd\tr8, r8, [lr, #4]\n+\tcbz\tr4, 36c <__gridxc_alloc_MOD_options.constprop.1+0x180>\n+\tldr.w\tlr, [r4]\n+\tldr.w\tr8, [pc, #140]\t@ 3bc <__gridxc_alloc_MOD_options.constprop.1+0x1d0>\n+\tadd\tr8, pc\n+\tstr.w\tlr, [r8, #12]\n+\tcmp\tip, fp\n \tit\tge\n-\tmovge\tr5, r1\n-\tcmp\tfp, r3\n+\tmovge\tip, fp\n+\tcmp\tr2, r6\n \tit\tge\n-\tmovge\tfp, r3\n-\tcmp\tr6, ip\n+\tmovge\tr2, r6\n+\tcmp\tr1, r7\n+\tmov\tlr, r2\n+\tldr\tr2, [sp, #4]\n \tit\tlt\n-\tmovlt\tr6, ip\n-\tcmp\tr4, r2\n+\tmovlt\tr1, r7\n+\tcmp\tr0, r2\n+\tmov\tr8, r1\n \tit\tlt\n-\tmovlt\tr4, r2\n-\tb.n\t2da <__gridxc_alloc_MOD_options.constprop.1+0xde>\n-\tldr\tr0, [pc, #92]\t@ (3c0 <__gridxc_alloc_MOD_options.constprop.1+0x1c4>)\n-\tadd\tr0, pc\n-\tldr.w\tlr, [r0]\n-\tb.n\t2c0 <__gridxc_alloc_MOD_options.constprop.1+0xc4>\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tcbz\tr2, 390 <__gridxc_alloc_MOD_options.constprop.1+0x194>\n-\tldr.w\tsl, [r2]\n-\tb.n\t280 <__gridxc_alloc_MOD_options.constprop.1+0x84>\n-\tldr\tr0, [pc, #76]\t@ (3c4 <__gridxc_alloc_MOD_options.constprop.1+0x1c8>)\n-\tadd\tr0, pc\n-\tldr\tr0, [r0, #0]\n-\tb.n\t33a <__gridxc_alloc_MOD_options.constprop.1+0x13e>\n-\tcmp\tip, r6\n-\tblt.n\t39c <__gridxc_alloc_MOD_options.constprop.1+0x1a0>\n-\tldr\tr2, [sp, #4]\n-\tcmp\tr2, r4\n-\tblt.n\t39c <__gridxc_alloc_MOD_options.constprop.1+0x1a0>\n-\tldr.w\tr9, [r3, #8]\n-\tldr.w\tlr, [r0, #8]\n-\tb.n\t2a6 <__gridxc_alloc_MOD_options.constprop.1+0xaa>\n-\tldr.w\tlr, [pc, #52]\t@ 3c8 <__gridxc_alloc_MOD_options.constprop.1+0x1cc>\n+\tmovlt\tr0, r2\n+\tb.n\t2dc <__gridxc_alloc_MOD_options.constprop.1+0xf0>\n+\tldr.w\tr9, [pc, #104]\t@ 3c0 <__gridxc_alloc_MOD_options.constprop.1+0x1d4>\n+\tadd\tr9, pc\n+\tldr.w\tsl, [r9]\n+\tb.n\t2c2 <__gridxc_alloc_MOD_options.constprop.1+0xd6>\n+\tldr\tr4, [sp, #60]\t@ 0x3c\n+\tcbz\tr4, 38c <__gridxc_alloc_MOD_options.constprop.1+0x1a0>\n+\tldr\tr4, [r4, #0]\n+\tstr\tr4, [sp, #8]\n+\tb.n\t276 <__gridxc_alloc_MOD_options.constprop.1+0x8a>\n+\tldr.w\tlr, [pc, #84]\t@ 3c4 <__gridxc_alloc_MOD_options.constprop.1+0x1d8>\n \tadd\tlr, pc\n-\tldr.w\tsl, [lr, #4]\n-\tb.n\t280 <__gridxc_alloc_MOD_options.constprop.1+0x84>\n-\tldr.w\tfp, [r3, #8]\n-\tldr\tr3, [r0, #8]\n-\tb.n\t2aa <__gridxc_alloc_MOD_options.constprop.1+0xae>\n-\t.word\t0x00000194\n+\tldr.w\tlr, [lr]\n+\tb.n\t32c <__gridxc_alloc_MOD_options.constprop.1+0x140>\n+\tcmp\tr1, r7\n+\tbgt.n\t39a <__gridxc_alloc_MOD_options.constprop.1+0x1ae>\n+\tldr\tr4, [sp, #4]\n+\tcmp\tr4, r0\n+\tblt.n\t39a <__gridxc_alloc_MOD_options.constprop.1+0x1ae>\n+\tldr.w\tsl, [ip, #8]\n+\tldr.w\tr9, [fp, #8]\n+\tb.n\t2a6 <__gridxc_alloc_MOD_options.constprop.1+0xba>\n+\tldr.w\tr9, [pc, #56]\t@ 3c8 <__gridxc_alloc_MOD_options.constprop.1+0x1dc>\n+\tadd\tr9, pc\n+\tldr.w\tr4, [r9, #4]\n+\tstr\tr4, [sp, #8]\n+\tb.n\t276 <__gridxc_alloc_MOD_options.constprop.1+0x8a>\n+\tldr.w\tip, [ip, #8]\n+\tldr.w\tfp, [fp, #8]\n+\tb.n\t2aa <__gridxc_alloc_MOD_options.constprop.1+0xbe>\n+\t.word\t0x000001a8\n R_ARM_REL32\t.bss\n-\t.word\t0x00000164\n+\t.word\t0x00000166\n R_ARM_REL32\t.bss\n-\t.word\t0x000000f6\n+\t.word\t0x000000f4\n R_ARM_REL32\t.bss\n-\t.word\t0x000000ea\n+\t.word\t0x000000e4\n R_ARM_REL32\t.bss\n-\t.word\t0x00000094\n+\t.word\t0x000000a8\n R_ARM_REL32\t.data\n-\t.word\t0x00000084\n+\t.word\t0x00000094\n R_ARM_REL32\t.bss\n-\t.word\t0x0000007a\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n+\t.word\t0x00000062\n R_ARM_REL32\t.data\n-\t.word\t0x0000004a\n+\t.word\t0x00000050\n R_ARM_REL32\t.data\n-\t.word\t0x00000030\n+\t.word\t0x00000034\n R_ARM_REL32\t.data\n \n 000003cc <__gridxc_alloc_MOD_options.constprop.2>:\n __gridxc_alloc_MOD_options.constprop.2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr\tr4, [pc, #588]\t@ (620 <__gridxc_alloc_MOD_options.constprop.2+0x254>)\n+\tldr\tr5, [pc, #544]\t@ (5f4 <__gridxc_alloc_MOD_options.constprop.2+0x228>)\n \tldr\tr3, [r3, #0]\n-\tsub\tsp, #100\t@ 0x64\n-\tadd\tr4, pc\n-\tldr.w\tr9, [r1]\n+\tsub\tsp, #52\t@ 0x34\n+\tadd\tr5, pc\n+\tldr\tr4, [r1, #0]\n \tldr\tr0, [r0, #0]\n \tldr\tr2, [r2, #0]\n-\tldr\tr5, [r4, #0]\n+\tldr\tr6, [r5, #0]\n \tldr\tr1, [r3, #0]\n-\tcbz\tr5, 436 <__gridxc_alloc_MOD_options.constprop.2+0x6a>\n-\tldrd\tr6, ip, [r2]\n-\tldr\tr7, [r3, #4]\n-\tcmp\tr6, r1\n-\tbne.n\t46a <__gridxc_alloc_MOD_options.constprop.2+0x9e>\n-\tcmp\tip, r7\n-\tbne.n\t46a <__gridxc_alloc_MOD_options.constprop.2+0x9e>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n+\tcbz\tr6, 436 <__gridxc_alloc_MOD_options.constprop.2+0x6a>\n+\tldrd\tr7, lr, [r2]\n+\tldr.w\tip, [r3, #4]\n+\tcmp\tr7, r1\n+\tbne.n\t45a <__gridxc_alloc_MOD_options.constprop.2+0x8e>\n+\tcmp\tlr, ip\n+\tbne.n\t45a <__gridxc_alloc_MOD_options.constprop.2+0x8e>\n+\tldr\tr5, [r2, #8]\n+\tldr\tr6, [r3, #8]\n \tldr.w\tsl, [r3, #12]\n-\tcmp\tr5, r4\n-\tldr\tr4, [r2, #12]\n-\tstr\tr4, [sp, #4]\n-\tbne.w\t5e0 <__gridxc_alloc_MOD_options.constprop.2+0x214>\n-\tcmp\tsl, r4\n-\tbne.w\t5e0 <__gridxc_alloc_MOD_options.constprop.2+0x214>\n-\tldr.w\tr8, [r3, #16]\n-\tldr.w\tlr, [r2, #16]\n-\tldr\tr4, [r2, #20]\n+\tcmp\tr6, r5\n+\tldr\tr5, [r2, #12]\n+\tstr\tr5, [sp, #4]\n+\tbne.w\t5b6 <__gridxc_alloc_MOD_options.constprop.2+0x1ea>\n+\tcmp\tsl, r5\n+\tbne.w\t5b6 <__gridxc_alloc_MOD_options.constprop.2+0x1ea>\n+\tldr.w\tr9, [r3, #16]\n+\tldr.w\tr8, [r2, #16]\n+\tldr\tr5, [r2, #20]\n \tldr.w\tfp, [r3, #20]\n-\tcmp\tr8, lr\n-\tstr\tr4, [sp, #8]\n-\tbne.n\t47a <__gridxc_alloc_MOD_options.constprop.2+0xae>\n-\tcmp\tfp, r4\n-\tbne.n\t47a <__gridxc_alloc_MOD_options.constprop.2+0xae>\n-\tldr\tr3, [pc, #508]\t@ (624 <__gridxc_alloc_MOD_options.constprop.2+0x258>)\n+\tcmp\tr9, r8\n+\tstr\tr5, [sp, #8]\n+\tbne.n\t46a <__gridxc_alloc_MOD_options.constprop.2+0x9e>\n+\tcmp\tfp, r5\n+\tbne.n\t46a <__gridxc_alloc_MOD_options.constprop.2+0x9e>\n+\tldr\tr3, [pc, #464]\t@ (5f8 <__gridxc_alloc_MOD_options.constprop.2+0x22c>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstrd\tr2, r2, [r3, #4]\n \tstr\tr2, [r3, #12]\n-\tadd\tsp, #100\t@ 0x64\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadd.w\tr2, r3, #16\n-\tstrd\tr5, r5, [r4, #8]\n-\tvld1.32\t{d16}, [r2]\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tldr\tr2, [r3, #4]\n-\tstr\tr2, [sp, #52]\t@ 0x34\n \tldr\tr2, [r3, #8]\n-\tstr\tr2, [sp, #56]\t@ 0x38\n+\tstr\tr2, [r0, #8]\n+\tldr\tr2, [r3, #16]\n+\tstr\tr1, [r0, #0]\n+\tstr\tr2, [r0, #16]\n+\tldr\tr1, [r3, #4]\n+\tldr\tr2, [r3, #20]\n \tldr\tr3, [r3, #12]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr3, [r0, #12]\n \tmovs\tr3, #1\n-\tvldr\td18, [sp, #48]\t@ 0x30\n-\tvldr\td19, [sp, #56]\t@ 0x38\n-\tstr\tr3, [r4, #4]\n-\tvst1.32\t{d18-d19}, [r0]!\n-\tvst1.32\t{d16}, [r0]\n-\tadd\tsp, #100\t@ 0x64\n+\tstrd\tr6, r6, [r5, #8]\n+\tstr\tr1, [r0, #4]\n+\tstr\tr2, [r0, #20]\n+\tstr\tr3, [r5, #4]\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr4, [r2, #12]\n+\tldr\tr5, [r2, #12]\n \tldr.w\tsl, [r3, #12]\n \tldr.w\tfp, [r3, #20]\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [r2, #20]\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [sp, #140]\t@ 0x8c\n-\tcmp\tr4, #0\n-\tbeq.n\t574 <__gridxc_alloc_MOD_options.constprop.2+0x1a8>\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #16]\n-\tcmp\tr6, r1\n-\tstr.w\tip, [sp, #40]\t@ 0x28\n-\tstrd\tr7, sl, [sp, #28]\n+\tstr\tr5, [sp, #4]\n+\tldr\tr5, [r2, #20]\n+\tstr\tr5, [sp, #8]\n+\tldr\tr5, [sp, #92]\t@ 0x5c\n+\tcmp\tr5, #0\n+\tbeq.n\t54a <__gridxc_alloc_MOD_options.constprop.2+0x17e>\n+\tldr\tr5, [r5, #0]\n+\tstr\tr5, [sp, #16]\n+\tcmp\tr7, r1\n+\tstr.w\tlr, [sp, #40]\t@ 0x28\n+\tstrd\tip, sl, [sp, #28]\n \tstr.w\tfp, [sp, #36]\t@ 0x24\n-\tbgt.w\t5ea <__gridxc_alloc_MOD_options.constprop.2+0x21e>\n-\tldr\tr5, [r3, #8]\n-\tldr\tr4, [r2, #8]\n-\tstr\tr5, [sp, #12]\n-\tcmp\tr5, r4\n-\tstr\tr4, [sp, #20]\n-\tblt.w\t5ea <__gridxc_alloc_MOD_options.constprop.2+0x21e>\n-\tldr.w\tr8, [r3, #16]\n-\tldr.w\tlr, [r2, #16]\n+\tbgt.w\t5c0 <__gridxc_alloc_MOD_options.constprop.2+0x1f4>\n+\tldr\tr6, [r3, #8]\n+\tldr\tr5, [r2, #8]\n+\tstr\tr6, [sp, #12]\n+\tcmp\tr6, r5\n+\tstr\tr5, [sp, #20]\n+\tblt.w\t5c0 <__gridxc_alloc_MOD_options.constprop.2+0x1f4>\n+\tldr.w\tr9, [r3, #16]\n \tldr\tr3, [sp, #16]\n-\tcmp\tr8, lr\n-\tstr.w\tlr, [sp, #24]\n+\tldr.w\tr8, [r2, #16]\n \teor.w\tr2, r3, #1\n-\tmov\tr3, r8\n-\tand.w\tr2, r2, #1\n-\tit\tlt\n-\tmovlt\tr2, #0\n-\tcmp\tr7, ip\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tbgt.n\t580 <__gridxc_alloc_MOD_options.constprop.2+0x1b4>\n+\tstr.w\tr8, [sp, #24]\n+\tmov\tr3, r2\n+\tcmp\tr9, r8\n+\tite\tlt\n+\tmovlt\tr3, #0\n+\tandge.w\tr3, r3, #1\n+\tcmp\tip, lr\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tmov\tr3, r9\n+\tbgt.n\t554 <__gridxc_alloc_MOD_options.constprop.2+0x188>\n \tldr\tr2, [sp, #4]\n \tcmp\tsl, r2\n-\tbgt.n\t57e <__gridxc_alloc_MOD_options.constprop.2+0x1b2>\n+\tbgt.n\t554 <__gridxc_alloc_MOD_options.constprop.2+0x188>\n \tldr\tr2, [sp, #8]\n \tcmp\tr2, fp\n-\tblt.n\t57e <__gridxc_alloc_MOD_options.constprop.2+0x1b2>\n+\tblt.n\t554 <__gridxc_alloc_MOD_options.constprop.2+0x188>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr3, #0\n \tbne.n\t424 <__gridxc_alloc_MOD_options.constprop.2+0x58>\n-\tmov\tr3, r8\n-\tstrd\tr4, lr, [sp, #20]\n-\tstr\tr5, [sp, #12]\n-\tldr\tr2, [pc, #324]\t@ (628 <__gridxc_alloc_MOD_options.constprop.2+0x25c>)\n-\tmovs\tr4, #1\n+\tmov\tr3, r9\n+\tstrd\tr5, r8, [sp, #20]\n+\tstr\tr6, [sp, #12]\n+\tldr\tr2, [pc, #292]\t@ (5fc <__gridxc_alloc_MOD_options.constprop.2+0x230>)\n+\tmovs\tr5, #1\n \tadd\tr2, pc\n-\tstrd\tr4, r4, [r2, #4]\n-\tldr\tr2, [sp, #136]\t@ 0x88\n+\tstrd\tr5, r5, [r2, #4]\n+\tldr\tr2, [sp, #88]\t@ 0x58\n \tcmp\tr2, #0\n-\tbeq.n\t5da <__gridxc_alloc_MOD_options.constprop.2+0x20e>\n-\tldr\tr4, [r2, #0]\n-\tldr\tr2, [pc, #308]\t@ (62c <__gridxc_alloc_MOD_options.constprop.2+0x260>)\n+\tbeq.n\t5b0 <__gridxc_alloc_MOD_options.constprop.2+0x1e4>\n+\tldr\tr5, [r2, #0]\n+\tldr\tr2, [pc, #280]\t@ (600 <__gridxc_alloc_MOD_options.constprop.2+0x234>)\n \tadd\tr2, pc\n-\tstr\tr4, [r2, #12]\n+\tstr\tr5, [r2, #12]\n \tldr\tr2, [sp, #16]\n \tcmp\tr2, #0\n-\tbeq.n\t59c <__gridxc_alloc_MOD_options.constprop.2+0x1d0>\n-\tcmp\tip, r7\n-\tmov\tr2, ip\n+\tbeq.n\t572 <__gridxc_alloc_MOD_options.constprop.2+0x1a6>\n+\tcmp\tlr, ip\n+\tmov\tr2, lr\n \tit\tge\n-\tmovge\tr2, r7\n-\tcmp\tr6, r1\n+\tmovge\tr2, ip\n+\tcmp\tr7, r1\n \tit\tlt\n-\tmovlt\tr6, r1\n+\tmovlt\tr7, r1\n \tstr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #24]\n-\tstr\tr3, [r0, #16]\n-\tcmp\tr3, r2\n-\tldr\tr4, [sp, #36]\t@ 0x24\n-\tit\tlt\n-\tmovlt\tr3, r2\n \tldr\tr2, [sp, #28]\n-\tstr\tr4, [r0, #20]\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #8]\n-\tstr\tr1, [sp, #80]\t@ 0x50\n-\tldr\tr5, [sp, #32]\n-\tcmp\tr2, r4\n+\tstrd\tr1, r2, [r0]\n+\tldr\tr2, [sp, #40]\t@ 0x28\n \tldr\tr1, [sp, #12]\n-\tit\tge\n-\tmovge\tr2, r4\n-\tstr\tr1, [sp, #88]\t@ 0x58\n-\tstr\tr5, [sp, #92]\t@ 0x5c\n-\tldr\tr4, [sp, #20]\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvldr\td17, [sp, #88]\t@ 0x58\n-\tcmp\tr4, r1\n+\tstr\tr2, [r4, #4]\n+\tldr\tr2, [sp, #20]\n+\tstr\tr3, [r0, #16]\n+\tcmp\tr2, r1\n+\tstr\tr7, [r4, #0]\n \tit\tlt\n-\tmovlt\tr4, r1\n-\tldr\tr1, [sp, #4]\n-\tstr.w\tr3, [r9, #16]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tcmp\tr1, r5\n-\tvst1.32\t{d16-d17}, [r0]\n+\tmovlt\tr2, r1\n+\tstr\tr2, [r4, #8]\n+\tldr\tr2, [sp, #24]\n+\tstr\tr1, [r0, #8]\n+\tcmp\tr2, r3\n+\tit\tlt\n+\tmovlt\tr2, r3\n+\tldr\tr3, [sp, #4]\n+\tstr\tr2, [r4, #16]\n+\tldr\tr2, [sp, #32]\n+\tstr\tr2, [r0, #12]\n+\tcmp\tr3, r2\n+\tit\tge\n+\tmovge\tr3, r2\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tstr\tr3, [r4, #12]\n+\tldr\tr3, [sp, #8]\n+\tstr\tr2, [r0, #20]\n+\tcmp\tr3, r2\n \tit\tge\n-\tmovge\tr1, r5\n-\tstrd\tr3, r4, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tstr.w\tr2, [r9, #20]\n-\tvst1.32\t{d16-d17}, [r9]\n-\tadd\tsp, #100\t@ 0x64\n+\tmovge\tr3, r2\n+\tstr\tr3, [r4, #20]\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr4, [pc, #184]\t@ (630 <__gridxc_alloc_MOD_options.constprop.2+0x264>)\n-\tadd\tr4, pc\n-\tldr\tr4, [r4, #4]\n-\tstr\tr4, [sp, #16]\n-\tb.n\t484 <__gridxc_alloc_MOD_options.constprop.2+0xb8>\n+\tldr\tr5, [pc, #184]\t@ (604 <__gridxc_alloc_MOD_options.constprop.2+0x238>)\n+\tadd\tr5, pc\n+\tldr\tr5, [r5, #4]\n+\tstr\tr5, [sp, #16]\n+\tb.n\t474 <__gridxc_alloc_MOD_options.constprop.2+0xa8>\n \tldr\tr2, [sp, #44]\t@ 0x2c\n \tcmp\tr2, #0\n-\tbeq.n\t4e2 <__gridxc_alloc_MOD_options.constprop.2+0x116>\n-\tldr\tr2, [pc, #172]\t@ (634 <__gridxc_alloc_MOD_options.constprop.2+0x268>)\n-\tmovs\tr4, #1\n+\tbeq.n\t4d4 <__gridxc_alloc_MOD_options.constprop.2+0x108>\n+\tldr\tr2, [pc, #172]\t@ (608 <__gridxc_alloc_MOD_options.constprop.2+0x23c>)\n+\tmovs\tr5, #1\n \tadd\tr2, pc\n-\tstrd\tr4, r4, [r2, #4]\n-\tldr\tr2, [sp, #136]\t@ 0x88\n+\tstrd\tr5, r5, [r2, #4]\n+\tldr\tr2, [sp, #88]\t@ 0x58\n \tcmp\tr2, #0\n-\tbeq.n\t608 <__gridxc_alloc_MOD_options.constprop.2+0x23c>\n-\tldr\tr4, [r2, #0]\n-\tldr\tr2, [pc, #160]\t@ (638 <__gridxc_alloc_MOD_options.constprop.2+0x26c>)\n+\tbeq.n\t5de <__gridxc_alloc_MOD_options.constprop.2+0x212>\n+\tldr\tr5, [r2, #0]\n+\tldr\tr2, [pc, #156]\t@ (60c <__gridxc_alloc_MOD_options.constprop.2+0x240>)\n \tadd\tr2, pc\n-\tstr\tr4, [r2, #12]\n-\tcmp\tr7, ip\n-\tmov\tr2, r7\n-\tldr\tr4, [sp, #20]\n+\tstr\tr5, [r2, #12]\n+\tcmp\tip, lr\n+\tmov\tr2, ip\n+\tldr\tr5, [sp, #20]\n \tit\tlt\n-\tmovlt\tr2, ip\n+\tmovlt\tr2, lr\n \tstr\tr2, [sp, #28]\n-\tcmp\tr1, r6\n+\tcmp\tr1, r7\n \tldr\tr2, [sp, #12]\n \tit\tge\n-\tmovge\tr1, r6\n-\tcmp\tr2, r4\n+\tmovge\tr1, r7\n+\tcmp\tr2, r5\n \tit\tge\n-\tmovge\tr2, r4\n+\tmovge\tr2, r5\n \tstr\tr2, [sp, #12]\n \tldr\tr2, [sp, #24]\n \tcmp\tr3, r2\n \tit\tge\n \tmovge\tr3, r2\n \tldr\tr2, [sp, #4]\n \tcmp\tsl, r2\n@@ -633,1542 +622,1515 @@\n \tmovlt\tsl, r2\n \tldr\tr2, [sp, #8]\n \tstr.w\tsl, [sp, #32]\n \tcmp\tfp, r2\n \tit\tlt\n \tmovlt\tfp, r2\n \tstr.w\tfp, [sp, #36]\t@ 0x24\n-\tb.n\t510 <__gridxc_alloc_MOD_options.constprop.2+0x144>\n-\tldr\tr2, [pc, #96]\t@ (63c <__gridxc_alloc_MOD_options.constprop.2+0x270>)\n+\tb.n\t502 <__gridxc_alloc_MOD_options.constprop.2+0x136>\n+\tldr\tr2, [pc, #92]\t@ (610 <__gridxc_alloc_MOD_options.constprop.2+0x244>)\n \tadd\tr2, pc\n-\tb.n\t4f2 <__gridxc_alloc_MOD_options.constprop.2+0x126>\n-\tldr\tr4, [r2, #20]\n+\tb.n\t4e4 <__gridxc_alloc_MOD_options.constprop.2+0x118>\n+\tldr\tr5, [r2, #20]\n \tldr.w\tfp, [r3, #20]\n-\tstr\tr4, [sp, #8]\n-\tb.n\t47a <__gridxc_alloc_MOD_options.constprop.2+0xae>\n-\tcmp\tr7, ip\n-\tbgt.n\t60e <__gridxc_alloc_MOD_options.constprop.2+0x242>\n-\tldr\tr4, [sp, #4]\n-\tcmp\tsl, r4\n-\tbgt.n\t60e <__gridxc_alloc_MOD_options.constprop.2+0x242>\n-\tldr\tr4, [sp, #8]\n-\tcmp\tr4, fp\n-\tblt.n\t60e <__gridxc_alloc_MOD_options.constprop.2+0x242>\n-\tldr\tr5, [r3, #8]\n-\tldr.w\tr8, [r3, #16]\n-\tldr\tr4, [r2, #8]\n-\tldr.w\tlr, [r2, #16]\n-\tb.n\t4da <__gridxc_alloc_MOD_options.constprop.2+0x10e>\n-\tldr\tr2, [pc, #52]\t@ (640 <__gridxc_alloc_MOD_options.constprop.2+0x274>)\n+\tstr\tr5, [sp, #8]\n+\tb.n\t46a <__gridxc_alloc_MOD_options.constprop.2+0x9e>\n+\tcmp\tip, lr\n+\tbgt.n\t5e4 <__gridxc_alloc_MOD_options.constprop.2+0x218>\n+\tldr\tr5, [sp, #4]\n+\tcmp\tsl, r5\n+\tbgt.n\t5e4 <__gridxc_alloc_MOD_options.constprop.2+0x218>\n+\tldr\tr5, [sp, #8]\n+\tcmp\tr5, fp\n+\tblt.n\t5e4 <__gridxc_alloc_MOD_options.constprop.2+0x218>\n+\tldr\tr6, [r3, #8]\n+\tldr.w\tr9, [r3, #16]\n+\tldr\tr5, [r2, #8]\n+\tldr.w\tr8, [r2, #16]\n+\tb.n\t4cc <__gridxc_alloc_MOD_options.constprop.2+0x100>\n+\tldr\tr2, [pc, #52]\t@ (614 <__gridxc_alloc_MOD_options.constprop.2+0x248>)\n \tadd\tr2, pc\n-\tb.n\t594 <__gridxc_alloc_MOD_options.constprop.2+0x1c8>\n-\tldr\tr4, [r2, #8]\n+\tb.n\t56a <__gridxc_alloc_MOD_options.constprop.2+0x19e>\n+\tldr\tr5, [r2, #8]\n \tldr\tr2, [r2, #16]\n \tstr\tr2, [sp, #24]\n \tldr\tr2, [r3, #8]\n-\tstr\tr4, [sp, #20]\n+\tstr\tr5, [sp, #20]\n \tldr\tr3, [r3, #16]\n \tstr\tr2, [sp, #12]\n-\tb.n\t4e2 <__gridxc_alloc_MOD_options.constprop.2+0x116>\n-\tnop\n-\t.word\t0x00000246\n+\tb.n\t4d4 <__gridxc_alloc_MOD_options.constprop.2+0x108>\n+\t.word\t0x0000021a\n R_ARM_REL32\t.bss\n-\t.word\t0x000001f8\n+\t.word\t0x000001cc\n R_ARM_REL32\t.bss\n-\t.word\t0x0000013e\n+\t.word\t0x00000120\n R_ARM_REL32\t.bss\n-\t.word\t0x00000132\n+\t.word\t0x00000114\n R_ARM_REL32\t.bss\n-\t.word\t0x000000b6\n+\t.word\t0x000000b4\n R_ARM_REL32\t.data\n-\t.word\t0x000000a8\n+\t.word\t0x000000a6\n R_ARM_REL32\t.bss\n-\t.word\t0x0000009c\n+\t.word\t0x0000009a\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005c\n+\t.word\t0x0000005a\n R_ARM_REL32\t.data\n-\t.word\t0x00000032\n+\t.word\t0x00000030\n R_ARM_REL32\t.data\n \n-00000644 <__gridxc_alloc_MOD_options.constprop.3>:\n+00000618 <__gridxc_alloc_MOD_options.constprop.3>:\n __gridxc_alloc_MOD_options.constprop.3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr\tr4, [pc, #856]\t@ (9a4 <__gridxc_alloc_MOD_options.constprop.3+0x360>)\n-\tldr\tr3, [r3, #0]\n-\tsub\tsp, #140\t@ 0x8c\n-\tadd\tr4, pc\n+\tldr.w\tr8, [r3]\n+\tldr\tr3, [r0, #0]\n+\tsub\tsp, #52\t@ 0x34\n+\tldr\tr0, [pc, #836]\t@ (96c <__gridxc_alloc_MOD_options.constprop.3+0x354>)\n+\tldr.w\tr9, [r2]\n+\tadd\tr0, pc\n \tldr\tr1, [r1, #0]\n-\tldr\tr0, [r0, #0]\n-\tstr\tr1, [sp, #4]\n-\tldr\tr5, [r4, #0]\n-\tldr\tr2, [r2, #0]\n-\tldr\tr1, [r3, #0]\n-\tcbz\tr5, 6be <__gridxc_alloc_MOD_options.constprop.3+0x7a>\n-\tldr.w\tlr, [r2]\n-\tldr.w\tr9, [r3, #4]\n-\tldr.w\tsl, [r2, #4]\n-\tcmp\tlr, r1\n-\tbne.n\t702 <__gridxc_alloc_MOD_options.constprop.3+0xbe>\n-\tcmp\tr9, sl\n-\tbne.n\t702 <__gridxc_alloc_MOD_options.constprop.3+0xbe>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n-\tcmp\tr5, r4\n-\tldr\tr4, [r3, #12]\n-\tstr\tr4, [sp, #8]\n-\tbne.w\t8a4 <__gridxc_alloc_MOD_options.constprop.3+0x260>\n-\tldr\tr5, [r2, #12]\n-\tstr\tr5, [sp, #12]\n-\tcmp\tr4, r5\n-\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tcmp\tr7, fp\n-\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr4, [r3, #20]\n-\tldr\tr5, [r2, #20]\n-\tcmp\tr4, r5\n-\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr6, [r3, #24]\n-\tldr\tr4, [r2, #24]\n+\tldr.w\tr2, [r8]\n+\tldr\tr4, [r0, #0]\n+\tcmp\tr4, #0\n+\tbeq.n\t6c4 <__gridxc_alloc_MOD_options.constprop.3+0xac>\n+\tldr.w\tfp, [r9]\n+\tldr.w\tr0, [r8, #4]\n+\tldr.w\tlr, [r9, #4]\n+\tcmp\tfp, r2\n+\tstr\tr0, [sp, #4]\n+\tbne.n\t6fe <__gridxc_alloc_MOD_options.constprop.3+0xe6>\n+\tcmp\tr0, lr\n+\tbne.n\t6fe <__gridxc_alloc_MOD_options.constprop.3+0xe6>\n+\tldr.w\tr0, [r9, #8]\n+\tldr.w\tsl, [r8, #8]\n+\tcmp\tsl, r0\n+\tldr.w\tr0, [r8, #12]\n+\tstr\tr0, [sp, #8]\n+\titt\tne\n+\tldrne.w\tr0, [r9, #12]\n+\tstrne\tr0, [sp, #12]\n+\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xf2>\n+\tldr.w\tr4, [r9, #12]\n+\tstr\tr4, [sp, #12]\n+\tcmp\tr0, r4\n+\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xf2>\n+\tldr.w\tr6, [r8, #16]\n+\tldr.w\tr4, [r9, #16]\n \tcmp\tr6, r4\n-\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr6, [r3, #28]\n-\tldr.w\tip, [r2, #28]\n-\tcmp\tr6, ip\n-\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr3, [pc, #760]\t@ (9a8 <__gridxc_alloc_MOD_options.constprop.3+0x364>)\n+\tbne.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xf2>\n+\tldr.w\tr0, [r9, #20]\n+\tldr.w\tr7, [r8, #20]\n+\tstr\tr0, [sp, #20]\n+\tcmp\tr7, r0\n+\tbne.w\t882 <__gridxc_alloc_MOD_options.constprop.3+0x26a>\n+\tldr.w\tr0, [r9, #24]\n+\tldr.w\tip, [r8, #24]\n+\tcmp\tip, r0\n+\tldr.w\tr0, [r8, #28]\n+\tstr\tr0, [sp, #16]\n+\titt\tne\n+\tldrne.w\tr0, [r9, #28]\n+\tstrne\tr0, [sp, #24]\n+\tbne.n\t71c <__gridxc_alloc_MOD_options.constprop.3+0x104>\n+\tldr.w\tr4, [r9, #28]\n+\tstr\tr4, [sp, #24]\n+\tcmp\tr0, r4\n+\tbne.n\t71c <__gridxc_alloc_MOD_options.constprop.3+0x104>\n+\tldr\tr3, [pc, #700]\t@ (970 <__gridxc_alloc_MOD_options.constprop.3+0x358>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstrd\tr2, r2, [r3, #4]\n \tstr\tr2, [r3, #12]\n-\tadd\tsp, #140\t@ 0x8c\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [r3, #16]\n-\tstrd\tr5, r5, [r4, #8]\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr2, [r3, #20]\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr2, [r3, #24]\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr2, [r3, #28]\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvldr\td17, [sp, #64]\t@ 0x40\n-\tldr\tr2, [r3, #4]\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [r3, #8]\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr3, [r3, #12]\n-\tstr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr2, [r3, #0]\n+\tldr.w\tr2, [r8, #8]\n+\tldr.w\tr1, [r8, #16]\n+\tstr\tr2, [r3, #8]\n+\tldr.w\tr2, [r8, #24]\n+\tstr\tr1, [r3, #16]\n+\tstr\tr2, [r3, #24]\n+\tldr.w\tr1, [r8, #4]\n+\tldr.w\tr2, [r8, #12]\n+\tstr\tr1, [r3, #4]\n+\tstr\tr2, [r3, #12]\n+\tldr.w\tr1, [r8, #20]\n+\tldr.w\tr2, [r8, #28]\n+\tstr\tr1, [r3, #20]\n+\tstr\tr2, [r3, #28]\n \tmovs\tr3, #1\n-\tvldr\td18, [sp, #40]\t@ 0x28\n-\tvldr\td19, [sp, #48]\t@ 0x30\n-\tstr\tr3, [r4, #4]\n-\tvst1.32\t{d18-d19}, [r0]!\n-\tvst1.32\t{d16-d17}, [r0]\n-\tadd\tsp, #140\t@ 0x8c\n+\tstrd\tr4, r4, [r0, #8]\n+\tstr\tr3, [r0, #4]\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr4, [r3, #12]\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [r2, #12]\n-\tstr\tr4, [sp, #12]\n-\tldr\tr4, [sp, #180]\t@ 0xb4\n-\tcmp\tr4, #0\n-\tbeq.w\t862 <__gridxc_alloc_MOD_options.constprop.3+0x21e>\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #20]\n-\tcmp\tlr, r1\n-\tbgt.w\t86c <__gridxc_alloc_MOD_options.constprop.3+0x228>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n-\tstr\tr4, [sp, #16]\n-\tcmp\tr4, r5\n-\tbgt.w\t86c <__gridxc_alloc_MOD_options.constprop.3+0x228>\n-\tldr.w\tfp, [r2, #16]\n-\tldr\tr7, [r3, #16]\n-\tcmp\tfp, r7\n-\tbgt.w\t86c <__gridxc_alloc_MOD_options.constprop.3+0x228>\n-\tldr\tr4, [r2, #24]\n-\tldr\tr6, [r3, #24]\n-\tstr\tr4, [sp, #24]\n-\tcmp\tr6, r4\n-\tblt.w\t86c <__gridxc_alloc_MOD_options.constprop.3+0x228>\n-\tldr\tr4, [sp, #20]\n-\tcmp\tsl, r9\n-\tstr.w\tsl, [sp, #28]\n-\teor.w\tr8, r4, #1\n-\tblt.w\t990 <__gridxc_alloc_MOD_options.constprop.3+0x34c>\n-\tldrd\tr5, r4, [sp, #8]\n-\tcmp\tr4, r5\n-\tblt.w\t926 <__gridxc_alloc_MOD_options.constprop.3+0x2e2>\n-\tldr\tr4, [r2, #20]\n-\tstr\tr4, [sp, #32]\n-\tmov\tr5, r4\n-\tldr\tr4, [r3, #20]\n-\tcmp\tr5, r4\n-\tblt.w\t968 <__gridxc_alloc_MOD_options.constprop.3+0x324>\n-\tldr\tr6, [r3, #28]\n-\tldr.w\tip, [r2, #28]\n-\tcmp\tr6, ip\n-\tbgt.w\t97c <__gridxc_alloc_MOD_options.constprop.3+0x338>\n-\tcmp.w\tr8, #0\n-\tbne.n\t6ac <__gridxc_alloc_MOD_options.constprop.3+0x68>\n-\tldr\tr5, [r3, #8]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tldr\tr4, [r2, #8]\n-\tstr\tr4, [sp, #16]\n-\tldr\tr4, [r2, #24]\n-\tstr\tr4, [sp, #24]\n-\tldr.w\tr8, [pc, #544]\t@ 9ac <__gridxc_alloc_MOD_options.constprop.3+0x368>\n-\tmovs\tr4, #1\n-\tadd\tr8, pc\n-\tstrd\tr4, r4, [r8, #4]\n-\tldr\tr4, [sp, #176]\t@ 0xb0\n-\tcmp\tr4, #0\n-\tbeq.n\t896 <__gridxc_alloc_MOD_options.constprop.3+0x252>\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tadd.w\tr8, r3, #20\n-\tldr\tr4, [sp, #8]\n-\tvld1.32\t{d7}, [r8]\n-\tldr.w\tr8, [pc, #516]\t@ 9b0 <__gridxc_alloc_MOD_options.constprop.3+0x36c>\n-\tstrd\tr4, r7, [sp, #128]\t@ 0x80\n-\tadd\tr8, pc\n-\tstrd\tr9, r5, [sp, #120]\t@ 0x78\n-\tldr\tr4, [sp, #36]\t@ 0x24\n-\tvldr\td16, [sp, #120]\t@ 0x78\n-\tvldr\td17, [sp, #128]\t@ 0x80\n-\tstr.w\tr4, [r8, #12]\n-\tldr\tr4, [sp, #20]\n-\tvmov.32\tr8, d7[1]\n-\tvstr\ts14, [sp, #36]\t@ 0x24\n-\tcmp\tr4, #0\n-\tbeq.n\t8aa <__gridxc_alloc_MOD_options.constprop.3+0x266>\n-\tcmp\tsl, r9\n-\tmov\tr3, sl\n-\tit\tge\n-\tmovge\tr3, r9\n-\tstr\tr3, [sp, #28]\n-\tldrd\tr2, r3, [sp, #8]\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr3, r2\n+\tldr.w\tr0, [r8, #12]\n+\tstr\tr0, [sp, #8]\n+\tldr.w\tr0, [r9, #12]\n+\tstr\tr0, [sp, #12]\n+\tldr.w\tr0, [r9, #20]\n+\tstr\tr0, [sp, #20]\n+\tldr.w\tr0, [r8, #28]\n+\tstr\tr0, [sp, #16]\n+\tldr.w\tr0, [r9, #28]\n+\tstr\tr0, [sp, #24]\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tcmp\tr0, #0\n+\tbeq.w\t85a <__gridxc_alloc_MOD_options.constprop.3+0x242>\n+\tldr\tr0, [r0, #0]\n+\tstr\tr0, [sp, #28]\n+\tcmp\tfp, r2\n+\tbgt.w\t864 <__gridxc_alloc_MOD_options.constprop.3+0x24c>\n+\tldr.w\tr0, [r9, #8]\n+\tldr.w\tsl, [r8, #8]\n+\tcmp\tr0, sl\n+\tbgt.w\t864 <__gridxc_alloc_MOD_options.constprop.3+0x24c>\n+\tldr.w\tr4, [r9, #16]\n+\tldr.w\tr6, [r8, #16]\n+\tcmp\tr4, r6\n+\tbgt.w\t864 <__gridxc_alloc_MOD_options.constprop.3+0x24c>\n+\tldr.w\tr5, [r9, #24]\n+\tldr.w\tip, [r8, #24]\n+\tstr\tr5, [sp, #32]\n+\tcmp\tip, r5\n+\tblt.w\t864 <__gridxc_alloc_MOD_options.constprop.3+0x24c>\n+\tldr\tr7, [sp, #28]\n+\tstr.w\tlr, [sp, #36]\t@ 0x24\n+\teor.w\tr7, r7, #1\n+\tmov\tr5, r7\n+\tldr\tr7, [sp, #4]\n+\tcmp\tlr, r7\n+\tblt.w\t95e <__gridxc_alloc_MOD_options.constprop.3+0x346>\n+\tldrd\tr4, r0, [sp, #8]\n+\tcmp\tr0, r4\n+\tblt.w\t8e8 <__gridxc_alloc_MOD_options.constprop.3+0x2d0>\n+\tldr.w\tr7, [r8, #20]\n+\tldr\tr0, [sp, #20]\n+\tcmp\tr0, r7\n+\tblt.w\t954 <__gridxc_alloc_MOD_options.constprop.3+0x33c>\n+\tldr\tr0, [sp, #16]\n+\tldr\tr4, [sp, #24]\n+\tcmp\tr0, r4\n+\tbgt.w\t932 <__gridxc_alloc_MOD_options.constprop.3+0x31a>\n+\tcmp\tr5, #0\n+\tbne.n\t6b2 <__gridxc_alloc_MOD_options.constprop.3+0x9a>\n+\tldr.w\tsl, [r8, #8]\n+\tldr.w\tr0, [r9, #8]\n+\tldr.w\tr6, [r8, #16]\n+\tldr.w\tr4, [r9, #16]\n+\tldr.w\tr5, [r9, #24]\n+\tstr\tr5, [sp, #32]\n+\tldr\tr7, [pc, #456]\t@ (974 <__gridxc_alloc_MOD_options.constprop.3+0x35c>)\n+\tmov.w\tip, #1\n+\tldr\tr5, [sp, #88]\t@ 0x58\n+\tadd\tr7, pc\n+\tstrd\tip, ip, [r7, #4]\n+\tcmp\tr5, #0\n+\tbeq.n\t878 <__gridxc_alloc_MOD_options.constprop.3+0x260>\n+\tldr.w\tip, [r5]\n+\tldr.w\tr5, [r8, #20]\n+\tldr\tr7, [pc, #436]\t@ (978 <__gridxc_alloc_MOD_options.constprop.3+0x360>)\n+\tstr\tr5, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #16]\n+\tadd\tr7, pc\n+\tstr\tr5, [sp, #40]\t@ 0x28\n+\tldr\tr5, [sp, #28]\n+\tstr.w\tip, [r7, #12]\n+\tldr.w\tip, [r8, #24]\n+\tcmp\tr5, #0\n+\tbeq.n\t890 <__gridxc_alloc_MOD_options.constprop.3+0x278>\n+\tldr\tr5, [sp, #4]\n+\tmov\tr7, lr\n+\tstr\tr5, [r3, #4]\n+\tcmp\tlr, r5\n+\tstr\tr6, [r3, #16]\n+\tit\tge\n+\tmovge\tr7, r5\n+\tstr\tr7, [sp, #36]\t@ 0x24\n+\tldrd\tr7, r5, [sp, #8]\n+\tstr\tr7, [r3, #12]\n+\tstr.w\tsl, [r3, #8]\n+\tcmp\tr5, r7\n+\tstr.w\tip, [r3, #24]\n+\tit\tge\n+\tmovge\tr5, r7\n+\tldr\tr7, [sp, #44]\t@ 0x2c\n+\tmov\tr9, r5\n+\tldr\tr5, [sp, #20]\n+\tstr\tr7, [r3, #20]\n+\tcmp\tr5, r7\n \tit\tge\n-\tmovge\tr3, r2\n-\tmov\tsl, r3\n-\tldrd\tr2, r3, [sp, #32]\n-\tcmp\tr3, r2\n+\tmovge\tr5, r7\n+\tldr\tr7, [sp, #40]\t@ 0x28\n+\tmov\tr8, r5\n+\tldr\tr5, [sp, #24]\n+\tcmp\tr5, r7\n \tit\tge\n-\tmovge\tr3, r2\n-\tcmp\tr4, r5\n-\tmov\tr9, r3\n-\tldr\tr3, [sp, #24]\n+\tmovge\tr5, r7\n+\tcmp\tfp, r2\n+\tmov\tlr, r5\n \tit\tlt\n-\tmovlt\tr4, r5\n-\tcmp\tfp, r7\n+\tmovlt\tfp, r2\n+\tldr\tr5, [sp, #32]\n+\tcmp\tr0, sl\n \tit\tlt\n-\tmovlt\tfp, r7\n-\tcmp\tr8, r3\n+\tmovlt\tr0, sl\n+\tcmp\tr4, r6\n \tit\tlt\n-\tmovlt\tr8, r3\n-\tadds\tr3, r0, #4\n-\tcmp\tip, r6\n-\tmov\tr2, ip\n-\tit\tge\n-\tmovge\tr2, r6\n-\tcmp\tlr, r1\n-\tvst1.32\t{d16-d17}, [r3]\n+\tmovlt\tr4, r6\n+\tcmp\tr5, ip\n \tit\tlt\n-\tmovlt\tlr, r1\n-\tadd.w\tr3, r0, #20\n-\tvst1.32\t{d7}, [r3]\n-\tldr\tr3, [sp, #28]\n-\tstr\tr6, [r0, #28]\n-\tstr\tr1, [r0, #0]\n-\tstrd\tr3, r4, [sp, #92]\t@ 0x5c\n-\tstr.w\tlr, [sp, #88]\t@ 0x58\n-\tstr.w\tsl, [sp, #100]\t@ 0x64\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvldr\td17, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #4]\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tstrd\tfp, r9, [sp, #72]\t@ 0x48\n-\tstrd\tr8, r2, [sp, #80]\t@ 0x50\n-\tvldr\td16, [sp, #72]\t@ 0x48\n-\tvldr\td17, [sp, #80]\t@ 0x50\n-\tvst1.32\t{d16-d17}, [r3]\n-\tadd\tsp, #140\t@ 0x8c\n+\tmovlt\tr5, ip\n+\tmov\tr6, r7\n+\tstr\tr6, [r3, #28]\n+\tstr\tr2, [r3, #0]\n+\tldr\tr3, [sp, #36]\t@ 0x24\n+\tstr.w\tfp, [r1]\n+\tstr\tr0, [r1, #8]\n+\tstr\tr4, [r1, #16]\n+\tstr\tr5, [r1, #24]\n+\tstr\tr3, [r1, #4]\n+\tstr.w\tr9, [r1, #12]\n+\tstr.w\tr8, [r1, #20]\n+\tstr.w\tlr, [r1, #28]\n+\tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr4, [pc, #336]\t@ (9b4 <__gridxc_alloc_MOD_options.constprop.3+0x370>)\n-\tadd\tr4, pc\n-\tldr\tr4, [r4, #4]\n-\tstr\tr4, [sp, #20]\n-\tb.n\t716 <__gridxc_alloc_MOD_options.constprop.3+0xd2>\n-\tmov.w\tr8, #0\n-\tcmp\tsl, r9\n-\tstr.w\tsl, [sp, #28]\n-\tbge.w\t750 <__gridxc_alloc_MOD_options.constprop.3+0x10c>\n-\tldr\tr5, [r3, #8]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tldr\tr4, [r2, #8]\n-\tstr\tr4, [sp, #16]\n-\tldr\tr4, [r2, #20]\n-\tstr\tr4, [sp, #32]\n-\tldr\tr4, [r2, #24]\n-\tldr\tr6, [r3, #28]\n-\tldr.w\tip, [r2, #28]\n-\tstr\tr4, [sp, #24]\n-\tb.n\t78a <__gridxc_alloc_MOD_options.constprop.3+0x146>\n-\tldr.w\tr8, [pc, #288]\t@ 9b8 <__gridxc_alloc_MOD_options.constprop.3+0x374>\n-\tadd\tr8, pc\n-\tldr.w\tr4, [r8]\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tb.n\t7a0 <__gridxc_alloc_MOD_options.constprop.3+0x15c>\n-\tldr\tr4, [r2, #12]\n-\tstr\tr4, [sp, #12]\n-\tb.n\t70a <__gridxc_alloc_MOD_options.constprop.3+0xc6>\n-\tldr\tr4, [r2, #8]\n-\tstr\tr4, [sp, #16]\n-\tldr\tr4, [r3, #12]\n-\tstr\tr4, [sp, #8]\n-\tldr\tr5, [r3, #8]\n-\tldr\tr4, [r2, #12]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tldr\tr6, [r3, #24]\n-\tstr\tr4, [sp, #12]\n-\tldr\tr4, [r2, #24]\n-\tstr\tr4, [sp, #24]\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr9, sl\n-\tit\tlt\n-\tmovlt\tr9, sl\n-\tldr.w\tr8, [sp, #24]\n-\tcmp\tr5, r4\n-\tldr.w\tsl, [sp, #12]\n-\tit\tge\n-\tmovge\tr5, r4\n-\tcmp\tr7, fp\n+\tldr\tr0, [pc, #288]\t@ (97c <__gridxc_alloc_MOD_options.constprop.3+0x364>)\n+\tadd\tr0, pc\n+\tldr\tr0, [r0, #4]\n+\tstr\tr0, [sp, #28]\n+\tb.n\t728 <__gridxc_alloc_MOD_options.constprop.3+0x110>\n+\tldr\tr0, [sp, #4]\n+\tstr.w\tlr, [sp, #36]\t@ 0x24\n+\tcmp\tr0, lr\n+\titt\tle\n+\tmovle\tr0, #0\n+\tmovle\tr5, r0\n+\tble.w\t76e <__gridxc_alloc_MOD_options.constprop.3+0x156>\n+\tb.n\t792 <__gridxc_alloc_MOD_options.constprop.3+0x17a>\n+\tldr\tr7, [pc, #260]\t@ (980 <__gridxc_alloc_MOD_options.constprop.3+0x368>)\n+\tadd\tr7, pc\n+\tldr.w\tip, [r7]\n+\tb.n\t7be <__gridxc_alloc_MOD_options.constprop.3+0x1a6>\n+\tldr.w\tr0, [r8, #28]\n+\tstr\tr0, [sp, #16]\n+\tldr.w\tr0, [r9, #28]\n+\tstr\tr0, [sp, #24]\n+\tb.n\t71c <__gridxc_alloc_MOD_options.constprop.3+0x104>\n+\tldr\tr7, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #4]\n+\tldr.w\tr9, [sp, #12]\n+\tcmp\tr5, lr\n+\tit\tlt\n+\tmovlt\tr5, lr\n+\tcmp\tsl, r0\n+\tstr\tr5, [r3, #4]\n \tit\tge\n-\tmovge\tr7, fp\n-\tcmp\tr6, r8\n+\tmovge\tsl, r0\n+\tldr\tr5, [sp, #32]\n+\tcmp\tr6, r4\n \tit\tge\n-\tmovge\tr6, r8\n-\tstr\tr6, [r0, #24]\n-\tstrd\tr9, r5, [sp, #104]\t@ 0x68\n-\tldr\tr5, [sp, #8]\n-\tstr\tr7, [sp, #116]\t@ 0x74\n-\tcmp\tr5, sl\n-\tit\tlt\n-\tmovlt\tr5, sl\n-\tstr\tr5, [sp, #112]\t@ 0x70\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tadds\tr5, r0, #4\n-\tldr.w\tr9, [r2, #20]\n-\tcmp\tr1, lr\n-\tldr\tr2, [r2, #28]\n+\tmovge\tr6, r4\n+\tstr\tr6, [r3, #16]\n+\tcmp\tip, r5\n+\tmov\tr6, ip\n+\tldrd\tr8, lr, [sp, #20]\n \tit\tge\n-\tmovge\tr1, lr\n-\tvst1.32\t{d16-d17}, [r5]\n-\tldr\tr5, [r3, #20]\n-\tldr\tr6, [r3, #28]\n-\tcmp\tr5, r9\n+\tmovge\tr6, r5\n+\tstr\tr6, [r3, #24]\n+\tldr\tr6, [sp, #8]\n+\tstr.w\tsl, [r3, #8]\n+\tcmp\tr6, r9\n \tit\tlt\n-\tmovlt\tr5, r9\n-\tcmp\tr6, r2\n+\tmovlt\tr6, r9\n+\tcmp\tr7, r8\n \tit\tlt\n-\tmovlt\tr6, r2\n-\tstr\tr5, [r0, #20]\n-\tb.n\t828 <__gridxc_alloc_MOD_options.constprop.3+0x1e4>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tstr\tr4, [sp, #16]\n-\tcmp.w\tr8, #0\n-\tbeq.n\t886 <__gridxc_alloc_MOD_options.constprop.3+0x242>\n-\tldr\tr6, [r3, #24]\n-\tldr\tr4, [r2, #24]\n-\tstr\tr4, [sp, #24]\n-\tldr.w\tip, [pc, #124]\t@ 9bc <__gridxc_alloc_MOD_options.constprop.3+0x378>\n-\tmov.w\tr8, #1\n-\tldr\tr4, [sp, #176]\t@ 0xb0\n-\tadd\tip, pc\n-\tstrd\tr8, r8, [ip, #4]\n-\tcbz\tr4, 958 <__gridxc_alloc_MOD_options.constprop.3+0x314>\n-\tldr\tr4, [r4, #0]\n-\tstr.w\tr4, [ip, #12]\n-\tb.n\t8c4 <__gridxc_alloc_MOD_options.constprop.3+0x280>\n-\tldr.w\tr8, [pc, #100]\t@ 9c0 <__gridxc_alloc_MOD_options.constprop.3+0x37c>\n+\tmovlt\tr7, r8\n+\tstr\tr7, [r3, #20]\n+\tldr\tr7, [sp, #16]\n+\tcmp\tr2, fp\n+\tit\tge\n+\tmovge\tr2, fp\n+\tstr\tr6, [r3, #12]\n+\tcmp\tr7, lr\n+\tit\tlt\n+\tmovlt\tr7, lr\n+\tstr\tr7, [sp, #40]\t@ 0x28\n+\tmov\tr6, r7\n+\tb.n\t836 <__gridxc_alloc_MOD_options.constprop.3+0x21e>\n+\tldr.w\tsl, [r8, #8]\n+\tcmp\tr5, #0\n+\tbeq.w\t796 <__gridxc_alloc_MOD_options.constprop.3+0x17e>\n+\tldr.w\tr0, [r9, #8]\n+\tldr.w\tr6, [r8, #16]\n+\tldr.w\tr4, [r9, #16]\n+\tldrd\tr7, ip, [r8, #20]\n+\tldr.w\tr5, [r9, #24]\n+\tstr\tr5, [sp, #32]\n+\tldr.w\tr8, [pc, #120]\t@ 984 <__gridxc_alloc_MOD_options.constprop.3+0x36c>\n+\tmov.w\tr9, #1\n+\tldr\tr5, [sp, #88]\t@ 0x58\n \tadd\tr8, pc\n-\tldr.w\tr4, [r8]\n-\tstr.w\tr4, [ip, #12]\n-\tb.n\t8c4 <__gridxc_alloc_MOD_options.constprop.3+0x280>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tstr\tr4, [sp, #16]\n-\tcmp.w\tr8, #0\n-\tbne.n\t938 <__gridxc_alloc_MOD_options.constprop.3+0x2f4>\n-\tb.n\t88a <__gridxc_alloc_MOD_options.constprop.3+0x246>\n-\tldr\tr4, [r2, #8]\n-\tldr\tr5, [r3, #8]\n-\tldr\tr7, [r3, #16]\n-\tldr.w\tfp, [r2, #16]\n-\tstr\tr4, [sp, #16]\n-\tcmp.w\tr8, #0\n-\tbne.n\t938 <__gridxc_alloc_MOD_options.constprop.3+0x2f4>\n-\tb.n\t786 <__gridxc_alloc_MOD_options.constprop.3+0x142>\n-\tcmp.w\tr8, #0\n-\tbne.n\t93e <__gridxc_alloc_MOD_options.constprop.3+0x2fa>\n-\tldr\tr4, [r2, #20]\n-\tldr\tr6, [r3, #28]\n-\tldr.w\tip, [r2, #28]\n-\tstr\tr4, [sp, #32]\n-\tb.n\t78a <__gridxc_alloc_MOD_options.constprop.3+0x146>\n+\tstrd\tr9, r9, [r8, #4]\n+\tcbz\tr5, 922 <__gridxc_alloc_MOD_options.constprop.3+0x30a>\n+\tldr\tr5, [r5, #0]\n+\tstr.w\tr5, [r8, #12]\n+\tb.n\t892 <__gridxc_alloc_MOD_options.constprop.3+0x27a>\n+\tldr.w\tr9, [pc, #100]\t@ 988 <__gridxc_alloc_MOD_options.constprop.3+0x370>\n+\tadd\tr9, pc\n+\tldr.w\tr5, [r9]\n+\tstr.w\tr5, [r8, #12]\n+\tb.n\t892 <__gridxc_alloc_MOD_options.constprop.3+0x27a>\n+\tldr.w\tsl, [r8, #8]\n+\tcmp\tr5, #0\n+\tbeq.w\t796 <__gridxc_alloc_MOD_options.constprop.3+0x17e>\n+\tldr.w\tr5, [r9, #24]\n+\tldr.w\tr0, [r9, #8]\n+\tldr.w\tr6, [r8, #16]\n+\tldr.w\tip, [r8, #24]\n+\tldr.w\tr4, [r9, #16]\n+\tstr\tr5, [sp, #32]\n+\tb.n\t908 <__gridxc_alloc_MOD_options.constprop.3+0x2f0>\n+\tldr.w\tsl, [r8, #8]\n+\tcmp\tr5, #0\n+\tbne.n\t93c <__gridxc_alloc_MOD_options.constprop.3+0x324>\n+\tb.n\t796 <__gridxc_alloc_MOD_options.constprop.3+0x17e>\n+\tcmp\tr5, #0\n+\tbeq.w\t7a8 <__gridxc_alloc_MOD_options.constprop.3+0x190>\n+\tldr.w\tr7, [r8, #20]\n+\tb.n\t908 <__gridxc_alloc_MOD_options.constprop.3+0x2f0>\n \tnop\n-\t.word\t0x00000352\n+\t.word\t0x0000033e\n R_ARM_REL32\t.bss\n-\t.word\t0x000002f4\n+\t.word\t0x000002b6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000218\n+\t.word\t0x000001c0\n R_ARM_REL32\t.bss\n-\t.word\t0x000001fa\n+\t.word\t0x000001ac\n R_ARM_REL32\t.bss\n-\t.word\t0x0000014c\n+\t.word\t0x0000011c\n R_ARM_REL32\t.data\n-\t.word\t0x0000011a\n+\t.word\t0x00000102\n R_ARM_REL32\t.data\n-\t.word\t0x00000070\n+\t.word\t0x0000006e\n R_ARM_REL32\t.bss\n-\t.word\t0x00000060\n+\t.word\t0x0000005e\n R_ARM_REL32\t.data\n \n-000009c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>:\n+0000098c <__gridxc_alloc_MOD_alloc_err.constprop.1>:\n __gridxc_alloc_MOD_alloc_err.constprop.1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3520]\t@ 0xdc0\n+\tstr.w\tr0, [ip, #3528]\t@ 0xdc8\n \tsub.w\tsp, sp, #532\t@ 0x214\n \tmov\tr6, r1\n-\tldr\tr1, [pc, #792]\t@ (cf8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x334>)\n-\tmov\tr7, r2\n-\tldr\tr2, [pc, #792]\t@ (cfc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x338>)\n+\tldr.w\tr1, [pc, #1048]\t@ dbc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x430>\n+\tmov\tr9, r2\n+\tldr.w\tr2, [pc, #1044]\t@ dc0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x434>\n \tmov\tr5, r3\n-\tldr\tr0, [sp, #576]\t@ 0x240\n \tadd\tr1, pc\n+\tldrd\tsl, r0, [sp, #568]\t@ 0x238\n \tstr\tr0, [sp, #4]\n-\tldr\tr0, [sp, #580]\t@ 0x244\n-\tstr\tr0, [sp, #8]\n \tldr\tr2, [r1, r2]\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #524]\t@ 0x20c\n \tmov.w\tr2, #0\n-\tcbz\tr3, a22 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x5e>\n+\tcbz\tr3, 9e8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x5c>\n \tldr\tr5, [r3, #0]\n-\tcbz\tr5, a22 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x5e>\n+\tcbz\tr5, 9e8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x5c>\n \tldr\tr2, [r3, #24]\n \tstr\tr2, [sp, #12]\n \tnegs\tr0, r2\n-\tcbnz\tr2, a10 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4c>\n+\tcbnz\tr2, 9d6 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4a>\n \tmov.w\tr0, #4294967295\t@ 0xffffffff\n \tmovs\tr2, #1\n \tstr\tr2, [sp, #12]\n \tldrd\tr1, r2, [r3, #40]\t@ 0x28\n \tldr\tr3, [r3, #36]\t@ 0x24\n \tsubs\tr2, r2, r1\n \tstr\tr3, [sp, #20]\n \tadds\tr2, #1\n \tsubs\tr3, r0, r3\n-\tstr\tr2, [sp, #16]\n+\tstr\tr2, [sp, #8]\n \tstr\tr3, [sp, #24]\n-\tldr.w\tr9, [pc, #732]\t@ d00 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x33c>\n-\tadd\tr9, pc\n-\tldr.w\tr3, [r9, #16]\n-\tcbnz\tr3, a50 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x8c>\n-\tldr\tr2, [pc, #724]\t@ (d04 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x340>)\n-\tldr\tr3, [pc, #712]\t@ (cfc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x338>)\n+\tldr\tr7, [pc, #984]\t@ (dc4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x438>)\n+\tadd\tr7, pc\n+\tldr\tr3, [r7, #16]\n+\tcbnz\tr3, a0e <__gridxc_alloc_MOD_alloc_err.constprop.1+0x82>\n+\tldr\tr2, [pc, #980]\t@ (dc8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x43c>)\n+\tldr\tr3, [pc, #972]\t@ (dc0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x434>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #524]\t@ 0x20c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\te80 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4bc>\n+\tbne.w\tdb6 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x42a>\n \tadd.w\tsp, sp, #532\t@ 0x214\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tadd\tr4, sp, #48\t@ 0x30\n-\tvldr\td16, [pc, #660]\t@ ce8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x324>\n-\tldr\tr3, [pc, #688]\t@ (d08 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x344>)\n-\tmov.w\tfp, #128\t@ 0x80\n+\tldr\tr3, [pc, #952]\t@ (dcc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x440>)\n+\tmov.w\tr8, #128\t@ 0x80\n \tmov\tr0, r4\n-\tadd.w\tsl, sp, #396\t@ 0x18c\n-\tvstr\td16, [sp, #48]\t@ 0x30\n \tadd\tr3, pc\n-\tstr.w\tfp, [r4, #72]\t@ 0x48\n-\tadd.w\tr8, sp, #44\t@ 0x2c\n+\tadd.w\tfp, sp, #396\t@ 0x18c\n+\tstr.w\tr8, [r4, #72]\t@ 0x48\n+\tmov.w\tr2, #16512\t@ 0x4080\n \tstr\tr3, [r4, #8]\n \tmovs\tr3, #0\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n \tstr\tr3, [r4, #48]\t@ 0x30\n \tmovw\tr3, #1588\t@ 0x634\n \tstr\tr3, [r4, #12]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #644]\t@ (d0c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x348>)\n+\tldr\tr1, [pc, #908]\t@ (dd0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x444>)\n \tmovs\tr2, #32\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tadd.w\tr1, r9, #16\n+\tadd.w\tr1, r7, #16\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, fp\n-\tadd.w\tfp, sp, #40\t@ 0x28\n-\tmov\tr3, sl\n+\tadd\tr7, sp, #40\t@ 0x28\n+\tmov\tr2, r8\n+\tadd.w\tr8, sp, #44\t@ 0x2c\n+\tmov\tr3, fp\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #604]\t@ (d10 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x34c>)\n-\tldr.w\tr9, [fp]\n+\tldr\tr3, [pc, #864]\t@ (dd4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x448>)\n+\tldr\tr1, [pc, #864]\t@ (dd8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x44c>)\n \tadd\tr3, pc\n-\tldr\tr1, [pc, #600]\t@ (d14 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x350>)\n+\tldr\tr2, [r7, #0]\n \tldr.w\tr0, [r8]\n-\tmov\tr2, r9\n \tadd\tr1, pc\n-\tstr\tr0, [sp, #28]\n+\tstr\tr2, [sp, #16]\n \tldr\tr3, [r3, #0]\n+\tstr\tr0, [sp, #28]\n \tblx\tr3\n-\tcmp.w\tr9, #0\n-\tbgt.w\td64 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x3a0>\n+\tldr\tr2, [sp, #16]\n+\tcmp\tr2, #0\n+\tbgt.w\tcb2 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x326>\n \tcmp\tr6, #0\n \tit\tne\n-\tcmpne\tr7, #0\n-\tit\tne\n+\tcmpne.w\tr9, #0\n+\tite\tne\n \tmovne\tr3, #1\n-\tit\teq\n \tmoveq\tr3, #0\n-\tbne.w\td7c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x3b8>\n+\tbne.w\td3a <__gridxc_alloc_MOD_alloc_err.constprop.1+0x3ae>\n \tcmp\tr6, #0\n-\tbeq.w\te0c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x448>\n-\tvldr\td16, [pc, #508]\t@ ce8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x324>\n-\tmovs\tr7, #128\t@ 0x80\n+\tbeq.w\tcc2 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x336>\n \tstr\tr3, [r4, #48]\t@ 0x30\n+\tmov.w\tr9, #128\t@ 0x80\n+\tldr\tr3, [pc, #812]\t@ (ddc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x450>)\n \tmov\tr0, r4\n-\tldr\tr3, [pc, #544]\t@ (d18 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x354>)\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n+\tstr.w\tr9, [r4, #72]\t@ 0x48\n+\tmov.w\tr2, #16512\t@ 0x4080\n \tadd\tr3, pc\n-\tvstr\td16, [sp, #48]\t@ 0x30\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n \tstr\tr3, [r4, #8]\n \tmovw\tr3, #1596\t@ 0x63c\n-\tstr\tr7, [r4, #72]\t@ 0x48\n \tstr\tr3, [r4, #12]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #524]\t@ (d1c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x358>)\n+\tldr\tr1, [pc, #776]\t@ (de0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x454>)\n \tmovs\tr2, #17\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr1, r6\n-\tldr\tr2, [sp, #4]\n+\tmov\tr2, sl\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tldr\tr1, [pc, #504]\t@ (d20 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x35c>)\n+\tldr\tr1, [pc, #760]\t@ (de4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x458>)\n \tmovs\tr2, #21\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, sl\n-\tmov\tr2, r7\n+\tmov\tr3, fp\n+\tmov\tr2, r9\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #480]\t@ (d24 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x360>)\n-\tldr\tr1, [pc, #480]\t@ (d28 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x364>)\n+\tldr\tr3, [pc, #732]\t@ (de8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x45c>)\n+\tldr\tr1, [pc, #736]\t@ (dec <__gridxc_alloc_MOD_alloc_err.constprop.1+0x460>)\n \tadd\tr3, pc\n-\tldr.w\tr7, [r8]\n+\tldr.w\tr9, [r8]\n \tadd\tr1, pc\n-\tldr.w\tr6, [fp]\n+\tldr\tr6, [r7, #0]\n \tadds\tr1, #8\n \tldr\tr3, [r3, #0]\n \tmov\tr2, r6\n-\tmov\tr0, r7\n+\tmov\tr0, r9\n \tblx\tr3\n \tcmp\tr6, #0\n-\tbgt.w\te04 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x440>\n+\tbgt.w\tcba <__gridxc_alloc_MOD_alloc_err.constprop.1+0x32e>\n \tcmp\tr5, #0\n-\tbeq.w\tcac <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2e8>\n-\tvldr\td16, [pc, #388]\t@ cf0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x32c>\n+\tbeq.w\tc80 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2f4>\n+\tldr\tr3, [pc, #704]\t@ (df0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x464>)\n \tmovs\tr6, #128\t@ 0x80\n-\tldr\tr3, [pc, #444]\t@ (d2c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x368>)\n \tmov\tr0, r4\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n+\tstr\tr6, [r4, #72]\t@ 0x48\n \tadd\tr3, pc\n-\tvstr\td16, [sp, #48]\t@ 0x30\n \tstr\tr3, [r4, #8]\n-\tldr\tr3, [pc, #432]\t@ (d30 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x36c>)\n-\tstr\tr6, [r4, #72]\t@ 0x48\n+\tldr\tr3, [pc, #696]\t@ (df4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x468>)\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n \tadd\tr3, pc\n \tstr\tr3, [r4, #52]\t@ 0x34\n \tmovs\tr3, #0\n \tstr\tr3, [r4, #48]\t@ 0x30\n \tmovs\tr3, #3\n \tstr\tr3, [r4, #56]\t@ 0x38\n \tmovw\tr3, #1604\t@ 0x644\n \tstr\tr3, [r4, #12]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #408]\t@ (d34 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x370>)\n+\tldr\tr1, [pc, #660]\t@ (df8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x46c>)\n \tmovs\tr2, #31\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tmov\tr2, r6\n-\tmov\tr3, sl\n+\tmov\tr3, fp\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #384]\t@ (d38 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x374>)\n-\tldr\tr1, [pc, #384]\t@ (d3c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x378>)\n+\tldr\tr3, [pc, #636]\t@ (dfc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x470>)\n+\tldr\tr1, [pc, #636]\t@ (e00 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x474>)\n \tadd\tr3, pc\n-\tldr.w\tr6, [fp]\n-\tldr.w\tr7, [r8]\n+\tldr\tr6, [r7, #0]\n+\tldr.w\tr9, [r8]\n \tadd\tr1, pc\n \tadds\tr1, #20\n \tmov\tr2, r6\n \tldr\tr3, [r3, #0]\n-\tmov\tr0, r7\n+\tmov\tr0, r9\n \tblx\tr3\n \tcmp\tr6, #0\n-\tble.n\tbda <__gridxc_alloc_MOD_alloc_err.constprop.1+0x216>\n-\tmov\tr0, r7\n+\tble.n\tba0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x214>\n+\tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #16]\n-\tadd.w\tr9, sp, #36\t@ 0x24\n+\tldr\tr3, [sp, #8]\n+\tadd.w\tsl, sp, #36\t@ 0x24\n \tmovs\tr6, #1\n \tcmp\tr3, #0\n \tbic.w\tr2, r3, r3, asr #31\n-\tstr.w\tr6, [r9]\n+\tstr.w\tr6, [sl]\n \tstr\tr2, [sp, #8]\n-\tble.n\tcac <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2e8>\n+\tble.n\tc80 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2f4>\n \tldrd\tr2, r3, [sp, #20]\n-\tvldr\td8, [pc, #248]\t@ cf0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x32c>\n \tadd\tr3, r2\n \tlsls\tr2, r2, #2\n-\tstr\tr2, [sp, #20]\n+\tstr\tr2, [sp, #24]\n \tldr\tr2, [sp, #12]\n \tadd\tr3, r2\n \tadd.w\tr5, r5, r3, lsl #2\n \tlsls\tr3, r2, #2\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [pc, #308]\t@ (d40 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x37c>)\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [pc, #564]\t@ (e04 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x478>)\n \tadd\tr3, pc\n \tadds\tr3, #20\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [pc, #304]\t@ (d44 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x380>)\n-\tmovs\tr7, #128\t@ 0x80\n-\tvstr\td8, [sp, #48]\t@ 0x30\n-\tmov\tr0, r4\n+\tstr\tr3, [sp, #16]\n+\tldr\tr3, [pc, #560]\t@ (e08 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x47c>)\n \tadd\tr3, pc\n+\tstr\tr3, [sp, #12]\n+\tldr\tr3, [sp, #12]\n+\tmov.w\tr9, #128\t@ 0x80\n \tstr\tr3, [r4, #8]\n-\tldr\tr3, [pc, #292]\t@ (d48 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x384>)\n-\tstr\tr7, [r4, #72]\t@ 0x48\n+\tmov\tr0, r4\n+\tldr\tr3, [pc, #548]\t@ (e0c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x480>)\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tstr.w\tr9, [r4, #72]\t@ 0x48\n \tadd\tr3, pc\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n \tstr\tr3, [r4, #52]\t@ 0x34\n \tmovs\tr3, #0\n \tstr\tr3, [r4, #48]\t@ 0x30\n \tmovs\tr3, #11\n \tstr\tr3, [r4, #56]\t@ 0x38\n \tmovw\tr3, #1607\t@ 0x647\n \tstr\tr3, [r4, #12]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n \tmovs\tr2, #4\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tldr\tr1, [pc, #256]\t@ (d4c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x388>)\n+\tldr\tr1, [pc, #500]\t@ (e10 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x484>)\n \tmovs\tr2, #1\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmovs\tr2, #4\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #20]\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tadds\tr1, r3, r5\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, r7\n-\tmov\tr3, sl\n+\tmov\tr2, r9\n+\tmov\tr3, fp\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #208]\t@ (d50 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x38c>)\n-\tldr.w\tr7, [fp]\n+\tldr\tr3, [pc, #452]\t@ (e14 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x488>)\n+\tldr.w\tr9, [r7]\n \tadd\tr3, pc\n \tldr.w\tr0, [r8]\n-\tldr\tr1, [sp, #12]\n-\tmov\tr2, r7\n+\tldr\tr1, [sp, #16]\n+\tmov\tr2, r9\n \tstr\tr0, [sp, #4]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp\tr7, #0\n-\tble.n\tc9c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2d8>\n+\tcmp.w\tr9, #0\n+\tble.n\tc70 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x2e4>\n \tldr\tr0, [sp, #4]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #24]\n \tadds\tr6, #1\n-\tstr.w\tr6, [r9]\n+\tstr.w\tr6, [sl]\n \tadd\tr5, r3\n \tldr\tr3, [sp, #8]\n \tcmp\tr3, r6\n-\tbge.n\tc12 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x24e>\n-\tldr\tr2, [pc, #164]\t@ (d54 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x390>)\n-\tldr\tr3, [pc, #76]\t@ (cfc <__gridxc_alloc_MOD_alloc_err.constprop.1+0x338>)\n+\tbge.n\tbda <__gridxc_alloc_MOD_alloc_err.constprop.1+0x24e>\n+\tldr\tr2, [pc, #404]\t@ (e18 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x48c>)\n+\tldr\tr3, [pc, #316]\t@ (dc0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x434>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #524]\t@ 0x20c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\te80 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4bc>\n-\tldr\tr3, [pc, #148]\t@ (d58 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x394>)\n+\tbne.w\tdb6 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x42a>\n+\tldr\tr3, [pc, #388]\t@ (e1c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x490>)\n \tmovs\tr2, #30\n-\tldr\tr1, [pc, #148]\t@ (d5c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x398>)\n+\tldr\tr1, [pc, #388]\t@ (e20 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x494>)\n \tadd\tr3, pc\n-\tldr\tr0, [pc, #148]\t@ (d60 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x39c>)\n+\tldr\tr0, [pc, #388]\t@ (e24 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x498>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tadds\tr1, #16\n \tldr\tr3, [r3, #0]\n \tadd.w\tsp, sp, #532\t@ 0x214\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tnop\n-\tnop.w\n-\t.word\t0x00004080\n-\t.word\t0xffffffff\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x0000030c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002d6\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ce\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000029e\n- R_ARM_REL32\t.LC0\n-\t.word\t0x0000027e\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000254\n- R_ARM_REL32\t.data.rel.local\n-\t.word\t0x0000024e\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000021a\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000204\n- R_ARM_REL32\t.LC4\n-\t.word\t0x000001f2\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000001da\n- R_ARM_REL32\t.data.rel.local\n-\t.word\t0x000001d8\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000001b2\n- R_ARM_REL32\t.LC0\n-\t.word\t0x000001aa\n- R_ARM_REL32\t.LC13\n-\t.word\t0x00000192\n- R_ARM_REL32\t.LC14\n-\t.word\t0x0000017a\n- R_ARM_REL32\t.data.rel.local\n-\t.word\t0x00000174\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000130\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000124\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000120\n- R_ARM_REL32\t.LC16\n-\t.word\t0x000000fa\n- R_ARM_REL32\t.LC17\n-\t.word\t0x000000ca\n- R_ARM_REL32\t.data.rel.local\n-\t.word\t0x000000a0\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000008c\n- R_ARM_REL32\t.data.rel.local\n-\t.word\t0x0000008c\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000008e\n- R_ARM_REL32\t.LC12\n \tldr\tr0, [sp, #28]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr6, #0\n-\tit\tne\n-\tcmpne\tr7, #0\n-\tit\tne\n-\tmovne\tr3, #1\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tbeq.w\tae4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x120>\n-\tvldr\td16, [pc, #264]\t@ e88 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4c4>\n+\tb.n\ta90 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x104>\n+\tmov\tr0, r9\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tb.n\tb26 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x19a>\n+\tcmp.w\tr9, #0\n+\tbeq.w\tb26 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x19a>\n+\tldr\tr3, [pc, #348]\t@ (e28 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x49c>)\n \tmov\tr0, r4\n-\tldr\tr3, [pc, #268]\t@ (e90 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4cc>)\n-\tmov.w\tr9, #128\t@ 0x80\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n+\tstr\tr6, [r4, #48]\t@ 0x30\n+\tmovs\tr6, #128\t@ 0x80\n \tadd\tr3, pc\n-\tvstr\td16, [sp, #48]\t@ 0x30\n+\tstr\tr6, [r4, #72]\t@ 0x48\n \tstr\tr3, [r4, #8]\n-\tmov.w\tr3, #1592\t@ 0x638\n-\tstr.w\tr9, [r4, #72]\t@ 0x48\n+\tmov.w\tr3, #1600\t@ 0x640\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n+\tmov.w\tr2, #16512\t@ 0x4080\n \tstr\tr3, [r4, #12]\n-\tmovs\tr3, #0\n-\tstr\tr3, [r4, #48]\t@ 0x30\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #236]\t@ (e94 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4d0>)\n-\tmovs\tr2, #17\n+\tldr\tr1, [pc, #312]\t@ (e2c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4a0>)\n+\tmovs\tr2, #24\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tmov\tr1, r6\n-\tldr\tr2, [sp, #4]\n-\tmov\tr0, r4\n-\tbl\t0 <_gfortran_transfer_character_write>\n- R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tldr\tr1, [pc, #216]\t@ (e98 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4d4>)\n+\tldr\tr1, [pc, #304]\t@ (e30 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4a4>)\n \tmovs\tr2, #14\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tmov\tr1, r7\n-\tldr\tr2, [sp, #8]\n+\tmov\tr1, r9\n+\tldr\tr2, [sp, #4]\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, sl\n-\tmov\tr2, r9\n+\tmov\tr3, fp\n+\tmov\tr2, r6\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #180]\t@ (e9c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4d8>)\n-\tldr\tr1, [pc, #184]\t@ (ea0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4dc>)\n+\tldr\tr3, [pc, #268]\t@ (e34 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4a8>)\n+\tldr\tr1, [pc, #268]\t@ (e38 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4ac>)\n \tadd\tr3, pc\n-\tldr.w\tr6, [fp]\n-\tldr.w\tr7, [r8]\n+\tldr.w\tr9, [r8]\n \tadd\tr1, pc\n-\tadds\tr1, #4\n-\tmov\tr2, r6\n+\tldr\tr6, [r7, #0]\n+\tadds\tr1, #12\n \tldr\tr3, [r3, #0]\n-\tmov\tr0, r7\n-\tblx\tr3\n-\tcmp\tr6, #0\n-\tble.w\tb62 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x19e>\n-\tmov\tr0, r7\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tb.n\tb62 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x19e>\n-\tcmp\tr7, #0\n-\tbeq.w\tb62 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x19e>\n-\tvldr\td16, [pc, #116]\t@ e88 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4c4>\n+\tb.n\tb1a <__gridxc_alloc_MOD_alloc_err.constprop.1+0x18e>\n+\tldr\tr3, [pc, #256]\t@ (e3c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4b0>)\n \tmov\tr0, r4\n-\tldr\tr3, [pc, #136]\t@ (ea4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4e0>)\n-\tstr\tr6, [r4, #48]\t@ 0x30\n-\tmovs\tr6, #128\t@ 0x80\n+\tstr.w\tfp, [r4, #68]\t@ 0x44\n+\tmov.w\tr2, #16512\t@ 0x4080\n \tadd\tr3, pc\n-\tstr.w\tsl, [r4, #68]\t@ 0x44\n-\tvstr\td16, [sp, #48]\t@ 0x30\n \tstr\tr3, [r4, #8]\n-\tmov.w\tr3, #1600\t@ 0x640\n-\tstr\tr6, [r4, #72]\t@ 0x48\n+\tmov.w\tr3, #1592\t@ 0x638\n \tstr\tr3, [r4, #12]\n+\tmovs\tr3, #128\t@ 0x80\n+\tstr\tr3, [r4, #72]\t@ 0x48\n+\tmovs\tr3, #0\n+\tstr\tr3, [r4, #48]\t@ 0x30\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #112]\t@ (ea8 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4e4>)\n-\tmovs\tr2, #24\n+\tldr\tr1, [pc, #216]\t@ (e40 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4b4>)\n+\tmovs\tr2, #17\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tldr\tr1, [pc, #104]\t@ (eac <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4e8>)\n+\tmov\tr1, r6\n+\tmov\tr2, sl\n+\tmov\tr0, r4\n+\tbl\t0 <_gfortran_transfer_character_write>\n+ R_ARM_THM_CALL\t_gfortran_transfer_character_write\n+\tldr\tr1, [pc, #200]\t@ (e44 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4b8>)\n \tmovs\tr2, #14\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tmov\tr1, r7\n-\tldr\tr2, [sp, #8]\n+\tmov\tr1, r9\n+\tldr\tr2, [sp, #4]\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, sl\n-\tmov\tr2, r6\n+\tmov\tr3, fp\n \tmov\tr1, r8\n-\tmov\tr0, fp\n+\tmovs\tr2, #128\t@ 0x80\n+\tmov\tr0, r7\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #68]\t@ (eb0 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4ec>)\n-\tldr\tr1, [pc, #68]\t@ (eb4 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4f0>)\n+\tldr\tr3, [pc, #164]\t@ (e48 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4bc>)\n+\tldr\tr1, [pc, #164]\t@ (e4c <__gridxc_alloc_MOD_alloc_err.constprop.1+0x4c0>)\n \tadd\tr3, pc\n-\tldr.w\tr7, [r8]\n+\tldr.w\tr9, [r8]\n \tadd\tr1, pc\n-\tldr.w\tr6, [fp]\n-\tadds\tr1, #12\n+\tldr\tr6, [r7, #0]\n+\tadds\tr1, #4\n \tldr\tr3, [r3, #0]\n-\tb.n\tb56 <__gridxc_alloc_MOD_alloc_err.constprop.1+0x192>\n+\tb.n\tb1a <__gridxc_alloc_MOD_alloc_err.constprop.1+0x18e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00004080\n-\t.word\t0xffffffff\n-\t.word\t0x00000100\n+\tnop\n+\t.word\t0x0000040a\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000003d6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003d0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x000003b0\n R_ARM_REL32\t.LC0\n-\t.word\t0x000000e4\n+\t.word\t0x00000384\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x0000035a\n+ R_ARM_REL32\t.data.rel.local\n+\t.word\t0x00000356\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000031e\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000302\n R_ARM_REL32\t.LC4\n-\t.word\t0x000000d2\n- R_ARM_REL32\t.LC5\n-\t.word\t0x000000b0\n+\t.word\t0x000002f0\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x000002d8\n+ R_ARM_REL32\t.data.rel.local\n+\t.word\t0x000002d6\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000002b8\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000002ae\n+ R_ARM_REL32\t.LC13\n+\t.word\t0x0000028e\n+ R_ARM_REL32\t.LC14\n+\t.word\t0x00000276\n R_ARM_REL32\t.data.rel.local\n-\t.word\t0x000000aa\n+\t.word\t0x00000272\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000082\n+\t.word\t0x00000232\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000022e\n R_ARM_REL32\t.LC0\n-\t.word\t0x00000068\n+\t.word\t0x0000021a\n+ R_ARM_REL32\t.LC16\n+\t.word\t0x000001ec\n+ R_ARM_REL32\t.LC17\n+\t.word\t0x000001bc\n+ R_ARM_REL32\t.data.rel.local\n+\t.word\t0x00000190\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000017c\n+ R_ARM_REL32\t.data.rel.local\n+\t.word\t0x0000017c\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000017e\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x00000152\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000130\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000060\n+\t.word\t0x00000128\n R_ARM_REL32\t.LC5\n-\t.word\t0x0000003e\n+\t.word\t0x00000106\n R_ARM_REL32\t.data.rel.local\n-\t.word\t0x0000003c\n+\t.word\t0x00000104\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000000f2\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000000d2\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x000000c0\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x0000009e\n+ R_ARM_REL32\t.data.rel.local\n+\t.word\t0x0000009c\n R_ARM_REL32\t.rodata\n \n-00000eb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>:\n+00000e50 <__gridxc_alloc_MOD_alloc_count.constprop.0>:\n __gridxc_alloc_MOD_alloc_count.constprop.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3608]\t@ 0xe18\n-\tldr\tr5, [pc, #892]\t@ (1248 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x390>)\n+\tldr\tr5, [pc, #908]\t@ (11f0 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a0>)\n \tsub\tsp, #452\t@ 0x1c4\n-\tldr\tr4, [pc, #892]\t@ (124c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x394>)\n+\tldr\tr4, [pc, #908]\t@ (11f4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a4>)\n \tmov\tr7, r0\n \tadd\tr5, pc\n \tmov\tr6, r1\n \tldr.w\tr8, [sp, #492]\t@ 0x1ec\n \tcmp\tr2, #0\n \tit\tne\n \tcmpne\tr3, #0\n \tldr\tr0, [sp, #496]\t@ 0x1f0\n \tldr\tr4, [r5, r4]\n \tmov\tr5, r3\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #444]\t@ 0x1bc\n \tmov.w\tr4, #0\n \tmov\tr4, r2\n-\tbne.w\t1118 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x260>\n+\tbne.w\t10b4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x264>\n \tcmp\tr2, #0\n-\tbeq.w\t1078 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x1c0>\n-\tldr\tr5, [pc, #852]\t@ (1250 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x398>)\n+\tbeq.w\t1010 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x1c0>\n+\tldr\tr5, [pc, #868]\t@ (11f8 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a8>)\n \tmovs\tr2, #15\n-\tldr\tr3, [pc, #852]\t@ (1254 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x39c>)\n+\tldr\tr3, [pc, #868]\t@ (11fc <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3ac>)\n \tmovs\tr0, #32\n \tadd\tr5, pc\n \tadds\tr5, #12\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t1138 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x280>\n+\tbeq.w\t10d4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x284>\n \tmov\tr1, r5\n \tmovs\tr0, #32\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tfp, r0, r0, asr #31\n \tadd.w\tsl, fp, #1\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [pc, #812]\t@ (1258 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a0>)\n+\tldr\tr1, [pc, #828]\t@ (1200 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b0>)\n \tmov\tr9, r0\n \tmov\tr3, r5\n \tmov\tr2, fp\n \tadd\tr1, pc\n-\tadd.w\tfp, r8, sl\n+\tadd.w\tr5, r8, sl\n \tmov\tr0, sl\n \tstr\tr1, [sp, #4]\n \tmovs\tr1, #1\n \tstr\tr1, [sp, #0]\n \tmov\tr1, r9\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, fp\n-\tcmp\tr0, #1\n-\tadd\tr5, sp, #372\t@ 0x174\n+\tcmp\tr5, #1\n+\tmov\tr0, r5\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tmov\tr2, sl\n \tmov\tr1, r0\n \tmov\tr3, r9\n \tstrd\tr8, r4, [sp]\n-\tmov\tr8, r0\n-\tmov\tr0, fp\n+\tmov\tfp, r0\n+\tmov\tr0, r5\n+\tadd.w\tr8, sp, #372\t@ 0x174\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp.w\tfp, #31\n-\tble.w\t11fc <__gridxc_alloc_MOD_alloc_count.constprop.0+0x344>\n-\tmov\tip, r8\n-\tmov\tr4, r5\n-\tldmia.w\tip!, {r0, r1, r2, r3}\n+\tcmp\tr5, #31\n+\tble.w\t119c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x34c>\n+\tmov\tr5, fp\n+\tmov\tr4, r8\n+\tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n-\tldmia.w\tip, {r0, r1, r2, r3}\n+\tldmia.w\tr5, {r0, r1, r2, r3}\n \tstmia.w\tr4, {r0, r1, r2, r3}\n-\tmov\tr0, r8\n+\tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldrb\tr3, [r6, #0]\n \tldr\tr2, [r7, #0]\n \tsubs\tr3, #68\t@ 0x44\n \tcmp\tr3, #15\n-\tbhi.n\tfa8 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xf0>\n+\tbhi.n\tf3e <__gridxc_alloc_MOD_alloc_count.constprop.0+0xee>\n \ttbb\t[pc, r3]\n-\t.word\t0x0808abab\n-\t.word\t0x08084c08\n-\t.word\t0x0808084c\n-\t.word\t0x4d4c0808\n-\tldr\tr3, [pc, #688]\t@ (125c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a4>)\n+\t.short\t0xaeae\n+\t.word\t0x4d080808\n+\t.word\t0x084d0808\n+\t.word\t0x08080808\n+\t.short\t0x4e4d\n+\tldr\tr3, [pc, #708]\t@ (1204 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b4>)\n \tadd\tr4, sp, #24\n-\tvldr\td16, [pc, #656]\t@ 1240 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x388>\n+\tmovw\tr2, #1695\t@ 0x69f\n \tmov\tr0, r4\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [pc, #680]\t@ (1260 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a8>)\n-\tadd.w\tr8, sp, #404\t@ 0x194\n-\tvstr\td16, [sp, #24]\n-\tmovw\tr2, #1695\t@ 0x69f\n+\tstrd\tr3, r2, [sp, #32]\n+\tldr\tr3, [pc, #696]\t@ (1208 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b8>)\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tadd.w\tr9, sp, #404\t@ 0x194\n+\tmov.w\tsl, #40\t@ 0x28\n \tadd\tr3, pc\n-\tmov.w\tr9, #40\t@ 0x28\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tadd\tr7, sp, #16\n-\tstr.w\tr8, [sp, #92]\t@ 0x5c\n+\tstr.w\tr9, [sp, #92]\t@ 0x5c\n \tstr\tr3, [sp, #76]\t@ 0x4c\n \tmovs\tr3, #4\n-\tstr.w\tr9, [sp, #96]\t@ 0x60\n+\tstr.w\tsl, [sp, #96]\t@ 0x60\n+\tadd\tr7, sp, #16\n \tstr\tr3, [sp, #80]\t@ 0x50\n \tmovs\tr3, #0\n \tstr\tr3, [sp, #72]\t@ 0x48\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #24]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #636]\t@ (1264 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3ac>)\n+\tldr\tr1, [pc, #652]\t@ (120c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3bc>)\n \tmov\tr0, r4\n \tmovs\tr2, #35\t@ 0x23\n+\tadd\tr5, sp, #20\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr1, r6\n \tmovs\tr2, #1\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tadd\tr6, sp, #20\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, r8\n-\tmov\tr2, r9\n+\tmov\tr3, r9\n+\tmov\tr2, sl\n \tmov\tr1, r7\n-\tmov\tr0, r6\n+\tmov\tr0, r5\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #600]\t@ (1268 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b0>)\n-\tldr\tr1, [pc, #600]\t@ (126c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b4>)\n+\tldr\tr3, [pc, #612]\t@ (1210 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c0>)\n+\tldr\tr1, [pc, #616]\t@ (1214 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c4>)\n \tadd\tr3, pc\n-\tldr\tr4, [r6, #0]\n-\tldr.w\tr8, [r7]\n+\tldr\tr4, [r5, #0]\n+\tldr\tr6, [r7, #0]\n \tadd\tr1, pc\n \tadds\tr1, #16\n \tmov\tr2, r4\n \tldr\tr3, [r3, #0]\n-\tmov\tr0, r8\n+\tmov\tr0, r6\n \tblx\tr3\n \tcmp\tr4, #0\n-\tbgt.w\t1180 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2c8>\n+\tbgt.w\t111a <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2ca>\n \tmovs\tr2, #0\n-\tb.n\t1036 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n+\tb.n\tfce <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n \tlsls\tr2, r2, #2\n \tadd\tr7, sp, #16\n-\tadd\tr6, sp, #20\n-\tmov\tr3, r5\n-\tmov\tr1, r6\n+\tadd\tr5, sp, #20\n+\tmov\tr1, r5\n+\tmov\tr3, r8\n \tmov\tr0, r7\n \tstr\tr2, [sp, #12]\n \tmovs\tr2, #32\n \tadd\tr4, sp, #12\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #552]\t@ (1270 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3b8>)\n-\tldr\tr5, [r7, #0]\n+\tldr\tr3, [pc, #568]\t@ (1218 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c8>)\n+\tldr\tr6, [r5, #0]\n \tmov\tr0, r4\n \tadd\tr3, pc\n-\tldr\tr6, [r6, #0]\n-\tmov\tr2, r5\n+\tldr\tr5, [r7, #0]\n \tmov\tr1, r6\n+\tmov\tr2, r5\n \tldr\tr3, [r3, #4]\n \tblx\tr3\n \tcmp\tr5, #0\n-\tbgt.n\t10f6 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x23e>\n-\tldr\tr2, [pc, #532]\t@ (1274 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3bc>)\n-\tldr\tr3, [pc, #492]\t@ (124c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x394>)\n+\tbgt.n\t1092 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x242>\n+\tldr\tr2, [pc, #548]\t@ (121c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3cc>)\n+\tldr\tr3, [pc, #508]\t@ (11f4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #444]\t@ 0x1bc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1238 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x380>\n+\tbne.w\t11ec <__gridxc_alloc_MOD_alloc_count.constprop.0+0x39c>\n \tadd\tsp, #452\t@ 0x1c4\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tcmp\tr3, #0\n-\tbeq.w\t118a <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2d2>\n+\tbeq.w\t1124 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2d4>\n \tmov\tr1, r3\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tr4, r0, r0, asr #31\n \tadd.w\tsl, r4, #1\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr2, [pc, #484]\t@ (1278 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c0>)\n-\tmov\tr3, r5\n+\tldr\tr2, [pc, #500]\t@ (1220 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d0>)\n+\tmov\tr8, r0\n \tmov\tr1, r0\n+\tmov\tr3, r5\n \tadd\tr2, pc\n-\tmov\tr9, r0\n-\tstr\tr2, [sp, #4]\n \tmov\tr0, sl\n+\tstr\tr2, [sp, #4]\n \tmovs\tr2, #1\n \tstr\tr2, [sp, #0]\n \tmov\tr2, r4\n \tadds\tr4, #13\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #456]\t@ (127c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c4>)\n-\tmov\tr8, r0\n+\tldr\tr3, [pc, #472]\t@ (1224 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d4>)\n+\tmov\tr1, r0\n \tmov\tr2, sl\n \tadd\tr3, pc\n-\tmov\tr1, r8\n-\tmov\tr0, r4\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n+\tmov\tr0, r4\n \tmovs\tr3, #12\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r9\n+\tmov\tr3, r8\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, r9\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tadd\tr5, sp, #372\t@ 0x174\n+\tadd.w\tr8, sp, #372\t@ 0x174\n \tcmp\tr4, #31\n-\tbgt.w\tf72 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xba>\n-\tmov\tr2, r4\n-\tmov\tr1, r8\n-\tmov\tr0, r5\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemcpy\n-\tmovs\tr1, #32\n-\tsubs\tr2, r1, r4\n-\tadds\tr0, r5, r4\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemset\n-\tb.n\tf84 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xcc>\n+\tble.w\t11d4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x384>\n+\tmov\tr5, r9\n+\tmov\tr4, r8\n+\tldmia\tr5!, {r0, r1, r2, r3}\n+\tstmia\tr4!, {r0, r1, r2, r3}\n+\tldmia.w\tr5, {r0, r1, r2, r3}\n+\tstmia.w\tr4, {r0, r1, r2, r3}\n+\tmov\tr0, r9\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tb.n\tf20 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xd0>\n \tlsls\tr2, r2, #3\n \tadd\tr7, sp, #16\n-\tadd\tr6, sp, #20\n-\tb.n\t1036 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n-\tldr\tr2, [pc, #392]\t@ (1280 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3c8>)\n-\tldr\tr3, [pc, #336]\t@ (124c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x394>)\n+\tadd\tr5, sp, #20\n+\tb.n\tfce <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n+\tldr\tr2, [pc, #404]\t@ (1228 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d8>)\n+\tldr\tr3, [pc, #348]\t@ (11f4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3a4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #444]\t@ 0x1bc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1238 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x380>\n+\tbne.w\t11ec <__gridxc_alloc_MOD_alloc_count.constprop.0+0x39c>\n \tmov\tr0, r6\n \tadd\tsp, #452\t@ 0x1c4\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n \tmov\tr1, r3\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tfp, r0, r0, asr #31\n \tadd.w\tsl, fp, #1\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [pc, #340]\t@ (1284 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3cc>)\n+\tldr\tr1, [pc, #352]\t@ (122c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3dc>)\n \tmov\tr9, r0\n \tmov\tr3, r5\n \tmov\tr2, fp\n \tadd\tr1, pc\n-\tb.n\tf32 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x7a>\n-\tadd.w\tsl, r8, #16\n-\tadd\tr5, sp, #372\t@ 0x174\n-\tmov\tr0, sl\n-\tcmp\tr0, #1\n+\tb.n\teca <__gridxc_alloc_MOD_alloc_count.constprop.0+0x7a>\n+\tadd.w\tr5, r8, #16\n+\tcmp\tr5, #1\n+\tmov\tr0, r5\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #316]\t@ (1288 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d0>)\n+\tldr\tr3, [pc, #328]\t@ (1230 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3e0>)\n \tmov\tr1, r0\n+\tstr.w\tr8, [sp]\n \tmov\tr9, r0\n \tadd\tr3, pc\n \tmovs\tr2, #16\n-\tmov\tr0, sl\n+\tmov\tr0, r5\n \tstr\tr4, [sp, #4]\n-\tstr.w\tr8, [sp]\n+\tadd.w\tr8, sp, #372\t@ 0x174\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tcmp.w\tsl, #31\n-\tble.n\t11e2 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x32a>\n-\tmov\tip, r9\n-\tmov\tr4, r5\n-\tldmia.w\tip!, {r0, r1, r2, r3}\n-\tstmia\tr4!, {r0, r1, r2, r3}\n-\tldmia.w\tip, {r0, r1, r2, r3}\n-\tstmia.w\tr4, {r0, r1, r2, r3}\n-\tmov\tr0, r9\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tb.n\tf8a <__gridxc_alloc_MOD_alloc_count.constprop.0+0xd2>\n+\tcmp\tr5, #31\n+\tbgt.n\t1072 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x222>\n+\tmov\tr2, r5\n+\tmov\tr1, r9\n \tmov\tr0, r8\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemcpy\n+\tmovs\tr1, #32\n+\tsubs\tr2, r1, r5\n+\tadd.w\tr0, r8, r5\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tb.n\t1082 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x232>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr2, #0\n-\tb.n\t1036 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n-\tldr\tr4, [pc, #256]\t@ (128c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d4>)\n+\tb.n\tfce <__gridxc_alloc_MOD_alloc_count.constprop.0+0x17e>\n+\tldr\tr4, [pc, #268]\t@ (1234 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3e4>)\n \tmovs\tr2, #15\n-\tldr\tr3, [pc, #256]\t@ (1290 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3d8>)\n+\tldr\tr3, [pc, #268]\t@ (1238 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3e8>)\n \tmovs\tr0, #32\n \tadd\tr4, pc\n \tadds\tr4, #12\n \tadd\tr3, pc\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1216 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x35e>\n+\tcmp\tr0, #0\n+\tbeq.n\t11b4 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x364>\n \tmov\tr1, r4\n \tmovs\tr0, #32\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tr5, r0, r0, asr #31\n \tadd.w\tsl, r5, #1\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr2, [pc, #220]\t@ (1294 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3dc>)\n-\tmov\tr3, r4\n+\tldr\tr2, [pc, #232]\t@ (123c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3ec>)\n+\tmov\tr8, r0\n \tmov\tr1, r0\n+\tmov\tr3, r4\n \tadd\tr2, pc\n-\tmov\tr9, r0\n-\tstr\tr2, [sp, #4]\n \tmov\tr0, sl\n+\tstr\tr2, [sp, #4]\n \tmovs\tr2, #1\n-\tadd.w\tr4, r5, #13\n \tstr\tr2, [sp, #0]\n \tmov\tr2, r5\n+\tadds\tr5, #13\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, r4\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #188]\t@ (1298 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3e0>)\n-\tmov\tr8, r0\n+\tldr\tr3, [pc, #204]\t@ (1240 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3f0>)\n+\tmov\tr1, r0\n \tmov\tr2, sl\n \tadd\tr3, pc\n-\tb.n\t10ba <__gridxc_alloc_MOD_alloc_count.constprop.0+0x202>\n-\tmov\tr2, sl\n-\tmov\tr1, r9\n+\tmov\tr9, r0\n+\tstr\tr3, [sp, #4]\n \tmov\tr0, r5\n+\tmovs\tr3, #12\n+\tstr\tr3, [sp, #0]\n+\tmov\tr3, r8\n+\tbl\t0 <_gfortran_concat_string>\n+ R_ARM_THM_CALL\t_gfortran_concat_string\n+\tmov\tr0, r8\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tadd.w\tr8, sp, #372\t@ 0x174\n+\tcmp\tr5, #31\n+\tbgt.w\t1072 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x222>\n+\tb.n\t1102 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2b2>\n+\tmov\tr2, r5\n+\tmov\tr1, fp\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr1, #32\n-\tsub.w\tr2, r1, sl\n-\tadd.w\tr0, r5, sl\n+\tsubs\tr2, r1, r5\n+\tadd.w\tr0, r8, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tb.n\t1178 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x2c0>\n-\tmov\tr2, fp\n-\tmov\tr1, r8\n-\tmov\tr0, r5\n+\tb.n\tf1a <__gridxc_alloc_MOD_alloc_count.constprop.0+0xca>\n+\tldr\tr5, [pc, #140]\t@ (1244 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3f4>)\n+\tadd.w\tr8, sp, #372\t@ 0x174\n+\tmov\tr4, r8\n+\tmov.w\tip, #538976288\t@ 0x20202020\n+\tadd\tr5, pc\n+\tldmia\tr5!, {r0, r1, r2, r3}\n+\tstmia\tr4!, {r0, r1, r2, r3}\n+\tldmia.w\tr5, {r0, r1, r2}\n+\tstmia.w\tr4, {r0, r1, r2}\n+\tstr.w\tip, [sp, #400]\t@ 0x190\n+\tb.n\tf20 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xd0>\n+\tmov\tr2, r4\n+\tmov\tr1, r9\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr1, #32\n-\tsub.w\tr2, r1, fp\n-\tadd.w\tr0, r5, fp\n+\tsubs\tr2, r1, r4\n+\tadd.w\tr0, r8, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tb.n\tf84 <__gridxc_alloc_MOD_alloc_count.constprop.0+0xcc>\n-\tldr.w\tip, [pc, #132]\t@ 129c <__gridxc_alloc_MOD_alloc_count.constprop.0+0x3e4>\n-\tadd\tr5, sp, #372\t@ 0x174\n-\tmov\tr4, r5\n-\tmov.w\tlr, #538976288\t@ 0x20202020\n-\tadd\tip, pc\n-\tldmia.w\tip!, {r0, r1, r2, r3}\n-\tstmia\tr4!, {r0, r1, r2, r3}\n-\tldmia.w\tip, {r0, r1, r2}\n-\tstmia.w\tr4, {r0, r1, r2}\n-\tstr.w\tlr, [sp, #400]\t@ 0x190\n-\tb.n\tf8a <__gridxc_alloc_MOD_alloc_count.constprop.0+0xd2>\n+\tb.n\t1082 <__gridxc_alloc_MOD_alloc_count.constprop.0+0x232>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x00000374\n+\t.word\t0x00000384\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000034c\n+\t.word\t0x0000035c\n R_ARM_REL32\t.data\n-\t.word\t0x0000034c\n+\t.word\t0x0000035c\n R_ARM_REL32\t.LC19\n-\t.word\t0x00000324\n+\t.word\t0x00000334\n R_ARM_REL32\t.LC18\n-\t.word\t0x000002a6\n+\t.word\t0x000002b8\n R_ARM_REL32\t.LC0\n-\t.word\t0x00000298\n+\t.word\t0x000002a8\n R_ARM_REL32\t.LC23\n-\t.word\t0x00000276\n+\t.word\t0x00000282\n R_ARM_REL32\t.LC24\n-\t.word\t0x00000252\n+\t.word\t0x00000260\n R_ARM_REL32\t.data.rel.local\n-\t.word\t0x0000024e\n+\t.word\t0x0000025e\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000220\n+\t.word\t0x00000230\n R_ARM_REL32\t.data.rel.local\n-\t.word\t0x00000210\n+\t.word\t0x00000220\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001dc\n+\t.word\t0x000001ea\n R_ARM_REL32\t.LC18\n-\t.word\t0x000001c0\n+\t.word\t0x000001d0\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000182\n+\t.word\t0x0000018e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000014c\n+\t.word\t0x00000158\n R_ARM_REL32\t.LC18\n-\t.word\t0x00000134\n+\t.word\t0x0000013e\n R_ARM_REL32\t.LC20\n-\t.word\t0x000000f6\n+\t.word\t0x00000104\n R_ARM_REL32\t.data\n-\t.word\t0x000000f6\n+\t.word\t0x00000104\n R_ARM_REL32\t.LC19\n-\t.word\t0x000000d4\n+\t.word\t0x000000de\n R_ARM_REL32\t.LC18\n-\t.word\t0x000000b6\n+\t.word\t0x000000c4\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000076\n+\t.word\t0x00000080\n R_ARM_REL32\t.LC22\n \n-000012a0 <__gridxc_alloc_MOD_dealloc_s1>:\n+00001248 <__gridxc_alloc_MOD_dealloc_s1>:\n __gridxc_alloc_MOD_dealloc_s1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr6, r1\n-\tldr\tr1, [pc, #192]\t@ (1374 <__gridxc_alloc_MOD_dealloc_s1+0xd4>)\n+\tldr\tr1, [pc, #192]\t@ (131c <__gridxc_alloc_MOD_dealloc_s1+0xd4>)\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #192]\t@ (1378 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n+\tldr\tr2, [pc, #192]\t@ (1320 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n \tadd\tr1, pc\n \tsub\tsp, #28\n \tldr\tr2, [r1, r2]\n \tldr\tr7, [sp, #56]\t@ 0x38\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #20]\n \tmov.w\tr2, #0\n \tldr\tr2, [r0, #0]\n \tldr.w\tr8, [sp, #60]\t@ 0x3c\n \tcmp\tr2, #0\n-\tbeq.n\t1356 <__gridxc_alloc_MOD_dealloc_s1+0xb6>\n+\tbeq.n\t12fc <__gridxc_alloc_MOD_dealloc_s1+0xb4>\n \tcmp\tr6, #0\n-\tmov.w\tr2, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr7, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r2\n+\tmoveq.w\tr8, #0\n \tstr\tr7, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tldrd\tr2, r1, [r0, #28]\n \tadd\tr0, sp, #16\n \tsub.w\tip, r1, r2\n-\tldr\tr1, [pc, #132]\t@ (137c <__gridxc_alloc_MOD_dealloc_s1+0xdc>)\n+\tldr\tr1, [pc, #132]\t@ (1324 <__gridxc_alloc_MOD_dealloc_s1+0xdc>)\n \tadd.w\tip, ip, #1\n \tmov\tr2, r6\n \tadd\tr1, pc\n \tbic.w\tip, ip, ip, asr #31\n \tmul.w\tip, r3, ip\n \tmov\tr3, r9\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1324 <__gridxc_alloc_MOD_dealloc_s1+0x84>\n+\tcbz\tr0, 12ca <__gridxc_alloc_MOD_dealloc_s1+0x82>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #88]\t@ (1380 <__gridxc_alloc_MOD_dealloc_s1+0xe0>)\n-\tldr\tr2, [pc, #92]\t@ (1384 <__gridxc_alloc_MOD_dealloc_s1+0xe4>)\n+\tldr\tr0, [pc, #92]\t@ (1328 <__gridxc_alloc_MOD_dealloc_s1+0xe0>)\n+\tldr\tr2, [pc, #92]\t@ (132c <__gridxc_alloc_MOD_dealloc_s1+0xe4>)\n \tadd\tr0, pc\n-\tldr\tr3, [pc, #76]\t@ (1378 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n+\tldr\tr3, [pc, #76]\t@ (1320 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n \tadd\tr2, pc\n \tstr\tr4, [r0, #16]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1370 <__gridxc_alloc_MOD_dealloc_s1+0xd0>\n+\tbne.n\t1316 <__gridxc_alloc_MOD_dealloc_s1+0xce>\n \tmov\tr2, r9\n \tmov\tr1, r6\n \tadds\tr0, #16\n \tmovs\tr3, #0\n \tstr.w\tr8, [sp, #60]\t@ 0x3c\n \tstr\tr7, [sp, #56]\t@ 0x38\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n-\tb.w\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #48]\t@ (1388 <__gridxc_alloc_MOD_dealloc_s1+0xe8>)\n-\tldr\tr3, [pc, #28]\t@ (1378 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n+\tb.w\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #48]\t@ (1330 <__gridxc_alloc_MOD_dealloc_s1+0xe8>)\n+\tldr\tr3, [pc, #32]\t@ (1320 <__gridxc_alloc_MOD_dealloc_s1+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1370 <__gridxc_alloc_MOD_dealloc_s1+0xd0>\n+\tbne.n\t1316 <__gridxc_alloc_MOD_dealloc_s1+0xce>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC25\n-\t.word\t0x00000054\n+\t.word\t0x00000056\n R_ARM_REL32\t.bss\n-\t.word\t0x00000054\n+\t.word\t0x00000056\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000002a\n+\t.word\t0x0000002c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000138c <__gridxc_alloc_MOD_dealloc_l3>:\n+00001334 <__gridxc_alloc_MOD_dealloc_l3>:\n __gridxc_alloc_MOD_dealloc_l3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #192]\t@ (1460 <__gridxc_alloc_MOD_dealloc_l3+0xd4>)\n+\tldr\tr2, [pc, #192]\t@ (1408 <__gridxc_alloc_MOD_dealloc_l3+0xd4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #192]\t@ (1464 <__gridxc_alloc_MOD_dealloc_l3+0xd8>)\n+\tldr\tr3, [pc, #192]\t@ (140c <__gridxc_alloc_MOD_dealloc_l3+0xd8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1442 <__gridxc_alloc_MOD_dealloc_l3+0xb6>\n+\tbeq.n\t13e8 <__gridxc_alloc_MOD_dealloc_l3+0xb4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #140]\t@ (1468 <__gridxc_alloc_MOD_dealloc_l3+0xdc>)\n+\tldr\tr1, [pc, #144]\t@ (1410 <__gridxc_alloc_MOD_dealloc_l3+0xdc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -2183,86 +2145,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 142a <__gridxc_alloc_MOD_dealloc_l3+0x9e>\n+\tcbz\tr0, 13d0 <__gridxc_alloc_MOD_dealloc_l3+0x9c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (146c <__gridxc_alloc_MOD_dealloc_l3+0xe0>)\n+\tldr\tr0, [pc, #64]\t@ (1414 <__gridxc_alloc_MOD_dealloc_l3+0xe0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1470 <__gridxc_alloc_MOD_dealloc_l3+0xe4>)\n-\tldr\tr3, [pc, #28]\t@ (1464 <__gridxc_alloc_MOD_dealloc_l3+0xd8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1418 <__gridxc_alloc_MOD_dealloc_l3+0xe4>)\n+\tldr\tr3, [pc, #32]\t@ (140c <__gridxc_alloc_MOD_dealloc_l3+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t145c <__gridxc_alloc_MOD_dealloc_l3+0xd0>\n+\tbne.n\t1402 <__gridxc_alloc_MOD_dealloc_l3+0xce>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000086\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC26\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001474 <__gridxc_alloc_MOD_dealloc_l2>:\n+0000141c <__gridxc_alloc_MOD_dealloc_l2>:\n __gridxc_alloc_MOD_dealloc_l2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #180]\t@ (153c <__gridxc_alloc_MOD_dealloc_l2+0xc8>)\n+\tldr\tr2, [pc, #176]\t@ (14e0 <__gridxc_alloc_MOD_dealloc_l2+0xc4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #180]\t@ (1540 <__gridxc_alloc_MOD_dealloc_l2+0xcc>)\n+\tldr\tr3, [pc, #176]\t@ (14e4 <__gridxc_alloc_MOD_dealloc_l2+0xc8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t151c <__gridxc_alloc_MOD_dealloc_l2+0xa8>\n+\tbeq.n\t14c2 <__gridxc_alloc_MOD_dealloc_l2+0xa6>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n-\tit\teq\n-\tmoveq\tr8, r3\n \tstr\tr6, [sp, #4]\n+\tit\teq\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #128]\t@ (1544 <__gridxc_alloc_MOD_dealloc_l2+0xd0>)\n+\tldr\tr1, [pc, #128]\t@ (14e8 <__gridxc_alloc_MOD_dealloc_l2+0xcc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tadd\tr0, sp, #16\n \tsubs\tr3, r3, r2\n@@ -2272,170 +2234,168 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tip, r3, ip\n \tmov\tr3, r9\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1504 <__gridxc_alloc_MOD_dealloc_l2+0x90>\n+\tcbz\tr0, 14aa <__gridxc_alloc_MOD_dealloc_l2+0x8e>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1548 <__gridxc_alloc_MOD_dealloc_l2+0xd4>)\n+\tldr\tr0, [pc, #64]\t@ (14ec <__gridxc_alloc_MOD_dealloc_l2+0xd0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (154c <__gridxc_alloc_MOD_dealloc_l2+0xd8>)\n-\tldr\tr3, [pc, #32]\t@ (1540 <__gridxc_alloc_MOD_dealloc_l2+0xcc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (14f0 <__gridxc_alloc_MOD_dealloc_l2+0xd4>)\n+\tldr\tr3, [pc, #28]\t@ (14e4 <__gridxc_alloc_MOD_dealloc_l2+0xc8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1536 <__gridxc_alloc_MOD_dealloc_l2+0xc2>\n+\tbne.n\t14dc <__gridxc_alloc_MOD_dealloc_l2+0xc0>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000000ac\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC26\n-\t.word\t0x00000038\n+\t.word\t0x00000036\n R_ARM_REL32\t.bss\n-\t.word\t0x00000028\n+\t.word\t0x00000026\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001550 <__gridxc_alloc_MOD_dealloc_l1>:\n+000014f4 <__gridxc_alloc_MOD_dealloc_l1>:\n __gridxc_alloc_MOD_dealloc_l1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #160]\t@ (1604 <__gridxc_alloc_MOD_dealloc_l1+0xb4>)\n+\tldr\tr2, [pc, #160]\t@ (15a8 <__gridxc_alloc_MOD_dealloc_l1+0xb4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #160]\t@ (1608 <__gridxc_alloc_MOD_dealloc_l1+0xb8>)\n+\tldr\tr3, [pc, #160]\t@ (15ac <__gridxc_alloc_MOD_dealloc_l1+0xb8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 15e6 <__gridxc_alloc_MOD_dealloc_l1+0x96>\n+\tcbz\tr3, 1588 <__gridxc_alloc_MOD_dealloc_l1+0x94>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #112]\t@ (160c <__gridxc_alloc_MOD_dealloc_l1+0xbc>)\n+\tldr\tr1, [pc, #112]\t@ (15b0 <__gridxc_alloc_MOD_dealloc_l1+0xbc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 15ce <__gridxc_alloc_MOD_dealloc_l1+0x7e>\n+\tcbz\tr0, 1570 <__gridxc_alloc_MOD_dealloc_l1+0x7c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1610 <__gridxc_alloc_MOD_dealloc_l1+0xc0>)\n+\tldr\tr0, [pc, #64]\t@ (15b4 <__gridxc_alloc_MOD_dealloc_l1+0xc0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1614 <__gridxc_alloc_MOD_dealloc_l1+0xc4>)\n-\tldr\tr3, [pc, #28]\t@ (1608 <__gridxc_alloc_MOD_dealloc_l1+0xb8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (15b8 <__gridxc_alloc_MOD_dealloc_l1+0xc4>)\n+\tldr\tr3, [pc, #32]\t@ (15ac <__gridxc_alloc_MOD_dealloc_l1+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1600 <__gridxc_alloc_MOD_dealloc_l1+0xb0>\n+\tbne.n\t15a2 <__gridxc_alloc_MOD_dealloc_l1+0xae>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000068\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC26\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001618 <__gridxc_alloc_MOD_dealloc_z2>:\n+000015bc <__gridxc_alloc_MOD_dealloc_z2>:\n __gridxc_alloc_MOD_dealloc_z2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #180]\t@ (16e0 <__gridxc_alloc_MOD_dealloc_z2+0xc8>)\n+\tldr\tr2, [pc, #176]\t@ (1680 <__gridxc_alloc_MOD_dealloc_z2+0xc4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #180]\t@ (16e4 <__gridxc_alloc_MOD_dealloc_z2+0xcc>)\n+\tldr\tr3, [pc, #176]\t@ (1684 <__gridxc_alloc_MOD_dealloc_z2+0xc8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t16c0 <__gridxc_alloc_MOD_dealloc_z2+0xa8>\n+\tbeq.n\t1662 <__gridxc_alloc_MOD_dealloc_z2+0xa6>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n-\tit\teq\n-\tmoveq\tr8, r3\n \tstr\tr6, [sp, #4]\n+\tit\teq\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #128]\t@ (16e8 <__gridxc_alloc_MOD_dealloc_z2+0xd0>)\n+\tldr\tr1, [pc, #128]\t@ (1688 <__gridxc_alloc_MOD_dealloc_z2+0xcc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tadd\tr0, sp, #16\n \tsubs\tr3, r3, r2\n@@ -2446,171 +2406,169 @@\n \tmul.w\tr4, r3, ip\n \tmov\tr3, r9\n \tlsls\tr4, r4, #1\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 16a8 <__gridxc_alloc_MOD_dealloc_z2+0x90>\n+\tcbz\tr0, 164a <__gridxc_alloc_MOD_dealloc_z2+0x8e>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (16ec <__gridxc_alloc_MOD_dealloc_z2+0xd4>)\n+\tldr\tr0, [pc, #64]\t@ (168c <__gridxc_alloc_MOD_dealloc_z2+0xd0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (16f0 <__gridxc_alloc_MOD_dealloc_z2+0xd8>)\n-\tldr\tr3, [pc, #32]\t@ (16e4 <__gridxc_alloc_MOD_dealloc_z2+0xcc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1690 <__gridxc_alloc_MOD_dealloc_z2+0xd4>)\n+\tldr\tr3, [pc, #28]\t@ (1684 <__gridxc_alloc_MOD_dealloc_z2+0xc8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t16da <__gridxc_alloc_MOD_dealloc_z2+0xc2>\n+\tbne.n\t167c <__gridxc_alloc_MOD_dealloc_z2+0xc0>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000000ac\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000038\n+\t.word\t0x00000036\n R_ARM_REL32\t.bss\n-\t.word\t0x00000028\n+\t.word\t0x00000026\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000016f4 <__gridxc_alloc_MOD_dealloc_z1>:\n+00001694 <__gridxc_alloc_MOD_dealloc_z1>:\n __gridxc_alloc_MOD_dealloc_z1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #164]\t@ (17ac <__gridxc_alloc_MOD_dealloc_z1+0xb8>)\n+\tldr\tr2, [pc, #164]\t@ (174c <__gridxc_alloc_MOD_dealloc_z1+0xb8>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #164]\t@ (17b0 <__gridxc_alloc_MOD_dealloc_z1+0xbc>)\n+\tldr\tr3, [pc, #164]\t@ (1750 <__gridxc_alloc_MOD_dealloc_z1+0xbc>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 178e <__gridxc_alloc_MOD_dealloc_z1+0x9a>\n+\tcbz\tr3, 172c <__gridxc_alloc_MOD_dealloc_z1+0x98>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #116]\t@ (17b4 <__gridxc_alloc_MOD_dealloc_z1+0xc0>)\n+\tldr\tr1, [pc, #116]\t@ (1754 <__gridxc_alloc_MOD_dealloc_z1+0xc0>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \tmov.w\tip, ip, lsl #1\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1776 <__gridxc_alloc_MOD_dealloc_z1+0x82>\n+\tcbz\tr0, 1714 <__gridxc_alloc_MOD_dealloc_z1+0x80>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (17b8 <__gridxc_alloc_MOD_dealloc_z1+0xc4>)\n+\tldr\tr0, [pc, #64]\t@ (1758 <__gridxc_alloc_MOD_dealloc_z1+0xc4>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (17bc <__gridxc_alloc_MOD_dealloc_z1+0xc8>)\n-\tldr\tr3, [pc, #28]\t@ (17b0 <__gridxc_alloc_MOD_dealloc_z1+0xbc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (175c <__gridxc_alloc_MOD_dealloc_z1+0xc8>)\n+\tldr\tr3, [pc, #32]\t@ (1750 <__gridxc_alloc_MOD_dealloc_z1+0xbc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t17a8 <__gridxc_alloc_MOD_dealloc_z1+0xb4>\n+\tbne.n\t1746 <__gridxc_alloc_MOD_dealloc_z1+0xb2>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x0000009c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000006c\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000017c0 <__gridxc_alloc_MOD_dealloc_d4>:\n+00001760 <__gridxc_alloc_MOD_dealloc_d4>:\n __gridxc_alloc_MOD_dealloc_d4():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #208]\t@ (18a4 <__gridxc_alloc_MOD_dealloc_d4+0xe4>)\n+\tldr\tr2, [pc, #208]\t@ (1844 <__gridxc_alloc_MOD_dealloc_d4+0xe4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #208]\t@ (18a8 <__gridxc_alloc_MOD_dealloc_d4+0xe8>)\n+\tldr\tr3, [pc, #208]\t@ (1848 <__gridxc_alloc_MOD_dealloc_d4+0xe8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1886 <__gridxc_alloc_MOD_dealloc_d4+0xc6>\n+\tbeq.n\t1824 <__gridxc_alloc_MOD_dealloc_d4+0xc4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #156]\t@ (18ac <__gridxc_alloc_MOD_dealloc_d4+0xec>)\n+\tldr\tr1, [pc, #160]\t@ (184c <__gridxc_alloc_MOD_dealloc_d4+0xec>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -2630,86 +2588,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 186e <__gridxc_alloc_MOD_dealloc_d4+0xae>\n+\tcbz\tr0, 180c <__gridxc_alloc_MOD_dealloc_d4+0xac>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (18b0 <__gridxc_alloc_MOD_dealloc_d4+0xf0>)\n+\tldr\tr0, [pc, #64]\t@ (1850 <__gridxc_alloc_MOD_dealloc_d4+0xf0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (18b4 <__gridxc_alloc_MOD_dealloc_d4+0xf4>)\n-\tldr\tr3, [pc, #28]\t@ (18a8 <__gridxc_alloc_MOD_dealloc_d4+0xe8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1854 <__gridxc_alloc_MOD_dealloc_d4+0xf4>)\n+\tldr\tr3, [pc, #32]\t@ (1848 <__gridxc_alloc_MOD_dealloc_d4+0xe8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t18a0 <__gridxc_alloc_MOD_dealloc_d4+0xe0>\n+\tbne.n\t183e <__gridxc_alloc_MOD_dealloc_d4+0xde>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000c8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000096\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000018b8 <__gridxc_alloc_MOD_dealloc_d3>:\n+00001858 <__gridxc_alloc_MOD_dealloc_d3>:\n __gridxc_alloc_MOD_dealloc_d3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #192]\t@ (198c <__gridxc_alloc_MOD_dealloc_d3+0xd4>)\n+\tldr\tr2, [pc, #192]\t@ (192c <__gridxc_alloc_MOD_dealloc_d3+0xd4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #192]\t@ (1990 <__gridxc_alloc_MOD_dealloc_d3+0xd8>)\n+\tldr\tr3, [pc, #192]\t@ (1930 <__gridxc_alloc_MOD_dealloc_d3+0xd8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t196e <__gridxc_alloc_MOD_dealloc_d3+0xb6>\n+\tbeq.n\t190c <__gridxc_alloc_MOD_dealloc_d3+0xb4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #140]\t@ (1994 <__gridxc_alloc_MOD_dealloc_d3+0xdc>)\n+\tldr\tr1, [pc, #144]\t@ (1934 <__gridxc_alloc_MOD_dealloc_d3+0xdc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -2724,86 +2682,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1956 <__gridxc_alloc_MOD_dealloc_d3+0x9e>\n+\tcbz\tr0, 18f4 <__gridxc_alloc_MOD_dealloc_d3+0x9c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1998 <__gridxc_alloc_MOD_dealloc_d3+0xe0>)\n+\tldr\tr0, [pc, #64]\t@ (1938 <__gridxc_alloc_MOD_dealloc_d3+0xe0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (199c <__gridxc_alloc_MOD_dealloc_d3+0xe4>)\n-\tldr\tr3, [pc, #28]\t@ (1990 <__gridxc_alloc_MOD_dealloc_d3+0xd8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (193c <__gridxc_alloc_MOD_dealloc_d3+0xe4>)\n+\tldr\tr3, [pc, #32]\t@ (1930 <__gridxc_alloc_MOD_dealloc_d3+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1988 <__gridxc_alloc_MOD_dealloc_d3+0xd0>\n+\tbne.n\t1926 <__gridxc_alloc_MOD_dealloc_d3+0xce>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000086\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000019a0 <__gridxc_alloc_MOD_dealloc_d2>:\n+00001940 <__gridxc_alloc_MOD_dealloc_d2>:\n __gridxc_alloc_MOD_dealloc_d2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #180]\t@ (1a68 <__gridxc_alloc_MOD_dealloc_d2+0xc8>)\n+\tldr\tr2, [pc, #176]\t@ (1a04 <__gridxc_alloc_MOD_dealloc_d2+0xc4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #180]\t@ (1a6c <__gridxc_alloc_MOD_dealloc_d2+0xcc>)\n+\tldr\tr3, [pc, #176]\t@ (1a08 <__gridxc_alloc_MOD_dealloc_d2+0xc8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1a48 <__gridxc_alloc_MOD_dealloc_d2+0xa8>\n+\tbeq.n\t19e6 <__gridxc_alloc_MOD_dealloc_d2+0xa6>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n-\tit\teq\n-\tmoveq\tr8, r3\n \tstr\tr6, [sp, #4]\n+\tit\teq\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #128]\t@ (1a70 <__gridxc_alloc_MOD_dealloc_d2+0xd0>)\n+\tldr\tr1, [pc, #128]\t@ (1a0c <__gridxc_alloc_MOD_dealloc_d2+0xcc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tadd\tr0, sp, #16\n \tsubs\tr3, r3, r2\n@@ -2813,170 +2771,168 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tip, r3, ip\n \tmov\tr3, r9\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1a30 <__gridxc_alloc_MOD_dealloc_d2+0x90>\n+\tcbz\tr0, 19ce <__gridxc_alloc_MOD_dealloc_d2+0x8e>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1a74 <__gridxc_alloc_MOD_dealloc_d2+0xd4>)\n+\tldr\tr0, [pc, #64]\t@ (1a10 <__gridxc_alloc_MOD_dealloc_d2+0xd0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1a78 <__gridxc_alloc_MOD_dealloc_d2+0xd8>)\n-\tldr\tr3, [pc, #32]\t@ (1a6c <__gridxc_alloc_MOD_dealloc_d2+0xcc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1a14 <__gridxc_alloc_MOD_dealloc_d2+0xd4>)\n+\tldr\tr3, [pc, #28]\t@ (1a08 <__gridxc_alloc_MOD_dealloc_d2+0xc8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1a62 <__gridxc_alloc_MOD_dealloc_d2+0xc2>\n+\tbne.n\t1a00 <__gridxc_alloc_MOD_dealloc_d2+0xc0>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000000ac\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000038\n+\t.word\t0x00000036\n R_ARM_REL32\t.bss\n-\t.word\t0x00000028\n+\t.word\t0x00000026\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001a7c <__gridxc_alloc_MOD_dealloc_d1>:\n+00001a18 <__gridxc_alloc_MOD_dealloc_d1>:\n __gridxc_alloc_MOD_dealloc_d1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #160]\t@ (1b30 <__gridxc_alloc_MOD_dealloc_d1+0xb4>)\n+\tldr\tr2, [pc, #160]\t@ (1acc <__gridxc_alloc_MOD_dealloc_d1+0xb4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #160]\t@ (1b34 <__gridxc_alloc_MOD_dealloc_d1+0xb8>)\n+\tldr\tr3, [pc, #160]\t@ (1ad0 <__gridxc_alloc_MOD_dealloc_d1+0xb8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 1b12 <__gridxc_alloc_MOD_dealloc_d1+0x96>\n+\tcbz\tr3, 1aac <__gridxc_alloc_MOD_dealloc_d1+0x94>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #112]\t@ (1b38 <__gridxc_alloc_MOD_dealloc_d1+0xbc>)\n+\tldr\tr1, [pc, #112]\t@ (1ad4 <__gridxc_alloc_MOD_dealloc_d1+0xbc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1afa <__gridxc_alloc_MOD_dealloc_d1+0x7e>\n+\tcbz\tr0, 1a94 <__gridxc_alloc_MOD_dealloc_d1+0x7c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1b3c <__gridxc_alloc_MOD_dealloc_d1+0xc0>)\n+\tldr\tr0, [pc, #64]\t@ (1ad8 <__gridxc_alloc_MOD_dealloc_d1+0xc0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1b40 <__gridxc_alloc_MOD_dealloc_d1+0xc4>)\n-\tldr\tr3, [pc, #28]\t@ (1b34 <__gridxc_alloc_MOD_dealloc_d1+0xb8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1adc <__gridxc_alloc_MOD_dealloc_d1+0xc4>)\n+\tldr\tr3, [pc, #32]\t@ (1ad0 <__gridxc_alloc_MOD_dealloc_d1+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1b2c <__gridxc_alloc_MOD_dealloc_d1+0xb0>\n+\tbne.n\t1ac6 <__gridxc_alloc_MOD_dealloc_d1+0xae>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000068\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001b44 <__gridxc_alloc_MOD_dealloc_r4>:\n+00001ae0 <__gridxc_alloc_MOD_dealloc_r4>:\n __gridxc_alloc_MOD_dealloc_r4():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #208]\t@ (1c28 <__gridxc_alloc_MOD_dealloc_r4+0xe4>)\n+\tldr\tr2, [pc, #208]\t@ (1bc4 <__gridxc_alloc_MOD_dealloc_r4+0xe4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #208]\t@ (1c2c <__gridxc_alloc_MOD_dealloc_r4+0xe8>)\n+\tldr\tr3, [pc, #208]\t@ (1bc8 <__gridxc_alloc_MOD_dealloc_r4+0xe8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1c0a <__gridxc_alloc_MOD_dealloc_r4+0xc6>\n+\tbeq.n\t1ba4 <__gridxc_alloc_MOD_dealloc_r4+0xc4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #156]\t@ (1c30 <__gridxc_alloc_MOD_dealloc_r4+0xec>)\n+\tldr\tr1, [pc, #160]\t@ (1bcc <__gridxc_alloc_MOD_dealloc_r4+0xec>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -2996,86 +2952,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1bf2 <__gridxc_alloc_MOD_dealloc_r4+0xae>\n+\tcbz\tr0, 1b8c <__gridxc_alloc_MOD_dealloc_r4+0xac>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1c34 <__gridxc_alloc_MOD_dealloc_r4+0xf0>)\n+\tldr\tr0, [pc, #64]\t@ (1bd0 <__gridxc_alloc_MOD_dealloc_r4+0xf0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1c38 <__gridxc_alloc_MOD_dealloc_r4+0xf4>)\n-\tldr\tr3, [pc, #28]\t@ (1c2c <__gridxc_alloc_MOD_dealloc_r4+0xe8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1bd4 <__gridxc_alloc_MOD_dealloc_r4+0xf4>)\n+\tldr\tr3, [pc, #32]\t@ (1bc8 <__gridxc_alloc_MOD_dealloc_r4+0xe8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1c24 <__gridxc_alloc_MOD_dealloc_r4+0xe0>\n+\tbne.n\t1bbe <__gridxc_alloc_MOD_dealloc_r4+0xde>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000c8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000096\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001c3c <__gridxc_alloc_MOD_dealloc_r3>:\n+00001bd8 <__gridxc_alloc_MOD_dealloc_r3>:\n __gridxc_alloc_MOD_dealloc_r3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #192]\t@ (1d10 <__gridxc_alloc_MOD_dealloc_r3+0xd4>)\n+\tldr\tr2, [pc, #192]\t@ (1cac <__gridxc_alloc_MOD_dealloc_r3+0xd4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #192]\t@ (1d14 <__gridxc_alloc_MOD_dealloc_r3+0xd8>)\n+\tldr\tr3, [pc, #192]\t@ (1cb0 <__gridxc_alloc_MOD_dealloc_r3+0xd8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1cf2 <__gridxc_alloc_MOD_dealloc_r3+0xb6>\n+\tbeq.n\t1c8c <__gridxc_alloc_MOD_dealloc_r3+0xb4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #140]\t@ (1d18 <__gridxc_alloc_MOD_dealloc_r3+0xdc>)\n+\tldr\tr1, [pc, #144]\t@ (1cb4 <__gridxc_alloc_MOD_dealloc_r3+0xdc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -3090,86 +3046,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1cda <__gridxc_alloc_MOD_dealloc_r3+0x9e>\n+\tcbz\tr0, 1c74 <__gridxc_alloc_MOD_dealloc_r3+0x9c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1d1c <__gridxc_alloc_MOD_dealloc_r3+0xe0>)\n+\tldr\tr0, [pc, #64]\t@ (1cb8 <__gridxc_alloc_MOD_dealloc_r3+0xe0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1d20 <__gridxc_alloc_MOD_dealloc_r3+0xe4>)\n-\tldr\tr3, [pc, #28]\t@ (1d14 <__gridxc_alloc_MOD_dealloc_r3+0xd8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1cbc <__gridxc_alloc_MOD_dealloc_r3+0xe4>)\n+\tldr\tr3, [pc, #32]\t@ (1cb0 <__gridxc_alloc_MOD_dealloc_r3+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1d0c <__gridxc_alloc_MOD_dealloc_r3+0xd0>\n+\tbne.n\t1ca6 <__gridxc_alloc_MOD_dealloc_r3+0xce>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000086\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001d24 <__gridxc_alloc_MOD_dealloc_r2>:\n+00001cc0 <__gridxc_alloc_MOD_dealloc_r2>:\n __gridxc_alloc_MOD_dealloc_r2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #180]\t@ (1dec <__gridxc_alloc_MOD_dealloc_r2+0xc8>)\n+\tldr\tr2, [pc, #176]\t@ (1d84 <__gridxc_alloc_MOD_dealloc_r2+0xc4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #180]\t@ (1df0 <__gridxc_alloc_MOD_dealloc_r2+0xcc>)\n+\tldr\tr3, [pc, #176]\t@ (1d88 <__gridxc_alloc_MOD_dealloc_r2+0xc8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1dcc <__gridxc_alloc_MOD_dealloc_r2+0xa8>\n+\tbeq.n\t1d66 <__gridxc_alloc_MOD_dealloc_r2+0xa6>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n-\tit\teq\n-\tmoveq\tr8, r3\n \tstr\tr6, [sp, #4]\n+\tit\teq\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #128]\t@ (1df4 <__gridxc_alloc_MOD_dealloc_r2+0xd0>)\n+\tldr\tr1, [pc, #128]\t@ (1d8c <__gridxc_alloc_MOD_dealloc_r2+0xcc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tadd\tr0, sp, #16\n \tsubs\tr3, r3, r2\n@@ -3179,253 +3135,251 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tip, r3, ip\n \tmov\tr3, r9\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1db4 <__gridxc_alloc_MOD_dealloc_r2+0x90>\n+\tcbz\tr0, 1d4e <__gridxc_alloc_MOD_dealloc_r2+0x8e>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1df8 <__gridxc_alloc_MOD_dealloc_r2+0xd4>)\n+\tldr\tr0, [pc, #64]\t@ (1d90 <__gridxc_alloc_MOD_dealloc_r2+0xd0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1dfc <__gridxc_alloc_MOD_dealloc_r2+0xd8>)\n-\tldr\tr3, [pc, #32]\t@ (1df0 <__gridxc_alloc_MOD_dealloc_r2+0xcc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1d94 <__gridxc_alloc_MOD_dealloc_r2+0xd4>)\n+\tldr\tr3, [pc, #28]\t@ (1d88 <__gridxc_alloc_MOD_dealloc_r2+0xc8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1de6 <__gridxc_alloc_MOD_dealloc_r2+0xc2>\n+\tbne.n\t1d80 <__gridxc_alloc_MOD_dealloc_r2+0xc0>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000000ac\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000038\n+\t.word\t0x00000036\n R_ARM_REL32\t.bss\n-\t.word\t0x00000028\n+\t.word\t0x00000026\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001e00 <__gridxc_alloc_MOD_dealloc_r1>:\n+00001d98 <__gridxc_alloc_MOD_dealloc_r1>:\n __gridxc_alloc_MOD_dealloc_r1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #160]\t@ (1eb4 <__gridxc_alloc_MOD_dealloc_r1+0xb4>)\n+\tldr\tr2, [pc, #160]\t@ (1e4c <__gridxc_alloc_MOD_dealloc_r1+0xb4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #160]\t@ (1eb8 <__gridxc_alloc_MOD_dealloc_r1+0xb8>)\n+\tldr\tr3, [pc, #160]\t@ (1e50 <__gridxc_alloc_MOD_dealloc_r1+0xb8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 1e96 <__gridxc_alloc_MOD_dealloc_r1+0x96>\n+\tcbz\tr3, 1e2c <__gridxc_alloc_MOD_dealloc_r1+0x94>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #112]\t@ (1ebc <__gridxc_alloc_MOD_dealloc_r1+0xbc>)\n+\tldr\tr1, [pc, #112]\t@ (1e54 <__gridxc_alloc_MOD_dealloc_r1+0xbc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1e7e <__gridxc_alloc_MOD_dealloc_r1+0x7e>\n+\tcbz\tr0, 1e14 <__gridxc_alloc_MOD_dealloc_r1+0x7c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1ec0 <__gridxc_alloc_MOD_dealloc_r1+0xc0>)\n+\tldr\tr0, [pc, #64]\t@ (1e58 <__gridxc_alloc_MOD_dealloc_r1+0xc0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1ec4 <__gridxc_alloc_MOD_dealloc_r1+0xc4>)\n-\tldr\tr3, [pc, #28]\t@ (1eb8 <__gridxc_alloc_MOD_dealloc_r1+0xb8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1e5c <__gridxc_alloc_MOD_dealloc_r1+0xc4>)\n+\tldr\tr3, [pc, #32]\t@ (1e50 <__gridxc_alloc_MOD_dealloc_r1+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1eb0 <__gridxc_alloc_MOD_dealloc_r1+0xb0>\n+\tbne.n\t1e46 <__gridxc_alloc_MOD_dealloc_r1+0xae>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000068\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001ec8 <__gridxc_alloc_MOD_dealloc_e1>:\n+00001e60 <__gridxc_alloc_MOD_dealloc_e1>:\n __gridxc_alloc_MOD_dealloc_e1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #160]\t@ (1f7c <__gridxc_alloc_MOD_dealloc_e1+0xb4>)\n+\tldr\tr2, [pc, #160]\t@ (1f14 <__gridxc_alloc_MOD_dealloc_e1+0xb4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #160]\t@ (1f80 <__gridxc_alloc_MOD_dealloc_e1+0xb8>)\n+\tldr\tr3, [pc, #160]\t@ (1f18 <__gridxc_alloc_MOD_dealloc_e1+0xb8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 1f5e <__gridxc_alloc_MOD_dealloc_e1+0x96>\n+\tcbz\tr3, 1ef4 <__gridxc_alloc_MOD_dealloc_e1+0x94>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #112]\t@ (1f84 <__gridxc_alloc_MOD_dealloc_e1+0xbc>)\n+\tldr\tr1, [pc, #112]\t@ (1f1c <__gridxc_alloc_MOD_dealloc_e1+0xbc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 1f46 <__gridxc_alloc_MOD_dealloc_e1+0x7e>\n+\tcbz\tr0, 1edc <__gridxc_alloc_MOD_dealloc_e1+0x7c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (1f88 <__gridxc_alloc_MOD_dealloc_e1+0xc0>)\n+\tldr\tr0, [pc, #64]\t@ (1f20 <__gridxc_alloc_MOD_dealloc_e1+0xc0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (1f8c <__gridxc_alloc_MOD_dealloc_e1+0xc4>)\n-\tldr\tr3, [pc, #28]\t@ (1f80 <__gridxc_alloc_MOD_dealloc_e1+0xb8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (1f24 <__gridxc_alloc_MOD_dealloc_e1+0xc4>)\n+\tldr\tr3, [pc, #32]\t@ (1f18 <__gridxc_alloc_MOD_dealloc_e1+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1f78 <__gridxc_alloc_MOD_dealloc_e1+0xb0>\n+\tbne.n\t1f0e <__gridxc_alloc_MOD_dealloc_e1+0xae>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000068\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001f90 <__gridxc_alloc_MOD_dealloc_i3>:\n+00001f28 <__gridxc_alloc_MOD_dealloc_i3>:\n __gridxc_alloc_MOD_dealloc_i3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #192]\t@ (2064 <__gridxc_alloc_MOD_dealloc_i3+0xd4>)\n+\tldr\tr2, [pc, #192]\t@ (1ffc <__gridxc_alloc_MOD_dealloc_i3+0xd4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #192]\t@ (2068 <__gridxc_alloc_MOD_dealloc_i3+0xd8>)\n+\tldr\tr3, [pc, #192]\t@ (2000 <__gridxc_alloc_MOD_dealloc_i3+0xd8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t2046 <__gridxc_alloc_MOD_dealloc_i3+0xb6>\n+\tbeq.n\t1fdc <__gridxc_alloc_MOD_dealloc_i3+0xb4>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tstr\tr6, [sp, #4]\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #140]\t@ (206c <__gridxc_alloc_MOD_dealloc_i3+0xdc>)\n+\tldr\tr1, [pc, #144]\t@ (2004 <__gridxc_alloc_MOD_dealloc_i3+0xdc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tsubs\tr3, r3, r2\n \tbic.w\tip, ip, ip, asr #31\n@@ -3440,86 +3394,86 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n \tmov\tr3, r9\n \tnegs\tr4, r4\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 202e <__gridxc_alloc_MOD_dealloc_i3+0x9e>\n+\tcbz\tr0, 1fc4 <__gridxc_alloc_MOD_dealloc_i3+0x9c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (2070 <__gridxc_alloc_MOD_dealloc_i3+0xe0>)\n+\tldr\tr0, [pc, #64]\t@ (2008 <__gridxc_alloc_MOD_dealloc_i3+0xe0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (2074 <__gridxc_alloc_MOD_dealloc_i3+0xe4>)\n-\tldr\tr3, [pc, #28]\t@ (2068 <__gridxc_alloc_MOD_dealloc_i3+0xd8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (200c <__gridxc_alloc_MOD_dealloc_i3+0xe4>)\n+\tldr\tr3, [pc, #32]\t@ (2000 <__gridxc_alloc_MOD_dealloc_i3+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t2060 <__gridxc_alloc_MOD_dealloc_i3+0xd0>\n+\tbne.n\t1ff6 <__gridxc_alloc_MOD_dealloc_i3+0xce>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x000000b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000086\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00002078 <__gridxc_alloc_MOD_dealloc_i2>:\n+00002010 <__gridxc_alloc_MOD_dealloc_i2>:\n __gridxc_alloc_MOD_dealloc_i2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #180]\t@ (2140 <__gridxc_alloc_MOD_dealloc_i2+0xc8>)\n+\tldr\tr2, [pc, #176]\t@ (20d4 <__gridxc_alloc_MOD_dealloc_i2+0xc4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #180]\t@ (2144 <__gridxc_alloc_MOD_dealloc_i2+0xcc>)\n+\tldr\tr3, [pc, #176]\t@ (20d8 <__gridxc_alloc_MOD_dealloc_i2+0xc8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t2120 <__gridxc_alloc_MOD_dealloc_i2+0xa8>\n+\tbeq.n\t20b6 <__gridxc_alloc_MOD_dealloc_i2+0xa6>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n-\tit\teq\n-\tmoveq\tr8, r3\n \tstr\tr6, [sp, #4]\n+\tit\teq\n+\tmoveq.w\tr8, #0\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #128]\t@ (2148 <__gridxc_alloc_MOD_dealloc_i2+0xd0>)\n+\tldr\tr1, [pc, #128]\t@ (20dc <__gridxc_alloc_MOD_dealloc_i2+0xcc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tsub.w\tip, r2, r3\n \tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tadd.w\tip, ip, #1\n \tadd\tr0, sp, #16\n \tsubs\tr3, r3, r2\n@@ -3529,10846 +3483,10482 @@\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tip, r3, ip\n \tmov\tr3, r9\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 2108 <__gridxc_alloc_MOD_dealloc_i2+0x90>\n+\tcbz\tr0, 209e <__gridxc_alloc_MOD_dealloc_i2+0x8e>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (214c <__gridxc_alloc_MOD_dealloc_i2+0xd4>)\n+\tldr\tr0, [pc, #64]\t@ (20e0 <__gridxc_alloc_MOD_dealloc_i2+0xd0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (2150 <__gridxc_alloc_MOD_dealloc_i2+0xd8>)\n-\tldr\tr3, [pc, #32]\t@ (2144 <__gridxc_alloc_MOD_dealloc_i2+0xcc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (20e4 <__gridxc_alloc_MOD_dealloc_i2+0xd4>)\n+\tldr\tr3, [pc, #28]\t@ (20d8 <__gridxc_alloc_MOD_dealloc_i2+0xc8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t213a <__gridxc_alloc_MOD_dealloc_i2+0xc2>\n+\tbne.n\t20d0 <__gridxc_alloc_MOD_dealloc_i2+0xc0>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000000ac\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000007a\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000038\n+\t.word\t0x00000036\n R_ARM_REL32\t.bss\n-\t.word\t0x00000028\n+\t.word\t0x00000026\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00002154 <__gridxc_alloc_MOD_dealloc_i1>:\n+000020e8 <__gridxc_alloc_MOD_dealloc_i1>:\n __gridxc_alloc_MOD_dealloc_i1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r2\n-\tldr\tr2, [pc, #160]\t@ (2208 <__gridxc_alloc_MOD_dealloc_i1+0xb4>)\n+\tldr\tr2, [pc, #160]\t@ (219c <__gridxc_alloc_MOD_dealloc_i1+0xb4>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #160]\t@ (220c <__gridxc_alloc_MOD_dealloc_i1+0xb8>)\n+\tldr\tr3, [pc, #160]\t@ (21a0 <__gridxc_alloc_MOD_dealloc_i1+0xb8>)\n \tadd\tr2, pc\n \tsub\tsp, #28\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #20]\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n-\tcbz\tr3, 21ea <__gridxc_alloc_MOD_dealloc_i1+0x96>\n+\tcbz\tr3, 217c <__gridxc_alloc_MOD_dealloc_i1+0x94>\n \tcmp\tr1, #0\n-\tmov.w\tr3, #0\n+\tmov\tr5, r0\n \tit\teq\n \tmoveq\tr6, #0\n \tcmp.w\tr9, #0\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #0\n \tstr\tr6, [sp, #4]\n \tstr.w\tr8, [sp, #8]\n-\tmov\tr5, r0\n \tmov\tr7, r1\n-\tldr\tr1, [pc, #112]\t@ (2210 <__gridxc_alloc_MOD_dealloc_i1+0xbc>)\n+\tldr\tr1, [pc, #112]\t@ (21a4 <__gridxc_alloc_MOD_dealloc_i1+0xbc>)\n \tldrd\tr3, r2, [r0, #28]\n \tadd\tr1, pc\n \tadd\tr0, sp, #16\n \tsub.w\tip, r2, r3\n \tmov\tr3, r9\n \tadd.w\tip, ip, #1\n \tmov\tr2, r7\n \tbic.w\tip, ip, ip, asr #31\n \trsb\tr4, ip, #0\n \tstr\tr4, [sp, #16]\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [r5, #0]\n-\tcbz\tr0, 21d2 <__gridxc_alloc_MOD_dealloc_i1+0x7e>\n+\tcbz\tr0, 2164 <__gridxc_alloc_MOD_dealloc_i1+0x7c>\n \tmovs\tr4, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr4, [r5, #0]\n-\tldr\tr0, [pc, #64]\t@ (2214 <__gridxc_alloc_MOD_dealloc_i1+0xc0>)\n+\tldr\tr0, [pc, #64]\t@ (21a8 <__gridxc_alloc_MOD_dealloc_i1+0xc0>)\n \tmov\tr2, r9\n \tmov\tr1, r7\n \tmovs\tr3, #0\n \tadd\tr0, pc\n \tstr.w\tr4, [r0, #16]!\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #44]\t@ (2218 <__gridxc_alloc_MOD_dealloc_i1+0xc4>)\n-\tldr\tr3, [pc, #28]\t@ (220c <__gridxc_alloc_MOD_dealloc_i1+0xb8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #44]\t@ (21ac <__gridxc_alloc_MOD_dealloc_i1+0xc4>)\n+\tldr\tr3, [pc, #32]\t@ (21a0 <__gridxc_alloc_MOD_dealloc_i1+0xb8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t2204 <__gridxc_alloc_MOD_dealloc_i1+0xb0>\n+\tbne.n\t2196 <__gridxc_alloc_MOD_dealloc_i1+0xae>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000068\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000036\n+\t.word\t0x00000038\n R_ARM_REL32\t.bss\n-\t.word\t0x00000026\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000221c <__gridxc_alloc_MOD_realloc_s1>:\n+000021b0 <__gridxc_alloc_MOD_realloc_s1>:\n __gridxc_alloc_MOD_realloc_s1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3736]\t@ 0xe98\n-\tsub\tsp, #324\t@ 0x144\n+\tstr.w\tr0, [ip, #3744]\t@ 0xea0\n+\tsub\tsp, #316\t@ 0x13c\n \tadd\tr7, sp, #16\n-\tldr\tr5, [pc, #884]\t@ (25a8 <__gridxc_alloc_MOD_realloc_s1+0x38c>)\n \tmov\tr4, r0\n-\tldr\tr6, [pc, #884]\t@ (25ac <__gridxc_alloc_MOD_realloc_s1+0x390>)\n-\tadd\tr5, pc\n-\tmov\tr8, r2\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tadd\tr6, pc\n-\tldr\tr3, [pc, #880]\t@ (25b0 <__gridxc_alloc_MOD_realloc_s1+0x394>)\n-\tmovs\tr2, #1\n-\tldr.w\tr0, [r7, #344]\t@ 0x158\n-\tstr\tr0, [r7, #56]\t@ 0x38\n-\tldr.w\tr0, [r7, #348]\t@ 0x15c\n-\tldr\tr3, [r5, r3]\n-\tldrd\tip, r5, [r7, #352]\t@ 0x160\n+\tldr.w\tr0, [r7, #336]\t@ 0x150\n+\tstr\tr0, [r7, #60]\t@ 0x3c\n+\tldr.w\tr0, [pc, #1200]\t@ 2680 <__gridxc_alloc_MOD_realloc_s1+0x4d0>\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tldr.w\tr3, [pc, #1200]\t@ 2684 <__gridxc_alloc_MOD_realloc_s1+0x4d4>\n+\tadd\tr0, pc\n+\tldr.w\tr5, [r7, #348]\t@ 0x15c\n+\tldr.w\tip, [r7, #340]\t@ 0x154\n+\tldr.w\tlr, [r7, #344]\t@ 0x158\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1184]\t@ 2688 <__gridxc_alloc_MOD_realloc_s1+0x4d8>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n+\tadd\tr0, pc\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [r6, #0]\n-\tbic.w\tr2, r5, r5, asr #31\n-\tstr\tr2, [r7, #48]\t@ 0x30\n-\tbeq.w\t2550 <__gridxc_alloc_MOD_realloc_s1+0x334>\n-\tldr\tr2, [r4, #32]\n-\tldr\tr6, [r4, #4]\n-\tstr\tr3, [r7, #52]\t@ 0x34\n+\titet\teq\n+\tstreq\tr3, [r7, #24]\n+\tmovne\tr6, #1\n+\tmoveq\tr6, #0\n+\tstr\tr6, [r0, #0]\n+\tbic.w\tr0, r5, r5, asr #31\n+\tstr\tr0, [r7, #44]\t@ 0x2c\n+\tbeq.n\t2232 <__gridxc_alloc_MOD_realloc_s1+0x82>\n+\tldr\tr0, [r4, #32]\n+\tstr\tr3, [r7, #48]\t@ 0x30\n \tldr\tr3, [r4, #28]\n-\tstr\tr6, [r7, #8]\n-\tldr\tr6, [r4, #24]\n-\tcmp\tr2, r3\n-\tstr\tr6, [r7, #12]\n-\tldr\tr6, [r4, #20]\n-\tstr\tr3, [r7, #24]\n+\tstr\tr3, [r7, #32]\n+\tcmp\tr0, r3\n+\tldr\tr6, [r4, #4]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr2, [r7, #20]\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tite\tge\n+\tmovge\tr3, r0\n+\tmovlt\tr3, #0\n \tstr\tr3, [r7, #96]\t@ 0x60\n-\tmov\tr3, r2\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #20]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr0, [r7, #28]\n \tstr\tr6, [r7, #16]\n-\tit\tlt\n-\tmovlt\tr3, #0\n-\tstr\tr3, [r7, #100]\t@ 0x64\n+\tstr\tr3, [r7, #24]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #752]\t@ 2590 <__gridxc_alloc_MOD_realloc_s1+0x374>\n-\tvldr\td19, [pc, #756]\t@ 2598 <__gridxc_alloc_MOD_realloc_s1+0x37c>\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\tldr.w\tr3, [r8]\n-\tadd.w\tr2, r7, #248\t@ 0xf8\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n-\tadd.w\tr3, r7, #124\t@ 0x7c\n-\tvldr\td17, [pc, #744]\t@ 25a0 <__gridxc_alloc_MOD_realloc_s1+0x384>\n \tmovs\tr6, #1\n-\tvstr\td16, [r7, #112]\t@ 0x70\n-\tadd.w\tr9, r7, #88\t@ 0x58\n-\tvstr\td16, [r7, #116]\t@ 0x74\n-\tadd.w\tr1, r7, #152\t@ 0x98\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #140\t@ 0x8c\n-\tldr.w\tr8, [pc, #736]\t@ 25b4 <__gridxc_alloc_MOD_realloc_s1+0x398>\n-\tvstr\td16, [r7, #160]\t@ 0xa0\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #172\t@ 0xac\n-\tvstr\td16, [r7, #164]\t@ 0xa4\n+\tstr\tr3, [r7, #84]\t@ 0x54\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr8, r7, #68\t@ 0x44\n+\tstr\tr3, [r7, #88]\t@ 0x58\n+\tadd.w\tr3, r7, #244\t@ 0xf4\n+\tstrd\tr2, r2, [r7, #132]\t@ 0x84\n+\tadd.w\tr9, r7, #84\t@ 0x54\n+\tstr\tr3, [r7, #56]\t@ 0x38\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #180]\t@ 0xb4\n+\tstrd\tr3, r3, [r7, #108]\t@ 0x6c\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tstrd\tr3, r3, [r7, #156]\t@ 0x9c\n+\tstr.w\tr3, [r7, #164]\t@ 0xa4\n+\tstrd\tr3, r3, [r7, #204]\t@ 0xcc\n+\tstr.w\tr3, [r7, #212]\t@ 0xd4\n+\tstr\tr0, [r7, #120]\t@ 0x78\n+\tstr.w\tr0, [r7, #168]\t@ 0xa8\n+\tstr.w\tr0, [r7, #216]\t@ 0xd8\n+\tstr\tr1, [r7, #104]\t@ 0x68\n+\tstr.w\tr1, [r7, #152]\t@ 0x98\n+\tstr.w\tr8, [r7, #100]\t@ 0x64\n+\tadd.w\tr8, r7, #76\t@ 0x4c\n+\tstrd\tr6, r6, [r7, #124]\t@ 0x7c\n+\tstrd\tr6, r6, [r7, #140]\t@ 0x8c\n+\tstrd\tr6, r6, [r7, #172]\t@ 0xac\n+\tstrd\tr6, r6, [r7, #188]\t@ 0xbc\n+\tstr.w\tr8, [r7, #148]\t@ 0x94\n+\tldr.w\tr8, [pc, #1004]\t@ 268c <__gridxc_alloc_MOD_realloc_s1+0x4dc>\n+\tstrd\tr1, r3, [r7, #248]\t@ 0xf8\n+\tstr.w\tr0, [r7, #264]\t@ 0x108\n \tadd\tr8, pc\n-\tvstr\td16, [r7, #208]\t@ 0xd0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #188\t@ 0xbc\n-\tvstr\td16, [r7, #212]\t@ 0xd4\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #220\t@ 0xdc\n-\tvstr\td16, [r7, #256]\t@ 0x100\n-\tvstr\td16, [r7, #260]\t@ 0x104\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #236\t@ 0xec\n+\tstr.w\tr2, [r7, #228]\t@ 0xe4\n+\tadd.w\tr0, r7, #100\t@ 0x64\n+\tstr.w\tr2, [r7, #232]\t@ 0xe8\n+\tstr.w\tr1, [r7, #200]\t@ 0xc8\n+\tadd.w\tr1, r7, #148\t@ 0x94\n+\tstrd\tr3, r3, [r7, #256]\t@ 0x100\n+\tstrd\tr6, r2, [r7, #272]\t@ 0x110\n+\tstr.w\tr2, [r7, #280]\t@ 0x118\n+\tadd.w\tr2, r7, #92\t@ 0x5c\n+\tstr.w\tr6, [r7, #224]\t@ 0xe0\n \tstr\tr2, [r7, #36]\t@ 0x24\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tstr.w\tr6, [r7, #148]\t@ 0x94\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #284\t@ 0x11c\n-\tstr.w\tr6, [r7, #196]\t@ 0xc4\n-\tvst1.32\t{d17}, [r3]\n-\tstr\tr3, [r7, #40]\t@ 0x28\n-\tmvn.w\tr3, #2\n-\tstr.w\tr6, [r7, #244]\t@ 0xf4\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tstr.w\tr3, [r7, #156]\t@ 0x9c\n-\tstr.w\tr3, [r7, #204]\t@ 0xcc\n-\tstr.w\tr3, [r7, #252]\t@ 0xfc\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr6, [r7, #292]\t@ 0x124\n-\tstr\tr3, [r7, #104]\t@ 0x68\n-\tadd.w\tr3, r7, #80\t@ 0x50\n-\tstr.w\tr3, [r7, #152]\t@ 0x98\n-\tadd.w\tr3, r7, #96\t@ 0x60\n-\tstr.w\tr9, [r7, #248]\t@ 0xf8\n-\tstr\tr3, [r7, #28]\n-\tstr.w\tr3, [r7, #200]\t@ 0xc8\n-\tmov\tr3, r2\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr2, r7, #200\t@ 0xc8\n-\tadd.w\tr0, r7, #104\t@ 0x68\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #196]\t@ 0xc4\n+\tadd.w\tr2, r7, #196\t@ 0xc4\n+\tstr.w\tr6, [r7, #220]\t@ 0xdc\n+\tstrd\tr6, r6, [r7, #236]\t@ 0xec\n+\tstr.w\tr6, [r7, #268]\t@ 0x10c\n+\tstrd\tr6, r6, [r7, #284]\t@ 0x11c\n+\tstr.w\tr9, [r7, #244]\t@ 0xf4\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r8, #8]\n-\tcbz\tr3, 23dc <__gridxc_alloc_MOD_realloc_s1+0x1c0>\n+\tcbz\tr3, 235e <__gridxc_alloc_MOD_realloc_s1+0x1ae>\n \tldr.w\tsl, [r8, #12]\n \tcmp.w\tsl, #0\n-\tbne.n\t2412 <__gridxc_alloc_MOD_realloc_s1+0x1f6>\n-\tldrd\tr3, r2, [r7, #20]\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n-\tsubs\tr3, r3, r2\n-\tldr\tr2, [r7, #48]\t@ 0x30\n+\tbne.n\t2394 <__gridxc_alloc_MOD_realloc_s1+0x1e4>\n+\tldrd\tr3, r1, [r7, #28]\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tsubs\tr3, r3, r1\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n \tadd\tr3, r6\n-\tcmp\tr0, #0\n-\tldr\tr1, [pc, #540]\t@ (25b8 <__gridxc_alloc_MOD_realloc_s1+0x39c>)\n+\tcmp\tr2, #0\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd\tr1, pc\n-\tmul.w\tr3, r2, r3\n+\tmul.w\tr3, r1, r3\n+\tldr\tr1, [pc, #876]\t@ (2690 <__gridxc_alloc_MOD_realloc_s1+0x4e0>)\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #68]\t@ 0x44\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tstr\tr6, [sp, #0]\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tadd\tr1, pc\n+\tldr.w\tr3, [r7, #352]\t@ 0x160\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n-\tcmp\tr3, #0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tldr.w\tr3, [r7, #356]\t@ 0x164\n+\tcmp\tr0, #0\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r0\n-\tadd.w\tr0, r7, #68\t@ 0x44\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r0\n+\tadd.w\tr0, r7, #64\t@ 0x40\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr.w\tsl, [r8, #16]\n-\tstr.w\tsl, [r7, #52]\t@ 0x34\n-\tldr\tr3, [pc, #476]\t@ (25bc <__gridxc_alloc_MOD_realloc_s1+0x3a0>)\n+\tstr.w\tsl, [r7, #48]\t@ 0x30\n+\tldr\tr3, [pc, #820]\t@ (2694 <__gridxc_alloc_MOD_realloc_s1+0x4e4>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 241c <__gridxc_alloc_MOD_realloc_s1+0x200>\n-\tldr\tr3, [pc, #472]\t@ (25c0 <__gridxc_alloc_MOD_realloc_s1+0x3a4>)\n+\tcbnz\tr3, 239e <__gridxc_alloc_MOD_realloc_s1+0x1ee>\n+\tldr\tr3, [pc, #816]\t@ (2698 <__gridxc_alloc_MOD_realloc_s1+0x4e8>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t2554 <__gridxc_alloc_MOD_realloc_s1+0x338>\n-\tldr\tr2, [pc, #464]\t@ (25c4 <__gridxc_alloc_MOD_realloc_s1+0x3a8>)\n-\tldr\tr3, [pc, #444]\t@ (25b0 <__gridxc_alloc_MOD_realloc_s1+0x394>)\n+\tbne.w\t24c6 <__gridxc_alloc_MOD_realloc_s1+0x316>\n+\tldr\tr2, [pc, #808]\t@ (269c <__gridxc_alloc_MOD_realloc_s1+0x4ec>)\n+\tldr\tr3, [pc, #780]\t@ (2684 <__gridxc_alloc_MOD_realloc_s1+0x4d4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr3, [r7, #292]\t@ 0x124\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2752 <__gridxc_alloc_MOD_realloc_s1+0x536>\n-\tadd.w\tr7, r7, #308\t@ 0x134\n+\tbne.w\t2676 <__gridxc_alloc_MOD_realloc_s1+0x4c6>\n+\tadd.w\tr7, r7, #300\t@ 0x12c\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t2554 <__gridxc_alloc_MOD_realloc_s1+0x338>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmovw\tr3, #1537\t@ 0x601\n-\tldrd\tr6, r8, [r7, #72]\t@ 0x48\n+\tbeq.w\t24c6 <__gridxc_alloc_MOD_realloc_s1+0x316>\n+\tldrd\tr6, r8, [r7, #68]\t@ 0x44\n+\tmovs\tr2, #0\n \tstr\tr5, [r4, #8]\n-\tvstr\td16, [r4, #12]\n-\tstrh\tr3, [r4, #16]\n \tsub.w\tr3, r8, r6\n+\tstrd\tr2, r2, [r4, #12]\n+\tmovw\tr2, #1537\t@ 0x601\n+\tstrh\tr2, [r4, #16]\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n-\tcbz\tr5, 2446 <__gridxc_alloc_MOD_realloc_s1+0x22a>\n+\tcbz\tr5, 23c6 <__gridxc_alloc_MOD_realloc_s1+0x216>\n \tumull\tr1, r2, r0, r5\n \tcmp\tr2, #0\n-\tbne.w\t274c <__gridxc_alloc_MOD_realloc_s1+0x530>\n+\tbne.w\t2670 <__gridxc_alloc_MOD_realloc_s1+0x4c0>\n \tcmp\tr3, #0\n \trsb\tsl, r6, #0\n \tit\tlt\n \tmovlt\tr0, #1\n-\tbge.w\t2734 <__gridxc_alloc_MOD_realloc_s1+0x518>\n+\tbge.w\t2658 <__gridxc_alloc_MOD_realloc_s1+0x4a8>\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t2756 <__gridxc_alloc_MOD_realloc_s1+0x53a>\n+\tbeq.w\t267a <__gridxc_alloc_MOD_realloc_s1+0x4ca>\n \tmovs\tr3, #1\n \tstr\tr3, [r4, #24]\n \tmovs\tr3, #0\n \tstrd\tr6, r8, [r4, #28]\n \tstr.w\tsl, [r4, #4]\n \tstr\tr5, [r4, #20]\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #280]\t@ 2590 <__gridxc_alloc_MOD_realloc_s1+0x374>\n-\tvldr\td19, [pc, #284]\t@ 2598 <__gridxc_alloc_MOD_realloc_s1+0x37c>\n-\tstr.w\tr9, [r7, #248]\t@ 0xf8\n-\tldr\tr0, [pc, #324]\t@ (25c8 <__gridxc_alloc_MOD_realloc_s1+0x3ac>)\n-\tmovs\tr6, #1\n-\tvstr\td17, [r7, #260]\t@ 0x104\n+\tldr\tr0, [pc, #684]\t@ (26a0 <__gridxc_alloc_MOD_realloc_s1+0x4f0>)\n+\tmovs\tr6, #0\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tmov.w\tr8, #1\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tvldr\td16, [pc, #264]\t@ 25a0 <__gridxc_alloc_MOD_realloc_s1+0x384>\n-\tstr.w\tr3, [r0, #16]!\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n \tcmp\tr1, #0\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tstr.w\tr9, [r7, #244]\t@ 0xf4\n \tit\teq\n-\tmoveq\tr3, #0\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tsl, r1\n-\tldr\tr2, [r7, #56]\t@ 0x38\n-\tmov\tr8, r3\n-\tstr.w\tr6, [r7, #292]\t@ 0x124\n+\tmoveq.w\tr9, #0\n+\tstrd\tr6, r6, [r7, #256]\t@ 0x100\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tfp, r1\n+\tldr.w\tr3, [r7, #352]\t@ 0x160\n+\tstrd\tr8, r8, [r7, #268]\t@ 0x10c\n+\tit\tne\n+\tmovne\tr9, r3\n \tmovs\tr3, #4\n-\tstr.w\tr3, [r7, #256]\t@ 0x100\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #264]\t@ 0x108\n-\tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #252]\t@ 0xfc\n+\tstr.w\tr3, [r7, #264]\t@ 0x108\n \tcmp\tr2, #0\n-\tstr.w\tr8, [sp]\n-\tmov\tfp, r2\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n+\tstr.w\tr3, [r7, #252]\t@ 0xfc\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #276]\t@ 0x114\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tr9, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #228]\t@ (25cc <__gridxc_alloc_MOD_realloc_s1+0x3b0>)\n+\tmoveq\tsl, r6\n+\tldr.w\tr3, [r7, #356]\t@ 0x164\n+\tstrd\tr8, r8, [r7, #284]\t@ 0x11c\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #260]\t@ 0x104\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstrd\tr9, sl, [sp]\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #576]\t@ (26a4 <__gridxc_alloc_MOD_realloc_s1+0x4f4>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #68\t@ 0x44\n+\tadd.w\tr0, r7, #64\t@ 0x40\n \tsubs\tr3, r3, r2\n-\tmov\tr2, sl\n-\tadd\tr3, r6\n+\tmov\tr2, fp\n+\tadd\tr3, r8\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr3, r5, r3\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tmov\tr3, fp\n-\tstrd\tr8, r9, [sp, #4]\n-\tstr\tr6, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tstrd\tr9, sl, [sp, #4]\n+\tstr.w\tr8, [sp]\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldrd\tr2, r3, [r4, #28]\n \tcmp\tr2, r3\n-\tbgt.w\t23e4 <__gridxc_alloc_MOD_realloc_s1+0x1c8>\n-\tcmp\tr5, #0\n-\tble.w\t23e4 <__gridxc_alloc_MOD_realloc_s1+0x1c8>\n-\tadd.w\tr8, r3, r6\n+\tbgt.w\t2366 <__gridxc_alloc_MOD_realloc_s1+0x1b6>\n+\tcmp\tr5, r6\n+\tble.w\t2366 <__gridxc_alloc_MOD_realloc_s1+0x1b6>\n \tldr.w\tfp, [r4, #24]\n-\tldr\tr6, [r4, #4]\n+\tadd\tr8, r3\n+\tldr\tr1, [r4, #4]\n \tsub.w\tr8, r8, r2\n \tldr.w\tr9, [r4]\n-\tmov.w\tsl, #0\n-\tmla\tr6, fp, r2, r6\n+\tmla\tsl, fp, r2, r1\n \tldr\tr0, [r4, #20]\n \tmov\tr2, r5\n \tmovs\tr1, #32\n-\tadd.w\tsl, sl, #1\n-\tmla\tr0, r0, r6, r9\n-\tadd\tr6, fp\n+\tadds\tr6, #1\n+\tmla\tr0, r0, sl, r9\n+\tadd\tsl, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tcmp\tr8, sl\n-\tbne.n\t2536 <__gridxc_alloc_MOD_realloc_s1+0x31a>\n-\tb.n\t23e4 <__gridxc_alloc_MOD_realloc_s1+0x1c8>\n-\tstr\tr3, [r7, #16]\n-\tb.n\t2296 <__gridxc_alloc_MOD_realloc_s1+0x7a>\n-\tldrd\tr0, r3, [r7, #80]\t@ 0x50\n+\tcmp\tr8, r6\n+\tbne.n\t24ae <__gridxc_alloc_MOD_realloc_s1+0x2fe>\n+\tb.n\t2366 <__gridxc_alloc_MOD_realloc_s1+0x1b6>\n+\tldrd\tr0, r3, [r7, #76]\t@ 0x4c\n \tmov\tr2, sp\n \tsubs.w\tsl, r3, r0\n-\tbmi.w\t2672 <__gridxc_alloc_MOD_realloc_s1+0x456>\n+\tbmi.n\t25a2 <__gridxc_alloc_MOD_realloc_s1+0x3f2>\n \tmla\tr3, sl, r5, r5\n \tldr\tr1, [r4, #0]\n-\tstr\tr1, [r7, #32]\n+\tstr\tr1, [r7, #40]\t@ 0x28\n \tadds\tr3, #7\n \tldr.w\tlr, [r4, #4]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tr6, sp\n \tcmp\tr6, r1\n-\tbeq.n\t25d0 <__gridxc_alloc_MOD_realloc_s1+0x3b4>\n+\tbeq.n\t2500 <__gridxc_alloc_MOD_realloc_s1+0x350>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t2580 <__gridxc_alloc_MOD_realloc_s1+0x364>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x0000036e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000036c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002ca\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000216\n- R_ARM_REL32\t.LC25\n-\t.word\t0x000001da\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d6\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001cc\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000013a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000de\n- R_ARM_REL32\t.LC25\n+\tb.n\t24f0 <__gridxc_alloc_MOD_realloc_s1+0x340>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 25e0 <__gridxc_alloc_MOD_realloc_s1+0x3c4>\n+\tcbz\tr3, 2510 <__gridxc_alloc_MOD_realloc_s1+0x360>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr6, sp, #16\n \tcmp\tr5, #0\n-\tble.n\t2672 <__gridxc_alloc_MOD_realloc_s1+0x456>\n-\tldrd\tr3, r1, [r7, #8]\n+\tble.n\t25a2 <__gridxc_alloc_MOD_realloc_s1+0x3f2>\n+\tldrd\tr3, r1, [r7, #16]\n \tmov.w\tr8, #0\n \tldr.w\tr9, [r4, #24]\n-\tstr\tr4, [r7, #0]\n+\tstrd\tr4, lr, [r7, #8]\n \tmla\tip, r0, r1, r3\n-\tldr\tr3, [r7, #16]\n-\tstr.w\tr9, [r7, #16]\n-\tstrd\tr0, r2, [r7, #4]\n+\tldr\tr3, [r7, #24]\n+\tstr.w\tr9, [r7, #24]\n+\tldr.w\tr9, [r7, #44]\t@ 0x2c\n+\tstrd\tr0, r2, [r7, #16]\n \tmul.w\tr1, r3, r1\n-\tstr\tr1, [r7, #12]\n-\tldr\tr1, [r7, #52]\t@ 0x34\n-\tldr.w\tr9, [r7, #12]\n-\tstr\tr6, [r7, #12]\n+\tstr\tr1, [r7, #4]\n+\tldr\tr1, [r7, #48]\t@ 0x30\n \tmla\tfp, r3, ip, r1\n \tmov\tr3, r6\n-\tldr\tr6, [r7, #48]\t@ 0x30\n \tmov\tr4, fp\n \tmov\tfp, r8\n-\tmov\tr8, lr\n+\tldr.w\tr8, [r7, #4]\n \tmov\tr1, r4\n \tmov\tr0, r3\n-\tmov\tr2, r6\n+\tmov\tr2, r9\n \tadd.w\tfp, fp, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tmov\tr3, r0\n \tadd\tr3, r5\n-\tadd\tr4, r9\n-\tcmp\tfp, sl\n-\tble.n\t261e <__gridxc_alloc_MOD_realloc_s1+0x402>\n-\tldrd\tr6, r9, [r7, #12]\n-\tstr.w\tr5, [r7, #356]\t@ 0x164\n-\tldrd\tr0, r2, [r7, #4]\n+\tadd\tr4, r8\n+\tcmp\tsl, fp\n+\tbge.n\t254e <__gridxc_alloc_MOD_realloc_s1+0x39e>\n+\tldrd\tr2, r9, [r7, #20]\n+\tstr.w\tr5, [r7, #348]\t@ 0x15c\n+\tldrd\tlr, r0, [r7, #12]\n \tmov.w\tfp, #0\n-\tldr\tr4, [r7, #0]\n-\tstr\tr2, [r7, #16]\n+\tldr\tr4, [r7, #8]\n+\tstr\tr2, [r7, #24]\n \tmov\tr5, r4\n-\tmla\tr8, r0, r9, r8\n-\tldr.w\tr4, [r7, #356]\t@ 0x164\n+\tmla\tr8, r0, r9, lr\n+\tldr.w\tr4, [r7, #348]\t@ 0x15c\n \tldr\tr0, [r5, #20]\n \tmov\tr1, r6\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr2, r4\n \tadd\tr6, r4\n \tmla\tr0, r0, r8, r3\n \tadd\tr8, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n-\tcmp\tsl, fp\n+\tcmp\tfp, sl\n \tadd.w\tfp, fp, #1\n-\tbne.n\t2654 <__gridxc_alloc_MOD_realloc_s1+0x438>\n-\tldr\tr2, [r7, #16]\n-\tldrd\tr3, r1, [r7, #20]\n+\tbne.n\t2584 <__gridxc_alloc_MOD_realloc_s1+0x3d4>\n+\tldr\tr2, [r7, #24]\n+\tldrd\tr3, r1, [r7, #28]\n \tmovs\tr4, #1\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tldr\tr0, [r7, #52]\t@ 0x34\n \tmov\tsp, r2\n \tsubs\tr3, r3, r1\n-\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n \tadds\tr3, #1\n-\tldr.w\tr2, [r7, #360]\t@ 0x168\n+\tldr.w\tr2, [r7, #352]\t@ 0x160\n \tcmp\tr0, #0\n \tbic.w\tr3, r3, r3, asr #31\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr.w\tr2, [r7, #360]\t@ 0x168\n-\tldr\tr2, [r7, #56]\t@ 0x38\n+\tstr.w\tr2, [r7, #352]\t@ 0x160\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r7, #364]\t@ 0x16c\n+\tldr.w\tr1, [r7, #356]\t@ 0x164\n \tcmp\tr2, #0\n \tit\teq\n \tmoveq\tr1, #0\n \tnegs\tr3, r3\n-\tstr.w\tr1, [r7, #364]\t@ 0x16c\n-\tstr\tr3, [r7, #68]\t@ 0x44\n+\tstr.w\tr1, [r7, #356]\t@ 0x164\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tstr\tr1, [sp, #8]\n-\tldr\tr1, [pc, #200]\t@ (2778 <__gridxc_alloc_MOD_realloc_s1+0x55c>)\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tldr\tr1, [pc, #200]\t@ (26a8 <__gridxc_alloc_MOD_realloc_s1+0x4f8>)\n+\tldr.w\tr3, [r7, #352]\t@ 0x160\n \tstr\tr3, [sp, #4]\n \tadd\tr1, pc\n \tmov\tr3, r2\n \tstr\tr4, [sp, #0]\n \tmov\tr2, r0\n-\tadd.w\tr0, r7, #68\t@ 0x44\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tcbz\tr3, 26d2 <__gridxc_alloc_MOD_realloc_s1+0x4b6>\n+\tadd.w\tr0, r7, #64\t@ 0x40\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tcbz\tr3, 2602 <__gridxc_alloc_MOD_realloc_s1+0x452>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #28]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tvldr\td18, [pc, #128]\t@ 2760 <__gridxc_alloc_MOD_realloc_s1+0x544>\n-\tvldr\td19, [pc, #132]\t@ 2768 <__gridxc_alloc_MOD_realloc_s1+0x54c>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [pc, #148]\t@ (277c <__gridxc_alloc_MOD_realloc_s1+0x560>)\n-\tvldr\td17, [pc, #132]\t@ 2770 <__gridxc_alloc_MOD_realloc_s1+0x554>\n+\tldr\tr0, [pc, #168]\t@ (26ac <__gridxc_alloc_MOD_realloc_s1+0x4fc>)\n+\tmovs\tr5, #0\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #40]\t@ 0x28\n+\tstrd\tr5, r5, [r7, #256]\t@ 0x100\n+\tstr.w\tr3, [r7, #244]\t@ 0xf4\n+\tldr\tr1, [r7, #52]\t@ 0x34\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #268]\t@ 0x10c\n+\tstrd\tr4, r4, [r7, #284]\t@ 0x11c\n \tmovs\tr4, #4\n-\tldrd\tr2, r1, [r7, #56]\t@ 0x38\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #256]\t@ 0x100\n+\tstr.w\tr4, [r7, #264]\t@ 0x108\n+\tstr.w\tr4, [r7, #252]\t@ 0xfc\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #276]\t@ 0x114\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #260]\t@ 0x104\n-\tstrh.w\tr4, [r7, #264]\t@ 0x108\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #292]\t@ 0x124\n+\tstrh.w\tr4, [r7, #260]\t@ 0x104\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #252]\t@ 0xfc\n-\tldr.w\tr4, [r7, #364]\t@ 0x16c\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr.w\tr4, [r7, #248]\t@ 0xf8\n+\tldr.w\tr4, [r7, #356]\t@ 0x164\n+\tldrd\tr3, r2, [r7, #56]\t@ 0x38\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #360]\t@ 0x168\n+\tldr.w\tr4, [r7, #352]\t@ 0x160\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t23f0 <__gridxc_alloc_MOD_realloc_s1+0x1d4>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t2372 <__gridxc_alloc_MOD_realloc_s1+0x1c2>\n \tmul.w\tr0, r5, r0\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbne.w\t2460 <__gridxc_alloc_MOD_realloc_s1+0x244>\n-\tb.n\t2756 <__gridxc_alloc_MOD_realloc_s1+0x53a>\n+\tbne.w\t23e0 <__gridxc_alloc_MOD_realloc_s1+0x230>\n+\tb.n\t267a <__gridxc_alloc_MOD_realloc_s1+0x4ca>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t2470 <__gridxc_alloc_MOD_realloc_s1+0x254>\n+\tb.n\t23f0 <__gridxc_alloc_MOD_realloc_s1+0x240>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t2470 <__gridxc_alloc_MOD_realloc_s1+0x254>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n+\tb.n\t23f0 <__gridxc_alloc_MOD_realloc_s1+0x240>\n+\t.word\t0x000004a6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000048e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003de\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000360\n+ R_ARM_REL32\t.LC25\n+\t.word\t0x00000330\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000032c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000322\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x000002a2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000023a\n+ R_ARM_REL32\t.LC25\n \t.word\t0x000000be\n R_ARM_REL32\t.LC25\n-\t.word\t0x0000008c\n+\t.word\t0x000000a0\n R_ARM_REL32\t.bss\n \n-00002780 <__gridxc_alloc_MOD_realloc_l3>:\n+000026b0 <__gridxc_alloc_MOD_realloc_l3>:\n __gridxc_alloc_MOD_realloc_l3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3512]\t@ 0xdb8\n-\tmov\tr8, r2\n-\tldr.w\tr2, [pc, #1088]\t@ 2bd8 <__gridxc_alloc_MOD_realloc_l3+0x458>\n+\tstr.w\tr0, [ip, #3600]\t@ 0xe10\n+\tmov\tfp, r2\n+\tldr.w\tr2, [pc, #1952]\t@ 2e64 <__gridxc_alloc_MOD_realloc_l3+0x7b4>\n \tmov\tip, r3\n-\tldr.w\tr3, [pc, #1084]\t@ 2bdc <__gridxc_alloc_MOD_realloc_l3+0x45c>\n+\tldr.w\tr3, [pc, #1948]\t@ 2e68 <__gridxc_alloc_MOD_realloc_l3+0x7b8>\n \tadd\tr2, pc\n-\tsub.w\tsp, sp, #516\t@ 0x204\n+\tsub\tsp, #460\t@ 0x1cc\n \tadd\tr7, sp, #16\n-\tmov\tlr, r1\n+\tmov\tr8, r1\n \tmov\tr6, r0\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [pc, #1072]\t@ 2be0 <__gridxc_alloc_MOD_realloc_l3+0x460>\n+\tldr.w\tr2, [pc, #1936]\t@ 2e6c <__gridxc_alloc_MOD_realloc_l3+0x7bc>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr3, [r7, #436]\t@ 0x1b4\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tadd\tr2, pc\n-\tldrd\tfp, r1, [r7, #576]\t@ 0x240\n+\tldr.w\tsl, [r7, #488]\t@ 0x1e8\n \tcmp\tr3, #0\n-\tstr\tr1, [r7, #32]\n-\tmov.w\tr1, #1\n-\tit\teq\n+\tite\tne\n+\tmovne\tr1, #1\n \tmoveq\tr1, #0\n \tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tstr\tr2, [r7, #28]\n-\tldr.w\tr2, [r7, #588]\t@ 0x24c\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tldrd\tr9, sl, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n+\tstr\tr2, [r7, #24]\n+\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n \tstr\tr2, [r7, #76]\t@ 0x4c\n-\tbeq.w\t2dae <__gridxc_alloc_MOD_realloc_l3+0x62e>\n+\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tldrd\tr9, lr, [r7, #480]\t@ 0x1e0\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\tbeq.w\t2c8e <__gridxc_alloc_MOD_realloc_l3+0x5de>\n \tmov\tr5, r0\n-\tstr\tr3, [r7, #24]\n+\tstr\tr3, [r7, #20]\n \tldr\tr3, [r0, #4]\n-\tadd.w\tr4, r7, #432\t@ 0x1b0\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tadd.w\tr4, r7, #376\t@ 0x178\n+\tstr\tr3, [r7, #12]\n \tldr\tr3, [r0, #24]\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r7, #216\t@ 0xd8\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #16]\n+\tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [r7, #32]\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tr4, {r0, r1, r2}\n \tldr\tr2, [r6, #20]\n-\tldrd\tr0, r1, [r7, #460]\t@ 0x1cc\n-\tstr\tr2, [r7, #68]\t@ 0x44\n-\tldr\tr4, [r7, #44]\t@ 0x2c\n-\tldrd\tr3, r2, [r7, #472]\t@ 0x1d8\n+\tldrd\tr0, r1, [r7, #404]\t@ 0x194\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr4, [r7, #32]\n+\tldrd\tr3, r2, [r7, #416]\t@ 0x1a0\n \tsubs\tr5, r1, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tstr\tr0, [r4, #0]\n \tsubs\tr0, r2, r3\n-\tstr\tr0, [r7, #84]\t@ 0x54\n+\tstr\tr0, [r7, #68]\t@ 0x44\n \tit\tmi\n \tmovmi\tr3, #1\n \tstr\tr3, [r4, #8]\n-\tldrd\tr0, r3, [r7, #484]\t@ 0x1e4\n+\tldrd\tr0, r3, [r7, #428]\t@ 0x1ac\n \tsubs\tr4, r3, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tcmp\tr5, #0\n-\tldr\tr5, [r7, #44]\t@ 0x2c\n+\tldr\tr5, [r7, #32]\n \tit\tlt\n \tmovlt\tr1, #0\n \tstr\tr0, [r5, #16]\n-\tldr\tr0, [r7, #84]\t@ 0x54\n+\tldr\tr0, [r7, #68]\t@ 0x44\n \tstr\tr1, [r5, #4]\n \tcmp\tr0, #0\n \tit\tlt\n \tmovlt\tr2, #0\n \tcmp\tr4, #0\n \tit\tlt\n \tmovlt\tr3, #0\n \tstr\tr2, [r5, #12]\n \tstr\tr3, [r5, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr3, [sl]\n-\tvldr\td18, [pc, #848]\t@ 2bb8 <__gridxc_alloc_MOD_realloc_l3+0x438>\n-\tvldr\td19, [pc, #852]\t@ 2bc0 <__gridxc_alloc_MOD_realloc_l3+0x440>\n-\tstr.w\tr3, [r7, #160]\t@ 0xa0\n-\tldr.w\tr2, [ip]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tldr.w\tr0, [lr]\n-\tldr.w\tr1, [r8]\n-\tadd.w\tr8, r7, #168\t@ 0xa8\n-\tldr.w\tr4, [r9]\n+\tldr.w\tr0, [r8]\n+\tadd.w\tr8, r7, #136\t@ 0x88\n+\tstr.w\tr0, [r8]\n+\tadd.w\tr0, r7, #184\t@ 0xb8\n+\tldr.w\tr1, [ip]\n+\tmov.w\tip, #4\n+\tldr.w\tr2, [lr]\n+\tldr.w\tr3, [r9]\n+\tadd.w\tr9, r7, #88\t@ 0x58\n+\tldr.w\tr4, [sl]\n \tldr.w\tr5, [fp]\n-\tstrd\tr0, r1, [r7, #120]\t@ 0x78\n-\tadd.w\tr0, r7, #384\t@ 0x180\n-\tstrd\tr2, r4, [r7, #128]\t@ 0x80\n-\tmov\tr4, r0\n-\tvldr\td17, [pc, #808]\t@ 2bc8 <__gridxc_alloc_MOD_realloc_l3+0x448>\n-\tadd.w\tr2, r7, #144\t@ 0x90\n-\tvldr\td20, [r7, #120]\t@ 0x78\n-\tvldr\td21, [r7, #128]\t@ 0x80\n-\tvstr\td16, [r7, #248]\t@ 0xf8\n-\tvstr\td16, [r7, #252]\t@ 0xfc\n-\tadd.w\tr1, r7, #420\t@ 0x1a4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #276\t@ 0x114\n-\tldr.w\tr9, [pc, #800]\t@ 2be4 <__gridxc_alloc_MOD_realloc_l3+0x464>\n-\tvstr\td16, [r7, #296]\t@ 0x128\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #308\t@ 0x134\n-\tvstr\td16, [r7, #300]\t@ 0x12c\n-\tadd\tr9, pc\n-\tstr\tr0, [r7, #20]\n-\tadd.w\tr0, r7, #240\t@ 0xf0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #324\t@ 0x144\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tadd.w\tr1, r7, #372\t@ 0x174\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #356\t@ 0x164\n-\tstr\tr5, [r2, #20]\n-\tadd.w\tr5, r7, #192\t@ 0xc0\n-\tvstr\td16, [r7, #344]\t@ 0x158\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tmovs\tr2, #3\n-\tvstr\td16, [r7, #348]\t@ 0x15c\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #404\t@ 0x194\n-\tstr.w\tr2, [r7, #332]\t@ 0x14c\n-\tstr\tr3, [r7, #40]\t@ 0x28\n-\tmvn.w\tr3, #2\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tvstr\td20, [r7, #144]\t@ 0x90\n-\tvstr\td21, [r7, #152]\t@ 0x98\n-\tstr\tr3, [r0, #4]\n-\tstr.w\tr2, [r7, #428]\t@ 0x1ac\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tstrd\tr2, r3, [r7, #336]\t@ 0x150\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tvst1.32\t{d17}, [r1]\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tstr.w\tr3, [r7, #388]\t@ 0x184\n-\tstr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tmov\tr3, r4\n-\tvstr\td16, [r7, #392]\t@ 0x188\n-\tvstr\td16, [r7, #396]\t@ 0x18c\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tvst1.32\t{d17}, [r1]\n-\tadd.w\tr1, r7, #288\t@ 0x120\n-\tstr.w\tr8, [r0]\n-\tstr.w\tr5, [r7, #288]\t@ 0x120\n+\tldr.w\tsl, [pc, #1720]\t@ 2e70 <__gridxc_alloc_MOD_realloc_l3+0x7c0>\n+\tstr.w\tr1, [r8, #8]\n+\tmvn.w\tr1, #2\n+\tstr.w\tr2, [r8, #16]\n+\tmovs\tr2, #2\n+\tstr\tr1, [r0, #4]\n+\tadd\tsl, pc\n+\tstrd\tr2, r2, [r0, #32]\n+\tstr.w\tr5, [r8, #4]\n+\tmovs\tr5, #3\n+\tstr.w\tr3, [r8, #12]\n+\tadd.w\tr3, r7, #328\t@ 0x148\n+\tstr\tr5, [r0, #44]\t@ 0x2c\n+\tstr.w\tr4, [r8, #20]\n+\tmovs\tr4, #1\n+\tstr\tr3, [r7, #28]\n+\tmovs\tr3, #0\n+\tstrd\tr4, r4, [r0, #24]\n+\tstrd\tr3, r3, [r7, #192]\t@ 0xc0\n+\tstr.w\tr3, [r7, #200]\t@ 0xc8\n+\tstrd\tr3, r3, [r7, #240]\t@ 0xf0\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstr\tr4, [r0, #40]\t@ 0x28\n+\tstr.w\tr2, [r7, #264]\t@ 0x108\n+\tstr.w\tip, [r0, #20]\n+\tstr.w\tip, [r7, #252]\t@ 0xfc\n+\tstrd\tr4, r4, [r7, #256]\t@ 0x100\n+\tstr.w\tr4, [r7, #272]\t@ 0x110\n+\tstr.w\tr9, [r0]\n+\tstr.w\tr5, [r7, #276]\t@ 0x114\n+\tstr.w\tr2, [r7, #268]\t@ 0x10c\n+\tstrd\tr4, r2, [r7, #308]\t@ 0x134\n+\tstrd\tr4, r5, [r7, #320]\t@ 0x140\n+\tstr.w\tr5, [r7, #372]\t@ 0x174\n+\tstr.w\tr2, [r7, #316]\t@ 0x13c\n+\tldr\tr5, [r7, #32]\n+\tstrd\tr4, r2, [r7, #356]\t@ 0x164\n+\tstr.w\tr2, [r7, #364]\t@ 0x16c\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr5, r1, [r7, #280]\t@ 0x118\n+\tadd.w\tr5, r7, #112\t@ 0x70\n+\tstrd\tr1, r3, [r7, #332]\t@ 0x14c\n+\tstr.w\tr1, [r7, #236]\t@ 0xec\n+\tadd.w\tr1, r7, #232\t@ 0xe8\n+\tstr.w\tip, [r7, #300]\t@ 0x12c\n+\tstr.w\tip, [r7, #348]\t@ 0x15c\n+\tstrd\tr3, r3, [r7, #288]\t@ 0x120\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tstrd\tr3, r3, [r7, #340]\t@ 0x154\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n+\tstr.w\tr4, [r7, #352]\t@ 0x160\n+\tstr.w\tr4, [r7, #368]\t@ 0x170\n+\tstr.w\tr8, [r7, #328]\t@ 0x148\n+\tstr.w\tr5, [r7, #232]\t@ 0xe8\n \tstr\tr2, [sp, #4]\n-\tldr\tr2, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n \tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #336\t@ 0x150\n+\tadd.w\tr2, r7, #280\t@ 0x118\n+\tldr\tr3, [r7, #28]\n \tbl\t3cc <__gridxc_alloc_MOD_options.constprop.2>\n-\tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 2986 <__gridxc_alloc_MOD_realloc_l3+0x206>\n-\tldr.w\tsl, [r9, #12]\n-\tcmp.w\tsl, #0\n-\tbeq.w\t2db8 <__gridxc_alloc_MOD_realloc_l3+0x638>\n-\tldr\tr3, [pc, #608]\t@ (2be8 <__gridxc_alloc_MOD_realloc_l3+0x468>)\n+\tldr.w\tr3, [sl, #8]\n+\tcbz\tr3, 289a <__gridxc_alloc_MOD_realloc_l3+0x1ea>\n+\tldr.w\tfp, [sl, #12]\n+\tcmp.w\tfp, #0\n+\tbeq.w\t2c98 <__gridxc_alloc_MOD_realloc_l3+0x5e8>\n+\tldr.w\tr3, [pc, #1496]\t@ 2e74 <__gridxc_alloc_MOD_realloc_l3+0x7c4>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t2c1a <__gridxc_alloc_MOD_realloc_l3+0x49a>\n-\tldrd\tr1, r3, [r8]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tlr, sl, [r8, #8]\n-\tsub.w\tfp, r3, r1\n-\tsub.w\tr2, sl, lr\n-\torr.w\tr0, fp, fp, asr #31\n-\tvstr\td16, [r6, #12]\n-\tadds\tr0, #1\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tmovs\tr3, #4\n-\tstr\tr1, [r7, #104]\t@ 0x68\n-\tstr.w\tlr, [r7, #116]\t@ 0x74\n-\tstr\tr0, [r7, #112]\t@ 0x70\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\torr.w\tr2, r2, r2, asr #31\n-\tvldr\td10, [r7, #104]\t@ 0x68\n-\tvldr\td11, [r7, #112]\t@ 0x70\n-\tadds\tr2, #1\n+\tbeq.w\t2b04 <__gridxc_alloc_MOD_realloc_l3+0x454>\n+\tldr.w\tr2, [r9, #4]\n+\tldr.w\tr4, [r9, #8]\n+\tldr.w\tr1, [r9]\n+\tldr.w\tr0, [r9, #12]\n+\tstr\tr1, [r7, #76]\t@ 0x4c\n+\tsubs\tr1, r2, r1\n+\tstr\tr0, [r7, #52]\t@ 0x34\n+\tsubs\tr0, r0, r4\n+\torr.w\tr3, r1, r1, asr #31\n+\tstr\tr2, [r7, #64]\t@ 0x40\n+\torr.w\tfp, r0, r0, asr #31\n+\tmovs\tr2, #0\n+\tstr\tr4, [r7, #72]\t@ 0x48\n+\tadds.w\tfp, fp, #1\n+\tadd.w\tr4, r3, #1\n+\tstrd\tr2, r2, [r6, #12]\n+\tmov.w\tr3, #4\n+\tstr\tr1, [r7, #56]\t@ 0x38\n \tstr\tr3, [r6, #8]\n \tmovw\tr3, #515\t@ 0x203\n+\tstr\tr0, [r7, #48]\t@ 0x30\n \tstrh\tr3, [r6, #16]\n-\tbeq.w\t2f6a <__gridxc_alloc_MOD_realloc_l3+0x7ea>\n-\tmvn.w\tr9, #2147483648\t@ 0x80000000\n-\tudiv\tr9, r9, r2\n-\tcmp\tr9, r0\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr9, r3\n-\tldrd\tr8, r3, [r8, #16]\n-\tmul.w\tr2, r0, r2\n-\tstrd\tsl, r2, [r7, #88]\t@ 0x58\n-\tsub.w\tsl, r3, r8\n-\tstrd\tr8, r3, [r7, #96]\t@ 0x60\n-\torr.w\tr3, sl, sl, asr #31\n-\tvldr\td8, [r7, #88]\t@ 0x58\n-\tvldr\td9, [r7, #96]\t@ 0x60\n-\tadds\tr3, #1\n-\tbeq.n\t2a2e <__gridxc_alloc_MOD_realloc_l3+0x2ae>\n-\tmvn.w\tip, #2147483648\t@ 0x80000000\n-\tmov\tr4, r9\n-\tudiv\tip, ip, r3\n-\tmul.w\tr3, r2, r3\n-\tcmp\tip, r2\n+\tbeq.w\t2e4e <__gridxc_alloc_MOD_realloc_l3+0x79e>\n+\tmov\tr1, fp\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r4\n+\tite\tge\n+\tmovge.w\tsl, #0\n+\tmovlt.w\tsl, #1\n+\tldr.w\tr3, [r9, #20]\n+\tmul.w\tfp, fp, r4\n+\tldr.w\tr2, [r9, #16]\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tsubs\tr3, r3, r2\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\torr.w\tr9, r3, r3, asr #31\n+\tadds.w\tr9, r9, #1\n+\tbeq.n\t2944 <__gridxc_alloc_MOD_realloc_l3+0x294>\n+\tmov\tr1, r9\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr9, r9, fp\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tcmp\tr0, fp\n \tit\tlt\n-\taddlt\tr4, #1\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n+\taddlt.w\tsl, sl, #1\n+\tcmp.w\tr9, #1073741824\t@ 0x40000000\n \tit\tge\n-\taddge\tr4, #1\n-\tmov\tr9, r4\n-\tldr\tr4, [r7, #80]\t@ 0x50\n-\tnegs\tr1, r1\n-\torr.w\tip, fp, r4\n-\torrs.w\tip, ip, sl\n-\tmls\tr1, r0, lr, r1\n-\tmls\tr8, r2, r8, r1\n-\tit\tpl\n-\tlslpl\tr3, r3, #2\n-\tit\tmi\n-\tmovmi\tr3, #0\n-\tcmp.w\tr9, #0\n-\tbne.w\t2f72 <__gridxc_alloc_MOD_realloc_l3+0x7f2>\n-\tcmp\tr3, #1\n+\taddge.w\tsl, sl, #1\n+\tldr\tr1, [r7, #56]\t@ 0x38\n+\tldr\tr2, [r7, #48]\t@ 0x30\n+\tldr\tr0, [r7, #72]\t@ 0x48\n+\torrs\tr1, r2\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\torrs\tr1, r3\n+\trsb\tr2, r2, #0\n+\tmls\tr2, r4, r0, r2\n+\tldr\tr0, [r7, #68]\t@ 0x44\n+\tmls\tr2, fp, r0, r2\n+\tite\tpl\n+\tmovpl.w\tr0, r9, lsl #2\n+\tmovmi\tr0, #0\n+\tstr\tr2, [r7, #56]\t@ 0x38\n+\tcmp.w\tsl, #0\n+\tbne.w\t2e56 <__gridxc_alloc_MOD_realloc_l3+0x7a6>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr3, #1\n-\tmov\tr0, r3\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r6, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t2f78 <__gridxc_alloc_MOD_realloc_l3+0x7f8>\n-\tadd.w\tr3, r6, #28\n-\tvldr\td16, [pc, #356]\t@ 2bd0 <__gridxc_alloc_MOD_realloc_l3+0x450>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r6, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r6, #20\n-\tstr.w\tr8, [r6, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tvldr\td18, [pc, #292]\t@ 2bb8 <__gridxc_alloc_MOD_realloc_l3+0x438>\n-\tvldr\td19, [pc, #296]\t@ 2bc0 <__gridxc_alloc_MOD_realloc_l3+0x440>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tvstr\td17, [r7, #396]\t@ 0x18c\n-\tvldr\td16, [pc, #296]\t@ 2bc8 <__gridxc_alloc_MOD_realloc_l3+0x448>\n-\tldr\tr0, [pc, #328]\t@ (2bec <__gridxc_alloc_MOD_realloc_l3+0x46c>)\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr1, [r7, #32]\n+\tbeq.w\t2e5c <__gridxc_alloc_MOD_realloc_l3+0x7ac>\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tmov.w\tlr, #1\n+\tstr\tr3, [r6, #28]\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r6, #32]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r6, #40]\t@ 0x28\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r6, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr3, [r6, #52]\t@ 0x34\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r6, #56]\t@ 0x38\n+\tmovs\tr3, #4\n+\tstr\tr4, [r6, #36]\t@ 0x24\n+\tstr.w\tfp, [r6, #48]\t@ 0x30\n+\tstr\tr2, [r6, #4]\n+\tstrd\tr3, lr, [r6, #20]\n+\tldr.w\tr0, [pc, #1224]\t@ 2e78 <__gridxc_alloc_MOD_realloc_l3+0x7c8>\n+\tmovs\tr4, #1\n+\tldr\tr1, [r7, #24]\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #28]\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr\tr2, [r7, #36]\t@ 0x24\n \tcmp\tr1, #0\n-\tvst1.32\t{d16}, [r3]\n-\tmov\tsl, r2\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tstr.w\tr8, [r7, #328]\t@ 0x148\n+\tmov.w\tr8, #0\n+\tstr.w\tsl, [r0, #16]!\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #348]\t@ 0x15c\n+\tstr.w\tr3, [r7, #336]\t@ 0x150\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #360]\t@ 0x168\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tr9, [r0, #16]!\n+\tmoveq.w\tsl, #0\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tcmp\tr2, #0\n-\tmov\tr8, r3\n-\tmov.w\tr3, #4\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n+\tit\teq\n+\tmoveq\tr9, r8\n+\tstrd\tr4, r4, [r7, #352]\t@ 0x160\n+\tit\tne\n+\tmovne\tr9, r3\n+\tstr.w\tr4, [r7, #368]\t@ 0x170\n+\tstrd\tr8, r8, [r7, #340]\t@ 0x154\n \tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #400]\t@ 0x190\n-\tmov.w\tr3, #3\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tstrh.w\tr3, [r7, #344]\t@ 0x158\n+\tmovs\tr3, #3\n+\tstr.w\tr3, [r7, #372]\t@ 0x174\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #388]\t@ 0x184\n-\tmov\tr9, r1\n-\tstr.w\tr8, [sp]\n-\tldr.w\tr4, [r7, #600]\t@ 0x258\n-\tit\teq\n-\tmoveq\tr4, #0\n-\tstr\tr4, [sp, #4]\n-\tldr\tr3, [r7, #20]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n+\tstr.w\tr3, [r7, #332]\t@ 0x14c\n+\tmov\tfp, r1\n+\tstrd\tsl, r9, [sp]\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #28]\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #84\t@ 0x54\n \tldrd\tr2, r3, [r6, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r6, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r4\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r4\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r6, #52]\t@ 0x34\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #200]\t@ (2bf0 <__gridxc_alloc_MOD_realloc_l3+0x470>)\n-\tadds\tr2, #1\n+\tldr.w\tr1, [pc, #1068]\t@ 2e7c <__gridxc_alloc_MOD_realloc_l3+0x7cc>\n+\tadd\tr2, r4\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r9\n+\tmov\tr2, fp\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr8, r4, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, sl\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr3, r4, [r6, #52]\t@ 0x34\n-\tldrd\tr0, ip, [r6, #40]\t@ 0x28\n-\tcmp\tr3, r4\n-\tbgt.n\t2c1a <__gridxc_alloc_MOD_realloc_l3+0x49a>\n-\tcmp\tr0, ip\n-\tbgt.n\t2c1a <__gridxc_alloc_MOD_realloc_l3+0x49a>\n-\tldrd\tr2, r1, [r6, #28]\n-\tcmp\tr2, r1\n-\tbgt.n\t2c1a <__gridxc_alloc_MOD_realloc_l3+0x49a>\n+\tstrd\tsl, r9, [sp, #4]\n+\tstr\tr4, [sp, #0]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr0, r4, [r6, #52]\t@ 0x34\n+\tldrd\tlr, ip, [r6, #40]\t@ 0x28\n+\tcmp\tr0, r4\n+\tbgt.n\t2b04 <__gridxc_alloc_MOD_realloc_l3+0x454>\n+\tcmp\tlr, ip\n+\tbgt.n\t2b04 <__gridxc_alloc_MOD_realloc_l3+0x454>\n+\tldrd\tr3, r1, [r6, #28]\n+\tcmp\tr3, r1\n+\tbgt.n\t2b04 <__gridxc_alloc_MOD_realloc_l3+0x454>\n \tadds\tr4, #1\n \tadds\tr1, #1\n-\tsubs\tr4, r4, r3\n-\tstr\tr4, [r7, #84]\t@ 0x54\n+\tsubs\tr4, r4, r0\n+\tstr\tr4, [r7, #76]\t@ 0x4c\n \tldr\tr4, [r6, #24]\n-\tsubs\tr1, r1, r2\n+\tsubs\tr1, r1, r3\n \tldr.w\tfp, [r6, #48]\t@ 0x30\n-\tadd.w\tip, ip, #1\n+\tmov\tr2, r8\n \tldr.w\tr8, [r6, #36]\t@ 0x24\n-\tmov.w\tsl, #0\n-\tldr.w\tlr, [r6, #20]\n-\tsub.w\tip, ip, r0\n-\tmul.w\tr2, r4, r2\n+\tadd.w\tip, ip, #1\n+\tsub.w\tip, ip, lr\n \tldr.w\tr9, [r6]\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tldr\tr2, [r6, #4]\n-\tstr.w\tfp, [r7, #72]\t@ 0x48\n+\tmul.w\tr3, r4, r3\n+\tstr.w\tfp, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tldr\tr3, [r6, #4]\n \tstrd\tr5, r6, [r7, #52]\t@ 0x34\n-\tmla\tr2, r3, fp, r2\n-\tmul.w\tr3, r0, r8\n+\tmla\tsl, r0, fp, r3\n+\tmul.w\tr3, lr, r8\n+\tldr.w\tlr, [r6, #20]\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tmul.w\tr0, r4, lr\n-\tmov\tr4, sl\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tmov\tr4, r2\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tmov.w\tfp, #0\n-\tadds\tr6, r2, r3\n-\tldr\tr3, [r7, #80]\t@ 0x50\n+\tadd.w\tr6, sl, r3\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tadd\tr6, r3\n \tmla\tr5, lr, r6, r9\n \tmovs\tr3, #0\n-\tb.n\t2bf4 <__gridxc_alloc_MOD_realloc_l3+0x474>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000434\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000041e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000030c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000025c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000013c\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000c4\n- R_ARM_REL32\t.LC26\n \tadds\tr3, #1\n \tstr\tr4, [r5, #0]\n \tcmp\tr1, r3\n \tadd\tr5, r0\n-\tbne.n\t2bf4 <__gridxc_alloc_MOD_realloc_l3+0x474>\n+\tbne.n\t2ae0 <__gridxc_alloc_MOD_realloc_l3+0x430>\n \tadd.w\tfp, fp, #1\n \tadd\tr6, r8\n \tcmp\tip, fp\n-\tbne.n\t2bb0 <__gridxc_alloc_MOD_realloc_l3+0x430>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n-\tadd.w\tsl, sl, #1\n-\tadd\tr2, r3\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tcmp\tr3, sl\n-\tbne.n\t2ba4 <__gridxc_alloc_MOD_realloc_l3+0x424>\n+\tbne.n\t2ada <__gridxc_alloc_MOD_realloc_l3+0x42a>\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tadds\tr2, #1\n+\tadd\tsl, r3\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tcmp\tr3, r2\n+\tbne.n\t2acc <__gridxc_alloc_MOD_realloc_l3+0x41c>\n \tldrd\tr5, r6, [r7, #52]\t@ 0x34\n-\tldr\tr3, [pc, #892]\t@ (2f98 <__gridxc_alloc_MOD_realloc_l3+0x818>)\n+\tldr\tr3, [pc, #888]\t@ (2e80 <__gridxc_alloc_MOD_realloc_l3+0x7d0>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t2d88 <__gridxc_alloc_MOD_realloc_l3+0x608>\n+\tbeq.w\t2c6c <__gridxc_alloc_MOD_realloc_l3+0x5bc>\n \tldr\tr3, [r5, #8]\n-\tstr\tr3, [r7, #48]\t@ 0x30\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr2, r3\n \tldr\tr3, [r5, #12]\n-\tstr.w\tsp, [r7, #16]\n+\tstr.w\tsp, [r7, #8]\n \tsubs\tr3, r3, r2\n \tldrd\tlr, r2, [r5]\n \tsub.w\tip, r2, lr\n \tldrd\tsl, r2, [r5, #16]\n \torr.w\tr0, ip, r3\n \tadd.w\tr9, ip, #1\n \tsub.w\tr1, r2, sl\n \tadds\tr2, r3, #1\n-\tstr\tr1, [r7, #76]\t@ 0x4c\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tmla\tr4, ip, r2, r2\n \tldr\tr2, [r6, #0]\n-\tstr\tr2, [r7, #84]\t@ 0x54\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n \tldr\tr2, [r6, #4]\n-\tstr\tr2, [r7, #12]\n+\tstr\tr2, [r7, #4]\n \torrs.w\tr2, r1, r0\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tbmi.w\t2e32 <__gridxc_alloc_MOD_realloc_l3+0x6b2>\n+\tstr\tr4, [r7, #64]\t@ 0x40\n+\tbmi.w\t2d16 <__gridxc_alloc_MOD_realloc_l3+0x666>\n \tmla\tr2, r1, r4, r4\n \tlsls\tr2, r2, #2\n \tadds\tr2, #7\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tr4, sp\n \tcmp\tr4, r1\n-\tbeq.w\t2eb8 <__gridxc_alloc_MOD_realloc_l3+0x738>\n+\tbeq.w\t2d9c <__gridxc_alloc_MOD_realloc_l3+0x6ec>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t2c7e <__gridxc_alloc_MOD_realloc_l3+0x4fe>\n-\tldrd\tr4, r2, [r7, #64]\t@ 0x40\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n-\tadd\tr4, r1\n-\tldr\tr1, [r7, #72]\t@ 0x48\n-\tadds\tr0, #1\n+\tb.n\t2b68 <__gridxc_alloc_MOD_realloc_l3+0x4b8>\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr0, [r7, #52]\t@ 0x34\n+\tldrd\tr2, r4, [r7, #56]\t@ 0x38\n+\tadd\tr0, r1\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tadds\tr4, #1\n \tadd\tr2, r1\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n-\tcmp\tr1, r0\n-\tbge.w\t2f1e <__gridxc_alloc_MOD_realloc_l3+0x79e>\n-\tldr\tr5, [r7, #32]\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n-\tldr\tr6, [r7, #28]\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tcmp\tr1, r4\n+\tbge.w\t2e02 <__gridxc_alloc_MOD_realloc_l3+0x752>\n+\tldr\tr5, [r7, #24]\n+\tadd.w\tr0, r7, #84\t@ 0x54\n+\tldr\tr6, [r7, #36]\t@ 0x24\n \tmovs\tr4, #1\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n-\tstr.w\tr3, [r7, #596]\t@ 0x254\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tldrd\tr2, r3, [r7, #472]\t@ 0x1d8\n-\tldr.w\tsp, [r7, #16]\n+\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tldrd\tr2, r3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tsp, [r7, #8]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #460]\t@ 0x1cc\n+\tldrd\tr1, r2, [r7, #404]\t@ 0x194\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #484]\t@ 0x1e4\n+\tldrd\tr1, r2, [r7, #428]\t@ 0x1ac\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #676]\t@ (2f9c <__gridxc_alloc_MOD_realloc_l3+0x81c>)\n+\tldr\tr1, [pc, #676]\t@ (2e84 <__gridxc_alloc_MOD_realloc_l3+0x7d4>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #24]\n-\tcbz\tr3, 2d28 <__gridxc_alloc_MOD_realloc_l3+0x5a8>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #20]\n+\tcbz\tr3, 2c12 <__gridxc_alloc_MOD_realloc_l3+0x562>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tvldr\td18, [pc, #588]\t@ 2f80 <__gridxc_alloc_MOD_realloc_l3+0x800>\n-\tvldr\td19, [pc, #592]\t@ 2f88 <__gridxc_alloc_MOD_realloc_l3+0x808>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tldr\tr0, [pc, #608]\t@ (2fa0 <__gridxc_alloc_MOD_realloc_l3+0x820>)\n-\tvldr\td17, [pc, #592]\t@ 2f90 <__gridxc_alloc_MOD_realloc_l3+0x810>\n+\tldr\tr0, [pc, #628]\t@ (2e88 <__gridxc_alloc_MOD_realloc_l3+0x7d8>)\n+\tmovs\tr5, #0\n+\tldr\tr3, [r7, #32]\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstrd\tr5, r5, [r7, #340]\t@ 0x154\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tldr\tr2, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #352]\t@ 0x160\n+\tstr.w\tr4, [r7, #368]\t@ 0x170\n \tmovs\tr4, #4\n-\tldrd\tr2, r1, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #392]\t@ 0x188\n+\tstr.w\tr4, [r7, #348]\t@ 0x15c\n+\tstr.w\tr4, [r7, #336]\t@ 0x150\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #360]\t@ 0x168\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #396]\t@ 0x18c\n-\tstrh.w\tr4, [r7, #400]\t@ 0x190\n+\tstrh.w\tr4, [r7, #344]\t@ 0x158\n \tmovs\tr4, #3\n-\tstr.w\tr4, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr4, [r7, #372]\t@ 0x174\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #388]\t@ 0x184\n-\tldr.w\tr4, [r7, #600]\t@ 0x258\n-\tldr\tr3, [r7, #20]\n+\tstr.w\tr4, [r7, #332]\t@ 0x14c\n+\tldr.w\tr4, [r7, #512]\t@ 0x200\n+\tldr\tr3, [r7, #28]\n+\tldr\tr1, [r7, #24]\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n+\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #536]\t@ (2fa4 <__gridxc_alloc_MOD_realloc_l3+0x824>)\n-\tldr\tr3, [pc, #540]\t@ (2fa8 <__gridxc_alloc_MOD_realloc_l3+0x828>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #540]\t@ (2e8c <__gridxc_alloc_MOD_realloc_l3+0x7dc>)\n+\tldr\tr3, [pc, #504]\t@ (2e68 <__gridxc_alloc_MOD_realloc_l3+0x7b8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2f6e <__gridxc_alloc_MOD_realloc_l3+0x7ee>\n-\tadd.w\tr7, r7, #500\t@ 0x1f4\n+\tbne.w\t2e52 <__gridxc_alloc_MOD_realloc_l3+0x7a2>\n+\tadd.w\tr7, r7, #444\t@ 0x1bc\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #216\t@ 0xd8\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tb.n\t285e <__gridxc_alloc_MOD_realloc_l3+0xde>\n-\tldrd\tr2, r3, [r7, #472]\t@ 0x1d8\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n-\tldr\tr4, [r7, #32]\n-\tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #460]\t@ 0x1cc\n-\tadds\tr3, #1\n-\tcmp\tr4, #0\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [r7, #32]\n+\tb.n\t278a <__gridxc_alloc_MOD_realloc_l3+0xda>\n+\tldr\tr3, [r7, #24]\n+\tadd.w\tr0, r7, #84\t@ 0x54\n+\tcmp\tr3, #0\n+\tldrd\tr2, r3, [r7, #416]\t@ 0x1a0\n+\tsub.w\tr3, r3, r2\n+\tldrd\tr1, r2, [r7, #404]\t@ 0x194\n+\tadd\tr3, r4\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r4\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #484]\t@ 0x1e4\n+\tldrd\tr1, r2, [r7, #428]\t@ 0x1ac\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #448]\t@ (2fac <__gridxc_alloc_MOD_realloc_l3+0x82c>)\n-\tadd.w\tr2, r2, #1\n-\tadd\tr1, pc\n+\tadd\tr2, r4\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tstr\tr4, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #28]\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n-\tcmp\tr2, #0\n+\tldr\tr4, [r7, #36]\t@ 0x24\n+\tldr.w\tr1, [r7, #512]\t@ 0x200\n+\tcmp\tr4, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #408]\t@ (2e90 <__gridxc_alloc_MOD_realloc_l3+0x7e0>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tmov\tr2, r4\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #24]\n+\tldr\tr2, [r7, #24]\n+\tadd\tr1, pc\n+\tmov\tr3, r4\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #20]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tsl, [r9, #16]\n-\tstr.w\tsl, [r7, #24]\n-\tb.n\t2986 <__gridxc_alloc_MOD_realloc_l3+0x206>\n+\tstr.w\tfp, [sl, #16]\n+\tstr.w\tfp, [r7, #20]\n+\tb.n\t289a <__gridxc_alloc_MOD_realloc_l3+0x1ea>\n \tcmp\tr1, #0\n-\tblt.w\t2ca8 <__gridxc_alloc_MOD_realloc_l3+0x528>\n-\tldr.w\tr8, [r7, #20]\n+\tblt.w\t2b92 <__gridxc_alloc_MOD_realloc_l3+0x4e2>\n+\tldr.w\tr8, [r7, #28]\n \tldr\tr2, [r6, #24]\n-\tstr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr2, [r7, #48]\t@ 0x30\n \tcmp\tr0, #0\n-\tblt.w\t2ca8 <__gridxc_alloc_MOD_realloc_l3+0x528>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tldr\tr4, [r7, #48]\t@ 0x30\n-\tstr.w\tlr, [r7, #52]\t@ 0x34\n-\tstrd\tr6, sl, [r7, #4]\n+\tblt.w\t2b92 <__gridxc_alloc_MOD_realloc_l3+0x4e2>\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n+\tldr\tr2, [r7, #12]\n+\tldr\tr4, [r7, #40]\t@ 0x28\n+\tstr.w\tlr, [r7, #44]\t@ 0x2c\n \tmla\tr2, sl, r1, r2\n \tmul.w\tr1, r0, r1\n-\tstr\tr1, [r7, #60]\t@ 0x3c\n-\tldr.w\tr1, [r7, #468]\t@ 0x1d4\n+\tstr\tr1, [r7, #52]\t@ 0x34\n+\tldr.w\tr1, [r7, #412]\t@ 0x19c\n \tmla\tr2, r4, r1, r2\n \tmul.w\tfp, r0, r1\n-\tldr\tr1, [r7, #64]\t@ 0x40\n+\tldr\tr1, [r7, #16]\n+\tstrd\tr6, sl, [r7, #12]\n \tmla\tr2, lr, r1, r2\n \tmul.w\tr5, r0, r1\n-\tldr\tr1, [r7, #24]\n+\tldr\tr1, [r7, #20]\n \tmla\tr0, r0, r2, r1\n \tmovs\tr2, #0\n \tmov\tr4, r2\n \tmov\tlr, r2\n \tmov\tr6, r0\n \tmov.w\tsl, #0\n-\tstr\tr0, [r7, #80]\t@ 0x50\n-\tstrd\tr2, r4, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr4, r0, [r7, #56]\t@ 0x38\n \tadd.w\tr4, r8, lr, lsl #2\n \tmov\tr0, r6\n \tmovs\tr1, #0\n \tldr\tr2, [r0, #0]\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tadd\tr0, r5\n \tadd.w\tr1, r1, #1\n \tstr.w\tr2, [r4], #4\n-\tbne.n\t2e98 <__gridxc_alloc_MOD_realloc_l3+0x718>\n+\tbne.n\t2d7c <__gridxc_alloc_MOD_realloc_l3+0x6cc>\n \tadd\tr6, fp\n \tadd\tlr, r9\n \tadd.w\tr2, sl, #1\n-\tcmp\tsl, r3\n-\tbeq.n\t2ece <__gridxc_alloc_MOD_realloc_l3+0x74e>\n+\tcmp\tr3, sl\n+\tbeq.n\t2db2 <__gridxc_alloc_MOD_realloc_l3+0x702>\n \tmov\tsl, r2\n-\tb.n\t2e90 <__gridxc_alloc_MOD_realloc_l3+0x710>\n+\tb.n\t2d74 <__gridxc_alloc_MOD_realloc_l3+0x6c4>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.n\t2f62 <__gridxc_alloc_MOD_realloc_l3+0x7e2>\n+\tbne.n\t2e46 <__gridxc_alloc_MOD_realloc_l3+0x796>\n \tldr\tr2, [r6, #24]\n \tadd.w\tr8, sp, #16\n-\tstr\tr2, [r7, #56]\t@ 0x38\n-\tb.n\t2e40 <__gridxc_alloc_MOD_realloc_l3+0x6c0>\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tldr\tr0, [r7, #80]\t@ 0x50\n-\tldrd\tr2, r4, [r7, #64]\t@ 0x40\n-\tadd\tr0, r1\n-\tldr\tr1, [r7, #72]\t@ 0x48\n+\tstr\tr2, [r7, #48]\t@ 0x30\n+\tb.n\t2d24 <__gridxc_alloc_MOD_realloc_l3+0x674>\n+\tldrd\tr4, r0, [r7, #56]\t@ 0x38\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tldr\tr2, [r7, #72]\t@ 0x48\n \tadds\tr4, #1\n+\tadd\tr0, r1\n+\tldr\tr1, [r7, #64]\t@ 0x40\n \tadd\tr2, r1\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n-\tcmp\tr1, r4\n-\tbge.n\t2e82 <__gridxc_alloc_MOD_realloc_l3+0x702>\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tldr.w\tlr, [r7, #52]\t@ 0x34\n-\tldrd\tr6, sl, [r7, #4]\n-\tldr\tr0, [r7, #12]\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tcmp\tr4, r1\n+\tble.n\t2d66 <__gridxc_alloc_MOD_realloc_l3+0x6b6>\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr.w\tlr, [r7, #44]\t@ 0x2c\n+\tldrd\tr6, sl, [r7, #12]\n+\tldr\tr0, [r7, #4]\n \tmul.w\tr2, lr, r1\n-\tstr\tr2, [r7, #52]\t@ 0x34\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n \tldr\tr2, [r6, #48]\t@ 0x30\n \tldr.w\tfp, [r6, #36]\t@ 0x24\n-\tstr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr2, [r7, #48]\t@ 0x30\n \tmla\tr2, sl, r2, r0\n \tldr.w\tsl, [r6, #20]\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tmov\tr4, r2\n-\tstr.w\tsl, [r7, #80]\t@ 0x50\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tstr.w\tsl, [r7, #72]\t@ 0x48\n \tmul.w\tlr, r1, sl\n \tmovs\tr1, #0\n \tmul.w\tr0, r0, fp\n+\tmov\tr4, r1\n+\tstr\tr0, [r7, #40]\t@ 0x28\n+\tmov\tr0, r2\n \tmov\tr2, r1\n-\tstr\tr0, [r7, #48]\t@ 0x30\n-\tmov\tr0, r1\n-\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr1, [r7, #40]\t@ 0x28\n \tmov\tr6, r2\n \tmov.w\tsl, #0\n-\tstrd\tr4, r2, [r7, #64]\t@ 0x40\n-\tadds\tr5, r4, r1\n-\tldr\tr1, [r7, #52]\t@ 0x34\n-\tstr\tr0, [r7, #60]\t@ 0x3c\n+\tstrd\tr2, r4, [r7, #56]\t@ 0x38\n+\tadds\tr5, r0, r1\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n+\tstr\tr0, [r7, #52]\t@ 0x34\n \tadd\tr5, r1\n-\tldrd\tr1, r2, [r7, #80]\t@ 0x50\n+\tldrd\tr1, r2, [r7, #72]\t@ 0x48\n \tadd.w\tr4, r8, r6, lsl #2\n \tmla\tr0, r1, r5, r2\n \tmovs\tr1, #0\n \tldr.w\tr2, [r4], #4\n \tcmp\tr1, ip\n \tstr\tr2, [r0, #0]\n \tadd.w\tr1, r1, #1\n \tadd\tr0, lr\n-\tbne.n\t2f40 <__gridxc_alloc_MOD_realloc_l3+0x7c0>\n+\tbne.n\t2e24 <__gridxc_alloc_MOD_realloc_l3+0x774>\n \tadd\tr5, fp\n \tadd\tr6, r9\n \tadd.w\tr2, sl, #1\n-\tcmp\tsl, r3\n-\tbeq.w\t2c90 <__gridxc_alloc_MOD_realloc_l3+0x510>\n+\tcmp\tr3, sl\n+\tbeq.w\t2b7a <__gridxc_alloc_MOD_realloc_l3+0x4ca>\n \tmov\tsl, r2\n-\tb.n\t2f32 <__gridxc_alloc_MOD_realloc_l3+0x7b2>\n+\tb.n\t2e16 <__gridxc_alloc_MOD_realloc_l3+0x766>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n-\tb.n\t2ec4 <__gridxc_alloc_MOD_realloc_l3+0x744>\n-\tmov\tr9, r2\n-\tb.n\t29ec <__gridxc_alloc_MOD_realloc_l3+0x26c>\n+\tb.n\t2da8 <__gridxc_alloc_MOD_realloc_l3+0x6f8>\n+\tmov\tsl, fp\n+\tb.n\t2904 <__gridxc_alloc_MOD_realloc_l3+0x254>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovw\tr9, #5014\t@ 0x1396\n-\tb.n\t2a86 <__gridxc_alloc_MOD_realloc_l3+0x306>\n-\tmovw\tr9, #5020\t@ 0x139c\n-\tb.n\t2a86 <__gridxc_alloc_MOD_realloc_l3+0x306>\n+\tmovw\tsl, #5014\t@ 0x1396\n+\tb.n\t29ae <__gridxc_alloc_MOD_realloc_l3+0x2fe>\n+\tmovw\tsl, #5020\t@ 0x139c\n+\tb.n\t29ae <__gridxc_alloc_MOD_realloc_l3+0x2fe>\n \tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000378\n+\t.word\t0x00000794\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000780\n R_ARM_REL32\t.bss\n-\t.word\t0x000002a0\n+\t.word\t0x000006a2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005d2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004be\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000424\n+ R_ARM_REL32\t.LC26\n+\t.word\t0x00000376\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000029e\n R_ARM_REL32\t.LC26\n-\t.word\t0x0000025a\n+\t.word\t0x0000026c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000214\n+\t.word\t0x00000218\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000001ba\n+\t.word\t0x0000018e\n R_ARM_REL32\t.LC26\n \n-00002fb0 <__gridxc_alloc_MOD_realloc_l2>:\n+00002e94 <__gridxc_alloc_MOD_realloc_l2>:\n __gridxc_alloc_MOD_realloc_l2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3640]\t@ 0xe38\n-\tsub\tsp, #404\t@ 0x194\n+\tstr.w\tr0, [ip, #3704]\t@ 0xe78\n+\tsub\tsp, #356\t@ 0x164\n \tadd\tr7, sp, #16\n \tmov\tfp, r0\n-\tldr\tr4, [pc, #1004]\t@ (33b8 <__gridxc_alloc_MOD_realloc_l2+0x408>)\n-\tmov\tr9, r3\n-\tldr\tr6, [pc, #1004]\t@ (33bc <__gridxc_alloc_MOD_realloc_l2+0x40c>)\n-\tldrd\tr5, r0, [r7, #440]\t@ 0x1b8\n-\tstr\tr0, [r7, #68]\t@ 0x44\n-\tldr\tr0, [pc, #1000]\t@ (33c0 <__gridxc_alloc_MOD_realloc_l2+0x410>)\n-\tadd\tr4, pc\n-\tadd\tr6, pc\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tldr\tr0, [r4, r0]\n+\tldr.w\tr5, [pc, #1560]\t@ 34c4 <__gridxc_alloc_MOD_realloc_l2+0x630>\n+\tldrd\tr4, r0, [r7, #376]\t@ 0x178\n+\tstr\tr0, [r7, #56]\t@ 0x38\n+\tldr.w\tr0, [pc, #1552]\t@ 34c8 <__gridxc_alloc_MOD_realloc_l2+0x634>\n+\tadd\tr5, pc\n+\tldr.w\tr6, [r7, #384]\t@ 0x180\n+\tldr.w\tip, [r7, #392]\t@ 0x188\n+\tldr\tr0, [r5, r0]\n+\tldr.w\tr5, [pc, #1540]\t@ 34cc <__gridxc_alloc_MOD_realloc_l2+0x638>\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #380]\t@ 0x17c\n+\tstr.w\tr0, [r7, #332]\t@ 0x14c\n \tmov.w\tr0, #0\n \tldr.w\tr0, [fp]\n-\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd\tr5, pc\n+\tstr\tr6, [r7, #60]\t@ 0x3c\n \tcmp\tr0, #0\n-\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tite\tne\n+\tmovne\tr6, #1\n+\tmoveq\tr6, #0\n+\tstr\tr6, [r5, #0]\n \tit\teq\n \tmoveq\tsl, r0\n-\tmov.w\tr3, #1\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [r6, #0]\n-\tldr.w\tr6, [r7, #456]\t@ 0x1c8\n-\tbeq.n\t306e <__gridxc_alloc_MOD_realloc_l2+0xbe>\n-\tldr.w\tr4, [fp, #44]\t@ 0x2c\n-\tstr\tr4, [r7, #52]\t@ 0x34\n-\tldr.w\tr4, [fp, #28]\n-\tstr\tr4, [r7, #48]\t@ 0x30\n-\tldr.w\tr4, [fp, #32]\n-\tstr\tr4, [r7, #44]\t@ 0x2c\n-\tldr.w\tr4, [fp, #36]\t@ 0x24\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tldr.w\tr4, [fp, #4]\n-\tstr\tr4, [r7, #16]\n-\tldr.w\tr4, [fp, #24]\n-\tldr.w\tr3, [fp, #40]\t@ 0x28\n-\tstr\tr4, [r7, #20]\n-\tldr\tr4, [r7, #52]\t@ 0x34\n-\tstr\tr3, [r7, #32]\n-\tsub.w\tlr, r4, r3\n+\tldr.w\tr5, [r7, #388]\t@ 0x184\n+\tstr\tr5, [r7, #68]\t@ 0x44\n+\tbeq.n\t2f4c <__gridxc_alloc_MOD_realloc_l2+0xb8>\n+\tldr.w\tr6, [fp, #44]\t@ 0x2c\n+\tstr\tr6, [r7, #44]\t@ 0x2c\n+\tldr.w\tr6, [fp, #28]\n+\tstr\tr6, [r7, #40]\t@ 0x28\n+\tldr.w\tr6, [fp, #32]\n+\tstr\tr6, [r7, #36]\t@ 0x24\n+\tldr.w\tr6, [fp, #36]\t@ 0x24\n+\tstr\tr6, [r7, #12]\n+\tldr.w\tr6, [fp, #4]\n+\tstr\tr6, [r7, #4]\n+\tldr.w\tr6, [fp, #24]\n+\tldr.w\tr5, [fp, #40]\t@ 0x28\n+\tstr\tr6, [r7, #8]\n+\tldr\tr6, [r7, #44]\t@ 0x2c\n+\tstr\tr5, [r7, #32]\n+\tsub.w\tlr, r6, r5\n \tldr.w\tsl, [fp, #20]\n-\tldrd\tr3, r4, [r7, #44]\t@ 0x2c\n-\tcmp\tr3, r4\n-\tblt.w\t35e6 <__gridxc_alloc_MOD_realloc_l2+0x636>\n+\tldrd\tr5, r6, [r7, #36]\t@ 0x24\n+\tcmp\tr5, r6\n+\tblt.w\t346c <__gridxc_alloc_MOD_realloc_l2+0x5d8>\n \tcmp.w\tlr, #0\n-\tstr.w\tr4, [r7, #168]\t@ 0xa8\n-\tldr.w\tlr, [r7, #44]\t@ 0x2c\n-\tblt.w\t3604 <__gridxc_alloc_MOD_realloc_l2+0x654>\n-\tldr.w\tip, [r7, #32]\n-\tldr.w\tr8, [r7, #52]\t@ 0x34\n-\tstrd\tlr, ip, [r7, #172]\t@ 0xac\n-\tstr.w\tr8, [r7, #180]\t@ 0xb4\n-\tstr\tr0, [r7, #56]\t@ 0x38\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr3, [r5, #0]\n-\tldr.w\tr0, [r9]\n-\tadd.w\tr5, r7, #364\t@ 0x16c\n-\tvldr\td18, [pc, #792]\t@ 3398 <__gridxc_alloc_MOD_realloc_l2+0x3e8>\n-\tvldr\td19, [pc, #796]\t@ 33a0 <__gridxc_alloc_MOD_realloc_l2+0x3f0>\n-\tstr\tr5, [r7, #36]\t@ 0x24\n-\tldr\tr1, [r1, #0]\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr0, r3, [r7, #104]\t@ 0x68\n-\tadd.w\tr3, r7, #204\t@ 0xcc\n-\tstrd\tr1, r2, [r7, #96]\t@ 0x60\n-\tadd.w\tr0, r7, #348\t@ 0x15c\n-\tvldr\td17, [pc, #780]\t@ 33a8 <__gridxc_alloc_MOD_realloc_l2+0x3f8>\n-\tmovs\tr2, #2\n-\tvldr\td20, [r7, #96]\t@ 0x60\n-\tvldr\td21, [r7, #104]\t@ 0x68\n-\tvstr\td16, [r7, #192]\t@ 0xc0\n-\tvstr\td16, [r7, #196]\t@ 0xc4\n-\tadd.w\tr1, r7, #136\t@ 0x88\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #220\t@ 0xdc\n-\tvstr\td16, [r7, #240]\t@ 0xf0\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #252\t@ 0xfc\n-\tvstr\td16, [r7, #244]\t@ 0xf4\n-\tvstr\td16, [r7, #288]\t@ 0x120\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tvstr\td16, [r7, #292]\t@ 0x124\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #300\t@ 0x12c\n-\tstr\tr0, [r7, #40]\t@ 0x28\n-\tstr.w\tr2, [r7, #228]\t@ 0xe4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #316\t@ 0x13c\n-\tstr.w\tr2, [r7, #276]\t@ 0x114\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #328\t@ 0x148\n-\tmov\tr4, r3\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tstr.w\tr2, [r7, #324]\t@ 0x144\n-\tmvn.w\tr3, #2\n-\tvstr\td16, [r7, #336]\t@ 0x150\n-\tstr.w\tr3, [r7, #188]\t@ 0xbc\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tvstr\td20, [r7, #120]\t@ 0x78\n-\tvstr\td21, [r7, #128]\t@ 0x80\n-\tstr.w\tr1, [r7, #184]\t@ 0xb8\n-\tadd.w\tr1, r7, #152\t@ 0x98\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n-\tadd.w\tr2, r7, #280\t@ 0x118\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstr.w\tr1, [r7, #232]\t@ 0xe8\n-\tadd.w\tr1, r7, #168\t@ 0xa8\n-\tvst1.32\t{d18-d19}, [r0]\n-\tadd.w\tr0, r7, #184\t@ 0xb8\n-\tvst1.32\t{d17}, [r5]\n-\tadd.w\tr5, r7, #120\t@ 0x78\n-\tstr\tr1, [r7, #28]\n-\tstr.w\tr1, [r7, #280]\t@ 0x118\n-\tadd.w\tr1, r7, #232\t@ 0xe8\n-\tstr.w\tr5, [r7, #328]\t@ 0x148\n-\tstr\tr6, [sp, #4]\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr6, [r7, #124]\t@ 0x7c\n+\tldr.w\tlr, [r7, #36]\t@ 0x24\n+\tblt.w\t3482 <__gridxc_alloc_MOD_realloc_l2+0x5ee>\n+\tldr\tr5, [r7, #32]\n+\tldr.w\tr8, [r7, #44]\t@ 0x2c\n+\tstrd\tlr, r5, [r7, #128]\t@ 0x80\n+\tstr.w\tr8, [r7, #136]\t@ 0x88\n+\tstr\tr0, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r3, #0]\n+\tmovs\tr5, #1\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tmovs\tr0, #4\n+\tldr\tr3, [r1, #0]\n+\tadd.w\tlr, r7, #92\t@ 0x5c\n+\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tmvn.w\tr1, #2\n+\tldr\tr3, [r4, #0]\n+\tadd.w\tr9, r7, #108\t@ 0x6c\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tadd.w\tr4, r7, #76\t@ 0x4c\n+\tldr\tr3, [r2, #0]\n+\tmovs\tr2, #0\n+\tstr\tr3, [r7, #112]\t@ 0x70\n+\tadd.w\tr3, r7, #284\t@ 0x11c\n+\tmov\tr6, r3\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tstrd\tr2, r2, [r7, #148]\t@ 0x94\n+\tmovs\tr3, #2\n+\tstr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstrd\tr2, r2, [r7, #196]\t@ 0xc4\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tstr.w\tr3, [r7, #172]\t@ 0xac\n+\tstr.w\tr3, [r7, #184]\t@ 0xb8\n+\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tstr.w\tr3, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #160]\t@ 0xa0\n+\tstr.w\tr0, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #144]\t@ 0x90\n+\tstr.w\tr1, [r7, #192]\t@ 0xc0\n+\tstrd\tr5, r5, [r7, #164]\t@ 0xa4\n+\tstr.w\tr5, [r7, #180]\t@ 0xb4\n+\tstrd\tr5, r5, [r7, #212]\t@ 0xd4\n+\tstr.w\tr5, [r7, #228]\t@ 0xe4\n+\tstr.w\tr4, [r7, #140]\t@ 0x8c\n+\tstr.w\tlr, [r7, #188]\t@ 0xbc\n+\tstrd\tr1, r2, [r7, #288]\t@ 0x120\n+\tstr.w\tr0, [r7, #256]\t@ 0x100\n+\tstr.w\tr0, [r7, #304]\t@ 0x130\n+\tadd.w\tr0, r7, #140\t@ 0x8c\n+\tstrd\tr2, r2, [r7, #244]\t@ 0xf4\n+\tstr.w\tr2, [r7, #252]\t@ 0xfc\n+\tstrd\tr5, r3, [r7, #264]\t@ 0x108\n+\tstrd\tr5, r3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr1, [r7, #240]\t@ 0xf0\n+\tadd.w\tr1, r7, #188\t@ 0xbc\n+\tstrd\tr2, r2, [r7, #296]\t@ 0x128\n+\tadd.w\tr2, r7, #124\t@ 0x7c\n+\tstrd\tr5, r3, [r7, #312]\t@ 0x138\n+\tstrd\tr5, r3, [r7, #324]\t@ 0x144\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tstr\tr2, [r7, #28]\n+\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tadd.w\tr2, r7, #236\t@ 0xec\n+\tstr.w\tr5, [r7, #260]\t@ 0x104\n+\tstr.w\tr5, [r7, #308]\t@ 0x134\n+\tstr.w\tr9, [r7, #284]\t@ 0x11c\n+\tstr.w\tip, [sp, #4]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r4\n-\tldr\tr4, [pc, #600]\t@ (33c4 <__gridxc_alloc_MOD_realloc_l2+0x414>)\n-\tbl\t1fc <__gridxc_alloc_MOD_options.constprop.1>\n-\tadd\tr4, pc\n-\tldr\tr3, [r4, #8]\n-\tcbz\tr3, 317c <__gridxc_alloc_MOD_realloc_l2+0x1cc>\n-\tldr\tr6, [r4, #12]\n-\tcmp\tr6, #0\n-\tbeq.w\t3580 <__gridxc_alloc_MOD_realloc_l2+0x5d0>\n-\tldr\tr3, [pc, #584]\t@ (33c8 <__gridxc_alloc_MOD_realloc_l2+0x418>)\n+\tmov\tr3, r6\n+\tldr.w\tr6, [pc, #1184]\t@ 34d0 <__gridxc_alloc_MOD_realloc_l2+0x63c>\n+\tbl\t1ec <__gridxc_alloc_MOD_options.constprop.1>\n+\tadd\tr6, pc\n+\tldr\tr3, [r6, #8]\n+\tcbz\tr3, 3046 <__gridxc_alloc_MOD_realloc_l2+0x1b2>\n+\tldr.w\tr8, [r6, #12]\n+\tcmp.w\tr8, #0\n+\tbeq.w\t3400 <__gridxc_alloc_MOD_realloc_l2+0x56c>\n+\tldr.w\tr3, [pc, #1164]\t@ 34d4 <__gridxc_alloc_MOD_realloc_l2+0x640>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t332e <__gridxc_alloc_MOD_realloc_l2+0x37e>\n-\tldrd\tr4, r0, [r7, #136]\t@ 0x88\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r6, [r7, #144]\t@ 0x90\n-\tsubs\tr2, r0, r4\n-\torr.w\tr1, r2, r2, asr #31\n-\tvstr\td16, [fp, #12]\n-\tadds\tr1, #1\n-\tstr\tr4, [r7, #80]\t@ 0x50\n-\tnegs\tr4, r4\n-\tstrd\tr1, r3, [r7, #88]\t@ 0x58\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tmovs\tr0, #4\n-\tvldr\td8, [r7, #80]\t@ 0x50\n-\tvldr\td9, [r7, #88]\t@ 0x58\n-\tmls\tr4, r1, r3, r4\n-\tsubs\tr3, r6, r3\n-\tstr.w\tr0, [fp, #8]\n-\torrs\tr2, r3\n-\tmovw\tr0, #514\t@ 0x202\n-\torr.w\tr3, r3, r3, asr #31\n-\tstrh.w\tr0, [fp, #16]\n-\tlsrs\tr2, r2, #31\n-\tadds\tr3, #1\n-\tbeq.w\t362a <__gridxc_alloc_MOD_realloc_l2+0x67a>\n-\tmvn.w\tip, #2147483648\t@ 0x80000000\n-\tudiv\tip, ip, r3\n-\tmul.w\tr3, r1, r3\n+\tbeq.w\t3200 <__gridxc_alloc_MOD_realloc_l2+0x36c>\n+\tldr\tr3, [r4, #0]\n+\tmovs\tr5, #0\n+\tldr\tr1, [r4, #4]\n+\tldrd\tr2, r4, [r4, #8]\n+\tsubs\tr6, r1, r3\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tnegs\tr0, r3\n+\tstr\tr3, [r7, #24]\n+\torr.w\tr8, r6, r6, asr #31\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tsubs\tr2, r4, r2\n+\torrs\tr6, r2\n+\tstr\tr1, [r7, #64]\t@ 0x40\n+\torr.w\tr2, r2, r2, asr #31\n+\tstrd\tr5, r5, [fp, #12]\n+\tlsrs\tr6, r6, #31\n+\tmla\tr1, r8, r3, r3\n+\tadd.w\tr8, r8, #1\n+\tsubs\tr3, r0, r1\n+\tmovs\tr1, #4\n+\tstr\tr3, [r7, #20]\n+\tstr.w\tr1, [fp, #8]\n+\tmovw\tr1, #514\t@ 0x202\n+\tstrh.w\tr1, [fp, #16]\n+\tadds\tr1, r2, #1\n+\tbeq.w\t34a6 <__gridxc_alloc_MOD_realloc_l2+0x612>\n+\tmul.w\tr3, r1, r8\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr3, [r7, #16]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #16]\n \tcmp.w\tr3, #1073741824\t@ 0x40000000\n+\tite\tlt\n+\tmovlt\tr2, #0\n+\tmovge\tr2, #1\n+\tcmp\tr0, r8\n \tit\tlt\n-\tmovlt\tr0, #0\n-\tit\tge\n-\tmovge\tr0, #1\n-\tcmp\tip, r1\n-\tit\tlt\n-\taddlt\tr0, #1\n+\taddlt\tr2, #1\n+\tlsls\tr0, r3, #2\n+\tcbz\tr6, 30c2 <__gridxc_alloc_MOD_realloc_l2+0x22e>\n+\tmov\tr0, r5\n \tcmp\tr2, #0\n-\tbne.w\t3600 <__gridxc_alloc_MOD_realloc_l2+0x650>\n-\tlsls\tr2, r3, #2\n-\tcmp\tr0, #0\n-\tbne.w\t3638 <__gridxc_alloc_MOD_realloc_l2+0x688>\n-\tcmp\tr2, #1\n+\tbne.w\t34b6 <__gridxc_alloc_MOD_realloc_l2+0x622>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr2, #1\n-\tmov\tr0, r2\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr.w\tr0, [fp]\n \tcmp\tr0, #0\n-\tbeq.w\t363e <__gridxc_alloc_MOD_realloc_l2+0x68e>\n-\tadd.w\tr3, fp, #28\n-\tstr.w\tr6, [fp, #44]\t@ 0x2c\n-\tvldr\td16, [pc, #400]\t@ 33b0 <__gridxc_alloc_MOD_realloc_l2+0x400>\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, fp, #20\n-\tstr.w\tr4, [fp, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t34bc <__gridxc_alloc_MOD_realloc_l2+0x628>\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr2, #1\n+\tstr.w\tr3, [fp, #28]\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr.w\tr3, [fp, #32]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tstrd\tr3, r4, [fp, #40]\t@ 0x28\n+\tldr\tr3, [r7, #20]\n+\tstr.w\tr3, [fp, #4]\n+\tmovs\tr3, #4\n+\tstrd\tr3, r2, [fp, #20]\n \tmovs\tr3, #0\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #348]\t@ 3398 <__gridxc_alloc_MOD_realloc_l2+0x3e8>\n-\tvldr\td19, [pc, #352]\t@ 33a0 <__gridxc_alloc_MOD_realloc_l2+0x3f0>\n-\tstr.w\tr5, [r7, #328]\t@ 0x148\n-\tldr\tr0, [pc, #388]\t@ (33cc <__gridxc_alloc_MOD_realloc_l2+0x41c>)\n-\tvstr\td17, [r7, #340]\t@ 0x154\n-\tvst1.32\t{d18-d19}, [r2]\n+\tstr.w\tr8, [fp, #36]\t@ 0x24\n+\tldr\tr0, [pc, #980]\t@ (34d8 <__gridxc_alloc_MOD_realloc_l2+0x644>)\n+\tmovs\tr5, #0\n+\tldr\tr1, [r7, #56]\t@ 0x38\n+\tmovs\tr4, #1\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tvldr\td16, [pc, #336]\t@ 33a8 <__gridxc_alloc_MOD_realloc_l2+0x3f8>\n-\tldr\tr6, [r7, #68]\t@ 0x44\n-\tldr.w\tr4, [r7, #460]\t@ 0x1cc\n-\tvst1.32\t{d16}, [r2]\n-\tcmp\tr6, #0\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tcmp\tr1, #0\n+\tstr.w\tr9, [r7, #284]\t@ 0x11c\n \tit\teq\n-\tmoveq\tr4, #0\n+\tmoveq\tr6, #0\n+\tstrd\tr5, r5, [r7, #296]\t@ 0x128\n \tstr.w\tr3, [r0, #16]!\n-\tmovs\tr3, #4\n-\tstr.w\tr3, [r7, #336]\t@ 0x150\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #344]\t@ 0x158\n+\tmov\tr9, r1\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n+\tstrd\tr4, r4, [r7, #308]\t@ 0x134\n+\tit\tne\n+\tmovne\tr6, r3\n \tmovs\tr3, #2\n-\tstr.w\tr3, [r7, #372]\t@ 0x174\n-\tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n+\tstr.w\tr3, [r7, #316]\t@ 0x13c\n \tcmp\tr2, #0\n-\tstr\tr4, [sp, #0]\n-\tmov\tr1, r6\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr5, #0\n-\tstr\tr5, [sp, #4]\n-\tmov\tr8, r2\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #116\t@ 0x74\n+\tmoveq\tr8, r5\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r7, #400]\t@ 0x190\n+\tstr.w\tr4, [r7, #324]\t@ 0x144\n+\tit\tne\n+\tmovne\tr8, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #300]\t@ 0x12c\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tstrd\tr6, r8, [sp]\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #72\t@ 0x48\n \tldrd\tr2, r3, [fp, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [fp, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r4\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n-\tldr\tr1, [pc, #276]\t@ (33d0 <__gridxc_alloc_MOD_realloc_l2+0x420>)\n+\tadd\tr2, r4\n+\tldr\tr1, [pc, #844]\t@ (34dc <__gridxc_alloc_MOD_realloc_l2+0x648>)\n \tbic.w\tr2, r2, r2, asr #31\n \tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r6\n+\tmov\tr2, r9\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr4, r5, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r8\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr0, r3, [fp, #40]\t@ 0x28\n-\tldrd\tr5, r1, [fp, #28]\n-\tcmp\tr0, r3\n-\tbgt.n\t332e <__gridxc_alloc_MOD_realloc_l2+0x37e>\n+\tstrd\tr6, r8, [sp, #4]\n+\tstr\tr4, [sp, #0]\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr2, r3, [fp, #40]\t@ 0x28\n+\tldrd\tr6, r1, [fp, #28]\n+\tcmp\tr2, r3\n+\tbgt.n\t3200 <__gridxc_alloc_MOD_realloc_l2+0x36c>\n \tldr.w\tlr, [fp, #36]\t@ 0x24\n-\tcmp\tr5, r1\n-\tbgt.n\t332e <__gridxc_alloc_MOD_realloc_l2+0x37e>\n-\tadds\tr3, #1\n-\tldr.w\tr8, [fp, #20]\n-\tsub.w\tip, r3, r0\n+\tcmp\tr6, r1\n+\tbgt.n\t3200 <__gridxc_alloc_MOD_realloc_l2+0x36c>\n+\tadd.w\tip, r3, r4\n \tldr.w\tr3, [fp, #4]\n-\tadds\tr1, #1\n-\tmovs\tr6, #0\n-\tsubs\tr1, r1, r5\n-\tldr.w\tr9, [fp]\n-\tmov\tr4, r6\n-\tmla\tr3, r0, lr, r3\n \tldr.w\tr0, [fp, #24]\n-\tmla\tr5, r0, r5, r3\n+\tadd\tr1, r4\n+\tldr.w\tr8, [fp, #20]\n+\tsubs\tr1, r1, r6\n+\tldr.w\tr9, [fp]\n+\tsub.w\tip, ip, r2\n+\tmla\tr3, r2, lr, r3\n+\tmov\tr4, r5\n+\tmla\tr6, r0, r6, r3\n \tmul.w\tr0, r0, r8\n-\tmla\tr2, r8, r5, r9\n+\tmla\tr2, r8, r6, r9\n \tmovs\tr3, #0\n \tadds\tr3, #1\n \tstr\tr4, [r2, #0]\n \tcmp\tr1, r3\n \tadd\tr2, r0\n-\tbne.n\t331c <__gridxc_alloc_MOD_realloc_l2+0x36c>\n-\tadds\tr6, #1\n-\tadd\tr5, lr\n-\tcmp\tip, r6\n-\tbne.n\t3316 <__gridxc_alloc_MOD_realloc_l2+0x366>\n-\tldr\tr3, [pc, #164]\t@ (33d4 <__gridxc_alloc_MOD_realloc_l2+0x424>)\n+\tbne.n\t31ee <__gridxc_alloc_MOD_realloc_l2+0x35a>\n+\tadds\tr5, #1\n+\tadd\tr6, lr\n+\tcmp\tr5, ip\n+\tbne.n\t31e8 <__gridxc_alloc_MOD_realloc_l2+0x354>\n+\tldr\tr3, [pc, #732]\t@ (34e0 <__gridxc_alloc_MOD_realloc_l2+0x64c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t355c <__gridxc_alloc_MOD_realloc_l2+0x5ac>\n-\tldrd\tr3, r2, [r7, #156]\t@ 0x9c\n+\tbeq.w\t33e0 <__gridxc_alloc_MOD_realloc_l2+0x54c>\n+\tldrd\tr3, r2, [r7, #96]\t@ 0x60\n \tstr.w\tsp, [r7, #24]\n-\tldr.w\tr0, [r7, #152]\t@ 0x98\n+\tldr\tr0, [r7, #92]\t@ 0x5c\n \tsub.w\tip, r3, r0\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tldr\tr3, [r7, #104]\t@ 0x68\n \tsub.w\tr8, r3, r2\n \tldr.w\tr3, [fp]\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #68]\t@ 0x44\n \torrs.w\tr1, ip, r8\n \tldr.w\tr3, [fp, #4]\n-\tstr\tr3, [r7, #12]\n+\tstr\tr3, [r7, #20]\n \tadd.w\tr3, ip, #1\n-\tbmi.n\t33d8 <__gridxc_alloc_MOD_realloc_l2+0x428>\n+\tbmi.n\t3260 <__gridxc_alloc_MOD_realloc_l2+0x3cc>\n \tmla\tr1, r8, r3, r3\n \tlsls\tr1, r1, #2\n \tadds\tr1, #7\n \tbic.w\tr4, r1, #4080\t@ 0xff0\n \tbic.w\tr1, r1, #7\n \tbic.w\tr4, r4, #15\n \tsub.w\tr4, sp, r4\n \tmov\tr5, sp\n \tcmp\tr5, r4\n-\tbeq.w\t360e <__gridxc_alloc_MOD_realloc_l2+0x65e>\n+\tbeq.w\t348a <__gridxc_alloc_MOD_realloc_l2+0x5f6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t3380 <__gridxc_alloc_MOD_realloc_l2+0x3d0>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x000003dc\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003de\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000252\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000246\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000178\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000010c\n- R_ARM_REL32\t.LC26\n-\t.word\t0x000000a0\n- R_ARM_REL32\t.bss\n+\tb.n\t324e <__gridxc_alloc_MOD_realloc_l2+0x3ba>\n \tcmp.w\tr8, #0\n-\tblt.n\t348c <__gridxc_alloc_MOD_realloc_l2+0x4dc>\n+\tblt.n\t3314 <__gridxc_alloc_MOD_realloc_l2+0x480>\n \tldr.w\tr1, [fp, #24]\n-\tldr.w\tr9, [r7, #60]\t@ 0x3c\n+\tldr.w\tr9, [r7, #52]\t@ 0x34\n \tcmp.w\tip, #0\n-\tblt.n\t348c <__gridxc_alloc_MOD_realloc_l2+0x4dc>\n-\tldr\tr5, [r7, #16]\n+\tblt.n\t3314 <__gridxc_alloc_MOD_realloc_l2+0x480>\n+\tldr\tr5, [r7, #4]\n \tmov.w\tlr, #0\n-\tldr\tr4, [r7, #72]\t@ 0x48\n-\tstrd\tfp, r2, [r7, #4]\n+\tldr\tr4, [r7, #12]\n+\tstrd\tr0, r1, [r7, #12]\n \tmla\tr6, r2, r4, r5\n \tmul.w\tr4, sl, r4\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tldr\tr4, [r7, #20]\n-\tldr.w\tfp, [r7, #72]\t@ 0x48\n-\tstrd\tr0, r1, [r7, #16]\n+\tstr\tr4, [r7, #64]\t@ 0x40\n+\tldr\tr4, [r7, #8]\n+\tstrd\tfp, r2, [r7, #4]\n+\tldr.w\tfp, [r7, #64]\t@ 0x40\n \tmla\tr6, r0, r4, r6\n \tmul.w\tr5, sl, r4\n-\tldr\tr4, [r7, #56]\t@ 0x38\n+\tldr\tr4, [r7, #48]\t@ 0x30\n \tmla\tr6, sl, r6, r4\n \tmov\tsl, lr\n \tadd.w\tr4, r9, lr, lsl #2\n \tmov\tr0, r6\n \tmovs\tr1, #0\n \tldr\tr2, [r0, #0]\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tadd\tr0, r5\n \tadd.w\tr1, r1, #1\n \tstr.w\tr2, [r4], #4\n-\tbne.n\t3424 <__gridxc_alloc_MOD_realloc_l2+0x474>\n+\tbne.n\t32ac <__gridxc_alloc_MOD_realloc_l2+0x418>\n \tadd.w\tsl, sl, #1\n \tadd\tr6, fp\n \tadd\tlr, r3\n-\tcmp\tr8, sl\n-\tbge.n\t341c <__gridxc_alloc_MOD_realloc_l2+0x46c>\n+\tcmp\tsl, r8\n+\tble.n\t32a4 <__gridxc_alloc_MOD_realloc_l2+0x410>\n \tldrd\tfp, r2, [r7, #4]\n-\tldr\tr5, [r7, #12]\n-\tldrd\tr0, r1, [r7, #16]\n+\tldr\tr5, [r7, #20]\n+\tldrd\tr0, r1, [r7, #12]\n \tldr.w\tr4, [fp, #36]\t@ 0x24\n \tldr.w\tsl, [fp, #20]\n-\tstr\tr4, [r7, #72]\t@ 0x48\n+\tstr\tr4, [r7, #64]\t@ 0x40\n \tmla\tr4, r2, r4, r5\n \tmovs\tr5, #0\n \tmla\tr4, r0, r1, r4\n \tmov\tr6, r5\n \tmul.w\tlr, sl, r1\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tadd.w\tfp, r9, r5, lsl #2\n \tmovs\tr1, #0\n \tmla\tr0, sl, r4, r2\n \tldr.w\tr2, [fp], #4\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tstr\tr2, [r0, #0]\n \tadd.w\tr1, r1, #1\n \tadd\tr0, lr\n-\tbne.n\t3470 <__gridxc_alloc_MOD_realloc_l2+0x4c0>\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tbne.n\t32f8 <__gridxc_alloc_MOD_realloc_l2+0x464>\n+\tldr\tr2, [r7, #64]\t@ 0x40\n \tadds\tr6, #1\n \tadd\tr5, r3\n-\tcmp\tr6, r8\n+\tcmp\tr8, r6\n \tadd\tr4, r2\n-\tble.n\t3464 <__gridxc_alloc_MOD_realloc_l2+0x4b4>\n+\tbge.n\t32ec <__gridxc_alloc_MOD_realloc_l2+0x458>\n \tldr\tr2, [r7, #32]\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n \tmovs\tr4, #1\n-\tldr\tr5, [r7, #68]\t@ 0x44\n+\tldr\tr5, [r7, #56]\t@ 0x38\n \tsubs\tr3, r3, r2\n-\tldrd\tr2, r1, [r7, #44]\t@ 0x2c\n+\tldrd\tr2, r1, [r7, #36]\t@ 0x24\n \tadds\tr3, #1\n \tcmp\tr5, #0\n \tldr.w\tsp, [r7, #24]\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadd.w\tr2, r2, #1\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr2, [r7, #396]\t@ 0x18c\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr.w\tr2, [r7, #460]\t@ 0x1cc\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tstr.w\tr2, [r7, #396]\t@ 0x18c\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n \tcmp\tr2, #0\n \tit\teq\n \tmoveq\tr1, #0\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr1, [r7, #400]\t@ 0x190\n \tstr\tr1, [sp, #8]\n-\tldr\tr1, [pc, #384]\t@ (3660 <__gridxc_alloc_MOD_realloc_l2+0x6b0>)\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tldr\tr1, [pc, #380]\t@ (34e4 <__gridxc_alloc_MOD_realloc_l2+0x650>)\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n \tstr\tr3, [sp, #4]\n \tadd\tr1, pc\n \tmov\tr3, r2\n \tstr\tr4, [sp, #0]\n \tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tcbz\tr3, 34fc <__gridxc_alloc_MOD_realloc_l2+0x54c>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tcbz\tr3, 3384 <__gridxc_alloc_MOD_realloc_l2+0x4f0>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n+\tldr\tr0, [pc, #352]\t@ (34e8 <__gridxc_alloc_MOD_realloc_l2+0x654>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #28]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #328]\t@ 0x148\n-\tvldr\td18, [pc, #320]\t@ 3648 <__gridxc_alloc_MOD_realloc_l2+0x698>\n-\tvldr\td19, [pc, #324]\t@ 3650 <__gridxc_alloc_MOD_realloc_l2+0x6a0>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tldr\tr0, [pc, #336]\t@ (3664 <__gridxc_alloc_MOD_realloc_l2+0x6b4>)\n-\tvldr\td17, [pc, #324]\t@ 3658 <__gridxc_alloc_MOD_realloc_l2+0x6a8>\n \tadd\tr0, pc\n-\tldr\tr1, [r7, #68]\t@ 0x44\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstrd\tr5, r5, [r7, #296]\t@ 0x128\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldrd\tr1, r2, [r7, #56]\t@ 0x38\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #308]\t@ 0x134\n+\tstr.w\tr4, [r7, #324]\t@ 0x144\n+\tmovs\tr4, #2\n+\tstr.w\tr4, [r7, #316]\t@ 0x13c\n+\tstr.w\tr4, [r7, #328]\t@ 0x148\n+\tstr.w\tr4, [r7, #320]\t@ 0x140\n \tmovs\tr4, #4\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #336]\t@ 0x150\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n+\tstr.w\tr4, [r7, #292]\t@ 0x124\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstrh.w\tr4, [r7, #344]\t@ 0x158\n-\tmovs\tr4, #2\n-\tstr.w\tr4, [r7, #372]\t@ 0x174\n+\tstrh.w\tr4, [r7, #300]\t@ 0x12c\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #332]\t@ 0x14c\n-\tldr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tldrd\tr3, r2, [r7, #60]\t@ 0x3c\n+\tstr.w\tr4, [r7, #288]\t@ 0x120\n+\tldr.w\tr4, [r7, #400]\t@ 0x190\n+\tldr\tr3, [r7, #52]\t@ 0x34\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr4, [r7, #396]\t@ 0x18c\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #264]\t@ (3668 <__gridxc_alloc_MOD_realloc_l2+0x6b8>)\n-\tldr\tr3, [pc, #268]\t@ (366c <__gridxc_alloc_MOD_realloc_l2+0x6bc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #264]\t@ (34ec <__gridxc_alloc_MOD_realloc_l2+0x658>)\n+\tldr\tr3, [pc, #228]\t@ (34c8 <__gridxc_alloc_MOD_realloc_l2+0x634>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n+\tldr.w\tr3, [r7, #332]\t@ 0x14c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t3634 <__gridxc_alloc_MOD_realloc_l2+0x684>\n-\tadd.w\tr7, r7, #388\t@ 0x184\n+\tbne.n\t34b2 <__gridxc_alloc_MOD_realloc_l2+0x61e>\n+\tadd.w\tr7, r7, #340\t@ 0x154\n \tmov\tsp, r7\n-\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldrd\tr1, r0, [r7, #44]\t@ 0x2c\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldrd\tr1, r0, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #56]\t@ 0x38\n \tcmp\tr3, #0\n \tsub.w\tr3, r1, r0\n \tldr\tr0, [r7, #32]\n-\tadd.w\tr3, r3, #1\n-\tldr\tr1, [r7, #52]\t@ 0x34\n+\tadd\tr3, r5\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n \tbic.w\tr3, r3, r3, asr #31\n \tsub.w\tr2, r1, r0\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tadd.w\tr2, r2, #1\n-\tldr\tr1, [pc, #200]\t@ (3670 <__gridxc_alloc_MOD_realloc_l2+0x6c0>)\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n-\tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr\tr5, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #396]\t@ 0x18c\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #64]\t@ 0x40\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tcmp\tr2, #0\n+\tldr\tr5, [r7, #60]\t@ 0x3c\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n+\tcmp\tr5, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #164]\t@ (34f0 <__gridxc_alloc_MOD_realloc_l2+0x65c>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tldr\tr2, [r7, #68]\t@ 0x44\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #56]\t@ 0x38\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tadd\tr1, pc\n+\tmov\tr3, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr\tr6, [r4, #16]\n-\tstr\tr6, [r7, #56]\t@ 0x38\n-\tb.n\t317c <__gridxc_alloc_MOD_realloc_l2+0x1cc>\n-\tmov.w\tip, #1\n+\tstr.w\tr8, [r6, #16]\n+\tstr.w\tr8, [r7, #48]\t@ 0x30\n+\tb.n\t3046 <__gridxc_alloc_MOD_realloc_l2+0x1b2>\n+\tmovs\tr5, #1\n \tcmp.w\tlr, #0\n-\tstr.w\tip, [r7, #168]\t@ 0xa8\n+\tstr\tr5, [r7, #124]\t@ 0x7c\n \tmov.w\tlr, #0\n-\tbge.w\t305c <__gridxc_alloc_MOD_realloc_l2+0xac>\n+\tbge.w\t2f3c <__gridxc_alloc_MOD_realloc_l2+0xa8>\n \tmov.w\tr8, #0\n-\tb.n\t3064 <__gridxc_alloc_MOD_realloc_l2+0xb4>\n-\tmovs\tr2, #0\n-\tb.n\t31fa <__gridxc_alloc_MOD_realloc_l2+0x24a>\n-\tmov.w\tip, #1\n+\tb.n\t2f42 <__gridxc_alloc_MOD_realloc_l2+0xae>\n+\tmovs\tr5, #1\n \tmov.w\tr8, #0\n-\tb.n\t3064 <__gridxc_alloc_MOD_realloc_l2+0xb4>\n+\tb.n\t2f42 <__gridxc_alloc_MOD_realloc_l2+0xae>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbnz\tr1, 3622 <__gridxc_alloc_MOD_realloc_l2+0x672>\n+\tcbnz\tr1, 349e <__gridxc_alloc_MOD_realloc_l2+0x60a>\n \tldr.w\tr1, [fp, #24]\n \tadd.w\tr9, sp, #16\n-\tb.n\t33e6 <__gridxc_alloc_MOD_realloc_l2+0x436>\n+\tb.n\t326e <__gridxc_alloc_MOD_realloc_l2+0x3da>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tb.n\t3618 <__gridxc_alloc_MOD_realloc_l2+0x668>\n+\tb.n\t3494 <__gridxc_alloc_MOD_realloc_l2+0x600>\n+\tmov\tr0, r6\n+\tcmp\tr6, #0\n+\tbeq.w\t30c8 <__gridxc_alloc_MOD_realloc_l2+0x234>\n \tmovs\tr0, #1\n-\tcmp\tr2, #0\n-\tbne.w\t3208 <__gridxc_alloc_MOD_realloc_l2+0x258>\n-\tb.n\t3200 <__gridxc_alloc_MOD_realloc_l2+0x250>\n+\tb.n\t30ce <__gridxc_alloc_MOD_realloc_l2+0x23a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t3234 <__gridxc_alloc_MOD_realloc_l2+0x284>\n+\tb.n\t3102 <__gridxc_alloc_MOD_realloc_l2+0x26e>\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t3234 <__gridxc_alloc_MOD_realloc_l2+0x284>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000178\n+\tb.n\t3102 <__gridxc_alloc_MOD_realloc_l2+0x26e>\n+\tnop\n+\t.word\t0x00000608\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000005f2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000498\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000486\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000344\n+ R_ARM_REL32\t.LC26\n+\t.word\t0x000002da\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000174\n R_ARM_REL32\t.LC26\n-\t.word\t0x0000014a\n+\t.word\t0x0000015a\n R_ARM_REL32\t.bss\n \t.word\t0x00000104\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000c2\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC26\n \n-00003674 <__gridxc_alloc_MOD_realloc_l1>:\n+000034f4 <__gridxc_alloc_MOD_realloc_l1>:\n __gridxc_alloc_MOD_realloc_l1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n-\tldr.w\tip, [pc, #892]\t@ 3a08 <__gridxc_alloc_MOD_realloc_l1+0x394>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #892]\t@ (3a0c <__gridxc_alloc_MOD_realloc_l1+0x398>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tlr, [pc, #888]\t@ 3a10 <__gridxc_alloc_MOD_realloc_l1+0x39c>\n+\tldr.w\tr0, [pc, #1100]\t@ 3954 <__gridxc_alloc_MOD_realloc_l1+0x460>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1096]\t@ 3958 <__gridxc_alloc_MOD_realloc_l1+0x464>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1088]\t@ 395c <__gridxc_alloc_MOD_realloc_l1+0x468>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #328]\t@ 0x148\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #336]\t@ 0x150\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t39a8 <__gridxc_alloc_MOD_realloc_l1+0x334>\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldrd\tr3, r2, [r4, #28]\n-\tstr\tr3, [r7, #24]\n-\tstr\tr2, [r7, #16]\n-\tcmp\tr2, r3\n+\titet\teq\n+\tstreq\tr3, [r7, #16]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t356e <__gridxc_alloc_MOD_realloc_l1+0x7a>\n+\tstr\tr3, [r7, #32]\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n-\tstr\tr3, [r7, #0]\n-\tldr\tr3, [r4, #24]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #16]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #752]\t@ 39e8 <__gridxc_alloc_MOD_realloc_l1+0x374>\n-\tvldr\td19, [pc, #756]\t@ 39f0 <__gridxc_alloc_MOD_realloc_l1+0x37c>\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #244\t@ 0xf4\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #100\t@ 0x64\n-\tvldr\td17, [pc, #744]\t@ 39f8 <__gridxc_alloc_MOD_realloc_l1+0x384>\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #92]\t@ 0x5c\n-\tadd.w\tsl, r7, #64\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #116\t@ 0x74\n-\tldr.w\tr9, [pc, #740]\t@ 3a14 <__gridxc_alloc_MOD_realloc_l1+0x3a0>\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tadd.w\tr1, r7, #128\t@ 0x80\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #148\t@ 0x94\n-\tvstr\td16, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #220\t@ 0xdc\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #896]\t@ 3960 <__gridxc_alloc_MOD_realloc_l1+0x46c>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n \tadd\tr9, pc\n-\tvstr\td16, [r7, #184]\t@ 0xb8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #164\t@ 0xa4\n-\tvstr\td16, [r7, #188]\t@ 0xbc\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #196\t@ 0xc4\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tstr\tr2, [r7, #32]\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #212\t@ 0xd4\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tvst1.32\t{d18-d19}, [fp]\n-\tstr\tr3, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #124]\t@ 0x7c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tadd.w\tr3, r7, #48\t@ 0x30\n-\tstr.w\tr8, [r7, #172]\t@ 0xac\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n-\tstr\tr3, [r7, #20]\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tadd.w\tr2, r7, #176\t@ 0xb0\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #80\t@ 0x50\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 3832 <__gridxc_alloc_MOD_realloc_l1+0x1be>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #8]\n-\tcmp\tr3, #0\n-\tbne.n\t386c <__gridxc_alloc_MOD_realloc_l1+0x1f8>\n-\tldr\tr2, [r7, #16]\n+\tcbz\tr3, 3698 <__gridxc_alloc_MOD_realloc_l1+0x1a4>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t36ce <__gridxc_alloc_MOD_realloc_l1+0x1da>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #24]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #548]\t@ (3a18 <__gridxc_alloc_MOD_realloc_l1+0x3a4>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #780]\t@ (3964 <__gridxc_alloc_MOD_realloc_l1+0x470>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #8]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr3, [pc, #488]\t@ (3a1c <__gridxc_alloc_MOD_realloc_l1+0x3a8>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #716]\t@ (3968 <__gridxc_alloc_MOD_realloc_l1+0x474>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 3876 <__gridxc_alloc_MOD_realloc_l1+0x202>\n-\tldr\tr3, [pc, #484]\t@ (3a20 <__gridxc_alloc_MOD_realloc_l1+0x3ac>)\n+\tcbnz\tr3, 36d8 <__gridxc_alloc_MOD_realloc_l1+0x1e4>\n+\tldr\tr3, [pc, #712]\t@ (396c <__gridxc_alloc_MOD_realloc_l1+0x478>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t39ac <__gridxc_alloc_MOD_realloc_l1+0x338>\n-\tldr\tr2, [pc, #476]\t@ (3a24 <__gridxc_alloc_MOD_realloc_l1+0x3b0>)\n-\tldr\tr3, [pc, #448]\t@ (3a0c <__gridxc_alloc_MOD_realloc_l1+0x398>)\n+\tbne.w\t37f0 <__gridxc_alloc_MOD_realloc_l1+0x2fc>\n+\tldr\tr2, [pc, #704]\t@ (3970 <__gridxc_alloc_MOD_realloc_l1+0x47c>)\n+\tldr\tr3, [pc, #680]\t@ (3958 <__gridxc_alloc_MOD_realloc_l1+0x464>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t3b5a <__gridxc_alloc_MOD_realloc_l1+0x4e6>\n-\tadd.w\tr7, r7, #284\t@ 0x11c\n+\tbne.w\t3942 <__gridxc_alloc_MOD_realloc_l1+0x44e>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t39ac <__gridxc_alloc_MOD_realloc_l1+0x338>\n-\tvldr\td8, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t37f0 <__gridxc_alloc_MOD_realloc_l1+0x2fc>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #4\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #513\t@ 0x201\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #1073741824\t@ 0x40000000\n-\tbge.w\t3b64 <__gridxc_alloc_MOD_realloc_l1+0x4f0>\n+\tbge.w\t394c <__gridxc_alloc_MOD_realloc_l1+0x458>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #2\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t3b5e <__gridxc_alloc_MOD_realloc_l1+0x4ea>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #312]\t@ 3a00 <__gridxc_alloc_MOD_realloc_l1+0x38c>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t3946 <__gridxc_alloc_MOD_realloc_l1+0x452>\n+\tmovs\tr3, #4\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #332]\t@ (3a28 <__gridxc_alloc_MOD_realloc_l1+0x3b4>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #28]\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #584]\t@ (3974 <__gridxc_alloc_MOD_realloc_l1+0x480>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #272]\t@ 39f8 <__gridxc_alloc_MOD_realloc_l1+0x384>\n-\tvldr\td18, [pc, #252]\t@ 39e8 <__gridxc_alloc_MOD_realloc_l1+0x374>\n-\tvldr\td19, [pc, #256]\t@ 39f0 <__gridxc_alloc_MOD_realloc_l1+0x37c>\n-\tvstr\td17, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tr1, r5\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n \tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #240]\t@ 0xf0\n-\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n \tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #32]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #220]\t@ (3a2c <__gridxc_alloc_MOD_realloc_l1+0x3b8>)\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #480]\t@ (3978 <__gridxc_alloc_MOD_realloc_l1+0x484>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr.w\tip, [r4, #24]\n-\tldrd\tr0, r1, [r4, #28]\n-\tldrd\tr3, r2, [r4]\n-\tcmp\tr0, r1\n-\tbgt.w\t383a <__gridxc_alloc_MOD_realloc_l1+0x1c6>\n-\tadd\tr1, r8\n-\tmla\tr2, ip, r0, r2\n-\tsubs\tr1, r1, r0\n-\tldr\tr0, [r4, #20]\n-\tmla\tr3, r0, r2, r3\n-\tmovs\tr2, #0\n-\tmul.w\tr0, ip, r0\n-\tmov\tip, r2\n-\tadds\tr2, #1\n-\tstr.w\tip, [r3]\n-\tcmp\tr2, r1\n-\tadd\tr3, r0\n-\tbne.n\t399a <__gridxc_alloc_MOD_realloc_l1+0x326>\n-\tb.n\t383a <__gridxc_alloc_MOD_realloc_l1+0x1c6>\n-\tstr\tr3, [r7, #12]\n-\tb.n\t36f0 <__gridxc_alloc_MOD_realloc_l1+0x7c>\n-\tldrd\tr9, r2, [r7, #56]\t@ 0x38\n-\tmov\tsl, sp\n+\tldrd\tr1, r2, [r4, #28]\n+\tldrd\tr3, r0, [r4]\n+\tcmp\tr1, r2\n+\tbgt.w\t36a0 <__gridxc_alloc_MOD_realloc_l1+0x1ac>\n+\tadd\tr2, r9\n+\tmla\tr0, ip, r1, r0\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [r4, #20]\n+\tmla\tr3, r1, r0, r3\n+\tmov\tr0, r8\n+\tmul.w\tr1, ip, r1\n+\tadd.w\tr8, r8, #1\n+\tstr\tr0, [r3, #0]\n+\tcmp\tr2, r8\n+\tadd\tr3, r1\n+\tbne.n\t37e2 <__gridxc_alloc_MOD_realloc_l1+0x2ee>\n+\tb.n\t36a0 <__gridxc_alloc_MOD_realloc_l1+0x1ac>\n+\tldrd\tr9, r2, [r7, #52]\t@ 0x34\n+\tmov\tfp, sp\n \tsubs.w\tr2, r2, r9\n-\tbmi.n\t3a9c <__gridxc_alloc_MOD_realloc_l1+0x428>\n+\tbmi.n\t388e <__gridxc_alloc_MOD_realloc_l1+0x39a>\n \tlsls\tr3, r2, #2\n \tldr\tr1, [r4, #0]\n \tadds\tr3, #11\n-\tstr\tr1, [r7, #8]\n+\tstr\tr1, [r7, #12]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tldr\tr0, [r4, #4]\n \tbic.w\tr1, r1, #15\n \tbic.w\tr3, r3, #7\n \tsub.w\tr1, sp, r1\n \tmov\tip, sp\n \tcmp\tip, r1\n-\tbeq.n\t3a30 <__gridxc_alloc_MOD_realloc_l1+0x3bc>\n+\tbeq.n\t3826 <__gridxc_alloc_MOD_realloc_l1+0x332>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t39d2 <__gridxc_alloc_MOD_realloc_l1+0x35e>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000372\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000036a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ca\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000021e\n- R_ARM_REL32\t.LC26\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000140\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000d6\n- R_ARM_REL32\t.LC26\n+\tb.n\t3816 <__gridxc_alloc_MOD_realloc_l1+0x322>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 3a40 <__gridxc_alloc_MOD_realloc_l1+0x3cc>\n+\tcbz\tr3, 3836 <__gridxc_alloc_MOD_realloc_l1+0x342>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldrd\tr1, r3, [r7]\n+\tldrd\tr1, r3, [r7, #4]\n \tmov.w\tlr, #0\n+\tldr.w\tsl, [r4, #24]\n \tmla\tip, r9, r3, r1\n-\tldr\tr1, [r7, #12]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr8, r1, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #32]\n \tmla\tip, r1, ip, r3\n-\tldr\tr1, [r4, #24]\n \tadd\tr3, sp, #12\n-\tstr\tr1, [r7, #12]\n \tmov\tr1, r3\n-\tstr\tr3, [r7, #4]\n+\tstr\tr3, [r7, #16]\n \tldr.w\tr3, [ip]\n \tadd.w\tlr, lr, #1\n \tadd\tip, r8\n \tcmp\tlr, r2\n \tstr.w\tr3, [r1, #4]!\n-\tble.n\t3a62 <__gridxc_alloc_MOD_realloc_l1+0x3ee>\n-\tldr\tr1, [r7, #12]\n-\tldr\tr3, [r7, #4]\n-\tmla\tr0, r9, r1, r0\n+\tble.n\t3858 <__gridxc_alloc_MOD_realloc_l1+0x364>\n \tldr\tr1, [r4, #20]\n-\tldr\tr4, [r7, #8]\n-\tmla\tr0, r1, r0, r4\n+\tmla\tr0, r9, sl, r0\n \tldr\tr4, [r7, #12]\n-\tmul.w\tip, r4, r1\n+\tldr\tr3, [r7, #16]\n+\tmul.w\tip, sl, r1\n+\tmla\tr0, r1, r0, r4\n \tmovs\tr4, #0\n \tldr.w\tr1, [r3, #4]!\n-\tcmp\tr2, r4\n+\tcmp\tr4, r2\n \tstr\tr1, [r0, #0]\n \tadd.w\tr4, r4, #1\n \tadd\tr0, ip\n-\tbne.n\t3a8c <__gridxc_alloc_MOD_realloc_l1+0x418>\n-\tldr\tr2, [r7, #24]\n+\tbne.n\t387e <__gridxc_alloc_MOD_realloc_l1+0x38a>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #16]\n-\tmov\tsp, sl\n-\tldr\tr1, [pc, #224]\t@ (3b88 <__gridxc_alloc_MOD_realloc_l1+0x514>)\n+\tldr\tr3, [r7, #20]\n+\tmov\tsp, fp\n+\tldr\tr1, [pc, #228]\t@ (397c <__gridxc_alloc_MOD_realloc_l1+0x488>)\n \tmov.w\tr4, #1\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n \tadd\tr1, pc\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #344]\t@ 0x158\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r5\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tcbz\tr3, 3afa <__gridxc_alloc_MOD_realloc_l1+0x486>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 38ec <__gridxc_alloc_MOD_realloc_l1+0x3f8>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #136]\t@ (3b8c <__gridxc_alloc_MOD_realloc_l1+0x518>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [pc, #144]\t@ (3980 <__gridxc_alloc_MOD_realloc_l1+0x48c>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #28]\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #96]\t@ 3b70 <__gridxc_alloc_MOD_realloc_l1+0x4fc>\n-\tvldr\td19, [pc, #100]\t@ 3b78 <__gridxc_alloc_MOD_realloc_l1+0x504>\n-\tvldr\td17, [pc, #104]\t@ 3b80 <__gridxc_alloc_MOD_realloc_l1+0x50c>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tstrh.w\tr4, [r7, #240]\t@ 0xf0\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #228]\t@ 0xe4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tldr\tr3, [r7, #32]\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t3846 <__gridxc_alloc_MOD_realloc_l1+0x1d2>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t36ac <__gridxc_alloc_MOD_realloc_l1+0x1b8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t38da <__gridxc_alloc_MOD_realloc_l1+0x266>\n+\tb.n\t3728 <__gridxc_alloc_MOD_realloc_l1+0x234>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t38da <__gridxc_alloc_MOD_realloc_l1+0x266>\n+\tb.n\t3728 <__gridxc_alloc_MOD_realloc_l1+0x234>\n \tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000c0\n+\t.word\t0x00000440\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000430\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000374\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000302\n R_ARM_REL32\t.LC26\n-\t.word\t0x0000007c\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002bc\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000023c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001d8\n+ R_ARM_REL32\t.LC26\n+\t.word\t0x000000c2\n+ R_ARM_REL32\t.LC26\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n \n-00003b90 <__gridxc_alloc_MOD_realloc_z2>:\n+00003984 <__gridxc_alloc_MOD_realloc_z2>:\n __gridxc_alloc_MOD_realloc_z2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3664]\t@ 0xe50\n-\tldr\tr4, [pc, #952]\t@ (3f60 <__gridxc_alloc_MOD_realloc_z2+0x3d0>)\n-\tsub\tsp, #380\t@ 0x17c\n+\tstr.w\tr0, [ip, #3712]\t@ 0xe80\n+\tldr.w\tr5, [pc, #1244]\t@ 3e74 <__gridxc_alloc_MOD_realloc_z2+0x4f0>\n \tmov\tr8, r0\n-\tldr\tr0, [pc, #952]\t@ (3f64 <__gridxc_alloc_MOD_realloc_z2+0x3d4>)\n-\tadd\tr4, pc\n-\tstr\tr3, [sp, #20]\n-\tldr\tr5, [sp, #436]\t@ 0x1b4\n-\tldr\tr0, [r4, r0]\n-\tldr\tr4, [pc, #944]\t@ (3f68 <__gridxc_alloc_MOD_realloc_z2+0x3d8>)\n+\tldr.w\tr0, [pc, #1244]\t@ 3e78 <__gridxc_alloc_MOD_realloc_z2+0x4f4>\n+\tsub\tsp, #348\t@ 0x15c\n+\tadd\tr5, pc\n+\tmov\tr9, r3\n+\tldr\tr6, [sp, #388]\t@ 0x184\n+\tldr\tr0, [r5, r0]\n+\tldr.w\tr5, [pc, #1232]\t@ 3e7c <__gridxc_alloc_MOD_realloc_z2+0x4f8>\n \tldr\tr0, [r0, #0]\n-\tstr\tr0, [sp, #372]\t@ 0x174\n+\tstr\tr0, [sp, #340]\t@ 0x154\n \tmov.w\tr0, #0\n \tldr.w\tr0, [r8]\n-\tadd\tr4, pc\n-\tstr\tr5, [sp, #32]\n+\tadd\tr5, pc\n+\tstr\tr6, [sp, #28]\n \tcmp\tr0, #0\n-\tldr\tr5, [sp, #440]\t@ 0x1b8\n-\tstr\tr5, [sp, #28]\n+\tldr\tr4, [sp, #384]\t@ 0x180\n+\tite\tne\n+\tmovne\tr6, #1\n+\tmoveq\tr6, #0\n+\tstr\tr6, [r5, #0]\n+\tldr\tr5, [sp, #392]\t@ 0x188\n+\tldrd\tr6, r7, [sp, #396]\t@ 0x18c\n+\tstr\tr5, [sp, #32]\n \tit\teq\n-\tmoveq\tr9, r0\n-\tmov.w\tr5, #1\n-\tldr\tr6, [sp, #432]\t@ 0x1b0\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tstr\tr5, [r4, #0]\n-\tldrd\tr4, r5, [sp, #444]\t@ 0x1bc\n-\tbeq.n\t3c34 <__gridxc_alloc_MOD_realloc_z2+0xa4>\n+\tstreq\tr0, [sp, #16]\n+\tbeq.n\t3a32 <__gridxc_alloc_MOD_realloc_z2+0xae>\n \tldr.w\tr3, [r8, #44]\t@ 0x2c\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr.w\tr3, [r8, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tldr.w\tr3, [r8, #32]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr.w\tr3, [r8, #36]\t@ 0x24\n+\tstr\tr3, [sp, #68]\t@ 0x44\n \tldr.w\tr3, [r8, #4]\n-\tldr.w\tr7, [r8, #40]\t@ 0x28\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr.w\tr3, [r8, #24]\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr.w\tr3, [r8, #20]\n+\tldr.w\tr5, [r8, #40]\t@ 0x28\n+\tstr\tr3, [sp, #16]\n \tldr\tr3, [sp, #44]\t@ 0x2c\n-\tstr\tr7, [sp, #64]\t@ 0x40\n-\tsub.w\tip, r3, r7\n-\tldr\tr7, [sp, #60]\t@ 0x3c\n+\tstr\tr5, [sp, #52]\t@ 0x34\n+\tsub.w\tip, r3, r5\n+\tldr\tr5, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr.w\tfp, [r8, #36]\t@ 0x24\n-\tldrd\tr9, sl, [r8, #20]\n-\tcmp\tr7, r3\n-\tblt.w\t40ae <__gridxc_alloc_MOD_realloc_z2+0x51e>\n+\tcmp\tr5, r3\n+\tblt.w\t3e3a <__gridxc_alloc_MOD_realloc_z2+0x4b6>\n \tcmp.w\tip, #0\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tmov\tip, r7\n-\tblt.w\t40c4 <__gridxc_alloc_MOD_realloc_z2+0x534>\n-\tldr\tr7, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tmov\tip, r5\n+\tblt.w\t3e50 <__gridxc_alloc_MOD_realloc_z2+0x4cc>\n+\tldr\tr5, [sp, #52]\t@ 0x34\n \tldr.w\tlr, [sp, #44]\t@ 0x2c\n-\tstrd\tip, r7, [sp, #164]\t@ 0xa4\n-\tstr.w\tlr, [sp, #172]\t@ 0xac\n+\tstrd\tip, r5, [sp, #136]\t@ 0x88\n+\tstr.w\tlr, [sp, #144]\t@ 0x90\n \tstr\tr0, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #772]\t@ 3f40 <__gridxc_alloc_MOD_realloc_z2+0x3b0>\n-\tvldr\td19, [pc, #776]\t@ 3f48 <__gridxc_alloc_MOD_realloc_z2+0x3b8>\n-\tadd\tr7, sp, #320\t@ 0x140\n-\tldr\tr0, [r3, #0]\n-\tldr\tr3, [r6, #0]\n-\tadd\tr6, sp, #356\t@ 0x164\n-\tldr\tr1, [r1, #0]\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr0, r3, [sp, #96]\t@ 0x60\n-\tadd\tr3, sp, #196\t@ 0xc4\n-\tstrd\tr1, r2, [sp, #88]\t@ 0x58\n-\tadd\tr0, sp, #340\t@ 0x154\n-\tvldr\td17, [pc, #756]\t@ 3f50 <__gridxc_alloc_MOD_realloc_z2+0x3c0>\n-\tmovs\tr2, #2\n-\tvldr\td20, [sp, #88]\t@ 0x58\n-\tvldr\td21, [sp, #96]\t@ 0x60\n-\tvstr\td16, [sp, #184]\t@ 0xb8\n-\tvstr\td16, [sp, #188]\t@ 0xbc\n-\tadd\tr1, sp, #128\t@ 0x80\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #212\t@ 0xd4\n-\tvstr\td16, [sp, #232]\t@ 0xe8\n-\tvst1.32\t{d17}, [r3]\n-\tadd\tr3, sp, #244\t@ 0xf4\n-\tvstr\td16, [sp, #236]\t@ 0xec\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #260\t@ 0x104\n-\tvstr\td16, [sp, #284]\t@ 0x11c\n-\tvst1.32\t{d17}, [r3]\n+\tldr.w\tr3, [r9]\n+\tmovs\tr5, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r1, #0]\n+\tadd.w\tip, sp, #100\t@ 0x64\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tmvn.w\tr1, #2\n+\tldr\tr3, [r4, #0]\n+\tadd\tr4, sp, #84\t@ 0x54\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tadd.w\tr9, sp, #116\t@ 0x74\n+\tldr\tr3, [r2, #0]\n+\tmovs\tr2, #0\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tadd\tr3, sp, #292\t@ 0x124\n-\tstr\tr0, [sp, #48]\t@ 0x30\n-\tstr\tr2, [sp, #220]\t@ 0xdc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #308\t@ 0x134\n-\tstr\tr2, [sp, #268]\t@ 0x10c\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr\tr2, [sp, #316]\t@ 0x13c\n+\tstrd\tr2, r2, [sp, #156]\t@ 0x9c\n+\tstr\tr3, [sp, #24]\n+\tmovs\tr3, #2\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tstrd\tr2, r2, [sp, #204]\t@ 0xcc\n+\tstr\tr2, [sp, #212]\t@ 0xd4\n \tstr\tr3, [sp, #180]\t@ 0xb4\n+\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n \tstr\tr3, [sp, #228]\t@ 0xe4\n-\tvstr\td16, [sp, #328]\t@ 0x148\n-\tstr\tr6, [sp, #52]\t@ 0x34\n-\tstr\tr7, [sp, #56]\t@ 0x38\n-\tvstr\td20, [sp, #112]\t@ 0x70\n-\tvstr\td21, [sp, #120]\t@ 0x78\n-\tstr\tr3, [sp, #276]\t@ 0x114\n-\tstrd\tr4, r5, [sp]\n-\tadd\tr5, sp, #112\t@ 0x70\n-\tldr\tr4, [pc, #668]\t@ (3f6c <__gridxc_alloc_MOD_realloc_z2+0x3dc>)\n-\tstr\tr2, [sp, #364]\t@ 0x16c\n-\tadd\tr2, sp, #272\t@ 0x110\n-\tadd\tr4, pc\n-\tstr\tr3, [sp, #324]\t@ 0x144\n-\tvstr\td16, [sp, #332]\t@ 0x14c\n-\tmov\tr3, r7\n-\tvst1.32\t{d18-d19}, [r0]\n-\tadd\tr0, sp, #176\t@ 0xb0\n-\tstr\tr1, [sp, #176]\t@ 0xb0\n-\tadd\tr1, sp, #144\t@ 0x90\n-\tvst1.32\t{d17}, [r6]\n-\tstr\tr1, [sp, #224]\t@ 0xe0\n-\tadd\tr1, sp, #160\t@ 0xa0\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #272]\t@ 0x110\n-\tadd\tr1, sp, #224\t@ 0xe0\n-\tstr\tr5, [sp, #320]\t@ 0x140\n-\tbl\t1fc <__gridxc_alloc_MOD_options.constprop.1>\n-\tldr\tr3, [r4, #8]\n-\tcbz\tr3, 3d06 <__gridxc_alloc_MOD_realloc_z2+0x176>\n-\tldr\tr6, [r4, #12]\n-\tcmp\tr6, #0\n-\tbeq.w\t4050 <__gridxc_alloc_MOD_realloc_z2+0x4c0>\n-\tldr\tr3, [pc, #616]\t@ (3f70 <__gridxc_alloc_MOD_realloc_z2+0x3e0>)\n+\tstr\tr3, [sp, #240]\t@ 0xf0\n+\tstr\tr3, [sp, #232]\t@ 0xe8\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tstr\tr0, [sp, #216]\t@ 0xd8\n+\tstr\tr1, [sp, #152]\t@ 0x98\n+\tstr\tr1, [sp, #200]\t@ 0xc8\n+\tstrd\tr5, r5, [sp, #172]\t@ 0xac\n+\tstr\tr5, [sp, #188]\t@ 0xbc\n+\tstrd\tr5, r5, [sp, #220]\t@ 0xdc\n+\tstr\tr5, [sp, #236]\t@ 0xec\n+\tstr\tr4, [sp, #148]\t@ 0x94\n+\tstr.w\tip, [sp, #196]\t@ 0xc4\n+\tstrd\tr6, r7, [sp]\n+\tadd\tr6, sp, #132\t@ 0x84\n+\tstr\tr6, [sp, #56]\t@ 0x38\n+\tstr\tr6, [sp, #244]\t@ 0xf4\n+\tldr\tr6, [pc, #996]\t@ (3e80 <__gridxc_alloc_MOD_realloc_z2+0x4fc>)\n+\tstrd\tr1, r2, [sp, #296]\t@ 0x128\n+\tadd\tr6, pc\n+\tstr\tr0, [sp, #264]\t@ 0x108\n+\tstr\tr0, [sp, #312]\t@ 0x138\n+\tadd\tr0, sp, #148\t@ 0x94\n+\tstrd\tr2, r2, [sp, #252]\t@ 0xfc\n+\tstr\tr2, [sp, #260]\t@ 0x104\n+\tstrd\tr5, r3, [sp, #272]\t@ 0x110\n+\tstrd\tr5, r3, [sp, #284]\t@ 0x11c\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tstr\tr1, [sp, #248]\t@ 0xf8\n+\tadd\tr1, sp, #196\t@ 0xc4\n+\tstrd\tr2, r2, [sp, #304]\t@ 0x130\n+\tadd\tr2, sp, #244\t@ 0xf4\n+\tstrd\tr5, r3, [sp, #320]\t@ 0x140\n+\tstrd\tr5, r3, [sp, #332]\t@ 0x14c\n+\tstr\tr3, [sp, #328]\t@ 0x148\n+\tldr\tr3, [sp, #24]\n+\tstr\tr5, [sp, #268]\t@ 0x10c\n+\tstr\tr5, [sp, #316]\t@ 0x13c\n+\tstr.w\tr9, [sp, #292]\t@ 0x124\n+\tbl\t1ec <__gridxc_alloc_MOD_options.constprop.1>\n+\tldr\tr3, [r6, #8]\n+\tcbz\tr3, 3ae6 <__gridxc_alloc_MOD_realloc_z2+0x162>\n+\tldr\tr7, [r6, #12]\n+\tcmp\tr7, #0\n+\tbeq.w\t3de0 <__gridxc_alloc_MOD_realloc_z2+0x45c>\n+\tldr\tr3, [pc, #924]\t@ (3e84 <__gridxc_alloc_MOD_realloc_z2+0x500>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t3eae <__gridxc_alloc_MOD_realloc_z2+0x31e>\n-\tldrd\tr4, r0, [sp, #128]\t@ 0x80\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r6, [sp, #136]\t@ 0x88\n-\tsubs\tr2, r0, r4\n-\torr.w\tr1, r2, r2, asr #31\n-\tvstr\td16, [r8, #12]\n+\tbeq.w\t3c94 <__gridxc_alloc_MOD_realloc_z2+0x310>\n+\tldrd\tsl, r3, [r4]\n+\tmovs\tr5, #0\n+\tldrd\tfp, r2, [r4, #8]\n+\tsub.w\tr6, r3, sl\n+\trsb\tr4, sl, #0\n+\tstr\tr3, [sp, #20]\n+\torr.w\tr7, r6, r6, asr #31\n+\tsub.w\tr1, r2, fp\n+\torrs\tr6, r1\n+\tstrd\tr5, r5, [r8, #12]\n+\torr.w\tr1, r1, r1, asr #31\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tmla\tr0, r7, fp, fp\n+\tlsrs\tr6, r6, #31\n+\tadds\tr7, #1\n \tadds\tr1, #1\n-\tstr\tr4, [sp, #72]\t@ 0x48\n-\tnegs\tr4, r4\n-\tstrd\tr1, r3, [sp, #80]\t@ 0x50\n-\tstr\tr0, [sp, #76]\t@ 0x4c\n-\tmovs\tr0, #16\n-\tvldr\td8, [sp, #72]\t@ 0x48\n-\tvldr\td9, [sp, #80]\t@ 0x50\n-\tmls\tr4, r1, r3, r4\n-\tsubs\tr3, r6, r3\n+\tsub.w\tr3, r4, r0\n+\tmov.w\tr0, #16\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tstr.w\tr0, [r8, #8]\n-\torrs\tr2, r3\n \tmovw\tr0, #1026\t@ 0x402\n-\torr.w\tr3, r3, r3, asr #31\n \tstrh.w\tr0, [r8, #16]\n-\tlsrs\tr2, r2, #31\n-\tadds\tr3, #1\n-\tbeq.w\t40cc <__gridxc_alloc_MOD_realloc_z2+0x53c>\n+\tbeq.w\t3e58 <__gridxc_alloc_MOD_realloc_z2+0x4d4>\n+\tmul.w\tr4, r1, r7\n \tmvn.w\tr0, #2147483648\t@ 0x80000000\n-\tudiv\tr0, r0, r3\n-\tmul.w\tr3, r1, r3\n-\tcmp.w\tr3, #268435456\t@ 0x10000000\n-\tit\tlt\n-\tmovlt\tr7, #0\n-\tit\tge\n-\tmovge\tr7, #1\n-\tcmp\tr0, r1\n-\tmov.w\tr0, r3, lsl #4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp.w\tr4, #268435456\t@ 0x10000000\n+\tite\tlt\n+\tmovlt\tr1, #0\n+\tmovge\tr1, #1\n+\tcmp\tr0, r7\n \tit\tlt\n-\taddlt\tr7, #1\n-\tcbz\tr2, 3d84 <__gridxc_alloc_MOD_realloc_z2+0x1f4>\n-\tmovs\tr0, #0\n-\tcmp\tr7, #0\n-\tbne.w\t40d8 <__gridxc_alloc_MOD_realloc_z2+0x548>\n+\taddlt\tr1, #1\n+\tlsls\tr0, r4, #4\n+\tcbz\tr6, 3b60 <__gridxc_alloc_MOD_realloc_z2+0x1dc>\n+\tmov\tr0, r5\n+\tcmp\tr1, #0\n+\tbne.w\t3e64 <__gridxc_alloc_MOD_realloc_z2+0x4e0>\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr.w\tr0, [r8]\n \tcmp\tr0, #0\n-\tbeq.w\t40de <__gridxc_alloc_MOD_realloc_z2+0x54e>\n-\tadd.w\tr3, r8, #28\n-\tstr.w\tr6, [r8, #44]\t@ 0x2c\n-\tvldr\td16, [pc, #432]\t@ 3f58 <__gridxc_alloc_MOD_realloc_z2+0x3c8>\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r8, #20\n-\tstr.w\tr4, [r8, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tmovs\tr3, #0\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tvldr\td18, [pc, #380]\t@ 3f40 <__gridxc_alloc_MOD_realloc_z2+0x3b0>\n-\tvldr\td19, [pc, #384]\t@ 3f48 <__gridxc_alloc_MOD_realloc_z2+0x3b8>\n-\tstr\tr5, [sp, #320]\t@ 0x140\n-\tvldr\td16, [pc, #384]\t@ 3f50 <__gridxc_alloc_MOD_realloc_z2+0x3c0>\n-\tmovs\tr6, #4\n-\tvstr\td17, [sp, #332]\t@ 0x14c\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tldr\tr0, [pc, #404]\t@ (3f74 <__gridxc_alloc_MOD_realloc_z2+0x3e4>)\n-\tldr\tr7, [sp, #32]\n+\tbeq.w\t3e6a <__gridxc_alloc_MOD_realloc_z2+0x4e6>\n+\tldr\tr3, [sp, #20]\n+\tmovs\tr2, #1\n+\tstr.w\tr3, [r8, #32]\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr.w\tr3, [r8, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tstr.w\tr3, [r8, #4]\n+\tmovs\tr3, #16\n+\tstrd\tr3, r2, [r8, #20]\n+\tmovs\tr3, #0\n+\tstr.w\tsl, [r8, #28]\n+\tstr.w\tfp, [r8, #40]\t@ 0x28\n+\tstr.w\tr7, [r8, #36]\t@ 0x24\n+\tldr\tr0, [pc, #740]\t@ (3e88 <__gridxc_alloc_MOD_realloc_z2+0x504>)\n+\tmovs\tr5, #1\n+\tldr\tr1, [sp, #28]\n+\tmovs\tr4, #2\n \tadd\tr0, pc\n-\tldr\tr4, [sp, #452]\t@ 0x1c4\n-\tvst1.32\t{d16}, [r2]\n-\tcmp\tr7, #0\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #32]\n+\tcmp\tr1, #0\n+\tmov.w\tip, #258\t@ 0x102\n \tit\teq\n-\tmoveq\tr4, #0\n-\tldr\tr5, [sp, #456]\t@ 0x1c8\n-\tmov\tr1, r7\n-\tcmp\tr2, #0\n+\tmoveq\tr6, #0\n+\tmov\tsl, r2\n \tstr.w\tr3, [r0, #16]!\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstr\tr4, [sp, #0]\n-\tstr\tr5, [sp, #4]\n-\tstr\tr6, [sp, #328]\t@ 0x148\n-\tmov.w\tr6, #258\t@ 0x102\n-\tstrh.w\tr6, [sp, #336]\t@ 0x150\n-\tmovs\tr6, #2\n-\tstr\tr6, [sp, #364]\t@ 0x16c\n-\tmvn.w\tr6, #2\n-\tstr\tr6, [sp, #324]\t@ 0x144\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tstrd\tr4, r5, [sp, #4]\n-\tadd\tr0, sp, #108\t@ 0x6c\n+\tldr\tr3, [sp, #404]\t@ 0x194\n+\tstr.w\tr9, [sp, #292]\t@ 0x124\n+\tmov\tr9, r1\n+\tit\tne\n+\tmovne\tr6, r3\n+\tldr\tr3, [sp, #408]\t@ 0x198\n+\tcmp\tr2, #0\n+\tstr\tr6, [sp, #0]\n+\tite\tne\n+\tmovne\tr7, r3\n+\tmoveq\tr7, #0\n+\tldr\tr3, [sp, #24]\n+\tstr\tr7, [sp, #4]\n+\tstrd\tr5, r5, [sp, #316]\t@ 0x13c\n+\tstr\tr5, [sp, #332]\t@ 0x14c\n+\tstr\tr4, [sp, #324]\t@ 0x144\n+\tstr\tr4, [sp, #336]\t@ 0x150\n+\tstr\tr4, [sp, #328]\t@ 0x148\n+\tmovs\tr4, #4\n+\tstr\tr4, [sp, #312]\t@ 0x138\n+\tstr\tr4, [sp, #300]\t@ 0x12c\n+\tmovs\tr4, #0\n+\tstrd\tr4, r4, [sp, #304]\t@ 0x130\n+\tstrh.w\tip, [sp, #308]\t@ 0x134\n+\tmvn.w\tip, #2\n+\tstr.w\tip, [sp, #296]\t@ 0x128\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tstr\tr5, [sp, #0]\n+\tadd\tr0, sp, #80\t@ 0x50\n+\tstrd\tr6, r7, [sp, #4]\n \tldrd\tr2, r3, [r8, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r8, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r5\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n-\tldr\tr1, [pc, #320]\t@ (3f78 <__gridxc_alloc_MOD_realloc_z2+0x3e8>)\n+\tadd\tr2, r5\n+\tldr\tr1, [pc, #620]\t@ (3e8c <__gridxc_alloc_MOD_realloc_z2+0x508>)\n \tbic.w\tr2, r2, r2, asr #31\n \tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r7\n-\tlsls\tr3, r3, #1\n+\tmov\tr2, r9\n+\tlsls\tr3, r5\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #28]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr0, r3, [r8, #40]\t@ 0x28\n-\tldrd\tr4, r1, [r8, #28]\n-\tcmp\tr0, r3\n-\tbgt.n\t3eae <__gridxc_alloc_MOD_realloc_z2+0x31e>\n+\tmov\tr3, sl\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr2, r3, [r8, #40]\t@ 0x28\n+\tldrd\tr5, r1, [r8, #28]\n+\tcmp\tr2, r3\n+\tbgt.n\t3c94 <__gridxc_alloc_MOD_realloc_z2+0x310>\n \tldr.w\tr7, [r8, #36]\t@ 0x24\n-\tcmp\tr4, r1\n-\tbgt.n\t3eae <__gridxc_alloc_MOD_realloc_z2+0x31e>\n+\tcmp\tr5, r1\n+\tbgt.n\t3c94 <__gridxc_alloc_MOD_realloc_z2+0x310>\n \tadds\tr3, #1\n \tldr.w\tip, [r8, #20]\n-\tsubs\tr6, r3, r0\n+\tsubs\tr6, r3, r2\n \tldr.w\tr3, [r8, #4]\n \tadds\tr1, #1\n \tldr.w\tlr, [r8]\n-\tsubs\tr1, r1, r4\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmovs\tr5, #0\n-\tmla\tr3, r0, r7, r3\n-\tldr.w\tr0, [r8, #24]\n-\tmla\tr4, r0, r4, r3\n-\tmul.w\tr0, r0, ip\n-\tmla\tr3, ip, r4, lr\n+\tsubs\tr1, r1, r5\n+\tmov.w\tsl, #0\n+\tmov.w\tfp, #0\n+\tmla\tr3, r2, r7, r3\n+\tldr.w\tr2, [r8, #24]\n+\tmla\tr5, r2, r5, r3\n+\tmul.w\tr0, r2, ip\n+\tmla\tr3, ip, r5, lr\n \tmovs\tr2, #0\n \tadds\tr2, #1\n-\tvstr\td16, [r3]\n-\tvstr\td16, [r3, #8]\n-\tcmp\tr2, r1\n+\tstrd\tsl, fp, [r3]\n+\tstrd\tsl, fp, [r3, #8]\n+\tcmp\tr1, r2\n \tadd\tr3, r0\n-\tbne.n\t3e96 <__gridxc_alloc_MOD_realloc_z2+0x306>\n-\tadds\tr5, #1\n-\tadd\tr4, r7\n-\tcmp\tr6, r5\n-\tbne.n\t3e90 <__gridxc_alloc_MOD_realloc_z2+0x300>\n-\tldr\tr3, [pc, #204]\t@ (3f7c <__gridxc_alloc_MOD_realloc_z2+0x3ec>)\n+\tbne.n\t3c7c <__gridxc_alloc_MOD_realloc_z2+0x2f8>\n+\tadds\tr4, #1\n+\tadd\tr5, r7\n+\tcmp\tr6, r4\n+\tbne.n\t3c76 <__gridxc_alloc_MOD_realloc_z2+0x2f2>\n+\tldr\tr3, [pc, #504]\t@ (3e90 <__gridxc_alloc_MOD_realloc_z2+0x50c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t4032 <__gridxc_alloc_MOD_realloc_z2+0x4a2>\n-\tldrd\tr4, r3, [sp, #152]\t@ 0x98\n+\tbeq.w\t3dc6 <__gridxc_alloc_MOD_realloc_z2+0x442>\n+\tldrd\tr4, r3, [sp, #108]\t@ 0x6c\n \tcmp\tr4, r3\n-\tbgt.n\t3f80 <__gridxc_alloc_MOD_realloc_z2+0x3f0>\n-\tldrd\tr6, r0, [sp, #144]\t@ 0x90\n+\tbgt.n\t3d20 <__gridxc_alloc_MOD_realloc_z2+0x39c>\n+\tldrd\tr6, r0, [sp, #100]\t@ 0x64\n \tcmp\tr6, r0\n-\tbgt.n\t3f80 <__gridxc_alloc_MOD_realloc_z2+0x3f0>\n-\tldr\tr2, [sp, #24]\n-\tmul.w\tlr, r9, sl\n-\tadds\tr0, #1\n-\tmla\tr5, fp, r4, r2\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tmla\tr5, r6, sl, r5\n-\tldr.w\tsl, [r8, #4]\n-\tmul.w\tfp, fp, r9\n-\tmla\tr5, r9, r5, r2\n+\tbgt.n\t3d20 <__gridxc_alloc_MOD_realloc_z2+0x39c>\n+\tldr\tr1, [sp, #68]\t@ 0x44\n \tadd.w\tr9, r3, #1\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tadds\tr0, #1\n \tldrd\tr7, r3, [r8, #20]\n-\tldr.w\tr2, [r8]\n-\tstr\tr2, [sp, #20]\n+\tmla\tr5, r1, r4, r2\n+\tldr\tr2, [sp, #16]\n \tmul.w\tip, r7, r3\n+\tmul.w\tsl, r1, r2\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmla\tr5, r6, r1, r5\n+\tmul.w\tlr, r2, r1\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tmla\tr5, r2, r5, r1\n+\tldrd\tfp, r2, [r8]\n+\tstr\tr2, [sp, #16]\n \tldr.w\tr2, [r8, #36]\t@ 0x24\n \tmul.w\tr8, r6, r3\n-\tstr\tr2, [sp, #24]\n-\tldr\tr3, [sp, #24]\n+\tstr\tr2, [sp, #20]\n+\tldrd\tr3, r2, [sp, #16]\n \tmov\tr1, r6\n-\tldr\tr2, [sp, #20]\n-\tmla\tr3, r4, r3, sl\n-\tadd\tr3, r8\n-\tmla\tr3, r7, r3, r2\n+\tmla\tr3, r4, r2, r3\n \tmov\tr2, r5\n-\tvldr\td17, [r2]\n+\tadd\tr3, r8\n+\tmla\tr3, r7, r3, fp\n+\tvldr\td6, [r2]\n \tadds\tr1, #1\n-\tvldr\td16, [r2, #8]\n-\tcmp\tr0, r1\n+\tvldr\td7, [r2, #8]\n+\tcmp\tr1, r0\n \tadd\tr2, lr\n-\tvstr\td17, [r3]\n-\tvstr\td16, [r3, #8]\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #8]\n \tadd\tr3, ip\n-\tbne.n\t3f16 <__gridxc_alloc_MOD_realloc_z2+0x386>\n+\tbne.n\t3cfe <__gridxc_alloc_MOD_realloc_z2+0x37a>\n \tadds\tr4, #1\n-\tadd\tr5, fp\n-\tcmp\tr9, r4\n-\tbne.n\t3f04 <__gridxc_alloc_MOD_realloc_z2+0x374>\n-\tb.n\t3f80 <__gridxc_alloc_MOD_realloc_z2+0x3f0>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000010\n-\t.word\t0x00000001\n-\t.word\t0x000003b0\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003a2\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000296\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000264\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000190\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000138\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000000c8\n- R_ARM_REL32\t.bss\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tadd\tr0, sp, #108\t@ 0x6c\n+\tadd\tr5, sl\n+\tcmp\tr4, r9\n+\tbne.n\t3cec <__gridxc_alloc_MOD_realloc_z2+0x368>\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadd\tr0, sp, #80\t@ 0x50\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tmovs\tr4, #1\n \tldr\tr1, [sp, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadds\tr3, #1\n-\tldr\tr5, [sp, #32]\n+\tldr\tr5, [sp, #28]\n \tsubs\tr2, r2, r1\n \tadds\tr2, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr5, #0\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #452]\t@ 0x1c4\n+\tldr\tr2, [sp, #404]\t@ 0x194\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr\tr2, [sp, #452]\t@ 0x1c4\n-\tldr\tr2, [sp, #28]\n-\tldr\tr1, [sp, #452]\t@ 0x1c4\n+\tstr\tr2, [sp, #404]\t@ 0x194\n+\tldr\tr2, [sp, #32]\n+\tldr\tr1, [sp, #404]\t@ 0x194\n \tlsls\tr3, r3, #1\n \tcmp\tr2, #0\n \tstr\tr1, [sp, #4]\n-\tldr\tr1, [sp, #456]\t@ 0x1c8\n+\tldr\tr1, [sp, #408]\t@ 0x198\n \tit\teq\n \tmoveq\tr1, #0\n \tstr\tr1, [sp, #8]\n \tnegs\tr3, r3\n-\tstr\tr1, [sp, #456]\t@ 0x1c8\n-\tldr\tr1, [pc, #316]\t@ (4100 <__gridxc_alloc_MOD_realloc_z2+0x570>)\n+\tstr\tr1, [sp, #408]\t@ 0x198\n+\tldr\tr1, [pc, #304]\t@ (3e94 <__gridxc_alloc_MOD_realloc_z2+0x510>)\n \tstr\tr3, [r0, #0]\n \tmov\tr3, r2\n \tadd\tr1, pc\n \tmov\tr2, r5\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr3, [sp, #36]\t@ 0x24\n-\tcbz\tr3, 3fde <__gridxc_alloc_MOD_realloc_z2+0x44e>\n+\tcbz\tr3, 3d7e <__gridxc_alloc_MOD_realloc_z2+0x3fa>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #320]\t@ 0x140\n-\tvldr\td18, [pc, #256]\t@ 40e8 <__gridxc_alloc_MOD_realloc_z2+0x558>\n-\tvldr\td19, [pc, #260]\t@ 40f0 <__gridxc_alloc_MOD_realloc_z2+0x560>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr0, [pc, #272]\t@ (4104 <__gridxc_alloc_MOD_realloc_z2+0x574>)\n-\tvldr\td17, [pc, #260]\t@ 40f8 <__gridxc_alloc_MOD_realloc_z2+0x568>\n+\tldr\tr0, [pc, #280]\t@ (3e98 <__gridxc_alloc_MOD_realloc_z2+0x514>)\n+\tmovs\tr5, #0\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #292]\t@ 0x124\n+\tldrd\tr1, r2, [sp, #28]\n+\tstrd\tr5, r5, [sp, #304]\t@ 0x130\n \tstr.w\tr4, [r0, #16]!\n-\tldr\tr4, [sp, #456]\t@ 0x1c8\n-\tldrd\tr2, r1, [sp, #28]\n-\tvst1.32\t{d17}, [r3]\n+\tldr\tr4, [sp, #408]\t@ 0x198\n \tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #452]\t@ 0x1c4\n+\tldr\tr4, [sp, #404]\t@ 0x194\n \tstr\tr4, [sp, #0]\n-\tmovs\tr4, #4\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tmovs\tr4, #1\n+\tldr\tr3, [sp, #24]\n+\tstrd\tr4, r4, [sp, #316]\t@ 0x13c\n+\tstr\tr4, [sp, #332]\t@ 0x14c\n+\tmovs\tr4, #2\n+\tstr\tr4, [sp, #324]\t@ 0x144\n+\tstr\tr4, [sp, #336]\t@ 0x150\n \tstr\tr4, [sp, #328]\t@ 0x148\n+\tmovs\tr4, #4\n+\tstr\tr4, [sp, #312]\t@ 0x138\n+\tstr\tr4, [sp, #300]\t@ 0x12c\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [sp, #332]\t@ 0x14c\n-\tstrh.w\tr4, [sp, #336]\t@ 0x150\n-\tmovs\tr4, #2\n-\tstr\tr4, [sp, #364]\t@ 0x16c\n+\tstrh.w\tr4, [sp, #308]\t@ 0x134\n \tmvn.w\tr4, #2\n-\tstr\tr4, [sp, #324]\t@ 0x144\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #212]\t@ (4108 <__gridxc_alloc_MOD_realloc_z2+0x578>)\n-\tldr\tr3, [pc, #212]\t@ (410c <__gridxc_alloc_MOD_realloc_z2+0x57c>)\n+\tstr\tr4, [sp, #296]\t@ 0x128\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #212]\t@ (3e9c <__gridxc_alloc_MOD_realloc_z2+0x518>)\n+\tldr\tr3, [pc, #172]\t@ (3e78 <__gridxc_alloc_MOD_realloc_z2+0x4f4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #372]\t@ 0x174\n+\tldr\tr3, [sp, #340]\t@ 0x154\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t40e4 <__gridxc_alloc_MOD_realloc_z2+0x554>\n-\tadd\tsp, #380\t@ 0x17c\n-\tvpop\t{d8-d9}\n+\tbne.n\t3e70 <__gridxc_alloc_MOD_realloc_z2+0x4ec>\n+\tadd\tsp, #348\t@ 0x15c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr2, [sp, #40]\t@ 0x28\n-\tadd\tr0, sp, #108\t@ 0x6c\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #64]\t@ 0x40\n+\tadd\tr0, sp, #80\t@ 0x50\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr1, [sp, #52]\t@ 0x34\n \tsubs\tr3, r3, r2\n \tldr\tr2, [sp, #44]\t@ 0x2c\n \tadds\tr3, #1\n-\tldr\tr7, [sp, #32]\n+\tstr\tr5, [sp, #0]\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #172]\t@ (4110 <__gridxc_alloc_MOD_realloc_z2+0x580>)\n+\tldr\tr5, [sp, #28]\n \tadds\tr2, #1\n \tbic.w\tr3, r3, r3, asr #31\n-\tcmp\tr7, #0\n-\tadd\tr1, pc\n+\tcmp\tr5, #0\n+\tldr\tr1, [pc, #160]\t@ (3ea0 <__gridxc_alloc_MOD_realloc_z2+0x51c>)\n \tbic.w\tr2, r2, r2, asr #31\n+\tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #32]\n \tmov.w\tr3, r3, lsl #1\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr\tr3, [sp, #452]\t@ 0x1c4\n+\tldr\tr3, [sp, #404]\t@ 0x194\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr2, #0\n \tstr\tr3, [sp, #4]\n-\tmov.w\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #456]\t@ 0x1c8\n+\tldr\tr3, [sp, #408]\t@ 0x198\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r2\n-\tmov\tr2, r7\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tmov\tr2, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr\tr6, [r4, #16]\n-\tstr\tr6, [sp, #36]\t@ 0x24\n-\tb.n\t3d06 <__gridxc_alloc_MOD_realloc_z2+0x176>\n-\tmovs\tr7, #1\n+\tstr\tr7, [r6, #16]\n+\tstr\tr7, [sp, #36]\t@ 0x24\n+\tb.n\t3ae6 <__gridxc_alloc_MOD_realloc_z2+0x162>\n+\tmovs\tr5, #1\n \tcmp.w\tip, #0\n-\tstr\tr7, [sp, #160]\t@ 0xa0\n+\tstr\tr5, [sp, #132]\t@ 0x84\n \tmov.w\tip, #0\n-\tbge.w\t3c24 <__gridxc_alloc_MOD_realloc_z2+0x94>\n+\tbge.w\t3a22 <__gridxc_alloc_MOD_realloc_z2+0x9e>\n \tmov.w\tlr, #0\n-\tb.n\t3c2a <__gridxc_alloc_MOD_realloc_z2+0x9a>\n-\tmovs\tr7, #1\n+\tb.n\t3a28 <__gridxc_alloc_MOD_realloc_z2+0xa4>\n+\tmovs\tr5, #1\n \tmov.w\tlr, #0\n-\tb.n\t3c2a <__gridxc_alloc_MOD_realloc_z2+0x9a>\n-\tmov\tr0, r2\n-\tcmp\tr2, #0\n-\tbeq.w\t3d8a <__gridxc_alloc_MOD_realloc_z2+0x1fa>\n+\tb.n\t3a28 <__gridxc_alloc_MOD_realloc_z2+0xa4>\n+\tmov\tr0, r6\n+\tcmp\tr6, #0\n+\tbeq.w\t3b66 <__gridxc_alloc_MOD_realloc_z2+0x1e2>\n \tmovs\tr0, #1\n-\tb.n\t3d90 <__gridxc_alloc_MOD_realloc_z2+0x200>\n+\tb.n\t3b6c <__gridxc_alloc_MOD_realloc_z2+0x1e8>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t3dbc <__gridxc_alloc_MOD_realloc_z2+0x22c>\n+\tb.n\t3ba2 <__gridxc_alloc_MOD_realloc_z2+0x21e>\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t3dbc <__gridxc_alloc_MOD_realloc_z2+0x22c>\n+\tb.n\t3ba2 <__gridxc_alloc_MOD_realloc_z2+0x21e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000134\n+\t.word\t0x000004d0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000004c0\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003dc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000398\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002da\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000264\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x000001f6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000128\n R_ARM_REL32\t.LC27\n-\t.word\t0x0000010a\n+\t.word\t0x00000110\n R_ARM_REL32\t.bss\n \t.word\t0x000000ce\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000a0\n+\t.word\t0x0000009a\n R_ARM_REL32\t.LC27\n \n-00004114 <__gridxc_alloc_MOD_realloc_z1>:\n+00003ea4 <__gridxc_alloc_MOD_realloc_z1>:\n __gridxc_alloc_MOD_realloc_z1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n-\tldr.w\tip, [pc, #900]\t@ 44b0 <__gridxc_alloc_MOD_realloc_z1+0x39c>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #900]\t@ (44b4 <__gridxc_alloc_MOD_realloc_z1+0x3a0>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tlr, [pc, #896]\t@ 44b8 <__gridxc_alloc_MOD_realloc_z1+0x3a4>\n+\tldr.w\tr0, [pc, #1128]\t@ 4320 <__gridxc_alloc_MOD_realloc_z1+0x47c>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1124]\t@ 4324 <__gridxc_alloc_MOD_realloc_z1+0x480>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1116]\t@ 4328 <__gridxc_alloc_MOD_realloc_z1+0x484>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #328]\t@ 0x148\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #336]\t@ 0x150\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t4458 <__gridxc_alloc_MOD_realloc_z1+0x344>\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldrd\tr3, r2, [r4, #28]\n-\tstr\tr3, [r7, #24]\n-\tstr\tr2, [r7, #16]\n-\tcmp\tr2, r3\n+\titet\teq\n+\tstreq\tr3, [r7, #16]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t3f1e <__gridxc_alloc_MOD_realloc_z1+0x7a>\n+\tstr\tr3, [r7, #32]\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n-\tstr\tr3, [r7, #0]\n-\tldr\tr3, [r4, #24]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #16]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #760]\t@ 4490 <__gridxc_alloc_MOD_realloc_z1+0x37c>\n-\tvldr\td19, [pc, #764]\t@ 4498 <__gridxc_alloc_MOD_realloc_z1+0x384>\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #244\t@ 0xf4\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #100\t@ 0x64\n-\tvldr\td17, [pc, #752]\t@ 44a0 <__gridxc_alloc_MOD_realloc_z1+0x38c>\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #92]\t@ 0x5c\n-\tadd.w\tsl, r7, #64\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #116\t@ 0x74\n-\tldr.w\tr9, [pc, #748]\t@ 44bc <__gridxc_alloc_MOD_realloc_z1+0x3a8>\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tadd.w\tr1, r7, #128\t@ 0x80\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #148\t@ 0x94\n-\tvstr\td16, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #220\t@ 0xdc\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #924]\t@ 432c <__gridxc_alloc_MOD_realloc_z1+0x488>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n \tadd\tr9, pc\n-\tvstr\td16, [r7, #184]\t@ 0xb8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #164\t@ 0xa4\n-\tvstr\td16, [r7, #188]\t@ 0xbc\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #196\t@ 0xc4\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tstr\tr2, [r7, #32]\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #212\t@ 0xd4\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tvst1.32\t{d18-d19}, [fp]\n-\tstr\tr3, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #124]\t@ 0x7c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tadd.w\tr3, r7, #48\t@ 0x30\n-\tstr.w\tr8, [r7, #172]\t@ 0xac\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n-\tstr\tr3, [r7, #20]\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tadd.w\tr2, r7, #176\t@ 0xb0\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #80\t@ 0x50\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 42d6 <__gridxc_alloc_MOD_realloc_z1+0x1c2>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #8]\n-\tcmp\tr3, #0\n-\tbne.n\t4310 <__gridxc_alloc_MOD_realloc_z1+0x1fc>\n-\tldr\tr2, [r7, #16]\n+\tcbz\tr3, 404c <__gridxc_alloc_MOD_realloc_z1+0x1a8>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t4082 <__gridxc_alloc_MOD_realloc_z1+0x1de>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #24]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #556]\t@ (44c0 <__gridxc_alloc_MOD_realloc_z1+0x3ac>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #808]\t@ (4330 <__gridxc_alloc_MOD_realloc_z1+0x48c>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \tlsl.w\tr3, r3, r8\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #8]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr3, [pc, #492]\t@ (44c4 <__gridxc_alloc_MOD_realloc_z1+0x3b0>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #740]\t@ (4334 <__gridxc_alloc_MOD_realloc_z1+0x490>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 431a <__gridxc_alloc_MOD_realloc_z1+0x206>\n-\tldr\tr3, [pc, #488]\t@ (44c8 <__gridxc_alloc_MOD_realloc_z1+0x3b4>)\n+\tcbnz\tr3, 408c <__gridxc_alloc_MOD_realloc_z1+0x1e8>\n+\tldr\tr3, [pc, #736]\t@ (4338 <__gridxc_alloc_MOD_realloc_z1+0x494>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t445c <__gridxc_alloc_MOD_realloc_z1+0x348>\n-\tldr\tr2, [pc, #480]\t@ (44cc <__gridxc_alloc_MOD_realloc_z1+0x3b8>)\n-\tldr\tr3, [pc, #452]\t@ (44b4 <__gridxc_alloc_MOD_realloc_z1+0x3a0>)\n+\tbne.w\t41b0 <__gridxc_alloc_MOD_realloc_z1+0x30c>\n+\tldr\tr2, [pc, #728]\t@ (433c <__gridxc_alloc_MOD_realloc_z1+0x498>)\n+\tldr\tr3, [pc, #704]\t@ (4324 <__gridxc_alloc_MOD_realloc_z1+0x480>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4612 <__gridxc_alloc_MOD_realloc_z1+0x4fe>\n-\tadd.w\tr7, r7, #284\t@ 0x11c\n+\tbne.w\t430e <__gridxc_alloc_MOD_realloc_z1+0x46a>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t445c <__gridxc_alloc_MOD_realloc_z1+0x348>\n-\tvldr\td8, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t41b0 <__gridxc_alloc_MOD_realloc_z1+0x30c>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #16\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #1025\t@ 0x401\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #268435456\t@ 0x10000000\n-\tbge.w\t461c <__gridxc_alloc_MOD_realloc_z1+0x508>\n+\tbge.w\t4318 <__gridxc_alloc_MOD_realloc_z1+0x474>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #4\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t4616 <__gridxc_alloc_MOD_realloc_z1+0x502>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #316]\t@ 44a8 <__gridxc_alloc_MOD_realloc_z1+0x394>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t4312 <__gridxc_alloc_MOD_realloc_z1+0x46e>\n+\tmovs\tr3, #16\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #336]\t@ (44d0 <__gridxc_alloc_MOD_realloc_z1+0x3bc>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #28]\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #608]\t@ (4340 <__gridxc_alloc_MOD_realloc_z1+0x49c>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #276]\t@ 44a0 <__gridxc_alloc_MOD_realloc_z1+0x38c>\n-\tvldr\td18, [pc, #256]\t@ 4490 <__gridxc_alloc_MOD_realloc_z1+0x37c>\n-\tvldr\td19, [pc, #260]\t@ 4498 <__gridxc_alloc_MOD_realloc_z1+0x384>\n-\tvstr\td17, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tr1, r5\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n \tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #240]\t@ 0xf0\n-\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n \tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #32]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #224]\t@ (44d4 <__gridxc_alloc_MOD_realloc_z1+0x3c0>)\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #504]\t@ (4344 <__gridxc_alloc_MOD_realloc_z1+0x4a0>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tlsl.w\tr3, r3, r8\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tlsl.w\tr3, r3, r9\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r4, #24]\n-\tldrd\tlr, r2, [r4, #28]\n-\tldrd\tr3, r1, [r4]\n-\tcmp\tlr, r2\n-\tbgt.w\t42de <__gridxc_alloc_MOD_realloc_z1+0x1ca>\n-\tmla\tr1, r0, lr, r1\n-\tadd.w\tip, r2, r8\n-\tldr\tr2, [r4, #20]\n-\tsub.w\tip, ip, lr\n-\tmla\tr3, r2, r1, r3\n-\tmovs\tr1, #0\n-\tmul.w\tlr, r0, r2\n-\tmovs\tr2, #0\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr.w\tip, [r4, #24]\n+\tldrd\tr1, r2, [r4, #28]\n+\tldrd\tr3, r0, [r4]\n+\tcmp\tr1, r2\n+\tbgt.w\t4054 <__gridxc_alloc_MOD_realloc_z1+0x1b0>\n+\tadd\tr2, r9\n+\tmla\tr0, ip, r1, r0\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [r4, #20]\n+\tmla\tr3, r1, r0, r3\n \tmovs\tr0, #0\n-\tadds\tr2, #1\n+\tmul.w\tip, ip, r1\n+\tmovs\tr1, #0\n+\tadd.w\tr8, r8, #1\n \tstrd\tr0, r1, [r3]\n \tstrd\tr0, r1, [r3, #8]\n-\tcmp\tr2, ip\n-\tadd\tr3, lr\n-\tbne.n\t4446 <__gridxc_alloc_MOD_realloc_z1+0x332>\n-\tb.n\t42de <__gridxc_alloc_MOD_realloc_z1+0x1ca>\n-\tstr\tr3, [r7, #12]\n-\tb.n\t4190 <__gridxc_alloc_MOD_realloc_z1+0x7c>\n-\tldrd\tr9, r1, [r7, #56]\t@ 0x38\n-\tmov\tsl, sp\n+\tcmp\tr2, r8\n+\tadd\tr3, ip\n+\tbne.n\t419c <__gridxc_alloc_MOD_realloc_z1+0x2f8>\n+\tb.n\t4054 <__gridxc_alloc_MOD_realloc_z1+0x1b0>\n+\tldrd\tr9, r1, [r7, #52]\t@ 0x34\n+\tmov\tfp, sp\n \tsubs.w\tr1, r1, r9\n-\tbmi.n\t4554 <__gridxc_alloc_MOD_realloc_z1+0x440>\n+\tbmi.n\t425a <__gridxc_alloc_MOD_realloc_z1+0x3b6>\n \tlsls\tr3, r1, #4\n \tldr\tr2, [r4, #0]\n \tadds\tr3, #16\n-\tstr\tr2, [r7, #8]\n+\tstr\tr2, [r7, #12]\n \tbic.w\tr0, r3, #4080\t@ 0xff0\n \tldr\tr2, [r4, #4]\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n \tmov\tip, sp\n \tcmp\tip, r0\n-\tbeq.n\t44d8 <__gridxc_alloc_MOD_realloc_z1+0x3c4>\n+\tbeq.n\t41e2 <__gridxc_alloc_MOD_realloc_z1+0x33e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t447e <__gridxc_alloc_MOD_realloc_z1+0x36a>\n-\tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000010\n-\t.word\t0x00000001\n-\t.word\t0x0000037a\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000372\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002d2\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000226\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000001e8\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001da\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000144\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000da\n- R_ARM_REL32\t.LC27\n+\tb.n\t41d2 <__gridxc_alloc_MOD_realloc_z1+0x32e>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 44e8 <__gridxc_alloc_MOD_realloc_z1+0x3d4>\n+\tcbz\tr3, 41f2 <__gridxc_alloc_MOD_realloc_z1+0x34e>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldrd\tr0, r3, [r7]\n+\tldrd\tr0, r3, [r7, #4]\n+\tldr.w\tsl, [r4, #24]\n \tmla\tip, r9, r3, r0\n-\tldr\tr0, [r7, #12]\n+\tldr\tr0, [r7, #16]\n \tmul.w\tr8, r0, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #32]\n \tmla\tip, r0, ip, r3\n-\tldr\tr3, [r4, #24]\n \tadd\tr0, sp, #16\n-\tstr\tr3, [r7, #12]\n \tmov\tlr, r0\n \tmovs\tr3, #0\n-\tvldr\td16, [ip, #8]\n+\tvldr\td7, [ip, #8]\n \tadds\tr3, #1\n \tadd.w\tlr, lr, #16\n \tcmp\tr3, r1\n-\tvstr\td16, [lr, #-8]\n-\tvldr\td16, [ip]\n+\tvstr\td7, [lr, #-8]\n+\tvldr\td7, [ip]\n \tadd\tip, r8\n-\tvstr\td16, [lr, #-16]\n-\tble.n\t4506 <__gridxc_alloc_MOD_realloc_z1+0x3f2>\n-\tldr\tr3, [r7, #12]\n-\tmov.w\tip, #0\n-\tmla\tr2, r9, r3, r2\n+\tvstr\td7, [lr, #-16]\n+\tble.n\t4210 <__gridxc_alloc_MOD_realloc_z1+0x36c>\n \tldr\tr3, [r4, #20]\n-\tldr\tr4, [r7, #8]\n-\tmla\tr2, r3, r2, r4\n+\tmla\tr2, r9, sl, r2\n \tldr\tr4, [r7, #12]\n-\tmul.w\tr3, r4, r3\n+\tmov.w\tip, #0\n+\tmla\tr2, r3, r2, r4\n+\tmul.w\tr3, r3, sl\n \tldrd\tr8, r9, [r0, #8]\n \tstrd\tr8, r9, [r2, #8]\n \tldrd\tr8, r9, [r0], #16\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tstrd\tr8, r9, [r2]\n \tadd.w\tip, ip, #1\n \tadd\tr2, r3\n-\tbne.n\t453a <__gridxc_alloc_MOD_realloc_z1+0x426>\n-\tldr\tr2, [r7, #24]\n+\tbne.n\t4240 <__gridxc_alloc_MOD_realloc_z1+0x39c>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #16]\n-\tmov\tsp, sl\n-\tldr\tr1, [pc, #224]\t@ (4640 <__gridxc_alloc_MOD_realloc_z1+0x52c>)\n+\tldr\tr3, [r7, #20]\n+\tmov\tsp, fp\n+\tldr\tr1, [pc, #228]\t@ (4348 <__gridxc_alloc_MOD_realloc_z1+0x4a4>)\n \tmov.w\tr4, #1\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr2, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr.w\tr2, [r7, #344]\t@ 0x158\n+\tstr.w\tr2, [r7, #328]\t@ 0x148\n \tlsls\tr3, r3, #1\n \tadd\tr1, pc\n \tnegs\tr3, r3\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr\tr2, [sp, #8]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tmov\tr2, r5\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tcbz\tr3, 45b2 <__gridxc_alloc_MOD_realloc_z1+0x49e>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 42b8 <__gridxc_alloc_MOD_realloc_z1+0x414>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #136]\t@ (4644 <__gridxc_alloc_MOD_realloc_z1+0x530>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [pc, #144]\t@ (434c <__gridxc_alloc_MOD_realloc_z1+0x4a8>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #28]\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #96]\t@ 4628 <__gridxc_alloc_MOD_realloc_z1+0x514>\n-\tvldr\td19, [pc, #100]\t@ 4630 <__gridxc_alloc_MOD_realloc_z1+0x51c>\n-\tvldr\td17, [pc, #104]\t@ 4638 <__gridxc_alloc_MOD_realloc_z1+0x524>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tstrh.w\tr4, [r7, #240]\t@ 0xf0\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #228]\t@ 0xe4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tldr\tr3, [r7, #32]\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t42ea <__gridxc_alloc_MOD_realloc_z1+0x1d6>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t4060 <__gridxc_alloc_MOD_realloc_z1+0x1bc>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t437e <__gridxc_alloc_MOD_realloc_z1+0x26a>\n+\tb.n\t40dc <__gridxc_alloc_MOD_realloc_z1+0x238>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t437e <__gridxc_alloc_MOD_realloc_z1+0x26a>\n+\tb.n\t40dc <__gridxc_alloc_MOD_realloc_z1+0x238>\n \tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000b2\n+\t.word\t0x0000045c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000044c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000390\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000031e\n R_ARM_REL32\t.LC27\n-\t.word\t0x0000007c\n+\t.word\t0x000002e2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002de\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002d4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000254\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001f0\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x000000b4\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n \n-00004648 <__gridxc_alloc_MOD_realloc_d4>:\n+00004350 <__gridxc_alloc_MOD_realloc_d4>:\n __gridxc_alloc_MOD_realloc_d4():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3424]\t@ 0xd60\n-\tsub.w\tsp, sp, #604\t@ 0x25c\n+\tstr.w\tr0, [ip, #3528]\t@ 0xdc8\n+\tsub.w\tsp, sp, #532\t@ 0x214\n \tadd\tr7, sp, #16\n+\tmov\tr9, r2\n+\tldr.w\tr2, [pc, #1932]\t@ 4af8 <__gridxc_alloc_MOD_realloc_d4+0x7a8>\n \tmov\tr5, r0\n-\tmov\tr9, r3\n-\tldr.w\tr3, [pc, #1184]\t@ 4b08 <__gridxc_alloc_MOD_realloc_d4+0x4c0>\n-\tstrd\tr2, r1, [r7, #100]\t@ 0x64\n-\tldr.w\tr2, [pc, #1180]\t@ 4b0c <__gridxc_alloc_MOD_realloc_d4+0x4c4>\n-\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n \tadd\tr2, pc\n-\tstr\tr0, [r7, #96]\t@ 0x60\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n+\tldr.w\tr0, [r7, #552]\t@ 0x228\n+\tldr.w\tr3, [pc, #1924]\t@ 4afc <__gridxc_alloc_MOD_realloc_d4+0x7ac>\n \tstr\tr0, [r7, #88]\t@ 0x58\n+\tldr.w\tr0, [r7, #556]\t@ 0x22c\n+\tstr\tr0, [r7, #80]\t@ 0x50\n+\tstr\tr1, [r7, #96]\t@ 0x60\n \tldr\tr4, [r5, #0]\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n \tcmp\tr4, #0\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1144]\t@ 4b10 <__gridxc_alloc_MOD_realloc_d4+0x4c8>\n-\tstr\tr2, [r7, #84]\t@ 0x54\n+\tldr.w\tr3, [pc, #1892]\t@ 4b00 <__gridxc_alloc_MOD_realloc_d4+0x7b0>\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tit\tne\n+\tmovne\tr2, #1\n \tadd\tr3, pc\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tmov.w\tr2, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tstr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #564]\t@ 0x234\n \tstr\tr3, [r7, #72]\t@ 0x48\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tldr.w\tr3, [r7, #572]\t@ 0x23c\n+\tstr\tr3, [r7, #56]\t@ 0x38\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n \tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tstr\tr3, [r7, #40]\t@ 0x28\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tbeq.w\t4d9c <__gridxc_alloc_MOD_realloc_d4+0x754>\n+\tbeq.w\t4a56 <__gridxc_alloc_MOD_realloc_d4+0x706>\n \tmovs\tr2, #72\t@ 0x48\n \tmov\tr1, r5\n-\tadd.w\tr0, r7, #508\t@ 0x1fc\n+\tadd.w\tr0, r7, #436\t@ 0x1b4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tstr\tr4, [r7, #68]\t@ 0x44\n-\tldrd\tr4, r6, [r7, #536]\t@ 0x218\n-\tldrd\tr0, sl, [r7, #548]\t@ 0x224\n+\tstr\tr4, [r7, #60]\t@ 0x3c\n+\tldrd\tr4, r6, [r7, #464]\t@ 0x1d0\n+\tldrd\tr0, sl, [r7, #476]\t@ 0x1dc\n \tsubs.w\tr8, r6, r4\n-\tldr.w\tfp, [r7, #564]\t@ 0x234\n+\tldr.w\tfp, [r7, #492]\t@ 0x1ec\n \tit\tmi\n \tmovmi\tr4, #1\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n \tsubs.w\tlr, sl, r0\n-\tldr.w\tr2, [r7, #572]\t@ 0x23c\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n \tit\tmi\n \tmovmi\tr0, #1\n-\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n \tsubs.w\tip, fp, r1\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tstr\tr3, [r7, #100]\t@ 0x64\n \tit\tmi\n \tmovmi\tr1, #1\n \tsubs\tr3, r3, r2\n-\tstr.w\tr4, [r7, #280]\t@ 0x118\n+\tstr.w\tr4, [r7, #208]\t@ 0xd0\n \tit\tmi\n \tmovmi\tr2, #1\n \tcmp.w\tr8, #0\n \tit\tlt\n \tmovlt\tr6, #0\n \tcmp.w\tlr, #0\n-\tmov.w\tlr, #0\n-\tstr.w\tr2, [r7, #304]\t@ 0x130\n \tit\tlt\n-\tmovlt\tsl, lr\n-\tcmp\tip, lr\n+\tmovlt.w\tsl, #0\n+\tcmp.w\tip, #0\n \tit\tlt\n-\tmovlt\tfp, lr\n-\tcmp\tr3, lr\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n+\tmovlt.w\tfp, #0\n+\tcmp\tr3, #0\n+\tldr\tr3, [r7, #100]\t@ 0x64\n \tit\tlt\n-\tmovlt\tr3, lr\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tadd.w\tr3, r7, #280\t@ 0x118\n-\tstr\tr3, [r7, #52]\t@ 0x34\n+\tmovlt\tr3, #0\n+\tstr\tr3, [r7, #100]\t@ 0x64\n+\tadd.w\tr3, r7, #208\t@ 0xd0\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r5, #4]\n-\tstr\tr3, [r7, #28]\n+\tstr\tr3, [r7, #20]\n \tldr\tr3, [r5, #24]\n-\tldr\tr2, [r7, #108]\t@ 0x6c\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr.w\tr2, [r7, #232]\t@ 0xe8\n+\tstr\tr3, [r7, #24]\n+\tldr\tr2, [r7, #100]\t@ 0x64\n \tldr\tr3, [r5, #20]\n-\tstr.w\tr0, [r7, #288]\t@ 0x120\n-\tstr.w\tr1, [r7, #296]\t@ 0x128\n-\tstr.w\tr6, [r7, #284]\t@ 0x11c\n-\tstr.w\tsl, [r7, #292]\t@ 0x124\n-\tstr.w\tfp, [r7, #300]\t@ 0x12c\n-\tstr.w\tr2, [r7, #308]\t@ 0x134\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n-\tldr\tr3, [r7, #88]\t@ 0x58\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr6, [r7, #100]\t@ 0x64\n-\tldr.w\tlr, [r9]\n-\tldr\tr4, [r3, #0]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tstr.w\tr0, [r7, #216]\t@ 0xd8\n+\tstr.w\tr1, [r7, #224]\t@ 0xe0\n+\tstr.w\tr6, [r7, #212]\t@ 0xd4\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstr.w\tfp, [r7, #228]\t@ 0xe4\n+\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tstr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr2, [r7, #80]\t@ 0x50\n+\tadd.w\tr8, r7, #176\t@ 0xb0\n+\tldr\tr6, [r7, #76]\t@ 0x4c\n+\tmvn.w\tsl, #2\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tadd.w\tfp, r7, #344\t@ 0x158\n+\tldr\tr1, [r2, #0]\n+\tldr\tr2, [r7, #72]\t@ 0x48\n \tldr.w\tip, [r6]\n-\tldr\tr6, [r7, #96]\t@ 0x60\n-\tldr\tr0, [r3, #0]\n-\tldr\tr3, [r7, #80]\t@ 0x50\n-\tldr.w\tr8, [r6]\n-\tadd.w\tr6, r7, #216\t@ 0xd8\n-\tvldr\td18, [pc, #856]\t@ 4ae8 <__gridxc_alloc_MOD_realloc_d4+0x4a0>\n-\tvldr\td19, [pc, #860]\t@ 4af0 <__gridxc_alloc_MOD_realloc_d4+0x4a8>\n-\tvstr\td16, [r7, #320]\t@ 0x140\n-\tldr\tr1, [r3, #0]\n-\tldr\tr3, [r7, #72]\t@ 0x48\n-\tvldr\td17, [pc, #856]\t@ 4af8 <__gridxc_alloc_MOD_realloc_d4+0x4b0>\n-\tvstr\td16, [r7, #324]\t@ 0x144\n-\tldr\tr2, [r3, #0]\n-\tldr\tr3, [r7, #104]\t@ 0x68\n-\tvstr\td16, [r7, #368]\t@ 0x170\n-\tvstr\td16, [r7, #372]\t@ 0x174\n+\tldr\tr4, [r7, #88]\t@ 0x58\n+\tldr\tr0, [r2, #0]\n+\tldr\tr6, [r7, #68]\t@ 0x44\n+\tldr\tr2, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r8, #24]\n+\tadd.w\tr0, r7, #240\t@ 0xf0\n+\tldr.w\tlr, [r6]\n \tldr\tr3, [r3, #0]\n-\tstrd\tr4, r0, [r7, #160]\t@ 0xa0\n-\tadd.w\tr0, r7, #312\t@ 0x138\n-\tstrd\tr1, r2, [r7, #168]\t@ 0xa8\n-\tadd.w\tr2, r7, #492\t@ 0x1ec\n-\tstrd\tr3, ip, [r7, #144]\t@ 0x90\n-\tadd.w\tr3, r7, #332\t@ 0x14c\n-\tvldr\td20, [r7, #160]\t@ 0xa0\n-\tvldr\td21, [r7, #168]\t@ 0xa8\n-\tstrd\tlr, r8, [r7, #152]\t@ 0x98\n-\tadd.w\tr1, r7, #456\t@ 0x1c8\n-\tldr.w\tr8, [pc, #820]\t@ 4b14 <__gridxc_alloc_MOD_realloc_d4+0x4cc>\n-\tvstr\td20, [r7, #200]\t@ 0xc8\n-\tvstr\td21, [r7, #208]\t@ 0xd0\n-\tadd\tr8, pc\n-\tvldr\td20, [r7, #144]\t@ 0x90\n-\tvldr\td21, [r7, #152]\t@ 0x98\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #348\t@ 0x15c\n-\tvstr\td20, [r7, #184]\t@ 0xb8\n-\tvstr\td21, [r7, #192]\t@ 0xc0\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #380\t@ 0x17c\n-\tstr\tr2, [r7, #44]\t@ 0x2c\n-\tmovs\tr2, #4\n-\tldr\tr4, [r7, #52]\t@ 0x34\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #396\t@ 0x18c\n-\tstr\tr1, [r7, #56]\t@ 0x38\n-\tadd.w\tr1, r7, #248\t@ 0xf8\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #476\t@ 0x1dc\n-\tstr\tr1, [r7, #108]\t@ 0x6c\n+\tldr.w\tr6, [r9]\n+\tadd.w\tr9, r7, #112\t@ 0x70\n+\tldr\tr2, [r2, #0]\n+\tldr\tr4, [r4, #0]\n+\tstr.w\tr2, [r8]\n+\tadd.w\tr2, r7, #336\t@ 0x150\n+\tstr.w\tr3, [r8, #8]\n+\tadd.w\tr3, r7, #384\t@ 0x180\n+\tstr.w\tr1, [r8, #16]\n+\tadd.w\tr1, r7, #288\t@ 0x120\n \tstr\tr3, [r7, #48]\t@ 0x30\n-\tmvn.w\tr3, #2\n-\tstr.w\tr1, [r7, #360]\t@ 0x168\n-\tadd.w\tr1, r7, #428\t@ 0x1ac\n-\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tstr\tr3, [r0, #4]\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tstr.w\tr3, [r7, #364]\t@ 0x16c\n-\tstr.w\tr2, [r7, #452]\t@ 0x1c4\n-\tstrd\tr4, r3, [r7, #408]\t@ 0x198\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tvst1.32\t{d18-d19}, [r1]\n-\tadd.w\tr1, r7, #444\t@ 0x1bc\n-\tvstr\td16, [r7, #464]\t@ 0x1d0\n-\tvstr\td16, [r7, #468]\t@ 0x1d4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tvst1.32\t{d17}, [r2]\n-\tadd.w\tr2, r7, #184\t@ 0xb8\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tstr.w\tr2, [r7, #456]\t@ 0x1c8\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tvst1.32\t{d17}, [r1]\n-\tadd.w\tr1, r7, #360\t@ 0x168\n-\tvstr\td16, [r7, #416]\t@ 0x1a0\n-\tstr\tr6, [r0, #0]\n-\tvstr\td16, [r7, #420]\t@ 0x1a4\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #408\t@ 0x198\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tbl\t644 <__gridxc_alloc_MOD_options.constprop.3>\n-\tldr.w\tr3, [r8, #8]\n-\tcbz\tr3, 48ae <__gridxc_alloc_MOD_realloc_d4+0x266>\n-\tldr.w\tsl, [r8, #12]\n-\tcmp.w\tsl, #0\n-\tbeq.w\t4da6 <__gridxc_alloc_MOD_realloc_d4+0x75e>\n-\tldr\tr3, [pc, #616]\t@ (4b18 <__gridxc_alloc_MOD_realloc_d4+0x4d0>)\n+\tstr.w\tr6, [r8, #4]\n+\tmovs\tr6, #1\n+\tstr.w\tr4, [r8, #12]\n+\tmovs\tr4, #0\n+\tstr.w\tip, [r8, #20]\n+\tmov.w\tip, #2\n+\tstr.w\tlr, [r8, #28]\n+\tmov.w\tlr, #4\n+\tstrd\tr4, r4, [r7, #248]\t@ 0xf8\n+\tstr.w\tr4, [r7, #256]\t@ 0x100\n+\tstrd\tr4, r4, [r7, #296]\t@ 0x128\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n+\tstrd\tr6, r6, [r0, #24]\n+\tstr\tr6, [r0, #40]\t@ 0x28\n+\tstr.w\tr4, [r7, #344]\t@ 0x158\n+\tstrd\tr4, r4, [r7, #348]\t@ 0x15c\n+\tldr\tr4, [r7, #44]\t@ 0x2c\n+\tstr.w\tsl, [r0, #4]\n+\tstrd\tr4, sl, [r7, #336]\t@ 0x150\n+\tmovs\tr4, #0\n+\tstr.w\tsl, [r7, #292]\t@ 0x124\n+\tstr.w\tsl, [r7, #388]\t@ 0x184\n+\tldr.w\tsl, [pc, #1516]\t@ 4b04 <__gridxc_alloc_MOD_realloc_d4+0x7b4>\n+\tstr.w\tlr, [r0, #20]\n+\tstr.w\tlr, [r0, #44]\t@ 0x2c\n+\tadd\tsl, pc\n+\tstr.w\tlr, [r7, #308]\t@ 0x134\n+\tstrd\tip, ip, [r0, #32]\n+\tstr.w\tr9, [r0]\n+\tstrd\tr6, ip, [r7, #316]\t@ 0x13c\n+\tstrd\tr6, lr, [r7, #328]\t@ 0x148\n+\tstr.w\tip, [r7, #324]\t@ 0x144\n+\tstr.w\tlr, [r7, #356]\t@ 0x164\n+\tstrd\tr6, ip, [r7, #364]\t@ 0x16c\n+\tstrd\tr6, lr, [r7, #376]\t@ 0x178\n+\tstr.w\tip, [r7, #372]\t@ 0x174\n+\tstr.w\tlr, [r7, #404]\t@ 0x194\n+\tstr.w\tlr, [r7, #428]\t@ 0x1ac\n+\tstrd\tr4, r4, [r7, #392]\t@ 0x188\n+\tstr.w\tr6, [r7, #312]\t@ 0x138\n+\tstr.w\tr6, [r7, #360]\t@ 0x168\n+\tstr.w\tr4, [r7, #400]\t@ 0x190\n+\tadd.w\tr4, r7, #144\t@ 0x90\n+\tstr\tr4, [r7, #100]\t@ 0x64\n+\tstr.w\tr4, [r7, #288]\t@ 0x120\n+\tldr\tr4, [r7, #40]\t@ 0x28\n+\tstrd\tr6, ip, [r7, #412]\t@ 0x19c\n+\tstr.w\tip, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr6, [r7, #408]\t@ 0x198\n+\tstr.w\tr6, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr8, [r7, #384]\t@ 0x180\n+\tstr\tr4, [sp, #4]\n+\tldr\tr4, [r7, #64]\t@ 0x40\n+\tstr\tr4, [sp, #0]\n+\tbl\t618 <__gridxc_alloc_MOD_options.constprop.3>\n+\tldr.w\tr3, [sl, #8]\n+\tcbz\tr3, 45a0 <__gridxc_alloc_MOD_realloc_d4+0x250>\n+\tldr.w\tfp, [sl, #12]\n+\tcmp.w\tfp, #0\n+\tbeq.w\t4a60 <__gridxc_alloc_MOD_realloc_d4+0x710>\n+\tldr.w\tr3, [pc, #1380]\t@ 4b08 <__gridxc_alloc_MOD_realloc_d4+0x7b8>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t4be4 <__gridxc_alloc_MOD_realloc_d4+0x59c>\n-\tldrd\tlr, r3, [r6]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tfp, r1, [r6, #8]\n-\tsub.w\tr2, r3, lr\n-\tstr\tr2, [r7, #104]\t@ 0x68\n-\tsub.w\tr0, r1, fp\n-\torr.w\tip, r2, r2, asr #31\n-\tvstr\td16, [r5, #12]\n-\tadd.w\tip, ip, #1\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\torr.w\tr2, r0, r0, asr #31\n-\tstr.w\tlr, [r7, #128]\t@ 0x80\n-\tmovs\tr3, #8\n-\tstr.w\tfp, [r7, #140]\t@ 0x8c\n-\tadds\tr2, #1\n-\tstr.w\tip, [r7, #136]\t@ 0x88\n-\tvldr\td10, [r7, #128]\t@ 0x80\n-\tvldr\td11, [r7, #136]\t@ 0x88\n+\tbeq.w\t48aa <__gridxc_alloc_MOD_realloc_d4+0x55a>\n+\tldr.w\tr2, [r9, #4]\n+\tldr.w\tr6, [r9, #8]\n+\tldr.w\tr1, [r9]\n+\tldr.w\tr0, [r9, #12]\n+\tstr\tr1, [r7, #96]\t@ 0x60\n+\tsubs\tr1, r2, r1\n+\tstr\tr0, [r7, #64]\t@ 0x40\n+\tsubs\tr0, r0, r6\n+\torr.w\tr3, r1, r1, asr #31\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\torr.w\tsl, r0, r0, asr #31\n+\tmovs\tr2, #0\n+\tstr\tr6, [r7, #92]\t@ 0x5c\n+\tadds.w\tsl, sl, #1\n+\tadd.w\tr6, r3, #1\n+\tstrd\tr2, r2, [r5, #12]\n+\tmov.w\tr3, #8\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tstr\tr3, [r5, #8]\n \tmov.w\tr3, #772\t@ 0x304\n+\tstr\tr0, [r7, #40]\t@ 0x28\n \tstrh\tr3, [r5, #16]\n-\tbeq.w\t4fe4 <__gridxc_alloc_MOD_realloc_d4+0x99c>\n-\tmvn.w\tr8, #2147483648\t@ 0x80000000\n-\tudiv\tr8, r8, r2\n-\tcmp\tr8, ip\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr8, r3\n-\tldrd\tr9, sl, [r6, #16]\n-\tmul.w\tr2, r2, ip\n-\tstrd\tr1, r2, [r7, #112]\t@ 0x70\n-\tsub.w\tr3, sl, r9\n-\tstrd\tr9, sl, [r7, #120]\t@ 0x78\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\torr.w\tr3, r3, r3, asr #31\n-\tvldr\td8, [r7, #112]\t@ 0x70\n-\tvldr\td9, [r7, #120]\t@ 0x78\n-\tadds\tr3, #1\n-\tbeq.n\t4954 <__gridxc_alloc_MOD_realloc_d4+0x30c>\n-\tmvn.w\tr1, #2147483648\t@ 0x80000000\n-\tmov\tr4, r8\n-\tudiv\tr1, r1, r3\n-\tcmp\tr1, r2\n+\tbeq.w\t4cd6 <__gridxc_alloc_MOD_realloc_d4+0x986>\n+\tmov\tr1, sl\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r6\n+\tite\tge\n+\tmovge.w\tfp, #0\n+\tmovlt.w\tfp, #1\n+\tldr.w\tr3, [r9, #20]\n+\tmul.w\tsl, sl, r6\n+\tldr.w\tr2, [r9, #16]\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tsubs\tr3, r3, r2\n+\tstr\tr2, [r7, #88]\t@ 0x58\n+\tstr\tr3, [r7, #32]\n+\torr.w\tr1, r3, r3, asr #31\n+\tadds\tr1, #1\n+\tbeq.n\t463a <__gridxc_alloc_MOD_realloc_d4+0x2ea>\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr1, [r7, #80]\t@ 0x50\n+\tcmp\tr0, sl\n \tit\tlt\n-\taddlt\tr4, #1\n-\tmov\tr8, r4\n-\tmul.w\tsl, r3, r2\n-\tldr\tr3, [r6, #28]\n-\tldr\tr6, [r6, #24]\n-\tstr\tr3, [r7, #96]\t@ 0x60\n-\tsubs\tr3, r3, r6\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\torr.w\tr3, r3, r3, asr #31\n+\taddlt.w\tfp, fp, #1\n+\tldr.w\tr3, [r9, #28]\n+\tmul.w\tr0, r1, sl\n+\tldr.w\tr2, [r9, #24]\n+\tstr\tr2, [r7, #80]\t@ 0x50\n+\tmov\tr4, r0\n+\tsubs\tr2, r3, r2\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n+\torr.w\tr3, r2, r2, asr #31\n \tadds\tr3, #1\n-\tbeq.n\t498a <__gridxc_alloc_MOD_realloc_d4+0x342>\n-\tmvn.w\tr1, #2147483648\t@ 0x80000000\n-\tmov\tr4, r8\n-\tudiv\tr1, r1, r3\n-\tmul.w\tr3, r3, sl\n-\tcmp\tr1, sl\n+\tbeq.n\t4680 <__gridxc_alloc_MOD_realloc_d4+0x330>\n+\tmov\tr1, r3\n+\tmul.w\tr3, r0, r3\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr2, [r7, #12]\n+\tstr\tr3, [r7, #16]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #16]\n+\tcmp\tr0, r4\n \tit\tlt\n-\taddlt\tr4, #1\n+\taddlt.w\tfp, fp, #1\n+\tldr\tr2, [r7, #12]\n \tcmp.w\tr3, #536870912\t@ 0x20000000\n-\tmov\tr1, r4\n \tit\tge\n-\taddge\tr1, #1\n-\tmov\tr8, r1\n-\tldr\tr1, [r7, #104]\t@ 0x68\n+\taddge.w\tfp, fp, #1\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tldr\tr4, [r7, #92]\t@ 0x5c\n \torrs\tr1, r0\n-\tmov\tr0, r1\n-\tldr\tr1, [r7, #100]\t@ 0x64\n-\torrs\tr0, r1\n-\trsb\tr1, lr, #0\n-\tmls\tr1, ip, fp, r1\n-\tmls\tr1, r2, r9, r1\n-\tldr\tr2, [r7, #88]\t@ 0x58\n-\tmls\tfp, sl, r6, r1\n-\torrs\tr0, r2\n-\tit\tpl\n+\tldr\tr0, [r7, #32]\n+\torr.w\tip, r1, r0\n+\tldr\tr0, [r7, #96]\t@ 0x60\n+\tnegs\tr0, r0\n+\tmls\tr0, r6, r4, r0\n+\tldr\tr4, [r7, #88]\t@ 0x58\n+\tmls\tr0, sl, r4, r0\n+\tldrd\tr1, r4, [r7, #76]\t@ 0x4c\n+\tmls\tr9, r1, r4, r0\n+\torrs.w\tr1, ip, r2\n+\tite\tpl\n \tlslpl\tr3, r3, #3\n-\tit\tmi\n \tmovmi\tr3, #0\n-\tcmp.w\tr8, #0\n-\tbne.w\t4fde <__gridxc_alloc_MOD_realloc_d4+0x996>\n+\tcmp.w\tfp, #0\n+\tbne.w\t4cd0 <__gridxc_alloc_MOD_realloc_d4+0x980>\n \tcmp\tr3, #1\n \tit\tcc\n \tmovcc\tr3, #1\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r5, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t4fec <__gridxc_alloc_MOD_realloc_d4+0x9a4>\n-\tadd.w\tr3, r5, #28\n-\tvldr\td16, [pc, #300]\t@ 4b00 <__gridxc_alloc_MOD_realloc_d4+0x4b8>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r5, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n+\tbeq.w\t4cde <__gridxc_alloc_MOD_realloc_d4+0x98e>\n \tldr\tr3, [r7, #96]\t@ 0x60\n+\tmovs\tr2, #1\n+\tstr\tr3, [r5, #28]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r5, #32]\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tstr\tr3, [r5, #40]\t@ 0x28\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r5, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #88]\t@ 0x58\n+\tstr\tr3, [r5, #52]\t@ 0x34\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r5, #56]\t@ 0x38\n+\tldr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r5, #64]\t@ 0x40\n+\tldr\tr3, [r7, #28]\n \tstr\tr3, [r5, #68]\t@ 0x44\n-\tadd.w\tr3, r5, #20\n-\tstr\tr6, [r5, #64]\t@ 0x40\n-\tstr.w\tsl, [r5, #60]\t@ 0x3c\n-\tstr.w\tfp, [r5, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvldr\td18, [pc, #228]\t@ 4ae8 <__gridxc_alloc_MOD_realloc_d4+0x4a0>\n-\tvldr\td19, [pc, #232]\t@ 4af0 <__gridxc_alloc_MOD_realloc_d4+0x4a8>\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tvstr\td17, [r7, #468]\t@ 0x1d4\n-\tvldr\td16, [pc, #232]\t@ 4af8 <__gridxc_alloc_MOD_realloc_d4+0x4b0>\n-\tldr\tr0, [pc, #264]\t@ (4b1c <__gridxc_alloc_MOD_realloc_d4+0x4d4>)\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr4, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r5, #60]\t@ 0x3c\n+\tmovs\tr3, #8\n+\tstr\tr6, [r5, #36]\t@ 0x24\n+\tstr.w\tsl, [r5, #48]\t@ 0x30\n+\tstr.w\tr9, [r5, #4]\n+\tstrd\tr3, r2, [r5, #20]\n+\tldr.w\tr0, [pc, #1032]\t@ 4b0c <__gridxc_alloc_MOD_realloc_d4+0x7bc>\n+\tmovs\tr6, #1\n+\tldr\tr4, [r7, #56]\t@ 0x38\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tldr\tr2, [r7, #52]\t@ 0x34\n \tcmp\tr4, #0\n-\tmov\tr1, r4\n-\tvst1.32\t{d16}, [r3]\n-\tmov\tr9, r2\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tstr.w\tr8, [r7, #384]\t@ 0x180\n+\tmov.w\tr8, #0\n+\tstr.w\tfp, [r0, #16]!\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #404]\t@ 0x194\n+\tstr.w\tr3, [r7, #392]\t@ 0x188\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tr8, [r0, #16]!\n+\tmoveq.w\tfp, #0\n+\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tmovs\tr3, #2\n+\tstrd\tr3, r3, [r7, #416]\t@ 0x1a0\n \tcmp\tr2, #0\n-\tmov\tr8, r3\n-\tmov.w\tr3, #4\n-\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tit\teq\n+\tmoveq\tsl, r8\n+\tstrd\tr8, r8, [r7, #396]\t@ 0x18c\n+\tmov\tr1, r4\n+\tit\tne\n+\tmovne\tsl, r3\n+\tstrd\tr6, r6, [r7, #408]\t@ 0x198\n \tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr6, [r7, #424]\t@ 0x1a8\n+\tstrh.w\tr3, [r7, #400]\t@ 0x190\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tstr.w\tr8, [sp]\n-\tldr.w\tr6, [r7, #696]\t@ 0x2b8\n-\tit\teq\n-\tmoveq\tr6, #0\n-\tstr\tr6, [sp, #4]\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n+\tstr.w\tr3, [r7, #388]\t@ 0x184\n+\tmov\tr9, r2\n+\tstrd\tfp, sl, [sp]\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #108\t@ 0x6c\n \tldrd\tr2, r3, [r5, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r5, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r5, #52]\t@ 0x34\n \tsubs\tr2, r2, r1\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r5, #64]\t@ 0x40\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #124]\t@ (4b20 <__gridxc_alloc_MOD_realloc_d4+0x4d8>)\n-\tadds\tr2, #1\n+\tldr\tr1, [pc, #864]\t@ (4b10 <__gridxc_alloc_MOD_realloc_d4+0x7c0>)\n+\tadd\tr2, r6\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r4\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr8, r6, [sp, #4]\n-\tstr\tr3, [sp, #0]\n \tmov\tr3, r9\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstrd\tfp, sl, [sp, #4]\n+\tstr\tr6, [sp, #0]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldrd\tr2, r0, [r5, #64]\t@ 0x40\n \tldrd\tlr, sl, [r5, #52]\t@ 0x34\n \tcmp\tr2, r0\n-\tbgt.w\t4be4 <__gridxc_alloc_MOD_realloc_d4+0x59c>\n+\tbgt.n\t48aa <__gridxc_alloc_MOD_realloc_d4+0x55a>\n \tcmp\tlr, sl\n-\tbgt.w\t4be4 <__gridxc_alloc_MOD_realloc_d4+0x59c>\n-\tldrd\tr8, r6, [r5, #40]\t@ 0x28\n-\tcmp\tr8, r6\n-\tbgt.w\t4be4 <__gridxc_alloc_MOD_realloc_d4+0x59c>\n+\tbgt.n\t48aa <__gridxc_alloc_MOD_realloc_d4+0x55a>\n+\tldrd\tr9, r6, [r5, #40]\t@ 0x28\n+\tcmp\tr9, r6\n+\tbgt.n\t48aa <__gridxc_alloc_MOD_realloc_d4+0x55a>\n \tldrd\tr3, r1, [r5, #28]\n \tcmp\tr3, r1\n-\tbgt.n\t4be4 <__gridxc_alloc_MOD_realloc_d4+0x59c>\n-\tb.n\t4b24 <__gridxc_alloc_MOD_realloc_d4+0x4dc>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000492\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000472\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000328\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000264\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000fc\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000078\n- R_ARM_REL32\t.LC27\n+\tbgt.n\t48aa <__gridxc_alloc_MOD_realloc_d4+0x55a>\n \tadd.w\tip, r0, #1\n \tadd.w\tr0, sl, #1\n \tsub.w\tfp, r0, lr\n \tldr\tr0, [r5, #24]\n \tadds\tr1, #1\n \tsub.w\tr4, ip, r2\n \tsubs\tr1, r1, r3\n \tldr.w\tsl, [r5, #48]\t@ 0x30\n-\tstr\tr4, [r7, #72]\t@ 0x48\n+\tstr\tr4, [r7, #68]\t@ 0x44\n \tadds\tr6, #1\n \tmul.w\tr3, r0, r3\n \tldr.w\tip, [r5, #20]\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\tsub.w\tr6, r6, r8\n+\tstr\tr3, [r7, #96]\t@ 0x60\n+\tsub.w\tr6, r6, r9\n \tldr\tr3, [r5, #60]\t@ 0x3c\n-\tvmov.i64\td16, #0x0000000000000000\n-\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tmov\tr4, r3\n \tldr\tr3, [r5, #4]\n+\tstr.w\tr8, [r7, #88]\t@ 0x58\n \tmul.w\tr0, r0, ip\n-\tstr\tr1, [r7, #88]\t@ 0x58\n+\tldr.w\tr8, [r5]\n+\tvldr\td7, [pc, #708]\t@ 4af0 <__gridxc_alloc_MOD_realloc_d4+0x7a0>\n \tmla\tr3, r2, r4, r3\n-\tldr\tr4, [r7, #108]\t@ 0x6c\n+\tldr\tr4, [r7, #100]\t@ 0x64\n \tmul.w\tr2, lr, sl\n \tldr.w\tlr, [r5, #36]\t@ 0x24\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tmul.w\tr2, r8, lr\n-\tldr.w\tr8, [r5]\n-\tstr\tr2, [r7, #104]\t@ 0x68\n-\tmovs\tr2, #0\n-\tstr\tr2, [r7, #96]\t@ 0x60\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tldr\tr1, [r7, #88]\t@ 0x58\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tmul.w\tr2, r9, lr\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #80]\t@ 0x50\n \tadd.w\tr9, r3, r2\n+\tstrd\tr4, r5, [r7, #36]\t@ 0x24\n \tmovs\tr2, #0\n-\tstr.w\tsl, [r7, #108]\t@ 0x6c\n-\tstrd\tr5, r3, [r7, #36]\t@ 0x24\n-\tstr\tr4, [r7, #32]\n-\tldr\tr3, [r7, #104]\t@ 0x68\n+\tmov\tr4, sl\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n \tmov.w\tsl, #0\n+\tstr\tr2, [r7, #100]\t@ 0x64\n \tadd.w\tr5, r9, r3\n-\tldr\tr3, [r7, #100]\t@ 0x64\n+\tldr\tr3, [r7, #96]\t@ 0x60\n \tadd\tr5, r3\n-\tmla\tr4, ip, r5, r8\n+\tmla\tr2, ip, r5, r8\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tvstr\td16, [r4]\n-\tcmp\tr1, r3\n-\tadd\tr4, r0\n-\tbne.n\t4ba8 <__gridxc_alloc_MOD_realloc_d4+0x560>\n+\tvstr\td7, [r2]\n+\tcmp\tr3, r1\n+\tadd\tr2, r0\n+\tbne.n\t486e <__gridxc_alloc_MOD_realloc_d4+0x51e>\n \tadd.w\tsl, sl, #1\n \tadd\tr5, lr\n-\tcmp\tr6, sl\n-\tbne.n\t4ba2 <__gridxc_alloc_MOD_realloc_d4+0x55a>\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n+\tcmp\tsl, r6\n+\tbne.n\t4868 <__gridxc_alloc_MOD_realloc_d4+0x518>\n+\tldr\tr2, [r7, #100]\t@ 0x64\n+\tadd\tr9, r4\n \tadds\tr2, #1\n \tcmp\tr2, fp\n-\tadd\tr9, r3\n-\tbne.n\t4b94 <__gridxc_alloc_MOD_realloc_d4+0x54c>\n-\tmov\tsl, r3\n-\tstr\tr1, [r7, #88]\t@ 0x58\n-\tldrd\tr5, r3, [r7, #36]\t@ 0x24\n-\tldr\tr1, [r7, #80]\t@ 0x50\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tadd\tr3, r1\n+\tbne.n\t4858 <__gridxc_alloc_MOD_realloc_d4+0x508>\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tmov\tsl, r4\n+\tstr\tr1, [r7, #80]\t@ 0x50\n \tldr\tr1, [r7, #72]\t@ 0x48\n+\tldr\tr2, [r7, #88]\t@ 0x58\n+\tadd\tr3, r1\n+\tldr\tr1, [r7, #68]\t@ 0x44\n \tadds\tr2, #1\n-\tldr\tr4, [r7, #32]\n+\tstr\tr2, [r7, #88]\t@ 0x58\n+\tldrd\tr4, r5, [r7, #36]\t@ 0x24\n \tcmp\tr2, r1\n-\tstr\tr2, [r7, #96]\t@ 0x60\n-\tbne.n\t4b80 <__gridxc_alloc_MOD_realloc_d4+0x538>\n-\tstr\tr4, [r7, #108]\t@ 0x6c\n-\tldr.w\tr3, [pc, #1064]\t@ 5010 <__gridxc_alloc_MOD_realloc_d4+0x9c8>\n+\tbne.n\t4846 <__gridxc_alloc_MOD_realloc_d4+0x4f6>\n+\tstr\tr4, [r7, #100]\t@ 0x64\n+\tldr\tr3, [pc, #616]\t@ (4b14 <__gridxc_alloc_MOD_realloc_d4+0x7c4>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t4d76 <__gridxc_alloc_MOD_realloc_d4+0x72e>\n-\tldr\tr1, [r7, #108]\t@ 0x6c\n-\tstr.w\tsp, [r7, #24]\n+\tbeq.w\t4a34 <__gridxc_alloc_MOD_realloc_d4+0x6e4>\n+\tldr\tr1, [r7, #100]\t@ 0x64\n+\tstr.w\tsp, [r7, #28]\n \tldr\tr3, [r1, #8]\n-\tstr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #68]\t@ 0x44\n \tmov\tr2, r3\n \tldr\tr3, [r1, #12]\n \tldr\tr6, [r1, #28]\n \tsub.w\tr9, r3, r2\n \tldrd\tr0, r3, [r1]\n \tsub.w\tip, r3, r0\n \tldr\tr3, [r1, #16]\n \tstr\tr3, [r7, #40]\t@ 0x28\n \tadd.w\tsl, ip, #1\n \tmov\tr2, r3\n \tldr\tr3, [r1, #20]\n \tsubs\tr2, r3, r2\n \tadd.w\tr3, r9, #1\n-\tstr\tr2, [r7, #100]\t@ 0x64\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n \tmla\tr4, ip, r3, r3\n \tldr\tr3, [r1, #24]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tsubs\tr6, r6, r3\n \torr.w\tr3, ip, r9\n \torr.w\tr1, r3, r2\n \tldr\tr3, [r5, #0]\n \tmla\tr2, r2, r4, r4\n-\tstr\tr3, [r7, #104]\t@ 0x68\n+\tstr\tr3, [r7, #96]\t@ 0x60\n \tldr\tr3, [r5, #4]\n-\tstr\tr3, [r7, #20]\n+\tstr\tr3, [r7, #16]\n \torrs.w\tr3, r6, r1\n-\tstr\tr4, [r7, #96]\t@ 0x60\n-\tstr\tr2, [r7, #32]\n-\tbmi.w\t4e34 <__gridxc_alloc_MOD_realloc_d4+0x7ec>\n+\tstr\tr4, [r7, #88]\t@ 0x58\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tbmi.w\t4b28 <__gridxc_alloc_MOD_realloc_d4+0x7d8>\n \tmla\tr3, r6, r2, r2\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tmov\tr4, sp\n \tcmp\tr4, r2\n-\tbeq.w\t4fc2 <__gridxc_alloc_MOD_realloc_d4+0x97a>\n+\tbeq.w\t4cb4 <__gridxc_alloc_MOD_realloc_d4+0x964>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t4c5e <__gridxc_alloc_MOD_realloc_d4+0x616>\n-\tldrd\tr5, r4, [r7, #16]\n-\tldr\tr3, [r7, #28]\n-\tldr\tr6, [r7, #36]\t@ 0x24\n+\tb.n\t4922 <__gridxc_alloc_MOD_realloc_d4+0x5d2>\n+\tldrd\tr4, r2, [r7, #12]\n+\tldrd\tr6, r5, [r7, #20]\n+\tldr\tr3, [r7, #32]\n \tadds\tr5, #1\n-\tldr\tr2, [r7, #12]\n \tadd\tr4, r3\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tcmp\tr6, r5\n \tadd\tr2, r3\n-\tbge.w\t4f54 <__gridxc_alloc_MOD_realloc_d4+0x90c>\n-\tldr\tr5, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n-\tldr\tr6, [r7, #60]\t@ 0x3c\n+\tbge.w\t4c46 <__gridxc_alloc_MOD_realloc_d4+0x8f6>\n+\tldr\tr5, [r7, #56]\t@ 0x38\n+\tadd.w\tr0, r7, #108\t@ 0x6c\n+\tldr\tr6, [r7, #52]\t@ 0x34\n \tmovs\tr4, #1\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #588]\t@ 0x24c\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #588]\t@ 0x24c\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n-\tldrd\tr2, r3, [r7, #548]\t@ 0x224\n-\tldr.w\tsp, [r7, #24]\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tldrd\tr2, r3, [r7, #476]\t@ 0x1dc\n+\tldr.w\tsp, [r7, #28]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #536]\t@ 0x218\n+\tldrd\tr1, r2, [r7, #464]\t@ 0x1d0\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #560]\t@ 0x230\n+\tldrd\tr1, r2, [r7, #488]\t@ 0x1e8\n \tsubs\tr2, r2, r1\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #572]\t@ 0x23c\n+\tldrd\tr1, r2, [r7, #500]\t@ 0x1f4\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #812]\t@ (5014 <__gridxc_alloc_MOD_realloc_d4+0x9cc>)\n+\tldr\tr1, [pc, #364]\t@ (4b18 <__gridxc_alloc_MOD_realloc_d4+0x7c8>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #588]\t@ 0x24c\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tcbz\tr3, 4d18 <__gridxc_alloc_MOD_realloc_d4+0x6d0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tcbz\tr3, 49dc <__gridxc_alloc_MOD_realloc_d4+0x68c>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvldr\td18, [pc, #724]\t@ 4ff8 <__gridxc_alloc_MOD_realloc_d4+0x9b0>\n-\tvldr\td19, [pc, #728]\t@ 5000 <__gridxc_alloc_MOD_realloc_d4+0x9b8>\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tldr\tr0, [pc, #744]\t@ (5018 <__gridxc_alloc_MOD_realloc_d4+0x9d0>)\n-\tvldr\td17, [pc, #728]\t@ 5008 <__gridxc_alloc_MOD_realloc_d4+0x9c0>\n-\tadd\tr0, pc\n-\tldr\tr1, [r7, #64]\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n+\tldr\tr0, [pc, #316]\t@ (4b1c <__gridxc_alloc_MOD_realloc_d4+0x7cc>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #44]\t@ 0x2c\n+\tadd\tr0, pc\n+\tstrd\tr5, r5, [r7, #396]\t@ 0x18c\n+\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tldr\tr1, [r7, #56]\t@ 0x38\n \tstr.w\tr4, [r0, #16]!\n \tmovs\tr4, #4\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr4, [r7, #500]\t@ 0x1f4\n+\tstr.w\tr4, [r7, #404]\t@ 0x194\n+\tstr.w\tr4, [r7, #392]\t@ 0x188\n+\tstr.w\tr4, [r7, #428]\t@ 0x1ac\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #408]\t@ 0x198\n+\tstr.w\tr4, [r7, #424]\t@ 0x1a8\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #416]\t@ 0x1a0\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #468]\t@ 0x1d4\n-\tstrh.w\tr4, [r7, #472]\t@ 0x1d8\n+\tstrh.w\tr4, [r7, #400]\t@ 0x190\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #460]\t@ 0x1cc\n-\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n-\tldrd\tr3, r2, [r7, #56]\t@ 0x38\n+\tstr.w\tr4, [r7, #388]\t@ 0x184\n+\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\tldrd\tr3, r2, [r7, #48]\t@ 0x30\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr4, [r7, #588]\t@ 0x24c\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #676]\t@ (501c <__gridxc_alloc_MOD_realloc_d4+0x9d4>)\n-\tldr\tr3, [pc, #676]\t@ (5020 <__gridxc_alloc_MOD_realloc_d4+0x9d8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #232]\t@ (4b20 <__gridxc_alloc_MOD_realloc_d4+0x7d0>)\n+\tldr\tr3, [pc, #196]\t@ (4afc <__gridxc_alloc_MOD_realloc_d4+0x7ac>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4fe8 <__gridxc_alloc_MOD_realloc_d4+0x9a0>\n-\tadd.w\tr7, r7, #588\t@ 0x24c\n+\tbne.w\t4cda <__gridxc_alloc_MOD_realloc_d4+0x98a>\n+\tadd.w\tr7, r7, #516\t@ 0x204\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadd.w\tr3, r7, #280\t@ 0x118\n-\tstr\tr4, [r7, #92]\t@ 0x5c\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tb.n\t476c <__gridxc_alloc_MOD_realloc_d4+0x124>\n-\tldrd\tr2, r3, [r7, #548]\t@ 0x224\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n-\tldr\tr4, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #208\t@ 0xd0\n+\tstr\tr4, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tb.n\t4472 <__gridxc_alloc_MOD_realloc_d4+0x122>\n+\tldrd\tr2, r3, [r7, #476]\t@ 0x1dc\n+\tadd.w\tr0, r7, #108\t@ 0x6c\n+\tldr\tr4, [r7, #56]\t@ 0x38\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #536]\t@ 0x218\n-\tadds\tr3, #1\n+\tldrd\tr1, r2, [r7, #464]\t@ 0x1d0\n+\tadd\tr3, r6\n \tcmp\tr4, #0\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #560]\t@ 0x230\n+\tldrd\tr1, r2, [r7, #488]\t@ 0x1e8\n \tsub.w\tr2, r2, r1\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #572]\t@ 0x23c\n+\tldrd\tr1, r2, [r7, #500]\t@ 0x1f4\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #568]\t@ (5024 <__gridxc_alloc_MOD_realloc_d4+0x9dc>)\n-\tadd.w\tr2, r2, #1\n-\tadd\tr1, pc\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n+\tmov\tr2, r4\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tstr\tr6, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #588]\t@ 0x24c\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n-\tcmp\tr2, #0\n+\tldr\tr6, [r7, #52]\t@ 0x34\n+\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tcmp\tr6, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #84]\t@ (4b24 <__gridxc_alloc_MOD_realloc_d4+0x7d4>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tmov\tr2, r4\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tadd\tr1, pc\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tsl, [r8, #16]\n-\tstr.w\tsl, [r7, #68]\t@ 0x44\n-\tb.n\t48ae <__gridxc_alloc_MOD_realloc_d4+0x266>\n+\tstr.w\tfp, [sl, #16]\n+\tstr.w\tfp, [r7, #60]\t@ 0x3c\n+\tb.n\t45a0 <__gridxc_alloc_MOD_realloc_d4+0x250>\n+\tnop\n+\t...\n+\t.word\t0x00000784\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000075a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005de\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000560\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000400\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000035c\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000264\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000168\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000136\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000e4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000004a\n+ R_ARM_REL32\t.LC27\n \tcmp\tr6, #0\n-\tblt.w\t4c88 <__gridxc_alloc_MOD_realloc_d4+0x640>\n-\tldr.w\tfp, [r7, #56]\t@ 0x38\n+\tblt.w\t494c <__gridxc_alloc_MOD_realloc_d4+0x5fc>\n+\tldr.w\tfp, [r7, #48]\t@ 0x30\n \tldr\tr3, [r5, #24]\n-\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr1, #0\n-\tblt.w\t4c88 <__gridxc_alloc_MOD_realloc_d4+0x640>\n-\tldr\tr4, [r7, #92]\t@ 0x5c\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n-\tldr\tr2, [r7, #28]\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tstr\tr5, [r7, #16]\n+\tblt.w\t494c <__gridxc_alloc_MOD_realloc_d4+0x5fc>\n+\tldr\tr4, [r7, #84]\t@ 0x54\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tldr\tr2, [r7, #20]\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tstr\tr5, [r7, #20]\n \tmla\tr2, r1, r3, r2\n \tldr\tr1, [r7, #40]\t@ 0x28\n \tmul.w\tr3, r4, r3\n-\tstr\tr3, [r7, #28]\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n+\tstr\tr3, [r7, #32]\n+\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n \tmla\tr2, r1, r3, r2\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #472]\t@ 0x1d8\n \tmul.w\tr3, r4, r3\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tmul.w\tr8, r4, r1\n \tmla\tr2, r3, r1, r2\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #24]\n \tmov\tr3, r4\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n+\tstr\tr0, [r7, #24]\n \tmla\tr2, r0, r1, r2\n \tmul.w\tr4, r4, r1\n-\tldr\tr1, [r7, #68]\t@ 0x44\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n \tmla\tr3, r3, r2, r1\n-\tmovs\tr2, #0\n \tmov\tr1, r6\n-\tmov\tr5, r2\n-\tmov\tr6, r2\n+\tmovs\tr2, #0\n \tmov\tlr, r1\n-\tmov\tr2, r3\n-\tmov\tr1, r5\n-\tmov\tr0, r2\n+\tmov\tr6, r2\n+\tmov\tr5, r3\n+\tmov\tr1, r6\n+\tmov\tr0, r5\n \tmovs\tr3, #0\n \tstrd\tr5, r6, [r7, #8]\n-\tstrd\tr2, lr, [r7]\n+\tstrd\tlr, r2, [r7]\n \tmov\tr6, r1\n \tmov\tr5, r0\n \tmov.w\tlr, #0\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tstrd\tr0, r1, [r7, #88]\t@ 0x58\n+\tstr\tr1, [r7, #100]\t@ 0x64\n+\tstrd\tr3, r0, [r7, #80]\t@ 0x50\n \tadd.w\tr0, fp, r6, lsl #3\n \tmov\tr1, r5\n \tmovs\tr2, #0\n-\tvldr\td16, [r1]\n-\tcmp\tip, r2\n+\tvldr\td7, [r1]\n+\tcmp\tr2, ip\n \tadd\tr1, r4\n \tadd.w\tr2, r2, #1\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t4ec0 <__gridxc_alloc_MOD_realloc_d4+0x878>\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t4bb2 <__gridxc_alloc_MOD_realloc_d4+0x862>\n \tadd\tr5, r8\n \tadd\tr6, sl\n \tadd.w\tr3, lr, #1\n-\tcmp\tr9, lr\n-\tbeq.n\t4ee2 <__gridxc_alloc_MOD_realloc_d4+0x89a>\n+\tcmp\tlr, r9\n+\tbeq.n\t4bd4 <__gridxc_alloc_MOD_realloc_d4+0x884>\n \tmov\tlr, r3\n-\tb.n\t4eb8 <__gridxc_alloc_MOD_realloc_d4+0x870>\n-\tldrd\tr0, r1, [r7, #88]\t@ 0x58\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tldr\tr5, [r7, #100]\t@ 0x64\n+\tb.n\t4baa <__gridxc_alloc_MOD_realloc_d4+0x85a>\n+\tldrd\tr3, r0, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #100]\t@ 0x64\n+\tldr\tr5, [r7, #92]\t@ 0x5c\n \tadd\tr0, r2\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tcmp\tr3, r5\n+\tldr\tr2, [r7, #88]\t@ 0x58\n+\tcmp\tr5, r3\n \tadd\tr1, r2\n \tadd.w\tr2, r3, #1\n-\tbeq.n\t4efe <__gridxc_alloc_MOD_realloc_d4+0x8b6>\n+\tbeq.n\t4bf0 <__gridxc_alloc_MOD_realloc_d4+0x8a0>\n \tmov\tr3, r2\n-\tb.n\t4eaa <__gridxc_alloc_MOD_realloc_d4+0x862>\n-\tldrd\tr2, lr, [r7]\n+\tb.n\t4b9c <__gridxc_alloc_MOD_realloc_d4+0x84c>\n \tldrd\tr5, r6, [r7, #8]\n-\tldr\tr3, [r7, #28]\n-\tadds\tr6, #1\n-\tadd\tr2, r3\n+\tldrd\tlr, r2, [r7]\n \tldr\tr3, [r7, #32]\n-\tcmp\tr6, lr\n+\tadds\tr2, #1\n \tadd\tr5, r3\n-\tble.n\t4e9c <__gridxc_alloc_MOD_realloc_d4+0x854>\n-\tldr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tcmp\tr2, lr\n+\tadd\tr6, r3\n+\tble.n\t4b8e <__gridxc_alloc_MOD_realloc_d4+0x83e>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tmov\tr6, lr\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n-\tldr\tr5, [r7, #16]\n-\tldr\tr1, [r7, #20]\n+\tldr\tr0, [r7, #24]\n+\tldr\tr5, [r7, #20]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr2, r0, r3\n-\tldr\tr0, [r7, #36]\t@ 0x24\n-\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr0, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r7, #72]\t@ 0x48\n \tldr\tr2, [r5, #60]\t@ 0x3c\n-\tstr\tr2, [r7, #28]\n+\tstr\tr2, [r7, #32]\n \tldr.w\tr8, [r5, #36]\t@ 0x24\n \tmla\tr4, r0, r2, r1\n \tldr\tr2, [r5, #48]\t@ 0x30\n \tldr\tr1, [r7, #40]\t@ 0x28\n-\tstr\tr2, [r7, #80]\t@ 0x50\n+\tstr\tr2, [r7, #64]\t@ 0x40\n \tmul.w\tr1, r2, r1\n \tldr\tr2, [r5, #20]\n \tstr\tr1, [r7, #40]\t@ 0x28\n-\tldr\tr1, [r7, #72]\t@ 0x48\n-\tstr\tr2, [r7, #108]\t@ 0x6c\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tstr\tr2, [r7, #100]\t@ 0x64\n \tmul.w\tlr, r3, r2\n \tmovs\tr3, #0\n \tmov\tr5, r3\n \tmov\tr2, r3\n \tmul.w\tr1, r1, r8\n-\tstr\tr1, [r7, #72]\t@ 0x48\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr0, r2\n-\tstr\tr6, [r7, #36]\t@ 0x24\n+\tstrd\tr6, r5, [r7, #20]\n \tadds\tr1, r4, r3\n \tmovs\tr3, #0\n-\tstrd\tr5, r4, [r7, #16]\n-\tstr\tr2, [r7, #12]\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr4, r2, [r7, #12]\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tmov\tr5, r0\n \tmovs\tr6, #0\n-\tstrd\tr1, r0, [r7, #88]\t@ 0x58\n+\tstrd\tr3, r1, [r7, #80]\t@ 0x50\n \tadds\tr4, r1, r2\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n \tadd\tr4, r2\n-\tldrd\tr3, r2, [r7, #104]\t@ 0x68\n+\tldrd\tr3, r2, [r7, #96]\t@ 0x60\n \tadd.w\tr0, fp, r5, lsl #3\n \tmla\tr1, r2, r4, r3\n \tmovs\tr2, #0\n-\tvldmia\tr0!, {d16}\n-\tcmp\tip, r2\n+\tvldmia\tr0!, {d7}\n+\tcmp\tr2, ip\n \tadd.w\tr2, r2, #1\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd\tr1, lr\n-\tbne.n\t4f84 <__gridxc_alloc_MOD_realloc_d4+0x93c>\n+\tbne.n\t4c76 <__gridxc_alloc_MOD_realloc_d4+0x926>\n \tadd\tr4, r8\n \tadd\tr5, sl\n \tadds\tr3, r6, #1\n \tcmp\tr6, r9\n-\tbeq.n\t4fa4 <__gridxc_alloc_MOD_realloc_d4+0x95c>\n+\tbeq.n\t4c96 <__gridxc_alloc_MOD_realloc_d4+0x946>\n \tmov\tr6, r3\n-\tb.n\t4f76 <__gridxc_alloc_MOD_realloc_d4+0x92e>\n-\tldrd\tr2, r3, [r7, #80]\t@ 0x50\n-\tldrd\tr1, r0, [r7, #88]\t@ 0x58\n-\tldr\tr4, [r7, #100]\t@ 0x64\n+\tb.n\t4c68 <__gridxc_alloc_MOD_realloc_d4+0x918>\n+\tldrd\tr3, r1, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n+\tldr\tr4, [r7, #92]\t@ 0x5c\n \tadd\tr1, r2\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tcmp\tr3, r4\n+\tldr\tr2, [r7, #88]\t@ 0x58\n+\tcmp\tr4, r3\n \tadd\tr0, r2\n \tadd.w\tr2, r3, #1\n-\tbeq.w\t4c70 <__gridxc_alloc_MOD_realloc_d4+0x628>\n+\tbeq.w\t4934 <__gridxc_alloc_MOD_realloc_d4+0x5e4>\n \tmov\tr3, r2\n-\tb.n\t4f64 <__gridxc_alloc_MOD_realloc_d4+0x91c>\n+\tb.n\t4c56 <__gridxc_alloc_MOD_realloc_d4+0x906>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbnz\tr3, 4fd6 <__gridxc_alloc_MOD_realloc_d4+0x98e>\n+\tcbnz\tr3, 4cc8 <__gridxc_alloc_MOD_realloc_d4+0x978>\n \tldr\tr3, [r5, #24]\n \tadd.w\tfp, sp, #16\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tb.n\t4e42 <__gridxc_alloc_MOD_realloc_d4+0x7fa>\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tb.n\t4b36 <__gridxc_alloc_MOD_realloc_d4+0x7e6>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t4fcc <__gridxc_alloc_MOD_realloc_d4+0x984>\n-\tmovw\tr8, #5014\t@ 0x1396\n-\tb.n\t49f6 <__gridxc_alloc_MOD_realloc_d4+0x3ae>\n-\tmov\tr8, r2\n-\tb.n\t491c <__gridxc_alloc_MOD_realloc_d4+0x2d4>\n+\tb.n\t4cbe <__gridxc_alloc_MOD_realloc_d4+0x96e>\n+\tmovw\tfp, #5014\t@ 0x1396\n+\tb.n\t4700 <__gridxc_alloc_MOD_realloc_d4+0x3b0>\n+\tmov\tfp, sl\n+\tb.n\t460a <__gridxc_alloc_MOD_realloc_d4+0x2ba>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovw\tr8, #5020\t@ 0x139c\n-\tb.n\t49f6 <__gridxc_alloc_MOD_realloc_d4+0x3ae>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000424\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000328\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000002e2\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000029e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000230\n- R_ARM_REL32\t.LC27\n+\tmovw\tfp, #5020\t@ 0x139c\n+\tb.n\t4700 <__gridxc_alloc_MOD_realloc_d4+0x3b0>\n \n-00005028 <__gridxc_alloc_MOD_realloc_d3>:\n+00004ce4 <__gridxc_alloc_MOD_realloc_d3>:\n __gridxc_alloc_MOD_realloc_d3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3520]\t@ 0xdc0\n-\tmov\tlr, r2\n-\tldr.w\tr2, [pc, #1056]\t@ 5460 <__gridxc_alloc_MOD_realloc_d3+0x438>\n+\tstr.w\tr0, [ip, #3608]\t@ 0xe18\n+\tmov\tsl, r2\n+\tldr.w\tr2, [pc, #1584]\t@ 5328 <__gridxc_alloc_MOD_realloc_d3+0x644>\n \tmov\tr6, r3\n-\tldr.w\tr3, [pc, #1052]\t@ 5464 <__gridxc_alloc_MOD_realloc_d3+0x43c>\n+\tldr.w\tr3, [pc, #1580]\t@ 532c <__gridxc_alloc_MOD_realloc_d3+0x648>\n \tadd\tr2, pc\n-\tsub\tsp, #508\t@ 0x1fc\n-\tmov\tr7, r1\n-\tmovs\tr1, #1\n+\tsub\tsp, #452\t@ 0x1c4\n+\tmov\tlr, r1\n \tmov\tr4, r0\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [pc, #1040]\t@ 5468 <__gridxc_alloc_MOD_realloc_d3+0x440>\n+\tldr.w\tr2, [pc, #1572]\t@ 5330 <__gridxc_alloc_MOD_realloc_d3+0x64c>\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #500]\t@ 0x1f4\n+\tstr\tr3, [sp, #444]\t@ 0x1bc\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tadd\tr2, pc\n-\tldr.w\tr8, [sp, #576]\t@ 0x240\n+\tldr.w\tr8, [sp, #488]\t@ 0x1e8\n \tcmp\tr3, #0\n-\tldr.w\tfp, [sp, #600]\t@ 0x258\n-\tit\teq\n+\tldr\tr7, [sp, #492]\t@ 0x1ec\n+\tite\tne\n+\tmovne\tr1, #1\n \tmoveq\tr1, #0\n \tstr\tr1, [r2, #0]\n-\tldr\tr2, [sp, #588]\t@ 0x24c\n+\tldrd\tr9, r2, [sp, #496]\t@ 0x1f0\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr2, [sp, #504]\t@ 0x1f8\n \tstr\tr2, [sp, #80]\t@ 0x50\n-\tldr\tr2, [sp, #592]\t@ 0x250\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #596]\t@ 0x254\n-\tldrd\tr9, sl, [sp, #580]\t@ 0x244\n-\tstr\tr2, [sp, #20]\n-\tbeq.w\t562c <__gridxc_alloc_MOD_realloc_d3+0x604>\n+\tldr\tr2, [sp, #508]\t@ 0x1fc\n+\tldr.w\tfp, [sp, #512]\t@ 0x200\n+\tstr\tr2, [sp, #16]\n+\tbeq.w\t5292 <__gridxc_alloc_MOD_realloc_d3+0x5ae>\n \tmov\tip, r0\n \tstr\tr3, [sp, #32]\n \tldr\tr3, [r0, #4]\n-\tadd\tr5, sp, #440\t@ 0x1b8\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tadd\tr5, sp, #384\t@ 0x180\n+\tstr\tr3, [sp, #52]\t@ 0x34\n \tldr\tr3, [r0, #24]\n-\tstr\tr3, [sp, #24]\n-\tadd\tr3, sp, #224\t@ 0xe0\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tadd\tr3, sp, #168\t@ 0xa8\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tip, {r0, r1, r2}\n \tstmia.w\tr5, {r0, r1, r2}\n-\tldr\tr3, [sp, #472]\t@ 0x1d8\n-\tstr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #416]\t@ 0x1a0\n+\tstr\tr3, [sp, #20]\n \tldr\tr2, [r4, #20]\n-\tldr\tr5, [sp, #88]\t@ 0x58\n-\tldr\tr0, [sp, #468]\t@ 0x1d4\n-\tldr\tr1, [sp, #16]\n+\tldr\tr5, [sp, #84]\t@ 0x54\n+\tldr\tr0, [sp, #412]\t@ 0x19c\n+\tldr\tr1, [sp, #20]\n \tstr\tr2, [sp, #36]\t@ 0x24\n-\tldrd\tr3, r2, [sp, #480]\t@ 0x1e0\n+\tldrd\tr3, r2, [sp, #424]\t@ 0x1a8\n \tsubs.w\tip, r1, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tstr\tr0, [r5, #0]\n \tsubs\tr0, r2, r3\n-\tstr\tr0, [sp, #28]\n+\tstr\tr0, [sp, #24]\n \tit\tmi\n \tmovmi\tr3, #1\n \tstr\tr3, [r5, #8]\n-\tldrd\tr0, r3, [sp, #492]\t@ 0x1ec\n+\tldrd\tr0, r3, [sp, #436]\t@ 0x1b4\n \tsubs\tr1, r3, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tcmp.w\tip, #0\n \tstr\tr0, [r5, #16]\n-\tldr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #20]\n \tit\tlt\n \tmovlt\tr0, #0\n-\tstr\tr0, [sp, #16]\n-\tldr\tr0, [sp, #28]\n+\tstr\tr0, [sp, #20]\n+\tldr\tr0, [sp, #24]\n \tcmp\tr0, #0\n-\tldr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #20]\n \tit\tlt\n \tmovlt\tr2, #0\n \tcmp\tr1, #0\n \tit\tlt\n \tmovlt\tr3, #0\n \tstr\tr0, [r5, #4]\n \tstr\tr2, [r5, #12]\n \tstr\tr3, [r5, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr3, [r9]\n-\tvldr\td18, [pc, #812]\t@ 5440 <__gridxc_alloc_MOD_realloc_d3+0x418>\n-\tvldr\td19, [pc, #816]\t@ 5448 <__gridxc_alloc_MOD_realloc_d3+0x420>\n-\tstr\tr3, [sp, #168]\t@ 0xa8\n \tldr\tr2, [r7, #0]\n-\tadd\tr3, sp, #268\t@ 0x10c\n-\tldr\tr1, [r6, #0]\n-\tldr.w\tr0, [lr]\n-\tldr.w\tr5, [r8]\n-\tldr.w\tr7, [sl]\n-\tstrd\tr2, r0, [sp, #128]\t@ 0x80\n-\tadd\tr0, sp, #392\t@ 0x188\n-\tstrd\tr1, r5, [sp, #136]\t@ 0x88\n-\tmov\tr6, r0\n-\tvldr\td17, [pc, #788]\t@ 5450 <__gridxc_alloc_MOD_realloc_d3+0x428>\n-\tadd\tr2, sp, #152\t@ 0x98\n-\tvldr\td20, [sp, #128]\t@ 0x80\n-\tvldr\td21, [sp, #136]\t@ 0x88\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tvstr\td16, [sp, #260]\t@ 0x104\n-\tadd\tr1, sp, #428\t@ 0x1ac\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #284\t@ 0x11c\n-\tldr.w\tr8, [pc, #788]\t@ 546c <__gridxc_alloc_MOD_realloc_d3+0x444>\n-\tvstr\td16, [sp, #304]\t@ 0x130\n-\tadd\tr5, sp, #200\t@ 0xc8\n-\tvst1.32\t{d17}, [r3]\n-\tadd\tr3, sp, #316\t@ 0x13c\n-\tvstr\td16, [sp, #308]\t@ 0x134\n-\tadd\tr8, pc\n-\tstr\tr0, [sp, #92]\t@ 0x5c\n-\tadd\tr0, sp, #248\t@ 0xf8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #332\t@ 0x14c\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n-\tadd\tr1, sp, #380\t@ 0x17c\n-\tvst1.32\t{d17}, [r3]\n-\tadd\tr3, sp, #364\t@ 0x16c\n-\tstr\tr7, [r2, #20]\n-\tadd\tr7, sp, #176\t@ 0xb0\n-\tvstr\td16, [sp, #352]\t@ 0x160\n-\tstr\tr2, [sp, #16]\n-\tmovs\tr2, #3\n-\tvstr\td16, [sp, #356]\t@ 0x164\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #412\t@ 0x19c\n-\tstr\tr2, [sp, #340]\t@ 0x154\n+\tmov.w\tip, #4\n+\tldr.w\tr0, [r8]\n+\tadd.w\tr8, sp, #96\t@ 0x60\n+\tstr\tr0, [sp, #156]\t@ 0x9c\n+\tadd\tr0, sp, #192\t@ 0xc0\n+\tldr.w\tr5, [r9]\n+\tadd\tr7, sp, #144\t@ 0x90\n+\tldr.w\tr9, [pc, #1368]\t@ 5334 <__gridxc_alloc_MOD_realloc_d3+0x650>\n+\tldr\tr3, [r6, #0]\n+\tldr.w\tr1, [lr]\n+\tadd\tr9, pc\n+\tldr.w\tr6, [sl]\n+\tmvn.w\tlr, #2\n+\tstr\tr1, [r7, #0]\n+\tstr\tr3, [r7, #8]\n+\tadd\tr3, sp, #336\t@ 0x150\n+\tstr\tr6, [r7, #4]\n+\tmovs\tr6, #1\n \tstr\tr3, [sp, #72]\t@ 0x48\n-\tmvn.w\tr3, #2\n-\tstr\tr2, [sp, #388]\t@ 0x184\n-\tvstr\td20, [sp, #152]\t@ 0x98\n-\tvstr\td21, [sp, #160]\t@ 0xa0\n-\tstr\tr3, [r0, #4]\n-\tvst1.32\t{d17}, [r1]\n-\tstr\tr2, [sp, #436]\t@ 0x1b4\n-\tldr\tr1, [sp, #20]\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tstr\tr7, [r0, #0]\n-\tstrd\tr2, r3, [sp, #344]\t@ 0x158\n+\tmovs\tr3, #0\n+\tstrd\tr6, r6, [r0, #24]\n+\tstrd\tr3, r3, [sp, #200]\t@ 0xc8\n+\tstr\tr3, [sp, #208]\t@ 0xd0\n+\tstrd\tr3, r3, [sp, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #256]\t@ 0x100\n+\tstr\tr6, [r0, #40]\t@ 0x28\n+\tstr.w\tip, [sp, #260]\t@ 0x104\n+\tstr.w\tlr, [r0, #4]\n+\tstr\tr2, [r7, #16]\n+\tmovs\tr2, #2\n+\tstr\tr5, [r7, #20]\n+\tmovs\tr5, #3\n+\tstrd\tr2, r2, [r0, #32]\n+\tstr\tr5, [r0, #44]\t@ 0x2c\n+\tstr\tr2, [sp, #272]\t@ 0x110\n+\tstr.w\tip, [r0, #20]\n+\tstrd\tr6, r6, [sp, #264]\t@ 0x108\n+\tstr\tr6, [sp, #280]\t@ 0x118\n+\tstr.w\tr8, [r0]\n+\tldr\tr1, [sp, #16]\n \tstr\tr1, [sp, #0]\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tstr\tr3, [sp, #396]\t@ 0x18c\n-\tstr\tr3, [sp, #300]\t@ 0x12c\n-\tldr\tr3, [sp, #16]\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tmov\tr3, r6\n-\tvstr\td16, [sp, #400]\t@ 0x190\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tstrd\tr1, lr, [sp, #288]\t@ 0x120\n+\tadd\tr1, sp, #240\t@ 0xf0\n+\tstrd\tlr, r3, [sp, #340]\t@ 0x154\n+\tstr\tr2, [sp, #276]\t@ 0x114\n+\tstrd\tr3, r3, [sp, #296]\t@ 0x128\n+\tstr\tr3, [sp, #304]\t@ 0x130\n+\tstrd\tr6, r2, [sp, #316]\t@ 0x13c\n+\tstr\tr2, [sp, #324]\t@ 0x144\n+\tstrd\tr3, r3, [sp, #348]\t@ 0x15c\n+\tstrd\tr6, r2, [sp, #364]\t@ 0x16c\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr2, [sp, #372]\t@ 0x174\n+\tadd\tr2, sp, #288\t@ 0x120\n+\tstr\tr5, [sp, #284]\t@ 0x11c\n+\tstr.w\tlr, [sp, #244]\t@ 0xf4\n+\tstr.w\tip, [sp, #308]\t@ 0x134\n+\tstr.w\tip, [sp, #356]\t@ 0x164\n+\tstrd\tr6, r5, [sp, #328]\t@ 0x148\n+\tstr\tr5, [sp, #380]\t@ 0x17c\n+\tadd\tr5, sp, #120\t@ 0x78\n \tstr.w\tfp, [sp, #4]\n-\tvstr\td16, [sp, #404]\t@ 0x194\n-\tvst1.32\t{d18-d19}, [r2]\n-\tadd\tr2, sp, #344\t@ 0x158\n-\tvst1.32\t{d17}, [r1]\n-\tadd\tr1, sp, #296\t@ 0x128\n-\tstr\tr5, [sp, #296]\t@ 0x128\n+\tstr\tr6, [sp, #312]\t@ 0x138\n+\tstr\tr6, [sp, #360]\t@ 0x168\n+\tstr\tr6, [sp, #376]\t@ 0x178\n+\tstr\tr7, [sp, #336]\t@ 0x150\n+\tstr\tr5, [sp, #240]\t@ 0xf0\n \tbl\t3cc <__gridxc_alloc_MOD_options.constprop.2>\n-\tldr.w\tr3, [r8, #8]\n-\tcbz\tr3, 51fc <__gridxc_alloc_MOD_realloc_d3+0x1d4>\n-\tldr.w\tr9, [r8, #12]\n-\tcmp.w\tr9, #0\n-\tbeq.w\t5634 <__gridxc_alloc_MOD_realloc_d3+0x60c>\n-\tldr\tr3, [pc, #624]\t@ (5470 <__gridxc_alloc_MOD_realloc_d3+0x448>)\n+\tldr.w\tr3, [r9, #8]\n+\tcbz\tr3, 4e98 <__gridxc_alloc_MOD_realloc_d3+0x1b4>\n+\tldr.w\tsl, [r9, #12]\n+\tcmp.w\tsl, #0\n+\tbeq.w\t529a <__gridxc_alloc_MOD_realloc_d3+0x5b6>\n+\tldr.w\tr3, [pc, #1180]\t@ 5338 <__gridxc_alloc_MOD_realloc_d3+0x654>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t547c <__gridxc_alloc_MOD_realloc_d3+0x454>\n-\tldrd\tr1, r3, [r7]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tip, r9, [r7, #8]\n-\tsub.w\tsl, r3, r1\n-\tsub.w\tfp, r9, ip\n-\torr.w\tr0, sl, sl, asr #31\n-\tvstr\td16, [r4, #12]\n-\tadds\tr0, #1\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\torr.w\tr2, fp, fp, asr #31\n-\tstr\tr1, [sp, #112]\t@ 0x70\n-\tmovs\tr3, #8\n-\tstr.w\tip, [sp, #124]\t@ 0x7c\n-\tadds\tr2, #1\n-\tstr\tr0, [sp, #120]\t@ 0x78\n-\tvldr\td10, [sp, #112]\t@ 0x70\n-\tvldr\td11, [sp, #120]\t@ 0x78\n+\tbeq.w\t50f0 <__gridxc_alloc_MOD_realloc_d3+0x40c>\n+\tldr.w\tr2, [r8, #4]\n+\tldr.w\tr1, [r8, #12]\n+\tldr.w\tr0, [r8, #8]\n+\tldr.w\tfp, [r8]\n+\tstr\tr1, [sp, #28]\n+\tsubs\tr1, r1, r0\n+\tsub.w\tr6, r2, fp\n+\tstr\tr2, [sp, #20]\n+\torr.w\tsl, r1, r1, asr #31\n+\tmovs\tr2, #0\n+\torr.w\tr3, r6, r6, asr #31\n+\tstr\tr6, [sp, #24]\n+\tstrd\tr2, r2, [r4, #12]\n+\tadds\tr6, r3, #1\n+\tadds.w\tsl, sl, #1\n+\tmov.w\tr3, #8\n+\tstr\tr0, [sp, #16]\n \tstr\tr3, [r4, #8]\n \tmovw\tr3, #771\t@ 0x303\n+\tstr\tr1, [sp, #40]\t@ 0x28\n \tstrh\tr3, [r4, #16]\n-\tbeq.w\t56b6 <__gridxc_alloc_MOD_realloc_d3+0x68e>\n-\tmvn.w\tr8, #2147483648\t@ 0x80000000\n-\tudiv\tr8, r8, r2\n-\tcmp\tr8, r0\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr8, r3\n-\tldrd\tlr, r3, [r7, #16]\n-\tmul.w\tr2, r0, r2\n-\tstrd\tr9, r2, [sp, #96]\t@ 0x60\n-\tsub.w\tr9, r3, lr\n-\tstrd\tlr, r3, [sp, #104]\t@ 0x68\n-\torr.w\tr3, r9, r9, asr #31\n-\tvldr\td8, [sp, #96]\t@ 0x60\n-\tvldr\td9, [sp, #104]\t@ 0x68\n-\tadds\tr3, #1\n-\tbeq.n\t52a2 <__gridxc_alloc_MOD_realloc_d3+0x27a>\n-\tmvn.w\tr7, #2147483648\t@ 0x80000000\n-\tmov\tr6, r8\n-\tudiv\tr7, r7, r3\n-\tmul.w\tr3, r2, r3\n-\tcmp\tr7, r2\n+\tbeq.w\t5318 <__gridxc_alloc_MOD_realloc_d3+0x634>\n+\tmov\tr1, sl\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r6\n+\tite\tge\n+\tmovge.w\tr9, #0\n+\tmovlt.w\tr9, #1\n+\tldr.w\tr2, [r8, #20]\n+\tmul.w\tsl, sl, r6\n+\tldr.w\tr3, [r8, #16]\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tsubs\tr2, r2, r3\n+\torr.w\tr8, r2, r2, asr #31\n+\tadds.w\tr8, r8, #1\n+\tbeq.n\t4f42 <__gridxc_alloc_MOD_realloc_d3+0x25e>\n+\tmov\tr1, r8\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr8, r8, sl\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tcmp\tr0, sl\n \tit\tlt\n-\taddlt\tr6, #1\n-\tcmp.w\tr3, #536870912\t@ 0x20000000\n+\taddlt.w\tr9, r9, #1\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tcmp.w\tr8, #536870912\t@ 0x20000000\n \tit\tge\n-\taddge\tr6, #1\n-\tmov\tr8, r6\n-\tnegs\tr1, r1\n-\torr.w\tr7, sl, fp\n-\torrs.w\tr7, r7, r9\n-\tit\tpl\n-\tlslpl\tr3, r3, #3\n-\tit\tmi\n-\tmovmi\tr3, #0\n-\tmls\tr1, r0, ip, r1\n-\tmls\tsl, r2, lr, r1\n-\tcmp.w\tr8, #0\n-\tbne.w\t56aa <__gridxc_alloc_MOD_realloc_d3+0x682>\n-\tcmp\tr3, #1\n+\taddge.w\tr9, r9, #1\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #24]\n+\tstr\tr3, [sp, #24]\n+\torrs\tr0, r1\n+\trsb\tr1, fp, #0\n+\tmov\tip, r0\n+\tldr\tr0, [sp, #16]\n+\tmls\tr1, r6, r0, r1\n+\torrs.w\tr0, ip, r2\n+\tmls\tr1, sl, r3, r1\n+\tite\tpl\n+\tmovpl.w\tr0, r8, lsl #3\n+\tmovmi\tr0, #0\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tcmp.w\tr9, #0\n+\tbne.w\t530c <__gridxc_alloc_MOD_realloc_d3+0x628>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr3, #1\n-\tmov\tr0, r3\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t56b0 <__gridxc_alloc_MOD_realloc_d3+0x688>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #376]\t@ 5458 <__gridxc_alloc_MOD_realloc_d3+0x430>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r4, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tsl, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t5312 <__gridxc_alloc_MOD_realloc_d3+0x62e>\n+\tldr\tr3, [sp, #20]\n+\tstr\tr3, [r4, #32]\n \tldr\tr3, [sp, #16]\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tmov.w\tip, #4\n-\tvldr\td18, [pc, #312]\t@ 5440 <__gridxc_alloc_MOD_realloc_d3+0x418>\n-\tvldr\td19, [pc, #316]\t@ 5448 <__gridxc_alloc_MOD_realloc_d3+0x420>\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr0, [pc, #356]\t@ (5474 <__gridxc_alloc_MOD_realloc_d3+0x44c>)\n-\tvstr\td17, [sp, #404]\t@ 0x194\n-\tldr\tr1, [sp, #80]\t@ 0x50\n-\tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr3, [r4, #40]\t@ 0x28\n+\tldr\tr3, [sp, #28]\n+\tstr\tr3, [r4, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #24]\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tstr\tr3, [r4, #52]\t@ 0x34\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr3, [r4, #56]\t@ 0x38\n+\tmovs\tr3, #8\n+\tstr.w\tsl, [r4, #48]\t@ 0x30\n+\tmov.w\tsl, #1\n+\tstr.w\tfp, [r4, #28]\n+\tstr\tr6, [r4, #36]\t@ 0x24\n+\tstr\tr1, [r4, #4]\n+\tstrd\tr3, sl, [r4, #20]\n+\tldr\tr0, [pc, #908]\t@ (533c <__gridxc_alloc_MOD_realloc_d3+0x658>)\n+\tmovs\tr6, #1\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tmov.w\tip, #2\n+\tadd\tr0, pc\n+\tldr\tr3, [sp, #516]\t@ 0x204\n \tcmp\tr1, #0\n-\tvldr\td16, [pc, #300]\t@ 5450 <__gridxc_alloc_MOD_realloc_d3+0x428>\n-\tldr\tr6, [sp, #608]\t@ 0x260\n-\tmov\tr9, r2\n-\tldr\tr7, [sp, #604]\t@ 0x25c\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tmov\tsl, r1\n+\tstr\tr7, [sp, #336]\t@ 0x150\n+\tstr.w\tr9, [r0, #16]!\n+\tit\tne\n+\tmovne\tr9, r3\n+\tldr\tr3, [sp, #520]\t@ 0x208\n \tit\teq\n-\tmoveq\tr7, #0\n+\tmoveq.w\tr9, #0\n \tcmp\tr2, #0\n-\tvst1.32\t{d16}, [r3]\n-\tit\teq\n-\tmoveq\tr6, #0\n-\tstr.w\tr8, [r0, #16]!\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tmov\tr8, r1\n-\tstr\tr6, [sp, #4]\n-\tstr\tr7, [sp, #0]\n-\tstr.w\tip, [sp, #400]\t@ 0x190\n+\tstr.w\tr9, [sp]\n+\tite\tne\n+\tmovne\tr8, r3\n+\tmoveq.w\tr8, #0\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tmov\tfp, r2\n+\tstr.w\tr8, [sp, #4]\n+\tmovs\tr7, #4\n+\tstrd\tr6, r6, [sp, #360]\t@ 0x168\n+\tstr\tr6, [sp, #376]\t@ 0x178\n+\tstr\tr7, [sp, #356]\t@ 0x164\n+\tstr\tr7, [sp, #344]\t@ 0x158\n+\tmovs\tr7, #0\n+\tstrd\tip, ip, [sp, #368]\t@ 0x170\n \tmov.w\tip, #258\t@ 0x102\n-\tstrh.w\tip, [sp, #408]\t@ 0x198\n+\tstrd\tr7, r7, [sp, #348]\t@ 0x15c\n+\tstrh.w\tip, [sp, #352]\t@ 0x160\n \tmov.w\tip, #3\n-\tstr.w\tip, [sp, #436]\t@ 0x1b4\n+\tstr.w\tip, [sp, #380]\t@ 0x17c\n \tmvn.w\tip, #2\n-\tstr.w\tip, [sp, #396]\t@ 0x18c\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tstrd\tr7, r6, [sp, #4]\n-\tadd\tr0, sp, #148\t@ 0x94\n+\tstr.w\tip, [sp, #340]\t@ 0x154\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tstrd\tr9, r8, [sp, #4]\n+\tadd\tr0, sp, #92\t@ 0x5c\n+\tstr\tr6, [sp, #0]\n \tldrd\tr2, r3, [r4, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r4, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r4, #52]\t@ 0x34\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #232]\t@ (5478 <__gridxc_alloc_MOD_realloc_d3+0x450>)\n-\tadds\tr2, #1\n+\tldr\tr1, [pc, #760]\t@ (5340 <__gridxc_alloc_MOD_realloc_d3+0x65c>)\n+\tadd\tr2, r6\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r8\n+\tmov\tr2, sl\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r9\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr3, r9, [r4, #52]\t@ 0x34\n-\tldrd\tr0, r6, [r4, #40]\t@ 0x28\n-\tcmp\tr3, r9\n-\tbgt.n\t547c <__gridxc_alloc_MOD_realloc_d3+0x454>\n-\tcmp\tr0, r6\n-\tbgt.n\t547c <__gridxc_alloc_MOD_realloc_d3+0x454>\n-\tldrd\tr2, r1, [r4, #28]\n-\tcmp\tr2, r1\n-\tbgt.n\t547c <__gridxc_alloc_MOD_realloc_d3+0x454>\n-\tldr.w\tlr, [r4, #24]\n+\tmov\tr3, fp\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr0, r9, [r4, #52]\t@ 0x34\n+\tldrd\tlr, r6, [r4, #40]\t@ 0x28\n+\tcmp\tr0, r9\n+\tbgt.n\t50f0 <__gridxc_alloc_MOD_realloc_d3+0x40c>\n+\tcmp\tlr, r6\n+\tbgt.n\t50f0 <__gridxc_alloc_MOD_realloc_d3+0x40c>\n+\tldrd\tr3, r1, [r4, #28]\n+\tcmp\tr3, r1\n+\tbgt.n\t50f0 <__gridxc_alloc_MOD_realloc_d3+0x40c>\n+\tmov\tr2, r7\n+\tldr\tr7, [r4, #24]\n \tadds\tr1, #1\n \tldr.w\tsl, [r4, #48]\t@ 0x30\n-\tsubs\tr1, r1, r2\n \tldr.w\tip, [r4, #36]\t@ 0x24\n+\tsubs\tr1, r1, r3\n \tadd.w\tr9, r9, #1\n-\tldr\tr7, [r4, #20]\n-\tsub.w\tr9, r9, r3\n-\tmul.w\tfp, lr, r2\n-\tldr\tr2, [r4, #4]\n \tadds\tr6, #1\n-\tvmov.i64\td16, #0x0000000000000000\n-\tsubs\tr6, r6, r0\n-\tstr\tr4, [sp, #28]\n-\tmov.w\tr8, #0\n-\tstr\tr5, [sp, #40]\t@ 0x28\n-\tmla\tr2, r3, sl, r2\n-\tmul.w\tr3, r0, ip\n-\tmul.w\tr0, lr, r7\n+\tmul.w\tfp, r7, r3\n+\tldr\tr3, [r4, #4]\n+\tsub.w\tr9, r9, r0\n+\tsub.w\tr6, r6, lr\n+\tvldr\td7, [pc, #644]\t@ 5320 <__gridxc_alloc_MOD_realloc_d3+0x63c>\n+\tstrd\tfp, r4, [sp, #20]\n+\tmla\tr8, r0, sl, r3\n+\tstr\tr5, [sp, #28]\n+\tmul.w\tr3, lr, ip\n \tldr.w\tlr, [r4]\n-\tmov\tr4, r9\n-\tstr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #16]\n+\tldrd\tr7, r3, [r4, #20]\n+\tmul.w\tr0, r3, r7\n+\tldr\tr3, [sp, #16]\n+\tmov.w\tfp, #0\n+\tadd.w\tr5, r8, r3\n \tldr\tr3, [sp, #20]\n-\tmov.w\tr9, #0\n-\tstr\tr2, [sp, #16]\n-\tadds\tr5, r2, r3\n-\tadd\tr5, fp\n-\tmla\tr2, r7, r5, lr\n+\tadd\tr5, r3\n+\tmla\tr4, r7, r5, lr\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tvstr\td16, [r2]\n-\tcmp\tr3, r1\n-\tadd\tr2, r0\n-\tbne.n\t5418 <__gridxc_alloc_MOD_realloc_d3+0x3f0>\n-\tadd.w\tr9, r9, #1\n+\tvstr\td7, [r4]\n+\tcmp\tr1, r3\n+\tadd\tr4, r0\n+\tbne.n\t50ce <__gridxc_alloc_MOD_realloc_d3+0x3ea>\n+\tadd.w\tfp, fp, #1\n \tadd\tr5, ip\n-\tcmp\tr9, r6\n-\tbne.n\t5412 <__gridxc_alloc_MOD_realloc_d3+0x3ea>\n-\tldr\tr2, [sp, #16]\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr8, r4\n-\tadd\tr2, sl\n-\tbne.n\t5406 <__gridxc_alloc_MOD_realloc_d3+0x3de>\n-\tldr\tr4, [sp, #28]\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tb.n\t547c <__gridxc_alloc_MOD_realloc_d3+0x454>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000414\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000402\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002fe\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000026e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000015a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000e2\n- R_ARM_REL32\t.LC27\n-\tldr\tr3, [pc, #600]\t@ (56d8 <__gridxc_alloc_MOD_realloc_d3+0x6b0>)\n+\tcmp\tr6, fp\n+\tbne.n\t50c8 <__gridxc_alloc_MOD_realloc_d3+0x3e4>\n+\tadds\tr2, #1\n+\tadd\tr8, sl\n+\tcmp\tr9, r2\n+\tbne.n\t50ba <__gridxc_alloc_MOD_realloc_d3+0x3d6>\n+\tldrd\tr4, r5, [sp, #24]\n+\tldr\tr3, [pc, #592]\t@ (5344 <__gridxc_alloc_MOD_realloc_d3+0x660>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t560e <__gridxc_alloc_MOD_realloc_d3+0x5e6>\n+\tbeq.w\t5278 <__gridxc_alloc_MOD_realloc_d3+0x594>\n \tldrd\tr3, r0, [r5, #16]\n \tcmp\tr3, r0\n-\tbgt.n\t5550 <__gridxc_alloc_MOD_realloc_d3+0x528>\n+\tbgt.n\t51c4 <__gridxc_alloc_MOD_realloc_d3+0x4e0>\n \tldr\tr6, [r5, #8]\n \tldr\tr1, [r5, #12]\n \tldrd\tr9, r2, [r5]\n \tcmp\tr6, r1\n \tmov\tr5, r6\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tbgt.n\t5550 <__gridxc_alloc_MOD_realloc_d3+0x528>\n+\tstr\tr6, [sp, #56]\t@ 0x38\n+\tbgt.n\t51c4 <__gridxc_alloc_MOD_realloc_d3+0x4e0>\n \tcmp\tr9, r2\n-\tbgt.n\t5550 <__gridxc_alloc_MOD_realloc_d3+0x528>\n+\tbgt.n\t51c4 <__gridxc_alloc_MOD_realloc_d3+0x4e0>\n \tadds\tr0, #1\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tldr\tr0, [sp, #24]\n+\tstr\tr0, [sp, #64]\t@ 0x40\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n \tadd.w\tfp, r1, #1\n-\tldr.w\tlr, [sp, #476]\t@ 0x1dc\n+\tldr.w\tlr, [sp, #420]\t@ 0x1a4\n \tadd.w\tip, r2, #1\n \tldr\tr7, [r4, #24]\n-\tldr\tr1, [sp, #488]\t@ 0x1e8\n+\tldr\tr1, [sp, #432]\t@ 0x1b0\n \tmul.w\tr6, r9, r0\n \tldr.w\tr8, [r4, #20]\n-\tstr\tr6, [sp, #56]\t@ 0x38\n+\tstr\tr6, [sp, #60]\t@ 0x3c\n \tldr\tr6, [sp, #36]\t@ 0x24\n \tldr\tr2, [r4, #0]\n \tstr\tr2, [sp, #16]\n \tmul.w\tr2, r5, lr\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #68]\t@ 0x44\n \tldr\tr2, [r4, #4]\n \tmul.w\tsl, r6, lr\n-\tstr\tr1, [sp, #52]\t@ 0x34\n+\tstr\tr1, [sp, #48]\t@ 0x30\n \tmul.w\tlr, r8, r7\n \tstr\tr2, [sp, #40]\t@ 0x28\n \tmul.w\tr0, r6, r0\n \tldr\tr2, [r4, #48]\t@ 0x30\n \tmul.w\tr1, r1, r3\n \tmul.w\tr7, r9, r7\n \tstr\tr2, [sp, #44]\t@ 0x2c\n \tldr\tr2, [r4, #36]\t@ 0x24\n \tstr\tr2, [sp, #20]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tstrd\tr1, r3, [sp, #24]\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tstrd\tr3, r1, [sp, #24]\n \tadds\tr5, r1, r2\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldr\tr2, [sp, #68]\t@ 0x44\n \tadd\tr5, r2\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd\tr5, r2\n \tldrd\tr2, r4, [sp, #32]\n \tmla\tr5, r4, r5, r2\n \tldrd\tr2, r4, [sp, #40]\t@ 0x28\n \tmla\tr6, r3, r4, r2\n-\tldr\tr4, [sp, #64]\t@ 0x40\n+\tldr\tr4, [sp, #56]\t@ 0x38\n \tldr\tr3, [sp, #20]\n \tmov\tr1, r5\n \tldr\tr2, [sp, #16]\n \tmla\tr3, r4, r3, r6\n \tadd\tr3, r7\n \tmla\tr3, r8, r3, r2\n \tmov\tr2, r9\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr2, #1\n \tadd\tr1, r0\n-\tcmp\tip, r2\n-\tvstr\td16, [r3]\n+\tcmp\tr2, ip\n+\tvstr\td7, [r3]\n \tadd\tr3, lr\n-\tbne.n\t5526 <__gridxc_alloc_MOD_realloc_d3+0x4fe>\n+\tbne.n\t519a <__gridxc_alloc_MOD_realloc_d3+0x4b6>\n \tadds\tr4, #1\n \tadd\tr5, sl\n \tcmp\tfp, r4\n-\tbne.n\t5514 <__gridxc_alloc_MOD_realloc_d3+0x4ec>\n-\tldrd\tr1, r3, [sp, #24]\n-\tldr\tr2, [sp, #52]\t@ 0x34\n+\tbne.n\t5188 <__gridxc_alloc_MOD_realloc_d3+0x4a4>\n+\tldrd\tr3, r1, [sp, #24]\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadds\tr3, #1\n \tadd\tr1, r2\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #64]\t@ 0x40\n \tcmp\tr3, r2\n-\tbne.n\t54f2 <__gridxc_alloc_MOD_realloc_d3+0x4ca>\n-\tldr\tr5, [sp, #80]\t@ 0x50\n-\tadd\tr0, sp, #148\t@ 0x94\n-\tldr\tr6, [sp, #84]\t@ 0x54\n+\tbne.n\t5166 <__gridxc_alloc_MOD_realloc_d3+0x482>\n+\tldr\tr5, [sp, #76]\t@ 0x4c\n+\tadd\tr0, sp, #92\t@ 0x5c\n+\tldr\tr6, [sp, #80]\t@ 0x50\n \tmovs\tr4, #1\n-\tldr\tr3, [sp, #604]\t@ 0x25c\n+\tldr\tr3, [sp, #516]\t@ 0x204\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n \tstr\tr3, [sp, #4]\n-\tstr\tr3, [sp, #604]\t@ 0x25c\n-\tldr\tr3, [sp, #608]\t@ 0x260\n+\tstr\tr3, [sp, #516]\t@ 0x204\n+\tldr\tr3, [sp, #520]\t@ 0x208\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tstr\tr3, [sp, #608]\t@ 0x260\n-\tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n+\tstr\tr3, [sp, #520]\t@ 0x208\n+\tldrd\tr2, r3, [sp, #424]\t@ 0x1a8\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [sp, #468]\t@ 0x1d4\n+\tldrd\tr1, r2, [sp, #412]\t@ 0x19c\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [sp, #492]\t@ 0x1ec\n+\tldrd\tr1, r2, [sp, #436]\t@ 0x1b4\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #328]\t@ (56dc <__gridxc_alloc_MOD_realloc_d3+0x6b4>)\n+\tldr\tr1, [pc, #320]\t@ (5348 <__gridxc_alloc_MOD_realloc_d3+0x664>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr3, [sp, #32]\n-\tcbz\tr3, 55ba <__gridxc_alloc_MOD_realloc_d3+0x592>\n+\tcbz\tr3, 522e <__gridxc_alloc_MOD_realloc_d3+0x54a>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tvldr\td18, [pc, #252]\t@ 56c0 <__gridxc_alloc_MOD_realloc_d3+0x698>\n-\tvldr\td19, [pc, #256]\t@ 56c8 <__gridxc_alloc_MOD_realloc_d3+0x6a0>\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr0, [pc, #272]\t@ (56e0 <__gridxc_alloc_MOD_realloc_d3+0x6b8>)\n-\tvldr\td17, [pc, #256]\t@ 56d0 <__gridxc_alloc_MOD_realloc_d3+0x6a8>\n+\tldr\tr0, [pc, #284]\t@ (534c <__gridxc_alloc_MOD_realloc_d3+0x668>)\n+\tmovs\tr5, #0\n+\tldr\tr3, [sp, #84]\t@ 0x54\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tldrd\tr1, r2, [sp, #76]\t@ 0x4c\n+\tstrd\tr5, r5, [sp, #348]\t@ 0x15c\n \tstr.w\tr4, [r0, #16]!\n-\tldr\tr4, [sp, #608]\t@ 0x260\n-\tldrd\tr1, r2, [sp, #80]\t@ 0x50\n-\tvst1.32\t{d17}, [r3]\n+\tldr\tr4, [sp, #520]\t@ 0x208\n \tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #604]\t@ 0x25c\n+\tldr\tr4, [sp, #516]\t@ 0x204\n \tstr\tr4, [sp, #0]\n+\tmovs\tr4, #1\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tstrd\tr4, r4, [sp, #360]\t@ 0x168\n+\tstr\tr4, [sp, #376]\t@ 0x178\n \tmovs\tr4, #4\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tstr\tr4, [sp, #400]\t@ 0x190\n+\tstr\tr4, [sp, #356]\t@ 0x164\n+\tstr\tr4, [sp, #344]\t@ 0x158\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [sp, #404]\t@ 0x194\n-\tstrh.w\tr4, [sp, #408]\t@ 0x198\n-\tmovs\tr4, #3\n-\tstr\tr4, [sp, #436]\t@ 0x1b4\n+\tstrh.w\tr4, [sp, #352]\t@ 0x160\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [sp, #368]\t@ 0x170\n \tmvn.w\tr4, #2\n-\tstr\tr4, [sp, #396]\t@ 0x18c\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #212]\t@ (56e4 <__gridxc_alloc_MOD_realloc_d3+0x6bc>)\n-\tldr\tr3, [pc, #212]\t@ (56e8 <__gridxc_alloc_MOD_realloc_d3+0x6c0>)\n+\tstr\tr4, [sp, #340]\t@ 0x154\n+\tmovs\tr4, #3\n+\tstr\tr4, [sp, #380]\t@ 0x17c\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #212]\t@ (5350 <__gridxc_alloc_MOD_realloc_d3+0x66c>)\n+\tldr\tr3, [pc, #176]\t@ (532c <__gridxc_alloc_MOD_realloc_d3+0x648>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #500]\t@ 0x1f4\n+\tldr\tr3, [sp, #444]\t@ 0x1bc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t56ba <__gridxc_alloc_MOD_realloc_d3+0x692>\n-\tadd\tsp, #508\t@ 0x1fc\n-\tvpop\t{d8-d11}\n+\tbne.n\t531c <__gridxc_alloc_MOD_realloc_d3+0x638>\n+\tadd\tsp, #452\t@ 0x1c4\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #224\t@ 0xe0\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tb.n\t5108 <__gridxc_alloc_MOD_realloc_d3+0xe0>\n-\tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n-\tadd\tr0, sp, #148\t@ 0x94\n-\tldr\tr6, [sp, #80]\t@ 0x50\n+\tadd\tr3, sp, #168\t@ 0xa8\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tb.n\t4dc0 <__gridxc_alloc_MOD_realloc_d3+0xdc>\n+\tldrd\tr2, r3, [sp, #424]\t@ 0x1a8\n+\tadd\tr0, sp, #92\t@ 0x5c\n+\tstr\tr6, [sp, #0]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [sp, #468]\t@ 0x1d4\n+\tldr\tr6, [sp, #76]\t@ 0x4c\n+\tldrd\tr1, r2, [sp, #412]\t@ 0x19c\n \tadds\tr3, #1\n \tcmp\tr6, #0\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadd.w\tr2, r2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [sp, #492]\t@ 0x1ec\n+\tldrd\tr1, r2, [sp, #436]\t@ 0x1b4\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #136]\t@ (56ec <__gridxc_alloc_MOD_realloc_d3+0x6c4>)\n+\tldr\tr1, [pc, #136]\t@ (5354 <__gridxc_alloc_MOD_realloc_d3+0x670>)\n \tadd.w\tr2, r2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #84]\t@ 0x54\n+\tldr\tr2, [sp, #80]\t@ 0x50\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr\tr3, [sp, #604]\t@ 0x25c\n+\tldr\tr3, [sp, #516]\t@ 0x204\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr2, #0\n \tstr\tr3, [sp, #4]\n-\tmov.w\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #608]\t@ 0x260\n+\tldr\tr3, [sp, #520]\t@ 0x208\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r2\n \tmov\tr2, r6\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [sp, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tr9, [r8, #16]\n-\tstr.w\tr9, [sp, #32]\n-\tb.n\t51fc <__gridxc_alloc_MOD_realloc_d3+0x1d4>\n-\tmovw\tr8, #5014\t@ 0x1396\n-\tb.n\t52f8 <__gridxc_alloc_MOD_realloc_d3+0x2d0>\n-\tmovw\tr8, #5020\t@ 0x139c\n-\tb.n\t52f8 <__gridxc_alloc_MOD_realloc_d3+0x2d0>\n-\tmov\tr8, r2\n-\tb.n\t5260 <__gridxc_alloc_MOD_realloc_d3+0x238>\n+\tstr.w\tsl, [r9, #16]\n+\tstr.w\tsl, [sp, #32]\n+\tb.n\t4e98 <__gridxc_alloc_MOD_realloc_d3+0x1b4>\n+\tmovw\tr9, #5014\t@ 0x1396\n+\tb.n\t4fae <__gridxc_alloc_MOD_realloc_d3+0x2ca>\n+\tmovw\tr9, #5020\t@ 0x139c\n+\tb.n\t4fae <__gridxc_alloc_MOD_realloc_d3+0x2ca>\n+\tmov\tr9, sl\n+\tb.n\t4f00 <__gridxc_alloc_MOD_realloc_d3+0x21c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000256\n+\t...\n+\t.word\t0x00000624\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000614\n R_ARM_REL32\t.bss\n-\t.word\t0x00000142\n+\t.word\t0x0000054e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000498\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000380\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002f2\n R_ARM_REL32\t.LC27\n-\t.word\t0x0000010a\n+\t.word\t0x0000024e\n R_ARM_REL32\t.bss\n-\t.word\t0x000000ce\n+\t.word\t0x0000013a\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000114\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000d0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000080\n R_ARM_REL32\t.LC27\n \n-000056f0 <__gridxc_alloc_MOD_realloc_d2>:\n+00005358 <__gridxc_alloc_MOD_realloc_d2>:\n __gridxc_alloc_MOD_realloc_d2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3664]\t@ 0xe50\n-\tldr\tr4, [pc, #928]\t@ (5aa8 <__gridxc_alloc_MOD_realloc_d2+0x3b8>)\n-\tsub\tsp, #380\t@ 0x17c\n+\tstr.w\tr0, [ip, #3712]\t@ 0xe80\n+\tldr.w\tr5, [pc, #1228]\t@ 5838 <__gridxc_alloc_MOD_realloc_d2+0x4e0>\n \tmov\tr8, r0\n-\tldr\tr0, [pc, #928]\t@ (5aac <__gridxc_alloc_MOD_realloc_d2+0x3bc>)\n-\tadd\tr4, pc\n-\tstr\tr3, [sp, #20]\n-\tldr\tr5, [sp, #436]\t@ 0x1b4\n-\tldr\tr0, [r4, r0]\n-\tldr\tr4, [pc, #920]\t@ (5ab0 <__gridxc_alloc_MOD_realloc_d2+0x3c0>)\n+\tldr.w\tr0, [pc, #1228]\t@ 583c <__gridxc_alloc_MOD_realloc_d2+0x4e4>\n+\tsub\tsp, #348\t@ 0x15c\n+\tadd\tr5, pc\n+\tmov\tr9, r3\n+\tldr\tr6, [sp, #388]\t@ 0x184\n+\tldr\tr0, [r5, r0]\n+\tldr.w\tr5, [pc, #1216]\t@ 5840 <__gridxc_alloc_MOD_realloc_d2+0x4e8>\n \tldr\tr0, [r0, #0]\n-\tstr\tr0, [sp, #372]\t@ 0x174\n+\tstr\tr0, [sp, #340]\t@ 0x154\n \tmov.w\tr0, #0\n \tldr.w\tr0, [r8]\n-\tadd\tr4, pc\n-\tstr\tr5, [sp, #32]\n+\tadd\tr5, pc\n+\tstr\tr6, [sp, #28]\n \tcmp\tr0, #0\n-\tldr\tr5, [sp, #440]\t@ 0x1b8\n-\tstr\tr5, [sp, #28]\n+\tldr\tr4, [sp, #384]\t@ 0x180\n+\tite\tne\n+\tmovne\tr6, #1\n+\tmoveq\tr6, #0\n+\tstr\tr6, [r5, #0]\n+\tldr\tr5, [sp, #392]\t@ 0x188\n+\tldrd\tr6, r7, [sp, #396]\t@ 0x18c\n+\tstr\tr5, [sp, #32]\n \tit\teq\n-\tmoveq\tr9, r0\n-\tmov.w\tr5, #1\n-\tldr\tr6, [sp, #432]\t@ 0x1b0\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tstr\tr5, [r4, #0]\n-\tldrd\tr4, r5, [sp, #444]\t@ 0x1bc\n-\tbeq.n\t5794 <__gridxc_alloc_MOD_realloc_d2+0xa4>\n+\tstreq\tr0, [sp, #16]\n+\tbeq.n\t5406 <__gridxc_alloc_MOD_realloc_d2+0xae>\n \tldr.w\tr3, [r8, #44]\t@ 0x2c\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tldr.w\tr3, [r8, #28]\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr.w\tr3, [r8, #32]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr.w\tr3, [r8, #36]\t@ 0x24\n+\tstr\tr3, [sp, #72]\t@ 0x48\n \tldr.w\tr3, [r8, #4]\n-\tldr.w\tr7, [r8, #40]\t@ 0x28\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr.w\tr3, [r8, #24]\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr.w\tr3, [r8, #20]\n+\tldr.w\tr5, [r8, #40]\t@ 0x28\n+\tstr\tr3, [sp, #16]\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tstr\tr7, [sp, #64]\t@ 0x40\n-\tsub.w\tip, r3, r7\n-\tldr\tr7, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tldr.w\tsl, [r8, #36]\t@ 0x24\n-\tldrd\tr9, fp, [r8, #20]\n-\tcmp\tr7, r3\n-\tblt.w\t5bf0 <__gridxc_alloc_MOD_realloc_d2+0x500>\n+\tstr\tr5, [sp, #52]\t@ 0x34\n+\tsub.w\tip, r3, r5\n+\tldrd\tr3, r5, [sp, #44]\t@ 0x2c\n+\tcmp\tr5, r3\n+\tblt.w\t57fe <__gridxc_alloc_MOD_realloc_d2+0x4a6>\n \tcmp.w\tip, #0\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tmov\tip, r7\n-\tblt.w\t5c06 <__gridxc_alloc_MOD_realloc_d2+0x516>\n-\tldr\tr7, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tmov\tip, r5\n+\tblt.w\t5814 <__gridxc_alloc_MOD_realloc_d2+0x4bc>\n+\tldr\tr5, [sp, #52]\t@ 0x34\n \tldr.w\tlr, [sp, #40]\t@ 0x28\n-\tstrd\tip, r7, [sp, #164]\t@ 0xa4\n-\tstr.w\tlr, [sp, #172]\t@ 0xac\n+\tstrd\tip, r5, [sp, #136]\t@ 0x88\n+\tstr.w\tlr, [sp, #144]\t@ 0x90\n \tstr\tr0, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #748]\t@ 5a88 <__gridxc_alloc_MOD_realloc_d2+0x398>\n-\tvldr\td19, [pc, #752]\t@ 5a90 <__gridxc_alloc_MOD_realloc_d2+0x3a0>\n-\tadd\tr7, sp, #320\t@ 0x140\n-\tldr\tr0, [r3, #0]\n-\tldr\tr3, [r6, #0]\n-\tadd\tr6, sp, #356\t@ 0x164\n-\tldr\tr1, [r1, #0]\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr0, r3, [sp, #96]\t@ 0x60\n-\tadd\tr3, sp, #196\t@ 0xc4\n-\tstrd\tr1, r2, [sp, #88]\t@ 0x58\n-\tadd\tr0, sp, #340\t@ 0x154\n-\tvldr\td17, [pc, #732]\t@ 5a98 <__gridxc_alloc_MOD_realloc_d2+0x3a8>\n-\tmovs\tr2, #2\n-\tvldr\td20, [sp, #88]\t@ 0x58\n-\tvldr\td21, [sp, #96]\t@ 0x60\n-\tvstr\td16, [sp, #184]\t@ 0xb8\n-\tvstr\td16, [sp, #188]\t@ 0xbc\n-\tadd\tr1, sp, #128\t@ 0x80\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #212\t@ 0xd4\n-\tvstr\td16, [sp, #232]\t@ 0xe8\n-\tvst1.32\t{d17}, [r3]\n-\tadd\tr3, sp, #244\t@ 0xf4\n-\tvstr\td16, [sp, #236]\t@ 0xec\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #260\t@ 0x104\n-\tvstr\td16, [sp, #284]\t@ 0x11c\n-\tvst1.32\t{d17}, [r3]\n+\tldr.w\tr3, [r9]\n+\tmovs\tr5, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r1, #0]\n+\tadd.w\tip, sp, #100\t@ 0x64\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tmvn.w\tr1, #2\n+\tldr\tr3, [r4, #0]\n+\tadd\tr4, sp, #84\t@ 0x54\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tadd.w\tr9, sp, #116\t@ 0x74\n+\tldr\tr3, [r2, #0]\n+\tmovs\tr2, #0\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tadd\tr3, sp, #292\t@ 0x124\n-\tstr\tr0, [sp, #52]\t@ 0x34\n-\tstr\tr2, [sp, #220]\t@ 0xdc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd\tr3, sp, #308\t@ 0x134\n-\tstr\tr2, [sp, #268]\t@ 0x10c\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr\tr2, [sp, #316]\t@ 0x13c\n+\tstrd\tr2, r2, [sp, #156]\t@ 0x9c\n+\tstr\tr3, [sp, #24]\n+\tmovs\tr3, #2\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tstrd\tr2, r2, [sp, #204]\t@ 0xcc\n+\tstr\tr2, [sp, #212]\t@ 0xd4\n \tstr\tr3, [sp, #180]\t@ 0xb4\n+\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n \tstr\tr3, [sp, #228]\t@ 0xe4\n-\tvstr\td16, [sp, #328]\t@ 0x148\n+\tstr\tr3, [sp, #240]\t@ 0xf0\n+\tstr\tr3, [sp, #232]\t@ 0xe8\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tstr\tr0, [sp, #216]\t@ 0xd8\n+\tstr\tr1, [sp, #152]\t@ 0x98\n+\tstr\tr1, [sp, #200]\t@ 0xc8\n+\tstrd\tr5, r5, [sp, #172]\t@ 0xac\n+\tstr\tr5, [sp, #188]\t@ 0xbc\n+\tstrd\tr5, r5, [sp, #220]\t@ 0xdc\n+\tstr\tr5, [sp, #236]\t@ 0xec\n+\tstr\tr4, [sp, #148]\t@ 0x94\n+\tstr.w\tip, [sp, #196]\t@ 0xc4\n+\tstrd\tr6, r7, [sp]\n+\tadd\tr6, sp, #132\t@ 0x84\n \tstr\tr6, [sp, #56]\t@ 0x38\n-\tstr\tr7, [sp, #48]\t@ 0x30\n-\tvstr\td20, [sp, #112]\t@ 0x70\n-\tvstr\td21, [sp, #120]\t@ 0x78\n-\tstr\tr3, [sp, #276]\t@ 0x114\n-\tstrd\tr4, r5, [sp]\n-\tadd\tr5, sp, #112\t@ 0x70\n-\tldr\tr4, [pc, #644]\t@ (5ab4 <__gridxc_alloc_MOD_realloc_d2+0x3c4>)\n-\tstr\tr2, [sp, #364]\t@ 0x16c\n-\tadd\tr2, sp, #272\t@ 0x110\n-\tadd\tr4, pc\n-\tstr\tr3, [sp, #324]\t@ 0x144\n-\tvstr\td16, [sp, #332]\t@ 0x14c\n-\tmov\tr3, r7\n-\tvst1.32\t{d18-d19}, [r0]\n-\tadd\tr0, sp, #176\t@ 0xb0\n-\tstr\tr1, [sp, #176]\t@ 0xb0\n-\tadd\tr1, sp, #144\t@ 0x90\n-\tvst1.32\t{d17}, [r6]\n-\tstr\tr1, [sp, #224]\t@ 0xe0\n-\tadd\tr1, sp, #160\t@ 0xa0\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #272]\t@ 0x110\n-\tadd\tr1, sp, #224\t@ 0xe0\n-\tstr\tr5, [sp, #320]\t@ 0x140\n-\tbl\t1fc <__gridxc_alloc_MOD_options.constprop.1>\n-\tldr\tr3, [r4, #8]\n-\tcbz\tr3, 5866 <__gridxc_alloc_MOD_realloc_d2+0x176>\n-\tldr\tr6, [r4, #12]\n-\tcmp\tr6, #0\n-\tbeq.w\t5b96 <__gridxc_alloc_MOD_realloc_d2+0x4a6>\n-\tldr\tr3, [pc, #592]\t@ (5ab8 <__gridxc_alloc_MOD_realloc_d2+0x3c8>)\n+\tstr\tr6, [sp, #244]\t@ 0xf4\n+\tldr\tr6, [pc, #980]\t@ (5844 <__gridxc_alloc_MOD_realloc_d2+0x4ec>)\n+\tstrd\tr1, r2, [sp, #296]\t@ 0x128\n+\tadd\tr6, pc\n+\tstr\tr0, [sp, #264]\t@ 0x108\n+\tstr\tr0, [sp, #312]\t@ 0x138\n+\tadd\tr0, sp, #148\t@ 0x94\n+\tstrd\tr2, r2, [sp, #252]\t@ 0xfc\n+\tstr\tr2, [sp, #260]\t@ 0x104\n+\tstrd\tr5, r3, [sp, #272]\t@ 0x110\n+\tstrd\tr5, r3, [sp, #284]\t@ 0x11c\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tstr\tr1, [sp, #248]\t@ 0xf8\n+\tadd\tr1, sp, #196\t@ 0xc4\n+\tstrd\tr2, r2, [sp, #304]\t@ 0x130\n+\tadd\tr2, sp, #244\t@ 0xf4\n+\tstrd\tr5, r3, [sp, #320]\t@ 0x140\n+\tstrd\tr5, r3, [sp, #332]\t@ 0x14c\n+\tstr\tr3, [sp, #328]\t@ 0x148\n+\tldr\tr3, [sp, #24]\n+\tstr\tr5, [sp, #268]\t@ 0x10c\n+\tstr\tr5, [sp, #316]\t@ 0x13c\n+\tstr.w\tr9, [sp, #292]\t@ 0x124\n+\tbl\t1ec <__gridxc_alloc_MOD_options.constprop.1>\n+\tldr\tr3, [r6, #8]\n+\tcbz\tr3, 54ba <__gridxc_alloc_MOD_realloc_d2+0x162>\n+\tldr\tr7, [r6, #12]\n+\tcmp\tr7, #0\n+\tbeq.w\t57a8 <__gridxc_alloc_MOD_realloc_d2+0x450>\n+\tldr\tr3, [pc, #908]\t@ (5848 <__gridxc_alloc_MOD_realloc_d2+0x4f0>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t5a08 <__gridxc_alloc_MOD_realloc_d2+0x318>\n-\tldrd\tr4, r0, [sp, #128]\t@ 0x80\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r6, [sp, #136]\t@ 0x88\n-\tsubs\tr2, r0, r4\n-\torr.w\tr1, r2, r2, asr #31\n-\tvstr\td16, [r8, #12]\n+\tbeq.w\t5662 <__gridxc_alloc_MOD_realloc_d2+0x30a>\n+\tldrd\tsl, r3, [r4]\n+\tmovs\tr5, #0\n+\tldrd\tfp, r2, [r4, #8]\n+\tsub.w\tr6, r3, sl\n+\trsb\tr4, sl, #0\n+\tstr\tr3, [sp, #20]\n+\torr.w\tr7, r6, r6, asr #31\n+\tsub.w\tr1, r2, fp\n+\torrs\tr6, r1\n+\tstrd\tr5, r5, [r8, #12]\n+\torr.w\tr1, r1, r1, asr #31\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tmla\tr0, r7, fp, fp\n+\tlsrs\tr6, r6, #31\n+\tadds\tr7, #1\n \tadds\tr1, #1\n-\tstr\tr4, [sp, #72]\t@ 0x48\n-\tnegs\tr4, r4\n-\tstrd\tr1, r3, [sp, #80]\t@ 0x50\n-\tstr\tr0, [sp, #76]\t@ 0x4c\n-\tmovs\tr0, #8\n-\tvldr\td8, [sp, #72]\t@ 0x48\n-\tvldr\td9, [sp, #80]\t@ 0x50\n-\tmls\tr4, r1, r3, r4\n-\tsubs\tr3, r6, r3\n+\tsub.w\tr3, r4, r0\n+\tmov.w\tr0, #8\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tstr.w\tr0, [r8, #8]\n-\torrs\tr2, r3\n \tmovw\tr0, #770\t@ 0x302\n-\torr.w\tr3, r3, r3, asr #31\n \tstrh.w\tr0, [r8, #16]\n-\tlsrs\tr2, r2, #31\n-\tadds\tr3, #1\n-\tbeq.w\t5c0e <__gridxc_alloc_MOD_realloc_d2+0x51e>\n+\tbeq.w\t581c <__gridxc_alloc_MOD_realloc_d2+0x4c4>\n+\tmul.w\tr4, r1, r7\n \tmvn.w\tr0, #2147483648\t@ 0x80000000\n-\tudiv\tr0, r0, r3\n-\tmul.w\tr3, r1, r3\n-\tcmp.w\tr3, #536870912\t@ 0x20000000\n-\tit\tlt\n-\tmovlt\tr7, #0\n-\tit\tge\n-\tmovge\tr7, #1\n-\tcmp\tr0, r1\n-\tmov.w\tr0, r3, lsl #3\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp.w\tr4, #536870912\t@ 0x20000000\n+\tite\tlt\n+\tmovlt\tr1, #0\n+\tmovge\tr1, #1\n+\tcmp\tr0, r7\n \tit\tlt\n-\taddlt\tr7, #1\n-\tcbz\tr2, 58e4 <__gridxc_alloc_MOD_realloc_d2+0x1f4>\n-\tmovs\tr0, #0\n-\tcmp\tr7, #0\n-\tbne.w\t5c1a <__gridxc_alloc_MOD_realloc_d2+0x52a>\n+\taddlt\tr1, #1\n+\tlsls\tr0, r4, #3\n+\tcbz\tr6, 5534 <__gridxc_alloc_MOD_realloc_d2+0x1dc>\n+\tmov\tr0, r5\n+\tcmp\tr1, #0\n+\tbne.w\t5828 <__gridxc_alloc_MOD_realloc_d2+0x4d0>\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr.w\tr0, [r8]\n \tcmp\tr0, #0\n-\tbeq.w\t5c20 <__gridxc_alloc_MOD_realloc_d2+0x530>\n-\tadd.w\tr3, r8, #28\n-\tstr.w\tr6, [r8, #44]\t@ 0x2c\n-\tvldr\td16, [pc, #408]\t@ 5aa0 <__gridxc_alloc_MOD_realloc_d2+0x3b0>\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r8, #20\n-\tstr.w\tr4, [r8, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t582e <__gridxc_alloc_MOD_realloc_d2+0x4d6>\n+\tldr\tr3, [sp, #20]\n+\tmovs\tr2, #1\n+\tstr.w\tr3, [r8, #32]\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr.w\tr3, [r8, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tstr.w\tr3, [r8, #4]\n+\tmovs\tr3, #8\n+\tstrd\tr3, r2, [r8, #20]\n \tmovs\tr3, #0\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tvldr\td18, [pc, #356]\t@ 5a88 <__gridxc_alloc_MOD_realloc_d2+0x398>\n-\tvldr\td19, [pc, #360]\t@ 5a90 <__gridxc_alloc_MOD_realloc_d2+0x3a0>\n-\tstr\tr5, [sp, #320]\t@ 0x140\n-\tvldr\td16, [pc, #360]\t@ 5a98 <__gridxc_alloc_MOD_realloc_d2+0x3a8>\n-\tmovs\tr6, #4\n-\tvstr\td17, [sp, #332]\t@ 0x14c\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr0, [pc, #380]\t@ (5abc <__gridxc_alloc_MOD_realloc_d2+0x3cc>)\n-\tldr\tr7, [sp, #32]\n+\tstr.w\tsl, [r8, #28]\n+\tstr.w\tfp, [r8, #40]\t@ 0x28\n+\tstr.w\tr7, [r8, #36]\t@ 0x24\n+\tldr\tr0, [pc, #724]\t@ (584c <__gridxc_alloc_MOD_realloc_d2+0x4f4>)\n+\tmovs\tr5, #1\n+\tldr\tr1, [sp, #28]\n+\tmovs\tr4, #2\n \tadd\tr0, pc\n-\tldr\tr4, [sp, #452]\t@ 0x1c4\n-\tvst1.32\t{d16}, [r2]\n-\tcmp\tr7, #0\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #32]\n+\tcmp\tr1, #0\n+\tmov.w\tip, #258\t@ 0x102\n \tit\teq\n-\tmoveq\tr4, #0\n-\tldr\tr5, [sp, #456]\t@ 0x1c8\n-\tmov\tr1, r7\n-\tcmp\tr2, #0\n+\tmoveq\tr6, #0\n+\tmov\tsl, r2\n \tstr.w\tr3, [r0, #16]!\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr4, [sp, #0]\n-\tstr\tr5, [sp, #4]\n-\tstr\tr6, [sp, #328]\t@ 0x148\n-\tmov.w\tr6, #258\t@ 0x102\n-\tstrh.w\tr6, [sp, #336]\t@ 0x150\n-\tmovs\tr6, #2\n-\tstr\tr6, [sp, #364]\t@ 0x16c\n-\tmvn.w\tr6, #2\n-\tstr\tr6, [sp, #324]\t@ 0x144\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tstrd\tr4, r5, [sp, #4]\n-\tadd\tr0, sp, #108\t@ 0x6c\n+\tldr\tr3, [sp, #404]\t@ 0x194\n+\tstr.w\tr9, [sp, #292]\t@ 0x124\n+\tmov\tr9, r1\n+\tit\tne\n+\tmovne\tr6, r3\n+\tldr\tr3, [sp, #408]\t@ 0x198\n+\tcmp\tr2, #0\n+\tstr\tr6, [sp, #0]\n+\tite\tne\n+\tmovne\tr7, r3\n+\tmoveq\tr7, #0\n+\tldr\tr3, [sp, #24]\n+\tstr\tr7, [sp, #4]\n+\tstrd\tr5, r5, [sp, #316]\t@ 0x13c\n+\tstr\tr5, [sp, #332]\t@ 0x14c\n+\tstr\tr4, [sp, #324]\t@ 0x144\n+\tstr\tr4, [sp, #336]\t@ 0x150\n+\tstr\tr4, [sp, #328]\t@ 0x148\n+\tmovs\tr4, #4\n+\tstr\tr4, [sp, #312]\t@ 0x138\n+\tstr\tr4, [sp, #300]\t@ 0x12c\n+\tmovs\tr4, #0\n+\tstrd\tr4, r4, [sp, #304]\t@ 0x130\n+\tstrh.w\tip, [sp, #308]\t@ 0x134\n+\tmvn.w\tip, #2\n+\tstr.w\tip, [sp, #296]\t@ 0x128\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tstr\tr5, [sp, #0]\n+\tadd\tr0, sp, #80\t@ 0x50\n+\tstrd\tr6, r7, [sp, #4]\n \tldrd\tr2, r3, [r8, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r8, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r5\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n-\tldr\tr1, [pc, #296]\t@ (5ac0 <__gridxc_alloc_MOD_realloc_d2+0x3d0>)\n+\tadd\tr2, r5\n+\tldr\tr1, [pc, #604]\t@ (5850 <__gridxc_alloc_MOD_realloc_d2+0x4f8>)\n \tbic.w\tr2, r2, r2, asr #31\n \tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r7\n+\tmov\tr2, r9\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #28]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr0, r3, [r8, #40]\t@ 0x28\n-\tldrd\tr4, r1, [r8, #28]\n-\tcmp\tr0, r3\n-\tbgt.n\t5a08 <__gridxc_alloc_MOD_realloc_d2+0x318>\n+\tmov\tr3, sl\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr2, r3, [r8, #40]\t@ 0x28\n+\tldrd\tr5, r1, [r8, #28]\n+\tcmp\tr2, r3\n+\tbgt.n\t5662 <__gridxc_alloc_MOD_realloc_d2+0x30a>\n \tldr.w\tr7, [r8, #36]\t@ 0x24\n-\tcmp\tr4, r1\n-\tbgt.n\t5a08 <__gridxc_alloc_MOD_realloc_d2+0x318>\n+\tcmp\tr5, r1\n+\tbgt.n\t5662 <__gridxc_alloc_MOD_realloc_d2+0x30a>\n \tadds\tr3, #1\n \tldr.w\tip, [r8, #20]\n-\tsubs\tr6, r3, r0\n+\tsubs\tr6, r3, r2\n \tldr.w\tr3, [r8, #4]\n \tadds\tr1, #1\n \tldr.w\tlr, [r8]\n-\tsubs\tr1, r1, r4\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmovs\tr5, #0\n-\tmla\tr3, r0, r7, r3\n-\tldr.w\tr0, [r8, #24]\n-\tmla\tr4, r0, r4, r3\n-\tmul.w\tr0, r0, ip\n-\tmla\tr2, ip, r4, lr\n+\tsubs\tr1, r1, r5\n+\tmov.w\tsl, #0\n+\tmov.w\tfp, #0\n+\tmla\tr3, r2, r7, r3\n+\tldr.w\tr2, [r8, #24]\n+\tmla\tr5, r2, r5, r3\n+\tmul.w\tr0, r2, ip\n+\tmla\tr2, ip, r5, lr\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tvstr\td16, [r2]\n-\tcmp\tr3, r1\n+\tstrd\tsl, fp, [r2]\n+\tcmp\tr1, r3\n \tadd\tr2, r0\n-\tbne.n\t59f4 <__gridxc_alloc_MOD_realloc_d2+0x304>\n-\tadds\tr5, #1\n-\tadd\tr4, r7\n-\tcmp\tr6, r5\n-\tbne.n\t59ee <__gridxc_alloc_MOD_realloc_d2+0x2fe>\n-\tldr\tr3, [pc, #184]\t@ (5ac4 <__gridxc_alloc_MOD_realloc_d2+0x3d4>)\n+\tbne.n\t564e <__gridxc_alloc_MOD_realloc_d2+0x2f6>\n+\tadds\tr4, #1\n+\tadd\tr5, r7\n+\tcmp\tr6, r4\n+\tbne.n\t5648 <__gridxc_alloc_MOD_realloc_d2+0x2f0>\n+\tldr\tr3, [pc, #496]\t@ (5854 <__gridxc_alloc_MOD_realloc_d2+0x4fc>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t5b78 <__gridxc_alloc_MOD_realloc_d2+0x488>\n-\tldrd\tr4, r3, [sp, #152]\t@ 0x98\n+\tbeq.w\t578e <__gridxc_alloc_MOD_realloc_d2+0x436>\n+\tldrd\tr4, r3, [sp, #108]\t@ 0x6c\n \tcmp\tr4, r3\n-\tbgt.n\t5ac8 <__gridxc_alloc_MOD_realloc_d2+0x3d8>\n-\tldrd\tr6, r0, [sp, #144]\t@ 0x90\n+\tbgt.n\t56e6 <__gridxc_alloc_MOD_realloc_d2+0x38e>\n+\tldrd\tr6, r0, [sp, #100]\t@ 0x64\n \tcmp\tr6, r0\n-\tbgt.n\t5ac8 <__gridxc_alloc_MOD_realloc_d2+0x3d8>\n-\tldr\tr2, [sp, #24]\n-\tmul.w\tlr, r9, fp\n-\tadds\tr0, #1\n-\tmla\tr5, r4, sl, r2\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tmla\tr5, r6, fp, r5\n-\tmul.w\tsl, sl, r9\n-\tmla\tr5, r9, r5, r2\n+\tbgt.n\t56e6 <__gridxc_alloc_MOD_realloc_d2+0x38e>\n+\tldrd\tr1, r2, [sp, #72]\t@ 0x48\n \tadd.w\tr9, r3, #1\n \tldrd\tr7, r3, [r8, #20]\n-\tldrd\tfp, r2, [r8]\n-\tstr\tr2, [sp, #20]\n+\tadds\tr0, #1\n+\tmla\tr5, r4, r1, r2\n+\tldr\tr2, [sp, #16]\n \tmul.w\tip, r7, r3\n+\tmul.w\tsl, r1, r2\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tmla\tr5, r6, r1, r5\n+\tmul.w\tlr, r2, r1\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tmla\tr5, r2, r5, r1\n+\tldrd\tfp, r2, [r8]\n+\tstr\tr2, [sp, #16]\n \tldr.w\tr2, [r8, #36]\t@ 0x24\n \tmul.w\tr8, r6, r3\n-\tstr\tr2, [sp, #24]\n-\tldrd\tr3, r2, [sp, #20]\n+\tstr\tr2, [sp, #20]\n+\tldrd\tr3, r2, [sp, #16]\n \tmov\tr1, r5\n \tmla\tr3, r4, r2, r3\n \tmov\tr2, r6\n \tadd\tr3, r8\n \tmla\tr3, r7, r3, fp\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr2, #1\n \tadd\tr1, lr\n-\tcmp\tr0, r2\n-\tvstr\td16, [r3]\n+\tcmp\tr2, r0\n+\tvstr\td7, [r3]\n \tadd\tr3, ip\n-\tbne.n\t5a6c <__gridxc_alloc_MOD_realloc_d2+0x37c>\n+\tbne.n\t56cc <__gridxc_alloc_MOD_realloc_d2+0x374>\n \tadds\tr4, #1\n \tadd\tr5, sl\n-\tcmp\tr9, r4\n-\tbne.n\t5a5a <__gridxc_alloc_MOD_realloc_d2+0x36a>\n-\tb.n\t5ac8 <__gridxc_alloc_MOD_realloc_d2+0x3d8>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000398\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000038a\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000027e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000024c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000178\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000120\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000000b6\n- R_ARM_REL32\t.bss\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tadd\tr0, sp, #108\t@ 0x6c\n+\tcmp\tr4, r9\n+\tbne.n\t56ba <__gridxc_alloc_MOD_realloc_d2+0x362>\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadd\tr0, sp, #80\t@ 0x50\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tmovs\tr4, #1\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #28]\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldrd\tr1, r2, [sp, #44]\t@ 0x2c\n \tadds\tr3, #1\n-\tldr\tr5, [sp, #32]\n-\tsubs\tr2, r2, r1\n-\tadds\tr2, #1\n-\tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr5, #0\n+\tsub.w\tr2, r2, r1\n+\tbic.w\tr3, r3, r3, asr #31\n+\tadd.w\tr2, r2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #452]\t@ 0x1c4\n+\tldr\tr2, [sp, #404]\t@ 0x194\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr\tr2, [sp, #452]\t@ 0x1c4\n-\tldr\tr2, [sp, #28]\n+\tstr\tr2, [sp, #404]\t@ 0x194\n+\tldr\tr2, [sp, #32]\n \tnegs\tr3, r3\n-\tldr\tr1, [sp, #452]\t@ 0x1c4\n+\tldr\tr1, [sp, #404]\t@ 0x194\n \tcmp\tr2, #0\n \tstr\tr1, [sp, #4]\n-\tldr\tr1, [sp, #456]\t@ 0x1c8\n+\tldr\tr1, [sp, #408]\t@ 0x198\n \tit\teq\n \tmoveq\tr1, #0\n \tstr\tr1, [sp, #8]\n-\tstr\tr1, [sp, #456]\t@ 0x1c8\n-\tldr\tr1, [pc, #316]\t@ (5c48 <__gridxc_alloc_MOD_realloc_d2+0x558>)\n+\tstr\tr1, [sp, #408]\t@ 0x198\n+\tldr\tr1, [pc, #300]\t@ (5858 <__gridxc_alloc_MOD_realloc_d2+0x500>)\n \tstr\tr3, [r0, #0]\n \tmov\tr3, r2\n \tadd\tr1, pc\n \tmov\tr2, r5\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr3, [sp, #36]\t@ 0x24\n-\tcbz\tr3, 5b24 <__gridxc_alloc_MOD_realloc_d2+0x434>\n+\tcbz\tr3, 5746 <__gridxc_alloc_MOD_realloc_d2+0x3ee>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #320]\t@ 0x140\n-\tvldr\td18, [pc, #256]\t@ 5c30 <__gridxc_alloc_MOD_realloc_d2+0x540>\n-\tvldr\td19, [pc, #260]\t@ 5c38 <__gridxc_alloc_MOD_realloc_d2+0x548>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr0, [pc, #276]\t@ (5c4c <__gridxc_alloc_MOD_realloc_d2+0x55c>)\n-\tvldr\td17, [pc, #260]\t@ 5c40 <__gridxc_alloc_MOD_realloc_d2+0x550>\n-\tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n+\tldr\tr0, [pc, #276]\t@ (585c <__gridxc_alloc_MOD_realloc_d2+0x504>)\n+\tmovs\tr5, #0\n \tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr0, pc\n+\tstr\tr3, [sp, #292]\t@ 0x124\n+\tldrd\tr1, r2, [sp, #28]\n+\tstrd\tr5, r5, [sp, #304]\t@ 0x130\n \tstr.w\tr4, [r0, #16]!\n-\tldr\tr4, [sp, #456]\t@ 0x1c8\n-\tldrd\tr2, r1, [sp, #28]\n-\tvst1.32\t{d17}, [r3]\n+\tldr\tr4, [sp, #408]\t@ 0x198\n \tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #452]\t@ 0x1c4\n+\tldr\tr4, [sp, #404]\t@ 0x194\n \tstr\tr4, [sp, #0]\n-\tmovs\tr4, #4\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmovs\tr4, #1\n+\tldr\tr3, [sp, #24]\n+\tstrd\tr4, r4, [sp, #316]\t@ 0x13c\n+\tstr\tr4, [sp, #332]\t@ 0x14c\n+\tmovs\tr4, #2\n+\tstr\tr4, [sp, #324]\t@ 0x144\n+\tstr\tr4, [sp, #336]\t@ 0x150\n \tstr\tr4, [sp, #328]\t@ 0x148\n+\tmovs\tr4, #4\n+\tstr\tr4, [sp, #312]\t@ 0x138\n+\tstr\tr4, [sp, #300]\t@ 0x12c\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [sp, #332]\t@ 0x14c\n-\tstrh.w\tr4, [sp, #336]\t@ 0x150\n-\tmovs\tr4, #2\n-\tstr\tr4, [sp, #364]\t@ 0x16c\n+\tstrh.w\tr4, [sp, #308]\t@ 0x134\n \tmvn.w\tr4, #2\n-\tstr\tr4, [sp, #324]\t@ 0x144\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #212]\t@ (5c50 <__gridxc_alloc_MOD_realloc_d2+0x560>)\n-\tldr\tr3, [pc, #216]\t@ (5c54 <__gridxc_alloc_MOD_realloc_d2+0x564>)\n+\tstr\tr4, [sp, #296]\t@ 0x128\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #208]\t@ (5860 <__gridxc_alloc_MOD_realloc_d2+0x508>)\n+\tldr\tr3, [pc, #168]\t@ (583c <__gridxc_alloc_MOD_realloc_d2+0x4e4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #372]\t@ 0x174\n+\tldr\tr3, [sp, #340]\t@ 0x154\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t5c26 <__gridxc_alloc_MOD_realloc_d2+0x536>\n-\tadd\tsp, #380\t@ 0x17c\n-\tvpop\t{d8-d9}\n+\tbne.n\t5834 <__gridxc_alloc_MOD_realloc_d2+0x4dc>\n+\tadd\tsp, #348\t@ 0x15c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr0, sp, #108\t@ 0x6c\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldrd\tr2, r3, [sp, #44]\t@ 0x2c\n+\tadd\tr0, sp, #80\t@ 0x50\n+\tldr\tr1, [sp, #52]\t@ 0x34\n \tsubs\tr3, r3, r2\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tadds\tr3, #1\n-\tldr\tr7, [sp, #32]\n+\tstr\tr5, [sp, #0]\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #172]\t@ (5c58 <__gridxc_alloc_MOD_realloc_d2+0x568>)\n+\tldr\tr5, [sp, #28]\n \tadds\tr2, #1\n \tbic.w\tr3, r3, r3, asr #31\n-\tcmp\tr7, #0\n-\tadd\tr1, pc\n+\tcmp\tr5, #0\n+\tldr\tr1, [pc, #156]\t@ (5864 <__gridxc_alloc_MOD_realloc_d2+0x50c>)\n \tbic.w\tr2, r2, r2, asr #31\n+\tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #32]\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr\tr3, [sp, #452]\t@ 0x1c4\n+\tldr\tr3, [sp, #404]\t@ 0x194\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr2, #0\n \tstr\tr3, [sp, #4]\n-\tmov.w\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #456]\t@ 0x1c8\n+\tldr\tr3, [sp, #408]\t@ 0x198\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r2\n-\tmov\tr2, r7\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tmov\tr2, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr\tr6, [r4, #16]\n-\tstr\tr6, [sp, #36]\t@ 0x24\n-\tb.n\t5866 <__gridxc_alloc_MOD_realloc_d2+0x176>\n-\tmovs\tr7, #1\n+\tstr\tr7, [r6, #16]\n+\tstr\tr7, [sp, #36]\t@ 0x24\n+\tb.n\t54ba <__gridxc_alloc_MOD_realloc_d2+0x162>\n+\tmovs\tr5, #1\n \tcmp.w\tip, #0\n-\tstr\tr7, [sp, #160]\t@ 0xa0\n+\tstr\tr5, [sp, #132]\t@ 0x84\n \tmov.w\tip, #0\n-\tbge.w\t5784 <__gridxc_alloc_MOD_realloc_d2+0x94>\n+\tbge.w\t53f6 <__gridxc_alloc_MOD_realloc_d2+0x9e>\n \tmov.w\tlr, #0\n-\tb.n\t578a <__gridxc_alloc_MOD_realloc_d2+0x9a>\n-\tmovs\tr7, #1\n+\tb.n\t53fc <__gridxc_alloc_MOD_realloc_d2+0xa4>\n+\tmovs\tr5, #1\n \tmov.w\tlr, #0\n-\tb.n\t578a <__gridxc_alloc_MOD_realloc_d2+0x9a>\n-\tmov\tr0, r2\n-\tcmp\tr2, #0\n-\tbeq.w\t58ea <__gridxc_alloc_MOD_realloc_d2+0x1fa>\n+\tb.n\t53fc <__gridxc_alloc_MOD_realloc_d2+0xa4>\n+\tmov\tr0, r6\n+\tcmp\tr6, #0\n+\tbeq.w\t553a <__gridxc_alloc_MOD_realloc_d2+0x1e2>\n \tmovs\tr0, #1\n-\tb.n\t58f0 <__gridxc_alloc_MOD_realloc_d2+0x200>\n+\tb.n\t5540 <__gridxc_alloc_MOD_realloc_d2+0x1e8>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t591c <__gridxc_alloc_MOD_realloc_d2+0x22c>\n+\tb.n\t5576 <__gridxc_alloc_MOD_realloc_d2+0x21e>\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t591c <__gridxc_alloc_MOD_realloc_d2+0x22c>\n+\tb.n\t5576 <__gridxc_alloc_MOD_realloc_d2+0x21e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000136\n+\t.word\t0x000004c0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000004b0\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003cc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000388\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000254\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x000001ec\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000124\n R_ARM_REL32\t.LC27\n \t.word\t0x0000010c\n R_ARM_REL32\t.bss\n-\t.word\t0x000000d0\n+\t.word\t0x000000ca\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000a2\n+\t.word\t0x00000096\n R_ARM_REL32\t.LC27\n \n-00005c5c <__gridxc_alloc_MOD_realloc_d1>:\n+00005868 <__gridxc_alloc_MOD_realloc_d1>:\n __gridxc_alloc_MOD_realloc_d1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n-\tldr.w\tip, [pc, #892]\t@ 5ff0 <__gridxc_alloc_MOD_realloc_d1+0x394>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #892]\t@ (5ff4 <__gridxc_alloc_MOD_realloc_d1+0x398>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tlr, [pc, #888]\t@ 5ff8 <__gridxc_alloc_MOD_realloc_d1+0x39c>\n+\tldr.w\tr0, [pc, #1100]\t@ 5cc8 <__gridxc_alloc_MOD_realloc_d1+0x460>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1096]\t@ 5ccc <__gridxc_alloc_MOD_realloc_d1+0x464>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1088]\t@ 5cd0 <__gridxc_alloc_MOD_realloc_d1+0x468>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #328]\t@ 0x148\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #336]\t@ 0x150\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t5f96 <__gridxc_alloc_MOD_realloc_d1+0x33a>\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldrd\tr3, r2, [r4, #28]\n-\tstr\tr3, [r7, #24]\n-\tstr\tr2, [r7, #16]\n-\tcmp\tr2, r3\n+\titet\teq\n+\tstreq\tr3, [r7, #16]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t58e2 <__gridxc_alloc_MOD_realloc_d1+0x7a>\n+\tstr\tr3, [r7, #32]\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n-\tstr\tr3, [r7, #0]\n-\tldr\tr3, [r4, #24]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #16]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #752]\t@ 5fd0 <__gridxc_alloc_MOD_realloc_d1+0x374>\n-\tvldr\td19, [pc, #756]\t@ 5fd8 <__gridxc_alloc_MOD_realloc_d1+0x37c>\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #244\t@ 0xf4\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #100\t@ 0x64\n-\tvldr\td17, [pc, #744]\t@ 5fe0 <__gridxc_alloc_MOD_realloc_d1+0x384>\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #92]\t@ 0x5c\n-\tadd.w\tsl, r7, #64\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #116\t@ 0x74\n-\tldr.w\tr9, [pc, #740]\t@ 5ffc <__gridxc_alloc_MOD_realloc_d1+0x3a0>\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tadd.w\tr1, r7, #128\t@ 0x80\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #148\t@ 0x94\n-\tvstr\td16, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #220\t@ 0xdc\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #896]\t@ 5cd4 <__gridxc_alloc_MOD_realloc_d1+0x46c>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n \tadd\tr9, pc\n-\tvstr\td16, [r7, #184]\t@ 0xb8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #164\t@ 0xa4\n-\tvstr\td16, [r7, #188]\t@ 0xbc\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #196\t@ 0xc4\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tstr\tr2, [r7, #32]\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #212\t@ 0xd4\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tvst1.32\t{d18-d19}, [fp]\n-\tstr\tr3, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #124]\t@ 0x7c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tadd.w\tr3, r7, #48\t@ 0x30\n-\tstr.w\tr8, [r7, #172]\t@ 0xac\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n-\tstr\tr3, [r7, #20]\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tadd.w\tr2, r7, #176\t@ 0xb0\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #80\t@ 0x50\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 5e1a <__gridxc_alloc_MOD_realloc_d1+0x1be>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #8]\n-\tcmp\tr3, #0\n-\tbne.n\t5e54 <__gridxc_alloc_MOD_realloc_d1+0x1f8>\n-\tldr\tr2, [r7, #16]\n+\tcbz\tr3, 5a0c <__gridxc_alloc_MOD_realloc_d1+0x1a4>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t5a42 <__gridxc_alloc_MOD_realloc_d1+0x1da>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #24]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #548]\t@ (6000 <__gridxc_alloc_MOD_realloc_d1+0x3a4>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #780]\t@ (5cd8 <__gridxc_alloc_MOD_realloc_d1+0x470>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #8]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr3, [pc, #488]\t@ (6004 <__gridxc_alloc_MOD_realloc_d1+0x3a8>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #716]\t@ (5cdc <__gridxc_alloc_MOD_realloc_d1+0x474>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 5e5e <__gridxc_alloc_MOD_realloc_d1+0x202>\n-\tldr\tr3, [pc, #484]\t@ (6008 <__gridxc_alloc_MOD_realloc_d1+0x3ac>)\n+\tcbnz\tr3, 5a4c <__gridxc_alloc_MOD_realloc_d1+0x1e4>\n+\tldr\tr3, [pc, #712]\t@ (5ce0 <__gridxc_alloc_MOD_realloc_d1+0x478>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t5f9a <__gridxc_alloc_MOD_realloc_d1+0x33e>\n-\tldr\tr2, [pc, #476]\t@ (600c <__gridxc_alloc_MOD_realloc_d1+0x3b0>)\n-\tldr\tr3, [pc, #448]\t@ (5ff4 <__gridxc_alloc_MOD_realloc_d1+0x398>)\n+\tbne.w\t5b6c <__gridxc_alloc_MOD_realloc_d1+0x304>\n+\tldr\tr2, [pc, #704]\t@ (5ce4 <__gridxc_alloc_MOD_realloc_d1+0x47c>)\n+\tldr\tr3, [pc, #680]\t@ (5ccc <__gridxc_alloc_MOD_realloc_d1+0x464>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t6140 <__gridxc_alloc_MOD_realloc_d1+0x4e4>\n-\tadd.w\tr7, r7, #284\t@ 0x11c\n+\tbne.w\t5cb8 <__gridxc_alloc_MOD_realloc_d1+0x450>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t5f9a <__gridxc_alloc_MOD_realloc_d1+0x33e>\n-\tvldr\td8, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t5b6c <__gridxc_alloc_MOD_realloc_d1+0x304>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #8\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #769\t@ 0x301\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #536870912\t@ 0x20000000\n-\tbge.w\t614a <__gridxc_alloc_MOD_realloc_d1+0x4ee>\n+\tbge.w\t5cc2 <__gridxc_alloc_MOD_realloc_d1+0x45a>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #3\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t6144 <__gridxc_alloc_MOD_realloc_d1+0x4e8>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #312]\t@ 5fe8 <__gridxc_alloc_MOD_realloc_d1+0x38c>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t5cbc <__gridxc_alloc_MOD_realloc_d1+0x454>\n+\tmovs\tr3, #8\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #332]\t@ (6010 <__gridxc_alloc_MOD_realloc_d1+0x3b4>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #28]\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #584]\t@ (5ce8 <__gridxc_alloc_MOD_realloc_d1+0x480>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #272]\t@ 5fe0 <__gridxc_alloc_MOD_realloc_d1+0x384>\n-\tvldr\td18, [pc, #252]\t@ 5fd0 <__gridxc_alloc_MOD_realloc_d1+0x374>\n-\tvldr\td19, [pc, #256]\t@ 5fd8 <__gridxc_alloc_MOD_realloc_d1+0x37c>\n-\tvstr\td17, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tr1, r5\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n \tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #240]\t@ 0xf0\n-\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n \tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #32]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #220]\t@ (6014 <__gridxc_alloc_MOD_realloc_d1+0x3b8>)\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #480]\t@ (5cec <__gridxc_alloc_MOD_realloc_d1+0x484>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr.w\tip, [r4, #24]\n-\tldrd\tr0, r1, [r4, #28]\n-\tldrd\tr3, r2, [r4]\n-\tcmp\tr0, r1\n-\tbgt.w\t5e22 <__gridxc_alloc_MOD_realloc_d1+0x1c6>\n-\tadd\tr1, r8\n-\tmla\tr2, ip, r0, r2\n-\tsubs\tr1, r1, r0\n-\tldr\tr0, [r4, #20]\n-\tmov.w\tr8, #0\n-\tmov.w\tr9, #0\n-\tmla\tr3, r0, r2, r3\n-\tmovs\tr2, #0\n-\tmul.w\tr0, ip, r0\n-\tadds\tr2, #1\n-\tstrd\tr8, r9, [r3]\n-\tcmp\tr2, r1\n-\tadd\tr3, r0\n-\tbne.n\t5f88 <__gridxc_alloc_MOD_realloc_d1+0x32c>\n-\tb.n\t5e22 <__gridxc_alloc_MOD_realloc_d1+0x1c6>\n-\tstr\tr3, [r7, #12]\n-\tb.n\t5cd8 <__gridxc_alloc_MOD_realloc_d1+0x7c>\n-\tldrd\tr9, r2, [r7, #56]\t@ 0x38\n-\tmov\tsl, sp\n+\tldrd\tr1, r2, [r4, #28]\n+\tldrd\tr3, r0, [r4]\n+\tcmp\tr1, r2\n+\tbgt.w\t5a14 <__gridxc_alloc_MOD_realloc_d1+0x1ac>\n+\tadd\tr2, r9\n+\tmla\tr0, ip, r1, r0\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [r4, #20]\n+\tmov.w\tsl, #0\n+\tmov.w\tfp, #0\n+\tmla\tr3, r1, r0, r3\n+\tmul.w\tr1, ip, r1\n+\tadd.w\tr8, r8, #1\n+\tstrd\tsl, fp, [r3]\n+\tcmp\tr2, r8\n+\tadd\tr3, r1\n+\tbne.n\t5b5c <__gridxc_alloc_MOD_realloc_d1+0x2f4>\n+\tb.n\t5a14 <__gridxc_alloc_MOD_realloc_d1+0x1ac>\n+\tldrd\tr9, r2, [r7, #52]\t@ 0x34\n+\tmov\tfp, sp\n \tsubs.w\tr2, r2, r9\n-\tbmi.n\t6082 <__gridxc_alloc_MOD_realloc_d1+0x426>\n+\tbmi.n\t5c04 <__gridxc_alloc_MOD_realloc_d1+0x39c>\n \tlsls\tr3, r2, #3\n \tldr\tr1, [r4, #0]\n \tadds\tr3, #8\n-\tstr\tr1, [r7, #8]\n+\tstr\tr1, [r7, #12]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tldr\tr0, [r4, #4]\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tip, sp\n \tcmp\tip, r1\n-\tbeq.n\t6018 <__gridxc_alloc_MOD_realloc_d1+0x3bc>\n+\tbeq.n\t5b9e <__gridxc_alloc_MOD_realloc_d1+0x336>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t5fbc <__gridxc_alloc_MOD_realloc_d1+0x360>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000372\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000036a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ca\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000021e\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000140\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000d6\n- R_ARM_REL32\t.LC27\n+\tb.n\t5b8e <__gridxc_alloc_MOD_realloc_d1+0x326>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 6028 <__gridxc_alloc_MOD_realloc_d1+0x3cc>\n+\tcbz\tr3, 5bae <__gridxc_alloc_MOD_realloc_d1+0x346>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldrd\tr1, r3, [r7]\n+\tldrd\tr1, r3, [r7, #4]\n \tmov.w\tlr, #0\n+\tldr.w\tsl, [r4, #24]\n \tmla\tip, r9, r3, r1\n-\tldr\tr1, [r7, #12]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr8, r1, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #32]\n \tmla\tip, r1, ip, r3\n-\tldr\tr1, [r4, #24]\n \tadd\tr3, sp, #16\n-\tstr\tr1, [r7, #12]\n \tmov\tr1, r3\n-\tvldr\td16, [ip]\n+\tvldr\td7, [ip]\n \tadd.w\tlr, lr, #1\n \tadd\tip, r8\n \tcmp\tlr, r2\n-\tvstmia\tr1!, {d16}\n-\tble.n\t6048 <__gridxc_alloc_MOD_realloc_d1+0x3ec>\n-\tldr\tr1, [r7, #12]\n-\tmla\tr0, r9, r1, r0\n+\tvstmia\tr1!, {d7}\n+\tble.n\t5bce <__gridxc_alloc_MOD_realloc_d1+0x366>\n \tldr\tr1, [r4, #20]\n-\tldr\tr4, [r7, #8]\n-\tmla\tr0, r1, r0, r4\n+\tmla\tr0, r9, sl, r0\n \tldr\tr4, [r7, #12]\n-\tmul.w\tip, r4, r1\n+\tmul.w\tip, sl, r1\n+\tmla\tr0, r1, r0, r4\n \tmovs\tr4, #0\n \tldrd\tr8, r9, [r3], #8\n-\tcmp\tr2, r4\n+\tcmp\tr4, r2\n \tstrd\tr8, r9, [r0]\n \tadd.w\tr4, r4, #1\n \tadd\tr0, ip\n-\tbne.n\t6070 <__gridxc_alloc_MOD_realloc_d1+0x414>\n-\tldr\tr2, [r7, #24]\n+\tbne.n\t5bf2 <__gridxc_alloc_MOD_realloc_d1+0x38a>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #16]\n-\tmov\tsp, sl\n-\tldr\tr1, [pc, #220]\t@ (6168 <__gridxc_alloc_MOD_realloc_d1+0x50c>)\n+\tldr\tr3, [r7, #20]\n+\tmov\tsp, fp\n+\tldr\tr1, [pc, #224]\t@ (5cf0 <__gridxc_alloc_MOD_realloc_d1+0x488>)\n \tmov.w\tr4, #1\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n \tadd\tr1, pc\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #344]\t@ 0x158\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r5\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tcbz\tr3, 60e0 <__gridxc_alloc_MOD_realloc_d1+0x484>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 5c62 <__gridxc_alloc_MOD_realloc_d1+0x3fa>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #132]\t@ (616c <__gridxc_alloc_MOD_realloc_d1+0x510>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [pc, #144]\t@ (5cf4 <__gridxc_alloc_MOD_realloc_d1+0x48c>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #28]\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #88]\t@ 6150 <__gridxc_alloc_MOD_realloc_d1+0x4f4>\n-\tvldr\td19, [pc, #92]\t@ 6158 <__gridxc_alloc_MOD_realloc_d1+0x4fc>\n-\tvldr\td17, [pc, #96]\t@ 6160 <__gridxc_alloc_MOD_realloc_d1+0x504>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tstrh.w\tr4, [r7, #240]\t@ 0xf0\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #228]\t@ 0xe4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tldr\tr3, [r7, #32]\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t5e2e <__gridxc_alloc_MOD_realloc_d1+0x1d2>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t5a20 <__gridxc_alloc_MOD_realloc_d1+0x1b8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t5ec2 <__gridxc_alloc_MOD_realloc_d1+0x266>\n+\tb.n\t5a9c <__gridxc_alloc_MOD_realloc_d1+0x234>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t5ec2 <__gridxc_alloc_MOD_realloc_d1+0x266>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000ba\n+\tb.n\t5a9c <__gridxc_alloc_MOD_realloc_d1+0x234>\n+\t.word\t0x00000440\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000430\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000374\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000302\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002bc\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000023c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001d8\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000076\n+\t.word\t0x000000c0\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000086\n R_ARM_REL32\t.bss\n \n-00006170 <__gridxc_alloc_MOD_realloc_r4>:\n+00005cf8 <__gridxc_alloc_MOD_realloc_r4>:\n __gridxc_alloc_MOD_realloc_r4():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3424]\t@ 0xd60\n-\tsub.w\tsp, sp, #604\t@ 0x25c\n+\tstr.w\tr0, [ip, #3536]\t@ 0xdd0\n+\tsub.w\tsp, sp, #524\t@ 0x20c\n \tadd\tr7, sp, #16\n+\tmov\tr9, r2\n+\tldr.w\tr2, [pc, #1932]\t@ 64a0 <__gridxc_alloc_MOD_realloc_r4+0x7a8>\n \tmov\tr5, r0\n-\tstrd\tr2, r1, [r7, #104]\t@ 0x68\n-\tldr.w\tr2, [pc, #1156]\t@ 6618 <__gridxc_alloc_MOD_realloc_r4+0x4a8>\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n \tadd\tr2, pc\n-\tldr.w\tr3, [pc, #1148]\t@ 661c <__gridxc_alloc_MOD_realloc_r4+0x4ac>\n-\tstr\tr0, [r7, #96]\t@ 0x60\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n+\tldr.w\tr0, [r7, #544]\t@ 0x220\n+\tldr.w\tr3, [pc, #1924]\t@ 64a4 <__gridxc_alloc_MOD_realloc_r4+0x7ac>\n \tstr\tr0, [r7, #88]\t@ 0x58\n+\tldr.w\tr0, [r7, #548]\t@ 0x224\n+\tstr\tr0, [r7, #80]\t@ 0x50\n+\tstr\tr1, [r7, #96]\t@ 0x60\n \tldr\tr4, [r5, #0]\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n \tcmp\tr4, #0\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1120]\t@ 6620 <__gridxc_alloc_MOD_realloc_r4+0x4b0>\n-\tstr\tr2, [r7, #84]\t@ 0x54\n+\tldr.w\tr3, [pc, #1892]\t@ 64a8 <__gridxc_alloc_MOD_realloc_r4+0x7b0>\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tit\tne\n+\tmovne\tr2, #1\n \tadd\tr3, pc\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tmov.w\tr2, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tstr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #556]\t@ 0x22c\n \tstr\tr3, [r7, #72]\t@ 0x48\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tldr.w\tr3, [r7, #564]\t@ 0x234\n+\tstr\tr3, [r7, #56]\t@ 0x38\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tldr.w\tr3, [r7, #572]\t@ 0x23c\n \tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n \tstr\tr3, [r7, #40]\t@ 0x28\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tbeq.w\t68b6 <__gridxc_alloc_MOD_realloc_r4+0x746>\n+\tbeq.w\t6404 <__gridxc_alloc_MOD_realloc_r4+0x70c>\n \tmovs\tr2, #72\t@ 0x48\n \tmov\tr1, r5\n-\tadd.w\tr0, r7, #508\t@ 0x1fc\n+\tadd.w\tr0, r7, #428\t@ 0x1ac\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tstr\tr4, [r7, #68]\t@ 0x44\n-\tldrd\tr4, r3, [r7, #536]\t@ 0x218\n-\tldrd\tr0, r9, [r7, #548]\t@ 0x224\n-\tsubs.w\tr8, r3, r4\n-\tldrd\tr2, fp, [r7, #572]\t@ 0x23c\n+\tstr\tr4, [r7, #60]\t@ 0x3c\n+\tldrd\tr4, r6, [r7, #456]\t@ 0x1c8\n+\tldrd\tr0, sl, [r7, #468]\t@ 0x1d4\n+\tsubs.w\tr8, r6, r4\n+\tldr.w\tfp, [r7, #484]\t@ 0x1e4\n \tit\tmi\n \tmovmi\tr4, #1\n-\tldr.w\tsl, [r7, #564]\t@ 0x234\n-\tsubs.w\tlr, r9, r0\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n+\tsubs.w\tlr, sl, r0\n+\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n \tit\tmi\n \tmovmi\tr0, #1\n-\tstr.w\tr4, [r7, #280]\t@ 0x118\n-\tsubs.w\tip, sl, r1\n-\tstr.w\tr0, [r7, #288]\t@ 0x120\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tsubs.w\tip, fp, r1\n+\tstr\tr3, [r7, #100]\t@ 0x64\n \tit\tmi\n \tmovmi\tr1, #1\n-\tsubs.w\tr6, fp, r2\n+\tsubs\tr3, r3, r2\n+\tstr.w\tr4, [r7, #204]\t@ 0xcc\n \tit\tmi\n \tmovmi\tr2, #1\n \tcmp.w\tr8, #0\n \tit\tlt\n-\tmovlt\tr3, #0\n+\tmovlt\tr6, #0\n \tcmp.w\tlr, #0\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tmov.w\tlr, #0\n-\tldr\tr3, [r5, #4]\n \tit\tlt\n-\tmovlt\tr9, lr\n-\tstr\tr3, [r7, #28]\n-\tcmp\tip, lr\n-\tldr\tr3, [r5, #24]\n+\tmovlt.w\tsl, #0\n+\tcmp.w\tip, #0\n \tit\tlt\n-\tmovlt\tsl, lr\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n-\tcmp\tr6, lr\n-\tldr\tr3, [r5, #20]\n+\tmovlt.w\tfp, #0\n+\tcmp\tr3, #0\n+\tldr\tr3, [r7, #100]\t@ 0x64\n \tit\tlt\n-\tmovlt\tfp, lr\n-\tadd.w\tr6, r7, #280\t@ 0x118\n-\tstr.w\tr1, [r7, #296]\t@ 0x128\n-\tstr\tr6, [r7, #52]\t@ 0x34\n-\tstr.w\tr2, [r7, #304]\t@ 0x130\n-\tstr.w\tr9, [r7, #292]\t@ 0x124\n-\tstr.w\tsl, [r7, #300]\t@ 0x12c\n-\tstr.w\tfp, [r7, #308]\t@ 0x134\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n-\tldr\tr3, [r7, #88]\t@ 0x58\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr6, [r7, #104]\t@ 0x68\n-\tvldr\td18, [pc, #868]\t@ 65f8 <__gridxc_alloc_MOD_realloc_r4+0x488>\n-\tvldr\td19, [pc, #872]\t@ 6600 <__gridxc_alloc_MOD_realloc_r4+0x490>\n-\tldr\tr4, [r3, #0]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tmovlt\tr3, #0\n+\tstr\tr3, [r7, #100]\t@ 0x64\n+\tadd.w\tr3, r7, #204\t@ 0xcc\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tldr\tr3, [r5, #4]\n+\tstr\tr3, [r7, #20]\n+\tldr\tr3, [r5, #24]\n+\tstr.w\tr2, [r7, #228]\t@ 0xe4\n+\tstr\tr3, [r7, #24]\n+\tldr\tr2, [r7, #100]\t@ 0x64\n+\tldr\tr3, [r5, #20]\n+\tstr.w\tr0, [r7, #212]\t@ 0xd4\n+\tstr.w\tr1, [r7, #220]\t@ 0xdc\n+\tstr.w\tr6, [r7, #208]\t@ 0xd0\n+\tstr.w\tsl, [r7, #216]\t@ 0xd8\n+\tstr.w\tfp, [r7, #224]\t@ 0xe0\n+\tstr.w\tr2, [r7, #232]\t@ 0xe8\n+\tstr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr2, [r7, #80]\t@ 0x50\n+\tadd.w\tr8, r7, #172\t@ 0xac\n+\tldr\tr6, [r7, #76]\t@ 0x4c\n+\tmvn.w\tsl, #2\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tadd.w\tfp, r7, #340\t@ 0x154\n+\tldr\tr1, [r2, #0]\n+\tldr\tr2, [r7, #72]\t@ 0x48\n \tldr.w\tip, [r6]\n-\tldr\tr6, [r7, #100]\t@ 0x64\n-\tldr\tr0, [r3, #0]\n-\tldr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr4, [r7, #88]\t@ 0x58\n+\tldr\tr0, [r2, #0]\n+\tldr\tr6, [r7, #68]\t@ 0x44\n+\tldr\tr2, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r8, #24]\n+\tadd.w\tr0, r7, #236\t@ 0xec\n \tldr.w\tlr, [r6]\n-\tldr\tr6, [r7, #96]\t@ 0x60\n-\tldr\tr1, [r3, #0]\n-\tldr\tr3, [r7, #72]\t@ 0x48\n-\tldr.w\tr8, [r6]\n-\tadd.w\tr6, r7, #248\t@ 0xf8\n-\tvldr\td17, [pc, #844]\t@ 6608 <__gridxc_alloc_MOD_realloc_r4+0x498>\n-\tldr\tr2, [r3, #0]\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tvstr\td16, [r7, #320]\t@ 0x140\n-\tvstr\td16, [r7, #368]\t@ 0x170\n-\tldr\tr3, [r3, #0]\n-\tstrd\tr4, r0, [r7, #160]\t@ 0xa0\n-\tadd.w\tr0, r7, #312\t@ 0x138\n-\tstrd\tr1, r2, [r7, #168]\t@ 0xa8\n-\tadd.w\tr1, r7, #456\t@ 0x1c8\n-\tstrd\tr3, ip, [r7, #144]\t@ 0x90\n-\tadd.w\tr3, r7, #332\t@ 0x14c\n-\tvldr\td20, [r7, #160]\t@ 0xa0\n-\tvldr\td21, [r7, #168]\t@ 0xa8\n-\tstrd\tlr, r8, [r7, #152]\t@ 0x98\n-\tvstr\td16, [r7, #324]\t@ 0x144\n-\tadd.w\tr2, r7, #492\t@ 0x1ec\n-\tvstr\td16, [r7, #372]\t@ 0x174\n-\tadd.w\tr4, r7, #216\t@ 0xd8\n-\tvstr\td20, [r7, #200]\t@ 0xc8\n-\tvstr\td21, [r7, #208]\t@ 0xd0\n-\tldr.w\tr8, [pc, #792]\t@ 6624 <__gridxc_alloc_MOD_realloc_r4+0x4b4>\n-\tvldr\td20, [r7, #144]\t@ 0x90\n-\tvldr\td21, [r7, #152]\t@ 0x98\n-\tadd\tr8, pc\n-\tvstr\td20, [r7, #184]\t@ 0xb8\n-\tvstr\td21, [r7, #192]\t@ 0xc0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #348\t@ 0x15c\n-\tstr\tr1, [r7, #56]\t@ 0x38\n-\tadd.w\tr1, r7, #428\t@ 0x1ac\n-\tvst1.32\t{d17}, [r3]\n+\tldr\tr3, [r3, #0]\n+\tldr.w\tr6, [r9]\n+\tadd.w\tr9, r7, #108\t@ 0x6c\n+\tldr\tr2, [r2, #0]\n+\tldr\tr4, [r4, #0]\n+\tstr.w\tr2, [r8]\n+\tadd.w\tr2, r7, #332\t@ 0x14c\n+\tstr.w\tr3, [r8, #8]\n \tadd.w\tr3, r7, #380\t@ 0x17c\n-\tstr\tr2, [r7, #44]\t@ 0x2c\n-\tmovs\tr2, #4\n-\tvst1.32\t{d18-d19}, [r1]\n-\tadd.w\tr1, r7, #444\t@ 0x1bc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #396\t@ 0x18c\n-\tvst1.32\t{d17}, [r1]\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #476\t@ 0x1dc\n-\tldr\tr1, [r7, #52]\t@ 0x34\n+\tstr.w\tr1, [r8, #16]\n+\tadd.w\tr1, r7, #284\t@ 0x11c\n \tstr\tr3, [r7, #48]\t@ 0x30\n-\tmvn.w\tr3, #2\n-\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tstr\tr3, [r0, #4]\n-\tstrd\tr1, r3, [r7, #408]\t@ 0x198\n-\tadd.w\tr1, r7, #360\t@ 0x168\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tstr.w\tr3, [r7, #364]\t@ 0x16c\n-\tstr.w\tr2, [r7, #452]\t@ 0x1c4\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tvstr\td16, [r7, #464]\t@ 0x1d0\n-\tvstr\td16, [r7, #468]\t@ 0x1d4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tvst1.32\t{d17}, [r2]\n-\tadd.w\tr2, r7, #184\t@ 0xb8\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tstr.w\tr2, [r7, #456]\t@ 0x1c8\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tvstr\td16, [r7, #416]\t@ 0x1a0\n-\tstr\tr4, [r0, #0]\n-\tvstr\td16, [r7, #420]\t@ 0x1a4\n-\tstr.w\tr6, [r7, #360]\t@ 0x168\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #408\t@ 0x198\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tbl\t644 <__gridxc_alloc_MOD_options.constprop.3>\n-\tldr.w\tr3, [r8, #8]\n-\tcbz\tr3, 63cc <__gridxc_alloc_MOD_realloc_r4+0x25c>\n-\tldr.w\tr9, [r8, #12]\n-\tcmp.w\tr9, #0\n-\tbeq.w\t68c0 <__gridxc_alloc_MOD_realloc_r4+0x750>\n-\tldr\tr3, [pc, #600]\t@ (6628 <__gridxc_alloc_MOD_realloc_r4+0x4b8>)\n+\tstr.w\tr6, [r8, #4]\n+\tmovs\tr6, #1\n+\tstr.w\tr4, [r8, #12]\n+\tmovs\tr4, #0\n+\tstr.w\tip, [r8, #20]\n+\tmov.w\tip, #2\n+\tstr.w\tlr, [r8, #28]\n+\tmov.w\tlr, #4\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstr.w\tr4, [r7, #252]\t@ 0xfc\n+\tstrd\tr4, r4, [r7, #292]\t@ 0x124\n+\tstr.w\tr4, [r7, #300]\t@ 0x12c\n+\tstrd\tr6, r6, [r0, #24]\n+\tstr\tr6, [r0, #40]\t@ 0x28\n+\tstr.w\tr4, [r7, #340]\t@ 0x154\n+\tstrd\tr4, r4, [r7, #344]\t@ 0x158\n+\tldr\tr4, [r7, #44]\t@ 0x2c\n+\tstr.w\tsl, [r0, #4]\n+\tstrd\tr4, sl, [r7, #332]\t@ 0x14c\n+\tmovs\tr4, #0\n+\tstr.w\tsl, [r7, #288]\t@ 0x120\n+\tstr.w\tsl, [r7, #384]\t@ 0x180\n+\tldr.w\tsl, [pc, #1516]\t@ 64ac <__gridxc_alloc_MOD_realloc_r4+0x7b4>\n+\tstr.w\tlr, [r0, #20]\n+\tstr.w\tlr, [r0, #44]\t@ 0x2c\n+\tadd\tsl, pc\n+\tstr.w\tlr, [r7, #304]\t@ 0x130\n+\tstrd\tip, ip, [r0, #32]\n+\tstr.w\tr9, [r0]\n+\tstrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstrd\tr6, lr, [r7, #324]\t@ 0x144\n+\tstr.w\tip, [r7, #320]\t@ 0x140\n+\tstr.w\tlr, [r7, #352]\t@ 0x160\n+\tstrd\tr6, ip, [r7, #360]\t@ 0x168\n+\tstrd\tr6, lr, [r7, #372]\t@ 0x174\n+\tstr.w\tip, [r7, #368]\t@ 0x170\n+\tstr.w\tlr, [r7, #400]\t@ 0x190\n+\tstr.w\tlr, [r7, #424]\t@ 0x1a8\n+\tstrd\tr4, r4, [r7, #388]\t@ 0x184\n+\tstr.w\tr6, [r7, #308]\t@ 0x134\n+\tstr.w\tr6, [r7, #356]\t@ 0x164\n+\tstr.w\tr4, [r7, #396]\t@ 0x18c\n+\tadd.w\tr4, r7, #140\t@ 0x8c\n+\tstr\tr4, [r7, #100]\t@ 0x64\n+\tstr.w\tr4, [r7, #284]\t@ 0x11c\n+\tldr\tr4, [r7, #40]\t@ 0x28\n+\tstrd\tr6, ip, [r7, #408]\t@ 0x198\n+\tstr.w\tip, [r7, #416]\t@ 0x1a0\n+\tstr.w\tr6, [r7, #404]\t@ 0x194\n+\tstr.w\tr6, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr8, [r7, #380]\t@ 0x17c\n+\tstr\tr4, [sp, #4]\n+\tldr\tr4, [r7, #64]\t@ 0x40\n+\tstr\tr4, [sp, #0]\n+\tbl\t618 <__gridxc_alloc_MOD_options.constprop.3>\n+\tldr.w\tr3, [sl, #8]\n+\tcbz\tr3, 5f48 <__gridxc_alloc_MOD_realloc_r4+0x250>\n+\tldr.w\tfp, [sl, #12]\n+\tcmp.w\tfp, #0\n+\tbeq.w\t640e <__gridxc_alloc_MOD_realloc_r4+0x716>\n+\tldr.w\tr3, [pc, #1380]\t@ 64b0 <__gridxc_alloc_MOD_realloc_r4+0x7b8>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t66fa <__gridxc_alloc_MOD_realloc_r4+0x58a>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tlr, r3, [r4]\n-\tldrd\tfp, r1, [r4, #8]\n-\tvstr\td16, [r5, #12]\n-\tsub.w\tr2, r3, lr\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tsub.w\tr3, r1, fp\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\torr.w\tip, r2, r2, asr #31\n-\tstr.w\tlr, [r7, #128]\t@ 0x80\n-\tadd.w\tip, ip, #1\n-\tstr.w\tfp, [r7, #140]\t@ 0x8c\n-\tstr.w\tip, [r7, #136]\t@ 0x88\n-\tstr\tr2, [r7, #104]\t@ 0x68\n-\torr.w\tr2, r3, r3, asr #31\n-\tvldr\td10, [r7, #128]\t@ 0x80\n-\tvldr\td11, [r7, #136]\t@ 0x88\n-\tmovs\tr3, #4\n-\tadds\tr2, #1\n+\tbeq.w\t6252 <__gridxc_alloc_MOD_realloc_r4+0x55a>\n+\tldr.w\tr2, [r9, #4]\n+\tldr.w\tr6, [r9, #8]\n+\tldr.w\tr1, [r9]\n+\tldr.w\tr0, [r9, #12]\n+\tstr\tr1, [r7, #96]\t@ 0x60\n+\tsubs\tr1, r2, r1\n+\tstr\tr0, [r7, #64]\t@ 0x40\n+\tsubs\tr0, r0, r6\n+\torr.w\tr3, r1, r1, asr #31\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\torr.w\tsl, r0, r0, asr #31\n+\tmovs\tr2, #0\n+\tstr\tr6, [r7, #92]\t@ 0x5c\n+\tadds.w\tsl, sl, #1\n+\tadd.w\tr6, r3, #1\n+\tstrd\tr2, r2, [r5, #12]\n+\tmov.w\tr3, #4\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tstr\tr3, [r5, #8]\n \tmov.w\tr3, #772\t@ 0x304\n+\tstr\tr0, [r7, #40]\t@ 0x28\n \tstrh\tr3, [r5, #16]\n-\tbeq.w\t6afe <__gridxc_alloc_MOD_realloc_r4+0x98e>\n-\tmvn.w\tr8, #2147483648\t@ 0x80000000\n-\tudiv\tr8, r8, r2\n-\tcmp\tr8, ip\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr8, r3\n-\tldrd\tsl, r9, [r4, #16]\n-\tmul.w\tr2, r2, ip\n-\tstrd\tr1, r2, [r7, #112]\t@ 0x70\n-\tsub.w\tr3, r9, sl\n-\tstrd\tsl, r9, [r7, #120]\t@ 0x78\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\torr.w\tr3, r3, r3, asr #31\n-\tvldr\td8, [r7, #112]\t@ 0x70\n-\tvldr\td9, [r7, #120]\t@ 0x78\n-\tadds\tr3, #1\n-\tbeq.n\t6476 <__gridxc_alloc_MOD_realloc_r4+0x306>\n-\tmvn.w\tr1, #2147483648\t@ 0x80000000\n-\tmov\tr0, r8\n-\tudiv\tr1, r1, r3\n-\tcmp\tr1, r2\n+\tbeq.w\t667a <__gridxc_alloc_MOD_realloc_r4+0x982>\n+\tmov\tr1, sl\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r6\n+\tite\tge\n+\tmovge.w\tfp, #0\n+\tmovlt.w\tfp, #1\n+\tldr.w\tr3, [r9, #20]\n+\tmul.w\tsl, sl, r6\n+\tldr.w\tr2, [r9, #16]\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tsubs\tr3, r3, r2\n+\tstr\tr2, [r7, #88]\t@ 0x58\n+\tstr\tr3, [r7, #32]\n+\torr.w\tr1, r3, r3, asr #31\n+\tadds\tr1, #1\n+\tbeq.n\t5fe2 <__gridxc_alloc_MOD_realloc_r4+0x2ea>\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr1, [r7, #80]\t@ 0x50\n+\tcmp\tr0, sl\n \tit\tlt\n-\taddlt\tr0, #1\n-\tmov\tr8, r0\n-\tmul.w\tr9, r3, r2\n-\tldr\tr3, [r4, #28]\n-\tldr\tr4, [r4, #24]\n-\tstr\tr3, [r7, #96]\t@ 0x60\n-\tsubs\tr3, r3, r4\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\torr.w\tr3, r3, r3, asr #31\n+\taddlt.w\tfp, fp, #1\n+\tldr.w\tr3, [r9, #28]\n+\tmul.w\tr0, r1, sl\n+\tldr.w\tr2, [r9, #24]\n+\tstr\tr2, [r7, #80]\t@ 0x50\n+\tmov\tr4, r0\n+\tsubs\tr2, r3, r2\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n+\torr.w\tr3, r2, r2, asr #31\n \tadds\tr3, #1\n-\tbeq.n\t64ac <__gridxc_alloc_MOD_realloc_r4+0x33c>\n-\tmvn.w\tr1, #2147483648\t@ 0x80000000\n-\tmov\tr0, r8\n-\tudiv\tr1, r1, r3\n-\tmul.w\tr3, r3, r9\n-\tcmp\tr1, r9\n+\tbeq.n\t6028 <__gridxc_alloc_MOD_realloc_r4+0x330>\n+\tmov\tr1, r3\n+\tmul.w\tr3, r0, r3\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr2, [r7, #12]\n+\tstr\tr3, [r7, #16]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #16]\n+\tcmp\tr0, r4\n \tit\tlt\n-\taddlt\tr0, #1\n+\taddlt.w\tfp, fp, #1\n+\tldr\tr2, [r7, #12]\n \tcmp.w\tr3, #1073741824\t@ 0x40000000\n-\tmov\tr1, r0\n \tit\tge\n-\taddge\tr1, #1\n-\tmov\tr8, r1\n-\tldrd\tr0, r1, [r7, #104]\t@ 0x68\n-\torrs\tr0, r1\n-\tldr\tr1, [r7, #100]\t@ 0x64\n-\torrs\tr0, r1\n-\trsb\tr1, lr, #0\n-\tmls\tr1, ip, fp, r1\n-\tmls\tr1, r2, sl, r1\n-\tldr\tr2, [r7, #88]\t@ 0x58\n-\tmls\tfp, r9, r4, r1\n-\torrs\tr0, r2\n-\tit\tpl\n+\taddge.w\tfp, fp, #1\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tldr\tr4, [r7, #92]\t@ 0x5c\n+\torrs\tr1, r0\n+\tldr\tr0, [r7, #32]\n+\torr.w\tip, r1, r0\n+\tldr\tr0, [r7, #96]\t@ 0x60\n+\tnegs\tr0, r0\n+\tmls\tr0, r6, r4, r0\n+\tldr\tr4, [r7, #88]\t@ 0x58\n+\tmls\tr0, sl, r4, r0\n+\tldrd\tr1, r4, [r7, #76]\t@ 0x4c\n+\tmls\tr9, r1, r4, r0\n+\torrs.w\tr1, ip, r2\n+\tite\tpl\n \tlslpl\tr3, r3, #2\n-\tit\tmi\n \tmovmi\tr3, #0\n-\tcmp.w\tr8, #0\n-\tbne.w\t6af8 <__gridxc_alloc_MOD_realloc_r4+0x988>\n+\tcmp.w\tfp, #0\n+\tbne.w\t6674 <__gridxc_alloc_MOD_realloc_r4+0x97c>\n \tcmp\tr3, #1\n \tit\tcc\n \tmovcc\tr3, #1\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r5, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t6b06 <__gridxc_alloc_MOD_realloc_r4+0x996>\n-\tadd.w\tr3, r5, #28\n-\tvldr\td16, [pc, #284]\t@ 6610 <__gridxc_alloc_MOD_realloc_r4+0x4a0>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r5, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n+\tbeq.w\t6682 <__gridxc_alloc_MOD_realloc_r4+0x98a>\n \tldr\tr3, [r7, #96]\t@ 0x60\n+\tmovs\tr2, #1\n+\tstr\tr3, [r5, #28]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r5, #32]\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tstr\tr3, [r5, #40]\t@ 0x28\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r5, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #88]\t@ 0x58\n+\tstr\tr3, [r5, #52]\t@ 0x34\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r5, #56]\t@ 0x38\n+\tldr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r5, #64]\t@ 0x40\n+\tldr\tr3, [r7, #28]\n \tstr\tr3, [r5, #68]\t@ 0x44\n-\tadd.w\tr3, r5, #20\n-\tstr\tr4, [r5, #64]\t@ 0x40\n-\tstr.w\tr9, [r5, #60]\t@ 0x3c\n-\tstr.w\tfp, [r5, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvldr\td18, [pc, #212]\t@ 65f8 <__gridxc_alloc_MOD_realloc_r4+0x488>\n-\tvldr\td19, [pc, #216]\t@ 6600 <__gridxc_alloc_MOD_realloc_r4+0x490>\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tvstr\td17, [r7, #468]\t@ 0x1d4\n-\tvldr\td16, [pc, #212]\t@ 6608 <__gridxc_alloc_MOD_realloc_r4+0x498>\n-\tldr\tr0, [pc, #244]\t@ (662c <__gridxc_alloc_MOD_realloc_r4+0x4bc>)\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr1, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r5, #60]\t@ 0x3c\n+\tmovs\tr3, #4\n+\tstr\tr6, [r5, #36]\t@ 0x24\n+\tstr.w\tsl, [r5, #48]\t@ 0x30\n+\tstr.w\tr9, [r5, #4]\n+\tstrd\tr3, r2, [r5, #20]\n+\tldr.w\tr0, [pc, #1032]\t@ 64b4 <__gridxc_alloc_MOD_realloc_r4+0x7bc>\n+\tmovs\tr6, #1\n+\tldr\tr4, [r7, #56]\t@ 0x38\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tcmp\tr1, #0\n-\tmov\tr9, r1\n-\tvst1.32\t{d16}, [r3]\n-\tmov\tsl, r2\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tcmp\tr4, #0\n+\tstr.w\tr8, [r7, #380]\t@ 0x17c\n+\tmov.w\tr8, #0\n+\tstr.w\tfp, [r0, #16]!\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tstr.w\tr3, [r7, #388]\t@ 0x184\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tr8, [r0, #16]!\n+\tmoveq.w\tfp, #0\n+\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tmovs\tr3, #2\n+\tstrd\tr3, r3, [r7, #412]\t@ 0x19c\n \tcmp\tr2, #0\n-\tmov\tr8, r3\n-\tmov.w\tr3, #4\n-\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tit\teq\n+\tmoveq\tsl, r8\n+\tstrd\tr8, r8, [r7, #392]\t@ 0x188\n+\tmov\tr1, r4\n+\tit\tne\n+\tmovne\tsl, r3\n+\tstrd\tr6, r6, [r7, #404]\t@ 0x194\n \tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr6, [r7, #420]\t@ 0x1a4\n+\tstrh.w\tr3, [r7, #396]\t@ 0x18c\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tstr.w\tr8, [sp]\n-\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n-\tit\teq\n-\tmoveq\tr4, #0\n-\tstr\tr4, [sp, #4]\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n+\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tmov\tr9, r2\n+\tstrd\tfp, sl, [sp]\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #104\t@ 0x68\n \tldrd\tr2, r3, [r5, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r5, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r5, #52]\t@ 0x34\n \tsubs\tr2, r2, r1\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r5, #64]\t@ 0x40\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #108]\t@ (6630 <__gridxc_alloc_MOD_realloc_r4+0x4c0>)\n-\tadds\tr2, #1\n+\tldr\tr1, [pc, #864]\t@ (64b8 <__gridxc_alloc_MOD_realloc_r4+0x7c0>)\n+\tadd\tr2, r6\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r9\n+\tmov\tr2, r4\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr8, r4, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, sl\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr2, r4, [r5, #64]\t@ 0x40\n-\tldrd\tlr, r8, [r5, #52]\t@ 0x34\n-\tcmp\tr2, r4\n-\tbgt.w\t66fa <__gridxc_alloc_MOD_realloc_r4+0x58a>\n-\tcmp\tlr, r8\n-\tbgt.w\t66fa <__gridxc_alloc_MOD_realloc_r4+0x58a>\n-\tb.n\t6634 <__gridxc_alloc_MOD_realloc_r4+0x4c4>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x0000047a\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000045a\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000030c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000256\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000ea\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000066\n- R_ARM_REL32\t.LC28\n-\tldrd\tr9, ip, [r5, #40]\t@ 0x28\n-\tcmp\tr9, ip\n-\tbgt.n\t66fa <__gridxc_alloc_MOD_realloc_r4+0x58a>\n+\tmov\tr3, r9\n+\tstrd\tfp, sl, [sp, #4]\n+\tstr\tr6, [sp, #0]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr2, r0, [r5, #64]\t@ 0x40\n+\tldrd\tlr, sl, [r5, #52]\t@ 0x34\n+\tcmp\tr2, r0\n+\tbgt.n\t6252 <__gridxc_alloc_MOD_realloc_r4+0x55a>\n+\tcmp\tlr, sl\n+\tbgt.n\t6252 <__gridxc_alloc_MOD_realloc_r4+0x55a>\n+\tldrd\tr9, r6, [r5, #40]\t@ 0x28\n+\tcmp\tr9, r6\n+\tbgt.n\t6252 <__gridxc_alloc_MOD_realloc_r4+0x55a>\n \tldrd\tr3, r1, [r5, #28]\n \tcmp\tr3, r1\n-\tbgt.n\t66fa <__gridxc_alloc_MOD_realloc_r4+0x58a>\n-\tadd.w\tr0, r8, #1\n-\tadds\tr1, #1\n-\tsub.w\tr0, r0, lr\n-\tstr\tr0, [r7, #96]\t@ 0x60\n+\tbgt.n\t6252 <__gridxc_alloc_MOD_realloc_r4+0x55a>\n+\tadd.w\tip, r0, #1\n+\tadd.w\tr0, sl, #1\n+\tsub.w\tfp, r0, lr\n \tldr\tr0, [r5, #24]\n+\tadds\tr1, #1\n+\tsub.w\tr4, ip, r2\n \tsubs\tr1, r1, r3\n-\tadds\tr4, #1\n-\tldr.w\tfp, [r5, #48]\t@ 0x30\n-\tsubs\tr4, r4, r2\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tldr.w\tr8, [r5, #36]\t@ 0x24\n-\tadd.w\tip, ip, #1\n+\tldr.w\tsl, [r5, #48]\t@ 0x30\n+\tstr\tr4, [r7, #68]\t@ 0x44\n+\tadds\tr6, #1\n \tmul.w\tr3, r0, r3\n-\tsub.w\tip, ip, r9\n-\tstr\tr3, [r7, #100]\t@ 0x64\n+\tldr.w\tip, [r5, #20]\n+\tstr\tr3, [r7, #96]\t@ 0x60\n+\tsub.w\tr6, r6, r9\n \tldr\tr3, [r5, #60]\t@ 0x3c\n-\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tmov\tr4, r3\n \tldr\tr3, [r5, #4]\n-\tstrd\tr6, r5, [r7, #36]\t@ 0x24\n+\tstr.w\tr8, [r7, #88]\t@ 0x58\n+\tmul.w\tr0, r0, ip\n+\tldr.w\tr8, [r5]\n+\tvldr\ts15, [pc, #712]\t@ 649c <__gridxc_alloc_MOD_realloc_r4+0x7a4>\n \tmla\tr3, r2, r4, r3\n-\tmovs\tr4, #0\n-\tmul.w\tr2, lr, fp\n-\tldr.w\tlr, [r5, #20]\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tmul.w\tr2, r9, r8\n-\tldr.w\tr9, [r5]\n-\tstr\tr2, [r7, #104]\t@ 0x68\n-\tmovs\tr2, #0\n-\tmul.w\tr0, r0, lr\n-\tstr\tr2, [r7, #88]\t@ 0x58\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tstr.w\tfp, [r7, #108]\t@ 0x6c\n-\tadd.w\tsl, r3, r2\n+\tldr\tr4, [r7, #100]\t@ 0x64\n+\tmul.w\tr2, lr, sl\n+\tldr.w\tlr, [r5, #36]\t@ 0x24\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tmul.w\tr2, r9, lr\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #80]\t@ 0x50\n+\tadd.w\tr9, r3, r2\n+\tstrd\tr4, r5, [r7, #36]\t@ 0x24\n \tmovs\tr2, #0\n-\tstr\tr3, [r7, #32]\n-\tldr\tr3, [r7, #104]\t@ 0x68\n-\tmov.w\tfp, #0\n-\tadd.w\tr6, sl, r3\n-\tldr\tr3, [r7, #100]\t@ 0x64\n-\tadd\tr6, r3\n-\tmla\tr5, lr, r6, r9\n+\tmov\tr4, sl\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tmov.w\tsl, #0\n+\tstr\tr2, [r7, #100]\t@ 0x64\n+\tadd.w\tr5, r9, r3\n+\tldr\tr3, [r7, #96]\t@ 0x60\n+\tadd\tr5, r3\n+\tmla\tr2, ip, r5, r8\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tstr\tr4, [r5, #0]\n-\tcmp\tr1, r3\n-\tadd\tr5, r0\n-\tbne.n\t66c0 <__gridxc_alloc_MOD_realloc_r4+0x550>\n-\tadd.w\tfp, fp, #1\n-\tadd\tr6, r8\n-\tcmp\tip, fp\n-\tbne.n\t66ba <__gridxc_alloc_MOD_realloc_r4+0x54a>\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n+\tvstr\ts15, [r2]\n+\tcmp\tr3, r1\n+\tadd\tr2, r0\n+\tbne.n\t6216 <__gridxc_alloc_MOD_realloc_r4+0x51e>\n+\tadd.w\tsl, sl, #1\n+\tadd\tr5, lr\n+\tcmp\tsl, r6\n+\tbne.n\t6210 <__gridxc_alloc_MOD_realloc_r4+0x518>\n+\tldr\tr2, [r7, #100]\t@ 0x64\n+\tadd\tr9, r4\n \tadds\tr2, #1\n-\tadd\tsl, r3\n-\tldr\tr3, [r7, #96]\t@ 0x60\n-\tcmp\tr2, r3\n-\tbne.n\t66ac <__gridxc_alloc_MOD_realloc_r4+0x53c>\n-\tldr\tr5, [r7, #80]\t@ 0x50\n-\tldr\tr3, [r7, #32]\n+\tcmp\tr2, fp\n+\tbne.n\t6200 <__gridxc_alloc_MOD_realloc_r4+0x508>\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tmov\tsl, r4\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tldr\tr1, [r7, #72]\t@ 0x48\n \tldr\tr2, [r7, #88]\t@ 0x58\n-\tadd\tr3, r5\n-\tldr\tr5, [r7, #72]\t@ 0x48\n+\tadd\tr3, r1\n+\tldr\tr1, [r7, #68]\t@ 0x44\n \tadds\tr2, #1\n-\tldr.w\tfp, [r7, #108]\t@ 0x6c\n-\tcmp\tr2, r5\n \tstr\tr2, [r7, #88]\t@ 0x58\n-\tbne.n\t669e <__gridxc_alloc_MOD_realloc_r4+0x52e>\n-\tldrd\tr6, r5, [r7, #36]\t@ 0x24\n-\tldr.w\tr3, [pc, #1068]\t@ 6b28 <__gridxc_alloc_MOD_realloc_r4+0x9b8>\n+\tldrd\tr4, r5, [r7, #36]\t@ 0x24\n+\tcmp\tr2, r1\n+\tbne.n\t61ee <__gridxc_alloc_MOD_realloc_r4+0x4f6>\n+\tstr\tr4, [r7, #100]\t@ 0x64\n+\tldr\tr3, [pc, #616]\t@ (64bc <__gridxc_alloc_MOD_realloc_r4+0x7c4>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t6890 <__gridxc_alloc_MOD_realloc_r4+0x720>\n-\tldr\tr3, [r6, #8]\n-\tstr\tr3, [r7, #72]\t@ 0x48\n+\tbeq.w\t63e2 <__gridxc_alloc_MOD_realloc_r4+0x6ea>\n+\tldr\tr1, [r7, #100]\t@ 0x64\n+\tstr.w\tsp, [r7, #28]\n+\tldr\tr3, [r1, #8]\n+\tstr\tr3, [r7, #68]\t@ 0x44\n \tmov\tr2, r3\n-\tldr\tr3, [r6, #12]\n-\tstr.w\tsp, [r7, #24]\n+\tldr\tr3, [r1, #12]\n+\tldr\tr6, [r1, #28]\n \tsub.w\tr9, r3, r2\n-\tldrd\tr0, r3, [r6]\n+\tldrd\tr0, r3, [r1]\n \tsub.w\tip, r3, r0\n-\tldr\tr3, [r6, #16]\n+\tldr\tr3, [r1, #16]\n \tstr\tr3, [r7, #40]\t@ 0x28\n \tadd.w\tsl, ip, #1\n \tmov\tr2, r3\n-\tldr\tr3, [r6, #20]\n+\tldr\tr3, [r1, #20]\n \tsubs\tr2, r3, r2\n \tadd.w\tr3, r9, #1\n-\tstr\tr2, [r7, #100]\t@ 0x64\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n \tmla\tr4, ip, r3, r3\n-\tldr\tr3, [r6, #24]\n-\tldr\tr6, [r6, #28]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r1, #24]\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tsubs\tr6, r6, r3\n \torr.w\tr3, ip, r9\n \torr.w\tr1, r3, r2\n \tldr\tr3, [r5, #0]\n \tmla\tr2, r2, r4, r4\n-\tstr\tr3, [r7, #104]\t@ 0x68\n+\tstr\tr3, [r7, #96]\t@ 0x60\n \tldr\tr3, [r5, #4]\n-\tstr\tr3, [r7, #20]\n+\tstr\tr3, [r7, #16]\n \torrs.w\tr3, r6, r1\n-\tstr\tr4, [r7, #96]\t@ 0x60\n-\tstr\tr2, [r7, #32]\n-\tbmi.w\t6952 <__gridxc_alloc_MOD_realloc_r4+0x7e2>\n+\tstr\tr4, [r7, #88]\t@ 0x58\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tbmi.w\t64d0 <__gridxc_alloc_MOD_realloc_r4+0x7d8>\n \tmla\tr3, r6, r2, r2\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tmov\tr4, sp\n \tcmp\tr4, r2\n-\tbeq.w\t6adc <__gridxc_alloc_MOD_realloc_r4+0x96c>\n+\tbeq.w\t6658 <__gridxc_alloc_MOD_realloc_r4+0x960>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t6778 <__gridxc_alloc_MOD_realloc_r4+0x608>\n-\tldrd\tr5, r4, [r7, #16]\n-\tldr\tr3, [r7, #28]\n-\tldr\tr6, [r7, #36]\t@ 0x24\n+\tb.n\t62d0 <__gridxc_alloc_MOD_realloc_r4+0x5d8>\n+\tldrd\tr4, r2, [r7, #12]\n+\tldrd\tr6, r5, [r7, #20]\n+\tldr\tr3, [r7, #32]\n \tadds\tr5, #1\n-\tldr\tr2, [r7, #12]\n \tadd\tr4, r3\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tcmp\tr6, r5\n \tadd\tr2, r3\n-\tbge.w\t6a70 <__gridxc_alloc_MOD_realloc_r4+0x900>\n-\tldr\tr5, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n-\tldr\tr6, [r7, #60]\t@ 0x3c\n+\tbge.w\t65ec <__gridxc_alloc_MOD_realloc_r4+0x8f4>\n+\tldr\tr5, [r7, #56]\t@ 0x38\n+\tadd.w\tr0, r7, #104\t@ 0x68\n+\tldr\tr6, [r7, #52]\t@ 0x34\n \tmovs\tr4, #1\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n-\tldrd\tr2, r3, [r7, #548]\t@ 0x224\n-\tldr.w\tsp, [r7, #24]\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldrd\tr2, r3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tsp, [r7, #28]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #536]\t@ 0x218\n+\tldrd\tr1, r2, [r7, #456]\t@ 0x1c8\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #560]\t@ 0x230\n+\tldrd\tr1, r2, [r7, #480]\t@ 0x1e0\n \tsubs\tr2, r2, r1\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #572]\t@ 0x23c\n+\tldrd\tr1, r2, [r7, #492]\t@ 0x1ec\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #812]\t@ (6b2c <__gridxc_alloc_MOD_realloc_r4+0x9bc>)\n+\tldr\tr1, [pc, #360]\t@ (64c0 <__gridxc_alloc_MOD_realloc_r4+0x7c8>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tcbz\tr3, 6832 <__gridxc_alloc_MOD_realloc_r4+0x6c2>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tcbz\tr3, 638a <__gridxc_alloc_MOD_realloc_r4+0x692>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvldr\td18, [pc, #720]\t@ 6b10 <__gridxc_alloc_MOD_realloc_r4+0x9a0>\n-\tvldr\td19, [pc, #724]\t@ 6b18 <__gridxc_alloc_MOD_realloc_r4+0x9a8>\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tldr\tr0, [pc, #744]\t@ (6b30 <__gridxc_alloc_MOD_realloc_r4+0x9c0>)\n-\tvldr\td17, [pc, #724]\t@ 6b20 <__gridxc_alloc_MOD_realloc_r4+0x9b0>\n-\tadd\tr0, pc\n-\tldr\tr1, [r7, #64]\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n+\tldr\tr0, [pc, #312]\t@ (64c4 <__gridxc_alloc_MOD_realloc_r4+0x7cc>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #44]\t@ 0x2c\n+\tadd\tr0, pc\n+\tstrd\tr5, r5, [r7, #392]\t@ 0x188\n+\tstr.w\tr3, [r7, #380]\t@ 0x17c\n+\tldr\tr1, [r7, #56]\t@ 0x38\n \tstr.w\tr4, [r0, #16]!\n \tmovs\tr4, #4\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr4, [r7, #500]\t@ 0x1f4\n+\tstr.w\tr4, [r7, #400]\t@ 0x190\n+\tstr.w\tr4, [r7, #388]\t@ 0x184\n+\tstr.w\tr4, [r7, #424]\t@ 0x1a8\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #404]\t@ 0x194\n+\tstr.w\tr4, [r7, #420]\t@ 0x1a4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #412]\t@ 0x19c\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #468]\t@ 0x1d4\n-\tstrh.w\tr4, [r7, #472]\t@ 0x1d8\n+\tstrh.w\tr4, [r7, #396]\t@ 0x18c\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #460]\t@ 0x1cc\n-\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n-\tldrd\tr3, r2, [r7, #56]\t@ 0x38\n+\tstr.w\tr4, [r7, #384]\t@ 0x180\n+\tldr.w\tr4, [r7, #584]\t@ 0x248\n+\tldrd\tr3, r2, [r7, #48]\t@ 0x30\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr4, [r7, #580]\t@ 0x244\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #672]\t@ (6b34 <__gridxc_alloc_MOD_realloc_r4+0x9c4>)\n-\tldr\tr3, [pc, #676]\t@ (6b38 <__gridxc_alloc_MOD_realloc_r4+0x9c8>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #228]\t@ (64c8 <__gridxc_alloc_MOD_realloc_r4+0x7d0>)\n+\tldr\tr3, [pc, #188]\t@ (64a4 <__gridxc_alloc_MOD_realloc_r4+0x7ac>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t6b02 <__gridxc_alloc_MOD_realloc_r4+0x992>\n-\tadd.w\tr7, r7, #588\t@ 0x24c\n+\tbne.w\t667e <__gridxc_alloc_MOD_realloc_r4+0x986>\n+\tadd.w\tr7, r7, #508\t@ 0x1fc\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadd.w\tr3, r7, #280\t@ 0x118\n-\tstr\tr4, [r7, #92]\t@ 0x5c\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tb.n\t628a <__gridxc_alloc_MOD_realloc_r4+0x11a>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #180\t@ 0xb4\n-\tcmp\tr3, #0\n-\tldrd\tr2, r3, [r7, #548]\t@ 0x224\n-\tsub.w\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #536]\t@ 0x218\n-\tadd.w\tr3, r3, #1\n+\tadd.w\tr3, r7, #204\t@ 0xcc\n+\tstr\tr4, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tb.n\t5e1a <__gridxc_alloc_MOD_realloc_r4+0x122>\n+\tldrd\tr2, r3, [r7, #468]\t@ 0x1d4\n+\tadd.w\tr0, r7, #104\t@ 0x68\n+\tldr\tr4, [r7, #56]\t@ 0x38\n+\tsubs\tr3, r3, r2\n+\tldrd\tr1, r2, [r7, #456]\t@ 0x1c8\n+\tadd\tr3, r6\n+\tcmp\tr4, #0\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #560]\t@ 0x230\n+\tldrd\tr1, r2, [r7, #480]\t@ 0x1e0\n \tsub.w\tr2, r2, r1\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #572]\t@ 0x23c\n+\tldrd\tr1, r2, [r7, #492]\t@ 0x1ec\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #560]\t@ (6b3c <__gridxc_alloc_MOD_realloc_r4+0x9cc>)\n-\tadd.w\tr2, r2, #1\n-\tadd\tr1, pc\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n+\tmov\tr2, r4\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tstr\tr6, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #580]\t@ 0x244\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n-\tcmp\tr2, #0\n+\tldr\tr6, [r7, #52]\t@ 0x34\n+\tldr.w\tr1, [r7, #584]\t@ 0x248\n+\tcmp\tr6, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #76]\t@ (64cc <__gridxc_alloc_MOD_realloc_r4+0x7d4>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tldr\tr2, [r7, #64]\t@ 0x40\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tadd\tr1, pc\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tr9, [r8, #16]\n-\tstr.w\tr9, [r7, #68]\t@ 0x44\n-\tb.n\t63cc <__gridxc_alloc_MOD_realloc_r4+0x25c>\n+\tstr.w\tfp, [sl, #16]\n+\tstr.w\tfp, [r7, #60]\t@ 0x3c\n+\tb.n\t5f48 <__gridxc_alloc_MOD_realloc_r4+0x250>\n+\t.word\t0x00000000\n+\t.word\t0x00000784\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000075a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005de\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000560\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000400\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000035c\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x00000264\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000162\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x00000130\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000de\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000044\n+ R_ARM_REL32\t.LC28\n \tcmp\tr6, #0\n-\tblt.w\t67a2 <__gridxc_alloc_MOD_realloc_r4+0x632>\n-\tldr.w\tfp, [r7, #56]\t@ 0x38\n+\tblt.w\t62fa <__gridxc_alloc_MOD_realloc_r4+0x602>\n+\tldr.w\tfp, [r7, #48]\t@ 0x30\n \tldr\tr3, [r5, #24]\n-\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr1, #0\n-\tblt.w\t67a2 <__gridxc_alloc_MOD_realloc_r4+0x632>\n-\tldr\tr4, [r7, #92]\t@ 0x5c\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n-\tldr\tr2, [r7, #28]\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tstr\tr5, [r7, #16]\n+\tblt.w\t62fa <__gridxc_alloc_MOD_realloc_r4+0x602>\n+\tldr\tr4, [r7, #84]\t@ 0x54\n+\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tldr\tr2, [r7, #20]\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tstr\tr5, [r7, #20]\n \tmla\tr2, r1, r3, r2\n \tldr\tr1, [r7, #40]\t@ 0x28\n \tmul.w\tr3, r4, r3\n-\tstr\tr3, [r7, #28]\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n+\tstr\tr3, [r7, #32]\n+\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n \tmla\tr2, r1, r3, r2\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n \tmul.w\tr3, r4, r3\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tmul.w\tr8, r4, r1\n \tmla\tr2, r3, r1, r2\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #24]\n \tmov\tr3, r4\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n+\tstr\tr0, [r7, #24]\n \tmla\tr2, r0, r1, r2\n \tmul.w\tr4, r4, r1\n-\tldr\tr1, [r7, #68]\t@ 0x44\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n \tmla\tr3, r3, r2, r1\n-\tmovs\tr2, #0\n \tmov\tr1, r6\n-\tmov\tr5, r2\n-\tmov\tr6, r2\n+\tmovs\tr2, #0\n \tmov\tlr, r1\n-\tmov\tr2, r3\n-\tmov\tr1, r5\n-\tmov\tr0, r2\n+\tmov\tr6, r2\n+\tmov\tr5, r3\n+\tmov\tr1, r6\n+\tmov\tr0, r5\n \tmovs\tr3, #0\n \tstrd\tr5, r6, [r7, #8]\n-\tstrd\tr2, lr, [r7]\n+\tstrd\tlr, r2, [r7]\n \tmov\tr6, r1\n \tmov\tr5, r0\n \tmov.w\tlr, #0\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n-\tstrd\tr0, r1, [r7, #88]\t@ 0x58\n+\tstr\tr1, [r7, #100]\t@ 0x64\n+\tstrd\tr3, r0, [r7, #80]\t@ 0x50\n \tadd.w\tr0, fp, r6, lsl #2\n \tmov\tr1, r5\n \tmovs\tr2, #0\n \tldr\tr3, [r1, #0]\n-\tcmp\tip, r2\n+\tcmp\tr2, ip\n \tadd\tr1, r4\n \tadd.w\tr2, r2, #1\n \tstr.w\tr3, [r0], #4\n-\tbne.n\t69de <__gridxc_alloc_MOD_realloc_r4+0x86e>\n+\tbne.n\t655a <__gridxc_alloc_MOD_realloc_r4+0x862>\n \tadd\tr5, r8\n \tadd\tr6, sl\n \tadd.w\tr3, lr, #1\n-\tcmp\tr9, lr\n-\tbeq.n\t69fe <__gridxc_alloc_MOD_realloc_r4+0x88e>\n+\tcmp\tlr, r9\n+\tbeq.n\t657a <__gridxc_alloc_MOD_realloc_r4+0x882>\n \tmov\tlr, r3\n-\tb.n\t69d6 <__gridxc_alloc_MOD_realloc_r4+0x866>\n-\tldrd\tr0, r1, [r7, #88]\t@ 0x58\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tldr\tr5, [r7, #100]\t@ 0x64\n+\tb.n\t6552 <__gridxc_alloc_MOD_realloc_r4+0x85a>\n+\tldrd\tr3, r0, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr1, [r7, #100]\t@ 0x64\n+\tldr\tr5, [r7, #92]\t@ 0x5c\n \tadd\tr0, r2\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tcmp\tr3, r5\n+\tldr\tr2, [r7, #88]\t@ 0x58\n+\tcmp\tr5, r3\n \tadd\tr1, r2\n \tadd.w\tr2, r3, #1\n-\tbeq.n\t6a1a <__gridxc_alloc_MOD_realloc_r4+0x8aa>\n+\tbeq.n\t6596 <__gridxc_alloc_MOD_realloc_r4+0x89e>\n \tmov\tr3, r2\n-\tb.n\t69c8 <__gridxc_alloc_MOD_realloc_r4+0x858>\n-\tldrd\tr2, lr, [r7]\n+\tb.n\t6544 <__gridxc_alloc_MOD_realloc_r4+0x84c>\n \tldrd\tr5, r6, [r7, #8]\n-\tldr\tr3, [r7, #28]\n-\tadds\tr6, #1\n-\tadd\tr2, r3\n+\tldrd\tlr, r2, [r7]\n \tldr\tr3, [r7, #32]\n-\tcmp\tr6, lr\n+\tadds\tr2, #1\n \tadd\tr5, r3\n-\tble.n\t69ba <__gridxc_alloc_MOD_realloc_r4+0x84a>\n-\tldr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tcmp\tr2, lr\n+\tadd\tr6, r3\n+\tble.n\t6536 <__gridxc_alloc_MOD_realloc_r4+0x83e>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tmov\tr6, lr\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n-\tldr\tr5, [r7, #16]\n-\tldr\tr1, [r7, #20]\n+\tldr\tr0, [r7, #24]\n+\tldr\tr5, [r7, #20]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr2, r0, r3\n-\tldr\tr0, [r7, #36]\t@ 0x24\n-\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr0, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r7, #72]\t@ 0x48\n \tldr\tr2, [r5, #60]\t@ 0x3c\n-\tstr\tr2, [r7, #28]\n+\tstr\tr2, [r7, #32]\n \tldr.w\tr8, [r5, #36]\t@ 0x24\n \tmla\tr4, r0, r2, r1\n \tldr\tr2, [r5, #48]\t@ 0x30\n \tldr\tr1, [r7, #40]\t@ 0x28\n-\tstr\tr2, [r7, #80]\t@ 0x50\n+\tstr\tr2, [r7, #64]\t@ 0x40\n \tmul.w\tr1, r2, r1\n \tldr\tr2, [r5, #20]\n \tstr\tr1, [r7, #40]\t@ 0x28\n-\tldr\tr1, [r7, #72]\t@ 0x48\n-\tstr\tr2, [r7, #108]\t@ 0x6c\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tstr\tr2, [r7, #100]\t@ 0x64\n \tmul.w\tlr, r3, r2\n \tmovs\tr3, #0\n \tmov\tr5, r3\n \tmov\tr2, r3\n \tmul.w\tr1, r1, r8\n-\tstr\tr1, [r7, #72]\t@ 0x48\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr0, r2\n-\tstr\tr6, [r7, #36]\t@ 0x24\n+\tstrd\tr6, r5, [r7, #20]\n \tadds\tr1, r4, r3\n \tmovs\tr3, #0\n-\tstrd\tr5, r4, [r7, #16]\n-\tstr\tr2, [r7, #12]\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr4, r2, [r7, #12]\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tmov\tr5, r0\n \tmovs\tr6, #0\n-\tstrd\tr1, r0, [r7, #88]\t@ 0x58\n+\tstrd\tr3, r1, [r7, #80]\t@ 0x50\n \tadds\tr4, r1, r2\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n \tadd\tr4, r2\n-\tldrd\tr3, r2, [r7, #104]\t@ 0x68\n+\tldrd\tr3, r2, [r7, #96]\t@ 0x60\n \tadd.w\tr0, fp, r5, lsl #2\n \tmla\tr1, r2, r4, r3\n \tmovs\tr2, #0\n \tldr.w\tr3, [r0], #4\n-\tcmp\tip, r2\n+\tcmp\tr2, ip\n \tstr\tr3, [r1, #0]\n \tadd.w\tr2, r2, #1\n \tadd\tr1, lr\n-\tbne.n\t6aa0 <__gridxc_alloc_MOD_realloc_r4+0x930>\n+\tbne.n\t661c <__gridxc_alloc_MOD_realloc_r4+0x924>\n \tadd\tr4, r8\n \tadd\tr5, sl\n \tadds\tr3, r6, #1\n \tcmp\tr6, r9\n-\tbeq.n\t6abe <__gridxc_alloc_MOD_realloc_r4+0x94e>\n+\tbeq.n\t663a <__gridxc_alloc_MOD_realloc_r4+0x942>\n \tmov\tr6, r3\n-\tb.n\t6a92 <__gridxc_alloc_MOD_realloc_r4+0x922>\n-\tldrd\tr2, r3, [r7, #80]\t@ 0x50\n-\tldrd\tr1, r0, [r7, #88]\t@ 0x58\n-\tldr\tr4, [r7, #100]\t@ 0x64\n+\tb.n\t660e <__gridxc_alloc_MOD_realloc_r4+0x916>\n+\tldrd\tr3, r1, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n+\tldr\tr4, [r7, #92]\t@ 0x5c\n \tadd\tr1, r2\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tcmp\tr3, r4\n+\tldr\tr2, [r7, #88]\t@ 0x58\n+\tcmp\tr4, r3\n \tadd\tr0, r2\n \tadd.w\tr2, r3, #1\n-\tbeq.w\t678a <__gridxc_alloc_MOD_realloc_r4+0x61a>\n+\tbeq.w\t62e2 <__gridxc_alloc_MOD_realloc_r4+0x5ea>\n \tmov\tr3, r2\n-\tb.n\t6a80 <__gridxc_alloc_MOD_realloc_r4+0x910>\n+\tb.n\t65fc <__gridxc_alloc_MOD_realloc_r4+0x904>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbnz\tr3, 6af0 <__gridxc_alloc_MOD_realloc_r4+0x980>\n+\tcbnz\tr3, 666c <__gridxc_alloc_MOD_realloc_r4+0x974>\n \tldr\tr3, [r5, #24]\n \tadd.w\tfp, sp, #16\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tb.n\t6960 <__gridxc_alloc_MOD_realloc_r4+0x7f0>\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tb.n\t64de <__gridxc_alloc_MOD_realloc_r4+0x7e6>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t6ae6 <__gridxc_alloc_MOD_realloc_r4+0x976>\n-\tmovw\tr8, #5014\t@ 0x1396\n-\tb.n\t6518 <__gridxc_alloc_MOD_realloc_r4+0x3a8>\n-\tmov\tr8, r2\n-\tb.n\t643e <__gridxc_alloc_MOD_realloc_r4+0x2ce>\n+\tb.n\t6662 <__gridxc_alloc_MOD_realloc_r4+0x96a>\n+\tmovw\tfp, #5014\t@ 0x1396\n+\tb.n\t60a8 <__gridxc_alloc_MOD_realloc_r4+0x3b0>\n+\tmov\tfp, sl\n+\tb.n\t5fb2 <__gridxc_alloc_MOD_realloc_r4+0x2ba>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovw\tr8, #5020\t@ 0x139c\n-\tb.n\t6518 <__gridxc_alloc_MOD_realloc_r4+0x3a8>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000426\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000326\n- R_ARM_REL32\t.LC28\n-\t.word\t0x000002e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000029c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000022a\n- R_ARM_REL32\t.LC28\n+\tmovw\tfp, #5020\t@ 0x139c\n+\tb.n\t60a8 <__gridxc_alloc_MOD_realloc_r4+0x3b0>\n \n-00006b40 <__gridxc_alloc_MOD_realloc_r3>:\n+00006688 <__gridxc_alloc_MOD_realloc_r3>:\n __gridxc_alloc_MOD_realloc_r3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3512]\t@ 0xdb8\n-\tmov\tr8, r2\n-\tldr.w\tr2, [pc, #1088]\t@ 6f98 <__gridxc_alloc_MOD_realloc_r3+0x458>\n-\tmov\tip, r3\n-\tldr.w\tr3, [pc, #1084]\t@ 6f9c <__gridxc_alloc_MOD_realloc_r3+0x45c>\n-\tadd\tr2, pc\n-\tsub.w\tsp, sp, #516\t@ 0x204\n+\tstr.w\tr0, [ip, #3600]\t@ 0xe10\n+\tsub\tsp, #460\t@ 0x1cc\n+\tmov\tfp, r2\n+\tldr.w\tr2, [pc, #1772]\t@ 6d8c <__gridxc_alloc_MOD_realloc_r3+0x704>\n \tadd\tr7, sp, #16\n+\tmov\tr6, r3\n+\tldr.w\tr3, [pc, #1768]\t@ 6d90 <__gridxc_alloc_MOD_realloc_r3+0x708>\n+\tadd\tr2, pc\n \tmov\tlr, r1\n-\tmov\tr6, r0\n+\tstr\tr0, [r7, #52]\t@ 0x34\n+\tldrd\tr8, ip, [r7, #480]\t@ 0x1e0\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [pc, #1072]\t@ 6fa0 <__gridxc_alloc_MOD_realloc_r3+0x460>\n+\tldr.w\tr2, [pc, #1756]\t@ 6d94 <__gridxc_alloc_MOD_realloc_r3+0x70c>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr3, [r7, #436]\t@ 0x1b4\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tadd\tr2, pc\n-\tldrd\tfp, r1, [r7, #576]\t@ 0x240\n+\tldr.w\tr9, [r7, #488]\t@ 0x1e8\n \tcmp\tr3, #0\n-\tstr\tr1, [r7, #32]\n-\tmov.w\tr1, #1\n-\tit\teq\n+\tldr.w\tsl, [r7, #504]\t@ 0x1f8\n+\tite\tne\n+\tmovne\tr1, #1\n \tmoveq\tr1, #0\n \tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n \tstr\tr2, [r7, #28]\n-\tldr.w\tr2, [r7, #588]\t@ 0x24c\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tldrd\tr9, sl, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tstr\tr2, [r7, #24]\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n \tstr\tr2, [r7, #76]\t@ 0x4c\n-\tbeq.w\t716e <__gridxc_alloc_MOD_realloc_r3+0x62e>\n+\tbeq.w\t6c62 <__gridxc_alloc_MOD_realloc_r3+0x5da>\n \tmov\tr5, r0\n-\tstr\tr3, [r7, #24]\n+\tstr\tr3, [r7, #20]\n \tldr\tr3, [r0, #4]\n-\tadd.w\tr4, r7, #432\t@ 0x1b0\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tadd.w\tr4, r7, #376\t@ 0x178\n+\tstr\tr3, [r7, #12]\n \tldr\tr3, [r0, #24]\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r7, #216\t@ 0xd8\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #16]\n+\tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [r7, #36]\t@ 0x24\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tr4, {r0, r1, r2}\n-\tldr\tr2, [r6, #20]\n-\tldrd\tr0, r1, [r7, #460]\t@ 0x1cc\n-\tstr\tr2, [r7, #68]\t@ 0x44\n-\tldr\tr4, [r7, #44]\t@ 0x2c\n-\tldrd\tr3, r2, [r7, #472]\t@ 0x1d8\n+\tldr\tr0, [r7, #52]\t@ 0x34\n+\tldr\tr4, [r7, #36]\t@ 0x24\n+\tldr\tr2, [r0, #20]\n+\tldrd\tr0, r1, [r7, #404]\t@ 0x194\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldrd\tr3, r2, [r7, #416]\t@ 0x1a0\n \tsubs\tr5, r1, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tstr\tr0, [r4, #0]\n \tsubs\tr0, r2, r3\n-\tstr\tr0, [r7, #84]\t@ 0x54\n+\tstr\tr0, [r7, #72]\t@ 0x48\n \tit\tmi\n \tmovmi\tr3, #1\n \tstr\tr3, [r4, #8]\n-\tldrd\tr0, r3, [r7, #484]\t@ 0x1e4\n+\tldrd\tr0, r3, [r7, #428]\t@ 0x1ac\n \tsubs\tr4, r3, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tcmp\tr5, #0\n-\tldr\tr5, [r7, #44]\t@ 0x2c\n+\tldr\tr5, [r7, #36]\t@ 0x24\n \tit\tlt\n \tmovlt\tr1, #0\n \tstr\tr0, [r5, #16]\n-\tldr\tr0, [r7, #84]\t@ 0x54\n+\tldr\tr0, [r7, #72]\t@ 0x48\n \tstr\tr1, [r5, #4]\n \tcmp\tr0, #0\n \tit\tlt\n \tmovlt\tr2, #0\n \tcmp\tr4, #0\n \tit\tlt\n \tmovlt\tr3, #0\n \tstr\tr2, [r5, #12]\n \tstr\tr3, [r5, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr3, [sl]\n-\tvldr\td18, [pc, #848]\t@ 6f78 <__gridxc_alloc_MOD_realloc_r3+0x438>\n-\tvldr\td19, [pc, #852]\t@ 6f80 <__gridxc_alloc_MOD_realloc_r3+0x440>\n-\tstr.w\tr3, [r7, #160]\t@ 0xa0\n-\tldr.w\tr2, [ip]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n+\tldr\tr1, [r6, #0]\n+\tadd.w\tr6, r7, #136\t@ 0x88\n \tldr.w\tr0, [lr]\n-\tldr.w\tr1, [r8]\n-\tadd.w\tr8, r7, #168\t@ 0xa8\n+\tldr.w\tr2, [ip]\n+\tmov.w\tip, #4\n+\tstr\tr0, [r6, #0]\n+\tadd.w\tr0, r7, #184\t@ 0xb8\n+\tldr.w\tr3, [r8]\n+\tadd.w\tr8, r7, #88\t@ 0x58\n \tldr.w\tr4, [r9]\n \tldr.w\tr5, [fp]\n-\tstrd\tr0, r1, [r7, #120]\t@ 0x78\n-\tadd.w\tr0, r7, #384\t@ 0x180\n-\tstrd\tr2, r4, [r7, #128]\t@ 0x80\n-\tmov\tr4, r0\n-\tvldr\td17, [pc, #808]\t@ 6f88 <__gridxc_alloc_MOD_realloc_r3+0x448>\n-\tadd.w\tr2, r7, #144\t@ 0x90\n-\tvldr\td20, [r7, #120]\t@ 0x78\n-\tvldr\td21, [r7, #128]\t@ 0x80\n-\tvstr\td16, [r7, #248]\t@ 0xf8\n-\tvstr\td16, [r7, #252]\t@ 0xfc\n-\tadd.w\tr1, r7, #420\t@ 0x1a4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #276\t@ 0x114\n-\tldr.w\tr9, [pc, #800]\t@ 6fa4 <__gridxc_alloc_MOD_realloc_r3+0x464>\n-\tvstr\td16, [r7, #296]\t@ 0x128\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #308\t@ 0x134\n-\tvstr\td16, [r7, #300]\t@ 0x12c\n+\tstr\tr2, [r6, #16]\n+\tmovs\tr2, #2\n+\tstr\tr5, [r6, #4]\n+\tmovs\tr5, #1\n+\tstrd\tr2, r2, [r0, #32]\n+\tstr\tr3, [r6, #12]\n+\tadd.w\tr3, r7, #328\t@ 0x148\n+\tstr\tr4, [r6, #20]\n+\tmovs\tr4, #3\n+\tstr\tr3, [r7, #32]\n+\tmovs\tr3, #0\n+\tstr\tr4, [r0, #44]\t@ 0x2c\n+\tstrd\tr3, r3, [r7, #192]\t@ 0xc0\n+\tstr.w\tr3, [r7, #200]\t@ 0xc8\n+\tstrd\tr3, r3, [r7, #240]\t@ 0xf0\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstrd\tr5, r5, [r0, #24]\n+\tstr\tr5, [r0, #40]\t@ 0x28\n+\tstr.w\tr2, [r7, #264]\t@ 0x108\n+\tstr.w\tip, [r7, #252]\t@ 0xfc\n+\tstr\tr1, [r6, #8]\n+\tmvn.w\tr1, #2\n+\tstr.w\tip, [r0, #20]\n+\tstr\tr1, [r0, #4]\n+\tldr.w\tr9, [pc, #1476]\t@ 6d98 <__gridxc_alloc_MOD_realloc_r3+0x710>\n+\tstrd\tr5, r5, [r7, #256]\t@ 0x100\n+\tstr.w\tr5, [r7, #272]\t@ 0x110\n \tadd\tr9, pc\n-\tstr\tr0, [r7, #20]\n-\tadd.w\tr0, r7, #240\t@ 0xf0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #324\t@ 0x144\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tadd.w\tr1, r7, #372\t@ 0x174\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #356\t@ 0x164\n-\tstr\tr5, [r2, #20]\n-\tadd.w\tr5, r7, #192\t@ 0xc0\n-\tvstr\td16, [r7, #344]\t@ 0x158\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tmovs\tr2, #3\n-\tvstr\td16, [r7, #348]\t@ 0x15c\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #404\t@ 0x194\n-\tstr.w\tr2, [r7, #332]\t@ 0x14c\n-\tstr\tr3, [r7, #40]\t@ 0x28\n-\tmvn.w\tr3, #2\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tvstr\td20, [r7, #144]\t@ 0x90\n-\tvstr\td21, [r7, #152]\t@ 0x98\n-\tstr\tr3, [r0, #4]\n-\tstr.w\tr2, [r7, #428]\t@ 0x1ac\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tstrd\tr2, r3, [r7, #336]\t@ 0x150\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tvst1.32\t{d17}, [r1]\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tstr.w\tr3, [r7, #388]\t@ 0x184\n-\tstr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tmov\tr3, r4\n-\tvstr\td16, [r7, #392]\t@ 0x188\n-\tvstr\td16, [r7, #396]\t@ 0x18c\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tvst1.32\t{d17}, [r1]\n-\tadd.w\tr1, r7, #288\t@ 0x120\n \tstr.w\tr8, [r0]\n-\tstr.w\tr5, [r7, #288]\t@ 0x120\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [r7, #80]\t@ 0x50\n+\tstr.w\tr4, [r7, #276]\t@ 0x114\n+\tstrd\tr5, r4, [r7, #320]\t@ 0x140\n+\tstr.w\tr4, [r7, #372]\t@ 0x174\n+\tldr\tr4, [r7, #36]\t@ 0x24\n+\tstrd\tr4, r1, [r7, #280]\t@ 0x118\n+\tadd.w\tr4, r7, #112\t@ 0x70\n+\tstr.w\tr2, [r7, #268]\t@ 0x10c\n+\tstr.w\tr1, [r7, #236]\t@ 0xec\n+\tstr.w\tip, [r7, #300]\t@ 0x12c\n+\tstr.w\tip, [r7, #348]\t@ 0x15c\n+\tstrd\tr5, r2, [r7, #308]\t@ 0x134\n+\tstr.w\tr2, [r7, #316]\t@ 0x13c\n+\tstrd\tr1, r3, [r7, #332]\t@ 0x14c\n+\tadd.w\tr1, r7, #232\t@ 0xe8\n+\tstrd\tr5, r2, [r7, #356]\t@ 0x164\n+\tstr.w\tr2, [r7, #364]\t@ 0x16c\n+\tstrd\tr3, r3, [r7, #288]\t@ 0x120\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tstr.w\tr5, [r7, #304]\t@ 0x130\n+\tstrd\tr3, r3, [r7, #340]\t@ 0x154\n+\tstr.w\tr5, [r7, #352]\t@ 0x160\n+\tstr.w\tr5, [r7, #368]\t@ 0x170\n+\tstr.w\tr6, [r7, #328]\t@ 0x148\n+\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tsl, [sp, #4]\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n \tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #336\t@ 0x150\n+\tadd.w\tr2, r7, #280\t@ 0x118\n+\tldr\tr3, [r7, #32]\n \tbl\t3cc <__gridxc_alloc_MOD_options.constprop.2>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 6d46 <__gridxc_alloc_MOD_realloc_r3+0x206>\n+\tcbz\tr3, 6864 <__gridxc_alloc_MOD_realloc_r3+0x1dc>\n \tldr.w\tsl, [r9, #12]\n \tcmp.w\tsl, #0\n-\tbeq.w\t7178 <__gridxc_alloc_MOD_realloc_r3+0x638>\n-\tldr\tr3, [pc, #608]\t@ (6fa8 <__gridxc_alloc_MOD_realloc_r3+0x468>)\n+\tbeq.w\t6c6c <__gridxc_alloc_MOD_realloc_r3+0x5e4>\n+\tldr.w\tr3, [pc, #1332]\t@ 6d9c <__gridxc_alloc_MOD_realloc_r3+0x714>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t6fda <__gridxc_alloc_MOD_realloc_r3+0x49a>\n-\tldrd\tr1, r3, [r8]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tlr, sl, [r8, #8]\n-\tsub.w\tfp, r3, r1\n-\tsub.w\tr2, sl, lr\n-\torr.w\tr0, fp, fp, asr #31\n-\tvstr\td16, [r6, #12]\n-\tadds\tr0, #1\n-\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tbeq.w\t6ad6 <__gridxc_alloc_MOD_realloc_r3+0x44e>\n+\tldr.w\tr2, [r8, #4]\n+\tldr.w\tr0, [r8]\n+\tldr.w\tr3, [r8, #8]\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tldr.w\tr5, [r8, #12]\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tstr\tr2, [r7, #64]\t@ 0x40\n+\tstr\tr0, [r7, #72]\t@ 0x48\n+\tsubs\tr0, r2, r0\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\torr.w\tr3, r0, r0, asr #31\n+\tstr\tr5, [r7, #48]\t@ 0x30\n+\tsubs\tr2, r5, r2\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r1, #12]\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tadds\tr5, r3, #1\n+\tstr\tr0, [r7, #56]\t@ 0x38\n \tmovs\tr3, #4\n-\tstr\tr1, [r7, #104]\t@ 0x68\n-\tstr.w\tlr, [r7, #116]\t@ 0x74\n-\tstr\tr0, [r7, #112]\t@ 0x70\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\torr.w\tr2, r2, r2, asr #31\n-\tvldr\td10, [r7, #104]\t@ 0x68\n-\tvldr\td11, [r7, #112]\t@ 0x70\n-\tadds\tr2, #1\n-\tstr\tr3, [r6, #8]\n+\tstr\tr3, [r1, #8]\n \tmovw\tr3, #771\t@ 0x303\n-\tstrh\tr3, [r6, #16]\n-\tbeq.w\t732a <__gridxc_alloc_MOD_realloc_r3+0x7ea>\n-\tmvn.w\tr9, #2147483648\t@ 0x80000000\n-\tudiv\tr9, r9, r2\n-\tcmp\tr9, r0\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr9, r3\n-\tldrd\tr8, r3, [r8, #16]\n-\tmul.w\tr2, r0, r2\n-\tstrd\tsl, r2, [r7, #88]\t@ 0x58\n-\tsub.w\tsl, r3, r8\n-\tstrd\tr8, r3, [r7, #96]\t@ 0x60\n-\torr.w\tr3, sl, sl, asr #31\n-\tvldr\td8, [r7, #88]\t@ 0x58\n-\tvldr\td9, [r7, #96]\t@ 0x60\n-\tadds\tr3, #1\n-\tbeq.n\t6dee <__gridxc_alloc_MOD_realloc_r3+0x2ae>\n-\tmvn.w\tip, #2147483648\t@ 0x80000000\n-\tmov\tr4, r9\n-\tudiv\tip, ip, r3\n-\tmul.w\tr3, r2, r3\n-\tcmp\tip, r2\n+\torr.w\tr2, r2, r2, asr #31\n+\tstrh\tr3, [r1, #16]\n+\tadds.w\tsl, r2, #1\n+\tbeq.w\t6e56 <__gridxc_alloc_MOD_realloc_r3+0x7ce>\n+\tmov\tr1, sl\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r5\n+\tite\tge\n+\tmovge.w\tr9, #0\n+\tmovlt.w\tr9, #1\n+\tldr.w\tr3, [r8, #20]\n+\tmul.w\tfp, sl, r5\n+\tldr.w\tsl, [r8, #16]\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tsub.w\tr3, r3, sl\n+\torr.w\tr8, r3, r3, asr #31\n+\tadds.w\tr8, r8, #1\n+\tbeq.n\t6910 <__gridxc_alloc_MOD_realloc_r3+0x288>\n+\tmov\tr1, r8\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr8, r8, fp\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tcmp\tr0, fp\n \tit\tlt\n-\taddlt\tr4, #1\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n+\taddlt.w\tr9, r9, #1\n+\tcmp.w\tr8, #1073741824\t@ 0x40000000\n \tit\tge\n-\taddge\tr4, #1\n-\tmov\tr9, r4\n-\tldr\tr4, [r7, #80]\t@ 0x50\n-\tnegs\tr1, r1\n-\torr.w\tip, fp, r4\n-\torrs.w\tip, ip, sl\n-\tmls\tr1, r0, lr, r1\n-\tmls\tr8, r2, r8, r1\n+\taddge.w\tr9, r9, #1\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tldr\tr1, [r7, #56]\t@ 0x38\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n+\torrs\tr1, r2\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\torrs\tr1, r3\n+\trsb\tr2, r2, #0\n+\tmls\tr2, r5, r0, r2\n \tit\tpl\n-\tlslpl\tr3, r3, #2\n+\tmovpl.w\tr0, r8, lsl #2\n+\tmls\tr2, fp, sl, r2\n \tit\tmi\n-\tmovmi\tr3, #0\n+\tmovmi\tr0, #0\n+\tstr\tr2, [r7, #68]\t@ 0x44\n \tcmp.w\tr9, #0\n-\tbne.w\t7332 <__gridxc_alloc_MOD_realloc_r3+0x7f2>\n-\tcmp\tr3, #1\n+\tbne.w\t6e5e <__gridxc_alloc_MOD_realloc_r3+0x7d6>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr3, #1\n-\tmov\tr0, r3\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r6, #0]\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tstr\tr0, [r1, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t7338 <__gridxc_alloc_MOD_realloc_r3+0x7f8>\n-\tadd.w\tr3, r6, #28\n-\tvldr\td16, [pc, #356]\t@ 6f90 <__gridxc_alloc_MOD_realloc_r3+0x450>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r6, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r6, #20\n-\tstr.w\tr8, [r6, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tvldr\td18, [pc, #292]\t@ 6f78 <__gridxc_alloc_MOD_realloc_r3+0x438>\n-\tvldr\td19, [pc, #296]\t@ 6f80 <__gridxc_alloc_MOD_realloc_r3+0x440>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tvstr\td17, [r7, #396]\t@ 0x18c\n-\tvldr\td16, [pc, #296]\t@ 6f88 <__gridxc_alloc_MOD_realloc_r3+0x448>\n-\tldr\tr0, [pc, #328]\t@ (6fac <__gridxc_alloc_MOD_realloc_r3+0x46c>)\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr1, [r7, #32]\n+\tbeq.w\t6e64 <__gridxc_alloc_MOD_realloc_r3+0x7dc>\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tmovs\tr3, #4\n+\tstr\tr2, [r1, #28]\n+\tmov.w\tlr, #1\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r1, #32]\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tstr\tr2, [r1, #40]\t@ 0x28\n+\tldr\tr2, [r7, #48]\t@ 0x30\n+\tstr\tr2, [r1, #44]\t@ 0x2c\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n+\tstr\tr2, [r1, #56]\t@ 0x38\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tstr\tr5, [r1, #36]\t@ 0x24\n+\tstr.w\tsl, [r1, #52]\t@ 0x34\n+\tstr.w\tfp, [r1, #48]\t@ 0x30\n+\tstr\tr2, [r1, #4]\n+\tstrd\tr3, lr, [r1, #20]\n+\tldr.w\tr0, [pc, #1056]\t@ 6da0 <__gridxc_alloc_MOD_realloc_r3+0x718>\n+\tmovs\tr5, #1\n+\tldr\tr1, [r7, #28]\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #28]\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr\tr2, [r7, #24]\n \tcmp\tr1, #0\n-\tvst1.32\t{d16}, [r3]\n-\tmov\tsl, r2\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tit\teq\n-\tmoveq\tr3, #0\n+\tstr.w\tr6, [r7, #328]\t@ 0x148\n+\tmov.w\tr6, #0\n \tstr.w\tr9, [r0, #16]!\n-\tcmp\tr2, #0\n-\tmov\tr8, r3\n+\tit\tne\n+\tmovne\tr9, r3\n \tmov.w\tr3, #4\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n+\tstr.w\tr3, [r7, #348]\t@ 0x15c\n+\tstr.w\tr3, [r7, #336]\t@ 0x150\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #360]\t@ 0x168\n+\tit\teq\n+\tmoveq.w\tr9, #0\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tcmp\tr2, #0\n+\tit\teq\n+\tmoveq\tr8, r6\n+\tstrd\tr5, r5, [r7, #352]\t@ 0x160\n+\tit\tne\n+\tmovne\tr8, r3\n+\tstr.w\tr5, [r7, #368]\t@ 0x170\n+\tstrd\tr6, r6, [r7, #340]\t@ 0x154\n \tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #400]\t@ 0x190\n-\tmov.w\tr3, #3\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tstrh.w\tr3, [r7, #344]\t@ 0x158\n+\tmovs\tr3, #3\n+\tstr.w\tr3, [r7, #372]\t@ 0x174\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #388]\t@ 0x184\n-\tmov\tr9, r1\n-\tstr.w\tr8, [sp]\n-\tldr.w\tr4, [r7, #600]\t@ 0x258\n-\tit\teq\n-\tmoveq\tr4, #0\n-\tstr\tr4, [sp, #4]\n-\tldr\tr3, [r7, #20]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n-\tldrd\tr2, r3, [r6, #40]\t@ 0x28\n+\tstr.w\tr3, [r7, #332]\t@ 0x14c\n+\tmov\tfp, r2\n+\tstrd\tr9, r8, [sp]\n+\tmov\tsl, r1\n+\tldr\tr3, [r7, #32]\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr0, [r7, #52]\t@ 0x34\n+\tldrd\tr2, r3, [r0, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r6, #28]\n-\tadds\tr3, #1\n+\tldrd\tr1, r2, [r0, #28]\n+\tadd\tr3, r5\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r5\n+\tldr\tr1, [r0, #52]\t@ 0x34\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r6, #52]\t@ 0x34\n+\tldr\tr2, [r0, #56]\t@ 0x38\n+\tadd.w\tr0, r7, #84\t@ 0x54\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #200]\t@ (6fb0 <__gridxc_alloc_MOD_realloc_r3+0x470>)\n-\tadds\tr2, #1\n+\tldr\tr1, [pc, #900]\t@ (6da4 <__gridxc_alloc_MOD_realloc_r3+0x71c>)\n+\tadd\tr2, r5\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r9\n+\tmov\tr2, sl\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr8, r4, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, sl\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr3, r4, [r6, #52]\t@ 0x34\n-\tldrd\tr0, ip, [r6, #40]\t@ 0x28\n-\tcmp\tr3, r4\n-\tbgt.n\t6fda <__gridxc_alloc_MOD_realloc_r3+0x49a>\n-\tcmp\tr0, ip\n-\tbgt.n\t6fda <__gridxc_alloc_MOD_realloc_r3+0x49a>\n-\tldrd\tr2, r1, [r6, #28]\n-\tcmp\tr2, r1\n-\tbgt.n\t6fda <__gridxc_alloc_MOD_realloc_r3+0x49a>\n-\tadds\tr4, #1\n+\tmov\tr3, fp\n+\tstr\tr5, [sp, #0]\n+\tstrd\tr9, r8, [sp, #4]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tldrd\tr0, r2, [r1, #52]\t@ 0x34\n+\tldrd\tip, r5, [r1, #40]\t@ 0x28\n+\tcmp\tr0, r2\n+\tbgt.n\t6ad6 <__gridxc_alloc_MOD_realloc_r3+0x44e>\n+\tcmp\tip, r5\n+\tbgt.n\t6ad6 <__gridxc_alloc_MOD_realloc_r3+0x44e>\n+\tldr\tr3, [r1, #28]\n+\tldr\tr1, [r1, #32]\n+\tcmp\tr3, r1\n+\tbgt.n\t6ad6 <__gridxc_alloc_MOD_realloc_r3+0x44e>\n+\tadds\tr2, #1\n+\tadds\tr5, #1\n+\tsub.w\tsl, r2, r0\n+\tmov\tr2, r6\n+\tsub.w\tr6, r5, ip\n+\tldr\tr5, [r7, #52]\t@ 0x34\n \tadds\tr1, #1\n-\tsubs\tr4, r4, r3\n-\tstr\tr4, [r7, #84]\t@ 0x54\n-\tldr\tr4, [r6, #24]\n-\tsubs\tr1, r1, r2\n-\tldr.w\tfp, [r6, #48]\t@ 0x30\n-\tadd.w\tip, ip, #1\n-\tldr.w\tr8, [r6, #36]\t@ 0x24\n-\tsub.w\tip, ip, r0\n-\tldr.w\tlr, [r6, #20]\n-\tmov.w\tsl, #0\n-\tmul.w\tr2, r4, r2\n-\tldr.w\tr9, [r6]\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tldr\tr2, [r6, #4]\n-\tstr.w\tfp, [r7, #72]\t@ 0x48\n-\tstrd\tr5, r6, [r7, #52]\t@ 0x34\n-\tmla\tr2, r3, fp, r2\n-\tmul.w\tr3, r0, r8\n-\tmul.w\tr0, r4, lr\n-\tmovs\tr4, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tvldr\ts15, [pc, #796]\t@ 6d88 <__gridxc_alloc_MOD_realloc_r3+0x700>\n+\tsubs\tr1, r1, r3\n+\tstrd\tr4, sl, [r7, #64]\t@ 0x40\n+\tldr\tr5, [r5, #24]\n+\tmul.w\tlr, r5, r3\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tstr.w\tlr, [r7, #72]\t@ 0x48\n+\tldr.w\tfp, [r3, #48]\t@ 0x30\n+\tldr\tr3, [r3, #4]\n+\tmla\tr9, r0, fp, r3\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr.w\tlr, [r3, #36]\t@ 0x24\n+\tldr.w\tr8, [r3]\n+\tmul.w\tr0, ip, lr\n+\tldr.w\tip, [r3, #20]\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n+\tmul.w\tr0, r5, ip\n \tldr\tr3, [r7, #76]\t@ 0x4c\n-\tmov.w\tfp, #0\n-\tadds\tr6, r2, r3\n-\tldr\tr3, [r7, #80]\t@ 0x50\n-\tadd\tr6, r3\n-\tmla\tr5, lr, r6, r9\n+\tmov.w\tsl, #0\n+\tadd.w\tr5, r9, r3\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tadd\tr5, r3\n+\tmla\tr4, ip, r5, r8\n \tmovs\tr3, #0\n-\tb.n\t6fb4 <__gridxc_alloc_MOD_realloc_r3+0x474>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000434\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000041e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000030c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000025c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000013c\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000c4\n- R_ARM_REL32\t.LC28\n \tadds\tr3, #1\n-\tstr\tr4, [r5, #0]\n+\tvstr\ts15, [r4]\n \tcmp\tr1, r3\n-\tadd\tr5, r0\n-\tbne.n\t6fb4 <__gridxc_alloc_MOD_realloc_r3+0x474>\n-\tadd.w\tfp, fp, #1\n-\tadd\tr6, r8\n-\tcmp\tip, fp\n-\tbne.n\t6f70 <__gridxc_alloc_MOD_realloc_r3+0x430>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tadd\tr4, r0\n+\tbne.n\t6ab4 <__gridxc_alloc_MOD_realloc_r3+0x42c>\n \tadd.w\tsl, sl, #1\n-\tadd\tr2, r3\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tcmp\tr3, sl\n-\tbne.n\t6f64 <__gridxc_alloc_MOD_realloc_r3+0x424>\n-\tldrd\tr5, r6, [r7, #52]\t@ 0x34\n-\tldr\tr3, [pc, #892]\t@ (7358 <__gridxc_alloc_MOD_realloc_r3+0x818>)\n+\tadd\tr5, lr\n+\tcmp\tr6, sl\n+\tbne.n\t6aae <__gridxc_alloc_MOD_realloc_r3+0x426>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tadds\tr2, #1\n+\tadd\tr9, fp\n+\tcmp\tr3, r2\n+\tbne.n\t6aa0 <__gridxc_alloc_MOD_realloc_r3+0x418>\n+\tldr\tr4, [r7, #64]\t@ 0x40\n+\tldr\tr3, [pc, #720]\t@ (6da8 <__gridxc_alloc_MOD_realloc_r3+0x720>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t7148 <__gridxc_alloc_MOD_realloc_r3+0x608>\n-\tldr\tr3, [r5, #8]\n-\tstr\tr3, [r7, #48]\t@ 0x30\n+\tbeq.w\t6c40 <__gridxc_alloc_MOD_realloc_r3+0x5b8>\n+\tldr\tr3, [r4, #8]\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr2, r3\n-\tldr\tr3, [r5, #12]\n-\tstr.w\tsp, [r7, #16]\n+\tldr\tr3, [r4, #12]\n+\tstr.w\tsp, [r7, #8]\n \tsubs\tr3, r3, r2\n-\tldrd\tlr, r2, [r5]\n-\tsub.w\tip, r2, lr\n-\tldrd\tsl, r2, [r5, #16]\n+\tldrd\tr6, r2, [r4]\n+\tsub.w\tip, r2, r6\n+\tldrd\tlr, r2, [r4, #16]\n \torr.w\tr0, ip, r3\n \tadd.w\tr9, ip, #1\n-\tsub.w\tr1, r2, sl\n+\tsub.w\tr1, r2, lr\n \tadds\tr2, r3, #1\n-\tstr\tr1, [r7, #76]\t@ 0x4c\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tmla\tr4, ip, r2, r2\n-\tldr\tr2, [r6, #0]\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tldr\tr2, [r6, #4]\n-\tstr\tr2, [r7, #12]\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tstr\tr4, [r7, #64]\t@ 0x40\n+\tldr\tr5, [r2, #0]\n+\tldr\tr2, [r2, #4]\n+\tstr\tr2, [r7, #4]\n \torrs.w\tr2, r1, r0\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tbmi.w\t71f2 <__gridxc_alloc_MOD_realloc_r3+0x6b2>\n+\tstr\tr5, [r7, #76]\t@ 0x4c\n+\tbmi.w\t6cea <__gridxc_alloc_MOD_realloc_r3+0x662>\n \tmla\tr2, r1, r4, r4\n \tlsls\tr2, r2, #2\n \tadds\tr2, #7\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tr4, sp\n \tcmp\tr4, r1\n-\tbeq.w\t7278 <__gridxc_alloc_MOD_realloc_r3+0x738>\n+\tbeq.w\t6d6e <__gridxc_alloc_MOD_realloc_r3+0x6e6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t703e <__gridxc_alloc_MOD_realloc_r3+0x4fe>\n-\tldrd\tr4, r2, [r7, #64]\t@ 0x40\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n-\tadd\tr4, r1\n-\tldr\tr1, [r7, #72]\t@ 0x48\n-\tadds\tr0, #1\n+\tb.n\t6b3c <__gridxc_alloc_MOD_realloc_r3+0x4b4>\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr0, [r7, #52]\t@ 0x34\n+\tldrd\tr2, r4, [r7, #56]\t@ 0x38\n+\tadd\tr0, r1\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tadds\tr4, #1\n \tadd\tr2, r1\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n-\tcmp\tr1, r0\n-\tbge.w\t72de <__gridxc_alloc_MOD_realloc_r3+0x79e>\n-\tldr\tr5, [r7, #32]\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n-\tldr\tr6, [r7, #28]\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tcmp\tr1, r4\n+\tbge.w\t6e0a <__gridxc_alloc_MOD_realloc_r3+0x782>\n+\tldr\tr5, [r7, #28]\n+\tadd.w\tr0, r7, #84\t@ 0x54\n+\tldr\tr6, [r7, #24]\n \tmovs\tr4, #1\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n-\tstr.w\tr3, [r7, #596]\t@ 0x254\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tldrd\tr2, r3, [r7, #472]\t@ 0x1d8\n-\tldr.w\tsp, [r7, #16]\n+\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tldrd\tr2, r3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tsp, [r7, #8]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #460]\t@ 0x1cc\n+\tldrd\tr1, r2, [r7, #404]\t@ 0x194\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #484]\t@ 0x1e4\n+\tldrd\tr1, r2, [r7, #428]\t@ 0x1ac\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #676]\t@ (735c <__gridxc_alloc_MOD_realloc_r3+0x81c>)\n+\tldr\tr1, [pc, #504]\t@ (6dac <__gridxc_alloc_MOD_realloc_r3+0x724>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #24]\n-\tcbz\tr3, 70e8 <__gridxc_alloc_MOD_realloc_r3+0x5a8>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #20]\n+\tcbz\tr3, 6be6 <__gridxc_alloc_MOD_realloc_r3+0x55e>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tvldr\td18, [pc, #588]\t@ 7340 <__gridxc_alloc_MOD_realloc_r3+0x800>\n-\tvldr\td19, [pc, #592]\t@ 7348 <__gridxc_alloc_MOD_realloc_r3+0x808>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tldr\tr0, [pc, #608]\t@ (7360 <__gridxc_alloc_MOD_realloc_r3+0x820>)\n-\tvldr\td17, [pc, #592]\t@ 7350 <__gridxc_alloc_MOD_realloc_r3+0x810>\n-\tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n+\tldr\tr0, [pc, #456]\t@ (6db0 <__gridxc_alloc_MOD_realloc_r3+0x728>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #36]\t@ 0x24\n+\tadd\tr0, pc\n+\tstrd\tr5, r5, [r7, #340]\t@ 0x154\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tldrd\tr2, r1, [r7, #24]\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #352]\t@ 0x160\n+\tstr.w\tr4, [r7, #368]\t@ 0x170\n \tmovs\tr4, #4\n-\tldrd\tr2, r1, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #392]\t@ 0x188\n+\tstr.w\tr4, [r7, #348]\t@ 0x15c\n+\tstr.w\tr4, [r7, #336]\t@ 0x150\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #360]\t@ 0x168\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #396]\t@ 0x18c\n-\tstrh.w\tr4, [r7, #400]\t@ 0x190\n+\tstrh.w\tr4, [r7, #344]\t@ 0x158\n \tmovs\tr4, #3\n-\tstr.w\tr4, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr4, [r7, #372]\t@ 0x174\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #388]\t@ 0x184\n-\tldr.w\tr4, [r7, #600]\t@ 0x258\n-\tldr\tr3, [r7, #20]\n+\tstr.w\tr4, [r7, #332]\t@ 0x14c\n+\tldr.w\tr4, [r7, #512]\t@ 0x200\n+\tldr\tr3, [r7, #32]\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n+\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #536]\t@ (7364 <__gridxc_alloc_MOD_realloc_r3+0x824>)\n-\tldr\tr3, [pc, #540]\t@ (7368 <__gridxc_alloc_MOD_realloc_r3+0x828>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #368]\t@ (6db4 <__gridxc_alloc_MOD_realloc_r3+0x72c>)\n+\tldr\tr3, [pc, #332]\t@ (6d90 <__gridxc_alloc_MOD_realloc_r3+0x708>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t732e <__gridxc_alloc_MOD_realloc_r3+0x7ee>\n-\tadd.w\tr7, r7, #500\t@ 0x1f4\n+\tbne.w\t6e5a <__gridxc_alloc_MOD_realloc_r3+0x7d2>\n+\tadd.w\tr7, r7, #444\t@ 0x1bc\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #216\t@ 0xd8\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tb.n\t6c1e <__gridxc_alloc_MOD_realloc_r3+0xde>\n-\tldrd\tr2, r3, [r7, #472]\t@ 0x1d8\n-\tadd.w\tr0, r7, #140\t@ 0x8c\n-\tldr\tr4, [r7, #32]\n-\tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #460]\t@ 0x1cc\n-\tadds\tr3, #1\n-\tcmp\tr4, #0\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tb.n\t6762 <__gridxc_alloc_MOD_realloc_r3+0xda>\n+\tldr\tr3, [r7, #28]\n+\tadd.w\tr0, r7, #84\t@ 0x54\n+\tcmp\tr3, #0\n+\tldrd\tr2, r3, [r7, #416]\t@ 0x1a0\n+\tsub.w\tr3, r3, r2\n+\tldrd\tr1, r2, [r7, #404]\t@ 0x194\n+\tadd\tr3, r5\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #484]\t@ 0x1e4\n+\tldrd\tr1, r2, [r7, #428]\t@ 0x1ac\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #448]\t@ (736c <__gridxc_alloc_MOD_realloc_r3+0x82c>)\n-\tadd.w\tr2, r2, #1\n-\tadd\tr1, pc\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n+\tstr\tr5, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #28]\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n-\tcmp\tr2, #0\n+\tldr\tr5, [r7, #24]\n+\tldr.w\tr1, [r7, #512]\t@ 0x200\n+\tcmp\tr5, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #236]\t@ (6db8 <__gridxc_alloc_MOD_realloc_r3+0x730>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tmov\tr2, r4\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #24]\n+\tldr\tr2, [r7, #28]\n+\tadd\tr1, pc\n+\tmov\tr3, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #20]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr.w\tsl, [r9, #16]\n-\tstr.w\tsl, [r7, #24]\n-\tb.n\t6d46 <__gridxc_alloc_MOD_realloc_r3+0x206>\n+\tstr.w\tsl, [r7, #20]\n+\tb.n\t6864 <__gridxc_alloc_MOD_realloc_r3+0x1dc>\n \tcmp\tr1, #0\n-\tblt.w\t7068 <__gridxc_alloc_MOD_realloc_r3+0x528>\n-\tldr.w\tr8, [r7, #20]\n-\tldr\tr2, [r6, #24]\n-\tstr\tr2, [r7, #56]\t@ 0x38\n+\tblt.w\t6b66 <__gridxc_alloc_MOD_realloc_r3+0x4de>\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tldr.w\tr8, [r7, #32]\n+\tldr\tr2, [r2, #24]\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n \tcmp\tr0, #0\n-\tblt.w\t7068 <__gridxc_alloc_MOD_realloc_r3+0x528>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tldr\tr4, [r7, #48]\t@ 0x30\n-\tstr.w\tlr, [r7, #52]\t@ 0x34\n-\tstrd\tr6, sl, [r7, #4]\n-\tmla\tr2, sl, r1, r2\n+\tblt.w\t6b66 <__gridxc_alloc_MOD_realloc_r3+0x4de>\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n+\tldr\tr2, [r7, #12]\n+\tldr\tr4, [r7, #40]\t@ 0x28\n+\tmla\tr2, lr, r1, r2\n \tmul.w\tr1, r0, r1\n-\tstr\tr1, [r7, #60]\t@ 0x3c\n-\tldr.w\tr1, [r7, #468]\t@ 0x1d4\n+\tstr\tr1, [r7, #48]\t@ 0x30\n+\tldr.w\tr1, [r7, #412]\t@ 0x19c\n \tmla\tr2, r4, r1, r2\n \tmul.w\tfp, r0, r1\n-\tldr\tr1, [r7, #64]\t@ 0x40\n-\tmla\tr2, lr, r1, r2\n+\tldr\tr1, [r7, #16]\n+\tstrd\tlr, r6, [r7, #12]\n+\tmla\tr2, r6, r1, r2\n \tmul.w\tr5, r0, r1\n-\tldr\tr1, [r7, #24]\n+\tldr\tr1, [r7, #20]\n \tmla\tr0, r0, r2, r1\n \tmovs\tr2, #0\n \tmov\tr4, r2\n \tmov\tlr, r2\n \tmov\tr6, r0\n \tmov.w\tsl, #0\n-\tstr\tr0, [r7, #80]\t@ 0x50\n-\tstrd\tr2, r4, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr4, r0, [r7, #56]\t@ 0x38\n \tadd.w\tr4, r8, lr, lsl #2\n \tmov\tr0, r6\n \tmovs\tr1, #0\n \tldr\tr2, [r0, #0]\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tadd\tr0, r5\n \tadd.w\tr1, r1, #1\n \tstr.w\tr2, [r4], #4\n-\tbne.n\t7258 <__gridxc_alloc_MOD_realloc_r3+0x718>\n+\tbne.n\t6d4e <__gridxc_alloc_MOD_realloc_r3+0x6c6>\n \tadd\tr6, fp\n \tadd\tlr, r9\n \tadd.w\tr2, sl, #1\n-\tcmp\tsl, r3\n-\tbeq.n\t728e <__gridxc_alloc_MOD_realloc_r3+0x74e>\n+\tcmp\tr3, sl\n+\tbeq.n\t6dbc <__gridxc_alloc_MOD_realloc_r3+0x734>\n \tmov\tsl, r2\n-\tb.n\t7250 <__gridxc_alloc_MOD_realloc_r3+0x710>\n+\tb.n\t6d46 <__gridxc_alloc_MOD_realloc_r3+0x6be>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.n\t7322 <__gridxc_alloc_MOD_realloc_r3+0x7e2>\n-\tldr\tr2, [r6, #24]\n+\tbne.n\t6e4e <__gridxc_alloc_MOD_realloc_r3+0x7c6>\n+\tldr\tr2, [r7, #52]\t@ 0x34\n \tadd.w\tr8, sp, #16\n-\tstr\tr2, [r7, #56]\t@ 0x38\n-\tb.n\t7200 <__gridxc_alloc_MOD_realloc_r3+0x6c0>\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tldr\tr0, [r7, #80]\t@ 0x50\n-\tldrd\tr2, r4, [r7, #64]\t@ 0x40\n-\tadd\tr0, r1\n-\tldr\tr1, [r7, #72]\t@ 0x48\n+\tldr\tr2, [r2, #24]\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n+\tb.n\t6cfa <__gridxc_alloc_MOD_realloc_r3+0x672>\n+\tnop\n+\t.word\t0x00000000\n+\t.word\t0x000006e0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000006cc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005b8\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000530\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000418\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000037e\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x000002cc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001f2\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x000001c0\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000016c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x000000e2\n+ R_ARM_REL32\t.LC28\n+\tldrd\tr4, r0, [r7, #56]\t@ 0x38\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr2, [r7, #72]\t@ 0x48\n \tadds\tr4, #1\n+\tadd\tr0, r1\n+\tldr\tr1, [r7, #64]\t@ 0x40\n \tadd\tr2, r1\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n-\tcmp\tr1, r4\n-\tbge.n\t7242 <__gridxc_alloc_MOD_realloc_r3+0x702>\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tldr.w\tlr, [r7, #52]\t@ 0x34\n-\tldrd\tr6, sl, [r7, #4]\n-\tldr\tr0, [r7, #12]\n-\tmul.w\tr2, lr, r1\n-\tstr\tr2, [r7, #52]\t@ 0x34\n-\tldr\tr2, [r6, #48]\t@ 0x30\n-\tldr.w\tfp, [r6, #36]\t@ 0x24\n-\tstr\tr2, [r7, #56]\t@ 0x38\n-\tmla\tr2, sl, r2, r0\n-\tldr.w\tsl, [r6, #20]\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tmov\tr4, r2\n-\tstr.w\tsl, [r7, #80]\t@ 0x50\n-\tmul.w\tlr, r1, sl\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tcmp\tr4, r1\n+\tble.n\t6d38 <__gridxc_alloc_MOD_realloc_r3+0x6b0>\n+\tldr\tr0, [r7, #44]\t@ 0x2c\n+\tldrd\tlr, r6, [r7, #12]\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tldr\tr4, [r7, #4]\n+\tmul.w\tr2, r6, r0\n+\tldr.w\tsl, [r1, #20]\n+\tldr.w\tfp, [r1, #36]\t@ 0x24\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n+\tldr\tr2, [r1, #48]\t@ 0x30\n+\tldr\tr1, [r7, #40]\t@ 0x28\n+\tstr\tr2, [r7, #48]\t@ 0x30\n+\tstr.w\tsl, [r7, #72]\t@ 0x48\n+\tmla\tr2, lr, r2, r4\n+\tmul.w\tr1, r1, fp\n+\tstr\tr1, [r7, #40]\t@ 0x28\n \tmovs\tr1, #0\n-\tmul.w\tr0, r0, fp\n+\tmul.w\tlr, r0, sl\n+\tmov\tr4, r1\n+\tmov\tr0, r2\n \tmov\tr2, r1\n-\tstr\tr0, [r7, #48]\t@ 0x30\n-\tmov\tr0, r1\n-\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr1, [r7, #40]\t@ 0x28\n \tmov\tr6, r2\n \tmov.w\tsl, #0\n-\tstrd\tr4, r2, [r7, #64]\t@ 0x40\n-\tadds\tr5, r4, r1\n-\tldr\tr1, [r7, #52]\t@ 0x34\n-\tstr\tr0, [r7, #60]\t@ 0x3c\n+\tstrd\tr2, r4, [r7, #56]\t@ 0x38\n+\tadds\tr5, r0, r1\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n+\tstr\tr0, [r7, #52]\t@ 0x34\n \tadd\tr5, r1\n-\tldrd\tr1, r2, [r7, #80]\t@ 0x50\n+\tldrd\tr1, r2, [r7, #72]\t@ 0x48\n \tadd.w\tr4, r8, r6, lsl #2\n \tmla\tr0, r1, r5, r2\n \tmovs\tr1, #0\n \tldr.w\tr2, [r4], #4\n \tcmp\tr1, ip\n \tstr\tr2, [r0, #0]\n \tadd.w\tr1, r1, #1\n \tadd\tr0, lr\n-\tbne.n\t7300 <__gridxc_alloc_MOD_realloc_r3+0x7c0>\n+\tbne.n\t6e2c <__gridxc_alloc_MOD_realloc_r3+0x7a4>\n \tadd\tr5, fp\n \tadd\tr6, r9\n \tadd.w\tr2, sl, #1\n-\tcmp\tsl, r3\n-\tbeq.w\t7050 <__gridxc_alloc_MOD_realloc_r3+0x510>\n+\tcmp\tr3, sl\n+\tbeq.w\t6b4e <__gridxc_alloc_MOD_realloc_r3+0x4c6>\n \tmov\tsl, r2\n-\tb.n\t72f2 <__gridxc_alloc_MOD_realloc_r3+0x7b2>\n+\tb.n\t6e1e <__gridxc_alloc_MOD_realloc_r3+0x796>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n-\tb.n\t7284 <__gridxc_alloc_MOD_realloc_r3+0x744>\n-\tmov\tr9, r2\n-\tb.n\t6dac <__gridxc_alloc_MOD_realloc_r3+0x26c>\n+\tb.n\t6d7a <__gridxc_alloc_MOD_realloc_r3+0x6f2>\n+\tmov\tr9, sl\n+\tb.n\t68d0 <__gridxc_alloc_MOD_realloc_r3+0x248>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr9, #5014\t@ 0x1396\n-\tb.n\t6e46 <__gridxc_alloc_MOD_realloc_r3+0x306>\n+\tb.n\t697c <__gridxc_alloc_MOD_realloc_r3+0x2f4>\n \tmovw\tr9, #5020\t@ 0x139c\n-\tb.n\t6e46 <__gridxc_alloc_MOD_realloc_r3+0x306>\n+\tb.n\t697c <__gridxc_alloc_MOD_realloc_r3+0x2f4>\n \tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000378\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002a0\n- R_ARM_REL32\t.LC28\n-\t.word\t0x0000025a\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000214\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000001ba\n- R_ARM_REL32\t.LC28\n \n-00007370 <__gridxc_alloc_MOD_realloc_r2>:\n+00006e6c <__gridxc_alloc_MOD_realloc_r2>:\n __gridxc_alloc_MOD_realloc_r2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3640]\t@ 0xe38\n-\tsub\tsp, #404\t@ 0x194\n+\tstr.w\tr0, [ip, #3704]\t@ 0xe78\n+\tsub\tsp, #356\t@ 0x164\n \tadd\tr7, sp, #16\n \tmov\tfp, r0\n-\tldr\tr4, [pc, #1004]\t@ (7778 <__gridxc_alloc_MOD_realloc_r2+0x408>)\n-\tmov\tr9, r3\n-\tldr\tr6, [pc, #1004]\t@ (777c <__gridxc_alloc_MOD_realloc_r2+0x40c>)\n-\tldrd\tr5, r0, [r7, #440]\t@ 0x1b8\n-\tstr\tr0, [r7, #68]\t@ 0x44\n-\tldr\tr0, [pc, #1000]\t@ (7780 <__gridxc_alloc_MOD_realloc_r2+0x410>)\n-\tadd\tr4, pc\n-\tadd\tr6, pc\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tldr\tr0, [r4, r0]\n+\tldr.w\tr5, [pc, #1560]\t@ 749c <__gridxc_alloc_MOD_realloc_r2+0x630>\n+\tldrd\tr4, r0, [r7, #376]\t@ 0x178\n+\tstr\tr0, [r7, #56]\t@ 0x38\n+\tldr.w\tr0, [pc, #1552]\t@ 74a0 <__gridxc_alloc_MOD_realloc_r2+0x634>\n+\tadd\tr5, pc\n+\tldr.w\tr6, [r7, #384]\t@ 0x180\n+\tldr.w\tip, [r7, #392]\t@ 0x188\n+\tldr\tr0, [r5, r0]\n+\tldr.w\tr5, [pc, #1540]\t@ 74a4 <__gridxc_alloc_MOD_realloc_r2+0x638>\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #380]\t@ 0x17c\n+\tstr.w\tr0, [r7, #332]\t@ 0x14c\n \tmov.w\tr0, #0\n \tldr.w\tr0, [fp]\n-\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd\tr5, pc\n+\tstr\tr6, [r7, #60]\t@ 0x3c\n \tcmp\tr0, #0\n-\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tite\tne\n+\tmovne\tr6, #1\n+\tmoveq\tr6, #0\n+\tstr\tr6, [r5, #0]\n \tit\teq\n \tmoveq\tsl, r0\n-\tmov.w\tr3, #1\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [r6, #0]\n-\tldr.w\tr6, [r7, #456]\t@ 0x1c8\n-\tbeq.n\t742e <__gridxc_alloc_MOD_realloc_r2+0xbe>\n-\tldr.w\tr4, [fp, #44]\t@ 0x2c\n-\tstr\tr4, [r7, #52]\t@ 0x34\n-\tldr.w\tr4, [fp, #28]\n-\tstr\tr4, [r7, #48]\t@ 0x30\n-\tldr.w\tr4, [fp, #32]\n-\tstr\tr4, [r7, #44]\t@ 0x2c\n-\tldr.w\tr4, [fp, #36]\t@ 0x24\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tldr.w\tr4, [fp, #4]\n-\tstr\tr4, [r7, #16]\n-\tldr.w\tr4, [fp, #24]\n-\tldr.w\tr3, [fp, #40]\t@ 0x28\n-\tstr\tr4, [r7, #20]\n-\tldr\tr4, [r7, #52]\t@ 0x34\n-\tstr\tr3, [r7, #32]\n-\tsub.w\tlr, r4, r3\n+\tldr.w\tr5, [r7, #388]\t@ 0x184\n+\tstr\tr5, [r7, #68]\t@ 0x44\n+\tbeq.n\t6f24 <__gridxc_alloc_MOD_realloc_r2+0xb8>\n+\tldr.w\tr6, [fp, #44]\t@ 0x2c\n+\tstr\tr6, [r7, #44]\t@ 0x2c\n+\tldr.w\tr6, [fp, #28]\n+\tstr\tr6, [r7, #40]\t@ 0x28\n+\tldr.w\tr6, [fp, #32]\n+\tstr\tr6, [r7, #36]\t@ 0x24\n+\tldr.w\tr6, [fp, #36]\t@ 0x24\n+\tstr\tr6, [r7, #12]\n+\tldr.w\tr6, [fp, #4]\n+\tstr\tr6, [r7, #4]\n+\tldr.w\tr6, [fp, #24]\n+\tldr.w\tr5, [fp, #40]\t@ 0x28\n+\tstr\tr6, [r7, #8]\n+\tldr\tr6, [r7, #44]\t@ 0x2c\n+\tstr\tr5, [r7, #32]\n+\tsub.w\tlr, r6, r5\n \tldr.w\tsl, [fp, #20]\n-\tldrd\tr3, r4, [r7, #44]\t@ 0x2c\n-\tcmp\tr3, r4\n-\tblt.w\t79a6 <__gridxc_alloc_MOD_realloc_r2+0x636>\n+\tldrd\tr5, r6, [r7, #36]\t@ 0x24\n+\tcmp\tr5, r6\n+\tblt.w\t7444 <__gridxc_alloc_MOD_realloc_r2+0x5d8>\n \tcmp.w\tlr, #0\n-\tstr.w\tr4, [r7, #168]\t@ 0xa8\n-\tldr.w\tlr, [r7, #44]\t@ 0x2c\n-\tblt.w\t79c4 <__gridxc_alloc_MOD_realloc_r2+0x654>\n-\tldr.w\tip, [r7, #32]\n-\tldr.w\tr8, [r7, #52]\t@ 0x34\n-\tstrd\tlr, ip, [r7, #172]\t@ 0xac\n-\tstr.w\tr8, [r7, #180]\t@ 0xb4\n-\tstr\tr0, [r7, #56]\t@ 0x38\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr3, [r5, #0]\n-\tldr.w\tr0, [r9]\n-\tadd.w\tr5, r7, #364\t@ 0x16c\n-\tvldr\td18, [pc, #792]\t@ 7758 <__gridxc_alloc_MOD_realloc_r2+0x3e8>\n-\tvldr\td19, [pc, #796]\t@ 7760 <__gridxc_alloc_MOD_realloc_r2+0x3f0>\n-\tstr\tr5, [r7, #36]\t@ 0x24\n-\tldr\tr1, [r1, #0]\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr0, r3, [r7, #104]\t@ 0x68\n-\tadd.w\tr3, r7, #204\t@ 0xcc\n-\tstrd\tr1, r2, [r7, #96]\t@ 0x60\n-\tadd.w\tr0, r7, #348\t@ 0x15c\n-\tvldr\td17, [pc, #780]\t@ 7768 <__gridxc_alloc_MOD_realloc_r2+0x3f8>\n-\tmovs\tr2, #2\n-\tvldr\td20, [r7, #96]\t@ 0x60\n-\tvldr\td21, [r7, #104]\t@ 0x68\n-\tvstr\td16, [r7, #192]\t@ 0xc0\n-\tvstr\td16, [r7, #196]\t@ 0xc4\n-\tadd.w\tr1, r7, #136\t@ 0x88\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #220\t@ 0xdc\n-\tvstr\td16, [r7, #240]\t@ 0xf0\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #252\t@ 0xfc\n-\tvstr\td16, [r7, #244]\t@ 0xf4\n-\tvstr\td16, [r7, #288]\t@ 0x120\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tvstr\td16, [r7, #292]\t@ 0x124\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #300\t@ 0x12c\n-\tstr\tr0, [r7, #40]\t@ 0x28\n-\tstr.w\tr2, [r7, #228]\t@ 0xe4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #316\t@ 0x13c\n-\tstr.w\tr2, [r7, #276]\t@ 0x114\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #328\t@ 0x148\n-\tmov\tr4, r3\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tstr.w\tr2, [r7, #324]\t@ 0x144\n-\tmvn.w\tr3, #2\n-\tvstr\td16, [r7, #336]\t@ 0x150\n-\tstr.w\tr3, [r7, #188]\t@ 0xbc\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tvstr\td20, [r7, #120]\t@ 0x78\n-\tvstr\td21, [r7, #128]\t@ 0x80\n-\tstr.w\tr1, [r7, #184]\t@ 0xb8\n-\tadd.w\tr1, r7, #152\t@ 0x98\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n-\tadd.w\tr2, r7, #280\t@ 0x118\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstr.w\tr1, [r7, #232]\t@ 0xe8\n-\tadd.w\tr1, r7, #168\t@ 0xa8\n-\tvst1.32\t{d18-d19}, [r0]\n-\tadd.w\tr0, r7, #184\t@ 0xb8\n-\tvst1.32\t{d17}, [r5]\n-\tadd.w\tr5, r7, #120\t@ 0x78\n-\tstr\tr1, [r7, #28]\n-\tstr.w\tr1, [r7, #280]\t@ 0x118\n-\tadd.w\tr1, r7, #232\t@ 0xe8\n-\tstr.w\tr5, [r7, #328]\t@ 0x148\n-\tstr\tr6, [sp, #4]\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr6, [r7, #124]\t@ 0x7c\n+\tldr.w\tlr, [r7, #36]\t@ 0x24\n+\tblt.w\t745a <__gridxc_alloc_MOD_realloc_r2+0x5ee>\n+\tldr\tr5, [r7, #32]\n+\tldr.w\tr8, [r7, #44]\t@ 0x2c\n+\tstrd\tlr, r5, [r7, #128]\t@ 0x80\n+\tstr.w\tr8, [r7, #136]\t@ 0x88\n+\tstr\tr0, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r3, #0]\n+\tmovs\tr5, #1\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tmovs\tr0, #4\n+\tldr\tr3, [r1, #0]\n+\tadd.w\tlr, r7, #92\t@ 0x5c\n+\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tmvn.w\tr1, #2\n+\tldr\tr3, [r4, #0]\n+\tadd.w\tr9, r7, #108\t@ 0x6c\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tadd.w\tr4, r7, #76\t@ 0x4c\n+\tldr\tr3, [r2, #0]\n+\tmovs\tr2, #0\n+\tstr\tr3, [r7, #112]\t@ 0x70\n+\tadd.w\tr3, r7, #284\t@ 0x11c\n+\tmov\tr6, r3\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tstrd\tr2, r2, [r7, #148]\t@ 0x94\n+\tmovs\tr3, #2\n+\tstr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstrd\tr2, r2, [r7, #196]\t@ 0xc4\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tstr.w\tr3, [r7, #172]\t@ 0xac\n+\tstr.w\tr3, [r7, #184]\t@ 0xb8\n+\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tstr.w\tr3, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #160]\t@ 0xa0\n+\tstr.w\tr0, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #144]\t@ 0x90\n+\tstr.w\tr1, [r7, #192]\t@ 0xc0\n+\tstrd\tr5, r5, [r7, #164]\t@ 0xa4\n+\tstr.w\tr5, [r7, #180]\t@ 0xb4\n+\tstrd\tr5, r5, [r7, #212]\t@ 0xd4\n+\tstr.w\tr5, [r7, #228]\t@ 0xe4\n+\tstr.w\tr4, [r7, #140]\t@ 0x8c\n+\tstr.w\tlr, [r7, #188]\t@ 0xbc\n+\tstrd\tr1, r2, [r7, #288]\t@ 0x120\n+\tstr.w\tr0, [r7, #256]\t@ 0x100\n+\tstr.w\tr0, [r7, #304]\t@ 0x130\n+\tadd.w\tr0, r7, #140\t@ 0x8c\n+\tstrd\tr2, r2, [r7, #244]\t@ 0xf4\n+\tstr.w\tr2, [r7, #252]\t@ 0xfc\n+\tstrd\tr5, r3, [r7, #264]\t@ 0x108\n+\tstrd\tr5, r3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr1, [r7, #240]\t@ 0xf0\n+\tadd.w\tr1, r7, #188\t@ 0xbc\n+\tstrd\tr2, r2, [r7, #296]\t@ 0x128\n+\tadd.w\tr2, r7, #124\t@ 0x7c\n+\tstrd\tr5, r3, [r7, #312]\t@ 0x138\n+\tstrd\tr5, r3, [r7, #324]\t@ 0x144\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tstr\tr2, [r7, #28]\n+\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tadd.w\tr2, r7, #236\t@ 0xec\n+\tstr.w\tr5, [r7, #260]\t@ 0x104\n+\tstr.w\tr5, [r7, #308]\t@ 0x134\n+\tstr.w\tr9, [r7, #284]\t@ 0x11c\n+\tstr.w\tip, [sp, #4]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r4\n-\tldr\tr4, [pc, #600]\t@ (7784 <__gridxc_alloc_MOD_realloc_r2+0x414>)\n-\tbl\t1fc <__gridxc_alloc_MOD_options.constprop.1>\n-\tadd\tr4, pc\n-\tldr\tr3, [r4, #8]\n-\tcbz\tr3, 753c <__gridxc_alloc_MOD_realloc_r2+0x1cc>\n-\tldr\tr6, [r4, #12]\n-\tcmp\tr6, #0\n-\tbeq.w\t7940 <__gridxc_alloc_MOD_realloc_r2+0x5d0>\n-\tldr\tr3, [pc, #584]\t@ (7788 <__gridxc_alloc_MOD_realloc_r2+0x418>)\n+\tmov\tr3, r6\n+\tldr.w\tr6, [pc, #1184]\t@ 74a8 <__gridxc_alloc_MOD_realloc_r2+0x63c>\n+\tbl\t1ec <__gridxc_alloc_MOD_options.constprop.1>\n+\tadd\tr6, pc\n+\tldr\tr3, [r6, #8]\n+\tcbz\tr3, 701e <__gridxc_alloc_MOD_realloc_r2+0x1b2>\n+\tldr.w\tr8, [r6, #12]\n+\tcmp.w\tr8, #0\n+\tbeq.w\t73d8 <__gridxc_alloc_MOD_realloc_r2+0x56c>\n+\tldr.w\tr3, [pc, #1164]\t@ 74ac <__gridxc_alloc_MOD_realloc_r2+0x640>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t76ee <__gridxc_alloc_MOD_realloc_r2+0x37e>\n-\tldrd\tr4, r0, [r7, #136]\t@ 0x88\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r6, [r7, #144]\t@ 0x90\n-\tsubs\tr2, r0, r4\n-\torr.w\tr1, r2, r2, asr #31\n-\tvstr\td16, [fp, #12]\n-\tadds\tr1, #1\n-\tstr\tr4, [r7, #80]\t@ 0x50\n-\tnegs\tr4, r4\n-\tstrd\tr1, r3, [r7, #88]\t@ 0x58\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tmovs\tr0, #4\n-\tvldr\td8, [r7, #80]\t@ 0x50\n-\tvldr\td9, [r7, #88]\t@ 0x58\n-\tmls\tr4, r1, r3, r4\n-\tsubs\tr3, r6, r3\n-\tstr.w\tr0, [fp, #8]\n-\torrs\tr2, r3\n-\tmovw\tr0, #770\t@ 0x302\n-\torr.w\tr3, r3, r3, asr #31\n-\tstrh.w\tr0, [fp, #16]\n-\tlsrs\tr2, r2, #31\n-\tadds\tr3, #1\n-\tbeq.w\t79ea <__gridxc_alloc_MOD_realloc_r2+0x67a>\n-\tmvn.w\tip, #2147483648\t@ 0x80000000\n-\tudiv\tip, ip, r3\n-\tmul.w\tr3, r1, r3\n+\tbeq.w\t71d8 <__gridxc_alloc_MOD_realloc_r2+0x36c>\n+\tldr\tr3, [r4, #0]\n+\tmovs\tr5, #0\n+\tldr\tr1, [r4, #4]\n+\tldrd\tr2, r4, [r4, #8]\n+\tsubs\tr6, r1, r3\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tnegs\tr0, r3\n+\tstr\tr3, [r7, #24]\n+\torr.w\tr8, r6, r6, asr #31\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tsubs\tr2, r4, r2\n+\torrs\tr6, r2\n+\tstr\tr1, [r7, #64]\t@ 0x40\n+\torr.w\tr2, r2, r2, asr #31\n+\tstrd\tr5, r5, [fp, #12]\n+\tlsrs\tr6, r6, #31\n+\tmla\tr1, r8, r3, r3\n+\tadd.w\tr8, r8, #1\n+\tsubs\tr3, r0, r1\n+\tmovs\tr1, #4\n+\tstr\tr3, [r7, #20]\n+\tstr.w\tr1, [fp, #8]\n+\tmovw\tr1, #770\t@ 0x302\n+\tstrh.w\tr1, [fp, #16]\n+\tadds\tr1, r2, #1\n+\tbeq.w\t747e <__gridxc_alloc_MOD_realloc_r2+0x612>\n+\tmul.w\tr3, r1, r8\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr3, [r7, #16]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #16]\n \tcmp.w\tr3, #1073741824\t@ 0x40000000\n+\tite\tlt\n+\tmovlt\tr2, #0\n+\tmovge\tr2, #1\n+\tcmp\tr0, r8\n \tit\tlt\n-\tmovlt\tr0, #0\n-\tit\tge\n-\tmovge\tr0, #1\n-\tcmp\tip, r1\n-\tit\tlt\n-\taddlt\tr0, #1\n+\taddlt\tr2, #1\n+\tlsls\tr0, r3, #2\n+\tcbz\tr6, 709a <__gridxc_alloc_MOD_realloc_r2+0x22e>\n+\tmov\tr0, r5\n \tcmp\tr2, #0\n-\tbne.w\t79c0 <__gridxc_alloc_MOD_realloc_r2+0x650>\n-\tlsls\tr2, r3, #2\n-\tcmp\tr0, #0\n-\tbne.w\t79f8 <__gridxc_alloc_MOD_realloc_r2+0x688>\n-\tcmp\tr2, #1\n+\tbne.w\t748e <__gridxc_alloc_MOD_realloc_r2+0x622>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr2, #1\n-\tmov\tr0, r2\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr.w\tr0, [fp]\n \tcmp\tr0, #0\n-\tbeq.w\t79fe <__gridxc_alloc_MOD_realloc_r2+0x68e>\n-\tadd.w\tr3, fp, #28\n-\tstr.w\tr6, [fp, #44]\t@ 0x2c\n-\tvldr\td16, [pc, #400]\t@ 7770 <__gridxc_alloc_MOD_realloc_r2+0x400>\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, fp, #20\n-\tstr.w\tr4, [fp, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t7494 <__gridxc_alloc_MOD_realloc_r2+0x628>\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr2, #1\n+\tstr.w\tr3, [fp, #28]\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr.w\tr3, [fp, #32]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tstrd\tr3, r4, [fp, #40]\t@ 0x28\n+\tldr\tr3, [r7, #20]\n+\tstr.w\tr3, [fp, #4]\n+\tmovs\tr3, #4\n+\tstrd\tr3, r2, [fp, #20]\n \tmovs\tr3, #0\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #348]\t@ 7758 <__gridxc_alloc_MOD_realloc_r2+0x3e8>\n-\tvldr\td19, [pc, #352]\t@ 7760 <__gridxc_alloc_MOD_realloc_r2+0x3f0>\n-\tstr.w\tr5, [r7, #328]\t@ 0x148\n-\tldr\tr0, [pc, #388]\t@ (778c <__gridxc_alloc_MOD_realloc_r2+0x41c>)\n-\tvstr\td17, [r7, #340]\t@ 0x154\n-\tvst1.32\t{d18-d19}, [r2]\n+\tstr.w\tr8, [fp, #36]\t@ 0x24\n+\tldr\tr0, [pc, #980]\t@ (74b0 <__gridxc_alloc_MOD_realloc_r2+0x644>)\n+\tmovs\tr4, #0\n+\tldr\tr1, [r7, #56]\t@ 0x38\n+\tmovs\tr5, #1\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tvldr\td16, [pc, #336]\t@ 7768 <__gridxc_alloc_MOD_realloc_r2+0x3f8>\n-\tldr\tr6, [r7, #68]\t@ 0x44\n-\tldr.w\tr4, [r7, #460]\t@ 0x1cc\n-\tvst1.32\t{d16}, [r2]\n-\tcmp\tr6, #0\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tcmp\tr1, #0\n+\tstr.w\tr9, [r7, #284]\t@ 0x11c\n \tit\teq\n-\tmoveq\tr4, #0\n+\tmoveq\tr6, #0\n+\tstrd\tr5, r5, [r7, #308]\t@ 0x134\n \tstr.w\tr3, [r0, #16]!\n-\tmovs\tr3, #4\n-\tstr.w\tr3, [r7, #336]\t@ 0x150\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #344]\t@ 0x158\n+\tmov\tr9, r1\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n+\tstr.w\tr5, [r7, #324]\t@ 0x144\n+\tit\tne\n+\tmovne\tr6, r3\n \tmovs\tr3, #2\n-\tstr.w\tr3, [r7, #372]\t@ 0x174\n-\tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n+\tstr.w\tr3, [r7, #316]\t@ 0x13c\n \tcmp\tr2, #0\n-\tstr\tr4, [sp, #0]\n-\tmov\tr1, r6\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr5, #0\n-\tstr\tr5, [sp, #4]\n-\tmov\tr8, r2\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #116\t@ 0x74\n+\tmoveq\tr8, r4\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r7, #400]\t@ 0x190\n+\tstrd\tr4, r4, [r7, #296]\t@ 0x128\n+\tit\tne\n+\tmovne\tr8, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #300]\t@ 0x12c\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tstrd\tr6, r8, [sp]\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #72\t@ 0x48\n \tldrd\tr2, r3, [fp, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [fp, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r5\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n-\tldr\tr1, [pc, #276]\t@ (7790 <__gridxc_alloc_MOD_realloc_r2+0x420>)\n+\tadd\tr2, r5\n+\tldr\tr1, [pc, #844]\t@ (74b4 <__gridxc_alloc_MOD_realloc_r2+0x648>)\n \tbic.w\tr2, r2, r2, asr #31\n \tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r6\n+\tmov\tr2, r9\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr4, r5, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r8\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldrd\tr0, r3, [fp, #40]\t@ 0x28\n+\tstrd\tr6, r8, [sp, #4]\n+\tstr\tr5, [sp, #0]\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldrd\tr2, r3, [fp, #40]\t@ 0x28\n \tldrd\tr5, r1, [fp, #28]\n-\tcmp\tr0, r3\n-\tbgt.n\t76ee <__gridxc_alloc_MOD_realloc_r2+0x37e>\n-\tldr.w\tlr, [fp, #36]\t@ 0x24\n+\tcmp\tr2, r3\n+\tbgt.n\t71d8 <__gridxc_alloc_MOD_realloc_r2+0x36c>\n+\tldr.w\tip, [fp, #36]\t@ 0x24\n \tcmp\tr5, r1\n-\tbgt.n\t76ee <__gridxc_alloc_MOD_realloc_r2+0x37e>\n+\tbgt.n\t71d8 <__gridxc_alloc_MOD_realloc_r2+0x36c>\n \tadds\tr3, #1\n-\tldr.w\tr8, [fp, #20]\n-\tsub.w\tip, r3, r0\n+\tldr.w\tlr, [fp, #20]\n+\tsubs\tr6, r3, r2\n \tldr.w\tr3, [fp, #4]\n \tadds\tr1, #1\n-\tldr.w\tr9, [fp]\n+\tldr.w\tr8, [fp]\n \tsubs\tr1, r1, r5\n-\tmovs\tr6, #0\n-\tmovs\tr4, #0\n-\tmla\tr3, r0, lr, r3\n-\tldr.w\tr0, [fp, #24]\n-\tmla\tr5, r0, r5, r3\n-\tmul.w\tr0, r0, r8\n-\tmla\tr2, r8, r5, r9\n+\tmov.w\tr9, #0\n+\tmla\tr3, r2, ip, r3\n+\tldr.w\tr2, [fp, #24]\n+\tmla\tr5, r2, r5, r3\n+\tmul.w\tr0, r2, lr\n+\tmla\tr2, lr, r5, r8\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tstr\tr4, [r2, #0]\n+\tstr.w\tr9, [r2]\n \tcmp\tr1, r3\n \tadd\tr2, r0\n-\tbne.n\t76dc <__gridxc_alloc_MOD_realloc_r2+0x36c>\n-\tadds\tr6, #1\n-\tadd\tr5, lr\n-\tcmp\tip, r6\n-\tbne.n\t76d6 <__gridxc_alloc_MOD_realloc_r2+0x366>\n-\tldr\tr3, [pc, #164]\t@ (7794 <__gridxc_alloc_MOD_realloc_r2+0x424>)\n+\tbne.n\t71c4 <__gridxc_alloc_MOD_realloc_r2+0x358>\n+\tadds\tr4, #1\n+\tadd\tr5, ip\n+\tcmp\tr4, r6\n+\tbne.n\t71be <__gridxc_alloc_MOD_realloc_r2+0x352>\n+\tldr\tr3, [pc, #732]\t@ (74b8 <__gridxc_alloc_MOD_realloc_r2+0x64c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t791c <__gridxc_alloc_MOD_realloc_r2+0x5ac>\n-\tldrd\tr3, r2, [r7, #156]\t@ 0x9c\n+\tbeq.w\t73b8 <__gridxc_alloc_MOD_realloc_r2+0x54c>\n+\tldrd\tr3, r2, [r7, #96]\t@ 0x60\n \tstr.w\tsp, [r7, #24]\n-\tldr.w\tr0, [r7, #152]\t@ 0x98\n+\tldr\tr0, [r7, #92]\t@ 0x5c\n \tsub.w\tip, r3, r0\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tldr\tr3, [r7, #104]\t@ 0x68\n \tsub.w\tr8, r3, r2\n \tldr.w\tr3, [fp]\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #68]\t@ 0x44\n \torrs.w\tr1, ip, r8\n \tldr.w\tr3, [fp, #4]\n-\tstr\tr3, [r7, #12]\n+\tstr\tr3, [r7, #20]\n \tadd.w\tr3, ip, #1\n-\tbmi.n\t7798 <__gridxc_alloc_MOD_realloc_r2+0x428>\n+\tbmi.n\t7238 <__gridxc_alloc_MOD_realloc_r2+0x3cc>\n \tmla\tr1, r8, r3, r3\n \tlsls\tr1, r1, #2\n \tadds\tr1, #7\n \tbic.w\tr4, r1, #4080\t@ 0xff0\n \tbic.w\tr1, r1, #7\n \tbic.w\tr4, r4, #15\n \tsub.w\tr4, sp, r4\n \tmov\tr5, sp\n \tcmp\tr5, r4\n-\tbeq.w\t79ce <__gridxc_alloc_MOD_realloc_r2+0x65e>\n+\tbeq.w\t7462 <__gridxc_alloc_MOD_realloc_r2+0x5f6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t7740 <__gridxc_alloc_MOD_realloc_r2+0x3d0>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x000003dc\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003de\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000252\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000246\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000178\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000010c\n- R_ARM_REL32\t.LC28\n-\t.word\t0x000000a0\n- R_ARM_REL32\t.bss\n+\tb.n\t7226 <__gridxc_alloc_MOD_realloc_r2+0x3ba>\n \tcmp.w\tr8, #0\n-\tblt.n\t784c <__gridxc_alloc_MOD_realloc_r2+0x4dc>\n+\tblt.n\t72ec <__gridxc_alloc_MOD_realloc_r2+0x480>\n \tldr.w\tr1, [fp, #24]\n-\tldr.w\tr9, [r7, #60]\t@ 0x3c\n+\tldr.w\tr9, [r7, #52]\t@ 0x34\n \tcmp.w\tip, #0\n-\tblt.n\t784c <__gridxc_alloc_MOD_realloc_r2+0x4dc>\n-\tldr\tr5, [r7, #16]\n+\tblt.n\t72ec <__gridxc_alloc_MOD_realloc_r2+0x480>\n+\tldr\tr5, [r7, #4]\n \tmov.w\tlr, #0\n-\tldr\tr4, [r7, #72]\t@ 0x48\n-\tstrd\tfp, r2, [r7, #4]\n+\tldr\tr4, [r7, #12]\n+\tstrd\tr0, r1, [r7, #12]\n \tmla\tr6, r2, r4, r5\n \tmul.w\tr4, sl, r4\n-\tstr\tr4, [r7, #72]\t@ 0x48\n-\tldr\tr4, [r7, #20]\n-\tldr.w\tfp, [r7, #72]\t@ 0x48\n-\tstrd\tr0, r1, [r7, #16]\n+\tstr\tr4, [r7, #64]\t@ 0x40\n+\tldr\tr4, [r7, #8]\n+\tstrd\tfp, r2, [r7, #4]\n+\tldr.w\tfp, [r7, #64]\t@ 0x40\n \tmla\tr6, r0, r4, r6\n \tmul.w\tr5, sl, r4\n-\tldr\tr4, [r7, #56]\t@ 0x38\n+\tldr\tr4, [r7, #48]\t@ 0x30\n \tmla\tr6, sl, r6, r4\n \tmov\tsl, lr\n \tadd.w\tr4, r9, lr, lsl #2\n \tmov\tr0, r6\n \tmovs\tr1, #0\n \tldr\tr2, [r0, #0]\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tadd\tr0, r5\n \tadd.w\tr1, r1, #1\n \tstr.w\tr2, [r4], #4\n-\tbne.n\t77e4 <__gridxc_alloc_MOD_realloc_r2+0x474>\n+\tbne.n\t7284 <__gridxc_alloc_MOD_realloc_r2+0x418>\n \tadd.w\tsl, sl, #1\n \tadd\tr6, fp\n \tadd\tlr, r3\n-\tcmp\tr8, sl\n-\tbge.n\t77dc <__gridxc_alloc_MOD_realloc_r2+0x46c>\n+\tcmp\tsl, r8\n+\tble.n\t727c <__gridxc_alloc_MOD_realloc_r2+0x410>\n \tldrd\tfp, r2, [r7, #4]\n-\tldr\tr5, [r7, #12]\n-\tldrd\tr0, r1, [r7, #16]\n+\tldr\tr5, [r7, #20]\n+\tldrd\tr0, r1, [r7, #12]\n \tldr.w\tr4, [fp, #36]\t@ 0x24\n \tldr.w\tsl, [fp, #20]\n-\tstr\tr4, [r7, #72]\t@ 0x48\n+\tstr\tr4, [r7, #64]\t@ 0x40\n \tmla\tr4, r2, r4, r5\n \tmovs\tr5, #0\n \tmla\tr4, r0, r1, r4\n \tmov\tr6, r5\n \tmul.w\tlr, sl, r1\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tadd.w\tfp, r9, r5, lsl #2\n \tmovs\tr1, #0\n \tmla\tr0, sl, r4, r2\n \tldr.w\tr2, [fp], #4\n-\tcmp\tr1, ip\n+\tcmp\tip, r1\n \tstr\tr2, [r0, #0]\n \tadd.w\tr1, r1, #1\n \tadd\tr0, lr\n-\tbne.n\t7830 <__gridxc_alloc_MOD_realloc_r2+0x4c0>\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tbne.n\t72d0 <__gridxc_alloc_MOD_realloc_r2+0x464>\n+\tldr\tr2, [r7, #64]\t@ 0x40\n \tadds\tr6, #1\n \tadd\tr5, r3\n-\tcmp\tr6, r8\n+\tcmp\tr8, r6\n \tadd\tr4, r2\n-\tble.n\t7824 <__gridxc_alloc_MOD_realloc_r2+0x4b4>\n+\tbge.n\t72c4 <__gridxc_alloc_MOD_realloc_r2+0x458>\n \tldr\tr2, [r7, #32]\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n \tmovs\tr4, #1\n-\tldr\tr5, [r7, #68]\t@ 0x44\n+\tldr\tr5, [r7, #56]\t@ 0x38\n \tsubs\tr3, r3, r2\n-\tldrd\tr2, r1, [r7, #44]\t@ 0x2c\n+\tldrd\tr2, r1, [r7, #36]\t@ 0x24\n \tadds\tr3, #1\n \tcmp\tr5, #0\n \tldr.w\tsp, [r7, #24]\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadd.w\tr2, r2, #1\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr2, [r7, #396]\t@ 0x18c\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr.w\tr2, [r7, #460]\t@ 0x1cc\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tstr.w\tr2, [r7, #396]\t@ 0x18c\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n \tcmp\tr2, #0\n \tit\teq\n \tmoveq\tr1, #0\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr1, [r7, #400]\t@ 0x190\n \tstr\tr1, [sp, #8]\n-\tldr\tr1, [pc, #384]\t@ (7a20 <__gridxc_alloc_MOD_realloc_r2+0x6b0>)\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tldr\tr1, [pc, #380]\t@ (74bc <__gridxc_alloc_MOD_realloc_r2+0x650>)\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n \tstr\tr3, [sp, #4]\n \tadd\tr1, pc\n \tmov\tr3, r2\n \tstr\tr4, [sp, #0]\n \tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tcbz\tr3, 78bc <__gridxc_alloc_MOD_realloc_r2+0x54c>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tcbz\tr3, 735c <__gridxc_alloc_MOD_realloc_r2+0x4f0>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n+\tldr\tr0, [pc, #352]\t@ (74c0 <__gridxc_alloc_MOD_realloc_r2+0x654>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #28]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #328]\t@ 0x148\n-\tvldr\td18, [pc, #320]\t@ 7a08 <__gridxc_alloc_MOD_realloc_r2+0x698>\n-\tvldr\td19, [pc, #324]\t@ 7a10 <__gridxc_alloc_MOD_realloc_r2+0x6a0>\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tldr\tr0, [pc, #336]\t@ (7a24 <__gridxc_alloc_MOD_realloc_r2+0x6b4>)\n-\tvldr\td17, [pc, #324]\t@ 7a18 <__gridxc_alloc_MOD_realloc_r2+0x6a8>\n \tadd\tr0, pc\n-\tldr\tr1, [r7, #68]\t@ 0x44\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstrd\tr5, r5, [r7, #296]\t@ 0x128\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldrd\tr1, r2, [r7, #56]\t@ 0x38\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #308]\t@ 0x134\n+\tstr.w\tr4, [r7, #324]\t@ 0x144\n+\tmovs\tr4, #2\n+\tstr.w\tr4, [r7, #316]\t@ 0x13c\n+\tstr.w\tr4, [r7, #328]\t@ 0x148\n+\tstr.w\tr4, [r7, #320]\t@ 0x140\n \tmovs\tr4, #4\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #336]\t@ 0x150\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n+\tstr.w\tr4, [r7, #292]\t@ 0x124\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstrh.w\tr4, [r7, #344]\t@ 0x158\n-\tmovs\tr4, #2\n-\tstr.w\tr4, [r7, #372]\t@ 0x174\n+\tstrh.w\tr4, [r7, #300]\t@ 0x12c\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #332]\t@ 0x14c\n-\tldr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tldrd\tr3, r2, [r7, #60]\t@ 0x3c\n+\tstr.w\tr4, [r7, #288]\t@ 0x120\n+\tldr.w\tr4, [r7, #400]\t@ 0x190\n+\tldr\tr3, [r7, #52]\t@ 0x34\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr4, [r7, #396]\t@ 0x18c\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #264]\t@ (7a28 <__gridxc_alloc_MOD_realloc_r2+0x6b8>)\n-\tldr\tr3, [pc, #268]\t@ (7a2c <__gridxc_alloc_MOD_realloc_r2+0x6bc>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #264]\t@ (74c4 <__gridxc_alloc_MOD_realloc_r2+0x658>)\n+\tldr\tr3, [pc, #228]\t@ (74a0 <__gridxc_alloc_MOD_realloc_r2+0x634>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n+\tldr.w\tr3, [r7, #332]\t@ 0x14c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t79f4 <__gridxc_alloc_MOD_realloc_r2+0x684>\n-\tadd.w\tr7, r7, #388\t@ 0x184\n+\tbne.n\t748a <__gridxc_alloc_MOD_realloc_r2+0x61e>\n+\tadd.w\tr7, r7, #340\t@ 0x154\n \tmov\tsp, r7\n-\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldrd\tr1, r0, [r7, #44]\t@ 0x2c\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldrd\tr1, r0, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #56]\t@ 0x38\n \tcmp\tr3, #0\n \tsub.w\tr3, r1, r0\n \tldr\tr0, [r7, #32]\n-\tadd.w\tr3, r3, #1\n-\tldr\tr1, [r7, #52]\t@ 0x34\n+\tadd\tr3, r5\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n \tbic.w\tr3, r3, r3, asr #31\n \tsub.w\tr2, r1, r0\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tadd.w\tr2, r2, #1\n-\tldr\tr1, [pc, #200]\t@ (7a30 <__gridxc_alloc_MOD_realloc_r2+0x6c0>)\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n-\tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr\tr5, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #396]\t@ 0x18c\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #64]\t@ 0x40\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tcmp\tr2, #0\n+\tldr\tr5, [r7, #60]\t@ 0x3c\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n+\tcmp\tr5, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #164]\t@ (74c8 <__gridxc_alloc_MOD_realloc_r2+0x65c>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tldr\tr2, [r7, #68]\t@ 0x44\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #56]\t@ 0x38\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tadd\tr1, pc\n+\tmov\tr3, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr\tr6, [r4, #16]\n-\tstr\tr6, [r7, #56]\t@ 0x38\n-\tb.n\t753c <__gridxc_alloc_MOD_realloc_r2+0x1cc>\n-\tmov.w\tip, #1\n+\tstr.w\tr8, [r6, #16]\n+\tstr.w\tr8, [r7, #48]\t@ 0x30\n+\tb.n\t701e <__gridxc_alloc_MOD_realloc_r2+0x1b2>\n+\tmovs\tr5, #1\n \tcmp.w\tlr, #0\n-\tstr.w\tip, [r7, #168]\t@ 0xa8\n+\tstr\tr5, [r7, #124]\t@ 0x7c\n \tmov.w\tlr, #0\n-\tbge.w\t741c <__gridxc_alloc_MOD_realloc_r2+0xac>\n+\tbge.w\t6f14 <__gridxc_alloc_MOD_realloc_r2+0xa8>\n \tmov.w\tr8, #0\n-\tb.n\t7424 <__gridxc_alloc_MOD_realloc_r2+0xb4>\n-\tmovs\tr2, #0\n-\tb.n\t75ba <__gridxc_alloc_MOD_realloc_r2+0x24a>\n-\tmov.w\tip, #1\n+\tb.n\t6f1a <__gridxc_alloc_MOD_realloc_r2+0xae>\n+\tmovs\tr5, #1\n \tmov.w\tr8, #0\n-\tb.n\t7424 <__gridxc_alloc_MOD_realloc_r2+0xb4>\n+\tb.n\t6f1a <__gridxc_alloc_MOD_realloc_r2+0xae>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbnz\tr1, 79e2 <__gridxc_alloc_MOD_realloc_r2+0x672>\n+\tcbnz\tr1, 7476 <__gridxc_alloc_MOD_realloc_r2+0x60a>\n \tldr.w\tr1, [fp, #24]\n \tadd.w\tr9, sp, #16\n-\tb.n\t77a6 <__gridxc_alloc_MOD_realloc_r2+0x436>\n+\tb.n\t7246 <__gridxc_alloc_MOD_realloc_r2+0x3da>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tb.n\t79d8 <__gridxc_alloc_MOD_realloc_r2+0x668>\n+\tb.n\t746c <__gridxc_alloc_MOD_realloc_r2+0x600>\n+\tmov\tr0, r6\n+\tcmp\tr6, #0\n+\tbeq.w\t70a0 <__gridxc_alloc_MOD_realloc_r2+0x234>\n \tmovs\tr0, #1\n-\tcmp\tr2, #0\n-\tbne.w\t75c8 <__gridxc_alloc_MOD_realloc_r2+0x258>\n-\tb.n\t75c0 <__gridxc_alloc_MOD_realloc_r2+0x250>\n+\tb.n\t70a6 <__gridxc_alloc_MOD_realloc_r2+0x23a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t75f4 <__gridxc_alloc_MOD_realloc_r2+0x284>\n+\tb.n\t70da <__gridxc_alloc_MOD_realloc_r2+0x26e>\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t75f4 <__gridxc_alloc_MOD_realloc_r2+0x284>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000178\n+\tb.n\t70da <__gridxc_alloc_MOD_realloc_r2+0x26e>\n+\tnop\n+\t.word\t0x00000608\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000005f2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000498\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000486\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000344\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x000002da\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000174\n R_ARM_REL32\t.LC28\n-\t.word\t0x0000014a\n+\t.word\t0x0000015a\n R_ARM_REL32\t.bss\n \t.word\t0x00000104\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000c2\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC28\n \n-00007a34 <__gridxc_alloc_MOD_realloc_r1>:\n+000074cc <__gridxc_alloc_MOD_realloc_r1>:\n __gridxc_alloc_MOD_realloc_r1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n-\tldr.w\tip, [pc, #892]\t@ 7dc8 <__gridxc_alloc_MOD_realloc_r1+0x394>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #892]\t@ (7dcc <__gridxc_alloc_MOD_realloc_r1+0x398>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tlr, [pc, #888]\t@ 7dd0 <__gridxc_alloc_MOD_realloc_r1+0x39c>\n+\tldr.w\tr0, [pc, #1096]\t@ 7928 <__gridxc_alloc_MOD_realloc_r1+0x45c>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1092]\t@ 792c <__gridxc_alloc_MOD_realloc_r1+0x460>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1084]\t@ 7930 <__gridxc_alloc_MOD_realloc_r1+0x464>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #328]\t@ 0x148\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #336]\t@ 0x150\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t7d6a <__gridxc_alloc_MOD_realloc_r1+0x336>\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldrd\tr3, r2, [r4, #28]\n-\tstr\tr3, [r7, #24]\n-\tstr\tr2, [r7, #16]\n-\tcmp\tr2, r3\n+\titet\teq\n+\tstreq\tr3, [r7, #16]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t7546 <__gridxc_alloc_MOD_realloc_r1+0x7a>\n+\tstr\tr3, [r7, #32]\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n-\tstr\tr3, [r7, #0]\n-\tldr\tr3, [r4, #24]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #16]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #752]\t@ 7da8 <__gridxc_alloc_MOD_realloc_r1+0x374>\n-\tvldr\td19, [pc, #756]\t@ 7db0 <__gridxc_alloc_MOD_realloc_r1+0x37c>\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #244\t@ 0xf4\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #100\t@ 0x64\n-\tvldr\td17, [pc, #744]\t@ 7db8 <__gridxc_alloc_MOD_realloc_r1+0x384>\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #92]\t@ 0x5c\n-\tadd.w\tsl, r7, #64\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #116\t@ 0x74\n-\tldr.w\tr9, [pc, #740]\t@ 7dd4 <__gridxc_alloc_MOD_realloc_r1+0x3a0>\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tadd.w\tr1, r7, #128\t@ 0x80\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #148\t@ 0x94\n-\tvstr\td16, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #220\t@ 0xdc\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #892]\t@ 7934 <__gridxc_alloc_MOD_realloc_r1+0x468>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n \tadd\tr9, pc\n-\tvstr\td16, [r7, #184]\t@ 0xb8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #164\t@ 0xa4\n-\tvstr\td16, [r7, #188]\t@ 0xbc\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #196\t@ 0xc4\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tstr\tr2, [r7, #32]\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #212\t@ 0xd4\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tvst1.32\t{d18-d19}, [fp]\n-\tstr\tr3, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #124]\t@ 0x7c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tadd.w\tr3, r7, #48\t@ 0x30\n-\tstr.w\tr8, [r7, #172]\t@ 0xac\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n-\tstr\tr3, [r7, #20]\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tadd.w\tr2, r7, #176\t@ 0xb0\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #80\t@ 0x50\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 7bf2 <__gridxc_alloc_MOD_realloc_r1+0x1be>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #8]\n-\tcmp\tr3, #0\n-\tbne.n\t7c2c <__gridxc_alloc_MOD_realloc_r1+0x1f8>\n-\tldr\tr2, [r7, #16]\n+\tcbz\tr3, 7670 <__gridxc_alloc_MOD_realloc_r1+0x1a4>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t76a6 <__gridxc_alloc_MOD_realloc_r1+0x1da>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #24]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #548]\t@ (7dd8 <__gridxc_alloc_MOD_realloc_r1+0x3a4>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #776]\t@ (7938 <__gridxc_alloc_MOD_realloc_r1+0x46c>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #8]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr3, [pc, #488]\t@ (7ddc <__gridxc_alloc_MOD_realloc_r1+0x3a8>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #712]\t@ (793c <__gridxc_alloc_MOD_realloc_r1+0x470>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 7c36 <__gridxc_alloc_MOD_realloc_r1+0x202>\n-\tldr\tr3, [pc, #484]\t@ (7de0 <__gridxc_alloc_MOD_realloc_r1+0x3ac>)\n+\tcbnz\tr3, 76b0 <__gridxc_alloc_MOD_realloc_r1+0x1e4>\n+\tldr\tr3, [pc, #708]\t@ (7940 <__gridxc_alloc_MOD_realloc_r1+0x474>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t7d6e <__gridxc_alloc_MOD_realloc_r1+0x33a>\n-\tldr\tr2, [pc, #476]\t@ (7de4 <__gridxc_alloc_MOD_realloc_r1+0x3b0>)\n-\tldr\tr3, [pc, #448]\t@ (7dcc <__gridxc_alloc_MOD_realloc_r1+0x398>)\n+\tbne.w\t77c8 <__gridxc_alloc_MOD_realloc_r1+0x2fc>\n+\tldr\tr2, [pc, #700]\t@ (7944 <__gridxc_alloc_MOD_realloc_r1+0x478>)\n+\tldr\tr3, [pc, #676]\t@ (792c <__gridxc_alloc_MOD_realloc_r1+0x460>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t7f16 <__gridxc_alloc_MOD_realloc_r1+0x4e2>\n-\tadd.w\tr7, r7, #284\t@ 0x11c\n+\tbne.w\t7916 <__gridxc_alloc_MOD_realloc_r1+0x44a>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t7d6e <__gridxc_alloc_MOD_realloc_r1+0x33a>\n-\tvldr\td8, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t77c8 <__gridxc_alloc_MOD_realloc_r1+0x2fc>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #4\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #769\t@ 0x301\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #1073741824\t@ 0x40000000\n-\tbge.w\t7f20 <__gridxc_alloc_MOD_realloc_r1+0x4ec>\n+\tbge.w\t7920 <__gridxc_alloc_MOD_realloc_r1+0x454>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #2\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t7f1a <__gridxc_alloc_MOD_realloc_r1+0x4e6>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #312]\t@ 7dc0 <__gridxc_alloc_MOD_realloc_r1+0x38c>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t791a <__gridxc_alloc_MOD_realloc_r1+0x44e>\n+\tmovs\tr3, #4\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #332]\t@ (7de8 <__gridxc_alloc_MOD_realloc_r1+0x3b4>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #28]\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #580]\t@ (7948 <__gridxc_alloc_MOD_realloc_r1+0x47c>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #272]\t@ 7db8 <__gridxc_alloc_MOD_realloc_r1+0x384>\n-\tvldr\td18, [pc, #252]\t@ 7da8 <__gridxc_alloc_MOD_realloc_r1+0x374>\n-\tvldr\td19, [pc, #256]\t@ 7db0 <__gridxc_alloc_MOD_realloc_r1+0x37c>\n-\tvstr\td17, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tr1, r5\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n \tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #240]\t@ 0xf0\n-\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n \tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #32]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #220]\t@ (7dec <__gridxc_alloc_MOD_realloc_r1+0x3b8>)\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #476]\t@ (794c <__gridxc_alloc_MOD_realloc_r1+0x480>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr.w\tip, [r4, #24]\n-\tldrd\tr0, r1, [r4, #28]\n-\tldrd\tr3, r2, [r4]\n-\tcmp\tr0, r1\n-\tbgt.w\t7bfa <__gridxc_alloc_MOD_realloc_r1+0x1c6>\n-\tadd\tr1, r8\n-\tmla\tr2, ip, r0, r2\n-\tsubs\tr1, r1, r0\n-\tldr\tr0, [r4, #20]\n-\tmla\tr3, r0, r2, r3\n-\tmovs\tr2, #0\n-\tmul.w\tr0, ip, r0\n-\tmov.w\tip, #0\n-\tadds\tr2, #1\n-\tstr.w\tip, [r3]\n-\tcmp\tr2, r1\n-\tadd\tr3, r0\n-\tbne.n\t7d5c <__gridxc_alloc_MOD_realloc_r1+0x328>\n-\tb.n\t7bfa <__gridxc_alloc_MOD_realloc_r1+0x1c6>\n-\tstr\tr3, [r7, #12]\n-\tb.n\t7ab0 <__gridxc_alloc_MOD_realloc_r1+0x7c>\n-\tldrd\tr9, r2, [r7, #56]\t@ 0x38\n-\tmov\tsl, sp\n+\tldrd\tr1, r2, [r4, #28]\n+\tldrd\tr3, r0, [r4]\n+\tcmp\tr1, r2\n+\tbgt.w\t7678 <__gridxc_alloc_MOD_realloc_r1+0x1ac>\n+\tadd\tr2, r9\n+\tmla\tr0, ip, r1, r0\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [r4, #20]\n+\tmla\tr3, r1, r0, r3\n+\tmovs\tr0, #0\n+\tmul.w\tr1, ip, r1\n+\tadd.w\tr8, r8, #1\n+\tstr\tr0, [r3, #0]\n+\tcmp\tr2, r8\n+\tadd\tr3, r1\n+\tbne.n\t77ba <__gridxc_alloc_MOD_realloc_r1+0x2ee>\n+\tb.n\t7678 <__gridxc_alloc_MOD_realloc_r1+0x1ac>\n+\tldrd\tr9, r2, [r7, #52]\t@ 0x34\n+\tmov\tfp, sp\n \tsubs.w\tr2, r2, r9\n-\tbmi.n\t7e58 <__gridxc_alloc_MOD_realloc_r1+0x424>\n+\tbmi.n\t7862 <__gridxc_alloc_MOD_realloc_r1+0x396>\n \tlsls\tr3, r2, #2\n \tldr\tr1, [r4, #0]\n \tadds\tr3, #11\n-\tstr\tr1, [r7, #8]\n+\tstr\tr1, [r7, #12]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tldr\tr0, [r4, #4]\n \tbic.w\tr1, r1, #15\n \tbic.w\tr3, r3, #7\n \tsub.w\tr1, sp, r1\n \tmov\tip, sp\n \tcmp\tip, r1\n-\tbeq.n\t7df0 <__gridxc_alloc_MOD_realloc_r1+0x3bc>\n+\tbeq.n\t77fe <__gridxc_alloc_MOD_realloc_r1+0x332>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t7d94 <__gridxc_alloc_MOD_realloc_r1+0x360>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000372\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000036a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ca\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000021e\n- R_ARM_REL32\t.LC28\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000140\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000d6\n- R_ARM_REL32\t.LC28\n+\tb.n\t77ee <__gridxc_alloc_MOD_realloc_r1+0x322>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 7e00 <__gridxc_alloc_MOD_realloc_r1+0x3cc>\n+\tcbz\tr3, 780e <__gridxc_alloc_MOD_realloc_r1+0x342>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldrd\tr1, r3, [r7]\n+\tldrd\tr1, r3, [r7, #4]\n \tmov.w\tlr, #0\n+\tldr.w\tsl, [r4, #24]\n \tmla\tip, r9, r3, r1\n-\tldr\tr1, [r7, #12]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr8, r1, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #32]\n \tmla\tip, r1, ip, r3\n-\tldr\tr1, [r4, #24]\n \tadd\tr3, sp, #16\n-\tstr\tr1, [r7, #12]\n \tmov\tr1, r3\n \tvldr\ts15, [ip]\n \tadd.w\tlr, lr, #1\n \tadd\tip, r8\n \tcmp\tlr, r2\n \tvstmia\tr1!, {s15}\n-\tble.n\t7e20 <__gridxc_alloc_MOD_realloc_r1+0x3ec>\n-\tldr\tr1, [r7, #12]\n-\tmla\tr0, r9, r1, r0\n+\tble.n\t782e <__gridxc_alloc_MOD_realloc_r1+0x362>\n \tldr\tr1, [r4, #20]\n-\tldr\tr4, [r7, #8]\n-\tmla\tr0, r1, r0, r4\n+\tmla\tr0, r9, sl, r0\n \tldr\tr4, [r7, #12]\n-\tmul.w\tip, r4, r1\n+\tmul.w\tip, sl, r1\n+\tmla\tr0, r1, r0, r4\n \tmovs\tr4, #0\n \tldr.w\tr1, [r3], #4\n-\tcmp\tr2, r4\n+\tcmp\tr4, r2\n \tstr\tr1, [r0, #0]\n \tadd.w\tr4, r4, #1\n \tadd\tr0, ip\n-\tbne.n\t7e48 <__gridxc_alloc_MOD_realloc_r1+0x414>\n-\tldr\tr2, [r7, #24]\n+\tbne.n\t7852 <__gridxc_alloc_MOD_realloc_r1+0x386>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #16]\n-\tmov\tsp, sl\n-\tldr\tr1, [pc, #220]\t@ (7f40 <__gridxc_alloc_MOD_realloc_r1+0x50c>)\n+\tldr\tr3, [r7, #20]\n+\tmov\tsp, fp\n+\tldr\tr1, [pc, #228]\t@ (7950 <__gridxc_alloc_MOD_realloc_r1+0x484>)\n \tmov.w\tr4, #1\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n \tadd\tr1, pc\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #344]\t@ 0x158\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r5\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tcbz\tr3, 7eb6 <__gridxc_alloc_MOD_realloc_r1+0x482>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 78c0 <__gridxc_alloc_MOD_realloc_r1+0x3f4>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #132]\t@ (7f44 <__gridxc_alloc_MOD_realloc_r1+0x510>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [pc, #144]\t@ (7954 <__gridxc_alloc_MOD_realloc_r1+0x488>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #28]\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #92]\t@ 7f28 <__gridxc_alloc_MOD_realloc_r1+0x4f4>\n-\tvldr\td19, [pc, #96]\t@ 7f30 <__gridxc_alloc_MOD_realloc_r1+0x4fc>\n-\tvldr\td17, [pc, #100]\t@ 7f38 <__gridxc_alloc_MOD_realloc_r1+0x504>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tstrh.w\tr4, [r7, #240]\t@ 0xf0\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #228]\t@ 0xe4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tldr\tr3, [r7, #32]\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t7c06 <__gridxc_alloc_MOD_realloc_r1+0x1d2>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t7684 <__gridxc_alloc_MOD_realloc_r1+0x1b8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t7c9a <__gridxc_alloc_MOD_realloc_r1+0x266>\n+\tb.n\t7700 <__gridxc_alloc_MOD_realloc_r1+0x234>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t7c9a <__gridxc_alloc_MOD_realloc_r1+0x266>\n+\tb.n\t7700 <__gridxc_alloc_MOD_realloc_r1+0x234>\n \tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000bc\n+\t.word\t0x0000043c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000042c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000370\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002fe\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000078\n+\t.word\t0x000002c6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002b8\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000238\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001d4\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x000000c2\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n \n-00007f48 <__gridxc_alloc_MOD_realloc_e1>:\n+00007958 <__gridxc_alloc_MOD_realloc_e1>:\n __gridxc_alloc_MOD_realloc_e1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n-\tldr.w\tip, [pc, #888]\t@ 82d8 <__gridxc_alloc_MOD_realloc_e1+0x390>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #888]\t@ (82dc <__gridxc_alloc_MOD_realloc_e1+0x394>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tlr, [pc, #884]\t@ 82e0 <__gridxc_alloc_MOD_realloc_e1+0x398>\n+\tldr.w\tr0, [pc, #1104]\t@ 7dbc <__gridxc_alloc_MOD_realloc_e1+0x464>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1100]\t@ 7dc0 <__gridxc_alloc_MOD_realloc_e1+0x468>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1092]\t@ 7dc4 <__gridxc_alloc_MOD_realloc_e1+0x46c>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #328]\t@ 0x148\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #336]\t@ 0x150\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t827c <__gridxc_alloc_MOD_realloc_e1+0x334>\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldrd\tr3, r2, [r4, #28]\n-\tstr\tr3, [r7, #24]\n-\tstr\tr2, [r7, #16]\n-\tcmp\tr2, r3\n+\titet\teq\n+\tstreq\tr3, [r7, #16]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t79d2 <__gridxc_alloc_MOD_realloc_e1+0x7a>\n+\tstr\tr3, [r7, #32]\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n-\tstr\tr3, [r7, #0]\n-\tldr\tr3, [r4, #24]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #16]\n \tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #748]\t@ 82b8 <__gridxc_alloc_MOD_realloc_e1+0x370>\n-\tvldr\td19, [pc, #752]\t@ 82c0 <__gridxc_alloc_MOD_realloc_e1+0x378>\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #244\t@ 0xf4\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #100\t@ 0x64\n-\tvldr\td17, [pc, #740]\t@ 82c8 <__gridxc_alloc_MOD_realloc_e1+0x380>\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #92]\t@ 0x5c\n-\tadd.w\tsl, r7, #64\t@ 0x40\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #116\t@ 0x74\n-\tldr.w\tr9, [pc, #736]\t@ 82e4 <__gridxc_alloc_MOD_realloc_e1+0x39c>\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tadd.w\tr1, r7, #128\t@ 0x80\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #148\t@ 0x94\n-\tvstr\td16, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #220\t@ 0xdc\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #900]\t@ 7dc8 <__gridxc_alloc_MOD_realloc_e1+0x470>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n \tadd\tr9, pc\n-\tvstr\td16, [r7, #184]\t@ 0xb8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #164\t@ 0xa4\n-\tvstr\td16, [r7, #188]\t@ 0xbc\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #196\t@ 0xc4\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tstr\tr2, [r7, #32]\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #212\t@ 0xd4\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #260\t@ 0x104\n-\tvst1.32\t{d18-d19}, [fp]\n-\tstr\tr3, [r7, #28]\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #124]\t@ 0x7c\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tadd.w\tr3, r7, #48\t@ 0x30\n-\tstr.w\tr8, [r7, #172]\t@ 0xac\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tadd.w\tr3, r7, #72\t@ 0x48\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n-\tstr\tr3, [r7, #20]\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tadd.w\tr2, r7, #176\t@ 0xb0\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #80\t@ 0x50\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 8106 <__gridxc_alloc_MOD_realloc_e1+0x1be>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #8]\n-\tcmp\tr3, #0\n-\tbne.n\t8140 <__gridxc_alloc_MOD_realloc_e1+0x1f8>\n-\tldr\tr2, [r7, #16]\n+\tcbz\tr3, 7afc <__gridxc_alloc_MOD_realloc_e1+0x1a4>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t7b32 <__gridxc_alloc_MOD_realloc_e1+0x1da>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #24]\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #544]\t@ (82e8 <__gridxc_alloc_MOD_realloc_e1+0x3a0>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #784]\t@ (7dcc <__gridxc_alloc_MOD_realloc_e1+0x474>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #8]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tldr\tr3, [pc, #484]\t@ (82ec <__gridxc_alloc_MOD_realloc_e1+0x3a4>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #720]\t@ (7dd0 <__gridxc_alloc_MOD_realloc_e1+0x478>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 814a <__gridxc_alloc_MOD_realloc_e1+0x202>\n-\tldr\tr3, [pc, #480]\t@ (82f0 <__gridxc_alloc_MOD_realloc_e1+0x3a8>)\n+\tcbnz\tr3, 7b3c <__gridxc_alloc_MOD_realloc_e1+0x1e4>\n+\tldr\tr3, [pc, #716]\t@ (7dd4 <__gridxc_alloc_MOD_realloc_e1+0x47c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t8280 <__gridxc_alloc_MOD_realloc_e1+0x338>\n-\tldr\tr2, [pc, #472]\t@ (82f4 <__gridxc_alloc_MOD_realloc_e1+0x3ac>)\n-\tldr\tr3, [pc, #444]\t@ (82dc <__gridxc_alloc_MOD_realloc_e1+0x394>)\n+\tbne.w\t7c5c <__gridxc_alloc_MOD_realloc_e1+0x304>\n+\tldr\tr2, [pc, #708]\t@ (7dd8 <__gridxc_alloc_MOD_realloc_e1+0x480>)\n+\tldr\tr3, [pc, #684]\t@ (7dc0 <__gridxc_alloc_MOD_realloc_e1+0x468>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t842a <__gridxc_alloc_MOD_realloc_e1+0x4e2>\n-\tadd.w\tr7, r7, #284\t@ 0x11c\n+\tbne.w\t7daa <__gridxc_alloc_MOD_realloc_e1+0x452>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t8280 <__gridxc_alloc_MOD_realloc_e1+0x338>\n-\tvldr\td8, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t7c5c <__gridxc_alloc_MOD_realloc_e1+0x304>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #8\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #257\t@ 0x101\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #536870912\t@ 0x20000000\n-\tbge.w\t8434 <__gridxc_alloc_MOD_realloc_e1+0x4ec>\n+\tbge.w\t7db4 <__gridxc_alloc_MOD_realloc_e1+0x45c>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #3\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t842e <__gridxc_alloc_MOD_realloc_e1+0x4e6>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #308]\t@ 82d0 <__gridxc_alloc_MOD_realloc_e1+0x388>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t7dae <__gridxc_alloc_MOD_realloc_e1+0x456>\n+\tmovs\tr3, #8\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #328]\t@ (82f8 <__gridxc_alloc_MOD_realloc_e1+0x3b0>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #28]\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #588]\t@ (7ddc <__gridxc_alloc_MOD_realloc_e1+0x484>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #268]\t@ 82c8 <__gridxc_alloc_MOD_realloc_e1+0x380>\n-\tvldr\td18, [pc, #248]\t@ 82b8 <__gridxc_alloc_MOD_realloc_e1+0x370>\n-\tvldr\td19, [pc, #252]\t@ 82c0 <__gridxc_alloc_MOD_realloc_e1+0x378>\n-\tvstr\td17, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #224]\t@ 0xe0\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n-\tmov\tr1, r5\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n \tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #240]\t@ 0xf0\n-\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r0, #16]!\n+\tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n \tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #32]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #216]\t@ (82fc <__gridxc_alloc_MOD_realloc_e1+0x3b4>)\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #484]\t@ (7de0 <__gridxc_alloc_MOD_realloc_e1+0x488>)\n \tldrd\tr2, r3, [r4, #28]\n \tadd\tr1, pc\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr2, [r4, #24]\n-\tldrd\tr0, r1, [r4, #28]\n-\tldrd\tr3, ip, [r4]\n-\tcmp\tr0, r1\n-\tbgt.w\t810e <__gridxc_alloc_MOD_realloc_e1+0x1c6>\n-\tadd\tr1, r8\n-\tmla\tip, r2, r0, ip\n-\tsubs\tr1, r1, r0\n-\tldr\tr0, [r4, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmla\tr3, r0, ip, r3\n-\tmul.w\tr0, r2, r0\n-\tmovs\tr2, #0\n-\tadds\tr2, #1\n-\tvstr\td16, [r3]\n-\tcmp\tr2, r1\n-\tadd\tr3, r0\n-\tbne.n\t826e <__gridxc_alloc_MOD_realloc_e1+0x326>\n-\tb.n\t810e <__gridxc_alloc_MOD_realloc_e1+0x1c6>\n-\tstr\tr3, [r7, #12]\n-\tb.n\t7fc4 <__gridxc_alloc_MOD_realloc_e1+0x7c>\n-\tldrd\tr9, r2, [r7, #56]\t@ 0x38\n-\tmov\tsl, sp\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr.w\tip, [r4, #24]\n+\tldrd\tr1, r2, [r4, #28]\n+\tldrd\tr3, r0, [r4]\n+\tcmp\tr1, r2\n+\tbgt.w\t7b04 <__gridxc_alloc_MOD_realloc_e1+0x1ac>\n+\tadd\tr2, r9\n+\tmla\tr0, ip, r1, r0\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [r4, #20]\n+\tmov.w\tsl, #0\n+\tmov.w\tfp, #0\n+\tmla\tr3, r1, r0, r3\n+\tmul.w\tr1, ip, r1\n+\tadd.w\tr8, r8, #1\n+\tstrd\tsl, fp, [r3]\n+\tcmp\tr2, r8\n+\tadd\tr3, r1\n+\tbne.n\t7c4c <__gridxc_alloc_MOD_realloc_e1+0x2f4>\n+\tb.n\t7b04 <__gridxc_alloc_MOD_realloc_e1+0x1ac>\n+\tldrd\tr9, r2, [r7, #52]\t@ 0x34\n+\tmov\tfp, sp\n \tsubs.w\tr2, r2, r9\n-\tbmi.n\t836c <__gridxc_alloc_MOD_realloc_e1+0x424>\n+\tbmi.n\t7cf6 <__gridxc_alloc_MOD_realloc_e1+0x39e>\n \tlsls\tr3, r2, #3\n \tldr\tr1, [r4, #0]\n \tadds\tr3, #8\n-\tstr\tr1, [r7, #8]\n+\tstr\tr1, [r7, #12]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tldr\tr0, [r4, #4]\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tip, sp\n \tcmp\tip, r1\n-\tbeq.n\t8300 <__gridxc_alloc_MOD_realloc_e1+0x3b8>\n+\tbeq.n\t7c8e <__gridxc_alloc_MOD_realloc_e1+0x336>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t82a2 <__gridxc_alloc_MOD_realloc_e1+0x35a>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x0000036e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000366\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002c6\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000021a\n- R_ARM_REL32\t.LC29\n-\t.word\t0x000001e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001dc\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d2\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000013c\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000d2\n- R_ARM_REL32\t.LC29\n+\tb.n\t7c7e <__gridxc_alloc_MOD_realloc_e1+0x326>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 8310 <__gridxc_alloc_MOD_realloc_e1+0x3c8>\n+\tcbz\tr3, 7c9e <__gridxc_alloc_MOD_realloc_e1+0x346>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldrd\tr1, r3, [r7]\n+\tldrd\tr1, r3, [r7, #4]\n \tmov.w\tlr, #0\n+\tldr.w\tsl, [r4, #24]\n \tmla\tip, r9, r3, r1\n-\tldr\tr1, [r7, #12]\n+\tldr\tr1, [r7, #16]\n \tmul.w\tr8, r1, r3\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #32]\n \tmla\tip, r1, ip, r3\n-\tldr\tr1, [r4, #24]\n \tadd\tr3, sp, #8\n-\tstr\tr1, [r7, #12]\n \tmov\tr1, r3\n-\tvldr\td16, [ip]\n+\tvldr\td7, [ip]\n \tadd.w\tlr, lr, #1\n \tadds\tr1, #8\n \tadd\tip, r8\n \tcmp\tlr, r2\n-\tvstr\td16, [r1]\n-\tble.n\t8330 <__gridxc_alloc_MOD_realloc_e1+0x3e8>\n-\tldr\tr1, [r7, #12]\n-\tmla\tr0, r9, r1, r0\n+\tvstr\td7, [r1]\n+\tble.n\t7cbe <__gridxc_alloc_MOD_realloc_e1+0x366>\n \tldr\tr1, [r4, #20]\n-\tldr\tr4, [r7, #8]\n-\tmla\tr0, r1, r0, r4\n+\tmla\tr0, r9, sl, r0\n \tldr\tr4, [r7, #12]\n-\tmul.w\tip, r4, r1\n+\tmul.w\tip, sl, r1\n+\tmla\tr0, r1, r0, r4\n \tmovs\tr4, #0\n \tldrd\tr8, r9, [r3, #8]!\n-\tcmp\tr2, r4\n+\tcmp\tr4, r2\n \tstrd\tr8, r9, [r0]\n \tadd.w\tr4, r4, #1\n \tadd\tr0, ip\n-\tbne.n\t835a <__gridxc_alloc_MOD_realloc_e1+0x412>\n-\tldr\tr2, [r7, #24]\n+\tbne.n\t7ce4 <__gridxc_alloc_MOD_realloc_e1+0x38c>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #16]\n-\tmov\tsp, sl\n-\tldr\tr1, [pc, #224]\t@ (8458 <__gridxc_alloc_MOD_realloc_e1+0x510>)\n+\tldr\tr3, [r7, #20]\n+\tmov\tsp, fp\n+\tldr\tr1, [pc, #228]\t@ (7de4 <__gridxc_alloc_MOD_realloc_e1+0x48c>)\n \tmov.w\tr4, #1\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n \tadd\tr1, pc\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #344]\t@ 0x158\n-\tadd.w\tr0, r7, #44\t@ 0x2c\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r5\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tcbz\tr3, 83ca <__gridxc_alloc_MOD_realloc_e1+0x482>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 7d54 <__gridxc_alloc_MOD_realloc_e1+0x3fc>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #136]\t@ (845c <__gridxc_alloc_MOD_realloc_e1+0x514>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [pc, #144]\t@ (7de8 <__gridxc_alloc_MOD_realloc_e1+0x490>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #28]\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #96]\t@ 8440 <__gridxc_alloc_MOD_realloc_e1+0x4f8>\n-\tvldr\td19, [pc, #100]\t@ 8448 <__gridxc_alloc_MOD_realloc_e1+0x500>\n-\tvldr\td17, [pc, #104]\t@ 8450 <__gridxc_alloc_MOD_realloc_e1+0x508>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #232]\t@ 0xe8\n+\tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #236]\t@ 0xec\n-\tstrh.w\tr4, [r7, #240]\t@ 0xf0\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #228]\t@ 0xe4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tldr\tr3, [r7, #32]\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t811a <__gridxc_alloc_MOD_realloc_e1+0x1d2>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t7b10 <__gridxc_alloc_MOD_realloc_e1+0x1b8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t81ae <__gridxc_alloc_MOD_realloc_e1+0x266>\n+\tb.n\t7b8c <__gridxc_alloc_MOD_realloc_e1+0x234>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t81ae <__gridxc_alloc_MOD_realloc_e1+0x266>\n+\tb.n\t7b8c <__gridxc_alloc_MOD_realloc_e1+0x234>\n \tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000c0\n+\t.word\t0x00000444\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000434\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000378\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000306\n R_ARM_REL32\t.LC29\n-\t.word\t0x0000007c\n+\t.word\t0x000002ce\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000240\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001dc\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x000000c2\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n \n-00008460 <__gridxc_alloc_MOD_realloc_i3>:\n+00007dec <__gridxc_alloc_MOD_realloc_i3>:\n __gridxc_alloc_MOD_realloc_i3():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3504]\t@ 0xdb0\n-\tmov\tr8, r2\n-\tldr.w\tr2, [pc, #1072]\t@ 88a8 <__gridxc_alloc_MOD_realloc_i3+0x448>\n+\tstr.w\tr0, [ip, #3592]\t@ 0xe08\n+\tmov\tfp, r2\n+\tldr.w\tr2, [pc, #1944]\t@ 8598 <__gridxc_alloc_MOD_realloc_i3+0x7ac>\n \tmov\tip, r3\n-\tldr.w\tr3, [pc, #1068]\t@ 88ac <__gridxc_alloc_MOD_realloc_i3+0x44c>\n+\tldr.w\tr3, [pc, #1940]\t@ 859c <__gridxc_alloc_MOD_realloc_i3+0x7b0>\n \tadd\tr2, pc\n-\tsub.w\tsp, sp, #524\t@ 0x20c\n+\tsub\tsp, #468\t@ 0x1d4\n \tadd\tr7, sp, #16\n-\tmov\tlr, r1\n+\tmov\tr8, r1\n \tmov\tr4, r0\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [pc, #1056]\t@ 88b0 <__gridxc_alloc_MOD_realloc_i3+0x450>\n+\tldr.w\tr2, [pc, #1928]\t@ 85a0 <__gridxc_alloc_MOD_realloc_i3+0x7b4>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tstr.w\tr3, [r7, #444]\t@ 0x1bc\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #0]\n \tadd\tr2, pc\n-\tldrd\tfp, r1, [r7, #584]\t@ 0x248\n+\tldr.w\tsl, [r7, #496]\t@ 0x1f0\n \tcmp\tr3, #0\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tmov.w\tr1, #1\n-\tit\teq\n+\tite\tne\n+\tmovne\tr1, #1\n \tmoveq\tr1, #0\n \tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tstr\tr2, [r7, #32]\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tstr\tr2, [r7, #88]\t@ 0x58\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tldrd\tr9, sl, [r7, #576]\t@ 0x240\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tstr\tr2, [r7, #28]\n+\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tstr\tr2, [r7, #40]\t@ 0x28\n+\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n \tstr\tr2, [r7, #84]\t@ 0x54\n-\tbeq.w\t8ae4 <__gridxc_alloc_MOD_realloc_i3+0x684>\n+\tldr.w\tr2, [r7, #512]\t@ 0x200\n+\tldrd\tr9, lr, [r7, #488]\t@ 0x1e8\n+\tstr\tr2, [r7, #80]\t@ 0x50\n+\tbeq.w\t8430 <__gridxc_alloc_MOD_realloc_i3+0x644>\n \tmov\tr6, r0\n-\tstr\tr3, [r7, #28]\n+\tstr\tr3, [r7, #24]\n \tldr\tr3, [r0, #4]\n-\tadd.w\tr5, r7, #440\t@ 0x1b8\n-\tstr\tr3, [r7, #52]\t@ 0x34\n+\tadd.w\tr5, r7, #384\t@ 0x180\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r0, #24]\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tstr\tr3, [r7, #48]\t@ 0x30\n+\tstr\tr3, [r7, #16]\n+\tadd.w\tr3, r7, #168\t@ 0xa8\n+\tstr\tr3, [r7, #32]\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tr6, {r0, r1, r2}\n \tstmia.w\tr5, {r0, r1, r2}\n \tldr\tr2, [r4, #20]\n-\tldrd\tr0, r1, [r7, #468]\t@ 0x1d4\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tldr\tr5, [r7, #48]\t@ 0x30\n-\tldrd\tr3, r2, [r7, #480]\t@ 0x1e0\n+\tldrd\tr0, r1, [r7, #412]\t@ 0x19c\n+\tstr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr5, [r7, #32]\n+\tldrd\tr3, r2, [r7, #424]\t@ 0x1a8\n \tsubs\tr6, r1, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tstr\tr0, [r5, #0]\n \tsubs\tr0, r2, r3\n-\tstr\tr0, [r7, #92]\t@ 0x5c\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n \tit\tmi\n \tmovmi\tr3, #1\n \tstr\tr3, [r5, #8]\n-\tldrd\tr0, r3, [r7, #492]\t@ 0x1ec\n+\tldrd\tr0, r3, [r7, #436]\t@ 0x1b4\n \tsubs\tr5, r3, r0\n \tit\tmi\n \tmovmi\tr0, #1\n \tcmp\tr6, #0\n-\tldr\tr6, [r7, #48]\t@ 0x30\n+\tldr\tr6, [r7, #32]\n \tit\tlt\n \tmovlt\tr1, #0\n \tstr\tr0, [r6, #16]\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n \tstr\tr1, [r6, #4]\n \tcmp\tr0, #0\n \tit\tlt\n \tmovlt\tr2, #0\n \tcmp\tr5, #0\n \tit\tlt\n \tmovlt\tr3, #0\n \tstr\tr2, [r6, #12]\n \tstr\tr3, [r6, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr3, [sl]\n-\tvldr\td18, [pc, #832]\t@ 8888 <__gridxc_alloc_MOD_realloc_i3+0x428>\n-\tvldr\td19, [pc, #836]\t@ 8890 <__gridxc_alloc_MOD_realloc_i3+0x430>\n-\tstr.w\tr3, [r7, #168]\t@ 0xa8\n-\tldr.w\tr2, [ip]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tldr.w\tr0, [lr]\n-\tadd.w\tsl, r7, #200\t@ 0xc8\n-\tldr.w\tr1, [r8]\n-\tldr.w\tr5, [r9]\n-\tldr.w\tr6, [fp]\n-\tstrd\tr0, r1, [r7, #128]\t@ 0x80\n-\tadd.w\tr0, r7, #392\t@ 0x188\n-\tstrd\tr2, r5, [r7, #136]\t@ 0x88\n-\tmov\tr5, r0\n-\tvldr\td17, [pc, #792]\t@ 8898 <__gridxc_alloc_MOD_realloc_i3+0x438>\n-\tadd.w\tr2, r7, #152\t@ 0x98\n-\tvldr\td20, [r7, #128]\t@ 0x80\n-\tvldr\td21, [r7, #136]\t@ 0x88\n-\tvstr\td16, [r7, #256]\t@ 0x100\n-\tvstr\td16, [r7, #260]\t@ 0x104\n-\tadd.w\tr1, r7, #428\t@ 0x1ac\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #284\t@ 0x11c\n-\tldr.w\tr8, [pc, #784]\t@ 88b4 <__gridxc_alloc_MOD_realloc_i3+0x454>\n-\tvstr\td16, [r7, #304]\t@ 0x130\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #316\t@ 0x13c\n-\tvstr\td16, [r7, #308]\t@ 0x134\n-\tadd\tr8, pc\n-\tstr\tr0, [r7, #24]\n-\tadd.w\tr0, r7, #248\t@ 0xf8\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #332\t@ 0x14c\n-\tstr\tr1, [r7, #40]\t@ 0x28\n-\tadd.w\tr1, r7, #380\t@ 0x17c\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #364\t@ 0x16c\n-\tstr\tr6, [r2, #20]\n-\tadd.w\tr6, r7, #176\t@ 0xb0\n-\tvstr\td16, [r7, #352]\t@ 0x160\n-\tstr\tr2, [r7, #92]\t@ 0x5c\n-\tmovs\tr2, #3\n-\tvstr\td16, [r7, #356]\t@ 0x164\n-\tstr\tr2, [r0, #44]\t@ 0x2c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #412\t@ 0x19c\n-\tstr.w\tr2, [r7, #340]\t@ 0x154\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tmvn.w\tr3, #2\n-\tstr.w\tr2, [r7, #388]\t@ 0x184\n-\tvstr\td20, [r7, #152]\t@ 0x98\n-\tvstr\td21, [r7, #160]\t@ 0xa0\n-\tstr\tr3, [r0, #4]\n-\tstr.w\tr2, [r7, #436]\t@ 0x1b4\n-\tldr\tr2, [r7, #48]\t@ 0x30\n-\tstrd\tr2, r3, [r7, #344]\t@ 0x158\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tvst1.32\t{d17}, [r1]\n-\tldr\tr1, [r7, #40]\t@ 0x28\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tstr.w\tr3, [r7, #300]\t@ 0x12c\n-\tldr\tr3, [r7, #92]\t@ 0x5c\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tmov\tr3, r5\n-\tvstr\td16, [r7, #400]\t@ 0x190\n-\tvstr\td16, [r7, #404]\t@ 0x194\n-\tvst1.32\t{d18-d19}, [r2]\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tvst1.32\t{d17}, [r1]\n-\tadd.w\tr1, r7, #296\t@ 0x128\n-\tstr\tr6, [r0, #0]\n-\tstr.w\tsl, [r7, #296]\t@ 0x128\n+\tadd.w\tr6, r7, #144\t@ 0x90\n+\tldr.w\tr0, [r8]\n+\tldr.w\tr1, [ip]\n+\tadd.w\tr8, r7, #96\t@ 0x60\n+\tldr.w\tr2, [lr]\n+\tmov.w\tlr, #4\n+\tstr\tr0, [r6, #0]\n+\tadd.w\tr0, r7, #192\t@ 0xc0\n+\tldr.w\tr3, [r9]\n+\tmvn.w\tr9, #2\n+\tldr.w\tr5, [sl]\n+\tadd.w\tsl, r7, #120\t@ 0x78\n+\tldr.w\tip, [fp]\n+\tstr.w\tr9, [r0, #4]\n+\tstr\tr1, [r6, #8]\n+\tstr\tr2, [r6, #16]\n+\tmovs\tr2, #2\n+\tstr.w\tip, [r6, #4]\n+\tmov.w\tip, #3\n+\tstrd\tr2, r2, [r0, #32]\n+\tstr\tr3, [r6, #12]\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tstr\tr5, [r6, #20]\n+\tmovs\tr5, #1\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tmovs\tr3, #0\n+\tstrd\tr5, r5, [r0, #24]\n+\tstrd\tr3, r3, [r7, #200]\t@ 0xc8\n+\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tstrd\tr3, r3, [r7, #248]\t@ 0xf8\n+\tstr.w\tr3, [r7, #256]\t@ 0x100\n+\tstr\tr5, [r0, #40]\t@ 0x28\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n+\tstr.w\tlr, [r7, #260]\t@ 0x104\n+\tstr.w\tip, [r0, #44]\t@ 0x2c\n+\tstr.w\tlr, [r0, #20]\n+\tstrd\tr5, r5, [r7, #264]\t@ 0x108\n+\tstr.w\tr5, [r7, #280]\t@ 0x118\n+\tstr.w\tr8, [r0]\n+\tldr\tr1, [r7, #32]\n+\tstrd\tr1, r9, [r7, #288]\t@ 0x120\n+\tadd.w\tr1, r7, #240\t@ 0xf0\n+\tstrd\tr9, r3, [r7, #340]\t@ 0x154\n+\tstr.w\tr9, [r7, #244]\t@ 0xf4\n+\tldr.w\tr9, [pc, #1600]\t@ 85a4 <__gridxc_alloc_MOD_realloc_i3+0x7b8>\n+\tstr.w\tr2, [r7, #276]\t@ 0x114\n+\tstrd\tr5, r2, [r7, #316]\t@ 0x13c\n+\tadd\tr9, pc\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n+\tstrd\tr5, r2, [r7, #364]\t@ 0x16c\n+\tstr.w\tr2, [r7, #372]\t@ 0x174\n+\tldr\tr2, [r7, #80]\t@ 0x50\n+\tstr.w\tip, [r7, #284]\t@ 0x11c\n+\tstr.w\tlr, [r7, #308]\t@ 0x134\n+\tstr.w\tlr, [r7, #356]\t@ 0x164\n+\tstrd\tr3, r3, [r7, #296]\t@ 0x128\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tstrd\tr5, ip, [r7, #328]\t@ 0x148\n+\tstr.w\tip, [r7, #380]\t@ 0x17c\n+\tstrd\tr3, r3, [r7, #348]\t@ 0x15c\n+\tstr.w\tr5, [r7, #312]\t@ 0x138\n+\tstr.w\tr5, [r7, #360]\t@ 0x168\n+\tstr.w\tr5, [r7, #376]\t@ 0x178\n+\tstr.w\tr6, [r7, #336]\t@ 0x150\n+\tstr.w\tsl, [r7, #240]\t@ 0xf0\n \tstr\tr2, [sp, #4]\n-\tldr\tr2, [r7, #88]\t@ 0x58\n+\tldr\tr2, [r7, #84]\t@ 0x54\n \tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #344\t@ 0x158\n+\tadd.w\tr2, r7, #288\t@ 0x120\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tbl\t3cc <__gridxc_alloc_MOD_options.constprop.2>\n-\tldr.w\tr3, [r8, #8]\n-\tcbz\tr3, 8664 <__gridxc_alloc_MOD_realloc_i3+0x204>\n-\tldr.w\tr9, [r8, #12]\n-\tcmp.w\tr9, #0\n-\tbeq.w\t8aee <__gridxc_alloc_MOD_realloc_i3+0x68e>\n-\tldr\tr3, [pc, #592]\t@ (88b8 <__gridxc_alloc_MOD_realloc_i3+0x458>)\n+\tldr.w\tr3, [r9, #8]\n+\tcbz\tr3, 7fd2 <__gridxc_alloc_MOD_realloc_i3+0x1e6>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbeq.w\t843a <__gridxc_alloc_MOD_realloc_i3+0x64e>\n+\tldr.w\tr3, [pc, #1492]\t@ 85a8 <__gridxc_alloc_MOD_realloc_i3+0x7bc>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t88c8 <__gridxc_alloc_MOD_realloc_i3+0x468>\n-\tldrd\tr1, r3, [r6]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tip, r9, [r6, #8]\n-\tsub.w\tfp, r3, r1\n-\tsub.w\tr2, r9, ip\n-\torr.w\tr0, fp, fp, asr #31\n-\tvstr\td16, [r4, #12]\n-\tadds\tr0, #1\n-\tstr\tr3, [r7, #116]\t@ 0x74\n-\tmovs\tr3, #4\n-\tstr\tr1, [r7, #112]\t@ 0x70\n-\tstr.w\tip, [r7, #124]\t@ 0x7c\n-\tstr\tr0, [r7, #120]\t@ 0x78\n-\tstr\tr2, [r7, #88]\t@ 0x58\n-\torr.w\tr2, r2, r2, asr #31\n-\tvldr\td10, [r7, #112]\t@ 0x70\n-\tvldr\td11, [r7, #120]\t@ 0x78\n-\tadds\tr2, #1\n+\tbeq.w\t821e <__gridxc_alloc_MOD_realloc_i3+0x432>\n+\tldr.w\tr2, [r8, #4]\n+\tldr.w\tr5, [r8, #8]\n+\tldr.w\tr1, [r8]\n+\tldr.w\tr0, [r8, #12]\n+\tstr\tr1, [r7, #84]\t@ 0x54\n+\tsubs\tr1, r2, r1\n+\tstr\tr0, [r7, #60]\t@ 0x3c\n+\tsubs\tr0, r0, r5\n+\torr.w\tr3, r1, r1, asr #31\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\torr.w\tfp, r0, r0, asr #31\n+\tmovs\tr2, #0\n+\tstr\tr5, [r7, #80]\t@ 0x50\n+\tadds.w\tfp, fp, #1\n+\tadd.w\tr5, r3, #1\n+\tstrd\tr2, r2, [r4, #12]\n+\tmov.w\tr3, #4\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tstr\tr3, [r4, #8]\n \tmovw\tr3, #259\t@ 0x103\n+\tstr\tr0, [r7, #56]\t@ 0x38\n \tstrh\tr3, [r4, #16]\n-\tbeq.w\t8c2a <__gridxc_alloc_MOD_realloc_i3+0x7ca>\n-\tmvn.w\tr8, #2147483648\t@ 0x80000000\n-\tudiv\tr8, r8, r2\n-\tcmp\tr8, r0\n-\tit\tge\n-\tmovge\tr3, #0\n-\tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr8, r3\n-\tldrd\tlr, r3, [r6, #16]\n-\tmul.w\tr2, r0, r2\n-\tstrd\tr9, r2, [r7, #96]\t@ 0x60\n-\tsub.w\tr9, r3, lr\n-\tstrd\tlr, r3, [r7, #104]\t@ 0x68\n-\torr.w\tr3, r9, r9, asr #31\n-\tvldr\td8, [r7, #96]\t@ 0x60\n-\tvldr\td9, [r7, #104]\t@ 0x68\n-\tadds\tr3, #1\n-\tbeq.n\t870c <__gridxc_alloc_MOD_realloc_i3+0x2ac>\n-\tmvn.w\tr6, #2147483648\t@ 0x80000000\n-\tmov\tr5, r8\n-\tudiv\tr6, r6, r3\n-\tmul.w\tr3, r2, r3\n-\tcmp\tr6, r2\n+\tbeq.w\t8584 <__gridxc_alloc_MOD_realloc_i3+0x798>\n+\tmov\tr1, fp\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, r5\n+\tite\tge\n+\tmovge.w\tr9, #0\n+\tmovlt.w\tr9, #1\n+\tldr.w\tr3, [r8, #20]\n+\tmul.w\tfp, fp, r5\n+\tldr.w\tr2, [r8, #16]\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tsubs\tr3, r3, r2\n+\tstr\tr2, [r7, #76]\t@ 0x4c\n+\torr.w\tr8, r3, r3, asr #31\n+\tadds.w\tr8, r8, #1\n+\tbeq.n\t807c <__gridxc_alloc_MOD_realloc_i3+0x290>\n+\tmov\tr1, r8\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr8, r8, fp\n+\tstr\tr3, [r7, #48]\t@ 0x30\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tcmp\tr0, fp\n \tit\tlt\n-\taddlt\tr5, #1\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n+\taddlt.w\tr9, r9, #1\n+\tcmp.w\tr8, #1073741824\t@ 0x40000000\n \tit\tge\n-\taddge\tr5, #1\n-\tmov\tr8, r5\n-\tldr\tr5, [r7, #88]\t@ 0x58\n-\tnegs\tr1, r1\n-\torr.w\tr6, fp, r5\n-\torrs.w\tr6, r6, r9\n-\tmls\tr1, r0, ip, r1\n-\tmls\tfp, r2, lr, r1\n-\tit\tpl\n-\tlslpl\tr3, r3, #2\n-\tit\tmi\n-\tmovmi\tr3, #0\n-\tcmp.w\tr8, #0\n-\tbne.w\t8c32 <__gridxc_alloc_MOD_realloc_i3+0x7d2>\n-\tcmp\tr3, #1\n+\taddge.w\tr9, r9, #1\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\torrs\tr1, r2\n+\tldr\tr2, [r7, #84]\t@ 0x54\n+\torrs\tr1, r3\n+\trsb\tr2, r2, #0\n+\tmls\tr2, r5, r0, r2\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n+\tmls\tr2, fp, r0, r2\n+\tite\tpl\n+\tmovpl.w\tr0, r8, lsl #2\n+\tmovmi\tr0, #0\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tcmp.w\tr9, #0\n+\tbne.w\t858c <__gridxc_alloc_MOD_realloc_i3+0x7a0>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr3, #1\n-\tmov\tr0, r3\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t8c38 <__gridxc_alloc_MOD_realloc_i3+0x7d8>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #340]\t@ 88a0 <__gridxc_alloc_MOD_realloc_i3+0x440>\n-\tvst1.32\t{d10-d11}, [r3]\n-\tadd.w\tr3, r4, #44\t@ 0x2c\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tfp, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r7, #92]\t@ 0x5c\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tvldr\td18, [pc, #280]\t@ 8888 <__gridxc_alloc_MOD_realloc_i3+0x428>\n-\tvldr\td19, [pc, #284]\t@ 8890 <__gridxc_alloc_MOD_realloc_i3+0x430>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [pc, #320]\t@ (88bc <__gridxc_alloc_MOD_realloc_i3+0x45c>)\n-\tvstr\td17, [r7, #404]\t@ 0x194\n-\tldr\tr1, [r7, #36]\t@ 0x24\n+\tbeq.w\t8592 <__gridxc_alloc_MOD_realloc_i3+0x7a6>\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tmov.w\tlr, #1\n+\tstr\tr3, [r4, #28]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r4, #32]\n+\tldr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r4, #40]\t@ 0x28\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr3, [r4, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tstr\tr3, [r4, #52]\t@ 0x34\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r4, #56]\t@ 0x38\n+\tmovs\tr3, #4\n+\tstr\tr5, [r4, #36]\t@ 0x24\n+\tstr.w\tfp, [r4, #48]\t@ 0x30\n+\tstr\tr2, [r4, #4]\n+\tstrd\tr3, lr, [r4, #20]\n+\tldr.w\tr0, [pc, #1220]\t@ 85ac <__gridxc_alloc_MOD_realloc_i3+0x7c0>\n+\tmovs\tr5, #0\n+\tldr\tr1, [r7, #28]\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tvldr\td16, [pc, #268]\t@ 8898 <__gridxc_alloc_MOD_realloc_i3+0x438>\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr\tr2, [r7, #40]\t@ 0x28\n \tcmp\tr1, #0\n-\tldr\tr2, [r7, #32]\n-\tldr.w\tr6, [r7, #604]\t@ 0x25c\n+\tstr.w\tr6, [r7, #336]\t@ 0x150\n+\tmov.w\tr6, #1\n+\tstr.w\tr9, [r0, #16]!\n+\tit\tne\n+\tmovne\tr9, r3\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #356]\t@ 0x164\n+\tstr.w\tr3, [r7, #344]\t@ 0x158\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #368]\t@ 0x170\n \tit\teq\n-\tmoveq\tr6, #0\n-\tvst1.32\t{d16}, [r3]\n-\tmovs\tr3, #4\n-\tstr.w\tr8, [r0, #16]!\n+\tmoveq.w\tr9, #0\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n \tcmp\tr2, #0\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tit\teq\n+\tmoveq\tr8, r5\n+\tstrd\tr5, r5, [r7, #348]\t@ 0x15c\n+\tit\tne\n+\tmovne\tr8, r3\n+\tstrd\tr6, r6, [r7, #360]\t@ 0x168\n \tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #408]\t@ 0x198\n-\tmov.w\tr3, #3\n-\tstr.w\tr3, [r7, #436]\t@ 0x1b4\n+\tstr.w\tr6, [r7, #376]\t@ 0x178\n+\tstrh.w\tr3, [r7, #352]\t@ 0x160\n+\tmovs\tr3, #3\n+\tstr.w\tr3, [r7, #380]\t@ 0x17c\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tmov\tr8, r1\n-\tstr\tr6, [sp, #0]\n-\tmov\tr9, r2\n-\tldr.w\tr5, [r7, #608]\t@ 0x260\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tstr\tr5, [sp, #4]\n-\tldr\tr3, [r7, #24]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #148\t@ 0x94\n+\tstr.w\tr3, [r7, #340]\t@ 0x154\n+\tmov\tfp, r1\n+\tstrd\tr9, r8, [sp]\n+\tstr\tr2, [r7, #40]\t@ 0x28\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #92\t@ 0x5c\n \tldrd\tr2, r3, [r4, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r4, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tldrd\tr1, r2, [r4, #52]\t@ 0x34\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #192]\t@ (88c0 <__gridxc_alloc_MOD_realloc_i3+0x460>)\n-\tadds\tr2, #1\n+\tldr.w\tr1, [pc, #1064]\t@ 85b0 <__gridxc_alloc_MOD_realloc_i3+0x7c4>\n+\tadd\tr2, r6\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r8\n+\tmov\tr2, fp\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr6, r5, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r9\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tstrd\tr9, r8, [sp, #4]\n+\tstr\tr6, [sp, #0]\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldr\tr3, [r4, #40]\t@ 0x28\n \tldrd\tr0, r2, [r4, #52]\t@ 0x34\n-\tstr\tr3, [r7, #88]\t@ 0x58\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n \tldr.w\tr8, [r4, #44]\t@ 0x2c\n \tcmp\tr0, r2\n-\tbgt.n\t88c8 <__gridxc_alloc_MOD_realloc_i3+0x468>\n+\tbgt.n\t821e <__gridxc_alloc_MOD_realloc_i3+0x432>\n \tcmp\tr3, r8\n-\tbgt.n\t88c8 <__gridxc_alloc_MOD_realloc_i3+0x468>\n+\tbgt.n\t821e <__gridxc_alloc_MOD_realloc_i3+0x432>\n \tldrd\tr3, r1, [r4, #28]\n \tcmp\tr3, r1\n-\tbgt.n\t88c8 <__gridxc_alloc_MOD_realloc_i3+0x468>\n+\tbgt.n\t821e <__gridxc_alloc_MOD_realloc_i3+0x432>\n \tmov\tr9, r0\n \tldr\tr0, [r4, #24]\n-\tadds\tr1, #1\n-\tmovs\tr5, #0\n+\tadd\tr1, r6\n+\tstr.w\tsl, [r7, #72]\t@ 0x48\n \tsubs\tr1, r1, r3\n-\tstrd\tsl, r2, [r7, #80]\t@ 0x50\n+\tmov\tfp, r1\n \tmul.w\tlr, r0, r3\n \tldrd\tr6, r3, [r4]\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr1, [r7, #80]\t@ 0x50\n \tldr\tr3, [r4, #48]\t@ 0x30\n-\tldr\tr2, [r7, #92]\t@ 0x5c\n-\tldr.w\tip, [r7, #88]\t@ 0x58\n-\tmla\tsl, r3, r9, r2\n-\tldr\tr2, [r4, #36]\t@ 0x24\n+\tldr.w\tip, [r7, #76]\t@ 0x4c\n+\tstr.w\tr9, [r7, #84]\t@ 0x54\n+\tmla\tsl, r3, r9, r1\n+\tmov\tr1, fp\n+\tldr\tr3, [r4, #36]\t@ 0x24\n \tmov.w\tfp, #0\n-\tmla\tr2, r2, ip, sl\n-\tadd\tr2, lr\n+\tmla\tr3, r3, ip, sl\n+\tadd.w\tr9, r3, lr\n \tldr\tr3, [r4, #20]\n \tadd.w\tfp, fp, #1\n \tcmp\tr1, fp\n-\tmul.w\tr3, r2, r3\n-\tadd\tr2, r0\n+\tmul.w\tr3, r3, r9\n+\tadd\tr9, r0\n \tstr\tr5, [r6, r3]\n-\tbne.n\t8868 <__gridxc_alloc_MOD_realloc_i3+0x408>\n+\tbne.n\t81fa <__gridxc_alloc_MOD_realloc_i3+0x40e>\n \tadd.w\tr3, ip, #1\n \tcmp\tr8, ip\n-\tbeq.w\t8bfe <__gridxc_alloc_MOD_realloc_i3+0x79e>\n+\tbeq.w\t8554 <__gridxc_alloc_MOD_realloc_i3+0x768>\n \tmov\tip, r3\n-\tb.n\t885c <__gridxc_alloc_MOD_realloc_i3+0x3fc>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000424\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000040e\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002fc\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000024e\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000138\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000bc\n- R_ARM_REL32\t.LC29\n-\tldr.w\tsl, [r7, #80]\t@ 0x50\n-\tldr\tr3, [pc, #908]\t@ (8c58 <__gridxc_alloc_MOD_realloc_i3+0x7f8>)\n+\tb.n\t81ec <__gridxc_alloc_MOD_realloc_i3+0x400>\n+\tldr.w\tsl, [r7, #72]\t@ 0x48\n+\tldr\tr3, [pc, #916]\t@ (85b4 <__gridxc_alloc_MOD_realloc_i3+0x7c8>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t8abe <__gridxc_alloc_MOD_realloc_i3+0x65e>\n+\tbeq.w\t840e <__gridxc_alloc_MOD_realloc_i3+0x622>\n \tldr.w\tr3, [sl, #8]\n-\tstr\tr3, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r7, #56]\t@ 0x38\n \tmov\tr2, r3\n \tldr.w\tr3, [sl, #12]\n-\tldrd\tr9, r0, [sl]\n-\tsub.w\tfp, r3, r2\n-\tldr.w\tr2, [sl, #16]\n-\tldr.w\tr3, [sl, #20]\n-\tsub.w\tr0, r0, r9\n-\tstr\tr2, [r7, #60]\t@ 0x3c\n-\torr.w\tr1, r0, fp\n+\tldrd\tr8, r0, [sl]\n \tsubs\tr2, r3, r2\n-\tadd.w\tr3, fp, #1\n-\tstr\tr2, [r7, #80]\t@ 0x50\n-\tstr.w\tsp, [r7, #20]\n-\tmla\tr5, r0, r3, r3\n+\tldr.w\tr1, [sl, #16]\n+\tldr.w\tr3, [sl, #20]\n+\tsub.w\tr0, r0, r8\n+\tstr\tr1, [r7, #52]\t@ 0x34\n+\tsubs\tr5, r3, r1\n+\tadds\tr3, r2, #1\n+\torr.w\tr1, r0, r2\n+\tstr\tr2, [r7, #20]\n+\tstr\tr5, [r7, #72]\t@ 0x48\n+\tmla\tr6, r0, r3, r3\n+\tstr.w\tsp, [r7, #12]\n \tldrd\tlr, r3, [r4]\n-\tstr\tr3, [r7, #56]\t@ 0x38\n-\tstr\tr5, [r7, #76]\t@ 0x4c\n+\tstr\tr3, [r7, #48]\t@ 0x30\n+\tstr\tr6, [r7, #68]\t@ 0x44\n \tadds\tr3, r0, #1\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\torrs.w\tr3, r2, r1\n-\tbmi.w\t8b68 <__gridxc_alloc_MOD_realloc_i3+0x708>\n-\tmla\tr3, r2, r5, r5\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\torrs.w\tr3, r5, r1\n+\tbmi.w\t84b8 <__gridxc_alloc_MOD_realloc_i3+0x6cc>\n+\tmla\tr3, r5, r6, r6\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tmov\tr5, sp\n \tcmp\tr5, r2\n-\tbeq.w\t8c0e <__gridxc_alloc_MOD_realloc_i3+0x7ae>\n+\tbeq.w\t8568 <__gridxc_alloc_MOD_realloc_i3+0x77c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t8936 <__gridxc_alloc_MOD_realloc_i3+0x4d6>\n-\tldrd\tr1, r4, [r7, #68]\t@ 0x44\n-\tldr\tr2, [r7, #52]\t@ 0x34\n+\tb.n\t828a <__gridxc_alloc_MOD_realloc_i3+0x49e>\n+\tldrd\tr4, r1, [r7, #60]\t@ 0x3c\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r7, #84]\t@ 0x54\n \tadds\tr4, #1\n \tadd\tr1, r2\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tadd\tr3, r2\n-\tldr\tr2, [r7, #80]\t@ 0x50\n-\tcmp\tr4, r2\n-\tble.w\t8bc6 <__gridxc_alloc_MOD_realloc_i3+0x766>\n-\tldrd\tr9, ip, [r7, #12]\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tcmp\tr2, r4\n+\tbge.w\t851c <__gridxc_alloc_MOD_realloc_i3+0x730>\n+\tldr.w\tip, [r7, #16]\n \tmovs\tr2, #0\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tldrd\tr4, lr, [r7, #4]\n-\tmul.w\tfp, r9, ip\n+\tldrd\tlr, r8, [r7, #4]\n+\tmov\tsl, r2\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tldr\tr4, [r7, #0]\n \tadd.w\tr9, r3, #1\n-\tadd\tr9, sl\n-\tstr.w\tr9, [r7, #84]\t@ 0x54\n-\tmov\tr9, r2\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #20]\n+\tmul.w\tfp, r8, ip\n+\tadd\tr9, r3\n+\tldr\tr1, [r7, #52]\t@ 0x34\n \tmov\tr6, r2\n \tldr\tr3, [r4, #48]\t@ 0x30\n-\tadd.w\tr8, r1, r9\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tldr\tr5, [r7, #64]\t@ 0x40\n-\tstrd\tr9, r2, [r7, #68]\t@ 0x44\n+\tadd.w\tr8, r1, sl\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr5, [r7, #56]\t@ 0x38\n+\tstrd\tsl, r2, [r7, #60]\t@ 0x3c\n \tmla\tr8, r3, r8, r1\n-\tmov\tr9, r8\n-\tldr\tr2, [r4, #36]\t@ 0x24\n+\tstr.w\tr8, [r7, #84]\t@ 0x54\n+\tldr\tr3, [r7, #84]\t@ 0x54\n \tmovs\tr1, #0\n-\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tldr\tr2, [r4, #36]\t@ 0x24\n \tmov\tsl, r5\n-\tmla\tr2, r2, r5, r9\n-\tadd.w\tr8, r3, r6, lsl #2\n+\tmla\tr2, r2, r5, r3\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tadd\tr2, fp\n+\tadd.w\tr8, r3, r6, lsl #2\n \tldr\tr3, [r4, #20]\n-\tcmp\tr0, r1\n+\tcmp\tr1, r0\n \tldr.w\tr5, [r8], #4\n \tadd.w\tr1, r1, #1\n \tmul.w\tr3, r2, r3\n \tadd\tr2, ip\n \tstr.w\tr5, [lr, r3]\n-\tbne.n\t89a6 <__gridxc_alloc_MOD_realloc_i3+0x546>\n-\tldr\tr3, [r7, #88]\t@ 0x58\n+\tbne.n\t82fe <__gridxc_alloc_MOD_realloc_i3+0x512>\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n \tmov\tr5, sl\n \tadds\tr5, #1\n \tadd\tr6, r3\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tcmp\tr3, r5\n-\tbne.n\t8994 <__gridxc_alloc_MOD_realloc_i3+0x534>\n-\tldrd\tr9, r2, [r7, #68]\t@ 0x44\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n-\tadd.w\tr9, r9, #1\n+\tcmp\tr5, r9\n+\tbne.n\t82ea <__gridxc_alloc_MOD_realloc_i3+0x4fe>\n+\tldrd\tsl, r2, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tadd.w\tsl, sl, #1\n \tadd\tr2, r3\n-\tldr\tr3, [r7, #80]\t@ 0x50\n-\tcmp\tr9, r3\n-\tble.n\t897c <__gridxc_alloc_MOD_realloc_i3+0x51c>\n-\tldr\tr5, [r7, #36]\t@ 0x24\n-\tadd.w\tr0, r7, #148\t@ 0x94\n-\tldr\tr6, [r7, #32]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tcmp\tr3, sl\n+\tbge.n\t82d0 <__gridxc_alloc_MOD_realloc_i3+0x4e4>\n+\tldr\tr5, [r7, #28]\n+\tadd.w\tr0, r7, #92\t@ 0x5c\n+\tldr\tr6, [r7, #40]\t@ 0x28\n \tmovs\tr4, #1\n-\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n \tcmp\tr5, #0\n \tit\teq\n \tmoveq\tr3, #0\n \tcmp\tr6, #0\n-\tstr.w\tr3, [r7, #604]\t@ 0x25c\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tstr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #608]\t@ 0x260\n-\tldrd\tr2, r3, [r7, #480]\t@ 0x1e0\n-\tldr.w\tsp, [r7, #20]\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tldrd\tr2, r3, [r7, #424]\t@ 0x1a8\n+\tldr.w\tsp, [r7, #12]\n \tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #468]\t@ 0x1d4\n+\tldrd\tr1, r2, [r7, #412]\t@ 0x19c\n \tadds\tr3, #1\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #492]\t@ 0x1ec\n+\tldrd\tr1, r2, [r7, #436]\t@ 0x1b4\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [pc, #560]\t@ (8c5c <__gridxc_alloc_MOD_realloc_i3+0x7fc>)\n+\tldr\tr1, [pc, #564]\t@ (85b8 <__gridxc_alloc_MOD_realloc_i3+0x7cc>)\n \tadds\tr2, #1\n \tadd\tr1, pc\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r5\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #28]\n-\tcbz\tr3, 8a5e <__gridxc_alloc_MOD_realloc_i3+0x5fe>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #24]\n+\tcbz\tr3, 83b4 <__gridxc_alloc_MOD_realloc_i3+0x5c8>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tvldr\td18, [pc, #468]\t@ 8c40 <__gridxc_alloc_MOD_realloc_i3+0x7e0>\n-\tvldr\td19, [pc, #472]\t@ 8c48 <__gridxc_alloc_MOD_realloc_i3+0x7e8>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [pc, #492]\t@ (8c60 <__gridxc_alloc_MOD_realloc_i3+0x800>)\n-\tvldr\td17, [pc, #472]\t@ 8c50 <__gridxc_alloc_MOD_realloc_i3+0x7f0>\n+\tldr\tr0, [pc, #516]\t@ (85bc <__gridxc_alloc_MOD_realloc_i3+0x7d0>)\n+\tmovs\tr5, #0\n+\tldr\tr3, [r7, #32]\n \tadd\tr0, pc\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #40]\t@ 0x28\n+\tstrd\tr5, r5, [r7, #348]\t@ 0x15c\n+\tstr.w\tr3, [r7, #336]\t@ 0x150\n+\tldr\tr1, [r7, #28]\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #360]\t@ 0x168\n+\tstr.w\tr4, [r7, #376]\t@ 0x178\n \tmovs\tr4, #4\n-\tldrd\tr2, r1, [r7, #32]\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #400]\t@ 0x190\n+\tstr.w\tr4, [r7, #356]\t@ 0x164\n+\tstr.w\tr4, [r7, #344]\t@ 0x158\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #368]\t@ 0x170\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #404]\t@ 0x194\n-\tstrh.w\tr4, [r7, #408]\t@ 0x198\n+\tstrh.w\tr4, [r7, #352]\t@ 0x160\n \tmovs\tr4, #3\n-\tstr.w\tr4, [r7, #436]\t@ 0x1b4\n+\tstr.w\tr4, [r7, #380]\t@ 0x17c\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #396]\t@ 0x18c\n-\tldr.w\tr4, [r7, #608]\t@ 0x260\n-\tldr\tr3, [r7, #24]\n+\tstr.w\tr4, [r7, #340]\t@ 0x154\n+\tldr.w\tr4, [r7, #520]\t@ 0x208\n+\tldrd\tr3, r2, [r7, #36]\t@ 0x24\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #604]\t@ 0x25c\n+\tldr.w\tr4, [r7, #516]\t@ 0x204\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #420]\t@ (8c64 <__gridxc_alloc_MOD_realloc_i3+0x804>)\n-\tldr\tr3, [pc, #420]\t@ (8c68 <__gridxc_alloc_MOD_realloc_i3+0x808>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #432]\t@ (85c0 <__gridxc_alloc_MOD_realloc_i3+0x7d4>)\n+\tldr\tr3, [pc, #392]\t@ (859c <__gridxc_alloc_MOD_realloc_i3+0x7b0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t8c2e <__gridxc_alloc_MOD_realloc_i3+0x7ce>\n-\tadd.w\tr7, r7, #508\t@ 0x1fc\n+\tbne.w\t8588 <__gridxc_alloc_MOD_realloc_i3+0x79c>\n+\tadd.w\tr7, r7, #452\t@ 0x1c4\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tstr\tr3, [r7, #72]\t@ 0x48\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tstr\tr3, [r7, #48]\t@ 0x30\n-\tb.n\t853e <__gridxc_alloc_MOD_realloc_i3+0xde>\n-\tldrd\tr2, r3, [r7, #480]\t@ 0x1e0\n-\tadd.w\tr0, r7, #148\t@ 0x94\n-\tldr\tr5, [r7, #36]\t@ 0x24\n-\tsubs\tr3, r3, r2\n-\tldrd\tr1, r2, [r7, #468]\t@ 0x1d4\n-\tadds\tr3, #1\n-\tcmp\tr5, #0\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #168\t@ 0xa8\n+\tstr\tr3, [r7, #32]\n+\tb.n\t7ec6 <__gridxc_alloc_MOD_realloc_i3+0xda>\n+\tldr\tr3, [r7, #28]\n+\tadd.w\tr0, r7, #92\t@ 0x5c\n+\tcmp\tr3, #0\n+\tldrd\tr2, r3, [r7, #424]\t@ 0x1a8\n+\tsub.w\tr3, r3, r2\n+\tldrd\tr1, r2, [r7, #412]\t@ 0x19c\n+\tadd\tr3, r5\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadd.w\tr2, r2, #1\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldrd\tr1, r2, [r7, #492]\t@ 0x1ec\n+\tldrd\tr1, r2, [r7, #436]\t@ 0x1b4\n \tsub.w\tr2, r2, r1\n-\tldr\tr1, [pc, #332]\t@ (8c6c <__gridxc_alloc_MOD_realloc_i3+0x80c>)\n-\tadd.w\tr2, r2, #1\n-\tadd\tr1, pc\n+\tadd\tr2, r5\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tstr\tr5, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #516]\t@ 0x204\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #32]\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n-\tcmp\tr2, #0\n+\tldr\tr5, [r7, #40]\t@ 0x28\n+\tldr.w\tr1, [r7, #520]\t@ 0x208\n+\tcmp\tr5, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #300]\t@ (85c4 <__gridxc_alloc_MOD_realloc_i3+0x7d8>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #28]\n+\tldr\tr2, [r7, #28]\n+\tadd\tr1, pc\n+\tmov\tr3, r5\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #24]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tr9, [r8, #16]\n-\tstr.w\tr9, [r7, #28]\n-\tb.n\t8664 <__gridxc_alloc_MOD_realloc_i3+0x204>\n-\tcmp\tr2, #0\n-\tblt.w\t89de <__gridxc_alloc_MOD_realloc_i3+0x57e>\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #24]\n+\tb.n\t7fd2 <__gridxc_alloc_MOD_realloc_i3+0x1e6>\n+\tcmp\tr5, #0\n+\tblt.w\t8334 <__gridxc_alloc_MOD_realloc_i3+0x548>\n \tldr.w\tip, [r4, #24]\n-\tldr\tr3, [r7, #24]\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r7, #80]\t@ 0x50\n \tcmp\tr1, #0\n-\tblt.w\t89de <__gridxc_alloc_MOD_realloc_i3+0x57e>\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tldr\tr5, [r7, #64]\t@ 0x40\n-\tstrd\tr9, ip, [r7, #12]\n-\tstr.w\tlr, [r7, #8]\n+\tblt.w\t8334 <__gridxc_alloc_MOD_realloc_i3+0x548>\n+\tldr.w\tr2, [r7, #432]\t@ 0x1b0\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tldr\tr5, [r7, #56]\t@ 0x38\n+\tstr.w\tr8, [r7, #8]\n+\tldr.w\tr9, [r7, #20]\n \tmla\tr3, r1, r2, r3\n-\tldr\tr1, [r7, #72]\t@ 0x48\n-\tldrd\tr8, lr, [r7, #88]\t@ 0x58\n-\tstr\tr4, [r7, #4]\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tldr.w\tsl, [r7, #76]\t@ 0x4c\n+\tstr\tr4, [r7, #0]\n+\tstr.w\tlr, [r7, #4]\n \tmul.w\tr2, r1, r2\n-\tstr\tr2, [r7, #52]\t@ 0x34\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n+\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n \tmla\tr3, r5, r2, r3\n-\tldr\tr5, [r7, #28]\n-\tmul.w\tr2, r1, r2\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tldr\tr2, [r7, #68]\t@ 0x44\n-\tmla\tr3, r9, r2, r3\n-\tldr.w\tr9, [r7, #84]\t@ 0x54\n+\tmul.w\tfp, r1, r2\n+\tldr\tr2, [r7, #16]\n+\tstr.w\tip, [r7, #16]\n+\tmla\tr3, r8, r2, r3\n+\tldr.w\tr8, [r7, #80]\t@ 0x50\n \tmul.w\tr6, r1, r2\n-\tmla\tr1, r1, r3, r5\n+\tldr\tr2, [r7, #24]\n+\tmla\tr1, r1, r3, r2\n \tmovs\tr3, #0\n \tmov\tr4, r3\n \tmov\tip, r3\n \tmov\tr5, r1\n-\tmov.w\tsl, #0\n+\tmov.w\tlr, #0\n \tstr\tr3, [r7, #84]\t@ 0x54\n-\tstrd\tr1, r4, [r7, #68]\t@ 0x44\n-\tadd.w\tr4, lr, ip, lsl #2\n+\tstrd\tr4, r1, [r7, #60]\t@ 0x3c\n+\tadd.w\tr4, r8, ip, lsl #2\n \tmov\tr1, r5\n \tmovs\tr2, #0\n \tldr\tr3, [r1, #0]\n \tcmp\tr2, r0\n \tadd\tr1, r6\n \tadd.w\tr2, r2, #1\n \tstr.w\tr3, [r4], #4\n-\tbne.n\t8bdc <__gridxc_alloc_MOD_realloc_i3+0x77c>\n-\tadd\tr5, r9\n-\tadd\tip, r8\n-\tadd.w\tr3, sl, #1\n-\tcmp\tsl, fp\n-\tbeq.w\t8948 <__gridxc_alloc_MOD_realloc_i3+0x4e8>\n-\tmov\tsl, r3\n-\tb.n\t8bd4 <__gridxc_alloc_MOD_realloc_i3+0x774>\n-\tldr\tr2, [r7, #84]\t@ 0x54\n+\tbne.n\t8532 <__gridxc_alloc_MOD_realloc_i3+0x746>\n+\tadd\tr5, fp\n+\tadd\tip, sl\n+\tadd.w\tr3, lr, #1\n+\tcmp\tr9, lr\n+\tbeq.w\t829c <__gridxc_alloc_MOD_realloc_i3+0x4b0>\n+\tmov\tlr, r3\n+\tb.n\t852a <__gridxc_alloc_MOD_realloc_i3+0x73e>\n+\tldr.w\tr9, [r7, #84]\t@ 0x54\n+\tmov\tfp, r1\n \tadd.w\tr3, r9, #1\n \tcmp\tr2, r9\n-\tbeq.w\t88c4 <__gridxc_alloc_MOD_realloc_i3+0x464>\n+\tbeq.w\t821a <__gridxc_alloc_MOD_realloc_i3+0x42e>\n \tmov\tr9, r3\n-\tb.n\t8850 <__gridxc_alloc_MOD_realloc_i3+0x3f0>\n+\tb.n\t81da <__gridxc_alloc_MOD_realloc_i3+0x3ee>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbnz\tr3, 8c22 <__gridxc_alloc_MOD_realloc_i3+0x7c2>\n+\tcbnz\tr3, 857c <__gridxc_alloc_MOD_realloc_i3+0x790>\n \tadd\tr3, sp, #16\n \tldr.w\tip, [r4, #24]\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n-\tb.n\t8b76 <__gridxc_alloc_MOD_realloc_i3+0x716>\n+\tstr\tr3, [r7, #80]\t@ 0x50\n+\tb.n\t84c6 <__gridxc_alloc_MOD_realloc_i3+0x6da>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t8c18 <__gridxc_alloc_MOD_realloc_i3+0x7b8>\n-\tmov\tr8, r2\n-\tb.n\t86ca <__gridxc_alloc_MOD_realloc_i3+0x26a>\n+\tb.n\t8572 <__gridxc_alloc_MOD_realloc_i3+0x786>\n+\tmov\tr9, fp\n+\tb.n\t803c <__gridxc_alloc_MOD_realloc_i3+0x250>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovw\tr8, #5014\t@ 0x1396\n-\tb.n\t8764 <__gridxc_alloc_MOD_realloc_i3+0x304>\n-\tmovw\tr8, #5020\t@ 0x139c\n-\tb.n\t8764 <__gridxc_alloc_MOD_realloc_i3+0x304>\n-\tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x0000038a\n+\tmovw\tr9, #5014\t@ 0x1396\n+\tb.n\t80e6 <__gridxc_alloc_MOD_realloc_i3+0x2fa>\n+\tmovw\tr9, #5020\t@ 0x139c\n+\tb.n\t80e6 <__gridxc_alloc_MOD_realloc_i3+0x2fa>\n+\t.word\t0x0000078c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000778\n R_ARM_REL32\t.bss\n-\t.word\t0x0000022a\n+\t.word\t0x00000634\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005ce\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004ba\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000420\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x00000390\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000230\n R_ARM_REL32\t.LC29\n-\t.word\t0x000001e4\n+\t.word\t0x000001fe\n R_ARM_REL32\t.bss\n-\t.word\t0x0000019e\n+\t.word\t0x000001aa\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000144\n+\t.word\t0x00000120\n R_ARM_REL32\t.LC29\n \n-00008c70 <__gridxc_alloc_MOD_realloc_i2>:\n+000085c8 <__gridxc_alloc_MOD_realloc_i2>:\n __gridxc_alloc_MOD_realloc_i2():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3640]\t@ 0xe38\n-\tsub\tsp, #404\t@ 0x194\n+\tstr.w\tr0, [ip, #3704]\t@ 0xe78\n+\tsub\tsp, #356\t@ 0x164\n \tadd\tr7, sp, #16\n \tmov\tr4, r0\n-\tldr\tr5, [pc, #972]\t@ (9058 <__gridxc_alloc_MOD_realloc_i2+0x3e8>)\n+\tldr.w\tr6, [pc, #1528]\t@ 8bd8 <__gridxc_alloc_MOD_realloc_i2+0x610>\n \tmov\tsl, r3\n-\tldr.w\tip, [pc, #972]\t@ 905c <__gridxc_alloc_MOD_realloc_i2+0x3ec>\n-\tldrd\tr6, r0, [r7, #440]\t@ 0x1b8\n-\tstr\tr0, [r7, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #964]\t@ (9060 <__gridxc_alloc_MOD_realloc_i2+0x3f0>)\n-\tadd\tr5, pc\n-\tadd\tip, pc\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tldr.w\tfp, [r7, #452]\t@ 0x1c4\n-\tldr\tr0, [r5, r0]\n+\tldrd\tr5, r0, [r7, #376]\t@ 0x178\n+\tstr\tr0, [r7, #48]\t@ 0x30\n+\tldr.w\tr0, [pc, #1520]\t@ 8bdc <__gridxc_alloc_MOD_realloc_i2+0x614>\n+\tadd\tr6, pc\n+\tldr.w\tr3, [r7, #384]\t@ 0x180\n+\tldr\tr0, [r6, r0]\n+\tldr.w\tr6, [pc, #1512]\t@ 8be0 <__gridxc_alloc_MOD_realloc_i2+0x618>\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #380]\t@ 0x17c\n+\tstr.w\tr0, [r7, #332]\t@ 0x14c\n \tmov.w\tr0, #0\n \tldr\tr0, [r4, #0]\n-\tstr\tr3, [r7, #56]\t@ 0x38\n-\tmovs\tr3, #1\n+\tadd\tr6, pc\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n \tcmp\tr0, #0\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tr3, [ip]\n-\tldr.w\tip, [r7, #456]\t@ 0x1c8\n-\tbeq.n\t8d1c <__gridxc_alloc_MOD_realloc_i2+0xac>\n-\tldr\tr5, [r4, #44]\t@ 0x2c\n-\tstr\tr5, [r7, #44]\t@ 0x2c\n-\tldr\tr5, [r4, #28]\n-\tstr\tr5, [r7, #40]\t@ 0x28\n-\tldr\tr5, [r4, #32]\n-\tstr\tr5, [r7, #36]\t@ 0x24\n-\tldr\tr5, [r4, #36]\t@ 0x24\n-\tstr\tr5, [r7, #12]\n-\tldr\tr5, [r4, #4]\n-\tstr\tr5, [r7, #4]\n-\tldr\tr5, [r4, #24]\n-\tstr\tr5, [r7, #8]\n-\tldr\tr5, [r4, #20]\n+\titet\teq\n+\tstreq\tr0, [r7, #56]\t@ 0x38\n+\tmovne.w\tip, #1\n+\tmoveq.w\tip, #0\n+\tstr.w\tip, [r6]\n+\tldrd\tip, lr, [r7, #388]\t@ 0x184\n+\tbeq.n\t866e <__gridxc_alloc_MOD_realloc_i2+0xa6>\n \tldr\tr3, [r4, #40]\t@ 0x28\n-\tstr\tr5, [r7, #76]\t@ 0x4c\n-\tldr\tr5, [r7, #44]\t@ 0x2c\n-\tstr\tr3, [r7, #24]\n-\tsub.w\tr8, r5, r3\n-\tldrd\tr3, r5, [r7, #36]\t@ 0x24\n-\tcmp\tr3, r5\n-\tblt.w\t928c <__gridxc_alloc_MOD_realloc_i2+0x61c>\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r4, #28]\n+\tstr\tr3, [r7, #32]\n+\tldr\tr3, [r4, #32]\n+\tstr\tr3, [r7, #28]\n+\tldr\tr3, [r4, #36]\t@ 0x24\n+\tstr\tr3, [r7, #12]\n+\tldr\tr3, [r4, #4]\n+\tstr\tr3, [r7, #4]\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tldr\tr6, [r4, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #56]\t@ 0x38\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr6, [r7, #24]\n+\tsub.w\tr8, r6, r3\n+\tldrd\tr6, r3, [r7, #28]\n+\tcmp\tr6, r3\n+\tblt.w\t8b82 <__gridxc_alloc_MOD_realloc_i2+0x5ba>\n \tcmp.w\tr8, #0\n-\tstr.w\tr5, [r7, #168]\t@ 0xa8\n-\tldr.w\tr8, [r7, #36]\t@ 0x24\n-\tblt.w\t92aa <__gridxc_alloc_MOD_realloc_i2+0x63a>\n-\tldr.w\tlr, [r7, #24]\n-\tldr.w\tr9, [r7, #44]\t@ 0x2c\n-\tstrd\tr8, lr, [r7, #172]\t@ 0xac\n-\tstr.w\tr9, [r7, #180]\t@ 0xb4\n-\tstr\tr0, [r7, #48]\t@ 0x30\n-\tb.n\t8d1e <__gridxc_alloc_MOD_realloc_i2+0xae>\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr3, [r6, #0]\n-\tldr.w\tr0, [sl]\n-\tadd.w\tr6, r7, #364\t@ 0x16c\n-\tvldr\td18, [pc, #776]\t@ 9038 <__gridxc_alloc_MOD_realloc_i2+0x3c8>\n-\tvldr\td19, [pc, #780]\t@ 9040 <__gridxc_alloc_MOD_realloc_i2+0x3d0>\n-\tstr\tr6, [r7, #28]\n-\tldr\tr1, [r1, #0]\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr0, r3, [r7, #104]\t@ 0x68\n-\tadd.w\tr3, r7, #204\t@ 0xcc\n-\tstrd\tr1, r2, [r7, #96]\t@ 0x60\n-\tadd.w\tr0, r7, #348\t@ 0x15c\n-\tvldr\td17, [pc, #764]\t@ 9048 <__gridxc_alloc_MOD_realloc_i2+0x3d8>\n-\tmovs\tr2, #2\n-\tvldr\td20, [r7, #96]\t@ 0x60\n-\tvldr\td21, [r7, #104]\t@ 0x68\n-\tvstr\td16, [r7, #192]\t@ 0xc0\n-\tvstr\td16, [r7, #196]\t@ 0xc4\n-\tadd.w\tr1, r7, #136\t@ 0x88\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #220\t@ 0xdc\n-\tvstr\td16, [r7, #240]\t@ 0xf0\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #252\t@ 0xfc\n-\tvstr\td16, [r7, #244]\t@ 0xf4\n-\tvstr\td16, [r7, #288]\t@ 0x120\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tvstr\td16, [r7, #292]\t@ 0x124\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #300\t@ 0x12c\n-\tstr\tr0, [r7, #32]\n-\tstr.w\tr2, [r7, #228]\t@ 0xe4\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #316\t@ 0x13c\n-\tstr.w\tr2, [r7, #276]\t@ 0x114\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #328\t@ 0x148\n-\tmov\tr5, r3\n+\tstr\tr3, [r7, #124]\t@ 0x7c\n+\tmov\tr8, r6\n+\tblt.w\t8b98 <__gridxc_alloc_MOD_realloc_i2+0x5d0>\n+\tldr\tr6, [r7, #36]\t@ 0x24\n+\tldr.w\tr9, [r7, #24]\n+\tstrd\tr8, r6, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #136]\t@ 0x88\n+\tstr\tr0, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [sl]\n+\tmovs\tr6, #1\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tmovs\tr0, #4\n+\tldr\tr3, [r1, #0]\n+\tadd.w\tr8, r7, #92\t@ 0x5c\n+\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tmvn.w\tr1, #2\n+\tldr\tr3, [r5, #0]\n+\tadd.w\tr5, r7, #76\t@ 0x4c\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tadd.w\tsl, r7, #108\t@ 0x6c\n+\tldr\tr3, [r2, #0]\n+\tmovs\tr2, #0\n+\tstr\tr3, [r7, #112]\t@ 0x70\n+\tadd.w\tr3, r7, #284\t@ 0x11c\n+\tstrd\tr2, r2, [r7, #148]\t@ 0x94\n \tstr\tr3, [r7, #52]\t@ 0x34\n-\tstr.w\tr2, [r7, #324]\t@ 0x144\n-\tmvn.w\tr3, #2\n-\tvstr\td16, [r7, #336]\t@ 0x150\n-\tstr.w\tr3, [r7, #188]\t@ 0xbc\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tvstr\td20, [r7, #120]\t@ 0x78\n-\tvstr\td21, [r7, #128]\t@ 0x80\n-\tstr.w\tr1, [r7, #184]\t@ 0xb8\n-\tadd.w\tr1, r7, #152\t@ 0x98\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n-\tmov\tr3, r5\n-\tldr\tr5, [pc, #640]\t@ (9064 <__gridxc_alloc_MOD_realloc_i2+0x3f4>)\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n-\tadd.w\tr2, r7, #280\t@ 0x118\n-\tadd\tr5, pc\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstr.w\tr1, [r7, #232]\t@ 0xe8\n-\tadd.w\tr1, r7, #168\t@ 0xa8\n-\tvst1.32\t{d18-d19}, [r0]\n-\tadd.w\tr0, r7, #184\t@ 0xb8\n-\tvst1.32\t{d17}, [r6]\n-\tadd.w\tr6, r7, #120\t@ 0x78\n-\tstr\tr1, [r7, #20]\n-\tstr.w\tr1, [r7, #280]\t@ 0x118\n-\tadd.w\tr1, r7, #232\t@ 0xe8\n-\tstr.w\tr6, [r7, #328]\t@ 0x148\n-\tstrd\tfp, ip, [sp]\n-\tbl\t1fc <__gridxc_alloc_MOD_options.constprop.1>\n-\tldr\tr3, [r5, #8]\n-\tcbz\tr3, 8e2e <__gridxc_alloc_MOD_realloc_i2+0x1be>\n-\tldr.w\tr8, [r5, #12]\n-\tcmp.w\tr8, #0\n-\tbeq.w\t9222 <__gridxc_alloc_MOD_realloc_i2+0x5b2>\n-\tldr\tr3, [pc, #568]\t@ (9068 <__gridxc_alloc_MOD_realloc_i2+0x3f8>)\n+\tmovs\tr3, #2\n+\tstr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstrd\tr2, r2, [r7, #196]\t@ 0xc4\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tstr.w\tr3, [r7, #172]\t@ 0xac\n+\tstr.w\tr3, [r7, #184]\t@ 0xb8\n+\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tstr.w\tr3, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #160]\t@ 0xa0\n+\tstr.w\tr0, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #144]\t@ 0x90\n+\tstr.w\tr1, [r7, #192]\t@ 0xc0\n+\tstrd\tr6, r6, [r7, #164]\t@ 0xa4\n+\tstr.w\tr6, [r7, #180]\t@ 0xb4\n+\tstrd\tr6, r6, [r7, #212]\t@ 0xd4\n+\tstr.w\tr6, [r7, #228]\t@ 0xe4\n+\tstr.w\tr5, [r7, #140]\t@ 0x8c\n+\tstr.w\tr8, [r7, #188]\t@ 0xbc\n+\tldr.w\tr8, [pc, #1268]\t@ 8be4 <__gridxc_alloc_MOD_realloc_i2+0x61c>\n+\tstrd\tr1, r2, [r7, #288]\t@ 0x120\n+\tstr.w\tr0, [r7, #256]\t@ 0x100\n+\tadd\tr8, pc\n+\tstr.w\tr0, [r7, #304]\t@ 0x130\n+\tadd.w\tr0, r7, #140\t@ 0x8c\n+\tstrd\tr2, r2, [r7, #244]\t@ 0xf4\n+\tstr.w\tr2, [r7, #252]\t@ 0xfc\n+\tstrd\tr6, r3, [r7, #264]\t@ 0x108\n+\tstrd\tr6, r3, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr1, [r7, #240]\t@ 0xf0\n+\tadd.w\tr1, r7, #188\t@ 0xbc\n+\tstrd\tr2, r2, [r7, #296]\t@ 0x128\n+\tadd.w\tr2, r7, #124\t@ 0x7c\n+\tstrd\tr6, r3, [r7, #312]\t@ 0x138\n+\tstrd\tr6, r3, [r7, #324]\t@ 0x144\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tstr\tr2, [r7, #20]\n+\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tadd.w\tr2, r7, #236\t@ 0xec\n+\tstr.w\tr6, [r7, #260]\t@ 0x104\n+\tstr.w\tr6, [r7, #308]\t@ 0x134\n+\tstr.w\tsl, [r7, #284]\t@ 0x11c\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tbl\t1ec <__gridxc_alloc_MOD_options.constprop.1>\n+\tldr.w\tr3, [r8, #8]\n+\tcbz\tr3, 8766 <__gridxc_alloc_MOD_realloc_i2+0x19e>\n+\tldr.w\tr9, [r8, #12]\n+\tcmp.w\tr9, #0\n+\tbeq.w\t8b16 <__gridxc_alloc_MOD_realloc_i2+0x54e>\n+\tldr.w\tr3, [pc, #1152]\t@ 8be8 <__gridxc_alloc_MOD_realloc_i2+0x620>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t8fd0 <__gridxc_alloc_MOD_realloc_i2+0x360>\n-\tldrd\tr5, r0, [r7, #136]\t@ 0x88\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r8, [r7, #144]\t@ 0x90\n-\tsubs\tr2, r0, r5\n-\torr.w\tr1, r2, r2, asr #31\n-\tvstr\td16, [r4, #12]\n+\tbeq.w\t891a <__gridxc_alloc_MOD_realloc_i2+0x352>\n+\tldrd\tr3, r2, [r5]\n+\tmovs\tr6, #0\n+\tldrd\tfp, r1, [r5, #8]\n+\tsub.w\tr8, r2, r3\n+\tstr\tr1, [r7, #60]\t@ 0x3c\n+\tnegs\tr5, r3\n+\torr.w\tr9, r8, r8, asr #31\n+\tsub.w\tr1, r1, fp\n+\torr.w\tr8, r8, r1\n+\tstr\tr2, [r7, #64]\t@ 0x40\n+\torr.w\tr1, r1, r1, asr #31\n+\tstrd\tr6, r6, [r4, #12]\n+\tmla\tr0, r9, fp, fp\n+\tmov.w\tr8, r8, lsr #31\n+\tadd.w\tr9, r9, #1\n \tadds\tr1, #1\n-\tstr\tr5, [r7, #80]\t@ 0x50\n-\tnegs\tr5, r5\n-\tstrd\tr1, r3, [r7, #88]\t@ 0x58\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tmovs\tr0, #4\n-\tvldr\td8, [r7, #80]\t@ 0x50\n-\tvldr\td9, [r7, #88]\t@ 0x58\n-\tmls\tr5, r1, r3, r5\n-\tsub.w\tr3, r8, r3\n+\tsub.w\tr2, r5, r0\n+\tmov.w\tr0, #4\n+\tstr\tr2, [r7, #68]\t@ 0x44\n \tstr\tr0, [r4, #8]\n-\torrs\tr2, r3\n \tmov.w\tr0, #258\t@ 0x102\n-\torr.w\tr3, r3, r3, asr #31\n \tstrh\tr0, [r4, #16]\n-\tlsrs\tr2, r2, #31\n-\tadds\tr3, #1\n-\tbeq.w\t92ce <__gridxc_alloc_MOD_realloc_i2+0x65e>\n-\tmvn.w\tip, #2147483648\t@ 0x80000000\n-\tudiv\tip, ip, r3\n-\tmul.w\tr3, r1, r3\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n-\tit\tlt\n-\tmovlt\tr0, #0\n-\tit\tge\n-\tmovge\tr0, #1\n-\tcmp\tip, r1\n+\tbeq.w\t8bba <__gridxc_alloc_MOD_realloc_i2+0x5f2>\n+\tmul.w\tr5, r1, r9\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tstr\tr3, [r7, #16]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp.w\tr5, #1073741824\t@ 0x40000000\n+\tldr\tr3, [r7, #16]\n+\tite\tlt\n+\tmovlt\tr1, #0\n+\tmovge\tr1, #1\n+\tcmp\tr0, r9\n \tit\tlt\n-\taddlt\tr0, #1\n-\tcmp\tr2, #0\n-\tbne.w\t92a6 <__gridxc_alloc_MOD_realloc_i2+0x636>\n-\tlsls\tr2, r3, #2\n-\tcmp\tr0, #0\n-\tbne.w\t92dc <__gridxc_alloc_MOD_realloc_i2+0x66c>\n-\tcmp\tr2, #1\n+\taddlt\tr1, #1\n+\tlsls\tr0, r5, #2\n+\tcmp.w\tr8, #0\n+\tbeq.n\t87ea <__gridxc_alloc_MOD_realloc_i2+0x222>\n+\tmov\tr0, r6\n+\tcmp\tr1, #0\n+\tbne.w\t8bcc <__gridxc_alloc_MOD_realloc_i2+0x604>\n+\tcmp\tr0, #1\n \tit\tcc\n-\tmovcc\tr2, #1\n-\tmov\tr0, r2\n+\tmovcc\tr0, #1\n+\tstr\tr3, [r7, #16]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t92e2 <__gridxc_alloc_MOD_realloc_i2+0x672>\n-\tadd.w\tr3, r4, #28\n-\tstr.w\tr8, [r4, #44]\t@ 0x2c\n-\tvldr\td16, [pc, #384]\t@ 9050 <__gridxc_alloc_MOD_realloc_i2+0x3e0>\n-\tvst1.32\t{d8-d9}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr\tr5, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t8bd2 <__gridxc_alloc_MOD_realloc_i2+0x60a>\n+\tldr\tr3, [r7, #16]\n+\tmovs\tr2, #1\n+\tstr\tr3, [r4, #28]\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tstr\tr3, [r4, #32]\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr3, [r4, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tstr\tr3, [r4, #4]\n+\tmovs\tr3, #4\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr2, [r7, #32]\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #336]\t@ 9038 <__gridxc_alloc_MOD_realloc_i2+0x3c8>\n-\tvldr\td19, [pc, #340]\t@ 9040 <__gridxc_alloc_MOD_realloc_i2+0x3d0>\n-\tstr.w\tr6, [r7, #328]\t@ 0x148\n-\tldr\tr0, [pc, #376]\t@ (906c <__gridxc_alloc_MOD_realloc_i2+0x3fc>)\n-\tvstr\td17, [r7, #340]\t@ 0x154\n-\tvst1.32\t{d18-d19}, [r2]\n+\tstr.w\tfp, [r4, #40]\t@ 0x28\n+\tstr.w\tr9, [r4, #36]\t@ 0x24\n+\tldr\tr0, [pc, #964]\t@ (8bec <__gridxc_alloc_MOD_realloc_i2+0x624>)\n+\tmovs\tr5, #0\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tmovs\tr6, #1\n \tadd\tr0, pc\n-\tldr\tr2, [r7, #28]\n-\tvldr\td16, [pc, #324]\t@ 9048 <__gridxc_alloc_MOD_realloc_i2+0x3d8>\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tldr.w\tr5, [r7, #460]\t@ 0x1cc\n-\tvst1.32\t{d16}, [r2]\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tcmp\tr1, #0\n-\tldr\tr2, [r7, #56]\t@ 0x38\n+\tstr.w\tsl, [r7, #284]\t@ 0x11c\n \tit\teq\n-\tmoveq\tr5, #0\n+\tmoveq.w\tr8, #0\n+\tstrd\tr5, r5, [r7, #296]\t@ 0x128\n \tstr.w\tr3, [r0, #16]!\n-\tmovs\tr3, #4\n-\tstr.w\tr3, [r7, #336]\t@ 0x150\n-\tmov.w\tr3, #258\t@ 0x102\n-\tstrh.w\tr3, [r7, #344]\t@ 0x158\n+\tmov\tfp, r2\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n+\tmov\tsl, r1\n+\tstrd\tr6, r6, [r7, #308]\t@ 0x134\n+\tit\tne\n+\tmovne\tr8, r3\n \tmovs\tr3, #2\n-\tstr.w\tr3, [r7, #372]\t@ 0x174\n-\tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #332]\t@ 0x14c\n+\tstr.w\tr3, [r7, #316]\t@ 0x13c\n \tcmp\tr2, #0\n-\tstr\tr5, [sp, #0]\n-\tmov\tr8, r1\n-\tldr.w\tr6, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr6, #0\n-\tstr\tr6, [sp, #4]\n-\tmov\tr9, r2\n+\tmoveq\tr9, r5\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tmov.w\tr3, #4\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r7, #400]\t@ 0x190\n+\tstr.w\tr6, [r7, #324]\t@ 0x144\n+\tit\tne\n+\tmovne\tr9, r3\n+\tmov.w\tr3, #258\t@ 0x102\n+\tstrh.w\tr3, [r7, #300]\t@ 0x12c\n+\tmvn.w\tr3, #2\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tstrd\tr8, r9, [sp]\n \tldr\tr3, [r7, #52]\t@ 0x34\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tadd.w\tr0, r7, #116\t@ 0x74\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tadd.w\tr0, r7, #72\t@ 0x48\n \tldrd\tr2, r3, [r4, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n \tldrd\tr1, r2, [r4, #28]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tsubs\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n-\tadds\tr2, #1\n-\tldr\tr1, [pc, #264]\t@ (9070 <__gridxc_alloc_MOD_realloc_i2+0x400>)\n+\tadd\tr2, r6\n+\tldr\tr1, [pc, #824]\t@ (8bf0 <__gridxc_alloc_MOD_realloc_i2+0x628>)\n \tbic.w\tr2, r2, r2, asr #31\n \tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n-\tmov\tr2, r8\n+\tmov\tr2, sl\n \tstr\tr3, [r0, #0]\n-\tmovs\tr3, #1\n-\tstrd\tr5, r6, [sp, #4]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r9\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tmov\tr3, fp\n+\tstrd\tr8, r9, [sp, #4]\n+\tstr\tr6, [sp, #0]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n \tldrd\tr1, r8, [r4, #40]\t@ 0x28\n \tldrd\tr2, r3, [r4, #28]\n \tcmp\tr1, r8\n-\tbgt.n\t8fd0 <__gridxc_alloc_MOD_realloc_i2+0x360>\n+\tbgt.n\t891a <__gridxc_alloc_MOD_realloc_i2+0x352>\n \tcmp\tr2, r3\n-\tbgt.n\t8fd0 <__gridxc_alloc_MOD_realloc_i2+0x360>\n+\tbgt.n\t891a <__gridxc_alloc_MOD_realloc_i2+0x352>\n \tldr\tr0, [r4, #24]\n-\tadds\tr3, #1\n+\tadd\tr3, r6\n \tldrd\tr6, r9, [r4]\n \tmov\tip, r1\n-\tmovs\tr5, #0\n \tsubs\tr1, r3, r2\n \tmul.w\tlr, r0, r2\n \tldr\tr2, [r4, #36]\t@ 0x24\n \tmov.w\tsl, #0\n \tmla\tr2, r2, ip, r9\n \tadd\tr2, lr\n \tldr\tr3, [r4, #20]\n \tadd.w\tsl, sl, #1\n \tcmp\tr1, sl\n \tmul.w\tr3, r2, r3\n \tadd\tr2, r0\n \tstr\tr5, [r6, r3]\n-\tbne.n\t8fb2 <__gridxc_alloc_MOD_realloc_i2+0x342>\n+\tbne.n\t88fc <__gridxc_alloc_MOD_realloc_i2+0x334>\n \tadd.w\tr3, ip, #1\n \tcmp\tr8, ip\n-\tbeq.n\t8fd0 <__gridxc_alloc_MOD_realloc_i2+0x360>\n+\tbeq.n\t891a <__gridxc_alloc_MOD_realloc_i2+0x352>\n \tmov\tip, r3\n-\tb.n\t8fa6 <__gridxc_alloc_MOD_realloc_i2+0x336>\n-\tldr\tr3, [pc, #160]\t@ (9074 <__gridxc_alloc_MOD_realloc_i2+0x404>)\n+\tb.n\t88f0 <__gridxc_alloc_MOD_realloc_i2+0x328>\n+\tldr\tr3, [pc, #728]\t@ (8bf4 <__gridxc_alloc_MOD_realloc_i2+0x62c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbeq.w\t91fe <__gridxc_alloc_MOD_realloc_i2+0x58e>\n-\tldr.w\tr2, [r7, #156]\t@ 0x9c\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n-\tldr.w\tr1, [r7, #160]\t@ 0xa0\n+\tbeq.w\t8af6 <__gridxc_alloc_MOD_realloc_i2+0x52e>\n+\tldr\tr2, [r7, #96]\t@ 0x60\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tldr\tr1, [r7, #100]\t@ 0x64\n \tsub.w\tip, r2, r3\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n+\tldr\tr2, [r7, #104]\t@ 0x68\n \tadd.w\tsl, ip, #1\n-\tstr\tr1, [r7, #72]\t@ 0x48\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tsub.w\tfp, r2, r1\n \tstr.w\tsp, [r7, #16]\n \tldrd\tr0, r2, [r4]\n-\tstr\tr2, [r7, #64]\t@ 0x40\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n \torrs.w\tr2, ip, fp\n-\tbmi.n\t9078 <__gridxc_alloc_MOD_realloc_i2+0x408>\n+\tbmi.n\t8976 <__gridxc_alloc_MOD_realloc_i2+0x3ae>\n \tmla\tr2, fp, sl, sl\n \tlsls\tr2, r2, #2\n \tadds\tr2, #7\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tmov\tr5, sp\n \tcmp\tr5, r1\n-\tbeq.w\t92b4 <__gridxc_alloc_MOD_realloc_i2+0x644>\n+\tbeq.w\t8ba0 <__gridxc_alloc_MOD_realloc_i2+0x5d8>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t9022 <__gridxc_alloc_MOD_realloc_i2+0x3b2>\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x000003ba\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003bc\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000276\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000234\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000016c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000100\n- R_ARM_REL32\t.LC29\n-\t.word\t0x0000009e\n- R_ARM_REL32\t.bss\n+\tb.n\t8964 <__gridxc_alloc_MOD_realloc_i2+0x39c>\n \tcmp.w\tfp, #0\n-\tblt.n\t912e <__gridxc_alloc_MOD_realloc_i2+0x4be>\n+\tblt.n\t8a2a <__gridxc_alloc_MOD_realloc_i2+0x462>\n \tldr\tr1, [r4, #24]\n \tldr\tr2, [r7, #52]\t@ 0x34\n-\tstr\tr2, [r7, #68]\t@ 0x44\n+\tstr\tr2, [r7, #64]\t@ 0x40\n \tcmp.w\tip, #0\n-\tblt.n\t912e <__gridxc_alloc_MOD_realloc_i2+0x4be>\n+\tblt.n\t8a2a <__gridxc_alloc_MOD_realloc_i2+0x462>\n \tldr\tr6, [r7, #12]\n \tldr\tr2, [r7, #4]\n-\tldr\tr5, [r7, #72]\t@ 0x48\n+\tldr\tr5, [r7, #68]\t@ 0x44\n \tstr\tr4, [r7, #4]\n-\tldr\tr4, [r7, #68]\t@ 0x44\n+\tldr\tr4, [r7, #64]\t@ 0x40\n \tmla\tr5, r5, r6, r2\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tstr\tr1, [r7, #76]\t@ 0x4c\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr1, [r7, #56]\t@ 0x38\n \tmul.w\tr9, r2, r6\n \tldr\tr6, [r7, #8]\n \tstrd\tr0, r3, [r7, #8]\n \tmla\tr5, r3, r6, r5\n \tmul.w\tlr, r2, r6\n-\tldr\tr6, [r7, #48]\t@ 0x30\n+\tldr\tr6, [r7, #40]\t@ 0x28\n \tmla\tr5, r2, r5, r6\n \tmovs\tr6, #0\n \tmov\tr8, r6\n \tadd.w\tr0, r4, r6, lsl #2\n \tmov\tr1, r5\n \tmovs\tr2, #0\n \tldr\tr3, [r1, #0]\n \tcmp\tip, r2\n \tadd\tr1, lr\n \tadd.w\tr2, r2, #1\n \tstr.w\tr3, [r0], #4\n-\tbne.n\t90c0 <__gridxc_alloc_MOD_realloc_i2+0x450>\n+\tbne.n\t89be <__gridxc_alloc_MOD_realloc_i2+0x3f6>\n \tadd.w\tr8, r8, #1\n \tadd\tr5, r9\n \tadd\tr6, sl\n \tcmp\tfp, r8\n-\tbge.n\t90b8 <__gridxc_alloc_MOD_realloc_i2+0x448>\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n+\tbge.n\t89b6 <__gridxc_alloc_MOD_realloc_i2+0x3ee>\n+\tldr\tr1, [r7, #56]\t@ 0x38\n \tmov.w\tlr, #0\n \tldrd\tr0, r3, [r7, #8]\n \tmov\tr6, lr\n \tldr\tr4, [r7, #4]\n+\tstr.w\tfp, [r7, #56]\t@ 0x38\n \tmul.w\tr8, r3, r1\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tmov\tfp, r6\n \tldr\tr3, [r4, #36]\t@ 0x24\n-\tldr\tr5, [r7, #64]\t@ 0x40\n+\tldr\tr5, [r7, #60]\t@ 0x3c\n \tadd\tr2, r6\n-\tstr.w\tlr, [r7, #76]\t@ 0x4c\n \tmla\tr2, r3, r2, r5\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldr\tr3, [r7, #64]\t@ 0x40\n \tmovs\tr5, #0\n \tadd\tr2, r8\n \tadd.w\tr9, r3, lr, lsl #2\n-\tmov\tlr, r6\n \tldr\tr3, [r4, #20]\n \tcmp\tip, r5\n \tldr.w\tr6, [r9], #4\n \tadd.w\tr5, r5, #1\n \tmul.w\tr3, r2, r3\n \tadd\tr2, r1\n \tstr\tr6, [r0, r3]\n-\tbne.n\t910a <__gridxc_alloc_MOD_realloc_i2+0x49a>\n-\tmov\tr6, lr\n-\tldr.w\tlr, [r7, #76]\t@ 0x4c\n+\tbne.n\t8a08 <__gridxc_alloc_MOD_realloc_i2+0x440>\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tmov\tr6, fp\n \tadds\tr6, #1\n \tadd\tlr, sl\n-\tcmp\tr6, fp\n-\tble.n\t90ee <__gridxc_alloc_MOD_realloc_i2+0x47e>\n-\tldr\tr2, [r7, #24]\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tcmp\tr3, r6\n+\tbge.n\t89f0 <__gridxc_alloc_MOD_realloc_i2+0x428>\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tldr\tr3, [r7, #24]\n \tmovs\tr4, #1\n-\tldr\tr5, [r7, #60]\t@ 0x3c\n+\tldr\tr5, [r7, #48]\t@ 0x30\n \tsubs\tr3, r3, r2\n-\tldrd\tr2, r1, [r7, #36]\t@ 0x24\n+\tldrd\tr2, r1, [r7, #28]\n \tadds\tr3, #1\n \tcmp\tr5, #0\n \tldr.w\tsp, [r7, #16]\n \tsub.w\tr2, r2, r1\n \tbic.w\tr3, r3, r3, asr #31\n \tadd.w\tr2, r2, #1\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tbic.w\tr2, r2, r2, asr #31\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr2, [r7, #396]\t@ 0x18c\n \tit\teq\n \tmoveq\tr2, #0\n-\tstr.w\tr2, [r7, #460]\t@ 0x1cc\n-\tldr\tr2, [r7, #56]\t@ 0x38\n+\tstr.w\tr2, [r7, #396]\t@ 0x18c\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tnegs\tr3, r3\n \tstr\tr3, [r0, #0]\n \tcmp\tr2, #0\n \tit\teq\n \tmoveq\tr1, #0\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr1, [r7, #400]\t@ 0x190\n \tstr\tr1, [sp, #8]\n-\tldr\tr1, [pc, #384]\t@ (9300 <__gridxc_alloc_MOD_realloc_i2+0x690>)\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tldr\tr1, [pc, #380]\t@ (8bf8 <__gridxc_alloc_MOD_realloc_i2+0x630>)\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n \tstr\tr3, [sp, #4]\n \tadd\tr1, pc\n \tmov\tr3, r2\n \tstr\tr4, [sp, #0]\n \tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tcbz\tr3, 919e <__gridxc_alloc_MOD_realloc_i2+0x52e>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tcbz\tr3, 8a9a <__gridxc_alloc_MOD_realloc_i2+0x4d2>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n+\tldr\tr0, [pc, #352]\t@ (8bfc <__gridxc_alloc_MOD_realloc_i2+0x634>)\n+\tmovs\tr5, #0\n \tldr\tr3, [r7, #20]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr.w\tr3, [r7, #328]\t@ 0x148\n-\tvldr\td18, [pc, #316]\t@ 92e8 <__gridxc_alloc_MOD_realloc_i2+0x678>\n-\tvldr\td19, [pc, #320]\t@ 92f0 <__gridxc_alloc_MOD_realloc_i2+0x680>\n-\tldr\tr3, [r7, #32]\n-\tldr\tr0, [pc, #336]\t@ (9304 <__gridxc_alloc_MOD_realloc_i2+0x694>)\n-\tvldr\td17, [pc, #320]\t@ 92f8 <__gridxc_alloc_MOD_realloc_i2+0x688>\n \tadd\tr0, pc\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tldr\tr3, [r7, #28]\n+\tstrd\tr5, r5, [r7, #296]\t@ 0x128\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldrd\tr2, r1, [r7, #44]\t@ 0x2c\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #308]\t@ 0x134\n+\tstr.w\tr4, [r7, #324]\t@ 0x144\n+\tmovs\tr4, #2\n+\tstr.w\tr4, [r7, #316]\t@ 0x13c\n+\tstr.w\tr4, [r7, #328]\t@ 0x148\n+\tstr.w\tr4, [r7, #320]\t@ 0x140\n \tmovs\tr4, #4\n-\tvst1.32\t{d17}, [r3]\n-\tstr.w\tr4, [r7, #336]\t@ 0x150\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n+\tstr.w\tr4, [r7, #292]\t@ 0x124\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #340]\t@ 0x154\n-\tstrh.w\tr4, [r7, #344]\t@ 0x158\n-\tmovs\tr4, #2\n-\tstr.w\tr4, [r7, #372]\t@ 0x174\n+\tstrh.w\tr4, [r7, #300]\t@ 0x12c\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #332]\t@ 0x14c\n-\tldr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tldrd\tr3, r2, [r7, #52]\t@ 0x34\n+\tstr.w\tr4, [r7, #288]\t@ 0x120\n+\tldr.w\tr4, [r7, #400]\t@ 0x190\n+\tldr\tr3, [r7, #52]\t@ 0x34\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr4, [r7, #396]\t@ 0x18c\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr2, [pc, #264]\t@ (9308 <__gridxc_alloc_MOD_realloc_i2+0x698>)\n-\tldr\tr3, [pc, #264]\t@ (930c <__gridxc_alloc_MOD_realloc_i2+0x69c>)\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr2, [pc, #264]\t@ (8c00 <__gridxc_alloc_MOD_realloc_i2+0x638>)\n+\tldr\tr3, [pc, #224]\t@ (8bdc <__gridxc_alloc_MOD_realloc_i2+0x614>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n+\tldr.w\tr3, [r7, #332]\t@ 0x14c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t92d8 <__gridxc_alloc_MOD_realloc_i2+0x668>\n-\tadd.w\tr7, r7, #388\t@ 0x184\n+\tbne.n\t8bc8 <__gridxc_alloc_MOD_realloc_i2+0x600>\n+\tadd.w\tr7, r7, #340\t@ 0x154\n \tmov\tsp, r7\n-\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldrd\tr1, r0, [r7, #36]\t@ 0x24\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tldrd\tr1, r0, [r7, #28]\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tcmp\tr3, #0\n \tsub.w\tr3, r1, r0\n-\tldr\tr0, [r7, #24]\n-\tadd.w\tr3, r3, #1\n-\tldr\tr1, [r7, #44]\t@ 0x2c\n+\tldr\tr0, [r7, #36]\t@ 0x24\n+\tadd\tr3, r6\n+\tldr\tr1, [r7, #24]\n \tbic.w\tr3, r3, r3, asr #31\n \tsub.w\tr2, r1, r0\n-\tadd.w\tr0, r7, #116\t@ 0x74\n-\tadd.w\tr2, r2, #1\n-\tldr\tr1, [pc, #200]\t@ (9310 <__gridxc_alloc_MOD_realloc_i2+0x6a0>)\n+\tadd.w\tr0, r7, #72\t@ 0x48\n+\tadd\tr2, r6\n \tbic.w\tr2, r2, r2, asr #31\n-\tadd\tr1, pc\n \tmul.w\tr3, r2, r3\n \trsb\tr3, r3, #0\n \tstr\tr3, [r0, #0]\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr\tr6, [sp, #0]\n \tit\teq\n \tmoveq\tr3, #0\n+\tldr.w\tr1, [r7, #396]\t@ 0x18c\n+\tit\tne\n+\tmovne\tr3, r1\n \tstr\tr3, [sp, #4]\n-\tmovs\tr3, #1\n-\tldr\tr2, [r7, #56]\t@ 0x38\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tcmp\tr2, #0\n+\tldr\tr6, [r7, #44]\t@ 0x2c\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n+\tcmp\tr6, #0\n+\tit\tne\n+\tmovne\tr3, r1\n+\tldr\tr1, [pc, #160]\t@ (8c04 <__gridxc_alloc_MOD_realloc_i2+0x63c>)\n \tit\teq\n \tmoveq\tr3, #0\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r2\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #48]\t@ 0x30\n+\tldr\tr2, [r7, #48]\t@ 0x30\n+\tadd\tr1, pc\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #40]\t@ 0x28\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tstr.w\tr8, [r5, #16]\n-\tstr.w\tr8, [r7, #48]\t@ 0x30\n-\tb.n\t8e2e <__gridxc_alloc_MOD_realloc_i2+0x1be>\n-\tmov.w\tlr, #1\n+\tstr.w\tr9, [r8, #16]\n+\tstr.w\tr9, [r7, #40]\t@ 0x28\n+\tb.n\t8766 <__gridxc_alloc_MOD_realloc_i2+0x19e>\n+\tmovs\tr6, #1\n \tcmp.w\tr8, #0\n-\tstr.w\tlr, [r7, #168]\t@ 0xa8\n+\tstr\tr6, [r7, #124]\t@ 0x7c\n \tmov.w\tr8, #0\n-\tbge.w\t8d08 <__gridxc_alloc_MOD_realloc_i2+0x98>\n+\tbge.w\t865e <__gridxc_alloc_MOD_realloc_i2+0x96>\n \tmov.w\tr9, #0\n-\tb.n\t8d10 <__gridxc_alloc_MOD_realloc_i2+0xa0>\n-\tmovs\tr2, #0\n-\tb.n\t8eaa <__gridxc_alloc_MOD_realloc_i2+0x23a>\n-\tmov.w\tlr, #1\n+\tb.n\t8664 <__gridxc_alloc_MOD_realloc_i2+0x9c>\n+\tmovs\tr6, #1\n \tmov.w\tr9, #0\n-\tb.n\t8d10 <__gridxc_alloc_MOD_realloc_i2+0xa0>\n+\tb.n\t8664 <__gridxc_alloc_MOD_realloc_i2+0x9c>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbnz\tr2, 92c6 <__gridxc_alloc_MOD_realloc_i2+0x656>\n+\tcbnz\tr2, 8bb2 <__gridxc_alloc_MOD_realloc_i2+0x5ea>\n \tadd\tr2, sp, #16\n \tldr\tr1, [r4, #24]\n-\tstr\tr2, [r7, #68]\t@ 0x44\n-\tb.n\t9084 <__gridxc_alloc_MOD_realloc_i2+0x414>\n+\tstr\tr2, [r7, #64]\t@ 0x40\n+\tb.n\t8982 <__gridxc_alloc_MOD_realloc_i2+0x3ba>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n-\tb.n\t92be <__gridxc_alloc_MOD_realloc_i2+0x64e>\n+\tb.n\t8baa <__gridxc_alloc_MOD_realloc_i2+0x5e2>\n+\tmov\tr0, r8\n+\tcmp.w\tr8, #0\n+\tbeq.w\t87f0 <__gridxc_alloc_MOD_realloc_i2+0x228>\n \tmovs\tr0, #1\n-\tcmp\tr2, #0\n-\tbne.w\t8eb8 <__gridxc_alloc_MOD_realloc_i2+0x248>\n-\tb.n\t8eb0 <__gridxc_alloc_MOD_realloc_i2+0x240>\n+\tb.n\t87f6 <__gridxc_alloc_MOD_realloc_i2+0x22e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t8ee0 <__gridxc_alloc_MOD_realloc_i2+0x270>\n+\tb.n\t8826 <__gridxc_alloc_MOD_realloc_i2+0x25e>\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t8ee0 <__gridxc_alloc_MOD_realloc_i2+0x270>\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000176\n+\tb.n\t8826 <__gridxc_alloc_MOD_realloc_i2+0x25e>\n+\t.word\t0x000005e6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000005d6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004e6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000047a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003ba\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000332\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x000002d4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000172\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000148\n+\t.word\t0x00000158\n R_ARM_REL32\t.bss\n \t.word\t0x00000102\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000c0\n+\t.word\t0x00000096\n R_ARM_REL32\t.LC29\n \n-00009314 <__gridxc_alloc_MOD_realloc_i1>:\n+00008c08 <__gridxc_alloc_MOD_realloc_i1>:\n __gridxc_alloc_MOD_realloc_i1():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3744]\t@ 0xea0\n-\tldr.w\tip, [pc, #892]\t@ 96a8 <__gridxc_alloc_MOD_realloc_i1+0x394>\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #892]\t@ (96ac <__gridxc_alloc_MOD_realloc_i1+0x398>)\n+\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n \tmov\tr4, r0\n-\tadd\tip, pc\n-\tsub\tsp, #308\t@ 0x134\n-\tldr.w\tlr, [pc, #888]\t@ 96b0 <__gridxc_alloc_MOD_realloc_i1+0x39c>\n+\tldr.w\tr0, [pc, #1100]\t@ 9068 <__gridxc_alloc_MOD_realloc_i1+0x460>\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #1096]\t@ 906c <__gridxc_alloc_MOD_realloc_i1+0x464>\n+\tadd\tr0, pc\n+\tsub\tsp, #292\t@ 0x124\n \tadd\tr7, sp, #16\n-\tmov\tr9, r2\n-\tldr.w\tr3, [ip, r3]\n-\tadd\tlr, pc\n-\tmovs\tr2, #1\n+\tldr\tr3, [r0, r3]\n+\tldr.w\tr0, [pc, #1088]\t@ 9070 <__gridxc_alloc_MOD_realloc_i1+0x468>\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n \tldr\tr3, [r4, #0]\n-\tldrd\tr6, r0, [r7, #336]\t@ 0x150\n+\tadd\tr0, pc\n+\tldr.w\tlr, [r7, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tit\teq\n-\tmoveq\tr2, #0\n-\tldr.w\tip, [r7, #344]\t@ 0x158\n-\tstr.w\tr2, [lr]\n-\tbeq.w\t9644 <__gridxc_alloc_MOD_realloc_i1+0x330>\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldrd\tr3, r2, [r4, #28]\n+\titet\teq\n+\tstreq\tr3, [r7, #12]\n+\tmovne.w\tr8, #1\n+\tmoveq.w\tr8, #0\n+\tldrd\tr6, ip, [r7, #312]\t@ 0x138\n+\tstr.w\tr8, [r0]\n+\tbeq.n\t8c82 <__gridxc_alloc_MOD_realloc_i1+0x7a>\n \tstr\tr3, [r7, #32]\n-\tstr\tr2, [r7, #24]\n-\tcmp\tr2, r3\n+\tldrd\tr3, r0, [r4, #28]\n+\tstr\tr3, [r7, #28]\n+\tstr\tr0, [r7, #20]\n+\tcmp\tr0, r3\n \tldr\tr3, [r4, #4]\n \tstr\tr3, [r7, #4]\n-\tldr\tr3, [r4, #24]\n-\tstr\tr3, [r7, #8]\n-\tldr\tr3, [r4, #20]\n-\tstr\tr3, [r7, #16]\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #28]\n \tit\tlt\n \tmovlt\tr3, #1\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tmov\tr3, r2\n-\tit\tlt\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tite\tge\n+\tmovge\tr3, r0\n \tmovlt\tr3, #0\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tldr\tr3, [r1, #0]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td18, [pc, #752]\t@ 9688 <__gridxc_alloc_MOD_realloc_i1+0x374>\n-\tvldr\td19, [pc, #756]\t@ 9690 <__gridxc_alloc_MOD_realloc_i1+0x37c>\n \tstr\tr3, [r7, #72]\t@ 0x48\n-\tldr.w\tr3, [r9]\n-\tadd.w\tfp, r7, #252\t@ 0xfc\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n-\tadd.w\tr3, r7, #108\t@ 0x6c\n-\tvldr\td17, [pc, #744]\t@ 9698 <__gridxc_alloc_MOD_realloc_i1+0x384>\n-\tadd.w\tr2, r7, #232\t@ 0xe8\n-\tvstr\td16, [r7, #96]\t@ 0x60\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #12]\n+\tldr\tr3, [r1, #0]\n \tmov.w\tr8, #1\n-\tvstr\td16, [r7, #100]\t@ 0x64\n-\tadd.w\tsl, r7, #72\t@ 0x48\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #124\t@ 0x7c\n-\tldr.w\tr9, [pc, #740]\t@ 96b4 <__gridxc_alloc_MOD_realloc_i1+0x3a0>\n-\tvstr\td16, [r7, #144]\t@ 0x90\n-\tadd.w\tr1, r7, #136\t@ 0x88\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #156\t@ 0x9c\n-\tvstr\td16, [r7, #148]\t@ 0x94\n-\tadd\tr9, pc\n-\tvstr\td16, [r7, #192]\t@ 0xc0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #172\t@ 0xac\n-\tvstr\td16, [r7, #196]\t@ 0xc4\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #204\t@ 0xcc\n-\tvstr\td16, [r7, #240]\t@ 0xf0\n-\tstr\tr2, [r7, #40]\t@ 0x28\n-\tvst1.32\t{d18-d19}, [r3]\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tmovs\tr0, #4\n+\tldr\tr3, [r2, #0]\n+\tmvn.w\tr1, #2\n+\tmovs\tr2, #2\n+\tadd.w\tr9, r7, #44\t@ 0x2c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tadd.w\tr3, r7, #220\t@ 0xdc\n-\tvstr\td16, [r7, #244]\t@ 0xf4\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #268\t@ 0x10c\n-\tvst1.32\t{d18-d19}, [fp]\n+\tstrd\tr2, r2, [r7, #108]\t@ 0x6c\n+\tadd.w\tsl, r7, #60\t@ 0x3c\n \tstr\tr3, [r7, #36]\t@ 0x24\n-\tvst1.32\t{d17}, [r3]\n-\tmvn.w\tr3, #2\n-\tstr.w\tr8, [r7, #132]\t@ 0x84\n+\tmovs\tr3, #0\n+\tstrd\tr2, r2, [r7, #156]\t@ 0x9c\n+\tstrd\tr3, r3, [r7, #84]\t@ 0x54\n \tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [r7, #132]\t@ 0x84\n \tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstrd\tr3, r3, [r7, #180]\t@ 0xb4\n \tstr.w\tr3, [r7, #188]\t@ 0xbc\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tadd.w\tr3, r7, #56\t@ 0x38\n-\tstr.w\tr8, [r7, #180]\t@ 0xb4\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\tadd.w\tr3, r7, #64\t@ 0x40\n-\tstr.w\tr8, [r7, #228]\t@ 0xe4\n-\tstr.w\tr3, [r7, #136]\t@ 0x88\n-\tadd.w\tr3, r7, #80\t@ 0x50\n-\tstr.w\tr8, [r7, #276]\t@ 0x114\n-\tstr\tr3, [r7, #28]\n-\tstr.w\tr3, [r7, #184]\t@ 0xb8\n-\tmov\tr3, r2\n-\tstr.w\tsl, [r7, #232]\t@ 0xe8\n-\tadd.w\tr2, r7, #184\t@ 0xb8\n-\tstrd\tr0, ip, [sp]\n-\tadd.w\tr0, r7, #88\t@ 0x58\n-\tbl\tf4 <__gridxc_alloc_MOD_options.constprop.0>\n+\tstr\tr0, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #144]\t@ 0x90\n+\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #76]\t@ 0x4c\n+\tadd.w\tr9, r7, #52\t@ 0x34\n+\tstrd\tr8, r8, [r7, #100]\t@ 0x64\n+\tstrd\tr8, r8, [r7, #116]\t@ 0x74\n+\tstrd\tr8, r8, [r7, #148]\t@ 0x94\n+\tstrd\tr8, r8, [r7, #164]\t@ 0xa4\n+\tstr.w\tr9, [r7, #124]\t@ 0x7c\n+\tldr.w\tr9, [pc, #896]\t@ 9074 <__gridxc_alloc_MOD_realloc_i1+0x46c>\n+\tstrd\tr1, r3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr0, [r7, #240]\t@ 0xf0\n+\tadd\tr9, pc\n+\tstr.w\tr2, [r7, #204]\t@ 0xcc\n+\tadd.w\tr0, r7, #76\t@ 0x4c\n+\tstr.w\tr2, [r7, #208]\t@ 0xd0\n+\tstr.w\tr1, [r7, #176]\t@ 0xb0\n+\tadd.w\tr1, r7, #124\t@ 0x7c\n+\tstrd\tr3, r3, [r7, #232]\t@ 0xe8\n+\tstrd\tr8, r2, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tr2, r7, #68\t@ 0x44\n+\tstr.w\tr8, [r7, #200]\t@ 0xc8\n+\tstr\tr2, [r7, #24]\n+\tstr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr2, r7, #172\t@ 0xac\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tstrd\tr8, r8, [r7, #212]\t@ 0xd4\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n+\tstrd\tr8, r8, [r7, #260]\t@ 0x104\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tstrd\tip, lr, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\tec <__gridxc_alloc_MOD_options.constprop.0>\n \tldr.w\tr3, [r9, #8]\n-\tcbz\tr3, 94d2 <__gridxc_alloc_MOD_realloc_i1+0x1be>\n-\tldr.w\tr3, [r9, #12]\n-\tstr\tr3, [r7, #20]\n-\tcmp\tr3, #0\n-\tbne.n\t950c <__gridxc_alloc_MOD_realloc_i1+0x1f8>\n-\tldr\tr2, [r7, #24]\n+\tcbz\tr3, 8dac <__gridxc_alloc_MOD_realloc_i1+0x1a4>\n+\tldr.w\tfp, [r9, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t8de2 <__gridxc_alloc_MOD_realloc_i1+0x1da>\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr1, [r7, #32]\n-\tadd.w\tr0, r7, #52\t@ 0x34\n-\tsub.w\tr3, r2, r1\n-\tldr\tr1, [pc, #548]\t@ (96b8 <__gridxc_alloc_MOD_realloc_i1+0x3a4>)\n+\tldr\tr3, [r7, #20]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n+\tldr\tr1, [pc, #780]\t@ (9078 <__gridxc_alloc_MOD_realloc_i1+0x470>)\n+\tsub.w\tr3, r3, r2\n+\tmov\tr2, r5\n \tadd\tr3, r8\n \tadd\tr1, pc\n \tbic.w\tr3, r3, r3, asr #31\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tstr.w\tr8, [sp]\n-\tmov\tr3, r6\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #4]\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #4]\n \tcmp\tr6, #0\n-\tldr.w\tr2, [r7, #352]\t@ 0x160\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n-\tmoveq\tr2, #0\n-\tstr\tr2, [sp, #8]\n-\tmov\tr2, r5\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr0, [r7, #44]\t@ 0x2c\n+\tmoveq\tr3, #0\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, r6\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #20]\n-\tstr.w\tr3, [r9, #16]\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr3, [pc, #488]\t@ (96bc <__gridxc_alloc_MOD_realloc_i1+0x3a8>)\n+\tstr.w\tfp, [r9, #16]\n+\tstr.w\tfp, [r7, #32]\n+\tldr\tr3, [pc, #716]\t@ (907c <__gridxc_alloc_MOD_realloc_i1+0x474>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tcbnz\tr3, 9516 <__gridxc_alloc_MOD_realloc_i1+0x202>\n-\tldr\tr3, [pc, #484]\t@ (96c0 <__gridxc_alloc_MOD_realloc_i1+0x3ac>)\n+\tcbnz\tr3, 8dec <__gridxc_alloc_MOD_realloc_i1+0x1e4>\n+\tldr\tr3, [pc, #712]\t@ (9080 <__gridxc_alloc_MOD_realloc_i1+0x478>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, #0\n-\tbne.w\t9648 <__gridxc_alloc_MOD_realloc_i1+0x334>\n-\tldr\tr2, [pc, #476]\t@ (96c4 <__gridxc_alloc_MOD_realloc_i1+0x3b0>)\n-\tldr\tr3, [pc, #448]\t@ (96ac <__gridxc_alloc_MOD_realloc_i1+0x398>)\n+\tbne.w\t8f00 <__gridxc_alloc_MOD_realloc_i1+0x2f8>\n+\tldr\tr2, [pc, #704]\t@ (9084 <__gridxc_alloc_MOD_realloc_i1+0x47c>)\n+\tldr\tr3, [pc, #680]\t@ (906c <__gridxc_alloc_MOD_realloc_i1+0x464>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t97fa <__gridxc_alloc_MOD_realloc_i1+0x4e6>\n-\tadd.w\tr7, r7, #292\t@ 0x124\n+\tbne.w\t9056 <__gridxc_alloc_MOD_realloc_i1+0x44e>\n+\tadd.w\tr7, r7, #276\t@ 0x114\n \tmov\tsp, r7\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr.w\tr3, [r9, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t9648 <__gridxc_alloc_MOD_realloc_i1+0x334>\n-\tvldr\td8, [r7, #56]\t@ 0x38\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbeq.w\t8f00 <__gridxc_alloc_MOD_realloc_i1+0x2f8>\n+\tldrd\tr8, r9, [r7, #44]\t@ 0x2c\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r4, #12]\n \tmovs\tr2, #4\n+\tsub.w\tr3, r9, r8\n \tstr\tr2, [r4, #8]\n \tmovw\tr2, #257\t@ 0x101\n-\tvmov.32\tr3, d8[1]\n-\tvmov\tr8, s16\n-\tvstr\td16, [r4, #12]\n \tstrh\tr2, [r4, #16]\n-\tsub.w\tr3, r3, r8\n \torr.w\tr0, r3, r3, asr #31\n \tadds\tr0, #1\n \tcmp.w\tr0, #1073741824\t@ 0x40000000\n-\tbge.w\t9804 <__gridxc_alloc_MOD_realloc_i1+0x4f0>\n+\tbge.w\t9060 <__gridxc_alloc_MOD_realloc_i1+0x458>\n \tcmp\tr3, #0\n-\trsb\tr8, r8, #0\n-\tit\tge\n+\trsb\tfp, r8, #0\n+\tite\tge\n \tlslge\tr0, r0, #2\n-\tit\tlt\n \tmovlt\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [r4, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t97fe <__gridxc_alloc_MOD_realloc_i1+0x4ea>\n-\tadd.w\tr3, r4, #28\n-\tvldr\td16, [pc, #312]\t@ 96a0 <__gridxc_alloc_MOD_realloc_i1+0x38c>\n-\tvst1.32\t{d8}, [r3]\n-\tadd.w\tr3, r4, #20\n-\tstr.w\tr8, [r4, #4]\n-\tvst1.32\t{d16}, [r3]\n+\tbeq.w\t905a <__gridxc_alloc_MOD_realloc_i1+0x452>\n+\tmovs\tr3, #4\n+\tmovs\tr2, #1\n+\tstrd\tr3, r2, [r4, #20]\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #332]\t@ (96c8 <__gridxc_alloc_MOD_realloc_i1+0x3b4>)\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tstrd\tr8, r9, [r4, #28]\n+\tstr.w\tfp, [r4, #4]\n+\tldr\tr0, [pc, #584]\t@ (9088 <__gridxc_alloc_MOD_realloc_i1+0x480>)\n \tcmp\tr5, #0\n+\tstr.w\tsl, [r7, #220]\t@ 0xdc\n+\tmov.w\tr8, #0\n \tadd\tr0, pc\n-\tvldr\td16, [pc, #272]\t@ 9698 <__gridxc_alloc_MOD_realloc_i1+0x384>\n-\tvldr\td18, [pc, #252]\t@ 9688 <__gridxc_alloc_MOD_realloc_i1+0x374>\n-\tvldr\td19, [pc, #256]\t@ 9690 <__gridxc_alloc_MOD_realloc_i1+0x37c>\n-\tvstr\td17, [r7, #244]\t@ 0xf4\n-\tstr.w\tr3, [r0, #16]!\n-\tmov.w\tr8, #1\n-\tldr.w\tr3, [r7, #348]\t@ 0x15c\n \tit\teq\n-\tmoveq\tr3, #0\n-\tstr.w\tsl, [r7, #232]\t@ 0xe8\n-\tcmp\tr6, #0\n-\tvst1.32\t{d18-d19}, [fp]\n-\tmov\tr9, r3\n-\tmov.w\tr3, #4\n-\tvst1.32\t{d16}, [r2]\n+\tmoveq.w\tsl, #0\n+\tmov.w\tr9, #1\n+\tstrd\tr8, r8, [r7, #232]\t@ 0xe8\n+\tstrd\tr9, r9, [r7, #244]\t@ 0xf4\n+\tmov\tr2, r6\n+\tstr.w\tr3, [r0, #16]!\n \tmov\tr1, r5\n+\tldr.w\tr3, [r7, #324]\t@ 0x144\n+\tstrd\tr9, r9, [r7, #260]\t@ 0x104\n+\tit\tne\n+\tmovne\tsl, r3\n+\tmovs\tr3, #4\n \tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tcmp\tr6, #0\n+\tstr.w\tr3, [r7, #228]\t@ 0xe4\n+\tmov.w\tr3, #2\n+\tstrd\tr3, r3, [r7, #252]\t@ 0xfc\n+\tit\teq\n+\tmoveq\tfp, r8\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n+\tit\tne\n+\tmovne\tfp, r3\n \tmov.w\tr3, #258\t@ 0x102\n-\tstr.w\tr8, [r7, #276]\t@ 0x114\n-\tmov\tr2, r6\n-\tstrh.w\tr3, [r7, #248]\t@ 0xf8\n+\tstrh.w\tr3, [r7, #236]\t@ 0xec\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tstr.w\tr9, [sp]\n-\tldr.w\tr3, [r7, #352]\t@ 0x160\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tstr\tr3, [sp, #4]\n-\tmov\tsl, r3\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tldr\tr1, [pc, #220]\t@ (96cc <__gridxc_alloc_MOD_realloc_i1+0x3b8>)\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstrd\tsl, fp, [sp]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tldr\tr1, [pc, #480]\t@ (908c <__gridxc_alloc_MOD_realloc_i1+0x484>)\n \tldrd\tr2, r3, [r4, #28]\n-\tadd.w\tr0, r7, #52\t@ 0x34\n \tadd\tr1, pc\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsubs\tr3, r3, r2\n \tmov\tr2, r5\n-\tadd\tr3, r8\n+\tadd\tr3, r9\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r7, #40]\t@ 0x28\n \tmov\tr3, r6\n-\tstrd\tr9, sl, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr.w\tip, [r4, #24]\n-\tldrd\tr3, r0, [r4, #28]\n-\tldrd\tlr, r2, [r4]\n-\tcmp\tr3, r0\n-\tbgt.w\t94da <__gridxc_alloc_MOD_realloc_i1+0x1c6>\n-\tadd\tr0, r8\n-\tmovs\tr1, #0\n-\tmla\tr2, ip, r3, r2\n-\tsubs\tr0, r0, r3\n-\tmov\tr8, r1\n+\tstrd\tsl, fp, [sp, #4]\n+\tstr.w\tr9, [sp]\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr0, [r4, #24]\n+\tldrd\tr3, r1, [r4, #28]\n+\tldrd\tip, r2, [r4]\n+\tcmp\tr3, r1\n+\tbgt.w\t8db4 <__gridxc_alloc_MOD_realloc_i1+0x1ac>\n+\tadd\tr1, r9\n+\tmla\tr2, r0, r3, r2\n+\tsubs\tr1, r1, r3\n+\tmov\tlr, r8\n \tldr\tr3, [r4, #20]\n-\tadds\tr1, #1\n-\tcmp\tr0, r1\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr1, r8\n \tmul.w\tr3, r2, r3\n-\tadd\tr2, ip\n-\tstr.w\tr8, [lr, r3]\n-\tbne.n\t9630 <__gridxc_alloc_MOD_realloc_i1+0x31c>\n-\tb.n\t94da <__gridxc_alloc_MOD_realloc_i1+0x1c6>\n-\tstr\tr3, [r7, #16]\n-\tb.n\t9390 <__gridxc_alloc_MOD_realloc_i1+0x7c>\n-\tldrd\tr0, r3, [r7, #64]\t@ 0x40\n-\tstr.w\tsp, [r7, #20]\n-\tsubs\tr3, r3, r0\n-\tbmi.n\t973a <__gridxc_alloc_MOD_realloc_i1+0x426>\n+\tadd\tr2, r0\n+\tstr.w\tlr, [ip, r3]\n+\tbne.n\t8eea <__gridxc_alloc_MOD_realloc_i1+0x2e2>\n+\tb.n\t8db4 <__gridxc_alloc_MOD_realloc_i1+0x1ac>\n+\tldrd\tfp, r3, [r7, #52]\t@ 0x34\n+\tstr.w\tsp, [r7, #16]\n+\tsubs.w\tr3, r3, fp\n+\tbmi.n\t8fa0 <__gridxc_alloc_MOD_realloc_i1+0x398>\n \tlsls\tr2, r3, #2\n \tldr.w\tr9, [r4]\n \tadds\tr2, #11\n+\tldr\tr0, [r4, #4]\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n-\tsub.w\tip, sp, r1\n-\tldr\tr1, [r4, #4]\n-\tstr\tr1, [r7, #12]\n-\tmov\tr1, ip\n+\tsub.w\tr1, sp, r1\n \tmov\tip, sp\n \tcmp\tip, r1\n-\tbeq.n\t96d0 <__gridxc_alloc_MOD_realloc_i1+0x3bc>\n+\tbeq.n\t8f38 <__gridxc_alloc_MOD_realloc_i1+0x330>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t9672 <__gridxc_alloc_MOD_realloc_i1+0x35e>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000372\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000036a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ca\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000021e\n- R_ARM_REL32\t.LC29\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001d6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000140\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000d2\n- R_ARM_REL32\t.LC29\n+\tb.n\t8f28 <__gridxc_alloc_MOD_realloc_i1+0x320>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 96e0 <__gridxc_alloc_MOD_realloc_i1+0x3cc>\n+\tcbz\tr2, 8f48 <__gridxc_alloc_MOD_realloc_i1+0x340>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tldrd\tr1, r2, [r7, #4]\n \tmov.w\tlr, #0\n \tldr.w\tr8, [r4, #24]\n-\tmla\tip, r0, r2, r1\n-\tldr\tr1, [r7, #16]\n+\tmla\tip, fp, r2, r1\n+\tldr\tr1, [r7, #12]\n \tmul.w\tsl, r1, r2\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n+\tldr\tr2, [r7, #32]\n \tmla\tip, r1, ip, r2\n \tadd\tr2, sp, #12\n \tmov\tr1, r2\n-\tstr\tr2, [r7, #16]\n+\tstr\tr2, [r7, #12]\n \tldr.w\tr2, [ip]\n \tadd.w\tlr, lr, #1\n \tadd\tip, sl\n-\tcmp\tlr, r3\n+\tcmp\tr3, lr\n \tstr.w\tr2, [r1, #4]!\n-\tble.n\t9702 <__gridxc_alloc_MOD_realloc_i1+0x3ee>\n-\tldrd\tr1, r2, [r7, #12]\n-\tmov\tlr, r5\n-\tmla\tip, r0, r8, r1\n+\tbge.n\t8f6a <__gridxc_alloc_MOD_realloc_i1+0x362>\n+\tldr\tr2, [r7, #12]\n+\tmla\tip, fp, r8, r0\n \tmovs\tr1, #0\n+\tmov\tlr, r5\n \tldr\tr0, [r4, #20]\n-\tcmp\tr3, r1\n+\tcmp\tr1, r3\n \tldr.w\tr5, [r2, #4]!\n \tadd.w\tr1, r1, #1\n \tmul.w\tr0, r0, ip\n \tadd\tip, r8\n \tstr.w\tr5, [r9, r0]\n-\tbne.n\t9720 <__gridxc_alloc_MOD_realloc_i1+0x40c>\n+\tbne.n\t8f86 <__gridxc_alloc_MOD_realloc_i1+0x37e>\n \tmov\tr5, lr\n-\tldr\tr2, [r7, #32]\n+\tldr\tr2, [r7, #28]\n \tcmp\tr5, #0\n-\tldr\tr3, [r7, #24]\n+\tldr\tr3, [r7, #20]\n \tmov.w\tr4, #1\n-\tldr.w\tsp, [r7, #20]\n-\tadd.w\tr0, r7, #52\t@ 0x34\n+\tldr.w\tsp, [r7, #16]\n+\tadd.w\tr0, r7, #40\t@ 0x28\n \tsub.w\tr3, r3, r2\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tadd.w\tr3, r3, #1\n \tit\teq\n \tmoveq\tr2, #0\n \tcmp\tr6, #0\n-\tstr.w\tr2, [r7, #348]\t@ 0x15c\n+\tstr.w\tr2, [r7, #324]\t@ 0x144\n \tbic.w\tr3, r3, r3, asr #31\n-\tldr\tr1, [pc, #192]\t@ (9828 <__gridxc_alloc_MOD_realloc_i1+0x514>)\n+\tldr\tr1, [pc, #192]\t@ (9090 <__gridxc_alloc_MOD_realloc_i1+0x488>)\n \trsb\tr3, r3, #0\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tldr.w\tr3, [r7, #352]\t@ 0x160\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tit\teq\n \tmoveq\tr3, #0\n-\tstr.w\tr3, [r7, #352]\t@ 0x160\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n \tadd\tr1, pc\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r5\n-\tldr.w\tr3, [r7, #352]\t@ 0x160\n+\tldr.w\tr3, [r7, #328]\t@ 0x148\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r6\n \tstr\tr4, [sp, #0]\n-\tbl\teb8 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tcbz\tr3, 979a <__gridxc_alloc_MOD_realloc_i1+0x486>\n+\tbl\te50 <__gridxc_alloc_MOD_alloc_count.constprop.0>\n+\tldr\tr3, [r7, #32]\n+\tcbz\tr3, 9000 <__gridxc_alloc_MOD_realloc_i1+0x3f8>\n \tmovs\tr4, #0\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [r7, #28]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [pc, #136]\t@ (982c <__gridxc_alloc_MOD_realloc_i1+0x518>)\n-\tmov\tr2, r6\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr0, [pc, #144]\t@ (9094 <__gridxc_alloc_MOD_realloc_i1+0x48c>)\n \tmov\tr1, r5\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #24]\n+\tmovs\tr5, #0\n \tadd\tr0, pc\n-\tvldr\td18, [pc, #96]\t@ 9810 <__gridxc_alloc_MOD_realloc_i1+0x4fc>\n-\tvldr\td19, [pc, #100]\t@ 9818 <__gridxc_alloc_MOD_realloc_i1+0x504>\n-\tvldr\td17, [pc, #104]\t@ 9820 <__gridxc_alloc_MOD_realloc_i1+0x50c>\n+\tstrd\tr5, r5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tmov\tr2, r6\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tstr.w\tr4, [r0, #16]!\n+\tmovs\tr4, #1\n+\tstrd\tr4, r4, [r7, #244]\t@ 0xf4\n+\tstrd\tr4, r4, [r7, #260]\t@ 0x104\n \tmovs\tr4, #4\n-\tvst1.32\t{d18-d19}, [fp]\n-\tvst1.32\t{d17}, [r3]\n \tstr.w\tr4, [r7, #240]\t@ 0xf0\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tmovs\tr4, #2\n+\tstrd\tr4, r4, [r7, #252]\t@ 0xfc\n \tmov.w\tr4, #258\t@ 0x102\n-\tvstr\td16, [r7, #244]\t@ 0xf4\n-\tstrh.w\tr4, [r7, #248]\t@ 0xf8\n-\tmovs\tr4, #1\n-\tstr.w\tr4, [r7, #276]\t@ 0x114\n+\tstrh.w\tr4, [r7, #236]\t@ 0xec\n \tmvn.w\tr4, #2\n-\tstr.w\tr4, [r7, #236]\t@ 0xec\n-\tldr.w\tr4, [r7, #352]\t@ 0x160\n-\tldr\tr3, [r7, #40]\t@ 0x28\n+\tstr.w\tr4, [r7, #224]\t@ 0xe0\n+\tldr.w\tr4, [r7, #328]\t@ 0x148\n \tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #348]\t@ 0x15c\n+\tldr.w\tr4, [r7, #324]\t@ 0x144\n \tstr\tr4, [sp, #0]\n-\tbl\t9c4 <__gridxc_alloc_MOD_alloc_err.constprop.1>\n-\tb.n\t94e6 <__gridxc_alloc_MOD_realloc_i1+0x1d2>\n+\tbl\t98c <__gridxc_alloc_MOD_alloc_err.constprop.1>\n+\tb.n\t8dc0 <__gridxc_alloc_MOD_realloc_i1+0x1b8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tmovw\tr3, #5020\t@ 0x139c\n-\tb.n\t957a <__gridxc_alloc_MOD_realloc_i1+0x266>\n+\tb.n\t8e3c <__gridxc_alloc_MOD_realloc_i1+0x234>\n \tmovw\tr3, #5014\t@ 0x1396\n-\tb.n\t957a <__gridxc_alloc_MOD_realloc_i1+0x266>\n+\tb.n\t8e3c <__gridxc_alloc_MOD_realloc_i1+0x234>\n \tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x000000aa\n+\t.word\t0x00000440\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000430\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000374\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000302\n R_ARM_REL32\t.LC29\n-\t.word\t0x0000007c\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002bc\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000023c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001d8\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x000000ac\n+ R_ARM_REL32\t.LC29\n+\t.word\t0x00000088\n R_ARM_REL32\t.bss\n \n-00009830 <__gridxc_alloc_MOD_alloc_default>:\n+00009098 <__gridxc_alloc_MOD_alloc_default>:\n __gridxc_alloc_MOD_alloc_default():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #68\t@ 0x44\n-\tmov\tr9, r2\n-\tldr\tr2, [pc, #436]\t@ (99fc <__gridxc_alloc_MOD_alloc_default+0x1cc>)\n \tmov\tr7, r3\n-\tldr\tr3, [pc, #436]\t@ (9a00 <__gridxc_alloc_MOD_alloc_default+0x1d0>)\n+\tldr\tr3, [pc, #440]\t@ (9268 <__gridxc_alloc_MOD_alloc_default+0x1d0>)\n+\tstr\tr2, [sp, #0]\n+\tldr\tr2, [pc, #440]\t@ (926c <__gridxc_alloc_MOD_alloc_default+0x1d4>)\n \tldr\tr4, [sp, #104]\t@ 0x68\n \tadd\tr2, pc\n-\tstr\tr4, [sp, #0]\n+\tstr\tr4, [sp, #4]\n+\tldr.w\tfp, [sp, #112]\t@ 0x70\n \tmov\tr4, r1\n-\tldr.w\tsl, [sp, #112]\t@ 0x70\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #60]\t@ 0x3c\n \tmov.w\tr3, #0\n \tldr\tr3, [sp, #108]\t@ 0x6c\n-\tstr\tr3, [sp, #4]\n+\tstr\tr3, [sp, #8]\n \tcmp\tr0, #0\n-\tbeq.w\t99b2 <__gridxc_alloc_MOD_alloc_default+0x182>\n-\tldr.w\tfp, [pc, #408]\t@ 9a04 <__gridxc_alloc_MOD_alloc_default+0x1d4>\n-\tadd\tr3, sp, #28\n+\tbeq.w\t9216 <__gridxc_alloc_MOD_alloc_default+0x17e>\n+\tldr.w\tsl, [pc, #412]\t@ 9270 <__gridxc_alloc_MOD_alloc_default+0x1d8>\n \tadd\tr5, sp, #16\n-\tstr\tr3, [sp, #12]\n-\tadd\tfp, pc\n-\tstr\tr5, [sp, #8]\n-\tmov\tr6, fp\n-\tmov\tr8, r3\n+\tstr\tr5, [sp, #12]\n \tmov\tlr, r0\n+\tadd\tsl, pc\n \tmov\tip, r0\n-\tvmov.i32\td16, #1\t@ 0x00000001\n+\tmov\tr6, sl\n+\tadd.w\tr9, sp, #28\n+\tmov\tr8, r9\n+\tvldr\td7, [pc, #372]\t@ 9260 <__gridxc_alloc_MOD_alloc_default+0x1c8>\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia.w\tr8!, {r0, r1, r2, r3}\n \tldmia.w\tr6, {r0, r1, r2, r3}\n \tstmia.w\tr8, {r0, r1, r2, r3}\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #24]\n-\tvstr\td16, [sp, #16]\n+\tvstr\td7, [sp, #16]\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tlr, {r0, r1, r2}\n-\tcbz\tr4, 98e2 <__gridxc_alloc_MOD_alloc_default+0xb2>\n-\tldrd\tr5, r8, [sp, #8]\n-\tmov\tlr, r4\n-\tldmia.w\tfp!, {r0, r1, r2, r3}\n-\tstmia.w\tr8!, {r0, r1, r2, r3}\n+\tcbz\tr4, 9148 <__gridxc_alloc_MOD_alloc_default+0xb0>\n+\tldmia.w\tsl!, {r0, r1, r2, r3}\n+\tstmia.w\tr9!, {r0, r1, r2, r3}\n+\tldr\tr5, [sp, #12]\n \tldmia.w\tr6, {r0, r1, r2, r3}\n-\tstmia.w\tr8, {r0, r1, r2, r3}\n+\tstmia.w\tr9, {r0, r1, r2, r3}\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #24]\n-\tvstr\td16, [sp, #16]\n+\tmov\tlr, r4\n+\tvstr\td7, [sp, #16]\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tlr, {r0, r1, r2}\n-\tldr\tr5, [pc, #292]\t@ (9a08 <__gridxc_alloc_MOD_alloc_default+0x1d8>)\n+\tldr\tr5, [pc, #296]\t@ (9274 <__gridxc_alloc_MOD_alloc_default+0x1dc>)\n \tadd\tr5, pc\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tip!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia.w\tip!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tip, {r0, r1, r2}\n-\tcmp.w\tr9, #0\n-\tbeq.n\t9916 <__gridxc_alloc_MOD_alloc_default+0xe6>\n-\tmov\tr6, r9\n-\tldr\tr5, [pc, #264]\t@ (9a0c <__gridxc_alloc_MOD_alloc_default+0x1dc>)\n+\tldr\tr3, [sp, #0]\n+\tcbz\tr3, 917a <__gridxc_alloc_MOD_alloc_default+0xe2>\n+\tmov\tr6, r3\n+\tldr\tr5, [pc, #272]\t@ (9278 <__gridxc_alloc_MOD_alloc_default+0x1e0>)\n \tadd\tr5, pc\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tr6, {r0, r1, r2}\n \tstmia.w\tr5, {r0, r1, r2}\n-\tldr\tr3, [sp, #0]\n-\tcbz\tr3, 9922 <__gridxc_alloc_MOD_alloc_default+0xf2>\n+\tldr\tr3, [sp, #4]\n+\tcbz\tr3, 9186 <__gridxc_alloc_MOD_alloc_default+0xee>\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [pc, #240]\t@ (9a10 <__gridxc_alloc_MOD_alloc_default+0x1e0>)\n+\tldr\tr3, [pc, #248]\t@ (927c <__gridxc_alloc_MOD_alloc_default+0x1e4>)\n \tadd\tr3, pc\n \tstr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #4]\n-\tcbz\tr3, 992e <__gridxc_alloc_MOD_alloc_default+0xfe>\n+\tldr\tr3, [sp, #8]\n+\tcbz\tr3, 9192 <__gridxc_alloc_MOD_alloc_default+0xfa>\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [pc, #232]\t@ (9a14 <__gridxc_alloc_MOD_alloc_default+0x1e4>)\n+\tldr\tr3, [pc, #240]\t@ (9280 <__gridxc_alloc_MOD_alloc_default+0x1e8>)\n \tadd\tr3, pc\n \tstr\tr2, [r3, #4]\n-\tcmp.w\tsl, #0\n-\tbeq.n\t993e <__gridxc_alloc_MOD_alloc_default+0x10e>\n-\tldr\tr3, [pc, #224]\t@ (9a18 <__gridxc_alloc_MOD_alloc_default+0x1e8>)\n-\tldr.w\tr2, [sl]\n+\tcmp.w\tfp, #0\n+\tbeq.n\t91a2 <__gridxc_alloc_MOD_alloc_default+0x10a>\n+\tldr\tr3, [pc, #232]\t@ (9284 <__gridxc_alloc_MOD_alloc_default+0x1ec>)\n+\tldr.w\tr2, [fp]\n \tadd\tr3, pc\n \tstr\tr2, [r3, #8]\n-\tcbz\tr7, 9960 <__gridxc_alloc_MOD_alloc_default+0x130>\n+\tcbz\tr7, 91c4 <__gridxc_alloc_MOD_alloc_default+0x12c>\n \tldr\tr3, [sp, #116]\t@ 0x74\n \tcmp\tr3, #31\n-\tble.n\t9990 <__gridxc_alloc_MOD_alloc_default+0x160>\n-\tldr\tr5, [pc, #212]\t@ (9a1c <__gridxc_alloc_MOD_alloc_default+0x1ec>)\n+\tble.n\t91f4 <__gridxc_alloc_MOD_alloc_default+0x15c>\n+\tldr\tr5, [pc, #220]\t@ (9288 <__gridxc_alloc_MOD_alloc_default+0x1f0>)\n \tldr\tr0, [r7, #0]\n \tadd\tr5, pc\n \tldr\tr1, [r7, #4]\n \tadds\tr5, #12\n \tldr\tr2, [r7, #8]\n \tldr\tr3, [r7, #12]\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldr\tr0, [r7, #16]\n \tldr\tr1, [r7, #20]\n \tldr\tr2, [r7, #24]\n \tldr\tr3, [r7, #28]\n \tstmia\tr5!, {r0, r1, r2, r3}\n-\tcbz\tr4, 9976 <__gridxc_alloc_MOD_alloc_default+0x146>\n-\tldr\tr5, [pc, #188]\t@ (9a20 <__gridxc_alloc_MOD_alloc_default+0x1f0>)\n+\tcbz\tr4, 91da <__gridxc_alloc_MOD_alloc_default+0x142>\n+\tldr\tr5, [pc, #196]\t@ (928c <__gridxc_alloc_MOD_alloc_default+0x1f4>)\n \tadd\tr5, pc\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia\tr5!, {r0, r1, r2, r3}\n \tstmia\tr4!, {r0, r1, r2, r3}\n \tldmia.w\tr5, {r0, r1, r2}\n \tstmia.w\tr4, {r0, r1, r2}\n-\tldr\tr2, [pc, #172]\t@ (9a24 <__gridxc_alloc_MOD_alloc_default+0x1f4>)\n-\tldr\tr3, [pc, #132]\t@ (9a00 <__gridxc_alloc_MOD_alloc_default+0x1d0>)\n+\tldr\tr2, [pc, #180]\t@ (9290 <__gridxc_alloc_MOD_alloc_default+0x1f8>)\n+\tldr\tr3, [pc, #136]\t@ (9268 <__gridxc_alloc_MOD_alloc_default+0x1d0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t99f6 <__gridxc_alloc_MOD_alloc_default+0x1c6>\n+\tbne.n\t925a <__gridxc_alloc_MOD_alloc_default+0x1c2>\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov\tr2, r3\n-\tldr\tr3, [pc, #148]\t@ (9a28 <__gridxc_alloc_MOD_alloc_default+0x1f8>)\n+\tldr\tr3, [pc, #156]\t@ (9294 <__gridxc_alloc_MOD_alloc_default+0x1fc>)\n \tmov\tr1, r7\n \tadd\tr3, pc\n \tadds\tr3, #12\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr2, [sp, #116]\t@ 0x74\n \tmov\tr3, r0\n \tldr\tr0, [sp, #116]\t@ 0x74\n \tmovs\tr1, #32\n \tsubs\tr2, r1, r2\n \tadds\tr0, r3, r0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tb.n\t9960 <__gridxc_alloc_MOD_alloc_default+0x130>\n+\tb.n\t91c4 <__gridxc_alloc_MOD_alloc_default+0x12c>\n \tcmp\tr1, #0\n-\tbeq.n\t98fa <__gridxc_alloc_MOD_alloc_default+0xca>\n-\tldr.w\tlr, [pc, #116]\t@ 9a2c <__gridxc_alloc_MOD_alloc_default+0x1fc>\n+\tbeq.n\t9160 <__gridxc_alloc_MOD_alloc_default+0xc8>\n+\tldr.w\tlr, [pc, #124]\t@ 9298 <__gridxc_alloc_MOD_alloc_default+0x200>\n \tmov\tr5, r1\n \tadd.w\tip, sp, #28\n-\tvmov.i32\td16, #1\t@ 0x00000001\n-\tadd\tlr, pc\n \tadd\tr6, sp, #16\n+\tadd\tlr, pc\n+\tvldr\td7, [pc, #52]\t@ 9260 <__gridxc_alloc_MOD_alloc_default+0x1c8>\n \tmov.w\tr8, #1\n \tldmia.w\tlr!, {r0, r1, r2, r3}\n \tstmia.w\tip!, {r0, r1, r2, r3}\n \tldmia.w\tlr, {r0, r1, r2, r3}\n \tstmia.w\tip, {r0, r1, r2, r3}\n \tstr.w\tr8, [sp, #24]\n-\tvstr\td16, [sp, #16]\n+\tvstr\td7, [sp, #16]\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia\tr6!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldmia.w\tr6, {r0, r1, r2}\n \tstmia.w\tr5, {r0, r1, r2}\n-\tb.n\t98fa <__gridxc_alloc_MOD_alloc_default+0xca>\n+\tb.n\t9160 <__gridxc_alloc_MOD_alloc_default+0xc8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x000001ac\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000001\n+\t.word\t0x00000001\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000018c\n+\t.word\t0x000001b4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000190\n R_ARM_REL32\t.LC30\n-\t.word\t0x00000120\n+\t.word\t0x00000126\n R_ARM_REL32\t.data\n-\t.word\t0x00000104\n+\t.word\t0x0000010c\n R_ARM_REL32\t.data\n-\t.word\t0x000000ee\n+\t.word\t0x000000f6\n R_ARM_REL32\t.data\n-\t.word\t0x000000e6\n+\t.word\t0x000000ee\n R_ARM_REL32\t.data\n-\t.word\t0x000000da\n+\t.word\t0x000000e2\n R_ARM_REL32\t.data\n-\t.word\t0x000000ce\n+\t.word\t0x000000d6\n R_ARM_REL32\t.data\n-\t.word\t0x000000b8\n+\t.word\t0x000000c0\n R_ARM_REL32\t.data\n-\t.word\t0x000000a6\n+\t.word\t0x000000ae\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000008e\n+\t.word\t0x00000096\n R_ARM_REL32\t.data\n-\t.word\t0x00000064\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC30\n \n-00009a30 <__gridxc_alloc_MOD_set_alloc_error_handler>:\n+0000929c <__gridxc_alloc_MOD_set_alloc_error_handler>:\n __gridxc_alloc_MOD_set_alloc_error_handler():\n-\tldr\tr3, [pc, #4]\t@ (9a38 <__gridxc_alloc_MOD_set_alloc_error_handler+0x8>)\n+\tldr\tr3, [pc, #4]\t@ (92a4 <__gridxc_alloc_MOD_set_alloc_error_handler+0x8>)\n \tadd\tr3, pc\n \tstr\tr0, [r3, #0]\n \tbx\tlr\n \t.word\t0x00000002\n R_ARM_REL32\t.data.rel.local\n \n-00009a3c <__gridxc_alloc_MOD_set_alloc_event_handler>:\n+000092a8 <__gridxc_alloc_MOD_set_alloc_event_handler>:\n __gridxc_alloc_MOD_set_alloc_event_handler():\n-\tldr\tr3, [pc, #4]\t@ (9a44 <__gridxc_alloc_MOD_set_alloc_event_handler+0x8>)\n+\tldr\tr3, [pc, #4]\t@ (92b0 <__gridxc_alloc_MOD_set_alloc_event_handler+0x8>)\n \tadd\tr3, pc\n \tstr\tr0, [r3, #4]\n \tbx\tlr\n \t.word\t0x00000002\n R_ARM_REL32\t.data.rel.local\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -85,71 +85,72 @@\n 0x00000520 5f646561 6c6c6f63 5f693300 5f5f6772 _dealloc_i3.__gr\n 0x00000530 69647863 5f616c6c 6f635f4d 4f445f64 idxc_alloc_MOD_d\n 0x00000540 65616c6c 6f635f69 32005f5f 67726964 ealloc_i2.__grid\n 0x00000550 78635f61 6c6c6f63 5f4d4f44 5f646561 xc_alloc_MOD_dea\n 0x00000560 6c6c6f63 5f693100 5f5f6772 69647863 lloc_i1.__gridxc\n 0x00000570 5f616c6c 6f635f4d 4f445f72 65616c6c _alloc_MOD_reall\n 0x00000580 6f635f73 31006d65 6d6d6f76 65005f5f oc_s1.memmove.__\n- 0x00000590 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x000005a0 5f726561 6c6c6f63 5f6c3300 5f5f6772 _realloc_l3.__gr\n- 0x000005b0 69647863 5f616c6c 6f635f4d 4f445f72 idxc_alloc_MOD_r\n- 0x000005c0 65616c6c 6f635f6c 32005f5f 67726964 ealloc_l2.__grid\n- 0x000005d0 78635f61 6c6c6f63 5f4d4f44 5f726561 xc_alloc_MOD_rea\n- 0x000005e0 6c6c6f63 5f6c3100 5f5f6772 69647863 lloc_l1.__gridxc\n- 0x000005f0 5f616c6c 6f635f4d 4f445f72 65616c6c _alloc_MOD_reall\n- 0x00000600 6f635f7a 32005f5f 67726964 78635f61 oc_z2.__gridxc_a\n- 0x00000610 6c6c6f63 5f4d4f44 5f726561 6c6c6f63 lloc_MOD_realloc\n- 0x00000620 5f7a3100 5f5f6772 69647863 5f616c6c _z1.__gridxc_all\n- 0x00000630 6f635f4d 4f445f72 65616c6c 6f635f64 oc_MOD_realloc_d\n- 0x00000640 34005f5f 67726964 78635f61 6c6c6f63 4.__gridxc_alloc\n- 0x00000650 5f4d4f44 5f726561 6c6c6f63 5f643300 _MOD_realloc_d3.\n- 0x00000660 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000670 4f445f72 65616c6c 6f635f64 32005f5f OD_realloc_d2.__\n- 0x00000680 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x00000690 5f726561 6c6c6f63 5f643100 5f5f6772 _realloc_d1.__gr\n- 0x000006a0 69647863 5f616c6c 6f635f4d 4f445f72 idxc_alloc_MOD_r\n- 0x000006b0 65616c6c 6f635f72 34005f5f 67726964 ealloc_r4.__grid\n- 0x000006c0 78635f61 6c6c6f63 5f4d4f44 5f726561 xc_alloc_MOD_rea\n- 0x000006d0 6c6c6f63 5f723300 5f5f6772 69647863 lloc_r3.__gridxc\n- 0x000006e0 5f616c6c 6f635f4d 4f445f72 65616c6c _alloc_MOD_reall\n- 0x000006f0 6f635f72 32005f5f 67726964 78635f61 oc_r2.__gridxc_a\n- 0x00000700 6c6c6f63 5f4d4f44 5f726561 6c6c6f63 lloc_MOD_realloc\n- 0x00000710 5f723100 5f5f6772 69647863 5f616c6c _r1.__gridxc_all\n- 0x00000720 6f635f4d 4f445f72 65616c6c 6f635f65 oc_MOD_realloc_e\n- 0x00000730 31005f5f 67726964 78635f61 6c6c6f63 1.__gridxc_alloc\n- 0x00000740 5f4d4f44 5f726561 6c6c6f63 5f693300 _MOD_realloc_i3.\n- 0x00000750 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000760 4f445f72 65616c6c 6f635f69 32005f5f OD_realloc_i2.__\n- 0x00000770 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x00000780 5f726561 6c6c6f63 5f693100 5f5f6772 _realloc_i1.__gr\n- 0x00000790 69647863 5f616c6c 6f635f4d 4f445f61 idxc_alloc_MOD_a\n- 0x000007a0 6c6c6f63 5f646566 61756c74 005f5f67 lloc_default.__g\n- 0x000007b0 72696478 635f616c 6c6f635f 4d4f445f ridxc_alloc_MOD_\n- 0x000007c0 7365745f 616c6c6f 635f6572 726f725f set_alloc_error_\n- 0x000007d0 68616e64 6c657200 5f5f6772 69647863 handler.__gridxc\n- 0x000007e0 5f616c6c 6f635f4d 4f445f73 65745f61 _alloc_MOD_set_a\n- 0x000007f0 6c6c6f63 5f657665 6e745f68 616e646c lloc_event_handl\n- 0x00000800 6572005f 5f677269 6478635f 616c6c6f er.__gridxc_allo\n- 0x00000810 635f4d4f 445f6e65 6564735f 6465616c c_MOD_needs_deal\n- 0x00000820 6c6f6300 5f5f6772 69647863 5f616c6c loc.__gridxc_all\n- 0x00000830 6f635f4d 4f445f6e 65656473 5f636f70 oc_MOD_needs_cop\n- 0x00000840 79005f5f 67726964 78635f61 6c6c6f63 y.__gridxc_alloc\n- 0x00000850 5f4d4f44 5f6e6565 64735f61 6c6c6f63 _MOD_needs_alloc\n- 0x00000860 005f5f67 72696478 635f616c 6c6f635f .__gridxc_alloc_\n- 0x00000870 4d4f445f 69657272 005f5f67 72696478 MOD_ierr.__gridx\n- 0x00000880 635f616c 6c6f635f 4d4f445f 64656661 c_alloc_MOD_defa\n- 0x00000890 756c7400 5f5f6772 69647863 5f616c6c ult.__gridxc_all\n- 0x000008a0 6f635f4d 4f445f61 73736f63 69617465 oc_MOD_associate\n- 0x000008b0 645f6172 72617900 5f5f6772 69647863 d_array.__gridxc\n- 0x000008c0 5f616c6c 6f635f4d 4f445f61 6c6c6f63 _alloc_MOD_alloc\n- 0x000008d0 5f6d656d 6f72795f 6576656e 74005f5f _memory_event.__\n- 0x000008e0 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x000008f0 5f616c6c 6f635f65 72726f72 5f726570 _alloc_error_rep\n- 0x00000900 6f727400 5f5f6772 69647863 5f616c6c ort.__gridxc_all\n- 0x00000910 6f635f4d 4f445f5f 5f767461 625f6772 oc_MOD___vtab_gr\n- 0x00000920 69647863 5f616c6c 6f635f41 6c6c6f63 idxc_alloc_Alloc\n- 0x00000930 64656661 756c7473 005f5f67 72696478 defaults.__gridx\n- 0x00000940 635f616c 6c6f635f 4d4f445f 5f5f6465 c_alloc_MOD___de\n- 0x00000950 665f696e 69745f67 72696478 635f616c f_init_gridxc_al\n- 0x00000960 6c6f635f 416c6c6f 63646566 61756c74 loc_Allocdefault\n- 0x00000970 7300 s.\n+ 0x00000590 61656162 695f7569 64697600 5f5f6165 aeabi_uidiv.__ae\n+ 0x000005a0 6162695f 69646976 005f5f67 72696478 abi_idiv.__gridx\n+ 0x000005b0 635f616c 6c6f635f 4d4f445f 7265616c c_alloc_MOD_real\n+ 0x000005c0 6c6f635f 6c33005f 5f677269 6478635f loc_l3.__gridxc_\n+ 0x000005d0 616c6c6f 635f4d4f 445f7265 616c6c6f alloc_MOD_reallo\n+ 0x000005e0 635f6c32 005f5f67 72696478 635f616c c_l2.__gridxc_al\n+ 0x000005f0 6c6f635f 4d4f445f 7265616c 6c6f635f loc_MOD_realloc_\n+ 0x00000600 6c31005f 5f677269 6478635f 616c6c6f l1.__gridxc_allo\n+ 0x00000610 635f4d4f 445f7265 616c6c6f 635f7a32 c_MOD_realloc_z2\n+ 0x00000620 005f5f67 72696478 635f616c 6c6f635f .__gridxc_alloc_\n+ 0x00000630 4d4f445f 7265616c 6c6f635f 7a31005f MOD_realloc_z1._\n+ 0x00000640 5f677269 6478635f 616c6c6f 635f4d4f _gridxc_alloc_MO\n+ 0x00000650 445f7265 616c6c6f 635f6434 005f5f67 D_realloc_d4.__g\n+ 0x00000660 72696478 635f616c 6c6f635f 4d4f445f ridxc_alloc_MOD_\n+ 0x00000670 7265616c 6c6f635f 6433005f 5f677269 realloc_d3.__gri\n+ 0x00000680 6478635f 616c6c6f 635f4d4f 445f7265 dxc_alloc_MOD_re\n+ 0x00000690 616c6c6f 635f6432 005f5f67 72696478 alloc_d2.__gridx\n+ 0x000006a0 635f616c 6c6f635f 4d4f445f 7265616c c_alloc_MOD_real\n+ 0x000006b0 6c6f635f 6431005f 5f677269 6478635f loc_d1.__gridxc_\n+ 0x000006c0 616c6c6f 635f4d4f 445f7265 616c6c6f alloc_MOD_reallo\n+ 0x000006d0 635f7234 005f5f67 72696478 635f616c c_r4.__gridxc_al\n+ 0x000006e0 6c6f635f 4d4f445f 7265616c 6c6f635f loc_MOD_realloc_\n+ 0x000006f0 7233005f 5f677269 6478635f 616c6c6f r3.__gridxc_allo\n+ 0x00000700 635f4d4f 445f7265 616c6c6f 635f7232 c_MOD_realloc_r2\n+ 0x00000710 005f5f67 72696478 635f616c 6c6f635f .__gridxc_alloc_\n+ 0x00000720 4d4f445f 7265616c 6c6f635f 7231005f MOD_realloc_r1._\n+ 0x00000730 5f677269 6478635f 616c6c6f 635f4d4f _gridxc_alloc_MO\n+ 0x00000740 445f7265 616c6c6f 635f6531 005f5f67 D_realloc_e1.__g\n+ 0x00000750 72696478 635f616c 6c6f635f 4d4f445f ridxc_alloc_MOD_\n+ 0x00000760 7265616c 6c6f635f 6933005f 5f677269 realloc_i3.__gri\n+ 0x00000770 6478635f 616c6c6f 635f4d4f 445f7265 dxc_alloc_MOD_re\n+ 0x00000780 616c6c6f 635f6932 005f5f67 72696478 alloc_i2.__gridx\n+ 0x00000790 635f616c 6c6f635f 4d4f445f 7265616c c_alloc_MOD_real\n+ 0x000007a0 6c6f635f 6931005f 5f677269 6478635f loc_i1.__gridxc_\n+ 0x000007b0 616c6c6f 635f4d4f 445f616c 6c6f635f alloc_MOD_alloc_\n+ 0x000007c0 64656661 756c7400 5f5f6772 69647863 default.__gridxc\n+ 0x000007d0 5f616c6c 6f635f4d 4f445f73 65745f61 _alloc_MOD_set_a\n+ 0x000007e0 6c6c6f63 5f657272 6f725f68 616e646c lloc_error_handl\n+ 0x000007f0 6572005f 5f677269 6478635f 616c6c6f er.__gridxc_allo\n+ 0x00000800 635f4d4f 445f7365 745f616c 6c6f635f c_MOD_set_alloc_\n+ 0x00000810 6576656e 745f6861 6e646c65 72005f5f event_handler.__\n+ 0x00000820 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n+ 0x00000830 5f6e6565 64735f64 65616c6c 6f63005f _needs_dealloc._\n+ 0x00000840 5f677269 6478635f 616c6c6f 635f4d4f _gridxc_alloc_MO\n+ 0x00000850 445f6e65 6564735f 636f7079 005f5f67 D_needs_copy.__g\n+ 0x00000860 72696478 635f616c 6c6f635f 4d4f445f ridxc_alloc_MOD_\n+ 0x00000870 6e656564 735f616c 6c6f6300 5f5f6772 needs_alloc.__gr\n+ 0x00000880 69647863 5f616c6c 6f635f4d 4f445f69 idxc_alloc_MOD_i\n+ 0x00000890 65727200 5f5f6772 69647863 5f616c6c err.__gridxc_all\n+ 0x000008a0 6f635f4d 4f445f64 65666175 6c74005f oc_MOD_default._\n+ 0x000008b0 5f677269 6478635f 616c6c6f 635f4d4f _gridxc_alloc_MO\n+ 0x000008c0 445f6173 736f6369 61746564 5f617272 D_associated_arr\n+ 0x000008d0 6179005f 5f677269 6478635f 616c6c6f ay.__gridxc_allo\n+ 0x000008e0 635f4d4f 445f616c 6c6f635f 6d656d6f c_MOD_alloc_memo\n+ 0x000008f0 72795f65 76656e74 005f5f67 72696478 ry_event.__gridx\n+ 0x00000900 635f616c 6c6f635f 4d4f445f 616c6c6f c_alloc_MOD_allo\n+ 0x00000910 635f6572 726f725f 7265706f 7274005f c_error_report._\n+ 0x00000920 5f677269 6478635f 616c6c6f 635f4d4f _gridxc_alloc_MO\n+ 0x00000930 445f5f5f 76746162 5f677269 6478635f D___vtab_gridxc_\n+ 0x00000940 616c6c6f 635f416c 6c6f6364 65666175 alloc_Allocdefau\n+ 0x00000950 6c747300 5f5f6772 69647863 5f616c6c lts.__gridxc_all\n+ 0x00000960 6f635f4d 4f445f5f 5f646566 5f696e69 oc_MOD___def_ini\n+ 0x00000970 745f6772 69647863 5f616c6c 6f635f41 t_gridxc_alloc_A\n+ 0x00000980 6c6c6f63 64656661 756c7473 00 llocdefaults.\n \n"}]}, {"source1": "am05.F90.o", "source2": "am05.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 6924 (bytes into file)\n+ Start of section headers: 7292 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x1b0c:\n+There are 11 section headers, starting at offset 0x1c7c:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 0014c8 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 001964 000148 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 001500 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 001500 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 001500 00002e 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 00152e 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 00152e 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 001564 000250 10 9 24 4\n- [ 9] .strtab STRTAB 00000000 0017b4 0001ad 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 001aac 00005f 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 001640 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 001ad4 000148 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 001678 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 001678 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 001678 00002e 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 0016a6 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0016a6 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 0016d4 000250 10 9 24 4\n+ [ 9] .strtab STRTAB 00000000 001924 0001ad 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 001c1c 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -6,35 +6,35 @@\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 4: 00000098 0 NOTYPE LOCAL DEFAULT 1 $d\n 5: 000000b4 0 NOTYPE LOCAL DEFAULT 1 $t\n 6: 00000460 0 NOTYPE LOCAL DEFAULT 1 $d\n 7: 00000001 1136 FUNC LOCAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_lambertw.localalias\n 8: 00000470 0 NOTYPE LOCAL DEFAULT 1 $t\n- 9: 000007e8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 10: 00000471 1224 FUNC LOCAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldapwc.localalias\n- 11: 00000938 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 00000970 0 NOTYPE LOCAL DEFAULT 1 $d\n- 13: 00000978 0 NOTYPE LOCAL DEFAULT 1 $t\n- 14: 00000af0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 15: 00000b18 0 NOTYPE LOCAL DEFAULT 1 $t\n- 16: 00000e68 0 NOTYPE LOCAL DEFAULT 1 $d\n- 17: 00000ef0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 18: 00001258 0 NOTYPE LOCAL DEFAULT 1 $d\n- 19: 00000979 2360 FUNC LOCAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss.localalias\n- 20: 000012b0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 21: 00001448 0 NOTYPE LOCAL DEFAULT 1 $d\n- 22: 00001474 0 NOTYPE LOCAL DEFAULT 1 $t\n- 23: 000014b8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 000007f8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 10: 00000471 1248 FUNC LOCAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldapwc.localalias\n+ 11: 00000950 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 00000988 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 13: 00000990 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 14: 00000b40 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 15: 00000b70 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 16: 00000f20 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 17: 00000fb0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 18: 000013c8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00000991 2704 FUNC LOCAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss.localalias\n+ 20: 00001420 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 21: 000015b8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 22: 000015ec 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 23: 00001630 0 NOTYPE LOCAL DEFAULT 1 $d\n 24: 00000001 1136 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_lambertw\n 25: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n 26: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n 27: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 29: 00000471 1224 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldapwc\n+ 29: 00000471 1248 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldapwc\n 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n- 31: 00000939 64 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldax\n- 32: 00000979 2360 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss\n+ 31: 00000951 64 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss_ldax\n+ 32: 00000991 2704 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05_xscss\n 33: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 34: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 35: 000012b1 452 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05wbs\n- 36: 00001475 84 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_saferecp\n+ 35: 00001421 460 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_am05wbs\n+ 36: 000015ed 84 FUNC GLOBAL DEFAULT 1 __gridxc_am05_MOD_saferecp\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,44 +1,44 @@\n \n-Relocation section '.rel.text' at offset 0x1964 contains 41 entries:\n+Relocation section '.rel.text' at offset 0x1ad4 contains 41 entries:\n Offset Info Type Sym. Value Symbol's Name\n 0000005e 0000190a R_ARM_THM_CALL 00000000 exp\n-00000086 00001a0a R_ARM_THM_CALL 00000000 log\n-0000008e 00001a0a R_ARM_THM_CALL 00000000 log\n+00000082 00001a0a R_ARM_THM_CALL 00000000 log\n+0000008a 00001a0a R_ARM_THM_CALL 00000000 log\n 000000b0 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000106 0000190a R_ARM_THM_CALL 00000000 exp\n 0000015e 0000190a R_ARM_THM_CALL 00000000 exp\n 000001b8 0000190a R_ARM_THM_CALL 00000000 exp\n 00000214 0000190a R_ARM_THM_CALL 00000000 exp\n 00000270 0000190a R_ARM_THM_CALL 00000000 exp\n 000002d8 0000190a R_ARM_THM_CALL 00000000 exp\n 00000334 0000190a R_ARM_THM_CALL 00000000 exp\n 00000390 0000190a R_ARM_THM_CALL 00000000 exp\n 000003ec 0000190a R_ARM_THM_CALL 00000000 exp\n 00000468 00001c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n 0000046c 00000203 R_ARM_REL32 00000000 .LC0\n-000004c4 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-000004d0 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-000004dc 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00000504 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00000554 00001a0a R_ARM_THM_CALL 00000000 log\n-000005bc 00001a0a R_ARM_THM_CALL 00000000 log\n-00000620 00001a0a R_ARM_THM_CALL 00000000 log\n-00000956 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00000b10 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000b14 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000c16 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00000c2a 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00000c7a 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00001064 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00001078 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-000010c4 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-000010ec 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-0000124e 0000220a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000012a8 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000012ac 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001306 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-0000131e 00001e0a R_ARM_THM_CALL 00000000 cbrt\n-00001440 0000220a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001468 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000146c 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001470 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004c8 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000004e4 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000004f0 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+0000052c 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+00000570 00001a0a R_ARM_THM_CALL 00000000 log\n+000005d0 00001a0a R_ARM_THM_CALL 00000000 log\n+00000634 00001a0a R_ARM_THM_CALL 00000000 log\n+0000096e 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+00000b68 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000b6c 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000c72 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+00000c86 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+00000cde 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+0000118a 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+00001196 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000011a6 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000011b2 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000013c0 0000220a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001418 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000141c 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001476 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+0000148e 00001e0a R_ARM_THM_CALL 00000000 cbrt\n+000015b0 0000220a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000015e0 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000015e4 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000015e8 00001b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -6,299 +6,299 @@\n 00000000 <__gridxc_am05_MOD_am05_xscss_lambertw>:\n __gridxc_am05_MOD_am05_xscss_lambertw.localalias():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4024]\t@ 0xfb8\n-\tvldr\td16, [pc, #132]\t@ 98 <__gridxc_am05_MOD_am05_xscss_lambertw+0x98>\n+\tvldr\td7, [pc, #132]\t@ 98 <__gridxc_am05_MOD_am05_xscss_lambertw+0x98>\n \tmov\tr4, r1\n \tvldr\td8, [r0]\n \tldr\tr5, [pc, #144]\t@ (b0 <__gridxc_am05_MOD_am05_xscss_lambertw+0xb0>)\n-\tvcmpe.f64\td8, d16\n+\tvcmpe.f64\td8, d7\n \tadd\tr5, pc\n \tvmrs\tAPSR_nzcv, fpscr\n \tbmi.w\t452 <__gridxc_am05_MOD_am05_xscss_lambertw+0x452>\n-\tvldr\td16, [pc, #112]\t@ a0 <__gridxc_am05_MOD_am05_xscss_lambertw+0xa0>\n-\tvcmpe.f64\td8, d16\n+\tvldr\td7, [pc, #112]\t@ a0 <__gridxc_am05_MOD_am05_xscss_lambertw+0xa0>\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t82 <__gridxc_am05_MOD_am05_xscss_lambertw+0x82>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvldr\td18, [pc, #104]\t@ a8 <__gridxc_am05_MOD_am05_xscss_lambertw+0xa8>\n-\tvmov.f64\td16, d17\n-\tvfma.f64\td16, d8, d18\n-\tvadd.f64\td16, d16, d16\n-\tvsqrt.f64\td13, d16\n-\tvsub.f64\td13, d13, d17\n+\tbgt.n\t7e <__gridxc_am05_MOD_am05_xscss_lambertw+0x7e>\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td5, [pc, #104]\t@ a8 <__gridxc_am05_MOD_am05_xscss_lambertw+0xa8>\n+\tvmov.f64\td7, d6\n+\tvmla.f64\td7, d8, d5\n+\tvadd.f64\td7, d7, d7\n+\tvsqrt.f64\td13, d7\n+\tvsub.f64\td13, d13, d6\n \tvmov.f64\td11, #240\t@ 0xbf800000 -1.0\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, d8\n+\tvmov.f64\td5, d8\n \tvcmp.f64\td13, d11\n-\tvfnms.f64\td16, d13, d0\n-\tvneg.f64\td9, d8\n+\tvnmls.f64\td5, d13, d0\n \tvmrs\tAPSR_nzcv, fpscr\n \tbne.n\tb4 <__gridxc_am05_MOD_am05_xscss_lambertw+0xb4>\n \tvstr\td13, [r4]\n \tvpop\t{d8-d14}\n \tpop\t{r4, r5, r6, pc}\n \tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvmov.f64\td13, d0\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvsub.f64\td13, d13, d0\n \tb.n\t56 <__gridxc_am05_MOD_am05_xscss_lambertw+0x56>\n+\tnop.w\n \t.word\t0x0c924223\n \t.word\t0x3bc79ca1\n \t.word\t0xa5a7f765\n \t.word\t0x3ff1505d\n \t.word\t0x8b145769\n \t.word\t0x4005bf0a\n \t.word\t0x0000008a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\tvmov.f64\td8, #0\t@ 0x40000000 2.0\n+\tvmov.f64\td9, #0\t@ 0x40000000 2.0\n \tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n \tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n \tvldr\td14, [pc, #924]\t@ 460 <__gridxc_am05_MOD_am05_xscss_lambertw+0x460>\n-\tvadd.f64\td17, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td17, d17, d12\n-\tvmul.f64\td17, d17, d16\n-\tvdiv.f64\td18, d17, d19\n-\tvfnms.f64\td18, d19, d0\n-\tvdiv.f64\td17, d16, d18\n-\tvmov.f64\td16, d14\n-\tvsub.f64\td13, d13, d17\n-\tvabs.f64\td17, d17\n-\tvabs.f64\td18, d13\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d4, d0\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td16, d18, d14\n-\tvcmpe.f64\td17, d16\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.n\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.n\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.n\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.n\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td7, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td8, d13, d8\n+\tvnmls.f64\td7, d13, d0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td9, d13, d9\n \tvadd.f64\td10, d13, d10\n-\tvmul.f64\td8, d8, d12\n-\tvmul.f64\td8, d8, d18\n-\tvdiv.f64\td17, d8, d10\n-\tvfnms.f64\td17, d0, d10\n-\tvdiv.f64\td16, d18, d17\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td17, d13\n+\tvmul.f64\td9, d9, d12\n+\tvmul.f64\td9, d9, d7\n+\tvdiv.f64\td5, d9, d10\n+\tvnmls.f64\td5, d0, d10\n+\tvdiv.f64\td6, d7, d5\n+\tvsub.f64\td13, d13, d6\n+\tvabs.f64\td6, d6\n+\tvabs.f64\td7, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td14, d17, d14\n-\tvcmpe.f64\td16, d14\n+\tvmla.f64\td14, d7, d14\n+\tvcmpe.f64\td6, d14\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td11, #240\t@ 0xbf800000 -1.0\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td18, d9\n+\tvmov.f64\td5, d8\n \tvcmp.f64\td13, d11\n-\tvfma.f64\td18, d13, d0\n+\tvnmls.f64\td5, d13, d0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvmov.f64\td8, #0\t@ 0x40000000 2.0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvmov.f64\td9, #0\t@ 0x40000000 2.0\n \tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n \tvldr\td14, [pc, #460]\t@ 460 <__gridxc_am05_MOD_am05_xscss_lambertw+0x460>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvmov.f64\td18, d9\n-\tvfma.f64\td18, d13, d0\n+\tvmov.f64\td5, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td16, d13, d8\n-\tvadd.f64\td19, d13, d10\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvfnms.f64\td17, d0, d19\n-\tvdiv.f64\td16, d18, d17\n-\tvmov.f64\td17, d14\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d13\n+\tvnmls.f64\td5, d13, d0\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td7, d13, d9\n+\tvadd.f64\td4, d13, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td6, d7, d4\n+\tvnmls.f64\td6, d0, d4\n+\tvdiv.f64\td7, d5, d6\n+\tvmov.f64\td6, d14\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td17, d18, d14\n-\tvcmpe.f64\td16, d17\n+\tvmla.f64\td6, d5, d14\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvcmp.f64\td13, d11\n-\tvfma.f64\td9, d0, d13\n+\tvnmls.f64\td8, d0, d13\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n-\tvadd.f64\td8, d13, d8\n+\tbeq.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n+\tvadd.f64\td9, d13, d9\n \tvadd.f64\td10, d13, d10\n-\tvmul.f64\td8, d8, d12\n-\tvmul.f64\td8, d8, d9\n-\tvdiv.f64\td17, d8, d10\n-\tvfnms.f64\td17, d10, d0\n-\tvdiv.f64\td16, d9, d17\n-\tvsub.f64\td13, d13, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td17, d13\n+\tvmul.f64\td9, d9, d12\n+\tvmul.f64\td9, d9, d8\n+\tvdiv.f64\td6, d9, d10\n+\tvnmls.f64\td6, d10, d0\n+\tvdiv.f64\td7, d8, d6\n+\tvsub.f64\td13, d13, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td6, d13\n \tvstr\td13, [r4]\n-\tvmla.f64\td14, d17, d14\n-\tvcmpe.f64\td16, d14\n+\tvmla.f64\td14, d6, d14\n+\tvcmpe.f64\td7, d14\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t7c <__gridxc_am05_MOD_am05_xscss_lambertw+0x7c>\n+\tbmi.w\t78 <__gridxc_am05_MOD_am05_xscss_lambertw+0x78>\n \tldr\tr3, [pc, #40]\t@ (468 <__gridxc_am05_MOD_am05_xscss_lambertw+0x468>)\n \tmovs\tr1, #45\t@ 0x2d\n \tvpop\t{d8-d14}\n \tldr\tr0, [pc, #36]\t@ (46c <__gridxc_am05_MOD_am05_xscss_lambertw+0x46c>)\n \tldr\tr3, [r5, r3]\n \tadd\tr0, pc\n \tldmia.w\tsp!, {r4, r5, r6, lr}\n@@ -317,721 +317,772 @@\n \n 00000470 <__gridxc_am05_MOD_am05_xscss_ldapwc>:\n __gridxc_am05_MOD_am05_xscss_ldapwc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3888]\t@ 0xf30\n-\tvldr\td16, [r0]\n-\tsub\tsp, #132\t@ 0x84\n-\tvldr\td18, [r0, #8]\n+\tstr.w\tr0, [ip, #3904]\t@ 0xf40\n+\tvldr\td7, [r0]\n+\tsub\tsp, #116\t@ 0x74\n+\tvldr\td5, [r0, #8]\n \tmov\tr5, r1\n-\tvldr\td19, [pc, #856]\t@ 7e8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x378>\n+\tvldr\td4, [pc, #872]\t@ 7f8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x388>\n \tmov\tr4, r2\n-\tvadd.f64\td17, d16, d18\n-\tvcmpe.f64\td17, d19\n+\tvadd.f64\td6, d7, d5\n+\tvcmpe.f64\td6, d4\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\t7d4 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x364>\n-\tvsub.f64\td16, d16, d18\n-\tvldr\td19, [pc, #836]\t@ 7f0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x380>\n-\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td12, d19, d17\n-\tvdiv.f64\td14, d16, d17\n-\tvsqrt.f64\td0, d12\n-\tvadd.f64\td10, d14, d15\n-\tvsub.f64\td11, d15, d14\n+\tbls.w\t7e4 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x374>\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td4, [pc, #852]\t@ 800 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x390>\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvldr\td15, [pc, #852]\t@ 808 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x398>\n+\tvdiv.f64\td9, d4, d6\n+\tvmov.f64\td14, d8\n+\tvdiv.f64\td3, d7, d6\n+\tvsqrt.f64\td0, d9\n+\tvstr\td3, [sp]\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td8, d0\n+\tvldr\td3, [sp]\n+\tvmov.f64\td13, d0\n+\tvadd.f64\td10, d3, d8\n+\tvsub.f64\td12, d8, d3\n+\tvstr\td3, [sp, #104]\t@ 0x68\n \tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td9, d0\n-\tvmov.f64\td0, d11\n+\tvmov.f64\td11, d0\n+\tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td22, d0\n-\tvmov.f64\td17, #0\t@ 0x40000000 2.0\n-\tvldr\td16, [pc, #780]\t@ 7f8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x388>\n-\tvmov.f64\td0, d12\n-\tvmul.f64\td13, d22, d11\n-\tvstr\td22, [sp, #120]\t@ 0x78\n-\tvfma.f64\td13, d9, d10\n-\tvsub.f64\td13, d13, d17\n-\tvmul.f64\td13, d13, d16\n+\tvmov.f64\td7, d0\n+\tvmov.f64\td4, #0\t@ 0x40000000 2.0\n+\tvldr\td2, [pc, #784]\t@ 810 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3a0>\n+\tvmov.f64\td0, d9\n+\tvstr\td12, [sp, #56]\t@ 0x38\n+\tvstr\td10, [sp, #48]\t@ 0x30\n+\tvmov.f64\td1, d7\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d11, d10\n+\tvldr\td9, [pc, #764]\t@ 818 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3a8>\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvsub.f64\td7, d7, d4\n+\tvmul.f64\td2, d7, d2\n+\tvstr\td2, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [pc, #756]\t@ 800 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x390>\n+\tvldr\td7, [pc, #748]\t@ 820 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3b0>\n \tvmov.f64\td12, d0\n-\tvldr\td18, [pc, #756]\t@ 808 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x398>\n-\tvldr\td16, [pc, #760]\t@ 810 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3a0>\n-\tvfma.f64\td18, d8, d17\n-\tvldr\td27, [pc, #760]\t@ 818 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3a8>\n-\tvldr\td20, [pc, #764]\t@ 820 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3b0>\n-\tvmov.f64\td17, d15\n-\tvldr\td19, [pc, #764]\t@ 828 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3b8>\n-\tvstr\td27, [sp, #112]\t@ 0x70\n-\tvfma.f64\td17, d0, d20\n-\tvmov.f64\td20, d27\n-\tvfma.f64\td16, d18, d8\n-\tvstr\td17, [sp]\n-\tvfma.f64\td20, d16, d8\n-\tvmul.f64\td20, d20, d8\n-\tvdiv.f64\td0, d19, d20\n-\tvstr\td20, [sp, #104]\t@ 0x68\n-\tvadd.f64\td0, d0, d15\n+\tvldr\td6, [pc, #748]\t@ 828 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3b8>\n+\tvmla.f64\td6, d13, d7\n+\tvldr\td7, [pc, #748]\t@ 830 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3c0>\n+\tvmla.f64\td7, d6, d13\n+\tvldr\td6, [pc, #748]\t@ 838 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3c8>\n+\tvmla.f64\td6, d7, d13\n+\tvldr\td7, [pc, #748]\t@ 840 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3d0>\n+\tvmul.f64\td10, d6, d13\n+\tvdiv.f64\td0, d7, d10\n+\tvldr\td7, [pc, #744]\t@ 848 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3d8>\n+\tvmul.f64\td10, d10, d15\n+\tvmla.f64\td10, d10, d10\n+\tvmla.f64\td14, d12, d7\n+\tvadd.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td21, [pc, #724]\t@ 830 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3c0>\n-\tvldr\td19, [pc, #728]\t@ 838 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3c8>\n-\tvmov.f64\td23, d15\n-\tvldr\td16, [pc, #728]\t@ 840 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3d0>\n-\tvfma.f64\td19, d8, d21\n-\tvldr\td29, [pc, #728]\t@ 848 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3d8>\n-\tvldr\td25, [pc, #732]\t@ 850 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3e0>\n-\tvldr\td18, [pc, #736]\t@ 858 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3e8>\n-\tvstr\td0, [sp, #88]\t@ 0x58\n-\tvmul.f64\td31, d0, d25\n-\tvldr\td26, [pc, #732]\t@ 860 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3f0>\n-\tvldr\td17, [sp]\n-\tvstr\td25, [sp, #96]\t@ 0x60\n-\tvfma.f64\td23, d12, d26\n-\tvstr\td29, [sp, #64]\t@ 0x40\n-\tvfma.f64\td16, d19, d8\n-\tvmov.f64\td19, d29\n-\tvnmul.f64\td31, d17, d31\n-\tvstr\td31, [sp, #72]\t@ 0x48\n-\tvstr\td23, [sp, #80]\t@ 0x50\n-\tvfma.f64\td19, d16, d8\n-\tvmul.f64\td19, d19, d8\n-\tvdiv.f64\td0, d18, d19\n-\tvstr\td19, [sp, #56]\t@ 0x38\n-\tvadd.f64\td0, d0, d15\n+\tvldr\td7, [pc, #728]\t@ 850 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3e0>\n+\tvldr\td6, [pc, #732]\t@ 858 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3e8>\n+\tvmov.f64\td5, d0\n+\tvstr\td14, [sp, #16]\n+\tvmla.f64\td6, d13, d7\n+\tvldr\td7, [pc, #724]\t@ 860 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3f0>\n+\tvstr\td5, [sp, #24]\n+\tvmla.f64\td7, d6, d13\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td9, d7, d13\n+\tvldr\td7, [pc, #712]\t@ 868 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3f8>\n+\tvmul.f64\td9, d9, d13\n+\tvdiv.f64\td0, d7, d9\n+\tvldr\td7, [pc, #708]\t@ 870 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x400>\n+\tvmla.f64\td6, d12, d7\n+\tvmul.f64\td7, d5, d15\n+\tvnmul.f64\td4, d14, d7\n+\tvldr\td14, [pc, #700]\t@ 878 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x408>\n+\tvmul.f64\td9, d9, d14\n+\tvstr\td4, [sp, #64]\t@ 0x40\n+\tvmla.f64\td9, d9, d9\n+\tvstr\td6, [sp]\n+\tvadd.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td18, [pc, #676]\t@ 868 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3f8>\n-\tvldr\td16, [pc, #680]\t@ 870 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x400>\n-\tvmov.f64\td30, d0\n-\tvldr\td7, [pc, #680]\t@ 878 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x408>\n-\tvfma.f64\td16, d8, d18\n-\tvldr\td26, [pc, #680]\t@ 880 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x410>\n-\tvldr\td6, [pc, #684]\t@ 888 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x418>\n-\tvldr\td28, [pc, #688]\t@ 890 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x420>\n-\tvmov.f64\td18, d26\n-\tvldr\td5, [pc, #688]\t@ 898 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x428>\n-\tvstr\td26, [sp, #48]\t@ 0x30\n-\tvstr\td30, [sp, #16]\n-\tvstr\td5, [sp, #24]\n-\tvfma.f64\td7, d16, d8\n-\tvmov.f64\td16, d15\n-\tvfma.f64\td16, d12, d28\n-\tvmul.f64\td28, d30, d5\n-\tvstr\td28, [sp, #8]\n-\tvfma.f64\td18, d7, d8\n-\tvstr\td16, [sp, #32]\n-\tvmul.f64\td18, d18, d8\n-\tvdiv.f64\td0, d6, d18\n-\tvstr\td18, [sp, #40]\t@ 0x28\n-\tvadd.f64\td0, d0, d15\n+\tvldr\td6, [pc, #680]\t@ 880 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x410>\n+\tvldr\td7, [pc, #684]\t@ 888 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x418>\n+\tvmov.f64\td1, d0\n+\tvmla.f64\td7, d13, d6\n+\tvldr\td6, [pc, #680]\t@ 890 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x420>\n+\tvstr\td1, [sp, #32]\n+\tvmla.f64\td6, d7, d13\n+\tvldr\td7, [pc, #676]\t@ 898 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x428>\n+\tvmov.f64\td3, d7\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvldr\td7, [sp]\n+\tvmla.f64\td3, d6, d13\n+\tvldr\td6, [pc, #664]\t@ 8a0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x430>\n+\tvmul.f64\td5, d3, d13\n+\tvmov.f64\td3, d8\n+\tvdiv.f64\td0, d6, d5\n+\tvldr\td6, [pc, #656]\t@ 8a8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x438>\n+\tvstr\td5, [sp, #80]\t@ 0x50\n+\tvmla.f64\td3, d12, d6\n+\tvmul.f64\td6, d1, d14\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td3, [sp, #40]\t@ 0x28\n+\tvstr\td7, [sp, #8]\n+\tvadd.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td5, [sp, #24]\n-\tvldr\td19, [sp, #56]\t@ 0x38\n-\tvldr\td25, [sp, #96]\t@ 0x60\n-\tvldr\td16, [sp]\n-\tvmul.f64\td3, d19, d5\n-\tvldr\td20, [sp, #104]\t@ 0x68\n-\tvdiv.f64\td19, d15, d8\n-\tvldr\td22, [sp, #120]\t@ 0x78\n-\tvmul.f64\td7, d16, d25\n-\tvldr\td24, [pc, #596]\t@ 8a0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x430>\n-\tvmul.f64\td6, d20, d25\n-\tvldr\td25, [pc, #596]\t@ 8a8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x438>\n-\tvsub.f64\td9, d9, d22\n-\tvldr\td22, [pc, #596]\t@ 8b0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x440>\n-\tvmul.f64\td24, d12, d24\n-\tvldr\td20, [pc, #596]\t@ 8b8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x448>\n-\tvmul.f64\td25, d12, d25\n-\tvldr\td27, [sp, #112]\t@ 0x70\n-\tvfma.f64\td25, d8, d22\n-\tvmla.f64\td6, d6, d6\n-\tvldr\td26, [sp, #48]\t@ 0x30\n-\tvmla.f64\td3, d3, d3\n-\tvmov.f64\td22, d24\n-\tvldr\td24, [pc, #572]\t@ 8c0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x450>\n-\tvfma.f64\td22, d8, d20\n-\tvldr\td20, [pc, #572]\t@ 8c8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x458>\n-\tvldr\td18, [sp, #40]\t@ 0x28\n-\tvldr\td16, [sp, #32]\n-\tvldr\td21, [sp, #88]\t@ 0x58\n-\tvldr\td23, [sp, #80]\t@ 0x50\n-\tvadd.f64\td25, d25, d20\n-\tvldr\td20, [pc, #556]\t@ 8d0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x460>\n-\tvldr\td29, [sp, #64]\t@ 0x40\n-\tvmul.f64\td5, d23, d5\n-\tvldr\td28, [sp, #8]\n-\tvmul.f64\td7, d7, d20\n-\tvmov.f64\td20, #16\t@ 0x40800000 4.0\n-\tvadd.f64\td24, d22, d24\n-\tvldr\td22, [pc, #536]\t@ 8d8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x468>\n-\tvmul.f64\td20, d14, d20\n-\tvmul.f64\td14, d14, d14\n-\tvldr\td17, [pc, #532]\t@ 8e0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x470>\n-\tvldr\td30, [sp, #16]\n-\tvldr\td31, [sp, #72]\t@ 0x48\n-\tvmul.f64\td20, d20, d14\n-\tvmul.f64\td14, d14, d14\n-\tvfma.f64\td25, d19, d27\n-\tvldr\td27, [pc, #516]\t@ 8e8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x478>\n-\tvfma.f64\td24, d19, d26\n-\tvmul.f64\td26, d18, d22\n-\tvldr\td18, [pc, #512]\t@ 8f0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x480>\n-\tvmla.f64\td26, d26, d26\n-\tvmul.f64\td27, d12, d27\n-\tvfma.f64\td27, d8, d18\n-\tvmul.f64\td18, d16, d22\n-\tvmul.f64\td22, d0, d22\n-\tvmul.f64\td7, d7, d25\n-\tvnmul.f64\td16, d16, d22\n-\tvldr\td22, [pc, #488]\t@ 8f8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x488>\n-\tvfma.f64\td16, d23, d28\n-\tvdiv.f64\td25, d7, d6\n-\tvmul.f64\td7, d13, d20\n-\tvldr\td20, [pc, #480]\t@ 900 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x490>\n-\tvmov.f64\td6, #240\t@ 0xbf800000 -1.0\n-\tvfma.f64\td6, d13, d14\n-\tvmul.f64\td18, d18, d20\n-\tvldr\td20, [pc, #472]\t@ 908 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x498>\n-\tvmul.f64\td5, d5, d20\n-\tvldr\td20, [pc, #472]\t@ 910 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4a0>\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td20, d12, d20\n-\tvdiv.f64\td24, d18, d26\n-\tvldr\td18, [pc, #464]\t@ 918 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4a8>\n-\tvfma.f64\td25, d21, d22\n-\tvldr\td21, [pc, #464]\t@ 920 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4b0>\n-\tvsub.f64\td22, d14, d15\n-\tvmul.f64\td22, d22, d17\n-\tvnmul.f64\td25, d25, d22\n-\tvfma.f64\td24, d0, d21\n-\tvldr\td21, [pc, #452]\t@ 928 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4b8>\n-\tvadd.f64\td27, d27, d21\n-\tvfma.f64\td27, d19, d29\n-\tvldr\td19, [pc, #448]\t@ 930 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4c0>\n-\tvmul.f64\td19, d9, d19\n-\tvfms.f64\td25, d14, d24\n-\tvmul.f64\td5, d5, d27\n-\tvdiv.f64\td21, d5, d3\n-\tvfma.f64\td21, d30, d18\n-\tvmul.f64\td18, d16, d14\n-\tvfma.f64\td18, d31, d22\n-\tvfma.f64\td16, d31, d17\n-\tvmul.f64\td17, d13, d18\n-\tvmul.f64\td19, d19, d18\n-\tvfma.f64\td19, d16, d7\n-\tvmul.f64\td13, d13, d25\n-\tvfma.f64\td13, d6, d21\n-\tvmov.f64\td16, d17\n-\tvfms.f64\td16, d23, d28\n-\tvmov.f64\td17, d16\n-\tvfms.f64\td17, d13, d20\n-\tvmov.f64\td18, d17\n-\tvfms.f64\td17, d10, d19\n-\tvfma.f64\td18, d11, d19\n-\tvstr\td16, [r5]\n-\tvstr\td18, [r4]\n-\tvstr\td17, [r4, #8]\n-\tadd\tsp, #132\t@ 0x84\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvldr\td5, [sp]\n+\tvmov.f64\td2, d9\n+\tvldr\td4, [pc, #616]\t@ 8b0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x440>\n+\tvsub.f64\td11, d11, d1\n+\tvldr\td1, [pc, #616]\t@ 8b8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x448>\n+\tvldr\td6, [sp, #16]\n+\tvmul.f64\td4, d12, d4\n+\tvldr\td9, [pc, #612]\t@ 8c0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x450>\n+\tvmla.f64\td4, d13, d1\n+\tvldr\td1, [pc, #612]\t@ 8c8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x458>\n+\tvstr\td11, [sp, #72]\t@ 0x48\n+\tvmul.f64\td11, d5, d14\n+\tvdiv.f64\td14, d8, d13\n+\tvmul.f64\td6, d6, d15\n+\tvmul.f64\td1, d12, d1\n+\tvldr\td3, [sp, #40]\t@ 0x28\n+\tvldr\td7, [sp, #88]\t@ 0x58\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvmov.f64\td15, d1\n+\tvldr\td1, [pc, #580]\t@ 8d0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x460>\n+\tvmla.f64\td15, d13, d9\n+\tvldr\td9, [pc, #580]\t@ 8d8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x468>\n+\tvmul.f64\td1, d12, d1\n+\tvmla.f64\td1, d13, d9\n+\tvldr\td13, [sp, #8]\n+\tvstr\td15, [sp]\n+\tvldr\td15, [pc, #568]\t@ 8e0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x470>\n+\tvmov.f64\td9, d1\n+\tvldr\td1, [pc, #568]\t@ 8e8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x478>\n+\tvadd.f64\td15, d4, d15\n+\tvldr\td4, [pc, #568]\t@ 8f0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x480>\n+\tvmla.f64\td15, d14, d7\n+\tvmul.f64\td7, d5, d4\n+\tvmul.f64\td5, d3, d4\n+\tvmul.f64\td4, d0, d4\n+\tvmla.f64\td7, d7, d7\n+\tvmul.f64\td5, d5, d1\n+\tvmls.f64\td13, d4, d3\n+\tvldr\td3, [sp]\n+\tvldr\td4, [pc, #540]\t@ 8f8 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x488>\n+\tvldr\td1, [pc, #544]\t@ 900 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x490>\n+\tvmul.f64\td15, d15, d5\n+\tvadd.f64\td4, d3, d4\n+\tvldr\td3, [pc, #332]\t@ 838 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3c8>\n+\tvdiv.f64\td5, d15, d7\n+\tvmla.f64\td4, d14, d3\n+\tvldr\td7, [pc, #528]\t@ 908 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x498>\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [pc, #524]\t@ 910 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4a0>\n+\tvadd.f64\td7, d9, d7\n+\tvmul.f64\td9, d3, d3\n+\tvmul.f64\td6, d4, d6\n+\tvdiv.f64\td4, d6, d10\n+\tvldr\td6, [pc, #256]\t@ 818 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x3a8>\n+\tvldr\td10, [pc, #508]\t@ 918 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4a8>\n+\tvmla.f64\td7, d14, d6\n+\tvldr\td6, [pc, #508]\t@ 920 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4b0>\n+\tvmul.f64\td11, d11, d6\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td7, [pc, #504]\t@ 928 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4b8>\n+\tvdiv.f64\td6, d11, d2\n+\tvldr\td2, [sp, #24]\n+\tvldr\td11, [sp, #72]\t@ 0x48\n+\tvmla.f64\td5, d0, d7\n+\tvmul.f64\td7, d9, d9\n+\tvldr\td0, [sp, #64]\t@ 0x40\n+\tvmul.f64\td5, d5, d7\n+\tvmla.f64\td4, d2, d1\n+\tvsub.f64\td1, d7, d8\n+\tvldr\td2, [sp, #96]\t@ 0x60\n+\tvmul.f64\td1, d1, d10\n+\tvnmls.f64\td8, d2, d7\n+\tvmul.f64\td7, d13, d7\n+\tvmla.f64\td13, d0, d10\n+\tvldr\td10, [sp, #48]\t@ 0x30\n+\tvnmla.f64\td5, d1, d4\n+\tvmla.f64\td7, d0, d1\n+\tvldr\td4, [sp, #32]\n+\tvldr\td0, [pc, #436]\t@ 930 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4c0>\n+\tvldr\td1, [sp, #8]\n+\tvmla.f64\td6, d4, d0\n+\tvnmls.f64\td1, d2, d7\n+\tvmul.f64\td6, d6, d8\n+\tvmla.f64\td6, d5, d2\n+\tvmov.f64\td5, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td3, d3, d5\n+\tvldr\td5, [pc, #412]\t@ 938 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4c8>\n+\tvmul.f64\td5, d11, d5\n+\tvmul.f64\td3, d3, d9\n+\tvmul.f64\td7, d5, d7\n+\tvldr\td5, [pc, #404]\t@ 940 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4d0>\n+\tvmul.f64\td3, d3, d2\n+\tvmul.f64\td2, d12, d5\n+\tvmov.f64\td5, d1\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvmla.f64\td7, d3, d13\n+\tvmls.f64\td5, d6, d2\n+\tvmov.f64\td4, d5\n+\tvmls.f64\td5, d10, d7\n+\tvmla.f64\td4, d12, d7\n+\tvstr\td1, [r5]\n+\tvstr\td4, [r4]\n+\tvstr\td5, [r4, #8]\n+\tadd\tsp, #116\t@ 0x74\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, pc}\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvmov.f64\td18, d16\n-\tvmov.f64\td17, d16\n-\tb.n\t7c0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x350>\n+\tvldr\td1, [pc, #352]\t@ 948 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x4d8>\n+\tvmov.f64\td4, d1\n+\tvmov.f64\td5, d1\n+\tb.n\t7d0 <__gridxc_am05_MOD_am05_xscss_ldapwc+0x360>\n \tnop\n \tnop.w\n \t.word\t0x00000000\n \t.word\t0x39b4484c\n \t.word\t0xa4aeacc4\n \t.word\t0x3fce8ec8\n+\t.word\t0xacec5cb5\n+\t.word\t0x3fa14acc\n \t.word\t0xcf2ff901\n \t.word\t0x3ffec750\n+\t.word\t0x2e48e8a7\n+\t.word\t0x401e61ff\n \t.word\t0xbd66277c\n \t.word\t0x3fdfca18\n \t.word\t0x04ff4342\n \t.word\t0x3fec2b17\n \t.word\t0xda5119ce\n \t.word\t0x400cfc1b\n \t.word\t0xb4395810\n \t.word\t0x4024b6c8\n-\t.word\t0x47ae147b\n-\t.word\t0x3fbc7ae1\n \t.word\t0x09de1044\n \t.word\t0x403d9bd7\n+\t.word\t0x47ae147b\n+\t.word\t0x3fbc7ae1\n \t.word\t0x36b8f9b1\n \t.word\t0x3fdf8c54\n \t.word\t0x3404ea4b\n \t.word\t0x3ffa3611\n \t.word\t0xa0f9096c\n \t.word\t0x400cb367\n-\t.word\t0x2e48e8a7\n-\t.word\t0x401e61ff\n-\t.word\t0xacec5cb5\n-\t.word\t0x3fa14acc\n \t.word\t0x9bc1d3b1\n \t.word\t0x403014fc\n \t.word\t0x8793dd98\n \t.word\t0x3fcb5a85\n+\t.word\t0x8ed6c7f8\n+\t.word\t0x3fafd63d\n \t.word\t0x840e171a\n \t.word\t0x3fe40164\n \t.word\t0x43fe5c92\n \t.word\t0x400aedfa\n \t.word\t0xde69ad43\n \t.word\t0x4018ca71\n \t.word\t0x75f6fd22\n \t.word\t0x402c3ce0\n \t.word\t0x9bc1d3b1\n \t.word\t0x404014fc\n \t.word\t0x2bfdb4cc\n \t.word\t0x3fca4d2b\n-\t.word\t0x8ed6c7f8\n-\t.word\t0x3fafd63d\n \t.word\t0x840e171a\n \t.word\t0x40040164\n-\t.word\t0xbd66277c\n-\t.word\t0x3fffca18\n-\t.word\t0x43bf7272\n-\t.word\t0x40052051\n \t.word\t0xb2fec56e\n \t.word\t0x4024327b\n+\t.word\t0x43bf7272\n+\t.word\t0x40052051\n+\t.word\t0xbd66277c\n+\t.word\t0x3fffca18\n+\t.word\t0x36b8f9b1\n+\t.word\t0x3fff8c54\n+\t.word\t0xe703afb8\n+\t.word\t0x4013a88c\n \t.word\t0xde69ad43\n \t.word\t0x4028ca71\n+\t.word\t0x8ed6c7f8\n+\t.word\t0xbf8fd63d\n+\t.word\t0x8ed6c7f8\n+\t.word\t0x3f9fd63d\n \t.word\t0xda5119ce\n \t.word\t0x401cfc1b\n+\t.word\t0x009a7c0f\n+\t.word\t0x3f6ec7b4\n \t.word\t0xacec5cb5\n \t.word\t0xbf914acc\n-\t.word\t0x8ed6c7f8\n-\t.word\t0x3f9fd63d\n+\t.word\t0xa0f9096c\n+\t.word\t0x401cb367\n \t.word\t0x56e5abb7\n \t.word\t0x3fe2b6dd\n-\t.word\t0x36b8f9b1\n-\t.word\t0x3fff8c54\n-\t.word\t0xe703afb8\n-\t.word\t0x4013a88c\n-\t.word\t0x009a7c0f\n-\t.word\t0x3f6ec7b4\n-\t.word\t0x8ed6c7f8\n-\t.word\t0xbf8fd63d\n \t.word\t0x8ed6c7f8\n \t.word\t0xbf9fd63d\n-\t.word\t0x55555555\n-\t.word\t0x3fd55555\n-\t.word\t0x56f9becd\n-\t.word\t0x3f8b36d3\n \t.word\t0x7bd53baa\n \t.word\t0x3f7a2ad8\n-\t.word\t0xa0f9096c\n-\t.word\t0x401cb367\n+\t.word\t0x56f9becd\n+\t.word\t0x3f8b36d3\n \t.word\t0x8a1ffb56\n \t.word\t0x400484e0\n+\t.word\t0x55555555\n+\t.word\t0x3fd55555\n+\t...\n \n-00000938 <__gridxc_am05_MOD_am05_xscss_ldax>:\n+00000950 <__gridxc_am05_MOD_am05_xscss_ldax>:\n __gridxc_am05_MOD_am05_xscss_ldax():\n \tpush\t{r3, r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4080]\t@ 0xff0\n-\tvldr\td16, [pc, #40]\t@ 970 <__gridxc_am05_MOD_am05_xscss_ldax+0x38>\n+\tvldr\td7, [pc, #40]\t@ 988 <__gridxc_am05_MOD_am05_xscss_ldax+0x38>\n \tmov\tr4, r1\n \tvldr\td0, [r0]\n \tmov\tr5, r2\n-\tvmul.f64\td0, d0, d16\n+\tvmul.f64\td0, d0, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n \tvneg.f64\td0, d0\n-\tvmov.f64\td16, #104\t@ 0x3f400000 0.750\n-\tvmul.f64\td16, d0, d16\n+\tvmov.f64\td7, #104\t@ 0x3f400000 0.750\n+\tvmul.f64\td7, d0, d7\n \tvstr\td0, [r5]\n-\tvstr\td16, [r4]\n+\tvstr\td7, [r4]\n \tpop\t{r3, r4, r5, pc}\n \t.word\t0xa4aeacc4\n \t.word\t0x3fee8ec8\n \n-00000978 <__gridxc_am05_MOD_am05_xscss>:\n+00000990 <__gridxc_am05_MOD_am05_xscss>:\n __gridxc_am05_MOD_am05_xscss.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3512]\t@ 0xdb8\n-\tvldr\td19, [pc, #352]\t@ af0 <__gridxc_am05_MOD_am05_xscss+0x178>\n-\tsub\tsp, #484\t@ 0x1e4\n-\tvldr\td21, [r1]\n-\tvmov.i64\td18, #0x0000000000000000\n-\tvldr\td11, [r0]\n-\tadd\tr6, sp, #296\t@ 0x128\n-\tldr\tr5, [pc, #364]\t@ (b10 <__gridxc_am05_MOD_am05_xscss+0x198>)\n-\tadd\tr7, sp, #408\t@ 0x198\n-\tldr\tr4, [pc, #364]\t@ (b14 <__gridxc_am05_MOD_am05_xscss+0x19c>)\n-\tvadd.f64\td22, d11, d19\n-\tvadd.f64\td20, d11, d21\n-\tvldr\td23, [r2]\n-\tadd\tr5, pc\n-\tvldr\td24, [r3]\n-\tvadd.f64\td19, d21, d19\n-\tldr\tr3, [sp, #584]\t@ 0x248\n-\tstr\tr3, [sp, #180]\t@ 0xb4\n-\tvmaxnm.f64\td20, d20, d22\n-\tvstr\td21, [sp, #352]\t@ 0x160\n-\tvstr\td23, [sp, #168]\t@ 0xa8\n-\tvstr\td24, [sp, #40]\t@ 0x28\n-\tvstr\td11, [sp, #344]\t@ 0x158\n-\tvmaxnm.f64\td19, d20, d19\n-\tvstr\td23, [sp, #360]\t@ 0x168\n-\tvstr\td24, [sp, #368]\t@ 0x170\n-\tldr\tr4, [r5, r4]\n-\tldrd\tr1, fp, [sp, #600]\t@ 0x258\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #476]\t@ 0x1dc\n-\tmov.w\tr4, #0\n-\tldr.w\tr9, [sp, #608]\t@ 0x260\n-\tldr\tr4, [sp, #612]\t@ 0x264\n-\tstr\tr4, [sp, #68]\t@ 0x44\n-\tldr\tr4, [sp, #616]\t@ 0x268\n-\tstr\tr4, [sp, #72]\t@ 0x48\n-\tldr\tr4, [sp, #620]\t@ 0x26c\n-\tstr\tr4, [sp, #76]\t@ 0x4c\n-\tldr\tr4, [sp, #624]\t@ 0x270\n-\tldrd\tr2, r3, [sp, #588]\t@ 0x24c\n-\tstr\tr4, [sp, #80]\t@ 0x50\n-\tldr\tr0, [sp, #596]\t@ 0x254\n-\tvstr\td18, [fp]\n-\tvstr\td19, [sp, #16]\n-\tvstr\td18, [r9]\n-\tldr\tr4, [sp, #628]\t@ 0x274\n-\tstr\tr4, [sp, #84]\t@ 0x54\n-\tldr\tr4, [sp, #632]\t@ 0x278\n-\tstr\tr4, [sp, #88]\t@ 0x58\n-\tldr\tr4, [sp, #636]\t@ 0x27c\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n-\tldr\tr4, [sp, #640]\t@ 0x280\n-\tstr\tr4, [sp, #96]\t@ 0x60\n-\tldr\tr4, [sp, #644]\t@ 0x284\n-\tstr\tr4, [sp, #100]\t@ 0x64\n-\tldr\tr4, [sp, #648]\t@ 0x288\n-\tstr\tr4, [sp, #104]\t@ 0x68\n-\tldr\tr4, [sp, #652]\t@ 0x28c\n-\tstr\tr4, [sp, #108]\t@ 0x6c\n-\tldr\tr4, [sp, #656]\t@ 0x290\n-\tstr\tr4, [sp, #152]\t@ 0x98\n-\tvldr\td21, [pc, #192]\t@ af8 <__gridxc_am05_MOD_am05_xscss+0x180>\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n-\tldr\tr4, [sp, #660]\t@ 0x294\n-\tstr\tr4, [sp, #60]\t@ 0x3c\n-\tldrd\tr4, r5, [r0]\n-\tvcmpe.f64\td23, d21\n+\tstr.w\tr0, [ip, #3376]\t@ 0xd30\n+\tvldr\td6, [pc, #408]\t@ b40 <__gridxc_am05_MOD_am05_xscss+0x1b0>\n+\tsub.w\tsp, sp, #620\t@ 0x26c\n+\tvldr\td4, [r1]\n+\tadd\tr7, sp, #432\t@ 0x1b0\n+\tvldr\td14, [r0]\n+\tadd\tr1, sp, #416\t@ 0x1a0\n+\tvldr\td2, [r2]\n+\tadd\tr0, sp, #576\t@ 0x240\n+\tldr\tr2, [pc, #424]\t@ (b68 <__gridxc_am05_MOD_am05_xscss+0x1d8>)\n+\tadd\tr4, sp, #400\t@ 0x190\n+\tvadd.f64\td3, d14, d6\n+\tvadd.f64\td5, d14, d4\n+\tvadd.f64\td6, d4, d6\n+\tvldr\td1, [r3]\n+\tadd\tr3, sp, #448\t@ 0x1c0\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [pc, #404]\t@ (b6c <__gridxc_am05_MOD_am05_xscss+0x1dc>)\n+\tadd\tr2, pc\n+\tvcmpe.f64\td5, d3\n+\tldr\tr5, [sp, #720]\t@ 0x2d0\n+\tstr\tr5, [sp, #288]\t@ 0x120\n+\tadd\tr5, sp, #544\t@ 0x220\n+\tstr\tr1, [sp, #52]\t@ 0x34\n+\tstr\tr0, [sp, #84]\t@ 0x54\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tstr\tr7, [sp, #264]\t@ 0x108\n+\tldrd\tr6, fp, [sp, #736]\t@ 0x2e0\n+\tvstr\td4, [sp, #488]\t@ 0x1e8\n+\tldr.w\tr9, [sp, #744]\t@ 0x2e8\n+\tvstr\td2, [sp, #280]\t@ 0x118\n+\tit\tlt\n+\tvmovlt.f64\td5, d3\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvstr\td14, [sp, #480]\t@ 0x1e0\n+\tvstr\td2, [sp, #496]\t@ 0x1f0\n+\tvstr\td1, [sp, #504]\t@ 0x1f8\n+\tvcmpe.f64\td5, d6\n+\tldr\tr3, [r2, r3]\n+\tvldr\td7, [pc, #300]\t@ b48 <__gridxc_am05_MOD_am05_xscss+0x1b8>\n+\tldr\tr0, [sp, #748]\t@ 0x2ec\n+\tldr\tr3, [r3, #0]\n+\tstr\tr3, [sp, #612]\t@ 0x264\n+\tmov.w\tr3, #0\n+\tstr\tr0, [sp, #160]\t@ 0xa0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tldr\tr0, [sp, #752]\t@ 0x2f0\n+\tldrd\tr2, r3, [sp, #724]\t@ 0x2d4\n+\tstr\tr0, [sp, #164]\t@ 0xa4\n+\tldr\tr1, [sp, #732]\t@ 0x2dc\n+\tvstr\td7, [fp]\n+\tit\tge\n+\tvmovge.f64\td6, d5\n+\tvstr\td7, [r9]\n+\tvldr\td4, [pc, #264]\t@ b50 <__gridxc_am05_MOD_am05_xscss+0x1c0>\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvcmpe.f64\td2, d4\n+\tldr\tr0, [sp, #756]\t@ 0x2f4\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tldr\tr0, [sp, #760]\t@ 0x2f8\n+\tstr\tr0, [sp, #172]\t@ 0xac\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tldr\tr0, [sp, #764]\t@ 0x2fc\n+\tstr\tr0, [sp, #176]\t@ 0xb0\n+\tldr\tr0, [sp, #768]\t@ 0x300\n+\tstr\tr0, [sp, #180]\t@ 0xb4\n+\tldr\tr0, [sp, #772]\t@ 0x304\n+\tstr\tr0, [sp, #184]\t@ 0xb8\n+\tldr\tr0, [sp, #776]\t@ 0x308\n+\tstr\tr0, [sp, #188]\t@ 0xbc\n+\tldr\tr0, [sp, #780]\t@ 0x30c\n+\tstr\tr0, [sp, #192]\t@ 0xc0\n+\tldr\tr0, [sp, #784]\t@ 0x310\n+\tstr\tr0, [sp, #196]\t@ 0xc4\n+\tldr\tr0, [sp, #788]\t@ 0x314\n+\tstr\tr0, [sp, #200]\t@ 0xc8\n+\tldr\tr0, [sp, #792]\t@ 0x318\n+\tstr\tr0, [sp, #204]\t@ 0xcc\n+\tldr\tr0, [sp, #796]\t@ 0x31c\n+\tstr\tr0, [sp, #144]\t@ 0x90\n \tldrd\tr0, r1, [r1]\n-\tstrd\tr0, r1, [sp, #384]\t@ 0x180\n+\tstrd\tr0, r1, [sp, #512]\t@ 0x200\n+\tldrd\tr0, r1, [r6]\n+\tstrd\tr0, r1, [sp, #520]\t@ 0x208\n \tldrd\tr0, r1, [r2]\n-\tvst1.8\t{d16-d17}, [r6 :64]\n-\tvmrs\tAPSR_nzcv, fpscr\n+\tstrd\tr0, r1, [sp, #528]\t@ 0x210\n \tldrd\tr2, r3, [r3]\n-\tstrd\tr2, r3, [sp, #400]\t@ 0x190\n-\tadd\tr3, sp, #312\t@ 0x138\n-\tstr\tr6, [sp, #160]\t@ 0xa0\n-\tstr\tr3, [sp, #164]\t@ 0xa4\n-\tadd\tr6, sp, #264\t@ 0x108\n-\tstrd\tr4, r5, [sp, #376]\t@ 0x178\n-\tvst1.8\t{d16-d17}, [r3 :64]\n-\tadd\tr3, sp, #280\t@ 0x118\n-\tstrd\tr0, r1, [sp, #392]\t@ 0x188\n-\tstr\tr3, [sp, #156]\t@ 0x9c\n-\tvst1.8\t{d16-d17}, [r6 :64]\n-\tvst1.8\t{d16-d17}, [r3 :64]\n-\tadd\tr3, sp, #440\t@ 0x1b8\n-\tvst1.8\t{d16-d17}, [r7 :64]\n-\tstr\tr3, [sp, #188]\t@ 0xbc\n-\tvst1.8\t{d16-d17}, [r3 :64]\n-\tbge.n\tab0 <__gridxc_am05_MOD_am05_xscss+0x138>\n-\tvldr\td16, [pc, #108]\t@ b00 <__gridxc_am05_MOD_am05_xscss+0x188>\n-\tvcmpe.f64\td23, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t121c <__gridxc_am05_MOD_am05_xscss+0x8a4>\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td17, d18\n-\tvstr\td18, [sp, #24]\n-\tb.n\tabc <__gridxc_am05_MOD_am05_xscss+0x144>\n-\tvldr\td16, [pc, #84]\t@ b08 <__gridxc_am05_MOD_am05_xscss+0x190>\n-\tvmov.f64\td17, d16\n-\tvstr\td16, [sp, #24]\n-\tvldr\td16, [pc, #56]\t@ af8 <__gridxc_am05_MOD_am05_xscss+0x180>\n-\tvstr\td17, [sp, #328]\t@ 0x148\n-\tvldr\td17, [sp, #40]\t@ 0x28\n-\tvstr\td18, [sp, #456]\t@ 0x1c8\n-\tvcmpe.f64\td17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\tb18 <__gridxc_am05_MOD_am05_xscss+0x1a0>\n-\tvldr\td16, [pc, #40]\t@ b00 <__gridxc_am05_MOD_am05_xscss+0x188>\n-\tvcmpe.f64\td17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t11ee <__gridxc_am05_MOD_am05_xscss+0x876>\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvstr\td16, [sp, #32]\n-\tb.n\tb24 <__gridxc_am05_MOD_am05_xscss+0x1ac>\n+\tstrd\tr2, r3, [sp, #536]\t@ 0x218\n+\tmov.w\tr3, #0\n+\tstrd\tr3, r3, [sp, #432]\t@ 0x1b0\n+\tstrd\tr3, r3, [sp, #440]\t@ 0x1b8\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tldr\tr0, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tstr\tr3, [sp, #400]\t@ 0x190\n+\tstr\tr3, [sp, #416]\t@ 0x1a0\n+\tstr\tr3, [sp, #576]\t@ 0x240\n+\tstr\tr3, [sp, #544]\t@ 0x220\n+\tstrd\tr3, r3, [r2, #4]\n+\tstr\tr3, [r2, #12]\n+\tstrd\tr3, r3, [r4, #4]\n+\tstr\tr3, [r4, #12]\n+\tstrd\tr3, r3, [r1, #4]\n+\tstr\tr3, [r1, #12]\n+\tstrd\tr3, r3, [r0, #4]\n+\tstr\tr3, [r0, #12]\n+\tstrd\tr3, r3, [r5, #4]\n+\tstr\tr3, [r5, #12]\n+\tbge.n\tafc <__gridxc_am05_MOD_am05_xscss+0x16c>\n+\tvldr\td7, [pc, #120]\t@ b58 <__gridxc_am05_MOD_am05_xscss+0x1c8>\n+\tvcmpe.f64\td2, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.w\t138c <__gridxc_am05_MOD_am05_xscss+0x9fc>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td5, d1\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tb.n\tb08 <__gridxc_am05_MOD_am05_xscss+0x178>\n+\tvmov.f64\td5, d1\n+\tvldr\td6, [pc, #92]\t@ b60 <__gridxc_am05_MOD_am05_xscss+0x1d0>\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvldr\td6, [pc, #68]\t@ b50 <__gridxc_am05_MOD_am05_xscss+0x1c0>\n+\tvstr\td7, [sp, #592]\t@ 0x250\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvcmpe.f64\td5, d6\n+\tvstr\td7, [sp, #464]\t@ 0x1d0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbge.n\tb70 <__gridxc_am05_MOD_am05_xscss+0x1e0>\n+\tvldr\td7, [pc, #52]\t@ b58 <__gridxc_am05_MOD_am05_xscss+0x1c8>\n+\tvcmpe.f64\td5, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.w\t135c <__gridxc_am05_MOD_am05_xscss+0x9cc>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tb.n\tb7c <__gridxc_am05_MOD_am05_xscss+0x1ec>\n+\tnop.w\n \t.word\t0xa0000000\n \t.word\t0x3c9cd2b2\n+\t...\n \t.word\t0xa2000000\n \t.word\t0x426d1a94\n \t.word\t0xfeebc2a0\n \t.word\t0x39b4484b\n \t.word\t0xb089a027\n \t.word\t0x3fe9e9e1\n-\t.word\t0x0000015a\n+\t.word\t0x0000018c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvldr\td17, [pc, #840]\t@ e68 <__gridxc_am05_MOD_am05_xscss+0x4f0>\n-\tvstr\td17, [sp, #32]\n-\tvstr\td16, [sp, #464]\t@ 0x1d0\n-\tadd\tr3, sp, #424\t@ 0x1a8\n-\tvldr\td16, [sp, #32]\n+\tvldr\td6, [pc, #940]\t@ f20 <__gridxc_am05_MOD_am05_xscss+0x590>\n+\tvldr\td7, [pc, #944]\t@ f28 <__gridxc_am05_MOD_am05_xscss+0x598>\n+\tvstr\td6, [sp, #64]\t@ 0x40\n+\tvstr\td7, [sp, #600]\t@ 0x258\n+\tadd\tr3, sp, #560\t@ 0x230\n+\tvldr\td7, [sp, #64]\t@ 0x40\n \tmov\tr2, r3\n-\tadd\tr0, sp, #344\t@ 0x158\n-\tadd\tr1, sp, #240\t@ 0xf0\n+\tadd\tr0, sp, #480\t@ 0x1e0\n+\tadd\tr1, sp, #376\t@ 0x178\n \tmov\tsl, r3\n-\tstr\tr3, [sp, #184]\t@ 0xb8\n-\tvstr\td16, [sp, #336]\t@ 0x150\n-\tadd.w\tr8, sp, #360\t@ 0x168\n-\tstr\tr0, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #292]\t@ 0x124\n+\tvstr\td7, [sp, #472]\t@ 0x1d8\n+\tadd.w\tr8, sp, #496\t@ 0x1f0\n+\tstr\tr0, [sp, #268]\t@ 0x10c\n \tbl\t470 <__gridxc_am05_MOD_am05_xscss_ldapwc>\n-\tvldr\td18, [sp, #16]\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvldr\td15, [sp, #240]\t@ 0xf0\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tadd\tr3, sp, #328\t@ 0x148\n-\tadd\tr2, sp, #352\t@ 0x160\n-\tvdiv.f64\td17, d17, d18\n-\tstr\tr7, [sp, #4]\n-\tvmul.f64\td16, d15, d16\n-\tmov\tr7, r3\n-\tmovs\tr5, #8\n-\tmovs\tr4, #0\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tvldr\td16, [pc, #764]\t@ e70 <__gridxc_am05_MOD_am05_xscss+0x4f8>\n-\tvcmpe.f64\td11, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvstr\td17, [sp, #8]\n-\tbhi.n\tc02 <__gridxc_am05_MOD_am05_xscss+0x28a>\n-\tvldr\td16, [pc, #752]\t@ e78 <__gridxc_am05_MOD_am05_xscss+0x500>\n-\tvldr\td17, [r8]\n-\tvcmpe.f64\td17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t11b8 <__gridxc_am05_MOD_am05_xscss+0x840>\n-\tvldr\td20, [r7, #8]\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td17, [sp, #8]\n-\tvldr\td19, [sl]\n-\tvsub.f64\td16, d16, d20\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td15, [sp, #376]\t@ 0x178\n+\tadd\tr3, sp, #464\t@ 0x1d0\n+\tadd\tr2, sp, #488\t@ 0x1e8\n+\tstr\tr5, [sp, #4]\n+\tvdiv.f64\td7, d7, d6\n+\tmov\tr5, r3\n+\tmovs\tr7, #8\n+\tmovs\tr6, #0\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tvstr\td15, [sp, #24]\n+\tvstr\td7, [sp, #16]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d15, d7\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tvldr\td7, [pc, #860]\t@ f30 <__gridxc_am05_MOD_am05_xscss+0x5a0>\n+\tvcmpe.f64\td14, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.n\tc62 <__gridxc_am05_MOD_am05_xscss+0x2d2>\n+\tvldr\td7, [pc, #852]\t@ f38 <__gridxc_am05_MOD_am05_xscss+0x5a8>\n+\tvldr\td6, [r8]\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.w\t131e <__gridxc_am05_MOD_am05_xscss+0x98e>\n+\tvldr\td4, [r5, #8]\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td5, [sp, #24]\n+\tvldr\td6, [sp, #16]\n+\tvsub.f64\td7, d7, d4\n \tldr\tr3, [sp, #4]\n-\tvmul.f64\td18, d17, d15\n-\tvldr\td17, [r9]\n-\tvmul.f64\td16, d16, d15\n-\tvfma.f64\td16, d19, d20\n-\tvfma.f64\td17, d11, d18\n-\tvstr\td16, [r3]\n-\tvstr\td17, [r9]\n-\tvstr\td16, [r6]\n-\tsubs\tr5, #8\n-\tcmn.w\tr5, #8\n-\tbeq.w\t1122 <__gridxc_am05_MOD_am05_xscss+0x7aa>\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d5\n+\tvldr\td5, [sl]\n+\tvmla.f64\td7, d4, d5\n+\tvstr\td7, [r3]\n+\tvstr\td7, [r4]\n+\tvldr\td7, [r9]\n+\tvmla.f64\td7, d6, d14\n+\tvstr\td7, [r9]\n+\tsubs\tr7, #8\n+\tcmn.w\tr7, #8\n+\tbeq.w\t1286 <__gridxc_am05_MOD_am05_xscss+0x8f6>\n \tldr\tr3, [sp, #4]\n \tadd.w\tsl, sl, #8\n-\tvldr\td16, [pc, #656]\t@ e70 <__gridxc_am05_MOD_am05_xscss+0x4f8>\n-\tsubs\tr7, #8\n+\tvldr\td7, [pc, #752]\t@ f30 <__gridxc_am05_MOD_am05_xscss+0x5a0>\n+\tsubs\tr5, #8\n \tadds\tr3, #8\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tadds\tr6, #8\n-\tadd.w\tr8, r8, #8\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tadds\tr4, #8\n-\tvldmia\tr3!, {d11}\n-\tvcmpe.f64\td11, d16\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\tb84 <__gridxc_am05_MOD_am05_xscss+0x20c>\n-\tvldr\td0, [pc, #636]\t@ e80 <__gridxc_am05_MOD_am05_xscss+0x508>\n-\tvadd.f64\td10, d11, d11\n-\tvmov.f64\td14, #104\t@ 0x3f400000 0.750\n+\tadd.w\tr8, r8, #8\n+\tadds\tr6, #8\n+\tvldmia\tr3!, {d14}\n+\tvcmpe.f64\td14, d7\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\tbe0 <__gridxc_am05_MOD_am05_xscss+0x250>\n+\tvldr\td0, [pc, #732]\t@ f40 <__gridxc_am05_MOD_am05_xscss+0x5b0>\n+\tvadd.f64\td10, d14, d14\n \tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td0, d11, d0\n+\tvmul.f64\td0, d14, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n \tvmov.f64\td8, d0\n-\tvldr\td0, [pc, #616]\t@ e88 <__gridxc_am05_MOD_am05_xscss+0x510>\n+\tvldr\td0, [pc, #716]\t@ f48 <__gridxc_am05_MOD_am05_xscss+0x5b8>\n \tvmul.f64\td9, d10, d9\n \tvmul.f64\td0, d10, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvnmul.f64\td14, d0, d14\n-\tvneg.f64\td16, d0\n-\tvstr\td0, [sp, #120]\t@ 0x78\n-\tvmul.f64\td9, d9, d14\n-\tvstr\td16, [sp, #112]\t@ 0x70\n-\tvldr\td13, [r8]\n-\tadd\tr1, sp, #248\t@ 0xf8\n-\tvldr\td16, [pc, #580]\t@ e90 <__gridxc_am05_MOD_am05_xscss+0x518>\n-\tadd\tr0, sp, #256\t@ 0x100\n-\tvsqrt.f64\td17, d13\n-\tvmul.f64\td12, d13, d13\n-\tvmul.f64\td16, d13, d16\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [sp, #256]\t@ 0x100\n+\tvmov.f64\td7, #104\t@ 0x3f400000 0.750\n+\tvstr\td0, [sp, #224]\t@ 0xe0\n+\tvnmul.f64\td7, d0, d7\n+\tvmul.f64\td9, d9, d7\n+\tvstr\td7, [sp, #32]\n+\tvneg.f64\td7, d0\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n+\tvldr\td11, [r8]\n+\tadd\tr1, sp, #384\t@ 0x180\n+\tvldr\td7, [pc, #672]\t@ f50 <__gridxc_am05_MOD_am05_xscss+0x5c0>\n+\tadd\tr0, sp, #392\t@ 0x188\n+\tvsqrt.f64\td6, d11\n+\tvmul.f64\td13, d11, d11\n+\tvmul.f64\td7, d11, d7\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [sp, #392]\t@ 0x188\n \tbl\t0 <__gridxc_am05_MOD_am05_xscss_lambertw>\n-\tvldr\td16, [pc, #560]\t@ e98 <__gridxc_am05_MOD_am05_xscss+0x520>\n-\tvcmpe.f64\td13, d16\n+\tvldr\td7, [pc, #652]\t@ f58 <__gridxc_am05_MOD_am05_xscss+0x5c8>\n+\tvcmpe.f64\td11, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t11e4 <__gridxc_am05_MOD_am05_xscss+0x86c>\n-\tvldr\td0, [sp, #248]\t@ 0xf8\n+\tbmi.w\t1352 <__gridxc_am05_MOD_am05_xscss+0x9c2>\n+\tvldr\td0, [sp, #384]\t@ 0x180\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n \tvmul.f64\td0, d0, d0\n-\tvldr\td16, [pc, #540]\t@ ea0 <__gridxc_am05_MOD_am05_xscss+0x528>\n-\tvldr\td17, [pc, #544]\t@ ea8 <__gridxc_am05_MOD_am05_xscss+0x530>\n-\tvmul.f64\td0, d0, d16\n-\tvdiv.f64\td19, d0, d13\n-\tvmul.f64\td17, d19, d17\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td17, d12, d17\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvldr\td23, [sp, #48]\t@ 0x30\n-\tadds\tr1, r3, r4\n-\tvldr\td5, [pc, #516]\t@ eb0 <__gridxc_am05_MOD_am05_xscss+0x538>\n-\tvadd.f64\td21, d17, d16\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tvldr\td25, [r1]\n-\tvmul.f64\td20, d12, d5\n+\tvldr\td7, [pc, #632]\t@ f60 <__gridxc_am05_MOD_am05_xscss+0x5d0>\n+\tvldr\td2, [pc, #636]\t@ f68 <__gridxc_am05_MOD_am05_xscss+0x5d8>\n+\tvmul.f64\td0, d0, d7\n+\tvdiv.f64\td1, d0, d11\n+\tvmul.f64\td2, d1, d2\n+\tvmul.f64\td2, d2, d2\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tvmul.f64\td4, d13, d2\n+\tvldr\td3, [sp, #136]\t@ 0x88\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td5, [sp, #16]\n+\tadds\tr1, r3, r6\n+\tvldr\td15, [pc, #612]\t@ f78 <__gridxc_am05_MOD_am05_xscss+0x5e8>\n+\tvadd.f64\td0, d4, d7\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvmul.f64\td5, d5, d3\n+\tvldr\td6, [r1]\n+\tvmul.f64\td3, d13, d15\n+\tvstr\td4, [sp, #112]\t@ 0x70\n \tldr\tr2, [r3, #0]\n-\tadd.w\tr3, r4, #480\t@ 0x1e0\n-\tvsqrt.f64\td22, d21\n+\tadd.w\tr3, r6, #616\t@ 0x268\n+\tvstr\td6, [sp, #104]\t@ 0x68\n \tadd.w\tr0, sp, r3\n-\tvadd.f64\td2, d20, d16\n-\tvldr\td18, [r0, #-24]\t@ 0xffffffe8\n-\tvsub.f64\td28, d16, d18\n-\tvsqrt.f64\td24, d22\n-\tvldr\td22, [sp, #8]\n-\tvmul.f64\td26, d22, d23\n-\tvldr\td22, [r9]\n-\tvldr\td23, [fp]\n-\tvmul.f64\td26, d26, d25\n-\tvfma.f64\td22, d10, d26\n-\tvstr\td22, [r9]\n-\tvmov.f64\td22, d16\n-\tvmul.f64\td26, d19, d24\n-\tvfma.f64\td22, d20, d26\n-\tvmov.f64\td26, d18\n-\tvdiv.f64\td27, d2, d22\n-\tvfma.f64\td26, d28, d27\n-\tvfma.f64\td23, d26, d9\n-\tvstr\td23, [fp]\n+\tvmul.f64\td5, d5, d6\n+\tvldr\td6, [r9]\n+\tvldr\td2, [r0, #-24]\t@ 0xffffffe8\n+\tvmla.f64\td6, d5, d10\n+\tvmov.f64\td10, d7\n+\tvadd.f64\td5, d3, d7\n+\tvsub.f64\td4, d7, d2\n+\tvstr\td2, [sp, #96]\t@ 0x60\n+\tvstr\td5, [sp, #88]\t@ 0x58\n+\tvstr\td6, [r9]\n+\tvsqrt.f64\td6, d0\n+\tvsqrt.f64\td6, d6\n+\tvmov.f64\td12, d6\n+\tvmul.f64\td6, d1, d6\n+\tvmla.f64\td10, d6, d3\n+\tvmov.f64\td6, d2\n+\tvdiv.f64\td15, d5, d10\n+\tvstr\td10, [sp, #8]\n+\tvmla.f64\td6, d4, d15\n+\tvstr\td15, [sp, #120]\t@ 0x78\n+\tvldr\td15, [fp]\n+\tvmla.f64\td15, d6, d9\n+\tvstr\td6, [sp, #128]\t@ 0x80\n+\tvstr\td15, [fp]\n \tcmp\tr2, #0\n-\tbeq.w\tbce <__gridxc_am05_MOD_am05_xscss+0x256>\n-\tvdiv.f64\td29, d24, d21\n+\tbeq.w\tc2e <__gridxc_am05_MOD_am05_xscss+0x29e>\n+\tvsub.f64\td9, d3, d7\n+\tvldr\td10, [sp, #112]\t@ 0x70\n+\tvdiv.f64\td3, d12, d0\n+\tvmov.f64\td6, #120\t@ 0x3fc00000 1.5\n+\tvstr\td12, [sp, #248]\t@ 0xf8\n \tvadd.f64\td8, d8, d8\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tvsub.f64\td20, d20, d16\n-\tvldr\td7, [pc, #396]\t@ eb8 <__gridxc_am05_MOD_am05_xscss+0x540>\n-\tvmul.f64\td3, d22, d22\n-\tadds\tr1, r3, r5\n-\tvldr\td9, [pc, #416]\t@ ed8 <__gridxc_am05_MOD_am05_xscss+0x560>\n-\tvmul.f64\td8, d8, d8\n-\tvldr\td6, [sp, #352]\t@ 0x160\n-\tvldr\td1, [sp, #248]\t@ 0xf8\n-\tvmov.f64\td30, #0\t@ 0x40000000 2.0\n-\tvldr\td23, [r1]\n+\tldr\tr3, [sp, #268]\t@ 0x10c\n \tcmp\tr2, #1\n-\tvstr\td6, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td0, d8, d11\n-\tvmul.f64\td8, d18, d18\n-\tvstr\td23, [sp, #136]\t@ 0x88\n-\tvmov.f64\td23, #120\t@ 0x3fc00000 1.5\n-\tvadd.f64\td4, d1, d16\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td31, d17, d23\n-\tvldr\td23, [sp, #344]\t@ 0x158\n-\tvmul.f64\td7, d8, d7\n-\tvstr\td8, [sp, #224]\t@ 0xe0\n-\tadd.w\tr0, r3, r4\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tvdiv.f64\td10, d16, d4\n-\tvstr\td23, [sp, #128]\t@ 0x80\n-\tvldr\td23, [r7, #8]\n-\tadd.w\tip, r3, r4\n-\tvnmul.f64\td9, d7, d9\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tvstr\td31, [sp, #192]\t@ 0xc0\n-\tvadd.f64\td31, d31, d16\n-\tvsub.f64\td8, d25, d23\n-\tvldr\td23, [sp, #128]\t@ 0x80\n-\tadd.w\tlr, r3, r4\n-\tvstr\td8, [sp, #144]\t@ 0x90\n-\tvstr\td29, [sp, #232]\t@ 0xe8\n-\tvsub.f64\td29, d27, d16\n-\tvmul.f64\td29, d29, d7\n-\tvneg.f64\td7, d7\n-\tvstr\td7, [sp, #208]\t@ 0xd0\n-\tvldr\td7, [sp, #32]\n-\tvmul.f64\td8, d6, d7\n-\tvldr\td7, [sp, #24]\n-\tvmul.f64\td6, d9, d15\n-\tvfma.f64\td8, d7, d23\n-\tvldr\td23, [sp, #136]\t@ 0x88\n-\tvldr\td7, [sp, #144]\t@ 0x90\n-\tvmul.f64\td23, d23, d15\n-\tvmul.f64\td23, d23, d7\n-\tvdiv.f64\td7, d6, d0\n-\tvdiv.f64\td6, d24, d21\n-\tvstr\td7, [lr]\n-\tvmul.f64\td7, d2, d10\n-\tvmul.f64\td7, d7, d31\n-\tvnmul.f64\td7, d6, d7\n-\tvldr\td6, [sl]\n-\tvfma.f64\td7, d20, d24\n-\tvmov.f64\td20, d30\n-\tvfma.f64\td23, d6, d8\n-\tvfma.f64\td20, d7, d19\n-\tvdiv.f64\td7, d5, d3\n-\tvmul.f64\td20, d7, d20\n-\tvldr\td7, [sp, #8]\n-\tvfma.f64\td29, d28, d20\n-\tvldr\td28, [pc, #156]\t@ ec0 <__gridxc_am05_MOD_am05_xscss+0x548>\n-\tvstr\td20, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td20, d15, d28\n-\tvmul.f64\td8, d12, d28\n-\tvmul.f64\td20, d20, d12\n-\tvnmul.f64\td20, d9, d20\n-\tvfma.f64\td20, d7, d23\n-\tvmul.f64\td23, d29, d14\n-\tvstr\td20, [r6]\n-\tvdiv.f64\td20, d23, d0\n-\tvldr\td0, [sp, #112]\t@ 0x70\n-\tvstr\td20, [ip]\n-\tvmul.f64\td20, d8, d14\n-\tvnmul.f64\td20, d29, d20\n-\tvfma.f64\td20, d26, d0\n-\tvstr\td20, [r0]\n-\tbeq.w\tbce <__gridxc_am05_MOD_am05_xscss+0x256>\n-\tb.n\tef0 <__gridxc_am05_MOD_am05_xscss+0x578>\n-\tnop\n+\tadd.w\tr1, r3, r7\n+\tldr\tr3, [sp, #264]\t@ 0x108\n+\tvmul.f64\td8, d8, d8\n+\tadd.w\tr0, r3, r6\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tvldr\td2, [r1]\n+\tadd.w\tip, r3, r6\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tvmul.f64\td8, d8, d14\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tadd.w\tlr, r3, r6\n+\tvstr\td8, [sp, #216]\t@ 0xd8\n+\tvldr\td8, [sp, #384]\t@ 0x180\n+\tvstr\td8, [sp, #312]\t@ 0x138\n+\tvadd.f64\td8, d8, d7\n+\tvstr\td8, [sp, #320]\t@ 0x140\n+\tvdiv.f64\td8, d7, d8\n+\tvstr\td3, [sp, #256]\t@ 0x100\n+\tvmul.f64\td3, d10, d6\n+\tvldr\td6, [sp, #8]\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td3, [sp, #328]\t@ 0x148\n+\tvadd.f64\td3, d3, d7\n+\tvmov.f64\td5, d6\n+\tvldr\td6, [sp, #96]\t@ 0x60\n+\tvstr\td3, [sp, #232]\t@ 0xe8\n+\tvldr\td3, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td5, [sp, #352]\t@ 0x160\n+\tvmov.f64\td12, d3\n+\tvldr\td3, [sp, #480]\t@ 0x1e0\n+\tvmov.f64\td15, d6\n+\tvldr\td6, [pc, #312]\t@ f70 <__gridxc_am05_MOD_am05_xscss+0x5e0>\n+\tvmov.f64\td10, d3\n+\tvstr\td12, [sp, #336]\t@ 0x150\n+\tvmul.f64\td6, d15, d6\n+\tvstr\td15, [sp, #368]\t@ 0x170\n+\tvldr\td15, [pc, #300]\t@ f78 <__gridxc_am05_MOD_am05_xscss+0x5e8>\n+\tvstr\td10, [sp, #272]\t@ 0x110\n+\tvdiv.f64\td15, d15, d5\n+\tvldr\td5, [r5, #8]\n+\tvstr\td15, [sp, #296]\t@ 0x128\n+\tvldr\td15, [sp, #104]\t@ 0x68\n+\tvsub.f64\td3, d15, d5\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvmul.f64\td5, d12, d5\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvstr\td3, [sp, #240]\t@ 0xf0\n+\tvldr\td3, [pc, #296]\t@ fa0 <__gridxc_am05_MOD_am05_xscss+0x610>\n+\tvmla.f64\td5, d12, d10\n+\tvldr\td10, [sp, #24]\n+\tvnmul.f64\td3, d6, d3\n+\tvmov.f64\td15, d3\n+\tvmul.f64\td3, d2, d10\n+\tvldr\td2, [sp, #240]\t@ 0xf0\n+\tvstr\td5, [sp, #304]\t@ 0x130\n+\tvmul.f64\td12, d15, d10\n+\tvstr\td15, [sp, #152]\t@ 0x98\n+\tvldr\td5, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td3, d3, d2\n+\tvldr\td15, [sp, #88]\t@ 0x58\n+\tvldr\td2, [sp, #232]\t@ 0xe8\n+\tvdiv.f64\td5, d12, d5\n+\tvstr\td5, [lr]\n+\tvmul.f64\td5, d15, d8\n+\tvldr\td15, [sp, #248]\t@ 0xf8\n+\tvmul.f64\td5, d5, d2\n+\tvldr\td2, [sp, #256]\t@ 0x100\n+\tvmul.f64\td5, d5, d2\n+\tvldr\td2, [sp, #296]\t@ 0x128\n+\tvnmls.f64\td5, d9, d15\n+\tvmov.f64\td9, #0\t@ 0x40000000 2.0\n+\tvldr\td15, [sp, #32]\n+\tvmla.f64\td9, d5, d1\n+\tvmul.f64\td9, d9, d2\n+\tvstr\td9, [sp, #360]\t@ 0x168\n+\tvmul.f64\td9, d4, d9\n+\tvldr\td4, [sp, #120]\t@ 0x78\n+\tvsub.f64\td5, d4, d7\n+\tvldr\td4, [pc, #140]\t@ f80 <__gridxc_am05_MOD_am05_xscss+0x5f0>\n+\tvmul.f64\td2, d13, d4\n+\tvmla.f64\td9, d5, d6\n+\tvmul.f64\td5, d10, d4\n+\tvldr\td4, [sp, #152]\t@ 0x98\n+\tvneg.f64\td6, d6\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvmul.f64\td5, d5, d13\n+\tvldr\td2, [sp, #304]\t@ 0x130\n+\tvmul.f64\td12, d9, d15\n+\tvmul.f64\td5, d5, d4\n+\tb.n\tfb0 <__gridxc_am05_MOD_am05_xscss+0x620>\n \t.word\t0xb089a027\n \t.word\t0x3fe9e9e1\n+\t...\n \t.word\t0x97d889bc\n \t.word\t0x3c9cd2b2\n \t.word\t0xfeebc2a0\n \t.word\t0x39b4484b\n \t.word\t0x2e9d68cd\n \t.word\t0x404d9bdb\n \t.word\t0xa4aeacc4\n@@ -1040,313 +1091,355 @@\n \t.word\t0x3fca20bd\n \t.word\t0x80000000\n \t.word\t0x3d06849b\n \t.word\t0x49123ef6\n \t.word\t0x40071374\n \t.word\t0xfacd5803\n \t.word\t0x3fb5e2a7\n-\t.word\t0x8db8bac7\n-\t.word\t0x3fe6f006\n \t.word\t0x8d4fdf3b\n \t.word\t0x40166e97\n+\t.word\t0x8db8bac7\n+\t.word\t0x3fe6f006\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n-\t.word\t0x2e0e3043\n-\t.word\t0x404f731d\n \t.word\t0x8db8bac7\n \t.word\t0x4006f006\n-\t.word\t0x3dd97f64\n-\t.word\t0x3fc85879\n+\t.word\t0x2e0e3043\n+\t.word\t0x404f731d\n \t.word\t0x8d4fdf3b\n \t.word\t0x40066e97\n+\t.word\t0x3dd97f64\n+\t.word\t0x3fc85879\n \t.word\t0xf98d728b\n \t.word\t0x3fe428a2\n-\tvfms.f64\td25, d12, d9\n-\tvmul.f64\td19, d19, d5\n-\tvmov.f64\td5, d21\n-\tvmul.f64\td21, d21, d21\n-\tvfma.f64\td5, d31, d10\n-\tvsub.f64\td7, d30, d1\n-\tvmul.f64\td31, d3, d22\n-\tvmov.f64\td0, d26\n-\tvmov.f64\td26, #8\t@ 0x40400000 3.0\n-\tvldr\td20, [sp, #144]\t@ 0x90\n-\tvdiv.f64\td23, d24, d21\n-\tvldr\td21, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td24, d10, d10\n-\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n-\tvadd.f64\td30, d17, d30\n-\tvfms.f64\td20, d12, d9\n-\tvmov.f64\td1, d25\n-\tvmul.f64\td25, d4, d4\n-\tvmul.f64\td21, d21, d19\n-\tvmul.f64\td7, d7, d10\n-\tvmul.f64\td19, d22, d19\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td28, d13, d28\n-\tvfnms.f64\td0, d12, d29\n-\tvmul.f64\td25, d25, d4\n-\tadds\tr2, r3, r5\n-\tvmul.f64\td21, d21, d5\n-\tvsub.f64\td5, d16, d27\n-\tvldr\td27, [sp, #208]\t@ 0xd0\n-\tsubs\tr5, #8\n-\tldr\tr3, [sp, #188]\t@ 0xbc\n-\tvstr\td20, [sp, #112]\t@ 0x70\n-\tvadd.f64\td3, d27, d27\n-\tadds\tr0, r3, r4\n-\tvdiv.f64\td27, d7, d25\n-\tvmov.f64\td25, #20\t@ 0x40a00000 5.0\n-\tvfma.f64\td25, d17, d26\n-\tvmul.f64\td26, d17, d10\n-\tadd.w\tr3, r4, #480\t@ 0x1e0\n-\tadd.w\tr1, sp, r3\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tvmla.f64\td24, d26, d24\n-\tvldr\td20, [r1, #-88]\t@ 0xffffffa8\n-\tvfnms.f64\td20, d12, d28\n-\tvfma.f64\td16, d25, d26\n-\tvmov.f64\td25, #240\t@ 0xbf800000 -1.0\n-\tvfms.f64\td25, d30, d17\n-\tvldr\td26, [sp, #192]\t@ 0xc0\n-\tvldr\td17, [pc, #-224]\t@ ec8 <__gridxc_am05_MOD_am05_xscss+0x550>\n-\tvfma.f64\td25, d26, d24\n-\tvmul.f64\td17, d18, d17\n-\tvmul.f64\td20, d20, d13\n-\tvmul.f64\td19, d19, d23\n-\tvldr\td23, [r1, #-104]\t@ 0xffffff98\n-\tvsub.f64\td23, d8, d23\n-\tvldr\td8, [r2]\n-\tvsub.f64\td8, d15, d8\n-\tvmul.f64\td8, d8, d10\n-\tvfma.f64\td25, d16, d27\n-\tvadd.f64\td16, d12, d12\n-\tvmul.f64\td8, d8, d9\n-\tvmul.f64\td16, d16, d21\n-\tvnmul.f64\td25, d25, d19\n-\tvldr\td19, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td25, d21, d16\n-\tvldr\td16, [pc, #-284]\t@ ed0 <__gridxc_am05_MOD_am05_xscss+0x558>\n-\tvmul.f64\td17, d17, d19\n-\tvldr\td19, [pc, #-284]\t@ ed8 <__gridxc_am05_MOD_am05_xscss+0x560>\n-\tvmul.f64\td12, d12, d16\n-\tvmul.f64\td5, d5, d17\n-\tvmul.f64\td12, d12, d22\n-\tvnmul.f64\td21, d21, d12\n-\tvmul.f64\td12, d17, d19\n-\tvfma.f64\td21, d2, d25\n-\tvldr\td17, [sp, #136]\t@ 0x88\n-\tvmul.f64\td12, d12, d20\n-\tvfma.f64\td12, d23, d9\n-\tvdiv.f64\td16, d21, d31\n-\tvldr\td21, [sp, #216]\t@ 0xd8\n-\tvfms.f64\td5, d21, d3\n-\tvmul.f64\td12, d12, d15\n-\tvfma.f64\td12, d6, d1\n-\tvsub.f64\td6, d15, d6\n-\tvmul.f64\td13, d6, d17\n-\tvldr\td17, [pc, #-344]\t@ ee0 <__gridxc_am05_MOD_am05_xscss+0x568>\n-\tvmul.f64\td18, d18, d17\n-\tvldr\td17, [r3]\n-\tvstr\td17, [sp, #136]\t@ 0x88\n-\tvfma.f64\td5, d16, d18\n-\tvldr\td16, [sp, #120]\t@ 0x78\n-\tvmul.f64\td20, d20, d5\n-\tvfma.f64\td20, d23, d29\n-\tvmul.f64\td20, d20, d14\n-\tvfma.f64\td20, d0, d16\n-\tvldr\td0, [sp, #16]\n-\tvstr\td20, [r0]\n+\tvldr\td4, [sp, #216]\t@ 0xd8\n+\tvdiv.f64\td4, d12, d4\n+\tvldr\td12, [sp, #208]\t@ 0xd0\n+\tvstr\td4, [ip]\n+\tvldr\td4, [sl]\n+\tvmla.f64\td3, d2, d4\n+\tvstr\td4, [sp, #216]\t@ 0xd8\n+\tvldr\td4, [sp, #16]\n+\tvldr\td2, [sp, #296]\t@ 0x128\n+\tvnmls.f64\td5, d3, d4\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvstr\td5, [r4]\n+\tvmul.f64\td5, d2, d15\n+\tvmul.f64\td5, d5, d9\n+\tvnmls.f64\td5, d4, d12\n+\tvstr\td5, [r0]\n+\tbeq.w\tc2e <__gridxc_am05_MOD_am05_xscss+0x29e>\n+\tvmul.f64\td5, d0, d0\n+\tvldr\td15, [sp, #248]\t@ 0xf8\n+\tvldr\td3, [pc, #-136]\t@ f78 <__gridxc_am05_MOD_am05_xscss+0x5e8>\n+\tvmov.f64\td12, #0\t@ 0x40000000 2.0\n+\tvldr\td10, [sp, #112]\t@ 0x70\n+\tvadd.f64\td6, d6, d6\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tvmul.f64\td4, d1, d3\n+\tvldr\td1, [sp, #312]\t@ 0x138\n+\tvdiv.f64\td3, d15, d5\n+\tadds\tr1, r3, r6\n+\tadd.w\tr3, r6, #616\t@ 0x268\n+\tvsub.f64\td1, d12, d1\n+\tvadd.f64\td12, d10, d12\n+\tadd.w\tr2, sp, r3\n+\tvstr\td1, [sp, #208]\t@ 0xd0\n+\tvldr\td1, [sp, #232]\t@ 0xe8\n+\tvstr\td12, [sp, #296]\t@ 0x128\n+\tvmov.f64\td12, d0\n+\tvldr\td0, [sp, #256]\t@ 0x100\n+\tvmla.f64\td12, d1, d8\n+\tvldr\td1, [sp, #8]\n+\tvmul.f64\td8, d8, d8\n+\tvmul.f64\td5, d0, d4\n+\tvmul.f64\td4, d1, d4\n+\tvldr\td1, [sp, #352]\t@ 0x160\n+\tvmul.f64\td5, d12, d5\n+\tvmul.f64\td3, d3, d4\n+\tvldr\td4, [sp, #8]\n+\tvmul.f64\td12, d1, d4\n+\tvldr\td1, [sp, #360]\t@ 0x168\n+\tvmul.f64\td0, d6, d1\n+\tvldr\td1, [pc, #-244]\t@ f80 <__gridxc_am05_MOD_am05_xscss+0x5f0>\n+\tvldr\td6, [sp, #128]\t@ 0x80\n+\tvmov.f64\td15, d12\n+\tvmul.f64\td4, d11, d1\n+\tvldr\td1, [sp, #120]\t@ 0x78\n+\tvnmls.f64\td6, d13, d9\n+\tvsub.f64\td12, d7, d1\n+\tvstr\td12, [sp, #120]\t@ 0x78\n+\tvldr\td12, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td12, d6, d12\n+\tvldr\td6, [r2, #-88]\t@ 0xffffffa8\n+\tvnmls.f64\td6, d4, d13\n+\tvmul.f64\td11, d6, d11\n+\tvldr\td6, [r2, #-104]\t@ 0xffffff98\n+\tvsub.f64\td1, d2, d6\n+\tvmul.f64\td9, d1, d9\n+\tvstr\td1, [sp, #112]\t@ 0x70\n+\tvldr\td1, [sp, #320]\t@ 0x140\n+\tvmul.f64\td6, d1, d1\n+\tvmov.f64\td2, d9\n+\tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td6, d6, d1\n+\tvldr\td1, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td4, d1, d9\n+\tvdiv.f64\td1, d4, d6\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tvmov.f64\td6, #20\t@ 0x40a00000 5.0\n+\tvmla.f64\td6, d10, d4\n+\tvmul.f64\td4, d10, d9\n+\tvmla.f64\td8, d4, d8\n+\tvmla.f64\td7, d6, d4\n+\tvldr\td6, [sp, #296]\t@ 0x128\n+\tvmov.f64\td4, #240\t@ 0xbf800000 -1.0\n+\tvmls.f64\td4, d6, d10\n+\tvldr\td6, [sp, #328]\t@ 0x148\n+\tvldr\td10, [sp, #120]\t@ 0x78\n+\tvmla.f64\td4, d8, d6\n+\tvldr\td6, [sp, #8]\n+\tvmla.f64\td4, d1, d7\n+\tvadd.f64\td7, d13, d13\n+\tvldr\td1, [sp, #152]\t@ 0x98\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td8, d13, d1\n+\tvmul.f64\td4, d4, d3\n+\tvldr\td3, [sp, #88]\t@ 0x58\n+\tvnmls.f64\td4, d7, d5\n+\tvldr\td7, [pc, #-420]\t@ f88 <__gridxc_am05_MOD_am05_xscss+0x5f8>\n+\tvmul.f64\td7, d13, d7\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td7, d7, d5\n+\tvldr\td5, [pc, #-428]\t@ f90 <__gridxc_am05_MOD_am05_xscss+0x600>\n+\tvnmls.f64\td7, d4, d3\n+\tvldr\td4, [sp, #96]\t@ 0x60\n+\tvldr\td3, [sp, #32]\n+\tvmul.f64\td5, d4, d5\n+\tvdiv.f64\td6, d7, d15\n+\tvldr\td7, [sp, #368]\t@ 0x170\n+\tvmul.f64\td13, d5, d7\n+\tvmov.f64\td7, d0\n+\tvldr\td5, [pc, #-456]\t@ f98 <__gridxc_am05_MOD_am05_xscss+0x608>\n+\tvldr\td0, [sp, #40]\t@ 0x28\n+\tvmul.f64\td5, d4, d5\n+\tvnmls.f64\td7, d10, d13\n+\tvmov.f64\td10, d2\n+\tvmla.f64\td7, d6, d5\n+\tvmla.f64\td10, d7, d11\n+\tvmla.f64\td12, d10, d3\n+\tvstr\td12, [r1]\n+\tldr\tr3, [sp, #288]\t@ 0x120\n+\tvldr\td6, [r3]\n+\tvstr\td6, [sp, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td14, [sp, #128]\t@ 0x80\n-\tvmov.f64\td18, d0\n-\tvmov.f64\td0, d14\n-\tvstr\td18, [sp, #120]\t@ 0x78\n+\tvmov.f64\td12, d0\n+\tvldr\td0, [sp, #272]\t@ 0x110\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [sp, #136]\t@ 0x88\n-\tvmov.f64\td19, d0\n-\tvldr\td20, [pc, #-416]\t@ ee8 <__gridxc_am05_MOD_am05_xscss+0x570>\n-\tvldr\td18, [sp, #16]\n-\tvmul.f64\td17, d17, d17\n-\tvldr\td21, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td16, d14, d21\n-\tvldr\td14, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td17, d17, d20\n-\tvmov.f64\td0, d14\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td17, d17, d18\n-\tvnmul.f64\td16, d16, d16\n-\tvmul.f64\td17, d17, d18\n-\tvldr\td18, [sp, #120]\t@ 0x78\n-\tvmul.f64\td17, d17, d18\n-\tvfma.f64\td16, d18, d17\n-\tvstr\td16, [sp, #120]\t@ 0x78\n+\tvldr\td15, [sp, #336]\t@ 0x150\n+\tvstr\td0, [sp, #8]\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvmov.f64\td18, d0\n-\tvmov.f64\td0, d11\n-\tvmul.f64\td17, d14, d16\n-\tvldr\td16, [sp, #120]\t@ 0x78\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td17, d17, d18\n-\tvfms.f64\td16, d18, d17\n-\tvstr\td16, [sp, #120]\t@ 0x78\n+\tvmov.f64\td10, d0\n+\tvmov.f64\td0, d14\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n+\tvldr\td7, [pc, #-536]\t@ fa0 <__gridxc_am05_MOD_am05_xscss+0x610>\n+\tvldr\td3, [sp, #272]\t@ 0x110\n \tvmul.f64\td0, d0, d0\n-\tvldr\td16, [sp, #120]\t@ 0x78\n-\tvldr\td20, [sp, #112]\t@ 0x70\n-\tcmn.w\tr5, #8\n-\tvldr\td7, [sp, #8]\n+\tvldr\td5, [sp, #8]\n+\tvmul.f64\td13, d13, d7\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvldr\td1, [sp, #152]\t@ 0x98\n+\tvmul.f64\td14, d0, d14\n+\tvldr\td0, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td7, d3, d7\n+\tvldr\td3, [sp, #240]\t@ 0xf0\n+\tldr\tr3, [sp, #292]\t@ 0x124\n+\tvldr\td6, [sp, #32]\n+\tvsub.f64\td2, d3, d8\n+\tvldr\td3, [sp, #112]\t@ 0x70\n+\tvmul.f64\td4, d7, d5\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tadds\tr2, r3, r7\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td3, d3, d1\n \tldr\tr3, [sp, #4]\n-\tvmul.f64\td0, d0, d11\n-\tvdiv.f64\td17, d8, d0\n-\tvmul.f64\td16, d17, d16\n-\tvfma.f64\td16, d13, d20\n-\tvfma.f64\td12, d7, d16\n-\tvstr\td12, [r3]\n-\tbne.w\tbd8 <__gridxc_am05_MOD_am05_xscss+0x260>\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tldrd\tr2, r3, [sp, #296]\t@ 0x128\n+\tvmul.f64\td7, d15, d5\n+\tvmla.f64\td3, d13, d11\n+\tvldr\td15, [sp, #104]\t@ 0x68\n+\tvmul.f64\td4, d4, d4\n+\tsubs\tr7, #8\n+\tcmn.w\tr7, #8\n+\tvsub.f64\td8, d15, d8\n+\tvmul.f64\td7, d7, d10\n+\tvldr\td10, [sp, #24]\n+\tvmul.f64\td5, d8, d0\n+\tvmla.f64\td5, d3, d10\n+\tvsub.f64\td3, d10, d0\n+\tvldr\td0, [sp, #344]\t@ 0x158\n+\tvmul.f64\td3, d3, d0\n+\tvmul.f64\td3, d3, d2\n+\tvldr\td2, [r2]\n+\tvsub.f64\td2, d10, d2\n+\tvmul.f64\td2, d2, d9\n+\tvmul.f64\td2, d2, d1\n+\tvdiv.f64\td1, d2, d14\n+\tvldr\td2, [pc, #-684]\t@ fa8 <__gridxc_am05_MOD_am05_xscss+0x618>\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td6, d6, d12\n+\tvnmls.f64\td4, d6, d12\n+\tvmls.f64\td4, d7, d7\n+\tvmla.f64\td3, d4, d1\n+\tvldr\td4, [sp, #16]\n+\tvmla.f64\td5, d3, d4\n+\tvstr\td5, [r3]\n+\tbne.w\tc38 <__gridxc_am05_MOD_am05_xscss+0x2a8>\n+\tldr\tr1, [sp, #176]\t@ 0xb0\n+\tldrd\tr2, r3, [sp, #432]\t@ 0x1b0\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tldrd\tr2, r3, [sp, #312]\t@ 0x138\n+\tldr\tr1, [sp, #180]\t@ 0xb4\n+\tldrd\tr2, r3, [sp, #448]\t@ 0x1c0\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n+\tldr\tr1, [sp, #184]\t@ 0xb8\n+\tldrd\tr2, r3, [sp, #400]\t@ 0x190\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #96]\t@ 0x60\n-\tldrd\tr2, r3, [sp, #280]\t@ 0x118\n+\tldr\tr1, [sp, #188]\t@ 0xbc\n+\tldrd\tr2, r3, [sp, #416]\t@ 0x1a0\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #100]\t@ 0x64\n-\tldrd\tr2, r3, [sp, #304]\t@ 0x130\n+\tldr\tr1, [sp, #192]\t@ 0xc0\n+\tldrd\tr2, r3, [sp, #440]\t@ 0x1b8\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tldrd\tr2, r3, [sp, #320]\t@ 0x140\n+\tldr\tr1, [sp, #196]\t@ 0xc4\n+\tldrd\tr2, r3, [sp, #456]\t@ 0x1c8\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #108]\t@ 0x6c\n-\tldrd\tr2, r3, [sp, #272]\t@ 0x110\n+\tldr\tr1, [sp, #200]\t@ 0xc8\n+\tldrd\tr2, r3, [sp, #408]\t@ 0x198\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #152]\t@ 0x98\n-\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n+\tldr\tr1, [sp, #204]\t@ 0xcc\n+\tldrd\tr2, r3, [sp, #424]\t@ 0x1a8\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tldrd\tr2, r3, [sp, #440]\t@ 0x1b8\n+\tldr\tr1, [sp, #160]\t@ 0xa0\n+\tldrd\tr2, r3, [sp, #576]\t@ 0x240\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tldrd\tr2, r3, [sp, #448]\t@ 0x1c0\n+\tldr\tr1, [sp, #164]\t@ 0xa4\n+\tldrd\tr2, r3, [sp, #584]\t@ 0x248\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tldrd\tr2, r3, [sp, #408]\t@ 0x198\n+\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tldrd\tr2, r3, [sp, #544]\t@ 0x220\n \tstrd\tr2, r3, [r1]\n-\tldr\tr1, [sp, #80]\t@ 0x50\n-\tldrd\tr2, r3, [sp, #416]\t@ 0x1a0\n+\tldr\tr1, [sp, #172]\t@ 0xac\n+\tldrd\tr2, r3, [sp, #552]\t@ 0x228\n \tstrd\tr2, r3, [r1]\n-\tldr\tr2, [pc, #268]\t@ (12a8 <__gridxc_am05_MOD_am05_xscss+0x930>)\n-\tldr\tr3, [pc, #268]\t@ (12ac <__gridxc_am05_MOD_am05_xscss+0x934>)\n+\tldr\tr2, [pc, #280]\t@ (1418 <__gridxc_am05_MOD_am05_xscss+0xa88>)\n+\tldr\tr3, [pc, #280]\t@ (141c <__gridxc_am05_MOD_am05_xscss+0xa8c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #476]\t@ 0x1dc\n+\tldr\tr3, [sp, #612]\t@ 0x264\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t124e <__gridxc_am05_MOD_am05_xscss+0x8d6>\n-\tadd\tsp, #484\t@ 0x1e4\n+\tbne.n\t13c0 <__gridxc_am05_MOD_am05_xscss+0xa30>\n+\tadd.w\tsp, sp, #620\t@ 0x26c\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td16, [pc, #156]\t@ 1258 <__gridxc_am05_MOD_am05_xscss+0x8e0>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tvldr\td11, [pc, #160]\t@ 1260 <__gridxc_am05_MOD_am05_xscss+0x8e8>\n-\tvstr\td16, [sp, #112]\t@ 0x70\n-\tvldr\td16, [pc, #160]\t@ 1268 <__gridxc_am05_MOD_am05_xscss+0x8f0>\n-\tvldr\td9, [pc, #164]\t@ 1270 <__gridxc_am05_MOD_am05_xscss+0x8f8>\n-\tvldr\td14, [pc, #168]\t@ 1278 <__gridxc_am05_MOD_am05_xscss+0x900>\n-\tvldr\td8, [pc, #172]\t@ 1280 <__gridxc_am05_MOD_am05_xscss+0x908>\n-\tvldr\td10, [pc, #176]\t@ 1288 <__gridxc_am05_MOD_am05_xscss+0x910>\n-\tvstr\td16, [sp, #120]\t@ 0x78\n-\tvstr\td11, [r3, #-8]\n-\tb.n\tc42 <__gridxc_am05_MOD_am05_xscss+0x2ca>\n-\tvldr\td17, [pc, #168]\t@ 1290 <__gridxc_am05_MOD_am05_xscss+0x918>\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tb.n\tc9a <__gridxc_am05_MOD_am05_xscss+0x322>\n-\tvmul.f64\td20, d17, d17\n-\tvldr\td16, [pc, #164]\t@ 1298 <__gridxc_am05_MOD_am05_xscss+0x920>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvldr\td18, [pc, #164]\t@ 12a0 <__gridxc_am05_MOD_am05_xscss+0x928>\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td19, d20, d16\n-\tvdiv.f64\td16, d17, d19\n-\tvsub.f64\td17, d17, d16\n-\tvmov.f64\td19, d16\n-\tvfma.f64\td19, d17, d18\n-\tvstr\td19, [sp, #32]\n-\tb.n\tb24 <__gridxc_am05_MOD_am05_xscss+0x1ac>\n-\tvmul.f64\td20, d23, d23\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td18, [pc, #112]\t@ 1298 <__gridxc_am05_MOD_am05_xscss+0x920>\n-\tvmov.f64\td19, d16\n-\tvldr\td17, [pc, #112]\t@ 12a0 <__gridxc_am05_MOD_am05_xscss+0x928>\n-\tvfma.f64\td19, d20, d18\n-\tvdiv.f64\td18, d16, d19\n-\tvsub.f64\td16, d16, d18\n-\tvmov.f64\td19, d18\n-\tvfma.f64\td19, d16, d17\n-\tvmov.f64\td17, d19\n-\tvstr\td19, [sp, #24]\n-\tb.n\tabc <__gridxc_am05_MOD_am05_xscss+0x144>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvldr\td7, [pc, #164]\t@ 13c8 <__gridxc_am05_MOD_am05_xscss+0xa38>\n+\tvldr\td9, [pc, #168]\t@ 13d0 <__gridxc_am05_MOD_am05_xscss+0xa40>\n+\tvldr\td8, [pc, #172]\t@ 13d8 <__gridxc_am05_MOD_am05_xscss+0xa48>\n+\tvstr\td7, [r3, #-8]\n+\tvldr\td7, [pc, #172]\t@ 13e0 <__gridxc_am05_MOD_am05_xscss+0xa50>\n+\tvldr\td10, [pc, #176]\t@ 13e8 <__gridxc_am05_MOD_am05_xscss+0xa58>\n+\tvldr\td14, [pc, #140]\t@ 13c8 <__gridxc_am05_MOD_am05_xscss+0xa38>\n+\tvstr\td7, [sp, #32]\n+\tvldr\td7, [pc, #172]\t@ 13f0 <__gridxc_am05_MOD_am05_xscss+0xa60>\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n+\tvldr\td7, [pc, #172]\t@ 13f8 <__gridxc_am05_MOD_am05_xscss+0xa68>\n+\tvstr\td7, [sp, #224]\t@ 0xe0\n+\tb.n\tca6 <__gridxc_am05_MOD_am05_xscss+0x316>\n+\tvldr\td2, [pc, #172]\t@ 1400 <__gridxc_am05_MOD_am05_xscss+0xa70>\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n+\tb.n\tcfe <__gridxc_am05_MOD_am05_xscss+0x36e>\n+\tvmul.f64\td7, d5, d5\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td4, [pc, #160]\t@ 1408 <__gridxc_am05_MOD_am05_xscss+0xa78>\n+\tvmov.f64\td5, d6\n+\tvmla.f64\td5, d7, d4\n+\tvdiv.f64\td7, d6, d5\n+\tvldr\td5, [pc, #152]\t@ 1410 <__gridxc_am05_MOD_am05_xscss+0xa80>\n+\tvsub.f64\td6, d6, d7\n+\tvmov.f64\td4, d7\n+\tvmla.f64\td4, d6, d5\n+\tvstr\td4, [sp, #64]\t@ 0x40\n+\tb.w\tb7c <__gridxc_am05_MOD_am05_xscss+0x1ec>\n+\tvmul.f64\td7, d2, d2\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td3, [pc, #112]\t@ 1408 <__gridxc_am05_MOD_am05_xscss+0xa78>\n+\tvmov.f64\td4, d6\n+\tvldr\td5, [pc, #112]\t@ 1410 <__gridxc_am05_MOD_am05_xscss+0xa80>\n+\tvmla.f64\td4, d7, d3\n+\tvdiv.f64\td7, d6, d4\n+\tvsub.f64\td6, d6, d7\n+\tvmov.f64\td4, d7\n+\tvmla.f64\td4, d6, d5\n+\tvmov.f64\td5, d1\n+\tvstr\td4, [sp, #56]\t@ 0x38\n+\tb.w\tb08 <__gridxc_am05_MOD_am05_xscss+0x178>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \tnop.w\n-\t.word\t0x705ce006\n-\t.word\t0xbed8277d\n \t.word\t0x97d889bc\n \t.word\t0x3c9cd2b2\n-\t.word\t0x705ce006\n-\t.word\t0x3ed8277d\n \t.word\t0xc9d7a4b9\n \t.word\t0xbb805131\n-\t.word\t0x1445a804\n-\t.word\t0xbed21d9e\n \t.word\t0x6e7f7760\n \t.word\t0x3ef2f880\n+\t.word\t0x1445a804\n+\t.word\t0xbed21d9e\n \t.word\t0x97d889bc\n \t.word\t0x3cacd2b2\n+\t.word\t0x705ce006\n+\t.word\t0xbed8277d\n+\t.word\t0x705ce006\n+\t.word\t0x3ed8277d\n \t.word\t0xc2abc2d8\n \t.word\t0x3f7def83\n \t.word\t0x8d4fdf3b\n \t.word\t0x40066e97\n \t.word\t0xb089a027\n \t.word\t0x3fe9e9e1\n-\t.word\t0x00000106\n+\t.word\t0x00000112\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-000012b0 <__gridxc_am05_MOD_am05wbs>:\n+00001420 <__gridxc_am05_MOD_am05wbs>:\n __gridxc_am05_MOD_am05wbs():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3816]\t@ 0xee8\n \tsub\tsp, #212\t@ 0xd4\n \tmov\tr7, r2\n-\tldr\tr2, [pc, #412]\t@ (1468 <__gridxc_am05_MOD_am05wbs+0x1b8>)\n+\tldr\tr2, [pc, #420]\t@ (15e0 <__gridxc_am05_MOD_am05wbs+0x1c0>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #412]\t@ (146c <__gridxc_am05_MOD_am05wbs+0x1bc>)\n+\tldr\tr3, [pc, #420]\t@ (15e4 <__gridxc_am05_MOD_am05wbs+0x1c4>)\n \tmov\tr4, r0\n \tadd\tr2, pc\n \tldr\tr0, [sp, #280]\t@ 0x118\n \tstr\tr0, [sp, #100]\t@ 0x64\n \tmov\tr5, r1\n-\tvldr\td11, [pc, #364]\t@ 1448 <__gridxc_am05_MOD_am05wbs+0x198>\n+\tvldr\td11, [pc, #364]\t@ 15b8 <__gridxc_am05_MOD_am05wbs+0x198>\n \tldr\tr3, [r2, r3]\n \tvldr\td9, [r4]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #204]\t@ 0xcc\n \tmov.w\tr3, #0\n \tldr\tr3, [sp, #284]\t@ 0x11c\n \tstr\tr3, [sp, #80]\t@ 0x50\n@@ -1364,35 +1457,35 @@\n \tvmov.f64\td10, d0\n \tvldr\td8, [r5]\n \tldrd\tfp, r9, [sp, #292]\t@ 0x124\n \tvmul.f64\td0, d8, d11\n \tvmul.f64\td9, d9, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [pc, #300]\t@ 1450 <__gridxc_am05_MOD_am05wbs+0x1a0>\n+\tvldr\td6, [pc, #300]\t@ 15c0 <__gridxc_am05_MOD_am05wbs+0x1a0>\n \tldrd\tr1, r3, [sp, #88]\t@ 0x58\n-\tvcmpe.f64\td9, d17\n-\tvldr\td16, [r7]\n+\tvcmpe.f64\td9, d6\n+\tvldr\td7, [r7]\n \tldrd\tr2, r0, [sp, #96]\t@ 0x60\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t13fa <__gridxc_am05_MOD_am05wbs+0x14a>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d9\n-\tvstr\td17, [sp, #128]\t@ 0x80\n+\tblt.n\t156a <__gridxc_am05_MOD_am05wbs+0x14a>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td6, d7, d9\n+\tvstr\td6, [sp, #128]\t@ 0x80\n \tvmul.f64\td8, d8, d0\n-\tvldr\td17, [pc, #252]\t@ 1450 <__gridxc_am05_MOD_am05wbs+0x1a0>\n-\tvldr\td16, [r6]\n-\tvcmpe.f64\td8, d17\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t1412 <__gridxc_am05_MOD_am05wbs+0x162>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d8\n-\tvstr\td17, [sp, #112]\t@ 0x70\n+\tvldr\td6, [pc, #252]\t@ 15c0 <__gridxc_am05_MOD_am05wbs+0x1a0>\n+\tvldr\td7, [r6]\n+\tvcmpe.f64\td8, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tblt.n\t1582 <__gridxc_am05_MOD_am05wbs+0x162>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td6, d7, d8\n+\tvstr\td6, [sp, #112]\t@ 0x70\n \tstrd\tr2, r1, [sp, #68]\t@ 0x44\n \tmov\tr1, r5\n \tldr\tr2, [sp, #80]\t@ 0x50\n \tmovs\tr5, #0\n \tstr\tr2, [sp, #24]\n \tadd\tr2, sp, #168\t@ 0xa8\n \tstr\tr2, [sp, #40]\t@ 0x28\n@@ -1427,86 +1520,87 @@\n \tstrd\tr4, r5, [sp, #120]\t@ 0x78\n \tstrd\tr4, r5, [sp, #160]\t@ 0xa0\n \tstrd\tr4, r5, [sp, #152]\t@ 0x98\n \tstrd\tr4, r5, [sp, #144]\t@ 0x90\n \tstrd\tr4, r5, [sp, #136]\t@ 0x88\n \tadd\tr4, sp, #108\t@ 0x6c\n \tstr\tr4, [sp, #76]\t@ 0x4c\n-\tbl\t978 <__gridxc_am05_MOD_am05_xscss>\n-\tldr\tr2, [pc, #144]\t@ (1470 <__gridxc_am05_MOD_am05wbs+0x1c0>)\n-\tldr\tr3, [pc, #140]\t@ (146c <__gridxc_am05_MOD_am05wbs+0x1bc>)\n+\tbl\t990 <__gridxc_am05_MOD_am05_xscss>\n+\tldr\tr2, [pc, #152]\t@ (15e8 <__gridxc_am05_MOD_am05wbs+0x1c8>)\n+\tldr\tr3, [pc, #148]\t@ (15e4 <__gridxc_am05_MOD_am05wbs+0x1c4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #204]\t@ 0xcc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1440 <__gridxc_am05_MOD_am05wbs+0x190>\n+\tbne.n\t15b0 <__gridxc_am05_MOD_am05wbs+0x190>\n \tadd\tsp, #212\t@ 0xd4\n \tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td17, [pc, #92]\t@ 1458 <__gridxc_am05_MOD_am05wbs+0x1a8>\n-\tvcmpe.f64\td16, d17\n+\tvldr\td6, [pc, #92]\t@ 15c8 <__gridxc_am05_MOD_am05wbs+0x1a8>\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t1436 <__gridxc_am05_MOD_am05wbs+0x186>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvstr\td16, [sp, #128]\t@ 0x80\n-\tb.n\t134c <__gridxc_am05_MOD_am05wbs+0x9c>\n-\tvldr\td17, [pc, #68]\t@ 1458 <__gridxc_am05_MOD_am05wbs+0x1a8>\n-\tvcmpe.f64\td16, d17\n+\tbhi.n\t15a6 <__gridxc_am05_MOD_am05wbs+0x186>\n+\tvldr\td7, [pc, #84]\t@ 15d0 <__gridxc_am05_MOD_am05wbs+0x1b0>\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tb.n\t14bc <__gridxc_am05_MOD_am05wbs+0x9c>\n+\tvldr\td6, [pc, #68]\t@ 15c8 <__gridxc_am05_MOD_am05wbs+0x1a8>\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t142a <__gridxc_am05_MOD_am05wbs+0x17a>\n+\tbhi.n\t159a <__gridxc_am05_MOD_am05wbs+0x17a>\n \tmovs\tr6, #0\n \tmovs\tr7, #0\n \tstrd\tr6, r7, [sp, #112]\t@ 0x70\n-\tb.n\t1372 <__gridxc_am05_MOD_am05wbs+0xc2>\n-\tadd\tr7, pc, #52\t@ (adr r7, 1460 <__gridxc_am05_MOD_am05wbs+0x1b0>)\n+\tb.n\t14e2 <__gridxc_am05_MOD_am05wbs+0xc2>\n+\tadd\tr7, pc, #60\t@ (adr r7, 15d8 <__gridxc_am05_MOD_am05wbs+0x1b8>)\n \tldrd\tr6, r7, [r7]\n \tstrd\tr6, r7, [sp, #112]\t@ 0x70\n-\tb.n\t1372 <__gridxc_am05_MOD_am05wbs+0xc2>\n-\tvldr\td16, [pc, #40]\t@ 1460 <__gridxc_am05_MOD_am05wbs+0x1b0>\n-\tvstr\td16, [sp, #128]\t@ 0x80\n-\tb.n\t134c <__gridxc_am05_MOD_am05wbs+0x9c>\n+\tb.n\t14e2 <__gridxc_am05_MOD_am05wbs+0xc2>\n+\tvldr\td7, [pc, #48]\t@ 15d8 <__gridxc_am05_MOD_am05wbs+0x1b8>\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tb.n\t14bc <__gridxc_am05_MOD_am05wbs+0x9c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop.w\n \t.word\t0x2e9d68cd\n \t.word\t0x404d9bdb\n \t.word\t0x00000000\n \t.word\t0x39a4484c\n \t.word\t0x00000000\n \t.word\t0x39b4484c\n+\t...\n \t.word\t0x39a08cea\n \t.word\t0x46293e59\n-\t.word\t0x00000194\n+\t.word\t0x0000019c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000008c\n+\t.word\t0x00000094\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001474 <__gridxc_am05_MOD_saferecp>:\n+000015ec <__gridxc_am05_MOD_saferecp>:\n __gridxc_am05_MOD_saferecp():\n-\tvldr\td16, [pc, #64]\t@ 14b8 <__gridxc_am05_MOD_saferecp+0x44>\n-\tvldr\td17, [r2]\n-\tvldr\td18, [r1]\n-\tvcmpe.f64\td17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t1494 <__gridxc_am05_MOD_saferecp+0x20>\n-\tvdiv.f64\td16, d18, d17\n-\tvstr\td16, [r0]\n+\tvldr\td7, [pc, #64]\t@ 1630 <__gridxc_am05_MOD_saferecp+0x44>\n+\tvldr\td6, [r2]\n+\tvldr\td5, [r1]\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tblt.n\t160c <__gridxc_am05_MOD_saferecp+0x20>\n+\tvdiv.f64\td7, d5, d6\n+\tvstr\td7, [r0]\n \tbx\tlr\n-\tvcmpe.f64\td18, d16\n+\tvcmpe.f64\td5, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t14a8 <__gridxc_am05_MOD_saferecp+0x34>\n+\tbhi.n\t1620 <__gridxc_am05_MOD_saferecp+0x34>\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r0]\n \tbx\tlr\n-\tadd\tr3, pc, #20\t@ (adr r3, 14c0 <__gridxc_am05_MOD_saferecp+0x4c>)\n+\tadd\tr3, pc, #20\t@ (adr r3, 1638 <__gridxc_am05_MOD_saferecp+0x4c>)\n \tldrd\tr2, r3, [r3]\n \tstrd\tr2, r3, [r0]\n \tbx\tlr\n \tnop.w\n \t.word\t0x00000000\n \t.word\t0x39b4484c\n \t.word\t0x39a08cea\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "array.F90.o", "source2": "array.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 21856 (bytes into file)\n+ Start of section headers: 20680 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x5560:\n+There are 11 section headers, starting at offset 0x50c8:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000034 003a90 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 0050c8 000438 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 003ac4 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 003ac4 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 003ac4 0005f7 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 0040bb 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0040bb 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 0040f0 000a40 10 9 128 4\n- [ 9] .strtab STRTAB 00000000 004b30 000596 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 005500 00005f 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000034 003600 00 AX 0 0 4\n+ [ 2] .rel.text REL 00000000 004c30 000438 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 003634 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 003634 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 003634 0005f7 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 003c2b 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 003c2b 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 003c58 000a40 10 9 128 4\n+ [ 9] .strtab STRTAB 00000000 004698 000596 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 005068 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,167 +1,167 @@\n \n Symbol table '.symtab' contains 164 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 4: 0000024c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 4: 00000250 0 NOTYPE LOCAL DEFAULT 1 $d\n 5: 00000018 0 NOTYPE LOCAL DEFAULT 5 .LC1\n- 6: 00000258 0 NOTYPE LOCAL DEFAULT 1 $t\n- 7: 000005a4 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 6: 0000025c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 7: 000004ac 0 NOTYPE LOCAL DEFAULT 1 $d\n 8: 0000002c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n- 9: 000005b0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 000008f4 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 000004b8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 10: 00000710 0 NOTYPE LOCAL DEFAULT 1 $d\n 11: 00000044 0 NOTYPE LOCAL DEFAULT 5 .LC3\n- 12: 00000900 0 NOTYPE LOCAL DEFAULT 1 $t\n- 13: 00000ad8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 12: 0000071c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 13: 000008f8 0 NOTYPE LOCAL DEFAULT 1 $d\n 14: 0000005c 0 NOTYPE LOCAL DEFAULT 5 .LC4\n- 15: 00000ae4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 16: 00000d94 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 15: 00000904 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 16: 00000ae0 0 NOTYPE LOCAL DEFAULT 1 $d\n 17: 00000070 0 NOTYPE LOCAL DEFAULT 5 .LC5\n- 18: 00000da0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 19: 0000103c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 18: 00000aec 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 19: 00000cc0 0 NOTYPE LOCAL DEFAULT 1 $d\n 20: 00000088 0 NOTYPE LOCAL DEFAULT 5 .LC6\n- 21: 00001048 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 00001188 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 00000ccc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 22: 00000e0c 0 NOTYPE LOCAL DEFAULT 1 $d\n 23: 000000a0 0 NOTYPE LOCAL DEFAULT 5 .LC7\n- 24: 00001194 0 NOTYPE LOCAL DEFAULT 1 $t\n- 25: 00001370 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 24: 00000e18 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 25: 00000f58 0 NOTYPE LOCAL DEFAULT 1 $d\n 26: 000000b4 0 NOTYPE LOCAL DEFAULT 5 .LC8\n- 27: 0000137c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 28: 00001544 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 27: 00000f64 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 28: 000010a8 0 NOTYPE LOCAL DEFAULT 1 $d\n 29: 000000cc 0 NOTYPE LOCAL DEFAULT 5 .LC9\n 30: 000000e8 0 NOTYPE LOCAL DEFAULT 5 .LC10\n 31: 00000104 0 NOTYPE LOCAL DEFAULT 5 .LC11\n 32: 00000120 0 NOTYPE LOCAL DEFAULT 5 .LC12\n- 33: 00001550 0 NOTYPE LOCAL DEFAULT 1 $t\n- 34: 000016fc 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 33: 000010b4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 34: 00001264 0 NOTYPE LOCAL DEFAULT 1 $d\n 35: 0000013c 0 NOTYPE LOCAL DEFAULT 5 .LC13\n 36: 00000154 0 NOTYPE LOCAL DEFAULT 5 .LC14\n 37: 0000016c 0 NOTYPE LOCAL DEFAULT 5 .LC15\n 38: 00000184 0 NOTYPE LOCAL DEFAULT 5 .LC16\n- 39: 00001714 0 NOTYPE LOCAL DEFAULT 1 $t\n- 40: 000018c0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 39: 0000127c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 40: 0000142c 0 NOTYPE LOCAL DEFAULT 1 $d\n 41: 0000019c 0 NOTYPE LOCAL DEFAULT 5 .LC17\n 42: 000001b8 0 NOTYPE LOCAL DEFAULT 5 .LC18\n 43: 000001d4 0 NOTYPE LOCAL DEFAULT 5 .LC19\n 44: 000001f0 0 NOTYPE LOCAL DEFAULT 5 .LC20\n- 45: 000018d8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 46: 00001a90 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 45: 00001444 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 46: 000015fc 0 NOTYPE LOCAL DEFAULT 1 $d\n 47: 0000020c 0 NOTYPE LOCAL DEFAULT 5 .LC21\n 48: 00000228 0 NOTYPE LOCAL DEFAULT 5 .LC22\n 49: 00000244 0 NOTYPE LOCAL DEFAULT 5 .LC23\n- 50: 00001aa8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 51: 00001c0c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 50: 00001614 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 51: 0000177c 0 NOTYPE LOCAL DEFAULT 1 $d\n 52: 00000260 0 NOTYPE LOCAL DEFAULT 5 .LC24\n 53: 00000278 0 NOTYPE LOCAL DEFAULT 5 .LC25\n 54: 00000290 0 NOTYPE LOCAL DEFAULT 5 .LC26\n- 55: 00001c20 0 NOTYPE LOCAL DEFAULT 1 $t\n- 56: 00001d84 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 55: 00001790 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 56: 000018f8 0 NOTYPE LOCAL DEFAULT 1 $d\n 57: 000002a8 0 NOTYPE LOCAL DEFAULT 5 .LC27\n 58: 000002c4 0 NOTYPE LOCAL DEFAULT 5 .LC28\n 59: 000002e0 0 NOTYPE LOCAL DEFAULT 5 .LC29\n- 60: 00001d98 0 NOTYPE LOCAL DEFAULT 1 $t\n- 61: 00001f14 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 60: 0000190c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 61: 00001a8c 0 NOTYPE LOCAL DEFAULT 1 $d\n 62: 000002fc 0 NOTYPE LOCAL DEFAULT 5 .LC30\n 63: 00000318 0 NOTYPE LOCAL DEFAULT 5 .LC31\n- 64: 00001f28 0 NOTYPE LOCAL DEFAULT 1 $t\n- 65: 00002038 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 64: 00001aa0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 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$d\n+ 122: 000033d4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 123: 000034d8 0 NOTYPE LOCAL DEFAULT 1 $d\n 124: 000005c0 0 NOTYPE LOCAL DEFAULT 5 .LC58\n 125: 000005dc 0 NOTYPE LOCAL DEFAULT 5 .LC59\n- 126: 00003974 0 NOTYPE LOCAL DEFAULT 1 $t\n- 127: 00003a80 0 NOTYPE LOCAL DEFAULT 1 $d\n- 128: 00000001 600 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_dp\n+ 126: 000034e8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 127: 000035f0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 128: 00000001 604 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_dp\n 129: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 130: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 131: 00000259 856 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_sp\n- 132: 000005b1 848 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_ip\n- 133: 00000901 484 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_dp\n- 134: 00000ae5 700 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_sp\n- 135: 00000da1 680 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_ip\n- 136: 00001049 332 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_dp\n- 137: 00001195 488 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_sp\n- 138: 0000137d 468 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_ip\n- 139: 00001551 452 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_dp\n- 140: 00001715 452 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_sp\n- 141: 000018d9 464 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_ip\n- 142: 00001aa9 376 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_dp\n- 143: 00001c21 376 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_sp\n- 144: 00001d99 400 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_ip\n- 145: 00001f29 288 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_dp\n- 146: 00002049 288 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_sp\n- 147: 00002169 304 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_ip\n- 148: 00002299 600 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_dp\n+ 131: 0000025d 604 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_sp\n+ 132: 000004b9 612 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_4d_1d_ip\n+ 133: 0000071d 488 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_dp\n+ 134: 00000905 488 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_sp\n+ 135: 00000aed 480 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_3d_1d_ip\n+ 136: 00000ccd 332 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_dp\n+ 137: 00000e19 332 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_sp\n+ 138: 00000f65 336 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_2d_1d_ip\n+ 139: 000010b5 456 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_dp\n+ 140: 0000127d 456 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_sp\n+ 141: 00001445 464 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_4d_ip\n+ 142: 00001615 380 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_dp\n+ 143: 00001791 380 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_sp\n+ 144: 0000190d 404 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_3d_ip\n+ 145: 00001aa1 292 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_dp\n+ 146: 00001bc5 292 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_sp\n+ 147: 00001ce9 304 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_aa_1d_2d_ip\n+ 148: 00001e19 600 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_dp\n 149: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 150: 000024f1 600 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_sp\n- 151: 00002749 608 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_ip\n- 152: 000029a9 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_dp\n- 153: 00002b81 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_sp\n- 154: 00002d59 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_ip\n- 155: 00002f31 336 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_dp\n- 156: 00003081 336 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_sp\n- 157: 000031d1 336 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_ip\n- 158: 00003321 360 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_dp\n- 159: 00003489 364 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_sp\n- 160: 000035f5 348 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_ip\n- 161: 00003751 276 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_dp\n- 162: 00003865 272 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_sp\n- 163: 00003975 284 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_ip\n+ 150: 00002071 600 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_sp\n+ 151: 000022c9 608 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_4d_1d_ip\n+ 152: 00002529 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_dp\n+ 153: 00002701 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_sp\n+ 154: 000028d9 472 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_3d_1d_ip\n+ 155: 00002ab1 328 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_dp\n+ 156: 00002bf9 328 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_sp\n+ 157: 00002d41 328 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_2d_1d_ip\n+ 158: 00002e89 364 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_dp\n+ 159: 00002ff5 364 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_sp\n+ 160: 00003161 352 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_3d_ip\n+ 161: 000032c1 276 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_dp\n+ 162: 000033d5 276 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_sp\n+ 163: 000034e9 280 FUNC GLOBAL DEFAULT 1 __gridxc_array_MOD_ac_1d_2d_ip\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,138 +1,138 @@\n \n-Relocation section '.rel.text' at offset 0x50c8 contains 135 entries:\n+Relocation section '.rel.text' at offset 0x4c30 contains 135 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000024c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000250 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000254 00000203 R_ARM_REL32 00000000 .LC0\n-000005a4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000005a8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000005ac 00000503 R_ARM_REL32 00000018 .LC1\n-000008f4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000008f8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000008fc 00000803 R_ARM_REL32 0000002c .LC2\n-00000ad8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000adc 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000ae0 00000b03 R_ARM_REL32 00000044 .LC3\n-00000d94 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d98 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000d9c 00000e03 R_ARM_REL32 0000005c .LC4\n-0000103c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001040 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001044 00001103 R_ARM_REL32 00000070 .LC5\n-00001188 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000118c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001190 00001403 R_ARM_REL32 00000088 .LC6\n-00001370 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001374 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001378 00001703 R_ARM_REL32 000000a0 .LC7\n-00001544 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001548 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000154c 00001a03 R_ARM_REL32 000000b4 .LC8\n-000016fc 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001700 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001704 00001d03 R_ARM_REL32 000000cc .LC9\n-00001708 00001e03 R_ARM_REL32 000000e8 .LC10\n-0000170c 00001f03 R_ARM_REL32 00000104 .LC11\n-00001710 00002003 R_ARM_REL32 00000120 .LC12\n-000018c0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000018c4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000018c8 00002303 R_ARM_REL32 0000013c .LC13\n-000018cc 00002403 R_ARM_REL32 00000154 .LC14\n-000018d0 00002503 R_ARM_REL32 0000016c .LC15\n-000018d4 00002603 R_ARM_REL32 00000184 .LC16\n-00001a90 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001a94 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001a98 00002903 R_ARM_REL32 0000019c .LC17\n-00001a9c 00002a03 R_ARM_REL32 000001b8 .LC18\n-00001aa0 00002b03 R_ARM_REL32 000001d4 .LC19\n-00001aa4 00002c03 R_ARM_REL32 000001f0 .LC20\n-00001c0c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001c10 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001c14 00002f03 R_ARM_REL32 0000020c .LC21\n-00001c18 00003003 R_ARM_REL32 00000228 .LC22\n-00001c1c 00003103 R_ARM_REL32 00000244 .LC23\n-00001d84 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001d88 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001d8c 00003403 R_ARM_REL32 00000260 .LC24\n-00001d90 00003503 R_ARM_REL32 00000278 .LC25\n-00001d94 00003603 R_ARM_REL32 00000290 .LC26\n-00001f14 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001f18 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001f1c 00003903 R_ARM_REL32 000002a8 .LC27\n-00001f20 00003a03 R_ARM_REL32 000002c4 .LC28\n-00001f24 00003b03 R_ARM_REL32 000002e0 .LC29\n-00002038 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000203c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002040 00003e03 R_ARM_REL32 000002fc .LC30\n-00002044 00003f03 R_ARM_REL32 00000318 .LC31\n-00002158 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000215c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002160 00004203 R_ARM_REL32 00000334 .LC32\n-00002164 00004303 R_ARM_REL32 0000034c .LC33\n-00002288 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000228c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002290 00004603 R_ARM_REL32 00000364 .LC34\n-00002294 00004703 R_ARM_REL32 00000380 .LC35\n-000023a6 0000950a R_ARM_THM_CALL 00000000 memcpy\n-000024e4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000024e8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000024ec 00004a03 R_ARM_REL32 0000039c .LC36\n-000025fe 0000950a R_ARM_THM_CALL 00000000 memcpy\n-0000273c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002740 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002744 00004d03 R_ARM_REL32 000003b4 .LC37\n-0000285c 0000950a R_ARM_THM_CALL 00000000 memcpy\n-0000299c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000029a0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000029a4 00005003 R_ARM_REL32 000003c8 .LC38\n-00002a86 0000950a R_ARM_THM_CALL 00000000 memcpy\n-00002b74 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002b78 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002b7c 00005303 R_ARM_REL32 000003e0 .LC39\n-00002c5e 0000950a R_ARM_THM_CALL 00000000 memcpy\n-00002d4c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002d50 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002d54 00005603 R_ARM_REL32 000003f8 .LC40\n-00002e36 0000950a R_ARM_THM_CALL 00000000 memcpy\n-00002f24 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002f28 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002f2c 00005903 R_ARM_REL32 0000040c .LC41\n-00002fdc 0000950a R_ARM_THM_CALL 00000000 memcpy\n-00003074 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003078 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000307c 00005c03 R_ARM_REL32 00000424 .LC42\n-0000312c 0000950a R_ARM_THM_CALL 00000000 memcpy\n-000031c4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000031c8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000031cc 00005f03 R_ARM_REL32 0000043c .LC43\n-0000327c 0000950a R_ARM_THM_CALL 00000000 memcpy\n-00003314 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003318 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000331c 00006203 R_ARM_REL32 00000450 .LC44\n-00003474 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003478 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000347c 00006503 R_ARM_REL32 00000468 .LC45\n-00003480 00006603 R_ARM_REL32 00000484 .LC46\n-00003484 00006703 R_ARM_REL32 000004a0 .LC47\n-000035e0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000035e4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000035e8 00006a03 R_ARM_REL32 000004bc .LC48\n-000035ec 00006b03 R_ARM_REL32 000004d4 .LC49\n-000035f0 00006c03 R_ARM_REL32 000004ec .LC50\n-0000373c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003740 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003744 00006f03 R_ARM_REL32 00000504 .LC51\n-00003748 00007003 R_ARM_REL32 00000520 .LC52\n-0000374c 00007103 R_ARM_REL32 0000053c .LC53\n-00003854 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003858 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000385c 00007403 R_ARM_REL32 00000558 .LC54\n-00003860 00007503 R_ARM_REL32 00000574 .LC55\n-00003964 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003968 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000396c 00007803 R_ARM_REL32 00000590 .LC56\n-00003970 00007903 R_ARM_REL32 000005a8 .LC57\n-00003a80 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003a84 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003a88 00007c03 R_ARM_REL32 000005c0 .LC58\n-00003a8c 00007d03 R_ARM_REL32 000005dc .LC59\n+00000250 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000254 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000258 00000203 R_ARM_REL32 00000000 .LC0\n+000004ac 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004b0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000004b4 00000503 R_ARM_REL32 00000018 .LC1\n+00000710 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000714 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000718 00000803 R_ARM_REL32 0000002c .LC2\n+000008f8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000008fc 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000900 00000b03 R_ARM_REL32 00000044 .LC3\n+00000ae0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000ae4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000ae8 00000e03 R_ARM_REL32 0000005c .LC4\n+00000cc0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000cc4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000cc8 00001103 R_ARM_REL32 00000070 .LC5\n+00000e0c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000e10 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000e14 00001403 R_ARM_REL32 00000088 .LC6\n+00000f58 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000f5c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000f60 00001703 R_ARM_REL32 000000a0 .LC7\n+000010a8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000010ac 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000010b0 00001a03 R_ARM_REL32 000000b4 .LC8\n+00001264 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001268 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000126c 00001d03 R_ARM_REL32 000000cc .LC9\n+00001270 00001e03 R_ARM_REL32 000000e8 .LC10\n+00001274 00001f03 R_ARM_REL32 00000104 .LC11\n+00001278 00002003 R_ARM_REL32 00000120 .LC12\n+0000142c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001430 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001434 00002303 R_ARM_REL32 0000013c .LC13\n+00001438 00002403 R_ARM_REL32 00000154 .LC14\n+0000143c 00002503 R_ARM_REL32 0000016c .LC15\n+00001440 00002603 R_ARM_REL32 00000184 .LC16\n+000015fc 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001600 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001604 00002903 R_ARM_REL32 0000019c .LC17\n+00001608 00002a03 R_ARM_REL32 000001b8 .LC18\n+0000160c 00002b03 R_ARM_REL32 000001d4 .LC19\n+00001610 00002c03 R_ARM_REL32 000001f0 .LC20\n+0000177c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001780 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001784 00002f03 R_ARM_REL32 0000020c .LC21\n+00001788 00003003 R_ARM_REL32 00000228 .LC22\n+0000178c 00003103 R_ARM_REL32 00000244 .LC23\n+000018f8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000018fc 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001900 00003403 R_ARM_REL32 00000260 .LC24\n+00001904 00003503 R_ARM_REL32 00000278 .LC25\n+00001908 00003603 R_ARM_REL32 00000290 .LC26\n+00001a8c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001a90 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001a94 00003903 R_ARM_REL32 000002a8 .LC27\n+00001a98 00003a03 R_ARM_REL32 000002c4 .LC28\n+00001a9c 00003b03 R_ARM_REL32 000002e0 .LC29\n+00001bb4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001bb8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001bbc 00003e03 R_ARM_REL32 000002fc .LC30\n+00001bc0 00003f03 R_ARM_REL32 00000318 .LC31\n+00001cd8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001cdc 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001ce0 00004203 R_ARM_REL32 00000334 .LC32\n+00001ce4 00004303 R_ARM_REL32 0000034c .LC33\n+00001e08 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001e0c 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001e10 00004603 R_ARM_REL32 00000364 .LC34\n+00001e14 00004703 R_ARM_REL32 00000380 .LC35\n+00001f26 0000950a R_ARM_THM_CALL 00000000 memcpy\n+00002064 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002068 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000206c 00004a03 R_ARM_REL32 0000039c .LC36\n+0000217e 0000950a R_ARM_THM_CALL 00000000 memcpy\n+000022bc 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000022c0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000022c4 00004d03 R_ARM_REL32 000003b4 .LC37\n+000023dc 0000950a R_ARM_THM_CALL 00000000 memcpy\n+0000251c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002520 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002524 00005003 R_ARM_REL32 000003c8 .LC38\n+00002608 0000950a R_ARM_THM_CALL 00000000 memcpy\n+000026f4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000026f8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000026fc 00005303 R_ARM_REL32 000003e0 .LC39\n+000027e0 0000950a R_ARM_THM_CALL 00000000 memcpy\n+000028cc 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000028d0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000028d4 00005603 R_ARM_REL32 000003f8 .LC40\n+000029b8 0000950a R_ARM_THM_CALL 00000000 memcpy\n+00002aa4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002aa8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002aac 00005903 R_ARM_REL32 0000040c .LC41\n+00002b56 0000950a R_ARM_THM_CALL 00000000 memcpy\n+00002bec 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002bf0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002bf4 00005c03 R_ARM_REL32 00000424 .LC42\n+00002c9e 0000950a R_ARM_THM_CALL 00000000 memcpy\n+00002d34 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002d38 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002d3c 00005f03 R_ARM_REL32 0000043c .LC43\n+00002de6 0000950a R_ARM_THM_CALL 00000000 memcpy\n+00002e7c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e80 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002e84 00006203 R_ARM_REL32 00000450 .LC44\n+00002fe0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002fe4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002fe8 00006503 R_ARM_REL32 00000468 .LC45\n+00002fec 00006603 R_ARM_REL32 00000484 .LC46\n+00002ff0 00006703 R_ARM_REL32 000004a0 .LC47\n+0000314c 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003150 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003154 00006a03 R_ARM_REL32 000004bc .LC48\n+00003158 00006b03 R_ARM_REL32 000004d4 .LC49\n+0000315c 00006c03 R_ARM_REL32 000004ec .LC50\n+000032ac 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000032b0 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000032b4 00006f03 R_ARM_REL32 00000504 .LC51\n+000032b8 00007003 R_ARM_REL32 00000520 .LC52\n+000032bc 00007103 R_ARM_REL32 0000053c .LC53\n+000033c4 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000033c8 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000033cc 00007403 R_ARM_REL32 00000558 .LC54\n+000033d0 00007503 R_ARM_REL32 00000574 .LC55\n+000034d8 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000034dc 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000034e0 00007803 R_ARM_REL32 00000590 .LC56\n+000034e4 00007903 R_ARM_REL32 000005a8 .LC57\n+000035f0 00008119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000035f4 0000821a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000035f8 00007c03 R_ARM_REL32 000005c0 .LC58\n+000035fc 00007d03 R_ARM_REL32 000005dc .LC59\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -2,31 +2,30 @@\n \n \n Disassembly of section .text:\n \n 00000000 <__gridxc_array_MOD_aa_4d_1d_dp>:\n __gridxc_array_MOD_aa_4d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr\tr6, [pc, #580]\t@ (24c <__gridxc_array_MOD_aa_4d_1d_dp+0x24c>)\n+\tldr\tr6, [pc, #584]\t@ (250 <__gridxc_array_MOD_aa_4d_1d_dp+0x250>)\n \tsub\tsp, #92\t@ 0x5c\n \tadd\tr6, pc\n \tstrd\tr0, r1, [sp, #16]\n \tmov\tr1, r3\n \tldr\tr3, [sp, #132]\t@ 0x84\n \tldr\tr0, [r2, #24]\n \tldr\tr4, [sp, #128]\t@ 0x80\n \tldr.w\tr8, [r3, #24]\n \tldr.w\tr9, [r3]\n-\tmovs\tr3, #1\n+\tnegs\tr3, r0\n \tcmp.w\tr8, #0\n \tstr\tr4, [sp, #56]\t@ 0x38\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #1\n \tstr\tr0, [sp, #24]\n-\tnegs\tr3, r0\n \tcbnz\tr0, 38 <__gridxc_array_MOD_aa_4d_1d_dp+0x38>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr0, #1\n \tstr\tr0, [sp, #24]\n \tldr.w\tsl, [r1]\n \tldr\tr1, [r2, #36]\t@ 0x24\n \tstr\tr1, [sp, #0]\n@@ -39,23 +38,22 @@\n \tstr\tr3, [sp, #28]\n \tldr\tr3, [sp, #16]\n \tldr\tr4, [r2, #60]\t@ 0x3c\n \tldr\tr7, [r1, #12]\n \tldr\tr2, [r3, #12]\n \tsub.w\tip, ip, r4\n \tcmp\tr2, r7\n-\tbgt.n\t13c <__gridxc_array_MOD_aa_4d_1d_dp+0x13c>\n-\tldr\tr5, [r1, #8]\n-\tldr\tr1, [sp, #24]\n+\tbgt.n\t13e <__gridxc_array_MOD_aa_4d_1d_dp+0x13e>\n \tldr\tr0, [r3, #8]\n-\tmov\tr3, r8\n-\tcmp\tr1, #1\n+\tldr\tr3, [sp, #24]\n+\tldr\tr5, [r1, #8]\n+\tcmp.w\tr8, #1\n \tit\teq\n \tcmpeq\tr3, #1\n-\tbne.n\t15e <__gridxc_array_MOD_aa_4d_1d_dp+0x15e>\n+\tbne.n\t160 <__gridxc_array_MOD_aa_4d_1d_dp+0x160>\n \tldr\tr3, [sp, #28]\n \tmla\tr1, r4, r2, ip\n \tstr\tr6, [sp, #40]\t@ 0x28\n \tmov\tr6, r4\n \tadds\tr3, #8\n \tstr\tr3, [sp, #28]\n \tldr\tr3, [sp, #12]\n@@ -64,15 +62,15 @@\n \tmul.w\tr3, r3, r0\n \tstr\tr3, [sp, #32]\n \tldr\tr3, [sp, #0]\n \tmov.w\tfp, r3, lsl #3\n \tadds\tr3, r5, #1\n \tstr\tr3, [sp, #24]\n \tcmp\tr0, r5\n-\tbgt.n\t130 <__gridxc_array_MOD_aa_4d_1d_dp+0x130>\n+\tbgt.n\t132 <__gridxc_array_MOD_aa_4d_1d_dp+0x132>\n \tldr\tr7, [sp, #20]\n \tmov\tr8, r0\n \tldr\tr3, [sp, #16]\n \tldr\tr4, [sp, #0]\n \tldr\tr7, [r7, #4]\n \tldr\tr3, [r3, #4]\n \tadd.w\tip, r7, #1\n@@ -81,40 +79,41 @@\n \tstrd\tr6, r0, [sp, #44]\t@ 0x2c\n \tstr\tr5, [sp, #52]\t@ 0x34\n \tstrd\tr2, r1, [sp, #60]\t@ 0x3c\n \tmla\tlr, r4, r3, r7\n \tadd\tlr, r1\n \tldr\tr2, [sp, #8]\n \tcmp\tr2, r3\n-\tblt.n\t118 <__gridxc_array_MOD_aa_4d_1d_dp+0x118>\n+\tblt.n\t11a <__gridxc_array_MOD_aa_4d_1d_dp+0x11a>\n \tldr\tr2, [sp, #20]\n \tmov\tr0, r3\n \tstr.w\tr8, [sp, #4]\n \tldr\tr4, [r2, #0]\n \tldr\tr2, [sp, #16]\n \tadd.w\tr1, r4, lr\n \tadds\tr7, r4, #1\n \tldr\tr6, [r2, #0]\n \tldr\tr2, [sp, #28]\n \tsubs\tr5, r6, r4\n \tsubs\tr7, r7, r6\n \tlsls\tr5, r5, #3\n \tadd.w\tr1, r2, r1, lsl #3\n \tsubs\tr5, #8\n-\tadd.w\tr2, sl, #4294967295\t@ 0xffffffff\n-\tadd.w\tr8, r5, r1\n \tcmp\tr4, r6\n-\tadd.w\tr2, r9, r2, lsl #3\n-\tblt.n\t10c <__gridxc_array_MOD_aa_4d_1d_dp+0x10c>\n-\tvldr\td17, [r2]\n-\tvldmia\tr8!, {d16}\n-\tvadd.f64\td16, d16, d17\n+\tittt\tge\n+\taddge.w\tr2, sl, #4294967295\t@ 0xffffffff\n+\taddge.w\tr8, r5, r1\n+\taddge.w\tr2, r9, r2, lsl #3\n+\tblt.n\t10e <__gridxc_array_MOD_aa_4d_1d_dp+0x10e>\n+\tvldr\td6, [r2]\n+\tvldmia\tr8!, {d7}\n+\tvadd.f64\td7, d7, d6\n \tcmp\tr8, r1\n-\tvstmia\tr2!, {d16}\n-\tbne.n\tf6 <__gridxc_array_MOD_aa_4d_1d_dp+0xf6>\n+\tvstmia\tr2!, {d7}\n+\tbne.n\tf8 <__gridxc_array_MOD_aa_4d_1d_dp+0xf8>\n \tadd\tsl, r7\n \tadds\tr0, #1\n \tadd\tr1, fp\n \tcmp\tr0, ip\n \tbne.n\te6 <__gridxc_array_MOD_aa_4d_1d_dp+0xe6>\n \tldr.w\tr8, [sp, #4]\n \tldr\tr2, [sp, #12]\n@@ -131,42 +130,43 @@\n \tadd\tr1, r6\n \tcmp\tr2, r3\n \tbne.n\t96 <__gridxc_array_MOD_aa_4d_1d_dp+0x96>\n \tldr\tr6, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, sl\n-\tblt.n\t158 <__gridxc_array_MOD_aa_4d_1d_dp+0x158>\n-\tldr\tr3, [pc, #264]\t@ (250 <__gridxc_array_MOD_aa_4d_1d_dp+0x250>)\n+\tblt.n\t15a <__gridxc_array_MOD_aa_4d_1d_dp+0x15a>\n+\tldr\tr3, [pc, #268]\t@ (254 <__gridxc_array_MOD_aa_4d_1d_dp+0x254>)\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #264]\t@ (254 <__gridxc_array_MOD_aa_4d_1d_dp+0x254>)\n+\tldr\tr0, [pc, #268]\t@ (258 <__gridxc_array_MOD_aa_4d_1d_dp+0x258>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr3, [sp, #12]\n \tadd.w\tlr, r7, #1\n-\tlsls\tr7, r1, #3\n \tmla\tip, r4, r2, ip\n \tstrd\tr8, r9, [sp, #4]\n-\tmov.w\tfp, r8, lsl #3\n \tstr\tr6, [sp, #60]\t@ 0x3c\n-\tmov\tr9, r7\n-\tmul.w\tr3, r3, r0\n+\tmov.w\tfp, r8, lsl #3\n \tmov\tr6, r4\n \tmov\tr4, lr\n+\tmul.w\tr3, r3, r0\n \tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #24]\n+\tlsls\tr7, r3, #3\n \tadds\tr3, r5, #1\n+\tmov\tr9, r7\n \tstr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr0, r5\n-\tbgt.n\t23e <__gridxc_array_MOD_aa_4d_1d_dp+0x23e>\n+\tbgt.n\t242 <__gridxc_array_MOD_aa_4d_1d_dp+0x242>\n \tldr\tr3, [sp, #16]\n \tmov\tlr, r0\n \tldr\tr7, [sp, #0]\n \tstrd\tr6, r0, [sp, #64]\t@ 0x40\n \tldr\tr1, [r3, #4]\n \tldr\tr3, [sp, #20]\n \tstr\tr1, [sp, #40]\t@ 0x28\n@@ -179,773 +179,589 @@\n \tstrd\tip, r4, [sp, #80]\t@ 0x50\n \tmla\tr1, r7, r1, r3\n \tmov\tr3, r0\n \tmov\tr7, r9\n \tadd\tr1, ip\n \tldrd\tr4, r2, [sp, #40]\t@ 0x28\n \tcmp\tr4, r2\n-\tbgt.n\t224 <__gridxc_array_MOD_aa_4d_1d_dp+0x224>\n+\tbgt.n\t228 <__gridxc_array_MOD_aa_4d_1d_dp+0x228>\n \tldr\tr2, [sp, #16]\n \tmov\tr5, r1\n \tstrd\tr3, r1, [sp, #32]\n \tldr\tr6, [r2, #0]\n \tldr\tr2, [sp, #20]\n \tldr.w\tip, [r2]\n \tldr\tr2, [sp, #24]\n \tadd.w\tr0, ip, #1\n \tsub.w\tr9, r0, r6\n \tmul.w\tlr, r6, r2\n \tldr\tr2, [sp, #28]\n \tadd.w\tlr, r2, lr, lsl #3\n \tcmp\tr6, ip\n-\tbgt.n\t216 <__gridxc_array_MOD_aa_4d_1d_dp+0x216>\n+\tbgt.n\t21a <__gridxc_array_MOD_aa_4d_1d_dp+0x21a>\n \tldr\tr2, [sp, #4]\n \tadd.w\tr3, sl, #4294967295\t@ 0xffffffff\n \tadd.w\tr1, lr, r5, lsl #3\n \tmul.w\tr3, r2, r3\n \tldr\tr2, [sp, #8]\n \tadd.w\tr3, r2, r3, lsl #3\n \tmov\tr2, r6\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tvldr\td17, [r1]\n+\tvldr\td6, [r1]\n \tcmp\tr2, r0\n \tadd\tr1, r7\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, fp\n-\tbne.n\t1fa <__gridxc_array_MOD_aa_4d_1d_dp+0x1fa>\n+\tbne.n\t1fe <__gridxc_array_MOD_aa_4d_1d_dp+0x1fe>\n \tadd\tsl, r9\n \tldr\tr3, [sp, #0]\n \tadds\tr4, #1\n \tcmp\tr4, r8\n \tadd\tr5, r3\n-\tbne.n\t1e0 <__gridxc_array_MOD_aa_4d_1d_dp+0x1e0>\n+\tbne.n\t1e4 <__gridxc_array_MOD_aa_4d_1d_dp+0x1e4>\n \tldrd\tr3, r1, [sp, #32]\n \tadds\tr3, #1\n \tldr\tr2, [sp, #12]\n \tadd\tr1, r2\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr3, r2\n-\tbne.n\t1b4 <__gridxc_array_MOD_aa_4d_1d_dp+0x1b4>\n+\tbne.n\t1b8 <__gridxc_array_MOD_aa_4d_1d_dp+0x1b8>\n \tldrd\tr6, r0, [sp, #64]\t@ 0x40\n \tmov\tr9, r7\n \tldrd\tr5, r2, [sp, #72]\t@ 0x48\n \tldrd\tip, r4, [sp, #80]\t@ 0x50\n \tadds\tr2, #1\n \tadd\tip, r6\n \tcmp\tr2, r4\n-\tbne.n\t184 <__gridxc_array_MOD_aa_4d_1d_dp+0x184>\n+\tbne.n\t188 <__gridxc_array_MOD_aa_4d_1d_dp+0x188>\n \tldr\tr6, [sp, #60]\t@ 0x3c\n-\tb.n\t13c <__gridxc_array_MOD_aa_4d_1d_dp+0x13c>\n+\tb.n\t13e <__gridxc_array_MOD_aa_4d_1d_dp+0x13e>\n \tnop\n-\t.word\t0x00000240\n+\t.word\t0x00000244\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000106\n+\t.word\t0x00000108\n R_ARM_REL32\t.LC0\n \n-00000258 <__gridxc_array_MOD_aa_4d_1d_sp>:\n+0000025c <__gridxc_array_MOD_aa_4d_1d_sp>:\n __gridxc_array_MOD_aa_4d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr.w\tlr, [pc, #836]\t@ 5a4 <__gridxc_array_MOD_aa_4d_1d_sp+0x34c>\n-\tsub\tsp, #132\t@ 0x84\n-\tadd\tlr, pc\n-\tstrd\tr0, r1, [sp, #52]\t@ 0x34\n-\tmov\tr0, r3\n-\tldr\tr1, [sp, #172]\t@ 0xac\n-\tldr\tr3, [r2, #24]\n-\tldr\tr4, [sp, #168]\t@ 0xa8\n-\tldr\tr5, [r1, #24]\n-\tldr.w\tr8, [r1]\n-\tnegs\tr1, r3\n-\tcmp\tr5, #0\n+\tldr\tr6, [pc, #584]\t@ (4ac <__gridxc_array_MOD_aa_4d_1d_sp+0x250>)\n+\tsub\tsp, #92\t@ 0x5c\n+\tadd\tr6, pc\n+\tstrd\tr0, r1, [sp, #16]\n+\tmov\tr1, r3\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr0, [r2, #24]\n+\tldr\tr4, [sp, #128]\t@ 0x80\n+\tldr.w\tr8, [r3, #24]\n+\tldr.w\tr9, [r3]\n+\tnegs\tr3, r0\n+\tcmp.w\tr8, #0\n+\tstr\tr4, [sp, #56]\t@ 0x38\n \tit\teq\n-\tmoveq\tr5, #1\n-\tstr\tr5, [sp, #4]\n-\tcbnz\tr3, 288 <__gridxc_array_MOD_aa_4d_1d_sp+0x30>\n-\tmov.w\tr1, #4294967295\t@ 0xffffffff\n-\tmovs\tr3, #1\n-\tldr.w\tsl, [r0]\n-\tldr\tr0, [r2, #36]\t@ 0x24\n-\tldr\tr5, [r2, #48]\t@ 0x30\n-\tldr\tr6, [r2, #60]\t@ 0x3c\n-\tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #12]\n-\tsubs\tr2, r1, r0\n-\tsubs\tr2, r2, r5\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tsub.w\tip, r2, r6\n-\tldr\tr5, [sp, #52]\t@ 0x34\n-\tstr\tr6, [sp, #76]\t@ 0x4c\n-\tldr\tr6, [sp, #56]\t@ 0x38\n-\tstr\tr0, [sp, #32]\n-\tldr\tr0, [r5, #12]\n-\tldr\tr2, [r6, #12]\n-\tcmp\tr0, r2\n-\tbgt.w\t48c <__gridxc_array_MOD_aa_4d_1d_sp+0x234>\n-\tldr\tr7, [r6, #8]\n-\tldr\tr6, [sp, #4]\n-\tldr\tr5, [r5, #8]\n-\tcmp\tr3, #1\n+\tmoveq.w\tr8, #1\n+\tstr\tr0, [sp, #24]\n+\tcbnz\tr0, 294 <__gridxc_array_MOD_aa_4d_1d_sp+0x38>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tmovs\tr0, #1\n+\tstr\tr0, [sp, #24]\n+\tldr.w\tsl, [r1]\n+\tldr\tr1, [r2, #36]\t@ 0x24\n+\tstr\tr1, [sp, #0]\n+\tsub.w\tip, r3, r1\n+\tldr\tr3, [r2, #48]\t@ 0x30\n+\tstr\tr3, [sp, #12]\n+\tsub.w\tip, ip, r3\n+\tldr\tr3, [r2, #0]\n+\tldr\tr1, [sp, #20]\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #16]\n+\tldr\tr4, [r2, #60]\t@ 0x3c\n+\tldr\tr7, [r1, #12]\n+\tldr\tr2, [r3, #12]\n+\tsub.w\tip, ip, r4\n+\tcmp\tr2, r7\n+\tbgt.n\t39a <__gridxc_array_MOD_aa_4d_1d_sp+0x13e>\n+\tldr\tr0, [r3, #8]\n+\tldr\tr3, [sp, #24]\n+\tldr\tr5, [r1, #8]\n+\tcmp.w\tr8, #1\n \tit\teq\n-\tcmpeq\tr6, #1\n-\tbne.w\t4b4 <__gridxc_array_MOD_aa_4d_1d_sp+0x25c>\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tadds\tr3, r2, #1\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #32]\n-\tstr\tr4, [sp, #96]\t@ 0x60\n-\tmov\tr4, r1\n-\tmul.w\tr2, r6, r5\n-\tadds\tr3, r6, r3\n-\tldr\tr6, [sp, #76]\t@ 0x4c\n-\tadd.w\tr9, r3, r6\n-\tsubs\tr3, r2, r6\n-\tldr\tr6, [sp, #32]\n-\tadd\tr2, ip\n-\tstr\tr2, [sp, #92]\t@ 0x5c\n-\tsubs\tr3, r3, r6\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr6, [sp, #76]\t@ 0x4c\n-\tsubs\tr3, r3, r2\n-\tadd\tr3, r1\n-\tmov\tr1, r9\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\trsb\tr3, r2, r2, lsl #30\n-\tldr.w\tr9, [sp, #12]\n-\tmul.w\tr6, r6, r0\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tadds\tr3, r7, #1\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tmov\tr3, sl\n-\tmov\tsl, r8\n-\tmov\tr8, r3\n-\tstr\tr6, [sp, #80]\t@ 0x50\n-\tcmp\tr5, r7\n-\tbgt.w\t476 <__gridxc_array_MOD_aa_4d_1d_sp+0x21e>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstr.w\tlr, [sp, #120]\t@ 0x78\n-\tldr.w\tlr, [sp, #32]\n-\tldr\tr2, [r3, #4]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tstrd\tip, r5, [sp, #100]\t@ 0x64\n-\tldr\tr6, [r3, #4]\n-\tstr\tr6, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tstrd\tr7, r0, [sp, #108]\t@ 0x6c\n-\tadd\tr3, r6\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tstr\tr4, [sp, #116]\t@ 0x74\n-\trsb\tfp, r3, r3, lsl #30\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tstr.w\tfp, [sp, #28]\n-\tmov\tfp, r5\n-\tadd\tr3, r6\n-\tldr\tr6, [sp, #32]\n-\tstr\tr1, [sp, #124]\t@ 0x7c\n-\tmla\tr2, r6, r2, r1\n-\tldr\tr6, [sp, #60]\t@ 0x3c\n-\tsubs\tr2, r2, r4\n-\tadds\tr6, #1\n-\tadd\tr2, ip\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tmov\tr2, r3\n-\tstr\tr6, [sp, #8]\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tcmp\tr3, r1\n-\tblt.n\t450 <__gridxc_array_MOD_aa_4d_1d_sp+0x1f8>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tmov\tr0, r1\n-\tstrd\tfp, r2, [sp, #40]\t@ 0x28\n-\tldr\tr5, [r3, #0]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr4, [r3, #0]\n+\tcmpeq\tr3, #1\n+\tbne.n\t3bc <__gridxc_array_MOD_aa_4d_1d_sp+0x160>\n \tldr\tr3, [sp, #28]\n-\tsubs\tr7, r4, r5\n-\tadds\tr3, r2, r3\n-\tadds\tr6, r7, #1\n-\tadd\tr3, r5\n-\tbic.w\tip, r6, #3\n-\tadd.w\tr3, r9, r3, lsl #2\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tadds\tr1, r3, r2\n-\tlsrs\tr3, r6, #2\n-\tlsls\tr3, r3, #4\n-\tstr\tr3, [sp, #12]\n-\tadd.w\tr3, ip, r5\n+\tmla\tr1, r4, r2, ip\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tmov\tr6, r4\n+\tadds\tr3, #4\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #12]\n+\tadds\tr7, #1\n+\tstr\tr7, [sp, #36]\t@ 0x24\n+\tmul.w\tr3, r3, r0\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #0]\n+\tmov.w\tfp, r3, lsl #2\n+\tadds\tr3, r5, #1\n \tstr\tr3, [sp, #24]\n-\tand.w\tr3, r6, #3\n-\tstr\tr3, [sp, #20]\n-\tcmp\tr4, r5\n-\tblt.n\t442 <__gridxc_array_MOD_aa_4d_1d_sp+0x1ea>\n-\tcmp\tr7, #2\n-\tbls.w\t4a8 <__gridxc_array_MOD_aa_4d_1d_sp+0x250>\n-\tldr\tr2, [sp, #16]\n-\tadd.w\tr3, r8, #1073741824\t@ 0x40000000\n-\tsubs\tr3, #1\n-\tadd.w\tr2, r2, r1, lsl #2\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #12]\n-\tadd.w\tr3, sl, r3, lsl #2\n-\tadd.w\tfp, r2, r3\n-\tldr\tr2, [sp, #4]\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvadd.f32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tfp, r3\n-\tbne.n\t3be <__gridxc_array_MOD_aa_4d_1d_sp+0x166>\n+\tcmp\tr0, r5\n+\tbgt.n\t38e <__gridxc_array_MOD_aa_4d_1d_sp+0x132>\n+\tldr\tr7, [sp, #20]\n+\tmov\tr8, r0\n+\tldr\tr3, [sp, #16]\n+\tldr\tr4, [sp, #0]\n+\tldr\tr7, [r7, #4]\n+\tldr\tr3, [r3, #4]\n+\tadd.w\tip, r7, #1\n+\tstr\tr7, [sp, #8]\n+\tldr\tr7, [sp, #32]\n+\tstrd\tr6, r0, [sp, #44]\t@ 0x2c\n+\tstr\tr5, [sp, #52]\t@ 0x34\n+\tstrd\tr2, r1, [sp, #60]\t@ 0x3c\n+\tmla\tlr, r4, r3, r7\n+\tadd\tlr, r1\n+\tldr\tr2, [sp, #8]\n+\tcmp\tr2, r3\n+\tblt.n\t376 <__gridxc_array_MOD_aa_4d_1d_sp+0x11a>\n \tldr\tr2, [sp, #20]\n-\tadd.w\tr3, r8, ip\n-\tcbz\tr2, 440 <__gridxc_array_MOD_aa_4d_1d_sp+0x1e8>\n-\tldr\tr2, [sp, #24]\n-\tadd.w\tfp, r1, r2\n-\tsubs\tr3, #1\n-\tadd.w\tfp, r9, fp, lsl #2\n-\tlsls\tr3, r3, #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, sl, r3\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tadd.w\tfp, r2, #1\n-\tcmp\tr4, fp\n-\tblt.n\t440 <__gridxc_array_MOD_aa_4d_1d_sp+0x1e8>\n-\tadd\tfp, r1\n-\tadds\tr2, #2\n-\tcmp\tr4, r2\n-\tadd.w\tfp, r9, fp, lsl #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, r3, #4\n-\tadd\tfp, sl\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tblt.n\t440 <__gridxc_array_MOD_aa_4d_1d_sp+0x1e8>\n-\tadd\tr2, r1\n-\tadds\tr3, #8\n-\tadd\tr3, sl\n-\tadd.w\tr2, r9, r2, lsl #2\n-\tvldr\ts15, [r3]\n+\tmov\tr0, r3\n+\tstr.w\tr8, [sp, #4]\n+\tldr\tr4, [r2, #0]\n+\tldr\tr2, [sp, #16]\n+\tadd.w\tr1, r4, lr\n+\tadds\tr7, r4, #1\n+\tldr\tr6, [r2, #0]\n+\tldr\tr2, [sp, #28]\n+\tsubs\tr5, r6, r4\n+\tsubs\tr7, r7, r6\n+\tlsls\tr5, r5, #2\n+\tadd.w\tr1, r2, r1, lsl #2\n+\tsubs\tr5, #4\n+\tcmp\tr4, r6\n+\tittt\tge\n+\taddge.w\tr2, sl, #4294967295\t@ 0xffffffff\n+\taddge.w\tr8, r5, r1\n+\taddge.w\tr2, r9, r2, lsl #2\n+\tblt.n\t36a <__gridxc_array_MOD_aa_4d_1d_sp+0x10e>\n \tvldr\ts14, [r2]\n+\tvldmia\tr8!, {s15}\n \tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [r3]\n-\tadd\tr8, r6\n-\tldr\tr3, [sp, #8]\n-\tadds\tr0, #1\n-\tadd\tr1, lr\n-\tcmp\tr0, r3\n-\tbne.n\t39a <__gridxc_array_MOD_aa_4d_1d_sp+0x142>\n-\tldrd\tfp, r2, [sp, #40]\t@ 0x28\n-\tadd.w\tfp, fp, #1\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #28]\n-\tadd\tr3, r1\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tcmp\tfp, r3\n-\tbne.w\t35a <__gridxc_array_MOD_aa_4d_1d_sp+0x102>\n-\tldrd\tip, r5, [sp, #100]\t@ 0x64\n-\tldrd\tr7, r0, [sp, #108]\t@ 0x6c\n-\tldrd\tr4, lr, [sp, #116]\t@ 0x74\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tldrd\tr2, r3, [sp, #76]\t@ 0x4c\n+\tcmp\tr8, r1\n+\tvstmia\tr2!, {s15}\n+\tbne.n\t354 <__gridxc_array_MOD_aa_4d_1d_sp+0xf8>\n+\tadd\tsl, r7\n \tadds\tr0, #1\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tcmp\tr0, r3\n-\tbne.w\t30a <__gridxc_array_MOD_aa_4d_1d_sp+0xb2>\n-\tldr\tr4, [sp, #96]\t@ 0x60\n-\tmov\tsl, r8\n-\tldr\tr3, [r4, #0]\n+\tadd\tr1, fp\n+\tcmp\tr0, ip\n+\tbne.n\t342 <__gridxc_array_MOD_aa_4d_1d_sp+0xe6>\n+\tldr.w\tr8, [sp, #4]\n+\tldr\tr2, [sp, #12]\n+\tadd.w\tr8, r8, #1\n+\tadd\tlr, r2\n+\tldr\tr2, [sp, #24]\n+\tcmp\tr8, r2\n+\tbne.n\t31a <__gridxc_array_MOD_aa_4d_1d_sp+0xbe>\n+\tldrd\tr6, r0, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\tldrd\tr2, r1, [sp, #60]\t@ 0x3c\n+\tadds\tr2, #1\n+\tldr\tr3, [sp, #36]\t@ 0x24\n+\tadd\tr1, r6\n+\tcmp\tr2, r3\n+\tbne.n\t2f2 <__gridxc_array_MOD_aa_4d_1d_sp+0x96>\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [r3, #0]\n \tcmp\tr3, sl\n-\tblt.n\t4ae <__gridxc_array_MOD_aa_4d_1d_sp+0x256>\n-\tldr\tr3, [pc, #276]\t@ (5a8 <__gridxc_array_MOD_aa_4d_1d_sp+0x350>)\n+\tblt.n\t3b6 <__gridxc_array_MOD_aa_4d_1d_sp+0x15a>\n+\tldr\tr3, [pc, #268]\t@ (4b0 <__gridxc_array_MOD_aa_4d_1d_sp+0x254>)\n \tmovs\tr1, #19\n-\tldr\tr0, [pc, #276]\t@ (5ac <__gridxc_array_MOD_aa_4d_1d_sp+0x354>)\n+\tldr\tr0, [pc, #268]\t@ (4b4 <__gridxc_array_MOD_aa_4d_1d_sp+0x258>)\n \tadd\tr0, pc\n-\tldr.w\tr3, [lr, r3]\n+\tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #132\t@ 0x84\n+\tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr2, r5\n-\tmov\tr3, r8\n-\tb.n\t3dc <__gridxc_array_MOD_aa_4d_1d_sp+0x184>\n-\tadd\tsp, #132\t@ 0x84\n+\tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tadds\tr2, #1\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tmov.w\tfp, r3, lsl #2\n-\tmov\tr4, r2\n-\tstr.w\tr8, [sp, #8]\n-\tmla\tr6, r1, r0, ip\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tmul.w\tr9, r1, r5\n-\tldr\tr1, [sp, #4]\n-\tmov.w\tip, r1, lsl #2\n-\tadds\tr1, r7, #1\n-\tstrd\tr1, r3, [sp, #36]\t@ 0x24\n-\tcmp\tr5, r7\n-\tbgt.n\t594 <__gridxc_array_MOD_aa_4d_1d_sp+0x33c>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstrd\tr5, r7, [sp, #60]\t@ 0x3c\n-\tstrd\tr0, r9, [sp, #68]\t@ 0x44\n-\tldr\tr2, [r3, #4]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstrd\tr6, r4, [sp, #80]\t@ 0x50\n-\tstr.w\tlr, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #12]\n+\tadd.w\tlr, r7, #1\n+\tmla\tip, r4, r2, ip\n+\tstrd\tr8, r9, [sp, #4]\n+\tstr\tr6, [sp, #60]\t@ 0x3c\n+\tmov.w\tfp, r8, lsl #2\n+\tmov\tr6, r4\n+\tmov\tr4, lr\n+\tmul.w\tr3, r3, r0\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #24]\n+\tlsls\tr7, r3, #2\n+\tadds\tr3, r5, #1\n+\tmov\tr9, r7\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tcmp\tr0, r5\n+\tbgt.n\t49e <__gridxc_array_MOD_aa_4d_1d_sp+0x242>\n+\tldr\tr3, [sp, #16]\n+\tmov\tlr, r0\n+\tldr\tr7, [sp, #0]\n+\tstrd\tr6, r0, [sp, #64]\t@ 0x40\n+\tldr\tr1, [r3, #4]\n+\tldr\tr3, [sp, #20]\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tstr\tr5, [sp, #72]\t@ 0x48\n \tldr\tr3, [r3, #4]\n-\tstr\tr3, [sp, #28]\n-\tmov\tr1, r3\n-\tmov\tr3, r5\n-\tadd.w\tr8, r1, #1\n-\tldr\tr1, [sp, #32]\n-\tmla\tr1, r1, r2, r9\n-\tadd\tr1, r6\n-\tldr\tr0, [sp, #28]\n-\tcmp\tr2, r0\n-\tbgt.n\t578 <__gridxc_array_MOD_aa_4d_1d_sp+0x320>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tadd.w\tr8, r3, #1\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstrd\tip, r4, [sp, #80]\t@ 0x50\n+\tmla\tr1, r7, r1, r3\n+\tmov\tr3, r0\n+\tmov\tr7, r9\n+\tadd\tr1, ip\n+\tldrd\tr4, r2, [sp, #40]\t@ 0x28\n+\tcmp\tr4, r2\n+\tbgt.n\t484 <__gridxc_array_MOD_aa_4d_1d_sp+0x228>\n+\tldr\tr2, [sp, #16]\n \tmov\tr5, r1\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tstr\tr2, [sp, #20]\n-\tldr\tr6, [r0, #0]\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #16]\n-\tstr\tr1, [sp, #24]\n-\tmul.w\tlr, r4, r6\n-\tldr\tr7, [r0, #0]\n-\tldr\tr4, [sp, #12]\n-\tadds\tr0, r7, #1\n+\tstrd\tr3, r1, [sp, #32]\n+\tldr\tr6, [r2, #0]\n+\tldr\tr2, [sp, #20]\n+\tldr.w\tip, [r2]\n+\tldr\tr2, [sp, #24]\n+\tadd.w\tr0, ip, #1\n \tsub.w\tr9, r0, r6\n-\tadd.w\tlr, r4, lr, lsl #2\n-\tmov\tr4, r2\n-\tcmp\tr6, r7\n-\tbgt.n\t568 <__gridxc_array_MOD_aa_4d_1d_sp+0x310>\n+\tmul.w\tlr, r6, r2\n+\tldr\tr2, [sp, #28]\n+\tadd.w\tlr, r2, lr, lsl #2\n+\tcmp\tr6, ip\n+\tbgt.n\t476 <__gridxc_array_MOD_aa_4d_1d_sp+0x21a>\n \tldr\tr2, [sp, #4]\n \tadd.w\tr3, sl, #4294967295\t@ 0xffffffff\n \tadd.w\tr1, lr, r5, lsl #2\n \tmul.w\tr3, r2, r3\n \tldr\tr2, [sp, #8]\n \tadd.w\tr3, r2, r3, lsl #2\n \tmov\tr2, r6\n \tvldr\ts15, [r3]\n \tadds\tr2, #1\n \tvldr\ts14, [r1]\n \tcmp\tr2, r0\n-\tadd\tr1, fp\n+\tadd\tr1, r7\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r3]\n-\tadd\tr3, ip\n-\tbne.n\t54c <__gridxc_array_MOD_aa_4d_1d_sp+0x2f4>\n+\tadd\tr3, fp\n+\tbne.n\t45a <__gridxc_array_MOD_aa_4d_1d_sp+0x1fe>\n \tadd\tsl, r9\n-\tldr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #0]\n \tadds\tr4, #1\n \tcmp\tr4, r8\n \tadd\tr5, r3\n-\tbne.n\t532 <__gridxc_array_MOD_aa_4d_1d_sp+0x2da>\n-\tldrd\tr3, r2, [sp, #16]\n-\tldr\tr1, [sp, #24]\n-\tldr\tr0, [sp, #48]\t@ 0x30\n+\tbne.n\t440 <__gridxc_array_MOD_aa_4d_1d_sp+0x1e4>\n+\tldrd\tr3, r1, [sp, #32]\n \tadds\tr3, #1\n-\tadd\tr1, r0\n-\tldr\tr0, [sp, #36]\t@ 0x24\n-\tcmp\tr3, r0\n-\tbne.n\t508 <__gridxc_array_MOD_aa_4d_1d_sp+0x2b0>\n-\tldrd\tr5, r7, [sp, #60]\t@ 0x3c\n-\tldrd\tr0, r9, [sp, #68]\t@ 0x44\n-\tldrd\tr6, r4, [sp, #80]\t@ 0x50\n-\tldr.w\tlr, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tadds\tr0, #1\n-\tcmp\tr0, r4\n-\tadd\tr6, r3\n-\tbne.n\t4da <__gridxc_array_MOD_aa_4d_1d_sp+0x282>\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tb.n\t48c <__gridxc_array_MOD_aa_4d_1d_sp+0x234>\n+\tldr\tr2, [sp, #12]\n+\tadd\tr1, r2\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tcmp\tr3, r2\n+\tbne.n\t414 <__gridxc_array_MOD_aa_4d_1d_sp+0x1b8>\n+\tldrd\tr6, r0, [sp, #64]\t@ 0x40\n+\tmov\tr9, r7\n+\tldrd\tr5, r2, [sp, #72]\t@ 0x48\n+\tldrd\tip, r4, [sp, #80]\t@ 0x50\n+\tadds\tr2, #1\n+\tadd\tip, r6\n+\tcmp\tr2, r4\n+\tbne.n\t3e4 <__gridxc_array_MOD_aa_4d_1d_sp+0x188>\n+\tldr\tr6, [sp, #60]\t@ 0x3c\n+\tb.n\t39a <__gridxc_array_MOD_aa_4d_1d_sp+0x13e>\n \tnop\n-\t.word\t0x0000033e\n+\t.word\t0x00000244\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000110\n+\t.word\t0x00000108\n R_ARM_REL32\t.LC1\n \n-000005b0 <__gridxc_array_MOD_aa_4d_1d_ip>:\n+000004b8 <__gridxc_array_MOD_aa_4d_1d_ip>:\n __gridxc_array_MOD_aa_4d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr.w\tr9, [pc, #828]\t@ 8f4 <__gridxc_array_MOD_aa_4d_1d_ip+0x344>\n-\tsub\tsp, #132\t@ 0x84\n-\tadd\tr9, pc\n-\tstrd\tr0, r1, [sp, #52]\t@ 0x34\n-\tldr\tr1, [sp, #172]\t@ 0xac\n-\tldr\tr4, [sp, #168]\t@ 0xa8\n+\tldr.w\tr8, [pc, #592]\t@ 710 <__gridxc_array_MOD_aa_4d_1d_ip+0x258>\n+\tsub\tsp, #100\t@ 0x64\n+\tadd\tr8, pc\n+\tstrd\tr0, r1, [sp, #24]\n+\tmov\tr1, r3\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tldr\tr0, [r2, #24]\n-\tstr\tr4, [sp, #88]\t@ 0x58\n-\tldr\tr4, [r1, #24]\n-\tldr.w\tr8, [r1]\n-\tcmp\tr4, #0\n-\tstr\tr0, [sp, #24]\n-\tit\teq\n-\tmoveq\tr4, #1\n-\tstr\tr4, [sp, #16]\n-\tcmp\tr0, #0\n-\tbeq.w\t7ee <__gridxc_array_MOD_aa_4d_1d_ip+0x23e>\n-\tnegs\tr0, r0\n-\tldr.w\tfp, [r3]\n-\tldr\tr3, [r2, #36]\t@ 0x24\n+\tldr\tr4, [sp, #136]\t@ 0x88\n+\tldr\tr5, [r3, #24]\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tcmp\tr5, #0\n+\tldr\tr4, [r3, #0]\n+\tstr\tr0, [sp, #36]\t@ 0x24\n+\tite\tne\n+\tmovne\tr3, r5\n+\tmoveq\tr3, #1\n+\tstr\tr3, [sp, #12]\n+\tnegs\tr3, r0\n+\tcbnz\tr0, 4ee <__gridxc_array_MOD_aa_4d_1d_ip+0x36>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tmovs\tr0, #1\n+\tstr\tr0, [sp, #36]\t@ 0x24\n+\tldr.w\tsl, [r1]\n+\tldr\tr1, [r2, #36]\t@ 0x24\n+\tstr\tr1, [sp, #4]\n+\tsubs\tr3, r3, r1\n \tldr\tr1, [r2, #48]\t@ 0x30\n-\tldr\tr6, [r2, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #8]\n-\tsubs\tr3, r0, r3\n+\tldr\tr0, [sp, #28]\n \tsubs\tr3, r3, r1\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tsubs\tr4, r3, r6\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr1, [sp, #20]\n+\tldr\tr1, [sp, #24]\n+\tldr.w\tip, [r2, #60]\t@ 0x3c\n \tldr\tr2, [r2, #0]\n-\tldr\tr7, [r1, #12]\n-\tstr\tr2, [sp, #28]\n-\tldr\tr2, [r3, #12]\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tcmp\tr2, r7\n-\tbgt.w\t7ca <__gridxc_array_MOD_aa_4d_1d_ip+0x21a>\n-\tldr.w\tip, [r3, #8]\n-\tldr\tr2, [sp, #24]\n-\tldr\tr3, [sp, #16]\n-\tldr.w\tlr, [r1, #8]\n-\tcmp\tr2, #1\n+\tldr\tr5, [r1, #12]\n+\tsub.w\tr3, r3, ip\n+\tstr\tr2, [sp, #32]\n+\tldr\tr2, [r0, #12]\n+\tcmp\tr5, r2\n+\tbgt.n\t5fc <__gridxc_array_MOD_aa_4d_1d_ip+0x144>\n+\tldr\tr6, [r1, #8]\n+\tldr.w\tlr, [r0, #8]\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tldr\tr0, [sp, #12]\n+\tcmp\tr0, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.w\t7fe <__gridxc_array_MOD_aa_4d_1d_ip+0x24e>\n-\tadd.w\tsl, r7, #1\n-\tldr\tr7, [sp, #48]\t@ 0x30\n-\tldr\tr1, [sp, #8]\n-\tstr.w\tr9, [sp, #100]\t@ 0x64\n-\tmov\tr9, r8\n-\tadds\tr3, r7, r1\n-\tldr.w\tr8, [sp, #28]\n-\tmul.w\tr2, r7, ip\n-\tadds\tr5, r3, r6\n-\tstr.w\tlr, [sp, #92]\t@ 0x5c\n-\tsubs\tr3, r2, r6\n-\tstr\tr0, [sp, #96]\t@ 0x60\n-\tsubs\tr3, r3, r1\n-\tadd\tr2, r4\n-\tsubs\tr3, r3, r7\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tadd\tr3, r0\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\trsb\tr2, r7, r7, lsl #30\n-\tmov\tr0, sl\n-\tmov\tr7, r6\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tmov\tr1, ip\n-\tadd.w\tr2, lr, #1\n-\tmov\tlr, fp\n-\tmul.w\tr3, r6, r3\n-\tmov\tr6, r4\n-\tstr\tr2, [sp, #68]\t@ 0x44\n+\tcmpeq\tr1, #1\n+\tbne.n\t620 <__gridxc_array_MOD_aa_4d_1d_ip+0x168>\n+\tmla\tr1, ip, r5, r3\n+\tadds\tr3, r2, #1\n+\tldr\tr2, [sp, #20]\n+\tstr\tr4, [sp, #0]\n \tmov\tr4, r3\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tcmp\tr1, r3\n-\tbgt.w\t7b6 <__gridxc_array_MOD_aa_4d_1d_ip+0x206>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tstrd\tr1, r4, [sp, #112]\t@ 0x70\n-\tldr.w\tfp, [r3, #4]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstrd\tr7, r6, [sp, #104]\t@ 0x68\n-\tstrd\tr0, r5, [sp, #120]\t@ 0x78\n+\tstr.w\tr8, [sp, #40]\t@ 0x28\n+\tmul.w\tr7, r2, r6\n+\tldr\tr2, [sp, #4]\n+\tmov.w\tfp, r2, lsl #2\n+\tadd.w\tr2, lr, #1\n+\tstr\tr2, [sp, #36]\t@ 0x24\n+\tmov\tr2, lr\n+\tmov\tlr, ip\n+\tmov\tip, r2\n+\tcmp\tr6, ip\n+\tbgt.n\t5f0 <__gridxc_array_MOD_aa_4d_1d_ip+0x138>\n+\tldr\tr3, [sp, #24]\n+\tmov\tr0, r6\n+\tstrd\tlr, r6, [sp, #44]\t@ 0x2c\n+\tstrd\tip, r5, [sp, #52]\t@ 0x34\n+\tldr\tr2, [r3, #4]\n+\tldr\tr3, [sp, #28]\n+\tstr\tr7, [sp, #60]\t@ 0x3c\n+\tstrd\tr1, r4, [sp, #68]\t@ 0x44\n \tldr\tr3, [r3, #4]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tadds\tr3, r4, r2\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\trsb\tsl, r3, r3, lsl #30\n-\tldr\tr3, [sp, #96]\t@ 0x60\n-\tadd.w\tip, r4, r2\n-\tldr\tr2, [sp, #8]\n-\tmov\tr4, fp\n-\tmla\tr2, r2, fp, r5\n-\tmov\tfp, sl\n-\tmov\tsl, r1\n-\tsubs\tr2, r2, r3\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tadd\tr2, r6\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tmov\tr2, ip\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr3, r4\n-\tblt.n\t798 <__gridxc_array_MOD_aa_4d_1d_ip+0x1e8>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tmov\tr0, r4\n-\tstrd\tsl, r4, [sp, #36]\t@ 0x24\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr6, [r3, #0]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr5, [r3, #0]\n-\tadd.w\tr3, r2, fp\n-\tadd\tr3, r6\n-\tsub.w\tip, r5, r6\n-\tadd.w\tr7, ip, #1\n-\tadd.w\tr3, r8, r3, lsl #2\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tstr\tr7, [sp, #4]\n-\tadds\tr1, r3, r2\n-\tbic.w\tr3, r7, #3\n \tstr\tr3, [sp, #16]\n-\tlsrs\tr3, r7, #2\n-\tlsls\tr3, r3, #4\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #16]\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #32]\n-\tand.w\tr3, r7, #3\n-\tstr\tr3, [sp, #28]\n-\tcmp\tr5, r6\n-\tblt.n\t786 <__gridxc_array_MOD_aa_4d_1d_ip+0x1d6>\n-\tcmp.w\tip, #2\n-\tbls.n\t7e8 <__gridxc_array_MOD_aa_4d_1d_ip+0x238>\n-\tadd.w\tr3, lr, #1073741824\t@ 0x40000000\n-\tldr\tr2, [sp, #24]\n-\tsubs\tr3, #1\n-\tldr\tr4, [sp, #20]\n-\tldr\tr7, [sp, #4]\n-\tadd.w\tr3, r9, r3, lsl #2\n-\tadd.w\tr2, r2, r1, lsl #2\n-\tadd\tr4, r3\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvadd.i32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tr4, r3\n-\tbne.n\t71c <__gridxc_array_MOD_aa_4d_1d_ip+0x16c>\n-\tldr\tr2, [sp, #28]\n-\tldr\tr3, [sp, #16]\n-\tstr\tr7, [sp, #4]\n-\tadd\tr3, lr\n-\tcbz\tr2, 782 <__gridxc_array_MOD_aa_4d_1d_ip+0x1d2>\n-\tldr\tr2, [sp, #32]\n-\tsubs\tr3, #1\n-\tadds\tr4, r1, r2\n-\tldr.w\tr7, [r9, r3, lsl #2]\n-\tldr.w\tr4, [r8, r4, lsl #2]\n-\tadd\tr4, r7\n-\tstr.w\tr4, [r9, r3, lsl #2]\n-\tadds\tr4, r2, #1\n-\tlsls\tr3, r3, #2\n-\tcmp\tr5, r4\n-\tblt.n\t782 <__gridxc_array_MOD_aa_4d_1d_ip+0x1d2>\n-\tadd.w\tsl, r3, #4\n-\tadd\tr4, r1\n-\tadds\tr2, #2\n-\tcmp\tr5, r2\n-\tldr.w\tr7, [r9, sl]\n-\tldr.w\tr4, [r8, r4, lsl #2]\n-\tadd\tr4, r7\n-\tstr.w\tr4, [r9, sl]\n-\tblt.n\t782 <__gridxc_array_MOD_aa_4d_1d_ip+0x1d2>\n-\tadds\tr3, #8\n-\tadd\tr2, r1\n-\tldr.w\tr4, [r8, r2, lsl #2]\n-\tldr.w\tr2, [r9, r3]\n-\tadd\tr2, r4\n-\tstr.w\tr2, [r9, r3]\n+\tadd.w\tr8, r3, #1\n \tldr\tr3, [sp, #4]\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #8]\n+\tmla\tr3, r3, r2, r7\n+\tadd\tr3, r1\n+\tldr\tr1, [sp, #16]\n+\tcmp\tr1, r2\n+\tblt.n\t5d6 <__gridxc_array_MOD_aa_4d_1d_ip+0x11e>\n+\tldr\tr1, [sp, #28]\n+\tmov\tr5, r2\n+\tstrd\tr0, r2, [sp, #8]\n+\tldr\tr6, [r1, #0]\n+\tldr\tr1, [sp, #24]\n+\tadds\tr4, r6, r3\n+\tadd.w\tlr, r6, #1\n+\tldr.w\tip, [r1]\n+\tldr\tr1, [sp, #32]\n+\tsub.w\tr7, ip, r6\n+\tsub.w\tlr, lr, ip\n+\tlsls\tr7, r7, #2\n+\tadd.w\tr4, r1, r4, lsl #2\n+\tsubs\tr7, #4\n+\tcmp\tr6, ip\n+\tblt.n\t5ca <__gridxc_array_MOD_aa_4d_1d_ip+0x112>\n+\tldr\tr2, [sp, #0]\n+\tadds\tr1, r7, r4\n+\tmov\tr9, r3\n+\tadd.w\tr2, r2, sl, lsl #2\n+\tsubs\tr2, #8\n+\tldr.w\tr0, [r2, #4]!\n+\tldr.w\tr3, [r1, #4]!\n+\tadd\tr0, r3\n+\tcmp\tr1, r4\n+\tstr\tr0, [r2, #0]\n+\tbne.n\t5b6 <__gridxc_array_MOD_aa_4d_1d_ip+0xfe>\n+\tmov\tr3, r9\n+\tadd\tsl, lr\n+\tadds\tr5, #1\n+\tadd\tr4, fp\n+\tcmp\tr5, r8\n+\tbne.n\t5a6 <__gridxc_array_MOD_aa_4d_1d_ip+0xee>\n+\tldrd\tr0, r2, [sp, #8]\n \tadds\tr0, #1\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #12]\n-\tcmp\tr0, r3\n-\tbne.n\t6fc <__gridxc_array_MOD_aa_4d_1d_ip+0x14c>\n-\tldrd\tsl, r4, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tsl, sl, #1\n-\tadd\tr2, r3\n+\tldr\tr1, [sp, #20]\n+\tadd\tr3, r1\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tcmp\tr0, r1\n+\tbne.n\t578 <__gridxc_array_MOD_aa_4d_1d_ip+0xc0>\n+\tldrd\tlr, r6, [sp, #44]\t@ 0x2c\n+\tldrd\tip, r5, [sp, #52]\t@ 0x34\n+\tldr\tr7, [sp, #60]\t@ 0x3c\n+\tldrd\tr1, r4, [sp, #68]\t@ 0x44\n+\tadds\tr5, #1\n+\tadd\tr1, lr\n+\tcmp\tr5, r4\n+\tbne.n\t54e <__gridxc_array_MOD_aa_4d_1d_ip+0x96>\n+\tldr.w\tr8, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tcmp\tsl, r3\n-\tbne.n\t6b4 <__gridxc_array_MOD_aa_4d_1d_ip+0x104>\n-\tldrd\tr7, r6, [sp, #104]\t@ 0x68\n-\tldrd\tr1, r4, [sp, #112]\t@ 0x70\n-\tldrd\tr0, r5, [sp, #120]\t@ 0x78\n-\tadd\tr4, r7\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tcmp\tr3, r0\n-\tbne.w\t66a <__gridxc_array_MOD_aa_4d_1d_ip+0xba>\n-\tldr.w\tr9, [sp, #100]\t@ 0x64\n-\tmov\tfp, lr\n-\tldr\tr3, [sp, #88]\t@ 0x58\n \tldr\tr3, [r3, #0]\n-\tcmp\tr3, fp\n-\tblt.n\t7f8 <__gridxc_array_MOD_aa_4d_1d_ip+0x248>\n-\tldr\tr3, [pc, #292]\t@ (8f8 <__gridxc_array_MOD_aa_4d_1d_ip+0x348>)\n+\tcmp\tr3, sl\n+\tblt.n\t61a <__gridxc_array_MOD_aa_4d_1d_ip+0x162>\n+\tldr\tr3, [pc, #268]\t@ (714 <__gridxc_array_MOD_aa_4d_1d_ip+0x25c>)\n \tmovs\tr1, #22\n-\tldr\tr0, [pc, #292]\t@ (8fc <__gridxc_array_MOD_aa_4d_1d_ip+0x34c>)\n+\tldr\tr0, [pc, #268]\t@ (718 <__gridxc_array_MOD_aa_4d_1d_ip+0x260>)\n \tadd\tr0, pc\n-\tldr.w\tr3, [r9, r3]\n+\tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #132\t@ 0x84\n+\tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr2, r6\n-\tmov\tr3, lr\n-\tb.n\t73c <__gridxc_array_MOD_aa_4d_1d_ip+0x18c>\n-\tmovs\tr1, #1\n-\tmov.w\tr0, #4294967295\t@ 0xffffffff\n-\tstr\tr1, [sp, #24]\n-\tb.n\t5e0 <__gridxc_array_MOD_aa_4d_1d_ip+0x30>\n-\tadd\tsp, #132\t@ 0x84\n+\tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tmla\tr7, ip, r5, r3\n+\tldr\tr3, [sp, #20]\n+\tadds\tr2, #1\n+\tmov.w\tr9, r1, lsl #2\n+\tmov.w\tfp, r0, lsl #2\n+\tmov\tr1, r2\n+\tmov\tr2, sl\n+\tstr\tr4, [sp, #16]\n+\tmul.w\tr3, r3, r6\n+\tstr.w\tr8, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr3, lr, #1\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr6, lr\n+\tbgt.n\t700 <__gridxc_array_MOD_aa_4d_1d_ip+0x248>\n+\tldr\tr3, [sp, #24]\n+\tstrd\tlr, r5, [sp, #80]\t@ 0x50\n+\tstrd\tip, r6, [sp, #72]\t@ 0x48\n+\tldr\tr4, [r3, #4]\n+\tldr\tr3, [sp, #28]\n+\tmov\tr5, r4\n+\tstrd\tr7, r1, [sp, #88]\t@ 0x58\n+\tldr\tr3, [r3, #4]\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tmov\tr0, r3\n+\tldr\tr3, [sp, #4]\n+\tadds\tr0, #1\n+\tstr\tr0, [sp, #8]\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n+\tmla\tr0, r3, r4, r0\n+\tmov\tr4, r6\n+\tadd\tr0, r7\n+\tmov\tr3, r0\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tcmp\tr5, r1\n+\tbgt.n\t6e8 <__gridxc_array_MOD_aa_4d_1d_ip+0x230>\n+\tldr\tr1, [sp, #24]\n+\tmov\tip, r3\n+\tldr\tr0, [sp, #36]\t@ 0x24\n+\tmov\tr7, r5\n+\tstrd\tr5, r4, [sp, #40]\t@ 0x28\n+\tldr.w\tlr, [r1]\n+\tldr\tr1, [sp, #28]\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr.w\tr8, [r1]\n+\tmul.w\tsl, lr, r0\n+\tldr\tr0, [sp, #32]\n+\tadd.w\tr6, r8, #1\n+\tsub.w\tr1, r6, lr\n+\tadd.w\tsl, r0, sl, lsl #2\n+\tcmp\tlr, r8\n+\tbgt.n\t6d6 <__gridxc_array_MOD_aa_4d_1d_ip+0x21e>\n+\tldr\tr0, [sp, #12]\n+\tsubs\tr3, r2, #1\n+\tadd.w\tr5, sl, ip, lsl #2\n+\tmov\tr4, lr\n+\tstr\tr2, [sp, #0]\n+\tmul.w\tr3, r0, r3\n+\tldr\tr0, [sp, #16]\n+\tadd.w\tr3, r0, r3, lsl #2\n+\tldr\tr0, [r3, #0]\n+\tadds\tr4, #1\n+\tldr\tr2, [r5, #0]\n+\tcmp\tr4, r6\n+\tadd\tr5, r9\n+\tadd\tr0, r2\n+\tstr\tr0, [r3, #0]\n+\tadd\tr3, fp\n+\tbne.n\t6c0 <__gridxc_array_MOD_aa_4d_1d_ip+0x208>\n+\tldr\tr2, [sp, #0]\n+\tadd\tr2, r1\n+\tldr\tr3, [sp, #4]\n \tadds\tr7, #1\n-\tstr.w\tr8, [sp, #20]\n-\tmov\tr8, r6\n-\tmla\tr5, r6, r3, r4\n+\tadd\tip, r3\n+\tldr\tr3, [sp, #8]\n+\tcmp\tr7, r3\n+\tbne.n\t6a6 <__gridxc_array_MOD_aa_4d_1d_ip+0x1ee>\n+\tldrd\tr5, r4, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr4, lr, #1\n-\tstrd\tr4, r9, [sp, #60]\t@ 0x3c\n-\tmul.w\tr1, r3, ip\n-\tldr\tr3, [sp, #16]\n-\tmov\tr6, r1\n-\tmov\tr1, fp\n-\tmov.w\tsl, r3, lsl #2\n-\tlsls\tr3, r2, #2\n-\tcmp\tip, lr\n-\tbgt.n\t8e0 <__gridxc_array_MOD_aa_4d_1d_ip+0x330>\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tstrd\tlr, r6, [sp, #80]\t@ 0x50\n-\tstr\tr5, [sp, #92]\t@ 0x5c\n-\tldr\tr0, [r2, #4]\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tstrd\tr8, ip, [sp, #68]\t@ 0x44\n-\tstr\tr7, [sp, #96]\t@ 0x60\n-\tldr\tr2, [r2, #4]\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tmov\tr4, r2\n+\tldr\tr1, [sp, #20]\n \tadds\tr4, #1\n-\tstr\tr4, [sp, #12]\n-\tldr\tr4, [sp, #8]\n-\tmla\tr4, r4, r0, r6\n-\tmov\tr6, r0\n-\tadd\tr4, r5\n-\tmov\tr5, ip\n-\tmov\tr2, r4\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tcmp\tr6, r0\n-\tbgt.n\t8c8 <__gridxc_array_MOD_aa_4d_1d_ip+0x318>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tmov\tlr, r2\n-\tldr\tr4, [sp, #24]\n-\tmov\tip, r6\n-\tstrd\tr6, r5, [sp, #32]\n-\tldr.w\tr8, [r0]\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tldr.w\tr9, [r0]\n-\tmul.w\tfp, r4, r8\n-\tldr\tr4, [sp, #28]\n-\tadd.w\tr7, r9, #1\n-\tsub.w\tr0, r7, r8\n-\tadd.w\tfp, r4, fp, lsl #2\n-\tcmp\tr8, r9\n-\tbgt.n\t8b4 <__gridxc_array_MOD_aa_4d_1d_ip+0x304>\n-\tldr\tr4, [sp, #16]\n-\tsubs\tr2, r1, #1\n-\tadd.w\tr6, fp, lr, lsl #2\n-\tmov\tr5, r8\n-\tstr\tr1, [sp, #4]\n-\tmul.w\tr2, r4, r2\n-\tldr\tr4, [sp, #20]\n-\tadd.w\tr2, r4, r2, lsl #2\n-\tldr\tr4, [r2, #0]\n-\tadds\tr5, #1\n-\tldr\tr1, [r6, #0]\n-\tcmp\tr5, r7\n-\tadd\tr6, r3\n-\tadd\tr4, r1\n-\tstr\tr4, [r2, #0]\n-\tadd\tr2, sl\n-\tbne.n\t89e <__gridxc_array_MOD_aa_4d_1d_ip+0x2ee>\n-\tldr\tr1, [sp, #4]\n-\tadd\tr1, r0\n-\tldr\tr2, [sp, #8]\n-\tadd.w\tip, ip, #1\n-\tadd\tlr, r2\n-\tldr\tr2, [sp, #12]\n-\tcmp\tip, r2\n-\tbne.n\t884 <__gridxc_array_MOD_aa_4d_1d_ip+0x2d4>\n-\tldrd\tr6, r5, [sp, #32]\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr0, [sp, #48]\t@ 0x30\n+\tadd\tr3, r1\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tcmp\tr4, r1\n+\tbne.n\t676 <__gridxc_array_MOD_aa_4d_1d_ip+0x1be>\n+\tldrd\tip, r6, [sp, #72]\t@ 0x48\n+\tldrd\tlr, r5, [sp, #80]\t@ 0x50\n+\tldrd\tr7, r1, [sp, #88]\t@ 0x58\n \tadds\tr5, #1\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tcmp\tr5, r0\n-\tbne.n\t854 <__gridxc_array_MOD_aa_4d_1d_ip+0x2a4>\n-\tldrd\tr8, ip, [sp, #68]\t@ 0x44\n-\tldrd\tlr, r6, [sp, #80]\t@ 0x50\n-\tldrd\tr5, r7, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r8\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tcmp\tr2, r7\n-\tbne.n\t826 <__gridxc_array_MOD_aa_4d_1d_ip+0x276>\n-\tldr.w\tr9, [sp, #64]\t@ 0x40\n-\tmov\tfp, r1\n-\tb.n\t7ca <__gridxc_array_MOD_aa_4d_1d_ip+0x21a>\n-\t.word\t0x00000336\n+\tadd\tr7, ip\n+\tcmp\tr5, r1\n+\tbne.n\t646 <__gridxc_array_MOD_aa_4d_1d_ip+0x18e>\n+\tldr.w\tr8, [sp, #68]\t@ 0x44\n+\tmov\tsl, r2\n+\tb.n\t5fc <__gridxc_array_MOD_aa_4d_1d_ip+0x144>\n+\t.word\t0x0000024a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000120\n+\t.word\t0x0000010a\n R_ARM_REL32\t.LC2\n \n-00000900 <__gridxc_array_MOD_aa_3d_1d_dp>:\n+0000071c <__gridxc_array_MOD_aa_3d_1d_dp>:\n __gridxc_array_MOD_aa_3d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov\tr4, r2\n \tmov\tr2, r3\n \tsub\tsp, #68\t@ 0x44\n-\tldr\tr6, [pc, #460]\t@ (ad8 <__gridxc_array_MOD_aa_3d_1d_dp+0x1d8>)\n+\tldr\tr6, [pc, #464]\t@ (8f8 <__gridxc_array_MOD_aa_3d_1d_dp+0x1dc>)\n \tadd\tr6, pc\n \tldr\tr3, [sp, #108]\t@ 0x6c\n \tstrd\tr0, r1, [sp, #24]\n \tldr\tr1, [r4, #24]\n \tldr\tr0, [r3, #24]\n \tldr.w\tip, [r3]\n-\tnegs\tr3, r1\n \tcmp\tr0, #0\n \tldr\tr7, [sp, #104]\t@ 0x68\n-\tit\teq\n-\tmoveq\tr0, #1\n+\tite\tne\n+\tmovne\tr3, r0\n+\tmoveq\tr3, #1\n \tstr\tr1, [sp, #32]\n-\tstr\tr0, [sp, #8]\n-\tcbnz\tr1, 934 <__gridxc_array_MOD_aa_3d_1d_dp+0x34>\n+\tstr\tr3, [sp, #8]\n+\tnegs\tr3, r1\n+\tcbnz\tr1, 752 <__gridxc_array_MOD_aa_3d_1d_dp+0x36>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr1, #1\n \tstr\tr1, [sp, #32]\n \tldr.w\tfp, [r4, #36]\t@ 0x24\n \tldr\tr0, [r2, #0]\n \tldr\tr2, [r4, #48]\t@ 0x30\n \tsub.w\tr3, r3, fp\n@@ -954,25 +770,25 @@\n \tldr\tr3, [sp, #24]\n \tldr\tr1, [r4, #0]\n \tstr\tr1, [sp, #36]\t@ 0x24\n \tldr\tr4, [r5, #8]\n \tldr\tr1, [r3, #8]\n \tstr\tr2, [sp, #16]\n \tcmp\tr1, r4\n-\tbgt.n\ta04 <__gridxc_array_MOD_aa_3d_1d_dp+0x104>\n+\tbgt.n\t826 <__gridxc_array_MOD_aa_3d_1d_dp+0x10a>\n \tldr\tr5, [r5, #4]\n-\tldr\tr2, [sp, #32]\n+\tldr\tr2, [sp, #8]\n \tstr\tr5, [sp, #20]\n-\tldr\tr5, [sp, #8]\n+\tldr\tr5, [sp, #32]\n \tldr\tr3, [r3, #4]\n \tcmp\tr2, #1\n \tit\teq\n \tcmpeq\tr5, #1\n \tadd.w\tr2, r4, #1\n-\tbne.n\ta24 <__gridxc_array_MOD_aa_3d_1d_dp+0x124>\n+\tbne.n\t846 <__gridxc_array_MOD_aa_3d_1d_dp+0x12a>\n \tstr\tr2, [sp, #8]\n \tmov.w\tlr, fp, lsl #3\n \tldr\tr2, [sp, #16]\n \tmov\tr5, ip\n \tldr\tr4, [sp, #36]\t@ 0x24\n \tmov\tr9, r1\n \tstrd\tr7, r6, [sp, #32]\n@@ -981,86 +797,87 @@\n \tmul.w\tr4, fp, r3\n \tmla\tr4, r2, r1, r4\n \tldr\tr2, [sp, #20]\n \tadd.w\tfp, r4, r8\n \tadd.w\tsl, r2, #1\n \tldr\tr2, [sp, #20]\n \tcmp\tr3, r2\n-\tbgt.n\t9f2 <__gridxc_array_MOD_aa_3d_1d_dp+0xf2>\n+\tbgt.n\t814 <__gridxc_array_MOD_aa_3d_1d_dp+0xf8>\n \tldr\tr2, [sp, #28]\n \tmov\tr6, r3\n \tstr\tr3, [sp, #4]\n \tldr\tr7, [r2, #0]\n \tldr\tr2, [sp, #24]\n \tadd.w\tr4, r7, fp\n \tadd.w\tr8, r7, #1\n \tldr\tr1, [r2, #0]\n \tldr\tr2, [sp, #12]\n \tsub.w\tip, r1, r7\n \tsub.w\tr8, r8, r1\n \tmov.w\tip, ip, lsl #3\n \tadd.w\tr4, r2, r4, lsl #3\n \tsub.w\tip, ip, #8\n-\tsubs\tr3, r0, #1\n-\tadd.w\tr2, ip, r4\n \tcmp\tr7, r1\n-\tadd.w\tr3, r5, r3, lsl #3\n-\tblt.n\t9e8 <__gridxc_array_MOD_aa_3d_1d_dp+0xe8>\n-\tvldr\td17, [r3]\n-\tvldmia\tr2!, {d16}\n-\tvadd.f64\td16, d16, d17\n+\tittt\tge\n+\taddge.w\tr3, r0, #4294967295\t@ 0xffffffff\n+\taddge.w\tr2, ip, r4\n+\taddge.w\tr3, r5, r3, lsl #3\n+\tblt.n\t80a <__gridxc_array_MOD_aa_3d_1d_dp+0xee>\n+\tvldr\td6, [r3]\n+\tvldmia\tr2!, {d7}\n+\tvadd.f64\td7, d7, d6\n \tcmp\tr2, r4\n-\tvstmia\tr3!, {d16}\n-\tbne.n\t9d2 <__gridxc_array_MOD_aa_3d_1d_dp+0xd2>\n+\tvstmia\tr3!, {d7}\n+\tbne.n\t7f4 <__gridxc_array_MOD_aa_3d_1d_dp+0xd8>\n \tadd\tr0, r8\n \tadds\tr6, #1\n \tadd\tr4, lr\n \tcmp\tr6, sl\n-\tbne.n\t9c4 <__gridxc_array_MOD_aa_3d_1d_dp+0xc4>\n+\tbne.n\t7e2 <__gridxc_array_MOD_aa_3d_1d_dp+0xc6>\n \tldr\tr3, [sp, #4]\n \tldr\tr2, [sp, #16]\n \tadd.w\tr9, r9, #1\n \tadd\tfp, r2\n \tldr\tr2, [sp, #8]\n \tcmp\tr9, r2\n-\tbne.n\t994 <__gridxc_array_MOD_aa_3d_1d_dp+0x94>\n+\tbne.n\t7b2 <__gridxc_array_MOD_aa_3d_1d_dp+0x96>\n \tldrd\tr7, r6, [sp, #32]\n \tldr\tr3, [r7, #0]\n \tcmp\tr3, r0\n-\tblt.n\ta1e <__gridxc_array_MOD_aa_3d_1d_dp+0x11e>\n-\tldr\tr3, [pc, #208]\t@ (adc <__gridxc_array_MOD_aa_3d_1d_dp+0x1dc>)\n+\tblt.n\t840 <__gridxc_array_MOD_aa_3d_1d_dp+0x124>\n+\tldr\tr3, [pc, #204]\t@ (8fc <__gridxc_array_MOD_aa_3d_1d_dp+0x1e0>)\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #208]\t@ (ae0 <__gridxc_array_MOD_aa_3d_1d_dp+0x1e0>)\n+\tldr\tr0, [pc, #204]\t@ (900 <__gridxc_array_MOD_aa_3d_1d_dp+0x1e4>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tstr\tr2, [sp, #52]\t@ 0x34\n \tmul.w\tr4, fp, r3\n \tldr\tr2, [sp, #16]\n-\tmov\tsl, ip\n-\tstrd\tr7, r6, [sp, #56]\t@ 0x38\n-\tmla\tr4, r2, r1, r4\n-\tadd.w\tr2, r8, r4\n-\tlsls\tr4, r5, #3\n-\tldr\tr5, [sp, #32]\n \tmov.w\tlr, r5, lsl #3\n \tldr\tr5, [sp, #20]\n+\tmov\tsl, ip\n+\tstrd\tr7, r6, [sp, #56]\t@ 0x38\n \tadds\tr5, #1\n \tstr\tr5, [sp, #4]\n+\tmla\tr4, r2, r1, r4\n+\tadd.w\tr2, r8, r4\n+\tldr\tr4, [sp, #8]\n \tmov\tr5, r2\n \tmov\tr2, r3\n \tmov\tr3, r5\n+\tlsls\tr4, r4, #3\n \tldr\tr5, [sp, #20]\n \tcmp\tr2, r5\n-\tbgt.n\tac4 <__gridxc_array_MOD_aa_3d_1d_dp+0x1c4>\n+\tbgt.n\t8e6 <__gridxc_array_MOD_aa_3d_1d_dp+0x1ca>\n \tldr\tr5, [sp, #24]\n \tmov\tr7, r3\n \tstr\tr2, [sp, #44]\t@ 0x2c\n \tstr\tr1, [sp, #40]\t@ 0x28\n \tldr.w\tip, [r5]\n \tldr\tr5, [sp, #28]\n \tstr\tr3, [sp, #48]\t@ 0x30\n@@ -1070,671 +887,518 @@\n \tstr\tr6, [sp, #12]\n \tldr\tr6, [sp, #32]\n \tmul.w\tr9, r6, ip\n \tldr\tr6, [sp, #36]\t@ 0x24\n \tadd.w\tr9, r6, r9, lsl #3\n \tmov\tr6, r2\n \tcmp\tip, r8\n-\tbgt.n\tab4 <__gridxc_array_MOD_aa_3d_1d_dp+0x1b4>\n+\tbgt.n\t8d6 <__gridxc_array_MOD_aa_3d_1d_dp+0x1ba>\n \tldr\tr2, [sp, #8]\n \tsubs\tr3, r0, #1\n \tadd.w\tr1, r9, r7, lsl #3\n \tmul.w\tr3, r2, r3\n \tmov\tr2, ip\n \tadd.w\tr3, sl, r3, lsl #3\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tvldr\td17, [r1]\n+\tvldr\td6, [r1]\n \tcmp\tr2, r5\n \tadd\tr1, lr\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r4\n-\tbne.n\ta96 <__gridxc_array_MOD_aa_3d_1d_dp+0x196>\n+\tbne.n\t8b8 <__gridxc_array_MOD_aa_3d_1d_dp+0x19c>\n \tldr\tr3, [sp, #12]\n \tadd\tr0, r3\n \tldr\tr3, [sp, #4]\n \tadds\tr6, #1\n \tadd\tr7, fp\n \tcmp\tr6, r3\n-\tbne.n\ta80 <__gridxc_array_MOD_aa_3d_1d_dp+0x180>\n+\tbne.n\t8a2 <__gridxc_array_MOD_aa_3d_1d_dp+0x186>\n \tldrd\tr1, r2, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tldr\tr5, [sp, #16]\n \tadds\tr1, #1\n \tadd\tr3, r5\n \tldr\tr5, [sp, #52]\t@ 0x34\n \tcmp\tr1, r5\n-\tbne.n\ta4e <__gridxc_array_MOD_aa_3d_1d_dp+0x14e>\n+\tbne.n\t870 <__gridxc_array_MOD_aa_3d_1d_dp+0x154>\n \tldrd\tr7, r6, [sp, #56]\t@ 0x38\n-\tb.n\ta04 <__gridxc_array_MOD_aa_3d_1d_dp+0x104>\n-\tnop\n-\t.word\t0x000001c8\n+\tb.n\t826 <__gridxc_array_MOD_aa_3d_1d_dp+0x10a>\n+\t.word\t0x000001cc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000cc\n+\t.word\t0x000000ca\n R_ARM_REL32\t.LC3\n \n-00000ae4 <__gridxc_array_MOD_aa_3d_1d_sp>:\n+00000904 <__gridxc_array_MOD_aa_3d_1d_sp>:\n __gridxc_array_MOD_aa_3d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tldr\tr7, [pc, #680]\t@ (d94 <__gridxc_array_MOD_aa_3d_1d_sp+0x2b0>)\n-\tsub\tsp, #84\t@ 0x54\n-\tadd\tr7, pc\n-\tstrd\tr0, r1, [sp, #52]\t@ 0x34\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [r2, #24]\n-\tldr.w\tip, [sp, #120]\t@ 0x78\n-\tldr.w\tfp, [r0, #24]\n-\tldr.w\tr8, [r0]\n-\tmovs\tr0, #1\n-\tcmp.w\tfp, #0\n-\tit\teq\n-\tmoveq\tfp, r0\n-\tnegs\tr0, r1\n-\tcbnz\tr1, b16 <__gridxc_array_MOD_aa_3d_1d_sp+0x32>\n-\tmov.w\tr0, #4294967295\t@ 0xffffffff\n-\tmovs\tr1, #1\n-\tldr.w\tsl, [r3]\n-\tldr\tr6, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr4, [r2, #36]\t@ 0x24\n-\tldr\tr5, [r2, #48]\t@ 0x30\n-\tldr.w\tr9, [r2]\n-\tldr\tr3, [r3, #8]\n-\tldr\tr2, [r6, #8]\n-\tstr\tr4, [sp, #0]\n-\tsubs\tr4, r0, r4\n-\tsub.w\tlr, r4, r5\n-\tcmp\tr3, r2\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tbgt.w\tcb8 <__gridxc_array_MOD_aa_3d_1d_sp+0x1d4>\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tldr\tr5, [r4, #4]\n-\tldr\tr4, [r6, #4]\n-\tstr\tr4, [sp, #48]\t@ 0x30\n-\tmov\tr4, fp\n-\tcmp\tr1, #1\n-\tit\teq\n-\tcmpeq\tr4, #1\n-\tstr\tr5, [sp, #32]\n-\tbne.w\tce0 <__gridxc_array_MOD_aa_3d_1d_sp+0x1fc>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadds\tr2, #1\n-\tldr\tr4, [sp, #0]\n-\tmov\tr6, r5\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tsubs\tr2, r3, #1\n-\tadds\tr5, r1, r4\n-\tstrd\tip, r7, [sp, #72]\t@ 0x48\n-\tmul.w\tr2, r1, r2\n-\tmul.w\tr1, r3, r1\n-\tsubs\tr2, r2, r4\n-\tmla\tr4, r4, r6, r5\n-\tsubs\tr5, r1, r5\n-\tadd\tr1, lr\n-\tsubs\tr4, r4, r0\n-\tadd\tr2, r0\n-\tadd.w\tfp, r5, r0\n-\tadd.w\tr0, r4, lr\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tlsls\tr0, r1, #2\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tldr.w\tlr, [sp]\n-\tstr.w\tfp, [sp, #28]\n-\tmov\tfp, r2\n-\tlsls\tr1, r1, #2\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #48]\t@ 0x30\n+\tmov\tr4, r2\n \tmov\tr2, r3\n-\tstr\tr0, [sp, #24]\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #4]\n-\tldr\tr3, [sp, #32]\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tcmp\tr3, r1\n-\tbgt.n\tc98 <__gridxc_array_MOD_aa_3d_1d_sp+0x1b4>\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tldr\tr6, [sp, #68]\t@ 0x44\n-\tstrd\tr2, fp, [sp, #36]\t@ 0x24\n-\tldr\tr5, [r1, #0]\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tadd.w\tr0, r5, fp\n-\tldr\tr4, [r1, #0]\n-\tldr\tr1, [sp, #24]\n-\tsubs\tr7, r4, r5\n-\tsub.w\tr3, r9, r1\n-\tldr\tr1, [sp, #28]\n-\tadd\tr1, r6\n-\tadd.w\tr6, r3, r0, lsl #2\n-\tstr\tr6, [sp, #12]\n-\tadds\tr6, r7, #1\n-\tldr\tr0, [sp, #32]\n-\tbic.w\tip, r6, #3\n-\tlsrs\tr3, r6, #2\n-\tlsls\tr3, r3, #4\n+\tsub\tsp, #68\t@ 0x44\n+\tldr\tr6, [pc, #464]\t@ (ae0 <__gridxc_array_MOD_aa_3d_1d_sp+0x1dc>)\n+\tadd\tr6, pc\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tstrd\tr0, r1, [sp, #24]\n+\tldr\tr1, [r4, #24]\n+\tldr\tr0, [r3, #24]\n+\tldr.w\tip, [r3]\n+\tcmp\tr0, #0\n+\tldr\tr7, [sp, #104]\t@ 0x68\n+\tite\tne\n+\tmovne\tr3, r0\n+\tmoveq\tr3, #1\n+\tstr\tr1, [sp, #32]\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, ip, r5\n-\tstr\tr3, [sp, #20]\n-\tand.w\tr3, r6, #3\n-\tstr\tr3, [sp, #16]\n-\tcmp\tr4, r5\n-\tblt.n\tc8a <__gridxc_array_MOD_aa_3d_1d_sp+0x1a6>\n-\tcmp\tr7, #2\n-\tbls.n\tcd4 <__gridxc_array_MOD_aa_3d_1d_sp+0x1f0>\n-\tldr\tr2, [sp, #12]\n-\tadd.w\tr3, sl, #1073741824\t@ 0x40000000\n-\tsubs\tr3, #1\n-\tadd.w\tr2, r2, r1, lsl #2\n-\tstr\tr2, [sp, #0]\n+\tnegs\tr3, r1\n+\tcbnz\tr1, 93a <__gridxc_array_MOD_aa_3d_1d_sp+0x36>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tmovs\tr1, #1\n+\tstr\tr1, [sp, #32]\n+\tldr.w\tfp, [r4, #36]\t@ 0x24\n+\tldr\tr0, [r2, #0]\n+\tldr\tr2, [r4, #48]\t@ 0x30\n+\tsub.w\tr3, r3, fp\n+\tldr\tr5, [sp, #28]\n+\tsub.w\tr8, r3, r2\n+\tldr\tr3, [sp, #24]\n+\tldr\tr1, [r4, #0]\n+\tstr\tr1, [sp, #36]\t@ 0x24\n+\tldr\tr4, [r5, #8]\n+\tldr\tr1, [r3, #8]\n+\tstr\tr2, [sp, #16]\n+\tcmp\tr1, r4\n+\tbgt.n\ta0e <__gridxc_array_MOD_aa_3d_1d_sp+0x10a>\n+\tldr\tr5, [r5, #4]\n \tldr\tr2, [sp, #8]\n-\tadd.w\tr3, r8, r3, lsl #2\n-\tadd.w\tfp, r2, r3\n-\tldr\tr2, [sp, #0]\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvadd.f32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tfp, r3\n-\tbne.n\tc06 <__gridxc_array_MOD_aa_3d_1d_sp+0x122>\n+\tstr\tr5, [sp, #20]\n+\tldr\tr5, [sp, #32]\n+\tldr\tr3, [r3, #4]\n+\tcmp\tr2, #1\n+\tit\teq\n+\tcmpeq\tr5, #1\n+\tadd.w\tr2, r4, #1\n+\tbne.n\ta2e <__gridxc_array_MOD_aa_3d_1d_sp+0x12a>\n+\tstr\tr2, [sp, #8]\n+\tmov.w\tlr, fp, lsl #2\n \tldr\tr2, [sp, #16]\n-\tadd.w\tr3, sl, ip\n-\tcbz\tr2, c88 <__gridxc_array_MOD_aa_3d_1d_sp+0x1a4>\n+\tmov\tr5, ip\n+\tldr\tr4, [sp, #36]\t@ 0x24\n+\tmov\tr9, r1\n+\tstrd\tr7, r6, [sp, #32]\n+\tadds\tr4, #4\n+\tstr\tr4, [sp, #12]\n+\tmul.w\tr4, fp, r3\n+\tmla\tr4, r2, r1, r4\n \tldr\tr2, [sp, #20]\n-\tadd.w\tfp, r1, r2\n-\tsubs\tr3, #1\n-\tadd.w\tfp, r9, fp, lsl #2\n-\tlsls\tr3, r3, #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, r8, r3\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tadd.w\tfp, r2, #1\n-\tcmp\tr4, fp\n-\tblt.n\tc88 <__gridxc_array_MOD_aa_3d_1d_sp+0x1a4>\n-\tadd\tfp, r1\n-\tadds\tr2, #2\n-\tcmp\tr4, r2\n-\tadd.w\tfp, r9, fp, lsl #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, r3, #4\n-\tadd\tfp, r8\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tblt.n\tc88 <__gridxc_array_MOD_aa_3d_1d_sp+0x1a4>\n-\tadd\tr2, r1\n-\tadds\tr3, #8\n-\tadd\tr3, r8\n-\tadd.w\tr2, r9, r2, lsl #2\n-\tvldr\ts15, [r3]\n-\tvldr\ts14, [r2]\n+\tadd.w\tfp, r4, r8\n+\tadd.w\tsl, r2, #1\n+\tldr\tr2, [sp, #20]\n+\tcmp\tr3, r2\n+\tbgt.n\t9fc <__gridxc_array_MOD_aa_3d_1d_sp+0xf8>\n+\tldr\tr2, [sp, #28]\n+\tmov\tr6, r3\n+\tstr\tr3, [sp, #4]\n+\tldr\tr7, [r2, #0]\n+\tldr\tr2, [sp, #24]\n+\tadd.w\tr4, r7, fp\n+\tadd.w\tr8, r7, #1\n+\tldr\tr1, [r2, #0]\n+\tldr\tr2, [sp, #12]\n+\tsub.w\tip, r1, r7\n+\tsub.w\tr8, r8, r1\n+\tmov.w\tip, ip, lsl #2\n+\tadd.w\tr4, r2, r4, lsl #2\n+\tsub.w\tip, ip, #4\n+\tcmp\tr7, r1\n+\tittt\tge\n+\taddge.w\tr3, r0, #4294967295\t@ 0xffffffff\n+\taddge.w\tr2, ip, r4\n+\taddge.w\tr3, r5, r3, lsl #2\n+\tblt.n\t9f2 <__gridxc_array_MOD_aa_3d_1d_sp+0xee>\n+\tvldr\ts14, [r3]\n+\tvldmia\tr2!, {s15}\n \tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [r3]\n-\tadd\tsl, r6\n+\tcmp\tr2, r4\n+\tvstmia\tr3!, {s15}\n+\tbne.n\t9dc <__gridxc_array_MOD_aa_3d_1d_sp+0xd8>\n+\tadd\tr0, r8\n+\tadds\tr6, #1\n+\tadd\tr4, lr\n+\tcmp\tr6, sl\n+\tbne.n\t9ca <__gridxc_array_MOD_aa_3d_1d_sp+0xc6>\n \tldr\tr3, [sp, #4]\n-\tadds\tr0, #1\n-\tadd\tr1, lr\n-\tcmp\tr0, r3\n-\tbne.n\tbe4 <__gridxc_array_MOD_aa_3d_1d_sp+0x100>\n-\tldrd\tr2, fp, [sp, #36]\t@ 0x24\n-\tadds\tr2, #1\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #28]\n-\tadd\tfp, r1\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #24]\n-\tadd\tr3, r1\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tcmp\tr2, r3\n-\tbne.w\tb9e <__gridxc_array_MOD_aa_3d_1d_sp+0xba>\n-\tldrd\tip, r7, [sp, #72]\t@ 0x48\n-\tldr.w\tr3, [ip]\n-\tcmp\tr3, sl\n-\tblt.n\tcda <__gridxc_array_MOD_aa_3d_1d_sp+0x1f6>\n-\tldr\tr3, [pc, #212]\t@ (d98 <__gridxc_array_MOD_aa_3d_1d_sp+0x2b4>)\n+\tldr\tr2, [sp, #16]\n+\tadd.w\tr9, r9, #1\n+\tadd\tfp, r2\n+\tldr\tr2, [sp, #8]\n+\tcmp\tr9, r2\n+\tbne.n\t99a <__gridxc_array_MOD_aa_3d_1d_sp+0x96>\n+\tldrd\tr7, r6, [sp, #32]\n+\tldr\tr3, [r7, #0]\n+\tcmp\tr3, r0\n+\tblt.n\ta28 <__gridxc_array_MOD_aa_3d_1d_sp+0x124>\n+\tldr\tr3, [pc, #204]\t@ (ae4 <__gridxc_array_MOD_aa_3d_1d_sp+0x1e0>)\n \tmovs\tr1, #19\n-\tldr\tr0, [pc, #212]\t@ (d9c <__gridxc_array_MOD_aa_3d_1d_sp+0x2b8>)\n+\tldr\tr0, [pc, #204]\t@ (ae8 <__gridxc_array_MOD_aa_3d_1d_sp+0x1e4>)\n \tadd\tr0, pc\n-\tldr\tr3, [r7, r3]\n+\tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #84\t@ 0x54\n+\tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr2, r5\n-\tmov\tr3, sl\n-\tb.n\tc24 <__gridxc_array_MOD_aa_3d_1d_sp+0x140>\n-\tadd\tsp, #84\t@ 0x54\n+\tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr0, [sp, #0]\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #20]\n-\tmov\tr2, r5\n-\tlsls\tr4, r1, #2\n-\tstrd\tr1, r9, [sp, #24]\n-\tmov.w\tr5, fp, lsl #2\n-\tmov\tr1, r3\n-\tmul.w\tr2, r0, r2\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tstrd\tip, r7, [sp, #36]\t@ 0x24\n-\tmla\tr2, r0, r3, r2\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tadd\tr2, lr\n-\tadds\tr0, #1\n-\tmov\tr3, r2\n-\tstr\tr0, [sp, #4]\n-\tldr\tr6, [sp, #32]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tcmp\tr6, r2\n-\tbgt.n\td80 <__gridxc_array_MOD_aa_3d_1d_sp+0x29c>\n-\tldr\tr2, [sp, #52]\t@ 0x34\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tmul.w\tr4, fp, r3\n+\tldr\tr2, [sp, #16]\n+\tmov.w\tlr, r5, lsl #2\n+\tldr\tr5, [sp, #20]\n+\tmov\tsl, ip\n+\tstrd\tr7, r6, [sp, #56]\t@ 0x38\n+\tadds\tr5, #1\n+\tstr\tr5, [sp, #4]\n+\tmla\tr4, r2, r1, r4\n+\tadd.w\tr2, r8, r4\n+\tldr\tr4, [sp, #8]\n+\tmov\tr5, r2\n+\tmov\tr2, r3\n+\tmov\tr3, r5\n+\tlsls\tr4, r4, #2\n+\tldr\tr5, [sp, #20]\n+\tcmp\tr2, r5\n+\tbgt.n\tace <__gridxc_array_MOD_aa_3d_1d_sp+0x1ca>\n+\tldr\tr5, [sp, #24]\n \tmov\tr7, r3\n-\tstrd\tr1, r3, [sp, #12]\n-\tldr.w\tip, [r2]\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tldr.w\tlr, [r2]\n-\tadd.w\tr0, lr, #1\n-\tsub.w\tr2, r0, ip\n-\tstr\tr2, [sp, #8]\n-\tldr\tr2, [sp, #24]\n-\tmul.w\tr9, r2, ip\n-\tldr\tr2, [sp, #28]\n-\tadd.w\tr9, r2, r9, lsl #2\n-\tcmp\tip, lr\n-\tbgt.n\td70 <__gridxc_array_MOD_aa_3d_1d_sp+0x28c>\n-\tadd.w\tr3, sl, #4294967295\t@ 0xffffffff\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tldr.w\tip, [r5]\n+\tldr\tr5, [sp, #28]\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr.w\tr8, [r5]\n+\tadd.w\tr5, r8, #1\n+\tsub.w\tr6, r5, ip\n+\tstr\tr6, [sp, #12]\n+\tldr\tr6, [sp, #32]\n+\tmul.w\tr9, r6, ip\n+\tldr\tr6, [sp, #36]\t@ 0x24\n+\tadd.w\tr9, r6, r9, lsl #2\n+\tmov\tr6, r2\n+\tcmp\tip, r8\n+\tbgt.n\tabe <__gridxc_array_MOD_aa_3d_1d_sp+0x1ba>\n+\tldr\tr2, [sp, #8]\n+\tsubs\tr3, r0, #1\n \tadd.w\tr1, r9, r7, lsl #2\n+\tmul.w\tr3, r2, r3\n \tmov\tr2, ip\n-\tmul.w\tr3, fp, r3\n-\tadd.w\tr3, r8, r3, lsl #2\n+\tadd.w\tr3, sl, r3, lsl #2\n \tvldr\ts15, [r3]\n \tadds\tr2, #1\n \tvldr\ts14, [r1]\n-\tcmp\tr2, r0\n-\tadd\tr1, r4\n+\tcmp\tr2, r5\n+\tadd\tr1, lr\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r3]\n-\tadd\tr3, r5\n-\tbne.n\td52 <__gridxc_array_MOD_aa_3d_1d_sp+0x26e>\n-\tldr\tr3, [sp, #8]\n-\tadd\tsl, r3\n-\tldr\tr3, [sp, #0]\n-\tadds\tr6, #1\n-\tadd\tr7, r3\n+\tadd\tr3, r4\n+\tbne.n\taa0 <__gridxc_array_MOD_aa_3d_1d_sp+0x19c>\n+\tldr\tr3, [sp, #12]\n+\tadd\tr0, r3\n \tldr\tr3, [sp, #4]\n+\tadds\tr6, #1\n+\tadd\tr7, fp\n \tcmp\tr6, r3\n-\tbne.n\td3c <__gridxc_array_MOD_aa_3d_1d_sp+0x258>\n-\tldrd\tr1, r3, [sp, #12]\n+\tbne.n\ta8a <__gridxc_array_MOD_aa_3d_1d_sp+0x186>\n+\tldrd\tr1, r2, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr5, [sp, #16]\n \tadds\tr1, #1\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #20]\n-\tcmp\tr1, r2\n-\tbne.n\td0c <__gridxc_array_MOD_aa_3d_1d_sp+0x228>\n-\tldrd\tip, r7, [sp, #36]\t@ 0x24\n-\tb.n\tcb8 <__gridxc_array_MOD_aa_3d_1d_sp+0x1d4>\n-\tnop\n-\t.word\t0x000002a4\n+\tadd\tr3, r5\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\tcmp\tr1, r5\n+\tbne.n\ta58 <__gridxc_array_MOD_aa_3d_1d_sp+0x154>\n+\tldrd\tr7, r6, [sp, #56]\t@ 0x38\n+\tb.n\ta0e <__gridxc_array_MOD_aa_3d_1d_sp+0x10a>\n+\t.word\t0x000001cc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000d2\n+\t.word\t0x000000ca\n R_ARM_REL32\t.LC4\n \n-00000da0 <__gridxc_array_MOD_aa_3d_1d_ip>:\n+00000aec <__gridxc_array_MOD_aa_3d_1d_ip>:\n __gridxc_array_MOD_aa_3d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov\tr5, r2\n-\tldr\tr2, [r2, #24]\n-\tsub\tsp, #92\t@ 0x5c\n-\tldr.w\tip, [pc, #656]\t@ 103c <__gridxc_array_MOD_aa_3d_1d_ip+0x29c>\n-\tadd\tip, pc\n-\tstrd\tr0, r1, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #132]\t@ 0x84\n-\tldr.w\tlr, [sp, #128]\t@ 0x80\n-\tldr\tr0, [r1, #24]\n-\tldr.w\tr8, [r1]\n-\tcmp\tr0, #0\n-\tit\teq\n-\tmoveq\tr0, #1\n-\tstr\tr0, [sp, #16]\n-\tnegs\tr0, r2\n-\tcbnz\tr2, dd2 <__gridxc_array_MOD_aa_3d_1d_ip+0x32>\n-\tmov.w\tr0, #4294967295\t@ 0xffffffff\n-\tmovs\tr2, #1\n-\tldr.w\tfp, [r3]\n-\tldr\tr3, [r5, #0]\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr6, [r5, #36]\t@ 0x24\n-\tldr\tr7, [r5, #48]\t@ 0x30\n-\tldr\tr3, [r3, #8]\n-\tsubs\tr5, r0, r6\n-\tldr\tr1, [r4, #8]\n-\tstr\tr6, [sp, #8]\n-\tsubs\tr6, r5, r7\n-\tcmp\tr3, r1\n-\tstr\tr7, [sp, #52]\t@ 0x34\n-\tbgt.w\tf58 <__gridxc_array_MOD_aa_3d_1d_ip+0x1b8>\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tldr\tr7, [r5, #4]\n-\tldr\tr5, [r4, #4]\n-\tstr\tr5, [sp, #56]\t@ 0x38\n-\tldr\tr5, [sp, #16]\n-\tstr\tr7, [sp, #36]\t@ 0x24\n+\tldr\tr6, [pc, #460]\t@ (cc0 <__gridxc_array_MOD_aa_3d_1d_ip+0x1d4>)\n+\tsub\tsp, #76\t@ 0x4c\n+\tadd\tr6, pc\n+\tstrd\tr0, r1, [sp, #32]\n+\tmov\tr1, r3\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr0, [r2, #24]\n+\tldr\tr7, [sp, #112]\t@ 0x70\n+\tldr\tr4, [r3, #24]\n+\tldr.w\tip, [r3]\n+\tcmp\tr4, #0\n+\tite\tne\n+\tmovne\tr3, r4\n+\tmoveq\tr3, #1\n+\tstr\tr3, [sp, #12]\n+\tnegs\tr3, r0\n+\tcbnz\tr0, b1e <__gridxc_array_MOD_aa_3d_1d_ip+0x32>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tmovs\tr0, #1\n+\tldr.w\tsl, [r5, #36]\t@ 0x24\n+\tldr.w\tfp, [r1]\n+\tldr\tr1, [r5, #48]\t@ 0x30\n+\tsub.w\tr3, r3, sl\n+\tldr\tr2, [r5, #0]\n+\tsubs\tr4, r3, r1\n+\tstr\tr1, [sp, #24]\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #32]\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tldr\tr3, [r1, #8]\n+\tldr\tr5, [r2, #8]\n+\tcmp\tr3, r5\n+\tbgt.n\tbec <__gridxc_array_MOD_aa_3d_1d_ip+0x100>\n+\tldr\tr2, [r2, #4]\n+\tstr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #12]\n+\tldr\tr1, [r1, #4]\n \tcmp\tr2, #1\n \tit\teq\n-\tcmpeq\tr5, #1\n-\tbne.w\tf82 <__gridxc_array_MOD_aa_3d_1d_ip+0x1e2>\n-\tadds\tr2, r1, #1\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tmov\tr4, r7\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr7, [sp, #8]\n-\tsubs\tr2, r3, #1\n-\tstrd\tlr, ip, [sp, #80]\t@ 0x50\n-\tadds\tr5, r1, r7\n-\tmul.w\tr2, r1, r2\n-\tmul.w\tr1, r3, r1\n-\tsubs\tr2, r2, r7\n-\tmla\tr7, r7, r4, r5\n-\tsubs\tr5, r1, r5\n-\tadd\tr1, r6\n-\tadd\tr2, r0\n-\tadd.w\tsl, r5, r0\n-\tmov.w\tr9, r1, lsl #2\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tldr\tr4, [sp, #4]\n-\tsubs\tr7, r7, r0\n-\tmov\tr5, sl\n-\tmov\tsl, r2\n-\tlsls\tr1, r1, #2\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tmov\tr2, r3\n-\tadds\tr0, r7, r6\n-\tstr\tr0, [sp, #76]\t@ 0x4c\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #12]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tcmp\tr3, r1\n-\tbgt.n\tf40 <__gridxc_array_MOD_aa_3d_1d_ip+0x1a0>\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tsub.w\tr3, r4, r9\n-\tstrd\tr2, r5, [sp, #40]\t@ 0x28\n-\tstr.w\tr9, [sp, #48]\t@ 0x30\n-\tldr\tr7, [r1, #0]\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tadd.w\tr0, r7, sl\n-\tstr\tr7, [sp, #4]\n-\tldr\tr6, [r1, #0]\n-\tadd.w\tr0, r3, r0, lsl #2\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tsub.w\tlr, r6, r7\n-\tstr\tr0, [sp, #24]\n-\tadd.w\tip, lr, #1\n-\tadds\tr1, r5, r1\n-\tbic.w\tr0, ip, #3\n-\tstr\tr0, [sp, #16]\n-\tmov.w\tr3, ip, lsr #2\n-\tldr\tr0, [sp, #36]\t@ 0x24\n-\tlsls\tr3, r3, #4\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #16]\n-\tadd\tr3, r7\n-\tstr\tr3, [sp, #32]\n-\tand.w\tr3, ip, #3\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #4]\n-\tcmp\tr6, r3\n-\tblt.n\tf2c <__gridxc_array_MOD_aa_3d_1d_ip+0x18c>\n-\tcmp.w\tlr, #2\n-\tbls.n\tf76 <__gridxc_array_MOD_aa_3d_1d_ip+0x1d6>\n-\tmov\tr7, r3\n-\tadd.w\tr3, fp, #1073741824\t@ 0x40000000\n+\tcmpeq\tr0, #1\n+\tadd.w\tr2, r5, #1\n+\tbne.n\tc0c <__gridxc_array_MOD_aa_3d_1d_ip+0x120>\n+\tstr\tr2, [sp, #16]\n+\tmul.w\tr0, sl, r1\n \tldr\tr2, [sp, #24]\n-\tsubs\tr3, #1\n-\tldr\tr5, [sp, #20]\n-\tadd.w\tr3, r8, r3, lsl #2\n-\tadd.w\tr2, r2, r1, lsl #2\n-\tadd\tr5, r3\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvadd.i32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tr5, r3\n-\tbne.n\tec4 <__gridxc_array_MOD_aa_3d_1d_ip+0x124>\n+\tmov.w\tlr, sl, lsl #2\n+\tstr.w\tip, [sp, #4]\n+\tstr\tr7, [sp, #20]\n+\tstr\tr6, [sp, #44]\t@ 0x2c\n+\tmla\tr0, r2, r3, r0\n \tldr\tr2, [sp, #28]\n-\tldr\tr3, [sp, #16]\n-\tstr\tr7, [sp, #4]\n-\tadd\tr3, fp\n-\tcbz\tr2, f2a <__gridxc_array_MOD_aa_3d_1d_ip+0x18a>\n+\tadd\tr4, r0\n+\tadd.w\tsl, r2, #1\n+\tmov\tr2, r4\n+\tmov\tr4, r3\n+\tmov\tr3, r2\n+\tldr\tr2, [sp, #28]\n+\tcmp\tr1, r2\n+\tbgt.n\tbdc <__gridxc_array_MOD_aa_3d_1d_ip+0xf0>\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tmov\tr6, r1\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tstrd\tr1, r4, [sp, #8]\n+\tldr\tr7, [r2, #0]\n \tldr\tr2, [sp, #32]\n-\tsubs\tr3, #1\n-\tadds\tr5, r1, r2\n-\tldr.w\tr7, [r8, r3, lsl #2]\n-\tldr.w\tr5, [r4, r5, lsl #2]\n-\tadd\tr5, r7\n-\tstr.w\tr5, [r8, r3, lsl #2]\n-\tadds\tr5, r2, #1\n-\tlsls\tr3, r3, #2\n-\tcmp\tr6, r5\n-\tblt.n\tf2a <__gridxc_array_MOD_aa_3d_1d_ip+0x18a>\n-\tadd.w\tr9, r3, #4\n-\tadd\tr5, r1\n-\tadds\tr2, #2\n-\tcmp\tr6, r2\n-\tldr.w\tr7, [r8, r9]\n-\tldr.w\tr5, [r4, r5, lsl #2]\n-\tadd\tr5, r7\n-\tstr.w\tr5, [r8, r9]\n-\tblt.n\tf2a <__gridxc_array_MOD_aa_3d_1d_ip+0x18a>\n-\tadds\tr3, #8\n-\tadd\tr2, r1\n-\tldr.w\tr5, [r4, r2, lsl #2]\n-\tldr.w\tr2, [r8, r3]\n-\tadd\tr2, r5\n-\tstr.w\tr2, [r8, r3]\n-\tadd\tfp, ip\n-\tldr\tr3, [sp, #8]\n-\tadds\tr0, #1\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #12]\n-\tcmp\tr0, r3\n-\tbne.n\tea2 <__gridxc_array_MOD_aa_3d_1d_ip+0x102>\n-\tldrd\tr2, r5, [sp, #40]\t@ 0x28\n-\tldr.w\tr9, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tadds\tr2, #1\n-\tadd\tr5, r3\n-\tadd\tsl, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tadd\tr9, r3\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tcmp\tr2, r3\n-\tbne.w\te52 <__gridxc_array_MOD_aa_3d_1d_ip+0xb2>\n-\tldrd\tlr, ip, [sp, #80]\t@ 0x50\n-\tldr.w\tr3, [lr]\n+\tadds\tr5, r7, r3\n+\tadd.w\tr8, r7, #1\n+\tldr\tr2, [r2, #0]\n+\tadd.w\tr5, r0, r5, lsl #2\n+\tsub.w\tip, r2, r7\n+\tsub.w\tr8, r8, r2\n+\tmov.w\tip, ip, lsl #2\n+\tsub.w\tip, ip, #4\n+\tcmp\tr7, r2\n+\tblt.n\tbd0 <__gridxc_array_MOD_aa_3d_1d_ip+0xe4>\n+\tldr\tr1, [sp, #4]\n+\tadd.w\tr0, ip, r5\n+\tmov\tr9, r3\n+\tadd.w\tr1, r1, fp, lsl #2\n+\tsubs\tr1, #8\n+\tldr.w\tr4, [r1, #4]!\n+\tldr.w\tr3, [r0, #4]!\n+\tadd\tr4, r3\n+\tcmp\tr0, r5\n+\tstr\tr4, [r1, #0]\n+\tbne.n\tbbc <__gridxc_array_MOD_aa_3d_1d_ip+0xd0>\n+\tmov\tr3, r9\n+\tadd\tfp, r8\n+\tadds\tr6, #1\n+\tadd\tr5, lr\n+\tcmp\tr6, sl\n+\tbne.n\tbaa <__gridxc_array_MOD_aa_3d_1d_ip+0xbe>\n+\tldrd\tr1, r4, [sp, #8]\n+\tadds\tr4, #1\n+\tldr\tr2, [sp, #24]\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #16]\n+\tcmp\tr4, r2\n+\tbne.n\tb7a <__gridxc_array_MOD_aa_3d_1d_ip+0x8e>\n+\tldr\tr7, [sp, #20]\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #0]\n \tcmp\tr3, fp\n-\tblt.n\tf7c <__gridxc_array_MOD_aa_3d_1d_ip+0x1dc>\n-\tldr\tr3, [pc, #220]\t@ (1040 <__gridxc_array_MOD_aa_3d_1d_ip+0x2a0>)\n+\tblt.n\tc06 <__gridxc_array_MOD_aa_3d_1d_ip+0x11a>\n+\tldr\tr3, [pc, #208]\t@ (cc4 <__gridxc_array_MOD_aa_3d_1d_ip+0x1d8>)\n \tmovs\tr1, #22\n-\tldr\tr0, [pc, #220]\t@ (1044 <__gridxc_array_MOD_aa_3d_1d_ip+0x2a4>)\n+\tldr\tr0, [pc, #208]\t@ (cc8 <__gridxc_array_MOD_aa_3d_1d_ip+0x1dc>)\n \tadd\tr0, pc\n-\tldr.w\tr3, [ip, r3]\n+\tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #92\t@ 0x5c\n+\tadd\tsp, #76\t@ 0x4c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr2, r3\n-\tmov\tr3, fp\n-\tb.n\tee4 <__gridxc_array_MOD_aa_3d_1d_ip+0x144>\n-\tadd\tsp, #92\t@ 0x5c\n+\tadd\tsp, #76\t@ 0x4c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr0, [sp, #8]\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tmov\tr1, r7\n-\tldr\tr4, [sp, #4]\n-\tlsls\tr7, r5, #2\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tmul.w\tr1, r0, r1\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tstr.w\tlr, [sp, #48]\t@ 0x30\n-\tstr.w\tip, [sp, #68]\t@ 0x44\n-\tmla\tr1, r0, r3, r1\n-\tadds\tr0, r1, r6\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tlsls\tr6, r2, #2\n-\tmov\tr2, r8\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #12]\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tldr\tr5, [sp, #56]\t@ 0x38\n-\tcmp\tr1, r5\n-\tbgt.n\t1026 <__gridxc_array_MOD_aa_3d_1d_ip+0x286>\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tmul.w\tr5, sl, r1\n+\tldr\tr2, [sp, #24]\n+\tmov.w\tlr, r0, lsl #2\n+\tstr\tr0, [sp, #60]\t@ 0x3c\n+\tmov\tr0, r1\n+\tstr.w\tip, [sp, #20]\n+\tstrd\tr7, r6, [sp, #64]\t@ 0x40\n+\tmla\tr5, r2, r3, r5\n+\tldr\tr2, [sp, #12]\n+\tadd\tr5, r4\n+\tlsls\tr4, r2, #2\n+\tldr\tr2, [sp, #28]\n+\tmov\tr1, r5\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tmov\tr2, sl\n+\tldr\tr5, [sp, #28]\n+\tcmp\tr0, r5\n+\tbgt.n\tcae <__gridxc_array_MOD_aa_3d_1d_ip+0x1c2>\n+\tldr\tr5, [sp, #32]\n \tmov\tip, r1\n-\tmov\tlr, r0\n-\tstrd\tr4, r3, [sp, #24]\n-\tstr\tr0, [sp, #32]\n+\tmov\tr7, r0\n+\tstrd\tr0, r3, [sp, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #52]\t@ 0x34\n \tldr.w\tr8, [r5]\n-\tldr\tr5, [sp, #64]\t@ 0x40\n+\tldr\tr5, [sp, #36]\t@ 0x24\n \tldr.w\tr9, [r5]\n-\tadd.w\tr5, r9, #1\n-\tsub.w\tr1, r5, r8\n-\tstr\tr1, [sp, #20]\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tmul.w\tsl, r1, r8\n-\tadd.w\tsl, r4, sl, lsl #2\n+\tadd.w\tr6, r9, #1\n+\tsub.w\tr5, r6, r8\n+\tstr\tr5, [sp, #16]\n+\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tmul.w\tsl, r5, r8\n+\tldr\tr5, [sp, #40]\t@ 0x28\n+\tadd.w\tsl, r5, sl, lsl #2\n \tcmp\tr8, r9\n-\tbgt.n\t1012 <__gridxc_array_MOD_aa_3d_1d_ip+0x272>\n-\tldr\tr1, [sp, #16]\n+\tbgt.n\tc9e <__gridxc_array_MOD_aa_3d_1d_ip+0x1b2>\n+\tldr\tr1, [sp, #12]\n \tadd.w\tr3, fp, #4294967295\t@ 0xffffffff\n-\tadd.w\tr4, sl, lr, lsl #2\n+\tadd.w\tr5, sl, ip, lsl #2\n \tmov\tr0, r8\n \tstr\tr2, [sp, #4]\n \tmul.w\tr3, r1, r3\n-\tadd.w\tr3, r2, r3, lsl #2\n+\tldr\tr1, [sp, #20]\n+\tadd.w\tr3, r1, r3, lsl #2\n \tldr\tr2, [r3, #0]\n \tadds\tr0, #1\n-\tldr\tr1, [r4, #0]\n-\tcmp\tr0, r5\n-\tadd\tr4, r6\n+\tldr\tr1, [r5, #0]\n+\tcmp\tr0, r6\n+\tadd\tr5, lr\n \tadd\tr2, r1\n \tstr\tr2, [r3, #0]\n-\tadd\tr3, r7\n-\tbne.n\tffa <__gridxc_array_MOD_aa_3d_1d_ip+0x25a>\n-\tldr\tr3, [sp, #20]\n+\tadd\tr3, r4\n+\tbne.n\tc86 <__gridxc_array_MOD_aa_3d_1d_ip+0x19a>\n+\tldr\tr3, [sp, #16]\n \tldr\tr2, [sp, #4]\n \tadd\tfp, r3\n \tldr\tr3, [sp, #8]\n-\tadd.w\tip, ip, #1\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #12]\n-\tcmp\tip, r3\n-\tbne.n\tfe0 <__gridxc_array_MOD_aa_3d_1d_ip+0x240>\n-\tldrd\tr4, r3, [sp, #24]\n-\tldr\tr0, [sp, #32]\n+\tadds\tr7, #1\n+\tadd\tip, r2\n+\tcmp\tr7, r3\n+\tbne.n\tc6a <__gridxc_array_MOD_aa_3d_1d_ip+0x17e>\n+\tldrd\tr0, r3, [sp, #44]\t@ 0x2c\n \tldr\tr1, [sp, #52]\t@ 0x34\n+\tldr\tr5, [sp, #24]\n \tadds\tr3, #1\n-\tadd\tr0, r1\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tcmp\tr3, r1\n-\tbne.n\tfae <__gridxc_array_MOD_aa_3d_1d_ip+0x20e>\n-\tldr.w\tlr, [sp, #48]\t@ 0x30\n-\tldr.w\tip, [sp, #68]\t@ 0x44\n-\tb.n\tf58 <__gridxc_array_MOD_aa_3d_1d_ip+0x1b8>\n-\t.word\t0x0000028a\n+\tadd\tr1, r5\n+\tldr\tr5, [sp, #56]\t@ 0x38\n+\tcmp\tr3, r5\n+\tbne.n\tc38 <__gridxc_array_MOD_aa_3d_1d_ip+0x14c>\n+\tldrd\tr7, r6, [sp, #64]\t@ 0x40\n+\tb.n\tbec <__gridxc_array_MOD_aa_3d_1d_ip+0x100>\n+\t.word\t0x000001c6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000da\n+\t.word\t0x000000cc\n R_ARM_REL32\t.LC5\n \n-00001048 <__gridxc_array_MOD_aa_2d_1d_dp>:\n+00000ccc <__gridxc_array_MOD_aa_2d_1d_dp>:\n __gridxc_array_MOD_aa_2d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov\tr5, r2\n \tmov\tlr, r1\n \tsub\tsp, #28\n \tmov\tr7, r0\n \tldr\tr1, [r5, #24]\n \tmov\tr0, r3\n-\tldr\tr3, [pc, #300]\t@ (1188 <__gridxc_array_MOD_aa_2d_1d_dp+0x140>)\n+\tldr\tr3, [pc, #300]\t@ (e0c <__gridxc_array_MOD_aa_2d_1d_dp+0x140>)\n \tldr\tr4, [sp, #68]\t@ 0x44\n \trsb\tr9, r1, #0\n \tadd\tr3, pc\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr.w\tfp, [r4, #24]\n \tldr.w\tsl, [r4]\n-\tmovs\tr4, #1\n \tcmp.w\tfp, #0\n \tit\teq\n-\tmoveq\tfp, r4\n-\tcbnz\tr1, 107e <__gridxc_array_MOD_aa_2d_1d_dp+0x36>\n+\tmoveq.w\tfp, #1\n+\tcbnz\tr1, d02 <__gridxc_array_MOD_aa_2d_1d_dp+0x36>\n \tmov.w\tr9, #4294967295\t@ 0xffffffff\n \tmovs\tr1, #1\n \tldr\tr4, [r0, #0]\n \tldr\tr0, [r5, #0]\n \tldr\tr6, [r5, #36]\t@ 0x24\n \tldr.w\tip, [lr, #4]\n \tstr\tr0, [sp, #4]\n \tsub.w\tr9, r9, r6\n \tldr\tr0, [r7, #4]\n \tcmp\tr0, ip\n-\tbgt.n\t10f8 <__gridxc_array_MOD_aa_2d_1d_dp+0xb0>\n-\tmov\tr5, fp\n+\tbgt.n\td7c <__gridxc_array_MOD_aa_2d_1d_dp+0xb0>\n \tldr\tr7, [r7, #0]\n-\tldr.w\tr8, [lr]\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr5, #1\n-\tbne.n\t1118 <__gridxc_array_MOD_aa_2d_1d_dp+0xd0>\n+\tcmpeq\tr1, #1\n+\tldr.w\tr8, [lr]\n+\tbne.n\td9c <__gridxc_array_MOD_aa_2d_1d_dp+0xd0>\n \tmla\tr1, r6, r0, r8\n \tldr\tr5, [sp, #4]\n \tsub.w\tlr, r7, r8\n \tadd.w\tip, ip, #1\n \tadd\tr1, r9\n \tadds\tr5, #8\n \tmov.w\tlr, lr, lsl #3\n \tadd.w\tr9, r8, #1\n \tadd.w\tr5, r5, r1, lsl #3\n \tlsls\tr6, r6, #3\n \tsub.w\tlr, lr, #8\n \tsub.w\tr9, r9, r7\n \tcmp\tr7, r8\n-\tbgt.n\t10f0 <__gridxc_array_MOD_aa_2d_1d_dp+0xa8>\n+\tbgt.n\td74 <__gridxc_array_MOD_aa_2d_1d_dp+0xa8>\n \tsubs\tr1, r4, #1\n \tadd.w\tfp, lr, r5\n \tadd.w\tr1, sl, r1, lsl #3\n-\tvldr\td17, [r1]\n-\tvldmia\tfp!, {d16}\n-\tvadd.f64\td16, d16, d17\n+\tvldr\td6, [r1]\n+\tvldmia\tfp!, {d7}\n+\tvadd.f64\td7, d7, d6\n \tcmp\tfp, r5\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t10da <__gridxc_array_MOD_aa_2d_1d_dp+0x92>\n+\tvstmia\tr1!, {d7}\n+\tbne.n\td5e <__gridxc_array_MOD_aa_2d_1d_dp+0x92>\n \tadd\tr4, r9\n \tadds\tr0, #1\n \tadd\tr5, r6\n \tcmp\tr0, ip\n-\tbne.n\t10cc <__gridxc_array_MOD_aa_2d_1d_dp+0x84>\n+\tbne.n\td50 <__gridxc_array_MOD_aa_2d_1d_dp+0x84>\n \tldr\tr2, [r2, #0]\n \tcmp\tr2, r4\n-\tblt.n\t1112 <__gridxc_array_MOD_aa_2d_1d_dp+0xca>\n-\tldr\tr2, [pc, #140]\t@ (118c <__gridxc_array_MOD_aa_2d_1d_dp+0x144>)\n+\tblt.n\td96 <__gridxc_array_MOD_aa_2d_1d_dp+0xca>\n+\tldr\tr2, [pc, #140]\t@ (e10 <__gridxc_array_MOD_aa_2d_1d_dp+0x144>)\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #140]\t@ (1190 <__gridxc_array_MOD_aa_2d_1d_dp+0x148>)\n+\tldr\tr0, [pc, #140]\t@ (e14 <__gridxc_array_MOD_aa_2d_1d_dp+0x148>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n@@ -1749,434 +1413,318 @@\n \tadd.w\tr5, r5, ip, lsl #3\n \tstr\tr5, [sp, #4]\n \tmov.w\tr5, fp, lsl #3\n \tmov.w\tip, r1, lsl #3\n \tsub.w\tr1, lr, r7\n \tstrd\tr1, r2, [sp, #12]\n \tcmp\tr7, r8\n-\tbgt.n\t1178 <__gridxc_array_MOD_aa_2d_1d_dp+0x130>\n+\tbgt.n\tdfc <__gridxc_array_MOD_aa_2d_1d_dp+0x130>\n \tsubs\tr3, r4, #1\n \tldr\tr2, [sp, #4]\n \tmul.w\tr3, fp, r3\n \tadd.w\tr1, r2, r9, lsl #3\n \tmov\tr2, r7\n \tadd.w\tr3, sl, r3, lsl #3\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tvldr\td17, [r1]\n+\tvldr\td6, [r1]\n \tcmp\tr2, lr\n \tadd\tr1, ip\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r5\n-\tbne.n\t115a <__gridxc_array_MOD_aa_2d_1d_dp+0x112>\n+\tbne.n\tdde <__gridxc_array_MOD_aa_2d_1d_dp+0x112>\n \tldr\tr3, [sp, #12]\n \tadd\tr4, r3\n \tldr\tr3, [sp, #8]\n \tadds\tr0, #1\n \tadd\tr9, r6\n \tcmp\tr0, r3\n-\tbne.n\t1144 <__gridxc_array_MOD_aa_2d_1d_dp+0xfc>\n+\tbne.n\tdc8 <__gridxc_array_MOD_aa_2d_1d_dp+0xfc>\n \tldrd\tr2, r3, [sp, #16]\n-\tb.n\t10f8 <__gridxc_array_MOD_aa_2d_1d_dp+0xb0>\n+\tb.n\td7c <__gridxc_array_MOD_aa_2d_1d_dp+0xb0>\n \t.word\t0x00000124\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000088\n R_ARM_REL32\t.LC6\n \n-00001194 <__gridxc_array_MOD_aa_2d_1d_sp>:\n+00000e18 <__gridxc_array_MOD_aa_2d_1d_sp>:\n __gridxc_array_MOD_aa_2d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tmov\tr4, r2\n-\tmov\tr6, r1\n-\tsub\tsp, #36\t@ 0x24\n-\tmov\tip, r0\n-\tldr\tr0, [pc, #460]\t@ (1370 <__gridxc_array_MOD_aa_2d_1d_sp+0x1dc>)\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tadd\tr0, pc\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tstr\tr2, [sp, #24]\n-\tldr\tr2, [r4, #24]\n-\tldr.w\tsl, [r1, #24]\n-\tldr\tr1, [r1, #0]\n-\trsb\tfp, r2, #0\n-\tcmp.w\tsl, #0\n-\tstr\tr1, [sp, #0]\n-\tmov.w\tr1, #1\n-\tstr\tr0, [sp, #28]\n+\tmov\tr5, r2\n+\tmov\tlr, r1\n+\tsub\tsp, #28\n+\tmov\tr7, r0\n+\tldr\tr1, [r5, #24]\n+\tmov\tr0, r3\n+\tldr\tr3, [pc, #300]\t@ (f58 <__gridxc_array_MOD_aa_2d_1d_sp+0x140>)\n+\tldr\tr4, [sp, #68]\t@ 0x44\n+\trsb\tr9, r1, #0\n+\tadd\tr3, pc\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tfp, [r4, #24]\n+\tldr.w\tsl, [r4]\n+\tcmp.w\tfp, #0\n \tit\teq\n-\tmoveq\tsl, r1\n-\tcbnz\tr2, 11ce <__gridxc_array_MOD_aa_2d_1d_sp+0x3a>\n-\tmov.w\tfp, #4294967295\t@ 0xffffffff\n-\tmovs\tr2, #1\n-\tldr.w\tr8, [r4, #36]\t@ 0x24\n-\tldr\tr7, [r4, #0]\n-\tldr\tr1, [r6, #4]\n-\tldr.w\tr4, [ip, #4]\n-\tldr\tr0, [r3, #0]\n-\tsub.w\tr3, fp, r8\n-\tcmp\tr4, r1\n-\tbgt.n\t12e0 <__gridxc_array_MOD_aa_2d_1d_sp+0x14c>\n-\tmov\tr5, sl\n-\tldr.w\tip, [ip]\n-\tldr\tr6, [r6, #0]\n-\tcmp\tr2, #1\n+\tmoveq.w\tfp, #1\n+\tcbnz\tr1, e4e <__gridxc_array_MOD_aa_2d_1d_sp+0x36>\n+\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tmovs\tr1, #1\n+\tldr\tr4, [r0, #0]\n+\tldr\tr0, [r5, #0]\n+\tldr\tr6, [r5, #36]\t@ 0x24\n+\tldr.w\tip, [lr, #4]\n+\tstr\tr0, [sp, #4]\n+\tsub.w\tr9, r9, r6\n+\tldr\tr0, [r7, #4]\n+\tcmp\tr0, ip\n+\tbgt.n\tec8 <__gridxc_array_MOD_aa_2d_1d_sp+0xb0>\n+\tldr\tr7, [r7, #0]\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr5, #1\n-\tbne.w\t130a <__gridxc_array_MOD_aa_2d_1d_sp+0x176>\n-\tsub.w\tr2, ip, r8\n-\tsub.w\tsl, r6, ip\n-\tadd\tr2, fp\n-\tadd.w\tr9, sl, #1\n-\tadd.w\tlr, r1, #1\n-\tmla\tr1, r8, r4, r3\n-\tadd.w\tr2, r7, r2, lsl #2\n-\tldr\tr5, [sp, #0]\n-\tsub.w\tr2, r2, r3, lsl #2\n-\tmov.w\tr3, r9, lsr #2\n-\tstr\tr2, [sp, #12]\n-\tlsls\tr3, r3, #4\n-\tstr\tr3, [sp, #4]\n-\tbic.w\tr3, r9, #3\n-\tstr\tr3, [sp, #8]\n-\tadd\tr3, ip\n-\tstr\tr3, [sp, #20]\n-\tand.w\tr3, r9, #3\n-\tstr\tr3, [sp, #16]\n-\tcmp\tip, r6\n-\tbgt.n\t12d8 <__gridxc_array_MOD_aa_2d_1d_sp+0x144>\n-\tcmp.w\tsl, #2\n-\tbls.n\t12fe <__gridxc_array_MOD_aa_2d_1d_sp+0x16a>\n-\tldr\tr2, [sp, #12]\n-\tadd.w\tr3, r0, #1073741824\t@ 0x40000000\n-\tsubs\tr3, #1\n-\tadd.w\tr2, r2, r1, lsl #2\n-\tstr\tr2, [sp, #0]\n-\tldr\tr2, [sp, #4]\n-\tadd.w\tr3, r5, r3, lsl #2\n-\tadd.w\tfp, r2, r3\n-\tldr\tr2, [sp, #0]\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvadd.f32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tfp, r3\n-\tbne.n\t1254 <__gridxc_array_MOD_aa_2d_1d_sp+0xc0>\n-\tldr\tr2, [sp, #16]\n-\tldr\tr3, [sp, #8]\n-\tadds\tr3, r0, r3\n-\tcbz\tr2, 12d6 <__gridxc_array_MOD_aa_2d_1d_sp+0x142>\n-\tldr\tr2, [sp, #20]\n-\tadd.w\tfp, r1, r2\n-\tsubs\tr3, #1\n-\tadd.w\tfp, r7, fp, lsl #2\n-\tlsls\tr3, r3, #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, r5, r3\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tadd.w\tfp, r2, #1\n-\tcmp\tr6, fp\n-\tblt.n\t12d6 <__gridxc_array_MOD_aa_2d_1d_sp+0x142>\n-\tadd\tfp, r1\n-\tadds\tr2, #2\n-\tcmp\tr6, r2\n-\tadd.w\tfp, r7, fp, lsl #2\n-\tvldr\ts14, [fp]\n-\tadd.w\tfp, r3, #4\n-\tadd\tfp, r5\n-\tvldr\ts15, [fp]\n-\tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [fp]\n-\tblt.n\t12d6 <__gridxc_array_MOD_aa_2d_1d_sp+0x142>\n-\tadd\tr2, r1\n-\tadds\tr3, #8\n-\tadd\tr3, r5\n-\tadd.w\tr2, r7, r2, lsl #2\n-\tvldr\ts15, [r3]\n-\tvldr\ts14, [r2]\n+\tcmpeq\tr1, #1\n+\tldr.w\tr8, [lr]\n+\tbne.n\tee8 <__gridxc_array_MOD_aa_2d_1d_sp+0xd0>\n+\tmla\tr1, r6, r0, r8\n+\tldr\tr5, [sp, #4]\n+\tsub.w\tlr, r7, r8\n+\tadd.w\tip, ip, #1\n+\tadd\tr1, r9\n+\tadds\tr5, #4\n+\tmov.w\tlr, lr, lsl #2\n+\tadd.w\tr9, r8, #1\n+\tadd.w\tr5, r5, r1, lsl #2\n+\tlsls\tr6, r6, #2\n+\tsub.w\tlr, lr, #4\n+\tsub.w\tr9, r9, r7\n+\tcmp\tr7, r8\n+\tbgt.n\tec0 <__gridxc_array_MOD_aa_2d_1d_sp+0xa8>\n+\tsubs\tr1, r4, #1\n+\tadd.w\tfp, lr, r5\n+\tadd.w\tr1, sl, r1, lsl #2\n+\tvldr\ts14, [r1]\n+\tvldmia\tfp!, {s15}\n \tvadd.f32\ts15, s15, s14\n-\tvstr\ts15, [r3]\n-\tadd\tr0, r9\n-\tadds\tr4, #1\n-\tadd\tr1, r8\n-\tcmp\tr4, lr\n-\tbne.n\t1230 <__gridxc_array_MOD_aa_2d_1d_sp+0x9c>\n-\tldr\tr3, [sp, #24]\n-\tldr\tr3, [r3, #0]\n-\tcmp\tr3, r0\n-\tblt.n\t1304 <__gridxc_array_MOD_aa_2d_1d_sp+0x170>\n-\tldr\tr3, [pc, #136]\t@ (1374 <__gridxc_array_MOD_aa_2d_1d_sp+0x1e0>)\n+\tcmp\tfp, r5\n+\tvstmia\tr1!, {s15}\n+\tbne.n\teaa <__gridxc_array_MOD_aa_2d_1d_sp+0x92>\n+\tadd\tr4, r9\n+\tadds\tr0, #1\n+\tadd\tr5, r6\n+\tcmp\tr0, ip\n+\tbne.n\te9c <__gridxc_array_MOD_aa_2d_1d_sp+0x84>\n+\tldr\tr2, [r2, #0]\n+\tcmp\tr2, r4\n+\tblt.n\tee2 <__gridxc_array_MOD_aa_2d_1d_sp+0xca>\n+\tldr\tr2, [pc, #140]\t@ (f5c <__gridxc_array_MOD_aa_2d_1d_sp+0x144>)\n \tmovs\tr1, #19\n-\tldr\tr2, [sp, #28]\n-\tldr\tr0, [pc, #136]\t@ (1378 <__gridxc_array_MOD_aa_2d_1d_sp+0x1e4>)\n-\tldr\tr3, [r2, r3]\n+\tldr\tr0, [pc, #140]\t@ (f60 <__gridxc_array_MOD_aa_2d_1d_sp+0x148>)\n \tadd\tr0, pc\n+\tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #36\t@ 0x24\n+\tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr2, ip\n-\tmov\tr3, r0\n-\tb.n\t1272 <__gridxc_array_MOD_aa_2d_1d_sp+0xde>\n-\tadd\tsp, #36\t@ 0x24\n+\tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tmla\tr9, r8, r4, r3\n-\tadds\tr3, r1, #1\n-\tstr\tr3, [sp, #4]\n-\tmul.w\tr3, ip, r2\n-\tldr\tr5, [sp, #0]\n-\tadd.w\tlr, r6, #1\n-\tmov.w\tfp, sl, lsl #2\n-\tadd.w\tr3, r7, r3, lsl #2\n-\tlsls\tr7, r2, #2\n-\tstr\tr3, [sp, #8]\n-\tsub.w\tr3, lr, ip\n-\tstr\tr3, [sp, #12]\n-\tcmp\tip, r6\n-\tbgt.n\t1362 <__gridxc_array_MOD_aa_2d_1d_sp+0x1ce>\n-\tsubs\tr3, r0, #1\n-\tldr\tr2, [sp, #8]\n-\tmul.w\tr3, sl, r3\n+\tadd.w\tr5, ip, #1\n+\tmul.w\tip, r1, r7\n+\tstr\tr5, [sp, #8]\n+\tmla\tr9, r6, r0, r9\n+\tldr\tr5, [sp, #4]\n+\tadd.w\tlr, r8, #1\n+\tstr\tr3, [sp, #20]\n+\tadd.w\tr5, r5, ip, lsl #2\n+\tstr\tr5, [sp, #4]\n+\tmov.w\tr5, fp, lsl #2\n+\tmov.w\tip, r1, lsl #2\n+\tsub.w\tr1, lr, r7\n+\tstrd\tr1, r2, [sp, #12]\n+\tcmp\tr7, r8\n+\tbgt.n\tf48 <__gridxc_array_MOD_aa_2d_1d_sp+0x130>\n+\tsubs\tr3, r4, #1\n+\tldr\tr2, [sp, #4]\n+\tmul.w\tr3, fp, r3\n \tadd.w\tr1, r2, r9, lsl #2\n-\tmov\tr2, ip\n-\tadd.w\tr3, r5, r3, lsl #2\n+\tmov\tr2, r7\n+\tadd.w\tr3, sl, r3, lsl #2\n \tvldr\ts15, [r3]\n \tadds\tr2, #1\n \tvldr\ts14, [r1]\n \tcmp\tr2, lr\n-\tadd\tr1, r7\n+\tadd\tr1, ip\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r3]\n-\tadd\tr3, fp\n-\tbne.n\t1344 <__gridxc_array_MOD_aa_2d_1d_sp+0x1b0>\n+\tadd\tr3, r5\n+\tbne.n\tf2a <__gridxc_array_MOD_aa_2d_1d_sp+0x112>\n \tldr\tr3, [sp, #12]\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr4, #1\n-\tadd\tr9, r8\n-\tcmp\tr4, r3\n-\tbne.n\t132e <__gridxc_array_MOD_aa_2d_1d_sp+0x19a>\n-\tb.n\t12e0 <__gridxc_array_MOD_aa_2d_1d_sp+0x14c>\n-\tnop\n-\t.word\t0x000001c8\n+\tadd\tr4, r3\n+\tldr\tr3, [sp, #8]\n+\tadds\tr0, #1\n+\tadd\tr9, r6\n+\tcmp\tr0, r3\n+\tbne.n\tf14 <__gridxc_array_MOD_aa_2d_1d_sp+0xfc>\n+\tldrd\tr2, r3, [sp, #16]\n+\tb.n\tec8 <__gridxc_array_MOD_aa_2d_1d_sp+0xb0>\n+\t.word\t0x00000124\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000082\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC7\n \n-0000137c <__gridxc_array_MOD_aa_2d_1d_ip>:\n+00000f64 <__gridxc_array_MOD_aa_2d_1d_ip>:\n __gridxc_array_MOD_aa_2d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tmov\tr6, r2\n-\tmov\tlr, r0\n-\tsub\tsp, #44\t@ 0x2c\n-\tmov\tr7, r1\n-\tldr\tr1, [r6, #24]\n-\tmov\tr2, r3\n-\tldr\tr4, [pc, #436]\t@ (1544 <__gridxc_array_MOD_aa_2d_1d_ip+0x1c8>)\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\trsb\tr9, r1, #0\n-\tadd\tr4, pc\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tldr.w\tsl, [r0, #24]\n-\tldr\tr0, [r0, #0]\n+\tmov\tlr, r1\n+\tldr\tr6, [r2, #24]\n+\tsub\tsp, #36\t@ 0x24\n+\tmov\tr1, r3\n+\tldr\tr3, [pc, #308]\t@ (10a8 <__gridxc_array_MOD_aa_2d_1d_ip+0x144>)\n+\tmov\tr7, r0\n+\tldr\tr4, [sp, #76]\t@ 0x4c\n+\tadd\tr3, pc\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tldr.w\tsl, [r4, #24]\n+\tldr.w\tr9, [r4]\n+\tnegs\tr4, r6\n \tcmp.w\tsl, #0\n-\tstr\tr0, [sp, #32]\n-\tmov.w\tr0, #1\n \tit\teq\n-\tmoveq\tsl, r0\n-\tcbnz\tr1, 13b6 <__gridxc_array_MOD_aa_2d_1d_ip+0x3a>\n-\tmov.w\tr9, #4294967295\t@ 0xffffffff\n-\tmovs\tr1, #1\n-\tldr\tr5, [r2, #0]\n-\tldr.w\tr8, [r6]\n-\tldr\tr2, [r6, #36]\t@ 0x24\n-\tldr\tr0, [r7, #4]\n-\tldr.w\tr6, [lr, #4]\n-\tsub.w\tip, r9, r2\n-\tcmp\tr6, r0\n-\tbgt.n\t14ae <__gridxc_array_MOD_aa_2d_1d_ip+0x132>\n-\tmov\tr4, sl\n-\tldr.w\tfp, [lr]\n+\tmoveq.w\tsl, #1\n+\tcbnz\tr6, f96 <__gridxc_array_MOD_aa_2d_1d_ip+0x32>\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n+\tmovs\tr6, #1\n+\tldr.w\tfp, [r2, #36]\t@ 0x24\n+\tldr\tr5, [r1, #0]\n+\tldr.w\tip, [lr, #4]\n+\tldr\tr1, [r2, #0]\n+\tsub.w\tr2, r4, fp\n+\tldr\tr4, [r7, #4]\n+\tcmp\tr4, ip\n+\tbgt.n\t1012 <__gridxc_array_MOD_aa_2d_1d_ip+0xae>\n \tldr\tr7, [r7, #0]\n-\tcmp\tr1, #1\n+\tcmp.w\tsl, #1\n \tit\teq\n-\tcmpeq\tr4, #1\n-\tbne.n\t14d6 <__gridxc_array_MOD_aa_2d_1d_ip+0x15a>\n-\tadds\tr1, r0, #1\n-\tstr\tr1, [sp, #4]\n-\tsub.w\tr1, r7, fp\n-\tstr\tr1, [sp, #8]\n-\tadd.w\tlr, r1, #1\n-\tsub.w\tr1, fp, r2\n-\tadd\tr1, r9\n-\tmov\tsl, r2\n-\tldr\tr4, [sp, #32]\n-\tadd.w\tr1, r8, r1, lsl #2\n-\tstr\tr3, [sp, #32]\n-\tsub.w\tr1, r1, ip, lsl #2\n-\tstr\tr1, [sp, #20]\n-\tmov.w\tr1, lr, lsr #2\n-\tmla\tip, r2, r6, ip\n-\tlsls\tr1, r1, #4\n-\tstr\tr1, [sp, #12]\n-\tbic.w\tr1, lr, #3\n-\tstr\tr1, [sp, #16]\n-\tadd\tr1, fp\n-\tstr\tr1, [sp, #28]\n-\tand.w\tr1, lr, #3\n-\tstr\tr1, [sp, #24]\n-\tcmp\tfp, r7\n-\tbgt.n\t14a2 <__gridxc_array_MOD_aa_2d_1d_ip+0x126>\n-\tldr\tr3, [sp, #8]\n-\tcmp\tr3, #2\n-\tbls.n\t14ca <__gridxc_array_MOD_aa_2d_1d_ip+0x14e>\n-\tadd.w\tr3, r5, #1073741824\t@ 0x40000000\n-\tldr\tr1, [sp, #20]\n-\tsubs\tr3, #1\n-\tldr\tr0, [sp, #12]\n-\tmov\tr2, sl\n-\tadd.w\tr3, r4, r3, lsl #2\n-\tadd.w\tr1, r1, ip, lsl #2\n-\tadd\tr0, r3\n-\tvld1.32\t{d16-d17}, [r3]\n-\tvld1.32\t{d18-d19}, [r1]!\n-\tvadd.i32\tq8, q8, q9\n-\tvst1.32\t{d16-d17}, [r3]!\n-\tcmp\tr0, r3\n-\tbne.n\t143c <__gridxc_array_MOD_aa_2d_1d_ip+0xc0>\n-\tldr\tr1, [sp, #24]\n-\tmov\tsl, r2\n-\tldr\tr3, [sp, #16]\n-\tadds\tr3, r5, r3\n-\tcbz\tr1, 14a0 <__gridxc_array_MOD_aa_2d_1d_ip+0x124>\n-\tldr\tr1, [sp, #28]\n-\tsubs\tr3, #1\n-\tadd.w\tr0, ip, r1\n-\tldr.w\tr2, [r4, r3, lsl #2]\n-\tldr.w\tr0, [r8, r0, lsl #2]\n-\tadd\tr0, r2\n-\tstr.w\tr0, [r4, r3, lsl #2]\n-\tadds\tr0, r1, #1\n-\tlsls\tr3, r3, #2\n-\tcmp\tr7, r0\n-\tblt.n\t14a0 <__gridxc_array_MOD_aa_2d_1d_ip+0x124>\n-\tadd.w\tr9, r3, #4\n-\tadd\tr0, ip\n-\tadds\tr1, #2\n-\tcmp\tr7, r1\n-\tldr.w\tr2, [r4, r9]\n-\tldr.w\tr0, [r8, r0, lsl #2]\n-\tadd\tr0, r2\n-\tstr.w\tr0, [r4, r9]\n-\tblt.n\t14a0 <__gridxc_array_MOD_aa_2d_1d_ip+0x124>\n-\tadds\tr3, #8\n-\tadd\tr1, ip\n-\tldr.w\tr0, [r8, r1, lsl #2]\n-\tldr\tr1, [r4, r3]\n-\tadd\tr1, r0\n-\tstr\tr1, [r4, r3]\n-\tadd\tr5, lr\n-\tldr\tr3, [sp, #4]\n-\tadds\tr6, #1\n-\tadd\tip, sl\n-\tcmp\tr6, r3\n-\tbne.n\t141c <__gridxc_array_MOD_aa_2d_1d_ip+0xa0>\n-\tldr\tr3, [sp, #32]\n-\tldr\tr3, [r3, #0]\n-\tcmp\tr3, r5\n-\tblt.n\t14d0 <__gridxc_array_MOD_aa_2d_1d_ip+0x154>\n-\tldr\tr3, [pc, #144]\t@ (1548 <__gridxc_array_MOD_aa_2d_1d_ip+0x1cc>)\n+\tcmpeq\tr6, #1\n+\tldr.w\tr8, [lr]\n+\tbne.n\t1032 <__gridxc_array_MOD_aa_2d_1d_ip+0xce>\n+\tmla\tr6, fp, r4, r8\n+\tsub.w\tlr, r7, r8\n+\tadd.w\tsl, r8, #1\n+\tadd.w\tip, ip, #1\n+\tadd\tr2, r6\n+\tmov.w\tlr, lr, lsl #2\n+\tmov.w\tfp, fp, lsl #2\n+\tsub.w\tlr, lr, #4\n+\tadd.w\tr6, r1, r2, lsl #2\n+\tsub.w\tsl, sl, r7\n+\tstr\tr0, [sp, #8]\n+\tcmp\tr7, r8\n+\tbgt.n\t1008 <__gridxc_array_MOD_aa_2d_1d_ip+0xa4>\n+\tadd.w\tr2, r9, r5, lsl #2\n+\tadd.w\tr1, lr, r6\n+\tsubs\tr2, #8\n+\tstr\tr4, [sp, #4]\n+\tldr.w\tr0, [r2, #4]!\n+\tldr.w\tr4, [r1, #4]!\n+\tadd\tr0, r4\n+\tcmp\tr1, r6\n+\tstr\tr0, [r2, #0]\n+\tbne.n\tff4 <__gridxc_array_MOD_aa_2d_1d_ip+0x90>\n+\tldr\tr4, [sp, #4]\n+\tadd\tr5, sl\n+\tadds\tr4, #1\n+\tadd\tr6, fp\n+\tcmp\tr4, ip\n+\tbne.n\tfe4 <__gridxc_array_MOD_aa_2d_1d_ip+0x80>\n+\tldr\tr0, [sp, #8]\n+\tldr\tr2, [r0, #0]\n+\tcmp\tr2, r5\n+\tblt.n\t102c <__gridxc_array_MOD_aa_2d_1d_ip+0xc8>\n+\tldr\tr2, [pc, #144]\t@ (10ac <__gridxc_array_MOD_aa_2d_1d_ip+0x148>)\n \tmovs\tr1, #22\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tldr\tr0, [pc, #144]\t@ (154c <__gridxc_array_MOD_aa_2d_1d_ip+0x1d0>)\n-\tldr\tr3, [r2, r3]\n+\tldr\tr0, [pc, #144]\t@ (10b0 <__gridxc_array_MOD_aa_2d_1d_ip+0x14c>)\n \tadd\tr0, pc\n+\tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #44\t@ 0x2c\n+\tadd\tsp, #36\t@ 0x24\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tmov\tr1, fp\n-\tmov\tr3, r5\n-\tb.n\t145c <__gridxc_array_MOD_aa_2d_1d_ip+0xe0>\n-\tadd\tsp, #44\t@ 0x2c\n+\tadd\tsp, #36\t@ 0x24\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadds\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tmul.w\tr0, fp, r1\n-\tmov.w\tlr, r1, lsl #2\n-\tmov.w\tr9, sl, lsl #2\n-\tmla\tip, r2, r6, ip\n-\tstr\tr3, [sp, #24]\n-\tadd.w\tr0, r8, r0, lsl #2\n-\tadd.w\tr8, r7, #1\n-\tsub.w\tr1, r8, fp\n-\tstrd\tr1, sl, [sp, #16]\n-\tldr.w\tsl, [sp, #32]\n-\tstr\tr0, [sp, #12]\n-\tcmp\tfp, r7\n-\tbgt.n\t1534 <__gridxc_array_MOD_aa_2d_1d_ip+0x1b8>\n+\tmla\tr2, fp, r4, r2\n+\tadd.w\tlr, r8, #1\n+\tstr\tr2, [sp, #4]\n+\tadd.w\tr2, ip, #1\n+\tmul.w\tip, r6, r7\n+\tstr\tr2, [sp, #8]\n+\tstrd\tr0, r3, [sp, #24]\n+\tadd.w\tr2, r1, ip, lsl #2\n+\tstr\tr2, [sp, #12]\n+\tsub.w\tr2, lr, r7\n+\tstrd\tr2, sl, [sp, #16]\n+\tldr\tr2, [sp, #4]\n+\tmov.w\tip, r6, lsl #2\n+\tmov.w\tr6, sl, lsl #2\n+\tmov\tsl, r9\n+\tcmp\tr7, r8\n+\tbgt.n\t1098 <__gridxc_array_MOD_aa_2d_1d_ip+0x134>\n \tldr\tr1, [sp, #20]\n \tsubs\tr3, r5, #1\n-\tmov\tr0, fp\n+\tmov\tr0, r7\n \tstr\tr2, [sp, #4]\n \tmul.w\tr3, r1, r3\n \tldr\tr1, [sp, #12]\n \tadd.w\tr3, sl, r3, lsl #2\n-\tadd.w\tr4, r1, ip, lsl #2\n+\tadd.w\tr9, r1, r2, lsl #2\n \tldr\tr1, [r3, #0]\n \tadds\tr0, #1\n-\tldr\tr2, [r4, #0]\n-\tcmp\tr0, r8\n-\tadd\tr4, lr\n+\tldr.w\tr2, [r9]\n+\tcmp\tr0, lr\n+\tadd\tr9, ip\n \tadd\tr1, r2\n \tstr\tr1, [r3, #0]\n-\tadd\tr3, r9\n-\tbne.n\t151c <__gridxc_array_MOD_aa_2d_1d_ip+0x1a0>\n+\tadd\tr3, r6\n+\tbne.n\t107e <__gridxc_array_MOD_aa_2d_1d_ip+0x11a>\n \tldr\tr3, [sp, #16]\n \tldr\tr2, [sp, #4]\n \tadd\tr5, r3\n \tldr\tr3, [sp, #8]\n-\tadds\tr6, #1\n-\tadd\tip, r2\n-\tcmp\tr6, r3\n-\tbne.n\t1502 <__gridxc_array_MOD_aa_2d_1d_ip+0x186>\n-\tldr\tr3, [sp, #24]\n-\tb.n\t14ae <__gridxc_array_MOD_aa_2d_1d_ip+0x132>\n-\tnop\n-\t.word\t0x000001ac\n+\tadds\tr4, #1\n+\tadd\tr2, fp\n+\tcmp\tr4, r3\n+\tbne.n\t1064 <__gridxc_array_MOD_aa_2d_1d_ip+0x100>\n+\tldrd\tr0, r3, [sp, #24]\n+\tb.n\t1012 <__gridxc_array_MOD_aa_2d_1d_ip+0xae>\n+\t.word\t0x0000012e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000008a\n+\t.word\t0x0000008e\n R_ARM_REL32\t.LC8\n \n-00001550 <__gridxc_array_MOD_aa_1d_4d_dp>:\n+000010b4 <__gridxc_array_MOD_aa_1d_4d_dp>:\n __gridxc_array_MOD_aa_1d_4d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n \tsub\tsp, #44\t@ 0x2c\n \tldr\tr6, [sp, #84]\t@ 0x54\n \tldr\tr4, [sp, #80]\t@ 0x50\n \tstr\tr4, [sp, #28]\n \tldr.w\tfp, [r6, #24]\n-\tldr\tr4, [pc, #396]\t@ (16fc <__gridxc_array_MOD_aa_1d_4d_dp+0x1ac>)\n+\tldr\tr4, [pc, #400]\t@ (1264 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b0>)\n \trsb\tr5, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #20]\n \tcmp.w\tfp, #0\n-\tbne.n\t1584 <__gridxc_array_MOD_aa_1d_4d_dp+0x34>\n+\tbne.n\t10e8 <__gridxc_array_MOD_aa_1d_4d_dp+0x34>\n \tmov.w\tr5, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr.w\tlr, [r0]\n \tldr\tr0, [r6, #36]\t@ 0x24\n \tldr\tr7, [r6, #48]\t@ 0x30\n \tldr.w\tip, [r6, #60]\t@ 0x3c\n \tsubs\tr5, r5, r0\n@@ -2193,98 +1741,97 @@\n \tstr\tr5, [sp, #12]\n \tcmp\tlr, r4\n \tldr\tr5, [r3, #8]\n \tldr.w\tr8, [r6]\n \tldr\tr2, [r2, #0]\n \tldr\tr6, [r3, #12]\n \tstr\tr5, [sp, #16]\n-\tbgt.n\t166c <__gridxc_array_MOD_aa_1d_4d_dp+0x11c>\n+\tbgt.n\t11d0 <__gridxc_array_MOD_aa_1d_4d_dp+0x11c>\n \tldr\tr3, [sp, #28]\n+\tcmp.w\tfp, #1\n+\tit\teq\n+\tcmpeq\tr1, #1\n \tldr\tr5, [r3, #0]\n-\tldr.w\tsl, [r3, #8]\n \tstr\tr5, [sp, #4]\n \tldr\tr5, [r3, #4]\n-\tmov\tr3, fp\n-\tcmp\tr1, #1\n-\tit\teq\n-\tcmpeq\tr3, #1\n+\tldr.w\tsl, [r3, #8]\n \tstr\tr5, [sp, #24]\n-\tbne.n\t1690 <__gridxc_array_MOD_aa_1d_4d_dp+0x140>\n+\tbne.n\t11f4 <__gridxc_array_MOD_aa_1d_4d_dp+0x140>\n \tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r4, lsl #3\n \tldr\tr3, [sp, #8]\n \tadd.w\tr2, r2, lr, lsl #3\n \tldr.w\tlr, [sp, #24]\n \tldrd\tr5, r4, [sp, #12]\n \tmla\tr1, ip, r6, r9\n \tmla\tr1, r7, r4, r1\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tmla\tr1, r0, r5, r1\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tadd.w\tr1, r8, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n+\tvldr\td7, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n \tldr\tr1, [sp, #4]\n \tcmp\tr1, r3\n-\tbge.n\t1616 <__gridxc_array_MOD_aa_1d_4d_dp+0xc6>\n-\tldr\tr3, [sp, #8]\n-\tadds\tr5, #1\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr3, [sp, #8]\n \tcmp\tlr, r5\n-\tbge.n\t161e <__gridxc_array_MOD_aa_1d_4d_dp+0xce>\n-\tldr\tr5, [sp, #12]\n-\tadds\tr4, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tldrlt\tr5, [sp, #12]\n \tcmp\tsl, r4\n-\tbge.n\t1626 <__gridxc_array_MOD_aa_1d_4d_dp+0xd6>\n-\tldr\tr4, [sp, #16]\n-\tadds\tr6, #1\n+\titt\tlt\n+\taddlt\tr6, #1\n+\tldrlt\tr4, [sp, #16]\n \tcmp\tfp, r2\n-\tbne.n\t15e8 <__gridxc_array_MOD_aa_1d_4d_dp+0x98>\n+\tbne.n\t114c <__gridxc_array_MOD_aa_1d_4d_dp+0x98>\n \tldr\tr2, [sp, #8]\n \tcmp\tr2, r3\n-\tbeq.n\t1640 <__gridxc_array_MOD_aa_1d_4d_dp+0xf0>\n-\tldr\tr3, [pc, #204]\t@ (1700 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b0>)\n+\tbeq.n\t11a4 <__gridxc_array_MOD_aa_1d_4d_dp+0xf0>\n+\tldr\tr3, [pc, #208]\t@ (1268 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b4>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #204]\t@ (1704 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b4>)\n+\tldr\tr0, [pc, #208]\t@ (126c <__gridxc_array_MOD_aa_1d_4d_dp+0x1b8>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #12]\n \tcmp\tr3, r5\n-\tbeq.n\t1656 <__gridxc_array_MOD_aa_1d_4d_dp+0x106>\n-\tldr\tr3, [pc, #184]\t@ (1700 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b0>)\n+\tbeq.n\t11ba <__gridxc_array_MOD_aa_1d_4d_dp+0x106>\n+\tldr\tr3, [pc, #188]\t@ (1268 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b4>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #184]\t@ (1708 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b8>)\n+\tldr\tr0, [pc, #188]\t@ (1270 <__gridxc_array_MOD_aa_1d_4d_dp+0x1bc>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #16]\n \tcmp\tr3, r4\n-\tbeq.n\t166c <__gridxc_array_MOD_aa_1d_4d_dp+0x11c>\n-\tldr\tr3, [pc, #160]\t@ (1700 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b0>)\n+\tbeq.n\t11d0 <__gridxc_array_MOD_aa_1d_4d_dp+0x11c>\n+\tldr\tr3, [pc, #164]\t@ (1268 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b4>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #168]\t@ (170c <__gridxc_array_MOD_aa_1d_4d_dp+0x1bc>)\n+\tldr\tr0, [pc, #172]\t@ (1274 <__gridxc_array_MOD_aa_1d_4d_dp+0x1c0>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #28]\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, r6\n-\tblt.n\t168a <__gridxc_array_MOD_aa_1d_4d_dp+0x13a>\n-\tldr\tr3, [pc, #136]\t@ (1700 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b0>)\n+\tblt.n\t11ee <__gridxc_array_MOD_aa_1d_4d_dp+0x13a>\n+\tldr\tr3, [pc, #140]\t@ (1268 <__gridxc_array_MOD_aa_1d_4d_dp+0x1b4>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #148]\t@ (1710 <__gridxc_array_MOD_aa_1d_4d_dp+0x1c0>)\n+\tldr\tr0, [pc, #152]\t@ (1278 <__gridxc_array_MOD_aa_1d_4d_dp+0x1c4>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #44\t@ 0x2c\n@@ -2296,73 +1843,75 @@\n \tmul.w\tr3, r1, r3\n \tadd.w\tr2, r2, r3, lsl #3\n \tlsls\tr3, r1, #3\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tldr\tr3, [sp, #8]\n \tldr\tr1, [sp, #36]\t@ 0x24\n \tadd.w\tlr, lr, #1\n-\tvldr\td17, [r2]\n+\tvldr\td6, [r2]\n \tadd\tr2, r1\n \tmla\tr1, r6, ip, r9\n \tmla\tr1, r4, r7, r1\n \tmla\tr1, r5, r0, r1\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n \tadd.w\tr1, r8, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n+\tvldr\td7, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n \tldr\tr1, [sp, #4]\n \tcmp\tr1, r3\n-\tbge.n\t16e2 <__gridxc_array_MOD_aa_1d_4d_dp+0x192>\n-\tldr\tr3, [sp, #8]\n-\tadds\tr5, #1\n \tldr\tr1, [sp, #24]\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr3, [sp, #8]\n \tcmp\tr1, r5\n-\tbge.n\t16ec <__gridxc_array_MOD_aa_1d_4d_dp+0x19c>\n-\tldr\tr5, [sp, #12]\n-\tadds\tr4, #1\n-\tcmp\tsl, r4\n-\tbge.n\t16f4 <__gridxc_array_MOD_aa_1d_4d_dp+0x1a4>\n-\tldr\tr4, [sp, #16]\n-\tadds\tr6, #1\n+\tit\tlt\n+\taddlt\tr4, #1\n \tldr\tr1, [sp, #32]\n+\tit\tlt\n+\tldrlt\tr5, [sp, #12]\n+\tcmp\tsl, r4\n+\titt\tlt\n+\taddlt\tr6, #1\n+\tldrlt\tr4, [sp, #16]\n \tcmp\tr1, lr\n-\tbne.n\t16aa <__gridxc_array_MOD_aa_1d_4d_dp+0x15a>\n-\tb.n\t162a <__gridxc_array_MOD_aa_1d_4d_dp+0xda>\n-\t.word\t0x00000186\n+\tbne.n\t120e <__gridxc_array_MOD_aa_1d_4d_dp+0x15a>\n+\tb.n\t118e <__gridxc_array_MOD_aa_1d_4d_dp+0xda>\n+\tnop\n+\t.word\t0x0000018a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000c6\n+\t.word\t0x000000ca\n R_ARM_REL32\t.LC9\n-\t.word\t0x000000b4\n+\t.word\t0x000000b8\n R_ARM_REL32\t.LC10\n-\t.word\t0x000000a2\n+\t.word\t0x000000a6\n R_ARM_REL32\t.LC11\n-\t.word\t0x0000008e\n+\t.word\t0x00000092\n R_ARM_REL32\t.LC12\n \n-00001714 <__gridxc_array_MOD_aa_1d_4d_sp>:\n+0000127c <__gridxc_array_MOD_aa_1d_4d_sp>:\n __gridxc_array_MOD_aa_1d_4d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n \tsub\tsp, #44\t@ 0x2c\n \tldr\tr6, [sp, #84]\t@ 0x54\n \tldr\tr4, [sp, #80]\t@ 0x50\n \tstr\tr4, [sp, #28]\n \tldr.w\tfp, [r6, #24]\n-\tldr\tr4, [pc, #396]\t@ (18c0 <__gridxc_array_MOD_aa_1d_4d_sp+0x1ac>)\n+\tldr\tr4, [pc, #400]\t@ (142c <__gridxc_array_MOD_aa_1d_4d_sp+0x1b0>)\n \trsb\tr5, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #20]\n \tcmp.w\tfp, #0\n-\tbne.n\t1748 <__gridxc_array_MOD_aa_1d_4d_sp+0x34>\n+\tbne.n\t12b0 <__gridxc_array_MOD_aa_1d_4d_sp+0x34>\n \tmov.w\tr5, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr.w\tlr, [r0]\n \tldr\tr0, [r6, #36]\t@ 0x24\n \tldr\tr7, [r6, #48]\t@ 0x30\n \tldr.w\tip, [r6, #60]\t@ 0x3c\n \tsubs\tr5, r5, r0\n@@ -2379,26 +1928,25 @@\n \tstr\tr5, [sp, #12]\n \tcmp\tlr, r4\n \tldr\tr5, [r3, #8]\n \tldr.w\tr8, [r6]\n \tldr\tr2, [r2, #0]\n \tldr\tr6, [r3, #12]\n \tstr\tr5, [sp, #16]\n-\tbgt.n\t1830 <__gridxc_array_MOD_aa_1d_4d_sp+0x11c>\n+\tbgt.n\t1398 <__gridxc_array_MOD_aa_1d_4d_sp+0x11c>\n \tldr\tr3, [sp, #28]\n+\tcmp.w\tfp, #1\n+\tit\teq\n+\tcmpeq\tr1, #1\n \tldr\tr5, [r3, #0]\n-\tldr.w\tsl, [r3, #8]\n \tstr\tr5, [sp, #4]\n \tldr\tr5, [r3, #4]\n-\tmov\tr3, fp\n-\tcmp\tr1, #1\n-\tit\teq\n-\tcmpeq\tr3, #1\n+\tldr.w\tsl, [r3, #8]\n \tstr\tr5, [sp, #24]\n-\tbne.n\t1854 <__gridxc_array_MOD_aa_1d_4d_sp+0x140>\n+\tbne.n\t13bc <__gridxc_array_MOD_aa_1d_4d_sp+0x140>\n \tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r4, lsl #2\n \tldr\tr3, [sp, #8]\n \tadd.w\tr2, r2, lr, lsl #2\n \tldr.w\tlr, [sp, #24]\n \tldrd\tr5, r4, [sp, #12]\n \tmla\tr1, ip, r6, r9\n@@ -2409,68 +1957,68 @@\n \tadds\tr3, #1\n \tadd.w\tr1, r8, r1, lsl #2\n \tvldr\ts15, [r1]\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n \tldr\tr1, [sp, #4]\n \tcmp\tr1, r3\n-\tbge.n\t17da <__gridxc_array_MOD_aa_1d_4d_sp+0xc6>\n-\tldr\tr3, [sp, #8]\n-\tadds\tr5, #1\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr3, [sp, #8]\n \tcmp\tlr, r5\n-\tbge.n\t17e2 <__gridxc_array_MOD_aa_1d_4d_sp+0xce>\n-\tldr\tr5, [sp, #12]\n-\tadds\tr4, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tldrlt\tr5, [sp, #12]\n \tcmp\tsl, r4\n-\tbge.n\t17ea <__gridxc_array_MOD_aa_1d_4d_sp+0xd6>\n-\tldr\tr4, [sp, #16]\n-\tadds\tr6, #1\n+\titt\tlt\n+\taddlt\tr6, #1\n+\tldrlt\tr4, [sp, #16]\n \tcmp\tfp, r2\n-\tbne.n\t17ac <__gridxc_array_MOD_aa_1d_4d_sp+0x98>\n+\tbne.n\t1314 <__gridxc_array_MOD_aa_1d_4d_sp+0x98>\n \tldr\tr2, [sp, #8]\n \tcmp\tr2, r3\n-\tbeq.n\t1804 <__gridxc_array_MOD_aa_1d_4d_sp+0xf0>\n-\tldr\tr3, [pc, #204]\t@ (18c4 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b0>)\n+\tbeq.n\t136c <__gridxc_array_MOD_aa_1d_4d_sp+0xf0>\n+\tldr\tr3, [pc, #208]\t@ (1430 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b4>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #204]\t@ (18c8 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b4>)\n+\tldr\tr0, [pc, #208]\t@ (1434 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b8>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #12]\n \tcmp\tr3, r5\n-\tbeq.n\t181a <__gridxc_array_MOD_aa_1d_4d_sp+0x106>\n-\tldr\tr3, [pc, #184]\t@ (18c4 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b0>)\n+\tbeq.n\t1382 <__gridxc_array_MOD_aa_1d_4d_sp+0x106>\n+\tldr\tr3, [pc, #188]\t@ (1430 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b4>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #184]\t@ (18cc <__gridxc_array_MOD_aa_1d_4d_sp+0x1b8>)\n+\tldr\tr0, [pc, #188]\t@ (1438 <__gridxc_array_MOD_aa_1d_4d_sp+0x1bc>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #16]\n \tcmp\tr3, r4\n-\tbeq.n\t1830 <__gridxc_array_MOD_aa_1d_4d_sp+0x11c>\n-\tldr\tr3, [pc, #160]\t@ (18c4 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b0>)\n+\tbeq.n\t1398 <__gridxc_array_MOD_aa_1d_4d_sp+0x11c>\n+\tldr\tr3, [pc, #164]\t@ (1430 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b4>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #168]\t@ (18d0 <__gridxc_array_MOD_aa_1d_4d_sp+0x1bc>)\n+\tldr\tr0, [pc, #172]\t@ (143c <__gridxc_array_MOD_aa_1d_4d_sp+0x1c0>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #28]\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, r6\n-\tblt.n\t184e <__gridxc_array_MOD_aa_1d_4d_sp+0x13a>\n-\tldr\tr3, [pc, #136]\t@ (18c4 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b0>)\n+\tblt.n\t13b6 <__gridxc_array_MOD_aa_1d_4d_sp+0x13a>\n+\tldr\tr3, [pc, #140]\t@ (1430 <__gridxc_array_MOD_aa_1d_4d_sp+0x1b4>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #148]\t@ (18d4 <__gridxc_array_MOD_aa_1d_4d_sp+0x1c0>)\n+\tldr\tr0, [pc, #152]\t@ (1440 <__gridxc_array_MOD_aa_1d_4d_sp+0x1c4>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #44\t@ 0x2c\n@@ -2495,60 +2043,62 @@\n \tadds\tr3, #1\n \tadd.w\tr1, r8, r1, lsl #2\n \tvldr\ts15, [r1]\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n \tldr\tr1, [sp, #4]\n \tcmp\tr1, r3\n-\tbge.n\t18a6 <__gridxc_array_MOD_aa_1d_4d_sp+0x192>\n-\tldr\tr3, [sp, #8]\n-\tadds\tr5, #1\n \tldr\tr1, [sp, #24]\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr3, [sp, #8]\n \tcmp\tr1, r5\n-\tbge.n\t18b0 <__gridxc_array_MOD_aa_1d_4d_sp+0x19c>\n-\tldr\tr5, [sp, #12]\n-\tadds\tr4, #1\n-\tcmp\tsl, r4\n-\tbge.n\t18b8 <__gridxc_array_MOD_aa_1d_4d_sp+0x1a4>\n-\tldr\tr4, [sp, #16]\n-\tadds\tr6, #1\n+\tit\tlt\n+\taddlt\tr4, #1\n \tldr\tr1, [sp, #32]\n+\tit\tlt\n+\tldrlt\tr5, [sp, #12]\n+\tcmp\tsl, r4\n+\titt\tlt\n+\taddlt\tr6, #1\n+\tldrlt\tr4, [sp, #16]\n \tcmp\tr1, lr\n-\tbne.n\t186e <__gridxc_array_MOD_aa_1d_4d_sp+0x15a>\n-\tb.n\t17ee <__gridxc_array_MOD_aa_1d_4d_sp+0xda>\n-\t.word\t0x00000186\n+\tbne.n\t13d6 <__gridxc_array_MOD_aa_1d_4d_sp+0x15a>\n+\tb.n\t1356 <__gridxc_array_MOD_aa_1d_4d_sp+0xda>\n+\tnop\n+\t.word\t0x0000018a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000c6\n+\t.word\t0x000000ca\n R_ARM_REL32\t.LC13\n-\t.word\t0x000000b4\n+\t.word\t0x000000b8\n R_ARM_REL32\t.LC14\n-\t.word\t0x000000a2\n+\t.word\t0x000000a6\n R_ARM_REL32\t.LC15\n-\t.word\t0x0000008e\n+\t.word\t0x00000092\n R_ARM_REL32\t.LC16\n \n-000018d8 <__gridxc_array_MOD_aa_1d_4d_ip>:\n+00001444 <__gridxc_array_MOD_aa_1d_4d_ip>:\n __gridxc_array_MOD_aa_1d_4d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #52\t@ 0x34\n \tldr\tr5, [sp, #92]\t@ 0x5c\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #36]\t@ 0x24\n \tldr.w\tfp, [r5, #24]\n-\tldr\tr4, [pc, #408]\t@ (1a90 <__gridxc_array_MOD_aa_1d_4d_ip+0x1b8>)\n+\tldr\tr4, [pc, #408]\t@ (15fc <__gridxc_array_MOD_aa_1d_4d_ip+0x1b8>)\n \trsb\tr6, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #32]\n \tcmp.w\tfp, #0\n-\tbne.n\t190c <__gridxc_array_MOD_aa_1d_4d_ip+0x34>\n+\tbne.n\t1478 <__gridxc_array_MOD_aa_1d_4d_ip+0x34>\n \tmov.w\tr6, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr.w\tip, [r5, #36]\t@ 0x24\n \tldr.w\tlr, [r5, #48]\t@ 0x30\n \tldr.w\tsl, [r0]\n \tldr\tr4, [r1, #0]\n \tldr\tr0, [r2, #24]\n@@ -2565,27 +2115,26 @@\n \tmoveq\tr0, #1\n \tldr\tr2, [r3, #4]\n \tcmp\tsl, r4\n \tstr\tr2, [sp, #20]\n \tldr\tr2, [r3, #8]\n \tldr\tr6, [r3, #12]\n \tstr\tr2, [sp, #24]\n-\tbgt.n\t19fa <__gridxc_array_MOD_aa_1d_4d_ip+0x122>\n+\tbgt.n\t1566 <__gridxc_array_MOD_aa_1d_4d_ip+0x122>\n \tldr\tr3, [sp, #36]\t@ 0x24\n+\tcmp.w\tfp, #1\n+\tit\teq\n+\tcmpeq\tr0, #1\n \tldr\tr2, [r3, #0]\n \tstr\tr2, [sp, #4]\n \tldr\tr2, [r3, #4]\n \tldr\tr3, [r3, #8]\n-\tstr\tr3, [sp, #12]\n-\tmov\tr3, fp\n-\tcmp\tr0, #1\n-\tit\teq\n-\tcmpeq\tr3, #1\n \tstr\tr2, [sp, #8]\n-\tbne.n\t1a1e <__gridxc_array_MOD_aa_1d_4d_ip+0x146>\n+\tstr\tr3, [sp, #12]\n+\tbne.n\t158a <__gridxc_array_MOD_aa_1d_4d_ip+0x146>\n \tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r1, r4, lsl #2\n \tldr\tr2, [sp, #16]\n \tldrd\tr5, r4, [sp, #20]\n \tadd.w\tr1, r1, sl, lsl #2\n \tmov\tsl, r6\n \tmla\tr3, r8, sl, r9\n@@ -2595,71 +2144,71 @@\n \tadd\tr3, r2\n \tadds\tr2, #1\n \tldr.w\tr6, [r7, r3, lsl #2]\n \tadd\tr0, r6\n \tstr.w\tr0, [r7, r3, lsl #2]\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r2\n-\tbge.n\t199c <__gridxc_array_MOD_aa_1d_4d_ip+0xc4>\n-\tldr\tr2, [sp, #16]\n-\tadds\tr5, #1\n \tldr\tr3, [sp, #8]\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr2, [sp, #16]\n \tcmp\tr3, r5\n-\tbge.n\t19a6 <__gridxc_array_MOD_aa_1d_4d_ip+0xce>\n-\tldr\tr5, [sp, #20]\n-\tadds\tr4, #1\n \tldr\tr3, [sp, #12]\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tldrlt\tr5, [sp, #20]\n \tcmp\tr3, r4\n-\tbge.n\t19b2 <__gridxc_array_MOD_aa_1d_4d_ip+0xda>\n-\tldr\tr4, [sp, #24]\n-\tadd.w\tsl, sl, #1\n+\titt\tlt\n+\taddlt.w\tsl, sl, #1\n+\tldrlt\tr4, [sp, #24]\n \tcmp\tfp, r1\n-\tbne.n\t1974 <__gridxc_array_MOD_aa_1d_4d_ip+0x9c>\n+\tbne.n\t14e0 <__gridxc_array_MOD_aa_1d_4d_ip+0x9c>\n \tmov\tr6, sl\n \tldr\tr3, [sp, #16]\n \tcmp\tr3, r2\n-\tbeq.n\t19ce <__gridxc_array_MOD_aa_1d_4d_ip+0xf6>\n-\tldr\tr3, [pc, #212]\t@ (1a94 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n+\tbeq.n\t153a <__gridxc_array_MOD_aa_1d_4d_ip+0xf6>\n+\tldr\tr3, [pc, #212]\t@ (1600 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #32]\n-\tldr\tr0, [pc, #208]\t@ (1a98 <__gridxc_array_MOD_aa_1d_4d_ip+0x1c0>)\n+\tldr\tr0, [pc, #208]\t@ (1604 <__gridxc_array_MOD_aa_1d_4d_ip+0x1c0>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #20]\n \tcmp\tr3, r5\n-\tbeq.n\t19e4 <__gridxc_array_MOD_aa_1d_4d_ip+0x10c>\n-\tldr\tr3, [pc, #188]\t@ (1a94 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n+\tbeq.n\t1550 <__gridxc_array_MOD_aa_1d_4d_ip+0x10c>\n+\tldr\tr3, [pc, #188]\t@ (1600 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #32]\n-\tldr\tr0, [pc, #192]\t@ (1a9c <__gridxc_array_MOD_aa_1d_4d_ip+0x1c4>)\n+\tldr\tr0, [pc, #192]\t@ (1608 <__gridxc_array_MOD_aa_1d_4d_ip+0x1c4>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #24]\n \tcmp\tr3, r4\n-\tbeq.n\t19fa <__gridxc_array_MOD_aa_1d_4d_ip+0x122>\n-\tldr\tr3, [pc, #168]\t@ (1a94 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n+\tbeq.n\t1566 <__gridxc_array_MOD_aa_1d_4d_ip+0x122>\n+\tldr\tr3, [pc, #168]\t@ (1600 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #32]\n-\tldr\tr0, [pc, #172]\t@ (1aa0 <__gridxc_array_MOD_aa_1d_4d_ip+0x1c8>)\n+\tldr\tr0, [pc, #172]\t@ (160c <__gridxc_array_MOD_aa_1d_4d_ip+0x1c8>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tldr\tr3, [r3, #12]\n \tcmp\tr3, r6\n-\tblt.n\t1a18 <__gridxc_array_MOD_aa_1d_4d_ip+0x140>\n-\tldr\tr3, [pc, #144]\t@ (1a94 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n+\tblt.n\t1584 <__gridxc_array_MOD_aa_1d_4d_ip+0x140>\n+\tldr\tr3, [pc, #144]\t@ (1600 <__gridxc_array_MOD_aa_1d_4d_ip+0x1bc>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #32]\n-\tldr\tr0, [pc, #152]\t@ (1aa4 <__gridxc_array_MOD_aa_1d_4d_ip+0x1cc>)\n+\tldr\tr0, [pc, #152]\t@ (1610 <__gridxc_array_MOD_aa_1d_4d_ip+0x1cc>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #52\t@ 0x34\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #52\t@ 0x34\n@@ -2685,65 +2234,65 @@\n \tmla\tr3, r2, fp, r3\n \tadds\tr2, #1\n \tldr.w\tr6, [r7, r3, lsl #2]\n \tadd\tr0, r6\n \tstr.w\tr0, [r7, r3, lsl #2]\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r2\n-\tbge.n\t1a6c <__gridxc_array_MOD_aa_1d_4d_ip+0x194>\n-\tldr\tr2, [sp, #16]\n-\tadds\tr5, #1\n \tldr\tr3, [sp, #8]\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr2, [sp, #16]\n \tcmp\tr3, r5\n-\tbge.n\t1a76 <__gridxc_array_MOD_aa_1d_4d_ip+0x19e>\n-\tldr\tr5, [sp, #20]\n-\tadds\tr4, #1\n \tldr\tr3, [sp, #12]\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tldrlt\tr5, [sp, #20]\n \tcmp\tr3, r4\n-\tbge.n\t1a84 <__gridxc_array_MOD_aa_1d_4d_ip+0x1ac>\n-\tldr\tr3, [sp, #28]\n-\tldr\tr4, [sp, #24]\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #28]\n+\titttt\tlt\n+\tldrlt\tr3, [sp, #28]\n+\tldrlt\tr4, [sp, #24]\n+\taddlt\tr3, #1\n+\tstrlt\tr3, [sp, #28]\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, sl\n-\tbne.n\t1a3a <__gridxc_array_MOD_aa_1d_4d_ip+0x162>\n+\tbne.n\t15a6 <__gridxc_array_MOD_aa_1d_4d_ip+0x162>\n \tldr\tr6, [sp, #28]\n-\tb.n\t19b8 <__gridxc_array_MOD_aa_1d_4d_ip+0xe0>\n+\tb.n\t1524 <__gridxc_array_MOD_aa_1d_4d_ip+0xe0>\n \tnop\n \t.word\t0x00000192\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x000000cc\n R_ARM_REL32\t.LC17\n \t.word\t0x000000ba\n R_ARM_REL32\t.LC18\n \t.word\t0x000000a8\n R_ARM_REL32\t.LC19\n \t.word\t0x00000094\n R_ARM_REL32\t.LC20\n \n-00001aa8 <__gridxc_array_MOD_aa_1d_3d_dp>:\n+00001614 <__gridxc_array_MOD_aa_1d_3d_dp>:\n __gridxc_array_MOD_aa_1d_3d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tldr\tr5, [sp, #68]\t@ 0x44\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #8]\n \tldr.w\tfp, [r5, #24]\n-\tldr\tr4, [pc, #324]\t@ (1c0c <__gridxc_array_MOD_aa_1d_3d_dp+0x164>)\n+\tldr\tr4, [pc, #328]\t@ (177c <__gridxc_array_MOD_aa_1d_3d_dp+0x168>)\n \trsb\tr7, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #12]\n \tcmp.w\tfp, #0\n-\tbne.n\t1adc <__gridxc_array_MOD_aa_1d_3d_dp+0x34>\n+\tbne.n\t1648 <__gridxc_array_MOD_aa_1d_3d_dp+0x34>\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r5, #36]\t@ 0x24\n \tldr\tr4, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr.w\tip, [r0]\n \tsubs\tr0, r7, r6\n@@ -2754,76 +2303,75 @@\n \tmoveq\tr1, #1\n \tldrd\tsl, r5, [r3]\n \tstr\tr5, [sp, #4]\n \tldr\tr2, [r2, #0]\n \tsubs\tr0, r0, r7\n \tldr\tr5, [r3, #8]\n \tcmp\tip, r4\n-\tbgt.n\t1b86 <__gridxc_array_MOD_aa_1d_3d_dp+0xde>\n+\tbgt.n\t16f2 <__gridxc_array_MOD_aa_1d_3d_dp+0xde>\n \tldr\tr3, [sp, #8]\n-\tldrd\tr8, r9, [r3]\n-\tmov\tr3, fp\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t1baa <__gridxc_array_MOD_aa_1d_3d_dp+0x102>\n+\tcmpeq\tr1, #1\n+\tldrd\tr8, r9, [r3]\n+\tbne.n\t1716 <__gridxc_array_MOD_aa_1d_3d_dp+0x102>\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r4, lsl #3\n \tmov\tr3, sl\n \tadd.w\tr2, r2, ip, lsl #3\n \tldr.w\tip, [sp, #4]\n \tmov\tr4, ip\n \tmla\tr1, r7, r5, r0\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tmla\tr1, r6, r4, r1\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tcmp\tr8, r3\n \tadd.w\tr1, lr, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n-\tbge.n\t1b50 <__gridxc_array_MOD_aa_1d_3d_dp+0xa8>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tcmp\tr9, r4\n-\tbge.n\t1b58 <__gridxc_array_MOD_aa_1d_3d_dp+0xb0>\n-\tadds\tr5, #1\n-\tmov\tr4, ip\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tmovlt\tr4, ip\n+\tvldr\td7, [r1]\n \tcmp\tfp, r2\n-\tbne.n\t1b28 <__gridxc_array_MOD_aa_1d_3d_dp+0x80>\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n+\tbne.n\t1694 <__gridxc_array_MOD_aa_1d_3d_dp+0x80>\n \tcmp\tsl, r3\n-\tbeq.n\t1b70 <__gridxc_array_MOD_aa_1d_3d_dp+0xc8>\n-\tldr\tr3, [pc, #172]\t@ (1c10 <__gridxc_array_MOD_aa_1d_3d_dp+0x168>)\n+\tbeq.n\t16dc <__gridxc_array_MOD_aa_1d_3d_dp+0xc8>\n+\tldr\tr3, [pc, #176]\t@ (1780 <__gridxc_array_MOD_aa_1d_3d_dp+0x16c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #172]\t@ (1c14 <__gridxc_array_MOD_aa_1d_3d_dp+0x16c>)\n+\tldr\tr0, [pc, #176]\t@ (1784 <__gridxc_array_MOD_aa_1d_3d_dp+0x170>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r4\n-\tbeq.n\t1b86 <__gridxc_array_MOD_aa_1d_3d_dp+0xde>\n-\tldr\tr3, [pc, #152]\t@ (1c10 <__gridxc_array_MOD_aa_1d_3d_dp+0x168>)\n+\tbeq.n\t16f2 <__gridxc_array_MOD_aa_1d_3d_dp+0xde>\n+\tldr\tr3, [pc, #156]\t@ (1780 <__gridxc_array_MOD_aa_1d_3d_dp+0x16c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #152]\t@ (1c18 <__gridxc_array_MOD_aa_1d_3d_dp+0x170>)\n+\tldr\tr0, [pc, #156]\t@ (1788 <__gridxc_array_MOD_aa_1d_3d_dp+0x174>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #8]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t1ba4 <__gridxc_array_MOD_aa_1d_3d_dp+0xfc>\n-\tldr\tr3, [pc, #128]\t@ (1c10 <__gridxc_array_MOD_aa_1d_3d_dp+0x168>)\n+\tblt.n\t1710 <__gridxc_array_MOD_aa_1d_3d_dp+0xfc>\n+\tldr\tr3, [pc, #132]\t@ (1780 <__gridxc_array_MOD_aa_1d_3d_dp+0x16c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #132]\t@ (1c1c <__gridxc_array_MOD_aa_1d_3d_dp+0x174>)\n+\tldr\tr0, [pc, #136]\t@ (178c <__gridxc_array_MOD_aa_1d_3d_dp+0x178>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n@@ -2835,66 +2383,68 @@\n \tstr.w\tsl, [sp, #20]\n \tmul.w\tr3, r1, r3\n \tlsls\tr1, r1, #3\n \tadd.w\tr2, r2, r3, lsl #3\n \tmov\tr3, sl\n \tmov\tsl, r1\n \tmla\tr1, r5, r7, r0\n-\tvldr\td17, [r2]\n+\tvldr\td6, [r2]\n \tmla\tr1, r4, r6, r1\n \tadd.w\tip, ip, #1\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadd\tr2, sl\n \tcmp\tr8, r3\n+\tadd\tr2, sl\n+\tit\tlt\n+\taddlt\tr4, #1\n \tadd.w\tr1, lr, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n-\tbge.n\t1bf6 <__gridxc_array_MOD_aa_1d_3d_dp+0x14e>\n-\tldr\tr3, [sp, #20]\n-\tadds\tr4, #1\n+\tit\tlt\n+\tldrlt\tr3, [sp, #20]\n \tcmp\tr9, r4\n-\tbge.n\t1bfe <__gridxc_array_MOD_aa_1d_3d_dp+0x156>\n-\tldr\tr4, [sp, #4]\n-\tadds\tr5, #1\n+\tit\tlt\n+\taddlt\tr5, #1\n+\tvldr\td7, [r1]\n+\tit\tlt\n+\tldrlt\tr4, [sp, #4]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n \tldr\tr1, [sp, #16]\n \tcmp\tr1, ip\n-\tbne.n\t1bc6 <__gridxc_array_MOD_aa_1d_3d_dp+0x11e>\n+\tbne.n\t1732 <__gridxc_array_MOD_aa_1d_3d_dp+0x11e>\n \tldr.w\tsl, [sp, #20]\n-\tb.n\t1b5c <__gridxc_array_MOD_aa_1d_3d_dp+0xb4>\n+\tb.n\t16c8 <__gridxc_array_MOD_aa_1d_3d_dp+0xb4>\n \tnop\n-\t.word\t0x0000013e\n+\t.word\t0x00000142\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000a6\n+\t.word\t0x000000aa\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000094\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC22\n-\t.word\t0x00000080\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC23\n \n-00001c20 <__gridxc_array_MOD_aa_1d_3d_sp>:\n+00001790 <__gridxc_array_MOD_aa_1d_3d_sp>:\n __gridxc_array_MOD_aa_1d_3d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tldr\tr5, [sp, #68]\t@ 0x44\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #8]\n \tldr.w\tfp, [r5, #24]\n-\tldr\tr4, [pc, #324]\t@ (1d84 <__gridxc_array_MOD_aa_1d_3d_sp+0x164>)\n+\tldr\tr4, [pc, #328]\t@ (18f8 <__gridxc_array_MOD_aa_1d_3d_sp+0x168>)\n \trsb\tr7, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #12]\n \tcmp.w\tfp, #0\n-\tbne.n\t1c54 <__gridxc_array_MOD_aa_1d_3d_sp+0x34>\n+\tbne.n\t17c4 <__gridxc_array_MOD_aa_1d_3d_sp+0x34>\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r5, #36]\t@ 0x24\n \tldr\tr4, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr.w\tip, [r0]\n \tsubs\tr0, r7, r6\n@@ -2905,76 +2455,75 @@\n \tmoveq\tr1, #1\n \tldrd\tsl, r5, [r3]\n \tstr\tr5, [sp, #4]\n \tldr\tr2, [r2, #0]\n \tsubs\tr0, r0, r7\n \tldr\tr5, [r3, #8]\n \tcmp\tip, r4\n-\tbgt.n\t1cfe <__gridxc_array_MOD_aa_1d_3d_sp+0xde>\n+\tbgt.n\t186e <__gridxc_array_MOD_aa_1d_3d_sp+0xde>\n \tldr\tr3, [sp, #8]\n-\tldrd\tr8, r9, [r3]\n-\tmov\tr3, fp\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t1d22 <__gridxc_array_MOD_aa_1d_3d_sp+0x102>\n+\tcmpeq\tr1, #1\n+\tldrd\tr8, r9, [r3]\n+\tbne.n\t1892 <__gridxc_array_MOD_aa_1d_3d_sp+0x102>\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r4, lsl #2\n \tmov\tr3, sl\n \tadd.w\tr2, r2, ip, lsl #2\n \tldr.w\tip, [sp, #4]\n \tmov\tr4, ip\n \tmla\tr1, r7, r5, r0\n \tvldmia\tr2!, {s14}\n \tmla\tr1, r6, r4, r1\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tcmp\tr8, r3\n \tadd.w\tr1, lr, r1, lsl #2\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n+\tcmp\tr9, r4\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tmovlt\tr4, ip\n \tvldr\ts15, [r1]\n+\tcmp\tfp, r2\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n-\tbge.n\t1cc8 <__gridxc_array_MOD_aa_1d_3d_sp+0xa8>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n-\tcmp\tr9, r4\n-\tbge.n\t1cd0 <__gridxc_array_MOD_aa_1d_3d_sp+0xb0>\n-\tadds\tr5, #1\n-\tmov\tr4, ip\n-\tcmp\tfp, r2\n-\tbne.n\t1ca0 <__gridxc_array_MOD_aa_1d_3d_sp+0x80>\n+\tbne.n\t1810 <__gridxc_array_MOD_aa_1d_3d_sp+0x80>\n \tcmp\tsl, r3\n-\tbeq.n\t1ce8 <__gridxc_array_MOD_aa_1d_3d_sp+0xc8>\n-\tldr\tr3, [pc, #172]\t@ (1d88 <__gridxc_array_MOD_aa_1d_3d_sp+0x168>)\n+\tbeq.n\t1858 <__gridxc_array_MOD_aa_1d_3d_sp+0xc8>\n+\tldr\tr3, [pc, #176]\t@ (18fc <__gridxc_array_MOD_aa_1d_3d_sp+0x16c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #172]\t@ (1d8c <__gridxc_array_MOD_aa_1d_3d_sp+0x16c>)\n+\tldr\tr0, [pc, #176]\t@ (1900 <__gridxc_array_MOD_aa_1d_3d_sp+0x170>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r4\n-\tbeq.n\t1cfe <__gridxc_array_MOD_aa_1d_3d_sp+0xde>\n-\tldr\tr3, [pc, #152]\t@ (1d88 <__gridxc_array_MOD_aa_1d_3d_sp+0x168>)\n+\tbeq.n\t186e <__gridxc_array_MOD_aa_1d_3d_sp+0xde>\n+\tldr\tr3, [pc, #156]\t@ (18fc <__gridxc_array_MOD_aa_1d_3d_sp+0x16c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #152]\t@ (1d90 <__gridxc_array_MOD_aa_1d_3d_sp+0x170>)\n+\tldr\tr0, [pc, #156]\t@ (1904 <__gridxc_array_MOD_aa_1d_3d_sp+0x174>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #8]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t1d1c <__gridxc_array_MOD_aa_1d_3d_sp+0xfc>\n-\tldr\tr3, [pc, #128]\t@ (1d88 <__gridxc_array_MOD_aa_1d_3d_sp+0x168>)\n+\tblt.n\t188c <__gridxc_array_MOD_aa_1d_3d_sp+0xfc>\n+\tldr\tr3, [pc, #132]\t@ (18fc <__gridxc_array_MOD_aa_1d_3d_sp+0x16c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #132]\t@ (1d94 <__gridxc_array_MOD_aa_1d_3d_sp+0x174>)\n+\tldr\tr0, [pc, #136]\t@ (1908 <__gridxc_array_MOD_aa_1d_3d_sp+0x178>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n@@ -2991,62 +2540,64 @@\n \tmov\tsl, r1\n \tmla\tr1, r5, r7, r0\n \tvldr\ts14, [r2]\n \tmla\tr1, r4, r6, r1\n \tadd.w\tip, ip, #1\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadd\tr2, sl\n \tcmp\tr8, r3\n+\tadd\tr2, sl\n+\tit\tlt\n+\taddlt\tr4, #1\n \tadd.w\tr1, lr, r1, lsl #2\n+\tit\tlt\n+\tldrlt\tr3, [sp, #20]\n+\tcmp\tr9, r4\n+\tit\tlt\n+\taddlt\tr5, #1\n \tvldr\ts15, [r1]\n+\tit\tlt\n+\tldrlt\tr4, [sp, #4]\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n-\tbge.n\t1d6e <__gridxc_array_MOD_aa_1d_3d_sp+0x14e>\n-\tldr\tr3, [sp, #20]\n-\tadds\tr4, #1\n-\tcmp\tr9, r4\n-\tbge.n\t1d76 <__gridxc_array_MOD_aa_1d_3d_sp+0x156>\n-\tldr\tr4, [sp, #4]\n-\tadds\tr5, #1\n \tldr\tr1, [sp, #16]\n \tcmp\tr1, ip\n-\tbne.n\t1d3e <__gridxc_array_MOD_aa_1d_3d_sp+0x11e>\n+\tbne.n\t18ae <__gridxc_array_MOD_aa_1d_3d_sp+0x11e>\n \tldr.w\tsl, [sp, #20]\n-\tb.n\t1cd4 <__gridxc_array_MOD_aa_1d_3d_sp+0xb4>\n+\tb.n\t1844 <__gridxc_array_MOD_aa_1d_3d_sp+0xb4>\n \tnop\n-\t.word\t0x0000013e\n+\t.word\t0x00000142\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000a6\n+\t.word\t0x000000aa\n R_ARM_REL32\t.LC24\n-\t.word\t0x00000094\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC25\n-\t.word\t0x00000080\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC26\n \n-00001d98 <__gridxc_array_MOD_aa_1d_3d_ip>:\n+0000190c <__gridxc_array_MOD_aa_1d_3d_ip>:\n __gridxc_array_MOD_aa_1d_3d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4024]\t@ 0xfb8\n \tsub\tsp, #36\t@ 0x24\n-\tldr.w\tsl, [pc, #360]\t@ 1f14 <__gridxc_array_MOD_aa_1d_3d_ip+0x17c>\n+\tldr.w\tsl, [pc, #364]\t@ 1a8c <__gridxc_array_MOD_aa_1d_3d_ip+0x180>\n \tmov\tr5, r3\n \tadd\tsl, pc\n \tldr\tr4, [sp, #72]\t@ 0x48\n \tstr\tr4, [sp, #16]\n \tmov\tr4, r1\n \tldr\tr1, [sp, #76]\t@ 0x4c\n \tldr.w\tr9, [r1, #24]\n \trsb\tr7, r9, #0\n \tcmp.w\tr9, #0\n-\tbne.n\t1dd0 <__gridxc_array_MOD_aa_1d_3d_ip+0x38>\n+\tbne.n\t1944 <__gridxc_array_MOD_aa_1d_3d_ip+0x38>\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tr9, #1\n \tldr\tr6, [r1, #36]\t@ 0x24\n \tldr.w\tip, [r0]\n \tldr\tr3, [r4, #0]\n \tsubs\tr0, r7, r6\n \tldr\tr4, [r2, #24]\n@@ -3060,22 +2611,21 @@\n \tsubs\tr0, r0, r7\n \tstr\tr1, [sp, #12]\n \tcmp\tip, r3\n \tldr\tr1, [r5, #4]\n \tldr\tr2, [r2, #0]\n \tldr\tr5, [r5, #8]\n \tstr\tr1, [sp, #8]\n-\tbgt.n\t1e88 <__gridxc_array_MOD_aa_1d_3d_ip+0xf0>\n+\tbgt.n\t19fe <__gridxc_array_MOD_aa_1d_3d_ip+0xf2>\n \tldr\tr1, [sp, #16]\n-\tldrd\tlr, r8, [r1]\n-\tmov\tr1, r9\n-\tcmp\tr4, #1\n+\tcmp.w\tr9, #1\n \tit\teq\n-\tcmpeq\tr1, #1\n-\tbne.n\t1eac <__gridxc_array_MOD_aa_1d_3d_ip+0x114>\n+\tcmpeq\tr4, #1\n+\tldrd\tlr, r8, [r1]\n+\tbne.n\t1a22 <__gridxc_array_MOD_aa_1d_3d_ip+0x116>\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r3, lsl #2\n \tstr.w\tsl, [sp, #20]\n \tadd.w\tr9, r2, ip, lsl #2\n \tmov\tip, r0\n \tldrd\tr4, r2, [sp, #8]\n \tldr\tr1, [sp, #4]\n@@ -3085,54 +2635,55 @@\n \tldr\tr0, [sp, #4]\n \tmla\tr2, r7, r5, ip\n \tmla\tr2, r0, r4, r2\n \tldr.w\tr0, [r9], #4\n \tadd\tr2, r3\n \tadds\tr3, #1\n \tcmp\tlr, r3\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n+\tcmp\tr8, r4\n \tldr.w\tr6, [r1, r2, lsl #2]\n+\tit\tlt\n+\taddlt\tr5, #1\n \tadd\tr0, r6\n \tstr.w\tr0, [r1, r2, lsl #2]\n-\tbge.n\t1e4c <__gridxc_array_MOD_aa_1d_3d_ip+0xb4>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n-\tcmp\tr8, r4\n-\tbge.n\t1e54 <__gridxc_array_MOD_aa_1d_3d_ip+0xbc>\n-\tldr\tr4, [sp, #8]\n-\tadds\tr5, #1\n+\tit\tlt\n+\tldrlt\tr4, [sp, #8]\n \tcmp\tfp, r9\n-\tbne.n\t1e28 <__gridxc_array_MOD_aa_1d_3d_ip+0x90>\n+\tbne.n\t199c <__gridxc_array_MOD_aa_1d_3d_ip+0x90>\n \tldr.w\tsl, [sp, #20]\n \tldr\tr2, [sp, #12]\n \tcmp\tr2, r3\n-\tbeq.n\t1e72 <__gridxc_array_MOD_aa_1d_3d_ip+0xda>\n-\tldr\tr3, [pc, #180]\t@ (1f18 <__gridxc_array_MOD_aa_1d_3d_ip+0x180>)\n+\tbeq.n\t19e8 <__gridxc_array_MOD_aa_1d_3d_ip+0xdc>\n+\tldr\tr3, [pc, #180]\t@ (1a90 <__gridxc_array_MOD_aa_1d_3d_ip+0x184>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #180]\t@ (1f1c <__gridxc_array_MOD_aa_1d_3d_ip+0x184>)\n+\tldr\tr0, [pc, #180]\t@ (1a94 <__gridxc_array_MOD_aa_1d_3d_ip+0x188>)\n \tadd\tr0, pc\n \tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #8]\n \tcmp\tr3, r4\n-\tbeq.n\t1e88 <__gridxc_array_MOD_aa_1d_3d_ip+0xf0>\n-\tldr\tr3, [pc, #156]\t@ (1f18 <__gridxc_array_MOD_aa_1d_3d_ip+0x180>)\n+\tbeq.n\t19fe <__gridxc_array_MOD_aa_1d_3d_ip+0xf2>\n+\tldr\tr3, [pc, #160]\t@ (1a90 <__gridxc_array_MOD_aa_1d_3d_ip+0x184>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #160]\t@ (1f20 <__gridxc_array_MOD_aa_1d_3d_ip+0x188>)\n+\tldr\tr0, [pc, #164]\t@ (1a98 <__gridxc_array_MOD_aa_1d_3d_ip+0x18c>)\n \tadd\tr0, pc\n \tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #16]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t1ea6 <__gridxc_array_MOD_aa_1d_3d_ip+0x10e>\n-\tldr\tr3, [pc, #132]\t@ (1f18 <__gridxc_array_MOD_aa_1d_3d_ip+0x180>)\n+\tblt.n\t1a1c <__gridxc_array_MOD_aa_1d_3d_ip+0x110>\n+\tldr\tr3, [pc, #136]\t@ (1a90 <__gridxc_array_MOD_aa_1d_3d_ip+0x184>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #140]\t@ (1f24 <__gridxc_array_MOD_aa_1d_3d_ip+0x18c>)\n+\tldr\tr0, [pc, #144]\t@ (1a9c <__gridxc_array_MOD_aa_1d_3d_ip+0x190>)\n \tadd\tr0, pc\n \tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #36\t@ 0x24\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #36\t@ 0x24\n@@ -3153,112 +2704,112 @@\n \tmla\tr2, r5, r7, lr\n \tldr\tr0, [sp, #4]\n \tadd.w\tip, ip, #1\n \tldr\tr6, [sp, #20]\n \tmla\tr2, r4, r0, r2\n \tldr.w\tr0, [fp]\n \tmla\tr2, r3, r9, r2\n-\tadd\tfp, r6\n \tadds\tr3, #1\n \tcmp\tsl, r3\n+\tadd\tfp, r6\n+\tit\tlt\n+\taddlt\tr4, #1\n \tldr.w\tr6, [r1, r2, lsl #2]\n+\tit\tlt\n+\tldrlt\tr3, [sp, #12]\n+\tcmp\tr8, r4\n \tadd\tr0, r6\n \tstr.w\tr0, [r1, r2, lsl #2]\n-\tbge.n\t1efe <__gridxc_array_MOD_aa_1d_3d_ip+0x166>\n-\tldr\tr3, [sp, #12]\n-\tadds\tr4, #1\n-\tcmp\tr8, r4\n-\tbge.n\t1f06 <__gridxc_array_MOD_aa_1d_3d_ip+0x16e>\n-\tldr\tr4, [sp, #8]\n-\tadds\tr5, #1\n \tldr\tr2, [sp, #24]\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr4, [sp, #8]\n \tcmp\tr2, ip\n-\tbne.n\t1ed0 <__gridxc_array_MOD_aa_1d_3d_ip+0x138>\n+\tbne.n\t1a46 <__gridxc_array_MOD_aa_1d_3d_ip+0x13a>\n \tldr.w\tsl, [sp, #28]\n-\tb.n\t1e5c <__gridxc_array_MOD_aa_1d_3d_ip+0xc4>\n+\tb.n\t19d2 <__gridxc_array_MOD_aa_1d_3d_ip+0xc6>\n \tnop\n-\t.word\t0x00000160\n+\t.word\t0x00000164\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000b0\n+\t.word\t0x000000b2\n R_ARM_REL32\t.LC27\n-\t.word\t0x0000009e\n+\t.word\t0x000000a0\n R_ARM_REL32\t.LC28\n-\t.word\t0x0000008a\n+\t.word\t0x0000008c\n R_ARM_REL32\t.LC29\n \n-00001f28 <__gridxc_array_MOD_aa_1d_2d_dp>:\n+00001aa0 <__gridxc_array_MOD_aa_1d_2d_dp>:\n __gridxc_array_MOD_aa_1d_2d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tsub\tsp, #12\n-\tldr\tr7, [pc, #252]\t@ (2038 <__gridxc_array_MOD_aa_1d_2d_dp+0x110>)\n+\tldr\tr7, [pc, #256]\t@ (1bb4 <__gridxc_array_MOD_aa_1d_2d_dp+0x114>)\n \tadd\tr7, pc\n \tldrd\tr8, r4, [sp, #48]\t@ 0x30\n \tldr.w\tfp, [r4, #24]\n \trsb\tip, fp, #0\n \tcmp.w\tfp, #0\n-\tbne.n\t1f58 <__gridxc_array_MOD_aa_1d_2d_dp+0x30>\n+\tbne.n\t1ad0 <__gridxc_array_MOD_aa_1d_2d_dp+0x30>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r0, #0]\n \tldr\tr0, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr\tr5, [r4, #36]\t@ 0x24\n \tcmp\tr1, #0\n \tldr.w\tlr, [r4]\n \tit\teq\n \tmoveq\tr1, #1\n \tldr\tr2, [r2, #0]\n \tldrd\tsl, r4, [r3]\n \tsub.w\tip, ip, r5\n \tcmp\tr6, r0\n-\tbgt.n\t1fcc <__gridxc_array_MOD_aa_1d_2d_dp+0xa4>\n-\tmov\tr3, fp\n+\tbgt.n\t1b44 <__gridxc_array_MOD_aa_1d_2d_dp+0xa4>\n \tldr.w\tr9, [r8]\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t1fee <__gridxc_array_MOD_aa_1d_2d_dp+0xc6>\n+\tcmpeq\tr1, #1\n+\tbne.n\t1b66 <__gridxc_array_MOD_aa_1d_2d_dp+0xc6>\n \tsubs\tr6, #1\n \tadd.w\tr0, r2, r0, lsl #3\n \tmov\tr3, sl\n \tadd.w\tr2, r2, r6, lsl #3\n \tmla\tr1, r4, r5, ip\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tcmp\tr9, r3\n \tadd.w\tr1, lr, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n-\tbge.n\t1fb6 <__gridxc_array_MOD_aa_1d_2d_dp+0x8e>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tcmp\tr0, r2\n-\tbne.n\t1f92 <__gridxc_array_MOD_aa_1d_2d_dp+0x6a>\n+\tvldr\td7, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n+\tbne.n\t1b0a <__gridxc_array_MOD_aa_1d_2d_dp+0x6a>\n \tcmp\tsl, r3\n-\tbeq.n\t1fcc <__gridxc_array_MOD_aa_1d_2d_dp+0xa4>\n-\tldr\tr3, [pc, #124]\t@ (203c <__gridxc_array_MOD_aa_1d_2d_dp+0x114>)\n+\tbeq.n\t1b44 <__gridxc_array_MOD_aa_1d_2d_dp+0xa4>\n+\tldr\tr3, [pc, #128]\t@ (1bb8 <__gridxc_array_MOD_aa_1d_2d_dp+0x118>)\n \tmovs\tr1, #25\n-\tldr\tr0, [pc, #124]\t@ (2040 <__gridxc_array_MOD_aa_1d_2d_dp+0x118>)\n+\tldr\tr0, [pc, #128]\t@ (1bbc <__gridxc_array_MOD_aa_1d_2d_dp+0x11c>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, r4\n-\tblt.n\t1fe8 <__gridxc_array_MOD_aa_1d_2d_dp+0xc0>\n-\tldr\tr3, [pc, #100]\t@ (203c <__gridxc_array_MOD_aa_1d_2d_dp+0x114>)\n+\tblt.n\t1b60 <__gridxc_array_MOD_aa_1d_2d_dp+0xc0>\n+\tldr\tr3, [pc, #104]\t@ (1bb8 <__gridxc_array_MOD_aa_1d_2d_dp+0x118>)\n \tmovs\tr1, #25\n-\tldr\tr0, [pc, #104]\t@ (2044 <__gridxc_array_MOD_aa_1d_2d_dp+0x11c>)\n+\tldr\tr0, [pc, #108]\t@ (1bc0 <__gridxc_array_MOD_aa_1d_2d_dp+0x120>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #12\n@@ -3268,108 +2819,108 @@\n \tadds\tr0, #1\n \tmul.w\tr3, r1, r3\n \tlsls\tr1, r1, #3\n \tmov\tr8, r1\n \tadd.w\tr2, r2, r3, lsl #3\n \tmov\tr3, sl\n \tmla\tr1, r4, r5, ip\n-\tvldr\td17, [r2]\n+\tvldr\td6, [r2]\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadds\tr6, #1\n-\tadd\tr2, r8\n \tcmp\tr9, r3\n+\tadd.w\tr6, r6, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tadd.w\tr1, lr, r1, lsl #3\n-\tvldr\td16, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r1]\n-\tbge.n\t202e <__gridxc_array_MOD_aa_1d_2d_dp+0x106>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\tadd\tr2, r8\n \tcmp\tr0, r6\n-\tbne.n\t2004 <__gridxc_array_MOD_aa_1d_2d_dp+0xdc>\n+\tvldr\td7, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n+\tbne.n\t1b7c <__gridxc_array_MOD_aa_1d_2d_dp+0xdc>\n \tldr.w\tr8, [sp, #4]\n-\tb.n\t1fba <__gridxc_array_MOD_aa_1d_2d_dp+0x92>\n-\t.word\t0x000000f8\n+\tb.n\t1b32 <__gridxc_array_MOD_aa_1d_2d_dp+0x92>\n+\tnop\n+\t.word\t0x000000fc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000078\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC30\n-\t.word\t0x00000066\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC31\n \n-00002048 <__gridxc_array_MOD_aa_1d_2d_sp>:\n+00001bc4 <__gridxc_array_MOD_aa_1d_2d_sp>:\n __gridxc_array_MOD_aa_1d_2d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tsub\tsp, #12\n-\tldr\tr7, [pc, #252]\t@ (2158 <__gridxc_array_MOD_aa_1d_2d_sp+0x110>)\n+\tldr\tr7, [pc, #256]\t@ (1cd8 <__gridxc_array_MOD_aa_1d_2d_sp+0x114>)\n \tadd\tr7, pc\n \tldrd\tr8, r4, [sp, #48]\t@ 0x30\n \tldr.w\tfp, [r4, #24]\n \trsb\tip, fp, #0\n \tcmp.w\tfp, #0\n-\tbne.n\t2078 <__gridxc_array_MOD_aa_1d_2d_sp+0x30>\n+\tbne.n\t1bf4 <__gridxc_array_MOD_aa_1d_2d_sp+0x30>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r0, #0]\n \tldr\tr0, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr\tr5, [r4, #36]\t@ 0x24\n \tcmp\tr1, #0\n \tldr.w\tlr, [r4]\n \tit\teq\n \tmoveq\tr1, #1\n \tldr\tr2, [r2, #0]\n \tldrd\tsl, r4, [r3]\n \tsub.w\tip, ip, r5\n \tcmp\tr6, r0\n-\tbgt.n\t20ec <__gridxc_array_MOD_aa_1d_2d_sp+0xa4>\n-\tmov\tr3, fp\n+\tbgt.n\t1c68 <__gridxc_array_MOD_aa_1d_2d_sp+0xa4>\n \tldr.w\tr9, [r8]\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t210e <__gridxc_array_MOD_aa_1d_2d_sp+0xc6>\n+\tcmpeq\tr1, #1\n+\tbne.n\t1c8a <__gridxc_array_MOD_aa_1d_2d_sp+0xc6>\n \tsubs\tr6, #1\n \tadd.w\tr0, r2, r0, lsl #2\n \tmov\tr3, sl\n \tadd.w\tr2, r2, r6, lsl #2\n \tmla\tr1, r4, r5, ip\n \tvldmia\tr2!, {s14}\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tcmp\tr9, r3\n \tadd.w\tr1, lr, r1, lsl #2\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n+\tcmp\tr0, r2\n \tvldr\ts15, [r1]\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n-\tbge.n\t20d6 <__gridxc_array_MOD_aa_1d_2d_sp+0x8e>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n-\tcmp\tr0, r2\n-\tbne.n\t20b2 <__gridxc_array_MOD_aa_1d_2d_sp+0x6a>\n+\tbne.n\t1c2e <__gridxc_array_MOD_aa_1d_2d_sp+0x6a>\n \tcmp\tsl, r3\n-\tbeq.n\t20ec <__gridxc_array_MOD_aa_1d_2d_sp+0xa4>\n-\tldr\tr3, [pc, #124]\t@ (215c <__gridxc_array_MOD_aa_1d_2d_sp+0x114>)\n+\tbeq.n\t1c68 <__gridxc_array_MOD_aa_1d_2d_sp+0xa4>\n+\tldr\tr3, [pc, #128]\t@ (1cdc <__gridxc_array_MOD_aa_1d_2d_sp+0x118>)\n \tmovs\tr1, #23\n-\tldr\tr0, [pc, #124]\t@ (2160 <__gridxc_array_MOD_aa_1d_2d_sp+0x118>)\n+\tldr\tr0, [pc, #128]\t@ (1ce0 <__gridxc_array_MOD_aa_1d_2d_sp+0x11c>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, r4\n-\tblt.n\t2108 <__gridxc_array_MOD_aa_1d_2d_sp+0xc0>\n-\tldr\tr3, [pc, #100]\t@ (215c <__gridxc_array_MOD_aa_1d_2d_sp+0x114>)\n+\tblt.n\t1c84 <__gridxc_array_MOD_aa_1d_2d_sp+0xc0>\n+\tldr\tr3, [pc, #104]\t@ (1cdc <__gridxc_array_MOD_aa_1d_2d_sp+0x118>)\n \tmovs\tr1, #23\n-\tldr\tr0, [pc, #104]\t@ (2164 <__gridxc_array_MOD_aa_1d_2d_sp+0x11c>)\n+\tldr\tr0, [pc, #108]\t@ (1ce4 <__gridxc_array_MOD_aa_1d_2d_sp+0x120>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #12\n@@ -3382,183 +2933,183 @@\n \tmov\tr8, r1\n \tadd.w\tr2, r2, r3, lsl #2\n \tmov\tr3, sl\n \tmla\tr1, r4, r5, ip\n \tvldr\ts14, [r2]\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadds\tr6, #1\n-\tadd\tr2, r8\n \tcmp\tr9, r3\n+\tadd.w\tr6, r6, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tadd.w\tr1, lr, r1, lsl #2\n+\tadd\tr2, r8\n+\tcmp\tr0, r6\n \tvldr\ts15, [r1]\n \tvadd.f32\ts15, s15, s14\n \tvstr\ts15, [r1]\n-\tbge.n\t214e <__gridxc_array_MOD_aa_1d_2d_sp+0x106>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n-\tcmp\tr0, r6\n-\tbne.n\t2124 <__gridxc_array_MOD_aa_1d_2d_sp+0xdc>\n+\tbne.n\t1ca0 <__gridxc_array_MOD_aa_1d_2d_sp+0xdc>\n \tldr.w\tr8, [sp, #4]\n-\tb.n\t20da <__gridxc_array_MOD_aa_1d_2d_sp+0x92>\n-\t.word\t0x000000f8\n+\tb.n\t1c56 <__gridxc_array_MOD_aa_1d_2d_sp+0x92>\n+\tnop\n+\t.word\t0x000000fc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000078\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC32\n-\t.word\t0x00000066\n+\t.word\t0x0000006a\n R_ARM_REL32\t.LC33\n \n-00002168 <__gridxc_array_MOD_aa_1d_2d_ip>:\n+00001ce8 <__gridxc_array_MOD_aa_1d_2d_ip>:\n __gridxc_array_MOD_aa_1d_2d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tsub\tsp, #20\n \tmov\tr5, r0\n-\tldr\tr6, [pc, #264]\t@ (2288 <__gridxc_array_MOD_aa_1d_2d_ip+0x120>)\n+\tldr\tr6, [pc, #264]\t@ (1e08 <__gridxc_array_MOD_aa_1d_2d_ip+0x120>)\n \tmov\tr4, r3\n \tldr\tr0, [sp, #60]\t@ 0x3c\n \tadd\tr6, pc\n \tldr.w\tsl, [sp, #56]\t@ 0x38\n \tldr.w\tr9, [r0, #24]\n \trsb\tip, r9, #0\n \tcmp.w\tr9, #0\n-\tbne.n\t219e <__gridxc_array_MOD_aa_1d_2d_ip+0x36>\n+\tbne.n\t1d1e <__gridxc_array_MOD_aa_1d_2d_ip+0x36>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tr9, #1\n \tldr\tr3, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr\tr7, [r5, #0]\n \tldr\tr5, [r0, #36]\t@ 0x24\n \tcmp\tr1, #0\n \tit\teq\n \tmoveq\tr1, #1\n \tldr\tr2, [r2, #0]\n-\tldr.w\tfp, [r0]\n+\tldr\tr0, [r0, #0]\n \tsub.w\tip, ip, r5\n \tldrd\tr8, r4, [r4]\n \tcmp\tr7, r3\n-\tbgt.n\t2212 <__gridxc_array_MOD_aa_1d_2d_ip+0xaa>\n-\tmov\tr0, r9\n+\tbgt.n\t1d8e <__gridxc_array_MOD_aa_1d_2d_ip+0xa6>\n \tldr.w\tlr, [sl]\n-\tcmp\tr1, #1\n+\tcmp.w\tr9, #1\n \tit\teq\n-\tcmpeq\tr0, #1\n-\tbne.n\t2234 <__gridxc_array_MOD_aa_1d_2d_ip+0xcc>\n+\tcmpeq\tr1, #1\n+\tbne.n\t1db0 <__gridxc_array_MOD_aa_1d_2d_ip+0xc8>\n \tsubs\tr7, #1\n \tadd.w\tr9, r2, r3, lsl #2\n-\tmov\tr0, fp\n+\tmov\tfp, r6\n \tmov\tr3, r8\n \tadd.w\tr2, r2, r7, lsl #2\n-\tmov\tfp, r6\n \tmla\tr1, r4, r5, ip\n \tldr.w\tr7, [r2], #4\n \tadd\tr1, r3\n \tadds\tr3, #1\n \tcmp\tlr, r3\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, r8\n \tldr.w\tr6, [r0, r1, lsl #2]\n+\tcmp\tr9, r2\n \tadd\tr7, r6\n \tstr.w\tr7, [r0, r1, lsl #2]\n-\tbge.n\t21fa <__gridxc_array_MOD_aa_1d_2d_ip+0x92>\n-\tadds\tr4, #1\n-\tmov\tr3, r8\n-\tcmp\tr9, r2\n-\tbne.n\t21dc <__gridxc_array_MOD_aa_1d_2d_ip+0x74>\n+\tbne.n\t1d58 <__gridxc_array_MOD_aa_1d_2d_ip+0x70>\n \tmov\tr6, fp\n \tcmp\tr8, r3\n-\tbeq.n\t2212 <__gridxc_array_MOD_aa_1d_2d_ip+0xaa>\n-\tldr\tr3, [pc, #132]\t@ (228c <__gridxc_array_MOD_aa_1d_2d_ip+0x124>)\n+\tbeq.n\t1d8e <__gridxc_array_MOD_aa_1d_2d_ip+0xa6>\n+\tldr\tr3, [pc, #136]\t@ (1e0c <__gridxc_array_MOD_aa_1d_2d_ip+0x124>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #132]\t@ (2290 <__gridxc_array_MOD_aa_1d_2d_ip+0x128>)\n+\tldr\tr0, [pc, #136]\t@ (1e10 <__gridxc_array_MOD_aa_1d_2d_ip+0x128>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [sl, #4]\n \tcmp\tr3, r4\n-\tblt.n\t222e <__gridxc_array_MOD_aa_1d_2d_ip+0xc6>\n-\tldr\tr3, [pc, #112]\t@ (228c <__gridxc_array_MOD_aa_1d_2d_ip+0x124>)\n+\tblt.n\t1daa <__gridxc_array_MOD_aa_1d_2d_ip+0xc2>\n+\tldr\tr3, [pc, #116]\t@ (1e0c <__gridxc_array_MOD_aa_1d_2d_ip+0x124>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #116]\t@ (2294 <__gridxc_array_MOD_aa_1d_2d_ip+0x12c>)\n+\tldr\tr0, [pc, #120]\t@ (1e14 <__gridxc_array_MOD_aa_1d_2d_ip+0x12c>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #20\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #20\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tadds\tr3, #1\n \tstr\tr3, [sp, #8]\n \tsubs\tr3, r7, #1\n-\tmov\tr0, fp\n \tstr.w\tr8, [sp, #4]\n \tstr\tr6, [sp, #12]\n \tmul.w\tr3, r1, r3\n \tlsls\tr1, r1, #2\n \tmov\tfp, r1\n \tadd.w\tr2, r2, r3, lsl #2\n \tmov\tr3, r8\n \tldr.w\tr8, [sp, #8]\n \tstr.w\tsl, [sp, #8]\n \tmov\tsl, r5\n \tmla\tr1, r4, sl, ip\n \tldr\tr5, [r2, #0]\n \tmla\tr1, r3, r9, r1\n \tadds\tr3, #1\n-\tadds\tr7, #1\n-\tadd\tr2, fp\n \tcmp\tlr, r3\n+\tadd.w\tr7, r7, #1\n+\tit\tlt\n+\taddlt\tr4, #1\n+\tadd\tr2, fp\n \tldr.w\tr6, [r0, r1, lsl #2]\n+\tit\tlt\n+\tldrlt\tr3, [sp, #4]\n+\tcmp\tr8, r7\n \tadd\tr6, r5\n \tstr.w\tr6, [r0, r1, lsl #2]\n-\tbge.n\t227c <__gridxc_array_MOD_aa_1d_2d_ip+0x114>\n-\tldr\tr3, [sp, #4]\n-\tadds\tr4, #1\n-\tcmp\tr8, r7\n-\tbne.n\t225a <__gridxc_array_MOD_aa_1d_2d_ip+0xf2>\n+\tbne.n\t1dd4 <__gridxc_array_MOD_aa_1d_2d_ip+0xec>\n \tldrd\tr8, sl, [sp, #4]\n \tldr\tr6, [sp, #12]\n-\tb.n\t2200 <__gridxc_array_MOD_aa_1d_2d_ip+0x98>\n+\tb.n\t1d7c <__gridxc_array_MOD_aa_1d_2d_ip+0x94>\n+\tnop\n \t.word\t0x00000102\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000082\n+\t.word\t0x00000086\n R_ARM_REL32\t.LC34\n-\t.word\t0x00000070\n+\t.word\t0x00000074\n R_ARM_REL32\t.LC35\n \n-00002298 <__gridxc_array_MOD_ac_4d_1d_dp>:\n+00001e18 <__gridxc_array_MOD_ac_4d_1d_dp>:\n __gridxc_array_MOD_ac_4d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3968]\t@ 0xf80\n \tsub\tsp, #92\t@ 0x5c\n \tmov\tr4, r2\n \tstrd\tr0, r1, [sp, #28]\n \tmov\tr1, r3\n \tldr\tr3, [sp, #132]\t@ 0x84\n \tldr\tr2, [sp, #128]\t@ 0x80\n \tstr\tr2, [sp, #56]\t@ 0x38\n \tldr\tr2, [r4, #24]\n \tldr\tr7, [r3, #24]\n-\tldr\tr0, [pc, #548]\t@ (24e4 <__gridxc_array_MOD_ac_4d_1d_dp+0x24c>)\n+\tldr\tr0, [pc, #548]\t@ (2064 <__gridxc_array_MOD_ac_4d_1d_dp+0x24c>)\n \tcmp\tr7, #0\n \tldr.w\tsl, [r3]\n \tadd\tr0, pc\n \tit\teq\n \tmoveq\tr7, #1\n \tnegs\tr3, r2\n \tstr\tr0, [sp, #60]\t@ 0x3c\n-\tcbnz\tr2, 22d6 <__gridxc_array_MOD_ac_4d_1d_dp+0x3e>\n+\tcbnz\tr2, 1e56 <__gridxc_array_MOD_ac_4d_1d_dp+0x3e>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr2, #1\n \tldr.w\tr9, [r1]\n \tldr\tr1, [r4, #36]\t@ 0x24\n \tldr\tr5, [sp, #28]\n \tsubs\tr3, r3, r1\n \tldr\tr6, [sp, #32]\n@@ -3569,21 +3120,21 @@\n \tldr\tr1, [r4, #0]\n \tldr\tr0, [r4, #60]\t@ 0x3c\n \tstr\tr1, [sp, #36]\t@ 0x24\n \tldr\tr4, [r5, #12]\n \tsubs\tr3, r3, r0\n \tldr\tr1, [r6, #12]\n \tcmp\tr4, r1\n-\tbgt.n\t23e0 <__gridxc_array_MOD_ac_4d_1d_dp+0x148>\n+\tbgt.n\t1f60 <__gridxc_array_MOD_ac_4d_1d_dp+0x148>\n \tldr\tr5, [r5, #8]\n-\tcmp\tr2, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n+\tcmpeq\tr2, #1\n \tldr\tr6, [r6, #8]\n-\tbne.n\t2404 <__gridxc_array_MOD_ac_4d_1d_dp+0x16c>\n+\tbne.n\t1f84 <__gridxc_array_MOD_ac_4d_1d_dp+0x16c>\n \tmla\tr2, r0, r4, r3\n \tldr\tr3, [sp, #24]\n \tmov\tr8, r6\n \tadd.w\tfp, r1, #1\n \tmul.w\tlr, r3, r5\n \tldr\tr3, [sp, #8]\n \tlsls\tr3, r3, #3\n@@ -3591,15 +3142,15 @@\n \tadds\tr3, r6, #1\n \tmov\tr6, sl\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tmov\tsl, r5\n \tmov\tr3, lr\n \tmov\tr5, r2\n \tcmp\tsl, r8\n-\tbgt.n\t23d8 <__gridxc_array_MOD_ac_4d_1d_dp+0x140>\n+\tbgt.n\t1f58 <__gridxc_array_MOD_ac_4d_1d_dp+0x140>\n \tldr\tr2, [sp, #28]\n \tadd.w\tip, r3, r5\n \tmov\tr1, sl\n \tstrd\tsl, r8, [sp, #64]\t@ 0x40\n \tstrd\tr4, r3, [sp, #72]\t@ 0x48\n \tldr.w\tlr, [r2, #4]\n \tldr\tr2, [sp, #32]\n@@ -3608,24 +3159,24 @@\n \tstr\tr2, [sp, #40]\t@ 0x28\n \tadds\tr7, r2, #1\n \tldr\tr2, [sp, #8]\n \tmul.w\tr2, r2, lr\n \tstrd\tr2, r0, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, lr\n-\tblt.n\t23be <__gridxc_array_MOD_ac_4d_1d_dp+0x126>\n+\tblt.n\t1f3e <__gridxc_array_MOD_ac_4d_1d_dp+0x126>\n \tldr\tr3, [sp, #28]\n \tmov\tr5, lr\n \tstrd\tr1, lr, [sp, #12]\n \tstr.w\tip, [sp, #20]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #32]\n \tldr.w\tsl, [r3]\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr4, fp, r3\n+\tadd.w\tr4, r3, fp\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr4, ip\n \tadd.w\tr4, r3, r4, lsl #3\n \tadd.w\tr3, sl, #1\n \tsub.w\tr8, r3, fp\n \tmov.w\tr3, r8, lsl #3\n \tstr\tr3, [sp, #0]\n@@ -3633,48 +3184,48 @@\n \tmov\tr8, r9\n \tmov\tr9, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #0]\n \tmov\tr1, r4\n \tcmp\tsl, fp\n \tadd.w\tr0, r6, r0, lsl #3\n-\tblt.n\t23aa <__gridxc_array_MOD_ac_4d_1d_dp+0x112>\n+\tblt.n\t1f2a <__gridxc_array_MOD_ac_4d_1d_dp+0x112>\n \tadd\tr8, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tcmp\tr7, r5\n \tadd\tr4, r3\n-\tbne.n\t2394 <__gridxc_array_MOD_ac_4d_1d_dp+0xfc>\n+\tbne.n\t1f14 <__gridxc_array_MOD_ac_4d_1d_dp+0xfc>\n \tldrd\tr1, lr, [sp, #12]\n \tmov\tr9, r8\n \tldr.w\tip, [sp, #20]\n \tldr\tr3, [sp, #24]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr1, r3\n-\tbne.n\t2356 <__gridxc_array_MOD_ac_4d_1d_dp+0xbe>\n+\tbne.n\t1ed6 <__gridxc_array_MOD_ac_4d_1d_dp+0xbe>\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tldrd\tsl, r8, [sp, #64]\t@ 0x40\n \tldrd\tr4, r3, [sp, #72]\t@ 0x48\n \tldrd\tr5, fp, [sp, #80]\t@ 0x50\n \tadds\tr4, #1\n \tadd\tr5, r0\n \tcmp\tr4, fp\n-\tbne.n\t2328 <__gridxc_array_MOD_ac_4d_1d_dp+0x90>\n+\tbne.n\t1ea8 <__gridxc_array_MOD_ac_4d_1d_dp+0x90>\n \tldr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, r9\n-\tblt.n\t23fe <__gridxc_array_MOD_ac_4d_1d_dp+0x166>\n-\tldr\tr3, [pc, #252]\t@ (24e8 <__gridxc_array_MOD_ac_4d_1d_dp+0x250>)\n+\tblt.n\t1f7e <__gridxc_array_MOD_ac_4d_1d_dp+0x166>\n+\tldr\tr3, [pc, #252]\t@ (2068 <__gridxc_array_MOD_ac_4d_1d_dp+0x250>)\n \tmovs\tr1, #21\n \tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #252]\t@ (24ec <__gridxc_array_MOD_ac_4d_1d_dp+0x254>)\n+\tldr\tr0, [pc, #252]\t@ (206c <__gridxc_array_MOD_ac_4d_1d_dp+0x254>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #92\t@ 0x5c\n@@ -3690,15 +3241,15 @@\n \tmul.w\tr3, r3, r5\n \tstr\tr3, [sp, #52]\t@ 0x34\n \tadds\tr3, r6, #1\n \tstrd\tr3, r2, [sp, #44]\t@ 0x2c\n \tmov\tr2, ip\n \tmov\tip, lr\n \tcmp\tr5, r6\n-\tbgt.n\t24da <__gridxc_array_MOD_ac_4d_1d_dp+0x242>\n+\tbgt.n\t205a <__gridxc_array_MOD_ac_4d_1d_dp+0x242>\n \tldr\tr3, [sp, #28]\n \tldr\tr0, [sp, #8]\n \tstr\tr5, [sp, #0]\n \tldr\tr1, [r3, #4]\n \tldr\tr3, [sp, #32]\n \tstr\tr1, [sp, #20]\n \tstrd\tr7, r5, [sp, #64]\t@ 0x40\n@@ -3711,96 +3262,96 @@\n \tstr.w\tip, [sp, #84]\t@ 0x54\n \tmla\tr1, r0, r1, r3\n \tmov\tr3, r5\n \tadd\tr1, r2\n \tldr\tr4, [sp, #20]\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tcmp\tr4, r2\n-\tbgt.n\t24c2 <__gridxc_array_MOD_ac_4d_1d_dp+0x22a>\n+\tbgt.n\t2042 <__gridxc_array_MOD_ac_4d_1d_dp+0x22a>\n \tldr\tr2, [sp, #28]\n \tmov\tr5, r1\n \tstrd\tr3, r1, [sp, #12]\n \tldr\tr6, [r2, #0]\n \tldr\tr2, [sp, #32]\n \tldr\tr7, [r2, #0]\n \tadds\tr0, r7, #1\n \tsubs\tr2, r0, r6\n \tstr\tr2, [sp, #0]\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tmul.w\tip, r6, r2\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tadd.w\tip, r2, ip, lsl #3\n \tcmp\tr6, r7\n-\tbgt.n\t24b4 <__gridxc_array_MOD_ac_4d_1d_dp+0x21c>\n+\tbgt.n\t2034 <__gridxc_array_MOD_ac_4d_1d_dp+0x21c>\n \tadd.w\tr3, r9, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #4]\n \tadd.w\tr1, ip, r5, lsl #3\n \tmul.w\tr3, sl, r3\n \tadd.w\tr3, r2, r3, lsl #3\n \tmov\tr2, r6\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr2, #1\n \tadd\tr1, r8\n \tcmp\tr2, r0\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tadd\tr3, fp\n-\tbne.n\t249e <__gridxc_array_MOD_ac_4d_1d_dp+0x206>\n+\tbne.n\t201e <__gridxc_array_MOD_ac_4d_1d_dp+0x206>\n \tldr\tr3, [sp, #0]\n \tadd\tr9, r3\n \tldr\tr3, [sp, #8]\n \tadds\tr4, #1\n \tcmp\tr4, lr\n \tadd\tr5, r3\n-\tbne.n\t2486 <__gridxc_array_MOD_ac_4d_1d_dp+0x1ee>\n+\tbne.n\t2006 <__gridxc_array_MOD_ac_4d_1d_dp+0x1ee>\n \tldrd\tr3, r1, [sp, #12]\n \tadds\tr3, #1\n \tldr\tr2, [sp, #24]\n \tadd\tr1, r2\n \tldr\tr2, [sp, #44]\t@ 0x2c\n \tcmp\tr3, r2\n-\tbne.n\t245e <__gridxc_array_MOD_ac_4d_1d_dp+0x1c6>\n+\tbne.n\t1fde <__gridxc_array_MOD_ac_4d_1d_dp+0x1c6>\n \tldrd\tr7, r5, [sp, #64]\t@ 0x40\n \tldrd\tr6, r4, [sp, #72]\t@ 0x48\n \tldrd\tr2, ip, [sp, #80]\t@ 0x50\n \tadds\tr4, #1\n \tadd\tr2, r7\n \tcmp\tr4, ip\n-\tbne.n\t242e <__gridxc_array_MOD_ac_4d_1d_dp+0x196>\n-\tb.n\t23e0 <__gridxc_array_MOD_ac_4d_1d_dp+0x148>\n+\tbne.n\t1fae <__gridxc_array_MOD_ac_4d_1d_dp+0x196>\n+\tb.n\t1f60 <__gridxc_array_MOD_ac_4d_1d_dp+0x148>\n \t.word\t0x0000021c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x000000f6\n R_ARM_REL32\t.LC36\n \n-000024f0 <__gridxc_array_MOD_ac_4d_1d_sp>:\n+00002070 <__gridxc_array_MOD_ac_4d_1d_sp>:\n __gridxc_array_MOD_ac_4d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3968]\t@ 0xf80\n \tsub\tsp, #92\t@ 0x5c\n \tmov\tr4, r2\n \tstrd\tr0, r1, [sp, #28]\n \tmov\tr1, r3\n \tldr\tr3, [sp, #132]\t@ 0x84\n \tldr\tr2, [sp, #128]\t@ 0x80\n \tstr\tr2, [sp, #56]\t@ 0x38\n \tldr\tr2, [r4, #24]\n \tldr\tr7, [r3, #24]\n-\tldr\tr0, [pc, #548]\t@ (273c <__gridxc_array_MOD_ac_4d_1d_sp+0x24c>)\n+\tldr\tr0, [pc, #548]\t@ (22bc <__gridxc_array_MOD_ac_4d_1d_sp+0x24c>)\n \tcmp\tr7, #0\n \tldr.w\tsl, [r3]\n \tadd\tr0, pc\n \tit\teq\n \tmoveq\tr7, #1\n \tnegs\tr3, r2\n \tstr\tr0, [sp, #60]\t@ 0x3c\n-\tcbnz\tr2, 252e <__gridxc_array_MOD_ac_4d_1d_sp+0x3e>\n+\tcbnz\tr2, 20ae <__gridxc_array_MOD_ac_4d_1d_sp+0x3e>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr2, #1\n \tldr.w\tr9, [r1]\n \tldr\tr1, [r4, #36]\t@ 0x24\n \tldr\tr5, [sp, #28]\n \tsubs\tr3, r3, r1\n \tldr\tr6, [sp, #32]\n@@ -3811,21 +3362,21 @@\n \tldr\tr1, [r4, #0]\n \tldr\tr0, [r4, #60]\t@ 0x3c\n \tstr\tr1, [sp, #36]\t@ 0x24\n \tldr\tr4, [r5, #12]\n \tsubs\tr3, r3, r0\n \tldr\tr1, [r6, #12]\n \tcmp\tr4, r1\n-\tbgt.n\t2638 <__gridxc_array_MOD_ac_4d_1d_sp+0x148>\n+\tbgt.n\t21b8 <__gridxc_array_MOD_ac_4d_1d_sp+0x148>\n \tldr\tr5, [r5, #8]\n-\tcmp\tr2, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n+\tcmpeq\tr2, #1\n \tldr\tr6, [r6, #8]\n-\tbne.n\t265c <__gridxc_array_MOD_ac_4d_1d_sp+0x16c>\n+\tbne.n\t21dc <__gridxc_array_MOD_ac_4d_1d_sp+0x16c>\n \tmla\tr2, r0, r4, r3\n \tldr\tr3, [sp, #24]\n \tmov\tr8, r6\n \tadd.w\tfp, r1, #1\n \tmul.w\tlr, r3, r5\n \tldr\tr3, [sp, #8]\n \tlsls\tr3, r3, #2\n@@ -3833,15 +3384,15 @@\n \tadds\tr3, r6, #1\n \tmov\tr6, sl\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tmov\tsl, r5\n \tmov\tr3, lr\n \tmov\tr5, r2\n \tcmp\tsl, r8\n-\tbgt.n\t2630 <__gridxc_array_MOD_ac_4d_1d_sp+0x140>\n+\tbgt.n\t21b0 <__gridxc_array_MOD_ac_4d_1d_sp+0x140>\n \tldr\tr2, [sp, #28]\n \tadd.w\tip, r3, r5\n \tmov\tr1, sl\n \tstrd\tsl, r8, [sp, #64]\t@ 0x40\n \tstrd\tr4, r3, [sp, #72]\t@ 0x48\n \tldr.w\tlr, [r2, #4]\n \tldr\tr2, [sp, #32]\n@@ -3850,24 +3401,24 @@\n \tstr\tr2, [sp, #40]\t@ 0x28\n \tadds\tr7, r2, #1\n \tldr\tr2, [sp, #8]\n \tmul.w\tr2, r2, lr\n \tstrd\tr2, r0, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, lr\n-\tblt.n\t2616 <__gridxc_array_MOD_ac_4d_1d_sp+0x126>\n+\tblt.n\t2196 <__gridxc_array_MOD_ac_4d_1d_sp+0x126>\n \tldr\tr3, [sp, #28]\n \tmov\tr5, lr\n \tstrd\tr1, lr, [sp, #12]\n \tstr.w\tip, [sp, #20]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #32]\n \tldr.w\tsl, [r3]\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr4, fp, r3\n+\tadd.w\tr4, r3, fp\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr4, ip\n \tadd.w\tr4, r3, r4, lsl #2\n \tadd.w\tr3, sl, #1\n \tsub.w\tr8, r3, fp\n \tmov.w\tr3, r8, lsl #2\n \tstr\tr3, [sp, #0]\n@@ -3875,48 +3426,48 @@\n \tmov\tr8, r9\n \tmov\tr9, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #0]\n \tmov\tr1, r4\n \tcmp\tsl, fp\n \tadd.w\tr0, r6, r0, lsl #2\n-\tblt.n\t2602 <__gridxc_array_MOD_ac_4d_1d_sp+0x112>\n+\tblt.n\t2182 <__gridxc_array_MOD_ac_4d_1d_sp+0x112>\n \tadd\tr8, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tcmp\tr7, r5\n \tadd\tr4, r3\n-\tbne.n\t25ec <__gridxc_array_MOD_ac_4d_1d_sp+0xfc>\n+\tbne.n\t216c <__gridxc_array_MOD_ac_4d_1d_sp+0xfc>\n \tldrd\tr1, lr, [sp, #12]\n \tmov\tr9, r8\n \tldr.w\tip, [sp, #20]\n \tldr\tr3, [sp, #24]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr1, r3\n-\tbne.n\t25ae <__gridxc_array_MOD_ac_4d_1d_sp+0xbe>\n+\tbne.n\t212e <__gridxc_array_MOD_ac_4d_1d_sp+0xbe>\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tldrd\tsl, r8, [sp, #64]\t@ 0x40\n \tldrd\tr4, r3, [sp, #72]\t@ 0x48\n \tldrd\tr5, fp, [sp, #80]\t@ 0x50\n \tadds\tr4, #1\n \tadd\tr5, r0\n \tcmp\tr4, fp\n-\tbne.n\t2580 <__gridxc_array_MOD_ac_4d_1d_sp+0x90>\n+\tbne.n\t2100 <__gridxc_array_MOD_ac_4d_1d_sp+0x90>\n \tldr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, r9\n-\tblt.n\t2656 <__gridxc_array_MOD_ac_4d_1d_sp+0x166>\n-\tldr\tr3, [pc, #252]\t@ (2740 <__gridxc_array_MOD_ac_4d_1d_sp+0x250>)\n+\tblt.n\t21d6 <__gridxc_array_MOD_ac_4d_1d_sp+0x166>\n+\tldr\tr3, [pc, #252]\t@ (22c0 <__gridxc_array_MOD_ac_4d_1d_sp+0x250>)\n \tmovs\tr1, #19\n \tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #252]\t@ (2744 <__gridxc_array_MOD_ac_4d_1d_sp+0x254>)\n+\tldr\tr0, [pc, #252]\t@ (22c4 <__gridxc_array_MOD_ac_4d_1d_sp+0x254>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #92\t@ 0x5c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #92\t@ 0x5c\n@@ -3932,15 +3483,15 @@\n \tmul.w\tr3, r3, r5\n \tstr\tr3, [sp, #52]\t@ 0x34\n \tadds\tr3, r6, #1\n \tstrd\tr3, r2, [sp, #44]\t@ 0x2c\n \tmov\tr2, ip\n \tmov\tip, lr\n \tcmp\tr5, r6\n-\tbgt.n\t2732 <__gridxc_array_MOD_ac_4d_1d_sp+0x242>\n+\tbgt.n\t22b2 <__gridxc_array_MOD_ac_4d_1d_sp+0x242>\n \tldr\tr3, [sp, #28]\n \tldr\tr0, [sp, #8]\n \tstr\tr5, [sp, #0]\n \tldr\tr1, [r3, #4]\n \tldr\tr3, [sp, #32]\n \tstr\tr1, [sp, #20]\n \tstrd\tr7, r5, [sp, #64]\t@ 0x40\n@@ -3953,96 +3504,96 @@\n \tstr.w\tip, [sp, #84]\t@ 0x54\n \tmla\tr1, r0, r1, r3\n \tmov\tr3, r5\n \tadd\tr1, r2\n \tldr\tr4, [sp, #20]\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tcmp\tr4, r2\n-\tbgt.n\t271a <__gridxc_array_MOD_ac_4d_1d_sp+0x22a>\n+\tbgt.n\t229a <__gridxc_array_MOD_ac_4d_1d_sp+0x22a>\n \tldr\tr2, [sp, #28]\n \tmov\tr5, r1\n \tstrd\tr3, r1, [sp, #12]\n \tldr\tr6, [r2, #0]\n \tldr\tr2, [sp, #32]\n \tldr\tr7, [r2, #0]\n \tadds\tr0, r7, #1\n \tsubs\tr2, r0, r6\n \tstr\tr2, [sp, #0]\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tmul.w\tip, r6, r2\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tadd.w\tip, r2, ip, lsl #2\n \tcmp\tr6, r7\n-\tbgt.n\t270c <__gridxc_array_MOD_ac_4d_1d_sp+0x21c>\n+\tbgt.n\t228c <__gridxc_array_MOD_ac_4d_1d_sp+0x21c>\n \tadd.w\tr3, r9, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #4]\n \tadd.w\tr1, ip, r5, lsl #2\n \tmul.w\tr3, sl, r3\n \tadd.w\tr3, r2, r3, lsl #2\n \tmov\tr2, r6\n \tvldr\ts15, [r1]\n \tadds\tr2, #1\n \tadd\tr1, r8\n \tcmp\tr2, r0\n \tvstr\ts15, [r3]\n \tadd\tr3, fp\n-\tbne.n\t26f6 <__gridxc_array_MOD_ac_4d_1d_sp+0x206>\n+\tbne.n\t2276 <__gridxc_array_MOD_ac_4d_1d_sp+0x206>\n \tldr\tr3, [sp, #0]\n \tadd\tr9, r3\n \tldr\tr3, [sp, #8]\n \tadds\tr4, #1\n \tcmp\tr4, lr\n \tadd\tr5, r3\n-\tbne.n\t26de <__gridxc_array_MOD_ac_4d_1d_sp+0x1ee>\n+\tbne.n\t225e <__gridxc_array_MOD_ac_4d_1d_sp+0x1ee>\n \tldrd\tr3, r1, [sp, #12]\n \tadds\tr3, #1\n \tldr\tr2, [sp, #24]\n \tadd\tr1, r2\n \tldr\tr2, [sp, #44]\t@ 0x2c\n \tcmp\tr3, r2\n-\tbne.n\t26b6 <__gridxc_array_MOD_ac_4d_1d_sp+0x1c6>\n+\tbne.n\t2236 <__gridxc_array_MOD_ac_4d_1d_sp+0x1c6>\n \tldrd\tr7, r5, [sp, #64]\t@ 0x40\n \tldrd\tr6, r4, [sp, #72]\t@ 0x48\n \tldrd\tr2, ip, [sp, #80]\t@ 0x50\n \tadds\tr4, #1\n \tadd\tr2, r7\n \tcmp\tr4, ip\n-\tbne.n\t2686 <__gridxc_array_MOD_ac_4d_1d_sp+0x196>\n-\tb.n\t2638 <__gridxc_array_MOD_ac_4d_1d_sp+0x148>\n+\tbne.n\t2206 <__gridxc_array_MOD_ac_4d_1d_sp+0x196>\n+\tb.n\t21b8 <__gridxc_array_MOD_ac_4d_1d_sp+0x148>\n \t.word\t0x0000021c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x000000f6\n R_ARM_REL32\t.LC37\n \n-00002748 <__gridxc_array_MOD_ac_4d_1d_ip>:\n+000022c8 <__gridxc_array_MOD_ac_4d_1d_ip>:\n __gridxc_array_MOD_ac_4d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3960]\t@ 0xf78\n \tsub\tsp, #100\t@ 0x64\n \tmov\tr4, r2\n \tstrd\tr0, r1, [sp, #32]\n \tmov\tr1, r3\n \tldr\tr3, [sp, #140]\t@ 0x8c\n \tldr\tr2, [sp, #136]\t@ 0x88\n \tstr\tr2, [sp, #64]\t@ 0x40\n \tldr\tr2, [r4, #24]\n \tldr\tr7, [r3, #24]\n-\tldr\tr0, [pc, #556]\t@ (299c <__gridxc_array_MOD_ac_4d_1d_ip+0x254>)\n+\tldr\tr0, [pc, #556]\t@ (251c <__gridxc_array_MOD_ac_4d_1d_ip+0x254>)\n \tcmp\tr7, #0\n \tldr.w\tsl, [r3]\n \tadd\tr0, pc\n \tit\teq\n \tmoveq\tr7, #1\n \tnegs\tr3, r2\n \tstr\tr0, [sp, #68]\t@ 0x44\n-\tcbnz\tr2, 2786 <__gridxc_array_MOD_ac_4d_1d_ip+0x3e>\n+\tcbnz\tr2, 2306 <__gridxc_array_MOD_ac_4d_1d_ip+0x3e>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr2, #1\n \tldr.w\tr9, [r1]\n \tldr\tr1, [r4, #36]\t@ 0x24\n \tldr\tr5, [sp, #32]\n \tsubs\tr3, r3, r1\n \tldr\tr6, [sp, #36]\t@ 0x24\n@@ -4053,21 +3604,21 @@\n \tldr\tr1, [r4, #0]\n \tldr\tr0, [r4, #60]\t@ 0x3c\n \tstr\tr1, [sp, #40]\t@ 0x28\n \tldr\tr4, [r5, #12]\n \tsubs\tr3, r3, r0\n \tldr\tr1, [r6, #12]\n \tcmp\tr4, r1\n-\tbgt.n\t2898 <__gridxc_array_MOD_ac_4d_1d_ip+0x150>\n+\tbgt.n\t2418 <__gridxc_array_MOD_ac_4d_1d_ip+0x150>\n \tldr\tr5, [r5, #8]\n-\tcmp\tr2, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n+\tcmpeq\tr2, #1\n \tldr\tr6, [r6, #8]\n-\tbne.w\t28bc <__gridxc_array_MOD_ac_4d_1d_ip+0x174>\n+\tbne.w\t243c <__gridxc_array_MOD_ac_4d_1d_ip+0x174>\n \tmla\tr2, r0, r4, r3\n \tldr\tr3, [sp, #28]\n \tmov\tr8, r6\n \tadd.w\tfp, r1, #1\n \tmul.w\tlr, r3, r5\n \tldr\tr3, [sp, #12]\n \tlsls\tr3, r3, #2\n@@ -4075,15 +3626,15 @@\n \tadds\tr3, r6, #1\n \tmov\tr6, sl\n \tstr\tr3, [sp, #48]\t@ 0x30\n \tmov\tsl, r5\n \tmov\tr3, lr\n \tmov\tr5, r2\n \tcmp\tsl, r8\n-\tbgt.n\t2890 <__gridxc_array_MOD_ac_4d_1d_ip+0x148>\n+\tbgt.n\t2410 <__gridxc_array_MOD_ac_4d_1d_ip+0x148>\n \tldr\tr2, [sp, #32]\n \tadd.w\tip, r3, r5\n \tmov\tr1, sl\n \tstr.w\tsl, [sp, #60]\t@ 0x3c\n \tstrd\tr8, r4, [sp, #72]\t@ 0x48\n \tldr.w\tlr, [r2, #4]\n \tldr\tr2, [sp, #36]\t@ 0x24\n@@ -4093,15 +3644,15 @@\n \tstr\tr2, [sp, #44]\t@ 0x2c\n \tadds\tr7, r2, #1\n \tldr\tr2, [sp, #12]\n \tmul.w\tr2, r2, lr\n \tstrd\tr2, r0, [sp, #52]\t@ 0x34\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr3, lr\n-\tblt.n\t2874 <__gridxc_array_MOD_ac_4d_1d_ip+0x12c>\n+\tblt.n\t23f4 <__gridxc_array_MOD_ac_4d_1d_ip+0x12c>\n \tldr\tr3, [sp, #32]\n \tmov\tr5, lr\n \tstrd\tr1, lr, [sp, #16]\n \tstr.w\tip, [sp, #24]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tldr.w\tsl, [r3]\n@@ -4118,48 +3669,48 @@\n \tmov\tr8, r9\n \tmov\tr9, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #4]\n \tmov\tr1, r4\n \tcmp\tsl, fp\n \tadd.w\tr0, r6, r0, lsl #2\n-\tblt.n\t2860 <__gridxc_array_MOD_ac_4d_1d_ip+0x118>\n+\tblt.n\t23e0 <__gridxc_array_MOD_ac_4d_1d_ip+0x118>\n \tadd\tr8, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #8]\n \tadds\tr5, #1\n \tcmp\tr7, r5\n \tadd\tr4, r3\n-\tbne.n\t284a <__gridxc_array_MOD_ac_4d_1d_ip+0x102>\n+\tbne.n\t23ca <__gridxc_array_MOD_ac_4d_1d_ip+0x102>\n \tldrd\tr1, lr, [sp, #16]\n \tmov\tr9, r8\n \tldr.w\tip, [sp, #24]\n \tldr\tr3, [sp, #28]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr1, r3\n-\tbne.n\t280c <__gridxc_array_MOD_ac_4d_1d_ip+0xc4>\n+\tbne.n\t238c <__gridxc_array_MOD_ac_4d_1d_ip+0xc4>\n \tldrd\tr0, sl, [sp, #56]\t@ 0x38\n \tldrd\tr8, r4, [sp, #72]\t@ 0x48\n \tldrd\tr3, r5, [sp, #80]\t@ 0x50\n \tldr.w\tfp, [sp, #88]\t@ 0x58\n \tadds\tr4, #1\n \tadd\tr5, r0\n \tcmp\tr4, fp\n-\tbne.n\t27da <__gridxc_array_MOD_ac_4d_1d_ip+0x92>\n+\tbne.n\t235a <__gridxc_array_MOD_ac_4d_1d_ip+0x92>\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, r9\n-\tblt.n\t28b6 <__gridxc_array_MOD_ac_4d_1d_ip+0x16e>\n-\tldr\tr3, [pc, #252]\t@ (29a0 <__gridxc_array_MOD_ac_4d_1d_ip+0x258>)\n+\tblt.n\t2436 <__gridxc_array_MOD_ac_4d_1d_ip+0x16e>\n+\tldr\tr3, [pc, #252]\t@ (2520 <__gridxc_array_MOD_ac_4d_1d_ip+0x258>)\n \tmovs\tr1, #22\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr0, [pc, #252]\t@ (29a4 <__gridxc_array_MOD_ac_4d_1d_ip+0x25c>)\n+\tldr\tr0, [pc, #252]\t@ (2524 <__gridxc_array_MOD_ac_4d_1d_ip+0x25c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #100\t@ 0x64\n@@ -4175,15 +3726,15 @@\n \tmul.w\tr3, r3, r5\n \tstr\tr3, [sp, #60]\t@ 0x3c\n \tadds\tr3, r6, #1\n \tstrd\tr3, r2, [sp, #52]\t@ 0x34\n \tmov\tr2, ip\n \tmov\tip, lr\n \tcmp\tr5, r6\n-\tbgt.n\t2992 <__gridxc_array_MOD_ac_4d_1d_ip+0x24a>\n+\tbgt.n\t2512 <__gridxc_array_MOD_ac_4d_1d_ip+0x24a>\n \tldr\tr3, [sp, #32]\n \tldr\tr0, [sp, #12]\n \tstr\tr5, [sp, #4]\n \tldr\tr1, [r3, #4]\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr1, [sp, #44]\t@ 0x2c\n \tstrd\tr7, r5, [sp, #72]\t@ 0x48\n@@ -4195,96 +3746,97 @@\n \tstrd\tr4, r2, [sp, #84]\t@ 0x54\n \tstr.w\tip, [sp, #92]\t@ 0x5c\n \tmla\tr1, r0, r1, r3\n \tmov\tr3, r5\n \tadd\tr1, r2\n \tldrd\tr4, r2, [sp, #44]\t@ 0x2c\n \tcmp\tr4, r2\n-\tbgt.n\t297a <__gridxc_array_MOD_ac_4d_1d_ip+0x232>\n+\tbgt.n\t24fa <__gridxc_array_MOD_ac_4d_1d_ip+0x232>\n \tldr\tr2, [sp, #32]\n \tmov\tr5, r1\n \tstrd\tr3, r1, [sp, #20]\n \tldr\tr6, [r2, #0]\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tldr\tr7, [r2, #0]\n \tadds\tr0, r7, #1\n \tsubs\tr2, r0, r6\n \tstr\tr2, [sp, #8]\n \tldr\tr2, [sp, #56]\t@ 0x38\n \tmul.w\tip, r6, r2\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tadd.w\tip, r2, ip, lsl #2\n \tcmp\tr6, r7\n-\tbgt.n\t296c <__gridxc_array_MOD_ac_4d_1d_ip+0x224>\n+\tbgt.n\t24ec <__gridxc_array_MOD_ac_4d_1d_ip+0x224>\n \tadd.w\tr3, r9, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #16]\n \tadd.w\tr1, ip, r5, lsl #2\n \tstr\tr4, [sp, #4]\n \tmul.w\tr3, sl, r3\n \tadd.w\tr3, r2, r3, lsl #2\n \tmov\tr2, r6\n \tldr\tr4, [r1, #0]\n \tadds\tr2, #1\n \tstr\tr4, [r3, #0]\n \tadd\tr1, r8\n \tadd\tr3, fp\n \tcmp\tr2, r0\n-\tbne.n\t2958 <__gridxc_array_MOD_ac_4d_1d_ip+0x210>\n+\tbne.n\t24d8 <__gridxc_array_MOD_ac_4d_1d_ip+0x210>\n \tldrd\tr4, r3, [sp, #4]\n \tadd\tr9, r3\n \tldr\tr3, [sp, #12]\n \tadds\tr4, #1\n \tcmp\tr4, lr\n \tadd\tr5, r3\n-\tbne.n\t293e <__gridxc_array_MOD_ac_4d_1d_ip+0x1f6>\n+\tbne.n\t24be <__gridxc_array_MOD_ac_4d_1d_ip+0x1f6>\n \tldrd\tr3, r1, [sp, #20]\n \tadds\tr3, #1\n \tldr\tr2, [sp, #28]\n \tadd\tr1, r2\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tcmp\tr3, r2\n-\tbne.n\t2916 <__gridxc_array_MOD_ac_4d_1d_ip+0x1ce>\n+\tbne.n\t2496 <__gridxc_array_MOD_ac_4d_1d_ip+0x1ce>\n \tldrd\tr7, r5, [sp, #72]\t@ 0x48\n \tldrd\tr6, r4, [sp, #80]\t@ 0x50\n \tldrd\tr2, ip, [sp, #88]\t@ 0x58\n \tadds\tr4, #1\n \tadd\tr2, r7\n \tcmp\tr4, ip\n-\tbne.n\t28e6 <__gridxc_array_MOD_ac_4d_1d_ip+0x19e>\n-\tb.n\t2898 <__gridxc_array_MOD_ac_4d_1d_ip+0x150>\n+\tbne.n\t2466 <__gridxc_array_MOD_ac_4d_1d_ip+0x19e>\n+\tb.n\t2418 <__gridxc_array_MOD_ac_4d_1d_ip+0x150>\n \t.word\t0x00000224\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x000000f6\n R_ARM_REL32\t.LC38\n \n-000029a8 <__gridxc_array_MOD_ac_3d_1d_dp>:\n+00002528 <__gridxc_array_MOD_ac_3d_1d_dp>:\n __gridxc_array_MOD_ac_3d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #68\t@ 0x44\n \tmov\tr7, r2\n-\tldr\tr6, [pc, #436]\t@ (2b74 <__gridxc_array_MOD_ac_3d_1d_dp+0x1cc>)\n+\tldr\tr6, [pc, #436]\t@ (26f4 <__gridxc_array_MOD_ac_3d_1d_dp+0x1cc>)\n \tldr\tr2, [sp, #108]\t@ 0x6c\n \tadd\tr6, pc\n \tstrd\tr1, r0, [sp, #32]\n \tmov\tr1, r3\n \tldr\tr3, [r7, #24]\n \tldr\tr0, [r2, #24]\n \tldr\tr5, [r2, #0]\n-\tnegs\tr2, r3\n \tcmp\tr0, #0\n \tldr.w\tr8, [sp, #104]\t@ 0x68\n-\tit\teq\n-\tmoveq\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tcbnz\tr3, 29e4 <__gridxc_array_MOD_ac_3d_1d_dp+0x3c>\n+\tite\tne\n+\tmovne\tr2, r0\n+\tmoveq\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tnegs\tr2, r3\n+\tcbnz\tr3, 2566 <__gridxc_array_MOD_ac_3d_1d_dp+0x3e>\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n \tmovs\tr3, #1\n \tldr\tr0, [r7, #0]\n \tldr.w\tfp, [r7, #36]\t@ 0x24\n \tldr\tr4, [r1, #0]\n \tstr\tr0, [sp, #40]\t@ 0x28\n \tsub.w\tr2, r2, fp\n@@ -4292,25 +3844,25 @@\n \tldr\tr0, [sp, #32]\n \tldr\tr7, [sp, #36]\t@ 0x24\n \tsubs\tr2, r2, r1\n \tstr\tr1, [sp, #20]\n \tldr\tr0, [r0, #8]\n \tldr\tr1, [r7, #8]\n \tcmp\tr1, r0\n-\tbgt.n\t2aac <__gridxc_array_MOD_ac_3d_1d_dp+0x104>\n+\tbgt.n\t262e <__gridxc_array_MOD_ac_3d_1d_dp+0x106>\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #24]\n \tldr\tr7, [sp, #32]\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #28]\n \tldr\tr7, [sp, #8]\n-\tcmp\tr3, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n-\tbne.n\t2ace <__gridxc_array_MOD_ac_3d_1d_dp+0x126>\n+\tcmpeq\tr3, #1\n+\tbne.n\t2650 <__gridxc_array_MOD_ac_3d_1d_dp+0x128>\n \tldr\tr3, [sp, #20]\n \tmov.w\tr9, fp, lsl #3\n \tstrd\tr8, r6, [sp, #52]\t@ 0x34\n \tmla\tr2, r3, r1, r2\n \tadds\tr3, r0, #1\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #24]\n@@ -4318,22 +3870,22 @@\n \tmul.w\tr3, fp, r3\n \tstr\tr3, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #28]\n \tadds\tr3, #1\n \tstr\tr3, [sp, #8]\n \tldrd\tr7, r3, [sp, #24]\n \tcmp\tr7, r3\n-\tbgt.n\t2a9c <__gridxc_array_MOD_ac_3d_1d_dp+0xf4>\n+\tbgt.n\t261e <__gridxc_array_MOD_ac_3d_1d_dp+0xf6>\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstrd\tip, r1, [sp, #12]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #32]\n \tldr.w\tsl, [r3]\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr6, fp, r3\n+\tadd.w\tr6, r3, fp\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tadd\tr6, ip\n \tadd.w\tr6, r3, r6, lsl #3\n \tadd.w\tr3, sl, #1\n \tsub.w\tr8, r3, fp\n \tmov.w\tr3, r8, lsl #3\n \tstr\tr3, [sp, #4]\n@@ -4341,39 +3893,39 @@\n \tmov\tr8, r4\n \tmov\tr4, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #4]\n \tmov\tr1, r6\n \tcmp\tsl, fp\n \tadd.w\tr0, r5, r0, lsl #3\n-\tblt.n\t2a8a <__gridxc_array_MOD_ac_3d_1d_dp+0xe2>\n+\tblt.n\t260c <__gridxc_array_MOD_ac_3d_1d_dp+0xe4>\n \tadd\tr8, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #8]\n \tadds\tr7, #1\n \tadd\tr6, r9\n \tcmp\tr3, r7\n-\tbne.n\t2a74 <__gridxc_array_MOD_ac_3d_1d_dp+0xcc>\n+\tbne.n\t25f6 <__gridxc_array_MOD_ac_3d_1d_dp+0xce>\n \tldr.w\tip, [sp, #12]\n \tmov\tr4, r8\n \tldr\tr1, [sp, #16]\n \tldr\tr3, [sp, #20]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr1, r3\n-\tbne.n\t2a3a <__gridxc_array_MOD_ac_3d_1d_dp+0x92>\n+\tbne.n\t25bc <__gridxc_array_MOD_ac_3d_1d_dp+0x94>\n \tldrd\tr8, r6, [sp, #52]\t@ 0x34\n \tldr.w\tr3, [r8]\n \tcmp\tr3, r4\n-\tblt.n\t2ac8 <__gridxc_array_MOD_ac_3d_1d_dp+0x120>\n-\tldr\tr3, [pc, #192]\t@ (2b78 <__gridxc_array_MOD_ac_3d_1d_dp+0x1d0>)\n+\tblt.n\t264a <__gridxc_array_MOD_ac_3d_1d_dp+0x122>\n+\tldr\tr3, [pc, #192]\t@ (26f8 <__gridxc_array_MOD_ac_3d_1d_dp+0x1d0>)\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #192]\t@ (2b7c <__gridxc_array_MOD_ac_3d_1d_dp+0x1d4>)\n+\tldr\tr0, [pc, #192]\t@ (26fc <__gridxc_array_MOD_ac_3d_1d_dp+0x1d4>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #68\t@ 0x44\n@@ -4393,15 +3945,15 @@\n \tmov\tr3, r2\n \tmov.w\tip, r0, lsl #3\n \tldr\tr0, [sp, #28]\n \tadds\tr0, #1\n \tstr\tr0, [sp, #4]\n \tldrd\tr5, r2, [sp, #24]\n \tcmp\tr5, r2\n-\tbgt.n\t2b60 <__gridxc_array_MOD_ac_3d_1d_dp+0x1b8>\n+\tbgt.n\t26e2 <__gridxc_array_MOD_ac_3d_1d_dp+0x1ba>\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tmov\tr6, r3\n \tstr\tr1, [sp, #16]\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr7, [r2, #0]\n \tldr\tr2, [sp, #32]\n \tldr.w\tr8, [r2]\n@@ -4409,76 +3961,76 @@\n \tsubs\tr2, r0, r7\n \tstr\tr2, [sp, #12]\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tmul.w\tr9, r7, r2\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tadd.w\tr9, r2, r9, lsl #3\n \tcmp\tr7, r8\n-\tbgt.n\t2b52 <__gridxc_array_MOD_ac_3d_1d_dp+0x1aa>\n+\tbgt.n\t26d4 <__gridxc_array_MOD_ac_3d_1d_dp+0x1ac>\n \tldr\tr2, [sp, #8]\n \tsubs\tr3, r4, #1\n \tadd.w\tr1, r9, r6, lsl #3\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r7\n \tadd.w\tr3, sl, r3, lsl #3\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr2, #1\n \tadd\tr1, lr\n \tcmp\tr2, r0\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tadd\tr3, ip\n-\tbne.n\t2b3c <__gridxc_array_MOD_ac_3d_1d_dp+0x194>\n+\tbne.n\t26be <__gridxc_array_MOD_ac_3d_1d_dp+0x196>\n \tldr\tr3, [sp, #12]\n \tadd\tr4, r3\n \tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tadd\tr6, fp\n \tcmp\tr5, r3\n-\tbne.n\t2b26 <__gridxc_array_MOD_ac_3d_1d_dp+0x17e>\n+\tbne.n\t26a8 <__gridxc_array_MOD_ac_3d_1d_dp+0x180>\n \tldr\tr1, [sp, #16]\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr2, [sp, #20]\n \tadds\tr1, #1\n \tadd\tr3, r2\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr1, r2\n-\tbne.n\t2afa <__gridxc_array_MOD_ac_3d_1d_dp+0x152>\n+\tbne.n\t267c <__gridxc_array_MOD_ac_3d_1d_dp+0x154>\n \tldrd\tr8, r6, [sp, #56]\t@ 0x38\n-\tb.n\t2aac <__gridxc_array_MOD_ac_3d_1d_dp+0x104>\n-\tnop\n+\tb.n\t262e <__gridxc_array_MOD_ac_3d_1d_dp+0x106>\n \t.word\t0x000001b0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000be\n+\t.word\t0x000000bc\n R_ARM_REL32\t.LC39\n \n-00002b80 <__gridxc_array_MOD_ac_3d_1d_sp>:\n+00002700 <__gridxc_array_MOD_ac_3d_1d_sp>:\n __gridxc_array_MOD_ac_3d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #68\t@ 0x44\n \tmov\tr7, r2\n-\tldr\tr6, [pc, #436]\t@ (2d4c <__gridxc_array_MOD_ac_3d_1d_sp+0x1cc>)\n+\tldr\tr6, [pc, #436]\t@ (28cc <__gridxc_array_MOD_ac_3d_1d_sp+0x1cc>)\n \tldr\tr2, [sp, #108]\t@ 0x6c\n \tadd\tr6, pc\n \tstrd\tr1, r0, [sp, #32]\n \tmov\tr1, r3\n \tldr\tr3, [r7, #24]\n \tldr\tr0, [r2, #24]\n \tldr\tr5, [r2, #0]\n-\tnegs\tr2, r3\n \tcmp\tr0, #0\n \tldr.w\tr8, [sp, #104]\t@ 0x68\n-\tit\teq\n-\tmoveq\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tcbnz\tr3, 2bbc <__gridxc_array_MOD_ac_3d_1d_sp+0x3c>\n+\tite\tne\n+\tmovne\tr2, r0\n+\tmoveq\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tnegs\tr2, r3\n+\tcbnz\tr3, 273e <__gridxc_array_MOD_ac_3d_1d_sp+0x3e>\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n \tmovs\tr3, #1\n \tldr\tr0, [r7, #0]\n \tldr.w\tfp, [r7, #36]\t@ 0x24\n \tldr\tr4, [r1, #0]\n \tstr\tr0, [sp, #40]\t@ 0x28\n \tsub.w\tr2, r2, fp\n@@ -4486,25 +4038,25 @@\n \tldr\tr0, [sp, #32]\n \tldr\tr7, [sp, #36]\t@ 0x24\n \tsubs\tr2, r2, r1\n \tstr\tr1, [sp, #20]\n \tldr\tr0, [r0, #8]\n \tldr\tr1, [r7, #8]\n \tcmp\tr1, r0\n-\tbgt.n\t2c84 <__gridxc_array_MOD_ac_3d_1d_sp+0x104>\n+\tbgt.n\t2806 <__gridxc_array_MOD_ac_3d_1d_sp+0x106>\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #24]\n \tldr\tr7, [sp, #32]\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #28]\n \tldr\tr7, [sp, #8]\n-\tcmp\tr3, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n-\tbne.n\t2ca6 <__gridxc_array_MOD_ac_3d_1d_sp+0x126>\n+\tcmpeq\tr3, #1\n+\tbne.n\t2828 <__gridxc_array_MOD_ac_3d_1d_sp+0x128>\n \tldr\tr3, [sp, #20]\n \tmov.w\tr9, fp, lsl #2\n \tstrd\tr8, r6, [sp, #52]\t@ 0x34\n \tmla\tr2, r3, r1, r2\n \tadds\tr3, r0, #1\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #24]\n@@ -4512,22 +4064,22 @@\n \tmul.w\tr3, fp, r3\n \tstr\tr3, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #28]\n \tadds\tr3, #1\n \tstr\tr3, [sp, #8]\n \tldrd\tr7, r3, [sp, #24]\n \tcmp\tr7, r3\n-\tbgt.n\t2c74 <__gridxc_array_MOD_ac_3d_1d_sp+0xf4>\n+\tbgt.n\t27f6 <__gridxc_array_MOD_ac_3d_1d_sp+0xf6>\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstrd\tip, r1, [sp, #12]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #32]\n \tldr.w\tsl, [r3]\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr6, fp, r3\n+\tadd.w\tr6, r3, fp\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tadd\tr6, ip\n \tadd.w\tr6, r3, r6, lsl #2\n \tadd.w\tr3, sl, #1\n \tsub.w\tr8, r3, fp\n \tmov.w\tr3, r8, lsl #2\n \tstr\tr3, [sp, #4]\n@@ -4535,39 +4087,39 @@\n \tmov\tr8, r4\n \tmov\tr4, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #4]\n \tmov\tr1, r6\n \tcmp\tsl, fp\n \tadd.w\tr0, r5, r0, lsl #2\n-\tblt.n\t2c62 <__gridxc_array_MOD_ac_3d_1d_sp+0xe2>\n+\tblt.n\t27e4 <__gridxc_array_MOD_ac_3d_1d_sp+0xe4>\n \tadd\tr8, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #8]\n \tadds\tr7, #1\n \tadd\tr6, r9\n \tcmp\tr3, r7\n-\tbne.n\t2c4c <__gridxc_array_MOD_ac_3d_1d_sp+0xcc>\n+\tbne.n\t27ce <__gridxc_array_MOD_ac_3d_1d_sp+0xce>\n \tldr.w\tip, [sp, #12]\n \tmov\tr4, r8\n \tldr\tr1, [sp, #16]\n \tldr\tr3, [sp, #20]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr1, r3\n-\tbne.n\t2c12 <__gridxc_array_MOD_ac_3d_1d_sp+0x92>\n+\tbne.n\t2794 <__gridxc_array_MOD_ac_3d_1d_sp+0x94>\n \tldrd\tr8, r6, [sp, #52]\t@ 0x34\n \tldr.w\tr3, [r8]\n \tcmp\tr3, r4\n-\tblt.n\t2ca0 <__gridxc_array_MOD_ac_3d_1d_sp+0x120>\n-\tldr\tr3, [pc, #192]\t@ (2d50 <__gridxc_array_MOD_ac_3d_1d_sp+0x1d0>)\n+\tblt.n\t2822 <__gridxc_array_MOD_ac_3d_1d_sp+0x122>\n+\tldr\tr3, [pc, #192]\t@ (28d0 <__gridxc_array_MOD_ac_3d_1d_sp+0x1d0>)\n \tmovs\tr1, #19\n-\tldr\tr0, [pc, #192]\t@ (2d54 <__gridxc_array_MOD_ac_3d_1d_sp+0x1d4>)\n+\tldr\tr0, [pc, #192]\t@ (28d4 <__gridxc_array_MOD_ac_3d_1d_sp+0x1d4>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #68\t@ 0x44\n@@ -4587,15 +4139,15 @@\n \tmov\tr3, r2\n \tmov.w\tip, r0, lsl #2\n \tldr\tr0, [sp, #28]\n \tadds\tr0, #1\n \tstr\tr0, [sp, #4]\n \tldrd\tr5, r2, [sp, #24]\n \tcmp\tr5, r2\n-\tbgt.n\t2d38 <__gridxc_array_MOD_ac_3d_1d_sp+0x1b8>\n+\tbgt.n\t28ba <__gridxc_array_MOD_ac_3d_1d_sp+0x1ba>\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tmov\tr6, r3\n \tstr\tr1, [sp, #16]\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr7, [r2, #0]\n \tldr\tr2, [sp, #32]\n \tldr.w\tr8, [r2]\n@@ -4603,76 +4155,76 @@\n \tsubs\tr2, r0, r7\n \tstr\tr2, [sp, #12]\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tmul.w\tr9, r7, r2\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tadd.w\tr9, r2, r9, lsl #2\n \tcmp\tr7, r8\n-\tbgt.n\t2d2a <__gridxc_array_MOD_ac_3d_1d_sp+0x1aa>\n+\tbgt.n\t28ac <__gridxc_array_MOD_ac_3d_1d_sp+0x1ac>\n \tldr\tr2, [sp, #8]\n \tsubs\tr3, r4, #1\n \tadd.w\tr1, r9, r6, lsl #2\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r7\n \tadd.w\tr3, sl, r3, lsl #2\n \tvldr\ts15, [r1]\n \tadds\tr2, #1\n \tadd\tr1, lr\n \tcmp\tr2, r0\n \tvstr\ts15, [r3]\n \tadd\tr3, ip\n-\tbne.n\t2d14 <__gridxc_array_MOD_ac_3d_1d_sp+0x194>\n+\tbne.n\t2896 <__gridxc_array_MOD_ac_3d_1d_sp+0x196>\n \tldr\tr3, [sp, #12]\n \tadd\tr4, r3\n \tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tadd\tr6, fp\n \tcmp\tr5, r3\n-\tbne.n\t2cfe <__gridxc_array_MOD_ac_3d_1d_sp+0x17e>\n+\tbne.n\t2880 <__gridxc_array_MOD_ac_3d_1d_sp+0x180>\n \tldr\tr1, [sp, #16]\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr2, [sp, #20]\n \tadds\tr1, #1\n \tadd\tr3, r2\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr1, r2\n-\tbne.n\t2cd2 <__gridxc_array_MOD_ac_3d_1d_sp+0x152>\n+\tbne.n\t2854 <__gridxc_array_MOD_ac_3d_1d_sp+0x154>\n \tldrd\tr8, r6, [sp, #56]\t@ 0x38\n-\tb.n\t2c84 <__gridxc_array_MOD_ac_3d_1d_sp+0x104>\n-\tnop\n+\tb.n\t2806 <__gridxc_array_MOD_ac_3d_1d_sp+0x106>\n \t.word\t0x000001b0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000be\n+\t.word\t0x000000bc\n R_ARM_REL32\t.LC40\n \n-00002d58 <__gridxc_array_MOD_ac_3d_1d_ip>:\n+000028d8 <__gridxc_array_MOD_ac_3d_1d_ip>:\n __gridxc_array_MOD_ac_3d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #68\t@ 0x44\n \tmov\tr7, r2\n-\tldr\tr6, [pc, #436]\t@ (2f24 <__gridxc_array_MOD_ac_3d_1d_ip+0x1cc>)\n+\tldr\tr6, [pc, #436]\t@ (2aa4 <__gridxc_array_MOD_ac_3d_1d_ip+0x1cc>)\n \tldr\tr2, [sp, #108]\t@ 0x6c\n \tadd\tr6, pc\n \tstrd\tr1, r0, [sp, #28]\n \tmov\tr1, r3\n \tldr\tr3, [r7, #24]\n \tldr\tr0, [r2, #24]\n \tldr\tr5, [r2, #0]\n-\tnegs\tr2, r3\n \tcmp\tr0, #0\n \tldr.w\tr8, [sp, #104]\t@ 0x68\n-\tit\teq\n-\tmoveq\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tcbnz\tr3, 2d94 <__gridxc_array_MOD_ac_3d_1d_ip+0x3c>\n+\tite\tne\n+\tmovne\tr2, r0\n+\tmoveq\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tnegs\tr2, r3\n+\tcbnz\tr3, 2916 <__gridxc_array_MOD_ac_3d_1d_ip+0x3e>\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n \tmovs\tr3, #1\n \tldr\tr0, [r7, #0]\n \tldr.w\tfp, [r7, #36]\t@ 0x24\n \tldr\tr4, [r1, #0]\n \tstr\tr0, [sp, #36]\t@ 0x24\n \tsub.w\tr2, r2, fp\n@@ -4680,25 +4232,25 @@\n \tldr\tr0, [sp, #28]\n \tldr\tr7, [sp, #32]\n \tsubs\tr2, r2, r1\n \tstr\tr1, [sp, #16]\n \tldr\tr0, [r0, #8]\n \tldr\tr1, [r7, #8]\n \tcmp\tr1, r0\n-\tbgt.n\t2e5c <__gridxc_array_MOD_ac_3d_1d_ip+0x104>\n+\tbgt.n\t29de <__gridxc_array_MOD_ac_3d_1d_ip+0x106>\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #20]\n \tldr\tr7, [sp, #28]\n \tldr\tr7, [r7, #4]\n \tstr\tr7, [sp, #24]\n \tldr\tr7, [sp, #8]\n-\tcmp\tr3, #1\n+\tcmp\tr7, #1\n \tit\teq\n-\tcmpeq\tr7, #1\n-\tbne.n\t2e7e <__gridxc_array_MOD_ac_3d_1d_ip+0x126>\n+\tcmpeq\tr3, #1\n+\tbne.n\t2a00 <__gridxc_array_MOD_ac_3d_1d_ip+0x128>\n \tldr\tr3, [sp, #16]\n \tmov.w\tr9, fp, lsl #2\n \tstrd\tr8, r6, [sp, #48]\t@ 0x30\n \tmla\tr2, r3, r1, r2\n \tadds\tr3, r0, #1\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #20]\n@@ -4706,15 +4258,15 @@\n \tmul.w\tr3, fp, r3\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #24]\n \tadds\tr3, #1\n \tstr\tr3, [sp, #4]\n \tldrd\tr7, r3, [sp, #20]\n \tcmp\tr7, r3\n-\tbgt.n\t2e4c <__gridxc_array_MOD_ac_3d_1d_ip+0xf4>\n+\tbgt.n\t29ce <__gridxc_array_MOD_ac_3d_1d_ip+0xf6>\n \tldr\tr3, [sp, #32]\n \tstrd\tip, r1, [sp, #8]\n \tldr.w\tfp, [r3]\n \tldr\tr3, [sp, #28]\n \tldr.w\tsl, [r3]\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tadd.w\tr6, fp, r3\n@@ -4729,39 +4281,39 @@\n \tmov\tr8, r4\n \tmov\tr4, r3\n \tadd.w\tr0, r8, #4294967295\t@ 0xffffffff\n \tldr\tr2, [sp, #0]\n \tmov\tr1, r6\n \tcmp\tsl, fp\n \tadd.w\tr0, r5, r0, lsl #2\n-\tblt.n\t2e3a <__gridxc_array_MOD_ac_3d_1d_ip+0xe2>\n+\tblt.n\t29bc <__gridxc_array_MOD_ac_3d_1d_ip+0xe4>\n \tadd\tr8, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [sp, #4]\n \tadds\tr7, #1\n \tadd\tr6, r9\n \tcmp\tr3, r7\n-\tbne.n\t2e24 <__gridxc_array_MOD_ac_3d_1d_ip+0xcc>\n+\tbne.n\t29a6 <__gridxc_array_MOD_ac_3d_1d_ip+0xce>\n \tldr.w\tip, [sp, #8]\n \tmov\tr4, r8\n \tldr\tr1, [sp, #12]\n \tldr\tr3, [sp, #16]\n \tadds\tr1, #1\n \tadd\tip, r3\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr1, r3\n-\tbne.n\t2dea <__gridxc_array_MOD_ac_3d_1d_ip+0x92>\n+\tbne.n\t296c <__gridxc_array_MOD_ac_3d_1d_ip+0x94>\n \tldrd\tr8, r6, [sp, #48]\t@ 0x30\n \tldr.w\tr3, [r8]\n \tcmp\tr3, r4\n-\tblt.n\t2e78 <__gridxc_array_MOD_ac_3d_1d_ip+0x120>\n-\tldr\tr3, [pc, #192]\t@ (2f28 <__gridxc_array_MOD_ac_3d_1d_ip+0x1d0>)\n+\tblt.n\t29fa <__gridxc_array_MOD_ac_3d_1d_ip+0x122>\n+\tldr\tr3, [pc, #192]\t@ (2aa8 <__gridxc_array_MOD_ac_3d_1d_ip+0x1d0>)\n \tmovs\tr1, #22\n-\tldr\tr0, [pc, #192]\t@ (2f2c <__gridxc_array_MOD_ac_3d_1d_ip+0x1d4>)\n+\tldr\tr0, [pc, #192]\t@ (2aac <__gridxc_array_MOD_ac_3d_1d_ip+0x1d4>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #68\t@ 0x44\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #68\t@ 0x44\n@@ -4781,118 +4333,113 @@\n \tmov\tr3, r2\n \tmov.w\tip, r0, lsl #2\n \tldr\tr0, [sp, #24]\n \tadds\tr0, #1\n \tstr\tr0, [sp, #4]\n \tldrd\tr5, r2, [sp, #20]\n \tcmp\tr5, r2\n-\tbgt.n\t2f10 <__gridxc_array_MOD_ac_3d_1d_ip+0x1b8>\n+\tbgt.n\t2a92 <__gridxc_array_MOD_ac_3d_1d_ip+0x1ba>\n \tldr\tr2, [sp, #32]\n \tmov\tr6, r3\n \tstrd\tr1, r3, [sp, #40]\t@ 0x28\n \tldr\tr7, [r2, #0]\n \tldr\tr2, [sp, #28]\n \tldr.w\tr8, [r2]\n \tadd.w\tr0, r8, #1\n \tsubs\tr2, r0, r7\n \tstr\tr2, [sp, #12]\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tmul.w\tr9, r7, r2\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tadd.w\tr9, r2, r9, lsl #2\n \tcmp\tr7, r8\n-\tbgt.n\t2f02 <__gridxc_array_MOD_ac_3d_1d_ip+0x1aa>\n+\tbgt.n\t2a84 <__gridxc_array_MOD_ac_3d_1d_ip+0x1ac>\n \tldr\tr2, [sp, #8]\n \tsubs\tr3, r4, #1\n \tadd.w\tr1, r9, r6, lsl #2\n \tstr\tr4, [sp, #0]\n \tmul.w\tr3, r2, r3\n \tmov\tr2, r7\n \tadd.w\tr3, sl, r3, lsl #2\n \tldr\tr4, [r1, #0]\n \tadds\tr2, #1\n \tstr\tr4, [r3, #0]\n \tadd\tr1, lr\n \tadd\tr3, ip\n \tcmp\tr2, r0\n-\tbne.n\t2eee <__gridxc_array_MOD_ac_3d_1d_ip+0x196>\n+\tbne.n\t2a70 <__gridxc_array_MOD_ac_3d_1d_ip+0x198>\n \tldr\tr4, [sp, #0]\n \tldr\tr3, [sp, #12]\n \tadd\tr4, r3\n \tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tadd\tr6, fp\n \tcmp\tr5, r3\n-\tbne.n\t2ed6 <__gridxc_array_MOD_ac_3d_1d_ip+0x17e>\n+\tbne.n\t2a58 <__gridxc_array_MOD_ac_3d_1d_ip+0x180>\n \tldrd\tr1, r3, [sp, #40]\t@ 0x28\n \tadds\tr1, #1\n \tldr\tr2, [sp, #16]\n \tadd\tr3, r2\n \tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr1, r2\n-\tbne.n\t2eaa <__gridxc_array_MOD_ac_3d_1d_ip+0x152>\n+\tbne.n\t2a2c <__gridxc_array_MOD_ac_3d_1d_ip+0x154>\n \tldrd\tr8, r6, [sp, #56]\t@ 0x38\n-\tb.n\t2e5c <__gridxc_array_MOD_ac_3d_1d_ip+0x104>\n-\tnop\n+\tb.n\t29de <__gridxc_array_MOD_ac_3d_1d_ip+0x106>\n \t.word\t0x000001b0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000be\n+\t.word\t0x000000bc\n R_ARM_REL32\t.LC41\n \n-00002f30 <__gridxc_array_MOD_ac_2d_1d_dp>:\n+00002ab0 <__gridxc_array_MOD_ac_2d_1d_dp>:\n __gridxc_array_MOD_ac_2d_1d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tmov\tr4, r2\n \tmov\tr8, r0\n \tmov\tlr, r1\n \tmov\tr1, r3\n-\tldr\tr3, [pc, #296]\t@ (3074 <__gridxc_array_MOD_ac_2d_1d_dp+0x144>)\n+\tldr\tr3, [pc, #288]\t@ (2bec <__gridxc_array_MOD_ac_2d_1d_dp+0x13c>)\n \tldr\tr0, [sp, #68]\t@ 0x44\n \tldr\tr6, [r4, #24]\n \tadd\tr3, pc\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr.w\tr9, [r0, #24]\n \trsb\tfp, r6, #0\n \tldr\tr0, [r0, #0]\n \tcmp.w\tr9, #0\n \tstr\tr0, [sp, #4]\n-\tmov.w\tr0, #1\n \tit\teq\n-\tmoveq\tr9, r0\n-\tcbnz\tr6, 2f74 <__gridxc_array_MOD_ac_2d_1d_dp+0x44>\n+\tmoveq.w\tr9, #1\n+\tcbnz\tr6, 2af2 <__gridxc_array_MOD_ac_2d_1d_dp+0x42>\n \tmov.w\tfp, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tldr\tr7, [r4, #36]\t@ 0x24\n \tldr\tr5, [r1, #0]\n \tldr.w\tr0, [lr, #4]\n \tsub.w\tfp, fp, r7\n \tldr\tr1, [r4, #0]\n \tldr.w\tr4, [r8, #4]\n-\tstr\tr1, [sp, #8]\n \tcmp\tr4, r0\n-\tbgt.n\t2fee <__gridxc_array_MOD_ac_2d_1d_dp+0xbe>\n-\tmov\tr1, r9\n+\tbgt.n\t2b68 <__gridxc_array_MOD_ac_2d_1d_dp+0xb8>\n \tldr.w\tr8, [r8]\n-\tldr.w\tsl, [lr]\n-\tcmp\tr6, #1\n+\tcmp.w\tr9, #1\n \tit\teq\n-\tcmpeq\tr1, #1\n-\tbne.n\t300e <__gridxc_array_MOD_ac_2d_1d_dp+0xde>\n+\tcmpeq\tr6, #1\n+\tldr.w\tsl, [lr]\n+\tbne.n\t2b88 <__gridxc_array_MOD_ac_2d_1d_dp+0xd8>\n \tadd.w\tr9, r0, #1\n \tmla\tr0, r7, r4, r8\n-\tldr\tr1, [sp, #8]\n \tlsls\tr7, r7, #3\n-\tadd\tr0, fp\n \tstrd\tr2, r3, [sp, #12]\n+\tadd\tr0, fp\n \tadd.w\tr6, r1, r0, lsl #3\n \tadd.w\tr1, sl, #1\n \tsub.w\tfp, r1, r8\n \tmov.w\tr1, fp, lsl #3\n \tstr\tr1, [sp, #8]\n \tmov\tr1, fp\n \tmov\tfp, r7\n@@ -4900,131 +4447,126 @@\n \tmov\tr5, r1\n \tldr\tr3, [sp, #4]\n \tsubs\tr0, r7, #1\n \tldr\tr2, [sp, #8]\n \tmov\tr1, r6\n \tcmp\tr8, sl\n \tadd.w\tr0, r3, r0, lsl #3\n-\tbgt.n\t2fe0 <__gridxc_array_MOD_ac_2d_1d_dp+0xb0>\n+\tbgt.n\t2b5a <__gridxc_array_MOD_ac_2d_1d_dp+0xaa>\n \tadd\tr7, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tadds\tr4, #1\n \tadd\tr6, fp\n \tcmp\tr9, r4\n-\tbne.n\t2fca <__gridxc_array_MOD_ac_2d_1d_dp+0x9a>\n+\tbne.n\t2b44 <__gridxc_array_MOD_ac_2d_1d_dp+0x94>\n \tldrd\tr2, r3, [sp, #12]\n \tmov\tr5, r7\n \tldr\tr2, [r2, #0]\n \tcmp\tr2, r5\n-\tblt.n\t3008 <__gridxc_array_MOD_ac_2d_1d_dp+0xd8>\n-\tldr\tr2, [pc, #128]\t@ (3078 <__gridxc_array_MOD_ac_2d_1d_dp+0x148>)\n+\tblt.n\t2b82 <__gridxc_array_MOD_ac_2d_1d_dp+0xd2>\n+\tldr\tr2, [pc, #128]\t@ (2bf0 <__gridxc_array_MOD_ac_2d_1d_dp+0x140>)\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #128]\t@ (307c <__gridxc_array_MOD_ac_2d_1d_dp+0x14c>)\n+\tldr\tr0, [pc, #128]\t@ (2bf4 <__gridxc_array_MOD_ac_2d_1d_dp+0x144>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #8]\n \tadd.w\tip, r0, #1\n \tmul.w\tr0, r8, r6\n-\tmov.w\tlr, r9, lsl #3\n \tmla\tfp, r7, r4, fp\n+\tmov.w\tlr, r9, lsl #3\n \tstr\tr3, [sp, #20]\n \tadd.w\tr1, r1, r0, lsl #3\n \tlsls\tr0, r6, #3\n \tadd.w\tr6, sl, #1\n \tstr\tr1, [sp, #8]\n \tsub.w\tr1, r6, r8\n \tstrd\tr1, r2, [sp, #12]\n \tcmp\tr8, sl\n-\tbgt.n\t3064 <__gridxc_array_MOD_ac_2d_1d_dp+0x134>\n+\tbgt.n\t2bdc <__gridxc_array_MOD_ac_2d_1d_dp+0x12c>\n \tsubs\tr3, r5, #1\n \tldr\tr2, [sp, #4]\n \tmul.w\tr3, r9, r3\n \tadd.w\tr3, r2, r3, lsl #3\n \tldr\tr2, [sp, #8]\n \tadd.w\tr1, r2, fp, lsl #3\n \tmov\tr2, r8\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr2, #1\n \tadd\tr1, r0\n \tcmp\tr2, r6\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tadd\tr3, lr\n-\tbne.n\t304e <__gridxc_array_MOD_ac_2d_1d_dp+0x11e>\n+\tbne.n\t2bc6 <__gridxc_array_MOD_ac_2d_1d_dp+0x116>\n \tldr\tr3, [sp, #12]\n \tadd\tr5, r3\n \tadds\tr4, #1\n \tadd\tfp, r7\n \tcmp\tr4, ip\n-\tbne.n\t3036 <__gridxc_array_MOD_ac_2d_1d_dp+0x106>\n+\tbne.n\t2bae <__gridxc_array_MOD_ac_2d_1d_dp+0xfe>\n \tldrd\tr2, r3, [sp, #16]\n-\tb.n\t2fee <__gridxc_array_MOD_ac_2d_1d_dp+0xbe>\n+\tb.n\t2b68 <__gridxc_array_MOD_ac_2d_1d_dp+0xb8>\n \tnop\n-\t.word\t0x00000120\n+\t.word\t0x00000118\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000007e\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC42\n \n-00003080 <__gridxc_array_MOD_ac_2d_1d_sp>:\n+00002bf8 <__gridxc_array_MOD_ac_2d_1d_sp>:\n __gridxc_array_MOD_ac_2d_1d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tmov\tr4, r2\n \tmov\tr8, r0\n \tmov\tlr, r1\n \tmov\tr1, r3\n-\tldr\tr3, [pc, #296]\t@ (31c4 <__gridxc_array_MOD_ac_2d_1d_sp+0x144>)\n+\tldr\tr3, [pc, #288]\t@ (2d34 <__gridxc_array_MOD_ac_2d_1d_sp+0x13c>)\n \tldr\tr0, [sp, #68]\t@ 0x44\n \tldr\tr6, [r4, #24]\n \tadd\tr3, pc\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr.w\tr9, [r0, #24]\n \trsb\tfp, r6, #0\n \tldr\tr0, [r0, #0]\n \tcmp.w\tr9, #0\n \tstr\tr0, [sp, #4]\n-\tmov.w\tr0, #1\n \tit\teq\n-\tmoveq\tr9, r0\n-\tcbnz\tr6, 30c4 <__gridxc_array_MOD_ac_2d_1d_sp+0x44>\n+\tmoveq.w\tr9, #1\n+\tcbnz\tr6, 2c3a <__gridxc_array_MOD_ac_2d_1d_sp+0x42>\n \tmov.w\tfp, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tldr\tr7, [r4, #36]\t@ 0x24\n \tldr\tr5, [r1, #0]\n \tldr.w\tr0, [lr, #4]\n \tsub.w\tfp, fp, r7\n \tldr\tr1, [r4, #0]\n \tldr.w\tr4, [r8, #4]\n-\tstr\tr1, [sp, #8]\n \tcmp\tr4, r0\n-\tbgt.n\t313e <__gridxc_array_MOD_ac_2d_1d_sp+0xbe>\n-\tmov\tr1, r9\n+\tbgt.n\t2cb0 <__gridxc_array_MOD_ac_2d_1d_sp+0xb8>\n \tldr.w\tr8, [r8]\n-\tldr.w\tsl, [lr]\n-\tcmp\tr6, #1\n+\tcmp.w\tr9, #1\n \tit\teq\n-\tcmpeq\tr1, #1\n-\tbne.n\t315e <__gridxc_array_MOD_ac_2d_1d_sp+0xde>\n+\tcmpeq\tr6, #1\n+\tldr.w\tsl, [lr]\n+\tbne.n\t2cd0 <__gridxc_array_MOD_ac_2d_1d_sp+0xd8>\n \tadd.w\tr9, r0, #1\n \tmla\tr0, r7, r4, r8\n-\tldr\tr1, [sp, #8]\n \tlsls\tr7, r7, #2\n-\tadd\tr0, fp\n \tstrd\tr2, r3, [sp, #12]\n+\tadd\tr0, fp\n \tadd.w\tr6, r1, r0, lsl #2\n \tadd.w\tr1, sl, #1\n \tsub.w\tfp, r1, r8\n \tmov.w\tr1, fp, lsl #2\n \tstr\tr1, [sp, #8]\n \tmov\tr1, fp\n \tmov\tfp, r7\n@@ -5032,131 +4574,126 @@\n \tmov\tr5, r1\n \tldr\tr3, [sp, #4]\n \tsubs\tr0, r7, #1\n \tldr\tr2, [sp, #8]\n \tmov\tr1, r6\n \tcmp\tr8, sl\n \tadd.w\tr0, r3, r0, lsl #2\n-\tbgt.n\t3130 <__gridxc_array_MOD_ac_2d_1d_sp+0xb0>\n+\tbgt.n\t2ca2 <__gridxc_array_MOD_ac_2d_1d_sp+0xaa>\n \tadd\tr7, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tadds\tr4, #1\n \tadd\tr6, fp\n \tcmp\tr9, r4\n-\tbne.n\t311a <__gridxc_array_MOD_ac_2d_1d_sp+0x9a>\n+\tbne.n\t2c8c <__gridxc_array_MOD_ac_2d_1d_sp+0x94>\n \tldrd\tr2, r3, [sp, #12]\n \tmov\tr5, r7\n \tldr\tr2, [r2, #0]\n \tcmp\tr2, r5\n-\tblt.n\t3158 <__gridxc_array_MOD_ac_2d_1d_sp+0xd8>\n-\tldr\tr2, [pc, #128]\t@ (31c8 <__gridxc_array_MOD_ac_2d_1d_sp+0x148>)\n+\tblt.n\t2cca <__gridxc_array_MOD_ac_2d_1d_sp+0xd2>\n+\tldr\tr2, [pc, #128]\t@ (2d38 <__gridxc_array_MOD_ac_2d_1d_sp+0x140>)\n \tmovs\tr1, #19\n-\tldr\tr0, [pc, #128]\t@ (31cc <__gridxc_array_MOD_ac_2d_1d_sp+0x14c>)\n+\tldr\tr0, [pc, #128]\t@ (2d3c <__gridxc_array_MOD_ac_2d_1d_sp+0x144>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #8]\n \tadd.w\tip, r0, #1\n \tmul.w\tr0, r8, r6\n-\tmov.w\tlr, r9, lsl #2\n \tmla\tfp, r7, r4, fp\n+\tmov.w\tlr, r9, lsl #2\n \tstr\tr3, [sp, #20]\n \tadd.w\tr1, r1, r0, lsl #2\n \tlsls\tr0, r6, #2\n \tadd.w\tr6, sl, #1\n \tstr\tr1, [sp, #8]\n \tsub.w\tr1, r6, r8\n \tstrd\tr1, r2, [sp, #12]\n \tcmp\tr8, sl\n-\tbgt.n\t31b4 <__gridxc_array_MOD_ac_2d_1d_sp+0x134>\n+\tbgt.n\t2d24 <__gridxc_array_MOD_ac_2d_1d_sp+0x12c>\n \tsubs\tr3, r5, #1\n \tldr\tr2, [sp, #4]\n \tmul.w\tr3, r9, r3\n \tadd.w\tr3, r2, r3, lsl #2\n \tldr\tr2, [sp, #8]\n \tadd.w\tr1, r2, fp, lsl #2\n \tmov\tr2, r8\n \tvldr\ts15, [r1]\n \tadds\tr2, #1\n \tadd\tr1, r0\n \tcmp\tr2, r6\n \tvstr\ts15, [r3]\n \tadd\tr3, lr\n-\tbne.n\t319e <__gridxc_array_MOD_ac_2d_1d_sp+0x11e>\n+\tbne.n\t2d0e <__gridxc_array_MOD_ac_2d_1d_sp+0x116>\n \tldr\tr3, [sp, #12]\n \tadd\tr5, r3\n \tadds\tr4, #1\n \tadd\tfp, r7\n \tcmp\tr4, ip\n-\tbne.n\t3186 <__gridxc_array_MOD_ac_2d_1d_sp+0x106>\n+\tbne.n\t2cf6 <__gridxc_array_MOD_ac_2d_1d_sp+0xfe>\n \tldrd\tr2, r3, [sp, #16]\n-\tb.n\t313e <__gridxc_array_MOD_ac_2d_1d_sp+0xbe>\n+\tb.n\t2cb0 <__gridxc_array_MOD_ac_2d_1d_sp+0xb8>\n \tnop\n-\t.word\t0x00000120\n+\t.word\t0x00000118\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000007e\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC43\n \n-000031d0 <__gridxc_array_MOD_ac_2d_1d_ip>:\n+00002d40 <__gridxc_array_MOD_ac_2d_1d_ip>:\n __gridxc_array_MOD_ac_2d_1d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tmov\tr4, r2\n \tmov\tr8, r0\n \tmov\tlr, r1\n \tmov\tr1, r3\n-\tldr\tr3, [pc, #296]\t@ (3314 <__gridxc_array_MOD_ac_2d_1d_ip+0x144>)\n+\tldr\tr3, [pc, #288]\t@ (2e7c <__gridxc_array_MOD_ac_2d_1d_ip+0x13c>)\n \tldr\tr0, [sp, #68]\t@ 0x44\n \tldr\tr6, [r4, #24]\n \tadd\tr3, pc\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr.w\tr9, [r0, #24]\n \trsb\tfp, r6, #0\n \tldr\tr0, [r0, #0]\n \tcmp.w\tr9, #0\n \tstr\tr0, [sp, #0]\n-\tmov.w\tr0, #1\n \tit\teq\n-\tmoveq\tr9, r0\n-\tcbnz\tr6, 3214 <__gridxc_array_MOD_ac_2d_1d_ip+0x44>\n+\tmoveq.w\tr9, #1\n+\tcbnz\tr6, 2d82 <__gridxc_array_MOD_ac_2d_1d_ip+0x42>\n \tmov.w\tfp, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tldr\tr7, [r4, #36]\t@ 0x24\n \tldr\tr5, [r1, #0]\n \tldr.w\tr0, [lr, #4]\n \tsub.w\tfp, fp, r7\n \tldr\tr1, [r4, #0]\n \tldr.w\tr4, [r8, #4]\n-\tstr\tr1, [sp, #4]\n \tcmp\tr4, r0\n-\tbgt.n\t328e <__gridxc_array_MOD_ac_2d_1d_ip+0xbe>\n-\tmov\tr1, r9\n+\tbgt.n\t2df8 <__gridxc_array_MOD_ac_2d_1d_ip+0xb8>\n \tldr.w\tr8, [r8]\n-\tldr.w\tsl, [lr]\n-\tcmp\tr6, #1\n+\tcmp.w\tr9, #1\n \tit\teq\n-\tcmpeq\tr1, #1\n-\tbne.n\t32ae <__gridxc_array_MOD_ac_2d_1d_ip+0xde>\n+\tcmpeq\tr6, #1\n+\tldr.w\tsl, [lr]\n+\tbne.n\t2e18 <__gridxc_array_MOD_ac_2d_1d_ip+0xd8>\n \tadd.w\tr9, r0, #1\n \tmla\tr0, r7, r4, r8\n-\tldr\tr1, [sp, #4]\n \tlsls\tr7, r7, #2\n-\tadd\tr0, fp\n \tstrd\tr2, r3, [sp, #8]\n+\tadd\tr0, fp\n \tadd.w\tr6, r1, r0, lsl #2\n \tadd.w\tr1, sl, #1\n \tsub.w\tfp, r1, r8\n \tmov.w\tr1, fp, lsl #2\n \tstr\tr1, [sp, #4]\n \tmov\tr1, fp\n \tmov\tfp, r7\n@@ -5164,101 +4701,100 @@\n \tmov\tr5, r1\n \tldr\tr3, [sp, #0]\n \tsubs\tr0, r7, #1\n \tldr\tr2, [sp, #4]\n \tmov\tr1, r6\n \tcmp\tr8, sl\n \tadd.w\tr0, r3, r0, lsl #2\n-\tbgt.n\t3280 <__gridxc_array_MOD_ac_2d_1d_ip+0xb0>\n+\tbgt.n\t2dea <__gridxc_array_MOD_ac_2d_1d_ip+0xaa>\n \tadd\tr7, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tadds\tr4, #1\n \tadd\tr6, fp\n \tcmp\tr9, r4\n-\tbne.n\t326a <__gridxc_array_MOD_ac_2d_1d_ip+0x9a>\n+\tbne.n\t2dd4 <__gridxc_array_MOD_ac_2d_1d_ip+0x94>\n \tldrd\tr2, r3, [sp, #8]\n \tmov\tr5, r7\n \tldr\tr2, [r2, #0]\n \tcmp\tr2, r5\n-\tblt.n\t32a8 <__gridxc_array_MOD_ac_2d_1d_ip+0xd8>\n-\tldr\tr2, [pc, #128]\t@ (3318 <__gridxc_array_MOD_ac_2d_1d_ip+0x148>)\n+\tblt.n\t2e12 <__gridxc_array_MOD_ac_2d_1d_ip+0xd2>\n+\tldr\tr2, [pc, #128]\t@ (2e80 <__gridxc_array_MOD_ac_2d_1d_ip+0x140>)\n \tmovs\tr1, #22\n-\tldr\tr0, [pc, #128]\t@ (331c <__gridxc_array_MOD_ac_2d_1d_ip+0x14c>)\n+\tldr\tr0, [pc, #128]\t@ (2e84 <__gridxc_array_MOD_ac_2d_1d_ip+0x144>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #4]\n \tadd.w\tip, r0, #1\n \tmul.w\tr0, r8, r6\n-\tmov.w\tlr, r9, lsl #2\n \tmla\tfp, r7, r4, fp\n+\tmov.w\tlr, r9, lsl #2\n \tstr\tr3, [sp, #20]\n \tadd.w\tr1, r1, r0, lsl #2\n \tlsls\tr0, r6, #2\n \tadd.w\tr6, sl, #1\n \tstr\tr1, [sp, #8]\n \tsub.w\tr1, r6, r8\n \tstrd\tr1, r2, [sp, #12]\n \tcmp\tr8, sl\n-\tbgt.n\t3304 <__gridxc_array_MOD_ac_2d_1d_ip+0x134>\n+\tbgt.n\t2e6c <__gridxc_array_MOD_ac_2d_1d_ip+0x12c>\n \tsubs\tr3, r5, #1\n \tldr\tr2, [sp, #0]\n \tstr\tr4, [sp, #4]\n \tmul.w\tr3, r9, r3\n \tadd.w\tr3, r2, r3, lsl #2\n \tldr\tr2, [sp, #8]\n \tadd.w\tr1, r2, fp, lsl #2\n \tmov\tr2, r8\n \tldr\tr4, [r1, #0]\n \tadds\tr2, #1\n \tstr\tr4, [r3, #0]\n \tadd\tr1, r0\n \tadd\tr3, lr\n \tcmp\tr2, r6\n-\tbne.n\t32f0 <__gridxc_array_MOD_ac_2d_1d_ip+0x120>\n+\tbne.n\t2e58 <__gridxc_array_MOD_ac_2d_1d_ip+0x118>\n \tldr\tr3, [sp, #12]\n \tldr\tr4, [sp, #4]\n \tadd\tr5, r3\n \tadds\tr4, #1\n \tadd\tfp, r7\n \tcmp\tr4, ip\n-\tbne.n\t32d6 <__gridxc_array_MOD_ac_2d_1d_ip+0x106>\n+\tbne.n\t2e3e <__gridxc_array_MOD_ac_2d_1d_ip+0xfe>\n \tldrd\tr2, r3, [sp, #16]\n-\tb.n\t328e <__gridxc_array_MOD_ac_2d_1d_ip+0xbe>\n+\tb.n\t2df8 <__gridxc_array_MOD_ac_2d_1d_ip+0xb8>\n \tnop\n-\t.word\t0x00000120\n+\t.word\t0x00000118\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000007e\n+\t.word\t0x0000007c\n R_ARM_REL32\t.LC44\n \n-00003320 <__gridxc_array_MOD_ac_1d_3d_dp>:\n+00002e88 <__gridxc_array_MOD_ac_1d_3d_dp>:\n __gridxc_array_MOD_ac_1d_3d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tldr\tr5, [sp, #68]\t@ 0x44\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #8]\n \tldr.w\tfp, [r5, #24]\n-\tldr\tr4, [pc, #308]\t@ (3474 <__gridxc_array_MOD_ac_1d_3d_dp+0x154>)\n+\tldr\tr4, [pc, #312]\t@ (2fe0 <__gridxc_array_MOD_ac_1d_3d_dp+0x158>)\n \trsb\tr7, fp, #0\n \tadd\tr4, pc\n \tstr\tr4, [sp, #12]\n \tcmp.w\tfp, #0\n-\tbne.n\t3354 <__gridxc_array_MOD_ac_1d_3d_dp+0x34>\n+\tbne.n\t2ebc <__gridxc_array_MOD_ac_1d_3d_dp+0x34>\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r5, #36]\t@ 0x24\n \tldr.w\tip, [r0]\n \tldr\tr0, [r2, #24]\n \tldr\tr4, [r1, #0]\n \tsubs\tr1, r7, r6\n@@ -5269,74 +4805,74 @@\n \tmoveq\tr0, #1\n \tldrd\tsl, r5, [r3]\n \tstr\tr5, [sp, #4]\n \tldr\tr2, [r2, #0]\n \tsubs\tr1, r1, r7\n \tldr\tr5, [r3, #8]\n \tcmp\tip, r4\n-\tbgt.n\t33f6 <__gridxc_array_MOD_ac_1d_3d_dp+0xd6>\n+\tbgt.n\t2f60 <__gridxc_array_MOD_ac_1d_3d_dp+0xd8>\n \tldr\tr3, [sp, #8]\n-\tldrd\tr8, r9, [r3]\n-\tmov\tr3, fp\n-\tcmp\tr0, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t341a <__gridxc_array_MOD_ac_1d_3d_dp+0xfa>\n+\tcmpeq\tr0, #1\n+\tldrd\tr8, r9, [r3]\n+\tbne.n\t2f84 <__gridxc_array_MOD_ac_1d_3d_dp+0xfc>\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tadd.w\tfp, r2, r4, lsl #3\n \tmov\tr3, sl\n \tadd.w\tr2, r2, ip, lsl #3\n \tldr.w\tip, [sp, #4]\n \tmov\tr4, ip\n \tadds\tr0, r3, r1\n-\tvldmia\tr2!, {d16}\n \tadds\tr3, #1\n \tcmp\tr8, r3\n+\tvldmia\tr2!, {d7}\n+\tit\tlt\n+\tmovlt\tr3, sl\n \tmla\tr0, r5, r7, r0\n \tmla\tr0, r4, r6, r0\n-\tadd.w\tr0, lr, r0, lsl #3\n-\tvstr\td16, [r0]\n-\tbge.n\t33c0 <__gridxc_array_MOD_ac_1d_3d_dp+0xa0>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\tit\tlt\n+\taddlt\tr4, #1\n \tcmp\tr9, r4\n-\tbge.n\t33c8 <__gridxc_array_MOD_ac_1d_3d_dp+0xa8>\n-\tadds\tr5, #1\n-\tmov\tr4, ip\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tmovlt\tr4, ip\n+\tadd.w\tr0, lr, r0, lsl #3\n \tcmp\tfp, r2\n-\tbne.n\t33a0 <__gridxc_array_MOD_ac_1d_3d_dp+0x80>\n+\tvstr\td7, [r0]\n+\tbne.n\t2f08 <__gridxc_array_MOD_ac_1d_3d_dp+0x80>\n \tcmp\tsl, r3\n-\tbeq.n\t33e0 <__gridxc_array_MOD_ac_1d_3d_dp+0xc0>\n-\tldr\tr3, [pc, #164]\t@ (3478 <__gridxc_array_MOD_ac_1d_3d_dp+0x158>)\n+\tbeq.n\t2f4a <__gridxc_array_MOD_ac_1d_3d_dp+0xc2>\n+\tldr\tr3, [pc, #168]\t@ (2fe4 <__gridxc_array_MOD_ac_1d_3d_dp+0x15c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #164]\t@ (347c <__gridxc_array_MOD_ac_1d_3d_dp+0x15c>)\n+\tldr\tr0, [pc, #164]\t@ (2fe8 <__gridxc_array_MOD_ac_1d_3d_dp+0x160>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r4\n-\tbeq.n\t33f6 <__gridxc_array_MOD_ac_1d_3d_dp+0xd6>\n-\tldr\tr3, [pc, #144]\t@ (3478 <__gridxc_array_MOD_ac_1d_3d_dp+0x158>)\n+\tbeq.n\t2f60 <__gridxc_array_MOD_ac_1d_3d_dp+0xd8>\n+\tldr\tr3, [pc, #144]\t@ (2fe4 <__gridxc_array_MOD_ac_1d_3d_dp+0x15c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #144]\t@ (3480 <__gridxc_array_MOD_ac_1d_3d_dp+0x160>)\n+\tldr\tr0, [pc, #148]\t@ (2fec <__gridxc_array_MOD_ac_1d_3d_dp+0x164>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #8]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t3414 <__gridxc_array_MOD_ac_1d_3d_dp+0xf4>\n-\tldr\tr3, [pc, #120]\t@ (3478 <__gridxc_array_MOD_ac_1d_3d_dp+0x158>)\n+\tblt.n\t2f7e <__gridxc_array_MOD_ac_1d_3d_dp+0xf6>\n+\tldr\tr3, [pc, #120]\t@ (2fe4 <__gridxc_array_MOD_ac_1d_3d_dp+0x15c>)\n \tmovs\tr1, #25\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #124]\t@ (3484 <__gridxc_array_MOD_ac_1d_3d_dp+0x164>)\n+\tldr\tr0, [pc, #128]\t@ (2ff0 <__gridxc_array_MOD_ac_1d_3d_dp+0x168>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n@@ -5348,218 +4884,215 @@\n \tstr.w\tsl, [sp, #20]\n \tmul.w\tr3, r0, r3\n \tlsls\tr0, r0, #3\n \tadd.w\tr2, r2, r3, lsl #3\n \tmov\tr3, sl\n \tmov\tsl, r0\n \tmla\tr0, r5, r7, r1\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tmla\tr0, r4, r6, r0\n \tadd.w\tip, ip, #1\n \tmla\tr0, r3, fp, r0\n \tadds\tr3, #1\n \tcmp\tr8, r3\n+\tadd\tr2, sl\n+\tit\tlt\n+\taddlt\tr4, #1\n \tadd.w\tr0, lr, r0, lsl #3\n-\tvstr\td16, [r0]\n-\tbge.n\t345c <__gridxc_array_MOD_ac_1d_3d_dp+0x13c>\n-\tldr\tr3, [sp, #20]\n-\tadds\tr4, #1\n+\tit\tlt\n+\tldrlt\tr3, [sp, #20]\n \tcmp\tr9, r4\n-\tbge.n\t3464 <__gridxc_array_MOD_ac_1d_3d_dp+0x144>\n-\tldr\tr4, [sp, #4]\n-\tadds\tr5, #1\n+\tit\tlt\n+\taddlt\tr5, #1\n+\tvstr\td7, [r0]\n \tldr\tr0, [sp, #16]\n-\tadd\tr2, sl\n+\tit\tlt\n+\tldrlt\tr4, [sp, #4]\n \tcmp\tr0, ip\n-\tbne.n\t3436 <__gridxc_array_MOD_ac_1d_3d_dp+0x116>\n+\tbne.n\t2fa0 <__gridxc_array_MOD_ac_1d_3d_dp+0x118>\n \tldr.w\tsl, [sp, #20]\n-\tb.n\t33cc <__gridxc_array_MOD_ac_1d_3d_dp+0xac>\n-\tnop\n-\t.word\t0x0000012e\n+\tb.n\t2f36 <__gridxc_array_MOD_ac_1d_3d_dp+0xae>\n+\t.word\t0x00000132\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000009e\n+\t.word\t0x000000a0\n R_ARM_REL32\t.LC45\n-\t.word\t0x0000008c\n+\t.word\t0x0000008e\n R_ARM_REL32\t.LC46\n-\t.word\t0x00000078\n+\t.word\t0x0000007a\n R_ARM_REL32\t.LC47\n \n-00003488 <__gridxc_array_MOD_ac_1d_3d_sp>:\n+00002ff4 <__gridxc_array_MOD_ac_1d_3d_sp>:\n __gridxc_array_MOD_ac_1d_3d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n-\tmov\tr6, r0\n-\tmov\tr5, r3\n-\tldr\tr3, [pc, #320]\t@ (35e0 <__gridxc_array_MOD_ac_1d_3d_sp+0x158>)\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tadd\tr3, pc\n+\tldr\tr5, [sp, #68]\t@ 0x44\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #8]\n-\tmov\tr4, r1\n-\tldr.w\tlr, [r0, #24]\n-\tstr\tr3, [sp, #12]\n-\trsb\tip, lr, #0\n-\tcmp.w\tlr, #0\n-\tbne.n\t34c2 <__gridxc_array_MOD_ac_1d_3d_sp+0x3a>\n-\tmov.w\tip, #4294967295\t@ 0xffffffff\n-\tmov.w\tlr, #1\n-\tldr\tr1, [r6, #0]\n-\tldr\tr6, [r0, #36]\t@ 0x24\n-\tldr\tr3, [r4, #0]\n-\tldr\tr7, [r0, #48]\t@ 0x30\n-\tsub.w\tip, ip, r6\n-\tldr\tr4, [r2, #24]\n-\tldr.w\tr8, [r0]\n-\tsub.w\tr0, ip, r7\n-\tcmp\tr4, #0\n-\tstr\tr0, [sp, #16]\n-\tldrd\tfp, r0, [r5]\n+\tldr.w\tfp, [r5, #24]\n+\tldr\tr4, [pc, #312]\t@ (314c <__gridxc_array_MOD_ac_1d_3d_sp+0x158>)\n+\trsb\tr7, fp, #0\n+\tadd\tr4, pc\n+\tstr\tr4, [sp, #12]\n+\tcmp.w\tfp, #0\n+\tbne.n\t3028 <__gridxc_array_MOD_ac_1d_3d_sp+0x34>\n+\tmov.w\tr7, #4294967295\t@ 0xffffffff\n+\tmov.w\tfp, #1\n+\tldr\tr6, [r5, #36]\t@ 0x24\n+\tldr.w\tip, [r0]\n+\tldr\tr0, [r2, #24]\n+\tldr\tr4, [r1, #0]\n+\tsubs\tr1, r7, r6\n+\tldr\tr7, [r5, #48]\t@ 0x30\n+\tcmp\tr0, #0\n+\tldr.w\tlr, [r5]\n \tit\teq\n-\tmoveq\tr4, #1\n+\tmoveq\tr0, #1\n+\tldrd\tsl, r5, [r3]\n+\tstr\tr5, [sp, #4]\n \tldr\tr2, [r2, #0]\n-\tcmp\tr1, r3\n-\tldr\tr5, [r5, #8]\n-\tstr\tr0, [sp, #4]\n-\tbgt.n\t3564 <__gridxc_array_MOD_ac_1d_3d_sp+0xdc>\n-\tldr\tr0, [sp, #8]\n-\tldrd\tr9, sl, [r0]\n-\tmov\tr0, lr\n-\tcmp\tr4, #1\n+\tsubs\tr1, r1, r7\n+\tldr\tr5, [r3, #8]\n+\tcmp\tip, r4\n+\tbgt.n\t30cc <__gridxc_array_MOD_ac_1d_3d_sp+0xd8>\n+\tldr\tr3, [sp, #8]\n+\tcmp.w\tfp, #1\n \tit\teq\n \tcmpeq\tr0, #1\n-\tbne.n\t3588 <__gridxc_array_MOD_ac_1d_3d_sp+0x100>\n-\tsubs\tr1, #1\n-\tldr\tr4, [sp, #4]\n-\tldr\tr0, [sp, #16]\n-\tadd.w\tlr, r2, r3, lsl #2\n-\tadd.w\tr1, r2, r1, lsl #2\n-\tmov\tr2, fp\n-\tadds\tr3, r2, r0\n-\tldr.w\tip, [r1], #4\n-\tadds\tr2, #1\n-\tcmp\tr9, r2\n-\tmla\tr3, r5, r7, r3\n-\tmla\tr3, r4, r6, r3\n-\tadd.w\tr3, r8, r3, lsl #2\n-\tstr.w\tip, [r3]\n-\tbge.n\t352e <__gridxc_array_MOD_ac_1d_3d_sp+0xa6>\n-\tadds\tr4, #1\n-\tmov\tr2, fp\n-\tcmp\tsl, r4\n-\tbge.n\t3536 <__gridxc_array_MOD_ac_1d_3d_sp+0xae>\n-\tldr\tr4, [sp, #4]\n-\tadds\tr5, #1\n-\tcmp\tlr, r1\n-\tbne.n\t350e <__gridxc_array_MOD_ac_1d_3d_sp+0x86>\n+\tldrd\tr8, r9, [r3]\n+\tbne.n\t30f0 <__gridxc_array_MOD_ac_1d_3d_sp+0xfc>\n+\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n+\tadd.w\tfp, r2, r4, lsl #2\n+\tmov\tr3, sl\n+\tadd.w\tr2, r2, ip, lsl #2\n+\tldr.w\tip, [sp, #4]\n+\tmov\tr4, ip\n+\tadds\tr0, r3, r1\n+\tadds\tr3, #1\n+\tcmp\tr8, r3\n+\tvldmia\tr2!, {s15}\n+\tit\tlt\n+\tmovlt\tr3, sl\n+\tmla\tr0, r5, r7, r0\n+\tmla\tr0, r4, r6, r0\n+\tit\tlt\n+\taddlt\tr4, #1\n+\tcmp\tr9, r4\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tmovlt\tr4, ip\n+\tadd.w\tr0, lr, r0, lsl #2\n \tcmp\tfp, r2\n-\tbeq.n\t354e <__gridxc_array_MOD_ac_1d_3d_sp+0xc6>\n-\tldr\tr3, [pc, #164]\t@ (35e4 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n+\tvstr\ts15, [r0]\n+\tbne.n\t3074 <__gridxc_array_MOD_ac_1d_3d_sp+0x80>\n+\tcmp\tsl, r3\n+\tbeq.n\t30b6 <__gridxc_array_MOD_ac_1d_3d_sp+0xc2>\n+\tldr\tr3, [pc, #168]\t@ (3150 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #160]\t@ (35e8 <__gridxc_array_MOD_ac_1d_3d_sp+0x160>)\n+\tldr\tr0, [pc, #164]\t@ (3154 <__gridxc_array_MOD_ac_1d_3d_sp+0x160>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r4\n-\tbeq.n\t3564 <__gridxc_array_MOD_ac_1d_3d_sp+0xdc>\n-\tldr\tr3, [pc, #140]\t@ (35e4 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n+\tbeq.n\t30cc <__gridxc_array_MOD_ac_1d_3d_sp+0xd8>\n+\tldr\tr3, [pc, #144]\t@ (3150 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #144]\t@ (35ec <__gridxc_array_MOD_ac_1d_3d_sp+0x164>)\n+\tldr\tr0, [pc, #148]\t@ (3158 <__gridxc_array_MOD_ac_1d_3d_sp+0x164>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #8]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t3582 <__gridxc_array_MOD_ac_1d_3d_sp+0xfa>\n-\tldr\tr3, [pc, #116]\t@ (35e4 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n+\tblt.n\t30ea <__gridxc_array_MOD_ac_1d_3d_sp+0xf6>\n+\tldr\tr3, [pc, #120]\t@ (3150 <__gridxc_array_MOD_ac_1d_3d_sp+0x15c>)\n \tmovs\tr1, #23\n \tldr\tr2, [sp, #12]\n-\tldr\tr0, [pc, #124]\t@ (35f0 <__gridxc_array_MOD_ac_1d_3d_sp+0x168>)\n+\tldr\tr0, [pc, #128]\t@ (315c <__gridxc_array_MOD_ac_1d_3d_sp+0x168>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tadds\tr3, r4, #1\n+\tstr\tr3, [sp, #16]\n+\tadd.w\tr3, ip, #4294967295\t@ 0xffffffff\n+\tldr\tr4, [sp, #4]\n+\tstr.w\tsl, [sp, #20]\n+\tmul.w\tr3, r0, r3\n+\tlsls\tr0, r0, #2\n+\tadd.w\tr2, r2, r3, lsl #2\n+\tmov\tr3, sl\n+\tmov\tsl, r0\n+\tmla\tr0, r5, r7, r1\n+\tvldr\ts15, [r2]\n+\tmla\tr0, r4, r6, r0\n+\tadd.w\tip, ip, #1\n+\tmla\tr0, r3, fp, r0\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #20]\n-\tsubs\tr3, r1, #1\n+\tcmp\tr8, r3\n+\tadd\tr2, sl\n+\tit\tlt\n+\taddlt\tr4, #1\n+\tadd.w\tr0, lr, r0, lsl #2\n+\tit\tlt\n+\tldrlt\tr3, [sp, #20]\n+\tcmp\tr9, r4\n+\tit\tlt\n+\taddlt\tr5, #1\n+\tvstr\ts15, [r0]\n \tldr\tr0, [sp, #16]\n-\tstr.w\tfp, [sp, #16]\n-\tmul.w\tr3, r4, r3\n-\tadd.w\tip, r2, r3, lsl #2\n-\tlsls\tr3, r4, #2\n-\tldr\tr4, [sp, #4]\n-\tmov\tr2, fp\n-\tmov\tfp, r3\n-\tmla\tr3, r5, r7, r0\n-\tvldr\ts15, [ip]\n-\tmla\tr3, r4, r6, r3\n-\tadds\tr1, #1\n-\tmla\tr3, r2, lr, r3\n-\tadds\tr2, #1\n-\tcmp\tr9, r2\n-\tadd.w\tr3, r8, r3, lsl #2\n-\tvstr\ts15, [r3]\n-\tbge.n\t35c8 <__gridxc_array_MOD_ac_1d_3d_sp+0x140>\n-\tldr\tr2, [sp, #16]\n-\tadds\tr4, #1\n-\tcmp\tsl, r4\n-\tbge.n\t35d0 <__gridxc_array_MOD_ac_1d_3d_sp+0x148>\n-\tldr\tr4, [sp, #4]\n-\tadds\tr5, #1\n-\tldr\tr3, [sp, #20]\n-\tadd\tip, fp\n-\tcmp\tr3, r1\n-\tbne.n\t35a4 <__gridxc_array_MOD_ac_1d_3d_sp+0x11c>\n-\tldr.w\tfp, [sp, #16]\n-\tb.n\t353a <__gridxc_array_MOD_ac_1d_3d_sp+0xb2>\n-\tnop\n-\t.word\t0x0000013a\n+\tit\tlt\n+\tldrlt\tr4, [sp, #4]\n+\tcmp\tr0, ip\n+\tbne.n\t310c <__gridxc_array_MOD_ac_1d_3d_sp+0x118>\n+\tldr.w\tsl, [sp, #20]\n+\tb.n\t30a2 <__gridxc_array_MOD_ac_1d_3d_sp+0xae>\n+\t.word\t0x00000132\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000009c\n+\t.word\t0x000000a0\n R_ARM_REL32\t.LC48\n-\t.word\t0x0000008a\n+\t.word\t0x0000008e\n R_ARM_REL32\t.LC49\n-\t.word\t0x00000076\n+\t.word\t0x0000007a\n R_ARM_REL32\t.LC50\n \n-000035f4 <__gridxc_array_MOD_ac_1d_3d_ip>:\n+00003160 <__gridxc_array_MOD_ac_1d_3d_ip>:\n __gridxc_array_MOD_ac_1d_3d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n \tmov\tr7, r2\n \tmov\tr5, r3\n-\tldr\tr3, [pc, #304]\t@ (373c <__gridxc_array_MOD_ac_1d_3d_ip+0x148>)\n+\tldr\tr3, [pc, #308]\t@ (32ac <__gridxc_array_MOD_ac_1d_3d_ip+0x14c>)\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tadd\tr3, pc\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #4]\n \tldr.w\tip, [r2, #24]\n \tstr\tr3, [sp, #8]\n \trsb\tlr, ip, #0\n \tcmp.w\tip, #0\n-\tbne.n\t362c <__gridxc_array_MOD_ac_1d_3d_ip+0x38>\n+\tbne.n\t3198 <__gridxc_array_MOD_ac_1d_3d_ip+0x38>\n \tmov.w\tlr, #4294967295\t@ 0xffffffff\n \tmov.w\tip, #1\n \tldr\tr4, [r7, #24]\n \tldr\tr3, [r1, #0]\n \tldr\tr1, [r7, #0]\n \tcmp\tr4, #0\n \tldr\tr7, [r2, #36]\t@ 0x24\n@@ -5570,72 +5103,72 @@\n \tldr.w\tlr, [r2, #48]\t@ 0x30\n \tldr.w\tr8, [r2]\n \tcmp\tr6, r3\n \tldrd\tfp, r2, [r5]\n \tsub.w\tr0, r0, lr\n \tldr\tr5, [r5, #8]\n \tstr\tr2, [sp, #0]\n-\tbgt.n\t36c8 <__gridxc_array_MOD_ac_1d_3d_ip+0xd4>\n+\tbgt.n\t3236 <__gridxc_array_MOD_ac_1d_3d_ip+0xd6>\n \tldr\tr2, [sp, #4]\n-\tldrd\tr9, sl, [r2]\n-\tmov\tr2, ip\n-\tcmp\tr4, #1\n+\tcmp.w\tip, #1\n \tit\teq\n-\tcmpeq\tr2, #1\n-\tbne.n\t36ec <__gridxc_array_MOD_ac_1d_3d_ip+0xf8>\n+\tcmpeq\tr4, #1\n+\tldrd\tr9, sl, [r2]\n+\tbne.n\t325a <__gridxc_array_MOD_ac_1d_3d_ip+0xfa>\n \tsubs\tr6, #1\n \tldr\tr4, [sp, #0]\n \tadd.w\tip, r1, r3, lsl #2\n \tmov\tr2, fp\n \tadd.w\tr1, r1, r6, lsl #2\n \tadds\tr3, r2, r0\n-\tldr.w\tr6, [r1], #4\n \tadds\tr2, #1\n \tcmp\tr9, r2\n+\tldr.w\tr6, [r1], #4\n+\tit\tlt\n+\tmovlt\tr2, fp\n \tmla\tr3, r5, lr, r3\n \tmla\tr3, r4, r7, r3\n-\tstr.w\tr6, [r8, r3, lsl #2]\n-\tbge.n\t3692 <__gridxc_array_MOD_ac_1d_3d_ip+0x9e>\n-\tadds\tr4, #1\n-\tmov\tr2, fp\n+\tit\tlt\n+\taddlt\tr4, #1\n \tcmp\tsl, r4\n-\tbge.n\t369a <__gridxc_array_MOD_ac_1d_3d_ip+0xa6>\n-\tldr\tr4, [sp, #0]\n-\tadds\tr5, #1\n+\titt\tlt\n+\taddlt\tr5, #1\n+\tldrlt\tr4, [sp, #0]\n \tcmp\tip, r1\n-\tbne.n\t3676 <__gridxc_array_MOD_ac_1d_3d_ip+0x82>\n+\tstr.w\tr6, [r8, r3, lsl #2]\n+\tbne.n\t31e2 <__gridxc_array_MOD_ac_1d_3d_ip+0x82>\n \tcmp\tfp, r2\n-\tbeq.n\t36b2 <__gridxc_array_MOD_ac_1d_3d_ip+0xbe>\n-\tldr\tr3, [pc, #156]\t@ (3740 <__gridxc_array_MOD_ac_1d_3d_ip+0x14c>)\n+\tbeq.n\t3220 <__gridxc_array_MOD_ac_1d_3d_ip+0xc0>\n+\tldr\tr3, [pc, #156]\t@ (32b0 <__gridxc_array_MOD_ac_1d_3d_ip+0x150>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #152]\t@ (3744 <__gridxc_array_MOD_ac_1d_3d_ip+0x150>)\n+\tldr\tr0, [pc, #156]\t@ (32b4 <__gridxc_array_MOD_ac_1d_3d_ip+0x154>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #0]\n \tcmp\tr3, r4\n-\tbeq.n\t36c8 <__gridxc_array_MOD_ac_1d_3d_ip+0xd4>\n-\tldr\tr3, [pc, #132]\t@ (3740 <__gridxc_array_MOD_ac_1d_3d_ip+0x14c>)\n+\tbeq.n\t3236 <__gridxc_array_MOD_ac_1d_3d_ip+0xd6>\n+\tldr\tr3, [pc, #136]\t@ (32b0 <__gridxc_array_MOD_ac_1d_3d_ip+0x150>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #136]\t@ (3748 <__gridxc_array_MOD_ac_1d_3d_ip+0x154>)\n+\tldr\tr0, [pc, #136]\t@ (32b8 <__gridxc_array_MOD_ac_1d_3d_ip+0x158>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #4]\n \tldr\tr3, [r3, #8]\n \tcmp\tr3, r5\n-\tblt.n\t36e6 <__gridxc_array_MOD_ac_1d_3d_ip+0xf2>\n-\tldr\tr3, [pc, #108]\t@ (3740 <__gridxc_array_MOD_ac_1d_3d_ip+0x14c>)\n+\tblt.n\t3254 <__gridxc_array_MOD_ac_1d_3d_ip+0xf4>\n+\tldr\tr3, [pc, #112]\t@ (32b0 <__gridxc_array_MOD_ac_1d_3d_ip+0x150>)\n \tmovs\tr1, #26\n \tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #116]\t@ (374c <__gridxc_array_MOD_ac_1d_3d_ip+0x158>)\n+\tldr\tr0, [pc, #116]\t@ (32bc <__gridxc_array_MOD_ac_1d_3d_ip+0x15c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #28\n@@ -5649,110 +5182,110 @@\n \tadd.w\tr1, r1, r3, lsl #2\n \tlsls\tr3, r4, #2\n \tldr\tr4, [sp, #0]\n \tmov\tfp, r3\n \tldr\tr3, [sp, #16]\n \tadds\tr6, #1\n \tldr\tr0, [r1, #0]\n+\tadd\tr1, fp\n \tmla\tr3, r5, lr, r3\n \tmla\tr3, r4, r7, r3\n \tmla\tr3, r2, ip, r3\n \tadds\tr2, #1\n \tcmp\tr9, r2\n-\tstr.w\tr0, [r8, r3, lsl #2]\n-\tbge.n\t3726 <__gridxc_array_MOD_ac_1d_3d_ip+0x132>\n-\tldr\tr2, [sp, #20]\n-\tadds\tr4, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tldrlt\tr2, [sp, #20]\n \tcmp\tsl, r4\n-\tbge.n\t372e <__gridxc_array_MOD_ac_1d_3d_ip+0x13a>\n-\tldr\tr4, [sp, #0]\n-\tadds\tr5, #1\n+\tstr.w\tr0, [r8, r3, lsl #2]\n+\tit\tlt\n+\taddlt\tr5, #1\n \tldr\tr3, [sp, #12]\n-\tadd\tr1, fp\n+\tit\tlt\n+\tldrlt\tr4, [sp, #0]\n \tcmp\tr3, r6\n-\tbne.n\t3706 <__gridxc_array_MOD_ac_1d_3d_ip+0x112>\n+\tbne.n\t3274 <__gridxc_array_MOD_ac_1d_3d_ip+0x114>\n \tldr.w\tfp, [sp, #20]\n-\tb.n\t369e <__gridxc_array_MOD_ac_1d_3d_ip+0xaa>\n-\t.word\t0x0000012a\n+\tb.n\t320c <__gridxc_array_MOD_ac_1d_3d_ip+0xac>\n+\t.word\t0x0000012e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000094\n+\t.word\t0x00000096\n R_ARM_REL32\t.LC51\n-\t.word\t0x00000082\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC52\n-\t.word\t0x0000006e\n+\t.word\t0x00000070\n R_ARM_REL32\t.LC53\n \n-00003750 <__gridxc_array_MOD_ac_1d_2d_dp>:\n+000032c0 <__gridxc_array_MOD_ac_1d_2d_dp>:\n __gridxc_array_MOD_ac_1d_2d_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tsub\tsp, #12\n-\tldr\tr7, [pc, #240]\t@ (3854 <__gridxc_array_MOD_ac_1d_2d_dp+0x104>)\n+\tldr\tr7, [pc, #240]\t@ (33c4 <__gridxc_array_MOD_ac_1d_2d_dp+0x104>)\n \tadd\tr7, pc\n \tldrd\tr8, r4, [sp, #48]\t@ 0x30\n \tldr.w\tfp, [r4, #24]\n \trsb\tip, fp, #0\n \tcmp.w\tfp, #0\n-\tbne.n\t3780 <__gridxc_array_MOD_ac_1d_2d_dp+0x30>\n+\tbne.n\t32f0 <__gridxc_array_MOD_ac_1d_2d_dp+0x30>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r0, #0]\n \tldr\tr0, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr\tr5, [r4, #36]\t@ 0x24\n \tcmp\tr1, #0\n \tldr.w\tlr, [r4]\n \tit\teq\n \tmoveq\tr1, #1\n \tldr\tr2, [r2, #0]\n \tldrd\tsl, r4, [r3]\n \tsub.w\tip, ip, r5\n \tcmp\tr6, r0\n-\tbgt.n\t37ee <__gridxc_array_MOD_ac_1d_2d_dp+0x9e>\n-\tmov\tr3, fp\n+\tbgt.n\t335e <__gridxc_array_MOD_ac_1d_2d_dp+0x9e>\n \tldr.w\tr9, [r8]\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t3810 <__gridxc_array_MOD_ac_1d_2d_dp+0xc0>\n+\tcmpeq\tr1, #1\n+\tbne.n\t3380 <__gridxc_array_MOD_ac_1d_2d_dp+0xc0>\n \tsubs\tr6, #1\n \tadd.w\tr0, r2, r0, lsl #3\n \tmov\tr3, sl\n \tadd.w\tr2, r2, r6, lsl #3\n \tadd.w\tr1, r3, ip\n-\tvldmia\tr2!, {d16}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n \tcmp\tr9, r3\n \tmla\tr1, r5, r4, r1\n-\tadd.w\tr1, lr, r1, lsl #3\n-\tvstr\td16, [r1]\n-\tbge.n\t37d8 <__gridxc_array_MOD_ac_1d_2d_dp+0x88>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\titt\tlt\n+\tmovlt\tr3, sl\n+\taddlt\tr4, #1\n \tcmp\tr0, r2\n-\tbne.n\t37ba <__gridxc_array_MOD_ac_1d_2d_dp+0x6a>\n+\tadd.w\tr1, lr, r1, lsl #3\n+\tvstr\td7, [r1]\n+\tbne.n\t332a <__gridxc_array_MOD_ac_1d_2d_dp+0x6a>\n \tcmp\tsl, r3\n-\tbeq.n\t37ee <__gridxc_array_MOD_ac_1d_2d_dp+0x9e>\n-\tldr\tr3, [pc, #116]\t@ (3858 <__gridxc_array_MOD_ac_1d_2d_dp+0x108>)\n+\tbeq.n\t335e <__gridxc_array_MOD_ac_1d_2d_dp+0x9e>\n+\tldr\tr3, [pc, #116]\t@ (33c8 <__gridxc_array_MOD_ac_1d_2d_dp+0x108>)\n \tmovs\tr1, #25\n-\tldr\tr0, [pc, #116]\t@ (385c <__gridxc_array_MOD_ac_1d_2d_dp+0x10c>)\n+\tldr\tr0, [pc, #116]\t@ (33cc <__gridxc_array_MOD_ac_1d_2d_dp+0x10c>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, r4\n-\tblt.n\t380a <__gridxc_array_MOD_ac_1d_2d_dp+0xba>\n-\tldr\tr3, [pc, #96]\t@ (3858 <__gridxc_array_MOD_ac_1d_2d_dp+0x108>)\n+\tblt.n\t337a <__gridxc_array_MOD_ac_1d_2d_dp+0xba>\n+\tldr\tr3, [pc, #96]\t@ (33c8 <__gridxc_array_MOD_ac_1d_2d_dp+0x108>)\n \tmovs\tr1, #25\n-\tldr\tr0, [pc, #100]\t@ (3860 <__gridxc_array_MOD_ac_1d_2d_dp+0x110>)\n+\tldr\tr0, [pc, #100]\t@ (33d0 <__gridxc_array_MOD_ac_1d_2d_dp+0x110>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #12\n@@ -5762,105 +5295,103 @@\n \tadds\tr0, #1\n \tmul.w\tr3, r1, r3\n \tlsls\tr1, r1, #3\n \tmov\tr8, r1\n \tadd.w\tr2, r2, r3, lsl #3\n \tmov\tr3, sl\n \tmla\tr1, r4, r5, ip\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadds\tr6, #1\n \tcmp\tr9, r3\n+\tadd.w\tr6, r6, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tadd.w\tr1, lr, r1, lsl #3\n-\tvstr\td16, [r1]\n-\tbge.n\t3846 <__gridxc_array_MOD_ac_1d_2d_dp+0xf6>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n \tadd\tr2, r8\n \tcmp\tr0, r6\n-\tbne.n\t3826 <__gridxc_array_MOD_ac_1d_2d_dp+0xd6>\n+\tvstr\td7, [r1]\n+\tbne.n\t3396 <__gridxc_array_MOD_ac_1d_2d_dp+0xd6>\n \tldr.w\tr8, [sp, #4]\n-\tb.n\t37dc <__gridxc_array_MOD_ac_1d_2d_dp+0x8c>\n-\tnop\n+\tb.n\t334c <__gridxc_array_MOD_ac_1d_2d_dp+0x8c>\n \t.word\t0x000000ec\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000072\n R_ARM_REL32\t.LC54\n \t.word\t0x00000060\n R_ARM_REL32\t.LC55\n \n-00003864 <__gridxc_array_MOD_ac_1d_2d_sp>:\n+000033d4 <__gridxc_array_MOD_ac_1d_2d_sp>:\n __gridxc_array_MOD_ac_1d_2d_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tsub\tsp, #12\n-\tldr\tr7, [pc, #236]\t@ (3964 <__gridxc_array_MOD_ac_1d_2d_sp+0x100>)\n+\tldr\tr7, [pc, #240]\t@ (34d8 <__gridxc_array_MOD_ac_1d_2d_sp+0x104>)\n \tadd\tr7, pc\n \tldrd\tr8, r4, [sp, #48]\t@ 0x30\n \tldr.w\tfp, [r4, #24]\n \trsb\tip, fp, #0\n \tcmp.w\tfp, #0\n-\tbne.n\t3894 <__gridxc_array_MOD_ac_1d_2d_sp+0x30>\n+\tbne.n\t3404 <__gridxc_array_MOD_ac_1d_2d_sp+0x30>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr6, [r0, #0]\n \tldr\tr0, [r1, #0]\n \tldr\tr1, [r2, #24]\n \tldr\tr5, [r4, #36]\t@ 0x24\n \tcmp\tr1, #0\n \tldr.w\tlr, [r4]\n \tit\teq\n \tmoveq\tr1, #1\n \tldr\tr2, [r2, #0]\n \tldrd\tsl, r4, [r3]\n \tsub.w\tip, ip, r5\n \tcmp\tr6, r0\n-\tbgt.n\t3900 <__gridxc_array_MOD_ac_1d_2d_sp+0x9c>\n-\tmov\tr3, fp\n+\tbgt.n\t3470 <__gridxc_array_MOD_ac_1d_2d_sp+0x9c>\n \tldr.w\tr9, [r8]\n-\tcmp\tr1, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr3, #1\n-\tbne.n\t3922 <__gridxc_array_MOD_ac_1d_2d_sp+0xbe>\n+\tcmpeq\tr1, #1\n+\tbne.n\t3492 <__gridxc_array_MOD_ac_1d_2d_sp+0xbe>\n \tsubs\tr6, #1\n \tadd.w\tr0, r2, r0, lsl #2\n \tmov\tr3, sl\n \tadd.w\tr2, r2, r6, lsl #2\n \tadd.w\tr1, r3, ip\n \tldr.w\tr6, [r2], #4\n \tadds\tr3, #1\n \tcmp\tr9, r3\n \tmla\tr1, r5, r4, r1\n+\titt\tlt\n+\tmovlt\tr3, sl\n+\taddlt\tr4, #1\n+\tcmp\tr0, r2\n \tadd.w\tr1, lr, r1, lsl #2\n \tstr\tr6, [r1, #0]\n-\tbge.n\t38ea <__gridxc_array_MOD_ac_1d_2d_sp+0x86>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n-\tcmp\tr0, r2\n-\tbne.n\t38ce <__gridxc_array_MOD_ac_1d_2d_sp+0x6a>\n+\tbne.n\t343e <__gridxc_array_MOD_ac_1d_2d_sp+0x6a>\n \tcmp\tsl, r3\n-\tbeq.n\t3900 <__gridxc_array_MOD_ac_1d_2d_sp+0x9c>\n-\tldr\tr3, [pc, #116]\t@ (3968 <__gridxc_array_MOD_ac_1d_2d_sp+0x104>)\n+\tbeq.n\t3470 <__gridxc_array_MOD_ac_1d_2d_sp+0x9c>\n+\tldr\tr3, [pc, #120]\t@ (34dc <__gridxc_array_MOD_ac_1d_2d_sp+0x108>)\n \tmovs\tr1, #23\n-\tldr\tr0, [pc, #116]\t@ (396c <__gridxc_array_MOD_ac_1d_2d_sp+0x108>)\n+\tldr\tr0, [pc, #120]\t@ (34e0 <__gridxc_array_MOD_ac_1d_2d_sp+0x10c>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, r4\n-\tblt.n\t391c <__gridxc_array_MOD_ac_1d_2d_sp+0xb8>\n-\tldr\tr3, [pc, #92]\t@ (3968 <__gridxc_array_MOD_ac_1d_2d_sp+0x104>)\n+\tblt.n\t348c <__gridxc_array_MOD_ac_1d_2d_sp+0xb8>\n+\tldr\tr3, [pc, #96]\t@ (34dc <__gridxc_array_MOD_ac_1d_2d_sp+0x108>)\n \tmovs\tr1, #23\n-\tldr\tr0, [pc, #96]\t@ (3970 <__gridxc_array_MOD_ac_1d_2d_sp+0x10c>)\n+\tldr\tr0, [pc, #100]\t@ (34e4 <__gridxc_array_MOD_ac_1d_2d_sp+0x110>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #12\n@@ -5873,141 +5404,138 @@\n \tmov\tr8, r1\n \tadd.w\tr2, r2, r3, lsl #2\n \tmov\tr3, sl\n \tmla\tr1, r4, r5, ip\n \tvldr\ts15, [r2]\n \tmla\tr1, r3, fp, r1\n \tadds\tr3, #1\n-\tadds\tr6, #1\n \tcmp\tr9, r3\n+\tadd.w\tr6, r6, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tadd.w\tr1, lr, r1, lsl #2\n-\tvstr\ts15, [r1]\n-\tbge.n\t3958 <__gridxc_array_MOD_ac_1d_2d_sp+0xf4>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n \tadd\tr2, r8\n \tcmp\tr0, r6\n-\tbne.n\t3938 <__gridxc_array_MOD_ac_1d_2d_sp+0xd4>\n+\tvstr\ts15, [r1]\n+\tbne.n\t34a8 <__gridxc_array_MOD_ac_1d_2d_sp+0xd4>\n \tldr.w\tr8, [sp, #4]\n-\tb.n\t38ee <__gridxc_array_MOD_ac_1d_2d_sp+0x8a>\n-\t.word\t0x000000e8\n+\tb.n\t345e <__gridxc_array_MOD_ac_1d_2d_sp+0x8a>\n+\tnop\n+\t.word\t0x000000ec\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000070\n+\t.word\t0x00000074\n R_ARM_REL32\t.LC56\n-\t.word\t0x0000005e\n+\t.word\t0x00000062\n R_ARM_REL32\t.LC57\n \n-00003974 <__gridxc_array_MOD_ac_1d_2d_ip>:\n+000034e8 <__gridxc_array_MOD_ac_1d_2d_ip>:\n __gridxc_array_MOD_ac_1d_2d_ip():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tsub\tsp, #12\n \tmov\tr5, r0\n-\tldr\tr7, [pc, #244]\t@ (3a80 <__gridxc_array_MOD_ac_1d_2d_ip+0x10c>)\n+\tldr\tr7, [pc, #240]\t@ (35f0 <__gridxc_array_MOD_ac_1d_2d_ip+0x108>)\n \tmov\tr4, r3\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tadd\tr7, pc\n \tldr.w\tr8, [sp, #48]\t@ 0x30\n \tldr.w\tfp, [r0, #24]\n \trsb\tip, fp, #0\n \tcmp.w\tfp, #0\n-\tbne.n\t39aa <__gridxc_array_MOD_ac_1d_2d_ip+0x36>\n+\tbne.n\t351e <__gridxc_array_MOD_ac_1d_2d_ip+0x36>\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmov.w\tfp, #1\n \tldr\tr3, [r2, #24]\n \tldr\tr6, [r5, #0]\n \tldr\tr1, [r1, #0]\n \tcmp\tr3, #0\n \tldr\tr5, [r0, #36]\t@ 0x24\n \tit\teq\n \tmoveq\tr3, #1\n \tldr.w\tlr, [r0]\n \tcmp\tr6, r1\n-\tsub.w\tr0, ip, r5\n \tldr\tr2, [r2, #0]\n+\tsub.w\tr0, ip, r5\n \tldrd\tsl, r4, [r4]\n-\tstr\tr0, [sp, #0]\n-\tbgt.n\t3a18 <__gridxc_array_MOD_ac_1d_2d_ip+0xa4>\n-\tmov\tr0, fp\n+\tbgt.n\t3588 <__gridxc_array_MOD_ac_1d_2d_ip+0xa0>\n \tldr.w\tr9, [r8]\n-\tcmp\tr3, #1\n+\tcmp.w\tfp, #1\n \tit\teq\n-\tcmpeq\tr0, #1\n-\tbne.n\t3a3a <__gridxc_array_MOD_ac_1d_2d_ip+0xc6>\n+\tcmpeq\tr3, #1\n+\tbne.n\t35aa <__gridxc_array_MOD_ac_1d_2d_ip+0xc2>\n \tsubs\tr6, #1\n \tadd.w\tr1, r2, r1, lsl #2\n-\tldr\tr0, [sp, #0]\n \tmov\tr3, sl\n-\tadd.w\tr2, r2, r6, lsl #2\n \tmov\tip, r1\n+\tadd.w\tr2, r2, r6, lsl #2\n \tadds\tr6, r3, r0\n \tldr.w\tr1, [r2], #4\n \tadds\tr3, #1\n \tcmp\tr9, r3\n \tmla\tr6, r5, r4, r6\n-\tstr.w\tr1, [lr, r6, lsl #2]\n-\tbge.n\t3a02 <__gridxc_array_MOD_ac_1d_2d_ip+0x8e>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\titt\tlt\n+\tmovlt\tr3, sl\n+\taddlt\tr4, #1\n \tcmp\tip, r2\n-\tbne.n\t39ea <__gridxc_array_MOD_ac_1d_2d_ip+0x76>\n+\tstr.w\tr1, [lr, r6, lsl #2]\n+\tbne.n\t355a <__gridxc_array_MOD_ac_1d_2d_ip+0x72>\n \tcmp\tsl, r3\n-\tbeq.n\t3a18 <__gridxc_array_MOD_ac_1d_2d_ip+0xa4>\n-\tldr\tr3, [pc, #120]\t@ (3a84 <__gridxc_array_MOD_ac_1d_2d_ip+0x110>)\n+\tbeq.n\t3588 <__gridxc_array_MOD_ac_1d_2d_ip+0xa0>\n+\tldr\tr3, [pc, #120]\t@ (35f4 <__gridxc_array_MOD_ac_1d_2d_ip+0x10c>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #120]\t@ (3a88 <__gridxc_array_MOD_ac_1d_2d_ip+0x114>)\n+\tldr\tr0, [pc, #120]\t@ (35f8 <__gridxc_array_MOD_ac_1d_2d_ip+0x110>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr.w\tr3, [r8, #4]\n \tcmp\tr3, r4\n-\tblt.n\t3a34 <__gridxc_array_MOD_ac_1d_2d_ip+0xc0>\n-\tldr\tr3, [pc, #96]\t@ (3a84 <__gridxc_array_MOD_ac_1d_2d_ip+0x110>)\n+\tblt.n\t35a4 <__gridxc_array_MOD_ac_1d_2d_ip+0xbc>\n+\tldr\tr3, [pc, #96]\t@ (35f4 <__gridxc_array_MOD_ac_1d_2d_ip+0x10c>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #100]\t@ (3a8c <__gridxc_array_MOD_ac_1d_2d_ip+0x118>)\n+\tldr\tr0, [pc, #100]\t@ (35fc <__gridxc_array_MOD_ac_1d_2d_ip+0x114>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tadd.w\tip, r6, #4294967295\t@ 0xffffffff\n \tadds\tr1, #1\n-\tldr\tr0, [sp, #0]\n-\tstr.w\tr8, [sp]\n+\tstr.w\tr8, [sp, #4]\n \tmul.w\tip, r3, ip\n \tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #4]\n+\tstr\tr3, [sp, #0]\n \tmov\tr3, sl\n-\tldr.w\tr8, [sp, #4]\n+\tldr.w\tr8, [sp]\n \tadd.w\tr2, r2, ip, lsl #2\n-\tstr\tr7, [sp, #4]\n+\tstr\tr7, [sp, #0]\n \tmla\tip, r4, r5, r0\n \tldr\tr7, [r2, #0]\n \tmla\tip, r3, fp, ip\n \tadds\tr3, #1\n-\tadds\tr6, #1\n \tcmp\tr9, r3\n-\tstr.w\tr7, [lr, ip, lsl #2]\n-\tbge.n\t3a74 <__gridxc_array_MOD_ac_1d_2d_ip+0x100>\n-\tadds\tr4, #1\n-\tmov\tr3, sl\n+\tadd.w\tr6, r6, #1\n+\titt\tlt\n+\taddlt\tr4, #1\n+\tmovlt\tr3, sl\n \tadd\tr2, r8\n \tcmp\tr1, r6\n-\tbne.n\t3a5a <__gridxc_array_MOD_ac_1d_2d_ip+0xe6>\n-\tldrd\tr8, r7, [sp]\n-\tb.n\t3a06 <__gridxc_array_MOD_ac_1d_2d_ip+0x92>\n-\t.word\t0x000000ee\n+\tstr.w\tr7, [lr, ip, lsl #2]\n+\tbne.n\t35c8 <__gridxc_array_MOD_ac_1d_2d_ip+0xe0>\n+\tldrd\tr7, r8, [sp]\n+\tb.n\t3576 <__gridxc_array_MOD_ac_1d_2d_ip+0x8e>\n+\t.word\t0x000000ea\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000074\n R_ARM_REL32\t.LC58\n \t.word\t0x00000062\n R_ARM_REL32\t.LC59\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "atomxc.F90.o", "source2": "atomxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 20052 (bytes into file)\n+ Start of section headers: 19880 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x4e54:\n+There are 12 section headers, starting at offset 0x4da8:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 00364c 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 004584 000868 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 003684 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 003688 000270 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 003688 00024c 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0038d8 000028 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 003900 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 003900 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 003934 000740 10 10 77 4\n- [10] .strtab STRTAB 00000000 004074 00050e 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 004dec 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0035e0 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0044d0 000870 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 003618 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 003618 000270 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 003618 00024c 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 003868 000028 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 003890 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 003890 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 0038c0 000700 10 10 73 4\n+ [10] .strtab STRTAB 00000000 003fc0 00050e 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 004d40 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Symbol table '.symtab' contains 116 entries:\n+Symbol table '.symtab' contains 112 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 4: 00000018 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 5: 0000001c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n@@ -35,85 +35,81 @@\n 31: 0000021c 0 NOTYPE LOCAL DEFAULT 5 .LC35\n 32: 00000228 0 NOTYPE LOCAL DEFAULT 5 .LC38\n 33: 00000230 0 NOTYPE LOCAL DEFAULT 5 .LC39\n 34: 00000238 0 NOTYPE LOCAL DEFAULT 5 .LC40\n 35: 00000240 0 NOTYPE LOCAL DEFAULT 5 .LC41\n 36: 00000248 0 NOTYPE LOCAL DEFAULT 5 .LC42\n 37: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 38: 00000448 0 NOTYPE LOCAL DEFAULT 1 $d\n- 39: 000004ac 0 NOTYPE LOCAL DEFAULT 1 $t\n- 40: 00000770 0 NOTYPE LOCAL DEFAULT 1 $d\n- 41: 000007a0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 42: 000011a8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 43: 000011f0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 44: 00001a70 0 NOTYPE LOCAL DEFAULT 1 $d\n- 45: 00001aa4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 46: 00001ff0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 47: 00001ff8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 48: 000023e0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 49: 00002434 0 NOTYPE LOCAL DEFAULT 1 $t\n- 50: 00002660 0 NOTYPE LOCAL DEFAULT 1 $d\n- 51: 00002690 0 NOTYPE LOCAL DEFAULT 1 $t\n- 52: 00002a38 0 NOTYPE LOCAL DEFAULT 1 $d\n- 53: 00002a6c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 54: 00002d10 0 NOTYPE LOCAL DEFAULT 1 $d\n- 55: 00002d30 0 NOTYPE LOCAL DEFAULT 1 $t\n- 56: 00003150 0 NOTYPE LOCAL DEFAULT 1 $d\n- 57: 00003184 0 NOTYPE LOCAL DEFAULT 1 $t\n- 58: 00003570 0 NOTYPE LOCAL DEFAULT 1 $d\n- 59: 000035b0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 60: 00003634 0 NOTYPE LOCAL DEFAULT 1 $d\n- 61: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 62: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 63: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 64: 00000000 48 OBJECT LOCAL DEFAULT 4 d.12\n- 65: 00000030 48 OBJECT LOCAL DEFAULT 4 dgddd.11\n- 66: 00000060 36 OBJECT LOCAL DEFAULT 4 drdm.10\n- 67: 00000084 36 OBJECT LOCAL DEFAULT 4 dvol.9\n- 68: 000000a8 60 OBJECT LOCAL DEFAULT 4 gd.8\n- 69: 000000e4 48 OBJECT LOCAL DEFAULT 4 dtdd.7\n- 70: 00000114 60 OBJECT LOCAL DEFAULT 4 dtdgd.6\n- 71: 00000150 48 OBJECT LOCAL DEFAULT 4 dphidk.5\n- 72: 00000180 48 OBJECT LOCAL DEFAULT 4 phi.4\n- 73: 000001b0 48 OBJECT LOCAL DEFAULT 4 tk.3\n- 74: 000001e0 48 OBJECT LOCAL DEFAULT 4 tr.2\n- 75: 00000210 48 OBJECT LOCAL DEFAULT 4 uk.1\n- 76: 00000240 48 OBJECT LOCAL DEFAULT 4 ur.0\n- 77: 00000001 13900 FUNC GLOBAL DEFAULT 1 __gridxc_atom_MOD_atomxc\n- 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_xcmod_MOD_getxc\n- 79: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n- 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 81: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 82: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n- 83: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n- 84: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n- 85: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n- 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n- 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n- 88: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 89: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 90: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 91: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n- 92: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d1\n- 93: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n- 94: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n- 95: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_ldaxc\n- 96: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 97: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n- 98: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d3\n- 99: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d1\n- 100: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d2\n- 101: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gga_MOD_ggaxc\n- 102: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_localxc\n- 103: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_decusp\n- 104: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_theta\n- 105: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_get_qmesh\n- 106: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_kcut\n- 107: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_interpolation\n- 108: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_mesh\n- 109: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_interpolation_local\n- 110: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n- 111: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_radfft_MOD_radfft\n- 112: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_phi\n- 113: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_matmul_r8\n- 114: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n- 115: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 38: 00000740 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 39: 000007b4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 40: 000011a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 41: 000011e8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 42: 00001a38 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 43: 00001a74 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 44: 00001fb0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 45: 00001fc0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 46: 00002388 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 47: 000023e4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 48: 00002620 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 49: 00002658 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 50: 00002a00 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 51: 00002a24 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 52: 00002cc8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 53: 00002cdc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 54: 00003128 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 55: 00003154 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 56: 00003590 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 57: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 58: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 59: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 60: 00000000 48 OBJECT LOCAL DEFAULT 4 d.12\n+ 61: 00000030 48 OBJECT LOCAL DEFAULT 4 dgddd.11\n+ 62: 00000060 36 OBJECT LOCAL DEFAULT 4 drdm.10\n+ 63: 00000084 36 OBJECT LOCAL DEFAULT 4 dvol.9\n+ 64: 000000a8 60 OBJECT LOCAL DEFAULT 4 gd.8\n+ 65: 000000e4 48 OBJECT LOCAL DEFAULT 4 dtdd.7\n+ 66: 00000114 60 OBJECT LOCAL DEFAULT 4 dtdgd.6\n+ 67: 00000150 48 OBJECT LOCAL DEFAULT 4 dphidk.5\n+ 68: 00000180 48 OBJECT LOCAL DEFAULT 4 phi.4\n+ 69: 000001b0 48 OBJECT LOCAL DEFAULT 4 tk.3\n+ 70: 000001e0 48 OBJECT LOCAL DEFAULT 4 tr.2\n+ 71: 00000210 48 OBJECT LOCAL DEFAULT 4 uk.1\n+ 72: 00000240 48 OBJECT LOCAL DEFAULT 4 ur.0\n+ 73: 00000001 13792 FUNC GLOBAL DEFAULT 1 __gridxc_atom_MOD_atomxc\n+ 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_xcmod_MOD_getxc\n+ 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n+ 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n+ 79: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n+ 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n+ 81: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n+ 82: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n+ 83: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+ 84: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n+ 85: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d1\n+ 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n+ 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 88: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 89: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 90: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n+ 91: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_ldaxc\n+ 92: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 93: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n+ 94: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d3\n+ 95: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d1\n+ 96: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d2\n+ 97: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gga_MOD_ggaxc\n+ 98: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_localxc\n+ 99: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_decusp\n+ 100: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_theta\n+ 101: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_get_qmesh\n+ 102: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_kcut\n+ 103: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_interpolation\n+ 104: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_mesh\n+ 105: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_interpolation_local\n+ 106: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n+ 107: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_radfft_MOD_radfft\n+ 108: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_phi\n+ 109: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_matmul_r8\n+ 110: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 111: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,272 +1,273 @@\n \n-Relocation section '.rel.text' at offset 0x4584 contains 269 entries:\n+Relocation section '.rel.text' at offset 0x44d0 contains 270 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000204 00004e0a R_ARM_THM_CALL 00000000 __gridxc_xcmod_MOD_getxc\n-0000022e 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000242 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000256 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000026a 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000027e 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000028e 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000029e 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000002ae 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000002cc 0000500a R_ARM_THM_CALL 00000000 malloc\n-000002dc 0000510a R_ARM_THM_CALL 00000000 memset\n-000002e2 0000500a R_ARM_THM_CALL 00000000 malloc\n-000002f2 0000510a R_ARM_THM_CALL 00000000 memset\n-000002f8 0000500a R_ARM_THM_CALL 00000000 malloc\n-00000308 0000510a R_ARM_THM_CALL 00000000 memset\n-000003a6 0000520a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-000003b0 0000530a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n-000003b6 0000540a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-000003da 0000550a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000416 0000560a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n-0000041c 0000570a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n-00000470 00005819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000474 00005819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000478 0000591a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000047c 00005a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000480 00000303 R_ARM_REL32 00000000 .LC0\n-00000484 00000403 R_ARM_REL32 00000018 .LC1\n-00000488 00000503 R_ARM_REL32 0000001c .LC2\n-0000048c 00000603 R_ARM_REL32 00000020 .LC3\n-00000490 00000703 R_ARM_REL32 00000024 .LC4\n-00000494 00000803 R_ARM_REL32 00000028 .LC5\n-00000498 00000903 R_ARM_REL32 0000002c .LC6\n-0000049c 00000a03 R_ARM_REL32 00000030 .LC7\n-000004a0 00000b03 R_ARM_REL32 00000034 .LC8\n-000004a4 00001003 R_ARM_REL32 00000128 .LC14\n-000004a8 00001103 R_ARM_REL32 00000160 .LC15\n-000004f6 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000051c 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00000538 00005c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00000554 00005c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00000584 00005d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00000780 00001203 R_ARM_REL32 00000174 .LC17\n-00000784 00003d03 R_ARM_REL32 00000000 .rodata\n-00000788 00000103 R_ARM_REL32 00000000 .bss\n-0000078c 00001303 R_ARM_REL32 00000180 .LC20\n-00000790 00001403 R_ARM_REL32 00000190 .LC21\n-00000794 00001503 R_ARM_REL32 0000019c .LC22\n-00000798 00001603 R_ARM_REL32 000001a8 .LC24\n+00000224 00004a0a R_ARM_THM_CALL 00000000 __gridxc_xcmod_MOD_getxc\n+00000250 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000266 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000027c 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000292 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000002a8 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000002ba 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000002cc 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000002de 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000300 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00000310 00004d0a R_ARM_THM_CALL 00000000 memset\n+00000316 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00000326 00004d0a R_ARM_THM_CALL 00000000 memset\n+0000032c 00004c0a R_ARM_THM_CALL 00000000 malloc\n+0000033c 00004d0a R_ARM_THM_CALL 00000000 memset\n+000003da 00004e0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+000003ee 00004f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n+000003f4 0000500a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+00000418 0000510a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000460 0000520a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n+00000466 0000530a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+000004d8 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+000004fe 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00000518 0000550a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00000532 0000550a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00000560 0000560a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00000758 00005719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000075c 00005719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000760 0000581a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000764 0000591a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000768 00000303 R_ARM_REL32 00000000 .LC0\n+0000076c 00000403 R_ARM_REL32 00000018 .LC1\n+00000770 00000503 R_ARM_REL32 0000001c .LC2\n+00000774 00000603 R_ARM_REL32 00000020 .LC3\n+00000778 00000703 R_ARM_REL32 00000024 .LC4\n+0000077c 00000803 R_ARM_REL32 00000028 .LC5\n+00000780 00000903 R_ARM_REL32 0000002c .LC6\n+00000784 00000a03 R_ARM_REL32 00000030 .LC7\n+00000788 00000b03 R_ARM_REL32 00000034 .LC8\n+0000078c 00001003 R_ARM_REL32 00000128 .LC14\n+00000790 00001103 R_ARM_REL32 00000160 .LC15\n+00000794 00001203 R_ARM_REL32 00000174 .LC17\n+00000798 00003903 R_ARM_REL32 00000000 .rodata\n 0000079c 00000103 R_ARM_REL32 00000000 .bss\n-00000a96 0000510a R_ARM_THM_CALL 00000000 memset\n-00000b9a 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000bdc 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000bf2 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000c08 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000c46 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000c90 00005f0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n-00000c9a 0000600a R_ARM_THM_CALL 00000000 free\n-00000f64 0000610a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n-00000f70 0000600a R_ARM_THM_CALL 00000000 free\n-00000f76 0000600a R_ARM_THM_CALL 00000000 free\n-00000f7c 0000600a R_ARM_THM_CALL 00000000 free\n-000010c0 0000620a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n-000010d2 0000630a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-000010e4 0000630a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-000010f6 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-00001106 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+000007a0 00001303 R_ARM_REL32 00000180 .LC20\n+000007a4 00001403 R_ARM_REL32 00000190 .LC21\n+000007a8 00001503 R_ARM_REL32 0000019c .LC22\n+000007ac 00001603 R_ARM_REL32 000001a8 .LC24\n+000007b0 00000103 R_ARM_REL32 00000000 .bss\n+00000a9c 00004d0a R_ARM_THM_CALL 00000000 memset\n+00000bae 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000bf0 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000c06 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000c1c 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000c56 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000c9c 00005b0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n+00000ca6 00005c0a R_ARM_THM_CALL 00000000 free\n+00000f4e 00005d0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n+00000f5a 00005c0a R_ARM_THM_CALL 00000000 free\n+00000f60 00005c0a R_ARM_THM_CALL 00000000 free\n+00000f66 00005c0a R_ARM_THM_CALL 00000000 free\n+000010a8 00005e0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n+000010ba 00005f0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+000010cc 00005f0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+000010de 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+000010ee 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+000011a8 00000103 R_ARM_REL32 00000000 .bss\n+000011ac 00000403 R_ARM_REL32 00000018 .LC1\n 000011b0 00000103 R_ARM_REL32 00000000 .bss\n-000011b4 00000103 R_ARM_REL32 00000000 .bss\n-000011b8 00000403 R_ARM_REL32 00000018 .LC1\n-000011bc 00000103 R_ARM_REL32 00000000 .bss\n-000011c0 00000503 R_ARM_REL32 0000001c .LC2\n-000011c4 00000603 R_ARM_REL32 00000020 .LC3\n-000011c8 00000703 R_ARM_REL32 00000024 .LC4\n-000011cc 00000103 R_ARM_REL32 00000000 .bss\n-000011d0 00000103 R_ARM_REL32 00000000 .bss\n-000011d4 00001603 R_ARM_REL32 000001a8 .LC24\n-000011d8 00001503 R_ARM_REL32 0000019c .LC22\n-000011dc 00001403 R_ARM_REL32 00000190 .LC21\n-000011e0 00001303 R_ARM_REL32 00000180 .LC20\n-000011e4 00001203 R_ARM_REL32 00000174 .LC17\n-000011e8 00005819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000011ec 0000591a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001200 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001212 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001224 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001236 00004f0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001276 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000012fa 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-0000134c 0000650a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00001356 0000600a R_ARM_THM_CALL 00000000 free\n-00001360 0000600a R_ARM_THM_CALL 00000000 free\n-000013e0 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00001478 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000014b2 0000660a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_localxc\n-000014bc 0000600a R_ARM_THM_CALL 00000000 free\n-000014c6 0000600a R_ARM_THM_CALL 00000000 free\n-00001538 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000015ca 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000015ec 0000670a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_decusp\n-000015f6 0000600a R_ARM_THM_CALL 00000000 free\n-00001600 0000600a R_ARM_THM_CALL 00000000 free\n-0000166a 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000016fc 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00001778 0000680a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n-00001786 0000600a R_ARM_THM_CALL 00000000 free\n-00001794 0000600a R_ARM_THM_CALL 00000000 free\n-00001a78 00002003 R_ARM_REL32 00000228 .LC38\n-00001a7c 00002103 R_ARM_REL32 00000230 .LC39\n-00001a80 00002203 R_ARM_REL32 00000238 .LC40\n-00001a84 00002303 R_ARM_REL32 00000240 .LC41\n-00001a88 00000103 R_ARM_REL32 00000000 .bss\n-00001a8c 00002403 R_ARM_REL32 00000248 .LC42\n-00001a90 00000103 R_ARM_REL32 00000000 .bss\n-00001a94 00000103 R_ARM_REL32 00000000 .bss\n-00001a98 00000103 R_ARM_REL32 00000000 .bss\n-00001a9c 00000103 R_ARM_REL32 00000000 .bss\n-00001aa0 00000103 R_ARM_REL32 00000000 .bss\n-0000202c 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000020b6 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002106 0000650a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00002110 0000600a R_ARM_THM_CALL 00000000 free\n-0000211c 0000600a R_ARM_THM_CALL 00000000 free\n-000021fe 0000500a R_ARM_THM_CALL 00000000 malloc\n-0000220c 0000500a R_ARM_THM_CALL 00000000 malloc\n-0000221a 0000500a R_ARM_THM_CALL 00000000 malloc\n-00002252 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000227c 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000229a 00005c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-000022b4 00005c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-000022de 00005d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00002358 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-0000236a 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-0000237c 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-0000238e 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-000023a0 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-000023b2 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-000023c4 0000620a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n-000023d6 0000640a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-000023f0 00000103 R_ARM_REL32 00000000 .bss\n-000023f4 00001203 R_ARM_REL32 00000174 .LC17\n-000023f8 00003d03 R_ARM_REL32 00000000 .rodata\n-000023fc 00000103 R_ARM_REL32 00000000 .bss\n-00002400 00001303 R_ARM_REL32 00000180 .LC20\n-00002404 00001403 R_ARM_REL32 00000190 .LC21\n-00002408 00001503 R_ARM_REL32 0000019c .LC22\n-0000240c 00001603 R_ARM_REL32 000001a8 .LC24\n-00002410 00000103 R_ARM_REL32 00000000 .bss\n-00002414 00001e03 R_ARM_REL32 00000210 .LC34\n-00002418 00001d03 R_ARM_REL32 00000204 .LC33\n-0000241c 00001c03 R_ARM_REL32 000001f8 .LC32\n-00002420 00001b03 R_ARM_REL32 000001ec .LC31\n-00002424 00001a03 R_ARM_REL32 000001e0 .LC28\n-00002428 00001903 R_ARM_REL32 000001d0 .LC27\n-0000242c 00001803 R_ARM_REL32 000001c0 .LC26\n-00002430 00001703 R_ARM_REL32 000001b4 .LC25\n-00002442 0000690a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n-00002474 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000249c 00005d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-000024be 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-000024e0 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00002508 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000252a 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000254c 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000256e 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00002668 00003d03 R_ARM_REL32 00000000 .rodata\n-0000266c 00000103 R_ARM_REL32 00000000 .bss\n-00002670 00001703 R_ARM_REL32 000001b4 .LC25\n-00002674 00001803 R_ARM_REL32 000001c0 .LC26\n-00002678 00001903 R_ARM_REL32 000001d0 .LC27\n-0000267c 00001a03 R_ARM_REL32 000001e0 .LC28\n-00002680 00001b03 R_ARM_REL32 000001ec .LC31\n-00002684 00001c03 R_ARM_REL32 000001f8 .LC32\n-00002688 00001d03 R_ARM_REL32 00000204 .LC33\n-0000268c 00001e03 R_ARM_REL32 00000210 .LC34\n-000026b6 00006a0a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n-0000275a 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000027e6 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002860 0000680a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n-0000286e 0000600a R_ARM_THM_CALL 00000000 free\n-00002882 0000600a R_ARM_THM_CALL 00000000 free\n-000028f8 00006b0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_interpolation\n-00002908 00006c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-000029c0 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000029fc 00006d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n-00002a06 0000600a R_ARM_THM_CALL 00000000 free\n-00002a58 00000103 R_ARM_REL32 00000000 .bss\n-00002a5c 00001f03 R_ARM_REL32 0000021c .LC35\n-00002a60 00000103 R_ARM_REL32 00000000 .bss\n-00002a64 00003d03 R_ARM_REL32 00000000 .rodata\n-00002a68 00000103 R_ARM_REL32 00000000 .bss\n-00002ac4 00006e0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00002ace 0000600a R_ARM_THM_CALL 00000000 free\n-00002b2c 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002b88 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002ba0 00006f0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-00002baa 0000600a R_ARM_THM_CALL 00000000 free\n-00002c26 0000700a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_phi\n-00002c8a 0000500a R_ARM_THM_CALL 00000000 malloc\n-00002d20 00000103 R_ARM_REL32 00000000 .bss\n-00002d24 00000103 R_ARM_REL32 00000000 .bss\n-00002d28 00003d03 R_ARM_REL32 00000000 .rodata\n-00002d2c 00000103 R_ARM_REL32 00000000 .bss\n-00002d78 0000500a R_ARM_THM_CALL 00000000 malloc\n-00002e64 0000600a R_ARM_THM_CALL 00000000 free\n-00002e72 0000600a R_ARM_THM_CALL 00000000 free\n-00002f34 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002f90 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00002fa8 00006f0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-00002fb2 0000600a R_ARM_THM_CALL 00000000 free\n-00002fc4 00006e0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00002fce 0000600a R_ARM_THM_CALL 00000000 free\n-00002ff0 00006c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-000030ac 00005e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-0000312e 00006d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n-00003164 00000103 R_ARM_REL32 00000000 .bss\n-00003168 00000103 R_ARM_REL32 00000000 .bss\n-0000316c 00000103 R_ARM_REL32 00000000 .bss\n-00003170 00003d03 R_ARM_REL32 00000000 .rodata\n-00003174 00003d03 R_ARM_REL32 00000000 .rodata\n-00003178 00000103 R_ARM_REL32 00000000 .bss\n-0000317c 00003d03 R_ARM_REL32 00000000 .rodata\n-00003180 00000103 R_ARM_REL32 00000000 .bss\n-00003216 0000500a R_ARM_THM_CALL 00000000 malloc\n-0000327a 0000710a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n-000032c0 0000600a R_ARM_THM_CALL 00000000 free\n-000032f0 00006d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n-000032fc 0000600a R_ARM_THM_CALL 00000000 free\n-00003316 0000600a R_ARM_THM_CALL 00000000 free\n-0000331e 0000600a R_ARM_THM_CALL 00000000 free\n-0000335e 0000600a R_ARM_THM_CALL 00000000 free\n-00003364 0000600a R_ARM_THM_CALL 00000000 free\n-0000336a 0000600a R_ARM_THM_CALL 00000000 free\n-000033e2 0000690a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n-00003408 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003434 00005d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00003458 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000347c 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-000034a0 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-000034c8 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-000034ec 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003510 00005b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000352a 00006a0a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n-00003558 00006c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-0000356c 0000720a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00003574 00000103 R_ARM_REL32 00000000 .bss\n-00003578 00000103 R_ARM_REL32 00000000 .bss\n-0000357c 00003d03 R_ARM_REL32 00000000 .rodata\n-00003580 00000103 R_ARM_REL32 00000000 .bss\n-00003584 00001703 R_ARM_REL32 000001b4 .LC25\n-00003588 00001803 R_ARM_REL32 000001c0 .LC26\n-0000358c 00001903 R_ARM_REL32 000001d0 .LC27\n-00003590 00001a03 R_ARM_REL32 000001e0 .LC28\n-00003594 00001b03 R_ARM_REL32 000001ec .LC31\n-00003598 00001c03 R_ARM_REL32 000001f8 .LC32\n-0000359c 00001d03 R_ARM_REL32 00000204 .LC33\n-000035a0 00001e03 R_ARM_REL32 00000210 .LC34\n-000035a4 00003d03 R_ARM_REL32 00000000 .rodata\n-000035a8 00000d03 R_ARM_REL32 0000005c .LC10\n-000035ac 00000f03 R_ARM_REL32 000000cc .LC12\n-000035bc 0000720a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000035cc 0000720a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000035d0 0000730a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000035ec 0000550a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00003634 00000d03 R_ARM_REL32 0000005c .LC10\n-00003638 00000f03 R_ARM_REL32 000000cc .LC12\n-0000363c 00000d03 R_ARM_REL32 0000005c .LC10\n-00003640 00000e03 R_ARM_REL32 00000078 .LC11\n-00003644 00000c03 R_ARM_REL32 00000038 .LC9\n-00003648 00005a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000011b4 00000503 R_ARM_REL32 0000001c .LC2\n+000011b8 00000603 R_ARM_REL32 00000020 .LC3\n+000011bc 00000703 R_ARM_REL32 00000024 .LC4\n+000011c0 00000103 R_ARM_REL32 00000000 .bss\n+000011c4 00000103 R_ARM_REL32 00000000 .bss\n+000011c8 00000103 R_ARM_REL32 00000000 .bss\n+000011cc 00001603 R_ARM_REL32 000001a8 .LC24\n+000011d0 00001503 R_ARM_REL32 0000019c .LC22\n+000011d4 00001403 R_ARM_REL32 00000190 .LC21\n+000011d8 00001303 R_ARM_REL32 00000180 .LC20\n+000011dc 00001203 R_ARM_REL32 00000174 .LC17\n+000011e0 00005719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000011e4 0000581a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000011f8 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000120a 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000121c 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000122e 00004b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001270 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000012fe 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000134c 0000610a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00001356 00005c0a R_ARM_THM_CALL 00000000 free\n+00001360 00005c0a R_ARM_THM_CALL 00000000 free\n+000013e8 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00001476 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000014ac 0000620a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_localxc\n+000014b6 00005c0a R_ARM_THM_CALL 00000000 free\n+000014c0 00005c0a R_ARM_THM_CALL 00000000 free\n+00001526 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000015aa 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000015d0 0000630a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_decusp\n+000015da 00005c0a R_ARM_THM_CALL 00000000 free\n+000015e4 00005c0a R_ARM_THM_CALL 00000000 free\n+0000164c 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000016da 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000175e 0000640a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n+0000176c 00005c0a R_ARM_THM_CALL 00000000 free\n+00001776 00005c0a R_ARM_THM_CALL 00000000 free\n+00001a48 00002003 R_ARM_REL32 00000228 .LC38\n+00001a4c 00002103 R_ARM_REL32 00000230 .LC39\n+00001a50 00002203 R_ARM_REL32 00000238 .LC40\n+00001a54 00002303 R_ARM_REL32 00000240 .LC41\n+00001a58 00000103 R_ARM_REL32 00000000 .bss\n+00001a5c 00002403 R_ARM_REL32 00000248 .LC42\n+00001a60 00000103 R_ARM_REL32 00000000 .bss\n+00001a64 00000103 R_ARM_REL32 00000000 .bss\n+00001a68 00000103 R_ARM_REL32 00000000 .bss\n+00001a6c 00000103 R_ARM_REL32 00000000 .bss\n+00001a70 00000103 R_ARM_REL32 00000000 .bss\n+00001ff8 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002086 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000020d2 0000610a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+000020dc 00005c0a R_ARM_THM_CALL 00000000 free\n+000020e8 00005c0a R_ARM_THM_CALL 00000000 free\n+000021a6 00004c0a R_ARM_THM_CALL 00000000 malloc\n+000021b4 00004c0a R_ARM_THM_CALL 00000000 malloc\n+000021c2 00004c0a R_ARM_THM_CALL 00000000 malloc\n+000021f8 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002222 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002240 0000550a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+0000225a 0000550a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00002284 0000560a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00002300 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+00002312 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+00002324 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+00002336 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+00002348 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+0000235a 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+0000236c 00005e0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n+0000237e 0000600a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+000023a0 00000103 R_ARM_REL32 00000000 .bss\n+000023a4 00001203 R_ARM_REL32 00000174 .LC17\n+000023a8 00003903 R_ARM_REL32 00000000 .rodata\n+000023ac 00000103 R_ARM_REL32 00000000 .bss\n+000023b0 00001303 R_ARM_REL32 00000180 .LC20\n+000023b4 00001403 R_ARM_REL32 00000190 .LC21\n+000023b8 00001503 R_ARM_REL32 0000019c .LC22\n+000023bc 00001603 R_ARM_REL32 000001a8 .LC24\n+000023c0 00000103 R_ARM_REL32 00000000 .bss\n+000023c4 00001e03 R_ARM_REL32 00000210 .LC34\n+000023c8 00001d03 R_ARM_REL32 00000204 .LC33\n+000023cc 00001c03 R_ARM_REL32 000001f8 .LC32\n+000023d0 00001b03 R_ARM_REL32 000001ec .LC31\n+000023d4 00001a03 R_ARM_REL32 000001e0 .LC28\n+000023d8 00001903 R_ARM_REL32 000001d0 .LC27\n+000023dc 00001803 R_ARM_REL32 000001c0 .LC26\n+000023e0 00001703 R_ARM_REL32 000001b4 .LC25\n+000023f2 0000650a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n+00002424 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+0000244e 0000560a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00002470 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002492 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+000024ba 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+000024de 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002502 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002526 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00002630 00000103 R_ARM_REL32 00000000 .bss\n+00002634 00003903 R_ARM_REL32 00000000 .rodata\n+00002638 00001703 R_ARM_REL32 000001b4 .LC25\n+0000263c 00001803 R_ARM_REL32 000001c0 .LC26\n+00002640 00001903 R_ARM_REL32 000001d0 .LC27\n+00002644 00001a03 R_ARM_REL32 000001e0 .LC28\n+00002648 00001b03 R_ARM_REL32 000001ec .LC31\n+0000264c 00001c03 R_ARM_REL32 000001f8 .LC32\n+00002650 00001d03 R_ARM_REL32 00000204 .LC33\n+00002654 00001e03 R_ARM_REL32 00000210 .LC34\n+0000268c 0000660a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n+0000271e 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000027ae 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000282e 0000640a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n+0000283c 00005c0a R_ARM_THM_CALL 00000000 free\n+00002850 00005c0a R_ARM_THM_CALL 00000000 free\n+000028c8 0000670a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_interpolation\n+000028dc 0000680a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00002972 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000029be 0000690a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n+000029cc 00005c0a R_ARM_THM_CALL 00000000 free\n+00002a10 00000103 R_ARM_REL32 00000000 .bss\n+00002a14 00001f03 R_ARM_REL32 0000021c .LC35\n+00002a18 00003903 R_ARM_REL32 00000000 .rodata\n+00002a1c 00000103 R_ARM_REL32 00000000 .bss\n+00002a20 00000103 R_ARM_REL32 00000000 .bss\n+00002a62 00006a0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00002a6c 00005c0a R_ARM_THM_CALL 00000000 free\n+00002ada 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002b36 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002b4a 00006b0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+00002b58 00005c0a R_ARM_THM_CALL 00000000 free\n+00002bde 00006c0a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_phi\n+00002c44 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00002ccc 00003903 R_ARM_REL32 00000000 .rodata\n+00002cd0 00000103 R_ARM_REL32 00000000 .bss\n+00002cd4 00000103 R_ARM_REL32 00000000 .bss\n+00002cd8 00000103 R_ARM_REL32 00000000 .bss\n+00002d20 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00002e12 00005c0a R_ARM_THM_CALL 00000000 free\n+00002e22 00005c0a R_ARM_THM_CALL 00000000 free\n+00002ee4 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002f40 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002f54 00006b0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+00002f62 00005c0a R_ARM_THM_CALL 00000000 free\n+00002f74 00006a0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00002f7e 00005c0a R_ARM_THM_CALL 00000000 free\n+00002fa0 0000680a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+0000304e 00005a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000030d6 0000690a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n+00003130 00000103 R_ARM_REL32 00000000 .bss\n+00003134 00000103 R_ARM_REL32 00000000 .bss\n+00003138 00003903 R_ARM_REL32 00000000 .rodata\n+0000313c 00000103 R_ARM_REL32 00000000 .bss\n+00003140 00003903 R_ARM_REL32 00000000 .rodata\n+00003144 00000103 R_ARM_REL32 00000000 .bss\n+00003148 00003903 R_ARM_REL32 00000000 .rodata\n+0000314c 00000103 R_ARM_REL32 00000000 .bss\n+00003150 00000103 R_ARM_REL32 00000000 .bss\n+000031b0 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00003216 00006d0a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n+0000325c 00005c0a R_ARM_THM_CALL 00000000 free\n+00003290 0000690a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_interpolation_local\n+0000329c 00005c0a R_ARM_THM_CALL 00000000 free\n+000032b6 00005c0a R_ARM_THM_CALL 00000000 free\n+000032be 00005c0a R_ARM_THM_CALL 00000000 free\n+000032f8 0000650a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n+0000331c 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+0000334a 0000560a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+0000336e 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003392 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+000033b6 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+000033dc 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003400 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003426 0000540a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+0000343e 0000660a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n+00003470 00005c0a R_ARM_THM_CALL 00000000 free\n+00003476 00005c0a R_ARM_THM_CALL 00000000 free\n+0000347c 00005c0a R_ARM_THM_CALL 00000000 free\n+000034e0 00006e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000034fc 0000510a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00003522 00006f0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003532 00006f0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003542 00006f0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003560 0000660a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n+00003584 0000680a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00003590 00000103 R_ARM_REL32 00000000 .bss\n+00003594 00003903 R_ARM_REL32 00000000 .rodata\n+00003598 00000103 R_ARM_REL32 00000000 .bss\n+0000359c 00001703 R_ARM_REL32 000001b4 .LC25\n+000035a0 00001803 R_ARM_REL32 000001c0 .LC26\n+000035a4 00001903 R_ARM_REL32 000001d0 .LC27\n+000035a8 00001a03 R_ARM_REL32 000001e0 .LC28\n+000035ac 00001b03 R_ARM_REL32 000001ec .LC31\n+000035b0 00001c03 R_ARM_REL32 000001f8 .LC32\n+000035b4 00001d03 R_ARM_REL32 00000204 .LC33\n+000035b8 00001e03 R_ARM_REL32 00000210 .LC34\n+000035bc 00000c03 R_ARM_REL32 00000038 .LC9\n+000035c0 0000591a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000035c4 00000d03 R_ARM_REL32 0000005c .LC10\n+000035c8 00000e03 R_ARM_REL32 00000078 .LC11\n+000035cc 00000d03 R_ARM_REL32 0000005c .LC10\n+000035d0 00000f03 R_ARM_REL32 000000cc .LC12\n+000035d4 00000d03 R_ARM_REL32 0000005c .LC10\n+000035d8 00000f03 R_ARM_REL32 000000cc .LC12\n+000035dc 00003903 R_ARM_REL32 00000000 .rodata\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,22 +1,23 @@\n-DCFRFAFHF\n-0NyD8l;c\n-$HI\t#}D\"FyD\n-ZKJF1F{D\n-$2I\"F}D\t#\n-~JSFQFzD\n-uJSFQFzD\n-nJSFQFzD\n- !AFxDSF\n-TKZFAF{D\t\n-LKZFAF{D\t\n-C2FBK)F\t\n-C2F1K)F\t\n-F I\"F HyDxD\n-KYF!\"5 {D\n+0e+F%F:\n __gridxc_atom_MOD_atomxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n+\tvpush\t{d8-d13}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n-\tstr.w\tr0, [ip, #2232]\t@ 0x8b8\n+\tstr.w\tr0, [ip, #2216]\t@ 0x8a8\n \tsub.w\tsp, sp, #14080\t@ 0x3700\n \tmov\tr6, r1\n \tsub\tsp, #4\n \tadd\tr7, sp, #48\t@ 0x30\n-\tldr.w\tr4, [pc, #1080]\t@ 470 <__gridxc_atom_MOD_atomxc+0x470>\n+\tldr.w\tr4, [pc, #1824]\t@ 758 <__gridxc_atom_MOD_atomxc+0x758>\n \tadd.w\tip, r7, #14016\t@ 0x36c0\n \tldr\tr2, [r2, #0]\n \tadd\tr4, pc\n \tadd.w\tip, ip, #12\n-\tstr.w\tr1, [r7, #232]\t@ 0xe8\n+\tstr.w\tr1, [r7, #256]\t@ 0x100\n \tadd.w\tr1, r7, #14080\t@ 0x3700\n-\tadds\tr1, #24\n-\tldr.w\tsl, [pc, #1056]\t@ 474 <__gridxc_atom_MOD_atomxc+0x474>\n+\tadds\tr1, #40\t@ 0x28\n+\tldr.w\tfp, [pc, #1800]\t@ 75c <__gridxc_atom_MOD_atomxc+0x75c>\n \tldr\tr5, [r1, #0]\n-\tadd\tsl, pc\n-\tldr.w\tr1, [pc, #1052]\t@ 478 <__gridxc_atom_MOD_atomxc+0x478>\n-\tstr.w\tr5, [r7, #204]\t@ 0xcc\n+\tadd\tfp, pc\n+\tldr.w\tr1, [pc, #1796]\t@ 760 <__gridxc_atom_MOD_atomxc+0x760>\n+\tstr.w\tr5, [r7, #220]\t@ 0xdc\n \tldr\tr1, [r4, r1]\n \tldr\tr1, [r1, #0]\n \tstr.w\tr1, [ip]\n \tmov.w\tr1, #0\n \tstr.w\tr0, [r7, #128]\t@ 0x80\n \tadd.w\tr0, r7, #14080\t@ 0x3700\n \tadd.w\tr1, r7, #14080\t@ 0x3700\n-\tadds\tr0, #32\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n+\tadds\tr0, #48\t@ 0x30\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n \tldr\tr3, [r6, #0]\n-\tadds\tr1, #28\n+\tadds\tr1, #44\t@ 0x2c\n \tldr\tr4, [r1, #0]\n \tbic.w\tr1, r2, r2, asr #31\n \tldr\tr0, [r0, #0]\n \tcmp\tr3, r2\n-\tstr.w\tr0, [r7, #196]\t@ 0xc4\n+\tstr.w\tr0, [r7, #212]\t@ 0xd4\n \tadd.w\tr0, r7, #14080\t@ 0x3700\n-\tadd.w\tr0, r0, #36\t@ 0x24\n-\tstr\tr1, [r7, #100]\t@ 0x64\n-\tstr\tr4, [r7, #64]\t@ 0x40\n+\tadd.w\tr0, r0, #52\t@ 0x34\n+\tstr\tr1, [r7, #84]\t@ 0x54\n+\tstr\tr4, [r7, #72]\t@ 0x48\n \tmvn.w\tr1, r1\n-\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tstr.w\tr3, [r7, #144]\t@ 0x90\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #192]\t@ 0xc0\n+\tstr.w\tr0, [r7, #208]\t@ 0xd0\n \tadd.w\tr0, r7, #14080\t@ 0x3700\n-\tadd.w\tr0, r0, #40\t@ 0x28\n-\tstr\tr1, [r7, #44]\t@ 0x2c\n+\tadd.w\tr0, r0, #56\t@ 0x38\n+\tstr\tr1, [r7, #56]\t@ 0x38\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #188]\t@ 0xbc\n+\tstr.w\tr0, [r7, #204]\t@ 0xcc\n \tadd.w\tr0, r7, #14080\t@ 0x3700\n-\tadd.w\tr0, r0, #44\t@ 0x2c\n+\tadd.w\tr0, r0, #60\t@ 0x3c\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr0, [r7, #184]\t@ 0xb8\n-\tadd.w\tr0, r7, #14080\t@ 0x3700\n-\tadd.w\tr0, r0, #48\t@ 0x30\n+\tstr.w\tr0, [r7, #200]\t@ 0xc8\n+\tadd.w\tr0, r7, #14144\t@ 0x3740\n \tldr\tr0, [r0, #0]\n-\tstr\tr0, [r7, #68]\t@ 0x44\n+\tstr\tr0, [r7, #76]\t@ 0x4c\n \tldr\tr0, [r5, #0]\n-\tstr.w\tr0, [r7, #276]\t@ 0x114\n+\tstr.w\tr0, [r7, #280]\t@ 0x118\n \tble.n\tec <__gridxc_atom_MOD_atomxc+0xec>\n-\tldr\tr3, [pc, #924]\t@ (47c <__gridxc_atom_MOD_atomxc+0x47c>)\n+\tldr.w\tr3, [pc, #1672]\t@ 764 <__gridxc_atom_MOD_atomxc+0x764>\n \tmovs\tr1, #21\n-\tldr\tr0, [pc, #924]\t@ (480 <__gridxc_atom_MOD_atomxc+0x480>)\n+\tldr.w\tr0, [pc, #1672]\t@ 768 <__gridxc_atom_MOD_atomxc+0x768>\n \tadd\tr0, pc\n-\tldr.w\tr3, [sl, r3]\n+\tldr.w\tr3, [fp, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tadd.w\tr0, r7, #1744\t@ 0x6d0\n-\tvldr\td20, [pc, #848]\t@ 448 <__gridxc_atom_MOD_atomxc+0x448>\n-\tvldr\td21, [pc, #852]\t@ 450 <__gridxc_atom_MOD_atomxc+0x450>\n-\taddw\tr3, r7, #1148\t@ 0x47c\n \tadd.w\tr4, r7, #5824\t@ 0x16c0\n-\tadd.w\tr5, r7, #9920\t@ 0x26c0\n-\tvstr\td16, [r0, #-604]\t@ 0xfffffda4\n+\tadd.w\tsl, r7, #1744\t@ 0x6d0\n \tadds\tr4, #16\n-\tvst1.32\t{d20-d21}, [r3]\n-\taddw\tr3, r7, #1676\t@ 0x68c\n+\tadd.w\tr6, r7, #9920\t@ 0x26c0\n+\tsub.w\tr3, sl, #616\t@ 0x268\n+\tmov\tr0, r4\n+\tadds\tr6, #16\n+\tsub.w\tr2, sl, #604\t@ 0x25c\n+\tadd.w\tr5, r7, #5760\t@ 0x1680\n+\tmov.w\tr9, #10\n+\tsub.w\tlr, r6, #60\t@ 0x3c\n \tadds\tr5, #16\n-\tvldr\td18, [pc, #828]\t@ 458 <__gridxc_atom_MOD_atomxc+0x458>\n-\tvldr\td19, [pc, #832]\t@ 460 <__gridxc_atom_MOD_atomxc+0x460>\n-\tvstr\td16, [r0, #-76]\t@ 0xffffffb4\n-\tvst1.32\t{d20-d21}, [r3]\n-\tsub.w\tr3, r4, #60\t@ 0x3c\n-\tadd.w\tr6, r7, #336\t@ 0x150\n-\tvstr\td16, [r4, #-68]\t@ 0xffffffbc\n-\tadd.w\tip, r7, #1456\t@ 0x5b0\n-\tvst1.32\t{d18-d19}, [r3]\n-\tsub.w\tr3, r5, #52\t@ 0x34\n+\tadd.w\tr1, r7, #1680\t@ 0x690\n+\tstr\tr5, [r7, #20]\n+\tstr\tr1, [r7, #24]\n+\tadd.w\tr5, r7, #5760\t@ 0x1680\n+\tadd.w\tr1, r7, #1656\t@ 0x678\n+\tstr.w\tr5, [r7, #176]\t@ 0xb0\n+\tstr.w\tr1, [r7, #136]\t@ 0x88\n+\tadd.w\tr5, r7, #336\t@ 0x150\n \tadd.w\tr1, r7, #1128\t@ 0x468\n-\tstr.w\tr6, [r7, #240]\t@ 0xf0\n-\tmov\tr6, r4\n-\tvstr\td16, [r5, #-60]\t@ 0xffffffc4\n-\tadd.w\tr2, r7, #1680\t@ 0x690\n-\tvst1.32\t{d18-d19}, [r3]\n-\tadd.w\tr3, r7, #5760\t@ 0x1680\n-\tadds\tr3, #16\n-\tstr.w\tr0, [r7, #292]\t@ 0x124\n-\tstr\tr4, [r7, #16]\n-\tstr\tr3, [r7, #20]\n-\tadd.w\tr3, r7, #5760\t@ 0x1680\n-\tstr\tr2, [r7, #24]\n-\tadd.w\tr2, r7, #1656\t@ 0x678\n-\tstr.w\tr3, [r7, #164]\t@ 0xa4\n-\tmovs\tr3, #20\n-\tstr\tr2, [r7, #124]\t@ 0x7c\n-\tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n-\tadd.w\tr1, r7, #1256\t@ 0x4e8\n-\tstr.w\tr2, [r4, #-76]\n-\tmovs\tr4, #8\n-\tstr.w\tr2, [r5, #-68]\n-\tstr.w\tr3, [r7, #1136]\t@ 0x470\n-\tstr.w\tr3, [r7, #1664]\t@ 0x680\n-\tstr.w\tr2, [r7, #1132]\t@ 0x46c\n-\tstr.w\tr2, [r7, #1660]\t@ 0x67c\n-\tmovw\tr2, #1537\t@ 0x601\n-\tstr.w\tr4, [r6, #-72]\n-\tstr.w\tr4, [r5, #-64]\n-\tstrh.w\tr2, [r7, #1144]\t@ 0x478\n-\tstrh.w\tr2, [r7, #1672]\t@ 0x688\n-\tmovw\tr2, #769\t@ 0x301\n-\tstr.w\tr5, [r7, #280]\t@ 0x118\n-\tstrh.w\tr2, [r6, #-64]\n-\tstrh.w\tr2, [r5, #-56]\n-\tmov\tr5, r0\n-\tstr.w\tip, [r7, #52]\t@ 0x34\n-\tstr.w\tip, [r7, #1128]\t@ 0x468\n-\tstr\tr1, [r7, #56]\t@ 0x38\n-\tstr.w\tr1, [r7, #1656]\t@ 0x678\n-\tadd.w\tr1, r7, #672\t@ 0x2a0\n-\tldr.w\tr0, [r7, #280]\t@ 0x118\n-\tstr.w\tr1, [r6, #-80]\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tadd.w\tr1, r7, #592\t@ 0x250\n-\tstr.w\tr1, [r0, #-72]\n-\tadd.w\tr0, r7, #9856\t@ 0x2680\n-\tstr\tr1, [r7, #40]\t@ 0x28\n-\tadds\tr0, #8\n-\tstrd\tr3, r3, [sp, #4]\n-\tstr\tr0, [r7, #104]\t@ 0x68\n-\tstr\tr0, [sp, #0]\n-\tldr.w\tr6, [r7, #240]\t@ 0xf0\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n-\tldr\tr2, [r7, #124]\t@ 0x7c\n-\tsub.w\tr0, r6, #28\n-\tldr\tr1, [r7, #92]\t@ 0x5c\n+\tstr.w\tr5, [r7, #232]\t@ 0xe8\n+\tstr\tr1, [r7, #108]\t@ 0x6c\n+\tmovs\tr5, #0\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tstrd\tr5, r5, [r2]\n+\tstr.w\tr5, [r4, #-64]\n+\tmovs\tr2, #20\n+\tstr.w\tr5, [r4, #-68]\n+\tmovs\tr4, #1\n+\tstr\tr2, [r3, #20]\n+\tadd.w\tr8, r7, #1456\t@ 0x5b0\n+\tstr\tr2, [r3, #8]\n+\tmovw\tip, #1537\t@ 0x601\n+\tstr\tr1, [r3, #4]\n+\tstr.w\tr1, [r0, #-76]\n+\tstr.w\tr6, [r7, #236]\t@ 0xec\n+\tstr.w\tr5, [r6, #-60]\n+\tmovs\tr6, #8\n+\tstrd\tr4, r4, [r3, #24]\n+\tstrd\tr4, r4, [r0, #-56]\t@ 0x38\n+\tstr.w\tr2, [sl, #-68]\n+\tstr.w\tr2, [sl, #-80]\n+\tstr.w\tr9, [r3, #32]\n+\tstr.w\tr9, [r0, #-48]\n+\tstr.w\tr1, [sl, #-84]\n+\tstr.w\tr6, [r0, #-60]\n+\tstr.w\tr0, [r7, #132]\t@ 0x84\n+\tstr.w\tr5, [sl, #-72]\n+\tstr.w\tr5, [sl, #-76]\n+\tstrd\tr4, r4, [sl, #-64]\t@ 0x40\n+\tstr.w\tr9, [sl, #-56]\n+\tstr.w\tr6, [r0, #-72]\n+\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tstrh.w\tip, [r3, #16]\n+\tstr.w\tr8, [r3]\n+\tstr.w\tr6, [r0, #-52]\n+\tldr.w\tr0, [r7, #132]\t@ 0x84\n+\tldr.w\tr3, [r7, #132]\t@ 0x84\n+\tstrh.w\tip, [sl, #-72]\n+\tmovw\tip, #769\t@ 0x301\n+\tstrh.w\tip, [r0, #-64]\n+\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tstr.w\tr5, [lr, #4]\n+\tstr.w\tr8, [r7, #64]\t@ 0x40\n+\tadd.w\tr8, r7, #1256\t@ 0x4e8\n+\tstrd\tr1, r6, [r0, #-68]\t@ 0x44\n+\tstr.w\tr8, [r7, #60]\t@ 0x3c\n+\tstr.w\tr8, [sl, #-88]\n+\tadd.w\tr8, r7, #672\t@ 0x2a0\n+\tstrh.w\tip, [r0, #-56]\n+\tstr.w\tr8, [r3, #-80]\n+\tadd.w\tr3, r7, #592\t@ 0x250\n+\tstr.w\tr9, [r0, #-40]\n+\tstr.w\tr3, [r0, #-72]\n+\tstrd\tr4, r4, [r0, #-48]\t@ 0x30\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #9856\t@ 0x2680\n+\tstr.w\tr8, [r7, #48]\t@ 0x30\n+\tadds\tr3, #8\n+\tstrd\tr2, r2, [sp, #4]\n+\tstr\tr3, [r7, #112]\t@ 0x70\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr0, [r7, #232]\t@ 0xe8\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n+\tldr.w\tr2, [r7, #136]\t@ 0x88\n+\tsubs\tr0, #20\n+\tldr\tr1, [r7, #108]\t@ 0x6c\n \tbl\t0 <__gridxc_xcmod_MOD_getxc>\n R_ARM_THM_CALL\t__gridxc_xcmod_MOD_getxc\n-\tsubw\tr3, r5, #1436\t@ 0x59c\n+\tsubw\tr3, sl, #1428\t@ 0x594\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #152]\t@ 0x98\n-\tcmp\tr3, #0\n-\tble.w\t21fc <__gridxc_atom_MOD_atomxc+0x21fc>\n-\tldr.w\tr8, [pc, #616]\t@ 484 <__gridxc_atom_MOD_atomxc+0x484>\n-\tmovs\tr6, #0\n-\tldr\tr4, [r7, #52]\t@ 0x34\n-\tmovs\tr5, #1\n-\tadd\tr8, pc\n-\tmov\tr9, r6\n-\tmov\tr3, r8\n+\tstr.w\tr3, [r7, #160]\t@ 0xa0\n+\tcmp\tr3, r5\n+\tble.w\t21a4 <__gridxc_atom_MOD_atomxc+0x21a4>\n+\tldr.w\tr6, [pc, #1328]\t@ 76c <__gridxc_atom_MOD_atomxc+0x76c>\n+\tmov\tr3, r5\n+\tmov\tr5, r4\n+\tldr\tr4, [r7, #64]\t@ 0x40\n+\tadd\tr6, pc\n+\tmov\tr8, r3\n+\tmov\tr9, r3\n+\tmov\tr3, r6\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t430 <__gridxc_atom_MOD_atomxc+0x430>\n-\tldr\tr3, [pc, #588]\t@ (488 <__gridxc_atom_MOD_atomxc+0x488>)\n+\tbeq.w\t47a <__gridxc_atom_MOD_atomxc+0x47a>\n+\tldr.w\tr3, [pc, #1300]\t@ 770 <__gridxc_atom_MOD_atomxc+0x770>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t430 <__gridxc_atom_MOD_atomxc+0x430>\n-\tldr\tr3, [pc, #572]\t@ (48c <__gridxc_atom_MOD_atomxc+0x48c>)\n+\tbeq.w\t47a <__gridxc_atom_MOD_atomxc+0x47a>\n+\tldr.w\tr3, [pc, #1280]\t@ 774 <__gridxc_atom_MOD_atomxc+0x774>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4ac <__gridxc_atom_MOD_atomxc+0x4ac>\n-\tldr\tr3, [pc, #556]\t@ (490 <__gridxc_atom_MOD_atomxc+0x490>)\n+\tbeq.w\t490 <__gridxc_atom_MOD_atomxc+0x490>\n+\tldr.w\tr3, [pc, #1264]\t@ 778 <__gridxc_atom_MOD_atomxc+0x778>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4ac <__gridxc_atom_MOD_atomxc+0x4ac>\n-\tldr\tr3, [pc, #540]\t@ (494 <__gridxc_atom_MOD_atomxc+0x494>)\n+\tbeq.w\t490 <__gridxc_atom_MOD_atomxc+0x490>\n+\tldr.w\tr3, [pc, #1244]\t@ 77c <__gridxc_atom_MOD_atomxc+0x77c>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 2b8 <__gridxc_atom_MOD_atomxc+0x2b8>\n-\tldr\tr3, [pc, #528]\t@ (498 <__gridxc_atom_MOD_atomxc+0x498>)\n+\tcbz\tr0, 2e8 <__gridxc_atom_MOD_atomxc+0x2e8>\n+\tldr.w\tr3, [pc, #1232]\t@ 780 <__gridxc_atom_MOD_atomxc+0x780>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 2b8 <__gridxc_atom_MOD_atomxc+0x2b8>\n-\tldr\tr3, [pc, #516]\t@ (49c <__gridxc_atom_MOD_atomxc+0x49c>)\n+\tcbz\tr0, 2e8 <__gridxc_atom_MOD_atomxc+0x2e8>\n+\tldr.w\tr3, [pc, #1216]\t@ 784 <__gridxc_atom_MOD_atomxc+0x784>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 2b8 <__gridxc_atom_MOD_atomxc+0x2b8>\n-\tldr\tr3, [pc, #504]\t@ (4a0 <__gridxc_atom_MOD_atomxc+0x4a0>)\n+\tcbz\tr0, 2e8 <__gridxc_atom_MOD_atomxc+0x2e8>\n+\tldr.w\tr3, [pc, #1204]\t@ 788 <__gridxc_atom_MOD_atomxc+0x788>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t35d4 <__gridxc_atom_MOD_atomxc+0x35d4>\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tbne.w\t34e4 <__gridxc_atom_MOD_atomxc+0x34e4>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tadds\tr5, #1\n \tadds\tr4, #20\n \tcmp\tr3, r5\n-\tbge.n\t226 <__gridxc_atom_MOD_atomxc+0x226>\n+\tbge.n\t248 <__gridxc_atom_MOD_atomxc+0x248>\n \tlsls\tr4, r3, #2\n-\tstr.w\tr9, [r7, #220]\t@ 0xdc\n+\tstr.w\tr8, [r7, #244]\t@ 0xf4\n \tmov\tr0, r4\n+\tstr.w\tr9, [r7, #100]\t@ 0x64\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #80]\t@ 0x50\n+\tstr\tr0, [r7, #92]\t@ 0x5c\n \tcmp\tr0, #0\n-\tbeq.w\t35c2 <__gridxc_atom_MOD_atomxc+0x35c2>\n+\tbeq.w\t3518 <__gridxc_atom_MOD_atomxc+0x3518>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n+\tstr\tr0, [r7, #88]\t@ 0x58\n \tcmp\tr0, #0\n-\tbeq.w\t35b2 <__gridxc_atom_MOD_atomxc+0x35b2>\n+\tbeq.w\t3528 <__gridxc_atom_MOD_atomxc+0x3528>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #72]\t@ 0x48\n+\tstr\tr0, [r7, #80]\t@ 0x50\n \tcmp\tr0, #0\n-\tbeq.w\t3562 <__gridxc_atom_MOD_atomxc+0x3562>\n+\tbeq.w\t3538 <__gridxc_atom_MOD_atomxc+0x3538>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n-\tmovw\tfp, #18764\t@ 0x494c\n-\tmovt\tfp, #22594\t@ 0x5842\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n+\tmovw\tr4, #18764\t@ 0x494c\n+\tmovt\tr4, #22594\t@ 0x5842\n \tcmp\tr3, #1\n-\tldr\tr3, [pc, #392]\t@ (4a4 <__gridxc_atom_MOD_atomxc+0x4a4>)\n-\tstr.w\tr6, [r7, #272]\t@ 0x110\n+\tldr.w\tr3, [pc, #1084]\t@ 78c <__gridxc_atom_MOD_atomxc+0x78c>\n+\tldr\tr5, [r7, #60]\t@ 0x3c\n \tmov.w\tr8, #0\n \tadd\tr3, pc\n-\tldr\tr5, [r7, #56]\t@ 0x38\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tmov.w\tr3, #1\n-\tldr.w\tr9, [r7, #76]\t@ 0x4c\n-\tit\tne\n+\tldr.w\tr9, [r7, #88]\t@ 0x58\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tite\teq\n+\tmoveq\tr3, #1\n \tmovne\tr3, #2\n-\tldr.w\tr6, [r7, #280]\t@ 0x118\n-\tvldr\td8, [pc, #296]\t@ 468 <__gridxc_atom_MOD_atomxc+0x468>\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tb.n\t35a <__gridxc_atom_MOD_atomxc+0x35a>\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tldr.w\tr6, [r7, #236]\t@ 0xec\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tb.n\t386 <__gridxc_atom_MOD_atomxc+0x386>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tadd.w\tr8, r8, #1\n \tadds\tr5, #20\n \tadd.w\tr9, r9, #4\n \tcmp\tr8, r3\n-\tbeq.w\t4c0 <__gridxc_atom_MOD_atomxc+0x4c0>\n+\tbeq.w\t4a4 <__gridxc_atom_MOD_atomxc+0x4a4>\n \tldr\tr3, [r5, #0]\n-\tcmp\tr3, fp\n-\tbne.n\t346 <__gridxc_atom_MOD_atomxc+0x346>\n+\tcmp\tr3, r4\n+\tbne.n\t372 <__gridxc_atom_MOD_atomxc+0x372>\n \tldrb\tr3, [r5, #4]\n \tcmp\tr3, #67\t@ 0x43\n-\tbne.n\t346 <__gridxc_atom_MOD_atomxc+0x346>\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n+\tbne.n\t372 <__gridxc_atom_MOD_atomxc+0x372>\n+\tldr.w\tr3, [r7, #292]\t@ 0x124\n \tmovs\tr2, #0\n \tstr.w\tr3, [r6, #-64]\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr4, [r7, #240]\t@ 0xf0\n-\tsubw\tr3, r3, #1444\t@ 0x5a4\n-\tldr\tr0, [r7, #104]\t@ 0x68\n-\tstr.w\tr2, [r6, #-24]\n-\tvstr\td8, [r6, #-72]\t@ 0xffffffb8\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r6, #-24]\n+\tsubw\tr3, sl, #1436\t@ 0x59c\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tstr\tr2, [r3, #0]\n \tmovs\tr2, #227\t@ 0xe3\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n \tstr.w\tr2, [r6, #-60]\n \tadds\tr2, r5, #6\n \tstr.w\tr2, [r6, #-4]\n \tmovs\tr2, #5\n \tstr\tr2, [r6, #0]\n-\tsub.w\tr2, r4, #36\t@ 0x24\n-\tsubs\tr4, #24\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstr.w\tr2, [r6, #-68]\n+\tsub.w\tr2, r3, #28\n \tstr.w\tr2, [r6, #-48]\n-\tstr.w\tr3, [r7, #268]\t@ 0x10c\n+\tmovw\tr2, #16544\t@ 0x40a0\n+\tstr.w\tr2, [r6, #-72]\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n-\tldr\tr0, [r7, #104]\t@ 0x68\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tmovs\tr2, #4\n-\tmov\tr1, r4\n+\tsubs\tr3, #16\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tmov\tr1, r3\n \tbl\t0 <_gfortran_transfer_integer>\n R_ARM_THM_CALL\t_gfortran_transfer_integer\n-\tldr\tr0, [r7, #104]\t@ 0x68\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n \tldr\tr3, [r3, #0]\n-\tcbz\tr3, 3f0 <__gridxc_atom_MOD_atomxc+0x3f0>\n+\tcbz\tr3, 42e <__gridxc_atom_MOD_atomxc+0x42e>\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #0]\n-\tldr\tr3, [pc, #224]\t@ (4a8 <__gridxc_atom_MOD_atomxc+0x4a8>)\n+\tldr\tr3, [pc, #904]\t@ (790 <__gridxc_atom_MOD_atomxc+0x790>)\n \tadd.w\tr1, r7, #13952\t@ 0x3680\n \tadds\tr1, #20\n \tmovs\tr0, #38\t@ 0x26\n \tadd\tr3, pc\n \tstr\tr5, [sp, #4]\n \tmovs\tr2, #18\n-\tstr.w\tr1, [r7, #268]\t@ 0x10c\n+\tstr.w\tr1, [r7, #288]\t@ 0x120\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tldr\tr3, [pc, #156]\t@ (47c <__gridxc_atom_MOD_atomxc+0x47c>)\n-\tldr.w\tr1, [r7, #268]\t@ 0x10c\n+\tldr\tr3, [pc, #836]\t@ (764 <__gridxc_atom_MOD_atomxc+0x764>)\n+\tldr.w\tr1, [r7, #288]\t@ 0x120\n \tmov\tr0, r1\n \tmovs\tr1, #38\t@ 0x26\n-\tldr.w\tr3, [sl, r3]\n+\tldr.w\tr3, [fp, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tsubw\tr3, r3, #1428\t@ 0x594\n+\tsubw\tr3, sl, #1420\t@ 0x58c\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n \tstr\tr2, [r3, #0]\n \tldr.w\tr3, [r7, #128]\t@ 0x80\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #1\n-\tbeq.w\t2136 <__gridxc_atom_MOD_atomxc+0x2136>\n-\tldr.w\tr2, [r7, #240]\t@ 0xf0\n+\tbne.n\t452 <__gridxc_atom_MOD_atomxc+0x452>\n+\tsub.w\tr3, sl, #1424\t@ 0x590\n+\tldr\tr2, [r3, #0]\n+\tcmp\tr2, #1\n+\titt\teq\n+\tmoveq.w\tr2, #532\t@ 0x214\n+\tstreq\tr2, [r3, #0]\n+\tldr.w\tr2, [r7, #232]\t@ 0xe8\n \tmovs\tr3, #0\n-\tmov\tr1, r4\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n \tmov\tr0, r9\n-\tsubs\tr2, #20\n+\tsubs\tr2, #12\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_init>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_init\n \tmov\tr0, r9\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_get_info>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_get_info\n-\tldr\tr3, [r7, #72]\t@ 0x48\n-\tldr\tr2, [r7, #80]\t@ 0x50\n+\tldr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #92]\t@ 0x5c\n \tstr.w\tr0, [r3, r8, lsl #2]\n \tmovs\tr3, #1\n \tstr.w\tr3, [r2, r8, lsl #2]\n-\tb.n\t346 <__gridxc_atom_MOD_atomxc+0x346>\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n-\tmovs\tr6, #1\n+\tb.n\t372 <__gridxc_atom_MOD_atomxc+0x372>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n+\tmov.w\tr9, #1\n \tadds\tr5, #1\n-\tmov\tr9, r6\n+\tmov\tr8, r9\n \tadds\tr4, #20\n \tcmp\tr3, r5\n-\tbge.w\t226 <__gridxc_atom_MOD_atomxc+0x226>\n-\tb.n\t2c4 <__gridxc_atom_MOD_atomxc+0x2c4>\n-\tnop.w\n-\t.word\t0x00000014\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000000a\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000000a\n-\t.word\t0x000040a0\n-\t.word\t0xffffffff\n-\t.word\t0x0000042c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000041a\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t...\n- R_ARM_GOT32\t__stack_chk_guard\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000039a\n- R_ARM_REL32\t.LC0\n-\t.word\t0x0000025e\n- R_ARM_REL32\t.LC1\n-\t.word\t0x00000244\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000234\n- R_ARM_REL32\t.LC3\n-\t.word\t0x00000224\n- R_ARM_REL32\t.LC4\n-\t.word\t0x00000214\n- R_ARM_REL32\t.LC5\n-\t.word\t0x00000208\n- R_ARM_REL32\t.LC6\n-\t.word\t0x000001fc\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000001f0\n- R_ARM_REL32\t.LC8\n-\t.word\t0x0000017c\n- R_ARM_REL32\t.LC14\n-\t.word\t0x000000d4\n- R_ARM_REL32\t.LC15\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tbge.w\t248 <__gridxc_atom_MOD_atomxc+0x248>\n+\tb.n\t2f4 <__gridxc_atom_MOD_atomxc+0x2f4>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tadds\tr5, #1\n-\tmov.w\tr9, #1\n+\tmov.w\tr8, #1\n \tadds\tr4, #20\n \tcmp\tr3, r5\n-\tbge.w\t226 <__gridxc_atom_MOD_atomxc+0x226>\n-\tb.n\t2c4 <__gridxc_atom_MOD_atomxc+0x2c4>\n-\tldr\tr3, [pc, #700]\t@ (780 <__gridxc_atom_MOD_atomxc+0x780>)\n+\tbge.w\t248 <__gridxc_atom_MOD_atomxc+0x248>\n+\tb.n\t2f4 <__gridxc_atom_MOD_atomxc+0x2f4>\n+\tldr\tr3, [pc, #748]\t@ (794 <__gridxc_atom_MOD_atomxc+0x794>)\n \tmovs\tr4, #0\n-\tldr.w\tr5, [r7, #232]\t@ 0xe8\n-\tldr.w\tr6, [r7, #272]\t@ 0x110\n-\tadd\tr3, pc\n+\tldr.w\tr6, [r7, #256]\t@ 0x100\n+\tmovs\tr5, #11\n \tstrd\tr4, r4, [sp, #12]\n-\tstr\tr5, [sp, #0]\n+\tadd\tr3, pc\n+\tstr\tr6, [sp, #0]\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #8\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tstr\tr4, [sp, #8]\n-\tldr.w\tr8, [pc, #676]\t@ 784 <__gridxc_atom_MOD_atomxc+0x784>\n-\tldr.w\tr9, [pc, #676]\t@ 788 <__gridxc_atom_MOD_atomxc+0x788>\n-\tldr.w\tsl, [r7, #204]\t@ 0xcc\n+\tldr.w\tr8, [pc, #724]\t@ 798 <__gridxc_atom_MOD_atomxc+0x798>\n+\tldr.w\tr9, [pc, #724]\t@ 79c <__gridxc_atom_MOD_atomxc+0x79c>\n+\tldr.w\tfp, [r7, #220]\t@ 0xdc\n \tadd\tr8, pc\n \tadd\tr9, pc\n \tmov\tr3, r8\n-\tmov\tr2, sl\n+\tmov\tr2, fp\n \tmov\tr1, r8\n \tmov\tr0, r9\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr3, [pc, #656]\t@ (78c <__gridxc_atom_MOD_atomxc+0x78c>)\n+\tldr\tr3, [pc, #704]\t@ (7a0 <__gridxc_atom_MOD_atomxc+0x7a0>)\n \tadd.w\tr2, r8, #4\n \tadd.w\tr1, r8, #8\n \tadd\tr3, pc\n \tadd.w\tr0, r9, #48\t@ 0x30\n-\tstr\tr5, [sp, #0]\n+\tstr\tr6, [sp, #0]\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #12\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r8\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tmovs\tr3, #11\n-\tstr\tr3, [sp, #12]\n-\tmov\tr2, r5\n-\tldr\tr3, [pc, #616]\t@ (790 <__gridxc_atom_MOD_atomxc+0x790>)\n+\tldr\tr3, [pc, #672]\t@ (7a4 <__gridxc_atom_MOD_atomxc+0x7a4>)\n+\tmov\tr2, r6\n \tmov\tr1, r8\n+\tadd\tr3, pc\n \tadd.w\tr0, r9, #96\t@ 0x60\n \tstr\tr4, [sp, #16]\n-\tadd\tr3, pc\n \tstrd\tr4, r4, [sp, #4]\n \tstr\tr4, [sp, #0]\n+\tstr\tr5, [sp, #12]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tmovs\tr3, #11\n-\tstrd\tr4, r3, [sp, #8]\n-\tmov\tr2, r5\n-\tldr\tr3, [pc, #588]\t@ (794 <__gridxc_atom_MOD_atomxc+0x794>)\n+\tldr\tr3, [pc, #648]\t@ (7a8 <__gridxc_atom_MOD_atomxc+0x7a8>)\n+\tmov\tr2, r6\n \tmov\tr1, r8\n-\tadd.w\tr0, r9, #132\t@ 0x84\n-\tstr\tr4, [sp, #16]\n \tadd\tr3, pc\n-\tstrd\tr4, r4, [sp]\n+\tadd.w\tr0, r9, #132\t@ 0x84\n+\tstrd\tr5, r4, [sp, #12]\n+\tstrd\tr4, r4, [sp, #4]\n+\tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr\tr3, [pc, #572]\t@ (798 <__gridxc_atom_MOD_atomxc+0x798>)\n+\tldr\tr3, [pc, #628]\t@ (7ac <__gridxc_atom_MOD_atomxc+0x7ac>)\n \tadd.w\tr2, r8, #12\n-\tmov\tr1, r8\n+\tstrd\tr8, r6, [sp, #4]\n \tadd\tr3, pc\n-\tadd.w\tr0, r9, #168\t@ 0xa8\n-\tstrd\tr8, r5, [sp, #4]\n-\tadd.w\tr5, r7, #352\t@ 0x160\n-\tstr.w\tsl, [sp]\n-\tmov\tsl, r2\n+\tmov\tr1, r8\n \tstr\tr3, [sp, #12]\n+\tadd.w\tr0, r9, #168\t@ 0xa8\n \tmovs\tr3, #9\n \tstr\tr4, [sp, #32]\n-\tstr\tr3, [sp, #28]\n-\tmov\tr3, r8\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n+\tstr.w\tfp, [sp]\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tstr\tr3, [sp, #28]\n+\tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr.w\tr1, [r7, #140]\t@ 0x8c\n-\tstr.w\tr5, [r7, #224]\t@ 0xe0\n+\tldr.w\tr1, [r7, #144]\t@ 0x90\n+\tldr.w\tr6, [r7, #240]\t@ 0xf0\n \tadd.w\tr2, r7, #400\t@ 0x190\n-\tldr.w\tr5, [r7, #228]\t@ 0xe4\n \tsubs\tr3, r1, #1\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tvldr\td7, [pc, #456]\t@ 740 <__gridxc_atom_MOD_atomxc+0x740>\n \tadd.w\tr0, r7, #368\t@ 0x170\n-\tvldr\td16, [pc, #460]\t@ 770 <__gridxc_atom_MOD_atomxc+0x770>\n+\tadd.w\tr3, r6, r3, lsl #3\n \tcmp\tr1, r4\n-\tadd.w\tr3, r5, r3, lsl #3\n-\tstr\tr2, [r7, #108]\t@ 0x6c\n-\tstr.w\tr0, [r7, #212]\t@ 0xd4\n+\tstr.w\tr2, [r7, #180]\t@ 0xb4\n+\tstr.w\tr0, [r7, #184]\t@ 0xb8\n \tvldr\td8, [r3]\n-\tvdiv.f64\td10, d16, d8\n-\tvstr\td8, [r7, #360]\t@ 0x168\n-\tvstr\td10, [r7, #352]\t@ 0x160\n-\tble.w\t33cc <__gridxc_atom_MOD_atomxc+0x33cc>\n-\tldr\tr1, [pc, #468]\t@ (79c <__gridxc_atom_MOD_atomxc+0x79c>)\n+\tvdiv.f64\td9, d7, d8\n+\tvstr\td8, [r7, #368]\t@ 0x170\n+\tvstr\td9, [r7, #360]\t@ 0x168\n+\tble.w\t32e0 <__gridxc_atom_MOD_atomxc+0x32e0>\n+\tldr\tr1, [pc, #528]\t@ (7b0 <__gridxc_atom_MOD_atomxc+0x7b0>)\n \tmov.w\tip, #1\n-\tldr.w\tr3, [r7, #228]\t@ 0xe4\n-\tvmov.i64\td20, #0x0000000000000000\n+\tldr.w\tr2, [r7, #144]\t@ 0x90\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tadd\tr1, pc\n-\tldr\tr0, [r7, #64]\t@ 0x40\n-\tstr\tr3, [r7, #48]\t@ 0x30\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tstr.w\tr3, [r7, #216]\t@ 0xd8\n-\tmov\tr9, r0\n+\tldr\tr4, [r7, #72]\t@ 0x48\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tadds\tr2, #1\n+\tstr.w\tr2, [r7, #168]\t@ 0xa8\n+\tmov\tr9, r4\n+\tldr\tr2, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tstr.w\tr4, [r7, #260]\t@ 0x104\n+\tstr.w\tr3, [r7, #228]\t@ 0xe4\n+\tlsls\tr2, r2, #3\n \tldr.w\tr4, [r1, #204]\t@ 0xcc\n \tldr.w\tr3, [r1, #172]\t@ 0xac\n-\tldr.w\tr2, [r7, #140]\t@ 0x8c\n-\tldr.w\tsl, [r1, #36]\t@ 0x24\n-\tstr.w\tr0, [r7, #244]\t@ 0xf4\n-\tadds\tr0, r3, r4\n+\tldr.w\tr8, [r1, #36]\t@ 0x24\n+\tstr.w\tr2, [r7, #284]\t@ 0x11c\n+\tadds\tr2, r3, r4\n \tldr\tr3, [r1, #4]\n-\tadds\tr2, #1\n \tldr.w\tlr, [r1, #24]\n-\tstr.w\tr2, [r7, #156]\t@ 0x9c\n-\tadd\tr3, sl\n-\tldr\tr2, [r7, #100]\t@ 0x64\n-\tldr.w\tr5, [r1, #216]\t@ 0xd8\n+\tldr.w\tr5, [r1, #192]\t@ 0xc0\n+\tadd\tr3, r8\n \tldr.w\tfp, [r1, #156]\t@ 0x9c\n-\tstr.w\tr5, [r7, #168]\t@ 0xa8\n+\tstr\tr5, [r7, #124]\t@ 0x7c\n \tadd.w\tr5, r3, lr\n \tldr.w\tr3, [r1, #136]\t@ 0x88\n-\tlsls\tr2, r2, #3\n-\tstr.w\tr2, [r7, #272]\t@ 0x110\n-\tldr.w\tr2, [r1, #192]\t@ 0xc0\n-\tldr.w\tr8, [r1, #120]\t@ 0x78\n-\tstr\tr2, [r7, #120]\t@ 0x78\n+\tldr.w\tr6, [r1, #216]\t@ 0xd8\n+\tstr\tr2, [r7, #116]\t@ 0x74\n \tadd.w\tr2, fp, r3\n+\tstr.w\tr6, [r7, #188]\t@ 0xbc\n \tldr\tr3, [r1, #100]\t@ 0x64\n-\tstr\tr0, [r7, #112]\t@ 0x70\n-\tadd.w\tr0, r8, r3\n+\tldr\tr6, [r1, #120]\t@ 0x78\n+\tvldr\td4, [pc, #316]\t@ 748 <__gridxc_atom_MOD_atomxc+0x748>\n+\tadds\tr0, r6, r3\n \tldr.w\tr3, [r1, #188]\t@ 0xbc\n-\tstr\tr3, [r7, #116]\t@ 0x74\n-\tvldr\td21, [pc, #312]\t@ 778 <__gridxc_atom_MOD_atomxc+0x778>\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tvldr\td6, [pc, #312]\t@ 750 <__gridxc_atom_MOD_atomxc+0x750>\n \tmul.w\tr4, r3, r4\n-\tldr\tr3, [r1, #20]\n+\tldr.w\tr3, [r1, #152]\t@ 0x98\n \tstr\tr4, [r7, #32]\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tmul.w\tr4, sl, r3\n-\tmul.w\tlr, r3, lr\n-\tldr\tr3, [r1, #116]\t@ 0x74\n-\tstr.w\tr4, [r7, #148]\t@ 0x94\n-\tmul.w\tr4, r3, r8\n-\tldr.w\tr8, [r1, #152]\t@ 0x98\n-\tstr.w\tr4, [r7, #136]\t@ 0x88\n-\tmul.w\tr4, r8, fp\n-\tstr.w\tr4, [r7, #132]\t@ 0x84\n-\tldr\tr4, [r1, #72]\t@ 0x48\n-\tstr.w\tr4, [r7, #160]\t@ 0xa0\n-\tldr\tr4, [r1, #68]\t@ 0x44\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n-\tldr.w\tr4, [r1, #132]\t@ 0x84\n-\tmla\tr8, r8, r2, r4\n-\tldr\tr2, [r1, #96]\t@ 0x60\n-\tstr.w\tr8, [r7, #256]\t@ 0x100\n-\tldr\tr4, [r7, #120]\t@ 0x78\n-\tmla\tsl, r3, r0, r2\n+\tldr\tr4, [r1, #20]\n+\tmul.w\tlr, r4, lr\n+\tstr.w\tlr, [r7, #300]\t@ 0x12c\n+\tmul.w\tr8, r8, r4\n+\tldr.w\tlr, [r1, #116]\t@ 0x74\n+\tstr.w\tr8, [r7, #164]\t@ 0xa4\n+\tmul.w\tr8, lr, r6\n+\tstr.w\tr8, [r7, #148]\t@ 0x94\n+\tmul.w\tr8, r3, fp\n+\tstr.w\tr8, [r7, #140]\t@ 0x8c\n+\tldr\tr6, [r1, #72]\t@ 0x48\n+\tstr.w\tr6, [r7, #172]\t@ 0xac\n+\tldr\tr6, [r1, #68]\t@ 0x44\n+\tstr.w\tr6, [r7, #292]\t@ 0x124\n+\tldr.w\tr6, [r1, #132]\t@ 0x84\n+\tstr.w\tsl, [r7, #96]\t@ 0x60\n+\tstr.w\tr9, [r7, #16]\n+\tmla\tr8, r3, r2, r6\n+\tldr\tr3, [r1, #96]\t@ 0x60\n \tldr\tr2, [r1, #0]\n-\tldr.w\tr0, [r7, #288]\t@ 0x120\n+\tldr.w\tr6, [r7, #188]\t@ 0xbc\n+\tstr.w\tr8, [r7, #268]\t@ 0x10c\n+\tsub.w\tr8, sl, #992\t@ 0x3e0\n+\tmla\tlr, lr, r0, r3\n \tldr.w\tr3, [r1, #168]\t@ 0xa8\n-\tmla\tr8, r0, r5, r2\n-\tldr.w\tr5, [r7, #168]\t@ 0xa8\n-\tldr\tr0, [r7, #112]\t@ 0x70\n-\tstr.w\tr8, [r7, #248]\t@ 0xf8\n-\tadds\tr2, r0, r5\n-\tldr\tr0, [r7, #116]\t@ 0x74\n-\tadd\tr2, r4\n-\tstr.w\tr5, [r7, #236]\t@ 0xec\n-\tmla\tr2, r0, r2, r3\n+\tmla\tr0, r4, r5, r2\n+\tldr\tr2, [r7, #116]\t@ 0x74\n+\tldr\tr5, [r7, #124]\t@ 0x7c\n+\tldr\tr4, [r7, #120]\t@ 0x78\n+\tadd\tr2, r6\n+\tadd\tr2, r5\n+\tstr.w\tr0, [r7, #264]\t@ 0x108\n+\tldr.w\tsl, [r7, #280]\t@ 0x118\n+\tstr.w\tr6, [r7, #252]\t@ 0xfc\n+\tmla\tr3, r4, r2, r3\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tlsl.w\tr3, r5, ip\n+\tmov\tr2, r3\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r1, #84]\t@ 0x54\n-\tstr.w\tr3, [r7, #172]\t@ 0xac\n+\tstr.w\tr3, [r7, #156]\t@ 0x9c\n+\tmov\tr0, r3\n \tldrd\tr1, r3, [r1, #48]\t@ 0x30\n-\tstr.w\tr1, [r7, #264]\t@ 0x108\n+\tstr.w\tr1, [r7, #276]\t@ 0x114\n+\tmul.w\tr1, r4, r2\n+\tadds\tr3, r0, r3\n+\tstr\tr1, [r7, #40]\t@ 0x28\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tmul.w\tr3, r6, r4\n \tldr.w\tr1, [r7, #172]\t@ 0xac\n-\tstr.w\tr2, [r7, #224]\t@ 0xe0\n-\tmov\tr2, r4\n-\tadds\tr3, r1, r3\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tmul.w\tr3, r5, r0\n-\tldr.w\tr1, [r7, #268]\t@ 0x10c\n-\tstr.w\tr3, [r7, #144]\t@ 0x90\n-\tlsl.w\tr4, r4, ip\n-\tldr.w\tr3, [r7, #160]\t@ 0xa0\n-\tstr\tr4, [r7, #88]\t@ 0x58\n-\tmul.w\tr0, r0, r4\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tmul.w\tfp, r1, r3\n-\tadds\tr3, r4, r2\n-\tstr\tr3, [r7, #28]\n-\tadd.w\tr3, r7, #752\t@ 0x2f0\n-\tstr\tr3, [r7, #96]\t@ 0x60\n-\tmov\tr1, ip\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tstr.w\tlr, [r7, #252]\t@ 0xfc\n-\tsub.w\tr8, r3, #992\t@ 0x3e0\n-\tstr.w\tr9, [r7, #8]\n-\tldr.w\tr9, [r7, #276]\t@ 0x114\n-\tmov\tr0, r8\n-\tstr\tr6, [r7, #12]\n-\tsub.w\tr8, r1, #5\n-\tmovs\tr3, #1\n-\tldr.w\tr4, [r7, #140]\t@ 0x8c\n-\tcmp\tr8, r3\n+\tldr.w\tr4, [r7, #292]\t@ 0x124\n+\tstr.w\tr3, [r7, #152]\t@ 0x98\n+\tmul.w\tfp, r4, r1\n+\tadds\tr1, r2, r5\n+\tstr\tr1, [r7, #28]\n+\tadd.w\tr1, r7, #752\t@ 0x2f0\n+\tstr\tr1, [r7, #104]\t@ 0x68\n+\tmov\tr1, r8\n+\tsub.w\tr2, ip, #5\n+\tldr.w\tr0, [r7, #144]\t@ 0x90\n+\tadd.w\tr3, ip, #5\n+\tcmp\tr2, #1\n \tit\tlt\n-\tmovlt\tr8, r3\n-\tadds\tr3, r1, #5\n-\tcmp\tr3, r4\n-\tmov\tr2, r3\n+\tmovlt\tr2, #1\n+\tcmp\tr3, r0\n+\tmov\tr5, r3\n \tit\tge\n-\tmovge\tr2, r4\n-\tsub.w\tr4, r8, r1\n-\tsubs\tr5, r2, r1\n-\tcmp\tr8, r2\n-\tstr.w\tr2, [r7, #260]\t@ 0x104\n-\tstr.w\tr5, [r7, #288]\t@ 0x120\n-\tbgt.w\t212a <__gridxc_atom_MOD_atomxc+0x212a>\n-\tldr\tr3, [r7, #96]\t@ 0x60\n-\tadd.w\tlr, r4, #5\n-\tldr.w\tr2, [r7, #252]\t@ 0xfc\n+\tmovge\tr5, r0\n+\tsub.w\tr4, r2, ip\n+\tsub.w\tr3, r5, ip\n+\tcmp\tr2, r5\n+\tstr.w\tr2, [r7, #288]\t@ 0x120\n+\tstr.w\tr5, [r7, #272]\t@ 0x110\n+\tbgt.w\t20f0 <__gridxc_atom_MOD_atomxc+0x20f0>\n+\tldr\tr2, [r7, #104]\t@ 0x68\n+\tadd.w\tr9, r4, #5\n+\tldr.w\tr0, [r7, #284]\t@ 0x11c\n \tmov\tr6, r4\n-\tadd.w\tip, r3, lr, lsl #3\n-\tmov\tr3, r5\n+\tadd.w\tr8, r2, r9, lsl #3\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n \tcmp\tr6, #0\n-\tbeq.w\t1a38 <__gridxc_atom_MOD_atomxc+0x1a38>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n+\tbeq.w\t1a00 <__gridxc_atom_MOD_atomxc+0x1a00>\n+\tvmov.f64\td3, #112\t@ 0x3f800000 1.0\n \tmov\tr5, r4\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n-\tvmov.f64\td18, d17\n-\tb.n\t7c2 <__gridxc_atom_MOD_atomxc+0x7c2>\n-\tnop\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tvmov.f64\td2, d3\n+\tb.n\t7d6 <__gridxc_atom_MOD_atomxc+0x7d6>\n+\tnop.w\n \t.word\t0x54442d18\n \t.word\t0x409921fb\n \t.word\t0x54442d18\n \t.word\t0x402921fb\n-\t.word\t0x000002b0\n+\t...\n+\t.word\t0x00000714\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000702\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t...\n+ R_ARM_GOT32\t__stack_chk_guard\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x00000682\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000526\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000508\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x000004f6\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x000004e4\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x000004d2\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x000004c4\n+ R_ARM_REL32\t.LC6\n+\t.word\t0x000004b6\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x000004a8\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x00000430\n+ R_ARM_REL32\t.LC14\n+\t.word\t0x0000037e\n+ R_ARM_REL32\t.LC15\n+\t.word\t0x000002de\n R_ARM_REL32\t.LC17\n-\t.word\t0x00000296\n+\t.word\t0x000002c8\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000298\n+\t.word\t0x000002ca\n R_ARM_REL32\t.bss\n-\t.word\t0x00000284\n+\t.word\t0x000002b6\n R_ARM_REL32\t.LC20\n-\t.word\t0x0000025c\n+\t.word\t0x00000298\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000242\n+\t.word\t0x00000282\n R_ARM_REL32\t.LC22\n-\t.word\t0x00000234\n+\t.word\t0x00000268\n R_ARM_REL32\t.LC24\n-\t.word\t0x000001c6\n+\t.word\t0x00000200\n R_ARM_REL32\t.bss\n \tnegs\tr2, r5\n-\tvmov\ts15, r2\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td18, d18, d16\n+\tvmov\ts10, r2\n+\tvcvt.f64.s32\td5, s10\n+\tvmul.f64\td2, d2, d5\n \tsubs\tr2, r6, r5\n-\tvmov\ts15, r2\n+\tvmov\ts10, r2\n \tadds\tr5, #1\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td5, s10\n \tcmp\tr3, r5\n-\tvmul.f64\td17, d17, d16\n-\tblt.n\t7d4 <__gridxc_atom_MOD_atomxc+0x7d4>\n+\tvmul.f64\td3, d3, d5\n+\tblt.n\t7e8 <__gridxc_atom_MOD_atomxc+0x7e8>\n \tcmp\tr5, #0\n \tit\tne\n \tcmpne\tr6, r5\n-\tbne.n\t7a0 <__gridxc_atom_MOD_atomxc+0x7a0>\n+\tbne.n\t7b4 <__gridxc_atom_MOD_atomxc+0x7b4>\n \tcmp\tr6, r5\n-\tbne.n\t7ae <__gridxc_atom_MOD_atomxc+0x7ae>\n+\tbne.n\t7c2 <__gridxc_atom_MOD_atomxc+0x7c2>\n \tadds\tr5, #1\n \tcmp\tr3, r5\n-\tbge.n\t7c2 <__gridxc_atom_MOD_atomxc+0x7c2>\n-\tvdiv.f64\td16, d18, d17\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tvstr\td16, [ip]\n+\tbge.n\t7d6 <__gridxc_atom_MOD_atomxc+0x7d6>\n+\tvdiv.f64\td5, d2, d3\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tvstr\td5, [r8]\n \tadds\tr6, #1\n-\tadd.w\tip, ip, #8\n+\tadd.w\tr8, r8, #8\n \tcmp\tr3, r6\n-\tbge.n\t758 <__gridxc_atom_MOD_atomxc+0x758>\n-\tstr.w\tr2, [r7, #252]\t@ 0xfc\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r7, #228]\t@ 0xe4\n-\tadd.w\tr5, r2, r8, lsl #3\n-\tvldr\td16, [r5, #-8]\n-\tadd.w\tr5, r0, lr, lsl #3\n-\tvldr\td17, [r5]\n+\tbge.n\t726 <__gridxc_atom_MOD_atomxc+0x726>\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tstr.w\tr0, [r7, #284]\t@ 0x11c\n+\tldr.w\tr6, [r7, #240]\t@ 0xf0\n+\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tadd.w\tr5, r6, r2, lsl #3\n+\tvldr\td5, [r5, #-8]\n+\tadd.w\tr5, r1, r9, lsl #3\n+\tvldr\td3, [r5]\n \tadds\tr5, r4, #1\n \tcmp\tr3, r5\n-\tvmul.f64\td16, d16, d17\n-\tblt.w\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd\tr5, r1\n-\tadd.w\tip, r4, #6\n-\tadd.w\tr5, r2, r5, lsl #3\n-\tadd.w\tr6, r0, ip, lsl #3\n-\tvldr\td17, [r5, #-8]\n+\tvmul.f64\td5, d5, d3\n+\tblt.w\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd\tr5, ip\n+\tadd.w\tr8, r4, #6\n+\tmov\tr2, r6\n+\tadd.w\tr5, r6, r5, lsl #3\n+\tadd.w\tr6, r1, r8, lsl #3\n+\tvldr\td2, [r5, #-8]\n \tadds\tr5, r4, #2\n-\tvldr\td18, [r6]\n+\tvldr\td3, [r6]\n \tcmp\tr3, r5\n-\tvfma.f64\td16, d18, d17\n-\tblt.w\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd\tr5, r1\n-\tadds\tr3, r4, #7\n+\tvmla.f64\td5, d2, d3\n+\tblt.w\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd\tr5, ip\n+\tadds\tr0, r4, #7\n \tadd.w\tr5, r2, r5, lsl #3\n-\tadd.w\tr6, r0, r3, lsl #3\n-\tvldr\td17, [r5, #-8]\n+\tadd.w\tr6, r1, r0, lsl #3\n+\tvldr\td2, [r5, #-8]\n \tadds\tr5, r4, #3\n-\tvldr\td18, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tvfma.f64\td16, d18, d17\n-\tcmp\tr6, r5\n-\tblt.w\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd\tr5, r1\n+\tvldr\td3, [r6]\n+\tcmp\tr3, r5\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd\tr5, ip\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td17, [r5, #-8]\n+\tvldr\td2, [r5, #-8]\n \tadd.w\tr5, r4, #8\n \tmov\tr2, r5\n-\tstr.w\tr2, [r7, #208]\t@ 0xd0\n \tadds\tr5, r4, #4\n-\tadd.w\tr6, r0, r2, lsl #3\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tcmp\tr2, r5\n-\tvldr\td18, [r6]\n-\tvfma.f64\td16, d18, d17\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tldr.w\tr2, [r7, #228]\t@ 0xe4\n-\tadd\tr5, r1\n+\tcmp\tr3, r5\n+\tstr.w\tr2, [r7, #224]\t@ 0xe0\n+\tadd.w\tr6, r1, r2, lsl #3\n+\tvldr\td3, [r6]\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tldr.w\tr2, [r7, #240]\t@ 0xf0\n+\tadd\tr5, ip\n \tadd.w\tr6, r4, #9\n+\tcmp\tr3, r9\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r0, r6, lsl #3\n-\tvldr\td18, [r5]\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvfma.f64\td16, d18, d17\n-\tcmp\tr5, lr\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd.w\tr5, r1, lr\n-\tadd.w\tlr, r4, #10\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r6, lsl #3\n+\tvldr\td3, [r5]\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd.w\tr5, ip, r9\n+\tadd.w\tr9, r4, #10\n+\tcmp\tr3, r8\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r0, lr, lsl #3\n-\tvldr\td18, [r5]\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvfma.f64\td16, d18, d17\n-\tcmp\tr5, ip\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd.w\tr5, r1, ip\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r9, lsl #3\n+\tvldr\td3, [r5]\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd.w\tr5, ip, r8\n+\tcmp\tr3, r0\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r0, r4, lsl #3\n-\tvldr\td18, [r5, #88]\t@ 0x58\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvfma.f64\td16, d18, d17\n-\tcmp\tr5, r3\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd\tr3, r1\n-\tadd.w\tr5, r2, r3, lsl #3\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r0, r4, lsl #3\n-\tvldr\td18, [r5, #96]\t@ 0x60\n-\tldr.w\tr5, [r7, #208]\t@ 0xd0\n-\tvfma.f64\td16, d18, d17\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r4, lsl #3\n+\tvldr\td3, [r5, #88]\t@ 0x58\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd\tr0, ip\n+\tadd.w\tr5, r2, r0, lsl #3\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r4, lsl #3\n+\tvldr\td3, [r5, #96]\t@ 0x60\n+\tldr.w\tr5, [r7, #224]\t@ 0xe0\n+\tvmla.f64\td5, d2, d3\n \tcmp\tr3, r5\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd\tr5, r1\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd\tr5, ip\n \tcmp\tr3, r6\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td18, [r5, #-8]\n-\tadd.w\tr5, r0, r4, lsl #3\n-\tvldr\td17, [r5, #104]\t@ 0x68\n-\tvfma.f64\td16, d18, d17\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadds\tr5, r1, r6\n-\tcmp\tr3, lr\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r4, lsl #3\n+\tvldr\td3, [r5, #104]\t@ 0x68\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd.w\tr5, ip, r6\n+\tcmp\tr3, r9\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r0, r4, lsl #3\n-\tvldr\td18, [r5, #112]\t@ 0x70\n-\tvfma.f64\td16, d18, d17\n-\tblt.n\t95a <__gridxc_atom_MOD_atomxc+0x95a>\n-\tadd.w\tr5, r1, lr\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r4, lsl #3\n+\tvldr\td3, [r5, #112]\t@ 0x70\n+\tvmla.f64\td5, d2, d3\n+\tblt.n\t95c <__gridxc_atom_MOD_atomxc+0x95c>\n+\tadd.w\tr5, ip, r9\n \tadd.w\tr5, r2, r5, lsl #3\n-\tvldr\td18, [r5, #-8]\n-\tadd.w\tr5, r0, r4, lsl #3\n-\tvldr\td17, [r5, #120]\t@ 0x78\n-\tvfma.f64\td16, d18, d17\n-\tvmul.f64\td18, d16, d21\n-\tldr.w\tr3, [r7, #216]\t@ 0xd8\n-\tvstr\td16, [sl]\n-\tvldmia\tr3!, {d17}\n-\tvmul.f64\td17, d17, d17\n-\tstr.w\tr3, [r7, #216]\t@ 0xd8\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tcmp\tr1, #1\n+\tvldr\td2, [r5, #-8]\n+\tadd.w\tr5, r1, r4, lsl #3\n+\tvldr\td3, [r5, #120]\t@ 0x78\n+\tvmla.f64\td5, d2, d3\n+\tvmul.f64\td2, d5, d4\n+\tldr.w\tr2, [r7, #228]\t@ 0xe4\n+\tvstr\td5, [lr]\n+\tvldmia\tr2!, {d3}\n+\tvmul.f64\td3, d3, d3\n+\tstr.w\tr2, [r7, #228]\t@ 0xe4\n+\tldr.w\tr2, [r7, #144]\t@ 0x90\n+\tcmp\tr2, ip\n \tit\tne\n-\tcmpne\tr3, r1\n-\tvmul.f64\td18, d17, d18\n-\tbne.n\t98a <__gridxc_atom_MOD_atomxc+0x98a>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td18, d18, d17\n-\tldr.w\tr3, [r7, #256]\t@ 0x100\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n-\tcmp\tr3, #0\n-\tbne.w\t1c96 <__gridxc_atom_MOD_atomxc+0x1c96>\n-\tcmp.w\tr9, #0\n+\tcmpne.w\tip, #1\n+\tvmul.f64\td2, d3, d2\n+\tbne.n\t98e <__gridxc_atom_MOD_atomxc+0x98e>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td2, d2, d3\n+\tldr.w\tr2, [r7, #268]\t@ 0x10c\n+\tvstr\td2, [r2]\n+\tldr.w\tr2, [r7, #244]\t@ 0xf4\n+\tcmp\tr2, #0\n+\tbne.w\t1c66 <__gridxc_atom_MOD_atomxc+0x1c66>\n+\tcmp.w\tsl, #0\n \tble.n\t9d8 <__gridxc_atom_MOD_atomxc+0x9d8>\n-\tldrd\tr6, ip, [r7, #244]\t@ 0xf4\n+\tldrd\tr6, r8, [r7, #260]\t@ 0x104\n \tmovs\tr5, #1\n-\tldr.w\tr2, [r7, #252]\t@ 0xfc\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tlr, [r7, #272]\t@ 0x110\n-\tvldr\td16, [r6]\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tldr.w\tr0, [r7, #284]\t@ 0x11c\n+\tvldr\td5, [r6]\n \tadds\tr5, #1\n-\tadd\tr6, lr\n-\tcmp\tr9, r5\n-\tvstr\td16, [ip]\n-\tadd\tip, r2\n+\tadd\tr6, r0\n+\tcmp\tsl, r5\n+\tvstr\td5, [r8]\n+\tadd\tr8, r2\n \tbge.n\t9b4 <__gridxc_atom_MOD_atomxc+0x9b4>\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n-\tstr.w\tr2, [r7, #252]\t@ 0xfc\n-\tcmp\tr3, #0\n-\tbne.w\t1f12 <__gridxc_atom_MOD_atomxc+0x1f12>\n-\tldr.w\tr3, [r7, #256]\t@ 0x100\n-\tadds\tr1, #1\n-\tldr.w\tr2, [r7, #132]\t@ 0x84\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tldr.w\tr2, [r7, #244]\t@ 0xf4\n+\tstr.w\tr0, [r7, #284]\t@ 0x11c\n+\tcmp\tr2, #0\n+\tbne.w\t1ecc <__gridxc_atom_MOD_atomxc+0x1ecc>\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n+\tadd.w\tip, ip, #1\n+\tldr.w\tr2, [r7, #140]\t@ 0x8c\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #256]\t@ 0x100\n-\tldr.w\tr3, [r7, #136]\t@ 0x88\n-\tldr.w\tr2, [r7, #144]\t@ 0x90\n-\tadd\tsl, r3\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr3, [r7, #268]\t@ 0x10c\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tldr.w\tr2, [r7, #152]\t@ 0x98\n+\tadd\tlr, r3\n+\tldr.w\tr3, [r7, #248]\t@ 0xf8\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #168]\t@ 0xa8\n-\tstr.w\tr3, [r7, #224]\t@ 0xe0\n-\tldr.w\tr3, [r7, #236]\t@ 0xec\n+\tldr.w\tr2, [r7, #188]\t@ 0xbc\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #172]\t@ 0xac\n-\tstr.w\tr3, [r7, #236]\t@ 0xec\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstr.w\tr3, [r7, #252]\t@ 0xfc\n+\tldr.w\tr3, [r7, #296]\t@ 0x128\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #244]\t@ 0xf4\n-\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #260]\t@ 0x104\n+\tldr.w\tr2, [r7, #164]\t@ 0xa4\n \tadds\tr3, #8\n-\tstr.w\tr3, [r7, #244]\t@ 0xf4\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstr.w\tr3, [r7, #260]\t@ 0x104\n+\tldr.w\tr3, [r7, #264]\t@ 0x108\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tldr.w\tr3, [r7, #156]\t@ 0x9c\n-\tcmp\tr1, r3\n-\tbne.w\t718 <__gridxc_atom_MOD_atomxc+0x718>\n-\tldrd\tr9, r6, [r7, #8]\n-\tcmp\tr6, #0\n-\tbne.w\t2434 <__gridxc_atom_MOD_atomxc+0x2434>\n-\tldr.w\tr1, [r7, #196]\t@ 0xc4\n+\tstr.w\tr3, [r7, #264]\t@ 0x108\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tcmp\tip, r3\n+\tbne.w\t6e2 <__gridxc_atom_MOD_atomxc+0x6e2>\n+\tldrd\tsl, r3, [r7, #96]\t@ 0x60\n+\tldr.w\tr9, [r7, #16]\n+\tcmp\tr3, #0\n+\tbne.w\t23e4 <__gridxc_atom_MOD_atomxc+0x23e4>\n+\tldr.w\tr1, [r7, #212]\t@ 0xd4\n \tmovs\tr3, #0\n \tmovs\tr2, #0\n \tstrd\tr2, r3, [r1]\n-\tldr.w\tr1, [r7, #192]\t@ 0xc0\n+\tldr.w\tr1, [r7, #208]\t@ 0xd0\n \tstrd\tr2, r3, [r1]\n-\tldr.w\tr1, [r7, #188]\t@ 0xbc\n+\tldr.w\tr1, [r7, #204]\t@ 0xcc\n \tstrd\tr2, r3, [r1]\n-\tldr.w\tr1, [r7, #184]\t@ 0xb8\n+\tldr.w\tr1, [r7, #200]\t@ 0xc8\n \tstrd\tr2, r3, [r1]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tcmp\tr3, #0\n-\tble.w\t333c <__gridxc_atom_MOD_atomxc+0x333c>\n-\tldr.w\tr2, [r7, #140]\t@ 0x8c\n+\tble.w\t344e <__gridxc_atom_MOD_atomxc+0x344e>\n+\tldr.w\tr2, [r7, #144]\t@ 0x90\n \tcmp\tr2, #0\n-\tble.w\t3352 <__gridxc_atom_MOD_atomxc+0x3352>\n-\tmov\tr8, r3\n-\tldr\tr3, [r7, #100]\t@ 0x64\n+\tble.w\t3464 <__gridxc_atom_MOD_atomxc+0x3464>\n+\tmov\tr6, r3\n+\tldr\tr3, [r7, #84]\t@ 0x54\n \tlsls\tr5, r2, #3\n \tmovs\tr4, #0\n \tlsls\tr1, r3, #3\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tmov\tr9, r1\n-\tstr.w\tr1, [r7, #272]\t@ 0x110\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tmov\tr8, r1\n+\tstr.w\tr1, [r7, #284]\t@ 0x11c\n \tmov\tr0, r3\n \tmov\tr2, r5\n \tmovs\tr1, #0\n \tadds\tr4, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr3, r0\n-\tadd\tr3, r9\n-\tcmp\tr8, r4\n-\tbne.n\ta8e <__gridxc_atom_MOD_atomxc+0xa8e>\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tadd\tr3, r8\n+\tcmp\tr6, r4\n+\tbne.n\ta94 <__gridxc_atom_MOD_atomxc+0xa94>\n+\tldr.w\tr2, [r7, #280]\t@ 0x118\n \tmovs\tr3, #24\n-\tldr.w\tr5, [pc, #1796]\t@ 11b0 <__gridxc_atom_MOD_atomxc+0x11b0>\n-\tstr\tr6, [r7, #32]\n-\tadd\tr5, pc\n-\tstr\tr5, [r7, #120]\t@ 0x78\n+\tstr.w\tsl, [r7, #300]\t@ 0x12c\n \tmul.w\tr3, r2, r3\n \tadd.w\tr2, r2, r2, lsl #1\n-\tstr.w\tr2, [r7, #148]\t@ 0x94\n+\tstr.w\tr2, [r7, #156]\t@ 0x9c\n \tadds\tr3, #16\n-\tstr.w\tr3, [r7, #268]\t@ 0x10c\n-\tldr.w\tr3, [pc, #1772]\t@ 11b4 <__gridxc_atom_MOD_atomxc+0x11b4>\n-\tldr\tr2, [r7, #68]\t@ 0x44\n+\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [pc, #1760]\t@ 11a8 <__gridxc_atom_MOD_atomxc+0x11a8>\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #216]\t@ 0xd8\n+\tstr.w\tr3, [r7, #196]\t@ 0xc4\n \tsub.w\tr8, r2, #8\n-\tadds\tr3, #188\t@ 0xbc\n+\tadd.w\tr3, r3, #276\t@ 0x114\n \tmovs\tr2, #1\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tadd.w\tr2, r7, #544\t@ 0x220\n-\tstr.w\tr2, [r7, #156]\t@ 0x9c\n-\tadd.w\tr2, r5, #20\n-\tstr\tr2, [r7, #124]\t@ 0x7c\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr4, [r7, #140]\t@ 0x8c\n+\tstr\tr3, [r7, #96]\t@ 0x60\n+\tstr.w\tr2, [r7, #296]\t@ 0x128\n+\tstr.w\tr8, [r7, #44]\t@ 0x2c\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr4, [r7, #144]\t@ 0x90\n \tsubs\tr1, r2, #5\n \tadds\tr3, r2, #5\n \tcmp\tr1, #1\n \tmov\tr0, r3\n \tit\tlt\n \tmovlt\tr1, #1\n \tcmp\tr3, r4\n \tit\tge\n \tmovge\tr0, r4\n \tmov\tr3, r2\n-\tstr.w\tr1, [r7, #200]\t@ 0xc8\n+\tstr.w\tr1, [r7, #216]\t@ 0xd8\n \tsubs\tr2, r1, r2\n \tsubs\tr1, r0, r3\n-\tstr\tr1, [r7, #116]\t@ 0x74\n-\tldr.w\tr1, [r7, #152]\t@ 0x98\n-\tstr.w\tr0, [r7, #144]\t@ 0x90\n-\tcmp\tr1, #0\n-\tstr.w\tr2, [r7, #172]\t@ 0xac\n-\tble.w\t2124 <__gridxc_atom_MOD_atomxc+0x2124>\n-\tldr\tr0, [r7, #52]\t@ 0x34\n-\tadd.w\tr3, r8, r3, lsl #3\n-\tldr.w\tr1, [pc, #1676]\t@ 11b8 <__gridxc_atom_MOD_atomxc+0x11b8>\n-\tstr.w\tr0, [r7, #252]\t@ 0xfc\n-\tldr\tr0, [r7, #36]\t@ 0x24\n-\tadd\tr1, pc\n-\tstr.w\tr0, [r7, #256]\t@ 0x100\n-\tldr\tr0, [r7, #40]\t@ 0x28\n \tstr.w\tr1, [r7, #136]\t@ 0x88\n-\tstr.w\tr0, [r7, #260]\t@ 0x104\n-\tldr.w\tr1, [pc, #1652]\t@ 11bc <__gridxc_atom_MOD_atomxc+0x11bc>\n-\tldr\tr0, [r7, #80]\t@ 0x50\n-\tstr.w\tr0, [r7, #220]\t@ 0xdc\n+\tldr.w\tr1, [r7, #160]\t@ 0xa0\n+\tstr.w\tr0, [r7, #148]\t@ 0x94\n+\tcmp\tr1, #0\n+\tstr.w\tr2, [r7, #184]\t@ 0xb8\n+\tble.w\tf58 <__gridxc_atom_MOD_atomxc+0xf58>\n+\tldr.w\tr1, [pc, #1676]\t@ 11ac <__gridxc_atom_MOD_atomxc+0x11ac>\n \tadd\tr1, pc\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n-\tmov\tfp, r1\n-\tstr.w\tr0, [r7, #224]\t@ 0xe0\n-\tldr\tr0, [r7, #72]\t@ 0x48\n-\tstr.w\tr0, [r7, #228]\t@ 0xe4\n-\tldr\tr0, [r7, #56]\t@ 0x38\n-\tstr\tr3, [r7, #112]\t@ 0x70\n+\tstr.w\tr1, [r7, #140]\t@ 0x8c\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tstr.w\tr1, [r7, #260]\t@ 0x104\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tstr.w\tr1, [r7, #264]\t@ 0x108\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tstr.w\tr1, [r7, #268]\t@ 0x10c\n+\tldr\tr1, [r7, #92]\t@ 0x5c\n+\tstr.w\tr1, [r7, #240]\t@ 0xf0\n+\tldr\tr1, [r7, #88]\t@ 0x58\n+\tstr.w\tr1, [r7, #244]\t@ 0xf4\n+\tldr\tr1, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #236]\t@ 0xec\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n+\tstr.w\tr1, [r7, #248]\t@ 0xf8\n+\tldr\tr1, [r7, #44]\t@ 0x2c\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tstr\tr3, [r7, #116]\t@ 0x74\n \tlsls\tr3, r2, #3\n-\tstr.w\tr0, [r7, #236]\t@ 0xec\n \tstr.w\tr3, [r7, #132]\t@ 0x84\n \tmovs\tr3, #1\n-\tstr.w\tr8, [r7, #48]\t@ 0x30\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tadd.w\tr3, r7, #464\t@ 0x1d0\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\tadd.w\tr3, r7, #432\t@ 0x1b0\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tadd.w\tr3, r7, #352\t@ 0x160\n+\tstr.w\tr3, [r7, #152]\t@ 0x98\n+\tadd.w\tr3, r7, #544\t@ 0x220\n \tstr.w\tr3, [r7, #168]\t@ 0xa8\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tstr.w\tr3, [r7, #232]\t@ 0xe8\n-\tldr.w\tr9, [r7, #252]\t@ 0xfc\n+\tadd.w\tr3, r7, #376\t@ 0x178\n+\tstr.w\tr3, [r7, #228]\t@ 0xe4\n+\tadd.w\tr3, r7, #464\t@ 0x1d0\n+\tstr\tr3, [r7, #104]\t@ 0x68\n+\tadd.w\tr3, r7, #440\t@ 0x1b8\n+\tstr.w\tr3, [r7, #180]\t@ 0xb4\n+\tadd.w\tr3, r7, #328\t@ 0x148\n+\tstr\tr3, [r7, #124]\t@ 0x7c\n+\tadd.w\tr3, r7, #344\t@ 0x158\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tadd.w\tr3, r7, #1032\t@ 0x408\n+\tstr.w\tr3, [r7, #164]\t@ 0xa4\n+\tldr.w\tsl, [r7, #260]\t@ 0x104\n \tmovs\tr2, #3\n-\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tldr.w\tr3, [r7, #140]\t@ 0x8c\n \tmovs\tr0, #20\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tldr\tr3, [r7, #124]\t@ 0x7c\n-\tldr\tr6, [r7, #120]\t@ 0x78\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tvld1.32\t{d8}, [r3]\n-\tldr\tr3, [r6, #40]\t@ 0x28\n-\tldr\tr4, [r6, #28]\n-\tsubs\tr3, r2, r3\n-\tldr\tr2, [r6, #36]\t@ 0x24\n-\tvmov.32\tr5, d8[1]\n+\tldr.w\tr3, [pc, #1532]\t@ 11b0 <__gridxc_atom_MOD_atomxc+0x11b0>\n+\tldr.w\tr4, [r7, #296]\t@ 0x128\n+\tadd\tr3, pc\n+\tldr\tr2, [r3, #40]\t@ 0x28\n+\tldr\tr1, [r3, #36]\t@ 0x24\n+\tsubs\tr2, r4, r2\n+\tldr\tr5, [r3, #0]\n+\tldr\tr4, [r3, #28]\n+\tldrd\tr9, r6, [r3, #20]\n+\tmul.w\tr2, r1, r2\n \trsb\tr4, r4, #1\n-\tmul.w\tr3, r2, r3\n-\tldr\tr2, [r6, #0]\n-\tnegs\tr5, r5\n-\tadd.w\tr8, r2, r3, lsl #3\n-\tldr\tr3, [r6, #32]\n-\tadd\tr4, r3\n+\trsb\tr8, r6, #0\n+\tadd.w\tr5, r5, r2, lsl #3\n+\tldr\tr2, [r3, #32]\n+\tadd\tr4, r2\n \tcmp\tr0, #0\n \tbeq.w\t13a6 <__gridxc_atom_MOD_atomxc+0x13a6>\n-\tldr.w\tr3, [pc, #1516]\t@ 11c0 <__gridxc_atom_MOD_atomxc+0x11c0>\n+\tldr.w\tr3, [pc, #1484]\t@ 11b4 <__gridxc_atom_MOD_atomxc+0x11b4>\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n \tbeq.w\t13a6 <__gridxc_atom_MOD_atomxc+0x13a6>\n-\tldr.w\tr3, [pc, #1500]\t@ 11c4 <__gridxc_atom_MOD_atomxc+0x11c4>\n+\tldr.w\tr3, [pc, #1468]\t@ 11b8 <__gridxc_atom_MOD_atomxc+0x11b8>\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t11f0 <__gridxc_atom_MOD_atomxc+0x11f0>\n-\tldr.w\tr3, [pc, #1480]\t@ 11c8 <__gridxc_atom_MOD_atomxc+0x11c8>\n+\tbeq.w\t11e8 <__gridxc_atom_MOD_atomxc+0x11e8>\n+\tldr.w\tr3, [pc, #1448]\t@ 11bc <__gridxc_atom_MOD_atomxc+0x11bc>\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t11f0 <__gridxc_atom_MOD_atomxc+0x11f0>\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n-\tsub.w\tr3, r1, #1200\t@ 0x4b0\n-\tsubw\tr2, r1, #1188\t@ 0x4a4\n+\tbeq.w\t11e8 <__gridxc_atom_MOD_atomxc+0x11e8>\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tmovs\tr1, #0\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n+\tsub.w\tr3, r2, #1200\t@ 0x4b0\n+\tsubw\tr2, r2, #1188\t@ 0x4a4\n \tstr\tr4, [r3, #32]\n-\tstrd\tr8, r5, [r3]\n-\tvstr\td16, [r2]\n-\tsubw\tr2, r1, #1180\t@ 0x49c\n-\tvst1.32\t{d8}, [r2]\n+\tstr.w\tr9, [r3, #20]\n+\tstr\tr6, [r3, #24]\n+\tstrd\tr5, r8, [r3]\n+\tstrd\tr1, r1, [r2]\n \tmovs\tr2, #8\n \tstr\tr2, [r3, #8]\n \tmovs\tr2, #1\n \tstr\tr2, [r3, #28]\n \tmovw\tr2, #769\t@ 0x301\n \tstrh\tr2, [r3, #16]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #228]\t@ 0xe4\n+\tldr.w\tr3, [r7, #236]\t@ 0xec\n \tstr\tr3, [sp, #32]\n \tmov\tr4, r0\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr.w\tr3, [r7, #244]\t@ 0xf4\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n \tstr\tr3, [sp, #24]\n-\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tldr\tr3, [r7, #108]\t@ 0x6c\n \tstr\tr3, [sp, #20]\n-\tldr\tr3, [r7, #104]\t@ 0x68\n+\tldr\tr3, [r7, #112]\t@ 0x70\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr3, [r7, #124]\t@ 0x7c\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr\tr3, [r7, #120]\t@ 0x78\n \tstr\tr3, [sp, #0]\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr3, r0\n-\tldr.w\tr2, [r7, #204]\t@ 0xcc\n+\tldr.w\tr2, [r7, #220]\t@ 0xdc\n \tldr.w\tr1, [r7, #128]\t@ 0x80\n-\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tldr.w\tr0, [r7, #248]\t@ 0xf8\n \tbl\t0 <__gridxc_lda_MOD_ldaxc>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_ldaxc\n-\tcmp\tr4, r8\n-\tbeq.n\tc9e <__gridxc_atom_MOD_atomxc+0xc9e>\n+\tcmp\tr4, r5\n+\tbeq.n\tcaa <__gridxc_atom_MOD_atomxc+0xcaa>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr1, [r7, #256]\t@ 0x100\n+\tldr.w\tr1, [r7, #264]\t@ 0x108\n \tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tldr.w\tr2, [r7, #240]\t@ 0xf0\n-\tvldr\td16, [r1]\n-\tldr.w\tr1, [r7, #260]\t@ 0x104\n-\tvldr\td23, [r3]\n-\tvldr\td24, [r2]\n-\tvldr\td17, [r1]\n-\tvmul.f64\td24, d16, d24\n-\tvmul.f64\td23, d17, d23\n-\tvstr\td24, [r2]\n-\tvstr\td23, [r3]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr2, [r7, #152]\t@ 0x98\n+\tvldr\td4, [r1]\n+\tldr.w\tr1, [r7, #268]\t@ 0x10c\n+\tvldr\td11, [r3, #-8]\n+\tvldr\td0, [r2, #-8]\n+\tvldr\td3, [r1]\n+\tvmul.f64\td0, d4, d0\n+\tvmul.f64\td11, d3, d11\n+\tvstr\td0, [r2, #-8]\n+\tvstr\td11, [r3, #-8]\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tcmp\tr3, #0\n \tit\tgt\n \tmovgt\tr2, #0\n-\tble.w\tec4 <__gridxc_atom_MOD_atomxc+0xec4>\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr1, [r7, #276]\t@ 0x114\n-\tsub.w\tr3, r3, #1312\t@ 0x520\n+\tble.w\teb4 <__gridxc_atom_MOD_atomxc+0xeb4>\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr1, [r7, #280]\t@ 0x118\n+\tsub.w\tr3, r3, #1304\t@ 0x518\n \tcmp\tr1, #1\n-\tvldr\td18, [r3]\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3]\n-\tble.w\t1bf6 <__gridxc_atom_MOD_atomxc+0x1bf6>\n-\tvldr\td18, [r3, #8]\n+\tvldr\td7, [r3]\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [r3]\n+\tble.w\t1bc6 <__gridxc_atom_MOD_atomxc+0x1bc6>\n+\tvldr\td7, [r3, #8]\n \tcmp\tr1, #2\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3, #8]\n-\tbeq.n\td26 <__gridxc_atom_MOD_atomxc+0xd26>\n-\tvldr\td18, [r3, #16]\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [r3, #8]\n+\tbeq.n\td32 <__gridxc_atom_MOD_atomxc+0xd32>\n+\tvldr\td7, [r3, #16]\n \tcmp\tr1, #3\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3, #16]\n-\tbeq.n\td26 <__gridxc_atom_MOD_atomxc+0xd26>\n-\tvldr\td18, [r3, #24]\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3, #24]\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr1, [r7, #276]\t@ 0x114\n-\tsub.w\tr3, r3, #1376\t@ 0x560\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [r3, #16]\n+\tbeq.n\td32 <__gridxc_atom_MOD_atomxc+0xd32>\n+\tvldr\td7, [r3, #24]\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [r3, #24]\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr1, [r7, #280]\t@ 0x118\n+\tsub.w\tr3, r3, #1368\t@ 0x558\n \tcmp\tr1, #2\n-\tvldr\td19, [r3]\n-\tvldr\td18, [r3, #8]\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td19, [r3]\n-\tvstr\td18, [r3, #8]\n-\tbeq.n\td6a <__gridxc_atom_MOD_atomxc+0xd6a>\n-\tvldr\td18, [r3, #16]\n+\tvldr\td6, [r3]\n+\tvldr\td7, [r3, #8]\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #8]\n+\tbeq.n\td76 <__gridxc_atom_MOD_atomxc+0xd76>\n+\tvldr\td7, [r3, #16]\n \tcmp\tr1, #3\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td18, [r3, #16]\n-\tbeq.n\td6a <__gridxc_atom_MOD_atomxc+0xd6a>\n-\tvldr\td18, [r3, #24]\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td18, [r3, #24]\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td7, [r3, #16]\n+\tbeq.n\td76 <__gridxc_atom_MOD_atomxc+0xd76>\n+\tvldr\td7, [r3, #24]\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td7, [r3, #24]\n \tcmp\tr2, #0\n-\tbne.w\t1aa4 <__gridxc_atom_MOD_atomxc+0x1aa4>\n+\tbne.w\t1a74 <__gridxc_atom_MOD_atomxc+0x1a74>\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #280]\t@ 0x118\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tldr.w\tr2, [fp, #156]\t@ 0x9c\n-\tldr.w\tr0, [r7, #284]\t@ 0x11c\n-\tldr.w\tr1, [fp, #84]\t@ 0x54\n-\tvldr\td26, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tldr.w\tr6, [fp, #72]\t@ 0x48\n-\tldr.w\tr5, [fp, #36]\t@ 0x24\n-\tldr.w\tr4, [fp, #24]\n-\tvldr\td25, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tldr.w\tsl, [r7, #212]\t@ 0xd4\n-\tvldr\td20, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvldr\td19, [r3]\n-\tldr.w\tr3, [fp, #136]\t@ 0x88\n-\tmla\tip, r2, r0, r3\n-\tldr.w\tr2, [fp, #52]\t@ 0x34\n-\tldr.w\tr3, [fp, #4]\n-\tmla\tr2, r1, r0, r2\n-\tldr.w\tr1, [r7, #172]\t@ 0xac\n-\tldr.w\tr0, [fp, #152]\t@ 0x98\n-\tmla\tr2, r1, r6, r2\n-\tldr.w\tr1, [fp, #132]\t@ 0x84\n-\tmla\tr1, r0, ip, r1\n-\tadds\tr0, r3, r4\n-\tvldr\td21, [r1]\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n-\tmla\tr3, r1, r5, r3\n-\tldr.w\tr1, [r7, #200]\t@ 0xc8\n-\tadd\tr3, r4\n-\tmla\tr0, r5, r1, r0\n-\tldr.w\tr1, [fp, #20]\n-\tmul.w\tip, r5, r1\n-\tldr.w\tr5, [fp]\n-\tmul.w\tr9, r1, r4\n-\tmla\tlr, r1, r0, r5\n-\tmla\tr4, r1, r3, r5\n-\tldr.w\tr1, [fp, #68]\t@ 0x44\n-\tldr.w\tr3, [fp, #48]\t@ 0x30\n-\tldr\tr5, [r7, #112]\t@ 0x70\n-\tmul.w\tr8, r1, r6\n-\tmovs\tr6, #16\n-\tmla\tr3, r1, r2, r3\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tmovs\tr1, #16\n+\tldr.w\tr4, [pc, #1076]\t@ 11c0 <__gridxc_atom_MOD_atomxc+0x11c0>\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tadd\tr4, pc\n+\tldr.w\tr8, [r7, #180]\t@ 0xb4\n+\tvldr\td12, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tldr\tr6, [r4, #84]\t@ 0x54\n+\tldr\tr5, [r4, #52]\t@ 0x34\n+\tldr.w\tr0, [r4, #156]\t@ 0x9c\n+\tvldr\td13, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tldr.w\tsl, [r4, #72]\t@ 0x48\n+\tmla\tr5, r6, r2, r5\n+\tldr.w\tr6, [r7, #184]\t@ 0xb8\n+\tldr.w\tip, [r4, #24]\n+\tvldr\td3, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tmla\tr5, r6, sl, r5\n+\tldr.w\tr6, [r4, #132]\t@ 0x84\n+\tldr.w\tlr, [r7, #228]\t@ 0xe4\n+\tvldr\td4, [r3]\n+\tldr\tr3, [r7, #116]\t@ 0x74\n \tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tadd.w\tr3, r7, #1032\t@ 0x408\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n \tadd.w\tr3, r7, #840\t@ 0x348\n-\tstr.w\tfp, [r7, #180]\t@ 0xb4\n-\tldr.w\tfp, [r7, #116]\t@ 0x74\n-\tstr.w\tr3, [r7, #244]\t@ 0xf4\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvldmia\tsl!, {d17}\n-\tvldr\td22, [r5]\n-\tvldr\td16, [r4]\n-\tvldmia\tr3!, {d18}\n-\tvmul.f64\td16, d21, d16\n-\tvadd.f64\td27, d18, d17\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tvsub.f64\td18, d24, d18\n-\tvsub.f64\td17, d23, d17\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n-\tvfma.f64\td26, d16, d24\n-\tvfma.f64\td25, d16, d23\n-\tvfma.f64\td22, d21, d27\n-\tvfma.f64\td20, d16, d18\n-\tvfma.f64\td19, d16, d17\n-\tvstr\td22, [r5]\n-\tcmp\tr3, #0\n-\tbne.w\t1136 <__gridxc_atom_MOD_atomxc+0x1136>\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n-\tadds\tr6, #24\n-\tadd\tr4, r9\n-\tadd\tlr, r9\n-\tadd\tr5, r3\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tcmp\tr3, r6\n-\tbne.n\te42 <__gridxc_atom_MOD_atomxc+0xe42>\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tldr.w\tfp, [r7, #180]\t@ 0xb4\n-\tvstr\td25, [r3]\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvstr\td26, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvstr\td19, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvstr\td20, [r3]\n-\tldr.w\tr2, [r7, #252]\t@ 0xfc\n+\tstr.w\tr3, [r7, #256]\t@ 0x100\n+\tldr.w\tr3, [r4, #136]\t@ 0x88\n+\tmla\tr9, r0, r2, r3\n+\tldr.w\tr2, [r4, #152]\t@ 0x98\n+\tldr\tr0, [r4, #36]\t@ 0x24\n+\tldr\tr3, [r4, #4]\n+\tmla\tr6, r2, r9, r6\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tadd.w\tfp, r3, ip\n+\tldr.w\tr9, [r4, #20]\n+\tmla\tr3, r2, r0, r3\n+\tldr.w\tr2, [r7, #216]\t@ 0xd8\n+\tvldr\td2, [r6]\n+\tldr\tr6, [r4, #0]\n+\tadd\tr3, ip\n+\tmul.w\tip, r9, ip\n+\tmla\tfp, r0, r2, fp\n+\tmul.w\tr0, r0, r9\n+\tmla\tr3, r9, r3, r6\n+\tmla\tr6, r9, fp, r6\n+\tldr.w\tfp, [r4, #68]\t@ 0x44\n+\tldr\tr4, [r4, #48]\t@ 0x30\n+\tmla\tr2, fp, r5, r4\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n+\tmul.w\tfp, fp, sl\n+\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tvldmia\tr8!, {d6}\n+\tvldmia\tlr!, {d5}\n+\tvldr\td9, [r2]\n+\tvldr\td7, [r3]\n+\tvadd.f64\td1, d6, d5\n+\tldr.w\tr4, [r7, #292]\t@ 0x124\n+\tvsub.f64\td6, d0, d6\n+\tvsub.f64\td5, d11, d5\n+\tvmul.f64\td7, d2, d7\n+\tvmla.f64\td9, d1, d2\n+\tvmla.f64\td12, d7, d0\n+\tvmla.f64\td13, d7, d11\n+\tvmla.f64\td3, d6, d7\n+\tvmla.f64\td4, d5, d7\n+\tvstr\td9, [r2]\n+\tcmp\tr4, #0\n+\tbne.w\t111e <__gridxc_atom_MOD_atomxc+0x111e>\n+\tldr.w\tr4, [r7, #284]\t@ 0x11c\n+\tadds\tr1, #24\n+\tadd\tr3, ip\n+\tadd\tr6, ip\n+\tadd\tr2, r4\n+\tldr.w\tr4, [r7, #276]\t@ 0x114\n+\tcmp\tr4, r1\n+\tbne.n\te3e <__gridxc_atom_MOD_atomxc+0xe3e>\n \tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvstr\td13, [r3]\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvstr\td12, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvstr\td3, [r3]\n+\tldr.w\tr2, [r7, #260]\t@ 0x104\n+\tldr.w\tr3, [r7, #224]\t@ 0xe0\n \tadds\tr2, #20\n-\tstr.w\tr2, [r7, #252]\t@ 0xfc\n-\tldr.w\tr2, [r7, #256]\t@ 0x100\n+\tstr.w\tr2, [r7, #260]\t@ 0x104\n+\tldr.w\tr2, [r7, #264]\t@ 0x108\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n \tadds\tr2, #8\n-\tstr.w\tr2, [r7, #256]\t@ 0x100\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n+\tstr.w\tr2, [r7, #264]\t@ 0x108\n+\tldr.w\tr2, [r7, #268]\t@ 0x10c\n \tadds\tr2, #8\n-\tstr.w\tr2, [r7, #260]\t@ 0x104\n-\tldr.w\tr2, [r7, #220]\t@ 0xdc\n-\tadds\tr2, #4\n-\tstr.w\tr2, [r7, #220]\t@ 0xdc\n-\tldr.w\tr2, [r7, #224]\t@ 0xe0\n+\tstr.w\tr2, [r7, #268]\t@ 0x10c\n+\tldr.w\tr2, [r7, #240]\t@ 0xf0\n \tadds\tr2, #4\n-\tstr.w\tr2, [r7, #224]\t@ 0xe0\n-\tldr.w\tr2, [r7, #228]\t@ 0xe4\n+\tstr.w\tr2, [r7, #240]\t@ 0xf0\n+\tldr.w\tr2, [r7, #244]\t@ 0xf4\n \tadds\tr2, #4\n-\tstr.w\tr2, [r7, #228]\t@ 0xe4\n+\tstr.w\tr2, [r7, #244]\t@ 0xf4\n \tldr.w\tr2, [r7, #236]\t@ 0xec\n-\tadds\tr2, #20\n+\tadds\tr2, #4\n \tstr.w\tr2, [r7, #236]\t@ 0xec\n-\tldr.w\tr2, [r7, #152]\t@ 0x98\n+\tldr.w\tr2, [r7, #248]\t@ 0xf8\n+\tadds\tr2, #20\n+\tstr.w\tr2, [r7, #248]\t@ 0xf8\n+\tldr.w\tr2, [r7, #160]\t@ 0xa0\n \tcmp\tr3, r2\n-\tble.w\tb8c <__gridxc_atom_MOD_atomxc+0xb8c>\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr2, [r7, #140]\t@ 0x8c\n+\tble.w\tba0 <__gridxc_atom_MOD_atomxc+0xba0>\n+\tldr.w\tr3, [r7, #296]\t@ 0x128\n+\tldr.w\tr2, [r7, #144]\t@ 0x90\n \tadds\tr3, #1\n-\tldr.w\tr8, [r7, #48]\t@ 0x30\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n \tcmp\tr2, r3\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tbge.w\taec <__gridxc_atom_MOD_atomxc+0xaec>\n-\tldr\tr6, [r7, #32]\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tbge.w\tae4 <__gridxc_atom_MOD_atomxc+0xae4>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tcmp\tr3, #0\n-\tble.n\tf6e <__gridxc_atom_MOD_atomxc+0xf6e>\n-\tldr\tr3, [r7, #80]\t@ 0x50\n+\tble.n\tf58 <__gridxc_atom_MOD_atomxc+0xf58>\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n \tmovs\tr4, #1\n-\tldr\tr5, [r7, #76]\t@ 0x4c\n-\tldr.w\tr9, [r7, #152]\t@ 0x98\n+\tldr\tr5, [r7, #88]\t@ 0x58\n+\tldr.w\tr6, [r7, #160]\t@ 0xa0\n \tsub.w\tr8, r3, #4\n-\tb.n\tf58 <__gridxc_atom_MOD_atomxc+0xf58>\n+\tb.n\tf42 <__gridxc_atom_MOD_atomxc+0xf42>\n \tadds\tr4, #1\n \tadds\tr5, #4\n-\tcmp\tr4, r9\n-\tbgt.n\tf6e <__gridxc_atom_MOD_atomxc+0xf6e>\n+\tcmp\tr4, r6\n+\tbgt.n\tf58 <__gridxc_atom_MOD_atomxc+0xf58>\n \tldr.w\tr3, [r8, #4]!\n \tcmp\tr3, #0\n-\tbeq.n\tf50 <__gridxc_atom_MOD_atomxc+0xf50>\n+\tbeq.n\tf3a <__gridxc_atom_MOD_atomxc+0xf3a>\n \tmov\tr0, r5\n \tadds\tr4, #1\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_end>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_end\n \tadds\tr5, #4\n-\tcmp\tr4, r9\n-\tble.n\tf58 <__gridxc_atom_MOD_atomxc+0xf58>\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n+\tcmp\tr4, r6\n+\tble.n\tf42 <__gridxc_atom_MOD_atomxc+0xf42>\n+\tldr\tr0, [r7, #88]\t@ 0x58\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [r7, #72]\t@ 0x48\n+\tldr\tr0, [r7, #80]\t@ 0x50\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [r7, #80]\t@ 0x50\n+\tldr\tr0, [r7, #92]\t@ 0x5c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tcmp\tr3, #0\n-\tble.w\t3372 <__gridxc_atom_MOD_atomxc+0x3372>\n-\tldr\tr2, [r7, #68]\t@ 0x44\n+\tble.w\t3484 <__gridxc_atom_MOD_atomxc+0x3484>\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n \tmovs\tr5, #1\n-\tldr\tr3, [pc, #572]\t@ (11cc <__gridxc_atom_MOD_atomxc+0x11cc>)\n-\tvmov.f64\td19, #16\t@ 0x40800000 4.0\n+\tldr\tr3, [pc, #584]\t@ (11c4 <__gridxc_atom_MOD_atomxc+0x11c4>)\n+\tvmov.f64\td4, #16\t@ 0x40800000 4.0\n \tadd.w\tip, r2, #8\n-\tldr\tr2, [r7, #100]\t@ 0x64\n+\tldr\tr2, [r7, #84]\t@ 0x54\n \tadd\tr3, pc\n-\tldr.w\tfp, [r7, #140]\t@ 0x8c\n-\tldr.w\tsl, [r7, #60]\t@ 0x3c\n+\tldr.w\tsl, [r7, #144]\t@ 0x90\n+\tldr\tr6, [r7, #68]\t@ 0x44\n \tmov\tr4, ip\n \tmov.w\tlr, r2, lsl #3\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tldr.w\tr2, [r7, #280]\t@ 0x118\n \tldr.w\tr1, [r3, #156]\t@ 0x9c\n \tadd.w\tr8, r2, #1\n \tldr.w\tr2, [r3, #136]\t@ 0x88\n \tldr.w\tr0, [r3, #152]\t@ 0x98\n \tldr.w\tr3, [r3, #132]\t@ 0x84\n \tadd.w\tr2, r2, r1, lsl #1\n-\tvldr\td20, [pc, #480]\t@ 11a8 <__gridxc_atom_MOD_atomxc+0x11a8>\n+\tvldr\td3, [pc, #496]\t@ 11a0 <__gridxc_atom_MOD_atomxc+0x11a0>\n \tmla\tr9, r0, r2, r3\n \tmul.w\tr0, r1, r0\n-\tcmp.w\tfp, #1\n-\tit\tgt\n+\tcmp.w\tsl, #1\n+\tittt\tgt\n \tmovgt\tr1, r9\n-\tit\tgt\n \tmovgt\tr2, r4\n-\tit\tgt\n \tmovgt\tr3, #0\n-\tble.n\tffc <__gridxc_atom_MOD_atomxc+0xffc>\n-\tvldr\td18, [r2]\n+\tble.n\tfe0 <__gridxc_atom_MOD_atomxc+0xfe0>\n+\tvldr\td5, [r2]\n \tadds\tr3, #1\n-\tvldr\td17, [r1]\n-\tcmp\tsl, r3\n+\tvldr\td6, [r1]\n+\tcmp\tr6, r3\n \tadd\tr1, r0\n-\tvdiv.f64\td16, d18, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\tfe4 <__gridxc_atom_MOD_atomxc+0xfe4>\n-\tvldr\td17, [r4]\n+\tvdiv.f64\td7, d5, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\tfc8 <__gridxc_atom_MOD_atomxc+0xfc8>\n+\tvldr\td6, [r4]\n \tadds\tr5, #1\n-\tvldr\td16, [r4, #8]\n+\tvldr\td7, [r4, #8]\n \tcmp\tr8, r5\n-\tvfnms.f64\td16, d17, d19\n-\tvmul.f64\td16, d16, d20\n-\tvstr\td16, [r4, #-8]\n+\tvnmls.f64\td7, d6, d4\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td7, [r4, #-8]\n \tadd\tr4, lr\n-\tbne.n\tfd2 <__gridxc_atom_MOD_atomxc+0xfd2>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvldr\td18, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvadd.f64\td18, d18, d18\n-\tvldr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvadd.f64\td16, d16, d16\n-\tvldr\td17, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvadd.f64\td17, d17, d17\n-\tvldr\td19, [r3]\n-\tvadd.f64\td19, d19, d19\n-\tcmp\tr6, #0\n-\tbne.w\t2150 <__gridxc_atom_MOD_atomxc+0x2150>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvstr\td19, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvstr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvstr\td17, [r3]\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n+\tbne.n\tfba <__gridxc_atom_MOD_atomxc+0xfba>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvldr\td4, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvadd.f64\td4, d4, d4\n+\tvldr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvadd.f64\td5, d5, d5\n+\tvldr\td6, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvadd.f64\td6, d6, d6\n+\tvldr\td7, [r3]\n+\tldr\tr3, [r7, #100]\t@ 0x64\n+\tvadd.f64\td7, d7, d7\n \tcmp\tr3, #0\n-\tble.n\t10ac <__gridxc_atom_MOD_atomxc+0x10ac>\n-\tldr.w\tr4, [r7, #140]\t@ 0x8c\n+\tbne.w\t20fc <__gridxc_atom_MOD_atomxc+0x20fc>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvstr\td7, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvstr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvstr\td6, [r3]\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tcmp\tr3, #0\n+\tble.n\t1094 <__gridxc_atom_MOD_atomxc+0x1094>\n+\tldr.w\tr4, [r7, #144]\t@ 0x90\n \tmov.w\tr0, #4294967295\t@ 0xffffffff\n-\tldr\tr5, [r7, #100]\t@ 0x64\n+\tldr\tr5, [r7, #84]\t@ 0x54\n \tmovs\tr1, #1\n-\tldr.w\tlr, [r7, #276]\t@ 0x114\n+\tldr.w\tr6, [r7, #280]\t@ 0x118\n \tadd.w\tr2, ip, r0, lsl #3\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadds\tr3, #1\n \tcmp\tr4, r3\n-\tvadd.f64\td16, d16, d16\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t108c <__gridxc_atom_MOD_atomxc+0x108c>\n+\tvadd.f64\td7, d7, d7\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t1072 <__gridxc_atom_MOD_atomxc+0x1072>\n \tadds\tr1, #1\n \tadd\tr0, r5\n-\tcmp\tlr, r1\n-\tbge.n\t1086 <__gridxc_atom_MOD_atomxc+0x1086>\n-\tcmp\tr6, #0\n-\tbne.w\t2344 <__gridxc_atom_MOD_atomxc+0x2344>\n-\tldr\tr5, [pc, #288]\t@ (11d0 <__gridxc_atom_MOD_atomxc+0x11d0>)\n+\tcmp\tr6, r1\n+\tbge.n\t106c <__gridxc_atom_MOD_atomxc+0x106c>\n+\tldr\tr3, [r7, #100]\t@ 0x64\n+\tcmp\tr3, #0\n+\tbne.w\t22ec <__gridxc_atom_MOD_atomxc+0x22ec>\n+\tldr\tr5, [pc, #304]\t@ (11c8 <__gridxc_atom_MOD_atomxc+0x11c8>)\n \tmovs\tr4, #0\n-\tldr\tr1, [pc, #288]\t@ (11d4 <__gridxc_atom_MOD_atomxc+0x11d4>)\n+\tldr\tr1, [pc, #304]\t@ (11cc <__gridxc_atom_MOD_atomxc+0x11cc>)\n \tmovs\tr3, #9\n \tadd\tr5, pc\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tadd.w\tr0, r5, #168\t@ 0xa8\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d3\n-\tldr\tr1, [pc, #272]\t@ (11d8 <__gridxc_atom_MOD_atomxc+0x11d8>)\n+\tldr\tr1, [pc, #288]\t@ (11d0 <__gridxc_atom_MOD_atomxc+0x11d0>)\n \tmovs\tr3, #11\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tadd.w\tr0, r5, #132\t@ 0x84\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #260]\t@ (11dc <__gridxc_atom_MOD_atomxc+0x11dc>)\n+\tldr\tr1, [pc, #276]\t@ (11d4 <__gridxc_atom_MOD_atomxc+0x11d4>)\n \tmovs\tr3, #11\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tadd.w\tr0, r5, #96\t@ 0x60\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #244]\t@ (11e0 <__gridxc_atom_MOD_atomxc+0x11e0>)\n+\tldr\tr1, [pc, #260]\t@ (11d8 <__gridxc_atom_MOD_atomxc+0x11d8>)\n \tmovs\tr3, #12\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tadd.w\tr0, r5, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #232]\t@ (11e4 <__gridxc_atom_MOD_atomxc+0x11e4>)\n+\tldr\tr1, [pc, #248]\t@ (11dc <__gridxc_atom_MOD_atomxc+0x11dc>)\n \tmovs\tr3, #8\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tmov\tr0, r5\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr2, [pc, #220]\t@ (11e8 <__gridxc_atom_MOD_atomxc+0x11e8>)\n-\tldr\tr3, [pc, #220]\t@ (11ec <__gridxc_atom_MOD_atomxc+0x11ec>)\n+\tldr\tr2, [pc, #236]\t@ (11e0 <__gridxc_atom_MOD_atomxc+0x11e0>)\n+\tldr\tr3, [pc, #236]\t@ (11e4 <__gridxc_atom_MOD_atomxc+0x11e4>)\n \tadd.w\tr1, r7, #14016\t@ 0x36c0\n \tadd\tr2, pc\n \tadds\tr1, #12\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t35d0 <__gridxc_atom_MOD_atomxc+0x35d0>\n+\tbne.w\t34e0 <__gridxc_atom_MOD_atomxc+0x34e0>\n \tadd.w\tr7, r7, #14016\t@ 0x36c0\n \tadds\tr7, #20\n \tmov\tsp, r7\n-\tvpop\t{d8-d11}\n+\tvpop\t{d8-d13}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr.w\tr3, [r7, #200]\t@ 0xc8\n-\tldr.w\tr2, [r7, #144]\t@ 0x90\n-\tcmp\tr3, r2\n-\tbgt.w\te8c <__gridxc_atom_MOD_atomxc+0xe8c>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n-\tmov\tr2, lr\n-\tldr.w\tr1, [r7, #264]\t@ 0x108\n-\tadd\tr3, r6\n-\tvldr\td29, [r3]\n-\tldr.w\tr3, [r7, #244]\t@ 0xf4\n-\tadd\tr3, r6\n-\tvldr\td28, [r3]\n-\tldr.w\tr3, [r7, #132]\t@ 0x84\n-\tvadd.f64\td27, d29, d28\n-\tadds\tr0, r5, r3\n-\tldr.w\tr3, [r7, #172]\t@ 0xac\n-\tvmul.f64\td27, d27, d21\n-\tvldr\td16, [r1]\n-\tadds\tr3, #1\n-\tvldr\td18, [r0]\n-\tadd\tr1, r8\n-\tvldr\td17, [r2]\n-\tcmp\tfp, r3\n-\tvfma.f64\td18, d16, d27\n-\tvmul.f64\td22, d29, d16\n-\tvmul.f64\td16, d16, d28\n-\tadd\tr2, ip\n-\tvnmul.f64\td17, d17, d21\n-\tvfma.f64\td20, d17, d22\n-\tvfma.f64\td19, d16, d17\n-\tvstmia\tr0!, {d18}\n-\tbge.n\t1170 <__gridxc_atom_MOD_atomxc+0x1170>\n-\tb.n\te8c <__gridxc_atom_MOD_atomxc+0xe8c>\n+\tldr.w\tr4, [r7, #216]\t@ 0xd8\n+\tldr.w\tr5, [r7, #148]\t@ 0x94\n+\tcmp\tr4, r5\n+\tbgt.w\te80 <__gridxc_atom_MOD_atomxc+0xe80>\n+\tldr.w\tr4, [r7, #164]\t@ 0xa4\n+\tmov\tr5, r6\n+\tstr.w\tr6, [r7, #288]\t@ 0x120\n+\tadd\tr4, r1\n+\tldr.w\tr9, [r7, #272]\t@ 0x110\n+\tldr.w\tr6, [r7, #136]\t@ 0x88\n+\tvldr\td9, [r4]\n+\tldr.w\tr4, [r7, #256]\t@ 0x100\n+\tadd\tr4, r1\n+\tvldr\td8, [r4]\n+\tldr.w\tr4, [r7, #132]\t@ 0x84\n+\tvadd.f64\td1, d9, d8\n+\tadd.w\tsl, r4, r2\n+\tldr.w\tr4, [r7, #184]\t@ 0xb8\n+\tvmul.f64\td1, d1, d2\n+\tvldr\td7, [r9]\n+\tadds\tr4, #1\n+\tvldr\td5, [sl]\n+\tadd\tr9, fp\n+\tvldr\td6, [r5]\n+\tcmp\tr6, r4\n+\tvmla.f64\td5, d7, d1\n+\tvmul.f64\td10, d9, d7\n+\tvmul.f64\td7, d7, d8\n+\tadd\tr5, r0\n+\tvmul.f64\td6, d2, d6\n+\tvmls.f64\td3, d10, d6\n+\tvmls.f64\td4, d7, d6\n+\tvstmia\tsl!, {d5}\n+\tbge.n\t1162 <__gridxc_atom_MOD_atomxc+0x1162>\n+\tldr.w\tr6, [r7, #288]\t@ 0x120\n+\tb.n\te80 <__gridxc_atom_MOD_atomxc+0xe80>\n+\tnop\n \tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x000006fe\n+\t.word\t0x000006da\n R_ARM_REL32\t.bss\n-\t.word\t0x000006e6\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000680\n+\t.word\t0x00000686\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000066a\n+\t.word\t0x000005f2\n R_ARM_REL32\t.bss\n-\t.word\t0x000005e2\n+\t.word\t0x000005c2\n R_ARM_REL32\t.LC2\n-\t.word\t0x000005d0\n+\t.word\t0x000005b0\n R_ARM_REL32\t.LC3\n-\t.word\t0x000005be\n+\t.word\t0x0000059e\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000022e\n+\t.word\t0x0000042c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000118\n+\t.word\t0x0000023c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000118\n+\t.word\t0x00000128\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000128\n R_ARM_REL32\t.LC24\n-\t.word\t0x0000010a\n+\t.word\t0x0000011a\n R_ARM_REL32\t.LC22\n-\t.word\t0x000000fc\n+\t.word\t0x0000010c\n R_ARM_REL32\t.LC21\n-\t.word\t0x000000ee\n+\t.word\t0x000000fe\n R_ARM_REL32\t.LC20\n-\t.word\t0x000000e0\n+\t.word\t0x000000f0\n R_ARM_REL32\t.LC17\n-\t.word\t0x000000d2\n+\t.word\t0x000000e2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\tldr.w\tr3, [pc, #2180]\t@ 1a78 <__gridxc_atom_MOD_atomxc+0x1a78>\n+\tldr.w\tr3, [pc, #2140]\t@ 1a48 <__gridxc_atom_MOD_atomxc+0x1a48>\n \tmovs\tr2, #5\n-\tldr.w\tr6, [r7, #236]\t@ 0xec\n+\tldr.w\tsl, [r7, #248]\t@ 0xf8\n \tmovs\tr0, #20\n \tadd\tr3, pc\n-\tmov\tr1, r6\n+\tmov\tr1, sl\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1240 <__gridxc_atom_MOD_atomxc+0x1240>\n-\tldr.w\tr3, [pc, #2164]\t@ 1a7c <__gridxc_atom_MOD_atomxc+0x1a7c>\n+\tcbz\tr0, 1238 <__gridxc_atom_MOD_atomxc+0x1238>\n+\tldr.w\tr3, [pc, #2124]\t@ 1a4c <__gridxc_atom_MOD_atomxc+0x1a4c>\n \tmovs\tr2, #5\n-\tmov\tr1, r6\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1240 <__gridxc_atom_MOD_atomxc+0x1240>\n-\tldr.w\tr3, [pc, #2148]\t@ 1a80 <__gridxc_atom_MOD_atomxc+0x1a80>\n+\tcbz\tr0, 1238 <__gridxc_atom_MOD_atomxc+0x1238>\n+\tldr.w\tr3, [pc, #2108]\t@ 1a50 <__gridxc_atom_MOD_atomxc+0x1a50>\n \tmovs\tr2, #4\n-\tmov\tr1, r6\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1240 <__gridxc_atom_MOD_atomxc+0x1240>\n-\tldr.w\tr3, [pc, #2136]\t@ 1a84 <__gridxc_atom_MOD_atomxc+0x1a84>\n+\tcbz\tr0, 1238 <__gridxc_atom_MOD_atomxc+0x1238>\n+\tldr.w\tr3, [pc, #2096]\t@ 1a54 <__gridxc_atom_MOD_atomxc+0x1a54>\n \tmovs\tr2, #4\n-\tmov\tr1, r6\n+\tmov\tr1, sl\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t1ff8 <__gridxc_atom_MOD_atomxc+0x1ff8>\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tmovs\tr6, #8\n-\tadd.w\tr0, r7, #504\t@ 0x1f8\n-\tsub.w\tr3, r1, #1240\t@ 0x4d8\n-\tsubw\tr2, r1, #1228\t@ 0x4cc\n+\tbne.w\t1fc0 <__gridxc_atom_MOD_atomxc+0x1fc0>\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tadd.w\tr0, r7, #508\t@ 0x1fc\n+\tsubw\tr3, r2, #1236\t@ 0x4d4\n+\tsub.w\tr2, r2, #1224\t@ 0x4c8\n+\tstr.w\tr9, [r3, #20]\n+\tmov.w\tr9, #8\n \tstr\tr4, [r3, #32]\n-\tmov\tr4, r1\n-\tstrd\tr8, r5, [r3]\n-\tmovs\tr5, #1\n-\tvstr\td9, [r2]\n-\tsubw\tr2, r1, #1220\t@ 0x4c4\n-\tvst1.32\t{d8}, [r2]\n+\tstr\tr6, [r3, #24]\n+\tmovs\tr6, #0\n+\tstrd\tr5, r8, [r3]\n+\tmov.w\tr8, #1\n+\tstrd\tr6, r6, [r2]\n \tmovw\tr2, #769\t@ 0x301\n-\tstr\tr6, [r3, #8]\n-\tstr\tr5, [r3, #28]\n+\tstr.w\tr8, [r3, #28]\n \tstrh\tr2, [r3, #16]\n+\tstr.w\tr9, [r3, #8]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr2, [pc, #2060]\t@ 1a88 <__gridxc_atom_MOD_atomxc+0x1a88>\n-\tmov\tr9, r0\n-\tldr.w\tr0, [r7, #284]\t@ 0x11c\n+\tldr.w\tr2, [pc, #2016]\t@ 1a58 <__gridxc_atom_MOD_atomxc+0x1a58>\n+\tmov\tr4, r0\n+\tldr.w\tr0, [r7, #296]\t@ 0x128\n \tadd\tr2, pc\n-\tsub.w\tr3, r4, #1200\t@ 0x4b0\n-\tadd.w\tr1, r2, #188\t@ 0xbc\n-\tstr\tr6, [r3, #8]\n-\tvld1.32\t{d16}, [r1]\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r3, #1200\t@ 0x4b0\n \tldr.w\tr1, [r2, #220]\t@ 0xdc\n-\tstr\tr5, [r3, #28]\n \tsubs\tr1, r0, r1\n \tldr.w\tr0, [r2, #216]\t@ 0xd8\n-\tstr\tr5, [r3, #40]\t@ 0x28\n-\tmul.w\tip, r0, r1\n-\tldr.w\tr1, [r2, #196]\t@ 0xc4\n-\tvmov.32\tr0, d16[1]\n-\tsubs\tr6, r5, r1\n-\tldr.w\tr1, [r2, #208]\t@ 0xd0\n-\tsubs\tr1, r5, r1\n-\tldr.w\tr5, [r2, #168]\t@ 0xa8\n-\tnegs\tr0, r0\n-\tadd.w\tr5, r5, ip, lsl #3\n-\tsubw\tip, r4, #1188\t@ 0x4a4\n-\tstr\tr5, [r3, #0]\n-\tvstr\td9, [ip]\n-\tsubw\tip, r4, #1180\t@ 0x49c\n-\tvst1.32\t{d16}, [ip]\n-\tldr.w\tip, [r2, #204]\t@ 0xcc\n-\tstr.w\tip, [r3, #36]\t@ 0x24\n-\tsub.w\tr0, r0, ip\n-\tstr\tr0, [r3, #4]\n-\tldr.w\tr0, [r2, #200]\t@ 0xc8\n-\tldr.w\tr2, [r2, #212]\t@ 0xd4\n-\tadd\tr6, r0\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n-\tadd\tr1, r2\n-\tstr\tr6, [r3, #32]\n-\tstr\tr1, [r3, #44]\t@ 0x2c\n+\tstr.w\tr8, [r3, #28]\n+\tstr.w\tr8, [r3, #40]\t@ 0x28\n+\tstr.w\tr9, [r3, #8]\n+\tmul.w\tlr, r0, r1\n+\tldr.w\tr0, [r7, #300]\t@ 0x12c\n+\tldr.w\tr1, [r2, #192]\t@ 0xc0\n+\tsubw\tr0, r0, #1188\t@ 0x4a4\n+\tstr\tr1, [r3, #24]\n+\tnegs\tr1, r1\n+\tstrd\tr6, r6, [r0]\n+\tldr.w\tr6, [r2, #168]\t@ 0xa8\n+\tldr.w\tr0, [r2, #196]\t@ 0xc4\n+\tadd.w\tr6, r6, lr, lsl #3\n+\tldr.w\tlr, [r2, #204]\t@ 0xcc\n+\tsub.w\tip, r8, r0\n+\tldr.w\tr0, [r2, #208]\t@ 0xd0\n+\tsub.w\tr1, r1, lr\n+\tstr\tr1, [r3, #4]\n+\tldr.w\tr1, [r2, #200]\t@ 0xc8\n+\tsub.w\tr0, r8, r0\n+\tstr.w\tlr, [r3, #36]\t@ 0x24\n+\tadd\tr1, ip\n+\tstr\tr1, [r3, #32]\n+\tldr.w\tr1, [r2, #212]\t@ 0xd4\n+\tldr.w\tr2, [r2, #188]\t@ 0xbc\n+\tadd\tr0, r1\n+\tstr\tr2, [r3, #20]\n+\tstr\tr0, [r3, #44]\t@ 0x2c\n \tmovw\tr2, #770\t@ 0x302\n+\tstr\tr6, [r3, #0]\n \tstrh\tr2, [r3, #16]\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #228]\t@ 0xe4\n+\tldr.w\tr3, [r7, #236]\t@ 0xec\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tmov\tr6, r0\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tmov\tr8, r0\n+\tldr.w\tr3, [r7, #244]\t@ 0xf4\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tstr\tr3, [sp, #20]\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr3, [r7, #124]\t@ 0x7c\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr\tr3, [r7, #120]\t@ 0x78\n \tstrd\tr0, r3, [sp]\n \tmovs\tr3, #3\n-\tldr.w\tr0, [pc, #1884]\t@ 1a8c <__gridxc_atom_MOD_atomxc+0x1a8c>\n+\tldr.w\tr0, [pc, #1828]\t@ 1a5c <__gridxc_atom_MOD_atomxc+0x1a5c>\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tadd.w\tr3, r7, #840\t@ 0x348\n \tstr\tr3, [sp, #24]\n-\tadd.w\tr3, r7, #1032\t@ 0x408\n-\tstr\tr3, [sp, #20]\n \tadd\tr0, pc\n-\tldr.w\tr2, [r7, #204]\t@ 0xcc\n-\tmov\tr3, r9\n+\tldr.w\tr2, [r7, #220]\t@ 0xdc\n+\tmov\tr3, r4\n \tldr.w\tr1, [r7, #128]\t@ 0x80\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n-\tcmp\tr9, r8\n+\tcmp\tr4, r5\n \tbeq.n\t135a <__gridxc_atom_MOD_atomxc+0x135a>\n-\tmov\tr0, r9\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr5, r6\n+\tcmp\tr6, r8\n \tbeq.n\t1364 <__gridxc_atom_MOD_atomxc+0x1364>\n-\tmov\tr0, r6\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tldr.w\tr2, [r7, #256]\t@ 0x100\n-\tvldr\td23, [r3]\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n-\tvldr\td16, [r2]\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n-\tvldr\td24, [r3]\n-\tvldr\td17, [r2]\n-\tvmul.f64\td24, d16, d24\n-\tvmul.f64\td23, d17, d23\n-\tvstr\td24, [r3]\n+\tldr.w\tr2, [r7, #264]\t@ 0x108\n+\tvldr\td11, [r3, #-8]\n+\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tvldr\td4, [r2]\n+\tldr.w\tr2, [r7, #268]\t@ 0x10c\n+\tvldr\td0, [r3, #-8]\n+\tvldr\td3, [r2]\n+\tvmul.f64\td0, d4, d0\n+\tvmul.f64\td11, d3, d11\n+\tvstr\td0, [r3, #-8]\n \tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tvstr\td23, [r3]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tvstr\td11, [r3, #-8]\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tcmp\tr3, #0\n-\tble.w\tec4 <__gridxc_atom_MOD_atomxc+0xec4>\n+\tble.w\teb4 <__gridxc_atom_MOD_atomxc+0xeb4>\n \tmovs\tr2, #1\n-\tb.n\tcdc <__gridxc_atom_MOD_atomxc+0xcdc>\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tmovs\tr6, #8\n-\tsub.w\tr3, r1, #1240\t@ 0x4d8\n-\tsubw\tr2, r1, #1228\t@ 0x4cc\n+\tb.n\tce8 <__gridxc_atom_MOD_atomxc+0xce8>\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tadd.w\tfp, r7, #528\t@ 0x210\n+\tsub.w\tr1, fp, #20\n+\tstr.w\tr1, [r7, #292]\t@ 0x124\n+\tsubw\tr3, r2, #1236\t@ 0x4d4\n+\tsub.w\tr2, r2, #1224\t@ 0x4c8\n+\tmov\tr0, r1\n+\tstr.w\tr9, [r3, #20]\n+\tmov.w\tr9, #8\n \tstr\tr4, [r3, #32]\n-\tstrd\tr8, r5, [r3]\n-\tmovs\tr5, #1\n-\tvstr\td9, [r2]\n-\tsubw\tr2, r1, #1220\t@ 0x4c4\n-\tvst1.32\t{d8}, [r2]\n-\tadd.w\tr2, r7, #504\t@ 0x1f8\n-\tstr\tr6, [r3, #8]\n-\tmov\tr0, r2\n-\tstr\tr5, [r3, #28]\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n+\tstr\tr6, [r3, #24]\n+\tmovs\tr6, #0\n+\tstrd\tr5, r8, [r3]\n+\tmov.w\tr8, #1\n+\tstrd\tr6, r6, [r2]\n \tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr8, [r3, #28]\n \tstrh\tr2, [r3, #16]\n+\tstr.w\tr9, [r3, #8]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [r7, #84]\t@ 0x54\n+\tldr.w\tr2, [pc, #1648]\t@ 1a60 <__gridxc_atom_MOD_atomxc+0x1a60>\n \tmov\tr4, r0\n-\tldr.w\tr0, [r7, #216]\t@ 0xd8\n-\tvld1.32\t{d16}, [r2]\n-\tldr.w\tr3, [r0, #220]\t@ 0xdc\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tvmov.32\tr1, d16[1]\n-\tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r0, #216]\t@ 0xd8\n-\tmul.w\tr0, r2, r3\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tnegs\tr1, r1\n+\tldr.w\tr0, [r7, #296]\t@ 0x128\n+\tadd\tr2, pc\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n \tsub.w\tr3, r3, #1200\t@ 0x4b0\n-\tstr\tr5, [r3, #28]\n-\tstr\tr5, [r3, #40]\t@ 0x28\n-\tldr.w\tr5, [r7, #216]\t@ 0xd8\n-\tstr\tr6, [r3, #8]\n-\tldr.w\tr2, [r5, #208]\t@ 0xd0\n-\tldr.w\tr6, [r5, #196]\t@ 0xc4\n-\tldr.w\tr5, [r5, #168]\t@ 0xa8\n-\trsb\tr2, r2, #1\n-\trsb\tr6, r6, #1\n-\tadd.w\tr5, r5, r0, lsl #3\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tstr\tr5, [r3, #0]\n+\tldr.w\tr1, [r2, #220]\t@ 0xdc\n+\tsubs\tr1, r0, r1\n+\tldr.w\tr0, [r2, #216]\t@ 0xd8\n+\tstr.w\tr8, [r3, #28]\n+\tstr.w\tr8, [r3, #40]\t@ 0x28\n+\tstr.w\tr9, [r3, #8]\n+\tmul.w\tlr, r0, r1\n+\tldr.w\tr0, [r7, #300]\t@ 0x12c\n+\tldr.w\tr1, [r2, #192]\t@ 0xc0\n \tsubw\tr0, r0, #1188\t@ 0x4a4\n-\tvstr\td9, [r0]\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tsubw\tr0, r0, #1180\t@ 0x49c\n-\tvst1.32\t{d16}, [r0]\n-\tldr.w\tr0, [r7, #216]\t@ 0xd8\n-\tldr.w\tr0, [r0, #204]\t@ 0xcc\n-\tstr\tr0, [r3, #36]\t@ 0x24\n-\tsubs\tr1, r1, r0\n-\tldr.w\tr0, [r7, #216]\t@ 0xd8\n+\tstr\tr1, [r3, #24]\n+\tnegs\tr1, r1\n+\tstrd\tr6, r6, [r0]\n+\tldr.w\tr6, [r2, #168]\t@ 0xa8\n+\tldr.w\tr0, [r2, #196]\t@ 0xc4\n+\tadd.w\tr6, r6, lr, lsl #3\n+\tldr.w\tlr, [r2, #204]\t@ 0xcc\n+\tsub.w\tip, r8, r0\n+\tldr.w\tr0, [r2, #208]\t@ 0xd0\n+\tsub.w\tr1, r1, lr\n \tstr\tr1, [r3, #4]\n-\tldr.w\tr1, [r0, #200]\t@ 0xc8\n-\tadd\tr6, r1\n-\tldr.w\tr1, [r0, #212]\t@ 0xd4\n-\tstr\tr6, [r3, #32]\n-\tadd\tr2, r1\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n-\tstr\tr2, [r3, #44]\t@ 0x2c\n+\tldr.w\tr1, [r2, #200]\t@ 0xc8\n+\tsub.w\tr0, r8, r0\n+\tstr.w\tlr, [r3, #36]\t@ 0x24\n+\tadd\tr1, ip\n+\tstr\tr1, [r3, #32]\n+\tldr.w\tr1, [r2, #212]\t@ 0xd4\n+\tldr.w\tr2, [r2, #188]\t@ 0xbc\n+\tadd\tr0, r1\n+\tstr\tr2, [r3, #20]\n+\tstr\tr0, [r3, #44]\t@ 0x2c\n \tmovw\tr2, #770\t@ 0x302\n+\tstr\tr6, [r3, #0]\n \tstrh\tr2, [r3, #16]\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n-\tstr\tr3, [sp, #12]\n-\tmov\tr6, r0\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tstr\tr3, [sp, #16]\n+\tmov\tr8, r0\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tmov\tr2, r4\n+\tstr\tr3, [sp, #12]\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr3, [r7, #124]\t@ 0x7c\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr\tr3, [r7, #120]\t@ 0x78\n \tstr\tr3, [sp, #0]\n \tadd.w\tr3, r7, #840\t@ 0x348\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #192]\t@ 0xc0\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #1032\t@ 0x408\n-\tstr\tr3, [sp, #16]\n \tmov\tr3, r0\n-\tldr.w\tr1, [r7, #204]\t@ 0xcc\n+\tldr.w\tr1, [r7, #220]\t@ 0xdc\n \tldr.w\tr0, [r7, #128]\t@ 0x80\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_localxc>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_localxc\n-\tcmp\tr4, r8\n-\tbeq.n\t14c0 <__gridxc_atom_MOD_atomxc+0x14c0>\n+\tcmp\tr4, r5\n+\tbeq.n\t14ba <__gridxc_atom_MOD_atomxc+0x14ba>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr5, r6\n-\tbeq.n\t14ca <__gridxc_atom_MOD_atomxc+0x14ca>\n-\tmov\tr0, r6\n+\tcmp\tr6, r8\n+\tbeq.n\t14c4 <__gridxc_atom_MOD_atomxc+0x14c4>\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tldr.w\tr4, [pc, #1468]\t@ 1a90 <__gridxc_atom_MOD_atomxc+0x1a90>\n-\tmov.w\tr8, #1\n-\tsubw\tr2, r0, #1228\t@ 0x4cc\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmovs\tr6, #0\n+\tldr.w\tr4, [pc, #1432]\t@ 1a64 <__gridxc_atom_MOD_atomxc+0x1a64>\n+\tmov.w\tr9, #1\n+\tsubw\tr1, r3, #1236\t@ 0x4d4\n+\tsub.w\tr3, r3, #1224\t@ 0x4c8\n \tadd\tr4, pc\n-\tsub.w\tr3, r0, #1240\t@ 0x4d8\n-\tmov.w\tr9, #8\n-\tvstr\td8, [r2]\n-\tadd.w\tr2, r4, #20\n-\tldr\tr6, [r4, #0]\n-\tvld1.32\t{d16}, [r2]\n-\tldr\tr2, [r4, #40]\t@ 0x28\n-\tsubs\tr2, r1, r2\n-\tldr\tr1, [r4, #36]\t@ 0x24\n-\tmul.w\tr1, r2, r1\n-\tvmov.32\tr2, d16[1]\n-\tadd.w\tr6, r6, r1, lsl #3\n-\tsubw\tr1, r0, #1220\t@ 0x4c4\n-\tstr\tr6, [r3, #0]\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tmov.w\tsl, #8\n+\tldr.w\tr0, [r7, #292]\t@ 0x124\n+\tstrd\tr6, r6, [r3]\n+\tldr\tr3, [r4, #40]\t@ 0x28\n+\tstr.w\tsl, [r1, #8]\n+\tsubs\tr3, r2, r3\n+\tldr\tr2, [r4, #36]\t@ 0x24\n+\tstr.w\tr9, [r1, #28]\n+\tmul.w\tr5, r2, r3\n+\tldr\tr2, [r4, #0]\n+\tldr\tr3, [r4, #28]\n+\tadd.w\tr8, r2, r5, lsl #3\n+\tldr\tr2, [r4, #24]\n+\tstr\tr2, [r1, #24]\n+\trsb\tr3, r3, #1\n \tnegs\tr2, r2\n-\tstr\tr2, [r3, #4]\n-\tldr\tr2, [r4, #28]\n-\tvst1.32\t{d16}, [r1]\n-\tldr\tr1, [r4, #32]\n-\trsb\tr2, r2, #1\n-\tstr.w\tr8, [r3, #28]\n-\tadd\tr2, r1\n-\tstr.w\tr9, [r3, #8]\n-\tstr\tr2, [r3, #32]\n-\tmovw\tr2, #769\t@ 0x301\n-\tldr.w\tr0, [r7, #288]\t@ 0x120\n-\tstrh\tr2, [r3, #16]\n+\tstr\tr2, [r1, #4]\n+\tldr\tr2, [r4, #32]\n+\tstr.w\tr8, [r1]\n+\tadd\tr3, r2\n+\tstr\tr3, [r1, #32]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r1, #20]\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh\tr3, [r1, #16]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, r4, #188\t@ 0xbc\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n-\tmov\tr5, r0\n-\tldr.w\tr2, [r4, #216]\t@ 0xd8\n-\tvld1.32\t{d16}, [r3]\n \tldr.w\tr3, [r4, #220]\t@ 0xdc\n-\tsubs\tr3, r1, r3\n-\tldr.w\tr1, [r4, #168]\t@ 0xa8\n-\tvmov.32\tr0, d16[1]\n-\tmul.w\tlr, r2, r3\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr2, [r4, #196]\t@ 0xc4\n-\tsub.w\tr3, r3, #1200\t@ 0x4b0\n-\tsub.w\tip, r8, r2\n-\tldr.w\tr2, [r4, #208]\t@ 0xd0\n-\tnegs\tr0, r0\n-\tstr.w\tr8, [r3, #28]\n-\tsub.w\tr2, r8, r2\n-\tstr.w\tr8, [r3, #40]\t@ 0x28\n-\tadd.w\tr8, r1, lr, lsl #3\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tstr.w\tr9, [r3, #8]\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tmov\tr5, r0\n+\tldr.w\tr1, [r4, #216]\t@ 0xd8\n+\tsubs\tr3, r2, r3\n+\tldr.w\tr2, [r4, #192]\t@ 0xc0\n+\tmul.w\tip, r1, r3\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r1, #1200\t@ 0x4b0\n \tsubw\tr1, r1, #1188\t@ 0x4a4\n-\tstr.w\tr8, [r3]\n-\tvstr\td8, [r1]\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tsubw\tr1, r1, #1180\t@ 0x49c\n-\tvst1.32\t{d16}, [r1]\n-\tldr.w\tr1, [r4, #204]\t@ 0xcc\n-\tstr\tr1, [r3, #36]\t@ 0x24\n-\tsubs\tr0, r0, r1\n-\tldr.w\tr1, [r4, #200]\t@ 0xc8\n-\tstr\tr0, [r3, #4]\n-\tadd\tr1, ip\n-\tstr\tr1, [r3, #32]\n-\tldr.w\tr1, [r4, #212]\t@ 0xd4\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n-\tadd\tr2, r1\n-\tstr\tr2, [r3, #44]\t@ 0x2c\n+\tstr\tr2, [r3, #24]\n+\tnegs\tr2, r2\n+\tstr.w\tsl, [r3, #8]\n+\tstr.w\tr9, [r3, #28]\n+\tstr.w\tr9, [r3, #40]\t@ 0x28\n+\tstrd\tr6, r6, [r1]\n+\tldr.w\tr6, [r4, #168]\t@ 0xa8\n+\tldr.w\tr1, [r4, #196]\t@ 0xc4\n+\tadd.w\tr6, r6, ip, lsl #3\n+\tldr.w\tip, [r4, #204]\t@ 0xcc\n+\tsub.w\tr0, r9, r1\n+\tldr.w\tr1, [r4, #208]\t@ 0xd0\n+\tsub.w\tr2, r2, ip\n+\tstr\tr2, [r3, #4]\n+\tldr.w\tr2, [r4, #200]\t@ 0xc8\n+\tsub.w\tr1, r9, r1\n+\tstr.w\tip, [r3, #36]\t@ 0x24\n+\tadd\tr0, r2\n+\tldr.w\tr2, [r4, #212]\t@ 0xd4\n+\tstr\tr0, [r3, #32]\n+\tadd\tr1, r2\n+\tldr.w\tr2, [r4, #188]\t@ 0xbc\n+\tstr\tr1, [r3, #44]\t@ 0x2c\n+\tstr\tr2, [r3, #20]\n \tmovw\tr2, #770\t@ 0x302\n+\tstr\tr6, [r3, #0]\n \tstrh\tr2, [r3, #16]\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tstr\tr3, [sp, #0]\n \tadd.w\tr3, r7, #936\t@ 0x3a8\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n \tmov\tr2, r0\n \tstr\tr3, [sp, #4]\n \tmov\tr4, r0\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr\tr3, [r7, #104]\t@ 0x68\n \tmov\tr1, r5\n-\tldr.w\tr0, [r7, #204]\t@ 0xcc\n-\tsubs\tr3, #8\n+\tsubs\tr3, #56\t@ 0x38\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr.w\tr0, [r7, #220]\t@ 0xdc\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_decusp>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_decusp\n-\tcmp\tr6, r5\n-\tbeq.n\t15fa <__gridxc_atom_MOD_atomxc+0x15fa>\n+\tcmp\tr8, r5\n+\tbeq.n\t15de <__gridxc_atom_MOD_atomxc+0x15de>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr8, r4\n-\tbeq.n\t1604 <__gridxc_atom_MOD_atomxc+0x1604>\n+\tcmp\tr6, r4\n+\tbeq.n\t15e8 <__gridxc_atom_MOD_atomxc+0x15e8>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr5, [pc, #1164]\t@ 1a94 <__gridxc_atom_MOD_atomxc+0x1a94>\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tldr\tr4, [r7, #88]\t@ 0x58\n+\tldr.w\tr6, [r7, #196]\t@ 0xc4\n+\tsub.w\tr0, fp, #56\t@ 0x38\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n \tmov.w\tr9, #1\n-\tadd\tr5, pc\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tadd.w\tr2, r5, #20\n-\tadd.w\tr3, r4, #20\n-\tmov\tr0, r4\n-\tmov.w\tsl, #8\n-\tvstr\td8, [r4, #12]\n-\tvld1.32\t{d16}, [r2]\n-\tldr\tr2, [r5, #36]\t@ 0x24\n-\tstr.w\tsl, [r4, #8]\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [r5, #40]\t@ 0x28\n-\tstr.w\tr9, [r4, #28]\n-\tsubs\tr3, r6, r3\n-\tmul.w\tr1, r2, r3\n-\tvmov.32\tr3, d16[1]\n-\tldr\tr2, [r5, #0]\n-\tadd.w\tr2, r2, r1, lsl #3\n-\tstr\tr2, [r4, #0]\n-\tnegs\tr3, r3\n-\tstr\tr3, [r4, #4]\n-\tldr\tr3, [r5, #28]\n-\tstr.w\tr2, [r7, #280]\t@ 0x118\n-\tldr\tr2, [r5, #32]\n-\trsb\tr3, r3, #1\n-\tadd\tr3, r2\n-\tstr\tr3, [r4, #32]\n-\tmovw\tr3, #769\t@ 0x301\n-\tstrh\tr3, [r4, #16]\n+\tmov.w\tr8, #8\n+\tldr\tr3, [r6, #40]\t@ 0x28\n+\tldr\tr4, [r6, #0]\n+\tsubs\tr3, r2, r3\n+\tldr\tr2, [r6, #36]\t@ 0x24\n+\tmul.w\tr5, r2, r3\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r2, #1272\t@ 0x4f8\n+\tsubw\tr1, r2, #1260\t@ 0x4ec\n+\tadd.w\tr4, r4, r5, lsl #3\n+\tstr.w\tr4, [r7, #288]\t@ 0x120\n+\tldr\tr2, [r6, #28]\n+\tmovs\tr5, #0\n+\tstr\tr4, [r3, #0]\n+\tldr\tr4, [r6, #24]\n+\trsb\tr2, r2, #1\n+\tstr\tr4, [r3, #24]\n+\tnegs\tr4, r4\n+\tstr\tr4, [r3, #4]\n+\tldr\tr4, [r6, #32]\n+\tstr.w\tr8, [r3, #8]\n+\tadd\tr2, r4\n+\tmov\tr4, r6\n+\tstr\tr2, [r3, #32]\n+\tldr\tr2, [r6, #20]\n+\tmovw\tr6, #769\t@ 0x301\n+\tstr\tr2, [r3, #20]\n+\tstr.w\tr9, [r3, #28]\n+\tstrd\tr5, r5, [r1]\n+\tstrh\tr6, [r3, #16]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, r5, #188\t@ 0xbc\n-\tldr.w\tr2, [r5, #216]\t@ 0xd8\n-\tmov\tr8, r0\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r5, #220]\t@ 0xdc\n-\tstr.w\tr6, [r7, #284]\t@ 0x11c\n-\tsubs\tr3, r6, r3\n-\tvmov.32\tr0, d16[1]\n+\tldr.w\tr3, [r4, #220]\t@ 0xdc\n+\tmov\tfp, r0\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n+\tldr.w\tr2, [r4, #216]\t@ 0xd8\n+\tsubs\tr3, r1, r3\n+\tldr.w\tr0, [r4, #192]\t@ 0xc0\n+\tmov\tr1, r4\n+\tstr.w\tr1, [r7, #196]\t@ 0xc4\n \tmul.w\tr6, r2, r3\n-\tsub.w\tr3, r1, #1200\t@ 0x4b0\n-\tldr.w\tr1, [r5, #168]\t@ 0xa8\n-\tldr.w\tr2, [r5, #196]\t@ 0xc4\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r2, #1200\t@ 0x4b0\n+\tsubw\tr2, r2, #1188\t@ 0x4a4\n+\tstr\tr0, [r3, #24]\n \tnegs\tr0, r0\n-\tstr.w\tsl, [r3, #8]\n-\tadd.w\tip, r1, r6, lsl #3\n-\tldr.w\tr6, [r7, #292]\t@ 0x124\n-\tstr.w\tip, [r3]\n-\tsub.w\tr4, r9, r2\n-\tsubw\tr1, r6, #1188\t@ 0x4a4\n+\tstr.w\tr8, [r3, #8]\n \tstr.w\tr9, [r3, #28]\n \tstr.w\tr9, [r3, #40]\t@ 0x28\n-\tldr.w\tr2, [r5, #208]\t@ 0xd0\n-\tvstr\td8, [r1]\n-\tsubw\tr1, r6, #1180\t@ 0x49c\n+\tstrd\tr5, r5, [r2]\n+\tldr.w\tr2, [r4, #196]\t@ 0xc4\n+\tsub.w\tr4, r9, r2\n+\tldr.w\tr2, [r1, #208]\t@ 0xd0\n+\tldr.w\tr1, [r1, #168]\t@ 0xa8\n \tsub.w\tr2, r9, r2\n-\tstr.w\tip, [r7, #264]\t@ 0x108\n-\tvst1.32\t{d16}, [r1]\n-\tldr.w\tr1, [r5, #204]\t@ 0xcc\n+\tadd.w\tsl, r1, r6, lsl #3\n+\tldr.w\tr6, [r7, #196]\t@ 0xc4\n+\tstr.w\tsl, [r3]\n+\tldr.w\tr1, [r6, #204]\t@ 0xcc\n \tstr\tr1, [r3, #36]\t@ 0x24\n \tsubs\tr0, r0, r1\n-\tldr.w\tr1, [r5, #200]\t@ 0xc8\n+\tldr.w\tr1, [r6, #200]\t@ 0xc8\n \tstr\tr0, [r3, #4]\n \tadd\tr4, r1\n-\tldr.w\tr1, [r5, #212]\t@ 0xd4\n+\tldr.w\tr1, [r6, #212]\t@ 0xd4\n \tstr\tr4, [r3, #32]\n+\tmov\tr4, r6\n \tadd\tr2, r1\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n \tstr\tr2, [r3, #44]\t@ 0x2c\n+\tldr.w\tr2, [r6, #188]\t@ 0xbc\n+\tstr\tr2, [r3, #20]\n \tmovw\tr2, #770\t@ 0x302\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n \tstrh\tr2, [r3, #16]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr2, [r5, #520]\t@ 0x208\n-\tldr.w\tr4, [r7, #284]\t@ 0x11c\n+\tldr.w\tr2, [r4, #520]\t@ 0x208\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n \tmov\tr6, r0\n \tsub.w\tip, r9, r2\n-\tldr.w\tr0, [r5, #516]\t@ 0x204\n-\tldr.w\tr2, [r5, #508]\t@ 0x1fc\n-\tldr.w\tr1, [r5, #504]\t@ 0x1f8\n-\tsubs\tr2, r4, r2\n-\tldr.w\tr4, [r7, #292]\t@ 0x124\n+\tldr.w\tr2, [r4, #508]\t@ 0x1fc\n+\tldr.w\tr0, [r4, #516]\t@ 0x204\n+\tsubs\tr2, r1, r2\n+\tldr.w\tr1, [r4, #504]\t@ 0x1f8\n+\tstr.w\tr4, [r7, #196]\t@ 0xc4\n+\tldr.w\tr3, [r7, #292]\t@ 0x124\n \tmul.w\tip, r0, ip\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n \tmla\tip, r1, r2, ip\n-\tsub.w\tr2, r4, #1440\t@ 0x5a0\n-\tsub.w\tr1, r4, #1240\t@ 0x4d8\n-\tldr\tr2, [r2, #0]\n-\tstrd\tr9, r2, [r1, #28]\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r5, #480]\t@ 0x1e0\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n+\tsub.w\tr2, r1, #1432\t@ 0x598\n+\tsubw\tr1, r1, #1236\t@ 0x4d4\n \tstr\tr0, [r1, #24]\n \tnegs\tr0, r0\n-\tstr.w\tsl, [r1, #8]\n+\tstr\tr0, [r1, #4]\n+\tldr.w\tr0, [r7, #196]\t@ 0xc4\n+\tldr\tr4, [r2, #0]\n+\tstr.w\tr8, [r1, #8]\n+\tldr.w\tr2, [r0, #480]\t@ 0x1e0\n+\tstrd\tr9, r4, [r1, #28]\n \tadd.w\tr2, r2, ip, lsl #3\n \tstr\tr2, [r1, #0]\n-\tsubw\tr2, r4, #1228\t@ 0x4cc\n-\tstr\tr0, [r1, #4]\n-\tmovw\tr0, #769\t@ 0x301\n-\tvstr\td8, [r2]\n-\tldr.w\tr2, [r5, #500]\t@ 0x1f4\n-\tstrh\tr0, [r1, #16]\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tsub.w\tr2, r2, #1224\t@ 0x4c8\n+\tstrd\tr5, r5, [r2]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstrh\tr2, [r1, #16]\n+\tldr.w\tr2, [r0, #500]\t@ 0x1f4\n \tstr\tr2, [r1, #20]\n-\tadd.w\tr2, r5, #276\t@ 0x114\n-\tadds\tr5, #228\t@ 0xe4\n+\tmov\tr1, fp\n+\tldr\tr2, [r7, #96]\t@ 0x60\n \tstr\tr2, [sp, #4]\n-\tstr\tr5, [sp, #0]\n+\tadd.w\tr2, r0, #228\t@ 0xe4\n+\tstr\tr2, [sp, #0]\n \tmov\tr2, r6\n-\tldr.w\tr0, [r7, #204]\t@ 0xcc\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #220]\t@ 0xdc\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_theta\n-\tldr.w\tr2, [r7, #280]\t@ 0x118\n-\tcmp\tr2, r8\n-\tbeq.n\t178a <__gridxc_atom_MOD_atomxc+0x178a>\n-\tmov\tr0, r8\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n+\tcmp\tr3, fp\n+\tbeq.n\t1770 <__gridxc_atom_MOD_atomxc+0x1770>\n+\tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tcmp\tr3, r6\n-\tbeq.n\t1798 <__gridxc_atom_MOD_atomxc+0x1798>\n+\tcmp\tsl, r6\n+\tbeq.n\t177a <__gridxc_atom_MOD_atomxc+0x177a>\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #764]\t@ (1a98 <__gridxc_atom_MOD_atomxc+0x1a98>)\n-\tldr.w\tr6, [r7, #276]\t@ 0x114\n+\tldr\tr3, [pc, #748]\t@ (1a68 <__gridxc_atom_MOD_atomxc+0x1a68>)\n+\tldr.w\tr6, [r7, #280]\t@ 0x118\n \tadd\tr3, pc\n \tcmp\tr6, #0\n-\tldrd\tr1, r2, [r3]\n+\tldrd\tip, r2, [r3]\n \tldr\tr0, [r3, #24]\n \tldr\tr5, [r3, #36]\t@ 0x24\n-\tble.w\t1c62 <__gridxc_atom_MOD_atomxc+0x1c62>\n-\tldr.w\tr4, [r7, #284]\t@ 0x11c\n+\tble.w\t1c32 <__gridxc_atom_MOD_atomxc+0x1c32>\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n \tcmp\tr6, #1\n-\tmla\tr2, r4, r5, r2\n+\tmla\tr2, r1, r5, r2\n \tldr\tr5, [r3, #20]\n \tadd.w\tr3, r2, r0\n-\tmla\tr2, r3, r5, r1\n-\tvldr\td16, [r2]\n-\tble.n\t17d6 <__gridxc_atom_MOD_atomxc+0x17d6>\n+\tmla\tr2, r3, r5, ip\n+\tvldr\td7, [r2]\n+\tble.n\t17b8 <__gridxc_atom_MOD_atomxc+0x17b8>\n \tadd\tr0, r3\n-\tmla\tr1, r5, r0, r1\n-\tvldr\td17, [r1]\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td19, [pc, #664]\t@ 1a70 <__gridxc_atom_MOD_atomxc+0x1a70>\n-\tvadd.f64\td19, d16, d19\n-\tldr\tr5, [pc, #700]\t@ (1a9c <__gridxc_atom_MOD_atomxc+0x1a9c>)\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n-\tadd\tr5, pc\n-\tldr.w\tr4, [r7, #288]\t@ 0x120\n+\tmla\tr1, r5, r0, ip\n+\tvldr\td6, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td4, [pc, #636]\t@ 1a38 <__gridxc_atom_MOD_atomxc+0x1a38>\n+\tvadd.f64\td4, d7, d4\n+\tldr\tr6, [pc, #680]\t@ (1a6c <__gridxc_atom_MOD_atomxc+0x1a6c>)\n \tcmp\tr4, #0\n-\tldr.w\tr3, [r5, #600]\t@ 0x258\n-\tldr.w\tr6, [r5, #580]\t@ 0x244\n-\tldr.w\tr2, [r5, #484]\t@ 0x1e4\n-\tldr.w\tr9, [r5, #576]\t@ 0x240\n-\tldr.w\tr8, [r5, #612]\t@ 0x264\n-\tmla\tr6, r3, r1, r6\n-\tldr.w\tr3, [r5, #504]\t@ 0x1f8\n-\tmla\tr2, r3, r1, r2\n-\tldr.w\tr3, [r5, #480]\t@ 0x1e0\n-\tldr.w\tr1, [r5, #516]\t@ 0x204\n-\tble.w\t1c90 <__gridxc_atom_MOD_atomxc+0x1c90>\n-\tldr.w\tr0, [r5, #596]\t@ 0x254\n-\tadd\tr2, r1\n-\tldr.w\tr5, [r5, #500]\t@ 0x1f4\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmla\tr3, r5, r2, r3\n-\tadd.w\tr2, r8, r6\n-\tmul.w\tr5, r1, r5\n-\tmovs\tr1, #0\n-\tmla\tr2, r0, r2, r9\n-\tmul.w\tr0, r8, r0\n-\tvldr\td18, [r2]\n-\tadds\tr1, #1\n-\tvldr\td17, [r3]\n-\tadd\tr2, r0\n-\tadd\tr3, r5\n-\tcmp\tr1, r4\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t183c <__gridxc_atom_MOD_atomxc+0x183c>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tstr.w\tr4, [r7, #288]\t@ 0x120\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d19\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tldr.w\tr2, [r7, #240]\t@ 0xf0\n-\tldr.w\tr1, [r7, #260]\t@ 0x104\n-\tvldr\td23, [r3]\n-\tvldr\td16, [r2, #-8]\n-\tvldr\td19, [r1]\n-\tldr.w\tr1, [r7, #256]\t@ 0x100\n-\tvadd.f64\td23, d16, d23\n-\tvldr\td21, [r2]\n-\tvldr\td20, [r1]\n-\tvadd.f64\td23, d23, d17\n-\tvstr\td23, [r3]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n-\tcmp\tr3, #0\n-\tble.w\t1c78 <__gridxc_atom_MOD_atomxc+0x1c78>\n-\tadd.w\tr3, r6, r8\n-\tldr\tr6, [pc, #508]\t@ (1aa0 <__gridxc_atom_MOD_atomxc+0x1aa0>)\n-\tmov\tr4, r3\n-\tldr\tr2, [r7, #108]\t@ 0x6c\n+\tldr.w\tr0, [r7, #296]\t@ 0x128\n \tadd\tr6, pc\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n-\tldr.w\tsl, [r7, #212]\t@ 0xd4\n-\tmovs\tr1, #0\n-\tstr.w\tfp, [r7, #96]\t@ 0x60\n+\tldr.w\tr2, [r6, #600]\t@ 0x258\n+\tldr.w\tr3, [r6, #580]\t@ 0x244\n+\tldr.w\tr1, [r6, #484]\t@ 0x1e4\n+\tldr.w\tr9, [r6, #576]\t@ 0x240\n+\tmla\tip, r2, r0, r3\n+\tldr.w\tr3, [r6, #504]\t@ 0x1f8\n+\tldr.w\tr2, [r6, #480]\t@ 0x1e0\n+\tmla\tr1, r3, r0, r1\n+\tldr.w\tr3, [r6, #612]\t@ 0x264\n+\tldr.w\tr0, [r6, #516]\t@ 0x204\n+\tble.w\t1c60 <__gridxc_atom_MOD_atomxc+0x1c60>\n+\tldr.w\tr5, [r6, #596]\t@ 0x254\n+\tadd\tr1, r0\n+\tldr.w\tr6, [r6, #500]\t@ 0x1f4\n+\tvldr\td7, [pc, #572]\t@ 1a40 <__gridxc_atom_MOD_atomxc+0x1a40>\n+\tmla\tr2, r6, r1, r2\n+\tadd.w\tr1, r3, ip\n+\tmul.w\tr6, r0, r6\n+\tmovs\tr0, #0\n+\tmla\tr1, r5, r1, r9\n+\tmul.w\tr5, r3, r5\n+\tvldr\td5, [r1]\n+\tadds\tr0, #1\n+\tvldr\td6, [r2]\n+\tadd\tr1, r5\n+\tadd\tr2, r6\n+\tcmp\tr4, r0\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t181a <__gridxc_atom_MOD_atomxc+0x181a>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td11, d7, d4\n+\tldr.w\tr2, [r7, #232]\t@ 0xe8\n+\tldr.w\tr1, [r7, #268]\t@ 0x10c\n+\tvldr\td5, [r2, #-8]\n+\tvldr\td7, [r2]\n+\tvldr\td4, [r1]\n+\tldr.w\tr1, [r7, #264]\t@ 0x108\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td3, [r1]\n+\tldr.w\tr1, [r7, #152]\t@ 0x98\n+\tvldr\td1, [r1, #-8]\n+\tvadd.f64\td11, d7, d11\n+\tvstr\td11, [r2, #-8]\n+\tldr.w\tr2, [r7, #280]\t@ 0x118\n+\tcmp\tr2, #0\n+\tble.w\t1c48 <__gridxc_atom_MOD_atomxc+0x1c48>\n+\tldr\tr6, [pc, #504]\t@ (1a70 <__gridxc_atom_MOD_atomxc+0x1a70>)\n+\tmovs\tr2, #0\n+\tstr.w\tr2, [r7, #256]\t@ 0x100\n+\tadd.w\tsl, ip, r3\n+\tadd\tr6, pc\n+\tldr.w\tfp, [r7, #228]\t@ 0xe4\n \tldr.w\tlr, [r6, #300]\t@ 0x12c\n-\tldr.w\tr3, [r6, #280]\t@ 0x118\n-\tldr.w\tr2, [r6, #264]\t@ 0x108\n-\tadd.w\tip, lr, r3\n-\tldr.w\tr3, [r6, #232]\t@ 0xe8\n+\tldr.w\tr2, [r6, #280]\t@ 0x118\n+\tldr.w\tr5, [r6, #264]\t@ 0x108\n+\tadd.w\tip, lr, r2\n+\tldr.w\tr2, [r6, #232]\t@ 0xe8\n \tldr.w\tr0, [r6, #324]\t@ 0x144\n-\tadd\tr3, r2\n+\tadd.w\tr8, r5, r2\n \tldr.w\tr2, [r6, #252]\t@ 0xfc\n \tadd\tip, r0\n \tldr.w\tr5, [r6, #312]\t@ 0x138\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tldr.w\tr3, [r6, #296]\t@ 0x128\n+\tadd.w\tr1, r8, r2\n+\tldr.w\tr8, [r6, #296]\t@ 0x128\n \tadd\tip, r5\n-\tmul.w\tr0, r3, r0\n-\tstr.w\tr0, [r7, #164]\t@ 0xa4\n-\tmul.w\tr0, r3, lr\n-\tstr.w\tr0, [r7, #280]\t@ 0x118\n-\tmul.w\tr5, r3, r5\n+\tmul.w\tr0, r8, r0\n+\tstr.w\tr0, [r7, #176]\t@ 0xb0\n+\tmul.w\tr0, r8, lr\n+\tstr.w\tr0, [r7, #288]\t@ 0x120\n+\tmul.w\tr5, r5, r8\n \tldr.w\tlr, [r6, #248]\t@ 0xf8\n \tldr.w\tr0, [r6, #264]\t@ 0x108\n \tmul.w\tr2, r2, lr\n \tmul.w\tr0, lr, r0\n-\tstr.w\tr0, [r7, #160]\t@ 0xa0\n+\tstr.w\tr0, [r7, #172]\t@ 0xac\n \tldr.w\tr0, [r6, #596]\t@ 0x254\n-\tmla\tr9, r0, r4, r9\n-\tldr.w\tr4, [r6, #276]\t@ 0x114\n+\tmla\tr9, r0, sl, r9\n+\tmul.w\tr0, r3, r0\n+\tldr.w\tr3, [r6, #276]\t@ 0x114\n \tldr.w\tr6, [r6, #228]\t@ 0xe4\n-\tmul.w\tr0, r8, r0\n-\tmla\tr3, r3, ip, r4\n-\tldr.w\tr4, [r7, #248]\t@ 0xf8\n-\tmla\tr4, lr, r4, r6\n+\tstr.w\tr9, [r7, #292]\t@ 0x124\n+\tmla\tr3, r8, ip, r3\n+\tmla\tr1, lr, r1, r6\n+\tstr.w\tr1, [r7, #252]\t@ 0xfc\n \tmov\tr6, r3\n-\tstr.w\tr4, [r7, #248]\t@ 0xf8\n-\tldr.w\tip, [r7, #248]\t@ 0xf8\n-\tldr.w\tr4, [r7, #288]\t@ 0x120\n-\tstr.w\tr9, [r7, #288]\t@ 0x120\n-\tvmov.i64\td16, #0x0000000000000000\n+\tldr.w\tip, [r7, #252]\t@ 0xfc\n+\tmovs\tr1, #0\n+\tvldr\td7, [pc, #304]\t@ 1a40 <__gridxc_atom_MOD_atomxc+0x1a40>\n \tcmp\tr4, #0\n-\tble.n\t1966 <__gridxc_atom_MOD_atomxc+0x1966>\n-\tldr.w\tlr, [r7, #288]\t@ 0x120\n+\tble.n\t1932 <__gridxc_atom_MOD_atomxc+0x1932>\n+\tldr.w\tlr, [r7, #292]\t@ 0x124\n \tmov\tr8, ip\n \tmovs\tr3, #0\n-\tvldr\td18, [lr]\n+\tvldr\td5, [lr]\n \tadds\tr3, #1\n-\tvldr\td17, [r8]\n+\tvldr\td6, [r8]\n \tadd\tlr, r0\n \tadd\tr8, r2\n \tcmp\tr3, r4\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t1950 <__gridxc_atom_MOD_atomxc+0x1950>\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t191c <__gridxc_atom_MOD_atomxc+0x191c>\n+\tldr.w\tr3, [r7, #272]\t@ 0x110\n \tmov.w\tr9, r1, lsl #3\n-\tvldr\td17, [sl]\n+\tvldr\td6, [fp]\n \tadds\tr1, #3\n-\tmov\tfp, r6\n+\tmov\tsl, r6\n \tmov.w\tlr, #1\n-\tstrd\tr6, r2, [r7, #244]\t@ 0xf4\n-\tvldmia\tr3!, {d18}\n-\tvadd.f64\td17, d17, d18\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n-\tldr.w\tr3, [r7, #180]\t@ 0xb4\n+\tstrd\tr6, r2, [r7, #252]\t@ 0xfc\n+\tvldmia\tr3!, {d5}\n+\tvadd.f64\td6, d6, d5\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tldr.w\tr3, [r7, #192]\t@ 0xc0\n \tadd.w\tr8, r3, r9\n-\tldr.w\tr3, [r7, #176]\t@ 0xb0\n-\tvadd.f64\td17, d17, d16\n+\tldr.w\tr3, [r7, #188]\t@ 0xbc\n+\tvadd.f64\td6, d6, d7\n \tadd\tr9, r3\n-\tvstmia\tsl!, {d17}\n-\tvmov.i64\td16, #0x0000000000000000\n+\tvstmia\tfp!, {d6}\n+\tvldr\td7, [pc, #208]\t@ 1a40 <__gridxc_atom_MOD_atomxc+0x1a40>\n \tcmp\tr4, #0\n-\tble.n\t19c6 <__gridxc_atom_MOD_atomxc+0x19c6>\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tmov\tr6, fp\n+\tble.n\t1992 <__gridxc_atom_MOD_atomxc+0x1992>\n+\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tmov\tr6, sl\n \tmovs\tr3, #0\n-\tvldr\td18, [r2]\n+\tvldr\td5, [r2]\n \tadds\tr3, #1\n-\tvldr\td17, [r6]\n+\tvldr\td6, [r6]\n \tadd\tr2, r0\n \tadd\tr6, r5\n-\tcmp\tr4, r3\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t19b0 <__gridxc_atom_MOD_atomxc+0x19b0>\n-\tvldr\td17, [r8]\n+\tcmp\tr3, r4\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t197c <__gridxc_atom_MOD_atomxc+0x197c>\n+\tvldr\td6, [r8]\n \tadd.w\tlr, lr, #1\n-\tvldmia\tr9!, {d18}\n+\tvldmia\tr9!, {d5}\n \tcmp.w\tlr, #4\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n-\tvadd.f64\td17, d17, d18\n-\tadd\tfp, r3\n-\tvadd.f64\td17, d17, d16\n-\tvstmia\tr8!, {d17}\n-\tbne.n\t19a0 <__gridxc_atom_MOD_atomxc+0x19a0>\n-\tldrd\tr6, r2, [r7, #244]\t@ 0xf4\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n+\tvadd.f64\td6, d6, d5\n+\tadd\tsl, r3\n+\tvadd.f64\td6, d6, d7\n+\tvstmia\tr8!, {d6}\n+\tbne.n\t196c <__gridxc_atom_MOD_atomxc+0x196c>\n+\tldrd\tr6, r2, [r7, #252]\t@ 0xfc\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n \tadd\tr6, r3\n-\tldr.w\tr3, [r7, #160]\t@ 0xa0\n+\tldr.w\tr3, [r7, #172]\t@ 0xac\n \tadd\tip, r3\n-\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tldr.w\tr3, [r7, #156]\t@ 0x9c\n \tcmp\tr1, r3\n-\tbne.n\t1940 <__gridxc_atom_MOD_atomxc+0x1940>\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n-\tldr.w\tr2, [r7, #256]\t@ 0x100\n-\tldr.w\tfp, [r7, #96]\t@ 0x60\n-\tvldr\td24, [r3]\n-\tvldr\td16, [r2]\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n-\tvmul.f64\td24, d16, d24\n-\tvldr\td17, [r2]\n+\tbne.n\t190c <__gridxc_atom_MOD_atomxc+0x190c>\n+\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tldr.w\tr2, [r7, #264]\t@ 0x108\n+\tvldr\td0, [r3, #-8]\n+\tvldr\td4, [r2]\n+\tldr.w\tr2, [r7, #268]\t@ 0x10c\n+\tvmul.f64\td0, d4, d0\n+\tvldr\td3, [r2]\n \tmovs\tr2, #1\n-\tvstr\td24, [r3]\n-\tvmul.f64\td23, d23, d17\n+\tvstr\td0, [r3, #-8]\n+\tvmul.f64\td11, d11, d3\n \tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tvstr\td23, [r3]\n-\tb.w\tcdc <__gridxc_atom_MOD_atomxc+0xcdc>\n-\tvmov.i64\td17, #0x0000000000000000\n+\tvstr\td11, [r3, #-8]\n+\tb.w\tce8 <__gridxc_atom_MOD_atomxc+0xce8>\n+\tvldr\td3, [pc, #60]\t@ 1a40 <__gridxc_atom_MOD_atomxc+0x1a40>\n \tmov\tr5, r4\n-\tstr.w\tr6, [r7, #288]\t@ 0x120\n-\tcbnz\tr5, 1a4c <__gridxc_atom_MOD_atomxc+0x1a4c>\n+\tstr.w\tr6, [r7, #300]\t@ 0x12c\n+\tcbnz\tr5, 1a14 <__gridxc_atom_MOD_atomxc+0x1a14>\n \tcmp\tr3, #0\n-\tble.w\t1c68 <__gridxc_atom_MOD_atomxc+0x1c68>\n+\tble.w\t1c38 <__gridxc_atom_MOD_atomxc+0x1c38>\n \tmovs\tr5, #1\n \tnegs\tr6, r5\n-\tvmov\ts15, r6\n+\tvmov\ts10, r6\n \tadds\tr5, #1\n-\tvcvt.f64.s32\td16, s15\n-\tcmp\tr3, r5\n-\tvdiv.f64\td18, d19, d16\n-\tvadd.f64\td17, d17, d18\n-\tbge.n\t1a42 <__gridxc_atom_MOD_atomxc+0x1a42>\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tvstr\td17, [r0, #40]\t@ 0x28\n-\tb.w\t7e0 <__gridxc_atom_MOD_atomxc+0x7e0>\n+\tvcvt.f64.s32\td5, s10\n+\tcmp\tr5, r3\n+\tvdiv.f64\td2, d7, d5\n+\tvadd.f64\td3, d3, d2\n+\tble.n\t1a0a <__gridxc_atom_MOD_atomxc+0x1a0a>\n+\tldr.w\tr6, [r7, #300]\t@ 0x12c\n+\tvstr\td3, [r1, #40]\t@ 0x28\n+\tb.w\t7f4 <__gridxc_atom_MOD_atomxc+0x7f4>\n \t.word\t0x00000000\n \t.word\t0x00100000\n-\t.word\t0x00000878\n+\t...\n+\t.word\t0x00000850\n R_ARM_REL32\t.LC38\n-\t.word\t0x00000868\n+\t.word\t0x00000840\n R_ARM_REL32\t.LC39\n-\t.word\t0x0000085a\n+\t.word\t0x00000832\n R_ARM_REL32\t.LC40\n-\t.word\t0x0000084c\n+\t.word\t0x00000824\n R_ARM_REL32\t.LC41\n-\t.word\t0x00000800\n+\t.word\t0x000007d6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000748\n+\t.word\t0x00000718\n R_ARM_REL32\t.LC42\n-\t.word\t0x000005aa\n+\t.word\t0x00000666\n R_ARM_REL32\t.bss\n-\t.word\t0x0000047e\n+\t.word\t0x00000586\n R_ARM_REL32\t.bss\n-\t.word\t0x000002f6\n+\t.word\t0x000002e4\n R_ARM_REL32\t.bss\n-\t.word\t0x000002b4\n+\t.word\t0x000002a0\n R_ARM_REL32\t.bss\n-\t.word\t0x000001f6\n+\t.word\t0x000001ea\n R_ARM_REL32\t.bss\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr2, [r7, #280]\t@ 0x118\n \tsub.w\tr3, r3, #712\t@ 0x2c8\n \tcmp\tr2, #2\n-\tvldr\td25, [r3]\n-\tvldr\td22, [r3, #8]\n-\tvldr\td21, [r3, #16]\n-\tvldr\td20, [r3, #24]\n-\tvmul.f64\td25, d25, d16\n-\tvldr\td19, [r3, #32]\n-\tvmul.f64\td22, d22, d16\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvmul.f64\td21, d21, d16\n-\tvmul.f64\td20, d20, d16\n-\tvmul.f64\td19, d19, d16\n-\tvstr\td25, [r3]\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td22, [r3, #8]\n-\tvstr\td21, [r3, #16]\n-\tvstr\td20, [r3, #24]\n-\tvstr\td19, [r3, #32]\n-\tvstr\td18, [r3, #40]\t@ 0x28\n-\tble.n\t1b48 <__gridxc_atom_MOD_atomxc+0x1b48>\n-\tvldr\td20, [r3, #48]\t@ 0x30\n+\tvldr\td8, [r3]\n+\tvldr\td7, [r3, #8]\n+\tvldr\td6, [r3, #16]\n+\tvldr\td5, [r3, #24]\n+\tvmul.f64\td8, d8, d4\n+\tvldr\td2, [r3, #32]\n+\tvmul.f64\td7, d7, d4\n+\tvldr\td1, [r3, #40]\t@ 0x28\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td2, d2, d4\n+\tvstr\td8, [r3]\n+\tvmul.f64\td1, d1, d4\n+\tvstr\td7, [r3, #8]\n+\tvstr\td6, [r3, #16]\n+\tvstr\td5, [r3, #24]\n+\tvstr\td2, [r3, #32]\n+\tvstr\td1, [r3, #40]\t@ 0x28\n+\tble.n\t1b18 <__gridxc_atom_MOD_atomxc+0x1b18>\n+\tvldr\td5, [r3, #48]\t@ 0x30\n \tcmp\tr2, #3\n-\tvldr\td19, [r3, #56]\t@ 0x38\n-\tvldr\td18, [r3, #64]\t@ 0x40\n-\tvmul.f64\td20, d20, d16\n-\tvmul.f64\td19, d19, d16\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td20, [r3, #48]\t@ 0x30\n-\tvstr\td19, [r3, #56]\t@ 0x38\n-\tvstr\td18, [r3, #64]\t@ 0x40\n-\tbeq.n\t1b48 <__gridxc_atom_MOD_atomxc+0x1b48>\n-\tvldr\td20, [r3, #72]\t@ 0x48\n-\tvldr\td19, [r3, #80]\t@ 0x50\n-\tvldr\td18, [r3, #88]\t@ 0x58\n-\tvmul.f64\td20, d20, d16\n-\tvmul.f64\td19, d19, d16\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td20, [r3, #72]\t@ 0x48\n-\tvstr\td19, [r3, #80]\t@ 0x50\n-\tvstr\td18, [r3, #88]\t@ 0x58\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tvldr\td6, [r3, #56]\t@ 0x38\n+\tvldr\td7, [r3, #64]\t@ 0x40\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td5, [r3, #48]\t@ 0x30\n+\tvstr\td6, [r3, #56]\t@ 0x38\n+\tvstr\td7, [r3, #64]\t@ 0x40\n+\tbeq.n\t1b18 <__gridxc_atom_MOD_atomxc+0x1b18>\n+\tvldr\td7, [r3, #72]\t@ 0x48\n+\tvldr\td6, [r3, #80]\t@ 0x50\n+\tvldr\td5, [r3, #88]\t@ 0x58\n+\tvmul.f64\td7, d7, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d4\n+\tvstr\td7, [r3, #72]\t@ 0x48\n+\tvstr\td6, [r3, #80]\t@ 0x50\n+\tvstr\td5, [r3, #88]\t@ 0x58\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr2, [r7, #280]\t@ 0x118\n \tsub.w\tr3, r3, #904\t@ 0x388\n \tcmp\tr2, #2\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #8]\n-\tvldr\td20, [r3, #16]\n-\tvldr\td19, [r3, #24]\n-\tvmul.f64\td22, d22, d17\n-\tvldr\td18, [r3, #32]\n-\tvmul.f64\td21, d21, d17\n-\tvldr\td16, [r3, #40]\t@ 0x28\n-\tvmul.f64\td20, d20, d17\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td22, [r3]\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td21, [r3, #8]\n-\tvstr\td20, [r3, #16]\n-\tvstr\td19, [r3, #24]\n-\tvstr\td18, [r3, #32]\n-\tvstr\td16, [r3, #40]\t@ 0x28\n-\tble.n\t1bec <__gridxc_atom_MOD_atomxc+0x1bec>\n-\tvldr\td19, [r3, #48]\t@ 0x30\n+\tvldr\td1, [r3]\n+\tvldr\td6, [r3, #8]\n+\tvldr\td7, [r3, #16]\n+\tvldr\td5, [r3, #24]\n+\tvmul.f64\td1, d1, d3\n+\tvldr\td4, [r3, #32]\n+\tvmul.f64\td6, d6, d3\n+\tvldr\td2, [r3, #40]\t@ 0x28\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d3\n+\tvstr\td1, [r3]\n+\tvmul.f64\td2, d2, d3\n+\tvstr\td6, [r3, #8]\n+\tvstr\td7, [r3, #16]\n+\tvstr\td5, [r3, #24]\n+\tvstr\td4, [r3, #32]\n+\tvstr\td2, [r3, #40]\t@ 0x28\n+\tble.n\t1bbc <__gridxc_atom_MOD_atomxc+0x1bbc>\n+\tvldr\td6, [r3, #48]\t@ 0x30\n \tcmp\tr2, #3\n-\tvldr\td18, [r3, #56]\t@ 0x38\n-\tvldr\td16, [r3, #64]\t@ 0x40\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td18, d18, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td19, [r3, #48]\t@ 0x30\n-\tvstr\td18, [r3, #56]\t@ 0x38\n-\tvstr\td16, [r3, #64]\t@ 0x40\n-\tbeq.n\t1bec <__gridxc_atom_MOD_atomxc+0x1bec>\n-\tvldr\td19, [r3, #72]\t@ 0x48\n-\tvldr\td18, [r3, #80]\t@ 0x50\n-\tvldr\td16, [r3, #88]\t@ 0x58\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td18, d18, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td19, [r3, #72]\t@ 0x48\n-\tvstr\td18, [r3, #80]\t@ 0x50\n-\tvstr\td16, [r3, #88]\t@ 0x58\n+\tvldr\td7, [r3, #56]\t@ 0x38\n+\tvldr\td5, [r3, #64]\t@ 0x40\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvstr\td6, [r3, #48]\t@ 0x30\n+\tvstr\td7, [r3, #56]\t@ 0x38\n+\tvstr\td5, [r3, #64]\t@ 0x40\n+\tbeq.n\t1bbc <__gridxc_atom_MOD_atomxc+0x1bbc>\n+\tvldr\td6, [r3, #72]\t@ 0x48\n+\tvldr\td7, [r3, #80]\t@ 0x50\n+\tvldr\td5, [r3, #88]\t@ 0x58\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvstr\td6, [r3, #72]\t@ 0x48\n+\tvstr\td7, [r3, #80]\t@ 0x50\n+\tvstr\td5, [r3, #88]\t@ 0x58\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #280]\t@ 0x118\n-\tb.w\td76 <__gridxc_atom_MOD_atomxc+0xd76>\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tsub.w\tr3, r3, #1376\t@ 0x560\n-\tvldr\td18, [r3]\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td18, [r3]\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tb.w\td82 <__gridxc_atom_MOD_atomxc+0xd82>\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r3, #1368\t@ 0x558\n+\tvldr\td7, [r3]\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td7, [r3]\n \tcmp\tr2, #0\n-\tbeq.w\td70 <__gridxc_atom_MOD_atomxc+0xd70>\n-\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tbeq.w\td7c <__gridxc_atom_MOD_atomxc+0xd7c>\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n \tsub.w\tr3, r2, #712\t@ 0x2c8\n-\tvldr\td19, [r3, #8]\n-\tvldr\td18, [r3, #16]\n-\tvldr\td20, [r3]\n-\tvmul.f64\td19, d19, d16\n-\tvmul.f64\td18, d18, d16\n-\tvmul.f64\td20, d20, d16\n-\tvldr\td16, [r3, #-176]\t@ 0xffffff50\n-\tvstr\td19, [r3, #8]\n-\tvstr\td18, [r3, #16]\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td19, [r3, #-192]\t@ 0xffffff40\n-\tvldr\td18, [r3, #-184]\t@ 0xffffff48\n-\tvstr\td20, [r3]\n-\tvmul.f64\td19, d19, d17\n-\tvstr\td16, [r3, #-176]\t@ 0xffffff50\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td19, [r3, #-192]\t@ 0xffffff40\n-\tvstr\td18, [r3, #-184]\t@ 0xffffff48\n-\tb.n\t1bec <__gridxc_atom_MOD_atomxc+0x1bec>\n-\tvldr\td19, [pc, #908]\t@ 1ff0 <__gridxc_atom_MOD_atomxc+0x1ff0>\n-\tb.n\t17de <__gridxc_atom_MOD_atomxc+0x17de>\n-\tstr.w\tr2, [r7, #252]\t@ 0xfc\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tvstr\td17, [r0, #40]\t@ 0x28\n-\tb.w\t7f2 <__gridxc_atom_MOD_atomxc+0x7f2>\n-\tvmul.f64\td20, d20, d21\n-\tvmul.f64\td19, d23, d19\n+\tvldr\td5, [r3]\n+\tvldr\td6, [r3, #8]\n+\tvldr\td7, [r3, #16]\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td5, [r3]\n+\tvstr\td6, [r3, #8]\n+\tvldr\td5, [r3, #-192]\t@ 0xffffff40\n+\tvldr\td6, [r3, #-184]\t@ 0xffffff48\n+\tvstr\td7, [r3, #16]\n+\tvldr\td7, [r3, #-176]\t@ 0xffffff50\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td5, [r3, #-192]\t@ 0xffffff40\n+\tvstr\td6, [r3, #-184]\t@ 0xffffff48\n+\tvstr\td7, [r3, #-176]\t@ 0xffffff50\n+\tb.n\t1bbc <__gridxc_atom_MOD_atomxc+0x1bbc>\n+\tvldr\td4, [pc, #892]\t@ 1fb0 <__gridxc_atom_MOD_atomxc+0x1fb0>\n+\tb.n\t17c0 <__gridxc_atom_MOD_atomxc+0x17c0>\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tstr.w\tr0, [r7, #284]\t@ 0x11c\n+\tvstr\td3, [r1, #40]\t@ 0x28\n+\tb.w\t806 <__gridxc_atom_MOD_atomxc+0x806>\n+\tvmul.f64\td3, d3, d1\n+\tvmul.f64\td4, d11, d4\n \tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tvstr\td20, [r2]\n-\tvstr\td19, [r3]\n-\tb.w\tec4 <__gridxc_atom_MOD_atomxc+0xec4>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tb.n\t185e <__gridxc_atom_MOD_atomxc+0x185e>\n-\tldr.w\tr3, [r7, #260]\t@ 0x104\n-\tcmp\tr8, r3\n-\tbgt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tlr, r4, #5\n-\tvldr\td17, [sl]\n-\tldr.w\tr2, [r7, #160]\t@ 0xa0\n-\tadd.w\tr6, r0, lr, lsl #3\n-\tldrd\tr3, r5, [r7, #264]\t@ 0x108\n-\tvldr\td18, [r6]\n-\tmul.w\tip, r4, r2\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tvdiv.f64\td16, d18, d17\n-\tadd\tr6, ip\n-\tmla\tr6, r5, r6, r3\n-\tvstr\td16, [r6]\n-\tbge.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr3, ip, r2\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tvldr\td17, [sl]\n-\tadd\tr6, r3\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tstr.w\tr5, [r7, #268]\t@ 0x10c\n-\tmla\tr6, r5, r6, r3\n-\tadds\tr3, r4, #6\n-\tadd.w\tip, r0, r3, lsl #3\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvldr\td18, [ip]\n-\tvdiv.f64\td16, d18, d17\n-\tvstr\td16, [r6]\n+\tvstr\td3, [r1, #-8]\n+\tvstr\td4, [r3, #-8]\n+\tb.w\teb4 <__gridxc_atom_MOD_atomxc+0xeb4>\n+\tvldr\td7, [pc, #852]\t@ 1fb8 <__gridxc_atom_MOD_atomxc+0x1fb8>\n+\tb.n\t1838 <__gridxc_atom_MOD_atomxc+0x1838>\n+\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tcmp\tr2, r0\n+\tbgt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr9, r4, #5\n+\tvldr\td5, [lr]\n+\tldr.w\tr2, [r7, #172]\t@ 0xac\n+\tadd.w\tr6, r1, r9, lsl #3\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tvldr\td2, [r6]\n+\tmul.w\tr8, r4, r2\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tvdiv.f64\td3, d2, d5\n+\tadd\tr6, r8\n+\tmla\tr6, r5, r6, r0\n+\tvstr\td3, [r6]\n+\tbge.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr0, r8, r2\n+\tstr.w\tr0, [r7, #224]\t@ 0xe0\n+\tldr.w\tr0, [r7, #224]\t@ 0xe0\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tvldr\td5, [lr]\n+\tadd\tr6, r0\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tstr.w\tr5, [r7, #292]\t@ 0x124\n+\tmla\tr6, r5, r6, r0\n+\tadds\tr0, r4, #6\n+\tadd.w\tr8, r1, r0, lsl #3\n+\tvldr\td2, [r8]\n+\tvdiv.f64\td3, d2, d5\n+\tvstr\td3, [r6]\n \tadds\tr6, r4, #2\n \tcmp\tr3, r6\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tldr.w\tr5, [r7, #208]\t@ 0xd0\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tadd\tr5, r2\n-\tstr.w\tr5, [r7, #208]\t@ 0xd0\n-\tadd\tr6, r5\n-\tvldr\td17, [sl]\n-\tldrd\tr3, r5, [r7, #264]\t@ 0x108\n-\tmla\tr6, r5, r6, r3\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tldr.w\tr0, [r7, #224]\t@ 0xe0\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tadd\tr0, r2\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tadd\tr6, r0\n+\tstr.w\tr0, [r7, #224]\t@ 0xe0\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tvldr\td5, [lr]\n+\tmla\tr6, r5, r6, r0\n \tadds\tr5, r4, #7\n-\tadd.w\tip, r0, r5, lsl #3\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvldr\td18, [ip]\n-\tvdiv.f64\td16, d18, d17\n-\tvstr\td16, [r6]\n+\tadd.w\tr8, r1, r5, lsl #3\n+\tvldr\td2, [r8]\n+\tvdiv.f64\td3, d2, d5\n+\tvstr\td3, [r6]\n \tadds\tr6, r4, #3\n-\tcmp\tr5, r6\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tip, r4, #8\n-\tldr.w\tr5, [r7, #208]\t@ 0xd0\n-\tstr.w\tip, [r7, #208]\t@ 0xd0\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvldr\td17, [sl]\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n+\tcmp\tr3, r6\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr8, r4, #8\n+\tldr.w\tr5, [r7, #224]\t@ 0xe0\n+\tstr.w\tr8, [r7, #224]\t@ 0xe0\n+\tadd.w\tr8, r1, r8, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n \tadd\tr5, r2\n-\tstr.w\tr5, [r7, #200]\t@ 0xc8\n-\tvldr\td18, [ip]\n+\tstr.w\tr5, [r7, #216]\t@ 0xd8\n+\tvldr\td2, [r8]\n \tadd\tr6, r5\n-\tldr.w\tr5, [r7, #268]\t@ 0x10c\n-\tvdiv.f64\td16, d18, d17\n-\tmla\tr6, r5, r6, r3\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvstr\td16, [r6]\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tvdiv.f64\td3, d2, d5\n+\tmla\tr6, r5, r6, r0\n+\tvstr\td3, [r6]\n \tadds\tr6, r4, #4\n \tcmp\tr3, r6\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tip, r4, #9\n-\tldr.w\tr3, [r7, #200]\t@ 0xc8\n-\tstr.w\tip, [r7, #200]\t@ 0xc8\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvldr\td17, [sl]\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tvldr\td18, [ip]\n-\tadd\tr6, r3\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tvdiv.f64\td16, d18, d17\n-\tmla\tr6, r5, r6, r3\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, lr\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tip, r4, #10\n-\tldr.w\tr5, [r7, #180]\t@ 0xb4\n-\tstr.w\tip, [r7, #180]\t@ 0xb4\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvldr\td17, [sl]\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr8, r4, #9\n+\tldr.w\tr0, [r7, #216]\t@ 0xd8\n+\tstr.w\tr8, [r7, #216]\t@ 0xd8\n+\tcmp\tr3, r9\n+\tadd.w\tr8, r1, r8, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tadd\tr0, r2\n+\tstr.w\tr0, [r7, #196]\t@ 0xc4\n+\tvldr\td2, [r8]\n+\tadd\tr6, r0\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tvdiv.f64\td3, d2, d5\n+\tmla\tr6, r5, r6, r0\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr8, r4, #10\n+\tldr.w\tr5, [r7, #196]\t@ 0xc4\n+\tstr.w\tr8, [r7, #196]\t@ 0xc4\n+\tadd.w\tr8, r1, r8, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n \tadd\tr5, r2\n-\tmov\tlr, r5\n-\tvldr\td18, [ip]\n+\tmov\tr9, r5\n+\tvldr\td2, [r8]\n \tadd\tr6, r5\n-\tldr.w\tr5, [r7, #268]\t@ 0x10c\n-\tvdiv.f64\td16, d18, d17\n-\tmla\tr6, r5, r6, r3\n-\tadds\tr3, r4, #6\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, r3\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr6, r0, r4, lsl #3\n-\tvldr\td17, [sl]\n-\tldrd\tr3, r5, [r7, #264]\t@ 0x108\n-\tadd.w\tip, lr, r2\n-\tvldr\td18, [r6, #88]\t@ 0x58\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tvdiv.f64\td16, d18, d17\n-\tadd\tr6, ip\n-\tmla\tr6, r5, r6, r3\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tvdiv.f64\td3, d2, d5\n+\tmla\tr6, r5, r6, r0\n+\tadds\tr0, r4, #6\n+\tcmp\tr3, r0\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr6, r1, r4, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tadd.w\tr8, r9, r2\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tvldr\td2, [r6, #88]\t@ 0x58\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tvdiv.f64\td3, d2, d5\n+\tadd\tr6, r8\n+\tmla\tr6, r5, r6, r0\n \tadds\tr5, r4, #7\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, r5\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr6, r0, r4, lsl #3\n-\tvldr\td17, [sl]\n-\tldr.w\tr5, [r7, #268]\t@ 0x10c\n-\tadd\tip, r2\n-\tvldr\td18, [r6, #96]\t@ 0x60\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tvdiv.f64\td16, d18, d17\n-\tadd\tr6, ip\n-\tmla\tr6, r5, r6, r3\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, r3\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr3, ip, r2\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tvldr\td17, [sl]\n-\tsub.w\tlr, r3, #992\t@ 0x3e0\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tadd.w\tip, lr, r4, lsl #3\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tadd\tr6, r3\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tvldr\td18, [ip, #104]\t@ 0x68\n-\tvdiv.f64\td16, d18, d17\n-\tmla\tr6, r5, r6, r3\n-\tldr.w\tr5, [r7, #200]\t@ 0xc8\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, r5\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr6, lr, r4, lsl #3\n-\tvldr\td17, [sl]\n-\tldr.w\tr5, [r7, #208]\t@ 0xd0\n-\tvldr\td18, [r6, #112]\t@ 0x70\n+\tcmp\tr3, r5\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr6, r1, r4, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tadd\tr8, r2\n+\tvldr\td2, [r6, #96]\t@ 0x60\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tvdiv.f64\td3, d2, d5\n+\tadd\tr6, r8\n+\tmla\tr6, r5, r6, r0\n+\tldr.w\tr0, [r7, #224]\t@ 0xe0\n+\tcmp\tr3, r0\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr0, r8, r2\n+\tstr.w\tr0, [r7, #224]\t@ 0xe0\n+\tldr\tr0, [r7, #96]\t@ 0x60\n+\tvldr\td5, [lr]\n+\tsub.w\tr9, r0, #992\t@ 0x3e0\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tadd.w\tr8, r9, r4, lsl #3\n+\tldr.w\tr0, [r7, #224]\t@ 0xe0\n+\tadd\tr6, r0\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tvldr\td2, [r8, #104]\t@ 0x68\n+\tvdiv.f64\td3, d2, d5\n+\tmla\tr6, r5, r6, r0\n+\tldr.w\tr5, [r7, #216]\t@ 0xd8\n+\tcmp\tr3, r5\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr6, r9, r4, lsl #3\n+\tvldr\td5, [lr]\n+\tldr.w\tr5, [r7, #224]\t@ 0xe0\n+\tvldr\td2, [r6, #112]\t@ 0x70\n \tadd\tr5, r2\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tmov\tip, r5\n-\tvdiv.f64\td16, d18, d17\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tmov\tr8, r5\n+\tvdiv.f64\td3, d2, d5\n \tadd\tr6, r5\n-\tldr.w\tr5, [r7, #268]\t@ 0x10c\n-\tmla\tr6, r5, r6, r3\n-\tldr.w\tr5, [r7, #180]\t@ 0xb4\n-\tvstr\td16, [r6]\n-\tldr.w\tr6, [r7, #288]\t@ 0x120\n-\tcmp\tr6, r5\n-\tblt.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tadd.w\tr6, lr, r4, lsl #3\n-\tvldr\td17, [sl]\n-\tadd.w\tr5, ip, r2\n-\tldr.w\tr2, [r7, #268]\t@ 0x10c\n-\tvldr\td18, [r6, #120]\t@ 0x78\n-\tldr.w\tr6, [r7, #284]\t@ 0x11c\n-\tvdiv.f64\td16, d18, d17\n+\tldr.w\tr5, [r7, #292]\t@ 0x124\n+\tmla\tr6, r5, r6, r0\n+\tldr.w\tr5, [r7, #196]\t@ 0xc4\n+\tcmp\tr3, r5\n+\tvstr\td3, [r6]\n+\tblt.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tadd.w\tr6, r9, r4, lsl #3\n+\tvldr\td5, [lr]\n+\tadd.w\tr5, r8, r2\n+\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tvldr\td2, [r6, #120]\t@ 0x78\n+\tldr.w\tr6, [r7, #296]\t@ 0x128\n+\tvdiv.f64\td3, d2, d5\n \tadd\tr5, r6\n-\tmla\tr5, r2, r5, r3\n-\tvstr\td16, [r5]\n-\tb.w\t99c <__gridxc_atom_MOD_atomxc+0x99c>\n-\tldr\tr3, [r7, #112]\t@ 0x70\n-\tmov.w\tlr, #4294967295\t@ 0xffffffff\n-\tldr.w\tr2, [r7, #236]\t@ 0xec\n-\tstr.w\tsl, [r7, #4]\n-\tadds\tr5, r3, r2\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr2, [r7, #160]\t@ 0xa0\n-\tldr.w\tsl, [r7, #32]\n-\tstr\tr0, [r7, #0]\n-\tmla\tr6, r2, r4, r3\n-\tldrd\tr3, r2, [r7, #264]\t@ 0x108\n-\tmla\tr3, r2, r6, r3\n-\tldr\tr2, [r7, #88]\t@ 0x58\n-\tstr.w\tr3, [r7, #176]\t@ 0xb0\n-\tldr\tr3, [r7, #120]\t@ 0x78\n-\tadd.w\tip, r2, r5\n-\tldr\tr2, [r7, #28]\n-\tadds\tr6, r3, r5\n-\tldr\tr3, [r7, #116]\t@ 0x74\n-\tadd\tr5, r2\n-\tmul.w\tr6, r3, r6\n-\tmul.w\tr5, r3, r5\n-\tmul.w\tip, r3, ip\n-\tsub.w\tr3, ip, r6\n-\tstr.w\tr3, [r7, #200]\t@ 0xc8\n-\tsubs\tr3, r5, r6\n-\tldr.w\tr6, [r7, #224]\t@ 0xe0\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tmov.w\tip, #1\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tadds\tr5, r3, r6\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r3, r8, lsl #3\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tstr.w\tr1, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r7, #200]\t@ 0xc8\n-\tvstr\td20, [r6]\n+\tmla\tr5, r2, r5, r0\n+\tvstr\td3, [r5]\n+\tb.w\t9a0 <__gridxc_atom_MOD_atomxc+0x9a0>\n+\tldr\tr2, [r7, #116]\t@ 0x74\n+\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tldr.w\tr0, [r7, #252]\t@ 0xfc\n+\tstrd\tlr, ip, [r7, #8]\n+\tadds\tr5, r2, r0\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr0, [r7, #172]\t@ 0xac\n+\tstr\tr1, [r7, #4]\n+\tldr.w\tlr, [r7, #32]\n+\tldr\tr1, [r7, #84]\t@ 0x54\n+\tmla\tr6, r0, r4, r2\n+\tldr.w\tr0, [r7, #292]\t@ 0x124\n+\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tmla\tr2, r0, r6, r2\n+\tldr\tr0, [r7, #44]\t@ 0x2c\n+\tstr.w\tr2, [r7, #192]\t@ 0xc0\n+\tldr\tr2, [r7, #124]\t@ 0x7c\n+\tadd.w\tr8, r0, r5\n+\tldr\tr0, [r7, #28]\n+\tadds\tr6, r2, r5\n+\tldr\tr2, [r7, #120]\t@ 0x78\n+\tadd\tr5, r0\n+\tldr.w\tr0, [r7, #288]\t@ 0x120\n+\tmul.w\tr6, r2, r6\n+\tmul.w\tr5, r2, r5\n+\tmul.w\tr8, r2, r8\n+\tsub.w\tr2, r8, r6\n+\tstr.w\tr2, [r7, #216]\t@ 0xd8\n+\tsubs\tr2, r5, r6\n+\tldr.w\tr6, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #224]\t@ 0xe0\n+\tmov.w\tr8, #1\n+\tldr\tr2, [r7, #40]\t@ 0x28\n+\tadds\tr5, r2, r6\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tadd.w\tr2, r2, r0, lsl #3\n+\tstr.w\tr2, [r7, #196]\t@ 0xc4\n+\tldr.w\tr2, [r7, #216]\t@ 0xd8\n+\tvstr\td6, [r6]\n \tadd\tr2, r6\n-\tvstr\td20, [r2]\n-\tldr.w\tr2, [r7, #208]\t@ 0xd0\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tvstr\td6, [r2]\n+\tldr.w\tr2, [r7, #224]\t@ 0xe0\n \tadd\tr2, r6\n-\tvstr\td20, [r2]\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n-\tcmp\tr8, r2\n-\tbgt.n\t1fd2 <__gridxc_atom_MOD_atomxc+0x1fd2>\n-\tldr.w\tr2, [r7, #180]\t@ 0xb4\n-\tldr.w\tr1, [r7, #176]\t@ 0xb0\n-\tvldr\td16, [r5]\n-\tadd.w\tr0, r2, lr, lsl #3\n+\tvstr\td6, [r2]\n+\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tcmp\tr2, r0\n+\tbgt.n\t1f92 <__gridxc_atom_MOD_atomxc+0x1f92>\n+\tldr.w\tr2, [r7, #196]\t@ 0xc4\n+\tldr.w\tr0, [r7, #192]\t@ 0xc0\n+\tvldr\td5, [r5]\n+\tadd.w\tip, r2, r9, lsl #3\n \tmov\tr2, r4\n-\tvldr\td18, [r1]\n+\tvldr\td3, [r0]\n \tadds\tr2, #1\n-\tvldmia\tr0!, {d17}\n-\tadd\tr1, fp\n+\tvldmia\tip!, {d2}\n+\tadd\tr0, fp\n \tcmp\tr3, r2\n-\tvfma.f64\td16, d18, d17\n-\tvstr\td16, [r5]\n-\tbge.n\t1fba <__gridxc_atom_MOD_atomxc+0x1fba>\n-\tldr\tr2, [r7, #100]\t@ 0x64\n-\tadd.w\tip, ip, #1\n-\tadd\tr6, sl\n-\tadd\tr5, sl\n-\tadd\tlr, r2\n-\tcmp\tr9, ip\n-\tbge.n\t1f88 <__gridxc_atom_MOD_atomxc+0x1f88>\n-\tldr.w\tr1, [r7, #288]\t@ 0x120\n-\tldrd\tr0, sl, [r7]\n+\tvmla.f64\td5, d2, d3\n+\tvstr\td5, [r5]\n+\tbge.n\t1f7a <__gridxc_atom_MOD_atomxc+0x1f7a>\n+\tadd.w\tr8, r8, #1\n+\tadd\tr6, lr\n+\tadd\tr9, r1\n+\tadd\tr5, lr\n+\tcmp\tsl, r8\n+\tbge.n\t1f44 <__gridxc_atom_MOD_atomxc+0x1f44>\n+\tldrd\tlr, ip, [r7, #8]\n+\tldr\tr1, [r7, #4]\n \tb.w\t9d8 <__gridxc_atom_MOD_atomxc+0x9d8>\n \tnop\n+\tnop.w\n \t.word\t0x00000000\n \t.word\t0x00100000\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tmovs\tr6, #8\n-\tsub.w\tr3, r0, #1240\t@ 0x4d8\n-\tsubw\tr2, r0, #1228\t@ 0x4cc\n+\t...\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tadd.w\tr0, r7, #508\t@ 0x1fc\n+\tsubw\tr3, r2, #1236\t@ 0x4d4\n+\tsub.w\tr2, r2, #1224\t@ 0x4c8\n+\tstr.w\tr9, [r3, #20]\n+\tmov.w\tr9, #8\n \tstr\tr4, [r3, #32]\n-\tmovs\tr4, #1\n-\tstrd\tr8, r5, [r3]\n-\tvstr\td9, [r2]\n-\tsubw\tr2, r0, #1220\t@ 0x4c4\n-\tadd.w\tr0, r7, #504\t@ 0x1f8\n-\tvst1.32\t{d8}, [r2]\n+\tmovs\tr4, #0\n+\tstr\tr6, [r3, #24]\n+\tstrd\tr5, r8, [r3]\n+\tmov.w\tr8, #1\n+\tstrd\tr4, r4, [r2]\n \tmovw\tr2, #769\t@ 0x301\n-\tstr\tr6, [r3, #8]\n-\tstr\tr4, [r3, #28]\n+\tstr.w\tr8, [r3, #28]\n \tstrh\tr2, [r3, #16]\n+\tstr.w\tr9, [r3, #8]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [pc, #956]\t@ (23f0 <__gridxc_atom_MOD_atomxc+0x23f0>)\n-\tmov\tr5, r0\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n+\tldr\tr2, [pc, #928]\t@ (23a0 <__gridxc_atom_MOD_atomxc+0x23a0>)\n+\tmov\tr6, r0\n+\tldr.w\tr0, [r7, #296]\t@ 0x128\n \tadd\tr2, pc\n-\tsub.w\tr3, r0, #1200\t@ 0x4b0\n-\tadd.w\tr1, r2, #188\t@ 0xbc\n-\tldr.w\tr0, [r2, #216]\t@ 0xd8\n-\tvld1.32\t{d16}, [r1]\n-\tstr\tr4, [r3, #28]\n-\tstr\tr4, [r3, #40]\t@ 0x28\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tsub.w\tr3, r3, #1200\t@ 0x4b0\n \tldr.w\tr1, [r2, #220]\t@ 0xdc\n-\tldr.w\tr4, [r7, #284]\t@ 0x11c\n-\tstr\tr6, [r3, #8]\n-\tsubs\tr1, r4, r1\n+\tsubs\tr1, r0, r1\n+\tldr.w\tr0, [r2, #216]\t@ 0xd8\n+\tstr.w\tr8, [r3, #28]\n+\tstr.w\tr8, [r3, #40]\t@ 0x28\n+\tstr.w\tr9, [r3, #8]\n \tmul.w\tr1, r0, r1\n-\tvmov.32\tr0, d16[1]\n-\tnegs\tr4, r0\n+\tldr.w\tr0, [r2, #192]\t@ 0xc0\n+\tstr\tr0, [r3, #24]\n+\trsb\tip, r0, #0\n+\tldr.w\tr0, [r7, #300]\t@ 0x12c\n+\tsubw\tr0, r0, #1188\t@ 0x4a4\n+\tstrd\tr4, r4, [r0]\n \tldr.w\tr0, [r2, #196]\t@ 0xc4\n-\trsb\tip, r0, #1\n+\tsub.w\tr4, r8, r0\n \tldr.w\tr0, [r2, #208]\t@ 0xd0\n-\trsb\tlr, r0, #1\n+\tsub.w\tlr, r8, r0\n \tldr.w\tr0, [r2, #168]\t@ 0xa8\n-\tadd.w\tr6, r0, r1, lsl #3\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tstr\tr6, [r3, #0]\n-\tsubw\tr1, r0, #1188\t@ 0x4a4\n-\tvstr\td9, [r1]\n-\tsubw\tr1, r0, #1180\t@ 0x49c\n-\tldr.w\tr0, [r7, #156]\t@ 0x9c\n-\tvst1.32\t{d16}, [r1]\n+\tadd.w\tr8, r0, r1, lsl #3\n \tldr.w\tr1, [r2, #204]\t@ 0xcc\n \tstr\tr1, [r3, #36]\t@ 0x24\n-\tsubs\tr4, r4, r1\n+\tsub.w\tr1, ip, r1\n+\tstr\tr1, [r3, #4]\n \tldr.w\tr1, [r2, #200]\t@ 0xc8\n-\tldr.w\tr2, [r2, #212]\t@ 0xd4\n-\tadd\tr1, ip\n-\tstr\tr4, [r3, #4]\n-\tadd\tr2, lr\n-\tstr\tr1, [r3, #32]\n-\tstr\tr2, [r3, #44]\t@ 0x2c\n+\tstr.w\tr8, [r3]\n+\tadd\tr4, r1\n+\tldr.w\tr1, [r2, #212]\t@ 0xd4\n+\tldr.w\tr2, [r2, #188]\t@ 0xbc\n+\tadd\tr1, lr\n+\tstr\tr4, [r3, #32]\n+\tstr\tr1, [r3, #44]\t@ 0x2c\n+\tstr\tr2, [r3, #20]\n \tmovw\tr2, #770\t@ 0x302\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n \tstrh\tr2, [r3, #16]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #228]\t@ 0xe4\n+\tldr.w\tr3, [r7, #236]\t@ 0xec\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr4, r0\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr.w\tr3, [r7, #244]\t@ 0xf4\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tldr\tr3, [r7, #124]\t@ 0x7c\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr\tr3, [r7, #120]\t@ 0x78\n \tstrd\tr0, r3, [sp]\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tadd.w\tr3, r7, #840\t@ 0x348\n \tstr\tr3, [sp, #24]\n \tadd.w\tr3, r7, #1032\t@ 0x408\n \tstr\tr3, [sp, #20]\n-\tmov\tr3, r5\n-\tldr.w\tr2, [r7, #204]\t@ 0xcc\n+\tmov\tr3, r6\n+\tldr.w\tr2, [r7, #220]\t@ 0xdc\n \tldr.w\tr1, [r7, #128]\t@ 0x80\n-\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tldr.w\tr0, [r7, #248]\t@ 0xf8\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n-\tcmp\tr5, r8\n-\tbeq.n\t2114 <__gridxc_atom_MOD_atomxc+0x2114>\n-\tmov\tr0, r5\n+\tcmp\tr6, r5\n+\tbeq.n\t20e0 <__gridxc_atom_MOD_atomxc+0x20e0>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr6, r4\n+\tcmp\tr8, r4\n \tbeq.w\t1364 <__gridxc_atom_MOD_atomxc+0x1364>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tb.w\t1364 <__gridxc_atom_MOD_atomxc+0x1364>\n-\tldr\tr6, [r7, #32]\n-\tb.w\tf6e <__gridxc_atom_MOD_atomxc+0xf6e>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvmov.f64\td18, d16\n-\tb.w\t95e <__gridxc_atom_MOD_atomxc+0x95e>\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tsub.w\tr3, r3, #1432\t@ 0x598\n-\tldr\tr2, [r3, #0]\n-\tcmp\tr2, #1\n-\tbne.w\t40a <__gridxc_atom_MOD_atomxc+0x40a>\n-\tmov.w\tr2, #532\t@ 0x214\n-\tstr\tr2, [r3, #0]\n-\tb.w\t40a <__gridxc_atom_MOD_atomxc+0x40a>\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n+\tvldr\td5, [pc, #660]\t@ 2388 <__gridxc_atom_MOD_atomxc+0x2388>\n+\tvmov.f64\td2, d5\n+\tb.w\t960 <__gridxc_atom_MOD_atomxc+0x960>\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n \tcmp\tr3, #0\n-\tble.w\t2324 <__gridxc_atom_MOD_atomxc+0x2324>\n-\tldr\tr0, [r7, #44]\t@ 0x2c\n+\tble.w\t22cc <__gridxc_atom_MOD_atomxc+0x22cc>\n+\tldr\tr0, [r7, #56]\t@ 0x38\n \tadds\tr3, #1\n-\tldr\tr2, [r7, #100]\t@ 0x64\n+\tldr\tr2, [r7, #84]\t@ 0x54\n \tmov.w\tr8, #0\n-\tldr\tr5, [r7, #64]\t@ 0x40\n+\tldr\tr5, [r7, #72]\t@ 0x48\n \tadd.w\tlr, r3, r0\n-\tldr\tr4, [r7, #68]\t@ 0x44\n+\tldr\tr4, [r7, #76]\t@ 0x4c\n \tmov.w\tr9, #0\n \tadd.w\tr1, r0, r2, lsl #1\n-\tldr.w\tsl, [r7, #276]\t@ 0x114\n+\tldr.w\tr6, [r7, #280]\t@ 0x118\n \tadds\tr1, #1\n-\tvldr\td21, [pc, #612]\t@ 23e0 <__gridxc_atom_MOD_atomxc+0x23e0>\n+\tvldr\td1, [pc, #616]\t@ 2390 <__gridxc_atom_MOD_atomxc+0x2390>\n \tnegs\tr0, r2\n \tmov.w\tip, r2, lsl #3\n \tadd.w\tr1, r5, r1, lsl #3\n-\tcmp.w\tsl, #0\n-\tble.n\t21aa <__gridxc_atom_MOD_atomxc+0x21aa>\n-\tvldr\td20, [r5]\n-\tcmp.w\tsl, #1\n-\tble.n\t21a0 <__gridxc_atom_MOD_atomxc+0x21a0>\n-\tvldr\td22, [r1]\n-\tvadd.f64\td20, d20, d22\n-\tvcmpe.f64\td20, d21\n+\tcmp\tr6, #0\n+\tble.n\t2152 <__gridxc_atom_MOD_atomxc+0x2152>\n+\tvldr\td2, [r5]\n+\tcmp\tr6, #1\n+\tble.n\t2148 <__gridxc_atom_MOD_atomxc+0x2148>\n+\tvldr\td3, [r1]\n+\tvadd.f64\td2, d2, d3\n+\tvcmpe.f64\td2, d1\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t21ea <__gridxc_atom_MOD_atomxc+0x21ea>\n+\tbmi.n\t2192 <__gridxc_atom_MOD_atomxc+0x2192>\n \tadds\tr0, #1\n \tadds\tr4, #8\n \tadds\tr1, #8\n \tadds\tr5, #8\n-\tcmp\tlr, r0\n-\tbne.n\t2188 <__gridxc_atom_MOD_atomxc+0x2188>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvstr\td19, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvstr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvstr\td17, [r3]\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tcmp\tr0, lr\n+\tbne.n\t2134 <__gridxc_atom_MOD_atomxc+0x2134>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvstr\td7, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvstr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvstr\td6, [r3]\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tcmp\tr3, #0\n-\tble.w\t2344 <__gridxc_atom_MOD_atomxc+0x2344>\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tble.w\t22ec <__gridxc_atom_MOD_atomxc+0x22ec>\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n \tadd.w\tip, r3, #8\n-\tb.w\t1076 <__gridxc_atom_MOD_atomxc+0x1076>\n+\tb.w\t105c <__gridxc_atom_MOD_atomxc+0x105c>\n \tmov\tr2, r4\n \tmovs\tr3, #0\n \tadds\tr3, #1\n \tstrd\tr8, r9, [r2]\n-\tcmp\tsl, r3\n+\tcmp\tr6, r3\n \tadd\tr2, ip\n-\tbne.n\t21ee <__gridxc_atom_MOD_atomxc+0x21ee>\n-\tb.n\t21aa <__gridxc_atom_MOD_atomxc+0x21aa>\n-\tmovs\tr0, #1\n+\tbne.n\t2196 <__gridxc_atom_MOD_atomxc+0x2196>\n+\tb.n\t2152 <__gridxc_atom_MOD_atomxc+0x2152>\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #80]\t@ 0x50\n+\tstr\tr0, [r7, #92]\t@ 0x5c\n \tcmp\tr0, #0\n-\tbeq.w\t35c0 <__gridxc_atom_MOD_atomxc+0x35c0>\n-\tmovs\tr0, #1\n+\tbeq.w\t3516 <__gridxc_atom_MOD_atomxc+0x3516>\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n+\tstr\tr0, [r7, #88]\t@ 0x58\n \tcmp\tr0, #0\n-\tbeq.w\t35b0 <__gridxc_atom_MOD_atomxc+0x35b0>\n-\tmovs\tr0, #1\n+\tbeq.w\t3526 <__gridxc_atom_MOD_atomxc+0x3526>\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r7, #72]\t@ 0x48\n+\tstr\tr0, [r7, #80]\t@ 0x50\n \tcmp\tr0, #0\n-\tbeq.w\t3560 <__gridxc_atom_MOD_atomxc+0x3560>\n-\tstr\tr4, [sp, #20]\n-\tmovs\tr4, #0\n-\tldr\tr2, [pc, #456]\t@ (23f4 <__gridxc_atom_MOD_atomxc+0x23f4>)\n-\tldr.w\tr5, [r7, #232]\t@ 0xe8\n-\tstrd\tr4, r4, [sp, #12]\n+\tbeq.w\t3536 <__gridxc_atom_MOD_atomxc+0x3536>\n+\tstrd\tr6, r5, [sp, #20]\n+\tstrd\tr5, r5, [sp, #12]\n+\tstr\tr5, [sp, #8]\n+\tldr\tr2, [pc, #456]\t@ (23a4 <__gridxc_atom_MOD_atomxc+0x23a4>)\n+\tldr.w\tr4, [r7, #256]\t@ 0x100\n+\tstr\tr4, [sp, #0]\n \tadd\tr2, pc\n-\tstr\tr5, [sp, #0]\n+\tldr\tr3, [pc, #452]\t@ (23a8 <__gridxc_atom_MOD_atomxc+0x23a8>)\n \tstr\tr2, [sp, #4]\n-\tstr\tr4, [sp, #24]\n-\tstr\tr4, [sp, #8]\n-\tldr\tr3, [pc, #440]\t@ (23f8 <__gridxc_atom_MOD_atomxc+0x23f8>)\n-\tldr.w\tsl, [r7, #204]\t@ 0xcc\n-\tldr\tr0, [pc, #436]\t@ (23fc <__gridxc_atom_MOD_atomxc+0x23fc>)\n+\tldr.w\tfp, [r7, #220]\t@ 0xdc\n \tadd\tr3, pc\n+\tldr\tr0, [pc, #444]\t@ (23ac <__gridxc_atom_MOD_atomxc+0x23ac>)\n \tmov\tr1, r3\n-\tmov\tr2, sl\n-\tadd\tr0, pc\n+\tmov\tr2, fp\n \tmov\tr6, r3\n+\tadd\tr0, pc\n \tmov\tr8, r0\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr3, [pc, #424]\t@ (2400 <__gridxc_atom_MOD_atomxc+0x2400>)\n+\tldr\tr3, [pc, #432]\t@ (23b0 <__gridxc_atom_MOD_atomxc+0x23b0>)\n \tadds\tr2, r6, #4\n \tadd.w\tr1, r6, #8\n \tadd.w\tr0, r8, #48\t@ 0x30\n \tadd\tr3, pc\n-\tstr\tr4, [sp, #24]\n-\tstrd\tr4, r4, [sp, #12]\n-\tstr\tr4, [sp, #8]\n-\tstr.w\tr5, [r7, #232]\t@ 0xe8\n-\tstr\tr5, [sp, #0]\n-\tmovs\tr5, #11\n+\tstr\tr5, [sp, #24]\n+\tstrd\tr5, r5, [sp, #12]\n+\tstr\tr5, [sp, #8]\n+\tstr.w\tr4, [r7, #256]\t@ 0x100\n+\tstr\tr4, [sp, #0]\n+\tmovs\tr4, #11\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #12\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r6\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tstrd\tr4, r4, [sp, #4]\n-\tstr\tr5, [sp, #12]\n+\tstrd\tr5, r5, [sp, #4]\n+\tstr\tr4, [sp, #12]\n \tmov\tr1, r6\n-\tstr\tr4, [sp, #16]\n+\tstr\tr5, [sp, #16]\n \tadd.w\tr0, r8, #96\t@ 0x60\n-\tstr\tr4, [sp, #0]\n-\tldr.w\tr9, [r7, #232]\t@ 0xe8\n-\tldr\tr3, [pc, #364]\t@ (2404 <__gridxc_atom_MOD_atomxc+0x2404>)\n+\tstr\tr5, [sp, #0]\n+\tldr.w\tr9, [r7, #256]\t@ 0x100\n+\tldr\tr3, [pc, #376]\t@ (23b4 <__gridxc_atom_MOD_atomxc+0x23b4>)\n \tmov\tr2, r9\n \tadd\tr3, pc\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr\tr3, [pc, #360]\t@ (2408 <__gridxc_atom_MOD_atomxc+0x2408>)\n+\tldr\tr3, [pc, #368]\t@ (23b8 <__gridxc_atom_MOD_atomxc+0x23b8>)\n \tmov\tr2, r9\n \tmov\tr1, r6\n \tadd\tr3, pc\n \tadd.w\tr0, r8, #132\t@ 0x84\n-\tstrd\tr5, r4, [sp, #12]\n-\tstrd\tr4, r4, [sp, #4]\n-\tstr\tr4, [sp, #0]\n+\tstrd\tr4, r5, [sp, #12]\n+\tstrd\tr5, r5, [sp, #4]\n+\tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr\tr3, [pc, #336]\t@ (240c <__gridxc_atom_MOD_atomxc+0x240c>)\n+\tldr\tr3, [pc, #348]\t@ (23bc <__gridxc_atom_MOD_atomxc+0x23bc>)\n \tadd.w\tr0, r8, #168\t@ 0xa8\n \tadd.w\tr2, r6, #12\n \tadd\tr3, pc\n \tmov\tr1, r6\n \tstr\tr3, [sp, #12]\n \tmovs\tr3, #9\n-\tstr\tr4, [sp, #32]\n+\tstr\tr5, [sp, #32]\n \tstr\tr3, [sp, #28]\n \tmov\tr3, r6\n-\tstrd\tr4, r4, [sp, #20]\n-\tstr\tr4, [sp, #16]\n+\tstrd\tr5, r5, [sp, #20]\n+\tstr\tr5, [sp, #16]\n \tstrd\tr6, r9, [sp, #4]\n-\tstr.w\tsl, [sp]\n+\tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr.w\tr1, [r7, #140]\t@ 0x8c\n-\tldr.w\tr5, [r7, #228]\t@ 0xe4\n+\tldr.w\tr1, [r7, #144]\t@ 0x90\n+\tldr.w\tr4, [r7, #240]\t@ 0xf0\n \tadd.w\tr2, r7, #400\t@ 0x190\n \tsubs\tr3, r1, #1\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tvldr\td16, [pc, #244]\t@ 23e8 <__gridxc_atom_MOD_atomxc+0x23e8>\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tvldr\td7, [pc, #252]\t@ 2398 <__gridxc_atom_MOD_atomxc+0x2398>\n \tadd.w\tr0, r7, #368\t@ 0x170\n-\tadd.w\tr3, r5, r3, lsl #3\n-\tcmp\tr1, r4\n-\tstr\tr2, [r7, #108]\t@ 0x6c\n-\tstr.w\tr0, [r7, #212]\t@ 0xd4\n+\tadd.w\tr3, r4, r3, lsl #3\n+\tcmp\tr1, #0\n+\tstr.w\tr2, [r7, #180]\t@ 0xb4\n+\tstr.w\tr0, [r7, #184]\t@ 0xb8\n \tvldr\td8, [r3]\n-\tvdiv.f64\td10, d16, d8\n-\tvstr\td8, [r7, #360]\t@ 0x168\n-\tvstr\td10, [r7, #352]\t@ 0x160\n-\tble.w\t3602 <__gridxc_atom_MOD_atomxc+0x3602>\n-\tmov\tr6, r4\n-\tstr.w\tr4, [r7, #220]\t@ 0xdc\n-\tb.w\t5c4 <__gridxc_atom_MOD_atomxc+0x5c4>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvstr\td19, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvstr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvstr\td17, [r3]\n-\tldr\tr5, [pc, #200]\t@ (2410 <__gridxc_atom_MOD_atomxc+0x2410>)\n+\tvdiv.f64\td9, d7, d8\n+\tvstr\td8, [r7, #368]\t@ 0x170\n+\tvstr\td9, [r7, #360]\t@ 0x168\n+\tble.w\t3546 <__gridxc_atom_MOD_atomxc+0x3546>\n+\tstr.w\tr5, [r7, #244]\t@ 0xf4\n+\tstr\tr5, [r7, #100]\t@ 0x64\n+\tb.w\t59e <__gridxc_atom_MOD_atomxc+0x59e>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvstr\td7, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvstr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvstr\td6, [r3]\n+\tldr\tr5, [pc, #208]\t@ (23c0 <__gridxc_atom_MOD_atomxc+0x23c0>)\n \tmovs\tr4, #0\n-\tldr\tr1, [pc, #200]\t@ (2414 <__gridxc_atom_MOD_atomxc+0x2414>)\n+\tldr\tr1, [pc, #208]\t@ (23c4 <__gridxc_atom_MOD_atomxc+0x23c4>)\n \tmov\tr2, r4\n \tadd\tr5, pc\n \tmovs\tr3, #9\n \tadd.w\tr0, r5, #576\t@ 0x240\n \tadd\tr1, pc\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #184]\t@ (2418 <__gridxc_atom_MOD_atomxc+0x2418>)\n+\tldr\tr1, [pc, #192]\t@ (23c8 <__gridxc_atom_MOD_atomxc+0x23c8>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #528\t@ 0x210\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #172]\t@ (241c <__gridxc_atom_MOD_atomxc+0x241c>)\n+\tldr\tr1, [pc, #180]\t@ (23cc <__gridxc_atom_MOD_atomxc+0x23cc>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #480\t@ 0x1e0\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #156]\t@ (2420 <__gridxc_atom_MOD_atomxc+0x2420>)\n+\tldr\tr1, [pc, #164]\t@ (23d0 <__gridxc_atom_MOD_atomxc+0x23d0>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #432\t@ 0x1b0\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #144]\t@ (2424 <__gridxc_atom_MOD_atomxc+0x2424>)\n+\tldr\tr1, [pc, #152]\t@ (23d4 <__gridxc_atom_MOD_atomxc+0x23d4>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #384\t@ 0x180\n \tadd\tr1, pc\n \tmovs\tr3, #10\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #128]\t@ (2428 <__gridxc_atom_MOD_atomxc+0x2428>)\n+\tldr\tr1, [pc, #136]\t@ (23d8 <__gridxc_atom_MOD_atomxc+0x23d8>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #336\t@ 0x150\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #116]\t@ (242c <__gridxc_atom_MOD_atomxc+0x242c>)\n+\tldr\tr1, [pc, #124]\t@ (23dc <__gridxc_atom_MOD_atomxc+0x23dc>)\n \tmov\tr2, r4\n \tadd.w\tr0, r5, #276\t@ 0x114\n \tadd\tr1, pc\n \tmovs\tr3, #12\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d3\n-\tldr\tr1, [pc, #100]\t@ (2430 <__gridxc_atom_MOD_atomxc+0x2430>)\n+\tldr\tr1, [pc, #108]\t@ (23e0 <__gridxc_atom_MOD_atomxc+0x23e0>)\n \tmovs\tr3, #11\n \tmov\tr2, r4\n \tadd\tr1, pc\n \tadd.w\tr0, r5, #228\t@ 0xe4\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tb.w\t10ac <__gridxc_atom_MOD_atomxc+0x10ac>\n+\tb.w\t1094 <__gridxc_atom_MOD_atomxc+0x1094>\n \tnop\n+\t...\n \t.word\t0xe826d695\n \t.word\t0x3e112e0b\n \t.word\t0x54442d18\n \t.word\t0x409921fb\n-\t.word\t0x000003b4\n+\t.word\t0x00000398\n R_ARM_REL32\t.bss\n-\t.word\t0x000001bc\n+\t.word\t0x000001c0\n R_ARM_REL32\t.LC17\n-\t.word\t0x000001ae\n+\t.word\t0x000001ba\n R_ARM_REL32\t.rodata\n-\t.word\t0x000001ac\n+\t.word\t0x000001b4\n R_ARM_REL32\t.bss\n-\t.word\t0x0000019a\n+\t.word\t0x000001a4\n R_ARM_REL32\t.LC20\n-\t.word\t0x00000168\n+\t.word\t0x00000172\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000160\n+\t.word\t0x0000016a\n R_ARM_REL32\t.LC22\n-\t.word\t0x00000146\n+\t.word\t0x00000150\n R_ARM_REL32\t.LC24\n-\t.word\t0x000000c0\n+\t.word\t0x000000c8\n R_ARM_REL32\t.bss\n-\t.word\t0x000000bc\n+\t.word\t0x000000c4\n R_ARM_REL32\t.LC34\n-\t.word\t0x000000b0\n+\t.word\t0x000000b8\n R_ARM_REL32\t.LC33\n-\t.word\t0x000000a2\n+\t.word\t0x000000aa\n R_ARM_REL32\t.LC32\n-\t.word\t0x00000094\n+\t.word\t0x0000009c\n R_ARM_REL32\t.LC31\n-\t.word\t0x00000086\n+\t.word\t0x0000008e\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000078\n+\t.word\t0x00000080\n R_ARM_REL32\t.LC27\n-\t.word\t0x0000006a\n+\t.word\t0x00000072\n R_ARM_REL32\t.LC26\n-\t.word\t0x0000005e\n+\t.word\t0x00000066\n R_ARM_REL32\t.LC25\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n \tmovs\tr1, #0\n \tmovs\tr4, #0\n-\tsubs\tr3, #32\n+\tsubs\tr3, #24\n \tmov\tr0, r3\n-\tmov\tr5, r3\n+\tmov\tr6, r3\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_get_qmesh>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_get_qmesh\n-\tldr\tr3, [pc, #544]\t@ (2668 <__gridxc_atom_MOD_atomxc+0x2668>)\n-\tldr\tr0, [pc, #544]\t@ (266c <__gridxc_atom_MOD_atomxc+0x266c>)\n-\tldr\tr2, [pc, #548]\t@ (2670 <__gridxc_atom_MOD_atomxc+0x2670>)\n-\tadd\tr3, pc\n-\tldr.w\tr6, [r7, #204]\t@ 0xcc\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tstr\tr3, [sp, #0]\n+\tldr\tr0, [pc, #560]\t@ (2630 <__gridxc_atom_MOD_atomxc+0x2630>)\n+\tldr\tr3, [pc, #564]\t@ (2634 <__gridxc_atom_MOD_atomxc+0x2634>)\n+\tldr\tr2, [pc, #564]\t@ (2638 <__gridxc_atom_MOD_atomxc+0x2638>)\n \tadd\tr0, pc\n+\tadd\tr3, pc\n \tmov\tfp, r0\n \tmov\tr1, r3\n \tadd\tr2, pc\n \tadds\tr0, #228\t@ 0xe4\n-\tstr\tr6, [sp, #0]\n-\tmov\tsl, r3\n \tstr\tr2, [sp, #4]\n-\tmovs\tr2, #11\n \tstr\tr4, [sp, #24]\n-\tadd.w\tr8, sl, #20\n-\tstr\tr2, [sp, #20]\n-\tmov\tr2, r5\n+\tmovs\tr2, #11\n \tstrd\tr4, r4, [sp, #12]\n+\tmov\tr5, r3\n+\tstr\tr2, [sp, #20]\n+\tmov\tr2, r6\n \tstr\tr4, [sp, #8]\n+\tadd.w\tr8, r5, #20\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr2, [pc, #504]\t@ (2674 <__gridxc_atom_MOD_atomxc+0x2674>)\n-\tmov\tr3, sl\n-\tmov\tr1, sl\n+\tstrd\tr4, r4, [sp, #20]\n+\tldr\tr2, [pc, #524]\t@ (263c <__gridxc_atom_MOD_atomxc+0x263c>)\n+\tmov\tr1, r5\n+\tstr\tr4, [sp, #32]\n+\tadd.w\tr0, fp, #276\t@ 0x114\n+\tstr\tr4, [sp, #16]\n \tadd\tr2, pc\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n \tstr\tr2, [sp, #12]\n \tmovs\tr2, #12\n-\tadd.w\tr0, fp, #276\t@ 0x114\n-\tstrd\tsl, r6, [sp, #4]\n-\tmovs\tr6, #9\n+\tstrd\tr5, r3, [sp, #4]\n+\tmov\tr3, r5\n \tstr\tr2, [sp, #28]\n-\tadd\tr2, sl\n-\tstr\tr4, [sp, #32]\n-\tstrd\tr4, r4, [sp, #20]\n-\tstr\tr4, [sp, #16]\n-\tstr\tr5, [sp, #0]\n+\tadds\tr2, r5, r2\n+\tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr2, [pc, #468]\t@ (2678 <__gridxc_atom_MOD_atomxc+0x2678>)\n-\tmov\tr3, sl\n-\tmov\tr1, sl\n+\tldr\tr2, [pc, #492]\t@ (2640 <__gridxc_atom_MOD_atomxc+0x2640>)\n+\tmov\tr3, r5\n+\tmov\tr1, r5\n \tadd\tr2, pc\n \tadd.w\tr0, fp, #336\t@ 0x150\n \tstr\tr2, [sp, #4]\n \tmovs\tr2, #13\n \tstr\tr4, [sp, #24]\n \tstr\tr2, [sp, #20]\n-\tmov\tr2, r5\n+\tmov\tr2, r6\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n-\tstr\tr5, [sp, #0]\n+\tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr2, [pc, #440]\t@ (267c <__gridxc_atom_MOD_atomxc+0x267c>)\n-\tmov\tr3, sl\n-\tmov\tr1, sl\n+\tldr\tr2, [pc, #460]\t@ (2644 <__gridxc_atom_MOD_atomxc+0x2644>)\n+\tmov\tr3, r5\n+\tmov\tr1, r5\n \tadd\tr2, pc\n \tadd.w\tr0, fp, #384\t@ 0x180\n \tstr\tr2, [sp, #4]\n \tmovs\tr2, #10\n \tstr\tr4, [sp, #24]\n \tstr\tr2, [sp, #20]\n-\tmov\tr2, r5\n+\tmov\tr2, r6\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n-\tstr\tr5, [sp, #0]\n+\tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr2, [pc, #408]\t@ (2680 <__gridxc_atom_MOD_atomxc+0x2680>)\n-\tadd.w\tr3, sl, #16\n+\tldr\tr2, [pc, #432]\t@ (2648 <__gridxc_atom_MOD_atomxc+0x2648>)\n+\tmovs\tr3, #9\n \tmov\tr1, r8\n+\tstr\tr3, [sp, #20]\n \tadd\tr2, pc\n-\tadd.w\tr0, fp, #432\t@ 0x1b0\n+\tmov\tr3, r5\n \tstr\tr2, [sp, #4]\n-\tmov\tr2, r3\n+\tadd.w\tr0, fp, #432\t@ 0x1b0\n+\tadd.w\tr2, r5, #16\n \tstr\tr4, [sp, #24]\n-\tmov\tr3, sl\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n-\tstr\tr5, [sp, #0]\n-\tstr\tr6, [sp, #20]\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n+\tstr\tr6, [sp, #0]\n+\tstr.w\tr2, [r7, #300]\t@ 0x12c\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr2, [pc, #372]\t@ (2684 <__gridxc_atom_MOD_atomxc+0x2684>)\n-\tstrd\tr6, r4, [sp, #20]\n-\tmov\tr3, sl\n-\tstrd\tr4, r4, [sp, #12]\n+\tldr\tr2, [pc, #396]\t@ (264c <__gridxc_atom_MOD_atomxc+0x264c>)\n+\tmovs\tr3, #9\n+\tstrd\tr4, r4, [sp, #8]\n+\tstrd\tr4, r3, [sp, #16]\n \tadd\tr2, pc\n-\tstr\tr4, [sp, #8]\n-\tmov\tr1, sl\n-\tstr\tr5, [sp, #0]\n-\tadd.w\tr0, fp, #480\t@ 0x1e0\n+\tstr\tr4, [sp, #24]\n+\tmov\tr3, r5\n+\tstr\tr6, [sp, #0]\n+\tmov\tr1, r5\n \tstr\tr2, [sp, #4]\n-\tldr.w\tr2, [r7, #232]\t@ 0xe8\n+\tadd.w\tr0, fp, #480\t@ 0x1e0\n+\tldr.w\tr2, [r7, #256]\t@ 0x100\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr0, [pc, #344]\t@ (2688 <__gridxc_atom_MOD_atomxc+0x2688>)\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tldr\tr0, [pc, #364]\t@ (2650 <__gridxc_atom_MOD_atomxc+0x2650>)\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n \tmov\tr1, r8\n+\tmovs\tr3, #9\n \tadd\tr0, pc\n-\tmov\tr3, sl\n+\tstrd\tr4, r3, [sp, #16]\n+\tmov\tr3, r5\n \tstr\tr0, [sp, #4]\n \tadd.w\tr0, fp, #528\t@ 0x210\n-\tstrd\tr6, r4, [sp, #20]\n-\tstrd\tr4, r4, [sp, #12]\n-\tstr\tr4, [sp, #8]\n-\tstr\tr5, [sp, #0]\n+\tstr\tr4, [sp, #24]\n+\tstrd\tr4, r4, [sp, #8]\n+\tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr2, [pc, #312]\t@ (268c <__gridxc_atom_MOD_atomxc+0x268c>)\n+\tldr\tr2, [pc, #332]\t@ (2654 <__gridxc_atom_MOD_atomxc+0x2654>)\n \tstrd\tr4, r4, [sp, #12]\n-\tmov\tr3, sl\n+\tmovs\tr3, #9\n \tadd\tr2, pc\n-\tstr\tr6, [sp, #20]\n-\tstr\tr5, [sp, #0]\n-\tadd.w\tr0, fp, #576\t@ 0x240\n+\tstr\tr3, [sp, #20]\n+\tstr\tr6, [sp, #0]\n+\tmov\tr3, r5\n \tstr\tr4, [sp, #24]\n-\tmov\tr1, sl\n+\tadd.w\tr0, fp, #576\t@ 0x240\n \tstr\tr4, [sp, #8]\n+\tmov\tr1, r5\n \tstr\tr2, [sp, #4]\n-\tldr.w\tr2, [r7, #232]\t@ 0xe8\n+\tldr.w\tr2, [r7, #256]\t@ 0x100\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n \tcmp\tr3, #2\n-\tble.w\t3608 <__gridxc_atom_MOD_atomxc+0x3608>\n-\tldr\tr2, [r7, #100]\t@ 0x64\n-\tvmov.i64\td21, #0x0000000000000000\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr.w\tr0, [r7, #276]\t@ 0x114\n-\tldr\tr1, [r7, #48]\t@ 0x30\n+\tble.w\t354c <__gridxc_atom_MOD_atomxc+0x354c>\n+\tldr\tr2, [r7, #84]\t@ 0x54\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tldr.w\tr0, [r7, #280]\t@ 0x118\n+\tldr\tr1, [r7, #36]\t@ 0x24\n \tadd.w\tr3, r3, r2, lsl #1\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr2, [r7, #72]\t@ 0x48\n \tadds\tr3, #1\n-\tvldr\td23, [pc, #204]\t@ 2660 <__gridxc_atom_MOD_atomxc+0x2660>\n+\tvldr\td2, [pc, #216]\t@ 2620 <__gridxc_atom_MOD_atomxc+0x2620>\n+\tvldr\td1, [pc, #220]\t@ 2628 <__gridxc_atom_MOD_atomxc+0x2628>\n \tadd.w\tr3, r2, r3, lsl #3\n \tmovs\tr2, #2\n-\tb.n\t2624 <__gridxc_atom_MOD_atomxc+0x2624>\n-\tvldr\td17, [r3, #8]\n-\tvadd.f64\td16, d16, d17\n-\tvcmpe.f64\td16, d23\n+\tb.n\t25e6 <__gridxc_atom_MOD_atomxc+0x25e6>\n+\tvldr\td7, [r3, #8]\n+\tvadd.f64\td0, d0, d7\n+\tvcmpe.f64\td0, d1\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.n\t25d6 <__gridxc_atom_MOD_atomxc+0x25d6>\n+\tvldr\td5, [r9]\n+\tvldr\td7, [r3]\n+\tvldr\td3, [r1]\n+\tvldr\td10, [r1, #8]\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td4, [r9, #16]\n+\tvldr\td5, [r3, #16]\n+\tvmul.f64\td0, d0, d10\n+\tvldr\td6, [r1, #16]\n+\tvmul.f64\td7, d7, d3\n+\tvadd.f64\td5, d5, d4\n+\tvmov.f64\td4, d0\n+\tvsub.f64\td7, d0, d7\n+\tvnmls.f64\td4, d5, d6\n+\tvsub.f64\td5, d6, d10\n+\tvsub.f64\td10, d3, d10\n+\tvsub.f64\td6, d6, d3\n+\tvmul.f64\td0, d6, d0\n+\tvdiv.f64\td11, d4, d5\n+\tvdiv.f64\td5, d7, d10\n+\tvadd.f64\td11, d11, d5\n+\tvadd.f64\td11, d11, d11\n+\tvdiv.f64\td6, d11, d0\n+\tvabs.f64\td6, d6\n+\tvcmpe.f64\td2, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t2614 <__gridxc_atom_MOD_atomxc+0x2614>\n-\tvldr\td18, [r9]\n-\tvldr\td17, [r3]\n-\tvldr\td24, [r1]\n-\tvldr\td19, [r1, #8]\n-\tvadd.f64\td17, d17, d18\n-\tvldr\td20, [r3, #16]\n-\tvldr\td22, [r9, #16]\n-\tvmul.f64\td16, d16, d19\n-\tvldr\td18, [r1, #16]\n-\tvadd.f64\td20, d20, d22\n-\tvmul.f64\td17, d17, d24\n-\tvmov.f64\td22, d16\n-\tvsub.f64\td17, d16, d17\n-\tvfnms.f64\td22, d20, d18\n-\tvsub.f64\td25, d24, d19\n-\tvsub.f64\td19, d18, d19\n-\tvsub.f64\td18, d18, d24\n-\tvdiv.f64\td20, d17, d25\n-\tvmul.f64\td16, d18, d16\n-\tvdiv.f64\td17, d22, d19\n-\tvadd.f64\td17, d20, d17\n-\tvadd.f64\td17, d17, d17\n-\tvdiv.f64\td18, d17, d16\n-\tvabs.f64\td18, d18\n-\tvmaxnm.f64\td21, d21, d18\n-\tldr.w\tr4, [r7, #140]\t@ 0x8c\n+\tit\tlt\n+\tvmovlt.f64\td2, d6\n+\tldr.w\tr4, [r7, #144]\t@ 0x90\n \tadds\tr3, #8\n \tadd.w\tr9, r9, #8\n \tadds\tr1, #8\n \tcmp\tr4, r2\n-\tbeq.n\t2690 <__gridxc_atom_MOD_atomxc+0x2690>\n+\tbeq.n\t2658 <__gridxc_atom_MOD_atomxc+0x2658>\n \tadds\tr2, #1\n \tcmp\tr0, #0\n-\tble.n\t2614 <__gridxc_atom_MOD_atomxc+0x2614>\n-\tvldr\td16, [r9, #8]\n+\tble.n\t25d6 <__gridxc_atom_MOD_atomxc+0x25d6>\n+\tvldr\td0, [r9, #8]\n \tcmp\tr0, #1\n-\tbgt.n\t259e <__gridxc_atom_MOD_atomxc+0x259e>\n-\tvcmpe.f64\td16, d23\n+\tbgt.n\t2556 <__gridxc_atom_MOD_atomxc+0x2556>\n+\tvcmpe.f64\td0, d1\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t2614 <__gridxc_atom_MOD_atomxc+0x2614>\n-\tvldr\td24, [r1]\n-\tvldr\td17, [r9]\n-\tvldr\td19, [r1, #8]\n-\tvldr\td18, [r1, #16]\n-\tvmul.f64\td17, d24, d17\n-\tvldr\td20, [r9, #16]\n-\tvmul.f64\td16, d19, d16\n-\tb.n\t25dc <__gridxc_atom_MOD_atomxc+0x25dc>\n-\tnop\n+\tbmi.n\t25d6 <__gridxc_atom_MOD_atomxc+0x25d6>\n+\tvldr\td3, [r1]\n+\tvldr\td7, [r9]\n+\tvldr\td10, [r1, #8]\n+\tvldr\td6, [r1, #16]\n+\tvmul.f64\td7, d3, d7\n+\tvldr\td5, [r9, #16]\n+\tvmul.f64\td0, d10, d0\n+\tb.n\t2594 <__gridxc_atom_MOD_atomxc+0x2594>\n \tnop.w\n+\t...\n \t.word\t0xe826d695\n \t.word\t0x3e112e0b\n-\t.word\t0x00000218\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000216\n+\t.word\t0x0000022a\n R_ARM_REL32\t.bss\n-\t.word\t0x00000214\n+\t.word\t0x0000022c\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000022a\n R_ARM_REL32\t.LC25\n-\t.word\t0x000001f2\n+\t.word\t0x00000200\n R_ARM_REL32\t.LC26\n-\t.word\t0x000001ce\n+\t.word\t0x000001e4\n R_ARM_REL32\t.LC27\n-\t.word\t0x000001b0\n+\t.word\t0x000001c6\n R_ARM_REL32\t.LC28\n-\t.word\t0x00000190\n+\t.word\t0x000001a6\n R_ARM_REL32\t.LC31\n-\t.word\t0x00000168\n+\t.word\t0x0000017e\n R_ARM_REL32\t.LC32\n-\t.word\t0x0000014e\n+\t.word\t0x00000160\n R_ARM_REL32\t.LC33\n-\t.word\t0x00000130\n+\t.word\t0x00000142\n R_ARM_REL32\t.LC34\n-\tvsqrt.f64\td16, d21\n-\tvmov.f64\td18, #52\t@ 0x41a00000 20.0\n-\tvldr\td17, [pc, #924]\t@ 2a38 <__gridxc_atom_MOD_atomxc+0x2a38>\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tsub.w\tr0, r3, #56\t@ 0x38\n-\tsub.w\tr2, r3, #48\t@ 0x30\n-\tstr.w\tr2, [r7, #224]\t@ 0xe0\n-\tvmaxnm.f64\td16, d16, d18\n-\tvminnm.f64\td16, d16, d17\n-\tvstr\td16, [r3, #-56]\t@ 0xffffffc8\n+\tvsqrt.f64\td7, d2\n+\tvmov.f64\td5, #52\t@ 0x41a00000 20.0\n+\tvldr\td6, [pc, #924]\t@ 2a00 <__gridxc_atom_MOD_atomxc+0x2a00>\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n+\tsub.w\tr0, r3, #48\t@ 0x30\n+\tvcmpe.f64\td7, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvstr\td7, [r3, #-48]\t@ 0xffffffd0\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_kcut>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_kcut\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tfp, [pc, #920]\t@ 2a58 <__gridxc_atom_MOD_atomxc+0x2a58>\n-\tvmov.i32\td11, #0\t@ 0x00000000\n-\tsub.w\tr3, r3, #1440\t@ 0x5a0\n-\tldr.w\tr4, [r7, #280]\t@ 0x118\n-\tldr\tr5, [r7, #16]\n+\tsub.w\tr3, sl, #1432\t@ 0x598\n+\tldr.w\tr8, [r3]\n+\tldr.w\tfp, [pc, #884]\t@ 2a10 <__gridxc_atom_MOD_atomxc+0x2a10>\n+\tmov.w\tr9, #1\n+\tldr.w\tr4, [r7, #236]\t@ 0xec\n+\tmovs\tr6, #0\n+\tldr.w\tr5, [r7, #132]\t@ 0x84\n \tadd\tfp, pc\n+\tadd.w\tr3, fp, #276\t@ 0x114\n+\tstr.w\tr8, [r7, #300]\t@ 0x12c\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldr.w\tr3, [fp, #40]\t@ 0x28\n \tmov.w\tr8, #1\n-\tldr.w\tsl, [r3]\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tstr.w\tsl, [r7, #288]\t@ 0x120\n-\tvdup.32\td9, sl\n-\tmov\tsl, r3\n-\tsub.w\tr2, r3, #76\t@ 0x4c\n-\tstr.w\tr2, [r7, #268]\t@ 0x10c\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tmovs\tr6, #1\n \tldr.w\tr2, [fp, #36]\t@ 0x24\n+\tsub.w\tr3, r9, r3\n \tldr.w\tr1, [fp]\n-\tldr\tr0, [r7, #124]\t@ 0x7c\n-\tvstr\td11, [r3]\n-\tadd.w\tr3, fp, #20\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [fp, #40]\t@ 0x28\n-\tsub.w\tr3, r8, r3\n+\tstrd\tr6, r6, [sl, #-76]\t@ 0x4c\n+\tstr.w\tr8, [sl, #-60]\n \tmul.w\tr2, r3, r2\n-\tvmov.32\tr3, d16[1]\n+\tldr.w\tr3, [fp, #28]\n+\tldr.w\tr0, [r7, #136]\t@ 0x88\n+\trsb\tr3, r3, #1\n \tadd.w\tr2, r1, r2, lsl #3\n+\tstr.w\tr2, [r7, #292]\t@ 0x124\n \tstr.w\tr2, [sl, #-88]\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tsub.w\tr2, sl, #68\t@ 0x44\n-\tnegs\tr3, r3\n-\tstr.w\tr3, [sl, #-84]\n-\tldr.w\tr3, [fp, #28]\n-\tvst1.32\t{d16}, [r2]\n+\tmovs\tr1, #8\n+\tldr.w\tr2, [fp, #24]\n+\tstr.w\tr2, [sl, #-64]\n+\tnegs\tr2, r2\n+\tstr.w\tr2, [sl, #-84]\n \tldr.w\tr2, [fp, #32]\n-\trsb\tr3, r3, #1\n-\tstr.w\tr6, [sl, #-60]\n+\tstr.w\tr1, [sl, #-80]\n \tadd\tr3, r2\n-\tmovw\tr2, #769\t@ 0x301\n \tstr.w\tr3, [sl, #-56]\n-\tmovs\tr3, #8\n+\tldr.w\tr3, [fp, #20]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr3, [sl, #-68]\n \tstrh.w\tr2, [sl, #-72]\n-\tstr.w\tr3, [sl, #-80]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr1, fp, #188\t@ 0xbc\n-\tmov\tr9, r0\n+\tldr.w\tr3, [fp, #220]\t@ 0xdc\n+\tstr.w\tr0, [r7, #296]\t@ 0x128\n+\tmovs\tr1, #8\n \tldr.w\tr0, [fp, #216]\t@ 0xd8\n-\tmovs\tr3, #8\n-\tstr.w\tr3, [r4, #-64]\n-\tvld1.32\t{d16}, [r1]\n-\tldr.w\tr1, [fp, #220]\t@ 0xdc\n-\tstr.w\tr6, [r4, #-44]\n-\tsub.w\tr1, r8, r1\n-\tstr.w\tr6, [r4, #-32]\n-\tvstr\td11, [r4, #-60]\t@ 0xffffffc4\n-\tmul.w\tr0, r1, r0\n-\tvmov.32\tr1, d16[1]\n-\trsb\tip, r1, #0\n-\tldr.w\tr1, [fp, #196]\t@ 0xc4\n-\tsub.w\tlr, r6, r1\n-\tldr.w\tr1, [fp, #208]\t@ 0xd0\n-\tsubs\tr3, r6, r1\n+\tsub.w\tr3, r9, r3\n+\tstr.w\tr1, [r4, #-64]\n \tldr.w\tr1, [fp, #168]\t@ 0xa8\n-\tadd.w\tr1, r1, r0, lsl #3\n+\tstr.w\tr6, [r4, #-56]\n+\tmul.w\tr3, r0, r3\n+\tldr.w\tr0, [fp, #192]\t@ 0xc0\n+\tstr.w\tr0, [r4, #-48]\n+\trsb\tip, r0, #0\n+\tldr.w\tr0, [fp, #196]\t@ 0xc4\n+\tadd.w\tr1, r1, r3, lsl #3\n+\tldr.w\tr3, [fp, #204]\t@ 0xcc\n+\tstr.w\tr3, [r4, #-36]\n+\tsub.w\tlr, r8, r0\n+\tsub.w\tr3, ip, r3\n+\tstr.w\tr3, [r4, #-68]\n+\tldr.w\tr3, [fp, #200]\t@ 0xc8\n+\tldr.w\tr0, [fp, #208]\t@ 0xd0\n+\tadd\tr3, lr\n+\tstr.w\tr3, [r4, #-40]\n+\tldr.w\tr3, [fp, #212]\t@ 0xd4\n+\tsub.w\tr0, r8, r0\n+\tstr.w\tr8, [r4, #-44]\n+\tadd\tr3, r0\n+\tstr.w\tr3, [r4, #-28]\n+\tldr.w\tr3, [fp, #188]\t@ 0xbc\n+\tstr.w\tr8, [r4, #-32]\n \tstr.w\tr1, [r4, #-72]\n-\tstr.w\tr1, [r7, #272]\t@ 0x110\n-\tsub.w\tr1, r4, #52\t@ 0x34\n-\tldr\tr0, [r7, #104]\t@ 0x68\n-\tvst1.32\t{d16}, [r1]\n-\tldr.w\tr1, [fp, #204]\t@ 0xcc\n-\tstr.w\tr1, [r4, #-36]\n-\tsub.w\tr1, ip, r1\n-\tstr.w\tr1, [r4, #-68]\n-\tldr.w\tr1, [fp, #200]\t@ 0xc8\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r4, #-40]\n-\tldr.w\tr1, [fp, #212]\t@ 0xd4\n-\tadd\tr1, r3\n-\tstr.w\tr1, [r4, #-28]\n-\tmovw\tr1, #770\t@ 0x302\n-\tstrh.w\tr1, [r4, #-56]\n+\tstr.w\tr3, [r4, #-52]\n+\tmovw\tr3, #770\t@ 0x302\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tstrh.w\tr3, [r4, #-56]\n+\tstr.w\tr6, [r4, #-60]\n+\tstr.w\tr1, [r7, #288]\t@ 0x120\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tmovs\tr3, #8\n-\tstr.w\tr3, [r5, #-72]\n-\tmovw\tr2, #769\t@ 0x301\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tstr.w\tr3, [r5, #-48]\n \tldr.w\tr3, [fp, #520]\t@ 0x208\n-\tvstr\td11, [r5, #-68]\t@ 0xffffffbc\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr6, [r5, #-64]\n+\tmovs\tr1, #8\n \tstrh.w\tr2, [r5, #-64]\n \trsb\tr3, r3, #1\n \tldr.w\tr2, [fp, #516]\t@ 0x204\n+\tstr.w\tr1, [r5, #-72]\n \tstr.w\tr2, [r5, #-56]\n-\tldr.w\tr1, [fp, #504]\t@ 0x1f8\n-\tstr.w\tr6, [r5, #-52]\n-\tmov\tr6, r0\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n \tmul.w\tr3, r2, r3\n \tnegs\tr2, r2\n \tstr.w\tr2, [r5, #-76]\n \tldr.w\tr2, [fp, #508]\t@ 0x1fc\n-\tsub.w\tr2, r8, r2\n+\tstr.w\tr1, [r5, #-48]\n+\tldr.w\tr1, [fp, #504]\t@ 0x1f8\n+\tsub.w\tr2, r9, r2\n+\tstr.w\tr8, [r5, #-52]\n+\tmov\tr8, r0\n+\tstr.w\tr6, [r5, #-68]\n \tmla\tr3, r1, r2, r3\n \tldr.w\tr2, [fp, #480]\t@ 0x1e0\n-\tmov\tr1, r9\n+\tldr.w\tr1, [r7, #284]\t@ 0x11c\n \tadd.w\tr2, r2, r3, lsl #3\n \tldr.w\tr3, [fp, #500]\t@ 0x1f4\n \tstr.w\tr2, [r5, #-80]\n \tmov\tr2, r0\n \tstr.w\tr3, [r5, #-60]\n-\tadd.w\tr3, fp, #276\t@ 0x114\n-\tstr\tr3, [sp, #4]\n \tadd.w\tr3, fp, #228\t@ 0xe4\n+\tstr\tr1, [sp, #4]\n \tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n-\tldr.w\tr0, [r7, #204]\t@ 0xcc\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n+\tldr.w\tr0, [r7, #220]\t@ 0xdc\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_theta\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tcmp\tr2, r9\n-\tbeq.n\t2872 <__gridxc_atom_MOD_atomxc+0x2872>\n-\tmov\tr0, r9\n+\tldrd\tr3, r2, [r7, #292]\t@ 0x124\n+\tcmp\tr3, r2\n+\tbeq.n\t2840 <__gridxc_atom_MOD_atomxc+0x2840>\n+\tmov\tr0, r2\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n-\tcmp\tr3, r6\n-\tbeq.w\t3302 <__gridxc_atom_MOD_atomxc+0x3302>\n-\tmov\tr0, r6\n-\tadd.w\tr8, r8, #1\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n+\tcmp\tr3, r8\n+\tbeq.w\t32a2 <__gridxc_atom_MOD_atomxc+0x32a2>\n+\tmov\tr0, r8\n+\tadd.w\tr9, r9, #1\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tcmp\tr3, r8\n-\tbge.w\t26f0 <__gridxc_atom_MOD_atomxc+0x26f0>\n-\tldr.w\tsl, [r7, #288]\t@ 0x120\n-\tvldr\td17, [pc, #424]\t@ 2a40 <__gridxc_atom_MOD_atomxc+0x2a40>\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tcmp\tr3, r9\n+\tbge.w\t26b8 <__gridxc_atom_MOD_atomxc+0x26b8>\n+\tldr.w\tr8, [r7, #300]\t@ 0x12c\n+\tvldr\td6, [pc, #420]\t@ 2a08 <__gridxc_atom_MOD_atomxc+0x2a08>\n \tldr\tr3, [r7, #20]\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n-\tvmul.f64\td17, d8, d17\n+\tldr.w\tr2, [r7, #176]\t@ 0xb0\n+\tvmul.f64\td6, d8, d6\n \taddw\tr1, r3, #4088\t@ 0xff8\n \tmovs\tr3, #0\n \tvmov\ts15, r3\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n \tcmp\tr1, r2\n-\tbne.n\t28a8 <__gridxc_atom_MOD_atomxc+0x28a8>\n-\tvldr\td17, [pc, #384]\t@ 2a40 <__gridxc_atom_MOD_atomxc+0x2a40>\n+\tbne.n\t2876 <__gridxc_atom_MOD_atomxc+0x2876>\n+\tvldr\td6, [pc, #376]\t@ 2a08 <__gridxc_atom_MOD_atomxc+0x2a08>\n \tldr\tr3, [r7, #24]\n-\tldr\tr2, [r7, #124]\t@ 0x7c\n-\tvmul.f64\td17, d10, d17\n+\tldr.w\tr2, [r7, #136]\t@ 0x88\n+\tvmul.f64\td6, d9, d6\n \tadd.w\tr1, r3, #4080\t@ 0xff0\n \tmovs\tr3, #0\n-\tstr.w\tr2, [r7, #272]\t@ 0x110\n-\tstr.w\tr1, [r7, #236]\t@ 0xec\n+\tstr.w\tr2, [r7, #288]\t@ 0x120\n+\tstr.w\tr1, [r7, #244]\t@ 0xf4\n \tvmov\ts15, r3\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n \tcmp\tr1, r2\n-\tbne.n\t28d8 <__gridxc_atom_MOD_atomxc+0x28d8>\n-\tldr\tr0, [pc, #364]\t@ (2a5c <__gridxc_atom_MOD_atomxc+0x2a5c>)\n+\tbne.n\t28a8 <__gridxc_atom_MOD_atomxc+0x28a8>\n+\tldr\tr0, [pc, #340]\t@ (2a14 <__gridxc_atom_MOD_atomxc+0x2a14>)\n \tmovs\tr2, #0\n \tmov\tr1, r2\n \tmovs\tr3, #8\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_mesh1d_MOD_set_interpolation>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_interpolation\n \tmovs\tr3, #0\n \tstrd\tr3, r3, [sp]\n \tmov\tr2, r3\n-\tldrd\tr1, r0, [r7, #228]\t@ 0xe4\n+\tldr.w\tr1, [r7, #240]\t@ 0xf0\n+\tldr.w\tr0, [r7, #256]\t@ 0x100\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tcmp.w\tsl, #0\n-\tble.w\t3626 <__gridxc_atom_MOD_atomxc+0x3626>\n-\tldr.w\tr9, [pc, #328]\t@ 2a60 <__gridxc_atom_MOD_atomxc+0x2a60>\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tldr\tr3, [pc, #324]\t@ (2a64 <__gridxc_atom_MOD_atomxc+0x2a64>)\n-\tmov.w\tfp, #1\n-\tadd\tr9, pc\n+\tcmp.w\tr8, #0\n+\tble.w\t2b6e <__gridxc_atom_MOD_atomxc+0x2b6e>\n+\tldr\tr3, [pc, #300]\t@ (2a18 <__gridxc_atom_MOD_atomxc+0x2a18>)\n+\tsub.w\tfp, sl, #616\t@ 0x268\n+\tldr\tr6, [pc, #300]\t@ (2a1c <__gridxc_atom_MOD_atomxc+0x2a1c>)\n+\tadd.w\tr2, r7, #1032\t@ 0x408\n \tadd\tr3, pc\n+\tstr.w\tr2, [r7, #284]\t@ 0x11c\n \tadds\tr3, #24\n-\tstr.w\tr3, [r7, #268]\t@ 0x10c\n-\tadd.w\tr3, r7, #1032\t@ 0x408\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n-\tadd.w\tr3, r9, #500\t@ 0x1f4\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tvldr\td10, [pc, #260]\t@ 2a48 <__gridxc_atom_MOD_atomxc+0x2a48>\n-\tvldr\td11, [pc, #264]\t@ 2a50 <__gridxc_atom_MOD_atomxc+0x2a50>\n-\tsub.w\tr8, r3, #700\t@ 0x2bc\n-\tstr.w\tr8, [r7, #260]\t@ 0x104\n-\tmov\tr8, r3\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr0, [r9, #516]\t@ 0x204\n-\tldr.w\tr6, [r9, #480]\t@ 0x1e0\n-\tldr.w\tr4, [r9, #436]\t@ 0x1b4\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r7, #260]\t@ 0x104\n-\tvmov.32\tr2, d16[1]\n-\tvstr\td8, [r3]\n-\tldr.w\tr3, [r9, #508]\t@ 0x1fc\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tmovs\tr3, #1\n+\tadd\tr6, pc\n+\tmov\tr9, r3\n+\tldr.w\tr3, [r6, #508]\t@ 0x1fc\n+\tsub.w\tr4, sl, #712\t@ 0x2c8\n+\tldr.w\tr2, [r6, #504]\t@ 0x1f8\n+\tmovs\tr5, #8\n+\tldr.w\tr1, [r6, #520]\t@ 0x208\n \trsb\tr3, r3, #1\n-\tnegs\tr1, r2\n+\tldr.w\tr0, [r6, #516]\t@ 0x204\n+\tsub.w\tr1, r9, r1\n+\tstr\tr2, [r4, #24]\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r9, #520]\t@ 0x208\n-\tsub.w\tr2, fp, r2\n-\tmla\tr3, r0, r2, r3\n-\tsub.w\tr2, r8, #712\t@ 0x2c8\n-\tldr.w\tr0, [r7, #264]\t@ 0x108\n-\tadd.w\tr6, r6, r3, lsl #3\n-\tsub.w\tr3, r8, #692\t@ 0x2b4\n-\tstr\tr1, [r2, #4]\n-\tldr.w\tr1, [r7, #140]\t@ 0x8c\n-\tstr\tr1, [r2, #32]\n-\tmovs\tr1, #8\n-\tstr\tr6, [r2, #0]\n-\tvst1.32\t{d16}, [r3]\n-\tmovs\tr3, #1\n-\tstr\tr1, [r2, #8]\n-\tstr\tr3, [r2, #28]\n-\tmovw\tr3, #769\t@ 0x301\n-\tstrh\tr3, [r2, #16]\n-\tldr.w\tr3, [r9, #432]\t@ 0x1b0\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tnegs\tr2, r2\n+\tstr\tr2, [r4, #4]\n+\tsub.w\tr2, sl, #700\t@ 0x2bc\n+\tmla\tr3, r0, r1, r3\n+\tldr.w\tr1, [r7, #144]\t@ 0x90\n+\tstr\tr1, [r4, #32]\n+\tldr.w\tr1, [r6, #480]\t@ 0x1e0\n+\tldr.w\tr0, [r7, #284]\t@ 0x11c\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tstr\tr3, [r4, #0]\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmovs\tr1, #1\n+\tldr.w\tr3, [r6, #500]\t@ 0x1f4\n+\tstr\tr3, [r4, #20]\n+\tmovs\tr3, #0\n+\tstrd\tr3, r3, [r2]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr\tr5, [r4, #8]\n+\tstr\tr1, [r4, #28]\n+\tstrh\tr2, [r4, #16]\n+\tldr.w\tr2, [r6, #432]\t@ 0x1b0\n+\tstr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr4, [r6, #436]\t@ 0x1b4\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tsub.w\tr2, r8, #616\t@ 0x268\n-\tvstr\td8, [r8, #-604]\t@ 0xfffffda4\n-\tmovw\tr3, #769\t@ 0x301\n-\tmovs\tr1, #8\n-\tmov\tr5, r0\n-\tstrh\tr3, [r2, #16]\n-\tldr\tr3, [r7, #104]\t@ 0x68\n-\tstr\tr3, [r2, #0]\n-\tsub.w\tr3, r8, #596\t@ 0x254\n-\tstr\tr1, [r2, #8]\n-\tvst1.32\t{d10-d11}, [r3]\n+\tmovs\tr1, #1\n+\tstr.w\tr1, [fp, #24]\n+\tsub.w\tr1, sl, #604\t@ 0x25c\n+\tldr\tr2, [r7, #112]\t@ 0x70\n \tmovs\tr3, #0\n-\tstr\tr3, [r2, #4]\n+\tstr.w\tr5, [fp, #8]\n+\tstrd\tr2, r3, [fp]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr5, [fp, #20]\n+\tmov\tr5, r0\n+\tstr.w\tr3, [fp, #28]\n+\tstrd\tr3, r3, [r1]\n+\tstrh.w\tr2, [fp, #16]\n+\tmov.w\tr2, #512\t@ 0x200\n+\tstr.w\tr2, [fp, #32]\n \tstrd\tr3, r3, [sp, #4]\n \tstr\tr0, [sp, #0]\n-\tldr.w\tr3, [r7, #232]\t@ 0xe8\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n-\tldr.w\tr1, [r7, #268]\t@ 0x10c\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n+\tldr.w\tr3, [r7, #256]\t@ 0x100\n+\tldr.w\tr2, [r7, #176]\t@ 0xb0\n+\tldr.w\tr1, [r7, #292]\t@ 0x124\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n \tbl\t0 <__gridxc_mesh1d_MOD_interpolation_local>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_interpolation_local\n-\tcmp\tr6, r5\n-\tbeq.n\t2a0a <__gridxc_atom_MOD_atomxc+0x2a0a>\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tcmp\tr3, r5\n+\tbeq.n\t29d0 <__gridxc_atom_MOD_atomxc+0x29d0>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr1, [pc, #92]\t@ (2a68 <__gridxc_atom_MOD_atomxc+0x2a68>)\n-\tsub.w\tr3, r8, #616\t@ 0x268\n-\tldr.w\tr0, [r7, #288]\t@ 0x120\n-\tadd\tr1, pc\n-\tldr\tr2, [r3, #0]\n-\tldr.w\tr6, [r1, #468]\t@ 0x1d4\n-\tldr.w\tr5, [r1, #452]\t@ 0x1c4\n-\tmla\tr3, fp, r6, r4\n-\tldr.w\tr4, [r1, #456]\t@ 0x1c8\n+\tldr\tr0, [pc, #76]\t@ (2a20 <__gridxc_atom_MOD_atomxc+0x2a20>)\n+\tldr.w\tr2, [fp]\n+\tadd\tr0, pc\n \tadd.w\tr1, r2, #4096\t@ 0x1000\n \tadds\tr1, #8\n-\tmla\tr3, r5, r3, r0\n-\tmul.w\tr0, r4, r5\n-\tb.n\t2a6c <__gridxc_atom_MOD_atomxc+0x2a6c>\n+\tldr.w\tip, [r0, #468]\t@ 0x1d4\n+\tldr.w\tr5, [r0, #452]\t@ 0x1c4\n+\tldr.w\tr0, [r0, #456]\t@ 0x1c8\n+\tmla\tr3, r9, ip, r4\n+\tldr.w\tr4, [r7, #296]\t@ 0x128\n+\tmla\tr3, r5, r3, r4\n+\tmul.w\tr4, r0, r5\n+\tb.n\t2a24 <__gridxc_atom_MOD_atomxc+0x2a24>\n+\tnop.w\n \t.word\t0x00000000\n \t.word\t0x40490000\n \t.word\t0x00000000\n \t.word\t0x3f600000\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000000\n-\t.word\t0x00000200\n-\t.word\t0x00000384\n+\t.word\t0x00000362\n R_ARM_REL32\t.bss\n-\t.word\t0x00000162\n+\t.word\t0x0000014a\n R_ARM_REL32\t.LC35\n-\t.word\t0x0000013a\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000013c\n+\t.word\t0x00000120\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000050\n+\t.word\t0x00000116\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000046\n R_ARM_REL32\t.bss\n-\tvldmia\tr2!, {d16}\n-\tvstr\td16, [r3]\n+\tvldmia\tr2!, {d7}\n+\tvstr\td7, [r3]\n \tcmp\tr1, r2\n-\tadd\tr3, r0\n-\tbne.n\t2a6c <__gridxc_atom_MOD_atomxc+0x2a6c>\n-\tadd.w\tfp, fp, #1\n-\tcmp\tfp, sl\n-\tble.w\t2952 <__gridxc_atom_MOD_atomxc+0x2952>\n-\tldr.w\tr8, [pc, #664]\t@ 2d20 <__gridxc_atom_MOD_atomxc+0x2d20>\n-\tadd.w\tr3, r7, #360\t@ 0x168\n-\tstr.w\tr3, [r7, #220]\t@ 0xdc\n-\tvmov.i32\td10, #0\t@ 0x00000000\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tadd\tr8, pc\n-\tldr.w\tfp, [r7, #280]\t@ 0x118\n-\tmov.w\tr9, #1\n-\tsub.w\tr2, r3, #604\t@ 0x25c\n-\tvldr\td8, [pc, #616]\t@ 2d10 <__gridxc_atom_MOD_atomxc+0x2d10>\n-\tsub.w\tr3, r3, #588\t@ 0x24c\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n-\tadd.w\tr3, r8, #452\t@ 0x1c4\n-\tstr.w\tr3, [r7, #268]\t@ 0x10c\n-\tb.n\t2ae2 <__gridxc_atom_MOD_atomxc+0x2ae2>\n-\tldr\tr0, [r7, #104]\t@ 0x68\n-\tmov\tr1, r6\n+\tadd\tr3, r4\n+\tbne.n\t2a24 <__gridxc_atom_MOD_atomxc+0x2a24>\n+\tadd.w\tr9, r9, #1\n+\tcmp\tr8, r9\n+\tbge.w\t2906 <__gridxc_atom_MOD_atomxc+0x2906>\n+\tldr.w\tr9, [pc, #652]\t@ 2ccc <__gridxc_atom_MOD_atomxc+0x2ccc>\n+\tmov.w\tfp, #1\n+\tldr\tr4, [pc, #648]\t@ (2cd0 <__gridxc_atom_MOD_atomxc+0x2cd0>)\n+\tmov\tr2, ip\n+\tadd\tr9, pc\n+\tldr.w\tr6, [r7, #236]\t@ 0xec\n+\tadd.w\tr3, r9, #16\n+\tadd\tr4, pc\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tstr.w\tr9, [r7, #292]\t@ 0x124\n+\tb.n\t2a80 <__gridxc_atom_MOD_atomxc+0x2a80>\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tmov\tr1, r5\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tadd.w\tr9, r9, #1\n-\tmov\tr0, r6\n+\tadd.w\tfp, fp, #1\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tsl, r9\n-\tblt.n\t2bbe <__gridxc_atom_MOD_atomxc+0x2bbe>\n-\tldr\tr3, [pc, #588]\t@ (2d24 <__gridxc_atom_MOD_atomxc+0x2d24>)\n-\tadd\tr3, pc\n-\tldrd\tr5, r4, [r3, #452]\t@ 0x1c4\n-\tldr.w\tr6, [r3, #468]\t@ 0x1d4\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r8, #460]\t@ 0x1cc\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n-\tvstr\td10, [r3]\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tvst1.32\t{d8}, [r3]\n-\tldr.w\tr3, [r8, #472]\t@ 0x1d8\n-\tsub.w\tr3, r9, r3\n-\tmul.w\tr3, r6, r3\n-\tmovw\tr6, #769\t@ 0x301\n-\tmls\tr3, r2, r4, r3\n-\tldr.w\tr2, [r7, #292]\t@ 0x124\n-\tsub.w\tr2, r2, #616\t@ 0x268\n-\tstrd\tr5, r4, [r2, #20]\n-\tnegs\tr4, r4\n-\tldr.w\tr5, [r8, #432]\t@ 0x1b0\n-\tstr\tr4, [r2, #4]\n-\tmovs\tr4, #8\n-\tstrh\tr6, [r2, #16]\n-\tadd.w\tr5, r5, r3, lsl #3\n-\tstr\tr4, [r2, #8]\n-\tstr\tr5, [r2, #0]\n+\tcmp\tr8, fp\n+\tblt.n\t2b6e <__gridxc_atom_MOD_atomxc+0x2b6e>\n+\tldr\tr3, [pc, #604]\t@ (2cd4 <__gridxc_atom_MOD_atomxc+0x2cd4>)\n+\tadd\tr3, pc\n+\tldrd\tr5, r0, [r3, #452]\t@ 0x1c4\n+\tldr.w\tr2, [r3, #468]\t@ 0x1d4\n+\tldr.w\tr3, [r4, #472]\t@ 0x1d8\n+\tsub.w\tip, sl, #616\t@ 0x268\n+\tldr.w\tr1, [r4, #432]\t@ 0x1b0\n+\tmovw\tr9, #513\t@ 0x201\n+\tsub.w\tr3, fp, r3\n+\tstrd\tr5, r0, [ip, #20]\n+\tmovs\tr5, #0\n+\tmul.w\tr3, r2, r3\n+\tldr.w\tr2, [r4, #460]\t@ 0x1cc\n+\tmls\tr3, r2, r0, r3\n+\tsub.w\tr2, sl, #604\t@ 0x25c\n+\tnegs\tr0, r0\n+\tstr.w\tr0, [ip, #4]\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tmovs\tr1, #8\n+\tstr.w\tr3, [ip]\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmovs\tr3, #1\n+\tstrd\tr5, r5, [r2]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr1, [ip, #8]\n+\tstr.w\tr3, [ip, #28]\n+\tstrh.w\tr2, [ip, #16]\n+\tstr.w\tr9, [ip, #32]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tldr.w\tr1, [r8, #468]\t@ 0x1d4\n-\tstr.w\tr4, [fp, #-64]\n-\tmov\tr4, r0\n-\tvstr\td10, [fp, #-60]\t@ 0xffffffc4\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r8, #460]\t@ 0x1cc\n-\tstrh.w\tr6, [fp, #-56]\n-\tvmov.32\tr2, d16[1]\n+\tmovs\tr3, #1\n+\tstrd\tr3, r9, [r6, #-44]\t@ 0x2c\n+\tmovw\tr2, #769\t@ 0x301\n+\tldr.w\tr3, [r4, #460]\t@ 0x1cc\n+\tmovs\tr1, #8\n+\tstrd\tr5, r5, [r6, #-60]\t@ 0x3c\n+\tmov\tr9, r0\n+\tstrh.w\tr2, [r6, #-56]\n \tnegs\tr3, r3\n-\tldr\tr0, [r7, #104]\t@ 0x68\n+\tldr.w\tr2, [r4, #456]\t@ 0x1c8\n+\tstr.w\tr2, [r6, #-48]\n+\tstr.w\tr1, [r6, #-64]\n+\tldr.w\tr1, [r4, #468]\t@ 0x1d4\n \tmul.w\tr3, r2, r3\n \tnegs\tr2, r2\n-\tstr.w\tr2, [fp, #-68]\n-\tldr.w\tr2, [r8, #472]\t@ 0x1d8\n-\tsub.w\tr2, r9, r2\n+\tstr.w\tr2, [r6, #-68]\n+\tldr.w\tr2, [r4, #472]\t@ 0x1d8\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tsub.w\tr2, fp, r2\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r8, #432]\t@ 0x1b0\n+\tldr.w\tr2, [r4, #432]\t@ 0x1b0\n \tadd.w\tr2, r2, r3, lsl #3\n-\tsub.w\tr3, fp, #44\t@ 0x2c\n-\tstr.w\tr2, [fp, #-72]\n-\tvst1.32\t{d8}, [r3]\n-\tsub.w\tr3, fp, #52\t@ 0x34\n-\tvst1.32\t{d16}, [r3]\n+\tldr.w\tr3, [r4, #452]\t@ 0x1c4\n+\tstr.w\tr2, [r6, #-72]\n+\tstr.w\tr3, [r6, #-52]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n-\tmov\tr6, r0\n-\tldr\tr0, [pc, #404]\t@ (2d28 <__gridxc_atom_MOD_atomxc+0x2d28>)\n-\tldr.w\tr2, [r7, #220]\t@ 0xdc\n-\tmov\tr3, r4\n-\tadd\tr0, pc\n-\tadd.w\tr1, r0, #16\n+\tmov\tr5, r0\n+\tmov\tr3, r9\n+\tldrd\tr0, r1, [r7, #292]\t@ 0x124\n+\tldr.w\tr2, [r7, #184]\t@ 0xb8\n \tadds\tr0, #20\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tr5, r4\n-\tbeq.n\t2bae <__gridxc_atom_MOD_atomxc+0x2bae>\n-\tmov\tr0, r4\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tcmp\tr3, r9\n+\tbeq.n\t2b5c <__gridxc_atom_MOD_atomxc+0x2b5c>\n+\tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [fp, #-72]\n-\tcmp\tr3, r6\n-\tbne.n\t2ac0 <__gridxc_atom_MOD_atomxc+0x2ac0>\n-\tadd.w\tr9, r9, #1\n-\tcmp\tr9, sl\n-\tble.n\t2ad6 <__gridxc_atom_MOD_atomxc+0x2ad6>\n-\tmul.w\tr3, sl, sl\n-\tbic.w\tr8, sl, sl, asr #31\n-\tvmov\ts15, r8\n-\tmov.w\tr2, sl, lsl #3\n-\tvldr\td8, [pc, #328]\t@ 2d18 <__gridxc_atom_MOD_atomxc+0x2d18>\n-\tmov\tr4, sl\n-\tvcvt.f32.s32\ts20, s15\n+\tldr.w\tr3, [r6, #-72]\n+\tcmp\tr3, r5\n+\tbne.w\t2a5e <__gridxc_atom_MOD_atomxc+0x2a5e>\n+\tadd.w\tfp, fp, #1\n+\tcmp\tr8, fp\n+\tbge.n\t2a74 <__gridxc_atom_MOD_atomxc+0x2a74>\n+\tmul.w\tr3, r8, r8\n+\tbic.w\tfp, r8, r8, asr #31\n+\tvmov\ts15, fp\n+\tmov.w\tr2, r8, lsl #3\n+\tstr.w\tsl, [r7, #292]\t@ 0x124\n+\tmov\tr4, r8\n+\tvcvt.f32.s32\ts16, s15\n \tlsls\tr3, r3, #3\n \tcmp\tr3, #1\n+\tldr.w\tsl, [r7, #236]\t@ 0xec\n \tit\tcc\n \tmovcc\tr3, #1\n-\tstr.w\tr3, [r7, #256]\t@ 0x100\n-\tldr\tr3, [pc, #324]\t@ (2d2c <__gridxc_atom_MOD_atomxc+0x2d2c>)\n+\tstr.w\tr3, [r7, #264]\t@ 0x108\n+\tldr\tr3, [pc, #316]\t@ (2cd8 <__gridxc_atom_MOD_atomxc+0x2cd8>)\n \tcmp\tr2, #1\n-\tvmul.f32\ts20, s20, s20\n+\tvmul.f32\ts16, s16, s16\n+\tvldr\ts17, [pc, #292]\t@ 2cc8 <__gridxc_atom_MOD_atomxc+0x2cc8>\n+\tadd\tr3, pc\n \tit\tcc\n \tmovcc\tr2, #1\n-\tadd\tr3, pc\n-\tstr.w\tr2, [r7, #244]\t@ 0xf4\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tmvn.w\tr2, sl\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n \tadd.w\tr3, r3, #336\t@ 0x150\n-\tstr.w\tr2, [r7, #252]\t@ 0xfc\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstr.w\tr2, [r7, #248]\t@ 0xf8\n+\tmvn.w\tr2, r8\n+\tstr.w\tr3, [r7, #252]\t@ 0xfc\n+\tstr.w\tr2, [r7, #260]\t@ 0x104\n \tmovs\tr2, #0\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvmov.i32\td11, #0\t@ 0x00000000\n-\tldr.w\tr2, [r7, #248]\t@ 0xf8\n-\tmovs\tr5, #1\n+\tstr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmovs\tr5, #0\n+\tldr.w\tr2, [r7, #252]\t@ 0xfc\n+\tmov.w\tr9, #1\n \tadd.w\tr1, r3, #384\t@ 0x180\n-\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tldr.w\tr0, [r7, #288]\t@ 0x120\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_phi>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_phi\n-\tldr.w\tr2, [r7, #280]\t@ 0x118\n-\tldr.w\tr1, [r7, #252]\t@ 0xfc\n-\tmovs\tr6, #0\n-\tsub.w\tr3, r2, #52\t@ 0x34\n-\tldr.w\tr0, [r7, #256]\t@ 0x100\n-\tstr.w\tr1, [r2, #-68]\n-\tmovw\tsl, #769\t@ 0x301\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tstr.w\tr4, [r2, #-28]\n-\tsub.w\tr9, r1, #712\t@ 0x2c8\n-\tvstr\td9, [r2, #-40]\t@ 0xffffffd8\n-\tvst1.32\t{d8}, [r3]\n-\tvstr\td11, [r1, #-700]\t@ 0xfffffd44\n-\tstr.w\tr5, [r2, #-44]\n-\tstr.w\tr5, [r2, #-32]\n-\tmovs\tr2, #8\n-\tstr.w\tr2, [r9, #8]\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tstr.w\tr6, [r9]\n-\tstrh.w\tsl, [r9, #16]\n-\tldr.w\tr1, [r2, #384]\t@ 0x180\n-\tstr.w\tr1, [r7, #264]\t@ 0x108\n-\tldr.w\tr1, [r2, #388]\t@ 0x184\n-\tldr.w\tfp, [r2, #408]\t@ 0x198\n-\tstr.w\tr1, [r7, #260]\t@ 0x104\n+\tldr.w\tr2, [r7, #260]\t@ 0x104\n+\tstr.w\tr2, [sl, #-68]\n+\tmovs\tr3, #8\n+\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tstr.w\tr3, [sl, #-52]\n+\tsub.w\tr8, r2, #712\t@ 0x2c8\n+\tsub.w\tr6, r2, #700\t@ 0x2bc\n+\tmovw\tr2, #769\t@ 0x301\n+\tldr.w\tr0, [r7, #264]\t@ 0x108\n+\tstr.w\tr4, [sl, #-40]\n+\tstr.w\tr5, [r8]\n+\tstrd\tr5, r5, [r6]\n+\tstr.w\tr3, [r8, #8]\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tstrh.w\tr2, [r8, #16]\n+\tstr.w\tr4, [sl, #-28]\n+\tldr.w\tr2, [r3, #384]\t@ 0x180\n+\tldr.w\tr1, [r3, #408]\t@ 0x198\n+\tstr.w\tr2, [r7, #276]\t@ 0x114\n+\tstr.w\tr4, [sl, #-36]\n+\tldr.w\tr2, [r3, #388]\t@ 0x184\n+\tstrd\tr9, r9, [sl, #-48]\t@ 0x30\n+\tstr.w\tr9, [sl, #-32]\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n+\tstr.w\tr1, [r7, #268]\t@ 0x10c\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n-\tmovs\tr2, #8\n-\tmov\tr1, r0\n-\tcmp\tr4, r6\n-\tstr.w\tr0, [r7, #268]\t@ 0x10c\n-\tstr.w\tr2, [r3, #-64]\n-\tmovw\tr2, #770\t@ 0x302\n-\tvstr\td11, [r3, #-60]\t@ 0xffffffc4\n-\tstr.w\tr0, [r3, #-72]\n-\tstrh.w\tr2, [r3, #-56]\n-\tble.w\t31fa <__gridxc_atom_MOD_atomxc+0x31fa>\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tmov\tip, r6\n-\tldr.w\tr0, [r7, #260]\t@ 0x104\n-\tmov.w\tsl, #4294967295\t@ 0xffffffff\n-\tadd.w\tr6, r1, #8\n-\tldr.w\tr3, [r2, #420]\t@ 0x1a4\n-\tldr.w\tr5, [r2, #404]\t@ 0x194\n-\tadd\tr0, r3\n-\tldr.w\tr2, [r7, #264]\t@ 0x108\n-\tmov\tlr, r0\n-\tadd\tlr, fp\n-\tmul.w\tr9, r5, r3\n-\tmla\tlr, r5, lr, r2\n-\tmul.w\tr5, fp, r5\n-\tadd.w\tr1, r6, sl, lsl #3\n+\tmovs\tr3, #8\n+\tstrd\tr5, r5, [sl, #-60]\t@ 0x3c\n+\tstr.w\tr0, [r7, #284]\t@ 0x11c\n+\tcmp\tr4, r5\n+\tstr.w\tr0, [sl, #-72]\n+\tmovw\tr0, #770\t@ 0x302\n+\tstr.w\tr3, [sl, #-64]\n+\tstrh.w\tr0, [sl, #-56]\n+\tble.w\t3198 <__gridxc_atom_MOD_atomxc+0x3198>\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tldr.w\tr1, [r7, #272]\t@ 0x110\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tldr.w\tr2, [r3, #420]\t@ 0x1a4\n+\tldr.w\tr3, [r3, #404]\t@ 0x194\n+\tadd\tr1, r2\n+\tmov\tlr, r1\n+\tldr.w\tr1, [r7, #268]\t@ 0x10c\n+\tadd\tlr, r1\n+\tmul.w\tr8, r3, r2\n+\tldr.w\tr2, [r7, #284]\t@ 0x11c\n+\tmul.w\tip, r1, r3\n+\tmla\tlr, r3, lr, r0\n+\tadd.w\tr6, r2, #8\n+\tadd.w\tr1, r6, r9, lsl #3\n \tmov\tr2, lr\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tmov\tr0, r3\n \tadds\tr3, #1\n-\tadd\tr2, r5\n+\tadd\tr2, ip\n \tcmp\tr4, r3\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t2cec <__gridxc_atom_MOD_atomxc+0x2cec>\n-\tadd\tlr, r9\n-\tadd\tsl, r4\n-\tadd.w\tr3, ip, #1\n-\tcmp\tip, r0\n-\tbeq.n\t2d30 <__gridxc_atom_MOD_atomxc+0x2d30>\n-\tmov\tip, r3\n-\tb.n\t2ce4 <__gridxc_atom_MOD_atomxc+0x2ce4>\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t2ca6 <__gridxc_atom_MOD_atomxc+0x2ca6>\n+\tadd\tlr, r8\n+\tadd\tr9, r4\n+\tadds\tr3, r5, #1\n+\tcmp\tr5, r0\n+\tbeq.n\t2cdc <__gridxc_atom_MOD_atomxc+0x2cdc>\n+\tmov\tr5, r3\n+\tb.n\t2c9e <__gridxc_atom_MOD_atomxc+0x2c9e>\n \tnop\n-\t.word\t0x00000001\n-\t.word\t0x00000201\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000284\n+\t.word\t0x44610000\n+\t.word\t0x00000280\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000027a\n R_ARM_REL32\t.bss\n-\t.word\t0x00000248\n+\t.word\t0x0000025a\n R_ARM_REL32\t.bss\n-\t.word\t0x0000018c\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000138\n+\t.word\t0x00000130\n R_ARM_REL32\t.bss\n+\tldr.w\tr9, [pc, #1104]\t@ 3130 <__gridxc_atom_MOD_atomxc+0x3130>\n \tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tldr.w\tsl, [pc, #1068]\t@ 3164 <__gridxc_atom_MOD_atomxc+0x3164>\n-\tsub.w\tr9, r3, #712\t@ 0x2c8\n-\tsub.w\tr3, r3, #692\t@ 0x2b4\n-\tadd\tsl, pc\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n-\tldr.w\tr0, [r7, #244]\t@ 0xf4\n-\tstr.w\tr4, [r9, #32]\n-\tldr.w\tr2, [sl, #456]\t@ 0x1c8\n-\tvst1.32\t{d8}, [r3]\n-\tldr.w\tr3, [sl, #436]\t@ 0x1b4\n-\tldr.w\tfp, [sl, #468]\t@ 0x1d4\n-\tmla\tr5, r2, r1, r3\n-\tldr.w\tr2, [sl, #432]\t@ 0x1b0\n+\tadd\tr9, pc\n+\tldr.w\tr1, [r7, #296]\t@ 0x128\n+\tsub.w\tr5, r3, #712\t@ 0x2c8\n+\tldr.w\tr0, [r7, #248]\t@ 0xf8\n+\tldr.w\tr3, [r9, #436]\t@ 0x1b4\n+\tldr.w\tr2, [r9, #456]\t@ 0x1c8\n+\tstr\tr4, [r5, #32]\n+\tldr.w\tr8, [r9, #468]\t@ 0x1d4\n+\tmla\tr2, r2, r1, r3\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r9, #28]\n+\tstr.w\tr2, [r7, #276]\t@ 0x114\n+\tstrd\tr3, r3, [r5, #24]\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr.w\tr3, [r9, #4]\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n+\tldr.w\tr2, [r9, #432]\t@ 0x1b0\n+\tstr\tr3, [r5, #4]\n+\tmovs\tr3, #8\n+\tstr\tr3, [r5, #20]\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr1, [sl, #452]\t@ 0x1c4\n-\tadd.w\tr3, r5, fp\n-\tldr.w\tr2, [r7, #264]\t@ 0x108\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmov\tsl, r0\n+\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tmov\tip, r0\n+\tldr.w\tr1, [r9, #452]\t@ 0x1c4\n+\tadd.w\tr3, r2, r8\n+\tldr.w\tr2, [r7, #272]\t@ 0x110\n+\tstr\tr0, [r5, #0]\n+\tstr.w\tr0, [r7, #276]\t@ 0x114\n \tmla\tr2, r1, r3, r2\n \tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tmul.w\tr1, fp, r1\n-\tvstr\td16, [r3, #-700]\t@ 0xfffffd44\n-\tmovw\tr3, #769\t@ 0x301\n-\tstrh.w\tr3, [r9, #16]\n+\tmul.w\tr1, r8, r1\n+\tsub.w\tr0, r3, #700\t@ 0x2bc\n \tmovs\tr3, #0\n-\tstr.w\tr0, [r9]\n-\tvldr\td16, [r2]\n+\tstrd\tr3, r3, [r0]\n+\tmovw\tr0, #769\t@ 0x301\n+\tstrh\tr0, [r5, #16]\n+\tmov\tr0, ip\n+\tldrd\tr8, r9, [r2]\n \tmov\tip, r3\n \tadds\tr3, #1\n \tadd\tr2, r1\n \tcmp\tr4, r3\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t2dac <__gridxc_atom_MOD_atomxc+0x2dac>\n-\tvldr\ts15, [pc, #928]\t@ 3160 <__gridxc_atom_MOD_atomxc+0x3160>\n-\tldr\tr0, [pc, #932]\t@ (3168 <__gridxc_atom_MOD_atomxc+0x3168>)\n-\tvcmpe.f32\ts20, s15\n+\tstrd\tr8, r9, [r0], #8\n+\tbne.n\t2d5a <__gridxc_atom_MOD_atomxc+0x2d5a>\n+\tvcmpe.f32\ts16, s17\n+\tldr\tr0, [pc, #960]\t@ (3134 <__gridxc_atom_MOD_atomxc+0x3134>)\n \tadd\tr0, pc\n-\tldrd\tr1, fp, [r0, #528]\t@ 0x210\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t3238 <__gridxc_atom_MOD_atomxc+0x3238>\n+\tldrd\tr1, r8, [r0, #528]\t@ 0x210\n+\tbhi.w\t31d4 <__gridxc_atom_MOD_atomxc+0x31d4>\n \tldr.w\tr2, [r0, #552]\t@ 0x228\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr.w\tr5, [r7, #284]\t@ 0x11c\n+\tldr.w\tr5, [r7, #296]\t@ 0x128\n \tldr.w\tr9, [r0, #548]\t@ 0x224\n-\tstr.w\tr8, [r7, #260]\t@ 0x104\n+\tvldr\td7, [pc, #920]\t@ 3128 <__gridxc_atom_MOD_atomxc+0x3128>\n+\tstr.w\tr4, [r7, #268]\t@ 0x10c\n \tmul.w\tr2, r2, r5\n \tmovs\tr5, #0\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n \tldr.w\tr2, [r0, #564]\t@ 0x234\n-\tldr.w\tr0, [r7, #264]\t@ 0x108\n-\tadd\tr0, fp\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tadd\tr0, r8\n \tadd\tr0, r2\n \tmul.w\tlr, r2, r9\n \tmla\tr0, r9, r0, r1\n \tcmp\tip, r5\n-\tvstr\td16, [r0]\n+\tvstr\td7, [r0]\n \tadd.w\tr5, r5, #1\n \tadd\tr0, lr\n-\tbne.n\t2e08 <__gridxc_atom_MOD_atomxc+0x2e08>\n-\tldr.w\tr0, [r7, #264]\t@ 0x108\n-\tadd\tr2, fp\n-\tldr.w\tr8, [r7, #260]\t@ 0x104\n-\tmov.w\tip, #0\n+\tbne.n\t2db2 <__gridxc_atom_MOD_atomxc+0x2db2>\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tadd\tr2, r8\n+\tldr.w\tr4, [r7, #268]\t@ 0x10c\n+\tmov.w\tr8, #4294967295\t@ 0xffffffff\n \tadd\tr2, r0\n+\tmov.w\tip, #0\n \tmla\tr5, r9, r2, r1\n-\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tldr.w\tr9, [r7, #276]\t@ 0x114\n \tadd.w\tip, ip, #1\n-\tvldr\td16, [r5]\n-\tadd.w\tr0, r6, r9, lsl #3\n-\tmov\tr1, sl\n+\tvldr\td7, [r5]\n+\tadd.w\tr0, r6, r8, lsl #3\n+\tmov\tr1, r9\n \tmovs\tr2, #0\n-\tvldmia\tr1!, {d18}\n+\tvldmia\tr1!, {d5}\n \tadds\tr2, #1\n-\tvldmia\tr0!, {d17}\n-\tcmp\tr8, r2\n-\tvfma.f64\td16, d18, d17\n-\tbgt.n\t2e3e <__gridxc_atom_MOD_atomxc+0x2e3e>\n-\tvstr\td16, [r5]\n-\tadd\tr9, r3\n+\tvldmia\tr0!, {d6}\n+\tcmp\tfp, r2\n+\tvmla.f64\td7, d5, d6\n+\tbgt.n\t2dec <__gridxc_atom_MOD_atomxc+0x2dec>\n+\tvstr\td7, [r5]\n+\tadd\tr8, r3\n \tadd\tr5, lr\n-\tcmp\tr8, ip\n-\tbgt.n\t2e2e <__gridxc_atom_MOD_atomxc+0x2e2e>\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tcbz\tr3, 2e68 <__gridxc_atom_MOD_atomxc+0x2e68>\n+\tcmp\tfp, ip\n+\tbgt.n\t2ddc <__gridxc_atom_MOD_atomxc+0x2ddc>\n+\tldr.w\tr3, [r7, #284]\t@ 0x11c\n+\tcbz\tr3, 2e16 <__gridxc_atom_MOD_atomxc+0x2e16>\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp.w\tsl, #0\n-\tbeq.w\t31da <__gridxc_atom_MOD_atomxc+0x31da>\n-\tmov\tr0, sl\n+\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tcmp\tr3, #0\n+\tbeq.w\t3178 <__gridxc_atom_MOD_atomxc+0x3178>\n+\tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n \tadds\tr2, #1\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr2, [r7, #236]\t@ 0xec\n+\tstr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr2, [r7, #244]\t@ 0xf4\n \tadds\tr3, #8\n-\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n \tcmp\tr3, r2\n-\tbne.w\t2c10 <__gridxc_atom_MOD_atomxc+0x2c10>\n-\tmov\tsl, r4\n-\tcmp.w\tsl, #0\n-\tble.w\t3542 <__gridxc_atom_MOD_atomxc+0x3542>\n-\tldr\tr4, [pc, #716]\t@ (316c <__gridxc_atom_MOD_atomxc+0x316c>)\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tmov.w\tr9, #1\n-\tldr.w\tr5, [r7, #280]\t@ 0x118\n+\tbne.w\t2bc8 <__gridxc_atom_MOD_atomxc+0x2bc8>\n+\tmov\tr8, r4\n+\tldr.w\tsl, [r7, #292]\t@ 0x124\n+\tcmp.w\tr8, #0\n+\tble.w\t3570 <__gridxc_atom_MOD_atomxc+0x3570>\n+\tldr.w\tr9, [pc, #740]\t@ 3138 <__gridxc_atom_MOD_atomxc+0x3138>\n+\tmov.w\tfp, #1\n+\tldr\tr4, [pc, #736]\t@ (313c <__gridxc_atom_MOD_atomxc+0x313c>)\n+\tadd.w\tr3, r7, #360\t@ 0x168\n+\tldr.w\tr5, [r7, #236]\t@ 0xec\n+\tadd\tr9, pc\n \tadd\tr4, pc\n-\tvldr\td8, [pc, #668]\t@ 3150 <__gridxc_atom_MOD_atomxc+0x3150>\n-\tsub.w\tr2, r3, #604\t@ 0x25c\n-\tsub.w\tr3, r3, #588\t@ 0x24c\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tstr.w\tr3, [r7, #272]\t@ 0x110\n-\tadd.w\tr3, r4, #548\t@ 0x224\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tmov.w\tr8, #8\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tmovw\tr6, #769\t@ 0x301\n-\tldr.w\tr0, [r4, #564]\t@ 0x234\n-\tvstr\td9, [r2]\n-\tldr.w\tr2, [r7, #272]\t@ 0x110\n-\tvld1.32\t{d16}, [r3]\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tstr.w\tr9, [r7, #288]\t@ 0x120\n+\tadd.w\tr3, r9, #16\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n \tldr.w\tr3, [r4, #556]\t@ 0x22c\n-\tvst1.32\t{d8}, [r2]\n-\tvmov.32\tr2, d16[1]\n+\tsub.w\tip, sl, #616\t@ 0x268\n+\tldr.w\tr2, [r4, #552]\t@ 0x228\n+\tmovs\tr6, #0\n+\tldr.w\tr1, [r4, #568]\t@ 0x238\n \tnegs\tr3, r3\n-\tnegs\tr1, r2\n+\tldr.w\tr0, [r4, #564]\t@ 0x234\n+\tmovw\tr9, #513\t@ 0x201\n+\tsub.w\tr1, fp, r1\n+\tstr.w\tr2, [ip, #24]\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r4, #568]\t@ 0x238\n-\tsub.w\tr2, r9, r2\n-\tmla\tr3, r0, r2, r3\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tsub.w\tr2, r0, #616\t@ 0x268\n-\tstr\tr1, [r2, #4]\n+\tnegs\tr2, r2\n+\tstr.w\tr2, [ip, #4]\n+\tsub.w\tr2, sl, #604\t@ 0x25c\n+\tmla\tr3, r0, r1, r3\n \tldr.w\tr1, [r4, #528]\t@ 0x210\n-\tadd.w\tfp, r1, r3, lsl #3\n-\tsub.w\tr3, r0, #596\t@ 0x254\n-\tstr.w\tfp, [r2]\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n-\tvst1.32\t{d16}, [r3]\n-\tstr.w\tr8, [r2, #8]\n-\tstrh\tr6, [r2, #16]\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tstr.w\tr3, [ip]\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tmovs\tr1, #8\n+\tldr.w\tr3, [r4, #548]\t@ 0x224\n+\tstr.w\tr3, [ip, #20]\n+\tmovs\tr3, #1\n+\tstrd\tr6, r6, [r2]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstr.w\tr1, [ip, #8]\n+\tstr.w\tr3, [ip, #28]\n+\tstrh.w\tr2, [ip, #16]\n+\tstr.w\tr9, [ip, #32]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr1, [r4, #564]\t@ 0x234\n-\tstr.w\tr8, [r5, #-64]\n-\tmov\tr8, r0\n-\tvstr\td9, [r5, #-60]\t@ 0xffffffc4\n-\tvld1.32\t{d16}, [r3]\n+\tmovs\tr3, #1\n+\tstrd\tr3, r9, [r5, #-44]\t@ 0x2c\n+\tmovw\tr2, #769\t@ 0x301\n \tldr.w\tr3, [r4, #556]\t@ 0x22c\n-\tstrh.w\tr6, [r5, #-56]\n-\tvmov.32\tr2, d16[1]\n+\tmovs\tr1, #8\n+\tstrd\tr6, r6, [r5, #-60]\t@ 0x3c\n+\tmov\tr9, r0\n+\tstrh.w\tr2, [r5, #-56]\n \tnegs\tr3, r3\n-\tldr\tr0, [r7, #104]\t@ 0x68\n+\tldr.w\tr2, [r4, #552]\t@ 0x228\n+\tstr.w\tr2, [r5, #-48]\n+\tstr.w\tr1, [r5, #-64]\n+\tldr.w\tr1, [r4, #564]\t@ 0x234\n \tmul.w\tr3, r2, r3\n \tnegs\tr2, r2\n \tstr.w\tr2, [r5, #-68]\n \tldr.w\tr2, [r4, #568]\t@ 0x238\n-\tsub.w\tr2, r9, r2\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tsub.w\tr2, fp, r2\n \tmla\tr3, r1, r2, r3\n \tldr.w\tr2, [r4, #528]\t@ 0x210\n \tadd.w\tr2, r2, r3, lsl #3\n-\tsub.w\tr3, r5, #44\t@ 0x2c\n+\tldr.w\tr3, [r4, #548]\t@ 0x224\n \tstr.w\tr2, [r5, #-72]\n-\tvst1.32\t{d8}, [r3]\n-\tsub.w\tr3, r5, #52\t@ 0x34\n-\tvst1.32\t{d16}, [r3]\n+\tstr.w\tr3, [r5, #-52]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n \tmov\tr6, r0\n-\tldr\tr0, [pc, #468]\t@ (3170 <__gridxc_atom_MOD_atomxc+0x3170>)\n-\tldr.w\tr2, [r7, #224]\t@ 0xe0\n-\tmov\tr3, r8\n-\tadd\tr0, pc\n-\tadd.w\tr1, r0, #16\n+\tldr.w\tr0, [r7, #288]\t@ 0x120\n+\tmov\tr3, r9\n+\tldrd\tr2, r1, [r7, #292]\t@ 0x124\n \tadds\tr0, #20\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tfp, r8\n-\tbeq.n\t2fb6 <__gridxc_atom_MOD_atomxc+0x2fb6>\n-\tmov\tr0, r8\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tcmp\tr3, r9\n+\tbeq.n\t2f66 <__gridxc_atom_MOD_atomxc+0x2f66>\n+\tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr3, [r5, #-72]\n \tcmp\tr3, r6\n-\tbeq.w\t32c6 <__gridxc_atom_MOD_atomxc+0x32c6>\n-\tldr\tr0, [r7, #104]\t@ 0x68\n+\tbeq.w\t3262 <__gridxc_atom_MOD_atomxc+0x3262>\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tmov\tr1, r6\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tadd.w\tr9, r9, #1\n+\tadd.w\tfp, fp, #1\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tsl, r9\n-\tbge.w\t2ece <__gridxc_atom_MOD_atomxc+0x2ece>\n-\tldr\tr0, [pc, #408]\t@ (3174 <__gridxc_atom_MOD_atomxc+0x3174>)\n+\tcmp\tr8, fp\n+\tbge.w\t2e78 <__gridxc_atom_MOD_atomxc+0x2e78>\n+\tldr\tr0, [pc, #436]\t@ (3140 <__gridxc_atom_MOD_atomxc+0x3140>)\n \tmovs\tr1, #0\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n-\tvmov.i32\td8, #0\t@ 0x00000000\n+\tldr.w\tr3, [r7, #184]\t@ 0xb8\n+\tmov.w\tr9, #1\n \tadd\tr0, pc\n \tstrd\tr1, r1, [sp]\n \tadd.w\tr2, r0, #32\n \tadds\tr0, #24\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n-\tldr.w\tfp, [pc, #384]\t@ 3178 <__gridxc_atom_MOD_atomxc+0x3178>\n-\tmov.w\tr9, #1\n-\tldr.w\tr5, [r7, #280]\t@ 0x118\n+\tldr.w\tr6, [r7, #144]\t@ 0x90\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldr.w\tfp, [pc, #408]\t@ 3144 <__gridxc_atom_MOD_atomxc+0x3144>\n+\tmov.w\tip, r6, lsl #3\n+\tldr.w\tr4, [r7, #236]\t@ 0xec\n \tlsrs\tr3, r3, #31\n-\tstr.w\tr3, [r7, #272]\t@ 0x110\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n \tadd\tfp, pc\n-\tvldr\td10, [pc, #320]\t@ 3150 <__gridxc_atom_MOD_atomxc+0x3150>\n-\tvldr\td9, [pc, #324]\t@ 3158 <__gridxc_atom_MOD_atomxc+0x3158>\n-\tlsls\tr2, r3, #3\n-\tstr.w\tr2, [r7, #268]\t@ 0x10c\n-\tadd.w\tr2, fp, #548\t@ 0x224\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n-\tldr.w\tr2, [r7, #292]\t@ 0x124\n-\tsub.w\tr1, r2, #604\t@ 0x25c\n-\tsub.w\tr2, r2, #588\t@ 0x24c\n-\tstrd\tsl, r2, [r7, #252]\t@ 0xfc\n-\tmov\tsl, r3\n-\tstr.w\tr1, [r7, #260]\t@ 0x104\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tmovw\tr6, #769\t@ 0x301\n-\tldr.w\tr0, [fp, #564]\t@ 0x234\n-\tldr.w\tr4, [fp, #580]\t@ 0x244\n-\tstr.w\tsp, [r7, #288]\t@ 0x120\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r7, #260]\t@ 0x104\n-\tvmov.32\tr2, d16[1]\n-\tvstr\td8, [r3]\n-\tldr.w\tr3, [r7, #256]\t@ 0x100\n-\tnegs\tr1, r2\n-\tvst1.32\t{d10}, [r3]\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tbic.w\tr3, ip, #4080\t@ 0xff0\n+\tbic.w\tr3, r3, #15\n+\tstr.w\tr8, [r7, #276]\t@ 0x114\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tstr.w\tip, [r7, #272]\t@ 0x110\n \tldr.w\tr3, [fp, #556]\t@ 0x22c\n+\tsub.w\tip, sl, #616\t@ 0x268\n+\tldr.w\tr2, [fp, #552]\t@ 0x228\n+\tmovw\tr5, #769\t@ 0x301\n+\tldr.w\tr1, [fp, #568]\t@ 0x238\n \tnegs\tr3, r3\n+\tldr.w\tr0, [fp, #564]\t@ 0x234\n+\tmovw\tlr, #513\t@ 0x201\n+\tsub.w\tr1, r9, r1\n+\tstr.w\tr2, [ip, #24]\n \tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [fp, #568]\t@ 0x238\n-\tsub.w\tr2, r9, r2\n-\tmla\tr3, r0, r2, r3\n-\tldr.w\tr0, [r7, #292]\t@ 0x124\n-\tsub.w\tr2, r0, #616\t@ 0x268\n-\tstr\tr1, [r2, #4]\n-\tldr.w\tr1, [fp, #528]\t@ 0x210\n-\tadd.w\tr8, r1, r3, lsl #3\n-\tsub.w\tr3, r0, #596\t@ 0x254\n-\tstr.w\tr8, [r2]\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n-\tvst1.32\t{d16}, [r3]\n+\tnegs\tr2, r2\n+\tstr.w\tr2, [ip, #4]\n+\tmla\tr3, r0, r1, r3\n+\tldr.w\tr2, [fp, #528]\t@ 0x210\n+\tsub.w\tr1, sl, #604\t@ 0x25c\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n+\tstr.w\tsp, [r7, #296]\t@ 0x128\n+\tadd.w\tr8, r2, r3, lsl #3\n+\tldr.w\tr3, [fp, #548]\t@ 0x224\n+\tmovs\tr2, #0\n+\tstr.w\tr3, [ip, #20]\n+\tstr.w\tr8, [ip]\n \tmovs\tr3, #8\n-\tstrh\tr6, [r2, #16]\n-\tstr\tr3, [r2, #8]\n+\tstrd\tr2, r2, [r1]\n+\tmovs\tr1, #1\n+\tstr.w\tr3, [ip, #8]\n \tldr.w\tr3, [fp, #576]\t@ 0x240\n-\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tstr.w\tr1, [ip, #28]\n+\tstrh.w\tr5, [ip, #16]\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tstr.w\tlr, [ip, #32]\n+\tldr.w\tr3, [fp, #580]\t@ 0x244\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tmovs\tr3, #8\n-\tstr.w\tr3, [r5, #-64]\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr.w\tr3, [r4, #-64]\n+\tstr.w\tr3, [r4, #-52]\n \tmovs\tr2, #0\n-\tstr.w\tr3, [r5, #-40]\n-\tsub.w\tr3, r5, #52\t@ 0x34\n-\tvstr\td8, [r5, #-60]\t@ 0xffffffc4\n-\tstrh.w\tr6, [r5, #-56]\n-\tmov\tr6, r0\n-\tvst1.32\t{d9}, [r3]\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n-\tstr.w\tr2, [r5, #-44]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tmovs\tr1, #1\n+\tstr.w\tr3, [r4, #-40]\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n+\tstr.w\tr2, [r4, #-56]\n+\tstr.w\tr1, [r4, #-48]\n+\tstrh.w\tr5, [r4, #-56]\n+\tmov\tr5, r0\n+\tstr.w\tr2, [r4, #-60]\n+\tstr.w\tr2, [r4, #-44]\n \tcmp\tr3, #0\n-\tbne.w\t32d2 <__gridxc_atom_MOD_atomxc+0x32d2>\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tmov\tr1, sp\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n-\tbeq.n\t3102 <__gridxc_atom_MOD_atomxc+0x3102>\n+\tbne.w\t326e <__gridxc_atom_MOD_atomxc+0x326e>\n+\tldr.w\tr3, [r7, #284]\t@ 0x11c\n+\tmov\tr2, sp\n+\tsub.w\tr3, sp, r3\n+\tcmp\tr2, r3\n+\tbeq.n\t30a2 <__gridxc_atom_MOD_atomxc+0x30a2>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n+\tmov\tr2, sp\n+\tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t30f4 <__gridxc_atom_MOD_atomxc+0x30f4>\n+\tbne.n\t3094 <__gridxc_atom_MOD_atomxc+0x3094>\n+\tldr.w\tr3, [r7, #272]\t@ 0x110\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t3334 <__gridxc_atom_MOD_atomxc+0x3334>\n-\tldr\tr3, [pc, #104]\t@ (317c <__gridxc_atom_MOD_atomxc+0x317c>)\n+\tbne.w\t32d8 <__gridxc_atom_MOD_atomxc+0x32d8>\n+\tldr\tr3, [pc, #144]\t@ (3148 <__gridxc_atom_MOD_atomxc+0x3148>)\n \tmovs\tr2, #0\n \tadd\tr1, sp, #48\t@ 0x30\n-\tstr.w\tr2, [r5, #-68]\n-\tstr.w\tr1, [r5, #-72]\n+\tstr.w\tr2, [r4, #-68]\n+\tstr.w\tr1, [r4, #-72]\n \tadd\tr3, pc\n \tstrd\tr2, r2, [sp, #4]\n \tadds\tr3, #24\n-\tstr\tr6, [sp, #0]\n-\tldr\tr0, [r7, #104]\t@ 0x68\n-\tldrd\tr2, r1, [r7, #228]\t@ 0xe4\n+\tstr\tr5, [sp, #0]\n+\tldr.w\tr2, [r7, #240]\t@ 0xf0\n+\tldr.w\tr1, [r7, #256]\t@ 0x100\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tbl\t0 <__gridxc_mesh1d_MOD_interpolation_local>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_interpolation_local\n-\tcmp\tr8, r6\n-\tbne.w\t331c <__gridxc_atom_MOD_atomxc+0x331c>\n-\tldr\tr3, [pc, #68]\t@ (3180 <__gridxc_atom_MOD_atomxc+0x3180>)\n-\tadd\tr3, pc\n-\tldr.w\tr2, [r3, #612]\t@ 0x264\n-\tmla\tr4, r2, r9, r4\n-\tldr.w\tr2, [r3, #600]\t@ 0x258\n-\tb.n\t3184 <__gridxc_atom_MOD_atomxc+0x3184>\n+\tcmp\tr8, r5\n+\tbne.w\t32bc <__gridxc_atom_MOD_atomxc+0x32bc>\n+\tldr\tr2, [pc, #104]\t@ (314c <__gridxc_atom_MOD_atomxc+0x314c>)\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n+\tadd\tr2, pc\n+\tldr.w\tr3, [r2, #612]\t@ 0x264\n+\tldr.w\tr2, [r2, #600]\t@ 0x258\n+\tmla\tr3, r3, r9, r1\n+\tldr\tr1, [pc, #88]\t@ (3150 <__gridxc_atom_MOD_atomxc+0x3150>)\n+\tadd\tr3, r2\n+\tmov\tr5, r9\n+\tadd\tr1, pc\n+\tldr.w\tr0, [r1, #596]\t@ 0x254\n+\tldr.w\tr1, [r7, #292]\t@ 0x124\n+\tmla\tr3, r0, r3, r1\n+\tldr.w\tr1, [r4, #-72]\n+\tmul.w\tr0, r2, r0\n+\tmovs\tr2, #0\n+\tldrd\tr8, r9, [r1], #8\n+\tadds\tr2, #1\n+\tstrd\tr8, r9, [r3]\n+\tcmp\tr6, r2\n+\tadd\tr3, r0\n+\tbne.n\t3112 <__gridxc_atom_MOD_atomxc+0x3112>\n+\tmov\tr9, r5\n+\tb.n\t3154 <__gridxc_atom_MOD_atomxc+0x3154>\n \tnop\n-\tnop.w\n-\t.word\t0x00000001\n-\t.word\t0x00000201\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x44610000\n-\t.word\t0x00000420\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000039c\n+\t...\n+\t.word\t0x00000448\n R_ARM_REL32\t.bss\n-\t.word\t0x000002b8\n+\t.word\t0x000003be\n R_ARM_REL32\t.bss\n-\t.word\t0x000001cc\n+\t.word\t0x000002d0\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000018c\n+\t.word\t0x000002d2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001a8\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000168\n+\t.word\t0x00000188\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n+\t.word\t0x00000082\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000042\n+\t.word\t0x00000062\n R_ARM_REL32\t.bss\n-\tldr\tr3, [pc, #1004]\t@ (3574 <__gridxc_atom_MOD_atomxc+0x3574>)\n-\tadd\tr4, r2\n-\tldr.w\tr1, [r5, #-72]\n-\tmov\tr6, r5\n-\tadd\tr3, pc\n-\tldr.w\tr0, [r3, #596]\t@ 0x254\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tmla\tr3, r0, r4, r3\n-\tmul.w\tr0, r2, r0\n-\tmovs\tr2, #0\n-\tldrd\tr4, r5, [r1], #8\n-\tadds\tr2, #1\n-\tstrd\tr4, r5, [r3]\n-\tcmp\tsl, r2\n-\tadd\tr3, r0\n-\tbne.n\t31a2 <__gridxc_atom_MOD_atomxc+0x31a2>\n-\tmov\tr5, r6\n-\tldr.w\tr3, [r7, #252]\t@ 0xfc\n+\t.word\t0x00000052\n+ R_ARM_REL32\t.bss\n+\tldr.w\tr3, [r7, #276]\t@ 0x114\n \tadd.w\tr9, r9, #1\n-\tldr.w\tsp, [r7, #288]\t@ 0x120\n-\tcmp\tr9, r3\n-\tble.w\t303a <__gridxc_atom_MOD_atomxc+0x303a>\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tmovs\tr6, #1\n-\tsubw\tr3, r3, #1436\t@ 0x59c\n+\tldr.w\tsp, [r7, #296]\t@ 0x128\n+\tcmp\tr3, r9\n+\tbge.w\t2fd2 <__gridxc_atom_MOD_atomxc+0x2fd2>\n+\tsubw\tr3, sl, #1428\t@ 0x594\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #152]\t@ 0x98\n-\tb.w\ta44 <__gridxc_atom_MOD_atomxc+0xa44>\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr3, [r7, #160]\t@ 0xa0\n+\tmovs\tr3, #1\n+\tstr\tr3, [r7, #100]\t@ 0x64\n+\tb.w\ta4a <__gridxc_atom_MOD_atomxc+0xa4a>\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n \tadds\tr2, #1\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tldr.w\tr2, [r7, #236]\t@ 0xec\n+\tstr.w\tr2, [r7, #296]\t@ 0x128\n+\tldr.w\tr2, [r7, #244]\t@ 0xf4\n \tadds\tr3, #8\n-\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n \tcmp\tr2, r3\n-\tbne.w\t2c10 <__gridxc_atom_MOD_atomxc+0x2c10>\n-\tb.n\t2e94 <__gridxc_atom_MOD_atomxc+0x2e94>\n-\tstrd\tr5, r4, [r9, #28]\n-\tldr.w\tr5, [r7, #292]\t@ 0x124\n-\tldr.w\tr0, [r7, #244]\t@ 0xf4\n-\tsub.w\tr3, r5, #692\t@ 0x2b4\n-\tvst1.32\t{d8}, [r3]\n+\tbne.w\t2bc8 <__gridxc_atom_MOD_atomxc+0x2bc8>\n+\tb.n\t2e44 <__gridxc_atom_MOD_atomxc+0x2e44>\n+\tstr.w\tr3, [r8, #20]\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr.w\tr3, [r9, #4]\n+\tldr.w\tr0, [r7, #248]\t@ 0xf8\n+\tstr.w\tr3, [r8, #4]\n+\tstrd\tr9, r9, [r8, #24]\n+\tstr.w\tr4, [r8, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tvldr\ts15, [pc, #852]\t@ 3570 <__gridxc_atom_MOD_atomxc+0x3570>\n-\tvstr\td11, [r5, #-700]\t@ 0xfffffd44\n-\tstrh.w\tsl, [r9, #16]\n-\tmov\tsl, r0\n-\tvcmpe.f32\ts20, s15\n-\tstr.w\tr0, [r9]\n+\tvcmpe.f32\ts16, s17\n+\tstrd\tr5, r5, [r6]\n+\tmovw\tr3, #769\t@ 0x301\n+\tstr.w\tr0, [r7, #276]\t@ 0x114\n+\tstrh.w\tr3, [r8, #16]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\t2e5c <__gridxc_atom_MOD_atomxc+0x2e5c>\n-\tldr\tr6, [pc, #828]\t@ (3578 <__gridxc_atom_MOD_atomxc+0x3578>)\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tstr.w\tr0, [r8]\n+\tbls.w\t2e0a <__gridxc_atom_MOD_atomxc+0x2e0a>\n \tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tmov.w\tfp, #0\n-\tadd\tr6, pc\n+\tmov.w\tr9, #0\n+\tldr\tr6, [pc, #944]\t@ (3590 <__gridxc_atom_MOD_atomxc+0x3590>)\n \tadd.w\tr1, r7, #1032\t@ 0x408\n \tsub.w\tr5, r3, #616\t@ 0x268\n-\tvstr\td16, [r3, #-604]\t@ 0xfffffda4\n+\tsub.w\tr3, r3, #604\t@ 0x25c\n+\tadd\tr6, pc\n+\tstrd\tr9, r9, [r5]\n+\tstrd\tr9, r9, [r3]\n \tldr.w\tr3, [r6, #528]\t@ 0x210\n-\tldr.w\tr9, [r6, #532]\t@ 0x214\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n+\tldr.w\tr8, [r6, #532]\t@ 0x214\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n \tmovs\tr3, #8\n-\tstrd\tfp, fp, [r5]\n \tstr\tr3, [r5, #8]\n \tstr\tr3, [r5, #20]\n \tmovw\tr3, #769\t@ 0x301\n \tstrh\tr3, [r5, #16]\n-\tmov\tr3, fp\n-\tstrd\tfp, fp, [sp]\n-\tldr\tr2, [r7, #104]\t@ 0x68\n-\tldr\tr0, [r7, #92]\t@ 0x5c\n+\tmov\tr3, r9\n+\tstrd\tr9, r9, [sp]\n+\tldr\tr2, [r7, #112]\t@ 0x70\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n \tbl\t0 <_gfortran_matmul_r8>\n R_ARM_THM_CALL\t_gfortran_matmul_r8\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n \tldr.w\tr0, [r6, #552]\t@ 0x228\n \tldr.w\tr3, [r6, #564]\t@ 0x234\n-\tmla\tr0, r0, r2, r9\n+\tmla\tr0, r0, r2, r8\n \tldrd\tr2, r1, [r5, #28]\n \tsubs.w\tip, r1, r2\n-\tbmi.n\t3314 <__gridxc_atom_MOD_atomxc+0x3314>\n+\tbmi.n\t32b4 <__gridxc_atom_MOD_atomxc+0x32b4>\n \tldr.w\tr1, [r6, #548]\t@ 0x224\n \tadds\tr2, r3, r0\n-\tldr.w\tr0, [r7, #264]\t@ 0x108\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n \tmla\tr2, r1, r2, r0\n \tldr\tr0, [r5, #0]\n \tmul.w\tr1, r3, r1\n \tmov\tr5, r0\n-\tvldmia\tr5!, {d16}\n-\tcmp\tfp, ip\n-\tadd.w\tfp, fp, #1\n-\tvstr\td16, [r2]\n+\tvldmia\tr5!, {d7}\n+\tcmp\tip, r9\n+\tadd.w\tr9, r9, #1\n+\tvstr\td7, [r2]\n \tadd\tr2, r1\n-\tbne.n\t32ae <__gridxc_atom_MOD_atomxc+0x32ae>\n+\tbne.n\t324a <__gridxc_atom_MOD_atomxc+0x324a>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t2e5c <__gridxc_atom_MOD_atomxc+0x2e5c>\n-\tadd.w\tr9, r9, #1\n-\tcmp\tr9, sl\n-\tble.w\t2ece <__gridxc_atom_MOD_atomxc+0x2ece>\n-\tb.n\t2fd8 <__gridxc_atom_MOD_atomxc+0x2fd8>\n-\tldr\tr3, [pc, #680]\t@ (357c <__gridxc_atom_MOD_atomxc+0x357c>)\n+\tb.n\t2e0a <__gridxc_atom_MOD_atomxc+0x2e0a>\n+\tadd.w\tfp, fp, #1\n+\tcmp\tr8, fp\n+\tbge.w\t2e78 <__gridxc_atom_MOD_atomxc+0x2e78>\n+\tb.n\t2f88 <__gridxc_atom_MOD_atomxc+0x2f88>\n+\tldr\tr3, [pc, #804]\t@ (3594 <__gridxc_atom_MOD_atomxc+0x3594>)\n \tadd.w\tr1, r7, #1032\t@ 0x408\n-\tstr.w\tr2, [r5, #-68]\n-\tstr.w\tr1, [r5, #-72]\n+\tstr.w\tr2, [r4, #-68]\n+\tstr.w\tr1, [r4, #-72]\n \tadd\tr3, pc\n \tstrd\tr2, r2, [sp, #4]\n \tadds\tr3, #24\n \tstr\tr0, [sp, #0]\n-\tldr\tr0, [r7, #104]\t@ 0x68\n-\tldrd\tr2, r1, [r7, #228]\t@ 0xe4\n+\tldr.w\tr2, [r7, #240]\t@ 0xf0\n+\tldr.w\tr1, [r7, #256]\t@ 0x100\n+\tldr\tr0, [r7, #112]\t@ 0x70\n \tbl\t0 <__gridxc_mesh1d_MOD_interpolation_local>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_interpolation_local\n-\tcmp\tr8, r6\n-\tbeq.w\t31b4 <__gridxc_atom_MOD_atomxc+0x31b4>\n-\tmov\tr0, r6\n+\tcmp\tr8, r5\n+\tbeq.w\t3154 <__gridxc_atom_MOD_atomxc+0x3154>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t31b4 <__gridxc_atom_MOD_atomxc+0x31b4>\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr3, r8\n-\tbge.w\t26f0 <__gridxc_atom_MOD_atomxc+0x26f0>\n-\tb.w\t2890 <__gridxc_atom_MOD_atomxc+0x2890>\n+\tb.n\t3154 <__gridxc_atom_MOD_atomxc+0x3154>\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tadd.w\tr9, r9, #1\n+\tcmp\tr3, r9\n+\tbge.w\t26b8 <__gridxc_atom_MOD_atomxc+0x26b8>\n+\tb.w\t285e <__gridxc_atom_MOD_atomxc+0x285e>\n \tldr\tr0, [r5, #0]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t2e5c <__gridxc_atom_MOD_atomxc+0x2e5c>\n-\tmov\tr0, r6\n+\tb.n\t2e0a <__gridxc_atom_MOD_atomxc+0x2e0a>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #604]\t@ (3580 <__gridxc_atom_MOD_atomxc+0x3580>)\n-\tadd\tr3, pc\n-\tldr.w\tr2, [r3, #612]\t@ 0x264\n-\tmla\tr4, r2, r9, r4\n-\tldr.w\tr2, [r3, #600]\t@ 0x258\n-\tb.n\t3184 <__gridxc_atom_MOD_atomxc+0x3184>\n+\tldr\tr2, [pc, #724]\t@ (3598 <__gridxc_atom_MOD_atomxc+0x3598>)\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n+\tadd\tr2, pc\n+\tldr.w\tr3, [r2, #612]\t@ 0x264\n+\tldr.w\tr2, [r2, #600]\t@ 0x258\n+\tmla\tr3, r3, r9, r1\n+\tb.n\t30f4 <__gridxc_atom_MOD_atomxc+0x30f4>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t3110 <__gridxc_atom_MOD_atomxc+0x3110>\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tcmp\tr3, #0\n-\tble.w\tf38 <__gridxc_atom_MOD_atomxc+0xf38>\n+\tb.n\t30b4 <__gridxc_atom_MOD_atomxc+0x30b4>\n \tldr\tr3, [r7, #100]\t@ 0x64\n-\tlsls\tr3, r3, #3\n-\tstr.w\tr3, [r7, #272]\t@ 0x110\n-\tb.w\taa2 <__gridxc_atom_MOD_atomxc+0xaa2>\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n \tcmp\tr3, #0\n-\tbgt.w\tf40 <__gridxc_atom_MOD_atomxc+0xf40>\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tldr\tr0, [r7, #72]\t@ 0x48\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tldr\tr0, [r7, #80]\t@ 0x50\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tb.w\tf8a <__gridxc_atom_MOD_atomxc+0xf8a>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvldr\td18, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvadd.f64\td18, d18, d18\n-\tvldr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvadd.f64\td16, d16, d16\n-\tvldr\td17, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvadd.f64\td17, d17, d17\n-\tvldr\td19, [r3]\n-\tvadd.f64\td19, d19, d19\n-\tcmp\tr6, #0\n-\tbne.w\t2150 <__gridxc_atom_MOD_atomxc+0x2150>\n-\tldr.w\tr3, [r7, #196]\t@ 0xc4\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tvstr\td19, [r3]\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n-\tvstr\td16, [r3]\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tvstr\td17, [r3]\n-\tb.w\t10ac <__gridxc_atom_MOD_atomxc+0x10ac>\n-\tcmp\tr6, #0\n-\tbeq.w\ta44 <__gridxc_atom_MOD_atomxc+0xa44>\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tbeq.w\ta4a <__gridxc_atom_MOD_atomxc+0xa4a>\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n \tmov\tr1, r4\n \tadd.w\tr6, r8, #16\n-\tsubs\tr3, #32\n+\tsubs\tr3, #24\n \tmov\tr0, r3\n \tmov\tfp, r3\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_get_qmesh>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_get_qmesh\n-\tmovs\tr3, #11\n+\tstrd\tr5, r4, [sp, #20]\n \tstrd\tr4, r4, [sp, #12]\n-\tmov\tr2, fp\n-\tstrd\tr3, r4, [sp, #20]\n \tmov\tr1, r8\n \tstr\tr4, [sp, #8]\n+\tmov\tr2, fp\n+\tldr\tr3, [pc, #656]\t@ (359c <__gridxc_atom_MOD_atomxc+0x359c>)\n \tadd.w\tr0, r9, #228\t@ 0xe4\n-\tldr\tr3, [pc, #392]\t@ (3584 <__gridxc_atom_MOD_atomxc+0x3584>)\n-\tldr.w\tr5, [r7, #204]\t@ 0xcc\n+\tldr.w\tr5, [r7, #220]\t@ 0xdc\n \tadd\tr3, pc\n \tstr\tr5, [sp, #0]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #12\n \tstr\tr3, [sp, #28]\n-\tmov\tr2, sl\n-\tldr\tr3, [pc, #372]\t@ (3588 <__gridxc_atom_MOD_atomxc+0x3588>)\n \tmov\tr1, r8\n+\tldr\tr3, [pc, #632]\t@ (35a0 <__gridxc_atom_MOD_atomxc+0x35a0>)\n \tadd.w\tr0, r9, #276\t@ 0x114\n-\tstrd\tr8, r5, [sp, #4]\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n \tadd\tr3, pc\n-\tstr\tr4, [sp, #32]\n+\tstrd\tr8, r5, [sp, #4]\n \tstr\tr3, [sp, #12]\n \tmov\tr3, r8\n-\tstrd\tr4, r4, [sp, #20]\n+\tstr\tr4, [sp, #32]\n \tadd.w\tr5, r8, #20\n+\tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr3, [pc, #336]\t@ (358c <__gridxc_atom_MOD_atomxc+0x358c>)\n-\tmov\tr2, fp\n+\tldr\tr3, [pc, #596]\t@ (35a4 <__gridxc_atom_MOD_atomxc+0x35a4>)\n \tmov\tr1, r8\n+\tmov\tr2, fp\n \tadd\tr3, pc\n \tadd.w\tr0, r9, #336\t@ 0x150\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #13\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r8\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n \tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr3, [pc, #304]\t@ (3590 <__gridxc_atom_MOD_atomxc+0x3590>)\n-\tmov\tr2, fp\n+\tldr\tr3, [pc, #564]\t@ (35a8 <__gridxc_atom_MOD_atomxc+0x35a8>)\n \tmov\tr1, r8\n+\tmov\tr2, fp\n \tadd\tr3, pc\n \tadd.w\tr0, r9, #384\t@ 0x180\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #10\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r8\n@@ -4398,190 +4320,227 @@\n \tstr\tr4, [sp, #8]\n \tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #9\n \tstrd\tr4, r3, [sp, #16]\n \tmov\tr2, r6\n-\tldr\tr3, [pc, #264]\t@ (3594 <__gridxc_atom_MOD_atomxc+0x3594>)\n+\tldr\tr3, [pc, #524]\t@ (35ac <__gridxc_atom_MOD_atomxc+0x35ac>)\n \tmov\tr1, r5\n \tadd.w\tr0, r9, #432\t@ 0x1b0\n \tstr\tr4, [sp, #24]\n \tadd\tr3, pc\n \tstrd\tr4, r4, [sp, #8]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r8\n \tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #9\n \tstrd\tr4, r3, [sp, #16]\n \tmov\tr1, r8\n-\tldr\tr3, [pc, #232]\t@ (3598 <__gridxc_atom_MOD_atomxc+0x3598>)\n+\tldr\tr3, [pc, #492]\t@ (35b0 <__gridxc_atom_MOD_atomxc+0x35b0>)\n \tadd.w\tr0, r9, #480\t@ 0x1e0\n \tstrd\tr4, r4, [sp, #8]\n \tadd\tr3, pc\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r8\n \tstr.w\tfp, [sp]\n-\tldr.w\tsl, [r7, #232]\t@ 0xe8\n-\tmov\tr2, sl\n+\tldr.w\tr2, [r7, #256]\t@ 0x100\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #9\n \tstrd\tr4, r3, [sp, #16]\n \tmov\tr2, r6\n-\tldr\tr3, [pc, #196]\t@ (359c <__gridxc_atom_MOD_atomxc+0x359c>)\n+\tldr\tr3, [pc, #456]\t@ (35b4 <__gridxc_atom_MOD_atomxc+0x35b4>)\n \tmov\tr1, r5\n \tadd.w\tr0, r9, #528\t@ 0x210\n \tstr\tr4, [sp, #24]\n \tadd\tr3, pc\n \tstrd\tr4, r4, [sp, #8]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r8\n \tstr.w\tfp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #9\n \tstr\tr3, [sp, #20]\n-\tmov\tr2, sl\n-\tldr\tr3, [pc, #168]\t@ (35a0 <__gridxc_atom_MOD_atomxc+0x35a0>)\n-\tadd.w\tr0, r9, #576\t@ 0x240\n \tmov\tr1, r8\n-\tstr.w\tfp, [sp]\n+\tldr\tr3, [pc, #428]\t@ (35b8 <__gridxc_atom_MOD_atomxc+0x35b8>)\n+\tadd.w\tr0, r9, #576\t@ 0x240\n+\tstrd\tr4, r4, [sp, #12]\n \tadd\tr3, pc\n-\tstr\tr4, [sp, #24]\n+\tstr.w\tfp, [sp]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r8\n-\tstrd\tr4, r4, [sp, #12]\n+\tstr\tr4, [sp, #24]\n \tstr\tr4, [sp, #8]\n+\tldr.w\tr2, [r7, #256]\t@ 0x100\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n-\tldr.w\tr1, [r7, #224]\t@ 0xe0\n+\tldr.w\tr1, [r7, #180]\t@ 0xb4\n \tmovs\tr2, #0\n-\tsub.w\tr0, r3, #56\t@ 0x38\n \tmovs\tr3, #0\n \tmovt\tr3, #16436\t@ 0x4034\n-\tstrd\tr2, r3, [r1, #-8]\n+\tsub.w\tr0, r1, #48\t@ 0x30\n+\tstrd\tr2, r3, [r1, #-48]\t@ 0x30\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_kcut>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_kcut\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tsub.w\tr3, r3, #1440\t@ 0x5a0\n-\tldr.w\tsl, [r3]\n-\tvdup.32\td9, sl\n-\tb.w\t2894 <__gridxc_atom_MOD_atomxc+0x2894>\n-\tldr\tr0, [pc, #96]\t@ (35a4 <__gridxc_atom_MOD_atomxc+0x35a4>)\n-\tmovs\tr1, #0\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n-\tmovs\tr6, #1\n-\tadd\tr0, pc\n-\tstrd\tr1, r1, [sp]\n-\tadd.w\tr2, r0, #32\n-\tadds\tr0, #24\n-\tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n- R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tb.w\ta44 <__gridxc_atom_MOD_atomxc+0xa44>\n-\tmov\tr4, r0\n-\tldr\tr1, [pc, #68]\t@ (35a8 <__gridxc_atom_MOD_atomxc+0x35a8>)\n+\tsub.w\tr3, sl, #1432\t@ 0x598\n+\tldr.w\tr8, [r3]\n+\tb.w\t2862 <__gridxc_atom_MOD_atomxc+0x2862>\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tcmp\tr3, #0\n+\tble.w\tf22 <__gridxc_atom_MOD_atomxc+0xf22>\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tlsls\tr3, r3, #3\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tb.w\taa8 <__gridxc_atom_MOD_atomxc+0xaa8>\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n+\tcmp\tr3, #0\n+\tbgt.w\tf2a <__gridxc_atom_MOD_atomxc+0xf2a>\n+\tldr\tr0, [r7, #88]\t@ 0x58\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tldr\tr0, [r7, #92]\t@ 0x5c\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tb.w\tf74 <__gridxc_atom_MOD_atomxc+0xf74>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvldr\td4, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvadd.f64\td4, d4, d4\n+\tvldr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvadd.f64\td5, d5, d5\n+\tvldr\td6, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvadd.f64\td6, d6, d6\n+\tvldr\td7, [r3]\n+\tldr\tr3, [r7, #100]\t@ 0x64\n+\tvadd.f64\td7, d7, d7\n+\tcmp\tr3, #0\n+\tbne.w\t20fc <__gridxc_atom_MOD_atomxc+0x20fc>\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #208]\t@ 0xd0\n+\tvstr\td7, [r3]\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tvstr\td5, [r3]\n+\tldr.w\tr3, [r7, #200]\t@ 0xc8\n+\tvstr\td6, [r3]\n+\tb.w\t1094 <__gridxc_atom_MOD_atomxc+0x1094>\n+\tbl\t0 <__stack_chk_fail>\n+ R_ARM_THM_CALL\t__stack_chk_fail\n+\tmovs\tr3, #20\n+\tstr\tr3, [sp, #0]\n+\tldr\tr3, [pc, #208]\t@ (35bc <__gridxc_atom_MOD_atomxc+0x35bc>)\n+\tadd.w\tr1, r7, #13952\t@ 0x3680\n+\tadds\tr1, #20\n+\tstr\tr4, [sp, #4]\n+\tadd\tr3, pc\n+\tstr.w\tr1, [r7, #300]\t@ 0x12c\n+\tmovs\tr2, #33\t@ 0x21\n+\tmovs\tr0, #53\t@ 0x35\n+\tbl\t0 <_gfortran_concat_string>\n+ R_ARM_THM_CALL\t_gfortran_concat_string\n+\tldr\tr3, [pc, #188]\t@ (35c0 <__gridxc_atom_MOD_atomxc+0x35c0>)\n+\tldr.w\tr1, [r7, #300]\t@ 0x12c\n+\tmov\tr0, r1\n+\tmovs\tr1, #53\t@ 0x35\n+\tldr.w\tr3, [fp, r3]\n+\tldr\tr3, [r3, #0]\n+\tblx\tr3\n+\tb.w\t2e8 <__gridxc_atom_MOD_atomxc+0x2e8>\n+\tldr\tr4, [r7, #92]\t@ 0x5c\n+\tldr\tr1, [pc, #168]\t@ (35c4 <__gridxc_atom_MOD_atomxc+0x35c4>)\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #68]\t@ (35ac <__gridxc_atom_MOD_atomxc+0x35ac>)\n+\tldr\tr0, [pc, #168]\t@ (35c8 <__gridxc_atom_MOD_atomxc+0x35c8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\t.word\t0x44610000\n-\t.word\t0x000003e2\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000032e\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000298\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000258\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000180\n- R_ARM_REL32\t.LC25\n-\t.word\t0x00000166\n- R_ARM_REL32\t.LC26\n-\t.word\t0x0000014a\n- R_ARM_REL32\t.LC27\n-\t.word\t0x0000012a\n- R_ARM_REL32\t.LC28\n-\t.word\t0x000000fe\n- R_ARM_REL32\t.LC31\n-\t.word\t0x000000de\n- R_ARM_REL32\t.LC32\n-\t.word\t0x000000ba\n- R_ARM_REL32\t.LC33\n-\t.word\t0x0000009a\n- R_ARM_REL32\t.LC34\n-\t.word\t0x00000054\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000003c\n- R_ARM_REL32\t.LC10\n-\t.word\t0x0000003e\n- R_ARM_REL32\t.LC12\n \tmov\tr4, r0\n-\tldr\tr1, [pc, #128]\t@ (3634 <__gridxc_atom_MOD_atomxc+0x3634>)\n+\tldr\tr1, [pc, #160]\t@ (35cc <__gridxc_atom_MOD_atomxc+0x35cc>)\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #128]\t@ (3638 <__gridxc_atom_MOD_atomxc+0x3638>)\n+\tldr\tr0, [pc, #160]\t@ (35d0 <__gridxc_atom_MOD_atomxc+0x35d0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr4, [r7, #80]\t@ 0x50\n-\tldr\tr1, [pc, #120]\t@ (363c <__gridxc_atom_MOD_atomxc+0x363c>)\n+\tmov\tr4, r0\n+\tldr\tr1, [pc, #152]\t@ (35d4 <__gridxc_atom_MOD_atomxc+0x35d4>)\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #120]\t@ (3640 <__gridxc_atom_MOD_atomxc+0x3640>)\n+\tldr\tr0, [pc, #152]\t@ (35d8 <__gridxc_atom_MOD_atomxc+0x35d8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tbl\t0 <__stack_chk_fail>\n- R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovs\tr3, #20\n-\tadd.w\tfp, r7, #13952\t@ 0x3680\n-\tstr\tr3, [sp, #0]\n-\tadd.w\tfp, fp, #20\n-\tldr\tr3, [pc, #96]\t@ (3644 <__gridxc_atom_MOD_atomxc+0x3644>)\n-\tmov\tr1, fp\n-\tmovs\tr2, #33\t@ 0x21\n-\tmovs\tr0, #53\t@ 0x35\n-\tadd\tr3, pc\n-\tstr\tr4, [sp, #4]\n-\tbl\t0 <_gfortran_concat_string>\n- R_ARM_THM_CALL\t_gfortran_concat_string\n-\tldr\tr3, [pc, #84]\t@ (3648 <__gridxc_atom_MOD_atomxc+0x3648>)\n-\tmov\tr0, fp\n-\tmovs\tr1, #53\t@ 0x35\n-\tldr.w\tr3, [sl, r3]\n-\tldr\tr3, [r3, #0]\n-\tblx\tr3\n-\tb.w\t2b8 <__gridxc_atom_MOD_atomxc+0x2b8>\n-\tmov\tr6, r4\n-\tb.w\ta44 <__gridxc_atom_MOD_atomxc+0xa44>\n-\tldr\tr3, [r7, #108]\t@ 0x6c\n+\tstr\tr5, [r7, #100]\t@ 0x64\n+\tb.w\ta4a <__gridxc_atom_MOD_atomxc+0xa4a>\n+\tldr.w\tr1, [r7, #180]\t@ 0xb4\n \tmovs\tr2, #0\n-\tsub.w\tr1, r3, #48\t@ 0x30\n-\tsub.w\tr0, r3, #56\t@ 0x38\n-\tstr.w\tr1, [r7, #224]\t@ 0xe0\n \tmovs\tr3, #0\n \tmovt\tr3, #16436\t@ 0x4034\n-\tstrd\tr2, r3, [r1, #-8]\n-\tb.w\t26b6 <__gridxc_atom_MOD_atomxc+0x26b6>\n-\tadd.w\tr3, r7, #360\t@ 0x168\n-\tstr.w\tr3, [r7, #220]\t@ 0xdc\n-\tb.w\t2bbe <__gridxc_atom_MOD_atomxc+0x2bbe>\n-\tnop\n-\t.word\t0x00000078\n- R_ARM_REL32\t.LC10\n-\t.word\t0x0000007a\n- R_ARM_REL32\t.LC12\n-\t.word\t0x00000070\n- R_ARM_REL32\t.LC10\n-\t.word\t0x00000072\n- R_ARM_REL32\t.LC11\n-\t.word\t0x00000058\n+\tsub.w\tr0, r1, #48\t@ 0x30\n+\tstrd\tr2, r3, [r1, #-48]\t@ 0x30\n+\tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_kcut>\n+ R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_kcut\n+\tsub.w\tr3, sl, #1432\t@ 0x598\n+\tldr.w\tr8, [r3]\n+\tb.w\t2698 <__gridxc_atom_MOD_atomxc+0x2698>\n+\tldr\tr0, [pc, #104]\t@ (35dc <__gridxc_atom_MOD_atomxc+0x35dc>)\n+\tmovs\tr1, #0\n+\tldr.w\tr3, [r7, #184]\t@ 0xb8\n+\tadd\tr0, pc\n+\tstrd\tr1, r1, [sp]\n+\tadd.w\tr2, r0, #32\n+\tadds\tr0, #24\n+\tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n+ R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n+\tmovs\tr3, #1\n+\tstr\tr3, [r7, #100]\t@ 0x64\n+\tb.w\ta4a <__gridxc_atom_MOD_atomxc+0xa4a>\n+\t.word\t0x000003a2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000314\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000002cc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000284\n+ R_ARM_REL32\t.LC25\n+\t.word\t0x0000026c\n+ R_ARM_REL32\t.LC26\n+\t.word\t0x0000024c\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x0000022c\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x00000200\n+ R_ARM_REL32\t.LC31\n+\t.word\t0x000001e0\n+ R_ARM_REL32\t.LC32\n+\t.word\t0x000001be\n+ R_ARM_REL32\t.LC33\n+\t.word\t0x000001a0\n+ R_ARM_REL32\t.LC34\n+\t.word\t0x000000c6\n R_ARM_REL32\t.LC9\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x000000a2\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x000000a4\n+ R_ARM_REL32\t.LC11\n+\t.word\t0x0000009a\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x0000009c\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x00000092\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x00000094\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x00000060\n+ R_ARM_REL32\t.rodata\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -29,25 +29,25 @@\n 0x000001a0 6572005f 67666f72 7472616e 5f73745f er._gfortran_st_\n 0x000001b0 72656164 5f646f6e 65005f67 666f7274 read_done._gfort\n 0x000001c0 72616e5f 636f6e63 61745f73 7472696e ran_concat_strin\n 0x000001d0 67005f5f 78635f66 30335f6c 69625f6d g.__xc_f03_lib_m\n 0x000001e0 5f4d4f44 5f78635f 6630335f 66756e63 _MOD_xc_f03_func\n 0x000001f0 5f696e69 74005f5f 78635f66 30335f6c _init.__xc_f03_l\n 0x00000200 69625f6d 5f4d4f44 5f78635f 6630335f ib_m_MOD_xc_f03_\n- 0x00000210 66756e63 5f676574 5f696e66 6f005f47 func_get_info._G\n- 0x00000220 4c4f4241 4c5f4f46 46534554 5f544142 LOBAL_OFFSET_TAB\n- 0x00000230 4c455f00 5f5f7374 61636b5f 63686b5f LE_.__stack_chk_\n- 0x00000240 67756172 64005f5f 67726964 78635f73 guard.__gridxc_s\n- 0x00000250 79735f4d 4f445f64 6965005f 5f677269 ys_MOD_die.__gri\n- 0x00000260 6478635f 616c6c6f 635f4d4f 445f7265 dxc_alloc_MOD_re\n- 0x00000270 616c6c6f 635f6432 005f5f67 72696478 alloc_d2.__gridx\n- 0x00000280 635f616c 6c6f635f 4d4f445f 7265616c c_alloc_MOD_real\n- 0x00000290 6c6f635f 6431005f 5f677269 6478635f loc_d1.__gridxc_\n- 0x000002a0 616c6c6f 635f4d4f 445f7265 616c6c6f alloc_MOD_reallo\n- 0x000002b0 635f6433 005f6766 6f727472 616e5f69 c_d3._gfortran_i\n+ 0x00000210 66756e63 5f676574 5f696e66 6f005f5f func_get_info.__\n+ 0x00000220 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n+ 0x00000230 5f726561 6c6c6f63 5f643200 5f5f6772 _realloc_d2.__gr\n+ 0x00000240 69647863 5f616c6c 6f635f4d 4f445f72 idxc_alloc_MOD_r\n+ 0x00000250 65616c6c 6f635f64 31005f5f 67726964 ealloc_d1.__grid\n+ 0x00000260 78635f61 6c6c6f63 5f4d4f44 5f726561 xc_alloc_MOD_rea\n+ 0x00000270 6c6c6f63 5f643300 5f474c4f 42414c5f lloc_d3._GLOBAL_\n+ 0x00000280 4f464653 45545f54 41424c45 5f005f5f OFFSET_TABLE_.__\n+ 0x00000290 73746163 6b5f6368 6b5f6775 61726400 stack_chk_guard.\n+ 0x000002a0 5f5f6772 69647863 5f737973 5f4d4f44 __gridxc_sys_MOD\n+ 0x000002b0 5f646965 005f6766 6f727472 616e5f69 _die._gfortran_i\n 0x000002c0 6e746572 6e616c5f 7061636b 005f5f67 nternal_pack.__g\n 0x000002d0 72696478 635f6c64 615f4d4f 445f6c64 ridxc_lda_MOD_ld\n 0x000002e0 61786300 66726565 005f5f78 635f6630 axc.free.__xc_f0\n 0x000002f0 335f6c69 625f6d5f 4d4f445f 78635f66 3_lib_m_MOD_xc_f\n 0x00000300 30335f66 756e635f 656e6400 5f5f6772 03_func_end.__gr\n 0x00000310 69647863 5f616c6c 6f635f4d 4f445f64 idxc_alloc_MOD_d\n 0x00000320 65616c6c 6f635f64 33005f5f 67726964 ealloc_d3.__grid\n@@ -74,11 +74,11 @@\n 0x00000470 6e746572 706f6c61 74696f6e 5f6c6f63 nterpolation_loc\n 0x00000480 616c005f 67666f72 7472616e 5f696e74 al._gfortran_int\n 0x00000490 65726e61 6c5f756e 7061636b 005f5f67 ernal_unpack.__g\n 0x000004a0 72696478 635f7261 64666674 5f4d4f44 ridxc_radfft_MOD\n 0x000004b0 5f726164 66667400 5f5f6772 69647863 _radfft.__gridxc\n 0x000004c0 5f766477 78635f4d 4f445f76 64775f70 _vdwxc_MOD_vdw_p\n 0x000004d0 6869005f 67666f72 7472616e 5f6d6174 hi._gfortran_mat\n- 0x000004e0 6d756c5f 7238005f 67666f72 7472616e mul_r8._gfortran\n- 0x000004f0 5f6f735f 6572726f 725f6174 005f5f73 _os_error_at.__s\n- 0x00000500 7461636b 5f63686b 5f666169 6c00 tack_chk_fail.\n+ 0x000004e0 6d756c5f 7238005f 5f737461 636b5f63 mul_r8.__stack_c\n+ 0x000004f0 686b5f66 61696c00 5f67666f 72747261 hk_fail._gfortra\n+ 0x00000500 6e5f6f73 5f657272 6f725f61 7400 n_os_error_at.\n \n"}]}, {"source1": "bessph.F90.o", "source2": "bessph.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 1644 (bytes into file)\n+ Start of section headers: 1628 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x66c:\n+There are 11 section headers, starting at offset 0x65c:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000264 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 00058c 000080 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 00029c 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 00029c 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 00029c 00005f 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 0002fb 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0002fb 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 000330 000130 10 9 6 4\n- [ 9] .strtab STRTAB 00000000 000460 000129 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 00060c 00005f 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 00025c 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 00057c 000080 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 000294 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 000294 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 000294 00005f 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 0002f3 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0002f3 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 000320 000130 10 9 6 4\n+ [ 9] .strtab STRTAB 00000000 000450 000129 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 0005fc 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -3,15 +3,15 @@\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 3: 00000038 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 5: 00000238 0 NOTYPE LOCAL DEFAULT 1 $d\n- 6: 00000001 612 FUNC GLOBAL DEFAULT 1 __gridxc_bessph_MOD_bessph\n+ 6: 00000001 604 FUNC GLOBAL DEFAULT 1 __gridxc_bessph_MOD_bessph\n 7: 00000000 0 NOTYPE GLOBAL DEFAULT UND sincos\n 8: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n 9: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n 10: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n 11: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_real_write\n 12: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n 13: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,19 +1,19 @@\n \n-Relocation section '.rel.text' at offset 0x58c contains 16 entries:\n+Relocation section '.rel.text' at offset 0x57c contains 16 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000128 0000070a R_ARM_THM_CALL 00000000 sincos\n-000001d2 0000080a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000001de 0000090a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000001e8 00000a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-000001f2 00000b0a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n-000001fc 00000c0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000208 00000d0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000224 00000e0a R_ARM_THM_CALL 00000000 free\n-00000230 00000f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000001d6 0000080a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000001e2 0000090a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+000001ec 00000a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+000001f6 00000b0a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n+00000200 00000c0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000020c 00000d0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000228 00000e0a R_ARM_THM_CALL 00000000 free\n+00000234 00000f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000240 00001019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000244 0000111a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000248 00001019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000024c 0000111a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000250 00001019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000254 00001019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000258 00000203 R_ARM_REL32 00000000 .LC0\n-0000025c 00000303 R_ARM_REL32 00000038 .LC1\n-00000260 0000121a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000024c 00001019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000250 00000203 R_ARM_REL32 00000000 .LC0\n+00000254 00000303 R_ARM_REL32 00000038 .LC1\n+00000258 0000121a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,8 +1,7 @@\n-!I F&\"yD\n )F FKFBF\n /build/reproducible-path/libgridxc-2.0.1/src/bessph.F90\n BESSPH: SERIES HAS NOT CONVERGED. L,X=\n __gridxc_bessph_MOD_bessph\n _gfortran_st_write\n _gfortran_transfer_character_write\n _gfortran_transfer_integer_write\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -6,161 +6,162 @@\n 00000000 <__gridxc_bessph_MOD_bessph>:\n __gridxc_bessph_MOD_bessph():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3544]\t@ 0xdd8\n-\tldr\tr2, [pc, #560]\t@ (248 <__gridxc_bessph_MOD_bessph+0x248>)\n+\tldr\tr2, [pc, #552]\t@ (240 <__gridxc_bessph_MOD_bessph+0x240>)\n \tsub\tsp, #508\t@ 0x1fc\n-\tldr\tr3, [pc, #560]\t@ (24c <__gridxc_bessph_MOD_bessph+0x24c>)\n+\tldr\tr3, [pc, #552]\t@ (244 <__gridxc_bessph_MOD_bessph+0x244>)\n \tadd\tr2, pc\n \tldr\tr4, [r0, #0]\n \tvldr\td9, [r1]\n-\tldr\tr6, [pc, #556]\t@ (250 <__gridxc_bessph_MOD_bessph+0x250>)\n+\tldr\tr6, [pc, #548]\t@ (248 <__gridxc_bessph_MOD_bessph+0x248>)\n \tldr\tr3, [r2, r3]\n \tmov.w\tr8, r4, lsl #1\n-\tvabs.f64\td17, d9\n+\tvabs.f64\td6, d9\n \tadd\tr6, pc\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #500]\t@ 0x1f4\n \tmov.w\tr3, #0\n \tadd.w\tr3, r8, #4294967295\t@ 0xffffffff\n \tcmp\tr3, #1\n \tit\tlt\n \tmovlt\tr3, #1\n \tvmov\ts15, r3\n-\tvcvt.f64.s32\td16, s15\n-\tvcmpe.f64\td17, d16\n+\tvcvt.f64.s32\td7, s15\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\t11e <__gridxc_bessph_MOD_bessph+0x11e>\n \tmov\tr7, r0\n \tmov\tr5, r1\n \tcmp\tr4, #0\n \tble.w\t190 <__gridxc_bessph_MOD_bessph+0x190>\n \tadd.w\tr2, r8, #3\n \tmovs\tr3, #3\n \tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n \tvmov\ts15, r3\n-\tvmul.f64\td17, d9, d8\n+\tvmul.f64\td6, d9, d8\n \tadds\tr3, #2\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s15\n \tcmp\tr2, r3\n-\tvdiv.f64\td8, d17, d16\n+\tvdiv.f64\td8, d6, d7\n \tbne.n\t68 <__gridxc_bessph_MOD_bessph+0x68>\n \tvmul.f64\td9, d9, d9\n-\tvmov.f64\td16, #80\t@ 0x3e800000 0.250\n+\tvmov.f64\td7, #80\t@ 0x3e800000 0.250\n \tadds\tr3, r4, #1\n-\tvmov\ts15, r3\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td21, [pc, #420]\t@ 238 <__gridxc_bessph_MOD_bessph+0x238>\n-\tvcvt.f64.s32\td17, s15\n-\tvmul.f64\td9, d9, d16\n-\tvadd.f64\td17, d17, d20\n-\tvmul.f64\td19, d9, d8\n-\tvdiv.f64\td16, d19, d17\n-\tvabs.f64\td17, d16\n-\tvneg.f64\td16, d16\n-\tvcmpe.f64\td17, d21\n+\tvmov\ts13, r3\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [pc, #420]\t@ 238 <__gridxc_bessph_MOD_bessph+0x238>\n+\tvcvt.f64.s32\td6, s13\n+\tvmul.f64\td9, d9, d7\n+\tvadd.f64\td6, d6, d4\n+\tvmul.f64\td2, d9, d8\n+\tvdiv.f64\td7, d2, d6\n+\tvabs.f64\td6, d7\n+\tvneg.f64\td7, d7\n+\tvcmpe.f64\td6, d3\n \tvmrs\tAPSR_nzcv, fpscr\n \tbmi.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n \tmovs\tr2, #1\n \tadds\tr2, #1\n \tcmp\tr2, #101\t@ 0x65\n \tbeq.n\t196 <__gridxc_bessph_MOD_bessph+0x196>\n+\tvmul.f64\td2, d9, d7\n+\tvadd.f64\td8, d8, d7\n \tadds\tr3, r4, r2\n \tvmov\ts15, r3\n-\tvmul.f64\td19, d9, d16\n-\tvadd.f64\td8, d8, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r2\n-\tvcvt.f64.s32\td17, s15\n-\tvadd.f64\td16, d16, d20\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td17, d19, d16\n-\tvabs.f64\td19, d17\n-\tvneg.f64\td16, d17\n-\tvcmpe.f64\td19, d21\n+\tvmov\ts13, r2\n+\tvcvt.f64.s32\td7, s15\n+\tvcvt.f64.s32\td6, s13\n+\tvadd.f64\td7, d7, d4\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td6, d2, d7\n+\tvabs.f64\td2, d6\n+\tvneg.f64\td7, d6\n+\tvcmpe.f64\td2, d3\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\tbc <__gridxc_bessph_MOD_bessph+0xbc>\n-\tldr\tr2, [pc, #344]\t@ (254 <__gridxc_bessph_MOD_bessph+0x254>)\n-\tldr\tr3, [pc, #332]\t@ (24c <__gridxc_bessph_MOD_bessph+0x24c>)\n+\tldr\tr2, [pc, #336]\t@ (24c <__gridxc_bessph_MOD_bessph+0x24c>)\n+\tldr\tr3, [pc, #324]\t@ (244 <__gridxc_bessph_MOD_bessph+0x244>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #500]\t@ 0x1f4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t230 <__gridxc_bessph_MOD_bessph+0x230>\n+\tbne.w\t234 <__gridxc_bessph_MOD_bessph+0x234>\n \tvmov.f64\td0, d8\n \tadd\tsp, #508\t@ 0x1fc\n \tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tadd\tr5, sp, #8\n \tvmov.f64\td0, d9\n \tmov\tr1, sp\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvldr\td17, [sp, #8]\n-\tvldr\td16, [r5, #-8]\n+\tvldr\td6, [sp, #8]\n+\tvldr\td7, [r5, #-8]\n \tcbz\tr4, 18a <__gridxc_bessph_MOD_bessph+0x18a>\n \tcmp\tr4, #1\n \tbeq.n\t17c <__gridxc_bessph_MOD_bessph+0x17c>\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td20, d18, d9\n-\tvmul.f64\td17, d20, d17\n-\tvsub.f64\td16, d17, d16\n-\tvmul.f64\td16, d16, d20\n-\tble.n\t22a <__gridxc_bessph_MOD_bessph+0x22a>\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td3, d5, d9\n+\tvmul.f64\td6, d3, d6\n+\tvsub.f64\td7, d6, d7\n+\tvmul.f64\td7, d7, d3\n+\tble.n\t22e <__gridxc_bessph_MOD_bessph+0x22e>\n \tadd.w\tr2, r8, #1\n \tmovs\tr3, #3\n \tb.n\t15c <__gridxc_bessph_MOD_bessph+0x15c>\n-\tvmov.f64\td16, d8\n-\tvmov\ts15, r3\n-\tvmul.f64\td18, d20, d16\n+\tvmov.f64\td7, d8\n+\tvmov\ts11, r3\n \tadds\tr3, #2\n-\tvcvt.f64.s32\td19, s15\n \tcmp\tr2, r3\n-\tvfnms.f64\td17, d19, d18\n-\tvmov.f64\td8, d17\n-\tvmov.f64\td17, d16\n+\tvcvt.f64.s32\td4, s11\n+\tvmul.f64\td5, d3, d7\n+\tvnmls.f64\td6, d4, d5\n+\tvmov.f64\td8, d6\n+\tvmov.f64\td6, d7\n \tbne.n\t158 <__gridxc_bessph_MOD_bessph+0x158>\n \tb.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n-\tvdiv.f64\td18, d17, d9\n-\tvsub.f64\td16, d18, d16\n-\tvdiv.f64\td8, d16, d9\n+\tvdiv.f64\td5, d6, d9\n+\tvsub.f64\td7, d5, d7\n+\tvdiv.f64\td8, d7, d9\n \tb.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n-\tvdiv.f64\td8, d17, d9\n+\tvdiv.f64\td8, d6, d9\n \tb.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n \tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n \tb.n\t7e <__gridxc_bessph_MOD_bessph+0x7e>\n-\tvabs.f64\td16, d16\n-\tvldr\td17, [pc, #156]\t@ 238 <__gridxc_bessph_MOD_bessph+0x238>\n-\tvcmpe.f64\td16, d17\n+\tvabs.f64\td7, d7\n+\tvldr\td6, [pc, #156]\t@ 238 <__gridxc_bessph_MOD_bessph+0x238>\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n \tble.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n-\tvldr\td16, [pc, #148]\t@ 240 <__gridxc_bessph_MOD_bessph+0x240>\n \tadd\tr4, sp, #24\n-\tldr\tr3, [pc, #168]\t@ (258 <__gridxc_bessph_MOD_bessph+0x258>)\n+\tldr\tr3, [pc, #164]\t@ (250 <__gridxc_bessph_MOD_bessph+0x250>)\n \tmov\tr0, r4\n+\tmov.w\tr2, #16512\t@ 0x4080\n+\tadd\tr3, pc\n \tadd.w\tr9, sp, #372\t@ 0x174\n \tmov.w\tr8, #128\t@ 0x80\n-\tvstr\td16, [sp, #24]\n-\tadd\tr3, pc\n-\tstr.w\tr9, [sp, #92]\t@ 0x5c\n \tstr\tr3, [sp, #32]\n+\tstr.w\tr9, [sp, #92]\t@ 0x5c\n \tmovs\tr3, #51\t@ 0x33\n \tstr.w\tr8, [sp, #96]\t@ 0x60\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmovs\tr3, #0\n \tstr\tr3, [sp, #72]\t@ 0x48\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #24]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #132]\t@ (25c <__gridxc_bessph_MOD_bessph+0x25c>)\n+\tldr\tr1, [pc, #120]\t@ (254 <__gridxc_bessph_MOD_bessph+0x254>)\n \tmov\tr0, r4\n \tmovs\tr2, #38\t@ 0x26\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tmov\tr1, r7\n@@ -179,43 +180,40 @@\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tmov\tr3, r9\n \tmov\tr2, r8\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #80]\t@ (260 <__gridxc_bessph_MOD_bessph+0x260>)\n+\tldr\tr3, [pc, #68]\t@ (258 <__gridxc_bessph_MOD_bessph+0x258>)\n \tldrd\tr5, r4, [sp, #16]\n \tldr\tr3, [r6, r3]\n \tmov\tr0, r5\n \tmov\tr1, r4\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tcmp\tr4, #0\n \tble.w\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tb.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n-\tvmov.f64\td8, d16\n+\tvmov.f64\td8, d7\n \tb.n\tfa <__gridxc_bessph_MOD_bessph+0xfa>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x00004080\n-\t.word\t0xffffffff\n-\t.word\t0x0000022a\n+\t.word\t0x00000222\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000021e\n+\t.word\t0x00000216\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000152\n+\t.word\t0x0000014a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000096\n+\t.word\t0x0000009a\n R_ARM_REL32\t.LC0\n-\t.word\t0x0000007c\n+\t.word\t0x00000070\n R_ARM_REL32\t.LC1\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "cellsubs.F90.o", "source2": "cellsubs.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 668 (bytes into file)\n+ Start of section headers: 704 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 9\n Section header string table index: 8\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,18 +1,18 @@\n-There are 9 section headers, starting at offset 0x29c:\n+There are 9 section headers, starting at offset 0x2c0:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000150 00 AX 0 0 8\n- [ 2] .data PROGBITS 00000000 000188 000000 00 WA 0 0 1\n- [ 3] .bss NOBITS 00000000 000188 000000 00 WA 0 0 1\n- [ 4] .note.GNU-stack PROGBITS 00000000 000188 000000 00 0 0 1\n- [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 000188 000033 00 0 0 1\n- [ 6] .symtab SYMTAB 00000000 0001bc 000050 10 7 3 4\n- [ 7] .strtab STRTAB 00000000 00020c 000041 00 0 0 1\n- [ 8] .shstrtab STRTAB 00000000 00024d 00004c 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 000178 00 AX 0 0 8\n+ [ 2] .data PROGBITS 00000000 0001b0 000000 00 WA 0 0 1\n+ [ 3] .bss NOBITS 00000000 0001b0 000000 00 WA 0 0 1\n+ [ 4] .note.GNU-stack PROGBITS 00000000 0001b0 000000 00 0 0 1\n+ [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 0001b0 00002d 00 0 0 1\n+ [ 6] .symtab SYMTAB 00000000 0001e0 000050 10 7 3 4\n+ [ 7] .strtab STRTAB 00000000 000230 000041 00 0 0 1\n+ [ 8] .shstrtab STRTAB 00000000 000271 00004c 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,8 +1,8 @@\n \n Symbol table '.symtab' contains 5 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 2: 00000148 0 NOTYPE LOCAL DEFAULT 1 $d\n- 3: 00000001 78 FUNC GLOBAL DEFAULT 1 __gridxc_cellsubs_MOD_volcel\n- 4: 00000051 256 FUNC GLOBAL DEFAULT 1 __gridxc_cellsubs_MOD_reclat\n+ 2: 00000170 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 3: 00000001 86 FUNC GLOBAL DEFAULT 1 __gridxc_cellsubs_MOD_volcel\n+ 4: 00000059 288 FUNC GLOBAL DEFAULT 1 __gridxc_cellsubs_MOD_reclat\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -1,97 +1,108 @@\n \n \n \n Disassembly of section .text:\n \n 00000000 <__gridxc_cellsubs_MOD_volcel>:\n __gridxc_cellsubs_MOD_volcel():\n-\tvldr\td21, [r0, #40]\t@ 0x28\n-\tvldr\td18, [r0]\n-\tvldr\td22, [r0, #16]\n-\tvldr\td19, [r0, #32]\n-\tvldr\td16, [r0, #24]\n-\tvnmul.f64\td0, d18, d21\n-\tvldr\td20, [r0, #8]\n-\tvnmul.f64\td17, d19, d22\n-\tvldr\td24, [r0, #56]\t@ 0x38\n-\tvfma.f64\td0, d22, d16\n-\tvldr\td23, [r0, #48]\t@ 0x30\n-\tvfma.f64\td17, d20, d21\n-\tvnmul.f64\td16, d16, d20\n-\tvfma.f64\td16, d19, d18\n-\tvldr\td20, [r0, #64]\t@ 0x40\n-\tvmul.f64\td0, d0, d24\n-\tvfma.f64\td0, d17, d23\n-\tvfma.f64\td0, d16, d20\n+\tvldr\td5, [r0]\n+\tvldr\td1, [r0, #40]\t@ 0x28\n+\tvldr\td4, [r0, #32]\n+\tvpush\t{d8}\n+\tvldr\td8, [r0, #16]\n+\tvmul.f64\td0, d1, d5\n+\tvldr\td3, [r0, #24]\n+\tvldr\td7, [r0, #8]\n+\tvmul.f64\td6, d8, d4\n+\tvldr\td2, [r0, #48]\t@ 0x30\n+\tvnmls.f64\td0, d8, d3\n+\tvpop\t{d8}\n+\tvnmls.f64\td6, d7, d1\n+\tvmul.f64\td7, d7, d3\n+\tvldr\td3, [r0, #64]\t@ 0x40\n+\tvnmls.f64\td7, d4, d5\n+\tvldr\td5, [r0, #56]\t@ 0x38\n+\tvmul.f64\td0, d0, d5\n+\tvmla.f64\td0, d6, d2\n+\tvmla.f64\td0, d7, d3\n \tvabs.f64\td0, d0\n \tbx\tlr\n \tnop\n \n-00000050 <__gridxc_cellsubs_MOD_reclat>:\n+00000058 <__gridxc_cellsubs_MOD_reclat>:\n __gridxc_cellsubs_MOD_reclat():\n-\tvldr\td29, [r0, #64]\t@ 0x40\n-\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n-\tvldr\td30, [r0, #40]\t@ 0x28\n-\tvldr\td7, [r0, #48]\t@ 0x30\n-\tvldr\td6, [r0, #24]\n-\tvldr\td31, [r0, #16]\n+\tvldr\td2, [r0, #40]\t@ 0x28\n+\tvldr\td6, [r0, #56]\t@ 0x38\n+\tvpush\t{d8-d15}\n+\tsub\tsp, #16\n \tvldr\td5, [r0]\n-\tvldr\td17, [r0, #32]\n-\tvnmul.f64\td26, d6, d29\n-\tvldr\td16, [r0, #56]\t@ 0x38\n-\tvnmul.f64\td23, d31, d7\n-\tvldr\td18, [r0, #8]\n-\tvnmul.f64\td20, d5, d30\n-\tvfma.f64\td23, d29, d5\n-\tvfma.f64\td26, d30, d7\n-\tvfma.f64\td20, d6, d31\n-\tvnmul.f64\td27, d16, d30\n-\tvnmul.f64\td24, d18, d29\n-\tvnmul.f64\td21, d31, d17\n-\tvfma.f64\td27, d17, d29\n-\tvfma.f64\td24, d16, d31\n-\tvfma.f64\td21, d30, d18\n-\tvnmul.f64\td25, d7, d17\n-\tvnmul.f64\td22, d5, d16\n-\tvnmul.f64\td19, d18, d6\n-\tvfma.f64\td25, d16, d6\n-\tvfma.f64\td22, d7, d18\n-\tvfma.f64\td19, d17, d5\n+\tvmul.f64\td3, d2, d6\n+\tvldr\td7, [r0, #32]\n+\tvldr\td9, [r0, #64]\t@ 0x40\n+\tvmul.f64\td4, d2, d5\n+\tvldr\td1, [r0, #24]\n+\tvldr\td0, [r0, #16]\n+\tvnmls.f64\td3, d7, d9\n+\tvldr\td10, [r0, #48]\t@ 0x30\n+\tvldr\td8, [r0, #8]\n+\tvmul.f64\td11, d9, d1\n+\tvnmls.f64\td4, d1, d0\n+\tvmul.f64\td15, d7, d0\n+\tvmul.f64\td12, d7, d10\n+\tvmul.f64\td14, d10, d0\n+\tvmul.f64\td13, d9, d8\n \tldr\tr3, [r2, #0]\n-\tvmul.f64\td18, d26, d18\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d20\n-\tvldr\td28, [pc, #120]\t@ 148 <__gridxc_cellsubs_MOD_reclat+0xf8>\n+\tvnmls.f64\td11, d2, d10\n+\tvnmls.f64\td15, d2, d8\n \tcmp\tr3, #1\n-\tvfma.f64\td18, d27, d5\n-\tvfma.f64\td17, d6, d24\n-\tvfma.f64\td16, d7, d21\n-\tvseleq.f64\td28, d28, d4\n-\tvfma.f64\td18, d25, d31\n-\tvfma.f64\td17, d30, d22\n-\tvfma.f64\td16, d29, d19\n-\tvdiv.f64\td29, d28, d18\n-\tvdiv.f64\td18, d28, d17\n-\tvdiv.f64\td17, d28, d16\n-\tvmul.f64\td27, d27, d29\n-\tvmul.f64\td26, d26, d29\n-\tvmul.f64\td25, d25, d29\n-\tvmul.f64\td24, d24, d18\n-\tvmul.f64\td23, d23, d18\n-\tvmul.f64\td22, d22, d18\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td20, d20, d17\n-\tvmul.f64\td19, d19, d17\n-\tvstr\td27, [r1]\n-\tvstr\td26, [r1, #8]\n-\tvstr\td25, [r1, #16]\n-\tvstr\td24, [r1, #24]\n-\tvstr\td23, [r1, #32]\n-\tvstr\td22, [r1, #40]\t@ 0x28\n-\tvstr\td21, [r1, #48]\t@ 0x30\n-\tvstr\td20, [r1, #56]\t@ 0x38\n-\tvstr\td19, [r1, #64]\t@ 0x40\n+\tvnmls.f64\td12, d6, d1\n+\tvnmls.f64\td14, d9, d5\n+\tvstr\td3, [sp]\n+\tvmul.f64\td3, d6, d5\n+\tvnmls.f64\td13, d6, d0\n+\tvstr\td4, [sp, #8]\n+\tvmul.f64\td6, d6, d4\n+\tvmov.f64\td4, d3\n+\tvldr\td3, [sp]\n+\tvmla.f64\td6, d10, d15\n+\tvnmls.f64\td4, d10, d8\n+\tvmul.f64\td10, d1, d8\n+\tvnmls.f64\td10, d7, d5\n+\tvmul.f64\td5, d3, d5\n+\tvmul.f64\td7, d7, d14\n+\tvmla.f64\td5, d11, d8\n+\tvmla.f64\td7, d1, d13\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td5, d12, d0\n+\tvmla.f64\td7, d2, d4\n+\tvldr\td2, [pc, #108]\t@ 170 <__gridxc_cellsubs_MOD_reclat+0x118>\n+\tvmla.f64\td6, d9, d10\n+\tit\tne\n+\tvmovne.f64\td2, d1\n+\tvdiv.f64\td1, d2, d5\n+\tvdiv.f64\td5, d2, d6\n+\tvdiv.f64\td6, d2, d7\n+\tvldr\td7, [sp, #8]\n+\tvmul.f64\td3, d3, d1\n+\tvmul.f64\td11, d11, d1\n+\tvmul.f64\td12, d12, d1\n+\tvmul.f64\td15, d15, d5\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td13, d13, d6\n+\tvmul.f64\td14, d14, d6\n+\tvmul.f64\td4, d4, d6\n+\tvmul.f64\td10, d10, d5\n+\tvstr\td3, [r1]\n+\tvstr\td11, [r1, #8]\n+\tvstr\td12, [r1, #16]\n+\tvstr\td13, [r1, #24]\n+\tvstr\td14, [r1, #32]\n+\tvstr\td4, [r1, #40]\t@ 0x28\n+\tvstr\td15, [r1, #48]\t@ 0x30\n+\tvstr\td7, [r1, #56]\t@ 0x38\n+\tvstr\td10, [r1, #64]\t@ 0x40\n+\tadd\tsp, #16\n+\tvpop\t{d8-d15}\n \tbx\tlr\n-\tnop\n \t.word\t0x54442d18\n \t.word\t0x401921fb\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "cellxc.F90.o", "source2": "cellxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 40996 (bytes into file)\n+ Start of section headers: 40668 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0xa024:\n+There are 12 section headers, starting at offset 0x9edc:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 007724 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 00926c 000d50 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 007760 000070 00 WA 0 0 8\n- [ 4] .bss NOBITS 00000000 0077d0 00088c 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 0077d0 000424 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 007bf4 000010 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 007c04 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 007c04 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 007c38 000ce0 10 10 147 4\n- [10] .strtab STRTAB 00000000 008918 000951 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 009fbc 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0075ac 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0090fc 000d78 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0075e8 000070 00 WA 0 0 8\n+ [ 4] .bss NOBITS 00000000 007658 000888 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 007658 000424 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 007a7c 000010 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 007a8c 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 007a8c 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 007abc 000ce0 10 10 146 4\n+ [10] .strtab STRTAB 00000000 00879c 00095e 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 009e74 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,16 +1,16 @@\n \n Symbol table '.symtab' contains 206 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n- 3: 00000001 1500 FUNC LOCAL DEFAULT 1 getgraddens.0\n+ 3: 00000001 1556 FUNC LOCAL DEFAULT 1 getgraddens.0\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 5: 000005c4 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 000005fc 0 NOTYPE LOCAL DEFAULT 1 $d\n 6: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 7: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 8: 00000008 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 9: 0000000c 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 10: 00000010 0 NOTYPE LOCAL DEFAULT 5 .LC4\n 11: 00000014 0 NOTYPE LOCAL DEFAULT 5 .LC5\n 12: 00000018 0 NOTYPE LOCAL DEFAULT 5 .LC6\n@@ -56,154 +56,154 @@\n 52: 000003d8 0 NOTYPE LOCAL DEFAULT 5 .LC50\n 53: 000003e4 0 NOTYPE LOCAL DEFAULT 5 .LC51\n 54: 000003f0 0 NOTYPE LOCAL DEFAULT 5 .LC52\n 55: 000003fc 0 NOTYPE LOCAL DEFAULT 5 .LC53\n 56: 00000408 0 NOTYPE LOCAL DEFAULT 5 .LC54\n 57: 00000414 0 NOTYPE LOCAL DEFAULT 5 .LC55\n 58: 00000420 0 NOTYPE LOCAL DEFAULT 5 .LC56\n- 59: 000005dc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 60: 00000e90 0 NOTYPE LOCAL DEFAULT 1 $d\n- 61: 00000f04 0 NOTYPE LOCAL DEFAULT 1 $t\n- 62: 00001288 0 NOTYPE LOCAL DEFAULT 1 $d\n- 63: 000012d4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 64: 000016e0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 65: 00001740 0 NOTYPE LOCAL DEFAULT 1 $t\n- 66: 00001b40 0 NOTYPE LOCAL DEFAULT 1 $d\n- 67: 00001b54 0 NOTYPE LOCAL DEFAULT 1 $t\n- 68: 00001f88 0 NOTYPE LOCAL DEFAULT 1 $d\n- 69: 00001f9c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 70: 00002940 0 NOTYPE LOCAL DEFAULT 1 $d\n- 71: 0000297c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 72: 00003688 0 NOTYPE LOCAL DEFAULT 1 $d\n- 73: 000036a4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 74: 00003a00 0 NOTYPE LOCAL DEFAULT 1 $d\n- 75: 00003a30 0 NOTYPE LOCAL DEFAULT 1 $t\n- 76: 00004790 0 NOTYPE LOCAL DEFAULT 1 $d\n- 77: 000047fc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 78: 00004c18 0 NOTYPE LOCAL DEFAULT 1 $d\n- 79: 00004c30 0 NOTYPE LOCAL DEFAULT 1 $t\n- 80: 00005178 0 NOTYPE LOCAL DEFAULT 1 $d\n- 81: 000051a8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 82: 000056b8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 83: 000056d8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 84: 00005c88 0 NOTYPE LOCAL DEFAULT 1 $d\n- 85: 00005cd0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 86: 00006020 0 NOTYPE LOCAL DEFAULT 1 $d\n- 87: 00006044 0 NOTYPE LOCAL DEFAULT 1 $t\n- 88: 00006b10 0 NOTYPE LOCAL DEFAULT 1 $d\n- 89: 00006b6c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 90: 00007100 0 NOTYPE LOCAL DEFAULT 1 $d\n- 91: 00007118 0 NOTYPE LOCAL DEFAULT 1 $t\n- 92: 00007640 0 NOTYPE LOCAL DEFAULT 1 $d\n- 93: 000076f0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 94: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 95: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 96: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 97: 00000000 4 OBJECT LOCAL DEFAULT 3 mydistr.48\n- 98: 00000004 4 OBJECT LOCAL DEFAULT 3 iodistr.49\n- 99: 00000008 12 OBJECT LOCAL DEFAULT 3 oldmesh.47\n- 100: 00000018 8 OBJECT LOCAL DEFAULT 3 timedisp.46\n- 101: 00000020 8 OBJECT LOCAL DEFAULT 3 timeavge.45\n- 102: 00000028 4 OBJECT LOCAL DEFAULT 3 io2my.42\n- 103: 00000030 8 OBJECT LOCAL DEFAULT 3 mytime.41\n- 104: 00000038 12 OBJECT LOCAL DEFAULT 3 my2left.24\n- 105: 00000044 12 OBJECT LOCAL DEFAULT 3 my2rght.23\n- 106: 00000050 4 OBJECT LOCAL DEFAULT 3 kdistr.21\n- 107: 00000054 12 OBJECT LOCAL DEFAULT 3 left2my.3\n- 108: 00000060 12 OBJECT LOCAL DEFAULT 3 rght2my.2\n- 109: 0000006c 4 OBJECT LOCAL DEFAULT 3 my2io.1\n- 110: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 111: 00000000 72 OBJECT LOCAL DEFAULT 4 dleft3.34\n- 112: 00000048 72 OBJECT LOCAL DEFAULT 4 drght3.33\n- 113: 00000090 72 OBJECT LOCAL DEFAULT 4 mydens.44\n- 114: 000000d8 72 OBJECT LOCAL DEFAULT 4 dleft1.38\n- 115: 00000120 72 OBJECT LOCAL DEFAULT 4 drght1.37\n- 116: 00000168 72 OBJECT LOCAL DEFAULT 4 dleft2.36\n- 117: 000001b0 72 OBJECT LOCAL DEFAULT 4 drght2.35\n- 118: 000001f8 60 OBJECT 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000023ac 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 72: 000029c0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 73: 000029e8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 74: 00003780 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 75: 000037a8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 76: 00003b28 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 77: 00003b44 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 78: 00004438 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 79: 000044a8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 80: 000049e0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 81: 00004a3c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 82: 00005488 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 83: 000054ec 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 84: 00006310 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 85: 0000636c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 86: 00006890 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 87: 000068b4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 88: 00006e50 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 89: 00006e68 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 90: 00007348 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 91: 00007400 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 92: 000075a8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 93: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 94: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 95: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 96: 00000000 4 OBJECT LOCAL DEFAULT 3 mydistr.48\n+ 97: 00000004 4 OBJECT LOCAL DEFAULT 3 iodistr.49\n+ 98: 00000008 12 OBJECT LOCAL DEFAULT 3 oldmesh.47\n+ 99: 00000018 8 OBJECT LOCAL DEFAULT 3 timedisp.46\n+ 100: 00000020 8 OBJECT LOCAL DEFAULT 3 timeavge.45\n+ 101: 00000028 4 OBJECT LOCAL DEFAULT 3 io2my.42\n+ 102: 00000030 8 OBJECT LOCAL DEFAULT 3 mytime.41\n+ 103: 00000038 12 OBJECT LOCAL DEFAULT 3 my2left.24\n+ 104: 00000044 12 OBJECT LOCAL DEFAULT 3 my2rght.23\n+ 105: 00000050 4 OBJECT LOCAL DEFAULT 3 kdistr.21\n+ 106: 00000054 12 OBJECT LOCAL DEFAULT 3 left2my.3\n+ 107: 00000060 12 OBJECT LOCAL DEFAULT 3 rght2my.2\n+ 108: 0000006c 4 OBJECT LOCAL DEFAULT 3 my2io.1\n+ 109: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 110: 00000000 72 OBJECT LOCAL DEFAULT 4 dleft3.34\n+ 111: 00000048 72 OBJECT LOCAL DEFAULT 4 drght3.33\n+ 112: 00000090 72 OBJECT LOCAL DEFAULT 4 mydens.44\n+ 113: 000000d8 72 OBJECT LOCAL DEFAULT 4 dleft1.38\n+ 114: 00000120 72 OBJECT LOCAL DEFAULT 4 drght1.37\n+ 115: 00000168 72 OBJECT LOCAL DEFAULT 4 dleft2.36\n+ 116: 000001b0 72 OBJECT LOCAL DEFAULT 4 drght2.35\n+ 117: 000001f8 60 OBJECT LOCAL DEFAULT 4 workload.43\n+ 118: 00000234 72 OBJECT LOCAL DEFAULT 4 myvxc.40\n+ 119: 0000027c 72 OBJECT LOCAL DEFAULT 4 mydvxcdd.39\n+ 120: 000002c4 72 OBJECT LOCAL DEFAULT 4 vleft1.32\n+ 121: 0000030c 72 OBJECT LOCAL DEFAULT 4 vrght1.31\n+ 122: 00000354 72 OBJECT LOCAL DEFAULT 4 vleft2.30\n+ 123: 0000039c 72 OBJECT LOCAL DEFAULT 4 vrght2.29\n+ 124: 000003e4 72 OBJECT LOCAL DEFAULT 4 vleft3.28\n+ 125: 0000042c 72 OBJECT LOCAL DEFAULT 4 vrght3.27\n+ 126: 00000474 72 OBJECT LOCAL DEFAULT 4 dleft.26\n+ 127: 000004bc 72 OBJECT LOCAL DEFAULT 4 drght.25\n+ 128: 00000504 60 OBJECT LOCAL DEFAULT 4 nonempty.22\n+ 129: 00000540 36 OBJECT LOCAL DEFAULT 4 dudk.20\n+ 130: 00000564 48 OBJECT LOCAL DEFAULT 4 dtdd.19\n+ 131: 00000594 60 OBJECT LOCAL DEFAULT 4 dtdgd.18\n+ 132: 000005d0 48 OBJECT LOCAL DEFAULT 4 dphidk.17\n+ 133: 00000600 48 OBJECT LOCAL DEFAULT 4 phi.16\n+ 134: 00000630 36 OBJECT LOCAL DEFAULT 4 tk.15\n+ 135: 00000654 36 OBJECT LOCAL DEFAULT 4 tr.14\n+ 136: 00000678 36 OBJECT LOCAL DEFAULT 4 tvac.13\n+ 137: 0000069c 36 OBJECT LOCAL DEFAULT 4 ur.12\n+ 138: 000006c0 36 OBJECT LOCAL DEFAULT 4 uk.11\n+ 139: 000006e4 48 OBJECT LOCAL DEFAULT 4 tvdw.10\n+ 140: 00000714 72 OBJECT LOCAL DEFAULT 4 tq.9\n+ 141: 0000075c 48 OBJECT LOCAL DEFAULT 4 uvdw.8\n+ 142: 0000078c 72 OBJECT LOCAL DEFAULT 4 uq.7\n+ 143: 000007d4 36 OBJECT LOCAL DEFAULT 4 vj.4\n+ 144: 000007f8 72 OBJECT LOCAL DEFAULT 4 vleft.6\n+ 145: 00000840 72 OBJECT LOCAL DEFAULT 4 vrght.5\n+ 146: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idiv\n 147: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n 148: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 149: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 150: 000005dd 28998 FUNC GLOBAL DEFAULT 1 __gridxc_cell_MOD_cellxc\n+ 150: 00000615 28568 FUNC GLOBAL DEFAULT 1 __gridxc_cell_MOD_cellxc\n 151: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_xcmod_MOD_getxc\n 152: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_alloc_default\n 153: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_volcel\n 154: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n 155: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n 156: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n 157: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n 158: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n 159: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 160: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_start\n- 161: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 162: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 163: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 164: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n- 165: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n- 166: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n- 167: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n- 168: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n- 169: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+ 160: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 161: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 162: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n+ 163: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n+ 164: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n+ 165: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n+ 166: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n+ 167: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+ 168: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_start\n+ 169: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n 170: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_setmeshdistr\n 171: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_mymeshbox\n 172: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_samemeshdistr\n 173: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_associatemeshtask\n 174: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_copymeshdata\n 175: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 176: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n- 177: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_config_MOD_gridxc_totnodes\n- 178: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_reclat\n- 179: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_ldaxc\n- 180: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gga_MOD_ggaxc\n- 181: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_localxc\n- 182: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_decusp\n- 183: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_theta\n- 184: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n- 185: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_addmeshdata\n- 186: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_l3\n- 187: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n- 188: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_get_qmesh\n- 189: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d1\n- 190: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n- 191: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n- 192: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d4\n- 193: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_chkgmx_MOD_meshkcut\n- 194: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_kcut\n- 195: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fftr_MOD_fftr2k\n- 196: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_phi\n- 197: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_matmul_r8\n- 198: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fftr_MOD_fftk2r\n- 199: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d3\n- 200: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n- 201: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_moreparallelsubs_MOD_miscallreducedouble\n- 202: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d2\n- 203: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d1\n- 204: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_l3\n+ 176: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_config_MOD_gridxc_totnodes\n+ 177: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_reclat\n+ 178: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_ldaxc\n+ 179: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gga_MOD_ggaxc\n+ 180: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_localxc\n+ 181: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_decusp\n+ 182: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_theta\n+ 183: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n+ 184: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_addmeshdata\n+ 185: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_l3\n+ 186: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n+ 187: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_get_qmesh\n+ 188: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d1\n+ 189: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n+ 190: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n+ 191: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d4\n+ 192: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_chkgmx_MOD_meshkcut\n+ 193: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_kcut\n+ 194: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d3\n+ 195: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n+ 196: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fftr_MOD_fftr2k\n+ 197: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_phi\n+ 198: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_matmul_r8\n+ 199: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fftr_MOD_fftk2r\n+ 200: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_moreparallelsubs_MOD_miscallreducedouble\n+ 201: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d2\n+ 202: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d1\n+ 203: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_l3\n+ 204: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n 205: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_stop\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,429 +1,434 @@\n \n-Relocation section '.rel.text' at offset 0x926c contains 426 entries:\n+Relocation section '.rel.text' at offset 0x90fc contains 431 entries:\n Offset Info Type Sym. Value Symbol's Name\n-000005be 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000005c4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000005c8 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000005cc 00000103 R_ARM_REL32 00000000 .data\n-000005d0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000005d4 00000203 R_ARM_REL32 00000000 .bss\n-000005d8 00000203 R_ARM_REL32 00000000 .bss\n-00000c58 0000970a R_ARM_THM_CALL 00000000 __gridxc_xcmod_MOD_getxc\n-00000c76 0000980a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_alloc_default\n-00000cb6 0000990a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n-00000d20 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d32 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d44 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d56 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d6a 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d7c 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d8c 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000dd2 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000de4 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000e12 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000e22 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000e2c 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000e32 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000e46 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000e68 00009f0a R_ARM_THM_CALL 00000000 free\n-00000e82 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000eb8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000ebc 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000ec0 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000ec4 0000a01a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_start\n-00000ec8 00000703 R_ARM_REL32 00000000 .LC0\n-00000ecc 00005e03 R_ARM_REL32 00000000 .rodata\n-00000ed0 00000803 R_ARM_REL32 00000008 .LC2\n-00000ed4 00001203 R_ARM_REL32 00000084 .LC12\n-00000ed8 00000903 R_ARM_REL32 0000000c .LC3\n-00000edc 00000a03 R_ARM_REL32 00000010 .LC4\n-00000ee0 00000b03 R_ARM_REL32 00000014 .LC5\n-00000ee4 00000c03 R_ARM_REL32 00000018 .LC6\n-00000ee8 00000d03 R_ARM_REL32 0000001c .LC7\n-00000eec 00000e03 R_ARM_REL32 00000020 .LC8\n-00000ef0 00000f03 R_ARM_REL32 00000024 .LC9\n-00000ef4 00001003 R_ARM_REL32 00000028 .LC10\n-00000ef8 00001403 R_ARM_REL32 00000094 .LC14\n-00000efc 0000a11a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000f00 00001303 R_ARM_REL32 0000008c .LC13\n-00000f08 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00000f1a 0000a30a R_ARM_THM_CALL 00000000 memset\n-00000f20 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00000f32 0000a30a R_ARM_THM_CALL 00000000 memset\n-00000f38 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00000f4a 0000a30a R_ARM_THM_CALL 00000000 memset\n-00000fde 0000a40a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-00000fec 0000a50a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n-00000ff2 0000a60a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-00001014 0000a70a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000104c 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n-00001052 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n-000010a6 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000010b8 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000010ca 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000010dc 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000010ec 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000010fc 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000110c 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001144 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001188 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001198 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000011a2 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000011a8 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-000011be 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-000011e6 00009f0a R_ARM_THM_CALL 00000000 free\n-00001222 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000014e 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000022e 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000005f8 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000005fc 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000600 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000604 00000103 R_ARM_REL32 00000000 .data\n+00000608 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000060c 00000203 R_ARM_REL32 00000000 .bss\n+00000610 00000203 R_ARM_REL32 00000000 .bss\n+00000cbe 0000970a R_ARM_THM_CALL 00000000 __gridxc_xcmod_MOD_getxc\n+00000cde 0000980a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_alloc_default\n+00000d24 0000990a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n+00000d90 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000da2 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000db4 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000dc6 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000dda 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000dee 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000dfe 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000e40 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000e52 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000e8c 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000e9c 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000ea6 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000eac 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000ec2 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000ee8 00009f0a R_ARM_THM_CALL 00000000 free\n+00000f02 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000f12 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00000f24 0000a10a R_ARM_THM_CALL 00000000 memset\n+00000f2a 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00000f3c 0000a10a R_ARM_THM_CALL 00000000 memset\n+00000f42 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00000f54 0000a10a R_ARM_THM_CALL 00000000 memset\n+00000ff0 0000a20a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+00000ffe 0000a30a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n+00001004 0000a40a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+00001026 0000a50a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00001068 0000a60a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n+0000106e 0000a70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+000010c0 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000010c4 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000010c8 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000010cc 0000a81a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_start\n+000010d0 00000703 R_ARM_REL32 00000000 .LC0\n+000010d4 00005d03 R_ARM_REL32 00000000 .rodata\n+000010d8 00000803 R_ARM_REL32 00000008 .LC2\n+000010dc 00001203 R_ARM_REL32 00000084 .LC12\n+000010e0 00001003 R_ARM_REL32 00000028 .LC10\n+000010e4 00000903 R_ARM_REL32 0000000c .LC3\n+000010e8 00000a03 R_ARM_REL32 00000010 .LC4\n+000010ec 00000b03 R_ARM_REL32 00000014 .LC5\n+000010f0 00000c03 R_ARM_REL32 00000018 .LC6\n+000010f4 00000d03 R_ARM_REL32 0000001c .LC7\n+000010f8 00000e03 R_ARM_REL32 00000020 .LC8\n+000010fc 00000f03 R_ARM_REL32 00000024 .LC9\n+00001100 00001403 R_ARM_REL32 00000094 .LC14\n+00001104 0000a91a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001108 00001303 R_ARM_REL32 0000008c .LC13\n+0000110c 00001003 R_ARM_REL32 00000028 .LC10\n+00001110 00001803 R_ARM_REL32 00000198 .LC19\n+00001114 00000803 R_ARM_REL32 00000008 .LC2\n+00001118 00000903 R_ARM_REL32 0000000c .LC3\n+0000111c 00000a03 R_ARM_REL32 00000010 .LC4\n+0000112a 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000113c 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001150 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001164 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001176 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001188 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000119a 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000011d0 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001216 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00001228 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n 00001232 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000123c 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00001242 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001258 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00001282 00009f0a R_ARM_THM_CALL 00000000 free\n-00001298 00001003 R_ARM_REL32 00000028 .LC10\n-0000129c 00001803 R_ARM_REL32 00000198 .LC19\n-000012a0 0000a11a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000012a4 00000803 R_ARM_REL32 00000008 .LC2\n-000012a8 00000903 R_ARM_REL32 0000000c .LC3\n-000012ac 00000a03 R_ARM_REL32 00000010 .LC4\n-000012b0 00000b03 R_ARM_REL32 00000014 .LC5\n-000012b4 00000c03 R_ARM_REL32 00000018 .LC6\n-000012b8 00000d03 R_ARM_REL32 0000001c .LC7\n-000012bc 00000e03 R_ARM_REL32 00000020 .LC8\n-000012c0 00000f03 R_ARM_REL32 00000024 .LC9\n-000012c4 00001003 R_ARM_REL32 00000028 .LC10\n-000012c8 00001103 R_ARM_REL32 00000060 .LC11\n-000012cc 00001003 R_ARM_REL32 00000028 .LC10\n-000012d0 00001103 R_ARM_REL32 00000060 .LC11\n-000012d6 0000a20a R_ARM_THM_CALL 00000000 malloc\n-000012e6 0000a20a R_ARM_THM_CALL 00000000 malloc\n-000012f6 0000a20a R_ARM_THM_CALL 00000000 malloc\n-0000134e 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n-0000137c 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-000013dc 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_samemeshdistr\n-00001424 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000014aa 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00001508 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000151a 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00001594 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-0000159e 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000015c2 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-000015d8 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00001612 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000161e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00001664 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00001670 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-000016a2 0000b00a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000016b2 0000b00a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000016c4 0000b00a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000016f8 00000103 R_ARM_REL32 00000000 .data\n-000016fc 0000b11a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+00001238 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000124e 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+0000127c 00009f0a R_ARM_THM_CALL 00000000 free\n+000012ba 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000012cc 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+000012d6 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+000012dc 00009d0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000012f2 00009e0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00001320 00009f0a R_ARM_THM_CALL 00000000 free\n+00001328 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00001338 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00001348 0000a00a R_ARM_THM_CALL 00000000 malloc\n+000013ae 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n+000013dc 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+0000143c 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_samemeshdistr\n+00001488 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00001508 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+00001564 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00001572 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+000015ea 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+000015f8 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+0000161a 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+0000162e 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+00001682 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000168c 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+000016d8 00000b03 R_ARM_REL32 00000014 .LC5\n+000016dc 00000c03 R_ARM_REL32 00000018 .LC6\n+000016e0 00000d03 R_ARM_REL32 0000001c .LC7\n+000016e4 00000e03 R_ARM_REL32 00000020 .LC8\n+000016e8 00000f03 R_ARM_REL32 00000024 .LC9\n+000016ec 00001003 R_ARM_REL32 00000028 .LC10\n+000016f0 00001103 R_ARM_REL32 00000060 .LC11\n+000016f4 0000a91a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000016f8 00001003 R_ARM_REL32 00000028 .LC10\n+000016fc 00001103 R_ARM_REL32 00000060 .LC11\n 00001700 00000103 R_ARM_REL32 00000000 .data\n-00001704 00000203 R_ARM_REL32 00000000 .bss\n+00001704 0000b01a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n 00001708 00000103 R_ARM_REL32 00000000 .data\n 0000170c 00000203 R_ARM_REL32 00000000 .bss\n 00001710 00000103 R_ARM_REL32 00000000 .data\n 00001714 00000203 R_ARM_REL32 00000000 .bss\n-00001718 00000203 R_ARM_REL32 00000000 .bss\n-0000171c 0000a11a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001718 00000103 R_ARM_REL32 00000000 .data\n+0000171c 00000203 R_ARM_REL32 00000000 .bss\n 00001720 00001a03 R_ARM_REL32 000001d8 .LC21\n-00001724 00001903 R_ARM_REL32 000001ac .LC20\n-00001728 00001503 R_ARM_REL32 000000cc .LC15\n-0000172c 00001703 R_ARM_REL32 0000013c .LC17\n-00001730 00001503 R_ARM_REL32 000000cc .LC15\n-00001734 00001703 R_ARM_REL32 0000013c .LC17\n-00001738 00001503 R_ARM_REL32 000000cc .LC15\n-0000173c 00001603 R_ARM_REL32 000000e8 .LC16\n-000017fc 0000b20a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n-00001a38 0000a30a R_ARM_THM_CALL 00000000 memset\n-00001a7c 0000a30a R_ARM_THM_CALL 00000000 memset\n-00001b0e 0000a30a R_ARM_THM_CALL 00000000 memset\n-00001b50 00005e03 R_ARM_REL32 00000000 .rodata\n-00001b9e 0000a30a R_ARM_THM_CALL 00000000 memset\n-00001c42 0000a30a R_ARM_THM_CALL 00000000 memset\n-00001f90 00000203 R_ARM_REL32 00000000 .bss\n-00001f94 00000203 R_ARM_REL32 00000000 .bss\n-00001f98 00000203 R_ARM_REL32 00000000 .bss\n-00002058 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002076 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002090 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000020a6 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000020f8 0000b30a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n-00002520 0000b40a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-0000256e 0000b50a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_localxc\n-00002584 0000b60a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_decusp\n-000025a2 0000b70a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n-00002948 00000e03 R_ARM_REL32 00000020 .LC8\n-0000294c 00000f03 R_ARM_REL32 00000024 .LC9\n-00002950 00000c03 R_ARM_REL32 00000018 .LC6\n-00002954 00000d03 R_ARM_REL32 0000001c .LC7\n-00002958 00000203 R_ARM_REL32 00000000 .bss\n-0000295c 00000203 R_ARM_REL32 00000000 .bss\n-00002960 00000203 R_ARM_REL32 00000000 .bss\n-00002964 00000203 R_ARM_REL32 00000000 .bss\n-00002968 00000203 R_ARM_REL32 00000000 .bss\n-0000296c 00000203 R_ARM_REL32 00000000 .bss\n-00002970 00000203 R_ARM_REL32 00000000 .bss\n-00002974 00000203 R_ARM_REL32 00000000 .bss\n-00002978 00000203 R_ARM_REL32 00000000 .bss\n-00002da8 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00002dc2 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00002ddc 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00002df8 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000315c 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000316e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003182 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003196 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003364 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000337e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003398 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-000033b2 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003690 00000103 R_ARM_REL32 00000000 .data\n-00003694 00000203 R_ARM_REL32 00000000 .bss\n-00003698 00000203 R_ARM_REL32 00000000 .bss\n-0000369c 00000203 R_ARM_REL32 00000000 .bss\n-000036a0 00000203 R_ARM_REL32 00000000 .bss\n-000036bc 0000b80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n-000036ce 00009f0a R_ARM_THM_CALL 00000000 free\n-000036d6 00009f0a R_ARM_THM_CALL 00000000 free\n-000036de 00009f0a R_ARM_THM_CALL 00000000 free\n-0000373c 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-0000374e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-000037c2 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000037cc 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000037f0 0000b90a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_addmeshdata\n-00003806 0000b90a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_addmeshdata\n-00003844 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00003850 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-000038ac 0000ba0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_l3\n-00003a18 00000103 R_ARM_REL32 00000000 .data\n-00003a1c 00000203 R_ARM_REL32 00000000 .bss\n-00003a20 00000203 R_ARM_REL32 00000000 .bss\n-00003a24 00000203 R_ARM_REL32 00000000 .bss\n-00003a28 00005e03 R_ARM_REL32 00000000 .rodata\n-00003a2c 00002d03 R_ARM_REL32 00000378 .LC42\n-00003d16 0000bb0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n-00003d28 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-00003dcc 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n-00003dfc 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003e2e 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003e66 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00003e8c 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003eb2 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003ed0 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003eee 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003f0c 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003f2a 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003f48 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-00003f74 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-00003fd4 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00003ffe 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00004008 0000c10a R_ARM_THM_CALL 00000000 __gridxc_chkgmx_MOD_meshkcut\n-00004016 0000c20a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n-0000402a 0000a30a R_ARM_THM_CALL 00000000 memset\n-00004072 0000b70a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n-000042c0 0000b70a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n-00004798 00000203 R_ARM_REL32 00000000 .bss\n-0000479c 00000103 R_ARM_REL32 00000000 .data\n-000047a0 00005e03 R_ARM_REL32 00000000 .rodata\n-000047a4 00000203 R_ARM_REL32 00000000 .bss\n-000047a8 00002e03 R_ARM_REL32 00000388 .LC43\n-000047ac 00002f03 R_ARM_REL32 00000394 .LC44\n-000047b0 00003003 R_ARM_REL32 000003a0 .LC46\n-000047b4 00003103 R_ARM_REL32 000003b0 .LC47\n-000047b8 00003203 R_ARM_REL32 000003c0 .LC48\n-000047bc 00003303 R_ARM_REL32 000003cc .LC49\n-000047c0 00003403 R_ARM_REL32 000003d8 .LC50\n-000047c4 00003503 R_ARM_REL32 000003e4 .LC51\n-000047c8 00003603 R_ARM_REL32 000003f0 .LC52\n-000047cc 00003703 R_ARM_REL32 000003fc .LC53\n-000047d0 00003803 R_ARM_REL32 00000408 .LC54\n-000047d4 00003903 R_ARM_REL32 00000414 .LC55\n-000047d8 00000203 R_ARM_REL32 00000000 .bss\n-000047dc 00000203 R_ARM_REL32 00000000 .bss\n-000047e0 00000203 R_ARM_REL32 00000000 .bss\n-000047e4 00000203 R_ARM_REL32 00000000 .bss\n-000047e8 00000203 R_ARM_REL32 00000000 .bss\n-000047ec 00000203 R_ARM_REL32 00000000 .bss\n-000047f0 00000203 R_ARM_REL32 00000000 .bss\n-000047f4 00000203 R_ARM_REL32 00000000 .bss\n-000047f8 00000203 R_ARM_REL32 00000000 .bss\n-000048be 0000c30a R_ARM_THM_CALL 00000000 __gridxc_fftr_MOD_fftr2k\n-00004a0e 0000b20a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n-00004a1a 0000a30a R_ARM_THM_CALL 00000000 memset\n-00004c20 00000103 R_ARM_REL32 00000000 .data\n-00004c24 00005e03 R_ARM_REL32 00000000 .rodata\n-00004c28 00000203 R_ARM_REL32 00000000 .bss\n-00004c2c 00000203 R_ARM_REL32 00000000 .bss\n-00004c3e 0000c40a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_phi\n-00004d9a 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00004e7c 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00004f64 0000c50a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n-00004f80 00009f0a R_ARM_THM_CALL 00000000 free\n-00004f94 00009f0a R_ARM_THM_CALL 00000000 free\n-00005184 00000203 R_ARM_REL32 00000000 .bss\n-00005188 00000203 R_ARM_REL32 00000000 .bss\n-0000518c 00000203 R_ARM_REL32 00000000 .bss\n-00005190 00000203 R_ARM_REL32 00000000 .bss\n-00005194 00000203 R_ARM_REL32 00000000 .bss\n-00005198 00000203 R_ARM_REL32 00000000 .bss\n-0000519c 00000203 R_ARM_REL32 00000000 .bss\n-000051a0 00000203 R_ARM_REL32 00000000 .bss\n-000051a4 00000203 R_ARM_REL32 00000000 .bss\n-00005222 0000a20a R_ARM_THM_CALL 00000000 malloc\n-00005308 0000a20a R_ARM_THM_CALL 00000000 malloc\n-000053f0 0000c50a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n-00005428 00009f0a R_ARM_THM_CALL 00000000 free\n-00005434 00009f0a R_ARM_THM_CALL 00000000 free\n-000056bc 00000203 R_ARM_REL32 00000000 .bss\n-000056c0 00000203 R_ARM_REL32 00000000 .bss\n-000056c4 00000203 R_ARM_REL32 00000000 .bss\n-000056c8 00000203 R_ARM_REL32 00000000 .bss\n-000056cc 00000203 R_ARM_REL32 00000000 .bss\n-000056d0 00000203 R_ARM_REL32 00000000 .bss\n-000056d4 00000203 R_ARM_REL32 00000000 .bss\n-00005778 0000c60a R_ARM_THM_CALL 00000000 __gridxc_fftr_MOD_fftk2r\n-0000592e 0000b20a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n-0000593a 0000a30a R_ARM_THM_CALL 00000000 memset\n-00005b32 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00005b70 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00005bc4 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00005c94 00000103 R_ARM_REL32 00000000 .data\n-00005c98 00005e03 R_ARM_REL32 00000000 .rodata\n-00005c9c 00000203 R_ARM_REL32 00000000 .bss\n-00005ca0 00005e03 R_ARM_REL32 00000000 .rodata\n-00005ca4 00000203 R_ARM_REL32 00000000 .bss\n-00005ca8 00001d03 R_ARM_REL32 00000278 .LC24\n-00005cac 00001f03 R_ARM_REL32 00000298 .LC27\n-00005cb0 00002003 R_ARM_REL32 000002a8 .LC28\n-00005cb4 00000203 R_ARM_REL32 00000000 .bss\n-00005cb8 0000a11a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00005cbc 00001b03 R_ARM_REL32 00000210 .LC22\n-00005cc0 00001c03 R_ARM_REL32 00000244 .LC23\n-00005cc4 00000103 R_ARM_REL32 00000000 .data\n-00005cc8 00000103 R_ARM_REL32 00000000 .data\n-00005ccc 0000b11a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n-00005ce8 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n-00005cfe 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-00005d54 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00005d86 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00005d90 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00005ec0 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00006030 00000103 R_ARM_REL32 00000000 .data\n-00006034 00005e03 R_ARM_REL32 00000000 .rodata\n-00006038 00000203 R_ARM_REL32 00000000 .bss\n-0000603c 00001d03 R_ARM_REL32 00000278 .LC24\n-00006040 00001e03 R_ARM_REL32 00000288 .LC26\n-00006168 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n-0000617c 0000c70a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n-00006192 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000062f4 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-0000633c 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-0000637c 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000063be 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000063fa 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00006438 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-0000647a 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000064bc 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000064fc 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00006538 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00006578 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000065b4 0000c00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00006b18 00000203 R_ARM_REL32 00000000 .bss\n-00006b1c 00000103 R_ARM_REL32 00000000 .data\n-00006b20 00000203 R_ARM_REL32 00000000 .bss\n-00006b24 00000103 R_ARM_REL32 00000000 .data\n-00006b28 00001e03 R_ARM_REL32 00000288 .LC26\n-00006b2c 00001d03 R_ARM_REL32 00000278 .LC24\n-00006b30 00005e03 R_ARM_REL32 00000000 .rodata\n-00006b34 00000203 R_ARM_REL32 00000000 .bss\n-00006b38 00002103 R_ARM_REL32 000002b8 .LC29\n-00006b3c 00002203 R_ARM_REL32 000002c8 .LC30\n-00006b40 00002303 R_ARM_REL32 000002d8 .LC31\n-00006b44 00002403 R_ARM_REL32 000002e8 .LC32\n-00006b48 00002503 R_ARM_REL32 000002f8 .LC33\n-00006b4c 00002603 R_ARM_REL32 00000308 .LC34\n-00006b50 00002703 R_ARM_REL32 00000318 .LC35\n-00006b54 00002803 R_ARM_REL32 00000328 .LC36\n-00006b58 00002903 R_ARM_REL32 00000338 .LC37\n-00006b5c 00002a03 R_ARM_REL32 00000348 .LC38\n-00006b60 00002b03 R_ARM_REL32 00000358 .LC39\n-00006b64 00002c03 R_ARM_REL32 00000368 .LC40\n-00006b68 00000203 R_ARM_REL32 00000000 .bss\n-00006b9a 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_samemeshdistr\n-00006daa 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00006e3c 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00006eb4 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00007108 00000103 R_ARM_REL32 00000000 .data\n-0000710c 00000203 R_ARM_REL32 00000000 .bss\n-00007110 00000203 R_ARM_REL32 00000000 .bss\n-00007114 00000203 R_ARM_REL32 00000000 .bss\n-00007272 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000728a 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000729c 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000072b6 0000980a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_alloc_default\n-0000734e 0000c90a R_ARM_THM_CALL 00000000 __gridxc_moreparallelsubs_MOD_miscallreducedouble\n-000073d0 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000073e2 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000073f4 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00007406 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00007418 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000742a 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000743c 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000744c 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000745e 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00007470 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00007482 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00007494 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000074ae 0000c80a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000074c0 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-000074d2 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-000074e4 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-000074f6 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-00007508 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-0000751a 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-0000752c 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-0000753e 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-00007550 0000c70a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n-00007562 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n-00007574 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n-00007586 0000cc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_l3\n-0000758c 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00007658 00000203 R_ARM_REL32 00000000 .bss\n-0000765c 00000203 R_ARM_REL32 00000000 .bss\n-00007660 00002003 R_ARM_REL32 000002a8 .LC28\n-00007664 00000203 R_ARM_REL32 00000000 .bss\n-00007668 00001f03 R_ARM_REL32 00000298 .LC27\n-0000766c 00001d03 R_ARM_REL32 00000278 .LC24\n-00007670 00000103 R_ARM_REL32 00000000 .data\n-00007674 00003a03 R_ARM_REL32 00000420 .LC56\n-00007678 00000703 R_ARM_REL32 00000000 .LC0\n-0000767c 0000cd1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n-00007680 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00007684 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00007688 00002c03 R_ARM_REL32 00000368 .LC40\n-0000768c 00002b03 R_ARM_REL32 00000358 .LC39\n-00007690 00002a03 R_ARM_REL32 00000348 .LC38\n-00007694 00002903 R_ARM_REL32 00000338 .LC37\n-00007698 00002803 R_ARM_REL32 00000328 .LC36\n-0000769c 00002703 R_ARM_REL32 00000318 .LC35\n-000076a0 00002603 R_ARM_REL32 00000308 .LC34\n-000076a4 00002503 R_ARM_REL32 000002f8 .LC33\n-000076a8 00002403 R_ARM_REL32 000002e8 .LC32\n-000076ac 00002303 R_ARM_REL32 000002d8 .LC31\n-000076b0 00002203 R_ARM_REL32 000002c8 .LC30\n-000076b4 00002103 R_ARM_REL32 000002b8 .LC29\n-000076b8 00000203 R_ARM_REL32 00000000 .bss\n-000076bc 00003903 R_ARM_REL32 00000414 .LC55\n-000076c0 00003803 R_ARM_REL32 00000408 .LC54\n-000076c4 00003703 R_ARM_REL32 000003fc .LC53\n-000076c8 00003603 R_ARM_REL32 000003f0 .LC52\n-000076cc 00003503 R_ARM_REL32 000003e4 .LC51\n-000076d0 00003403 R_ARM_REL32 000003d8 .LC50\n-000076d4 00003303 R_ARM_REL32 000003cc .LC49\n-000076d8 00003203 R_ARM_REL32 000003c0 .LC48\n-000076dc 00003103 R_ARM_REL32 000003b0 .LC47\n-000076e0 00003003 R_ARM_REL32 000003a0 .LC46\n-000076e4 00002f03 R_ARM_REL32 00000394 .LC44\n-000076e8 00002e03 R_ARM_REL32 00000388 .LC43\n-000076ec 00002d03 R_ARM_REL32 00000378 .LC42\n-000076f8 0000af0a R_ARM_THM_CALL 00000000 memcpy\n-00007704 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000172c 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00001738 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00001768 0000a91a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000176c 00001903 R_ARM_REL32 000001ac .LC20\n+00001826 0000b10a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n+00001ada 0000a10a R_ARM_THM_CALL 00000000 memset\n+00001b20 0000a10a R_ARM_THM_CALL 00000000 memset\n+00001b60 00005d03 R_ARM_REL32 00000000 .rodata\n+00001bc8 0000a10a R_ARM_THM_CALL 00000000 memset\n+00001c3e 0000a10a R_ARM_THM_CALL 00000000 memset\n+00001cd8 0000a10a R_ARM_THM_CALL 00000000 memset\n+00002028 00000203 R_ARM_REL32 00000000 .bss\n+0000202c 00000203 R_ARM_REL32 00000000 .bss\n+00002030 00000203 R_ARM_REL32 00000000 .bss\n+000020e4 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002100 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002118 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000212c 00009a0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000217e 0000b20a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n+00002390 00000e03 R_ARM_REL32 00000020 .LC8\n+00002394 00000f03 R_ARM_REL32 00000024 .LC9\n+00002398 00000c03 R_ARM_REL32 00000018 .LC6\n+0000239c 00000d03 R_ARM_REL32 0000001c .LC7\n+000023a0 00000203 R_ARM_REL32 00000000 .bss\n+000023a4 00000203 R_ARM_REL32 00000000 .bss\n+000023a8 00000203 R_ARM_REL32 00000000 .bss\n+000025cc 0000b30a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00002616 0000b40a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_localxc\n+0000262c 0000b50a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_decusp\n+0000264a 0000b60a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n+000029d0 00000203 R_ARM_REL32 00000000 .bss\n+000029d4 00000203 R_ARM_REL32 00000000 .bss\n+000029d8 00000203 R_ARM_REL32 00000000 .bss\n+000029dc 00000203 R_ARM_REL32 00000000 .bss\n+000029e0 00000203 R_ARM_REL32 00000000 .bss\n+000029e4 00000203 R_ARM_REL32 00000000 .bss\n+00002b02 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00002cd8 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00002e84 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00002e9e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00002eb8 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00002ed2 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000322a 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000323c 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003250 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003266 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000343a 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003454 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000346e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003488 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+0000359a 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000036de 0000920a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003790 00000103 R_ARM_REL32 00000000 .data\n+00003794 00000203 R_ARM_REL32 00000000 .bss\n+00003798 00000203 R_ARM_REL32 00000000 .bss\n+0000379c 00000203 R_ARM_REL32 00000000 .bss\n+000037a0 00000203 R_ARM_REL32 00000000 .bss\n+000037a4 00000203 R_ARM_REL32 00000000 .bss\n+000037c0 0000b70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n+000037d2 00009f0a R_ARM_THM_CALL 00000000 free\n+000037da 00009f0a R_ARM_THM_CALL 00000000 free\n+000037e2 00009f0a R_ARM_THM_CALL 00000000 free\n+0000384a 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003858 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+000038ca 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+000038d8 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+000038f2 0000b80a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_addmeshdata\n+0000390a 0000b80a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_addmeshdata\n+00003964 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003970 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+000039d0 0000b90a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_l3\n+00003b30 00000103 R_ARM_REL32 00000000 .data\n+00003b34 00000203 R_ARM_REL32 00000000 .bss\n+00003b38 00000203 R_ARM_REL32 00000000 .bss\n+00003b3c 00005d03 R_ARM_REL32 00000000 .rodata\n+00003b40 00002d03 R_ARM_REL32 00000378 .LC42\n+00003c54 0000ba0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n+00003c66 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00003d02 0000bb0a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_get_qmesh\n+00003d34 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003d66 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003da0 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00003dc6 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003df0 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003e0e 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003e2a 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003e48 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003e64 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003e80 0000bc0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00003eac 0000bd0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00003f04 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00003f2e 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00003f38 0000c00a R_ARM_THM_CALL 00000000 __gridxc_chkgmx_MOD_meshkcut\n+00003f42 0000c10a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_kcut\n+00003f56 0000a10a R_ARM_THM_CALL 00000000 memset\n+00003f9e 0000b60a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n+000041f8 0000b60a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_theta\n+00004448 00000203 R_ARM_REL32 00000000 .bss\n+0000444c 00000103 R_ARM_REL32 00000000 .data\n+00004450 00005d03 R_ARM_REL32 00000000 .rodata\n+00004454 00000203 R_ARM_REL32 00000000 .bss\n+00004458 00002e03 R_ARM_REL32 00000388 .LC43\n+0000445c 00002f03 R_ARM_REL32 00000394 .LC44\n+00004460 00003003 R_ARM_REL32 000003a0 .LC46\n+00004464 00003103 R_ARM_REL32 000003b0 .LC47\n+00004468 00003203 R_ARM_REL32 000003c0 .LC48\n+0000446c 00003303 R_ARM_REL32 000003cc .LC49\n+00004470 00003403 R_ARM_REL32 000003d8 .LC50\n+00004474 00003503 R_ARM_REL32 000003e4 .LC51\n+00004478 00003603 R_ARM_REL32 000003f0 .LC52\n+0000447c 00003703 R_ARM_REL32 000003fc .LC53\n+00004480 00003803 R_ARM_REL32 00000408 .LC54\n+00004484 00003903 R_ARM_REL32 00000414 .LC55\n+00004488 00000203 R_ARM_REL32 00000000 .bss\n+0000448c 00000203 R_ARM_REL32 00000000 .bss\n+00004490 00000203 R_ARM_REL32 00000000 .bss\n+00004494 00000203 R_ARM_REL32 00000000 .bss\n+00004498 00000203 R_ARM_REL32 00000000 .bss\n+0000449c 00000203 R_ARM_REL32 00000000 .bss\n+000044a0 00000203 R_ARM_REL32 00000000 .bss\n+000044a4 00000203 R_ARM_REL32 00000000 .bss\n+00004552 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004592 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+000045ea 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+000046c0 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n+000046d6 0000ab0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+0000472c 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+0000475e 0000be0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00004768 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00004884 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+000049f8 00005d03 R_ARM_REL32 00000000 .rodata\n+000049fc 00000203 R_ARM_REL32 00000000 .bss\n+00004a00 00001d03 R_ARM_REL32 00000278 .LC24\n+00004a04 00001f03 R_ARM_REL32 00000298 .LC27\n+00004a08 00002003 R_ARM_REL32 000002a8 .LC28\n+00004a0c 00000203 R_ARM_REL32 00000000 .bss\n+00004a10 0000a91a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00004a14 00001b03 R_ARM_REL32 00000210 .LC22\n+00004a18 00001c03 R_ARM_REL32 00000244 .LC23\n+00004a1c 00000103 R_ARM_REL32 00000000 .data\n+00004a20 00000103 R_ARM_REL32 00000000 .data\n+00004a24 0000b01a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+00004a28 00000103 R_ARM_REL32 00000000 .data\n+00004a2c 00005d03 R_ARM_REL32 00000000 .rodata\n+00004a30 00000203 R_ARM_REL32 00000000 .bss\n+00004a34 00001d03 R_ARM_REL32 00000278 .LC24\n+00004a38 00001e03 R_ARM_REL32 00000288 .LC26\n+00004b58 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_setmeshdistr\n+00004b6c 0000c20a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n+00004b82 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00004ce0 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004d28 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004d68 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004da6 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004de2 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004e20 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004e62 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004ea4 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004ee4 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004f20 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004f5e 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00004f9c 0000bf0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00005028 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00005034 0000af0a R_ARM_THM_CALL 00000000 memcpy\n+00005498 00000203 R_ARM_REL32 00000000 .bss\n+0000549c 00000103 R_ARM_REL32 00000000 .data\n+000054a0 00000203 R_ARM_REL32 00000000 .bss\n+000054a4 00000103 R_ARM_REL32 00000000 .data\n+000054a8 00001e03 R_ARM_REL32 00000288 .LC26\n+000054ac 00001d03 R_ARM_REL32 00000278 .LC24\n+000054b0 00005d03 R_ARM_REL32 00000000 .rodata\n+000054b4 00002103 R_ARM_REL32 000002b8 .LC29\n+000054b8 00000203 R_ARM_REL32 00000000 .bss\n+000054bc 00002203 R_ARM_REL32 000002c8 .LC30\n+000054c0 00002303 R_ARM_REL32 000002d8 .LC31\n+000054c4 00002403 R_ARM_REL32 000002e8 .LC32\n+000054c8 00002503 R_ARM_REL32 000002f8 .LC33\n+000054cc 00002603 R_ARM_REL32 00000308 .LC34\n+000054d0 00002703 R_ARM_REL32 00000318 .LC35\n+000054d4 00002803 R_ARM_REL32 00000328 .LC36\n+000054d8 00002903 R_ARM_REL32 00000338 .LC37\n+000054dc 00002a03 R_ARM_REL32 00000348 .LC38\n+000054e0 00002b03 R_ARM_REL32 00000358 .LC39\n+000054e4 00002c03 R_ARM_REL32 00000368 .LC40\n+000054e8 00000203 R_ARM_REL32 00000000 .bss\n+000055f2 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_samemeshdistr\n+00005a86 0000c40a R_ARM_THM_CALL 00000000 __gridxc_fftr_MOD_fftr2k\n+00005bac 0000b10a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n+00005bb8 0000a10a R_ARM_THM_CALL 00000000 memset\n+00005dc8 0000c50a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_phi\n+00005f1e 0000a00a R_ARM_THM_CALL 00000000 malloc\n+00006004 0000a00a R_ARM_THM_CALL 00000000 malloc\n+000060e2 0000c60a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n+00006106 00009f0a R_ARM_THM_CALL 00000000 free\n+0000611a 00009f0a R_ARM_THM_CALL 00000000 free\n+00006324 00000103 R_ARM_REL32 00000000 .data\n+00006328 00000203 R_ARM_REL32 00000000 .bss\n+0000632c 00000203 R_ARM_REL32 00000000 .bss\n+00006330 00000203 R_ARM_REL32 00000000 .bss\n+00006334 00000203 R_ARM_REL32 00000000 .bss\n+00006338 00000103 R_ARM_REL32 00000000 .data\n+0000633c 00005d03 R_ARM_REL32 00000000 .rodata\n+00006340 00000203 R_ARM_REL32 00000000 .bss\n+00006344 00000203 R_ARM_REL32 00000000 .bss\n+00006348 00000203 R_ARM_REL32 00000000 .bss\n+0000634c 00000203 R_ARM_REL32 00000000 .bss\n+00006350 00000203 R_ARM_REL32 00000000 .bss\n+00006354 00000203 R_ARM_REL32 00000000 .bss\n+00006358 00000203 R_ARM_REL32 00000000 .bss\n+0000635c 00000203 R_ARM_REL32 00000000 .bss\n+00006360 00000203 R_ARM_REL32 00000000 .bss\n+00006364 00000203 R_ARM_REL32 00000000 .bss\n+00006368 00000203 R_ARM_REL32 00000000 .bss\n+000063e2 0000a00a R_ARM_THM_CALL 00000000 malloc\n+000064cc 0000a00a R_ARM_THM_CALL 00000000 malloc\n+000065ba 0000c60a R_ARM_THM_CALL 00000000 _gfortran_matmul_r8\n+000065f2 00009f0a R_ARM_THM_CALL 00000000 free\n+000065fe 00009f0a R_ARM_THM_CALL 00000000 free\n+0000689c 00000203 R_ARM_REL32 00000000 .bss\n+000068a0 00000203 R_ARM_REL32 00000000 .bss\n+000068a4 00000203 R_ARM_REL32 00000000 .bss\n+000068a8 00000203 R_ARM_REL32 00000000 .bss\n+000068ac 00000203 R_ARM_REL32 00000000 .bss\n+000068b0 00000203 R_ARM_REL32 00000000 .bss\n+0000694e 0000c70a R_ARM_THM_CALL 00000000 __gridxc_fftr_MOD_fftk2r\n+00006bae 0000b10a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n+00006bba 0000a10a R_ARM_THM_CALL 00000000 memset\n+00006e5c 00000203 R_ARM_REL32 00000000 .bss\n+00006e60 00000103 R_ARM_REL32 00000000 .data\n+00006e64 00005d03 R_ARM_REL32 00000000 .rodata\n+00006fc0 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00006fd8 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00006fea 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007000 0000980a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_alloc_default\n+00007086 0000c80a R_ARM_THM_CALL 00000000 __gridxc_moreparallelsubs_MOD_miscallreducedouble\n+0000710a 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+0000711c 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+0000712e 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007140 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007152 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007164 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007176 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007186 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00007198 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000071aa 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000071bc 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000071ce 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000071e8 0000c30a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000071fa 0000c90a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+0000720c 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+0000721e 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+00007230 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+00007242 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+00007254 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+00007266 0000c90a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+00007278 0000c90a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+0000728a 0000c20a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n+0000729c 0000c90a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n+000072ae 0000ca0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n+000072c0 0000cb0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_l3\n+000072c6 0000930a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000072d6 0000cc0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000072e6 0000cc0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000072f8 0000cc0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00007350 00000203 R_ARM_REL32 00000000 .bss\n+00007354 00000203 R_ARM_REL32 00000000 .bss\n+00007358 00002003 R_ARM_REL32 000002a8 .LC28\n+0000735c 00000203 R_ARM_REL32 00000000 .bss\n+00007360 00001f03 R_ARM_REL32 00000298 .LC27\n+00007364 00001d03 R_ARM_REL32 00000278 .LC24\n+00007368 00000103 R_ARM_REL32 00000000 .data\n+0000736c 00003a03 R_ARM_REL32 00000420 .LC56\n+00007370 0000cd1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n+00007374 00000703 R_ARM_REL32 00000000 .LC0\n+00007378 00009419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000737c 0000951a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00007380 00002c03 R_ARM_REL32 00000368 .LC40\n+00007384 00002b03 R_ARM_REL32 00000358 .LC39\n+00007388 00002a03 R_ARM_REL32 00000348 .LC38\n+0000738c 00002903 R_ARM_REL32 00000338 .LC37\n+00007390 00002803 R_ARM_REL32 00000328 .LC36\n+00007394 00002703 R_ARM_REL32 00000318 .LC35\n+00007398 00002603 R_ARM_REL32 00000308 .LC34\n+0000739c 00002503 R_ARM_REL32 000002f8 .LC33\n+000073a0 00002403 R_ARM_REL32 000002e8 .LC32\n+000073a4 00002303 R_ARM_REL32 000002d8 .LC31\n+000073a8 00002203 R_ARM_REL32 000002c8 .LC30\n+000073ac 00002103 R_ARM_REL32 000002b8 .LC29\n+000073b0 00000203 R_ARM_REL32 00000000 .bss\n+000073b4 00003903 R_ARM_REL32 00000414 .LC55\n+000073b8 00003803 R_ARM_REL32 00000408 .LC54\n+000073bc 00003703 R_ARM_REL32 000003fc .LC53\n+000073c0 00003603 R_ARM_REL32 000003f0 .LC52\n+000073c4 00003503 R_ARM_REL32 000003e4 .LC51\n+000073c8 00003403 R_ARM_REL32 000003d8 .LC50\n+000073cc 00003303 R_ARM_REL32 000003cc .LC49\n+000073d0 00003203 R_ARM_REL32 000003c0 .LC48\n+000073d4 00003103 R_ARM_REL32 000003b0 .LC47\n+000073d8 00003003 R_ARM_REL32 000003a0 .LC46\n+000073dc 00002f03 R_ARM_REL32 00000394 .LC44\n+000073e0 00002e03 R_ARM_REL32 00000388 .LC43\n+000073e4 00002d03 R_ARM_REL32 00000378 .LC42\n+000073e8 00001503 R_ARM_REL32 000000cc .LC15\n+000073ec 00001703 R_ARM_REL32 0000013c .LC17\n+000073f0 00001503 R_ARM_REL32 000000cc .LC15\n+000073f4 00001703 R_ARM_REL32 0000013c .LC17\n+000073f8 00001503 R_ARM_REL32 000000cc .LC15\n+000073fc 00001603 R_ARM_REL32 000000e8 .LC16\n+000074ac 0000ad0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00007532 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+000075a0 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+000075a8 00000203 R_ARM_REL32 00000000 .bss\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,22 +1,18 @@\n-hxcXh8cXj\n-g9jygyj9g\n-7I6\"PFyD\n-!\"MIPFyD\n-!\"(IPFyD\n-*F[FIF0F\n-F#I\"F#HyDxD\n-F!I\"F!HyDxD\n+i{g;j;g{j;e\n K F)F{D2F\n-DEH\"|D!F\n-CF*FYFHF\n-H9BF)F{D\n-$9BF)F{D\n-\tCF|DBFxD\n-%zj+F)F(F\n+t6JF)F{D\n+\\6JF)F{D\n+(6JF)F{D\n+l\tCF|DBFxD\n+%:j+F)F(F\n+%vI*F|D\t#\n+FFI\"FFHyDxD\n+FDI\"FDHyDxD\n+ABI\"FBHyDxD\n /build/reproducible-path/libgridxc-2.0.1/src/cellxc.F90\n cellXC ERROR: Unknown functional \n cellXC ERROR: d2Exc/dn2 not implemented for built-in \n Error allocating %lu bytes\n In file '/build/reproducible-path/libgridxc-2.0.1/src/cellxc.F90', around line 393\n In file '/build/reproducible-path/libgridxc-2.0.1/src/cellxc.F90', around line 395\n Bad libxc code in \n@@ -83,40 +79,40 @@\n vleft3.28\n vrght3.27\n dleft.26\n drght.25\n nonempty.22\n dtdgd.18\n dphidk.17\n+__aeabi_idiv\n __stack_chk_fail\n _GLOBAL_OFFSET_TABLE_\n __stack_chk_guard\n __gridxc_cell_MOD_cellxc\n __gridxc_xcmod_MOD_getxc\n __gridxc_alloc_MOD_alloc_default\n __gridxc_cellsubs_MOD_volcel\n _gfortran_compare_string\n _gfortran_st_write\n _gfortran_transfer_character_write\n _gfortran_st_write_done\n _gfortran_string_trim\n-__gridxc_sys_MOD_gridxc_timer_start\n-__gridxc_sys_MOD_die\n _gfortran_st_read\n _gfortran_transfer_integer\n _gfortran_st_read_done\n _gfortran_concat_string\n __xc_f03_lib_m_MOD_xc_f03_func_init\n __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+__gridxc_sys_MOD_gridxc_timer_start\n+__gridxc_sys_MOD_die\n __gridxc_mesh3d_MOD_setmeshdistr\n __gridxc_mesh3d_MOD_mymeshbox\n __gridxc_mesh3d_MOD_samemeshdistr\n __gridxc_mesh3d_MOD_associatemeshtask\n __gridxc_mesh3d_MOD_copymeshdata\n-_gfortran_os_error_at\n __gridxc_config_MOD_gridxc_totnodes\n __gridxc_cellsubs_MOD_reclat\n __gridxc_lda_MOD_ldaxc\n __gridxc_gga_MOD_ggaxc\n __gridxc_vdwxc_MOD_vdw_localxc\n __gridxc_vdwxc_MOD_vdw_decusp\n __gridxc_vdwxc_MOD_vdw_theta\n@@ -127,23 +123,24 @@\n __gridxc_vdwxc_MOD_vdw_get_qmesh\n __gridxc_alloc_MOD_realloc_d1\n __gridxc_alloc_MOD_realloc_d2\n __gridxc_alloc_MOD_realloc_d3\n __gridxc_alloc_MOD_realloc_d4\n __gridxc_chkgmx_MOD_meshkcut\n __gridxc_vdwxc_MOD_vdw_set_kcut\n+__gridxc_alloc_MOD_dealloc_d3\n+__gridxc_alloc_MOD_dealloc_d4\n __gridxc_fftr_MOD_fftr2k\n __gridxc_vdwxc_MOD_vdw_phi\n _gfortran_matmul_r8\n __gridxc_fftr_MOD_fftk2r\n-__gridxc_alloc_MOD_dealloc_d3\n-__gridxc_alloc_MOD_dealloc_d4\n __gridxc_moreparallelsubs_MOD_miscallreducedouble\n __gridxc_alloc_MOD_dealloc_d2\n __gridxc_alloc_MOD_dealloc_d1\n __gridxc_alloc_MOD_dealloc_l3\n+_gfortran_os_error_at\n __gridxc_sys_MOD_gridxc_timer_stop\n .shstrtab\n .rel.text\n .rodata.str1.4\n .note.GNU-stack\n .ARM.attributes\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -7,9874 +7,9758 @@\n getgraddens.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tlr, #4096\t@ 0x1000\n \tsub.w\tlr, sp, lr\n \tstr.w\tr0, [lr, #3856]\t@ 0xf10\n \tsub\tsp, #204\t@ 0xcc\n \tadd\tr7, sp, #0\n-\tmov\tr4, r2\n-\tldr.w\tr2, [pc, #1452]\t@ 5c4 \n+\tmov\tr6, r0\n+\tmov\tr0, r2\n+\tldr.w\tr2, [pc, #1504]\t@ 5fc \n \tmov\tr5, r1\n \tldr.w\tr1, [ip, #556]\t@ 0x22c\n-\tmov\tr6, r0\n-\tstr.w\tr3, [r7, #160]\t@ 0xa0\n+\tstr.w\tr3, [r7, #156]\t@ 0x9c\n \tadd\tr2, pc\n-\tldr.w\tr3, [pc, #1436]\t@ 5c8 \n-\tstr.w\tr1, [r7, #156]\t@ 0x9c\n-\tldr.w\tr9, [r1]\n-\tmov\tr1, sp\n+\tldr.w\tr3, [pc, #1492]\t@ 600 \n+\tmov\tr4, ip\n+\tstr.w\tr1, [r7, #152]\t@ 0x98\n+\tmov\tip, sp\n+\tldr\tr1, [r1, #0]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr.w\tr3, [r7, #196]\t@ 0xc4\n \tmov.w\tr3, #0\n-\tbic.w\tr3, r9, r9, asr #31\n+\tbic.w\tr3, r1, r1, asr #31\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n+\tcmp\tip, r2\n \tbeq.n\t66 \n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n+\tmov\tip, sp\n+\tcmp\tip, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n \tbne.n\t58 \n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t5b6 \n-\tmov\tfp, sp\n-\tcmp.w\tr9, #0\n-\tble.n\t9c \n-\tldr.w\tr3, [r7, #160]\t@ 0xa0\n+\tbne.w\t5f0 \n+\tmov\tsl, sp\n+\tcmp\tr1, #0\n+\tble.n\t9e \n+\tldr.w\tr3, [r7, #156]\t@ 0x9c\n \tmovs\tr2, #0\n-\tmovs\tr0, #0\n-\tmovs\tr1, #0\n+\tmov.w\tr8, #0\n+\tmov.w\tr9, #0\n \tadds\tr2, #1\n-\tstrd\tr0, r1, [r3]\n-\tstrd\tr0, r1, [r3, #8]\n-\tcmp\tr2, r9\n-\tstrd\tr0, r1, [r3, #16]\n+\tstrd\tr8, r9, [r3]\n+\tstrd\tr8, r9, [r3, #8]\n+\tcmp\tr2, r1\n+\tstrd\tr8, r9, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t86 \n+\tbne.n\t88 \n \tldr\tr3, [r6, #0]\n-\tstr.w\tr3, [r7, #172]\t@ 0xac\n-\tldr\tr3, [r5, #0]\n \tstr.w\tr3, [r7, #168]\t@ 0xa8\n-\tldr\tr3, [r4, #0]\n+\tldr\tr3, [r5, #0]\n \tstr.w\tr3, [r7, #164]\t@ 0xa4\n-\tldr.w\tr3, [pc, #1308]\t@ 5cc \n+\tldr\tr3, [r0, #0]\n+\tstr.w\tr3, [r7, #160]\t@ 0xa0\n+\tldr.w\tr3, [pc, #1360]\t@ 604 \n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tbne.w\t25e \n-\tldrd\tr3, r1, [ip, #540]\t@ 0x21c\n-\tadd.w\tr8, r7, #184\t@ 0xb8\n-\tldr.w\tr2, [ip, #536]\t@ 0x218\n-\tmovs\tr6, #1\n-\tstr.w\tr2, [r7, #148]\t@ 0x94\n-\tadd\tr3, r1\n-\tldr.w\tr2, [ip, #532]\t@ 0x214\n-\tlsls\tr1, r1, #3\n-\tstr.w\tr3, [r7, #136]\t@ 0x88\n-\tmovs\tr3, #3\n-\tstr.w\tr2, [r7, #144]\t@ 0x90\n-\tmovs\tr5, #2\n-\tldr.w\tr2, [ip, #528]\t@ 0x210\n-\tmov\tr4, r3\n-\tstr.w\tr2, [r7, #140]\t@ 0x8c\n-\tmovs\tr0, #4\n-\tldr.w\tr2, [ip, #552]\t@ 0x228\n-\tstr.w\tr2, [r7, #152]\t@ 0x98\n-\tmvn.w\tsl, #2\n-\tadd.w\tr2, ip, r3, lsl #3\n+\tbne.w\t290 \n+\tldrd\tr3, r6, [r4, #540]\t@ 0x21c\n+\tmov.w\tfp, #3\n+\tldr.w\tlr, [r4, #552]\t@ 0x228\n+\tmov.w\tsl, #1\n+\tadd\tr3, r6\n \tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tstrd\tr1, r2, [r7, #176]\t@ 0xb0\n-\tldr.w\tr3, [r7, #172]\t@ 0xac\n-\tstr.w\tr3, [r7, #184]\t@ 0xb8\n-\tldr.w\tr3, [r7, #168]\t@ 0xa8\n-\tstr.w\tr3, [r7, #188]\t@ 0xbc\n-\tldr.w\tr3, [r7, #164]\t@ 0xa4\n-\tstr.w\tr3, [r7, #192]\t@ 0xc0\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n-\tldr.w\tfp, [r3]\n-\tldr.w\tr3, [r8]\n-\tcmp.w\tfp, #0\n-\tadd\tr3, sl\n-\tblt.n\t200 \n-\tcmp\tr3, #0\n-\tblt.n\t212 \n-\tsdiv\tlr, r3, fp\n-\tmls\tr3, fp, lr, r3\n-\tcmp.w\tr9, #0\n-\tstr.w\tr3, [r8]\n-\tble.n\t1e0 \n-\tldr.w\tr1, [r7, #136]\t@ 0x88\n-\tadd.w\tlr, r9, #1\n-\tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tmov.w\tfp, #1\n-\tldr.w\tr2, [r7, #192]\t@ 0xc0\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #148]\t@ 0x94\n-\tmla\tr9, r2, r1, r3\n-\tldr.w\tr3, [r7, #188]\t@ 0xbc\n+\tldr.w\tr3, [r4, #536]\t@ 0x218\n+\tlsls\tr6, r6, #3\n+\tstr.w\tr3, [r7, #144]\t@ 0x90\n+\tmov.w\tr9, #2\n+\tldr.w\tr3, [r4, #532]\t@ 0x214\n+\tmov\tr8, fp\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tldr.w\tr3, [r4, #528]\t@ 0x210\n+\tstr.w\tr3, [r7, #136]\t@ 0x88\n+\tadd.w\tr3, r7, #184\t@ 0xb8\n+\tstr.w\tr1, [r7, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tmvn.w\tr2, #2\n+\tadd.w\tr5, r4, fp, lsl #3\n+\tstr.w\tfp, [r7, #124]\t@ 0x7c\n+\tmov\tfp, r2\n+\tstr.w\tlr, [r7, #148]\t@ 0x94\n+\tldr.w\tr2, [r7, #168]\t@ 0xa8\n+\tstr.w\tr2, [r7, #184]\t@ 0xb8\n+\tldr.w\tr2, [r7, #164]\t@ 0xa4\n+\tstr.w\tr2, [r7, #188]\t@ 0xbc\n+\tldr.w\tr2, [r7, #160]\t@ 0xa0\n+\tstr.w\tr2, [r7, #192]\t@ 0xc0\n+\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tldr\tr0, [r2, #0]\n+\tldr.w\tr2, [r7, #176]\t@ 0xb0\n+\tcmp\tr0, #0\n+\tstr.w\tr0, [r7, #172]\t@ 0xac\n+\tldr\tr1, [r2, #0]\n+\tadd.w\tr2, fp, r1\n+\tmov\tr1, r0\n+\tblt.n\t21a \n+\tcmp\tr2, #0\n+\tblt.n\t23c \n+\tmov\tr0, r2\n+\tstr.w\tr2, [r7, #128]\t@ 0x80\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr2, [r7, #128]\t@ 0x80\n+\tmovs\tr3, #4\n+\tldr.w\tr1, [r7, #172]\t@ 0xac\n+\tmls\tr2, r1, r0, r2\n+\tldr.w\tr1, [r7, #176]\t@ 0xb0\n+\tstr\tr2, [r1, #0]\n+\tldr.w\tr2, [r7, #180]\t@ 0xb4\n+\tcmp\tr2, #0\n+\tble.n\t202 \n+\tmov\tr0, r2\n+\tldr.w\tr1, [r7, #132]\t@ 0x84\n+\tldr.w\tr2, [r7, #184]\t@ 0xb8\n+\tadds\tr0, #1\n+\tmov\tlr, r0\n+\tldr.w\tr0, [r7, #192]\t@ 0xc0\n+\tadd\tr1, r2\n \tldr.w\tr2, [r7, #144]\t@ 0x90\n-\tmla\tr9, r3, r2, r9\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tldrd\tr1, r2, [r7, #176]\t@ 0xb0\n-\tadd.w\tr9, r3, r9, lsl #3\n-\tldr.w\tr3, [r7, #160]\t@ 0xa0\n-\tstr.w\tr6, [ip, #548]\t@ 0x224\n+\tmov.w\tip, #1\n+\tmla\tr1, r0, r2, r1\n+\tldr.w\tr2, [r7, #188]\t@ 0xbc\n+\tldr.w\tr0, [r7, #140]\t@ 0x8c\n+\tmla\tr1, r2, r0, r1\n+\tldr.w\tr2, [r7, #136]\t@ 0x88\n+\tmov\tr0, lr\n+\tadd.w\tr1, r2, r1, lsl #3\n+\tldr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstr.w\tsl, [r4, #548]\t@ 0x224\n+\tadd.w\tip, ip, #1\n+\tvldr\td5, [r2]\n+\tcmp\tr0, ip\n+\tvldr\td3, [r1]\n+\tadd.w\tr2, r2, #24\n+\tvldr\td4, [r5, #-24]\t@ 0xffffffe8\n+\tstr.w\tr9, [r4, #548]\t@ 0x224\n+\tvldr\td6, [r2, #-16]\n+\tvldr\td1, [r1]\n+\tvmla.f64\td5, d3, d4\n+\tvldr\td2, [r5, #-16]\n+\tstr.w\tr8, [r4, #548]\t@ 0x224\n+\tvldr\td7, [r2, #-8]\n+\tvldr\td4, [r1]\n+\tvmla.f64\td6, d1, d2\n+\tvldr\td3, [r5, #-8]\n+\tadd\tr1, r6\n+\tstr.w\tr3, [r4, #548]\t@ 0x224\n+\tvmla.f64\td7, d3, d4\n+\tvstr\td5, [r2, #-24]\t@ 0xffffffe8\n+\tvstr\td6, [r2, #-16]\n+\tvstr\td7, [r2, #-8]\n+\tbne.n\t1a8 \n \tadd.w\tfp, fp, #1\n-\tvldr\td18, [r3]\n-\tcmp\tlr, fp\n-\tvldr\td20, [r9]\n-\tadd.w\tr3, r3, #24\n-\tvldr\td19, [r2, #-24]\t@ 0xffffffe8\n-\tstr.w\tr5, [ip, #548]\t@ 0x224\n-\tvldr\td17, [r3, #-16]\n-\tvldr\td22, [r9]\n-\tvfma.f64\td18, d20, d19\n-\tvldr\td21, [r2, #-16]\n-\tstr.w\tr4, [ip, #548]\t@ 0x224\n-\tvldr\td16, [r3, #-8]\n-\tvldr\td19, [r9]\n-\tvfma.f64\td17, d22, d21\n-\tvldr\td20, [r2, #-8]\n-\tadd\tr9, r1\n-\tstr.w\tr0, [ip, #548]\t@ 0x224\n-\tvfma.f64\td16, d20, d19\n-\tvstr\td18, [r3, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r3, #-16]\n-\tvstr\td16, [r3, #-8]\n-\tbne.n\t182 \n-\tstrd\tr1, r2, [r7, #176]\t@ 0xb0\n-\tldr.w\tr3, [r7, #180]\t@ 0xb4\n-\tadd.w\tsl, sl, #1\n-\tcmp.w\tsl, #4\n-\tadd.w\tr3, r3, #72\t@ 0x48\n-\tstr.w\tr3, [r7, #180]\t@ 0xb4\n-\tbeq.n\t218 \n-\tldr.w\tr3, [r7, #156]\t@ 0x9c\n-\tldr.w\tr9, [r3]\n-\tb.n\t106 \n-\tadd.w\tlr, r3, #4294967295\t@ 0xffffffff\n-\tcmp\tr3, #0\n-\tble.n\t136 \n-\tsdiv\tlr, lr, fp\n-\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n-\tb.n\t13a \n-\tadd.w\tlr, r3, #1\n-\tb.n\t208 \n+\tadds\tr5, #72\t@ 0x48\n+\tcmp.w\tfp, #4\n+\tbeq.n\t244 \n \tldr.w\tr2, [r7, #152]\t@ 0x98\n-\tadd.w\tr8, r8, #4\n-\tldr.w\tr3, [r7, #132]\t@ 0x84\n+\tldr\tr2, [r2, #0]\n+\tstr.w\tr2, [r7, #180]\t@ 0xb4\n+\tb.n\t112 \n+\tcmp\tr2, #0\n+\tit\tgt\n+\taddgt.w\tr0, r2, #4294967295\t@ 0xffffffff\n+\tble.n\t240 \n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tstr.w\tr2, [r7, #128]\t@ 0x80\n+\tldr\tr1, [r3, #0]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr2, [r7, #128]\t@ 0x80\n+\tsubs\tr0, #1\n+\tmovs\tr3, #4\n+\tb.n\t158 \n+\tadds\tr0, r2, #1\n+\tb.n\t224 \n+\tmov\tr1, r0\n+\tb.n\t148 \n+\tldr.w\tr2, [r7, #176]\t@ 0xb0\n+\tldr.w\tfp, [r7, #124]\t@ 0x7c\n+\tldr.w\tlr, [r7, #148]\t@ 0x94\n \tadds\tr2, #4\n-\tldr.w\tr1, [r7, #176]\t@ 0xb0\n-\tcmp\tr3, #9\n-\tstr.w\tr2, [r7, #152]\t@ 0x98\n-\tbeq.n\t23e \n-\tldr.w\tr2, [r7, #156]\t@ 0x9c\n-\tadds\tr3, #3\n-\tldr.w\tr9, [r2]\n-\tb.n\tf6 \n-\tldr\tr2, [pc, #912]\t@ (5d0 )\n-\tldr\tr3, [pc, #900]\t@ (5c8 )\n+\tcmp.w\tfp, #9\n+\tstr.w\tr2, [r7, #176]\t@ 0xb0\n+\tadd.w\tlr, lr, #4\n+\tbeq.n\t270 \n+\tldr.w\tr2, [r7, #152]\t@ 0x98\n+\tadd.w\tfp, fp, #3\n+\tldr\tr2, [r2, #0]\n+\tstr.w\tr2, [r7, #180]\t@ 0xb4\n+\tb.n\t100 \n+\tldr\tr2, [pc, #916]\t@ (608 )\n+\tldr\tr3, [pc, #908]\t@ (600 )\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [r7, #196]\t@ 0xc4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t5be \n+\tbne.w\t5f8 \n \tadds\tr7, #204\t@ 0xcc\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #884]\t@ (5d4 )\n-\tadd.w\tr6, r7, #184\t@ 0xb8\n-\tmov\tsl, ip\n-\tmov.w\tr8, #1\n+\tldr\tr3, [pc, #888]\t@ (60c )\n+\tadd.w\tip, r7, #184\t@ 0xb8\n+\tmov.w\tr9, #1\n \tadd\tr3, pc\n-\tldr\tr0, [r3, #0]\n-\tstr\tr0, [r7, #52]\t@ 0x34\n-\tldr\tr0, [r3, #4]\n-\tstr\tr0, [r7, #48]\t@ 0x30\n-\tldr\tr0, [r3, #36]\t@ 0x24\n-\tstr\tr0, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [r3, #48]\t@ 0x30\n-\tstr\tr0, [r7, #40]\t@ 0x28\n-\tldr\tr0, [r3, #60]\t@ 0x3c\n-\tstr\tr0, [r7, #36]\t@ 0x24\n-\tldr\tr0, [r3, #20]\n-\tstr\tr0, [r7, #60]\t@ 0x3c\n-\tldr\tr0, [r3, #72]\t@ 0x48\n-\tstr\tr0, [r7, #32]\n-\tldr\tr0, [r3, #76]\t@ 0x4c\n-\tstr\tr0, [r7, #28]\n-\tldr\tr0, [r3, #96]\t@ 0x60\n-\tstr\tr0, [r7, #24]\n-\tldr\tr0, [r3, #108]\t@ 0x6c\n-\tstr\tr0, [r7, #20]\n-\tldr\tr0, [r3, #120]\t@ 0x78\n-\tstr\tr0, [r7, #16]\n-\tldr.w\tr0, [r3, #132]\t@ 0x84\n-\tstr\tr0, [r7, #12]\n-\tldr\tr0, [r3, #92]\t@ 0x5c\n-\tldr.w\tr2, [r3, #204]\t@ 0xcc\n-\tldr.w\tr1, [r3, #164]\t@ 0xa4\n-\tstr\tr0, [r7, #56]\t@ 0x38\n-\tldr.w\tr0, [r3, #144]\t@ 0x90\n+\tldr\tr5, [r3, #0]\n+\tstr\tr5, [r7, #52]\t@ 0x34\n+\tldr\tr5, [r3, #4]\n+\tstr\tr5, [r7, #48]\t@ 0x30\n \tldr\tr5, [r3, #24]\n+\tstr\tr5, [r7, #44]\t@ 0x2c\n+\tldr\tr5, [r3, #36]\t@ 0x24\n+\tstr\tr5, [r7, #40]\t@ 0x28\n+\tldr\tr5, [r3, #48]\t@ 0x30\n+\tstr\tr5, [r7, #36]\t@ 0x24\n+\tldr\tr5, [r3, #60]\t@ 0x3c\n+\tstr\tr5, [r7, #32]\n+\tldr\tr5, [r3, #20]\n+\tstr\tr5, [r7, #60]\t@ 0x3c\n+\tldr\tr5, [r3, #72]\t@ 0x48\n+\tstr\tr5, [r7, #28]\n+\tldr\tr5, [r3, #76]\t@ 0x4c\n+\tstr\tr5, [r7, #24]\n+\tldr\tr5, [r3, #96]\t@ 0x60\n+\tstr\tr5, [r7, #20]\n+\tldr\tr5, [r3, #108]\t@ 0x6c\n+\tstr\tr5, [r7, #16]\n+\tldr\tr5, [r3, #120]\t@ 0x78\n+\tstr\tr5, [r7, #12]\n+\tldr.w\tr5, [r3, #132]\t@ 0x84\n+\tldr.w\tr2, [r3, #204]\t@ 0xcc\n+\tldr.w\tr0, [r3, #164]\t@ 0xa4\n+\tstr\tr5, [r7, #8]\n+\tldr\tr5, [r3, #92]\t@ 0x5c\n \tstr\tr2, [r7, #64]\t@ 0x40\n-\tmul.w\tlr, r2, r1\n-\tstr\tr1, [r7, #72]\t@ 0x48\n-\tstr\tr0, [r7, #68]\t@ 0x44\n-\tldr.w\tr0, [r3, #148]\t@ 0x94\n-\tstr\tr0, [r7, #88]\t@ 0x58\n-\tldr.w\tr0, [r3, #168]\t@ 0xa8\n-\tstr\tr0, [r7, #108]\t@ 0x6c\n-\tldr.w\tr0, [r3, #180]\t@ 0xb4\n-\tstr\tr0, [r7, #104]\t@ 0x68\n-\tldr.w\tr0, [r3, #192]\t@ 0xc0\n-\tstr\tr0, [r7, #100]\t@ 0x64\n-\tldr.w\tr0, [r3, #216]\t@ 0xd8\n-\tstr\tr0, [r7, #96]\t@ 0x60\n-\tldr.w\tr0, [r3, #220]\t@ 0xdc\n-\tstr\tr0, [r7, #92]\t@ 0x5c\n-\tldr.w\tr0, [r3, #240]\t@ 0xf0\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n-\tldr.w\tr0, [r3, #252]\t@ 0xfc\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tldr.w\tr0, [r3, #264]\t@ 0x108\n-\tstr\tr0, [r7, #80]\t@ 0x50\n-\tldr.w\tr0, [r3, #276]\t@ 0x114\n-\tstr\tr0, [r7, #112]\t@ 0x70\n-\tldr.w\tr0, [r3, #236]\t@ 0xec\n-\tstr\tr0, [r7, #120]\t@ 0x78\n-\tldr.w\tr0, [r3, #288]\t@ 0x120\n-\tstr\tr0, [r7, #116]\t@ 0x74\n-\tldr.w\tr0, [r3, #292]\t@ 0x124\n-\tstr\tr0, [r7, #124]\t@ 0x7c\n-\tldr.w\tr0, [r3, #312]\t@ 0x138\n+\tstr\tr0, [r7, #72]\t@ 0x48\n+\tmul.w\tfp, r2, r0\n+\tstr\tr5, [r7, #56]\t@ 0x38\n+\tldr.w\tr5, [r3, #144]\t@ 0x90\n+\tstr\tr5, [r7, #68]\t@ 0x44\n+\tldr.w\tr5, [r3, #148]\t@ 0x94\n+\tstr\tr5, [r7, #88]\t@ 0x58\n+\tldr.w\tr5, [r3, #168]\t@ 0xa8\n+\tstr\tr5, [r7, #108]\t@ 0x6c\n+\tldr.w\tr5, [r3, #180]\t@ 0xb4\n+\tstr\tr5, [r7, #104]\t@ 0x68\n+\tldr.w\tr5, [r3, #192]\t@ 0xc0\n+\tstr\tr5, [r7, #100]\t@ 0x64\n+\tldr.w\tr5, [r3, #216]\t@ 0xd8\n+\tstr\tr5, [r7, #96]\t@ 0x60\n+\tldr.w\tr5, [r3, #220]\t@ 0xdc\n+\tstr\tr5, [r7, #92]\t@ 0x5c\n+\tldr.w\tr5, [r3, #240]\t@ 0xf0\n+\tstr\tr5, [r7, #76]\t@ 0x4c\n+\tldr.w\tr5, [r3, #252]\t@ 0xfc\n+\tstr\tr5, [r7, #84]\t@ 0x54\n+\tldr.w\tr5, [r3, #264]\t@ 0x108\n+\tstr\tr5, [r7, #80]\t@ 0x50\n+\tldr.w\tr5, [r3, #276]\t@ 0x114\n+\tstr\tr5, [r7, #112]\t@ 0x70\n+\tldr.w\tr5, [r3, #236]\t@ 0xec\n+\tstr\tr5, [r7, #120]\t@ 0x78\n+\tldr.w\tr5, [r3, #288]\t@ 0x120\n+\tstr\tr5, [r7, #116]\t@ 0x74\n+\tldr.w\tr5, [r3, #292]\t@ 0x124\n+\tstr\tr5, [r7, #124]\t@ 0x7c\n+\tldr.w\tr5, [r3, #312]\t@ 0x138\n+\tstr.w\tr5, [r7, #132]\t@ 0x84\n+\tldr.w\tr5, [r3, #324]\t@ 0x144\n+\tstr.w\tr5, [r7, #144]\t@ 0x90\n \tldr.w\tr2, [r3, #336]\t@ 0x150\n-\tstr.w\tr0, [r7, #132]\t@ 0x84\n-\tldr.w\tr0, [r3, #324]\t@ 0x144\n-\tstr.w\tr0, [r7, #144]\t@ 0x90\n \tstr.w\tr2, [r7, #140]\t@ 0x8c\n \tldr.w\tr2, [r3, #348]\t@ 0x15c\n \tldr.w\tr3, [r3, #308]\t@ 0x134\n \tstr.w\tr2, [r7, #136]\t@ 0x88\n-\tmov\tr2, r5\n \tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tmov\tr3, r9\n-\tstr.w\tip, [r7, #148]\t@ 0x94\n-\tldr.w\tr1, [sl, #504]\t@ 0x1f8\n-\tmovs\tr0, #24\n-\tstr.w\tr1, [r7, #152]\t@ 0x98\n-\tldr.w\tr1, [r7, #148]\t@ 0x94\n-\tldr.w\tr4, [r7, #128]\t@ 0x80\n-\tldr\tr5, [r7, #112]\t@ 0x70\n-\tstrd\tr2, r8, [r7, #4]\n-\tmla\tr1, r0, r8, r1\n-\tldr.w\tr0, [r7, #136]\t@ 0x88\n-\tmul.w\tr4, r4, r0\n-\tldr\tr0, [r7, #120]\t@ 0x78\n-\tmul.w\tr5, r5, r0\n+\tstr.w\tr4, [r7, #148]\t@ 0x94\n+\tstr.w\tr4, [r7, #172]\t@ 0xac\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tmovs\tr2, #24\n+\tldr.w\tr0, [r7, #128]\t@ 0x80\n+\tstr.w\tr9, [r7, #4]\n+\tldr.w\tr3, [r3, #504]\t@ 0x1f8\n+\tstr.w\tr3, [r7, #176]\t@ 0xb0\n+\tldr.w\tr3, [r7, #172]\t@ 0xac\n+\tmla\tr2, r2, r9, r3\n+\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tmul.w\tr4, r0, r3\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tldr\tr3, [r7, #120]\t@ 0x78\n+\tmov\tr8, r4\n+\tmul.w\tr5, r0, r3\n \tmvn.w\tr0, #2\n-\tstrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tldr.w\tr2, [r7, #172]\t@ 0xac\n-\tstr.w\tr2, [r7, #184]\t@ 0xb8\n-\tldr.w\tr2, [r7, #168]\t@ 0xa8\n-\tstr.w\tr2, [r7, #188]\t@ 0xbc\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n-\tstr.w\tr2, [r7, #192]\t@ 0xc0\n-\tldr\tr2, [r6, #0]\n-\tadd.w\tip, r0, r2\n-\tldr.w\tr2, [r7, #152]\t@ 0x98\n-\tstr.w\tip, [r6]\n-\tcmp\tip, r2\n-\tldr.w\tr2, [r7, #184]\t@ 0xb8\n-\tblt.w\t4a0 \n-\tldr.w\tr4, [sl, #508]\t@ 0x1fc\n-\tldrd\tr9, r8, [r7, #188]\t@ 0xbc\n-\tcmp\tip, r4\n-\tble.n\t45e \n-\tldr\tr4, [r7, #124]\t@ 0x7c\n-\tcmp\tr3, #0\n-\tldr.w\tr5, [r7, #132]\t@ 0x84\n-\tmla\tr2, r2, r5, r4\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tstr.w\tr3, [r7, #184]\t@ 0xb8\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tstr.w\tr3, [r7, #188]\t@ 0xbc\n+\tldr.w\tr3, [r7, #160]\t@ 0xa0\n+\tstr.w\tr3, [r7, #192]\t@ 0xc0\n+\tldr.w\tr3, [ip]\n+\tadd.w\tlr, r0, r3\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n+\tstr.w\tlr, [ip]\n+\tcmp\tlr, r3\n+\tblt.w\t4d2 \n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tldr.w\tr4, [r7, #192]\t@ 0xc0\n+\tstr.w\tr4, [r7, #180]\t@ 0xb4\n+\tldr.w\tr3, [r3, #508]\t@ 0x1fc\n+\tmov\tr6, r3\n+\tcmp\tlr, r6\n+\tldrd\tr3, r9, [r7, #184]\t@ 0xb8\n+\tble.n\t492 \n+\tldr\tr6, [r7, #124]\t@ 0x7c\n+\tcmp\tr1, #0\n+\tldr.w\tr4, [r7, #132]\t@ 0x84\n+\tmla\tr3, r3, r4, r6\n \tldr.w\tr4, [r7, #144]\t@ 0x90\n-\tmla\tr2, r9, r4, r2\n+\tldr.w\tr6, [r7, #180]\t@ 0xb4\n+\tmla\tr3, r9, r4, r3\n \tldr.w\tr4, [r7, #140]\t@ 0x8c\n-\tmla\tr2, r8, r4, r2\n-\tble.n\t44e \n+\tmla\tr3, r6, r4, r3\n+\tble.n\t482 \n \tldr.w\tr4, [r7, #136]\t@ 0x88\n-\tmov\tr8, fp\n-\tldr.w\tr5, [r7, #128]\t@ 0x80\n-\tmov.w\tip, #0\n-\tadd\tr2, r4\n+\tmov\tlr, sl\n+\tldr.w\tr6, [r7, #128]\t@ 0x80\n+\tadd\tr3, r4\n \tldr\tr4, [r7, #116]\t@ 0x74\n-\tmla\tr2, r5, r2, r4\n-\tldrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tadd.w\tip, ip, #1\n-\tvldr\td16, [r2]\n-\tcmp\tr3, ip\n-\tadd\tr2, r4\n-\tvstmia\tr8!, {d16}\n-\tbne.n\t3de \n-\tldr.w\tr2, [r7, #160]\t@ 0xa0\n-\tadds\tr3, #1\n-\tvldr\td22, [r1, #-24]\t@ 0xffffffe8\n-\tmov\tr8, fp\n-\tvldr\td21, [r1, #-16]\n-\tmov.w\tip, #1\n-\tvldr\td20, [r1, #-8]\n-\tstrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tvldmia\tr8!, {d19}\n-\tadd.w\tip, ip, #1\n-\tvldr\td18, [r2]\n-\tcmp\tr3, ip\n-\tvldr\td17, [r2, #8]\n-\tadd.w\tr2, r2, #24\n-\tvldr\td16, [r2, #-8]\n-\tvfma.f64\td18, d19, d22\n-\tvfma.f64\td17, d19, d21\n-\tvfma.f64\td16, d20, d19\n-\tvstr\td18, [r2, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r2, #-16]\n-\tvstr\td16, [r2, #-8]\n-\tbne.n\t40c \n-\tldr.w\tr3, [r7, #148]\t@ 0x94\n-\tmovs\tr2, #4\n-\tstrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tstr.w\tr2, [r3, #548]\t@ 0x224\n+\tmla\tr3, r6, r3, r4\n+\tmovs\tr6, #0\n+\tmov\tr4, r8\n+\tldrd\tr8, r9, [r3]\n+\tadds\tr6, #1\n+\tadd\tr3, r4\n+\tcmp\tr1, r6\n+\tstrd\tr8, r9, [lr], #8\n+\tbne.n\t41e \n+\tldr.w\tr3, [r7, #156]\t@ 0x9c\n+\tadds\tr1, #1\n+\tvldr\td1, [r2, #-24]\t@ 0xffffffe8\n+\tmov\tlr, sl\n+\tvldr\td2, [r2, #-16]\n+\tmovs\tr6, #1\n+\tvldr\td3, [r2, #-8]\n+\tvldmia\tlr!, {d4}\n+\tadds\tr6, #1\n+\tvldr\td5, [r3]\n+\tcmp\tr1, r6\n+\tvldr\td6, [r3, #8]\n+\tadd.w\tr3, r3, #24\n+\tvldr\td7, [r3, #-8]\n+\tvmla.f64\td5, d4, d1\n+\tvmla.f64\td6, d4, d2\n+\tvmla.f64\td7, d3, d4\n+\tvstr\td5, [r3, #-24]\t@ 0xffffffe8\n+\tvstr\td6, [r3, #-16]\n+\tvstr\td7, [r3, #-8]\n+\tbne.n\t444 \n+\tldr.w\tr3, [r7, #172]\t@ 0xac\n+\tmov\tr8, r4\n+\tmovs\tr1, #4\n+\tstr.w\tr1, [r3, #548]\t@ 0x224\n \tadds\tr0, #1\n-\tadds\tr1, #72\t@ 0x48\n+\tadds\tr2, #72\t@ 0x48\n \tcmp\tr0, #4\n-\tbeq.n\t4ea \n-\tldr.w\tr3, [r7, #156]\t@ 0x9c\n-\tldr\tr3, [r3, #0]\n-\tb.n\t36a \n+\tbeq.n\t51a \n+\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tldr\tr1, [r3, #0]\n+\tb.n\t39e \n \tldr\tr4, [r7, #88]\t@ 0x58\n-\tcmp\tr3, #0\n-\tldr\tr5, [r7, #108]\t@ 0x6c\n-\tmla\tr2, r2, r5, r4\n+\tcmp\tr1, #0\n+\tldr\tr6, [r7, #108]\t@ 0x6c\n+\tmla\tr3, r3, r6, r4\n \tldr\tr4, [r7, #104]\t@ 0x68\n-\tmla\tr2, r9, r4, r2\n+\tldr.w\tr6, [r7, #180]\t@ 0xb4\n+\tmla\tr3, r9, r4, r3\n \tldr\tr4, [r7, #100]\t@ 0x64\n-\tmla\tr2, r8, r4, r2\n-\tble.n\t44e \n+\tmla\tr3, r6, r4, r3\n+\tble.n\t482 \n \tldr\tr4, [r7, #64]\t@ 0x40\n-\tmov\tr8, fp\n-\tmov.w\tip, #0\n-\tadd\tr2, r4\n-\tldrd\tr4, r5, [r7, #68]\t@ 0x44\n-\tmla\tr2, r5, r2, r4\n-\tldrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tadd.w\tip, ip, #1\n-\tvldr\td16, [r2]\n-\tcmp\tip, r3\n-\tadd\tr2, lr\n-\tvstmia\tr8!, {d16}\n-\tbne.n\t48c \n-\tb.n\t3f0 \n+\tmov\tlr, sl\n+\tadd\tr3, r4\n+\tldrd\tr4, r6, [r7, #68]\t@ 0x44\n+\tmla\tr3, r6, r3, r4\n+\tmovs\tr6, #0\n+\tmov\tr4, r8\n+\tldrd\tr8, r9, [r3]\n+\tadds\tr6, #1\n+\tadd\tr3, fp\n+\tcmp\tr6, r1\n+\tstrd\tr8, r9, [lr], #8\n+\tbne.n\t4c0 \n+\tb.n\t42e \n \tldr\tr4, [r7, #92]\t@ 0x5c\n-\tcmp\tr3, #0\n-\tldr\tr5, [r7, #76]\t@ 0x4c\n-\tmla\tr2, r2, r5, r4\n+\tcmp\tr1, #0\n+\tldr\tr6, [r7, #76]\t@ 0x4c\n+\tldr.w\tr3, [r7, #184]\t@ 0xb8\n+\tmla\tr3, r3, r6, r4\n \tldr\tr4, [r7, #84]\t@ 0x54\n-\tldr.w\tr5, [r7, #188]\t@ 0xbc\n-\tmla\tip, r5, r4, r2\n-\tldr.w\tr2, [r7, #192]\t@ 0xc0\n+\tldr.w\tr6, [r7, #188]\t@ 0xbc\n+\tmla\tr6, r6, r4, r3\n+\tldr.w\tr3, [r7, #192]\t@ 0xc0\n \tldr\tr4, [r7, #80]\t@ 0x50\n-\tmla\tr2, r2, r4, ip\n-\tble.n\t44e \n+\tmla\tr3, r3, r4, r6\n+\tble.n\t482 \n \tldr\tr4, [r7, #112]\t@ 0x70\n-\tmov\tr8, fp\n-\tldr\tr5, [r7, #120]\t@ 0x78\n-\tmov.w\tip, #0\n-\tadd\tr2, r4\n+\tmov\tlr, sl\n+\tldr\tr6, [r7, #120]\t@ 0x78\n+\tadd\tr3, r4\n \tldr\tr4, [r7, #96]\t@ 0x60\n-\tmla\tr2, r5, r2, r4\n-\tldrd\tr5, r4, [r7, #176]\t@ 0xb0\n-\tadd.w\tip, ip, #1\n-\tvldr\td16, [r2]\n-\tcmp\tip, r3\n-\tadd\tr2, r5\n-\tvstmia\tr8!, {d16}\n-\tbne.n\t4d6 \n-\tb.n\t3f0 \n-\tldrd\tr2, r8, [r7, #4]\n-\tadd.w\tsl, sl, #8\n-\tadds\tr6, #4\n-\tadd.w\tr8, r8, #1\n-\tcmp.w\tr8, #4\n-\tbeq.w\t23e \n-\tldr.w\tr3, [r7, #156]\t@ 0x9c\n-\tcmp.w\tr8, #2\n-\tldr\tr3, [r3, #0]\n-\tbeq.n\t552 \n-\tldr\tr1, [r7, #12]\n-\tmov.w\tr8, #3\n-\tstr.w\tr1, [r7, #136]\t@ 0x88\n-\tldr\tr1, [r7, #16]\n-\tstr.w\tr1, [r7, #140]\t@ 0x8c\n-\tldr\tr1, [r7, #20]\n-\tstr.w\tr1, [r7, #144]\t@ 0x90\n-\tldr\tr1, [r7, #24]\n-\tstr.w\tr1, [r7, #132]\t@ 0x84\n-\tldr\tr1, [r7, #56]\t@ 0x38\n-\tstr.w\tr1, [r7, #128]\t@ 0x80\n-\tldr\tr1, [r7, #28]\n-\tstr\tr1, [r7, #124]\t@ 0x7c\n-\tldr\tr1, [r7, #32]\n-\tstr\tr1, [r7, #116]\t@ 0x74\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tstr\tr1, [r7, #112]\t@ 0x70\n-\tldr\tr1, [r7, #40]\t@ 0x28\n-\tstr\tr1, [r7, #80]\t@ 0x50\n-\tldr\tr1, [r7, #44]\t@ 0x2c\n-\tstr\tr1, [r7, #84]\t@ 0x54\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tstr\tr1, [r7, #120]\t@ 0x78\n-\tldr\tr1, [r7, #48]\t@ 0x30\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n-\tldr\tr1, [r7, #52]\t@ 0x34\n+\tmla\tr3, r6, r3, r4\n+\tmovs\tr6, #0\n+\tmov\tr4, r8\n+\tldrd\tr8, r9, [r3]\n+\tadds\tr6, #1\n+\tadd\tr3, r5\n+\tcmp\tr6, r1\n+\tstrd\tr8, r9, [lr], #8\n+\tbne.n\t508 \n+\tb.n\t42e \n+\tldr.w\tr9, [r7, #4]\n+\tadd.w\tip, ip, #4\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tadd.w\tr9, r9, #1\n+\tadds\tr3, #8\n+\tcmp.w\tr9, #4\n+\tstr.w\tr3, [r7, #148]\t@ 0x94\n+\tbeq.w\t270 \n+\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tcmp.w\tr9, #2\n+\tldr\tr1, [r3, #0]\n+\tbeq.n\t58c \n+\tldr\tr3, [r7, #8]\n+\tmov.w\tr9, #3\n+\tstr.w\tr3, [r7, #136]\t@ 0x88\n+\tldr\tr3, [r7, #12]\n+\tstr.w\tr3, [r7, #140]\t@ 0x8c\n+\tldr\tr3, [r7, #16]\n+\tstr.w\tr3, [r7, #144]\t@ 0x90\n+\tldr\tr3, [r7, #20]\n+\tstr.w\tr3, [r7, #132]\t@ 0x84\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tstr.w\tr3, [r7, #128]\t@ 0x80\n+\tldr\tr3, [r7, #24]\n+\tstr\tr3, [r7, #124]\t@ 0x7c\n+\tldr\tr3, [r7, #28]\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tldr\tr3, [r7, #32]\n+\tstr\tr3, [r7, #112]\t@ 0x70\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tstr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r7, #96]\t@ 0x60\n+\tb.n\t36a \n+\tldr\tr3, [pc, #128]\t@ (610 )\n+\tadd\tr3, pc\n+\tldr.w\tr2, [r3, #360]\t@ 0x168\n+\tstr\tr2, [r7, #96]\t@ 0x60\n+\tldr.w\tr2, [r3, #364]\t@ 0x16c\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n+\tldr.w\tr2, [r3, #384]\t@ 0x180\n \tstr\tr2, [r7, #76]\t@ 0x4c\n-\tstr\tr1, [r7, #96]\t@ 0x60\n-\tb.n\t338 \n-\tldr\tr1, [pc, #132]\t@ (5d8 )\n-\tadd\tr1, pc\n-\tldr.w\tr0, [r1, #360]\t@ 0x168\n-\tstr\tr0, [r7, #96]\t@ 0x60\n-\tldr.w\tr0, [r1, #364]\t@ 0x16c\n-\tstr\tr0, [r7, #92]\t@ 0x5c\n-\tldr.w\tr0, [r1, #384]\t@ 0x180\n-\tstr\tr0, [r7, #76]\t@ 0x4c\n-\tldr.w\tr0, [r1, #396]\t@ 0x18c\n-\tstr\tr0, [r7, #84]\t@ 0x54\n-\tldr.w\tr0, [r1, #408]\t@ 0x198\n-\tstr\tr0, [r7, #80]\t@ 0x50\n-\tldr.w\tr0, [r1, #420]\t@ 0x1a4\n-\tstr\tr0, [r7, #112]\t@ 0x70\n-\tldr.w\tr0, [r1, #380]\t@ 0x17c\n-\tstr\tr0, [r7, #120]\t@ 0x78\n-\tldr.w\tr0, [r1, #432]\t@ 0x1b0\n-\tstr\tr0, [r7, #116]\t@ 0x74\n-\tldr.w\tr0, [r1, #436]\t@ 0x1b4\n-\tstr\tr0, [r7, #124]\t@ 0x7c\n-\tldr.w\tr0, [r1, #456]\t@ 0x1c8\n-\tstr.w\tr0, [r7, #132]\t@ 0x84\n-\tldr.w\tr0, [r1, #468]\t@ 0x1d4\n-\tstr.w\tr0, [r7, #144]\t@ 0x90\n-\tldr.w\tr0, [r1, #480]\t@ 0x1e0\n-\tstr.w\tr0, [r7, #140]\t@ 0x8c\n-\tldr.w\tr0, [r1, #492]\t@ 0x1ec\n-\tldr.w\tr1, [r1, #452]\t@ 0x1c4\n-\tstr.w\tr0, [r7, #136]\t@ 0x88\n-\tstr.w\tr1, [r7, #128]\t@ 0x80\n-\tb.n\t338 \n+\tldr.w\tr2, [r3, #396]\t@ 0x18c\n+\tstr\tr2, [r7, #84]\t@ 0x54\n+\tldr.w\tr2, [r3, #408]\t@ 0x198\n+\tstr\tr2, [r7, #80]\t@ 0x50\n+\tldr.w\tr2, [r3, #420]\t@ 0x1a4\n+\tstr\tr2, [r7, #112]\t@ 0x70\n+\tldr.w\tr2, [r3, #380]\t@ 0x17c\n+\tstr\tr2, [r7, #120]\t@ 0x78\n+\tldr.w\tr2, [r3, #432]\t@ 0x1b0\n+\tstr\tr2, [r7, #116]\t@ 0x74\n+\tldr.w\tr2, [r3, #436]\t@ 0x1b4\n+\tstr\tr2, [r7, #124]\t@ 0x7c\n+\tldr.w\tr2, [r3, #456]\t@ 0x1c8\n+\tstr.w\tr2, [r7, #132]\t@ 0x84\n+\tldr.w\tr2, [r3, #468]\t@ 0x1d4\n+\tstr.w\tr2, [r7, #144]\t@ 0x90\n+\tldr.w\tr2, [r3, #480]\t@ 0x1e0\n+\tstr.w\tr2, [r7, #140]\t@ 0x8c\n+\tldr.w\tr2, [r3, #492]\t@ 0x1ec\n+\tldr.w\tr3, [r3, #452]\t@ 0x1c4\n+\tstr.w\tr2, [r7, #136]\t@ 0x88\n+\tstr.w\tr3, [r7, #128]\t@ 0x80\n+\tb.n\t36a \n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tb.n\t74 \n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x0000059a\n+\t.word\t0x000005d2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000516\n+\t.word\t0x0000054c\n R_ARM_REL32\t.data\n-\t.word\t0x0000038a\n+\t.word\t0x00000390\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000366\n+\t.word\t0x0000036e\n R_ARM_REL32\t.bss\n-\t.word\t0x00000080\n+\t.word\t0x0000007e\n R_ARM_REL32\t.bss\n \n-000005dc <__gridxc_cell_MOD_cellxc>:\n+00000614 <__gridxc_cell_MOD_cellxc>:\n __gridxc_cell_MOD_cellxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #760]\t@ 0x2f8\n-\tsubw\tsp, sp, #3236\t@ 0xca4\n+\tstr.w\tr0, [ip, #784]\t@ 0x310\n+\tsubw\tsp, sp, #3212\t@ 0xc8c\n \tadd\tr7, sp, #48\t@ 0x30\n \tmov\tr6, r2\n-\taddw\tr4, r7, #2488\t@ 0x9b8\n-\tstr.w\tr1, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr1, [pc, #2228]\t@ eb8 <__gridxc_cell_MOD_cellxc+0x8dc>\n-\tstr.w\tr0, [r7, #404]\t@ 0x194\n-\tmov\tr0, r3\n-\tldr.w\tr3, [pc, #2224]\t@ ebc <__gridxc_cell_MOD_cellxc+0x8e0>\n+\tldr.w\tr2, [pc, #2700]\t@ 10c0 <__gridxc_cell_MOD_cellxc+0xaac>\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr1, [pc, #2696]\t@ 10c4 <__gridxc_cell_MOD_cellxc+0xab0>\n+\tstr.w\tr0, [r7, #396]\t@ 0x18c\n+\tadd.w\tr0, r7, #2464\t@ 0x9a0\n+\tadd\tr1, pc\n+\tldr.w\tr4, [r7, #3292]\t@ 0xcdc\n+\tldr.w\tip, [r7, #3264]\t@ 0xcc0\n+\tldr.w\tr5, [r7, #3268]\t@ 0xcc4\n+\tldr\tr2, [r1, r2]\n+\tldr.w\tr1, [r7, #3288]\t@ 0xcd8\n+\tldr\tr2, [r2, #0]\n+\tstr.w\tr2, [r7, #3156]\t@ 0xc54\n+\tmov.w\tr2, #0\n+\tstr.w\tr4, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr4, [r7, #3296]\t@ 0xce0\n+\tstr.w\tr4, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr4, [r7, #3300]\t@ 0xce4\n+\tstr.w\tr4, [r7, #216]\t@ 0xd8\n+\tldr.w\tr4, [r7, #3304]\t@ 0xce8\n+\tldr.w\tr2, [r7, #3316]\t@ 0xcf4\n+\tstr.w\tr1, [r7, #2992]\t@ 0xbb0\n+\tstr.w\tr4, [r7, #212]\t@ 0xd4\n+\tldr.w\tr1, [pc, #2624]\t@ 10c8 <__gridxc_cell_MOD_cellxc+0xab4>\n+\tldr.w\tr4, [r7, #3308]\t@ 0xcec\n+\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n \tadd\tr1, pc\n-\tldr.w\tr5, [r7, #3308]\t@ 0xcec\n-\tldr.w\tip, [r7, #3288]\t@ 0xcd8\n-\tldr.w\tr2, [r7, #3292]\t@ 0xcdc\n-\tldr\tr3, [r1, r3]\n-\tldr.w\tr1, [r7, #3340]\t@ 0xd0c\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #3180]\t@ 0xc6c\n-\tmov.w\tr3, #0\n-\tldr.w\tr3, [r7, #3312]\t@ 0xcf0\n-\tstr.w\tr4, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr4, [r7, #3316]\t@ 0xcf4\n-\tstr.w\tr3, [r7, #3016]\t@ 0xbc8\n-\tstr.w\tr4, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr3, [pc, #2172]\t@ ec0 <__gridxc_cell_MOD_cellxc+0x8e4>\n+\tldr.w\tr2, [r7, #3284]\t@ 0xcd4\n+\tstr.w\tr4, [r7, #456]\t@ 0x1c8\n+\tldr.w\tr4, [r7, #3312]\t@ 0xcf0\n+\tstr.w\tr0, [r7, #792]\t@ 0x318\n+\tstr.w\tr1, [r7, #640]\t@ 0x280\n+\tmovs\tr1, #0\n+\tldr.w\tlr, [r7, #3276]\t@ 0xccc\n+\tstr.w\tr1, [r7, #3024]\t@ 0xbd0\n+\tldr.w\tr0, [r7, #3280]\t@ 0xcd0\n+\tldr.w\tr1, [r7, #3272]\t@ 0xcc8\n+\tstr.w\tr6, [r7, #3016]\t@ 0xbc8\n+\tstr.w\tr2, [r7, #3020]\t@ 0xbcc\n+\tstr.w\tr4, [r7, #704]\t@ 0x2c0\n \tldr.w\tr4, [r7, #3320]\t@ 0xcf8\n-\tstr.w\tr4, [r7, #504]\t@ 0x1f8\n-\tadd\tr3, pc\n+\tstr.w\tr4, [r7, #652]\t@ 0x28c\n \tldr.w\tr4, [r7, #3324]\t@ 0xcfc\n-\tstr.w\tr3, [r7, #632]\t@ 0x278\n-\tmovs\tr3, #0\n-\tstr.w\tr4, [r7, #224]\t@ 0xe0\n-\tstr.w\tr3, [r7, #3048]\t@ 0xbe8\n-\tadd.w\tr3, r7, #3296\t@ 0xce0\n-\tldr.w\tr4, [r7, #3328]\t@ 0xd00\n-\tstr.w\tr4, [r7, #220]\t@ 0xdc\n-\tldr.w\tr4, [r7, #3332]\t@ 0xd04\n-\tstr.w\tr4, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr4, [r7, #3336]\t@ 0xd08\n-\tldmia.w\tr3, {r3, r8, lr}\n-\tstr.w\tr6, [r7, #3040]\t@ 0xbe0\n-\tstr.w\tr1, [r7, #728]\t@ 0x2d8\n-\tstr.w\tr5, [r7, #3044]\t@ 0xbe4\n-\tstr.w\tr4, [r7, #696]\t@ 0x2b8\n-\tldr.w\tr4, [r7, #3344]\t@ 0xd10\n-\tstr.w\tr4, [r7, #648]\t@ 0x288\n-\tldr.w\tr4, [r7, #3348]\t@ 0xd14\n-\tldr.w\tsl, [r7, #3352]\t@ 0xd18\n-\tstr.w\tr4, [r7, #588]\t@ 0x24c\n-\tcmp\tr1, #0\n-\tbeq.w\t9a6 <__gridxc_cell_MOD_cellxc+0x3ca>\n-\tldr.w\tr1, [ip]\n-\tldr\tr0, [r0, #0]\n-\tldr.w\tr4, [r8]\n-\tldr.w\tr9, [r3]\n+\tstr.w\tr4, [r7, #576]\t@ 0x240\n+\tldr.w\tr4, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr8, [r7, #3328]\t@ 0xd00\n+\tcmp\tr4, #0\n+\tbeq.w\t9ca <__gridxc_cell_MOD_cellxc+0x3b6>\n+\tldr.w\tr4, [ip]\n+\tldr\tr3, [r3, #0]\n+\tldr\tr1, [r1, #0]\n+\tstr.w\tr1, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [lr]\n \tldr\tr5, [r5, #0]\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tsubs\tr4, r1, r0\n \tldr\tr2, [r2, #0]\n-\tldr.w\tr3, [lr]\n-\tstr.w\tr5, [r7, #764]\t@ 0x2fc\n-\tadds\tr5, r4, #1\n-\tstr.w\tr4, [r7, #580]\t@ 0x244\n-\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr5, [r7, #752]\t@ 0x2f0\n-\tsub.w\tr5, r9, r2\n-\tsubs\tr4, r3, r4\n-\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tadds\tr3, r5, #1\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr4, [r7, #576]\t@ 0x240\n-\tldr.w\tr4, [r7, #576]\t@ 0x240\n-\tbic.w\tip, r3, r3, asr #31\n-\tstr.w\tip, [r7, #532]\t@ 0x214\n-\tadds\tr3, r4, #1\n-\tstr.w\tip, [r7, #704]\t@ 0x2c0\n-\tldr.w\tr4, [r7, #580]\t@ 0x244\n-\tmla\tip, r5, ip, ip\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tstr.w\tr4, [r7, #568]\t@ 0x238\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tldr.w\tr4, [r7, #576]\t@ 0x240\n-\tbic.w\tip, ip, ip, asr #31\n-\tstr.w\tr4, [r7, #592]\t@ 0x250\n-\tldr.w\tr4, [r7, #576]\t@ 0x240\n-\tmul.w\tr3, r3, r3\n-\tstr.w\tr5, [r7, #488]\t@ 0x1e8\n-\tstr.w\tr3, [r7, #572]\t@ 0x23c\n-\tstr.w\tr3, [r7, #440]\t@ 0x1b8\n-\tmla\tr3, r4, ip, ip\n-\tstr.w\tip, [r7, #448]\t@ 0x1c0\n-\tstr.w\tip, [r7, #700]\t@ 0x2bc\n-\tstr.w\tr5, [r7, #596]\t@ 0x254\n-\tbic.w\tr4, r3, r3, asr #31\n-\tstr.w\tr4, [r7, #620]\t@ 0x26c\n-\tnegs\tr3, r4\n-\tstr.w\tr4, [r7, #512]\t@ 0x200\n-\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tstrd\tr1, r2, [r7, #804]\t@ 0x324\n-\tstr.w\tr0, [r7, #800]\t@ 0x320\n-\tldr.w\tr4, [r7, #704]\t@ 0x2c0\n-\tldr.w\tr1, [r7, #700]\t@ 0x2bc\n-\tldr\tr0, [r7, #88]\t@ 0x58\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tstr.w\tr4, [r7, #784]\t@ 0x310\n-\tstr.w\tr9, [r7, #812]\t@ 0x32c\n-\tstr.w\tr1, [r7, #788]\t@ 0x314\n-\tstr.w\tr0, [r7, #792]\t@ 0x318\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n+\tsubs\tr1, r4, r3\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr\tr0, [r0, #0]\n \tstr.w\tr2, [r7, #796]\t@ 0x31c\n-\tvldr\td10, [r7, #800]\t@ 0x320\n-\tvldr\td11, [r7, #808]\t@ 0x328\n-\tvldr\td16, [r7, #784]\t@ 0x310\n-\tvldr\td17, [r7, #792]\t@ 0x318\n-\tcbz\tr3, 7ce <__gridxc_cell_MOD_cellxc+0x1f2>\n-\tmov\tr3, r2\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tadd.w\tr2, r2, r2, lsl #1\n-\tstrd\tr3, r4, [r7, #284]\t@ 0x11c\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tldr.w\tr5, [r7, #764]\t@ 0x2fc\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tsubs\tr3, r3, r5\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tstr.w\tr4, [r7, #688]\t@ 0x2b0\n+\tadds\tr4, r1, #1\n \tsubs\tr2, r0, r2\n-\tstr.w\tr5, [r7, #280]\t@ 0x118\n-\tstr.w\tr2, [r7, #144]\t@ 0x90\n-\tstr.w\tr1, [r7, #148]\t@ 0x94\n-\tstr.w\tr3, [r7, #152]\t@ 0x98\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n-\tldr.w\tr0, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tadds\tr0, r3, #1\n+\tstr.w\tr0, [r7, #656]\t@ 0x290\n+\tbic.w\tr0, r4, r4, asr #31\n+\tstr.w\tr1, [r7, #548]\t@ 0x224\n+\tstr.w\tr1, [r7, #564]\t@ 0x234\n+\tstr.w\tr4, [r7, #636]\t@ 0x27c\n+\tmla\tr1, r3, r0, r0\n+\tldr.w\tr4, [r7, #796]\t@ 0x31c\n+\tstr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tbic.w\tr1, r1, r1, asr #31\n+\tstr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tmul.w\tr4, r4, r4\n+\tadds\tr5, r2, #1\n+\tstr.w\tr2, [r7, #480]\t@ 0x1e0\n+\tmla\tr3, r2, r1, r1\n+\tstr.w\tr2, [r7, #580]\t@ 0x244\n+\tstr.w\tr0, [r7, #436]\t@ 0x1b4\n+\tstr.w\tr5, [r7, #644]\t@ 0x284\n+\tbic.w\tr3, r3, r3, asr #31\n+\tstr.w\tr4, [r7, #572]\t@ 0x23c\n+\tnegs\tr2, r3\n+\tstr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tstrd\tr4, r1, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tstr.w\tr2, [r7, #408]\t@ 0x198\n+\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr2, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tcbz\tr3, 7dc <__gridxc_cell_MOD_cellxc+0x1c8>\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tadd.w\tr2, r3, r3, lsl #1\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tstr.w\tr3, [r7, #144]\t@ 0x90\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tstr.w\tr3, [r7, #272]\t@ 0x110\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tstr.w\tr1, [r7, #268]\t@ 0x10c\n+\tstr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr1, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #564]\t@ 0x234\n+\tstr.w\tr2, [r7, #412]\t@ 0x19c\n+\tsubs\tr2, r1, r2\n+\tstr.w\tr3, [r7, #148]\t@ 0x94\n+\tstr.w\tr2, [r7, #140]\t@ 0x8c\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n \tcmp\tr3, #0\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tstr.w\tr2, [r3, #544]\t@ 0x220\n+\tldr.w\tr2, [r7, #220]\t@ 0xdc\n+\tstr.w\tr0, [r3, #532]\t@ 0x214\n \tit\teq\n \tmoveq\tr0, #0\n+\tstr.w\tr1, [r3, #536]\t@ 0x218\n+\tstr.w\tr2, [r3, #540]\t@ 0x21c\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tstr.w\tr0, [r7, #132]\t@ 0x84\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n \tit\teq\n \tmoveq\tr0, #0\n \tbic.w\tr2, r3, r3, asr #31\n-\taddw\tr3, r7, #3020\t@ 0xbcc\n-\tstr.w\tr0, [r7, #272]\t@ 0x110\n+\tite\tne\n+\tmovne\tr3, r1\n+\tmoveq\tr3, #0\n+\tstr.w\tr3, [r7, #128]\t@ 0x80\n \tmov.w\tr2, r2, lsl #3\n-\tldr.w\tr0, [r7, #704]\t@ 0x2c0\n-\tvst1.32\t{d16-d17}, [r3]\n+\tstr.w\tr0, [r7, #264]\t@ 0x108\n \tmov\tr3, r2\n-\tit\teq\n-\tmoveq\tr0, #0\n+\tldr.w\tr0, [r7, #564]\t@ 0x234\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n-\tstr.w\tr0, [r7, #136]\t@ 0x88\n-\tldr.w\tr0, [r7, #596]\t@ 0x254\n-\tbic.w\tr1, r1, #15\n \tit\teq\n \tmoveq\tr0, #0\n-\tstr.w\tr0, [r7, #276]\t@ 0x114\n-\tldr.w\tr0, [r7, #568]\t@ 0x238\n+\tbic.w\tr1, r1, #15\n+\tldr.w\tr4, [r7, #580]\t@ 0x244\n \tsub.w\tr1, sp, r1\n-\tit\teq\n-\tmoveq\tr0, #0\n-\tstr.w\tr0, [r7, #140]\t@ 0x8c\n+\tstr.w\tr0, [r7, #136]\t@ 0x88\n \tmov\tr0, sp\n+\tit\teq\n+\tmoveq\tr4, #0\n \tadds\tr2, #7\n \tcmp\tr0, r1\n-\tbeq.n\t848 <__gridxc_cell_MOD_cellxc+0x26c>\n+\tstr.w\tr4, [r7, #260]\t@ 0x104\n+\tbeq.n\t86c <__gridxc_cell_MOD_cellxc+0x258>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t83a <__gridxc_cell_MOD_cellxc+0x25e>\n+\tbne.n\t85e <__gridxc_cell_MOD_cellxc+0x24a>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\ta30 <__gridxc_cell_MOD_cellxc+0x454>\n+\tbne.w\ta58 <__gridxc_cell_MOD_cellxc+0x444>\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tadd\tr3, sp, #48\t@ 0x30\n \tsub.w\tr1, sp, r1\n-\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n \tcmp\tr0, r1\n \tbic.w\tr3, r2, #7\n-\tbeq.n\t880 <__gridxc_cell_MOD_cellxc+0x2a4>\n+\tbeq.n\t8a4 <__gridxc_cell_MOD_cellxc+0x290>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t872 <__gridxc_cell_MOD_cellxc+0x296>\n+\tbne.n\t896 <__gridxc_cell_MOD_cellxc+0x282>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\ta38 <__gridxc_cell_MOD_cellxc+0x45c>\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tbne.w\ta60 <__gridxc_cell_MOD_cellxc+0x44c>\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tadd\tr1, sp, #48\t@ 0x30\n-\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n \tmov\tr4, sp\n \tadd.w\tr3, r3, r3, lsl #1\n \tbic.w\tr3, r3, r3, asr #31\n \tlsls\tr3, r3, #3\n \tmov\tr1, r3\n \tadds\tr3, #7\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n \tcmp\tr4, r0\n-\tbeq.n\t8c6 <__gridxc_cell_MOD_cellxc+0x2ea>\n+\tbeq.n\t8ea <__gridxc_cell_MOD_cellxc+0x2d6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr4, sp\n \tcmp\tr4, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t8b8 <__gridxc_cell_MOD_cellxc+0x2dc>\n+\tbne.n\t8dc <__gridxc_cell_MOD_cellxc+0x2c8>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 8d6 <__gridxc_cell_MOD_cellxc+0x2fa>\n+\tcbz\tr1, 8fa <__gridxc_cell_MOD_cellxc+0x2e6>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr0, r2, #4080\t@ 0xff0\n \tmov\tr4, sp\n \tbic.w\tr0, r0, #15\n \tadd\tr1, sp, #48\t@ 0x30\n \tsub.w\tr0, sp, r0\n-\tstr.w\tr1, [r7, #748]\t@ 0x2ec\n+\tstr.w\tr1, [r7, #764]\t@ 0x2fc\n \tcmp\tr4, r0\n \tbic.w\tr1, r2, #7\n-\tbeq.n\t900 <__gridxc_cell_MOD_cellxc+0x324>\n+\tbeq.n\t924 <__gridxc_cell_MOD_cellxc+0x310>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr4, sp\n \tcmp\tr4, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t8f2 <__gridxc_cell_MOD_cellxc+0x316>\n+\tbne.n\t916 <__gridxc_cell_MOD_cellxc+0x302>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 910 <__gridxc_cell_MOD_cellxc+0x334>\n+\tcbz\tr1, 934 <__gridxc_cell_MOD_cellxc+0x320>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr0, r3, #4080\t@ 0xff0\n \tmov\tr4, sp\n \tbic.w\tr0, r0, #15\n \tadd\tr1, sp, #48\t@ 0x30\n \tsub.w\tr0, sp, r0\n-\tstr\tr1, [r7, #56]\t@ 0x38\n+\tstr\tr1, [r7, #60]\t@ 0x3c\n \tcmp\tr4, r0\n \tbic.w\tr1, r3, #7\n-\tbeq.n\t938 <__gridxc_cell_MOD_cellxc+0x35c>\n+\tbeq.n\t95c <__gridxc_cell_MOD_cellxc+0x348>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr4, sp\n \tcmp\tr4, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t92a <__gridxc_cell_MOD_cellxc+0x34e>\n+\tbne.n\t94e <__gridxc_cell_MOD_cellxc+0x33a>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 948 <__gridxc_cell_MOD_cellxc+0x36c>\n+\tcbz\tr1, 96c <__gridxc_cell_MOD_cellxc+0x358>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr0, r2, #4080\t@ 0xff0\n \tmov\tr4, sp\n \tbic.w\tr0, r0, #15\n \tadd\tr1, sp, #48\t@ 0x30\n \tsub.w\tr0, sp, r0\n-\tstr\tr1, [r7, #52]\t@ 0x34\n+\tstr\tr1, [r7, #56]\t@ 0x38\n \tcmp\tr4, r0\n \tbic.w\tr1, r2, #7\n-\tbeq.n\t970 <__gridxc_cell_MOD_cellxc+0x394>\n+\tbeq.n\t994 <__gridxc_cell_MOD_cellxc+0x380>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr4, sp\n \tcmp\tr4, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t962 <__gridxc_cell_MOD_cellxc+0x386>\n+\tbne.n\t986 <__gridxc_cell_MOD_cellxc+0x372>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 980 <__gridxc_cell_MOD_cellxc+0x3a4>\n+\tcbz\tr1, 9a4 <__gridxc_cell_MOD_cellxc+0x390>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr0, r3, #4080\t@ 0xff0\n \tadd\tr1, sp, #48\t@ 0x30\n \tbic.w\tr0, r0, #15\n-\tstr.w\tr1, [r7, #660]\t@ 0x294\n+\tstr.w\tr1, [r7, #668]\t@ 0x29c\n \tsub.w\tr0, sp, r0\n \tbic.w\tr1, r3, #7\n \tmov\tr4, sp\n \tcmp\tr4, r0\n-\tbeq.n\ta40 <__gridxc_cell_MOD_cellxc+0x464>\n+\tbeq.n\ta68 <__gridxc_cell_MOD_cellxc+0x454>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t996 <__gridxc_cell_MOD_cellxc+0x3ba>\n-\tldr.w\tr1, [ip]\n-\tldr.w\tr4, [lr]\n+\tb.n\t9ba <__gridxc_cell_MOD_cellxc+0x3a6>\n+\tldr\tr3, [r3, #0]\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [lr]\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr\tr3, [r2, #0]\n+\tldr.w\tr4, [ip]\n+\tstr.w\tr3, [r7, #796]\t@ 0x31c\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr\tr1, [r1, #0]\n+\tldr\tr5, [r5, #0]\n+\tstr.w\tr4, [r7, #688]\t@ 0x2b0\n+\tsubs\tr4, r4, r3\n \tldr\tr0, [r0, #0]\n-\tstr.w\tr4, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr4, [r8]\n-\tldr.w\tr9, [r3]\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tldr\tr3, [r5, #0]\n-\tsubs\tr5, r1, r0\n-\tldr\tr2, [r2, #0]\n-\tstr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tstr.w\tr5, [r7, #568]\t@ 0x238\n-\tadds\tr5, #1\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tsub.w\tr4, r9, r2\n-\tstr.w\tr5, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr5, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr4, [r7, #596]\t@ 0x254\n-\tsubs\tr5, r5, r3\n-\tadds\tr3, r4, #1\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr5, [r7, #592]\t@ 0x250\n-\tbic.w\tr3, r3, r3, asr #31\n-\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n-\tadds\tr3, r5, #1\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tmul.w\tip, r3, r3\n-\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n-\tstr.w\tip, [r7, #440]\t@ 0x1b8\n-\tmla\tr3, r4, r3, r3\n+\tsubs\tr3, r1, r5\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tstr.w\tr4, [r7, #564]\t@ 0x234\n+\tadds\tr4, #1\n+\tsubs\tr2, r0, r2\n+\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tadds\tr0, r3, #1\n+\tstr.w\tr0, [r7, #656]\t@ 0x290\n+\tbic.w\tr0, r4, r4, asr #31\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tr1, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tmla\tr3, r3, r0, r0\n+\tstr.w\tr4, [r7, #636]\t@ 0x27c\n+\tstr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tadds\tr4, r2, #1\n+\tstr.w\tr2, [r7, #580]\t@ 0x244\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n-\tmla\tr3, r5, r3, r3\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tmul.w\tr1, r1, r1\n+\tstr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tstr.w\tr4, [r7, #644]\t@ 0x284\n+\tmla\tr3, r2, r3, r3\n+\tstr.w\tr1, [r7, #428]\t@ 0x1ac\n \tbic.w\tr3, r3, r3, asr #31\n-\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tstr.w\tr3, [r7, #544]\t@ 0x220\n \tnegs\tr3, r3\n-\tstr\tr3, [r7, #88]\t@ 0x58\n-\tb.n\t756 <__gridxc_cell_MOD_cellxc+0x17a>\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tb.n\t78c <__gridxc_cell_MOD_cellxc+0x178>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t856 <__gridxc_cell_MOD_cellxc+0x27a>\n+\tb.n\t87a <__gridxc_cell_MOD_cellxc+0x266>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t88e <__gridxc_cell_MOD_cellxc+0x2b2>\n+\tb.n\t8b2 <__gridxc_cell_MOD_cellxc+0x29e>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, a50 <__gridxc_cell_MOD_cellxc+0x474>\n+\tcbz\tr1, a78 <__gridxc_cell_MOD_cellxc+0x464>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tadd\tr0, sp, #48\t@ 0x30\n \tsub.w\tr1, sp, r1\n-\tstr.w\tr0, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr0, [r7, #756]\t@ 0x2f4\n \tmov\tr0, sp\n \tcmp\tr0, r1\n-\tbeq.n\ta76 <__gridxc_cell_MOD_cellxc+0x49a>\n+\tbeq.n\ta9e <__gridxc_cell_MOD_cellxc+0x48a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\ta66 <__gridxc_cell_MOD_cellxc+0x48a>\n+\tb.n\ta8e <__gridxc_cell_MOD_cellxc+0x47a>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, a86 <__gridxc_cell_MOD_cellxc+0x4aa>\n+\tcbz\tr2, aae <__gridxc_cell_MOD_cellxc+0x49a>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n+\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n \tadd\tr1, sp, #48\t@ 0x30\n-\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tstr.w\tr1, [r7, #720]\t@ 0x2d0\n \tlsls\tr2, r2, #3\n \tmov\tr1, r2\n \tadds\tr2, #7\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n \tmov\tr4, sp\n \tcmp\tr4, r0\n-\tbeq.n\tab2 <__gridxc_cell_MOD_cellxc+0x4d6>\n+\tbeq.n\tada <__gridxc_cell_MOD_cellxc+0x4c6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\taa2 <__gridxc_cell_MOD_cellxc+0x4c6>\n+\tb.n\taca <__gridxc_cell_MOD_cellxc+0x4b6>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, ac2 <__gridxc_cell_MOD_cellxc+0x4e6>\n+\tcbz\tr1, aea <__gridxc_cell_MOD_cellxc+0x4d6>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tadd\tr0, sp, #48\t@ 0x30\n \tsub.w\tr1, sp, r1\n-\tstr.w\tr0, [r7, #264]\t@ 0x108\n+\tstr.w\tr0, [r7, #256]\t@ 0x100\n \tmov\tr0, sp\n \tcmp\tr0, r1\n-\tbeq.n\tae8 <__gridxc_cell_MOD_cellxc+0x50c>\n+\tbeq.n\tb10 <__gridxc_cell_MOD_cellxc+0x4fc>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\tad8 <__gridxc_cell_MOD_cellxc+0x4fc>\n+\tb.n\tb00 <__gridxc_cell_MOD_cellxc+0x4ec>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, af8 <__gridxc_cell_MOD_cellxc+0x51c>\n+\tcbz\tr2, b20 <__gridxc_cell_MOD_cellxc+0x50c>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr2, r2, #15\n \tadd\tr1, sp, #48\t@ 0x30\n \tsub.w\tr2, sp, r2\n-\tstr.w\tr1, [r7, #260]\t@ 0x104\n+\tstr.w\tr1, [r7, #252]\t@ 0xfc\n \tmov\tr1, sp\n \tcmp\tr1, r2\n-\tbeq.n\tb1e <__gridxc_cell_MOD_cellxc+0x542>\n+\tbeq.n\tb46 <__gridxc_cell_MOD_cellxc+0x532>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\tb0e <__gridxc_cell_MOD_cellxc+0x532>\n+\tb.n\tb36 <__gridxc_cell_MOD_cellxc+0x522>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, b2e <__gridxc_cell_MOD_cellxc+0x552>\n+\tcbz\tr3, b56 <__gridxc_cell_MOD_cellxc+0x542>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr\tr3, [pc, #916]\t@ (ec4 <__gridxc_cell_MOD_cellxc+0x8e8>)\n+\tldr.w\tr3, [pc, #1396]\t@ 10cc <__gridxc_cell_MOD_cellxc+0xab8>\n \tmovs\tr1, #7\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr\tr0, [pc, #912]\t@ (ec8 <__gridxc_cell_MOD_cellxc+0x8ec>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr.w\tr0, [pc, #1388]\t@ 10d0 <__gridxc_cell_MOD_cellxc+0xabc>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tadd\tr2, sp, #48\t@ 0x30\n-\tstr.w\tr2, [r7, #528]\t@ 0x210\n+\tstr.w\tr2, [r7, #512]\t@ 0x200\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp.w\tsl, #0\n-\tbeq.w\t11ec <__gridxc_cell_MOD_cellxc+0xc10>\n-\tldr.w\tr3, [sl]\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\taddw\tr3, r7, #1380\t@ 0x564\n-\tvldr\td20, [pc, #816]\t@ e90 <__gridxc_cell_MOD_cellxc+0x8b4>\n-\tvldr\td21, [pc, #820]\t@ e98 <__gridxc_cell_MOD_cellxc+0x8bc>\n-\tadd.w\tr2, r7, #1368\t@ 0x558\n-\tvldr\td18, [pc, #820]\t@ ea0 <__gridxc_cell_MOD_cellxc+0x8c4>\n-\tvldr\td19, [pc, #824]\t@ ea8 <__gridxc_cell_MOD_cellxc+0x8cc>\n-\tvstr\td16, [r3]\n-\taddw\tr3, r7, #1388\t@ 0x56c\n-\tmov\tr1, r2\n-\tadd.w\tr0, r7, #1440\t@ 0x5a0\n-\tmov.w\tip, #20\n-\tadd.w\tr4, r7, #1512\t@ 0x5e8\n-\tadd.w\tr5, r7, #2144\t@ 0x860\n-\tvst1.32\t{d20-d21}, [r3]\n-\taddw\tr3, r7, #1452\t@ 0x5ac\n-\tstr.w\tip, [r2, #8]\n-\tvstr\td16, [r3]\n-\taddw\tr3, r7, #1460\t@ 0x5b4\n-\tstr.w\tr2, [r7, #544]\t@ 0x220\n-\tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tstr.w\tr0, [r7, #604]\t@ 0x25c\n-\tvst1.32\t{d20-d21}, [r3]\n-\taddw\tr3, r7, #1524\t@ 0x5f4\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n-\tvstr\td16, [r3]\n-\taddw\tr3, r7, #1532\t@ 0x5fc\n-\tstr.w\tr3, [r7, #640]\t@ 0x280\n-\tstr.w\tip, [r7, #1448]\t@ 0x5a8\n-\tvst1.32\t{d18-d19}, [r3]\n-\taddw\tr3, r7, #2156\t@ 0x86c\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tvstr\td16, [r3]\n-\taddw\tr3, r7, #2164\t@ 0x874\n-\tstr\tr2, [r1, #4]\n-\tstr.w\tr4, [r7, #556]\t@ 0x22c\n-\tvst1.32\t{d18-d19}, [r3]\n-\tstr.w\tr5, [r7, #720]\t@ 0x2d0\n-\tstr.w\tr3, [r7, #548]\t@ 0x224\n-\tadd.w\tr3, r7, #900\t@ 0x384\n-\tstr.w\tr2, [r7, #1444]\t@ 0x5a4\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tadd.w\tr3, r7, #1744\t@ 0x6d0\n-\tstr.w\tr2, [r7, #1516]\t@ 0x5ec\n-\tstr.w\tr2, [r7, #2148]\t@ 0x864\n-\tmovs\tr2, #8\n-\tstr\tr3, [r7, #76]\t@ 0x4c\n-\tstr.w\tr2, [r7, #1520]\t@ 0x5f0\n-\tstr.w\tr2, [r7, #2152]\t@ 0x868\n-\tmovw\tr2, #1537\t@ 0x601\n-\tstrh\tr2, [r1, #16]\n-\tstrh.w\tr2, [r7, #1456]\t@ 0x5b0\n-\tmovw\tr2, #769\t@ 0x301\n-\tstrh.w\tr2, [r7, #1528]\t@ 0x5f8\n-\tstrh.w\tr2, [r7, #2160]\t@ 0x870\n-\tadd.w\tr2, r7, #1944\t@ 0x798\n-\tstr\tr2, [r1, #0]\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tmov\tr2, r0\n-\tstr\tr3, [r0, #0]\n-\tadd.w\tr0, r7, #1664\t@ 0x680\n-\tadd.w\tr3, r7, #1584\t@ 0x630\n-\tstr\tr0, [r7, #32]\n-\tstr.w\tr0, [r7, #1512]\t@ 0x5e8\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\tstr.w\tr3, [r7, #2144]\t@ 0x860\n-\tmov\tr3, r4\n-\tstrd\tip, ip, [sp, #4]\n+\tcmp.w\tr8, #0\n+\tbeq.w\t1282 <__gridxc_cell_MOD_cellxc+0xc6e>\n+\tldr.w\tr3, [r8]\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\taddw\tr4, r7, #2132\t@ 0x854\n+\tstr.w\tr4, [r7, #648]\t@ 0x288\n+\tadd.w\tr0, r7, #1488\t@ 0x5d0\n+\taddw\tr5, r7, #1500\t@ 0x5dc\n+\tstr.w\tr5, [r7, #592]\t@ 0x250\n+\tadd.w\tr2, r7, #1344\t@ 0x540\n+\tldr.w\tr5, [r7, #648]\t@ 0x288\n+\tadd.w\tr1, r7, #1416\t@ 0x588\n+\tstr.w\tr0, [r7, #632]\t@ 0x278\n+\taddw\tr3, r7, #2120\t@ 0x848\n+\tadd.w\tr4, r7, #884\t@ 0x374\n+\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr4, [r7, #388]\t@ 0x184\n+\tmov\tr3, r1\n \tmovs\tr4, #0\n-\tstr\tr5, [sp, #0]\n-\tldr.w\tr9, [r7, #396]\t@ 0x18c\n+\tstr.w\tr4, [r7, #1504]\t@ 0x5e0\n+\tstr.w\tr4, [r7, #1500]\t@ 0x5dc\n+\tmov.w\tr9, #20\n+\tstr\tr4, [r5, #0]\n+\tmovs\tr5, #1\n+\tstr\tr5, [r0, #28]\n+\tmovs\tr1, #10\n+\tstr\tr5, [r0, #24]\n+\tmov\tr0, r2\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstr.w\tr9, [r7, #1436]\t@ 0x59c\n+\tmov.w\tr8, #8\n+\tstr.w\tr9, [r7, #1424]\t@ 0x590\n+\tmovw\tip, #1537\t@ 0x601\n+\tstr.w\tr4, [r7, #1432]\t@ 0x598\n+\tadd.w\tlr, r7, #1920\t@ 0x780\n+\tstr.w\tr4, [r7, #1428]\t@ 0x594\n+\tstr.w\tr5, [r7, #1444]\t@ 0x5a4\n+\tstr.w\tr5, [r7, #1440]\t@ 0x5a0\n+\tstr.w\tr9, [r7, #1364]\t@ 0x554\n+\tstr\tr1, [r3, #32]\n+\tstr.w\tr9, [r7, #1352]\t@ 0x548\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tstr.w\tr1, [r7, #1376]\t@ 0x560\n+\tstr.w\tr4, [r7, #1360]\t@ 0x550\n+\tstr.w\tr4, [r7, #1356]\t@ 0x54c\n+\tstr.w\tr5, [r7, #1372]\t@ 0x55c\n+\tstr.w\tr5, [r7, #1368]\t@ 0x558\n+\tstr.w\tr0, [r7, #624]\t@ 0x270\n+\tstr\tr2, [r0, #4]\n+\tldr.w\tr0, [r7, #728]\t@ 0x2d8\n+\tstr\tr1, [r3, #32]\n+\tstr\tr2, [r0, #4]\n+\tstr\tr2, [r3, #4]\n+\tldr.w\tr0, [r7, #624]\t@ 0x270\n+\tstr.w\tr8, [r3, #20]\n+\tstr.w\tr8, [r3, #8]\n+\tstrh.w\tip, [r0, #16]\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr0, [r7, #728]\t@ 0x2d8\n+\tstr.w\tlr, [r7, #72]\t@ 0x48\n+\tstr.w\tr8, [r3, #20]\n+\tstrh.w\tip, [r0, #16]\n+\tmovw\tip, #769\t@ 0x301\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr0, [r7, #624]\t@ 0x270\n+\tstrh.w\tip, [r3, #16]\n+\tstr.w\tlr, [r0]\n+\tadd.w\tlr, r7, #1720\t@ 0x6b8\n+\tldr.w\tr0, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tstr.w\tlr, [r7, #76]\t@ 0x4c\n+\tstr.w\tlr, [r0]\n+\tadd.w\tr0, r7, #1640\t@ 0x668\n+\tstr\tr0, [r3, #0]\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tstr\tr0, [r7, #28]\n+\tstr\tr4, [r3, #4]\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tstrh.w\tip, [r3, #16]\n+\tstr.w\tr8, [r3, #8]\n+\tstr\tr1, [r3, #32]\n+\tadd.w\tr1, r7, #1560\t@ 0x618\n+\tstr\tr2, [r3, #4]\n+\tstr\tr1, [r3, #0]\n+\tstrd\tr5, r5, [r3, #24]\n+\tstr\tr1, [r7, #80]\t@ 0x50\n+\tstrd\tr9, r9, [sp, #4]\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr9, [r7, #388]\t@ 0x184\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n \tmov\tr0, r9\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n \tbl\t0 <__gridxc_xcmod_MOD_getxc>\n R_ARM_THM_CALL\t__gridxc_xcmod_MOD_getxc\n-\tldr\tr3, [pc, #620]\t@ (ecc <__gridxc_cell_MOD_cellxc+0x8f0>)\n-\taddw\tr1, r7, #1204\t@ 0x4b4\n-\tmov\tr2, r4\n-\tmov\tr0, r1\n+\tldr.w\tr3, [pc, #1040]\t@ 10d4 <__gridxc_cell_MOD_cellxc+0xac0>\n+\taddw\tr2, r7, #1180\t@ 0x49c\n+\tmov\tr1, r4\n+\tmov\tr0, r2\n \tadd\tr3, pc\n \tstrd\tr4, r4, [sp, #8]\n \tstrd\tr3, r3, [sp]\n \tmov\tr3, r4\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tmov\tr1, r4\n+\tstr\tr2, [r7, #32]\n+\tmov\tr2, r4\n \tbl\t0 <__gridxc_alloc_MOD_alloc_default>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_alloc_default\n-\tldr\tr5, [r6, #0]\n+\tldr\tr2, [r6, #0]\n+\tstr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tadd.w\tr3, r7, #872\t@ 0x368\n \tldr\tr2, [r6, #4]\n-\tadd.w\tr3, r7, #888\t@ 0x378\n-\tldr\tr1, [r6, #8]\n-\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n-\tmul.w\tr3, r2, r5\n-\tcmp\tr1, #2\n-\tstr.w\tr5, [r7, #664]\t@ 0x298\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tmov\tr1, r2\n+\tldr\tr2, [r6, #8]\n+\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n+\tstr.w\tr3, [r7, #392]\t@ 0x188\n+\tcmp\tr2, #2\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n \tit\tge\n-\tmovge\tr1, #2\n-\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n-\tstr.w\tr1, [r7, #888]\t@ 0x378\n-\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tstr.w\tr2, [r7, #656]\t@ 0x290\n-\tmul.w\tr5, r1, r3\n+\tmovge\tr2, #2\n+\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr2, [r7, #872]\t@ 0x368\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tmul.w\tr3, r1, r2\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tmul.w\tr8, r2, r3\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n-\tvmov\ts15, r5\n-\tldr.w\tr1, [r9]\n-\tvmov.f64\td13, d0\n-\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n-\tvcvt.f64.s32\td16, s15\n-\tcmp\tr1, r4\n-\tvdiv.f64\td15, d0, d16\n-\tble.w\t12d4 <__gridxc_cell_MOD_cellxc+0xcf8>\n-\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n-\tcmp\tr1, #0\n-\tbeq.w\t106a <__gridxc_cell_MOD_cellxc+0xa8e>\n-\tldr\tr3, [pc, #492]\t@ (ed0 <__gridxc_cell_MOD_cellxc+0x8f4>)\n+\tvmov\ts15, r8\n+\tldr.w\tr2, [r9]\n+\tvmov.f64\td15, d0\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tvcvt.f64.s32\td7, s15\n+\tcmp\tr2, r4\n+\tvdiv.f64\td11, d0, d7\n+\tble.w\t1326 <__gridxc_cell_MOD_cellxc+0xd12>\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tcmp\tr2, #0\n+\tbeq.w\t1086 <__gridxc_cell_MOD_cellxc+0xa72>\n+\tldr\tr3, [pc, #900]\t@ (10d8 <__gridxc_cell_MOD_cellxc+0xac4>)\n \tmov\tr2, r4\n-\tstr.w\tr4, [r7, #540]\t@ 0x21c\n-\tvmov.i64\td9, #0x0000000000000000\n+\tstr.w\tr4, [r7, #520]\t@ 0x208\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #652]\t@ 0x28c\n-\tldr\tr3, [pc, #476]\t@ (ed4 <__gridxc_cell_MOD_cellxc+0x8f8>)\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr\tr3, [pc, #892]\t@ (10dc <__gridxc_cell_MOD_cellxc+0xac8>)\n+\tstr.w\tr5, [r7, #692]\t@ 0x2b4\n \tmov\tr5, r2\n+\tadd\tr3, pc\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr\tr3, [pc, #880]\t@ (10e0 <__gridxc_cell_MOD_cellxc+0xacc>)\n \tldrd\tr4, r8, [r7, #72]\t@ 0x48\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #636]\t@ 0x27c\n-\tldr\tr3, [r7, #80]\t@ 0x50\n-\tvldr\td8, [pc, #424]\t@ eb0 <__gridxc_cell_MOD_cellxc+0x8d4>\n-\tmov\tfp, r3\n-\tstr.w\tr2, [r7, #692]\t@ 0x2b4\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tb.n\tdc8 <__gridxc_cell_MOD_cellxc+0x7ec>\n-\tldr\tr3, [pc, #448]\t@ (ed8 <__gridxc_cell_MOD_cellxc+0x8fc>)\n+\tldr.w\tr9, [r7, #80]\t@ 0x50\n+\tvldr\td13, [pc, #828]\t@ 10b8 <__gridxc_cell_MOD_cellxc+0xaa4>\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tb.n\te36 <__gridxc_cell_MOD_cellxc+0x822>\n+\tldr\tr3, [pc, #860]\t@ (10e4 <__gridxc_cell_MOD_cellxc+0xad0>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\tdda <__gridxc_cell_MOD_cellxc+0x7fe>\n-\tldr\tr3, [pc, #432]\t@ (edc <__gridxc_cell_MOD_cellxc+0x900>)\n+\tbeq.n\te48 <__gridxc_cell_MOD_cellxc+0x834>\n+\tldr\tr3, [pc, #844]\t@ (10e8 <__gridxc_cell_MOD_cellxc+0xad4>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\tdda <__gridxc_cell_MOD_cellxc+0x7fe>\n-\tldr\tr3, [pc, #420]\t@ (ee0 <__gridxc_cell_MOD_cellxc+0x904>)\n+\tbeq.n\te48 <__gridxc_cell_MOD_cellxc+0x834>\n+\tldr\tr3, [pc, #832]\t@ (10ec <__gridxc_cell_MOD_cellxc+0xad8>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\tdda <__gridxc_cell_MOD_cellxc+0x7fe>\n-\tldr\tr3, [pc, #404]\t@ (ee4 <__gridxc_cell_MOD_cellxc+0x908>)\n+\tbeq.n\te48 <__gridxc_cell_MOD_cellxc+0x834>\n+\tldr\tr3, [pc, #816]\t@ (10f0 <__gridxc_cell_MOD_cellxc+0xadc>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\te70 <__gridxc_cell_MOD_cellxc+0x894>\n-\tldr\tr3, [pc, #388]\t@ (ee8 <__gridxc_cell_MOD_cellxc+0x90c>)\n+\tbeq.w\tef0 <__gridxc_cell_MOD_cellxc+0x8dc>\n+\tldr\tr3, [pc, #800]\t@ (10f4 <__gridxc_cell_MOD_cellxc+0xae0>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\te70 <__gridxc_cell_MOD_cellxc+0x894>\n-\tldr\tr3, [pc, #376]\t@ (eec <__gridxc_cell_MOD_cellxc+0x910>)\n+\tbeq.w\tef0 <__gridxc_cell_MOD_cellxc+0x8dc>\n+\tldr\tr3, [pc, #784]\t@ (10f8 <__gridxc_cell_MOD_cellxc+0xae4>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, d96 <__gridxc_cell_MOD_cellxc+0x7ba>\n-\tldr\tr3, [pc, #364]\t@ (ef0 <__gridxc_cell_MOD_cellxc+0x914>)\n+\tcbz\tr0, e08 <__gridxc_cell_MOD_cellxc+0x7f4>\n+\tldr\tr3, [pc, #772]\t@ (10fc <__gridxc_cell_MOD_cellxc+0xae8>)\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t11f2 <__gridxc_cell_MOD_cellxc+0xc16>\n-\tvldr\td16, [fp]\n+\tbne.w\t1288 <__gridxc_cell_MOD_cellxc+0xc74>\n+\tvldr\td7, [r9]\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #540]\t@ 0x21c\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tvadd.f64\td9, d9, d16\n-\tmov\tr2, fp\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tadds\tr2, #8\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n+\tvadd.f64\td13, d13, d7\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tadds\tr4, #20\n-\tmov\tfp, r2\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tadds\tr3, #1\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n \tadd.w\tr8, r8, #20\n+\tadds\tr3, #1\n+\tadd.w\tr9, r9, #8\n \tcmp\tr2, r3\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tblt.w\tf04 <__gridxc_cell_MOD_cellxc+0x928>\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tblt.n\tf0c <__gridxc_cell_MOD_cellxc+0x8f8>\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.n\td16 <__gridxc_cell_MOD_cellxc+0x73a>\n-\tldr.w\tr3, [r7, #636]\t@ 0x27c\n+\tbne.n\td86 <__gridxc_cell_MOD_cellxc+0x772>\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tmovs\tr2, #4\n \tmov\tr1, r8\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.n\te78 <__gridxc_cell_MOD_cellxc+0x89c>\n-\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n-\taddw\tr9, r7, #3100\t@ 0xc1c\n-\tldr\tr3, [pc, #252]\t@ (ef4 <__gridxc_cell_MOD_cellxc+0x918>)\n+\tbne.n\tef8 <__gridxc_cell_MOD_cellxc+0x8e4>\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmov.w\tlr, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n \tmovs\tr5, #80\t@ 0x50\n-\tmov\tr0, r2\n-\tstr.w\tr9, [r2, #68]\t@ 0x44\n-\tadd\tr3, pc\n-\tstr\tr5, [r2, #72]\t@ 0x48\n-\tstr\tr3, [r2, #8]\n+\tmov\tr0, r3\n+\tstr\tr2, [r3, #8]\n+\tmov\tr2, r3\n \tmov.w\tr3, #372\t@ 0x174\n-\tvstr\td8, [r2]\n+\tstr\tr5, [r2, #72]\t@ 0x48\n \tstr\tr3, [r2, #12]\n-\tmovs\tr3, #0\n-\tstr\tr3, [r2, #48]\t@ 0x30\n+\taddw\tr3, r7, #3076\t@ 0xc04\n+\tstr\tr3, [r2, #68]\t@ 0x44\n+\tmovs\tr2, #0\n+\tstr\tr2, [r0, #48]\t@ 0x30\n+\tmov.w\tr2, #16512\t@ 0x4080\n+\tstrd\tr2, lr, [r0]\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr.w\tsl, [r7, #720]\t@ 0x2d0\n-\tldr\tr1, [pc, #220]\t@ (ef8 <__gridxc_cell_MOD_cellxc+0x91c>)\n+\tldr.w\tsl, [r7, #760]\t@ 0x2f8\n \tmovs\tr2, #54\t@ 0x36\n+\tldr\tr1, [pc, #616]\t@ (1100 <__gridxc_cell_MOD_cellxc+0xaec>)\n \tmov\tr0, sl\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmovs\tr2, #20\n \tmov\tr1, r8\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, r9\n \tmov\tr2, r5\n-\tadd.w\tr1, r7, #976\t@ 0x3d0\n-\tadd.w\tr0, r7, #984\t@ 0x3d8\n+\tadd.w\tr1, r7, #960\t@ 0x3c0\n+\tadd.w\tr0, r7, #968\t@ 0x3c8\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n \tmov\tr5, r1\n-\tmov\tr9, r0\n+\tmov\tsl, r0\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #176]\t@ (efc <__gridxc_cell_MOD_cellxc+0x920>)\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr.w\tr9, [r9]\n+\tldr\tr3, [pc, #572]\t@ (1104 <__gridxc_cell_MOD_cellxc+0xaf0>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n \tldr\tr5, [r5, #0]\n+\tldr.w\tr1, [sl]\n \tldr\tr3, [r2, r3]\n-\tmov\tr1, r9\n \tmov\tr0, r5\n+\tstr.w\tr1, [r7, #552]\t@ 0x228\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp.w\tr9, #0\n-\tble.n\te6c <__gridxc_cell_MOD_cellxc+0x890>\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tcmp\tr1, #0\n+\tble.n\teec <__gridxc_cell_MOD_cellxc+0x8d8>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr5, #1\n-\tb.n\tda8 <__gridxc_cell_MOD_cellxc+0x7cc>\n+\tb.n\te1a <__gridxc_cell_MOD_cellxc+0x806>\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tb.n\tda8 <__gridxc_cell_MOD_cellxc+0x7cc>\n-\tldr\tr3, [pc, #132]\t@ (f00 <__gridxc_cell_MOD_cellxc+0x924>)\n+\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n+\tb.n\te1a <__gridxc_cell_MOD_cellxc+0x806>\n+\tldr\tr3, [pc, #524]\t@ (1108 <__gridxc_cell_MOD_cellxc+0xaf4>)\n \tmovs\tr2, #4\n \tmov\tr1, r8\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.n\te6c <__gridxc_cell_MOD_cellxc+0x890>\n-\tb.n\tdec <__gridxc_cell_MOD_cellxc+0x810>\n-\tnop.w\n-\t.word\t0x00000014\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000000a\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000000a\n-\t.word\t0x00004080\n-\t.word\t0xffffffff\n-\t.word\t0x000008a6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000870\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_start\n-\t.word\t0x0000038a\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000262\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000001de\n- R_ARM_REL32\t.LC2\n-\t.word\t0x000001d4\n- R_ARM_REL32\t.LC12\n-\t.word\t0x000001b6\n- R_ARM_REL32\t.LC3\n-\t.word\t0x000001a8\n- R_ARM_REL32\t.LC4\n-\t.word\t0x0000019a\n- R_ARM_REL32\t.LC5\n-\t.word\t0x0000018c\n- R_ARM_REL32\t.LC6\n-\t.word\t0x0000017c\n- R_ARM_REL32\t.LC7\n-\t.word\t0x0000016e\n- R_ARM_REL32\t.LC8\n-\t.word\t0x00000162\n- R_ARM_REL32\t.LC9\n-\t.word\t0x000000f2\n- R_ARM_REL32\t.LC10\n-\t.word\t0x000000d4\n- R_ARM_REL32\t.LC14\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000007c\n- R_ARM_REL32\t.LC13\n-\tlsls\tr4, r2, #2\n+\tbne.n\teec <__gridxc_cell_MOD_cellxc+0x8d8>\n+\tb.n\te5a <__gridxc_cell_MOD_cellxc+0x846>\n+\tmov\tr3, r2\n+\tlsls\tr4, r3, #2\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #456]\t@ 0x1c8\n+\tstr.w\tr0, [r7, #448]\t@ 0x1c0\n \tcmp\tr0, #0\n-\tbeq.w\t16ba <__gridxc_cell_MOD_cellxc+0x10de>\n+\tbeq.w\t72ee <__gridxc_cell_MOD_cellxc+0x6cda>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #452]\t@ 0x1c4\n+\tstr.w\tr0, [r7, #444]\t@ 0x1bc\n \tcmp\tr0, #0\n-\tbeq.w\t16a8 <__gridxc_cell_MOD_cellxc+0x10cc>\n+\tbeq.w\t72cc <__gridxc_cell_MOD_cellxc+0x6cb8>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #436]\t@ 0x1b4\n+\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n \tcmp\tr0, #0\n-\tbeq.w\t1698 <__gridxc_cell_MOD_cellxc+0x10bc>\n+\tbeq.w\t72dc <__gridxc_cell_MOD_cellxc+0x6cc8>\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tmovw\tr9, #18764\t@ 0x494c\n-\tmovt\tr9, #22594\t@ 0x5842\n-\tcmp\tr3, #1\n-\tldr\tr3, [pc, #824]\t@ (1298 <__gridxc_cell_MOD_cellxc+0xcbc>)\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tldr\tr4, [r7, #76]\t@ 0x4c\n \tmov.w\tr8, #0\n+\tcmp\tr3, #1\n+\tldr\tr3, [pc, #420]\t@ (110c <__gridxc_cell_MOD_cellxc+0xaf8>)\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #636]\t@ 0x27c\n-\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tmov.w\tr3, #1\n-\tvldr\td8, [pc, #784]\t@ 1288 <__gridxc_cell_MOD_cellxc+0xcac>\n-\tit\tne\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tmovw\tr3, #18764\t@ 0x494c\n+\tmovt\tr3, #22594\t@ 0x5842\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tite\teq\n+\tmoveq\tr3, #1\n \tmovne\tr3, #2\n-\tstr.w\tr3, [r7, #652]\t@ 0x28c\n-\tb.n\tf9e <__gridxc_cell_MOD_cellxc+0x9c2>\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n+\tmov\tfp, r3\n+\tb.n\tfa0 <__gridxc_cell_MOD_cellxc+0x98c>\n+\tmov\tr3, fp\n \tadd.w\tr8, r8, #1\n-\tadds\tr4, #20\n \tadds\tr3, #4\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tcmp\tr8, r3\n-\tbeq.w\t1624 <__gridxc_cell_MOD_cellxc+0x1048>\n+\tadds\tr4, #20\n+\tmov\tfp, r3\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tcmp\tr3, r8\n+\tbeq.w\t1692 <__gridxc_cell_MOD_cellxc+0x107e>\n \tldr\tr3, [r4, #0]\n-\tcmp\tr3, r9\n-\tbne.n\tf84 <__gridxc_cell_MOD_cellxc+0x9a8>\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tcmp\tr3, r2\n+\tbne.n\tf8a <__gridxc_cell_MOD_cellxc+0x976>\n \tldrb\tr3, [r4, #4]\n \tcmp\tr3, #67\t@ 0x43\n-\tbne.n\tf84 <__gridxc_cell_MOD_cellxc+0x9a8>\n-\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n-\tmovs\tr2, #0\n-\tldr.w\tr3, [r7, #636]\t@ 0x27c\n-\tadd.w\tsl, r7, #928\t@ 0x3a0\n-\tmov\tr0, r1\n-\tstr.w\tr2, [r7, #832]\t@ 0x340\n-\tstr\tr3, [r1, #8]\n-\tadd.w\tr3, r7, #832\t@ 0x340\n-\tstr\tr2, [r1, #48]\t@ 0x30\n+\tbne.n\tf8a <__gridxc_cell_MOD_cellxc+0x976>\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmovs\tr1, #0\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tstr.w\tr1, [r7, #816]\t@ 0x330\n+\tstr\tr2, [r3, #8]\n+\tmov\tr2, r3\n+\tstr\tr1, [r3, #48]\t@ 0x30\n+\tadd.w\tr3, r7, #816\t@ 0x330\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tmov\tr0, r2\n+\tstr\tr3, [r2, #24]\n+\tmov\tr3, r2\n \tmov.w\tr2, #400\t@ 0x190\n-\tstr\tr3, [r1, #24]\n-\tstr\tr2, [r1, #12]\n+\tstr\tr2, [r3, #12]\n \tadds\tr2, r4, #6\n-\tvstr\td8, [r1]\n-\tstr\tr2, [r1, #68]\t@ 0x44\n+\tstr\tr2, [r3, #68]\t@ 0x44\n \tmovs\tr2, #5\n-\tstr\tr2, [r1, #72]\t@ 0x48\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n+\tstr\tr2, [r3, #72]\t@ 0x48\n+\tmovw\tr2, #16544\t@ 0x40a0\n+\tstrd\tr2, r9, [r3]\n+\tadd.w\tr9, r7, #912\t@ 0x390\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n-\tldr.w\tfp, [r7, #720]\t@ 0x2d0\n+\tldr.w\tsl, [r7, #760]\t@ 0x2f8\n \tmovs\tr2, #4\n-\tmov\tr1, sl\n-\tmov\tr0, fp\n+\tmov\tr1, r9\n+\tmov\tr0, sl\n \tbl\t0 <_gfortran_transfer_integer>\n R_ARM_THM_CALL\t_gfortran_transfer_integer\n-\tmov\tr0, fp\n+\tmov\tr0, sl\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n \tldr\tr3, [r3, #0]\n-\tcbz\tr3, 102c <__gridxc_cell_MOD_cellxc+0xa50>\n+\tcbz\tr3, 103e <__gridxc_cell_MOD_cellxc+0xa2a>\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #0]\n-\tldr\tr3, [pc, #664]\t@ (129c <__gridxc_cell_MOD_cellxc+0xcc0>)\n-\taddw\tr1, r7, #3060\t@ 0xbf4\n+\tldr\tr3, [pc, #248]\t@ (1110 <__gridxc_cell_MOD_cellxc+0xafc>)\n+\taddw\tr1, r7, #3036\t@ 0xbdc\n \tmovs\tr2, #18\n \tmovs\tr0, #38\t@ 0x26\n \tadd\tr3, pc\n \tstr\tr4, [sp, #4]\n-\tstr.w\tr1, [r7, #628]\t@ 0x274\n+\tstr.w\tr1, [r7, #560]\t@ 0x230\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tldr\tr3, [pc, #644]\t@ (12a0 <__gridxc_cell_MOD_cellxc+0xcc4>)\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr.w\tr1, [r7, #628]\t@ 0x274\n+\tldr\tr3, [pc, #216]\t@ (1104 <__gridxc_cell_MOD_cellxc+0xaf0>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [r7, #560]\t@ 0x230\n \tldr\tr3, [r2, r3]\n \tmov\tr0, r1\n \tmovs\tr1, #38\t@ 0x26\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tadd.w\tr2, r7, #932\t@ 0x3a4\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tadd.w\tr2, r7, #916\t@ 0x394\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tstr\tr3, [r2, #0]\n-\tldr.w\tr3, [r7, #404]\t@ 0x194\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #1\n-\tbeq.w\t16c8 <__gridxc_cell_MOD_cellxc+0x10ec>\n-\tmov\tr1, sl\n-\tldr.w\tsl, [r7, #740]\t@ 0x2e4\n+\tbne.n\t1062 <__gridxc_cell_MOD_cellxc+0xa4e>\n+\tldr.w\tr3, [r9]\n+\tcmp\tr3, #1\n+\titt\teq\n+\tmoveq.w\tr3, #532\t@ 0x214\n+\tstreq.w\tr3, [r9]\n \tmovs\tr3, #0\n-\tmov\tr0, sl\n+\tmov\tr1, r9\n+\tmov\tr0, fp\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_init>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_init\n-\tmov\tr0, sl\n+\tmov\tr0, fp\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_get_info>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_get_info\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n+\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n \tstr.w\tr0, [r3, r8, lsl #2]\n \tmovs\tr3, #1\n \tstr.w\tr3, [r2, r8, lsl #2]\n-\tb.n\tf84 <__gridxc_cell_MOD_cellxc+0x9a8>\n-\tldr\tr0, [pc, #568]\t@ (12a4 <__gridxc_cell_MOD_cellxc+0xcc8>)\n-\tmovs\tr3, #1\n-\tvmov.i64\td9, #0x0000000000000000\n+\tb.n\tf8a <__gridxc_cell_MOD_cellxc+0x976>\n+\tldr\tr0, [pc, #140]\t@ (1114 <__gridxc_cell_MOD_cellxc+0xb00>)\n+\tmov\tr9, r5\n \tldr\tr4, [r7, #72]\t@ 0x48\n+\tmov\tr5, r2\n \tadd\tr0, pc\n-\tstr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tldr\tr0, [pc, #556]\t@ (12a8 <__gridxc_cell_MOD_cellxc+0xccc>)\n-\tmov\tfp, r3\n+\tstr.w\tr0, [r7, #692]\t@ 0x2b4\n+\tldr\tr0, [pc, #128]\t@ (1118 <__gridxc_cell_MOD_cellxc+0xb04>)\n \tldr.w\tr8, [r7, #80]\t@ 0x50\n-\tmov\tr5, r1\n \tadd\tr0, pc\n-\tstr.w\tr0, [r7, #652]\t@ 0x28c\n-\tldr\tr0, [pc, #544]\t@ (12ac <__gridxc_cell_MOD_cellxc+0xcd0>)\n-\tstr.w\tr1, [r7, #540]\t@ 0x21c\n+\tstr.w\tr0, [r7, #600]\t@ 0x258\n+\tldr\tr0, [pc, #120]\t@ (111c <__gridxc_cell_MOD_cellxc+0xb08>)\n+\tvldr\td13, [pc, #20]\t@ 10b8 <__gridxc_cell_MOD_cellxc+0xaa4>\n \tadd\tr0, pc\n-\tstr.w\tr1, [r7, #692]\t@ 0x2b4\n-\tstr.w\tr0, [r7, #636]\t@ 0x27c\n-\tb.n\t113a <__gridxc_cell_MOD_cellxc+0xb5e>\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tstr.w\tr2, [r7, #520]\t@ 0x208\n+\tstr.w\tr0, [r7, #584]\t@ 0x248\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tb.n\t11c6 <__gridxc_cell_MOD_cellxc+0xbb2>\n+\tnop\n+\t...\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000a7c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000a32\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_start\n+\t.word\t0x00000566\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000402\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000037c\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x00000372\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x0000036a\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x00000352\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x00000344\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x00000336\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x00000328\n+ R_ARM_REL32\t.LC6\n+\t.word\t0x00000318\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x00000308\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x000002fc\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x00000262\n+ R_ARM_REL32\t.LC14\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x00000204\n+ R_ARM_REL32\t.LC13\n+\t.word\t0x000001a2\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x000000ee\n+ R_ARM_REL32\t.LC19\n+\t.word\t0x00000082\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x0000007a\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x00000072\n+ R_ARM_REL32\t.LC4\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t114c <__gridxc_cell_MOD_cellxc+0xb70>\n-\tldr.w\tr3, [r7, #636]\t@ 0x27c\n+\tbeq.n\t11d8 <__gridxc_cell_MOD_cellxc+0xbc4>\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t114c <__gridxc_cell_MOD_cellxc+0xb70>\n-\tldr\tr3, [pc, #492]\t@ (12b0 <__gridxc_cell_MOD_cellxc+0xcd4>)\n+\tbeq.n\t11d8 <__gridxc_cell_MOD_cellxc+0xbc4>\n+\tldr.w\tr3, [pc, #1424]\t@ 16d8 <__gridxc_cell_MOD_cellxc+0x10c4>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t114c <__gridxc_cell_MOD_cellxc+0xb70>\n-\tldr\tr3, [pc, #480]\t@ (12b4 <__gridxc_cell_MOD_cellxc+0xcd8>)\n+\tbeq.n\t11d8 <__gridxc_cell_MOD_cellxc+0xbc4>\n+\tldr.w\tr3, [pc, #1408]\t@ 16dc <__gridxc_cell_MOD_cellxc+0x10c8>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1150 <__gridxc_cell_MOD_cellxc+0xb74>\n-\tldr\tr3, [pc, #468]\t@ (12b8 <__gridxc_cell_MOD_cellxc+0xcdc>)\n+\tcbz\tr0, 11dc <__gridxc_cell_MOD_cellxc+0xbc8>\n+\tldr.w\tr3, [pc, #1396]\t@ 16e0 <__gridxc_cell_MOD_cellxc+0x10cc>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1150 <__gridxc_cell_MOD_cellxc+0xb74>\n-\tldr\tr3, [pc, #456]\t@ (12bc <__gridxc_cell_MOD_cellxc+0xce0>)\n+\tcbz\tr0, 11dc <__gridxc_cell_MOD_cellxc+0xbc8>\n+\tldr.w\tr3, [pc, #1380]\t@ 16e4 <__gridxc_cell_MOD_cellxc+0x10d0>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 1112 <__gridxc_cell_MOD_cellxc+0xb36>\n-\tldr\tr3, [pc, #444]\t@ (12c0 <__gridxc_cell_MOD_cellxc+0xce4>)\n+\tcbz\tr0, 11a0 <__gridxc_cell_MOD_cellxc+0xb8c>\n+\tldr.w\tr3, [pc, #1368]\t@ 16e8 <__gridxc_cell_MOD_cellxc+0x10d4>\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 1158 <__gridxc_cell_MOD_cellxc+0xb7c>\n-\tvldr\td16, [r8]\n+\tcbnz\tr0, 11e4 <__gridxc_cell_MOD_cellxc+0xbd0>\n+\tvldr\td7, [r8]\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #540]\t@ 0x21c\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tvadd.f64\td9, d9, d16\n-\tmov\tr3, fp\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n+\tvadd.f64\td13, d13, d7\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd.w\tr9, r9, #1\n \tadds\tr4, #20\n-\tmov\tfp, r3\n \tadd.w\tr8, r8, #8\n-\tcmp\tr2, r3\n-\tblt.w\tf04 <__gridxc_cell_MOD_cellxc+0x928>\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tcmp\tr3, r9\n+\tblt.w\tf0e <__gridxc_cell_MOD_cellxc+0x8fa>\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #20\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.n\t109c <__gridxc_cell_MOD_cellxc+0xac0>\n+\tbne.n\t1120 <__gridxc_cell_MOD_cellxc+0xb0c>\n \tmovs\tr5, #1\n-\tb.n\t1124 <__gridxc_cell_MOD_cellxc+0xb48>\n+\tb.n\t11b2 <__gridxc_cell_MOD_cellxc+0xb9e>\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tb.n\t1124 <__gridxc_cell_MOD_cellxc+0xb48>\n-\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n-\tmov.w\tr9, #80\t@ 0x50\n-\tvldr\td16, [pc, #300]\t@ 1290 <__gridxc_cell_MOD_cellxc+0xcb4>\n+\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n+\tb.n\t11b2 <__gridxc_cell_MOD_cellxc+0xb9e>\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tldr.w\tr3, [pc, #1276]\t@ 16ec <__gridxc_cell_MOD_cellxc+0x10d8>\n \tmov\tr0, r2\n-\tldr\tr3, [pc, #348]\t@ (12c4 <__gridxc_cell_MOD_cellxc+0xce8>)\n-\tstr.w\tr9, [r2, #72]\t@ 0x48\n-\tvstr\td16, [r2]\n \tadd\tr3, pc\n \tstr\tr3, [r2, #8]\n-\taddw\tr3, r7, #3100\t@ 0xc1c\n+\taddw\tr3, r7, #3076\t@ 0xc04\n \tstr\tr3, [r2, #68]\t@ 0x44\n+\tmovs\tr2, #80\t@ 0x50\n+\tstr\tr2, [r0, #72]\t@ 0x48\n \tmovs\tr2, #0\n \tstr\tr2, [r0, #48]\t@ 0x30\n+\tmov.w\tr2, #16512\t@ 0x4080\n+\tstrd\tr2, r1, [r0]\n \tmovw\tr2, #385\t@ 0x181\n \tstr\tr2, [r0, #12]\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr.w\tsl, [r7, #720]\t@ 0x2d0\n+\tldr.w\tsl, [r7, #760]\t@ 0x2f8\n \tmovs\tr2, #33\t@ 0x21\n-\tldr\tr1, [pc, #308]\t@ (12c8 <__gridxc_cell_MOD_cellxc+0xcec>)\n+\tldr.w\tr1, [pc, #1228]\t@ 16f0 <__gridxc_cell_MOD_cellxc+0x10dc>\n \tmov\tr0, sl\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmovs\tr2, #20\n \tmov\tr1, r4\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, r9\n-\tadd.w\tr1, r7, #976\t@ 0x3d0\n-\tadd.w\tr0, r7, #984\t@ 0x3d8\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n-\tmov\tsl, r1\n-\tmov\tr9, r0\n+\tadd.w\tr1, r7, #960\t@ 0x3c0\n+\tadd.w\tr0, r7, #968\t@ 0x3c8\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tmovs\tr2, #80\t@ 0x50\n+\tmov\tfp, r1\n+\tmov\tsl, r0\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #220]\t@ (12a0 <__gridxc_cell_MOD_cellxc+0xcc4>)\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr.w\tr9, [r9]\n-\tldr.w\tr0, [sl]\n+\tldr.w\tr3, [pc, #1184]\t@ 16f4 <__gridxc_cell_MOD_cellxc+0x10e0>\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [sl]\n+\tldr.w\tr0, [fp]\n \tldr\tr3, [r2, r3]\n-\tmov\tr1, r9\n-\tstr.w\tr0, [r7, #628]\t@ 0x274\n+\tstr.w\tr1, [r7, #552]\t@ 0x228\n+\tstr.w\tr0, [r7, #560]\t@ 0x230\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp.w\tr9, #0\n-\tble.n\t1124 <__gridxc_cell_MOD_cellxc+0xb48>\n-\tldr.w\tr0, [r7, #628]\t@ 0x274\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tcmp\tr1, #0\n+\tble.n\t11b2 <__gridxc_cell_MOD_cellxc+0xb9e>\n+\tldr.w\tr0, [r7, #560]\t@ 0x230\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t1124 <__gridxc_cell_MOD_cellxc+0xb48>\n-\tstr.w\tsl, [r7, #724]\t@ 0x2d4\n-\tb.n\tb56 <__gridxc_cell_MOD_cellxc+0x57a>\n-\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n-\tmov.w\tr9, #80\t@ 0x50\n-\tvldr\td16, [pc, #148]\t@ 1290 <__gridxc_cell_MOD_cellxc+0xcb4>\n+\tb.n\t11b2 <__gridxc_cell_MOD_cellxc+0xb9e>\n+\tstr.w\tr8, [r7, #732]\t@ 0x2dc\n+\tb.n\tb82 <__gridxc_cell_MOD_cellxc+0x56e>\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tldr.w\tr3, [pc, #1124]\t@ 16f8 <__gridxc_cell_MOD_cellxc+0x10e4>\n \tmov\tr0, r2\n-\tldr\tr3, [pc, #200]\t@ (12cc <__gridxc_cell_MOD_cellxc+0xcf0>)\n-\tstr.w\tr9, [r2, #72]\t@ 0x48\n-\tvstr\td16, [r2]\n \tadd\tr3, pc\n \tstr\tr3, [r2, #8]\n-\taddw\tr3, r7, #3100\t@ 0xc1c\n+\taddw\tr3, r7, #3076\t@ 0xc04\n \tstr\tr3, [r2, #68]\t@ 0x44\n+\tmovs\tr2, #80\t@ 0x50\n+\tstr\tr2, [r0, #72]\t@ 0x48\n \tmovs\tr2, #0\n \tstr\tr2, [r0, #48]\t@ 0x30\n+\tmov.w\tr2, #16512\t@ 0x4080\n+\tstrd\tr2, r1, [r0]\n \tmovw\tr2, #385\t@ 0x181\n \tstr\tr2, [r0, #12]\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr.w\tsl, [r7, #720]\t@ 0x2d0\n+\tldr.w\tsl, [r7, #760]\t@ 0x2f8\n \tmovs\tr2, #33\t@ 0x21\n-\tldr\tr1, [pc, #160]\t@ (12d0 <__gridxc_cell_MOD_cellxc+0xcf4>)\n+\tldr.w\tr1, [pc, #1076]\t@ 16fc <__gridxc_cell_MOD_cellxc+0x10e8>\n \tmov\tr0, sl\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmovs\tr2, #20\n \tmov\tr1, r4\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, r9\n-\tadd.w\tr1, r7, #976\t@ 0x3d0\n-\tadd.w\tr0, r7, #984\t@ 0x3d8\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n-\tmov\tsl, r1\n-\tmov\tr9, r0\n+\tadd.w\tr1, r7, #960\t@ 0x3c0\n+\tadd.w\tr0, r7, #968\t@ 0x3c8\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tmovs\tr2, #80\t@ 0x50\n+\tmov\tfp, r1\n+\tmov\tsl, r0\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #64]\t@ (12a0 <__gridxc_cell_MOD_cellxc+0xcc4>)\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr.w\tr9, [r9]\n-\tldr.w\tr0, [sl]\n+\tldr\tr3, [pc, #1020]\t@ (16f4 <__gridxc_cell_MOD_cellxc+0x10e0>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [sl]\n+\tldr.w\tr0, [fp]\n \tldr\tr3, [r2, r3]\n-\tmov\tr1, r9\n-\tstr.w\tr0, [r7, #628]\t@ 0x274\n+\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tstr.w\tr0, [r7, #552]\t@ 0x228\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp.w\tr9, #0\n-\tble.w\tda8 <__gridxc_cell_MOD_cellxc+0x7cc>\n-\tldr.w\tr0, [r7, #628]\t@ 0x274\n+\tldr.w\tr1, [r7, #536]\t@ 0x218\n+\tcmp\tr1, #0\n+\tble.w\te1a <__gridxc_cell_MOD_cellxc+0x806>\n+\tldr.w\tr0, [r7, #552]\t@ 0x228\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\tda8 <__gridxc_cell_MOD_cellxc+0x7cc>\n-\t.word\t0x000040a0\n-\t.word\t0xffffffff\n-\t.word\t0x00004080\n-\t.word\t0xffffffff\n-\t.word\t0x00000330\n- R_ARM_REL32\t.LC10\n-\t.word\t0x0000028c\n- R_ARM_REL32\t.LC19\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000022c\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000220\n- R_ARM_REL32\t.LC3\n-\t.word\t0x00000218\n- R_ARM_REL32\t.LC4\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.LC5\n-\t.word\t0x000001d6\n- R_ARM_REL32\t.LC6\n-\t.word\t0x000001ca\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000001be\n- R_ARM_REL32\t.LC8\n-\t.word\t0x000001b2\n- R_ARM_REL32\t.LC9\n-\t.word\t0x00000150\n- R_ARM_REL32\t.LC10\n-\t.word\t0x0000012e\n- R_ARM_REL32\t.LC11\n-\t.word\t0x000000be\n- R_ARM_REL32\t.LC10\n-\t.word\t0x0000009c\n- R_ARM_REL32\t.LC11\n-\tmovs\tr0, #1\n+\tb.n\te1a <__gridxc_cell_MOD_cellxc+0x806>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #456]\t@ 0x1c8\n+\tstr.w\tr0, [r7, #448]\t@ 0x1c0\n \tcmp\tr0, #0\n-\tbeq.w\t16b6 <__gridxc_cell_MOD_cellxc+0x10da>\n-\tmovs\tr0, #1\n+\tbeq.w\t72ea <__gridxc_cell_MOD_cellxc+0x6cd6>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #452]\t@ 0x1c4\n+\tstr.w\tr0, [r7, #444]\t@ 0x1bc\n \tcmp\tr0, #0\n-\tbeq.w\t16a6 <__gridxc_cell_MOD_cellxc+0x10ca>\n-\tmovs\tr0, #1\n+\tbeq.w\t72ca <__gridxc_cell_MOD_cellxc+0x6cb6>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r7, #436]\t@ 0x1b4\n+\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n \tcmp\tr0, #0\n-\tbeq.w\t1696 <__gridxc_cell_MOD_cellxc+0x10ba>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tbeq.w\t72da <__gridxc_cell_MOD_cellxc+0x6cc6>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbne.w\t1676 <__gridxc_cell_MOD_cellxc+0x109a>\n-\tvmov.i64\td9, #0x0000000000000000\n-\tstr.w\tr3, [r7, #540]\t@ 0x21c\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tadd.w\tr3, r7, #1040\t@ 0x410\n-\tldr\tr4, [pc, #984]\t@ (16f8 <__gridxc_cell_MOD_cellxc+0x111c>)\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tbne.w\t173e <__gridxc_cell_MOD_cellxc+0x112a>\n+\tvldr\td13, [pc, #876]\t@ 16d0 <__gridxc_cell_MOD_cellxc+0x10bc>\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #700]\t@ 0x2bc\n+\tadd.w\tr2, r7, #1024\t@ 0x400\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr\tr4, [pc, #904]\t@ (1700 <__gridxc_cell_MOD_cellxc+0x10ec>)\n \tmov\tr1, r6\n-\tstr.w\tr2, [r7, #1056]\t@ 0x420\n+\tstr\tr2, [r7, #84]\t@ 0x54\n+\tstr\tr3, [r2, #0]\n \tadd\tr4, pc\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tadds\tr0, r4, #4\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tr2, [r7, #1060]\t@ 0x424\n-\tmov\tr2, r3\n-\tvst1.64\t{d10-d11}, [r3 :64]\n+\tstr\tr3, [r2, #8]\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr\tr3, [r2, #16]\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tstr\tr3, [r2, #4]\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr\tr3, [r2, #12]\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr\tr3, [r2, #20]\n \tmovs\tr3, #0\n \tstrd\tr3, r3, [sp, #20]\n \tstrd\tr3, r3, [sp, #12]\n \tstrd\tr3, r3, [sp, #4]\n \tstr\tr3, [sp, #0]\n \tbl\t0 <__gridxc_mesh3d_MOD_setmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_setmeshdistr\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n \tcmp\tr3, #0\n-\tbeq.w\t5bec <__gridxc_cell_MOD_cellxc+0x5610>\n+\tbeq.w\t460c <__gridxc_cell_MOD_cellxc+0x3ff8>\n \tldr\tr2, [r4, #4]\n-\tldr\tr3, [pc, #924]\t@ (16fc <__gridxc_cell_MOD_cellxc+0x1120>)\n+\tldr\tr3, [pc, #836]\t@ (1704 <__gridxc_cell_MOD_cellxc+0x10f0>)\n \tstr\tr2, [r4, #0]\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n \tldr\tr3, [r2, r3]\n-\tstr\tr3, [r7, #48]\t@ 0x30\n-\tadd.w\tr3, r7, #2992\t@ 0xbb0\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\taddw\tr3, r7, #2968\t@ 0xb98\n \tmov\tr2, r3\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tldr\tr4, [pc, #904]\t@ (1700 <__gridxc_cell_MOD_cellxc+0x1124>)\n+\tstr.w\tr3, [r7, #452]\t@ 0x1c4\n+\tldr\tr4, [pc, #816]\t@ (1708 <__gridxc_cell_MOD_cellxc+0x10f4>)\n \tmov\tr0, r6\n \tadd\tr4, pc\n \tmov\tr1, r4\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n \tldr.w\tr1, [r3, #504]\t@ 0x1f8\n \tldr.w\tr0, [r3, #516]\t@ 0x204\n \tldr.w\tr2, [r3, #508]\t@ 0x1fc\n \tldr.w\tr5, [r3, #512]\t@ 0x200\n \tldr.w\tr6, [r3, #524]\t@ 0x20c\n \tldr.w\tr3, [r3, #520]\t@ 0x208\n-\tstr.w\tr2, [r7, #668]\t@ 0x29c\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n \tsubs\tr2, r2, r1\n-\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr1, [r7, #692]\t@ 0x2b4\n \tadds\tr1, r4, #4\n-\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tstr.w\tr0, [r7, #644]\t@ 0x284\n \tstr.w\tr5, [r7, #688]\t@ 0x2b0\n \tsubs\tr5, r0, r5\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n \tmov\tr0, r4\n \tsubs\tr3, r6, r3\n-\tstr.w\tr2, [r7, #656]\t@ 0x290\n-\tstr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n \tadds\tr2, #1\n \tadds\tr3, #1\n-\tstr.w\tr2, [r7, #484]\t@ 0x1e4\n-\tstr.w\tr6, [r7, #652]\t@ 0x28c\n+\tstr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr6, [r7, #636]\t@ 0x27c\n \tadds\tr2, r5, #1\n-\tstr.w\tr5, [r7, #524]\t@ 0x20c\n-\tstr.w\tr2, [r7, #480]\t@ 0x1e0\n-\tstr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr5, [r7, #508]\t@ 0x1fc\n+\tstr.w\tr2, [r7, #468]\t@ 0x1d4\n+\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n \tbl\t0 <__gridxc_mesh3d_MOD_samemeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_samemeshdistr\n \tcmp\tr0, #0\n-\tbeq.w\t5a88 <__gridxc_cell_MOD_cellxc+0x54ac>\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tbeq.w\t44a8 <__gridxc_cell_MOD_cellxc+0x3e94>\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbeq.w\t5a66 <__gridxc_cell_MOD_cellxc+0x548a>\n+\tbeq.w\t441c <__gridxc_cell_MOD_cellxc+0x3e08>\n \tldr\tr3, [r4, #0]\n \tcmp\tr3, #0\n-\tbne.w\t5a88 <__gridxc_cell_MOD_cellxc+0x54ac>\n-\tldr\tr3, [pc, #776]\t@ (1704 <__gridxc_cell_MOD_cellxc+0x1128>)\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tbne.w\t44a8 <__gridxc_cell_MOD_cellxc+0x3e94>\n+\tldr\tr3, [pc, #688]\t@ (170c <__gridxc_cell_MOD_cellxc+0x10f8>)\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n \tadd\tr3, pc\n-\tldr.w\tr6, [r2, #552]\t@ 0x228\n+\tldr.w\tr2, [r2, #552]\t@ 0x228\n \tldr.w\tr3, [r3, #144]\t@ 0x90\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n \tcmp\tr3, #0\n-\tbeq.w\t1740 <__gridxc_cell_MOD_cellxc+0x1164>\n-\tadd.w\tr3, r7, #984\t@ 0x3d8\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr\tr2, [pc, #752]\t@ (1708 <__gridxc_cell_MOD_cellxc+0x112c>)\n+\tbeq.w\t1770 <__gridxc_cell_MOD_cellxc+0x115c>\n+\tadd.w\tr3, r7, #968\t@ 0x3c8\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr\tr2, [pc, #660]\t@ (1710 <__gridxc_cell_MOD_cellxc+0x10fc>)\n \tadd\tr2, pc\n \tadds\tr5, r2, #4\n \tadd.w\tr4, r2, #40\t@ 0x28\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tldr.w\tr0, [r7, #720]\t@ 0x2d0\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tvldr\td16, [pc, #680]\t@ 16e0 <__gridxc_cell_MOD_cellxc+0x1104>\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #564]\t@ 0x234\n \tmov\tr1, r5\n-\tstr\tr3, [r0, #32]\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tstr\tr3, [r0, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tstr\tr3, [r0, #56]\t@ 0x38\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tstr\tr3, [r0, #68]\t@ 0x44\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n-\tvstr\td17, [r3]\n-\tldr.w\tr3, [r7, #548]\t@ 0x224\n-\tldr.w\tr2, [r5, #532]\t@ 0x214\n-\tldr.w\tr6, [r5, #552]\t@ 0x228\n-\tvst1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r5, #544]\t@ 0x220\n-\tstr\tr3, [r0, #60]\t@ 0x3c\n+\tldr.w\tr0, [r7, #792]\t@ 0x318\n+\tmov\tr5, r2\n+\tstr\tr3, [r2, #32]\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr\tr3, [r2, #44]\t@ 0x2c\n+\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tstr\tr3, [r2, #56]\t@ 0x38\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tstr\tr3, [r2, #68]\t@ 0x44\n+\tldr.w\tr3, [r0, #544]\t@ 0x220\n+\tstr\tr3, [r2, #60]\t@ 0x3c\n \tnegs\tr3, r3\n-\tstr\tr3, [r0, #4]\n-\tldr\tr3, [pc, #660]\t@ (170c <__gridxc_cell_MOD_cellxc+0x1130>)\n-\tstr\tr2, [r0, #36]\t@ 0x24\n-\tldr.w\tr2, [r5, #536]\t@ 0x218\n-\tadd\tr3, pc\n-\tstr\tr2, [r0, #48]\t@ 0x30\n-\tadds\tr3, #144\t@ 0x90\n-\tldr.w\tr2, [r5, #528]\t@ 0x210\n-\tstr\tr2, [r0, #0]\n-\tmovs\tr2, #0\n-\tstr\tr2, [r0, #28]\n-\tstr\tr2, [r0, #40]\t@ 0x28\n-\tstr\tr2, [r0, #52]\t@ 0x34\n-\tmovs\tr2, #8\n-\tstr\tr2, [r0, #8]\n-\tmov.w\tr2, #772\t@ 0x304\n-\tstrh\tr2, [r0, #16]\n-\tmovs\tr2, #1\n-\tstr\tr2, [r0, #64]\t@ 0x40\n-\tmov\tr2, r0\n-\tstrd\tr3, r4, [sp]\n+\tstr\tr3, [r2, #4]\n+\tldr.w\tr3, [r0, #532]\t@ 0x214\n+\tstr\tr3, [r5, #36]\t@ 0x24\n+\tldr.w\tr3, [r0, #536]\t@ 0x218\n+\tldr.w\tr6, [r0, #552]\t@ 0x228\n+\tstr\tr3, [r5, #48]\t@ 0x30\n+\tldr\tr2, [pc, #584]\t@ (1714 <__gridxc_cell_MOD_cellxc+0x1100>)\n+\tldr.w\tr3, [r0, #528]\t@ 0x210\n+\tldr.w\tr0, [r7, #648]\t@ 0x288\n+\tadd\tr2, pc\n+\tstr\tr3, [r5, #0]\n+\tadds\tr2, #144\t@ 0x90\n+\tmovs\tr3, #0\n+\tstr.w\tr6, [r7, #656]\t@ 0x290\n+\tstrd\tr3, r3, [r0]\n \tmov\tr0, r6\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr\tr3, [r5, #28]\n+\tstr\tr3, [r5, #40]\t@ 0x28\n+\tstr\tr3, [r5, #52]\t@ 0x34\n+\tmovs\tr3, #8\n+\tstr\tr3, [r5, #20]\n+\tstr\tr3, [r5, #8]\n+\tmovs\tr3, #1\n+\tstr\tr3, [r5, #24]\n+\tstr\tr3, [r5, #64]\t@ 0x40\n+\tmov.w\tr3, #772\t@ 0x304\n+\tstrh\tr3, [r5, #16]\n+\tstrd\tr2, r4, [sp]\n+\tmov\tr2, r5\n+\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbeq.w\t5a7c <__gridxc_cell_MOD_cellxc+0x54a0>\n-\tldr\tr3, [pc, #596]\t@ (1710 <__gridxc_cell_MOD_cellxc+0x1134>)\n-\tadd\tr3, pc\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n-\tldr\tr3, [r3, #0]\n+\tbeq.w\t1aae <__gridxc_cell_MOD_cellxc+0x149a>\n+\tldr.w\tr8, [pc, #512]\t@ 1718 <__gridxc_cell_MOD_cellxc+0x1104>\n+\tadd\tr8, pc\n+\tldr.w\tr3, [r8]\n \tcmp\tr3, #0\n-\tbeq.w\t5a5a <__gridxc_cell_MOD_cellxc+0x547e>\n-\tadd.w\tr3, r7, #992\t@ 0x3e0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tadd.w\tr5, r7, #1016\t@ 0x3f8\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tbeq.w\t1778 <__gridxc_cell_MOD_cellxc+0x1164>\n+\tldr\tr6, [pc, #500]\t@ (171c <__gridxc_cell_MOD_cellxc+0x1108>)\n \tmovs\tr2, #72\t@ 0x48\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n-\tmov\tfp, r5\n-\tldr\tr4, [pc, #556]\t@ (1714 <__gridxc_cell_MOD_cellxc+0x1138>)\n-\tstrd\tr3, r5, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #644]\t@ 0x284\n-\tadd\tr4, pc\n-\tadd.w\tr1, r4, #216\t@ 0xd8\n-\taddw\tr0, r4, #1140\t@ 0x474\n-\tadd.w\tr5, r3, #56\t@ 0x38\n-\tadds\tr3, #68\t@ 0x44\n-\tmov\tsl, r3\n-\tstr.w\tr5, [r7, #752]\t@ 0x2f0\n-\tvldr\td10, [pc, #480]\t@ 16e8 <__gridxc_cell_MOD_cellxc+0x110c>\n+\tldr.w\tr5, [r7, #792]\t@ 0x318\n+\tadd.w\tr3, r7, #976\t@ 0x3d0\n+\tadd\tr6, pc\n+\tadd.w\tr4, r7, #1000\t@ 0x3e8\n+\tadd.w\tr1, r6, #216\t@ 0xd8\n+\taddw\tr0, r6, #1140\t@ 0x474\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tadd.w\tr3, r8, #56\t@ 0x38\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tadd.w\tr3, r8, #68\t@ 0x44\n+\tstr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tstr.w\tr4, [r7, #744]\t@ 0x2e8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tvldr\td8, [pc, #480]\t@ 16f0 <__gridxc_cell_MOD_cellxc+0x1114>\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r4, #288\t@ 0x120\n-\taddw\tr0, r4, #1212\t@ 0x4bc\n+\tadd.w\tr1, r6, #288\t@ 0x120\n+\taddw\tr0, r6, #1212\t@ 0x4bc\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmov\tr5, fp\n-\tldr.w\tip, [r7, #460]\t@ 0x1cc\n-\tldr.w\tr9, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r3, #504]\t@ 0x1f8\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tadd.w\tr3, r6, #144\t@ 0x90\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tip, [r7, #452]\t@ 0x1c4\n+\tldr.w\tlr, [r7, #784]\t@ 0x310\n+\tldrd\tr2, r3, [r1, #504]\t@ 0x1f8\n \tmov\tr4, ip\n-\tmov\tlr, r9\n-\tvdup.32\td16, r3\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n+\tsub.w\tfp, r2, #3\n+\tadd.w\tsl, r2, #4294967295\t@ 0xffffffff\n+\tadd.w\tr9, r3, #3\n+\tadds\tr2, r3, #1\n+\tstr.w\tr2, [r7, #592]\t@ 0x250\n \tldmia\tr4!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tvadd.i32\td16, d16, d10\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n \tldmia.w\tr4, {r0, r1}\n \tstmia.w\tlr, {r0, r1}\n-\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tvst1.64\t{d16}, [r1 :64]!\n-\tldr.w\tr3, [r2, #508]\t@ 0x1fc\n-\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tvdup.32\td16, r3\n+\tstrd\tfp, sl, [r2]\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tmovs\tr2, #0\n \tldmia.w\tr4, {r0, r1}\n \tstmia.w\tr5, {r0, r1}\n-\tvadd.i32\td16, d16, d8\n-\tldr.w\tr1, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr8, [r7, #644]\t@ 0x284\n-\tldr.w\tr4, [r7, #752]\t@ 0x2f0\n-\tvst1.64\t{d16}, [r1 :64]!\n-\tmov\tr0, r4\n-\tstr.w\tr1, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tmov\tr1, r8\n+\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\taddw\tr5, r6, #1212\t@ 0x4bc\n+\tstrd\tr4, r9, [r0]\n+\tldr.w\tr4, [r7, #768]\t@ 0x300\n+\tmov\tr0, r4\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tmov\tr1, r8\n-\tmov\tr0, sl\n+\tldr.w\tfp, [r7, #608]\t@ 0x260\n \tmovs\tr2, #0\n+\tmov\tr1, r8\n+\tmov\tr0, fp\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tstr.w\tr4, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr4, [r7, #768]\t@ 0x300\n \tstr\tr4, [sp, #4]\n-\tmov\tr3, r9\n-\tldr\tr4, [pc, #364]\t@ (1718 <__gridxc_cell_MOD_cellxc+0x113c>)\n+\taddw\tr4, r6, #1140\t@ 0x474\n+\tstr\tr4, [sp, #0]\n \tmov\tr1, r8\n-\tmov\tr9, r8\n-\tmov\tr0, r6\n-\tadd\tr4, pc\n-\tadd.w\tr5, r4, #144\t@ 0x90\n-\taddw\tr8, r4, #1140\t@ 0x474\n-\tmov\tr2, r5\n-\tstr.w\tr8, [sp]\n+\tldr.w\tsl, [r7, #584]\t@ 0x248\n+\tldr.w\tr9, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov\tr2, sl\n+\tmov\tr0, r9\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tmov\tr2, r5\n-\tmov\tr3, fp\n-\tmov\tr1, r9\n-\tmov\tr0, r6\n-\tstr.w\tsl, [sp, #4]\n-\taddw\tr5, r4, #1212\t@ 0x4bc\n+\tstr.w\tfp, [sp, #4]\n \tstr\tr5, [sp, #0]\n+\tmov\tr2, sl\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tmov\tr1, r8\n+\tmov\tr0, r9\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tmov\tr0, sl\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n+\tadds\tr1, #8\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n \tadd.w\tr1, r2, #8\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadds\tr3, #1\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadds\tr2, #4\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadds\tr2, r0, #4\n+\tstr.w\tr1, [r7, #736]\t@ 0x2e0\n+\tadd.w\tr1, r0, #8\n+\tstr.w\tr1, [r7, #744]\t@ 0x2e8\n+\tadds\tr1, r2, #4\n+\tmov\tr2, fp\n \tcmp\tr3, #4\n-\tmov\tsl, r2\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tbeq.w\t1750 <__gridxc_cell_MOD_cellxc+0x1174>\n+\tadd.w\tr2, r2, #4\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tstr.w\tr1, [r7, #768]\t@ 0x300\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tbeq.w\t1778 <__gridxc_cell_MOD_cellxc+0x1164>\n \tcmp\tr3, #2\n-\tbeq.n\t165c <__gridxc_cell_MOD_cellxc+0x1080>\n-\tmov\tr1, r4\n-\tmov\tr0, r8\n+\tbeq.n\t1724 <__gridxc_cell_MOD_cellxc+0x1110>\n+\tmov\tr1, r6\n+\tmov\tr0, r4\n \tmovs\tr2, #72\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tadd.w\tr1, r4, #72\t@ 0x48\n-\tmov\tr0, r5\n \tmovs\tr2, #72\t@ 0x48\n+\tmov\tr0, r5\n+\tadds\tr1, r6, r2\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\t1524 <__gridxc_cell_MOD_cellxc+0xf48>\n-\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tb.n\t1584 <__gridxc_cell_MOD_cellxc+0xf70>\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n \teor.w\tr3, r5, #1\n-\tand.w\tr3, r3, #1\n \tcmp\tr2, #0\n-\tit\teq\n+\tite\teq\n \tmoveq\tr3, #0\n-\tcbnz\tr3, 1682 <__gridxc_cell_MOD_cellxc+0x10a6>\n+\tandne.w\tr3, r3, #1\n+\tcmp\tr3, #0\n+\tbne.n\t174a <__gridxc_cell_MOD_cellxc+0x1136>\n \tcmp\tr2, #0\n-\tbeq.w\t131a <__gridxc_cell_MOD_cellxc+0xd3e>\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tbeq.w\t136c <__gridxc_cell_MOD_cellxc+0xd58>\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, #2\n-\tble.w\t131a <__gridxc_cell_MOD_cellxc+0xd3e>\n-\tldr\tr3, [pc, #208]\t@ (171c <__gridxc_cell_MOD_cellxc+0x1140>)\n+\tble.w\t136c <__gridxc_cell_MOD_cellxc+0xd58>\n+\tldr\tr3, [pc, #56]\t@ (16f4 <__gridxc_cell_MOD_cellxc+0x10e0>)\n \tmovs\tr1, #54\t@ 0x36\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr\tr0, [pc, #204]\t@ (1720 <__gridxc_cell_MOD_cellxc+0x1144>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr\tr0, [pc, #92]\t@ (1720 <__gridxc_cell_MOD_cellxc+0x110c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t131a <__gridxc_cell_MOD_cellxc+0xd3e>\n-\tadd.w\tr1, r4, #360\t@ 0x168\n-\tmov\tr0, r8\n+\tb.n\t136c <__gridxc_cell_MOD_cellxc+0xd58>\n+\tnop.w\n+\t...\n+\t.word\t0x00000586\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x00000576\n+ R_ARM_REL32\t.LC6\n+\t.word\t0x00000568\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x0000055a\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x0000054c\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x000004f6\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x000004c6\n+ R_ARM_REL32\t.LC11\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x0000045e\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x0000042e\n+ R_ARM_REL32\t.LC11\n+\t.word\t0x00000380\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n+\t.word\t0x0000032c\n+ R_ARM_REL32\t.data\n+\t.word\t0x000002aa\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000290\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000023c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001fa\n+ R_ARM_REL32\t.data\n+\t.word\t0x000001e6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000058\n+ R_ARM_REL32\t.LC21\n+\tadd.w\tr1, r6, #360\t@ 0x168\n+\tmov\tr0, r4\n \tmovs\tr2, #72\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tadd.w\tr1, r4, #432\t@ 0x1b0\n \tmov\tr0, r5\n \tmovs\tr2, #72\t@ 0x48\n+\tadd.w\tr1, r6, #432\t@ 0x1b0\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\t1524 <__gridxc_cell_MOD_cellxc+0xf48>\n-\tvmov.i64\td9, #0x0000000000000000\n-\tstr.w\tr4, [r7, #540]\t@ 0x21c\n-\tstr.w\tr4, [r7, #692]\t@ 0x2b4\n-\tldr\tr3, [pc, #152]\t@ (171c <__gridxc_cell_MOD_cellxc+0x1140>)\n+\tb.n\t1584 <__gridxc_cell_MOD_cellxc+0xf70>\n+\tvldr\td13, [pc, #32]\t@ 1760 <__gridxc_cell_MOD_cellxc+0x114c>\n+\tstr.w\tr4, [r7, #520]\t@ 0x208\n+\tstr.w\tr4, [r7, #700]\t@ 0x2bc\n+\tldr\tr3, [pc, #28]\t@ (1768 <__gridxc_cell_MOD_cellxc+0x1154>)\n \tmovs\tr1, #43\t@ 0x2b\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr\tr0, [pc, #152]\t@ (1724 <__gridxc_cell_MOD_cellxc+0x1148>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr\tr0, [pc, #24]\t@ (176c <__gridxc_cell_MOD_cellxc+0x1158>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t163e <__gridxc_cell_MOD_cellxc+0x1062>\n-\tmov\tr4, r0\n-\tldr\tr1, [pc, #140]\t@ (1728 <__gridxc_cell_MOD_cellxc+0x114c>)\n-\tmov\tr2, r4\n-\tldr\tr0, [pc, #140]\t@ (172c <__gridxc_cell_MOD_cellxc+0x1150>)\n-\tadd\tr1, pc\n-\tadd\tr0, pc\n-\tbl\t0 <_gfortran_os_error_at>\n- R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tmov\tr4, r0\n-\tldr\tr1, [pc, #132]\t@ (1730 <__gridxc_cell_MOD_cellxc+0x1154>)\n-\tmov\tr2, r4\n-\tldr\tr0, [pc, #132]\t@ (1734 <__gridxc_cell_MOD_cellxc+0x1158>)\n-\tadd\tr1, pc\n-\tadd\tr0, pc\n-\tbl\t0 <_gfortran_os_error_at>\n- R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr\tr1, [pc, #124]\t@ (1738 <__gridxc_cell_MOD_cellxc+0x115c>)\n-\tmov\tr2, r4\n-\tldr\tr0, [pc, #124]\t@ (173c <__gridxc_cell_MOD_cellxc+0x1160>)\n-\tadd\tr1, pc\n-\tadd\tr0, pc\n-\tbl\t0 <_gfortran_os_error_at>\n- R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr.w\tr3, [sl]\n-\tcmp\tr3, #1\n-\tbne.w\t1042 <__gridxc_cell_MOD_cellxc+0xa66>\n-\tmov.w\tr3, #532\t@ 0x214\n-\tstr.w\tr3, [sl]\n-\tb.n\t1042 <__gridxc_cell_MOD_cellxc+0xa66>\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0xfffffffd\n-\t.word\t0xffffffff\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n-\t.word\t0x000003ca\n- R_ARM_REL32\t.data\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n-\t.word\t0x00000384\n- R_ARM_REL32\t.data\n-\t.word\t0x00000302\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002ec\n- R_ARM_REL32\t.data\n-\t.word\t0x0000028c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000252\n- R_ARM_REL32\t.data\n-\t.word\t0x00000222\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000162\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n+\tb.n\t16ae <__gridxc_cell_MOD_cellxc+0x109a>\n+\tnop\n+\t...\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000c8\n- R_ARM_REL32\t.LC21\n-\t.word\t0x00000092\n+\t.word\t0x00000012\n R_ARM_REL32\t.LC20\n-\t.word\t0x00000086\n- R_ARM_REL32\t.LC15\n-\t.word\t0x00000088\n- R_ARM_REL32\t.LC17\n-\t.word\t0x0000007e\n- R_ARM_REL32\t.LC15\n-\t.word\t0x00000080\n- R_ARM_REL32\t.LC17\n-\t.word\t0x00000074\n- R_ARM_REL32\t.LC15\n-\t.word\t0x00000076\n- R_ARM_REL32\t.LC16\n-\tadd.w\tr3, r7, #984\t@ 0x3d8\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tadd.w\tr3, r7, #992\t@ 0x3e0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tvldr\ts15, [r6]\n-\tvmov.f64\td29, #112\t@ 0x3f800000 1.0\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tadd.w\tr4, r7, #1296\t@ 0x510\n-\tldr\tr2, [pc, #1004]\t@ (1b50 <__gridxc_cell_MOD_cellxc+0x1574>)\n+\tadd.w\tr3, r7, #968\t@ 0x3c8\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tvmov.f64\td0, #112\t@ 0x3f800000 1.0\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr4, r7, #1272\t@ 0x4f8\n+\tldr.w\tr5, [r7, #624]\t@ 0x270\n \tmov\tr1, r4\n-\tvcvt.f64.s32\td25, s15\n-\tvldr\ts15, [r6, #4]\n+\tvldr\ts6, [r2]\n+\tmov\tr0, r5\n+\tvldr\ts8, [r2, #4]\n+\tvldr\ts2, [r2, #8]\n+\tvcvt.f64.s32\td3, s6\n+\tvldr\td7, [r3, #8]\n+\tvcvt.f64.s32\td4, s8\n+\tvldr\td6, [r3]\n+\tvcvt.f64.s32\td1, s2\n+\tvldr\td5, [r3, #16]\n+\tvldr\td8, [r3, #24]\n+\tvdiv.f64\td2, d0, d3\n+\tldr\tr2, [pc, #928]\t@ (1b60 <__gridxc_cell_MOD_cellxc+0x154c>)\n+\tvdiv.f64\td3, d0, d4\n \tadd\tr2, pc\n-\tvldr\td23, [r3]\n+\tvdiv.f64\td4, d0, d1\n \tadds\tr2, #8\n-\tvldr\td22, [r3, #8]\n-\tvldr\td21, [r3, #16]\n-\tvldr\td20, [r3, #24]\n-\tvldr\td19, [r3, #32]\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvldr\td17, [r3, #48]\t@ 0x30\n-\tvldr\td16, [r3, #56]\t@ 0x38\n-\tvdiv.f64\td27, d29, d25\n-\tvldr\td24, [r3, #64]\t@ 0x40\n-\tldr\tr3, [r6, #8]\n-\tvcvt.f64.s32\td25, s15\n-\tvmov\ts15, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tvcvt.f64.s32\td28, s15\n-\tmov\tr0, r3\n-\tvdiv.f64\td26, d29, d25\n-\tvdiv.f64\td25, d29, d28\n-\tvmul.f64\td23, d23, d27\n-\tvmul.f64\td22, d22, d27\n-\tvmul.f64\td21, d21, d27\n-\tvstr\td23, [r3]\n-\tvmul.f64\td20, d20, d26\n-\tvmul.f64\td19, d19, d26\n-\tvmul.f64\td18, d18, d26\n-\tvstr\td22, [r3, #8]\n-\tvstr\td21, [r3, #16]\n-\tvmul.f64\td17, d17, d25\n-\tvmul.f64\td16, d16, d25\n-\tvmul.f64\td24, d24, d25\n-\tvstr\td20, [r3, #24]\n-\tvstr\td19, [r3, #32]\n-\tvstr\td18, [r3, #40]\t@ 0x28\n-\tvstr\td17, [r3, #48]\t@ 0x30\n-\tvstr\td16, [r3, #56]\t@ 0x38\n-\tvstr\td24, [r3, #64]\t@ 0x40\n+\tvmul.f64\td7, d7, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td8, d8, d3\n+\tvstr\td7, [r5, #8]\n+\tvldr\td7, [r3, #32]\n+\tvstr\td6, [r5]\n+\tvldr\td6, [r3, #40]\t@ 0x28\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td5, [r5, #16]\n+\tvldr\td5, [r3, #48]\t@ 0x30\n+\tvmul.f64\td6, d6, d3\n+\tvldr\td3, [r3, #56]\t@ 0x38\n+\tvstr\td8, [r5, #24]\n+\tvstr\td7, [r5, #32]\n+\tvmul.f64\td5, d5, d4\n+\tvldr\td7, [r3, #64]\t@ 0x40\n+\tvmul.f64\td3, d3, d4\n+\tvstr\td6, [r5, #40]\t@ 0x28\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td5, [r5, #48]\t@ 0x30\n+\tvstr\td3, [r5, #56]\t@ 0x38\n+\tvstr\td7, [r5, #64]\t@ 0x40\n \tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n-\tvldr\td17, [pc, #828]\t@ 1b40 <__gridxc_cell_MOD_cellxc+0x1564>\n-\tvldr\td24, [r4]\n+\tvldr\td5, [pc, #804]\t@ 1b50 <__gridxc_cell_MOD_cellxc+0x153c>\n+\tvldr\td0, [r4]\n+\tvmov.f64\td6, #232\t@ 0xbf400000 -0.750\n+\tldr.w\tr1, [r7, #792]\t@ 0x318\n \tmovs\tr2, #0\n-\tvldr\td23, [r4, #8]\n+\tvldr\td1, [r4, #8]\n \tmovs\tr3, #0\n-\tvldr\td22, [r4, #16]\n-\tvldr\td21, [r4, #24]\n-\tvmul.f64\td2, d24, d17\n-\tvldr\td20, [r4, #32]\n-\tvmul.f64\td1, d23, d17\n-\tvldr\td19, [r4, #40]\t@ 0x28\n-\tvmul.f64\td0, d22, d17\n-\tvldr\td25, [r4, #48]\t@ 0x30\n-\tvmul.f64\td8, d21, d17\n-\tvldr\td18, [r4, #56]\t@ 0x38\n-\tvmul.f64\td10, d20, d17\n-\tvldr\td26, [r4, #64]\t@ 0x40\n-\tvmul.f64\td11, d19, d17\n-\tldr.w\tr1, [r7, #756]\t@ 0x2f4\n-\tvmul.f64\td12, d25, d17\n-\tvmul.f64\td14, d18, d17\n-\tvldr\td16, [pc, #756]\t@ 1b48 <__gridxc_cell_MOD_cellxc+0x156c>\n-\tvmul.f64\td17, d26, d17\n-\tvmul.f64\td4, d24, d16\n-\tvmul.f64\td3, d23, d16\n-\tvmul.f64\td31, d22, d16\n-\tvmul.f64\td7, d21, d16\n-\tvneg.f64\td27, d17\n-\tvstr\td17, [r1, #64]\t@ 0x40\n-\tvmov.f64\td17, #232\t@ 0xbf400000 -0.750\n-\tvmul.f64\td30, d20, d16\n-\tvmul.f64\td29, d19, d16\n-\tvmul.f64\td5, d25, d16\n-\tvmul.f64\td6, d18, d16\n-\tvmul.f64\td24, d24, d17\n-\tvmul.f64\td23, d23, d17\n-\tvmul.f64\td22, d22, d17\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td20, d20, d17\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td16, d26, d16\n-\tvmul.f64\td25, d25, d17\n-\tvmul.f64\td18, d18, d17\n-\tvstr\td2, [r1]\n-\tvmul.f64\td17, d26, d17\n-\tvstr\td1, [r1, #8]\n-\tvneg.f64\td2, d2\n-\tvstr\td0, [r1, #16]\n-\tvneg.f64\td1, d1\n+\tvmul.f64\td8, d0, d5\n+\tvldr\td2, [r4, #16]\n+\tvldr\td3, [r4, #24]\n+\tvldr\td4, [r4, #32]\n+\tvldr\td9, [r4, #40]\t@ 0x28\n+\tvstr\td8, [r1]\n+\tvneg.f64\td8, d8\n+\tvldr\td10, [r4, #48]\t@ 0x30\n+\tvldr\td12, [r4, #56]\t@ 0x38\n+\tvldr\td14, [r4, #64]\t@ 0x40\n+\tvstr\td8, [r7, #624]\t@ 0x270\n+\tvmul.f64\td8, d1, d5\n+\tvldr\td7, [pc, #740]\t@ 1b58 <__gridxc_cell_MOD_cellxc+0x1544>\n+\tvstr\td8, [r1, #8]\n+\tvneg.f64\td8, d8\n+\tvstr\td8, [r7, #608]\t@ 0x260\n+\tvmul.f64\td8, d2, d5\n+\tvstr\td8, [r1, #16]\n+\tvneg.f64\td8, d8\n+\tvstr\td8, [r7, #600]\t@ 0x258\n+\tvmul.f64\td8, d3, d5\n \tvstr\td8, [r1, #24]\n-\tvneg.f64\td0, d0\n-\tvstr\td10, [r1, #32]\n \tvneg.f64\td8, d8\n-\tvstr\td11, [r1, #40]\t@ 0x28\n-\tvneg.f64\td10, d10\n-\tvstr\td12, [r1, #48]\t@ 0x30\n-\tvneg.f64\td11, d11\n-\tvstr\td14, [r1, #56]\t@ 0x38\n-\tvneg.f64\td12, d12\n-\tvstr\td4, [r1, #72]\t@ 0x48\n-\tvneg.f64\td14, d14\n-\tvstr\td3, [r1, #80]\t@ 0x50\n-\tvneg.f64\td4, d4\n-\tvstr\td24, [r1, #144]\t@ 0x90\n+\tvstr\td8, [r7, #592]\t@ 0x250\n+\tvmul.f64\td8, d4, d5\n+\tvstr\td8, [r1, #32]\n+\tvneg.f64\td8, d8\n+\tvstr\td8, [r7, #584]\t@ 0x248\n+\tvmul.f64\td8, d9, d5\n+\tvstr\td8, [r1, #40]\t@ 0x28\n+\tvneg.f64\td8, d8\n+\tvstr\td8, [r7, #552]\t@ 0x228\n+\tvmul.f64\td8, d10, d5\n+\tvstr\td8, [r1, #48]\t@ 0x30\n+\tvneg.f64\td8, d8\n+\tvstr\td8, [r7, #536]\t@ 0x218\n+\tvmul.f64\td8, d12, d5\n+\tvmul.f64\td5, d14, d5\n+\tvstr\td8, [r1, #56]\t@ 0x38\n+\tvneg.f64\td8, d8\n+\tvstr\td5, [r1, #64]\t@ 0x40\n+\tvneg.f64\td5, d5\n+\tvstr\td5, [r7, #528]\t@ 0x210\n+\tvmul.f64\td5, d0, d7\n+\tvmul.f64\td0, d0, d6\n+\tvstr\td5, [r1, #72]\t@ 0x48\n+\tvneg.f64\td5, d5\n+\tvstr\td0, [r1, #144]\t@ 0x90\n+\tvneg.f64\td0, d0\n+\tvstr\td5, [r7, #768]\t@ 0x300\n+\tvmul.f64\td5, d1, d7\n+\tvmul.f64\td1, d1, d6\n+\tvstr\td5, [r1, #80]\t@ 0x50\n+\tvneg.f64\td5, d5\n+\tvstr\td5, [r7, #744]\t@ 0x2e8\n+\tvmul.f64\td5, d2, d7\n+\tvstr\td1, [r1, #152]\t@ 0x98\n+\tvmul.f64\td2, d2, d6\n+\tvneg.f64\td1, d1\n+\tvstr\td0, [r1, #288]\t@ 0x120\n+\tvstr\td5, [r1, #88]\t@ 0x58\n+\tvneg.f64\td5, d5\n+\tvstr\td2, [r1, #160]\t@ 0xa0\n+\tvneg.f64\td2, d2\n+\tvstr\td1, [r1, #296]\t@ 0x128\n+\tvstr\td5, [r7, #736]\t@ 0x2e0\n+\tvmul.f64\td5, d3, d7\n+\tvmul.f64\td3, d3, d6\n+\tvstr\td2, [r1, #304]\t@ 0x130\n+\tvstr\td5, [r1, #96]\t@ 0x60\n+\tvneg.f64\td5, d5\n+\tvstr\td3, [r1, #168]\t@ 0xa8\n \tvneg.f64\td3, d3\n-\tvstr\td23, [r1, #152]\t@ 0x98\n-\tvneg.f64\td24, d24\n-\tvstr\td31, [r1, #88]\t@ 0x58\n-\tvneg.f64\td23, d23\n-\tvstr\td22, [r1, #160]\t@ 0xa0\n-\tvneg.f64\td31, d31\n-\tvstr\td7, [r1, #96]\t@ 0x60\n-\tvneg.f64\td22, d22\n-\tvstr\td21, [r1, #168]\t@ 0xa8\n-\tvneg.f64\td7, d7\n-\tvstr\td30, [r1, #104]\t@ 0x68\n-\tvneg.f64\td21, d21\n-\tvstr\td20, [r1, #176]\t@ 0xb0\n-\tvneg.f64\td30, d30\n-\tvstr\td29, [r1, #112]\t@ 0x70\n-\tvneg.f64\td20, d20\n+\tvstr\td5, [r7, #672]\t@ 0x2a0\n+\tvmul.f64\td5, d4, d7\n+\tvmul.f64\td4, d4, d6\n+\tvstr\td3, [r7, #784]\t@ 0x310\n+\tvldr\td2, [r7, #784]\t@ 0x310\n+\tvneg.f64\td3, d5\n+\tvstr\td5, [r1, #104]\t@ 0x68\n+\tvstr\td4, [r1, #176]\t@ 0xb0\n+\tvmul.f64\td5, d9, d7\n+\tvneg.f64\td4, d4\n+\tvstr\td2, [r1, #312]\t@ 0x138\n+\tvstr\td3, [r7, #656]\t@ 0x290\n+\tvmul.f64\td3, d10, d6\n+\tvstr\td5, [r1, #112]\t@ 0x70\n+\tvstr\td4, [r7, #776]\t@ 0x308\n+\tvmul.f64\td4, d9, d6\n+\tvneg.f64\td9, d5\n+\tvmul.f64\td5, d10, d7\n+\tvldr\td2, [r7, #776]\t@ 0x308\n+\tvstr\td4, [r1, #184]\t@ 0xb8\n+\tvneg.f64\td4, d4\n+\tvneg.f64\td10, d5\n \tvstr\td5, [r1, #120]\t@ 0x78\n-\tvneg.f64\td29, d29\n-\tvstr\td6, [r1, #128]\t@ 0x80\n+\tvmul.f64\td5, d12, d7\n+\tvmul.f64\td7, d14, d7\n+\tvmul.f64\td12, d12, d6\n+\tvmul.f64\td14, d14, d6\n+\tvldr\td6, [r7, #768]\t@ 0x300\n+\tvstr\td2, [r1, #320]\t@ 0x140\n+\tvstr\td7, [r1, #136]\t@ 0x88\n+\tvneg.f64\td7, d7\n+\tvstr\td6, [r1, #360]\t@ 0x168\n+\tvldr\td6, [r7, #744]\t@ 0x2e8\n+\tvstr\td5, [r1, #128]\t@ 0x80\n \tvneg.f64\td5, d5\n-\tvstr\td16, [r1, #136]\t@ 0x88\n-\tvneg.f64\td6, d6\n-\tvstr\td19, [r1, #184]\t@ 0xb8\n-\tvneg.f64\td19, d19\n-\tvstr\td18, [r1, #200]\t@ 0xc8\n-\tvneg.f64\td16, d16\n-\tvstr\td17, [r1, #208]\t@ 0xd0\n-\tvneg.f64\td18, d18\n-\tvneg.f64\td17, d17\n+\tvstr\td6, [r1, #368]\t@ 0x170\n+\tvldr\td6, [r7, #736]\t@ 0x2e0\n+\tvstr\td6, [r1, #376]\t@ 0x178\n+\tvldr\td6, [r7, #672]\t@ 0x2a0\n+\tvstr\td6, [r1, #384]\t@ 0x180\n+\tvldr\td6, [r7, #656]\t@ 0x290\n+\tvstr\td6, [r1, #392]\t@ 0x188\n+\tvstr\td7, [r1, #424]\t@ 0x1a8\n+\tvldr\td7, [r7, #624]\t@ 0x270\n+\tvstr\td3, [r1, #192]\t@ 0xc0\n+\tvneg.f64\td3, d3\n+\tvstr\td12, [r1, #200]\t@ 0xc8\n+\tvneg.f64\td12, d12\n+\tvstr\td7, [r1, #432]\t@ 0x1b0\n+\tvldr\td7, [r7, #608]\t@ 0x260\n+\tvstr\td14, [r1, #208]\t@ 0xd0\n+\tvneg.f64\td14, d14\n+\tvstr\td5, [r1, #416]\t@ 0x1a0\n+\tvstr\td7, [r1, #440]\t@ 0x1b8\n+\tvldr\td7, [r7, #600]\t@ 0x258\n \tstrd\tr2, r3, [r1, #216]\t@ 0xd8\n-\tvstr\td19, [r1, #328]\t@ 0x148\n-\tvneg.f64\td19, d25\n \tstrd\tr2, r3, [r1, #224]\t@ 0xe0\n+\tvstr\td7, [r1, #448]\t@ 0x1c0\n+\tvldr\td7, [r7, #592]\t@ 0x250\n \tstrd\tr2, r3, [r1, #232]\t@ 0xe8\n \tstrd\tr2, r3, [r1, #240]\t@ 0xf0\n+\tvstr\td7, [r1, #456]\t@ 0x1c8\n+\tvldr\td7, [r7, #584]\t@ 0x248\n \tstrd\tr2, r3, [r1, #248]\t@ 0xf8\n \tstrd\tr2, r3, [r1, #256]\t@ 0x100\n+\tvstr\td7, [r1, #464]\t@ 0x1d0\n+\tvldr\td7, [r7, #552]\t@ 0x228\n \tstrd\tr2, r3, [r1, #264]\t@ 0x108\n \tstrd\tr2, r3, [r1, #272]\t@ 0x110\n-\tvstr\td24, [r1, #288]\t@ 0x120\n-\tvstr\td23, [r1, #296]\t@ 0x128\n-\tvstr\td22, [r1, #304]\t@ 0x130\n-\tvstr\td21, [r1, #312]\t@ 0x138\n-\tvstr\td20, [r1, #320]\t@ 0x140\n-\tvstr\td4, [r1, #360]\t@ 0x168\n-\tvstr\td25, [r1, #192]\t@ 0xc0\n-\tvstr\td3, [r1, #368]\t@ 0x170\n-\tvstr\td19, [r1, #336]\t@ 0x150\n-\tvstr\td31, [r1, #376]\t@ 0x178\n-\tvstr\td7, [r1, #384]\t@ 0x180\n-\tvstr\td30, [r1, #392]\t@ 0x188\n-\tvstr\td18, [r1, #344]\t@ 0x158\n-\tvstr\td29, [r1, #400]\t@ 0x190\n-\tvstr\td17, [r1, #352]\t@ 0x160\n-\tvstr\td5, [r1, #408]\t@ 0x198\n-\tvstr\td6, [r1, #416]\t@ 0x1a0\n-\tvstr\td16, [r1, #424]\t@ 0x1a8\n-\tvstr\td2, [r1, #432]\t@ 0x1b0\n-\tvstr\td1, [r1, #440]\t@ 0x1b8\n \tstrd\tr2, r3, [r1, #280]\t@ 0x118\n-\tvstr\td0, [r1, #448]\t@ 0x1c0\n-\tvstr\td8, [r1, #456]\t@ 0x1c8\n-\tvstr\td10, [r1, #464]\t@ 0x1d0\n-\tvstr\td11, [r1, #472]\t@ 0x1d8\n-\tvstr\td12, [r1, #480]\t@ 0x1e0\n-\tvstr\td14, [r1, #488]\t@ 0x1e8\n-\tvstr\td27, [r1, #496]\t@ 0x1f0\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tvstr\td9, [r1, #400]\t@ 0x190\n+\tvstr\td10, [r1, #408]\t@ 0x198\n+\tvstr\td4, [r1, #328]\t@ 0x148\n+\tvstr\td3, [r1, #336]\t@ 0x150\n+\tvstr\td12, [r1, #344]\t@ 0x158\n+\tvstr\td14, [r1, #352]\t@ 0x160\n+\tvstr\td7, [r1, #472]\t@ 0x1d8\n+\tvldr\td7, [r7, #536]\t@ 0x218\n+\tvldr\td5, [r7, #528]\t@ 0x210\n+\tvstr\td8, [r1, #488]\t@ 0x1e8\n+\tvstr\td7, [r1, #480]\t@ 0x1e0\n+\tvstr\td5, [r1, #496]\t@ 0x1f0\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n \tmovs\tr4, #0\n \tmovs\tr5, #0\n-\tldr.w\tr0, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr0, [r7, #456]\t@ 0x1c8\n \tmovs\tr2, #72\t@ 0x48\n \tmovs\tr1, #0\n \tstrd\tr4, r5, [r3]\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n \tstrd\tr4, r5, [r3]\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tldr.w\tr3, [r7, #216]\t@ 0xd8\n \tstrd\tr4, r5, [r3]\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n \tstrd\tr4, r5, [r3]\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, #0\n-\tble.n\t1aba <__gridxc_cell_MOD_cellxc+0x14de>\n-\tldrd\tr2, r3, [r7, #592]\t@ 0x250\n+\tble.n\t1b76 <__gridxc_cell_MOD_cellxc+0x1562>\n+\tldr.w\tr2, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #564]\t@ 0x234\n \torrs\tr3, r2\n-\tbmi.n\t1aba <__gridxc_cell_MOD_cellxc+0x14de>\n+\tbmi.n\t1b76 <__gridxc_cell_MOD_cellxc+0x1562>\n \tadds\tr3, r2, #1\n \tmovs\tr6, #0\n-\tmov\tr2, r6\n+\tmov\tr8, r6\n \tlsls\tr3, r3, #3\n \tmov\tfp, r3\n-\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n \tlsls\tr5, r3, #3\n-\tmov\tr0, r6\n-\tmov.w\tr8, #0\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tmov\tr2, r6\n+\tmov.w\tr9, #0\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tmovs\tr4, #0\n-\tmov\tr9, r0\n \tmov\tsl, r2\n-\tadd.w\tr3, r3, r0, lsl #3\n+\tadd.w\tr3, r3, r2, lsl #3\n \tmovs\tr1, #0\n \tmov\tr0, r3\n \tmov\tr2, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n+\tldr.w\tr1, [r7, #616]\t@ 0x268\n \tmov\tr3, r0\n \tcmp\tr1, r4\n \tadd\tr3, r5\n \tadd.w\tr4, r4, #1\n-\tbne.n\t1a76 <__gridxc_cell_MOD_cellxc+0x149a>\n-\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n-\tmov\tr0, r9\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tbne.n\t1b1a <__gridxc_cell_MOD_cellxc+0x1506>\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n \tmov\tr2, sl\n-\tadd\tr0, r3\n-\tadd.w\tr3, r8, #1\n-\tcmp\tr1, r8\n-\tbeq.n\t1aaa <__gridxc_cell_MOD_cellxc+0x14ce>\n-\tmov\tr8, r3\n-\tb.n\t1a68 <__gridxc_cell_MOD_cellxc+0x148c>\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n-\tadds\tr2, #1\n+\tldr.w\tr1, [r7, #580]\t@ 0x244\n+\tadd\tr2, r3\n+\tadd.w\tr3, r9, #1\n+\tcmp\tr1, r9\n+\tbeq.n\t1b64 <__gridxc_cell_MOD_cellxc+0x1550>\n+\tmov\tr9, r3\n+\tb.n\t1b0e <__gridxc_cell_MOD_cellxc+0x14fa>\n+\tnop.w\n+\t.word\t0x11111111\n+\t.word\t0xbf911111\n+\t.word\t0x33333333\n+\t.word\t0x3fc33333\n+\t.word\t0x0000039a\n+ R_ARM_REL32\t.rodata\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tadd.w\tr8, r8, #1\n \tadd\tr6, r3\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tcmp\tr2, r3\n-\tbne.n\t1a62 <__gridxc_cell_MOD_cellxc+0x1486>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tcmp\tr3, r8\n+\tbne.n\t1b08 <__gridxc_cell_MOD_cellxc+0x14f4>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.n\t1b64 <__gridxc_cell_MOD_cellxc+0x1588>\n+\tbeq.n\t1c04 <__gridxc_cell_MOD_cellxc+0x15f0>\n \tldr.w\tr3, [r7, #572]\t@ 0x23c\n-\tcmp\tr3, #0\n-\tbeq.n\t1b64 <__gridxc_cell_MOD_cellxc+0x1588>\n-\tldr.w\tr2, [r7, #580]\t@ 0x244\n-\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr1, [r7, #576]\t@ 0x240\n+\tcbz\tr3, 1c04 <__gridxc_cell_MOD_cellxc+0x15f0>\n+\tldr.w\tr2, [r7, #548]\t@ 0x224\n+\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n \torrs\tr3, r2\n \torrs\tr3, r1\n-\tbmi.n\t1b64 <__gridxc_cell_MOD_cellxc+0x1588>\n+\tbmi.n\t1c04 <__gridxc_cell_MOD_cellxc+0x15f0>\n \tadds\tr3, r2, #1\n-\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr2, [r7, #408]\t@ 0x198\n \tmovs\tr6, #0\n \tlsls\tr3, r3, #3\n \tmov\tfp, r3\n-\tldr.w\tr3, [r7, #620]\t@ 0x26c\n-\tadds\tr2, r3, r2\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tadd.w\tr8, r3, r2\n+\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n \tlsls\tr5, r3, #3\n-\tmov\tr0, r2\n-\tmov.w\tr8, #0\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tmov\tr2, r8\n+\tmov.w\tr9, #0\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tmovs\tr4, #0\n-\tmov\tr9, r2\n-\tmov\tsl, r0\n-\tadd.w\tr3, r3, r0, lsl #3\n+\tmov\tsl, r2\n+\tadd.w\tr3, r3, r2, lsl #3\n \tmovs\tr1, #0\n \tmov\tr0, r3\n \tmov\tr2, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n \tmov\tr3, r0\n \tcmp\tr1, r4\n \tadd\tr3, r5\n \tadd.w\tr4, r4, #1\n-\tbne.n\t1b08 <__gridxc_cell_MOD_cellxc+0x152c>\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tmov\tr0, sl\n-\tldr.w\tr1, [r7, #576]\t@ 0x240\n-\tmov\tr2, r9\n-\tadd\tr0, r3\n-\tadd.w\tr3, r8, #1\n-\tcmp\tr8, r1\n-\tbeq.n\t1b54 <__gridxc_cell_MOD_cellxc+0x1578>\n-\tmov\tr8, r3\n-\tb.n\t1afa <__gridxc_cell_MOD_cellxc+0x151e>\n-\tnop.w\n-\t.word\t0x11111111\n-\t.word\t0xbf911111\n-\t.word\t0x33333333\n-\t.word\t0x3fc33333\n-\t.word\t0x000003e0\n- R_ARM_REL32\t.rodata\n-\tldr.w\tr3, [r7, #620]\t@ 0x26c\n-\tadds\tr6, #1\n+\tbne.n\t1bc2 <__gridxc_cell_MOD_cellxc+0x15ae>\n+\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tmov\tr2, sl\n+\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n \tadd\tr2, r3\n+\tadd.w\tr3, r9, #1\n+\tcmp\tr1, r9\n+\tbeq.n\t1bf4 <__gridxc_cell_MOD_cellxc+0x15e0>\n+\tmov\tr9, r3\n+\tb.n\t1bb6 <__gridxc_cell_MOD_cellxc+0x15a2>\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tadds\tr6, #1\n+\tadd\tr8, r3\n \tldr.w\tr3, [r7, #572]\t@ 0x23c\n \tcmp\tr3, r6\n-\tbne.n\t1af4 <__gridxc_cell_MOD_cellxc+0x1518>\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n-\tcbz\tr3, 1bca <__gridxc_cell_MOD_cellxc+0x15ee>\n-\tldr.w\tr2, [r7, #140]\t@ 0x8c\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n-\tldr.w\tr1, [r7, #272]\t@ 0x110\n+\tbne.n\t1bb0 <__gridxc_cell_MOD_cellxc+0x159c>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tcbz\tr3, 1c66 <__gridxc_cell_MOD_cellxc+0x1652>\n+\tldr.w\tr2, [r7, #136]\t@ 0x88\n+\tldr.w\tr3, [r7, #264]\t@ 0x108\n+\tldr.w\tr1, [r7, #260]\t@ 0x104\n \torrs\tr3, r2\n \torrs\tr3, r1\n-\tbmi.n\t1bca <__gridxc_cell_MOD_cellxc+0x15ee>\n-\tldr.w\tr3, [r7, #136]\t@ 0x88\n-\tadds\tr2, #1\n+\tbmi.n\t1c66 <__gridxc_cell_MOD_cellxc+0x1652>\n+\tadds\tr3, r2, #1\n \tmovs\tr5, #0\n-\tlsls\tr2, r2, #3\n \tmov\tr6, r5\n-\tlsls\tr3, r3, #3\n-\tmov\tr8, r3\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tmov.w\tr9, r3, lsl #3\n+\tldr.w\tr3, [r7, #132]\t@ 0x84\n+\tmov.w\tr8, r3, lsl #3\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n \tmovs\tr4, #0\n \tadd.w\tr3, r3, r5, lsl #3\n-\tmov\tr0, r3\n \tmovs\tr1, #0\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tmov\tr0, r3\n+\tmov\tr2, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n+\tldr.w\tr1, [r7, #264]\t@ 0x108\n \tmov\tr3, r0\n+\tcmp\tr1, r4\n \tadd\tr3, r8\n-\tcmp\tr2, r4\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n \tadd.w\tr4, r4, #1\n-\tbne.n\t1b96 <__gridxc_cell_MOD_cellxc+0x15ba>\n-\tldr.w\tr3, [r7, #132]\t@ 0x84\n-\tldr.w\tr1, [r7, #272]\t@ 0x110\n+\tbne.n\t1c38 <__gridxc_cell_MOD_cellxc+0x1624>\n+\tldr.w\tr3, [r7, #128]\t@ 0x80\n+\tldr.w\tr2, [r7, #260]\t@ 0x104\n \tadd\tr5, r3\n \tadds\tr3, r6, #1\n-\tcmp\tr1, r6\n-\tbeq.n\t1bca <__gridxc_cell_MOD_cellxc+0x15ee>\n+\tcmp\tr2, r6\n+\tbeq.n\t1c66 <__gridxc_cell_MOD_cellxc+0x1652>\n \tmov\tr6, r3\n-\tb.n\t1b8c <__gridxc_cell_MOD_cellxc+0x15b0>\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tb.n\t1c2e <__gridxc_cell_MOD_cellxc+0x161a>\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n \tcmp\tr3, #0\n-\tbeq.n\t1c96 <__gridxc_cell_MOD_cellxc+0x16ba>\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n+\tbeq.n\t1d2c <__gridxc_cell_MOD_cellxc+0x1718>\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \tcmp\tr3, #0\n-\tble.n\t1c96 <__gridxc_cell_MOD_cellxc+0x16ba>\n-\tldr.w\tr2, [r7, #152]\t@ 0x98\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr1, [r7, #284]\t@ 0x11c\n+\tble.n\t1d2c <__gridxc_cell_MOD_cellxc+0x1718>\n+\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr1, [r7, #272]\t@ 0x110\n \torrs\tr3, r2\n \torrs\tr3, r1\n-\tbmi.n\t1c96 <__gridxc_cell_MOD_cellxc+0x16ba>\n+\tbmi.n\t1d2c <__gridxc_cell_MOD_cellxc+0x1718>\n \tadds\tr3, r2, #1\n-\tldr.w\tr2, [r7, #144]\t@ 0x90\n+\tldr.w\tr2, [r7, #140]\t@ 0x8c\n \tlsls\tr5, r3, #3\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n-\tlsls\tr6, r2, #3\n-\tmovs\tr2, #0\n-\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tmovs\tr4, #3\n-\tadd.w\tr8, r3, r1\n-\tmovs\tr0, #0\n-\tmov\tr1, r4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmov\tr3, r5\n-\tmov\tr4, r8\n-\tmov\tr5, r0\n-\tmov\tip, r1\n-\tmov\tr0, r8\n-\tmov\tr8, r3\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tldr.w\tr3, [r7, #412]\t@ 0x19c\n+\tadd.w\tr8, r3, r2\n+\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tlsls\tr6, r3, #3\n+\tmovs\tr3, #0\n+\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n+\tadd.w\tr4, r8, r2\n+\tmovs\tr2, #3\n+\tmovs\tr1, #0\n+\tstr.w\tr8, [r7, #784]\t@ 0x310\n+\tmov\tr0, r4\n+\tmov\tr8, r5\n+\tmov\tr5, r1\n+\tldr.w\tr1, [r7, #576]\t@ 0x240\n \tmov.w\tr9, #0\n-\tstr.w\tr4, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr4, [r7, #768]\t@ 0x300\n \tmov\tfp, r0\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadd.w\tsl, r3, r4, lsl #3\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tsl, r1, r4, lsl #3\n \tmov\tr4, r9\n-\tmov\tr9, ip\n+\tmov\tr9, r2\n \tmov\tr0, sl\n \tmov\tr2, r8\n \tmovs\tr1, #0\n \tadd\tsl, r6\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n \tcmp\tr3, r4\n \tadd.w\tr4, r4, #1\n-\tbne.n\t1c3a <__gridxc_cell_MOD_cellxc+0x165e>\n-\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tbne.n\t1cd0 <__gridxc_cell_MOD_cellxc+0x16bc>\n+\tldr.w\tr1, [r7, #144]\t@ 0x90\n \tmov\tr0, fp\n-\tldr.w\tr4, [r7, #740]\t@ 0x2e4\n-\tmov\tip, r9\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadds\tr1, r5, #1\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tcmp\tr3, r5\n-\tbeq.n\t1c72 <__gridxc_cell_MOD_cellxc+0x1696>\n-\tmov\tr5, r1\n-\tb.n\t1c20 <__gridxc_cell_MOD_cellxc+0x1644>\n-\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tmov\tr4, ip\n+\tldr.w\tr4, [r7, #768]\t@ 0x300\n+\tmov\tr2, r9\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tip, r5, #1\n+\tadd\tr4, r1\n+\tldr.w\tr1, [r7, #272]\t@ 0x110\n+\tcmp\tr1, r5\n+\tbeq.n\t1d0a <__gridxc_cell_MOD_cellxc+0x16f6>\n+\tmov\tr5, ip\n+\tb.n\t1cb6 <__gridxc_cell_MOD_cellxc+0x16a2>\n+\tldr.w\tr1, [r7, #416]\t@ 0x1a0\n+\tmov\tr4, r0\n \tmov\tr5, r8\n-\tmov\tr8, r0\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tadd\tr8, r1\n-\tsubs\tr4, #1\n-\tbne.n\t1c0c <__gridxc_cell_MOD_cellxc+0x1630>\n-\tldr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tadds\tr2, #1\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #280]\t@ 0x118\n-\tcmp\tr1, r2\n-\tbne.n\t1c02 <__gridxc_cell_MOD_cellxc+0x1626>\n-\tldr.w\tr3, [r7, #540]\t@ 0x21c\n+\tsubs\tr2, #1\n+\tldr.w\tr8, [r7, #784]\t@ 0x310\n+\tadd\tr4, r1\n+\tbne.n\t1caa <__gridxc_cell_MOD_cellxc+0x1696>\n+\tldr.w\tr2, [r7, #412]\t@ 0x19c\n+\tadds\tr3, #1\n+\tadd\tr8, r2\n+\tldr.w\tr2, [r7, #268]\t@ 0x10c\n+\tcmp\tr2, r3\n+\tbne.n\t1ca0 <__gridxc_cell_MOD_cellxc+0x168c>\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n \tcmp\tr3, #0\n-\tbne.w\t3856 <__gridxc_cell_MOD_cellxc+0x327a>\n-\tadd.w\tr3, r7, #976\t@ 0x3d0\n-\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tbne.w\t3976 <__gridxc_cell_MOD_cellxc+0x3362>\n+\tadd.w\tr3, r7, #960\t@ 0x3c0\n+\tstr\tr3, [r7, #88]\t@ 0x58\n+\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n \tcmp\tr3, #0\n-\tble.w\t366c <__gridxc_cell_MOD_cellxc+0x3090>\n-\tldr\tr3, [pc, #732]\t@ (1f90 <__gridxc_cell_MOD_cellxc+0x19b4>)\n-\tmov.w\tip, #0\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n+\tble.w\t3764 <__gridxc_cell_MOD_cellxc+0x3150>\n+\tldr\tr3, [pc, #736]\t@ (2028 <__gridxc_cell_MOD_cellxc+0x1a14>)\n+\tmov.w\tr8, #0\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tmov\tr9, r8\n \tadd\tr3, pc\n-\tstrd\tip, ip, [r7, #104]\t@ 0x68\n-\tstr\tr3, [r7, #28]\n+\tstrd\tr8, r8, [r7, #104]\t@ 0x68\n+\tstr\tr3, [r7, #24]\n \taddw\tr3, r3, #1140\t@ 0x474\n \tlsls\tr2, r2, #3\n-\tstr.w\tip, [r7, #100]\t@ 0x64\n+\tstr.w\tr8, [r7, #100]\t@ 0x64\n \tstr\tr2, [r7, #92]\t@ 0x5c\n-\tstr.w\tip, [r7, #204]\t@ 0xcc\n-\tstr.w\tip, [r7, #292]\t@ 0x124\n-\tstr\tr3, [r7, #24]\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr8, [r7, #204]\t@ 0xcc\n+\tstr\tr3, [r7, #20]\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n \tcmp\tr3, #0\n-\tble.w\t33fe <__gridxc_cell_MOD_cellxc+0x2e22>\n-\tldr\tr5, [pc, #684]\t@ (1f94 <__gridxc_cell_MOD_cellxc+0x19b8>)\n+\tble.w\t34dc <__gridxc_cell_MOD_cellxc+0x2ec8>\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #564]\t@ 0x234\n-\tadd\tr5, pc\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n \tcmp\tr3, #0\n-\tble.w\t23ec <__gridxc_cell_MOD_cellxc+0x1e10>\n-\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n-\tmovs\tr4, #0\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tmov\tsl, r4\n+\tble.w\t2496 <__gridxc_cell_MOD_cellxc+0x1e82>\n+\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n+\tmovs\tr6, #0\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n \tldr\tr3, [r7, #100]\t@ 0x64\n-\tmov\tr9, ip\n-\tldr.w\tr8, [r7, #292]\t@ 0x124\n-\tldr.w\tfp, [r7, #224]\t@ 0xe0\n+\tldr.w\tsl, [r7, #620]\t@ 0x26c\n+\tldr.w\tfp, [r7, #212]\t@ 0xd4\n \tmla\tr3, r2, r1, r3\n-\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n \tadd.w\tr3, r1, r3, lsl #3\n \tstr\tr3, [r7, #96]\t@ 0x60\n-\tldr.w\tr3, [r7, #136]\t@ 0x88\n-\tmla\tr3, r2, r3, ip\n+\tldr.w\tr3, [r7, #132]\t@ 0x84\n+\tmla\tr3, r2, r3, r8\n \tlsls\tr3, r3, #3\n \tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #820\t@ 0x334\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tadd.w\tr3, r7, #824\t@ 0x338\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tadd.w\tr3, r7, #828\t@ 0x33c\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr0, [r7, #564]\t@ 0x234\n-\tldr.w\tr1, [r5, #144]\t@ 0x90\n+\tadd.w\tr3, r7, #804\t@ 0x324\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tadd.w\tr3, r7, #808\t@ 0x328\n+\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr3, r7, #812\t@ 0x32c\n+\tstr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tldr\tr4, [pc, #596]\t@ (202c <__gridxc_cell_MOD_cellxc+0x1a18>)\n \tldr.w\tr3, [r2, #512]\t@ 0x200\n-\tldr.w\tlr, [r2, #504]\t@ 0x1f8\n-\tadd.w\tip, r0, r3\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tadd.w\tr0, lr, sl\n-\tstr.w\tip, [r3]\n+\tadd\tr4, pc\n+\tldr.w\tip, [r2, #504]\t@ 0x1f8\n+\tadd.w\tlr, r1, r3\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr0, ip, r6\n+\tldr.w\tr1, [r4, #144]\t@ 0x90\n+\tstr.w\tlr, [r3]\n \tldr.w\tr3, [r2, #520]\t@ 0x208\n-\tadd.w\tr6, r8, r3\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n-\tstr\tr6, [r3, #0]\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tadd.w\tr5, r9, r3\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tstr\tr5, [r3, #0]\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tstr\tr0, [r3, #0]\n \tcmp\tr1, #0\n-\tbeq.n\t1e24 <__gridxc_cell_MOD_cellxc+0x1848>\n-\tldr.w\tr2, [r5, #168]\t@ 0xa8\n-\tldr.w\tr3, [r5, #148]\t@ 0x94\n+\tbeq.n\t1ebc <__gridxc_cell_MOD_cellxc+0x18a8>\n+\tldr.w\tr2, [r4, #168]\t@ 0xa8\n+\tldr.w\tr3, [r4, #148]\t@ 0x94\n \tmla\tr3, r2, r0, r3\n-\tldr.w\tr2, [r5, #180]\t@ 0xb4\n-\tldr.w\tr0, [r7, #764]\t@ 0x2fc\n-\tcmp\tr0, #0\n-\tmla\tr3, r2, ip, r3\n-\tldr.w\tr2, [r5, #192]\t@ 0xc0\n-\tmla\tr3, r2, r6, r3\n-\tldrd\tr4, r2, [r5, #204]\t@ 0xcc\n-\tble.n\t1dd8 <__gridxc_cell_MOD_cellxc+0x17fc>\n-\tmla\tr3, r4, r2, r3\n-\tldr.w\tr2, [r5, #164]\t@ 0xa4\n-\tstr.w\tlr, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n-\tldr.w\tlr, [r7, #764]\t@ 0x2fc\n-\tmul.w\tr4, r2, r4\n-\tmla\tr3, r2, r3, r1\n+\tldr.w\tr2, [r4, #180]\t@ 0xb4\n+\tldr.w\tr0, [r4, #204]\t@ 0xcc\n+\tmla\tr2, r2, lr, r3\n+\tldr.w\tr3, [r4, #192]\t@ 0xc0\n+\tmla\tr2, r3, r5, r2\n+\tldr.w\tr3, [r4, #208]\t@ 0xd0\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tcmp\tr3, #0\n+\tble.n\t1e72 <__gridxc_cell_MOD_cellxc+0x185e>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tsl, [r7, #784]\t@ 0x310\n+\tldr.w\tsl, [r7, #796]\t@ 0x31c\n+\tmla\tr2, r0, r3, r2\n+\tldr.w\tr3, [r4, #164]\t@ 0xa4\n+\tldr.w\tr4, [r7, #724]\t@ 0x2d4\n+\tmul.w\tr0, r3, r0\n+\tmla\tr3, r3, r2, r1\n \tmovs\tr2, #0\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tadd\tr3, r4\n-\tcmp\tlr, r2\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t1dc4 <__gridxc_cell_MOD_cellxc+0x17e8>\n-\tldr.w\tlr, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n+\tadd\tr3, r0\n+\tcmp\tsl, r2\n+\tvstmia\tr4!, {d7}\n+\tbne.n\t1e5e <__gridxc_cell_MOD_cellxc+0x184a>\n+\tldr.w\tsl, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n \tldr\tr2, [r3, #0]\n \tcmp\tr2, #0\n-\tble.n\t1e86 <__gridxc_cell_MOD_cellxc+0x18aa>\n-\tvmov.i64\td8, #0x0000000000000000\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tble.n\t1f1e <__gridxc_cell_MOD_cellxc+0x190a>\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n \tmovs\tr3, #0\n-\tvldmia\tr0!, {d16}\n+\tvldr\td10, [pc, #404]\t@ 2018 <__gridxc_cell_MOD_cellxc+0x1a04>\n+\tvldmia\tr0!, {d7}\n \tmov\tr1, r3\n \tadds\tr3, #1\n \tcmp\tr2, r3\n-\tvadd.f64\td8, d8, d16\n-\tbne.n\t1dec <__gridxc_cell_MOD_cellxc+0x1810>\n-\tvldr\td16, [pc, #392]\t@ 1f88 <__gridxc_cell_MOD_cellxc+0x19ac>\n-\tvcmpe.f64\td8, d16\n+\tvadd.f64\td10, d10, d7\n+\tbne.n\t1e86 <__gridxc_cell_MOD_cellxc+0x1872>\n+\tvldr\td7, [pc, #392]\t@ 2020 <__gridxc_cell_MOD_cellxc+0x1a0c>\n+\tvcmpe.f64\td10, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.w\t1f9c <__gridxc_cell_MOD_cellxc+0x19c0>\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tadd.w\tr3, sl, #1\n-\tcmp\tsl, r2\n-\tbeq.w\t23ea <__gridxc_cell_MOD_cellxc+0x1e0e>\n+\tbpl.w\t2034 <__gridxc_cell_MOD_cellxc+0x1a20>\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadds\tr3, r6, #1\n+\tcmp\tr6, r2\n+\tbeq.w\t2492 <__gridxc_cell_MOD_cellxc+0x1e7e>\n \tldr\tr2, [r7, #96]\t@ 0x60\n-\tmov\tsl, r3\n+\tmov\tr6, r3\n \tadds\tr2, #8\n \tstr\tr2, [r7, #96]\t@ 0x60\n-\tb.n\t1d42 <__gridxc_cell_MOD_cellxc+0x1766>\n+\tb.n\t1dcc <__gridxc_cell_MOD_cellxc+0x17b8>\n \tldr.w\tr3, [r2, #540]\t@ 0x21c\n \tmov\tr0, r2\n-\tldr.w\tr4, [r7, #564]\t@ 0x234\n+\tldr.w\tr4, [r7, #552]\t@ 0x228\n \tldr.w\tr2, [r2, #532]\t@ 0x214\n-\tadd\tr3, sl\n+\tadd\tr3, r6\n \tmla\tr2, r2, r4, r3\n \tldr.w\tr3, [r0, #536]\t@ 0x218\n \tldr.w\tr4, [r0, #544]\t@ 0x220\n-\tmla\tr3, r3, r8, r2\n+\tmla\tr3, r3, r9, r2\n \tmov\tr2, r0\n-\tldr.w\tr0, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr0, [r7, #796]\t@ 0x31c\n \tcmp\tr0, #0\n-\tble.n\t1dd8 <__gridxc_cell_MOD_cellxc+0x17fc>\n+\tble.n\t1e72 <__gridxc_cell_MOD_cellxc+0x185e>\n \tldr.w\tr2, [r2, #528]\t@ 0x210\n \tadd\tr3, r4\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n \tlsls\tr4, r4, #3\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n \tadd.w\tr3, r2, r3, lsl #3\n \tmov\tr2, r1\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n \tadd\tr3, r4\n \tcmp\tr1, r2\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t1e64 <__gridxc_cell_MOD_cellxc+0x1888>\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t1efc <__gridxc_cell_MOD_cellxc+0x18e8>\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tldr\tr2, [r3, #0]\n \tcmp\tr2, #0\n-\tbgt.n\t1de2 <__gridxc_cell_MOD_cellxc+0x1806>\n-\tldr.w\tr3, [r7, #656]\t@ 0x290\n-\tmov\tr4, sl\n-\tstr.w\tip, [r7, #752]\t@ 0x2f0\n-\tmov\tfp, r1\n-\tstr.w\tr6, [r7, #740]\t@ 0x2e4\n-\tmov\tip, r9\n-\tadds\tr6, r4, #1\n-\tcmp\tsl, r3\n-\tstr.w\tr1, [r7, #736]\t@ 0x2e0\n-\tbeq.w\t23ec <__gridxc_cell_MOD_cellxc+0x1e10>\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tldr\tr3, [pc, #236]\t@ (1f98 <__gridxc_cell_MOD_cellxc+0x19bc>)\n-\tldr.w\tr0, [r2, #540]\t@ 0x21c\n+\tbgt.n\t1e7c <__gridxc_cell_MOD_cellxc+0x1868>\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tmov\tfp, r5\n+\tstr.w\tsl, [r7, #620]\t@ 0x26c\n+\tadds\tr5, r6, #1\n+\tmov\tsl, lr\n+\tcmp\tr6, r3\n+\tmov\tlr, r1\n+\tbeq.w\t2496 <__gridxc_cell_MOD_cellxc+0x1e82>\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tadd.w\tr6, ip, r5\n+\tldr\tr3, [pc, #240]\t@ (2030 <__gridxc_cell_MOD_cellxc+0x1a1c>)\n+\tldr.w\tr1, [r2, #540]\t@ 0x21c\n \tadd\tr3, pc\n-\tstr.w\tr0, [r7, #668]\t@ 0x29c\n-\tldr.w\tr0, [r2, #544]\t@ 0x220\n-\tstr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr0, [r2, #532]\t@ 0x214\n-\tstr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr0, [r2, #536]\t@ 0x218\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr1, [r2, #544]\t@ 0x220\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r2, #532]\t@ 0x214\n+\tstr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r2, #536]\t@ 0x218\n \tldr.w\tr2, [r2, #528]\t@ 0x210\n-\tldr.w\tr4, [r3, #168]\t@ 0xa8\n-\tmov\tsl, r0\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd.w\tr0, lr, r6\n+\tldr.w\tr0, [r3, #168]\t@ 0xa8\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n \tldr.w\tr2, [r3, #148]\t@ 0x94\n-\tldr.w\tr8, [r3, #192]\t@ 0xc0\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr4, [r7, #732]\t@ 0x2dc\n-\tldrd\tr2, r1, [r3, #204]\t@ 0xcc\n \tldr.w\tr4, [r3, #180]\t@ 0xb4\n+\tstr.w\tr1, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tldrd\tr2, r1, [r3, #204]\t@ 0xcc\n+\tldr.w\tr0, [r3, #192]\t@ 0xc0\n \tldr.w\tr3, [r3, #164]\t@ 0xa4\n-\tmov\tr9, r3\n-\tmov\tr3, fp\n-\tcmp\tr3, #0\n-\tbeq.w\t35f4 <__gridxc_cell_MOD_cellxc+0x3018>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tcmp.w\tlr, #0\n+\tbeq.w\t36ee <__gridxc_cell_MOD_cellxc+0x30da>\n+\tmov\tr3, sl\n \tmul.w\tr3, r4, r3\n \tmov\tr4, r3\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tmul.w\tr8, r8, r3\n+\tmov\tr3, fp\n+\tmul.w\tr3, r0, r3\n+\tmov\tr0, r3\n \tmul.w\tr3, r2, r1\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tmov\tr3, r9\n+\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tmul.w\tr3, r2, r3\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tmla\tr3, r2, r0, r3\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldrd\tr3, r2, [r7, #732]\t@ 0x2dc\n+\tmla\tr3, r2, r6, r3\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n \tadd\tr3, r4\n \tcmp\tr2, #0\n-\tadd\tr3, r8\n-\tble.n\t1f74 <__gridxc_cell_MOD_cellxc+0x1998>\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n+\tadd\tr3, r0\n+\tble.n\t2004 <__gridxc_cell_MOD_cellxc+0x19f0>\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tmla\tr3, r9, r3, r2\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n+\tmla\tr3, r2, r3, lr\n \tmovs\tr2, #0\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tadds\tr2, #1\n \tldrd\tsl, fp, [r3]\n \tstrd\tsl, fp, [r1], #8\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n \tadd\tr3, r1\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n-\tcmp\tr1, r2\n-\tbne.n\t1f54 <__gridxc_cell_MOD_cellxc+0x1978>\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tadds\tr3, r6, #1\n-\tcmp\tr6, r2\n-\tbge.w\t33e8 <__gridxc_cell_MOD_cellxc+0x2e0c>\n-\tadd.w\tr0, lr, r3\n-\tmov\tr6, r3\n-\tb.n\t1f24 <__gridxc_cell_MOD_cellxc+0x1948>\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tcmp\tr2, r1\n+\tbne.n\t1fe4 <__gridxc_cell_MOD_cellxc+0x19d0>\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadds\tr3, r5, #1\n+\tcmp\tr5, r2\n+\tbge.w\t34c6 <__gridxc_cell_MOD_cellxc+0x2eb2>\n+\tadd.w\tr6, ip, r3\n+\tmov\tr5, r3\n+\tb.n\t1fb8 <__gridxc_cell_MOD_cellxc+0x19a4>\n+\t...\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x000002d0\n+\t.word\t0x000002d2\n R_ARM_REL32\t.bss\n-\t.word\t0x000002a4\n+\t.word\t0x0000024e\n R_ARM_REL32\t.bss\n-\t.word\t0x000000e6\n+\t.word\t0x000000ea\n R_ARM_REL32\t.bss\n \tldr.w\tr3, [r7, #204]\t@ 0xcc\n-\tvmov.i64\td17, #0x0000000000000000\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n \tmovs\tr2, #0\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n+\tvldr\td6, [pc, #840]\t@ 2388 <__gridxc_cell_MOD_cellxc+0x1d74>\n \tadds\tr3, #1\n \tstr.w\tr3, [r7, #204]\t@ 0xcc\n-\tvldr\td16, [r0]\n+\tvldr\td7, [r0]\n+\tvcmpe.f64\td7, #0.0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tcmp\tr1, r2\n \tadd.w\tr2, r2, #1\n-\tvmaxnm.f64\td16, d16, d17\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t1fb0 <__gridxc_cell_MOD_cellxc+0x19d4>\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t2048 <__gridxc_cell_MOD_cellxc+0x1a34>\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbne.w\t33d0 <__gridxc_cell_MOD_cellxc+0x2df4>\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tbne.w\t34aa <__gridxc_cell_MOD_cellxc+0x2e96>\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tcmp\tr3, #0\n-\tble.w\t1e0c <__gridxc_cell_MOD_cellxc+0x1830>\n+\tble.w\t1ea6 <__gridxc_cell_MOD_cellxc+0x1892>\n \tldr\tr3, [r7, #72]\t@ 0x48\n-\tstr.w\tr3, [r7, #636]\t@ 0x27c\n-\tldr\tr3, [r7, #32]\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n+\tstr.w\tr3, [r7, #644]\t@ 0x284\n+\tldr\tr3, [r7, #28]\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n \tldr\tr3, [r7, #80]\t@ 0x50\n-\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n \tldr\tr3, [r7, #76]\t@ 0x4c\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tstr.w\tr3, [r7, #604]\t@ 0x25c\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n \tstr.w\tfp, [r7, #624]\t@ 0x270\n-\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n-\tldr.w\tfp, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n+\tldr.w\tfp, [r7, #216]\t@ 0xd8\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n \tstr.w\tr3, [r7, #608]\t@ 0x260\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n-\tstr.w\tr3, [r7, #612]\t@ 0x264\n-\tmov.w\tr3, sl, lsl #3\n-\tstrd\tsl, r8, [r7, #16]\n-\tstr.w\tr3, [r7, #408]\t@ 0x198\n+\tlsls\tr3, r6, #3\n+\tstrd\tr6, r9, [r7, #12]\n+\tstr.w\tr3, [r7, #400]\t@ 0x190\n \tmovs\tr3, #1\n-\tstr.w\tr9, [r7, #12]\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tr3, r7, #960\t@ 0x3c0\n-\tstr\tr5, [r7, #8]\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tstr.w\tr8, [r7, #8]\n+\tstr.w\tr3, [r7, #524]\t@ 0x20c\n+\tadd.w\tr3, r7, #920\t@ 0x398\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n \tadd.w\tr3, r7, #936\t@ 0x3a8\n-\tstr.w\tr3, [r7, #216]\t@ 0xd8\n-\tadd.w\tr3, r7, #952\t@ 0x3b8\n-\tstr.w\tr3, [r7, #212]\t@ 0xd4\n-\tadd.w\tr3, r7, #944\t@ 0x3b0\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr3, [pc, #2300]\t@ 2948 <__gridxc_cell_MOD_cellxc+0x236c>\n+\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr\tr3, [pc, #696]\t@ (2390 <__gridxc_cell_MOD_cellxc+0x1d7c>)\n \tmovs\tr2, #3\n-\tldr.w\tr5, [r7, #636]\t@ 0x27c\n+\tldr.w\tr5, [r7, #644]\t@ 0x284\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n \tldr.w\tr4, [r3, #556]\t@ 0x22c\n \tcmp\tr0, #0\n-\tbeq.w\t2538 <__gridxc_cell_MOD_cellxc+0x1f5c>\n-\tldr.w\tr3, [pc, #2272]\t@ 294c <__gridxc_cell_MOD_cellxc+0x2370>\n+\tbeq.w\t25e0 <__gridxc_cell_MOD_cellxc+0x1fcc>\n+\tldr\tr3, [pc, #668]\t@ (2394 <__gridxc_cell_MOD_cellxc+0x1d80>)\n \tmovs\tr2, #3\n \tmov\tr1, r5\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t2538 <__gridxc_cell_MOD_cellxc+0x1f5c>\n-\tldr.w\tr3, [pc, #2252]\t@ 2950 <__gridxc_cell_MOD_cellxc+0x2374>\n+\tbeq.w\t25e0 <__gridxc_cell_MOD_cellxc+0x1fcc>\n+\tldr\tr3, [pc, #652]\t@ (2398 <__gridxc_cell_MOD_cellxc+0x1d84>)\n \tmovs\tr2, #3\n \tmov\tr1, r5\n \tmovs\tr0, #20\n \tadd\tr3, pc\n-\tvmul.f64\td10, d8, d15\n+\tvmul.f64\td8, d10, d11\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t24d2 <__gridxc_cell_MOD_cellxc+0x1ef6>\n-\tldr.w\tr3, [pc, #2232]\t@ 2954 <__gridxc_cell_MOD_cellxc+0x2378>\n+\tbeq.w\t257e <__gridxc_cell_MOD_cellxc+0x1f6a>\n+\tldr\tr3, [pc, #632]\t@ (239c <__gridxc_cell_MOD_cellxc+0x1d88>)\n \tmovs\tr2, #3\n \tmov\tr1, r5\n \tmovs\tr0, #20\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t24d2 <__gridxc_cell_MOD_cellxc+0x1ef6>\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n+\tbeq.w\t257e <__gridxc_cell_MOD_cellxc+0x1f6a>\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n \tmov\tr2, r4\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n \tstr\tr3, [sp, #24]\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n+\tldr.w\tr3, [r7, #256]\t@ 0x100\n \tstr\tr3, [sp, #20]\n-\tldr.w\tr3, [r7, #260]\t@ 0x104\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #216]\t@ 0xd8\n-\tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tldr.w\tr4, [r7, #536]\t@ 0x218\n+\tstr\tr4, [sp, #4]\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n \tstr\tr3, [sp, #0]\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr1, [r7, #404]\t@ 0x194\n-\tldr.w\tr0, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr1, [r7, #396]\t@ 0x18c\n+\tldr.w\tr0, [r7, #584]\t@ 0x248\n \tbl\t0 <__gridxc_lda_MOD_ldaxc>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_ldaxc\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tvldr\td22, [r3, #-8]\n \tmovs\tr3, #0\n+\tvldr\td3, [r4]\n \tmov\tlr, r3\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tvldmia\tr2!, {d18}\n-\tvldr\td21, [r3, #-8]\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n-\tldr.w\tr2, [r7, #520]\t@ 0x208\n-\tvmul.f64\td21, d18, d21\n-\tvldmia\tr2!, {d17}\n-\tvstr\td21, [r3, #-8]\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tvmul.f64\td22, d17, d22\n-\tstr.w\tr2, [r7, #520]\t@ 0x208\n-\tvstr\td22, [r3, #-8]\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tcmp\tr3, #0\n-\tble.n\t2186 <__gridxc_cell_MOD_cellxc+0x1baa>\n-\tldr.w\tr1, [r7, #660]\t@ 0x294\n-\tmov\tr0, r3\n-\tmovs\tr3, #0\n-\tvldr\td16, [r1]\n+\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tvldmia\tr2!, {d5}\n+\tvldr\td4, [r3]\n+\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tvmul.f64\td4, d5, d4\n+\tvldmia\tr2!, {d6}\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tvmul.f64\td3, d6, d3\n+\tstr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tvstr\td3, [r3]\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tcmp\tr3, #0\n+\tittt\tgt\n+\tmovgt\tr0, r3\n+\tmovgt\tr3, #0\n+\tldrgt.w\tr1, [r7, #668]\t@ 0x29c\n+\tble.n\t220a <__gridxc_cell_MOD_cellxc+0x1bf6>\n+\tvldr\td7, [r1]\n \tmov\tr2, r3\n \tadds\tr3, #1\n \tcmp\tr0, r3\n-\tvmul.f64\td16, d18, d16\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t2150 <__gridxc_cell_MOD_cellxc+0x1b74>\n-\tldr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tvmul.f64\td7, d5, d7\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t21d4 <__gridxc_cell_MOD_cellxc+0x1bc0>\n+\tldr.w\tr0, [r7, #684]\t@ 0x2ac\n \tmovs\tr1, #0\n-\tvldr\td16, [r0]\n+\tvldr\td7, [r0]\n \tcmp\tr2, r1\n \tadd.w\tr1, r1, #1\n-\tvmul.f64\td16, d17, d16\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t216a <__gridxc_cell_MOD_cellxc+0x1b8e>\n+\tvmul.f64\td7, d6, d7\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t21ee <__gridxc_cell_MOD_cellxc+0x1bda>\n \tcmp.w\tlr, #0\n-\tbne.w\t2c10 <__gridxc_cell_MOD_cellxc+0x2634>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tbne.w\t2cec <__gridxc_cell_MOD_cellxc+0x26d8>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbne.w\t2492 <__gridxc_cell_MOD_cellxc+0x1eb6>\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tvmul.f64\td16, d21, d10\n-\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n-\tvmul.f64\td19, d22, d10\n-\tvldr\td18, [r3]\n-\tvldr\td17, [r2]\n-\tvadd.f64\td18, d18, d16\n-\tvadd.f64\td17, d17, d19\n-\tvstr\td18, [r3]\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n-\tvstr\td17, [r2]\n-\tcbz\tr3, 21d4 <__gridxc_cell_MOD_cellxc+0x1bf8>\n-\tldr.w\tr2, [r7, #408]\t@ 0x198\n-\tvadd.f64\td21, d21, d22\n+\tbne.w\t253e <__gridxc_cell_MOD_cellxc+0x1f2a>\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tvmul.f64\td5, d4, d8\n+\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n+\tvmul.f64\td2, d3, d8\n+\tvldr\td7, [r3]\n+\tvldr\td6, [r2]\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td6, d6, d2\n+\tvstr\td7, [r3]\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tvstr\td6, [r2]\n+\tcbz\tr3, 2258 <__gridxc_cell_MOD_cellxc+0x1c44>\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n+\tvadd.f64\td4, d4, d3\n \tldr\tr3, [r7, #68]\t@ 0x44\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #648]\t@ 0x288\n+\tldr.w\tr2, [r7, #652]\t@ 0x28c\n \tadd\tr3, r2\n-\tvstr\td21, [r3]\n+\tvstr\td4, [r3]\n \tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tvldr\td17, [fp]\n-\tvldr\td23, [r3]\n-\tvadd.f64\td19, d19, d17\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tvadd.f64\td23, d16, d23\n+\tvldr\td1, [fp]\n+\tvldr\td6, [r3]\n+\tvadd.f64\td1, d5, d1\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tvadd.f64\td2, d2, d6\n \tcmp\tr3, #0\n-\tbne.w\t2402 <__gridxc_cell_MOD_cellxc+0x1e26>\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tbne.w\t24ac <__gridxc_cell_MOD_cellxc+0x1e98>\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, #0\n-\tble.w\t32f4 <__gridxc_cell_MOD_cellxc+0x2d18>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n-\tldr.w\tr2, [r7, #716]\t@ 0x2cc\n+\tble.w\t33c4 <__gridxc_cell_MOD_cellxc+0x2db0>\n+\tldr.w\tr0, [r7, #668]\t@ 0x29c\n \tmovs\tr3, #0\n-\tldr.w\tr4, [r7, #764]\t@ 0x2fc\n-\tvldmia\tr2!, {d18}\n+\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr4, [r7, #796]\t@ 0x31c\n+\tvldr\td6, [pc, #248]\t@ 2388 <__gridxc_cell_MOD_cellxc+0x1d74>\n+\tvldmia\tr2!, {d5}\n \tmov\tr1, r3\n-\tvldmia\tr0!, {d17}\n+\tvldmia\tr0!, {d7}\n \tadds\tr3, #1\n \tcmp\tr4, r3\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t220e <__gridxc_cell_MOD_cellxc+0x1c32>\n-\tvfms.f64\td23, d15, d16\n-\tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tvneg.f64\td20, d15\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr.w\tr4, [r7, #672]\t@ 0x2a0\n+\tvmla.f64\td6, d5, d7\n+\tbne.n\t2292 <__gridxc_cell_MOD_cellxc+0x1c7e>\n+\tvmls.f64\td1, d11, d6\n+\tldr.w\tr4, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n \tmovs\tr2, #0\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n-\tvstr\td23, [r3]\n-\tvldmia\tr0!, {d18}\n+\tvldr\td7, [pc, #208]\t@ 2388 <__gridxc_cell_MOD_cellxc+0x1d74>\n+\tvstr\td1, [fp]\n+\tvldmia\tr0!, {d5}\n \tcmp\tr1, r2\n-\tvldmia\tr4!, {d17}\n+\tvldmia\tr4!, {d6}\n \tadd.w\tr2, r2, #1\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t2240 <__gridxc_cell_MOD_cellxc+0x1c64>\n-\tldr.w\tr3, [pc, #1792]\t@ 2958 <__gridxc_cell_MOD_cellxc+0x237c>\n-\tvfma.f64\td19, d20, d16\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t22bc <__gridxc_cell_MOD_cellxc+0x1ca8>\n+\tvmls.f64\td2, d11, d7\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tvstr\td2, [r3]\n+\tldr\tr3, [pc, #192]\t@ (23a0 <__gridxc_cell_MOD_cellxc+0x1d8c>)\n \tadd\tr3, pc\n \tldr.w\tr3, [r3, #564]\t@ 0x234\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tvstr\td19, [fp]\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n \tcmp\tr3, #0\n-\tbeq.w\t2902 <__gridxc_cell_MOD_cellxc+0x2326>\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr0, [pc, #1764]\t@ 295c <__gridxc_cell_MOD_cellxc+0x2380>\n+\tbeq.w\t29e8 <__gridxc_cell_MOD_cellxc+0x23d4>\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr\tr5, [pc, #176]\t@ (23a4 <__gridxc_cell_MOD_cellxc+0x1d90>)\n \tldr\tr1, [r3, #0]\n-\tadd\tr0, pc\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tldr.w\tr2, [r0, #588]\t@ 0x24c\n+\tadd\tr5, pc\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr2, [r5, #588]\t@ 0x24c\n+\tldr\tr0, [r3, #0]\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tldr\tr4, [r3, #0]\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n-\tldr\tr5, [r3, #0]\n-\tldr.w\tr3, [r0, #568]\t@ 0x238\n+\tldr.w\tr3, [r5, #568]\t@ 0x238\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r0, #600]\t@ 0x258\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr2, [r5, #600]\t@ 0x258\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n \tcmp\tr1, #0\n+\tmla\tr3, r0, r2, r3\n+\tldr.w\tr2, [r5, #612]\t@ 0x264\n \tmla\tr3, r4, r2, r3\n-\tldr.w\tr2, [r0, #612]\t@ 0x264\n-\tmla\tr3, r5, r2, r3\n-\tldrd\tr4, r2, [r0, #624]\t@ 0x270\n-\tble.n\t22f0 <__gridxc_cell_MOD_cellxc+0x1d14>\n+\tldrd\tr4, r2, [r5, #624]\t@ 0x270\n+\tble.n\t236e <__gridxc_cell_MOD_cellxc+0x1d5a>\n \tmla\tr3, r4, r2, r3\n-\tmov\tr5, r1\n-\tldr.w\tr2, [r0, #584]\t@ 0x248\n-\tldr.w\tr1, [r7, #616]\t@ 0x268\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n-\tmul.w\tr4, r2, r4\n+\tldr.w\tr1, [r7, #620]\t@ 0x26c\n+\tldr.w\tr2, [r5, #584]\t@ 0x248\n+\tldr.w\tr0, [r7, #668]\t@ 0x29c\n+\tldr.w\tr5, [r7, #796]\t@ 0x31c\n \tmla\tr3, r2, r3, r1\n-\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tmul.w\tr4, r2, r4\n \tmovs\tr2, #0\n-\tvldr\td18, [r3]\n+\tvldr\td5, [r3]\n \tadds\tr2, #1\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tcmp\tr5, r2\n-\tvldmia\tr1!, {d17}\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvldmia\tr1!, {d6}\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r4\n-\tbne.n\t22d0 <__gridxc_cell_MOD_cellxc+0x1cf4>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tbne.n\t234e <__gridxc_cell_MOD_cellxc+0x1d3a>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.n\t2376 <__gridxc_cell_MOD_cellxc+0x1d9a>\n-\tldr.w\tr4, [pc, #1636]\t@ 2960 <__gridxc_cell_MOD_cellxc+0x2384>\n-\tadd\tr4, pc\n-\tldr.w\tr2, [r4, #636]\t@ 0x27c\n-\tcmp\tr2, #0\n-\tbeq.w\t2c80 <__gridxc_cell_MOD_cellxc+0x26a4>\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr1, [r4, #660]\t@ 0x294\n-\tldr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tldr\tr0, [r3, #0]\n-\tldr.w\tr3, [r4, #640]\t@ 0x280\n-\tmla\tr3, r0, r1, r3\n-\tldr.w\tr0, [r7, #668]\t@ 0x29c\n-\tldr.w\tr1, [r4, #672]\t@ 0x2a0\n+\tbeq.n\t241c <__gridxc_cell_MOD_cellxc+0x1e08>\n+\tldr\tr5, [pc, #48]\t@ (23a8 <__gridxc_cell_MOD_cellxc+0x1d94>)\n+\tadd\tr5, pc\n+\tldr.w\tr3, [r5, #636]\t@ 0x27c\n+\tcmp\tr3, #0\n+\tbeq.w\t2d5c <__gridxc_cell_MOD_cellxc+0x2748>\n+\tb.n\t23ac <__gridxc_cell_MOD_cellxc+0x1d98>\n+\tnop\n+\t...\n+\t.word\t0x000002ac\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x00000292\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x00000282\n+ R_ARM_REL32\t.LC6\n+\t.word\t0x0000026e\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x000000be\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000aa\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000002c\n+ R_ARM_REL32\t.bss\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr0, [r5, #660]\t@ 0x294\n+\tldr.w\tr1, [r5, #640]\t@ 0x280\n+\tldr\tr4, [r2, #0]\n+\tldr.w\tr2, [r5, #672]\t@ 0x2a0\n+\tldr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tmla\tr1, r4, r0, r1\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n \tldr\tr0, [r0, #0]\n-\tmla\tr0, r0, r1, r3\n-\tldr.w\tr1, [r7, #664]\t@ 0x298\n-\tldr.w\tr3, [r4, #684]\t@ 0x2ac\n+\tmla\tr0, r0, r2, r1\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr2, [r5, #684]\t@ 0x2ac\n \tldr\tr1, [r1, #0]\n-\tmla\tr0, r1, r3, r0\n-\tldrd\tr1, r3, [r4, #696]\t@ 0x2b8\n-\tcbz\tr5, 2376 <__gridxc_cell_MOD_cellxc+0x1d9a>\n-\tmla\tr0, r1, r3, r0\n-\tldr.w\tr4, [r4, #656]\t@ 0x290\n-\tmla\tr3, r4, r0, r2\n+\tmla\tr0, r1, r2, r0\n+\tldrd\tr2, r1, [r5, #696]\t@ 0x2b8\n+\tcbz\tr6, 241c <__gridxc_cell_MOD_cellxc+0x1e08>\n+\tmla\tr0, r2, r1, r0\n+\tldr.w\tr4, [r5, #656]\t@ 0x290\n+\tmov\tr5, r6\n+\tmla\tr3, r4, r0, r3\n+\tldrd\tr0, r1, [r7, #252]\t@ 0xfc\n+\tmul.w\tr4, r2, r4\n \tmovs\tr2, #0\n-\tmul.w\tr4, r1, r4\n-\tldrd\tr0, r1, [r7, #260]\t@ 0x104\n+\tvldr\td5, [r3]\n \tadds\tr2, #1\n-\tvldr\td18, [r3]\n+\tvldmia\tr0!, {d7}\n \tcmp\tr5, r2\n-\tvldmia\tr0!, {d16}\n-\tvldmia\tr1!, {d17}\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvldmia\tr1!, {d6}\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r4\n-\tbne.n\t2356 <__gridxc_cell_MOD_cellxc+0x1d7a>\n+\tbne.n\t23fc <__gridxc_cell_MOD_cellxc+0x1de8>\n \tcmp.w\tlr, #0\n-\tbne.w\t297c <__gridxc_cell_MOD_cellxc+0x23a0>\n-\tldr.w\tr2, [r7, #636]\t@ 0x27c\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tbne.w\t2a22 <__gridxc_cell_MOD_cellxc+0x240e>\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tldr.w\tr3, [r7, #524]\t@ 0x20c\n \tadds\tr2, #20\n-\tstr.w\tr2, [r7, #636]\t@ 0x27c\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tstr.w\tr2, [r7, #644]\t@ 0x284\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr3, [r7, #524]\t@ 0x20c\n \tadds\tr2, #20\n-\tstr.w\tr2, [r7, #600]\t@ 0x258\n-\tldr.w\tr2, [r7, #604]\t@ 0x25c\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #592]\t@ 0x250\n \tadds\tr2, #4\n-\tstr.w\tr2, [r7, #604]\t@ 0x25c\n+\tstr.w\tr2, [r7, #592]\t@ 0x250\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tadds\tr2, #4\n+\tstr.w\tr2, [r7, #600]\t@ 0x258\n \tldr.w\tr2, [r7, #608]\t@ 0x260\n \tadds\tr2, #4\n \tstr.w\tr2, [r7, #608]\t@ 0x260\n-\tldr.w\tr2, [r7, #612]\t@ 0x264\n-\tadds\tr2, #4\n-\tstr.w\tr2, [r7, #612]\t@ 0x264\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n \tcmp\tr3, r2\n-\tble.w\t2048 <__gridxc_cell_MOD_cellxc+0x1a6c>\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldrd\tsl, r8, [r7, #16]\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tble.w\t20d6 <__gridxc_cell_MOD_cellxc+0x1ac2>\n+\tldr.w\tr3, [r7, #388]\t@ 0x184\n+\tldrd\tr6, r9, [r7, #12]\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tcmp\tsl, r2\n-\tldr.w\tr9, [r7, #12]\n-\tadd.w\tr3, sl, #1\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tcmp\tr6, r2\n+\tldr.w\tsl, [r7, #208]\t@ 0xd0\n+\tadd.w\tr3, r6, #1\n+\tldr.w\tr8, [r7, #8]\n \tldr.w\tfp, [r7, #624]\t@ 0x270\n-\tldr\tr5, [r7, #8]\n-\tbne.w\t1e1a <__gridxc_cell_MOD_cellxc+0x183e>\n-\tmov\tip, r9\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\tbne.w\t1eb2 <__gridxc_cell_MOD_cellxc+0x189e>\n+\tstr.w\tsl, [r7, #620]\t@ 0x26c\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n \tadds\tr3, r2, #1\n \tcmp\tr2, r1\n-\tbge.w\t33fe <__gridxc_cell_MOD_cellxc+0x2e22>\n-\tstr.w\tr3, [r7, #564]\t@ 0x234\n-\tb.n\t1cee <__gridxc_cell_MOD_cellxc+0x1712>\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tldr.w\tr4, [r7, #764]\t@ 0x2fc\n+\tbge.w\t34dc <__gridxc_cell_MOD_cellxc+0x2ec8>\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tb.n\t1d7c <__gridxc_cell_MOD_cellxc+0x1768>\n+\tldr.w\tr3, [r7, #276]\t@ 0x114\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tldr.w\tr4, [r7, #796]\t@ 0x31c\n \tcmp\tr4, #0\n \tmul.w\tr2, r2, r3\n-\tble.w\t32f4 <__gridxc_cell_MOD_cellxc+0x2d18>\n-\tldr.w\tr5, [r7, #420]\t@ 0x1a4\n+\tble.w\t33c4 <__gridxc_cell_MOD_cellxc+0x2db0>\n+\tldr.w\tr5, [r7, #412]\t@ 0x19c\n \tmov\tr8, r4\n-\tldr.w\tr3, [r7, #144]\t@ 0x90\n-\tldr.w\tr0, [r7, #424]\t@ 0x1a8\n+\tldr.w\tr3, [r7, #140]\t@ 0x8c\n+\tldr.w\tr0, [r7, #416]\t@ 0x1a0\n \tldr\tr1, [r7, #108]\t@ 0x6c\n \tadd\tr3, r5\n \tadd\tr3, r0\n \tmov.w\tip, r5, lsl #3\n \tadd\tr3, r1\n-\tlsls\tr6, r0, #3\n+\tldr.w\tr1, [r7, #756]\t@ 0x2f4\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #588]\t@ 0x24c\n+\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tlsls\tr6, r0, #3\n \tlsls\tr5, r0, #4\n \tmovs\tr0, #0\n \tadd.w\tr3, r2, r3, lsl #3\n-\tldr.w\tr2, [r7, #408]\t@ 0x198\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n \tadd\tr3, r2\n-\tldrd\tr1, r2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n+\tvldr\td5, [r1]\n \tadds\tr4, r3, r6\n-\tvldr\td18, [r1]\n+\tvldr\td6, [r2]\n \tadds\tr0, #1\n-\tvldr\td22, [r2]\n+\tvldr\td7, [r1, #8]\n+\tadds\tr2, #24\n+\tvldr\td4, [r2, #-16]\n \tadds\tr1, #24\n-\tvldr\td21, [r2, #8]\n+\tvldr\td0, [r1, #-8]\n+\tvadd.f64\td6, d5, d6\n+\tvldr\td3, [r2, #-8]\n \tcmp\tr8, r0\n-\tvldr\td17, [r1, #-16]\n-\tadd.w\tr2, r2, #24\n-\tvldr\td16, [r1, #-8]\n-\tvadd.f64\td18, d18, d22\n-\tvldr\td20, [r2, #-8]\n-\tvadd.f64\td17, d17, d21\n-\tvadd.f64\td16, d16, d20\n-\tvstr\td18, [r3]\n-\tvstr\td17, [r4]\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td3, d0, d3\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r4]\n \tadd.w\tr4, r3, r5\n \tadd\tr3, ip\n-\tvstr\td16, [r4]\n-\tbne.n\t244c <__gridxc_cell_MOD_cellxc+0x1e70>\n-\tb.n\t21fc <__gridxc_cell_MOD_cellxc+0x1c20>\n-\tldr.w\tr1, [r7, #440]\t@ 0x1b8\n+\tvstr\td3, [r4]\n+\tbne.n\t24fa <__gridxc_cell_MOD_cellxc+0x1ee6>\n+\tb.n\t2280 <__gridxc_cell_MOD_cellxc+0x1c6c>\n+\tldr.w\tr1, [r7, #428]\t@ 0x1ac\n \tcmp\tr1, #0\n-\tbeq.w\t2190 <__gridxc_cell_MOD_cellxc+0x1bb4>\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n+\tbeq.w\t2214 <__gridxc_cell_MOD_cellxc+0x1c00>\n+\tldr.w\tr2, [r7, #252]\t@ 0xfc\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tmov\tr0, r3\n \tadds\tr3, #1\n \tcmp\tr1, r3\n-\tvmul.f64\td16, d18, d16\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t24a2 <__gridxc_cell_MOD_cellxc+0x1ec6>\n-\tldr.w\tr1, [r7, #264]\t@ 0x108\n+\tvmul.f64\td7, d5, d7\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t254e <__gridxc_cell_MOD_cellxc+0x1f3a>\n+\tldr.w\tr1, [r7, #256]\t@ 0x100\n \tmovs\tr2, #0\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tcmp\tr0, r2\n \tadd.w\tr2, r2, #1\n-\tvmul.f64\td16, d17, d16\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t24bc <__gridxc_cell_MOD_cellxc+0x1ee0>\n-\tb.n\t2190 <__gridxc_cell_MOD_cellxc+0x1bb4>\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n+\tvmul.f64\td7, d6, d7\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t2568 <__gridxc_cell_MOD_cellxc+0x1f54>\n+\tb.n\t2214 <__gridxc_cell_MOD_cellxc+0x1c00>\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n \tmov\tr2, r4\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tstr\tr3, [sp, #24]\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n \tstr\tr3, [sp, #20]\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #216]\t@ 0xd8\n-\tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n-\tstr\tr3, [sp, #4]\n+\tldr.w\tr4, [r7, #536]\t@ 0x218\n+\tstr\tr4, [sp, #8]\n \tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tstr\tr3, [sp, #4]\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tstr\tr3, [sp, #0]\n \tmovs\tr3, #20\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr1, [r7, #404]\t@ 0x194\n-\tldr.w\tr0, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr1, [r7, #396]\t@ 0x18c\n+\tldr.w\tr0, [r7, #584]\t@ 0x248\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tmov.w\tlr, #1\n-\tvldr\td22, [r3, #-8]\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tb.n\t210c <__gridxc_cell_MOD_cellxc+0x1b30>\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tvldr\td3, [r4]\n+\tmov.w\tlr, #1\n+\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tb.n\t218e <__gridxc_cell_MOD_cellxc+0x1b7a>\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tmov\tr1, r4\n \tstr\tr3, [sp, #20]\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [r7, #216]\t@ 0xd8\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n \tstr\tr3, [sp, #0]\n-\tldr.w\tr6, [r7, #528]\t@ 0x210\n-\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr0, [r7, #404]\t@ 0x194\n+\tldr.w\tr6, [r7, #512]\t@ 0x200\n+\tldr.w\tr5, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr0, [r7, #396]\t@ 0x18c\n \tmov\tr3, r6\n \tmov\tr2, r5\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_localxc>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_localxc\n-\tldr\tr1, [r7, #52]\t@ 0x34\n+\tldr\tr1, [r7, #56]\t@ 0x38\n \tstr\tr1, [sp, #4]\n \tmov\tr0, r4\n-\tldr\tr1, [r7, #56]\t@ 0x38\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n+\tadd.w\tr3, r7, #928\t@ 0x3a0\n \tmov\tr2, r6\n \tstr\tr1, [sp, #0]\n \tmov\tr1, r5\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_decusp>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_decusp\n-\tldr\tr3, [pc, #984]\t@ (2964 <__gridxc_cell_MOD_cellxc+0x2388>)\n+\tldr\tr3, [pc, #924]\t@ (29d0 <__gridxc_cell_MOD_cellxc+0x23bc>)\n \tmov\tr0, r4\n \tmov\tr1, r5\n \tadd\tr3, pc\n \tmov\tr2, r6\n \taddw\tr4, r3, #1428\t@ 0x594\n \tstr\tr4, [sp, #4]\n \taddw\tr4, r3, #1380\t@ 0x564\n \taddw\tr3, r3, #1620\t@ 0x654\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_theta\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tble.w\t33c0 <__gridxc_cell_MOD_cellxc+0x2de4>\n-\tvmov.i64\td8, #0x0000000000000000\n+\tble.w\t349a <__gridxc_cell_MOD_cellxc+0x2e86>\n+\tvldr\td10, [pc, #868]\t@ 29c0 <__gridxc_cell_MOD_cellxc+0x23ac>\n \tmov\tr2, r5\n \tmovs\tr3, #0\n-\tvldmia\tr2!, {d16}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n \tcmp\tr1, r3\n-\tvadd.f64\td8, d8, d16\n-\tbne.n\t25ba <__gridxc_cell_MOD_cellxc+0x1fde>\n-\tvldr\td19, [pc, #884]\t@ 2940 <__gridxc_cell_MOD_cellxc+0x2364>\n-\tvmul.f64\td10, d15, d8\n-\tvadd.f64\td19, d8, d19\n-\tldr\tr3, [pc, #912]\t@ (2968 <__gridxc_cell_MOD_cellxc+0x238c>)\n-\tadd.w\tlr, r7, #892\t@ 0x37c\n+\tvadd.f64\td10, d10, d7\n+\tbne.n\t2662 <__gridxc_cell_MOD_cellxc+0x204e>\n+\tvldr\td4, [pc, #852]\t@ 29c8 <__gridxc_cell_MOD_cellxc+0x23b4>\n+\tvmul.f64\td8, d11, d10\n+\tvadd.f64\td4, d10, d4\n+\tldr\tr3, [pc, #852]\t@ (29d4 <__gridxc_cell_MOD_cellxc+0x23c0>)\n+\tadd.w\tlr, r7, #876\t@ 0x36c\n \tldr.w\tr6, [lr]\n \tmov\tr8, sp\n \tadd\tr3, pc\n \tcmp\tr6, #0\n-\tldr.w\tr9, [r3, #1888]\t@ 0x760\n-\tldr.w\tr5, [r3, #1892]\t@ 0x764\n+\tldr.w\tr9, [r3, #1884]\t@ 0x75c\n+\tldr.w\tr5, [r3, #1888]\t@ 0x760\n \tldr.w\tsl, [r3, #1692]\t@ 0x69c\n \tldr.w\tr3, [r3, #1696]\t@ 0x6a0\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tble.n\t269e <__gridxc_cell_MOD_cellxc+0x20c2>\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tble.n\t2746 <__gridxc_cell_MOD_cellxc+0x2132>\n \tlsls\tr3, r6, #3\n \tmov\tr1, sp\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t261c <__gridxc_cell_MOD_cellxc+0x2040>\n+\tbeq.n\t26c4 <__gridxc_cell_MOD_cellxc+0x20b0>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t260e <__gridxc_cell_MOD_cellxc+0x2032>\n+\tbne.n\t26b6 <__gridxc_cell_MOD_cellxc+0x20a2>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 262c <__gridxc_cell_MOD_cellxc+0x2050>\n+\tcbz\tr3, 26d4 <__gridxc_cell_MOD_cellxc+0x20c0>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr\tr1, [pc, #828]\t@ (296c <__gridxc_cell_MOD_cellxc+0x2390>)\n+\tldr\tr1, [pc, #768]\t@ (29d8 <__gridxc_cell_MOD_cellxc+0x23c4>)\n \tmovs\tr3, #0\n \tldr.w\tr2, [r7, #204]\t@ 0xcc\n \tadd\tr0, sp, #48\t@ 0x30\n \tadd\tr1, pc\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n \tmov\tr4, r0\n-\tldr.w\tr3, [r1, #1912]\t@ 0x778\n-\tldr.w\tip, [r1, #1924]\t@ 0x784\n+\tldr.w\tr3, [r1, #1908]\t@ 0x774\n+\tldr.w\tip, [r1, #1920]\t@ 0x780\n \tmla\tr3, r3, r2, r5\n-\tldr.w\tr5, [r1, #1908]\t@ 0x774\n+\tldr.w\tr5, [r1, #1904]\t@ 0x770\n \tmovs\tr2, #0\n \tadd\tr3, ip\n \tmla\tr3, r5, r3, r9\n \tmul.w\tr5, ip, r5\n \tldr.w\tip, [r1, #1716]\t@ 0x6b4\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tmov\tr1, r2\n \tadds\tr2, #1\n \tadd\tr3, r5\n \tcmp\tr6, r2\n-\tvstmia\tr4!, {d16}\n-\tbne.n\t265e <__gridxc_cell_MOD_cellxc+0x2082>\n-\tldr\tr3, [pc, #764]\t@ (2970 <__gridxc_cell_MOD_cellxc+0x2394>)\n+\tvstmia\tr4!, {d7}\n+\tbne.n\t2706 <__gridxc_cell_MOD_cellxc+0x20f2>\n+\tldr\tr3, [pc, #704]\t@ (29dc <__gridxc_cell_MOD_cellxc+0x23c8>)\n \tmovs\tr4, #0\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tmov\tr6, fp\n \tadd\tr3, pc\n \tadd\tr2, ip\n \tldr.w\tr5, [r3, #1712]\t@ 0x6b0\n \tmla\tr2, r5, r2, sl\n-\tmul.w\tr5, ip, r5\n+\tmul.w\tr5, r5, ip\n \tldrd\tsl, fp, [r0], #8\n \tcmp\tr1, r4\n \tstrd\tsl, fp, [r2]\n \tadd.w\tr4, r4, #1\n \tadd\tr2, r5\n-\tbne.n\t268a <__gridxc_cell_MOD_cellxc+0x20ae>\n+\tbne.n\t2732 <__gridxc_cell_MOD_cellxc+0x211e>\n \tmov\tfp, r6\n-\tldr\tr1, [pc, #724]\t@ (2974 <__gridxc_cell_MOD_cellxc+0x2398>)\n+\tldr\tr1, [pc, #664]\t@ (29e0 <__gridxc_cell_MOD_cellxc+0x23cc>)\n \tmov\tsp, r8\n \tadd\tr1, pc\n \tldr.w\tr3, [r1, #1720]\t@ 0x6b8\n \tldr.w\tr0, [r1, #1724]\t@ 0x6bc\n \tldr.w\tr5, [r1, #1716]\t@ 0x6b4\n-\tstr.w\tr5, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr5, [r7, #776]\t@ 0x308\n \tcmp\tr3, r0\n \tldr.w\tr9, [r1, #1692]\t@ 0x69c\n \tldr.w\tip, [r1, #1696]\t@ 0x6a0\n \tldr.w\tr6, [r1, #1620]\t@ 0x654\n \tldr.w\tr2, [r1, #1624]\t@ 0x658\n \tldr.w\tr4, [r1, #1648]\t@ 0x670\n \tldr.w\tr5, [r1, #1644]\t@ 0x66c\n-\tbgt.w\t334e <__gridxc_cell_MOD_cellxc+0x2d72>\n+\tbgt.w\t3420 <__gridxc_cell_MOD_cellxc+0x2e0c>\n \tmla\tr2, r5, r4, r2\n-\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tadds\tr0, #1\n-\tvmov.i64\td16, #0x0000000000000000\n+\tvldr\td7, [pc, #568]\t@ 29c0 <__gridxc_cell_MOD_cellxc+0x23ac>\n \tsubs\tr0, r0, r3\n \tmla\tr3, r4, r3, ip\n \tldr.w\tr4, [r1, #1712]\t@ 0x6b0\n \tldr.w\tr1, [r1, #1640]\t@ 0x668\n \tmla\tr3, r4, r3, r9\n \tmla\tr2, r1, r2, r6\n \tmul.w\tr1, r5, r1\n-\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n \tmul.w\tr4, r5, r4\n \tmovs\tr5, #0\n-\tvldr\td18, [r3]\n+\tvldr\td5, [r3]\n \tadds\tr5, #1\n-\tvldr\td17, [r2]\n+\tvldr\td6, [r2]\n \tadd\tr3, r4\n \tadd\tr2, r1\n \tcmp\tr0, r5\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t2704 <__gridxc_cell_MOD_cellxc+0x2128>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td22, d16, d19\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tvldr\td18, [r2, #-8]\n-\tvldr\td16, [r2]\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t27ac <__gridxc_cell_MOD_cellxc+0x2198>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td3, d7, d4\n+\tldr.w\tr2, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tvldr\td6, [r2]\n+\tvldr\td7, [r3, #-8]\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tvadd.f64\td7, d7, d6\n \tldr.w\tr3, [r3, #556]\t@ 0x22c\n-\tvadd.f64\td16, d16, d18\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tvadd.f64\td22, d16, d22\n-\tvstr\td22, [r2, #-8]\n-\tble.w\t28f2 <__gridxc_cell_MOD_cellxc+0x2316>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr\tr6, [pc, #548]\t@ (2978 <__gridxc_cell_MOD_cellxc+0x239c>)\n+\tvadd.f64\td3, d7, d3\n+\tvstr\td3, [r2]\n+\tble.w\t29aa <__gridxc_cell_MOD_cellxc+0x2396>\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr\tr6, [pc, #484]\t@ (29e4 <__gridxc_cell_MOD_cellxc+0x23d0>)\n \tadd.w\tr1, ip, r2\n-\tldr.w\tr2, [lr]\n-\tmov\tr0, r1\n-\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr1, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [r7, #684]\t@ 0x2ac\n \tadd\tr6, pc\n-\tldr\tr4, [r7, #56]\t@ 0x38\n-\tstr.w\tr4, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr2, [lr]\n+\tldr\tr4, [r7, #60]\t@ 0x3c\n \tadd.w\tr3, r1, r3, lsl #3\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tldr.w\tr5, [r6, #1452]\t@ 0x5ac\n \tadd.w\tlr, r3, #24\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n \tldr.w\tr3, [r6, #1432]\t@ 0x598\n+\tstr.w\tr4, [r7, #744]\t@ 0x2e8\n \tldr.w\tr4, [r6, #1476]\t@ 0x5c4\n \tadd\tr3, r5\n \tldr.w\tip, [r6, #1464]\t@ 0x5b8\n+\tldr.w\tr0, [r6, #1416]\t@ 0x588\n \tstr.w\tr2, [r7, #736]\t@ 0x2e0\n \tadds\tr2, r3, r4\n-\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n \tldr.w\tr3, [r6, #1384]\t@ 0x568\n-\tldr.w\tr1, [r6, #1416]\t@ 0x588\n-\tadd\tr3, r1\n-\tadd.w\tr1, r2, ip\n+\tadd\tr3, r0\n+\tadd.w\tr0, r2, ip\n \tldr.w\tr2, [r6, #1404]\t@ 0x57c\n \tadd.w\tsl, r3, r2\n \tldr.w\tr3, [r6, #1448]\t@ 0x5a8\n \tmul.w\tr4, r3, r4\n \tmul.w\tr8, r3, r5\n-\tstr.w\tr4, [r7, #652]\t@ 0x28c\n+\tstr.w\tr4, [r7, #664]\t@ 0x298\n \tmul.w\tr5, r3, ip\n \tldr.w\tr4, [r6, #1416]\t@ 0x588\n \tldr.w\tip, [r6, #1400]\t@ 0x578\n \tmul.w\tr4, ip, r4\n-\tstr.w\tr4, [r7, #676]\t@ 0x2a4\n \tmul.w\tr2, ip, r2\n+\tstr.w\tr4, [r7, #656]\t@ 0x290\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n \tldr.w\tr4, [r6, #1712]\t@ 0x6b0\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmla\tr9, r4, r0, r9\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tmul.w\tr4, r0, r4\n-\tldr.w\tr0, [r6, #1428]\t@ 0x594\n-\tmla\tr1, r3, r1, r0\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tmla\tr9, r4, r2, r9\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tmul.w\tr4, r2, r4\n+\tldr.w\tr2, [r6, #1428]\t@ 0x594\n+\tmla\tr2, r3, r0, r2\n \tldr.w\tr3, [r6, #1380]\t@ 0x564\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr6, [r7, #732]\t@ 0x2dc\n \tmla\tr0, ip, sl, r3\n-\tstr.w\tr0, [r7, #752]\t@ 0x2f0\n-\tldrd\tr1, r0, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr6, [r7, #644]\t@ 0x284\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tstr.w\tfp, [r7, #644]\t@ 0x284\n-\tvmov.i64\td16, #0x0000000000000000\n+\tmov\tr3, r2\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n+\tldr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tfp, [r7, #636]\t@ 0x27c\n+\tvldr\td6, [pc, #252]\t@ 29c0 <__gridxc_cell_MOD_cellxc+0x23ac>\n \tcmp\tr0, #0\n-\tble.n\t28fc <__gridxc_cell_MOD_cellxc+0x2320>\n-\tldr.w\tfp, [r7, #752]\t@ 0x2f0\n+\tble.n\t29b6 <__gridxc_cell_MOD_cellxc+0x23a2>\n+\tldr.w\tfp, [r7, #768]\t@ 0x300\n \tmov\tsl, r9\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tmov.w\tip, #0\n-\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tvldr\td18, [sl]\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tvldr\td5, [sl]\n \tadd.w\tip, ip, #1\n-\tvldr\td17, [fp]\n+\tvldr\td7, [fp]\n \tadd\tsl, r4\n \tadd\tfp, r2\n \tcmp\tr0, ip\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t2834 <__gridxc_cell_MOD_cellxc+0x2258>\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n+\tvmla.f64\td6, d5, d7\n+\tbne.n\t28dc <__gridxc_cell_MOD_cellxc+0x22c8>\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tsub.w\tip, lr, #24\n-\tvldr\td17, [r1]\n+\tvldr\td7, [r1]\n \tmov\tsl, r3\n \tmov\tfp, r6\n-\tvldmia\tr2!, {d18}\n-\tvadd.f64\td17, d17, d18\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tvadd.f64\td16, d17, d16\n-\tvstmia\tr1!, {d16}\n+\tstr.w\tr6, [r7, #728]\t@ 0x2d8\n+\tvldmia\tr2!, {d5}\n+\tvadd.f64\td7, d7, d5\n+\tstr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tvadd.f64\td7, d7, d6\n+\tvstmia\tr1!, {d7}\n \tstrd\tr3, r1, [r7, #732]\t@ 0x2dc\n-\tvmov.i64\td16, #0x0000000000000000\n+\tvldr\td7, [pc, #144]\t@ 29c0 <__gridxc_cell_MOD_cellxc+0x23ac>\n \tcmp\tr0, #0\n-\tble.n\t28a0 <__gridxc_cell_MOD_cellxc+0x22c4>\n-\tmov\tr1, sl\n-\tmov\tr2, r9\n+\tble.n\t2950 <__gridxc_cell_MOD_cellxc+0x233c>\n+\tmov\tr6, sl\n+\tmov\tr1, r9\n \tmovs\tr3, #0\n-\tvldr\td18, [r2]\n+\tvldr\td5, [r1]\n \tadds\tr3, #1\n-\tvldr\td17, [r1]\n-\tadd\tr2, r4\n-\tadd\tr1, r5\n+\tvldr\td6, [r6]\n+\tadd\tr1, r4\n+\tadd\tr6, r5\n \tcmp\tr0, r3\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t288a <__gridxc_cell_MOD_cellxc+0x22ae>\n-\tvldr\td17, [ip]\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t293a <__gridxc_cell_MOD_cellxc+0x2326>\n+\tvldr\td6, [ip]\n \tadd\tsl, r8\n-\tvldmia\tfp!, {d18}\n-\tvadd.f64\td17, d17, d18\n-\tvadd.f64\td17, d17, d16\n-\tvstmia\tip!, {d17}\n+\tvldmia\tfp!, {d5}\n+\tvadd.f64\td6, d6, d5\n+\tvadd.f64\td6, d6, d7\n+\tvstmia\tip!, {d6}\n \tcmp\tlr, ip\n-\tbne.n\t287c <__gridxc_cell_MOD_cellxc+0x22a0>\n+\tbne.n\t292c <__gridxc_cell_MOD_cellxc+0x2318>\n \tldrd\tr3, r1, [r7, #732]\t@ 0x2dc\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n \tadd.w\tlr, lr, #24\n-\tldr.w\tr4, [r7, #676]\t@ 0x2a4\n-\tadds\tr6, #24\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr4, [r7, #656]\t@ 0x290\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr6, [r7, #728]\t@ 0x2d8\n \tadd\tr2, r4\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tadds\tr6, #24\n \tcmp\tr2, r1\n-\tbne.n\t281a <__gridxc_cell_MOD_cellxc+0x223e>\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tbne.n\t28c2 <__gridxc_cell_MOD_cellxc+0x22ae>\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n \tmovs\tr3, #4\n-\tldr.w\tfp, [r7, #644]\t@ 0x284\n+\tldr.w\tfp, [r7, #636]\t@ 0x27c\n \tstr.w\tr3, [r2, #548]\t@ 0x224\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n+\tstr.w\tr3, [r7, #208]\t@ 0xd0\n \tmov\tlr, r3\n-\tb.n\t210c <__gridxc_cell_MOD_cellxc+0x1b30>\n-\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tb.n\t2854 <__gridxc_cell_MOD_cellxc+0x2278>\n-\tmov\tr2, r3\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n-\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n-\tldrd\tr4, r3, [r7, #92]\t@ 0x5c\n-\tldr.w\tr5, [r7, #764]\t@ 0x2fc\n-\tvldr\td18, [r3]\n-\tadds\tr2, #1\n-\tvldmia\tr0!, {d16}\n-\tcmp\tr5, r2\n-\tvldmia\tr1!, {d17}\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n-\tadd\tr3, r4\n-\tbne.n\t2914 <__gridxc_cell_MOD_cellxc+0x2338>\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tb.n\t22f0 <__gridxc_cell_MOD_cellxc+0x1d14>\n+\tb.w\t218e <__gridxc_cell_MOD_cellxc+0x1b7a>\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n+\tb.n\t28fc <__gridxc_cell_MOD_cellxc+0x22e8>\n \tnop.w\n-\t.word\t0x00000000\n+\t...\n \t.word\t0x00100000\n-\t.word\t0x000008f0\n- R_ARM_REL32\t.LC8\n-\t.word\t0x000008d4\n- R_ARM_REL32\t.LC9\n-\t.word\t0x000008c2\n- R_ARM_REL32\t.LC6\n-\t.word\t0x000008ac\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000006f8\n- R_ARM_REL32\t.bss\n-\t.word\t0x000006de\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000660\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003d2\n+\t.word\t0x00000396\n R_ARM_REL32\t.bss\n-\t.word\t0x00000384\n+\t.word\t0x00000348\n R_ARM_REL32\t.bss\n-\t.word\t0x00000332\n+\t.word\t0x000002f6\n R_ARM_REL32\t.bss\n-\t.word\t0x000002f2\n+\t.word\t0x000002b6\n R_ARM_REL32\t.bss\n-\t.word\t0x000002ce\n+\t.word\t0x00000292\n R_ARM_REL32\t.bss\n-\t.word\t0x00000212\n+\t.word\t0x000001d4\n R_ARM_REL32\t.bss\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr3, [pc, #3340]\t@ 3690 <__gridxc_cell_MOD_cellxc+0x30b4>\n+\tmov\tr2, r3\n+\tldr.w\tr0, [r7, #668]\t@ 0x29c\n+\tldr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tldrd\tr4, r3, [r7, #92]\t@ 0x5c\n+\tldr.w\tr5, [r7, #796]\t@ 0x31c\n+\tvldr\td5, [r3]\n+\tadds\tr2, #1\n+\tvldmia\tr0!, {d7}\n+\tcmp\tr5, r2\n+\tvldmia\tr1!, {d6}\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tadd\tr3, r4\n+\tbne.n\t29fa <__gridxc_cell_MOD_cellxc+0x23e6>\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n+\tb.n\t236e <__gridxc_cell_MOD_cellxc+0x1d5a>\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [pc, #3432]\t@ 3790 <__gridxc_cell_MOD_cellxc+0x317c>\n \tldr\tr2, [r2, #0]\n \tadd\tr3, pc\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n+\tstr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n \tldr\tr3, [r3, #0]\n \tldr\tr2, [r2, #0]\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n \tldr\tr2, [r2, #0]\n-\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr6, [r2, #556]\t@ 0x22c\n+\tstr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tldr.w\tr1, [r2, #556]\t@ 0x22c\n+\tstr\tr1, [r7, #36]\t@ 0x24\n \tcmp\tr3, #0\n-\tbne.w\t2cde <__gridxc_cell_MOD_cellxc+0x2702>\n-\tldrd\tr3, sl, [r2, #536]\t@ 0x218\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tbne.w\t2dbc <__gridxc_cell_MOD_cellxc+0x27a8>\n+\tmov\tr3, r2\n+\tldr.w\tr9, [r1]\n \tldr.w\tr5, [r2, #544]\t@ 0x220\n-\tldr.w\tr3, [r2, #532]\t@ 0x214\n-\tldr.w\tr1, [r2, #552]\t@ 0x228\n+\tldr.w\tr2, [r2, #552]\t@ 0x228\n+\tldr.w\tr1, [r3, #540]\t@ 0x21c\n \tcmp\tr5, #1\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r2, #528]\t@ 0x210\n-\tsub.w\tr1, r1, #4\n-\tldr.w\tr8, [r6]\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tbne.w\t343c <__gridxc_cell_MOD_cellxc+0x2e60>\n-\tadd.w\tr9, r7, #1248\t@ 0x4e0\n+\tstr.w\tr1, [r7, #656]\t@ 0x290\n+\tsub.w\tr2, r2, #4\n+\tldr.w\tr1, [r3, #536]\t@ 0x218\n+\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr1, [r3, #532]\t@ 0x214\n+\tldr.w\tr3, [r3, #528]\t@ 0x210\n+\tstr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tbne.w\t3514 <__gridxc_cell_MOD_cellxc+0x2f00>\n+\tadd.w\tr8, r7, #1224\t@ 0x4c8\n+\taddw\tsl, r7, #2488\t@ 0x9b8\n+\tadd.w\tr4, r9, #1\n \tldr\tr6, [r7, #92]\t@ 0x5c\n \tldr.w\tr5, [r7, #624]\t@ 0x270\n-\tadd.w\tr3, r7, #2512\t@ 0x9d0\n-\tmov\tip, r9\n-\tmovs\tr2, #26\n-\tadd.w\tr4, r8, #1\n-\tstr.w\tr8, [r7, #732]\t@ 0x2dc\n-\tstr.w\tsl, [r7, #652]\t@ 0x28c\n-\tldr.w\tr0, [r1, #4]!\n-\tmov\tlr, r3\n-\tmvn.w\tr8, #2\n-\tstr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tstrd\tr3, r2, [r7, #640]\t@ 0x280\n-\tstr.w\tr1, [r7, #628]\t@ 0x274\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r9]\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr3, [r9, #4]\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr3, [r9, #8]\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [ip]\n-\tcmp\tr2, #0\n-\tadd\tr3, r8\n-\tblt.w\t2bf8 <__gridxc_cell_MOD_cellxc+0x261c>\n+\tmov\tr0, r2\n+\tmovs\tr3, #26\n+\tmov\tr1, sl\n+\tmov\tr2, r8\n+\tmov\tip, r4\n+\tstr.w\tr9, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr4, [r0, #4]!\n+\tmov\tr9, r1\n+\tstr.w\tr4, [r7, #784]\t@ 0x310\n+\tmvn.w\tsl, #2\n+\tmov\tr4, ip\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n+\tstr.w\tr1, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr0, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r8]\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr.w\tr3, [r8, #4]\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr3, [r8, #8]\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tldr\tr3, [r2, #0]\n+\tcmp\tr1, #0\n+\tadd\tr3, sl\n+\tblt.w\t2cc4 <__gridxc_cell_MOD_cellxc+0x26b0>\n \tcmp\tr3, #0\n-\tblt.w\t2c0c <__gridxc_cell_MOD_cellxc+0x2630>\n-\tsdiv\tr2, r3, r2\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tmls\tr3, r1, r2, r3\n-\tstr.w\tr3, [ip]\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tblt.w\t2ce8 <__gridxc_cell_MOD_cellxc+0x26d4>\n+\tmov\tr0, r3\n+\tstr.w\tr2, [r7, #636]\t@ 0x27c\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr2, [r7, #636]\t@ 0x27c\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tmls\tr3, r1, r0, r3\n+\tstr\tr3, [r2, #0]\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #0\n-\tble.n\t2b28 <__gridxc_cell_MOD_cellxc+0x254c>\n-\tldrd\tsl, r3, [r9]\n-\tldr.w\tr0, [r7, #652]\t@ 0x28c\n-\tldr.w\tr1, [r9, #8]\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tadd\tr0, sl\n-\tadds\tr0, #1\n-\tvldr\td25, [lr, #-24]\t@ 0xffffffe8\n-\tvldr\td24, [lr, #-16]\n-\tvldr\td23, [lr, #-8]\n-\tmla\tr0, r1, r2, r0\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tvldr\td22, [r5]\n-\tvldr\td21, [fp]\n-\tmla\tr0, r3, r2, r0\n-\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n-\tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n-\tmla\tr3, r1, r2, r3\n-\tadd.w\tr1, r3, sl\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tmov.w\tsl, #1\n-\tadd.w\tr0, r3, r0, lsl #3\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n-\tadd.w\tr1, r3, r1, lsl #3\n-\tldrd\tr2, r3, [r7, #744]\t@ 0x2e8\n-\tadd.w\tsl, sl, #1\n-\tvldr\td16, [r2, #8]\n-\tadds\tr3, #24\n-\tvldr\td18, [r2]\n-\tcmp\tr4, sl\n-\tvldr\td17, [r3, #-16]\n-\tadd.w\tr2, r2, #24\n-\tvmul.f64\td16, d24, d16\n-\tvldr\td27, [r2, #-8]\n-\tvfma.f64\td16, d25, d18\n-\tvldr\td19, [r3, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td17, d24, d17\n-\tvldr\td20, [r0]\n-\tvldr\td26, [r3, #-8]\n-\tvfma.f64\td17, d25, d19\n-\tvldr\td18, [r1]\n-\tvfma.f64\td16, d23, d27\n-\tvnmul.f64\td20, d20, d15\n-\tvfma.f64\td17, d23, d26\n-\tvfma.f64\td22, d16, d20\n-\tvadd.f64\td16, d16, d17\n-\tvadd.f64\td18, d18, d16\n-\tvstr\td22, [r5]\n-\tvldmia\tr0!, {d16}\n-\tvstr\td18, [r1]\n-\tadd\tr1, r6\n-\tvnmul.f64\td16, d16, d15\n-\tvfma.f64\td21, d16, d17\n-\tvstr\td21, [fp]\n-\tbne.n\t2ab8 <__gridxc_cell_MOD_cellxc+0x24dc>\n-\tadd.w\tr8, r8, #1\n-\tadd.w\tlr, lr, #72\t@ 0x48\n-\tcmp.w\tr8, #4\n-\tbne.w\t2a12 <__gridxc_cell_MOD_cellxc+0x2436>\n-\tldrd\tr3, r2, [r7, #640]\t@ 0x280\n-\tadd.w\tip, ip, #4\n-\tldr.w\tr1, [r7, #628]\t@ 0x274\n-\tadds\tr2, #3\n+\tble.n\t2bf0 <__gridxc_cell_MOD_cellxc+0x25dc>\n+\tldr.w\tlr, [r8]\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n+\tldrd\tip, r3, [r8, #4]\n+\tadd\tr1, lr\n+\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tadds\tr1, #1\n+\tvldr\td1, [r9, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [r9, #-16]\n+\tvldr\td3, [r9, #-8]\n+\tmla\tr1, r3, r0, r1\n+\tldr.w\tr0, [r7, #712]\t@ 0x2c8\n+\tvldr\td4, [fp]\n+\tvldr\td5, [r5]\n+\tmul.w\tr3, r0, r3\n+\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tmla\tr3, ip, r0, r3\n+\tldr.w\tr0, [r7, #728]\t@ 0x2d8\n+\tadd\tr3, lr\n+\tmov.w\tlr, #1\n+\tmla\tr1, ip, r0, r1\n+\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tadd.w\tip, r0, r1, lsl #3\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tadd.w\tr0, r1, r3, lsl #3\n+\tldr.w\tr1, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tvldr\td7, [r1]\n+\tadd.w\tlr, lr, #1\n+\tvldr\td12, [r1, #8]\n \tadds\tr3, #24\n-\tcmp\tr2, #35\t@ 0x23\n-\tbne.w\t29fc <__gridxc_cell_MOD_cellxc+0x2420>\n-\tldr.w\tr8, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tvldr\td6, [r3, #-24]\t@ 0xffffffe8\n+\tadds\tr1, #24\n+\tvmul.f64\td7, d1, d7\n+\tvldr\td0, [r1, #-8]\n+\tvmla.f64\td7, d2, d12\n+\tvldr\td14, [r3, #-16]\n+\tvmul.f64\td6, d1, d6\n+\tvldr\td9, [ip]\n+\tvldr\td8, [r3, #-8]\n+\tcmp\tr4, lr\n+\tvmla.f64\td6, d2, d14\n+\tvldr\td12, [r0]\n+\tvmla.f64\td7, d3, d0\n+\tvmul.f64\td9, d11, d9\n+\tvmla.f64\td6, d3, d8\n+\tvmls.f64\td4, d9, d7\n+\tvadd.f64\td7, d7, d6\n+\tvadd.f64\td12, d12, d7\n+\tvstr\td4, [fp]\n+\tvldmia\tip!, {d7}\n+\tvstr\td12, [r0]\n+\tadd\tr0, r6\n+\tvmul.f64\td7, d11, d7\n+\tvmls.f64\td5, d7, d6\n+\tvstr\td5, [r5]\n+\tbne.n\t2b82 <__gridxc_cell_MOD_cellxc+0x256e>\n+\tadd.w\tsl, sl, #1\n+\tadd.w\tr9, r9, #72\t@ 0x48\n+\tcmp.w\tsl, #4\n+\tbne.w\t2acc <__gridxc_cell_MOD_cellxc+0x24b8>\n+\tldr.w\tr3, [r7, #620]\t@ 0x26c\n+\tmov\tip, r4\n+\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n+\tadds\tr2, #4\n+\tadds\tr3, #3\n+\tldr.w\tr0, [r7, #476]\t@ 0x1dc\n+\tadds\tr1, #24\n+\tcmp\tr3, #35\t@ 0x23\n+\tbne.w\t2ab0 <__gridxc_cell_MOD_cellxc+0x249c>\n+\tldr.w\tr9, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n \tmovs\tr2, #1\n-\tldr.w\tr1, [r7, #468]\t@ 0x1d4\n-\tadd.w\tr4, r8, r2\n-\tadd.w\tr9, r3, #8\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr1, [r7, #456]\t@ 0x1c8\n+\tadd.w\tr4, r9, r2\n+\tadd.w\tr8, r3, #8\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tmov\tr5, fp\n \tadd.w\tlr, r3, #8\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tadd.w\tr0, r3, #8\n \tmov\tfp, r0\n \tmov\tip, r1\n \tmov.w\tsl, #1\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tcmp.w\tr8, #0\n-\tble.n\t2bc0 <__gridxc_cell_MOD_cellxc+0x25e4>\n-\tvldr\td18, [ip]\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n+\tcmp.w\tr9, #0\n+\tble.n\t2c8c <__gridxc_cell_MOD_cellxc+0x2678>\n+\tvldr\td4, [ip]\n \tmov\tr6, lr\n-\tmov\tr1, r9\n+\tmov\tr1, r8\n \tmov\tr2, fp\n \tmovs\tr3, #1\n-\tvldr\td17, [r1, #-8]\n+\tvldr\td6, [r1, #-8]\n \tadds\tr3, #1\n-\tvldr\td19, [r6, #-8]\n+\tvldr\td5, [r6, #-8]\n \tadds\tr2, #24\n-\tvldr\td16, [r2, #-32]\t@ 0xffffffe0\n+\tvldr\td7, [r2, #-32]\t@ 0xffffffe0\n \tadds\tr1, #24\n \tadds\tr6, #24\n \tcmp\tr3, r4\n-\tvadd.f64\td17, d17, d19\n-\tvnmul.f64\td16, d16, d15\n-\tvfma.f64\td18, d17, d16\n-\tbne.n\t2b98 <__gridxc_cell_MOD_cellxc+0x25bc>\n-\tvstr\td18, [ip]\n+\tvadd.f64\td6, d6, d5\n+\tvmul.f64\td7, d11, d7\n+\tvmls.f64\td4, d6, d7\n+\tbne.n\t2c64 <__gridxc_cell_MOD_cellxc+0x2650>\n+\tvstr\td4, [ip]\n \tadd.w\tsl, sl, #1\n \tadd.w\tip, ip, #8\n \tadd.w\tfp, fp, #8\n \tcmp.w\tsl, #4\n-\tbne.n\t2b86 <__gridxc_cell_MOD_cellxc+0x25aa>\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadd.w\tr9, r9, #8\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tbne.n\t2c52 <__gridxc_cell_MOD_cellxc+0x263e>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd.w\tr8, r8, #8\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tadd.w\tlr, lr, #8\n \tadds\tr2, #1\n \tadds\tr1, #24\n \tcmp\tr2, #4\n-\tbne.n\t2b76 <__gridxc_cell_MOD_cellxc+0x259a>\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tbne.n\t2c42 <__gridxc_cell_MOD_cellxc+0x262e>\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n \tmov\tfp, r5\n \tstr.w\tr2, [r3, #548]\t@ 0x224\n-\tb.w\t237e <__gridxc_cell_MOD_cellxc+0x1da2>\n+\tb.w\t2424 <__gridxc_cell_MOD_cellxc+0x1e10>\n \tcmp\tr3, #0\n-\tble.w\t2a40 <__gridxc_cell_MOD_cellxc+0x2464>\n-\tsubs\tr2, r3, #1\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tsdiv\tr2, r2, r1\n-\tsubs\tr2, #1\n-\tb.n\t2a44 <__gridxc_cell_MOD_cellxc+0x2468>\n-\tadds\tr2, r3, #1\n-\tb.n\t2c00 <__gridxc_cell_MOD_cellxc+0x2624>\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tit\tgt\n+\taddgt.w\tr0, r3, #4294967295\t@ 0xffffffff\n+\tble.w\t2af8 <__gridxc_cell_MOD_cellxc+0x24e4>\n+\tstr.w\tr2, [r7, #636]\t@ 0x27c\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr2, [r7, #636]\t@ 0x27c\n+\tsubs\tr0, #1\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tb.n\t2b0e <__gridxc_cell_MOD_cellxc+0x24fa>\n+\tadds\tr0, r3, #1\n+\tb.n\t2cd0 <__gridxc_cell_MOD_cellxc+0x26bc>\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n \tmovs\tr0, #0\n-\tvldr\td20, [r3]\n+\tvldr\td7, [r3]\n \tcmp\tr2, r0\n-\tvldr\td19, [r3, #8]\n+\tvldr\td2, [r3, #8]\n \tadd.w\tr0, r0, #1\n-\tvldr\td16, [r3, #16]\n+\tvldr\td1, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tvmul.f64\td20, d20, d18\n-\tvmul.f64\td19, d19, d18\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td20, [r3, #-24]\t@ 0xffffffe8\n-\tvstr\td19, [r3, #-16]\n-\tvstr\td16, [r3, #-8]\n-\tbne.n\t2c16 <__gridxc_cell_MOD_cellxc+0x263a>\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td2, d2, d5\n+\tvmul.f64\td1, d1, d5\n+\tvstr\td7, [r3, #-24]\t@ 0xffffffe8\n+\tvstr\td2, [r3, #-16]\n+\tvstr\td1, [r3, #-8]\n+\tbne.n\t2cf2 <__gridxc_cell_MOD_cellxc+0x26de>\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tmovs\tr0, #0\n-\tvldr\td20, [r3]\n+\tvldr\td7, [r3]\n \tcmp\tr2, r0\n-\tvldr\td19, [r3, #8]\n+\tvldr\td2, [r3, #8]\n \tadd.w\tr0, r0, #1\n-\tvldr\td16, [r3, #16]\n+\tvldr\td1, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tvmul.f64\td20, d20, d17\n-\tvmul.f64\td19, d19, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td20, [r3, #-24]\t@ 0xffffffe8\n-\tvstr\td19, [r3, #-16]\n-\tvstr\td16, [r3, #-8]\n-\tbne.n\t2c4c <__gridxc_cell_MOD_cellxc+0x2670>\n-\tb.w\t2186 <__gridxc_cell_MOD_cellxc+0x1baa>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tldr.w\tr1, [r7, #564]\t@ 0x234\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td2, d2, d6\n+\tvmul.f64\td1, d1, d6\n+\tvstr\td7, [r3, #-24]\t@ 0xffffffe8\n+\tvstr\td2, [r3, #-16]\n+\tvstr\td1, [r3, #-8]\n+\tbne.n\t2d28 <__gridxc_cell_MOD_cellxc+0x2714>\n+\tb.w\t220a <__gridxc_cell_MOD_cellxc+0x1bf6>\n+\tldr.w\tr2, [r7, #436]\t@ 0x1b4\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n \tldr.w\tr5, [r7, #572]\t@ 0x23c\n-\tmul.w\tr1, r1, r3\n+\tmul.w\tr1, r1, r2\n \tcmp\tr5, #0\n-\tbeq.w\t2376 <__gridxc_cell_MOD_cellxc+0x1d9a>\n-\tldr.w\tr0, [r7, #620]\t@ 0x26c\n-\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tbeq.w\t241c <__gridxc_cell_MOD_cellxc+0x1e08>\n+\tldr.w\tr0, [r7, #568]\t@ 0x238\n+\tmov\tr2, r3\n+\tldr.w\tr3, [r7, #408]\t@ 0x198\n \tldr\tr4, [r7, #104]\t@ 0x68\n \tadd\tr3, r0\n \tadd\tr3, r4\n \tlsls\tr4, r0, #3\n \tadd\tr3, r1\n-\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n \tadd.w\tr3, r1, r3, lsl #3\n-\tldr.w\tr1, [r7, #408]\t@ 0x198\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tadd\tr3, r1\n-\tldrd\tr0, r1, [r7, #260]\t@ 0x104\n+\tldrd\tr0, r1, [r7, #252]\t@ 0xfc\n \tadds\tr2, #1\n-\tvldr\td18, [r3]\n+\tvldr\td5, [r3]\n \tcmp\tr5, r2\n-\tvldmia\tr0!, {d16}\n-\tvldmia\tr1!, {d17}\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvldmia\tr0!, {d7}\n+\tvldmia\tr1!, {d6}\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r4\n-\tbne.n\t2cba <__gridxc_cell_MOD_cellxc+0x26de>\n-\tb.w\t2376 <__gridxc_cell_MOD_cellxc+0x1d9a>\n-\tldr\tr5, [r7, #28]\n+\tbne.n\t2d98 <__gridxc_cell_MOD_cellxc+0x2784>\n+\tb.w\t241c <__gridxc_cell_MOD_cellxc+0x1e08>\n+\tldr.w\tr4, [pc, #2516]\t@ 3794 <__gridxc_cell_MOD_cellxc+0x3180>\n+\tadd.w\tr8, r7, #1224\t@ 0x4c8\n+\tstr.w\tr8, [r7, #688]\t@ 0x2b0\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr9, r7, #1248\t@ 0x4e0\n-\tldr.w\tr3, [r5, #628]\t@ 0x274\n-\tldr.w\tr1, [r5, #624]\t@ 0x270\n+\tadd\tr4, pc\n+\tadd.w\tr1, r4, #216\t@ 0xd8\n+\taddw\tr0, r4, #1140\t@ 0x474\n+\tldr.w\tr3, [r4, #628]\t@ 0x274\n+\tldr.w\tr5, [r4, #624]\t@ 0x270\n \trsb\tr3, r3, #1\n-\tldr.w\tr4, [r5, #164]\t@ 0xa4\n-\tstr.w\tr4, [r7, #428]\t@ 0x1ac\n-\tadd.w\tr4, r5, #216\t@ 0xd8\n-\tmov\tr8, r4\n-\tstr.w\tr1, [r7, #412]\t@ 0x19c\n-\tmul.w\tr0, r1, r3\n-\tmov\tr1, r4\n-\tldr\tr4, [r5, #20]\n-\tstr\tr4, [r7, #44]\t@ 0x2c\n-\tldr\tr4, [r5, #92]\t@ 0x5c\n-\tstr\tr4, [r7, #64]\t@ 0x40\n-\tldr.w\tr4, [r5, #1016]\t@ 0x3f8\n-\tstr\tr4, [r7, #60]\t@ 0x3c\n-\tldr.w\tr4, [r5, #1088]\t@ 0x440\n-\tstr\tr4, [r7, #40]\t@ 0x28\n-\tldr.w\tr4, [r5, #144]\t@ 0x90\n-\tstr.w\tr4, [r7, #252]\t@ 0xfc\n-\tldr.w\tr4, [r5, #148]\t@ 0x94\n-\tstr.w\tr4, [r7, #248]\t@ 0xf8\n-\tldr.w\tr4, [r5, #168]\t@ 0xa8\n-\tstr.w\tr4, [r7, #340]\t@ 0x154\n-\tldr.w\tr4, [r5, #180]\t@ 0xb4\n-\tstr.w\tr4, [r7, #336]\t@ 0x150\n-\tldr.w\tr4, [r5, #192]\t@ 0xc0\n-\tstr.w\tr4, [r7, #332]\t@ 0x14c\n-\tldr.w\tr4, [r5, #584]\t@ 0x248\n-\tldr.w\tr3, [r5, #204]\t@ 0xcc\n-\tstr.w\tr4, [r7, #328]\t@ 0x148\n-\tldr.w\tr4, [r5, #592]\t@ 0x250\n-\tstr.w\tr0, [r7, #300]\t@ 0x12c\n+\tldr.w\tr6, [r4, #164]\t@ 0xa4\n+\tstr.w\tr6, [r7, #316]\t@ 0x13c\n+\tstr.w\tr5, [r7, #240]\t@ 0xf0\n+\tmul.w\tr3, r5, r3\n+\tstr.w\tr3, [r7, #284]\t@ 0x11c\n+\tldr.w\tr3, [r4, #204]\t@ 0xcc\n+\tstr.w\tr3, [r7, #404]\t@ 0x194\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r4, #92]\t@ 0x5c\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tldr.w\tr3, [r4, #1016]\t@ 0x3f8\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tldr.w\tr3, [r4, #1088]\t@ 0x440\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tldr.w\tr3, [r4, #144]\t@ 0x90\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tldr.w\tr3, [r4, #148]\t@ 0x94\n \tstr.w\tr3, [r7, #244]\t@ 0xf4\n-\tldr\tr0, [r7, #24]\n-\tstr.w\tr4, [r7, #324]\t@ 0x144\n-\tldr.w\tr4, [r5, #588]\t@ 0x24c\n-\tstr.w\tr4, [r7, #320]\t@ 0x140\n-\tldr.w\tr4, [r5, #604]\t@ 0x25c\n-\tstr.w\tr4, [r7, #316]\t@ 0x13c\n-\tldr.w\tr4, [r5, #600]\t@ 0x258\n-\tstr.w\tr4, [r7, #312]\t@ 0x138\n-\tldr.w\tr4, [r5, #616]\t@ 0x268\n-\tstr.w\tr4, [r7, #308]\t@ 0x134\n-\tldr.w\tr4, [r5, #612]\t@ 0x264\n-\tstr.w\tr4, [r7, #304]\t@ 0x130\n-\tldr.w\tr4, [r7, #428]\t@ 0x1ac\n-\tstr.w\tr9, [r7, #676]\t@ 0x2a4\n-\tmul.w\tr4, r3, r4\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tstr.w\tr4, [r7, #268]\t@ 0x10c\n-\tmov\tr4, r5\n-\tnegs\tr3, r3\n+\tldr.w\tr3, [r4, #168]\t@ 0xa8\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tldr.w\tr3, [r4, #180]\t@ 0xb4\n+\tstr.w\tr3, [r7, #324]\t@ 0x144\n+\tldr.w\tr3, [r4, #192]\t@ 0xc0\n+\tstr.w\tr3, [r7, #320]\t@ 0x140\n+\tldr.w\tr3, [r4, #584]\t@ 0x248\n+\tstr.w\tr3, [r7, #312]\t@ 0x138\n+\tldr.w\tr3, [r4, #592]\t@ 0x250\n+\tstr.w\tr3, [r7, #308]\t@ 0x134\n+\tldr.w\tr3, [r4, #588]\t@ 0x24c\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tldr.w\tr3, [r4, #604]\t@ 0x25c\n+\tstr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr3, [r4, #600]\t@ 0x258\n \tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r4, #616]\t@ 0x268\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r4, #612]\t@ 0x264\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tldr.w\tr3, [r7, #404]\t@ 0x194\n+\tmul.w\tr3, r3, r6\n+\tmovs\tr6, #1\n+\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tnegs\tr3, r5\n+\tstr.w\tr3, [r7, #280]\t@ 0x118\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr1, [r5, #236]\t@ 0xec\n-\tstr.w\tr1, [r5, #1160]\t@ 0x488\n+\tldr.w\tr3, [r4, #236]\t@ 0xec\n \tmovs\tr2, #72\t@ 0x48\n-\taddw\tr0, r5, #1212\t@ 0x4bc\n-\tstr.w\tr1, [r7, #444]\t@ 0x1bc\n-\tadd.w\tr1, r5, #288\t@ 0x120\n+\tadd.w\tr1, r4, #288\t@ 0x120\n+\taddw\tr0, r4, #1212\t@ 0x4bc\n+\tstr.w\tr3, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr3, [r4, #1160]\t@ 0x488\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr1, [r5, #308]\t@ 0x134\n-\tstr.w\tr1, [r5, #1232]\t@ 0x4d0\n+\tldr.w\tr3, [r4, #308]\t@ 0x134\n \tmovs\tr2, #72\t@ 0x48\n-\taddw\tr0, r5, #2044\t@ 0x7fc\n-\tstr.w\tr1, [r7, #492]\t@ 0x1ec\n-\tadd.w\tr1, r5, #708\t@ 0x2c4\n+\tadd.w\tr1, r4, #708\t@ 0x2c4\n+\tadd.w\tr0, r4, #2040\t@ 0x7f8\n+\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr3, [r4, #1232]\t@ 0x4d0\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr1, [r5, #728]\t@ 0x2d8\n-\tstr.w\tr1, [r5, #2064]\t@ 0x810\n-\taddw\tr0, r5, #2116\t@ 0x844\n-\tstr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr3, [r4, #728]\t@ 0x2d8\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r5, #780\t@ 0x30c\n-\tmovs\tr5, #1\n+\tadd.w\tr1, r4, #780\t@ 0x30c\n+\tadd.w\tr0, r4, #2112\t@ 0x840\n+\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr3, [r4, #2060]\t@ 0x80c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr.w\tr3, [r4, #800]\t@ 0x320\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tstr\tr6, [r7, #4]\n-\tmov\tr6, r5\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tstr.w\tr3, [r7, #640]\t@ 0x280\n-\tsub.w\tr3, r8, #216\t@ 0xd8\n-\tstr.w\tr3, [r7, #652]\t@ 0x28c\n-\taddw\tr3, r8, #1804\t@ 0x70c\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tstr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tmov\tr3, r6\n+\tldr.w\tr6, [r7, #792]\t@ 0x318\n \tmov.w\tlr, #24\n-\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tstr.w\tr2, [r3, #2136]\t@ 0x858\n-\tldr.w\tr2, [r3, #2180]\t@ 0x884\n-\tldr.w\tr0, [r3, #2176]\t@ 0x880\n-\tmla\tlr, lr, r6, r5\n-\tldr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tmvn.w\tsl, #2\n+\tstr.w\tr2, [r4, #2132]\t@ 0x854\n+\tldr.w\tr2, [r4, #2176]\t@ 0x880\n+\tldr.w\tr0, [r4, #2172]\t@ 0x87c\n+\tmla\tlr, lr, r3, r6\n+\tldr.w\tr6, [r7, #664]\t@ 0x298\n \trsb\tr1, r2, #1\n-\tldr.w\tr2, [r3, #2108]\t@ 0x83c\n-\tldr.w\tr4, [r3, #1200]\t@ 0x4b0\n-\tldr.w\tr5, [r5, #504]\t@ 0x1f8\n+\tldr.w\tr2, [r4, #2104]\t@ 0x838\n+\tldr.w\tr5, [r4, #1200]\t@ 0x4b0\n+\tldr.w\tr6, [r6, #504]\t@ 0x1f8\n \tmul.w\tr1, r0, r1\n-\tstr.w\tr5, [r7, #644]\t@ 0x284\n+\tstr.w\tr6, [r7, #656]\t@ 0x290\n \trsb\tr2, r2, #1\n-\tldr.w\tr5, [r3, #1212]\t@ 0x4bc\n-\tstr.w\tr1, [r7, #348]\t@ 0x15c\n-\tstr.w\tr5, [r7, #240]\t@ 0xf0\n-\tldr.w\tr1, [r3, #2104]\t@ 0x838\n-\tldr.w\tr5, [r3, #1216]\t@ 0x4c0\n-\tstr.w\tr5, [r7, #236]\t@ 0xec\n-\tldr.w\tr5, [r3, #1236]\t@ 0x4d4\n-\tstr.w\tr5, [r7, #388]\t@ 0x184\n+\tldr.w\tr6, [r4, #1212]\t@ 0x4bc\n+\tstr.w\tr1, [r7, #336]\t@ 0x150\n+\tstr.w\tr6, [r7, #236]\t@ 0xec\n+\tldr.w\tr1, [r4, #2100]\t@ 0x834\n+\tldr.w\tr6, [r4, #1216]\t@ 0x4c0\n+\tstr.w\tr6, [r7, #232]\t@ 0xe8\n+\tldr.w\tr6, [r4, #1236]\t@ 0x4d4\n+\tstr.w\tr6, [r7, #376]\t@ 0x178\n \tmul.w\tr2, r1, r2\n-\tldr.w\tr5, [r3, #1248]\t@ 0x4e0\n-\tstr.w\tr5, [r7, #384]\t@ 0x180\n-\tldr.w\tr5, [r3, #1260]\t@ 0x4ec\n-\tstr.w\tr5, [r7, #380]\t@ 0x17c\n-\tldr.w\tr5, [r3, #2116]\t@ 0x844\n+\tldr.w\tr6, [r4, #1248]\t@ 0x4e0\n+\tstr.w\tr6, [r7, #372]\t@ 0x174\n+\tldr.w\tr6, [r4, #1260]\t@ 0x4ec\n+\tstr.w\tr6, [r7, #368]\t@ 0x170\n+\tldr.w\tr6, [r4, #2112]\t@ 0x840\n \tstr.w\tr2, [r7, #160]\t@ 0xa0\n-\tstr.w\tr5, [r7, #376]\t@ 0x178\n-\tldr.w\tr2, [r3, #1272]\t@ 0x4f8\n-\tldr.w\tr5, [r3, #2144]\t@ 0x860\n-\tstr.w\tr0, [r7, #228]\t@ 0xe4\n+\tstr.w\tr6, [r7, #364]\t@ 0x16c\n+\tldr.w\tr2, [r4, #1272]\t@ 0x4f8\n+\tldr.w\tr6, [r4, #2140]\t@ 0x85c\n+\tstr.w\tr2, [r7, #228]\t@ 0xe4\n+\tstr\tr5, [r7, #116]\t@ 0x74\n+\tstr.w\tr0, [r7, #224]\t@ 0xe0\n \tstr\tr1, [r7, #112]\t@ 0x70\n-\tstr.w\tr2, [r7, #232]\t@ 0xe8\n-\tstr\tr4, [r7, #116]\t@ 0x74\n-\tstr.w\tr5, [r7, #372]\t@ 0x174\n-\tldr.w\tr5, [r3, #2140]\t@ 0x85c\n-\tstr.w\tr5, [r7, #368]\t@ 0x170\n-\tldr.w\tr5, [r3, #2156]\t@ 0x86c\n-\tstr.w\tr5, [r7, #364]\t@ 0x16c\n-\tldr.w\tr5, [r3, #2152]\t@ 0x868\n-\tstr.w\tr5, [r7, #360]\t@ 0x168\n-\tldr.w\tr5, [r3, #2168]\t@ 0x878\n-\tstr.w\tr5, [r7, #356]\t@ 0x164\n-\tldr.w\tr5, [r3, #2164]\t@ 0x874\n-\tstr.w\tr5, [r7, #352]\t@ 0x160\n-\tldr.w\tr5, [r3, #1140]\t@ 0x474\n-\tstr\tr5, [r7, #124]\t@ 0x7c\n-\tldr.w\tr5, [r3, #1144]\t@ 0x478\n-\tstr\tr5, [r7, #120]\t@ 0x78\n-\tldr.w\tr5, [r3, #1164]\t@ 0x48c\n-\tstr.w\tr5, [r7, #200]\t@ 0xc8\n-\tldr.w\tr5, [r3, #1176]\t@ 0x498\n-\tstr.w\tr5, [r7, #196]\t@ 0xc4\n-\tldr.w\tr5, [r3, #1188]\t@ 0x4a4\n-\tstr.w\tr5, [r7, #192]\t@ 0xc0\n-\tldr.w\tr5, [r3, #2044]\t@ 0x7fc\n-\tstr.w\tr5, [r7, #188]\t@ 0xbc\n-\tldr.w\tr5, [r3, #2072]\t@ 0x818\n-\tstr.w\tr5, [r7, #184]\t@ 0xb8\n-\tldr.w\tr5, [r3, #2068]\t@ 0x814\n-\tstr.w\tr5, [r7, #180]\t@ 0xb4\n-\tldr.w\tr5, [r3, #2084]\t@ 0x824\n-\tstr.w\tr5, [r7, #176]\t@ 0xb0\n-\tldr.w\tr5, [r3, #2080]\t@ 0x820\n-\tstr.w\tr5, [r7, #172]\t@ 0xac\n-\tldr.w\tr5, [r3, #2096]\t@ 0x830\n-\tstr.w\tr5, [r7, #168]\t@ 0xa8\n-\tldr.w\tr3, [r3, #2092]\t@ 0x82c\n-\tstr.w\tr3, [r7, #164]\t@ 0xa4\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr6, [r7, #360]\t@ 0x168\n+\tldr.w\tr6, [r4, #2136]\t@ 0x858\n+\tstr.w\tr6, [r7, #356]\t@ 0x164\n+\tldr.w\tr6, [r4, #2152]\t@ 0x868\n+\tstr.w\tr6, [r7, #352]\t@ 0x160\n+\tldr.w\tr6, [r4, #2148]\t@ 0x864\n+\tstr.w\tr6, [r7, #348]\t@ 0x15c\n+\tldr.w\tr6, [r4, #2164]\t@ 0x874\n+\tstr.w\tr6, [r7, #344]\t@ 0x158\n+\tldr.w\tr6, [r4, #2160]\t@ 0x870\n+\tstr.w\tr6, [r7, #340]\t@ 0x154\n+\tldr.w\tr6, [r4, #1140]\t@ 0x474\n+\tstr\tr6, [r7, #124]\t@ 0x7c\n+\tldr.w\tr6, [r4, #1144]\t@ 0x478\n+\tstr\tr6, [r7, #120]\t@ 0x78\n+\tldr.w\tr6, [r4, #1164]\t@ 0x48c\n+\tstr.w\tr6, [r7, #200]\t@ 0xc8\n+\tldr.w\tr6, [r4, #1176]\t@ 0x498\n+\tstr.w\tr6, [r7, #196]\t@ 0xc4\n+\tldr.w\tr6, [r4, #1188]\t@ 0x4a4\n+\tstr.w\tr6, [r7, #192]\t@ 0xc0\n+\tldr.w\tr6, [r4, #2040]\t@ 0x7f8\n+\tstr.w\tr6, [r7, #188]\t@ 0xbc\n+\tldr.w\tr6, [r4, #2068]\t@ 0x814\n+\tstr.w\tr6, [r7, #184]\t@ 0xb8\n+\tldr.w\tr6, [r4, #2064]\t@ 0x810\n+\tstr.w\tr6, [r7, #180]\t@ 0xb4\n+\tldr.w\tr6, [r4, #2080]\t@ 0x820\n+\tstr.w\tr6, [r7, #176]\t@ 0xb0\n+\tldr.w\tr6, [r4, #2076]\t@ 0x81c\n+\tstr.w\tr6, [r7, #172]\t@ 0xac\n+\tldr.w\tr6, [r4, #2092]\t@ 0x82c\n+\tstr.w\tr6, [r7, #168]\t@ 0xa8\n+\tldr.w\tr6, [r4, #2088]\t@ 0x828\n+\tstr.w\tr6, [r7, #164]\t@ 0xa4\n+\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n+\tstr\tr3, [r7, #4]\n+\tstr.w\tsl, [r7, #784]\t@ 0x310\n+\tstr\tr4, [r7, #0]\n+\tmul.w\tr2, r6, r2\n+\tstr.w\tr2, [r7, #380]\t@ 0x17c\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr.w\tr9, [r2]\n+\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n+\tmul.w\tr2, r2, r5\n \tldr.w\tr5, [r7, #624]\t@ 0x270\n-\tstr\tr6, [r7, #0]\n-\tmul.w\tr3, r3, r2\n-\tstr.w\tr3, [r7, #256]\t@ 0x100\n-\tldr\tr3, [r7, #4]\n-\tldr.w\tr8, [r3]\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tmul.w\tr3, r3, r4\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tnegs\tr3, r0\n-\tstr.w\tr3, [r7, #344]\t@ 0x158\n-\tnegs\tr3, r1\n-\tstr.w\tr3, [r7, #156]\t@ 0x9c\n-\tmvn.w\tr3, #2\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r9]\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n-\tstr.w\tr3, [r9, #4]\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr3, [r9, #8]\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr2, [r7, #152]\t@ 0x98\n+\tldr.w\tr2, [pc, #1896]\t@ 3798 <__gridxc_cell_MOD_cellxc+0x3184>\n+\tadd\tr2, pc\n+\tstr.w\tr2, [r7, #636]\t@ 0x27c\n+\tnegs\tr2, r0\n+\tstr.w\tr2, [r7, #332]\t@ 0x14c\n+\tnegs\tr2, r1\n+\tstr.w\tr2, [r7, #156]\t@ 0x9c\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r8]\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr3, [r8, #4]\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr3, [r8, #8]\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tldr\tr3, [r2, #0]\n \tadd\tr3, r1\n \tstr\tr3, [r2, #0]\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n \tcmp\tr3, r2\n-\tblt.w\t3252 <__gridxc_cell_MOD_cellxc+0x2c76>\n-\tldr.w\tr2, [r7, #640]\t@ 0x280\n-\tldrd\tr0, r1, [r9]\n+\tblt.w\t3324 <__gridxc_cell_MOD_cellxc+0x2d10>\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tldrd\tr0, r1, [r8]\n \tldr.w\tr2, [r2, #508]\t@ 0x1fc\n-\tldr.w\tr4, [r9, #8]\n+\tldr.w\tr4, [r8, #8]\n \tcmp\tr3, r2\n-\tble.w\t31b2 <__gridxc_cell_MOD_cellxc+0x2bd6>\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n-\tcmp.w\tr8, #0\n-\tldr.w\tr3, [r7, #236]\t@ 0xec\n+\tble.w\t3284 <__gridxc_cell_MOD_cellxc+0x2c70>\n+\tldr.w\tr2, [r7, #376]\t@ 0x178\n+\tcmp.w\tr9, #0\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n \tmla\tr3, r0, r2, r3\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n+\tldr.w\tr2, [r7, #372]\t@ 0x174\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r7, #380]\t@ 0x17c\n+\tldr.w\tr2, [r7, #368]\t@ 0x170\n \tmla\tr3, r4, r2, r3\n-\tble.n\t3008 <__gridxc_cell_MOD_cellxc+0x2a2c>\n-\tldr.w\tr2, [r7, #232]\t@ 0xe8\n-\tldr.w\tr6, [r7, #492]\t@ 0x1ec\n+\tble.n\t30d8 <__gridxc_cell_MOD_cellxc+0x2ac4>\n+\tldr.w\tr2, [r7, #228]\t@ 0xe4\n+\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #240]\t@ 0xf0\n-\tldr.w\tip, [r7, #256]\t@ 0x100\n+\tldr.w\tr2, [r7, #236]\t@ 0xec\n+\tldr.w\tip, [r7, #380]\t@ 0x17c\n \tmla\tr3, r6, r3, r2\n-\tldr.w\tr6, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n \tmovs\tr2, #0\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n \tadd\tr3, ip\n-\tcmp\tr8, r2\n-\tvstmia\tr6!, {d16}\n-\tbne.n\t2ff8 <__gridxc_cell_MOD_cellxc+0x2a1c>\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tldr.w\tr2, [r7, #376]\t@ 0x178\n+\tcmp\tr9, r2\n+\tvstmia\tr6!, {d7}\n+\tbne.n\t30c8 <__gridxc_cell_MOD_cellxc+0x2ab4>\n+\tldr.w\tr3, [r7, #352]\t@ 0x160\n+\tldr.w\tr2, [r7, #364]\t@ 0x16c\n \tsubs\tr1, r1, r3\n-\tldr.w\tr3, [r7, #372]\t@ 0x174\n-\tldr.w\tsl, [r7, #228]\t@ 0xe4\n+\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tldr.w\tsl, [r7, #476]\t@ 0x1dc\n \tsubs\tr0, r0, r3\n-\tldr.w\tr3, [r7, #356]\t@ 0x164\n+\tldr.w\tr3, [r7, #344]\t@ 0x158\n \tsubs\tr4, r4, r3\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tldr.w\tr3, [r7, #348]\t@ 0x15c\n \tmul.w\tr1, r3, r1\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tldr.w\tr3, [r7, #356]\t@ 0x164\n \tmla\tr1, r3, r0, r1\n-\tldr.w\tr3, [r7, #352]\t@ 0x160\n+\tldr.w\tr3, [r7, #340]\t@ 0x154\n \tmla\tr1, r3, r4, r1\n-\tldr.w\tr3, [r7, #348]\t@ 0x15c\n+\tldr.w\tr3, [r7, #336]\t@ 0x150\n \tadds\tr3, r1, r3\n \tadd.w\tr3, r2, r3, lsl #3\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #332]\t@ 0x14c\n \tstr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n-\tcmp.w\tr8, #0\n-\tvstr\td16, [r3]\n+\tldr.w\tr1, [r7, #636]\t@ 0x27c\n+\tmovs\tr2, #0\n \tmovw\tr3, #769\t@ 0x301\n-\tstrh.w\tr3, [r2, #2024]\t@ 0x7e8\n-\tble.n\t3114 <__gridxc_cell_MOD_cellxc+0x2b38>\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tadd.w\tr6, r8, #1\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tcmp\tr9, r2\n+\tstr.w\tr2, [r1, #2020]\t@ 0x7e4\n+\tstr.w\tr2, [r1, #2016]\t@ 0x7e0\n+\tstrh.w\tr3, [r1, #2020]\t@ 0x7e4\n+\tble.n\t31e0 <__gridxc_cell_MOD_cellxc+0x2bcc>\n+\tldrd\tr3, r2, [r7, #728]\t@ 0x2d8\n+\tadd.w\tr6, r9, #1\n+\tldr.w\tr4, [r7, #720]\t@ 0x2d0\n \tmovs\tr0, #1\n-\tadd.w\tr1, r3, sl\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n-\tvldr\td23, [lr, #-24]\t@ 0xffffffe8\n-\tvldr\td22, [lr, #-16]\n-\tmla\tr1, r3, r1, r2\n-\tvldr\td21, [lr, #-8]\n-\tmul.w\tip, r3, sl\n-\tldrd\tr2, r3, [r7, #744]\t@ 0x2e8\n+\tadds\tr1, r2, r3\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tmul.w\tip, sl, r3\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tvldr\td2, [lr, #-24]\t@ 0xffffffe8\n+\tvldr\td3, [lr, #-16]\n+\tmla\tr1, sl, r1, r2\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tvldr\td4, [lr, #-8]\n+\tvldr\td6, [r2, #8]\n \tadds\tr0, #1\n-\tvldr\td17, [r2, #8]\n-\tadds\tr3, #24\n-\tvldr\td16, [r3, #-16]\n+\tvldr\td7, [r3, #8]\n \tadds\tr2, #24\n-\tvldr\td19, [r2, #-24]\t@ 0xffffffe8\n+\tvldr\td8, [r3]\n \tcmp\tr0, r6\n-\tvldr\td18, [r3, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td17, d22, d17\n-\tvmul.f64\td16, d22, d16\n-\tvldr\td25, [r2, #-8]\n-\tvfma.f64\td17, d19, d23\n-\tvldr\td24, [r3, #-8]\n-\tvfma.f64\td16, d18, d23\n-\tvldmia\tr4!, {d18}\n-\tvldr\td20, [r5]\n-\tvldr\td19, [fp]\n-\tvfma.f64\td17, d25, d21\n-\tvnmul.f64\td18, d15, d18\n-\tvfma.f64\td16, d24, d21\n-\tvfma.f64\td20, d17, d18\n-\tvfma.f64\td19, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td20, [r5]\n-\tvstr\td19, [fp]\n-\tvldr\td17, [r1]\n-\tvadd.f64\td17, d17, d16\n-\tvstr\td17, [r1]\n+\tvldr\td5, [r2, #-24]\t@ 0xffffffe8\n+\tvmul.f64\td6, d3, d6\n+\tvmul.f64\td7, d3, d7\n+\tvldr\td1, [r3, #16]\n+\tvmla.f64\td7, d2, d8\n+\tvldr\td0, [r2, #-8]\n+\tvmla.f64\td6, d2, d5\n+\tvldmia\tr4!, {d5}\n+\tvldr\td8, [fp]\n+\tadd.w\tr3, r3, #24\n+\tvldr\td9, [r5]\n+\tvmla.f64\td7, d4, d1\n+\tvmul.f64\td5, d5, d11\n+\tvmla.f64\td6, d4, d0\n+\tvmls.f64\td9, d5, d7\n+\tvmls.f64\td8, d5, d6\n+\tvadd.f64\td6, d7, d6\n+\tvstr\td9, [r5]\n+\tvstr\td8, [fp]\n+\tvldr\td7, [r1]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r1]\n \tadd\tr1, ip\n-\tbne.n\t30a8 <__gridxc_cell_MOD_cellxc+0x2acc>\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tbne.n\t3172 <__gridxc_cell_MOD_cellxc+0x2b5e>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tadd.w\tlr, lr, #72\t@ 0x48\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n \tcmp\tr3, #4\n-\tbne.w\t2f74 <__gridxc_cell_MOD_cellxc+0x2998>\n-\tldr.w\tr3, [r7, #640]\t@ 0x280\n-\tldr\tr6, [r7, #0]\n-\tadds\tr3, #8\n-\tstr.w\tr3, [r7, #640]\t@ 0x280\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tadds\tr6, #1\n-\tcmp\tr6, #4\n-\tadd.w\tr3, r3, #4\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tbeq.w\t331c <__gridxc_cell_MOD_cellxc+0x2d40>\n-\tcmp\tr6, #2\n-\tbeq.w\t3356 <__gridxc_cell_MOD_cellxc+0x2d7a>\n-\tldr.w\tr4, [pc, #1348]\t@ 3694 <__gridxc_cell_MOD_cellxc+0x30b8>\n+\tbne.w\t3044 <__gridxc_cell_MOD_cellxc+0x2a30>\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tmov\tr1, sl\n+\tldr\tr3, [r7, #4]\n+\tadds\tr2, #8\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tadds\tr3, #1\n+\tldr\tr4, [r7, #0]\n+\tcmp\tr3, #4\n+\tadd.w\tr2, r2, #4\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tbeq.w\t33ec <__gridxc_cell_MOD_cellxc+0x2dd8>\n+\tcmp\tr3, #2\n+\tbeq.w\t3428 <__gridxc_cell_MOD_cellxc+0x2e14>\n+\tldr\tr5, [r7, #24]\n \tmovs\tr2, #72\t@ 0x48\n-\tadd\tr4, pc\n-\tmov\tr1, r4\n-\taddw\tr0, r4, #1140\t@ 0x474\n+\tldr\tr0, [r7, #20]\n+\tmov\tr1, r5\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr2, #72\t@ 0x48\n-\tldr\tr5, [r7, #44]\t@ 0x2c\n-\tadds\tr1, r4, r2\n-\taddw\tr0, r4, #1212\t@ 0x4bc\n-\tstr.w\tr5, [r4, #1160]\t@ 0x488\n+\tadds\tr1, r5, r2\n+\tldr\tr6, [r7, #48]\t@ 0x30\n+\taddw\tr0, r5, #1212\t@ 0x4bc\n+\tstr.w\tr6, [r5, #1160]\t@ 0x488\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tadd.w\tr1, r5, #996\t@ 0x3e4\n+\tstr.w\tr2, [r5, #1232]\t@ 0x4d0\n+\tadd.w\tr0, r5, #2040\t@ 0x7f8\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r4, #996\t@ 0x3e4\n-\taddw\tr0, r4, #2044\t@ 0x7fc\n-\tstr.w\tr3, [r4, #1232]\t@ 0x4d0\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\taddw\tr1, r4, #1068\t@ 0x42c\n-\tstr.w\tr2, [r4, #2064]\t@ 0x810\n-\taddw\tr0, r4, #2116\t@ 0x844\n+\tmov\tr3, r5\n \tmovs\tr2, #72\t@ 0x48\n+\tldr\tr5, [r7, #44]\t@ 0x2c\n+\taddw\tr1, r3, #1068\t@ 0x42c\n+\tadd.w\tr0, r3, #2112\t@ 0x840\n+\tstr.w\tr5, [r3, #2060]\t@ 0x80c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr1, [r7, #40]\t@ 0x28\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n-\tstr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tstr.w\tr2, [r7, #432]\t@ 0x1b0\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tb.n\t2e20 <__gridxc_cell_MOD_cellxc+0x2844>\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n-\tcmp.w\tr8, #0\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tstr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tr5, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n+\tb.n\t2ee8 <__gridxc_cell_MOD_cellxc+0x28d4>\n+\tldr.w\tr2, [r7, #328]\t@ 0x148\n+\tcmp.w\tr9, #0\n+\tldr.w\tr3, [r7, #244]\t@ 0xf4\n \tmla\tr3, r0, r2, r3\n-\tldr.w\tr2, [r7, #336]\t@ 0x150\n+\tldr.w\tr2, [r7, #324]\t@ 0x144\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r7, #332]\t@ 0x14c\n+\tldr.w\tr2, [r7, #320]\t@ 0x140\n \tmla\tr3, r4, r2, r3\n-\tble.n\t3200 <__gridxc_cell_MOD_cellxc+0x2c24>\n-\tldr.w\tr2, [r7, #244]\t@ 0xf4\n-\tldr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tble.n\t32d2 <__gridxc_cell_MOD_cellxc+0x2cbe>\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n+\tldr.w\tr6, [r7, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #252]\t@ 0xfc\n-\tldr.w\tip, [r7, #268]\t@ 0x10c\n+\tldr.w\tr2, [r7, #248]\t@ 0xf8\n+\tldr.w\tip, [r7, #384]\t@ 0x180\n \tmla\tr3, r6, r3, r2\n-\tldr.w\tr6, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n \tmovs\tr2, #0\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n \tadd\tr3, ip\n-\tcmp\tr8, r2\n-\tvstmia\tr6!, {d16}\n-\tbne.n\t31f0 <__gridxc_cell_MOD_cellxc+0x2c14>\n-\tldr.w\tr3, [r7, #316]\t@ 0x13c\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tcmp\tr9, r2\n+\tvstmia\tr6!, {d7}\n+\tbne.n\t32c2 <__gridxc_cell_MOD_cellxc+0x2cae>\n+\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr2, [r7, #620]\t@ 0x26c\n \tsubs\tr1, r1, r3\n-\tldr.w\tr3, [r7, #324]\t@ 0x144\n-\tldr.w\tsl, [r7, #412]\t@ 0x19c\n-\tsubs\tr0, r0, r3\n \tldr.w\tr3, [r7, #308]\t@ 0x134\n+\tldr.w\tsl, [r7, #312]\t@ 0x138\n+\tsubs\tr0, r0, r3\n+\tldr.w\tr3, [r7, #292]\t@ 0x124\n \tsubs\tr4, r4, r3\n-\tldr.w\tr3, [r7, #312]\t@ 0x138\n+\tldr.w\tr3, [r7, #296]\t@ 0x128\n \tmul.w\tr1, r3, r1\n-\tldr.w\tr3, [r7, #320]\t@ 0x140\n-\tmla\tr1, r3, r0, r1\n \tldr.w\tr3, [r7, #304]\t@ 0x130\n+\tmla\tr1, r3, r0, r1\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n \tmla\tr1, r3, r4, r1\n-\tldr.w\tr3, [r7, #300]\t@ 0x12c\n+\tldr.w\tr3, [r7, #284]\t@ 0x11c\n \tadds\tr3, r1, r3\n \tadd.w\tr3, r2, r3, lsl #3\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #280]\t@ 0x118\n \tstr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #328]\t@ 0x148\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #296]\t@ 0x128\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tb.n\t3058 <__gridxc_cell_MOD_cellxc+0x2a7c>\n-\tldrd\tr4, r0, [r9]\n-\tcmp.w\tr8, #0\n+\tb.n\t3128 <__gridxc_cell_MOD_cellxc+0x2b14>\n+\tldrd\tr4, r0, [r8]\n+\tcmp.w\tr9, #0\n \tldr.w\tr2, [r7, #200]\t@ 0xc8\n \tldr\tr3, [r7, #120]\t@ 0x78\n-\tldr.w\tr6, [r9, #8]\n+\tldr.w\tr6, [r8, #8]\n \tmla\tr3, r4, r2, r3\n \tldr.w\tr2, [r7, #196]\t@ 0xc4\n \tmla\tr3, r0, r2, r3\n \tldr.w\tr2, [r7, #192]\t@ 0xc0\n \tmla\tr3, r6, r2, r3\n-\tble.n\t32a2 <__gridxc_cell_MOD_cellxc+0x2cc6>\n+\tble.n\t3374 <__gridxc_cell_MOD_cellxc+0x2d60>\n \tldr\tr2, [r7, #116]\t@ 0x74\n-\tldr.w\tr1, [r7, #444]\t@ 0x1bc\n+\tldr.w\tr1, [r7, #440]\t@ 0x1b8\n \tadd\tr3, r2\n \tldr\tr2, [r7, #124]\t@ 0x7c\n-\tldr.w\tip, [r7, #128]\t@ 0x80\n+\tldr.w\tip, [r7, #152]\t@ 0x98\n \tmla\tr3, r1, r3, r2\n-\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n \tmovs\tr2, #0\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n \tadd\tr3, ip\n-\tcmp\tr8, r2\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t3292 <__gridxc_cell_MOD_cellxc+0x2cb6>\n+\tcmp\tr9, r2\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t3364 <__gridxc_cell_MOD_cellxc+0x2d50>\n \tldr.w\tr3, [r7, #176]\t@ 0xb0\n \tldr.w\tr2, [r7, #188]\t@ 0xbc\n \tsubs\tr0, r0, r3\n \tldr.w\tr3, [r7, #184]\t@ 0xb8\n-\tldr.w\tsl, [r7, #112]\t@ 0x70\n+\tldr.w\tsl, [r7, #420]\t@ 0x1a4\n \tsubs\tr4, r4, r3\n \tldr.w\tr3, [r7, #168]\t@ 0xa8\n \tsubs\tr6, r6, r3\n \tldr.w\tr3, [r7, #172]\t@ 0xac\n \tmul.w\tr0, r3, r0\n \tldr.w\tr3, [r7, #180]\t@ 0xb4\n \tmla\tr0, r3, r4, r0\n \tldr.w\tr3, [r7, #164]\t@ 0xa4\n \tmla\tr0, r3, r6, r0\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tadds\tr3, r0, r3\n \tadd.w\tr3, r2, r3, lsl #3\n-\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tldr\tr3, [r7, #112]\t@ 0x70\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n \tldr.w\tr3, [r7, #156]\t@ 0x9c\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tb.n\t3058 <__gridxc_cell_MOD_cellxc+0x2a7c>\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tb.n\t3128 <__gridxc_cell_MOD_cellxc+0x2b14>\n \tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tvstr\td19, [fp]\n-\tvstr\td23, [r3]\n-\tldr\tr3, [pc, #916]\t@ (3698 <__gridxc_cell_MOD_cellxc+0x30bc>)\n+\tvstr\td1, [fp]\n+\tvstr\td2, [r3]\n+\tldr\tr3, [pc, #968]\t@ (379c <__gridxc_cell_MOD_cellxc+0x3188>)\n \tadd\tr3, pc\n \tldr.w\tr3, [r3, #564]\t@ 0x234\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n \tcmp\tr3, #0\n-\tbne.w\t2270 <__gridxc_cell_MOD_cellxc+0x1c94>\n+\tbne.w\t22ee <__gridxc_cell_MOD_cellxc+0x1cda>\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tb.w\t22f0 <__gridxc_cell_MOD_cellxc+0x1d14>\n-\tldr\tr3, [pc, #892]\t@ (369c <__gridxc_cell_MOD_cellxc+0x30c0>)\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n+\tb.w\t236e <__gridxc_cell_MOD_cellxc+0x1d5a>\n+\tldr\tr3, [pc, #944]\t@ (37a0 <__gridxc_cell_MOD_cellxc+0x318c>)\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n \tadd\tr3, pc\n \tstr.w\tr2, [r3, #2028]\t@ 0x7ec\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr2, [r3, #2012]\t@ 0x7dc\n \tldr.w\tr2, [r7, #732]\t@ 0x2dc\n \tstr.w\tr2, [r3, #2008]\t@ 0x7d8\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr2, [r3, #2004]\t@ 0x7d4\n \tmovs\tr2, #1\n-\tstr.w\tsl, [r3, #2032]\t@ 0x7f0\n-\tstr.w\tr2, [r3, #2036]\t@ 0x7f4\n+\tstr.w\tr1, [r3, #2024]\t@ 0x7e8\n+\tstr.w\tr2, [r3, #2032]\t@ 0x7f0\n \tmovs\tr2, #8\n-\tstr.w\tr8, [r3, #2040]\t@ 0x7f8\n-\tstr.w\tr2, [r3, #2016]\t@ 0x7e0\n-\tb.n\t2b52 <__gridxc_cell_MOD_cellxc+0x2576>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tb.w\t2722 <__gridxc_cell_MOD_cellxc+0x2146>\n-\tldr\tr4, [pc, #840]\t@ (36a0 <__gridxc_cell_MOD_cellxc+0x30c4>)\n+\tstr.w\tr9, [r3, #2036]\t@ 0x7f4\n+\tstr.w\tr2, [r3, #2012]\t@ 0x7dc\n+\tb.w\t2c1e <__gridxc_cell_MOD_cellxc+0x260a>\n+\tvldr\td7, [pc, #860]\t@ 3780 <__gridxc_cell_MOD_cellxc+0x316c>\n+\tb.w\t27ca <__gridxc_cell_MOD_cellxc+0x21b6>\n+\tldr\tr6, [pc, #888]\t@ (37a4 <__gridxc_cell_MOD_cellxc+0x3190>)\n \tmovs\tr2, #72\t@ 0x48\n-\tadd\tr4, pc\n-\tadd.w\tr1, r4, #360\t@ 0x168\n-\taddw\tr0, r4, #1140\t@ 0x474\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd\tr6, pc\n+\tadd.w\tr1, r6, #360\t@ 0x168\n+\taddw\tr0, r6, #1140\t@ 0x474\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr2, #72\t@ 0x48\n-\tldr.w\tr3, [r4, #380]\t@ 0x17c\n-\tadd.w\tr1, r4, #432\t@ 0x1b0\n-\taddw\tr0, r4, #1212\t@ 0x4bc\n-\tstr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tstr.w\tr3, [r4, #1160]\t@ 0x488\n+\tldr.w\tr3, [r6, #380]\t@ 0x17c\n+\tadd.w\tr1, r6, #432\t@ 0x1b0\n+\taddw\tr0, r6, #1212\t@ 0x4bc\n+\tstr.w\tr3, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr3, [r6, #1160]\t@ 0x488\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr3, [r4, #452]\t@ 0x1c4\n+\tldr.w\tr3, [r6, #452]\t@ 0x1c4\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r4, #852\t@ 0x354\n-\taddw\tr0, r4, #2044\t@ 0x7fc\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tstr.w\tr3, [r4, #1232]\t@ 0x4d0\n+\tadd.w\tr1, r6, #852\t@ 0x354\n+\tadd.w\tr0, r6, #2040\t@ 0x7f8\n+\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr3, [r6, #1232]\t@ 0x4d0\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr3, [r4, #872]\t@ 0x368\n+\tldr.w\tr3, [r6, #872]\t@ 0x368\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r4, #924\t@ 0x39c\n-\taddw\tr0, r4, #2116\t@ 0x844\n-\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tstr.w\tr3, [r4, #2064]\t@ 0x810\n+\tadd.w\tr1, r6, #924\t@ 0x39c\n+\tadd.w\tr0, r6, #2112\t@ 0x840\n+\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr3, [r6, #2060]\t@ 0x80c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr3, [r4, #944]\t@ 0x3b0\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tb.n\t2e20 <__gridxc_cell_MOD_cellxc+0x2844>\n-\tvmov.i64\td10, #0x0000000000000000\n-\tvldr\td19, [pc, #704]\t@ 3688 <__gridxc_cell_MOD_cellxc+0x30ac>\n-\tvmov.f64\td8, d10\n-\tb.w\t25d4 <__gridxc_cell_MOD_cellxc+0x1ff8>\n-\tldr.w\tip, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tldrd\tr2, r1, [r7, #664]\t@ 0x298\n-\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r6, #944]\t@ 0x3b0\n+\tstr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tb.n\t2ee8 <__gridxc_cell_MOD_cellxc+0x28d4>\n+\tvldr\td8, [pc, #740]\t@ 3780 <__gridxc_cell_MOD_cellxc+0x316c>\n+\tvldr\td4, [pc, #744]\t@ 3788 <__gridxc_cell_MOD_cellxc+0x3174>\n+\tvmov.f64\td10, d8\n+\tb.w\t267c <__gridxc_cell_MOD_cellxc+0x2068>\n+\tldr.w\tip, [r7, #792]\t@ 0x318\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr0, [r7, #692]\t@ 0x2b4\n \tbl\t0 \n-\tb.w\t1fce <__gridxc_cell_MOD_cellxc+0x19f2>\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n-\tstr\tr0, [r3, #0]\n+\tb.w\t2070 <__gridxc_cell_MOD_cellxc+0x1a5c>\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tstr\tr6, [r3, #0]\n \tadds\tr3, r2, #1\n \tcmp\tr2, r1\n-\tblt.w\t23fc <__gridxc_cell_MOD_cellxc+0x1e20>\n+\tblt.w\t24a6 <__gridxc_cell_MOD_cellxc+0x1e92>\n \tldr\tr3, [r7, #100]\t@ 0x64\n-\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n+\tldr.w\tr2, [r7, #432]\t@ 0x1b0\n \tstr\tr3, [r7, #100]\t@ 0x64\n \tldr\tr3, [r7, #104]\t@ 0x68\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tldr.w\tr2, [r7, #144]\t@ 0x90\n \tstr\tr3, [r7, #104]\t@ 0x68\n \tldr\tr3, [r7, #108]\t@ 0x6c\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tldr.w\tr2, [r7, #464]\t@ 0x1d0\n \tstr\tr3, [r7, #108]\t@ 0x6c\n-\tldr.w\tr3, [r7, #132]\t@ 0x84\n-\tcmp\tr2, r1\n-\tadd\tip, r3\n-\tadd.w\tr3, r2, #1\n-\tbeq.w\t366c <__gridxc_cell_MOD_cellxc+0x3090>\n-\tstr.w\tr3, [r7, #292]\t@ 0x124\n-\tb.w\t1cda <__gridxc_cell_MOD_cellxc+0x16fe>\n-\tadd.w\tr9, r7, #1248\t@ 0x4e0\n-\tldr.w\tip, [r7, #92]\t@ 0x5c\n+\tldr.w\tr3, [r7, #128]\t@ 0x80\n+\tcmp\tr9, r2\n+\tadd\tr8, r3\n+\tadd.w\tr3, r9, #1\n+\tbeq.w\t3764 <__gridxc_cell_MOD_cellxc+0x3150>\n+\tmov\tr9, r3\n+\tb.w\t1d6c <__gridxc_cell_MOD_cellxc+0x1758>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\taddw\tsl, r7, #2488\t@ 0x9b8\n+\tadd.w\tr6, r9, #1\n+\tstr.w\tr9, [r7, #636]\t@ 0x27c\n \tldr.w\tr4, [r7, #624]\t@ 0x270\n-\tadd.w\tr3, sl, r5\n-\tmov\tr6, r9\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n+\tadd\tr3, r5\n+\tldr.w\tr9, [r7, #92]\t@ 0x5c\n+\tmov\tr1, r2\n+\tstr.w\tr3, [r7, #620]\t@ 0x26c\n \tlsls\tr5, r5, #3\n-\tadd.w\tr3, r7, #2512\t@ 0x9d0\n-\tmovs\tr2, #26\n-\tadd.w\tlr, r8, #1\n-\tstr.w\tr8, [r7, #640]\t@ 0x280\n+\tmovs\tr3, #26\n+\tmov\tr2, sl\n+\tadd.w\tr8, r7, #1224\t@ 0x4c8\n+\tstr.w\tr8, [r7, #656]\t@ 0x290\n \tldr.w\tr0, [r1, #4]!\n-\tmov\tsl, r3\n-\tmov\tr8, r6\n-\tstr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n+\tmov\tsl, r2\n+\tstr.w\tr0, [r7, #784]\t@ 0x310\n \tmvn.w\tr0, #2\n-\tstrd\tr1, r3, [r7, #492]\t@ 0x1ec\n-\tstr.w\tr0, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r9]\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr3, [r9, #4]\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr3, [r9, #8]\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr3, [r8]\n+\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr1, [r7, #440]\t@ 0x1b8\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r8]\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr.w\tr3, [r8, #4]\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr3, [r8, #8]\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tldr\tr3, [r3, #0]\n+\tcmp\tr1, #0\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tcmp\tr2, #0\n-\tblt.w\t35dc <__gridxc_cell_MOD_cellxc+0x3000>\n+\tblt.w\t36ce <__gridxc_cell_MOD_cellxc+0x30ba>\n \tcmp\tr3, #0\n-\tblt.w\t35f0 <__gridxc_cell_MOD_cellxc+0x3014>\n-\tsdiv\tr2, r3, r2\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tblt.w\t36ea <__gridxc_cell_MOD_cellxc+0x30d6>\n+\tmov\tr0, r3\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tmov\tr2, r0\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tmls\tr3, r1, r2, r3\n-\tstr.w\tr3, [r8]\n-\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tstr\tr3, [r2, #0]\n+\tldr.w\tr3, [r7, #636]\t@ 0x27c\n \tcmp\tr3, #0\n-\tble.n\t35a8 <__gridxc_cell_MOD_cellxc+0x2fcc>\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tldr.w\tr6, [r9]\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n-\tldr.w\tr0, [r7, #628]\t@ 0x274\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr1, [r9, #8]\n-\tadd\tr0, r6\n-\tstr.w\tr3, [r7, #652]\t@ 0x28c\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n-\tvldr\td25, [sl, #-24]\t@ 0xffffffe8\n-\tvldr\td24, [sl, #-16]\n+\tble.n\t3692 <__gridxc_cell_MOD_cellxc+0x307e>\n+\tldrd\tip, lr, [r8]\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr0, [r7, #620]\t@ 0x26c\n+\tldr.w\tr1, [r8, #8]\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tadd\tr0, ip\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tvldr\td2, [sl, #-24]\t@ 0xffffffe8\n+\tvldr\td3, [sl, #-16]\n \tmla\tr0, r3, r1, r0\n-\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n-\tvldr\td23, [sl, #-8]\n-\tvldr\td22, [r4]\n-\tvldr\td21, [fp]\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tvldr\td4, [sl, #-8]\n+\tvldr\td5, [fp]\n+\tvldr\td6, [r4]\n \tmul.w\tr1, r3, r1\n-\tldr.w\tr3, [r9, #4]\n-\tmla\tr1, r2, r3, r1\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd\tr1, r6\n-\tmovs\tr6, #1\n-\tmla\tr0, r2, r3, r0\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tmla\tr1, r3, lr, r1\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tadd\tr1, ip\n+\tmov.w\tip, #1\n+\tmla\tr0, r3, lr, r0\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n \tadd.w\tr0, r3, r0, lsl #3\n-\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tadd.w\tr1, r3, r1, lsl #3\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n-\tvldr\td16, [r2, #8]\n-\tadds\tr6, #1\n-\tvldr\td18, [r2]\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tvldr\td7, [r2, #8]\n+\tadd.w\tip, ip, #1\n+\tvldr\td12, [r2]\n \tadds\tr3, #24\n-\tvldr\td17, [r3, #-16]\n+\tvldr\td0, [r3, #-16]\n \tadds\tr2, #24\n-\tvmul.f64\td16, d24, d16\n-\tvldr\td27, [r2, #-8]\n-\tvfma.f64\td16, d18, d25\n-\tvldr\td19, [r3, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td17, d24, d17\n-\tvldr\td20, [r0]\n-\tvldr\td26, [r3, #-8]\n-\tcmp\tr6, lr\n-\tvfma.f64\td17, d19, d25\n-\tvldr\td18, [r1]\n-\tvfma.f64\td16, d27, d23\n-\tvmul.f64\td20, d15, d20\n-\tvfma.f64\td17, d26, d23\n-\tvfms.f64\td22, d16, d20\n-\tvadd.f64\td16, d17, d16\n-\tvadd.f64\td18, d18, d16\n-\tvstr\td22, [r4]\n-\tvldr\td16, [r0]\n+\tvmul.f64\td7, d3, d7\n+\tvldr\td1, [r2, #-8]\n+\tvmla.f64\td7, d2, d12\n+\tvldr\td14, [r3, #-24]\t@ 0xffffffe8\n+\tvmul.f64\td0, d3, d0\n+\tvldr\td9, [r0]\n+\tvldr\td8, [r3, #-8]\n+\tcmp\tip, r6\n+\tvmla.f64\td0, d2, d14\n+\tvldr\td12, [r1]\n+\tvmla.f64\td7, d4, d1\n+\tvmul.f64\td9, d11, d9\n+\tvmla.f64\td0, d4, d8\n+\tvmls.f64\td5, d9, d7\n+\tvadd.f64\td7, d0, d7\n+\tvadd.f64\td12, d12, d7\n+\tvstr\td5, [fp]\n+\tvldr\td7, [r0]\n \tadd\tr0, r5\n-\tvstr\td18, [r1]\n-\tadd\tr1, ip\n-\tvnmul.f64\td16, d16, d15\n-\tvfma.f64\td21, d17, d16\n-\tvstr\td21, [fp]\n-\tbne.n\t353a <__gridxc_cell_MOD_cellxc+0x2f5e>\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tvstr\td12, [r1]\n+\tadd\tr1, r9\n+\tvmul.f64\td7, d11, d7\n+\tvmls.f64\td6, d7, d0\n+\tvstr\td6, [r4]\n+\tbne.n\t3622 <__gridxc_cell_MOD_cellxc+0x300e>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tadd.w\tsl, sl, #72\t@ 0x48\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #4\n-\tbne.w\t347e <__gridxc_cell_MOD_cellxc+0x2ea2>\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tmov\tr6, r8\n-\tldrd\tr1, r3, [r7, #492]\t@ 0x1ec\n-\tadds\tr2, #3\n-\tadds\tr6, #4\n-\tcmp\tr2, #35\t@ 0x23\n-\tadd.w\tr3, r3, #24\n-\tbne.w\t3462 <__gridxc_cell_MOD_cellxc+0x2e86>\n-\tldr.w\tr8, [r7, #640]\t@ 0x280\n-\tb.w\t2b52 <__gridxc_cell_MOD_cellxc+0x2576>\n-\tcmp\tr3, #0\n-\tble.w\t34b0 <__gridxc_cell_MOD_cellxc+0x2ed4>\n-\tsubs\tr2, r3, #1\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tsdiv\tr2, r2, r1\n-\tsubs\tr2, #1\n-\tb.n\t34b4 <__gridxc_cell_MOD_cellxc+0x2ed8>\n-\tadds\tr2, r3, #1\n-\tb.n\t35e4 <__gridxc_cell_MOD_cellxc+0x3008>\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tmov\tr4, sl\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tmul.w\tr8, r2, r3\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tmul.w\tr4, r3, r4\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tlsls\tr3, r3, #3\n-\tmov\tr9, r3\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n-\tadds\tr3, r6, r3\n-\tadd\tr3, r8\n+\tbne.w\t3560 <__gridxc_cell_MOD_cellxc+0x2f4c>\n+\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tadds\tr3, #3\n+\tadds\tr0, #4\n+\tldr.w\tr1, [r7, #440]\t@ 0x1b8\n+\tadds\tr2, #24\n+\tcmp\tr3, #35\t@ 0x23\n+\tstr.w\tr0, [r7, #656]\t@ 0x290\n+\tbne.w\t3542 <__gridxc_cell_MOD_cellxc+0x2f2e>\n+\tldr.w\tr9, [r7, #636]\t@ 0x27c\n+\tb.w\t2c1e <__gridxc_cell_MOD_cellxc+0x260a>\n+\tcmp\tr3, #0\n+\tit\tgt\n+\taddgt.w\tr0, r3, #4294967295\t@ 0xffffffff\n+\tble.w\t3594 <__gridxc_cell_MOD_cellxc+0x2f80>\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tsubs\tr2, r0, #1\n+\tb.n\t35a4 <__gridxc_cell_MOD_cellxc+0x2f90>\n+\tadds\tr0, r3, #1\n+\tb.n\t36da <__gridxc_cell_MOD_cellxc+0x30c6>\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr0, [r7, #728]\t@ 0x2d8\n+\tmul.w\tr0, r3, r0\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tmul.w\tr4, r3, r9\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tmov.w\tlr, r3, lsl #3\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n+\tadds\tr3, r5, r3\n+\tadd\tr3, r0\n \tcmp\tr2, #0\n \tadd\tr3, r4\n-\tble.n\t3658 <__gridxc_cell_MOD_cellxc+0x307c>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n+\tble.n\t3750 <__gridxc_cell_MOD_cellxc+0x313c>\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tstr.w\tr1, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n \tadd.w\tr3, r2, r3, lsl #3\n \tmovs\tr2, #0\n-\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tadds\tr2, #1\n \tldrd\tsl, fp, [r3]\n-\tadd\tr3, r9\n+\tadd\tr3, lr\n \tstrd\tsl, fp, [r1], #8\n-\tstr.w\tr1, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n \tcmp\tr2, r1\n-\tbne.n\t363c <__gridxc_cell_MOD_cellxc+0x3060>\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tadds\tr3, r6, #1\n-\tcmp\tr6, r2\n-\tbge.w\t33e8 <__gridxc_cell_MOD_cellxc+0x2e0c>\n-\tadd.w\tr0, lr, r3\n-\tmov\tr6, r3\n-\tb.n\t3612 <__gridxc_cell_MOD_cellxc+0x3036>\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tbne.n\t3734 <__gridxc_cell_MOD_cellxc+0x3120>\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadds\tr3, r5, #1\n+\tcmp\tr5, r2\n+\tbge.w\t34c6 <__gridxc_cell_MOD_cellxc+0x2eb2>\n+\tadd.w\tr6, ip, r3\n+\tmov\tr5, r3\n+\tb.n\t370a <__gridxc_cell_MOD_cellxc+0x30f6>\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tcmp\tr3, #0\n-\tble.n\t36ca <__gridxc_cell_MOD_cellxc+0x30ee>\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tble.n\t37ce <__gridxc_cell_MOD_cellxc+0x31ba>\n+\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n \tmovs\tr4, #1\n-\tldr.w\tr5, [r7, #452]\t@ 0x1c4\n+\tldr.w\tr5, [r7, #444]\t@ 0x1bc\n \tsubs\tr6, r3, #4\n-\tb.n\t36b0 <__gridxc_cell_MOD_cellxc+0x30d4>\n+\tb.n\t37b4 <__gridxc_cell_MOD_cellxc+0x31a0>\n \tnop\n \tnop.w\n-\t.word\t0x00000000\n+\t...\n \t.word\t0x00100000\n-\t.word\t0x00000d06\n+\t.word\t0x00000d60\n R_ARM_REL32\t.data\n-\t.word\t0x0000053c\n+\t.word\t0x000009c6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000392\n+\t.word\t0x00000762\n R_ARM_REL32\t.bss\n-\t.word\t0x00000376\n+\t.word\t0x000003c6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000342\n+\t.word\t0x000003aa\n R_ARM_REL32\t.bss\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\t.word\t0x00000370\n+ R_ARM_REL32\t.bss\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tadds\tr4, #1\n \tadds\tr5, #4\n \tcmp\tr4, r3\n-\tbgt.n\t36ca <__gridxc_cell_MOD_cellxc+0x30ee>\n+\tbgt.n\t37ce <__gridxc_cell_MOD_cellxc+0x31ba>\n \tldr.w\tr3, [r6, #4]!\n \tcmp\tr3, #0\n-\tbeq.n\t36a4 <__gridxc_cell_MOD_cellxc+0x30c8>\n+\tbeq.n\t37a8 <__gridxc_cell_MOD_cellxc+0x3194>\n \tmov\tr0, r5\n \tadds\tr4, #1\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_end>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_end\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tadds\tr5, #4\n \tcmp\tr4, r3\n-\tble.n\t36b0 <__gridxc_cell_MOD_cellxc+0x30d4>\n-\tldr.w\tr0, [r7, #452]\t@ 0x1c4\n+\tble.n\t37b4 <__gridxc_cell_MOD_cellxc+0x31a0>\n+\tldr.w\tr0, [r7, #444]\t@ 0x1bc\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r7, #436]\t@ 0x1b4\n+\tldr.w\tr0, [r7, #424]\t@ 0x1a8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r7, #456]\t@ 0x1c8\n+\tldr.w\tr0, [r7, #448]\t@ 0x1c0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbeq.w\t65da <__gridxc_cell_MOD_cellxc+0x5ffe>\n-\tldr\tr5, [pc, #808]\t@ (3a18 <__gridxc_cell_MOD_cellxc+0x343c>)\n+\tbeq.w\t503c <__gridxc_cell_MOD_cellxc+0x4a28>\n+\tldr\tr5, [pc, #828]\t@ (3b30 <__gridxc_cell_MOD_cellxc+0x351c>)\n \tadd\tr5, pc\n-\tmov\tr8, r5\n \tldr\tr3, [r5, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t65da <__gridxc_cell_MOD_cellxc+0x5ffe>\n-\tldr.w\tr6, [r7, #756]\t@ 0x2f4\n-\tadd.w\tr3, r7, #1016\t@ 0x3f8\n-\tldr\tr4, [pc, #792]\t@ (3a1c <__gridxc_cell_MOD_cellxc+0x3440>)\n+\tbeq.w\t503c <__gridxc_cell_MOD_cellxc+0x4a28>\n+\tldr.w\tr6, [r7, #792]\t@ 0x318\n+\tadd.w\tr3, r7, #976\t@ 0x3d0\n+\tldr.w\tr8, [pc, #812]\t@ 3b34 <__gridxc_cell_MOD_cellxc+0x3520>\n \tmovs\tr2, #72\t@ 0x48\n-\tstr.w\tr6, [r7, #760]\t@ 0x2f8\n-\tmov\tfp, r3\n-\tldr.w\tr1, [r6, #552]\t@ 0x228\n-\tadd\tr4, pc\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\taddw\tr0, r4, #2044\t@ 0x7fc\n-\tstr.w\tr1, [r7, #736]\t@ 0x2e0\n-\tadd.w\tr1, r4, #708\t@ 0x2c4\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd.w\tr4, r7, #1000\t@ 0x3e8\n+\tadd\tr8, pc\n+\tldr.w\tr3, [r6, #552]\t@ 0x228\n+\tadd.w\tr1, r8, #2040\t@ 0x7f8\n+\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tmov\tr0, r1\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tr1, [r7, #744]\t@ 0x2e8\n+\tadd.w\tr1, r8, #708\t@ 0x2c4\n+\tstrd\tr3, r4, [r7, #764]\t@ 0x2fc\n \tadd.w\tr3, r5, #84\t@ 0x54\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n \tadd.w\tr3, r5, #96\t@ 0x60\n-\tmov\tsl, r3\n-\tstr.w\tr6, [r7, #748]\t@ 0x2ec\n-\tvldr\td10, [pc, #708]\t@ 3a00 <__gridxc_cell_MOD_cellxc+0x3424>\n+\tstr.w\tr6, [r7, #756]\t@ 0x2f4\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tvldr\td8, [pc, #708]\t@ 3a08 <__gridxc_cell_MOD_cellxc+0x342c>\n \tmovs\tr2, #72\t@ 0x48\n-\tadd.w\tr1, r4, #780\t@ 0x30c\n-\taddw\tr0, r4, #2116\t@ 0x844\n+\tadd.w\tr1, r8, #780\t@ 0x30c\n+\tadd.w\tr0, r8, #2112\t@ 0x840\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmov\tr5, fp\n-\tldr.w\tip, [r7, #460]\t@ 0x1cc\n-\tldr.w\tr9, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r3, #504]\t@ 0x1f8\n-\tmov\tr4, ip\n-\tmov\tr6, r9\n-\tvdup.32\td16, r3\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n+\tldr.w\tip, [r7, #784]\t@ 0x310\n+\tmov\tr4, r3\n+\tmov\tr6, r3\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tlr, [r7, #776]\t@ 0x308\n+\tldrd\tr2, r3, [r3, #504]\t@ 0x1f8\n+\tadd.w\tsl, r2, #4294967295\t@ 0xffffffff\n+\tadd.w\tr9, r3, #3\n+\tsub.w\tfp, r2, #3\n+\tadds\tr2, r3, #1\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n \tldmia\tr4!, {r0, r1, r2, r3}\n-\tstmia\tr6!, {r0, r1, r2, r3}\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tvadd.i32\td16, d16, d10\n+\tstmia.w\tip!, {r0, r1, r2, r3}\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n \tldmia.w\tr4, {r0, r1}\n-\tstmia.w\tr6, {r0, r1}\n-\tldr.w\tr0, [r7, #748]\t@ 0x2ec\n-\tvst1.64\t{d16}, [r0 :64]!\n-\tldr.w\tr3, [r3, #508]\t@ 0x1fc\n-\tstr.w\tr0, [r7, #748]\t@ 0x2ec\n-\tvdup.32\td16, r3\n-\tldmia.w\tip!, {r0, r1, r2, r3}\n-\tstmia\tr5!, {r0, r1, r2, r3}\n-\tmovs\tr2, #0\n+\tstmia.w\tip, {r0, r1}\n+\tstrd\tfp, sl, [r3]\n+\tldmia\tr6!, {r0, r1, r2, r3}\n+\tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia.w\tr4, {r0, r1}\n-\tstmia.w\tr5, {r0, r1}\n-\tvadd.i32\td16, d16, d8\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr4, [r7, #752]\t@ 0x2f0\n-\tmov\tr1, r8\n-\tvst1.64\t{d16}, [r0 :64]!\n-\tstr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tmov\tr0, r4\n+\tstmia.w\tlr, {r0, r1}\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tmov\tr1, r5\n+\tldr.w\tsl, [r7, #736]\t@ 0x2e0\n+\tadd.w\tr4, r8, #564\t@ 0x234\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tstrd\tr2, r9, [r0]\n+\tmovs\tr2, #0\n+\tmov\tr0, sl\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tmov\tr0, sl\n+\tldr.w\tr9, [r7, #732]\t@ 0x2dc\n \tmovs\tr2, #0\n-\tmov\tr1, r8\n+\tmov\tr1, r5\n+\tmov\tr0, r9\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tstr.w\tr4, [r7, #752]\t@ 0x2f0\n-\tstr\tr4, [sp, #4]\n-\tmov\tr1, r9\n-\tldr\tr4, [pc, #580]\t@ (3a20 <__gridxc_cell_MOD_cellxc+0x3444>)\n-\tmov\tr3, r8\n-\tldr.w\tr9, [r7, #736]\t@ 0x2e0\n-\tadd\tr4, pc\n-\taddw\tr6, r4, #2044\t@ 0x7fc\n-\tadd.w\tr5, r4, #564\t@ 0x234\n-\tmov\tr0, r9\n-\tmov\tr2, r6\n-\tstr\tr5, [sp, #0]\n+\tstr\tr4, [sp, #0]\n+\tstr.w\tsl, [sp, #4]\n+\tmov\tr3, r5\n+\tldr.w\tr6, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tmov\tr0, r6\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tbl\t0 <__gridxc_mesh3d_MOD_addmeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_addmeshdata\n-\tstr\tr5, [sp, #0]\n-\taddw\tr5, r4, #2116\t@ 0x844\n-\tmov\tr3, r8\n-\tmov\tr2, r5\n-\tmov\tr1, fp\n-\tmov\tr0, r9\n-\tstr.w\tsl, [sp, #4]\n+\tstr\tr4, [sp, #0]\n+\tstr.w\tr9, [sp, #4]\n+\tadd.w\tr4, r8, #2112\t@ 0x840\n+\tmov\tr0, r6\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tmov\tr3, r5\n+\tmov\tr2, r4\n \tbl\t0 <__gridxc_mesh3d_MOD_addmeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_addmeshdata\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tmov\tr1, sl\n-\tadd.w\tr0, r2, #8\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tmov\tr1, r9\n+\tadds\tr2, #8\n+\tstr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n \tadds\tr3, #1\n-\tstr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tadds\tr2, #4\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadds\tr2, r1, #4\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n \tcmp\tr3, #4\n-\tmov\tsl, r2\n-\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tbeq.w\t65da <__gridxc_cell_MOD_cellxc+0x5ffe>\n+\tadd.w\tr6, r2, #8\n+\tmov\tr2, sl\n+\tadd.w\tr2, r2, #4\n+\tadd.w\tr0, r0, #8\n+\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tadd.w\tr2, r1, #4\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tstr.w\tr6, [r7, #764]\t@ 0x2fc\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n+\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tbeq.w\t503c <__gridxc_cell_MOD_cellxc+0x4a28>\n \tcmp\tr3, #2\n-\tbeq.w\t76f0 <__gridxc_cell_MOD_cellxc+0x7114>\n-\tadd.w\tr1, r4, #996\t@ 0x3e4\n-\tmov\tr0, r6\n+\tbeq.w\t501e <__gridxc_cell_MOD_cellxc+0x4a0a>\n+\tadd.w\tr1, r8, #996\t@ 0x3e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tmovs\tr2, #72\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\taddw\tr1, r4, #1068\t@ 0x42c\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tmovs\tr2, #72\t@ 0x48\n+\taddw\tr1, r8, #1068\t@ 0x42c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\t3758 <__gridxc_cell_MOD_cellxc+0x317c>\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tadd.w\tr0, r7, #968\t@ 0x3c8\n-\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\tb.n\t3862 <__gridxc_cell_MOD_cellxc+0x324e>\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tadd.w\tr0, r7, #952\t@ 0x3b8\n+\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n+\tmov.w\tr8, #0\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n \tstr\tr3, [r2, #0]\n-\tldr.w\tr3, [r7, #656]\t@ 0x290\n-\tstr.w\tr0, [r7, #544]\t@ 0x220\n-\tstr.w\tr3, [r7, #968]\t@ 0x3c8\n-\tadd.w\tr3, r7, #976\t@ 0x3d0\n-\tstr.w\tr1, [r7, #976]\t@ 0x3d0\n-\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tldr\tr4, [pc, #416]\t@ (3a24 <__gridxc_cell_MOD_cellxc+0x3448>)\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr0, [r7, #592]\t@ 0x250\n+\tstr.w\tr3, [r7, #952]\t@ 0x3b8\n+\tadd.w\tr3, r7, #960\t@ 0x3c0\n+\tstr.w\tr1, [r7, #960]\t@ 0x3c0\n+\tstr\tr3, [r7, #88]\t@ 0x58\n+\tldr\tr4, [pc, #404]\t@ (3b38 <__gridxc_cell_MOD_cellxc+0x3524>)\n \tstr\tr3, [sp, #0]\n-\tldr\tr3, [pc, #416]\t@ (3a28 <__gridxc_cell_MOD_cellxc+0x344c>)\n+\tldr\tr3, [pc, #404]\t@ (3b3c <__gridxc_cell_MOD_cellxc+0x3528>)\n \tadd\tr4, pc\n \tstr\tr2, [sp, #8]\n \tadd\tr3, pc\n-\tldr\tr2, [pc, #412]\t@ (3a2c <__gridxc_cell_MOD_cellxc+0x3450>)\n+\tldr\tr2, [pc, #400]\t@ (3b40 <__gridxc_cell_MOD_cellxc+0x352c>)\n \tadds\tr3, #8\n-\tstr\tr3, [sp, #4]\n+\tstr.w\tr8, [sp, #32]\n \tadd\tr2, pc\n \tmov\tr1, r3\n \tstr\tr2, [sp, #12]\n-\tmovs\tr2, #0\n-\tstr\tr2, [sp, #32]\n-\tstrd\tr2, r2, [sp, #20]\n-\tstr\tr2, [sp, #16]\n \tmovs\tr2, #15\n+\tstr\tr3, [sp, #4]\n \tstr\tr2, [sp, #28]\n \tmov\tr2, r0\n+\tstrd\tr8, r8, [sp, #20]\n \taddw\tr0, r4, #1284\t@ 0x504\n+\tstr.w\tr8, [sp, #16]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_l3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_l3\n \tldr.w\tr6, [r4, #144]\t@ 0x90\n \tldr.w\tlr, [r4, #1284]\t@ 0x504\n-\tldr.w\tr3, [r4, #1288]\t@ 0x508\n-\tcmp\tr6, #0\n-\tbeq.w\t43ca <__gridxc_cell_MOD_cellxc+0x3dee>\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tldr.w\tsl, [r4, #1288]\t@ 0x508\n \tldr.w\tip, [r4, #1308]\t@ 0x51c\n+\tcmp\tr6, #0\n+\tbeq.w\t42fe <__gridxc_cell_MOD_cellxc+0x3cea>\n+\tldr.w\tr3, [r7, #636]\t@ 0x27c\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n \tcmp\tr3, r2\n-\tblt.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tblt.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n \tldr.w\tr1, [r7, #688]\t@ 0x2b0\n \tcmp\tr2, r1\n-\tblt.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tldr.w\tr1, [r7, #668]\t@ 0x29c\n-\tldr.w\tr5, [r7, #708]\t@ 0x2c4\n+\tblt.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tldr.w\tr5, [r7, #692]\t@ 0x2b4\n \tcmp\tr1, r5\n-\tblt.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n+\tblt.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr9, [r4, #1332]\t@ 0x534\n \tadds\tr2, #1\n-\tstr.w\tr2, [r7, #644]\t@ 0x284\n-\tldr.w\tr2, [r4, #148]\t@ 0x94\n+\tstr.w\tr2, [r7, #636]\t@ 0x27c\n \tadds\tr3, #1\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tadds\tr1, #1\n-\tldr.w\tr2, [r4, #168]\t@ 0xa8\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr8, [r4, #1332]\t@ 0x534\n \tldr.w\tr2, [r4, #1304]\t@ 0x518\n-\tldr.w\tr9, [r4, #1320]\t@ 0x528\n+\tadds\tr1, #1\n+\tldr.w\tfp, [r4, #1320]\t@ 0x528\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r4, #148]\t@ 0x94\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [r4, #168]\t@ 0xa8\n \tldr.w\tr5, [r4, #192]\t@ 0xc0\n \tldr.w\tr0, [r4, #204]\t@ 0xcc\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr1, [r7, #652]\t@ 0x28c\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tr1, [r7, #644]\t@ 0x284\n \tldr.w\tr3, [r4, #164]\t@ 0xa4\n \tldr.w\tr1, [r4, #180]\t@ 0xb4\n-\tmul.w\tr4, r8, r2\n-\tstr.w\tr4, [r7, #732]\t@ 0x2dc\n \tmul.w\tr4, r9, r2\n-\tstr.w\tr4, [r7, #668]\t@ 0x29c\n-\tldr.w\tr4, [r7, #724]\t@ 0x2d4\n-\tmul.w\tr8, r5, r3\n-\tvldr\td17, [pc, #196]\t@ 3a10 <__gridxc_cell_MOD_cellxc+0x3434>\n-\tstr.w\tr8, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr4, [r7, #736]\t@ 0x2e0\n+\tmul.w\tr4, fp, r2\n+\tstr.w\tr4, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr4, [r7, #732]\t@ 0x2dc\n+\tmul.w\tr9, r5, r3\n+\tvldr\td5, [pc, #188]\t@ 3b28 <__gridxc_cell_MOD_cellxc+0x3514>\n+\tstr.w\tr9, [r7, #744]\t@ 0x2e8\n \tmul.w\tr4, r5, r4\n-\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n \tadd.w\tr4, r4, r0, lsl #1\n \tadd\tr4, r5\n \tmul.w\tr5, r3, r0\n \tldr.w\tr0, [r7, #688]\t@ 0x2b0\n-\tmov\tfp, r5\n+\tstr.w\tr5, [r7, #776]\t@ 0x308\n \tmla\tr4, r0, r1, r4\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n \tmul.w\tr1, r3, r1\n-\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r7, #692]\t@ 0x2b4\n \tmla\tr4, r0, r1, r4\n-\tmul.w\tr0, r3, r0\n-\tstr.w\tr0, [r7, #740]\t@ 0x2e4\n \tmla\tr1, r3, r4, r6\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmla\tr3, r2, r3, lr\n-\tmov\tsl, r3\n+\tmul.w\tr3, r3, r0\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tmla\tr3, r2, sl, lr\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n \tmul.w\tr3, r2, ip\n \tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tldr.w\tr6, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr5, [r7, #784]\t@ 0x310\n \tmov\tr4, r1\n-\tmov\tr5, sl\n-\tldr.w\tr0, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr6, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr0, [r7, #692]\t@ 0x2b4\n \tmov\tr2, r4\n-\tldr.w\tr8, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr9, [r7, #796]\t@ 0x31c\n \tmov\tr3, r5\n-\tstr.w\tr1, [r7, #640]\t@ 0x280\n-\tb.n\t39f4 <__gridxc_cell_MOD_cellxc+0x3418>\n-\tsub.w\tr9, r2, fp\n-\tcmp.w\tr8, #1\n-\tvldr\td16, [r9]\n-\tble.n\t39d0 <__gridxc_cell_MOD_cellxc+0x33f4>\n-\tvldr\td18, [r2]\n-\tvadd.f64\td16, d16, d18\n-\tvcmpe.f64\td16, d17\n+\tstr.w\tr1, [r7, #624]\t@ 0x270\n+\tb.n\t3b1a <__gridxc_cell_MOD_cellxc+0x3506>\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tcmp.w\tr9, #1\n+\tsub.w\tfp, r2, r1\n+\tvldr\td7, [fp]\n+\tble.n\t3af6 <__gridxc_cell_MOD_cellxc+0x34e2>\n+\tvldr\td6, [r2]\n+\tvadd.f64\td7, d7, d6\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t39fa <__gridxc_cell_MOD_cellxc+0x341e>\n+\tblt.n\t3b20 <__gridxc_cell_MOD_cellxc+0x350c>\n \tmovs\tr1, #1\n \tstr\tr1, [r3, #0]\n \tldr.w\tr1, [r7, #664]\t@ 0x298\n \tadds\tr0, #1\n \tadd\tr3, r1\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n \tadd\tr2, r1\n-\tldr.w\tr1, [r7, #652]\t@ 0x28c\n+\tldr.w\tr1, [r7, #644]\t@ 0x284\n \tcmp\tr0, r1\n-\tbeq.n\t3a30 <__gridxc_cell_MOD_cellxc+0x3454>\n-\tcmp.w\tr8, #0\n-\tbgt.n\t39ba <__gridxc_cell_MOD_cellxc+0x33de>\n-\tmovs\tr1, #0\n-\tstr\tr1, [r3, #0]\n-\tb.n\t39de <__gridxc_cell_MOD_cellxc+0x3402>\n-\t.word\t0xfffffffd\n-\t.word\t0xffffffff\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n+\tbeq.n\t3b44 <__gridxc_cell_MOD_cellxc+0x3530>\n+\tcmp.w\tr9, #0\n+\tbgt.n\t3adc <__gridxc_cell_MOD_cellxc+0x34c8>\n+\tstr.w\tr8, [r3]\n+\tb.n\t3b04 <__gridxc_cell_MOD_cellxc+0x34f0>\n+\tnop\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x00000326\n+\t.word\t0x0000033a\n R_ARM_REL32\t.data\n-\t.word\t0x00000308\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000023c\n+\t.word\t0x0000031e\n R_ARM_REL32\t.bss\n-\t.word\t0x0000019a\n+\t.word\t0x0000018c\n R_ARM_REL32\t.bss\n-\t.word\t0x0000019a\n+\t.word\t0x0000018c\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000196\n+\t.word\t0x00000186\n R_ARM_REL32\t.LC42\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tadds\tr6, #1\n-\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n \tadd\tr5, r3\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tadd\tr4, r3\n-\tldr.w\tr3, [r7, #644]\t@ 0x284\n+\tldr.w\tr3, [r7, #636]\t@ 0x27c\n \tcmp\tr6, r3\n-\tbne.n\t39a8 <__gridxc_cell_MOD_cellxc+0x33cc>\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n-\tmov\tr2, sl\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tbne.n\t3aca <__gridxc_cell_MOD_cellxc+0x34b6>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n \tadd\tr2, r0\n-\tmov\tsl, r2\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n \tadd\tr1, r2\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tcmp\tr2, r3\n-\tbne.n\t39a0 <__gridxc_cell_MOD_cellxc+0x33c4>\n-\tldr.w\tr2, [pc, #3368]\t@ 4798 <__gridxc_cell_MOD_cellxc+0x41bc>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tcmp\tr3, r2\n+\tbne.n\t3ac0 <__gridxc_cell_MOD_cellxc+0x34ac>\n+\tldr.w\tr2, [pc, #2240]\t@ 4448 <__gridxc_cell_MOD_cellxc+0x3e34>\n \tadd\tr2, pc\n \tldr.w\tr3, [r2, #1336]\t@ 0x538\n \tldr.w\tr1, [r2, #1340]\t@ 0x53c\n \tldr.w\tr4, [r2, #1312]\t@ 0x520\n-\tldr.w\tr5, [r2, #1324]\t@ 0x52c\n+\tldr.w\tr5, [r2, #1316]\t@ 0x524\n \tcmp\tr3, r1\n-\tldr.w\tr0, [r2, #1328]\t@ 0x530\n-\tldr.w\tr6, [r2, #1316]\t@ 0x524\n-\tstr.w\tr4, [r7, #652]\t@ 0x28c\n-\tstr.w\tr5, [r7, #644]\t@ 0x284\n-\tstr.w\tr0, [r7, #680]\t@ 0x2a8\n-\tbgt.w\t43c6 <__gridxc_cell_MOD_cellxc+0x3dea>\n+\tldr.w\tr6, [r2, #1328]\t@ 0x530\n+\tmov\tfp, r4\n+\tldr.w\tr8, [r2, #1324]\t@ 0x52c\n+\tstr.w\tr5, [r7, #784]\t@ 0x310\n+\tstr.w\tr6, [r7, #776]\t@ 0x308\n+\tbgt.w\t42fa <__gridxc_cell_MOD_cellxc+0x3ce6>\n \tadds\tr1, #1\n \tldr.w\tr0, [r2, #1320]\t@ 0x528\n \tsubs\tr1, r1, r3\n-\tstr.w\tr1, [r7, #636]\t@ 0x27c\n+\tstr.w\tr1, [r7, #768]\t@ 0x300\n \tldr.w\tr1, [r2, #1332]\t@ 0x534\n-\tstr.w\tr0, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr0, [r2, #1304]\t@ 0x518\n-\tsubs\tr2, r6, r4\n-\tstr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tmul.w\tr3, r1, r3\n-\tmov\tr1, r2\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n-\tmul.w\tsl, r0, ip\n-\tadds\tr2, r3, r2\n-\tmla\tr8, r4, ip, r2\n-\tadds\tr2, r1, #1\n-\tbic.w\tr1, r2, #3\n-\tstr.w\tr2, [r7, #668]\t@ 0x29c\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd\tr1, r4\n-\tcmp\tr2, #3\n-\tit\thi\n-\tmovhi\tr4, r1\n-\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n-\tmul.w\tr1, r1, r5\n-\tadd.w\tr2, r8, r1\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tadds\tr3, r4, #2\n-\tmla\tr8, r0, r2, lr\n-\tstr.w\tr3, [r7, #564]\t@ 0x234\n-\tmov\tr2, r3\n-\tadds\tr3, r4, #3\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tmovs\tr1, #0\n-\tstr.w\tr8, [r7, #760]\t@ 0x2f8\n-\tadds\tr3, #1\n-\tsubs\tr5, r3, r5\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr5, [r7, #520]\t@ 0x208\n-\tmul.w\tr5, r3, r0\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr5, [r7, #628]\t@ 0x274\n-\tmul.w\tr5, r3, r0\n-\tadd.w\tr3, r7, #768\t@ 0x300\n-\tstr.w\tr5, [r7, #624]\t@ 0x270\n-\tmul.w\tr5, ip, r4\n-\tstr.w\tr5, [r7, #616]\t@ 0x268\n-\tmla\tr5, r4, ip, ip\n-\tstr.w\tr5, [r7, #608]\t@ 0x260\n-\tadds\tr5, r4, #1\n-\tldr.w\tr4, [r7, #688]\t@ 0x2b0\n-\tstr.w\tr5, [r7, #612]\t@ 0x264\n-\tmul.w\tr5, ip, r2\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tstr.w\tr5, [r7, #600]\t@ 0x258\n-\tmul.w\tr4, ip, r4\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tstr.w\tr4, [r7, #640]\t@ 0x280\n-\tmov\tr4, r1\n-\tlsrs\tr2, r2, #2\n-\tstr.w\tr2, [r7, #560]\t@ 0x230\n-\tadd.w\tr2, r7, #772\t@ 0x304\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n-\tadd.w\tr2, r7, #776\t@ 0x308\n-\tstr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tadd.w\tr2, r7, #780\t@ 0x30c\n-\tstr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n-\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n-\tcmp\tr2, r5\n-\tbgt.w\t3cd6 <__gridxc_cell_MOD_cellxc+0x36fa>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tmov.w\tr8, #0\n-\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tldr.w\tr5, [r7, #740]\t@ 0x2e4\n-\tand.w\tr9, r2, #3\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n-\tcmp\tr2, r6\n-\tbgt.n\t3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tcmp\tr2, #3\n-\tbls.n\t3c54 <__gridxc_cell_MOD_cellxc+0x3678>\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tmov.w\tip, #0\n-\tmov\tr3, sl\n-\tstr.w\tr1, [r7, #444]\t@ 0x1bc\n-\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tadd.w\tip, ip, #1\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tldr\tr1, [r1, #0]\n-\tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr1, [r7, #516]\t@ 0x204\n-\tadd.w\tsl, r2, r3\n-\tldr\tr2, [r2, r3]\n-\tadd.w\tfp, sl, r3\n-\tstr\tr2, [r1, #0]\n-\tldr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr2, [sl, r3]\n-\tstr\tr2, [r1, #0]\n-\tadd.w\tr2, fp, r3, lsl #1\n-\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr1, [fp, r3]\n-\tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tvld1.64\t{d18-d19}, [r2 :64]\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tvceq.i32\tq9, q9, #0\n-\tcmp\tip, r2\n-\tvmvn\tq9, q9\n-\tvsub.i32\tq8, q8, q9\n-\tbne.n\t3bde <__gridxc_cell_MOD_cellxc+0x3602>\n-\tvadd.i32\td7, d16, d17\n-\tldr.w\tr1, [r7, #444]\t@ 0x1bc\n-\tmov\tsl, r3\n-\tvpadd.i32\td7, d7, d7\n-\tvmov\tr2, s14\n-\tadd\tr4, r2\n-\tcmp.w\tr9, #0\n-\tbeq.n\t3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tadds\tr2, r5, r2\n-\tmul.w\tr2, r0, r2\n-\tldr.w\tr2, [lr, r2]\n-\tcbz\tr2, 3c66 <__gridxc_cell_MOD_cellxc+0x368a>\n-\tadds\tr4, #1\n-\tldr.w\tr2, [r7, #612]\t@ 0x264\n-\tcmp\tr6, r2\n-\tblt.n\t3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n-\tldr.w\tr2, [r7, #608]\t@ 0x260\n-\tadds\tr2, r5, r2\n-\tmul.w\tr2, r0, r2\n-\tldr.w\tr2, [lr, r2]\n-\tcbz\tr2, 3c80 <__gridxc_cell_MOD_cellxc+0x36a4>\n-\tadds\tr4, #1\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tcmp\tr6, r2\n-\tblt.n\t3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tadds\tr2, r5, r2\n-\tmul.w\tr2, r0, r2\n-\tldr.w\tr2, [lr, r2]\n-\tcbz\tr2, 3c9a <__gridxc_cell_MOD_cellxc+0x36be>\n-\tadds\tr4, #1\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tcmp\tr6, r2\n-\tblt.n\t3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n-\tldr.w\tr2, [r7, #640]\t@ 0x280\n-\tadds\tr2, r5, r2\n-\tmul.w\tr2, r0, r2\n-\tldr.w\tr2, [lr, r2]\n-\tcbz\tr2, 3cb4 <__gridxc_cell_MOD_cellxc+0x36d8>\n+\tldr.w\tr2, [r2, #1304]\t@ 0x518\n+\tmla\tr3, r3, r1, sl\n+\tmla\tr3, r4, ip, r3\n+\tmla\tr3, r0, r8, r3\n+\tmul.w\tr9, r2, r1\n+\tmul.w\tip, r2, ip\n+\tmul.w\tr1, r2, r0\n+\tmla\tlr, r2, r3, lr\n+\tadds\tr2, r6, #1\n+\tsub.w\tr2, r2, r8\n+\tmovs\tr3, #0\n+\tmov\tsl, r2\n+\tadds\tr2, r5, #1\n+\tsubs\tr2, r2, r4\n+\tmov\tr4, r3\n+\tstr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tcmp\tr8, r2\n+\tbgt.n\t3c30 <__gridxc_cell_MOD_cellxc+0x361c>\n+\tmov\tr2, lr\n+\tmovs\tr6, #0\n+\tldr.w\tr5, [r7, #784]\t@ 0x310\n+\tcmp\tfp, r5\n+\tbgt.n\t3c28 <__gridxc_cell_MOD_cellxc+0x3614>\n+\tmov\tr5, r2\n+\tmovs\tr0, #0\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tldr\tr3, [r5, #0]\n+\tcbz\tr3, 3c18 <__gridxc_cell_MOD_cellxc+0x3604>\n \tadds\tr4, #1\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadd.w\tr8, r8, #1\n-\tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tadd\tr5, r2\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tcmp\tr3, r8\n-\tbne.w\t3bb8 <__gridxc_cell_MOD_cellxc+0x35dc>\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tadds\tr1, #1\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #636]\t@ 0x27c\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tcmp\tr3, r1\n-\tbne.w\t3b92 <__gridxc_cell_MOD_cellxc+0x35b6>\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr5, [pc, #2712]\t@ 479c <__gridxc_cell_MOD_cellxc+0x41c0>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tadds\tr0, #1\n+\tadd\tr5, ip\n+\tcmp\tr3, r0\n+\tbne.n\t3c12 <__gridxc_cell_MOD_cellxc+0x35fe>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tadds\tr6, #1\n+\tadd\tr2, r1\n+\tcmp\tsl, r6\n+\tbne.n\t3c02 <__gridxc_cell_MOD_cellxc+0x35ee>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tadds\tr3, #1\n+\tadd\tlr, r9\n+\tcmp\tr2, r3\n+\tbne.n\t3bf6 <__gridxc_cell_MOD_cellxc+0x35e2>\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldr.w\tr5, [pc, #2056]\t@ 444c <__gridxc_cell_MOD_cellxc+0x3e38>\n \tldr.w\tr2, [r3, #552]\t@ 0x228\n \tadd\tr5, pc\n \tadds\tr5, #80\t@ 0x50\n \tmov\tr6, r2\n \tmov\tr1, r5\n \tmov\tr0, r6\n \tmovs\tr2, #0\n \tbl\t0 <__gridxc_mesh3d_MOD_fftmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_fftmeshdistr\n \tmov\tr1, r5\n-\tadd.w\tr5, r7, #1064\t@ 0x428\n+\tadd.w\tr5, r7, #1048\t@ 0x418\n \tmov\tr0, r6\n \tmov\tr2, r5\n-\tstr.w\tr5, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr5, [r7, #476]\t@ 0x1dc\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldr.w\tr3, [r7, #1072]\t@ 0x430\n-\tldr.w\tr2, [r7, #1076]\t@ 0x434\n-\tmov\tr9, r6\n+\tldr.w\tr3, [r7, #1056]\t@ 0x420\n+\tldr.w\tr2, [r7, #1060]\t@ 0x424\n+\tmov\tfp, r6\n \tsubs\tr2, r2, r3\n-\tldr.w\tr3, [r7, #1064]\t@ 0x428\n+\tldr.w\tr3, [r7, #1048]\t@ 0x418\n \tmov\tr1, r2\n-\tstr.w\tr2, [r7, #640]\t@ 0x280\n-\tldr.w\tr2, [r7, #1068]\t@ 0x42c\n+\tstr.w\tr2, [r7, #644]\t@ 0x284\n+\tldr.w\tr2, [r7, #1052]\t@ 0x41c\n \tadds\tr5, r1, #1\n-\tadd.w\tr1, r7, #892\t@ 0x37c\n-\tstr.w\tr1, [r7, #752]\t@ 0x2f0\n+\tadd.w\tr1, r7, #876\t@ 0x36c\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n \tsubs\tr6, r2, r3\n-\tldr.w\tr2, [r7, #1084]\t@ 0x43c\n-\tldr.w\tr3, [r7, #1080]\t@ 0x438\n+\tldr.w\tr2, [r7, #1068]\t@ 0x42c\n+\tldr.w\tr3, [r7, #1064]\t@ 0x428\n+\tadd.w\tsl, r6, #1\n+\tstr.w\tr6, [r7, #736]\t@ 0x2e0\n \tmovs\tr1, #0\n-\tstr.w\tr6, [r7, #732]\t@ 0x2dc\n \tsubs\tr3, r2, r3\n-\tadd.w\tr2, r7, #884\t@ 0x374\n+\tadd.w\tr2, r7, #868\t@ 0x364\n \tmov\tr0, r2\n-\tadds\tr2, r6, #1\n-\tstr.w\tr2, [r7, #652]\t@ 0x28c\n \tmov\tr2, r3\n-\tstr.w\tr3, [r7, #628]\t@ 0x274\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n \tmla\tr3, r6, r5, r5\n \tmla\tr3, r2, r3, r3\n-\tldr.w\tr6, [r7, #484]\t@ 0x1e4\n-\tldr.w\tr8, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr8, [r7, #776]\t@ 0x308\n \tcmp\tr3, r4\n \tstr.w\tr5, [r7, #636]\t@ 0x27c\n \tit\tlt\n \tmovlt\tr3, r4\n-\tldr.w\tr4, [r7, #652]\t@ 0x28c\n+\tldr.w\tr4, [r7, #472]\t@ 0x1d8\n \tstr\tr3, [r0, #0]\n-\tcmp\tr6, r4\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tcmp\tr4, sl\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tit\tlt\n-\tmovlt\tr6, r4\n-\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tstr.w\tr0, [r7, #680]\t@ 0x2a8\n-\tmov\tr0, r8\n-\tcmp\tr4, r5\n-\tstr.w\tr6, [r7, #740]\t@ 0x2e4\n+\tmovlt\tr4, sl\n+\tcmp\tr6, r5\n \tit\tlt\n-\tmovlt\tr4, r5\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n-\tstr.w\tr4, [r7, #724]\t@ 0x2d4\n-\tmovs\tr4, #0\n+\tmovlt\tr6, r5\n+\tldr.w\tr5, [r7, #460]\t@ 0x1cc\n+\tstr.w\tr0, [r7, #692]\t@ 0x2b4\n+\tmov\tr0, r8\n \tcmp\tr5, r3\n+\tstr.w\tr4, [r7, #768]\t@ 0x300\n \tit\tlt\n \tmovlt\tr5, r3\n-\tstr.w\tr5, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr6, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr5, [r7, #696]\t@ 0x2b8\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_get_qmesh>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_get_qmesh\n-\tldr.w\tr3, [pc, #2508]\t@ 47a0 <__gridxc_cell_MOD_cellxc+0x41c4>\n-\tldr.w\tr0, [pc, #2508]\t@ 47a4 <__gridxc_cell_MOD_cellxc+0x41c8>\n+\tldr.w\tr3, [pc, #1864]\t@ 4450 <__gridxc_cell_MOD_cellxc+0x3e3c>\n+\tmovs\tr4, #0\n+\tldr.w\tr0, [pc, #1860]\t@ 4454 <__gridxc_cell_MOD_cellxc+0x3e40>\n \tmov\tr2, r8\n \tadd\tr3, pc\n \tmovs\tr1, #11\n \tadds\tr5, r3, #4\n-\tmov\tsl, r3\n-\tldr.w\tr3, [pc, #2500]\t@ 47a8 <__gridxc_cell_MOD_cellxc+0x41cc>\n+\tmov\tr9, r3\n+\tldr.w\tr3, [pc, #1852]\t@ 4458 <__gridxc_cell_MOD_cellxc+0x3e44>\n \tadd\tr0, pc\n \tmov\tr6, r0\n \tstr\tr1, [sp, #12]\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tadd.w\tr0, r0, #1344\t@ 0x540\n \tstr\tr4, [sp, #16]\n \tstrd\tr4, r4, [sp, #4]\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr0, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr3, [pc, #2468]\t@ 47ac <__gridxc_cell_MOD_cellxc+0x41d0>\n+\tldr.w\tr0, [r7, #792]\t@ 0x318\n+\tldr.w\tr3, [pc, #1820]\t@ 445c <__gridxc_cell_MOD_cellxc+0x3e48>\n \tmov.w\tip, #11\n \tmov\tr2, r8\n \tldr.w\tr1, [r0, #556]\t@ 0x22c\n \tadd\tr3, pc\n \tstrd\tr4, ip, [sp, #16]\n \taddw\tr0, r6, #1380\t@ 0x564\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r5\n \tstr\tr4, [sp, #24]\n \tstrd\tr4, r4, [sp, #8]\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n \tstr\tr1, [sp, #0]\n \tmov\tr1, r5\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #32]\n-\tmov\tr2, sl\n+\tmov\tr2, r9\n \tstr\tr4, [sp, #16]\n \tadds\tr2, #12\n-\tldr.w\tr3, [pc, #2416]\t@ 47b0 <__gridxc_cell_MOD_cellxc+0x41d4>\n+\tldr.w\tr3, [pc, #1768]\t@ 4460 <__gridxc_cell_MOD_cellxc+0x3e4c>\n \taddw\tr0, r6, #1428\t@ 0x594\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tstrd\tr5, r1, [sp, #4]\n \tadd\tr3, pc\n-\tstr.w\tr8, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr8, [r7, #776]\t@ 0x308\n \tmov\tr1, r5\n \tstr.w\tr8, [sp]\n \tstr\tr3, [sp, #12]\n \tmovs\tr3, #12\n \tstr\tr3, [sp, #28]\n \tmov\tr3, r5\n-\tstr.w\tsl, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr9, [r7, #688]\t@ 0x2b0\n+\tmov\tr9, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr.w\tr3, [pc, #2376]\t@ 47b4 <__gridxc_cell_MOD_cellxc+0x41d8>\n+\tldr.w\tr3, [pc, #1724]\t@ 4464 <__gridxc_cell_MOD_cellxc+0x3e50>\n \tmov\tr2, r8\n \tmov\tr1, r5\n \tadd\tr3, pc\n \tadd.w\tr0, r6, #1488\t@ 0x5d0\n \tstr.w\tr8, [sp]\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #13\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r5\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr.w\tr3, [pc, #2340]\t@ 47b8 <__gridxc_cell_MOD_cellxc+0x41dc>\n+\tldr.w\tr3, [pc, #1692]\t@ 4468 <__gridxc_cell_MOD_cellxc+0x3e54>\n \tmov\tr2, r8\n \tmov\tr1, r5\n \tadd\tr3, pc\n \tadd.w\tr0, r6, #1536\t@ 0x600\n \tstr.w\tr8, [sp]\n+\tmov.w\tr8, #9\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #10\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r5\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr.w\tr3, [pc, #2308]\t@ 47bc <__gridxc_cell_MOD_cellxc+0x41e0>\n-\tmov\tr2, r8\n-\tmovs\tr1, #9\n+\tldr.w\tr3, [pc, #1652]\t@ 446c <__gridxc_cell_MOD_cellxc+0x3e58>\n+\tmov\tr2, r9\n+\tmov\tr1, r5\n \tadd\tr3, pc\n \tadd.w\tr0, r6, #1584\t@ 0x630\n-\tstr\tr1, [sp, #12]\n-\tmov\tr1, r5\n+\tstr.w\tr8, [sp, #12]\n \tstr\tr4, [sp, #16]\n \tstrd\tr4, r4, [sp, #4]\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr3, [pc, #2280]\t@ 47c0 <__gridxc_cell_MOD_cellxc+0x41e4>\n-\tmov\tr2, r8\n-\tmovs\tr1, #9\n+\tldr.w\tr3, [pc, #1628]\t@ 4470 <__gridxc_cell_MOD_cellxc+0x3e5c>\n+\tmov\tr2, r9\n+\tmov\tr1, r5\n \tadd\tr3, pc\n \taddw\tr0, r6, #1620\t@ 0x654\n-\tstrd\tr4, r1, [sp, #8]\n-\tmov\tr1, r5\n-\tstr\tr4, [sp, #16]\n-\tstrd\tr4, r4, [sp]\n+\tstrd\tr8, r4, [sp, #12]\n+\tstrd\tr4, r4, [sp, #4]\n+\tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr3, [pc, #2256]\t@ 47c4 <__gridxc_cell_MOD_cellxc+0x41e8>\n-\tmov\tr2, r8\n+\tldr.w\tr3, [pc, #1604]\t@ 4474 <__gridxc_cell_MOD_cellxc+0x3e60>\n+\tmov\tr2, r9\n \tmovs\tr1, #11\n \tadd\tr3, pc\n \tadd.w\tr0, r6, #1656\t@ 0x678\n \tstrd\tr4, r1, [sp, #8]\n \tmov\tr1, r5\n \tstr\tr4, [sp, #16]\n \tstrd\tr4, r4, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr3, [pc, #2228]\t@ 47c8 <__gridxc_cell_MOD_cellxc+0x41ec>\n-\tmov\tr2, r8\n-\tmovs\tr1, #9\n+\tldr.w\tr3, [pc, #1576]\t@ 4478 <__gridxc_cell_MOD_cellxc+0x3e64>\n+\tmov\tr2, r9\n+\tmov\tr1, r5\n \tadd\tr3, pc\n \taddw\tr0, r6, #1692\t@ 0x69c\n-\tstrd\tr4, r1, [sp, #8]\n-\tmov\tr1, r5\n-\tstr\tr4, [sp, #16]\n-\tstrd\tr4, r4, [sp]\n+\tstrd\tr8, r4, [sp, #12]\n+\tstrd\tr4, r4, [sp, #4]\n+\tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr3, [pc, #2204]\t@ 47cc <__gridxc_cell_MOD_cellxc+0x41f0>\n-\tmov\tr2, r8\n-\tmovs\tr1, #9\n+\tldr.w\tr3, [pc, #1552]\t@ 447c <__gridxc_cell_MOD_cellxc+0x3e68>\n+\tmov\tr2, r9\n+\tmov\tr1, r5\n \tadd\tr3, pc\n \tadd.w\tr0, r6, #1728\t@ 0x6c0\n-\tstrd\tr4, r1, [sp, #8]\n-\tmov\tr1, r5\n-\tstr\tr4, [sp, #16]\n-\tstrd\tr4, r4, [sp]\n+\tstrd\tr8, r4, [sp, #12]\n+\tstrd\tr4, r4, [sp, #4]\n+\tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr.w\tr3, [pc, #2176]\t@ 47d0 <__gridxc_cell_MOD_cellxc+0x41f4>\n+\tldr.w\tr3, [pc, #1528]\t@ 4480 <__gridxc_cell_MOD_cellxc+0x3e6c>\n \tmovs\tr1, #11\n \tstr\tr1, [sp, #20]\n \taddw\tr1, r6, #1764\t@ 0x6e4\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n \tmov\tr0, r1\n \tadd\tr3, pc\n \tmov\tr1, r5\n-\tstr.w\tr8, [sp]\n+\tstr.w\tr9, [sp]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r5\n \tstr\tr4, [sp, #24]\n-\tmov\tsl, r0\n+\tmov\tr9, r0\n \tstrd\tr4, r4, [sp, #12]\n \tstr\tr4, [sp, #8]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n-\tmov\tr8, r0\n+\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr\tr1, [r7, #88]\t@ 0x58\n \tsubs\tr2, #1\n \tstr\tr2, [r0, #0]\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n \tadd.w\tip, r3, #8\n-\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n \tsubs\tr2, #1\n \tstr\tr2, [r1, #0]\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n \tsubs\tr2, #1\n \tstr\tr2, [r3, #0]\n-\tmovs\tr2, #9\n-\tstrd\tr2, r4, [sp, #36]\t@ 0x24\n-\tldr.w\tr2, [pc, #2084]\t@ 47d4 <__gridxc_cell_MOD_cellxc+0x41f8>\n+\tldr.w\tr2, [pc, #1448]\t@ 4484 <__gridxc_cell_MOD_cellxc+0x3e70>\n \tstrd\tr5, r5, [sp, #12]\n-\tadd.w\tr5, r6, #1816\t@ 0x718\n+\taddw\tr5, r6, #1812\t@ 0x714\n \tstrd\tip, r3, [sp, #4]\n \tadd\tr2, pc\n \tmov\tr3, ip\n-\tstrd\tr4, r4, [sp, #28]\n-\tstr\tr4, [sp, #24]\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tstrd\tr8, r4, [sp, #36]\t@ 0x24\n \tstr\tr1, [sp, #0]\n+\tmov\tr8, r0\n \tmov\tr1, ip\n \tstr\tr2, [sp, #20]\n+\tstrd\tr4, r4, [sp, #28]\n \tmov\tr2, r0\n+\tstr\tr4, [sp, #24]\n \tmov\tr0, r5\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tmov\tip, sl\n-\tadd.w\tlr, r6, #1888\t@ 0x760\n+\tmov\tip, r9\n+\taddw\tlr, r6, #1884\t@ 0x75c\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia.w\tip!, {r0, r1, r2, r3}\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n \tldmia.w\tip, {r0, r1, r2, r3}\n \tstmia.w\tlr, {r0, r1, r2, r3}\n \tmovs\tr2, #72\t@ 0x48\n \tmov\tr1, r5\n-\tadd.w\tr0, r6, #1936\t@ 0x790\n+\taddw\tr0, r6, #1932\t@ 0x78c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tmov\tr1, r9\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tmov\tr1, fp\n \tbl\t0 <__gridxc_chkgmx_MOD_meshkcut>\n R_ARM_THM_CALL\t__gridxc_chkgmx_MOD_meshkcut\n-\tldr.w\tr2, [r7, #464]\t@ 0x1d0\n \tmov\tr0, r8\n-\tvstr\td0, [r2, #-8]\n+\tvstr\td0, [r8]\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_kcut>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_kcut\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, r4\n-\tble.n\t404e <__gridxc_cell_MOD_cellxc+0x3a72>\n+\tble.n\t3f7a <__gridxc_cell_MOD_cellxc+0x3966>\n \tlsls\tr2, r3, #3\n \tmov\tr1, r4\n-\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n \tadds\tr4, #1\n \tstrd\tr0, r1, [r3]\n \tadds\tr3, #24\n \tstrd\tr0, r1, [r3, #-16]\n \tcmp\tr4, r2\n \tstrd\tr0, r1, [r3, #-8]\n-\tbne.n\t4036 <__gridxc_cell_MOD_cellxc+0x3a5a>\n-\tldr.w\tr4, [pc, #1928]\t@ 47d8 <__gridxc_cell_MOD_cellxc+0x41fc>\n-\tmov\tr9, sp\n-\tldr.w\tr2, [r7, #528]\t@ 0x210\n+\tbne.n\t3f62 <__gridxc_cell_MOD_cellxc+0x394e>\n+\tldr.w\tr4, [pc, #1292]\t@ 4488 <__gridxc_cell_MOD_cellxc+0x3e74>\n+\tmov\tfp, sp\n+\tldr.w\tr2, [r7, #512]\t@ 0x200\n \tadd\tr4, pc\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n \taddw\tr3, r4, #1428\t@ 0x594\n \tstr\tr3, [sp, #4]\n \taddw\tr3, r4, #1380\t@ 0x564\n \tstr\tr3, [sp, #0]\n \taddw\tr3, r4, #1620\t@ 0x654\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_theta\n \tldr.w\tr3, [r4, #1648]\t@ 0x670\n \tldr.w\tr2, [r4, #1652]\t@ 0x674\n \tsubs\tr6, r2, r3\n-\tbmi.n\t4132 <__gridxc_cell_MOD_cellxc+0x3b56>\n+\tbmi.n\t4064 <__gridxc_cell_MOD_cellxc+0x3a50>\n \tlsls\tr1, r6, #3\n-\tldr.w\tr2, [r4, #1660]\t@ 0x67c\n+\tldr.w\tr2, [r4, #1624]\t@ 0x658\n \tadds\tr1, #8\n-\tldr.w\tlr, [r4, #1620]\t@ 0x654\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n-\tmov\tfp, r2\n+\tldr.w\tr2, [r4, #1660]\t@ 0x67c\n \tbic.w\tr0, r0, #15\n-\tldr.w\tr2, [r4, #1684]\t@ 0x694\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n \tsub.w\tr0, sp, r0\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n \tmov\tr2, sp\n-\tldr.w\tsl, [r4, #1624]\t@ 0x658\n-\tldr.w\tr5, [r4, #1656]\t@ 0x678\n+\tldr.w\tlr, [r4, #1620]\t@ 0x654\n \tcmp\tr2, r0\n-\tbeq.n\t40c0 <__gridxc_cell_MOD_cellxc+0x3ae4>\n+\tldr.w\tr5, [r4, #1656]\t@ 0x678\n+\tldr.w\tr8, [r4, #1684]\t@ 0x694\n+\tbeq.n\t3fee <__gridxc_cell_MOD_cellxc+0x39da>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t40b2 <__gridxc_cell_MOD_cellxc+0x3ad6>\n+\tbne.n\t3fe0 <__gridxc_cell_MOD_cellxc+0x39cc>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 40d2 <__gridxc_cell_MOD_cellxc+0x3af6>\n+\tcbz\tr1, 4000 <__gridxc_cell_MOD_cellxc+0x39ec>\n \tsubs\tr1, #4\n \tadd.w\tr2, sp, r1\n \tstr\tr0, [r2, #0]\n-\tldr.w\tr0, [pc, #1800]\t@ 47dc <__gridxc_cell_MOD_cellxc+0x4200>\n+\tldr.w\tr0, [pc, #1160]\t@ 448c <__gridxc_cell_MOD_cellxc+0x3e78>\n \tadd\tr1, sp, #48\t@ 0x30\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tmov\tip, r1\n-\tmovs\tr4, #0\n \tadd\tr0, pc\n-\tldr.w\tr8, [r0, #1644]\t@ 0x66c\n+\tmovs\tr4, #0\n+\tldr.w\tr9, [r0, #1644]\t@ 0x66c\n+\tmla\tr3, r3, r9, r2\n \tldr.w\tr2, [r0, #1640]\t@ 0x668\n \tldr.w\tr0, [r0, #1680]\t@ 0x690\n-\tmla\tr3, r3, r8, sl\n \tmla\tr3, r2, r3, lr\n-\tmul.w\tr2, r8, r2\n-\tvldr\td16, [r3]\n+\tmul.w\tr2, r9, r2\n+\tvldr\td7, [r3]\n \tadds\tr4, #1\n \tadd\tr3, r2\n \tcmp\tr6, r4\n-\tvstmia\tip!, {d16}\n-\tbge.n\t40f6 <__gridxc_cell_MOD_cellxc+0x3b1a>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tmla\tr3, r0, r2, fp\n-\tldr.w\tr2, [pc, #1744]\t@ 47e0 <__gridxc_cell_MOD_cellxc+0x4204>\n+\tvstmia\tip!, {d7}\n+\tbge.n\t4028 <__gridxc_cell_MOD_cellxc+0x3a14>\n+\tldr.w\tr2, [pc, #1108]\t@ 4490 <__gridxc_cell_MOD_cellxc+0x3e7c>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n \tadd\tr2, pc\n+\tmla\tr3, r0, r8, r3\n \tldr.w\tr2, [r2, #1676]\t@ 0x68c\n \tmla\tr3, r2, r3, r5\n \tmul.w\tr2, r0, r2\n \tmovs\tr0, #0\n \tldrd\tr4, r5, [r1], #8\n \tadds\tr0, #1\n \tstrd\tr4, r5, [r3]\n \tcmp\tr6, r0\n \tadd\tr3, r2\n-\tbge.n\t4122 <__gridxc_cell_MOD_cellxc+0x3b46>\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tmov\tsp, r9\n+\tbge.n\t4054 <__gridxc_cell_MOD_cellxc+0x3a40>\n+\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tmov\tsp, fp\n \tcmp\tr3, #0\n-\tble.w\t4580 <__gridxc_cell_MOD_cellxc+0x3fa4>\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tble.w\t57fc <__gridxc_cell_MOD_cellxc+0x51e8>\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n \tcmp\tr3, #0\n-\tble.w\t4580 <__gridxc_cell_MOD_cellxc+0x3fa4>\n-\tldr.w\tr3, [pc, #1688]\t@ 47e4 <__gridxc_cell_MOD_cellxc+0x4208>\n+\tble.w\t57fc <__gridxc_cell_MOD_cellxc+0x51e8>\n+\tldr.w\tr3, [pc, #1048]\t@ 4494 <__gridxc_cell_MOD_cellxc+0x3e80>\n \tmovs\tr2, #0\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n+\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n \tadd\tr3, pc\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tstr.w\tr3, [r7, #672]\t@ 0x2a0\n \taddw\tr3, r3, #1620\t@ 0x654\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n \tcmp\tr3, #0\n-\tble.w\t4558 <__gridxc_cell_MOD_cellxc+0x3f7c>\n-\tldr.w\tr8, [pc, #1648]\t@ 47e8 <__gridxc_cell_MOD_cellxc+0x420c>\n+\tble.w\t57e4 <__gridxc_cell_MOD_cellxc+0x51d0>\n+\tldr.w\tr8, [pc, #1008]\t@ 4498 <__gridxc_cell_MOD_cellxc+0x3e84>\n \tmovs\tr3, #0\n-\tldr.w\tr4, [r7, #756]\t@ 0x2f4\n-\tmov\tr9, r3\n-\tldr.w\tfp, [r7, #668]\t@ 0x29c\n+\tstr.w\tsl, [r7, #664]\t@ 0x298\n+\tmov\tfp, r3\n+\tldr.w\tr4, [r7, #792]\t@ 0x318\n \tadd\tr8, pc\n-\tb.n\t4198 <__gridxc_cell_MOD_cellxc+0x3bbc>\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tadd.w\tr3, r9, #1\n-\tcmp\tr9, r2\n-\tbeq.w\t43b0 <__gridxc_cell_MOD_cellxc+0x3dd4>\n-\tmov\tr9, r3\n+\tldr.w\tsl, [r7, #672]\t@ 0x2a0\n+\tb.n\t40ce <__gridxc_cell_MOD_cellxc+0x3aba>\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadd.w\tr3, fp, #1\n+\tcmp\tfp, r2\n+\tbeq.w\t42e0 <__gridxc_cell_MOD_cellxc+0x3ccc>\n+\tmov\tfp, r3\n \tldr.w\tr2, [r8, #1332]\t@ 0x534\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n \tldr.w\tr3, [r8, #1288]\t@ 0x508\n \tmla\tr3, r2, r1, r3\n \tldr.w\tr2, [r8, #1320]\t@ 0x528\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n \tmla\tr3, r2, r1, r3\n \tldr.w\tr2, [r8, #1308]\t@ 0x51c\n-\tmla\tr3, r2, r9, r3\n+\tmla\tr3, r2, fp, r3\n \tldr.w\tr2, [r8, #1304]\t@ 0x518\n \tmul.w\tr3, r2, r3\n \tldr.w\tr2, [r8, #1284]\t@ 0x504\n \tldr\tr3, [r2, r3]\n \tcmp\tr3, #0\n-\tbeq.n\t4188 <__gridxc_cell_MOD_cellxc+0x3bac>\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tmov\tr5, r1\n-\tldr.w\tr6, [r4, #512]\t@ 0x200\n-\tadd.w\tr0, r7, #820\t@ 0x334\n-\tadd.w\tr1, r7, #824\t@ 0x338\n-\tadd.w\tr2, r7, #828\t@ 0x33c\n-\tadd.w\tip, r5, r6\n+\tbeq.n\t40be <__gridxc_cell_MOD_cellxc+0x3aaa>\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tmov\tr6, r1\n+\tldr.w\tr5, [r4, #512]\t@ 0x200\n+\tadd.w\tr9, r7, #804\t@ 0x324\n+\tadd.w\tr1, r7, #808\t@ 0x328\n+\tadd.w\tr2, r7, #812\t@ 0x32c\n \tadds\tr3, #1\n-\tldr.w\tr6, [r4, #520]\t@ 0x208\n-\tldr.w\tr5, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tldr.w\tlr, [r8, #144]\t@ 0x90\n-\tadd.w\tsl, r6, r5\n+\tadd\tr6, r5\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tldr.w\tr5, [r4, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tip, [r8, #144]\t@ 0x90\n+\tadd.w\tlr, r5, r0\n \tldr.w\tr3, [r4, #504]\t@ 0x1f8\n-\tstr.w\tip, [r1]\n-\tadd\tr3, r9\n-\tstr.w\tsl, [r2]\n-\tstr\tr3, [r0, #0]\n-\tcmp.w\tlr, #0\n-\tbeq.w\t44da <__gridxc_cell_MOD_cellxc+0x3efe>\n-\tldr.w\tr5, [r8, #148]\t@ 0x94\n-\tldr.w\tr6, [r8, #168]\t@ 0xa8\n-\tmla\tr3, r6, r3, r5\n-\tldr.w\tr5, [r8, #180]\t@ 0xb4\n-\tmla\tip, r5, ip, r3\n+\tstr\tr6, [r1, #0]\n+\tadd\tr3, fp\n+\tstr.w\tlr, [r2]\n+\tstr.w\tr3, [r9]\n+\tcmp.w\tip, #0\n+\tbeq.w\t4fc6 <__gridxc_cell_MOD_cellxc+0x49b2>\n+\tldr.w\tr0, [r8, #148]\t@ 0x94\n+\tldr.w\tr5, [r8, #168]\t@ 0xa8\n+\tmla\tr3, r5, r3, r0\n+\tldr.w\tr0, [r8, #180]\t@ 0xb4\n+\tmla\tr6, r0, r6, r3\n \tldr.w\tr3, [r8, #192]\t@ 0xc0\n-\tldr.w\tr5, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr0, [r7, #796]\t@ 0x31c\n+\tcmp\tr0, #0\n+\tmla\tr3, r3, lr, r6\n+\tldrd\tr6, r5, [r8, #204]\t@ 0xcc\n+\tble.n\t41a0 <__gridxc_cell_MOD_cellxc+0x3b8c>\n+\tmla\tr3, r6, r5, r3\n+\tldr.w\tr5, [r8, #164]\t@ 0xa4\n+\tmovs\tr0, #0\n+\tmla\tr3, r5, r3, ip\n+\tmov\tip, r2\n+\tmul.w\tr5, r6, r5\n+\tldr.w\tr6, [r7, #724]\t@ 0x2d4\n+\tvldr\td7, [r3]\n+\tadds\tr0, #1\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n+\tadd\tr3, r5\n+\tcmp\tr2, r0\n+\tvstmia\tr6!, {d7}\n+\tbne.n\t418a <__gridxc_cell_MOD_cellxc+0x3b76>\n+\tmov\tr2, ip\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tldr\tr5, [r3, #0]\n \tcmp\tr5, #0\n-\tmla\tr3, r3, sl, ip\n-\tldrd\tip, r6, [r8, #204]\t@ 0xcc\n-\tble.n\t4274 <__gridxc_cell_MOD_cellxc+0x3c98>\n-\tmla\tr3, ip, r6, r3\n-\tldr.w\tr6, [r8, #164]\t@ 0xa4\n-\tmovs\tr5, #0\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tmla\tr3, r6, r3, lr\n-\tmov\tlr, fp\n-\tmul.w\tr6, ip, r6\n-\tldr.w\tip, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n-\tadds\tr5, #1\n-\tldrd\tsl, fp, [r3]\n-\tcmp\tr2, r5\n-\tadd\tr3, r6\n-\tstrd\tsl, fp, [ip], #8\n-\tbne.n\t425a <__gridxc_cell_MOD_cellxc+0x3c7e>\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tmov\tfp, lr\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tldr\tr6, [r3, #0]\n-\tcmp\tr6, #0\n-\tble.n\t429a <__gridxc_cell_MOD_cellxc+0x3cbe>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tble.n\t41d0 <__gridxc_cell_MOD_cellxc+0x3bbc>\n+\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n \tmovs\tr3, #0\n-\tvldr\td16, [r5]\n+\tvldr\td6, [pc, #644]\t@ 4438 <__gridxc_cell_MOD_cellxc+0x3e24>\n+\tvldr\td7, [r0]\n \tadds\tr3, #1\n-\tcmp\tr6, r3\n-\tvmaxnm.f64\td16, d16, d17\n-\tvstmia\tr5!, {d16}\n-\tbne.n\t4288 <__gridxc_cell_MOD_cellxc+0x3cac>\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tvcmpe.f64\td7, #0.0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tcmp\tr5, r3\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t41b4 <__gridxc_cell_MOD_cellxc+0x3ba0>\n+\tldr.w\tr5, [r7, #512]\t@ 0x200\n+\tmov\tr0, r9\n \tmov\tip, r4\n \tmov\tr3, r5\n \tbl\t0 \n \tldr.w\tr0, [r4, #556]\t@ 0x22c\n-\taddw\tr3, fp, #1428\t@ 0x594\n+\taddw\tr3, sl, #1428\t@ 0x594\n \tstr\tr3, [sp, #4]\n-\taddw\tr3, fp, #1380\t@ 0x564\n+\taddw\tr3, sl, #1380\t@ 0x564\n \tstr\tr3, [sp, #0]\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n \tmov\tr2, r5\n-\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_theta\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr6, [fp, #1620]\t@ 0x654\n-\tldr.w\tr2, [fp, #1624]\t@ 0x658\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr5, [sl, #1620]\t@ 0x654\n+\tldr.w\tr2, [sl, #1624]\t@ 0x658\n \tldr.w\tlr, [r3]\n-\tldr.w\tr3, [fp, #1764]\t@ 0x6e4\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr3, [sl, #1764]\t@ 0x6e4\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n \tcmp.w\tlr, #0\n-\tldr.w\tr3, [fp, #1768]\t@ 0x6e8\n-\tstr.w\tsp, [r7, #708]\t@ 0x2c4\n-\tble.n\t439e <__gridxc_cell_MOD_cellxc+0x3dc2>\n+\tldr.w\tr3, [sl, #1768]\t@ 0x6e8\n+\tstr.w\tsp, [r7, #696]\t@ 0x2b8\n+\tble.n\t42ce <__gridxc_cell_MOD_cellxc+0x3cba>\n \tmov.w\tr1, lr, lsl #3\n-\tmov\tr5, sp\n+\tmov\tr6, sp\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n-\tcmp\tr5, r0\n-\tbeq.n\t430e <__gridxc_cell_MOD_cellxc+0x3d32>\n+\tcmp\tr6, r0\n+\tbeq.n\t4246 <__gridxc_cell_MOD_cellxc+0x3c32>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr5, sp\n-\tcmp\tr5, r0\n+\tmov\tr6, sp\n+\tcmp\tr6, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4300 <__gridxc_cell_MOD_cellxc+0x3d24>\n+\tbne.n\t4238 <__gridxc_cell_MOD_cellxc+0x3c24>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 431e <__gridxc_cell_MOD_cellxc+0x3d42>\n+\tcbz\tr1, 4256 <__gridxc_cell_MOD_cellxc+0x3c42>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tldr.w\tr1, [pc, #1228]\t@ 47ec <__gridxc_cell_MOD_cellxc+0x4210>\n-\tadd\tr5, sp, #48\t@ 0x30\n-\tmov\tsl, r5\n+\tldr\tr1, [pc, #580]\t@ (449c <__gridxc_cell_MOD_cellxc+0x3e88>)\n+\tadd\tr6, sp, #48\t@ 0x30\n+\tmov\tr9, r6\n \tmov.w\tip, #0\n \tadd\tr1, pc\n \tldr.w\tr0, [r1, #1644]\t@ 0x66c\n \tadd\tr2, r0\n \tldr.w\tr0, [r1, #1640]\t@ 0x668\n-\tmla\tr2, r0, r2, r6\n-\tldr.w\tr6, [r1, #1644]\t@ 0x66c\n+\tmla\tr2, r0, r2, r5\n+\tldr.w\tr5, [r1, #1644]\t@ 0x66c\n \tstr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmul.w\tr0, r6, r0\n-\tldr.w\tr6, [r1, #1788]\t@ 0x6fc\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tmul.w\tr0, r5, r0\n+\tldr.w\tr5, [r1, #1788]\t@ 0x6fc\n \tldr.w\tr1, [r1, #1800]\t@ 0x708\n-\tmla\tr3, r6, r2, r3\n+\tmla\tr3, r5, r2, r3\n \tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tvldr\td16, [r2]\n-\tmov\tr6, ip\n+\tvldr\td7, [r2]\n+\tmov\tr5, ip\n \tadd.w\tip, ip, #1\n \tadd\tr2, r0\n \tcmp\tlr, ip\n-\tvstmia\tsl!, {d16}\n-\tbne.n\t435a <__gridxc_cell_MOD_cellxc+0x3d7e>\n-\tldr.w\tr2, [pc, #1152]\t@ 47f0 <__gridxc_cell_MOD_cellxc+0x4214>\n+\tvstmia\tr9!, {d7}\n+\tbne.n\t4290 <__gridxc_cell_MOD_cellxc+0x3c7c>\n+\tldr\tr2, [pc, #504]\t@ (44a0 <__gridxc_cell_MOD_cellxc+0x3e8c>)\n \tadd\tr3, r1\n-\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n-\tmov\tip, fp\n+\tldr.w\tr0, [r7, #692]\t@ 0x2b4\n \tadd\tr2, pc\n \tldr.w\tr2, [r2, #1784]\t@ 0x6f8\n \tmla\tr3, r2, r3, r0\n \tmul.w\tr2, r1, r2\n \tmovs\tr1, #0\n-\tldrd\tsl, fp, [r5], #8\n-\tcmp\tr6, r1\n-\tstrd\tsl, fp, [r3]\n+\tvldmia\tr6!, {d7}\n+\tcmp\tr5, r1\n \tadd.w\tr1, r1, #1\n+\tvstr\td7, [r3]\n \tadd\tr3, r2\n-\tbne.n\t438a <__gridxc_cell_MOD_cellxc+0x3dae>\n-\tmov\tfp, ip\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tadd.w\tr3, r9, #1\n-\tldr.w\tsp, [r7, #708]\t@ 0x2c4\n-\tcmp\tr9, r2\n-\tbne.w\t4196 <__gridxc_cell_MOD_cellxc+0x3bba>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\tbne.n\t42bc <__gridxc_cell_MOD_cellxc+0x3ca8>\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadd.w\tr3, fp, #1\n+\tldr.w\tsp, [r7, #696]\t@ 0x2b8\n+\tcmp\tfp, r2\n+\tbne.w\t40cc <__gridxc_cell_MOD_cellxc+0x3ab8>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tldr.w\tsl, [r7, #664]\t@ 0x298\n \tadds\tr3, r2, #1\n \tcmp\tr2, r1\n-\tbeq.w\t456c <__gridxc_cell_MOD_cellxc+0x3f90>\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tb.n\t4174 <__gridxc_cell_MOD_cellxc+0x3b98>\n+\tbeq.w\t6bd6 <__gridxc_cell_MOD_cellxc+0x65c2>\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tb.n\t40a6 <__gridxc_cell_MOD_cellxc+0x3a92>\n \tmovs\tr4, #0\n-\tb.n\t3cfe <__gridxc_cell_MOD_cellxc+0x3722>\n-\tldr.w\tr1, [r7, #472]\t@ 0x1d8\n-\tmov\tr5, r3\n-\tldr.w\tip, [r4, #1308]\t@ 0x51c\n-\tcmp\tr1, #0\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tble.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tcmp\tr1, #0\n-\tble.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n-\tcmp\tr1, #0\n-\tble.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tldr.w\tr0, [r7, #756]\t@ 0x2f4\n+\tb.n\t3c3c <__gridxc_cell_MOD_cellxc+0x3628>\n+\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tcmp\tr3, #0\n+\tble.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tcmp\tr3, #0\n+\tble.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tcmp\tr3, #0\n+\tble.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tldr.w\tr2, [r4, #1304]\t@ 0x518\n \tmov\tr9, r6\n-\tldr.w\tr3, [r4, #1304]\t@ 0x518\n-\tldr.w\tr1, [r4, #1332]\t@ 0x534\n-\tldr.w\tr2, [r0, #544]\t@ 0x220\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r4, #1320]\t@ 0x528\n-\tmov\tr4, r0\n-\tmul.w\tr1, r1, r3\n-\tldr.w\tr6, [r0, #540]\t@ 0x21c\n-\tstr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tvldr\td17, [pc, #884]\t@ 4790 <__gridxc_cell_MOD_cellxc+0x41b4>\n-\tmul.w\tr1, r2, r3\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr1, [r0, #528]\t@ 0x210\n-\tadd.w\tr0, r6, r2, lsl #1\n-\tadds\tr2, r6, r2\n-\tstr.w\tr9, [r7, #752]\t@ 0x2f0\n-\tadd.w\tr0, r1, r0, lsl #3\n-\tadd.w\tr1, r1, r2, lsl #3\n-\tmla\tr2, r3, r5, lr\n-\tstr.w\tr1, [r7, #740]\t@ 0x2e4\n-\tmul.w\tr3, r3, ip\n-\tldr.w\tr1, [r4, #532]\t@ 0x214\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tmov\tsl, r2\n-\tldr.w\tr3, [r4, #536]\t@ 0x218\n-\tstr.w\tr0, [r7, #736]\t@ 0x2e0\n-\tstr.w\tr1, [r7, #664]\t@ 0x298\n-\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n-\tmov.w\tr3, r9, lsl #3\n-\tmovs\tr0, #0\n-\tmov\tfp, sl\n-\tadds\tr2, r3, r2\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tmov\tr8, r0\n-\tadds\tr3, r2, r3\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr1, [r7, #680]\t@ 0x2a8\n-\tlsls\tr3, r0, #3\n-\tldr.w\tr4, [r7, #708]\t@ 0x2c4\n-\tmov\tr2, fp\n-\tadds\tr1, r3, r1\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldr.w\tr0, [r4, #1332]\t@ 0x534\n+\tldr.w\tr1, [r4, #1320]\t@ 0x528\n+\tldrd\tr5, r6, [r3, #540]\t@ 0x21c\n+\tstr.w\tr9, [r7, #776]\t@ 0x308\n+\tmul.w\tr0, r0, r2\n+\tvldr\td5, [pc, #260]\t@ 4440 <__gridxc_cell_MOD_cellxc+0x3e2c>\n+\tstr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tmul.w\tr0, r1, r2\n+\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tadd.w\tr4, r5, r6, lsl #1\n+\tldr.w\tr0, [r3, #528]\t@ 0x210\n+\tadds\tr1, r5, r6\n+\tadd.w\tr4, r0, r4, lsl #3\n+\tadd.w\tr0, r0, r1, lsl #3\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n+\tldr.w\tr0, [r3, #532]\t@ 0x214\n+\tstr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tmla\tr0, r2, sl, lr\n+\tmul.w\tr2, r2, ip\n+\tstr.w\tr4, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n+\tmov\tfp, r0\n+\tldr.w\tr2, [r3, #536]\t@ 0x218\n+\tstr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n+\tmov.w\tr1, r9, lsl #3\n+\tmov\tr8, fp\n+\tmovs\tr2, #0\n+\tadds\tr0, r1, r0\n+\tstr.w\tr0, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tadds\tr1, r0, r1\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr4, [r7, #692]\t@ 0x2b4\n+\tlsls\tr1, r2, #3\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n+\tmov\tr0, r8\n+\tadds\tr4, r1, r4\n \tmovs\tr6, #0\n-\tadd\tr4, r3\n-\tb.n\t44cc <__gridxc_cell_MOD_cellxc+0x3ef0>\n-\tvldr\td16, [r4]\n-\tcmp\tr3, #1\n-\tble.n\t44a8 <__gridxc_cell_MOD_cellxc+0x3ecc>\n-\tvldr\td18, [r1]\n-\tvadd.f64\td16, d16, d18\n-\tvcmpe.f64\td16, d17\n+\tadd\tr5, r1\n+\tb.n\t43ea <__gridxc_cell_MOD_cellxc+0x3dd6>\n+\tvldr\td7, [r5]\n+\tcmp\tr1, #1\n+\tble.n\t43c6 <__gridxc_cell_MOD_cellxc+0x3db2>\n+\tvldr\td6, [r4]\n+\tvadd.f64\td7, d7, d6\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t44d4 <__gridxc_cell_MOD_cellxc+0x3ef8>\n-\tmovs\tr3, #1\n-\tstr\tr3, [r2, #0]\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tadds\tr1, #8\n-\tldr.w\tr5, [r7, #656]\t@ 0x290\n+\tblt.n\t43f2 <__gridxc_cell_MOD_cellxc+0x3dde>\n+\tmovs\tr1, #1\n+\tstr\tr1, [r0, #0]\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n \tadds\tr4, #8\n-\tadd\tr2, r3\n-\tadds\tr3, r6, #1\n-\tcmp\tr6, r5\n-\tbeq.n\t4536 <__gridxc_cell_MOD_cellxc+0x3f5a>\n-\tmov\tr6, r3\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tcmp\tr3, #0\n-\tbgt.n\t4498 <__gridxc_cell_MOD_cellxc+0x3ebc>\n-\tmovs\tr3, #0\n-\tstr\tr3, [r2, #0]\n-\tb.n\t44b6 <__gridxc_cell_MOD_cellxc+0x3eda>\n-\tldr.w\tr3, [r4, #540]\t@ 0x21c\n-\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr6, [r4, #532]\t@ 0x214\n-\tadd\tr3, r9\n-\tmla\tr6, r6, r5, r3\n-\tldr.w\tr3, [r4, #536]\t@ 0x218\n-\tldr.w\tr5, [r7, #740]\t@ 0x2e4\n-\tmla\tr6, r3, r5, r6\n-\tldr.w\tr5, [r7, #764]\t@ 0x2fc\n-\tldr.w\tr3, [r4, #544]\t@ 0x220\n-\tcmp\tr5, #0\n-\tble.w\t4274 <__gridxc_cell_MOD_cellxc+0x3c98>\n-\tadd\tr6, r3\n-\tmov.w\tip, r3, lsl #3\n-\tldr.w\tr3, [r4, #528]\t@ 0x210\n-\tmov\tr5, lr\n-\tmov\tlr, fp\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd.w\tr3, r3, r6, lsl #3\n-\tldr.w\tr6, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n-\tadds\tr5, #1\n-\tldrd\tsl, fp, [r3]\n-\tcmp\tr2, r5\n-\tadd\tr3, ip\n-\tstrd\tsl, fp, [r6], #8\n-\tbne.n\t4520 <__gridxc_cell_MOD_cellxc+0x3f44>\n-\tb.n\t426e <__gridxc_cell_MOD_cellxc+0x3c92>\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tmov\tr3, fp\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n-\tmov\tfp, r3\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n-\tcmp\tr8, r2\n-\tadd\tr0, r3\n-\tadd.w\tr3, r8, #1\n-\tbeq.w\t47fc <__gridxc_cell_MOD_cellxc+0x4220>\n-\tmov\tr8, r3\n-\tb.n\t4484 <__gridxc_cell_MOD_cellxc+0x3ea8>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n-\tadds\tr3, r2, #1\n-\tcmp\tr2, r1\n-\tbeq.n\t456c <__gridxc_cell_MOD_cellxc+0x3f90>\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tb.n\t416a <__gridxc_cell_MOD_cellxc+0x3b8e>\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tadds\tr3, r2, #1\n-\tcmp\tr2, r1\n-\tbeq.n\t4580 <__gridxc_cell_MOD_cellxc+0x3fa4>\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tb.n\t4164 <__gridxc_cell_MOD_cellxc+0x3b88>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tcmp\tr3, #0\n-\tble.w\t5920 <__gridxc_cell_MOD_cellxc+0x5344>\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tmov.w\tsl, #1\n-\tldr\tr5, [pc, #600]\t@ (47f4 <__gridxc_cell_MOD_cellxc+0x4218>)\n-\tldr\tr4, [pc, #604]\t@ (47f8 <__gridxc_cell_MOD_cellxc+0x421c>)\n-\tldr.w\tr3, [r3, #552]\t@ 0x228\n-\tadd\tr5, pc\n-\tadd\tr4, pc\n-\tstr.w\tr3, [r7, #444]\t@ 0x1bc\n-\taddw\tr3, r5, #1836\t@ 0x72c\n-\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tldr.w\tr2, [r5, #1864]\t@ 0x748\n-\tstr.w\tr2, [r7, #608]\t@ 0x260\n-\tldr.w\tr2, [r5, #1852]\t@ 0x73c\n-\tvld1.32\t{d7}, [r3]\n-\tstr.w\tr2, [r7, #600]\t@ 0x258\n-\tadd.w\tr2, r7, #616\t@ 0x268\n-\tldr.w\tr3, [r5, #1816]\t@ 0x718\n-\tstr.w\tr3, [r7, #612]\t@ 0x264\n-\tvmov\tfp, s14\n-\tvst1.32\t{d7[1]}, [r2]\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr3, [r5, #1876]\t@ 0x754\n-\tcmp\tr2, #0\n-\tble.w\t4824 <__gridxc_cell_MOD_cellxc+0x4248>\n-\tldr.w\tr0, [r5, #1680]\t@ 0x690\n-\tldr.w\tr2, [r5, #1660]\t@ 0x67c\n-\tldr.w\tr6, [r5, #1656]\t@ 0x678\n-\tldr.w\tr1, [r5, #1764]\t@ 0x6e4\n-\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tmla\tr2, r0, sl, r2\n-\tldr.w\tr0, [r5, #1676]\t@ 0x68c\n-\tldr.w\tr1, [r5, #1788]\t@ 0x6fc\n-\tstr.w\tr1, [r7, #664]\t@ 0x298\n-\tldr.w\tr1, [r5, #1784]\t@ 0x6f8\n-\tmla\tlr, r0, r2, r6\n-\tldr.w\tr0, [r5, #1800]\t@ 0x708\n-\tldr.w\tr2, [r5, #1768]\t@ 0x6e8\n-\tstr.w\tr1, [r7, #644]\t@ 0x284\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr9, [r5, #1284]\t@ 0x504\n-\tmla\tr2, r0, sl, r2\n-\tldr.w\tr8, [r5, #1332]\t@ 0x534\n-\tstr.w\tr2, [r7, #668]\t@ 0x29c\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tadds\tr5, #8\n+\tadd\tr0, r1\n+\tadds\tr1, r6, #1\n+\tcmp\tr6, r3\n+\tbeq.n\t43f8 <__gridxc_cell_MOD_cellxc+0x3de4>\n+\tmov\tr6, r1\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n \tcmp\tr1, #0\n-\tldr.w\tr2, [r5, #1820]\t@ 0x71c\n-\tldr.w\tr0, [r5, #1288]\t@ 0x508\n-\tadd.w\tip, r3, r2\n-\tldr.w\tr2, [r5, #1308]\t@ 0x51c\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr6, [r5, #1320]\t@ 0x528\n-\tldr.w\tr2, [r5, #1304]\t@ 0x518\n-\tble.w\t4824 <__gridxc_cell_MOD_cellxc+0x4248>\n-\tmul.w\tr6, r2, r6\n-\tstr.w\tr6, [r7, #492]\t@ 0x1ec\n-\tmul.w\tr1, r2, r8\n-\tldr.w\tr6, [r7, #740]\t@ 0x2e4\n-\tmla\tr0, r2, r0, r9\n-\tstr.w\tr1, [r7, #516]\t@ 0x204\n-\tldr.w\tr1, [r7, #612]\t@ 0x264\n-\tmul.w\tr6, r2, r6\n-\tldr.w\tr2, [r7, #608]\t@ 0x260\n-\tstr.w\tr6, [r7, #740]\t@ 0x2e4\n-\tmla\tr1, fp, ip, r1\n-\tmov.w\tip, #0\n-\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n-\tmul.w\tr2, fp, r2\n-\tstr.w\tip, [r7, #624]\t@ 0x270\n-\tstr.w\tr2, [r7, #520]\t@ 0x208\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tmul.w\tr2, fp, r2\n-\tstr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tmul.w\tr2, fp, r2\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmov\tr6, sl\n-\tldr.w\tr1, [r7, #708]\t@ 0x2c4\n-\tldr.w\tsl, [r7, #656]\t@ 0x290\n-\tmov\tfp, r0\n-\tmovs\tr2, #0\n-\tstr.w\tr3, [r7, #412]\t@ 0x19c\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n-\tcmp\tr2, #0\n-\tble.n\t4740 <__gridxc_cell_MOD_cellxc+0x4164>\n-\tmov\tr9, r1\n-\tmov\tr2, fp\n-\tmov.w\tr8, #0\n-\tstrd\tr0, r6, [r7, #560]\t@ 0x230\n-\tstr.w\tr1, [r7, #544]\t@ 0x220\n-\tb.n\t4716 <__gridxc_cell_MOD_cellxc+0x413a>\n-\tldrd\tr3, r6, [r7, #664]\t@ 0x298\n-\tadd.w\tip, ip, #1\n-\tldr.w\tr1, [r7, #644]\t@ 0x284\n-\tcmp\tr8, sl\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tmla\tr6, ip, r3, r6\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tadd\tr2, r0\n-\tadd.w\tr0, r8, #1\n-\tmla\tr6, r1, r6, r3\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tvldr\td16, [r6]\n-\tvstr\td16, [r9]\n-\tadd\tr9, r3\n-\tbeq.n\t4738 <__gridxc_cell_MOD_cellxc+0x415c>\n-\tmov\tr8, r0\n-\tldr\tr0, [r2, #0]\n-\tcmp\tr0, #0\n-\tbne.n\t46e0 <__gridxc_cell_MOD_cellxc+0x4104>\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tadd.w\tr0, r8, #1\n-\tvldr\td16, [lr]\n-\tcmp\tr8, sl\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tvstr\td16, [r9]\n-\tadd\tr9, r3\n-\tbne.n\t4714 <__gridxc_cell_MOD_cellxc+0x4138>\n-\tldrd\tr0, r6, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr3, [r7, #524]\t@ 0x20c\n-\tadd\tfp, r2\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tadd\tr1, r2\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tadd.w\tr8, r2, #1\n-\tcmp\tr2, r3\n-\tbeq.n\t4762 <__gridxc_cell_MOD_cellxc+0x4186>\n-\tstr.w\tr8, [r7, #680]\t@ 0x2a8\n-\tb.n\t46c6 <__gridxc_cell_MOD_cellxc+0x40ea>\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tmov\tsl, r6\n-\tldr.w\tr1, [r7, #520]\t@ 0x208\n-\tadd\tr0, r2\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr6, [r7, #476]\t@ 0x1dc\n+\tbgt.n\t43b6 <__gridxc_cell_MOD_cellxc+0x3da2>\n+\tmovs\tr1, #0\n+\tstr\tr1, [r0, #0]\n+\tb.n\t43d4 <__gridxc_cell_MOD_cellxc+0x3dc0>\n+\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n+\tadd\tr8, r1\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tcmp\tr0, r4\n \tadd\tr2, r1\n-\tldr.w\tr1, [r7, #624]\t@ 0x270\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tadds\tr2, r1, #1\n-\tcmp\tr1, r6\n-\tbeq.n\t4824 <__gridxc_cell_MOD_cellxc+0x4248>\n-\tstr.w\tr2, [r7, #624]\t@ 0x270\n-\tb.n\t46b0 <__gridxc_cell_MOD_cellxc+0x40d4>\n+\tadd.w\tr1, r0, #1\n+\tbeq.w\t72fc <__gridxc_cell_MOD_cellxc+0x6ce8>\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n+\tb.n\t43a2 <__gridxc_cell_MOD_cellxc+0x3d8e>\n+\tldr\tr3, [pc, #132]\t@ (44a4 <__gridxc_cell_MOD_cellxc+0x3e90>)\n+\tadd\tr3, pc\n+\tldr.w\tr3, [r3, #144]\t@ 0x90\n+\tcmp\tr3, #0\n+\tbne.w\t1472 <__gridxc_cell_MOD_cellxc+0xe5e>\n+\tadd.w\tr3, r7, #968\t@ 0x3c8\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tb.w\t1aae <__gridxc_cell_MOD_cellxc+0x149a>\n+\tnop\n+\t...\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x00000d24\n+\t.word\t0x000008bc\n R_ARM_REL32\t.bss\n-\t.word\t0x00000a8e\n+\t.word\t0x00000800\n R_ARM_REL32\t.data\n-\t.word\t0x000009c2\n+\t.word\t0x0000073a\n R_ARM_REL32\t.rodata\n-\t.word\t0x000009ba\n+\t.word\t0x00000732\n R_ARM_REL32\t.bss\n-\t.word\t0x000009b8\n+\t.word\t0x00000730\n R_ARM_REL32\t.LC43\n-\t.word\t0x00000996\n+\t.word\t0x0000070e\n R_ARM_REL32\t.LC44\n-\t.word\t0x0000095e\n+\t.word\t0x000006d6\n R_ARM_REL32\t.LC46\n-\t.word\t0x0000093e\n+\t.word\t0x000006b4\n R_ARM_REL32\t.LC47\n-\t.word\t0x0000091c\n+\t.word\t0x00000692\n R_ARM_REL32\t.LC48\n-\t.word\t0x000008fa\n+\t.word\t0x0000066c\n R_ARM_REL32\t.LC49\n-\t.word\t0x000008e0\n+\t.word\t0x00000652\n R_ARM_REL32\t.LC50\n-\t.word\t0x000008c6\n+\t.word\t0x0000063a\n R_ARM_REL32\t.LC51\n-\t.word\t0x000008ac\n+\t.word\t0x00000620\n R_ARM_REL32\t.LC52\n-\t.word\t0x00000892\n+\t.word\t0x00000608\n R_ARM_REL32\t.LC53\n-\t.word\t0x0000086e\n+\t.word\t0x000005e6\n R_ARM_REL32\t.LC54\n-\t.word\t0x00000814\n+\t.word\t0x00000596\n R_ARM_REL32\t.LC55\n-\t.word\t0x0000077c\n+\t.word\t0x00000500\n R_ARM_REL32\t.bss\n-\t.word\t0x000006fc\n+\t.word\t0x0000047c\n R_ARM_REL32\t.bss\n-\t.word\t0x000006ca\n+\t.word\t0x0000044c\n R_ARM_REL32\t.bss\n-\t.word\t0x0000068e\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000660\n- R_ARM_REL32\t.bss\n-\t.word\t0x000004be\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000472\n+\t.word\t0x0000040c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000250\n+\t.word\t0x000003de\n R_ARM_REL32\t.bss\n-\t.word\t0x00000252\n+\t.word\t0x00000238\n R_ARM_REL32\t.bss\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmov\tr3, sl\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tmov\tsl, r3\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tcmp\tr2, r1\n-\tadd\tr9, r3\n-\tadd.w\tr3, r2, #1\n-\tbeq.w\t3a6c <__gridxc_cell_MOD_cellxc+0x3490>\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tb.n\t4466 <__gridxc_cell_MOD_cellxc+0x3e8a>\n-\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tr0, [r7, #600]\t@ 0x258\n-\tnegs\tr2, r2\n-\tstr\tr0, [r6, #36]\t@ 0x24\n-\tsubs\tr2, r2, r0\n-\tldr.w\tr0, [r7, #608]\t@ 0x260\n-\tstr\tr0, [r6, #48]\t@ 0x30\n-\tsubs\tr2, r2, r0\n-\tldr.w\tr0, [r4, #1844]\t@ 0x734\n-\tsubs\tr2, r2, r3\n-\tstr\tr2, [r6, #4]\n-\tldr.w\tr2, [r7, #552]\t@ 0x228\n-\trsb\tr0, r0, #1\n-\tldr.w\tr1, [r4, #1848]\t@ 0x738\n-\tadd\tr0, r1\n-\tldr.w\tr1, [r4, #1860]\t@ 0x744\n-\tvstr\td16, [r2]\n-\tldr.w\tr2, [r7, #548]\t@ 0x224\n-\tstr\tr3, [r6, #60]\t@ 0x3c\n-\tvst1.32\t{d7}, [r2]\n-\tldr.w\tr2, [r4, #1880]\t@ 0x758\n-\tstr\tr0, [r6, #32]\n-\trsb\tr2, r2, #1\n-\tldr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r7, #612]\t@ 0x264\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tldr.w\tr2, [r4, #1856]\t@ 0x740\n-\tstr\tr3, [r6, #0]\n-\trsb\tr2, r2, #1\n-\tldr.w\tr3, [r4, #1868]\t@ 0x74c\n-\tadd\tr2, r1\n-\tldr\tr1, [pc, #904]\t@ (4c20 <__gridxc_cell_MOD_cellxc+0x4644>)\n-\tstr\tr2, [r6, #44]\t@ 0x2c\n-\trsb\tr3, r3, #1\n-\tldr.w\tr2, [r4, #1872]\t@ 0x750\n-\tadd\tr1, pc\n-\tadd\tr3, r2\n-\tmov\tr2, r6\n-\tstr\tr3, [r6, #56]\t@ 0x38\n-\tmovs\tr3, #1\n-\tstr\tr3, [r6, #28]\n-\tstr\tr3, [r6, #40]\t@ 0x28\n-\tstr\tr3, [r6, #52]\t@ 0x34\n-\tstrd\tr3, r3, [r6, #64]\t@ 0x40\n-\tmovs\tr3, #8\n-\tstr\tr3, [r6, #8]\n-\tmov.w\tr3, #772\t@ 0x304\n-\tstrh\tr3, [r6, #16]\n-\tbl\t0 <__gridxc_fftr_MOD_fftr2k>\n- R_ARM_THM_CALL\t__gridxc_fftr_MOD_fftr2k\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tcmp\tr3, #0\n-\tble.w\t49f2 <__gridxc_cell_MOD_cellxc+0x4416>\n-\tldr.w\tr2, [r4, #1800]\t@ 0x708\n-\tldr.w\tr3, [r4, #1768]\t@ 0x6e8\n-\tldr.w\tr1, [r4, #1764]\t@ 0x6e4\n-\tstr.w\tr1, [r7, #668]\t@ 0x29c\n-\tldr.w\tr1, [r4, #1784]\t@ 0x6f8\n-\tmla\tr3, r2, sl, r3\n-\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr2, [r4, #1876]\t@ 0x754\n-\tldr.w\tr1, [r7, #636]\t@ 0x27c\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tldr.w\tr3, [r4, #1820]\t@ 0x71c\n-\tcmp\tr1, #0\n-\tldr.w\tr6, [r4, #1788]\t@ 0x6fc\n-\tadd\tr3, r2\n-\tldr.w\tip, [r4, #1816]\t@ 0x718\n-\tldr.w\tr0, [r4, #1864]\t@ 0x748\n-\tldr.w\tr8, [r4, #1852]\t@ 0x73c\n-\tldr.w\tlr, [r4, #1840]\t@ 0x730\n-\tldr.w\tr2, [r4, #1836]\t@ 0x72c\n-\tstr.w\tr6, [r7, #644]\t@ 0x284\n-\tble.n\t49f2 <__gridxc_cell_MOD_cellxc+0x4416>\n-\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tmla\tr3, r2, r3, ip\n-\tmul.w\tip, r2, r0\n-\tmul.w\tr0, r2, r8\n-\tstr.w\tr0, [r7, #624]\t@ 0x270\n-\tmovs\tr0, #0\n-\tmul.w\tlr, r2, lr\n-\tmul.w\tr2, r1, r6\n-\tmov\tr1, r0\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tfp, [r7, #616]\t@ 0x268\n-\tmov\tr6, sl\n-\tmovs\tr2, #0\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tstr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n-\tcmp\tr2, #0\n-\tble.n\t49b2 <__gridxc_cell_MOD_cellxc+0x43d6>\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n-\tadd.w\tr9, r2, r0\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n-\tadd.w\tr8, r0, #1\n-\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tmov\tsl, r8\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tmla\tr2, r8, r2, r3\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tmla\tr2, r1, r2, r3\n-\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tb.n\t4992 <__gridxc_cell_MOD_cellxc+0x43b6>\n-\tadd.w\tr8, r8, #1\n-\tvldr\td16, [r0]\n-\tcmp\tr8, r9\n-\tadd\tr0, lr\n-\tvstr\td16, [r2]\n-\tadd\tr2, fp\n-\tbne.n\t498e <__gridxc_cell_MOD_cellxc+0x43b2>\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tstr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tadd.w\tr0, r3, sl\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tldr.w\tr1, [r7, #640]\t@ 0x280\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tmov\tr2, r3\n-\tcmp\tr3, r1\n-\tadd.w\tr2, r2, #1\n-\tbeq.n\t49d8 <__gridxc_cell_MOD_cellxc+0x43fc>\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tb.n\t4956 <__gridxc_cell_MOD_cellxc+0x437a>\n-\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tmov\tsl, r6\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr6, [r7, #628]\t@ 0x274\n-\tadds\tr2, r1, #1\n-\tadd\tr3, ip\n-\tcmp\tr1, r6\n-\tbeq.n\t49f2 <__gridxc_cell_MOD_cellxc+0x4416>\n-\tmov\tr1, r2\n-\tb.n\t493e <__gridxc_cell_MOD_cellxc+0x4362>\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tadd.w\tsl, sl, #1\n-\tcmp\tr3, sl\n-\tbge.w\t45b0 <__gridxc_cell_MOD_cellxc+0x3fd4>\n-\tldr\tr2, [pc, #544]\t@ (4c24 <__gridxc_cell_MOD_cellxc+0x4648>)\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tadd\tr2, pc\n-\tldr.w\tr1, [r7, #604]\t@ 0x25c\n-\tadds\tr2, #4\n-\tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n- R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tmovs\tr2, #72\t@ 0x48\n-\tmovs\tr1, #0\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tcmp\tr3, #0\n-\tble.w\t5532 <__gridxc_cell_MOD_cellxc+0x4f56>\n-\tvldr\td12, [pc, #492]\t@ 4c18 <__gridxc_cell_MOD_cellxc+0x463c>\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n-\tldr.w\tr2, [r7, #636]\t@ 0x27c\n-\tcmp\tr2, #0\n-\tble.w\t5160 <__gridxc_cell_MOD_cellxc+0x4b84>\n-\tldr\tr2, [pc, #488]\t@ (4c28 <__gridxc_cell_MOD_cellxc+0x464c>)\n-\tadd\tr2, pc\n-\tstr.w\tr2, [r7, #608]\t@ 0x260\n-\tmovs\tr2, #0\n-\tstr.w\tr2, [r7, #624]\t@ 0x270\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n-\tcmp\tr2, #0\n-\tble.w\t50a2 <__gridxc_cell_MOD_cellxc+0x4ac6>\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tadd.w\tr3, r7, #820\t@ 0x334\n-\tldr.w\tr8, [r7, #604]\t@ 0x25c\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tadd.w\tr3, r7, #824\t@ 0x338\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tadd.w\tr3, r7, #828\t@ 0x33c\n-\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tadd.w\tr3, r7, #960\t@ 0x3c0\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr3, [r7, #612]\t@ 0x264\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n-\tadd.w\tr3, r3, #1488\t@ 0x5d0\n-\tstr.w\tr3, [r7, #520]\t@ 0x208\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tldr.w\tsl, [r3, #552]\t@ 0x228\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tldr.w\tip, [sl]\n-\tldr\tr2, [r3, #0]\n-\tadd.w\tr9, r2, r1\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tldr\tr1, [r3, #8]\n-\tadd.w\tlr, ip, ip, lsr #31\n-\tldr\tr3, [r3, #16]\n-\tstr.w\tr9, [r2]\n-\tcmp.w\tr9, lr, asr #1\n-\tldr.w\tr2, [r7, #624]\t@ 0x270\n-\tadd\tr1, r2\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tstr\tr1, [r2, #0]\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tstr\tr3, [r2, #0]\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tble.n\t4afe <__gridxc_cell_MOD_cellxc+0x4522>\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tsub.w\tr9, r9, ip\n-\tstr.w\tr9, [r2]\n-\tldr.w\tip, [sl, #4]\n-\tadd.w\tlr, ip, ip, lsr #31\n-\tcmp.w\tr1, lr, asr #1\n-\tble.n\t4b16 <__gridxc_cell_MOD_cellxc+0x453a>\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tsub.w\tr1, r1, ip\n-\tstr\tr1, [r2, #0]\n-\tldr.w\tr0, [sl, #8]\n-\tadd.w\tip, r0, r0, lsr #31\n-\tcmp.w\tr3, ip, asr #1\n-\tble.n\t4b2c <__gridxc_cell_MOD_cellxc+0x4550>\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tsubs\tr3, r3, r0\n-\tstr\tr3, [r2, #0]\n-\tvmov\ts15, r1\n-\tvldr\td11, [r8, #32]\n-\tvldr\td10, [r8, #24]\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r9\n-\tvldr\td22, [r8, #8]\n-\tvcvt.f64.s32\td24, s15\n-\tvldr\td20, [r8]\n-\tvmov\ts15, r3\n-\tvldr\td19, [r8, #56]\t@ 0x38\n-\tvmul.f64\td11, d16, d11\n-\tvmul.f64\td10, d16, d10\n-\tvcvt.f64.s32\td23, s15\n-\tvldr\td8, [r8, #40]\t@ 0x28\n-\tvfma.f64\td11, d24, d22\n-\tvfma.f64\td10, d24, d20\n-\tvldr\td18, [r8, #16]\n-\tvldr\td20, [r8, #48]\t@ 0x30\n-\tvmul.f64\td8, d16, d8\n-\tvldr\td16, [r8, #64]\t@ 0x40\n-\tvfma.f64\td11, d23, d19\n-\tvfma.f64\td8, d24, d18\n-\tvfma.f64\td10, d23, d20\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tvfma.f64\td8, d23, d16\n-\tvldr\td17, [r3, #-8]\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n-\tvmul.f64\td16, d11, d11\n-\tvfma.f64\td16, d10, d10\n-\tvfma.f64\td16, d8, d8\n-\tvsqrt.f64\td18, d16\n-\tvcmpe.f64\td18, d17\n-\tvstr\td18, [r3]\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t4c30 <__gridxc_cell_MOD_cellxc+0x4654>\n-\tldr\tr1, [pc, #116]\t@ (4c2c <__gridxc_cell_MOD_cellxc+0x4650>)\n-\tcmp\tr4, #0\n-\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n-\tadd\tr1, pc\n-\tldr.w\tr3, [r1, #1892]\t@ 0x764\n-\tldr.w\tr2, [r1, #1912]\t@ 0x778\n-\tmla\tr2, r2, r0, r3\n-\tldr.w\tr3, [r1, #1888]\t@ 0x760\n-\tldr.w\tr0, [r1, #1924]\t@ 0x784\n-\tble.n\t4bfa <__gridxc_cell_MOD_cellxc+0x461e>\n-\tldr.w\tr1, [r1, #1908]\t@ 0x774\n-\tadd\tr2, r0\n-\tmov.w\tsl, #0\n-\tmov.w\tfp, #0\n-\tmla\tr3, r1, r2, r3\n-\tmovs\tr2, #0\n-\tmul.w\tr1, r0, r1\n-\tadds\tr2, #1\n-\tstrd\tsl, fp, [r3]\n-\tcmp\tr4, r2\n-\tadd\tr3, r1\n-\tbne.n\t4bee <__gridxc_cell_MOD_cellxc+0x4612>\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tadds\tr3, r2, #1\n-\tcmp\tr1, r2\n-\tbeq.w\t5098 <__gridxc_cell_MOD_cellxc+0x4abc>\n-\tmov\tr1, r3\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tb.n\t4aa0 <__gridxc_cell_MOD_cellxc+0x44c4>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x0000037c\n- R_ARM_REL32\t.data\n-\t.word\t0x0000021a\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000001e6\n+\t.word\t0x000001f0\n R_ARM_REL32\t.bss\n-\t.word\t0x0000006a\n+\t.word\t0x00000082\n R_ARM_REL32\t.bss\n-\tmov\tr0, r3\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n-\tldr.w\tr2, [r7, #520]\t@ 0x208\n-\tadd.w\tr1, r3, #1536\t@ 0x600\n-\tbl\t0 <__gridxc_vdwxc_MOD_vdw_phi>\n- R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_phi\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n-\tcmp\tr4, #0\n-\tstr.w\tsp, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr2, [r3, #1584]\t@ 0x630\n-\tldr.w\tr9, [r3, #1764]\t@ 0x6e4\n-\tldr.w\tr1, [r3, #1768]\t@ 0x6e8\n-\tldr.w\tfp, [r3, #1588]\t@ 0x634\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tble.n\t4d0e <__gridxc_cell_MOD_cellxc+0x4732>\n-\tlsls\tr3, r4, #3\n-\tmov\tr0, sp\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr0, r2\n-\tbeq.n\t4c84 <__gridxc_cell_MOD_cellxc+0x46a8>\n-\tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr0, sp\n-\tcmp\tr0, r2\n-\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4c76 <__gridxc_cell_MOD_cellxc+0x469a>\n-\tubfx\tr3, r3, #0, #12\n-\tsub.w\tsp, sp, r3\n-\tcbz\tr3, 4c94 <__gridxc_cell_MOD_cellxc+0x46b8>\n-\tsubs\tr3, #4\n-\tadd\tr3, sp\n-\tstr\tr0, [r3, #0]\n-\tldr.w\tr2, [pc, #1260]\t@ 5184 <__gridxc_cell_MOD_cellxc+0x4ba8>\n-\tadd\tr0, sp, #48\t@ 0x30\n-\tmov\tlr, r0\n-\tmov.w\tip, #0\n-\tadd\tr2, pc\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r2, #1788]\t@ 0x6fc\n-\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tmla\tr3, r3, r2, r1\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tsl, [r2, #1800]\t@ 0x708\n-\tldr.w\tr1, [r2, #1784]\t@ 0x6f8\n-\tadd\tr3, sl\n-\tldr.w\tr2, [r2, #1608]\t@ 0x648\n-\tmla\tr3, r1, r3, r9\n-\tmul.w\tr1, r1, sl\n-\tvldr\td16, [r3]\n-\tmov\tr9, ip\n-\tadd.w\tip, ip, #1\n-\tadd\tr3, r1\n-\tcmp\tr4, ip\n-\tvstmia\tlr!, {d16}\n-\tbne.n\t4ccc <__gridxc_cell_MOD_cellxc+0x46f0>\n-\tldr.w\tr1, [pc, #1188]\t@ 5188 <__gridxc_cell_MOD_cellxc+0x4bac>\n-\tadd.w\tr3, r2, fp\n-\tldr.w\tr4, [r7, #724]\t@ 0x2d4\n-\tadd\tr1, pc\n-\tldr.w\tr1, [r1, #1604]\t@ 0x644\n-\tmla\tr3, r1, r3, r4\n-\tmul.w\tr2, r1, r2\n-\tmovs\tr1, #0\n-\tldrd\tsl, fp, [r0], #8\n-\tcmp\tr9, r1\n-\tstrd\tsl, fp, [r3]\n-\tadd.w\tr1, r1, #1\n-\tadd\tr3, r2\n-\tbne.n\t4cfc <__gridxc_cell_MOD_cellxc+0x4720>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tvmov.i32\td14, #0\t@ 0x00000000\n-\tldr.w\tsl, [pc, #1140]\t@ 518c <__gridxc_cell_MOD_cellxc+0x4bb0>\n-\tadd.w\tr2, r7, #1248\t@ 0x4e0\n-\tadd.w\tr9, r7, #1088\t@ 0x440\n-\tmov\tr1, r2\n-\tldr\tr4, [r3, #0]\n-\tadd\tsl, pc\n-\taddw\tr3, r7, #1100\t@ 0x44c\n-\taddw\tip, r7, #1268\t@ 0x4f4\n-\tstr.w\tr4, [r7, #1292]\t@ 0x50c\n-\tmov.w\tfp, #8\n-\tvdup.32\td16, r4\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tmul.w\tr0, r4, r4\n-\tvstr\td14, [r3]\n-\tmovs\tr3, #1\n-\tldr.w\tsp, [r7, #760]\t@ 0x2f8\n-\tstr.w\tfp, [r9, #8]\n-\tlsls\tr0, r0, #3\n-\tvstr\td16, [r2, #32]\n-\tcmp\tr0, #1\n-\tstr.w\tr3, [r7, #1276]\t@ 0x4fc\n-\tstr.w\tr3, [r7, #1288]\t@ 0x508\n-\tmov.w\tr3, #0\n-\tstr.w\tr3, [r9]\n-\tit\tcc\n-\tmovcc\tr0, #1\n-\tldr.w\tr3, [sl, #1536]\t@ 0x600\n-\tmvns\tr2, r4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tstr\tr2, [r1, #4]\n-\tldr.w\tr3, [sl, #1540]\t@ 0x604\n-\tldr.w\tr2, [sl, #1560]\t@ 0x618\n-\tvst1.32\t{d12}, [ip]\n-\tmovw\tip, #769\t@ 0x301\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n-\tstr.w\tr1, [r7, #600]\t@ 0x258\n-\tstrh.w\tip, [r9, #16]\n-\tbl\t0 \n- R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tcmp\tr4, #0\n-\tstr.w\tr0, [r7, #724]\t@ 0x2d4\n-\tmov.w\tr3, #0\n-\tstr\tr0, [r2, #0]\n-\taddw\tr0, r7, #1260\t@ 0x4ec\n-\tvstr\td14, [r0]\n-\tmovw\tr0, #770\t@ 0x302\n-\tstr.w\tfp, [r2, #8]\n-\tstrh\tr0, [r2, #16]\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tble.n\t4e36 <__gridxc_cell_MOD_cellxc+0x485a>\n-\tldr.w\tr1, [r7, #708]\t@ 0x2c4\n-\tmov\tfp, r3\n-\tldr.w\tr3, [sl, #1572]\t@ 0x624\n-\tldr.w\tr0, [sl, #1556]\t@ 0x614\n-\tadd\tr1, r3\n-\tmov\tip, r1\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadd\tip, r2\n-\tmul.w\tr3, r0, r3\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tmul.w\tlr, r2, r0\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tmla\tr1, r0, ip, r1\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tadd.w\tr1, r3, #8\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tadd.w\tip, r1, r2, lsl #3\n-\tmovs\tr3, #0\n-\tvldr\td16, [r0]\n-\tmov\tsl, r3\n-\tadds\tr3, #1\n-\tadd\tr0, lr\n-\tcmp\tr4, r3\n-\tvstmia\tip!, {d16}\n-\tbne.n\t4e08 <__gridxc_cell_MOD_cellxc+0x482c>\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tadd\tr2, r4\n-\tldr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tcmp\tfp, sl\n-\tadd\tr3, r0\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tadd.w\tr3, fp, #1\n-\tbeq.n\t4e36 <__gridxc_cell_MOD_cellxc+0x485a>\n-\tmov\tfp, r3\n-\tb.n\t4dfe <__gridxc_cell_MOD_cellxc+0x4822>\n-\taddw\tr3, r7, #1108\t@ 0x454\n-\tldr.w\tfp, [pc, #852]\t@ 5190 <__gridxc_cell_MOD_cellxc+0x4bb4>\n-\tstr.w\tr4, [r9, #32]\n-\tadd\tfp, pc\n-\tvst1.32\t{d12}, [r3]\n-\tlsls\tr3, r4, #3\n-\tcmp\tr3, #1\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tit\tcc\n-\tmovcc\tr3, #1\n-\tldr.w\tr2, [fp, #1608]\t@ 0x648\n-\tmov\tr0, r3\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r9, #28]\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr.w\tr3, [r9, #4]\n-\tldr.w\tr3, [fp, #1584]\t@ 0x630\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [fp, #1588]\t@ 0x634\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tbl\t0 \n- R_ARM_THM_CALL\tmalloc\n-\tbic.w\tlr, r4, r4, asr #31\n-\tvmov\ts15, lr\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvcvt.f32.s32\ts15, s15\n-\tmov\tsl, r0\n-\tstr.w\tr0, [r9]\n-\tcmp\tr4, #0\n-\tmovw\tr0, #769\t@ 0x301\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tvstr\td16, [r3]\n-\tvmul.f32\ts15, s15, s15\n-\tldr.w\tr3, [r7, #616]\t@ 0x268\n-\tstrh.w\tr0, [r9, #16]\n-\tble.w\t5956 <__gridxc_cell_MOD_cellxc+0x537a>\n-\tldr.w\tr0, [fp, #1604]\t@ 0x644\n-\tadd\tr3, r2\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tmov\tip, sl\n-\tmla\tr3, r0, r3, r1\n-\tmul.w\tr0, r2, r0\n-\tmovs\tr2, #0\n-\tvldr\td16, [r3]\n-\tadd\tr3, r0\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadds\tr2, #1\n-\tcmp\tr4, r2\n-\tvstmia\tip!, {d16}\n-\tbne.n\t4ece <__gridxc_cell_MOD_cellxc+0x48f2>\n-\tvldr\ts14, [pc, #668]\t@ 5180 <__gridxc_cell_MOD_cellxc+0x4ba4>\n-\tldr\tr3, [pc, #684]\t@ (5194 <__gridxc_cell_MOD_cellxc+0x4bb8>)\n-\tvcmpe.f32\ts15, s14\n-\tadd\tr3, pc\n-\tldr.w\tr1, [r3, #1728]\t@ 0x6c0\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr1, [r3, #1752]\t@ 0x6d8\n-\tbls.w\t50b6 <__gridxc_cell_MOD_cellxc+0x4ada>\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tfp, [pc, #652]\t@ 5198 <__gridxc_cell_MOD_cellxc+0x4bbc>\n-\tmovs\tr0, #8\n-\tstr\tr4, [r6, #32]\n-\tmov\tr1, r9\n-\tadd\tfp, pc\n-\tldr.w\tr2, [r7, #548]\t@ 0x224\n-\tvstr\td16, [r3]\n-\tmovs\tr3, #0\n-\tstr\tr0, [r6, #8]\n-\taddw\tr0, fp, #1748\t@ 0x6d4\n-\tvld1.32\t{d16}, [r0]\n-\tldr.w\tr0, [fp, #1756]\t@ 0x6dc\n-\tvmov.32\tip, d16[1]\n-\trsb\tr0, r0, #1\n-\tvst1.32\t{d16}, [r2]\n-\tldr.w\tr2, [fp, #1728]\t@ 0x6c0\n-\tmul.w\tr0, ip, r0\n-\trsb\tip, ip, #0\n-\tstr.w\tip, [r6, #4]\n-\tadd.w\tr0, r2, r0, lsl #3\n-\tstr\tr0, [r6, #0]\n-\tmovs\tr0, #1\n-\tstr\tr0, [r6, #28]\n-\tmovw\tr0, #769\t@ 0x301\n-\tstrh\tr0, [r6, #16]\n-\tstrd\tr3, r3, [sp]\n-\tmov\tr0, r6\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tbl\t0 <_gfortran_matmul_r8>\n- R_ARM_THM_CALL\t_gfortran_matmul_r8\n-\tldr.w\tr3, [fp, #1728]\t@ 0x6c0\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [fp, #1732]\t@ 0x6c4\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tcbz\tr3, 4f8c <__gridxc_cell_MOD_cellxc+0x49b0>\n-\tmov\tr0, r3\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tmovs\tr3, #0\n-\tstr\tr3, [r2, #0]\n-\tcmp.w\tsl, #0\n-\tbeq.n\t4f9e <__gridxc_cell_MOD_cellxc+0x49c2>\n-\tmov\tr0, sl\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r9]\n-\tldr\tr3, [pc, #508]\t@ (519c <__gridxc_cell_MOD_cellxc+0x4bc0>)\n-\tcmp\tr4, #0\n-\tstr.w\tsp, [r7, #708]\t@ 0x2c4\n-\tadd\tr3, pc\n-\tldr.w\tfp, [r3, #1888]\t@ 0x760\n-\tldr.w\tsl, [r3, #1892]\t@ 0x764\n-\tble.n\t5066 <__gridxc_cell_MOD_cellxc+0x4a8a>\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tmov\tr1, sp\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n-\tbeq.n\t4fd6 <__gridxc_cell_MOD_cellxc+0x49fa>\n-\tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n-\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4fc8 <__gridxc_cell_MOD_cellxc+0x49ec>\n-\tubfx\tr3, r3, #0, #12\n-\tsub.w\tsp, sp, r3\n-\tcbz\tr3, 4fe6 <__gridxc_cell_MOD_cellxc+0x4a0a>\n-\tsubs\tr3, #4\n-\tadd\tr3, sp\n-\tstr\tr0, [r3, #0]\n-\tldr\tr1, [pc, #440]\t@ (51a0 <__gridxc_cell_MOD_cellxc+0x4bc4>)\n-\tadd\tr0, sp, #48\t@ 0x30\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tmov\tlr, r0\n-\tadd\tr1, pc\n-\tmov.w\tip, #0\n-\tldr.w\tr2, [r1, #1752]\t@ 0x6d8\n-\tldr.w\tr9, [r1, #1748]\t@ 0x6d4\n-\tadd\tr3, r2\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tmla\tr3, r9, r3, r2\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tmul.w\tr9, r9, r2\n-\tldr.w\tr2, [r1, #1912]\t@ 0x778\n-\tldr.w\tr1, [r1, #1924]\t@ 0x784\n-\tmla\tr2, r2, r3, sl\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tvldr\td16, [r3]\n-\tmov\tsl, ip\n-\tadd.w\tip, ip, #1\n-\tadd\tr3, r9\n-\tcmp\tr4, ip\n-\tvstmia\tlr!, {d16}\n-\tbne.n\t502c <__gridxc_cell_MOD_cellxc+0x4a50>\n-\tldr\tr3, [pc, #352]\t@ (51a4 <__gridxc_cell_MOD_cellxc+0x4bc8>)\n-\tadd\tr2, r1\n-\tadd\tr3, pc\n-\tldr.w\tr4, [r3, #1908]\t@ 0x774\n-\tmla\tr3, r4, r2, fp\n-\tmul.w\tr2, r4, r1\n-\tmovs\tr1, #0\n-\tvldmia\tr0!, {d16}\n-\tcmp\tsl, r1\n-\tadd.w\tr1, r1, #1\n-\tvstr\td16, [r3]\n-\tadd\tr3, r2\n-\tbne.n\t5054 <__gridxc_cell_MOD_cellxc+0x4a78>\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n-\tvldr\td16, [pc, #268]\t@ 5178 <__gridxc_cell_MOD_cellxc+0x4b9c>\n-\tldr.w\tsp, [r7, #708]\t@ 0x2c4\n-\tvldr\td14, [r3]\n-\tvcmpe.f64\td14, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.w\t51a8 <__gridxc_cell_MOD_cellxc+0x4bcc>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n-\tldr\tr4, [r3, #0]\n-\tadds\tr3, r2, #1\n-\tcmp\tr1, r2\n-\tbne.w\t4c0a <__gridxc_cell_MOD_cellxc+0x462e>\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #624]\t@ 0x270\n-\tldr.w\tr0, [r7, #640]\t@ 0x280\n-\tadds\tr2, r1, #1\n-\tcmp\tr0, r1\n-\tbeq.n\t5160 <__gridxc_cell_MOD_cellxc+0x4b84>\n-\tstr.w\tr2, [r7, #624]\t@ 0x270\n-\tb.n\t4a4a <__gridxc_cell_MOD_cellxc+0x446e>\n-\tldr.w\tr0, [r3, #1732]\t@ 0x6c4\n-\tmov.w\tip, #0\n-\tldr.w\tr3, [r3, #1748]\t@ 0x6d4\n-\tvmov.i64\td16, #0x0000000000000000\n-\tadd.w\tfp, r0, r1\n-\tstr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n-\tmul.w\tr0, r1, r3\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr0, [r7, #564]\t@ 0x234\n-\tmov\tr0, ip\n-\tmla\tfp, r3, fp, r1\n-\tmov\tr3, fp\n-\tldr.w\tr1, [r7, #564]\t@ 0x234\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tvstr\td16, [r3]\n-\tadd\tr3, r1\n-\tcmp\tr2, r0\n-\tadd.w\tr0, r0, #1\n-\tbne.n\t50e6 <__gridxc_cell_MOD_cellxc+0x4b0a>\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tadd.w\tr1, r3, #8\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tmov\tr0, sl\n-\tvldr\td16, [fp]\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #616]\t@ 0x268\n-\tadd.w\tip, r1, r3, lsl #3\n-\tmovs\tr3, #0\n-\tvldmia\tr0!, {d18}\n-\tadds\tr3, #1\n-\tvldmia\tip!, {d17}\n-\tcmp\tr3, lr\n-\tvfma.f64\td16, d18, d17\n-\tblt.n\t5130 <__gridxc_cell_MOD_cellxc+0x4b54>\n-\tldr.w\tr3, [r7, #616]\t@ 0x268\n-\tvstr\td16, [fp]\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #616]\t@ 0x268\n-\tldr.w\tr3, [r7, #564]\t@ 0x234\n-\tadd\tfp, r3\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tcmp\tr3, lr\n-\tblt.n\t5116 <__gridxc_cell_MOD_cellxc+0x4b3a>\n-\tb.n\t4f78 <__gridxc_cell_MOD_cellxc+0x499c>\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tadd.w\tr8, r7, #848\t@ 0x350\n+\tadd.w\tr9, r7, #856\t@ 0x358\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n \tldr.w\tr1, [r7, #644]\t@ 0x284\n-\tldr.w\tr0, [r7, #628]\t@ 0x274\n-\tadds\tr2, r1, #1\n-\tcmp\tr1, r0\n-\tbge.w\t596a <__gridxc_cell_MOD_cellxc+0x538e>\n-\tstr.w\tr2, [r7, #644]\t@ 0x284\n-\tb.n\t4a32 <__gridxc_cell_MOD_cellxc+0x4456>\n-\tnop\n-\t.word\t0x9ee75616\n-\t.word\t0x3cd203af\n-\t.word\t0x44610000\n-\t.word\t0x000004e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000498\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000462\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000034a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002a4\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000280\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001f2\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001ac\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000015c\n- R_ARM_REL32\t.bss\n-\tldr.w\tr3, [r7, #548]\t@ 0x224\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tfp, [pc, #1288]\t@ 56bc <__gridxc_cell_MOD_cellxc+0x50e0>\n-\tadd.w\tr1, r7, #1128\t@ 0x468\n-\tmov.w\tsl, #8\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadd\tfp, pc\n-\tstr.w\tsl, [r7, #1136]\t@ 0x470\n-\tvst1.32\t{d12}, [r3]\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tvstr\td16, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr9, [fp, #1512]\t@ 0x5e8\n-\tldr\tr4, [r3, #0]\n-\taddw\tr3, r7, #1140\t@ 0x474\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tmvns\tr2, r4\n-\tstr\tr4, [r6, #44]\t@ 0x2c\n-\tvdup.32\td17, r4\n-\tvstr\td16, [r3]\n-\tmul.w\tr0, r4, r4\n-\tmovs\tr3, #1\n-\tstr\tr3, [r6, #28]\n-\tstr\tr3, [r6, #40]\t@ 0x28\n-\tmovs\tr3, #0\n-\tlsls\tr0, r0, #3\n-\tstr.w\tr3, [r7, #1128]\t@ 0x468\n-\tcmp\tr0, #1\n-\tldr.w\tr3, [fp, #1488]\t@ 0x5d0\n-\tit\tcc\n-\tmovcc\tr0, #1\n-\tstr\tr2, [r6, #4]\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tmovw\tr2, #769\t@ 0x301\n-\tldr.w\tr3, [fp, #1492]\t@ 0x5d4\n-\tvstr\td17, [r6, #32]\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tstrh.w\tr2, [r7, #1144]\t@ 0x478\n-\tbl\t0 \n- R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tcmp\tr4, #0\n-\tvldr\td16, [r7, #680]\t@ 0x2a8\n-\tstr.w\tsl, [r6, #8]\n+\tadd.w\tr0, r7, #844\t@ 0x34c\n+\tldr.w\tr3, [r3, #556]\t@ 0x22c\n \tmov\tsl, r0\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tvstr\td16, [r3]\n-\tmov.w\tr3, #0\n-\tstr\tr0, [r6, #0]\n-\tmovw\tr0, #770\t@ 0x302\n-\tstrh\tr0, [r6, #16]\n-\tble.n\t52ca <__gridxc_cell_MOD_cellxc+0x4cee>\n-\tldr.w\tip, [fp, #1524]\t@ 0x5f4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [fp, #1508]\t@ 0x5e4\n-\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n-\tadd\tr3, ip\n-\tadd\tr3, r9\n-\tmla\tr3, r2, r3, r0\n-\tmul.w\tr0, r2, ip\n-\tstr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tmul.w\tr2, r9, r2\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tmov.w\tr9, #4294967295\t@ 0xffffffff\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tadd.w\tr2, sl, #8\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tmov\tip, r3\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tadd.w\tlr, r2, r9, lsl #3\n-\tmovs\tr2, #0\n-\tvldr\td16, [ip]\n-\tmov\tfp, r2\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tadds\tr2, #1\n-\tcmp\tr4, r2\n-\tadd\tip, r3\n-\tvstmia\tlr!, {d16}\n-\tbne.n\t5298 <__gridxc_cell_MOD_cellxc+0x4cbc>\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd\tr9, r4\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tcmp\tr0, fp\n-\tadd\tr3, r2\n-\tadd.w\tr2, r0, #1\n-\tbeq.n\t52ca <__gridxc_cell_MOD_cellxc+0x4cee>\n-\tmov\tr0, r2\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tb.n\t5288 <__gridxc_cell_MOD_cellxc+0x4cac>\n-\tldr\tr3, [pc, #1012]\t@ (56c0 <__gridxc_cell_MOD_cellxc+0x50e4>)\n-\taddw\tr2, r7, #1148\t@ 0x47c\n-\tlsls\tr0, r4, #3\n-\tstr\tr4, [r1, #32]\n-\tadd\tr3, pc\n-\tcmp\tr0, #1\n-\tvst1.32\t{d12}, [r2]\n-\tmov.w\tr2, #1\n-\tstr\tr2, [r1, #28]\n-\tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tstr\tr2, [r1, #4]\n-\tit\tcc\n-\tmovcc\tr0, #1\n-\tldr.w\tr2, [r3, #1584]\t@ 0x630\n-\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr2, [r3, #1588]\t@ 0x634\n-\tldr.w\tr9, [r3, #1608]\t@ 0x648\n-\tstr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr2, [r7, #676]\t@ 0x2a4\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tbl\t0 \n- R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr3, [r7, #600]\t@ 0x258\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr1, [r7, #724]\t@ 0x2d4\n-\tmovw\tr2, #769\t@ 0x301\n-\tmov\tfp, r0\n-\tcmp\tr4, #0\n-\tvstr\td16, [r3]\n-\tbic.w\tr3, r4, r4, asr #31\n-\tvmov\ts15, r3\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tstr\tr0, [r1, #0]\n-\tvcvt.f32.s32\ts15, s15\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tstrh\tr2, [r1, #16]\n-\tvmul.f32\ts15, s15, s15\n-\tble.w\t5982 <__gridxc_cell_MOD_cellxc+0x53a6>\n-\tldr.w\tr2, [r3, #1604]\t@ 0x644\n-\tmov\tip, fp\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n-\tadd\tr3, r9\n-\tmla\tr3, r2, r3, r0\n-\tmovs\tr0, #0\n-\tmul.w\tr2, r9, r2\n-\tvldr\td16, [r3]\n-\tadd\tr3, r2\n-\tstr.w\tr0, [r7, #616]\t@ 0x268\n-\tadds\tr0, #1\n-\tcmp\tr4, r0\n-\tvstmia\tip!, {d16}\n-\tbne.n\t535e <__gridxc_cell_MOD_cellxc+0x4d82>\n-\tvldr\ts14, [pc, #836]\t@ 56b8 <__gridxc_cell_MOD_cellxc+0x50dc>\n-\tldr\tr3, [pc, #844]\t@ (56c4 <__gridxc_cell_MOD_cellxc+0x50e8>)\n-\tvcmpe.f32\ts15, s14\n-\tadd\tr3, pc\n-\tldr.w\tr2, [r3, #1344]\t@ 0x540\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr2, [r3, #1368]\t@ 0x558\n-\tbls.w\t59ac <__gridxc_cell_MOD_cellxc+0x53d0>\n-\tldr.w\tr9, [pc, #820]\t@ 56c8 <__gridxc_cell_MOD_cellxc+0x50ec>\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tadd.w\tr0, r7, #1168\t@ 0x490\n-\tstr\tr4, [r0, #32]\n-\tadd\tr9, pc\n-\taddw\tr3, r9, #1364\t@ 0x554\n-\tldr.w\tr2, [r9, #1344]\t@ 0x540\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r9, #1372]\t@ 0x55c\n-\tvmov.32\tip, d16[1]\n-\trsb\tr3, r3, #1\n-\tmul.w\tr3, ip, r3\n-\tadd.w\tr2, r2, r3, lsl #3\n-\trsb\tr3, ip, #0\n-\tstr\tr3, [r0, #4]\n-\taddw\tr3, r7, #1180\t@ 0x49c\n-\tstr\tr2, [r0, #0]\n-\tmovs\tr2, #8\n-\tstr\tr2, [r0, #8]\n-\tmovs\tr2, #1\n-\tvstr\td17, [r3]\n-\taddw\tr3, r7, #1188\t@ 0x4a4\n-\tstr\tr2, [r0, #28]\n-\tmovw\tr2, #769\t@ 0x301\n-\tstrh\tr2, [r0, #16]\n-\tmov\tr2, r6\n-\tvst1.32\t{d16}, [r3]\n-\tmovs\tr3, #0\n-\tstrd\tr3, r3, [sp]\n-\tbl\t0 <_gfortran_matmul_r8>\n- R_ARM_THM_CALL\t_gfortran_matmul_r8\n-\tldr.w\tr3, [r9, #1344]\t@ 0x540\n-\tstr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr3, [r9, #1348]\t@ 0x544\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tldr.w\tr3, [r9, #1584]\t@ 0x630\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr3, [r9, #1588]\t@ 0x634\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr3, [r9, #1368]\t@ 0x558\n-\tldr.w\tr9, [r9, #1608]\t@ 0x648\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tcmp.w\tsl, #0\n-\tbeq.n\t542c <__gridxc_cell_MOD_cellxc+0x4e50>\n-\tmov\tr0, sl\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tcmp.w\tfp, #0\n-\tbeq.n\t5438 <__gridxc_cell_MOD_cellxc+0x4e5c>\n-\tmov\tr0, fp\n-\tbl\t0 \n- R_ARM_THM_CALL\tfree\n-\tvdiv.f64\td17, d13, d14\n-\tldr\tr0, [pc, #652]\t@ (56cc <__gridxc_cell_MOD_cellxc+0x50f0>)\n-\tadd\tr0, pc\n-\tldr.w\tip, [r0, #1372]\t@ 0x55c\n-\tldr.w\tr1, [r0, #1376]\t@ 0x560\n-\tldr.w\tr3, [r0, #1612]\t@ 0x64c\n-\tcmp\tip, r1\n-\tbgt.w\t5a54 <__gridxc_cell_MOD_cellxc+0x5478>\n-\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n-\tadds\tr1, #1\n-\tsub.w\tr1, r1, ip\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmla\tsl, r9, r3, r2\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmla\tlr, r2, ip, r3\n-\tldr.w\tip, [r0, #1364]\t@ 0x554\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tmla\tlr, ip, lr, r3\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tmul.w\tip, r2, ip\n-\tldr.w\tr2, [r0, #1604]\t@ 0x644\n-\tmovs\tr0, #0\n-\tmla\tr3, r2, sl, r3\n-\tmul.w\tr2, r9, r2\n-\tvldr\td19, [lr]\n-\tadds\tr0, #1\n-\tvldr\td18, [r3]\n-\tadd\tlr, ip\n-\tadd\tr3, r2\n-\tcmp\tr1, r0\n-\tvfma.f64\td16, d19, d18\n-\tbne.n\t5492 <__gridxc_cell_MOD_cellxc+0x4eb6>\n-\tvmul.f64\td16, d16, d17\n-\tvmul.f64\td27, d10, d16\n-\tvmul.f64\td26, d11, d16\n-\tvmul.f64\td25, d8, d16\n-\tvldr\td22, [r5]\n-\tvldr\td21, [r5, #8]\n-\tmovs\tr3, #4\n-\tvldr\td20, [r5, #16]\n-\tvldr\td19, [r5, #24]\n-\tvfms.f64\td22, d10, d27\n-\tvldr\td18, [r5, #32]\n-\tvfms.f64\td21, d11, d27\n-\tvldr\td17, [r5, #40]\t@ 0x28\n-\tvfms.f64\td20, d8, d27\n-\tvldr\td16, [r5, #48]\t@ 0x30\n-\tvfms.f64\td19, d10, d26\n-\tvldr\td23, [r5, #56]\t@ 0x38\n-\tvfms.f64\td18, d11, d26\n-\tvldr\td24, [r5, #64]\t@ 0x40\n-\tvfms.f64\td17, d8, d26\n-\tvfms.f64\td16, d10, d25\n-\tvfms.f64\td23, d11, d25\n-\tvfms.f64\td24, d8, d25\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tvstr\td22, [r5]\n-\tvstr\td21, [r5, #8]\n-\tstr.w\tr3, [r2, #548]\t@ 0x224\n-\tvstr\td20, [r5, #16]\n-\tvstr\td19, [r5, #24]\n-\tvstr\td18, [r5, #32]\n-\tvstr\td17, [r5, #40]\t@ 0x28\n-\tvstr\td16, [r5, #48]\t@ 0x30\n-\tvstr\td23, [r5, #56]\t@ 0x38\n-\tvstr\td24, [r5, #64]\t@ 0x40\n-\tb.w\t4bfa <__gridxc_cell_MOD_cellxc+0x461e>\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tldr\tr5, [pc, #396]\t@ (56d0 <__gridxc_cell_MOD_cellxc+0x50f4>)\n-\tldr\tr4, [pc, #400]\t@ (56d4 <__gridxc_cell_MOD_cellxc+0x50f8>)\n-\tldr.w\tr3, [r3, #552]\t@ 0x228\n-\tadd\tr5, pc\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tadd\tr4, pc\n-\tmovs\tr3, #1\n-\taddw\tr2, r5, #1956\t@ 0x7a4\n-\tstr.w\tr2, [r7, #564]\t@ 0x234\n-\tldr.w\tr2, [r7, #564]\t@ 0x234\n-\tldr.w\tr1, [r5, #1984]\t@ 0x7c0\n-\tstr.w\tr1, [r7, #644]\t@ 0x284\n-\tldr.w\tr1, [r5, #1972]\t@ 0x7b4\n-\tvld1.32\t{d7}, [r2]\n-\tstr.w\tr1, [r7, #624]\t@ 0x270\n-\tadd.w\tr1, r7, #668\t@ 0x29c\n-\tldr.w\tr2, [r5, #1936]\t@ 0x790\n-\tstr.w\tr2, [r7, #664]\t@ 0x298\n-\tvmov\tr6, s14\n-\tvst1.32\t{d7[1]}, [r1]\n-\tldr.w\tr1, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr2, [r5, #1996]\t@ 0x7cc\n-\tcmp\tr1, #0\n-\tble.w\t56d8 <__gridxc_cell_MOD_cellxc+0x50fc>\n-\tldr.w\tr0, [r5, #1924]\t@ 0x784\n-\tldr.w\tr1, [r5, #1892]\t@ 0x764\n-\tmla\tr1, r0, r3, r1\n-\tldr.w\tr0, [r5, #1888]\t@ 0x760\n-\tstr.w\tr0, [r7, #616]\t@ 0x268\n-\tldr.w\tr0, [r5, #1912]\t@ 0x778\n-\tstr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr0, [r5, #1908]\t@ 0x774\n-\tstr.w\tr1, [r7, #612]\t@ 0x264\n-\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr1, [r5, #1940]\t@ 0x794\n-\tldr.w\tr0, [r7, #636]\t@ 0x27c\n-\tadd\tr1, r2\n-\tcmp\tr0, #0\n-\tble.w\t56d8 <__gridxc_cell_MOD_cellxc+0x50fc>\n-\tldr.w\tr0, [r7, #664]\t@ 0x298\n-\tmla\tr9, r6, r1, r0\n-\tldr.w\tr1, [r7, #644]\t@ 0x284\n-\tmovs\tr0, #0\n-\tmul.w\tr1, r6, r1\n-\tstr.w\tr1, [r7, #608]\t@ 0x260\n-\tldr.w\tr1, [r7, #624]\t@ 0x270\n-\tmul.w\tr1, r6, r1\n-\tstr.w\tr1, [r7, #604]\t@ 0x25c\n-\tldr.w\tr1, [r7, #668]\t@ 0x29c\n-\tmul.w\tip, r6, r1\n-\tldr.w\tr6, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tmul.w\tlr, r1, r6\n-\tmov\tr6, r0\n-\tmovs\tr1, #0\n-\tstr.w\tr1, [r7, #676]\t@ 0x2a4\n-\tmov\tr1, r9\n-\tstr.w\tr9, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n-\tcmp\tr3, #0\n-\tble.n\t5674 <__gridxc_cell_MOD_cellxc+0x5098>\n-\tadd.w\tr8, r0, #1\n-\tadd.w\tsl, r3, r0\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n-\tmov\tfp, r8\n-\tldr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr9, [r7, #752]\t@ 0x2f0\n-\tmla\tr0, r8, r0, r3\n-\tldr.w\tr3, [r7, #616]\t@ 0x268\n-\tmla\tr0, r2, r0, r3\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tb.n\t5654 <__gridxc_cell_MOD_cellxc+0x5078>\n-\tadd.w\tr8, r8, #1\n-\tvldr\td16, [r0]\n-\tcmp\tr8, sl\n-\tadd\tr0, lr\n-\tvstr\td16, [r9]\n-\tadd\tr9, ip\n-\tbne.n\t5650 <__gridxc_cell_MOD_cellxc+0x5074>\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tadd.w\tr0, r3, fp\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #604]\t@ 0x25c\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #640]\t@ 0x280\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tadd.w\tr8, r3, #1\n-\tcmp\tr2, r3\n-\tbeq.n\t5698 <__gridxc_cell_MOD_cellxc+0x50bc>\n-\tstr.w\tr8, [r7, #676]\t@ 0x2a4\n-\tb.n\t5618 <__gridxc_cell_MOD_cellxc+0x503c>\n-\tmov\tr9, r1\n-\tldr.w\tr1, [r7, #608]\t@ 0x260\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tadd.w\tr8, r6, #1\n-\tadd\tr9, r1\n-\tldr.w\tr1, [r7, #628]\t@ 0x274\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tcmp\tr6, r1\n-\tbeq.n\t56d8 <__gridxc_cell_MOD_cellxc+0x50fc>\n-\tmov\tr6, r8\n-\tb.n\t5604 <__gridxc_cell_MOD_cellxc+0x5028>\n-\t.word\t0x44610000\n-\t.word\t0x000004f8\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003e8\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000344\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000324\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000028a\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000184\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000182\n- R_ARM_REL32\t.bss\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n-\tldr.w\tr0, [r7, #624]\t@ 0x270\n-\tnegs\tr1, r3\n-\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n-\tsubs\tr1, r1, r0\n-\tldr.w\tr6, [r4, #1964]\t@ 0x7ac\n-\tstr\tr0, [r3, #36]\t@ 0x24\n-\trsb\tr6, r6, #1\n-\tldr.w\tr0, [r7, #644]\t@ 0x284\n-\tstr\tr0, [r3, #48]\t@ 0x30\n-\tsubs\tr1, r1, r0\n-\tldr.w\tr0, [r4, #1968]\t@ 0x7b0\n-\tsubs\tr1, r1, r2\n-\tstr\tr1, [r3, #4]\n-\tldr.w\tr1, [r7, #552]\t@ 0x228\n-\tadd\tr6, r0\n-\tldr.w\tr0, [r4, #1980]\t@ 0x7bc\n-\tvstr\td16, [r1]\n-\tldr.w\tr1, [r7, #548]\t@ 0x224\n-\tstr\tr2, [r3, #60]\t@ 0x3c\n-\tvst1.32\t{d7}, [r1]\n-\tldr.w\tr1, [r4, #2000]\t@ 0x7d0\n-\tstr\tr6, [r3, #32]\n-\tmovs\tr6, #1\n-\trsb\tr1, r1, #1\n-\tstr\tr6, [r3, #28]\n-\tstr\tr6, [r3, #40]\t@ 0x28\n-\tstr\tr6, [r3, #52]\t@ 0x34\n-\tmul.w\tr2, r1, r2\n-\tldr.w\tr1, [r7, #664]\t@ 0x298\n-\tstrd\tr6, r6, [r3, #64]\t@ 0x40\n-\tmovs\tr6, #8\n-\tstr\tr6, [r3, #8]\n-\tmov.w\tr6, #772\t@ 0x304\n-\tadd.w\tr2, r1, r2, lsl #3\n-\tldr.w\tr1, [r4, #1976]\t@ 0x7b8\n-\tstr\tr2, [r3, #0]\n-\trsb\tr1, r1, #1\n-\tldr.w\tr2, [r4, #1988]\t@ 0x7c4\n-\tadd\tr1, r0\n-\tstr\tr1, [r3, #44]\t@ 0x2c\n-\tldr.w\tr1, [r4, #1992]\t@ 0x7c8\n-\trsb\tr2, r2, #1\n-\tldr.w\tr0, [r7, #600]\t@ 0x258\n-\tadd\tr2, r1\n-\tldr.w\tr1, [pc, #1316]\t@ 5c94 <__gridxc_cell_MOD_cellxc+0x56b8>\n-\tstr\tr2, [r3, #56]\t@ 0x38\n-\tmov\tr2, r3\n-\tadd\tr1, pc\n-\tstrh\tr6, [r3, #16]\n-\tbl\t0 <__gridxc_fftr_MOD_fftk2r>\n- R_ARM_THM_CALL\t__gridxc_fftr_MOD_fftk2r\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tcmp\tr3, #0\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tble.w\t5910 <__gridxc_cell_MOD_cellxc+0x5334>\n-\tldr.w\tr1, [r4, #1924]\t@ 0x784\n-\tldr.w\tr2, [r4, #1892]\t@ 0x764\n-\tldr.w\tr0, [r4, #1888]\t@ 0x760\n-\tstr.w\tr0, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr0, [r4, #1912]\t@ 0x778\n-\tmla\tr2, r1, r3, r2\n-\tldr.w\tr1, [r4, #1996]\t@ 0x7cc\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [r4, #1940]\t@ 0x794\n-\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n-\tadd.w\tip, r1, r2\n-\tldr.w\tr2, [r4, #1332]\t@ 0x534\n-\tldr.w\tr0, [r4, #1908]\t@ 0x774\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr2, [r4, #1308]\t@ 0x51c\n-\tstr.w\tr2, [r7, #664]\t@ 0x298\n-\tstr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr2, [r4, #1984]\t@ 0x7c0\n-\tldr.w\tr0, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr1, [r4, #1320]\t@ 0x528\n-\tstr.w\tr2, [r7, #644]\t@ 0x284\n-\tcmp\tr0, #0\n-\tldr.w\tr2, [r4, #1972]\t@ 0x7b4\n-\tstr.w\tr1, [r7, #668]\t@ 0x29c\n-\tstr.w\tr2, [r7, #624]\t@ 0x270\n-\tldr.w\tr9, [r4, #1284]\t@ 0x504\n-\tldr.w\tr6, [r4, #1288]\t@ 0x508\n-\tldr.w\tr1, [r4, #1304]\t@ 0x518\n-\tldr.w\tr8, [r4, #1936]\t@ 0x790\n-\tldr.w\tlr, [r4, #1960]\t@ 0x7a8\n-\tldr.w\tr2, [r4, #1956]\t@ 0x7a4\n-\tble.w\t5910 <__gridxc_cell_MOD_cellxc+0x5334>\n-\tmla\tr0, r1, r6, r9\n-\tldr.w\tr6, [r7, #740]\t@ 0x2e4\n-\tmla\tip, r2, ip, r8\n-\tstr.w\tip, [r7, #752]\t@ 0x2f0\n-\tmul.w\tlr, r2, lr\n-\tmul.w\tr6, r1, r6\n-\tstr.w\tr6, [r7, #616]\t@ 0x268\n-\tldr.w\tr6, [r7, #644]\t@ 0x284\n-\tmul.w\tr6, r2, r6\n-\tstr.w\tr6, [r7, #644]\t@ 0x284\n-\tldr.w\tr6, [r7, #668]\t@ 0x29c\n-\tmul.w\tr6, r1, r6\n-\tstr.w\tr6, [r7, #612]\t@ 0x264\n-\tldr.w\tr6, [r7, #664]\t@ 0x298\n-\tmul.w\tip, r1, r6\n-\tldr.w\tr1, [r7, #624]\t@ 0x270\n-\tmovs\tr6, #0\n-\tstr.w\tr6, [r7, #668]\t@ 0x29c\n-\tmul.w\tr1, r2, r1\n-\tstr.w\tr1, [r7, #624]\t@ 0x270\n-\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n-\tmov\tfp, r3\n-\tldr.w\tsl, [r7, #656]\t@ 0x290\n-\tmovs\tr2, #0\n-\tstr.w\tr0, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr2, [r7, #664]\t@ 0x298\n-\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n-\tcmp\tr2, #0\n-\tble.n\t58ba <__gridxc_cell_MOD_cellxc+0x52de>\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tmov\tr9, r1\n-\tmov.w\tr8, #0\n-\tstrd\tr1, fp, [r7, #604]\t@ 0x25c\n-\tb.n\t5884 <__gridxc_cell_MOD_cellxc+0x52a8>\n-\tmov\tr8, fp\n-\tldr\tr3, [r2, #0]\n-\tcbz\tr3, 58aa <__gridxc_cell_MOD_cellxc+0x52ce>\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tadds\tr6, #1\n-\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n-\tvldr\td16, [r9]\n-\tmla\tfp, r6, r1, r3\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr1, [r7, #676]\t@ 0x2a4\n-\tmla\tfp, r1, fp, r3\n-\tvstr\td16, [fp]\n-\tadd\tr2, ip\n-\tadd\tr9, lr\n-\tadd.w\tfp, r8, #1\n-\tcmp\tr8, sl\n-\tbne.n\t5882 <__gridxc_cell_MOD_cellxc+0x52a6>\n-\tldrd\tr1, fp, [r7, #604]\t@ 0x25c\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #624]\t@ 0x270\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tadd\tr1, r3\n+\tldr.w\tr5, [r7, #636]\t@ 0x27c\n+\tstr.w\tr2, [r7, #852]\t@ 0x354\n+\tldr\tr4, [r3, #0]\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tldr.w\tr3, [r7, #524]\t@ 0x20c\n-\tadd.w\tr8, r2, #1\n-\tcmp\tr2, r3\n-\tbeq.n\t58e4 <__gridxc_cell_MOD_cellxc+0x5308>\n-\tstr.w\tr8, [r7, #664]\t@ 0x298\n-\tb.n\t586a <__gridxc_cell_MOD_cellxc+0x528e>\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tmov\tr3, fp\n-\tldr.w\tr1, [r7, #644]\t@ 0x284\n-\tadd\tr0, r2\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tadd\tr2, r1\n-\tldr.w\tr1, [r7, #668]\t@ 0x29c\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tadd.w\tr8, r1, #1\n-\tcmp\tr1, r2\n-\tbeq.n\t5910 <__gridxc_cell_MOD_cellxc+0x5334>\n-\tstr.w\tr8, [r7, #668]\t@ 0x29c\n-\tb.n\t5856 <__gridxc_cell_MOD_cellxc+0x527a>\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tadds\tr3, #1\n-\tcmp\tr2, r3\n-\tbge.w\t555a <__gridxc_cell_MOD_cellxc+0x4f7e>\n-\tb.w\t1ca8 <__gridxc_cell_MOD_cellxc+0x16cc>\n-\tldr\tr2, [pc, #884]\t@ (5c98 <__gridxc_cell_MOD_cellxc+0x56bc>)\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tadd\tr2, pc\n-\tldr.w\tr1, [r7, #604]\t@ 0x25c\n-\tadds\tr2, #4\n-\tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n- R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tmovs\tr2, #72\t@ 0x48\n-\tmovs\tr1, #0\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemset\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tcmp\tr3, #0\n-\tbgt.w\t4a28 <__gridxc_cell_MOD_cellxc+0x444c>\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tb.w\t1ca8 <__gridxc_cell_MOD_cellxc+0x16cc>\n-\tvldr\ts14, [pc, #824]\t@ 5c90 <__gridxc_cell_MOD_cellxc+0x56b4>\n-\tvcmpe.f32\ts15, s14\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t4f02 <__gridxc_cell_MOD_cellxc+0x4926>\n-\tb.w\t4f68 <__gridxc_cell_MOD_cellxc+0x498c>\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tcmp\tr3, #0\n-\tbgt.w\t553c <__gridxc_cell_MOD_cellxc+0x4f60>\n-\tb.w\t1ca8 <__gridxc_cell_MOD_cellxc+0x16cc>\n-\tvldr\ts14, [pc, #780]\t@ 5c90 <__gridxc_cell_MOD_cellxc+0x56b4>\n-\tvcmpe.f32\ts15, s14\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t5392 <__gridxc_cell_MOD_cellxc+0x4db6>\n-\tldr.w\tr2, [r3, #1344]\t@ 0x540\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr2, [r3, #1348]\t@ 0x544\n-\tldr.w\tr3, [r3, #1368]\t@ 0x558\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tb.n\t5420 <__gridxc_cell_MOD_cellxc+0x4e44>\n-\tldr.w\tr1, [r3, #1348]\t@ 0x544\n-\tvmov.i64\td16, #0x0000000000000000\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tmov.w\tip, #0\n-\tldr.w\tr1, [r3, #1364]\t@ 0x554\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmla\tr3, r1, r3, r2\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tmul.w\tr2, r2, r1\n-\tmov\tr1, r3\n-\tstr.w\tr2, [r7, #600]\t@ 0x258\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tvstr\td16, [r1]\n-\tadd\tr1, r2\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tcmp\tr2, ip\n-\tadd.w\tip, ip, #1\n-\tbne.n\t59e0 <__gridxc_cell_MOD_cellxc+0x5404>\n-\tmov.w\tip, #4294967295\t@ 0xffffffff\n-\tmovs\tr2, #0\n-\tadd.w\tr1, sl, #8\n-\tstr.w\tr1, [r7, #616]\t@ 0x268\n-\tldr.w\tr1, [r7, #616]\t@ 0x268\n-\tadds\tr2, #1\n-\tvldr\td16, [r3]\n-\tstr.w\tfp, [r7, #564]\t@ 0x234\n-\tadd.w\tlr, r1, ip, lsl #3\n-\tmovs\tr1, #0\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #564]\t@ 0x234\n-\tadds\tr1, #1\n-\tvldmia\tlr!, {d17}\n-\tvldmia\tr3!, {d18}\n-\tstr.w\tr3, [r7, #564]\t@ 0x234\n-\tvfma.f64\td16, d18, d17\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr1, r3\n-\tblt.n\t5a1c <__gridxc_cell_MOD_cellxc+0x5440>\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tadd\tip, r0\n-\tldr.w\tr1, [r7, #600]\t@ 0x258\n-\tvstr\td16, [r3]\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tcmp\tr2, r1\n-\tblt.n\t5a04 <__gridxc_cell_MOD_cellxc+0x5428>\n-\tb.n\t5420 <__gridxc_cell_MOD_cellxc+0x4e44>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tb.n\t54ac <__gridxc_cell_MOD_cellxc+0x4ed0>\n-\tadd.w\tr3, r7, #992\t@ 0x3e0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tb.w\t1750 <__gridxc_cell_MOD_cellxc+0x1174>\n-\tldr\tr3, [pc, #564]\t@ (5c9c <__gridxc_cell_MOD_cellxc+0x56c0>)\n-\tadd\tr3, pc\n-\tldr.w\tr3, [r3, #144]\t@ 0x90\n-\tcmp\tr3, #0\n-\tbne.w\t140e <__gridxc_cell_MOD_cellxc+0xe32>\n-\tadd.w\tr3, r7, #984\t@ 0x3d8\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tadd.w\tr3, r7, #992\t@ 0x3e0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tb.w\t1a0c <__gridxc_cell_MOD_cellxc+0x1430>\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tadd.w\tr0, r7, #860\t@ 0x35c\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tmov\tr5, r0\n-\tldr.w\tr1, [r7, #668]\t@ 0x29c\n-\tadd.w\tr8, r7, #864\t@ 0x360\n-\tldr.w\tr3, [r3, #556]\t@ 0x22c\n-\tmov\tfp, r0\n-\tstr.w\tr2, [r7, #868]\t@ 0x364\n-\tadd.w\tr2, r7, #872\t@ 0x368\n-\tstr.w\tr1, [r7, #872]\t@ 0x368\n-\tadd.w\tr1, r7, #876\t@ 0x36c\n-\tmov\tr0, r2\n-\tmov\tsl, r2\n-\tmov\tr2, r1\n-\tldr.w\tr9, [r3]\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr1, [r7, #664]\t@ 0x298\n-\tldr.w\tr4, [r7, #652]\t@ 0x28c\n-\tstr.w\tr3, [r7, #860]\t@ 0x35c\n+\tmov\tfp, r4\n+\tstr.w\tr3, [r7, #844]\t@ 0x34c\n \tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tstr\tr1, [r2, #0]\n-\tadd.w\tr1, r7, #880\t@ 0x370\n \tstr.w\tr3, [r8]\n-\tadd.w\tr3, r7, #868\t@ 0x364\n+\tadd.w\tr3, r7, #852\t@ 0x354\n+\tstr.w\tr2, [r9]\n+\tadd.w\tr2, r7, #860\t@ 0x35c\n+\tstr.w\tr1, [r7, #860]\t@ 0x35c\n+\tadd.w\tr1, r7, #864\t@ 0x360\n+\tstr.w\tr5, [r7, #864]\t@ 0x360\n+\tadd.w\tr5, r7, #880\t@ 0x370\n \tstr.w\tr4, [r7, #880]\t@ 0x370\n-\tadd.w\tr4, r7, #896\t@ 0x380\n-\tstr.w\tr9, [r7, #896]\t@ 0x380\n-\tstr.w\tr4, [r7, #760]\t@ 0x2f8\n-\tstr\tr4, [sp, #16]\n-\tstr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr5, [r7, #784]\t@ 0x310\n+\tstr\tr5, [sp, #16]\n+\tstr.w\tr1, [r7, #744]\t@ 0x2e8\n \tstr\tr1, [sp, #8]\n-\tmov\tr1, r5\n+\tmov\tr1, r0\n \tstr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [pc, #412]\t@ (5ca0 <__gridxc_cell_MOD_cellxc+0x56c4>)\n-\tldr\tr6, [pc, #416]\t@ (5ca4 <__gridxc_cell_MOD_cellxc+0x56c8>)\n+\tldr.w\tr3, [pc, #1244]\t@ 49f8 <__gridxc_cell_MOD_cellxc+0x43e4>\n+\tldr.w\tr6, [pc, #1244]\t@ 49fc <__gridxc_cell_MOD_cellxc+0x43e8>\n \tadd\tr3, pc\n-\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n \tadds\tr4, r3, #4\n-\tldr\tr3, [pc, #408]\t@ (5ca8 <__gridxc_cell_MOD_cellxc+0x56cc>)\n+\tldr.w\tr3, [pc, #1236]\t@ 4a00 <__gridxc_cell_MOD_cellxc+0x43ec>\n \tadd\tr6, pc\n \tstr\tr2, [sp, #0]\n \tadd\tr3, pc\n-\tstr.w\tr4, [r7, #752]\t@ 0x2f0\n-\tmov\tr2, r0\n-\tstr\tr4, [sp, #12]\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tmov\tr2, r9\n \tadd.w\tr0, r6, #144\t@ 0x90\n+\tstr\tr4, [sp, #12]\n \tmovs\tr4, #0\n \tstr\tr3, [sp, #20]\n \tmovs\tr3, #13\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr3, r8\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #24]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #40]\t@ 0x28\n-\tmov\tr2, sl\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n \tadd.w\tr0, r6, #564\t@ 0x234\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr1, [r7, #744]\t@ 0x2e8\n \tstr\tr1, [sp, #8]\n-\tmov\tr1, r5\n+\tmov\tr1, sl\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [pc, #324]\t@ (5cac <__gridxc_cell_MOD_cellxc+0x56d0>)\n+\tldr.w\tr3, [pc, #1156]\t@ 4a04 <__gridxc_cell_MOD_cellxc+0x43f0>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadd\tr3, pc\n+\tstr\tr2, [sp, #0]\n \tstr\tr3, [sp, #20]\n+\tmov\tr2, r9\n \tmovs\tr3, #12\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.w\t65ce <__gridxc_cell_MOD_cellxc+0x5ff2>\n-\tmul.w\tr3, r9, r9\n-\tadd.w\tr2, r7, #984\t@ 0x3d8\n-\tstr.w\tr3, [r7, #984]\t@ 0x3d8\n+\tbeq.w\t4fba <__gridxc_cell_MOD_cellxc+0x49a6>\n+\tmov\tr3, fp\n+\tadd.w\tr2, r7, #968\t@ 0x3c8\n+\tstr.w\tr2, [r7, #560]\t@ 0x230\n \tadd.w\tr0, r6, #636\t@ 0x27c\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tmov\tr1, r5\n-\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tmov\tr1, sl\n+\tmul.w\tr3, r3, r3\n+\tstr.w\tr3, [r7, #968]\t@ 0x3c8\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr2, [sp, #16]\n-\tmov\tr2, sl\n+\tmov\tr2, r9\n \tstr\tr3, [sp, #12]\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tstr\tr3, [sp, #8]\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n \tstr\tr3, [sp, #0]\n-\tldr\tr3, [pc, #244]\t@ (5cb0 <__gridxc_cell_MOD_cellxc+0x56d4>)\n+\tldr.w\tr3, [pc, #1064]\t@ 4a08 <__gridxc_cell_MOD_cellxc+0x43f4>\n \tadd\tr3, pc\n \tstr\tr3, [sp, #20]\n \tmovs\tr3, #15\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbne.w\t61b4 <__gridxc_cell_MOD_cellxc+0x5bd8>\n-\tldr\tr3, [pc, #224]\t@ (5cb4 <__gridxc_cell_MOD_cellxc+0x56d8>)\n+\tbne.w\t4ba4 <__gridxc_cell_MOD_cellxc+0x4590>\n+\tldr.w\tr3, [pc, #1040]\t@ 4a0c <__gridxc_cell_MOD_cellxc+0x43f8>\n \tadd\tr3, pc\n \tldr.w\tr3, [r3, #144]\t@ 0x90\n \tcmp\tr3, #0\n-\tbne.w\t1416 <__gridxc_cell_MOD_cellxc+0xe3a>\n-\tadd.w\tr3, r7, #992\t@ 0x3e0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tb.w\t1a0c <__gridxc_cell_MOD_cellxc+0x1430>\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tcbz\tr3, 5c04 <__gridxc_cell_MOD_cellxc+0x5628>\n-\tldr\tr3, [pc, #196]\t@ (5cb8 <__gridxc_cell_MOD_cellxc+0x56dc>)\n+\tbne.w\t147a <__gridxc_cell_MOD_cellxc+0xe66>\n+\tb.w\t1aae <__gridxc_cell_MOD_cellxc+0x149a>\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tcbz\tr3, 4624 <__gridxc_cell_MOD_cellxc+0x4010>\n+\tldr\tr3, [pc, #1020]\t@ (4a10 <__gridxc_cell_MOD_cellxc+0x43fc>)\n \tmovs\tr1, #50\t@ 0x32\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr\tr0, [pc, #192]\t@ (5cbc <__gridxc_cell_MOD_cellxc+0x56e0>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr\tr0, [pc, #1016]\t@ (4a14 <__gridxc_cell_MOD_cellxc+0x4400>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n-\tcbz\tr3, 5c1c <__gridxc_cell_MOD_cellxc+0x5640>\n-\tldr\tr3, [pc, #172]\t@ (5cb8 <__gridxc_cell_MOD_cellxc+0x56dc>)\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tcbz\tr3, 463c <__gridxc_cell_MOD_cellxc+0x4028>\n+\tldr\tr3, [pc, #996]\t@ (4a10 <__gridxc_cell_MOD_cellxc+0x43fc>)\n \tmovs\tr1, #48\t@ 0x30\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tldr\tr0, [pc, #172]\t@ (5cc0 <__gridxc_cell_MOD_cellxc+0x56e4>)\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tldr\tr0, [pc, #996]\t@ (4a18 <__gridxc_cell_MOD_cellxc+0x4404>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #164]\t@ (5cc4 <__gridxc_cell_MOD_cellxc+0x56e8>)\n-\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tldr\tr3, [pc, #988]\t@ (4a1c <__gridxc_cell_MOD_cellxc+0x4408>)\n+\tldr.w\tr1, [r7, #744]\t@ 0x2e8\n \tadd\tr3, pc\n \tldr\tr2, [r3, #8]\n \tcmp\tr1, r2\n-\tbne.n\t5cd0 <__gridxc_cell_MOD_cellxc+0x56f4>\n+\tbne.n\t46a8 <__gridxc_cell_MOD_cellxc+0x4094>\n \tldr\tr2, [r3, #12]\n-\tldr.w\tr1, [r7, #656]\t@ 0x290\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n \tcmp\tr1, r2\n-\tbne.n\t5cd0 <__gridxc_cell_MOD_cellxc+0x56f4>\n+\tbne.n\t46a8 <__gridxc_cell_MOD_cellxc+0x4094>\n \tldr\tr3, [r3, #16]\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n \tcmp\tr2, r3\n-\tbne.n\t5cd0 <__gridxc_cell_MOD_cellxc+0x56f4>\n-\tldr.w\tr8, [pc, #136]\t@ 5cc8 <__gridxc_cell_MOD_cellxc+0x56ec>\n-\tldr\tr4, [pc, #136]\t@ (5ccc <__gridxc_cell_MOD_cellxc+0x56f0>)\n+\tbne.n\t46a8 <__gridxc_cell_MOD_cellxc+0x4094>\n+\tldr.w\tr8, [pc, #960]\t@ 4a20 <__gridxc_cell_MOD_cellxc+0x440c>\n+\tldr\tr4, [pc, #960]\t@ (4a24 <__gridxc_cell_MOD_cellxc+0x4410>)\n \tadd\tr8, pc\n \tldr\tr0, [r6, #0]\n \tadd.w\tr3, r8, #8\n \tldr\tr1, [r6, #4]\n \tldr\tr2, [r6, #8]\n \tstmia\tr3!, {r0, r1, r2}\n-\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n \tldr\tr3, [r3, r4]\n-\tstr\tr3, [r7, #48]\t@ 0x30\n+\tstr\tr3, [r7, #52]\t@ 0x34\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #1\n-\tble.n\t5c7a <__gridxc_cell_MOD_cellxc+0x569e>\n-\tvldr\td19, [r8, #24]\n-\tvldr\td18, [r8, #32]\n-\tvldr\td16, [pc, #28]\t@ 5c88 <__gridxc_cell_MOD_cellxc+0x56ac>\n-\tvdiv.f64\td17, d19, d18\n-\tvcmpe.f64\td17, d16\n+\tble.n\t469a <__gridxc_cell_MOD_cellxc+0x4086>\n+\tvldr\td6, [r8, #24]\n+\tvldr\td7, [r8, #32]\n+\tvldr\td5, [pc, #852]\t@ 49e0 <__gridxc_cell_MOD_cellxc+0x43cc>\n+\tvdiv.f64\td4, d6, d7\n+\tvcmpe.f64\td4, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t5cee <__gridxc_cell_MOD_cellxc+0x5712>\n-\tadd.w\tr3, r7, #2992\t@ 0xbb0\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tbgt.n\t46c6 <__gridxc_cell_MOD_cellxc+0x40b2>\n+\taddw\tr3, r7, #2968\t@ 0xb98\n+\tstr.w\tr3, [r7, #452]\t@ 0x1c4\n \tmov\tr2, r3\n-\tb.w\t1374 <__gridxc_cell_MOD_cellxc+0xd98>\n-\t.word\t0x9999999a\n-\t.word\t0x3fb99999\n-\t.word\t0x44610000\n-\t.word\t0x0000051c\n- R_ARM_REL32\t.data\n-\t.word\t0x0000036e\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000230\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000198\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000192\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000192\n- R_ARM_REL32\t.LC24\n-\t.word\t0x00000142\n- R_ARM_REL32\t.LC27\n-\t.word\t0x000000f2\n- R_ARM_REL32\t.LC28\n-\t.word\t0x000000dc\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000000ba\n- R_ARM_REL32\t.LC22\n-\t.word\t0x000000a6\n- R_ARM_REL32\t.LC23\n-\t.word\t0x0000009e\n- R_ARM_REL32\t.data\n-\t.word\t0x00000080\n- R_ARM_REL32\t.data\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n+\tb.w\t13d4 <__gridxc_cell_MOD_cellxc+0xdc0>\n \tmovs\tr3, #0\n-\tldr\tr0, [pc, #860]\t@ (6030 <__gridxc_cell_MOD_cellxc+0x5a54>)\n+\tldr\tr0, [pc, #892]\t@ (4a28 <__gridxc_cell_MOD_cellxc+0x4414>)\n \tstrd\tr3, r3, [sp, #20]\n \tmov\tr1, r6\n \tstrd\tr3, r3, [sp, #12]\n \tadd\tr0, pc\n \tstrd\tr3, r3, [sp, #4]\n \tstr\tr3, [sp, #0]\n \tldr\tr2, [r7, #84]\t@ 0x54\n \tbl\t0 <__gridxc_mesh3d_MOD_setmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_setmeshdistr\n-\tb.n\t5c3e <__gridxc_cell_MOD_cellxc+0x5662>\n-\tadd.w\tr3, r7, #2992\t@ 0xbb0\n+\tb.n\t465e <__gridxc_cell_MOD_cellxc+0x404a>\n+\taddw\tr3, r7, #2968\t@ 0xb98\n \tmov\tr0, r6\n \tmov\tr2, r3\n \tmov\tr1, r8\n \tmov\tfp, r3\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr.w\tr3, [r7, #452]\t@ 0x1c4\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldr\tr3, [pc, #816]\t@ (6034 <__gridxc_cell_MOD_cellxc+0x5a58>)\n-\tldr\tr4, [pc, #816]\t@ (6038 <__gridxc_cell_MOD_cellxc+0x5a5c>)\n-\tmovs\tr5, #0\n+\tldr\tr3, [pc, #848]\t@ (4a2c <__gridxc_cell_MOD_cellxc+0x4418>)\n+\tldr\tr4, [pc, #848]\t@ (4a30 <__gridxc_cell_MOD_cellxc+0x441c>)\n+\tmovs\tr6, #0\n \tadd\tr3, pc\n-\tldr.w\tr1, [r7, #400]\t@ 0x190\n+\tldr.w\tr1, [r7, #392]\t@ 0x188\n \tadds\tr3, #4\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [pc, #808]\t@ (603c <__gridxc_cell_MOD_cellxc+0x5a60>)\n+\tldr\tr3, [pc, #840]\t@ (4a34 <__gridxc_cell_MOD_cellxc+0x4420>)\n \tadd\tr4, pc\n \tstr\tr1, [sp, #16]\n-\tadd.w\tr9, r7, #3008\t@ 0xbc0\n-\tstr\tr5, [sp, #40]\t@ 0x28\n-\taddw\tr6, r7, #3004\t@ 0xbbc\n-\tstrd\tr5, r5, [sp, #28]\n-\taddw\tr2, r7, #2996\t@ 0xbb4\n-\tstr\tr5, [sp, #24]\n+\taddw\tr9, r7, #2984\t@ 0xba8\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\taddw\tr5, r7, #2980\t@ 0xba4\n+\tstrd\tr6, r6, [sp, #28]\n+\taddw\tr2, r7, #2972\t@ 0xb9c\n+\tstr\tr6, [sp, #24]\n \tadd\tr3, pc\n \tstr.w\tr9, [sp, #4]\n-\taddw\tsl, r7, #3012\t@ 0xbc4\n+\taddw\tsl, r7, #2988\t@ 0xbac\n \tstr\tr3, [sp, #20]\n \tmov\tr1, fp\n-\tstr\tr6, [sp, #0]\n+\tstr\tr5, [sp, #0]\n \tmovs\tr3, #13\n \tstr.w\tsl, [sp, #8]\n \tadd.w\tr0, r4, #144\t@ 0x90\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\taddw\tr3, r7, #3000\t@ 0xbb8\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tadd.w\tr3, r7, #2976\t@ 0xba0\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr9, sl, [sp, #4]\n-\tldr\tr1, [pc, #736]\t@ (6040 <__gridxc_cell_MOD_cellxc+0x5a64>)\n-\tadd.w\tr0, r4, #504\t@ 0x1f8\n-\tstr\tr6, [sp, #0]\n+\tldr\tr1, [pc, #768]\t@ (4a38 <__gridxc_cell_MOD_cellxc+0x4424>)\n \tadd.w\tr9, r8, #40\t@ 0x28\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tadd.w\tr6, r8, #4\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tadd\tr1, pc\n-\tstr\tr5, [sp, #32]\n-\tstrd\tr5, r5, [sp, #20]\n-\tstr\tr5, [sp, #16]\n+\tstr\tr5, [sp, #0]\n+\tadd.w\tr0, r4, #504\t@ 0x1f8\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tr5, r8, #4\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd\tr1, pc\n+\tstr\tr6, [sp, #32]\n+\tstrd\tr6, r6, [sp, #20]\n+\tstr\tr6, [sp, #16]\n \tstr\tr1, [sp, #12]\n \tmovs\tr1, #15\n \tstr\tr1, [sp, #28]\n \tmov\tr1, fp\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tmov\tr1, r6\n \tmov\tr2, r8\n+\tmov\tr1, r5\n \tmov\tr0, r9\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tvldr\td17, [pc, #636]\t@ 6020 <__gridxc_cell_MOD_cellxc+0x5a44>\n-\tadd.w\tr3, r4, #164\t@ 0xa4\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tldrd\tr2, r0, [r7, #632]\t@ 0x278\n \tstr\tr0, [r2, #32]\n-\tmov\tr1, r6\n-\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n-\tmov\tr6, r2\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tmov.w\tr8, #8\n \tstr\tr0, [r2, #44]\t@ 0x2c\n-\tldr.w\tr0, [r7, #668]\t@ 0x29c\n-\tstr\tr0, [r2, #56]\t@ 0x38\n \tldr.w\tr0, [r7, #644]\t@ 0x284\n-\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n-\tvstr\td16, [r0]\n-\tldr.w\tr0, [r7, #640]\t@ 0x280\n-\tvst1.32\t{d17}, [r0]\n-\tldr.w\tr0, [r7, #552]\t@ 0x228\n-\tvstr\td16, [r0]\n-\tvld1.32\t{d16}, [r3]\n+\tstr\tr0, [r2, #56]\t@ 0x38\n+\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\tstr\tr6, [r1, #0]\n+\tmov\tr1, r5\n+\tldr.w\tr5, [r7, #792]\t@ 0x318\n+\tstrd\tr6, r6, [r0]\n \tldr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr3, [r5, #532]\t@ 0x214\n \tstr\tr0, [r2, #68]\t@ 0x44\n+\tmov\tr0, r2\n+\tldr.w\tr3, [r5, #532]\t@ 0x214\n \tstr\tr3, [r2, #36]\t@ 0x24\n-\tmvns\tr3, r3\n \tldr.w\tr2, [r5, #536]\t@ 0x218\n-\tldr.w\tr0, [r5, #544]\t@ 0x220\n-\tstr\tr2, [r6, #48]\t@ 0x30\n+\tmvns\tr3, r3\n+\tstr\tr2, [r0, #48]\t@ 0x30\n \tsubs\tr3, r3, r2\n-\tldr.w\tr2, [r4, #172]\t@ 0xac\n-\tsubs\tr3, r3, r0\n-\tstr\tr0, [r6, #60]\t@ 0x3c\n-\tmov\tr0, r6\n-\tstr\tr3, [r6, #4]\n-\trsb\tr2, r2, #1\n-\tldr.w\tr3, [r4, #176]\t@ 0xb0\n-\tadds\tr6, r2, r3\n+\tldr.w\tr2, [r5, #544]\t@ 0x220\n+\tstr\tr2, [r0, #60]\t@ 0x3c\n+\tsubs\tr3, r3, r2\n+\tstr\tr3, [r0, #4]\n \tldr.w\tr3, [r5, #528]\t@ 0x210\n+\tmov\tr2, r0\n \tstr\tr3, [r0, #0]\n+\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r4, #164]\t@ 0xa4\n+\tstr\tr3, [r0, #20]\n \tmovs\tr3, #1\n-\tstr\tr3, [r0, #28]\n-\tstr\tr3, [r0, #40]\t@ 0x28\n-\tstr\tr3, [r0, #52]\t@ 0x34\n-\tstr\tr3, [r0, #64]\t@ 0x40\n-\tldr.w\tr5, [r7, #720]\t@ 0x2d0\n+\tmov\tr0, r2\n+\tstr\tr3, [r2, #28]\n+\tstr\tr3, [r2, #24]\n+\tstr\tr3, [r2, #40]\t@ 0x28\n+\tstr\tr3, [r2, #52]\t@ 0x34\n+\tstr\tr3, [r2, #64]\t@ 0x40\n+\tstr.w\tr8, [r2, #20]\n+\tstr.w\tr8, [r2, #8]\n+\tldr.w\tr2, [r4, #172]\t@ 0xac\n+\tldr.w\tr5, [r4, #176]\t@ 0xb0\n+\tsubs\tr2, r3, r2\n+\tadd.w\tlr, r2, r5\n \tldr.w\tr2, [r4, #184]\t@ 0xb8\n-\tldr.w\tr0, [r4, #188]\t@ 0xbc\n+\tldr.w\tr5, [r4, #188]\t@ 0xbc\n \tsubs\tr2, r3, r2\n-\tstr\tr3, [r5, #28]\n-\tadd.w\tip, r2, r0\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n+\tadd.w\tip, r2, r5\n \tldr.w\tr2, [r4, #196]\t@ 0xc4\n-\tldr.w\tr0, [r4, #200]\t@ 0xc8\n+\tldr.w\tr5, [r4, #200]\t@ 0xc8\n \tsubs\tr2, r3, r2\n-\tadd\tr2, r0\n-\tmovs\tr0, #8\n-\tstr\tr0, [r5, #8]\n-\tldr.w\tr5, [r7, #720]\t@ 0x2d0\n-\tstr\tr0, [r5, #8]\n-\tmov.w\tr0, #772\t@ 0x304\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tstrh\tr0, [r5, #16]\n-\tldr.w\tr5, [r7, #720]\t@ 0x2d0\n-\tstr\tr3, [r5, #40]\t@ 0x28\n-\tstr\tr3, [r5, #52]\t@ 0x34\n-\tstr\tr3, [r5, #64]\t@ 0x40\n-\tldr.w\tr3, [r4, #208]\t@ 0xd0\n-\tstrh\tr0, [r5, #16]\n-\tstr\tr2, [r5, #56]\t@ 0x38\n-\trsb\tr2, r3, #1\n+\tadd\tr2, r5\n+\tmov.w\tr5, #772\t@ 0x304\n+\tstrh\tr5, [r0, #16]\n+\tldr.w\tr0, [r7, #648]\t@ 0x288\n+\tstr\tr6, [r0, #4]\n+\tldr.w\tr6, [r7, #760]\t@ 0x2f8\n \tldr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tvmov.32\tr3, d16[1]\n-\tstr\tr0, [r5, #68]\t@ 0x44\n-\tldr.w\tr0, [r7, #548]\t@ 0x224\n-\tstr\tr6, [r5, #32]\n-\tldr.w\tr6, [r4, #180]\t@ 0xb4\n-\tstr.w\tip, [r5, #44]\t@ 0x2c\n-\tnegs\tr3, r3\n-\tvst1.32\t{d16}, [r0]\n-\tsubs\tr3, r3, r6\n+\tstr\tr3, [r6, #28]\n+\tstr\tr3, [r6, #40]\t@ 0x28\n+\tstr\tr3, [r6, #52]\t@ 0x34\n+\tstr\tr3, [r6, #64]\t@ 0x40\n+\tldr.w\tr3, [r4, #208]\t@ 0xd0\n+\tstr\tr0, [r6, #68]\t@ 0x44\n \tldr.w\tr0, [r4, #204]\t@ 0xcc\n-\tstr\tr6, [r5, #36]\t@ 0x24\n-\tldr.w\tr6, [r4, #192]\t@ 0xc0\n-\tstr\tr0, [r5, #60]\t@ 0x3c\n-\tsubs\tr3, r3, r6\n-\tmul.w\tr2, r0, r2\n+\trsb\tr3, r3, #1\n+\tstr\tr2, [r6, #56]\t@ 0x38\n+\tstrh\tr5, [r6, #16]\n+\tldr.w\tr5, [r4, #180]\t@ 0xb4\n+\tmul.w\tr2, r0, r3\n+\tldr.w\tr3, [r4, #168]\t@ 0xa8\n+\tstr\tr3, [r6, #24]\n+\tnegs\tr3, r3\n+\tstr\tr5, [r6, #36]\t@ 0x24\n+\tsubs\tr3, r3, r5\n+\tldr.w\tr5, [r4, #192]\t@ 0xc0\n+\tstr.w\tlr, [r6, #32]\n+\tsubs\tr3, r3, r5\n+\tstr.w\tip, [r6, #44]\t@ 0x2c\n \tsubs\tr3, r3, r0\n-\tstr\tr6, [r5, #48]\t@ 0x30\n-\tstr\tr3, [r5, #4]\n-\tmov\tr0, r5\n+\tstr\tr0, [r6, #60]\t@ 0x3c\n+\tstr\tr5, [r6, #48]\t@ 0x30\n+\tmov\tr5, r6\n+\tstr.w\tr8, [r6, #8]\n+\tstr\tr3, [r6, #4]\n \tldr.w\tr3, [r4, #144]\t@ 0x90\n \tadd.w\tr3, r3, r2, lsl #3\n-\tstr\tr3, [r5, #0]\n-\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n+\tstr\tr3, [r6, #0]\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldr.w\tr6, [r3, #552]\t@ 0x228\n \tmov\tr3, fp\n-\tldr.w\tr6, [r5, #552]\t@ 0x228\n-\tstrd\tr0, r9, [sp]\n+\tstrd\tr5, r9, [sp]\n \tmov\tr0, r6\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tldrd\tr3, r0, [r5, #520]\t@ 0x208\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tcmp\tr3, r0\n-\tbgt.w\t619e <__gridxc_cell_MOD_cellxc+0x5bc2>\n-\tldrd\tlr, r1, [r5, #512]\t@ 0x200\n-\tldrd\tr8, r3, [r5, #504]\t@ 0x1f8\n-\tcmp\tlr, r1\n-\tldr.w\tr2, [r4, #504]\t@ 0x1f8\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldrd\tr2, r0, [r3, #520]\t@ 0x208\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tcmp\tr2, r0\n+\tbgt.w\t4b8e <__gridxc_cell_MOD_cellxc+0x457a>\n+\tldrd\tlr, r2, [r3, #512]\t@ 0x200\n+\tldr.w\tr5, [r4, #504]\t@ 0x1f8\n+\tstr.w\tr5, [r7, #776]\t@ 0x308\n+\tcmp\tlr, r2\n \tldr.w\tr5, [r4, #508]\t@ 0x1fc\n+\tldrd\tr8, r3, [r3, #504]\t@ 0x1f8\n+\tstr.w\tr5, [r7, #768]\t@ 0x300\n \tldr.w\tip, [r4, #528]\t@ 0x210\n-\tstr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tstr.w\tr5, [r7, #736]\t@ 0x2e0\n-\tbgt.w\t6088 <__gridxc_cell_MOD_cellxc+0x5aac>\n+\tbgt.w\t4a78 <__gridxc_cell_MOD_cellxc+0x4464>\n \tcmp\tr8, r3\n-\tbgt.w\t6088 <__gridxc_cell_MOD_cellxc+0x5aac>\n-\tldr.w\tr9, [r4, #552]\t@ 0x228\n-\tadds\tr0, #1\n-\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n-\tadds\tr3, #1\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tadds\tr1, #1\n-\tstr.w\tr3, [r7, #636]\t@ 0x27c\n-\tvmov.i64\td18, #0x0000000000000000\n-\tldr.w\tr3, [r4, #192]\t@ 0xc0\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tstr.w\tr1, [r7, #640]\t@ 0x280\n-\tmul.w\tr1, r8, ip\n-\tmla\tr1, r9, r0, r1\n-\tvldr\td19, [pc, #252]\t@ 6028 <__gridxc_cell_MOD_cellxc+0x5a4c>\n-\tmul.w\tr0, r3, r0\n-\tldr.w\tr3, [r4, #204]\t@ 0xcc\n-\tadd\tr1, r5\n-\tldr.w\tr5, [r4, #540]\t@ 0x21c\n-\tadd.w\tr0, r0, r3, lsl #1\n+\tbgt.w\t4a78 <__gridxc_cell_MOD_cellxc+0x4464>\n+\tadds\tr2, #1\n+\tstr.w\tr2, [r7, #644]\t@ 0x284\n+\tadds\tr2, r3, #1\n+\tstr.w\tr2, [r7, #636]\t@ 0x27c\n+\tldr.w\tr2, [r4, #540]\t@ 0x21c\n+\tadds\tr1, r0, #1\n+\tldr.w\tr5, [r4, #192]\t@ 0xc0\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tmov\tfp, r2\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr0, [r4, #164]\t@ 0xa4\n+\tstr.w\tr1, [r7, #656]\t@ 0x290\n+\tldr.w\tr1, [r4, #204]\t@ 0xcc\n+\tmul.w\tr2, r5, r2\n \tldr.w\tr3, [r4, #148]\t@ 0x94\n-\tmla\tr1, r5, lr, r1\n-\tadd\tr3, r0\n-\tldr.w\tr0, [r4, #180]\t@ 0xb4\n-\tstr.w\tr1, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr9, [r4, #552]\t@ 0x228\n+\tvldr\td3, [pc, #236]\t@ 49e8 <__gridxc_cell_MOD_cellxc+0x43d4>\n+\tadd.w\tr2, r2, r1, lsl #1\n+\tmul.w\tr1, r0, r5\n+\tstr.w\tr1, [r7, #692]\t@ 0x2b4\n+\tadd\tr3, r2\n+\tldr.w\tr1, [r4, #204]\t@ 0xcc\n+\tmul.w\tr2, fp, lr\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n+\tvldr\td4, [pc, #212]\t@ 49f0 <__gridxc_cell_MOD_cellxc+0x43dc>\n+\tmul.w\tr1, r0, r1\n+\tstr.w\tr1, [r7, #664]\t@ 0x298\n \tldr.w\tr1, [r4, #168]\t@ 0xa8\n-\tmla\tr3, lr, r0, r3\n-\tmla\tsl, r1, r8, r3\n-\tldr.w\tr1, [r4, #164]\t@ 0xa4\n-\tldr.w\tr3, [r4, #192]\t@ 0xc0\n-\tmul.w\tr3, r3, r1\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n-\tmul.w\tr3, r1, r0\n-\tstr.w\tr3, [r7, #652]\t@ 0x28c\n-\tldr.w\tr3, [r4, #168]\t@ 0xa8\n-\tldr.w\tr0, [r4, #524]\t@ 0x20c\n-\tmul.w\tr3, r1, r3\n-\tstr.w\tr3, [r7, #668]\t@ 0x29c\n-\tldr.w\tr3, [r4, #204]\t@ 0xcc\n+\tmla\tr3, r8, r1, r3\n+\tmul.w\tr1, r0, r1\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r4, #180]\t@ 0xb4\n+\tmla\tr3, lr, r1, r3\n+\tmul.w\tr1, r0, r1\n+\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tmla\tr2, r9, r1, r2\n+\tadd\tr2, r5\n+\tldr.w\tr5, [r4, #524]\t@ 0x20c\n \tldr.w\tr4, [r4, #144]\t@ 0x90\n-\tmul.w\tr3, r1, r3\n-\tmla\tr4, r1, sl, r4\n-\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r7, #656]\t@ 0x290\n-\tmul.w\tr3, r9, r0\n-\tstr.w\tr3, [r7, #664]\t@ 0x298\n-\tmul.w\tr9, ip, r0\n-\tmla\tr3, r0, r1, r2\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tmul.w\tr3, r5, r0\n-\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tfp, [r7, #752]\t@ 0x2f0\n-\tmov\tr5, r4\n-\tstr.w\tlr, [r7, #724]\t@ 0x2d4\n-\tmov\tr1, r5\n+\tmla\tr2, r8, ip, r2\n+\tmul.w\tr1, r5, r9\n+\tmla\tr0, r0, r3, r4\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tstr.w\tr1, [r7, #736]\t@ 0x2e0\n+\tmla\tsl, r5, r2, r3\n+\tmul.w\tr3, fp, r5\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tmul.w\tr3, r5, ip\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tmov\tr5, r0\n+\tmov\tfp, sl\n+\tstr.w\tlr, [r7, #744]\t@ 0x2e8\n+\tmov\tr2, r5\n \tmov\tr3, fp\n-\tstr.w\tr8, [r7, #732]\t@ 0x2dc\n-\tb.n\t600c <__gridxc_cell_MOD_cellxc+0x5a30>\n-\tldr.w\tr0, [r7, #656]\t@ 0x290\n-\tcmp\tr2, #1\n-\tsub.w\tsl, r1, r0\n-\tvldr\td16, [sl]\n-\tble.n\t5fe4 <__gridxc_cell_MOD_cellxc+0x5a08>\n-\tvldr\td20, [r1]\n-\tvadd.f64\td16, d16, d20\n-\tvcmpe.f64\td16, d19\n+\tmov\tr4, r8\n+\tb.n\t49ce <__gridxc_cell_MOD_cellxc+0x43ba>\n+\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tsub.w\tr9, r2, r1\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tcmp\tr1, #1\n+\tvldr\td7, [r9]\n+\tble.n\t49aa <__gridxc_cell_MOD_cellxc+0x4396>\n+\tvldr\td6, [r2]\n+\tvadd.f64\td7, d7, d6\n+\tvcmpe.f64\td7, d3\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t6014 <__gridxc_cell_MOD_cellxc+0x5a38>\n-\tvstr\td17, [r3]\n-\tldr.w\tr0, [r7, #668]\t@ 0x29c\n-\tadd\tr3, r9\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tadd\tr1, r0\n-\tldr.w\tr0, [r7, #636]\t@ 0x27c\n-\tadds\tr2, #1\n-\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n-\tcmp\tr2, r0\n-\tbeq.n\t6044 <__gridxc_cell_MOD_cellxc+0x5a68>\n-\tldr.w\tr2, [r7, #764]\t@ 0x2fc\n-\tcmp\tr2, #0\n-\tbgt.n\t5fcc <__gridxc_cell_MOD_cellxc+0x59f0>\n-\tvstr\td18, [r3]\n-\tb.n\t5ff2 <__gridxc_cell_MOD_cellxc+0x5a16>\n-\tnop\n+\tble.n\t49d6 <__gridxc_cell_MOD_cellxc+0x43c2>\n+\tvstr\td5, [r3]\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tadds\tr4, #1\n+\tadd\tr3, r1\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r7, #636]\t@ 0x27c\n+\tcmp\tr4, r1\n+\tbeq.n\t4a3c <__gridxc_cell_MOD_cellxc+0x4428>\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tcmp\tr1, #0\n+\tbgt.n\t498e <__gridxc_cell_MOD_cellxc+0x437a>\n+\tvstr\td4, [r3]\n+\tb.n\t49b8 <__gridxc_cell_MOD_cellxc+0x43a4>\n \tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n+\t.word\t0x9999999a\n+\t.word\t0x3fb99999\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x0000034e\n+\t...\n+\t.word\t0x000004d2\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000004ca\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004ca\n+ R_ARM_REL32\t.LC24\n+\t.word\t0x0000047c\n+ R_ARM_REL32\t.LC27\n+\t.word\t0x00000424\n+ R_ARM_REL32\t.LC28\n+\t.word\t0x0000040c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x000003f2\n+ R_ARM_REL32\t.LC22\n+\t.word\t0x000003de\n+ R_ARM_REL32\t.LC23\n+\t.word\t0x000003d6\n R_ARM_REL32\t.data\n-\t.word\t0x00000328\n+\t.word\t0x000003b8\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n+\t.word\t0x0000036e\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000348\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000320\n+\t.word\t0x00000340\n R_ARM_REL32\t.bss\n-\t.word\t0x0000030c\n+\t.word\t0x0000032c\n R_ARM_REL32\t.LC24\n-\t.word\t0x000002c8\n+\t.word\t0x000002e8\n R_ARM_REL32\t.LC26\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tadd\tfp, r3\n-\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tadd\tfp, r2\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tadd\tr5, r2\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tcmp\tr2, r3\n+\tbne.n\t4986 <__gridxc_cell_MOD_cellxc+0x4372>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd\tsl, r3\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n \tadds\tr2, #1\n-\tstr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tadd\tr5, r3\n-\tldr.w\tr3, [r7, #640]\t@ 0x280\n-\tcmp\tr3, r2\n-\tbne.n\t5fc2 <__gridxc_cell_MOD_cellxc+0x59e6>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr3, [r7, #644]\t@ 0x284\n-\tadds\tr1, #1\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tcmp\tr3, r1\n-\tbne.n\t5fb8 <__gridxc_cell_MOD_cellxc+0x59dc>\n-\tldr.w\tr3, [pc, #2700]\t@ 6b18 <__gridxc_cell_MOD_cellxc+0x653c>\n-\tldr.w\tr0, [pc, #2700]\t@ 6b1c <__gridxc_cell_MOD_cellxc+0x6540>\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd\tr0, r3\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tcmp\tr2, r3\n+\tbne.n\t497e <__gridxc_cell_MOD_cellxc+0x436a>\n+\tldr.w\tr3, [pc, #2588]\t@ 5498 <__gridxc_cell_MOD_cellxc+0x4e84>\n+\tldr.w\tr0, [pc, #2588]\t@ 549c <__gridxc_cell_MOD_cellxc+0x4e88>\n \tadd\tr3, pc\n \tadd\tr0, pc\n \tldrd\tr5, r4, [r3, #556]\t@ 0x22c\n \tldrd\tlr, r8, [r3, #544]\t@ 0x220\n \tcmp\tr5, r4\n-\tvldr\td17, [r0, #32]\n-\tbgt.n\t613e <__gridxc_cell_MOD_cellxc+0x5b62>\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [r0, #32]\n+\tbgt.n\t4b2e <__gridxc_cell_MOD_cellxc+0x451a>\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n \tcmp\tlr, r8\n-\tvdiv.f64\td16, d18, d17\n-\tbgt.n\t613e <__gridxc_cell_MOD_cellxc+0x5b62>\n+\tvdiv.f64\td7, d5, d6\n+\tbgt.n\t4b2e <__gridxc_cell_MOD_cellxc+0x451a>\n \tldrd\tr1, r2, [r3, #532]\t@ 0x214\n \tcmp\tr1, r2\n-\tbgt.n\t613e <__gridxc_cell_MOD_cellxc+0x5b62>\n+\tbgt.n\t4b2e <__gridxc_cell_MOD_cellxc+0x451a>\n \tadds\tr2, #1\n-\tvldr\td17, [r0, #48]\t@ 0x30\n+\tvldr\td6, [r0, #48]\t@ 0x30\n \tsubs\tr2, r2, r1\n \tadd.w\tr0, r8, #1\n \tadds\tr4, #1\n \tsub.w\tr9, r0, lr\n \tmov\tfp, r2\n-\tldr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n \tldr.w\tr2, [r3, #552]\t@ 0x228\n \tsub.w\tr8, r4, r5\n \tldr.w\tr4, [r3, #540]\t@ 0x21c\n-\tvmul.f64\td16, d16, d17\n+\tvmul.f64\td7, d7, d6\n \tldr.w\tr3, [r3, #524]\t@ 0x20c\n \tmov.w\tsl, #0\n \tmla\tr0, r5, r2, r0\n \tmla\tr0, lr, r4, r0\n \tmla\tr0, ip, r1, r0\n-\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tmul.w\tip, ip, r3\n \tmul.w\tlr, r3, r2\n \tmul.w\tr2, r3, r4\n \tmla\tr0, r3, r0, r1\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n \tmov\tr4, r0\n \tmovs\tr1, #0\n \tmov\tr3, r4\n \tmovs\tr5, #0\n-\tvldr\td17, [r3]\n+\tvldr\td6, [r3]\n \tadds\tr5, #1\n-\tcmp\tr5, fp\n-\tvmul.f64\td17, d17, d16\n-\tvstr\td17, [r3]\n+\tcmp\tfp, r5\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td6, [r3]\n \tadd\tr3, ip\n-\tbne.n\t6114 <__gridxc_cell_MOD_cellxc+0x5b38>\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tbne.n\t4b04 <__gridxc_cell_MOD_cellxc+0x44f0>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tadds\tr1, #1\n-\tcmp\tr9, r1\n+\tcmp\tr1, r9\n \tadd\tr4, r3\n-\tbne.n\t6110 <__gridxc_cell_MOD_cellxc+0x5b34>\n+\tbne.n\t4b00 <__gridxc_cell_MOD_cellxc+0x44ec>\n \tadd.w\tsl, sl, #1\n \tadd\tr0, lr\n \tcmp\tr8, sl\n-\tbne.n\t610c <__gridxc_cell_MOD_cellxc+0x5b30>\n-\tldr.w\tr4, [pc, #2528]\t@ 6b20 <__gridxc_cell_MOD_cellxc+0x6544>\n+\tbne.n\t4afc <__gridxc_cell_MOD_cellxc+0x44e8>\n+\tldr.w\tr4, [pc, #2416]\t@ 54a0 <__gridxc_cell_MOD_cellxc+0x4e8c>\n \tmov.w\tr8, #0\n-\tldr.w\tr0, [pc, #2524]\t@ 6b24 <__gridxc_cell_MOD_cellxc+0x6548>\n+\tldr.w\tr0, [pc, #2412]\t@ 54a4 <__gridxc_cell_MOD_cellxc+0x4e90>\n \tmov\tr3, r8\n \tadd\tr4, pc\n \tmov\tr2, r8\n \tadd\tr0, pc\n \tadd.w\tr5, r4, #504\t@ 0x1f8\n \tmov\tr1, r6\n \tstr\tr0, [sp, #20]\n \tstrd\tr8, r8, [sp, #12]\n \tstrd\tr8, r8, [sp, #4]\n \tstr.w\tr8, [sp]\n \tstr\tr5, [sp, #24]\n \tbl\t0 <__gridxc_mesh3d_MOD_setmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_setmeshdistr\n-\tldr.w\tr1, [pc, #2488]\t@ 6b28 <__gridxc_cell_MOD_cellxc+0x654c>\n+\tldr.w\tr1, [pc, #2376]\t@ 54a8 <__gridxc_cell_MOD_cellxc+0x4e94>\n \tmov\tr0, r5\n \tmovs\tr3, #15\n \tadd\tr1, pc\n \tmov\tr2, r8\n \tstr.w\tr8, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d3\n-\tldr.w\tr1, [pc, #2472]\t@ 6b2c <__gridxc_cell_MOD_cellxc+0x6550>\n+\tldr.w\tr1, [pc, #2360]\t@ 54ac <__gridxc_cell_MOD_cellxc+0x4e98>\n \tmov\tr2, r8\n \tadd.w\tr0, r4, #144\t@ 0x90\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr.w\tr8, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr.w\tr2, [r7, #460]\t@ 0x1cc\n-\tb.w\t1374 <__gridxc_cell_MOD_cellxc+0xd98>\n+\tldr.w\tr2, [r7, #452]\t@ 0x1c4\n+\tb.w\t13d4 <__gridxc_cell_MOD_cellxc+0xdc0>\n \tldr.w\tr3, [r4, #504]\t@ 0x1f8\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr3, [r4, #508]\t@ 0x1fc\n \tldr.w\tip, [r4, #528]\t@ 0x210\n-\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tb.n\t6088 <__gridxc_cell_MOD_cellxc+0x5aac>\n-\tadd.w\tr3, r7, #836\t@ 0x344\n-\tadd.w\tr2, r7, #848\t@ 0x350\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tb.n\t4a78 <__gridxc_cell_MOD_cellxc+0x4464>\n+\tadd.w\tr3, r7, #820\t@ 0x334\n+\tadd.w\tr2, r7, #832\t@ 0x340\n \tmov\tr5, r3\n-\tstr.w\tr2, [r7, #640]\t@ 0x280\n-\tadd.w\tr2, r7, #856\t@ 0x358\n-\tstr.w\tr2, [r7, #628]\t@ 0x274\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tadd.w\tr1, r7, #840\t@ 0x348\n-\tstr.w\tr5, [r7, #600]\t@ 0x258\n-\tadd.w\tr3, r7, #852\t@ 0x354\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n+\tadd.w\tr2, r7, #840\t@ 0x348\n+\tstr.w\tr2, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tadd.w\tr1, r7, #824\t@ 0x338\n+\tstr.w\tr5, [r7, #528]\t@ 0x210\n+\tadd.w\tr3, r7, #836\t@ 0x344\n \tsubs\tr2, #3\n \tstr\tr2, [r5, #0]\n \tldr.w\tr5, [r7, #688]\t@ 0x2b0\n-\tadd.w\tr6, r7, #844\t@ 0x34c\n-\tstr.w\tr1, [r7, #644]\t@ 0x284\n-\tadd.w\tip, r7, #904\t@ 0x388\n+\tadd.w\tr6, r7, #828\t@ 0x33c\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tadd.w\tip, r7, #888\t@ 0x378\n \tsubs\tr2, r5, #3\n-\tldr.w\tr5, [r7, #644]\t@ 0x284\n-\tstr.w\tr3, [r7, #636]\t@ 0x27c\n-\tadd.w\tr1, r7, #912\t@ 0x390\n-\tstr.w\tr6, [r7, #584]\t@ 0x248\n-\tadd.w\tr0, r7, #916\t@ 0x394\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tadd.w\tr1, r7, #896\t@ 0x380\n+\tstr.w\tr6, [r7, #524]\t@ 0x20c\n+\tadd.w\tr0, r7, #900\t@ 0x384\n \tstr\tr2, [r5, #0]\n-\tadd.w\tr4, r7, #924\t@ 0x39c\n-\tldr.w\tr5, [r7, #724]\t@ 0x2d4\n-\tmov\tr9, fp\n-\tldr.w\tr6, [r7, #636]\t@ 0x27c\n+\tadd.w\tr4, r7, #908\t@ 0x38c\n+\tldr.w\tr5, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr6, [r7, #608]\t@ 0x260\n \tsubs\tr2, r5, #3\n-\tldr.w\tr5, [r7, #640]\t@ 0x280\n-\tstr.w\tr2, [r7, #844]\t@ 0x34c\n-\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n-\tstr.w\tip, [r7, #564]\t@ 0x234\n+\tldr.w\tr5, [r7, #656]\t@ 0x290\n+\tstr.w\tr2, [r7, #828]\t@ 0x33c\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tstr.w\tip, [r7, #504]\t@ 0x1f8\n \tsubs\tr2, #1\n \tstr\tr2, [r5, #0]\n \tldr.w\tr2, [r7, #688]\t@ 0x2b0\n-\tstr.w\tr1, [r7, #624]\t@ 0x270\n+\tstr.w\tr1, [r7, #592]\t@ 0x250\n \tsubs\tr2, #1\n \tstr\tr2, [r6, #0]\n-\tldr.w\tr6, [r7, #628]\t@ 0x274\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tstr.w\tr0, [r7, #616]\t@ 0x268\n-\tadd.w\tr0, r7, #920\t@ 0x398\n+\tldr.w\tr6, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr0, [r7, #584]\t@ 0x248\n+\tadd.w\tr0, r7, #904\t@ 0x388\n \tsubs\tr2, #1\n \tstr\tr2, [r6, #0]\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n-\tstr.w\tr0, [r7, #612]\t@ 0x264\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tstr.w\tr0, [r7, #552]\t@ 0x228\n \tadds\tr2, #1\n \tstr.w\tr2, [ip]\n-\tadd.w\tip, r7, #908\t@ 0x38c\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n-\tstr.w\tr4, [r7, #608]\t@ 0x260\n+\tadd.w\tip, r7, #892\t@ 0x37c\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tstr.w\tr4, [r7, #536]\t@ 0x218\n \tmovs\tr4, #0\n \tadds\tr6, r2, #1\n-\tstr.w\tip, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [pc, #2136]\t@ 54b0 <__gridxc_cell_MOD_cellxc+0x4e9c>\n \tstr.w\tr6, [ip]\n-\tmov.w\tip, #13\n-\tldr.w\tr6, [r7, #652]\t@ 0x28c\n-\tldr.w\tr3, [pc, #2228]\t@ 6b30 <__gridxc_cell_MOD_cellxc+0x6554>\n-\tadds\tr2, r6, #1\n-\tldr.w\tr6, [r7, #624]\t@ 0x270\n+\tmov\tfp, ip\n+\tldr.w\tr6, [r7, #636]\t@ 0x27c\n \tadd\tr3, pc\n-\tldr.w\tr0, [pc, #2220]\t@ 6b34 <__gridxc_cell_MOD_cellxc+0x6558>\n \tadds\tr1, r3, #4\n-\tldr.w\tr3, [pc, #2220]\t@ 6b38 <__gridxc_cell_MOD_cellxc+0x655c>\n+\tldr.w\tr3, [pc, #2120]\t@ 54b4 <__gridxc_cell_MOD_cellxc+0x4ea0>\n+\tadds\tr2, r6, #1\n+\tldr.w\tr6, [r7, #592]\t@ 0x250\n+\tadd\tr3, pc\n+\tldr.w\tr0, [pc, #2112]\t@ 54b8 <__gridxc_cell_MOD_cellxc+0x4ea4>\n+\tmov.w\tip, #13\n \tstr\tr2, [r6, #0]\n \tadd\tr0, pc\n-\tldr.w\tr6, [r7, #616]\t@ 0x268\n-\tadd\tr3, pc\n-\tldr.w\tr2, [r7, #668]\t@ 0x29c\n+\tldr.w\tr6, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n \tadds\tr2, #3\n \tstr\tr2, [r6, #0]\n-\tldr.w\tr6, [r7, #612]\t@ 0x264\n-\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr.w\tr6, [r7, #552]\t@ 0x228\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n \tadds\tr2, #3\n \tstr\tr2, [r6, #0]\n-\tldr.w\tr6, [r7, #608]\t@ 0x260\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n+\tldr.w\tr6, [r7, #536]\t@ 0x218\n+\tldr.w\tr2, [r7, #636]\t@ 0x27c\n \tadds\tr2, #3\n \tstr\tr2, [r6, #0]\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr3, [sp, #20]\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n \tmov\tr3, r8\n-\tstr.w\tr1, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr1, [r7, #776]\t@ 0x308\n \tstr\tr1, [sp, #12]\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tstr\tr2, [sp, #8]\n \tldr.w\tr6, [r7, #736]\t@ 0x2e0\n \tstr\tr6, [sp, #4]\n \tmov\tr6, r0\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadds\tr0, #216\t@ 0xd8\n \tstr\tr2, [sp, #0]\n \tmov\tr2, r5\n \tstr.w\tip, [sp, #36]\t@ 0x24\n-\tldr.w\tr1, [r7, #600]\t@ 0x258\n-\tstr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [r7, #528]\t@ 0x210\n+\tstr.w\tr5, [r7, #656]\t@ 0x290\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tmov.w\tip, #13\n \tstrd\tr4, r4, [sp, #24]\n \tmov\tr5, ip\n \tstrd\tr4, ip, [sp, #32]\n \tstr\tr4, [sp, #40]\t@ 0x28\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tstr\tr0, [sp, #8]\n \tadd.w\tr0, r6, #288\t@ 0x120\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [pc, #2068]\t@ 6b3c <__gridxc_cell_MOD_cellxc+0x6560>\n-\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [pc, #1960]\t@ 54bc <__gridxc_cell_MOD_cellxc+0x4ea8>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tstr\tr2, [sp, #0]\n \tadd\tr3, pc\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r8\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tr1, [r7, #564]\t@ 0x234\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n-\tmov\tr2, sl\n+\tmov\tr2, r9\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tstr\tr0, [sp, #8]\n \tadd.w\tr0, r6, #360\t@ 0x168\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [pc, #2004]\t@ 6b40 <__gridxc_cell_MOD_cellxc+0x6564>\n-\tldr.w\tr1, [r7, #636]\t@ 0x27c\n+\tldr.w\tr3, [pc, #1896]\t@ 54c0 <__gridxc_cell_MOD_cellxc+0x4eac>\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n \tstr\tr1, [sp, #0]\n \tadd\tr3, pc\n \tstr\tr3, [sp, #20]\n-\tmov\tr1, fp\n-\tldr.w\tr3, [r7, #644]\t@ 0x284\n+\tmov\tr1, sl\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n-\tmov\tr2, sl\n+\tmov\tr2, r9\n \tstr\tr4, [sp, #24]\n-\tmov\tr1, r9\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmov\tr1, sl\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tstr\tr0, [sp, #8]\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [pc, #1948]\t@ 6b44 <__gridxc_cell_MOD_cellxc+0x6568>\n-\tldr.w\tr0, [r7, #612]\t@ 0x264\n-\tstr\tr0, [sp, #0]\n+\tldr.w\tr3, [pc, #1840]\t@ 54c4 <__gridxc_cell_MOD_cellxc+0x4eb0>\n+\tldr.w\tr0, [r7, #552]\t@ 0x228\n \tadd\tr3, pc\n+\tstr\tr0, [sp, #0]\n \tstr\tr3, [sp, #20]\n \tadd.w\tr0, r6, #432\t@ 0x1b0\n-\tldr.w\tfp, [r7, #560]\t@ 0x230\n \tmov\tr3, fp\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n-\tmov\tr2, sl\n+\tmov\tr1, sl\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n-\tldr.w\tr1, [r7, #628]\t@ 0x274\n-\tstr\tr1, [sp, #8]\n-\tldr.w\tr1, [r7, #584]\t@ 0x248\n-\tstr\tr1, [sp, #4]\n-\tmov\tr1, r9\n-\tldr.w\tr3, [pc, #1884]\t@ 6b48 <__gridxc_cell_MOD_cellxc+0x656c>\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr0, [r7, #600]\t@ 0x258\n+\tstr\tr0, [sp, #8]\n+\tldr.w\tr0, [r7, #524]\t@ 0x20c\n+\tstr\tr0, [sp, #4]\n+\tmov\tr0, r6\n+\tldr.w\tr3, [pc, #1780]\t@ 54c8 <__gridxc_cell_MOD_cellxc+0x4eb4>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadd\tr3, pc\n-\tstr\tr0, [sp, #0]\n+\tstr\tr2, [sp, #0]\n \tstr\tr3, [sp, #20]\n-\tmov\tr0, r6\n+\tmov\tr2, r9\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n-\tmov\tr2, sl\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n-\tldr.w\tr1, [r7, #608]\t@ 0x260\n-\tstr\tr1, [sp, #8]\n-\tldr.w\tr1, [r7, #624]\t@ 0x270\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tstr\tr0, [sp, #8]\n+\tadd.w\tr0, r6, #72\t@ 0x48\n+\tldr.w\tr1, [r7, #592]\t@ 0x250\n \tstr\tr1, [sp, #4]\n-\tmov\tr1, r9\n-\tldr.w\tr3, [pc, #1828]\t@ 6b4c <__gridxc_cell_MOD_cellxc+0x6570>\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tmov\tr1, sl\n+\tldr.w\tr3, [pc, #1724]\t@ 54cc <__gridxc_cell_MOD_cellxc+0x4eb8>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadd\tr3, pc\n-\tstr\tr0, [sp, #0]\n+\tstr\tr2, [sp, #0]\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr0, r6, #72\t@ 0x48\n+\tmov\tr2, r9\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr2, [r7, #640]\t@ 0x280\n-\tldr.w\tr1, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tldr.w\tr1, [r7, #528]\t@ 0x210\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tstr\tr0, [sp, #8]\n+\tadd.w\tr0, r6, #708\t@ 0x2c4\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [pc, #1768]\t@ 6b50 <__gridxc_cell_MOD_cellxc+0x6574>\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr3, [pc, #1652]\t@ 54d0 <__gridxc_cell_MOD_cellxc+0x4ebc>\n \tadd\tr3, pc\n-\tstr\tr0, [sp, #0]\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr0, r6, #708\t@ 0x2c4\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tr1, [r7, #564]\t@ 0x234\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n-\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n \tstr\tr0, [sp, #8]\n+\tadd.w\tr0, r6, #780\t@ 0x30c\n \tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tstr\tr3, [sp, #4]\n-\tldr.w\tr3, [pc, #1704]\t@ 6b54 <__gridxc_cell_MOD_cellxc+0x6578>\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr3, [pc, #1592]\t@ 54d4 <__gridxc_cell_MOD_cellxc+0x4ec0>\n \tadd\tr3, pc\n-\tstr\tr0, [sp, #0]\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr0, r6, #780\t@ 0x30c\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr1, [r7, #636]\t@ 0x27c\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n \tstr\tr1, [sp, #0]\n-\tmov\tr1, r9\n-\tldr.w\tr3, [r7, #644]\t@ 0x284\n+\tmov\tr1, sl\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tstrd\tr5, r4, [sp, #36]\t@ 0x24\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #24]\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n \tadd.w\tr0, r6, #852\t@ 0x354\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tstr\tr2, [sp, #8]\n-\tldr.w\tr2, [pc, #1640]\t@ 6b58 <__gridxc_cell_MOD_cellxc+0x657c>\n+\tldr.w\tr2, [pc, #1536]\t@ 54d8 <__gridxc_cell_MOD_cellxc+0x4ec4>\n \tldr.w\tr5, [r7, #736]\t@ 0x2e0\n \tadd\tr2, pc\n \tstr\tr5, [sp, #4]\n \tstr\tr2, [sp, #20]\n-\tmov\tr2, sl\n+\tmov\tr2, r9\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tstr\tr2, [sp, #8]\n-\tadd.w\tr0, r6, #924\t@ 0x39c\n+\tmov\tr3, fp\n \tstr\tr5, [sp, #4]\n \tmovs\tr5, #13\n-\tldr.w\tr3, [r7, #612]\t@ 0x264\n-\tmov\tr1, r9\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n \tstrd\tr4, r5, [sp, #32]\n \tstrd\tr4, r4, [sp, #24]\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, fp\n+\tstr\tr1, [sp, #0]\n+\tmov\tr1, sl\n \tstr\tr4, [sp, #40]\t@ 0x28\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [pc, #1584]\t@ 6b5c <__gridxc_cell_MOD_cellxc+0x6580>\n-\tldr.w\tr5, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr2, [pc, #1484]\t@ 54dc <__gridxc_cell_MOD_cellxc+0x4ec8>\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tadd\tr2, pc\n-\tstr\tr5, [sp, #12]\n+\tstr\tr0, [sp, #12]\n \tstr\tr2, [sp, #20]\n-\tmov\tr2, sl\n+\tadd.w\tr0, r6, #924\t@ 0x39c\n+\tmov\tr2, r9\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr3, [r7, #628]\t@ 0x274\n-\tstr\tr3, [sp, #8]\n-\tadd.w\tr0, r6, #996\t@ 0x3e4\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n-\tmov\tr2, sl\n-\tstr\tr3, [sp, #4]\n-\tmovs\tr3, #13\n-\tstrd\tr4, r4, [sp, #24]\n-\tmov\tr1, r9\n-\tstrd\tr4, r3, [sp, #32]\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #600]\t@ 0x258\n+\tstr\tr1, [sp, #8]\n+\tmov\tr2, r9\n+\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\tstrd\tr5, r4, [sp, #36]\t@ 0x24\n+\tstrd\tr4, r4, [sp, #28]\n+\tstr\tr1, [sp, #4]\n+\tmov\tr1, sl\n+\tstr\tr4, [sp, #24]\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tstr\tr3, [sp, #16]\n-\tstr.w\tr5, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr3, [pc, #1528]\t@ 6b60 <__gridxc_cell_MOD_cellxc+0x6584>\n-\tstr\tr5, [sp, #12]\n-\tldr.w\tr5, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n+\tstr\tr0, [sp, #12]\n+\tadd.w\tr0, r6, #996\t@ 0x3e4\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr3, [pc, #1416]\t@ 54e0 <__gridxc_cell_MOD_cellxc+0x4ecc>\n \tadd\tr3, pc\n-\tstr\tr5, [sp, #0]\n \tstr\tr3, [sp, #20]\n \tmov\tr3, r8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tmovs\tr3, #13\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tmov\tr2, sl\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmov\tr1, r9\n+\tstr\tr5, [sp, #36]\t@ 0x24\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov\tr2, r9\n \tstr\tr3, [sp, #16]\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tstr\tr0, [sp, #12]\n-\tldr.w\tr3, [r7, #608]\t@ 0x260\n-\tstr\tr3, [sp, #8]\n-\tldr.w\tr0, [pc, #1484]\t@ 6b64 <__gridxc_cell_MOD_cellxc+0x6588>\n-\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tstr\tr0, [sp, #8]\n+\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tstr\tr1, [sp, #4]\n+\tmov\tr1, sl\n+\tldr.w\tr0, [pc, #1376]\t@ 54e4 <__gridxc_cell_MOD_cellxc+0x4ed0>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n \tadd\tr0, pc\n-\tstr\tr3, [sp, #4]\n+\tstr\tr3, [sp, #0]\n \tstr\tr0, [sp, #20]\n \tmov\tr3, r8\n \taddw\tr0, r6, #1068\t@ 0x42c\n-\tstr\tr5, [sp, #0]\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr4, [sp, #24]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n \tldr.w\tr3, [r6, #144]\t@ 0x90\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr6, [r2, #552]\t@ 0x228\n+\tldr.w\tr2, [r2, #552]\t@ 0x228\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n \tcmp\tr3, #0\n-\tbne.w\t1416 <__gridxc_cell_MOD_cellxc+0xe3a>\n-\tb.w\t14b8 <__gridxc_cell_MOD_cellxc+0xedc>\n-\tadd.w\tr3, r7, #984\t@ 0x3d8\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tb.w\t5bc8 <__gridxc_cell_MOD_cellxc+0x55ec>\n-\tldr.w\tr2, [pc, #1420]\t@ 6b68 <__gridxc_cell_MOD_cellxc+0x658c>\n+\tbne.w\t147a <__gridxc_cell_MOD_cellxc+0xe66>\n+\tb.w\t1516 <__gridxc_cell_MOD_cellxc+0xf02>\n+\tadd.w\tr3, r7, #968\t@ 0x3c8\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tb.w\t45ee <__gridxc_cell_MOD_cellxc+0x3fda>\n+\tldr.w\tr3, [r4, #540]\t@ 0x21c\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tldr.w\tr5, [r4, #532]\t@ 0x214\n+\tadd\tr3, fp\n+\tldr.w\tr6, [r4, #544]\t@ 0x220\n+\tmla\tr5, r5, r0, r3\n+\tldr.w\tr3, [r4, #536]\t@ 0x218\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tmla\tr5, r3, r0, r5\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tcmp\tr3, #0\n+\tble.w\t41a0 <__gridxc_cell_MOD_cellxc+0x3b8c>\n+\tldr.w\tr3, [r4, #528]\t@ 0x210\n+\tadd\tr5, r6\n+\tmov\tr0, ip\n+\tlsls\tr6, r6, #3\n+\tmov\tip, r2\n+\tadd.w\tr3, r3, r5, lsl #3\n+\tldr.w\tr5, [r7, #724]\t@ 0x2d4\n+\tvldr\td7, [r3]\n+\tadds\tr0, #1\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n+\tadd\tr3, r6\n+\tcmp\tr2, r0\n+\tvstmia\tr5!, {d7}\n+\tbne.n\t5006 <__gridxc_cell_MOD_cellxc+0x49f2>\n+\tb.w\t419e <__gridxc_cell_MOD_cellxc+0x3b8a>\n+\tadd.w\tr1, r8, #852\t@ 0x354\n+\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n+\tmovs\tr2, #72\t@ 0x48\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemcpy\n+\tmov\tr0, r4\n+\tmovs\tr2, #72\t@ 0x48\n+\tadd.w\tr1, r8, #924\t@ 0x39c\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemcpy\n+\tb.w\t3862 <__gridxc_cell_MOD_cellxc+0x324e>\n+\tldr.w\tr2, [pc, #1192]\t@ 54e8 <__gridxc_cell_MOD_cellxc+0x4ed4>\n \tadd\tr2, pc\n \tldr.w\tr3, [r2, #564]\t@ 0x234\n-\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [r7, #620]\t@ 0x26c\n \tcmp\tr3, #0\n-\tbeq.w\t6b86 <__gridxc_cell_MOD_cellxc+0x65aa>\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tbeq.w\t55dc <__gridxc_cell_MOD_cellxc+0x4fc8>\n+\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n \tcmp\tr3, #0\n-\tble.w\t6b86 <__gridxc_cell_MOD_cellxc+0x65aa>\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tadd.w\tr1, r7, #824\t@ 0x338\n-\tstr.w\tr1, [r7, #668]\t@ 0x29c\n-\tadd.w\tr4, r7, #828\t@ 0x33c\n-\tstr.w\tr4, [r7, #664]\t@ 0x298\n-\tvmov.i64\td18, #0x0000000000000000\n-\tldr.w\tfp, [r3]\n-\tadd.w\tr3, r7, #820\t@ 0x334\n-\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tble.w\t55dc <__gridxc_cell_MOD_cellxc+0x4fc8>\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tadd.w\tr1, r7, #808\t@ 0x328\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr4, r7, #812\t@ 0x32c\n+\tstr.w\tr4, [r7, #672]\t@ 0x2a0\n+\tmov.w\tr9, #0\n+\tldr\tr3, [r3, #0]\n+\tmov\tr8, r9\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tadd.w\tr3, r7, #804\t@ 0x324\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n \tldrd\tr6, ip, [r2, #656]\t@ 0x290\n-\tstr.w\tr6, [r7, #676]\t@ 0x2a4\n+\tstr.w\tr6, [r7, #720]\t@ 0x2d0\n \tldr.w\tr1, [r3, #504]\t@ 0x1f8\n-\tldr.w\tr8, [r3, #520]\t@ 0x208\n+\tldr.w\tr5, [r3, #520]\t@ 0x208\n \tldr.w\tr4, [r3, #540]\t@ 0x21c\n-\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n \tldrd\tr1, r3, [r2, #584]\t@ 0x248\n-\tstr.w\tr1, [r7, #660]\t@ 0x294\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n \tldrd\tr0, r1, [r2, #164]\t@ 0xa4\n-\tstr.w\tr0, [r7, #652]\t@ 0x28c\n+\tstr.w\tr0, [r7, #668]\t@ 0x29c\n \tldr.w\tr0, [r2, #628]\t@ 0x274\n-\tstr.w\tr0, [r7, #712]\t@ 0x2c8\n+\tstr.w\tr0, [r7, #728]\t@ 0x2d8\n \tldr.w\tr0, [r2, #700]\t@ 0x2bc\n-\tstr.w\tr0, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr0, [r7, #724]\t@ 0x2d4\n \tldr.w\tr0, [r2, #684]\t@ 0x2ac\n-\tstr.w\tr0, [r7, #600]\t@ 0x258\n+\tstr.w\tr0, [r7, #636]\t@ 0x27c\n \tldr.w\tr0, [r2, #612]\t@ 0x264\n-\tstr.w\tr0, [r7, #604]\t@ 0x25c\n-\tldr.w\tr0, [r2, #192]\t@ 0xc0\n-\tldr.w\tr6, [r2, #624]\t@ 0x270\n-\tstr.w\tr4, [r7, #640]\t@ 0x280\n \tstr.w\tr0, [r7, #644]\t@ 0x284\n+\tldr.w\tr0, [r2, #192]\t@ 0xc0\n+\tldr.w\tlr, [r2, #624]\t@ 0x270\n+\tstr.w\tr4, [r7, #620]\t@ 0x26c\n \tldr.w\tr4, [r2, #696]\t@ 0x2b8\n-\tldr.w\tr5, [r2, #640]\t@ 0x280\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tmla\tr5, r0, ip, r5\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tstr.w\tr5, [r7, #452]\t@ 0x1c4\n-\tmul.w\tr5, r0, ip\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tadd.w\tip, r8, #1\n-\tldr.w\tr5, [r2, #568]\t@ 0x238\n-\tmla\tr5, r3, r0, r5\n-\tldr.w\tr0, [r7, #660]\t@ 0x294\n-\tstr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tmul.w\tr5, r3, r0\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr0, [r7, #668]\t@ 0x29c\n-\tldr\tr5, [r3, #0]\n-\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tmov\tr9, r5\n-\tldr.w\tr5, [r3, #512]\t@ 0x200\n-\tstr.w\tr5, [r7, #564]\t@ 0x234\n-\tldr\tr5, [r0, #0]\n-\tldr.w\tr0, [r7, #664]\t@ 0x298\n-\tstr.w\tr5, [r7, #624]\t@ 0x270\n-\tldr\tr5, [r0, #0]\n-\tmov\tsl, r5\n-\tldr.w\tr5, [r2, #144]\t@ 0x90\n-\tstr.w\tr5, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr5, [r3, #532]\t@ 0x214\n-\tstr.w\tr5, [r7, #516]\t@ 0x204\n-\tldr.w\tr5, [r2, #180]\t@ 0xb4\n-\tstr.w\tr5, [r7, #560]\t@ 0x230\n-\tldr.w\tr5, [r2, #632]\t@ 0x278\n-\tstr.w\tr5, [r7, #636]\t@ 0x27c\n-\tldr.w\tr5, [r2, #600]\t@ 0x258\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tldr.w\tr5, [r2, #636]\t@ 0x27c\n-\tstr.w\tr5, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr5, [r2, #704]\t@ 0x2c0\n-\tstr.w\tr5, [r7, #628]\t@ 0x274\n-\tldr.w\tr5, [r2, #672]\t@ 0x2a0\n-\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n-\tstr.w\tr5, [r7, #528]\t@ 0x210\n-\tldr.w\tr5, [r3, #536]\t@ 0x218\n+\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tldr.w\tr6, [r2, #640]\t@ 0x280\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tvldr\td5, [pc, #920]\t@ 5488 <__gridxc_cell_MOD_cellxc+0x4e74>\n+\tmla\tr6, ip, r0, r6\n+\tldr.w\tr0, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr6, [r7, #444]\t@ 0x1bc\n+\tmul.w\tr6, ip, r0\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tstr.w\tr6, [r7, #452]\t@ 0x1c4\n+\tadd.w\tip, r5, #1\n+\tldr.w\tr6, [r2, #568]\t@ 0x238\n+\tmla\tr6, r3, r0, r6\n+\tldr.w\tr0, [r7, #684]\t@ 0x2ac\n+\tstr.w\tr6, [r7, #424]\t@ 0x1a8\n+\tmul.w\tr6, r3, r0\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tstr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tldr\tr6, [r3, #0]\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tmov\tsl, r6\n+\tldr.w\tr6, [r3, #512]\t@ 0x200\n+\tstr.w\tr6, [r7, #528]\t@ 0x210\n+\tldr\tr6, [r0, #0]\n+\tldr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr6, [r7, #552]\t@ 0x228\n+\tldr\tr6, [r0, #0]\n+\tmov\tfp, r6\n+\tldr.w\tr6, [r2, #144]\t@ 0x90\n+\tstr.w\tr6, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr6, [r3, #532]\t@ 0x214\n+\tstr.w\tr6, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr6, [r2, #180]\t@ 0xb4\n+\tstr.w\tr6, [r7, #524]\t@ 0x20c\n+\tldr.w\tr6, [r2, #632]\t@ 0x278\n+\tstr.w\tr6, [r7, #600]\t@ 0x258\n+\tldr.w\tr6, [r2, #600]\t@ 0x258\n+\tstr.w\tr6, [r7, #512]\t@ 0x200\n+\tldr.w\tr6, [r2, #636]\t@ 0x27c\n+\tstr.w\tr6, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr6, [r2, #704]\t@ 0x2c0\n+\tstr.w\tr6, [r7, #592]\t@ 0x250\n+\tldr.w\tr6, [r2, #672]\t@ 0x2a0\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tstr.w\tr6, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr6, [r3, #536]\t@ 0x218\n \tldr.w\tr3, [r2, #148]\t@ 0x94\n \tldr.w\tr2, [r2, #204]\t@ 0xcc\n-\tstr.w\tr2, [r7, #616]\t@ 0x268\n-\tldr.w\tr2, [r7, #652]\t@ 0x28c\n-\tstr.w\tr5, [r7, #472]\t@ 0x1d8\n-\tmla\tr5, r1, r0, r3\n-\tstr.w\tr5, [r7, #412]\t@ 0x19c\n-\tmul.w\tr5, r2, r1\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tstr.w\tr5, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tldr.w\tr2, [r7, #668]\t@ 0x29c\n+\tstr.w\tr6, [r7, #396]\t@ 0x18c\n+\tmla\tr6, r1, r0, r3\n+\tstr.w\tr6, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr0, [r7, #720]\t@ 0x2d0\n+\tmul.w\tr6, r1, r2\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tstr.w\tr6, [r7, #404]\t@ 0x194\n \tldr.w\tr3, [r2, #544]\t@ 0x220\n-\tlsls\tr3, r3, #3\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tmov\tr1, r3\n+\tlsls\tr1, r3, #3\n \tldr.w\tr3, [r2, #528]\t@ 0x210\n-\tldr.w\tr2, [r7, #640]\t@ 0x280\n-\tadds\tr5, r3, r1\n-\tldr.w\tr1, [r7, #600]\t@ 0x258\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n-\tstr.w\tr5, [r7, #520]\t@ 0x208\n-\tldr.w\tr5, [r7, #656]\t@ 0x290\n-\tadd\tr3, ip\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr2, [r7, #620]\t@ 0x26c\n+\tadds\tr6, r3, r1\n+\tstr.w\tr6, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr6, [r7, #708]\t@ 0x2c4\n \tadds\tr3, r2, #1\n-\tadds\tr5, r3, r5\n-\tstr.w\tr5, [r7, #388]\t@ 0x184\n-\tmul.w\tr5, r1, r8\n-\tldr.w\tr1, [r7, #604]\t@ 0x25c\n-\tstr.w\tr5, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tmul.w\tr5, r1, r8\n-\tldr.w\tr1, [r7, #644]\t@ 0x284\n-\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n-\tmul.w\tr5, r8, r1\n-\tstr.w\tr5, [r7, #736]\t@ 0x2e0\n-\tmul.w\tr5, r4, r3\n-\tstr.w\tr5, [r7, #476]\t@ 0x1dc\n-\tmovs\tr3, #0\n-\tldr.w\tr0, [r7, #676]\t@ 0x2a4\n-\tldr.w\tr1, [r7, #660]\t@ 0x294\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tmul.w\tr5, r4, r0\n-\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n-\tldr.w\tr0, [r7, #652]\t@ 0x28c\n+\tstr.w\tr1, [r7, #448]\t@ 0x1c0\n+\tadds\tr6, r3, r6\n+\tldr.w\tr3, [r7, #636]\t@ 0x27c\n+\tstr.w\tr6, [r7, #376]\t@ 0x178\n+\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tmul.w\tr6, r5, r3\n+\tldr.w\tr3, [r7, #644]\t@ 0x284\n+\tstr.w\tr6, [r7, #732]\t@ 0x2dc\n+\tadd\tr1, ip\n+\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tmul.w\tr6, r5, r3\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr.w\tr6, [r7, #756]\t@ 0x2f4\n+\tmul.w\tr6, r5, r3\n+\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tstr.w\tr6, [r7, #764]\t@ 0x2fc\n+\tmul.w\tr6, r4, r3\n+\tmul.w\tr4, r4, r0\n+\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr4, [r7, #536]\t@ 0x218\n \tldr.w\tr3, [r7, #728]\t@ 0x2d8\n-\tstr.w\tr5, [r7, #608]\t@ 0x260\n-\tmul.w\tr4, r6, r4\n-\tstr.w\tr4, [r7, #436]\t@ 0x1b4\n-\tmul.w\tr4, r6, r1\n-\tldr.w\tr1, [r7, #616]\t@ 0x268\n+\tldr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr0, [r7, #668]\t@ 0x29c\n+\tstr.w\tr9, [r7, #768]\t@ 0x300\n+\tmul.w\tr4, lr, r3\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tmul.w\tr1, lr, r1\n+\tstr.w\tr4, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr1, [r7, #584]\t@ 0x248\n+\tmul.w\tlr, r0, r3\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tlsls\tr3, r3, #3\n+\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tsub.w\tr3, r3, r2, lsl #3\n-\tstr.w\tr4, [r7, #612]\t@ 0x264\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tmul.w\tlr, r0, r1\n-\tldr.w\tr1, [r7, #512]\t@ 0x200\n-\tlsls\tr1, r1, #3\n-\tstr.w\tr1, [r7, #408]\t@ 0x198\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr3, [r7, #372]\t@ 0x174\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n \tcmp\tr3, #0\n-\tble.w\t6aa8 <__gridxc_cell_MOD_cellxc+0x64cc>\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tble.w\t556e <__gridxc_cell_MOD_cellxc+0x4f5a>\n+\tldr.w\tr3, [r7, #376]\t@ 0x178\n \tmovs\tr4, #0\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n-\tadd\tr2, r3\n-\tstr.w\tr2, [r7, #396]\t@ 0x18c\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n-\tsub.w\tr3, r2, r3, lsl #3\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tadd\tr3, r8\n+\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tldr.w\tr3, [r7, #372]\t@ 0x174\n+\tsub.w\tr3, r3, r8, lsl #3\n+\tstr.w\tr3, [r7, #380]\t@ 0x17c\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n \tcmp\tr3, #0\n-\tble.w\t697a <__gridxc_cell_MOD_cellxc+0x639e>\n-\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr0, [r7, #412]\t@ 0x19c\n+\tble.w\t53d6 <__gridxc_cell_MOD_cellxc+0x4dc2>\n+\tldrd\tr2, r3, [r7, #440]\t@ 0x1b8\n+\tldr.w\tr0, [r7, #460]\t@ 0x1cc\n \tadds\tr1, r3, r2\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr6, [r7, #504]\t@ 0x1f8\n \tadd\tr1, r3\n-\tvldr\td19, [pc, #700]\t@ 6b10 <__gridxc_cell_MOD_cellxc+0x6534>\n-\tldrd\tr2, r3, [r7, #436]\t@ 0x1b4\n+\tvldr\td4, [pc, #488]\t@ 5490 <__gridxc_cell_MOD_cellxc+0x4e7c>\n+\tldrd\tr2, r3, [r7, #420]\t@ 0x1a4\n \tadds\tr2, r3, r2\n-\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n \tadd\tr2, r3\n-\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n \tadd\tr3, r0\n-\tldr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #764]\t@ 0x2fc\n \tadd\tr3, r0\n-\tldr.w\tr0, [r7, #564]\t@ 0x234\n+\tldr.w\tr0, [r7, #528]\t@ 0x210\n \tadd\tr0, r4\n-\tstr.w\tr0, [r7, #624]\t@ 0x270\n-\tmla\tr1, r0, r5, r1\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tmla\tr2, r0, r5, r2\n-\tldr.w\tr5, [r7, #560]\t@ 0x230\n-\tmla\tr3, r0, r5, r3\n-\tldr.w\tr0, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr5, [r7, #676]\t@ 0x2a4\n-\tmla\tr1, r5, r1, r0\n-\tldr.w\tr0, [r7, #744]\t@ 0x2e8\n-\tldr.w\tr5, [r7, #660]\t@ 0x294\n-\tmla\tr2, r5, r2, r0\n-\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n-\tldr.w\tr5, [r7, #652]\t@ 0x28c\n-\tmla\tr3, r5, r3, r0\n-\tldr.w\tr0, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n-\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tmla\tr3, r4, r5, r0\n-\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n-\tldr.w\tr5, [r7, #640]\t@ 0x280\n-\tadd.w\tr0, r0, r3, lsl #3\n-\tstr.w\tr0, [r7, #672]\t@ 0x2a0\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tmul.w\tr9, r4, r0\n-\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n-\tadds\tr3, r0, r5\n-\tldr.w\tr0, [r7, #628]\t@ 0x274\n-\tadd.w\tr6, r3, r9\n-\tmov\tr5, r8\n-\tadds\tr3, r0, #1\n-\tldr.w\tr0, [r7, #708]\t@ 0x2c4\n-\tmov\tr8, r2\n-\tsubs\tr0, r3, r0\n-\tstr.w\tr0, [r7, #404]\t@ 0x194\n-\tldr.w\tr0, [r7, #636]\t@ 0x27c\n-\tadds\tr3, r0, #1\n-\tldr.w\tr0, [r7, #712]\t@ 0x2c8\n-\tldr.w\tsl, [r7, #432]\t@ 0x1b0\n-\tsubs\tr0, r3, r0\n-\tstr.w\tr0, [r7, #400]\t@ 0x190\n-\tldr.w\tr0, [r7, #396]\t@ 0x18c\n-\tadd\tr0, r9\n-\tstr.w\tr0, [r7, #496]\t@ 0x1f0\n-\tmov\tr0, fp\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr0, [r7, #552]\t@ 0x228\n+\tmla\tr1, r0, r6, r1\n+\tldr.w\tr6, [r7, #512]\t@ 0x200\n+\tmla\tr2, r0, r6, r2\n+\tldr.w\tr6, [r7, #524]\t@ 0x20c\n+\tmla\tr3, r0, r6, r3\n+\tldr.w\tr0, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tmla\tr1, r6, r1, r0\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n+\tldr.w\tr6, [r7, #684]\t@ 0x2ac\n+\tmla\tr2, r6, r2, r0\n+\tldr.w\tr0, [r7, #668]\t@ 0x29c\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tmla\tr3, r0, r3, r2\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tmla\tr3, r4, r3, r9\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n+\tmul.w\tsl, r4, r3\n+\tldr.w\tr3, [r7, #620]\t@ 0x26c\n+\tadd\tr3, r8\n+\tadd.w\tr6, r3, sl\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tadds\tr3, #1\n+\tsubs\tr3, r3, r2\n+\tstr.w\tr3, [r7, #392]\t@ 0x188\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tadds\tr3, #1\n+\tsubs\tr3, r3, r2\n+\tstr.w\tr3, [r7, #388]\t@ 0x184\n+\tldr.w\tr3, [r7, #384]\t@ 0x180\n+\tldr.w\tr0, [r7, #608]\t@ 0x260\n+\tadd\tr3, sl\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #0\n-\tbeq.n\t69fc <__gridxc_cell_MOD_cellxc+0x6420>\n+\tbeq.n\t545a <__gridxc_cell_MOD_cellxc+0x4e46>\n \tcmp\tr0, #0\n-\tble.n\t698a <__gridxc_cell_MOD_cellxc+0x63ae>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmov\tr2, sl\n+\tble.n\t53e6 <__gridxc_cell_MOD_cellxc+0x4dd2>\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n \tmovs\tr3, #0\n-\tvldr\td17, [r2]\n+\tvldr\td7, [pc, #276]\t@ 5488 <__gridxc_cell_MOD_cellxc+0x4e74>\n+\tvldr\td6, [r2]\n \tadds\tr3, #1\n \tadd\tr2, lr\n-\tcmp\tr0, r3\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\t6928 <__gridxc_cell_MOD_cellxc+0x634c>\n-\tvcmpe.f64\td16, d19\n+\tcmp\tr3, r0\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\t5374 <__gridxc_cell_MOD_cellxc+0x4d60>\n+\tvcmpe.f64\td7, d4\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t698a <__gridxc_cell_MOD_cellxc+0x63ae>\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tbmi.n\t53e6 <__gridxc_cell_MOD_cellxc+0x4dd2>\n+\tldr.w\tr3, [r7, #452]\t@ 0x1c4\n \tadds\tr6, #1\n+\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n \tadd\tr1, r3\n-\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n \tadds\tr3, #8\n-\tstr.w\tr3, [r7, #672]\t@ 0x2a0\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tadd\tr8, r3\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tadd\tsl, r3\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n \tcmp\tr3, r6\n-\tbne.n\t6914 <__gridxc_cell_MOD_cellxc+0x6338>\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tmov\tfp, r0\n-\tldr.w\tr2, [r7, #656]\t@ 0x290\n-\tmov\tr8, r5\n-\tmov\tsl, r5\n+\tbne.n\t535e <__gridxc_cell_MOD_cellxc+0x4d4a>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov\tfp, r5\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr0, [r7, #608]\t@ 0x260\n \tadd\tr3, r2\n-\tmov\tr9, r3\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n+\tmov\tsl, r3\n+\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n \tadds\tr3, r4, #1\n \tcmp\tr4, r2\n-\tbge.w\t6aa8 <__gridxc_cell_MOD_cellxc+0x64cc>\n+\tbge.w\t556e <__gridxc_cell_MOD_cellxc+0x4f5a>\n \tmov\tr4, r3\n-\tb.n\t682e <__gridxc_cell_MOD_cellxc+0x6252>\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tb.n\t5286 <__gridxc_cell_MOD_cellxc+0x4c72>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tcmp\tr3, #0\n-\tbeq.n\t6a26 <__gridxc_cell_MOD_cellxc+0x644a>\n-\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n-\tldr.w\tr2, [r7, #636]\t@ 0x27c\n+\tbeq.n\t54ec <__gridxc_cell_MOD_cellxc+0x4ed8>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n \tcmp\tr3, r2\n-\tbgt.n\t69be <__gridxc_cell_MOD_cellxc+0x63e2>\n-\tldr.w\tfp, [r7, #400]\t@ 0x190\n-\tmov\tr2, r8\n+\tbgt.n\t541c <__gridxc_cell_MOD_cellxc+0x4e08>\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n \tmovs\tr3, #0\n-\tstr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tldr.w\tr1, [r7, #612]\t@ 0x264\n+\tldr.w\tfp, [r7, #388]\t@ 0x184\n+\tstr.w\tr1, [r7, #608]\t@ 0x260\n+\tldr.w\tr1, [r7, #584]\t@ 0x248\n \tadds\tr3, #1\n-\tvstr\td18, [r2]\n-\tcmp\tr3, fp\n+\tvstr\td5, [r2]\n+\tcmp\tfp, r3\n \tadd\tr2, r1\n-\tbne.n\t69aa <__gridxc_cell_MOD_cellxc+0x63ce>\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tbne.n\t5408 <__gridxc_cell_MOD_cellxc+0x4df4>\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.n\t6942 <__gridxc_cell_MOD_cellxc+0x6366>\n-\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tbeq.n\t538e <__gridxc_cell_MOD_cellxc+0x4d7a>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #0\n-\tbeq.n\t6a50 <__gridxc_cell_MOD_cellxc+0x6474>\n-\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n-\tldr.w\tr2, [r7, #628]\t@ 0x274\n+\tbeq.n\t5516 <__gridxc_cell_MOD_cellxc+0x4f02>\n+\tldr.w\tr3, [r7, #724]\t@ 0x2d4\n+\tldr.w\tr2, [r7, #592]\t@ 0x250\n \tcmp\tr3, r2\n-\tbgt.n\t6942 <__gridxc_cell_MOD_cellxc+0x6366>\n-\tldr.w\tfp, [r7, #404]\t@ 0x194\n+\tbgt.n\t538e <__gridxc_cell_MOD_cellxc+0x4d7a>\n+\tldr.w\tfp, [r7, #392]\t@ 0x188\n \tmov\tr2, r1\n \tmovs\tr3, #0\n-\tstr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tstr.w\tr1, [r7, #608]\t@ 0x260\n+\tldr.w\tr1, [r7, #536]\t@ 0x218\n \tadds\tr3, #1\n-\tvstr\td18, [r2]\n-\tcmp\tr3, fp\n+\tvstr\td5, [r2]\n+\tcmp\tfp, r3\n \tadd\tr2, r1\n-\tbne.n\t69e6 <__gridxc_cell_MOD_cellxc+0x640a>\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tb.n\t6942 <__gridxc_cell_MOD_cellxc+0x6366>\n+\tbne.n\t5444 <__gridxc_cell_MOD_cellxc+0x4e30>\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tb.n\t538e <__gridxc_cell_MOD_cellxc+0x4d7a>\n \tcmp\tr0, #0\n-\tble.n\t698a <__gridxc_cell_MOD_cellxc+0x63ae>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr.w\tfp, [r7, #460]\t@ 0x1cc\n+\tble.n\t53e6 <__gridxc_cell_MOD_cellxc+0x4dd2>\n+\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tldr.w\tfp, [r7, #448]\t@ 0x1c0\n+\tvldr\td7, [pc, #32]\t@ 5488 <__gridxc_cell_MOD_cellxc+0x4e74>\n \tadd.w\tr2, r3, r6, lsl #3\n-\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n-\tvldr\td17, [r2]\n-\tadds\tr3, #1\n-\tadd\tr2, fp\n-\tcmp\tr0, r3\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\t6a14 <__gridxc_cell_MOD_cellxc+0x6438>\n-\tb.n\t6938 <__gridxc_cell_MOD_cellxc+0x635c>\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n-\tcmp\tr3, #0\n-\tble.n\t69be <__gridxc_cell_MOD_cellxc+0x63e2>\n-\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n-\tmov\tfp, r1\n \tldr.w\tr3, [r7, #744]\t@ 0x2e8\n-\tldr.w\tr1, [r7, #408]\t@ 0x198\n+\tvldr\td6, [r2]\n \tadds\tr3, #1\n-\tvstr\td18, [r2]\n-\tadd\tr2, r1\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n-\tcmp\tr3, r1\n-\tbne.n\t6a38 <__gridxc_cell_MOD_cellxc+0x645c>\n-\tmov\tr1, fp\n-\tb.n\t69be <__gridxc_cell_MOD_cellxc+0x63e2>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tmul.w\tfp, r4, r3\n-\tldr.w\tr3, [r7, #572]\t@ 0x23c\n-\tcmp\tr3, #0\n-\tbeq.w\t6942 <__gridxc_cell_MOD_cellxc+0x6366>\n-\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr3, [r7, #620]\t@ 0x26c\n-\tstr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tadds\tr3, r2, r3\n-\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n-\tadd\tr3, r2\n-\tadd\tr3, fp\n-\tadds\tr2, r3, r6\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n-\tsub.w\tr3, r3, r9, lsl #3\n-\tadd.w\tr3, r3, r2, lsl #3\n-\tldr.w\tr2, [r7, #620]\t@ 0x26c\n-\tmov.w\tfp, r2, lsl #3\n-\tldr.w\tr2, [r7, #724]\t@ 0x2d4\n-\tldr.w\tr1, [r7, #572]\t@ 0x23c\n-\tadds\tr2, #1\n-\tvstr\td18, [r3]\n-\tadd\tr3, fp\n-\tcmp\tr1, r2\n-\tbne.n\t6a92 <__gridxc_cell_MOD_cellxc+0x64b6>\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tb.n\t6942 <__gridxc_cell_MOD_cellxc+0x6366>\n-\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tmov\tr8, ip\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n-\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #600]\t@ 0x258\n-\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #604]\t@ 0x25c\n-\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n-\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #644]\t@ 0x284\n-\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n-\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tcmp\tip, r3\n-\tbeq.n\t6b6c <__gridxc_cell_MOD_cellxc+0x6590>\n-\tadd.w\tip, ip, #1\n-\tb.n\t6808 <__gridxc_cell_MOD_cellxc+0x622c>\n+\tadd\tr2, fp\n+\tcmp\tr3, r0\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\t5472 <__gridxc_cell_MOD_cellxc+0x4e5e>\n+\tb.n\t5384 <__gridxc_cell_MOD_cellxc+0x4d70>\n \tnop.w\n+\t...\n \t.word\t0xe826d695\n \t.word\t0x3e112e0b\n-\t.word\t0x00000a84\n+\t.word\t0x00000a14\n R_ARM_REL32\t.bss\n-\t.word\t0x00000a86\n+\t.word\t0x00000a16\n R_ARM_REL32\t.data\n-\t.word\t0x000009d0\n+\t.word\t0x00000960\n R_ARM_REL32\t.bss\n-\t.word\t0x000009d0\n+\t.word\t0x00000960\n R_ARM_REL32\t.data\n-\t.word\t0x000009b0\n+\t.word\t0x00000940\n R_ARM_REL32\t.LC26\n-\t.word\t0x0000099e\n+\t.word\t0x0000092e\n R_ARM_REL32\t.LC24\n-\t.word\t0x000008aa\n+\t.word\t0x00000848\n R_ARM_REL32\t.rodata\n-\t.word\t0x000008a0\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000089e\n+\t.word\t0x0000083e\n R_ARM_REL32\t.LC29\n-\t.word\t0x0000080a\n+\t.word\t0x00000836\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000079e\n R_ARM_REL32\t.LC30\n-\t.word\t0x000007ca\n+\t.word\t0x0000075e\n R_ARM_REL32\t.LC31\n-\t.word\t0x00000790\n+\t.word\t0x00000726\n R_ARM_REL32\t.LC32\n-\t.word\t0x00000754\n+\t.word\t0x000006ec\n R_ARM_REL32\t.LC33\n-\t.word\t0x0000071c\n+\t.word\t0x000006b2\n R_ARM_REL32\t.LC34\n-\t.word\t0x000006de\n+\t.word\t0x00000670\n R_ARM_REL32\t.LC35\n-\t.word\t0x000006a0\n+\t.word\t0x00000632\n R_ARM_REL32\t.LC36\n-\t.word\t0x00000660\n+\t.word\t0x000005f8\n R_ARM_REL32\t.LC37\n-\t.word\t0x00000628\n+\t.word\t0x000005c4\n R_ARM_REL32\t.LC38\n-\t.word\t0x000005ec\n+\t.word\t0x00000584\n R_ARM_REL32\t.LC39\n-\t.word\t0x000005c2\n+\t.word\t0x00000558\n R_ARM_REL32\t.LC40\n-\t.word\t0x00000586\n+\t.word\t0x000004a4\n R_ARM_REL32\t.bss\n-\tldr.w\tr3, [r7, #664]\t@ 0x298\n-\tldr.w\tr2, [r7, #624]\t@ 0x270\n-\tstr.w\tsl, [r3]\n-\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n+\tcmp\tr3, #0\n+\tble.n\t541c <__gridxc_cell_MOD_cellxc+0x4e08>\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tmov\tfp, r1\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n+\tadds\tr3, #1\n+\tvstr\td5, [r2]\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tcmp\tr1, r3\n+\tbne.n\t54fe <__gridxc_cell_MOD_cellxc+0x4eea>\n+\tmov\tr1, fp\n+\tb.n\t541c <__gridxc_cell_MOD_cellxc+0x4e08>\n+\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n+\tmul.w\tfp, r4, r3\n+\tldr.w\tr3, [r7, #572]\t@ 0x23c\n+\tcmp\tr3, #0\n+\tbeq.w\t538e <__gridxc_cell_MOD_cellxc+0x4d7a>\n+\tldr.w\tr2, [r7, #408]\t@ 0x198\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tstr.w\tr1, [r7, #608]\t@ 0x260\n+\tadds\tr3, r2, r3\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tadd\tr3, r2\n+\tadd\tr3, fp\n+\tadds\tr2, r3, r6\n+\tldr.w\tr3, [r7, #380]\t@ 0x17c\n+\tsub.w\tr3, r3, sl, lsl #3\n+\tadd.w\tr3, r3, r2, lsl #3\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tmov.w\tfp, r2, lsl #3\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr1, [r7, #572]\t@ 0x23c\n+\tadds\tr2, #1\n+\tvstr\td5, [r3]\n+\tadd\tr3, fp\n+\tcmp\tr2, r1\n+\tbne.n\t5558 <__gridxc_cell_MOD_cellxc+0x4f44>\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tb.n\t538e <__gridxc_cell_MOD_cellxc+0x4d7a>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tmov\tr5, ip\n+\tldr.w\tr2, [r7, #432]\t@ 0x1b0\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #396]\t@ 0x18c\n+\tldr.w\tr2, [r7, #636]\t@ 0x27c\n+\tadd\tr8, r3\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tstr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n+\tcmp\tip, r3\n+\tbeq.n\t55c2 <__gridxc_cell_MOD_cellxc+0x4fae>\n+\tadd.w\tip, ip, #1\n+\tb.n\t5264 <__gridxc_cell_MOD_cellxc+0x4c50>\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tstr.w\tfp, [r3]\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tstr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n-\tstr.w\tr9, [r3]\n-\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tstr.w\tsl, [r3]\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tcmp\tr3, #0\n-\tbeq.w\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n-\tldr.w\tr4, [pc, #1396]\t@ 7108 <__gridxc_cell_MOD_cellxc+0x6b2c>\n-\tadd\tr4, pc\n-\tmov\tr1, r4\n-\tadds\tr0, r4, #4\n+\tbeq.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n+\tldr.w\tr8, [pc, #3388]\t@ 6324 <__gridxc_cell_MOD_cellxc+0x5d10>\n+\tadd\tr8, pc\n+\tmov\tr1, r8\n+\tadd.w\tr0, r8, #4\n \tbl\t0 <__gridxc_mesh3d_MOD_samemeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_samemeshdistr\n-\tmov\tr6, r0\n+\tmov\tr4, r0\n \tcmp\tr0, #0\n-\tbeq.w\t6da0 <__gridxc_cell_MOD_cellxc+0x67c4>\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tbeq.w\t74a2 <__gridxc_cell_MOD_cellxc+0x6e8e>\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, #0\n-\tble.n\t6ca6 <__gridxc_cell_MOD_cellxc+0x66ca>\n-\tldrd\tr2, r3, [r7, #592]\t@ 0x250\n+\tble.n\t5702 <__gridxc_cell_MOD_cellxc+0x50ee>\n+\tldr.w\tr2, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #564]\t@ 0x234\n \torrs\tr3, r2\n-\tbmi.n\t6ca6 <__gridxc_cell_MOD_cellxc+0x66ca>\n-\tldr.w\tr2, [pc, #1356]\t@ 710c <__gridxc_cell_MOD_cellxc+0x6b30>\n+\tbmi.n\t5702 <__gridxc_cell_MOD_cellxc+0x50ee>\n+\tldr.w\tr2, [pc, #3340]\t@ 6328 <__gridxc_cell_MOD_cellxc+0x5d14>\n \tmovs\tr6, #0\n-\tstr.w\tr6, [r7, #760]\t@ 0x2f8\n+\tmov\tr8, r6\n \tadd\tr2, pc\n \tldrd\tip, r1, [r2, #624]\t@ 0x270\n \tldr.w\tr3, [r2, #568]\t@ 0x238\n \tmla\tr5, r1, ip, r3\n \tldrd\tr4, r1, [r2, #612]\t@ 0x264\n \tldrd\tr0, r3, [r2, #600]\t@ 0x258\n \tmla\tr5, r1, r4, r5\n \tmla\tr5, r3, r0, r5\n \tldrd\tr1, r3, [r2, #588]\t@ 0x24c\n \tmla\tr5, r3, r1, r5\n \tldr.w\tr3, [r2, #584]\t@ 0x248\n \tldr.w\tr2, [r2, #564]\t@ 0x234\n-\tmul.w\tr8, r3, r0\n-\tmla\tr9, r3, r5, r2\n-\tmul.w\tr2, r3, ip\n-\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tmul.w\tr2, r3, r4\n+\tmul.w\tr4, r3, r4\n+\tmla\tr2, r3, r5, r2\n+\tstr.w\tr4, [r7, #776]\t@ 0x308\n+\tmul.w\tr5, r3, ip\n+\tmul.w\tr0, r3, r0\n+\tstr.w\tr5, [r7, #792]\t@ 0x318\n \tmul.w\tr3, r1, r3\n-\tstr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tmov\tr2, r6\n-\tmov\tr0, r9\n+\tstr.w\tr0, [r7, #784]\t@ 0x310\n+\tmov\tr9, r6\n+\tmov\tr0, r2\n \tmovs\tr4, #0\n-\tmov\tr5, r2\n-\tstr.w\tr2, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tmov\tr5, r9\n+\tldr.w\tr2, [r7, #564]\t@ 0x234\n \tmov\tip, r0\n \tmov.w\tlr, #0\n \tmov\tr1, r0\n-\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr0, [r7, #704]\t@ 0x2c0\n \tmov\tsl, ip\n-\tstr.w\tr8, [r7, #744]\t@ 0x2e8\n+\tstr.w\tlr, [r7, #764]\t@ 0x2fc\n \tadd.w\tfp, r0, r5, lsl #3\n \tmovs\tr0, #0\n-\tvldr\td16, [sl]\n-\tcmp\tr2, r0\n+\tvldr\td7, [sl]\n+\tcmp\tr0, r2\n \tadd\tsl, r3\n \tadd.w\tr0, r0, #1\n-\tvstmia\tfp!, {d16}\n-\tbne.n\t6c38 <__gridxc_cell_MOD_cellxc+0x665c>\n-\tldr.w\tr0, [r7, #704]\t@ 0x2c0\n+\tvstmia\tfp!, {d7}\n+\tbne.n\t5696 <__gridxc_cell_MOD_cellxc+0x5082>\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tldr.w\tlr, [r7, #764]\t@ 0x2fc\n+\tadd\tip, r0\n+\tldr.w\tr0, [r7, #716]\t@ 0x2cc\n \tadd.w\tsl, lr, #1\n-\tldr.w\tr8, [r7, #744]\t@ 0x2e8\n \tadd\tr5, r0\n-\tldr.w\tr0, [r7, #596]\t@ 0x254\n-\tadd\tip, r8\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n \tcmp\tlr, r0\n-\tbeq.n\t6c66 <__gridxc_cell_MOD_cellxc+0x668a>\n+\tbeq.n\t56c8 <__gridxc_cell_MOD_cellxc+0x50b4>\n \tmov\tlr, sl\n-\tb.n\t6c28 <__gridxc_cell_MOD_cellxc+0x664c>\n+\tb.n\t5686 <__gridxc_cell_MOD_cellxc+0x5072>\n \tmov\tr0, r1\n-\tldr.w\tr1, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tldr.w\tr5, [r7, #580]\t@ 0x244\n \tadd\tr0, r1\n-\tldr.w\tr1, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tcmp\tr4, r5\n-\tadd\tr2, r1\n+\tadd\tr9, r1\n \tadd.w\tr1, r4, #1\n-\tbeq.n\t6c88 <__gridxc_cell_MOD_cellxc+0x66ac>\n+\tbeq.n\t56ea <__gridxc_cell_MOD_cellxc+0x50d6>\n \tmov\tr4, r1\n-\tb.n\t6c16 <__gridxc_cell_MOD_cellxc+0x663a>\n-\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n-\tadd\tr9, r1\n-\tldr.w\tr1, [r7, #512]\t@ 0x200\n-\tadds\tr2, #1\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tb.n\t5674 <__gridxc_cell_MOD_cellxc+0x5060>\n+\tldr.w\tr1, [r7, #792]\t@ 0x318\n+\tadd.w\tr8, r8, #1\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r7, #544]\t@ 0x220\n \tadd\tr6, r1\n-\tldr.w\tr1, [r7, #764]\t@ 0x2fc\n-\tcmp\tr2, r1\n-\tbne.n\t6c10 <__gridxc_cell_MOD_cellxc+0x6634>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r7, #796]\t@ 0x31c\n+\tcmp\tr8, r1\n+\tbne.n\t566e <__gridxc_cell_MOD_cellxc+0x505a>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.w\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n+\tbeq.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n \tldr.w\tr3, [r7, #572]\t@ 0x23c\n \tcmp\tr3, #0\n-\tbeq.w\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tbeq.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n+\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n+\tldr.w\tr3, [r7, #548]\t@ 0x224\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tldr.w\tr2, [r7, #480]\t@ 0x1e0\n \torrs\tr3, r2\n-\tbmi.w\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n-\tldr.w\tr3, [pc, #1088]\t@ 7110 <__gridxc_cell_MOD_cellxc+0x6b34>\n-\tldr.w\tr2, [r7, #620]\t@ 0x26c\n+\tbmi.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n+\tldr.w\tr3, [pc, #3072]\t@ 632c <__gridxc_cell_MOD_cellxc+0x5d18>\n+\tmov.w\tr8, #0\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n \tadd\tr3, pc\n-\tldr.w\tr1, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr1, [r7, #408]\t@ 0x198\n \tadd.w\tlr, r2, r1\n-\tmovs\tr2, #0\n \tldrd\tr6, r1, [r3, #696]\t@ 0x2b8\n-\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n \tldr.w\tr2, [r3, #640]\t@ 0x280\n \tmla\tr2, r1, r6, r2\n \tldrd\tr5, r1, [r3, #684]\t@ 0x2ac\n \tmla\tr2, r1, r5, r2\n \tldrd\tr4, r1, [r3, #672]\t@ 0x2a0\n \tmla\tr2, r1, r4, r2\n \tldrd\tr1, r0, [r3, #660]\t@ 0x294\n \tmla\tr2, r0, r1, r2\n \tldr.w\tr0, [r3, #656]\t@ 0x290\n \tldr.w\tr3, [r3, #636]\t@ 0x27c\n-\tmul.w\tr8, r0, r4\n-\tmla\tr9, r0, r2, r3\n-\tmul.w\tr3, r0, r6\n-\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n-\tmul.w\tr3, r0, r5\n+\tmla\tr3, r0, r2, r3\n+\tmul.w\tr2, r0, r6\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tmul.w\tr2, r0, r5\n+\tstr.w\tr2, [r7, #776]\t@ 0x308\n+\tmul.w\tr2, r0, r4\n \tmul.w\tr0, r1, r0\n-\tstr.w\tr3, [r7, #756]\t@ 0x2f4\n-\tmov\tr3, lr\n-\tmov\tr1, r9\n+\tstr.w\tr2, [r7, #792]\t@ 0x318\n+\tmov\tr9, lr\n+\tmov\tr1, r3\n \tmovs\tr4, #0\n-\tmov\tr5, r3\n+\tmov\tr5, r9\n \tmov\tr6, r1\n \tmov.w\tip, #0\n \tmov\tr2, r1\n-\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r7, #752]\t@ 0x2f0\n \tmov\tsl, r6\n-\tstrd\tr3, r5, [r7, #744]\t@ 0x2e8\n+\tstrd\tr3, r6, [r7, #764]\t@ 0x2fc\n \tadd.w\tfp, r1, r5, lsl #3\n \tmovs\tr1, #0\n-\tvldr\td16, [sl]\n+\tvldr\td7, [sl]\n \tadd\tsl, r0\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tvstmia\tfp!, {d16}\n+\tldr.w\tr3, [r7, #548]\t@ 0x224\n+\tvstmia\tfp!, {d7}\n \tcmp\tr3, r1\n \tadd.w\tr1, r1, #1\n-\tbne.n\t6d4e <__gridxc_cell_MOD_cellxc+0x6772>\n-\tldrd\tr3, r5, [r7, #744]\t@ 0x2e8\n-\tadd\tr6, r8\n-\tldr.w\tr1, [r7, #532]\t@ 0x214\n+\tbne.n\t57ac <__gridxc_cell_MOD_cellxc+0x5198>\n+\tldrd\tr3, r6, [r7, #764]\t@ 0x2fc\n \tadd.w\tsl, ip, #1\n+\tldr.w\tr1, [r7, #792]\t@ 0x318\n+\tadd\tr6, r1\n+\tldr.w\tr1, [r7, #436]\t@ 0x1b4\n \tadd\tr5, r1\n-\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n \tcmp\tip, r1\n-\tbeq.n\t6d80 <__gridxc_cell_MOD_cellxc+0x67a4>\n+\tbeq.w\t7326 <__gridxc_cell_MOD_cellxc+0x6d12>\n \tmov\tip, sl\n-\tb.n\t6d3e <__gridxc_cell_MOD_cellxc+0x6762>\n-\tmov\tr1, r2\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tb.n\t579c <__gridxc_cell_MOD_cellxc+0x5188>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tadds\tr3, r2, #1\n+\tcmp\tr2, r1\n+\tbeq.w\t6bd6 <__gridxc_cell_MOD_cellxc+0x65c2>\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tb.w\t409c <__gridxc_cell_MOD_cellxc+0x3a88>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr\tr3, [r3, #0]\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tcmp\tr3, #0\n+\tble.w\t6ba0 <__gridxc_cell_MOD_cellxc+0x658c>\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tmov.w\tr8, #1\n+\tldr.w\tr3, [r3, #552]\t@ 0x228\n+\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr3, [pc, #2832]\t@ 6330 <__gridxc_cell_MOD_cellxc+0x5d1c>\n+\tadd\tr3, pc\n+\tldr.w\tr2, [r3, #1812]\t@ 0x714\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr.w\tr2, [r3, #1860]\t@ 0x744\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr2, [r3, #1848]\t@ 0x738\n+\tstr.w\tr2, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r3, #1836]\t@ 0x72c\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #460]\t@ 0x1cc\n+\tldr.w\tr6, [r3, #1872]\t@ 0x750\n+\tldr.w\tr5, [r3, #1832]\t@ 0x728\n+\tcmp\tr2, #0\n+\tble.w\t59e8 <__gridxc_cell_MOD_cellxc+0x53d4>\n+\tldr.w\tr1, [r3, #1680]\t@ 0x690\n+\tldr.w\tr2, [r3, #1660]\t@ 0x67c\n+\tldr.w\tr0, [r3, #1676]\t@ 0x68c\n+\tldr.w\tr9, [r3, #1288]\t@ 0x508\n+\tldr.w\tr4, [r3, #1332]\t@ 0x534\n+\tmla\tr2, r1, r8, r2\n+\tldr.w\tr1, [r3, #1656]\t@ 0x678\n+\tmla\tip, r0, r2, r1\n+\tldr.w\tr1, [r3, #1800]\t@ 0x708\n+\tldr.w\tr2, [r3, #1768]\t@ 0x6e8\n+\tldr.w\tr0, [r3, #1284]\t@ 0x504\n+\tmla\tr2, r1, r8, r2\n+\tldr.w\tr1, [r3, #1764]\t@ 0x6e4\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr2, [r3, #1816]\t@ 0x718\n+\tstr.w\tr1, [r7, #692]\t@ 0x2b4\n+\tadd.w\tlr, r6, r2\n+\tldr.w\tr2, [r3, #1320]\t@ 0x528\n+\tldr.w\tr1, [r3, #1788]\t@ 0x6fc\n+\tmov\tfp, r2\n+\tldr.w\tr2, [r3, #1308]\t@ 0x51c\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r3, #1304]\t@ 0x518\n+\tldr.w\tr3, [r3, #1784]\t@ 0x6f8\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tcmp\tr3, #0\n+\tble.w\t59e8 <__gridxc_cell_MOD_cellxc+0x53d4>\n+\tmla\tr1, r2, r9, r0\n+\tmov\tr0, fp\n+\tmul.w\tr3, r2, r4\n+\tmovs\tr4, #0\n+\tstr.w\tr3, [r7, #524]\t@ 0x20c\n+\tmul.w\tr0, r2, r0\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr.w\tr0, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tmla\tr3, r5, lr, r3\n+\tmul.w\tlr, r2, r0\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tmul.w\tr2, r5, r2\n+\tstr.w\tr2, [r7, #528]\t@ 0x210\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tmul.w\tr2, r5, r2\n+\tstr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tmul.w\tr2, r5, r2\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tmov\tr2, r4\n+\tmovs\tr0, #0\n+\tstr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tmov\tr0, r3\n+\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr2, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr8, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr3, [r7, #404]\t@ 0x194\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tcmp\tr3, #0\n+\tble.n\t5996 <__gridxc_cell_MOD_cellxc+0x5382>\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tmov\tr8, r0\n+\tmovs\tr2, #0\n+\tstr.w\tr1, [r7, #552]\t@ 0x228\n+\tstr.w\tr0, [r7, #536]\t@ 0x218\n+\tb.n\t597c <__gridxc_cell_MOD_cellxc+0x5368>\n+\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tadds\tr4, #1\n+\tldr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tadd\tr3, lr\n+\tadd.w\tr9, r2, #1\n+\tmla\tfp, r4, r0, r1\n+\tldr.w\tr1, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tmla\tfp, r0, fp, r1\n+\tvldr\td7, [fp]\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n+\tvstr\td7, [r8]\n+\tadd\tr8, r1\n+\tldr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tcmp\tr2, r1\n+\tbeq.n\t598e <__gridxc_cell_MOD_cellxc+0x537a>\n+\tmov\tr2, r9\n+\tldr\tr1, [r3, #0]\n+\tcmp\tr1, #0\n+\tbne.n\t5944 <__gridxc_cell_MOD_cellxc+0x5330>\n+\tadd\tr3, lr\n+\tadd.w\tr9, r2, #1\n+\tvldr\td7, [ip]\n+\tb.n\t5968 <__gridxc_cell_MOD_cellxc+0x5354>\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tadd\tr0, r3\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tadd.w\tr8, r2, #1\n+\tcmp\tr2, r3\n+\tbeq.n\t59c0 <__gridxc_cell_MOD_cellxc+0x53ac>\n+\tstr.w\tr8, [r7, #696]\t@ 0x2b8\n+\tb.n\t592a <__gridxc_cell_MOD_cellxc+0x5316>\n+\tldr.w\tr0, [r7, #524]\t@ 0x20c\n+\tldr.w\tr3, [r7, #404]\t@ 0x194\n+\tadd\tr1, r0\n+\tldr.w\tr0, [r7, #528]\t@ 0x210\n+\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n+\tadd\tr3, r0\n+\tldr.w\tr0, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr8, [r7, #420]\t@ 0x1a4\n+\tadd.w\tr9, r2, #1\n+\tcmp\tr2, r0\n+\tbeq.n\t59e8 <__gridxc_cell_MOD_cellxc+0x53d4>\n+\tmov\tr2, r9\n+\tb.n\t5912 <__gridxc_cell_MOD_cellxc+0x52fe>\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmovs\tr1, #0\n+\tldr.w\tr2, [r7, #648]\t@ 0x288\n+\tldr.w\tr4, [pc, #2368]\t@ 6334 <__gridxc_cell_MOD_cellxc+0x5d20>\n+\tstr\tr5, [r3, #20]\n+\tmov\tr5, r3\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tadd\tr4, pc\n+\tstrd\tr1, r1, [r2]\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tstr\tr3, [r5, #24]\n+\tnegs\tr3, r3\n+\tstr\tr2, [r5, #36]\t@ 0x24\n+\tsubs\tr3, r3, r2\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tstr\tr6, [r5, #60]\t@ 0x3c\n+\tsubs\tr3, r3, r2\n+\tstr\tr2, [r5, #48]\t@ 0x30\n+\tsubs\tr3, r3, r6\n+\tstr\tr3, [r5, #4]\n+\tmovs\tr3, #1\n+\tstr\tr3, [r5, #28]\n+\tstr\tr3, [r5, #40]\t@ 0x28\n+\tmov\tr2, r5\n+\tstr\tr3, [r5, #52]\t@ 0x34\n+\tstrd\tr3, r3, [r5, #64]\t@ 0x40\n+\tldr.w\tr3, [r4, #1876]\t@ 0x754\n+\tldr.w\tr1, [pc, #2308]\t@ 6338 <__gridxc_cell_MOD_cellxc+0x5d24>\n+\trsb\tr3, r3, #1\n+\tldr.w\tr0, [r7, #488]\t@ 0x1e8\n+\tadd\tr1, pc\n+\tmul.w\tr3, r6, r3\n+\tldr.w\tr6, [r7, #664]\t@ 0x298\n+\tadd.w\tr3, r6, r3, lsl #3\n+\tstr\tr3, [r5, #0]\n+\tldr.w\tr3, [r4, #1840]\t@ 0x730\n+\tldr.w\tr5, [r4, #1844]\t@ 0x734\n+\trsb\tlr, r3, #1\n+\tldr.w\tr3, [r4, #1852]\t@ 0x73c\n+\tadd\tr5, lr\n+\tstr\tr5, [r2, #32]\n+\tldr.w\tr5, [r4, #1856]\t@ 0x740\n+\trsb\tip, r3, #1\n+\tldr.w\tr3, [r4, #1864]\t@ 0x748\n+\tadd\tr5, ip\n+\tstr\tr5, [r2, #44]\t@ 0x2c\n+\tldr.w\tr5, [r4, #1868]\t@ 0x74c\n+\trsb\tr6, r3, #1\n+\tmovs\tr3, #8\n+\tstr\tr3, [r2, #8]\n+\tadd\tr5, r6\n+\tmov.w\tr3, #772\t@ 0x304\n+\tstr\tr5, [r2, #56]\t@ 0x38\n+\tstrh\tr3, [r2, #16]\n+\tbl\t0 <__gridxc_fftr_MOD_fftr2k>\n+ R_ARM_THM_CALL\t__gridxc_fftr_MOD_fftr2k\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tcmp\tr3, #0\n+\tble.n\t5b8e <__gridxc_cell_MOD_cellxc+0x557a>\n+\tldr.w\tr2, [r4, #1800]\t@ 0x708\n+\tldr.w\tr3, [r4, #1768]\t@ 0x6e8\n+\tldr.w\tr1, [r4, #1764]\t@ 0x6e4\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r4, #1788]\t@ 0x6fc\n+\tmla\tr3, r2, r8, r3\n+\tldr.w\tr2, [r4, #1816]\t@ 0x718\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r4, #1872]\t@ 0x750\n+\tldr.w\tip, [r4, #1812]\t@ 0x714\n+\tldr.w\tr0, [r4, #1860]\t@ 0x744\n+\tadd\tr3, r2\n+\tldr.w\tr5, [r4, #1848]\t@ 0x738\n+\tldr.w\tr6, [r4, #1836]\t@ 0x72c\n+\tldr.w\tr2, [r4, #1832]\t@ 0x728\n+\tstr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr1, [r4, #1784]\t@ 0x6f8\n+\tldr.w\tr4, [r7, #636]\t@ 0x27c\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tcmp\tr4, #0\n+\tble.n\t5b8e <__gridxc_cell_MOD_cellxc+0x557a>\n+\tmul.w\tr4, r2, r0\n+\tmla\tr3, r2, r3, ip\n+\tmul.w\tr0, r2, r5\n+\tmul.w\tr5, r2, r6\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tmovs\tr0, #0\n+\tmul.w\tr6, r1, r2\n+\tmov\tr1, r0\n+\tmov\tip, r3\n+\tmov.w\tlr, #0\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tcmp.w\tsl, #0\n+\tble.n\t5b62 <__gridxc_cell_MOD_cellxc+0x554e>\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tadd.w\tr9, r0, #1\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tadd.w\tfp, sl, r0\n+\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr9, [r7, #656]\t@ 0x290\n+\tstr.w\tip, [r7, #664]\t@ 0x298\n+\tmla\tr2, r9, r3, r2\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tmla\tr2, r0, r2, r3\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tmov\tr0, ip\n+\tb.n\t5b44 <__gridxc_cell_MOD_cellxc+0x5530>\n+\tadd.w\tr9, r9, #1\n+\tvldr\td7, [r0]\n+\tcmp\tr9, fp\n+\tadd\tr0, r5\n+\tvstr\td7, [r2]\n+\tadd\tr2, r6\n+\tbne.n\t5b40 <__gridxc_cell_MOD_cellxc+0x552c>\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tadd\tr0, r3\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tadd.w\tr2, lr, #1\n+\tadd\tip, r3\n+\tldr.w\tr3, [r7, #644]\t@ 0x284\n+\tcmp\tlr, r3\n+\tbeq.n\t5b78 <__gridxc_cell_MOD_cellxc+0x5564>\n+\tmov\tlr, r2\n+\tb.n\t5b0a <__gridxc_cell_MOD_cellxc+0x54f6>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tadd.w\tip, r1, #1\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tadd\tr3, r4\n+\tcmp\tr1, r2\n+\tbeq.n\t5b8e <__gridxc_cell_MOD_cellxc+0x557a>\n+\tmov\tr1, ip\n+\tb.n\t5b00 <__gridxc_cell_MOD_cellxc+0x54ec>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr3, r8\n+\tbge.w\t581c <__gridxc_cell_MOD_cellxc+0x5208>\n+\tldr.w\tr2, [pc, #1948]\t@ 633c <__gridxc_cell_MOD_cellxc+0x5d28>\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tadd\tr2, pc\n+\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tadds\tr2, #4\n+\tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n+ R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n+\tldr.w\tr0, [r7, #632]\t@ 0x278\n+\tmovs\tr2, #72\t@ 0x48\n+\tmovs\tr1, #0\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tcmp\tr3, #0\n+\tble.w\t6b94 <__gridxc_cell_MOD_cellxc+0x6580>\n+\tldr.w\tr3, [pc, #1912]\t@ 6340 <__gridxc_cell_MOD_cellxc+0x5d2c>\n+\tadd\tr3, pc\n+\tstr.w\tr3, [r7, #524]\t@ 0x20c\n+\tmov\tr2, r3\n+\tmovs\tr3, #0\n+\tadd.w\tr2, r2, #1488\t@ 0x5d0\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr2, [r7, #636]\t@ 0x27c\n+\tcmp\tr2, #0\n+\tble.w\t62f6 <__gridxc_cell_MOD_cellxc+0x5ce2>\n+\tmovs\tr2, #0\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tcmp.w\tsl, #0\n+\tble.w\t622e <__gridxc_cell_MOD_cellxc+0x5c1a>\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr.w\tr3, [pc, #1860]\t@ 6344 <__gridxc_cell_MOD_cellxc+0x5d30>\n+\tldr.w\tr4, [r7, #784]\t@ 0x310\n+\tadd\tr3, pc\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr8, [r7, #728]\t@ 0x2d8\n+\tadd.w\tr3, r7, #804\t@ 0x324\n+\tldr.w\tr6, [r7, #632]\t@ 0x278\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tadd.w\tr3, r7, #808\t@ 0x328\n+\tstr.w\tsl, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr3, r7, #812\t@ 0x32c\n+\tstr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tldr.w\tr0, [r7, #528]\t@ 0x210\n+\tvldr\td10, [r8, #32]\n+\tldr.w\tsl, [r3, #552]\t@ 0x228\n+\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tvldr\td4, [r8, #8]\n+\tldr.w\tip, [sl]\n+\tldr\tr2, [r3, #0]\n+\tvldr\td9, [r8, #24]\n+\tadd.w\tr9, r2, r1\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tldr\tr1, [r3, #8]\n+\tadd.w\tlr, ip, ip, lsr #31\n+\tldr\tr3, [r3, #16]\n+\tstr.w\tr9, [r2]\n+\tcmp.w\tr9, lr, asr #1\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tit\tgt\n+\tsubgt.w\tr9, r9, ip\n+\tldr.w\tip, [sl, #4]\n \tadd\tr1, r2\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tcmp\tr5, r4\n+\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tvldr\td5, [r8]\n+\tadd.w\tlr, ip, ip, lsr #31\n+\tvldr\td0, [r8, #56]\t@ 0x38\n+\tstr\tr1, [r2, #0]\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tvldr\td3, [r8, #40]\t@ 0x28\n \tadd\tr3, r2\n-\tadd.w\tr2, r4, #1\n-\tbeq.w\t761e <__gridxc_cell_MOD_cellxc+0x7042>\n-\tmov\tr4, r2\n-\tb.n\t6d34 <__gridxc_cell_MOD_cellxc+0x6758>\n-\tadd.w\tr5, r4, #108\t@ 0x6c\n-\tmov\tr2, r0\n-\tmov\tr1, r4\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tstr\tr3, [r2, #0]\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tadd\tr2, r0\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tit\tgt\n+\tldrgt.w\tr2, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr0, [sl, #8]\n+\tit\tgt\n+\tstrgt.w\tr9, [r2]\n+\tcmp.w\tr1, lr, asr #1\n+\tit\tgt\n+\tsubgt.w\tr1, r1, ip\n+\tvmov\ts15, r1\n+\tadd.w\tip, r0, r0, lsr #31\n+\tit\tgt\n+\tldrgt.w\tr2, [r7, #680]\t@ 0x2a8\n+\tvcvt.f64.s32\td8, s15\n+\tvmov\ts15, r9\n+\tit\tgt\n+\tstrgt\tr1, [r2, #0]\n+\tvcvt.f64.s32\td1, s15\n+\tcmp.w\tr3, ip, asr #1\n+\tvmul.f64\td10, d8, d10\n+\tit\tgt\n+\tsubgt\tr3, r3, r0\n+\tvmov\ts15, r3\n+\tvmul.f64\td9, d8, d9\n+\tvmul.f64\td8, d8, d3\n+\tit\tgt\n+\tldrgt.w\tr2, [r7, #672]\t@ 0x2a0\n+\tvcvt.f64.s32\td2, s15\n+\tvmla.f64\td10, d1, d4\n+\tvmla.f64\td9, d1, d5\n+\tit\tgt\n+\tstrgt\tr3, [r2, #0]\n+\tvldr\td7, [r8, #48]\t@ 0x30\n+\tvldr\td6, [r8, #16]\n+\tvmla.f64\td10, d2, d0\n+\tvldr\td5, [r8, #64]\t@ 0x40\n+\tvmla.f64\td9, d2, d7\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tvmla.f64\td8, d1, d6\n+\tvldr\td4, [r3]\n+\tvmla.f64\td8, d2, d5\n+\tvmul.f64\td7, d10, d10\n+\tvmla.f64\td7, d9, d9\n+\tvmla.f64\td7, d8, d8\n+\tvsqrt.f64\td6, d7\n+\tvcmpe.f64\td6, d4\n+\tvstr\td6, [r3, #-8]\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.n\t5db8 <__gridxc_cell_MOD_cellxc+0x57a4>\n+\tldr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tcmp\tr4, #0\n+\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r1, #1888]\t@ 0x760\n+\tldr.w\tr2, [r1, #1908]\t@ 0x774\n+\tmla\tr2, r2, r0, r3\n+\tldr.w\tr3, [r1, #1884]\t@ 0x75c\n+\tldr.w\tr0, [r1, #1920]\t@ 0x780\n+\tble.n\t5da0 <__gridxc_cell_MOD_cellxc+0x578c>\n+\tldr.w\tr1, [r1, #1904]\t@ 0x770\n+\tadd\tr2, r0\n+\tmov.w\tsl, #0\n+\tmov.w\tfp, #0\n+\tmla\tr3, r1, r2, r3\n+\tmovs\tr2, #0\n+\tmul.w\tr1, r0, r1\n+\tadds\tr2, #1\n+\tstrd\tsl, fp, [r3]\n+\tcmp\tr4, r2\n+\tadd\tr3, r1\n+\tbne.n\t5d94 <__gridxc_cell_MOD_cellxc+0x5780>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [r7, #736]\t@ 0x2e0\n+\tadds\tr3, r2, #1\n+\tcmp\tr1, r2\n+\tbeq.w\t6220 <__gridxc_cell_MOD_cellxc+0x5c0c>\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tb.n\t5c3e <__gridxc_cell_MOD_cellxc+0x562a>\n+\tldr.w\tr3, [r7, #524]\t@ 0x20c\n+\tadd.w\tr0, r7, #944\t@ 0x3b0\n+\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tadd.w\tr1, r3, #1536\t@ 0x600\n+\tbl\t0 <__gridxc_vdwxc_MOD_vdw_phi>\n+ R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_phi\n+\tldr.w\tr3, [r7, #524]\t@ 0x20c\n+\tcmp\tr4, #0\n+\tstr.w\tsp, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r3, #1584]\t@ 0x630\n+\tldr.w\tsl, [r3, #1764]\t@ 0x6e4\n+\tldr.w\tr1, [r3, #1768]\t@ 0x6e8\n+\tldr.w\tfp, [r3, #1588]\t@ 0x634\n+\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tble.n\t5e94 <__gridxc_cell_MOD_cellxc+0x5880>\n+\tlsls\tr3, r4, #3\n+\tmov\tr0, sp\n+\tbic.w\tr2, r3, #4080\t@ 0xff0\n+\tbic.w\tr2, r2, #15\n+\tsub.w\tr2, sp, r2\n+\tcmp\tr0, r2\n+\tbeq.n\t5e0e <__gridxc_cell_MOD_cellxc+0x57fa>\n+\tsub.w\tsp, sp, #4096\t@ 0x1000\n+\tmov\tr0, sp\n+\tcmp\tr0, r2\n+\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n+\tbne.n\t5e00 <__gridxc_cell_MOD_cellxc+0x57ec>\n+\tubfx\tr3, r3, #0, #12\n+\tsub.w\tsp, sp, r3\n+\tcbz\tr3, 5e1e <__gridxc_cell_MOD_cellxc+0x580a>\n+\tsubs\tr3, #4\n+\tadd\tr3, sp\n+\tstr\tr0, [r3, #0]\n+\tldr.w\tr2, [pc, #1320]\t@ 6348 <__gridxc_cell_MOD_cellxc+0x5d34>\n+\tadd\tr0, sp, #48\t@ 0x30\n+\tmov\tr9, r0\n+\tmov.w\tip, #0\n+\tadd\tr2, pc\n+\tmov\tlr, r2\n+\tldr.w\tr3, [r2, #1788]\t@ 0x6fc\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tmla\tr3, r3, r2, r1\n+\tmov\tr2, lr\n+\tldr.w\tlr, [lr, #1800]\t@ 0x708\n+\tldr.w\tr1, [r2, #1784]\t@ 0x6f8\n+\tadd\tr3, lr\n+\tldr.w\tr2, [r2, #1608]\t@ 0x648\n+\tmla\tr3, r1, r3, sl\n+\tmul.w\tr1, r1, lr\n+\tvldr\td7, [r3]\n+\tmov\tlr, ip\n+\tadd.w\tip, ip, #1\n+\tadd\tr3, r1\n+\tcmp\tr4, ip\n+\tvstmia\tr9!, {d7}\n+\tbne.n\t5e52 <__gridxc_cell_MOD_cellxc+0x583e>\n+\tldr.w\tr1, [pc, #1252]\t@ 634c <__gridxc_cell_MOD_cellxc+0x5d38>\n+\tadd.w\tr3, r2, fp\n+\tldr.w\tr4, [r7, #732]\t@ 0x2dc\n+\tadd\tr1, pc\n+\tldr.w\tr1, [r1, #1604]\t@ 0x644\n+\tmla\tr3, r1, r3, r4\n+\tmul.w\tr2, r1, r2\n+\tmovs\tr1, #0\n+\tldrd\tsl, fp, [r0], #8\n+\tcmp\tlr, r1\n+\tstrd\tsl, fp, [r3]\n+\tadd.w\tr1, r1, #1\n+\tadd\tr3, r2\n+\tbne.n\t5e82 <__gridxc_cell_MOD_cellxc+0x586e>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tr9, r7, #1072\t@ 0x430\n+\tldr.w\tfp, [pc, #1200]\t@ 6350 <__gridxc_cell_MOD_cellxc+0x5d3c>\n+\tmov.w\tsl, #0\n+\tldr.w\tsp, [r7, #784]\t@ 0x310\n+\tadd.w\tr2, r7, #1224\t@ 0x4c8\n+\tldr\tr4, [r3, #0]\n+\tadd\tfp, pc\n+\taddw\tr3, r7, #1084\t@ 0x43c\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tmovs\tr3, #1\n+\tstr.w\tr3, [r7, #1252]\t@ 0x4e4\n+\tstr.w\tr3, [r7, #1248]\t@ 0x4e0\n+\tmvns\tr1, r4\n+\tmul.w\tr0, r4, r4\n+\tstr.w\tr3, [r7, #1264]\t@ 0x4f0\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r9, #8]\n+\tstr.w\tr3, [r7, #1244]\t@ 0x4dc\n+\tmovw\tip, #769\t@ 0x301\n+\tlsls\tr0, r0, #3\n+\tldr.w\tr3, [fp, #1536]\t@ 0x600\n+\tcmp\tr0, #1\n+\tstr.w\tr1, [r7, #1228]\t@ 0x4cc\n+\tit\tcc\n+\tmovcc\tr0, #1\n+\tldr.w\tr1, [fp, #1560]\t@ 0x618\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [fp, #1540]\t@ 0x604\n+\tstr.w\tsl, [r7, #1088]\t@ 0x440\n+\tstr.w\tsl, [r7, #1084]\t@ 0x43c\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tstr.w\tr1, [r7, #784]\t@ 0x310\n+\tstr.w\tr4, [r7, #1256]\t@ 0x4e8\n+\tstr.w\tr4, [r7, #1268]\t@ 0x4f4\n+\tstr.w\tr4, [r7, #1260]\t@ 0x4ec\n+\tstr.w\tsl, [r9]\n+\tstrh.w\tip, [r9, #16]\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmalloc\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tmovs\tr3, #8\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tcmp\tr4, sl\n+\tstr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tstr\tr0, [r2, #0]\n+\tstr.w\tsl, [r7, #1236]\t@ 0x4d4\n+\tstr.w\tsl, [r7, #1240]\t@ 0x4d8\n+\tstr\tr3, [r2, #8]\n+\tmovw\tr3, #770\t@ 0x302\n+\tstrh\tr3, [r2, #16]\n+\tble.n\t5fb6 <__gridxc_cell_MOD_cellxc+0x59a2>\n+\tldr.w\tr3, [fp, #1572]\t@ 0x624\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tldr.w\tlr, [fp, #1556]\t@ 0x614\n+\tadd\tr0, r3\n+\tstr.w\tsl, [r7, #784]\t@ 0x310\n+\tmov\tip, r0\n+\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tadd\tip, r1\n+\tmul.w\tr3, lr, r3\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tmla\tfp, lr, ip, r0\n+\tmul.w\tlr, r1, lr\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tadds\tr3, #8\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tmov\tr0, fp\n+\tadd.w\tip, r3, r1, lsl #3\n+\tmovs\tr3, #0\n+\tvldr\td7, [r0]\n+\tmov\tsl, r3\n+\tadds\tr3, #1\n+\tadd\tr0, lr\n+\tcmp\tr4, r3\n+\tvstmia\tip!, {d7}\n+\tbne.n\t5f8a <__gridxc_cell_MOD_cellxc+0x5976>\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd\tr1, r4\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tadd\tfp, r3\n+\tcmp\tr0, sl\n+\tadd.w\tr3, r0, #1\n+\tbeq.n\t5fb6 <__gridxc_cell_MOD_cellxc+0x59a2>\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tb.n\t5f7e <__gridxc_cell_MOD_cellxc+0x596a>\n+\tldr.w\tfp, [pc, #924]\t@ 6354 <__gridxc_cell_MOD_cellxc+0x5d40>\n+\tlsls\tr3, r4, #3\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tmov\tr2, r3\n+\tadd\tfp, pc\n+\tcmp\tr2, #1\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n+\tmov.w\tr3, #1\n+\tstrd\tr3, r3, [r9, #24]\n+\tmov\tr3, r2\n+\tit\tcc\n+\tmovcc\tr3, #1\n+\tstr.w\tr4, [r9, #32]\n+\tmov\tr0, r3\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr3, [r9, #4]\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r9, #20]\n+\tldr.w\tr3, [fp, #1584]\t@ 0x630\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [fp, #1588]\t@ 0x634\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [fp, #1608]\t@ 0x648\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmalloc\n+\tbic.w\tlr, r4, r4, asr #31\n+\tvmov\ts15, lr\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tmovs\tr2, #0\n+\tvcvt.f32.s32\ts15, s15\n+\tcmp\tr4, r2\n+\tmovw\tip, #769\t@ 0x301\n+\tmov\tsl, r0\n+\tstrd\tr2, r2, [r3]\n+\tstr.w\tr0, [r9]\n+\tvmul.f32\ts15, s15, s15\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tstrh.w\tip, [r9, #16]\n+\tble.w\t66fc <__gridxc_cell_MOD_cellxc+0x60e8>\n+\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tvmov.f32\ts13, s15\n+\tldr.w\tip, [fp, #1604]\t@ 0x644\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tadd\tr3, r0\n+\tmla\tr3, ip, r3, r1\n+\tmovs\tr1, #0\n+\tmul.w\tip, r0, ip\n+\tmov\tr0, sl\n+\tvldr\td7, [r3]\n+\tadd\tr3, ip\n+\tstr.w\tr1, [r7, #600]\t@ 0x258\n+\tadds\tr1, #1\n+\tcmp\tr4, r1\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t605c <__gridxc_cell_MOD_cellxc+0x5a48>\n+\tvldr\ts14, [pc, #684]\t@ 6320 <__gridxc_cell_MOD_cellxc+0x5d0c>\n+\tldr\tr3, [pc, #736]\t@ (6358 <__gridxc_cell_MOD_cellxc+0x5d44>)\n+\tvcmpe.f32\ts13, s14\n+\tadd\tr3, pc\n+\tldr.w\tr0, [r3, #1728]\t@ 0x6c0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tldr.w\tip, [r3, #1752]\t@ 0x6d8\n+\tstr.w\tr0, [r7, #784]\t@ 0x310\n+\tbls.w\t6242 <__gridxc_cell_MOD_cellxc+0x5c2e>\n+\tldr.w\tfp, [pc, #712]\t@ 635c <__gridxc_cell_MOD_cellxc+0x5d48>\n+\tmovs\tr3, #0\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tmovs\tr0, #8\n+\tadd\tfp, pc\n+\tstr\tr4, [r5, #32]\n+\tstrd\tr3, r3, [r1]\n+\tmov\tr1, r9\n+\tstr\tr0, [r5, #8]\n+\tmovs\tr0, #1\n+\tstr\tr0, [r5, #28]\n+\tldr.w\tr0, [fp, #1756]\t@ 0x6dc\n+\trsb\tip, r0, #1\n+\tldr.w\tr0, [fp, #1752]\t@ 0x6d8\n+\tstr\tr0, [r5, #24]\n+\tmul.w\tip, r0, ip\n+\tnegs\tr0, r0\n+\tstr\tr0, [r5, #4]\n+\tldr.w\tr0, [fp, #1728]\t@ 0x6c0\n+\tadd.w\tr0, r0, ip, lsl #3\n+\tstr\tr0, [r5, #0]\n+\tldr.w\tr0, [fp, #1748]\t@ 0x6d4\n+\tstr\tr0, [r5, #20]\n+\tmovw\tr0, #769\t@ 0x301\n+\tstrh\tr0, [r5, #16]\n \tmov\tr0, r5\n-\tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n- R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n-\tldr\tr2, [r7, #88]\t@ 0x58\n-\tvmov.i32\td10, #0\t@ 0x00000000\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n-\tmov.w\tfp, #8\n-\tstr\tr2, [r3, #4]\n-\tmov.w\tsl, #1\n-\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n-\tmov\tr1, r4\n-\tstr\tr6, [r3, #28]\n-\tstr\tr6, [r3, #40]\t@ 0x28\n-\tldr.w\tr8, [r2, #552]\t@ 0x228\n-\tldr.w\tr2, [r7, #568]\t@ 0x238\n-\tstr\tr2, [r3, #32]\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tstr\tr2, [r3, #44]\t@ 0x2c\n-\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n-\tstr\tr2, [r3, #36]\t@ 0x24\n+\tstrd\tr3, r3, [sp]\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tbl\t0 <_gfortran_matmul_r8>\n+ R_ARM_THM_CALL\t_gfortran_matmul_r8\n+\tldr.w\tr3, [fp, #1728]\t@ 0x6c0\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [fp, #1732]\t@ 0x6c4\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tcbz\tr3, 6112 <__gridxc_cell_MOD_cellxc+0x5afe>\n+\tmov\tr0, r3\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tmovs\tr3, #0\n+\tstr\tr3, [r2, #0]\n+\tcmp.w\tsl, #0\n+\tbeq.n\t6124 <__gridxc_cell_MOD_cellxc+0x5b10>\n+\tmov\tr0, sl\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r9]\n+\tldr\tr3, [pc, #568]\t@ (6360 <__gridxc_cell_MOD_cellxc+0x5d4c>)\n+\tcmp\tr4, #0\n+\tstr.w\tsp, [r7, #696]\t@ 0x2b8\n+\tadd\tr3, pc\n+\tldr.w\tfp, [r3, #1884]\t@ 0x75c\n+\tldr.w\tsl, [r3, #1888]\t@ 0x760\n+\tble.n\t61ee <__gridxc_cell_MOD_cellxc+0x5bda>\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tmov\tr1, sp\n+\tbic.w\tr2, r3, #4080\t@ 0xff0\n+\tbic.w\tr2, r2, #15\n+\tsub.w\tr2, sp, r2\n+\tcmp\tr1, r2\n+\tbeq.n\t615c <__gridxc_cell_MOD_cellxc+0x5b48>\n+\tsub.w\tsp, sp, #4096\t@ 0x1000\n+\tmov\tr1, sp\n+\tcmp\tr1, r2\n+\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n+\tbne.n\t614e <__gridxc_cell_MOD_cellxc+0x5b3a>\n+\tubfx\tr3, r3, #0, #12\n+\tsub.w\tsp, sp, r3\n+\tcbz\tr3, 616c <__gridxc_cell_MOD_cellxc+0x5b58>\n+\tsubs\tr3, #4\n+\tadd\tr3, sp\n+\tstr\tr0, [r3, #0]\n+\tldr\tr2, [pc, #500]\t@ (6364 <__gridxc_cell_MOD_cellxc+0x5d50>)\n+\tadd\tr1, sp, #48\t@ 0x30\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tmov\tr9, r1\n+\tadd\tr2, pc\n+\tmov.w\tip, #0\n+\tldr.w\tr0, [r2, #1752]\t@ 0x6d8\n+\tldr.w\tlr, [r2, #1748]\t@ 0x6d4\n+\tadd\tr3, r0\n+\tstr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tmla\tr3, lr, r3, r0\n+\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tmul.w\tlr, lr, r0\n+\tldr.w\tr0, [r2, #1908]\t@ 0x774\n+\tldr.w\tr2, [r2, #1920]\t@ 0x780\n+\tmla\tsl, r0, r3, sl\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tvldr\td7, [r3]\n+\tmov\tr0, ip\n+\tadd.w\tip, ip, #1\n+\tadd\tr3, lr\n+\tcmp\tr4, ip\n+\tvstmia\tr9!, {d7}\n+\tbne.n\t61b2 <__gridxc_cell_MOD_cellxc+0x5b9e>\n+\tldr\tr4, [pc, #416]\t@ (6368 <__gridxc_cell_MOD_cellxc+0x5d54>)\n+\tadd.w\tr3, sl, r2\n+\tadd\tr4, pc\n+\tldr.w\tr4, [r4, #1904]\t@ 0x770\n+\tmla\tr3, r4, r3, fp\n+\tmul.w\tr2, r4, r2\n+\tmovs\tr4, #0\n+\tldrd\tsl, fp, [r1], #8\n+\tcmp\tr0, r4\n+\tstrd\tsl, fp, [r3]\n+\tadd.w\tr4, r4, #1\n+\tadd\tr3, r2\n+\tbne.n\t61dc <__gridxc_cell_MOD_cellxc+0x5bc8>\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tvldr\td7, [pc, #284]\t@ 6310 <__gridxc_cell_MOD_cellxc+0x5cfc>\n+\tldr.w\tsp, [r7, #696]\t@ 0x2b8\n+\tvldr\td12, [r3, #-8]\n+\tvcmpe.f64\td12, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbgt.w\t636c <__gridxc_cell_MOD_cellxc+0x5d58>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [r7, #736]\t@ 0x2e0\n+\tldr\tr4, [r3, #0]\n+\tadds\tr3, r2, #1\n+\tcmp\tr1, r2\n+\tbne.w\t5db0 <__gridxc_cell_MOD_cellxc+0x579c>\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr.w\tsl, [r7, #440]\t@ 0x1b8\n+\tadd\tr3, r1\n+\tstr.w\tr4, [r7, #784]\t@ 0x310\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tldr.w\tr0, [r7, #644]\t@ 0x284\n+\tadds\tr2, r1, #1\n+\tcmp\tr0, r1\n+\tbeq.n\t62f6 <__gridxc_cell_MOD_cellxc+0x5ce2>\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tb.n\t5bf0 <__gridxc_cell_MOD_cellxc+0x55dc>\n+\tldr.w\tr0, [r3, #1732]\t@ 0x6c4\n+\tldr.w\tr3, [r3, #1748]\t@ 0x6d4\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd.w\tfp, r0, ip\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr0, [r7, #656]\t@ 0x290\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tvldr\td7, [pc, #184]\t@ 6318 <__gridxc_cell_MOD_cellxc+0x5d04>\n+\tmul.w\tip, ip, r3\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tstr.w\tip, [r7, #552]\t@ 0x228\n+\tmla\tfp, r3, fp, r0\n+\tmovs\tr0, #0\n+\tmov\tr3, fp\n \tldr.w\tr2, [r7, #552]\t@ 0x228\n-\tvldr\td8, [pc, #788]\t@ 7100 <__gridxc_cell_MOD_cellxc+0x6b24>\n-\tldr.w\tr9, [pc, #804]\t@ 7114 <__gridxc_cell_MOD_cellxc+0x6b38>\n-\tvstr\td10, [r2]\n-\tmov\tr2, r3\n-\tstr\tr0, [r3, #56]\t@ 0x38\n+\tvstr\td7, [r3]\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tcmp\tr2, r0\n+\tadd.w\tr0, r0, #1\n+\tbne.n\t6276 <__gridxc_cell_MOD_cellxc+0x5c62>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tadds\tr3, #8\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr0, [r7, #600]\t@ 0x258\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tvldr\td7, [fp]\n+\tadd.w\tip, r3, r0, lsl #3\n+\tmov\tr0, sl\n+\tmovs\tr3, #0\n+\tvldmia\tr0!, {d5}\n+\tadds\tr3, #1\n+\tvldmia\tip!, {d6}\n+\tcmp\tr3, lr\n+\tvmla.f64\td7, d5, d6\n+\tblt.n\t62c6 <__gridxc_cell_MOD_cellxc+0x5cb2>\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tvstr\td7, [fp]\n+\tadd\tr3, r1\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tadd\tfp, r3\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tcmp\tr3, lr\n+\tblt.n\t62a8 <__gridxc_cell_MOD_cellxc+0x5c94>\n+\tb.n\t60fa <__gridxc_cell_MOD_cellxc+0x5ae6>\n+\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tldr.w\tr0, [r7, #624]\t@ 0x270\n+\tadds\tr2, r1, #1\n+\tcmp\tr1, r0\n+\tbge.w\t671e <__gridxc_cell_MOD_cellxc+0x610a>\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n+\tb.n\t5be0 <__gridxc_cell_MOD_cellxc+0x55cc>\n+\tnop.w\n+\t.word\t0x9ee75616\n+\t.word\t0x3cd203af\n+\t...\n+\t.word\t0x44610000\n+\t.word\t0x00000d36\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000d04\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000bf2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000b0c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000932\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000008f8\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000794\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000772\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000073a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000051a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004d6\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000049e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000038e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002da\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002bc\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000230\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001ea\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000198\n+ R_ARM_REL32\t.bss\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tmov.w\tsl, #8\n+\tldr.w\tr9, [pc, #1316]\t@ 689c <__gridxc_cell_MOD_cellxc+0x6288>\n+\tmovs\tr1, #1\n+\tstr.w\tsl, [r5, #20]\n+\tmov.w\tfp, #0\n+\tldr\tr4, [r3, #0]\n \tadd\tr9, pc\n-\tldr.w\tr0, [r7, #700]\t@ 0x2bc\n-\tstr\tr0, [r3, #48]\t@ 0x30\n-\tldr.w\tr0, [r7, #764]\t@ 0x2fc\n-\tstr\tr0, [r3, #68]\t@ 0x44\n-\tldr.w\tr0, [r7, #512]\t@ 0x200\n-\tstr\tr0, [r3, #60]\t@ 0x3c\n+\tadd.w\tr3, r7, #1120\t@ 0x460\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tstrd\tr1, r1, [r5, #24]\n+\taddw\tr2, r7, #1108\t@ 0x454\n+\tldr.w\tr3, [r9, #1488]\t@ 0x5d0\n+\tmul.w\tr0, r4, r4\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r9, #1492]\t@ 0x5d4\n+\tstr\tr1, [r5, #40]\t@ 0x28\n+\tmvns\tr1, r4\n+\tlsls\tr0, r0, #3\n+\tstr\tr1, [r5, #4]\n+\tcmp\tr0, #1\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tit\tcc\n+\tmovcc\tr0, #1\n+\tldr.w\tr3, [r9, #1512]\t@ 0x5e8\n+\tstr\tr4, [r5, #32]\n+\tmovw\tr1, #769\t@ 0x301\n+\tstr\tr4, [r5, #44]\t@ 0x2c\n+\tstr\tr4, [r5, #36]\t@ 0x24\n+\tstr.w\tfp, [r7, #1124]\t@ 0x464\n+\tstr.w\tsl, [r7, #1116]\t@ 0x45c\n+\tstrh.w\tr1, [r7, #1124]\t@ 0x464\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tfp, [r7, #1108]\t@ 0x454\n+\tstr.w\tfp, [r7, #1120]\t@ 0x460\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmalloc\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tmovw\tr1, #770\t@ 0x302\n+\tstr.w\tsl, [r5, #8]\n+\tcmp\tr4, fp\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tmov\tsl, r0\n+\tstr.w\tfp, [r3, #4]\n+\tstr.w\tfp, [r3]\n+\tstr\tr0, [r5, #0]\n+\tstrh\tr1, [r5, #16]\n+\tble.n\t648c <__gridxc_cell_MOD_cellxc+0x5e78>\n+\tldr.w\tip, [r9, #1524]\t@ 0x5f4\n \tldr.w\tr0, [r7, #696]\t@ 0x2b8\n-\tstr\tr0, [r3, #0]\n-\tldr.w\tr0, [r7, #548]\t@ 0x224\n-\tstr\tr6, [r3, #52]\t@ 0x34\n-\tvst1.32\t{d8}, [r0]\n-\tmov\tr0, r8\n-\tstr.w\tfp, [r3, #8]\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tadd\tr0, ip\n+\tldr.w\tr3, [r9, #1508]\t@ 0x5e4\n+\tadd\tr0, r1\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tmul.w\tip, r3, ip\n+\tmla\tr0, r3, r0, r1\n+\tldr.w\tr1, [r7, #784]\t@ 0x310\n+\tstr.w\tip, [r7, #732]\t@ 0x2dc\n+\tmul.w\tr3, r1, r3\n+\tadd.w\tr1, sl, #8\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr1, [r7, #600]\t@ 0x258\n+\tldr.w\tr1, [r7, #600]\t@ 0x258\n+\tmov\tlr, r0\n+\tmov.w\tip, #0\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd.w\tr9, r1, r3, lsl #3\n+\tmov\tr1, fp\n+\tvldr\td7, [lr]\n+\tmov\tfp, ip\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd.w\tip, ip, #1\n+\tcmp\tr4, ip\n+\tadd\tlr, r3\n+\tvstmia\tr9!, {d7}\n+\tbne.n\t6458 <__gridxc_cell_MOD_cellxc+0x5e44>\n+\tmov\tip, r1\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd\tr0, r1\n+\tmov\tr1, ip\n+\tadd\tr3, r4\n+\tadd.w\tip, ip, #1\n+\tcmp\tr1, fp\n+\tbeq.n\t648c <__gridxc_cell_MOD_cellxc+0x5e78>\n+\tmov\tfp, ip\n+\tb.n\t6444 <__gridxc_cell_MOD_cellxc+0x5e30>\n+\tldr.w\tr1, [pc, #1040]\t@ 68a0 <__gridxc_cell_MOD_cellxc+0x628c>\n+\tlsls\tr0, r4, #3\n+\tcmp\tr0, #1\n+\tmov.w\tr3, #1\n+\tadd\tr1, pc\n+\tstrd\tr3, r3, [r2, #24]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr\tr3, [r2, #4]\n+\tmov.w\tr3, #8\n+\tstr\tr3, [r2, #20]\n+\tldr.w\tr3, [r1, #1584]\t@ 0x630\n+\tit\tcc\n+\tmovcc\tr0, #1\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r1, #1588]\t@ 0x634\n+\tldr.w\tr9, [r1, #1608]\t@ 0x648\n+\tstr\tr4, [r2, #32]\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmalloc\n+\tbic.w\tr3, r4, r4, asr #31\n+\tvmov\ts15, r3\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tmov.w\tip, #0\n+\tvcvt.f32.s32\ts15, s15\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tmov\tfp, r0\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tcmp\tr4, ip\n+\tstr\tr0, [r2, #0]\n+\tstrd\tip, ip, [r3]\n+\tvmul.f32\ts15, s15, s15\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh\tr3, [r2, #16]\n+\tble.w\t6ad0 <__gridxc_cell_MOD_cellxc+0x64bc>\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tmov\tlr, ip\n+\tldr.w\tr0, [r1, #1604]\t@ 0x644\n+\tvmov.f32\ts13, s15\n+\tadd.w\tr1, r3, r9\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov\tip, fp\n+\tmla\tr1, r0, r1, r3\n+\tmov\tr3, lr\n+\tmul.w\tr0, r9, r0\n+\tvldr\td7, [r1]\n+\tadd\tr1, r0\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tadds\tr3, #1\n+\tcmp\tr4, r3\n+\tvstmia\tip!, {d7}\n+\tbne.n\t652a <__gridxc_cell_MOD_cellxc+0x5f16>\n+\tvldr\ts14, [pc, #856]\t@ 6898 <__gridxc_cell_MOD_cellxc+0x6284>\n+\tldr\tr0, [pc, #864]\t@ (68a4 <__gridxc_cell_MOD_cellxc+0x6290>)\n+\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tvcmpe.f32\ts13, s14\n+\tadd\tr0, pc\n+\tldr.w\tr1, [r0, #1344]\t@ 0x540\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tmov\tr3, r1\n+\tldr.w\tr1, [r0, #1368]\t@ 0x558\n+\tstr.w\tr1, [r7, #656]\t@ 0x290\n+\tbls.w\t6afa <__gridxc_cell_MOD_cellxc+0x64e6>\n+\tldr.w\tr9, [pc, #828]\t@ 68a8 <__gridxc_cell_MOD_cellxc+0x6294>\n+\tmov\tr1, r2\n+\tadd.w\tr0, r7, #1144\t@ 0x478\n+\tstr\tr4, [r0, #32]\n+\tadd\tr9, pc\n+\tldr.w\tr3, [r9, #1372]\t@ 0x55c\n+\tldr.w\tr2, [r9, #1368]\t@ 0x558\n+\trsb\tr3, r3, #1\n+\tstr\tr2, [r0, #24]\n+\tmul.w\tr3, r2, r3\n+\tnegs\tr2, r2\n+\tstr\tr2, [r0, #4]\n+\tldr.w\tr2, [r9, #1344]\t@ 0x540\n+\tadd.w\tr2, r2, r3, lsl #3\n+\tstr\tr2, [r0, #0]\n+\tldr.w\tr2, [r9, #1364]\t@ 0x554\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #1160]\t@ 0x488\n+\tstr.w\tr3, [r7, #1156]\t@ 0x484\n+\tstr\tr2, [r0, #20]\n+\tmovs\tr2, #8\n+\tstr\tr2, [r0, #8]\n+\tmovs\tr2, #1\n+\tstr\tr2, [r0, #28]\n+\tmovw\tr2, #769\t@ 0x301\n+\tstrh\tr2, [r0, #16]\n+\tmov\tr2, r5\n+\tstrd\tr3, r3, [sp]\n+\tbl\t0 <_gfortran_matmul_r8>\n+ R_ARM_THM_CALL\t_gfortran_matmul_r8\n+\tldr.w\tr3, [r9, #1344]\t@ 0x540\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r9, #1348]\t@ 0x544\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r9, #1584]\t@ 0x630\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r9, #1588]\t@ 0x634\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r9, #1368]\t@ 0x558\n+\tldr.w\tr9, [r9, #1608]\t@ 0x648\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tcmp.w\tsl, #0\n+\tbeq.n\t65f6 <__gridxc_cell_MOD_cellxc+0x5fe2>\n+\tmov\tr0, sl\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tcmp.w\tfp, #0\n+\tbeq.n\t6602 <__gridxc_cell_MOD_cellxc+0x5fee>\n+\tmov\tr0, fp\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tvdiv.f64\td6, d15, d12\n+\tldr\tr2, [pc, #676]\t@ (68ac <__gridxc_cell_MOD_cellxc+0x6298>)\n+\tadd\tr2, pc\n+\tldr.w\tsl, [r2, #1372]\t@ 0x55c\n+\tldr.w\tr0, [r2, #1376]\t@ 0x560\n+\tldr.w\tr3, [r2, #1612]\t@ 0x64c\n+\tcmp\tsl, r0\n+\tbgt.w\t6b8e <__gridxc_cell_MOD_cellxc+0x657a>\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tadds\tr0, #1\n+\tvldr\td7, [pc, #620]\t@ 6890 <__gridxc_cell_MOD_cellxc+0x627c>\n+\tmla\tfp, r9, r3, r1\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tmla\tlr, r1, sl, r3\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tsub.w\tsl, r0, sl\n+\tldr.w\tr0, [r2, #1364]\t@ 0x554\n+\tldr.w\tr2, [r2, #1604]\t@ 0x644\n+\tmla\tip, r0, lr, r3\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmul.w\tr0, r1, r0\n+\tmovs\tr1, #0\n+\tmla\tr3, r2, fp, r3\n+\tmul.w\tr2, r9, r2\n+\tvldr\td4, [ip]\n+\tadds\tr1, #1\n+\tvldr\td5, [r3]\n+\tadd\tip, r0\n+\tadd\tr3, r2\n+\tcmp\tsl, r1\n+\tvmla.f64\td7, d4, d5\n+\tbne.n\t665c <__gridxc_cell_MOD_cellxc+0x6048>\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td4, d9, d7\n+\tvldr\td5, [r6]\n+\tvmul.f64\td6, d10, d7\n+\tvmul.f64\td7, d8, d7\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tmovs\tr3, #4\n+\tvmls.f64\td5, d9, d4\n+\tstr.w\tr3, [r2, #548]\t@ 0x224\n+\tvstr\td5, [r6]\n+\tvldr\td5, [r6, #8]\n+\tvmls.f64\td5, d10, d4\n+\tvstr\td5, [r6, #8]\n+\tvldr\td5, [r6, #16]\n+\tvmls.f64\td5, d8, d4\n+\tvldr\td4, [r6, #48]\t@ 0x30\n+\tvmls.f64\td4, d9, d7\n+\tvstr\td5, [r6, #16]\n+\tvldr\td5, [r6, #24]\n+\tvmls.f64\td5, d9, d6\n+\tvstr\td4, [r6, #48]\t@ 0x30\n+\tvstr\td5, [r6, #24]\n+\tvldr\td5, [r6, #32]\n+\tvmls.f64\td5, d10, d6\n+\tvstr\td5, [r6, #32]\n+\tvldr\td5, [r6, #40]\t@ 0x28\n+\tvmls.f64\td5, d8, d6\n+\tvldr\td6, [r6, #64]\t@ 0x40\n+\tvmls.f64\td6, d8, d7\n+\tvstr\td5, [r6, #40]\t@ 0x28\n+\tvldr\td5, [r6, #56]\t@ 0x38\n+\tvmls.f64\td5, d10, d7\n+\tvstr\td6, [r6, #64]\t@ 0x40\n+\tvstr\td5, [r6, #56]\t@ 0x38\n+\tb.w\t5da0 <__gridxc_cell_MOD_cellxc+0x578c>\n+\tvldr\ts14, [pc, #408]\t@ 6898 <__gridxc_cell_MOD_cellxc+0x6284>\n+\tvcmpe.f32\ts15, s14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.w\t6090 <__gridxc_cell_MOD_cellxc+0x5a7c>\n+\tldr.w\tr3, [fp, #1728]\t@ 0x6c0\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [fp, #1732]\t@ 0x6c4\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tb.n\t60fa <__gridxc_cell_MOD_cellxc+0x5ae6>\n+\tldr.w\tr3, [r7, #388]\t@ 0x184\n+\tldr\tr3, [r3, #0]\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tcmp\tr3, #0\n+\tble.w\t1d3c <__gridxc_cell_MOD_cellxc+0x1728>\n+\tldr.w\tr3, [r7, #792]\t@ 0x318\n+\tmov.w\tr8, #1\n+\tldr.w\tr3, [r3, #552]\t@ 0x228\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr\tr0, [pc, #364]\t@ (68b0 <__gridxc_cell_MOD_cellxc+0x629c>)\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tadd\tr0, pc\n+\tcmp\tr2, #0\n+\tldr.w\tr3, [r0, #1932]\t@ 0x78c\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r0, #1968]\t@ 0x7b0\n+\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tldr.w\tr3, [r0, #1956]\t@ 0x7a4\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tip, [r0, #1992]\t@ 0x7c8\n+\tldr.w\tr5, [r0, #1980]\t@ 0x7bc\n+\tldr.w\tr3, [r0, #1952]\t@ 0x7a0\n+\tble.w\t68b4 <__gridxc_cell_MOD_cellxc+0x62a0>\n+\tldr.w\tr1, [r0, #1920]\t@ 0x780\n+\tldr.w\tr2, [r0, #1888]\t@ 0x760\n+\tldr.w\tr6, [r0, #1908]\t@ 0x774\n+\tstr.w\tr6, [r7, #656]\t@ 0x290\n+\tmla\tr2, r1, r8, r2\n+\tldr.w\tr1, [r0, #1884]\t@ 0x75c\n+\tstr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr2, [r0, #1936]\t@ 0x790\n+\tldr.w\tr1, [r7, #636]\t@ 0x27c\n+\tldr.w\tr0, [r0, #1904]\t@ 0x770\n+\tadd\tr2, ip\n+\tcmp\tr1, #0\n+\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tble.w\t68b4 <__gridxc_cell_MOD_cellxc+0x62a0>\n+\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tmul.w\tr9, r0, r6\n+\tmla\tr4, r3, r2, r1\n+\tmovs\tr1, #0\n+\tmul.w\tr2, r3, r5\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tmul.w\tr2, r3, r2\n+\tstr.w\tr2, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tmul.w\tr6, r3, r2\n+\tmov\tr2, r1\n+\tmovs\tr0, #0\n+\tmov\tlr, r4\n+\tstr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tmov\tr0, r9\n+\tstr.w\tr8, [r7, #552]\t@ 0x228\n+\tstr.w\tr2, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tcmp.w\tsl, #0\n+\tble.n\t684a <__gridxc_cell_MOD_cellxc+0x6236>\n+\tadd.w\tr8, r1, #1\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tadd.w\tfp, sl, r1\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tmov\tr9, lr\n+\tstr.w\tr8, [r7, #592]\t@ 0x250\n+\tmla\tr1, r8, r1, r3\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tmla\tr1, r2, r1, r3\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tb.n\t6828 <__gridxc_cell_MOD_cellxc+0x6214>\n+\tadd.w\tr8, r8, #1\n+\tvldr\td7, [r1]\n+\tcmp\tr8, fp\n+\tadd\tr1, r0\n+\tvstr\td7, [r9]\n+\tadd\tr9, r6\n+\tbne.n\t6824 <__gridxc_cell_MOD_cellxc+0x6210>\n+\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tstr.w\tr2, [r7, #776]\t@ 0x308\n+\tadd\tr1, r3\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr2, [r7, #644]\t@ 0x284\n+\tadd\tlr, r3\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tadd.w\tr8, r3, #1\n+\tcmp\tr2, r3\n+\tbeq.n\t6866 <__gridxc_cell_MOD_cellxc+0x6252>\n+\tstr.w\tr8, [r7, #732]\t@ 0x2dc\n+\tb.n\t67ee <__gridxc_cell_MOD_cellxc+0x61da>\n+\tmov\tr9, r0\n+\tldr.w\tr0, [r7, #608]\t@ 0x260\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tadd\tr4, r0\n+\tldr.w\tr0, [r7, #624]\t@ 0x270\n+\tldr.w\tr8, [r7, #552]\t@ 0x228\n+\tadd.w\tlr, r2, #1\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tcmp\tr2, r0\n+\tbeq.n\t68b4 <__gridxc_cell_MOD_cellxc+0x62a0>\n+\tmov\tr2, lr\n+\tb.n\t67d8 <__gridxc_cell_MOD_cellxc+0x61c4>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x44610000\n+\t.word\t0x00000514\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000404\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000354\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000330\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002a0\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000164\n+ R_ARM_REL32\t.bss\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tmovs\tr1, #0\n+\tldr.w\tr4, [pc, #1440]\t@ 6e5c <__gridxc_cell_MOD_cellxc+0x6848>\n+\tldr.w\tr6, [r7, #728]\t@ 0x2d8\n+\tstr\tr3, [r2, #20]\n+\tadd\tr4, pc\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tldr.w\tr0, [r7, #584]\t@ 0x248\n+\tstrd\tr1, r1, [r3]\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr1, [r7, #692]\t@ 0x2b4\n+\tstr\tr3, [r2, #24]\n+\tnegs\tr3, r3\n+\tsubs\tr3, r3, r1\n+\tstr\tr5, [r2, #48]\t@ 0x30\n+\tsubs\tr3, r3, r5\n+\tldr.w\tr5, [r4, #1964]\t@ 0x7ac\n+\tsub.w\tr3, r3, ip\n+\tstr\tr3, [r2, #4]\n+\tmovs\tr3, #1\n+\tstr\tr3, [r2, #28]\n+\tstr\tr3, [r2, #40]\t@ 0x28\n+\tstr\tr3, [r2, #52]\t@ 0x34\n+\tstrd\tr3, r3, [r2, #64]\t@ 0x40\n+\tldr.w\tr3, [r4, #1996]\t@ 0x7cc\n+\tstr.w\tip, [r2, #60]\t@ 0x3c\n+\trsb\tr3, r3, #1\n+\tstr\tr1, [r2, #36]\t@ 0x24\n+\tldr.w\tr1, [pc, #1364]\t@ 6e60 <__gridxc_cell_MOD_cellxc+0x684c>\n+\tmul.w\tr3, ip, r3\n+\tadd\tr1, pc\n+\tadd.w\tr3, r6, r3, lsl #3\n+\tstr\tr3, [r2, #0]\n+\tldr.w\tr3, [r4, #1960]\t@ 0x7a8\n+\trsb\tlr, r3, #1\n+\tldr.w\tr3, [r4, #1972]\t@ 0x7b4\n+\tadd\tr5, lr\n+\tstr\tr5, [r2, #32]\n+\tldr.w\tr5, [r4, #1976]\t@ 0x7b8\n+\trsb\tip, r3, #1\n+\tldr.w\tr3, [r4, #1984]\t@ 0x7c0\n+\tadd\tr5, ip\n+\tstr\tr5, [r2, #44]\t@ 0x2c\n+\tldr.w\tr5, [r4, #1988]\t@ 0x7c4\n+\trsb\tr6, r3, #1\n+\tmovs\tr3, #8\n+\tstr\tr3, [r2, #8]\n+\tadd\tr5, r6\n \tmov.w\tr3, #772\t@ 0x304\n-\tstr.w\tsl, [r2, #64]\t@ 0x40\n+\tstr\tr5, [r2, #56]\t@ 0x38\n \tstrh\tr3, [r2, #16]\n-\tstr\tr5, [sp, #4]\n-\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n-\tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r9, #564\t@ 0x234\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n- R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n+\tbl\t0 <__gridxc_fftr_MOD_fftk2r>\n+ R_ARM_THM_CALL\t__gridxc_fftr_MOD_fftk2r\n+\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tcmp\tr3, #0\n+\tble.w\t6abe <__gridxc_cell_MOD_cellxc+0x64aa>\n+\tldr.w\tr2, [r4, #1920]\t@ 0x780\n+\tldr.w\tr3, [r4, #1888]\t@ 0x760\n+\tldr.w\tr1, [r4, #1308]\t@ 0x51c\n+\tldr.w\tr6, [r4, #1968]\t@ 0x7b0\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tmla\tr3, r2, r8, r3\n+\tldr.w\tr2, [r4, #1992]\t@ 0x7c8\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r4, #1936]\t@ 0x790\n+\tstr.w\tr6, [r7, #680]\t@ 0x2a8\n+\tadds\tr5, r2, r3\n+\tldr.w\tr3, [r4, #1884]\t@ 0x75c\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr3, [r4, #1908]\t@ 0x774\n+\tstr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r4, #1904]\t@ 0x770\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr2, [r4, #1320]\t@ 0x528\n+\tstr.w\tr2, [r7, #692]\t@ 0x2b4\n+\tcmp\tr3, #0\n+\tldr.w\tr9, [r4, #1284]\t@ 0x504\n+\tldr.w\tfp, [r4, #1288]\t@ 0x508\n+\tldr.w\tip, [r4, #1332]\t@ 0x534\n+\tldr.w\tr0, [r4, #1304]\t@ 0x518\n+\tldr.w\tr1, [r4, #1932]\t@ 0x78c\n+\tldr.w\tlr, [r4, #1980]\t@ 0x7bc\n+\tldr.w\tr6, [r4, #1956]\t@ 0x7a4\n+\tldr.w\tr2, [r4, #1952]\t@ 0x7a0\n+\tble.n\t6abe <__gridxc_cell_MOD_cellxc+0x64aa>\n+\tldr.w\tr4, [r7, #692]\t@ 0x2b4\n+\tmla\tr3, r0, fp, r9\n+\tmla\tr1, r2, r5, r1\n+\tmul.w\tr5, r0, ip\n+\tmul.w\tr6, r2, r6\n+\tstr.w\tr5, [r7, #656]\t@ 0x290\n+\tmul.w\tr4, r0, r4\n+\tstr.w\tr4, [r7, #664]\t@ 0x298\n+\tmul.w\tr5, r2, lr\n+\tldr.w\tr4, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tmovs\tr5, #0\n+\tstr.w\tr5, [r7, #692]\t@ 0x2b4\n+\tmul.w\tr4, r0, r4\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tmul.w\tr0, r2, r0\n+\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tmov\tlr, r3\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tmov\tip, r1\n+\tmovs\tr0, #0\n+\tstr.w\tr8, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tcmp\tr2, #0\n+\tble.n\t6a78 <__gridxc_cell_MOD_cellxc+0x6464>\n+\tmov\tr9, ip\n+\tmov\tr2, lr\n+\tmov.w\tr8, #0\n+\tstr.w\tr0, [r7, #600]\t@ 0x258\n+\tstr.w\tr1, [r7, #592]\t@ 0x250\n+\tb.n\t6a3e <__gridxc_cell_MOD_cellxc+0x642a>\n+\tmov\tr8, fp\n+\tldr\tr1, [r2, #0]\n+\tcbz\tr1, 6a64 <__gridxc_cell_MOD_cellxc+0x6450>\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n+\tadds\tr5, #1\n+\tldr.w\tr0, [r7, #732]\t@ 0x2dc\n+\tvldr\td7, [r9]\n+\tmla\tfp, r5, r0, r1\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tldr.w\tr0, [r7, #728]\t@ 0x2d8\n-\tcmp\tr0, #0\n-\tbeq.n\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n-\tldr.w\tr1, [r7, #552]\t@ 0x228\n-\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tstr.w\tfp, [r2, #8]\n-\tstr.w\tsl, [r2, #64]\t@ 0x40\n-\tvstr\td10, [r1]\n-\tmov.w\tr1, #772\t@ 0x304\n-\tstrh\tr1, [r2, #16]\n-\tldr.w\tr1, [r7, #580]\t@ 0x244\n-\tstr\tr1, [r2, #32]\n-\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n-\tstr\tr1, [r2, #44]\t@ 0x2c\n-\tldr.w\tr1, [r7, #532]\t@ 0x214\n-\tstr\tr1, [r2, #36]\t@ 0x24\n-\tldr.w\tr1, [r7, #576]\t@ 0x240\n-\tstr\tr1, [r2, #56]\t@ 0x38\n-\tldr.w\tr1, [r7, #448]\t@ 0x1c0\n-\tstr\tr1, [r2, #48]\t@ 0x30\n-\tstr\tr0, [r2, #0]\n-\tldr.w\tr1, [r7, #572]\t@ 0x23c\n-\tldr.w\tr0, [r7, #548]\t@ 0x224\n-\tstr\tr6, [r2, #28]\n-\tstr\tr6, [r2, #40]\t@ 0x28\n-\tstr\tr6, [r2, #52]\t@ 0x34\n-\tmov\tr6, r2\n-\tstr\tr1, [r2, #68]\t@ 0x44\n-\tldr.w\tr1, [r7, #620]\t@ 0x26c\n-\tstr\tr1, [r2, #60]\t@ 0x3c\n-\tmov\tr1, r4\n-\tldr.w\tr4, [r7, #620]\t@ 0x26c\n-\tadd.w\tr2, r9, #636\t@ 0x27c\n-\tvst1.32\t{d8}, [r0]\n+\tmla\tfp, r0, fp, r1\n+\tvstr\td7, [fp]\n+\tadd\tr2, r4\n+\tadd\tr9, r6\n+\tadd.w\tfp, r8, #1\n+\tcmp\tr8, r3\n+\tbne.n\t6a3c <__gridxc_cell_MOD_cellxc+0x6428>\n+\tldr.w\tr0, [r7, #600]\t@ 0x258\n+\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tadd.w\tr8, r0, #1\n+\tadd\tlr, r2\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tadd\tip, r2\n+\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n+\tcmp\tr0, r2\n+\tbeq.n\t6a94 <__gridxc_cell_MOD_cellxc+0x6480>\n \tmov\tr0, r8\n-\tnegs\tr4, r4\n-\tstr\tr4, [r6, #4]\n-\tstrd\tr6, r5, [sp]\n-\tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n- R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr2, [r7, #540]\t@ 0x21c\n-\tvldr\td25, [r3]\n+\tb.n\t6a22 <__gridxc_cell_MOD_cellxc+0x640e>\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr0, [r7, #692]\t@ 0x2b4\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr8, [r7, #680]\t@ 0x2a8\n+\tadd.w\tip, r0, #1\n+\tadd\tr1, r2\n+\tldr.w\tr2, [r7, #464]\t@ 0x1d0\n+\tcmp\tr0, r2\n+\tbeq.n\t6abe <__gridxc_cell_MOD_cellxc+0x64aa>\n+\tstr.w\tip, [r7, #692]\t@ 0x2b4\n+\tb.n\t6a10 <__gridxc_cell_MOD_cellxc+0x63fc>\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr3, r8\n+\tbge.w\t6742 <__gridxc_cell_MOD_cellxc+0x612e>\n+\tb.w\t1d3c <__gridxc_cell_MOD_cellxc+0x1728>\n+\tvldr\ts14, [pc, #900]\t@ 6e58 <__gridxc_cell_MOD_cellxc+0x6844>\n+\tvcmpe.f32\ts15, s14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbhi.w\t6568 <__gridxc_cell_MOD_cellxc+0x5f54>\n+\tldr.w\tr3, [r1, #1344]\t@ 0x540\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r1, #1348]\t@ 0x544\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r1, #1368]\t@ 0x558\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tb.n\t65ea <__gridxc_cell_MOD_cellxc+0x5fd6>\n+\tldr.w\tr2, [r0, #1348]\t@ 0x544\n+\tmov.w\tip, #0\n+\tldr.w\tr0, [r0, #1364]\t@ 0x554\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tadd\tr2, r1\n+\tvldr\td7, [pc, #832]\t@ 6e50 <__gridxc_cell_MOD_cellxc+0x683c>\n+\tmla\tr2, r0, r2, r3\n+\tmul.w\tr3, r1, r0\n+\tmov\tr0, r2\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tvstr\td7, [r0]\n+\tadd\tr0, r3\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tcmp\tr3, ip\n+\tadd.w\tip, ip, #1\n+\tbne.n\t6b1e <__gridxc_cell_MOD_cellxc+0x650a>\n+\tmov.w\tip, #4294967295\t@ 0xffffffff\n+\tmovs\tr1, #0\n+\tadd.w\tr3, sl, #8\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tadds\tr1, #1\n+\tvldr\td7, [r2]\n+\tmovs\tr0, #0\n+\tstr.w\tfp, [r7, #552]\t@ 0x228\n+\tadd.w\tlr, r3, ip, lsl #3\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tadds\tr0, #1\n+\tvldmia\tlr!, {d6}\n+\tvldmia\tr3!, {d5}\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tvmla.f64\td7, d5, d6\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tcmp\tr0, r3\n+\tblt.n\t6b56 <__gridxc_cell_MOD_cellxc+0x6542>\n \tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tvldr\td26, [r3]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvadd.f64\td18, d25, d26\n-\tvldr\td16, [r3]\n-\tvldr\td17, [r3, #32]\n-\tvldr\td24, [r3, #64]\t@ 0x40\n-\tvadd.f64\td16, d18, d16\n-\tvadd.f64\td17, d18, d17\n-\tvadd.f64\td24, d18, d24\n-\tvstr\td16, [r3]\n-\tvstr\td17, [r3, #32]\n-\tvstr\td24, [r3, #64]\t@ 0x40\n+\tvstr\td7, [r2]\n+\tadd\tip, r3\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tadd\tr2, r3\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tcmp\tr1, r3\n+\tblt.n\t6b42 <__gridxc_cell_MOD_cellxc+0x652e>\n+\tb.n\t65ea <__gridxc_cell_MOD_cellxc+0x5fd6>\n+\tvldr\td7, [pc, #704]\t@ 6e50 <__gridxc_cell_MOD_cellxc+0x683c>\n+\tb.n\t6676 <__gridxc_cell_MOD_cellxc+0x6062>\n+\tldr.w\tr3, [r7, #388]\t@ 0x184\n+\tldr\tr3, [r3, #0]\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tb.n\t6732 <__gridxc_cell_MOD_cellxc+0x611e>\n+\tldr\tr2, [pc, #704]\t@ (6e64 <__gridxc_cell_MOD_cellxc+0x6850>)\n+\tldr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tadd\tr2, pc\n+\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n+\tadds\tr2, #4\n+\tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n+ R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n+\tldr.w\tr0, [r7, #632]\t@ 0x278\n+\tmovs\tr2, #72\t@ 0x48\n+\tmovs\tr1, #0\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tcmp\tr3, #0\n+\tbgt.w\t5bc6 <__gridxc_cell_MOD_cellxc+0x55b2>\n+\tldr.w\tr3, [r7, #388]\t@ 0x184\n+\tldr\tr3, [r3, #0]\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tb.w\t1d3c <__gridxc_cell_MOD_cellxc+0x1728>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tadds\tr3, r2, #1\n+\tcmp\tr2, r1\n+\tbeq.w\t57fc <__gridxc_cell_MOD_cellxc+0x51e8>\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tb.w\t4096 <__gridxc_cell_MOD_cellxc+0x3a82>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd.w\tr8, r8, #1\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tadd\tlr, r2\n+\tldr.w\tr2, [r7, #572]\t@ 0x23c\n+\tcmp\tr8, r2\n+\tbne.w\t578c <__gridxc_cell_MOD_cellxc+0x5178>\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr2, [r7, #520]\t@ 0x208\n+\tvldr\td3, [r3]\n+\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tvldr\td2, [r3]\n+\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tvadd.f64\td5, d3, d2\n+\tvldr\td6, [r3]\n+\tvldr\td7, [r3, #32]\n+\tvldr\td4, [r3, #64]\t@ 0x40\n+\tvadd.f64\td6, d5, d6\n+\tvadd.f64\td7, d5, d7\n+\tvadd.f64\td4, d5, d4\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #32]\n+\tvstr\td4, [r3, #64]\t@ 0x40\n \tcmp\tr2, #0\n-\tbne.w\t7590 <__gridxc_cell_MOD_cellxc+0x6fb4>\n-\tvldr\td20, [r3, #8]\n-\tvldr\td21, [r3, #16]\n-\tvldr\td23, [r3, #24]\n-\tvldr\td22, [r3, #40]\t@ 0x28\n-\tvldr\td18, [r3, #48]\t@ 0x30\n-\tvldr\td19, [r3, #56]\t@ 0x38\n-\tvmov.f64\td30, #112\t@ 0x3f800000 1.0\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n-\tldr.w\tr2, [r7, #220]\t@ 0xdc\n-\tvadd.f64\td25, d25, d25\n-\tvdiv.f64\td27, d30, d13\n-\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n-\tvadd.f64\td26, d26, d26\n-\tvldr\td29, [r3]\n-\tvldr\td28, [r2]\n-\tvstr\td25, [r1]\n-\tvadd.f64\td29, d29, d29\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tvadd.f64\td28, d28, d28\n-\tvstr\td29, [r3]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvstr\td26, [r1]\n-\tvstr\td28, [r2]\n-\tvmul.f64\td16, d27, d16\n-\tvmul.f64\td20, d27, d20\n-\tvmul.f64\td21, d27, d21\n-\tvmul.f64\td23, d27, d23\n-\tvmul.f64\td17, d27, d17\n-\tvmul.f64\td22, d27, d22\n-\tvmul.f64\td18, d27, d18\n-\tvmul.f64\td19, d27, d19\n-\tvmul.f64\td27, d27, d24\n-\tvstr\td16, [r3]\n-\tvstr\td20, [r3, #8]\n-\tvstr\td21, [r3, #16]\n-\tvstr\td23, [r3, #24]\n-\tvstr\td17, [r3, #32]\n-\tvstr\td22, [r3, #40]\t@ 0x28\n-\tvstr\td18, [r3, #48]\t@ 0x30\n-\tvstr\td19, [r3, #56]\t@ 0x38\n-\tvstr\td27, [r3, #64]\t@ 0x40\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tbne.w\t7400 <__gridxc_cell_MOD_cellxc+0x6dec>\n+\tvldr\td5, [r3, #8]\n+\tvldr\td9, [r3, #16]\n+\tvldr\td8, [r3, #24]\n+\tvldr\td0, [r3, #40]\t@ 0x28\n+\tvldr\td10, [r3, #48]\t@ 0x30\n+\tvldr\td1, [r3, #56]\t@ 0x38\n+\tvadd.f64\td3, d3, d3\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tvadd.f64\td2, d2, d2\n+\tvstr\td3, [r3]\n+\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tvstr\td2, [r3]\n+\tvmov.f64\td2, #112\t@ 0x3f800000 1.0\n+\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tvdiv.f64\td3, d2, d15\n+\tvmul.f64\td6, d3, d6\n+\tvmul.f64\td5, d3, d5\n+\tvmul.f64\td9, d3, d9\n+\tvmul.f64\td8, d3, d8\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td0, d3, d0\n+\tvmul.f64\td10, d3, d10\n+\tvmul.f64\td1, d3, d1\n+\tvmul.f64\td3, d3, d4\n+\tvstr\td6, [r3]\n+\tvstr\td5, [r3, #8]\n+\tvstr\td9, [r3, #16]\n+\tvstr\td8, [r3, #24]\n+\tvstr\td7, [r3, #32]\n+\tvstr\td0, [r3, #40]\t@ 0x28\n+\tvstr\td10, [r3, #48]\t@ 0x30\n+\tvstr\td1, [r3, #56]\t@ 0x38\n+\tvstr\td3, [r3, #64]\t@ 0x40\n+\tldr.w\tr3, [r7, #216]\t@ 0xd8\n+\tvldr\td4, [r3]\n+\tvadd.f64\td4, d4, d4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #212]\t@ 0xd4\n+\tvldr\td4, [r3]\n+\tvadd.f64\td4, d4, d4\n+\tvstr\td4, [r3]\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr3, #0\n-\tble.n\t7026 <__gridxc_cell_MOD_cellxc+0x6a4a>\n-\tldrd\tr2, r3, [r7, #592]\t@ 0x250\n+\tble.n\t6d7a <__gridxc_cell_MOD_cellxc+0x6766>\n+\tldr.w\tr2, [r7, #580]\t@ 0x244\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #564]\t@ 0x234\n \torrs\tr3, r2\n-\tbmi.n\t7026 <__gridxc_cell_MOD_cellxc+0x6a4a>\n-\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tbmi.n\t6d7a <__gridxc_cell_MOD_cellxc+0x6766>\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n \tmovs\tr1, #0\n \tmov\tr6, r1\n \tmov.w\tip, r3, lsl #3\n \tmov\tr3, r1\n \tmovs\tr5, #0\n-\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n \tmovs\tr0, #0\n-\tldr.w\tr9, [r7, #568]\t@ 0x238\n+\tldr.w\tr9, [r7, #564]\t@ 0x234\n \tadd.w\tr4, r2, r3, lsl #3\n \tmov\tr8, r4\n \tmov.w\tlr, #0\n-\tvldr\td24, [r8]\n+\tvldr\td4, [r8]\n \tcmp\tlr, r9\n \tadd.w\tlr, lr, #1\n-\tvadd.f64\td24, d24, d24\n-\tvstmia\tr8!, {d24}\n-\tbne.n\t6fdc <__gridxc_cell_MOD_cellxc+0x6a00>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n+\tvadd.f64\td4, d4, d4\n+\tvstmia\tr8!, {d4}\n+\tbne.n\t6d30 <__gridxc_cell_MOD_cellxc+0x671c>\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n \tadd\tr4, ip\n \tadd.w\tlr, r0, #1\n-\tcmp\tr2, r0\n-\tbeq.n\t7002 <__gridxc_cell_MOD_cellxc+0x6a26>\n+\tcmp\tr0, r2\n+\tbeq.n\t6d56 <__gridxc_cell_MOD_cellxc+0x6742>\n \tmov\tr0, lr\n-\tb.n\t6fd6 <__gridxc_cell_MOD_cellxc+0x69fa>\n-\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\tb.n\t6d2a <__gridxc_cell_MOD_cellxc+0x6716>\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr0, [r7, #580]\t@ 0x244\n \tadd\tr3, r2\n \tadds\tr2, r5, #1\n-\tcmp\tr5, r0\n-\tbeq.n\t7016 <__gridxc_cell_MOD_cellxc+0x6a3a>\n+\tcmp\tr0, r5\n+\tbeq.n\t6d6a <__gridxc_cell_MOD_cellxc+0x6756>\n \tmov\tr5, r2\n-\tb.n\t6fc8 <__gridxc_cell_MOD_cellxc+0x69ec>\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tb.n\t6d1c <__gridxc_cell_MOD_cellxc+0x6708>\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n \tadds\tr6, #1\n \tadd\tr1, r3\n-\tldr.w\tr3, [r7, #764]\t@ 0x2fc\n+\tldr.w\tr3, [r7, #796]\t@ 0x31c\n \tcmp\tr6, r3\n-\tbne.n\t6fc4 <__gridxc_cell_MOD_cellxc+0x69e8>\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvadd.f64\td16, d16, d16\n-\tvadd.f64\td20, d20, d20\n-\tvadd.f64\td21, d21, d21\n-\tvadd.f64\td23, d23, d23\n-\tvadd.f64\td17, d17, d17\n-\tvadd.f64\td22, d22, d22\n-\tvadd.f64\td18, d18, d18\n-\tvadd.f64\td19, d19, d19\n-\tvadd.f64\td27, d27, d27\n-\tvstr\td16, [r3]\n-\tvstr\td20, [r3, #8]\n-\tvstr\td21, [r3, #16]\n-\tvstr\td23, [r3, #24]\n-\tvstr\td17, [r3, #32]\n-\tvstr\td22, [r3, #40]\t@ 0x28\n-\tvstr\td18, [r3, #48]\t@ 0x30\n-\tvstr\td19, [r3, #56]\t@ 0x38\n-\tvstr\td27, [r3, #64]\t@ 0x40\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tbne.n\t6d18 <__gridxc_cell_MOD_cellxc+0x6704>\n+\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tvadd.f64\td6, d6, d6\n+\tvadd.f64\td5, d5, d5\n+\tvadd.f64\td9, d9, d9\n+\tvadd.f64\td8, d8, d8\n+\tvadd.f64\td7, d7, d7\n+\tvadd.f64\td0, d0, d0\n+\tvadd.f64\td10, d10, d10\n+\tvadd.f64\td1, d1, d1\n+\tvadd.f64\td3, d3, d3\n+\tvstr\td6, [r3]\n+\tvstr\td5, [r3, #8]\n+\tvstr\td9, [r3, #16]\n+\tvstr\td8, [r3, #24]\n+\tvstr\td7, [r3, #32]\n+\tvstr\td0, [r3, #40]\t@ 0x28\n+\tvstr\td10, [r3, #48]\t@ 0x30\n+\tvstr\td1, [r3, #56]\t@ 0x38\n+\tvstr\td3, [r3, #64]\t@ 0x40\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tcmp\tr3, #0\n-\tbeq.n\t7128 <__gridxc_cell_MOD_cellxc+0x6b4c>\n+\tbeq.n\t6e78 <__gridxc_cell_MOD_cellxc+0x6864>\n \tldr.w\tr3, [r7, #572]\t@ 0x23c\n \tcmp\tr3, #0\n-\tbeq.n\t7128 <__gridxc_cell_MOD_cellxc+0x6b4c>\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tbeq.n\t6e78 <__gridxc_cell_MOD_cellxc+0x6864>\n+\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n+\tldr.w\tr3, [r7, #548]\t@ 0x224\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tldr.w\tr2, [r7, #480]\t@ 0x1e0\n \torrs\tr3, r2\n-\tbmi.n\t7128 <__gridxc_cell_MOD_cellxc+0x6b4c>\n-\tldr.w\tr3, [r7, #620]\t@ 0x26c\n+\tbmi.n\t6e78 <__gridxc_cell_MOD_cellxc+0x6864>\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n \tmovs\tr6, #0\n-\tldr.w\tr5, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr5, [r7, #408]\t@ 0x198\n \tadd\tr5, r3\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n \tmov.w\tip, r3, lsl #3\n \tmov\tr1, r5\n \tmovs\tr3, #0\n-\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n \tmovs\tr0, #0\n-\tldr.w\tr9, [r7, #580]\t@ 0x244\n+\tldr.w\tr9, [r7, #548]\t@ 0x224\n \tadd.w\tr4, r2, r1, lsl #3\n \tmov\tr8, r4\n \tmov.w\tlr, #0\n-\tvldr\td16, [r8]\n-\tcmp\tr9, lr\n+\tvldr\td7, [r8]\n+\tcmp\tlr, r9\n \tadd.w\tlr, lr, #1\n-\tvadd.f64\td16, d16, d16\n-\tvstmia\tr8!, {d16}\n-\tbne.n\t70c0 <__gridxc_cell_MOD_cellxc+0x6ae4>\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tvadd.f64\td7, d7, d7\n+\tvstmia\tr8!, {d7}\n+\tbne.n\t6e14 <__gridxc_cell_MOD_cellxc+0x6800>\n+\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n \tadd\tr4, ip\n \tadd.w\tlr, r0, #1\n-\tcmp\tr2, r0\n-\tbeq.n\t70e6 <__gridxc_cell_MOD_cellxc+0x6b0a>\n+\tcmp\tr0, r2\n+\tbeq.n\t6e3a <__gridxc_cell_MOD_cellxc+0x6826>\n \tmov\tr0, lr\n-\tb.n\t70ba <__gridxc_cell_MOD_cellxc+0x6ade>\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr0, [r7, #576]\t@ 0x240\n+\tb.n\t6e0e <__gridxc_cell_MOD_cellxc+0x67fa>\n+\tldr.w\tr2, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr0, [r7, #480]\t@ 0x1e0\n \tadd\tr1, r2\n \tadds\tr2, r3, #1\n \tcmp\tr0, r3\n-\tbeq.n\t7118 <__gridxc_cell_MOD_cellxc+0x6b3c>\n+\tbeq.n\t6e68 <__gridxc_cell_MOD_cellxc+0x6854>\n \tmov\tr3, r2\n-\tb.n\t70ac <__gridxc_cell_MOD_cellxc+0x6ad0>\n+\tb.n\t6e00 <__gridxc_cell_MOD_cellxc+0x67ec>\n \tnop\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000570\n- R_ARM_REL32\t.data\n-\t.word\t0x00000542\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000436\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000316\n+\t...\n+\t.word\t0x44610000\n+\t.word\t0x00000594\n R_ARM_REL32\t.bss\n-\tldr.w\tr3, [r7, #620]\t@ 0x26c\n+\t.word\t0x0000054c\n+ R_ARM_REL32\t.data\n+\t.word\t0x000002ba\n+ R_ARM_REL32\t.rodata\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n \tadds\tr6, #1\n \tadd\tr5, r3\n \tldr.w\tr3, [r7, #572]\t@ 0x23c\n-\tcmp\tr6, r3\n-\tbne.n\t70a8 <__gridxc_cell_MOD_cellxc+0x6acc>\n-\tldr.w\tr3, [r7, #648]\t@ 0x288\n-\tcbz\tr3, 7188 <__gridxc_cell_MOD_cellxc+0x6bac>\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n+\tcmp\tr3, r6\n+\tbne.n\t6dfc <__gridxc_cell_MOD_cellxc+0x67e8>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tcbz\tr3, 6ed8 <__gridxc_cell_MOD_cellxc+0x68c4>\n+\tldr.w\tr2, [r7, #264]\t@ 0x108\n+\tldr.w\tr3, [r7, #136]\t@ 0x88\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #272]\t@ 0x110\n+\tldr.w\tr2, [r7, #260]\t@ 0x104\n \torrs\tr3, r2\n-\tbmi.n\t7188 <__gridxc_cell_MOD_cellxc+0x6bac>\n-\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tbmi.n\t6ed8 <__gridxc_cell_MOD_cellxc+0x68c4>\n+\tldr.w\tr3, [r7, #132]\t@ 0x84\n \tmov.w\tip, r3, lsl #3\n \tmovs\tr3, #0\n \tmov\tr6, r3\n-\tldr.w\tr2, [r7, #648]\t@ 0x288\n+\tldr.w\tr2, [r7, #652]\t@ 0x28c\n \tadd.w\tr1, r2, r3, lsl #3\n \tmovs\tr2, #0\n \tmov\tr4, r1\n \tmovs\tr0, #0\n \tmov\tlr, r3\n-\tvldr\td16, [r4]\n-\tldr.w\tr3, [r7, #140]\t@ 0x8c\n-\tvadd.f64\td16, d16, d16\n+\tvldr\td7, [r4]\n+\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tvadd.f64\td7, d7, d7\n \tcmp\tr3, r0\n \tadd.w\tr0, r0, #1\n-\tvstmia\tr4!, {d16}\n-\tbne.n\t715c <__gridxc_cell_MOD_cellxc+0x6b80>\n-\tldr.w\tr4, [r7, #276]\t@ 0x114\n+\tvstmia\tr4!, {d7}\n+\tbne.n\t6eac <__gridxc_cell_MOD_cellxc+0x6898>\n+\tldr.w\tr4, [r7, #264]\t@ 0x108\n \tmov\tr3, lr\n \tadd\tr1, ip\n \tadds\tr0, r2, #1\n \tcmp\tr4, r2\n-\tbeq.w\t770c <__gridxc_cell_MOD_cellxc+0x7130>\n+\tbeq.w\t748c <__gridxc_cell_MOD_cellxc+0x6e78>\n \tmov\tr2, r0\n-\tb.n\t7156 <__gridxc_cell_MOD_cellxc+0x6b7a>\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tb.n\t6ea6 <__gridxc_cell_MOD_cellxc+0x6892>\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n \tcmp\tr3, #0\n-\tbeq.n\t723a <__gridxc_cell_MOD_cellxc+0x6c5e>\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n+\tbeq.n\t6f8a <__gridxc_cell_MOD_cellxc+0x6976>\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n \tcmp\tr3, #0\n-\tble.n\t723a <__gridxc_cell_MOD_cellxc+0x6c5e>\n-\tldr.w\tr2, [r7, #536]\t@ 0x218\n-\tldr.w\tr3, [r7, #152]\t@ 0x98\n+\tble.n\t6f8a <__gridxc_cell_MOD_cellxc+0x6976>\n+\tldr.w\tr2, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n \torrs\tr3, r2\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n+\tldr.w\tr2, [r7, #272]\t@ 0x110\n \torrs\tr3, r2\n-\tbmi.n\t723a <__gridxc_cell_MOD_cellxc+0x6c5e>\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tbmi.n\t6f8a <__gridxc_cell_MOD_cellxc+0x6976>\n+\tldr.w\tr2, [r7, #412]\t@ 0x19c\n \tmovs\tr5, #0\n-\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tldr.w\tr3, [r7, #140]\t@ 0x8c\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #288]\t@ 0x120\n+\tldr.w\tr2, [r7, #276]\t@ 0x114\n \tlsls\tr6, r2, #3\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n+\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n \tadds\tr4, r3, r2\n \tmov\tr2, r4\n \tmov.w\tip, #3\n-\tldr.w\tr9, [r7, #152]\t@ 0x98\n+\tldr.w\tr9, [r7, #148]\t@ 0x94\n \tmov\tr1, r2\n \tmovs\tr3, #0\n-\tldr.w\tr0, [r7, #588]\t@ 0x24c\n+\tldr.w\tr0, [r7, #576]\t@ 0x240\n \tmov.w\tsl, #0\n \tadd.w\tfp, r0, r1, lsl #3\n \tmov\tr8, fp\n \tmov.w\tlr, #0\n-\tvldr\td16, [r8]\n+\tvldr\td7, [r8]\n \tcmp\tr9, lr\n \tadd.w\tlr, lr, #1\n-\tvadd.f64\td16, d16, d16\n-\tvstmia\tr8!, {d16}\n-\tbne.n\t71e2 <__gridxc_cell_MOD_cellxc+0x6c06>\n-\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tvadd.f64\td7, d7, d7\n+\tvstmia\tr8!, {d7}\n+\tbne.n\t6f32 <__gridxc_cell_MOD_cellxc+0x691e>\n+\tldr.w\tr0, [r7, #516]\t@ 0x204\n \tadd\tfp, r6\n \tadd.w\tlr, sl, #1\n \tcmp\tr0, sl\n-\tbeq.n\t7208 <__gridxc_cell_MOD_cellxc+0x6c2c>\n+\tbeq.n\t6f58 <__gridxc_cell_MOD_cellxc+0x6944>\n \tmov\tsl, lr\n-\tb.n\t71dc <__gridxc_cell_MOD_cellxc+0x6c00>\n-\tldr.w\tr0, [r7, #148]\t@ 0x94\n+\tb.n\t6f2c <__gridxc_cell_MOD_cellxc+0x6918>\n+\tldr.w\tr0, [r7, #144]\t@ 0x90\n \tadd.w\tlr, r3, #1\n \tadd\tr1, r0\n-\tldr.w\tr0, [r7, #284]\t@ 0x11c\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n \tcmp\tr0, r3\n-\tbeq.n\t721e <__gridxc_cell_MOD_cellxc+0x6c42>\n+\tbeq.n\t6f6e <__gridxc_cell_MOD_cellxc+0x695a>\n \tmov\tr3, lr\n-\tb.n\t71d0 <__gridxc_cell_MOD_cellxc+0x6bf4>\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tb.n\t6f20 <__gridxc_cell_MOD_cellxc+0x690c>\n+\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n \tsubs.w\tip, ip, #1\n \tadd\tr2, r3\n-\tbne.n\t71c8 <__gridxc_cell_MOD_cellxc+0x6bec>\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tbne.n\t6f18 <__gridxc_cell_MOD_cellxc+0x6904>\n+\tldr.w\tr3, [r7, #412]\t@ 0x19c\n \tadds\tr5, #1\n \tadd\tr4, r3\n-\tldr.w\tr3, [r7, #280]\t@ 0x118\n-\tcmp\tr3, r5\n-\tbne.n\t71c2 <__gridxc_cell_MOD_cellxc+0x6be6>\n-\tldr.w\tr3, [r7, #540]\t@ 0x21c\n+\tldr.w\tr3, [r7, #268]\t@ 0x10c\n+\tcmp\tr5, r3\n+\tbne.n\t6f12 <__gridxc_cell_MOD_cellxc+0x68fe>\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n \tcmp\tr3, #0\n-\tbne.w\t749a <__gridxc_cell_MOD_cellxc+0x6ebe>\n-\tldr.w\tr4, [pc, #1040]\t@ 7658 <__gridxc_cell_MOD_cellxc+0x707c>\n+\tbne.w\t71d4 <__gridxc_cell_MOD_cellxc+0x6bc0>\n+\tldr\tr4, [pc, #952]\t@ (7350 <__gridxc_cell_MOD_cellxc+0x6d3c>)\n \tadd\tr4, pc\n \tldr.w\tr3, [r4, #144]\t@ 0x90\n-\tcbz\tr3, 72a0 <__gridxc_cell_MOD_cellxc+0x6cc4>\n-\tldr.w\tr3, [r7, #692]\t@ 0x2b4\n+\tcbz\tr3, 6fee <__gridxc_cell_MOD_cellxc+0x69da>\n+\tldr.w\tr3, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tbne.w\t73c0 <__gridxc_cell_MOD_cellxc+0x6de4>\n-\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n-\tcbz\tr3, 7276 <__gridxc_cell_MOD_cellxc+0x6c9a>\n-\tldr\tr0, [pc, #1016]\t@ (765c <__gridxc_cell_MOD_cellxc+0x7080>)\n+\tbne.w\t70fa <__gridxc_cell_MOD_cellxc+0x6ae6>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tcbz\tr3, 6fc4 <__gridxc_cell_MOD_cellxc+0x69b0>\n+\tldr\tr0, [pc, #932]\t@ (7354 <__gridxc_cell_MOD_cellxc+0x6d40>)\n \tmovs\tr2, #0\n-\tldr\tr1, [pc, #1016]\t@ (7660 <__gridxc_cell_MOD_cellxc+0x7084>)\n+\tldr\tr1, [pc, #932]\t@ (7358 <__gridxc_cell_MOD_cellxc+0x6d44>)\n \tmovs\tr3, #15\n \tadd\tr0, pc\n \tstr\tr2, [sp, #0]\n \tadd.w\tr0, r0, #636\t@ 0x27c\n \tadd\tr1, pc\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr4, [pc, #1004]\t@ (7664 <__gridxc_cell_MOD_cellxc+0x7088>)\n+\tldr\tr4, [pc, #916]\t@ (735c <__gridxc_cell_MOD_cellxc+0x6d48>)\n \tmovs\tr5, #0\n-\tldr\tr1, [pc, #1004]\t@ (7668 <__gridxc_cell_MOD_cellxc+0x708c>)\n+\tldr\tr1, [pc, #916]\t@ (7360 <__gridxc_cell_MOD_cellxc+0x6d4c>)\n \tmovs\tr3, #12\n \tadd\tr4, pc\n \tmov\tr2, r5\n \tadd\tr1, pc\n \tadd.w\tr0, r4, #564\t@ 0x234\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #988]\t@ (766c <__gridxc_cell_MOD_cellxc+0x7090>)\n+\tldr\tr1, [pc, #900]\t@ (7364 <__gridxc_cell_MOD_cellxc+0x6d50>)\n \tadd.w\tr0, r4, #144\t@ 0x90\n \tmov\tr2, r5\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n \tmovs\tr5, #0\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr2, [r7, #32]\n \tmov\tr3, r5\n \tmov\tr1, r5\n \tmov\tr0, r5\n \tstrd\tr5, r5, [sp, #8]\n \tstrd\tr5, r5, [sp]\n-\tvmov.i64\td8, #0x0000000000000000\n \tbl\t0 <__gridxc_alloc_MOD_alloc_default>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_alloc_default\n-\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\taddw\tr0, r7, #2180\t@ 0x884\n-\tldr\tr4, [pc, #932]\t@ (7670 <__gridxc_cell_MOD_cellxc+0x7094>)\n-\tstr\tr3, [r6, #0]\n+\tldr.w\tr0, [r7, #560]\t@ 0x230\n+\tldr.w\tr6, [r7, #760]\t@ 0x2f8\n \tmov.w\tip, #3\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tvldr\td8, [pc, #820]\t@ 7348 <__gridxc_cell_MOD_cellxc+0x6d34>\n+\tldr\tr4, [pc, #848]\t@ (7368 <__gridxc_cell_MOD_cellxc+0x6d54>)\n+\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tstr\tr3, [r6, #0]\n \tadd\tr4, pc\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tmov.w\tlr, #8\n-\tvstr\td8, [r4, #48]\t@ 0x30\n-\tvstr\td16, [r3]\n-\tldr.w\tr3, [r7, #548]\t@ 0x224\n-\tvldr\td16, [pc, #848]\t@ 7640 <__gridxc_cell_MOD_cellxc+0x7064>\n-\tvldr\td17, [pc, #852]\t@ 7648 <__gridxc_cell_MOD_cellxc+0x706c>\n-\tvstr\td8, [r2, #-8]\n-\tldrd\tr2, r1, [r7, #504]\t@ 0x1f8\n-\tvst1.32\t{d16-d17}, [r3]\n-\tvldr\td16, [pc, #844]\t@ 7650 <__gridxc_cell_MOD_cellxc+0x7074>\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tvst1.32\t{d16}, [r0]\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tvstr\td8, [r0]\n+\tvstr\td8, [r0, #-8]\n \tmov\tr0, r6\n+\tstrd\tr5, r5, [r3]\n+\tldrd\tr2, r1, [r7, #492]\t@ 0x1ec\n+\tstr.w\tip, [r6, #32]\n \tstr.w\tip, [r6, #44]\t@ 0x2c\n+\tstr.w\tip, [r6, #36]\t@ 0x24\n+\tmovs\tr6, #1\n+\tldr.w\tr3, [r7, #216]\t@ 0xd8\n+\tstrd\tr6, r6, [r0, #24]\n+\tstr\tr6, [r0, #40]\t@ 0x28\n+\tmovs\tr6, #8\n+\tvstr\td8, [r4, #48]\t@ 0x30\n+\tstr\tr6, [r0, #20]\n+\tstr\tr6, [r0, #8]\n \tmvn.w\tr6, #3\n-\tvstr\td8, [r3]\n-\tstrd\tr6, lr, [r0, #4]\n+\tstr\tr6, [r0, #4]\n \tmovw\tr6, #770\t@ 0x302\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n \tstrh\tr6, [r0, #16]\n \tstr.w\tip, [sp, #36]\t@ 0x24\n \tstr\tr0, [sp, #24]\n-\tldr.w\tr0, [r7, #500]\t@ 0x1f4\n-\tstr\tr0, [sp, #8]\n-\tldr.w\tr0, [r7, #220]\t@ 0xdc\n-\tstr\tr0, [sp, #0]\n+\tldr\tr6, [r7, #88]\t@ 0x58\n+\tstr\tr6, [sp, #4]\n+\tldr.w\tr6, [r7, #212]\t@ 0xd4\n+\tldr\tr0, [pc, #760]\t@ (736c <__gridxc_cell_MOD_cellxc+0x6d58>)\n \tstrd\tr5, r5, [sp, #28]\n+\tstr\tr6, [sp, #0]\n+\tadd\tr0, pc\n \tstrd\tr5, r5, [sp, #16]\n-\tldr\tr0, [pc, #816]\t@ (7674 <__gridxc_cell_MOD_cellxc+0x7098>)\n \tstr\tr5, [sp, #12]\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tadd\tr0, pc\n-\tstr\tr5, [sp, #4]\n+\tldr.w\tr5, [r7, #560]\t@ 0x230\n+\tstr\tr5, [sp, #8]\n \tbl\t0 <__gridxc_moreparallelsubs_MOD_miscallreducedouble>\n R_ARM_THM_CALL\t__gridxc_moreparallelsubs_MOD_miscallreducedouble\n-\tldr\tr3, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n \tmovs\tr1, #7\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tvldr\td16, [r5]\n-\tldr\tr3, [r3, #0]\n-\tvmov\ts15, r3\n-\tldr\tr0, [pc, #784]\t@ (7678 <__gridxc_cell_MOD_cellxc+0x709c>)\n-\tvldr\td19, [r2, #-8]\n-\tvcvt.f64.s32\td17, s15\n-\tldr\tr2, [pc, #780]\t@ (767c <__gridxc_cell_MOD_cellxc+0x70a0>)\n+\tvldr\td7, [r5, #-8]\n+\tvldr\td4, [r5]\n+\tvldr\ts12, [r3]\n+\tldr\tr3, [pc, #720]\t@ (7370 <__gridxc_cell_MOD_cellxc+0x6d5c>)\n+\tldr\tr0, [pc, #720]\t@ (7374 <__gridxc_cell_MOD_cellxc+0x6d60>)\n+\tvcvt.f64.s32\td6, s12\n \tadd\tr0, pc\n-\tmov\tr3, r2\n-\tldr.w\tr2, [r7, #632]\t@ 0x278\n-\tvdiv.f64\td18, d16, d17\n-\tvdiv.f64\td16, d19, d17\n-\tvstr\td18, [r4, #32]\n-\tvfms.f64\td16, d18, d18\n-\tvmaxnm.f64\td16, d16, d8\n-\tvsqrt.f64\td17, d16\n-\tvstr\td17, [r4, #24]\n+\tvdiv.f64\td5, d7, d6\n+\tvdiv.f64\td7, d4, d6\n+\tvstr\td5, [r4, #32]\n+\tvmls.f64\td7, d5, d5\n+\tvcmpe.f64\td7, d8\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d8\n+\tvsqrt.f64\td6, d7\n+\tvstr\td6, [r4, #24]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #740]\t@ (7680 <__gridxc_cell_MOD_cellxc+0x70a4>)\n-\tldr\tr3, [pc, #740]\t@ (7684 <__gridxc_cell_MOD_cellxc+0x70a8>)\n+\tldr\tr2, [pc, #672]\t@ (7378 <__gridxc_cell_MOD_cellxc+0x6d64>)\n+\tldr\tr3, [pc, #676]\t@ (737c <__gridxc_cell_MOD_cellxc+0x6d68>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #3180]\t@ 0xc6c\n+\tldr.w\tr3, [r7, #3156]\t@ 0xc54\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t758c <__gridxc_cell_MOD_cellxc+0x6fb0>\n-\taddw\tr7, r7, #3188\t@ 0xc74\n+\tbne.w\t72c6 <__gridxc_cell_MOD_cellxc+0x6cb2>\n+\taddw\tr7, r7, #3164\t@ 0xc5c\n \tmov\tsp, r7\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [pc, #708]\t@ (7688 <__gridxc_cell_MOD_cellxc+0x70ac>)\n+\tldr\tr1, [pc, #644]\t@ (7380 <__gridxc_cell_MOD_cellxc+0x6d6c>)\n \tmovs\tr5, #0\n \tmov\tr2, r5\n \taddw\tr0, r4, #1068\t@ 0x42c\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #692]\t@ (768c <__gridxc_cell_MOD_cellxc+0x70b0>)\n+\tldr\tr1, [pc, #628]\t@ (7384 <__gridxc_cell_MOD_cellxc+0x6d70>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #996\t@ 0x3e4\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #680]\t@ (7690 <__gridxc_cell_MOD_cellxc+0x70b4>)\n+\tldr\tr1, [pc, #612]\t@ (7388 <__gridxc_cell_MOD_cellxc+0x6d74>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #924\t@ 0x39c\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #664]\t@ (7694 <__gridxc_cell_MOD_cellxc+0x70b8>)\n+\tldr\tr1, [pc, #600]\t@ (738c <__gridxc_cell_MOD_cellxc+0x6d78>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #852\t@ 0x354\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #652]\t@ (7698 <__gridxc_cell_MOD_cellxc+0x70bc>)\n+\tldr\tr1, [pc, #584]\t@ (7390 <__gridxc_cell_MOD_cellxc+0x6d7c>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #780\t@ 0x30c\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #636]\t@ (769c <__gridxc_cell_MOD_cellxc+0x70c0>)\n+\tldr\tr1, [pc, #572]\t@ (7394 <__gridxc_cell_MOD_cellxc+0x6d80>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #708\t@ 0x2c4\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #624]\t@ (76a0 <__gridxc_cell_MOD_cellxc+0x70c4>)\n+\tldr\tr1, [pc, #556]\t@ (7398 <__gridxc_cell_MOD_cellxc+0x6d84>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #72\t@ 0x48\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #608]\t@ (76a4 <__gridxc_cell_MOD_cellxc+0x70c8>)\n+\tldr\tr1, [pc, #544]\t@ (739c <__gridxc_cell_MOD_cellxc+0x6d88>)\n \tmov\tr2, r5\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #596]\t@ (76a8 <__gridxc_cell_MOD_cellxc+0x70cc>)\n+\tldr\tr1, [pc, #532]\t@ (73a0 <__gridxc_cell_MOD_cellxc+0x6d8c>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #432\t@ 0x1b0\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #584]\t@ (76ac <__gridxc_cell_MOD_cellxc+0x70d0>)\n+\tldr\tr1, [pc, #516]\t@ (73a4 <__gridxc_cell_MOD_cellxc+0x6d90>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #360\t@ 0x168\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #568]\t@ (76b0 <__gridxc_cell_MOD_cellxc+0x70d4>)\n+\tldr\tr1, [pc, #504]\t@ (73a8 <__gridxc_cell_MOD_cellxc+0x6d94>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #288\t@ 0x120\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #556]\t@ (76b4 <__gridxc_cell_MOD_cellxc+0x70d8>)\n+\tldr\tr1, [pc, #488]\t@ (73ac <__gridxc_cell_MOD_cellxc+0x6d98>)\n \tadd.w\tr0, r4, #216\t@ 0xd8\n \tmov\tr2, r5\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tb.n\t725a <__gridxc_cell_MOD_cellxc+0x6c7e>\n-\tldr\tr4, [pc, #540]\t@ (76b8 <__gridxc_cell_MOD_cellxc+0x70dc>)\n+\tb.n\t6fa8 <__gridxc_cell_MOD_cellxc+0x6994>\n+\tldr\tr4, [pc, #472]\t@ (73b0 <__gridxc_cell_MOD_cellxc+0x6d9c>)\n \tmovs\tr5, #0\n-\tldr\tr1, [pc, #540]\t@ (76bc <__gridxc_cell_MOD_cellxc+0x70e0>)\n+\tldr\tr1, [pc, #472]\t@ (73b4 <__gridxc_cell_MOD_cellxc+0x6da0>)\n \tmov\tr2, r5\n \tadd\tr4, pc\n \tmovs\tr3, #9\n-\tadd.w\tr0, r4, #1816\t@ 0x718\n+\taddw\tr0, r4, #1812\t@ 0x714\n \tadd\tr1, pc\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr1, [pc, #524]\t@ (76c0 <__gridxc_cell_MOD_cellxc+0x70e4>)\n+\tldr\tr1, [pc, #456]\t@ (73b8 <__gridxc_cell_MOD_cellxc+0x6da4>)\n \tmov\tr2, r5\n \taddw\tr0, r4, #1764\t@ 0x6e4\n \tadd\tr1, pc\n \tmovs\tr3, #11\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #508]\t@ (76c4 <__gridxc_cell_MOD_cellxc+0x70e8>)\n+\tldr\tr1, [pc, #444]\t@ (73bc <__gridxc_cell_MOD_cellxc+0x6da8>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1728\t@ 0x6c0\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #496]\t@ (76c8 <__gridxc_cell_MOD_cellxc+0x70ec>)\n+\tldr\tr1, [pc, #428]\t@ (73c0 <__gridxc_cell_MOD_cellxc+0x6dac>)\n \tmov\tr2, r5\n \taddw\tr0, r4, #1692\t@ 0x69c\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #480]\t@ (76cc <__gridxc_cell_MOD_cellxc+0x70f0>)\n+\tldr\tr1, [pc, #416]\t@ (73c4 <__gridxc_cell_MOD_cellxc+0x6db0>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1656\t@ 0x678\n \tadd\tr1, pc\n \tmovs\tr3, #11\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #468]\t@ (76d0 <__gridxc_cell_MOD_cellxc+0x70f4>)\n+\tldr\tr1, [pc, #400]\t@ (73c8 <__gridxc_cell_MOD_cellxc+0x6db4>)\n \tmov\tr2, r5\n \taddw\tr0, r4, #1620\t@ 0x654\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #452]\t@ (76d4 <__gridxc_cell_MOD_cellxc+0x70f8>)\n+\tldr\tr1, [pc, #388]\t@ (73cc <__gridxc_cell_MOD_cellxc+0x6db8>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1584\t@ 0x630\n \tadd\tr1, pc\n \tmovs\tr3, #9\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #440]\t@ (76d8 <__gridxc_cell_MOD_cellxc+0x70fc>)\n+\tldr\tr1, [pc, #372]\t@ (73d0 <__gridxc_cell_MOD_cellxc+0x6dbc>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1536\t@ 0x600\n \tadd\tr1, pc\n \tmovs\tr3, #10\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #424]\t@ (76dc <__gridxc_cell_MOD_cellxc+0x7100>)\n+\tldr\tr1, [pc, #360]\t@ (73d4 <__gridxc_cell_MOD_cellxc+0x6dc0>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1488\t@ 0x5d0\n \tadd\tr1, pc\n \tmovs\tr3, #13\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #412]\t@ (76e0 <__gridxc_cell_MOD_cellxc+0x7104>)\n+\tldr\tr1, [pc, #344]\t@ (73d8 <__gridxc_cell_MOD_cellxc+0x6dc4>)\n \tmov\tr2, r5\n \taddw\tr0, r4, #1428\t@ 0x594\n \tadd\tr1, pc\n \tmovs\tr3, #12\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d3\n-\tldr\tr1, [pc, #396]\t@ (76e4 <__gridxc_cell_MOD_cellxc+0x7108>)\n+\tldr\tr1, [pc, #332]\t@ (73dc <__gridxc_cell_MOD_cellxc+0x6dc8>)\n \tmov\tr2, r5\n \taddw\tr0, r4, #1380\t@ 0x564\n \tadd\tr1, pc\n \tmovs\tr3, #11\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d2\n-\tldr\tr1, [pc, #384]\t@ (76e8 <__gridxc_cell_MOD_cellxc+0x710c>)\n+\tldr\tr1, [pc, #316]\t@ (73e0 <__gridxc_cell_MOD_cellxc+0x6dcc>)\n \tmov\tr2, r5\n \tadd.w\tr0, r4, #1344\t@ 0x540\n \tadd\tr1, pc\n \tmovs\tr3, #11\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d1\n-\tldr\tr1, [pc, #368]\t@ (76ec <__gridxc_cell_MOD_cellxc+0x7110>)\n+\tldr\tr1, [pc, #304]\t@ (73e4 <__gridxc_cell_MOD_cellxc+0x6dd0>)\n \taddw\tr0, r4, #1284\t@ 0x504\n \tmov\tr2, r5\n \tadd\tr1, pc\n \tmovs\tr3, #15\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_l3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_l3\n-\tb.n\t7244 <__gridxc_cell_MOD_cellxc+0x6c68>\n+\tb.n\t6f94 <__gridxc_cell_MOD_cellxc+0x6980>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tvldr\td28, [r3]\n-\tvldr\td6, [r3, #8]\n-\tvldr\td7, [r3, #16]\n-\tvldr\td31, [r3, #24]\n-\tvfma.f64\td16, d9, d28\n-\tvldr\td27, [r3, #32]\n-\tvldr\td30, [r3, #40]\t@ 0x28\n-\tvldr\td4, [r3, #48]\t@ 0x30\n-\tvldr\td3, [r3, #56]\t@ 0x38\n-\tvfma.f64\td17, d9, d27\n-\tvldr\td5, [r3, #64]\t@ 0x40\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvfma.f64\td24, d9, d5\n-\tvldr\td20, [r3, #8]\n-\tvldr\td21, [r3, #16]\n-\tvfma.f64\td20, d9, d6\n-\tvldr\td23, [r3, #24]\n-\tvfma.f64\td21, d9, d7\n-\tvldr\td22, [r3, #40]\t@ 0x28\n-\tvfma.f64\td23, d9, d31\n-\tvldr\td18, [r3, #48]\t@ 0x30\n-\tvfma.f64\td22, d9, d30\n-\tvldr\td19, [r3, #56]\t@ 0x38\n-\tvfma.f64\td18, d4, d9\n-\tvfma.f64\td19, d9, d3\n-\tvstr\td16, [r3]\n-\tvstr\td17, [r3, #32]\n-\tvstr\td24, [r3, #64]\t@ 0x40\n-\tvstr\td20, [r3, #8]\n-\tvstr\td21, [r3, #16]\n-\tvstr\td23, [r3, #24]\n-\tvstr\td22, [r3, #40]\t@ 0x28\n-\tvstr\td18, [r3, #48]\t@ 0x30\n-\tvstr\td19, [r3, #56]\t@ 0x38\n-\tb.n\t6f16 <__gridxc_cell_MOD_cellxc+0x693a>\n-\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n-\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmov\tr4, r0\n+\tldr\tr1, [pc, #280]\t@ (73e8 <__gridxc_cell_MOD_cellxc+0x6dd4>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #280]\t@ (73ec <__gridxc_cell_MOD_cellxc+0x6dd8>)\n+\tadd\tr1, pc\n+\tadd\tr0, pc\n+\tbl\t0 <_gfortran_os_error_at>\n+ R_ARM_THM_CALL\t_gfortran_os_error_at\n+\tmov\tr4, r0\n+\tldr\tr1, [pc, #272]\t@ (73f0 <__gridxc_cell_MOD_cellxc+0x6ddc>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #272]\t@ (73f4 <__gridxc_cell_MOD_cellxc+0x6de0>)\n+\tadd\tr1, pc\n+\tadd\tr0, pc\n+\tbl\t0 <_gfortran_os_error_at>\n+ R_ARM_THM_CALL\t_gfortran_os_error_at\n+\tldr.w\tr4, [r7, #448]\t@ 0x1c0\n+\tldr\tr1, [pc, #264]\t@ (73f8 <__gridxc_cell_MOD_cellxc+0x6de4>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #264]\t@ (73fc <__gridxc_cell_MOD_cellxc+0x6de8>)\n+\tadd\tr1, pc\n+\tadd\tr0, pc\n+\tbl\t0 <_gfortran_os_error_at>\n+ R_ARM_THM_CALL\t_gfortran_os_error_at\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tmov\tr2, fp\n+\tldr.w\tr0, [r7, #464]\t@ 0x1d0\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tmov\tfp, r2\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tcmp\tr1, r0\n \tadd\tr9, r2\n-\tldr.w\tr2, [r7, #620]\t@ 0x26c\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n-\tadd\tlr, r2\n-\tldr.w\tr2, [r7, #572]\t@ 0x23c\n-\tcmp\tr2, r3\n-\tbne.w\t6d2e <__gridxc_cell_MOD_cellxc+0x6752>\n-\tb.n\t6eb8 <__gridxc_cell_MOD_cellxc+0x68dc>\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n-\t.word\t0x00000003\n-\t.word\t0x00000001\n-\t.word\t0x0000040c\n+\tadd.w\tr2, r1, #1\n+\tbeq.w\t3b84 <__gridxc_cell_MOD_cellxc+0x3570>\n+\tstr.w\tr2, [r7, #776]\t@ 0x308\n+\tb.w\t4382 <__gridxc_cell_MOD_cellxc+0x3d6e>\n+\tmov\tr1, r2\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n+\tadd\tr1, r2\n+\tldr.w\tr2, [r7, #432]\t@ 0x1b0\n+\tcmp\tr4, r5\n+\tadd\tr9, r2\n+\tadd.w\tr2, r4, #1\n+\tbeq.w\t6bee <__gridxc_cell_MOD_cellxc+0x65da>\n+\tmov\tr4, r2\n+\tb.w\t5792 <__gridxc_cell_MOD_cellxc+0x517e>\n+\t...\n+\t.word\t0x000003b6\n R_ARM_REL32\t.bss\n-\t.word\t0x000003f0\n+\t.word\t0x0000039a\n R_ARM_REL32\t.bss\n-\t.word\t0x000003ec\n+\t.word\t0x00000396\n R_ARM_REL32\t.LC28\n-\t.word\t0x000003e2\n+\t.word\t0x0000038c\n R_ARM_REL32\t.bss\n-\t.word\t0x000003e2\n+\t.word\t0x0000038c\n R_ARM_REL32\t.LC27\n-\t.word\t0x000003d2\n+\t.word\t0x0000037c\n R_ARM_REL32\t.LC24\n-\t.word\t0x00000396\n+\t.word\t0x00000348\n R_ARM_REL32\t.data\n-\t.word\t0x00000326\n+\t.word\t0x000002f0\n R_ARM_REL32\t.LC56\n-\t.word\t0x00000304\n- R_ARM_REL32\t.LC0\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_stop\n-\t.word\t0x000002de\n+\t.word\t0x000002ca\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x0000029c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002ba\n+\t.word\t0x00000278\n R_ARM_REL32\t.LC40\n-\t.word\t0x000002ac\n+\t.word\t0x0000026a\n R_ARM_REL32\t.LC39\n-\t.word\t0x0000029e\n+\t.word\t0x0000025c\n R_ARM_REL32\t.LC38\n-\t.word\t0x00000290\n+\t.word\t0x0000024e\n R_ARM_REL32\t.LC37\n-\t.word\t0x00000282\n+\t.word\t0x00000240\n R_ARM_REL32\t.LC36\n-\t.word\t0x00000274\n+\t.word\t0x00000232\n R_ARM_REL32\t.LC35\n-\t.word\t0x00000266\n+\t.word\t0x00000224\n R_ARM_REL32\t.LC34\n-\t.word\t0x0000025a\n+\t.word\t0x00000218\n R_ARM_REL32\t.LC33\n-\t.word\t0x0000024c\n+\t.word\t0x0000020a\n R_ARM_REL32\t.LC32\n-\t.word\t0x0000023e\n+\t.word\t0x000001fc\n R_ARM_REL32\t.LC31\n-\t.word\t0x00000230\n+\t.word\t0x000001ee\n R_ARM_REL32\t.LC30\n-\t.word\t0x00000222\n+\t.word\t0x000001e0\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000212\n+\t.word\t0x000001d0\n R_ARM_REL32\t.bss\n-\t.word\t0x0000020e\n+\t.word\t0x000001cc\n R_ARM_REL32\t.LC55\n-\t.word\t0x00000202\n+\t.word\t0x000001c0\n R_ARM_REL32\t.LC54\n-\t.word\t0x000001f4\n+\t.word\t0x000001b2\n R_ARM_REL32\t.LC53\n-\t.word\t0x000001e6\n+\t.word\t0x000001a4\n R_ARM_REL32\t.LC52\n-\t.word\t0x000001d8\n+\t.word\t0x00000196\n R_ARM_REL32\t.LC51\n-\t.word\t0x000001ca\n+\t.word\t0x00000188\n R_ARM_REL32\t.LC50\n-\t.word\t0x000001bc\n+\t.word\t0x0000017a\n R_ARM_REL32\t.LC49\n-\t.word\t0x000001ae\n+\t.word\t0x0000016c\n R_ARM_REL32\t.LC48\n-\t.word\t0x000001a0\n+\t.word\t0x0000015e\n R_ARM_REL32\t.LC47\n-\t.word\t0x00000192\n+\t.word\t0x00000150\n R_ARM_REL32\t.LC46\n-\t.word\t0x00000184\n+\t.word\t0x00000142\n R_ARM_REL32\t.LC44\n-\t.word\t0x00000176\n+\t.word\t0x00000134\n R_ARM_REL32\t.LC43\n-\t.word\t0x00000168\n+\t.word\t0x00000126\n R_ARM_REL32\t.LC42\n-\tadd.w\tr1, r4, #852\t@ 0x354\n-\tmov\tr0, r6\n-\tmovs\tr2, #72\t@ 0x48\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemcpy\n-\tadd.w\tr1, r4, #924\t@ 0x39c\n-\tmov\tr0, r5\n-\tmovs\tr2, #72\t@ 0x48\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemcpy\n-\tb.w\t3758 <__gridxc_cell_MOD_cellxc+0x317c>\n-\tldr.w\tr2, [r7, #132]\t@ 0x84\n-\tldr.w\tr1, [r7, #272]\t@ 0x110\n+\t.word\t0x00000112\n+ R_ARM_REL32\t.LC15\n+\t.word\t0x00000114\n+ R_ARM_REL32\t.LC17\n+\t.word\t0x0000010a\n+ R_ARM_REL32\t.LC15\n+\t.word\t0x0000010c\n+ R_ARM_REL32\t.LC17\n+\t.word\t0x00000100\n+ R_ARM_REL32\t.LC15\n+\t.word\t0x00000102\n+ R_ARM_REL32\t.LC16\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n+\tvldr\td5, [r2]\n+\tvldr\td9, [r2, #8]\n+\tvldr\td8, [r2, #16]\n+\tvmla.f64\td6, d13, d5\n+\tvldr\td5, [r2, #32]\n+\tvldr\td0, [r2, #24]\n+\tvldr\td10, [r2, #40]\t@ 0x28\n+\tvmla.f64\td7, d13, d5\n+\tvldr\td5, [r2, #64]\t@ 0x40\n+\tvldr\td1, [r2, #48]\t@ 0x30\n+\tvldr\td11, [r2, #56]\t@ 0x38\n+\tvmla.f64\td4, d13, d5\n+\tvldr\td5, [r3, #8]\n+\tvmla.f64\td5, d13, d9\n+\tvldr\td9, [r3, #16]\n+\tvmla.f64\td9, d13, d8\n+\tvldr\td8, [r3, #24]\n+\tvmla.f64\td8, d13, d0\n+\tvldr\td0, [r3, #40]\t@ 0x28\n+\tvmla.f64\td0, d13, d10\n+\tvldr\td10, [r3, #48]\t@ 0x30\n+\tvmla.f64\td10, d13, d1\n+\tvldr\td1, [r3, #56]\t@ 0x38\n+\tvmla.f64\td1, d13, d11\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #32]\n+\tvstr\td4, [r3, #64]\t@ 0x40\n+\tvstr\td5, [r3, #8]\n+\tvstr\td9, [r3, #16]\n+\tvstr\td8, [r3, #24]\n+\tvstr\td0, [r3, #40]\t@ 0x28\n+\tvstr\td10, [r3, #48]\t@ 0x30\n+\tvstr\td1, [r3, #56]\t@ 0x38\n+\tb.w\t6c66 <__gridxc_cell_MOD_cellxc+0x6652>\n+\tldr.w\tr2, [r7, #128]\t@ 0x80\n+\tldr.w\tr1, [r7, #260]\t@ 0x104\n \tadd\tr3, r2\n \tadds\tr2, r6, #1\n \tcmp\tr1, r6\n-\tbeq.w\t7188 <__gridxc_cell_MOD_cellxc+0x6bac>\n+\tbeq.w\t6ed8 <__gridxc_cell_MOD_cellxc+0x68c4>\n \tmov\tr6, r2\n-\tb.n\t714c <__gridxc_cell_MOD_cellxc+0x6b70>\n-\tnop\n+\tb.n\t6e9c <__gridxc_cell_MOD_cellxc+0x6888>\n+\tadd.w\tfp, r8, #108\t@ 0x6c\n+\tmov\tr2, r0\n+\tmov\tr1, r8\n+\tmov\tr0, fp\n+\tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n+ R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #220]\t@ 0xdc\n+\tmovs\tr6, #8\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tmovs\tr5, #1\n+\tstr\tr2, [r3, #4]\n+\tmov.w\tr9, #772\t@ 0x304\n+\tldr.w\tr2, [r7, #792]\t@ 0x318\n+\tstrd\tr4, r4, [r1]\n+\tmov\tr1, r8\n+\tldr.w\tsl, [pc, #212]\t@ 75a8 <__gridxc_cell_MOD_cellxc+0x6f94>\n+\tldr.w\tr0, [r2, #552]\t@ 0x228\n+\tldr.w\tr2, [r7, #564]\t@ 0x234\n+\tadd\tsl, pc\n+\tstr\tr2, [r3, #32]\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tstr\tr2, [r3, #44]\t@ 0x2c\n+\tldr.w\tr2, [r7, #716]\t@ 0x2cc\n+\tstr\tr2, [r3, #36]\t@ 0x24\n+\tldr.w\tr2, [r7, #580]\t@ 0x244\n+\tstr\tr2, [r3, #56]\t@ 0x38\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tstr\tr2, [r3, #48]\t@ 0x30\n+\tldr.w\tr2, [r7, #796]\t@ 0x31c\n+\tstr\tr2, [r3, #68]\t@ 0x44\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tstr\tr2, [r3, #60]\t@ 0x3c\n+\tmov\tr2, r3\n+\tstr\tr4, [r3, #28]\n+\tstr\tr4, [r3, #40]\t@ 0x28\n+\tstr\tr4, [r3, #52]\t@ 0x34\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tstr\tr3, [r2, #0]\n+\tstr\tr6, [r2, #20]\n+\tstr\tr6, [r2, #8]\n+\tstr\tr5, [r2, #24]\n+\tstr\tr5, [r2, #64]\t@ 0x40\n+\tstrh.w\tr9, [r2, #16]\n+\tstr.w\tfp, [sp, #4]\n+\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tstr\tr2, [sp, #0]\n+\tadd.w\tr2, sl, #564\t@ 0x234\n+\tstr.w\tr0, [r7, #784]\t@ 0x310\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n+ R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n+\tldr.w\tr0, [r7, #752]\t@ 0x2f0\n+\tcmp\tr0, #0\n+\tbeq.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tstr\tr4, [r1, #4]\n+\tstrh.w\tr9, [r2, #16]\n+\tstr\tr6, [r2, #20]\n+\tstr\tr6, [r2, #8]\n+\tstr\tr4, [r1, #0]\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tstr\tr1, [r2, #32]\n+\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n+\tstr\tr1, [r2, #44]\t@ 0x2c\n+\tldr.w\tr1, [r7, #436]\t@ 0x1b4\n+\tstr\tr5, [r2, #24]\n+\tstr\tr5, [r2, #64]\t@ 0x40\n+\tmov\tr5, r2\n+\tstr\tr1, [r2, #36]\t@ 0x24\n+\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n+\tstr\tr4, [r2, #28]\n+\tstr\tr4, [r2, #40]\t@ 0x28\n+\tstr\tr4, [r2, #52]\t@ 0x34\n+\tstr\tr1, [r2, #56]\t@ 0x38\n+\tldr.w\tr4, [r7, #568]\t@ 0x238\n+\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tstr\tr1, [r2, #48]\t@ 0x30\n+\tldr.w\tr1, [r7, #572]\t@ 0x23c\n+\tstr\tr1, [r2, #68]\t@ 0x44\n+\tmov\tr1, r8\n+\tstr\tr4, [r2, #60]\t@ 0x3c\n+\tnegs\tr4, r4\n+\tstr\tr0, [r2, #0]\n+\tadd.w\tr2, sl, #636\t@ 0x27c\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tstr\tr4, [r5, #4]\n+\tstrd\tr5, fp, [sp]\n+\tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n+ R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n+\tb.w\t6c08 <__gridxc_cell_MOD_cellxc+0x65f4>\n+\t.word\t0x000000c8\n+ R_ARM_REL32\t.bss\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -44,110 +44,110 @@\n 0x00000290 6b2e3230 00647464 642e3139 00647464 k.20.dtdd.19.dtd\n 0x000002a0 67642e31 38006470 6869646b 2e313700 gd.18.dphidk.17.\n 0x000002b0 7068692e 31360074 6b2e3135 0074722e phi.16.tk.15.tr.\n 0x000002c0 31340074 7661632e 31330075 722e3132 14.tvac.13.ur.12\n 0x000002d0 00756b2e 31310074 7664772e 31300074 .uk.11.tvdw.10.t\n 0x000002e0 712e3900 75766477 2e380075 712e3700 q.9.uvdw.8.uq.7.\n 0x000002f0 766a2e34 00766c65 66742e36 00767267 vj.4.vleft.6.vrg\n- 0x00000300 68742e35 005f5f73 7461636b 5f63686b ht.5.__stack_chk\n- 0x00000310 5f666169 6c005f47 4c4f4241 4c5f4f46 _fail._GLOBAL_OF\n- 0x00000320 46534554 5f544142 4c455f00 5f5f7374 FSET_TABLE_.__st\n- 0x00000330 61636b5f 63686b5f 67756172 64005f5f ack_chk_guard.__\n- 0x00000340 67726964 78635f63 656c6c5f 4d4f445f gridxc_cell_MOD_\n- 0x00000350 63656c6c 7863005f 5f677269 6478635f cellxc.__gridxc_\n- 0x00000360 78636d6f 645f4d4f 445f6765 74786300 xcmod_MOD_getxc.\n- 0x00000370 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000380 4f445f61 6c6c6f63 5f646566 61756c74 OD_alloc_default\n- 0x00000390 005f5f67 72696478 635f6365 6c6c7375 .__gridxc_cellsu\n- 0x000003a0 62735f4d 4f445f76 6f6c6365 6c005f67 bs_MOD_volcel._g\n- 0x000003b0 666f7274 72616e5f 636f6d70 6172655f fortran_compare_\n- 0x000003c0 73747269 6e67005f 67666f72 7472616e string._gfortran\n- 0x000003d0 5f73745f 77726974 65005f67 666f7274 _st_write._gfort\n- 0x000003e0 72616e5f 7472616e 73666572 5f636861 ran_transfer_cha\n- 0x000003f0 72616374 65725f77 72697465 005f6766 racter_write._gf\n- 0x00000400 6f727472 616e5f73 745f7772 6974655f ortran_st_write_\n- 0x00000410 646f6e65 005f6766 6f727472 616e5f73 done._gfortran_s\n- 0x00000420 7472696e 675f7472 696d0066 72656500 tring_trim.free.\n- 0x00000430 5f5f6772 69647863 5f737973 5f4d4f44 __gridxc_sys_MOD\n- 0x00000440 5f677269 6478635f 74696d65 725f7374 _gridxc_timer_st\n- 0x00000450 61727400 5f5f6772 69647863 5f737973 art.__gridxc_sys\n- 0x00000460 5f4d4f44 5f646965 006d616c 6c6f6300 _MOD_die.malloc.\n- 0x00000470 6d656d73 6574005f 67666f72 7472616e memset._gfortran\n- 0x00000480 5f73745f 72656164 005f6766 6f727472 _st_read._gfortr\n- 0x00000490 616e5f74 72616e73 6665725f 696e7465 an_transfer_inte\n- 0x000004a0 67657200 5f67666f 72747261 6e5f7374 ger._gfortran_st\n- 0x000004b0 5f726561 645f646f 6e65005f 67666f72 _read_done._gfor\n- 0x000004c0 7472616e 5f636f6e 6361745f 73747269 tran_concat_stri\n- 0x000004d0 6e67005f 5f78635f 6630335f 6c69625f ng.__xc_f03_lib_\n- 0x000004e0 6d5f4d4f 445f7863 5f663033 5f66756e m_MOD_xc_f03_fun\n- 0x000004f0 635f696e 6974005f 5f78635f 6630335f c_init.__xc_f03_\n- 0x00000500 6c69625f 6d5f4d4f 445f7863 5f663033 lib_m_MOD_xc_f03\n- 0x00000510 5f66756e 635f6765 745f696e 666f005f _func_get_info._\n- 0x00000520 5f677269 6478635f 6d657368 33645f4d _gridxc_mesh3d_M\n- 0x00000530 4f445f73 65746d65 73686469 73747200 OD_setmeshdistr.\n- 0x00000540 5f5f6772 69647863 5f6d6573 6833645f __gridxc_mesh3d_\n- 0x00000550 4d4f445f 6d796d65 7368626f 78005f5f MOD_mymeshbox.__\n- 0x00000560 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n- 0x00000570 445f7361 6d656d65 73686469 73747200 D_samemeshdistr.\n- 0x00000580 5f5f6772 69647863 5f6d6573 6833645f __gridxc_mesh3d_\n- 0x00000590 4d4f445f 6173736f 63696174 656d6573 MOD_associatemes\n- 0x000005a0 68746173 6b005f5f 67726964 78635f6d htask.__gridxc_m\n- 0x000005b0 65736833 645f4d4f 445f636f 70796d65 esh3d_MOD_copyme\n- 0x000005c0 73686461 7461006d 656d6370 79005f67 shdata.memcpy._g\n- 0x000005d0 666f7274 72616e5f 6f735f65 72726f72 fortran_os_error\n- 0x000005e0 5f617400 5f5f6772 69647863 5f636f6e _at.__gridxc_con\n- 0x000005f0 6669675f 4d4f445f 67726964 78635f74 fig_MOD_gridxc_t\n- 0x00000600 6f746e6f 64657300 5f5f6772 69647863 otnodes.__gridxc\n- 0x00000610 5f63656c 6c737562 735f4d4f 445f7265 _cellsubs_MOD_re\n- 0x00000620 636c6174 005f5f67 72696478 635f6c64 clat.__gridxc_ld\n- 0x00000630 615f4d4f 445f6c64 61786300 5f5f6772 a_MOD_ldaxc.__gr\n- 0x00000640 69647863 5f676761 5f4d4f44 5f676761 idxc_gga_MOD_gga\n- 0x00000650 7863005f 5f677269 6478635f 76647778 xc.__gridxc_vdwx\n- 0x00000660 635f4d4f 445f7664 775f6c6f 63616c78 c_MOD_vdw_localx\n- 0x00000670 63005f5f 67726964 78635f76 64777863 c.__gridxc_vdwxc\n- 0x00000680 5f4d4f44 5f766477 5f646563 75737000 _MOD_vdw_decusp.\n- 0x00000690 5f5f6772 69647863 5f766477 78635f4d __gridxc_vdwxc_M\n- 0x000006a0 4f445f76 64775f74 68657461 005f5f78 OD_vdw_theta.__x\n- 0x000006b0 635f6630 335f6c69 625f6d5f 4d4f445f c_f03_lib_m_MOD_\n- 0x000006c0 78635f66 30335f66 756e635f 656e6400 xc_f03_func_end.\n- 0x000006d0 5f5f6772 69647863 5f6d6573 6833645f __gridxc_mesh3d_\n- 0x000006e0 4d4f445f 6164646d 65736864 61746100 MOD_addmeshdata.\n- 0x000006f0 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000700 4f445f72 65616c6c 6f635f6c 33005f5f OD_realloc_l3.__\n- 0x00000710 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n- 0x00000720 445f6666 746d6573 68646973 7472005f D_fftmeshdistr._\n- 0x00000730 5f677269 6478635f 76647778 635f4d4f _gridxc_vdwxc_MO\n- 0x00000740 445f7664 775f6765 745f716d 65736800 D_vdw_get_qmesh.\n- 0x00000750 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000760 4f445f72 65616c6c 6f635f64 31005f5f OD_realloc_d1.__\n- 0x00000770 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x00000780 5f726561 6c6c6f63 5f643200 5f5f6772 _realloc_d2.__gr\n- 0x00000790 69647863 5f616c6c 6f635f4d 4f445f72 idxc_alloc_MOD_r\n- 0x000007a0 65616c6c 6f635f64 33005f5f 67726964 ealloc_d3.__grid\n- 0x000007b0 78635f61 6c6c6f63 5f4d4f44 5f726561 xc_alloc_MOD_rea\n- 0x000007c0 6c6c6f63 5f643400 5f5f6772 69647863 lloc_d4.__gridxc\n- 0x000007d0 5f63686b 676d785f 4d4f445f 6d657368 _chkgmx_MOD_mesh\n- 0x000007e0 6b637574 005f5f67 72696478 635f7664 kcut.__gridxc_vd\n- 0x000007f0 7778635f 4d4f445f 7664775f 7365745f wxc_MOD_vdw_set_\n- 0x00000800 6b637574 005f5f67 72696478 635f6666 kcut.__gridxc_ff\n- 0x00000810 74725f4d 4f445f66 66747232 6b005f5f tr_MOD_fftr2k.__\n- 0x00000820 67726964 78635f76 64777863 5f4d4f44 gridxc_vdwxc_MOD\n- 0x00000830 5f766477 5f706869 005f6766 6f727472 _vdw_phi._gfortr\n- 0x00000840 616e5f6d 61746d75 6c5f7238 005f5f67 an_matmul_r8.__g\n- 0x00000850 72696478 635f6666 74725f4d 4f445f66 ridxc_fftr_MOD_f\n- 0x00000860 66746b32 72005f5f 67726964 78635f61 ftk2r.__gridxc_a\n- 0x00000870 6c6c6f63 5f4d4f44 5f646561 6c6c6f63 lloc_MOD_dealloc\n- 0x00000880 5f643300 5f5f6772 69647863 5f616c6c _d3.__gridxc_all\n- 0x00000890 6f635f4d 4f445f64 65616c6c 6f635f64 oc_MOD_dealloc_d\n- 0x000008a0 34005f5f 67726964 78635f6d 6f726570 4.__gridxc_morep\n- 0x000008b0 6172616c 6c656c73 7562735f 4d4f445f arallelsubs_MOD_\n- 0x000008c0 6d697363 616c6c72 65647563 65646f75 miscallreducedou\n- 0x000008d0 626c6500 5f5f6772 69647863 5f616c6c ble.__gridxc_all\n- 0x000008e0 6f635f4d 4f445f64 65616c6c 6f635f64 oc_MOD_dealloc_d\n- 0x000008f0 32005f5f 67726964 78635f61 6c6c6f63 2.__gridxc_alloc\n- 0x00000900 5f4d4f44 5f646561 6c6c6f63 5f643100 _MOD_dealloc_d1.\n- 0x00000910 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n- 0x00000920 4f445f64 65616c6c 6f635f6c 33005f5f OD_dealloc_l3.__\n- 0x00000930 67726964 78635f73 79735f4d 4f445f67 gridxc_sys_MOD_g\n- 0x00000940 72696478 635f7469 6d65725f 73746f70 ridxc_timer_stop\n- 0x00000950 00 .\n+ 0x00000300 68742e35 005f5f61 65616269 5f696469 ht.5.__aeabi_idi\n+ 0x00000310 76005f5f 73746163 6b5f6368 6b5f6661 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V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 1956 (bytes into file)\n+ Start of section headers: 2248 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x7a4:\n+There are 12 section headers, starting at offset 0x8c8:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000430 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 0006cc 000070 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 000468 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 000468 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 000468 00001a 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 000484 000004 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 000488 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000488 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 0004bc 000120 10 10 10 4\n- [10] .strtab STRTAB 00000000 0005dc 0000f0 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 00073c 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 000558 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0007f0 000070 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 000590 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 000590 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 000590 00001a 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 0005ac 000004 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 0005b0 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0005b0 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 0005e0 000120 10 10 10 4\n+ [10] .strtab STRTAB 00000000 000700 0000f0 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 000860 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,21 +1,21 @@\n \n Symbol table '.symtab' contains 18 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 4: 00000378 0 NOTYPE LOCAL DEFAULT 1 $d\n- 5: 00000001 928 FUNC LOCAL DEFAULT 1 __gridxc_chkgmx_MOD_chkgmx.localalias\n- 6: 000003a0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 7: 00000418 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 4: 000004a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 00000001 1224 FUNC LOCAL DEFAULT 1 __gridxc_chkgmx_MOD_chkgmx.localalias\n+ 6: 000004c8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 7: 00000548 0 NOTYPE LOCAL DEFAULT 1 $d\n 8: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 9: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 10: 00000001 928 FUNC GLOBAL DEFAULT 1 __gridxc_chkgmx_MOD_chkgmx\n+ 10: 00000001 1224 FUNC GLOBAL DEFAULT 1 __gridxc_chkgmx_MOD_chkgmx\n 11: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_minvec_MOD_minvec\n 12: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n 13: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 14: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 15: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 16: 000003a1 144 FUNC GLOBAL DEFAULT 1 __gridxc_chkgmx_MOD_meshkcut\n+ 16: 000004c9 144 FUNC GLOBAL DEFAULT 1 __gridxc_chkgmx_MOD_meshkcut\n 17: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_reclat\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,17 +1,17 @@\n \n-Relocation section '.rel.text' at offset 0x6cc contains 14 entries:\n+Relocation section '.rel.text' at offset 0x7f0 contains 14 entries:\n Offset Info Type Sym. Value Symbol's Name\n 000000e4 00000b0a R_ARM_THM_CALL 00000000 __gridxc_minvec_MOD_minvec\n-00000372 00000c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000388 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000038c 00000e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000390 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000394 00000f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000398 00000203 R_ARM_REL32 00000000 .LC0\n-0000039c 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003ce 0000110a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n-00000412 00000c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000420 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000424 00000e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000428 00000803 R_ARM_REL32 00000000 .rodata\n-0000042c 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000049c 00000c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000004b0 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004b4 00000e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000004b8 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004bc 00000f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000004c0 00000203 R_ARM_REL32 00000000 .LC0\n+000004c4 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004f6 0000110a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n+00000544 00000c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000548 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000054c 00000e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000550 00000803 R_ARM_REL32 00000000 .rodata\n+00000554 00000d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,8 +1,7 @@\n-+*FkF!F@\n CHKGMX: K NOT IN FIRST BZ\n __gridxc_chkgmx_MOD_chkgmx.localalias\n __gridxc_chkgmx_MOD_chkgmx\n __gridxc_minvec_MOD_minvec\n __stack_chk_fail\n _GLOBAL_OFFSET_TABLE_\n __stack_chk_guard\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -3,323 +3,400 @@\n \n Disassembly of section .text:\n \n 00000000 <__gridxc_chkgmx_MOD_chkgmx>:\n __gridxc_chkgmx_MOD_chkgmx.localalias():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d13}\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3808]\t@ 0xee0\n-\tmov\tip, r2\n-\tvldr\td25, [r1, #16]\n-\tvldr\td24, [r1, #40]\t@ 0x28\n-\tmov\tr5, r3\n-\tvldr\td23, [r1, #64]\t@ 0x40\n-\tsub\tsp, #224\t@ 0xe0\n-\tvldr\ts15, [ip]\n+\tstr.w\tr0, [ip, #3648]\t@ 0xe40\n+\tvldr\ts10, [r2]\n \tmov\tr4, r0\n-\tvldr\td22, [r1]\n-\tadd\tr2, sp, #144\t@ 0x90\n-\tvldr\td17, [r1, #8]\n-\tmov\tr0, sp\n-\tvcvt.f64.s32\td16, s15\n-\tvldr\td21, [r1, #24]\n-\tvldr\td20, [r1, #32]\n-\tvldr\td19, [r1, #48]\t@ 0x30\n-\tvldr\td18, [r1, #56]\t@ 0x38\n-\tldr\tr1, [pc, #828]\t@ (388 <__gridxc_chkgmx_MOD_chkgmx+0x388>)\n-\tvmul.f64\td17, d16, d17\n-\tldr\tr3, [pc, #824]\t@ (38c <__gridxc_chkgmx_MOD_chkgmx+0x38c>)\n-\tvmul.f64\td22, d16, d22\n-\tadd\tr1, pc\n-\tvldr\ts15, [ip, #4]\n-\tvmul.f64\td16, d16, d25\n-\tvldr\td8, [pc, #788]\t@ 378 <__gridxc_chkgmx_MOD_chkgmx+0x378>\n-\tldr\tr6, [pc, #808]\t@ (390 <__gridxc_chkgmx_MOD_chkgmx+0x390>)\n-\tldr\tr3, [r1, r3]\n-\tldr.w\tr1, [ip, #8]\n+\tvldr\ts12, [r2, #4]\n+\tmov\tr5, r3\n+\tvldr\ts14, [r2, #8]\n+\tsub\tsp, #368\t@ 0x170\n+\tvcvt.f64.s32\td5, s10\n+\tvldr\td2, [r1, #64]\t@ 0x40\n+\tvcvt.f64.s32\td6, s12\n+\tvldr\td10, [r1]\n+\tvcvt.f64.s32\td7, s14\n+\tvldr\td9, [r1, #8]\n+\tvldr\td11, [r1, #16]\n+\tadd\tr2, sp, #288\t@ 0x120\n+\tvldr\td0, [r1, #24]\n+\tvmul.f64\td10, d5, d10\n+\tvldr\td1, [r1, #32]\n+\tvmul.f64\td9, d5, d9\n+\tvldr\td8, [r1, #40]\t@ 0x28\n+\tvmul.f64\td5, d5, d11\n+\tvldr\td3, [r1, #48]\t@ 0x30\n+\tvmul.f64\td0, d6, d0\n+\tvldr\td4, [r1, #56]\t@ 0x38\n+\tvmul.f64\td1, d6, d1\n+\tldr.w\tr0, [pc, #1092]\t@ 4b0 <__gridxc_chkgmx_MOD_chkgmx+0x4b0>\n+\tvmul.f64\td6, d6, d8\n+\tldr.w\tr3, [pc, #1088]\t@ 4b4 <__gridxc_chkgmx_MOD_chkgmx+0x4b4>\n+\tvmul.f64\td3, d7, d3\n+\tadd\tr0, pc\n+\tvmul.f64\td4, d7, d4\n+\tvmul.f64\td7, d7, d2\n+\tadd\tr1, sp, #216\t@ 0xd8\n+\tldr.w\tr6, [pc, #1072]\t@ 4b8 <__gridxc_chkgmx_MOD_chkgmx+0x4b8>\n+\tvmov.f64\td15, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [r0, r3]\n+\tadd\tr0, sp, #144\t@ 0x90\n \tadd\tr6, pc\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #220]\t@ 0xdc\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n \tmov.w\tr3, #0\n-\tvstr\td17, [sp, #80]\t@ 0x50\n-\tvstr\td17, [sp, #8]\n-\tvcvt.f64.s32\td17, s15\n-\tvmov\ts15, r1\n-\tvstr\td16, [sp, #88]\t@ 0x58\n-\tvstr\td16, [sp, #16]\n-\tadd\tr1, sp, #72\t@ 0x48\n-\tvcvt.f64.s32\td16, s15\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvmul.f64\td21, d17, d21\n-\tvmul.f64\td20, d17, d20\n-\tvmul.f64\td17, d17, d24\n-\tvstr\td22, [sp]\n-\tvmul.f64\td19, d16, d19\n-\tvmul.f64\td18, d16, d18\n-\tvmul.f64\td16, d16, d23\n-\tvstr\td21, [sp, #96]\t@ 0x60\n-\tvstr\td21, [sp, #24]\n-\tvstr\td20, [sp, #104]\t@ 0x68\n-\tvstr\td20, [sp, #32]\n-\tvstr\td17, [sp, #112]\t@ 0x70\n-\tvstr\td17, [sp, #40]\t@ 0x28\n-\tvstr\td19, [sp, #120]\t@ 0x78\n-\tvstr\td19, [sp, #48]\t@ 0x30\n-\tvstr\td18, [sp, #128]\t@ 0x80\n-\tvstr\td18, [sp, #56]\t@ 0x38\n-\tvstr\td16, [sp, #136]\t@ 0x88\n-\tvstr\td16, [sp, #64]\t@ 0x40\n+\tvstr\td7, [sp, #280]\t@ 0x118\n+\tvstr\td9, [sp, #224]\t@ 0xe0\n+\tvstr\td9, [sp, #152]\t@ 0x98\n+\tvstr\td5, [sp, #232]\t@ 0xe8\n+\tvstr\td5, [sp, #160]\t@ 0xa0\n+\tvstr\td0, [sp, #240]\t@ 0xf0\n+\tvstr\td0, [sp, #168]\t@ 0xa8\n+\tvstr\td1, [sp, #248]\t@ 0xf8\n+\tvstr\td1, [sp, #176]\t@ 0xb0\n+\tvstr\td6, [sp, #256]\t@ 0x100\n+\tvstr\td6, [sp, #184]\t@ 0xb8\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvstr\td3, [sp, #192]\t@ 0xc0\n+\tvstr\td4, [sp, #272]\t@ 0x110\n+\tvstr\td4, [sp, #200]\t@ 0xc8\n+\tvstr\td10, [sp, #216]\t@ 0xd8\n+\tvstr\td10, [sp, #144]\t@ 0x90\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n \tbl\t0 <__gridxc_minvec_MOD_minvec>\n R_ARM_THM_CALL\t__gridxc_minvec_MOD_minvec\n-\tvldr\td2, [sp, #72]\t@ 0x48\n+\tvldr\td7, [sp, #216]\t@ 0xd8\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tvldr\td28, [sp, #96]\t@ 0x60\n-\tvmov.f64\td22, #96\t@ 0x3f000000 0.5\n-\tvldr\td11, [sp, #120]\t@ 0x78\n-\tvldr\td1, [sp, #80]\t@ 0x50\n-\tvldr\td27, [sp, #104]\t@ 0x68\n-\tvldr\td12, [sp, #128]\t@ 0x80\n-\tvldr\td0, [sp, #88]\t@ 0x58\n-\tvldr\td26, [sp, #112]\t@ 0x70\n-\tvldr\td13, [sp, #136]\t@ 0x88\n-\tvldr\td25, [r4]\n-\tvldr\td24, [r4, #8]\n-\tvldr\td23, [r4, #16]\n+\tvldr\td9, [r4]\n+\tvldr\td13, [r4, #16]\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tvldr\td14, [r4, #8]\n+\tvstr\td9, [sp, #48]\t@ 0x30\n+\tvstr\td7, [sp, #16]\n+\tvldr\td7, [sp, #264]\t@ 0x108\n+\tvstr\td13, [sp]\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td7, [sp, #248]\t@ 0xf8\n+\tvstr\td7, [sp, #32]\n+\tvldr\td7, [sp, #272]\t@ 0x110\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td7, [sp, #232]\t@ 0xe8\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tvldr\td7, [sp, #256]\t@ 0x100\n+\tvstr\td7, [sp, #24]\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tvldr\td7, [pc, #852]\t@ 4a0 <__gridxc_chkgmx_MOD_chkgmx+0x4a0>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n \tvmov\ts15, r2\n-\tvcvt.f64.s32\td17, s15\n-\tvmul.f64\td16, d12, d17\n-\tvmul.f64\td21, d11, d17\n-\tvmul.f64\td17, d13, d17\n-\tvsub.f64\td20, d16, d1\n-\tvsub.f64\td19, d21, d2\n-\tvsub.f64\td18, d17, d0\n-\tvsub.f64\td7, d16, d27\n-\tvsub.f64\td6, d21, d28\n-\tvadd.f64\td31, d1, d16\n-\tvadd.f64\td30, d2, d21\n-\tvadd.f64\td29, d0, d17\n-\tvsub.f64\td3, d20, d27\n-\tvsub.f64\td4, d19, d28\n-\tvsub.f64\td5, d18, d26\n-\tvmul.f64\td9, d3, d3\n-\tvmul.f64\td3, d24, d3\n-\tvfma.f64\td9, d4, d4\n-\tvfma.f64\td3, d25, d4\n-\tvsub.f64\td4, d17, d26\n-\tvfma.f64\td9, d5, d5\n-\tvfma.f64\td3, d23, d5\n-\tvmul.f64\td5, d7, d7\n-\tvfma.f64\td5, d6, d6\n-\tvfma.f64\td5, d4, d4\n-\tvmov.f64\td10, d3\n-\tvsqrt.f64\td3, d9\n-\tvmul.f64\td9, d24, d7\n-\tvfma.f64\td9, d6, d25\n-\tvsub.f64\td7, d30, d28\n-\tvsqrt.f64\td6, d5\n-\tvfma.f64\td9, d4, d23\n-\tvdiv.f64\td5, d10, d3\n-\tvdiv.f64\td4, d9, d6\n-\tvfnms.f64\td5, d3, d22\n-\tvfnms.f64\td4, d6, d22\n-\tvsub.f64\td6, d29, d26\n-\tvmov.f64\td10, d5\n-\tvsub.f64\td5, d31, d27\n-\tvmov.f64\td9, d4\n-\tvmul.f64\td4, d5, d5\n-\tvmul.f64\td5, d24, d5\n-\tvfma.f64\td4, d7, d7\n-\tvfma.f64\td5, d25, d7\n-\tvmul.f64\td7, d20, d20\n-\tvfma.f64\td7, d19, d19\n-\tvfma.f64\td4, d6, d6\n-\tvfma.f64\td5, d23, d6\n-\tvfma.f64\td7, d18, d18\n-\tvmov.f64\td3, d5\n-\tvsqrt.f64\td6, d7\n-\tvmul.f64\td7, d24, d20\n-\tvsqrt.f64\td5, d4\n-\tvfma.f64\td7, d25, d19\n-\tvfma.f64\td7, d23, d18\n-\tvdiv.f64\td4, d3, d5\n-\tvdiv.f64\td3, d7, d6\n-\tvfnms.f64\td4, d5, d22\n-\tvfnms.f64\td3, d6, d22\n-\tvminnm.f64\td7, d3, d9\n-\tvminnm.f64\td7, d7, d10\n-\tvminnm.f64\td7, d7, d4\n-\tvminnm.f64\td7, d7, d8\n+\tvldr\td11, [sp, #16]\n+\tvldr\td12, [sp, #96]\t@ 0x60\n+\tvcvt.f64.s32\td8, s15\n+\tvldr\td7, [sp, #104]\t@ 0x68\n+\tvldr\td4, [sp, #32]\n+\tvldr\td10, [sp, #24]\n+\tvldr\td13, [sp, #112]\t@ 0x70\n+\tvmul.f64\td5, d7, d8\n+\tvldr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td9, [sp, #128]\t@ 0x80\n+\tvmul.f64\td1, d7, d8\n+\tvldr\td7, [sp, #136]\t@ 0x88\n+\tvsub.f64\td0, d5, d12\n+\tvsub.f64\td6, d5, d11\n+\tvstr\td5, [sp, #64]\t@ 0x40\n+\tvadd.f64\td5, d12, d5\n+\tvmul.f64\td8, d7, d8\n+\tvldr\td12, [sp, #48]\t@ 0x30\n+\tvsub.f64\td3, d1, d4\n+\tvsub.f64\td7, d1, d13\n+\tvstr\td1, [sp, #56]\t@ 0x38\n+\tvadd.f64\td13, d13, d1\n+\tvstr\td5, [sp, #8]\n+\tvmul.f64\td5, d6, d6\n+\tvsub.f64\td4, d8, d10\n+\tvmul.f64\td6, d6, d12\n+\tvmla.f64\td5, d3, d3\n+\tvmla.f64\td6, d14, d3\n+\tvldr\td3, [sp]\n+\tvsub.f64\td2, d8, d9\n+\tvmla.f64\td5, d4, d4\n+\tvmla.f64\td6, d4, d3\n+\tvmul.f64\td3, d14, d7\n+\tvmla.f64\td3, d12, d0\n+\tvsqrt.f64\td4, d5\n+\tvdiv.f64\td5, d6, d4\n+\tvmul.f64\td6, d7, d7\n+\tvmla.f64\td6, d0, d0\n+\tvmla.f64\td6, d2, d2\n+\tvsqrt.f64\td1, d6\n+\tvnmls.f64\td5, d4, d15\n+\tvldr\td4, [sp, #32]\n+\tvsub.f64\td6, d7, d4\n+\tvstr\td6, [sp, #80]\t@ 0x50\n+\tvldr\td6, [sp, #8]\n+\tvstr\td5, [sp, #88]\t@ 0x58\n+\tvsub.f64\td5, d0, d11\n+\tvsub.f64\td6, d6, d11\n+\tvadd.f64\td11, d9, d8\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvsub.f64\td1, d2, d10\n+\tvsub.f64\td10, d13, d4\n+\tvldr\td4, [sp]\n+\tvldr\td9, [sp, #72]\t@ 0x48\n+\tvmla.f64\td3, d4, d2\n+\tvdiv.f64\td4, d3, d9\n+\tvldr\td3, [sp, #88]\t@ 0x58\n+\tvnmls.f64\td4, d9, d15\n+\tvldr\td9, [sp, #80]\t@ 0x50\n+\tvcmpe.f64\td4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td4, d3\n+\tvmul.f64\td3, d5, d5\n+\tvmla.f64\td3, d9, d9\n+\tvmul.f64\td5, d12, d5\n+\tvmla.f64\td5, d14, d9\n+\tvldr\td9, [sp]\n+\tvmla.f64\td3, d1, d1\n+\tvmla.f64\td5, d9, d1\n+\tvsqrt.f64\td1, d3\n+\tvdiv.f64\td3, d5, d1\n+\tvmul.f64\td5, d6, d6\n+\tvmla.f64\td5, d10, d10\n+\tvmul.f64\td6, d12, d6\n+\tvmla.f64\td6, d14, d10\n+\tvnmls.f64\td3, d1, d15\n+\tvcmpe.f64\td4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tls\n+\tvmovls.f64\td3, d4\n+\tvldr\td4, [sp, #24]\n+\tvsub.f64\td4, d11, d4\n+\tvmla.f64\td5, d4, d4\n+\tvmla.f64\td6, d9, d4\n+\tvsqrt.f64\td4, d5\n+\tvdiv.f64\td5, d6, d4\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvnmls.f64\td5, d4, d15\n+\tvcmpe.f64\td3, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td3, d5\n+\tvcmpe.f64\td3, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td3, d6\n \tcmp\tr2, #0\n-\tbne.w\t348 <__gridxc_chkgmx_MOD_chkgmx+0x348>\n-\tvadd.f64\td20, d27, d20\n-\tvadd.f64\td19, d28, d19\n-\tvmul.f64\td8, d31, d31\n-\tvadd.f64\td18, d26, d18\n-\tvfma.f64\td8, d30, d30\n-\tvadd.f64\td16, d27, d16\n-\tvadd.f64\td21, d28, d21\n-\tvadd.f64\td6, d27, d31\n-\tvmul.f64\td3, d20, d20\n-\tvmul.f64\td20, d20, d24\n-\tvfma.f64\td20, d19, d25\n-\tvfma.f64\td3, d19, d19\n-\tvfma.f64\td8, d29, d29\n-\tvmul.f64\td31, d24, d31\n-\tvadd.f64\td5, d28, d30\n-\tvfma.f64\td31, d25, d30\n-\tvmul.f64\td4, d16, d16\n-\tvadd.f64\td17, d26, d17\n-\tvfma.f64\td3, d18, d18\n-\tvfma.f64\td4, d21, d21\n-\tvadd.f64\td19, d26, d29\n-\tvmul.f64\td16, d16, d24\n-\tvfma.f64\td31, d23, d29\n-\tvfma.f64\td16, d21, d25\n+\tbne.w\t460 <__gridxc_chkgmx_MOD_chkgmx+0x460>\n+\tvldr\td9, [sp, #24]\n \tadds\tr2, #1\n-\tvfma.f64\td4, d17, d17\n+\tvldr\td6, [sp, #16]\n+\tvldr\td10, [sp, #32]\n+\tvadd.f64\td4, d9, d2\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvadd.f64\td5, d6, d0\n+\tvadd.f64\td0, d9, d8\n+\tvldr\td8, [sp, #8]\n+\tvadd.f64\td7, d10, d7\n+\tvadd.f64\td6, d6, d2\n+\tvldr\td2, [sp, #56]\t@ 0x38\n+\tvldr\td12, [sp, #48]\t@ 0x30\n+\tvadd.f64\td1, d10, d2\n+\tvmul.f64\td2, d13, d13\n+\tvmla.f64\td2, d8, d8\n+\tvadd.f64\td10, d10, d13\n+\tvmla.f64\td2, d11, d11\n+\tvsqrt.f64\td8, d2\n+\tvmul.f64\td2, d5, d5\n+\tvmla.f64\td2, d7, d7\n+\tvmul.f64\td5, d5, d12\n+\tvmla.f64\td5, d7, d14\n+\tvldr\td7, [sp]\n+\tvmla.f64\td2, d4, d4\n+\tvmla.f64\td5, d4, d7\n+\tvsqrt.f64\td7, d2\n+\tvdiv.f64\td4, d5, d7\n+\tvmov.f64\td5, d4\n+\tvldr\td4, [sp]\n+\tvnmls.f64\td5, d7, d15\n+\tvmul.f64\td7, d6, d6\n+\tvmla.f64\td7, d1, d1\n+\tvmul.f64\td6, d6, d12\n+\tvmla.f64\td6, d1, d14\n+\tvmla.f64\td7, d0, d0\n+\tvmla.f64\td6, d0, d4\n+\tvsqrt.f64\td4, d7\n+\tvldr\td7, [sp, #8]\n+\tvdiv.f64\td2, d6, d4\n+\tvldr\td6, [sp, #8]\n+\tvnmls.f64\td2, d4, d15\n+\tvmul.f64\td4, d14, d13\n+\tvmla.f64\td4, d12, d6\n+\tvldr\td6, [sp, #16]\n+\tvadd.f64\td7, d6, d7\n+\tvldr\td6, [sp]\n+\tvmla.f64\td4, d6, d11\n+\tvadd.f64\td6, d9, d11\n+\tvdiv.f64\td1, d4, d8\n+\tvmul.f64\td4, d7, d7\n+\tvmla.f64\td4, d10, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d10, d14\n+\tvmla.f64\td4, d6, d6\n+\tvnmls.f64\td1, d8, d15\n+\tvcmpe.f64\td5, d1\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td5, d1\n+\tvcmpe.f64\td5, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td5, d3\n+\tvldr\td3, [sp]\n+\tvmla.f64\td7, d6, d3\n+\tvsqrt.f64\td6, d4\n+\tvcmpe.f64\td5, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td5, d2\n+\tvdiv.f64\td4, d7, d6\n+\tvnmls.f64\td4, d6, d15\n+\tvcmpe.f64\td5, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\thi\n+\tvmovhi.f64\td7, d4\n+\tvmovls.f64\td7, d5\n \tcmp\tr2, #2\n-\tvmov.f64\td30, d20\n-\tvmul.f64\td20, d6, d6\n-\tvfma.f64\td20, d5, d5\n-\tvmul.f64\td6, d6, d24\n-\tvfma.f64\td16, d17, d23\n-\tvfma.f64\td6, d5, d25\n-\tvsqrt.f64\td21, d3\n-\tvmov.f64\td29, d30\n-\tvfma.f64\td29, d18, d23\n-\tvfma.f64\td20, d19, d19\n-\tvsqrt.f64\td18, d8\n-\tvfma.f64\td6, d19, d23\n-\tvsqrt.f64\td17, d4\n-\tvsqrt.f64\td19, d20\n-\tvdiv.f64\td30, d29, d21\n-\tvdiv.f64\td20, d31, d18\n-\tvdiv.f64\td29, d16, d17\n-\tvdiv.f64\td16, d6, d19\n-\tvfnms.f64\td30, d21, d22\n-\tvfnms.f64\td20, d18, d22\n-\tvfnms.f64\td29, d17, d22\n-\tvfnms.f64\td16, d19, d22\n-\tvminnm.f64\td30, d30, d20\n-\tvminnm.f64\td30, d30, d7\n-\tvminnm.f64\td29, d29, d30\n-\tvminnm.f64\td8, d16, d29\n-\tbne.w\t120 <__gridxc_chkgmx_MOD_chkgmx+0x120>\n-\tvcmpe.f64\td8, #0.0\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tbne.w\t150 <__gridxc_chkgmx_MOD_chkgmx+0x150>\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t312 <__gridxc_chkgmx_MOD_chkgmx+0x312>\n-\tldr\tr3, [pc, #140]\t@ (394 <__gridxc_chkgmx_MOD_chkgmx+0x394>)\n+\tbpl.n\t426 <__gridxc_chkgmx_MOD_chkgmx+0x426>\n+\tldr\tr3, [pc, #160]\t@ (4bc <__gridxc_chkgmx_MOD_chkgmx+0x4bc>)\n \tmovs\tr1, #25\n-\tldr\tr0, [pc, #140]\t@ (398 <__gridxc_chkgmx_MOD_chkgmx+0x398>)\n+\tldr\tr0, [pc, #160]\t@ (4c0 <__gridxc_chkgmx_MOD_chkgmx+0x4c0>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvldr\td16, [pc, #108]\t@ 380 <__gridxc_chkgmx_MOD_chkgmx+0x380>\n-\tvfma.f64\td16, d8, d8\n-\tvldr\td17, [r5]\n-\tvcmpe.f64\td17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t32c <__gridxc_chkgmx_MOD_chkgmx+0x32c>\n-\tvstr\td16, [r5]\n-\tldr\tr2, [pc, #108]\t@ (39c <__gridxc_chkgmx_MOD_chkgmx+0x39c>)\n-\tldr\tr3, [pc, #92]\t@ (38c <__gridxc_chkgmx_MOD_chkgmx+0x38c>)\n+\tvldr\td7, [pc, #128]\t@ 4a8 <__gridxc_chkgmx_MOD_chkgmx+0x4a8>\n+\tvldr\td5, [sp, #40]\t@ 0x28\n+\tvldr\td6, [r5]\n+\tvnmls.f64\td7, d5, d5\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.n\t444 <__gridxc_chkgmx_MOD_chkgmx+0x444>\n+\tvstr\td7, [r5]\n+\tldr\tr2, [pc, #124]\t@ (4c4 <__gridxc_chkgmx_MOD_chkgmx+0x4c4>)\n+\tldr\tr3, [pc, #108]\t@ (4b4 <__gridxc_chkgmx_MOD_chkgmx+0x4b4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #220]\t@ 0xdc\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t372 <__gridxc_chkgmx_MOD_chkgmx+0x372>\n-\tadd\tsp, #224\t@ 0xe0\n-\tvpop\t{d8-d13}\n+\tbne.n\t49c <__gridxc_chkgmx_MOD_chkgmx+0x49c>\n+\tadd\tsp, #368\t@ 0x170\n+\tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvmul.f64\td6, d16, d16\n-\tvfma.f64\td6, d21, d21\n-\tvfma.f64\td6, d17, d17\n+\tvldr\td5, [sp, #56]\t@ 0x38\n+\tvldr\td1, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d5, d5\n+\tvmla.f64\td6, d1, d1\n+\tvmla.f64\td6, d8, d8\n \tvsqrt.f64\td4, d6\n-\tvmul.f64\td6, d24, d16\n-\tvfma.f64\td6, d25, d21\n-\tvfma.f64\td6, d23, d17\n+\tvmul.f64\td6, d14, d5\n+\tvmla.f64\td6, d12, d1\n+\tvmla.f64\td6, d9, d8\n \tvdiv.f64\td5, d6, d4\n-\tvfnms.f64\td5, d4, d22\n-\tvminnm.f64\td7, d7, d5\n-\tb.n\t226 <__gridxc_chkgmx_MOD_chkgmx+0x226>\n+\tvnmls.f64\td5, d4, d15\n+\tvcmpe.f64\td3, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td3, d5\n+\tb.n\t2d6 <__gridxc_chkgmx_MOD_chkgmx+0x2d6>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \t.word\t0x78b58c40\n \t.word\t0x4415af1d\n \t.word\t0xe2308c3a\n-\t.word\t0xbe45798e\n-\t.word\t0x0000032e\n+\t.word\t0x3e45798e\n+\t.word\t0x00000432\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000320\n+\t.word\t0x00000422\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000008a\n+\t.word\t0x0000009e\n R_ARM_REL32\t.LC0\n-\t.word\t0x00000068\n+\t.word\t0x00000078\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000003a0 <__gridxc_chkgmx_MOD_meshkcut>:\n+000004c8 <__gridxc_chkgmx_MOD_meshkcut>:\n __gridxc_chkgmx_MOD_meshkcut():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3968]\t@ 0xf80\n-\tldr.w\tip, [pc, #112]\t@ 420 <__gridxc_chkgmx_MOD_meshkcut+0x80>\n+\tldr.w\tip, [pc, #112]\t@ 548 <__gridxc_chkgmx_MOD_meshkcut+0x80>\n \tsub\tsp, #116\t@ 0x74\n-\tldr\tr3, [pc, #108]\t@ (424 <__gridxc_chkgmx_MOD_meshkcut+0x84>)\n+\tldr\tr3, [pc, #108]\t@ (54c <__gridxc_chkgmx_MOD_meshkcut+0x84>)\n \tadd\tr4, sp, #32\n \tadd\tip, pc\n-\tldr\tr2, [pc, #108]\t@ (428 <__gridxc_chkgmx_MOD_meshkcut+0x88>)\n+\tldr\tr2, [pc, #108]\t@ (550 <__gridxc_chkgmx_MOD_meshkcut+0x88>)\n \tmov\tr5, r1\n \tmov\tr1, r4\n \tadd\tr2, pc\n \tldr.w\tr3, [ip, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #108]\t@ 0x6c\n \tmov.w\tr3, #0\n \tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n \tadd\tr0, sp, #8\n-\tvldr\td18, [pc, #60]\t@ 418 <__gridxc_chkgmx_MOD_meshkcut+0x78>\n+\tmovs\tr3, #0\n \tmov\tr2, r5\n-\tmov\tr3, sp\n \tmov\tr1, r4\n-\tvst1.8\t{d16-d17}, [r0 :64]\n-\tvstr\td16, [r0, #16]\n-\tvstr\td18, [sp]\n+\tstr\tr3, [sp, #8]\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n+\tstrd\tr3, r3, [r0, #4]\n+\tmovw\tr5, #65535\t@ 0xffff\n+\tmovt\tr5, #32751\t@ 0x7fef\n+\tstrd\tr3, r3, [r0, #12]\n+\tstr\tr3, [r0, #20]\n+\tmov\tr3, sp\n+\tstrd\tr4, r5, [sp]\n \tbl\t0 <__gridxc_chkgmx_MOD_chkgmx>\n-\tldr\tr2, [pc, #56]\t@ (42c <__gridxc_chkgmx_MOD_meshkcut+0x8c>)\n-\tldr\tr3, [pc, #44]\t@ (424 <__gridxc_chkgmx_MOD_meshkcut+0x84>)\n+\tldr\tr2, [pc, #44]\t@ (554 <__gridxc_chkgmx_MOD_meshkcut+0x8c>)\n+\tldr\tr3, [pc, #36]\t@ (54c <__gridxc_chkgmx_MOD_meshkcut+0x84>)\n \tadd\tr2, pc\n-\tvldr\td16, [sp]\n+\tvldr\td7, [sp]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #108]\t@ 0x6c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t412 <__gridxc_chkgmx_MOD_meshkcut+0x72>\n-\tvsqrt.f64\td0, d16\n+\tbne.n\t544 <__gridxc_chkgmx_MOD_meshkcut+0x7c>\n+\tvsqrt.f64\td0, d7\n \tadd\tsp, #116\t@ 0x74\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0xffffffff\n-\t.word\t0x7fefffff\n \t.word\t0x00000064\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000064\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000032\n+\t.word\t0x00000028\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "debugxc.F90.o", "source2": "debugxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 1716 (bytes into file)\n+ Start of section headers: 1700 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x6b4:\n+There are 11 section headers, starting at offset 0x6a4:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000190 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 000584 0000d0 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 0001c8 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 0001c8 000024 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 0001c8 000059 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 000221 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 000221 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 000254 0001a0 10 9 12 4\n- [ 9] .strtab STRTAB 00000000 0003f4 00018e 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 000654 00005f 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000034 000188 00 AX 0 0 4\n+ [ 2] .rel.text REL 00000000 000574 0000d0 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 0001bc 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 0001bc 000024 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0001bc 000059 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 000215 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 000215 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 000244 0001a0 10 9 12 4\n+ [ 9] .strtab STRTAB 00000000 0003e4 00018e 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 000644 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -15,15 +15,15 @@\n 11: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n 12: 00000001 116 FUNC GLOBAL DEFAULT 1 __gridxc_debugxc_MOD_closedebugoutputfile\n 13: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_close\n 14: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n 15: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 16: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 17: 00000020 4 OBJECT GLOBAL DEFAULT 4 __gridxc_debugxc_MOD_udebug\n- 18: 00000075 284 FUNC GLOBAL DEFAULT 1 __gridxc_debugxc_MOD_setdebugoutputunit\n+ 18: 00000075 276 FUNC GLOBAL DEFAULT 1 __gridxc_debugxc_MOD_setdebugoutputunit\n 19: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n 20: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n 21: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n 22: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n 23: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_io_MOD_io_assign\n 24: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_open\n 25: 00000000 32 OBJECT GLOBAL HIDDEN 4 __gridxc_debugxc_MOD_filename\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,29 +1,29 @@\n \n-Relocation section '.rel.text' at offset 0x584 contains 26 entries:\n+Relocation section '.rel.text' at offset 0x574 contains 26 entries:\n Offset Info Type Sym. Value Symbol's Name\n 0000003c 00000d0a R_ARM_THM_CALL 00000000 _gfortran_st_close\n 00000058 00000e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n 0000005c 00000303 R_ARM_REL32 00000000 .LC0\n 00000060 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000064 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000068 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 0000006c 0000111a R_ARM_GOT_BREL 00000020 __gridxc_debugxc_MOD_udebug\n 00000070 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000000e6 0000130a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000000f2 0000140a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000000fc 0000150a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00000108 0000140a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000010e 0000160a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000114 0000170a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_assign\n-00000136 0000180a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00000156 00000e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000000ea 0000130a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000000f6 0000140a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000100 0000150a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+0000010c 0000140a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000112 0000160a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000118 0000170a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_assign\n+0000013a 0000180a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+0000015a 00000e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000160 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000164 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000168 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000016c 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000170 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000174 0000111a R_ARM_GOT_BREL 00000020 __gridxc_debugxc_MOD_udebug\n-00000178 00000303 R_ARM_REL32 00000000 .LC0\n-0000017c 00000103 R_ARM_REL32 00000000 .bss\n-00000180 00000603 R_ARM_REL32 0000003c .LC1\n-00000184 00000703 R_ARM_REL32 00000048 .LC2\n-00000188 00000803 R_ARM_REL32 00000054 .LC3\n-0000018c 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000016c 0000111a R_ARM_GOT_BREL 00000020 __gridxc_debugxc_MOD_udebug\n+00000170 00000303 R_ARM_REL32 00000000 .LC0\n+00000174 00000103 R_ARM_REL32 00000000 .bss\n+00000178 00000603 R_ARM_REL32 0000003c .LC1\n+0000017c 00000703 R_ARM_REL32 00000048 .LC2\n+00000180 00000803 R_ARM_REL32 00000054 .LC3\n+00000184 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,10 +1,10 @@\n JAXhF\th\t\n-}8I|D8K8J{DaX\th\n-&IZF FyD\n+}6I|D6K6J{DaX\th\n+#IZF FyD\n /build/reproducible-path/libgridxc-2.0.1/src/debugxc.F90\n (a,i0,a)\n debugXC.\n __gridxc_debugxc_MOD_closedebugoutputfile\n _gfortran_st_close\n __stack_chk_fail\n _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -59,64 +59,65 @@\n \n 00000074 <__gridxc_debugxc_MOD_setdebugoutputunit>:\n __gridxc_debugxc_MOD_setdebugoutputunit():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3520]\t@ 0xdc0\n-\tldr\tr4, [pc, #224]\t@ (168 <__gridxc_debugxc_MOD_setdebugoutputunit+0xf4>)\n+\tldr\tr4, [pc, #216]\t@ (160 <__gridxc_debugxc_MOD_setdebugoutputunit+0xec>)\n \tsub.w\tsp, sp, #540\t@ 0x21c\n-\tldr\tr1, [pc, #224]\t@ (16c <__gridxc_debugxc_MOD_setdebugoutputunit+0xf8>)\n+\tldr\tr1, [pc, #216]\t@ (164 <__gridxc_debugxc_MOD_setdebugoutputunit+0xf0>)\n \tadd\tr4, pc\n-\tldr\tr3, [pc, #224]\t@ (170 <__gridxc_debugxc_MOD_setdebugoutputunit+0xfc>)\n-\tldr\tr2, [pc, #224]\t@ (174 <__gridxc_debugxc_MOD_setdebugoutputunit+0x100>)\n+\tldr\tr3, [pc, #216]\t@ (168 <__gridxc_debugxc_MOD_setdebugoutputunit+0xf4>)\n+\tldr\tr2, [pc, #216]\t@ (16c <__gridxc_debugxc_MOD_setdebugoutputunit+0xf8>)\n \tadd\tr3, pc\n \tldr\tr1, [r4, r1]\n \tldr\tr1, [r1, #0]\n \tstr\tr1, [sp, #532]\t@ 0x214\n \tmov.w\tr1, #0\n \tldr\tr5, [r3, r2]\n \tldr\tr3, [r5, #0]\n \tcmp\tr3, #0\n-\tbgt.n\t13a <__gridxc_debugxc_MOD_setdebugoutputunit+0xc6>\n-\tldr\tr7, [pc, #208]\t@ (178 <__gridxc_debugxc_MOD_setdebugoutputunit+0x104>)\n+\tbgt.n\t13e <__gridxc_debugxc_MOD_setdebugoutputunit+0xca>\n+\tldr\tr7, [pc, #200]\t@ (170 <__gridxc_debugxc_MOD_setdebugoutputunit+0xfc>)\n \tadd\tr4, sp, #184\t@ 0xb8\n-\tvldr\td16, [pc, #180]\t@ 160 <__gridxc_debugxc_MOD_setdebugoutputunit+0xec>\n \tmovs\tr3, #42\t@ 0x2a\n+\tldr.w\tsl, [pc, #196]\t@ 174 <__gridxc_debugxc_MOD_setdebugoutputunit+0x100>\n \tadd\tr7, pc\n-\tldr.w\tsl, [pc, #200]\t@ 17c <__gridxc_debugxc_MOD_setdebugoutputunit+0x108>\n \tstrd\tr7, r3, [sp, #192]\t@ 0xc0\n+\tldr\tr3, [pc, #192]\t@ (178 <__gridxc_debugxc_MOD_setdebugoutputunit+0x104>)\n \tmov\tr6, r0\n-\tldr\tr3, [pc, #192]\t@ (180 <__gridxc_debugxc_MOD_setdebugoutputunit+0x10c>)\n \tmov\tr0, r4\n-\tvstr\td16, [sp, #184]\t@ 0xb8\n+\tmov.w\tr2, #20480\t@ 0x5000\n \tadd\tsl, pc\n \tadd\tr3, pc\n \tmov.w\tr9, #32\n-\tstr\tr3, [sp, #236]\t@ 0xec\n \tmov.w\tr8, #0\n \tmov.w\tfp, #8\n+\tstr\tr3, [sp, #236]\t@ 0xec\n \tstr.w\tsl, [sp, #252]\t@ 0xfc\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr.w\tr9, [sp, #256]\t@ 0x100\n+\tstrd\tr2, r3, [sp, #184]\t@ 0xb8\n \tstr.w\tr8, [sp, #232]\t@ 0xe8\n \tstr.w\tfp, [sp, #240]\t@ 0xf0\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #152]\t@ (184 <__gridxc_debugxc_MOD_setdebugoutputunit+0x110>)\n+\tldr\tr1, [pc, #140]\t@ (17c <__gridxc_debugxc_MOD_setdebugoutputunit+0x108>)\n \tmov\tr2, fp\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr1, r6\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tldr\tr1, [pc, #132]\t@ (188 <__gridxc_debugxc_MOD_setdebugoutputunit+0x114>)\n+\tldr\tr1, [pc, #120]\t@ (180 <__gridxc_debugxc_MOD_setdebugoutputunit+0x10c>)\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n@@ -132,44 +133,41 @@\n \tmovs\tr3, #47\t@ 0x2f\n \tstr.w\tsl, [r0, #44]\t@ 0x2c\n \tstr.w\tr9, [r0, #40]\t@ 0x28\n \tstr.w\tr8, [r0, #164]\t@ 0xa4\n \tstr\tr3, [r0, #12]\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tldr\tr2, [pc, #80]\t@ (18c <__gridxc_debugxc_MOD_setdebugoutputunit+0x118>)\n-\tldr\tr3, [pc, #44]\t@ (16c <__gridxc_debugxc_MOD_setdebugoutputunit+0xf8>)\n+\tldr\tr2, [pc, #68]\t@ (184 <__gridxc_debugxc_MOD_setdebugoutputunit+0x110>)\n+\tldr\tr3, [pc, #32]\t@ (164 <__gridxc_debugxc_MOD_setdebugoutputunit+0xf0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #532]\t@ 0x214\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t156 <__gridxc_debugxc_MOD_setdebugoutputunit+0xe2>\n+\tbne.n\t15a <__gridxc_debugxc_MOD_setdebugoutputunit+0xe6>\n \tadd.w\tsp, sp, #540\t@ 0x21c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\tnop.w\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x000000d8\n+\t.word\t0x000000d0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000da\n+\t.word\t0x000000d2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_debugxc_MOD_udebug\n-\t.word\t0x000000c4\n+\t.word\t0x000000bc\n R_ARM_REL32\t.LC0\n-\t.word\t0x000000b4\n+\t.word\t0x000000b0\n R_ARM_REL32\t.bss\n-\t.word\t0x000000b6\n+\t.word\t0x000000b2\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000090\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000007e\n+\t.word\t0x00000072\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000004a\n+\t.word\t0x0000003e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "fft3d.F90.o", "source2": "fft3d.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 5460 (bytes into file)\n+ Start of section headers: 5336 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x1554:\n+There are 12 section headers, starting at offset 0x14d8:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000b78 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 00129c 000250 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 000bb0 000030 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 000be0 0000d0 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 000be0 0000bf 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 000ca0 000008 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 000ca8 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000ca8 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 000cdc 000320 10 10 30 4\n- [10] .strtab STRTAB 00000000 000ffc 0002a0 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 0014ec 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000034 000b54 00 AX 0 0 4\n+ [ 2] .rel.text REL 00000000 001230 000240 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 000b88 000030 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 000bb8 0000cc 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 000bb8 0000bf 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 000c78 000008 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 000c80 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000c80 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 000cb0 0002e0 10 10 26 4\n+ [10] .strtab STRTAB 00000000 000f90 0002a0 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 001470 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,53 +1,49 @@\n \n-Symbol table '.symtab' contains 50 entries:\n+Symbol table '.symtab' contains 46 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 5: 00000008 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 6: 0000003c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 7: 00000068 0 NOTYPE LOCAL DEFAULT 5 .LC4\n 8: 00000074 0 NOTYPE LOCAL DEFAULT 5 .LC6\n 9: 00000094 0 NOTYPE LOCAL DEFAULT 5 .LC7\n 10: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 11: 000003d8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 12: 00000414 0 NOTYPE LOCAL DEFAULT 1 $t\n- 13: 000007b8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 14: 000007d8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 15: 00000b3c 0 NOTYPE LOCAL DEFAULT 1 $d\n- 16: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 17: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 18: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 19: 00000000 12 OBJECT LOCAL DEFAULT 3 adistr.6\n- 20: 0000000c 4 OBJECT LOCAL DEFAULT 3 mydistr.7\n- 21: 00000010 4 OBJECT LOCAL DEFAULT 3 io2my.5\n- 22: 00000014 4 OBJECT LOCAL DEFAULT 3 my2io.4\n- 23: 00000018 12 OBJECT LOCAL DEFAULT 3 my2a.3\n- 24: 00000024 12 OBJECT LOCAL DEFAULT 3 a2my.2\n- 25: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 26: 00000000 12 OBJECT LOCAL DEFAULT 4 oldmesh.9\n- 27: 00000010 48 OBJECT LOCAL DEFAULT 4 trigs.8\n- 28: 00000040 72 OBJECT LOCAL DEFAULT 4 mydat.1\n- 29: 00000088 72 OBJECT LOCAL DEFAULT 4 adat.0\n- 30: 00000001 2936 FUNC GLOBAL DEFAULT 1 __gridxc_fft3d_MOD_fft3d\n- 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_mymeshbox\n- 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_associatemeshtask\n- 33: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_redistributemeshdata\n- 34: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n- 35: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gpfa_core_dp_MOD_gpfa_\n- 36: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n- 37: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 38: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 39: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 40: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_start\n- 41: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 42: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_associated\n- 43: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n- 44: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fft_gpfa_MOD_setgpfa_check\n- 45: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n- 46: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_copymeshdata\n- 47: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n- 48: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 49: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_stop\n+ 11: 00000ad4 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 12: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 13: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 14: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 15: 00000000 12 OBJECT LOCAL DEFAULT 3 adistr.6\n+ 16: 0000000c 4 OBJECT LOCAL DEFAULT 3 mydistr.7\n+ 17: 00000010 4 OBJECT LOCAL DEFAULT 3 io2my.5\n+ 18: 00000014 4 OBJECT LOCAL DEFAULT 3 my2io.4\n+ 19: 00000018 12 OBJECT LOCAL DEFAULT 3 my2a.3\n+ 20: 00000024 12 OBJECT LOCAL DEFAULT 3 a2my.2\n+ 21: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 22: 00000000 12 OBJECT LOCAL DEFAULT 4 oldmesh.9\n+ 23: 0000000c 48 OBJECT LOCAL DEFAULT 4 trigs.8\n+ 24: 0000003c 72 OBJECT LOCAL DEFAULT 4 mydat.1\n+ 25: 00000084 72 OBJECT LOCAL DEFAULT 4 adat.0\n+ 26: 00000001 2900 FUNC GLOBAL DEFAULT 1 __gridxc_fft3d_MOD_fft3d\n+ 27: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_mymeshbox\n+ 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_associatemeshtask\n+ 29: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_redistributemeshdata\n+ 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n+ 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gpfa_core_dp_MOD_gpfa_\n+ 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n+ 33: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 34: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_associated\n+ 35: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d2\n+ 36: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fft_gpfa_MOD_setgpfa_check\n+ 37: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n+ 38: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_copymeshdata\n+ 39: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n+ 40: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 41: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 42: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 43: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_start\n+ 44: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 45: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_gridxc_timer_stop\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,77 +1,75 @@\n \n-Relocation section '.rel.text' at offset 0x129c contains 74 entries:\n+Relocation section '.rel.text' at offset 0x1230 contains 72 entries:\n Offset Info Type Sym. Value Symbol's Name\n-000000b4 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-00000142 0000200a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00000154 0000200a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-0000016a 0000200a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00000174 0000200a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000001e8 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-000001f2 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-0000022e 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-000002dc 0000220a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000318 0000230a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n-00000326 0000240a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-0000032c 0000250a R_ARM_THM_CALL 00000000 free\n-00000354 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-00000362 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-0000039e 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-000003e0 00002619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003e4 00002619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003e8 0000271a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000003ec 0000281a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_start\n-000003f0 00000403 R_ARM_REL32 00000000 .LC0\n-000003f4 0000291a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000003f8 00000603 R_ARM_REL32 0000003c .LC2\n-000003fc 00000203 R_ARM_REL32 00000000 .bss\n-00000400 00000103 R_ARM_REL32 00000000 .data\n-00000404 00000203 R_ARM_REL32 00000000 .bss\n-00000408 00001003 R_ARM_REL32 00000000 .rodata\n-0000040c 00000103 R_ARM_REL32 00000000 .data\n-00000410 00000203 R_ARM_REL32 00000000 .bss\n-00000418 0000240a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-0000041e 0000250a R_ARM_THM_CALL 00000000 free\n-000004ea 0000220a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-0000050c 0000230a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n-0000054a 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-0000055a 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-0000058c 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-00000650 0000220a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000678 0000230a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n-00000686 0000240a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-0000068c 0000250a R_ARM_THM_CALL 00000000 free\n-000006be 0000210a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n-00000708 00002a0a R_ARM_THM_CALL 00000000 _gfortran_associated\n-000007c0 00001003 R_ARM_REL32 00000000 .rodata\n-000007c4 00000103 R_ARM_REL32 00000000 .data\n-000007c8 00000203 R_ARM_REL32 00000000 .bss\n-000007cc 00001003 R_ARM_REL32 00000000 .rodata\n-000007d0 00000203 R_ARM_REL32 00000000 .bss\n-000007d4 00000103 R_ARM_REL32 00000000 .data\n-000007e8 00002a0a R_ARM_THM_CALL 00000000 _gfortran_associated\n-0000085e 00002a0a R_ARM_THM_CALL 00000000 _gfortran_associated\n-0000091e 00002b0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000097c 0000220a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000988 00002c0a R_ARM_THM_CALL 00000000 __gridxc_fft_gpfa_MOD_setgpfa_check\n-00000996 0000240a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-0000099c 0000250a R_ARM_THM_CALL 00000000 free\n-000009d6 00002d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n-00000a8a 00002e0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00000aae 00002f0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00000abe 00002f0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00000b38 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000b3c 00000203 R_ARM_REL32 00000000 .bss\n-00000b40 00000203 R_ARM_REL32 00000000 .bss\n-00000b44 00002619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000b48 0000271a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000b4c 0000311a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n-00000b50 00000403 R_ARM_REL32 00000000 .LC0\n-00000b54 00000203 R_ARM_REL32 00000000 .bss\n-00000b58 00001003 R_ARM_REL32 00000000 .rodata\n-00000b5c 00000703 R_ARM_REL32 00000068 .LC4\n-00000b60 00000103 R_ARM_REL32 00000000 .data\n-00000b64 0000291a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000b68 00000503 R_ARM_REL32 00000008 .LC1\n-00000b6c 00000903 R_ARM_REL32 00000094 .LC7\n-00000b70 00000803 R_ARM_REL32 00000074 .LC6\n-00000b74 00000803 R_ARM_REL32 00000074 .LC6\n+000000bc 00001b0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+0000015a 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+0000016a 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00000182 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+0000018c 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00000214 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+00000220 00001b0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00000266 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+00000310 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000350 00001f0a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n+0000035e 0000200a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00000364 0000210a R_ARM_THM_CALL 00000000 free\n+00000390 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+0000039e 00001b0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+000003dc 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+00000406 0000200a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+0000040c 0000210a R_ARM_THM_CALL 00000000 free\n+000004d4 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000004f4 00001f0a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n+0000052e 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+0000053e 00001b0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00000570 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+00000624 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000064e 00001f0a R_ARM_THM_CALL 00000000 __gridxc_gpfa_core_dp_MOD_gpfa_\n+0000065c 0000200a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00000662 0000210a R_ARM_THM_CALL 00000000 free\n+00000692 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_redistributemeshdata\n+000006dc 0000220a R_ARM_THM_CALL 00000000 _gfortran_associated\n+0000079c 0000220a R_ARM_THM_CALL 00000000 _gfortran_associated\n+00000810 0000220a R_ARM_THM_CALL 00000000 _gfortran_associated\n+000008b8 0000230a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+00000910 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000091c 0000240a R_ARM_THM_CALL 00000000 __gridxc_fft_gpfa_MOD_setgpfa_check\n+0000092a 0000200a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00000930 0000210a R_ARM_THM_CALL 00000000 free\n+0000096a 0000250a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n+00000a20 0000260a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+00000a46 0000270a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00000a56 0000270a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00000ad0 0000280a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000ad4 00002919 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000ad8 00002919 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000adc 00002a1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000ae0 00002b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_start\n+00000ae4 00000403 R_ARM_REL32 00000000 .LC0\n+00000ae8 00002c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000aec 00000603 R_ARM_REL32 0000003c .LC2\n+00000af0 00000203 R_ARM_REL32 00000000 .bss\n+00000af4 00000103 R_ARM_REL32 00000000 .data\n+00000af8 00000203 R_ARM_REL32 00000000 .bss\n+00000afc 00000c03 R_ARM_REL32 00000000 .rodata\n+00000b00 00000203 R_ARM_REL32 00000000 .bss\n+00000b04 00000103 R_ARM_REL32 00000000 .data\n+00000b08 00000c03 R_ARM_REL32 00000000 .rodata\n+00000b0c 00000203 R_ARM_REL32 00000000 .bss\n+00000b10 00000103 R_ARM_REL32 00000000 .data\n+00000b14 00000c03 R_ARM_REL32 00000000 .rodata\n+00000b18 00000203 R_ARM_REL32 00000000 .bss\n+00000b1c 00000103 R_ARM_REL32 00000000 .data\n+00000b20 00000203 R_ARM_REL32 00000000 .bss\n+00000b24 00000203 R_ARM_REL32 00000000 .bss\n+00000b28 00002919 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000b2c 00002d1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n+00000b30 00000403 R_ARM_REL32 00000000 .LC0\n+00000b34 00000203 R_ARM_REL32 00000000 .bss\n+00000b38 00000c03 R_ARM_REL32 00000000 .rodata\n+00000b3c 00000703 R_ARM_REL32 00000068 .LC4\n+00000b40 00000103 R_ARM_REL32 00000000 .data\n+00000b44 00000503 R_ARM_REL32 00000008 .LC1\n+00000b48 00000903 R_ARM_REL32 00000094 .LC7\n+00000b4c 00000803 R_ARM_REL32 00000074 .LC6\n+00000b50 00000803 R_ARM_REL32 00000074 .LC6\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "comments": ["Ordering differences only"], "unified_diff": "@@ -9,24 +9,24 @@\n __gridxc_fft3d_MOD_fft3d\n __gridxc_mesh3d_MOD_mymeshbox\n __gridxc_mesh3d_MOD_associatemeshtask\n __gridxc_mesh3d_MOD_redistributemeshdata\n _gfortran_internal_pack\n __gridxc_gpfa_core_dp_MOD_gpfa_\n _gfortran_internal_unpack\n-_GLOBAL_OFFSET_TABLE_\n-__stack_chk_guard\n-__gridxc_sys_MOD_gridxc_timer_start\n-__gridxc_sys_MOD_die\n _gfortran_associated\n __gridxc_alloc_MOD_realloc_d2\n __gridxc_fft_gpfa_MOD_setgpfa_check\n __gridxc_mesh3d_MOD_fftmeshdistr\n __gridxc_mesh3d_MOD_copymeshdata\n __gridxc_alloc_MOD_dealloc_d4\n __stack_chk_fail\n+_GLOBAL_OFFSET_TABLE_\n+__stack_chk_guard\n+__gridxc_sys_MOD_gridxc_timer_start\n+__gridxc_sys_MOD_die\n __gridxc_sys_MOD_gridxc_timer_stop\n .shstrtab\n .rel.text\n .rodata.str1.4\n .note.GNU-stack\n .ARM.attributes\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -3,1194 +3,1184 @@\n \n Disassembly of section .text:\n \n 00000000 <__gridxc_fft3d_MOD_fft3d>:\n __gridxc_fft3d_MOD_fft3d():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3560]\t@ 0xde8\n-\tldr\tr5, [pc, #968]\t@ (3e0 <__gridxc_fft3d_MOD_fft3d+0x3e0>)\n-\tsub\tsp, #484\t@ 0x1e4\n-\tldr\tr7, [pc, #968]\t@ (3e4 <__gridxc_fft3d_MOD_fft3d+0x3e4>)\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr4, [pc, #968]\t@ (3e8 <__gridxc_fft3d_MOD_fft3d+0x3e8>)\n+\tstr.w\tr0, [ip, #3600]\t@ 0xe10\n+\tldr.w\tr4, [pc, #2752]\t@ ad4 <__gridxc_fft3d_MOD_fft3d+0xad4>\n+\tsub\tsp, #460\t@ 0x1cc\n+\tmov\tr6, r0\n+\tldr.w\tr5, [pc, #2748]\t@ ad8 <__gridxc_fft3d_MOD_fft3d+0xad8>\n+\tldr.w\tr0, [pc, #2748]\t@ adc <__gridxc_fft3d_MOD_fft3d+0xadc>\n+\tadd\tr4, pc\n \tadd\tr5, pc\n-\tadd\tr7, pc\n-\tstr\tr7, [sp, #76]\t@ 0x4c\n-\tmov\tfp, r1\n+\tstr\tr5, [sp, #76]\t@ 0x4c\n \tmov\tr9, r2\n-\tmov\tr6, r0\n-\tldr\tr4, [r5, r4]\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #476]\t@ 0x1dc\n-\tmov.w\tr4, #0\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [pc, #944]\t@ (3ec <__gridxc_fft3d_MOD_fft3d+0x3ec>)\n-\tldr\tr4, [r0, #24]\n-\tvstr\td16, [sp, #260]\t@ 0x104\n-\tvstr\td16, [sp, #300]\t@ 0x12c\n-\tcmp\tr4, #0\n+\tadd\tr7, sp, #284\t@ 0x11c\n+\tmov\tfp, r1\n+\tldr\tr0, [r4, r0]\n+\tadd\tr4, sp, #248\t@ 0xf8\n+\tldr\tr0, [r0, #0]\n+\tstr\tr0, [sp, #452]\t@ 0x1c4\n+\tmov.w\tr0, #0\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tldr.w\tr2, [pc, #2724]\t@ ae0 <__gridxc_fft3d_MOD_fft3d+0xae0>\n \tstr\tr1, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tmovs\tr3, #0\n+\tstr\tr4, [sp, #80]\t@ 0x50\n+\tstrd\tr3, r3, [sp, #252]\t@ 0xfc\n+\tstrd\tr3, r3, [sp, #284]\t@ 0x11c\n+\tstr\tr7, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #292]\t@ 0x124\n+\tmovs\tr3, #8\n+\tstr\tr3, [sp, #244]\t@ 0xf4\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh.w\tr3, [sp, #252]\t@ 0xfc\n+\tstrh.w\tr3, [sp, #288]\t@ 0x120\n+\tldr\tr4, [r6, #24]\n+\tldr\tr3, [r5, r2]\n+\tldrd\tr2, r1, [r6, #64]\t@ 0x40\n+\tcmp\tr4, #0\n \tit\teq\n \tmoveq\tr4, #1\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tmovs\tr2, #8\n-\tstr\tr2, [sp, #256]\t@ 0x100\n-\tstr\tr2, [sp, #296]\t@ 0x128\n-\tmovs\tr2, #0\n-\tstr\tr2, [sp, #268]\t@ 0x10c\n-\tstr\tr2, [sp, #308]\t@ 0x134\n-\tmovw\tr2, #769\t@ 0x301\n-\tstrh.w\tr2, [sp, #264]\t@ 0x108\n-\tstrh.w\tr2, [sp, #304]\t@ 0x130\n-\tldrd\tr2, r1, [r0, #64]\t@ 0x40\n-\tldr\tr3, [r7, r3]\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n \tsubs\tr7, r1, r2\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tldrd\tr2, r4, [r0, #28]\n-\tstr\tr7, [sp, #112]\t@ 0x70\n \tldr\tr3, [r3, #0]\n-\tsubs\tr4, r4, r2\n-\tldr.w\tsl, [r6]\n-\tldrd\tr2, r5, [r0, #40]\t@ 0x28\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n+\tldrd\tr2, r4, [r6, #28]\n+\tstr\tr7, [sp, #108]\t@ 0x6c\n+\tldr.w\tr0, [pc, #2656]\t@ ae4 <__gridxc_fft3d_MOD_fft3d+0xae4>\n+\tsubs\tr1, r4, r2\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tldrd\tr2, r5, [r6, #40]\t@ 0x28\n+\tadd\tr0, pc\n \tsubs\tr2, r5, r2\n \tstr\tr2, [sp, #32]\n-\tldrd\tr2, r1, [r0, #52]\t@ 0x34\n-\tldr\tr0, [pc, #864]\t@ (3f0 <__gridxc_fft3d_MOD_fft3d+0x3f0>)\n+\tldrd\tr2, r1, [r6, #52]\t@ 0x34\n+\tldr\tr4, [r6, #48]\t@ 0x30\n \tsubs\tr5, r1, r2\n+\tstr\tr4, [sp, #64]\t@ 0x40\n \tmovs\tr1, #6\n-\tadd\tr0, pc\n-\tstr\tr5, [sp, #48]\t@ 0x30\n+\tldr\tr4, [r6, #60]\t@ 0x3c\n+\tstr\tr4, [sp, #68]\t@ 0x44\n+\tadds\tr4, r7, #1\n+\tldr.w\tsl, [r6]\n \tldr.w\tr8, [r6, #36]\t@ 0x24\n-\tldr\tr2, [r6, #48]\t@ 0x30\n-\tldr\tr6, [r6, #60]\t@ 0x3c\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tstr\tr6, [sp, #60]\t@ 0x3c\n-\tadds\tr6, r7, #1\n-\tstr\tr6, [sp, #64]\t@ 0x40\n+\tstr\tr5, [sp, #52]\t@ 0x34\n+\tstr\tr4, [sp, #72]\t@ 0x48\n \tblx\tr3\n-\tadd\tr1, sp, #224\t@ 0xe0\n-\tmov\tr0, r9\n-\tmov\tr6, r1\n-\tmov\tr2, r1\n-\tstr\tr1, [sp, #156]\t@ 0x9c\n+\tadd\tr3, sp, #212\t@ 0xd4\n \tmov\tr1, fp\n+\tmov\tr2, r3\n+\tmov\tr0, r9\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldrd\tr2, r3, [r6]\n+\tldrd\tr2, r3, [sp, #212]\t@ 0xd4\n+\tldr\tr1, [sp, #40]\t@ 0x28\n \tsubs\tr3, r3, r2\n-\tcmp\tr4, r3\n-\tblt.w\t9fc <__gridxc_fft3d_MOD_fft3d+0x9fc>\n-\tldrd\tr2, r3, [r6, #8]\n+\tcmp\tr1, r3\n+\tblt.w\t98e <__gridxc_fft3d_MOD_fft3d+0x98e>\n+\tldrd\tr2, r3, [sp, #220]\t@ 0xdc\n \tsubs\tr3, r3, r2\n \tldr\tr2, [sp, #32]\n \tcmp\tr2, r3\n-\tblt.w\t9fc <__gridxc_fft3d_MOD_fft3d+0x9fc>\n-\tldrd\tr2, r3, [r6, #16]\n+\tblt.w\t98e <__gridxc_fft3d_MOD_fft3d+0x98e>\n+\tldrd\tr2, r3, [sp, #228]\t@ 0xe4\n \tsubs\tr3, r3, r2\n \tcmp\tr5, r3\n-\tblt.w\t9fc <__gridxc_fft3d_MOD_fft3d+0x9fc>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tblt.w\t98e <__gridxc_fft3d_MOD_fft3d+0x98e>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tcmp\tr3, #2\n-\tbeq.n\tf4 <__gridxc_fft3d_MOD_fft3d+0xf4>\n-\tldr\tr3, [pc, #780]\t@ (3f4 <__gridxc_fft3d_MOD_fft3d+0x3f4>)\n+\tbeq.n\t102 <__gridxc_fft3d_MOD_fft3d+0x102>\n+\tldr.w\tr3, [pc, #2552]\t@ ae8 <__gridxc_fft3d_MOD_fft3d+0xae8>\n \tmovs\tr1, #41\t@ 0x29\n \tldr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr0, [pc, #780]\t@ (3f8 <__gridxc_fft3d_MOD_fft3d+0x3f8>)\n+\tldr.w\tr0, [pc, #2548]\t@ aec <__gridxc_fft3d_MOD_fft3d+0xaec>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #772]\t@ (3fc <__gridxc_fft3d_MOD_fft3d+0x3fc>)\n-\tldr\tr2, [sp, #40]\t@ 0x28\n+\tldr.w\tr3, [pc, #2540]\t@ af0 <__gridxc_fft3d_MOD_fft3d+0xaf0>\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n \tadd\tr3, pc\n \tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #148]\t@ 0x94\n+\tstr\tr2, [sp, #132]\t@ 0x84\n \tmov\tr1, r2\n \tldr\tr2, [r3, #0]\n \tcmp\tr1, r2\n-\tbne.w\t8a8 <__gridxc_fft3d_MOD_fft3d+0x8a8>\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tbne.w\t858 <__gridxc_fft3d_MOD_fft3d+0x858>\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tldr\tr2, [r3, #4]\n \tldr\tr1, [r0, #4]\n \tcmp\tr1, r2\n-\tbne.w\t8a8 <__gridxc_fft3d_MOD_fft3d+0x8a8>\n+\tbne.w\t858 <__gridxc_fft3d_MOD_fft3d+0x858>\n \tldr\tr1, [r0, #8]\n \tldr\tr2, [r3, #8]\n \tcmp\tr1, r2\n-\tbne.w\t8a8 <__gridxc_fft3d_MOD_fft3d+0x8a8>\n+\tbne.w\t858 <__gridxc_fft3d_MOD_fft3d+0x858>\n \tmov\tr2, r0\n \tldr\tr0, [r0, #0]\n \tldr\tr1, [r2, #4]\n \tldr\tr2, [r2, #8]\n \tstmia\tr3!, {r0, r1, r2}\n-\tadd\tr3, sp, #420\t@ 0x1a4\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tadd\tr3, sp, #400\t@ 0x190\n+\tadd\tr3, sp, #392\t@ 0x188\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tadd\tr3, sp, #380\t@ 0x17c\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr6, [pc, #716]\t@ (400 <__gridxc_fft3d_MOD_fft3d+0x400>)\n+\tldr.w\tr6, [pc, #2480]\t@ af4 <__gridxc_fft3d_MOD_fft3d+0xaf4>\n \tldr\tr5, [sp, #88]\t@ 0x58\n \tadd\tr6, pc\n-\tadd.w\tr4, r6, #12\n+\tadd.w\tr3, r6, #12\n \tmov\tr1, r5\n+\tmov\tr4, r3\n \tadd.w\tr0, r6, #16\n-\tmov\tr2, r4\n+\tmov\tr2, r3\n+\tmov\tr9, r6\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tmov\tr9, r6\n+\tmov\tr2, r4\n \tmov\tr1, r5\n \tadd.w\tr0, r6, #20\n-\tmov\tr2, r4\n \tadd.w\tr7, r9, #36\t@ 0x24\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n+\tldr\tr4, [sp, #40]\t@ 0x28\n \tldr\tr5, [sp, #32]\n \tadds\tr6, #24\n \tmov\tfp, r7\n-\tstr.w\tr9, [sp, #80]\t@ 0x50\n+\tstr.w\tr9, [sp, #92]\t@ 0x5c\n \tmov\tr2, r9\n \tmov\tr0, r6\n-\tmov\tr1, r4\n+\tldr\tr1, [sp, #56]\t@ 0x38\n \tadds\tr6, #4\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n \tmov\tr2, r9\n \tmov\tr0, r7\n-\tmov\tr1, r4\n+\tldr\tr1, [sp, #56]\t@ 0x38\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n \tadd.w\tr9, r9, #4\n \tadds\tr7, #4\n \tcmp\tfp, r6\n-\tbne.n\t162 <__gridxc_fft3d_MOD_fft3d+0x162>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n-\tadd.w\tfp, sp, #200\t@ 0xc8\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tmov\tr2, r4\n-\tstr\tr3, [sp, #424]\t@ 0x1a8\n+\tbne.n\t17a <__gridxc_fft3d_MOD_fft3d+0x17a>\n+\tmov\tr9, r4\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tmovs\tr4, #8\n+\tstr\tr4, [sp, #400]\t@ 0x190\n+\tldr\tr4, [sp, #48]\t@ 0x30\n+\tmov\tlr, r5\n+\tstr\tr5, [sp, #32]\n \tmovs\tr7, #0\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr3, [sp, #456]\t@ 0x1c8\n-\tldr\tr6, [pc, #616]\t@ (404 <__gridxc_fft3d_MOD_fft3d+0x404>)\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tldr\tr5, [sp, #92]\t@ 0x5c\n+\tadd.w\tfp, sp, #188\t@ 0xbc\n+\tstr\tr7, [sp, #392]\t@ 0x188\n+\tmov.w\tip, #8\n+\tadd.w\tr3, r5, #16\n+\tstr\tr3, [sp, #0]\n+\tstr\tr7, [r4, #4]\n+\tldr\tr4, [sp, #60]\t@ 0x3c\n+\tstr\tr4, [sp, #404]\t@ 0x194\n+\tldr\tr4, [sp, #52]\t@ 0x34\n+\tstr\tr4, [sp, #436]\t@ 0x1b4\n+\tldr.w\tr6, [pc, #2352]\t@ af8 <__gridxc_fft3d_MOD_fft3d+0xaf8>\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tstr\tr4, [sp, #428]\t@ 0x1ac\n \tadd\tr6, pc\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tadd.w\tr9, r6, #64\t@ 0x40\n-\tstr\tr3, [sp, #468]\t@ 0x1d4\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tstr\tr5, [sp, #32]\n-\tstr\tr5, [sp, #444]\t@ 0x1bc\n-\tadds\tr3, #16\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tldr\tr4, [sp, #72]\t@ 0x48\n+\tadd.w\tr3, r6, #60\t@ 0x3c\n+\tstr\tr4, [sp, #448]\t@ 0x1c0\n+\tldr\tr4, [sp, #68]\t@ 0x44\n \tldr\tr0, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #56]\t@ 0x38\n \tldr\tr1, [sp, #36]\t@ 0x24\n-\tstr\tr3, [sp, #0]\n-\tmov\tr3, r9\n-\tstr\tr5, [sp, #460]\t@ 0x1cc\n-\tnegs\tr5, r5\n-\tstr\tr7, [sp, #428]\t@ 0x1ac\n-\tstr\tr7, [sp, #440]\t@ 0x1b8\n-\tstr\tr7, [sp, #452]\t@ 0x1c4\n-\tmovs\tr7, #8\n-\tstr\tr5, [sp, #84]\t@ 0x54\n-\tstr\tr7, [sp, #420]\t@ 0x1a4\n+\tstr.w\tlr, [sp, #424]\t@ 0x1a8\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tstr.w\tip, [sp, #388]\t@ 0x184\n+\tmov.w\tip, #772\t@ 0x304\n \tstr\tr7, [sp, #408]\t@ 0x198\n-\tmov.w\tr7, #772\t@ 0x304\n-\tstr\tr5, [sp, #404]\t@ 0x194\n-\tvstr\td8, [sp, #412]\t@ 0x19c\n-\tstr.w\tr8, [sp, #436]\t@ 0x1b4\n-\tstrh.w\tr7, [sp, #416]\t@ 0x1a0\n-\tmovs\tr7, #1\n-\tstr.w\tsl, [sp, #400]\t@ 0x190\n-\tstr\tr7, [sp, #464]\t@ 0x1d0\n+\tstrh.w\tip, [sp, #396]\t@ 0x18c\n+\tstr.w\tr9, [sp, #412]\t@ 0x19c\n+\tmov.w\tr9, #1\n+\tstr\tr7, [sp, #420]\t@ 0x1a4\n+\tstr\tr7, [sp, #432]\t@ 0x1b0\n+\tstr\tr4, [sp, #440]\t@ 0x1b8\n+\tnegs\tr4, r4\n+\tstr.w\tr9, [sp, #444]\t@ 0x1bc\n+\tstr.w\tr8, [sp, #416]\t@ 0x1a0\n+\tstr.w\tsl, [sp, #380]\t@ 0x17c\n+\tstr\tr4, [sp, #88]\t@ 0x58\n+\tstr\tr4, [sp, #384]\t@ 0x180\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tmov\tr1, r5\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tmov\tr2, fp\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tstr\tr5, [sp, #92]\t@ 0x5c\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tmov\tr1, r9\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tmov\tr1, r3\n+\tadd\tr3, sp, #164\t@ 0xa4\n+\tmov\tr5, r3\n+\tstr\tr5, [sp, #56]\t@ 0x38\n \tldrd\tr2, r3, [fp]\n-\tmov\tr0, r4\n-\tadd\tr4, sp, #176\t@ 0xb0\n-\tstr\tr4, [sp, #68]\t@ 0x44\n \tsubs\tr3, r3, r2\n-\tadds\tr5, r3, r7\n-\tstr\tr5, [sp, #176]\t@ 0xb0\n+\tadd.w\tr4, r3, r9\n+\tstr\tr4, [r5, #0]\n \tldrd\tr2, r3, [fp, #8]\n \tsubs\tr3, r3, r2\n-\tadd.w\tr9, r3, r7\n-\tstr.w\tr9, [sp, #180]\t@ 0xb4\n+\tadd.w\tr5, r3, r9\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tstr\tr5, [r3, #4]\n \tldrd\tr2, r3, [fp, #16]\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tadds\tr4, r3, r7\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tstr\tr4, [r3, #8]\n-\tadd.w\tr3, r2, #24\n+\tadd.w\tr2, r3, r9\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tstr\tr2, [sp, #96]\t@ 0x60\n+\tstr\tr2, [r3, #8]\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tmov\tr3, r2\n+\tadds\tr3, #24\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r6, #136\t@ 0x88\n+\tadd.w\tr3, r6, #132\t@ 0x84\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n-\tmul.w\tr3, r9, r5\n-\tmovs\tr2, #8\n-\tstr\tr2, [sp, #408]\t@ 0x198\n-\tldr\tr2, [r6, #56]\t@ 0x38\n-\tldr.w\tr0, [r6, #196]\t@ 0xc4\n-\tmul.w\tr3, r4, r3\n-\tstr\tr7, [sp, #428]\t@ 0x1ac\n-\tstr\tr3, [sp, #280]\t@ 0x118\n-\tsubs\tr2, r7, r2\n-\tstr\tr3, [sp, #320]\t@ 0x140\n-\tadd.w\tr3, r6, #36\t@ 0x24\n-\tstr\tr7, [sp, #276]\t@ 0x114\n-\tstr\tr7, [sp, #316]\t@ 0x13c\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r6, #200]\t@ 0xc8\n-\tldr\tr1, [r6, #52]\t@ 0x34\n-\tsubs\tr7, r7, r3\n+\tmul.w\tr3, r5, r4\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldr\tr1, [sp, #80]\t@ 0x50\n+\tldr\tr2, [r6, #40]\t@ 0x28\n+\tldr\tr4, [sp, #48]\t@ 0x30\n+\tmul.w\tr3, r0, r3\n+\tstr\tr7, [r1, #4]\n+\tstr\tr3, [sp, #268]\t@ 0x10c\n+\tsub.w\tr2, r9, r2\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #304]\t@ 0x130\n+\tldrd\tip, r3, [r6, #192]\t@ 0xc0\n+\tstr\tr7, [r1, #4]\n+\tmovs\tr1, #8\n+\tstr\tr1, [sp, #256]\t@ 0x100\n+\tstr\tr1, [sp, #292]\t@ 0x124\n+\tsub.w\tr1, r9, r3\n \trsb\tr3, r3, #2\n-\tvldr\td17, [pc, #368]\t@ 3d8 <__gridxc_fft3d_MOD_fft3d+0x3d8>\n-\tldr\tr5, [sp, #72]\t@ 0x48\n-\tmul.w\tr7, r0, r7\n-\tvstr\td8, [sp, #412]\t@ 0x19c\n-\tmul.w\tr0, r3, r0\n-\tldr.w\tr3, [r6, #136]\t@ 0x88\n-\tmul.w\tr2, r1, r2\n-\tvmov.32\tr1, d16[1]\n-\tvstr\td8, [sp, #260]\t@ 0x104\n-\tadd.w\tr7, r3, r7, lsl #3\n-\tadd.w\tr3, r3, r0, lsl #3\n-\tldr\tr0, [r6, #16]\n-\tstr\tr3, [sp, #288]\t@ 0x120\n-\tldr\tr3, [r6, #44]\t@ 0x2c\n-\tnegs\tr1, r1\n-\tadd.w\tr2, r0, r2, lsl #3\n-\tldr\tr0, [r6, #48]\t@ 0x30\n-\trsb\tr3, r3, #1\n+\tldr.w\tr0, [r6, #132]\t@ 0x84\n+\tstr\tr7, [sp, #392]\t@ 0x188\n+\tmul.w\tr1, ip, r1\n \tstr\tr7, [sp, #248]\t@ 0xf8\n-\tadd\tr3, r0\n-\tadd\tr0, sp, #268\t@ 0x10c\n-\tstr\tr0, [sp, #100]\t@ 0x64\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n-\tmovw\tr3, #769\t@ 0x301\n-\tvst1.32\t{d17}, [r0]\n-\tadd\tr0, sp, #308\t@ 0x134\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n-\tstrh.w\tr3, [sp, #416]\t@ 0x1a0\n-\tvst1.32\t{d17}, [r0]\n-\tldr\tr0, [sp, #36]\t@ 0x24\n-\tvst1.32\t{d16}, [r5]\n-\tstrh.w\tr3, [sp, #264]\t@ 0x108\n-\tvstr\td8, [sp, #300]\t@ 0x12c\n-\tstrh.w\tr3, [sp, #304]\t@ 0x130\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstrd\tr2, r1, [sp, #400]\t@ 0x190\n-\tstr\tr3, [sp, #252]\t@ 0xfc\n-\tstr\tr3, [sp, #292]\t@ 0x124\n+\tmul.w\tr3, ip, r3\n+\tstr.w\tr9, [sp, #264]\t@ 0x108\n+\tstr.w\tr9, [sp, #260]\t@ 0x104\n+\tadd.w\tr1, r0, r1, lsl #3\n+\tstr\tr7, [sp, #284]\t@ 0x11c\n+\tadd.w\tr0, r0, r3, lsl #3\n+\tldr\tr3, [r6, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #236]\t@ 0xec\n+\tadd\tr2, r3\n+\tldr\tr3, [r6, #32]\n+\tstr\tr3, [sp, #400]\t@ 0x190\n+\tldr\tr3, [r6, #36]\t@ 0x24\n+\tstr\tr7, [r4, #4]\n+\tmovs\tr4, #8\n+\tstrd\tr9, r2, [sp, #408]\t@ 0x198\n+\tmovw\tr2, #769\t@ 0x301\n+\tstrd\tr9, r9, [sp, #296]\t@ 0x128\n+\tstr\tr0, [sp, #272]\t@ 0x110\n+\tstr\tr4, [sp, #388]\t@ 0x184\n+\tstrh.w\tr2, [sp, #252]\t@ 0xfc\n+\tstrh.w\tr2, [sp, #288]\t@ 0x120\n+\tstr\tr3, [sp, #404]\t@ 0x194\n+\tnegs\tr3, r3\n+\tstr\tr3, [sp, #384]\t@ 0x180\n+\tldr\tr3, [r6, #52]\t@ 0x34\n+\tstrh.w\tr2, [sp, #396]\t@ 0x18c\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstr\tr2, [sp, #240]\t@ 0xf0\n+\tsub.w\tr3, r9, r3\n+\tstr\tr2, [sp, #276]\t@ 0x114\n+\tldr\tr2, [r6, #48]\t@ 0x30\n+\tldr.w\tr9, [sp, #36]\t@ 0x24\n+\tmov\tr0, r9\n+\tmul.w\tr3, r2, r3\n+\tldr\tr2, [r6, #12]\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr\tr3, [sp, #380]\t@ 0x17c\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tmul.w\tr3, r4, r9\n-\tstr\tr3, [sp, #168]\t@ 0xa8\n-\tadd\tr3, sp, #248\t@ 0xf8\n-\tmov\tr7, r3\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [pc, #280]\t@ (408 <__gridxc_fft3d_MOD_fft3d+0x408>)\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #56]\t@ 0x38\n \tmov\tr6, r0\n-\tldr\tr5, [r2, #0]\n-\tadd\tr1, sp, #288\t@ 0x120\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tadd\tr2, sp, #168\t@ 0xa8\n+\tmul.w\tr3, r1, r5\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tadd\tr3, sp, #236\t@ 0xec\n+\tmov\tr7, r3\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tldr.w\tr3, [pc, #2000]\t@ afc <__gridxc_fft3d_MOD_fft3d+0xafc>\n+\tadd\tr5, sp, #160\t@ 0xa0\n+\tldr\tr4, [r1, #0]\n+\tadd\tr1, sp, #272\t@ 0x110\n \tadd\tr3, pc\n-\tstrd\tr4, r4, [sp]\n-\tstr\tr2, [sp, #152]\t@ 0x98\n-\tadd\tr4, sp, #172\t@ 0xac\n+\tstrd\tr2, r2, [sp]\n+\tstr\tr5, [sp, #12]\n+\tadd\tr2, sp, #156\t@ 0x9c\n+\tstr\tr2, [sp, #136]\t@ 0x88\n \tstr\tr2, [sp, #8]\n \tmov\tr2, r0\n-\tstr\tr4, [sp, #12]\n \tmov\tr0, r7\n-\tstr\tr5, [sp, #144]\t@ 0x90\n-\tnegs\tr5, r5\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n+\tstr\tr4, [sp, #128]\t@ 0x80\n+\tstr\tr5, [sp, #96]\t@ 0x60\n+\tnegs\tr4, r4\n \tstr\tr1, [sp, #104]\t@ 0x68\n-\tstr\tr5, [sp, #88]\t@ 0x58\n-\tstr\tr5, [sp, #172]\t@ 0xac\n+\tstr\tr4, [sp, #92]\t@ 0x5c\n+\tstr\tr4, [sp, #160]\t@ 0xa0\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n R_ARM_THM_CALL\t__gridxc_gpfa_core_dp_MOD_gpfa_\n-\tldr\tr3, [sp, #400]\t@ 0x190\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n \tcmp\tr3, r6\n-\tbeq.n\t330 <__gridxc_fft3d_MOD_fft3d+0x330>\n-\tldr\tr0, [sp, #36]\t@ 0x24\n+\tbeq.n\t368 <__gridxc_fft3d_MOD_fft3d+0x368>\n+\tmov\tr0, r9\n \tmov\tr1, r6\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr7, [pc, #216]\t@ (40c <__gridxc_fft3d_MOD_fft3d+0x40c>)\n-\tldr\tr6, [pc, #220]\t@ (410 <__gridxc_fft3d_MOD_fft3d+0x410>)\n-\tadd\tr7, pc\n-\tadd.w\tr3, r7, #12\n+\tldr.w\tr6, [pc, #1940]\t@ b00 <__gridxc_fft3d_MOD_fft3d+0xb00>\n+\tldr.w\tr7, [pc, #1940]\t@ b04 <__gridxc_fft3d_MOD_fft3d+0xb04>\n \tadd\tr6, pc\n+\tadd.w\tr3, r6, #60\t@ 0x3c\n+\tadd\tr7, pc\n \tmov\tr5, r3\n-\tadd.w\tr4, r6, #64\t@ 0x40\n-\tadd.w\tr9, r6, #136\t@ 0x88\n+\tadd.w\tr9, r6, #132\t@ 0x84\n+\tadd.w\tr2, r7, #12\n \tadd.w\tr3, r7, #36\t@ 0x24\n-\tmov\tr2, r5\n \tmov\tr1, r9\n \tmov\tr0, r7\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r4\n+\tmov\tr3, r5\n+\tmov\tr4, r2\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n \tadds\tr1, r7, #4\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tmov\tr2, fp\n \tadds\tr7, #28\n-\tstr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #112]\t@ 0x70\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n \tstr\tr7, [sp, #0]\n-\tldr\tr1, [sp, #80]\t@ 0x50\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n+\tldr\tr1, [sp, #112]\t@ 0x70\n \tmov\tr3, r9\n-\tmov\tr2, r1\n-\tmov\tr1, r4\n \tldrd\tr7, r4, [fp]\n+\tmov\tr2, r1\n+\tmov\tr1, r5\n \tsubs\tr7, r4, r7\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tadds\tr5, r7, #1\n-\tstr\tr5, [sp, #140]\t@ 0x8c\n-\tstr\tr5, [r4, #0]\n-\tldrd\tr7, r5, [fp, #8]\n-\tsub.w\tr9, r5, r7\n-\tadd.w\tr5, r9, #1\n-\tstr\tr5, [r4, #4]\n-\tldrd\tr4, r7, [fp, #16]\n-\tstr\tr5, [sp, #136]\t@ 0x88\n-\tldr\tr5, [sp, #68]\t@ 0x44\n-\tsubs\tr4, r7, r4\n-\tstr\tr4, [sp, #116]\t@ 0x74\n-\tadds\tr4, #1\n-\tstr\tr4, [r5, #8]\n+\tadds\tr4, r7, #1\n+\tldr\tr7, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #124]\t@ 0x7c\n+\tstr\tr4, [r7, #0]\n+\tldrd\tr5, r4, [fp, #8]\n+\tsub.w\tr9, r4, r5\n+\tadd.w\tr4, r9, #1\n+\tstr\tr4, [r7, #4]\n+\tldrd\tr7, r5, [fp, #16]\n+\tsubs\tr5, r5, r7\n+\tstr\tr5, [sp, #112]\t@ 0x70\n+\tadd.w\tr9, r5, #1\n+\tldr\tr5, [sp, #56]\t@ 0x38\n+\tstr.w\tr9, [r5, #8]\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n-\tcmp\tr4, #0\n-\tble.w\t524 <__gridxc_fft3d_MOD_fft3d+0x524>\n-\tadd\tr2, sp, #412\t@ 0x19c\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tmovs\tr4, #0\n-\tadd\tr2, sp, #260\t@ 0x104\n-\tldr.w\tr9, [sp, #32]\n-\tstr\tr2, [sp, #128]\t@ 0x80\n-\tadd\tr2, sp, #300\t@ 0x12c\n-\tvldr\td9, [pc, #24]\t@ 3d8 <__gridxc_fft3d_MOD_fft3d+0x3d8>\n-\tstr\tr2, [sp, #132]\t@ 0x84\n-\tadd\tr2, sp, #180\t@ 0xb4\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n-\tadd.w\tr2, r6, #36\t@ 0x24\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tldrd\tr3, r2, [sp, #136]\t@ 0x88\n-\tb.n\t430 <__gridxc_fft3d_MOD_fft3d+0x430>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x000003bc\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003be\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t...\n- R_ARM_GOT32\t__stack_chk_guard\n- R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_start\n-\t.word\t0x0000035a\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000306\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000300\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002c8\n- R_ARM_REL32\t.data\n-\t.word\t0x00000260\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000010a\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000000d4\n- R_ARM_REL32\t.data\n-\t.word\t0x000000d2\n- R_ARM_REL32\t.bss\n+\tcmp.w\tr9, #0\n+\tble.w\t506 <__gridxc_fft3d_MOD_fft3d+0x506>\n+\tldr.w\tr3, [pc, #1820]\t@ b08 <__gridxc_fft3d_MOD_fft3d+0xb08>\n+\tmovs\tr1, #0\n+\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tmov.w\tr9, #8\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tadd\tr3, sp, #168\t@ 0xa8\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tmov\tr3, r4\n+\tmov\tr4, r1\n+\tb.n\t41e <__gridxc_fft3d_MOD_fft3d+0x41e>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tmov\tr1, r7\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [sp, #116]\t@ 0x74\n+\tldr\tr2, [sp, #112]\t@ 0x70\n \tadds\tr3, r4, #1\n \tcmp\tr4, r2\n-\tbeq.n\t520 <__gridxc_fft3d_MOD_fft3d+0x520>\n+\tbeq.n\t506 <__gridxc_fft3d_MOD_fft3d+0x506>\n \tmov\tr4, r3\n \tldrd\tr2, r3, [r5]\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tstr\tr3, [sp, #280]\t@ 0x118\n-\tstr\tr3, [sp, #320]\t@ 0x140\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tvld1.32\t{d16}, [r2]\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tldr.w\tr1, [r6, #184]\t@ 0xb8\n-\tvst1.32\t{d9}, [r3]\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvstr\td8, [r2]\n-\tldr\tr2, [sp, #128]\t@ 0x80\n-\tvst1.32\t{d9}, [r3]\n-\tldr.w\tr3, [r6, #188]\t@ 0xbc\n-\tvstr\td8, [r2]\n-\tldr\tr2, [sp, #132]\t@ 0x84\n+\tstr\tr3, [sp, #268]\t@ 0x10c\n+\tstr\tr3, [sp, #304]\t@ 0x130\n+\tldr.w\tr3, [r6, #184]\t@ 0xb8\n+\tldr.w\tr2, [r6, #180]\t@ 0xb4\n \tsubs\tr3, r4, r3\n-\tmul.w\tr3, r1, r3\n \tldr.w\tr1, [r6, #196]\t@ 0xc4\n-\tvstr\td8, [r2]\n-\tldr.w\tr2, [r6, #200]\t@ 0xc8\n-\trsb\tr0, r2, #1\n-\trsb\tr2, r2, #2\n-\tmla\tr0, r1, r0, r3\n-\tmla\tr3, r1, r2, r3\n-\tldr\tr2, [r6, #56]\t@ 0x38\n-\tldr\tr1, [r6, #52]\t@ 0x34\n-\trsb\tr2, r2, #2\n-\tmul.w\tr2, r1, r2\n-\tldr.w\tr1, [r6, #136]\t@ 0x88\n-\tadd.w\tr0, r1, r0, lsl #3\n+\tldr.w\tr0, [r6, #192]\t@ 0xc0\n+\tstr.w\tr9, [sp, #256]\t@ 0x100\n+\tmul.w\tr3, r2, r3\n+\trsb\tr2, r1, #1\n+\trsb\tr1, r1, #2\n+\tstr.w\tr9, [sp, #292]\t@ 0x124\n+\tstr.w\tr9, [sp, #244]\t@ 0xf4\n+\tmla\tr2, r0, r2, r3\n+\tstr.w\tr9, [sp, #280]\t@ 0x118\n+\tmla\tr3, r0, r1, r3\n+\tldr.w\tr1, [r6, #132]\t@ 0x84\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tadd.w\tr2, r1, r2, lsl #3\n \tadd.w\tr1, r1, r3, lsl #3\n-\tldr\tr3, [r6, #44]\t@ 0x2c\n-\tstr\tr1, [sp, #288]\t@ 0x120\n-\tldr\tr1, [r6, #48]\t@ 0x30\n-\trsb\tr3, r3, #1\n-\tstr\tr0, [sp, #248]\t@ 0xf8\n-\tadd\tr3, r1\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n-\tmovs\tr3, #8\n-\tstr\tr3, [sp, #408]\t@ 0x198\n-\tstr\tr3, [sp, #256]\t@ 0x100\n-\tvmov.32\tr1, d16[1]\n-\tstr\tr3, [sp, #296]\t@ 0x128\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #428]\t@ 0x1ac\n-\tstr\tr3, [sp, #276]\t@ 0x114\n-\tstr\tr3, [sp, #316]\t@ 0x13c\n-\tmovw\tr3, #769\t@ 0x301\n-\tstrh.w\tr3, [sp, #416]\t@ 0x1a0\n-\tnegs\tr1, r1\n-\tstrh.w\tr3, [sp, #264]\t@ 0x108\n-\tstrh.w\tr3, [sp, #304]\t@ 0x130\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr0, [sp, #36]\t@ 0x24\n-\tvst1.32\t{d16}, [r3]\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [sp, #252]\t@ 0xfc\n-\tstr\tr3, [sp, #292]\t@ 0x124\n-\tldr\tr3, [r6, #16]\n-\tstr\tr1, [sp, #404]\t@ 0x194\n-\tadd.w\tr3, r3, r2, lsl #3\n+\tstr\tr2, [sp, #236]\t@ 0xec\n+\tstr\tr1, [sp, #272]\t@ 0x110\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tldr\tr3, [r6, #32]\n \tstr\tr3, [sp, #400]\t@ 0x190\n+\tmovs\tr3, #0\n+\tstr\tr3, [r2, #4]\n+\tstr\tr3, [r1, #4]\n+\tstr\tr3, [r2, #0]\n+\tmovs\tr2, #1\n+\tstr\tr3, [r1, #0]\n+\tmovw\tr1, #769\t@ 0x301\n+\tstrd\tr3, r3, [r0]\n+\tldr\tr3, [r6, #40]\t@ 0x28\n+\tstrh.w\tr1, [sp, #252]\t@ 0xfc\n+\tstrh.w\tr1, [sp, #288]\t@ 0x120\n+\tsubs\tr3, r2, r3\n+\tstrd\tr2, r2, [sp, #260]\t@ 0x104\n+\tstrd\tr2, r2, [sp, #296]\t@ 0x128\n+\tstr.w\tr9, [sp, #388]\t@ 0x184\n+\tldr\tr0, [r6, #44]\t@ 0x2c\n+\tstrh.w\tr1, [sp, #396]\t@ 0x18c\n+\tadd\tr3, r0\n+\tstrd\tr2, r3, [sp, #408]\t@ 0x198\n+\tldr\tr3, [r6, #52]\t@ 0x34\n+\tmov.w\tr0, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [r6, #48]\t@ 0x30\n+\trsb\tr3, r3, #2\n+\tstr\tr0, [sp, #240]\t@ 0xf0\n+\tstr\tr0, [sp, #276]\t@ 0x114\n+\tldr\tr0, [sp, #36]\t@ 0x24\n+\tmul.w\tr3, r2, r3\n+\tldr\tr2, [r6, #12]\n+\tadd.w\tr2, r2, r3, lsl #3\n+\tldr\tr3, [r6, #36]\t@ 0x24\n+\tstr\tr2, [sp, #380]\t@ 0x17c\n+\tstr\tr3, [sp, #404]\t@ 0x194\n+\tnegs\tr3, r3\n+\tstr\tr3, [sp, #384]\t@ 0x180\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #96]\t@ 0x60\n \tmov\tr7, r0\n+\tldr\tr2, [sp, #120]\t@ 0x78\n \tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #116]\t@ 0x74\n+\tstr\tr2, [sp, #0]\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n \tstrd\tr5, r3, [sp, #8]\n \tstr\tr2, [r3, #0]\n-\tmov\tr2, r0\n-\tldr\tr3, [pc, #700]\t@ (7c0 <__gridxc_fft3d_MOD_fft3d+0x7c0>)\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tadd\tr3, pc\n-\tldr\tr0, [sp, #96]\t@ 0x60\n-\tstr\tr3, [sp, #0]\n \tmov\tr3, r5\n+\tmov\tr2, r0\n+\tldrd\tr0, r1, [sp, #100]\t@ 0x64\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n R_ARM_THM_CALL\t__gridxc_gpfa_core_dp_MOD_gpfa_\n-\tldr\tr3, [sp, #400]\t@ 0x190\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n \tcmp\tr3, r7\n-\tbne.w\t414 <__gridxc_fft3d_MOD_fft3d+0x414>\n-\tldr\tr2, [sp, #116]\t@ 0x74\n+\tbne.n\t402 <__gridxc_fft3d_MOD_fft3d+0x402>\n+\tldr\tr2, [sp, #112]\t@ 0x70\n \tadds\tr3, r4, #1\n \tcmp\tr4, r2\n-\tbne.n\t42a <__gridxc_fft3d_MOD_fft3d+0x42a>\n-\tstr.w\tr9, [sp, #32]\n-\tldr\tr6, [pc, #668]\t@ (7c4 <__gridxc_fft3d_MOD_fft3d+0x7c4>)\n-\tldr.w\tr9, [pc, #672]\t@ 7c8 <__gridxc_fft3d_MOD_fft3d+0x7c8>\n-\tadd\tr6, pc\n+\tbne.n\t418 <__gridxc_fft3d_MOD_fft3d+0x418>\n+\tldr.w\tr9, [pc, #1540]\t@ b0c <__gridxc_fft3d_MOD_fft3d+0xb0c>\n+\tldr.w\tr6, [pc, #1540]\t@ b10 <__gridxc_fft3d_MOD_fft3d+0xb10>\n \tadd\tr9, pc\n-\tadd.w\tr3, r6, #12\n+\tadd.w\tr3, r9, #60\t@ 0x3c\n+\tadd\tr6, pc\n \tmov\tr5, r3\n-\tadd.w\tr4, r9, #64\t@ 0x40\n-\tadd.w\tr7, r9, #136\t@ 0x88\n+\tadd.w\tr7, r9, #132\t@ 0x84\n+\tadd.w\tr2, r6, #12\n \tadd.w\tr3, r6, #40\t@ 0x28\n-\tmov\tr2, r5\n \tmov\tr1, r7\n \tadds\tr0, r6, #4\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r4\n+\tmov\tr3, r5\n+\tmov\tr4, r2\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n \tadd.w\tr1, r6, #8\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tmov\tr2, fp\n \tadds\tr6, #32\n-\tstr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #112]\t@ 0x70\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n \tstr\tr6, [sp, #0]\n \tmov\tr3, r7\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tmov\tr0, r4\n+\tldr\tr1, [sp, #112]\t@ 0x70\n \tldrd\tr7, r6, [fp]\n \tmov\tr2, r1\n-\tmov\tr1, r4\n-\tmov\tr0, r5\n+\tmov\tr1, r5\n+\tldr\tr5, [sp, #56]\t@ 0x38\n \tsubs\tr6, r6, r7\n-\tldr\tr5, [sp, #68]\t@ 0x44\n \tadds\tr4, r6, #1\n \tldrd\tr7, r6, [fp, #8]\n \tstr\tr4, [r5, #0]\n \tsubs\tr6, r6, r7\n \tldrd\tip, r7, [fp, #16]\n \tadds\tr6, #1\n \tstr\tr6, [r5, #4]\n \tsub.w\tr7, r7, ip\n \tadds\tr7, #1\n \tstr\tr7, [r5, #8]\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tvldr\td17, [pc, #548]\t@ 7b8 <__gridxc_fft3d_MOD_fft3d+0x7b8>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr.w\tr2, [r9, #56]\t@ 0x38\n+\tldr.w\tr2, [r9, #32]\n+\tldrd\tr0, r3, [r9, #192]\t@ 0xc0\n+\tstr\tr2, [sp, #400]\t@ 0x190\n+\tldr.w\tr1, [r9, #132]\t@ 0x84\n \tmul.w\tr6, r4, r6\n-\tldr.w\tr1, [r9, #52]\t@ 0x34\n-\tvst1.32\t{d17}, [r3]\n-\trsb\tr2, r2, #3\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvstr\td16, [sp, #412]\t@ 0x19c\n-\tmul.w\tr7, r6, r7\n-\tvstr\td16, [sp, #260]\t@ 0x104\n-\tmul.w\tr2, r1, r2\n-\tvstr\td16, [sp, #300]\t@ 0x12c\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r9, #36\t@ 0x24\n-\tldr.w\tr0, [r9, #196]\t@ 0xc4\n-\tstr\tr7, [sp, #280]\t@ 0x118\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r9, #200]\t@ 0xc8\n-\tstr\tr7, [sp, #320]\t@ 0x140\n-\trsb\tr1, r3, #1\n+\trsb\tr2, r3, #1\n \trsb\tr3, r3, #2\n-\tvmov.32\tr7, d16[1]\n-\tldr\tr4, [sp, #36]\t@ 0x24\n+\tmul.w\tr2, r0, r2\n \tmul.w\tr3, r0, r3\n-\tmul.w\tr1, r0, r1\n-\tldr.w\tr0, [r9, #136]\t@ 0x88\n-\tnegs\tr7, r7\n-\tadd.w\tr1, r0, r1, lsl #3\n-\tstr\tr1, [sp, #248]\t@ 0xf8\n-\tldr.w\tr1, [r9, #16]\n-\tadd.w\tr0, r0, r3, lsl #3\n-\tldr.w\tr3, [r9, #44]\t@ 0x2c\n-\tstr\tr0, [sp, #288]\t@ 0x120\n-\tmov\tr0, r4\n+\tmul.w\tr7, r6, r7\n \tadd.w\tr2, r1, r2, lsl #3\n-\tldr.w\tr1, [r9, #48]\t@ 0x30\n-\trsb\tr3, r3, #1\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n+\tstr\tr2, [sp, #236]\t@ 0xec\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tadd.w\tr1, r1, r3, lsl #3\n+\tmovs\tr3, #0\n+\tstr\tr3, [sp, #392]\t@ 0x188\n+\tstr\tr7, [sp, #268]\t@ 0x10c\n+\tstr\tr3, [r2, #4]\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #248]\t@ 0xf8\n+\tstr\tr7, [sp, #304]\t@ 0x130\n+\tstr\tr3, [r2, #4]\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #284]\t@ 0x11c\n+\tstr\tr1, [sp, #272]\t@ 0x110\n+\tstr\tr3, [r2, #4]\n \tmovs\tr3, #8\n-\tstr\tr3, [sp, #408]\t@ 0x198\n \tstr\tr3, [sp, #256]\t@ 0x100\n-\tstr\tr3, [sp, #296]\t@ 0x128\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #428]\t@ 0x1ac\n-\tstr\tr3, [sp, #276]\t@ 0x114\n-\tstr\tr3, [sp, #316]\t@ 0x13c\n-\tmovw\tr3, #769\t@ 0x301\n-\tstrh.w\tr3, [sp, #416]\t@ 0x1a0\n-\tvst1.32\t{d16}, [r1]\n-\tstr\tr2, [sp, #400]\t@ 0x190\n-\tstrh.w\tr3, [sp, #264]\t@ 0x108\n-\tstrh.w\tr3, [sp, #304]\t@ 0x130\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr7, [sp, #404]\t@ 0x194\n-\tstr\tr3, [sp, #252]\t@ 0xfc\n+\tmovs\tr2, #1\n+\tstr\tr3, [sp, #244]\t@ 0xf4\n \tstr\tr3, [sp, #292]\t@ 0x124\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tstr\tr3, [sp, #388]\t@ 0x184\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh.w\tr3, [sp, #252]\t@ 0xfc\n+\tstrh.w\tr3, [sp, #288]\t@ 0x120\n+\tstrh.w\tr3, [sp, #396]\t@ 0x18c\n+\tldr.w\tr3, [r9, #40]\t@ 0x28\n+\tldr.w\tr1, [r9, #36]\t@ 0x24\n+\tstrd\tr2, r2, [sp, #260]\t@ 0x104\n+\tsubs\tr3, r2, r3\n+\tstrd\tr2, r2, [sp, #296]\t@ 0x128\n+\tldr.w\tr0, [r9, #44]\t@ 0x2c\n+\tldr\tr4, [sp, #36]\t@ 0x24\n+\tadd\tr3, r0\n+\tstrd\tr2, r3, [sp, #408]\t@ 0x198\n+\tldr.w\tr3, [r9, #52]\t@ 0x34\n+\tmov.w\tr0, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r9, #48]\t@ 0x30\n+\trsb\tr3, r3, #3\n+\tstr\tr0, [sp, #240]\t@ 0xf0\n+\tstr\tr0, [sp, #276]\t@ 0x114\n+\tmov\tr0, r4\n+\tstr\tr1, [sp, #404]\t@ 0x194\n+\tnegs\tr1, r1\n+\tmul.w\tr3, r2, r3\n+\tldr.w\tr2, [r9, #12]\n+\tstr\tr1, [sp, #384]\t@ 0x180\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr\tr3, [sp, #380]\t@ 0x17c\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldrd\tr2, r3, [sp, #88]\t@ 0x58\n \tmov\tr7, r0\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldrd\tr2, r3, [sp, #92]\t@ 0x5c\n+\tldrd\tr0, r1, [sp, #100]\t@ 0x64\n \tstr\tr2, [r3, #0]\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #136]\t@ 0x88\n \tstr\tr3, [sp, #8]\n-\tldr\tr2, [pc, #356]\t@ (7cc <__gridxc_fft3d_MOD_fft3d+0x7cc>)\n+\tldr.w\tr2, [pc, #1240]\t@ b14 <__gridxc_fft3d_MOD_fft3d+0xb14>\n \tstr\tr6, [r3, #0]\n-\tadd\tr3, sp, #164\t@ 0xa4\n+\tadd\tr3, sp, #152\t@ 0x98\n \tadd\tr2, pc\n \tstr\tr6, [r3, #0]\n \tstr\tr2, [sp, #0]\n-\tadd\tr2, sp, #184\t@ 0xb8\n+\tadd\tr2, sp, #172\t@ 0xac\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r7\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n R_ARM_THM_CALL\t__gridxc_gpfa_core_dp_MOD_gpfa_\n-\tldr\tr3, [sp, #400]\t@ 0x190\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n \tcmp\tr3, r7\n-\tbeq.n\t690 <__gridxc_fft3d_MOD_fft3d+0x690>\n+\tbeq.n\t666 <__gridxc_fft3d_MOD_fft3d+0x666>\n \tmov\tr0, r4\n \tmov\tr1, r7\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #316]\t@ (7d0 <__gridxc_fft3d_MOD_fft3d+0x7d0>)\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tldr.w\tr9, [pc, #316]\t@ 7d4 <__gridxc_fft3d_MOD_fft3d+0x7d4>\n+\tldr.w\tr3, [pc, #1200]\t@ b18 <__gridxc_fft3d_MOD_fft3d+0xb18>\n \tmovs\tr6, #0\n-\tadd\tr3, pc\n+\tldr.w\tr9, [pc, #1196]\t@ b1c <__gridxc_fft3d_MOD_fft3d+0xb1c>\n \tmovs\tr7, #8\n+\tadd\tr3, pc\n \tmov\tfp, r3\n-\tadds\tr3, #64\t@ 0x40\n+\tadds\tr3, #60\t@ 0x3c\n \tadd\tr9, pc\n \tmov\tr4, r3\n \tadd.w\tr2, r9, #12\n \tadd.w\tr3, r9, #44\t@ 0x2c\n-\tadd.w\tr1, fp, #136\t@ 0x88\n+\tadd.w\tr1, fp, #132\t@ 0x84\n \tadd.w\tr0, r9, #8\n \tstr\tr3, [sp, #0]\n \tmov\tr3, r4\n \tmov\tr5, r2\n \tbl\t0 <__gridxc_mesh3d_MOD_redistributemeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_redistributemeshdata\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr1, sp, #328\t@ 0x148\n-\tstr\tr2, [sp, #360]\t@ 0x168\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadd\tr1, sp, #308\t@ 0x134\n+\tstr\tr2, [sp, #332]\t@ 0x14c\n \tmov\tr0, r4\n \tldr\tr2, [sp, #52]\t@ 0x34\n-\tstr\tr2, [sp, #352]\t@ 0x160\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tstr\tr2, [sp, #384]\t@ 0x180\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tstr\tr2, [sp, #376]\t@ 0x178\n+\tstr\tr2, [sp, #364]\t@ 0x16c\n \tldr\tr2, [sp, #64]\t@ 0x40\n-\tstr\tr2, [sp, #396]\t@ 0x18c\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #356]\t@ 0x164\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr2, [sp, #376]\t@ 0x178\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #340]\t@ 0x154\n+\tstr\tr2, [sp, #368]\t@ 0x170\n \tldr\tr3, [sp, #32]\n-\tstr\tr2, [sp, #388]\t@ 0x184\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tstr\tr3, [sp, #372]\t@ 0x174\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #352]\t@ 0x160\n \tmov.w\tr3, #772\t@ 0x304\n-\tstr\tr2, [sp, #332]\t@ 0x14c\n-\tvstr\td8, [sp, #340]\t@ 0x154\n-\tstr.w\tr8, [sp, #364]\t@ 0x16c\n-\tstrh.w\tr3, [sp, #344]\t@ 0x158\n+\tstrd\tr6, r6, [sp, #320]\t@ 0x140\n+\tstr.w\tr8, [sp, #344]\t@ 0x158\n+\tstrh.w\tr3, [sp, #324]\t@ 0x144\n \tmovs\tr3, #1\n-\tstr.w\tsl, [sp, #328]\t@ 0x148\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tstr\tr6, [sp, #356]\t@ 0x164\n-\tstr\tr6, [sp, #368]\t@ 0x170\n-\tstr\tr6, [sp, #380]\t@ 0x17c\n-\tstr\tr7, [sp, #348]\t@ 0x15c\n-\tstr\tr7, [sp, #336]\t@ 0x150\n+\tstr.w\tsl, [sp, #308]\t@ 0x134\n+\tstr\tr3, [sp, #372]\t@ 0x174\n+\tstr\tr2, [sp, #312]\t@ 0x138\n+\tstr\tr6, [sp, #336]\t@ 0x150\n+\tstr\tr6, [sp, #348]\t@ 0x15c\n+\tstr\tr6, [sp, #360]\t@ 0x168\n+\tstr\tr7, [sp, #328]\t@ 0x148\n+\tstr\tr7, [sp, #316]\t@ 0x13c\n \tbl\t0 <_gfortran_associated>\n R_ARM_THM_CALL\t_gfortran_associated\n-\tldr.w\tr2, [fp, #124]\t@ 0x7c\n-\tmovs\tr3, #1\n-\tcmp\tr2, r6\n+\tldr.w\tr3, [fp, #120]\t@ 0x78\n+\tcmp\tr0, r6\n \tit\tne\n-\tcmpne\tr0, r6\n-\tbeq.w\ta38 <__gridxc_fft3d_MOD_fft3d+0xa38>\n-\tldr\tr3, [sp, #144]\t@ 0x90\n+\tcmpne\tr3, r6\n+\tbeq.w\t9ca <__gridxc_fft3d_MOD_fft3d+0x9ca>\n+\tldr\tr3, [sp, #128]\t@ 0x80\n \tcmp\tr3, #0\n-\tble.n\t7da <__gridxc_fft3d_MOD_fft3d+0x7da>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tble.n\t78e <__gridxc_fft3d_MOD_fft3d+0x78e>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tcmp\tr3, #0\n-\tble.n\t7da <__gridxc_fft3d_MOD_fft3d+0x7da>\n+\tble.n\t78e <__gridxc_fft3d_MOD_fft3d+0x78e>\n \tldr\tr2, [sp, #32]\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \torrs\tr3, r2\n-\tldr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #52]\t@ 0x34\n \torrs\tr3, r2\n-\tbmi.n\t7da <__gridxc_fft3d_MOD_fft3d+0x7da>\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tldr\tr1, [sp, #148]\t@ 0x94\n+\tbmi.n\t78e <__gridxc_fft3d_MOD_fft3d+0x78e>\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tldr\tr1, [sp, #132]\t@ 0x84\n \tldr\tr3, [r2, #4]\n \tldr\tr2, [r2, #8]\n \tmul.w\tr1, r3, r1\n \tmov\tr3, r1\n \tmul.w\tr3, r2, r3\n \tvmov\ts15, r3\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tvcvt.f64.s32\td16, s15\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tvcvt.f64.s32\td7, s15\n \tcmp\tr3, #1\n-\tvdiv.f64\td17, d18, d16\n-\tbne.w\tac4 <__gridxc_fft3d_MOD_fft3d+0xac4>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tvdiv.f64\td6, d5, d7\n+\tbne.w\ta5c <__gridxc_fft3d_MOD_fft3d+0xa5c>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tmov.w\tr6, r8, lsl #3\n-\tldr\tr0, [sp, #56]\t@ 0x38\n+\tldr\tr4, [sp, #64]\t@ 0x40\n \tldr\tr5, [sp, #32]\n \tadd.w\tr3, sl, r3, lsl #3\n-\tmov\tr2, r0\n+\tmov\tr2, r4\n \tadd.w\tr1, r3, #8\n \tmovs\tr3, #0\n-\tmov.w\tr9, r0, lsl #3\n-\tmov\tr4, r3\n-\tadd.w\tlr, r1, r4, lsl #3\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tmov\tip, r4\n+\tmov.w\tr9, r4, lsl #3\n+\tmov\tr7, r3\n+\tmov\tr0, r3\n+\tadd.w\tlr, r1, r7, lsl #3\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tmov\tip, r7\n \tmov.w\tfp, #0\n-\tstr\tr4, [sp, #32]\n-\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr7, [sp, #32]\n+\tstr\tr0, [sp, #44]\t@ 0x2c\n \tmov\tr0, lr\n \tmov\tr4, ip\n \tmovs\tr7, #0\n \tadd.w\tr3, sl, r4, lsl #3\n-\tvldr\td16, [r3]\n-\tvmul.f64\td16, d17, d16\n-\tvstmia\tr3!, {d16}\n+\tvldr\td7, [r3]\n+\tvmul.f64\td7, d6, d7\n+\tvstmia\tr3!, {d7}\n \tcmp\tr0, r3\n-\tbne.n\t796 <__gridxc_fft3d_MOD_fft3d+0x796>\n+\tbne.n\t76a <__gridxc_fft3d_MOD_fft3d+0x76a>\n \tadd\tr4, r8\n \tadd\tr0, r6\n \tadds\tr3, r7, #1\n-\tcmp\tr5, r7\n-\tbeq.w\ta10 <__gridxc_fft3d_MOD_fft3d+0xa10>\n+\tcmp\tr7, r5\n+\tbeq.w\t9a2 <__gridxc_fft3d_MOD_fft3d+0x9a2>\n \tmov\tr7, r3\n-\tb.n\t792 <__gridxc_fft3d_MOD_fft3d+0x792>\n-\tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x000002b8\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000296\n- R_ARM_REL32\t.data\n-\t.word\t0x00000298\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000015c\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000130\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000012c\n- R_ARM_REL32\t.data\n+\tb.n\t766 <__gridxc_fft3d_MOD_fft3d+0x766>\n+\tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr5, [sp, #32]\n-\tldr\tr6, [pc, #864]\t@ (b3c <__gridxc_fft3d_MOD_fft3d+0xb3c>)\n+\tldr\tr6, [pc, #912]\t@ (b20 <__gridxc_fft3d_MOD_fft3d+0xb20>)\n \tadd\tr6, pc\n-\tadd.w\tr7, r6, #136\t@ 0x88\n-\tadd.w\tr1, r6, #64\t@ 0x40\n+\tadd.w\tr7, r6, #132\t@ 0x84\n+\tadd.w\tr1, r6, #60\t@ 0x3c\n \tmov\tr0, r7\n \tbl\t0 <_gfortran_associated>\n R_ARM_THM_CALL\t_gfortran_associated\n-\tldr.w\tr3, [r6, #196]\t@ 0xc4\n+\tldr.w\tr3, [r6, #192]\t@ 0xc0\n \tcmp\tr3, #0\n \tit\tne\n \tcmpne\tr0, #0\n-\tit\tne\n+\tittet\tne\n+\tmovne\tr3, #0\n \tmovne\tr2, #1\n-\tit\teq\n \tmoveq\tr2, #0\n-\tbeq.w\tab4 <__gridxc_fft3d_MOD_fft3d+0xab4>\n-\tmovs\tr3, #0\n-\tstr.w\tr3, [r6, #136]\t@ 0x88\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n-\tmovs\tr4, #0\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstr\tr3, [sp, #424]\t@ 0x1a8\n+\tstrne.w\tr3, [r6, #132]\t@ 0x84\n+\tbeq.w\ta4c <__gridxc_fft3d_MOD_fft3d+0xa4c>\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tmovs\tr7, #0\n+\tmovs\tr3, #8\n+\tstr\tr7, [sp, #392]\t@ 0x188\n+\tstr\tr3, [sp, #400]\t@ 0x190\n+\tstr\tr7, [r2, #4]\n+\tstr\tr3, [sp, #388]\t@ 0x184\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #412]\t@ 0x19c\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #404]\t@ 0x194\n \tldr\tr3, [sp, #32]\n-\tstr\tr3, [sp, #444]\t@ 0x1bc\n-\tldr\tr5, [pc, #804]\t@ (b40 <__gridxc_fft3d_MOD_fft3d+0xb40>)\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr3, [sp, #456]\t@ 0x1c8\n-\tadd\tr5, pc\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tadd.w\tr6, r5, #64\t@ 0x40\n-\tstr\tr3, [sp, #448]\t@ 0x1c0\n-\tmov\tr0, r6\n+\tstr\tr3, [sp, #424]\t@ 0x1a8\n+\tldr.w\tr9, [pc, #844]\t@ b24 <__gridxc_fft3d_MOD_fft3d+0xb24>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #436]\t@ 0x1b4\n+\tadd\tr9, pc\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tstr\tr3, [sp, #468]\t@ 0x1d4\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #460]\t@ 0x1cc\n+\tadd.w\tr6, r9, #60\t@ 0x3c\n+\tstr\tr3, [sp, #428]\t@ 0x1ac\n+\tmov\tr0, r6\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #440]\t@ 0x1b8\n \tldr\tr1, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tstr\tr3, [sp, #404]\t@ 0x194\n-\tmovs\tr3, #8\n-\tvstr\td16, [sp, #412]\t@ 0x19c\n-\tstr\tr3, [sp, #420]\t@ 0x1a4\n-\tstr\tr3, [sp, #408]\t@ 0x198\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #384]\t@ 0x180\n \tmov.w\tr3, #772\t@ 0x304\n-\tstr.w\tr8, [sp, #436]\t@ 0x1b4\n-\tstrh.w\tr3, [sp, #416]\t@ 0x1a0\n+\tstr.w\tr8, [sp, #416]\t@ 0x1a0\n+\tstrh.w\tr3, [sp, #396]\t@ 0x18c\n \tmovs\tr3, #1\n-\tstr.w\tsl, [sp, #400]\t@ 0x190\n-\tstr\tr3, [sp, #464]\t@ 0x1d0\n-\tstr\tr4, [sp, #428]\t@ 0x1ac\n-\tstr\tr4, [sp, #440]\t@ 0x1b8\n-\tstr\tr4, [sp, #452]\t@ 0x1c4\n+\tstr.w\tsl, [sp, #380]\t@ 0x17c\n+\tstr\tr3, [sp, #444]\t@ 0x1bc\n+\tstr\tr7, [sp, #408]\t@ 0x198\n+\tstr\tr7, [sp, #420]\t@ 0x1a4\n+\tstr\tr7, [sp, #432]\t@ 0x1b0\n \tbl\t0 <_gfortran_associated>\n R_ARM_THM_CALL\t_gfortran_associated\n-\tldr\tr3, [r5, #124]\t@ 0x7c\n-\tcmp\tr3, r4\n-\tit\tne\n-\tcmpne\tr0, r4\n+\tldr.w\tr3, [r9, #120]\t@ 0x78\n+\tcmp\tr3, r7\n \tit\tne\n+\tcmpne\tr0, r7\n+\titte\tne\n+\tstrne.w\tr7, [r9, #60]\t@ 0x3c\n \tmovne\tr2, #1\n-\tit\teq\n \tmoveq\tr2, #0\n-\tbeq.w\taa4 <__gridxc_fft3d_MOD_fft3d+0xaa4>\n-\tstr\tr4, [r5, #64]\t@ 0x40\n-\tldr\tr2, [pc, #712]\t@ (b44 <__gridxc_fft3d_MOD_fft3d+0xb44>)\n-\tldr\tr3, [pc, #716]\t@ (b48 <__gridxc_fft3d_MOD_fft3d+0xb48>)\n+\tbeq.w\ta3c <__gridxc_fft3d_MOD_fft3d+0xa3c>\n+\tldr\tr2, [pc, #760]\t@ (b28 <__gridxc_fft3d_MOD_fft3d+0xb28>)\n+\tldr\tr3, [pc, #684]\t@ (adc <__gridxc_fft3d_MOD_fft3d+0xadc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #476]\t@ 0x1dc\n+\tldr\tr3, [sp, #452]\t@ 0x1c4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\tb38 <__gridxc_fft3d_MOD_fft3d+0xb38>\n-\tldr\tr3, [pc, #700]\t@ (b4c <__gridxc_fft3d_MOD_fft3d+0xb4c>)\n+\tbne.w\tad0 <__gridxc_fft3d_MOD_fft3d+0xad0>\n+\tldr\tr3, [pc, #744]\t@ (b2c <__gridxc_fft3d_MOD_fft3d+0xb2c>)\n \tmovs\tr1, #6\n \tldr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr0, [pc, #696]\t@ (b50 <__gridxc_fft3d_MOD_fft3d+0xb50>)\n+\tldr\tr0, [pc, #740]\t@ (b30 <__gridxc_fft3d_MOD_fft3d+0xb30>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #484\t@ 0x1e4\n-\tvpop\t{d8-d9}\n+\tadd\tsp, #460\t@ 0x1cc\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n-\tldr\tr7, [pc, #680]\t@ (b54 <__gridxc_fft3d_MOD_fft3d+0xb54>)\n-\tmov.w\tr3, #256\t@ 0x100\n-\tadd\tr2, sp, #160\t@ 0xa0\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tadd\tr7, pc\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tmov\tr9, r3\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tmov\tr3, r7\n-\tldr\tr4, [pc, #664]\t@ (b58 <__gridxc_fft3d_MOD_fft3d+0xb58>)\n-\tldr\tr0, [r2, #0]\n+\tldr\tr3, [pc, #728]\t@ (b34 <__gridxc_fft3d_MOD_fft3d+0xb34>)\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tadd\tr3, pc\n+\tstr.w\tr8, [sp, #96]\t@ 0x60\n \tldr\tr1, [r2, #4]\n-\tadd\tr4, pc\n+\tldr\tr0, [r2, #0]\n \tldr\tr2, [r2, #8]\n \tstmia\tr3!, {r0, r1, r2}\n-\tadd\tr2, sp, #412\t@ 0x19c\n-\tldr\tr3, [pc, #656]\t@ (b5c <__gridxc_fft3d_MOD_fft3d+0xb5c>)\n-\tldr\tr6, [sp, #32]\n-\tadd\tr3, pc\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tmovs\tr3, #2\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tadd\tr3, sp, #188\t@ 0xbc\n-\tstr\tr2, [sp, #80]\t@ 0x50\n+\tadd\tr2, sp, #148\t@ 0x94\n+\tldr\tr1, [pc, #712]\t@ (b38 <__gridxc_fft3d_MOD_fft3d+0xb38>)\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tmov\tr5, r2\n+\tmov.w\tr3, #256\t@ 0x100\n+\tadd\tr1, pc\n \tmov\tfp, r3\n-\tadd\tr2, sp, #420\t@ 0x1a4\n-\tstr\tr4, [sp, #100]\t@ 0x64\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tadd\tr2, sp, #400\t@ 0x190\n-\tstr.w\tr9, [sp, #32]\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tadd.w\tr2, r7, #16\n-\tstr\tr2, [sp, #104]\t@ 0x68\n-\tadds\tr2, r4, #4\n-\tstr\tr2, [sp, #116]\t@ 0x74\n-\tadd.w\tr2, r7, #36\t@ 0x24\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #4]\n-\tmovs\tr4, #1\n-\tldr\tr3, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tstr\tr1, [sp, #112]\t@ 0x70\n+\tmovs\tr3, #2\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr3, sp, #176\t@ 0xb0\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tadd\tr3, sp, #392\t@ 0x188\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tadd\tr3, sp, #380\t@ 0x17c\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tadds\tr3, r1, #4\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tmovs\tr7, #0\n \tstr\tr3, [sp, #0]\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #24]\n-\tstrd\tr3, r3, [sp, #12]\n-\tstr\tr3, [sp, #8]\n+\tmov\tr2, r5\n+\tldr\tr3, [pc, #672]\t@ (b3c <__gridxc_fft3d_MOD_fft3d+0xb3c>)\n+\tmovs\tr6, #1\n+\tldr\tr4, [sp, #116]\t@ 0x74\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #4]\n \tmovs\tr3, #11\n \tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr0, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tmov\tr0, r4\n+\tstr\tr7, [sp, #24]\n+\tsubs\tr4, #12\n \tmov\tr1, r3\n+\tstrd\tr7, r7, [sp, #12]\n+\tstr\tr7, [sp, #8]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n-\tldr.w\tr9, [sp, #40]\t@ 0x28\n-\tstr.w\tr8, [sp, #92]\t@ 0x5c\n-\tmov\tr8, r9\n-\tmov\tr9, r6\n-\tmov\tr6, fp\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tldr\tr2, [r7, #56]\t@ 0x38\n-\tldr\tr1, [r7, #16]\n-\tsub.w\tip, r4, r2\n-\tldr\tr2, [r7, #52]\t@ 0x34\n-\tvld1.32\t{d16}, [r3]\n-\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr.w\tr9, [sp, #92]\t@ 0x5c\n+\tldr.w\tr8, [sp, #44]\t@ 0x2c\n+\tstr.w\tsl, [sp, #100]\t@ 0x64\n+\tmov\tsl, r9\n+\tmov\tr9, r8\n+\tmov\tr8, r5\n+\tldr\tr3, [r4, #52]\t@ 0x34\n+\tldr\tr1, [r4, #48]\t@ 0x30\n+\tsubs\tr3, r6, r3\n+\tldr\tr0, [r4, #40]\t@ 0x28\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\trsb\tr0, r0, #1\n+\tldr\tr5, [r4, #36]\t@ 0x24\n+\tmul.w\tr3, r1, r3\n+\tldr\tr1, [r4, #12]\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tldr\tr1, [r4, #44]\t@ 0x2c\n+\tadd\tr0, r1\n+\tldr\tr1, [r4, #32]\n+\tstr\tr1, [sp, #400]\t@ 0x190\n+\tstrd\tr7, r7, [r2]\n+\tstr\tr0, [sp, #412]\t@ 0x19c\n \tldr\tr0, [sp, #36]\t@ 0x24\n-\tmul.w\tip, r2, ip\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tvmov.32\tr5, d16[1]\n-\tvstr\td8, [r3]\n-\trsb\tr2, r2, #1\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tadd.w\tr1, r1, ip, lsl #3\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tstr\tr2, [sp, #432]\t@ 0x1b0\n-\tmovs\tr2, #8\n-\tstr\tr2, [sp, #408]\t@ 0x198\n-\tmovs\tr2, #1\n-\tstr\tr2, [sp, #428]\t@ 0x1ac\n-\tmovw\tr2, #769\t@ 0x301\n-\tstrh.w\tr2, [sp, #416]\t@ 0x1a0\n+\tstr\tr3, [sp, #380]\t@ 0x17c\n+\tmovs\tr3, #8\n+\tstr\tr5, [sp, #404]\t@ 0x194\n \tnegs\tr5, r5\n-\tvst1.32\t{d16}, [r3]\n-\tstrd\tr1, r5, [sp, #400]\t@ 0x190\n+\tstr\tr3, [sp, #388]\t@ 0x184\n+\tmovs\tr3, #1\n+\tstr\tr5, [sp, #384]\t@ 0x180\n+\tstr\tr3, [sp, #408]\t@ 0x198\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh.w\tr3, [sp, #396]\t@ 0x18c\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tmov\tr2, r6\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tmov\tr3, r8\n+\tmov\tr3, r9\n+\tmov\tr2, sl\n+\tmov\tr1, r8\n \tmov\tr5, r0\n \tbl\t0 <__gridxc_fft_gpfa_MOD_setgpfa_check>\n R_ARM_THM_CALL\t__gridxc_fft_gpfa_MOD_setgpfa_check\n-\tldr\tr2, [sp, #400]\t@ 0x190\n-\tcmp\tr2, r5\n-\tbeq.n\t9a0 <__gridxc_fft3d_MOD_fft3d+0x9a0>\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tcmp\tr3, r5\n+\tbeq.n\t934 <__gridxc_fft3d_MOD_fft3d+0x934>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tmov\tr1, r5\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tadds\tr4, #1\n-\tadds\tr6, #4\n-\tadd.w\tr8, r8, #4\n-\tcmp\tr4, #4\n-\tbne.n\t930 <__gridxc_fft3d_MOD_fft3d+0x930>\n-\tldrd\tr1, r3, [fp]\n-\tmov\tr6, r9\n-\tldr\tr0, [sp, #32]\n-\tldr.w\tr8, [sp, #92]\t@ 0x5c\n-\tldr.w\tr2, [fp, #8]\n-\tcmp\tr0, r1\n-\tblt.n\t9de <__gridxc_fft3d_MOD_fft3d+0x9de>\n-\tcmp\tr3, r0\n-\tbgt.n\t9de <__gridxc_fft3d_MOD_fft3d+0x9de>\n-\tcmp\tr2, r0\n-\tbgt.n\t9de <__gridxc_fft3d_MOD_fft3d+0x9de>\n-\tstr.w\tr9, [sp, #32]\n-\tldr\tr2, [pc, #400]\t@ (b60 <__gridxc_fft3d_MOD_fft3d+0xb60>)\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tadds\tr6, #1\n+\tadd.w\tsl, sl, #4\n+\tadd.w\tr9, r9, #4\n+\tcmp\tr6, #4\n+\tbne.n\t8ce <__gridxc_fft3d_MOD_fft3d+0x8ce>\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tmov\tr5, r8\n+\tldr.w\tsl, [sp, #100]\t@ 0x64\n+\tldrd\tr0, r3, [r2]\n+\tldr\tr1, [r2, #8]\n+\tcmp\tfp, r0\n+\tblt.n\t972 <__gridxc_fft3d_MOD_fft3d+0x972>\n+\tcmp\tr3, fp\n+\tbgt.n\t972 <__gridxc_fft3d_MOD_fft3d+0x972>\n+\tcmp\tr1, fp\n+\tbgt.n\t972 <__gridxc_fft3d_MOD_fft3d+0x972>\n+\tldr.w\tr8, [sp, #96]\t@ 0x60\n+\tldr\tr2, [pc, #476]\t@ (b40 <__gridxc_fft3d_MOD_fft3d+0xb40>)\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tadd\tr2, pc\n \tadd.w\tr1, r2, #12\n \tbl\t0 <__gridxc_mesh3d_MOD_fftmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_fftmeshdistr\n-\tb.w\t130 <__gridxc_fft3d_MOD_fft3d+0x130>\n+\tb.w\t140 <__gridxc_fft3d_MOD_fft3d+0x140>\n+\tcmp\tr3, r0\n+\tit\tlt\n+\tmovlt\tr3, r0\n \tcmp\tr3, r1\n \tit\tlt\n \tmovlt\tr3, r1\n-\tcmp\tr3, r2\n-\tit\tlt\n-\tmovlt\tr3, r2\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr3, [sp, #32]\n-\tstr\tr3, [r2, #0]\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr3, [r5, #0]\n+\tmov\tfp, r3\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tcmp\tr3, #1\n-\tbeq.n\ta90 <__gridxc_fft3d_MOD_fft3d+0xa90>\n+\tbeq.n\ta26 <__gridxc_fft3d_MOD_fft3d+0xa26>\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tb.n\t8fa <__gridxc_fft3d_MOD_fft3d+0x8fa>\n-\tldr\tr3, [pc, #356]\t@ (b64 <__gridxc_fft3d_MOD_fft3d+0xb64>)\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tb.n\t892 <__gridxc_fft3d_MOD_fft3d+0x892>\n+\tldr\tr3, [pc, #344]\t@ (ae8 <__gridxc_fft3d_MOD_fft3d+0xae8>)\n \tmovs\tr1, #50\t@ 0x32\n \tldr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr0, [pc, #356]\t@ (b68 <__gridxc_fft3d_MOD_fft3d+0xb68>)\n+\tldr\tr0, [pc, #428]\t@ (b44 <__gridxc_fft3d_MOD_fft3d+0xb44>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.w\tde <__gridxc_fft3d_MOD_fft3d+0xde>\n+\tb.w\te8 <__gridxc_fft3d_MOD_fft3d+0xe8>\n \tadd\tip, r2\n \tadd\tlr, r9\n \tadd.w\tr3, fp, #1\n \tcmp\tfp, r1\n-\tbeq.n\ta20 <__gridxc_fft3d_MOD_fft3d+0xa20>\n+\tbeq.n\t9b2 <__gridxc_fft3d_MOD_fft3d+0x9b2>\n \tmov\tfp, r3\n-\tb.n\t78c <__gridxc_fft3d_MOD_fft3d+0x78c>\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tldr\tr4, [sp, #32]\n-\tldr\tr7, [sp, #112]\t@ 0x70\n-\tadd\tr4, r0\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tadds\tr0, r3, #1\n-\tcmp\tr7, r3\n-\tbeq.w\t7d8 <__gridxc_fft3d_MOD_fft3d+0x7d8>\n-\tmov\tr3, r0\n-\tb.n\t77a <__gridxc_fft3d_MOD_fft3d+0x77a>\n+\tb.n\t760 <__gridxc_fft3d_MOD_fft3d+0x760>\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr7, [sp, #32]\n+\tldr\tr4, [sp, #108]\t@ 0x6c\n+\tadd\tr7, r3\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tadds\tr3, r0, #1\n+\tcmp\tr4, r0\n+\tbeq.w\t78c <__gridxc_fft3d_MOD_fft3d+0x78c>\n+\tmov\tr0, r3\n+\tb.n\t74e <__gridxc_fft3d_MOD_fft3d+0x74e>\n \tldr\tr0, [sp, #36]\t@ 0x24\n-\tmov\tr2, r4\n+\tadd.w\tr3, r9, #20\n \tstr\tr0, [sp, #0]\n-\tmov.w\tr0, #772\t@ 0x304\n-\tvstr\td8, [sp, #412]\t@ 0x19c\n+\tmov\tr2, r4\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tmov\tr1, r5\n-\tstrh.w\tr0, [sp, #416]\t@ 0x1a0\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tstr\tr0, [sp, #432]\t@ 0x1b0\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tstr\tr0, [sp, #424]\t@ 0x1a8\n-\tldr\tr0, [sp, #32]\n+\tstr\tr3, [sp, #4]\n+\tstr\tr7, [sp, #400]\t@ 0x190\n+\tstr\tr6, [sp, #392]\t@ 0x188\n+\tstr\tr6, [r0, #4]\n+\tmov.w\tr0, #772\t@ 0x304\n+\tstrh.w\tr0, [sp, #396]\t@ 0x18c\n+\tmovs\tr0, #1\n \tstr\tr0, [sp, #444]\t@ 0x1bc\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tstr\tr0, [sp, #456]\t@ 0x1c8\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tstr\tr0, [sp, #448]\t@ 0x1c0\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tstr\tr0, [sp, #468]\t@ 0x1d4\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tstr\tr0, [sp, #412]\t@ 0x19c\n \tldr\tr0, [sp, #60]\t@ 0x3c\n-\tstr\tr0, [sp, #460]\t@ 0x1cc\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tstr\tr3, [sp, #464]\t@ 0x1d0\n-\tadd.w\tr3, r9, #20\n \tstr\tr0, [sp, #404]\t@ 0x194\n-\tstr\tr3, [sp, #4]\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tstr\tr7, [sp, #420]\t@ 0x1a4\n-\tstr\tr7, [sp, #408]\t@ 0x198\n-\tstr\tr6, [sp, #428]\t@ 0x1ac\n-\tstr\tr6, [sp, #440]\t@ 0x1b8\n-\tstr\tr6, [sp, #452]\t@ 0x1c4\n-\tstr.w\tr8, [sp, #436]\t@ 0x1b4\n-\tstr.w\tsl, [sp, #400]\t@ 0x190\n+\tldr\tr0, [sp, #32]\n+\tstr\tr0, [sp, #424]\t@ 0x1a8\n+\tldr\tr0, [sp, #52]\t@ 0x34\n+\tstr\tr0, [sp, #436]\t@ 0x1b4\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tstr\tr0, [sp, #428]\t@ 0x1ac\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tstr\tr0, [sp, #448]\t@ 0x1c0\n+\tldr\tr0, [sp, #68]\t@ 0x44\n+\tstr\tr0, [sp, #440]\t@ 0x1b8\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tstr\tr7, [sp, #388]\t@ 0x184\n+\tstr\tr6, [sp, #408]\t@ 0x198\n+\tstr\tr6, [sp, #420]\t@ 0x1a4\n+\tstr\tr6, [sp, #432]\t@ 0x1b0\n+\tstr.w\tr8, [sp, #416]\t@ 0x1a0\n+\tstr.w\tsl, [sp, #380]\t@ 0x17c\n+\tstr\tr0, [sp, #384]\t@ 0x180\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tb.n\t71c <__gridxc_fft3d_MOD_fft3d+0x71c>\n-\tldr\tr3, [pc, #208]\t@ (b64 <__gridxc_fft3d_MOD_fft3d+0xb64>)\n+\tb.n\t6ee <__gridxc_fft3d_MOD_fft3d+0x6ee>\n+\tldr\tr3, [pc, #192]\t@ (ae8 <__gridxc_fft3d_MOD_fft3d+0xae8>)\n \tmovs\tr1, #42\t@ 0x2a\n \tldr\tr2, [sp, #76]\t@ 0x4c\n-\tstr\tr6, [sp, #32]\n-\tldr\tr0, [pc, #208]\t@ (b6c <__gridxc_fft3d_MOD_fft3d+0xb6c>)\n+\tldr\tr0, [pc, #280]\t@ (b48 <__gridxc_fft3d_MOD_fft3d+0xb48>)\n+\tldr.w\tr8, [sp, #96]\t@ 0x60\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t9cc <__gridxc_fft3d_MOD_fft3d+0x9cc>\n-\tldr\tr1, [pc, #200]\t@ (b70 <__gridxc_fft3d_MOD_fft3d+0xb70>)\n+\tb.n\t960 <__gridxc_fft3d_MOD_fft3d+0x960>\n+\tldr\tr1, [pc, #268]\t@ (b4c <__gridxc_fft3d_MOD_fft3d+0xb4c>)\n \tmovs\tr3, #28\n \tmov\tr0, r6\n \tstr\tr2, [sp, #0]\n \tadd\tr1, pc\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tb.n\t878 <__gridxc_fft3d_MOD_fft3d+0x878>\n-\tldr\tr1, [pc, #188]\t@ (b74 <__gridxc_fft3d_MOD_fft3d+0xb74>)\n+\tb.n\t82c <__gridxc_fft3d_MOD_fft3d+0x82c>\n+\tldr\tr1, [pc, #256]\t@ (b50 <__gridxc_fft3d_MOD_fft3d+0xb50>)\n \tmov\tr0, r7\n \tmovs\tr3, #28\n \tstr\tr2, [sp, #0]\n \tadd\tr1, pc\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tb.n\t808 <__gridxc_fft3d_MOD_fft3d+0x808>\n+\tb.n\t7ba <__gridxc_fft3d_MOD_fft3d+0x7ba>\n \tmovs\tr2, #0\n-\tldr\tr7, [sp, #44]\t@ 0x2c\n+\tldr\tr4, [sp, #40]\t@ 0x28\n \tldr\tr5, [sp, #32]\n \tlsls\tr0, r3, #3\n-\tldr.w\tfp, [sp, #56]\t@ 0x38\n+\tldr.w\tfp, [sp, #64]\t@ 0x40\n \tmov\tr1, r2\n-\tldr\tr4, [sp, #48]\t@ 0x30\n+\tldr\tr6, [sp, #52]\t@ 0x34\n \tmov\tr3, r2\n \tmov.w\tr9, #0\n \tmov\tip, r3\n \tmov.w\tlr, #0\n \tstr.w\tfp, [sp, #32]\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tadd.w\tr4, sl, ip, lsl #3\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tadd.w\tr6, sl, ip, lsl #3\n \tmov.w\tfp, #0\n-\tvldr\td16, [r4]\n-\tcmp\tfp, r7\n+\tvldr\td7, [r6]\n+\tcmp\tr4, fp\n \tadd.w\tfp, fp, #1\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r4]\n-\tadd\tr4, r0\n-\tbne.n\taee <__gridxc_fft3d_MOD_fft3d+0xaee>\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r6]\n+\tadd\tr6, r0\n+\tbne.n\ta86 <__gridxc_fft3d_MOD_fft3d+0xa86>\n \tadd\tip, r8\n-\tadd.w\tr4, lr, #1\n+\tadd.w\tr6, lr, #1\n \tcmp\tr5, lr\n-\tbeq.n\tb12 <__gridxc_fft3d_MOD_fft3d+0xb12>\n-\tmov\tlr, r4\n-\tb.n\tae6 <__gridxc_fft3d_MOD_fft3d+0xae6>\n+\tbeq.n\taaa <__gridxc_fft3d_MOD_fft3d+0xaaa>\n+\tmov\tlr, r6\n+\tb.n\ta7e <__gridxc_fft3d_MOD_fft3d+0xa7e>\n \tldr.w\tfp, [sp, #32]\n-\tadd.w\tr6, r9, #1\n-\tldr\tr4, [sp, #40]\t@ 0x28\n+\tadd.w\tr7, r9, #1\n+\tldr\tr6, [sp, #40]\t@ 0x28\n \tadd\tr3, fp\n-\tcmp\tr4, r9\n-\tbeq.n\tb26 <__gridxc_fft3d_MOD_fft3d+0xb26>\n-\tmov\tr9, r6\n-\tb.n\tada <__gridxc_fft3d_MOD_fft3d+0xada>\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr6, [sp, #112]\t@ 0x70\n+\tcmp\tr6, r9\n+\tbeq.n\tabe <__gridxc_fft3d_MOD_fft3d+0xabe>\n+\tmov\tr9, r7\n+\tb.n\ta72 <__gridxc_fft3d_MOD_fft3d+0xa72>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr7, [sp, #108]\t@ 0x6c\n \tadd\tr2, r3\n \tadds\tr3, r1, #1\n-\tcmp\tr6, r1\n-\tbeq.w\t7d8 <__gridxc_fft3d_MOD_fft3d+0x7d8>\n+\tcmp\tr7, r1\n+\tbeq.w\t78a <__gridxc_fft3d_MOD_fft3d+0x78a>\n \tmov\tr1, r3\n-\tb.n\tad4 <__gridxc_fft3d_MOD_fft3d+0xad4>\n+\tb.n\ta6c <__gridxc_fft3d_MOD_fft3d+0xa6c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x0000035c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000031c\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002c4\n+\t.word\t0x00000ab0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000ab2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t...\n R_ARM_GOT32\t__stack_chk_guard\n+ R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_start\n+\t.word\t0x00000a54\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x000009ec\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x000009e4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000009aa\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000926\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000007c6\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000078c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000078a\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000710\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000005fa\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000005f8\n+ R_ARM_REL32\t.data\n+\t.word\t0x000004ce\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000004a2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000004a0\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000038c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000344\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002f4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_stop\n-\t.word\t0x000002b4\n+\t.word\t0x000002e0\n R_ARM_REL32\t.LC0\n-\t.word\t0x0000029e\n+\t.word\t0x000002d4\n R_ARM_REL32\t.bss\n-\t.word\t0x00000292\n+\t.word\t0x000002be\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000028a\n+\t.word\t0x00000298\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000018c\n+\t.word\t0x000001d8\n R_ARM_REL32\t.data\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000015e\n+\t.word\t0x000001a8\n R_ARM_REL32\t.LC1\n-\t.word\t0x000000cc\n+\t.word\t0x00000110\n R_ARM_REL32\t.LC7\n-\t.word\t0x000000c0\n+\t.word\t0x00000104\n R_ARM_REL32\t.LC6\n-\t.word\t0x000000b4\n+\t.word\t0x000000f8\n R_ARM_REL32\t.LC6\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -17,29 +17,29 @@\n 0x000000e0 6833645f 4d4f445f 72656469 73747269 h3d_MOD_redistri\n 0x000000f0 62757465 6d657368 64617461 005f6766 butemeshdata._gf\n 0x00000100 6f727472 616e5f69 6e746572 6e616c5f ortran_internal_\n 0x00000110 7061636b 005f5f67 72696478 635f6770 pack.__gridxc_gp\n 0x00000120 66615f63 6f72655f 64705f4d 4f445f67 fa_core_dp_MOD_g\n 0x00000130 7066615f 005f6766 6f727472 616e5f69 pfa_._gfortran_i\n 0x00000140 6e746572 6e616c5f 756e7061 636b0066 nternal_unpack.f\n- 0x00000150 72656500 5f474c4f 42414c5f 4f464653 ree._GLOBAL_OFFS\n- 0x00000160 45545f54 41424c45 5f005f5f 73746163 ET_TABLE_.__stac\n- 0x00000170 6b5f6368 6b5f6775 61726400 5f5f6772 k_chk_guard.__gr\n- 0x00000180 69647863 5f737973 5f4d4f44 5f677269 idxc_sys_MOD_gri\n- 0x00000190 6478635f 74696d65 725f7374 61727400 dxc_timer_start.\n- 0x000001a0 5f5f6772 69647863 5f737973 5f4d4f44 __gridxc_sys_MOD\n- 0x000001b0 5f646965 005f6766 6f727472 616e5f61 _die._gfortran_a\n- 0x000001c0 73736f63 69617465 64005f5f 67726964 ssociated.__grid\n- 0x000001d0 78635f61 6c6c6f63 5f4d4f44 5f726561 xc_alloc_MOD_rea\n- 0x000001e0 6c6c6f63 5f643200 5f5f6772 69647863 lloc_d2.__gridxc\n- 0x000001f0 5f666674 5f677066 615f4d4f 445f7365 _fft_gpfa_MOD_se\n- 0x00000200 74677066 615f6368 65636b00 5f5f6772 tgpfa_check.__gr\n- 0x00000210 69647863 5f6d6573 6833645f 4d4f445f idxc_mesh3d_MOD_\n- 0x00000220 6666746d 65736864 69737472 005f5f67 fftmeshdistr.__g\n- 0x00000230 72696478 635f6d65 73683364 5f4d4f44 ridxc_mesh3d_MOD\n- 0x00000240 5f636f70 796d6573 68646174 61005f5f _copymeshdata.__\n- 0x00000250 67726964 78635f61 6c6c6f63 5f4d4f44 gridxc_alloc_MOD\n- 0x00000260 5f646561 6c6c6f63 5f643400 5f5f7374 _dealloc_d4.__st\n- 0x00000270 61636b5f 63686b5f 6661696c 005f5f67 ack_chk_fail.__g\n+ 0x00000150 72656500 5f67666f 72747261 6e5f6173 ree._gfortran_as\n+ 0x00000160 736f6369 61746564 005f5f67 72696478 sociated.__gridx\n+ 0x00000170 635f616c 6c6f635f 4d4f445f 7265616c c_alloc_MOD_real\n+ 0x00000180 6c6f635f 6432005f 5f677269 6478635f loc_d2.__gridxc_\n+ 0x00000190 6666745f 67706661 5f4d4f44 5f736574 fft_gpfa_MOD_set\n+ 0x000001a0 67706661 5f636865 636b005f 5f677269 gpfa_check.__gri\n+ 0x000001b0 6478635f 6d657368 33645f4d 4f445f66 dxc_mesh3d_MOD_f\n+ 0x000001c0 66746d65 73686469 73747200 5f5f6772 ftmeshdistr.__gr\n+ 0x000001d0 69647863 5f6d6573 6833645f 4d4f445f idxc_mesh3d_MOD_\n+ 0x000001e0 636f7079 6d657368 64617461 005f5f67 copymeshdata.__g\n+ 0x000001f0 72696478 635f616c 6c6f635f 4d4f445f ridxc_alloc_MOD_\n+ 0x00000200 6465616c 6c6f635f 6434005f 5f737461 dealloc_d4.__sta\n+ 0x00000210 636b5f63 686b5f66 61696c00 5f474c4f ck_chk_fail._GLO\n+ 0x00000220 42414c5f 4f464653 45545f54 41424c45 BAL_OFFSET_TABLE\n+ 0x00000230 5f005f5f 73746163 6b5f6368 6b5f6775 _.__stack_chk_gu\n+ 0x00000240 61726400 5f5f6772 69647863 5f737973 ard.__gridxc_sys\n+ 0x00000250 5f4d4f44 5f677269 6478635f 74696d65 _MOD_gridxc_time\n+ 0x00000260 725f7374 61727400 5f5f6772 69647863 r_start.__gridxc\n+ 0x00000270 5f737973 5f4d4f44 5f646965 005f5f67 _sys_MOD_die.__g\n 0x00000280 72696478 635f7379 735f4d4f 445f6772 ridxc_sys_MOD_gr\n 0x00000290 69647863 5f74696d 65725f73 746f7000 idxc_timer_stop.\n \n"}]}, {"source1": "fftr.F90.o", "source2": "fftr.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 7652 (bytes into file)\n+ Start of section headers: 8384 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x1de4:\n+There are 12 section headers, starting at offset 0x20c0:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000034 0015dc 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 001b7c 000200 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 001610 000010 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 001620 0000e4 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 001620 000082 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0016a4 00000c 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 0016b0 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0016b0 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 0016e4 000290 10 10 22 4\n- [10] .strtab STRTAB 00000000 001974 000208 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 001d7c 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 001730 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 001d30 000328 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 001768 000010 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 001778 0000e4 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 001778 000082 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 0017fc 00000c 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 001808 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 001808 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 001838 0002e0 10 10 26 4\n+ [10] .strtab STRTAB 00000000 001b18 000215 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 002058 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,44 +1,49 @@\n \n-Symbol table '.symtab' contains 41 entries:\n+Symbol table '.symtab' contains 46 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 5: 00000030 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 6: 0000003c 0 NOTYPE LOCAL DEFAULT 5 .LC4\n 7: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 8: 00000ae0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 9: 00000b38 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 00000d70 0 NOTYPE LOCAL DEFAULT 1 $d\n- 11: 00000048 0 NOTYPE LOCAL DEFAULT 5 .LC6\n- 12: 00000078 0 NOTYPE LOCAL DEFAULT 5 .LC7\n- 13: 00000d78 0 NOTYPE LOCAL DEFAULT 1 $t\n- 14: 00001598 0 NOTYPE LOCAL DEFAULT 1 $d\n- 15: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 16: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 17: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 18: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 19: 00000000 72 OBJECT LOCAL DEFAULT 4 fc.2\n- 20: 00000048 72 OBJECT LOCAL DEFAULT 4 fmk.1\n- 21: 00000090 72 OBJECT LOCAL DEFAULT 4 fc.0\n- 22: 00000001 3448 FUNC GLOBAL DEFAULT 1 __gridxc_fftr_MOD_fftk2r\n- 23: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_mymeshbox\n- 24: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n- 25: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d4\n- 26: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_associatemeshtask\n- 27: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fft3d_MOD_fft3d\n- 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_copymeshdata\n- 29: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n- 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 33: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 34: 00000d79 2148 FUNC GLOBAL DEFAULT 1 __gridxc_fftr_MOD_fftr2k\n- 35: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 36: 000000d8 12 OBJECT GLOBAL HIDDEN 4 __gridxc_fftr_MOD_themesh\n- 37: 0000000c 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_r2k\n- 38: 00000008 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_mk2k\n- 39: 00000000 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_kdistr\n- 40: 00000004 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_k2r\n+ 8: 000004a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 000004e4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 10: 00000ba0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 11: 00000bc8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 00000e48 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 13: 00000048 0 NOTYPE LOCAL DEFAULT 5 .LC6\n+ 14: 00000078 0 NOTYPE LOCAL DEFAULT 5 .LC7\n+ 15: 00000e58 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 16: 00001428 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 17: 00001474 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 18: 00001728 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 20: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 21: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 22: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 23: 00000000 72 OBJECT LOCAL DEFAULT 4 fc.2\n+ 24: 00000048 72 OBJECT LOCAL DEFAULT 4 fmk.1\n+ 25: 00000090 72 OBJECT LOCAL DEFAULT 4 fc.0\n+ 26: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idiv\n+ 27: 00000001 3672 FUNC GLOBAL DEFAULT 1 __gridxc_fftr_MOD_fftk2r\n+ 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_mymeshbox\n+ 29: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_fftmeshdistr\n+ 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d4\n+ 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_associatemeshtask\n+ 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 33: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 34: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 35: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fft3d_MOD_fft3d\n+ 36: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh3d_MOD_copymeshdata\n+ 37: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d4\n+ 38: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 39: 00000e59 2264 FUNC GLOBAL DEFAULT 1 __gridxc_fftr_MOD_fftr2k\n+ 40: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 41: 000000d8 12 OBJECT GLOBAL HIDDEN 4 __gridxc_fftr_MOD_themesh\n+ 42: 0000000c 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_r2k\n+ 43: 00000008 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_mk2k\n+ 44: 00000000 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_kdistr\n+ 45: 00000004 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fftr_MOD_k2r\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,67 +1,104 @@\n \n-Relocation section '.rel.text' at offset 0x1b7c contains 64 entries:\n+Relocation section '.rel.text' at offset 0x1d30 contains 101 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000080 0000170a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-000000b6 0000180a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n-000000c4 0000170a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-0000018a 0000190a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000001ec 0000190a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00000200 00001a0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00000210 00001a0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-000004e8 00001b0a R_ARM_THM_CALL 00000000 __gridxc_fft3d_MOD_fft3d\n-000005b8 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-000005f0 00001d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-0000069c 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-00000ae0 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000ae4 00001f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000ae8 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000aec 00000103 R_ARM_REL32 00000000 .data\n-00000af0 00000403 R_ARM_REL32 00000000 .LC0\n-00000af4 0000201a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000af8 00000f03 R_ARM_REL32 00000000 .rodata\n-00000afc 00000203 R_ARM_REL32 00000000 .bss\n-00000b00 00000503 R_ARM_REL32 00000030 .LC1\n-00000b04 00000103 R_ARM_REL32 00000000 .data\n-00000b08 00000603 R_ARM_REL32 0000003c .LC4\n-00000b0c 00000103 R_ARM_REL32 00000000 .data\n-00000b10 00000203 R_ARM_REL32 00000000 .bss\n-00000b14 00000203 R_ARM_REL32 00000000 .bss\n-00000b18 00000103 R_ARM_REL32 00000000 .data\n-00000b1c 00000f03 R_ARM_REL32 00000000 .rodata\n-00000b20 00000103 R_ARM_REL32 00000000 .data\n-00000b24 00000203 R_ARM_REL32 00000000 .bss\n-00000b28 00000103 R_ARM_REL32 00000000 .data\n-00000b2c 00000503 R_ARM_REL32 00000030 .LC1\n-00000b30 00000203 R_ARM_REL32 00000000 .bss\n-00000b34 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d64 00001d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00000d6a 0000210a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000d70 00000203 R_ARM_REL32 00000000 .bss\n-00000d74 00000603 R_ARM_REL32 0000003c .LC4\n-00000df0 0000170a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-00000e28 0000180a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n-00000e36 0000170a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n-00000e70 00001a0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n-00000f0e 0000190a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-0000106c 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n-0000112c 00001b0a R_ARM_THM_CALL 00000000 __gridxc_fft3d_MOD_fft3d\n-00001162 0000230a R_ARM_THM_CALL 00000000 memset\n-0000131a 00001d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-00001592 0000210a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001598 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000159c 00001f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000015a0 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000015a4 00000103 R_ARM_REL32 00000000 .data\n-000015a8 00000b03 R_ARM_REL32 00000048 .LC6\n-000015ac 0000201a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000015b0 00000f03 R_ARM_REL32 00000000 .rodata\n-000015b4 00000203 R_ARM_REL32 00000000 .bss\n-000015b8 00000c03 R_ARM_REL32 00000078 .LC7\n-000015bc 00000103 R_ARM_REL32 00000000 .data\n-000015c0 00000f03 R_ARM_REL32 00000000 .rodata\n-000015c4 00000203 R_ARM_REL32 00000000 .bss\n-000015c8 00000103 R_ARM_REL32 00000000 .data\n-000015cc 00000203 R_ARM_REL32 00000000 .bss\n-000015d0 00000203 R_ARM_REL32 00000000 .bss\n-000015d4 00000c03 R_ARM_REL32 00000078 .LC7\n-000015d8 00001e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000086 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+000000b6 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n+000000c0 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00000178 00001e0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+000001d6 00001e0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+000001e8 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+000001f8 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00000382 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000003c6 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000428 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000047a 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000004a8 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004ac 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000004b0 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004b4 00000103 R_ARM_REL32 00000000 .data\n+000004b8 00000403 R_ARM_REL32 00000000 .LC0\n+000004bc 0000221a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000004c0 00001303 R_ARM_REL32 00000000 .rodata\n+000004c4 00000203 R_ARM_REL32 00000000 .bss\n+000004c8 00000503 R_ARM_REL32 00000030 .LC1\n+000004cc 00000103 R_ARM_REL32 00000000 .data\n+000004d0 00000603 R_ARM_REL32 0000003c .LC4\n+000004d4 00000103 R_ARM_REL32 00000000 .data\n+000004d8 00000203 R_ARM_REL32 00000000 .bss\n+000004dc 00000203 R_ARM_REL32 00000000 .bss\n+000004e0 00000103 R_ARM_REL32 00000000 .data\n+00000550 0000230a R_ARM_THM_CALL 00000000 __gridxc_fft3d_MOD_fft3d\n+00000614 0000240a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+0000064c 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00000682 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000069c 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000006fe 0000240a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+00000788 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000007dc 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000844 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000898 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000916 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000930 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000009cc 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000a24 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000a8c 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000aea 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000b72 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000b90 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000ba8 00000203 R_ARM_REL32 00000000 .bss\n+00000bac 00001303 R_ARM_REL32 00000000 .rodata\n+00000bb0 00000103 R_ARM_REL32 00000000 .data\n+00000bb4 00000103 R_ARM_REL32 00000000 .data\n+00000bb8 00000503 R_ARM_REL32 00000030 .LC1\n+00000bbc 00000203 R_ARM_REL32 00000000 .bss\n+00000bc0 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000bc4 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000c74 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000cbe 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000d24 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000d80 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000e00 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000e1a 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000e36 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00000e3e 0000260a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000e50 00000203 R_ARM_REL32 00000000 .bss\n+00000e54 00000603 R_ARM_REL32 0000003c .LC4\n+00000ecc 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00000efa 00001d0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_fftmeshdistr\n+00000f08 00001c0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_mymeshbox\n+00000f44 00001f0a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_associatemeshtask\n+00000fde 00001e0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+00001134 0000240a R_ARM_THM_CALL 00000000 __gridxc_mesh3d_MOD_copymeshdata\n+000011d4 0000230a R_ARM_THM_CALL 00000000 __gridxc_fft3d_MOD_fft3d\n+0000120c 0000280a R_ARM_THM_CALL 00000000 memset\n+00001300 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00001342 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000137a 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00001406 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+00001430 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001434 0000211a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001438 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000143c 00000103 R_ARM_REL32 00000000 .data\n+00001440 00000d03 R_ARM_REL32 00000048 .LC6\n+00001444 0000221a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001448 00001303 R_ARM_REL32 00000000 .rodata\n+0000144c 00000203 R_ARM_REL32 00000000 .bss\n+00001450 00000e03 R_ARM_REL32 00000078 .LC7\n+00001454 00000103 R_ARM_REL32 00000000 .data\n+00001458 00001303 R_ARM_REL32 00000000 .rodata\n+0000145c 00000203 R_ARM_REL32 00000000 .bss\n+00001460 00000103 R_ARM_REL32 00000000 .data\n+00001464 00000203 R_ARM_REL32 00000000 .bss\n+00001468 00000203 R_ARM_REL32 00000000 .bss\n+0000146c 00000e03 R_ARM_REL32 00000078 .LC7\n+00001470 00002019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000014a6 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000014c2 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000014da 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00001576 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000015b2 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000015e6 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000168a 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000016a4 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000016c0 00001a0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00001720 0000260a R_ARM_THM_CALL 00000000 __stack_chk_fail\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,23 +1,24 @@\n fftk2r ERROR: size of input array f too small\n fftk2r fc\n fftk2r fmk\n fftr2k ERROR: size of input array f too small\n fftr2k fc\n+__aeabi_idiv\n __gridxc_fftr_MOD_fftk2r\n __gridxc_mesh3d_MOD_mymeshbox\n __gridxc_mesh3d_MOD_fftmeshdistr\n __gridxc_alloc_MOD_realloc_d4\n __gridxc_mesh3d_MOD_associatemeshtask\n-__gridxc_fft3d_MOD_fft3d\n-__gridxc_mesh3d_MOD_copymeshdata\n-__gridxc_alloc_MOD_dealloc_d4\n _GLOBAL_OFFSET_TABLE_\n __stack_chk_guard\n __gridxc_sys_MOD_die\n+__gridxc_fft3d_MOD_fft3d\n+__gridxc_mesh3d_MOD_copymeshdata\n+__gridxc_alloc_MOD_dealloc_d4\n __stack_chk_fail\n __gridxc_fftr_MOD_fftr2k\n __gridxc_fftr_MOD_themesh\n __gridxc_fftr_MOD_r2k\n __gridxc_fftr_MOD_mk2k\n __gridxc_fftr_MOD_kdistr\n __gridxc_fftr_MOD_k2r\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -3,2196 +3,2422 @@\n \n Disassembly of section .text:\n \n 00000000 <__gridxc_fftr_MOD_fftk2r>:\n __gridxc_fftr_MOD_fftk2r():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n+\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3520]\t@ 0xdc0\n-\tldr.w\tr4, [pc, #2760]\t@ ae0 <__gridxc_fftr_MOD_fftk2r+0xae0>\n-\tsub.w\tsp, sp, #532\t@ 0x214\n-\tmov\tr3, r2\n-\tldr.w\tr2, [pc, #2756]\t@ ae4 <__gridxc_fftr_MOD_fftk2r+0xae4>\n-\tadd\tr4, pc\n-\tadd\tr5, sp, #304\t@ 0x130\n-\tstr\tr0, [sp, #184]\t@ 0xb8\n+\tstr.w\tr0, [ip, #3496]\t@ 0xda8\n+\tsub.w\tsp, sp, #548\t@ 0x224\n+\tmov\tr4, r2\n+\tldr.w\tr2, [pc, #1164]\t@ 4a8 <__gridxc_fftr_MOD_fftk2r+0x4a8>\n+\tadd\tr5, sp, #372\t@ 0x174\n+\tldr.w\tr3, [pc, #1160]\t@ 4ac <__gridxc_fftr_MOD_fftk2r+0x4ac>\n \tmov\tr6, r0\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n-\tldr.w\tr8, [pc, #2744]\t@ ae8 <__gridxc_fftr_MOD_fftk2r+0xae8>\n-\tldr\tr2, [r4, r2]\n-\tldr\tr4, [r3, #24]\n+\tadd\tr2, pc\n+\tstr\tr0, [sp, #208]\t@ 0xd0\n+\tstr\tr1, [sp, #68]\t@ 0x44\n+\tadd.w\tr9, sp, #300\t@ 0x12c\n+\tldr.w\tr8, [pc, #1148]\t@ 4b0 <__gridxc_fftr_MOD_fftk2r+0x4b0>\n+\tldr\tr3, [r2, r3]\n \tadd\tr8, pc\n-\tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #524]\t@ 0x20c\n-\tmov.w\tr2, #0\n-\tstr\tr5, [sp, #252]\t@ 0xfc\n-\tcmp\tr4, #0\n+\tldr\tr3, [r3, #0]\n+\tstr\tr3, [sp, #540]\t@ 0x21c\n+\tmov.w\tr3, #0\n+\tldr\tr3, [r4, #24]\n+\tstr\tr5, [sp, #280]\t@ 0x118\n+\tcmp\tr3, #0\n \tit\teq\n-\tmoveq\tr4, #1\n-\tstr\tr4, [sp, #104]\t@ 0x68\n-\tldrd\tr2, r4, [r3, #64]\t@ 0x40\n-\tsub.w\tfp, r4, r2\n-\tldrd\tr2, r4, [r3, #28]\n-\tsubs\tr2, r4, r2\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tldrd\tr2, r4, [r3, #40]\t@ 0x28\n-\tsubs\tr2, r4, r2\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldrd\tr2, r4, [r3, #52]\t@ 0x34\n-\tsub.w\tsl, r4, r2\n-\tldr\tr4, [r3, #0]\n-\tstr\tr4, [sp, #52]\t@ 0x34\n+\tmoveq\tr3, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tldrd\tr3, r2, [r4, #64]\t@ 0x40\n+\tsub.w\tsl, r2, r3\n+\tldrd\tr3, r2, [r4, #28]\n+\tsub.w\tfp, r2, r3\n+\tldrd\tr3, r2, [r4, #40]\t@ 0x28\n+\tsubs\tr3, r2, r3\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldrd\tr3, r2, [r4, #52]\t@ 0x34\n+\tsubs\tr3, r2, r3\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [r4, #0]\n \tmov\tr2, r5\n-\tldr\tr4, [r3, #36]\t@ 0x24\n-\tstr\tr4, [sp, #56]\t@ 0x38\n-\tldr\tr4, [r3, #48]\t@ 0x30\n-\tldr\tr3, [r3, #60]\t@ 0x3c\n-\tstr\tr4, [sp, #128]\t@ 0x80\n-\tstr\tr3, [sp, #204]\t@ 0xcc\n-\tadd.w\tr3, fp, #1\n-\tstr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tmov\tr5, r6\n+\tldr\tr3, [r4, #36]\t@ 0x24\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [r4, #48]\t@ 0x30\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr3, [r4, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #232]\t@ 0xe8\n+\tadd.w\tr3, sl, #1\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tvldr\td17, [sp, #304]\t@ 0x130\n-\tvmov.i32\td18, #1\t@ 0x00000001\n-\tvldr\td16, [sp, #312]\t@ 0x138\n+\tldrd\tr2, r3, [sp, #372]\t@ 0x174\n \tmov\tr0, r6\n-\tldrd\tr2, r3, [sp, #320]\t@ 0x140\n-\tvtrn.32\td17, d16\n-\tldr.w\tr4, [pc, #2640]\t@ aec <__gridxc_fftr_MOD_fftk2r+0xaec>\n+\tldr.w\tr1, [pc, #1056]\t@ 4b4 <__gridxc_fftr_MOD_fftk2r+0x4b4>\n+\tadd\tr6, sp, #324\t@ 0x144\n+\tsubs\tr3, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #312]\t@ 0x138\n+\tldrd\tr2, r3, [sp, #380]\t@ 0x17c\n+\tadd\tr1, pc\n+\tmov\tr4, r1\n+\tsubs\tr3, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #316]\t@ 0x13c\n+\tldrd\tr2, r3, [sp, #388]\t@ 0x184\n \tsubs\tr3, r3, r2\n \tmovs\tr2, #0\n-\tadd\tr4, pc\n \tadds\tr3, #1\n-\tmov\tr1, r4\n-\tstr\tr3, [sp, #288]\t@ 0x120\n-\tvsub.i32\td16, d16, d17\n-\tvadd.i32\td16, d16, d18\n-\tvstr\td16, [sp, #280]\t@ 0x118\n+\tstr\tr3, [sp, #320]\t@ 0x140\n \tbl\t0 <__gridxc_mesh3d_MOD_fftmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_fftmeshdistr\n-\tadd\tr3, sp, #328\t@ 0x148\n \tmov\tr1, r4\n-\tmov\tr0, r6\n-\tmov\tr2, r3\n-\tstr\tr3, [sp, #80]\t@ 0x50\n+\tmov\tr0, r5\n+\tmov\tr2, r6\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldr\tr3, [sp, #332]\t@ 0x14c\n-\tadd\tr0, sp, #452\t@ 0x1c4\n-\tldr\tr2, [sp, #328]\t@ 0x148\n-\tadd\tr6, sp, #292\t@ 0x124\n-\tldr\tr5, [sp, #336]\t@ 0x150\n-\tmov\tr9, r6\n-\tldr\tr1, [sp, #340]\t@ 0x154\n-\tldr\tr7, [sp, #348]\t@ 0x15c\n-\tldr\tr4, [sp, #344]\t@ 0x158\n-\tstr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #328]\t@ 0x148\n+\tldr\tr2, [sp, #324]\t@ 0x144\n+\tadd\tr0, sp, #468\t@ 0x1d4\n+\tldr\tr5, [sp, #332]\t@ 0x14c\n+\tldr\tr1, [sp, #336]\t@ 0x150\n+\tldr\tr7, [sp, #344]\t@ 0x158\n+\tldr\tr4, [sp, #340]\t@ 0x154\n+\tstr\tr3, [sp, #196]\t@ 0xc4\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n-\tstr\tr0, [sp, #208]\t@ 0xd0\n-\tstr\tr3, [sp, #292]\t@ 0x124\n+\tstr\tr0, [sp, #236]\t@ 0xec\n+\tstr\tr3, [sp, #300]\t@ 0x12c\n \tsubs\tr3, r1, r5\n-\tldr.w\tr0, [pc, #2568]\t@ af0 <__gridxc_fftr_MOD_fftk2r+0xaf0>\n+\tldr\tr0, [pc, #984]\t@ (4b8 <__gridxc_fftr_MOD_fftk2r+0x4b8>)\n \tadds\tr3, #1\n-\tstr\tr4, [sp, #152]\t@ 0x98\n-\tstr\tr3, [sp, #296]\t@ 0x128\n+\tstr\tr4, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #304]\t@ 0x130\n \tsubs\tr3, r7, r4\n-\tldr\tr4, [sp, #208]\t@ 0xd0\n+\tldr\tr4, [sp, #236]\t@ 0xec\n \tadd\tr0, pc\n-\tstr\tr5, [sp, #132]\t@ 0x84\n-\tadd\tr5, sp, #280\t@ 0x118\n-\tstr\tr7, [sp, #180]\t@ 0xb4\n+\tstr\tr5, [sp, #152]\t@ 0x98\n+\tadd\tr5, sp, #312\t@ 0x138\n+\tstr\tr7, [sp, #204]\t@ 0xcc\n \tmovs\tr7, #0\n \tadds\tr3, #1\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #176]\t@ 0xb0\n-\tstr\tr3, [sp, #300]\t@ 0x12c\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #484]\t@ 0x1e4\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr2, [sp, #172]\t@ 0xac\n+\tstr\tr1, [sp, #200]\t@ 0xc8\n+\tstr\tr3, [sp, #308]\t@ 0x134\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #512]\t@ 0x200\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tldr.w\tr1, [r5], #4\n-\tstr\tr3, [sp, #496]\t@ 0x1f0\n-\tldr.w\tr3, [r6], #4\n-\tstr\tr7, [sp, #480]\t@ 0x1e0\n-\tstr\tr7, [sp, #492]\t@ 0x1ec\n+\tstr\tr3, [sp, #524]\t@ 0x20c\n+\tldr.w\tr3, [r9], #4\n+\tstrd\tr7, fp, [sp, #496]\t@ 0x1f0\n+\tstr\tr7, [sp, #508]\t@ 0x1fc\n \tcmp\tr1, r3\n-\tstrd\tr7, sl, [sp, #504]\t@ 0x1f8\n+\tstr\tr7, [sp, #520]\t@ 0x208\n \tit\tlt\n \tmovlt\tr1, r3\n \tldrd\tr2, r3, [r4, #28]\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r1\n-\tbge.w\t8a2 <__gridxc_fftr_MOD_fftk2r+0x8a2>\n-\tldr.w\tr3, [pc, #2492]\t@ af4 <__gridxc_fftr_MOD_fftk2r+0xaf4>\n+\tbge.w\t93c <__gridxc_fftr_MOD_fftk2r+0x93c>\n+\tldr\tr3, [pc, #908]\t@ (4bc <__gridxc_fftr_MOD_fftk2r+0x4bc>)\n \tmovs\tr1, #45\t@ 0x2d\n \tadds\tr4, #12\n \tldr.w\tr3, [r8, r3]\n-\tstr\tr0, [sp, #84]\t@ 0x54\n+\tstr\tr0, [sp, #72]\t@ 0x48\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tcmp\tr5, r9\n-\tbne.n\t106 <__gridxc_fftr_MOD_fftk2r+0x106>\n-\tldr.w\tr5, [pc, #2472]\t@ af8 <__gridxc_fftr_MOD_fftk2r+0xaf8>\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tcmp\tr5, r6\n+\tbne.n\tfc <__gridxc_fftr_MOD_fftk2r+0xfc>\n+\tmov\tr1, r6\n+\tldr\tr5, [pc, #888]\t@ (4c0 <__gridxc_fftr_MOD_fftk2r+0x4c0>)\n+\tldr\tr6, [pc, #892]\t@ (4c4 <__gridxc_fftr_MOD_fftk2r+0x4c4>)\n \tmovs\tr4, #0\n-\tldr.w\tr6, [pc, #2468]\t@ afc <__gridxc_fftr_MOD_fftk2r+0xafc>\n-\tadd\tr2, sp, #332\t@ 0x14c\n-\tldr.w\tr3, [pc, #2468]\t@ b00 <__gridxc_fftr_MOD_fftk2r+0xb00>\n+\tldr\tr3, [pc, #892]\t@ (4c8 <__gridxc_fftr_MOD_fftk2r+0x4c8>)\n \tadd\tr5, pc\n \tadd\tr6, pc\n \tstr\tr5, [sp, #16]\n \tadd\tr3, pc\n-\tldr\tr1, [sp, #80]\t@ 0x50\n-\tstr\tr3, [sp, #20]\n \tadds\tr5, #4\n+\tstr\tr3, [sp, #20]\n+\tadd\tr2, sp, #328\t@ 0x148\n \tmovs\tr3, #9\n \tmov\tr0, r6\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #348\t@ 0x15c\n+\tadd\tr3, sp, #344\t@ 0x158\n \tstr\tr5, [sp, #12]\n \tstr\tr3, [sp, #8]\n-\tadd\tr3, sp, #344\t@ 0x158\n+\tadd\tr3, sp, #340\t@ 0x154\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr3, [sp, #4]\n-\tadd\tr3, sp, #340\t@ 0x154\n+\tadd\tr3, sp, #336\t@ 0x150\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr3, [sp, #0]\n-\tadd\tr3, sp, #336\t@ 0x150\n+\tadd\tr3, sp, #332\t@ 0x14c\n \tstr\tr4, [sp, #24]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr3, [pc, #2420]\t@ b04 <__gridxc_fftr_MOD_fftk2r+0xb04>\n+\tldr\tr3, [pc, #844]\t@ (4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t1f0 <__gridxc_fftr_MOD_fftk2r+0x1f0>\n+\tbeq.n\t1da <__gridxc_fftr_MOD_fftk2r+0x1da>\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tadd.w\tr0, r6, #72\t@ 0x48\n \tstrd\tr4, r4, [sp, #28]\n-\tadd\tr2, sp, #356\t@ 0x164\n+\tadd\tr2, sp, #352\t@ 0x160\n \tstr\tr4, [sp, #24]\n-\tadd\tr1, sp, #352\t@ 0x160\n-\tldr\tr4, [sp, #172]\t@ 0xac\n-\tldr.w\tr3, [pc, #2392]\t@ b08 <__gridxc_fftr_MOD_fftk2r+0xb08>\n+\tadd\tr1, sp, #348\t@ 0x15c\n+\tldr\tr4, [sp, #196]\t@ 0xc4\n+\tldr\tr3, [pc, #820]\t@ (4d0 <__gridxc_fftr_MOD_fftk2r+0x4d0>)\n \tnegs\tr4, r4\n-\tstr\tr4, [sp, #352]\t@ 0x160\n-\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tstr\tr4, [sp, #348]\t@ 0x15c\n+\tldr\tr4, [sp, #200]\t@ 0xc8\n \tadd\tr3, pc\n \tstrd\tr5, r5, [sp, #12]\n \tnegs\tr4, r4\n-\tstr\tr4, [sp, #360]\t@ 0x168\n-\tldr\tr4, [sp, #180]\t@ 0xb4\n+\tstr\tr4, [sp, #356]\t@ 0x164\n+\tldr\tr4, [sp, #204]\t@ 0xcc\n \tstr\tr3, [sp, #20]\n \tmovs\tr3, #10\n \tnegs\tr4, r4\n-\tstr\tr4, [sp, #368]\t@ 0x170\n-\tldr\tr4, [sp, #68]\t@ 0x44\n+\tstr\tr4, [sp, #364]\t@ 0x16c\n+\tldr\tr4, [sp, #172]\t@ 0xac\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #372\t@ 0x174\n-\tnegs\tr4, r4\n-\tstr\tr4, [sp, #356]\t@ 0x164\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tstr\tr3, [sp, #8]\n \tadd\tr3, sp, #368\t@ 0x170\n \tnegs\tr4, r4\n-\tstr\tr4, [sp, #364]\t@ 0x16c\n+\tstr\tr4, [sp, #352]\t@ 0x160\n \tldr\tr4, [sp, #152]\t@ 0x98\n-\tstr\tr3, [sp, #4]\n+\tstr\tr3, [sp, #8]\n \tadd\tr3, sp, #364\t@ 0x16c\n-\tstr\tr3, [sp, #0]\n+\tnegs\tr4, r4\n+\tstr\tr4, [sp, #360]\t@ 0x168\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #4]\n \tadd\tr3, sp, #360\t@ 0x168\n+\tstr\tr3, [sp, #0]\n+\tadd\tr3, sp, #356\t@ 0x164\n \tnegs\tr4, r4\n-\tstr\tr4, [sp, #372]\t@ 0x174\n+\tstr\tr4, [sp, #368]\t@ 0x170\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr.w\tr3, [pc, #2328]\t@ b0c <__gridxc_fftr_MOD_fftk2r+0xb0c>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [pc, #760]\t@ (4d4 <__gridxc_fftr_MOD_fftk2r+0x4d4>)\n+\tldr\tr1, [sp, #68]\t@ 0x44\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #236]\t@ 0xec\n+\tstr\tr3, [sp, #264]\t@ 0x108\n \tmov\tr4, r3\n \tmov\tr2, r3\n \tadds\tr0, r3, #4\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n \tadd.w\tr3, r4, #8\n \tmov\tr0, r3\n \tmov\tr1, r4\n \tmovs\tr2, #0\n-\tstr\tr3, [sp, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #276]\t@ 0x114\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tcmp.w\tfp, #0\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp.w\tsl, #0\n \tbic.w\tr3, r3, r3, asr #31\n+\tstr\tr3, [sp, #272]\t@ 0x110\n+\tblt.w\t62c <__gridxc_fftr_MOD_fftk2r+0x62c>\n+\tadd.w\tr3, fp, #1\n \tstr\tr3, [sp, #244]\t@ 0xf4\n-\tblt.w\t5d0 <__gridxc_fftr_MOD_fftk2r+0x5d0>\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tvmov.i64\td8, #0x0000000000000000\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #216]\t@ 0xd8\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tldr.w\tfp, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #248]\t@ 0xf8\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvldr\td8, [pc, #640]\t@ 4a0 <__gridxc_fftr_MOD_fftk2r+0x4a0>\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #220]\t@ 0xdc\n-\tadd.w\tr3, sl, #1\n-\tstr\tr3, [sp, #224]\t@ 0xe0\n-\tldr\tr3, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #252]\t@ 0xfc\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n \tnegs\tr3, r3\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #148]\t@ 0x94\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #204]\t@ 0xcc\n+\tldr\tr2, [sp, #232]\t@ 0xe8\n \tsubs\tr3, r3, r2\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n-\tldr.w\tr3, [pc, #2236]\t@ b10 <__gridxc_fftr_MOD_fftk2r+0xb10>\n+\tstr\tr3, [sp, #256]\t@ 0x100\n+\tldr\tr3, [pc, #672]\t@ (4d8 <__gridxc_fftr_MOD_fftk2r+0x4d8>)\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #268]\t@ 0x10c\n+\tstr\tr3, [sp, #292]\t@ 0x124\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #212]\t@ 0xd4\n-\tadd\tr3, sp, #464\t@ 0x1d0\n \tstr\tr3, [sp, #240]\t@ 0xf0\n-\tadd\tr3, sp, #388\t@ 0x184\n-\tstr\tr3, [sp, #260]\t@ 0x104\n+\tadd\tr3, sp, #480\t@ 0x1e0\n+\tstr\tr3, [sp, #268]\t@ 0x10c\n+\tadd\tr3, sp, #408\t@ 0x198\n+\tstr\tr3, [sp, #288]\t@ 0x120\n \tadd\tr3, sp, #396\t@ 0x18c\n-\tstr\tr3, [sp, #264]\t@ 0x108\n-\tadd\tr3, sp, #376\t@ 0x178\n-\tstr\tr3, [sp, #256]\t@ 0x100\n-\tldr\tr3, [sp, #236]\t@ 0xec\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tldr\tr1, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #284]\t@ 0x11c\n+\tldr\tr3, [sp, #264]\t@ 0x108\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldr\tr1, [sp, #160]\t@ 0xa0\n \tldr\tr3, [r3, #0]\n \tadd.w\tr2, r2, r1, lsl #3\n-\tstr\tr2, [sp, #232]\t@ 0xe8\n+\tstr\tr2, [sp, #260]\t@ 0x104\n \tcmp\tr3, #0\n-\tbne.w\t644 <__gridxc_fftr_MOD_fftk2r+0x644>\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tldr\tr2, [sp, #152]\t@ 0x98\n+\tbne.w\t6a8 <__gridxc_fftr_MOD_fftk2r+0x6a8>\n+\tldr\tr3, [sp, #204]\t@ 0xcc\n+\tldr\tr2, [sp, #176]\t@ 0xb0\n \tcmp\tr3, r2\n-\tblt.w\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n-\tldr.w\tr2, [pc, #2180]\t@ b14 <__gridxc_fftr_MOD_fftk2r+0xb14>\n-\tadd\tr2, pc\n-\tldr\tr1, [r2, #60]\t@ 0x3c\n-\tldr\tr3, [r2, #4]\n-\tstr\tr1, [sp, #140]\t@ 0x8c\n-\tadds\tr5, r1, r3\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tadds\tr4, r1, r5\n-\tldr\tr1, [sp, #132]\t@ 0x84\n-\tcmp\tr3, r1\n-\tblt.w\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tcmp\tr3, fp\n-\tblt.w\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n-\tldr.w\tr3, [pc, #2148]\t@ b18 <__gridxc_fftr_MOD_fftk2r+0xb18>\n-\tldr\tr6, [r2, #0]\n+\tblt.w\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tldr\tr3, [pc, #620]\t@ (4dc <__gridxc_fftr_MOD_fftk2r+0x4dc>)\n \tadd\tr3, pc\n-\tstr\tr6, [sp, #92]\t@ 0x5c\n-\tldr\tr6, [r2, #36]\t@ 0x24\n-\tldrd\tr9, sl, [r2, #72]\t@ 0x48\n-\tstr\tr6, [sp, #76]\t@ 0x4c\n-\tldr.w\tlr, [r3]\n-\tldr.w\tr8, [r2, #132]\t@ 0x84\n-\tldr.w\tip, [r2, #120]\t@ 0x78\n-\tldr\tr1, [r2, #108]\t@ 0x6c\n-\tldrd\tr3, r0, [r2, #92]\t@ 0x5c\n-\tldr\tr7, [r2, #48]\t@ 0x30\n-\tldrd\tr2, r6, [r2, #20]\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tcmp.w\tlr, #0\n-\tbeq.w\t6a2 <__gridxc_fftr_MOD_fftk2r+0x6a2>\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tadd.w\tlr, sl, r8\n-\tcmp\tr2, #1\n-\tbne.w\tb38 <__gridxc_fftr_MOD_fftk2r+0xb38>\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tmul.w\tr8, r0, r3\n-\tldr\tr4, [sp, #76]\t@ 0x4c\n-\tstr\tr7, [sp, #196]\t@ 0xc4\n-\tstr.w\tfp, [sp, #272]\t@ 0x110\n-\tmla\tr2, r7, r2, r5\n-\tldr\tr5, [sp, #132]\t@ 0x84\n-\tmla\tr4, r4, r5, r2\n-\tnegs\tr2, r5\n-\tmul.w\tr5, r3, r1\n-\tstr\tr5, [sp, #120]\t@ 0x78\n-\tmul.w\tr2, r1, r2\n+\tldr\tr1, [r3, #60]\t@ 0x3c\n+\tldr\tr2, [r3, #4]\n+\tstr\tr1, [sp, #184]\t@ 0xb8\n+\tadd.w\tr8, r1, r2\n+\tadd.w\tr2, r1, r8\n \tldr\tr1, [sp, #152]\t@ 0x98\n-\tmls\tr2, fp, r0, r2\n-\tldr\tr0, [sp, #136]\t@ 0x88\n-\tadd\tr2, lr\n-\tmls\tr2, ip, r1, r2\n-\tmla\tr5, r3, r2, r9\n-\tmul.w\tr3, r3, ip\n-\tstr\tr3, [sp, #192]\t@ 0xc0\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tldrd\tsl, r2, [r3]\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tcmp\tr2, r1\n+\tblt.w\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tldr\tr2, [sp, #196]\t@ 0xc4\n+\tldr\tr1, [sp, #172]\t@ 0xac\n+\tcmp\tr2, r1\n+\tblt.w\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tldr\tr2, [pc, #584]\t@ (4e0 <__gridxc_fftr_MOD_fftk2r+0x4e0>)\n+\tldrd\tlr, r9, [r3, #72]\t@ 0x48\n+\tadd\tr2, pc\n+\tldr.w\tsl, [r3, #132]\t@ 0x84\n+\tldr.w\tip, [r3, #120]\t@ 0x78\n+\tldr\tr6, [r2, #0]\n+\tldr\tr2, [r3, #0]\n+\tstr\tr2, [sp, #116]\t@ 0x74\n+\tldr\tr2, [r3, #36]\t@ 0x24\n+\tldr\tr4, [r3, #108]\t@ 0x6c\n+\tldrd\tr1, r7, [r3, #92]\t@ 0x5c\n+\tstr\tr2, [sp, #100]\t@ 0x64\n+\tldr\tr5, [r3, #48]\t@ 0x30\n+\tldrd\tr3, r2, [r3, #20]\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tcmp\tr6, #0\n+\tbeq.w\t704 <__gridxc_fftr_MOD_fftk2r+0x704>\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tadd.w\tr6, r9, sl\n+\tcmp\tr3, #1\n+\tbne.w\tbc8 <__gridxc_fftr_MOD_fftk2r+0xbc8>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmul.w\tr0, r1, r4\n+\tstr\tr0, [sp, #144]\t@ 0x90\n+\tmul.w\tr0, r1, r7\n+\tnegs\tr3, r3\n+\tstr\tr0, [sp, #68]\t@ 0x44\n+\tldr\tr0, [sp, #100]\t@ 0x64\n+\tmul.w\tr3, r4, r3\n+\tldr\tr4, [sp, #172]\t@ 0xac\n+\tmls\tr3, r4, r7, r3\n+\tldr\tr7, [sp, #208]\t@ 0xd0\n+\tadd\tr3, r6\n+\tldr\tr6, [sp, #176]\t@ 0xb0\n+\tmls\tr3, ip, r6, r3\n+\tmla\tr9, r1, r3, lr\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmul.w\tr1, ip, r1\n+\tstr.w\tr9, [sp, #164]\t@ 0xa4\n+\tstr\tr1, [sp, #216]\t@ 0xd8\n+\tldrd\tfp, r1, [r7]\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tmul.w\tr1, r0, r3\n+\tmul.w\tr0, r4, r2\n+\tstrd\tr1, r5, [sp, #224]\t@ 0xe0\n+\tstr\tr0, [sp, #140]\t@ 0x8c\n+\tadd.w\tr3, r1, r8\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tmul.w\tr2, r0, r2\n+\tldr\tr0, [sp, #140]\t@ 0x8c\n \tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr.w\tip, [r3, #8]\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tmul.w\tr9, r3, r6\n-\tmul.w\tr3, fp, r6\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #188]\t@ 0xbc\n-\tmul.w\tr3, r2, sl\n-\tstr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadd\tr3, r0\n+\tldr\tr0, [sp, #204]\t@ 0xcc\n+\tsubs\tr3, r3, r2\n+\tstr\tr3, [sp, #212]\t@ 0xd4\n+\tmov\tr3, r6\n+\tadds\tr0, #1\n+\tmla\tsl, r5, r6, r2\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tmov\tr8, r3\n+\tldr\tr3, [sp, #200]\t@ 0xc8\n+\tldr\tr6, [sp, #160]\t@ 0xa0\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tadd.w\tr3, fp, #1\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tadds\tr6, r3, #2\n-\tstr\tr6, [sp, #200]\t@ 0xc8\n-\tmov\tr6, r0\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tcmp.w\tip, #0\n-\tmul.w\tr3, r1, r3\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tmul.w\tr2, r2, fp\n+\tadds\tr3, r4, #1\n+\tstr\tr2, [sp, #168]\t@ 0xa8\n+\tldr\tr2, [r7, #8]\n \tstr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tadd\tr3, r4\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\trsb\tr3, r1, #0\n-\tblt.w\t630 <__gridxc_fftr_MOD_fftk2r+0x630>\n-\tcmp\tr3, #0\n-\tblt.w\t640 <__gridxc_fftr_MOD_fftk2r+0x640>\n-\tsdiv\tr2, r3, ip\n-\tmls\tr3, ip, r2, r3\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tldr.w\tfp, [sp, #132]\t@ 0x84\n-\tstr\tr5, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #60]\t@ 0x3c\n-\tmul.w\tlr, r2, r3\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n-\tmov\tr3, r4\n-\tstr\tr6, [sp, #148]\t@ 0x94\n-\tadds\tr0, r2, #1\n-\tstr\tr0, [sp, #116]\t@ 0x74\n-\tldr\tr0, [sp, #200]\t@ 0xc8\n-\tstrd\tr5, r4, [sp, #156]\t@ 0x9c\n-\tadds\tr2, r0, r2\n-\tstrd\tr1, ip, [sp, #164]\t@ 0xa4\n-\tstr\tr2, [sp, #112]\t@ 0x70\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tmul.w\tr6, fp, sl\n-\trsb\tr5, fp, #0\n-\tcmp\tr2, #0\n-\tblt.w\t61a <__gridxc_fftr_MOD_fftk2r+0x61a>\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tmov\tr5, r2\n+\tstr\tr0, [sp, #220]\t@ 0xdc\n+\tadds\tr3, #2\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\trsb\tr4, r8, #0\n \tcmp\tr5, #0\n-\tblt.w\t62c <__gridxc_fftr_MOD_fftk2r+0x62c>\n-\tsdiv\tr2, r5, r2\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tldr\tr4, [sp, #60]\t@ 0x3c\n-\tstrd\tfp, r3, [sp, #96]\t@ 0x60\n-\tmls\tr5, r1, r2, r5\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tadds\tr7, r3, r2\n-\tadds\tr1, r2, r1\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tmul.w\tr5, sl, r5\n-\tmul.w\tr7, r0, r7\n-\tmul.w\tr1, r0, r1\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tsubs\tr7, r7, r1\n-\tadd\tr1, r2\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadd\tr2, r6\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tadd.w\tr4, r0, r4, lsl #3\n-\tldr\tr0, [sp, #112]\t@ 0x70\n-\tadd.w\tip, r0, r6\n-\tldr\tr0, [sp, #116]\t@ 0x74\n-\tadd\tr6, r0\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tb.n\t448 <__gridxc_fftr_MOD_fftk2r+0x448>\n-\tcmp\tr3, #0\n-\tblt.n\t47a <__gridxc_fftr_MOD_fftk2r+0x47a>\n-\tsdiv\tfp, r3, sl\n-\tmls\tr3, sl, fp, r3\n-\tvldmia\tr4!, {d16}\n-\tadd.w\tfp, r1, r7\n-\tadds\tr3, #1\n-\tadd\tr3, r5\n-\tadd\tr3, lr\n-\tcmp\tr2, r3\n-\tbeq.n\t462 <__gridxc_fftr_MOD_fftk2r+0x462>\n-\tbge.n\t46c <__gridxc_fftr_MOD_fftk2r+0x46c>\n-\tvstr\td16, [fp]\n-\tvldr\td16, [r0]\n-\tadds\tr2, #1\n-\tvstr\td16, [r1]\n-\tsub.w\tr0, r0, r8\n-\tadd\tr1, r9\n-\tcmp\tip, r2\n-\tbeq.n\t480 <__gridxc_fftr_MOD_fftk2r+0x480>\n-\tsubs\tr3, r6, r2\n-\tcmp.w\tsl, #0\n-\tbge.n\t410 <__gridxc_fftr_MOD_fftk2r+0x410>\n-\tadd.w\tfp, r3, #4294967295\t@ 0xffffffff\n-\tcmp\tr3, #0\n-\tble.n\t414 <__gridxc_fftr_MOD_fftk2r+0x414>\n-\tsdiv\tfp, fp, sl\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n-\tb.n\t418 <__gridxc_fftr_MOD_fftk2r+0x418>\n-\tvstr\td16, [fp]\n-\tvmov.f64\td16, d8\n-\tb.n\t438 <__gridxc_fftr_MOD_fftk2r+0x438>\n-\tvldr\td17, [r0]\n-\tvneg.f64\td16, d16\n-\tvstr\td17, [fp]\n-\tb.n\t438 <__gridxc_fftr_MOD_fftk2r+0x438>\n-\tadd.w\tfp, r3, #1\n-\tb.n\t458 <__gridxc_fftr_MOD_fftk2r+0x458>\n-\tldrd\tr1, r2, [sp, #56]\t@ 0x38\n-\tldrd\tfp, r3, [sp, #96]\t@ 0x60\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tadd.w\tfp, fp, #1\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tsubs\tr2, r2, r1\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadd\tr1, r2\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tstr\tr1, [sp, #64]\t@ 0x40\n-\tcmp\tr2, fp\n-\tbne.n\t3b2 <__gridxc_fftr_MOD_fftk2r+0x3b2>\n+\tmul.w\tr3, r8, r3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #224]\t@ 0xe0\n+\tadd\tr3, sl\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #212]\t@ 0xd4\n+\tadd\tr3, sl\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tblt.w\t68e <__gridxc_fftr_MOD_fftk2r+0x68e>\n+\tcmp\tr4, #0\n+\tblt.w\t6a4 <__gridxc_fftr_MOD_fftk2r+0x6a4>\n+\tmov\tr1, r5\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr3, r0\n+\tmls\tr4, r5, r3, r4\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tstrd\tr6, r8, [sp, #180]\t@ 0xb4\n+\tstrd\tr5, sl, [sp, #188]\t@ 0xbc\n+\tmul.w\tr3, r3, r4\n+\tldr\tr4, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tstrd\tr6, r3, [sp, #80]\t@ 0x50\n \tldr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr6, [sp, #148]\t@ 0x94\n-\tldrd\tr5, r4, [sp, #156]\t@ 0x9c\n+\tadds\tr2, r3, #1\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n+\tadds\tr3, r2, r3\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tmul.w\tr8, r4, fp\n+\tnegs\tr7, r4\n+\tcmp\tr1, #0\n+\tblt.w\t676 <__gridxc_fftr_MOD_fftk2r+0x676>\n+\tcmp\tr7, #0\n+\tblt.w\t68a <__gridxc_fftr_MOD_fftk2r+0x68a>\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tldr.w\tsl, [sp, #84]\t@ 0x54\n+\tstr\tr4, [sp, #120]\t@ 0x78\n+\tmls\tr7, r3, r0, r7\n+\tmul.w\tr3, fp, r7\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadds\tr6, r3, r2\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tmul.w\tr6, r3, r6\n+\tmul.w\tr9, r3, r2\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tsub.w\tr9, r9, r6\n \tadd\tr6, r3\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n-\tldrd\tr1, ip, [sp, #164]\t@ 0xa4\n-\tsubs\tr5, r5, r3\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n-\tadds\tr1, #1\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tadd.w\tr5, r3, r8\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr7, r3, r2, lsl #3\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tmov\tr2, r7\n+\tmov\tr7, sl\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tmov\tsl, r2\n+\tadd\tr8, r3\n+\tmov\tr3, r8\n+\tmov\tr8, fp\n+\tmov\tfp, r3\n+\tb.n\t464 <__gridxc_fftr_MOD_fftk2r+0x464>\n+\tcmp\tr4, #0\n+\tblt.n\t49a <__gridxc_fftr_MOD_fftk2r+0x49a>\n+\tmov\tr1, r8\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr4, r8, r0, r4\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvldmia\tsl!, {d7}\n+\tadd.w\tr0, r9, r6\n+\tadds\tr4, #1\n \tadd\tr4, r3\n-\tldr\tr3, [sp, #188]\t@ 0xbc\n-\tcmp\tr3, r1\n-\tbne.w\t364 <__gridxc_fftr_MOD_fftk2r+0x364>\n-\tldr.w\tfp, [sp, #272]\t@ 0x110\n-\tldr.w\tr3, [pc, #1612]\t@ b1c <__gridxc_fftr_MOD_fftk2r+0xb1c>\n-\tldr.w\tr5, [pc, #1612]\t@ b20 <__gridxc_fftr_MOD_fftk2r+0xb20>\n-\tldr.w\tr4, [pc, #1612]\t@ b24 <__gridxc_fftr_MOD_fftk2r+0xb24>\n-\tadd\tr3, pc\n-\tldr\tr7, [sp, #184]\t@ 0xb8\n-\tadd\tr5, pc\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr4, r3\n+\tcmp\tr5, r4\n+\tbeq.n\t482 <__gridxc_fftr_MOD_fftk2r+0x482>\n+\tbge.n\t48c <__gridxc_fftr_MOD_fftk2r+0x48c>\n+\tvstr\td7, [r0]\n+\tvldr\td7, [r7]\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tadds\tr5, #1\n+\tvstr\td7, [r6]\n+\tsubs\tr7, r7, r3\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr3, r5\n+\tbeq.n\t4e4 <__gridxc_fftr_MOD_fftk2r+0x4e4>\n+\tsub.w\tr4, fp, r5\n+\tcmp.w\tr8, #0\n+\tbge.n\t420 <__gridxc_fftr_MOD_fftk2r+0x420>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.n\t424 <__gridxc_fftr_MOD_fftk2r+0x424>\n+\tmov\tr1, r8\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t42c <__gridxc_fftr_MOD_fftk2r+0x42c>\n+\tvstr\td7, [r0]\n+\tvmov.f64\td7, d8\n+\tb.n\t450 <__gridxc_fftr_MOD_fftk2r+0x450>\n+\tvldr\td6, [r7]\n+\tvneg.f64\td7, d7\n+\tvstr\td6, [r0]\n+\tb.n\t450 <__gridxc_fftr_MOD_fftk2r+0x450>\n+\tadds\tr0, r4, #1\n+\tb.n\t478 <__gridxc_fftr_MOD_fftk2r+0x478>\n+\tnop\n+\t...\n+\t.word\t0x0000047e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000476\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000410\n+ R_ARM_REL32\t.data\n+\t.word\t0x000003ca\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x00000370\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000372\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000372\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x0000034a\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000032c\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x000002f2\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000029e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000026a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000242\n+ R_ARM_REL32\t.data\n+\tldrd\tr2, r3, [sp, #76]\t@ 0x4c\n+\tmov\tfp, r8\n+\tldr\tr1, [sp, #144]\t@ 0x90\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #120]\t@ 0x78\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tadds\tr4, #1\n+\tsubs\tr3, r3, r1\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tr3, r4\n+\tbne.w\t3b0 <__gridxc_fftr_MOD_fftk2r+0x3b0>\n+\tldrd\tr6, r8, [sp, #180]\t@ 0xb4\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #216]\t@ 0xd8\n+\tadd.w\tr8, r8, #1\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tldrd\tr5, sl, [sp, #188]\t@ 0xbc\n+\tsubs\tr3, r3, r2\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr3, [sp, #228]\t@ 0xe4\n+\tadd\tsl, r3\n+\tldr\tr3, [sp, #220]\t@ 0xdc\n+\tcmp\tr8, r3\n+\tbne.w\t35a <__gridxc_fftr_MOD_fftk2r+0x35a>\n+\tldr.w\tr4, [pc, #1648]\t@ ba8 <__gridxc_fftr_MOD_fftk2r+0xba8>\n+\tldr.w\tr3, [pc, #1648]\t@ bac <__gridxc_fftr_MOD_fftk2r+0xbac>\n \tadd\tr4, pc\n-\tadds\tr3, #8\n+\tldr\tr7, [sp, #208]\t@ 0xd0\n+\tldr.w\tr1, [pc, #1644]\t@ bb0 <__gridxc_fftr_MOD_fftk2r+0xbb0>\n+\tadd\tr3, pc\n \tmov\tr0, r4\n+\tadds\tr3, #8\n+\tadd\tr1, pc\n \tmov\tr2, r7\n-\tmov\tr1, r5\n+\tmov\tr5, r1\n \tbl\t0 <__gridxc_fft3d_MOD_fft3d>\n R_ARM_THM_CALL\t__gridxc_fft3d_MOD_fft3d\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr3, [sp, #260]\t@ 0x104\n-\tldr\tr0, [r4, #36]\t@ 0x24\n-\tldr\tr2, [r4, #60]\t@ 0x3c\n-\tstr\tr0, [sp, #412]\t@ 0x19c\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n-\tstr\tr2, [sp, #436]\t@ 0x1b4\n-\tvstr\td16, [r3]\n-\tadd.w\tr3, r4, #20\n-\tvld1.32\t{d16}, [r3]\n-\tldr\tr3, [sp, #264]\t@ 0x108\n-\tvst1.32\t{d16}, [r3]\n \tldr\tr3, [r4, #64]\t@ 0x40\n-\trsb\tr1, r3, #1\n-\tvmov.32\tr3, d16[1]\n-\tmul.w\tr1, r2, r1\n+\tldr\tr2, [r4, #60]\t@ 0x3c\n+\trsb\tr3, r3, #1\n+\tldr\tr0, [r4, #36]\t@ 0x24\n+\tstr\tr0, [sp, #432]\t@ 0x1b0\n+\tstr\tr2, [sp, #456]\t@ 0x1c8\n+\tmul.w\tr1, r2, r3\n+\tldr\tr3, [r4, #24]\n+\tstr\tr3, [sp, #420]\t@ 0x1a4\n \tnegs\tr3, r3\n \tsubs\tr3, r3, r0\n \tldr\tr0, [r4, #48]\t@ 0x30\n-\tstr\tr0, [sp, #424]\t@ 0x1a8\n+\tstr\tr0, [sp, #444]\t@ 0x1bc\n \tsubs\tr3, r3, r0\n \tsubs\tr3, r3, r2\n \tldr\tr2, [r4, #40]\t@ 0x28\n-\tstr\tr3, [sp, #380]\t@ 0x17c\n+\tstr\tr3, [sp, #400]\t@ 0x190\n \trsb\tr0, r2, #1\n \tldr\tr2, [r4, #52]\t@ 0x34\n \tldr\tr3, [r4, #28]\n \trsb\tr6, r2, #1\n \tldr\tr2, [r4, #0]\n \trsb\tr3, r3, #1\n \tadd.w\tr2, r2, r1, lsl #3\n-\tstr\tr2, [sp, #376]\t@ 0x178\n+\tstr\tr2, [sp, #396]\t@ 0x18c\n \tldr\tr2, [r4, #32]\n+\tldr\tr1, [sp, #288]\t@ 0x120\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #408]\t@ 0x198\n+\tstr\tr3, [sp, #428]\t@ 0x1ac\n \tldr\tr3, [r4, #44]\t@ 0x2c\n-\tmovs\tr2, #8\n-\tstr\tr2, [sp, #384]\t@ 0x180\n+\tmovs\tr2, #0\n \tadd\tr0, r3\n \tldr\tr3, [r4, #56]\t@ 0x38\n-\tstr\tr0, [sp, #420]\t@ 0x1a4\n-\tmov\tr0, r7\n+\tstr\tr0, [sp, #440]\t@ 0x1b8\n+\tmov.w\tr0, #772\t@ 0x304\n \tadd\tr6, r3\n-\tmovs\tr3, #1\n-\tstr\tr6, [sp, #432]\t@ 0x1b0\n-\tstr\tr3, [sp, #404]\t@ 0x194\n+\tldr\tr3, [r4, #20]\n \tstr\tr3, [sp, #416]\t@ 0x1a0\n-\tstr\tr3, [sp, #428]\t@ 0x1ac\n-\tstrd\tr3, r3, [sp, #440]\t@ 0x1b8\n-\tstr\tr2, [sp, #472]\t@ 0x1d8\n-\tldr\tr1, [sp, #232]\t@ 0xe8\n-\tstr\tr1, [sp, #452]\t@ 0x1c4\n-\tldr\tr1, [sp, #208]\t@ 0xd0\n-\tstr\tr1, [sp, #0]\n-\tldr\tr1, [sp, #216]\t@ 0xd8\n-\tstr\tr1, [sp, #484]\t@ 0x1e4\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tstr\tr1, [sp, #476]\t@ 0x1dc\n-\tldr\tr1, [sp, #220]\t@ 0xdc\n-\tstr\tr1, [sp, #496]\t@ 0x1f0\n-\tldr\tr1, [sp, #56]\t@ 0x38\n+\tmovs\tr3, #1\n+\tstrd\tr2, r2, [r1]\n+\tmovs\tr1, #8\n+\tstr\tr3, [sp, #424]\t@ 0x1a8\n+\tstr\tr3, [sp, #436]\t@ 0x1b4\n+\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tstrd\tr3, r3, [sp, #460]\t@ 0x1cc\n+\tstr\tr1, [sp, #404]\t@ 0x194\n+\tstr\tr6, [sp, #452]\t@ 0x1c4\n+\tstrh.w\tr0, [sp, #412]\t@ 0x19c\n \tstr\tr1, [sp, #488]\t@ 0x1e8\n-\tldr\tr1, [sp, #224]\t@ 0xe0\n-\tstr\tr3, [sp, #480]\t@ 0x1e0\n-\tstr\tr3, [sp, #492]\t@ 0x1ec\n-\tstr\tr3, [sp, #504]\t@ 0x1f8\n-\tstr\tr1, [sp, #508]\t@ 0x1fc\n-\tstrd\tr3, r3, [sp, #516]\t@ 0x204\n-\tldr\tr1, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #228]\t@ 0xe4\n-\tldr\tr4, [sp, #204]\t@ 0xcc\n-\tstr\tr2, [sp, #460]\t@ 0x1cc\n-\tmov.w\tr2, #772\t@ 0x304\n+\tstr\tr1, [sp, #476]\t@ 0x1dc\n+\tldr\tr1, [sp, #260]\t@ 0x104\n+\tstr\tr1, [sp, #468]\t@ 0x1d4\n+\tldr\tr1, [sp, #236]\t@ 0xec\n+\tstr\tr1, [sp, #0]\n+\tldr\tr1, [sp, #268]\t@ 0x10c\n+\tldr\tr4, [sp, #232]\t@ 0xe8\n+\tstrd\tr2, r2, [r1]\n+\tldr\tr1, [sp, #244]\t@ 0xf4\n \tstr\tr1, [sp, #500]\t@ 0x1f4\n+\tldr\tr1, [sp, #124]\t@ 0x7c\n+\tstr\tr1, [sp, #492]\t@ 0x1ec\n+\tldr\tr1, [sp, #248]\t@ 0xf8\n+\tstr\tr1, [sp, #512]\t@ 0x200\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tstr\tr1, [sp, #504]\t@ 0x1f8\n+\tldr\tr1, [sp, #252]\t@ 0xfc\n+\tstr\tr3, [sp, #496]\t@ 0x1f0\n+\tstr\tr3, [sp, #508]\t@ 0x1fc\n+\tstr\tr3, [sp, #520]\t@ 0x208\n+\tstr\tr1, [sp, #524]\t@ 0x20c\n+\tstrd\tr3, r3, [sp, #532]\t@ 0x214\n+\tldr\tr1, [sp, #148]\t@ 0x94\n+\tldr\tr3, [sp, #256]\t@ 0x100\n+\tstrh.w\tr0, [sp, #484]\t@ 0x1e4\n+\tmov\tr0, r7\n+\tstr\tr1, [sp, #516]\t@ 0x204\n \tmov\tr1, r5\n-\tstrh.w\tr2, [sp, #392]\t@ 0x188\n-\tstrh.w\tr2, [sp, #468]\t@ 0x1d4\n-\tstr\tr3, [sp, #456]\t@ 0x1c8\n+\tstr\tr3, [sp, #472]\t@ 0x1d8\n \tadds\tr3, r5, #4\n+\tstr\tr4, [sp, #528]\t@ 0x210\n \tstr\tr3, [sp, #4]\n-\tldrd\tr3, r2, [sp, #252]\t@ 0xfc\n-\tstr\tr4, [sp, #512]\t@ 0x200\n+\tldrd\tr3, r2, [sp, #280]\t@ 0x118\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tldr\tr3, [sp, #212]\t@ 0xd4\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #240]\t@ 0xf0\n \tadd\tr2, r4\n-\tstr\tr2, [sp, #136]\t@ 0x88\n-\tldr\tr2, [sp, #244]\t@ 0xf4\n+\tstr\tr2, [sp, #160]\t@ 0xa0\n+\tldr\tr2, [sp, #272]\t@ 0x110\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #212]\t@ 0xd4\n+\tstr\tr3, [sp, #240]\t@ 0xf0\n \tcmp\tr2, r3\n-\tbge.w\t270 <__gridxc_fftr_MOD_fftk2r+0x270>\n-\tldr.w\tr3, [pc, #1364]\t@ b28 <__gridxc_fftr_MOD_fftk2r+0xb28>\n+\tbge.w\t24e <__gridxc_fftr_MOD_fftk2r+0x24e>\n+\tldr.w\tr3, [pc, #1412]\t@ bb4 <__gridxc_fftr_MOD_fftk2r+0xbb4>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tbne.w\td54 <__gridxc_fftr_MOD_fftk2r+0xd54>\n-\tldr.w\tr1, [pc, #1356]\t@ b2c <__gridxc_fftr_MOD_fftk2r+0xb2c>\n+\tbne.w\te26 <__gridxc_fftr_MOD_fftk2r+0xe26>\n+\tldr.w\tr1, [pc, #1404]\t@ bb8 <__gridxc_fftr_MOD_fftk2r+0xbb8>\n \tmovs\tr2, #0\n-\tldr.w\tr0, [pc, #1352]\t@ b30 <__gridxc_fftr_MOD_fftk2r+0xb30>\n+\tldr.w\tr0, [pc, #1400]\t@ bbc <__gridxc_fftr_MOD_fftk2r+0xbbc>\n \tmovs\tr3, #9\n \tstr\tr2, [sp, #0]\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr.w\tr2, [pc, #1340]\t@ b34 <__gridxc_fftr_MOD_fftk2r+0xb34>\n-\tldr.w\tr3, [pc, #1256]\t@ ae4 <__gridxc_fftr_MOD_fftk2r+0xae4>\n+\tldr.w\tr2, [pc, #1388]\t@ bc0 <__gridxc_fftr_MOD_fftk2r+0xbc0>\n+\tldr.w\tr3, [pc, #1388]\t@ bc4 <__gridxc_fftr_MOD_fftk2r+0xbc4>\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #524]\t@ 0x20c\n+\tldr\tr3, [sp, #540]\t@ 0x21c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\td6a <__gridxc_fftr_MOD_fftk2r+0xd6a>\n-\tadd.w\tsp, sp, #532\t@ 0x214\n-\tvpop\t{d8}\n+\tbne.w\te3e <__gridxc_fftr_MOD_fftk2r+0xe3e>\n+\tadd.w\tsp, sp, #548\t@ 0x224\n+\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tcmp\tr5, #0\n-\tble.w\t3c8 <__gridxc_fftr_MOD_fftk2r+0x3c8>\n-\tsubs\tr2, r5, #1\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tsdiv\tr2, r2, r1\n-\tsubs\tr2, #1\n-\tb.n\t3cc <__gridxc_fftr_MOD_fftk2r+0x3cc>\n-\tadds\tr2, r5, #1\n-\tb.n\t622 <__gridxc_fftr_MOD_fftk2r+0x622>\n-\tsubs\tr2, r3, #1\n-\tcmp\tr3, #0\n-\tble.w\t384 <__gridxc_fftr_MOD_fftk2r+0x384>\n-\tsdiv\tr2, r2, ip\n-\tsubs\tr2, #1\n+\tcmp\tr7, #0\n+\tit\tgt\n+\taddgt.w\tr0, r7, #4294967295\t@ 0xffffffff\n+\tble.w\t3c4 <__gridxc_fftr_MOD_fftk2r+0x3c4>\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t3ca <__gridxc_fftr_MOD_fftk2r+0x3ca>\n+\tadds\tr0, r7, #1\n+\tb.n\t682 <__gridxc_fftr_MOD_fftk2r+0x682>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.w\t37e <__gridxc_fftr_MOD_fftk2r+0x37e>\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, #1\n \tb.n\t388 <__gridxc_fftr_MOD_fftk2r+0x388>\n-\tadds\tr2, r3, #1\n-\tb.n\t638 <__gridxc_fftr_MOD_fftk2r+0x638>\n-\tldr\tr3, [sp, #248]\t@ 0xf8\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #4]\n+\tadds\tr0, r4, #1\n+\tb.n\t69a <__gridxc_fftr_MOD_fftk2r+0x69a>\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tmovs\tr4, #1\n-\tldr\tr3, [sp, #216]\t@ 0xd8\n-\tstr\tr3, [sp, #484]\t@ 0x1e4\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tstr\tr3, [sp, #476]\t@ 0x1dc\n-\tldr\tr3, [sp, #220]\t@ 0xdc\n-\tstr\tr3, [sp, #496]\t@ 0x1f0\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #488]\t@ 0x1e8\n-\tldr\tr3, [sp, #224]\t@ 0xe0\n-\tstr\tr3, [sp, #508]\t@ 0x1fc\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #4]\n+\tldr\tr3, [sp, #244]\t@ 0xf4\n \tstr\tr3, [sp, #500]\t@ 0x1f4\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n-\tldr\tr1, [sp, #236]\t@ 0xec\n-\tldr\tr0, [sp, #184]\t@ 0xb8\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #204]\t@ 0xcc\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #492]\t@ 0x1ec\n+\tldr\tr3, [sp, #248]\t@ 0xf8\n \tstr\tr3, [sp, #512]\t@ 0x200\n-\tldr\tr3, [sp, #228]\t@ 0xe4\n-\tstr\tr3, [sp, #456]\t@ 0x1c8\n-\tldr\tr3, [sp, #268]\t@ 0x10c\n-\tstr\tr2, [sp, #452]\t@ 0x1c4\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #504]\t@ 0x1f8\n+\tldr\tr3, [sp, #252]\t@ 0xfc\n+\tstr\tr3, [sp, #524]\t@ 0x20c\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #516]\t@ 0x204\n+\tldr\tr3, [sp, #232]\t@ 0xe8\n+\tstr\tr3, [sp, #528]\t@ 0x210\n+\tldr\tr5, [sp, #268]\t@ 0x10c\n+\tldr\tr3, [sp, #256]\t@ 0x100\n+\tstr\tr3, [sp, #472]\t@ 0x1d8\n+\tldr\tr3, [sp, #292]\t@ 0x124\n+\tstr\tr2, [sp, #468]\t@ 0x1d4\n+\tstr\tr4, [sp, #496]\t@ 0x1f0\n \tadds\tr3, #72\t@ 0x48\n-\tldr\tr2, [sp, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #508]\t@ 0x1fc\n \tstr\tr3, [sp, #0]\n-\tadd\tr3, sp, #352\t@ 0x160\n-\tstr\tr4, [sp, #480]\t@ 0x1e0\n-\tstr\tr4, [sp, #492]\t@ 0x1ec\n-\tstr\tr4, [sp, #504]\t@ 0x1f8\n-\tstrd\tr4, r4, [sp, #516]\t@ 0x204\n+\tadd\tr3, sp, #348\t@ 0x15c\n+\tstr\tr4, [sp, #520]\t@ 0x208\n+\tstrd\tr4, r4, [sp, #532]\t@ 0x214\n \tmovs\tr4, #8\n-\tstr\tr4, [sp, #472]\t@ 0x1d8\n-\tstr\tr4, [sp, #460]\t@ 0x1cc\n+\tldr\tr2, [sp, #236]\t@ 0xec\n+\tstr\tr4, [sp, #488]\t@ 0x1e8\n+\tstr\tr4, [sp, #476]\t@ 0x1dc\n+\tmovs\tr4, #0\n+\tldr\tr1, [sp, #264]\t@ 0x108\n+\tldr\tr0, [sp, #208]\t@ 0xd0\n+\tstrd\tr4, r4, [r5]\n \tmov.w\tr4, #772\t@ 0x304\n-\tstrh.w\tr4, [sp, #468]\t@ 0x1d4\n+\tstrh.w\tr4, [sp, #484]\t@ 0x1e4\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tb.n\t284 <__gridxc_fftr_MOD_fftk2r+0x284>\n-\tldr\tr3, [sp, #104]\t@ 0x68\n+\tb.n\t262 <__gridxc_fftr_MOD_fftk2r+0x262>\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n \tcmp\tr3, #1\n-\tbne.w\t8ac <__gridxc_fftr_MOD_fftk2r+0x8ac>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tldr\tr2, [sp, #184]\t@ 0xb8\n-\tldr.w\tip, [sp, #136]\t@ 0x88\n-\tstr\tr7, [sp, #168]\t@ 0xa8\n-\tmul.w\tr3, r1, r3\n-\tldr\tr1, [sp, #152]\t@ 0x98\n-\tldrd\tsl, r5, [r2]\n-\tstr.w\tfp, [sp, #192]\t@ 0xc0\n-\tstr\tr5, [sp, #64]\t@ 0x40\n-\tmla\tr3, r7, r1, r3\n-\tmul.w\tlr, sl, r5\n-\tadds\tr0, r3, r4\n-\tldr\tr4, [r2, #8]\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tmul.w\tr2, fp, r6\n-\tstr\tr2, [sp, #120]\t@ 0x78\n+\tbne.w\t948 <__gridxc_fftr_MOD_fftk2r+0x948>\n+\tldr\tr4, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr1, [sp, #208]\t@ 0xd0\n+\tldr\tr6, [sp, #52]\t@ 0x34\n+\tldr\tr7, [sp, #160]\t@ 0xa0\n+\tmul.w\tr3, r4, r3\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tldrd\tr8, r0, [r1]\n+\tstr\tr5, [sp, #192]\t@ 0xc0\n+\tstr\tr0, [sp, #88]\t@ 0x58\n+\tmla\tr3, r5, r4, r3\n+\tmov\tr5, r7\n \tmov\tr7, r4\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tmov\tr4, r0\n-\tmov\tr0, r1\n+\tadd\tr6, r3\n+\tmul.w\tr3, r8, r0\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tmov\tsl, r6\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tmov\tfp, sl\n+\tldr\tr6, [r1, #8]\n+\tmov\tsl, r8\n+\tmov\tr9, r6\n+\tmul.w\tr3, r3, r2\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tmul.w\tr2, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tldr\tr2, [sp, #204]\t@ 0xcc\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #164]\t@ 0xa4\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tmul.w\tr3, r3, r6\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tstr\tr2, [sp, #188]\t@ 0xbc\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tadds\tr3, #2\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #88]\t@ 0x58\n-\tadd.w\tr2, fp, #1\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #172]\t@ 0xac\n-\tmov\tfp, r3\n-\tadds\tr6, r2, #2\n-\tstr\tr6, [sp, #188]\t@ 0xbc\n-\tmul.w\tr3, r0, lr\n-\tnegs\tr1, r0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tcmp\tr7, #0\n+\tstr\tr2, [sp, #112]\t@ 0x70\n \tldr\tr3, [sp, #140]\t@ 0x8c\n-\tsub.w\tr3, r4, r3\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tblt.w\t88e <__gridxc_fftr_MOD_fftk2r+0x88e>\n-\tcmp\tr1, #0\n-\tblt.w\t89e <__gridxc_fftr_MOD_fftk2r+0x89e>\n-\tsdiv\tr3, r1, r7\n-\tldr\tr6, [sp, #100]\t@ 0x64\n-\tmls\tr1, r7, r3, r1\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tmov\tr5, r4\n-\tadds\tr3, r6, #1\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\tldr\tr3, [sp, #188]\t@ 0xbc\n-\tmul.w\tr9, r1, lr\n-\tstr\tr0, [sp, #124]\t@ 0x7c\n-\tadd\tr3, r6\n-\tldr\tr6, [sp, #128]\t@ 0x80\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #136]\t@ 0x88\n-\tstrd\tlr, r7, [sp, #144]\t@ 0x90\n-\tstrd\tip, r4, [sp, #156]\t@ 0x9c\n-\tmla\tr3, r6, r1, r3\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tmov\tr3, ip\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tmul.w\tr6, r2, sl\n-\trsb\tip, r2, #0\n-\tcmp\tr1, #0\n-\tblt.w\t872 <__gridxc_fftr_MOD_fftk2r+0x872>\n-\tcmp.w\tip, #0\n-\tblt.w\t888 <__gridxc_fftr_MOD_fftk2r+0x888>\n-\tsdiv\tr1, ip, r1\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tldr\tr7, [sp, #60]\t@ 0x3c\n-\tldr\tr4, [sp, #80]\t@ 0x50\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tmls\tip, r0, r1, ip\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tstr\tr5, [sp, #96]\t@ 0x60\n-\tadds\tr0, r5, r1\n-\tadd\tr7, r1\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tmul.w\tr8, sl, ip\n-\tmul.w\tr0, r4, r0\n-\tmul.w\tr7, r4, r7\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tsubs\tr7, r7, r0\n-\tadd\tr0, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd\tr1, r6\n-\tadd\tr1, r4\n-\tldr\tr4, [sp, #108]\t@ 0x6c\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tmla\tip, r1, ip, r4\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tadd.w\tr4, r1, r3, lsl #3\n-\tldr\tr1, [sp, #112]\t@ 0x70\n-\tadd.w\tlr, r1, r6\n-\tldr\tr1, [sp, #116]\t@ 0x74\n-\tadd\tr6, r1\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tb.n\t7f0 <__gridxc_fftr_MOD_fftk2r+0x7f0>\n-\tcmp\tr3, #0\n-\tblt.n\t86e <__gridxc_fftr_MOD_fftk2r+0x86e>\n-\tsdiv\tr2, r3, sl\n-\tmls\tr3, sl, r2, r3\n-\tvldmia\tr4!, {d16}\n-\tadds\tr5, r0, r7\n+\tnegs\tr4, r7\n+\tcmp.w\tr9, #0\n+\tmul.w\tr3, r7, r3\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tsub.w\tr3, fp, r3\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tblt.w\t922 <__gridxc_fftr_MOD_fftk2r+0x922>\n+\tcmp\tr4, #0\n+\tblt.w\t938 <__gridxc_fftr_MOD_fftk2r+0x938>\n+\tmov\tr1, r9\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tmls\tr4, r9, r2, r4\n+\tldr\tr6, [sp, #152]\t@ 0x98\n \tadds\tr2, r3, #1\n-\tadd\tr2, r8\n-\tadd\tr2, r9\n-\tcmp\tr2, r1\n-\tbeq.n\t806 <__gridxc_fftr_MOD_fftk2r+0x806>\n-\tble.n\t858 <__gridxc_fftr_MOD_fftk2r+0x858>\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tadd\tr3, ip\n-\tvstr\td16, [r5]\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tvldr\td16, [r3]\n-\tadds\tr1, #1\n-\tvstr\td16, [r0]\n-\tcmp\tr1, lr\n-\tadd\tr0, fp\n-\tbeq.n\t81a <__gridxc_fftr_MOD_fftk2r+0x81a>\n-\tsubs\tr3, r6, r1\n-\tcmp.w\tsl, #0\n-\tbge.n\t7b6 <__gridxc_fftr_MOD_fftk2r+0x7b6>\n-\tsubs\tr2, r3, #1\n-\tcmp\tr3, #0\n-\tble.n\t7ba <__gridxc_fftr_MOD_fftk2r+0x7ba>\n-\tsdiv\tr2, r2, sl\n-\tsubs\tr2, #1\n-\tb.n\t7be <__gridxc_fftr_MOD_fftk2r+0x7be>\n-\tvstr\td16, [r5]\n-\tvmov.f64\td16, d8\n-\tadds\tr1, #1\n-\tcmp\tr1, lr\n-\tvstr\td16, [r0]\n-\tadd\tr0, fp\n-\tbne.n\t7f0 <__gridxc_fftr_MOD_fftk2r+0x7f0>\n-\tldrd\tr3, r2, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tadds\tr2, #1\n-\tldr\tr5, [sp, #96]\t@ 0x60\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tadd\tr0, r1\n-\tadd\tr5, r1\n+\tstr\tr2, [sp, #132]\t@ 0x84\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n+\tstr.w\tr9, [sp, #164]\t@ 0xa4\n+\tmov\tr9, sl\n+\tadds\tr3, r2, r3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [sp, #148]\t@ 0x94\n+\tstr.w\tfp, [sp, #80]\t@ 0x50\n+\tstr\tr5, [sp, #72]\t@ 0x48\n+\tmul.w\tr3, r4, r3\n+\tstr\tr7, [sp, #144]\t@ 0x90\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr5, [sp, #168]\t@ 0xa8\n+\tstr.w\tfp, [sp, #180]\t@ 0xb4\n+\tmla\tr3, r2, r4, r3\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tldr\tr1, [sp, #88]\t@ 0x58\n-\tstr\tr0, [sp, #60]\t@ 0x3c\n-\tcmp\tr2, r1\n-\tbne.n\t74c <__gridxc_fftr_MOD_fftk2r+0x74c>\n-\tldrd\tip, r4, [sp, #156]\t@ 0x9c\n+\tmul.w\tr7, r6, r9\n+\tnegs\tr4, r6\n+\tcmp\tr1, #0\n+\tblt.w\t90a <__gridxc_fftr_MOD_fftk2r+0x90a>\n+\tcmp\tr4, #0\n+\tblt.w\t91e <__gridxc_fftr_MOD_fftk2r+0x91e>\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tldr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr6, [sp, #92]\t@ 0x5c\n+\tmov\tr6, r9\n+\tmls\tr3, r3, r0, r4\n+\tldr\tr0, [sp, #84]\t@ 0x54\n+\tadds\tr5, r1, r2\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tadd.w\tr8, r0, r2\n+\tldr\tr2, [sp, #116]\t@ 0x74\n+\tmul.w\tr5, r1, r5\n+\tmul.w\tr8, r1, r8\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tsub.w\tr8, r8, r5\n+\tadd\tr5, r2\n+\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tadds\tr4, r2, r7\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tadd\tr4, r2\n+\tmul.w\tr2, r9, r3\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tmla\tr3, r1, r3, r2\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tsl, r3, r2, lsl #3\n \tldr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tadd\tip, r3\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n-\tadds\tr0, #1\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tldrd\tlr, r7, [sp, #144]\t@ 0x90\n-\tcmp\tr0, r3\n-\tbne.w\t6fe <__gridxc_fftr_MOD_fftk2r+0x6fe>\n-\tldr.w\tfp, [sp, #192]\t@ 0xc0\n-\tb.n\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n+\tadd.w\tfp, r3, r7\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tadd\tr7, r3\n+\tmov\tr3, r8\n+\tmov\tr9, r7\n+\tmov\tr8, sl\n+\tmov\tsl, r3\n+\tb.n\t884 <__gridxc_fftr_MOD_fftk2r+0x884>\n+\tcmp\tr7, #0\n+\tblt.n\t8c2 <__gridxc_fftr_MOD_fftk2r+0x8c2>\n+\tmov\tr1, r6\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr0, r6, r0, r7\n \tldr\tr2, [sp, #52]\t@ 0x34\n-\tadd\tr3, ip\n-\tvneg.f64\td16, d16\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tldrd\tr2, r3, [r3]\n-\tstrd\tr2, r3, [r5]\n-\tb.n\t7e4 <__gridxc_fftr_MOD_fftk2r+0x7e4>\n-\tadds\tr2, r3, #1\n-\tb.n\t7fe <__gridxc_fftr_MOD_fftk2r+0x7fe>\n-\tcmp.w\tip, #0\n-\tble.w\t764 <__gridxc_fftr_MOD_fftk2r+0x764>\n-\tadd.w\tr1, ip, #4294967295\t@ 0xffffffff\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tsdiv\tr1, r1, r0\n-\tsubs\tr1, #1\n-\tb.n\t768 <__gridxc_fftr_MOD_fftk2r+0x768>\n-\tadd.w\tr1, ip, #1\n-\tb.n\t87e <__gridxc_fftr_MOD_fftk2r+0x87e>\n-\tsubs\tr3, r1, #1\n-\tcmp\tr1, #0\n-\tble.w\t71a <__gridxc_fftr_MOD_fftk2r+0x71a>\n-\tsdiv\tr3, r3, r7\n-\tsubs\tr3, #1\n-\tb.n\t71e <__gridxc_fftr_MOD_fftk2r+0x71e>\n-\tadds\tr3, r1, #1\n+\tvldmia\tr8!, {d7}\n+\tadd.w\tip, r5, sl\n+\tadds\tr3, r0, #1\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tadd\tr3, r2\n+\tcmp\tr3, r4\n+\tbeq.n\t8a0 <__gridxc_fftr_MOD_fftk2r+0x8a0>\n+\tble.n\t8aa <__gridxc_fftr_MOD_fftk2r+0x8aa>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tvstr\td7, [ip]\n+\tadd\tr0, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvldr\td7, [r0]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadds\tr4, #1\n+\tvstr\td7, [r5]\n+\tcmp\tr4, fp\n+\tadd\tr5, r3\n+\tbeq.n\t8c6 <__gridxc_fftr_MOD_fftk2r+0x8c6>\n+\tsub.w\tr7, r9, r4\n+\tcmp\tr6, #0\n+\tbge.n\t83c <__gridxc_fftr_MOD_fftk2r+0x83c>\n+\tcmp\tr7, #0\n+\tit\tgt\n+\taddgt.w\tr0, r7, #4294967295\t@ 0xffffffff\n+\tble.n\t840 <__gridxc_fftr_MOD_fftk2r+0x840>\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t848 <__gridxc_fftr_MOD_fftk2r+0x848>\n+\tvstr\td7, [ip]\n+\tvmov.f64\td7, d8\n+\tb.n\t876 <__gridxc_fftr_MOD_fftk2r+0x876>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tvneg.f64\td7, d7\n+\tadd\tr0, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvldr\td6, [r0]\n+\tvstr\td6, [ip]\n+\tb.n\t876 <__gridxc_fftr_MOD_fftk2r+0x876>\n+\tadds\tr0, r7, #1\n \tb.n\t896 <__gridxc_fftr_MOD_fftk2r+0x896>\n+\tldrd\tr3, r2, [sp, #72]\t@ 0x48\n+\tmov\tr9, r6\n+\tldr\tr6, [sp, #92]\t@ 0x5c\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tadds\tr6, #1\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tr6, r3\n+\tbne.w\t7c6 <__gridxc_fftr_MOD_fftk2r+0x7c6>\n+\tmov\tsl, r9\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldrd\tr9, r5, [sp, #164]\t@ 0xa4\n+\tldr.w\tfp, [sp, #180]\t@ 0xb4\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tldr\tr7, [sp, #144]\t@ 0x90\n+\tadd\tfp, r3\n+\tldr\tr3, [sp, #188]\t@ 0xbc\n+\tadds\tr7, #1\n+\tcmp\tr7, r3\n+\tbne.w\t764 <__gridxc_fftr_MOD_fftk2r+0x764>\n+\tb.n\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.w\t7da <__gridxc_fftr_MOD_fftk2r+0x7da>\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t7e0 <__gridxc_fftr_MOD_fftk2r+0x7e0>\n+\tadds\tr0, r4, #1\n+\tb.n\t916 <__gridxc_fftr_MOD_fftk2r+0x916>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.w\t784 <__gridxc_fftr_MOD_fftk2r+0x784>\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr2, r0, #1\n+\tb.n\t78e <__gridxc_fftr_MOD_fftk2r+0x78e>\n+\tadds\tr0, r4, #1\n+\tb.n\t92e <__gridxc_fftr_MOD_fftk2r+0x92e>\n \tadds\tr4, #12\n-\tcmp\tr5, r9\n-\tbne.w\t106 <__gridxc_fftr_MOD_fftk2r+0x106>\n-\tb.n\t14e <__gridxc_fftr_MOD_fftk2r+0x14e>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tvmov.i64\td18, #0x0000000000000000\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tmov\tr8, r7\n-\tldr\tr2, [sp, #184]\t@ 0xb8\n-\tldr.w\tlr, [sp, #136]\t@ 0x88\n-\tstr.w\tfp, [sp, #164]\t@ 0xa4\n-\tmul.w\tr3, r1, r3\n-\tldr\tr1, [sp, #152]\t@ 0x98\n-\tldrd\tsl, r5, [r2]\n-\tldr\tr0, [r2, #8]\n-\tmul.w\tr2, fp, r6\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n-\tmla\tr3, r7, r1, r3\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tadd.w\tip, r3, r4\n-\tmul.w\tr3, r5, sl\n+\tcmp\tr5, r6\n+\tbne.w\tfc <__gridxc_fftr_MOD_fftk2r+0xfc>\n+\tb.w\t142 <__gridxc_fftr_MOD_fftk2r+0x142>\n+\tldr\tr4, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr1, [sp, #208]\t@ 0xd0\n+\tldr\tr7, [sp, #160]\t@ 0xa0\n+\tldr.w\tr9, [sp, #176]\t@ 0xb0\n+\tmul.w\tr3, r4, r3\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tldrd\tr8, r0, [r1]\n+\tstr\tr0, [sp, #92]\t@ 0x5c\n+\tvldr\td9, [pc, #572]\t@ ba0 <__gridxc_fftr_MOD_fftk2r+0xba0>\n+\tmla\tr3, r5, r4, r3\n+\tldr\tr4, [sp, #52]\t@ 0x34\n+\tmul.w\tr6, r0, r8\n+\tadd\tr4, r3\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tmov\tsl, r4\n+\tldr\tr4, [r1, #8]\n+\tmov\tfp, r6\n+\tmul.w\tr3, r3, r2\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tmul.w\tr2, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr2, [sp, #132]\t@ 0x84\n+\tldr\tr2, [sp, #204]\t@ 0xcc\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #160]\t@ 0xa0\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tmov\tr4, r1\n-\tstr\tr3, [sp, #156]\t@ 0x9c\n-\tldr\tr3, [sp, #80]\t@ 0x50\n+\tstr\tr2, [sp, #144]\t@ 0x90\n+\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n \tlsls\tr2, r2, #3\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n+\tadds\tr3, #2\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tmov\tr3, sl\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tmov\tsl, r8\n+\tmov\tr8, r7\n+\tmov\tr7, r3\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #88]\t@ 0x58\n-\tadd.w\tr2, fp, #1\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #172]\t@ 0xac\n-\tmul.w\tr3, r3, r6\n-\tadds\tr6, r2, #2\n-\tmov\tfp, r3\n-\tmov\tr2, r5\n-\tmov\tr7, r6\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tnegs\tr1, r4\n-\tcmp\tr0, #0\n-\tmul.w\tr3, r4, r3\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tsub.w\tr5, ip, r3\n-\tblt.w\taca <__gridxc_fftr_MOD_fftk2r+0xaca>\n-\tcmp\tr1, #0\n-\tblt.w\tada <__gridxc_fftr_MOD_fftk2r+0xada>\n-\tsdiv\tr3, r1, r0\n-\tldr\tr6, [sp, #112]\t@ 0x70\n-\tmls\tr1, r0, r3, r1\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tadds\tr3, r6, #1\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tadds\tr3, r7, r6\n-\tstr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tldr\tr6, [sp, #128]\t@ 0x80\n-\tstrd\tlr, ip, [sp, #68]\t@ 0x44\n-\tstr\tr0, [sp, #168]\t@ 0xa8\n-\tmul.w\tr9, r1, r3\n-\tldr\tr3, [sp, #136]\t@ 0x88\n-\tstr.w\tr8, [sp, #188]\t@ 0xbc\n-\tstr\tr4, [sp, #192]\t@ 0xc0\n-\tstrd\tlr, ip, [sp, #196]\t@ 0xc4\n-\tmla\tr3, r6, r1, r3\n-\tmov\tr1, r5\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\tmov\tr5, r2\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tmov\tr2, r1\n-\tstr\tr7, [sp, #272]\t@ 0x110\n-\tmul.w\tr6, r3, sl\n-\trsb\tip, r3, #0\n-\tcmp\tr5, #0\n-\tblt.w\tab0 <__gridxc_fftr_MOD_fftk2r+0xab0>\n-\tcmp.w\tip, #0\n-\tblt.w\tac4 <__gridxc_fftr_MOD_fftk2r+0xac4>\n-\tsdiv\tr1, ip, r5\n-\tmls\tip, r5, r1, ip\n-\tldr\tr0, [sp, #72]\t@ 0x48\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tldr\tr4, [sp, #80]\t@ 0x50\n-\tadd\tr0, r1\n-\tadds\tr7, r2, r1\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tmul.w\tr3, r9, fp\n+\trsb\tr6, r9, #0\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tcmp\tr4, #0\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tsub.w\tr3, r7, r3\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tblt.w\tb82 <__gridxc_fftr_MOD_fftk2r+0xb82>\n+\tcmp\tr6, #0\n+\tblt.w\tb98 <__gridxc_fftr_MOD_fftk2r+0xb98>\n+\tmov\tr1, r4\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tmls\tr2, r4, r2, r6\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tadds\tr1, r3, #1\n+\tstr\tr1, [sp, #140]\t@ 0x8c\n+\tldr\tr1, [sp, #156]\t@ 0x9c\n+\tstr.w\tr9, [sp, #188]\t@ 0xbc\n+\tmov\tr9, sl\n+\tadds\tr3, r1, r3\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tmul.w\tr3, r2, fp\n+\tldr\tr1, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstrd\tr8, r7, [sp, #80]\t@ 0x50\n+\tstrd\tfp, r4, [sp, #164]\t@ 0xa4\n+\tstr\tr5, [sp, #180]\t@ 0xb4\n+\tmla\tr3, r1, r2, r3\n+\tstr.w\tr8, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tmov\tr3, r6\n+\tstr\tr7, [sp, #212]\t@ 0xd4\n \tldr\tr1, [sp, #92]\t@ 0x5c\n-\tmul.w\tr8, ip, sl\n-\tstr\tr5, [sp, #96]\t@ 0x60\n-\tmul.w\tr0, r4, r0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tmul.w\tr7, r4, r7\n-\tldr\tr4, [sp, #112]\t@ 0x70\n-\tstr\tr2, [sp, #108]\t@ 0x6c\n-\tsubs\tr7, r7, r0\n-\tadd\tr0, r1\n+\tmul.w\tr6, r3, r9\n+\tnegs\tr4, r3\n+\tcmp\tr1, #0\n+\tblt.w\tb64 <__gridxc_fftr_MOD_fftk2r+0xb64>\n+\tcmp\tr4, #0\n+\tblt.w\tb7e <__gridxc_fftr_MOD_fftk2r+0xb7e>\n+\tmov\tr0, r4\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tmov\tr8, r0\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n \tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd\tr1, r6\n-\tadd\tr1, r4\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tmla\tip, r1, ip, r4\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tstr.w\tip, [sp, #64]\t@ 0x40\n-\tldr.w\tip, [sp, #120]\t@ 0x78\n-\tadd.w\tr4, r1, r4, lsl #3\n-\tldr\tr1, [sp, #144]\t@ 0x90\n-\tadd.w\tlr, r1, r6\n-\tldr\tr1, [sp, #148]\t@ 0x94\n-\tadd\tr6, r1\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tstr\tr6, [sp, #60]\t@ 0x3c\n-\tb.n\ta1a <__gridxc_fftr_MOD_fftk2r+0xa1a>\n-\tcmp\tr3, #0\n-\tblt.n\taac <__gridxc_fftr_MOD_fftk2r+0xaac>\n-\tsdiv\tr2, r3, sl\n-\tmls\tr3, sl, r2, r3\n-\tvldr\td16, [r4]\n-\tadds\tr5, r0, r7\n-\tadds\tr2, r3, #1\n-\tadd\tr2, r8\n-\tadd\tr2, r9\n-\tcmp\tr2, r1\n-\tbeq.n\ta34 <__gridxc_fftr_MOD_fftk2r+0xa34>\n-\tble.n\ta90 <__gridxc_fftr_MOD_fftk2r+0xa90>\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tvstr\td16, [r5]\n-\tldr\tr5, [sp, #104]\t@ 0x68\n-\tmla\tr3, r3, r5, r2\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tvldr\td16, [r3]\n-\tadds\tr1, #1\n-\tvstr\td16, [r0]\n-\tadd\tr4, ip\n-\tadd\tr0, fp\n-\tcmp\tr1, lr\n-\tbeq.n\ta4a <__gridxc_fftr_MOD_fftk2r+0xa4a>\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp.w\tsl, #0\n-\tsub.w\tr3, r3, r1\n-\tbge.n\t9d8 <__gridxc_fftr_MOD_fftk2r+0x9d8>\n-\tsubs\tr2, r3, #1\n-\tcmp\tr3, #0\n-\tble.n\t9dc <__gridxc_fftr_MOD_fftk2r+0x9dc>\n-\tsdiv\tr2, r2, sl\n-\tsubs\tr2, #1\n-\tb.n\t9e0 <__gridxc_fftr_MOD_fftk2r+0x9e0>\n-\tvstr\td16, [r5]\n-\tvmov.f64\td16, d18\n-\tadds\tr1, #1\n-\tadd\tr4, ip\n-\tcmp\tr1, lr\n-\tvstr\td16, [r0]\n-\tadd\tr0, fp\n-\tbne.n\ta1a <__gridxc_fftr_MOD_fftk2r+0xa1a>\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tldrd\tr5, r3, [sp, #96]\t@ 0x60\n-\tadd\tr1, r0\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tldrd\tr1, r0, [sp, #72]\t@ 0x48\n-\tadds\tr3, #1\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tmls\tr8, r2, r8, r4\n+\tldr\tr2, [sp, #132]\t@ 0x84\n+\tadds\tr5, r1, r2\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tadds\tr7, r0, r2\n+\tldr\tr2, [sp, #116]\t@ 0x74\n+\tmul.w\tsl, r8, r9\n+\tmul.w\tr5, r1, r5\n+\tmul.w\tr7, r1, r7\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tsubs\tr7, r7, r5\n+\tadd\tr5, r2\n \tldr\tr2, [sp, #108]\t@ 0x6c\n-\tadd\tr1, r0\n-\tstr\tr1, [sp, #72]\t@ 0x48\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr2, r0\n-\tcmp\tr3, r1\n-\tbne.w\t966 <__gridxc_fftr_MOD_fftk2r+0x966>\n-\tldrd\tlr, ip, [sp, #196]\t@ 0xc4\n-\tmov\tr2, r5\n-\tldrd\tr8, r4, [sp, #188]\t@ 0xbc\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tmov\tr3, r7\n+\tadds\tr4, r2, r6\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tadd\tr4, r2\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tmla\tr2, r1, r8, r2\n+\tldr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadd.w\tr8, r2, r1, lsl #3\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tmov\tr7, r8\n+\tmov\tr8, r3\n+\tadd.w\tfp, r2, r6\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tadd\tr2, r6\n+\tmov\tr6, r9\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tb.n\tad2 <__gridxc_fftr_MOD_fftk2r+0xad2>\n+\tcmp.w\tr9, #0\n+\tblt.n\tb18 <__gridxc_fftr_MOD_fftk2r+0xb18>\n+\tmov\tr1, r6\n+\tmov\tr0, r9\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr3, r6, r0, r9\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tvldr\td7, [r7]\n+\tadd.w\tip, r5, r8\n+\tadds\tr0, r3, #1\n+\tadd\tr0, sl\n+\tadd\tr0, r2\n+\tcmp\tr0, r4\n+\tbeq.n\taf2 <__gridxc_fftr_MOD_fftk2r+0xaf2>\n+\tble.n\tafc <__gridxc_fftr_MOD_fftk2r+0xafc>\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr1, [sp, #124]\t@ 0x7c\n+\tvstr\td7, [ip]\n+\tmla\tr3, r3, r1, r2\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tvldr\td7, [r3]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n \tadds\tr4, #1\n-\tldr\tr0, [sp, #168]\t@ 0xa8\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tldr\tr7, [sp, #272]\t@ 0x110\n-\tadd\tip, r8\n-\tcmp\tr4, r3\n-\tbne.w\t90a <__gridxc_fftr_MOD_fftk2r+0x90a>\n-\tldr.w\tfp, [sp, #164]\t@ 0xa4\n-\tb.n\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tvneg.f64\td16, d16\n-\tldr\tr6, [sp, #104]\t@ 0x68\n-\tmla\tr3, r3, r6, r2\n-\tldr\tr2, [sp, #52]\t@ 0x34\n+\tvstr\td7, [r5]\n+\tcmp\tr4, fp\n+\tadd\tr7, r3\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tadd\tr5, r3\n+\tbeq.n\tb1e <__gridxc_fftr_MOD_fftk2r+0xb1e>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr6, #0\n+\tsub.w\tr9, r3, r4\n+\tbge.n\ta82 <__gridxc_fftr_MOD_fftk2r+0xa82>\n+\tcmp.w\tr9, #0\n+\tit\tgt\n+\taddgt.w\tr0, r9, #4294967295\t@ 0xffffffff\n+\tble.n\ta88 <__gridxc_fftr_MOD_fftk2r+0xa88>\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\ta90 <__gridxc_fftr_MOD_fftk2r+0xa90>\n+\tvstr\td7, [ip]\n+\tvmov.f64\td7, d9\n+\tb.n\tac0 <__gridxc_fftr_MOD_fftk2r+0xac0>\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tvneg.f64\td7, d7\n+\tldr\tr1, [sp, #124]\t@ 0x7c\n+\tmla\tr3, r3, r1, r2\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd.w\tr3, r2, r3, lsl #3\n-\tldrd\tr2, r3, [r3]\n-\tstrd\tr2, r3, [r5]\n-\tb.n\ta0c <__gridxc_fftr_MOD_fftk2r+0xa0c>\n-\tadds\tr2, r3, #1\n+\tvldr\td6, [r3]\n+\tvstr\td6, [ip]\n+\tb.n\tac0 <__gridxc_fftr_MOD_fftk2r+0xac0>\n+\tadd.w\tr0, r9, #1\n+\tb.n\tae8 <__gridxc_fftr_MOD_fftk2r+0xae8>\n+\tldrd\tr1, r2, [sp, #76]\t@ 0x4c\n+\tmov\tr9, r6\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tadd\tr2, r1\n+\tldr\tr1, [sp, #100]\t@ 0x64\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tadds\tr3, #1\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #84]\t@ 0x54\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tcmp\tr3, r2\n+\tbne.w\ta0c <__gridxc_fftr_MOD_fftk2r+0xa0c>\n+\tmov\tsl, r9\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldrd\tr9, r8, [sp, #188]\t@ 0xbc\n+\tldr\tr5, [sp, #180]\t@ 0xb4\n+\tldr\tr7, [sp, #212]\t@ 0xd4\n+\tadd\tr8, r3\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tadd.w\tr9, r9, #1\n+\tldrd\tfp, r4, [sp, #164]\t@ 0xa4\n+\tadd\tr7, r5\n+\tcmp\tr9, r3\n+\tbne.w\t9aa <__gridxc_fftr_MOD_fftk2r+0x9aa>\n+\tb.n\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.w\ta20 <__gridxc_fftr_MOD_fftk2r+0xa20>\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadd.w\tr8, r0, #4294967295\t@ 0xffffffff\n \tb.n\ta2c <__gridxc_fftr_MOD_fftk2r+0xa2c>\n-\tadd.w\tr1, ip, #4294967295\t@ 0xffffffff\n-\tcmp.w\tip, #0\n-\tble.w\t97c <__gridxc_fftr_MOD_fftk2r+0x97c>\n-\tsdiv\tr1, r1, r5\n-\tsubs\tr1, #1\n-\tb.n\t980 <__gridxc_fftr_MOD_fftk2r+0x980>\n-\tadd.w\tr1, ip, #1\n-\tb.n\tabc <__gridxc_fftr_MOD_fftk2r+0xabc>\n-\tsubs\tr3, r1, #1\n-\tcmp\tr1, #0\n-\tble.w\t926 <__gridxc_fftr_MOD_fftk2r+0x926>\n-\tsdiv\tr3, r3, r0\n-\tsubs\tr3, #1\n-\tb.n\t92a <__gridxc_fftr_MOD_fftk2r+0x92a>\n-\tadds\tr3, r1, #1\n-\tb.n\tad2 <__gridxc_fftr_MOD_fftk2r+0xad2>\n-\tnop\n-\t.word\t0x00000aba\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000ab0\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000a46\n- R_ARM_REL32\t.data\n-\t.word\t0x000009f8\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000996\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000998\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000998\n- R_ARM_REL32\t.LC1\n-\t.word\t0x0000096e\n- R_ARM_REL32\t.data\n-\t.word\t0x0000094e\n- R_ARM_REL32\t.LC4\n-\t.word\t0x00000912\n- R_ARM_REL32\t.data\n-\t.word\t0x000008b8\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000087e\n+\tadds\tr0, r4, #1\n+\tb.n\tb70 <__gridxc_fftr_MOD_fftk2r+0xb70>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.w\t9c8 <__gridxc_fftr_MOD_fftk2r+0x9c8>\n+\tmov\tr1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr2, r0, #1\n+\tb.n\t9d2 <__gridxc_fftr_MOD_fftk2r+0x9d2>\n+\tadds\tr0, r6, #1\n+\tb.n\tb8e <__gridxc_fftr_MOD_fftk2r+0xb8e>\n+\tnop.w\n+\t...\n+\t.word\t0x00000668\n R_ARM_REL32\t.bss\n-\t.word\t0x0000085e\n- R_ARM_REL32\t.data\n-\t.word\t0x00000640\n+\t.word\t0x00000664\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000640\n+\t.word\t0x00000662\n R_ARM_REL32\t.data\n-\t.word\t0x00000642\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000550\n+\t.word\t0x00000580\n R_ARM_REL32\t.data\n-\t.word\t0x0000053c\n+\t.word\t0x0000056c\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000053e\n+\t.word\t0x0000056e\n R_ARM_REL32\t.bss\n-\t.word\t0x00000534\n+\t.word\t0x00000564\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\tldr\tr5, [sp, #132]\t@ 0x84\n-\tvmov.i64\td17, #0x0000000000000000\n-\tstrd\tr7, fp, [sp, #164]\t@ 0xa4\n-\tnegs\tr2, r5\n-\tmul.w\tr2, r1, r2\n-\tmul.w\tr1, r1, r3\n-\tstr\tr1, [sp, #116]\t@ 0x74\n-\tldr\tr1, [sp, #152]\t@ 0x98\n-\tmls\tr2, ip, r1, r2\n-\tadd\tlr, r2\n-\tmul.w\tr2, r3, ip\n-\tstr\tr2, [sp, #156]\t@ 0x9c\n-\tmls\tr2, fp, r0, lr\n-\tmla\tlr, r3, r2, r9\n-\tldr\tr2, [sp, #184]\t@ 0xb8\n-\tmul.w\tr3, r0, r3\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldrd\tr8, r3, [r2]\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tmul.w\tr3, r0, r5\n-\tmov\tr0, r1\n-\tmla\tr3, r1, r7, r3\n-\tldr\tr1, [r2, #8]\n-\tadds\tr5, r3, r4\n-\tldr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr4, [sp, #136]\t@ 0x88\n-\tmul.w\tr3, r3, r8\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tmul.w\tsl, r3, r6\n-\tmul.w\tr3, fp, r6\n-\tstr\tr3, [sp, #120]\t@ 0x78\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tmov.w\tr9, r3, lsl #3\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tadd.w\tr3, fp, #1\n-\tstr\tr3, [sp, #84]\t@ 0x54\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmul.w\tr0, r4, r1\n+\tstr\tr0, [sp, #136]\t@ 0x88\n+\tmul.w\tr0, r1, ip\n+\tnegs\tr3, r3\n+\tstr\tr0, [sp, #188]\t@ 0xbc\n+\tvldr\td9, [pc, #620]\t@ e48 <__gridxc_fftr_MOD_fftk2r+0xe48>\n+\tmul.w\tr3, r4, r3\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tmov\tr8, r4\n+\tmls\tr3, ip, r4, r3\n+\tadd\tr3, r6\n+\tldr\tr6, [sp, #172]\t@ 0xac\n+\tmls\tr3, r6, r7, r3\n+\tmla\tr0, r1, r3, lr\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmul.w\tr1, r7, r1\n+\tldr\tr7, [sp, #208]\t@ 0xd0\n+\tstr\tr1, [sp, #64]\t@ 0x40\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tldrd\tsl, r1, [r7]\n+\tstr\tr1, [sp, #120]\t@ 0x78\n+\tmov\tr6, r1\n+\tldr\tr1, [sp, #100]\t@ 0x64\n+\tmul.w\tr0, r6, sl\n+\tldr\tr6, [r7, #8]\n+\tmul.w\tr3, r1, r3\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tmla\tr3, r4, r5, r3\n+\tstr\tr0, [sp, #180]\t@ 0xb4\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tadd\tr1, r3\n \tldr\tr3, [sp, #172]\t@ 0xac\n-\tadds\tr6, r3, #2\n-\tmov\tr7, r6\n-\tmov\tr6, r4\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tnegs\tr2, r0\n-\tcmp\tr1, #0\n-\tmul.w\tr3, r0, r3\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tsub.w\tr3, r5, r3\n-\tblt.w\td40 <__gridxc_fftr_MOD_fftk2r+0xd40>\n-\tcmp\tr2, #0\n-\tblt.w\td50 <__gridxc_fftr_MOD_fftk2r+0xd50>\n-\tsdiv\tr4, r2, r1\n-\tmls\tr2, r1, r4, r2\n-\tldr\tr4, [sp, #148]\t@ 0x94\n-\tldr.w\tfp, [sp, #132]\t@ 0x84\n-\tstrd\tr5, lr, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tmul.w\tip, r4, r2\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tstrd\tr1, r0, [sp, #188]\t@ 0xbc\n-\tadds\tr4, r2, #1\n-\tstrd\tr6, r5, [sp, #196]\t@ 0xc4\n-\tadds\tr2, r7, r2\n-\tstr\tr4, [sp, #144]\t@ 0x90\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n-\tstrd\tlr, r7, [sp, #272]\t@ 0x110\n-\tldr\tr1, [sp, #96]\t@ 0x60\n-\tmul.w\tr6, fp, r8\n-\trsb\tr2, fp, #0\n-\tcmp\tr1, #0\n-\tblt.w\td2a <__gridxc_fftr_MOD_fftk2r+0xd2a>\n-\tcmp\tr2, #0\n-\tblt.w\td3c <__gridxc_fftr_MOD_fftk2r+0xd3c>\n-\tsdiv\tr1, r2, r1\n-\tldr\tr0, [sp, #96]\t@ 0x60\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tstr.w\tfp, [sp, #100]\t@ 0x64\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tmls\tr2, r0, r1, r2\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tmul.w\tr5, r8, r2\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tadd\tr1, r2\n-\tadds\tr7, r3, r2\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tmul.w\tr1, r0, r1\n-\tmul.w\tr7, r0, r7\n-\tldr\tr0, [sp, #112]\t@ 0x70\n-\tsubs\tr7, r7, r1\n-\tadd\tr1, r2\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadd\tr2, r6\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tadd.w\tr0, r0, r4, lsl #3\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tadd.w\tlr, r4, r6\n-\tldr\tr4, [sp, #144]\t@ 0x90\n-\tadd\tr6, r4\n-\tldr\tr4, [sp, #72]\t@ 0x48\n-\tb.n\tca0 <__gridxc_fftr_MOD_fftk2r+0xca0>\n-\tcmp\tr3, #0\n-\tblt.n\tcce <__gridxc_fftr_MOD_fftk2r+0xcce>\n-\tsdiv\tfp, r3, r8\n-\tmls\tr3, r8, fp, r3\n-\tvldr\td16, [r0]\n-\tadd.w\tfp, r1, r7\n+\tldr\tr7, [sp, #160]\t@ 0xa0\n+\tmul.w\tr0, r0, r2\n+\tmov\tr9, r7\n+\tmul.w\tr2, r3, r2\n \tadds\tr3, #1\n-\tadd\tr3, r5\n-\tadd\tr3, ip\n-\tcmp\tr2, r3\n-\tbeq.n\tcba <__gridxc_fftr_MOD_fftk2r+0xcba>\n-\tblt.n\tcc4 <__gridxc_fftr_MOD_fftk2r+0xcc4>\n-\tvneg.f64\td16, d16\n-\tvldr\td18, [r4]\n-\tvstr\td18, [fp]\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n+\tmov\tr7, r1\n+\tldr\tr2, [sp, #204]\t@ 0xcc\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tadds\tr2, #1\n-\tvstr\td16, [r1]\n-\tadd\tr0, r9\n-\tadd\tr1, sl\n-\tsubs\tr4, r4, r3\n-\tcmp\tr2, lr\n-\tbeq.n\tcd4 <__gridxc_fftr_MOD_fftk2r+0xcd4>\n-\tsubs\tr3, r6, r2\n-\tcmp.w\tr8, #0\n-\tbge.n\tc62 <__gridxc_fftr_MOD_fftk2r+0xc62>\n-\tadd.w\tfp, r3, #4294967295\t@ 0xffffffff\n-\tcmp\tr3, #0\n-\tble.n\tc66 <__gridxc_fftr_MOD_fftk2r+0xc66>\n-\tsdiv\tfp, fp, r8\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n-\tb.n\tc6a <__gridxc_fftr_MOD_fftk2r+0xc6a>\n-\tvstr\td16, [fp]\n-\tvmov.f64\td16, d17\n-\tb.n\tc8e <__gridxc_fftr_MOD_fftk2r+0xc8e>\n-\tvstr\td16, [fp]\n-\tvldr\td16, [r4]\n-\tb.n\tc8e <__gridxc_fftr_MOD_fftk2r+0xc8e>\n-\tadd.w\tfp, r3, #1\n-\tb.n\tcb0 <__gridxc_fftr_MOD_fftk2r+0xcb0>\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tldr\tr0, [sp, #116]\t@ 0x74\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tldr.w\tfp, [sp, #100]\t@ 0x64\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tadd.w\tfp, fp, #1\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tsubs\tr2, r2, r0\n+\tstr\tr2, [sp, #192]\t@ 0xc0\n+\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tstr\tr0, [sp, #68]\t@ 0x44\n+\tlsls\tr2, r2, #3\n \tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tadds\tr3, #2\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #180]\t@ 0xb4\n+\trsb\tr4, r8, #0\n+\tcmp\tr6, #0\n+\tmul.w\tr3, r8, r3\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tsub.w\tr3, r7, r3\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tblt.w\te0c <__gridxc_fftr_MOD_fftk2r+0xe0c>\n+\tcmp\tr4, #0\n+\tblt.w\te22 <__gridxc_fftr_MOD_fftk2r+0xe22>\n+\tmov\tr1, r6\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr3, r0\n+\tmls\tr4, r6, r3, r4\n+\tldr\tr3, [sp, #180]\t@ 0xb4\n+\tstr.w\tr9, [sp, #84]\t@ 0x54\n+\tstrd\tr6, r5, [sp, #212]\t@ 0xd4\n+\tstrd\tr8, r9, [sp, #220]\t@ 0xdc\n+\tmul.w\tr3, r3, r4\n+\tldr\tr4, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tstrd\tr7, r3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tstr\tr7, [sp, #228]\t@ 0xe4\n+\tadds\tr2, r3, #1\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n+\tadds\tr3, r2, r3\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr1, [sp, #120]\t@ 0x78\n+\tmul.w\tr8, r4, sl\n+\tnegs\tr5, r4\n+\tcmp\tr1, #0\n+\tblt.w\tdf4 <__gridxc_fftr_MOD_fftk2r+0xdf4>\n+\tcmp\tr5, #0\n+\tblt.w\te08 <__gridxc_fftr_MOD_fftk2r+0xe08>\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #120]\t@ 0x78\n \tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r1\n-\tcmp\tfp, r2\n-\tbne.n\tc02 <__gridxc_fftr_MOD_fftk2r+0xc02>\n-\tldrd\tr6, r5, [sp, #196]\t@ 0xc4\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tldrd\tlr, r7, [sp, #272]\t@ 0x110\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr7, [sp, #92]\t@ 0x5c\n+\tmls\tr5, r3, r0, r5\n+\tstr\tr4, [sp, #128]\t@ 0x80\n+\tmul.w\tr3, sl, r5\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tadds\tr6, r2, r3\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tadd.w\tr9, r1, r3\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tmul.w\tr6, r2, r6\n+\tmul.w\tr9, r2, r9\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tsub.w\tr9, r9, r6\n \tadd\tr6, r3\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tldrd\tr1, r0, [sp, #188]\t@ 0xbc\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tadd.w\tr5, r3, r8\n+\tldr\tr3, [sp, #132]\t@ 0x84\n \tadd\tr5, r3\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tfp, r3, r2, lsl #3\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tmov\tr2, r9\n+\tmov\tr9, r7\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tmov\tr7, fp\n+\tmov\tfp, r2\n+\tadd\tr8, r3\n+\tmov\tr3, r8\n+\tmov\tr8, sl\n+\tmov\tsl, r3\n+\tb.n\td6a <__gridxc_fftr_MOD_fftk2r+0xd6a>\n+\tcmp\tr4, #0\n+\tblt.n\td9c <__gridxc_fftr_MOD_fftk2r+0xd9c>\n+\tmov\tr1, r8\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr0, r8, r0, r4\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tvldr\td7, [r7]\n+\tadd.w\tr4, r6, fp\n \tadds\tr0, #1\n-\tsub.w\tlr, lr, r3\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tcmp\tr0, r3\n-\tbne.w\tbb8 <__gridxc_fftr_MOD_fftk2r+0xbb8>\n-\tldr.w\tfp, [sp, #168]\t@ 0xa8\n-\tb.w\t4cc <__gridxc_fftr_MOD_fftk2r+0x4cc>\n-\tcmp\tr2, #0\n-\tble.w\tc18 <__gridxc_fftr_MOD_fftk2r+0xc18>\n-\tsubs\tr1, r2, #1\n-\tldr\tr0, [sp, #96]\t@ 0x60\n-\tsdiv\tr1, r1, r0\n-\tsubs\tr1, #1\n-\tb.n\tc1c <__gridxc_fftr_MOD_fftk2r+0xc1c>\n-\tadds\tr1, r2, #1\n-\tb.n\td32 <__gridxc_fftr_MOD_fftk2r+0xd32>\n-\tsubs\tr4, r2, #1\n-\tcmp\tr2, #0\n-\tble.w\tbd4 <__gridxc_fftr_MOD_fftk2r+0xbd4>\n-\tsdiv\tr4, r4, r1\n-\tsubs\tr4, #1\n-\tb.n\tbd8 <__gridxc_fftr_MOD_fftk2r+0xbd8>\n-\tadds\tr4, r2, #1\n-\tb.n\td48 <__gridxc_fftr_MOD_fftk2r+0xd48>\n-\tldr\tr0, [pc, #24]\t@ (d70 <__gridxc_fftr_MOD_fftk2r+0xd70>)\n+\tadd\tr0, r3\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tr0, r3\n+\tcmp\tr5, r0\n+\tbeq.n\td88 <__gridxc_fftr_MOD_fftk2r+0xd88>\n+\tblt.n\td92 <__gridxc_fftr_MOD_fftk2r+0xd92>\n+\tvneg.f64\td7, d7\n+\tvldr\td6, [r9]\n+\tvstr\td6, [r4]\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tadds\tr5, #1\n+\tvstr\td7, [r6]\n+\tadd\tr7, r3\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tsub.w\tr9, r9, r3\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr5, r3\n+\tbeq.n\tda0 <__gridxc_fftr_MOD_fftk2r+0xda0>\n+\tsub.w\tr4, sl, r5\n+\tcmp.w\tr8, #0\n+\tbge.n\td1c <__gridxc_fftr_MOD_fftk2r+0xd1c>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.n\td20 <__gridxc_fftr_MOD_fftk2r+0xd20>\n+\tmov\tr1, r8\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\td28 <__gridxc_fftr_MOD_fftk2r+0xd28>\n+\tvstr\td7, [r4]\n+\tvmov.f64\td7, d9\n+\tb.n\td50 <__gridxc_fftr_MOD_fftk2r+0xd50>\n+\tvstr\td7, [r4]\n+\tvldr\td7, [r9]\n+\tb.n\td50 <__gridxc_fftr_MOD_fftk2r+0xd50>\n+\tadds\tr0, r4, #1\n+\tb.n\td7e <__gridxc_fftr_MOD_fftk2r+0xd7e>\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tmov\tsl, r8\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #136]\t@ 0x88\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #128]\t@ 0x80\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tadds\tr4, #1\n+\tsubs\tr3, r3, r1\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tr4, r3\n+\tbne.w\tca8 <__gridxc_fftr_MOD_fftk2r+0xca8>\n+\tldrd\tr8, r9, [sp, #220]\t@ 0xdc\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #188]\t@ 0xbc\n+\tadd.w\tr8, r8, #1\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tldrd\tr6, r5, [sp, #212]\t@ 0xd4\n+\tsubs\tr3, r3, r2\n+\tldr\tr7, [sp, #228]\t@ 0xe4\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tadd\tr7, r5\n+\tcmp\tr8, r3\n+\tbne.w\tc50 <__gridxc_fftr_MOD_fftk2r+0xc50>\n+\tb.w\t534 <__gridxc_fftr_MOD_fftk2r+0x534>\n+\tcmp\tr5, #0\n+\tit\tgt\n+\taddgt.w\tr0, r5, #4294967295\t@ 0xffffffff\n+\tble.w\tcbc <__gridxc_fftr_MOD_fftk2r+0xcbc>\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\tcc2 <__gridxc_fftr_MOD_fftk2r+0xcc2>\n+\tadds\tr0, r5, #1\n+\tb.n\te00 <__gridxc_fftr_MOD_fftk2r+0xe00>\n+\tcmp\tr4, #0\n+\tit\tgt\n+\taddgt.w\tr0, r4, #4294967295\t@ 0xffffffff\n+\tble.w\tc70 <__gridxc_fftr_MOD_fftk2r+0xc70>\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, #1\n+\tb.n\tc7a <__gridxc_fftr_MOD_fftk2r+0xc7a>\n+\tadds\tr0, r4, #1\n+\tb.n\te18 <__gridxc_fftr_MOD_fftk2r+0xe18>\n+\tldr\tr0, [pc, #40]\t@ (e50 <__gridxc_fftr_MOD_fftk2r+0xe50>)\n \tmovs\tr2, #0\n-\tldr\tr1, [pc, #24]\t@ (d74 <__gridxc_fftr_MOD_fftk2r+0xd74>)\n+\tldr\tr1, [pc, #40]\t@ (e54 <__gridxc_fftr_MOD_fftk2r+0xe54>)\n \tmovs\tr3, #10\n \tadd\tr0, pc\n \tstr\tr2, [sp, #0]\n \tadd\tr1, pc\n \tadds\tr0, #72\t@ 0x48\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tb.n\t5de <__gridxc_fftr_MOD_fftk2r+0x5de>\n+\tb.w\t63a <__gridxc_fftr_MOD_fftk2r+0x63a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x00000010\n+\tnop.w\n+\t...\n+\t.word\t0x0000001e\n R_ARM_REL32\t.bss\n-\t.word\t0x00000010\n+\t.word\t0x0000001e\n R_ARM_REL32\t.LC4\n \n-00000d78 <__gridxc_fftr_MOD_fftr2k>:\n+00000e58 <__gridxc_fftr_MOD_fftr2k>:\n __gridxc_fftr_MOD_fftr2k():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3568]\t@ 0xdf0\n-\tsub\tsp, #476\t@ 0x1dc\n-\tmov\tr4, r2\n-\tldr.w\tr2, [pc, #2052]\t@ 1598 <__gridxc_fftr_MOD_fftr2k+0x820>\n-\tmov\tr7, r0\n-\tldr.w\tr3, [pc, #2052]\t@ 159c <__gridxc_fftr_MOD_fftr2k+0x824>\n-\tmov\tsl, r1\n+\tstr.w\tr0, [ip, #3560]\t@ 0xde8\n+\tsub\tsp, #500\t@ 0x1f4\n+\tmov\tr5, r2\n+\tldr.w\tr2, [pc, #1472]\t@ 1430 <__gridxc_fftr_MOD_fftr2k+0x5d8>\n+\tmov\tr6, r0\n+\tldr.w\tr3, [pc, #1472]\t@ 1434 <__gridxc_fftr_MOD_fftr2k+0x5dc>\n+\tmov\tr9, r1\n \tadd\tr2, pc\n-\tstr\tr0, [sp, #144]\t@ 0x90\n-\tstr\tr1, [sp, #208]\t@ 0xd0\n-\tldr.w\tr8, [pc, #2044]\t@ 15a0 <__gridxc_fftr_MOD_fftr2k+0x828>\n+\tstr\tr0, [sp, #172]\t@ 0xac\n+\tstr\tr1, [sp, #224]\t@ 0xe0\n+\tldr.w\tr8, [pc, #1464]\t@ 1438 <__gridxc_fftr_MOD_fftr2k+0x5e0>\n \tldr\tr3, [r2, r3]\n-\tadd\tr2, sp, #272\t@ 0x110\n+\tadd\tr2, sp, #324\t@ 0x144\n \tadd\tr8, pc\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #468]\t@ 0x1d4\n+\tstr\tr3, [sp, #492]\t@ 0x1ec\n \tmov.w\tr3, #0\n-\tldr\tr3, [r4, #24]\n+\tldr\tr3, [r5, #24]\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr3, #1\n-\tstr\tr3, [sp, #132]\t@ 0x84\n-\tldrd\tr3, r5, [r4, #64]\t@ 0x40\n-\tsubs\tr5, r5, r3\n-\tldrd\tr3, r6, [r4, #28]\n-\tsub.w\tr9, r6, r3\n-\tldrd\tr3, r6, [r4, #40]\t@ 0x28\n-\tsub.w\tfp, r6, r3\n-\tldrd\tr3, r6, [r4, #52]\t@ 0x34\n-\tsubs\tr3, r6, r3\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tldrd\tr3, r4, [r5, #64]\t@ 0x40\n+\tsub.w\tsl, r4, r3\n+\tldrd\tr3, r4, [r5, #28]\n+\tadd.w\tfp, sl, #1\n+\tsubs\tr7, r4, r3\n+\tldrd\tr3, r4, [r5, #40]\t@ 0x28\n+\tsubs\tr3, r4, r3\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldrd\tr3, r4, [r5, #52]\t@ 0x34\n+\tsubs\tr3, r4, r3\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [r5, #0]\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [r5, #36]\t@ 0x24\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [r5, #48]\t@ 0x30\n \tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr3, [r4, #0]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [r4, #36]\t@ 0x24\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr3, [r4, #48]\t@ 0x30\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [r4, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tadds\tr3, r5, #1\n-\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [r5, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #180]\t@ 0xb4\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tvldr\td17, [sp, #272]\t@ 0x110\n-\tvmov.i32\td18, #1\t@ 0x00000001\n-\tvldr\td16, [sp, #280]\t@ 0x118\n-\tmov\tr0, r7\n-\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n-\tvtrn.32\td17, d16\n+\tldrd\tr2, r3, [sp, #324]\t@ 0x144\n+\tmov\tr0, r6\n+\tldr.w\tr1, [pc, #1380]\t@ 143c <__gridxc_fftr_MOD_fftr2k+0x5e4>\n+\tsubs\tr3, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #288]\t@ 0x120\n+\tldrd\tr2, r3, [sp, #332]\t@ 0x14c\n+\tadd\tr1, pc\n+\tmov\tr4, r1\n+\tsubs\tr3, r3, r2\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #292]\t@ 0x124\n+\tldrd\tr2, r3, [sp, #340]\t@ 0x154\n \tsubs\tr3, r3, r2\n \tmovs\tr2, #0\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #256]\t@ 0x100\n-\tldr.w\tr3, [pc, #1936]\t@ 15a4 <__gridxc_fftr_MOD_fftr2k+0x82c>\n-\tvsub.i32\td16, d16, d17\n-\tadd\tr3, pc\n-\tmov\tr1, r3\n-\tmov\tr4, r3\n-\tvadd.i32\td16, d16, d18\n-\tvstr\td16, [sp, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #296]\t@ 0x128\n \tbl\t0 <__gridxc_mesh3d_MOD_fftmeshdistr>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_fftmeshdistr\n-\tadd\tr3, sp, #296\t@ 0x128\n-\tmov\tr1, r4\n+\tadd\tr3, sp, #300\t@ 0x12c\n \tmov\tr2, r3\n-\tmov\tr0, r7\n+\tmov\tr1, r4\n+\tmov\tr0, r6\n \tstr\tr3, [sp, #176]\t@ 0xb0\n \tbl\t0 <__gridxc_mesh3d_MOD_mymeshbox>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_mymeshbox\n-\tldr\tr2, [sp, #296]\t@ 0x128\n-\tldr\tr3, [sp, #300]\t@ 0x12c\n-\tldr\tr0, [sp, #308]\t@ 0x134\n-\tldr\tr6, [sp, #304]\t@ 0x130\n-\tldr\tr7, [sp, #316]\t@ 0x13c\n-\tldr\tr1, [sp, #312]\t@ 0x138\n-\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n+\tldr\tr3, [sp, #304]\t@ 0x130\n+\tldr\tr0, [sp, #312]\t@ 0x138\n+\tldr\tr5, [sp, #308]\t@ 0x134\n+\tldr\tr6, [sp, #320]\t@ 0x140\n+\tldr\tr1, [sp, #316]\t@ 0x13c\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #260]\t@ 0x104\n-\tsubs\tr3, r0, r6\n-\tstr\tr2, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #276]\t@ 0x114\n+\tsubs\tr3, r0, r5\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n \tadds\tr3, #1\n \tmov\tr2, r4\n-\tstr\tr0, [sp, #156]\t@ 0x9c\n+\tstr\tr0, [sp, #188]\t@ 0xbc\n \tadd.w\tr0, r4, #12\n-\tstr\tr1, [sp, #140]\t@ 0x8c\n-\tstr\tr3, [sp, #264]\t@ 0x108\n-\tsubs\tr3, r7, r1\n-\tmov\tr1, sl\n+\tstr\tr1, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tsubs\tr3, r6, r1\n+\tmov\tr1, r9\n \tadds\tr3, #1\n-\tstr\tr6, [sp, #108]\t@ 0x6c\n-\tadd\tr6, sp, #260\t@ 0x104\n-\tstr\tr7, [sp, #160]\t@ 0xa0\n-\tmov\tsl, r6\n-\tstr\tr3, [sp, #268]\t@ 0x10c\n+\tstr\tr5, [sp, #136]\t@ 0x88\n+\tadd.w\tr9, sp, #276\t@ 0x114\n+\tstr\tr6, [sp, #192]\t@ 0xc0\n+\tadd\tr5, sp, #288\t@ 0x120\n+\tstr\tr3, [sp, #284]\t@ 0x11c\n \tbl\t0 <__gridxc_mesh3d_MOD_associatemeshtask>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_associatemeshtask\n-\tldr.w\tr0, [pc, #1840]\t@ 15a8 <__gridxc_fftr_MOD_fftr2k+0x830>\n-\tadd\tr3, sp, #396\t@ 0x18c\n-\tadd\tr2, sp, #248\t@ 0xf8\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tadd\tr0, pc\n+\tldr.w\tr0, [pc, #1268]\t@ 1440 <__gridxc_fftr_MOD_fftr2k+0x5e8>\n+\tadd\tr3, sp, #420\t@ 0x1a4\n \tmov\tr4, r3\n-\tmovs\tr7, #0\n-\tmov\tr5, r2\n-\tstr\tr3, [sp, #220]\t@ 0xdc\n-\tldr\tr3, [sp, #112]\t@ 0x70\n+\tmovs\tr6, #0\n+\tadd\tr0, pc\n+\tstr\tr3, [sp, #244]\t@ 0xf4\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr3, [sp, #464]\t@ 0x1d0\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tldr.w\tr1, [r5], #4\n-\tstr\tr3, [sp, #452]\t@ 0x1c4\n-\tldr.w\tr3, [r6], #4\n-\tstrd\tr7, r9, [sp, #424]\t@ 0x1a8\n-\tstrd\tr7, fp, [sp, #436]\t@ 0x1b4\n+\tstr\tr3, [sp, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r9], #4\n+\tstrd\tr6, r7, [sp, #448]\t@ 0x1c0\n+\tstr\tr6, [sp, #460]\t@ 0x1cc\n \tcmp\tr1, r3\n-\tstr\tr7, [sp, #448]\t@ 0x1c0\n+\tstr\tr6, [sp, #472]\t@ 0x1d8\n \tit\tlt\n \tmovlt\tr1, r3\n \tldrd\tr2, r3, [r4, #28]\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r1\n-\tbge.w\t139e <__gridxc_fftr_MOD_fftr2k+0x626>\n-\tldr.w\tr3, [pc, #1780]\t@ 15ac <__gridxc_fftr_MOD_fftr2k+0x834>\n+\tbge.w\t14ec <__gridxc_fftr_MOD_fftr2k+0x694>\n+\tldr.w\tr3, [pc, #1212]\t@ 1444 <__gridxc_fftr_MOD_fftr2k+0x5ec>\n \tmovs\tr1, #45\t@ 0x2d\n \tadds\tr4, #12\n \tldr.w\tr3, [r8, r3]\n-\tstr\tr0, [sp, #56]\t@ 0x38\n+\tstr\tr0, [sp, #52]\t@ 0x34\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tcmp\tr5, sl\n-\tbne.n\te88 <__gridxc_fftr_MOD_fftr2k+0x110>\n-\tldr.w\tr3, [pc, #1760]\t@ 15b0 <__gridxc_fftr_MOD_fftr2k+0x838>\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tldr\tr0, [sp, #52]\t@ 0x34\n+\tcmp\tr5, r3\n+\tbne.n\tf56 <__gridxc_fftr_MOD_fftr2k+0xfe>\n+\tldr.w\tr3, [pc, #1188]\t@ 1448 <__gridxc_fftr_MOD_fftr2k+0x5f0>\n \tmovs\tr4, #0\n-\tldr.w\tr0, [pc, #1756]\t@ 15b4 <__gridxc_fftr_MOD_fftr2k+0x83c>\n-\tadd\tr2, sp, #300\t@ 0x12c\n+\tldr.w\tr0, [pc, #1188]\t@ 144c <__gridxc_fftr_MOD_fftr2k+0x5f4>\n+\tadd\tr2, sp, #304\t@ 0x130\n \tadd\tr3, pc\n \tstr\tr3, [sp, #16]\n \tadds\tr3, #4\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [pc, #1748]\t@ 15b8 <__gridxc_fftr_MOD_fftr2k+0x840>\n+\tldr.w\tr3, [pc, #1176]\t@ 1450 <__gridxc_fftr_MOD_fftr2k+0x5f8>\n \tadd\tr0, pc\n \tldr\tr1, [sp, #176]\t@ 0xb0\n+\tmov\tr5, r0\n \tadd\tr3, pc\n-\tstr\tr0, [sp, #164]\t@ 0xa4\n-\tstr\tr3, [sp, #20]\n \tadds\tr0, #144\t@ 0x90\n+\tstr\tr3, [sp, #20]\n \tmovs\tr3, #9\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #316\t@ 0x13c\n+\tadd\tr3, sp, #320\t@ 0x140\n \tstrd\tr4, r4, [sp, #28]\n \tstr\tr3, [sp, #8]\n-\tadd\tr3, sp, #312\t@ 0x138\n+\tadd\tr3, sp, #316\t@ 0x13c\n \tstr\tr4, [sp, #24]\n \tstr\tr3, [sp, #4]\n-\tadd\tr3, sp, #308\t@ 0x134\n+\tadd\tr3, sp, #312\t@ 0x138\n \tstr\tr3, [sp, #0]\n-\tadd\tr3, sp, #304\t@ 0x130\n-\tldr\tr5, [sp, #48]\t@ 0x30\n+\tadd\tr3, sp, #308\t@ 0x134\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tcmp\tr5, r4\n-\tbic.w\tr3, r3, r3, asr #31\n-\tstr\tr3, [sp, #180]\t@ 0xb4\n-\tblt.w\t130a <__gridxc_fftr_MOD_fftr2k+0x592>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tvmov.i64\td8, #0x0000000000000000\n-\tldr\tr0, [sp, #104]\t@ 0x68\n+\tbic.w\tr3, fp, fp, asr #31\n+\tcmp\tsl, r4\n+\tstr\tr3, [sp, #200]\t@ 0xc8\n+\tblt.w\t13f6 <__gridxc_fftr_MOD_fftr2k+0x59e>\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n+\tmov\tsl, r5\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tldr\tr0, [sp, #112]\t@ 0x70\n \tnegs\tr3, r2\n \tsubs\tr3, r3, r1\n-\tlsls\tr2, r2, #3\n+\tstr\tr4, [sp, #148]\t@ 0x94\n \tsubs\tr3, r3, r0\n-\tldr\tr0, [sp, #148]\t@ 0x94\n-\tstr\tr2, [sp, #172]\t@ 0xac\n-\tlsls\tr2, r1, #3\n+\tldr\tr0, [sp, #180]\t@ 0xb4\n+\tlsls\tr2, r2, #3\n+\tstr\tr7, [sp, #260]\t@ 0x104\n \tsubs\tr3, r3, r0\n-\tstr\tr3, [sp, #204]\t@ 0xcc\n-\tldr.w\tr3, [pc, #1656]\t@ 15bc <__gridxc_fftr_MOD_fftr2k+0x844>\n-\tadd.w\tr0, fp, #1\n-\tstr\tr0, [sp, #196]\t@ 0xc4\n+\tstr\tr3, [sp, #220]\t@ 0xdc\n+\tldr.w\tr3, [pc, #1096]\t@ 1454 <__gridxc_fftr_MOD_fftr2k+0x5fc>\n+\tldr\tr0, [sp, #160]\t@ 0xa0\n \tadd\tr3, pc\n-\tldr\tr0, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #84]\t@ 0x54\n \tadds\tr3, #12\n-\tstr\tr3, [sp, #216]\t@ 0xd8\n-\tadd.w\tr3, r9, #1\n-\tstr\tr3, [sp, #192]\t@ 0xc0\n-\tadds\tr0, #1\n-\tstr\tr4, [sp, #124]\t@ 0x7c\n-\tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #184]\t@ 0xb8\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #168]\t@ 0xa8\n-\tadd\tr3, sp, #408\t@ 0x198\n-\tstr\tr3, [sp, #224]\t@ 0xe0\n-\tadd\tr3, sp, #332\t@ 0x14c\n-\tstr\tr3, [sp, #232]\t@ 0xe8\n-\tadd\tr3, sp, #340\t@ 0x154\n-\tstr\tr3, [sp, #236]\t@ 0xec\n-\tadd\tr3, sp, #320\t@ 0x140\n \tstr\tr3, [sp, #228]\t@ 0xe4\n-\torr.w\tr3, r9, fp\n-\tstr\tr3, [sp, #240]\t@ 0xf0\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tstr\tr0, [sp, #200]\t@ 0xc8\n-\tadds\tr3, #164\t@ 0xa4\n-\tstr\tr2, [sp, #188]\t@ 0xbc\n-\tstr\tr3, [sp, #212]\t@ 0xd4\n-\tstr.w\tr9, [sp, #244]\t@ 0xf4\n-\tstr.w\tfp, [sp, #128]\t@ 0x80\n+\tldr.w\tr3, [pc, #1088]\t@ 1458 <__gridxc_fftr_MOD_fftr2k+0x600>\n+\tadds\tr4, r0, #1\n+\tstr\tr4, [sp, #212]\t@ 0xd4\n+\tlsls\tr2, r1, #3\n+\tadd\tr3, pc\n+\tldr\tr4, [sp, #152]\t@ 0x98\n+\tadds\tr3, #4\n+\tstr\tr3, [sp, #252]\t@ 0xfc\n+\tldr.w\tr3, [pc, #1072]\t@ 145c <__gridxc_fftr_MOD_fftr2k+0x604>\n+\tadds\tr4, #1\n+\tstr\tr2, [sp, #204]\t@ 0xcc\n+\tmovs\tr2, #1\n+\tadd\tr3, pc\n+\tstr\tr2, [sp, #196]\t@ 0xc4\n+\tadds\tr3, #144\t@ 0x90\n+\tstr\tr3, [sp, #256]\t@ 0x100\n+\tadds\tr3, r7, #1\n+\tstr\tr3, [sp, #208]\t@ 0xd0\n+\tadd\tr2, sp, #360\t@ 0x168\n+\tstr\tr2, [sp, #240]\t@ 0xf0\n+\tlsls\tr3, r3, #3\n+\tadd\tr2, sp, #432\t@ 0x1b0\n+\tstr\tr2, [sp, #248]\t@ 0xf8\n+\tadd\tr2, sp, #348\t@ 0x15c\n+\tstr\tr2, [sp, #236]\t@ 0xec\n+\torr.w\tr2, r7, r0\n+\tmov\tr7, r3\n+\tstr\tr4, [sp, #216]\t@ 0xd8\n+\tstr\tr2, [sp, #232]\t@ 0xe8\n+\tldr\tr3, [sp, #208]\t@ 0xd0\n+\tmovs\tr2, #1\n+\tstr\tr3, [sp, #380]\t@ 0x17c\n+\tmovs\tr5, #0\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tstr\tr3, [sp, #372]\t@ 0x174\n \tldr\tr3, [sp, #212]\t@ 0xd4\n-\tldr\tr7, [sp, #164]\t@ 0xa4\n-\tvld1.32\t{d16}, [r3]\n-\tldr\tr3, [sp, #224]\t@ 0xe0\n-\tldr.w\tr2, [r7, #176]\t@ 0xb0\n-\tvstr\td9, [r3]\n-\tldr\tr3, [sp, #232]\t@ 0xe8\n-\tvstr\td9, [r3]\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n-\tstr\tr3, [sp, #428]\t@ 0x1ac\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tstr\tr3, [sp, #420]\t@ 0x1a4\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n-\tstr\tr3, [sp, #440]\t@ 0x1b8\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tstr\tr3, [sp, #432]\t@ 0x1b0\n-\tldr\tr3, [sp, #200]\t@ 0xc8\n-\tstr\tr3, [sp, #452]\t@ 0x1c4\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tstr\tr3, [sp, #444]\t@ 0x1bc\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tstr\tr3, [sp, #456]\t@ 0x1c8\n-\tldr\tr3, [sp, #204]\t@ 0xcc\n-\tstr\tr3, [sp, #400]\t@ 0x190\n-\tldr\tr3, [sp, #236]\t@ 0xec\n-\tvst1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r7, #172]\t@ 0xac\n-\trsb\tr3, r3, #1\n-\tadd\tr3, r2\n-\tmovs\tr2, #8\n+\tstr\tr3, [sp, #392]\t@ 0x188\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tstr\tr3, [sp, #384]\t@ 0x180\n+\tldr\tr3, [sp, #216]\t@ 0xd8\n+\tstr\tr3, [sp, #404]\t@ 0x194\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #396]\t@ 0x18c\n+\tldr\tr3, [sp, #180]\t@ 0xb4\n+\tstr\tr3, [sp, #408]\t@ 0x198\n+\tldr\tr3, [sp, #220]\t@ 0xdc\n \tstr\tr3, [sp, #352]\t@ 0x160\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #424]\t@ 0x1a8\n-\tstr\tr3, [sp, #436]\t@ 0x1b4\n-\tstr\tr3, [sp, #448]\t@ 0x1c0\n-\tstrd\tr3, r3, [sp, #460]\t@ 0x1cc\n-\tstr\tr2, [sp, #416]\t@ 0x1a0\n-\tstr\tr2, [sp, #404]\t@ 0x194\n-\tstr\tr2, [sp, #328]\t@ 0x148\n-\tldr.w\tr2, [r7, #184]\t@ 0xb8\n-\tldr.w\tr1, [r7, #188]\t@ 0xbc\n-\tsubs\tr2, r3, r2\n-\tldr.w\tr6, [r7, #200]\t@ 0xc8\n-\tadds\tr0, r2, r1\n-\tldr.w\tr2, [r7, #196]\t@ 0xc4\n-\tldr.w\tr5, [r7, #180]\t@ 0xb4\n-\tsubs\tr2, r3, r2\n-\tstrd\tr3, r0, [sp, #360]\t@ 0x168\n-\tadds\tr1, r2, r6\n-\tstr\tr1, [sp, #376]\t@ 0x178\n-\tldr\tr1, [sp, #216]\t@ 0xd8\n-\tmov.w\tr2, #772\t@ 0x304\n-\tstr\tr1, [sp, #4]\n+\tldr.w\tr3, [sl, #164]\t@ 0xa4\n+\tldr\tr1, [sp, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #440]\t@ 0x1b8\n+\tldr\tr3, [sp, #240]\t@ 0xf0\n+\tstr\tr2, [sp, #376]\t@ 0x178\n+\tstr\tr2, [sp, #388]\t@ 0x184\n+\tstr\tr5, [r3, #4]\n+\tstr\tr2, [sp, #400]\t@ 0x190\n+\tstrd\tr2, r2, [sp, #412]\t@ 0x19c\n+\tstr\tr5, [r1, #4]\n+\tstr\tr5, [r3, #0]\n+\tstr\tr5, [r1, #0]\n+\tmovs\tr1, #8\n+\tldr.w\tr3, [sl, #168]\t@ 0xa8\n+\tstr\tr1, [sp, #368]\t@ 0x170\n+\tstr\tr1, [sp, #356]\t@ 0x164\n+\tstr\tr1, [sp, #428]\t@ 0x1ac\n+\tldr.w\tr1, [sl, #172]\t@ 0xac\n+\tldr.w\tr0, [sl, #176]\t@ 0xb0\n+\tsubs\tr1, r2, r1\n+\tldr.w\tr4, [sl, #188]\t@ 0xbc\n+\tadds\tr6, r1, r0\n+\tldr.w\tr1, [sl, #184]\t@ 0xb8\n+\tstrd\tr2, r6, [sp, #448]\t@ 0x1c0\n+\tsubs\tr1, r2, r1\n+\tstr\tr2, [sp, #460]\t@ 0x1cc\n+\tadds\tr0, r1, r4\n+\tldr.w\tr1, [sl, #196]\t@ 0xc4\n+\tldr.w\tr4, [sl, #200]\t@ 0xc8\n+\tsubs\tr1, r2, r1\n+\tstr\tr0, [sp, #464]\t@ 0x1d0\n+\tadd.w\tip, r1, r4\n+\tldr\tr1, [sp, #148]\t@ 0x94\n+\tmov.w\tr4, #772\t@ 0x304\n+\tstrh.w\tr4, [sp, #364]\t@ 0x16c\n+\tstrh.w\tr4, [sp, #436]\t@ 0x1b4\n+\tldr\tr4, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #472]\t@ 0x1d8\n+\tstrd\tr2, r2, [sp, #484]\t@ 0x1e4\n+\tadd.w\tr4, r4, r1, lsl #3\n \tldr\tr1, [sp, #228]\t@ 0xe4\n+\tstr\tr1, [sp, #4]\n+\tldr\tr1, [sp, #244]\t@ 0xf4\n \tstr\tr1, [sp, #0]\n-\tstr\tr3, [sp, #348]\t@ 0x15c\n-\tstrh.w\tr2, [sp, #412]\t@ 0x19c\n-\tstrh.w\tr2, [sp, #336]\t@ 0x150\n-\tvmov.32\tr2, d16[1]\n-\tstr\tr3, [sp, #372]\t@ 0x174\n-\tstrd\tr3, r3, [sp, #384]\t@ 0x180\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tldr.w\tr1, [r7, #204]\t@ 0xcc\n-\trsb\tr3, r3, #1\n-\tnegs\tr2, r2\n-\tsubs\tr2, r2, r5\n-\tldr\tr6, [sp, #60]\t@ 0x3c\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tmul.w\tr0, r1, r3\n-\tldr.w\tr3, [r7, #192]\t@ 0xc0\n-\tstr\tr3, [sp, #368]\t@ 0x170\n-\tsubs\tr3, r2, r3\n-\tadd.w\tr6, r6, r4, lsl #3\n+\tstr\tr3, [sp, #444]\t@ 0x1bc\n+\tnegs\tr3, r3\n+\tldr.w\tr0, [sl, #180]\t@ 0xb4\n+\tldr.w\tr2, [sl, #208]\t@ 0xd0\n+\tldr.w\tr1, [sl, #204]\t@ 0xcc\n+\tsubs\tr3, r3, r0\n+\tstr\tr0, [sp, #456]\t@ 0x1c8\n+\trsb\tr2, r2, #1\n+\tldr.w\tr0, [sl, #192]\t@ 0xc0\n+\tstr.w\tip, [sp, #476]\t@ 0x1dc\n+\tsubs\tr3, r3, r0\n+\tmul.w\tr2, r1, r2\n \tsubs\tr3, r3, r1\n-\tstr\tr3, [sp, #324]\t@ 0x144\n-\tldr.w\tr3, [r7, #144]\t@ 0x90\n-\tstr\tr6, [sp, #396]\t@ 0x18c\n-\tstr\tr5, [sp, #356]\t@ 0x164\n-\tadd.w\tr3, r3, r0, lsl #3\n-\tstr\tr1, [sp, #380]\t@ 0x17c\n-\tstr\tr3, [sp, #320]\t@ 0x140\n+\tstr\tr1, [sp, #480]\t@ 0x1e0\n+\tstr\tr0, [sp, #468]\t@ 0x1d4\n+\tstr\tr4, [sp, #348]\t@ 0x15c\n+\tstr\tr3, [sp, #424]\t@ 0x1a8\n+\tldr.w\tr3, [sl, #144]\t@ 0x90\n+\tldr\tr1, [sp, #224]\t@ 0xe0\n+\tldr\tr0, [sp, #172]\t@ 0xac\n+\tadd.w\tr3, r3, r2, lsl #3\n+\tldr\tr2, [sp, #236]\t@ 0xec\n+\tstr\tr3, [sp, #420]\t@ 0x1a4\n \tldr\tr3, [sp, #176]\t@ 0xb0\n-\tldr\tr2, [sp, #220]\t@ 0xdc\n-\tldr\tr1, [sp, #208]\t@ 0xd0\n-\tldr\tr0, [sp, #144]\t@ 0x90\n \tbl\t0 <__gridxc_mesh3d_MOD_copymeshdata>\n R_ARM_THM_CALL\t__gridxc_mesh3d_MOD_copymeshdata\n-\tmov\tr2, r7\n-\tldr.w\tr5, [r7, #196]\t@ 0xc4\n-\tldr.w\tr3, [r7, #200]\t@ 0xc8\n-\tldr.w\tr6, [r2, #188]\t@ 0xbc\n-\tldr.w\tr7, [r7, #184]\t@ 0xb8\n-\tcmp\tr5, r3\n-\tbgt.n\t1114 <__gridxc_fftr_MOD_fftr2k+0x39c>\n-\tcmp\tr7, r6\n-\tbgt.n\t1114 <__gridxc_fftr_MOD_fftr2k+0x39c>\n-\tldr\tr0, [sp, #164]\t@ 0xa4\n-\tldrd\tr2, r1, [r0, #172]\t@ 0xac\n-\tcmp\tr2, r1\n-\tbgt.n\t1114 <__gridxc_fftr_MOD_fftr2k+0x39c>\n+\tldrd\tip, r6, [sl, #196]\t@ 0xc4\n+\tldrd\tlr, r3, [sl, #184]\t@ 0xb8\n+\tcmp\tip, r6\n+\tbgt.n\t11ca <__gridxc_fftr_MOD_fftr2k+0x372>\n+\tcmp\tlr, r3\n+\tbgt.n\t11ca <__gridxc_fftr_MOD_fftr2k+0x372>\n+\tldrd\tr4, r1, [sl, #172]\t@ 0xac\n+\tcmp\tr4, r1\n+\tbgt.n\t11ca <__gridxc_fftr_MOD_fftr2k+0x372>\n \tadds\tr3, #1\n-\tadds\tr1, #1\n-\tsub.w\tlr, r3, r5\n-\tmov\tr3, r0\n-\tmov\tr4, r3\n-\tldr.w\tr0, [r0, #204]\t@ 0xcc\n-\tsubs\tr1, r1, r2\n+\tldr.w\tr0, [sl, #204]\t@ 0xcc\n+\tmov\tr2, r5\n+\tsub.w\tr5, r3, lr\n+\tldr.w\tr3, [sl, #148]\t@ 0x94\n \tadds\tr6, #1\n-\tldr.w\tr3, [r3, #148]\t@ 0x94\n-\tsubs\tr6, r6, r7\n-\tldr.w\tr9, [r4, #192]\t@ 0xc0\n-\tmov.w\tip, #0\n-\tldr.w\tsl, [r4, #180]\t@ 0xb4\n+\tsub.w\tr6, r6, ip\n+\tldr.w\tr8, [sl, #168]\t@ 0xa8\n+\tadds\tr1, #1\n+\tvldr\td7, [pc, #696]\t@ 1428 <__gridxc_fftr_MOD_fftr2k+0x5d0>\n \tadd.w\tr3, r3, r0, lsl #1\n-\tldr.w\tfp, [r4, #168]\t@ 0xa8\n-\tmla\tr3, r5, r9, r3\n-\tldr.w\tr5, [r4, #164]\t@ 0xa4\n-\tmla\tr3, r7, sl, r3\n-\tmla\tr2, fp, r2, r3\n-\tldr.w\tr3, [r4, #144]\t@ 0x90\n-\tldr\tr4, [sp, #128]\t@ 0x80\n-\tmul.w\tr8, r5, r9\n-\tmul.w\tr7, r5, sl\n-\tmul.w\tr0, fp, r5\n-\tmla\tr2, r5, r2, r3\n-\tmov\tsl, r2\n-\tmov.w\tr9, #0\n-\tmov\tr5, sl\n+\tldr.w\tr0, [sl, #192]\t@ 0xc0\n+\tsubs\tr1, r1, r4\n+\tmla\tr3, ip, r0, r3\n+\tldr.w\tip, [sl, #180]\t@ 0xb4\n+\tmla\tr3, lr, ip, r3\n+\tmla\tlr, r8, r4, r3\n+\tldr.w\tr4, [sl, #164]\t@ 0xa4\n+\tldr.w\tr3, [sl, #144]\t@ 0x90\n+\tmul.w\tr9, r4, r0\n+\tmul.w\tip, r4, ip\n+\tmul.w\tr0, r8, r4\n+\tmla\tlr, r4, lr, r3\n+\tmov\tfp, lr\n+\tmov.w\tr8, #0\n+\tmov\tr4, fp\n \tmovs\tr3, #0\n \tadds\tr3, #1\n-\tvstr\td8, [r5]\n+\tvstr\td7, [r4]\n \tcmp\tr3, r1\n-\tadd\tr5, r0\n-\tbne.n\t10f2 <__gridxc_fftr_MOD_fftr2k+0x37a>\n-\tadd.w\tr9, r9, #1\n-\tadd\tsl, r7\n-\tcmp\tr9, r6\n-\tbne.n\t10ee <__gridxc_fftr_MOD_fftr2k+0x376>\n-\tadd.w\tip, ip, #1\n-\tadd\tr2, r8\n-\tcmp\tip, lr\n-\tbne.n\t10e8 <__gridxc_fftr_MOD_fftr2k+0x370>\n-\tstr\tr4, [sp, #128]\t@ 0x80\n-\tldr.w\tr3, [pc, #1192]\t@ 15c0 <__gridxc_fftr_MOD_fftr2k+0x848>\n-\tldr.w\tr0, [pc, #1192]\t@ 15c4 <__gridxc_fftr_MOD_fftr2k+0x84c>\n-\tldr.w\tr1, [pc, #1192]\t@ 15c8 <__gridxc_fftr_MOD_fftr2k+0x850>\n-\tadd\tr3, pc\n-\tadd\tr0, pc\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tadds\tr3, #4\n-\tadds\tr0, #144\t@ 0x90\n+\tadd\tr4, r0\n+\tbne.n\t11ac <__gridxc_fftr_MOD_fftr2k+0x354>\n+\tadd.w\tr8, r8, #1\n+\tadd\tfp, ip\n+\tcmp\tr8, r5\n+\tbne.n\t11a8 <__gridxc_fftr_MOD_fftr2k+0x350>\n+\tadds\tr2, #1\n+\tadd\tlr, r9\n+\tcmp\tr2, r6\n+\tbne.n\t11a2 <__gridxc_fftr_MOD_fftr2k+0x34a>\n+\tldr\tr1, [pc, #660]\t@ (1460 <__gridxc_fftr_MOD_fftr2k+0x608>)\n+\tldr\tr3, [sp, #252]\t@ 0xfc\n+\tldr\tr2, [sp, #172]\t@ 0xac\n \tadd\tr1, pc\n+\tldr\tr0, [sp, #256]\t@ 0x100\n \tbl\t0 <__gridxc_fft3d_MOD_fft3d>\n R_ARM_THM_CALL\t__gridxc_fft3d_MOD_fft3d\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #232]\t@ 0xe8\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \torrs\tr3, r2\n-\tbmi.n\t117e <__gridxc_fftr_MOD_fftr2k+0x406>\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tbmi.n\t1230 <__gridxc_fftr_MOD_fftr2k+0x3d8>\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n \tcmp\tr3, #1\n-\tbne.w\t1546 <__gridxc_fftr_MOD_fftr2k+0x7ce>\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n-\tmovs\tr7, #0\n-\tldr\tr4, [sp, #128]\t@ 0x80\n-\tldr.w\tfp, [sp, #104]\t@ 0x68\n+\tbne.w\t16ce <__gridxc_fftr_MOD_fftr2k+0x876>\n+\tmovs\tr6, #0\n+\tstr.w\tsl, [sp, #52]\t@ 0x34\n+\tldr\tr5, [sp, #148]\t@ 0x94\n \tmov\tsl, r6\n-\tldrd\tr8, r9, [sp, #184]\t@ 0xb8\n-\tmov\tr6, r7\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tmovs\tr5, #0\n-\tadd.w\tr7, r3, sl, lsl #3\n-\tmov\tr0, r7\n-\tmov\tr2, r8\n+\tldr.w\tfp, [sp, #88]\t@ 0x58\n+\tldr.w\tr8, [sp, #160]\t@ 0xa0\n+\tldr.w\tr9, [sp, #204]\t@ 0xcc\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tadd.w\tr3, fp, r5, lsl #3\n+\tmovs\tr4, #0\n+\tmov\tr0, r3\n+\tmov\tr2, r7\n \tmovs\tr1, #0\n-\tadd\tr7, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tcmp\tr5, r4\n-\tadd.w\tr5, r5, #1\n-\tbne.n\t115a <__gridxc_fftr_MOD_fftr2k+0x3e2>\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tadd\tsl, fp\n-\tadds\tr3, r6, #1\n-\tcmp\tr6, r2\n-\tbeq.n\t117c <__gridxc_fftr_MOD_fftr2k+0x404>\n-\tmov\tr6, r3\n-\tb.n\t1152 <__gridxc_fftr_MOD_fftr2k+0x3da>\n-\tstr\tr4, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tmov\tr3, r0\n+\tcmp\tr4, r8\n+\tadd\tr3, r9\n+\tadd.w\tr4, r4, #1\n+\tbne.n\t1206 <__gridxc_fftr_MOD_fftr2k+0x3ae>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tsl, r6\n+\tadd\tr5, r3\n+\tadd.w\tr3, sl, #1\n+\tbeq.n\t122c <__gridxc_fftr_MOD_fftr2k+0x3d4>\n+\tmov\tsl, r3\n+\tb.n\t1200 <__gridxc_fftr_MOD_fftr2k+0x3a8>\n+\tldr.w\tsl, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tldr\tr2, [sp, #168]\t@ 0xa8\n \tcmp\tr3, r2\n-\tblt.w\t12f4 <__gridxc_fftr_MOD_fftr2k+0x57c>\n-\tldr.w\tr2, [pc, #1088]\t@ 15cc <__gridxc_fftr_MOD_fftr2k+0x854>\n-\tldr\tr1, [sp, #108]\t@ 0x6c\n+\tblt.w\t13e0 <__gridxc_fftr_MOD_fftr2k+0x588>\n+\tldr\tr2, [pc, #552]\t@ (1464 <__gridxc_fftr_MOD_fftr2k+0x60c>)\n+\tldr\tr0, [sp, #136]\t@ 0x88\n \tadd\tr2, pc\n \tldr.w\tr3, [r2, #148]\t@ 0x94\n-\tldr.w\tr6, [r2, #204]\t@ 0xcc\n-\tadd.w\tr7, r3, r6, lsl #1\n+\tldr.w\tr1, [r2, #204]\t@ 0xcc\n+\tadd.w\tip, r3, r1, lsl #1\n+\tldr\tr3, [sp, #188]\t@ 0xbc\n+\tcmp\tr3, r0\n+\tblt.w\t13e0 <__gridxc_fftr_MOD_fftr2k+0x588>\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tldr\tr0, [sp, #164]\t@ 0xa4\n+\tcmp\tr3, r0\n+\tblt.w\t13e0 <__gridxc_fftr_MOD_fftr2k+0x588>\n \tldr\tr3, [sp, #156]\t@ 0x9c\n-\tcmp\tr3, r1\n-\tblt.w\t12f4 <__gridxc_fftr_MOD_fftr2k+0x57c>\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tcmp\tr3, r1\n-\tblt.w\t12f4 <__gridxc_fftr_MOD_fftr2k+0x57c>\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tldr.w\tr3, [r2, #144]\t@ 0x90\n-\tldr.w\tr0, [r2, #192]\t@ 0xc0\n-\tcmp\tr4, #1\n-\tldr.w\tr1, [r2, #180]\t@ 0xb4\n-\tldrd\tr2, fp, [r2, #164]\t@ 0xa4\n-\tbne.w\t13a8 <__gridxc_fftr_MOD_fftr2k+0x630>\n-\tldr\tr5, [sp, #140]\t@ 0x8c\n-\tnegs\tr6, r6\n-\tmul.w\tr4, r6, r2\n-\tldr\tr6, [sp, #136]\t@ 0x88\n-\tmul.w\tr5, r0, r5\n-\tmul.w\tr0, r0, r2\n-\tmov\tlr, r4\n+\tldr.w\tr6, [r2, #144]\t@ 0x90\n+\tldr.w\tr5, [r2, #192]\t@ 0xc0\n+\tcmp\tr3, #1\n+\tldr.w\tr4, [r2, #180]\t@ 0xb4\n+\tldrd\tr2, r0, [r2, #164]\t@ 0xa4\n+\tbne.w\t14f8 <__gridxc_fftr_MOD_fftr2k+0x6a0>\n+\tnegs\tr1, r1\n+\tstr\tr7, [sp, #264]\t@ 0x108\n+\tstr.w\tsl, [sp, #268]\t@ 0x10c\n+\tmul.w\tr3, r1, r2\n+\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tmul.w\tr1, r5, r1\n+\tmul.w\tr5, r5, r2\n+\tstr\tr5, [sp, #140]\t@ 0x8c\n+\tmla\tr1, r3, r0, r1\n+\tldr\tr5, [sp, #136]\t@ 0x88\n+\tmla\tr1, r4, r5, r1\n+\tmul.w\tr4, r2, r4\n+\tadd.w\tr3, ip, r1\n+\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tstr\tr4, [sp, #108]\t@ 0x6c\n+\tnegs\tr4, r1\n+\tldr\tr1, [sp, #192]\t@ 0xc0\n+\tmla\tr5, r2, r3, r6\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tmul.w\tr2, r2, r0\n+\tmvns\tr1, r1\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tmov\tr7, r5\n+\tldrd\tr8, r2, [r3]\n+\tstr\tr1, [sp, #144]\t@ 0x90\n+\tldr\tr0, [r3, #8]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr1, [sp, #148]\t@ 0x94\n+\tnegs\tr3, r3\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tmov\tr9, r1\n \tstr\tr0, [sp, #116]\t@ 0x74\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tmla\tr5, r6, fp, r5\n-\tmul.w\tfp, r2, fp\n-\tmla\tr5, r1, r0, r5\n-\tldr\tr0, [sp, #160]\t@ 0xa0\n-\tmul.w\tr1, r1, r2\n-\tadd\tr5, r7\n-\tstr\tr1, [sp, #80]\t@ 0x50\n-\tmvns\tr0, r0\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n-\tstr\tr0, [sp, #120]\t@ 0x78\n-\tmla\tr6, r2, r5, r3\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tldr\tr0, [sp, #156]\t@ 0x9c\n-\tldrd\tsl, r1, [r3]\n-\tnegs\tr2, r2\n-\tldr\tr5, [r3, #8]\n+\tldr\tr0, [sp, #188]\t@ 0xbc\n+\tmvn.w\tfp, r3\n+\tmul.w\tr3, r8, r2\n+\tstr\tr2, [sp, #80]\t@ 0x50\n \tadds\tr0, #1\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tnegs\tr3, r3\n-\tstr\tr1, [sp, #56]\t@ 0x38\n-\tmvn.w\tr9, r2\n-\tmul.w\tr2, sl, r1\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tnegs\tr1, r3\n-\tcmp\tr5, #0\n-\tmul.w\tr1, r2, r1\n-\tblt.w\t1386 <__gridxc_fftr_MOD_fftr2k+0x60e>\n-\tcmp\tr3, #0\n-\tblt.w\t1398 <__gridxc_fftr_MOD_fftr2k+0x620>\n-\tsdiv\tr2, r3, r5\n-\tsubs\tr4, r3, #1\n-\tmls\tr2, r5, r2, r3\n-\tadds\tr3, r1, #1\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tstrd\tr5, r4, [sp, #96]\t@ 0x60\n-\tmov\tr4, r7\n-\tstrd\tr6, r7, [sp, #88]\t@ 0x58\n-\tmul.w\tip, r3, r2\n-\tstrd\tr0, r6, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tcmp\tr2, #0\n-\tmul.w\tr8, sl, r3\n-\trsb\tr3, r3, #0\n-\tblt.w\t1372 <__gridxc_fftr_MOD_fftr2k+0x5fa>\n-\tcmp\tr3, #0\n-\tblt.w\t1382 <__gridxc_fftr_MOD_fftr2k+0x60a>\n-\tsdiv\tr7, r3, r2\n-\tmls\tr7, r2, r7, r3\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tstr\tr0, [sp, #96]\t@ 0x60\n+\tstr.w\tfp, [sp, #60]\t@ 0x3c\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tnegs\tr3, r4\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tcmp\tr1, #0\n+\tmul.w\tr5, r2, r3\n+\tblt.w\t14ce <__gridxc_fftr_MOD_fftr2k+0x676>\n+\tcmp\tr4, #0\n+\tblt.w\t14e4 <__gridxc_fftr_MOD_fftr2k+0x68c>\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tsl, r0\n+\tsubs\tr3, r4, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr6, [sp, #136]\t@ 0x88\n+\tstrd\tr7, r9, [sp, #68]\t@ 0x44\n+\tstr\tr7, [sp, #128]\t@ 0x80\n+\tmls\tsl, r3, sl, r4\n+\tadds\tr3, r5, #1\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tstr\tr6, [sp, #76]\t@ 0x4c\n+\tstr.w\tr9, [sp, #132]\t@ 0x84\n+\tmul.w\tr3, r3, sl\n+\tstr\tr3, [sp, #52]\t@ 0x34\n \tldr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tadd\tr8, r3\n-\tldr\tr1, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tmul.w\tr7, sl, r7\n-\tadd.w\tr5, r2, r4, lsl #3\n-\tsub.w\tr6, r8, r3\n-\tcmp.w\tsl, #0\n-\tblt.n\t135c <__gridxc_fftr_MOD_fftr2k+0x5e4>\n-\tcmp\tr3, #0\n-\tblt.n\t136c <__gridxc_fftr_MOD_fftr2k+0x5f4>\n-\tsdiv\tr2, r3, sl\n-\tsubs\tr0, r3, #1\n-\tmls\tr2, sl, r2, r3\n-\tadds\tr2, #1\n-\tadd\tr2, r7\n-\tadd\tr2, ip\n-\tcmp\tr6, r2\n-\tbgt.n\t133e <__gridxc_fftr_MOD_fftr2k+0x5c6>\n-\tadd.w\tr2, lr, r1\n-\tmov\tr3, r0\n-\tadd\tr1, fp\n-\tcmp\tr0, r9\n-\tvldr\td16, [r2]\n-\tvstmia\tr5!, {d16}\n-\tbne.n\t128e <__gridxc_fftr_MOD_fftr2k+0x516>\n-\tldr\tr2, [sp, #64]\t@ 0x40\n \tldr\tr1, [sp, #80]\t@ 0x50\n-\tadd\tr4, r2\n+\tnegs\tr7, r3\n+\tcmp\tr1, #0\n+\tmul.w\tr9, r8, r3\n+\tblt.w\t14b6 <__gridxc_fftr_MOD_fftr2k+0x65e>\n+\tcmp\tr7, #0\n+\tblt.w\t14ca <__gridxc_fftr_MOD_fftr2k+0x672>\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr4, [sp, #100]\t@ 0x64\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\tmls\tr7, r3, r0, r7\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tmov\tr6, r4\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tmov\tr4, r9\n+\tmul.w\tr7, r8, r7\n+\tadd.w\tfp, r3, r2, lsl #3\n+\tmov\tr9, r7\n+\tsubs\tr7, r4, r6\n+\tcmp.w\tr8, #0\n+\tblt.w\t1496 <__gridxc_fftr_MOD_fftr2k+0x63e>\n+\tcmp\tr6, #0\n+\tblt.w\t14ae <__gridxc_fftr_MOD_fftr2k+0x656>\n+\tmov\tr1, r8\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tadd.w\tsl, r6, #4294967295\t@ 0xffffffff\n+\tmov\tr3, r0\n+\tmls\tr3, r8, r3, r6\n \tldr\tr2, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tadds\tr3, #1\n+\tadd\tr3, r9\n+\tadd\tr3, r2\n+\tcmp\tr7, r3\n+\tbgt.n\t1474 <__gridxc_fftr_MOD_fftr2k+0x61c>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tmov\tr6, sl\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tadd\tr3, r5\n+\tadd\tr5, r2\n+\tldrd\tr0, r1, [r3]\n+\tstrd\tr0, r1, [fp], #8\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tsl, r3\n+\tbne.n\t1366 <__gridxc_fftr_MOD_fftr2k+0x50e>\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tadd\tr2, r1\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr1, [sp, #108]\t@ 0x6c\n+\tstr\tr2, [sp, #72]\t@ 0x48\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #96]\t@ 0x60\n \tcmp\tr2, r3\n-\tbne.n\t125c <__gridxc_fftr_MOD_fftr2k+0x4e4>\n-\tldrd\tr6, r7, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tldrd\tr5, r4, [sp, #96]\t@ 0x60\n-\tadd\tr7, r2\n-\tldr\tr2, [sp, #116]\t@ 0x74\n-\tmov\tr3, r4\n-\tadd\tr6, r2\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tcmp\tr4, r2\n-\tbne.n\t1224 <__gridxc_fftr_MOD_fftr2k+0x4ac>\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [sp, #148]\t@ 0x94\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tbne.n\t132a <__gridxc_fftr_MOD_fftr2k+0x4d2>\n+\tldrd\tr7, r9, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tldr\tr4, [sp, #124]\t@ 0x7c\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tadd\tr7, r3\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tcmp\tr4, r3\n+\tbne.n\t12e8 <__gridxc_fftr_MOD_fftr2k+0x490>\n+\tldrd\tr7, sl, [sp, #264]\t@ 0x108\n+\tldr\tr2, [sp, #148]\t@ 0x94\n+\tldr\tr1, [sp, #180]\t@ 0xb4\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n \tadd\tr2, r1\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n+\tstr\tr2, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #196]\t@ 0xc4\n \tcmp\tr2, r3\n-\tbge.w\tf8c <__gridxc_fftr_MOD_fftr2k+0x214>\n-\tldr\tr0, [pc, #708]\t@ (15d0 <__gridxc_fftr_MOD_fftr2k+0x858>)\n+\tbge.w\t1056 <__gridxc_fftr_MOD_fftr2k+0x1fe>\n+\tldr\tr0, [pc, #112]\t@ (1468 <__gridxc_fftr_MOD_fftr2k+0x610>)\n \tmovs\tr2, #0\n-\tldr\tr1, [pc, #708]\t@ (15d4 <__gridxc_fftr_MOD_fftr2k+0x85c>)\n+\tldr\tr1, [pc, #112]\t@ (146c <__gridxc_fftr_MOD_fftr2k+0x614>)\n \tmovs\tr3, #9\n \tadd\tr0, pc\n \tstr\tr2, [sp, #0]\n \tadd\tr1, pc\n \tadds\tr0, #144\t@ 0x90\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tldr\tr2, [pc, #696]\t@ (15d8 <__gridxc_fftr_MOD_fftr2k+0x860>)\n-\tldr\tr3, [pc, #632]\t@ (159c <__gridxc_fftr_MOD_fftr2k+0x824>)\n+\tldr\tr2, [pc, #100]\t@ (1470 <__gridxc_fftr_MOD_fftr2k+0x618>)\n+\tldr\tr3, [pc, #36]\t@ (1434 <__gridxc_fftr_MOD_fftr2k+0x5dc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #468]\t@ 0x1d4\n+\tldr\tr3, [sp, #492]\t@ 0x1ec\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1592 <__gridxc_fftr_MOD_fftr2k+0x81a>\n-\tadd\tsp, #476\t@ 0x1dc\n-\tvpop\t{d8-d9}\n+\tbne.w\t1720 <__gridxc_fftr_MOD_fftr2k+0x8c8>\n+\tadd\tsp, #500\t@ 0x1f4\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td16, [r1]\n-\tmov\tr3, r0\n-\tadd\tr1, fp\n-\tcmp\tr9, r0\n-\tvneg.f64\td16, d16\n-\tvstmia\tr5!, {d16}\n-\tbeq.n\t12c4 <__gridxc_fftr_MOD_fftr2k+0x54c>\n-\tsub.w\tr6, r8, r3\n-\tcmp.w\tsl, #0\n-\tbge.n\t1298 <__gridxc_fftr_MOD_fftr2k+0x520>\n-\tsubs\tr0, r3, #1\n-\tcmp\tr3, #0\n-\tmov\tr2, r0\n-\tble.n\t129c <__gridxc_fftr_MOD_fftr2k+0x524>\n-\tsdiv\tr2, r2, sl\n-\tsubs\tr2, #1\n-\tb.n\t12a2 <__gridxc_fftr_MOD_fftr2k+0x52a>\n-\tadds\tr2, r3, #1\n-\tsubs\tr0, r3, #1\n-\tb.n\t1364 <__gridxc_fftr_MOD_fftr2k+0x5ec>\n-\tsubs\tr7, r3, #1\n-\tcmp\tr3, #0\n-\tble.w\t1274 <__gridxc_fftr_MOD_fftr2k+0x4fc>\n-\tsdiv\tr7, r7, r2\n-\tsubs\tr7, #1\n-\tb.n\t1278 <__gridxc_fftr_MOD_fftr2k+0x500>\n-\tadds\tr7, r3, #1\n-\tb.n\t137a <__gridxc_fftr_MOD_fftr2k+0x602>\n-\tsubs\tr4, r3, #1\n-\tcmp\tr3, #0\n-\tmov\tr2, r4\n-\tble.w\t1238 <__gridxc_fftr_MOD_fftr2k+0x4c0>\n-\tsdiv\tr2, r2, r5\n-\tsubs\tr2, #1\n-\tb.n\t123e <__gridxc_fftr_MOD_fftr2k+0x4c6>\n-\tadds\tr2, r3, #1\n-\tsubs\tr4, r3, #1\n-\tb.n\t1390 <__gridxc_fftr_MOD_fftr2k+0x618>\n-\tadds\tr4, #12\n-\tcmp\tr5, sl\n-\tbne.w\te88 <__gridxc_fftr_MOD_fftr2k+0x110>\n-\tb.n\tece <__gridxc_fftr_MOD_fftr2k+0x156>\n-\tmul.w\tr4, r2, r6\n-\tsubs\tr5, r7, r6\n-\tstr\tr4, [sp, #48]\t@ 0x30\n-\tldr\tr4, [sp, #140]\t@ 0x8c\n-\tldr.w\tlr, [sp, #172]\t@ 0xac\n-\tldr.w\tsl, [sp, #48]\t@ 0x30\n-\tmla\tr5, r0, r4, r5\n-\tmul.w\tr0, r2, r0\n-\tstr\tr0, [sp, #116]\t@ 0x74\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tmla\tr0, r1, r0, r5\n-\tldr\tr5, [sp, #136]\t@ 0x88\n-\tmul.w\tr1, r1, r2\n-\tstr\tr1, [sp, #80]\t@ 0x50\n-\tmla\tr0, r5, fp, r0\n-\tnegs\tr5, r5\n-\tmul.w\tfp, r2, fp\n-\tstr\tr5, [sp, #72]\t@ 0x48\n-\tmla\tr7, r2, r0, r3\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr0, [sp, #160]\t@ 0xa0\n-\tldrd\tr1, r2, [r3]\n-\tmvns\tr0, r0\n-\tldr\tr6, [r3, #8]\n-\tnegs\tr3, r4\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr4, [sp, #156]\t@ 0x9c\n-\tmul.w\tr2, r2, r1\n-\tstr\tr0, [sp, #120]\t@ 0x78\n-\tcmp\tr6, #0\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tadd.w\tr4, r4, #1\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tstr\tr4, [sp, #68]\t@ 0x44\n-\tmov\tr4, r0\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tmvn.w\tr9, r2\n-\trsb\tr2, r3, #0\n-\tmul.w\tr0, r0, r2\n-\tblt.n\t14e8 <__gridxc_fftr_MOD_fftr2k+0x770>\n-\tcmp\tr3, #0\n-\tblt.w\t1540 <__gridxc_fftr_MOD_fftr2k+0x7c8>\n-\tsdiv\tr2, r3, r6\n-\tsubs\tr5, r3, #1\n-\tmls\tr2, r6, r2, r3\n-\tadds\tr3, r0, #1\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr.w\tr8, [sp, #108]\t@ 0x6c\n-\tstr\tr4, [sp, #48]\t@ 0x30\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tmul.w\tip, r3, r2\n-\tmov\tr3, r7\n-\tstr.w\tr8, [sp, #52]\t@ 0x34\n-\tstrd\tr4, r7, [sp, #92]\t@ 0x5c\n-\tstr\tr5, [sp, #100]\t@ 0x64\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tcmp\tr0, #0\n-\tmul.w\tr7, r2, r1\n-\trsb\tr2, r2, #0\n-\tblt.n\t152e <__gridxc_fftr_MOD_fftr2k+0x7b6>\n-\tcmp\tr2, #0\n-\tblt.n\t153c <__gridxc_fftr_MOD_fftr2k+0x7c4>\n-\tsdiv\tr6, r2, r0\n-\tmls\tr6, r0, r6, r2\n-\tldr\tr4, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tadd\tr7, r2\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tmul.w\tr6, r1, r6\n-\tadd.w\tr4, r0, r4, lsl #3\n-\tmov\tr0, r3\n-\tcmp\tr1, #0\n-\tblt.n\t1514 <__gridxc_fftr_MOD_fftr2k+0x79c>\n-\tcmp\tr2, #0\n-\tblt.n\t1526 <__gridxc_fftr_MOD_fftr2k+0x7ae>\n-\tsdiv\tr5, r2, r1\n-\tadd.w\tr8, r2, #4294967295\t@ 0xffffffff\n-\tmls\tr5, r1, r5, r2\n-\tsubs\tr2, r7, r2\n-\tadds\tr5, #1\n-\tadd\tr5, r6\n-\tadd\tr5, ip\n-\tcmp\tr5, r2\n-\tmov\tr2, r8\n-\tblt.n\t14f8 <__gridxc_fftr_MOD_fftr2k+0x780>\n-\tvldr\td16, [r0]\n-\tcmp\tr8, r9\n-\tadd\tr0, fp\n-\tvstr\td16, [r4]\n-\tadd\tr4, lr\n-\tbne.n\t1478 <__gridxc_fftr_MOD_fftr2k+0x700>\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tadd\tr0, r4\n-\tstr\tr0, [sp, #48]\t@ 0x30\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tadd\tr3, r0\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tcmp\tr2, r0\n-\tbne.n\t1448 <__gridxc_fftr_MOD_fftr2k+0x6d0>\n-\tldrd\tr6, r4, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tldrd\tr7, r5, [sp, #96]\t@ 0x60\n-\tadd\tr4, r2\n-\tldr\tr2, [sp, #116]\t@ 0x74\n-\tmov\tr3, r5\n-\tadd\tr7, r2\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tcmp\tr5, r2\n-\tbeq.w\t12f4 <__gridxc_fftr_MOD_fftr2k+0x57c>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tnegs\tr2, r3\n-\tcmp\tr6, #0\n-\tmul.w\tr0, r0, r2\n-\tbge.n\t141a <__gridxc_fftr_MOD_fftr2k+0x6a2>\n-\tsubs\tr5, r3, #1\n-\tcmp\tr3, #0\n-\tmov\tr2, r5\n-\tble.n\t1420 <__gridxc_fftr_MOD_fftr2k+0x6a8>\n-\tsdiv\tr2, r2, r6\n-\tsubs\tr2, #1\n-\tb.n\t1426 <__gridxc_fftr_MOD_fftr2k+0x6ae>\n-\tadd.w\tr5, r0, sl\n-\tcmp\tr8, r9\n-\tadd\tr0, fp\n-\tvldr\td16, [r5]\n-\tvneg.f64\td16, d16\n-\tvstr\td16, [r4]\n-\tadd\tr4, lr\n-\tbeq.n\t14aa <__gridxc_fftr_MOD_fftr2k+0x732>\n-\tcmp\tr1, #0\n-\tbge.n\t147c <__gridxc_fftr_MOD_fftr2k+0x704>\n-\tadd.w\tr8, r2, #4294967295\t@ 0xffffffff\n-\tcmp\tr2, #0\n-\tmov\tr5, r8\n-\tble.n\t1480 <__gridxc_fftr_MOD_fftr2k+0x708>\n-\tsdiv\tr5, r5, r1\n-\tsubs\tr5, #1\n-\tb.n\t1488 <__gridxc_fftr_MOD_fftr2k+0x710>\n-\tadds\tr5, r2, #1\n-\tadd.w\tr8, r2, #4294967295\t@ 0xffffffff\n-\tb.n\t151e <__gridxc_fftr_MOD_fftr2k+0x7a6>\n-\tsubs\tr6, r2, #1\n-\tcmp\tr2, #0\n-\tble.n\t145c <__gridxc_fftr_MOD_fftr2k+0x6e4>\n-\tsdiv\tr6, r6, r0\n-\tsubs\tr6, #1\n-\tb.n\t1460 <__gridxc_fftr_MOD_fftr2k+0x6e8>\n-\tadds\tr6, r2, #1\n-\tb.n\t1534 <__gridxc_fftr_MOD_fftr2k+0x7bc>\n-\tadds\tr2, r3, #1\n-\tsubs\tr5, r3, #1\n-\tb.n\t14f0 <__gridxc_fftr_MOD_fftr2k+0x778>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tmov\tsl, r2\n-\tldr.w\tr8, [sp, #60]\t@ 0x3c\n-\tmovs\tr1, #0\n-\tldr\tr6, [sp, #244]\t@ 0xf4\n-\tldr.w\tr9, [sp, #64]\t@ 0x40\n-\tldr\tr4, [sp, #128]\t@ 0x80\n-\tldr\tr5, [sp, #104]\t@ 0x68\n-\tldr\tr7, [sp, #172]\t@ 0xac\n-\tmov\tip, r3\n-\tmov.w\tlr, #0\n-\tadd.w\tfp, r8, ip, lsl #3\n-\tmovs\tr0, #0\n-\tcmp\tr6, r0\n-\tvstr\td8, [fp]\n-\tadd.w\tr0, r0, #1\n-\tadd\tfp, r7\n-\tbne.n\t1568 <__gridxc_fftr_MOD_fftr2k+0x7f0>\n-\tadd\tip, r9\n-\tadd.w\tr2, lr, #1\n-\tcmp\tlr, r4\n-\tbeq.n\t1584 <__gridxc_fftr_MOD_fftr2k+0x80c>\n-\tmov\tlr, r2\n-\tb.n\t1562 <__gridxc_fftr_MOD_fftr2k+0x7ea>\n-\tadd\tr3, r5\n-\tadds\tr2, r1, #1\n-\tcmp\tr1, sl\n-\tbeq.w\t117c <__gridxc_fftr_MOD_fftr2k+0x404>\n-\tmov\tr1, r2\n-\tb.n\t155c <__gridxc_fftr_MOD_fftr2k+0x7e4>\n-\tbl\t0 <__stack_chk_fail>\n- R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x000007f8\n+\t...\n+\t.word\t0x000005b4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000007f2\n+\t.word\t0x000005ae\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000786\n+\t.word\t0x00000554\n R_ARM_REL32\t.data\n-\t.word\t0x00000726\n+\t.word\t0x000004ea\n R_ARM_REL32\t.LC6\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000006d2\n+\t.word\t0x00000498\n R_ARM_REL32\t.rodata\n-\t.word\t0x000006ca\n+\t.word\t0x00000490\n R_ARM_REL32\t.bss\n-\t.word\t0x000006ca\n+\t.word\t0x0000048e\n R_ARM_REL32\t.LC7\n-\t.word\t0x0000066e\n+\t.word\t0x00000442\n R_ARM_REL32\t.data\n-\t.word\t0x0000049c\n+\t.word\t0x00000434\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000049e\n+\t.word\t0x00000426\n R_ARM_REL32\t.bss\n-\t.word\t0x0000049a\n+\t.word\t0x0000028c\n R_ARM_REL32\t.data\n-\t.word\t0x0000043a\n+\t.word\t0x00000222\n R_ARM_REL32\t.bss\n-\t.word\t0x000002ba\n+\t.word\t0x00000066\n R_ARM_REL32\t.bss\n-\t.word\t0x000002ba\n+\t.word\t0x00000066\n R_ARM_REL32\t.LC7\n-\t.word\t0x000002b2\n+\t.word\t0x0000005e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\tvldr\td7, [r5]\n+\tmov\tr6, sl\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvneg.f64\td7, d7\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tr3, sl\n+\tvstmia\tfp!, {d7}\n+\tbeq.n\t13ac <__gridxc_fftr_MOD_fftr2k+0x554>\n+\tsubs\tr7, r4, r6\n+\tcmp.w\tr8, #0\n+\tbge.w\t1370 <__gridxc_fftr_MOD_fftr2k+0x518>\n+\tcmp\tr6, #0\n+\titt\tgt\n+\taddgt.w\tsl, r6, #4294967295\t@ 0xffffffff\n+\tmovgt\tr0, sl\n+\tble.w\t1376 <__gridxc_fftr_MOD_fftr2k+0x51e>\n+\tmov\tr1, r8\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, #1\n+\tb.n\t1384 <__gridxc_fftr_MOD_fftr2k+0x52c>\n+\tadds\tr0, r6, #1\n+\tadd.w\tsl, r6, #4294967295\t@ 0xffffffff\n+\tb.n\t14a4 <__gridxc_fftr_MOD_fftr2k+0x64c>\n+\tcmp\tr7, #0\n+\tit\tgt\n+\taddgt.w\tr0, r7, #4294967295\t@ 0xffffffff\n+\tble.w\t1340 <__gridxc_fftr_MOD_fftr2k+0x4e8>\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t1346 <__gridxc_fftr_MOD_fftr2k+0x4ee>\n+\tadds\tr0, r7, #1\n+\tb.n\t14c2 <__gridxc_fftr_MOD_fftr2k+0x66a>\n+\tcmp\tr4, #0\n+\tble.w\t12fe <__gridxc_fftr_MOD_fftr2k+0x4a6>\n+\tsubs\tr3, r4, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tmov\tr0, r3\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tadd.w\tsl, r0, #4294967295\t@ 0xffffffff\n+\tb.n\t130a <__gridxc_fftr_MOD_fftr2k+0x4b2>\n+\tsubs\tr3, r4, #1\n+\tadds\tr0, r4, #1\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tb.n\t14da <__gridxc_fftr_MOD_fftr2k+0x682>\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tadds\tr4, #12\n+\tcmp\tr5, r3\n+\tbne.w\tf56 <__gridxc_fftr_MOD_fftr2k+0xfe>\n+\tb.n\tfa0 <__gridxc_fftr_MOD_fftr2k+0x148>\n+\tsub.w\tr3, ip, r1\n+\tmul.w\tr1, r2, r1\n+\tstr\tr1, [sp, #60]\t@ 0x3c\n+\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tstr\tr7, [sp, #144]\t@ 0x90\n+\tstr.w\tsl, [sp, #264]\t@ 0x108\n+\tmla\tr3, r5, r1, r3\n+\tmul.w\tr5, r2, r5\n+\tstr\tr5, [sp, #132]\t@ 0x84\n+\tldr\tr5, [sp, #136]\t@ 0x88\n+\tmla\tr3, r4, r5, r3\n+\tnegs\tr5, r1\n+\tmul.w\tr4, r4, r2\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tldr\tr4, [sp, #164]\t@ 0xa4\n+\tmla\tr3, r4, r0, r3\n+\tmla\tr3, r2, r3, r6\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tmul.w\tr3, r2, r0\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tldrd\tr8, r2, [r3]\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr6, [r3, #8]\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tmul.w\tr9, r2, r8\n+\tmov\tr7, r6\n+\tmvns\tr3, r3\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tmov\tr6, r9\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #188]\t@ 0xbc\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tnegs\tr3, r4\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tmvn.w\tfp, r3\n+\tnegs\tr3, r5\n+\tcmp\tr7, #0\n+\tmul.w\tr9, r6, r3\n+\tblt.w\t16b0 <__gridxc_fftr_MOD_fftr2k+0x858>\n+\tcmp\tr5, #0\n+\tblt.w\t16c8 <__gridxc_fftr_MOD_fftr2k+0x870>\n+\tmov\tr1, r7\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr4, r5, #1\n+\tmov\tr3, r0\n+\tmls\tr3, r7, r3, r5\n+\tadd.w\tr2, r9, #1\n+\tstrd\tr6, r7, [sp, #120]\t@ 0x78\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tstr\tr4, [sp, #128]\t@ 0x80\n+\tmul.w\tr9, r6, r3\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tnegs\tr6, r3\n+\tcmp\tr1, #0\n+\tmul.w\tr7, r3, r8\n+\tblt.n\t169a <__gridxc_fftr_MOD_fftr2k+0x842>\n+\tcmp\tr6, #0\n+\tblt.n\t16ac <__gridxc_fftr_MOD_fftr2k+0x854>\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #100]\t@ 0x64\n+\tldr\tr5, [sp, #72]\t@ 0x48\n+\tmls\tr6, r3, r0, r6\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tr7, r3\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tmul.w\tr6, r8, r6\n+\tadd.w\tsl, r3, r2, lsl #3\n+\tmov\tr2, r4\n+\tmov\tr4, r7\n+\tmov\tr7, r6\n+\tcmp.w\tr8, #0\n+\tblt.n\t167a <__gridxc_fftr_MOD_fftr2k+0x822>\n+\tcmp\tr2, #0\n+\tblt.n\t1694 <__gridxc_fftr_MOD_fftr2k+0x83c>\n+\tmov\tr0, r2\n+\tmov\tr1, r8\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tmov\tr3, r0\n+\tsubs\tr6, r2, #1\n+\tmls\tr3, r8, r3, r2\n+\tsubs\tr2, r4, r2\n+\tadds\tr3, #1\n+\tadd\tr3, r7\n+\tadd\tr3, r9\n+\tcmp\tr3, r2\n+\tmov\tr2, r6\n+\tblt.n\t1658 <__gridxc_fftr_MOD_fftr2k+0x800>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr6, fp\n+\tldrd\tr0, r1, [r5]\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tstrd\tr0, r1, [sl]\n+\tadd\tsl, r3\n+\tbne.n\t15d6 <__gridxc_fftr_MOD_fftr2k+0x77e>\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr2, r1\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tadds\tr3, #1\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tcmp\tr3, r2\n+\tbne.n\t159e <__gridxc_fftr_MOD_fftr2k+0x746>\n+\tldrd\tr3, r2, [sp, #108]\t@ 0x6c\n+\tldr\tr4, [sp, #128]\t@ 0x80\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #132]\t@ 0x84\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tmov\tr5, r4\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tldrd\tr6, r7, [sp, #120]\t@ 0x78\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tcmp\tr4, r3\n+\tbne.n\t1560 <__gridxc_fftr_MOD_fftr2k+0x708>\n+\tldr\tr7, [sp, #144]\t@ 0x90\n+\tldr.w\tsl, [sp, #264]\t@ 0x108\n+\tb.n\t13e0 <__gridxc_fftr_MOD_fftr2k+0x588>\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tr6, fp\n+\tadd\tr3, r5\n+\tvldr\td7, [r3]\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tvneg.f64\td7, d7\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tvstr\td7, [sl]\n+\tadd\tsl, r3\n+\tbeq.n\t1616 <__gridxc_fftr_MOD_fftr2k+0x7be>\n+\tcmp.w\tr8, #0\n+\tbge.n\t15dc <__gridxc_fftr_MOD_fftr2k+0x784>\n+\tcmp\tr2, #0\n+\titt\tgt\n+\taddgt.w\tr6, r2, #4294967295\t@ 0xffffffff\n+\tmovgt\tr0, r6\n+\tble.n\t15e0 <__gridxc_fftr_MOD_fftr2k+0x788>\n+\tmov\tr1, r8\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tsubs\tr3, r0, #1\n+\tb.n\t15f0 <__gridxc_fftr_MOD_fftr2k+0x798>\n+\tadds\tr0, r2, #1\n+\tsubs\tr6, r2, #1\n+\tb.n\t1686 <__gridxc_fftr_MOD_fftr2k+0x82e>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.n\t15b0 <__gridxc_fftr_MOD_fftr2k+0x758>\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t15b6 <__gridxc_fftr_MOD_fftr2k+0x75e>\n+\tadds\tr0, r6, #1\n+\tb.n\t16a4 <__gridxc_fftr_MOD_fftr2k+0x84c>\n+\tcmp\tr5, #0\n+\titt\tgt\n+\taddgt.w\tr4, r5, #4294967295\t@ 0xffffffff\n+\tmovgt\tr0, r4\n+\tble.w\t1572 <__gridxc_fftr_MOD_fftr2k+0x71a>\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, #1\n+\tb.n\t157e <__gridxc_fftr_MOD_fftr2k+0x726>\n+\tadds\tr0, r5, #1\n+\tsubs\tr4, r5, #1\n+\tb.n\t16be <__gridxc_fftr_MOD_fftr2k+0x866>\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tmovs\tr1, #0\n+\tldr.w\tr8, [sp, #88]\t@ 0x58\n+\tldr\tr5, [sp, #260]\t@ 0x104\n+\tldr.w\tr9, [sp, #92]\t@ 0x5c\n+\tldr.w\tfp, [sp, #160]\t@ 0xa0\n+\tldr\tr6, [sp, #84]\t@ 0x54\n+\tvldr\td7, [pc, #68]\t@ 1728 <__gridxc_fftr_MOD_fftr2k+0x8d0>\n+\tmov\tip, r3\n+\tmov.w\tlr, #0\n+\tadd.w\tr4, r8, ip, lsl #3\n+\tmovs\tr0, #0\n+\tcmp\tr5, r0\n+\tvstr\td7, [r4]\n+\tadd.w\tr0, r0, #1\n+\tadd\tr4, r6\n+\tbne.n\t16f2 <__gridxc_fftr_MOD_fftr2k+0x89a>\n+\tadd\tip, r9\n+\tadd.w\tr2, lr, #1\n+\tcmp\tlr, fp\n+\tbeq.n\t170e <__gridxc_fftr_MOD_fftr2k+0x8b6>\n+\tmov\tlr, r2\n+\tb.n\t16ec <__gridxc_fftr_MOD_fftr2k+0x894>\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tadds\tr0, r1, #1\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r2\n+\tbeq.w\t1230 <__gridxc_fftr_MOD_fftr2k+0x3d8>\n+\tmov\tr1, r0\n+\tb.n\t16e6 <__gridxc_fftr_MOD_fftr2k+0x88e>\n+\tbl\t0 <__stack_chk_fail>\n+ R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop.w\n+\t...\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -1,36 +1,37 @@\n \n Hex dump of section '.strtab':\n 0x00000000 00246400 2e4c4330 002e4c43 31002e4c .$d..LC0..LC1..L\n 0x00000010 43340024 74002e4c 4336002e 4c433700 C4.$t..LC6..LC7.\n 0x00000020 66632e32 00666d6b 2e310066 632e3000 fc.2.fmk.1.fc.0.\n- 0x00000030 5f5f6772 69647863 5f666674 725f4d4f __gridxc_fftr_MO\n- 0x00000040 445f6666 746b3272 005f5f67 72696478 D_fftk2r.__gridx\n- 0x00000050 635f6d65 73683364 5f4d4f44 5f6d796d c_mesh3d_MOD_mym\n- 0x00000060 65736862 6f78005f 5f677269 6478635f eshbox.__gridxc_\n- 0x00000070 6d657368 33645f4d 4f445f66 66746d65 mesh3d_MOD_fftme\n- 0x00000080 73686469 73747200 5f5f6772 69647863 shdistr.__gridxc\n- 0x00000090 5f616c6c 6f635f4d 4f445f72 65616c6c _alloc_MOD_reall\n- 0x000000a0 6f635f64 34005f5f 67726964 78635f6d oc_d4.__gridxc_m\n- 0x000000b0 65736833 645f4d4f 445f6173 736f6369 esh3d_MOD_associ\n- 0x000000c0 6174656d 65736874 61736b00 5f5f6772 atemeshtask.__gr\n- 0x000000d0 69647863 5f666674 33645f4d 4f445f66 idxc_fft3d_MOD_f\n- 0x000000e0 66743364 005f5f67 72696478 635f6d65 ft3d.__gridxc_me\n- 0x000000f0 73683364 5f4d4f44 5f636f70 796d6573 sh3d_MOD_copymes\n- 0x00000100 68646174 61005f5f 67726964 78635f61 hdata.__gridxc_a\n- 0x00000110 6c6c6f63 5f4d4f44 5f646561 6c6c6f63 lloc_MOD_dealloc\n- 0x00000120 5f643400 5f474c4f 42414c5f 4f464653 _d4._GLOBAL_OFFS\n- 0x00000130 45545f54 41424c45 5f005f5f 73746163 ET_TABLE_.__stac\n- 0x00000140 6b5f6368 6b5f6775 61726400 5f5f6772 k_chk_guard.__gr\n- 0x00000150 69647863 5f737973 5f4d4f44 5f646965 idxc_sys_MOD_die\n- 0x00000160 005f5f73 7461636b 5f63686b 5f666169 .__stack_chk_fai\n- 0x00000170 6c005f5f 67726964 78635f66 6674725f l.__gridxc_fftr_\n- 0x00000180 4d4f445f 66667472 326b006d 656d7365 MOD_fftr2k.memse\n- 0x00000190 74005f5f 67726964 78635f66 6674725f t.__gridxc_fftr_\n- 0x000001a0 4d4f445f 7468656d 65736800 5f5f6772 MOD_themesh.__gr\n- 0x000001b0 69647863 5f666674 725f4d4f 445f7232 idxc_fftr_MOD_r2\n- 0x000001c0 6b005f5f 67726964 78635f66 6674725f k.__gridxc_fftr_\n- 0x000001d0 4d4f445f 6d6b326b 005f5f67 72696478 MOD_mk2k.__gridx\n- 0x000001e0 635f6666 74725f4d 4f445f6b 64697374 c_fftr_MOD_kdist\n- 0x000001f0 72005f5f 67726964 78635f66 6674725f r.__gridxc_fftr_\n- 0x00000200 4d4f445f 6b327200 MOD_k2r.\n+ 0x00000030 5f5f6165 6162695f 69646976 005f5f67 __aeabi_idiv.__g\n+ 0x00000040 72696478 635f6666 74725f4d 4f445f66 ridxc_fftr_MOD_f\n+ 0x00000050 66746b32 72005f5f 67726964 78635f6d ftk2r.__gridxc_m\n+ 0x00000060 65736833 645f4d4f 445f6d79 6d657368 esh3d_MOD_mymesh\n+ 0x00000070 626f7800 5f5f6772 69647863 5f6d6573 box.__gridxc_mes\n+ 0x00000080 6833645f 4d4f445f 6666746d 65736864 h3d_MOD_fftmeshd\n+ 0x00000090 69737472 005f5f67 72696478 635f616c istr.__gridxc_al\n+ 0x000000a0 6c6f635f 4d4f445f 7265616c 6c6f635f loc_MOD_realloc_\n+ 0x000000b0 6434005f 5f677269 6478635f 6d657368 d4.__gridxc_mesh\n+ 0x000000c0 33645f4d 4f445f61 73736f63 69617465 3d_MOD_associate\n+ 0x000000d0 6d657368 7461736b 005f474c 4f42414c meshtask._GLOBAL\n+ 0x000000e0 5f4f4646 5345545f 5441424c 455f005f _OFFSET_TABLE_._\n+ 0x000000f0 5f737461 636b5f63 686b5f67 75617264 _stack_chk_guard\n+ 0x00000100 005f5f67 72696478 635f7379 735f4d4f .__gridxc_sys_MO\n+ 0x00000110 445f6469 65005f5f 67726964 78635f66 D_die.__gridxc_f\n+ 0x00000120 66743364 5f4d4f44 5f666674 3364005f ft3d_MOD_fft3d._\n+ 0x00000130 5f677269 6478635f 6d657368 33645f4d _gridxc_mesh3d_M\n+ 0x00000140 4f445f63 6f70796d 65736864 61746100 OD_copymeshdata.\n+ 0x00000150 5f5f6772 69647863 5f616c6c 6f635f4d __gridxc_alloc_M\n+ 0x00000160 4f445f64 65616c6c 6f635f64 34005f5f OD_dealloc_d4.__\n+ 0x00000170 73746163 6b5f6368 6b5f6661 696c005f stack_chk_fail._\n+ 0x00000180 5f677269 6478635f 66667472 5f4d4f44 _gridxc_fftr_MOD\n+ 0x00000190 5f666674 72326b00 6d656d73 6574005f _fftr2k.memset._\n+ 0x000001a0 5f677269 6478635f 66667472 5f4d4f44 _gridxc_fftr_MOD\n+ 0x000001b0 5f746865 6d657368 005f5f67 72696478 _themesh.__gridx\n+ 0x000001c0 635f6666 74725f4d 4f445f72 326b005f c_fftr_MOD_r2k._\n+ 0x000001d0 5f677269 6478635f 66667472 5f4d4f44 _gridxc_fftr_MOD\n+ 0x000001e0 5f6d6b32 6b005f5f 67726964 78635f66 _mk2k.__gridxc_f\n+ 0x000001f0 6674725f 4d4f445f 6b646973 7472005f ftr_MOD_kdistr._\n+ 0x00000200 5f677269 6478635f 66667472 5f4d4f44 _gridxc_fftr_MOD\n+ 0x00000210 5f6b3272 00 _k2r.\n \n"}]}, {"source1": "ggaxc.F90.o", "source2": "ggaxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 32196 (bytes into file)\n+ Start of section headers: 33688 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x7dc4:\n+There are 12 section headers, starting at offset 0x8398:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 005e78 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 0073d4 000988 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 005eb0 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 005eb0 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 005eb0 0001ff 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0060b0 000038 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 0060e8 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0060e8 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 00611c 000b40 10 10 137 4\n- [10] .strtab STRTAB 00000000 006c5c 000777 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 007d5c 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0063cc 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0079a8 000988 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 006404 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 006404 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 006404 0001ff 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 006608 000038 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 006640 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 006640 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 006670 000bc0 10 10 145 4\n+ [10] .strtab STRTAB 00000000 007230 000777 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 008330 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,183 +1,191 @@\n \n-Symbol table '.symtab' contains 180 entries:\n+Symbol table '.symtab' contains 188 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n- 1: 00000001 960 FUNC LOCAL DEFAULT 1 __gridxc_gga_MOD_pw86formx\n+ 1: 00000001 1016 FUNC LOCAL DEFAULT 1 __gridxc_gga_MOD_pw86formx\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 3: 00000390 0 NOTYPE LOCAL DEFAULT 1 $d\n- 4: 000003c0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 5: 000003c1 1976 FUNC LOCAL DEFAULT 1 __gridxc_gga_MOD_pbeformxc\n- 6: 00000820 0 NOTYPE LOCAL DEFAULT 1 $d\n- 7: 0000086c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 8: 00000b60 0 NOTYPE LOCAL DEFAULT 1 $d\n- 9: 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__gridxc_gga_MOD_pbejsjrhegxc\n- 162: 000044fd 168 FUNC GLOBAL DEFAULT 1 __gridxc_gga_MOD_pbejsjrloxc\n- 163: 000045a5 168 FUNC GLOBAL DEFAULT 1 __gridxc_gga_MOD_pbesolxc\n- 164: 0000464d 168 FUNC GLOBAL DEFAULT 1 __gridxc_gga_MOD_revpbexc\n- 165: 000046f5 168 FUNC GLOBAL DEFAULT 1 __gridxc_gga_MOD_pbexc\n- 166: 0000479d 5852 FUNC GLOBAL DEFAULT 1 __gridxc_gga_MOD_ggaxc\n- 167: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n- 168: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n- 169: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n- 170: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n- 171: 00000000 0 NOTYPE GLOBAL DEFAULT UND atan2\n- 172: 00000000 0 NOTYPE GLOBAL DEFAULT UND sincos\n- 173: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 174: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_hybrids_MOD_hsexc\n- 175: 00000000 0 NOTYPE GLOBAL DEFAULT UND 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0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 186: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n+ 187: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,308 +1,308 @@\n \n-Relocation section '.rel.text' at offset 0x73d4 contains 305 entries:\n+Relocation section '.rel.text' at offset 0x79a8 contains 305 entries:\n Offset Info Type Sym. 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R_ARM_THM_CALL 00000000 cbrt\n-00003a10 0000890a R_ARM_THM_CALL 00000000 cbrt\n-00003a24 0000890a R_ARM_THM_CALL 00000000 cbrt\n-00003a64 0000900a R_ARM_THM_CALL 00000000 exp\n-00003b1c 0000900a R_ARM_THM_CALL 00000000 exp\n-00003b5c 0000910a R_ARM_THM_CALL 00000000 log\n-00003bea 0000890a R_ARM_THM_CALL 00000000 cbrt\n-00003c2a 0000910a R_ARM_THM_CALL 00000000 log\n-00003c46 0000900a R_ARM_THM_CALL 00000000 exp\n-00003d50 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003d54 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003d58 00008703 R_ARM_REL32 00000000 .rodata\n-00003d5c 00008703 R_ARM_REL32 00000000 .rodata\n-00003d74 00008b0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n-000042ea 00008c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000042f8 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000042fc 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004380 00008c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000043a0 00008d19 R_ARM_BASE_PREL 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__stack_chk_fail\n-00004640 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004644 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004648 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000046cc 00008c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000046e8 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000046ec 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000046f0 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004774 00008c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004790 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004794 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004798 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004916 0000a70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-00004922 0000a70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-00004942 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-0000496e 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-00004a4c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004a64 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004a7c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004a94 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004aac 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004ac4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004adc 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004af4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b0c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b24 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b3c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b54 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b6c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004b88 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004ba0 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004bbc 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004bd4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004bec 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c08 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c20 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c3c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c54 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c6c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004c88 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004ca0 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004cb8 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004cd4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004cec 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d04 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d20 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d38 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d50 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d6c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d84 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004da0 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004db4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004f38 0000ab0a R_ARM_THM_CALL 00000000 atan2\n-00004f50 0000ac0a R_ARM_THM_CALL 00000000 sincos\n-00004f70 0000ac0a R_ARM_THM_CALL 00000000 sincos\n-00004faa 0000ab0a R_ARM_THM_CALL 00000000 atan2\n-00004fb2 0000ac0a R_ARM_THM_CALL 00000000 sincos\n-00005118 00008e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000511c 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005120 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005124 0000ad1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00005128 00004f03 R_ARM_REL32 00000000 .LC8\n-0000512c 00005003 R_ARM_REL32 00000028 .LC9\n-00005130 00005103 R_ARM_REL32 00000048 .LC10\n-00005134 00008703 R_ARM_REL32 00000000 .rodata\n-00005138 00008d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000513c 00005203 R_ARM_REL32 00000068 .LC11\n-00005140 00005303 R_ARM_REL32 0000006c .LC12\n-00005144 00005403 R_ARM_REL32 00000070 .LC13\n-00005148 00005503 R_ARM_REL32 00000078 .LC14\n-0000514c 00005603 R_ARM_REL32 00000080 .LC15\n-00005150 00005703 R_ARM_REL32 00000084 .LC16\n-00005154 00005803 R_ARM_REL32 00000088 .LC17\n-00005158 00005903 R_ARM_REL32 00000090 .LC18\n-0000515c 00005a03 R_ARM_REL32 00000098 .LC19\n-00005160 00005b03 R_ARM_REL32 000000a0 .LC20\n-00005164 00005c03 R_ARM_REL32 000000a8 .LC21\n-00005168 00005d03 R_ARM_REL32 000000b0 .LC22\n-0000516c 00005e03 R_ARM_REL32 000000b4 .LC23\n-00005170 00005f03 R_ARM_REL32 000000b8 .LC24\n-00005174 00006003 R_ARM_REL32 000000c0 .LC25\n-00005178 00006103 R_ARM_REL32 000000c8 .LC26\n-0000517c 00006203 R_ARM_REL32 000000d0 .LC27\n-00005180 00006303 R_ARM_REL32 000000d8 .LC28\n-00005184 00006403 R_ARM_REL32 000000e0 .LC29\n-00005188 00006503 R_ARM_REL32 000000e8 .LC30\n-0000518c 00006603 R_ARM_REL32 000000f0 .LC31\n-00005190 00006703 R_ARM_REL32 000000fc .LC32\n-00005194 00006803 R_ARM_REL32 00000108 .LC33\n-00005198 00006903 R_ARM_REL32 00000114 .LC34\n-0000519c 00006a03 R_ARM_REL32 00000120 .LC35\n-000051a0 00006b03 R_ARM_REL32 0000012c .LC36\n-000051a4 00006c03 R_ARM_REL32 00000138 .LC37\n-000051a8 00006d03 R_ARM_REL32 00000144 .LC38\n-000051ac 00006e03 R_ARM_REL32 00000150 .LC39\n-000051b0 00006f03 R_ARM_REL32 0000015c .LC40\n-000051b4 00007003 R_ARM_REL32 00000168 .LC41\n-000051b8 00007103 R_ARM_REL32 00000174 .LC42\n-000051bc 00007203 R_ARM_REL32 00000180 .LC43\n-000051c0 00007303 R_ARM_REL32 00000188 .LC44\n-000051c4 00007403 R_ARM_REL32 00000190 .LC45\n-000051c8 00007503 R_ARM_REL32 00000198 .LC46\n-0000545a 0000a70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-00005466 0000a70a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-00005472 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-0000549e 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-00005570 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-0000559c 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-00005740 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-0000576c 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-000058aa 0000a80a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-000058d6 0000a90a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-000059b8 00008c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00005a04 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005a18 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005be2 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005bf4 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005c40 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005c52 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005c9e 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005cb0 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005cfc 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005d0e 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005d42 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_hybrids_MOD_hsexc\n-00005d5a 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005d6c 0000aa0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00005da0 0000af0a R_ARM_THM_CALL 00000000 __gridxc_hybrids_MOD_pbe0xc\n-00005dba 0000b00a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00005dce 0000b10a R_ARM_THM_CALL 00000000 malloc\n-00005de8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00005df4 0000b30a R_ARM_THM_CALL 00000000 free\n-00005e0c 0000b30a R_ARM_THM_CALL 00000000 free\n-00005e30 00008703 R_ARM_REL32 00000000 .rodata\n-00005e34 00008703 R_ARM_REL32 00000000 .rodata\n-00005e38 00008703 R_ARM_REL32 00000000 .rodata\n-00005e3c 00008703 R_ARM_REL32 00000000 .rodata\n-00005e40 00007603 R_ARM_REL32 000001a0 .LC47\n-00005e44 00007703 R_ARM_REL32 000001a4 .LC48\n-00005e48 00007803 R_ARM_REL32 000001a8 .LC49\n-00005e4c 00007903 R_ARM_REL32 000001b0 .LC50\n-00005e50 00007a03 R_ARM_REL32 000001b8 .LC51\n-00005e54 00007b03 R_ARM_REL32 000001bc .LC52\n-00005e58 00007c03 R_ARM_REL32 000001c0 .LC53\n-00005e5c 00007d03 R_ARM_REL32 000001c4 .LC54\n-00005e60 00007e03 R_ARM_REL32 000001c8 .LC55\n-00005e64 00007f03 R_ARM_REL32 000001d0 .LC56\n-00005e68 00008003 R_ARM_REL32 000001d8 .LC57\n-00005e6c 00008103 R_ARM_REL32 000001e0 .LC58\n-00005e70 00008203 R_ARM_REL32 000001e8 .LC59\n-00005e74 0000ad1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000018e 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000001e2 0000920a R_ARM_THM_CALL 00000000 pow\n+000001f6 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+000003bc 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000003e8 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000003ec 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000003f0 00008f03 R_ARM_REL32 00000000 .rodata\n+000003f4 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000560 0000970a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+0000056c 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000005d4 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000005e8 0000910a R_ARM_THM_CALL 00000000 cbrt\n+0000063c 0000980a R_ARM_THM_CALL 00000000 exp\n+000006aa 0000990a R_ARM_THM_CALL 00000000 log\n+0000075a 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000007ae 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00000880 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000884 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000888 00008f03 R_ARM_REL32 00000000 .rodata\n+00000c4e 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000c68 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000c6c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000dc4 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00000e0e 0000990a R_ARM_THM_CALL 00000000 log\n+00000e6a 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00001010 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001014 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001018 00008f03 R_ARM_REL32 00000000 .rodata\n+0000101c 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000107a 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000011dc 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00001200 0000980a R_ARM_THM_CALL 00000000 exp\n+00001256 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00001430 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001434 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001438 00008f03 R_ARM_REL32 00000000 .rodata\n+0000143c 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000149a 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000152a 00009c0a R_ARM_THM_CALL 00000000 memset\n+00001562 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001580 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001584 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001588 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000160e 00009c0a R_ARM_THM_CALL 00000000 memset\n+00001646 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001668 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000166c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001670 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000017d0 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00001834 0000920a R_ARM_THM_CALL 00000000 pow\n+0000189a 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00001ab0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001ab4 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001ab8 00008f03 R_ARM_REL32 00000000 .rodata\n+00001baa 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001bb8 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001bbc 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001c0e 00009c0a R_ARM_THM_CALL 00000000 memset\n+00001c30 00008f03 R_ARM_REL32 00000000 .rodata\n+00001c82 00009c0a R_ARM_THM_CALL 00000000 memset\n+00001ca4 00008f03 R_ARM_REL32 00000000 .rodata\n+00001de8 0000a20a R_ARM_THM_CALL 00000000 __gridxc_am05_MOD_am05wbs\n+00001f5e 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001f70 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001f74 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001f78 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000020ea 0000970a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+000020fa 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002162 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002172 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000021ca 0000980a R_ARM_THM_CALL 00000000 exp\n+0000223a 0000990a R_ARM_THM_CALL 00000000 log\n+000022c0 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000022e4 0000980a R_ARM_THM_CALL 00000000 exp\n+000022fc 0000990a R_ARM_THM_CALL 00000000 log\n+00002366 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00002448 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000244c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002450 00008f03 R_ARM_REL32 00000000 .rodata\n+00002454 00008f03 R_ARM_REL32 00000000 .rodata\n+00002836 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002850 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002854 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000029ba 0000970a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+000029c6 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002a2e 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002a3e 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002a96 0000980a R_ARM_THM_CALL 00000000 exp\n+00002b06 0000990a R_ARM_THM_CALL 00000000 log\n+00002b80 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00002ba8 0000980a R_ARM_THM_CALL 00000000 exp\n+00002bd2 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00002cf0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002cf4 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002cf8 00008f03 R_ARM_REL32 00000000 .rodata\n+00002cfc 00008f03 R_ARM_REL32 00000000 .rodata\n+0000307a 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003090 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003094 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000031fe 0000910a R_ARM_THM_CALL 00000000 cbrt\n+0000321e 0000990a R_ARM_THM_CALL 00000000 log\n+00003262 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003286 0000990a R_ARM_THM_CALL 00000000 log\n+000032ba 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000032ca 0000910a R_ARM_THM_CALL 00000000 cbrt\n+0000332e 0000990a R_ARM_THM_CALL 00000000 log\n+00003376 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003406 0000990a R_ARM_THM_CALL 00000000 log\n+00003446 0000910a R_ARM_THM_CALL 00000000 cbrt\n+000034d0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000034d4 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000034f8 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003530 0000980a R_ARM_THM_CALL 00000000 exp\n+00003b1a 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003b2a 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003b92 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003ba2 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003c44 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003c58 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003c5c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003dbe 0000970a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+00003dce 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003de2 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003e62 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003e72 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00003eb2 0000980a R_ARM_THM_CALL 00000000 exp\n+00003f4e 0000980a R_ARM_THM_CALL 00000000 exp\n+00003fae 0000990a R_ARM_THM_CALL 00000000 log\n+00004044 0000910a R_ARM_THM_CALL 00000000 cbrt\n+00004080 0000990a R_ARM_THM_CALL 00000000 log\n+00004140 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004144 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004148 00008f03 R_ARM_REL32 00000000 .rodata\n+00004160 0000980a R_ARM_THM_CALL 00000000 exp\n+000041bc 0000930a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+000045b0 00008f03 R_ARM_REL32 00000000 .rodata\n+00004818 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004828 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000482c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000048b0 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000048d0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000048d4 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000048d8 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000495c 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004978 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000497c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004980 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004a04 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004a20 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004a24 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004a28 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004aac 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004ac8 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004acc 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004ad0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004b54 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004b70 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004b74 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004b78 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004bfc 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004c18 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004c1c 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004c20 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004ca4 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004cc0 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004cc4 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004cc8 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e48 0000af0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+00004e54 0000af0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+00004e78 0000b00a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+00004e9c 0000b10a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n+00004f78 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004f90 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004fa8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004fc0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004fd8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004ff0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005008 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005020 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005038 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005050 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005068 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005080 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005098 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000050b0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000050c8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000050e0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000050f8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005110 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005128 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005140 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005158 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005170 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005188 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000051a0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000051b8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000051d0 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000051e8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005200 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005218 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005230 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005248 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005260 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005278 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005290 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000052a8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000052bc 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000544c 0000b30a R_ARM_THM_CALL 00000000 atan2\n+00005464 0000b40a R_ARM_THM_CALL 00000000 sincos\n+00005484 0000b40a R_ARM_THM_CALL 00000000 sincos\n+000054be 0000b30a R_ARM_THM_CALL 00000000 atan2\n+000054c6 0000b40a R_ARM_THM_CALL 00000000 sincos\n+00005648 0000961a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000564c 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005650 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005654 0000b51a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00005658 00005303 R_ARM_REL32 00000000 .LC8\n+0000565c 00005403 R_ARM_REL32 00000028 .LC9\n+00005660 00005503 R_ARM_REL32 00000048 .LC10\n+00005664 00008f03 R_ARM_REL32 00000000 .rodata\n+00005668 00009519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000566c 00005603 R_ARM_REL32 00000068 .LC11\n+00005670 00005703 R_ARM_REL32 0000006c .LC12\n+00005674 00005803 R_ARM_REL32 00000070 .LC13\n+00005678 00005903 R_ARM_REL32 00000078 .LC14\n+0000567c 00005a03 R_ARM_REL32 00000080 .LC15\n+00005680 00005b03 R_ARM_REL32 00000084 .LC16\n+00005684 00005c03 R_ARM_REL32 00000088 .LC17\n+00005688 00005d03 R_ARM_REL32 00000090 .LC18\n+0000568c 00005e03 R_ARM_REL32 00000098 .LC19\n+00005690 00005f03 R_ARM_REL32 000000a0 .LC20\n+00005694 00006003 R_ARM_REL32 000000a8 .LC21\n+00005698 00006103 R_ARM_REL32 000000b0 .LC22\n+0000569c 00006203 R_ARM_REL32 000000b4 .LC23\n+000056a0 00006303 R_ARM_REL32 000000b8 .LC24\n+000056a4 00006403 R_ARM_REL32 000000c0 .LC25\n+000056a8 00006503 R_ARM_REL32 000000c8 .LC26\n+000056ac 00006603 R_ARM_REL32 000000d0 .LC27\n+000056b0 00006703 R_ARM_REL32 000000d8 .LC28\n+000056b4 00006803 R_ARM_REL32 000000e0 .LC29\n+000056b8 00006903 R_ARM_REL32 000000e8 .LC30\n+000056bc 00006a03 R_ARM_REL32 000000f0 .LC31\n+000056c0 00006b03 R_ARM_REL32 000000fc .LC32\n+000056c4 00006c03 R_ARM_REL32 00000108 .LC33\n+000056c8 00006d03 R_ARM_REL32 00000114 .LC34\n+000056cc 00006e03 R_ARM_REL32 00000120 .LC35\n+000056d0 00006f03 R_ARM_REL32 0000012c .LC36\n+000056d4 00007003 R_ARM_REL32 00000138 .LC37\n+000056d8 00007103 R_ARM_REL32 00000144 .LC38\n+000056dc 00007203 R_ARM_REL32 00000150 .LC39\n+000056e0 00007303 R_ARM_REL32 0000015c .LC40\n+000056e4 00007403 R_ARM_REL32 00000168 .LC41\n+000056e8 00007503 R_ARM_REL32 00000174 .LC42\n+000056ec 00007603 R_ARM_REL32 00000180 .LC43\n+000056f0 00007703 R_ARM_REL32 00000188 .LC44\n+000056f4 00007803 R_ARM_REL32 00000190 .LC45\n+000056f8 00007903 R_ARM_REL32 00000198 .LC46\n+0000599c 0000af0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+000059a8 0000af0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+000059b8 0000b00a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+000059da 0000b10a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n+00005ab6 0000b00a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+00005ad8 0000b10a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n+00005bc8 00008f03 R_ARM_REL32 00000000 .rodata\n+00005bcc 00008f03 R_ARM_REL32 00000000 .rodata\n+00005c9c 0000b00a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+00005cc0 0000b10a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n+00005e2a 0000b00a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+00005e4c 0000b10a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n+00005f2e 0000940a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005f74 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00005f86 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00006160 00008f03 R_ARM_REL32 00000000 .rodata\n+00006164 00008f03 R_ARM_REL32 00000000 .rodata\n+00006168 00007a03 R_ARM_REL32 000001a0 .LC47\n+0000616c 00007b03 R_ARM_REL32 000001a4 .LC48\n+0000617c 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000618e 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000061d6 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000061e8 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00006230 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00006242 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000628a 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000629c 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000062d0 0000b60a R_ARM_THM_CALL 00000000 __gridxc_hybrids_MOD_hsexc\n+000062e4 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000062f6 0000b20a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000632a 0000b70a R_ARM_THM_CALL 00000000 __gridxc_hybrids_MOD_pbe0xc\n+00006344 0000b80a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00006358 0000b90a R_ARM_THM_CALL 00000000 malloc\n+00006370 0000ba0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000637c 0000bb0a R_ARM_THM_CALL 00000000 free\n+00006394 0000bb0a R_ARM_THM_CALL 00000000 free\n+0000639c 00007c03 R_ARM_REL32 000001a8 .LC49\n+000063a0 00007d03 R_ARM_REL32 000001b0 .LC50\n+000063a4 00007e03 R_ARM_REL32 000001b8 .LC51\n+000063a8 00007f03 R_ARM_REL32 000001bc .LC52\n+000063ac 00008003 R_ARM_REL32 000001c0 .LC53\n+000063b0 00008103 R_ARM_REL32 000001c4 .LC54\n+000063b4 00008203 R_ARM_REL32 000001c8 .LC55\n+000063b8 00008303 R_ARM_REL32 000001d0 .LC56\n+000063bc 00008403 R_ARM_REL32 000001d8 .LC57\n+000063c0 00008503 R_ARM_REL32 000001e0 .LC58\n+000063c4 00008603 R_ARM_REL32 000001e8 .LC59\n+000063c8 0000b51a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,8 +1,10 @@\n =@UUUUUU\n+G@UUUUUU\n+G?UUUUUU\n ggaxc: ERROR: invalid value of nSpin\n xc_func and xc_info not present\n GGAXC: Functional is not a GGA\n PBEJsJrLO\n pbejsjrlo\n PBEJSJRLO\n PBEJsJrHEG\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -5,1489 +5,1595 @@\n \n 00000000 <__gridxc_gga_MOD_pw86formx>:\n __gridxc_gga_MOD_pw86formx():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3664]\t@ 0xe50\n-\tldr\tr6, [pc, #920]\t@ (3b0 <__gridxc_gga_MOD_pw86formx+0x3b0>)\n-\tsub\tsp, #332\t@ 0x14c\n-\tldr\tr5, [pc, #920]\t@ (3b4 <__gridxc_gga_MOD_pw86formx+0x3b4>)\n+\tstr.w\tr0, [ip, #3672]\t@ 0xe58\n+\tldr\tr6, [pc, #976]\t@ (3e8 <__gridxc_gga_MOD_pw86formx+0x3e8>)\n+\tsub\tsp, #324\t@ 0x144\n+\tldr\tr5, [pc, #976]\t@ (3ec <__gridxc_gga_MOD_pw86formx+0x3ec>)\n \tmov\tr8, r2\n \tadd\tr6, pc\n \tmov\tsl, r0\n-\tldr\tr4, [sp, #432]\t@ 0x1b0\n+\tldr\tr4, [sp, #424]\t@ 0x1a8\n \tmov\tr9, r1\n-\tldrd\tfp, ip, [sp, #448]\t@ 0x1c0\n+\tldr.w\tip, [sp, #444]\t@ 0x1bc\n \tldr\tr5, [r6, r5]\n \tldr.w\tlr, [r4]\n \tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #324]\t@ 0x144\n+\tstr\tr5, [sp, #316]\t@ 0x13c\n \tmov.w\tr5, #0\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #436]\t@ 0x1b4\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #428]\t@ 0x1ac\n \tcmp.w\tlr, #1\n-\tldrd\tr5, r2, [sp, #440]\t@ 0x1b8\n-\tstr\tr2, [sp, #112]\t@ 0x70\n-\tvldr\td10, [r3]\n-\tbeq.w\t338 <__gridxc_gga_MOD_pw86formx+0x338>\n-\tadd\tr4, sp, #272\t@ 0x110\n-\tvldr\td16, [r3, #8]\n+\tldrd\tr5, r2, [sp, #432]\t@ 0x1b0\n+\tstr\tr2, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #440]\t@ 0x1b8\n+\tvldr\td7, [r3]\n+\tstr\tr2, [sp, #124]\t@ 0x7c\n+\tbeq.w\t362 <__gridxc_gga_MOD_pw86formx+0x362>\n+\tvldr\td5, [r3, #8]\n+\tadd\tr4, sp, #264\t@ 0x108\n+\tvstr\td7, [sp, #136]\t@ 0x88\n \tmov\tr7, r4\n+\tvldr\td6, [pc, #864]\t@ 3c0 <__gridxc_gga_MOD_pw86formx+0x3c0>\n+\tadd\tr6, sp, #288\t@ 0x120\n+\tvadd.f64\td7, d5, d7\n \tldr\tr0, [r5, #0]\n \tldr\tr1, [r5, #4]\n-\tadd\tr6, sp, #296\t@ 0x128\n \tldr\tr2, [r5, #8]\n-\tvadd.f64\td18, d16, d10\n \tldr\tr3, [r5, #12]\n+\tvcmpe.f64\td7, d6\n \tstmia\tr7!, {r0, r1, r2, r3}\n \tldr\tr0, [r5, #16]\n \tldr\tr1, [r5, #20]\n \tstmia\tr7!, {r0, r1}\n-\tvldr\td17, [pc, #804]\t@ 390 <__gridxc_gga_MOD_pw86formx+0x390>\n-\tvstr\td16, [sp, #152]\t@ 0x98\n-\tvstr\td10, [sp, #144]\t@ 0x90\n-\tldr\tr2, [r5, #32]\n-\tvmaxnm.f64\td16, d18, d17\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [sp, #144]\t@ 0x90\n \tldr\tr0, [r5, #24]\n \tldr\tr1, [r5, #28]\n+\tldr\tr2, [r5, #32]\n \tldr\tr3, [r5, #36]\t@ 0x24\n \tstmia\tr6!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tldr\tr0, [r5, #40]\t@ 0x28\n \tldr\tr1, [r5, #44]\t@ 0x2c\n \tstmia\tr6!, {r0, r1}\n-\tvstr\td16, [sp, #128]\t@ 0x80\n-\tvldr\td17, [sp, #280]\t@ 0x118\n-\tvmov.f64\td24, #62\t@ 0x41f00000 30.0\n-\tvldr\td16, [sp, #304]\t@ 0x130\n-\tvmov.f64\td23, #46\t@ 0x41700000 15.0\n-\tvldr\td22, [sp, #272]\t@ 0x110\n-\tadd\tr7, sp, #176\t@ 0xb0\n-\tvldr\td21, [sp, #296]\t@ 0x128\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td19, [sp, #288]\t@ 0x120\n-\tvfma.f64\td17, d22, d22\n-\tvldr\td18, [sp, #312]\t@ 0x138\n-\tvfma.f64\td16, d21, d21\n-\tvldr\td20, [sl]\n-\tvldr\td11, [r9]\n-\tvmov.f64\td21, #16\t@ 0x40800000 4.0\n-\tvldr\td12, [r8]\n-\tvmov.f64\td22, #24\t@ 0x40c00000 6.0\n-\tvfma.f64\td17, d19, d19\n-\tvmul.f64\td24, d20, d24\n-\tvfma.f64\td16, d18, d18\n-\tvmul.f64\td20, d20, d23\n-\tvmul.f64\td19, d11, d21\n-\tvldr\td25, [pc, #676]\t@ 390 <__gridxc_gga_MOD_pw86formx+0x390>\n-\tadd.w\tr8, sp, #144\t@ 0x90\n-\tadd.w\tsl, sp, #192\t@ 0xc0\n-\tadd\tr6, sp, #208\t@ 0xd0\n-\tadd\tr5, sp, #224\t@ 0xe0\n-\tvstr\td20, [sp, #80]\t@ 0x50\n-\tvmul.f64\td20, d12, d22\n-\tvstr\td19, [sp, #96]\t@ 0x60\n-\tvmov.i64\td19, #0x0000000000000000\n-\tadd.w\tr9, sp, #160\t@ 0xa0\n-\tadd\tr3, sp, #136\t@ 0x88\n-\tvsqrt.f64\td18, d17\n-\tstr.w\tr9, [sp, #68]\t@ 0x44\n-\tvsqrt.f64\td17, d16\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tstrd\tlr, fp, [sp, #116]\t@ 0x74\n-\tstr.w\tip, [sp, #124]\t@ 0x7c\n-\tvstr\td24, [sp, #72]\t@ 0x48\n-\tvstr\td20, [sp, #88]\t@ 0x58\n-\tvstr\td18, [sp, #192]\t@ 0xc0\n-\tvstr\td17, [sp, #200]\t@ 0xc8\n-\tvldmia\tr8!, {d8}\n-\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n-\tvldmia\tsl!, {d14}\n-\tmov\tfp, r7\n-\tvldr\td16, [pc, #596]\t@ 398 <__gridxc_gga_MOD_pw86formx+0x398>\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tadd.w\tfp, sp, #184\t@ 0xb8\n+\tvldr\td3, [sp, #264]\t@ 0x108\n+\tadd\tr6, sp, #200\t@ 0xc8\n+\tvldr\td7, [sp, #296]\t@ 0x128\n+\tadd\tr5, sp, #216\t@ 0xd8\n+\tvmul.f64\td6, d6, d6\n+\tvldr\td4, [sp, #280]\t@ 0x118\n+\tvmla.f64\td6, d3, d3\n+\tvldr\td3, [sp, #288]\t@ 0x120\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [sl]\n+\tvldr\td1, [r8]\n+\tadd.w\tr8, sp, #168\t@ 0xa8\n+\tvmla.f64\td7, d3, d3\n+\tvmov.f64\td3, #46\t@ 0x41700000 15.0\n+\tvmla.f64\td6, d4, d4\n+\tvldr\td4, [sp, #304]\t@ 0x130\n+\tvldr\td2, [r9]\n+\tadd.w\tr9, sp, #136\t@ 0x88\n+\tvldr\td12, [pc, #724]\t@ 3c0 <__gridxc_gga_MOD_pw86formx+0x3c0>\n+\tadd.w\tsl, sp, #152\t@ 0x98\n+\tvmla.f64\td7, d4, d4\n+\tvmov.f64\td4, #62\t@ 0x41f00000 30.0\n+\tadd\tr3, sp, #128\t@ 0x80\n+\tstr.w\tsl, [sp, #44]\t@ 0x2c\n+\tvmul.f64\td4, d5, d4\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tstr.w\tlr, [sp, #108]\t@ 0x6c\n+\tstr.w\tip, [sp, #120]\t@ 0x78\n+\tvstr\td2, [sp, #48]\t@ 0x30\n+\tvstr\td4, [sp, #64]\t@ 0x40\n+\tvsqrt.f64\td4, d6\n+\tvmul.f64\td6, d5, d3\n+\tvstr\td1, [sp, #56]\t@ 0x38\n+\tvstr\td6, [sp, #72]\t@ 0x48\n+\tvmov.f64\td6, #24\t@ 0x40c00000 6.0\n+\tvmul.f64\td6, d1, d6\n+\tvstr\td6, [sp, #80]\t@ 0x50\n+\tvsqrt.f64\td6, d7\n+\tvmov.f64\td7, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td7, d2, d7\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvstr\td4, [sp, #184]\t@ 0xb8\n+\tvstr\td6, [sp, #192]\t@ 0xc0\n+\tvldr\td6, [pc, #636]\t@ 3c8 <__gridxc_gga_MOD_pw86formx+0x3c8>\n+\tvstr\td6, [sp, #8]\n+\tvldmia\tr9!, {d8}\n+\tmov\tr7, r8\n+\tvldmia\tfp!, {d10}\n \tadds\tr4, #24\n-\tvadd.f64\td8, d8, d8\n-\tvstr\td19, [sp, #56]\t@ 0x38\n-\tvadd.f64\td14, d14, d14\n-\tvstr\td25, [sp, #48]\t@ 0x30\n+\tvldr\td7, [pc, #624]\t@ 3d0 <__gridxc_gga_MOD_pw86formx+0x3d0>\n \tadds\tr5, #24\n-\tvmaxnm.f64\td8, d8, d25\n-\tvmaxnm.f64\td14, d14, d25\n-\tvmul.f64\td0, d8, d16\n-\tvstmia\tr7!, {d8}\n+\tvadd.f64\td8, d8, d8\n+\tvadd.f64\td10, d10, d10\n+\tvcmpe.f64\td8, d12\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td10, d12\n+\tit\tlt\n+\tvmovlt.f64\td8, d12\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d8, d7\n+\tvstmia\tr8!, {d8}\n+\tit\tlt\n+\tvmovlt.f64\td10, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td16, d14, d10\n-\tvmul.f64\td23, d8, d0\n-\tvmov.f64\td22, #112\t@ 0x3f800000 1.0\n-\tvldr\td1, [pc, #548]\t@ 3a0 <__gridxc_gga_MOD_pw86formx+0x3a0>\n-\tvstr\td0, [sp, #40]\t@ 0x28\n-\tvstr\td22, [sp, #8]\n-\tvdiv.f64\td9, d16, d23\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvstr\td23, [sp, #32]\n-\tvmul.f64\td18, d9, d9\n-\tvmul.f64\td20, d9, d18\n-\tvfma.f64\td16, d18, d11\n-\tvstr\td18, [sp, #16]\n-\tvmul.f64\td13, d20, d20\n-\tvstr\td20, [sp, #24]\n-\tvmul.f64\td13, d13, d12\n-\tvfma.f64\td13, d18, d16\n-\tvadd.f64\td13, d13, d22\n-\tvmov.f64\td0, d13\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td6, d8, d0\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td1, [pc, #564]\t@ 3d8 <__gridxc_gga_MOD_pw86formx+0x3d8>\n+\tvmul.f64\td5, d10, d5\n+\tvstr\td0, [sp, #16]\n+\tvstr\td6, [sp, #32]\n+\tvstr\td7, [sp, #24]\n+\tvdiv.f64\td13, d5, d6\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvmul.f64\td14, d13, d13\n+\tvmul.f64\td15, d13, d14\n+\tvmla.f64\td5, d14, d4\n+\tvldr\td4, [sp, #56]\t@ 0x38\n+\tvmul.f64\td9, d15, d15\n+\tvmul.f64\td9, d9, d4\n+\tvmla.f64\td9, d5, d14\n+\tvadd.f64\td9, d9, d7\n+\tvmov.f64\td0, d9\n \tbl\t0 \n R_ARM_THM_CALL\tpow\n-\tldr\tr1, [pc, #504]\t@ (3b8 <__gridxc_gga_MOD_pw86formx+0x3b8>)\n-\tvmov.f64\td15, d0\n+\tldr\tr1, [pc, #520]\t@ (3f0 <__gridxc_gga_MOD_pw86formx+0x3f0>)\n+\tldrd\tr0, r3, [sp, #96]\t@ 0x60\n \tstr\tr6, [sp, #0]\n-\tldrd\tr0, r3, [sp, #104]\t@ 0x68\n-\tmov\tr2, fp\n+\tmov\tr2, r7\n \tadd\tr1, pc\n-\tadds\tr6, #8\n+\tvmov.f64\td11, d0\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td22, [sp, #8]\n-\tvldr\td16, [pc, #452]\t@ 3a0 <__gridxc_gga_MOD_pw86formx+0x3a0>\n-\tvldr\td17, [sp, #88]\t@ 0x58\n-\tvdiv.f64\td27, d22, d8\n-\tvldr\td18, [sp, #16]\n-\tvmul.f64\td28, d15, d16\n-\tvldr\td21, [pc, #440]\t@ 3a8 <__gridxc_gga_MOD_pw86formx+0x3a8>\n-\tvdiv.f64\td16, d22, d14\n-\tvldr\td22, [sp, #96]\t@ 0x60\n-\tvfma.f64\td22, d18, d17\n-\tvldr\td17, [sp, #40]\t@ 0x28\n-\tvldr\td23, [sp, #32]\n-\tvdiv.f64\td29, d28, d13\n-\tvldr\td18, [r4, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td21, d17, d21\n-\tvldr\td28, [r4, #-8]\n-\tvldr\td17, [r4, #-16]\n-\tvldr\td31, [sp, #136]\t@ 0x88\n-\tvadd.f64\td18, d18, d18\n-\tvldr\td20, [sp, #24]\n-\tvadd.f64\td28, d28, d28\n-\tvdiv.f64\td30, d21, d23\n-\tvadd.f64\td17, d17, d17\n-\tvmul.f64\td8, d8, d31\n-\tvldr\td19, [sp, #72]\t@ 0x48\n-\tvmul.f64\td22, d22, d20\n-\tvldr\td26, [r6, #-8]\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvfma.f64\td22, d9, d19\n-\tvldr\td19, [sp, #56]\t@ 0x38\n-\tvmul.f64\td18, d18, d8\n-\tvmul.f64\td17, d17, d8\n-\tvmul.f64\td28, d28, d8\n-\tvmul.f64\td20, d8, d9\n-\tvfma.f64\td19, d8, d15\n-\tcmp\tr8, r3\n-\tvldr\td25, [sp, #48]\t@ 0x30\n-\tvmul.f64\td9, d9, d16\n-\tvmul.f64\td18, d18, d16\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td16, d28, d16\n-\tvmul.f64\td22, d29, d22\n-\tvmul.f64\td18, d18, d9\n-\tvmul.f64\td17, d17, d9\n-\tvmul.f64\td16, d16, d9\n-\tvadd.f64\td30, d30, d27\n-\tvmul.f64\td18, d18, d22\n-\tvmul.f64\td17, d17, d22\n-\tvmul.f64\td16, d16, d22\n-\tvmul.f64\td20, d20, d30\n-\tvstr\td18, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tvnmul.f64\td22, d22, d20\n-\tvfma.f64\td22, d26, d15\n-\tvstmia\tr9!, {d22}\n-\tbne.w\t134 <__gridxc_gga_MOD_pw86formx+0x134>\n-\tvmul.f64\td19, d19, d10\n-\tvldr\td16, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tldrd\tlr, fp, [sp, #116]\t@ 0x74\n-\tvdiv.f64\td16, d19, d16\n-\tldr.w\tip, [sp, #124]\t@ 0x7c\n+\tvldr\td6, [sp, #16]\n+\tadds\tr6, #8\n+\tvldr\td2, [pc, #476]\t@ 3e0 <__gridxc_gga_MOD_pw86formx+0x3e0>\n+\tvldr\td7, [sp, #24]\n+\tvldr\td1, [sp, #88]\t@ 0x58\n+\tvmul.f64\td2, d6, d2\n+\tvldr\td6, [sp, #32]\n+\tvdiv.f64\td5, d7, d10\n+\tvldr\td3, [r6, #-8]\n+\tvdiv.f64\td4, d7, d8\n+\tvldr\td7, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tvmla.f64\td1, d14, d7\n+\tcmp\tr9, r3\n+\tvdiv.f64\td7, d2, d6\n+\tvldr\td2, [sp, #8]\n+\tvadd.f64\td6, d7, d4\n+\tvldr\td7, [pc, #412]\t@ 3d8 <__gridxc_gga_MOD_pw86formx+0x3d8>\n+\tvmul.f64\td7, d11, d7\n+\tvdiv.f64\td4, d7, d9\n+\tvldr\td7, [sp, #128]\t@ 0x80\n+\tvmul.f64\td7, d8, d7\n+\tvmla.f64\td2, d7, d11\n+\tvstr\td2, [sp, #8]\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvmul.f64\td0, d13, d2\n+\tvldr\td2, [r4, #-16]\n+\tvmla.f64\td0, d1, d15\n+\tvldr\td1, [r4, #-24]\t@ 0xffffffe8\n+\tvadd.f64\td2, d2, d2\n+\tvadd.f64\td1, d1, d1\n+\tvmul.f64\td2, d2, d7\n+\tvmul.f64\td1, d1, d7\n+\tvmul.f64\td0, d0, d4\n+\tvldr\td4, [r4, #-8]\n+\tvmul.f64\td2, d2, d5\n+\tvmul.f64\td1, d1, d5\n+\tvadd.f64\td4, d4, d4\n+\tvmul.f64\td4, d4, d7\n+\tvmul.f64\td7, d7, d13\n+\tvmul.f64\td7, d6, d7\n+\tvmul.f64\td4, d4, d5\n+\tvmul.f64\td6, d13, d5\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td2, d2, d6\n+\tvmul.f64\td4, d4, d6\n+\tvnmls.f64\td7, d11, d3\n+\tvmul.f64\td1, d1, d0\n+\tvmul.f64\td2, d2, d0\n+\tvmul.f64\td4, d4, d0\n+\tvstr\td1, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td2, [r5, #-16]\n+\tvstr\td4, [r5, #-8]\n+\tvstmia\tsl!, {d7}\n+\tbne.w\t150 <__gridxc_gga_MOD_pw86formx+0x150>\n+\tvldr\td7, [sp, #8]\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tldr.w\tlr, [sp, #108]\t@ 0x6c\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #112]\t@ 0x70\n+\tldr.w\tip, [sp, #120]\t@ 0x78\n \tcmp.w\tlr, #0\n-\tvstr\td16, [r3]\n-\tble.n\t31a <__gridxc_gga_MOD_pw86formx+0x31a>\n-\tldrd\tr2, r3, [sp, #160]\t@ 0xa0\n-\tstrd\tr2, r3, [fp]\n-\tldrd\tr2, r3, [sp, #224]\t@ 0xe0\n+\tvdiv.f64\td6, d7, d6\n+\tvstr\td6, [r3]\n+\tble.n\t344 <__gridxc_gga_MOD_pw86formx+0x344>\n+\tldr\tr1, [sp, #124]\t@ 0x7c\n+\tcmp.w\tlr, #1\n+\tldrd\tr2, r3, [sp, #152]\t@ 0x98\n+\tstrd\tr2, r3, [r1]\n+\tldrd\tr2, r3, [sp, #216]\t@ 0xd8\n \tstrd\tr2, r3, [ip]\n-\tldrd\tr2, r3, [sp, #232]\t@ 0xe8\n+\tldrd\tr2, r3, [sp, #224]\t@ 0xe0\n \tstrd\tr2, r3, [ip, #8]\n-\tldrd\tr2, r3, [sp, #240]\t@ 0xf0\n-\tcmp.w\tlr, #1\n+\tldrd\tr2, r3, [sp, #232]\t@ 0xe8\n \tstrd\tr2, r3, [ip, #16]\n-\tbeq.n\t31a <__gridxc_gga_MOD_pw86formx+0x31a>\n-\tldrd\tr2, r3, [sp, #168]\t@ 0xa8\n-\tstrd\tr2, r3, [fp, #8]\n-\tldrd\tr2, r3, [sp, #256]\t@ 0x100\n+\tbeq.n\t344 <__gridxc_gga_MOD_pw86formx+0x344>\n+\tldrd\tr2, r3, [sp, #160]\t@ 0xa0\n+\tstrd\tr2, r3, [r1, #8]\n+\tldrd\tr2, r3, [sp, #248]\t@ 0xf8\n \tstrd\tr2, r3, [ip, #32]\n-\tldrd\tr0, r1, [sp, #248]\t@ 0xf8\n+\tldrd\tr0, r1, [sp, #240]\t@ 0xf0\n \tstrd\tr0, r1, [ip, #24]\n-\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n+\tldrd\tr2, r3, [sp, #256]\t@ 0x100\n \tstrd\tr2, r3, [ip, #40]\t@ 0x28\n-\tldr\tr2, [pc, #160]\t@ (3bc <__gridxc_gga_MOD_pw86formx+0x3bc>)\n-\tldr\tr3, [pc, #148]\t@ (3b4 <__gridxc_gga_MOD_pw86formx+0x3b4>)\n+\tldr\tr2, [pc, #172]\t@ (3f4 <__gridxc_gga_MOD_pw86formx+0x3f4>)\n+\tldr\tr3, [pc, #164]\t@ (3ec <__gridxc_gga_MOD_pw86formx+0x3ec>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #324]\t@ 0x144\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t388 <__gridxc_gga_MOD_pw86formx+0x388>\n-\tadd\tsp, #332\t@ 0x14c\n+\tbne.n\t3bc <__gridxc_gga_MOD_pw86formx+0x3bc>\n+\tadd\tsp, #324\t@ 0x144\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td18, [r5]\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n-\tvldr\td17, [r5, #8]\n-\tadd\tr4, sp, #272\t@ 0x110\n-\tvldr\td16, [r5, #16]\n-\tvmul.f64\td20, d10, d19\n-\tvldr\td21, [pc, #64]\t@ 390 <__gridxc_gga_MOD_pw86formx+0x390>\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmaxnm.f64\td19, d10, d21\n-\tvstr\td20, [sp, #144]\t@ 0x90\n-\tvstr\td20, [sp, #152]\t@ 0x98\n-\tvstr\td18, [sp, #272]\t@ 0x110\n-\tvstr\td18, [sp, #296]\t@ 0x128\n-\tvstr\td19, [sp, #128]\t@ 0x80\n-\tvstr\td17, [sp, #280]\t@ 0x118\n-\tvstr\td17, [sp, #304]\t@ 0x130\n-\tvstr\td16, [sp, #288]\t@ 0x120\n-\tvstr\td16, [sp, #312]\t@ 0x138\n-\tb.n\t8e <__gridxc_gga_MOD_pw86formx+0x8e>\n+\tvldr\td2, [pc, #92]\t@ 3c0 <__gridxc_gga_MOD_pw86formx+0x3c0>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r5]\n+\tadd\tr4, sp, #264\t@ 0x108\n+\tvldr\td5, [r5, #8]\n+\tvmul.f64\td1, d7, d3\n+\tvcmpe.f64\td7, d2\n+\tvldr\td6, [r5, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvstr\td1, [sp, #136]\t@ 0x88\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td1, [sp, #144]\t@ 0x90\n+\tvstr\td4, [sp, #264]\t@ 0x108\n+\tvstr\td4, [sp, #288]\t@ 0x120\n+\tvstr\td5, [sp, #272]\t@ 0x110\n+\tvstr\td5, [sp, #296]\t@ 0x128\n+\tit\tlt\n+\tvmovlt.f64\td7, d2\n+\tvstr\td6, [sp, #280]\t@ 0x118\n+\tvstr\td6, [sp, #304]\t@ 0x130\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tb.n\t9c <__gridxc_gga_MOD_pw86formx+0x9c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n+\t...\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0x11111111\n \t.word\t0x3fb11111\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x00000390\n+\t.word\t0x000003c8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000001e8\n+\t.word\t0x000001fc\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000009a\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000003c0 <__gridxc_gga_MOD_pbeformxc>:\n+000003f8 <__gridxc_gga_MOD_pbeformxc>:\n __gridxc_gga_MOD_pbeformxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3376]\t@ 0xd30\n-\tldr.w\tr6, [pc, #1160]\t@ 860 <__gridxc_gga_MOD_pbeformxc+0x4a0>\n-\tsub.w\tsp, sp, #620\t@ 0x26c\n-\tldr.w\tr5, [pc, #1156]\t@ 864 <__gridxc_gga_MOD_pbeformxc+0x4a4>\n+\tstr.w\tr0, [ip, #3384]\t@ 0xd38\n+\tldr.w\tr6, [pc, #1136]\t@ 880 <__gridxc_gga_MOD_pbeformxc+0x488>\n+\tsub.w\tsp, sp, #612\t@ 0x264\n+\tldr.w\tr5, [pc, #1132]\t@ 884 <__gridxc_gga_MOD_pbeformxc+0x48c>\n \tmov\tr7, r0\n \tadd\tr6, pc\n-\tldr\tr4, [sp, #720]\t@ 0x2d0\n+\tldr\tr4, [sp, #712]\t@ 0x2c8\n \tldr\tr5, [r6, r5]\n \tmov\tr6, r2\n-\tldr\tr2, [sp, #724]\t@ 0x2d4\n+\tldr\tr2, [sp, #716]\t@ 0x2cc\n \tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #612]\t@ 0x264\n+\tstr\tr5, [sp, #604]\t@ 0x25c\n \tmov.w\tr5, #0\n \tmov\tr5, r1\n \tstr\tr3, [sp, #80]\t@ 0x50\n-\tldrd\tr3, r1, [sp, #728]\t@ 0x2d8\n-\tstr\tr1, [sp, #152]\t@ 0x98\n-\tldr\tr1, [sp, #736]\t@ 0x2e0\n-\tstr\tr1, [sp, #156]\t@ 0x9c\n-\tldr\tr1, [sp, #740]\t@ 0x2e4\n+\tldrd\tr3, r1, [sp, #720]\t@ 0x2d0\n+\tstr\tr1, [sp, #168]\t@ 0xa8\n+\tldr\tr1, [sp, #728]\t@ 0x2d8\n+\tstr\tr1, [sp, #172]\t@ 0xac\n+\tldr\tr1, [sp, #732]\t@ 0x2dc\n \tldr\tr4, [r4, #0]\n-\tstr\tr1, [sp, #348]\t@ 0x15c\n-\tldr\tr1, [sp, #744]\t@ 0x2e8\n+\tstr\tr1, [sp, #340]\t@ 0x154\n+\tldr\tr1, [sp, #736]\t@ 0x2e0\n \tcmp\tr4, #1\n-\tstr\tr1, [sp, #352]\t@ 0x160\n-\tldrd\tr8, r1, [sp, #748]\t@ 0x2ec\n-\tstr\tr4, [sp, #132]\t@ 0x84\n-\tvldr\td16, [r2]\n-\tstr\tr1, [sp, #356]\t@ 0x164\n-\tbeq.w\tafa <__gridxc_gga_MOD_pbeformxc+0x73a>\n-\tvldr\td17, [r3, #16]\n-\tvldr\td23, [r2, #8]\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvstr\td16, [sp, #392]\t@ 0x188\n-\tvadd.f64\td9, d23, d16\n-\tvldr\td20, [r3, #8]\n-\tvadd.f64\td16, d17, d18\n-\tvldr\td19, [r3, #32]\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #24]\n-\tvldr\td26, [pc, #984]\t@ 820 <__gridxc_gga_MOD_pbeformxc+0x460>\n-\tvadd.f64\td24, d19, d20\n-\tvstr\td16, [sp, #120]\t@ 0x78\n-\tvmov.f64\td16, d19\n-\tvadd.f64\td25, d21, d22\n-\tvstr\td17, [sp, #576]\t@ 0x240\n-\tvmaxnm.f64\td9, d9, d26\n-\tvmov.f64\td17, d20\n-\tvstr\td23, [sp, #400]\t@ 0x190\n-\tvstr\td22, [sp, #560]\t@ 0x230\n-\tvstr\td21, [sp, #584]\t@ 0x248\n-\tvstr\td25, [sp, #488]\t@ 0x1e8\n-\tvstr\td20, [sp, #568]\t@ 0x238\n-\tvstr\td19, [sp, #592]\t@ 0x250\n-\tvstr\td24, [sp, #496]\t@ 0x1f0\n-\tvldr\td19, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td23, [sp, #488]\t@ 0x1e8\n-\tvfma.f64\td16, d21, d21\n-\tvmul.f64\td17, d17, d17\n-\tvldr\td21, [sp, #120]\t@ 0x78\n-\tvstr\td19, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td19, d19, d19\n-\tvfma.f64\td19, d23, d23\n-\tvfma.f64\td17, d22, d22\n-\tvldr\td20, [sp, #576]\t@ 0x240\n-\tvfma.f64\td16, d18, d18\n-\tvstr\td18, [sp, #600]\t@ 0x258\n-\tadd\tr4, sp, #392\t@ 0x188\n-\tvldr\td15, [pc, #868]\t@ 820 <__gridxc_gga_MOD_pbeformxc+0x460>\n-\tadd\tr2, sp, #376\t@ 0x178\n-\tvfma.f64\td17, d20, d20\n-\tldr\tr3, [pc, #932]\t@ (868 <__gridxc_gga_MOD_pbeformxc+0x4a8>)\n+\tstr\tr1, [sp, #344]\t@ 0x158\n+\tldrd\tr8, r1, [sp, #740]\t@ 0x2e4\n+\tstr\tr4, [sp, #156]\t@ 0x9c\n+\tvldr\td7, [r2]\n+\tstr\tr1, [sp, #348]\t@ 0x15c\n+\tbeq.w\tbea <__gridxc_gga_MOD_pbeformxc+0x7f2>\n+\tvldr\td1, [r2, #8]\n+\tvldr\td6, [pc, #988]\t@ 838 <__gridxc_gga_MOD_pbeformxc+0x440>\n+\tvldr\td5, [r3]\n+\tvadd.f64\td12, d1, d7\n+\tvldr\td2, [r3, #24]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #32]\n+\tvadd.f64\td0, d2, d5\n+\tvstr\td7, [sp, #384]\t@ 0x180\n+\tvcmpe.f64\td12, d6\n+\tvldr\td7, [r3, #16]\n+\tvstr\td5, [sp, #552]\t@ 0x228\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvstr\td1, [sp, #392]\t@ 0x188\n+\tvadd.f64\td1, d4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td4, [sp, #584]\t@ 0x248\n+\tvadd.f64\td4, d7, d5\n+\tvstr\td7, [sp, #568]\t@ 0x238\n+\tvmov.f64\td7, d3\n+\tvstr\td0, [sp, #480]\t@ 0x1e0\n+\tvstr\td1, [sp, #488]\t@ 0x1e8\n+\tvstr\td2, [sp, #576]\t@ 0x240\n+\tit\tlt\n+\tvmovlt.f64\td12, d6\n+\tvmov.f64\td1, d4\n+\tvstr\td3, [sp, #560]\t@ 0x230\n+\tvstr\td4, [sp, #128]\t@ 0x80\n+\tvldr\td3, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td4, [sp, #552]\t@ 0x228\n+\tadd\tr4, sp, #384\t@ 0x180\n+\tvldr\td2, [sp, #480]\t@ 0x1e0\n+\tadd\tr2, sp, #368\t@ 0x170\n+\tvldr\td6, [sp, #584]\t@ 0x248\n \tmov\tr1, r4\n-\tvstr\td23, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td7, d4, d4\n+\tvstr\td3, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td4, d3, d3\n+\tvldr\td3, [sp, #576]\t@ 0x240\n+\tvmla.f64\td4, d2, d2\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td5, [sp, #592]\t@ 0x250\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td6, d3, d3\n+\tvldr\td13, [pc, #820]\t@ 838 <__gridxc_gga_MOD_pbeformxc+0x440>\n+\tldr\tr3, [pc, #896]\t@ (888 <__gridxc_gga_MOD_pbeformxc+0x490>)\n+\tadd.w\tfp, sp, #432\t@ 0x1b0\n+\tvmla.f64\td4, d1, d1\n+\tvstr\td2, [sp, #216]\t@ 0xd8\n \tadd\tr3, pc\n \tstr\tr3, [sp, #84]\t@ 0x54\n+\tvmla.f64\td6, d5, d5\n \tmov\tr0, r3\n-\tadd\tr3, sp, #456\t@ 0x1c8\n-\tvmov.f64\td18, d19\n \tadds\tr0, #4\n-\tvfma.f64\td18, d21, d21\n-\tvstr\td21, [sp, #504]\t@ 0x1f8\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvldr\td14, [pc, #832]\t@ 828 <__gridxc_gga_MOD_pbeformxc+0x468>\n-\tadd.w\tfp, sp, #440\t@ 0x1b8\n-\tadd.w\tr9, sp, #424\t@ 0x1a8\n-\tvsqrt.f64\td19, d17\n-\tadd.w\tsl, sp, #408\t@ 0x198\n-\tvsqrt.f64\td17, d16\n-\tvsqrt.f64\td16, d18\n-\tvstr\td19, [sp, #440]\t@ 0x1b8\n-\tvstr\td17, [sp, #448]\t@ 0x1c0\n-\tvmaxnm.f64\td8, d16, d15\n-\tvstr\td8, [sp, #224]\t@ 0xe0\n+\tadd\tr3, sp, #448\t@ 0x1c0\n+\tvstr\td1, [sp, #496]\t@ 0x1f0\n+\tadd.w\tr9, sp, #416\t@ 0x1a0\n+\tadd.w\tsl, sp, #400\t@ 0x190\n+\tvsqrt.f64\td5, d4\n+\tvsqrt.f64\td4, d6\n+\tvldr\td6, [sp, #568]\t@ 0x238\n+\tvmla.f64\td7, d6, d6\n+\tvsqrt.f64\td6, d7\n+\tvcmpe.f64\td5, d13\n+\tvstr\td4, [sp, #440]\t@ 0x1b8\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td10, d13\n+\tvmovge.f64\td10, d5\n+\tvstr\td6, [sp, #432]\t@ 0x1b0\n+\tvstr\td10, [sp, #232]\t@ 0xe8\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td16, [pc, #792]\t@ 830 <__gridxc_gga_MOD_pbeformxc+0x470>\n-\tvmul.f64\td0, d9, d16\n+\tvldr\td7, [pc, #728]\t@ 840 <__gridxc_gga_MOD_pbeformxc+0x448>\n+\tvmul.f64\td0, d12, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [pc, #788]\t@ 838 <__gridxc_gga_MOD_pbeformxc+0x478>\n-\tvdiv.f64\td21, d12, d9\n-\tvldr\td20, [sp, #400]\t@ 0x190\n-\tvldr\td16, [sp, #392]\t@ 0x188\n-\tvmul.f64\td17, d0, d17\n-\tvldr\td19, [pc, #776]\t@ 840 <__gridxc_gga_MOD_pbeformxc+0x480>\n-\tvldr\td18, [pc, #780]\t@ 848 <__gridxc_gga_MOD_pbeformxc+0x488>\n-\tvsub.f64\td16, d16, d20\n-\tvstr\td0, [sp, #232]\t@ 0xe8\n-\tvsqrt.f64\td11, d17\n-\tvmul.f64\td16, d16, d21\n-\tvstr\td21, [sp, #144]\t@ 0x90\n-\tvmaxnm.f64\td16, d16, d19\n-\tvstr\td11, [sp, #240]\t@ 0xf0\n-\tvminnm.f64\td16, d16, d18\n-\tvadd.f64\td17, d16, d12\n-\tvsub.f64\td10, d12, d16\n-\tvmov.f64\td0, d17\n-\tvstr\td17, [sp, #368]\t@ 0x170\n-\tvstr\td10, [sp, #248]\t@ 0xf8\n+\tvldr\td6, [sp, #392]\t@ 0x188\n+\tvldr\td7, [sp, #384]\t@ 0x180\n+\tvstr\td0, [sp, #240]\t@ 0xf0\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d8, d12\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvldr\td6, [pc, #696]\t@ 848 <__gridxc_gga_MOD_pbeformxc+0x450>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvldr\td6, [pc, #688]\t@ 850 <__gridxc_gga_MOD_pbeformxc+0x458>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvldr\td6, [pc, #676]\t@ 858 <__gridxc_gga_MOD_pbeformxc+0x460>\n+\tvmul.f64\td6, d0, d6\n+\tvsub.f64\td9, d8, d7\n+\tvsqrt.f64\td14, d6\n+\tvadd.f64\td6, d7, d8\n+\tvstr\td9, [sp, #256]\t@ 0x100\n+\tvmov.f64\td0, d6\n+\tvstr\td6, [sp, #360]\t@ 0x168\n+\tvstr\td14, [sp, #248]\t@ 0xf8\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, d0\n-\tvmov.f64\td0, d10\n-\tvmov.f64\td13, d16\n-\tvstr\td16, [sp, #264]\t@ 0x108\n+\tvmov.f64\td11, d0\n+\tvstr\td0, [sp, #264]\t@ 0x108\n+\tvmov.f64\td0, d9\n+\tvldr\td9, [pc, #632]\t@ 860 <__gridxc_gga_MOD_pbeformxc+0x468>\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td20, d0, d0\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvldr\td10, [sp, #376]\t@ 0x178\n-\tvmul.f64\td17, d9, d11\n-\tvstr\td0, [sp, #288]\t@ 0x120\n-\tvfma.f64\td20, d13, d13\n-\tvmul.f64\td19, d8, d16\n-\tvmul.f64\td18, d10, d14\n-\tvstr\td10, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td16, d20, d16\n-\tvstr\td20, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td13, d16, d16\n-\tvmul.f64\td17, d17, d16\n-\tvdiv.f64\td8, d19, d17\n-\tvmul.f64\td13, d13, d16\n-\tvdiv.f64\td16, d18, d13\n-\tvstr\td8, [sp, #256]\t@ 0x100\n-\tvneg.f64\td0, d16\n-\tvstr\td16, [sp, #272]\t@ 0x110\n+\tvmul.f64\td6, d12, d14\n+\tvstr\td0, [sp, #296]\t@ 0x128\n+\tvmul.f64\td7, d11, d11\n+\tvldr\td11, [sp, #368]\t@ 0x170\n+\tvmla.f64\td7, d0, d0\n+\tvstr\td11, [sp, #112]\t@ 0x70\n+\tvmov.f64\td4, d7\n+\tvstr\td7, [sp, #176]\t@ 0xb0\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td5, d10, d7\n+\tvmul.f64\td7, d4, d7\n+\tvmul.f64\td10, d7, d7\n+\tvmul.f64\td6, d6, d7\n+\tvdiv.f64\td14, d5, d6\n+\tvmul.f64\td10, d10, d7\n+\tvmul.f64\td7, d11, d9\n+\tvdiv.f64\td7, d7, d10\n+\tvstr\td14, [sp, #136]\t@ 0x88\n+\tvneg.f64\td0, d7\n+\tvstr\td7, [sp, #272]\t@ 0x110\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td16, [r7]\n-\tvsub.f64\td19, d0, d12\n-\tvmul.f64\td18, d8, d8\n-\tvldr\td17, [pc, #616]\t@ 850 <__gridxc_gga_MOD_pbeformxc+0x490>\n-\tadd\tr7, sp, #472\t@ 0x1d8\n-\tvmul.f64\td16, d16, d14\n+\tvldr\td7, [r7]\n+\tvsub.f64\td4, d0, d8\n+\tvmul.f64\td5, d14, d14\n+\tvldr\td6, [pc, #536]\t@ 868 <__gridxc_gga_MOD_pbeformxc+0x470>\n+\tadd\tr7, sp, #464\t@ 0x1d0\n+\tvmul.f64\td7, d7, d9\n \tvstr\td0, [sp, #280]\t@ 0x118\n-\tvmul.f64\td20, d18, d18\n-\tvstr\td18, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td8, d13, d17\n-\tvmov.f64\td17, d12\n-\tvdiv.f64\td14, d16, d19\n-\tvstr\td19, [sp, #176]\t@ 0xb0\n-\tvstr\td20, [sp, #320]\t@ 0x140\n-\tvstr\td8, [sp, #184]\t@ 0xb8\n-\tvfma.f64\td18, d14, d20\n-\tvfma.f64\td17, d14, d18\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td18, [sp, #296]\t@ 0x128\n-\tvdiv.f64\td17, d12, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #336]\t@ 0x150\n-\tvstr\td16, [sp, #304]\t@ 0x130\n-\tvadd.f64\td16, d16, d12\n-\tvmov.f64\td0, d16\n-\tvstr\td16, [sp, #192]\t@ 0xc0\n+\tvstr\td4, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td9, d10, d6\n+\tvmul.f64\td6, d5, d5\n+\tvstr\td5, [sp, #208]\t@ 0xd0\n+\tvdiv.f64\td4, d7, d4\n+\tvstr\td9, [sp, #192]\t@ 0xc0\n+\tvstr\td6, [sp, #144]\t@ 0x90\n+\tvmla.f64\td5, d4, d6\n+\tvmov.f64\td6, d8\n+\tvstr\td4, [sp, #288]\t@ 0x120\n+\tvmla.f64\td6, d4, d5\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td5, [sp, #120]\t@ 0x78\n+\tvdiv.f64\td6, d8, d6\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #328]\t@ 0x148\n+\tvstr\td7, [sp, #304]\t@ 0x130\n+\tvadd.f64\td7, d7, d8\n+\tvmov.f64\td0, d7\n+\tvstr\td7, [sp, #200]\t@ 0xc8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td17, d8, d0\n-\tvldr\td8, [r6]\n-\tvmov.i64\td30, #0x0000000000000000\n-\tvldr\td16, [r5]\n-\tadd\tr6, sp, #560\t@ 0x230\n-\tstr.w\tr8, [sp, #344]\t@ 0x158\n-\tadd\tr5, sp, #512\t@ 0x200\n-\tvdiv.f64\td29, d12, d8\n-\tvstr\td17, [sp, #312]\t@ 0x138\n-\tvadd.f64\td17, d10, d17\n-\tvadd.f64\td18, d8, d12\n+\tvldr\td14, [r6]\n+\tvmul.f64\td6, d9, d0\n+\tvldr\td7, [r5]\n+\tstr.w\tr8, [sp, #336]\t@ 0x150\n+\tadd\tr6, sp, #552\t@ 0x228\n+\tvdiv.f64\td5, d8, d14\n+\tvadd.f64\td4, d14, d8\n+\tadd\tr5, sp, #504\t@ 0x1f8\n+\tvldr\td3, [pc, #420]\t@ 870 <__gridxc_gga_MOD_pbeformxc+0x478>\n+\tvstr\td6, [sp, #312]\t@ 0x138\n+\tvadd.f64\td6, d11, d6\n \tmov\tr8, fp\n-\tadd\tr3, sp, #384\t@ 0x180\n+\tadd\tr3, sp, #376\t@ 0x178\n \tstr.w\tsl, [sp, #68]\t@ 0x44\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tvstr\td17, [sp, #136]\t@ 0x88\n-\tvldr\td17, [sp, #456]\t@ 0x1c8\n-\tvstr\td18, [sp, #72]\t@ 0x48\n-\tvstr\td17, [sp, #328]\t@ 0x148\n-\tvldr\td17, [sp, #464]\t@ 0x1d0\n-\tvstr\td17, [sp, #360]\t@ 0x168\n-\tvadd.f64\td17, d8, d8\n-\tvstr\td17, [sp, #96]\t@ 0x60\n-\tvadd.f64\td17, d16, d16\n-\tvstr\td17, [sp, #88]\t@ 0x58\n-\tvmul.f64\td16, d29, d16\n-\tvstr\td29, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #104]\t@ 0x68\n-\tvldmia\tr4!, {d13}\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tvstr\td6, [sp, #160]\t@ 0xa0\n+\tvldr\td6, [sp, #448]\t@ 0x1c0\n+\tvstr\td4, [sp, #72]\t@ 0x48\n+\tvstr\td6, [sp, #320]\t@ 0x140\n+\tvldr\td6, [sp, #456]\t@ 0x1c8\n+\tvstr\td6, [sp, #352]\t@ 0x160\n+\tvadd.f64\td6, d14, d14\n+\tvstr\td6, [sp, #96]\t@ 0x60\n+\tvadd.f64\td6, d7, d7\n+\tvstr\td6, [sp, #88]\t@ 0x58\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td5, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvldmia\tr4!, {d10}\n \tmov\tfp, r9\n-\tvldmia\tr8!, {d11}\n+\tvldmia\tr8!, {d9}\n+\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #284]\t@ 840 <__gridxc_gga_MOD_pbeformxc+0x448>\n \tadds\tr6, #24\n-\tvldr\td16, [pc, #376]\t@ 830 <__gridxc_gga_MOD_pbeformxc+0x470>\n+\tvadd.f64\td10, d10, d10\n+\tvstr\td3, [sp, #40]\t@ 0x28\n+\tvadd.f64\td9, d9, d9\n \tadds\tr5, #24\n-\tvadd.f64\td13, d13, d13\n-\tvstr\td30, [sp, #56]\t@ 0x38\n-\tvadd.f64\td11, d11, d11\n-\tvmaxnm.f64\td13, d13, d15\n-\tvmaxnm.f64\td11, d11, d15\n-\tvmul.f64\td0, d13, d16\n-\tvstmia\tr9!, {d13}\n+\tvcmpe.f64\td10, d13\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td9, d13\n+\tit\tlt\n+\tvmovlt.f64\td10, d13\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d10, d7\n+\tvstmia\tr9!, {d10}\n+\tit\tlt\n+\tvmovlt.f64\td9, d13\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td22, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td24, d13, d0\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvmul.f64\td19, d11, d22\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td6, d10, d0\n+\tvmov.f64\td11, d0\n+\tvldr\td3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tmov\tr2, fp\n+\tvmul.f64\td7, d9, d7\n \tstr\tr7, [sp, #0]\n-\tadds\tr7, #8\n \tldrd\tr0, r1, [sp, #80]\t@ 0x50\n-\tvstr\td0, [sp, #48]\t@ 0x30\n-\tvdiv.f64\td12, d19, d24\n-\tvldr\td19, [sp, #72]\t@ 0x48\n-\tvstr\td22, [sp, #40]\t@ 0x28\n-\tvstr\td24, [sp, #32]\n-\tvstr\td21, [sp, #16]\n-\tvmul.f64\td23, d16, d12\n-\tvmul.f64\td23, d23, d12\n-\tvadd.f64\td20, d23, d21\n-\tvstr\td23, [sp, #24]\n-\tvdiv.f64\td10, d21, d20\n-\tvfms.f64\td19, d10, d8\n-\tvmul.f64\td10, d10, d10\n-\tvstr\td19, [sp, #8]\n+\tvstr\td6, [sp, #32]\n+\tadds\tr7, #8\n+\tvdiv.f64\td0, d7, d6\n+\tvldr\td7, [sp, #104]\t@ 0x68\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td0, [sp, #24]\n+\tvmul.f64\td7, d7, d0\n+\tvadd.f64\td5, d7, d15\n+\tvstr\td7, [sp, #16]\n+\tvdiv.f64\td8, d15, d5\n+\tvmls.f64\td3, d8, d14\n+\tvmul.f64\td8, d8, d8\n+\tvstr\td3, [sp, #8]\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td25, [pc, #288]\t@ 858 <__gridxc_gga_MOD_pbeformxc+0x498>\n-\tvldr\td0, [sp, #48]\t@ 0x30\n-\tvldr\td21, [sp, #16]\n-\tvldr\td24, [sp, #32]\n-\tvmul.f64\td0, d0, d25\n-\tvldr\td23, [sp, #24]\n-\tvdiv.f64\td20, d21, d11\n-\tvldr\td16, [sp, #96]\t@ 0x60\n-\tvldr\td31, [r6, #-24]\t@ 0xffffffe8\n-\tvldr\td19, [sp, #8]\n-\tvdiv.f64\td17, d0, d24\n-\tvldr\td30, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td24, d21, d13\n-\tvldr\td18, [sp, #88]\t@ 0x58\n-\tvldr\td27, [r7, #-8]\n+\tvldr\td1, [pc, #196]\t@ 878 <__gridxc_gga_MOD_pbeformxc+0x480>\n+\tvldr\td6, [sp, #32]\n+\tvldr\td0, [sp, #24]\n+\tvmul.f64\td11, d11, d1\n+\tvldr\td7, [sp, #16]\n+\tvdiv.f64\td4, d15, d9\n+\tvldr\td3, [sp, #8]\n+\tvldr\td9, [r7, #-8]\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tvmul.f64\td18, d18, d12\n-\tvldr\td22, [sp, #40]\t@ 0x28\n+\tvdiv.f64\td5, d11, d6\n+\tvdiv.f64\td6, d15, d10\n+\tvmul.f64\td9, d3, d9\n \tcmp\tr3, r4\n-\tvadd.f64\td17, d17, d24\n-\tvadd.f64\td24, d12, d12\n-\tvnmul.f64\td17, d17, d24\n-\tvldr\td24, [r6, #-8]\n-\tvmul.f64\td17, d17, d23\n-\tvdiv.f64\td23, d17, d12\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tvmul.f64\td28, d16, d17\n-\tvldr\td17, [sp, #384]\t@ 0x180\n-\tvmul.f64\td16, d13, d17\n-\tvldr\td17, [r6, #-16]\n-\tvmul.f64\td31, d28, d31\n-\tvmul.f64\td17, d28, d17\n-\tvmul.f64\td28, d28, d24\n-\tvfma.f64\td30, d16, d19\n-\tvmul.f64\td31, d31, d16\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td28, d28, d16\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td31, d31, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td23, d23, d16\n-\tvmul.f64\td16, d28, d20\n-\tvmul.f64\td20, d12, d20\n-\tvmul.f64\td23, d23, d10\n-\tvmul.f64\td31, d31, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td16, d16, d20\n-\tvfma.f64\td23, d27, d19\n-\tvmul.f64\td31, d31, d18\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td31, d31, d10\n-\tvmul.f64\td17, d17, d10\n-\tvmul.f64\td16, d16, d10\n-\tvstmia\tsl!, {d23}\n-\tvstr\td31, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tbne.w\t6a8 <__gridxc_gga_MOD_pbeformxc+0x2e8>\n-\tb.n\t86c <__gridxc_gga_MOD_pbeformxc+0x4ac>\n+\tvadd.f64\td6, d5, d6\n+\tvadd.f64\td5, d0, d0\n+\tvnmul.f64\td6, d6, d5\n+\tvldr\td5, [r6, #-24]\t@ 0xffffffe8\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [sp, #96]\t@ 0x60\n+\tvdiv.f64\td11, d6, d0\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmul.f64\td2, d7, d6\n+\tvldr\td7, [sp, #376]\t@ 0x178\n+\tvmov.f64\td6, d3\n+\tvldr\td3, [sp, #40]\t@ 0x28\n+\tvmul.f64\td7, d10, d7\n+\tvldr\td10, [r6, #-8]\n+\tvmul.f64\td5, d2, d5\n+\tvmla.f64\td3, d7, d6\n+\tvldr\td6, [r6, #-16]\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td6, d2, d6\n+\tvmul.f64\td2, d2, d10\n+\tb.n\t88c <__gridxc_gga_MOD_pbeformxc+0x494>\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0xeafdf295\n-\t.word\t0x404014fc\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x6dc9c883\n-\t.word\t0x3ff45f30\n \t.word\t0xffffdcd1\n \t.word\t0xbfefffff\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n+\t.word\t0x6dc9c883\n+\t.word\t0x3ff45f30\n+\t.word\t0xeafdf295\n+\t.word\t0x404014fc\n \t.word\t0xf1fb1946\n \t.word\t0x3f9fd63c\n+\t...\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x0000047a\n+\t.word\t0x00000462\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000039a\n+\t.word\t0x00000370\n R_ARM_REL32\t.rodata\n-\tvldr\td6, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvmul.f64\td22, d6, d22\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tldr.w\tr8, [sp, #344]\t@ 0x158\n-\tvstr\td16, [r3]\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td2, d2, d7\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td7, d11, d7\n+\tvmla.f64\td9, d7, d8\n+\tvmul.f64\td7, d0, d4\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td0, d4, d0\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td7, d2, d7\n+\tvmul.f64\td5, d5, d0\n+\tvstmia\tsl!, {d9}\n+\tvmul.f64\td6, d6, d0\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td5, d5, d8\n+\tvmul.f64\td6, d6, d8\n+\tvmul.f64\td7, d7, d8\n+\tvstr\td5, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td6, [r5, #-16]\n+\tvstr\td7, [r5, #-8]\n+\tbne.w\t714 <__gridxc_gga_MOD_pbeformxc+0x31c>\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tvldr\td7, [sp, #160]\t@ 0xa0\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tldr\tr0, [sp, #156]\t@ 0x9c\n+\tvstr\td7, [r3]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n \tcmp\tr0, #0\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tvmul.f64\td22, d22, d30\n-\tvstr\td22, [r3]\n-\tble.w\tada <__gridxc_gga_MOD_pbeformxc+0x71a>\n-\tvldr\td16, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td14, d0, d7\n+\tldr.w\tr8, [sp, #336]\t@ 0x150\n+\tvmul.f64\td14, d14, d3\n+\tvstr\td14, [r3]\n+\tble.w\tbca <__gridxc_gga_MOD_pbeformxc+0x7d2>\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n \tcmp\tr0, #1\n-\tvldr\td17, [sp, #240]\t@ 0xf0\n-\tvldr\td18, [sp, #120]\t@ 0x78\n-\tvldr\td7, [sp, #256]\t@ 0x100\n-\tvmul.f64\td20, d16, d17\n-\tvldr\td16, [sp, #264]\t@ 0x108\n-\tvldr\td17, [sp, #272]\t@ 0x110\n-\tvmul.f64\td18, d9, d18\n-\tvldr\td22, [sp, #184]\t@ 0xb8\n-\tvdiv.f64\td24, d21, d16\n-\tvldr\td16, [sp, #288]\t@ 0x120\n-\tvldr\td5, [sp, #168]\t@ 0xa8\n-\tvldr\td4, [sp, #296]\t@ 0x128\n-\tvdiv.f64\td16, d21, d16\n-\tvldr\td31, [sp, #304]\t@ 0x130\n-\tvldr\td3, [sp, #312]\t@ 0x138\n-\tvldr\td1, [sp, #320]\t@ 0x140\n-\tvldr\td2, [sp, #336]\t@ 0x150\n-\tldr\tr1, [sp, #356]\t@ 0x164\n-\tldr\tr4, [sp, #352]\t@ 0x160\n-\tldr\tr5, [sp, #348]\t@ 0x15c\n-\tldrd\tr2, r3, [sp, #408]\t@ 0x198\n-\tvsub.f64\td24, d24, d16\n-\tvldr\td16, [sp, #280]\t@ 0x118\n-\tvmul.f64\td16, d16, d14\n-\tvmul.f64\td24, d24, d25\n-\tvdiv.f64\td25, d21, d4\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [sp, #176]\t@ 0xb0\n-\tvdiv.f64\td29, d16, d17\n-\tvldr\td16, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td19, d16, d6\n-\tvldr\td16, [sp, #224]\t@ 0xe0\n-\tvdiv.f64\td23, d21, d16\n-\tvldr\td16, [sp, #192]\t@ 0xc0\n-\tvmul.f64\td19, d19, d24\n-\tvdiv.f64\td27, d21, d16\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td17, d9, d16\n-\tvldr\td16, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td16, d9, d16\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td18, d18, d23\n-\tvmul.f64\td23, d7, d23\n-\tvmul.f64\td17, d17, d22\n-\tvmul.f64\td16, d16, d22\n-\tvmul.f64\td18, d18, d22\n-\tvmul.f64\td22, d22, d31\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td18, d18, d23\n-\tvldr\td23, [pc, #508]\t@ b60 <__gridxc_gga_MOD_pbeformxc+0x7a0>\n-\tvmul.f64\td22, d22, d27\n-\tvmul.f64\td23, d20, d23\n-\tvmul.f64\td23, d23, d6\n-\tvdiv.f64\td26, d23, d20\n-\tvldr\td23, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tvdiv.f64\td28, d20, d23\n-\tvmul.f64\td23, d5, d9\n-\tvdiv.f64\td30, d21, d23\n-\tvmov.f64\td21, #16\t@ 0x40800000 4.0\n-\tvldr\td23, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td21, d14, d21\n-\tvfma.f64\td20, d21, d23\n-\tvldr\td21, [sp, #328]\t@ 0x148\n-\tvmov.f64\td23, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td20, d20, d7\n-\tvmul.f64\td10, d7, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvsub.f64\td20, d21, d5\n-\tvadd.f64\td26, d26, d6\n-\tvmul.f64\td17, d17, d31\n-\tvmul.f64\td16, d16, d31\n-\tvmul.f64\td18, d18, d31\n-\tvadd.f64\td31, d3, d21\n-\tvnmul.f64\td7, d23, d28\n-\tvmul.f64\td23, d3, d23\n-\tvmul.f64\td20, d20, d30\n-\tvfma.f64\td20, d7, d19\n-\tvmul.f64\td19, d28, d19\n-\tvadd.f64\td21, d26, d19\n-\tvmul.f64\td19, d23, d19\n-\tvmul.f64\td20, d20, d29\n-\tvnmul.f64\td21, d10, d21\n-\tvfma.f64\td21, d1, d20\n-\tvmul.f64\td20, d4, d20\n-\tvfma.f64\td20, d14, d21\n-\tvmul.f64\td21, d25, d21\n-\tvfms.f64\td21, d20, d2\n-\tvfma.f64\td19, d22, d21\n-\tvfma.f64\td31, d9, d19\n-\tvmov.f64\td19, d25\n-\tvfms.f64\td19, d14, d2\n-\tvstr\td31, [r4]\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td19, d18, d19\n-\tvmul.f64\td17, d17, d27\n-\tvmul.f64\td16, d16, d27\n-\tvmul.f64\td19, d19, d27\n-\tvstr\td17, [r1]\n-\tvstr\td16, [r1, #8]\n-\tvstr\td19, [r1, #16]\n+\tvldr\td6, [sp, #248]\t@ 0xf8\n+\tvldr\td8, [sp, #288]\t@ 0x120\n+\tvldr\td11, [sp, #304]\t@ 0x130\n+\tvmul.f64\td3, d7, d6\n+\tvldr\td7, [sp, #264]\t@ 0x108\n+\tvldr\td6, [sp, #296]\t@ 0x128\n+\tvldr\td14, [sp, #176]\t@ 0xb0\n+\tvdiv.f64\td7, d15, d7\n+\tvdiv.f64\td6, d15, d6\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tvmul.f64\td1, d7, d1\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvmul.f64\td7, d7, d8\n+\tvstr\td1, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #184]\t@ 0xb8\n+\tvdiv.f64\td7, d7, d6\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvmul.f64\td7, d6, d0\n+\tvldr\td6, [sp, #232]\t@ 0xe8\n+\tvdiv.f64\td2, d15, d6\n+\tvldr\td6, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td7, d7, d1\n+\tvldr\td1, [sp, #136]\t@ 0x88\n+\tvdiv.f64\td13, d15, d6\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td4, d12, d6\n+\tvldr\td6, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td5, d12, d6\n+\tvldr\td6, [sp, #128]\t@ 0x80\n+\tvmul.f64\td6, d12, d6\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td2, d1, d2\n+\tvldr\td1, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td4, d4, d1\n+\tvmul.f64\td5, d5, d1\n+\tvmul.f64\td6, d6, d1\n+\tvmul.f64\td1, d1, d11\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [pc, #640]\t@ c58 <__gridxc_gga_MOD_pbeformxc+0x860>\n+\tvmul.f64\td9, d1, d13\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvmul.f64\td2, d3, d2\n+\tvstr\td9, [sp, #32]\n+\tvldr\td9, [sp, #120]\t@ 0x78\n+\tvmul.f64\td2, d2, d0\n+\tvdiv.f64\td9, d15, d9\n+\tvdiv.f64\td10, d2, d3\n+\tvmul.f64\td2, d1, d12\n+\tvmov.f64\td3, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td14, d3, d14\n+\tvdiv.f64\td2, d15, d2\n+\tvmov.f64\td15, d8\n+\tvadd.f64\td10, d10, d0\n+\tvmul.f64\td0, d14, d7\n+\tvstr\td2, [sp, #16]\n+\tvmov.f64\td2, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td2, d8, d2\n+\tvldr\td8, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td3, d2, d8\n+\tvldr\td2, [sp, #136]\t@ 0x88\n+\tvmul.f64\td3, d3, d2\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td2, d2, d3\n+\tvldr\td3, [sp, #320]\t@ 0x140\n+\tvmul.f64\td4, d4, d11\n+\tvmul.f64\td5, d5, d11\n+\tvmul.f64\td6, d6, d11\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tvstr\td2, [sp, #24]\n+\tvsub.f64\td8, d3, d1\n+\tvmul.f64\td2, d14, d11\n+\tvldr\td1, [sp, #312]\t@ 0x138\n+\tvmul.f64\td11, d1, d11\n+\tvadd.f64\td3, d1, d3\n+\tvstr\td2, [sp, #8]\n+\tvldr\td2, [sp, #8]\n+\tvmul.f64\td7, d2, d7\n+\tvldr\td2, [sp, #16]\n+\tvnmls.f64\td7, d8, d2\n+\tvldr\td8, [sp, #40]\t@ 0x28\n+\tvldr\td2, [sp, #24]\n+\tldr\tr5, [sp, #340]\t@ 0x154\n+\tldr\tr1, [sp, #348]\t@ 0x15c\n+\tldrd\tr2, r3, [sp, #400]\t@ 0x190\n \tstrd\tr2, r3, [r5]\n-\tldrd\tr2, r3, [sp, #512]\t@ 0x200\n+\tldr\tr4, [sp, #344]\t@ 0x158\n+\tldrd\tr2, r3, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td7, d7, d8\n+\tvadd.f64\td8, d10, d0\n \tstrd\tr2, r3, [r8]\n-\tldrd\tr2, r3, [sp, #520]\t@ 0x208\n+\tldrd\tr2, r3, [sp, #512]\t@ 0x200\n \tstrd\tr2, r3, [r8, #8]\n-\tldrd\tr2, r3, [sp, #528]\t@ 0x210\n+\tldrd\tr2, r3, [sp, #520]\t@ 0x208\n+\tvmul.f64\td8, d8, d2\n+\tvldr\td2, [sp, #144]\t@ 0x90\n \tstrd\tr2, r3, [r8, #16]\n-\tbeq.n\tada <__gridxc_gga_MOD_pbeformxc+0x71a>\n-\tvldr\td18, [sp, #368]\t@ 0x170\n-\tvldr\td20, [sp, #360]\t@ 0x168\n-\tvstr\td16, [r1, #32]\n-\tvnmul.f64\td11, d6, d18\n-\tvstr\td17, [r1, #24]\n-\tvsub.f64\td18, d20, d5\n-\tvadd.f64\td20, d20, d3\n-\tldrd\tr2, r3, [sp, #416]\t@ 0x1a0\n+\tvnmls.f64\td8, d2, d7\n+\tvldr\td2, [sp, #120]\t@ 0x78\n+\tvmul.f64\td7, d2, d7\n+\tvldr\td2, [sp, #328]\t@ 0x148\n+\tvmla.f64\td7, d15, d8\n+\tvmul.f64\td7, d7, d2\n+\tvnmls.f64\td7, d9, d8\n+\tvldr\td8, [sp, #32]\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td7, d11, d0\n+\tvmla.f64\td3, d7, d12\n+\tvmov.f64\td7, d9\n+\tvmls.f64\td7, d15, d2\n+\tvstr\td3, [r4]\n+\tvmov.f64\td3, d2\n+\tvmul.f64\td4, d4, d7\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td7, d6, d7\n+\tvmul.f64\td4, d4, d13\n+\tvmul.f64\td5, d5, d13\n+\tvmul.f64\td7, d7, d13\n+\tvstr\td4, [r1]\n+\tvstr\td5, [r1, #8]\n+\tvstr\td7, [r1, #16]\n+\tbeq.n\tbca <__gridxc_gga_MOD_pbeformxc+0x7d2>\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvldr\td6, [sp, #360]\t@ 0x168\n+\tvstr\td5, [r1, #32]\n+\tvldr\td5, [sp, #56]\t@ 0x38\n+\tvnmul.f64\td6, d0, d6\n+\tvstr\td4, [r1, #24]\n+\tvstr\td7, [r1, #40]\t@ 0x28\n+\tvldr\td4, [sp, #8]\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td5, [sp, #352]\t@ 0x160\n+\tvldr\td2, [sp, #120]\t@ 0x78\n+\tvldr\td8, [sp, #32]\n+\tvsub.f64\td7, d5, d7\n+\tvadd.f64\td5, d5, d1\n+\tvmul.f64\td1, d4, d6\n+\tvldr\td4, [sp, #16]\n+\tvmla.f64\td10, d6, d14\n+\tvmul.f64\td11, d11, d6\n+\tldrd\tr2, r3, [sp, #408]\t@ 0x198\n \tstrd\tr2, r3, [r5, #8]\n-\tvmul.f64\td11, d11, d24\n-\tvstr\td19, [r1, #40]\t@ 0x28\n-\tvmul.f64\td18, d18, d30\n-\tldrd\tr2, r3, [sp, #536]\t@ 0x218\n+\tvnmls.f64\td1, d7, d4\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tldrd\tr2, r3, [sp, #528]\t@ 0x210\n \tstrd\tr2, r3, [r8, #24]\n-\tvfma.f64\td18, d7, d11\n-\tvfma.f64\td26, d11, d28\n-\tvmul.f64\td23, d23, d11\n-\tldrd\tr2, r3, [sp, #544]\t@ 0x220\n+\tldrd\tr2, r3, [sp, #536]\t@ 0x218\n \tstrd\tr2, r3, [r8, #32]\n-\tldrd\tr2, r3, [sp, #552]\t@ 0x228\n-\tvmul.f64\td23, d23, d28\n+\tldrd\tr2, r3, [sp, #544]\t@ 0x220\n \tstrd\tr2, r3, [r8, #40]\t@ 0x28\n-\tvmul.f64\td16, d18, d29\n-\tvnmul.f64\td10, d10, d26\n-\tvfma.f64\td10, d16, d1\n-\tvmul.f64\td16, d4, d16\n-\tvfma.f64\td16, d14, d10\n-\tvmul.f64\td25, d25, d10\n-\tvfms.f64\td25, d16, d2\n-\tvfma.f64\td23, d25, d22\n-\tvfma.f64\td20, d9, d23\n-\tvstr\td20, [r4, #8]\n-\tldr\tr2, [pc, #148]\t@ (b70 <__gridxc_gga_MOD_pbeformxc+0x7b0>)\n-\tldr\tr3, [pc, #148]\t@ (b74 <__gridxc_gga_MOD_pbeformxc+0x7b4>)\n+\tvmul.f64\td1, d1, d7\n+\tvldr\td7, [sp, #24]\n+\tvmul.f64\td10, d10, d7\n+\tvldr\td7, [sp, #144]\t@ 0x90\n+\tvnmls.f64\td10, d1, d7\n+\tvmul.f64\td7, d15, d10\n+\tvmla.f64\td7, d2, d1\n+\tvmul.f64\td7, d7, d3\n+\tvnmls.f64\td7, d9, d10\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td7, d11, d14\n+\tvmla.f64\td5, d7, d12\n+\tvstr\td5, [r4, #8]\n+\tldr\tr2, [pc, #156]\t@ (c68 <__gridxc_gga_MOD_pbeformxc+0x870>)\n+\tldr\tr3, [pc, #156]\t@ (c6c <__gridxc_gga_MOD_pbeformxc+0x874>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #612]\t@ 0x264\n+\tldr\tr3, [sp, #604]\t@ 0x25c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\tb5c <__gridxc_gga_MOD_pbeformxc+0x79c>\n-\tadd.w\tsp, sp, #620\t@ 0x26c\n+\tbne.n\tc4e <__gridxc_gga_MOD_pbeformxc+0x856>\n+\tadd.w\tsp, sp, #612\t@ 0x264\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td17, [r3, #16]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #8]\n-\tvmul.f64\td20, d16, d18\n-\tvmov.f64\td23, d17\n-\tvstr\td17, [sp, #120]\t@ 0x78\n-\tvmul.f64\td19, d22, d18\n-\tvldr\td9, [pc, #76]\t@ b68 <__gridxc_gga_MOD_pbeformxc+0x7a8>\n-\tvmul.f64\td17, d21, d18\n-\tvstr\td22, [sp, #488]\t@ 0x1e8\n-\tvstr\td21, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td18, d23, d18\n-\tvmaxnm.f64\td9, d16, d9\n-\tvmov.f64\td22, d19\n-\tvmov.f64\td21, d19\n-\tvmov.f64\td16, d17\n-\tvstr\td20, [sp, #392]\t@ 0x188\n-\tvstr\td20, [sp, #400]\t@ 0x190\n-\tvstr\td19, [sp, #560]\t@ 0x230\n-\tvstr\td19, [sp, #584]\t@ 0x248\n-\tvstr\td17, [sp, #568]\t@ 0x238\n-\tvstr\td17, [sp, #592]\t@ 0x250\n-\tvstr\td18, [sp, #576]\t@ 0x240\n-\tb.n\t482 <__gridxc_gga_MOD_pbeformxc+0xc2>\n+\tvldr\td12, [pc, #116]\t@ c60 <__gridxc_gga_MOD_pbeformxc+0x868>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [r3, #16]\n+\tvldr\td4, [r3]\n+\tvmul.f64\td2, d7, d5\n+\tvcmpe.f64\td7, d12\n+\tvldr\td6, [r3, #8]\n+\tvmov.f64\td1, d3\n+\tvstr\td3, [sp, #128]\t@ 0x80\n+\tvstr\td4, [sp, #480]\t@ 0x1e0\n+\tvmul.f64\td4, d4, d5\n+\tvstr\td6, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td6, d6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td5, d3, d5\n+\tvstr\td2, [sp, #384]\t@ 0x180\n+\tvstr\td2, [sp, #392]\t@ 0x188\n+\tvstr\td4, [sp, #552]\t@ 0x228\n+\tvstr\td4, [sp, #576]\t@ 0x240\n+\tit\tge\n+\tvmovge.f64\td12, d7\n+\tvstr\td6, [sp, #560]\t@ 0x230\n+\tvmov.f64\td7, d6\n+\tvstr\td6, [sp, #584]\t@ 0x248\n+\tvstr\td5, [sp, #568]\t@ 0x238\n+\tb.n\t4c4 <__gridxc_gga_MOD_pbeformxc+0xcc>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n+\tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000008e\n+\t.word\t0x00000096\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00000b78 <__gridxc_gga_MOD_b88formx.constprop.0>:\n+00000c70 <__gridxc_gga_MOD_b88formx.constprop.0>:\n __gridxc_gga_MOD_b88formx.constprop.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3632]\t@ 0xe30\n-\tldr\tr6, [pc, #936]\t@ (f38 <__gridxc_gga_MOD_b88formx.constprop.0+0x3c0>)\n-\tsub\tsp, #364\t@ 0x16c\n-\tldr\tr5, [pc, #936]\t@ (f3c <__gridxc_gga_MOD_b88formx.constprop.0+0x3c4>)\n+\tstr.w\tr0, [ip, #3640]\t@ 0xe38\n+\tldr\tr6, [pc, #904]\t@ (1010 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a0>)\n+\tsub\tsp, #356\t@ 0x164\n+\tldr\tr5, [pc, #904]\t@ (1014 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a4>)\n \tadd\tr6, pc\n-\tldr\tr4, [sp, #464]\t@ 0x1d0\n-\tldrd\tsl, ip, [sp, #480]\t@ 0x1e0\n+\tldr\tr4, [sp, #456]\t@ 0x1c8\n+\tldr.w\tip, [sp, #476]\t@ 0x1dc\n \tldr\tr5, [r6, r5]\n \tldr.w\tlr, [r4]\n \tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #356]\t@ 0x164\n+\tstr\tr5, [sp, #348]\t@ 0x15c\n \tmov.w\tr5, #0\n-\tstrd\tr2, r3, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #468]\t@ 0x1d4\n+\tstrd\tr2, r3, [sp, #120]\t@ 0x78\n+\tldr\tr3, [sp, #460]\t@ 0x1cc\n \tcmp.w\tlr, #1\n-\tldrd\tr5, r2, [sp, #472]\t@ 0x1d8\n-\tstrd\tr0, r1, [sp, #120]\t@ 0x78\n-\tstr\tr2, [sp, #144]\t@ 0x90\n-\tvldr\td16, [r3]\n-\tbeq.w\teca <__gridxc_gga_MOD_b88formx.constprop.0+0x352>\n-\tadd\tr4, sp, #304\t@ 0x130\n-\tvldr\td17, [r3, #8]\n+\tldrd\tr5, r2, [sp, #464]\t@ 0x1d0\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tldr\tr2, [sp, #472]\t@ 0x1d8\n+\tvldr\td7, [r3]\n+\tstrd\tr0, r1, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #156]\t@ 0x9c\n+\tbeq.w\t1020 <__gridxc_gga_MOD_b88formx.constprop.0+0x3b0>\n+\tvldr\td5, [r3, #8]\n+\tadd\tr4, sp, #296\t@ 0x128\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n \tmov\tr7, r4\n+\tvldr\td6, [pc, #800]\t@ ff0 <__gridxc_gga_MOD_b88formx.constprop.0+0x380>\n+\tadd\tr6, sp, #320\t@ 0x140\n+\tvadd.f64\td7, d5, d7\n \tldr\tr0, [r5, #0]\n \tldr\tr1, [r5, #4]\n-\tadd\tr6, sp, #328\t@ 0x148\n \tldr\tr2, [r5, #8]\n \tldr\tr3, [r5, #12]\n+\tvcmpe.f64\td7, d6\n \tstmia\tr7!, {r0, r1, r2, r3}\n \tldr\tr0, [r5, #16]\n \tldr\tr1, [r5, #20]\n \tstmia\tr7!, {r0, r1}\n-\tvstr\td16, [sp, #176]\t@ 0xb0\n-\tvadd.f64\td16, d17, d16\n-\tvldr\td18, [pc, #824]\t@ f20 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a8>\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [sp, #176]\t@ 0xb0\n \tldr\tr0, [r5, #24]\n \tldr\tr1, [r5, #28]\n-\tvmaxnm.f64\td16, d16, d18\n \tldr\tr2, [r5, #32]\n \tldr\tr3, [r5, #36]\t@ 0x24\n \tstmia\tr6!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tldr\tr0, [r5, #40]\t@ 0x28\n \tldr\tr1, [r5, #44]\t@ 0x2c\n \tstmia\tr6!, {r0, r1}\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n-\tvldr\td17, [sp, #312]\t@ 0x138\n-\tvmov.i64\td20, #0x0000000000000000\n-\tvldr\td16, [sp, #336]\t@ 0x150\n-\tadd.w\tr8, sp, #176\t@ 0xb0\n-\tvldr\td22, [sp, #304]\t@ 0x130\n-\tadd\tr7, sp, #208\t@ 0xd0\n-\tvldr\td21, [sp, #328]\t@ 0x148\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td18, [sp, #344]\t@ 0x158\n-\tvfma.f64\td17, d22, d22\n-\tvldr\td19, [sp, #320]\t@ 0x140\n-\tvfma.f64\td16, d21, d21\n-\tldr\tr3, [pc, #772]\t@ (f40 <__gridxc_gga_MOD_b88formx.constprop.0+0x3c8>)\n-\tvldr\td27, [pc, #740]\t@ f20 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a8>\n-\tadd.w\tfp, sp, #224\t@ 0xe0\n-\tadd\tr6, sp, #240\t@ 0xf0\n-\tadd\tr5, sp, #256\t@ 0x100\n-\tvfma.f64\td17, d19, d19\n-\tadd\tr3, pc\n-\tvfma.f64\td16, d18, d18\n-\tadd.w\tr9, sp, #192\t@ 0xc0\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tadd\tr3, sp, #168\t@ 0xa8\n-\tstr.w\tr9, [sp, #116]\t@ 0x74\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tstrd\tlr, sl, [sp, #148]\t@ 0x94\n-\tstr.w\tip, [sp, #156]\t@ 0x9c\n-\tvsqrt.f64\td18, d17\n-\tvsqrt.f64\td17, d16\n-\tvstr\td18, [sp, #224]\t@ 0xe0\n-\tvstr\td17, [sp, #232]\t@ 0xe8\n-\tvldmia\tr8!, {d8}\n-\tmov\tsl, r7\n+\tvstr\td7, [sp, #144]\t@ 0x90\n+\tvldr\td6, [sp, #304]\t@ 0x130\n+\tadd.w\tr9, sp, #168\t@ 0xa8\n+\tvldr\td7, [sp, #328]\t@ 0x148\n+\tadd.w\tr8, sp, #200\t@ 0xc8\n+\tvldr\td2, [sp, #296]\t@ 0x128\n+\tadd.w\tfp, sp, #216\t@ 0xd8\n+\tvldr\td3, [sp, #320]\t@ 0x140\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [sp, #336]\t@ 0x150\n+\tvmla.f64\td6, d2, d2\n+\tvldr\td4, [sp, #312]\t@ 0x138\n+\tvmla.f64\td7, d3, d3\n+\tldr\tr3, [pc, #724]\t@ (1018 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a8>)\n+\tvldr\td1, [pc, #692]\t@ ff8 <__gridxc_gga_MOD_b88formx.constprop.0+0x388>\n+\tadd\tr6, sp, #232\t@ 0xe8\n+\tvldr\td15, [pc, #676]\t@ ff0 <__gridxc_gga_MOD_b88formx.constprop.0+0x380>\n+\tadd\tr5, sp, #248\t@ 0xf8\n+\tvmla.f64\td6, d4, d4\n+\tadd\tr3, pc\n+\tvmla.f64\td7, d5, d5\n+\tadd.w\tsl, sp, #184\t@ 0xb8\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tadd\tr3, sp, #160\t@ 0xa0\n+\tstr.w\tsl, [sp, #108]\t@ 0x6c\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tstr.w\tlr, [sp, #140]\t@ 0x8c\n+\tstr.w\tip, [sp, #152]\t@ 0x98\n+\tvstr\td1, [sp, #8]\n+\tvsqrt.f64\td5, d6\n+\tvsqrt.f64\td6, d7\n+\tvstr\td5, [sp, #216]\t@ 0xd8\n+\tvstr\td6, [sp, #224]\t@ 0xe0\n+\tvldmia\tr9!, {d9}\n+\tmov\tr7, r8\n \tvldmia\tfp!, {d10}\n \tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvldr\td16, [pc, #672]\t@ f28 <__gridxc_gga_MOD_b88formx.constprop.0+0x3b0>\n+\tvldr\td7, [pc, #620]\t@ 1000 <__gridxc_gga_MOD_b88formx.constprop.0+0x390>\n+\tadds\tr4, #24\n+\tvadd.f64\td9, d9, d9\n \tadds\tr5, #24\n-\tvadd.f64\td8, d8, d8\n-\tvstr\td20, [sp, #104]\t@ 0x68\n \tvadd.f64\td10, d10, d10\n-\tvstr\td27, [sp, #96]\t@ 0x60\n-\tadds\tr4, #24\n-\tvmaxnm.f64\td8, d8, d27\n-\tvmaxnm.f64\td10, d10, d27\n-\tvmul.f64\td0, d8, d16\n-\tvstmia\tr7!, {d8}\n+\tvcmpe.f64\td9, d15\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td10, d15\n+\tit\tlt\n+\tvmovlt.f64\td9, d15\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d9, d7\n+\tvstmia\tr8!, {d9}\n+\tit\tlt\n+\tvmovlt.f64\td10, d15\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td26, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td25, d8, d0\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tvmul.f64\td16, d10, d26\n-\tvstr\td0, [sp, #80]\t@ 0x50\n-\tvstr\td26, [sp, #88]\t@ 0x58\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td1, d9, d0\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tvmov.f64\td5, d12\n+\tvstr\td0, [sp, #96]\t@ 0x60\n+\tvmul.f64\td7, d10, d7\n+\tvstr\td1, [sp, #88]\t@ 0x58\n \tvldr\td13, [r3]\n-\tvdiv.f64\td9, d16, d25\n-\tvmov.f64\td16, d12\n-\tvstr\td25, [sp, #72]\t@ 0x48\n-\tvmul.f64\td17, d9, d13\n-\tvmul.f64\td11, d9, d9\n-\tvfma.f64\td16, d17, d17\n-\tvstr\td17, [sp, #56]\t@ 0x38\n-\tvsqrt.f64\td28, d16\n-\tvadd.f64\td24, d17, d28\n-\tvstr\td28, [sp, #64]\t@ 0x40\n-\tvmov.f64\td0, d24\n-\tvstr\td24, [sp, #48]\t@ 0x30\n+\tvdiv.f64\td8, d7, d1\n+\tvmul.f64\td7, d8, d13\n+\tvmul.f64\td14, d8, d8\n+\tvmla.f64\td5, d7, d7\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvsqrt.f64\td6, d5\n+\tvadd.f64\td5, d7, d6\n+\tvstr\td6, [sp, #80]\t@ 0x50\n+\tvmov.f64\td0, d5\n+\tvstr\td5, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tvmov.f64\td19, d12\n-\tvmov.f64\td21, d12\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tmov\tr2, sl\n-\tvstr\td0, [sp, #24]\n-\tvldr\td22, [r3]\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tvmul.f64\td23, d9, d22\n-\tvstr\td22, [sp, #40]\t@ 0x28\n-\tvldr\td14, [r3]\n-\tldrd\tr1, r3, [sp, #136]\t@ 0x88\n-\tvfma.f64\td19, d0, d23\n-\tvmul.f64\td11, d11, d14\n+\tmov\tr2, r7\n+\tldr\tr7, [sp, #112]\t@ 0x70\n+\tvmov.f64\td4, d12\n \tstr\tr6, [sp, #0]\n-\tvstr\td23, [sp, #32]\n-\tvadd.f64\td14, d14, d14\n \tadds\tr6, #8\n-\tvmul.f64\td14, d14, d9\n-\tvdiv.f64\td15, d12, d19\n-\tvfma.f64\td21, d11, d15\n-\tvmul.f64\td19, d15, d15\n-\tvstr\td19, [sp, #8]\n-\tvstr\td21, [sp, #16]\n+\tldrd\tr1, r3, [sp, #128]\t@ 0x80\n+\tvstr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td5, [r7]\n+\tldr\tr7, [sp, #116]\t@ 0x74\n+\tldr\tr0, [sp, #124]\t@ 0x7c\n+\tvmul.f64\td7, d8, d5\n+\tvstr\td5, [sp, #64]\t@ 0x40\n+\tvldr\td11, [r7]\n+\tvmla.f64\td4, d0, d7\n+\tvstr\td7, [sp, #24]\n+\tvmul.f64\td14, d14, d11\n+\tvmov.f64\td7, d12\n+\tvadd.f64\td11, d11, d11\n+\tvmul.f64\td11, d11, d8\n+\tvdiv.f64\td3, d12, d4\n+\tvmla.f64\td7, d14, d3\n+\tvmul.f64\td6, d3, d3\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvstr\td7, [sp, #32]\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td17, [sp, #56]\t@ 0x38\n-\tvldr\td28, [sp, #64]\t@ 0x40\n-\tvldr\td18, [sp, #80]\t@ 0x50\n-\tvldr\td31, [r4, #-16]\n-\tvdiv.f64\td29, d17, d28\n-\tvldr\td28, [pc, #452]\t@ f30 <__gridxc_gga_MOD_b88formx.constprop.0+0x3b8>\n-\tvdiv.f64\td17, d12, d10\n-\tvldr\td19, [sp, #8]\n-\tvldr\td25, [sp, #72]\t@ 0x48\n-\tvmul.f64\td28, d18, d28\n-\tvldr\td5, [r4, #-8]\n-\tvldr\td18, [r4, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td11, d11, d19\n-\tvdiv.f64\td30, d12, d8\n-\tvldr\td7, [sp, #168]\t@ 0xa8\n-\tvadd.f64\td5, d5, d5\n-\tvldr\td24, [sp, #48]\t@ 0x30\n-\tvdiv.f64\td19, d28, d25\n-\tvadd.f64\td18, d18, d18\n-\tvmul.f64\td8, d8, d7\n-\tvadd.f64\td28, d31, d31\n-\tvldr\td23, [sp, #32]\n-\tvldr\td0, [sp, #24]\n-\tvldr\td22, [sp, #40]\t@ 0x28\n-\tvmul.f64\td18, d18, d8\n-\tvmul.f64\td28, d28, d8\n-\tvmul.f64\td25, d5, d8\n-\tvmul.f64\td31, d9, d8\n-\tvldr\td21, [sp, #16]\n-\tvldr\td6, [r6, #-8]\n-\tldr\tr3, [sp, #116]\t@ 0x74\n-\tvldr\td20, [sp, #104]\t@ 0x68\n-\tvfma.f64\td20, d21, d8\n-\tcmp\tr8, r3\n-\tvldr\td26, [sp, #88]\t@ 0x58\n-\tvldr\td27, [sp, #96]\t@ 0x60\n-\tvmla.f64\td13, d29, d13\n-\tvmul.f64\td9, d9, d17\n-\tvmul.f64\td18, d18, d17\n-\tvmul.f64\td28, d28, d17\n-\tvmul.f64\td25, d25, d17\n-\tvmul.f64\td18, d18, d9\n-\tvmul.f64\td28, d28, d9\n-\tvmul.f64\td25, d25, d9\n-\tvadd.f64\td19, d19, d30\n-\tvdiv.f64\td17, d13, d24\n-\tvmul.f64\td19, d31, d19\n-\tvmul.f64\td17, d17, d23\n-\tvfma.f64\td17, d0, d22\n-\tvnmul.f64\td16, d17, d11\n-\tvfma.f64\td16, d14, d15\n-\tvnmul.f64\td19, d16, d19\n-\tvmul.f64\td18, d18, d16\n-\tvfma.f64\td19, d21, d6\n-\tvmul.f64\td28, d28, d16\n-\tvmul.f64\td25, d25, d16\n-\tvstr\td18, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td28, [r5, #-16]\n-\tvstr\td25, [r5, #-8]\n-\tvstmia\tr9!, {d19}\n-\tbne.w\tc76 <__gridxc_gga_MOD_b88formx.constprop.0+0xfe>\n-\tvmul.f64\td20, d20, d26\n-\tvldr\td16, [sp, #160]\t@ 0xa0\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tldrd\tlr, sl, [sp, #148]\t@ 0x94\n-\tvdiv.f64\td16, d20, d16\n-\tldr.w\tip, [sp, #156]\t@ 0x9c\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvldr\td6, [sp, #80]\t@ 0x50\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvdiv.f64\td4, d7, d6\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvldr\td3, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d0, d5\n+\tvldr\td5, [sp, #16]\n+\tvmul.f64\td14, d14, d6\n+\tvldr\td2, [sp, #96]\t@ 0x60\n+\tvldr\td1, [sp, #88]\t@ 0x58\n+\tvldr\td0, [r4, #-24]\t@ 0xffffffe8\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tvadd.f64\td0, d0, d0\n+\tcmp\tr9, r3\n+\tvmla.f64\td13, d4, d13\n+\tvldr\td4, [r6, #-8]\n+\tvdiv.f64\td6, d13, d5\n+\tvldr\td5, [sp, #24]\n+\tvmla.f64\td7, d6, d5\n+\tvdiv.f64\td6, d12, d9\n+\tvdiv.f64\td5, d12, d10\n+\tvmul.f64\td7, d7, d14\n+\tvnmls.f64\td7, d11, d3\n+\tvldr\td3, [pc, #312]\t@ 1008 <__gridxc_gga_MOD_b88formx.constprop.0+0x398>\n+\tvmul.f64\td3, d2, d3\n+\tvdiv.f64\td2, d3, d1\n+\tvldr\td3, [sp, #8]\n+\tvldr\td1, [r4, #-16]\n+\tvadd.f64\td1, d1, d1\n+\tvadd.f64\td2, d2, d6\n+\tvldr\td6, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td6, d9, d6\n+\tvldr\td9, [sp, #32]\n+\tvmla.f64\td3, d9, d6\n+\tvmul.f64\td0, d0, d6\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td0, d0, d5\n+\tvmul.f64\td1, d1, d5\n+\tvstr\td3, [sp, #8]\n+\tvldr\td3, [r4, #-8]\n+\tvadd.f64\td3, d3, d3\n+\tvmul.f64\td3, d3, d6\n+\tvmul.f64\td6, d8, d6\n+\tvmul.f64\td8, d8, d5\n+\tvmul.f64\td6, d2, d6\n+\tvmul.f64\td3, d3, d5\n+\tvmul.f64\td0, d0, d8\n+\tvmul.f64\td1, d1, d8\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td3, d3, d8\n+\tvmul.f64\td0, d0, d7\n+\tvmul.f64\td1, d1, d7\n+\tvnmls.f64\td6, d9, d4\n+\tvmul.f64\td3, d3, d7\n+\tvstr\td0, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td1, [r5, #-16]\n+\tvstr\td3, [r5, #-8]\n+\tvstmia\tsl!, {d6}\n+\tbne.w\td82 <__gridxc_gga_MOD_b88formx.constprop.0+0x112>\n+\tvldr\td7, [sp, #8]\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tldr.w\tlr, [sp, #140]\t@ 0x8c\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #144]\t@ 0x90\n+\tldr.w\tip, [sp, #152]\t@ 0x98\n \tcmp.w\tlr, #0\n-\tvstr\td16, [r3]\n-\tble.n\teac <__gridxc_gga_MOD_b88formx.constprop.0+0x334>\n-\tldrd\tr2, r3, [sp, #192]\t@ 0xc0\n-\tstrd\tr2, r3, [sl]\n-\tldrd\tr2, r3, [sp, #256]\t@ 0x100\n+\tvdiv.f64\td6, d7, d6\n+\tvstr\td6, [r3]\n+\tble.n\tfce <__gridxc_gga_MOD_b88formx.constprop.0+0x35e>\n+\tldr\tr1, [sp, #156]\t@ 0x9c\n+\tcmp.w\tlr, #1\n+\tldrd\tr2, r3, [sp, #184]\t@ 0xb8\n+\tstrd\tr2, r3, [r1]\n+\tldrd\tr2, r3, [sp, #248]\t@ 0xf8\n \tstrd\tr2, r3, [ip]\n-\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n+\tldrd\tr2, r3, [sp, #256]\t@ 0x100\n \tstrd\tr2, r3, [ip, #8]\n-\tldrd\tr2, r3, [sp, #272]\t@ 0x110\n-\tcmp.w\tlr, #1\n+\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n \tstrd\tr2, r3, [ip, #16]\n-\tbeq.n\teac <__gridxc_gga_MOD_b88formx.constprop.0+0x334>\n-\tldrd\tr2, r3, [sp, #200]\t@ 0xc8\n-\tstrd\tr2, r3, [sl, #8]\n-\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n+\tbeq.n\tfce <__gridxc_gga_MOD_b88formx.constprop.0+0x35e>\n+\tldrd\tr2, r3, [sp, #192]\t@ 0xc0\n+\tstrd\tr2, r3, [r1, #8]\n+\tldrd\tr2, r3, [sp, #280]\t@ 0x118\n \tstrd\tr2, r3, [ip, #32]\n-\tldrd\tr0, r1, [sp, #280]\t@ 0x118\n+\tldrd\tr0, r1, [sp, #272]\t@ 0x110\n \tstrd\tr0, r1, [ip, #24]\n-\tldrd\tr2, r3, [sp, #296]\t@ 0x128\n+\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n \tstrd\tr2, r3, [ip, #40]\t@ 0x28\n-\tldr\tr2, [pc, #148]\t@ (f44 <__gridxc_gga_MOD_b88formx.constprop.0+0x3cc>)\n-\tldr\tr3, [pc, #140]\t@ (f3c <__gridxc_gga_MOD_b88formx.constprop.0+0x3c4>)\n+\tldr\tr2, [pc, #76]\t@ (101c <__gridxc_gga_MOD_b88formx.constprop.0+0x3ac>)\n+\tldr\tr3, [pc, #64]\t@ (1014 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #356]\t@ 0x164\n+\tldr\tr3, [sp, #348]\t@ 0x15c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\tf1a <__gridxc_gga_MOD_b88formx.constprop.0+0x3a2>\n-\tadd\tsp, #364\t@ 0x16c\n+\tbne.n\t107a <__gridxc_gga_MOD_b88formx.constprop.0+0x40a>\n+\tadd\tsp, #356\t@ 0x164\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td19, [r5]\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td18, [r5, #8]\n-\tadd\tr4, sp, #304\t@ 0x130\n-\tvldr\td17, [r5, #16]\n-\tvmul.f64\td21, d16, d20\n-\tvldr\td22, [pc, #60]\t@ f20 <__gridxc_gga_MOD_b88formx.constprop.0+0x3a8>\n-\tvmul.f64\td19, d19, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmaxnm.f64\td16, d16, d22\n-\tvstr\td21, [sp, #176]\t@ 0xb0\n-\tvstr\td21, [sp, #184]\t@ 0xb8\n-\tvstr\td19, [sp, #304]\t@ 0x130\n-\tvstr\td19, [sp, #328]\t@ 0x148\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n-\tvstr\td18, [sp, #312]\t@ 0x138\n-\tvstr\td18, [sp, #336]\t@ 0x150\n-\tvstr\td17, [sp, #320]\t@ 0x140\n-\tvstr\td17, [sp, #344]\t@ 0x158\n-\tb.n\tc06 <__gridxc_gga_MOD_b88formx.constprop.0+0x8e>\n-\tbl\t0 <__stack_chk_fail>\n- R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n+\t...\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x000003a2\n+\t.word\t0x00000382\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002f2\n+\t.word\t0x000002c2\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000090\n+\t.word\t0x00000046\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\tvldr\td2, [pc, #92]\t@ 1080 <__gridxc_gga_MOD_b88formx.constprop.0+0x410>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r5]\n+\tadd\tr4, sp, #296\t@ 0x128\n+\tvldr\td5, [r5, #8]\n+\tvmul.f64\td1, d7, d3\n+\tvcmpe.f64\td7, d2\n+\tvldr\td6, [r5, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvstr\td1, [sp, #168]\t@ 0xa8\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td1, [sp, #176]\t@ 0xb0\n+\tvstr\td4, [sp, #296]\t@ 0x128\n+\tvstr\td4, [sp, #320]\t@ 0x140\n+\tvstr\td5, [sp, #304]\t@ 0x130\n+\tvstr\td5, [sp, #328]\t@ 0x148\n+\tit\tlt\n+\tvmovlt.f64\td7, d2\n+\tvstr\td6, [sp, #312]\t@ 0x138\n+\tvstr\td6, [sp, #336]\t@ 0x150\n+\tvstr\td7, [sp, #144]\t@ 0x90\n+\tb.n\td0c <__gridxc_gga_MOD_b88formx.constprop.0+0x9c>\n+\tbl\t0 <__stack_chk_fail>\n+ R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n+\t.word\t0x812dea11\n+\t.word\t0x3d719799\n \n-00000f48 <__gridxc_gga_MOD_c09x>:\n+00001088 <__gridxc_gga_MOD_c09x>:\n __gridxc_gga_MOD_c09x.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3720]\t@ 0xe88\n-\tldr\tr5, [pc, #960]\t@ (1320 <__gridxc_gga_MOD_c09x+0x3d8>)\n-\tsub\tsp, #276\t@ 0x114\n-\tldr\tr4, [pc, #960]\t@ (1324 <__gridxc_gga_MOD_c09x+0x3dc>)\n+\tstr.w\tr0, [ip, #3728]\t@ 0xe90\n+\tldr\tr5, [pc, #912]\t@ (1430 <__gridxc_gga_MOD_c09x+0x3a8>)\n+\tsub\tsp, #268\t@ 0x10c\n+\tldr\tr4, [pc, #912]\t@ (1434 <__gridxc_gga_MOD_c09x+0x3ac>)\n \tadd\tr5, pc\n-\tldr.w\tlr, [r1]\n-\tldr\tr1, [sp, #376]\t@ 0x178\n-\tldrd\tfp, ip, [sp, #388]\t@ 0x184\n-\tcmp.w\tlr, #1\n+\tldr\tr7, [r1, #0]\n+\tldr\tr1, [sp, #368]\t@ 0x170\n+\tldrd\tlr, ip, [sp, #384]\t@ 0x180\n+\tcmp\tr7, #1\n \tldr\tr4, [r5, r4]\n \tmov\tr5, r3\n-\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tldr\tr3, [sp, #372]\t@ 0x174\n \tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #268]\t@ 0x10c\n+\tstr\tr4, [sp, #260]\t@ 0x104\n \tmov.w\tr4, #0\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #384]\t@ 0x180\n-\tldr.w\tsl, [sp, #396]\t@ 0x18c\n-\tvldr\td9, [r2]\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tstr\tr0, [sp, #36]\t@ 0x24\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tbeq.w\t1286 <__gridxc_gga_MOD_c09x+0x33e>\n-\tadd\tr4, sp, #216\t@ 0xd8\n-\tvldr\td16, [r2, #8]\n-\tmov\tr7, r4\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #376]\t@ 0x178\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tvldr\td7, [r2]\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tstr\tr0, [sp, #28]\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tbeq.w\t1440 <__gridxc_gga_MOD_c09x+0x3b8>\n+\tvldr\td5, [r2, #8]\n+\tadd\tr4, sp, #208\t@ 0xd0\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tmov\tr8, r4\n+\tvldr\td6, [pc, #776]\t@ 13e8 <__gridxc_gga_MOD_c09x+0x360>\n+\tadd\tr6, sp, #232\t@ 0xe8\n+\tvadd.f64\td7, d5, d7\n \tldr\tr0, [r5, #0]\n \tldr\tr1, [r5, #4]\n-\tadd\tr6, sp, #240\t@ 0xf0\n \tldr\tr2, [r5, #8]\n-\tvadd.f64\td18, d16, d9\n \tldr\tr3, [r5, #12]\n-\tstmia\tr7!, {r0, r1, r2, r3}\n+\tvcmpe.f64\td7, d6\n+\tstmia.w\tr8!, {r0, r1, r2, r3}\n \tldr\tr0, [r5, #16]\n \tldr\tr1, [r5, #20]\n-\tstmia\tr7!, {r0, r1}\n-\tvldr\td17, [pc, #808]\t@ 12e0 <__gridxc_gga_MOD_c09x+0x398>\n-\tvstr\td16, [sp, #96]\t@ 0x60\n-\tvstr\td9, [sp, #88]\t@ 0x58\n-\tldr\tr2, [r5, #32]\n-\tvmaxnm.f64\td16, d18, d17\n+\tstmia.w\tr8!, {r0, r1}\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [sp, #88]\t@ 0x58\n \tldr\tr0, [r5, #24]\n \tldr\tr1, [r5, #28]\n+\tldr\tr2, [r5, #32]\n \tldr\tr3, [r5, #36]\t@ 0x24\n \tstmia\tr6!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tldr\tr0, [r5, #40]\t@ 0x28\n \tldr\tr1, [r5, #44]\t@ 0x2c\n \tstmia\tr6!, {r0, r1}\n-\tvstr\td16, [sp, #64]\t@ 0x40\n-\tvldr\td17, [sp, #224]\t@ 0xe0\n-\tadd\tr3, sp, #136\t@ 0x88\n-\tvldr\td16, [sp, #248]\t@ 0xf8\n-\tvmov.i64\td13, #0x0000000000000000\n-\tvldr\td21, [sp, #216]\t@ 0xd8\n-\tadd.w\tr8, sp, #88\t@ 0x58\n-\tvldr\td20, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td18, [sp, #256]\t@ 0x100\n-\tvfma.f64\td17, d21, d21\n-\tvldr\td19, [sp, #232]\t@ 0xe8\n-\tvfma.f64\td16, d20, d20\n-\tstr.w\tsl, [sp, #72]\t@ 0x48\n-\tvldr\td15, [pc, #720]\t@ 12e0 <__gridxc_gga_MOD_c09x+0x398>\n-\tadd\tr7, sp, #120\t@ 0x78\n-\tadd\tr6, sp, #152\t@ 0x98\n-\tadd\tr5, sp, #168\t@ 0xa8\n-\tvfma.f64\td17, d19, d19\n-\tmov\tsl, r3\n-\tvfma.f64\td16, d18, d18\n-\tadd.w\tr9, sp, #104\t@ 0x68\n-\tadd\tr2, sp, #80\t@ 0x50\n-\tstr.w\tr9, [sp, #32]\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tstrd\tlr, fp, [sp, #52]\t@ 0x34\n-\tstr.w\tip, [sp, #60]\t@ 0x3c\n-\tvsqrt.f64\td18, d17\n-\tvsqrt.f64\td17, d16\n-\tvstr\td18, [sp, #136]\t@ 0x88\n-\tvstr\td17, [sp, #144]\t@ 0x90\n-\tvldmia\tr8!, {d9}\n-\tmov\tfp, r7\n-\tvldmia\tsl!, {d14}\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tadd.w\tr9, sp, #80\t@ 0x50\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tadd.w\tr8, sp, #112\t@ 0x70\n+\tvldr\td2, [sp, #208]\t@ 0xd0\n+\tadd.w\tfp, sp, #128\t@ 0x80\n+\tvldr\td3, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td6, d2, d2\n+\tvldr\td4, [sp, #224]\t@ 0xe0\n+\tvmla.f64\td7, d3, d3\n+\tvldr\td1, [pc, #664]\t@ 13f0 <__gridxc_gga_MOD_c09x+0x368>\n+\tadd\tr6, sp, #144\t@ 0x90\n+\tadd\tr5, sp, #160\t@ 0xa0\n+\tadd.w\tsl, sp, #96\t@ 0x60\n+\tadd\tr3, sp, #72\t@ 0x48\n+\tvmla.f64\td6, d4, d4\n+\tvstr\td1, [sp, #8]\n+\tvmla.f64\td7, d5, d5\n+\tvldr\td1, [pc, #628]\t@ 13e8 <__gridxc_gga_MOD_c09x+0x360>\n+\tstr.w\tsl, [sp, #24]\n+\tstr\tr3, [sp, #32]\n+\tstrd\tr7, lr, [sp, #44]\t@ 0x2c\n+\tstr.w\tip, [sp, #52]\t@ 0x34\n+\tvsqrt.f64\td5, d6\n+\tvsqrt.f64\td6, d7\n+\tvstr\td5, [sp, #128]\t@ 0x80\n+\tvstr\td6, [sp, #136]\t@ 0x88\n+\tvldmia\tr9!, {d8}\n+\tmov\tr7, r8\n+\tvldmia\tfp!, {d10}\n+\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #596]\t@ 13f8 <__gridxc_gga_MOD_c09x+0x370>\n \tadds\tr4, #24\n-\tvldr\td16, [pc, #660]\t@ 12e8 <__gridxc_gga_MOD_c09x+0x3a0>\n+\tvadd.f64\td8, d8, d8\n+\tvstr\td1, [sp, #16]\n+\tvadd.f64\td10, d10, d10\n+\tvmov.f64\td14, d12\n \tadds\tr5, #24\n-\tvadd.f64\td9, d9, d9\n-\tvldr\td8, [pc, #656]\t@ 12f0 <__gridxc_gga_MOD_c09x+0x3a8>\n-\tvadd.f64\td14, d14, d14\n-\tvmaxnm.f64\td9, d9, d15\n-\tvmaxnm.f64\td14, d14, d15\n-\tvmul.f64\td0, d9, d16\n-\tvstmia\tr7!, {d9}\n+\tvcmpe.f64\td8, d1\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td10, d1\n+\tit\tlt\n+\tvmovlt.f64\td8, d1\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d8, d7\n+\tvstmia\tr8!, {d8}\n+\tit\tlt\n+\tvmovlt.f64\td10, d1\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td26, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td11, d9, d0\n-\tvstr\td0, [sp, #16]\n-\tvmul.f64\td16, d14, d26\n-\tvstr\td26, [sp, #24]\n-\tvdiv.f64\td10, d16, d11\n-\tvldr\td16, [pc, #612]\t@ 12f8 <__gridxc_gga_MOD_c09x+0x3b0>\n-\tvmul.f64\td25, d10, d10\n-\tvnmul.f64\td0, d16, d25\n-\tvstr\td25, [sp, #8]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td15, d8, d0\n+\tvmov.f64\td11, d0\n+\tvmul.f64\td7, d10, d7\n+\tvdiv.f64\td9, d7, d15\n+\tvldr\td7, [pc, #520]\t@ 1400 <__gridxc_gga_MOD_c09x+0x378>\n+\tvmul.f64\td13, d9, d9\n+\tvnmul.f64\td0, d7, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td18, [pc, #600]\t@ 1300 <__gridxc_gga_MOD_c09x+0x3b8>\n-\tvldr\td25, [sp, #8]\n-\tvmul.f64\td28, d0, d0\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tvldr\td27, [pc, #592]\t@ 1308 <__gridxc_gga_MOD_c09x+0x3c0>\n-\tvmul.f64\td18, d0, d18\n-\tvldr\td23, [pc, #592]\t@ 1310 <__gridxc_gga_MOD_c09x+0x3c8>\n-\tvmul.f64\td21, d25, d0\n-\tvsub.f64\td0, d19, d0\n-\tvmov.f64\td12, d19\n-\tvmul.f64\td27, d28, d27\n-\tldr\tr1, [pc, #596]\t@ (1328 <__gridxc_gga_MOD_c09x+0x3e0>)\n-\tmov\tr2, fp\n-\tvnmul.f64\td18, d10, d18\n+\tvldr\td5, [pc, #512]\t@ 1408 <__gridxc_gga_MOD_c09x+0x380>\n+\tvmul.f64\td4, d0, d0\n+\tvmul.f64\td3, d13, d0\n+\tvldr\td7, [pc, #508]\t@ 1410 <__gridxc_gga_MOD_c09x+0x388>\n+\tmov\tr2, r7\n+\tvmul.f64\td5, d0, d5\n+\tvsub.f64\td0, d12, d0\n+\tldr\tr1, [pc, #536]\t@ (1438 <__gridxc_gga_MOD_c09x+0x3b0>)\n+\tvmul.f64\td6, d9, d4\n \tstr\tr6, [sp, #0]\n-\tvfma.f64\td12, d0, d8\n+\tldrd\tr0, r3, [sp, #28]\n+\tvnmul.f64\td5, d9, d5\n+\tvmla.f64\td14, d0, d7\n \tadd\tr1, pc\n-\tldrd\tr0, r3, [sp, #36]\t@ 0x24\n-\tvstr\td19, [sp, #8]\n-\tvmul.f64\td21, d21, d18\n-\tvnmul.f64\td8, d8, d18\n-\tvfma.f64\td21, d10, d28\n-\tvfma.f64\td12, d25, d27\n \tadds\tr6, #8\n-\tvfma.f64\td8, d21, d23\n+\tvmla.f64\td6, d3, d5\n+\tvmul.f64\td7, d5, d7\n+\tvldr\td5, [pc, #472]\t@ 1418 <__gridxc_gga_MOD_c09x+0x390>\n+\tvmul.f64\td5, d4, d5\n+\tvmla.f64\td14, d5, d13\n+\tvldr\td5, [pc, #468]\t@ 1420 <__gridxc_gga_MOD_c09x+0x398>\n+\tvnmls.f64\td7, d6, d5\n+\tvmov.f64\td13, d7\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td22, [sp, #16]\n-\tvldr\td27, [pc, #528]\t@ 1318 <__gridxc_gga_MOD_c09x+0x3d0>\n-\tvldr\td19, [sp, #8]\n-\tvldr\td25, [r4, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td27, d22, d27\n-\tvldr\td17, [r4, #-16]\n-\tvdiv.f64\td23, d19, d14\n-\tvldr\td16, [r4, #-8]\n-\tvdiv.f64\td21, d19, d9\n-\tvldr\td19, [sp, #80]\t@ 0x50\n-\tvadd.f64\td25, d25, d25\n-\tvadd.f64\td17, d17, d17\n-\tvdiv.f64\td22, d27, d11\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td20, d9, d19\n-\tvldr\td18, [r6, #-8]\n-\tldr\tr3, [sp, #32]\n-\tvldr\td26, [sp, #24]\n-\tcmp\tr8, r3\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td25, d25, d20\n-\tvmul.f64\td19, d20, d10\n-\tvfma.f64\td13, d20, d12\n-\tvmul.f64\td24, d10, d23\n-\tvmul.f64\td20, d25, d23\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvadd.f64\td22, d22, d21\n-\tvmul.f64\td20, d20, d24\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td22, d22, d19\n-\tvmul.f64\td20, d20, d8\n-\tvmul.f64\td17, d17, d8\n-\tvmul.f64\td16, d16, d8\n-\tvnmul.f64\td8, d8, d22\n-\tvfma.f64\td8, d18, d12\n-\tvstr\td20, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tvstmia\tr9!, {d8}\n-\tbne.w\t1046 <__gridxc_gga_MOD_c09x+0xfe>\n-\tvmul.f64\td13, d13, d26\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldrd\tlr, fp, [sp, #52]\t@ 0x34\n-\tvdiv.f64\td16, d13, d16\n-\tldr.w\tip, [sp, #60]\t@ 0x3c\n-\tldr.w\tsl, [sp, #72]\t@ 0x48\n-\tcmp.w\tlr, #0\n-\tvstr\td16, [r3]\n-\tble.n\t127a <__gridxc_gga_MOD_c09x+0x332>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tcmp.w\tlr, #1\n-\tldrd\tr2, r3, [sp, #104]\t@ 0x68\n+\tvdiv.f64\td7, d12, d8\n+\tvldr\td4, [pc, #456]\t@ 1428 <__gridxc_gga_MOD_c09x+0x3a0>\n+\tvdiv.f64\td6, d12, d10\n+\tvldr\td0, [r4, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [r4, #-16]\n+\tvmul.f64\td4, d11, d4\n+\tvldr\td5, [r6, #-8]\n+\tvadd.f64\td0, d0, d0\n+\tldr\tr3, [sp, #24]\n+\tvadd.f64\td2, d2, d2\n+\tvldr\td1, [sp, #16]\n+\tcmp\tr9, r3\n+\tvdiv.f64\td3, d4, d15\n+\tvldr\td4, [sp, #8]\n+\tvadd.f64\td3, d3, d7\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvmul.f64\td7, d8, d7\n+\tvmla.f64\td4, d7, d14\n+\tvmul.f64\td0, d0, d7\n+\tvmul.f64\td2, d2, d7\n+\tvmul.f64\td0, d0, d6\n+\tvmul.f64\td2, d2, d6\n+\tvstr\td4, [sp, #8]\n+\tvldr\td4, [r4, #-8]\n+\tvadd.f64\td4, d4, d4\n+\tvmul.f64\td4, d4, d7\n+\tvmul.f64\td7, d7, d9\n+\tvmul.f64\td9, d9, d6\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td4, d4, d6\n+\tvmul.f64\td0, d0, d9\n+\tvmul.f64\td2, d2, d9\n+\tvmul.f64\td7, d7, d13\n+\tvmul.f64\td4, d4, d9\n+\tvmul.f64\td0, d0, d13\n+\tvmul.f64\td2, d2, d13\n+\tvnmls.f64\td7, d14, d5\n+\tvmul.f64\td4, d4, d13\n+\tvstr\td0, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td2, [r5, #-16]\n+\tvstr\td4, [r5, #-8]\n+\tvstmia\tsl!, {d7}\n+\tbne.w\t1192 <__gridxc_gga_MOD_c09x+0x10a>\n+\tvldr\td7, [sp, #8]\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldrd\tr7, lr, [sp, #44]\t@ 0x2c\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tldr.w\tip, [sp, #52]\t@ 0x34\n+\tcmp\tr7, #0\n+\tvdiv.f64\td6, d7, d6\n+\tvstr\td6, [r3]\n+\tble.n\t13d6 <__gridxc_gga_MOD_c09x+0x34e>\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tcmp\tr7, #1\n+\tldrd\tr2, r3, [sp, #96]\t@ 0x60\n \tstrd\tr2, r3, [r1]\n+\tldrd\tr2, r3, [sp, #160]\t@ 0xa0\n+\tstrd\tr2, r3, [lr]\n \tldrd\tr2, r3, [sp, #168]\t@ 0xa8\n-\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [lr, #8]\n \tldrd\tr2, r3, [sp, #176]\t@ 0xb0\n-\tstrd\tr2, r3, [ip, #8]\n-\tldrd\tr2, r3, [sp, #184]\t@ 0xb8\n-\tstrd\tr2, r3, [ip, #16]\n-\tmov.w\tr2, #0\n-\tmov.w\tr3, #0\n-\tbeq.n\t1262 <__gridxc_gga_MOD_c09x+0x31a>\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tstrd\tr2, r3, [fp, #8]\n-\tstrd\tr2, r3, [fp]\n-\tstrd\tr2, r3, [r0]\n-\tstrd\tr2, r3, [sl]\n-\tstrd\tr2, r3, [sl, #8]\n-\tstrd\tr2, r3, [sl, #16]\n-\tstrd\tr2, r3, [sl, #24]\n-\tstrd\tr2, r3, [sl, #32]\n-\tstrd\tr2, r3, [sl, #40]\t@ 0x28\n-\tldrd\tr2, r3, [sp, #112]\t@ 0x70\n+\tstrd\tr2, r3, [lr, #16]\n+\tbeq.n\t13b8 <__gridxc_gga_MOD_c09x+0x330>\n+\tldrd\tr2, r3, [sp, #104]\t@ 0x68\n \tstrd\tr2, r3, [r1, #8]\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldrd\tr2, r3, [sp, #184]\t@ 0xb8\n+\tstrd\tr2, r3, [lr, #24]\n+\tldrd\tr2, r3, [sp, #192]\t@ 0xc0\n+\tstrd\tr2, r3, [lr, #32]\n \tldrd\tr2, r3, [sp, #200]\t@ 0xc8\n+\tstrd\tr2, r3, [lr, #40]\t@ 0x28\n+\tmovs\tr2, #0\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [r1]\n+\tstrd\tr2, r3, [r1, #8]\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [ip, #8]\n+\tstrd\tr2, r3, [r1]\n+\tstrd\tr2, r3, [ip, #16]\n+\tstrd\tr2, r3, [ip, #24]\n \tstrd\tr2, r3, [ip, #32]\n-\tldrd\tr0, r1, [sp, #192]\t@ 0xc0\n-\tstrd\tr0, r1, [ip, #24]\n-\tldrd\tr2, r3, [sp, #208]\t@ 0xd0\n \tstrd\tr2, r3, [ip, #40]\t@ 0x28\n-\tldr\tr2, [pc, #228]\t@ (132c <__gridxc_gga_MOD_c09x+0x3e4>)\n-\tldr\tr3, [pc, #220]\t@ (1324 <__gridxc_gga_MOD_c09x+0x3dc>)\n+\tldr\tr2, [pc, #160]\t@ (143c <__gridxc_gga_MOD_c09x+0x3b4>)\n+\tldr\tr3, [pc, #148]\t@ (1434 <__gridxc_gga_MOD_c09x+0x3ac>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #268]\t@ 0x10c\n+\tldr\tr3, [sp, #260]\t@ 0x104\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t12d6 <__gridxc_gga_MOD_c09x+0x38e>\n-\tadd\tsp, #276\t@ 0x114\n+\tbne.n\t149a <__gridxc_gga_MOD_c09x+0x412>\n+\tadd\tsp, #268\t@ 0x10c\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tstrd\tr2, r3, [fp]\n-\tstrd\tr2, r3, [sl]\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tmovs\tr2, #0\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [ip, #8]\n \tstrd\tr2, r3, [r1]\n-\tstrd\tr2, r3, [sl, #8]\n-\tstrd\tr2, r3, [sl, #16]\n-\tb.n\t1244 <__gridxc_gga_MOD_c09x+0x2fc>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tstrd\tr2, r3, [ip, #16]\n+\tstrd\tr2, r3, [r1]\n+\tb.n\t139a <__gridxc_gga_MOD_c09x+0x312>\n+\tldr\tr1, [sp, #36]\t@ 0x24\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\t1244 <__gridxc_gga_MOD_c09x+0x2fc>\n-\tvldr\td18, [r5]\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n-\tvldr\td17, [r5, #8]\n-\tadd\tr4, sp, #216\t@ 0xd8\n-\tvldr\td16, [r5, #16]\n-\tvmul.f64\td20, d9, d19\n-\tvldr\td21, [pc, #64]\t@ 12e0 <__gridxc_gga_MOD_c09x+0x398>\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmaxnm.f64\td19, d9, d21\n-\tvstr\td20, [sp, #88]\t@ 0x58\n-\tvstr\td20, [sp, #96]\t@ 0x60\n-\tvstr\td18, [sp, #216]\t@ 0xd8\n-\tvstr\td18, [sp, #240]\t@ 0xf0\n-\tvstr\td19, [sp, #64]\t@ 0x40\n-\tvstr\td17, [sp, #224]\t@ 0xe0\n-\tvstr\td17, [sp, #248]\t@ 0xf8\n-\tvstr\td16, [sp, #232]\t@ 0xe8\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tb.n\tfd8 <__gridxc_gga_MOD_c09x+0x90>\n-\tbl\t0 <__stack_chk_fail>\n- R_ARM_THM_CALL\t__stack_chk_fail\n+\tb.n\t139a <__gridxc_gga_MOD_c09x+0x312>\n \tnop\n \tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n+\t...\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x1eb851ec\n-\t.word\t0x3ff3eb85\n \t.word\t0x10cb295f\n \t.word\t0x3f98bac7\n \t.word\t0x10cb295f\n \t.word\t0x3fa8bac7\n+\t.word\t0x1eb851ec\n+\t.word\t0x3ff3eb85\n \t.word\t0x80000000\n \t.word\t0x3faf9724\n \t.word\t0x80000000\n \t.word\t0x3fbf9724\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x000003ba\n+\t.word\t0x0000038a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000246\n+\t.word\t0x00000202\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000e0\n+\t.word\t0x0000009a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\tvldr\td2, [pc, #92]\t@ 14a0 <__gridxc_gga_MOD_c09x+0x418>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r5]\n+\tadd\tr4, sp, #208\t@ 0xd0\n+\tvldr\td5, [r5, #8]\n+\tvmul.f64\td1, d7, d3\n+\tvcmpe.f64\td7, d2\n+\tvldr\td6, [r5, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvstr\td1, [sp, #80]\t@ 0x50\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td1, [sp, #88]\t@ 0x58\n+\tvstr\td4, [sp, #208]\t@ 0xd0\n+\tvstr\td4, [sp, #232]\t@ 0xe8\n+\tvstr\td5, [sp, #216]\t@ 0xd8\n+\tvstr\td5, [sp, #240]\t@ 0xf0\n+\tit\tlt\n+\tvmovlt.f64\td7, d2\n+\tvstr\td6, [sp, #224]\t@ 0xe0\n+\tvstr\td6, [sp, #248]\t@ 0xf8\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tb.n\t1122 <__gridxc_gga_MOD_c09x+0x9a>\n+\tbl\t0 <__stack_chk_fail>\n+ R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n+\t.word\t0x812dea11\n+\t.word\t0x3d719799\n \n-00001330 <__gridxc_gga_MOD_b88kbmx>:\n+000014a8 <__gridxc_gga_MOD_b88kbmx>:\n __gridxc_gga_MOD_b88kbmx.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #60\t@ 0x3c\n \tmov\tr4, r1\n \tmov\tr5, r3\n-\tldr\tr6, [pc, #192]\t@ (1408 <__gridxc_gga_MOD_b88kbmx+0xd8>)\n+\tldr\tr6, [pc, #192]\t@ (1580 <__gridxc_gga_MOD_b88kbmx+0xd8>)\n \tmov\tr3, r0\n \tadd\tr0, sp, #24\n \tldr\tr1, [sp, #88]\t@ 0x58\n \tadd\tr6, pc\n \tstr\tr1, [sp, #12]\n \tmov\tr1, r2\n \tstr\tr4, [sp, #0]\n \tadd\tr2, sp, #32\n \tstrd\tr1, r5, [sp, #4]\n \tadd\tr1, sp, #40\t@ 0x28\n \tldr.w\tr8, [sp, #92]\t@ 0x5c\n \tldr\tr5, [r4, #0]\n-\tldr\tr4, [pc, #164]\t@ (140c <__gridxc_gga_MOD_b88kbmx+0xdc>)\n+\tldr\tr4, [pc, #164]\t@ (1584 <__gridxc_gga_MOD_b88kbmx+0xdc>)\n \tldr.w\tr9, [sp, #100]\t@ 0x64\n \tldr\tr4, [r6, r4]\n-\tadd\tr7, pc, #128\t@ (adr r7, 13f0 <__gridxc_gga_MOD_b88kbmx+0xc0>)\n+\tadd\tr7, pc, #128\t@ (adr r7, 1568 <__gridxc_gga_MOD_b88kbmx+0xc0>)\n \tldrd\tr6, r7, [r7]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #52]\t@ 0x34\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #16]\n \tstrd\tr6, r7, [sp, #32]\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tadd\tr7, pc, #112\t@ (adr r7, 13f8 <__gridxc_gga_MOD_b88kbmx+0xc8>)\n+\tadd\tr7, pc, #112\t@ (adr r7, 1570 <__gridxc_gga_MOD_b88kbmx+0xc8>)\n \tldrd\tr6, r7, [r7]\n \tstr\tr4, [sp, #20]\n \tstrd\tr6, r7, [sp, #40]\t@ 0x28\n-\tadd\tr7, pc, #108\t@ (adr r7, 1400 <__gridxc_gga_MOD_b88kbmx+0xd0>)\n+\tadd\tr7, pc, #108\t@ (adr r7, 1578 <__gridxc_gga_MOD_b88kbmx+0xd0>)\n \tldrd\tr6, r7, [r7]\n \tstrd\tr6, r7, [sp, #24]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tmovs\tr6, #0\n-\tbl\tb78 <__gridxc_gga_MOD_b88formx.constprop.0>\n+\tbl\tc70 <__gridxc_gga_MOD_b88formx.constprop.0>\n \tmovs\tr7, #0\n \tcmp\tr5, #0\n \tstrd\tr6, r7, [r8]\n-\tble.n\t13d0 <__gridxc_gga_MOD_b88kbmx+0xa0>\n+\tble.n\t1548 <__gridxc_gga_MOD_b88kbmx+0xa0>\n \tlsls\tr2, r5, #3\n \tmov\tr0, r9\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmovs\tr2, #0\n \tmov\tr3, r4\n \tadds\tr2, #1\n \tstrd\tr6, r7, [r3]\n \tstrd\tr6, r7, [r3, #8]\n \tcmp\tr2, r5\n \tstrd\tr6, r7, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t13ba <__gridxc_gga_MOD_b88kbmx+0x8a>\n-\tldr\tr2, [pc, #60]\t@ (1410 <__gridxc_gga_MOD_b88kbmx+0xe0>)\n-\tldr\tr3, [pc, #56]\t@ (140c <__gridxc_gga_MOD_b88kbmx+0xdc>)\n+\tbne.n\t1532 <__gridxc_gga_MOD_b88kbmx+0x8a>\n+\tldr\tr2, [pc, #60]\t@ (1588 <__gridxc_gga_MOD_b88kbmx+0xe0>)\n+\tldr\tr3, [pc, #56]\t@ (1584 <__gridxc_gga_MOD_b88kbmx+0xdc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #52]\t@ 0x34\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t13ea <__gridxc_gga_MOD_b88kbmx+0xba>\n+\tbne.n\t1562 <__gridxc_gga_MOD_b88kbmx+0xba>\n \tadd\tsp, #60\t@ 0x3c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \t.word\t0xc13b96ee\n \t.word\t0x401f2ea5\n@@ -1498,85 +1604,85 @@\n \t.word\t0x000000b6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000038\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001414 <__gridxc_gga_MOD_b88x>:\n+0000158c <__gridxc_gga_MOD_b88x>:\n __gridxc_gga_MOD_b88x.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #60\t@ 0x3c\n \tmov\tr4, r1\n \tmov\tr5, r3\n-\tldr\tr6, [pc, #196]\t@ (14f0 <__gridxc_gga_MOD_b88x+0xdc>)\n+\tldr\tr6, [pc, #196]\t@ (1668 <__gridxc_gga_MOD_b88x+0xdc>)\n \tmov\tr3, r0\n \tadd\tr0, sp, #24\n \tldr\tr1, [sp, #88]\t@ 0x58\n \tadd\tr6, pc\n \tstr\tr1, [sp, #12]\n \tmov\tr1, r2\n \tstr\tr4, [sp, #0]\n \tadd\tr2, sp, #32\n \tstrd\tr1, r5, [sp, #4]\n \tadd\tr1, sp, #40\t@ 0x28\n \tldr.w\tr8, [sp, #92]\t@ 0x5c\n \tldr\tr5, [r4, #0]\n-\tldr\tr4, [pc, #168]\t@ (14f4 <__gridxc_gga_MOD_b88x+0xe0>)\n+\tldr\tr4, [pc, #168]\t@ (166c <__gridxc_gga_MOD_b88x+0xe0>)\n \tldr.w\tr9, [sp, #100]\t@ 0x64\n \tldr\tr4, [r6, r4]\n-\tadd\tr7, pc, #132\t@ (adr r7, 14d8 <__gridxc_gga_MOD_b88x+0xc4>)\n+\tadd\tr7, pc, #132\t@ (adr r7, 1650 <__gridxc_gga_MOD_b88x+0xc4>)\n \tldrd\tr6, r7, [r7]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #52]\t@ 0x34\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #16]\n \tstrd\tr6, r7, [sp, #32]\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tadd\tr7, pc, #116\t@ (adr r7, 14e0 <__gridxc_gga_MOD_b88x+0xcc>)\n+\tadd\tr7, pc, #116\t@ (adr r7, 1658 <__gridxc_gga_MOD_b88x+0xcc>)\n \tldrd\tr6, r7, [r7]\n \tstr\tr4, [sp, #20]\n \tstrd\tr6, r7, [sp, #40]\t@ 0x28\n-\tadd\tr7, pc, #112\t@ (adr r7, 14e8 <__gridxc_gga_MOD_b88x+0xd4>)\n+\tadd\tr7, pc, #112\t@ (adr r7, 1660 <__gridxc_gga_MOD_b88x+0xd4>)\n \tldrd\tr6, r7, [r7]\n \tstrd\tr6, r7, [sp, #24]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tmovs\tr6, #0\n-\tbl\tb78 <__gridxc_gga_MOD_b88formx.constprop.0>\n+\tbl\tc70 <__gridxc_gga_MOD_b88formx.constprop.0>\n \tmovs\tr7, #0\n \tcmp\tr5, #0\n \tstrd\tr6, r7, [r8]\n-\tble.n\t14b4 <__gridxc_gga_MOD_b88x+0xa0>\n+\tble.n\t162c <__gridxc_gga_MOD_b88x+0xa0>\n \tlsls\tr2, r5, #3\n \tmov\tr0, r9\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmovs\tr2, #0\n \tmov\tr3, r4\n \tadds\tr2, #1\n \tstrd\tr6, r7, [r3]\n \tstrd\tr6, r7, [r3, #8]\n \tcmp\tr2, r5\n \tstrd\tr6, r7, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t149e <__gridxc_gga_MOD_b88x+0x8a>\n-\tldr\tr2, [pc, #64]\t@ (14f8 <__gridxc_gga_MOD_b88x+0xe4>)\n-\tldr\tr3, [pc, #60]\t@ (14f4 <__gridxc_gga_MOD_b88x+0xe0>)\n+\tbne.n\t1616 <__gridxc_gga_MOD_b88x+0x8a>\n+\tldr\tr2, [pc, #64]\t@ (1670 <__gridxc_gga_MOD_b88x+0xe4>)\n+\tldr\tr3, [pc, #60]\t@ (166c <__gridxc_gga_MOD_b88x+0xe0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #52]\t@ 0x34\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t14ce <__gridxc_gga_MOD_b88x+0xba>\n+\tbne.n\t1646 <__gridxc_gga_MOD_b88x+0xba>\n \tadd\tsp, #60\t@ 0x3c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \tnop.w\n \t.word\t0xc13b96ee\n@@ -1588,281 +1694,287 @@\n \t.word\t0x000000ba\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x0000003c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000014fc <__gridxc_gga_MOD_bhx>:\n+00001674 <__gridxc_gga_MOD_bhx>:\n __gridxc_gga_MOD_bhx.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3640]\t@ 0xe38\n-\tldr.w\tr5, [pc, #1036]\t@ 1920 <__gridxc_gga_MOD_bhx+0x424>\n-\tsub\tsp, #356\t@ 0x164\n-\tldr.w\tr4, [pc, #1036]\t@ 1924 <__gridxc_gga_MOD_bhx+0x428>\n+\tstr.w\tr0, [ip, #3648]\t@ 0xe40\n+\tldr.w\tr5, [pc, #1060]\t@ 1ab0 <__gridxc_gga_MOD_bhx+0x43c>\n+\tsub\tsp, #348\t@ 0x15c\n+\tldr.w\tr4, [pc, #1060]\t@ 1ab4 <__gridxc_gga_MOD_bhx+0x440>\n \tadd\tr5, pc\n-\tldr.w\tlr, [r1]\n-\tldr\tr1, [sp, #456]\t@ 0x1c8\n-\tldrd\tfp, ip, [sp, #468]\t@ 0x1d4\n-\tcmp.w\tlr, #1\n+\tldr\tr7, [r1, #0]\n+\tldr\tr1, [sp, #448]\t@ 0x1c0\n+\tldrd\tlr, ip, [sp, #464]\t@ 0x1d0\n+\tcmp\tr7, #1\n \tldr\tr4, [r5, r4]\n \tmov\tr5, r3\n-\tldr\tr3, [sp, #460]\t@ 0x1cc\n+\tldr\tr3, [sp, #452]\t@ 0x1c4\n \tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #348]\t@ 0x15c\n+\tstr\tr4, [sp, #340]\t@ 0x154\n \tmov.w\tr4, #0\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr3, [sp, #464]\t@ 0x1d0\n-\tldr.w\tsl, [sp, #476]\t@ 0x1dc\n-\tvldr\td16, [r2]\n-\tstr\tr1, [sp, #128]\t@ 0x80\n-\tstr\tr0, [sp, #116]\t@ 0x74\n-\tstr\tr3, [sp, #156]\t@ 0x9c\n-\tbeq.w\t19b4 <__gridxc_gga_MOD_bhx+0x4b8>\n-\tadd\tr4, sp, #296\t@ 0x128\n-\tvldr\td17, [r2, #8]\n-\tmov\tr7, r4\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr3, [sp, #456]\t@ 0x1c8\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr3, [sp, #460]\t@ 0x1cc\n+\tvldr\td7, [r2]\n+\tstr\tr1, [sp, #120]\t@ 0x78\n+\tstr\tr0, [sp, #108]\t@ 0x6c\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tbeq.w\t1b50 <__gridxc_gga_MOD_bhx+0x4dc>\n+\tvldr\td5, [r2, #8]\n+\tadd\tr4, sp, #288\t@ 0x120\n+\tvstr\td7, [sp, #160]\t@ 0xa0\n+\tmov\tr8, r4\n+\tvldr\td6, [pc, #856]\t@ 1a28 <__gridxc_gga_MOD_bhx+0x3b4>\n+\tadd\tr6, sp, #312\t@ 0x138\n+\tvadd.f64\td7, d5, d7\n \tldr\tr0, [r5, #0]\n \tldr\tr1, [r5, #4]\n-\tadd\tr6, sp, #320\t@ 0x140\n \tldr\tr2, [r5, #8]\n \tldr\tr3, [r5, #12]\n-\tstmia\tr7!, {r0, r1, r2, r3}\n+\tvcmpe.f64\td7, d6\n+\tstmia.w\tr8!, {r0, r1, r2, r3}\n \tldr\tr0, [r5, #16]\n \tldr\tr1, [r5, #20]\n-\tstmia\tr7!, {r0, r1}\n-\tvstr\td16, [sp, #168]\t@ 0xa8\n-\tvadd.f64\td16, d17, d16\n-\tvldr\td18, [pc, #812]\t@ 18a0 <__gridxc_gga_MOD_bhx+0x3a4>\n-\tvstr\td17, [sp, #176]\t@ 0xb0\n+\tstmia.w\tr8!, {r0, r1}\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [sp, #168]\t@ 0xa8\n \tldr\tr0, [r5, #24]\n \tldr\tr1, [r5, #28]\n-\tvmaxnm.f64\td16, d16, d18\n \tldr\tr2, [r5, #32]\n \tldr\tr3, [r5, #36]\t@ 0x24\n \tstmia\tr6!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tldr\tr0, [r5, #40]\t@ 0x28\n \tldr\tr1, [r5, #44]\t@ 0x2c\n \tstmia\tr6!, {r0, r1}\n-\tvstr\td16, [sp, #144]\t@ 0x90\n-\tvldr\td17, [sp, #304]\t@ 0x130\n-\tadd\tr3, sp, #216\t@ 0xd8\n-\tvldr\td16, [sp, #328]\t@ 0x148\n-\tvmov.i64\td22, #0x0000000000000000\n-\tvldr\td21, [sp, #296]\t@ 0x128\n-\tadd.w\tr8, sp, #168\t@ 0xa8\n-\tvldr\td20, [sp, #320]\t@ 0x140\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td18, [sp, #336]\t@ 0x150\n-\tvfma.f64\td17, d21, d21\n-\tvldr\td19, [sp, #312]\t@ 0x138\n-\tvfma.f64\td16, d20, d20\n-\tstr.w\tsl, [sp, #152]\t@ 0x98\n-\tvldr\td27, [pc, #728]\t@ 18a0 <__gridxc_gga_MOD_bhx+0x3a4>\n-\tadd\tr7, sp, #200\t@ 0xc8\n-\tadd\tr6, sp, #232\t@ 0xe8\n-\tadd\tr5, sp, #248\t@ 0xf8\n-\tvfma.f64\td17, d19, d19\n-\tmov\tsl, r3\n-\tvfma.f64\td16, d18, d18\n-\tadd.w\tr9, sp, #184\t@ 0xb8\n-\tadd\tr2, sp, #160\t@ 0xa0\n-\tstr.w\tr9, [sp, #112]\t@ 0x70\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tstrd\tlr, fp, [sp, #132]\t@ 0x84\n-\tstr.w\tip, [sp, #140]\t@ 0x8c\n-\tvsqrt.f64\td18, d17\n-\tvsqrt.f64\td17, d16\n-\tvstr\td18, [sp, #216]\t@ 0xd8\n-\tvstr\td17, [sp, #224]\t@ 0xe0\n-\tvldmia\tr8!, {d8}\n-\tmov\tfp, r7\n-\tvldmia\tsl!, {d15}\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tvldr\td6, [sp, #296]\t@ 0x128\n+\tadd.w\tr9, sp, #160\t@ 0xa0\n+\tvldr\td7, [sp, #320]\t@ 0x140\n+\tadd.w\tr8, sp, #192\t@ 0xc0\n+\tvldr\td2, [sp, #288]\t@ 0x120\n+\tadd.w\tfp, sp, #208\t@ 0xd0\n+\tvldr\td3, [sp, #312]\t@ 0x138\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [sp, #328]\t@ 0x148\n+\tvmla.f64\td6, d2, d2\n+\tvldr\td4, [sp, #304]\t@ 0x130\n+\tvmla.f64\td7, d3, d3\n+\tvldr\td1, [pc, #744]\t@ 1a30 <__gridxc_gga_MOD_bhx+0x3bc>\n+\tvldr\td14, [pc, #732]\t@ 1a28 <__gridxc_gga_MOD_bhx+0x3b4>\n+\tadd\tr6, sp, #224\t@ 0xe0\n+\tadd\tr5, sp, #240\t@ 0xf0\n+\tadd.w\tsl, sp, #176\t@ 0xb0\n+\tvmla.f64\td6, d4, d4\n+\tadd\tr3, sp, #152\t@ 0x98\n+\tvmla.f64\td7, d5, d5\n+\tstr.w\tsl, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstrd\tr7, lr, [sp, #124]\t@ 0x7c\n+\tstr.w\tip, [sp, #132]\t@ 0x84\n+\tvstr\td1, [sp, #8]\n+\tvsqrt.f64\td5, d6\n+\tvsqrt.f64\td6, d7\n+\tvstr\td5, [sp, #208]\t@ 0xd0\n+\tvstr\td6, [sp, #216]\t@ 0xd8\n+\tvldmia\tr9!, {d3}\n+\tmov\tr7, r8\n+\tvldmia\tfp!, {d10}\n+\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #676]\t@ 1a38 <__gridxc_gga_MOD_bhx+0x3c4>\n \tadds\tr4, #24\n-\tvldr\td16, [pc, #668]\t@ 18a8 <__gridxc_gga_MOD_bhx+0x3ac>\n+\tvadd.f64\td3, d3, d3\n+\tvldr\td12, [pc, #676]\t@ 1a40 <__gridxc_gga_MOD_bhx+0x3cc>\n+\tvadd.f64\td10, d10, d10\n+\tvldr\td11, [pc, #676]\t@ 1a48 <__gridxc_gga_MOD_bhx+0x3d4>\n \tadds\tr5, #24\n-\tvadd.f64\td8, d8, d8\n-\tvstr\td22, [sp, #104]\t@ 0x68\n-\tvadd.f64\td15, d15, d15\n-\tvstr\td27, [sp, #96]\t@ 0x60\n-\tvldr\td14, [pc, #652]\t@ 18b0 <__gridxc_gga_MOD_bhx+0x3b4>\n-\tvldr\td11, [pc, #656]\t@ 18b8 <__gridxc_gga_MOD_bhx+0x3bc>\n-\tvmaxnm.f64\td8, d8, d27\n-\tvmaxnm.f64\td15, d15, d27\n-\tvmul.f64\td0, d8, d16\n-\tvstmia\tr7!, {d8}\n+\tvcmpe.f64\td3, d14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td10, d14\n+\tit\tlt\n+\tvmovlt.f64\td3, d14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d3, d7\n+\tvstmia\tr8!, {d3}\n+\tit\tlt\n+\tvmovlt.f64\td10, d14\n+\tvstr\td3, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td26, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td25, d8, d0\n-\tvldr\td17, [pc, #632]\t@ 18c0 <__gridxc_gga_MOD_bhx+0x3c4>\n-\tvmul.f64\td19, d15, d26\n-\tvldr\td18, [pc, #632]\t@ 18c8 <__gridxc_gga_MOD_bhx+0x3cc>\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td21, [pc, #632]\t@ 18d0 <__gridxc_gga_MOD_bhx+0x3d4>\n-\tvstr\td0, [sp, #80]\t@ 0x50\n-\tvstr\td26, [sp, #88]\t@ 0x58\n-\tvdiv.f64\td10, d19, d25\n-\tvmov.f64\td1, d21\n-\tvstr\td21, [sp, #72]\t@ 0x48\n-\tvstr\td25, [sp, #64]\t@ 0x40\n-\tvstr\td16, [sp, #8]\n-\tvmul.f64\td12, d10, d10\n-\tvmul.f64\td13, d10, d12\n-\tvfma.f64\td18, d12, d17\n-\tvmul.f64\td20, d13, d13\n-\tvmul.f64\td14, d20, d14\n-\tvstr\td20, [sp, #16]\n-\tvfma.f64\td14, d12, d18\n-\tvadd.f64\td14, d14, d16\n-\tvmov.f64\td0, d14\n+\tvldr\td3, [sp, #16]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvldr\td5, [pc, #624]\t@ 1a50 <__gridxc_gga_MOD_bhx+0x3dc>\n+\tvstr\td0, [sp, #32]\n+\tvmul.f64\td6, d3, d0\n+\tvmul.f64\td7, d10, d7\n+\tvstr\td3, [sp, #96]\t@ 0x60\n+\tvdiv.f64\td9, d7, d6\n+\tvstr\td6, [sp, #16]\n+\tvldr\td6, [pc, #604]\t@ 1a58 <__gridxc_gga_MOD_bhx+0x3e4>\n+\tvmul.f64\td7, d9, d9\n+\tvmul.f64\td4, d9, d7\n+\tvmla.f64\td6, d7, d5\n+\tvldr\td5, [pc, #596]\t@ 1a60 <__gridxc_gga_MOD_bhx+0x3ec>\n+\tvstr\td7, [sp, #24]\n+\tvmul.f64\td15, d4, d4\n+\tvmov.f64\td1, d5\n+\tvstr\td4, [sp, #88]\t@ 0x58\n+\tvstr\td5, [sp, #80]\t@ 0x50\n+\tvmul.f64\td12, d15, d12\n+\tvmul.f64\td11, d15, d11\n+\tvmla.f64\td12, d6, d7\n+\tvadd.f64\td12, d12, d13\n+\tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tpow\n-\tvldr\td20, [sp, #16]\n-\tvldr\td18, [pc, #564]\t@ 18d8 <__gridxc_gga_MOD_bhx+0x3dc>\n-\tvmov.f64\td9, d0\n-\tvldr\td16, [sp, #8]\n-\tmov\tr2, fp\n-\tvmul.f64\td11, d20, d11\n-\tvldr\td19, [pc, #556]\t@ 18e0 <__gridxc_gga_MOD_bhx+0x3e4>\n-\tldr\tr1, [pc, #624]\t@ (1928 <__gridxc_gga_MOD_bhx+0x42c>)\n-\tvmov.f64\td24, d16\n+\tvldr\td6, [pc, #556]\t@ 1a68 <__gridxc_gga_MOD_bhx+0x3f4>\n+\tvstr\td15, [sp, #40]\t@ 0x28\n+\tvmov.f64\td4, d13\n+\tldr\tr1, [pc, #624]\t@ (1ab8 <__gridxc_gga_MOD_bhx+0x444>)\n+\tvmov.f64\td8, d0\n+\tvadd.f64\td6, d11, d6\n \tstr\tr6, [sp, #0]\n-\tvfma.f64\td24, d12, d19\n+\tldrd\tr0, r3, [sp, #108]\t@ 0x6c\n+\tmov\tr2, r7\n \tadd\tr1, pc\n-\tvadd.f64\td18, d11, d18\n-\tvadd.f64\td31, d11, d16\n-\tvmul.f64\td12, d12, d13\n-\tvstr\td20, [sp, #56]\t@ 0x38\n-\tldrd\tr0, r3, [sp, #116]\t@ 0x74\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvdiv.f64\td19, d16, d18\n-\tvstr\td31, [sp, #48]\t@ 0x30\n-\tvdiv.f64\td28, d16, d31\n \tadds\tr6, #8\n-\tvstr\td24, [sp, #24]\n-\tvmul.f64\td11, d11, d19\n-\tvstr\td19, [sp, #32]\n-\tvstr\td28, [sp, #16]\n-\tvmul.f64\td18, d11, d0\n-\tvfma.f64\td18, d28, d24\n-\tvstr\td18, [sp, #8]\n+\tvdiv.f64\td15, d13, d6\n+\tvldr\td6, [pc, #528]\t@ 1a70 <__gridxc_gga_MOD_bhx+0x3fc>\n+\tvmov.f64\td7, d15\n+\tvadd.f64\td15, d11, d13\n+\tvdiv.f64\td5, d13, d15\n+\tvmul.f64\td11, d11, d7\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tvmul.f64\td15, d15, d15\n+\tvldr\td7, [sp, #24]\n+\tvmla.f64\td4, d7, d6\n+\tvmul.f64\td6, d11, d0\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvstr\td4, [sp, #64]\t@ 0x40\n+\tvmla.f64\td6, d5, d4\n+\tvstr\td5, [sp, #24]\n+\tvstr\td6, [sp, #48]\t@ 0x30\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td29, [pc, #472]\t@ 18e8 <__gridxc_gga_MOD_bhx+0x3ec>\n-\tvldr\td30, [pc, #476]\t@ 18f0 <__gridxc_gga_MOD_bhx+0x3f4>\n-\tvldr\td21, [sp, #72]\t@ 0x48\n-\tvldr\td31, [sp, #48]\t@ 0x30\n-\tvdiv.f64\td23, d16, d15\n-\tvldr\td17, [sp, #80]\t@ 0x50\n-\tvdiv.f64\td6, d16, d8\n-\tvmul.f64\td21, d9, d21\n-\tvmul.f64\td16, d12, d29\n-\tvmul.f64\td31, d31, d31\n-\tvmul.f64\td17, d17, d30\n-\tvldr\td29, [pc, #444]\t@ 18f8 <__gridxc_gga_MOD_bhx+0x3fc>\n-\tvldr\td25, [sp, #64]\t@ 0x40\n-\tvdiv.f64\td7, d21, d14\n-\tvldr\td21, [pc, #440]\t@ 1900 <__gridxc_gga_MOD_bhx+0x404>\n-\tvmul.f64\td13, d13, d29\n-\tvldr\td19, [sp, #32]\n-\tvdiv.f64\td29, d17, d25\n-\tvldr\td17, [pc, #432]\t@ 1908 <__gridxc_gga_MOD_bhx+0x40c>\n-\tvdiv.f64\td25, d16, d31\n-\tvfma.f64\td13, d10, d21\n-\tvldr\td21, [pc, #428]\t@ 1910 <__gridxc_gga_MOD_bhx+0x414>\n-\tvmul.f64\td16, d16, d9\n-\tvmul.f64\td17, d10, d17\n-\tvldr\td20, [sp, #56]\t@ 0x38\n-\tvldr\td30, [pc, #420]\t@ 1918 <__gridxc_gga_MOD_bhx+0x41c>\n-\tvmul.f64\td9, d9, d21\n-\tvldr\td28, [sp, #16]\n-\tvmul.f64\td16, d16, d19\n-\tvldr\td24, [sp, #24]\n-\tvfma.f64\td13, d12, d30\n-\tvldr\td5, [sp, #160]\t@ 0xa0\n-\tvfma.f64\td16, d28, d17\n-\tvldr\td3, [r4, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td9, d9, d20\n-\tvldr\td17, [r4, #-8]\n-\tvldr\td20, [r4, #-16]\n-\tvmul.f64\td8, d8, d5\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvldr\td2, [sp, #32]\n+\tvldr\td0, [pc, #464]\t@ 1a78 <__gridxc_gga_MOD_bhx+0x404>\n+\tvmul.f64\td6, d8, d5\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvmul.f64\td0, d2, d0\n+\tvldr\td3, [sp, #96]\t@ 0x60\n+\tvldr\td1, [sp, #16]\n+\tvmul.f64\td7, d7, d4\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvdiv.f64\td5, d6, d12\n+\tvldr\td6, [pc, #432]\t@ 1a80 <__gridxc_gga_MOD_bhx+0x40c>\n+\tvdiv.f64\td12, d13, d10\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tvdiv.f64\td10, d13, d3\n+\tvmul.f64\td6, d7, d6\n+\tvdiv.f64\td1, d0, d1\n+\tvldr\td0, [pc, #416]\t@ 1a88 <__gridxc_gga_MOD_bhx+0x414>\n+\tcmp\tr9, r3\n+\tvdiv.f64\td13, d6, d15\n+\tvmul.f64\td4, d4, d0\n+\tvldr\td0, [pc, #412]\t@ 1a90 <__gridxc_gga_MOD_bhx+0x41c>\n+\tvmul.f64\td6, d6, d8\n+\tvldr\td15, [sp, #56]\t@ 0x38\n+\tvmla.f64\td4, d9, d0\n+\tvldr\td0, [pc, #404]\t@ 1a98 <__gridxc_gga_MOD_bhx+0x424>\n+\tvmul.f64\td6, d6, d15\n+\tvmul.f64\td0, d9, d0\n+\tvmul.f64\td11, d5, d11\n+\tvldr\td5, [r6, #-8]\n+\tvadd.f64\td1, d1, d10\n+\tvldr\td10, [sp, #24]\n+\tvmla.f64\td6, d0, d10\n+\tvldr\td0, [pc, #380]\t@ 1aa0 <__gridxc_gga_MOD_bhx+0x42c>\n+\tvmul.f64\td8, d8, d0\n+\tvldr\td0, [pc, #380]\t@ 1aa8 <__gridxc_gga_MOD_bhx+0x434>\n+\tvmls.f64\td6, d13, d2\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvmla.f64\td4, d7, d0\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvmul.f64\td2, d8, d2\n+\tvmul.f64\td2, d2, d7\n+\tvldr\td7, [sp, #152]\t@ 0x98\n+\tvmul.f64\td7, d3, d7\n+\tvmla.f64\td6, d4, d11\n+\tvldr\td4, [sp, #8]\n+\tvmul.f64\td2, d2, d15\n+\tvldr\td3, [r4, #-16]\n+\tvmla.f64\td4, d7, d0\n+\tvmls.f64\td6, d2, d15\n+\tvldr\td2, [r4, #-24]\t@ 0xffffffe8\n \tvadd.f64\td3, d3, d3\n-\tvldr\td18, [sp, #8]\n-\tvadd.f64\td17, d17, d17\n-\tvldr\td4, [r6, #-8]\n+\tvadd.f64\td2, d2, d2\n+\tvmul.f64\td3, d3, d7\n+\tvstr\td4, [sp, #8]\n+\tvmul.f64\td2, d2, d7\n+\tvldr\td4, [r4, #-8]\n+\tvmul.f64\td3, d3, d12\n+\tvadd.f64\td4, d4, d4\n+\tvmul.f64\td2, d2, d12\n+\tvmul.f64\td4, d4, d7\n+\tvmul.f64\td7, d7, d9\n \tvmul.f64\td9, d9, d12\n-\tvadd.f64\td20, d20, d20\n-\tvmul.f64\td31, d8, d10\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tvmul.f64\td21, d3, d8\n-\tvldr\td22, [sp, #104]\t@ 0x68\n-\tvmul.f64\td17, d17, d8\n-\tvfma.f64\td22, d8, d18\n-\tvnmul.f64\td9, d19, d9\n-\tvmul.f64\td20, d20, d8\n-\tcmp\tr8, r3\n-\tvldr\td26, [sp, #88]\t@ 0x58\n-\tvldr\td27, [sp, #96]\t@ 0x60\n-\tvmul.f64\td10, d10, d23\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td20, d20, d23\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td21, d21, d10\n-\tvmul.f64\td11, d7, d11\n-\tvmul.f64\td20, d20, d10\n-\tvmul.f64\td17, d17, d10\n-\tvadd.f64\td29, d29, d6\n-\tvfms.f64\td16, d25, d24\n-\tvmul.f64\td31, d31, d29\n-\tvfma.f64\td16, d13, d11\n-\tvfma.f64\td16, d9, d19\n-\tvnmul.f64\td31, d16, d31\n-\tvmul.f64\td21, d21, d16\n-\tvfma.f64\td31, d4, d18\n-\tvmul.f64\td20, d20, d16\n-\tvmul.f64\td17, d17, d16\n-\tvstr\td21, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td20, [r5, #-16]\n-\tvstr\td17, [r5, #-8]\n-\tvstmia\tr9!, {d31}\n-\tbne.w\t15fe <__gridxc_gga_MOD_bhx+0x102>\n-\tvmul.f64\td22, d22, d26\n-\tvldr\td16, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tldrd\tlr, fp, [sp, #132]\t@ 0x84\n-\tvdiv.f64\td16, d22, d16\n-\tldr.w\tip, [sp, #140]\t@ 0x8c\n-\tldr.w\tsl, [sp, #152]\t@ 0x98\n-\tcmp.w\tlr, #0\n-\tvstr\td16, [r3]\n-\tble.w\t19a8 <__gridxc_gga_MOD_bhx+0x4ac>\n-\tldr\tr1, [sp, #156]\t@ 0x9c\n-\tcmp.w\tlr, #1\n-\tldrd\tr2, r3, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td7, d1, d7\n+\tvmul.f64\td4, d4, d12\n+\tvmul.f64\td2, d2, d9\n+\tvmul.f64\td3, d3, d9\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td4, d4, d9\n+\tvmul.f64\td2, d2, d6\n+\tvmul.f64\td3, d3, d6\n+\tvnmls.f64\td7, d0, d5\n+\tvmul.f64\td4, d4, d6\n+\tvstr\td2, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td3, [r5, #-16]\n+\tvstr\td4, [r5, #-8]\n+\tvstmia\tsl!, {d7}\n+\tbne.w\t1782 <__gridxc_gga_MOD_bhx+0x10e>\n+\tvldr\td7, [sp, #8]\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tldrd\tr7, lr, [sp, #124]\t@ 0x7c\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #136]\t@ 0x88\n+\tldr.w\tip, [sp, #132]\t@ 0x84\n+\tcmp\tr7, #0\n+\tvdiv.f64\td6, d7, d6\n+\tvstr\td6, [r3]\n+\tble.w\t1b44 <__gridxc_gga_MOD_bhx+0x4d0>\n+\tldr\tr1, [sp, #148]\t@ 0x94\n+\tcmp\tr7, #1\n+\tldrd\tr2, r3, [sp, #176]\t@ 0xb0\n \tstrd\tr2, r3, [r1]\n+\tldrd\tr2, r3, [sp, #240]\t@ 0xf0\n+\tstrd\tr2, r3, [lr]\n \tldrd\tr2, r3, [sp, #248]\t@ 0xf8\n-\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [lr, #8]\n \tldrd\tr2, r3, [sp, #256]\t@ 0x100\n-\tstrd\tr2, r3, [ip, #8]\n-\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n-\tstrd\tr2, r3, [ip, #16]\n-\tmov.w\tr2, #0\n-\tmov.w\tr3, #0\n-\tbeq.n\t1990 <__gridxc_gga_MOD_bhx+0x494>\n-\tb.n\t192c <__gridxc_gga_MOD_bhx+0x430>\n-\tnop\n-\tnop.w\n+\tstrd\tr2, r3, [lr, #16]\n+\tbeq.w\t1b26 <__gridxc_gga_MOD_bhx+0x4b2>\n+\tb.n\t1abc <__gridxc_gga_MOD_bhx+0x448>\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n+\t...\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0x1a9fbe77\n \t.word\t0x3fc4dd2f\n \t.word\t0x0ed3d85a\n \t.word\t0x3f964d7f\n \t.word\t0xe147ae14\n@@ -1871,2562 +1983,2731 @@\n \t.word\t0x3ffd9db2\n \t.word\t0x11111111\n \t.word\t0x3fb11111\n \t.word\t0x66666666\n \t.word\t0x3ff26666\n \t.word\t0x1f72bbc7\n \t.word\t0x3fb826f5\n-\t.word\t0x4b1ee244\n-\t.word\t0x3fc0ba1f\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n+\t.word\t0x4b1ee244\n+\t.word\t0x3fc0ba1f\n \t.word\t0xe147ae14\n \t.word\t0x4051547a\n \t.word\t0x2d0e5604\n \t.word\t0x400d9db2\n \t.word\t0x1f72bbc7\n \t.word\t0x3fc826f5\n \t.word\t0x92bcb410\n \t.word\t0x3f6750ef\n \t.word\t0xa7ef9db2\n \t.word\t0x3fef4bc6\n-\t.word\t0x00000402\n+\t.word\t0x0000041a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000262\n+\t.word\t0x0000025e\n R_ARM_REL32\t.rodata\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tstrd\tr2, r3, [fp, #8]\n-\tstrd\tr2, r3, [fp]\n-\tstrd\tr2, r3, [r0]\n-\tstrd\tr2, r3, [sl]\n-\tstrd\tr2, r3, [sl, #8]\n-\tstrd\tr2, r3, [sl, #16]\n-\tstrd\tr2, r3, [sl, #24]\n-\tstrd\tr2, r3, [sl, #32]\n-\tstrd\tr2, r3, [sl, #40]\t@ 0x28\n-\tldrd\tr2, r3, [sp, #192]\t@ 0xc0\n+\tldrd\tr2, r3, [sp, #184]\t@ 0xb8\n \tstrd\tr2, r3, [r1, #8]\n+\tldr\tr1, [sp, #144]\t@ 0x90\n+\tldrd\tr2, r3, [sp, #264]\t@ 0x108\n+\tstrd\tr2, r3, [lr, #24]\n+\tldrd\tr2, r3, [sp, #272]\t@ 0x110\n+\tstrd\tr2, r3, [lr, #32]\n \tldrd\tr2, r3, [sp, #280]\t@ 0x118\n+\tstrd\tr2, r3, [lr, #40]\t@ 0x28\n+\tmovs\tr2, #0\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [r1]\n+\tstrd\tr2, r3, [r1, #8]\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [ip, #8]\n+\tstrd\tr2, r3, [r1]\n+\tstrd\tr2, r3, [ip, #16]\n+\tstrd\tr2, r3, [ip, #24]\n \tstrd\tr2, r3, [ip, #32]\n-\tldrd\tr0, r1, [sp, #272]\t@ 0x110\n-\tstrd\tr0, r1, [ip, #24]\n-\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n \tstrd\tr2, r3, [ip, #40]\t@ 0x28\n-\tldr\tr2, [pc, #156]\t@ (1a10 <__gridxc_gga_MOD_bhx+0x514>)\n-\tldr\tr3, [pc, #156]\t@ (1a14 <__gridxc_gga_MOD_bhx+0x518>)\n+\tldr\tr2, [pc, #172]\t@ (1bb8 <__gridxc_gga_MOD_bhx+0x544>)\n+\tldr\tr3, [pc, #176]\t@ (1bbc <__gridxc_gga_MOD_bhx+0x548>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #348]\t@ 0x15c\n+\tldr\tr3, [sp, #340]\t@ 0x154\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1a04 <__gridxc_gga_MOD_bhx+0x508>\n-\tadd\tsp, #356\t@ 0x164\n+\tbne.n\t1baa <__gridxc_gga_MOD_bhx+0x536>\n+\tadd\tsp, #348\t@ 0x15c\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tstrd\tr2, r3, [fp]\n-\tstrd\tr2, r3, [sl]\n+\tldr\tr1, [sp, #144]\t@ 0x90\n+\tmovs\tr2, #0\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [ip, #8]\n \tstrd\tr2, r3, [r1]\n-\tstrd\tr2, r3, [sl, #8]\n-\tstrd\tr2, r3, [sl, #16]\n-\tb.n\t1972 <__gridxc_gga_MOD_bhx+0x476>\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tstrd\tr2, r3, [ip, #16]\n+\tstrd\tr2, r3, [r1]\n+\tb.n\t1b08 <__gridxc_gga_MOD_bhx+0x494>\n+\tldr\tr1, [sp, #116]\t@ 0x74\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\t1972 <__gridxc_gga_MOD_bhx+0x476>\n-\tvldr\td19, [r5]\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td18, [r5, #8]\n-\tadd\tr4, sp, #296\t@ 0x128\n-\tvldr\td17, [r5, #16]\n-\tvmul.f64\td21, d16, d20\n-\tvldr\td22, [pc, #60]\t@ 1a08 <__gridxc_gga_MOD_bhx+0x50c>\n-\tvmul.f64\td19, d19, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmaxnm.f64\td16, d16, d22\n-\tvstr\td21, [sp, #168]\t@ 0xa8\n-\tvstr\td21, [sp, #176]\t@ 0xb0\n-\tvstr\td19, [sp, #296]\t@ 0x128\n-\tvstr\td19, [sp, #320]\t@ 0x140\n-\tvstr\td16, [sp, #144]\t@ 0x90\n-\tvstr\td18, [sp, #304]\t@ 0x130\n-\tvstr\td18, [sp, #328]\t@ 0x148\n-\tvstr\td17, [sp, #312]\t@ 0x138\n-\tvstr\td17, [sp, #336]\t@ 0x150\n-\tb.n\t1590 <__gridxc_gga_MOD_bhx+0x94>\n+\tb.n\t1b08 <__gridxc_gga_MOD_bhx+0x494>\n+\tvldr\td2, [pc, #92]\t@ 1bb0 <__gridxc_gga_MOD_bhx+0x53c>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r5]\n+\tadd\tr4, sp, #288\t@ 0x120\n+\tvldr\td5, [r5, #8]\n+\tvmul.f64\td1, d7, d3\n+\tvcmpe.f64\td7, d2\n+\tvldr\td6, [r5, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvstr\td1, [sp, #160]\t@ 0xa0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td1, [sp, #168]\t@ 0xa8\n+\tvstr\td4, [sp, #288]\t@ 0x120\n+\tvstr\td4, [sp, #312]\t@ 0x138\n+\tvstr\td5, [sp, #296]\t@ 0x128\n+\tvstr\td5, [sp, #320]\t@ 0x140\n+\tit\tlt\n+\tvmovlt.f64\td7, d2\n+\tvstr\td6, [sp, #304]\t@ 0x130\n+\tvstr\td6, [sp, #328]\t@ 0x148\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tb.n\t1712 <__gridxc_gga_MOD_bhx+0x9e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x00000096\n+\t.word\t0x000000a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00001a18 <__gridxc_gga_MOD_pw86rx>:\n+00001bc0 <__gridxc_gga_MOD_pw86rx>:\n __gridxc_gga_MOD_pw86rx.localalias():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n \tsub\tsp, #24\n \tmovs\tr5, #0\n \tldr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r3\n \tstr\tr2, [sp, #4]\n \tmov\tr3, r0\n \tstr\tr4, [sp, #8]\n \tstr\tr1, [sp, #0]\n-\tldr\tr0, [pc, #76]\t@ (1a88 <__gridxc_gga_MOD_pw86rx+0x70>)\n+\tldr\tr0, [pc, #76]\t@ (1c30 <__gridxc_gga_MOD_pw86rx+0x70>)\n \tldr\tr4, [sp, #48]\t@ 0x30\n \tldr\tr6, [r1, #0]\n \tadd\tr0, pc\n \tstr\tr4, [sp, #16]\n \tadd.w\tr2, r0, #8\n \tldr\tr4, [sp, #56]\t@ 0x38\n \tadd.w\tr1, r0, #16\n \tstr\tr4, [sp, #20]\n \tadds\tr0, #24\n \tbl\t0 <__gridxc_gga_MOD_pw86formx>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tmovs\tr4, #0\n \tcmp\tr6, #0\n \tstrd\tr4, r5, [r3]\n-\tble.n\t1a84 <__gridxc_gga_MOD_pw86rx+0x6c>\n+\tble.n\t1c2c <__gridxc_gga_MOD_pw86rx+0x6c>\n \tlsls\tr2, r6, #3\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tmovs\tr2, #0\n \tadds\tr2, #1\n \tstrd\tr4, r5, [r3]\n \tstrd\tr4, r5, [r3, #8]\n \tcmp\tr2, r6\n \tstrd\tr4, r5, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t1a6e <__gridxc_gga_MOD_pw86rx+0x56>\n+\tbne.n\t1c16 <__gridxc_gga_MOD_pw86rx+0x56>\n \tadd\tsp, #24\n \tpop\t{r4, r5, r6, pc}\n \t.word\t0x00000046\n R_ARM_REL32\t.rodata\n \n-00001a8c <__gridxc_gga_MOD_pw86x>:\n+00001c34 <__gridxc_gga_MOD_pw86x>:\n __gridxc_gga_MOD_pw86x.localalias():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n \tsub\tsp, #24\n \tmovs\tr5, #0\n \tldr\tr4, [sp, #40]\t@ 0x28\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r3\n \tstr\tr2, [sp, #4]\n \tmov\tr3, r0\n \tstr\tr4, [sp, #8]\n \tstr\tr1, [sp, #0]\n-\tldr\tr0, [pc, #76]\t@ (1afc <__gridxc_gga_MOD_pw86x+0x70>)\n+\tldr\tr0, [pc, #76]\t@ (1ca4 <__gridxc_gga_MOD_pw86x+0x70>)\n \tldr\tr4, [sp, #48]\t@ 0x30\n \tldr\tr6, [r1, #0]\n \tadd\tr0, pc\n \tstr\tr4, [sp, #16]\n \tadd.w\tr2, r0, #32\n \tldr\tr4, [sp, #56]\t@ 0x38\n \tadd.w\tr1, r0, #40\t@ 0x28\n \tstr\tr4, [sp, #20]\n \tadds\tr0, #48\t@ 0x30\n \tbl\t0 <__gridxc_gga_MOD_pw86formx>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tmovs\tr4, #0\n \tcmp\tr6, #0\n \tstrd\tr4, r5, [r3]\n-\tble.n\t1af8 <__gridxc_gga_MOD_pw86x+0x6c>\n+\tble.n\t1ca0 <__gridxc_gga_MOD_pw86x+0x6c>\n \tlsls\tr2, r6, #3\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tmovs\tr2, #0\n \tadds\tr2, #1\n \tstrd\tr4, r5, [r3]\n \tstrd\tr4, r5, [r3, #8]\n \tcmp\tr2, r6\n \tstrd\tr4, r5, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t1ae2 <__gridxc_gga_MOD_pw86x+0x56>\n+\tbne.n\t1c8a <__gridxc_gga_MOD_pw86x+0x56>\n \tadd\tsp, #24\n \tpop\t{r4, r5, r6, pc}\n \t.word\t0x00000046\n R_ARM_REL32\t.rodata\n \n-00001b00 <__gridxc_gga_MOD_am05xc>:\n+00001ca8 <__gridxc_gga_MOD_am05xc>:\n __gridxc_gga_MOD_am05xc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3696]\t@ 0xe70\n-\tldr\tr0, [pc, #648]\t@ (1da0 <__gridxc_gga_MOD_am05xc+0x2a0>)\n+\tldr\tr0, [pc, #688]\t@ (1f70 <__gridxc_gga_MOD_am05xc+0x2c8>)\n \tmov\tr4, r1\n-\tldr\tr1, [pc, #648]\t@ (1da4 <__gridxc_gga_MOD_am05xc+0x2a4>)\n+\tldr\tr1, [pc, #688]\t@ (1f74 <__gridxc_gga_MOD_am05xc+0x2cc>)\n \tsub\tsp, #308\t@ 0x134\n \tadd\tr0, pc\n \tmov\tip, r3\n \tldr\tr3, [r4, #0]\n \tldrd\tr9, sl, [sp, #400]\t@ 0x190\n \tcmp\tr3, #1\n \tldr\tr1, [r0, r1]\n \tldrd\tr8, r7, [sp, #408]\t@ 0x198\n \tldr\tr1, [r1, #0]\n \tstr\tr1, [sp, #300]\t@ 0x12c\n \tmov.w\tr1, #0\n \tldrd\tr6, r5, [sp, #416]\t@ 0x1a0\n-\tvldr\td19, [r2]\n-\tbeq.w\t1d32 <__gridxc_gga_MOD_am05xc+0x232>\n+\tvldr\td6, [r2]\n+\tbeq.w\t1ef8 <__gridxc_gga_MOD_am05xc+0x250>\n+\tvldr\td7, [r2, #8]\n \tadd.w\tfp, sp, #248\t@ 0xf8\n+\tvldr\td5, [pc, #628]\t@ 1f68 <__gridxc_gga_MOD_am05xc+0x2c0>\n+\tadd.w\tlr, sp, #272\t@ 0x110\n \tldr.w\tr0, [ip]\n+\tvadd.f64\td9, d7, d6\n \tldr.w\tr1, [ip, #4]\n-\tadd.w\tlr, sp, #272\t@ 0x110\n-\tldr.w\tr3, [ip, #12]\n-\tvldr\td16, [r2, #8]\n \tldr.w\tr2, [ip, #8]\n+\tldr.w\tr3, [ip, #12]\n \tstmia.w\tfp!, {r0, r1, r2, r3}\n+\tvcmpe.f64\td9, d5\n \tldr.w\tr0, [ip, #16]\n \tldr.w\tr1, [ip, #20]\n-\tvadd.f64\td14, d16, d19\n \tstmia.w\tfp!, {r0, r1}\n-\tvldr\td17, [pc, #548]\t@ 1d98 <__gridxc_gga_MOD_am05xc+0x298>\n+\tvmrs\tAPSR_nzcv, fpscr\n \tldr.w\tr0, [ip, #24]\n \tldr.w\tr1, [ip, #28]\n \tldr.w\tr2, [ip, #32]\n-\tvmaxnm.f64\td14, d14, d17\n \tldr.w\tr3, [ip, #36]\t@ 0x24\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td9, d5\n \tldr.w\tr0, [ip, #40]\t@ 0x28\n \tldr.w\tr1, [ip, #44]\t@ 0x2c\n \tstmia.w\tlr!, {r0, r1}\n-\tvldr\td9, [sp, #256]\t@ 0x100\n+\tvldr\td13, [sp, #256]\t@ 0x100\n \tadd\tr3, sp, #88\t@ 0x58\n-\tvldr\td12, [sp, #280]\t@ 0x118\n+\tvldr\td14, [sp, #248]\t@ 0xf8\n \tadd.w\tfp, sp, #48\t@ 0x30\n-\tvldr\td10, [sp, #248]\t@ 0xf8\n-\tadd\tr2, sp, #136\t@ 0x88\n-\tvldr\td13, [sp, #272]\t@ 0x110\n-\tvmul.f64\td18, d9, d9\n-\tvmul.f64\td17, d12, d12\n \tvldr\td8, [sp, #264]\t@ 0x108\n-\tvfma.f64\td18, d10, d10\n-\tvldr\td11, [sp, #288]\t@ 0x120\n-\tvfma.f64\td17, d13, d13\n-\tvldr\td20, [pc, #460]\t@ 1d98 <__gridxc_gga_MOD_am05xc+0x298>\n-\tstr\tr3, [sp, #32]\n+\tadd\tr2, sp, #136\t@ 0x88\n+\tvmul.f64\td5, d13, d13\n+\tvldr\td11, [sp, #280]\t@ 0x118\n+\tvmla.f64\td5, d14, d14\n+\tvldr\td12, [sp, #272]\t@ 0x110\n+\tvldr\td10, [sp, #288]\t@ 0x120\n \tadd\tr1, sp, #64\t@ 0x40\n-\tadd\tr3, sp, #96\t@ 0x60\n+\tstr\tr3, [sp, #32]\n \tadd\tr0, sp, #56\t@ 0x38\n-\tvfma.f64\td18, d8, d8\n-\tvmaxnm.f64\td19, d19, d20\n-\tvfma.f64\td17, d11, d11\n-\tvmaxnm.f64\td16, d16, d20\n+\tadd\tr3, sp, #96\t@ 0x60\n+\tstr.w\tfp, [sp]\n+\tvmla.f64\td5, d8, d8\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr3, sp, #120\t@ 0x78\n-\tstr.w\tfp, [sp]\n-\tvstr\td19, [sp, #56]\t@ 0x38\n-\tvstr\td16, [sp, #64]\t@ 0x40\n \tstr\tr3, [sp, #24]\n \tadd\tr3, sp, #128\t@ 0x80\n \tstr\tr3, [sp, #28]\n \tadd\tr3, sp, #72\t@ 0x48\n-\tvsqrt.f64\td19, d18\n \tstr\tr3, [sp, #16]\n-\tvsqrt.f64\td16, d17\n \tadd\tr3, sp, #80\t@ 0x50\n \tstr\tr3, [sp, #20]\n \tadd\tr3, sp, #104\t@ 0x68\n \tstr\tr3, [sp, #8]\n \tadd\tr3, sp, #112\t@ 0x70\n \tstr\tr3, [sp, #12]\n \tadd\tr3, sp, #40\t@ 0x28\n \tstr\tr3, [sp, #4]\n+\tvsqrt.f64\td4, d5\n+\tvmul.f64\td5, d11, d11\n+\tvmla.f64\td5, d12, d12\n \tadd\tr3, sp, #144\t@ 0x90\n-\tvstr\td19, [sp, #136]\t@ 0x88\n-\tvstr\td16, [sp, #144]\t@ 0x90\n+\tvmla.f64\td5, d10, d10\n+\tvstr\td4, [sp, #136]\t@ 0x88\n+\tvsqrt.f64\td4, d5\n+\tvldr\td5, [pc, #424]\t@ 1f68 <__gridxc_gga_MOD_am05xc+0x2c0>\n+\tvcmpe.f64\td6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td7, d5\n+\tit\tlt\n+\tvmovlt.f64\td6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvstr\td4, [sp, #144]\t@ 0x90\n \tbl\t0 <__gridxc_am05_MOD_am05wbs>\n R_ARM_THM_CALL\t__gridxc_am05_MOD_am05wbs\n \tldr\tr3, [r4, #0]\n \tcmp\tr3, #0\n-\tble.w\t1d78 <__gridxc_gga_MOD_am05xc+0x278>\n-\tvldr\td17, [sp, #120]\t@ 0x78\n+\tble.w\t1f48 <__gridxc_gga_MOD_am05xc+0x2a0>\n+\tvldr\td5, [sp, #120]\t@ 0x78\n \tcmp\tr3, #1\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvmul.f64\td21, d10, d17\n-\tvmul.f64\td20, d9, d17\n-\tvmul.f64\td10, d10, d16\n-\tvmul.f64\td17, d8, d17\n-\tvmul.f64\td9, d9, d16\n-\tvmul.f64\td8, d8, d16\n-\tbeq.n\t1cf4 <__gridxc_gga_MOD_am05xc+0x1f4>\n-\tvldr\td19, [fp]\n-\tvstr\td20, [r6, #8]\n-\tvldr\td16, [sp, #128]\t@ 0x80\n-\tvdiv.f64\td20, d19, d14\n-\tvldr\td18, [sp, #96]\t@ 0x60\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvmul.f64\td2, d14, d5\n+\tvmul.f64\td3, d13, d5\n+\tvmul.f64\td14, d14, d4\n+\tvmul.f64\td5, d8, d5\n+\tvmul.f64\td13, d13, d4\n+\tvmul.f64\td8, d8, d4\n+\tbeq.n\t1eba <__gridxc_gga_MOD_am05xc+0x212>\n+\tvldr\td7, [fp]\n+\tvstr\td5, [r6, #16]\n \tldrd\tr2, r3, [fp, #-8]\n \tstrd\tr2, r3, [sl]\n+\tvdiv.f64\td6, d7, d9\n+\tvldr\td7, [sp, #128]\t@ 0x80\n \tldrd\tr2, r3, [sp, #104]\t@ 0x68\n \tstrd\tr2, r3, [r8]\n+\tvmul.f64\td5, d12, d7\n+\tvstr\td2, [r6]\n \tldrd\tr2, r3, [sp, #72]\t@ 0x48\n-\tvmul.f64\td19, d12, d16\n \tstrd\tr2, r3, [r7]\n-\tvmul.f64\td12, d12, d18\n \tldrd\tr2, r3, [sp, #112]\t@ 0x70\n-\tvstr\td21, [r6]\n-\tvmul.f64\td21, d13, d16\n-\tvmul.f64\td16, d11, d16\n-\tvmul.f64\td13, d13, d18\n-\tvmul.f64\td11, d11, d18\n+\tvstr\td5, [r6, #24]\n+\tvmul.f64\td5, d11, d7\n+\tvmul.f64\td7, d10, d7\n \tstrd\tr2, r3, [r8, #8]\n \tldrd\tr2, r3, [sp, #80]\t@ 0x50\n \tstrd\tr2, r3, [r7, #8]\n-\tvstr\td10, [r5]\n-\tvstr\td9, [r5, #8]\n-\tvstr\td17, [r6, #16]\n+\tvstr\td14, [r5]\n+\tvstr\td3, [r6, #8]\n+\tvstr\td13, [r5, #8]\n \tvstr\td8, [r5, #16]\n-\tvstr\td21, [r6, #24]\n-\tvstr\td19, [r6, #32]\n-\tvstr\td16, [r6, #40]\t@ 0x28\n-\tvstr\td13, [r5, #24]\n-\tvstr\td12, [r5, #32]\n-\tvstr\td11, [r5, #40]\t@ 0x28\n-\tvstr\td20, [r9]\n-\tldr\tr2, [pc, #208]\t@ (1da8 <__gridxc_gga_MOD_am05xc+0x2a8>)\n-\tldr\tr3, [pc, #200]\t@ (1da4 <__gridxc_gga_MOD_am05xc+0x2a4>)\n+\tvstr\td5, [r6, #32]\n+\tvstr\td7, [r6, #40]\t@ 0x28\n+\tvstr\td6, [r9]\n+\tvldr\td6, [sp, #96]\t@ 0x60\n+\tvmul.f64\td12, d12, d6\n+\tvmul.f64\td11, d11, d6\n+\tvmul.f64\td10, d10, d6\n+\tvstr\td12, [r5, #24]\n+\tvstr\td11, [r5, #32]\n+\tvstr\td10, [r5, #40]\t@ 0x28\n+\tldr\tr2, [pc, #216]\t@ (1f78 <__gridxc_gga_MOD_am05xc+0x2d0>)\n+\tldr\tr3, [pc, #212]\t@ (1f74 <__gridxc_gga_MOD_am05xc+0x2cc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #300]\t@ 0x12c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1d8e <__gridxc_gga_MOD_am05xc+0x28e>\n+\tbne.n\t1f5e <__gridxc_gga_MOD_am05xc+0x2b6>\n \tadd\tsp, #308\t@ 0x134\n \tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td18, [fp]\n+\tvldr\td4, [fp]\n \tldrd\tr2, r3, [fp, #-8]\n \tstrd\tr2, r3, [sl]\n-\tvdiv.f64\td16, d18, d14\n-\tvstr\td21, [r6]\n+\tvdiv.f64\td7, d4, d9\n+\tvstr\td2, [r6]\n \tldrd\tr2, r3, [sp, #104]\t@ 0x68\n \tstrd\tr2, r3, [r8]\n \tldrd\tr2, r3, [sp, #72]\t@ 0x48\n \tstrd\tr2, r3, [r7]\n-\tvstr\td10, [r5]\n-\tvstr\td20, [r6, #8]\n-\tvstr\td17, [r6, #16]\n-\tvstr\td9, [r5, #8]\n+\tvstr\td14, [r5]\n+\tvstr\td3, [r6, #8]\n+\tvstr\td5, [r6, #16]\n+\tvstr\td13, [r5, #8]\n \tvstr\td8, [r5, #16]\n-\tvstr\td16, [r9]\n-\tb.n\t1cd6 <__gridxc_gga_MOD_am05xc+0x1d6>\n-\tvldr\td20, [ip]\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvldr\td18, [ip, #8]\n-\tvldr\td17, [ip, #16]\n-\tvmul.f64\td20, d20, d16\n-\tvldr\td14, [pc, #80]\t@ 1d98 <__gridxc_gga_MOD_am05xc+0x298>\n-\tvmul.f64\td18, d18, d16\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td16, d19, d16\n-\tvmaxnm.f64\td14, d19, d14\n-\tvstr\td20, [sp, #248]\t@ 0xf8\n-\tvstr\td20, [sp, #272]\t@ 0x110\n-\tvmov.f64\td19, d16\n-\tvstr\td18, [sp, #256]\t@ 0x100\n-\tvstr\td18, [sp, #280]\t@ 0x118\n-\tvstr\td17, [sp, #264]\t@ 0x108\n-\tvstr\td17, [sp, #288]\t@ 0x120\n-\tb.n\t1b9a <__gridxc_gga_MOD_am05xc+0x9a>\n-\tvldr\td17, [fp]\n+\tvstr\td7, [r9]\n+\tb.n\t1e9c <__gridxc_gga_MOD_am05xc+0x1f4>\n+\tvldr\td9, [pc, #108]\t@ 1f68 <__gridxc_gga_MOD_am05xc+0x2c0>\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [ip]\n+\tvldr\td4, [ip, #8]\n+\tvcmpe.f64\td6, d9\n+\tvldr\td5, [ip, #16]\n+\tvmul.f64\td3, d3, d7\n+\tvmul.f64\td4, d4, d7\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td7, d6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td3, [sp, #248]\t@ 0xf8\n+\tvstr\td3, [sp, #272]\t@ 0x110\n+\tvstr\td4, [sp, #256]\t@ 0x100\n+\tvstr\td4, [sp, #280]\t@ 0x118\n+\tit\tge\n+\tvmovge.f64\td9, d6\n+\tvstr\td5, [sp, #264]\t@ 0x108\n+\tvmov.f64\td6, d7\n+\tvstr\td5, [sp, #288]\t@ 0x120\n+\tb.n\t1d4c <__gridxc_gga_MOD_am05xc+0xa4>\n+\tvldr\td6, [fp]\n \tldrd\tr2, r3, [fp, #-8]\n \tstrd\tr2, r3, [sl]\n-\tvdiv.f64\td16, d17, d14\n-\tvstr\td16, [r9]\n-\tb.n\t1cd6 <__gridxc_gga_MOD_am05xc+0x1d6>\n+\tvdiv.f64\td7, d6, d9\n+\tvstr\td7, [r9]\n+\tb.n\t1e9c <__gridxc_gga_MOD_am05xc+0x1f4>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x00000280\n+\t.word\t0x000002a8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000ca\n+\t.word\t0x000000d4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00001dac <__gridxc_gga_MOD_wcxc>:\n+00001f7c <__gridxc_gga_MOD_wcxc>:\n __gridxc_gga_MOD_wcxc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3424]\t@ 0xd60\n-\tsub.w\tsp, sp, #572\t@ 0x23c\n-\tldr.w\tr4, [pc, #1232]\t@ 2298 <__gridxc_gga_MOD_wcxc+0x4ec>\n+\tstr.w\tr0, [ip, #3432]\t@ 0xd68\n+\tsub.w\tsp, sp, #564\t@ 0x234\n+\tldr.w\tr4, [pc, #1200]\t@ 2448 <__gridxc_gga_MOD_wcxc+0x4cc>\n \tmov\tr5, r1\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadd\tr4, pc\n-\tstr\tr1, [sp, #100]\t@ 0x64\n-\tldr.w\tr1, [pc, #1224]\t@ 229c <__gridxc_gga_MOD_wcxc+0x4f0>\n+\tstr\tr1, [sp, #132]\t@ 0x84\n+\tldr.w\tr1, [pc, #1192]\t@ 244c <__gridxc_gga_MOD_wcxc+0x4d0>\n \tldr\tr1, [r4, r1]\n-\tldr\tr4, [sp, #672]\t@ 0x2a0\n+\tldr\tr4, [sp, #664]\t@ 0x298\n \tldr\tr1, [r1, #0]\n-\tstr\tr1, [sp, #564]\t@ 0x234\n+\tstr\tr1, [sp, #556]\t@ 0x22c\n \tmov.w\tr1, #0\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tldr\tr0, [sp, #676]\t@ 0x2a4\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n-\tldrd\tr7, r0, [sp, #680]\t@ 0x2a8\n-\tstr\tr0, [sp, #300]\t@ 0x12c\n+\tstr\tr0, [sp, #60]\t@ 0x3c\n+\tldr\tr0, [sp, #668]\t@ 0x29c\n+\tstr\tr0, [sp, #140]\t@ 0x8c\n+\tldrd\tr7, r0, [sp, #672]\t@ 0x2a0\n+\tstr\tr0, [sp, #292]\t@ 0x124\n \tldr\tr1, [r5, #0]\n-\tldr\tr0, [sp, #688]\t@ 0x2b0\n-\tstr\tr0, [sp, #304]\t@ 0x130\n+\tldr\tr0, [sp, #680]\t@ 0x2a8\n+\tstr\tr0, [sp, #296]\t@ 0x128\n \tcmp\tr1, #1\n-\tldr\tr0, [sp, #692]\t@ 0x2b4\n-\tstr\tr4, [sp, #104]\t@ 0x68\n-\tstr\tr0, [sp, #308]\t@ 0x134\n-\tbeq.w\t255a <__gridxc_gga_MOD_wcxc+0x7ae>\n-\tvldr\td23, [r2, #8]\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #24]\n-\tvldr\td17, [r3, #16]\n-\tvadd.f64\td9, d23, d16\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvadd.f64\td25, d21, d22\n-\tvstr\td16, [sp, #344]\t@ 0x158\n-\tvldr\td20, [r3, #8]\n-\tvadd.f64\td16, d17, d18\n-\tvldr\td19, [r3, #32]\n-\tvldr\td26, [pc, #984]\t@ 2208 <__gridxc_gga_MOD_wcxc+0x45c>\n-\tvstr\td23, [sp, #352]\t@ 0x160\n-\tvmov.f64\td23, d22\n-\tvadd.f64\td24, d19, d20\n-\tvstr\td21, [sp, #536]\t@ 0x218\n-\tvstr\td16, [sp, #72]\t@ 0x48\n-\tvmaxnm.f64\td9, d9, d26\n-\tvstr\td17, [sp, #528]\t@ 0x210\n-\tvmov.f64\td16, d19\n-\tvmov.f64\td17, d20\n-\tvmov.f64\td21, d25\n-\tvstr\td22, [sp, #512]\t@ 0x200\n-\tvstr\td25, [sp, #440]\t@ 0x1b8\n-\tvstr\td20, [sp, #520]\t@ 0x208\n-\tvstr\td19, [sp, #544]\t@ 0x220\n-\tvstr\td24, [sp, #448]\t@ 0x1c0\n-\tvldr\td19, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td22, [sp, #536]\t@ 0x218\n-\tvmul.f64\td17, d17, d17\n-\tvfma.f64\td17, d23, d23\n-\tvldr\td20, [sp, #528]\t@ 0x210\n-\tvstr\td19, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td19, d19, d19\n-\tvfma.f64\td19, d21, d21\n-\tvfma.f64\td16, d22, d22\n-\tvstr\td21, [sp, #160]\t@ 0xa0\n-\tadd.w\tfp, sp, #344\t@ 0x158\n-\tvldr\td21, [sp, #72]\t@ 0x48\n-\tvfma.f64\td17, d20, d20\n-\tvstr\td18, [sp, #552]\t@ 0x228\n-\tadd\tr3, sp, #408\t@ 0x198\n-\tvfma.f64\td16, d18, d18\n-\tvldr\td13, [pc, #856]\t@ 2208 <__gridxc_gga_MOD_wcxc+0x45c>\n-\tldr\tr0, [pc, #1004]\t@ (22a0 <__gridxc_gga_MOD_wcxc+0x4f4>)\n-\tadd\tr2, sp, #328\t@ 0x148\n+\tldr\tr0, [sp, #684]\t@ 0x2ac\n+\tstr\tr4, [sp, #136]\t@ 0x88\n+\tstr\tr0, [sp, #300]\t@ 0x12c\n+\tbeq.w\t27d2 <__gridxc_gga_MOD_wcxc+0x856>\n+\tvldr\td1, [r2, #8]\n+\tvldr\td6, [pc, #984]\t@ 23b0 <__gridxc_gga_MOD_wcxc+0x434>\n+\tvldr\td5, [r3]\n+\tvadd.f64\td8, d1, d7\n+\tvldr\td2, [r3, #24]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #32]\n+\tvadd.f64\td0, d2, d5\n+\tvstr\td7, [sp, #336]\t@ 0x150\n+\tvcmpe.f64\td8, d6\n+\tvldr\td7, [r3, #16]\n+\tvstr\td5, [sp, #504]\t@ 0x1f8\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvstr\td1, [sp, #344]\t@ 0x158\n+\tvadd.f64\td1, d4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td4, [sp, #536]\t@ 0x218\n+\tvstr\td7, [sp, #520]\t@ 0x208\n+\tvadd.f64\td4, d7, d5\n+\tvstr\td0, [sp, #432]\t@ 0x1b0\n+\tvstr\td1, [sp, #440]\t@ 0x1b8\n+\tvstr\td2, [sp, #528]\t@ 0x210\n+\tite\tlt\n+\tvmovlt.f64\td7, d6\n+\tvmovge.f64\td7, d8\n+\tvmov.f64\td1, d4\n+\tvstr\td3, [sp, #512]\t@ 0x200\n+\tvstr\td4, [sp, #88]\t@ 0x58\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvmov.f64\td7, d3\n+\tvldr\td3, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td4, [sp, #504]\t@ 0x1f8\n+\tadd.w\tfp, sp, #336\t@ 0x150\n+\tvldr\td2, [sp, #432]\t@ 0x1b0\n+\tadd\tr3, sp, #400\t@ 0x190\n+\tvldr\td6, [sp, #536]\t@ 0x218\n+\tadd\tr2, sp, #320\t@ 0x140\n+\tvmla.f64\td7, d4, d4\n+\tvstr\td3, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td4, d3, d3\n+\tvldr\td3, [sp, #528]\t@ 0x210\n+\tvmla.f64\td4, d2, d2\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td5, [sp, #544]\t@ 0x220\n \tmov\tr1, fp\n-\tvstr\td21, [sp, #456]\t@ 0x1c8\n+\tvmla.f64\td6, d3, d3\n+\tvstr\td2, [sp, #176]\t@ 0xb0\n+\tvldr\td2, [pc, #804]\t@ 23b0 <__gridxc_gga_MOD_wcxc+0x434>\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td4, d1, d1\n+\tldr\tr0, [pc, #952]\t@ (2450 <__gridxc_gga_MOD_wcxc+0x4d4>)\n+\tvstr\td1, [sp, #448]\t@ 0x1c0\n+\tadd.w\tr9, sp, #384\t@ 0x180\n+\tvmla.f64\td6, d5, d5\n \tadd\tr0, pc\n-\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td18, d19\n \tadds\tr0, #4\n-\tvfma.f64\td18, d21, d21\n-\tadd.w\tr9, sp, #392\t@ 0x188\n-\tvsqrt.f64\td19, d17\n-\tadd.w\tsl, sp, #376\t@ 0x178\n-\tadd\tr6, sp, #424\t@ 0x1a8\n-\tadd\tr5, sp, #512\t@ 0x200\n-\tvsqrt.f64\td17, d16\n-\tadd\tr4, sp, #464\t@ 0x1d0\n-\tadd.w\tr8, sp, #360\t@ 0x168\n-\tvsqrt.f64\td16, d18\n-\tvstr\td19, [sp, #392]\t@ 0x188\n-\tvstr\td17, [sp, #400]\t@ 0x190\n-\tvmaxnm.f64\td10, d16, d13\n-\tvstr\td10, [sp, #176]\t@ 0xb0\n+\tvstr\td2, [sp, #16]\n+\tadd.w\tsl, sp, #368\t@ 0x170\n+\tadd\tr6, sp, #416\t@ 0x1a0\n+\tadd\tr5, sp, #504\t@ 0x1f8\n+\tadd\tr4, sp, #456\t@ 0x1c8\n+\tadd.w\tr8, sp, #352\t@ 0x160\n+\tvsqrt.f64\td5, d4\n+\tvsqrt.f64\td4, d6\n+\tvldr\td6, [sp, #520]\t@ 0x208\n+\tvmla.f64\td7, d6, d6\n+\tvsqrt.f64\td6, d7\n+\tvcmpe.f64\td5, d2\n+\tvstr\td4, [sp, #392]\t@ 0x188\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td11, d2\n+\tvmovge.f64\td11, d5\n+\tvstr\td6, [sp, #384]\t@ 0x180\n+\tvstr\td11, [sp, #192]\t@ 0xc0\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td16, [pc, #784]\t@ 2210 <__gridxc_gga_MOD_wcxc+0x464>\n-\tvmul.f64\td0, d9, d16\n+\tvldr\td9, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #708]\t@ 23b8 <__gridxc_gga_MOD_wcxc+0x43c>\n+\tvmul.f64\td0, d9, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td18, [pc, #780]\t@ 2218 <__gridxc_gga_MOD_wcxc+0x46c>\n-\tvdiv.f64\td17, d15, d9\n-\tvldr\td22, [sp, #352]\t@ 0x160\n-\tvldr\td16, [sp, #344]\t@ 0x158\n-\tvmul.f64\td18, d0, d18\n-\tvldr\td20, [pc, #768]\t@ 2220 <__gridxc_gga_MOD_wcxc+0x474>\n-\tvldr\td19, [pc, #772]\t@ 2228 <__gridxc_gga_MOD_wcxc+0x47c>\n-\tvsub.f64\td16, d16, d22\n-\tvstr\td0, [sp, #184]\t@ 0xb8\n-\tvsqrt.f64\td11, d18\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #88]\t@ 0x58\n-\tvmaxnm.f64\td16, d16, d20\n-\tvstr\td11, [sp, #192]\t@ 0xc0\n-\tvminnm.f64\td16, d16, d19\n-\tvadd.f64\td17, d16, d15\n-\tvsub.f64\td8, d15, d16\n-\tvmov.f64\td0, d17\n-\tvstr\td17, [sp, #320]\t@ 0x140\n-\tvstr\td8, [sp, #200]\t@ 0xc8\n+\tvldr\td6, [sp, #344]\t@ 0x158\n+\tvldr\td7, [sp, #336]\t@ 0x150\n+\tvstr\td0, [sp, #200]\t@ 0xc8\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d8, d9\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvldr\td6, [pc, #676]\t@ 23c0 <__gridxc_gga_MOD_wcxc+0x444>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvldr\td6, [pc, #664]\t@ 23c8 <__gridxc_gga_MOD_wcxc+0x44c>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvldr\td6, [pc, #656]\t@ 23d0 <__gridxc_gga_MOD_wcxc+0x454>\n+\tvmul.f64\td6, d0, d6\n+\tvsub.f64\td10, d8, d7\n+\tvsqrt.f64\td12, d6\n+\tvadd.f64\td6, d7, d8\n+\tvstr\td10, [sp, #216]\t@ 0xd8\n+\tvmov.f64\td0, d6\n+\tvstr\td6, [sp, #312]\t@ 0x138\n+\tvstr\td12, [sp, #208]\t@ 0xd0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, d0\n-\tvmov.f64\td0, d8\n-\tvmov.f64\td12, d16\n-\tvstr\td16, [sp, #216]\t@ 0xd8\n+\tvmov.f64\td13, d0\n+\tvstr\td0, [sp, #224]\t@ 0xe0\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td22, d0, d0\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvldr\td8, [sp, #328]\t@ 0x148\n-\tvmul.f64\td19, d9, d11\n-\tvldr\td18, [pc, #684]\t@ 2230 <__gridxc_gga_MOD_wcxc+0x484>\n-\tvfma.f64\td22, d12, d12\n-\tvmul.f64\td20, d10, d16\n-\tvstr\td0, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td18, d8, d18\n-\tvstr\td8, [sp, #120]\t@ 0x78\n-\tvmul.f64\td16, d22, d16\n-\tvstr\td22, [sp, #112]\t@ 0x70\n-\tvmul.f64\td12, d16, d16\n-\tvmul.f64\td19, d19, d16\n-\tvdiv.f64\td10, d20, d19\n-\tvmul.f64\td12, d12, d16\n-\tvdiv.f64\td16, d18, d12\n-\tvstr\td10, [sp, #208]\t@ 0xd0\n-\tvneg.f64\td0, d16\n-\tvstr\td16, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td5, d9, d12\n+\tvldr\td10, [sp, #320]\t@ 0x140\n+\tvmul.f64\td7, d13, d13\n+\tvldr\td6, [pc, #596]\t@ 23d8 <__gridxc_gga_MOD_wcxc+0x45c>\n+\tvmla.f64\td7, d0, d0\n+\tvstr\td0, [sp, #256]\t@ 0x100\n+\tvstr\td10, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d10, d6\n+\tvmov.f64\td3, d7\n+\tvstr\td7, [sp, #144]\t@ 0x90\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td4, d11, d7\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td9, d7, d7\n+\tvmul.f64\td5, d5, d7\n+\tvdiv.f64\td11, d4, d5\n+\tvmul.f64\td9, d9, d7\n+\tvdiv.f64\td7, d6, d9\n+\tvstr\td11, [sp, #96]\t@ 0x60\n+\tvneg.f64\td0, d7\n+\tvstr\td7, [sp, #232]\t@ 0xe8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td20, d0, d15\n-\tvldr\td16, [pc, #620]\t@ 2238 <__gridxc_gga_MOD_wcxc+0x48c>\n-\tvmul.f64\td17, d10, d10\n-\tvldr\td18, [pc, #620]\t@ 2240 <__gridxc_gga_MOD_wcxc+0x494>\n-\tvstr\td0, [sp, #232]\t@ 0xe8\n-\tvstr\td20, [sp, #128]\t@ 0x80\n-\tvmul.f64\td10, d12, d18\n-\tvmul.f64\td19, d17, d17\n-\tvdiv.f64\td12, d16, d20\n-\tvstr\td17, [sp, #272]\t@ 0x110\n-\tvmov.f64\td18, d15\n-\tvstr\td19, [sp, #152]\t@ 0x98\n-\tvstr\td10, [sp, #136]\t@ 0x88\n-\tvfma.f64\td17, d19, d12\n-\tvfma.f64\td18, d12, d17\n-\tvmul.f64\td16, d17, d16\n-\tvstr\td17, [sp, #248]\t@ 0xf8\n-\tvdiv.f64\td17, d15, d18\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #288]\t@ 0x120\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tvadd.f64\td16, d16, d15\n-\tvmov.f64\td0, d16\n-\tvstr\td16, [sp, #144]\t@ 0x90\n+\tvsub.f64\td4, d0, d8\n+\tvldr\td7, [pc, #524]\t@ 23e0 <__gridxc_gga_MOD_wcxc+0x464>\n+\tvmul.f64\td5, d11, d11\n+\tvldr\td6, [pc, #524]\t@ 23e8 <__gridxc_gga_MOD_wcxc+0x46c>\n+\tvstr\td0, [sp, #240]\t@ 0xf0\n+\tvstr\td4, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td4, d7, d4\n+\tvmul.f64\td9, d9, d6\n+\tvstr\td5, [sp, #264]\t@ 0x108\n+\tvmov.f64\td6, d5\n+\tvmul.f64\td5, d5, d5\n+\tvstr\td9, [sp, #160]\t@ 0xa0\n+\tvstr\td5, [sp, #112]\t@ 0x70\n+\tvmla.f64\td6, d5, d4\n+\tvstr\td4, [sp, #248]\t@ 0xf8\n+\tvmov.f64\td5, d6\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td6, [sp, #72]\t@ 0x48\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d4, d5\n+\tvdiv.f64\td6, d8, d6\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #280]\t@ 0x118\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvadd.f64\td7, d7, d8\n+\tvmov.f64\td0, d7\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td16, d10, d0\n-\tvmov.i64\td31, #0x0000000000000000\n-\tstr\tr7, [sp, #296]\t@ 0x128\n+\tvmul.f64\td7, d9, d0\n+\tstr\tr7, [sp, #288]\t@ 0x120\n \tmov\tr7, r9\n-\tadd\tr3, sp, #336\t@ 0x150\n-\tstr.w\tr8, [sp, #64]\t@ 0x40\n-\tvstr\td16, [sp, #264]\t@ 0x108\n-\tvadd.f64\td16, d8, d16\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tvstr\td16, [sp, #80]\t@ 0x50\n-\tvldr\td16, [sp, #408]\t@ 0x198\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvldr\td16, [sp, #416]\t@ 0x1a0\n-\tvstr\td16, [sp, #312]\t@ 0x138\n-\tvldmia\tr7!, {d16}\n-\tmov\tr9, sl\n+\tvldr\td2, [sp, #16]\n+\tadd\tr3, sp, #328\t@ 0x148\n+\tstr.w\tr8, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvadd.f64\td7, d10, d7\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td7, [sp, #400]\t@ 0x190\n+\tvstr\td7, [sp, #272]\t@ 0x110\n+\tvldr\td7, [sp, #408]\t@ 0x198\n+\tvstr\td7, [sp, #304]\t@ 0x130\n+\tvldr\td7, [pc, #384]\t@ 23f0 <__gridxc_gga_MOD_wcxc+0x474>\n+\tvstr\td7, [sp, #8]\n \tvldmia\tfp!, {d8}\n+\tmov\tr9, sl\n+\tvldmia\tr7!, {d11}\n \tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n-\tvstr\td31, [sp, #56]\t@ 0x38\n+\tvldr\td7, [pc, #304]\t@ 23b8 <__gridxc_gga_MOD_wcxc+0x43c>\n \tadds\tr5, #24\n-\tvadd.f64\td16, d16, d16\n-\tvldr\td11, [pc, #468]\t@ 2248 <__gridxc_gga_MOD_wcxc+0x49c>\n \tvadd.f64\td8, d8, d8\n+\tvstr\td2, [sp, #32]\n+\tvadd.f64\td11, d11, d11\n+\tvmov.f64\td14, d15\n \tadds\tr4, #24\n-\tvmaxnm.f64\td16, d16, d13\n-\tvmaxnm.f64\td8, d8, d13\n-\tvstr\td16, [sp, #16]\n-\tvstr\td16, [sp, #8]\n-\tvldr\td16, [pc, #384]\t@ 2210 <__gridxc_gga_MOD_wcxc+0x464>\n+\tvcmpe.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td11, d2\n+\tit\tlt\n+\tvmovlt.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d8, d7\n \tvstmia\tsl!, {d8}\n-\tvmul.f64\td0, d8, d16\n+\tit\tlt\n+\tvmovlt.f64\td11, d2\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #8]\n-\tvmov.f64\td25, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td19, d8, d0\n-\tvstr\td0, [sp, #48]\t@ 0x30\n-\tvmul.f64\td18, d16, d25\n-\tvstr\td25, [sp, #40]\t@ 0x28\n-\tvstr\td16, [sp, #32]\n-\tvstr\td19, [sp, #24]\n-\tvdiv.f64\td22, d18, d19\n-\tvmul.f64\td10, d22, d22\n-\tvstr\td22, [sp, #16]\n-\tvneg.f64\td0, d10\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td3, d8, d0\n+\tvstr\td0, [sp, #24]\n+\tvmul.f64\td7, d11, d7\n+\tvstr\td3, [sp, #16]\n+\tvdiv.f64\td13, d7, d3\n+\tvmul.f64\td9, d13, d13\n+\tvneg.f64\td0, d9\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmul.f64\td21, d10, d10\n-\tvldr\td18, [pc, #376]\t@ 2250 <__gridxc_gga_MOD_wcxc+0x4a4>\n-\tvmov.f64\td20, d15\n-\tvldr\td16, [pc, #376]\t@ 2258 <__gridxc_gga_MOD_wcxc+0x4ac>\n-\tvmov.f64\td14, d0\n-\tvfma.f64\td20, d21, d18\n-\tvfma.f64\td11, d0, d16\n-\tvmov.f64\td0, d20\n-\tvstr\td20, [sp, #8]\n+\tvmul.f64\td7, d9, d9\n+\tvldr\td6, [pc, #264]\t@ 23f8 <__gridxc_gga_MOD_wcxc+0x47c>\n+\tvmov.f64\td12, d0\n+\tvmla.f64\td14, d7, d6\n+\tvmov.f64\td0, d14\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td22, [sp, #16]\n-\tvldr\td18, [pc, #352]\t@ 2260 <__gridxc_gga_MOD_wcxc+0x4b4>\n-\tvfma.f64\td0, d10, d11\n-\tvldr\td20, [sp, #8]\n+\tvldr\td6, [pc, #252]\t@ 2400 <__gridxc_gga_MOD_wcxc+0x484>\n+\tvldr\td7, [pc, #256]\t@ 2408 <__gridxc_gga_MOD_wcxc+0x48c>\n \tmov\tr2, r9\n-\tldr\tr1, [pc, #408]\t@ (22a4 <__gridxc_gga_MOD_wcxc+0x4f8>)\n-\tvmul.f64\td18, d22, d18\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tvldr\td5, [pc, #260]\t@ 2410 <__gridxc_gga_MOD_wcxc+0x494>\n+\tvmla.f64\td7, d12, d6\n+\tvmov.f64\td6, d15\n+\tldr\tr1, [pc, #316]\t@ (2454 <__gridxc_gga_MOD_wcxc+0x4d8>)\n+\tldr\tr3, [sp, #128]\t@ 0x80\n \tstr\tr6, [sp, #0]\n \tadd\tr1, pc\n-\tldr\tr0, [sp, #68]\t@ 0x44\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n \tadds\tr6, #8\n-\tvstr\td22, [sp, #8]\n-\tvmul.f64\td18, d18, d10\n-\tvsub.f64\td10, d15, d10\n-\tvdiv.f64\td11, d18, d20\n-\tvldr\td18, [pc, #316]\t@ 2268 <__gridxc_gga_MOD_wcxc+0x4bc>\n-\tvmov.f64\td20, d15\n-\tvfma.f64\td20, d0, d18\n-\tvdiv.f64\td18, d15, d20\n-\tvldr\td20, [pc, #308]\t@ 2270 <__gridxc_gga_MOD_wcxc+0x4c4>\n-\tvmul.f64\td14, d14, d20\n-\tvldr\td20, [pc, #308]\t@ 2278 <__gridxc_gga_MOD_wcxc+0x4cc>\n-\tvfma.f64\td20, d10, d14\n-\tvldr\td14, [pc, #308]\t@ 2280 <__gridxc_gga_MOD_wcxc+0x4d4>\n-\tvfma.f64\td11, d20, d22\n-\tvldr\td20, [pc, #308]\t@ 2288 <__gridxc_gga_MOD_wcxc+0x4dc>\n-\tvmul.f64\td10, d18, d18\n-\tvfms.f64\td14, d18, d20\n+\tvmla.f64\td0, d7, d9\n+\tvldr\td7, [pc, #240]\t@ 2418 <__gridxc_gga_MOD_wcxc+0x49c>\n+\tvmul.f64\td7, d13, d7\n+\tvmul.f64\td7, d7, d9\n+\tvmla.f64\td6, d0, d5\n+\tvldr\td5, [pc, #232]\t@ 2420 <__gridxc_gga_MOD_wcxc+0x4a4>\n+\tvdiv.f64\td10, d7, d14\n+\tvsub.f64\td7, d15, d9\n+\tvmul.f64\td5, d12, d5\n+\tvldr\td14, [pc, #224]\t@ 2428 <__gridxc_gga_MOD_wcxc+0x4ac>\n+\tvldr\td12, [pc, #228]\t@ 2430 <__gridxc_gga_MOD_wcxc+0x4b4>\n+\tvdiv.f64\td9, d15, d6\n+\tvldr\td6, [pc, #228]\t@ 2438 <__gridxc_gga_MOD_wcxc+0x4bc>\n+\tvmla.f64\td6, d7, d5\n+\tvldr\td7, [pc, #228]\t@ 2440 <__gridxc_gga_MOD_wcxc+0x4c4>\n+\tvmla.f64\td10, d6, d13\n+\tvmls.f64\td14, d9, d7\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td27, [pc, #300]\t@ 2290 <__gridxc_gga_MOD_wcxc+0x4e4>\n-\tvldr\td17, [sp, #48]\t@ 0x30\n-\tvldr\td16, [sp, #32]\n-\tvldr\td19, [sp, #24]\n-\tvmul.f64\td17, d17, d27\n-\tvldr\td21, [r5, #-24]\t@ 0xffffffe8\n-\tvdiv.f64\td23, d15, d16\n-\tvldr\td22, [sp, #8]\n-\tvdiv.f64\td16, d15, d8\n-\tvldr\td31, [sp, #56]\t@ 0x38\n-\tvadd.f64\td21, d21, d21\n-\tvldr\td20, [r6, #-8]\n-\tvdiv.f64\td18, d17, d19\n-\tvldr\td19, [r5, #-16]\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvldr\td25, [sp, #40]\t@ 0x28\n-\tvadd.f64\td19, d19, d19\n+\tvldr\td1, [sp, #24]\n+\tvmul.f64\td9, d9, d9\n+\tvdiv.f64\td6, d15, d11\n+\tvldr\td3, [sp, #16]\n+\tvldr\td4, [r6, #-8]\n+\tvmul.f64\td7, d1, d12\n+\tvldr\td1, [r5, #-24]\t@ 0xffffffe8\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvldr\td2, [sp, #32]\n+\tvadd.f64\td1, d1, d1\n \tcmp\tr3, fp\n-\tvadd.f64\td18, d18, d16\n-\tvldr\td16, [sp, #336]\t@ 0x150\n-\tvmul.f64\td8, d8, d16\n-\tvldr\td16, [r5, #-8]\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td21, d21, d8\n-\tvmul.f64\td19, d19, d8\n-\tvfma.f64\td31, d8, d14\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td8, d8, d22\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td22, d23, d22\n-\tvmul.f64\td19, d19, d23\n-\tvmul.f64\td18, d18, d8\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td21, d21, d22\n-\tvmul.f64\td19, d19, d22\n-\tvmul.f64\td18, d18, d11\n-\tvmul.f64\td16, d16, d22\n-\tvnmul.f64\td17, d10, d18\n-\tvmul.f64\td16, d16, d11\n-\tvfma.f64\td17, d20, d14\n-\tvmul.f64\td18, d21, d11\n-\tb.n\t22a8 <__gridxc_gga_MOD_wcxc+0x4fc>\n+\tvdiv.f64\td5, d7, d3\n+\tvldr\td3, [r5, #-16]\n+\tvdiv.f64\td7, d15, d8\n+\tvadd.f64\td3, d3, d3\n+\tvadd.f64\td5, d5, d7\n+\tvldr\td7, [sp, #328]\t@ 0x148\n+\tb.n\t2458 <__gridxc_gga_MOD_wcxc+0x4dc>\n \tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x6dc9c883\n-\t.word\t0x3ff45f30\n \t.word\t0xffffdcd1\n \t.word\t0xbfefffff\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n+\t.word\t0x6dc9c883\n+\t.word\t0x3ff45f30\n \t.word\t0xeafdf295\n \t.word\t0x404014fc\n \t.word\t0xdd62e0ae\n \t.word\t0x40012b4b\n \t.word\t0xf1fb1946\n \t.word\t0x3f9fd63c\n-\t.word\t0x3c0ca458\n-\t.word\t0x3fbf9add\n+\t...\n \t.word\t0x209aaa3b\n \t.word\t0x3f803eea\n \t.word\t0xaee0db2a\n \t.word\t0x3fb8975d\n-\t.word\t0x209aaa3b\n-\t.word\t0x3fa03eea\n+\t.word\t0x3c0ca458\n+\t.word\t0x3fbf9add\n \t.word\t0x01460cbc\n \t.word\t0x3ff3e687\n+\t.word\t0x209aaa3b\n+\t.word\t0x3fa03eea\n \t.word\t0xaee0db2a\n \t.word\t0x3fc8975d\n-\t.word\t0x3c0ca458\n-\t.word\t0x3fcf9add\n \t.word\t0x1a9fbe77\n \t.word\t0x3ffcdd2f\n-\t.word\t0x353f7cee\n-\t.word\t0x3fe9ba5e\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x000004c6\n+\t.word\t0x3c0ca458\n+\t.word\t0x3fcf9add\n+\t.word\t0x353f7cee\n+\t.word\t0x3fe9ba5e\n+\t.word\t0x000004a6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003e0\n+\t.word\t0x000003aa\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000018c\n+\t.word\t0x00000134\n R_ARM_REL32\t.rodata\n-\tvmul.f64\td16, d16, d10\n-\tvmul.f64\td18, d18, d10\n-\tvstr\td16, [r4, #-8]\n-\tvstmia\tr8!, {d17}\n-\tvmul.f64\td17, d19, d11\n-\tvstr\td18, [r4, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td17, d17, d10\n-\tvstr\td17, [r4, #-16]\n-\tbne.w\t205a <__gridxc_gga_MOD_wcxc+0x2ae>\n-\tvldr\td6, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvmul.f64\td25, d6, d25\n-\tldr\tr7, [sp, #296]\t@ 0x128\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tvmul.f64\td25, d25, d31\n-\tvstr\td25, [r3]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #8]\n+\tvmla.f64\td7, d8, d14\n+\tvmul.f64\td1, d1, d8\n+\tvmul.f64\td3, d3, d8\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td3, d3, d6\n+\tvstr\td7, [sp, #8]\n+\tvldr\td7, [r5, #-8]\n+\tvadd.f64\td7, d7, d7\n+\tvmul.f64\td7, d7, d8\n+\tvmul.f64\td8, d8, d13\n+\tvmul.f64\td8, d5, d8\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td5, d6, d13\n+\tvmul.f64\td8, d8, d10\n+\tvmul.f64\td1, d1, d5\n+\tvmul.f64\td3, d3, d5\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td8, d8, d9\n+\tvmul.f64\td1, d1, d10\n+\tvmul.f64\td3, d3, d10\n+\tvmul.f64\td7, d7, d10\n+\tvnmls.f64\td8, d14, d4\n+\tvmul.f64\td1, d1, d9\n+\tvmul.f64\td3, d3, d9\n+\tvmul.f64\td7, d7, d9\n+\tvstr\td1, [r4, #-24]\t@ 0xffffffe8\n+\tvstr\td3, [r4, #-16]\n+\tvstr\td7, [r4, #-8]\n+\tvstmia\tr8!, {d8}\n+\tbne.w\t2276 <__gridxc_gga_MOD_wcxc+0x2fa>\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tvldr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvldr\td6, [sp, #8]\n+\tvstr\td7, [r3]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tvmul.f64\td7, d0, d7\n+\tldr\tr7, [sp, #288]\t@ 0x120\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tldr\tr3, [sp, #132]\t@ 0x84\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tble.w\t253a <__gridxc_gga_MOD_wcxc+0x78e>\n-\tvldr\td16, [sp, #184]\t@ 0xb8\n+\tble.w\t27b2 <__gridxc_gga_MOD_wcxc+0x836>\n+\tvldr\td7, [sp, #200]\t@ 0xc8\n \tcmp\tr1, #1\n-\tvldr\td17, [sp, #192]\t@ 0xc0\n-\tvldr\td18, [sp, #72]\t@ 0x48\n-\tvldr\td20, [sp, #136]\t@ 0x88\n-\tvmul.f64\td22, d16, d17\n-\tvldr\td16, [sp, #216]\t@ 0xd8\n-\tvldr\td17, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td18, d9, d18\n-\tvldr\td31, [sp, #208]\t@ 0xd0\n-\tvdiv.f64\td23, d15, d16\n-\tvldr\td16, [sp, #240]\t@ 0xf0\n-\tvldr\td28, [sp, #256]\t@ 0x100\n-\tvldr\td5, [sp, #120]\t@ 0x78\n-\tvdiv.f64\td16, d15, d16\n-\tvldr\td7, [sp, #272]\t@ 0x110\n-\tvmul.f64\td21, d20, d28\n-\tvldr\td4, [sp, #248]\t@ 0xf8\n-\tvldr\td1, [sp, #152]\t@ 0x98\n-\tvldr\td2, [sp, #288]\t@ 0x120\n-\tvldr\td3, [sp, #264]\t@ 0x108\n-\tldr\tr0, [sp, #308]\t@ 0x134\n-\tldr\tr5, [sp, #300]\t@ 0x12c\n-\tldrd\tr2, r3, [sp, #360]\t@ 0x168\n+\tvldr\td6, [sp, #208]\t@ 0xd0\n+\tvldr\td11, [sp, #248]\t@ 0xf8\n+\tvldr\td8, [sp, #40]\t@ 0x28\n+\tvmul.f64\td3, d7, d6\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvdiv.f64\td7, d15, d7\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvdiv.f64\td6, d15, d6\n+\tvldr\td14, [sp, #144]\t@ 0x90\n+\tvmul.f64\td4, d8, d4\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td1, d7, d12\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td7, d7, d11\n+\tvstr\td1, [sp, #32]\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td7, d7, d6\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvstr\td7, [sp, #16]\n+\tvmul.f64\td7, d6, d0\n+\tvldr\td6, [sp, #192]\t@ 0xc0\n+\tvdiv.f64\td2, d15, d6\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td7, d7, d1\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvdiv.f64\td13, d15, d6\n+\tvldr\td6, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td5, d8, d6\n+\tvldr\td6, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td6, d8, d6\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td2, d2, d1\n+\tvldr\td1, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td5, d5, d1\n+\tvmul.f64\td6, d6, d1\n+\tvmul.f64\td4, d4, d1\n+\tvmul.f64\td1, d1, d9\n+\tvldr\td9, [sp, #72]\t@ 0x48\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td4, d4, d2\n+\tvldr\td2, [pc, #628]\t@ 2840 <__gridxc_gga_MOD_wcxc+0x8c4>\n+\tvdiv.f64\td9, d15, d9\n+\tvmul.f64\td10, d1, d13\n+\tvmov.f64\td1, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td2, d3, d2\n+\tvmul.f64\td1, d11, d1\n+\tvstr\td10, [sp, #24]\n+\tvmul.f64\td2, d2, d0\n+\tvdiv.f64\td10, d2, d3\n+\tvmov.f64\td3, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td14, d3, d14\n+\tvadd.f64\td10, d10, d0\n+\tvldr\td0, [sp, #64]\t@ 0x40\n+\tvmul.f64\td2, d0, d8\n+\tvdiv.f64\td12, d15, d2\n+\tvmov.f64\td15, d11\n+\tvldr\td11, [sp, #264]\t@ 0x108\n+\tvmla.f64\td3, d1, d11\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tvmul.f64\td2, d3, d1\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td3, d2, d1\n+\tvldr\td2, [sp, #104]\t@ 0x68\n+\tvldr\td1, [sp, #272]\t@ 0x110\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d2\n+\tvsub.f64\td8, d1, d0\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td0, d14, d7\n+\tvstr\td12, [sp, #8]\n+\tvldr\td12, [sp, #80]\t@ 0x50\n+\tvadd.f64\td2, d12, d1\n+\tvmul.f64\td1, d14, d11\n+\tvmul.f64\td11, d12, d11\n+\tvldr\td12, [sp, #8]\n+\tvmul.f64\td7, d1, d7\n+\tvnmls.f64\td7, d8, d12\n+\tvadd.f64\td8, d10, d0\n+\tvldr\td12, [sp, #16]\n+\tvmul.f64\td8, d8, d3\n+\tvmul.f64\td7, d7, d12\n+\tvldr\td12, [sp, #112]\t@ 0x70\n+\tldr\tr5, [sp, #292]\t@ 0x124\n+\tldr\tr4, [sp, #296]\t@ 0x128\n+\tldr\tr0, [sp, #300]\t@ 0x12c\n+\tvnmls.f64\td8, d12, d7\n+\tvldr\td12, [sp, #72]\t@ 0x48\n+\tldrd\tr2, r3, [sp, #352]\t@ 0x160\n \tstrd\tr2, r3, [r7]\n-\tvsub.f64\td23, d23, d16\n-\tvldr\td16, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td23, d23, d27\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [sp, #128]\t@ 0x80\n-\tvdiv.f64\td29, d16, d17\n-\tvldr\td16, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td19, d16, d6\n-\tvldr\td16, [sp, #176]\t@ 0xb0\n-\tvdiv.f64\td24, d15, d16\n-\tvldr\td16, [sp, #144]\t@ 0x90\n-\tvmul.f64\td19, d19, d23\n-\tvdiv.f64\td26, d15, d16\n-\tvldr\td16, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td17, d9, d16\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td16, d9, d16\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td24, d24, d31\n-\tvmul.f64\td21, d21, d26\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvldr\td20, [sp, #112]\t@ 0x70\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td18, d18, d24\n-\tvldr\td24, [pc, #500]\t@ 25c0 <__gridxc_gga_MOD_wcxc+0x814>\n-\tvmul.f64\td24, d22, d24\n-\tvmul.f64\td24, d24, d6\n-\tvdiv.f64\td25, d24, d22\n-\tvmov.f64\td22, #0\t@ 0x40000000 2.0\n-\tvmul.f64\td24, d5, d9\n-\tvdiv.f64\td27, d22, d20\n-\tvmov.f64\td20, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td20, d12, d20\n-\tvdiv.f64\td30, d15, d24\n-\tvdiv.f64\td24, d15, d4\n-\tvfma.f64\td22, d20, d7\n-\tvmul.f64\td22, d22, d31\n-\tvmul.f64\td17, d17, d22\n-\tvmul.f64\td16, d16, d22\n-\tvmul.f64\td18, d18, d22\n-\tvmul.f64\td11, d22, d31\n-\tvmov.f64\td22, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td17, d17, d28\n-\tvmul.f64\td16, d16, d28\n-\tvmul.f64\td18, d18, d28\n-\tvldr\td28, [sp, #280]\t@ 0x118\n-\tvsub.f64\td20, d28, d5\n-\tvadd.f64\td28, d3, d28\n-\tvadd.f64\td25, d25, d6\n-\tvmul.f64\td31, d27, d22\n-\tvmul.f64\td22, d3, d22\n-\tvmul.f64\td20, d20, d30\n-\tvfms.f64\td20, d31, d19\n-\tvmul.f64\td19, d27, d19\n-\tvadd.f64\td7, d25, d19\n-\tvmul.f64\td19, d22, d19\n-\tvmul.f64\td20, d29, d20\n-\tvnmul.f64\td7, d11, d7\n-\tvfma.f64\td7, d1, d20\n-\tvmul.f64\td20, d4, d20\n-\tvfma.f64\td20, d12, d7\n-\tvmul.f64\td7, d24, d7\n-\tvfms.f64\td7, d20, d2\n-\tvfma.f64\td19, d21, d7\n-\tvfma.f64\td28, d9, d19\n-\tvmov.f64\td19, d24\n-\tvfms.f64\td19, d12, d2\n-\tvstr\td28, [r5]\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td19, d18, d19\n-\tvmul.f64\td17, d17, d26\n-\tvmul.f64\td16, d16, d26\n-\tvmul.f64\td19, d19, d26\n-\tvstr\td17, [r0]\n-\tvstr\td16, [r0, #8]\n-\tvstr\td19, [r0, #16]\n-\tldrd\tr2, r3, [sp, #464]\t@ 0x1d0\n-\tldr\tr4, [sp, #304]\t@ 0x130\n+\tvmul.f64\td7, d12, d7\n+\tvldr\td12, [sp, #280]\t@ 0x118\n+\tldrd\tr2, r3, [sp, #456]\t@ 0x1c8\n \tstrd\tr2, r3, [r4]\n-\tldrd\tr2, r3, [sp, #472]\t@ 0x1d8\n+\tldrd\tr2, r3, [sp, #464]\t@ 0x1d0\n \tstrd\tr2, r3, [r4, #8]\n-\tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n+\tvmla.f64\td7, d15, d8\n+\tldrd\tr2, r3, [sp, #472]\t@ 0x1d8\n \tstrd\tr2, r3, [r4, #16]\n-\tbeq.n\t253a <__gridxc_gga_MOD_wcxc+0x78e>\n-\tvldr\td18, [sp, #320]\t@ 0x140\n-\tvldr\td20, [sp, #312]\t@ 0x138\n-\tldrd\tr2, r3, [sp, #368]\t@ 0x170\n-\tvnmul.f64\td10, d6, d18\n-\tvsub.f64\td18, d20, d5\n-\tvadd.f64\td20, d20, d3\n+\tvmul.f64\td7, d7, d12\n+\tvnmls.f64\td7, d9, d8\n+\tvldr\td8, [sp, #24]\n+\tvmul.f64\td7, d7, d8\n+\tvldr\td8, [sp, #40]\t@ 0x28\n+\tvmla.f64\td7, d11, d0\n+\tvmla.f64\td2, d7, d8\n+\tvmov.f64\td7, d9\n+\tvstr\td2, [r5]\n+\tvmov.f64\td2, d15\n+\tvmov.f64\td15, d12\n+\tvmls.f64\td7, d2, d12\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td7, d4, d7\n+\tvmul.f64\td5, d5, d13\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td7, d7, d13\n+\tvstr\td5, [r0]\n+\tvstr\td6, [r0, #8]\n+\tvstr\td7, [r0, #16]\n+\tbeq.n\t27b2 <__gridxc_gga_MOD_wcxc+0x836>\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvldr\td4, [sp, #312]\t@ 0x138\n+\tvstr\td7, [r0, #40]\t@ 0x28\n+\tvldr\td7, [sp, #32]\n+\tvnmul.f64\td4, d0, d4\n+\tvldr\td13, [sp, #304]\t@ 0x130\n+\tvldr\td0, [sp, #64]\t@ 0x40\n+\tvstr\td5, [r0, #24]\n+\tvldr\td5, [sp, #8]\n+\tvmul.f64\td4, d4, d7\n+\tvsub.f64\td7, d13, d0\n+\tvldr\td12, [sp, #72]\t@ 0x48\n+\tvstr\td6, [r0, #32]\n+\tvldr\td6, [sp, #80]\t@ 0x50\n+\tvmul.f64\td1, d4, d1\n+\tvmla.f64\td10, d4, d14\n+\tvmul.f64\td11, d11, d4\n+\tvadd.f64\td6, d13, d6\n+\tldrd\tr2, r3, [sp, #360]\t@ 0x168\n+\tvnmls.f64\td1, d7, d5\n+\tvldr\td7, [sp, #16]\n \tstrd\tr2, r3, [r7, #8]\n-\tldrd\tr2, r3, [sp, #488]\t@ 0x1e8\n-\tvmul.f64\td10, d10, d23\n-\tvmul.f64\td18, d18, d30\n+\tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n+\tvmul.f64\td10, d10, d3\n \tstrd\tr2, r3, [r4, #24]\n-\tldrd\tr2, r3, [sp, #496]\t@ 0x1f0\n+\tldrd\tr2, r3, [sp, #488]\t@ 0x1e8\n \tstrd\tr2, r3, [r4, #32]\n-\tvfms.f64\td18, d10, d31\n-\tvfma.f64\td25, d10, d27\n-\tvmul.f64\td22, d22, d10\n-\tvstr\td17, [r0, #24]\n-\tldrd\tr2, r3, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td1, d1, d7\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tldrd\tr2, r3, [sp, #496]\t@ 0x1f0\n \tstrd\tr2, r3, [r4, #40]\t@ 0x28\n-\tvstr\td16, [r0, #32]\n-\tvmul.f64\td22, d22, d27\n-\tvstr\td19, [r0, #40]\t@ 0x28\n-\tvmul.f64\td18, d18, d29\n-\tvnmul.f64\td11, d11, d25\n-\tvfma.f64\td11, d1, d18\n-\tvmul.f64\td14, d4, d18\n-\tvfma.f64\td14, d12, d11\n-\tvmul.f64\td24, d24, d11\n-\tvfms.f64\td24, d14, d2\n-\tvfma.f64\td22, d24, d21\n-\tvfma.f64\td20, d9, d22\n-\tvstr\td20, [r5, #8]\n-\tldr\tr2, [pc, #148]\t@ (25d0 <__gridxc_gga_MOD_wcxc+0x824>)\n-\tldr\tr3, [pc, #148]\t@ (25d4 <__gridxc_gga_MOD_wcxc+0x828>)\n+\tvnmls.f64\td10, d7, d1\n+\tvmul.f64\td7, d2, d10\n+\tvmla.f64\td7, d12, d1\n+\tvmul.f64\td7, d7, d15\n+\tvnmls.f64\td7, d9, d10\n+\tvldr\td10, [sp, #24]\n+\tvmul.f64\td7, d7, d10\n+\tvmla.f64\td7, d11, d14\n+\tvmla.f64\td6, d7, d8\n+\tvstr\td6, [r5, #8]\n+\tldr\tr2, [pc, #156]\t@ (2850 <__gridxc_gga_MOD_wcxc+0x8d4>)\n+\tldr\tr3, [pc, #156]\t@ (2854 <__gridxc_gga_MOD_wcxc+0x8d8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #564]\t@ 0x234\n+\tldr\tr3, [sp, #556]\t@ 0x22c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t25bc <__gridxc_gga_MOD_wcxc+0x810>\n-\tadd.w\tsp, sp, #572\t@ 0x23c\n+\tbne.n\t2836 <__gridxc_gga_MOD_wcxc+0x8ba>\n+\tadd.w\tsp, sp, #564\t@ 0x234\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td17, [r3, #16]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #8]\n-\tvmul.f64\td20, d16, d18\n-\tvmov.f64\td23, d17\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvmul.f64\td19, d22, d18\n-\tvldr\td9, [pc, #76]\t@ 25c8 <__gridxc_gga_MOD_wcxc+0x81c>\n-\tvmul.f64\td17, d21, d18\n-\tvstr\td21, [sp, #448]\t@ 0x1c0\n-\tvstr\td22, [sp, #440]\t@ 0x1b8\n-\tvmov.f64\td21, d22\n-\tvmul.f64\td18, d23, d18\n-\tvmaxnm.f64\td9, d16, d9\n-\tvmov.f64\td23, d19\n-\tvstr\td20, [sp, #344]\t@ 0x158\n-\tvmov.f64\td16, d17\n-\tvstr\td20, [sp, #352]\t@ 0x160\n-\tvstr\td19, [sp, #512]\t@ 0x200\n-\tvstr\td19, [sp, #536]\t@ 0x218\n-\tvstr\td17, [sp, #520]\t@ 0x208\n-\tvstr\td17, [sp, #544]\t@ 0x220\n-\tvstr\td18, [sp, #528]\t@ 0x210\n-\tb.n\t1e6c <__gridxc_gga_MOD_wcxc+0xc0>\n+\tvldr\td3, [pc, #116]\t@ 2848 <__gridxc_gga_MOD_wcxc+0x8cc>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r3]\n+\tvldr\td6, [r3, #8]\n+\tvmul.f64\td2, d7, d5\n+\tvcmpe.f64\td7, d3\n+\tvldr\td1, [r3, #16]\n+\tvstr\td4, [sp, #432]\t@ 0x1b0\n+\tvmul.f64\td4, d4, d5\n+\tvstr\td6, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td5, d1, d5\n+\tvstr\td1, [sp, #88]\t@ 0x58\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td2, [sp, #336]\t@ 0x150\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvstr\td4, [sp, #504]\t@ 0x1f8\n+\tvstr\td4, [sp, #528]\t@ 0x210\n+\tvstr\td6, [sp, #512]\t@ 0x200\n+\tit\tlt\n+\tvmovlt.f64\td7, d3\n+\tvstr\td6, [sp, #536]\t@ 0x218\n+\tvstr\td5, [sp, #520]\t@ 0x208\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvmov.f64\td7, d6\n+\tb.n\t2046 <__gridxc_gga_MOD_wcxc+0xca>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n+\tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000008e\n+\t.word\t0x00000096\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-000025d8 <__gridxc_gga_MOD_rpbexc>:\n+00002858 <__gridxc_gga_MOD_rpbexc>:\n __gridxc_gga_MOD_rpbexc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3432]\t@ 0xd68\n \tsub.w\tsp, sp, #564\t@ 0x234\n-\tldr.w\tr4, [pc, #1156]\t@ 2a78 <__gridxc_gga_MOD_rpbexc+0x4a0>\n+\tldr.w\tr4, [pc, #1148]\t@ 2cf0 <__gridxc_gga_MOD_rpbexc+0x498>\n \tmov\tr5, r1\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadd\tr4, pc\n-\tstr\tr1, [sp, #100]\t@ 0x64\n-\tldr.w\tr1, [pc, #1148]\t@ 2a7c <__gridxc_gga_MOD_rpbexc+0x4a4>\n+\tstr\tr1, [sp, #124]\t@ 0x7c\n+\tldr.w\tr1, [pc, #1140]\t@ 2cf4 <__gridxc_gga_MOD_rpbexc+0x49c>\n \tldr\tr1, [r4, r1]\n \tldr\tr4, [sp, #664]\t@ 0x298\n \tldr\tr1, [r1, #0]\n \tstr\tr1, [sp, #556]\t@ 0x22c\n \tmov.w\tr1, #0\n-\tstr\tr0, [sp, #76]\t@ 0x4c\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tldr\tr0, [sp, #668]\t@ 0x29c\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n+\tstr\tr0, [sp, #132]\t@ 0x84\n \tldrd\tr7, r0, [sp, #672]\t@ 0x2a0\n \tstr\tr0, [sp, #292]\t@ 0x124\n \tldr\tr1, [r5, #0]\n \tldr\tr0, [sp, #680]\t@ 0x2a8\n \tstr\tr0, [sp, #296]\t@ 0x128\n \tcmp\tr1, #1\n \tldr\tr0, [sp, #684]\t@ 0x2ac\n-\tstr\tr4, [sp, #104]\t@ 0x68\n+\tstr\tr4, [sp, #128]\t@ 0x80\n \tstr\tr0, [sp, #300]\t@ 0x12c\n-\tbeq.w\t2cea <__gridxc_gga_MOD_rpbexc+0x712>\n-\tvldr\td23, [r2, #8]\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #24]\n-\tvldr\td17, [r3, #16]\n-\tvadd.f64\td10, d23, d16\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvadd.f64\td25, d21, d22\n-\tvstr\td16, [sp, #336]\t@ 0x150\n-\tvldr\td20, [r3, #8]\n-\tvadd.f64\td16, d17, d18\n-\tvldr\td19, [r3, #32]\n-\tvldr\td26, [pc, #956]\t@ 2a18 <__gridxc_gga_MOD_rpbexc+0x440>\n-\tvstr\td23, [sp, #344]\t@ 0x158\n-\tvmov.f64\td23, d22\n-\tvadd.f64\td24, d19, d20\n-\tvstr\td21, [sp, #528]\t@ 0x210\n-\tvstr\td16, [sp, #80]\t@ 0x50\n-\tvmaxnm.f64\td10, d10, d26\n-\tvstr\td17, [sp, #520]\t@ 0x208\n-\tvmov.f64\td16, d19\n-\tvmov.f64\td17, d20\n-\tvmov.f64\td21, d25\n-\tvstr\td22, [sp, #504]\t@ 0x1f8\n-\tvstr\td25, [sp, #432]\t@ 0x1b0\n-\tvstr\td20, [sp, #512]\t@ 0x200\n-\tvstr\td19, [sp, #536]\t@ 0x218\n-\tvstr\td24, [sp, #440]\t@ 0x1b8\n-\tvldr\td19, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td22, [sp, #528]\t@ 0x210\n-\tvmul.f64\td17, d17, d17\n-\tvfma.f64\td17, d23, d23\n-\tvldr\td20, [sp, #520]\t@ 0x208\n-\tvstr\td19, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td19, d19, d19\n-\tvfma.f64\td19, d21, d21\n-\tvfma.f64\td16, d22, d22\n-\tvstr\td21, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvldr\td21, [sp, #80]\t@ 0x50\n-\tvfma.f64\td17, d20, d20\n-\tvstr\td18, [sp, #544]\t@ 0x220\n+\tbeq.w\t3016 <__gridxc_gga_MOD_rpbexc+0x7be>\n+\tvldr\td1, [r2, #8]\n+\tvldr\td6, [pc, #980]\t@ 2c88 <__gridxc_gga_MOD_rpbexc+0x430>\n+\tvldr\td5, [r3]\n+\tvadd.f64\td15, d1, d7\n+\tvldr\td2, [r3, #24]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #32]\n+\tvadd.f64\td0, d2, d5\n+\tvstr\td7, [sp, #336]\t@ 0x150\n+\tvcmpe.f64\td15, d6\n+\tvldr\td7, [r3, #16]\n+\tvstr\td5, [sp, #504]\t@ 0x1f8\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvstr\td1, [sp, #344]\t@ 0x158\n+\tvadd.f64\td1, d4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td4, [sp, #536]\t@ 0x218\n+\tvadd.f64\td4, d7, d5\n+\tvstr\td7, [sp, #520]\t@ 0x208\n+\tvmov.f64\td7, d3\n+\tvstr\td0, [sp, #432]\t@ 0x1b0\n+\tvstr\td1, [sp, #440]\t@ 0x1b8\n+\tvstr\td2, [sp, #528]\t@ 0x210\n+\tit\tlt\n+\tvmovlt.f64\td15, d6\n+\tvmov.f64\td1, d4\n+\tvstr\td3, [sp, #512]\t@ 0x200\n+\tvstr\td4, [sp, #80]\t@ 0x50\n+\tvldr\td3, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td4, [sp, #504]\t@ 0x1f8\n \tadd.w\tfp, sp, #336\t@ 0x150\n-\tvfma.f64\td16, d18, d18\n-\tvldr\td14, [pc, #824]\t@ 2a18 <__gridxc_gga_MOD_rpbexc+0x440>\n-\tvdiv.f64\td9, d12, d10\n-\tldr\tr0, [pc, #920]\t@ (2a80 <__gridxc_gga_MOD_rpbexc+0x4a8>)\n+\tvldr\td2, [sp, #432]\t@ 0x1b0\n \tadd\tr3, sp, #400\t@ 0x190\n+\tvldr\td6, [sp, #536]\t@ 0x218\n \tadd\tr2, sp, #320\t@ 0x140\n-\tadd\tr0, pc\n+\tvmla.f64\td7, d4, d4\n+\tvstr\td3, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td4, d3, d3\n+\tvldr\td3, [sp, #528]\t@ 0x210\n+\tvmla.f64\td4, d2, d2\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td5, [sp, #544]\t@ 0x220\n \tmov\tr1, fp\n-\tvmov.f64\td18, d19\n+\tvmla.f64\td6, d3, d3\n+\tvldr\td11, [pc, #812]\t@ 2c88 <__gridxc_gga_MOD_rpbexc+0x430>\n+\tldr\tr0, [pc, #920]\t@ (2cf8 <__gridxc_gga_MOD_rpbexc+0x4a0>)\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td4, d1, d1\n+\tvstr\td2, [sp, #176]\t@ 0xb0\n+\tadd\tr0, pc\n+\tvstr\td1, [sp, #448]\t@ 0x1c0\n+\tvmla.f64\td6, d5, d5\n \tadds\tr0, #4\n-\tvfma.f64\td18, d21, d21\n-\tvstr\td21, [sp, #448]\t@ 0x1c0\n-\tvsqrt.f64\td19, d17\n \tadd.w\tr9, sp, #384\t@ 0x180\n \tadd.w\tsl, sp, #368\t@ 0x170\n \tadd\tr6, sp, #416\t@ 0x1a0\n-\tvsqrt.f64\td17, d16\n \tadd\tr5, sp, #504\t@ 0x1f8\n \tadd\tr4, sp, #456\t@ 0x1c8\n \tadd.w\tr8, sp, #352\t@ 0x160\n-\tvsqrt.f64\td16, d18\n-\tvstr\td19, [sp, #384]\t@ 0x180\n-\tvstr\td17, [sp, #392]\t@ 0x188\n-\tvmaxnm.f64\td11, d16, d14\n-\tvstr\td11, [sp, #176]\t@ 0xb0\n+\tvsqrt.f64\td5, d4\n+\tvsqrt.f64\td4, d6\n+\tvldr\td6, [sp, #520]\t@ 0x208\n+\tvmla.f64\td7, d6, d6\n+\tvsqrt.f64\td6, d7\n+\tvcmpe.f64\td5, d11\n+\tvstr\td4, [sp, #392]\t@ 0x188\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td9, d11\n+\tvmovge.f64\td9, d5\n+\tvstr\td6, [sp, #384]\t@ 0x180\n+\tvstr\td9, [sp, #192]\t@ 0xc0\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td16, [pc, #752]\t@ 2a20 <__gridxc_gga_MOD_rpbexc+0x448>\n-\tvmul.f64\td0, d10, d16\n+\tvldr\td7, [pc, #720]\t@ 2c90 <__gridxc_gga_MOD_rpbexc+0x438>\n+\tvmul.f64\td0, d15, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [pc, #748]\t@ 2a28 <__gridxc_gga_MOD_rpbexc+0x450>\n-\tvldr\td20, [sp, #344]\t@ 0x158\n-\tvldr\td16, [sp, #336]\t@ 0x150\n-\tvmul.f64\td17, d0, d17\n-\tvldr\td19, [pc, #740]\t@ 2a30 <__gridxc_gga_MOD_rpbexc+0x458>\n-\tvldr\td18, [pc, #744]\t@ 2a38 <__gridxc_gga_MOD_rpbexc+0x460>\n-\tvsub.f64\td16, d16, d20\n-\tvstr\td0, [sp, #184]\t@ 0xb8\n-\tvsqrt.f64\td13, d17\n-\tvmul.f64\td16, d16, d9\n-\tvmaxnm.f64\td16, d16, d19\n-\tvminnm.f64\td16, d16, d18\n-\tvadd.f64\td17, d16, d12\n-\tvsub.f64\td8, d12, d16\n-\tvmov.f64\td0, d17\n-\tvstr\td17, [sp, #312]\t@ 0x138\n-\tvstr\td8, [sp, #200]\t@ 0xc8\n-\tvstr\td13, [sp, #192]\t@ 0xc0\n+\tvldr\td6, [sp, #344]\t@ 0x158\n+\tvldr\td7, [sp, #336]\t@ 0x150\n+\tvstr\td0, [sp, #200]\t@ 0xc8\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d8, d15\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #32]\n+\tvldr\td6, [pc, #688]\t@ 2c98 <__gridxc_gga_MOD_rpbexc+0x440>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvldr\td6, [pc, #676]\t@ 2ca0 <__gridxc_gga_MOD_rpbexc+0x448>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvldr\td6, [pc, #668]\t@ 2ca8 <__gridxc_gga_MOD_rpbexc+0x450>\n+\tvmul.f64\td6, d0, d6\n+\tvsub.f64\td10, d8, d7\n+\tvsqrt.f64\td12, d6\n+\tvadd.f64\td6, d7, d8\n+\tvstr\td10, [sp, #216]\t@ 0xd8\n+\tvmov.f64\td0, d6\n+\tvstr\td6, [sp, #312]\t@ 0x138\n+\tvstr\td12, [sp, #208]\t@ 0xd0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, d0\n-\tvmov.f64\td0, d8\n-\tvmov.f64\td15, d16\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n+\tvmov.f64\td13, d0\n+\tvstr\td0, [sp, #224]\t@ 0xe0\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td20, d0, d0\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td18, d10, d13\n-\tvldr\td8, [sp, #320]\t@ 0x140\n-\tvfma.f64\td20, d15, d15\n-\tvmul.f64\td19, d11, d16\n-\tvldr\td17, [pc, #652]\t@ 2a40 <__gridxc_gga_MOD_rpbexc+0x468>\n-\tvstr\td0, [sp, #232]\t@ 0xe8\n-\tvstr\td8, [sp, #120]\t@ 0x78\n-\tvmul.f64\td17, d8, d17\n-\tvmul.f64\td16, d20, d16\n-\tvstr\td20, [sp, #112]\t@ 0x70\n-\tvmul.f64\td13, d16, d16\n-\tvmul.f64\td18, d18, d16\n-\tvdiv.f64\td11, d19, d18\n-\tvmul.f64\td13, d13, d16\n-\tvdiv.f64\td16, d17, d13\n-\tvneg.f64\td0, d16\n-\tvstr\td16, [sp, #216]\t@ 0xd8\n+\tvldr\td10, [sp, #320]\t@ 0x140\n+\tvmul.f64\td5, d15, d12\n+\tvldr\td6, [pc, #612]\t@ 2cb0 <__gridxc_gga_MOD_rpbexc+0x458>\n+\tvmul.f64\td7, d13, d13\n+\tvstr\td0, [sp, #256]\t@ 0x100\n+\tvmla.f64\td7, d0, d0\n+\tvstr\td10, [sp, #144]\t@ 0x90\n+\tvmul.f64\td6, d10, d6\n+\tvmov.f64\td3, d7\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td4, d9, d7\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td9, d7, d7\n+\tvmul.f64\td5, d5, d7\n+\tvdiv.f64\td12, d4, d5\n+\tvmul.f64\td9, d9, d7\n+\tvdiv.f64\td7, d6, d9\n+\tvstr\td12, [sp, #88]\t@ 0x58\n+\tvneg.f64\td0, d7\n+\tvstr\td7, [sp, #232]\t@ 0xe8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td20, d0, d12\n-\tvldr\td16, [pc, #600]\t@ 2a48 <__gridxc_gga_MOD_rpbexc+0x470>\n-\tvmul.f64\td18, d11, d11\n-\tvldr\td17, [pc, #600]\t@ 2a50 <__gridxc_gga_MOD_rpbexc+0x478>\n-\tvstr\td0, [sp, #224]\t@ 0xe0\n-\tvstr\td20, [sp, #128]\t@ 0x80\n-\tvmul.f64\td15, d13, d17\n-\tvmul.f64\td19, d18, d18\n-\tvdiv.f64\td13, d16, d20\n-\tvstr\td18, [sp, #272]\t@ 0x110\n-\tvmov.f64\td17, d12\n-\tvstr\td19, [sp, #152]\t@ 0x98\n-\tvstr\td15, [sp, #136]\t@ 0x88\n-\tvfma.f64\td18, d19, d13\n-\tvfma.f64\td17, d13, d18\n-\tvmul.f64\td16, d18, d16\n-\tvstr\td18, [sp, #240]\t@ 0xf0\n-\tvdiv.f64\td17, d12, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #264]\t@ 0x108\n-\tvstr\td16, [sp, #248]\t@ 0xf8\n-\tvadd.f64\td16, d16, d12\n-\tvldr\td12, [pc, #532]\t@ 2a58 <__gridxc_gga_MOD_rpbexc+0x480>\n-\tvmov.f64\td0, d16\n-\tvstr\td16, [sp, #144]\t@ 0x90\n+\tvsub.f64\td4, d0, d8\n+\tvldr\td7, [pc, #536]\t@ 2cb8 <__gridxc_gga_MOD_rpbexc+0x460>\n+\tvmul.f64\td5, d12, d12\n+\tvldr\td6, [pc, #536]\t@ 2cc0 <__gridxc_gga_MOD_rpbexc+0x468>\n+\tvstr\td0, [sp, #240]\t@ 0xf0\n+\tvstr\td4, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td4, d7, d4\n+\tvmul.f64\td9, d9, d6\n+\tvstr\td5, [sp, #272]\t@ 0x110\n+\tvmov.f64\td6, d5\n+\tvmul.f64\td5, d5, d5\n+\tvstr\td9, [sp, #160]\t@ 0xa0\n+\tvstr\td5, [sp, #104]\t@ 0x68\n+\tvmla.f64\td6, d5, d4\n+\tvstr\td4, [sp, #248]\t@ 0xf8\n+\tvmov.f64\td5, d6\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td6, [sp, #64]\t@ 0x40\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d4, d5\n+\tvdiv.f64\td6, d8, d6\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #96]\t@ 0x60\n+\tvstr\td7, [sp, #264]\t@ 0x108\n+\tvadd.f64\td7, d7, d8\n+\tvmov.f64\td0, d7\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td16, d15, d0\n-\tvmov.i64\td25, #0x0000000000000000\n+\tvmul.f64\td7, d9, d0\n \tstr\tr7, [sp, #288]\t@ 0x120\n \tmov\tr7, r9\n \tadd\tr3, sp, #328\t@ 0x148\n-\tstr.w\tr8, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tvadd.f64\td16, d8, d16\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tvstr\td16, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #400]\t@ 0x190\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvldr\td16, [sp, #408]\t@ 0x198\n-\tvstr\td16, [sp, #304]\t@ 0x130\n-\tvldmia\tr7!, {d16}\n+\tstr.w\tr8, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvadd.f64\td7, d10, d7\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td7, [sp, #400]\t@ 0x190\n+\tvstr\td7, [sp, #280]\t@ 0x118\n+\tvldr\td7, [sp, #408]\t@ 0x198\n+\tvstr\td7, [sp, #304]\t@ 0x130\n+\tvldr\td7, [pc, #400]\t@ 2cc8 <__gridxc_gga_MOD_rpbexc+0x470>\n+\tvstr\td7, [sp, #8]\n+\tvldmia\tfp!, {d12}\n \tmov\tr9, sl\n-\tvldmia\tfp!, {d8}\n+\tvldmia\tr7!, {d8}\n+\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #320]\t@ 2c90 <__gridxc_gga_MOD_rpbexc+0x438>\n \tadds\tr5, #24\n-\tvstr\td25, [sp, #64]\t@ 0x40\n+\tvadd.f64\td12, d12, d12\n \tadds\tr4, #24\n-\tvadd.f64\td16, d16, d16\n \tvadd.f64\td8, d8, d8\n-\tvmaxnm.f64\td16, d16, d14\n-\tvmaxnm.f64\td8, d8, d14\n-\tvstr\td16, [sp, #16]\n-\tvstr\td16, [sp, #8]\n-\tvldr\td16, [pc, #368]\t@ 2a20 <__gridxc_gga_MOD_rpbexc+0x448>\n-\tvstmia\tsl!, {d8}\n-\tvmul.f64\td0, d8, d16\n+\tvcmpe.f64\td12, d11\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td8, d11\n+\tit\tlt\n+\tvmovlt.f64\td12, d11\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d12, d7\n+\tvstmia\tsl!, {d12}\n+\tit\tlt\n+\tvmovlt.f64\td8, d11\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #8]\n-\tvmov.f64\td24, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td21, d8, d0\n-\tvstr\td0, [sp, #56]\t@ 0x38\n-\tvmul.f64\td18, d16, d24\n-\tvstr\td24, [sp, #48]\t@ 0x30\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvstr\td21, [sp, #32]\n-\tvdiv.f64\td15, d18, d21\n-\tvmul.f64\td0, d15, d15\n-\tvnmul.f64\td0, d12, d0\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d12, d0\n+\tvmov.f64\td14, d0\n+\tvmul.f64\td6, d8, d6\n+\tvstr\td7, [sp, #24]\n+\tvdiv.f64\td10, d6, d7\n+\tvldr\td7, [pc, #304]\t@ 2cd0 <__gridxc_gga_MOD_rpbexc+0x478>\n+\tvmul.f64\td0, d10, d10\n+\tvnmul.f64\td0, d7, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvldr\td18, [pc, #364]\t@ 2a60 <__gridxc_gga_MOD_rpbexc+0x488>\n+\tvsub.f64\td5, d9, d0\n+\tvldr\td6, [pc, #292]\t@ 2cd8 <__gridxc_gga_MOD_rpbexc+0x480>\n+\tvmov.f64\td13, d0\n+\tvmov.f64\td0, d9\n+\tldr\tr1, [pc, #316]\t@ (2cfc <__gridxc_gga_MOD_rpbexc+0x4a4>)\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tmov\tr2, r9\n-\tvsub.f64\td19, d20, d0\n-\tvmov.f64\td22, d20\n-\tldr\tr1, [pc, #388]\t@ (2a84 <__gridxc_gga_MOD_rpbexc+0x4ac>)\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tvmla.f64\td0, d5, d6\n \tstr\tr6, [sp, #0]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tadd\tr1, pc\n-\tvfma.f64\td22, d19, d18\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n-\tvstr\td0, [sp, #24]\n \tadds\tr6, #8\n-\tvstr\td20, [sp, #16]\n-\tvstr\td22, [sp, #8]\n+\tvstr\td0, [sp, #16]\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td27, [pc, #328]\t@ 2a68 <__gridxc_gga_MOD_rpbexc+0x490>\n-\tvldr\td17, [sp, #56]\t@ 0x38\n-\tvldr\td20, [sp, #16]\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvmul.f64\td17, d17, d27\n-\tvldr\td21, [sp, #32]\n-\tvldr\td0, [sp, #24]\n-\tvdiv.f64\td18, d20, d16\n-\tvldr\td26, [pc, #304]\t@ 2a70 <__gridxc_gga_MOD_rpbexc+0x498>\n-\tvdiv.f64\td16, d20, d8\n-\tvldr\td22, [sp, #8]\n-\tvldr\td25, [sp, #64]\t@ 0x40\n-\tvdiv.f64\td19, d17, d21\n-\tvldr\td17, [r5, #-24]\t@ 0xffffffe8\n-\tvldr\td21, [r5, #-8]\n-\tvmul.f64\td26, d0, d26\n-\tvnmul.f64\td0, d12, d15\n-\tvldr\td23, [r6, #-8]\n-\tvadd.f64\td17, d17, d17\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tvadd.f64\td21, d21, d21\n-\tvldr\td24, [sp, #48]\t@ 0x30\n+\tvldr\td1, [pc, #264]\t@ 2ce0 <__gridxc_gga_MOD_rpbexc+0x488>\n+\tvldr\td7, [sp, #24]\n+\tvldr\td6, [sp, #328]\t@ 0x148\n+\tvmul.f64\td14, d14, d1\n+\tvldr\td0, [sp, #16]\n+\tvdiv.f64\td4, d9, d8\n+\tvldr\td5, [r5, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [r5, #-8]\n+\tvldr\td8, [r6, #-8]\n+\tvdiv.f64\td3, d14, d7\n+\tvadd.f64\td5, d5, d5\n+\tvdiv.f64\td7, d9, d12\n+\tvmul.f64\td12, d12, d6\n+\tvldr\td6, [sp, #8]\n+\tvadd.f64\td2, d2, d2\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvmla.f64\td6, d12, d0\n+\tvmul.f64\td5, d5, d12\n+\tvmul.f64\td2, d2, d12\n \tcmp\tr3, fp\n-\tvadd.f64\td19, d19, d16\n-\tvldr\td16, [sp, #328]\t@ 0x148\n-\tvmul.f64\td8, d8, d16\n-\tvldr\td16, [r5, #-16]\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td17, d17, d8\n-\tvmul.f64\td21, d21, d8\n-\tvfma.f64\td25, d8, d22\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td8, d8, d26\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td21, d21, d18\n-\tvmul.f64\td8, d8, d15\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td18, d18, d15\n-\tvnmul.f64\td19, d19, d8\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td21, d21, d18\n-\tvnmul.f64\td19, d0, d19\n-\tvmul.f64\td0, d0, d26\n-\tvfma.f64\td19, d23, d22\n-\tvnmul.f64\td17, d0, d17\n-\tvnmul.f64\td16, d0, d16\n-\tvnmul.f64\td0, d0, d21\n-\tvstr\td17, [r4, #-24]\t@ 0xffffffe8\n-\tvstmia\tr8!, {d19}\n-\tvstr\td16, [r4, #-16]\n-\tvstr\td0, [r4, #-8]\n-\tbne.w\t2882 <__gridxc_gga_MOD_rpbexc+0x2aa>\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvmul.f64\td24, d9, d24\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tldr\tr7, [sp, #288]\t@ 0x120\n-\tvstr\td16, [r3]\n-\tvmul.f64\td24, d24, d25\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tvstr\td24, [r3]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr1, [r3, #0]\n-\tcmp\tr1, #0\n-\tble.w\t2cca <__gridxc_gga_MOD_rpbexc+0x6f2>\n-\tb.n\t2a88 <__gridxc_gga_MOD_rpbexc+0x4b0>\n-\tnop.w\n+\tvstr\td6, [sp, #8]\n+\tvldr\td6, [pc, #192]\t@ 2ce8 <__gridxc_gga_MOD_rpbexc+0x490>\n+\tvmul.f64\td13, d13, d6\n+\tvmul.f64\td6, d12, d13\n+\tvmul.f64\td6, d6, d10\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td2, d2, d4\n+\tvadd.f64\td3, d3, d7\n+\tvldr\td7, [pc, #140]\t@ 2cd0 <__gridxc_gga_MOD_rpbexc+0x478>\n+\tvnmul.f64\td7, d7, d10\n+\tvnmul.f64\td3, d3, d6\n+\tvldr\td6, [r5, #-16]\n+\tvadd.f64\td6, d6, d6\n+\tvmul.f64\td3, d3, d7\n+\tvmul.f64\td7, d7, d13\n+\tvmul.f64\td6, d6, d12\n+\tvnmls.f64\td3, d0, d8\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td4, d4, d10\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td4, d2, d4\n+\tvstmia\tr8!, {d3}\n+\tvnmul.f64\td5, d7, d5\n+\tvnmul.f64\td6, d7, d6\n+\tb.n\t2d00 <__gridxc_gga_MOD_rpbexc+0x4a8>\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x6dc9c883\n-\t.word\t0x3ff45f30\n \t.word\t0xffffdcd1\n \t.word\t0xbfefffff\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n+\t.word\t0x6dc9c883\n+\t.word\t0x3ff45f30\n \t.word\t0xeafdf295\n \t.word\t0x404014fc\n \t.word\t0xdd62e0ae\n \t.word\t0x40012b4b\n \t.word\t0xf1fb1946\n \t.word\t0x3f9fd63c\n+\t...\n \t.word\t0x8c8d59f4\n \t.word\t0x3fd17954\n \t.word\t0x353f7cee\n \t.word\t0x3fe9ba5e\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n \t.word\t0x353f7cee\n \t.word\t0x3ff9ba5e\n-\t.word\t0x0000047a\n+\t.word\t0x00000472\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000392\n+\t.word\t0x0000038a\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000017c\n+\t.word\t0x0000012e\n R_ARM_REL32\t.rodata\n-\tvldr\td16, [sp, #184]\t@ 0xb8\n+\tvnmul.f64\td7, d7, d4\n+\tvstr\td5, [r4, #-24]\t@ 0xffffffe8\n+\tvstr\td6, [r4, #-16]\n+\tvstr\td7, [r4, #-8]\n+\tbne.w\t2b3e <__gridxc_gga_MOD_rpbexc+0x2e6>\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td5, [sp, #32]\n+\tvldr\td6, [sp, #8]\n+\tvstr\td7, [r3]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvmul.f64\td7, d5, d7\n+\tldr\tr7, [sp, #288]\t@ 0x120\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr1, [r3, #0]\n+\tcmp\tr1, #0\n+\tble.w\t2ff6 <__gridxc_gga_MOD_rpbexc+0x79e>\n+\tvldr\td7, [sp, #200]\t@ 0xc8\n \tcmp\tr1, #1\n-\tvldr\td17, [sp, #192]\t@ 0xc0\n-\tvldr\td18, [sp, #80]\t@ 0x50\n-\tvldr\td25, [pc, #696]\t@ 2d50 <__gridxc_gga_MOD_rpbexc+0x778>\n-\tvmul.f64\td23, d16, d17\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvldr\td17, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td18, d10, d18\n-\tvldr\td21, [sp, #136]\t@ 0x88\n-\tvdiv.f64\td22, d20, d16\n-\tvldr\td16, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td25, d23, d25\n-\tvldr\td6, [sp, #120]\t@ 0x78\n-\tvldr\td5, [sp, #240]\t@ 0xf0\n-\tvdiv.f64\td16, d20, d16\n-\tvldr\td31, [sp, #272]\t@ 0x110\n-\tvldr\td28, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td25, d25, d9\n-\tvldr\td2, [sp, #152]\t@ 0x98\n-\tvldr\td3, [sp, #264]\t@ 0x108\n-\tvldr\td4, [sp, #256]\t@ 0x100\n-\tldr\tr0, [sp, #300]\t@ 0x12c\n+\tvldr\td6, [sp, #208]\t@ 0xd0\n+\tvldr\td0, [sp, #248]\t@ 0xf8\n+\tvldr\td10, [sp, #80]\t@ 0x50\n+\tvmul.f64\td4, d7, d6\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvmul.f64\td2, d15, d10\n+\tvldr\td14, [sp, #136]\t@ 0x88\n+\tvdiv.f64\td7, d9, d7\n+\tvldr\td11, [sp, #264]\t@ 0x108\n+\tvdiv.f64\td6, d9, d6\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td8, d7, d1\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tvmov.f64\td1, d5\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td8, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td7, d7, d6\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvstr\td7, [sp, #24]\n+\tvmul.f64\td7, d6, d5\n+\tvldr\td6, [sp, #192]\t@ 0xc0\n+\tvdiv.f64\td3, d9, d6\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td7, d7, d8\n+\tvldr\td8, [sp, #88]\t@ 0x58\n+\tvdiv.f64\td13, d9, d6\n+\tvldr\td6, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td5, d15, d6\n+\tvldr\td6, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td6, d15, d6\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td2, d2, d3\n+\tvmul.f64\td3, d3, d8\n+\tvldr\td8, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td5, d5, d8\n+\tvmul.f64\td6, d6, d8\n+\tvmul.f64\td2, d2, d8\n+\tvmul.f64\td12, d8, d11\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td2, d2, d3\n+\tvldr\td3, [pc, #636]\t@ 3080 <__gridxc_gga_MOD_rpbexc+0x828>\n+\tvmul.f64\td12, d12, d13\n+\tvmul.f64\td3, d4, d3\n+\tvmul.f64\td3, d3, d1\n+\tvdiv.f64\td10, d3, d4\n+\tvmov.f64\td4, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td14, d4, d14\n+\tvadd.f64\td10, d10, d1\n+\tvldr\td1, [sp, #144]\t@ 0x90\n+\tvmul.f64\td3, d1, d15\n+\tvdiv.f64\td3, d9, d3\n+\tvstr\td3, [sp, #16]\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvdiv.f64\td8, d9, d3\n+\tvmov.f64\td3, #16\t@ 0x40800000 4.0\n+\tvmov.f64\td9, d0\n+\tvmul.f64\td3, d0, d3\n+\tvldr\td0, [sp, #272]\t@ 0x110\n+\tvmla.f64\td4, d3, d0\n+\tvldr\td3, [sp, #88]\t@ 0x58\n+\tvmul.f64\td0, d14, d7\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td3, d4, d3\n+\tvmul.f64\td4, d2, d11\n+\tvmul.f64\td5, d5, d11\n+\tvmul.f64\td6, d6, d11\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tvstr\td3, [sp, #8]\n+\tvmul.f64\td3, d14, d11\n+\tvldr\td2, [sp, #72]\t@ 0x48\n+\tvstr\td4, [sp, #48]\t@ 0x30\n+\tvldr\td4, [sp, #280]\t@ 0x118\n+\tvmul.f64\td11, d2, d11\n+\tvstr\td8, [sp, #40]\t@ 0x28\n+\tvmul.f64\td7, d3, d7\n+\tvsub.f64\td8, d4, d1\n+\tvadd.f64\td4, d2, d4\n+\tvldr\td2, [sp, #16]\n+\tvnmls.f64\td7, d8, d2\n+\tvldr\td2, [sp, #24]\n+\tvadd.f64\td8, d10, d0\n+\tvmul.f64\td7, d7, d2\n+\tvldr\td2, [sp, #8]\n \tldr\tr5, [sp, #292]\t@ 0x124\n+\tldr\tr4, [sp, #296]\t@ 0x128\n+\tvmul.f64\td8, d8, d2\n+\tvldr\td2, [sp, #104]\t@ 0x68\n+\tldr\tr0, [sp, #300]\t@ 0x12c\n \tldrd\tr2, r3, [sp, #352]\t@ 0x160\n \tstrd\tr2, r3, [r7]\n+\tvnmls.f64\td8, d2, d7\n+\tvldr\td2, [sp, #64]\t@ 0x40\n \tldrd\tr2, r3, [sp, #456]\t@ 0x1c8\n-\tvsub.f64\td22, d22, d16\n-\tvldr\td16, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td16, d16, d13\n-\tvmul.f64\td22, d22, d27\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [sp, #128]\t@ 0x80\n-\tvdiv.f64\td29, d16, d17\n-\tvldr\td16, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td19, d16, d9\n-\tvldr\td16, [sp, #176]\t@ 0xb0\n-\tvdiv.f64\td24, d20, d16\n-\tvldr\td16, [sp, #144]\t@ 0x90\n-\tvmul.f64\td19, d19, d22\n-\tvdiv.f64\td26, d20, d16\n-\tvldr\td16, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td17, d10, d16\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td16, d10, d16\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td24, d24, d11\n-\tvmul.f64\td17, d17, d21\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td18, d18, d21\n-\tvmul.f64\td21, d21, d28\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td21, d21, d26\n-\tvdiv.f64\td24, d25, d23\n-\tvldr\td23, [sp, #112]\t@ 0x70\n-\tvmov.f64\td25, #0\t@ 0x40000000 2.0\n-\tvdiv.f64\td27, d25, d23\n-\tvmul.f64\td23, d6, d10\n-\tvdiv.f64\td30, d20, d23\n-\tvdiv.f64\td23, d20, d5\n-\tvmov.f64\td20, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td20, d13, d20\n-\tvfma.f64\td25, d20, d31\n-\tvmul.f64\td25, d25, d11\n-\tvmul.f64\td17, d17, d25\n-\tvmul.f64\td16, d16, d25\n-\tvmul.f64\td18, d18, d25\n-\tvmul.f64\td11, d25, d11\n-\tvmov.f64\td25, #8\t@ 0x40400000 3.0\n-\tvadd.f64\td24, d24, d9\n-\tvmul.f64\td17, d17, d28\n-\tvmul.f64\td16, d16, d28\n-\tvmul.f64\td18, d18, d28\n-\tvldr\td28, [sp, #280]\t@ 0x118\n-\tvmul.f64\td31, d27, d25\n-\tvmul.f64\td25, d4, d25\n-\tvsub.f64\td20, d28, d6\n-\tvadd.f64\td28, d4, d28\n-\tvmul.f64\td20, d20, d30\n-\tvfms.f64\td20, d31, d19\n-\tvmul.f64\td19, d27, d19\n-\tvadd.f64\td7, d24, d19\n-\tvmul.f64\td19, d25, d19\n-\tvmul.f64\td20, d29, d20\n-\tvnmul.f64\td7, d11, d7\n-\tvfma.f64\td7, d2, d20\n-\tvmul.f64\td20, d5, d20\n-\tvfma.f64\td20, d13, d7\n-\tvmul.f64\td7, d23, d7\n-\tvfms.f64\td7, d3, d20\n-\tvfma.f64\td19, d21, d7\n-\tvfma.f64\td28, d10, d19\n-\tvmov.f64\td19, d23\n-\tvfms.f64\td19, d13, d3\n-\tvstr\td28, [r5]\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td19, d18, d19\n-\tvmul.f64\td17, d17, d26\n-\tvmul.f64\td16, d16, d26\n-\tvmul.f64\td19, d19, d26\n-\tvstr\td17, [r0]\n-\tvstr\td16, [r0, #8]\n-\tvstr\td19, [r0, #16]\n-\tldr\tr4, [sp, #296]\t@ 0x128\n \tstrd\tr2, r3, [r4]\n+\tvmul.f64\td7, d2, d7\n+\tvldr\td2, [sp, #96]\t@ 0x60\n \tldrd\tr2, r3, [sp, #464]\t@ 0x1d0\n \tstrd\tr2, r3, [r4, #8]\n \tldrd\tr2, r3, [sp, #472]\t@ 0x1d8\n \tstrd\tr2, r3, [r4, #16]\n-\tbeq.n\t2cca <__gridxc_gga_MOD_rpbexc+0x6f2>\n-\tvldr\td18, [sp, #312]\t@ 0x138\n-\tvldr\td20, [sp, #304]\t@ 0x130\n+\tvmla.f64\td7, d9, d8\n+\tvmul.f64\td7, d7, d2\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvnmls.f64\td7, d2, d8\n+\tvmov.f64\td8, d2\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d11, d0\n+\tvmov.f64\td0, d9\n+\tvldr\td9, [sp, #96]\t@ 0x60\n+\tvmla.f64\td4, d7, d15\n+\tvmov.f64\td7, d2\n+\tvmls.f64\td7, d0, d9\n+\tvstr\td4, [r5]\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td7, d4, d7\n+\tvmul.f64\td5, d5, d13\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td7, d7, d13\n+\tvstr\td5, [r0]\n+\tvstr\td6, [r0, #8]\n+\tvstr\td7, [r0, #16]\n+\tbeq.n\t2ff6 <__gridxc_gga_MOD_rpbexc+0x79e>\n+\tvldr\td13, [sp, #312]\t@ 0x138\n+\tvldr\td4, [sp, #32]\n+\tvstr\td7, [r0, #40]\t@ 0x28\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvnmul.f64\td4, d4, d13\n+\tvldr\td13, [sp, #304]\t@ 0x130\n+\tvstr\td5, [r0, #24]\n+\tvldr\td5, [sp, #16]\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvmul.f64\td4, d4, d7\n+\tvsub.f64\td7, d13, d1\n+\tvstr\td6, [r0, #32]\n+\tvldr\td6, [sp, #72]\t@ 0x48\n \tldrd\tr2, r3, [sp, #360]\t@ 0x168\n-\tvnmul.f64\td9, d9, d18\n-\tvsub.f64\td18, d20, d6\n-\tvadd.f64\td20, d20, d4\n+\tvmul.f64\td3, d4, d3\n+\tvmla.f64\td10, d4, d14\n+\tvmul.f64\td4, d4, d11\n+\tvadd.f64\td6, d13, d6\n \tstrd\tr2, r3, [r7, #8]\n \tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n-\tvmul.f64\td9, d9, d22\n-\tvmul.f64\td18, d18, d30\n+\tvnmls.f64\td3, d7, d5\n+\tvldr\td7, [sp, #24]\n \tstrd\tr2, r3, [r4, #24]\n \tldrd\tr2, r3, [sp, #488]\t@ 0x1e8\n \tstrd\tr2, r3, [r4, #32]\n-\tvfms.f64\td18, d9, d31\n-\tvfma.f64\td24, d9, d27\n-\tvmul.f64\td9, d9, d25\n-\tvstr\td17, [r0, #24]\n \tldrd\tr2, r3, [sp, #496]\t@ 0x1f0\n \tstrd\tr2, r3, [r4, #40]\t@ 0x28\n-\tvstr\td16, [r0, #32]\n-\tvmul.f64\td9, d9, d27\n-\tvstr\td19, [r0, #40]\t@ 0x28\n-\tvmul.f64\td18, d18, d29\n-\tvnmul.f64\td11, d11, d24\n-\tvfma.f64\td11, d2, d18\n-\tvmul.f64\td15, d5, d18\n-\tvfma.f64\td15, d13, d11\n-\tvmul.f64\td23, d23, d11\n-\tvfms.f64\td23, d15, d3\n-\tvfma.f64\td9, d23, d21\n-\tvfma.f64\td20, d10, d9\n-\tvstr\td20, [r5, #8]\n-\tldr\tr2, [pc, #148]\t@ (2d60 <__gridxc_gga_MOD_rpbexc+0x788>)\n-\tldr\tr3, [pc, #148]\t@ (2d64 <__gridxc_gga_MOD_rpbexc+0x78c>)\n+\tvmul.f64\td3, d3, d7\n+\tvldr\td7, [sp, #8]\n+\tvmul.f64\td10, d10, d7\n+\tvldr\td7, [sp, #104]\t@ 0x68\n+\tvnmls.f64\td10, d7, d3\n+\tvmul.f64\td7, d0, d10\n+\tvmla.f64\td7, d2, d3\n+\tvmul.f64\td7, d7, d9\n+\tvnmls.f64\td7, d8, d10\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d4, d14\n+\tvmla.f64\td6, d7, d15\n+\tvstr\td6, [r5, #8]\n+\tldr\tr2, [pc, #152]\t@ (3090 <__gridxc_gga_MOD_rpbexc+0x838>)\n+\tldr\tr3, [pc, #152]\t@ (3094 <__gridxc_gga_MOD_rpbexc+0x83c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #556]\t@ 0x22c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t2d4c <__gridxc_gga_MOD_rpbexc+0x774>\n+\tbne.n\t307a <__gridxc_gga_MOD_rpbexc+0x822>\n \tadd.w\tsp, sp, #564\t@ 0x234\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td17, [r3, #16]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #8]\n-\tvmul.f64\td20, d16, d18\n-\tvmov.f64\td23, d17\n-\tvstr\td17, [sp, #80]\t@ 0x50\n-\tvmul.f64\td19, d22, d18\n-\tvldr\td10, [pc, #76]\t@ 2d58 <__gridxc_gga_MOD_rpbexc+0x780>\n-\tvmul.f64\td17, d21, d18\n-\tvstr\td21, [sp, #440]\t@ 0x1b8\n-\tvstr\td22, [sp, #432]\t@ 0x1b0\n-\tvmov.f64\td21, d22\n-\tvmul.f64\td18, d23, d18\n-\tvmaxnm.f64\td10, d16, d10\n-\tvmov.f64\td23, d19\n-\tvstr\td20, [sp, #336]\t@ 0x150\n-\tvmov.f64\td16, d17\n-\tvstr\td20, [sp, #344]\t@ 0x158\n-\tvstr\td19, [sp, #504]\t@ 0x1f8\n-\tvstr\td19, [sp, #528]\t@ 0x210\n-\tvstr\td17, [sp, #512]\t@ 0x200\n-\tvstr\td17, [sp, #536]\t@ 0x218\n-\tvstr\td18, [sp, #520]\t@ 0x208\n-\tb.n\t2698 <__gridxc_gga_MOD_rpbexc+0xc0>\n+\tvldr\td15, [pc, #112]\t@ 3088 <__gridxc_gga_MOD_rpbexc+0x830>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [r3, #16]\n+\tvldr\td4, [r3]\n+\tvmul.f64\td2, d7, d5\n+\tvcmpe.f64\td7, d15\n+\tvldr\td6, [r3, #8]\n+\tvmov.f64\td1, d3\n+\tvstr\td3, [sp, #80]\t@ 0x50\n+\tvstr\td4, [sp, #432]\t@ 0x1b0\n+\tvmul.f64\td4, d4, d5\n+\tvstr\td6, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td6, d6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td5, d3, d5\n+\tvstr\td2, [sp, #336]\t@ 0x150\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvstr\td4, [sp, #504]\t@ 0x1f8\n+\tvstr\td4, [sp, #528]\t@ 0x210\n+\tit\tge\n+\tvmovge.f64\td15, d7\n+\tvstr\td6, [sp, #512]\t@ 0x200\n+\tvmov.f64\td7, d6\n+\tvstr\td6, [sp, #536]\t@ 0x218\n+\tvstr\td5, [sp, #520]\t@ 0x208\n+\tb.n\t291a <__gridxc_gga_MOD_rpbexc+0xc2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000008e\n+\t.word\t0x00000092\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00002d68 <__gridxc_gga_MOD_blypxc>:\n+00003098 <__gridxc_gga_MOD_blypxc>:\n __gridxc_gga_MOD_blypxc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3672]\t@ 0xe58\n-\tldr.w\tr4, [pc, #1080]\t@ 31b8 <__gridxc_gga_MOD_blypxc+0x450>\n-\tsub\tsp, #324\t@ 0x144\n-\tldr\tr7, [r0, #0]\n+\tstr.w\tr0, [ip, #3616]\t@ 0xe20\n+\tvldr\td7, [pc, #992]\t@ 3490 <__gridxc_gga_MOD_blypxc+0x3f8>\n+\tsub\tsp, #380\t@ 0x17c\n+\tvldr\td8, [r1]\n \tmov\tip, r2\n-\tldr.w\tr0, [pc, #1076]\t@ 31bc <__gridxc_gga_MOD_blypxc+0x454>\n-\tadd\tr4, pc\n-\tvldr\td19, [pc, #1000]\t@ 3178 <__gridxc_gga_MOD_blypxc+0x410>\n+\tldr.w\tr5, [pc, #1044]\t@ 34d0 <__gridxc_gga_MOD_blypxc+0x438>\n \tmov\tr6, r3\n-\tvldr\td8, [r1]\n+\tldr.w\tr4, [pc, #1044]\t@ 34d4 <__gridxc_gga_MOD_blypxc+0x43c>\n+\tvcmpe.f64\td8, d7\n+\tadd\tr5, pc\n+\tldr\tr7, [r0, #0]\n+\tldr.w\tsl, [sp, #480]\t@ 0x1e0\n+\tldr\tr4, [r5, r4]\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tldr\tr4, [r4, #0]\n+\tstr\tr4, [sp, #372]\t@ 0x174\n+\tmov.w\tr4, #0\n+\tldrd\tr8, r9, [sp, #484]\t@ 0x1e4\n+\tldrd\tr4, r5, [sp, #492]\t@ 0x1ec\n+\tite\tlt\n+\tvmovlt.f64\td6, d7\n+\tvmovge.f64\td6, d8\n \tcmp\tr7, #1\n-\tldr.w\tsl, [sp, #424]\t@ 0x1a8\n-\tldr\tr0, [r4, r0]\n-\tvmaxnm.f64\td17, d8, d19\n-\tldrd\tr8, r9, [sp, #428]\t@ 0x1ac\n-\tldr\tr0, [r0, #0]\n-\tstr\tr0, [sp, #316]\t@ 0x13c\n-\tmov.w\tr0, #0\n-\tldrd\tr4, r5, [sp, #436]\t@ 0x1b4\n-\tbeq.w\t37ca <__gridxc_gga_MOD_blypxc+0xa62>\n-\tadd.w\tfp, sp, #264\t@ 0x108\n+\tvstr\td6, [sp]\n+\tbeq.w\t3be6 <__gridxc_gga_MOD_blypxc+0xb4e>\n+\tvldr\td15, [r1, #8]\n+\tadd.w\tfp, sp, #320\t@ 0x140\n \tldr\tr0, [r2, #0]\n-\tvldr\td16, [r1, #8]\n-\tadd.w\tlr, sp, #288\t@ 0x120\n+\tadd.w\tlr, sp, #344\t@ 0x158\n \tldr\tr1, [r2, #4]\n-\tvmov.f64\td12, d17\n+\tvmov.f64\td10, d6\n+\tvcmpe.f64\td15, d7\n+\tvadd.f64\td8, d15, d8\n \tldr\tr2, [r2, #8]\n \tldr.w\tr3, [ip, #12]\n-\tvadd.f64\td8, d16, d8\n \tstmia.w\tfp!, {r0, r1, r2, r3}\n-\tvmaxnm.f64\td16, d16, d19\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td8, d7\n \tldr.w\tr0, [ip, #16]\n \tldr.w\tr1, [ip, #20]\n \tstmia.w\tfp!, {r0, r1}\n-\tvmaxnm.f64\td8, d8, d19\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n+\tvstr\td6, [sp, #240]\t@ 0xf0\n+\tit\tlt\n+\tvmovlt.f64\td15, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n \tldr.w\tr0, [ip, #24]\n \tldr.w\tr1, [ip, #28]\n \tldr.w\tr2, [ip, #32]\n \tldr.w\tr3, [ip, #36]\t@ 0x24\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n+\tit\tlt\n+\tvmovlt.f64\td8, d7\n \tldr.w\tr0, [ip, #40]\t@ 0x28\n \tldr.w\tr1, [ip, #44]\t@ 0x2c\n \tstmia.w\tlr!, {r0, r1}\n-\tvstr\td16, [sp, #192]\t@ 0xc0\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tvldr\td19, [sp, #296]\t@ 0x128\n-\tvldr\td22, [sp, #264]\t@ 0x108\n-\tvldr\td23, [sp, #288]\t@ 0x120\n-\tvmul.f64\td20, d18, d18\n-\tvstr\td19, [sp, #32]\n-\tvmul.f64\td19, d19, d19\n-\tvfma.f64\td20, d22, d22\n-\tvldr\td24, [sp, #280]\t@ 0x118\n-\tvfma.f64\td19, d23, d23\n-\tvldr\td25, [sp, #304]\t@ 0x130\n-\tvstr\td18, [sp, #8]\n-\tvstr\td22, [sp]\n-\tvfma.f64\td20, d24, d24\n-\tvldr\td22, [pc, #816]\t@ 3180 <__gridxc_gga_MOD_blypxc+0x418>\n-\tvfma.f64\td19, d25, d25\n-\tvldr\td21, [pc, #800]\t@ 3178 <__gridxc_gga_MOD_blypxc+0x410>\n-\tvstr\td23, [sp, #24]\n-\tvcmpe.f64\td12, d22\n-\tvstr\td24, [sp, #16]\n-\tvstr\td25, [sp, #40]\t@ 0x28\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvsqrt.f64\td18, d20\n-\tvsqrt.f64\td9, d19\n-\tvmaxnm.f64\td10, d18, d21\n-\tvmaxnm.f64\td18, d9, d21\n-\tvstr\td10, [sp, #56]\t@ 0x38\n-\tvstr\td18, [sp, #48]\t@ 0x30\n-\tbmi.w\t36d8 <__gridxc_gga_MOD_blypxc+0x970>\n-\tvmov.f64\td0, d12\n-\tvstr\td22, [sp, #80]\t@ 0x50\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvstr\td16, [sp, #64]\t@ 0x40\n+\tvstr\td15, [sp, #248]\t@ 0xf8\n+\tvldr\td7, [sp, #328]\t@ 0x148\n+\tvldr\td6, [sp, #320]\t@ 0x140\n+\tvldr\td5, [sp, #336]\t@ 0x150\n+\tvstr\td7, [sp, #24]\n+\tvmul.f64\td7, d7, d7\n+\tvmla.f64\td7, d6, d6\n+\tvldr\td3, [sp, #352]\t@ 0x160\n+\tvldr\td4, [sp, #344]\t@ 0x158\n+\tvstr\td5, [sp, #32]\n+\tvstr\td6, [sp, #16]\n+\tvmla.f64\td7, d5, d5\n+\tvldr\td6, [sp, #360]\t@ 0x168\n+\tvldr\td13, [pc, #764]\t@ 3498 <__gridxc_gga_MOD_blypxc+0x400>\n+\tvstr\td4, [sp, #40]\t@ 0x28\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tvsqrt.f64\td5, d7\n+\tvmul.f64\td7, d3, d3\n+\tvmla.f64\td7, d4, d4\n+\tvmla.f64\td7, d6, d6\n+\tvsqrt.f64\td6, d7\n+\tvldr\td7, [pc, #720]\t@ 3490 <__gridxc_gga_MOD_blypxc+0x3f8>\n+\tvcmpe.f64\td5, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td9, d7\n+\tvmovge.f64\td9, d5\n+\tvcmpe.f64\td6, d7\n+\tvstr\td9, [sp, #64]\t@ 0x40\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td10, d13\n+\tit\tge\n+\tvmovge.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td7, [sp, #8]\n+\tbmi.w\t3b04 <__gridxc_gga_MOD_blypxc+0xa6c>\n+\tvmov.f64\td0, d10\n+\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td0, d0, d12\n-\tvldr\td13, [pc, #736]\t@ 3188 <__gridxc_gga_MOD_blypxc+0x420>\n-\tvdiv.f64\td10, d10, d0\n-\tvmul.f64\td14, d10, d10\n-\tvstr\td10, [sp, #200]\t@ 0xc8\n-\tvadd.f64\td19, d14, d9\n-\tvsqrt.f64\td0, d19\n-\tvadd.f64\td0, d0, d10\n+\tvmul.f64\td0, d0, d10\n+\tvdiv.f64\td9, d9, d0\n+\tvmul.f64\td11, d9, d9\n+\tvstr\td9, [sp, #256]\t@ 0x100\n+\tvadd.f64\td7, d11, d12\n+\tvsqrt.f64\td0, d7\n+\tvadd.f64\td0, d0, d9\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td20, [pc, #712]\t@ 3190 <__gridxc_gga_MOD_blypxc+0x428>\n-\tvldr\td19, [pc, #716]\t@ 3198 <__gridxc_gga_MOD_blypxc+0x430>\n-\tvldr\td11, [sp, #192]\t@ 0xc0\n-\tvmul.f64\td0, d0, d20\n-\tvmov.f64\td20, d9\n-\tvmul.f64\td14, d14, d19\n-\tvldr\td22, [sp, #80]\t@ 0x50\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvfma.f64\td20, d0, d10\n-\tvcmpe.f64\td11, d22\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvdiv.f64\td15, d14, d20\n-\tvsub.f64\td15, d13, d15\n-\tbmi.w\t376a <__gridxc_gga_MOD_blypxc+0xa02>\n-\tvmov.f64\td0, d11\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #64]\t@ 0x40\n+\tvldr\td7, [pc, #636]\t@ 34a0 <__gridxc_gga_MOD_blypxc+0x408>\n+\tvmov.f64\td6, d12\n+\tvldr\td5, [pc, #636]\t@ 34a8 <__gridxc_gga_MOD_blypxc+0x410>\n+\tvmul.f64\td7, d0, d7\n+\tvmul.f64\td5, d11, d5\n+\tvldr\td11, [pc, #632]\t@ 34b0 <__gridxc_gga_MOD_blypxc+0x418>\n+\tvmla.f64\td6, d7, d9\n+\tvldr\td9, [sp, #248]\t@ 0xf8\n+\tvcmpe.f64\td9, d13\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvdiv.f64\td7, d5, d6\n+\tvsub.f64\td7, d11, d7\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tbmi.w\t3b8a <__gridxc_gga_MOD_blypxc+0xaf2>\n+\tvmov.f64\td0, d9\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td0, d0, d11\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td10, d16, d0\n-\tvmul.f64\td13, d10, d10\n-\tvstr\td10, [sp, #208]\t@ 0xd0\n-\tvadd.f64\td19, d13, d9\n-\tvsqrt.f64\td0, d19\n-\tvadd.f64\td0, d0, d10\n+\tvmul.f64\td0, d0, d9\n+\tvldr\td7, [sp, #8]\n+\tvdiv.f64\td12, d7, d0\n+\tvmul.f64\td13, d12, d12\n+\tvstr\td12, [sp, #264]\t@ 0x108\n+\tvadd.f64\td7, d13, d11\n+\tvsqrt.f64\td0, d7\n+\tvadd.f64\td0, d0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmov.f64\td19, d0\n-\tvldr\td23, [pc, #592]\t@ 3190 <__gridxc_gga_MOD_blypxc+0x428>\n-\tvldr\td22, [pc, #596]\t@ 3198 <__gridxc_gga_MOD_blypxc+0x430>\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvmul.f64\td19, d19, d23\n-\tvldr\td20, [pc, #568]\t@ 3188 <__gridxc_gga_MOD_blypxc+0x420>\n-\tvmul.f64\td13, d13, d22\n-\tvmov.f64\td22, d9\n-\tvmov.f64\td0, d17\n-\tvfma.f64\td22, d19, d10\n-\tvdiv.f64\td14, d13, d22\n-\tvsub.f64\td14, d20, d14\n+\tvldr\td7, [pc, #532]\t@ 34a0 <__gridxc_gga_MOD_blypxc+0x408>\n+\tvmov.f64\td6, d11\n+\tvmul.f64\td7, d0, d7\n+\tvldr\td0, [sp]\n+\tvmla.f64\td6, d7, d12\n+\tvldr\td7, [pc, #520]\t@ 34a8 <__gridxc_gga_MOD_blypxc+0x410>\n+\tvmul.f64\td7, d13, d7\n+\tvdiv.f64\td13, d11, d8\n+\tvdiv.f64\td5, d7, d6\n+\tvldr\td7, [pc, #512]\t@ 34b0 <__gridxc_gga_MOD_blypxc+0x418>\n+\tvsub.f64\td12, d7, d5\n+\tvstr\td12, [sp, #80]\t@ 0x50\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvmov.f64\td10, d0\n-\tvmov.f64\td0, d16\n+\tvmov.f64\td14, d0\n+\tvstr\td0, [sp, #96]\t@ 0x60\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvdiv.f64\td19, d9, d8\n-\tvmul.f64\td21, d0, d14\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvmov.f64\td9, d0\n-\tvmul.f64\td22, d15, d17\n-\tvldr\td23, [pc, #488]\t@ 3180 <__gridxc_gga_MOD_blypxc+0x418>\n-\tvmul.f64\td21, d21, d16\n-\tvcmpe.f64\td12, d23\n-\tvfma.f64\td21, d22, d10\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td18, d19, d19\n-\tvstr\td18, [sp, #128]\t@ 0x80\n-\tvmul.f64\td18, d21, d19\n-\tvstr\td18, [sp, #104]\t@ 0x68\n-\tbmi.w\t3742 <__gridxc_gga_MOD_blypxc+0x9da>\n-\tvldr\td13, [sp, #200]\t@ 0xc8\n-\tvmov.f64\td23, #112\t@ 0x3f800000 1.0\n-\tvstr\td17, [sp, #112]\t@ 0x70\n-\tvstr\td19, [sp, #96]\t@ 0x60\n-\tvmul.f64\td22, d13, d13\n-\tvstr\td16, [sp, #88]\t@ 0x58\n-\tvstr\td23, [sp, #80]\t@ 0x50\n-\tvadd.f64\td24, d22, d23\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvsqrt.f64\td25, d24\n-\tvadd.f64\td0, d13, d25\n-\tvstr\td25, [sp, #64]\t@ 0x40\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvldr\td5, [sp]\n+\tvmov.f64\td7, d0\n+\tvldr\td4, [pc, #444]\t@ 3498 <__gridxc_gga_MOD_blypxc+0x400>\n+\tvmul.f64\td5, d6, d5\n+\tvmul.f64\td6, d0, d12\n+\tvcmpe.f64\td10, d4\n+\tvmul.f64\td6, d6, d15\n+\tvmla.f64\td6, d5, d14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td6, [sp, #88]\t@ 0x58\n+\tvmul.f64\td6, d13, d13\n+\tvstr\td6, [sp, #176]\t@ 0xb0\n+\tbmi.w\t3b62 <__gridxc_gga_MOD_blypxc+0xaca>\n+\tvldr\td11, [sp, #256]\t@ 0x100\n+\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvmul.f64\td2, d11, d11\n+\tvadd.f64\td6, d2, d12\n+\tvstr\td2, [sp, #112]\t@ 0x70\n+\tvsqrt.f64\td4, d6\n+\tvadd.f64\td0, d11, d4\n+\tvstr\td4, [sp, #104]\t@ 0x68\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td25, [sp, #64]\t@ 0x40\n-\tvldr\td26, [pc, #408]\t@ 3190 <__gridxc_gga_MOD_blypxc+0x428>\n-\tvldr\td23, [sp, #80]\t@ 0x50\n-\tvdiv.f64\td24, d13, d25\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tvmul.f64\td26, d13, d26\n-\tvsub.f64\td25, d24, d0\n-\tvmov.f64\td24, d23\n-\tvfma.f64\td24, d26, d0\n-\tvldr\td26, [pc, #392]\t@ 31a0 <__gridxc_gga_MOD_blypxc+0x438>\n-\tvmov.f64\td0, d12\n-\tvmul.f64\td22, d22, d26\n-\tvmul.f64\td22, d22, d25\n-\tvldr\td25, [pc, #384]\t@ 31a8 <__gridxc_gga_MOD_blypxc+0x440>\n-\tvmul.f64\td24, d24, d24\n-\tvfms.f64\td22, d13, d25\n-\tvdiv.f64\td18, d22, d24\n-\tvneg.f64\td22, d13\n-\tvstr\td22, [sp, #64]\t@ 0x40\n-\tvstr\td18, [sp, #72]\t@ 0x48\n+\tvldr\td4, [sp, #104]\t@ 0x68\n+\tvmov.f64\td6, d12\n+\tvldr\td2, [sp, #112]\t@ 0x70\n+\tvldr\td3, [pc, #376]\t@ 34b8 <__gridxc_gga_MOD_blypxc+0x420>\n+\tvdiv.f64\td5, d11, d4\n+\tvldr\td4, [pc, #344]\t@ 34a0 <__gridxc_gga_MOD_blypxc+0x408>\n+\tvmul.f64\td3, d2, d3\n+\tvmul.f64\td4, d11, d4\n+\tvmla.f64\td6, d4, d0\n+\tvldr\td4, [pc, #360]\t@ 34c0 <__gridxc_gga_MOD_blypxc+0x428>\n+\tvmul.f64\td4, d11, d4\n+\tvmul.f64\td6, d6, d6\n+\tvsub.f64\td5, d5, d0\n+\tvmov.f64\td0, d10\n+\tvnmls.f64\td4, d5, d3\n+\tvdiv.f64\td3, d4, d6\n+\tvstr\td3, [sp, #104]\t@ 0x68\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td23, [sp, #80]\t@ 0x50\n-\tvmul.f64\td12, d0, d12\n-\tvldr\td18, [sp, #72]\t@ 0x48\n-\tvldr\td22, [sp, #64]\t@ 0x40\n-\tvdiv.f64\td24, d23, d13\n-\tvldr\td19, [sp, #96]\t@ 0x60\n-\tvdiv.f64\td23, d18, d12\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tvfma.f64\td15, d18, d22\n-\tvldr\td22, [pc, #324]\t@ 31b0 <__gridxc_gga_MOD_blypxc+0x448>\n-\tvmul.f64\td0, d0, d22\n-\tvmul.f64\td16, d0, d15\n-\tvstr\td16, [sp, #144]\t@ 0x90\n-\tvldr\td16, [sp]\n-\tvmul.f64\td21, d16, d24\n-\tvldr\td16, [sp, #8]\n-\tvmul.f64\td22, d16, d24\n-\tvldr\td16, [sp, #16]\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td24, d16, d24\n-\tvmul.f64\td22, d22, d23\n-\tvmul.f64\td16, d24, d23\n-\tvstr\td16, [sp, #136]\t@ 0x88\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvldr\td23, [pc, #216]\t@ 3180 <__gridxc_gga_MOD_blypxc+0x418>\n-\tvstr\td21, [sp, #216]\t@ 0xd8\n-\tvstr\td22, [sp, #224]\t@ 0xe0\n-\tvcmpe.f64\td11, d23\n+\tvdiv.f64\td6, d12, d11\n+\tvmul.f64\td10, d0, d10\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvdiv.f64\td4, d3, d10\n+\tvmls.f64\td5, d11, d3\n+\tvldr\td3, [pc, #308]\t@ 34c8 <__gridxc_gga_MOD_blypxc+0x430>\n+\tvmul.f64\td0, d0, d3\n+\tvmul.f64\td7, d5, d0\n+\tvstr\td7, [sp, #192]\t@ 0xc0\n+\tvldr\td7, [sp, #16]\n+\tvmul.f64\td5, d7, d6\n+\tvldr\td7, [sp, #24]\n+\tvmul.f64\td3, d7, d6\n+\tvldr\td7, [sp, #32]\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td3, d3, d4\n+\tvmul.f64\td7, d6, d4\n+\tvstr\td7, [sp, #184]\t@ 0xb8\n+\tvldr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td6, [pc, #200]\t@ 3498 <__gridxc_gga_MOD_blypxc+0x400>\n+\tvstr\td5, [sp, #272]\t@ 0x110\n+\tvstr\td3, [sp, #280]\t@ 0x118\n+\tvcmpe.f64\td9, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t3754 <__gridxc_gga_MOD_blypxc+0x9ec>\n-\tvldr\td12, [sp, #208]\t@ 0xd0\n-\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n-\tvstr\td17, [sp, #88]\t@ 0x58\n-\tvstr\td19, [sp, #80]\t@ 0x50\n-\tvmul.f64\td13, d12, d12\n-\tvstr\td16, [sp, #72]\t@ 0x48\n-\tvadd.f64\td22, d13, d15\n-\tvsqrt.f64\td23, d22\n-\tvadd.f64\td0, d12, d23\n-\tvstr\td23, [sp, #64]\t@ 0x40\n+\tbmi.w\t3b74 <__gridxc_gga_MOD_blypxc+0xadc>\n+\tvldr\td10, [sp, #264]\t@ 0x108\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvmul.f64\td12, d10, d10\n+\tvadd.f64\td6, d12, d11\n+\tvsqrt.f64\td4, d6\n+\tvadd.f64\td0, d10, d4\n+\tvstr\td4, [sp, #72]\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td23, [sp, #64]\t@ 0x40\n-\tvldr\td24, [pc, #160]\t@ 3190 <__gridxc_gga_MOD_blypxc+0x428>\n-\tvdiv.f64\td22, d12, d23\n-\tvmul.f64\td24, d12, d24\n-\tvsub.f64\td23, d22, d0\n-\tvmov.f64\td22, d15\n-\tvfma.f64\td22, d24, d0\n-\tvldr\td24, [pc, #152]\t@ 31a0 <__gridxc_gga_MOD_blypxc+0x438>\n-\tvmov.f64\td0, d11\n-\tvmul.f64\td21, d13, d24\n-\tvmul.f64\td21, d21, d23\n-\tvldr\td23, [pc, #144]\t@ 31a8 <__gridxc_gga_MOD_blypxc+0x440>\n-\tvmul.f64\td22, d22, d22\n-\tvfms.f64\td21, d12, d23\n-\tvdiv.f64\td13, d21, d22\n-\tvneg.f64\td21, d12\n-\tvstr\td21, [sp, #64]\t@ 0x40\n+\tvldr\td4, [sp, #72]\t@ 0x48\n+\tvmov.f64\td6, d11\n+\tvldr\td3, [pc, #164]\t@ 34b8 <__gridxc_gga_MOD_blypxc+0x420>\n+\tvdiv.f64\td5, d10, d4\n+\tvldr\td4, [pc, #132]\t@ 34a0 <__gridxc_gga_MOD_blypxc+0x408>\n+\tvmul.f64\td3, d12, d3\n+\tvmul.f64\td4, d10, d4\n+\tvmla.f64\td6, d4, d0\n+\tvldr\td4, [pc, #148]\t@ 34c0 <__gridxc_gga_MOD_blypxc+0x428>\n+\tvmul.f64\td4, d10, d4\n+\tvmul.f64\td6, d6, d6\n+\tvsub.f64\td5, d5, d0\n+\tvmov.f64\td0, d9\n+\tvnmls.f64\td4, d5, d3\n+\tvdiv.f64\td12, d4, d6\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvdiv.f64\td22, d15, d12\n-\tvldr\td21, [sp, #64]\t@ 0x40\n-\tvmul.f64\td11, d0, d11\n-\tvldr\td19, [sp, #80]\t@ 0x50\n-\tvldr\td17, [sp, #88]\t@ 0x58\n-\tvfma.f64\td14, d21, d13\n-\tvldr\td21, [pc, #100]\t@ 31b0 <__gridxc_gga_MOD_blypxc+0x448>\n-\tvmul.f64\td0, d0, d21\n-\tvdiv.f64\td21, d13, d11\n-\tvmul.f64\td16, d0, d14\n-\tvstr\td16, [sp, #176]\t@ 0xb0\n-\tvldr\td16, [sp, #24]\n-\tvmul.f64\td24, d16, d22\n-\tvldr\td16, [sp, #32]\n-\tvmul.f64\td23, d16, d22\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tb.n\t31c0 <__gridxc_gga_MOD_blypxc+0x458>\n-\tnop\n+\tvdiv.f64\td6, d11, d10\n+\tvmul.f64\td9, d0, d9\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvldr\td3, [pc, #112]\t@ 34c8 <__gridxc_gga_MOD_blypxc+0x430>\n+\tvmul.f64\td0, d0, d3\n+\tvdiv.f64\td4, d12, d9\n+\tvmls.f64\td5, d10, d12\n+\tvmul.f64\td7, d5, d0\n+\tvstr\td7, [sp, #232]\t@ 0xe8\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvmul.f64\td5, d7, d6\n+\tvmul.f64\td7, d5, d4\n+\tvstr\td7, [sp, #216]\t@ 0xd8\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvmul.f64\td5, d7, d6\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tb.n\t34d8 <__gridxc_gga_MOD_blypxc+0x440>\n \tnop.w\n \t.word\t0xe2308c3a\n \t.word\t0x3e45798e\n \t.word\t0x88e368f1\n \t.word\t0x3ee4f8b5\n-\t.word\t0xe8b6951e\n-\t.word\t0xbfedc6dd\n \t.word\t0x5f6fd220\n \t.word\t0x3f99ce07\n \t.word\t0xea4a8c15\n \t.word\t0x3f713404\n+\t.word\t0xe8b6951e\n+\t.word\t0xbfedc6dd\n \t.word\t0x5abc392a\n \t.word\t0x3f1bbecd\n \t.word\t0xea4a8c15\n \t.word\t0x3f813404\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n-\t.word\t0x0000042a\n+\t.word\t0x00000406\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\tvmul.f64\td22, d16, d22\n-\tvmul.f64\td16, d24, d21\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td16, d23, d21\n-\tvstr\td16, [sp, #152]\t@ 0x98\n-\tvmul.f64\td16, d22, d21\n-\tvstr\td16, [sp, #168]\t@ 0xa8\n-\tvldr\td16, [sp, #72]\t@ 0x48\n-\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td7, d5, d4\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td7, d6, d4\n+\tvstr\td7, [sp, #224]\t@ 0xe0\n+\tvldr\td7, [sp, #104]\t@ 0x68\n \tvmov.f64\td0, d8\n-\tvstr\td17, [sp, #96]\t@ 0x60\n-\tvmul.f64\td10, d10, d10\n-\tvstr\td19, [sp, #88]\t@ 0x58\n-\tvstr\td16, [sp, #80]\t@ 0x50\n+\tvstr\td7, [sp, #80]\t@ 0x50\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvdiv.f64\td12, d13, d0\n-\tvldr\td21, [pc, #868]\t@ 3568 <__gridxc_gga_MOD_blypxc+0x800>\n-\tvldr\td24, [pc, #872]\t@ 3570 <__gridxc_gga_MOD_blypxc+0x808>\n-\tvmul.f64\td22, d8, d8\n-\tvmul.f64\td15, d0, d0\n-\tvmov.f64\td11, d0\n-\tvstr\td21, [sp, #120]\t@ 0x78\n-\tvstr\td24, [sp, #112]\t@ 0x70\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvmul.f64\td31, d12, d21\n-\tvmul.f64\td12, d12, d24\n-\tvadd.f64\td14, d12, d13\n-\tvneg.f64\td0, d31\n-\tvstr\td31, [sp, #64]\t@ 0x40\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [pc, #996]\t@ 38e8 <__gridxc_gga_MOD_blypxc+0x850>\n+\tvmul.f64\td12, d0, d0\n+\tvdiv.f64\td9, d7, d0\n+\tvldr\td4, [pc, #992]\t@ 38f0 <__gridxc_gga_MOD_blypxc+0x858>\n+\tvstr\td0, [sp, #168]\t@ 0xa8\n+\tvmov.f64\td14, d7\n+\tvmul.f64\td11, d8, d8\n+\tvmul.f64\td5, d9, d6\n+\tvmul.f64\td9, d9, d4\n+\tvneg.f64\td0, d5\n+\tvadd.f64\td10, d9, d7\n+\tvstr\td5, [sp, #72]\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvmov.f64\td28, #28\t@ 0x40e00000 7.0\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n-\tvdiv.f64\td26, d13, d14\n-\tvldr\td31, [sp, #64]\t@ 0x40\n-\tvstr\td16, [r6]\n-\tvmul.f64\td3, d9, d9\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvmul.f64\td20, d8, d22\n-\tvldr\td17, [sp, #96]\t@ 0x60\n-\tvmul.f64\td14, d8, d14\n-\tvldr\td23, [pc, #780]\t@ 3578 <__gridxc_gga_MOD_blypxc+0x810>\n-\tvmov.f64\td27, #38\t@ 0x41300000 11.0\n-\tvmul.f64\td1, d16, d16\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvmul.f64\td20, d20, d15\n-\tvldr\td19, [pc, #768]\t@ 3580 <__gridxc_gga_MOD_blypxc+0x818>\n-\tvmov.f64\td18, d23\n-\tvldr\td21, [sp, #32]\n-\tvmul.f64\td24, d16, d16\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvldr\td2, [sp, #24]\n-\tvmov.f64\td9, #240\t@ 0xbf800000 -1.0\n-\tvdiv.f64\td5, d0, d20\n-\tvldr\td4, [pc, #744]\t@ 3588 <__gridxc_gga_MOD_blypxc+0x820>\n-\tvmul.f64\td20, d17, d16\n-\tvldr\td30, [pc, #744]\t@ 3590 <__gridxc_gga_MOD_blypxc+0x828>\n-\tvmul.f64\td29, d17, d17\n+\tvldr\td3, [sp, #88]\t@ 0x58\n \tcmp\tr7, #0\n-\tvstr\td24, [sp, #56]\t@ 0x38\n-\tvmul.f64\td23, d20, d19\n-\tvldr\td19, [sp, #8]\n-\tvmul.f64\td10, d10, d29\n-\tvmul.f64\td25, d19, d21\n-\tvldr\td19, [sp, #16]\n-\tvdiv.f64\td0, d23, d14\n-\tvmul.f64\td23, d16, d16\n-\tvmul.f64\td3, d3, d23\n-\tvfma.f64\td31, d12, d26\n-\tvfma.f64\td18, d31, d28\n-\tvldr\td28, [sp]\n-\tvfma.f64\td9, d31, d7\n-\tvsub.f64\td12, d31, d27\n-\tvmul.f64\td5, d5, d26\n-\tvfma.f64\td25, d28, d2\n-\tvmul.f64\td28, d20, d4\n-\tvmul.f64\td6, d12, d17\n-\tvmul.f64\td12, d12, d16\n-\tvstr\td18, [sp, #48]\t@ 0x30\n-\tvmov.f64\td21, d9\n-\tvmov.f64\td14, d25\n-\tvldr\td25, [sp, #40]\t@ 0x28\n-\tvfma.f64\td14, d19, d25\n-\tvldr\td19, [sp, #88]\t@ 0x58\n-\tvfma.f64\td21, d6, d19\n-\tvfma.f64\td23, d21, d28\n-\tvstr\td21, [sp, #64]\t@ 0x40\n-\tvmov.f64\td25, d23\n-\tvmul.f64\td23, d18, d28\n-\tvfma.f64\td23, d22, d30\n-\tvmov.f64\td22, d9\n-\tvfma.f64\td22, d12, d19\n-\tvadd.f64\td30, d10, d3\n-\tvfma.f64\td29, d22, d28\n-\tvmov.f64\td2, d22\n-\tvldr\td22, [pc, #664]\t@ 35d8 <__gridxc_gga_MOD_blypxc+0x870>\n-\tvmul.f64\td28, d20, d22\n-\tvmul.f64\td28, d28, d30\n-\tvfma.f64\td0, d5, d28\n-\tvldr\td28, [pc, #584]\t@ 3598 <__gridxc_gga_MOD_blypxc+0x830>\n-\tvmul.f64\td28, d5, d28\n-\tvmul.f64\td23, d23, d28\n-\tvmul.f64\td25, d25, d28\n-\tvmov.f64\td22, d0\n-\tvmul.f64\td29, d29, d28\n-\tvfnms.f64\td22, d14, d23\n-\tvfma.f64\td22, d25, d1\n-\tvfma.f64\td22, d24, d29\n-\tvmul.f64\td22, d22, d19\n-\tvstr\td22, [sl]\n-\tble.w\t36b8 <__gridxc_gga_MOD_blypxc+0x950>\n-\tvldr\td21, [sp, #120]\t@ 0x78\n-\tvmul.f64\td15, d8, d15\n-\tvfms.f64\td21, d11, d27\n-\tvldr\td27, [sp, #144]\t@ 0x90\n-\tvldr\td22, [pc, #528]\t@ 35a0 <__gridxc_gga_MOD_blypxc+0x838>\n-\tvmul.f64\td11, d8, d11\n-\tvldr\td24, [sp, #112]\t@ 0x70\n-\tvmul.f64\td30, d20, d30\n-\tvstr\td27, [r8]\n-\tvmul.f64\td18, d16, d4\n-\tvldr\td27, [sp, #136]\t@ 0x88\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvldr\td2, [sp, #8]\n+\tvstr\td3, [r6]\n+\tvldr\td3, [sp, #96]\t@ 0x60\n+\tvmov.f64\td1, d5\n+\tvmul.f64\td5, d8, d11\n+\tvmul.f64\td2, d2, d2\n+\tvstr\td12, [sp, #152]\t@ 0x98\n+\tvmul.f64\td6, d3, d3\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvldr\td7, [sp, #80]\t@ 0x50\n+\tvmul.f64\td5, d5, d12\n+\tvstr\td2, [sp, #64]\t@ 0x40\n+\tvmul.f64\td4, d3, d3\n+\tvmov.f64\td2, d11\n+\tvdiv.f64\td3, d14, d10\n+\tvldr\td14, [sp]\n+\tvldr\td11, [pc, #888]\t@ 38f8 <__gridxc_gga_MOD_blypxc+0x860>\n+\tvmul.f64\td10, d8, d10\n+\tvmul.f64\td7, d7, d7\n+\tvstr\td4, [sp, #104]\t@ 0x68\n+\tvdiv.f64\td4, d0, d5\n+\tvmul.f64\td5, d14, d15\n+\tvmla.f64\td1, d9, d3\n+\tvstr\td3, [sp, #120]\t@ 0x78\n+\tvmov.f64\td9, #38\t@ 0x41300000 11.0\n+\tvmul.f64\td0, d4, d3\n+\tvmul.f64\td3, d14, d14\n+\tvmul.f64\td4, d6, d3\n+\tvmul.f64\td6, d5, d11\n+\tvstr\td0, [sp, #8]\n+\tvdiv.f64\td12, d6, d10\n+\tvstr\td4, [sp, #72]\t@ 0x48\n+\tvmul.f64\td4, d15, d15\n+\tvldr\td6, [pc, #828]\t@ 3900 <__gridxc_gga_MOD_blypxc+0x868>\n+\tvmov.f64\td10, d1\n+\tvmov.f64\td11, d6\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td10, [sp, #160]\t@ 0xa0\n+\tvmov.f64\td0, d7\n+\tvsub.f64\td7, d1, d9\n+\tvmov.f64\td1, #28\t@ 0x40e00000 7.0\n+\tvnmls.f64\td11, d10, d1\n+\tvmul.f64\td1, d7, d14\n+\tvmul.f64\td7, d7, d15\n+\tvstr\td0, [sp, #136]\t@ 0x88\n+\tvmov.f64\td14, d1\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n+\tvadd.f64\td0, d1, d0\n+\tvnmls.f64\td6, d10, d7\n+\tvldr\td1, [sp, #48]\t@ 0x30\n+\tvldr\td7, [sp, #24]\n+\tvstr\td11, [sp, #80]\t@ 0x50\n+\tvldr\td11, [sp, #32]\n+\tvmul.f64\td7, d7, d1\n+\tvldr\td1, [sp, #16]\n+\tvstr\td14, [sp, #128]\t@ 0x80\n+\tvldr\td10, [pc, #732]\t@ 3908 <__gridxc_gga_MOD_blypxc+0x870>\n+\tvstr\td6, [sp, #112]\t@ 0x70\n+\tvstr\td12, [sp, #144]\t@ 0x90\n+\tvldr\td12, [sp, #40]\t@ 0x28\n+\tvmla.f64\td7, d1, d12\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvmla.f64\td7, d11, d12\n+\tvldr\td11, [pc, #784]\t@ 3958 <__gridxc_gga_MOD_blypxc+0x8c0>\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [pc, #768]\t@ 3950 <__gridxc_gga_MOD_blypxc+0x8b8>\n+\tvmul.f64\td1, d5, d7\n+\tvmov.f64\td7, d6\n+\tvmla.f64\td7, d14, d13\n+\tvmla.f64\td4, d7, d1\n+\tvstr\td7, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td7, d5, d11\n+\tvldr\td12, [sp, #144]\t@ 0x90\n+\tvldr\td14, [sp, #8]\n+\tvmul.f64\td7, d7, d0\n+\tvmla.f64\td12, d7, d14\n+\tvldr\td7, [sp, #80]\t@ 0x50\n+\tvmul.f64\td7, d7, d1\n+\tvmla.f64\td7, d2, d10\n+\tvldr\td10, [sp, #88]\t@ 0x58\n+\tvldr\td2, [sp, #112]\t@ 0x70\n+\tvmla.f64\td2, d10, d13\n+\tvmov.f64\td6, d12\n+\tvmla.f64\td3, d2, d1\n+\tvstr\td2, [sp, #144]\t@ 0x90\n+\tvldr\td2, [pc, #624]\t@ 3910 <__gridxc_gga_MOD_blypxc+0x878>\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvmul.f64\td2, d14, d2\n+\tvmul.f64\td7, d7, d2\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td10, d3, d2\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvnmls.f64\td6, d1, d7\n+\tvmla.f64\td6, d4, d3\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvmla.f64\td6, d3, d10\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td6, [sl]\n+\tble.w\t3ae4 <__gridxc_gga_MOD_blypxc+0xa4c>\n+\tvldr\td14, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td0, d5, d0\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n \tcmp\tr7, #1\n-\tvdiv.f64\td0, d13, d11\n-\tldrd\tr2, r3, [sp, #216]\t@ 0xd8\n-\tvstr\td27, [r4, #16]\n-\tvmov.f64\td27, d21\n+\tvldr\td12, [pc, #512]\t@ 38e8 <__gridxc_gga_MOD_blypxc+0x850>\n+\tvstr\td14, [r8]\n+\tvldr\td14, [sp, #184]\t@ 0xb8\n+\tvmls.f64\td12, d6, d9\n+\tvldr\td9, [pc, #504]\t@ 38f0 <__gridxc_gga_MOD_blypxc+0x858>\n+\tvmul.f64\td3, d8, d6\n+\tvstr\td14, [r4, #16]\n+\tvldr\td14, [sp, #120]\t@ 0x78\n+\tvmla.f64\td12, d14, d9\n+\tvldr\td9, [sp, #152]\t@ 0x98\n+\tvmul.f64\td1, d8, d9\n+\tvldr\td9, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td6, d9, d13\n+\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td9, d9, 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<__gridxc_gga_MOD_blypxc+0x8b0>\n+\tvnmls.f64\td1, d11, d9\n+\tvmul.f64\td11, d3, d5\n+\tvldr\td3, [sp, #144]\t@ 0x90\n+\tvstr\td11, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td11, d3, d15\n+\tvsub.f64\td6, d13, d6\n+\tvmul.f64\td3, d1, d5\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvstr\td3, [sp, #144]\t@ 0x90\n+\tvldr\td3, [sp, #136]\t@ 0x88\n+\tvmla.f64\td3, d1, d14\n+\tvadd.f64\td14, d13, d13\n+\tvstr\td14, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td1, d3, d15\n+\tvldr\td3, [sp, #152]\t@ 0x98\n+\tvmla.f64\td3, d1, d0\n+\tvldr\td0, [pc, #376]\t@ 3958 <__gridxc_gga_MOD_blypxc+0x8c0>\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvmul.f64\td3, d3, d0\n+\tvldr\td0, [sp, #128]\t@ 0x80\n+\tvmla.f64\td1, d14, d0\n+\tvldr\td0, [sp, #144]\t@ 0x90\n+\tvmov.f64\td14, d3\n+\tvldr\td3, [pc, #300]\t@ 3928 <__gridxc_gga_MOD_blypxc+0x890>\n+\tvmla.f64\td0, d1, d15\n+\tvstr\td0, [sp, #128]\t@ 0x80\n+\tvldr\td0, [pc, #328]\t@ 3950 <__gridxc_gga_MOD_blypxc+0x8b8>\n+\tvmul.f64\td1, d15, d0\n+\tvldr\td0, [pc, #288]\t@ 3930 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#8]\n-\tvmul.f64\td22, d21, d26\n-\tvldr\td21, [pc, #460]\t@ 35a8 <__gridxc_gga_MOD_blypxc+0x840>\n-\tvmul.f64\td22, d22, d26\n-\tvfms.f64\td22, d31, d19\n-\tvldr\td31, [sp, #48]\t@ 0x30\n-\tvmul.f64\td22, d22, d21\n-\tvmul.f64\td21, d0, d21\n-\tvmul.f64\td21, d21, d5\n-\tvmul.f64\td27, d27, d21\n-\tvdiv.f64\td21, d13, d17\n-\tvdiv.f64\td11, d27, d5\n-\tvmul.f64\td30, d30, d27\n-\tvmov.f64\td27, d7\n-\tvfma.f64\td7, d19, d17\n-\tvfma.f64\td27, d19, d16\n-\tvstr\td30, [sp, #104]\t@ 0x68\n-\tvmul.f64\td24, d27, d22\n-\tvmul.f64\td27, d7, d22\n-\tvfms.f64\td24, d12, d15\n-\tvfms.f64\td27, d6, d15\n-\tvmul.f64\td7, d20, d24\n-\tvmov.f64\td15, d7\n-\tvstr\td7, [sp, #96]\t@ 0x60\n-\tvfma.f64\td15, d2, d16\n-\tvmul.f64\td2, d20, d27\n-\tvadd.f64\td27, d19, d19\n-\tvsub.f64\td21, d19, d21\n-\tvmov.f64\td7, d27\n-\tvmov.f64\td27, d9\n-\tvstr\td15, [sp, #80]\t@ 0x50\n-\tvfma.f64\td27, d7, d6\n-\tvldr\td15, [pc, #348]\t@ 35b0 <__gridxc_gga_MOD_blypxc+0x848>\n-\tvmov.f64\td6, d3\n-\tvstr\td7, [sp, #88]\t@ 0x58\n-\tvfma.f64\td6, d10, d15\n-\tvmov.f64\td24, d27\n-\tvmov.f64\td27, d2\n-\tvfma.f64\td27, d24, d16\n-\tvmul.f64\td24, d6, d16\n-\tvldr\td6, [pc, #268]\t@ 3580 <__gridxc_gga_MOD_blypxc+0x818>\n-\tvfma.f64\td30, d24, d5\n-\tvldr\td24, [pc, #316]\t@ 35b8 <__gridxc_gga_MOD_blypxc+0x850>\n-\tvmul.f64\td24, d8, d24\n-\tvstr\td27, [sp, #72]\t@ 0x48\n-\tvmov.f64\td8, d24\n-\tvfma.f64\td8, d31, d18\n-\tvldr\td18, [pc, #304]\t@ 35c0 <__gridxc_gga_MOD_blypxc+0x858>\n-\tvadd.f64\td31, d17, d17\n-\tvmul.f64\td18, d20, d18\n-\tvmul.f64\td20, d20, d19\n-\tvmul.f64\td7, d18, d22\n-\tvldr\td22, [pc, #292]\t@ 35c8 <__gridxc_gga_MOD_blypxc+0x860>\n-\tvmul.f64\td20, d20, d6\n-\tvldr\td6, [pc, #292]\t@ 35d0 <__gridxc_gga_MOD_blypxc+0x868>\n-\tvmul.f64\td22, d0, d22\n-\tvldr\td0, [sp, #24]\n-\tvadd.f64\td27, d7, d8\n-\tvmul.f64\td6, d5, d6\n-\tvmul.f64\td20, d20, d26\n-\tvmul.f64\td22, d22, d26\n-\tvldr\td26, [pc, #272]\t@ 35d8 <__gridxc_gga_MOD_blypxc+0x870>\n-\tvsub.f64\td18, d21, d22\n-\tvmul.f64\td18, d18, d20\n-\tvfms.f64\td18, d30, d26\n-\tvmul.f64\td30, d11, d23\n-\tvmov.f64\td26, d30\n-\tvfma.f64\td26, d27, d28\n-\tvldr\td27, [sp, #80]\t@ 0x50\n-\tvfma.f64\td31, d27, d4\n-\tvldr\td27, [sp, #72]\t@ 0x48\n-\tvfma.f64\td18, d14, d26\n-\tvmul.f64\td26, d11, d25\n-\tvmov.f64\td8, d26\n-\tvfma.f64\td8, d27, d6\n-\tvmul.f64\td27, d11, d29\n-\tvldr\td11, [sp, #56]\t@ 0x38\n-\tvfma.f64\td18, d8, d1\n-\tvmov.f64\td8, d27\n-\tvfma.f64\td8, d31, d28\n-\tvldr\td31, [sp, #16]\n-\tvfma.f64\td18, d11, d8\n-\tvldr\td8, [sp, #32]\n-\tvstr\td18, [r9]\n-\tvldr\td18, [sp]\n-\tvadd.f64\td18, d18, d18\n-\tvmul.f64\td18, d18, d25\n-\tvfma.f64\td18, d0, d23\n-\tvldr\td0, [sp, #8]\n-\tvstr\td18, [r5]\n-\tvadd.f64\td18, d0, d0\n-\tvmul.f64\td18, d18, d25\n-\tvfma.f64\td18, d8, d23\n-\tvstr\td18, [r5, #8]\n-\tvadd.f64\td18, d31, d31\n-\tvmul.f64\td18, d18, d25\n-\tvldr\td25, [sp, #40]\t@ 0x28\n-\tvfma.f64\td18, d25, d23\n-\tvstr\td18, [r5, #16]\n-\tbeq.w\t36b8 <__gridxc_gga_MOD_blypxc+0x950>\n-\tb.n\t35e0 <__gridxc_gga_MOD_blypxc+0x878>\n+\tvsub.f64\td1, d6, d5\n+\tvnmls.f64\td14, d1, d9\n+\tvmul.f64\td9, d8, d3\n+\tvmul.f64\td8, d12, d7\n+\tvmov.f64\td3, d9\n+\tvldr\td9, [sp, #96]\t@ 0x60\n+\tvmov.f64\td6, d14\n+\tvmov.f64\td14, d8\n+\tvmla.f64\td14, d0, d2\n+\tvldr\td0, [sp]\n+\tvadd.f64\td1, d0, d0\n+\tvmla.f64\td6, d14, d9\n+\tvldr\td9, [pc, #164]\t@ 3950 <__gridxc_gga_MOD_blypxc+0x8b8>\n+\tvmla.f64\td1, d11, d9\n+\tvmul.f64\td11, d12, d4\n+\tvldr\td9, [sp, #128]\t@ 0x80\n+\tvstr\td3, [sp, #128]\t@ 0x80\n+\tvmov.f64\td14, d11\n+\tvmla.f64\td14, d9, d3\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvmla.f64\td6, d14, d9\n+\tvmul.f64\td9, d12, d10\n+\tvldr\td12, [sp, #64]\t@ 0x40\n+\tvmov.f64\td14, d9\n+\tvmla.f64\td14, d1, d2\n+\tvmla.f64\td6, d14, d12\n+\tb.n\t3960 <__gridxc_gga_MOD_blypxc+0x8c8>\n \tnop\n \tnop.w\n \t.word\t0x3404ea4b\n \t.word\t0x3fd03611\n \t.word\t0x189374bc\n \t.word\t0x3fd65604\n-\t.word\t0x00000000\n-\t.word\t0xc0478000\n \t.word\t0xf73c0c20\n \t.word\t0x3fc92e1e\n-\t.word\t0x1c71c71c\n-\t.word\t0x3fbc71c7\n+\t.word\t0x00000000\n+\t.word\t0x40478000\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n \t.word\t0x8e4bb2b2\n \t.word\t0x3f7a971a\n \t.word\t0xaf9ebe9b\n \t.word\t0x3fbf2e59\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x55555555\n-\t.word\t0x400d5555\n+\t.word\t0x45989ed7\n+\t.word\t0x3f47a2c2\n \t.word\t0x55555555\n \t.word\t0x40055555\n \t.word\t0x38e38e39\n \t.word\t0x3fe8e38e\n \t.word\t0x7619f0fa\n \t.word\t0x3fbdc805\n-\t.word\t0x45989ed7\n-\t.word\t0x3f47a2c2\n+\t.word\t0x55555555\n+\t.word\t0x400d5555\n+\t.word\t0x1c71c71c\n+\t.word\t0x3fbc71c7\n \t.word\t0xa8684e26\n \t.word\t0x3fce4c5a\n-\tvdiv.f64\td18, d13, d16\n-\tvfma.f64\td10, d3, d15\n-\tvldr\td3, [sp, #88]\t@ 0x58\n-\tvadd.f64\td16, d16, d16\n-\tvldr\td21, [sp, #64]\t@ 0x40\n-\tvldr\td15, [sp, #96]\t@ 0x60\n-\tvfma.f64\td9, d3, d12\n-\tvldr\td31, [sp, #48]\t@ 0x30\n-\tvfma.f64\td2, d21, d17\n-\tvldr\td8, [sp, #32]\n-\tvldr\td3, [sp, #176]\t@ 0xb0\n+\tvldr\td12, [sp, #16]\n+\tvadd.f64\td0, d12, d12\n+\tvldr\td12, [sp, #40]\t@ 0x28\n+\tvmul.f64\td1, d12, d7\n+\tvmla.f64\td1, d0, d4\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvstr\td6, [r9]\n+\tvldr\td6, [sp, #24]\n+\tvadd.f64\td3, d6, d6\n+\tvldr\td6, [sp, #32]\n+\tvstr\td1, [r5]\n+\tvadd.f64\td6, d6, d6\n+\tvmul.f64\td1, d0, d7\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvmla.f64\td1, d3, d4\n+\tvmul.f64\td3, d0, d7\n+\tvmla.f64\td3, d6, d4\n+\tvstr\td1, [r5, #8]\n+\tvstr\td3, [r5, #16]\n+\tbeq.w\t3ae4 <__gridxc_gga_MOD_blypxc+0xa4c>\n+\tvldr\td12, [sp, #136]\t@ 0x88\n+\tvldr\td14, [pc, #-112]\t@ 3948 <__gridxc_gga_MOD_blypxc+0x8b0>\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvldr\td0, [sp]\n+\tvmla.f64\td6, d12, d14\n+\tvldr\td14, [sp, #168]\t@ 0xa8\n+\tvldr\td12, [sp, #88]\t@ 0x58\n+\tvldr\td4, [sp, #200]\t@ 0xc8\n+\tvldr\td1, [sp, #144]\t@ 0x90\n+\tvmla.f64\td1, d4, d0\n+\tvldr\td4, [sp, #192]\t@ 0xc0\n+\tvmov.f64\td3, d6\n+\tvldr\td6, [sp, #112]\t@ 0x70\n+\tvmla.f64\td6, d14, d12\n+\tvldr\td14, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td3, d3, d0\n+\tvstr\td14, [r8, #8]\n+\tvmov.f64\td12, d1\n+\tvldr\td14, [sp, #216]\t@ 0xd8\n+\tvmov.f64\td1, d0\n+\tvstr\td14, [r4, #24]\n+\tvmla.f64\td4, d6, d0\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n \tvldr\td0, [sp, #8]\n-\tvmul.f64\td21, d10, d17\n-\tvstr\td3, [r8, #8]\n-\tvldr\td3, [sp, #160]\t@ 0xa0\n-\tvfma.f64\td15, d9, d17\n-\tvmul.f64\td17, d17, d4\n-\tvfma.f64\td16, d2, d4\n-\tvldr\td2, [sp, #24]\n-\tvstr\td3, [r4, #24]\n-\tvldr\td3, [sp, #152]\t@ 0x98\n-\tvfma.f64\td24, d31, d17\n-\tvadd.f64\td17, d25, d25\n-\tvldr\td31, [sp, #16]\n-\tvstr\td3, [r4, #32]\n-\tvldr\td3, [sp, #168]\t@ 0xa8\n-\tvfma.f64\td27, d15, d6\n-\tvmul.f64\td17, d17, d29\n-\tvfma.f64\td26, d16, d28\n-\tvfma.f64\td17, d31, d23\n-\tvstr\td3, [r4, #40]\t@ 0x28\n-\tvadd.f64\td7, d7, d24\n-\tvfma.f64\td30, d7, d28\n-\tvsub.f64\td18, d19, d18\n-\tvadd.f64\td19, d2, d2\n-\tvstr\td17, [r5, #40]\t@ 0x28\n-\tvsub.f64\td18, d18, d22\n-\tvldr\td22, [pc, #-160]\t@ 35d8 <__gridxc_gga_MOD_blypxc+0x870>\n-\tvmul.f64\td19, d19, d29\n-\tvmul.f64\td18, d18, d20\n-\tvldr\td20, [sp, #104]\t@ 0x68\n-\tvfma.f64\td20, d21, d5\n-\tvldr\td21, [sp]\n-\tvfma.f64\td19, d21, d23\n-\tvfms.f64\td18, d20, d22\n-\tvadd.f64\td20, d8, d8\n-\tvstr\td19, [r5, #24]\n-\tvfma.f64\td18, d14, d30\n-\tvmul.f64\td20, d20, d29\n-\tvfma.f64\td20, d0, d23\n-\tvfma.f64\td18, d11, d27\n-\tvfma.f64\td18, d26, d1\n-\tvstr\td20, [r5, #32]\n-\tvstr\td18, [r9, #8]\n-\tldr\tr2, [pc, #372]\t@ (3830 <__gridxc_gga_MOD_blypxc+0xac8>)\n-\tldr\tr3, [pc, #376]\t@ (3834 <__gridxc_gga_MOD_blypxc+0xacc>)\n+\tvdiv.f64\td6, d6, d15\n+\tvldr\td14, [sp, #208]\t@ 0xd0\n+\tvstr\td14, [r4, #32]\n+\tvldr\td14, [sp, #224]\t@ 0xe0\n+\tvstr\td14, [r4, #40]\t@ 0x28\n+\tvldr\td14, [sp, #128]\t@ 0x80\n+\tvmla.f64\td9, d4, d14\n+\tvldr\td14, [sp, #120]\t@ 0x78\n+\tvldr\td4, [pc, #-228]\t@ 3950 <__gridxc_gga_MOD_blypxc+0x8b8>\n+\tvsub.f64\td6, d13, d6\n+\tvldr\td13, [sp, #152]\t@ 0x98\n+\tvmla.f64\td13, d3, d0\n+\tvldr\td3, [sp, #80]\t@ 0x50\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvsub.f64\td5, d6, d5\n+\tvmov.f64\td6, d13\n+\tvldr\td13, [pc, #-252]\t@ 3958 <__gridxc_gga_MOD_blypxc+0x8c0>\n+\tvmul.f64\td6, d6, d13\n+\tvldr\td13, [sp, #176]\t@ 0xb0\n+\tvnmls.f64\td6, d5, d14\n+\tvmul.f64\td14, d1, d4\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvmla.f64\td13, d14, d3\n+\tvmov.f64\td5, d13\n+\tvldr\td13, [sp, #184]\t@ 0xb8\n+\tvadd.f64\td5, d5, d13\n+\tvmla.f64\td8, d5, d2\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvmla.f64\td6, d8, d1\n+\tvmla.f64\td6, d9, d5\n+\tvadd.f64\td5, d15, d15\n+\tvmla.f64\td5, d12, d4\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvadd.f64\td4, d0, d0\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td12, [sp, #16]\n+\tvmla.f64\td11, d5, d2\n+\tvldr\td5, [sp, #40]\t@ 0x28\n+\tvmul.f64\td2, d12, d7\n+\tvadd.f64\td3, d5, d5\n+\tvadd.f64\td5, d0, d0\n+\tvmla.f64\td2, d3, d10\n+\tvmla.f64\td6, d11, d9\n+\tvstr\td6, [r9, #8]\n+\tvldr\td6, [sp, #24]\n+\tvldr\td11, [sp, #32]\n+\tvstr\td2, [r5, #24]\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td7, d11, d7\n+\tvmla.f64\td6, d4, d10\n+\tvmla.f64\td7, d5, d10\n+\tvstr\td6, [r5, #32]\n+\tvstr\td7, [r5, #40]\t@ 0x28\n+\tldr\tr2, [pc, #368]\t@ (3c58 <__gridxc_gga_MOD_blypxc+0xbc0>)\n+\tldr\tr3, [pc, #372]\t@ (3c5c <__gridxc_gga_MOD_blypxc+0xbc4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr3, [sp, #372]\t@ 0x174\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t381e <__gridxc_gga_MOD_blypxc+0xab6>\n-\tadd\tsp, #324\t@ 0x144\n+\tbne.w\t3c44 <__gridxc_gga_MOD_blypxc+0xbac>\n+\tadd\tsp, #380\t@ 0x17c\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td11, [sp, #192]\t@ 0xc0\n-\tvcmpe.f64\td11, d22\n+\tvldr\td9, [sp, #248]\t@ 0xf8\n+\tvcmpe.f64\td9, d13\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t37c2 <__gridxc_gga_MOD_blypxc+0xa5a>\n-\tvmov.f64\td0, d17\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #64]\t@ 0x40\n+\tbpl.n\t3bda <__gridxc_gga_MOD_blypxc+0xb42>\n+\tvldr\td11, [sp]\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #64]\t@ 0x40\n \tvmov.f64\td10, d0\n-\tvmov.f64\td0, d16\n+\tvstr\td0, [sp, #96]\t@ 0x60\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvldr\td21, [pc, #284]\t@ 3828 <__gridxc_gga_MOD_blypxc+0xac0>\n-\tvmov.f64\td9, d0\n-\tvdiv.f64\td19, d20, d8\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvmov.f64\td14, d21\n-\tvmul.f64\td22, d17, d21\n-\tvmul.f64\td21, d0, d21\n-\tvmul.f64\td21, d21, d16\n-\tvfma.f64\td21, d10, d22\n-\tvmul.f64\td18, d19, d19\n-\tvstr\td18, [sp, #128]\t@ 0x80\n-\tvmul.f64\td18, d19, d21\n-\tvstr\td18, [sp, #104]\t@ 0x68\n-\tvmov.i64\td21, #0x0000000000000000\n-\tvmov.f64\td22, d21\n-\tvstr\td21, [sp, #136]\t@ 0x88\n-\tvstr\td21, [sp, #144]\t@ 0x90\n-\tb.n\t30a4 <__gridxc_gga_MOD_blypxc+0x33c>\n-\tvmov.i64\td18, #0x0000000000000000\n-\tvstr\td18, [sp, #160]\t@ 0xa0\n-\tvstr\td18, [sp, #152]\t@ 0x98\n-\tvstr\td18, [sp, #168]\t@ 0xa8\n-\tvstr\td18, [sp, #176]\t@ 0xb0\n-\tb.n\t31e0 <__gridxc_gga_MOD_blypxc+0x478>\n-\tvmov.f64\td0, d17\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #64]\t@ 0x40\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td5, [pc, #276]\t@ 3c48 <__gridxc_gga_MOD_blypxc+0xbb0>\n+\tvmov.f64\td7, d0\n+\tvdiv.f64\td13, d6, d8\n+\tvmul.f64\td6, d0, d5\n+\tvmul.f64\td4, d11, d5\n+\tvstr\td5, [sp, #80]\t@ 0x50\n+\tvmul.f64\td6, d6, d15\n+\tvmla.f64\td6, d4, d10\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td6, [sp, #88]\t@ 0x58\n+\tvmul.f64\td6, d13, d13\n+\tvstr\td6, [sp, #176]\t@ 0xb0\n+\tvldr\td5, [pc, #236]\t@ 3c50 <__gridxc_gga_MOD_blypxc+0xbb8>\n+\tvmov.f64\td3, d5\n+\tvstr\td5, [sp, #184]\t@ 0xb8\n+\tvstr\td5, [sp, #192]\t@ 0xc0\n+\tb.n\t33ce <__gridxc_gga_MOD_blypxc+0x336>\n+\tvldr\td6, [pc, #216]\t@ 3c50 <__gridxc_gga_MOD_blypxc+0xbb8>\n+\tvstr\td6, [sp, #216]\t@ 0xd8\n+\tvstr\td6, [sp, #208]\t@ 0xd0\n+\tvstr\td6, [sp, #224]\t@ 0xe0\n+\tvstr\td6, [sp, #232]\t@ 0xe8\n+\tb.n\t34f0 <__gridxc_gga_MOD_blypxc+0x458>\n+\tvdiv.f64\td13, d12, d8\n+\tvldr\td0, [sp]\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvmov.f64\td10, d0\n-\tvmov.f64\td14, d13\n-\tvmov.f64\td0, d16\n+\tvmov.f64\td14, d0\n+\tvstr\td0, [sp, #96]\t@ 0x60\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvdiv.f64\td19, d9, d8\n-\tvmul.f64\td13, d0, d13\n-\tvldr\td16, [sp, #64]\t@ 0x40\n-\tvmov.f64\td9, d0\n-\tvmul.f64\td21, d15, d17\n-\tvmul.f64\td13, d13, d16\n-\tvfma.f64\td13, d10, d21\n-\tvmul.f64\td18, d19, d19\n-\tvstr\td18, [sp, #128]\t@ 0x80\n-\tvmul.f64\td18, d19, d13\n-\tvstr\td18, [sp, #104]\t@ 0x68\n-\tb.w\t2fbc <__gridxc_gga_MOD_blypxc+0x254>\n-\tvldr\td15, [pc, #100]\t@ 3828 <__gridxc_gga_MOD_blypxc+0xac0>\n-\tb.w\t2f00 <__gridxc_gga_MOD_blypxc+0x198>\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r2]\n-\tvldr\td21, [r2, #8]\n-\tvmul.f64\td16, d8, d23\n-\tvldr\td20, [r2, #16]\n-\tvmul.f64\td22, d22, d23\n-\tvmov.f64\td8, d17\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td20, d20, d23\n-\tvmaxnm.f64\td16, d16, d19\n-\tvstr\td22, [sp, #264]\t@ 0x108\n-\tvstr\td22, [sp, #288]\t@ 0x120\n-\tvstr\td21, [sp, #272]\t@ 0x110\n-\tvmov.f64\td17, d16\n-\tvmov.f64\td12, d16\n-\tvstr\td21, [sp, #296]\t@ 0x128\n-\tvstr\td20, [sp, #280]\t@ 0x118\n-\tvstr\td20, [sp, #304]\t@ 0x130\n-\tvstr\td16, [sp, #184]\t@ 0xb8\n-\tvstr\td16, [sp, #192]\t@ 0xc0\n-\tb.w\t2e14 <__gridxc_gga_MOD_blypxc+0xac>\n+\tvldr\td5, [sp]\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvmov.f64\td7, d0\n+\tvstr\td11, [sp, #80]\t@ 0x50\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td5, d0, d11\n+\tvmul.f64\td6, d6, d14\n+\tvmla.f64\td6, d5, d15\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td6, [sp, #88]\t@ 0x58\n+\tvmul.f64\td6, d13, d13\n+\tvstr\td6, [sp, #176]\t@ 0xb0\n+\tb.w\t330a <__gridxc_gga_MOD_blypxc+0x272>\n+\tvldr\td7, [pc, #108]\t@ 3c48 <__gridxc_gga_MOD_blypxc+0xbb0>\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tb.w\t325a <__gridxc_gga_MOD_blypxc+0x1c2>\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [r2]\n+\tvldr\td5, [r2, #8]\n+\tvmul.f64\td15, d8, d3\n+\tvldr\td6, [r2, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvldr\td8, [sp]\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvcmpe.f64\td15, d7\n+\tvstr\td4, [sp, #320]\t@ 0x140\n+\tvstr\td4, [sp, #344]\t@ 0x158\n+\tvstr\td5, [sp, #328]\t@ 0x148\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [sp, #352]\t@ 0x160\n+\tvstr\td6, [sp, #336]\t@ 0x150\n+\tvstr\td6, [sp, #360]\t@ 0x168\n+\tit\tlt\n+\tvmovlt.f64\td15, d7\n+\tvmov.f64\td10, d15\n+\tvstr\td15, [sp, #240]\t@ 0xf0\n+\tvstr\td15, [sp, #248]\t@ 0xf8\n+\tvstr\td15, [sp]\n+\tb.w\t316a <__gridxc_gga_MOD_blypxc+0xd2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\tnop.w\n \t.word\t0xe8b6951e\n \t.word\t0xbfedc6dd\n-\t.word\t0x00000170\n+\t...\n+\t.word\t0x0000016c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00003838 <__gridxc_gga_MOD_pw91xc>:\n+00003c60 <__gridxc_gga_MOD_pw91xc>:\n __gridxc_gga_MOD_pw91xc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3312]\t@ 0xcf0\n-\tldr.w\tr4, [pc, #1280]\t@ 3d50 <__gridxc_gga_MOD_pw91xc+0x518>\n+\tstr.w\tr0, [ip, #3304]\t@ 0xce8\n+\tldr.w\tr4, [pc, #1224]\t@ 4140 <__gridxc_gga_MOD_pw91xc+0x4e0>\n \tmov\tr8, r1\n-\tldr.w\tr1, [pc, #1280]\t@ 3d54 <__gridxc_gga_MOD_pw91xc+0x51c>\n-\tsub.w\tsp, sp, #684\t@ 0x2ac\n+\tldr.w\tr1, [pc, #1224]\t@ 4144 <__gridxc_gga_MOD_pw91xc+0x4e4>\n+\tsub.w\tsp, sp, #692\t@ 0x2b4\n \tadd\tr4, pc\n-\tvldr\td16, [r2]\n-\tldrd\tsl, fp, [sp, #800]\t@ 0x320\n+\tvldr\td7, [r2]\n+\tldrd\tsl, fp, [sp, #808]\t@ 0x328\n \tldr\tr1, [r4, r1]\n \tldr\tr1, [r1, #0]\n-\tstr\tr1, [sp, #676]\t@ 0x2a4\n+\tstr\tr1, [sp, #684]\t@ 0x2ac\n \tmov.w\tr1, #0\n-\tldr\tr1, [sp, #784]\t@ 0x310\n-\tstr\tr0, [sp, #112]\t@ 0x70\n-\tldr\tr0, [sp, #788]\t@ 0x314\n-\tstr\tr1, [sp, #176]\t@ 0xb0\n-\tstr\tr0, [sp, #180]\t@ 0xb4\n+\tldr\tr1, [sp, #792]\t@ 0x318\n+\tstr\tr0, [sp, #104]\t@ 0x68\n+\tldr\tr0, [sp, #796]\t@ 0x31c\n+\tstr\tr1, [sp, #232]\t@ 0xe8\n+\tstr\tr0, [sp, #236]\t@ 0xec\n \tldr.w\tr1, [r8]\n-\tldr\tr0, [sp, #792]\t@ 0x318\n-\tstr\tr0, [sp, #416]\t@ 0x1a0\n+\tldr\tr0, [sp, #800]\t@ 0x320\n+\tstr\tr0, [sp, #424]\t@ 0x1a8\n \tcmp\tr1, #1\n-\tldr\tr0, [sp, #796]\t@ 0x31c\n-\tstr\tr0, [sp, #420]\t@ 0x1a4\n-\tbeq.w\t4286 <__gridxc_gga_MOD_pw91xc+0xa4e>\n-\tvldr\td23, [r2, #8]\n-\tvldr\td22, [r3]\n-\tvldr\td20, [r3, #8]\n-\tvldr\td19, [r3, #32]\n-\tvadd.f64\td9, d23, d16\n-\tvldr\td17, [r3, #16]\n-\tvldr\td21, [r3, #24]\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvadd.f64\td24, d19, d20\n-\tvstr\td16, [sp, #456]\t@ 0x1c8\n-\tvadd.f64\td25, d21, d22\n-\tvldr\td26, [pc, #984]\t@ 3c90 <__gridxc_gga_MOD_pw91xc+0x458>\n-\tvadd.f64\td16, d17, d18\n-\tvstr\td23, [sp, #464]\t@ 0x1d0\n-\tvstr\td24, [sp, #560]\t@ 0x230\n-\tvmov.f64\td23, d22\n-\tvstr\td17, [sp, #640]\t@ 0x280\n-\tvmaxnm.f64\td9, d9, d26\n-\tvmov.f64\td17, d20\n-\tvmov.f64\td24, d25\n-\tvstr\td16, [sp, #152]\t@ 0x98\n-\tvmov.f64\td16, d19\n-\tvstr\td22, [sp, #624]\t@ 0x270\n-\tvstr\td21, [sp, #648]\t@ 0x288\n-\tvstr\td25, [sp, #552]\t@ 0x228\n-\tvstr\td20, [sp, #632]\t@ 0x278\n-\tvstr\td19, [sp, #656]\t@ 0x290\n-\tvldr\td20, [sp, #560]\t@ 0x230\n-\tvmul.f64\td16, d16, d16\n-\tvldr\td22, [sp, #648]\t@ 0x288\n-\tvmul.f64\td17, d17, d17\n-\tvfma.f64\td17, d23, d23\n-\tvldr\td21, [sp, #640]\t@ 0x280\n-\tvstr\td20, [sp, #280]\t@ 0x118\n-\tvmul.f64\td20, d20, d20\n-\tvfma.f64\td20, d24, d24\n-\tvfma.f64\td16, d22, d22\n-\tvldr\td22, [sp, #152]\t@ 0x98\n+\tldr\tr0, [sp, #804]\t@ 0x324\n+\tstr\tr0, [sp, #428]\t@ 0x1ac\n+\tbeq.w\t47b6 <__gridxc_gga_MOD_pw91xc+0xb56>\n+\tvldr\td1, [r2, #8]\n+\tvldr\td6, [pc, #984]\t@ 4090 <__gridxc_gga_MOD_pw91xc+0x430>\n+\tvldr\td5, [r3]\n+\tvadd.f64\td15, d1, d7\n+\tvldr\td2, [r3, #24]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #32]\n+\tvadd.f64\td0, d2, d5\n+\tvstr\td7, [sp, #464]\t@ 0x1d0\n+\tvcmpe.f64\td15, d6\n+\tvldr\td7, [r3, #16]\n+\tvstr\td5, [sp, #632]\t@ 0x278\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvstr\td1, [sp, #472]\t@ 0x1d8\n+\tvadd.f64\td1, d4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td4, [sp, #664]\t@ 0x298\n+\tvadd.f64\td4, d7, d5\n+\tvstr\td0, [sp, #560]\t@ 0x230\n+\tvstr\td2, [sp, #656]\t@ 0x290\n+\tvstr\td1, [sp, #568]\t@ 0x238\n+\tvstr\td3, [sp, #640]\t@ 0x280\n+\tit\tlt\n+\tvmovlt.f64\td15, d6\n+\tvmov.f64\td1, d4\n+\tvmov.f64\td6, d3\n+\tvstr\td4, [sp, #200]\t@ 0xc8\n+\tvstr\td7, [sp, #648]\t@ 0x288\n+\tvldr\td3, [sp, #568]\t@ 0x238\n+\tvmul.f64\td6, d6, d6\n+\tvldr\td4, [sp, #632]\t@ 0x278\n \tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n-\tvstr\td18, [sp, #664]\t@ 0x298\n-\tvfma.f64\td17, d21, d21\n-\tvdiv.f64\td12, d8, d9\n-\tvldr\td19, [pc, #860]\t@ 3c90 <__gridxc_gga_MOD_pw91xc+0x458>\n-\tvfma.f64\td16, d18, d18\n-\tldr.w\tr0, [pc, #1052]\t@ 3d58 <__gridxc_gga_MOD_pw91xc+0x520>\n-\tadd\tr4, sp, #456\t@ 0x1c8\n-\tadd\tr3, sp, #520\t@ 0x208\n+\tvldr\td2, [sp, #560]\t@ 0x230\n+\tadd\tr4, sp, #464\t@ 0x1d0\n+\tvldr\td7, [sp, #664]\t@ 0x298\n+\tadd\tr3, sp, #528\t@ 0x210\n+\tvmla.f64\td6, d4, d4\n+\tvstr\td3, [sp, #304]\t@ 0x130\n+\tvmul.f64\td4, d3, d3\n+\tvldr\td3, [sp, #656]\t@ 0x290\n+\tvmla.f64\td4, d2, d2\n+\tvmul.f64\td7, d7, d7\n+\tvstr\td5, [sp, #672]\t@ 0x2a0\n+\tadd\tr2, sp, #448\t@ 0x1c0\n+\tvmla.f64\td7, d3, d3\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvdiv.f64\td9, d8, d15\n+\tvldr\td2, [pc, #808]\t@ 4090 <__gridxc_gga_MOD_pw91xc+0x430>\n+\tvmla.f64\td4, d1, d1\n+\tldr\tr0, [pc, #984]\t@ (4148 <__gridxc_gga_MOD_pw91xc+0x4e8>)\n+\tmov\tr1, r4\n+\tvstr\td1, [sp, #576]\t@ 0x240\n+\tvmla.f64\td7, d5, d5\n \tadd\tr0, pc\n-\tadd\tr2, sp, #440\t@ 0x1b8\n \tadds\tr0, #4\n-\tmov\tr1, r4\n-\tvmov.f64\td18, d20\n-\tvstr\td24, [sp, #272]\t@ 0x110\n-\tvfma.f64\td18, d22, d22\n-\tvstr\td22, [sp, #568]\t@ 0x238\n-\tvsqrt.f64\td20, d17\n-\tvstr\td19, [sp, #24]\n-\tvmov.f64\td11, #96\t@ 0x3f000000 0.5\n-\tadd.w\tr9, sp, #504\t@ 0x1f8\n-\tvsqrt.f64\td17, d16\n-\tadd\tr6, sp, #624\t@ 0x270\n-\tadd\tr5, sp, #576\t@ 0x240\n-\tadd\tr7, sp, #472\t@ 0x1d8\n-\tvsqrt.f64\td16, d18\n-\tvstr\td20, [sp, #504]\t@ 0x1f8\n-\tvstr\td17, [sp, #512]\t@ 0x200\n-\tvmaxnm.f64\td13, d16, d19\n-\tvstr\td13, [sp, #288]\t@ 0x120\n+\tvstr\td2, [sp, #24]\n+\tadd.w\tr9, sp, #512\t@ 0x200\n+\tadd\tr6, sp, #632\t@ 0x278\n+\tadd\tr5, sp, #584\t@ 0x248\n+\tadd\tr7, sp, #480\t@ 0x1e0\n+\tvsqrt.f64\td5, d4\n+\tvsqrt.f64\td4, d7\n+\tvldr\td7, [sp, #648]\t@ 0x288\n+\tvmla.f64\td6, d7, d7\n+\tvsqrt.f64\td7, d6\n+\tvcmpe.f64\td5, d2\n+\tvstr\td4, [sp, #520]\t@ 0x208\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td10, d2\n+\tvmovge.f64\td10, d5\n+\tvstr\td7, [sp, #512]\t@ 0x200\n+\tvstr\td10, [sp, #312]\t@ 0x138\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td0, [pc, #776]\t@ 3c98 <__gridxc_gga_MOD_pw91xc+0x460>\n-\tvstr\td12, [sp, #96]\t@ 0x60\n-\tvmul.f64\td0, d12, d0\n+\tvldr\td0, [pc, #724]\t@ 4098 <__gridxc_gga_MOD_pw91xc+0x438>\n+\tvstr\td9, [sp, #88]\t@ 0x58\n+\tvmul.f64\td0, d9, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [pc, #768]\t@ 3ca0 <__gridxc_gga_MOD_pw91xc+0x468>\n-\tvmov.f64\td10, d0\n-\tvmul.f64\td0, d9, d16\n+\tvldr\td7, [pc, #716]\t@ 40a0 <__gridxc_gga_MOD_pw91xc+0x440>\n+\tvmov.f64\td11, d0\n+\tvstr\td0, [sp, #136]\t@ 0x88\n+\tvmul.f64\td0, d15, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [pc, #760]\t@ 3ca8 <__gridxc_gga_MOD_pw91xc+0x470>\n-\tvldr\td20, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td18, d13, d11\n-\tvldr\td16, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td17, d0, d17\n-\tvldr\td22, [pc, #748]\t@ 3cb0 <__gridxc_gga_MOD_pw91xc+0x478>\n-\tvldr\td21, [pc, #752]\t@ 3cb8 <__gridxc_gga_MOD_pw91xc+0x480>\n-\tvsub.f64\td16, d16, d20\n-\tvmul.f64\td20, d9, d0\n-\tvstr\td0, [sp, #296]\t@ 0x128\n-\tvsqrt.f64\td17, d17\n-\tvdiv.f64\td14, d18, d20\n-\tvmul.f64\td16, d16, d12\n-\tvmaxnm.f64\td16, d16, d22\n-\tvminnm.f64\td16, d16, d21\n-\tvadd.f64\td19, d16, d8\n-\tvsub.f64\td12, d8, d16\n-\tvmov.f64\td0, d19\n-\tvstr\td19, [sp, #432]\t@ 0x1b0\n-\tvstr\td12, [sp, #312]\t@ 0x138\n-\tvmul.f64\td16, d9, d17\n-\tvstr\td17, [sp, #304]\t@ 0x130\n-\tvstr\td14, [sp, #128]\t@ 0x80\n-\tvdiv.f64\td15, d18, d16\n-\tvstr\td15, [sp, #136]\t@ 0x88\n+\tvldr\td6, [sp, #472]\t@ 0x1d8\n+\tvldr\td7, [sp, #464]\t@ 0x1d0\n+\tvmul.f64\td5, d15, d0\n+\tvstr\td0, [sp, #320]\t@ 0x140\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [pc, #684]\t@ 40a8 <__gridxc_gga_MOD_pw91xc+0x448>\n+\tvmul.f64\td6, d0, d6\n+\tvmul.f64\td7, d7, d9\n+\tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n+\tvsqrt.f64\td4, d6\n+\tvldr\td6, [pc, #672]\t@ 40b0 <__gridxc_gga_MOD_pw91xc+0x450>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvldr\td6, [pc, #660]\t@ 40b8 <__gridxc_gga_MOD_pw91xc+0x458>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvmul.f64\td6, d10, d9\n+\tvsub.f64\td10, d8, d7\n+\tvstr\td4, [sp, #328]\t@ 0x148\n+\tvdiv.f64\td14, d6, d5\n+\tvadd.f64\td5, d7, d8\n+\tvmul.f64\td7, d15, d4\n+\tvstr\td10, [sp, #344]\t@ 0x158\n+\tvmov.f64\td0, d5\n+\tvstr\td5, [sp, #440]\t@ 0x1b8\n+\tvdiv.f64\td7, d6, d7\n+\tvstr\td14, [sp, #336]\t@ 0x150\n+\tvstr\td7, [sp, #176]\t@ 0xb0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, d0\n-\tvmov.f64\td0, d12\n-\tvmov.f64\td13, d16\n-\tvstr\td16, [sp, #320]\t@ 0x140\n+\tvmov.f64\td13, d0\n+\tvstr\td0, [sp, #352]\t@ 0x160\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td16, d0, d0\n-\tvldr\td12, [sp, #440]\t@ 0x1b8\n-\tvldr\td17, [pc, #652]\t@ 3cc0 <__gridxc_gga_MOD_pw91xc+0x488>\n-\tvfma.f64\td16, d13, d13\n-\tvstr\td0, [sp, #352]\t@ 0x160\n-\tvstr\td12, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td17, d12, d17\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td16, d16, d11\n-\tvmul.f64\td11, d16, d16\n-\tvmul.f64\td13, d16, d11\n-\tvdiv.f64\td16, d17, d13\n-\tvstr\td13, [sp, #328]\t@ 0x148\n-\tvneg.f64\td0, d16\n-\tvstr\td16, [sp, #336]\t@ 0x150\n+\tvmul.f64\td6, d0, d0\n+\tvldr\td12, [sp, #448]\t@ 0x1c0\n+\tvmla.f64\td6, d13, d13\n+\tvldr\td7, [pc, #572]\t@ 40c0 <__gridxc_gga_MOD_pw91xc+0x460>\n+\tvstr\td0, [sp, #384]\t@ 0x180\n+\tvstr\td12, [sp, #144]\t@ 0x90\n+\tvmul.f64\td7, d12, d7\n+\tvmul.f64\td9, d6, d9\n+\tvstr\td6, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td10, d9, d9\n+\tvmul.f64\td13, d9, d10\n+\tvdiv.f64\td6, d7, d13\n+\tvstr\td13, [sp, #360]\t@ 0x168\n+\tvneg.f64\td0, d6\n+\tvstr\td6, [sp, #368]\t@ 0x170\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td16, d0, d8\n-\tvldr\td17, [pc, #600]\t@ 3cc8 <__gridxc_gga_MOD_pw91xc+0x490>\n-\tvmul.f64\td22, d14, d14\n-\tvstr\td0, [sp, #344]\t@ 0x158\n-\tvmul.f64\td18, d10, d10\n-\tvldr\td0, [pc, #592]\t@ 3cd0 <__gridxc_gga_MOD_pw91xc+0x498>\n-\tvmul.f64\td20, d11, d11\n-\tvdiv.f64\td29, d17, d16\n-\tvldr\td16, [pc, #588]\t@ 3cd8 <__gridxc_gga_MOD_pw91xc+0x4a0>\n-\tvldr\td17, [pc, #592]\t@ 3ce0 <__gridxc_gga_MOD_pw91xc+0x4a8>\n-\tvmov.f64\td11, d8\n-\tvmul.f64\td0, d22, d0\n-\tvmov.f64\td19, d18\n-\tvfma.f64\td17, d18, d16\n-\tvstr\td20, [sp, #256]\t@ 0x100\n-\tvstr\td18, [sp, #392]\t@ 0x188\n-\tvmul.f64\td28, d15, d15\n-\tvldr\td18, [pc, #568]\t@ 3ce8 <__gridxc_gga_MOD_pw91xc+0x4b0>\n-\tvnmul.f64\td0, d20, d0\n-\tvldr\td20, [pc, #568]\t@ 3cf0 <__gridxc_gga_MOD_pw91xc+0x4b8>\n-\tvldr\td16, [pc, #572]\t@ 3cf8 <__gridxc_gga_MOD_pw91xc+0x4c0>\n-\tvmul.f64\td21, d28, d28\n-\tvstr\td28, [sp, #16]\n-\tvfma.f64\td11, d19, d20\n-\tvstr\td22, [sp, #248]\t@ 0xf8\n-\tvstr\td21, [sp, #240]\t@ 0xf0\n-\tvfma.f64\td11, d10, d17\n-\tvldr\td17, [pc, #552]\t@ 3d00 <__gridxc_gga_MOD_pw91xc+0x4c8>\n-\tvfma.f64\td17, d10, d18\n-\tvldr\td18, [pc, #552]\t@ 3d08 <__gridxc_gga_MOD_pw91xc+0x4d0>\n-\tvfma.f64\td17, d19, d18\n-\tvmov.f64\td14, d17\n-\tvstr\td17, [sp, #368]\t@ 0x170\n-\tvmov.f64\td17, d28\n-\tvfma.f64\td17, d21, d29\n-\tvstr\td29, [sp, #8]\n-\tvmov.f64\td18, d17\n-\tvmul.f64\td16, d17, d16\n-\tvstr\td17, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td17, d8\n-\tvfma.f64\td17, d29, d18\n-\tvdiv.f64\td17, d8, d17\n-\tvmul.f64\td15, d16, d17\n-\tvstr\td17, [sp, #400]\t@ 0x190\n-\tvstr\td15, [sp, #360]\t@ 0x168\n+\tvldr\td7, [sp, #176]\t@ 0xb0\n+\tvldr\td6, [pc, #524]\t@ 40c8 <__gridxc_gga_MOD_pw91xc+0x468>\n+\tvmul.f64\td3, d14, d14\n+\tvstr\td0, [sp, #376]\t@ 0x178\n+\tvmul.f64\td5, d10, d10\n+\tvmul.f64\td9, d7, d7\n+\tvsub.f64\td7, d0, d8\n+\tvldr\td0, [pc, #508]\t@ 40d0 <__gridxc_gga_MOD_pw91xc+0x470>\n+\tvmul.f64\td10, d11, d11\n+\tvstr\td3, [sp, #272]\t@ 0x110\n+\tvstr\td5, [sp, #280]\t@ 0x118\n+\tvdiv.f64\td4, d6, d7\n+\tvmul.f64\td0, d3, d0\n+\tvldr\td6, [pc, #492]\t@ 40d8 <__gridxc_gga_MOD_pw91xc+0x478>\n+\tvmul.f64\td2, d9, d9\n+\tvldr\td7, [pc, #492]\t@ 40e0 <__gridxc_gga_MOD_pw91xc+0x480>\n+\tvstr\td10, [sp, #408]\t@ 0x198\n+\tvnmul.f64\td0, d5, d0\n+\tvldr\td5, [pc, #488]\t@ 40e8 <__gridxc_gga_MOD_pw91xc+0x488>\n+\tvstr\td2, [sp, #216]\t@ 0xd8\n+\tvstr\td9, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td6, d11, d5\n+\tvldr\td5, [pc, #480]\t@ 40f0 <__gridxc_gga_MOD_pw91xc+0x490>\n+\tvmla.f64\td6, d10, d5\n+\tvmov.f64\td14, d6\n+\tvstr\td6, [sp, #392]\t@ 0x188\n+\tvmov.f64\td6, d9\n+\tvmla.f64\td6, d2, d4\n+\tvstr\td4, [sp, #16]\n+\tvmov.f64\td5, d6\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td6, [sp, #152]\t@ 0x98\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d4, d5\n+\tvdiv.f64\td6, d8, d6\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #168]\t@ 0xa8\n+\tvstr\td7, [sp, #184]\t@ 0xb8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvdiv.f64\td17, d8, d11\n-\tvldr\td16, [pc, #488]\t@ 3d10 <__gridxc_gga_MOD_pw91xc+0x4d8>\n-\tvadd.f64\td18, d15, d8\n-\tvstr\td0, [sp, #376]\t@ 0x178\n-\tvmov.f64\td15, d0\n-\tvmov.f64\td0, d18\n-\tvstr\td18, [sp, #232]\t@ 0xe8\n-\tvfma.f64\td16, d17, d14\n-\tvstr\td17, [sp, #264]\t@ 0x108\n-\tvldr\td17, [pc, #464]\t@ 3d18 <__gridxc_gga_MOD_pw91xc+0x4e0>\n-\tvmul.f64\td8, d16, d17\n-\tvldr\td16, [pc, #464]\t@ 3d20 <__gridxc_gga_MOD_pw91xc+0x4e8>\n-\tvmul.f64\td11, d13, d16\n-\tvstr\td8, [sp, #384]\t@ 0x180\n-\tvstr\td11, [sp, #224]\t@ 0xe0\n+\tvldr\td5, [pc, #420]\t@ 40f8 <__gridxc_gga_MOD_pw91xc+0x498>\n+\tvmov.f64\td4, d8\n+\tvldr\td7, [pc, #420]\t@ 4100 <__gridxc_gga_MOD_pw91xc+0x4a0>\n+\tvldr\td6, [pc, #424]\t@ 4108 <__gridxc_gga_MOD_pw91xc+0x4a8>\n+\tvmla.f64\td4, d10, d5\n+\tvstr\td0, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td6, d10, d7\n+\tvmov.f64\td7, d4\n+\tvmla.f64\td7, d6, d11\n+\tvdiv.f64\td6, d8, d7\n+\tvldr\td7, [sp, #184]\t@ 0xb8\n+\tvadd.f64\td5, d7, d8\n+\tvldr\td7, [pc, #396]\t@ 4110 <__gridxc_gga_MOD_pw91xc+0x4b0>\n+\tvmov.f64\td0, d5\n+\tvstr\td5, [sp, #256]\t@ 0x100\n+\tvnmls.f64\td7, d6, d14\n+\tvstr\td6, [sp, #288]\t@ 0x120\n+\tvldr\td6, [pc, #384]\t@ 4118 <__gridxc_gga_MOD_pw91xc+0x4b8>\n+\tvmul.f64\td8, d7, d6\n+\tvldr\td7, [pc, #384]\t@ 4120 <__gridxc_gga_MOD_pw91xc+0x4c0>\n+\tvmul.f64\td10, d13, d7\n+\tvstr\td8, [sp, #400]\t@ 0x190\n+\tvstr\td10, [sp, #248]\t@ 0xf8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td28, [sp, #16]\n-\tvmov.i64\td24, #0x0000000000000000\n-\tvldr\td16, [sp, #520]\t@ 0x208\n-\tadd\tr3, sp, #448\t@ 0x1c0\n-\tvldr\td29, [sp, #8]\n-\tvmul.f64\td31, d28, d8\n-\tvldr\td19, [sp, #24]\n-\tvstr\td16, [sp, #408]\t@ 0x198\n-\tvldr\td16, [sp, #528]\t@ 0x210\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tadd\tr3, sp, #488\t@ 0x1e8\n-\tstr\tr7, [sp, #108]\t@ 0x6c\n-\tvstr\td16, [sp, #424]\t@ 0x1a8\n-\tvmul.f64\td16, d31, d15\n-\tvfma.f64\td16, d11, d0\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\tadd\tr3, sp, #536\t@ 0x218\n+\tvmul.f64\td7, d9, d8\n+\tvldr\td6, [sp, #192]\t@ 0xc0\n+\tvldr\td5, [sp, #528]\t@ 0x210\n+\tadd\tr3, sp, #456\t@ 0x1c8\n+\tvldr\td2, [sp, #24]\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tadd\tr3, sp, #496\t@ 0x1f0\n+\tvstr\td7, [sp, #264]\t@ 0x108\n+\tvmul.f64\td7, d7, d6\n+\tvmla.f64\td7, d10, d0\n+\tvstr\td5, [sp, #416]\t@ 0x1a0\n+\tvldr\td5, [sp, #536]\t@ 0x218\n \tstr\tr3, [sp, #120]\t@ 0x78\n-\tvstr\td31, [sp, #184]\t@ 0xb8\n-\tvstr\td29, [sp, #192]\t@ 0xc0\n-\tvstr\td28, [sp, #200]\t@ 0xc8\n-\tvstr\td16, [sp, #144]\t@ 0x90\n-\tvadd.f64\td16, d12, d16\n-\tvstr\td16, [sp, #168]\t@ 0xa8\n+\tadd\tr3, sp, #544\t@ 0x220\n+\tstr\tr7, [sp, #96]\t@ 0x60\n+\tvstr\td5, [sp, #432]\t@ 0x1b0\n+\tvldr\td5, [pc, #320]\t@ 4128 <__gridxc_gga_MOD_pw91xc+0x4c8>\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tvstr\td7, [sp, #160]\t@ 0xa0\n+\tvadd.f64\td7, d12, d7\n+\tvstr\td5, [sp, #8]\n+\tvstr\td7, [sp, #224]\t@ 0xe0\n \tvldmia\tr4!, {d8}\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvldmia\tr9!, {d14}\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n+\tvldmia\tr9!, {d9}\n \tadds\tr6, #24\n-\tvldr\td16, [pc, #220]\t@ 3ca0 <__gridxc_gga_MOD_pw91xc+0x468>\n-\tvmov.f64\td11, d12\n-\tvadd.f64\td8, d8, d8\n-\tvstr\td24, [sp, #88]\t@ 0x58\n-\tvadd.f64\td14, d14, d14\n-\tvstr\td19, [sp, #80]\t@ 0x50\n+\tvldr\td7, [pc, #148]\t@ 40a0 <__gridxc_gga_MOD_pw91xc+0x440>\n \tadds\tr5, #24\n-\tvmaxnm.f64\td8, d8, d19\n-\tvmaxnm.f64\td14, d14, d19\n-\tvmul.f64\td0, d8, d16\n-\tvstr\td8, [sp, #488]\t@ 0x1e8\n+\tvadd.f64\td8, d8, d8\n+\tvstr\td2, [sp, #80]\t@ 0x50\n+\tvadd.f64\td9, d9, d9\n+\tvldr\td13, [pc, #272]\t@ 4130 <__gridxc_gga_MOD_pw91xc+0x4d0>\n+\tvcmpe.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td9, d2\n+\tit\tlt\n+\tvmovlt.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d8, d7\n+\tvstr\td8, [sp, #496]\t@ 0x1f0\n+\tit\tlt\n+\tvmovlt.f64\td9, d2\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td26, d8, d0\n-\tvstr\td0, [sp, #72]\t@ 0x48\n-\tvmul.f64\td16, d14, d21\n-\tvstr\td21, [sp, #64]\t@ 0x40\n-\tvstr\td26, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td13, d16, d26\n-\tvldr\td16, [pc, #284]\t@ 3d28 <__gridxc_gga_MOD_pw91xc+0x4f0>\n-\tvmul.f64\td0, d13, d16\n-\tvmov.f64\td16, d12\n-\tvmul.f64\td15, d13, d13\n-\tvfma.f64\td16, d0, d0\n-\tvsqrt.f64\td7, d16\n-\tvadd.f64\td0, d0, d7\n-\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td1, d8, d0\n+\tvmov.f64\td11, d0\n+\tvmul.f64\td7, d9, d7\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvdiv.f64\td12, d7, d1\n+\tvldr\td7, [pc, #212]\t@ 4138 <__gridxc_gga_MOD_pw91xc+0x4d8>\n+\tvmul.f64\td0, d12, d7\n+\tvmov.f64\td7, d14\n+\tvmul.f64\td10, d12, d12\n+\tvmla.f64\td7, d0, d0\n+\tvsqrt.f64\td3, d7\n+\tvadd.f64\td0, d0, d3\n+\tvstr\td3, [sp, #64]\t@ 0x40\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td20, [pc, #256]\t@ 3d30 <__gridxc_gga_MOD_pw91xc+0x4f8>\n-\tvmul.f64\td20, d0, d20\n-\tvldr\td0, [pc, #152]\t@ 3cd0 <__gridxc_gga_MOD_pw91xc+0x498>\n-\tvnmul.f64\td0, d0, d15\n-\tvfma.f64\td11, d13, d20\n-\tvstr\td20, [sp, #40]\t@ 0x28\n-\tbl\t0 \n- R_ARM_THM_CALL\texp\n-\tvldr\td16, [pc, #236]\t@ 3d38 <__gridxc_gga_MOD_pw91xc+0x500>\n-\tvmul.f64\td25, d15, d13\n-\tvldr\td15, [pc, #236]\t@ 3d40 <__gridxc_gga_MOD_pw91xc+0x508>\n-\tldr\tr1, [pc, #260]\t@ (3d5c <__gridxc_gga_MOD_pw91xc+0x524>)\n-\tvmul.f64\td16, d13, d16\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tstr\tr3, [sp, #0]\n-\tadd\tr1, pc\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tldrd\tr0, r2, [sp, #112]\t@ 0x70\n-\tvmov.f64\td18, d11\n-\tvfma.f64\td18, d25, d16\n-\tvldr\td16, [pc, #212]\t@ 3d48 <__gridxc_gga_MOD_pw91xc+0x510>\n-\tvstr\td25, [sp, #32]\n-\tvstr\td0, [sp, #24]\n-\tvfms.f64\td15, d0, d16\n-\tvdiv.f64\td23, d12, d18\n-\tvmov.f64\td18, d11\n-\tb.n\t3d60 <__gridxc_gga_MOD_pw91xc+0x528>\n+\tvmul.f64\td13, d0, d13\n+\tvmov.f64\td7, d14\n+\tb.n\t414c <__gridxc_gga_MOD_pw91xc+0x4ec>\n \tnop\n-\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0xa4aeacc4\n \t.word\t0x3fce8ec8\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0x6dc9c883\n@@ -4437,478 +4718,557 @@\n \t.word\t0x3fefffff\n \t.word\t0x26a4059d\n \t.word\t0x404436bc\n \t.word\t0x0c51b48d\n \t.word\t0x400594a8\n \t.word\t0x00000000\n \t.word\t0x40590000\n-\t.word\t0x7d805e5f\n-\t.word\t0x3fb2ea74\n-\t.word\t0x0e560419\n-\t.word\t0x4021722d\n-\t.word\t0xd46f587d\n-\t.word\t0x3f97d30a\n-\t.word\t0x7ced9168\n-\t.word\t0x3fde353f\n-\t.word\t0x0c51b48e\n-\t.word\t0x400594a8\n \t.word\t0x80841ede\n \t.word\t0x3f65097c\n+\t.word\t0x0c51b48e\n+\t.word\t0x400594a8\n+\t.word\t0xd46f587d\n+\t.word\t0x3f97d30a\n \t.word\t0xdaba8ff8\n \t.word\t0x3edefde0\n+\t.word\t0x7ced9168\n+\t.word\t0x3fde353f\n+\t.word\t0x7d805e5f\n+\t.word\t0x3fb2ea74\n+\t.word\t0x0e560419\n+\t.word\t0x4021722d\n \t.word\t0xf9eb5caa\n-\t.word\t0xbf5e5d2b\n+\t.word\t0x3f5e5d2b\n \t.word\t0xf23cc8de\n \t.word\t0x402f8307\n \t.word\t0xc1e222c8\n \t.word\t0x3f995447\n-\t.word\t0xc432ca58\n-\t.word\t0x401f2eb1\n+\t...\n \t.word\t0x0aa64c30\n \t.word\t0x3fc92546\n-\t.word\t0xd2f1a9fc\n-\t.word\t0x3f70624d\n-\t.word\t0x9652bd3c\n-\t.word\t0x3fd18e21\n-\t.word\t0xa176ddad\n-\t.word\t0x3fc34eb9\n-\t.word\t0x000004f2\n+\t.word\t0xc432ca58\n+\t.word\t0x401f2eb1\n+\t.word\t0x000004ba\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000412\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000000f8\n+\t.word\t0x000003ca\n R_ARM_REL32\t.rodata\n-\tvmul.f64\td15, d13, d15\n-\tvfma.f64\td18, d15, d13\n-\tvstr\td18, [sp, #8]\n-\tvmul.f64\td11, d18, d23\n-\tvstr\td23, [sp, #16]\n+\tvldr\td0, [pc, #992]\t@ 4530 <__gridxc_gga_MOD_pw91xc+0x8d0>\n+\tvmla.f64\td7, d12, d13\n+\tvnmul.f64\td0, d0, d10\n+\tvmul.f64\td10, d10, d12\n+\tvstr\td7, [sp, #24]\n+\tbl\t0 \n+ R_ARM_THM_CALL\texp\n+\tvldr\td5, [pc, #976]\t@ 4538 <__gridxc_gga_MOD_pw91xc+0x8d8>\n+\tvmov.f64\td4, d0\n+\tvldr\td7, [sp, #24]\n+\tldr.w\tr1, [pc, #1084]\t@ 45b0 <__gridxc_gga_MOD_pw91xc+0x950>\n+\tvmul.f64\td5, d12, d5\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvmov.f64\td6, d7\n+\tstr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tadd\tr1, pc\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvmla.f64\td6, d5, d10\n+\tvldr\td5, [pc, #948]\t@ 4540 <__gridxc_gga_MOD_pw91xc+0x8e0>\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tvstr\td4, [sp, #24]\n+\tvdiv.f64\td0, d14, d6\n+\tvldr\td6, [pc, #940]\t@ 4548 <__gridxc_gga_MOD_pw91xc+0x8e8>\n+\tvmls.f64\td6, d4, d5\n+\tvmul.f64\td6, d6, d12\n+\tvmla.f64\td7, d6, d12\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #32]\n+\tvmul.f64\td5, d7, d0\n+\tvstr\td0, [sp, #48]\t@ 0x30\n+\tvstr\td5, [sp, #40]\t@ 0x28\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td30, [pc, #964]\t@ 4140 <__gridxc_gga_MOD_pw91xc+0x908>\n-\tvldr\td7, [sp, #48]\t@ 0x30\n-\tvldr\td20, [sp, #40]\t@ 0x28\n-\tvmul.f64\td30, d13, d30\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tvldr\td26, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td27, d12, d14\n-\tvldr\td25, [sp, #32]\n-\tvldr\td18, [sp, #8]\n-\tvdiv.f64\td16, d30, d7\n-\tvldr\td0, [sp, #24]\n-\tvldr\td23, [sp, #16]\n-\tvldr\td24, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvldr\td21, [sp, #64]\t@ 0x40\n+\tvldr\td7, [pc, #908]\t@ 4550 <__gridxc_gga_MOD_pw91xc+0x8f0>\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvmul.f64\td7, d12, d7\n+\tvldr\td2, [sp, #24]\n+\tvdiv.f64\td4, d14, d9\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tvdiv.f64\td5, d7, d3\n+\tvadd.f64\td6, d6, d6\n+\tvdiv.f64\td7, d14, d8\n \tcmp\tr4, r3\n-\tvldr\td19, [sp, #80]\t@ 0x50\n-\tvadd.f64\td16, d16, d20\n-\tvldr\td20, [pc, #904]\t@ 4148 <__gridxc_gga_MOD_pw91xc+0x910>\n-\tvmul.f64\td22, d22, d20\n-\tvdiv.f64\td30, d22, d26\n-\tvldr\td26, [pc, #900]\t@ 4150 <__gridxc_gga_MOD_pw91xc+0x918>\n-\tvdiv.f64\td22, d12, d8\n-\tvadd.f64\td30, d30, d22\n-\tvmov.f64\td22, d16\n-\tvfma.f64\td22, d25, d26\n-\tvldr\td26, [r6, #-24]\t@ 0xffffffe8\n-\tvadd.f64\td26, d26, d26\n-\tvmul.f64\td18, d18, d22\n-\tvldr\td22, [pc, #876]\t@ 4158 <__gridxc_gga_MOD_pw91xc+0x920>\n-\tvmul.f64\td17, d0, d22\n-\tvldr\td22, [r6, #-8]\n-\tvadd.f64\td22, d22, d22\n-\tvfma.f64\td16, d25, d17\n-\tvmov.f64\td17, #0\t@ 0x40000000 2.0\n-\tvldr\td25, [r6, #-16]\n-\tvfma.f64\td16, d15, d17\n-\tvadd.f64\td25, d25, d25\n-\tvfms.f64\td16, d23, d18\n-\tvldr\td18, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td18, d8, d18\n-\tvmul.f64\td26, d26, d18\n-\tvmul.f64\td25, d25, d18\n-\tvmul.f64\td22, d22, d18\n-\tvfma.f64\td24, d18, d11\n-\tvmul.f64\td18, d18, d13\n-\tvmul.f64\td23, d23, d16\n-\tvmul.f64\td16, d13, d27\n-\tvmul.f64\td26, d26, d27\n-\tvmul.f64\td25, d25, d27\n-\tvmul.f64\td22, d22, d27\n-\tvmul.f64\td18, d18, d30\n-\tvmul.f64\td26, d26, d16\n-\tvmul.f64\td25, d25, d16\n-\tvmul.f64\td16, d22, d16\n-\tvldr\td22, [sp, #536]\t@ 0x218\n-\tvnmul.f64\td18, d23, d18\n-\tvfma.f64\td18, d22, d11\n-\tvmul.f64\td26, d26, d23\n-\tvmul.f64\td25, d25, d23\n-\tvmul.f64\td16, d16, d23\n-\tvstr\td26, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td25, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tvstmia\tr7!, {d18}\n-\tbne.w\t3bb2 <__gridxc_gga_MOD_pw91xc+0x37a>\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvldr\td18, [sp, #96]\t@ 0x60\n+\tvadd.f64\td5, d5, d13\n+\tvldr\td13, [pc, #868]\t@ 4558 <__gridxc_gga_MOD_pw91xc+0x8f8>\n+\tvmul.f64\td11, d11, d13\n+\tvmov.f64\td0, d5\n+\tvdiv.f64\td3, d11, d1\n+\tvldr\td1, [pc, #860]\t@ 4560 <__gridxc_gga_MOD_pw91xc+0x900>\n+\tvmul.f64\td1, d2, d1\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvmla.f64\td0, d1, d10\n+\tvldr\td1, [sp, #8]\n+\tvadd.f64\td3, d3, d7\n+\tvadd.f64\td7, d0, d6\n+\tvldr\td6, [pc, #840]\t@ 4568 <__gridxc_gga_MOD_pw91xc+0x908>\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvmla.f64\td5, d10, d6\n+\tvldr\td6, [sp, #32]\n+\tvmul.f64\td5, d5, d6\n+\tvldr\td6, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td6, d8, d6\n+\tvmls.f64\td7, d5, d0\n+\tvldr\td5, [r6, #-8]\n+\tvmla.f64\td1, d6, d2\n+\tvadd.f64\td5, d5, d5\n+\tvmul.f64\td5, d5, d6\n+\tvmul.f64\td7, d7, d0\n+\tvldr\td0, [r6, #-24]\t@ 0xffffffe8\n+\tvstr\td1, [sp, #8]\n+\tvadd.f64\td0, d0, d0\n+\tvldr\td1, [r6, #-16]\n+\tvmul.f64\td5, d5, d4\n+\tvadd.f64\td1, d1, d1\n+\tvmul.f64\td0, d0, d6\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td6, d6, d12\n+\tvmul.f64\td0, d0, d4\n+\tvmul.f64\td6, d3, d6\n+\tvmul.f64\td1, d1, d4\n+\tvmul.f64\td3, d12, d4\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td0, d0, d3\n+\tvmul.f64\td1, d1, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td0, d0, d7\n+\tvmul.f64\td1, d1, d7\n+\tvmul.f64\td5, d5, d7\n+\tvldr\td7, [sp, #544]\t@ 0x220\n+\tvnmls.f64\td6, d2, d7\n+\tvstr\td0, [r5, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [sp, #80]\t@ 0x50\n+\tvstr\td1, [r5, #-16]\n+\tvstr\td5, [r5, #-8]\n+\tvstmia\tr7!, {d6}\n+\tbne.w\t3ffc <__gridxc_gga_MOD_pw91xc+0x39c>\n+\tldr\tr3, [sp, #236]\t@ 0xec\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tvldr\td1, [sp, #88]\t@ 0x58\n+\tvldr\td5, [sp, #8]\n+\tvstr\td7, [r3]\n+\tvmul.f64\td7, d1, d6\n+\tldr\tr3, [sp, #232]\t@ 0xe8\n \tldr.w\tr1, [r8]\n-\tvstr\td16, [r3]\n-\tvmul.f64\td16, d18, d21\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tvldr\td31, [sp, #184]\t@ 0xb8\n \tcmp\tr1, #0\n-\tvldr\td29, [sp, #192]\t@ 0xc0\n-\tvldr\td28, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td16, d16, d24\n-\tvstr\td16, [r3]\n-\tble.w\t4266 <__gridxc_gga_MOD_pw91xc+0xa2e>\n-\tvldr\td16, [sp, #320]\t@ 0x140\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td7, [r3]\n+\tble.w\t4796 <__gridxc_gga_MOD_pw91xc+0xb36>\n+\tvldr\td7, [sp, #352]\t@ 0x160\n \tcmp\tr1, #1\n-\tvldr\td19, [sp, #312]\t@ 0x138\n-\tvldr\td27, [sp, #136]\t@ 0x88\n-\tvdiv.f64\td23, d12, d16\n-\tvldr\td16, [sp, #352]\t@ 0x160\n-\tvmul.f64\td3, d19, d18\n-\tvldr\td19, [sp, #336]\t@ 0x150\n-\tvldr\td30, [sp, #296]\t@ 0x128\n-\tvdiv.f64\td16, d12, d16\n-\tvldr\td6, [sp, #304]\t@ 0x130\n-\tvldr\td1, [sp, #392]\t@ 0x188\n-\tvldr\td26, [sp, #368]\t@ 0x170\n-\tvmul.f64\td21, d6, d21\n-\tvsub.f64\td23, d23, d16\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvdiv.f64\td8, d17, d16\n-\tvmov.f64\td16, d18\n-\tvldr\td18, [sp, #344]\t@ 0x158\n-\tvmul.f64\td2, d23, d20\n-\tvmul.f64\td0, d19, d18\n-\tvsub.f64\td19, d12, d18\n-\tvldr\td18, [sp, #288]\t@ 0x120\n-\tvmul.f64\td3, d3, d2\n-\tvdiv.f64\td7, d12, d18\n-\tvldr\td18, [sp, #232]\t@ 0xe8\n-\tvdiv.f64\td15, d12, d19\n-\tvldr\td19, [sp, #128]\t@ 0x80\n-\tvmul.f64\td0, d0, d29\n-\tvdiv.f64\td13, d12, d18\n-\tvldr\td18, [sp, #384]\t@ 0x180\n-\tvmul.f64\td4, d27, d18\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tvmul.f64\td23, d18, d7\n-\tvldr\td18, [sp, #280]\t@ 0x118\n-\tvmul.f64\td22, d18, d7\n-\tvldr\td18, [sp, #152]\t@ 0x98\n-\tvmul.f64\td24, d18, d7\n-\tvmul.f64\td18, d30, d20\n-\tvmul.f64\td20, d10, d20\n-\tvmul.f64\td18, d18, d16\n-\tvnmul.f64\td20, d16, d20\n-\tvmul.f64\td21, d21, d18\n-\tvmul.f64\td18, d19, d18\n-\tvmul.f64\td26, d26, d20\n-\tvdiv.f64\td25, d21, d30\n-\tvldr\td21, [sp, #216]\t@ 0xd8\n-\tvdiv.f64\td5, d18, d30\n-\tvldr\td30, [sp, #408]\t@ 0x198\n-\tvmul.f64\td18, d21, d9\n-\tvdiv.f64\td14, d12, d18\n-\tvldr\td18, [sp, #160]\t@ 0xa0\n-\tvdiv.f64\td11, d12, d18\n-\tvldr\td18, [pc, #476]\t@ 4160 <__gridxc_gga_MOD_pw91xc+0x928>\n-\tvmov.f64\td12, d21\n-\tvmul.f64\td25, d25, d27\n-\tvfma.f64\td5, d19, d16\n-\tvldr\td19, [pc, #468]\t@ 4168 <__gridxc_gga_MOD_pw91xc+0x930>\n-\tvdiv.f64\td6, d25, d6\n-\tvmov.f64\td25, #8\t@ 0x40400000 3.0\n-\tvfma.f64\td6, d27, d16\n-\tvldr\td16, [sp, #144]\t@ 0x90\n-\tvldr\td27, [pc, #456]\t@ 4170 <__gridxc_gga_MOD_pw91xc+0x938>\n-\tvfma.f64\td27, d10, d18\n-\tvsub.f64\td18, d30, d21\n-\tvadd.f64\td21, d16, d30\n-\tvldr\td30, [pc, #448]\t@ 4178 <__gridxc_gga_MOD_pw91xc+0x940>\n-\tvfma.f64\td27, d1, d30\n-\tvldr\td30, [pc, #448]\t@ 4180 <__gridxc_gga_MOD_pw91xc+0x948>\n-\tvfma.f64\td30, d10, d19\n-\tvnmul.f64\td1, d25, d8\n-\tvmul.f64\td25, d16, d25\n-\tvldr\td16, [pc, #440]\t@ 4188 <__gridxc_gga_MOD_pw91xc+0x950>\n-\tvldr\td10, [sp, #128]\t@ 0x80\n-\tvmov.f64\td19, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td18, d18, d14\n-\tvmul.f64\td26, d26, d16\n-\tvmul.f64\td19, d29, d19\n-\tvfma.f64\td18, d1, d3\n-\tvmul.f64\td30, d30, d16\n-\tvmul.f64\td26, d26, d27\n-\tvldr\td27, [sp, #376]\t@ 0x178\n-\tvfma.f64\td17, d28, d19\n-\tvldr\td19, [sp, #136]\t@ 0x88\n-\tvmul.f64\td30, d30, d20\n-\tvldr\td20, [sp, #264]\t@ 0x108\n-\tvmul.f64\td18, d0, d18\n-\tvfms.f64\td30, d20, d26\n-\tvldr\td26, [sp, #256]\t@ 0x100\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td19, d19, d7\n+\tvldr\td0, [sp, #256]\t@ 0x100\n+\tvldr\td12, [sp, #328]\t@ 0x148\n+\tvdiv.f64\td2, d14, d7\n+\tvldr\td7, [sp, #384]\t@ 0x180\n+\tvdiv.f64\td0, d14, d0\n+\tvldr\td8, [sp, #400]\t@ 0x190\n+\tvmul.f64\td4, d12, d6\n+\tvldr\td6, [sp, #368]\t@ 0x170\n+\tvdiv.f64\td7, d14, d7\n+\tvldr\td10, [sp, #296]\t@ 0x128\n+\tvldr\td11, [sp, #392]\t@ 0x188\n+\tvstr\td0, [sp, #24]\n+\tvldr\td0, [sp, #176]\t@ 0xb0\n+\tvsub.f64\td2, d2, d7\n+\tvldr\td7, [sp, #344]\t@ 0x158\n+\tvmul.f64\td8, d0, d8\n+\tvmul.f64\td5, d7, d1\n+\tvldr\td7, [sp, #376]\t@ 0x178\n+\tvmul.f64\td2, d2, d13\n+\tvmul.f64\td3, d6, d7\n+\tvsub.f64\td6, d14, d7\n+\tvldr\td7, [sp, #312]\t@ 0x138\n+\tvstr\td8, [sp, #72]\t@ 0x48\n+\tvmul.f64\td5, d5, d2\n+\tvldr\td8, [sp, #16]\n+\tvdiv.f64\td7, d14, d7\n+\tvstr\td2, [sp, #176]\t@ 0xb0\n+\tvdiv.f64\td9, d14, d6\n+\tvmul.f64\td3, d3, d8\n+\tvstr\td5, [sp, #32]\n+\tvstr\td3, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d10, d7\n+\tvldr\td10, [sp, #304]\t@ 0x130\n+\tvstr\td9, [sp, #40]\t@ 0x28\n+\tvldr\td9, [sp, #136]\t@ 0x88\n+\tvmul.f64\td2, d10, d7\n+\tvldr\td10, [sp, #200]\t@ 0xc8\n+\tvstr\td6, [sp, #104]\t@ 0x68\n+\tvmul.f64\td3, d10, d7\n+\tvldr\td10, [sp, #336]\t@ 0x150\n+\tvstr\td2, [sp, #112]\t@ 0x70\n+\tvstr\td3, [sp, #96]\t@ 0x60\n+\tvldr\td3, [sp, #320]\t@ 0x140\n+\tvmul.f64\td6, d3, d13\n+\tvmul.f64\td13, d9, d13\n+\tvmul.f64\td6, d6, d1\n+\tvnmul.f64\td13, d1, d13\n+\tvmul.f64\td4, d4, d6\n+\tvmul.f64\td2, d11, d13\n+\tvmov.f64\td11, d3\n+\tvmul.f64\td6, d10, d6\n+\tvdiv.f64\td3, d4, d11\n+\tvmov.f64\td4, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td11, d6, d11\n+\tvmul.f64\td3, d3, d0\n+\tvmla.f64\td11, d10, d1\n+\tvdiv.f64\td8, d3, d12\n+\tvldr\td3, [sp, #144]\t@ 0x90\n+\tvldr\td12, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td6, d3, d15\n+\tvldr\td3, [pc, #392]\t@ 4570 <__gridxc_gga_MOD_pw91xc+0x910>\n+\tvdiv.f64\td12, d4, d12\n+\tvdiv.f64\td5, d14, d6\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td6, d14, d6\n+\tvnmla.f64\td8, d1, d0\n+\tvmov.f64\td1, #8\t@ 0x40400000 3.0\n+\tvstr\td5, [sp, #56]\t@ 0x38\n+\tvstr\td6, [sp, #8]\n+\tvldr\td6, [pc, #364]\t@ 4578 <__gridxc_gga_MOD_pw91xc+0x918>\n+\tvldr\td5, [sp, #416]\t@ 0x1a0\n+\tvmla.f64\td6, d9, d3\n+\tvldr\td3, [sp, #144]\t@ 0x90\n+\tvldr\td9, [sp, #16]\n+\tvsub.f64\td14, d5, d3\n+\tvldr\td3, [pc, #348]\t@ 4580 <__gridxc_gga_MOD_pw91xc+0x920>\n+\tvstr\td14, [sp, #120]\t@ 0x78\n+\tvldr\td14, [sp, #160]\t@ 0xa0\n+\tvadd.f64\td14, d14, d5\n+\tvldr\td5, [sp, #408]\t@ 0x198\n+\tvmla.f64\td6, d5, d3\n+\tvmov.f64\td3, #16\t@ 0x40800000 4.0\n+\tvldr\td5, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td3, d9, d3\n+\tvldr\td9, [sp, #136]\t@ 0x88\n+\tvmla.f64\td4, d3, d5\n+\tvmul.f64\td3, d0, d7\n+\tvldr\td5, [sp, #288]\t@ 0x120\n \tvmul.f64\td7, d10, d7\n-\tvnmul.f64\td18, d15, d18\n-\tvmul.f64\td16, d20, d30\n-\tvldr\td20, [pc, #360]\t@ 4190 <__gridxc_gga_MOD_pw91xc+0x958>\n-\tvmul.f64\td20, d27, d20\n-\tvmul.f64\td16, d16, d28\n-\tvnmul.f64\td28, d6, d17\n-\tvmul.f64\td20, d20, d10\n-\tvldr\td10, [sp, #360]\t@ 0x168\n-\tvmul.f64\td20, d20, d26\n-\tvldr\td26, [pc, #340]\t@ 4198 <__gridxc_gga_MOD_pw91xc+0x960>\n-\tvmul.f64\td26, d27, d26\n-\tvnmul.f64\td30, d5, d20\n-\tvmov.f64\td5, d27\n-\tvldr\td27, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td26, d26, d27\n-\tvldr\td27, [sp, #328]\t@ 0x148\n-\tvmul.f64\td26, d26, d27\n-\tvneg.f64\td27, d6\n-\tvldr\td6, [sp, #224]\t@ 0xe0\n-\tvadd.f64\td27, d27, d27\n-\tvmul.f64\td17, d6, d17\n-\tvmul.f64\td6, d6, d10\n-\tvfma.f64\td16, d4, d27\n-\tvmul.f64\td17, d17, d10\n-\tvmul.f64\td27, d6, d13\n-\tvadd.f64\td6, d5, d5\n-\tvstr\td27, [sp, #8]\n-\tvmov.f64\td27, d28\n-\tvstr\td6, [sp, #16]\n-\tvldr\td10, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td16, d16, d5\n-\tvldr\td5, [sp, #240]\t@ 0xf0\n-\tvldr\td6, [sp, #400]\t@ 0x190\n-\tldr\tr0, [sp, #420]\t@ 0x1a4\n-\tvfma.f64\td27, d5, d18\n-\tvmul.f64\td18, d10, d18\n-\tldr\tr4, [sp, #416]\t@ 0x1a0\n-\tldrd\tr2, r3, [sp, #472]\t@ 0x1d8\n-\tstrd\tr2, r3, [r4]\n-\tldrd\tr2, r3, [sp, #576]\t@ 0x240\n-\tstrd\tr2, r3, [sl]\n-\tldrd\tr2, r3, [sp, #584]\t@ 0x248\n-\tvfma.f64\td18, d29, d27\n-\tvmul.f64\td27, d11, d27\n-\tstrd\tr2, r3, [sl, #8]\n-\tldrd\tr2, r3, [sp, #592]\t@ 0x250\n-\tstrd\tr2, r3, [sl, #16]\n-\tvfms.f64\td27, d6, d18\n-\tvmov.f64\td18, d11\n-\tvfms.f64\td18, d29, d6\n-\tvmul.f64\td17, d18, d17\n-\tvldr\td18, [sp, #16]\n-\tvmul.f64\td17, d17, d13\n-\tvfma.f64\td17, d4, d18\n-\tvmov.f64\td4, d30\n-\tvfma.f64\td4, d26, d3\n-\tvmov.f64\td18, d16\n-\tvmul.f64\td3, d8, d3\n-\tvfms.f64\td18, d31, d4\n-\tvldr\td4, [sp, #8]\n-\tvfma.f64\td18, d25, d3\n-\tvfma.f64\td18, d4, d27\n-\tvfma.f64\td21, d9, d18\n-\tvstr\td21, [r0]\n-\tvmul.f64\td21, d7, d23\n-\tvmul.f64\td23, d19, d23\n-\tvmul.f64\td21, d21, d20\n-\tvmul.f64\td23, d23, d17\n-\tvfms.f64\td23, d31, d21\n-\tvmul.f64\td21, d7, d22\n-\tvmul.f64\td7, d24, d7\n-\tvmul.f64\td22, d19, d22\n-\tvmul.f64\td19, d24, d19\n-\tb.n\t41a0 <__gridxc_gga_MOD_pw91xc+0x968>\n+\tvmul.f64\td4, d4, d0\n+\tvldr\td0, [pc, #296]\t@ 4588 <__gridxc_gga_MOD_pw91xc+0x928>\n+\tvmul.f64\td2, d2, d0\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td2, d12, d1\n+\tvstr\td2, [sp, #48]\t@ 0x30\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td2, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td1, d2, d1\n+\tvldr\td2, [pc, #272]\t@ 4590 <__gridxc_gga_MOD_pw91xc+0x930>\n+\tvstr\td1, [sp, #80]\t@ 0x50\n+\tvldr\td1, [pc, #272]\t@ 4598 <__gridxc_gga_MOD_pw91xc+0x938>\n+\tvmla.f64\td2, d9, d1\n+\tvldr\td1, [pc, #272]\t@ 45a0 <__gridxc_gga_MOD_pw91xc+0x940>\n+\tvmul.f64\td9, d8, d4\n+\tvstr\td9, [sp, #128]\t@ 0x80\n+\tvmul.f64\td2, d2, d0\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvnmls.f64\td6, d2, d13\n+\tvldr\td13, [sp, #48]\t@ 0x30\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td5, [sp, #32]\n+\tvmul.f64\td2, d13, d5\n+\tvldr\td13, [sp, #120]\t@ 0x78\n+\tvldr\td5, [sp, #272]\t@ 0x110\n+\tvnmls.f64\td2, d13, d0\n+\tvldr\td13, [sp, #64]\t@ 0x40\n+\tvldr\td0, [pc, #224]\t@ 45a8 <__gridxc_gga_MOD_pw91xc+0x948>\n+\tvmul.f64\td2, d2, d13\n+\tvldr\td13, [sp, #40]\t@ 0x28\n+\tvnmul.f64\td2, d13, d2\n+\tvldr\td13, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td0, d13, d0\n+\tvmul.f64\td1, d13, d1\n+\tvmul.f64\td0, d0, d10\n+\tvmul.f64\td1, d1, d5\n+\tvldr\td10, [sp, #280]\t@ 0x118\n+\tvldr\td5, [sp, #360]\t@ 0x168\n+\tvmul.f64\td0, d0, d10\n+\tvmov.f64\td10, d13\n+\tvmul.f64\td13, d1, d5\n+\tvadd.f64\td1, d8, d8\n+\tvldr\td8, [sp, #248]\t@ 0xf8\n+\tvldr\td5, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td11, d11, d0\n+\tvmul.f64\td4, d8, d4\n+\tvmul.f64\td8, d8, d5\n+\tvmul.f64\td4, d4, d5\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvmul.f64\td1, d1, d5\n+\tvstr\td4, [sp, #120]\t@ 0x78\n+\tvldr\td4, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td1, d6, d4\n+\tb.n\t45b4 <__gridxc_gga_MOD_pw91xc+0x954>\n \tnop\n+\t.word\t0x00000000\n+\t.word\t0x40590000\n+\t.word\t0xd2f1a9fc\n+\t.word\t0x3f70624d\n+\t.word\t0xa176ddad\n+\t.word\t0x3fc34eb9\n+\t.word\t0x9652bd3c\n+\t.word\t0x3fd18e21\n \t.word\t0x1f580a03\n \t.word\t0x3ff880cd\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0xd2f1a9fc\n-\t.word\t0x3f90624d\n \t.word\t0x0c49ba5e\n \t.word\t0x403e2b02\n+\t.word\t0xd2f1a9fc\n+\t.word\t0x3f90624d\n \t.word\t0x7ced9168\n \t.word\t0x3fee353f\n-\t.word\t0xdaba8ff8\n-\t.word\t0x3eeefde0\n \t.word\t0x0e560419\n \t.word\t0x4021722d\n \t.word\t0xbc408d8e\n \t.word\t0x3fcc5fae\n-\t.word\t0xd46f587d\n-\t.word\t0x3f97d30a\n \t.word\t0xf23cc8de\n \t.word\t0x402f8307\n-\t.word\t0x00000000\n-\t.word\t0x40690000\n+\t.word\t0xd46f587d\n+\t.word\t0x3f97d30a\n+\t.word\t0xdaba8ff8\n+\t.word\t0x3eeefde0\n \t.word\t0x00000000\n \t.word\t0x40790000\n-\tvmul.f64\td21, d21, d20\n-\tvmul.f64\td7, d7, d20\n-\tvmul.f64\td22, d22, d17\n-\tvmul.f64\td19, d19, d17\n-\tvfms.f64\td22, d31, d21\n-\tvmul.f64\td23, d9, d23\n-\tvfms.f64\td19, d31, d7\n-\tvneg.f64\td31, d31\n-\tvstr\td23, [fp]\n-\tvmul.f64\td22, d9, d22\n-\tvmul.f64\td19, d9, d19\n-\tvstr\td22, [fp, #8]\n-\tvstr\td19, [fp, #16]\n-\tbeq.n\t4266 <__gridxc_gga_MOD_pw91xc+0xa2e>\n-\tvldr\td18, [sp, #432]\t@ 0x1b0\n-\tvldr\td17, [sp, #96]\t@ 0x60\n-\tvstr\td19, [fp, #40]\t@ 0x28\n-\tvldr\td19, [sp, #424]\t@ 0x1a8\n-\tvnmul.f64\td17, d17, d18\n-\tvstr\td23, [fp, #24]\n-\tldrd\tr2, r3, [sp, #600]\t@ 0x258\n-\tvsub.f64\td18, d19, d12\n-\tvmov.f64\td20, d19\n-\tvldr\td19, [sp, #144]\t@ 0x90\n-\tvmul.f64\td17, d17, d2\n-\tstrd\tr2, r3, [sl, #24]\n+\t.word\t0x00000000\n+\t.word\t0x40690000\n+\t.word\t0x0000042a\n+ R_ARM_REL32\t.rodata\n+\tvldr\td6, [sp, #24]\n+\tvmul.f64\td4, d8, d6\n+\tvadd.f64\td6, d10, d10\n+\tvmov.f64\td8, d9\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td5, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td1, d1, d10\n+\tvldr\td10, [sp, #152]\t@ 0x98\n+\tvstr\td4, [sp, #72]\t@ 0x48\n+\tvmla.f64\td8, d5, d2\n+\tvldr\td4, [sp, #16]\n+\tvmul.f64\td2, d10, d2\n+\tvldr\td9, [sp, #8]\n+\tvldr\td10, [sp, #168]\t@ 0xa8\n+\tldr\tr0, [sp, #428]\t@ 0x1ac\n+\tvmov.f64\td5, d9\n+\tldr\tr4, [sp, #424]\t@ 0x1a8\n+\tvmls.f64\td5, d4, d10\n \tldrd\tr2, r3, [sp, #480]\t@ 0x1e0\n-\tvmul.f64\td18, d18, d14\n-\tvadd.f64\td19, d20, d19\n+\tstrd\tr2, r3, [r4]\n+\tvmla.f64\td2, d4, d8\n+\tldrd\tr2, r3, [sp, #584]\t@ 0x248\n+\tstrd\tr2, r3, [sl]\n+\tldrd\tr2, r3, [sp, #592]\t@ 0x250\n+\tstrd\tr2, r3, [sl, #8]\n+\tldrd\tr2, r3, [sp, #600]\t@ 0x258\n+\tstrd\tr2, r3, [sl, #16]\n+\tvmul.f64\td2, d2, d10\n+\tvldr\td10, [sp, #120]\t@ 0x78\n+\tvmul.f64\td4, d5, d10\n+\tvmov.f64\td5, d11\n+\tvnmls.f64\td2, d9, d8\n+\tvldr\td9, [sp, #24]\n+\tvmla.f64\td6, d4, d9\n+\tvldr\td4, [sp, #32]\n+\tvldr\td9, [sp, #264]\t@ 0x108\n+\tvnmls.f64\td5, d13, d4\n+\tvmov.f64\td8, d5\n+\tvmul.f64\td5, d12, d4\n+\tvmov.f64\td4, d1\n+\tvmls.f64\td4, d8, d9\n+\tvldr\td8, [sp, #80]\t@ 0x50\n+\tvmla.f64\td4, d5, d8\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvmla.f64\td4, d2, d5\n+\tvldr\td5, [sp, #104]\t@ 0x68\n+\tvldr\td2, [sp, #112]\t@ 0x70\n+\tvmul.f64\td10, d3, d5\n+\tvmla.f64\td14, d4, d15\n+\tvmul.f64\td4, d7, d5\n+\tvmul.f64\td5, d7, d2\n+\tvmul.f64\td2, d3, d2\n+\tvmul.f64\td4, d4, d0\n+\tvmul.f64\td5, d5, d0\n+\tvmul.f64\td4, d4, d9\n+\tvstr\td14, [r0]\n+\tvmov.f64\td14, d9\n+\tvldr\td9, [sp, #96]\t@ 0x60\n+\tvmul.f64\td7, d9, d7\n+\tvmul.f64\td3, d9, d3\n+\tvmul.f64\td5, d5, d14\n+\tvnmls.f64\td4, d10, d6\n+\tvmul.f64\td7, d7, d0\n+\tvnmls.f64\td5, d2, d6\n+\tvmov.f64\td2, d14\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td4, d4, d15\n+\tvnmls.f64\td7, d3, d6\n+\tvmul.f64\td5, d5, d15\n+\tvstr\td4, [fp]\n+\tvstr\td5, [fp, #8]\n+\tvmul.f64\td7, d7, d15\n+\tvstr\td7, [fp, #16]\n+\tbeq.n\t4796 <__gridxc_gga_MOD_pw91xc+0xb36>\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvldr\td14, [sp, #440]\t@ 0x1b8\n+\tvstr\td7, [fp, #40]\t@ 0x28\n+\tvldr\td7, [sp, #176]\t@ 0xb0\n+\tvnmul.f64\td6, d6, d14\n+\tvldr\td3, [sp, #144]\t@ 0x90\n+\tvstr\td5, [fp, #32]\n+\tvstr\td4, [fp, #24]\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td10, [sp, #152]\t@ 0x98\n+\tvldr\td9, [sp, #8]\n+\tldrd\tr2, r3, [sp, #488]\t@ 0x1e8\n \tstrd\tr2, r3, [r4, #8]\n-\tvfma.f64\td18, d1, d17\n-\tvfma.f64\td30, d26, d17\n-\tvmul.f64\td8, d8, d17\n-\tvstr\td22, [fp, #32]\n+\tvnmls.f64\td11, d13, d6\n+\tvldr\td13, [sp, #40]\t@ 0x28\n \tldrd\tr2, r3, [sp, #608]\t@ 0x260\n-\tstrd\tr2, r3, [sl, #32]\n+\tstrd\tr2, r3, [sl, #24]\n \tldrd\tr2, r3, [sp, #616]\t@ 0x268\n+\tstrd\tr2, r3, [sl, #32]\n+\tldrd\tr2, r3, [sp, #624]\t@ 0x270\n \tstrd\tr2, r3, [sl, #40]\t@ 0x28\n-\tvmul.f64\td17, d18, d0\n-\tvfma.f64\td16, d31, d30\n-\tvnmul.f64\td17, d15, d17\n-\tvfma.f64\td16, d25, d8\n-\tvfma.f64\td28, d5, d17\n-\tvmul.f64\td17, d10, d17\n-\tvfma.f64\td17, d29, d28\n-\tvmul.f64\td11, d11, d28\n-\tvfms.f64\td11, d17, d6\n-\tvfma.f64\td16, d11, d4\n-\tvfma.f64\td19, d9, d16\n-\tvstr\td19, [r0, #8]\n-\tldr\tr2, [pc, #144]\t@ (42f8 <__gridxc_gga_MOD_pw91xc+0xac0>)\n-\tldr\tr3, [pc, #144]\t@ (42fc <__gridxc_gga_MOD_pw91xc+0xac4>)\n+\tvmls.f64\td1, d11, d2\n+\tvldr\td11, [sp, #432]\t@ 0x1b0\n+\tvldr\td2, [sp, #160]\t@ 0xa0\n+\tvsub.f64\td7, d11, d3\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvadd.f64\td5, d11, d2\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvmul.f64\td4, d2, d6\n+\tvmul.f64\td6, d12, d6\n+\tvldr\td12, [sp, #128]\t@ 0x80\n+\tvnmls.f64\td4, d7, d0\n+\tvldr\td7, [sp, #216]\t@ 0xd8\n+\tvmla.f64\td1, d6, d8\n+\tvldr\td8, [sp, #16]\n+\tvmul.f64\td4, d4, d3\n+\tvnmul.f64\td4, d13, d4\n+\tvmla.f64\td12, d7, d4\n+\tvmul.f64\td6, d8, d12\n+\tvmla.f64\td6, d10, d4\n+\tvldr\td10, [sp, #168]\t@ 0xa8\n+\tvldr\td4, [sp, #72]\t@ 0x48\n+\tvmul.f64\td6, d6, d10\n+\tvnmls.f64\td6, d9, d12\n+\tvmla.f64\td1, d6, d4\n+\tvmla.f64\td5, d1, d15\n+\tvstr\td5, [r0, #8]\n+\tldr\tr2, [pc, #144]\t@ (4828 <__gridxc_gga_MOD_pw91xc+0xbc8>)\n+\tldr\tr3, [pc, #144]\t@ (482c <__gridxc_gga_MOD_pw91xc+0xbcc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #676]\t@ 0x2a4\n+\tldr\tr3, [sp, #684]\t@ 0x2ac\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t42ea <__gridxc_gga_MOD_pw91xc+0xab2>\n-\tadd.w\tsp, sp, #684\t@ 0x2ac\n+\tbne.n\t4818 <__gridxc_gga_MOD_pw91xc+0xbb8>\n+\tadd.w\tsp, sp, #692\t@ 0x2b4\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td17, [r3, #16]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r3]\n-\tvldr\td21, [r3, #8]\n-\tvmul.f64\td20, d16, d18\n-\tvmov.f64\td23, d17\n-\tvstr\td17, [sp, #152]\t@ 0x98\n-\tvmul.f64\td19, d22, d18\n-\tvldr\td9, [pc, #72]\t@ 42f0 <__gridxc_gga_MOD_pw91xc+0xab8>\n-\tvmul.f64\td17, d21, d18\n-\tvmov.f64\td24, d22\n-\tvstr\td22, [sp, #552]\t@ 0x228\n-\tvmul.f64\td18, d23, d18\n-\tvmaxnm.f64\td9, d16, d9\n-\tvmov.f64\td23, d19\n-\tvstr\td21, [sp, #560]\t@ 0x230\n-\tvmov.f64\td16, d17\n-\tvstr\td20, [sp, #456]\t@ 0x1c8\n-\tvstr\td20, [sp, #464]\t@ 0x1d0\n-\tvstr\td19, [sp, #624]\t@ 0x270\n-\tvstr\td19, [sp, #648]\t@ 0x288\n-\tvstr\td17, [sp, #632]\t@ 0x278\n-\tvstr\td17, [sp, #656]\t@ 0x290\n-\tvstr\td18, [sp, #640]\t@ 0x280\n-\tb.w\t38f6 <__gridxc_gga_MOD_pw91xc+0xbe>\n+\tvldr\td15, [pc, #104]\t@ 4820 <__gridxc_gga_MOD_pw91xc+0xbc0>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [r3, #16]\n+\tvldr\td4, [r3]\n+\tvmul.f64\td2, d7, d5\n+\tvcmpe.f64\td7, d15\n+\tvldr\td6, [r3, #8]\n+\tvmov.f64\td1, d3\n+\tvstr\td3, [sp, #200]\t@ 0xc8\n+\tvstr\td4, [sp, #560]\t@ 0x230\n+\tvmul.f64\td4, d4, d5\n+\tvstr\td6, [sp, #568]\t@ 0x238\n+\tvmul.f64\td6, d6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td5, d3, d5\n+\tvstr\td2, [sp, #464]\t@ 0x1d0\n+\tvstr\td2, [sp, #472]\t@ 0x1d8\n+\tvstr\td4, [sp, #632]\t@ 0x278\n+\tvstr\td4, [sp, #656]\t@ 0x290\n+\tit\tge\n+\tvmovge.f64\td15, d7\n+\tvstr\td6, [sp, #640]\t@ 0x280\n+\tvstr\td6, [sp, #664]\t@ 0x298\n+\tvstr\td5, [sp, #648]\t@ 0x288\n+\tb.w\t3d20 <__gridxc_gga_MOD_pw91xc+0xc0>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x0000008a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00004300 <__gridxc_gga_MOD_pbegcgxhegxc>:\n+00004830 <__gridxc_gga_MOD_pbegcgxhegxc>:\n __gridxc_gga_MOD_pbegcgxhegxc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #116]\t@ 4388 <__gridxc_gga_MOD_pbegcgxhegxc+0x88>\n+\tvldr\td7, [pc, #116]\t@ 48b8 <__gridxc_gga_MOD_pbegcgxhegxc+0x88>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #120]\t@ (43a0 <__gridxc_gga_MOD_pbegcgxhegxc+0xa0>)\n+\tldr\tr5, [pc, #120]\t@ (48d0 <__gridxc_gga_MOD_pbegcgxhegxc+0xa0>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #116]\t@ (43a4 <__gridxc_gga_MOD_pbegcgxhegxc+0xa4>)\n+\tldr\tr4, [pc, #116]\t@ (48d4 <__gridxc_gga_MOD_pbegcgxhegxc+0xa4>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #76]\t@ 4390 <__gridxc_gga_MOD_pbegcgxhegxc+0x90>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #76]\t@ 48c0 <__gridxc_gga_MOD_pbegcgxhegxc+0x90>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #64]\t@ 4398 <__gridxc_gga_MOD_pbegcgxhegxc+0x98>\n+\tvldr\td7, [pc, #64]\t@ 48c8 <__gridxc_gga_MOD_pbegcgxhegxc+0x98>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #60]\t@ (43a8 <__gridxc_gga_MOD_pbegcgxhegxc+0xa8>)\n-\tldr\tr3, [pc, #56]\t@ (43a4 <__gridxc_gga_MOD_pbegcgxhegxc+0xa4>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #60]\t@ (48d8 <__gridxc_gga_MOD_pbegcgxhegxc+0xa8>)\n+\tldr\tr3, [pc, #56]\t@ (48d4 <__gridxc_gga_MOD_pbegcgxhegxc+0xa4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t4380 <__gridxc_gga_MOD_pbegcgxhegxc+0x80>\n+\tbne.n\t48b0 <__gridxc_gga_MOD_pbegcgxhegxc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop.w\n \t.word\t0xbcd35a86\n \t.word\t0x3fb114e3\n@@ -4919,65 +5279,65 @@\n \t.word\t0x0000006c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000038\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000043ac <__gridxc_gga_MOD_pbegcgxloxc>:\n+000048dc <__gridxc_gga_MOD_pbegcgxloxc>:\n __gridxc_gga_MOD_pbegcgxloxc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 4430 <__gridxc_gga_MOD_pbegcgxloxc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4960 <__gridxc_gga_MOD_pbegcgxloxc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (4448 <__gridxc_gga_MOD_pbegcgxloxc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4978 <__gridxc_gga_MOD_pbegcgxloxc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (444c <__gridxc_gga_MOD_pbegcgxloxc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (497c <__gridxc_gga_MOD_pbegcgxloxc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 4438 <__gridxc_gga_MOD_pbegcgxloxc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4968 <__gridxc_gga_MOD_pbegcgxloxc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 4440 <__gridxc_gga_MOD_pbegcgxloxc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4970 <__gridxc_gga_MOD_pbegcgxloxc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (4450 <__gridxc_gga_MOD_pbegcgxloxc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (444c <__gridxc_gga_MOD_pbegcgxloxc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4980 <__gridxc_gga_MOD_pbegcgxloxc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (497c <__gridxc_gga_MOD_pbegcgxloxc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t442c <__gridxc_gga_MOD_pbegcgxloxc+0x80>\n+\tbne.n\t495c <__gridxc_gga_MOD_pbegcgxloxc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xbcd35a86\n \t.word\t0x3fb114e3\n \t.word\t0x3c0ca458\n@@ -4987,65 +5347,65 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00004454 <__gridxc_gga_MOD_pbejsjrhegxc>:\n+00004984 <__gridxc_gga_MOD_pbejsjrhegxc>:\n __gridxc_gga_MOD_pbejsjrhegxc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 44d8 <__gridxc_gga_MOD_pbejsjrhegxc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4a08 <__gridxc_gga_MOD_pbejsjrhegxc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (44f0 <__gridxc_gga_MOD_pbejsjrhegxc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4a20 <__gridxc_gga_MOD_pbejsjrhegxc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (44f4 <__gridxc_gga_MOD_pbejsjrhegxc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (4a24 <__gridxc_gga_MOD_pbejsjrhegxc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 44e0 <__gridxc_gga_MOD_pbejsjrhegxc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4a10 <__gridxc_gga_MOD_pbejsjrhegxc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 44e8 <__gridxc_gga_MOD_pbejsjrhegxc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4a18 <__gridxc_gga_MOD_pbejsjrhegxc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (44f8 <__gridxc_gga_MOD_pbejsjrhegxc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (44f4 <__gridxc_gga_MOD_pbejsjrhegxc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4a28 <__gridxc_gga_MOD_pbejsjrhegxc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (4a24 <__gridxc_gga_MOD_pbejsjrhegxc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t44d4 <__gridxc_gga_MOD_pbejsjrhegxc+0x80>\n+\tbne.n\t4a04 <__gridxc_gga_MOD_pbejsjrhegxc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xdf3b645a\n \t.word\t0x3fa78d4f\n \t.word\t0x0cf986c8\n@@ -5055,65 +5415,65 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000044fc <__gridxc_gga_MOD_pbejsjrloxc>:\n+00004a2c <__gridxc_gga_MOD_pbejsjrloxc>:\n __gridxc_gga_MOD_pbejsjrloxc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 4580 <__gridxc_gga_MOD_pbejsjrloxc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4ab0 <__gridxc_gga_MOD_pbejsjrloxc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (4598 <__gridxc_gga_MOD_pbejsjrloxc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4ac8 <__gridxc_gga_MOD_pbejsjrloxc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (459c <__gridxc_gga_MOD_pbejsjrloxc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (4acc <__gridxc_gga_MOD_pbejsjrloxc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 4588 <__gridxc_gga_MOD_pbejsjrloxc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4ab8 <__gridxc_gga_MOD_pbejsjrloxc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 4590 <__gridxc_gga_MOD_pbejsjrloxc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4ac0 <__gridxc_gga_MOD_pbejsjrloxc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (45a0 <__gridxc_gga_MOD_pbejsjrloxc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (459c <__gridxc_gga_MOD_pbejsjrloxc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4ad0 <__gridxc_gga_MOD_pbejsjrloxc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (4acc <__gridxc_gga_MOD_pbejsjrloxc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t457c <__gridxc_gga_MOD_pbejsjrloxc+0x80>\n+\tbne.n\t4aac <__gridxc_gga_MOD_pbejsjrloxc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xdf3b645a\n \t.word\t0x3fa78d4f\n \t.word\t0x0cf986c8\n@@ -5123,65 +5483,65 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000045a4 <__gridxc_gga_MOD_pbesolxc>:\n+00004ad4 <__gridxc_gga_MOD_pbesolxc>:\n __gridxc_gga_MOD_pbesolxc.localalias():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 4628 <__gridxc_gga_MOD_pbesolxc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4b58 <__gridxc_gga_MOD_pbesolxc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (4640 <__gridxc_gga_MOD_pbesolxc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4b70 <__gridxc_gga_MOD_pbesolxc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (4644 <__gridxc_gga_MOD_pbesolxc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (4b74 <__gridxc_gga_MOD_pbesolxc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 4630 <__gridxc_gga_MOD_pbesolxc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4b60 <__gridxc_gga_MOD_pbesolxc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 4638 <__gridxc_gga_MOD_pbesolxc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4b68 <__gridxc_gga_MOD_pbesolxc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (4648 <__gridxc_gga_MOD_pbesolxc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (4644 <__gridxc_gga_MOD_pbesolxc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4b78 <__gridxc_gga_MOD_pbesolxc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (4b74 <__gridxc_gga_MOD_pbesolxc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t4624 <__gridxc_gga_MOD_pbesolxc+0x80>\n+\tbne.n\t4b54 <__gridxc_gga_MOD_pbesolxc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xdf3b645a\n \t.word\t0x3fa78d4f\n \t.word\t0x3c0ca458\n@@ -5191,65 +5551,65 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000464c <__gridxc_gga_MOD_revpbexc>:\n+00004b7c <__gridxc_gga_MOD_revpbexc>:\n __gridxc_gga_MOD_revpbexc():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 46d0 <__gridxc_gga_MOD_revpbexc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4c00 <__gridxc_gga_MOD_revpbexc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (46e8 <__gridxc_gga_MOD_revpbexc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4c18 <__gridxc_gga_MOD_revpbexc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (46ec <__gridxc_gga_MOD_revpbexc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (4c1c <__gridxc_gga_MOD_revpbexc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 46d8 <__gridxc_gga_MOD_revpbexc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4c08 <__gridxc_gga_MOD_revpbexc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 46e0 <__gridxc_gga_MOD_revpbexc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4c10 <__gridxc_gga_MOD_revpbexc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (46f0 <__gridxc_gga_MOD_revpbexc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (46ec <__gridxc_gga_MOD_revpbexc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4c20 <__gridxc_gga_MOD_revpbexc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (4c1c <__gridxc_gga_MOD_revpbexc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t46cc <__gridxc_gga_MOD_revpbexc+0x80>\n+\tbne.n\t4bfc <__gridxc_gga_MOD_revpbexc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xbcd35a86\n \t.word\t0x3fb114e3\n \t.word\t0x7576bfc1\n@@ -5259,65 +5619,65 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000046f4 <__gridxc_gga_MOD_pbexc>:\n+00004c24 <__gridxc_gga_MOD_pbexc>:\n __gridxc_gga_MOD_pbexc():\n \tpush\t{r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #76\t@ 0x4c\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #112]\t@ 4778 <__gridxc_gga_MOD_pbexc+0x84>\n+\tvldr\td7, [pc, #112]\t@ 4ca8 <__gridxc_gga_MOD_pbexc+0x84>\n \tmov\tr3, r0\n \tadd\tr0, sp, #40\t@ 0x28\n \tldr\tr4, [sp, #88]\t@ 0x58\n \tstr\tr4, [sp, #12]\n \tmov\tr4, r1\n \tmov\tr1, r2\n \tstrd\tr1, r5, [sp, #4]\n-\tldr\tr5, [pc, #116]\t@ (4790 <__gridxc_gga_MOD_pbexc+0x9c>)\n+\tldr\tr5, [pc, #116]\t@ (4cc0 <__gridxc_gga_MOD_pbexc+0x9c>)\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr4, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n-\tldr\tr4, [pc, #112]\t@ (4794 <__gridxc_gga_MOD_pbexc+0xa0>)\n+\tldr\tr4, [pc, #112]\t@ (4cc4 <__gridxc_gga_MOD_pbexc+0xa0>)\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #68]\t@ 0x44\n \tmov.w\tr4, #0\n \tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #72]\t@ 4780 <__gridxc_gga_MOD_pbexc+0x8c>\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [pc, #72]\t@ 4cb0 <__gridxc_gga_MOD_pbexc+0x8c>\n \tstr\tr4, [sp, #16]\n \tldr\tr4, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #20]\n \tldr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #24]\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #104]\t@ 0x68\n-\tvldr\td16, [pc, #60]\t@ 4788 <__gridxc_gga_MOD_pbexc+0x94>\n+\tvldr\td7, [pc, #60]\t@ 4cb8 <__gridxc_gga_MOD_pbexc+0x94>\n \tstr\tr4, [sp, #28]\n \tldr\tr4, [sp, #108]\t@ 0x6c\n \tstr\tr4, [sp, #32]\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tldr\tr2, [pc, #56]\t@ (4798 <__gridxc_gga_MOD_pbexc+0xa4>)\n-\tldr\tr3, [pc, #52]\t@ (4794 <__gridxc_gga_MOD_pbexc+0xa0>)\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tldr\tr2, [pc, #56]\t@ (4cc8 <__gridxc_gga_MOD_pbexc+0xa4>)\n+\tldr\tr3, [pc, #52]\t@ (4cc4 <__gridxc_gga_MOD_pbexc+0xa0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t4774 <__gridxc_gga_MOD_pbexc+0x80>\n+\tbne.n\t4ca4 <__gridxc_gga_MOD_pbexc+0x80>\n \tadd\tsp, #76\t@ 0x4c\n \tpop\t{r4, r5, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0xbcd35a86\n \t.word\t0x3fb114e3\n \t.word\t0x7576bfc1\n@@ -5327,1916 +5687,1927 @@\n \t.word\t0x00000068\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000479c <__gridxc_gga_MOD_ggaxc>:\n+00004ccc <__gridxc_gga_MOD_ggaxc>:\n __gridxc_gga_MOD_ggaxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3576]\t@ 0xdf8\n-\tsub\tsp, #420\t@ 0x1a4\n+\tstr.w\tr0, [ip, #3560]\t@ 0xde8\n+\tsub\tsp, #436\t@ 0x1b4\n \tadd\tr7, sp, #40\t@ 0x28\n \tldr\tr6, [r2, #0]\n-\tldr.w\tr2, [pc, #2400]\t@ 5118 <__gridxc_gga_MOD_ggaxc+0x97c>\n-\tstr\tr1, [r7, #52]\t@ 0x34\n-\tldr.w\tr1, [pc, #2396]\t@ 511c <__gridxc_gga_MOD_ggaxc+0x980>\n-\tldrd\tr8, r4, [r7, #480]\t@ 0x1e0\n+\tldr.w\tr2, [pc, #2400]\t@ 5648 <__gridxc_gga_MOD_ggaxc+0x97c>\n+\tmov\tr9, r0\n+\tstr\tr1, [r7, #60]\t@ 0x3c\n+\tldr.w\tr1, [pc, #2396]\t@ 564c <__gridxc_gga_MOD_ggaxc+0x980>\n+\tldrd\tfp, r4, [r7, #496]\t@ 0x1f0\n \tadd\tr1, pc\n-\tstr\tr4, [r7, #64]\t@ 0x40\n-\tstr\tr0, [r7, #60]\t@ 0x3c\n-\tldr.w\tfp, [r7, #492]\t@ 0x1ec\n+\tstr\tr4, [r7, #72]\t@ 0x48\n+\tldrd\tsl, r4, [r7, #512]\t@ 0x200\n \tldr\tr2, [r1, r2]\n \tadd.w\tr1, r6, r6, lsl #1\n-\tldrd\tsl, r4, [r7, #496]\t@ 0x1f0\n \tbic.w\tr1, r1, r1, asr #31\n \tldr\tr2, [r2, #0]\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n+\tstr.w\tr2, [r7, #388]\t@ 0x184\n \tmov.w\tr2, #0\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n \tlsls\tr1, r1, #3\n-\tstr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr2, [r7, #64]\t@ 0x40\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n+\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n \tbic.w\tr0, r0, #15\n+\tstr\tr2, [r7, #68]\t@ 0x44\n \tsub.w\tip, sp, r0\n-\tldr.w\tr0, [r7, #512]\t@ 0x200\n-\tstr\tr0, [r7, #48]\t@ 0x30\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tstr\tr0, [r7, #68]\t@ 0x44\n-\tldr.w\tr0, [pc, #2328]\t@ 5120 <__gridxc_gga_MOD_ggaxc+0x984>\n-\tldrd\tr5, r2, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr0, [r7, #528]\t@ 0x210\n+\tstr\tr0, [r7, #56]\t@ 0x38\n+\tldr.w\tr0, [r7, #532]\t@ 0x214\n+\tstr\tr0, [r7, #80]\t@ 0x50\n+\tldr.w\tr0, [pc, #2324]\t@ 5650 <__gridxc_gga_MOD_ggaxc+0x984>\n+\tldrd\tr5, r2, [r7, #520]\t@ 0x208\n \tadd\tr0, pc\n-\tstr\tr0, [r7, #44]\t@ 0x2c\n+\tstr\tr0, [r7, #52]\t@ 0x34\n \tmov\tr0, ip\n \tmov\tip, sp\n \tcmp\tip, r0\n-\tbeq.n\t4828 <__gridxc_gga_MOD_ggaxc+0x8c>\n+\tbeq.n\t4d5a <__gridxc_gga_MOD_ggaxc+0x8e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tip, sp\n \tcmp\tip, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t481a <__gridxc_gga_MOD_ggaxc+0x7e>\n+\tbne.n\t4d4c <__gridxc_gga_MOD_ggaxc+0x80>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t4a32 <__gridxc_gga_MOD_ggaxc+0x296>\n+\tbne.w\t4f62 <__gridxc_gga_MOD_ggaxc+0x296>\n \tbic.w\tr1, r6, r6, asr #31\n \tmov\tip, sp\n-\tadd.w\tr9, sp, #40\t@ 0x28\n+\tadd.w\tr8, sp, #40\t@ 0x28\n \tlsls\tr1, r1, #3\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n \tcmp\tip, r0\n-\tbeq.n\t4860 <__gridxc_gga_MOD_ggaxc+0xc4>\n+\tbeq.n\t4d92 <__gridxc_gga_MOD_ggaxc+0xc6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tip, sp\n \tcmp\tip, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4852 <__gridxc_gga_MOD_ggaxc+0xb6>\n+\tbne.n\t4d84 <__gridxc_gga_MOD_ggaxc+0xb8>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t5772 <__gridxc_gga_MOD_ggaxc+0xfd6>\n+\tbne.w\t5cc6 <__gridxc_gga_MOD_ggaxc+0xffa>\n \tadd\tr1, sp, #40\t@ 0x28\n \tcmp\tr6, #4\n-\tstr\tr1, [r7, #8]\n-\tbeq.w\t4eee <__gridxc_gga_MOD_ggaxc+0x752>\n+\tstr\tr1, [r7, #28]\n+\tbeq.w\t5402 <__gridxc_gga_MOD_ggaxc+0x736>\n \tsubs\tr1, r6, #1\n \tcmp\tr1, #1\n-\tbls.w\t509c <__gridxc_gga_MOD_ggaxc+0x900>\n-\tldr.w\tr3, [pc, #2208]\t@ 5124 <__gridxc_gga_MOD_ggaxc+0x988>\n+\tbls.w\t55ae <__gridxc_gga_MOD_ggaxc+0x8e2>\n+\tldr.w\tr3, [pc, #2208]\t@ 5654 <__gridxc_gga_MOD_ggaxc+0x988>\n \tmovs\tr1, #36\t@ 0x24\n-\tstr\tr2, [r7, #40]\t@ 0x28\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr.w\tr0, [pc, #2204]\t@ 5128 <__gridxc_gga_MOD_ggaxc+0x98c>\n+\tstr\tr2, [r7, #48]\t@ 0x30\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tldr.w\tr0, [pc, #2200]\t@ 5658 <__gridxc_gga_MOD_ggaxc+0x98c>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [r7, #40]\t@ 0x28\n+\tldr\tr2, [r7, #48]\t@ 0x30\n \tcmp\tr2, #0\n-\tbeq.w\t4a3a <__gridxc_gga_MOD_ggaxc+0x29e>\n+\tbeq.w\t4f6a <__gridxc_gga_MOD_ggaxc+0x29e>\n \tldr\tr3, [r2, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t4a3a <__gridxc_gga_MOD_ggaxc+0x29e>\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tldr\tr2, [r7, #48]\t@ 0x30\n+\tbeq.w\t4f6a <__gridxc_gga_MOD_ggaxc+0x29e>\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tldr\tr2, [r7, #80]\t@ 0x50\n \tcmp\tr2, #0\n \tit\tne\n \tcmpne\tr3, #0\n-\tbne.n\t48c6 <__gridxc_gga_MOD_ggaxc+0x12a>\n-\tldr.w\tr3, [pc, #2160]\t@ 5124 <__gridxc_gga_MOD_ggaxc+0x988>\n+\tbne.n\t4df8 <__gridxc_gga_MOD_ggaxc+0x12c>\n+\tldr.w\tr3, [pc, #2156]\t@ 5654 <__gridxc_gga_MOD_ggaxc+0x988>\n \tmovs\tr1, #31\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr.w\tr0, [pc, #2160]\t@ 512c <__gridxc_gga_MOD_ggaxc+0x990>\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tldr.w\tr0, [pc, #2156]\t@ 565c <__gridxc_gga_MOD_ggaxc+0x990>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvldr\td15, [r7, #328]\t@ 0x148\n+\tvldr\td9, [r7, #344]\t@ 0x158\n \tcmp\tr6, #1\n-\tvldr\td14, [r7, #320]\t@ 0x140\n-\tvldr\td13, [r7, #336]\t@ 0x150\n-\tvmul.f64\td16, d15, d15\n-\tvfma.f64\td16, d14, d14\n-\tvfma.f64\td16, d13, d13\n-\tvstr\td16, [r7, #200]\t@ 0xc8\n-\tbeq.w\t5458 <__gridxc_gga_MOD_ggaxc+0xcbc>\n-\tvldr\td16, [r7, #352]\t@ 0x160\n-\tvldr\td20, [r7, #344]\t@ 0x158\n-\tvldr\td19, [r7, #360]\t@ 0x168\n-\tvmul.f64\td18, d15, d16\n-\tvmul.f64\td16, d16, d16\n-\tvfma.f64\td18, d14, d20\n-\tvfma.f64\td16, d20, d20\n-\tldr\tr0, [r7, #68]\t@ 0x44\n-\tvfma.f64\td18, d19, d13\n-\tvfma.f64\td16, d19, d19\n-\tvstr\td18, [r7, #208]\t@ 0xd0\n-\tvstr\td16, [r7, #216]\t@ 0xd8\n+\tvldr\td8, [r7, #336]\t@ 0x150\n+\tvldr\td10, [r7, #352]\t@ 0x160\n+\tvmul.f64\td7, d9, d9\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tvmla.f64\td7, d8, d8\n+\tvmla.f64\td7, d10, d10\n+\tvstr\td7, [r7, #216]\t@ 0xd8\n+\tbeq.w\t599c <__gridxc_gga_MOD_ggaxc+0xcd0>\n+\tvldr\td4, [r7, #360]\t@ 0x168\n+\tvldr\td7, [r7, #368]\t@ 0x170\n+\tvldr\td5, [r7, #376]\t@ 0x178\n+\tvmul.f64\td6, d8, d4\n+\tvmla.f64\td6, d9, d7\n+\tvmul.f64\td7, d7, d7\n+\tvmla.f64\td7, d4, d4\n+\tvmla.f64\td6, d5, d10\n+\tvmla.f64\td7, d5, d5\n+\tvstr\td6, [r7, #224]\t@ 0xe0\n+\tvstr\td7, [r7, #232]\t@ 0xe8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n \tcmp\tr0, #2\n-\tbeq.w\t556e <__gridxc_gga_MOD_ggaxc+0xdd2>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tbeq.w\t5ab0 <__gridxc_gga_MOD_ggaxc+0xde4>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n \tcmp\tr0, #32\n-\tbeq.w\t58a8 <__gridxc_gga_MOD_ggaxc+0x110c>\n-\tldr.w\tr3, [pc, #2036]\t@ 5124 <__gridxc_gga_MOD_ggaxc+0x988>\n+\tbeq.w\t5e24 <__gridxc_gga_MOD_ggaxc+0x1158>\n+\tldr.w\tr3, [pc, #2036]\t@ 5654 <__gridxc_gga_MOD_ggaxc+0x988>\n \tmovs\tr1, #30\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr.w\tr0, [pc, #2040]\t@ 5130 <__gridxc_gga_MOD_ggaxc+0x994>\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tadd.w\tfp, r7, #136\t@ 0x88\n+\tldr.w\tr0, [pc, #2036]\t@ 5660 <__gridxc_gga_MOD_ggaxc+0x994>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tldr\tr0, [r7, #80]\t@ 0x50\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tldr\tr3, [r7, #8]\n-\tldr.w\tr1, [pc, #2024]\t@ 5134 <__gridxc_gga_MOD_ggaxc+0x998>\n-\tmov\tr8, r0\n+\tldr\tr3, [r7, #28]\n+\tldr.w\tr1, [pc, #2020]\t@ 5664 <__gridxc_gga_MOD_ggaxc+0x998>\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr.w\tr8, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #176\t@ 0xb0\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tadd.w\tr8, r7, #120\t@ 0x78\n-\tstr\tr3, [sp, #8]\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tadd.w\tr3, r7, #192\t@ 0xc0\n \tadd\tr1, pc\n-\tadd.w\tr3, r7, #200\t@ 0xc8\n-\tstr.w\tr8, [sp]\n+\tstr\tr3, [sp, #8]\n+\tstr.w\tfp, [sp]\n+\tadd.w\tr3, r7, #216\t@ 0xd8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n \tcmp\tr6, #1\n-\tbeq.w\t54a2 <__gridxc_gga_MOD_ggaxc+0xd06>\n-\tvldr\td18, [r7, #176]\t@ 0xb0\n-\tvldr\td19, [r7, #192]\t@ 0xc0\n-\tvldr\td16, [r7, #184]\t@ 0xb8\n-\tvadd.f64\td18, d18, d18\n-\tvldr\td27, [r7, #344]\t@ 0x158\n-\tvadd.f64\td19, d19, d19\n-\tvldr\td26, [r7, #352]\t@ 0x160\n-\tvldr\td25, [r7, #360]\t@ 0x168\n-\tvmul.f64\td22, d16, d14\n-\tvmul.f64\td24, d16, d27\n-\tvmul.f64\td21, d16, d15\n-\tvmul.f64\td23, d16, d26\n-\tvfma.f64\td24, d18, d14\n-\tvmul.f64\td28, d25, d16\n-\tvmul.f64\td16, d16, d13\n-\tvfma.f64\td23, d18, d15\n-\tvfma.f64\td28, d18, d13\n-\tvfma.f64\td22, d19, d27\n-\tvfma.f64\td21, d19, d26\n-\tvfma.f64\td16, d25, d19\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tvldr\td20, [r8]\n-\tcmp\tr3, #1\n-\tvstr\td24, [r9]\n-\tvstr\td23, [r9, #8]\n-\tvstr\td28, [r9, #16]\n-\tvstr\td22, [r9, #24]\n-\tvstr\td21, [r9, #32]\n-\tvstr\td16, [r9, #40]\t@ 0x28\n-\tbeq.w\t55a4 <__gridxc_gga_MOD_ggaxc+0xe08>\n-\tcmp\tr3, #0\n-\tbne.w\t565c <__gridxc_gga_MOD_ggaxc+0xec0>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tbeq.w\t59de <__gridxc_gga_MOD_ggaxc+0xd12>\n+\tvldr\td4, [r7, #192]\t@ 0xc0\n+\tcmp.w\tr9, #1\n+\tvldr\td6, [r7, #200]\t@ 0xc8\n+\tvldr\td2, [r7, #360]\t@ 0x168\n+\tvadd.f64\td4, d4, d4\n+\tvldr\td1, [r7, #368]\t@ 0x170\n+\tvldr\td5, [r7, #208]\t@ 0xd0\n+\tvldr\td0, [r7, #376]\t@ 0x178\n+\tvldr\td7, [fp]\n+\tvmul.f64\td3, d4, d8\n+\tvadd.f64\td5, d5, d5\n+\tvmla.f64\td3, d6, d2\n+\tvmul.f64\td2, d5, d2\n+\tvmla.f64\td2, d6, d8\n+\tvstr\td3, [r8]\n+\tvmul.f64\td3, d4, d9\n+\tvmla.f64\td3, d6, d1\n+\tvmul.f64\td1, d5, d1\n+\tvmla.f64\td1, d6, d9\n+\tvstr\td2, [r8, #24]\n+\tvstr\td3, [r8, #8]\n+\tvmul.f64\td3, d0, d6\n+\tvmul.f64\td6, d6, d10\n+\tvmla.f64\td3, d4, d10\n+\tvmla.f64\td6, d0, d5\n+\tvstr\td1, [r8, #32]\n+\tvstr\td3, [r8, #16]\n+\tvstr\td6, [r8, #40]\t@ 0x28\n+\tbeq.w\t5ae0 <__gridxc_gga_MOD_ggaxc+0xe14>\n+\tcmp.w\tr9, #0\n+\tbne.w\t5ba2 <__gridxc_gga_MOD_ggaxc+0xed6>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr6, #0\n-\tvstr\td20, [r3]\n-\tbgt.w\t54d8 <__gridxc_gga_MOD_ggaxc+0xd3c>\n-\tldr\tr1, [r7, #56]\t@ 0x38\n+\tvstr\td7, [r3]\n+\tbgt.w\t5a16 <__gridxc_gga_MOD_ggaxc+0xd4a>\n+\tldr\tr1, [r7, #64]\t@ 0x40\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tldr.w\tr2, [pc, #1836]\t@ 5138 <__gridxc_gga_MOD_ggaxc+0x99c>\n-\tldr.w\tr3, [pc, #1800]\t@ 5118 <__gridxc_gga_MOD_ggaxc+0x97c>\n+\tldr.w\tr2, [pc, #1836]\t@ 5668 <__gridxc_gga_MOD_ggaxc+0x99c>\n+\tldr.w\tr3, [pc, #1800]\t@ 5648 <__gridxc_gga_MOD_ggaxc+0x97c>\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #372]\t@ 0x174\n+\tldr.w\tr3, [r7, #388]\t@ 0x184\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t59b8 <__gridxc_gga_MOD_ggaxc+0x121c>\n-\tadd.w\tr7, r7, #380\t@ 0x17c\n+\tbne.w\t5f2e <__gridxc_gga_MOD_ggaxc+0x1262>\n+\tadd.w\tr7, r7, #396\t@ 0x18c\n \tmov\tsp, r7\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tb.n\t4836 <__gridxc_gga_MOD_ggaxc+0x9a>\n-\tldr.w\tr3, [pc, #1792]\t@ 513c <__gridxc_gga_MOD_ggaxc+0x9a0>\n+\tb.n\t4d68 <__gridxc_gga_MOD_ggaxc+0x9c>\n+\tldr.w\tr3, [pc, #1792]\t@ 566c <__gridxc_gga_MOD_ggaxc+0x9a0>\n \tmovs\tr2, #3\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4df2 <__gridxc_gga_MOD_ggaxc+0x656>\n-\tldr.w\tr3, [pc, #1768]\t@ 5140 <__gridxc_gga_MOD_ggaxc+0x9a4>\n+\tbeq.w\t52fa <__gridxc_gga_MOD_ggaxc+0x62e>\n+\tldr.w\tr3, [pc, #1772]\t@ 5670 <__gridxc_gga_MOD_ggaxc+0x9a4>\n \tmovs\tr2, #3\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4df2 <__gridxc_gga_MOD_ggaxc+0x656>\n-\tldr.w\tr3, [pc, #1748]\t@ 5144 <__gridxc_gga_MOD_ggaxc+0x9a8>\n+\tbeq.w\t52fa <__gridxc_gga_MOD_ggaxc+0x62e>\n+\tldr.w\tr3, [pc, #1752]\t@ 5674 <__gridxc_gga_MOD_ggaxc+0x9a8>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5424 <__gridxc_gga_MOD_ggaxc+0xc88>\n-\tldr.w\tr3, [pc, #1728]\t@ 5148 <__gridxc_gga_MOD_ggaxc+0x9ac>\n+\tbeq.w\t5968 <__gridxc_gga_MOD_ggaxc+0xc9c>\n+\tldr.w\tr3, [pc, #1732]\t@ 5678 <__gridxc_gga_MOD_ggaxc+0x9ac>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5424 <__gridxc_gga_MOD_ggaxc+0xc88>\n-\tldr.w\tr3, [pc, #1708]\t@ 514c <__gridxc_gga_MOD_ggaxc+0x9b0>\n+\tbeq.w\t5968 <__gridxc_gga_MOD_ggaxc+0xc9c>\n+\tldr.w\tr3, [pc, #1712]\t@ 567c <__gridxc_gga_MOD_ggaxc+0x9b0>\n \tmovs\tr2, #2\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t577c <__gridxc_gga_MOD_ggaxc+0xfe0>\n-\tldr.w\tr3, [pc, #1688]\t@ 5150 <__gridxc_gga_MOD_ggaxc+0x9b4>\n+\tbeq.w\t5cd0 <__gridxc_gga_MOD_ggaxc+0x1004>\n+\tldr.w\tr3, [pc, #1692]\t@ 5680 <__gridxc_gga_MOD_ggaxc+0x9b4>\n \tmovs\tr2, #2\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t577c <__gridxc_gga_MOD_ggaxc+0xfe0>\n-\tldr.w\tr3, [pc, #1668]\t@ 5154 <__gridxc_gga_MOD_ggaxc+0x9b8>\n+\tbeq.w\t5cd0 <__gridxc_gga_MOD_ggaxc+0x1004>\n+\tldr.w\tr3, [pc, #1672]\t@ 5684 <__gridxc_gga_MOD_ggaxc+0x9b8>\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t591a <__gridxc_gga_MOD_ggaxc+0x117e>\n-\tldr.w\tr3, [pc, #1648]\t@ 5158 <__gridxc_gga_MOD_ggaxc+0x9bc>\n+\tbeq.w\t5e90 <__gridxc_gga_MOD_ggaxc+0x11c4>\n+\tldr.w\tr3, [pc, #1652]\t@ 5688 <__gridxc_gga_MOD_ggaxc+0x9bc>\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t591a <__gridxc_gga_MOD_ggaxc+0x117e>\n-\tldr.w\tr3, [pc, #1628]\t@ 515c <__gridxc_gga_MOD_ggaxc+0x9c0>\n+\tbeq.w\t5e90 <__gridxc_gga_MOD_ggaxc+0x11c4>\n+\tldr.w\tr3, [pc, #1632]\t@ 568c <__gridxc_gga_MOD_ggaxc+0x9c0>\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t591a <__gridxc_gga_MOD_ggaxc+0x117e>\n-\tldr.w\tr3, [pc, #1608]\t@ 5160 <__gridxc_gga_MOD_ggaxc+0x9c4>\n+\tbeq.w\t5e90 <__gridxc_gga_MOD_ggaxc+0x11c4>\n+\tldr.w\tr3, [pc, #1612]\t@ 5690 <__gridxc_gga_MOD_ggaxc+0x9c4>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5986 <__gridxc_gga_MOD_ggaxc+0x11ea>\n-\tldr.w\tr3, [pc, #1588]\t@ 5164 <__gridxc_gga_MOD_ggaxc+0x9c8>\n+\tbeq.w\t5efc <__gridxc_gga_MOD_ggaxc+0x1230>\n+\tldr.w\tr3, [pc, #1592]\t@ 5694 <__gridxc_gga_MOD_ggaxc+0x9c8>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5986 <__gridxc_gga_MOD_ggaxc+0x11ea>\n-\tldr.w\tr3, [pc, #1568]\t@ 5168 <__gridxc_gga_MOD_ggaxc+0x9cc>\n+\tbeq.w\t5efc <__gridxc_gga_MOD_ggaxc+0x1230>\n+\tldr.w\tr3, [pc, #1572]\t@ 5698 <__gridxc_gga_MOD_ggaxc+0x9cc>\n \tmovs\tr2, #3\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5986 <__gridxc_gga_MOD_ggaxc+0x11ea>\n-\tldr.w\tr3, [pc, #1548]\t@ 516c <__gridxc_gga_MOD_ggaxc+0x9d0>\n+\tbeq.w\t5efc <__gridxc_gga_MOD_ggaxc+0x1230>\n+\tldr.w\tr3, [pc, #1552]\t@ 569c <__gridxc_gga_MOD_ggaxc+0x9d0>\n \tmovs\tr2, #3\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5986 <__gridxc_gga_MOD_ggaxc+0x11ea>\n-\tldr.w\tr3, [pc, #1528]\t@ 5170 <__gridxc_gga_MOD_ggaxc+0x9d4>\n+\tbeq.w\t5efc <__gridxc_gga_MOD_ggaxc+0x1230>\n+\tldr.w\tr3, [pc, #1532]\t@ 56a0 <__gridxc_gga_MOD_ggaxc+0x9d4>\n \tmovs\tr2, #4\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b9c <__gridxc_gga_MOD_ggaxc+0x1400>\n-\tldr.w\tr3, [pc, #1504]\t@ 5174 <__gridxc_gga_MOD_ggaxc+0x9d8>\n+\tbeq.w\t610a <__gridxc_gga_MOD_ggaxc+0x143e>\n+\tldr.w\tr3, [pc, #1512]\t@ 56a4 <__gridxc_gga_MOD_ggaxc+0x9d8>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b9c <__gridxc_gga_MOD_ggaxc+0x1400>\n-\tldr.w\tr3, [pc, #1484]\t@ 5178 <__gridxc_gga_MOD_ggaxc+0x9dc>\n+\tbeq.w\t610a <__gridxc_gga_MOD_ggaxc+0x143e>\n+\tldr.w\tr3, [pc, #1492]\t@ 56a8 <__gridxc_gga_MOD_ggaxc+0x9dc>\n \tmovs\tr2, #6\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b66 <__gridxc_gga_MOD_ggaxc+0x13ca>\n-\tldr.w\tr3, [pc, #1460]\t@ 517c <__gridxc_gga_MOD_ggaxc+0x9e0>\n+\tbeq.w\t60d4 <__gridxc_gga_MOD_ggaxc+0x1408>\n+\tldr.w\tr3, [pc, #1472]\t@ 56ac <__gridxc_gga_MOD_ggaxc+0x9e0>\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b66 <__gridxc_gga_MOD_ggaxc+0x13ca>\n-\tldr.w\tr3, [pc, #1440]\t@ 5180 <__gridxc_gga_MOD_ggaxc+0x9e4>\n+\tbeq.w\t60d4 <__gridxc_gga_MOD_ggaxc+0x1408>\n+\tldr.w\tr3, [pc, #1452]\t@ 56b0 <__gridxc_gga_MOD_ggaxc+0x9e4>\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b66 <__gridxc_gga_MOD_ggaxc+0x13ca>\n-\tldr.w\tr3, [pc, #1420]\t@ 5184 <__gridxc_gga_MOD_ggaxc+0x9e8>\n+\tbeq.w\t60d4 <__gridxc_gga_MOD_ggaxc+0x1408>\n+\tldr.w\tr3, [pc, #1432]\t@ 56b4 <__gridxc_gga_MOD_ggaxc+0x9e8>\n \tmovs\tr2, #4\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b30 <__gridxc_gga_MOD_ggaxc+0x1394>\n-\tldr.w\tr3, [pc, #1396]\t@ 5188 <__gridxc_gga_MOD_ggaxc+0x9ec>\n+\tbeq.w\t609e <__gridxc_gga_MOD_ggaxc+0x13d2>\n+\tldr.w\tr3, [pc, #1412]\t@ 56b8 <__gridxc_gga_MOD_ggaxc+0x9ec>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5b30 <__gridxc_gga_MOD_ggaxc+0x1394>\n-\tldr.w\tr3, [pc, #1376]\t@ 518c <__gridxc_gga_MOD_ggaxc+0x9f0>\n+\tbeq.w\t609e <__gridxc_gga_MOD_ggaxc+0x13d2>\n+\tldr.w\tr3, [pc, #1392]\t@ 56bc <__gridxc_gga_MOD_ggaxc+0x9f0>\n \tmovs\tr2, #9\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5afa <__gridxc_gga_MOD_ggaxc+0x135e>\n-\tldr.w\tr3, [pc, #1352]\t@ 5190 <__gridxc_gga_MOD_ggaxc+0x9f4>\n+\tbeq.w\t6068 <__gridxc_gga_MOD_ggaxc+0x139c>\n+\tldr.w\tr3, [pc, #1372]\t@ 56c0 <__gridxc_gga_MOD_ggaxc+0x9f4>\n \tmovs\tr2, #9\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5afa <__gridxc_gga_MOD_ggaxc+0x135e>\n-\tldr.w\tr3, [pc, #1332]\t@ 5194 <__gridxc_gga_MOD_ggaxc+0x9f8>\n+\tbeq.w\t6068 <__gridxc_gga_MOD_ggaxc+0x139c>\n+\tldr.w\tr3, [pc, #1352]\t@ 56c4 <__gridxc_gga_MOD_ggaxc+0x9f8>\n \tmovs\tr2, #9\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5afa <__gridxc_gga_MOD_ggaxc+0x135e>\n-\tldr.w\tr3, [pc, #1312]\t@ 5198 <__gridxc_gga_MOD_ggaxc+0x9fc>\n+\tbeq.w\t6068 <__gridxc_gga_MOD_ggaxc+0x139c>\n+\tldr.w\tr3, [pc, #1332]\t@ 56c8 <__gridxc_gga_MOD_ggaxc+0x9fc>\n \tmovs\tr2, #10\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5ac4 <__gridxc_gga_MOD_ggaxc+0x1328>\n-\tldr.w\tr3, [pc, #1288]\t@ 519c <__gridxc_gga_MOD_ggaxc+0xa00>\n+\tbeq.w\t6032 <__gridxc_gga_MOD_ggaxc+0x1366>\n+\tldr.w\tr3, [pc, #1312]\t@ 56cc <__gridxc_gga_MOD_ggaxc+0xa00>\n \tmovs\tr2, #10\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5ac4 <__gridxc_gga_MOD_ggaxc+0x1328>\n-\tldr.w\tr3, [pc, #1268]\t@ 51a0 <__gridxc_gga_MOD_ggaxc+0xa04>\n+\tbeq.w\t6032 <__gridxc_gga_MOD_ggaxc+0x1366>\n+\tldr.w\tr3, [pc, #1292]\t@ 56d0 <__gridxc_gga_MOD_ggaxc+0xa04>\n \tmovs\tr2, #10\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5ac4 <__gridxc_gga_MOD_ggaxc+0x1328>\n-\tldr.w\tr3, [pc, #1248]\t@ 51a4 <__gridxc_gga_MOD_ggaxc+0xa08>\n+\tbeq.w\t6032 <__gridxc_gga_MOD_ggaxc+0x1366>\n+\tldr.w\tr3, [pc, #1272]\t@ 56d4 <__gridxc_gga_MOD_ggaxc+0xa08>\n \tmovs\tr2, #9\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a8e <__gridxc_gga_MOD_ggaxc+0x12f2>\n-\tldr.w\tr3, [pc, #1224]\t@ 51a8 <__gridxc_gga_MOD_ggaxc+0xa0c>\n+\tbeq.w\t5ffc <__gridxc_gga_MOD_ggaxc+0x1330>\n+\tldr.w\tr3, [pc, #1252]\t@ 56d8 <__gridxc_gga_MOD_ggaxc+0xa0c>\n \tmovs\tr2, #9\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a8e <__gridxc_gga_MOD_ggaxc+0x12f2>\n-\tldr.w\tr3, [pc, #1204]\t@ 51ac <__gridxc_gga_MOD_ggaxc+0xa10>\n+\tbeq.w\t5ffc <__gridxc_gga_MOD_ggaxc+0x1330>\n+\tldr.w\tr3, [pc, #1232]\t@ 56dc <__gridxc_gga_MOD_ggaxc+0xa10>\n \tmovs\tr2, #9\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a8e <__gridxc_gga_MOD_ggaxc+0x12f2>\n-\tldr.w\tr3, [pc, #1184]\t@ 51b0 <__gridxc_gga_MOD_ggaxc+0xa14>\n+\tbeq.w\t5ffc <__gridxc_gga_MOD_ggaxc+0x1330>\n+\tldr.w\tr3, [pc, #1212]\t@ 56e0 <__gridxc_gga_MOD_ggaxc+0xa14>\n \tmovs\tr2, #10\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a58 <__gridxc_gga_MOD_ggaxc+0x12bc>\n-\tldr.w\tr3, [pc, #1160]\t@ 51b4 <__gridxc_gga_MOD_ggaxc+0xa18>\n+\tbeq.w\t5fc6 <__gridxc_gga_MOD_ggaxc+0x12fa>\n+\tldr.w\tr3, [pc, #1192]\t@ 56e4 <__gridxc_gga_MOD_ggaxc+0xa18>\n \tmovs\tr2, #10\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a58 <__gridxc_gga_MOD_ggaxc+0x12bc>\n-\tldr.w\tr3, [pc, #1140]\t@ 51b8 <__gridxc_gga_MOD_ggaxc+0xa1c>\n+\tbeq.w\t5fc6 <__gridxc_gga_MOD_ggaxc+0x12fa>\n+\tldr.w\tr3, [pc, #1172]\t@ 56e8 <__gridxc_gga_MOD_ggaxc+0xa1c>\n \tmovs\tr2, #10\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t5a58 <__gridxc_gga_MOD_ggaxc+0x12bc>\n-\tldr.w\tr3, [pc, #1120]\t@ 51bc <__gridxc_gga_MOD_ggaxc+0xa20>\n+\tbeq.w\t5fc6 <__gridxc_gga_MOD_ggaxc+0x12fa>\n+\tldr.w\tr3, [pc, #1152]\t@ 56ec <__gridxc_gga_MOD_ggaxc+0xa20>\n \tmovs\tr2, #4\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t59bc <__gridxc_gga_MOD_ggaxc+0x1220>\n-\tldr.w\tr3, [pc, #1096]\t@ 51c0 <__gridxc_gga_MOD_ggaxc+0xa24>\n+\tbeq.w\t5f32 <__gridxc_gga_MOD_ggaxc+0x1266>\n+\tldr.w\tr3, [pc, #1132]\t@ 56f0 <__gridxc_gga_MOD_ggaxc+0xa24>\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t59bc <__gridxc_gga_MOD_ggaxc+0x1220>\n-\tldr.w\tr3, [pc, #1076]\t@ 51c4 <__gridxc_gga_MOD_ggaxc+0xa28>\n+\tbeq.w\t5f32 <__gridxc_gga_MOD_ggaxc+0x1266>\n+\tldr.w\tr3, [pc, #1112]\t@ 56f4 <__gridxc_gga_MOD_ggaxc+0xa28>\n \tmovs\tr2, #5\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 4dbe <__gridxc_gga_MOD_ggaxc+0x622>\n-\tldr.w\tr3, [pc, #1056]\t@ 51c8 <__gridxc_gga_MOD_ggaxc+0xa2c>\n+\tcbz\tr0, 52c6 <__gridxc_gga_MOD_ggaxc+0x5fa>\n+\tldr.w\tr3, [pc, #1096]\t@ 56f8 <__gridxc_gga_MOD_ggaxc+0xa2c>\n \tmovs\tr2, #5\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t59f2 <__gridxc_gga_MOD_ggaxc+0x1256>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tbne.w\t5f68 <__gridxc_gga_MOD_ggaxc+0x129c>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1a18 <__gridxc_gga_MOD_pw86rx>\n-\tb.n\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tstr\tr3, [sp, #16]\n-\tadd.w\tr1, r7, #112\t@ 0x70\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1bc0 <__gridxc_gga_MOD_pw86rx>\n+\tb.n\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #96\t@ 0x60\n+\tadd.w\tr2, r7, #240\t@ 0xf0\n+\tstr\tr3, [sp, #16]\n+\tadd.w\tr1, r7, #128\t@ 0x80\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tadd.w\tr0, r7, #112\t@ 0x70\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tstr\tr2, [sp, #32]\n-\tadd.w\tr2, r7, #272\t@ 0x110\n+\tadd.w\tr2, r7, #288\t@ 0x120\n \tstr\tr2, [sp, #28]\n-\tadd.w\tr2, r7, #144\t@ 0x90\n-\tstr\tr2, [sp, #24]\n \tadd.w\tr2, r7, #160\t@ 0xa0\n+\tstr\tr2, [sp, #24]\n+\tadd.w\tr2, r7, #176\t@ 0xb0\n \tstr\tr2, [sp, #20]\n-\tadd.w\tr2, r7, #320\t@ 0x140\n+\tadd.w\tr2, r7, #336\t@ 0x150\n \tstr\tr2, [sp, #8]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n+\tadd.w\tr2, r7, #144\t@ 0x90\n \tstr\tr2, [sp, #4]\n-\tadd.w\tr2, r7, #92\t@ 0x5c\n+\tadd.w\tr2, r7, #108\t@ 0x6c\n \tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #104\t@ 0x68\n-\taddw\tr9, pc, #716\t@ 0x2cc\n+\tadd.w\tr2, r7, #120\t@ 0x78\n+\taddw\tr9, pc, #756\t@ 0x2f4\n \tldrd\tr8, r9, [r9]\n \tstrd\tr8, r9, [r2, #-8]\n-\taddw\tr9, pc, #712\t@ 0x2c8\n+\taddw\tr9, pc, #752\t@ 0x2f0\n \tldrd\tr8, r9, [r9]\n-\tstrd\tr8, r9, [r7, #112]\t@ 0x70\n-\taddw\tr9, pc, #708\t@ 0x2c4\n+\tstrd\tr8, r9, [r7, #128]\t@ 0x80\n+\taddw\tr9, pc, #748\t@ 0x2ec\n \tldrd\tr8, r9, [r9]\n \tstrd\tr8, r9, [r2]\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n \tcmp\tr6, #4\n-\tbeq.w\t51cc <__gridxc_gga_MOD_ggaxc+0xa30>\n+\tbeq.w\t56fc <__gridxc_gga_MOD_ggaxc+0xa30>\n \tcmp\tr6, #0\n-\tble.w\t4a08 <__gridxc_gga_MOD_ggaxc+0x26c>\n-\tldrd\tr2, r3, [r7, #160]\t@ 0xa0\n+\tble.w\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n+\tldr\tr1, [r7, #68]\t@ 0x44\n \tcmp\tr6, #1\n-\tvldr\td23, [r7, #144]\t@ 0x90\n-\tvldr\td19, [r7, #272]\t@ 0x110\n-\tvldr\td16, [r7, #280]\t@ 0x118\n-\tvldr\td20, [r7, #288]\t@ 0x120\n-\tvldr\td24, [r7, #224]\t@ 0xe0\n-\tvldr\td22, [r7, #232]\t@ 0xe8\n-\tvldr\td25, [r7, #240]\t@ 0xf0\n-\tstrd\tr2, r3, [fp]\n-\tbeq.w\t5404 <__gridxc_gga_MOD_ggaxc+0xc68>\n-\tvldr\td29, [r7, #152]\t@ 0x98\n-\tvldr\td21, [r7, #168]\t@ 0xa8\n-\tvldr\td30, [r7, #248]\t@ 0xf8\n-\tvldr\td31, [r7, #256]\t@ 0x100\n-\tvldr\td18, [r7, #264]\t@ 0x108\n-\tvldr\td26, [r7, #296]\t@ 0x128\n-\tvldr\td27, [r7, #304]\t@ 0x130\n-\tvldr\td17, [r7, #312]\t@ 0x138\n-\tvstr\td21, [fp, #8]\n-\tvstr\td29, [sl, #8]\n-\tvstr\td23, [sl]\n-\tvstr\td19, [r4]\n-\tvstr\td16, [r4, #8]\n-\tvstr\td20, [r4, #16]\n-\tvstr\td26, [r4, #24]\n-\tvstr\td27, [r4, #32]\n-\tvstr\td17, [r4, #40]\t@ 0x28\n-\tvstr\td24, [r5]\n-\tvstr\td22, [r5, #8]\n-\tvstr\td25, [r5, #16]\n-\tvstr\td30, [r5, #24]\n-\tvstr\td31, [r5, #32]\n-\tvstr\td18, [r5, #40]\t@ 0x28\n-\tb.n\t4a08 <__gridxc_gga_MOD_ggaxc+0x26c>\n-\tvldr\td12, [r3, #24]\n+\tldrd\tr2, r3, [r7, #176]\t@ 0xb0\n+\tvldr\td5, [r7, #160]\t@ 0xa0\n+\tvldr\td2, [r7, #288]\t@ 0x120\n+\tvldr\td3, [r7, #296]\t@ 0x128\n+\tvldr\td1, [r7, #304]\t@ 0x130\n+\tvldr\td8, [r7, #240]\t@ 0xf0\n+\tvldr\td0, [r7, #248]\t@ 0xf8\n+\tvldr\td9, [r7, #256]\t@ 0x100\n+\tstrd\tr2, r3, [r1]\n+\tbeq.w\t5948 <__gridxc_gga_MOD_ggaxc+0xc7c>\n+\tvldr\td7, [r7, #272]\t@ 0x110\n+\tmov\tr3, r1\n+\tvldr\td13, [r7, #168]\t@ 0xa8\n+\tvldr\td4, [r7, #184]\t@ 0xb8\n+\tvstr\td7, [r7, #80]\t@ 0x50\n+\tvldr\td14, [r7, #264]\t@ 0x108\n+\tvldr\td6, [r7, #280]\t@ 0x118\n+\tvldr\td11, [r7, #312]\t@ 0x138\n+\tvldr\td10, [r7, #320]\t@ 0x140\n+\tvldr\td7, [r7, #328]\t@ 0x148\n+\tvstr\td7, [r4, #40]\t@ 0x28\n+\tvldr\td7, [r7, #80]\t@ 0x50\n+\tvstr\td4, [r3, #8]\n+\tvstr\td13, [sl, #8]\n+\tvstr\td5, [sl]\n+\tvstr\td2, [r4]\n+\tvstr\td3, [r4, #8]\n+\tvstr\td1, [r4, #16]\n+\tvstr\td11, [r4, #24]\n+\tvstr\td10, [r4, #32]\n+\tvstr\td8, [r5]\n+\tvstr\td0, [r5, #8]\n+\tvstr\td9, [r5, #16]\n+\tvstr\td14, [r5, #24]\n+\tvstr\td7, [r5, #32]\n+\tvstr\td6, [r5, #40]\t@ 0x28\n+\tb.n\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n+\tvldr\td11, [r3, #16]\n \tmovs\tr1, #2\n-\tvldr\td9, [r3, #16]\n-\tvldr\td20, [r3]\n-\tvmul.f64\td16, d12, d12\n+\tvldr\td12, [r3, #24]\n+\tvldr\td4, [r3]\n+\tvmul.f64\td7, d11, d11\n \tvldr\td13, [r3, #8]\n-\tvfma.f64\td16, d9, d9\n-\tvldr\td18, [pc, #492]\t@ 50f8 <__gridxc_gga_MOD_ggaxc+0x95c>\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n-\tvsub.f64\td1, d20, d13\n-\tvadd.f64\td13, d20, d13\n-\tvsqrt.f64\td0, d16\n+\tvmla.f64\td7, d12, d12\n+\tvldr\td6, [pc, #512]\t@ 5620 <__gridxc_gga_MOD_ggaxc+0x954>\n+\tstr\tr1, [r7, #108]\t@ 0x6c\n+\tvsub.f64\td1, d4, d13\n+\tvadd.f64\td13, d4, d13\n+\tvsqrt.f64\td0, d7\n \tvadd.f64\td0, d0, d0\n-\tvmul.f64\td16, d0, d0\n-\tvfma.f64\td16, d1, d1\n-\tvsqrt.f64\td15, d16\n-\tvcmpe.f64\td16, d18\n+\tvmul.f64\td7, d0, d0\n+\tvmla.f64\td7, d1, d1\n+\tvsqrt.f64\td14, d7\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t53bc <__gridxc_gga_MOD_ggaxc+0xc20>\n-\tstr\tr2, [r7, #16]\n+\tble.w\t58fa <__gridxc_gga_MOD_ggaxc+0xc2e>\n+\tstr\tr2, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tatan2\n-\tadd.w\tr3, r7, #80\t@ 0x50\n-\tadd.w\tr2, r7, #72\t@ 0x48\n-\tvmov.f64\td8, d0\n+\tadd.w\tr3, r7, #96\t@ 0x60\n+\tadd.w\tr2, r7, #88\t@ 0x58\n+\tvmov.f64\td9, d0\n \tmov\tr0, r3\n \tmov\tr1, r2\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tstr\tr2, [r7, #40]\t@ 0x28\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tstr\tr2, [r7, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tldr\tr2, [r7, #40]\t@ 0x28\n+\tldr\tr2, [r7, #48]\t@ 0x30\n \tvmov.f64\td0, #96\t@ 0x3f000000 0.5\n-\tldr\tr0, [r7, #36]\t@ 0x24\n-\tadd.w\tr3, r7, #88\t@ 0x58\n-\tvmul.f64\td0, d8, d0\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tadd.w\tr3, r7, #104\t@ 0x68\n+\tvmul.f64\td0, d9, d0\n \tmov\tr1, r2\n-\tvldr\td10, [r7, #80]\t@ 0x50\n-\tvldr\td11, [r2]\n-\tstr\tr3, [r7, #24]\n+\tvldr\td15, [r7, #96]\t@ 0x60\n+\tvldr\td8, [r2]\n+\tstr\tr3, [r7, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tldr\tr3, [r7, #24]\n-\tvldr\td16, [r2]\n-\tvldr\td8, [r3, #-8]\n-\tldr\tr2, [r7, #16]\n-\tvmul.f64\td22, d16, d16\n-\tvstr\td16, [r7]\n-\tvmul.f64\td14, d16, d8\n-\tvmul.f64\td21, d8, d8\n-\tvadd.f64\td14, d14, d14\n-\tvmov.f64\td1, d9\n+\tldr\tr2, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tvldr\td7, [r2]\n+\tvldr\td6, [r3, #-8]\n+\tldr\tr2, [r7, #32]\n+\tvstr\td8, [r7, #8]\n+\tvmul.f64\td9, d7, d7\n+\tvmul.f64\td10, d7, d6\n+\tvmul.f64\td8, d6, d6\n+\tvstr\td7, [r7, #16]\n+\tvstr\td6, [r7]\n+\tvadd.f64\td10, d10, d10\n+\tvmov.f64\td1, d11\n \tvneg.f64\td0, d12\n-\tstr\tr3, [r7, #12]\n-\tstr\tr2, [r7, #32]\n-\tvstr\td22, [r7, #16]\n-\tvstr\td21, [r7, #24]\n+\tstrd\tr3, r2, [r7, #32]\n \tbl\t0 \n R_ARM_THM_CALL\tatan2\n-\tldrd\tr0, r1, [r7, #36]\t@ 0x24\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tldr\tr0, [r7, #40]\t@ 0x28\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tldr\tr3, [r7, #12]\n-\tvldr\td19, [r8, #72]\t@ 0x48\n-\tvldr\td21, [r7, #24]\n-\tvldr\td16, [r8, #48]\t@ 0x30\n-\tvldr\td12, [r3, #-8]\n-\tldr\tr3, [r7, #40]\t@ 0x28\n-\tvldr\td28, [r8, #40]\t@ 0x28\n-\tvldr\td17, [r8, #88]\t@ 0x58\n-\tvnmul.f64\td19, d19, d12\n-\tvldr\td22, [r7, #16]\n-\tvldr\td9, [r3]\n-\tvmul.f64\td30, d28, d21\n-\tvldr\td24, [r8, #64]\t@ 0x40\n-\tvnmul.f64\td17, d17, d12\n-\tvldr\td18, [r8, #80]\t@ 0x50\n-\tvmul.f64\td28, d28, d22\n-\tvldr\td23, [r8, #56]\t@ 0x38\n-\tvfma.f64\td19, d9, d16\n-\tvldr\td16, [r8, #32]\n-\tvfma.f64\td17, d24, d9\n-\tvldr\td26, [r8, #8]\n-\tvnmul.f64\td18, d18, d12\n-\tvldr\td24, [r8, #24]\n-\tvfma.f64\td18, d9, d23\n-\tvldr\td27, [r8]\n-\tvmul.f64\td23, d16, d21\n-\tvldr\td25, [r8, #16]\n-\tvmul.f64\td16, d16, d22\n-\tvfma.f64\td23, d26, d22\n-\tvfma.f64\td16, d26, d21\n-\tvmul.f64\td29, d24, d21\n-\tvmov.f64\td26, d30\n-\tvfma.f64\td29, d27, d22\n-\tvfma.f64\td26, d25, d22\n-\tvmul.f64\td24, d24, d22\n-\tvmov.f64\td22, d28\n-\tvfma.f64\td24, d27, d21\n-\tvfma.f64\td22, d25, d21\n-\tvfma.f64\td23, d18, d14\n-\tvadd.f64\td21, d15, d13\n-\tvfma.f64\td26, d17, d14\n-\tvfma.f64\td29, d19, d14\n-\tvfms.f64\td16, d18, d14\n-\tvsub.f64\td15, d13, d15\n-\tvfms.f64\td22, d17, d14\n-\tvfms.f64\td24, d19, d14\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tldr\tr2, [r7, #32]\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td15, d15, d17\n-\tvstr\td23, [r7, #328]\t@ 0x148\n-\tvstr\td29, [r7, #320]\t@ 0x140\n-\tvstr\td21, [r7, #128]\t@ 0x80\n-\tvstr\td15, [r7, #136]\t@ 0x88\n-\tvstr\td24, [r7, #344]\t@ 0x158\n-\tvstr\td16, [r7, #352]\t@ 0x160\n-\tvstr\td26, [r7, #336]\t@ 0x150\n-\tvstr\td22, [r7, #360]\t@ 0x168\n-\tb.w\t4898 <__gridxc_gga_MOD_ggaxc+0xfc>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvldr\td16, [r3]\n-\tvldr\td18, [r8, #8]\n-\tcmp\tr6, #1\n-\tldrd\tr0, r1, [r8, #16]\n-\tstr\tr6, [r7, #92]\t@ 0x5c\n-\tvmaxnm.f64\td16, d16, d17\n-\tstrd\tr0, r1, [r7, #336]\t@ 0x150\n-\tvstr\td18, [r7, #328]\t@ 0x148\n-\tvstr\td16, [r7, #128]\t@ 0x80\n-\tvldr\td16, [r8]\n-\tvstr\td16, [r7, #320]\t@ 0x140\n-\tbeq.w\t4898 <__gridxc_gga_MOD_ggaxc+0xfc>\n-\tvldr\td16, [r3, #8]\n-\tldrd\tr0, r1, [r8, #24]\n-\tstrd\tr0, r1, [r7, #344]\t@ 0x158\n-\tvmaxnm.f64\td16, d16, d17\n-\tldrd\tr0, r1, [r8, #32]\n+\tldr\tr3, [r7, #32]\n+\tvldr\td7, [fp, #72]\t@ 0x48\n+\tvldr\td3, [fp, #80]\t@ 0x50\n+\tvldr\td5, [fp, #48]\t@ 0x30\n+\tvldr\td6, [r3, #-8]\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tvldr\td4, [fp, #88]\t@ 0x58\n+\tvmul.f64\td7, d6, d7\n+\tvmul.f64\td3, d6, d3\n+\tvstr\td6, [r7, #40]\t@ 0x28\n+\tvldr\td12, [r3]\n+\tvmul.f64\td4, d6, d4\n+\tvldr\td6, [fp, #8]\n+\tvldr\td1, [fp, #32]\n+\tvnmls.f64\td7, d12, d5\n+\tvldr\td5, [fp, #56]\t@ 0x38\n+\tvldr\td2, [fp, #16]\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tvnmls.f64\td3, d12, d5\n+\tvldr\td5, [fp, #64]\t@ 0x40\n+\tvnmls.f64\td4, d12, d5\n+\tvldr\td5, [fp]\n+\tvmul.f64\td7, d7, d10\n+\tvmul.f64\td0, d3, d10\n+\tvmul.f64\td3, d5, d9\n+\tvmul.f64\td5, d5, d8\n+\tvmul.f64\td11, d4, d10\n+\tvldr\td4, [fp, #24]\n+\tvldr\td10, [fp, #40]\t@ 0x28\n+\tvmla.f64\td3, d4, d8\n+\tvmla.f64\td5, d4, d9\n+\tvadd.f64\td3, d3, d7\n+\tvsub.f64\td5, d5, d7\n+\tvmul.f64\td7, d6, d9\n+\tvmul.f64\td6, d6, d8\n+\tvmla.f64\td7, d1, d8\n+\tvmla.f64\td6, d1, d9\n+\tvstr\td3, [r7, #336]\t@ 0x150\n+\tvstr\td5, [r7, #360]\t@ 0x168\n+\tvadd.f64\td7, d7, d0\n+\tvsub.f64\td6, d6, d0\n+\tvstr\td7, [r7, #344]\t@ 0x158\n+\tvmul.f64\td7, d10, d8\n+\tvmla.f64\td7, d2, d9\n+\tvstr\td6, [r7, #368]\t@ 0x170\n+\tvmul.f64\td6, d10, d9\n+\tvmla.f64\td6, d2, d8\n+\tvadd.f64\td7, d7, d11\n+\tvsub.f64\td6, d6, d11\n+\tvstr\td7, [r7, #352]\t@ 0x160\n+\tvadd.f64\td7, d14, d13\n+\tvsub.f64\td13, d13, d14\n+\tvstr\td6, [r7, #376]\t@ 0x178\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td13, d13, d6\n+\tvstr\td7, [r7, #144]\t@ 0x90\n+\tvstr\td13, [r7, #152]\t@ 0x98\n+\tb.n\t4dca <__gridxc_gga_MOD_ggaxc+0xfe>\n+\tvldr\td7, [r3]\n+\tvldr\td6, [pc, #116]\t@ 5628 <__gridxc_gga_MOD_ggaxc+0x95c>\n+\tvldr\td5, [fp]\n+\tldrd\tr0, r1, [fp, #16]\n+\tvcmpe.f64\td7, d6\n+\tstr\tr6, [r7, #108]\t@ 0x6c\n \tstrd\tr0, r1, [r7, #352]\t@ 0x160\n-\tldrd\tr0, r1, [r8, #40]\t@ 0x28\n+\tvstr\td5, [r7, #336]\t@ 0x150\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tcmp\tr6, #1\n+\tvstr\td7, [r7, #144]\t@ 0x90\n+\tvldr\td7, [fp, #8]\n+\tvstr\td7, [r7, #344]\t@ 0x158\n+\tbeq.w\t4dca <__gridxc_gga_MOD_ggaxc+0xfe>\n+\tvldr\td7, [r3, #8]\n+\tldrd\tr0, r1, [fp, #24]\n \tstrd\tr0, r1, [r7, #360]\t@ 0x168\n-\tvstr\td16, [r7, #136]\t@ 0x88\n-\tb.w\t4898 <__gridxc_gga_MOD_ggaxc+0xfc>\n+\tvcmpe.f64\td7, d6\n+\tldrd\tr0, r1, [fp, #32]\n+\tstrd\tr0, r1, [r7, #368]\t@ 0x170\n+\tldrd\tr0, r1, [fp, #40]\t@ 0x28\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tstrd\tr0, r1, [r7, #376]\t@ 0x178\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvstr\td7, [r7, #152]\t@ 0x98\n+\tb.w\t4dca <__gridxc_gga_MOD_ggaxc+0xfe>\n+\tnop\n \tnop.w\n \t.word\t0x99a88ea8\n \t.word\t0x3af357c2\n+\t...\n \t.word\t0xbcd35a86\n \t.word\t0x3fb114e3\n \t.word\t0x7576bfc1\n \t.word\t0x3fcc191d\n \t.word\t0x353f7cee\n \t.word\t0x3fe9ba5e\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000954\n+\t.word\t0x00000952\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000090e\n+\t.word\t0x0000090c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000894\n+\t.word\t0x00000892\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000868\n+\t.word\t0x00000866\n R_ARM_REL32\t.LC9\n-\t.word\t0x000007f2\n+\t.word\t0x000007ec\n R_ARM_REL32\t.LC10\n-\t.word\t0x000007cc\n+\t.word\t0x000007d0\n R_ARM_REL32\t.rodata\n \t.word\t0x00000724\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000006f0\n+\t.word\t0x000006f2\n R_ARM_REL32\t.LC11\n-\t.word\t0x000006da\n+\t.word\t0x000006de\n R_ARM_REL32\t.LC12\n-\t.word\t0x000006c6\n+\t.word\t0x000006ca\n R_ARM_REL32\t.LC13\n-\t.word\t0x000006b2\n+\t.word\t0x000006b6\n R_ARM_REL32\t.LC14\n-\t.word\t0x0000069e\n+\t.word\t0x000006a2\n R_ARM_REL32\t.LC15\n-\t.word\t0x0000068a\n+\t.word\t0x0000068e\n R_ARM_REL32\t.LC16\n-\t.word\t0x00000676\n+\t.word\t0x0000067a\n R_ARM_REL32\t.LC17\n-\t.word\t0x00000662\n+\t.word\t0x00000666\n R_ARM_REL32\t.LC18\n-\t.word\t0x0000064e\n+\t.word\t0x00000652\n R_ARM_REL32\t.LC19\n-\t.word\t0x0000063a\n+\t.word\t0x0000063e\n R_ARM_REL32\t.LC20\n-\t.word\t0x00000626\n+\t.word\t0x0000062a\n R_ARM_REL32\t.LC21\n-\t.word\t0x00000612\n+\t.word\t0x00000616\n R_ARM_REL32\t.LC22\n-\t.word\t0x000005fe\n+\t.word\t0x00000602\n R_ARM_REL32\t.LC23\n-\t.word\t0x000005e8\n+\t.word\t0x000005ee\n R_ARM_REL32\t.LC24\n-\t.word\t0x000005d2\n+\t.word\t0x000005da\n R_ARM_REL32\t.LC25\n-\t.word\t0x000005bc\n+\t.word\t0x000005c6\n R_ARM_REL32\t.LC26\n-\t.word\t0x000005a6\n+\t.word\t0x000005b2\n R_ARM_REL32\t.LC27\n-\t.word\t0x00000592\n+\t.word\t0x0000059e\n R_ARM_REL32\t.LC28\n-\t.word\t0x0000057c\n+\t.word\t0x0000058a\n R_ARM_REL32\t.LC29\n-\t.word\t0x00000566\n+\t.word\t0x00000576\n R_ARM_REL32\t.LC30\n-\t.word\t0x00000550\n+\t.word\t0x00000562\n R_ARM_REL32\t.LC31\n-\t.word\t0x0000053a\n+\t.word\t0x0000054e\n R_ARM_REL32\t.LC32\n-\t.word\t0x00000526\n+\t.word\t0x0000053a\n R_ARM_REL32\t.LC33\n-\t.word\t0x00000510\n+\t.word\t0x00000526\n R_ARM_REL32\t.LC34\n-\t.word\t0x000004fa\n+\t.word\t0x00000512\n R_ARM_REL32\t.LC35\n-\t.word\t0x000004e6\n+\t.word\t0x000004fe\n R_ARM_REL32\t.LC36\n-\t.word\t0x000004d0\n+\t.word\t0x000004ea\n R_ARM_REL32\t.LC37\n-\t.word\t0x000004ba\n+\t.word\t0x000004d6\n R_ARM_REL32\t.LC38\n-\t.word\t0x000004a6\n+\t.word\t0x000004c2\n R_ARM_REL32\t.LC39\n-\t.word\t0x00000490\n+\t.word\t0x000004ae\n R_ARM_REL32\t.LC40\n-\t.word\t0x0000047a\n+\t.word\t0x0000049a\n R_ARM_REL32\t.LC41\n-\t.word\t0x00000466\n+\t.word\t0x00000486\n R_ARM_REL32\t.LC42\n-\t.word\t0x00000450\n+\t.word\t0x00000472\n R_ARM_REL32\t.LC43\n-\t.word\t0x0000043a\n+\t.word\t0x0000045e\n R_ARM_REL32\t.LC44\n-\t.word\t0x00000424\n+\t.word\t0x0000044a\n R_ARM_REL32\t.LC45\n-\t.word\t0x00000412\n+\t.word\t0x0000043a\n R_ARM_REL32\t.LC46\n-\tvldr\td18, [r7, #168]\t@ 0xa8\n-\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n-\tvldr\td19, [r7, #160]\t@ 0xa0\n-\tvmov.f64\td20, #224\t@ 0xbf000000 -0.5\n-\tvldr\td22, [r7, #144]\t@ 0x90\n-\tvmul.f64\td9, d9, d3\n-\tvldr\td23, [r7, #152]\t@ 0x98\n-\tvmul.f64\td20, d12, d20\n-\tvsub.f64\td17, d19, d18\n-\tvadd.f64\td19, d19, d18\n-\tvldr\td16, [r7]\n-\tvmul.f64\td8, d8, d8\n-\tvsub.f64\td18, d22, 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0x50\n+\tvldr\td7, [r7, #328]\t@ 0x148\n+\tvldr\td5, [r7, #304]\t@ 0x130\n+\tvmul.f64\td6, d7, d2\n+\tvmla.f64\td6, d5, d3\n+\tvstr\td6, [r4, #16]\n+\tvmul.f64\td6, d7, d3\n+\tvsub.f64\td7, d5, d7\n+\tvmla.f64\td6, d5, d2\n+\tvldr\td5, [r7, #256]\t@ 0x100\n+\tvmul.f64\td7, d7, d15\n+\tvmul.f64\td4, d7, d1\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td6, [r4, #40]\t@ 0x28\n+\tvstr\td7, [r4, #88]\t@ 0x58\n+\tvldr\td7, [r7, #280]\t@ 0x118\n+\tvstr\td4, [r4, #64]\t@ 0x40\n+\tvmul.f64\td6, d7, d2\n+\tvmla.f64\td6, d5, d3\n+\tvmul.f64\td3, d7, d3\n+\tvsub.f64\td7, d5, d7\n+\tvmla.f64\td3, d5, d2\n+\tvmul.f64\td7, d7, d15\n+\tvstr\td6, [r5, #16]\n+\tvmul.f64\td1, d7, d1\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td3, [r5, #40]\t@ 0x28\n+\tvstr\td1, [r5, #64]\t@ 0x40\n+\tvstr\td7, [r5, #88]\t@ 0x58\n+\tb.w\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n+\tvldr\td10, [pc, #708]\t@ 5bc0 <__gridxc_gga_MOD_ggaxc+0xef4>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tadd.w\tr3, r7, #96\t@ 0x60\n \tstr\tr3, [r7, #40]\t@ 0x28\n-\tvmov.f64\td10, d14\n-\tvmov.f64\td21, d14\n-\tvmov.f64\td8, d14\n+\tvmov.f64\td9, d7\n \tadd.w\tr3, r7, #88\t@ 0x58\n-\tb.n\t4f96 <__gridxc_gga_MOD_ggaxc+0x7fa>\n-\tvmov.i64\td17, #0x0000000000000000\n+\tvmov.f64\td15, d10\n+\tstr\tr3, [r7, #48]\t@ 0x30\n+\tvmov.f64\td8, d10\n+\tadd.w\tr3, r7, #104\t@ 0x68\n+\tvstr\td7, [r7, #8]\n+\tvstr\td10, [r7]\n+\tvstr\td7, [r7, #16]\n+\tb.n\t54b2 <__gridxc_gga_MOD_ggaxc+0x7e6>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tvldr\td7, [pc, #656]\t@ 5bc0 <__gridxc_gga_MOD_ggaxc+0xef4>\n+\tvstr\td7, [r3]\n+\tvmov.f64\td3, d7\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tvmov.f64\td1, d7\n+\tvmov.f64\td2, d7\n+\tvstr\td7, [r3]\n+\tvstr\td5, [sl]\n+\tvstr\td2, [r4]\n+\tvstr\td3, [r4, #8]\n+\tvstr\td1, [r4, #16]\n+\tvstr\td8, [r5]\n+\tvstr\td0, [r5, #8]\n+\tvstr\td9, [r5, #16]\n+\tb.w\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tvmov.f64\td16, d17\n-\tvmov.f64\td20, d17\n-\tvmov.f64\td19, d17\n-\tvstr\td17, [r3]\n-\tvstr\td17, [fp]\n-\tvstr\td23, [sl]\n-\tvstr\td19, [r4]\n-\tvstr\td16, [r4, #8]\n-\tvstr\td20, [r4, #16]\n-\tvstr\td24, [r5]\n-\tvstr\td22, [r5, #8]\n-\tvstr\td25, [r5, #16]\n-\tb.w\t4a08 <__gridxc_gga_MOD_ggaxc+0x26c>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n+\tadd.w\tr2, r7, #144\t@ 0x90\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t25d8 <__gridxc_gga_MOD_rpbexc>\n-\tb.n\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t2858 <__gridxc_gga_MOD_rpbexc>\n+\tb.n\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n \tcmp\tr0, #2\n-\tbeq.w\t573e <__gridxc_gga_MOD_ggaxc+0xfa2>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tbeq.w\t5c96 <__gridxc_gga_MOD_ggaxc+0xfca>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n \tcmp\tr0, #32\n-\tbne.w\t492c <__gridxc_gga_MOD_ggaxc+0x190>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tbne.w\t4e5e <__gridxc_gga_MOD_ggaxc+0x192>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tadd.w\tfp, r7, #136\t@ 0x88\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tldr\tr3, [r7, #8]\n-\tldr.w\tr1, [pc, #2484]\t@ 5e30 <__gridxc_gga_MOD_ggaxc+0x1694>\n-\tmov\tr8, r0\n+\tldr\tr3, [r7, #28]\n+\tldr\tr1, [pc, #520]\t@ (5bc8 <__gridxc_gga_MOD_ggaxc+0xefc>)\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr.w\tr8, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #176\t@ 0xb0\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tadd.w\tr8, r7, #120\t@ 0x78\n-\tstr\tr3, [sp, #8]\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tadd.w\tr3, r7, #192\t@ 0xc0\n \tadd\tr1, pc\n-\tadd.w\tr3, r7, #200\t@ 0xc8\n-\tstr.w\tr8, [sp]\n+\tstr\tr3, [sp, #8]\n+\tstr.w\tfp, [sp]\n+\tadd.w\tr3, r7, #216\t@ 0xd8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-\tvldr\td16, [r7, #176]\t@ 0xb0\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tvldr\td17, [r8]\n-\tvadd.f64\td16, d16, d16\n-\tcmp\tr3, #1\n-\tvmul.f64\td14, d16, d14\n-\tvmul.f64\td15, d16, d15\n-\tvmul.f64\td16, d16, d13\n-\tvstr\td14, [r9]\n-\tvstr\td15, [r9, #8]\n-\tvstr\td16, [r9, #16]\n-\tbeq.n\t55bc <__gridxc_gga_MOD_ggaxc+0xe20>\n-\tcmp\tr3, #0\n-\tbne.w\t5678 <__gridxc_gga_MOD_ggaxc+0xedc>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tvstr\td17, [r3]\n-\tldr\tr3, [r7, #8]\n+\tvldr\td6, [r7, #192]\t@ 0xc0\n+\tcmp.w\tr9, #1\n+\tvldr\td7, [fp]\n+\tvadd.f64\td6, d6, d6\n+\tvmul.f64\td8, d6, d8\n+\tvmul.f64\td9, d6, d9\n+\tvmul.f64\td6, d6, d10\n+\tvstr\td8, [r8]\n+\tvstr\td9, [r8, #8]\n+\tvstr\td6, [r8, #16]\n+\tbeq.n\t5af8 <__gridxc_gga_MOD_ggaxc+0xe2c>\n+\tcmp.w\tr9, #0\n+\tbne.w\t5bd0 <__gridxc_gga_MOD_ggaxc+0xf04>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #28]\n \tcmp\tr6, #1\n-\tvldr\td19, [r9]\n-\tvldr\td16, [r9, #8]\n-\tvldr\td20, [r9, #16]\n-\tvldr\td28, [r3]\n-\tvstr\td28, [r7, #160]\t@ 0xa0\n-\tbeq.w\t58fa <__gridxc_gga_MOD_ggaxc+0x115e>\n-\tvmov.i64\td18, #0x0000000000000000\n-\tvldr\td21, [r3, #8]\n-\tldr\tr3, [r7, #56]\t@ 0x38\n+\tvldr\td2, [r8]\n+\tvldr\td3, [r8, #8]\n+\tvldr\td1, [r8, #16]\n+\tvldr\td7, [r3]\n+\tvstr\td7, [r7, #72]\t@ 0x48\n+\tvstr\td7, [r7, #176]\t@ 0xb0\n+\tbeq.w\t5e6e <__gridxc_gga_MOD_ggaxc+0x11a2>\n+\tvldr\td4, [r3, #8]\n \tcmp\tr6, #4\n-\tvldr\td26, [r9, #24]\n-\tvldr\td27, [r9, #32]\n-\tvldr\td17, [r9, #40]\t@ 0x28\n-\tvstr\td18, [r3]\n-\tvstr\td21, [r7, #168]\t@ 0xa8\n-\tvstr\td19, [r7, #272]\t@ 0x110\n-\tvstr\td16, [r7, #280]\t@ 0x118\n-\tvstr\td20, [r7, #288]\t@ 0x120\n-\tvstr\td26, [r7, #296]\t@ 0x128\n-\tvstr\td27, [r7, #304]\t@ 0x130\n-\tvstr\td17, [r7, #312]\t@ 0x138\n-\tvstr\td18, [r7, #152]\t@ 0x98\n-\tvstr\td18, [r7, #144]\t@ 0x90\n-\tvstr\td18, [r7, #224]\t@ 0xe0\n-\tvstr\td18, [r7, #232]\t@ 0xe8\n-\tvstr\td18, [r7, #240]\t@ 0xf0\n-\tvstr\td18, [r7, #248]\t@ 0xf8\n-\tvstr\td18, [r7, #256]\t@ 0x100\n-\tvstr\td18, [r7, #264]\t@ 0x108\n-\tbeq.w\t5856 <__gridxc_gga_MOD_ggaxc+0x10ba>\n-\tvmov.f64\td31, d18\n-\tvmov.f64\td30, d18\n-\tvmov.f64\td25, d18\n-\tvmov.f64\td22, d18\n-\tvmov.f64\td24, d18\n-\tvmov.f64\td29, d18\n-\tvmov.f64\td23, d18\n-\tb.n\t5656 <__gridxc_gga_MOD_ggaxc+0xeba>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tvldr\td6, [pc, #384]\t@ 5bc0 <__gridxc_gga_MOD_ggaxc+0xef4>\n+\tvldr\td11, [r8, #24]\n+\tvldr\td10, [r8, #32]\n+\tvldr\td7, [r8, #40]\t@ 0x28\n+\tvstr\td2, [r7, #288]\t@ 0x120\n+\tvstr\td3, [r7, #296]\t@ 0x128\n+\tvstr\td1, [r7, #304]\t@ 0x130\n+\tvstr\td4, [r7, #184]\t@ 0xb8\n+\tvstr\td6, [r3]\n+\tvstr\td6, [r7, #168]\t@ 0xa8\n+\tvstr\td6, [r7, #160]\t@ 0xa0\n+\tvstr\td6, [r7, #240]\t@ 0xf0\n+\tvstr\td6, [r7, #248]\t@ 0xf8\n+\tvstr\td6, [r7, #256]\t@ 0x100\n+\tvstr\td6, [r7, #264]\t@ 0x108\n+\tvstr\td6, [r7, #272]\t@ 0x110\n+\tvstr\td6, [r7, #280]\t@ 0x118\n+\tvstr\td11, [r7, #312]\t@ 0x138\n+\tvstr\td10, [r7, #320]\t@ 0x140\n+\tvstr\td7, [r7, #328]\t@ 0x148\n+\tbeq.w\t5dc2 <__gridxc_gga_MOD_ggaxc+0x10f6>\n+\tvmov.f64\td14, d6\n+\tvmov.f64\td9, d6\n+\tvmov.f64\td0, d6\n+\tvmov.f64\td8, d6\n+\tvmov.f64\td13, d6\n+\tvmov.f64\td5, d6\n+\tvstr\td6, [r7, #80]\t@ 0x50\n+\tb.n\t5b96 <__gridxc_gga_MOD_ggaxc+0xeca>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tadd.w\tfp, r7, #136\t@ 0x88\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tldr\tr3, [r7, #8]\n-\tldr.w\tr1, [pc, #2236]\t@ 5e34 <__gridxc_gga_MOD_ggaxc+0x1698>\n-\tmov\tr8, r0\n+\tldr\tr3, [r7, #28]\n+\tldr\tr1, [pc, #268]\t@ (5bcc <__gridxc_gga_MOD_ggaxc+0xf00>)\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr.w\tr8, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #176\t@ 0xb0\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tadd.w\tr8, r7, #120\t@ 0x78\n-\tstr\tr3, [sp, #8]\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tadd.w\tr3, r7, #192\t@ 0xc0\n \tadd\tr1, pc\n-\tadd.w\tr3, r7, #200\t@ 0xc8\n-\tstr.w\tr8, [sp]\n+\tstr\tr3, [sp, #8]\n+\tstr.w\tfp, [sp]\n+\tadd.w\tr3, r7, #216\t@ 0xd8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-\tb.w\t4978 <__gridxc_gga_MOD_ggaxc+0x1dc>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n+\tb.w\t4ea6 <__gridxc_gga_MOD_ggaxc+0x1da>\n+\tldr\tr3, [r7, #64]\t@ 0x40\n \tcmp\tr6, #0\n-\tvstr\td20, [r3]\n-\tbgt.n\t55c2 <__gridxc_gga_MOD_ggaxc+0xe26>\n-\tldr\tr1, [r7, #64]\t@ 0x40\n+\tvstr\td7, [r3]\n+\tbgt.n\t5afe <__gridxc_gga_MOD_ggaxc+0xe32>\n+\tldr\tr1, [r7, #72]\t@ 0x48\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.w\t4a08 <__gridxc_gga_MOD_ggaxc+0x26c>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tvstr\td17, [r3]\n-\tldr\tr3, [r7, #8]\n-\tcmp\tr6, #1\n-\tvldr\td24, [r9]\n-\tvldr\td22, [r9, #8]\n-\tvldr\td25, [r9, #16]\n-\tvldr\td23, [r3]\n-\tvstr\td23, [r7, #144]\t@ 0x90\n-\tbeq.w\t53ea <__gridxc_gga_MOD_ggaxc+0xc4e>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvldr\td29, [r3, #8]\n+\tb.w\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #28]\n+\tcmp\tr6, #1\n+\tvldr\td8, [r8]\n+\tvldr\td0, [r8, #8]\n+\tvldr\td9, [r8, #16]\n+\tvldr\td5, [r3]\n+\tvstr\td5, [r7, #160]\t@ 0xa0\n+\tbeq.w\t592c <__gridxc_gga_MOD_ggaxc+0xc60>\n+\tvldr\td6, [r8, #32]\n \tcmp\tr6, #4\n-\tvldr\td30, [r9, #24]\n-\tvldr\td31, [r9, #32]\n-\tvldr\td18, [r9, #40]\t@ 0x28\n-\tvstr\td17, [r3]\n-\tvstr\td29, [r7, #152]\t@ 0x98\n-\tvstr\td24, [r7, #224]\t@ 0xe0\n-\tvstr\td22, [r7, #232]\t@ 0xe8\n-\tvstr\td25, [r7, #240]\t@ 0xf0\n-\tvstr\td30, [r7, #248]\t@ 0xf8\n-\tvstr\td31, [r7, #256]\t@ 0x100\n-\tvstr\td18, [r7, #264]\t@ 0x108\n-\tvstr\td17, [r7, #168]\t@ 0xa8\n-\tvstr\td17, [r7, #160]\t@ 0xa0\n-\tvstr\td17, [r7, #272]\t@ 0x110\n-\tvstr\td17, [r7, #280]\t@ 0x118\n-\tvstr\td17, [r7, #288]\t@ 0x120\n-\tvstr\td17, [r7, #296]\t@ 0x128\n-\tvstr\td17, [r7, #304]\t@ 0x130\n-\tvstr\td17, [r7, #312]\t@ 0x138\n-\tbeq.w\t57b2 <__gridxc_gga_MOD_ggaxc+0x1016>\n-\tvmov.f64\td27, d17\n-\tvmov.f64\td26, d17\n-\tvmov.f64\td20, d17\n-\tvmov.f64\td16, d17\n-\tvmov.f64\td19, d17\n-\tvmov.f64\td21, d17\n-\tvmov.f64\td28, d17\n-\tvstr\td28, [fp]\n-\tb.n\t4eb0 <__gridxc_gga_MOD_ggaxc+0x714>\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tvldr\td13, [r3, #8]\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tvldr\td7, [pc, #152]\t@ 5bc0 <__gridxc_gga_MOD_ggaxc+0xef4>\n+\tvldr\td14, [r8, #24]\n+\tvstr\td6, [r7, #80]\t@ 0x50\n+\tvstr\td6, [r7, #272]\t@ 0x110\n+\tvldr\td6, [r8, #40]\t@ 0x28\n+\tvstr\td8, [r7, #240]\t@ 0xf0\n+\tvstr\td0, [r7, #248]\t@ 0xf8\n+\tvstr\td9, [r7, #256]\t@ 0x100\n+\tvstr\td13, [r7, #168]\t@ 0xa8\n+\tvstr\td7, [r3]\n+\tvstr\td7, [r7, #184]\t@ 0xb8\n+\tvstr\td7, [r7, #176]\t@ 0xb0\n+\tvstr\td7, [r7, #288]\t@ 0x120\n+\tvstr\td7, [r7, #296]\t@ 0x128\n+\tvstr\td7, [r7, #304]\t@ 0x130\n+\tvstr\td7, [r7, #312]\t@ 0x138\n+\tvstr\td7, [r7, #320]\t@ 0x140\n+\tvstr\td7, [r7, #328]\t@ 0x148\n+\tvstr\td14, [r7, #264]\t@ 0x108\n+\tvstr\td6, [r7, #280]\t@ 0x118\n+\tbeq.w\t5d06 <__gridxc_gga_MOD_ggaxc+0x103a>\n+\tvmov.f64\td10, d7\n+\tvmov.f64\td11, d7\n+\tvmov.f64\td1, d7\n+\tvmov.f64\td3, d7\n+\tvmov.f64\td2, d7\n+\tvmov.f64\td4, d7\n+\tvstr\td7, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tvldr\td12, [r7, #72]\t@ 0x48\n+\tvstr\td12, [r3]\n+\tb.n\t53c0 <__gridxc_gga_MOD_ggaxc+0x6f4>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr6, #0\n-\tvmul.f64\td17, d20, d17\n-\tvstr\td17, [r3]\n-\tbgt.n\t5686 <__gridxc_gga_MOD_ggaxc+0xeea>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tvstr\td17, [r3]\n-\tb.w\t4a08 <__gridxc_gga_MOD_ggaxc+0x26c>\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tbgt.n\t5bde <__gridxc_gga_MOD_ggaxc+0xf12>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tvmul.f64\td17, d17, d16\n-\tvstr\td17, [r3]\n-\tldr\tr3, [r7, #8]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td20, [r9, #16]\n+\tvstr\td7, [r3]\n+\tb.w\t4f38 <__gridxc_gga_MOD_ggaxc+0x26c>\n+\tnop\n+\t...\n+\t.word\t0x000001f6\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000000fc\n+ R_ARM_REL32\t.rodata\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #28]\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvldr\td1, [r8, #16]\n \tcmp\tr6, #1\n-\tvldr\td19, [r9]\n-\tvldr\td16, [r9, #8]\n-\tvldr\td28, [r3]\n-\tvmul.f64\td20, d20, d18\n-\tvmul.f64\td19, d19, d18\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td28, d28, d18\n-\tvstr\td28, [r7, #160]\t@ 0xa0\n-\tbeq.w\t58de <__gridxc_gga_MOD_ggaxc+0x1142>\n-\tvldr\td21, [r3, #8]\n+\tvldr\td2, [r8]\n+\tvldr\td3, [r8, #8]\n+\tvldr\td5, [r3]\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td2, d2, d6\n+\tvmul.f64\td3, d3, d6\n+\tvmul.f64\td5, d5, d6\n+\tvstr\td5, [r7, #72]\t@ 0x48\n+\tvstr\td5, [r7, #176]\t@ 0xb0\n+\tbeq.w\t5e54 <__gridxc_gga_MOD_ggaxc+0x1188>\n+\tldr\tr2, [r7, #64]\t@ 0x40\n \tcmp\tr6, #4\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tvldr\td26, [r9, #24]\n-\tvldr\td27, [r9, #32]\n-\tvmul.f64\td21, d21, d18\n-\tvstr\td19, [r7, #272]\t@ 0x110\n-\tvstr\td17, [r3]\n-\tvmul.f64\td26, d26, d18\n-\tvldr\td17, [r9, #40]\t@ 0x28\n-\tvmul.f64\td27, d27, d18\n-\tvstr\td16, [r7, #280]\t@ 0x118\n-\tvstr\td20, [r7, #288]\t@ 0x120\n-\tvmul.f64\td17, d17, d18\n-\tvstr\td28, [r7, #144]\t@ 0x90\n-\tvstr\td19, [r7, #224]\t@ 0xe0\n-\tvstr\td21, [r7, #168]\t@ 0xa8\n-\tvstr\td21, [r7, #152]\t@ 0x98\n-\tvstr\td26, [r7, #296]\t@ 0x128\n-\tvstr\td27, [r7, #304]\t@ 0x130\n-\tvstr\td17, [r7, #312]\t@ 0x138\n-\tvstr\td16, [r7, #232]\t@ 0xe8\n-\tvstr\td20, [r7, #240]\t@ 0xf0\n-\tvstr\td26, [r7, #248]\t@ 0xf8\n-\tvstr\td27, [r7, #256]\t@ 0x100\n-\tvstr\td17, [r7, #264]\t@ 0x108\n-\tbeq.n\t5804 <__gridxc_gga_MOD_ggaxc+0x1068>\n-\tvmov.f64\td18, d17\n-\tvmov.f64\td31, d27\n-\tvmov.f64\td30, d26\n-\tvmov.f64\td25, d20\n-\tvmov.f64\td22, d16\n-\tvmov.f64\td24, d19\n-\tvmov.f64\td29, d21\n-\tvmov.f64\td23, d28\n-\tb.n\t5656 <__gridxc_gga_MOD_ggaxc+0xeba>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tvldr\td4, [r3, #8]\n+\tvldr\td11, [r8, #24]\n+\tvldr\td10, [r8, #32]\n+\tvstr\td7, [r2]\n+\tvmul.f64\td4, d4, d6\n+\tvldr\td7, [r8, #40]\t@ 0x28\n+\tvmul.f64\td11, d11, d6\n+\tvmul.f64\td10, d10, d6\n+\tvstr\td2, [r7, #288]\t@ 0x120\n+\tvstr\td3, [r7, #296]\t@ 0x128\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td1, [r7, #304]\t@ 0x130\n+\tvstr\td5, [r7, #160]\t@ 0xa0\n+\tvstr\td2, [r7, #240]\t@ 0xf0\n+\tvstr\td3, [r7, #248]\t@ 0xf8\n+\tvstr\td1, [r7, #256]\t@ 0x100\n+\tvstr\td4, [r7, #184]\t@ 0xb8\n+\tvstr\td4, [r7, #168]\t@ 0xa8\n+\tvstr\td11, [r7, #312]\t@ 0x138\n+\tvstr\td11, [r7, #264]\t@ 0x108\n+\tvstr\td10, [r7, #320]\t@ 0x140\n+\tvstr\td10, [r7, #272]\t@ 0x110\n+\tvstr\td7, [r7, #328]\t@ 0x148\n+\tvstr\td7, [r7, #280]\t@ 0x118\n+\tbeq.n\t5d64 <__gridxc_gga_MOD_ggaxc+0x1098>\n+\tvmov.f64\td6, d7\n+\tvmov.f64\td14, d11\n+\tvmov.f64\td9, d1\n+\tvmov.f64\td0, d3\n+\tvmov.f64\td8, d2\n+\tvmov.f64\td13, d4\n+\tvstr\td10, [r7, #80]\t@ 0x50\n+\tb.n\t5b96 <__gridxc_gga_MOD_ggaxc+0xeca>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tadd.w\tfp, r7, #136\t@ 0x88\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tldr\tr3, [r7, #8]\n-\tldr.w\tr1, [pc, #1776]\t@ 5e38 <__gridxc_gga_MOD_ggaxc+0x169c>\n-\tmov\tr8, r0\n+\tldr\tr3, [r7, #28]\n+\tldr.w\tr1, [pc, #1212]\t@ 6160 <__gridxc_gga_MOD_ggaxc+0x1494>\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr.w\tr8, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #176\t@ 0xb0\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tadd.w\tr8, r7, #120\t@ 0x78\n-\tstr\tr3, [sp, #8]\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tadd.w\tr3, r7, #192\t@ 0xc0\n \tadd\tr1, pc\n-\tadd.w\tr3, r7, #200\t@ 0xc8\n-\tstr.w\tr8, [sp]\n+\tstr\tr3, [sp, #8]\n+\tstr.w\tfp, [sp]\n+\tadd.w\tr3, r7, #216\t@ 0xd8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-\tb.n\t54a2 <__gridxc_gga_MOD_ggaxc+0xd06>\n+\tb.n\t59de <__gridxc_gga_MOD_ggaxc+0xd12>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tb.w\t486e <__gridxc_gga_MOD_ggaxc+0xd2>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tb.w\t4da0 <__gridxc_gga_MOD_ggaxc+0xd4>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1dac <__gridxc_gga_MOD_wcxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tvsub.f64\td18, d23, d29\n-\tvadd.f64\td29, d23, d29\n-\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td20, #224\t@ 0xbf000000 -0.5\n-\tvldr\td16, [r7]\n-\tvmul.f64\td8, d8, d8\n-\tvmul.f64\td9, d9, d3\n-\tvmul.f64\td20, d12, d20\n-\tvmov.f64\td4, d29\n-\tvfms.f64\td29, d11, d18\n-\tvfma.f64\td4, d11, d18\n-\tvmul.f64\td18, d10, d18\n-\tvmul.f64\td16, d16, d16\n-\tvmov.f64\td5, d17\n-\tvmov.f64\td19, d17\n-\tvmov.f64\td7, d17\n-\tvmul.f64\td2, d18, d9\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td4, d4, d3\n-\tvmul.f64\td3, d29, d3\n-\tb.n\t5248 <__gridxc_gga_MOD_ggaxc+0xaac>\n-\tvsub.f64\td17, d28, d21\n-\tvadd.f64\td21, d28, d21\n-\tvmov.f64\td20, #224\t@ 0xbf000000 -0.5\n-\tvmul.f64\td9, d9, d18\n-\tvldr\td16, [r7]\n-\tvmul.f64\td8, d8, d8\n-\tvmul.f64\td20, d12, d20\n-\tvmov.f64\td7, d21\n-\tvfms.f64\td21, d11, d17\n-\tvfma.f64\td7, d11, d17\n-\tvmul.f64\td17, d10, d17\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td5, d17, d9\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td19, d21, d18\n-\tvmul.f64\td7, d7, d18\n-\tvmov.f64\td2, d5\n-\tvmov.f64\td18, d17\n-\tvmov.f64\td3, d19\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1f7c <__gridxc_gga_MOD_wcxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tvldr\td6, [r7, #16]\n+\tvmov.f64\td0, #224\t@ 0xbf000000 -0.5\n+\tvldr\td4, [r7, #8]\n+\tvmov.f64\td10, d7\n+\tvldr\td9, [r7, #40]\t@ 0x28\n+\tvmul.f64\td3, d6, d6\n+\tvldr\td6, [r7]\n+\tvmul.f64\td0, d9, d0\n+\tvmul.f64\td2, d6, d6\n+\tvsub.f64\td6, d5, d13\n+\tvadd.f64\td5, d5, d13\n+\tvmul.f64\td8, d4, d6\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td6, d15, d6\n+\tvmul.f64\td1, d12, d4\n+\tvadd.f64\td9, d5, d8\n+\tvsub.f64\td5, d5, d8\n+\tvmov.f64\td8, d7\n+\tvmul.f64\td11, d6, d1\n+\tvmul.f64\td6, d6, d0\n+\tvmul.f64\td9, d9, d4\n+\tvmul.f64\td5, d5, d4\n \tvmov.f64\td4, d7\n-\tb.n\t5248 <__gridxc_gga_MOD_ggaxc+0xaac>\n-\tvsub.f64\td17, d28, d21\n-\tvadd.f64\td21, d28, d21\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td20, #224\t@ 0xbf000000 -0.5\n-\tvldr\td16, [r7]\n-\tvmul.f64\td8, d8, d8\n-\tvmul.f64\td9, d9, d19\n-\tvmul.f64\td20, d12, d20\n-\tvmov.f64\td7, d21\n-\tvfms.f64\td21, d11, d17\n-\tvfma.f64\td7, d11, d17\n-\tvmul.f64\td17, d10, d17\n-\tvmul.f64\td16, d16, d16\n-\tvmov.f64\td2, d18\n-\tvmov.f64\td3, d18\n-\tvmov.f64\td4, d18\n-\tvmul.f64\td5, d17, d9\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td7, d7, d19\n-\tvmul.f64\td19, d21, d19\n-\tb.n\t5248 <__gridxc_gga_MOD_ggaxc+0xaac>\n-\tldr\tr0, [r7, #68]\t@ 0x44\n+\tb.n\t5784 <__gridxc_gga_MOD_ggaxc+0xab8>\n+\tvldr\td7, [r7, #16]\n+\tvmov.f64\td0, #224\t@ 0xbf000000 -0.5\n+\tvldr\td8, [r7, #40]\t@ 0x28\n+\tvmul.f64\td1, d12, d6\n+\tvmul.f64\td3, d7, d7\n+\tvldr\td7, [r7]\n+\tvmul.f64\td0, d8, d0\n+\tvmul.f64\td2, d7, d7\n+\tvsub.f64\td7, d5, d4\n+\tvadd.f64\td4, d5, d4\n+\tvldr\td5, [r7, #8]\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td7, d15, d7\n+\tvadd.f64\td8, d4, d5\n+\tvsub.f64\td4, d4, d5\n+\tvmul.f64\td10, d7, d1\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td8, d8, d6\n+\tvmul.f64\td4, d4, d6\n+\tvmov.f64\td11, d10\n+\tvmov.f64\td6, d7\n+\tvmov.f64\td5, d4\n+\tvmov.f64\td9, d8\n+\tb.n\t5784 <__gridxc_gga_MOD_ggaxc+0xab8>\n+\tvldr\td7, [r7, #16]\n+\tvmov.f64\td0, #224\t@ 0xbf000000 -0.5\n+\tvldr\td5, [r7, #72]\t@ 0x48\n+\tvmov.f64\td11, d6\n+\tvldr\td8, [r7, #40]\t@ 0x28\n+\tvmul.f64\td3, d7, d7\n+\tvldr\td7, [r7]\n+\tvmul.f64\td0, d8, d0\n+\tvmul.f64\td2, d7, d7\n+\tvsub.f64\td7, d5, d4\n+\tvadd.f64\td4, d5, d4\n+\tvldr\td5, [r7, #8]\n+\tvmul.f64\td9, d5, d7\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d15, d7\n+\tvmul.f64\td1, d12, d5\n+\tvadd.f64\td8, d4, d9\n+\tvsub.f64\td4, d4, d9\n+\tvmov.f64\td9, d6\n+\tvmul.f64\td10, d7, d1\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td8, d8, d5\n+\tvmul.f64\td4, d4, d5\n+\tvmov.f64\td5, d6\n+\tb.n\t5784 <__gridxc_gga_MOD_ggaxc+0xab8>\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tadd.w\tfp, r7, #136\t@ 0x88\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tldr\tr3, [r7, #8]\n-\tldr.w\tr1, [pc, #1416]\t@ 5e3c <__gridxc_gga_MOD_ggaxc+0x16a0>\n-\tmov\tr8, r0\n+\tldr\tr3, [r7, #28]\n+\tldr\tr1, [pc, #816]\t@ (6164 <__gridxc_gga_MOD_ggaxc+0x1498>)\n+\tmov\tr9, r0\n \tstr\tr3, [sp, #4]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr.w\tr8, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #176\t@ 0xb0\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tadd.w\tr8, r7, #120\t@ 0x78\n-\tstr\tr3, [sp, #8]\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tadd.w\tr3, r7, #192\t@ 0xc0\n \tadd\tr1, pc\n-\tadd.w\tr3, r7, #200\t@ 0xc8\n-\tstr.w\tr8, [sp]\n+\tstr\tr3, [sp, #8]\n+\tstr.w\tfp, [sp]\n+\tadd.w\tr3, r7, #216\t@ 0xd8\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_gga_exc_vxc\n-\tb.w\t4978 <__gridxc_gga_MOD_ggaxc+0x1dc>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tvmov.f64\td22, d16\n-\tvmov.f64\td23, d28\n-\tvmov.f64\td25, d20\n-\tvmov.f64\td24, d19\n-\tvstr\td28, [fp]\n-\tvstr\td17, [r3]\n-\tb.n\t5404 <__gridxc_gga_MOD_ggaxc+0xc68>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tvstr\td28, [fp]\n-\tvmov.f64\td22, d17\n-\tvmov.f64\td23, d17\n-\tvmov.f64\td25, d17\n-\tvmov.f64\td24, d17\n-\tvstr\td17, [r3]\n-\tb.n\t5404 <__gridxc_gga_MOD_ggaxc+0xc68>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tstr\tr3, [sp, #16]\n-\tadd.w\tr1, r7, #112\t@ 0x70\n+\tb.w\t4ea6 <__gridxc_gga_MOD_ggaxc+0x1da>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #96\t@ 0x60\n+\tvmov.f64\td0, d3\n+\tvmov.f64\td9, d1\n+\tvmov.f64\td8, d2\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tvstr\td5, [r3]\n+\tb.n\t5948 <__gridxc_gga_MOD_ggaxc+0xc7c>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tvldr\td7, [pc, #712]\t@ 6140 <__gridxc_gga_MOD_ggaxc+0x1474>\n+\tvmov.f64\td0, d7\n+\tvmov.f64\td5, d7\n+\tvmov.f64\td9, d7\n+\tvmov.f64\td8, d7\n+\tvstr\td7, [r3]\n+\tb.n\t5948 <__gridxc_gga_MOD_ggaxc+0xc7c>\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #240\t@ 0xf0\n+\tstr\tr3, [sp, #16]\n+\tadd.w\tr1, r7, #128\t@ 0x80\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tadd.w\tr0, r7, #112\t@ 0x70\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tstr\tr2, [sp, #32]\n-\tadd.w\tr2, r7, #272\t@ 0x110\n+\tadd.w\tr2, r7, #288\t@ 0x120\n \tstr\tr2, [sp, #28]\n-\tadd.w\tr2, r7, #144\t@ 0x90\n-\tstr\tr2, [sp, #24]\n \tadd.w\tr2, r7, #160\t@ 0xa0\n+\tstr\tr2, [sp, #24]\n+\tadd.w\tr2, r7, #176\t@ 0xb0\n \tstr\tr2, [sp, #20]\n-\tadd.w\tr2, r7, #320\t@ 0x140\n+\tadd.w\tr2, r7, #336\t@ 0x150\n \tstr\tr2, [sp, #8]\n-\tadd.w\tr2, r7, #128\t@ 0x80\n+\tadd.w\tr2, r7, #144\t@ 0x90\n \tstr\tr2, [sp, #4]\n-\tadd.w\tr2, r7, #92\t@ 0x5c\n+\tadd.w\tr2, r7, #108\t@ 0x6c\n \tstr\tr2, [sp, #0]\n-\tadd.w\tr2, r7, #104\t@ 0x68\n-\taddw\tr9, pc, #1212\t@ 0x4bc\n+\tadd.w\tr2, r7, #120\t@ 0x78\n+\taddw\tr9, pc, #628\t@ 0x274\n \tldrd\tr8, r9, [r9]\n \tstrd\tr8, r9, [r2, #-8]\n-\taddw\tr9, pc, #1208\t@ 0x4b8\n+\taddw\tr9, pc, #624\t@ 0x270\n \tldrd\tr8, r9, [r9]\n-\tstrd\tr8, r9, [r7, #112]\t@ 0x70\n-\taddw\tr9, pc, #1204\t@ 0x4b4\n+\tstrd\tr8, r9, [r7, #128]\t@ 0x80\n+\taddw\tr9, pc, #620\t@ 0x26c\n \tldrd\tr8, r9, [r9]\n \tstrd\tr8, r9, [r2]\n-\tbl\t3c0 <__gridxc_gga_MOD_pbeformxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #224\t@ 0xe0\n-\tstr\tr3, [sp, #0]\n-\tadd.w\tr1, r7, #128\t@ 0x80\n+\tbl\t3f8 <__gridxc_gga_MOD_pbeformxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr0, r7, #92\t@ 0x5c\n+\tadd.w\tr2, r7, #240\t@ 0xf0\n+\tstr\tr3, [sp, #0]\n+\tadd.w\tr1, r7, #144\t@ 0x90\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tadd.w\tr0, r7, #108\t@ 0x6c\n \tstr\tr2, [sp, #16]\n-\tadd.w\tr2, r7, #272\t@ 0x110\n+\tadd.w\tr2, r7, #288\t@ 0x120\n \tstr\tr2, [sp, #12]\n-\tadd.w\tr2, r7, #144\t@ 0x90\n-\tstr\tr2, [sp, #8]\n \tadd.w\tr2, r7, #160\t@ 0xa0\n+\tstr\tr2, [sp, #8]\n+\tadd.w\tr2, r7, #176\t@ 0xb0\n \tstr\tr2, [sp, #4]\n-\tadd.w\tr2, r7, #320\t@ 0x140\n-\tbl\t2d68 <__gridxc_gga_MOD_blypxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n+\tadd.w\tr2, r7, #336\t@ 0x150\n+\tbl\t3098 <__gridxc_gga_MOD_blypxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1a8c <__gridxc_gga_MOD_pw86x>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr.w\tr3, [pc, #1100]\t@ 5e40 <__gridxc_gga_MOD_ggaxc+0x16a4>\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1c34 <__gridxc_gga_MOD_pw86x>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tldr\tr3, [pc, #508]\t@ (6168 <__gridxc_gga_MOD_ggaxc+0x149c>)\n \tmovs\tr2, #3\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5a22 <__gridxc_gga_MOD_ggaxc+0x1286>\n-\tldr.w\tr3, [pc, #1080]\t@ 5e44 <__gridxc_gga_MOD_ggaxc+0x16a8>\n+\tcbz\tr0, 5f90 <__gridxc_gga_MOD_ggaxc+0x12c4>\n+\tldr\tr3, [pc, #496]\t@ (616c <__gridxc_gga_MOD_ggaxc+0x14a0>)\n \tmovs\tr2, #3\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t5bd2 <__gridxc_gga_MOD_ggaxc+0x1436>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tbne.w\t6170 <__gridxc_gga_MOD_ggaxc+0x14a4>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1414 <__gridxc_gga_MOD_b88x>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t158c <__gridxc_gga_MOD_b88x>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t4300 <__gridxc_gga_MOD_pbegcgxhegxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t4830 <__gridxc_gga_MOD_pbegcgxhegxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t43ac <__gridxc_gga_MOD_pbegcgxloxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t48dc <__gridxc_gga_MOD_pbegcgxloxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t4454 <__gridxc_gga_MOD_pbejsjrhegxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t4984 <__gridxc_gga_MOD_pbejsjrhegxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t44fc <__gridxc_gga_MOD_pbejsjrloxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t4a2c <__gridxc_gga_MOD_pbejsjrloxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1b00 <__gridxc_gga_MOD_am05xc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1ca8 <__gridxc_gga_MOD_am05xc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t45a4 <__gridxc_gga_MOD_pbesolxc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t4ad4 <__gridxc_gga_MOD_pbesolxc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t3838 <__gridxc_gga_MOD_pw91xc>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [pc, #628]\t@ (5e48 <__gridxc_gga_MOD_ggaxc+0x16ac>)\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t3c60 <__gridxc_gga_MOD_pw91xc>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\t...\n+\t.word\t0xbcd35a86\n+\t.word\t0x3fb114e3\n+\t.word\t0x7576bfc1\n+\t.word\t0x3fcc191d\n+\t.word\t0x1eb851ec\n+\t.word\t0x3ff3eb85\n+\t.word\t0x000004a8\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000320\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000001f2\n+ R_ARM_REL32\t.LC47\n+\t.word\t0x000001e4\n+ R_ARM_REL32\t.LC48\n+\tldr\tr3, [pc, #552]\t@ (639c <__gridxc_gga_MOD_ggaxc+0x16d0>)\n \tmovs\tr2, #6\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5bfa <__gridxc_gga_MOD_ggaxc+0x145e>\n-\tldr\tr3, [pc, #608]\t@ (5e4c <__gridxc_gga_MOD_ggaxc+0x16b0>)\n+\tcbz\tr0, 6194 <__gridxc_gga_MOD_ggaxc+0x14c8>\n+\tldr\tr3, [pc, #540]\t@ (63a0 <__gridxc_gga_MOD_ggaxc+0x16d4>)\n \tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 5c30 <__gridxc_gga_MOD_ggaxc+0x1494>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tcbnz\tr0, 61ca <__gridxc_gga_MOD_ggaxc+0x14fe>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t1330 <__gridxc_gga_MOD_b88kbmx>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [pc, #540]\t@ (5e50 <__gridxc_gga_MOD_ggaxc+0x16b4>)\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t14a8 <__gridxc_gga_MOD_b88kbmx>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tldr\tr3, [pc, #472]\t@ (63a4 <__gridxc_gga_MOD_ggaxc+0x16d8>)\n \tmovs\tr2, #3\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5c58 <__gridxc_gga_MOD_ggaxc+0x14bc>\n-\tldr\tr3, [pc, #524]\t@ (5e54 <__gridxc_gga_MOD_ggaxc+0x16b8>)\n+\tcbz\tr0, 61ee <__gridxc_gga_MOD_ggaxc+0x1522>\n+\tldr\tr3, [pc, #456]\t@ (63a8 <__gridxc_gga_MOD_ggaxc+0x16dc>)\n \tmovs\tr2, #3\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 5c8e <__gridxc_gga_MOD_ggaxc+0x14f2>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tcbnz\tr0, 6224 <__gridxc_gga_MOD_ggaxc+0x1558>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\tf48 <__gridxc_gga_MOD_c09x>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [pc, #456]\t@ (5e58 <__gridxc_gga_MOD_ggaxc+0x16bc>)\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1088 <__gridxc_gga_MOD_c09x>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tldr\tr3, [pc, #388]\t@ (63ac <__gridxc_gga_MOD_ggaxc+0x16e0>)\n \tmovs\tr2, #2\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5cb6 <__gridxc_gga_MOD_ggaxc+0x151a>\n-\tldr\tr3, [pc, #436]\t@ (5e5c <__gridxc_gga_MOD_ggaxc+0x16c0>)\n+\tcbz\tr0, 6248 <__gridxc_gga_MOD_ggaxc+0x157c>\n+\tldr\tr3, [pc, #376]\t@ (63b0 <__gridxc_gga_MOD_ggaxc+0x16e4>)\n \tmovs\tr2, #2\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 5cec <__gridxc_gga_MOD_ggaxc+0x1550>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tcbnz\tr0, 627e <__gridxc_gga_MOD_ggaxc+0x15b2>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n-\tbl\t14fc <__gridxc_gga_MOD_bhx>\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [pc, #368]\t@ (5e60 <__gridxc_gga_MOD_ggaxc+0x16c4>)\n+\tadd.w\tr3, r7, #336\t@ 0x150\n+\tbl\t1674 <__gridxc_gga_MOD_bhx>\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tldr\tr3, [pc, #308]\t@ (63b4 <__gridxc_gga_MOD_ggaxc+0x16e8>)\n \tmovs\tr2, #5\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5d14 <__gridxc_gga_MOD_ggaxc+0x1578>\n-\tldr\tr3, [pc, #352]\t@ (5e64 <__gridxc_gga_MOD_ggaxc+0x16c8>)\n+\tcbz\tr0, 62a2 <__gridxc_gga_MOD_ggaxc+0x15d6>\n+\tldr\tr3, [pc, #292]\t@ (63b8 <__gridxc_gga_MOD_ggaxc+0x16ec>)\n \tmovs\tr2, #5\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 5d4a <__gridxc_gga_MOD_ggaxc+0x15ae>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tcbnz\tr0, 62d8 <__gridxc_gga_MOD_ggaxc+0x160c>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n+\tadd.w\tr3, r7, #336\t@ 0x150\n \tbl\t0 <__gridxc_hybrids_MOD_hsexc>\n R_ARM_THM_CALL\t__gridxc_hybrids_MOD_hsexc\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tldr\tr3, [pc, #284]\t@ (5e68 <__gridxc_gga_MOD_ggaxc+0x16cc>)\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tldr\tr3, [pc, #224]\t@ (63bc <__gridxc_gga_MOD_ggaxc+0x16f0>)\n \tmovs\tr2, #4\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n-\tmov\tr1, r8\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 5d72 <__gridxc_gga_MOD_ggaxc+0x15d6>\n-\tldr\tr3, [pc, #264]\t@ (5e6c <__gridxc_gga_MOD_ggaxc+0x16d0>)\n+\tcbz\tr0, 62fc <__gridxc_gga_MOD_ggaxc+0x1630>\n+\tldr\tr3, [pc, #212]\t@ (63c0 <__gridxc_gga_MOD_ggaxc+0x16f4>)\n \tmovs\tr2, #4\n-\tldr.w\tr0, [r7, #520]\t@ 0x208\n-\tmov\tr1, r8\n+\tldr.w\tr0, [r7, #536]\t@ 0x218\n+\tmov\tr1, r9\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 5da8 <__gridxc_gga_MOD_ggaxc+0x160c>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd.w\tr2, r7, #128\t@ 0x80\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr1, r7, #92\t@ 0x5c\n+\tcbnz\tr0, 6332 <__gridxc_gga_MOD_ggaxc+0x1666>\n \tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr2, r7, #144\t@ 0x90\n+\tstr\tr3, [sp, #4]\n+\tadd.w\tr1, r7, #108\t@ 0x6c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tstr\tr3, [sp, #0]\n-\tadd.w\tr3, r7, #224\t@ 0xe0\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd.w\tr3, r7, #240\t@ 0xf0\n+\tldr\tr0, [r7, #60]\t@ 0x3c\n \tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r7, #272\t@ 0x110\n+\tadd.w\tr3, r7, #288\t@ 0x120\n \tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tstr\tr3, [sp, #12]\n \tadd.w\tr3, r7, #160\t@ 0xa0\n+\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, r7, #176\t@ 0xb0\n \tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r7, #320\t@ 0x140\n+\tadd.w\tr3, r7, #336\t@ 0x150\n \tbl\t0 <__gridxc_hybrids_MOD_pbe0xc>\n R_ARM_THM_CALL\t__gridxc_hybrids_MOD_pbe0xc\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tadd.w\tr8, r7, #112\t@ 0x70\n-\tadd.w\tr1, r7, #104\t@ 0x68\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\tadd.w\tfp, r7, #120\t@ 0x78\n+\tadd.w\tr8, r7, #128\t@ 0x80\n+\tmov\tr3, r9\n+\tmov\tr1, fp\n+\tldr.w\tr2, [r7, #536]\t@ 0x218\n \tmov\tr0, r8\n-\tldr.w\tr2, [r7, #520]\t@ 0x208\n-\tstr\tr1, [r7, #68]\t@ 0x44\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr.w\tr8, [r7, #112]\t@ 0x70\n+\tldr.w\tr8, [r7, #128]\t@ 0x80\n \tadd.w\tr9, r8, #22\n \tmov\tr0, r9\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [r7, #68]\t@ 0x44\n-\tmovs\tr2, #22\n-\tldr\tr3, [r1, #0]\n+\tldr\tr3, [pc, #100]\t@ (63c4 <__gridxc_gga_MOD_ggaxc+0x16f8>)\n+\tldr.w\tfp, [r7, #120]\t@ 0x78\n \tmov\tr1, r0\n-\tstrd\tr3, r0, [r7, #64]\t@ 0x40\n-\tmov\tr0, r9\n-\tstrd\tr8, r3, [sp]\n-\tldr\tr3, [pc, #136]\t@ (5e70 <__gridxc_gga_MOD_ggaxc+0x16d4>)\n+\tstr\tr0, [r7, #80]\t@ 0x50\n \tadd\tr3, pc\n+\tmovs\tr2, #22\n+\tmov\tr0, r9\n+\tstrd\tr8, fp, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tcmp.w\tr8, #0\n-\tble.n\t5df8 <__gridxc_gga_MOD_ggaxc+0x165c>\n-\tldr\tr0, [r7, #64]\t@ 0x40\n+\tble.n\t6380 <__gridxc_gga_MOD_ggaxc+0x16b4>\n+\tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #120]\t@ (5e74 <__gridxc_gga_MOD_ggaxc+0x16d8>)\n+\tldr\tr3, [pc, #68]\t@ (63c8 <__gridxc_gga_MOD_ggaxc+0x16fc>)\n \tmov\tr1, r9\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr.w\tr8, [r7, #68]\t@ 0x44\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tldr.w\tr8, [r7, #80]\t@ 0x50\n \tldr\tr3, [r2, r3]\n \tmov\tr0, r8\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.w\t4e5a <__gridxc_gga_MOD_ggaxc+0x6be>\n-\tnop.w\n-\t.word\t0xbcd35a86\n-\t.word\t0x3fb114e3\n-\t.word\t0x7576bfc1\n-\t.word\t0x3fcc191d\n-\t.word\t0x1eb851ec\n-\t.word\t0x3ff3eb85\n-\t.word\t0x00000998\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000089e\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000006d2\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000056c\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000043c\n- R_ARM_REL32\t.LC47\n-\t.word\t0x0000042a\n- R_ARM_REL32\t.LC48\n-\t.word\t0x00000266\n+\tb.w\t5362 <__gridxc_gga_MOD_ggaxc+0x696>\n+\t.word\t0x0000021e\n R_ARM_REL32\t.LC49\n-\t.word\t0x00000256\n- R_ARM_REL32\t.LC50\n \t.word\t0x00000210\n+ R_ARM_REL32\t.LC50\n+\t.word\t0x000001cc\n R_ARM_REL32\t.LC51\n-\t.word\t0x00000200\n+\t.word\t0x000001be\n R_ARM_REL32\t.LC52\n-\t.word\t0x000001ba\n+\t.word\t0x0000017a\n R_ARM_REL32\t.LC53\n-\t.word\t0x000001aa\n+\t.word\t0x0000016c\n R_ARM_REL32\t.LC54\n-\t.word\t0x00000164\n+\t.word\t0x00000128\n R_ARM_REL32\t.LC55\n-\t.word\t0x00000154\n+\t.word\t0x0000011a\n R_ARM_REL32\t.LC56\n-\t.word\t0x0000010e\n+\t.word\t0x000000d6\n R_ARM_REL32\t.LC57\n-\t.word\t0x000000fe\n+\t.word\t0x000000c8\n R_ARM_REL32\t.LC58\n-\t.word\t0x00000086\n+\t.word\t0x0000005a\n R_ARM_REL32\t.LC59\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "gridxc.F90.o", "source2": "gridxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 164 (bytes into file)\n+ Start of section headers: 160 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 7\n Section header string table index: 6\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,16 +1,16 @@\n-There are 7 section headers, starting at offset 0xa4:\n+There are 7 section headers, starting at offset 0xa0:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 000000 00 AX 0 0 1\n [ 2] .data PROGBITS 00000000 000034 000000 00 WA 0 0 1\n [ 3] .bss NOBITS 00000000 000034 000000 00 WA 0 0 1\n [ 4] .note.GNU-stack PROGBITS 00000000 000034 000000 00 0 0 1\n- [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 000034 000033 00 0 0 1\n- [ 6] .shstrtab STRTAB 00000000 000067 00003c 00 0 0 1\n+ [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 000034 00002d 00 0 0 1\n+ [ 6] .shstrtab STRTAB 00000000 000061 00003c 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "gridxc_config.F90.o", "source2": "gridxc_config.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 528 (bytes into file)\n+ Start of section headers: 524 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 10\n Section header string table index: 9\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,19 +1,19 @@\n-There are 10 section headers, starting at offset 0x210:\n+There are 10 section headers, starting at offset 0x20c:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 000028 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 0001a8 000018 08 I 7 1 4\n+ [ 2] .rel.text REL 00000000 0001a4 000018 08 I 7 1 4\n [ 3] .data PROGBITS 00000000 00005c 000004 00 WA 0 0 4\n [ 4] .bss NOBITS 00000000 000060 000004 00 WA 0 0 4\n [ 5] .note.GNU-stack PROGBITS 00000000 000060 000000 00 0 0 1\n- [ 6] .ARM.attributes ARM_ATTRIBUTES 00000000 000060 000033 00 0 0 1\n- [ 7] .symtab SYMTAB 00000000 000094 000090 10 8 5 4\n- [ 8] .strtab STRTAB 00000000 000124 000083 00 0 0 1\n- [ 9] .shstrtab STRTAB 00000000 0001c0 000050 00 0 0 1\n+ [ 6] .ARM.attributes ARM_ATTRIBUTES 00000000 000060 00002d 00 0 0 1\n+ [ 7] .symtab SYMTAB 00000000 000090 000090 10 8 5 4\n+ [ 8] .strtab STRTAB 00000000 000120 000083 00 0 0 1\n+ [ 9] .shstrtab STRTAB 00000000 0001bc 000050 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,6 +1,6 @@\n \n-Relocation section '.rel.text' at offset 0x1a8 contains 3 entries:\n+Relocation section '.rel.text' at offset 0x1a4 contains 3 entries:\n Offset Info Type Sym. Value Symbol's Name\n 0000001c 00000619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000020 0000071a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n 00000024 0000081a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "gridxc_fft_gpfa.F90.o", "source2": "gridxc_fft_gpfa.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 77700 (bytes into file)\n+ Start of section headers: 82600 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x12f84:\n+There are 12 section headers, starting at offset 0x142a8:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 011c7c 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 0129bc 000560 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 011cb4 000004 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 011cb8 00003c 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 011cb8 000250 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 011f08 000014 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 011f1c 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 011f1c 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 011f50 000620 10 10 69 4\n- [10] .strtab STRTAB 00000000 012570 00044b 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 012f1c 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 012988 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0136e0 000b60 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0129c0 000004 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 0129c4 000038 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0129c4 000250 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 012c14 000014 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 012c28 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 012c28 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 012c58 000610 10 10 65 4\n+ [10] .strtab STRTAB 00000000 013268 000476 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 014240 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,101 +1,100 @@\n \n-Symbol table '.symtab' contains 98 entries:\n+Symbol table '.symtab' contains 97 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n- 3: 00000001 12448 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0\n+ 3: 00000001 13110 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 5: 00001908 0 NOTYPE LOCAL DEFAULT 1 $d\n- 6: 00001918 0 NOTYPE LOCAL DEFAULT 1 $t\n- 7: 000030a1 6192 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0\n- 8: 00003380 0 NOTYPE LOCAL DEFAULT 1 $d\n- 9: 00003390 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 000048d1 15900 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0\n- 11: 00006860 0 NOTYPE LOCAL DEFAULT 1 $d\n- 12: 00006870 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 5: 00001be0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 6: 00001bf0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 7: 00003339 6270 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0\n+ 8: 00003648 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 00003658 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 10: 00004bb9 16162 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0\n+ 11: 00006aa8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 12: 00006ab8 0 NOTYPE LOCAL DEFAULT 1 $t\n 13: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 14: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 15: 00000044 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 16: 0000004c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 17: 00000054 0 NOTYPE LOCAL DEFAULT 5 .LC3\n- 18: 00008860 0 NOTYPE LOCAL DEFAULT 1 $d\n- 19: 0000886c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 20: 00008c30 0 NOTYPE LOCAL DEFAULT 1 $d\n- 21: 00008c40 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 0000aac0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 23: 0000aac8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 24: 0000ad50 0 NOTYPE LOCAL DEFAULT 1 $d\n- 25: 0000ad78 0 NOTYPE LOCAL DEFAULT 1 $t\n- 26: 0000b458 0 NOTYPE LOCAL DEFAULT 1 $d\n- 27: 0000b474 0 NOTYPE LOCAL DEFAULT 1 $t\n- 28: 0000bac8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 29: 0000baf0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 30: 000086ed 22074 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa_.localalias\n- 31: 0000dea8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 32: 0000deb4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 33: 0000e3e8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 34: 0000e410 0 NOTYPE LOCAL DEFAULT 1 $t\n- 35: 0000ee30 0 NOTYPE LOCAL DEFAULT 1 $d\n- 36: 0000ee7c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 37: 0000dd29 12946 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa_.localalias\n- 38: 00011210 0 NOTYPE LOCAL DEFAULT 1 $d\n- 39: 00011248 0 NOTYPE LOCAL DEFAULT 1 $t\n- 40: 000114a8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 41: 00011249 664 FUNC LOCAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_check.localalias\n- 42: 00000070 0 NOTYPE LOCAL DEFAULT 5 .LC4\n- 43: 0000008c 0 NOTYPE LOCAL DEFAULT 5 .LC5\n- 44: 000000ec 0 NOTYPE LOCAL DEFAULT 5 .LC6\n- 45: 000000f4 0 NOTYPE LOCAL DEFAULT 5 .LC7\n- 46: 0000011c 0 NOTYPE LOCAL DEFAULT 5 .LC8\n- 47: 00000174 0 NOTYPE LOCAL DEFAULT 5 .LC9\n- 48: 000001b8 0 NOTYPE LOCAL DEFAULT 5 .LC10\n- 49: 00000218 0 NOTYPE LOCAL DEFAULT 5 .LC11\n- 50: 000114e0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 51: 000114e1 448 FUNC LOCAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0\n- 52: 00011650 0 NOTYPE LOCAL DEFAULT 1 $d\n- 53: 000116a0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 54: 000117b0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 55: 000117c8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 56: 000118d8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 57: 000118f0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 58: 000119b8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 59: 000119dc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 60: 00011aa8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 61: 00000228 0 NOTYPE LOCAL DEFAULT 5 .LC14\n- 62: 00011acc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 63: 00011c48 0 NOTYPE LOCAL DEFAULT 1 $d\n- 64: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 65: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 66: 00000008 12 OBJECT LOCAL DEFAULT 6 iprime.0\n- 67: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 68: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_pow_i4_i4\n- 70: 000086ed 22074 FUNC GLOBAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa_\n- 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n- 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n- 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n- 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n- 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n- 79: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 81: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 82: 0000dd29 12946 FUNC GLOBAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa_\n- 83: 00010fbd 652 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa\n- 84: 00000000 0 NOTYPE GLOBAL DEFAULT UND sincos\n- 85: 00011249 664 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_check\n- 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_stop_string\n- 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n- 88: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n- 89: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n- 90: 000116a1 296 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_dp\n- 91: 000117c9 296 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_sp\n- 92: 000118f1 236 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n- 93: 000119dd 240 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp\n- 94: 00011acd 432 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_nfft\n- 95: 00000018 36 OBJECT GLOBAL HIDDEN 4 __gridxc_fft_gpfa_MOD_trigs\n- 96: 00000000 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fft_gpfa_MOD_nold\n- 97: 00000000 20 OBJECT GLOBAL HIDDEN 4 __gridxc_fft_gpfa_MOD_msg\n+ 18: 00008c60 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00008c6c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 20: 00008ff8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 00009008 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 22: 0000b1c0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 23: 0000b1f0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 24: 0000b6f0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 25: 0000b714 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 26: 00008add 23772 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa_.localalias\n+ 27: 0000e95c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 28: 0000e968 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 29: 0000ec60 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 30: 0000ec90 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 31: 0000f950 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 32: 0000f974 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 33: 0000e7b9 13596 FUNC LOCAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa_.localalias\n+ 34: 00011f30 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 35: 00011f68 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 36: 000121e0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 37: 00011f69 680 FUNC LOCAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_check.localalias\n+ 38: 00000070 0 NOTYPE LOCAL DEFAULT 5 .LC4\n+ 39: 0000008c 0 NOTYPE LOCAL DEFAULT 5 .LC5\n+ 40: 000000ec 0 NOTYPE LOCAL DEFAULT 5 .LC6\n+ 41: 000000f4 0 NOTYPE LOCAL DEFAULT 5 .LC7\n+ 42: 0000011c 0 NOTYPE LOCAL DEFAULT 5 .LC8\n+ 43: 00000174 0 NOTYPE LOCAL DEFAULT 5 .LC9\n+ 44: 000001b8 0 NOTYPE LOCAL DEFAULT 5 .LC10\n+ 45: 00000218 0 NOTYPE LOCAL DEFAULT 5 .LC11\n+ 46: 00012210 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 47: 00012211 412 FUNC LOCAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0\n+ 48: 00012374 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 49: 000123ac 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 50: 000124bc 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 51: 000124d4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 52: 000125e4 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 53: 000125fc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 54: 000126bc 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 55: 000126d8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 56: 00012798 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 57: 00000228 0 NOTYPE LOCAL DEFAULT 5 .LC14\n+ 58: 000127b4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 59: 0001295c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 60: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 61: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 62: 00000008 12 OBJECT LOCAL DEFAULT 6 iprime.0\n+ 63: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 64: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 65: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idiv\n+ 66: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_uidiv\n+ 67: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_pow_i4_i4\n+ 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idivmod\n+ 69: 00008add 23772 FUNC GLOBAL DEFAULT 1 __gridxc_gpfa_core_sp_MOD_gpfa_\n+ 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n+ 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n+ 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n+ 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 79: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 81: 0000e7b9 13596 FUNC GLOBAL DEFAULT 1 __gridxc_gpfa_core_dp_MOD_gpfa_\n+ 82: 00011cd5 660 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa\n+ 83: 00000000 0 NOTYPE GLOBAL DEFAULT UND sincos\n+ 84: 00011f69 680 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_setgpfa_check\n+ 85: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_stop_string\n+ 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n+ 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n+ 88: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n+ 89: 000123ad 296 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_dp\n+ 90: 000124d5 296 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_sp\n+ 91: 000125fd 220 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n+ 92: 000126d9 220 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp\n+ 93: 000127b5 468 FUNC GLOBAL DEFAULT 1 __gridxc_fft_gpfa_MOD_nfft\n+ 94: 00000014 36 OBJECT GLOBAL HIDDEN 4 __gridxc_fft_gpfa_MOD_trigs\n+ 95: 00000000 4 OBJECT GLOBAL HIDDEN 3 __gridxc_fft_gpfa_MOD_nold\n+ 96: 00000000 20 OBJECT GLOBAL HIDDEN 4 __gridxc_fft_gpfa_MOD_msg\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,175 +1,367 @@\n \n-Relocation section '.rel.text' at offset 0x129bc contains 172 entries:\n+Relocation section '.rel.text' at offset 0x136e0 contains 364 entries:\n Offset Info Type Sym. Value Symbol's Name\n-000030c0 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-00008860 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008864 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008868 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000088dc 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-0000aac0 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000aac4 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000ab76 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-0000b126 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-0000b132 00004a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-0000b138 00004b0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0000b14c 00004c0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000b162 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0000b17c 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000b18a 00004f0a R_ARM_THM_CALL 00000000 free\n-0000b1a0 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0000b1ba 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000b1c0 00004f0a R_ARM_THM_CALL 00000000 free\n-0000b1d4 00004f0a R_ARM_THM_CALL 00000000 free\n-0000b460 00000e03 R_ARM_REL32 00000000 .LC0\n-0000b464 00000f03 R_ARM_REL32 00000044 .LC1\n-0000b468 00001003 R_ARM_REL32 0000004c .LC2\n-0000b46c 00001103 R_ARM_REL32 00000054 .LC3\n-0000b470 0000501a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000dd10 0000510a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0000dea8 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000deac 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000deb0 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000df44 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-0000dfce 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-0000ed10 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-0000ed20 00004a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-0000ed2a 00004b0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0000ed38 00004c0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000ed4c 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0000ed66 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000ed82 00004f0a R_ARM_THM_CALL 00000000 free\n-0000edb2 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0000edce 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000edd4 00004f0a R_ARM_THM_CALL 00000000 free\n-0000edea 00004f0a R_ARM_THM_CALL 00000000 free\n-0000ee60 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000ee64 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000ee68 00000e03 R_ARM_REL32 00000000 .LC0\n-0000ee6c 00000f03 R_ARM_REL32 00000044 .LC1\n-0000ee70 00001003 R_ARM_REL32 0000004c .LC2\n-0000ee74 00001103 R_ARM_REL32 00000054 .LC3\n-0000ee78 0000501a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00010fb6 0000510a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0001104e 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-00011058 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-000110ec 0000540a R_ARM_THM_CALL 00000000 sincos\n-00011158 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00011162 00004a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00011168 00004b0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0001117a 00004c0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0001118c 00004d0a R_ARM_THM_CALL 00000000 malloc\n-000111a4 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000111ae 00004f0a R_ARM_THM_CALL 00000000 free\n-000111bc 00004d0a R_ARM_THM_CALL 00000000 malloc\n-000111d4 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000111da 00004f0a R_ARM_THM_CALL 00000000 free\n-000111ee 00004f0a R_ARM_THM_CALL 00000000 free\n-0001120a 0000510a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00011220 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00011224 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00011228 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0001122c 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00011230 00000e03 R_ARM_REL32 00000000 .LC0\n-00011234 00000203 R_ARM_REL32 00000000 .bss\n-00011238 00000f03 R_ARM_REL32 00000044 .LC1\n-0001123c 00001003 R_ARM_REL32 0000004c .LC2\n-00011240 00001103 R_ARM_REL32 00000054 .LC3\n-00011244 0000501a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000112e2 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-000112ec 0000450a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n-00011382 0000540a R_ARM_THM_CALL 00000000 sincos\n-000113f0 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000113fe 00004a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00011406 00004b0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00011412 00004c0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00011424 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0001143c 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00011446 00004f0a R_ARM_THM_CALL 00000000 free\n-00011454 00004d0a R_ARM_THM_CALL 00000000 malloc\n-0001146c 00004e0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00011472 00004f0a R_ARM_THM_CALL 00000000 free\n-00011484 00004f0a R_ARM_THM_CALL 00000000 free\n-000114a0 0000510a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000114b8 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000114bc 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000114c0 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000114c4 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000114c8 00000e03 R_ARM_REL32 00000000 .LC0\n-000114cc 00000203 R_ARM_REL32 00000000 .bss\n-000114d0 00000f03 R_ARM_REL32 00000044 .LC1\n-000114d4 00001003 R_ARM_REL32 0000004c .LC2\n-000114d8 00001103 R_ARM_REL32 00000054 .LC3\n-000114dc 0000501a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00011548 00004f0a R_ARM_THM_CALL 00000000 free\n-00011572 00004d0a R_ARM_THM_CALL 00000000 malloc\n-000115e6 00004d0a R_ARM_THM_CALL 00000000 malloc\n-00011610 0000560a R_ARM_THM_CALL 00000000 _gfortran_stop_string\n-00011614 0000510a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00011622 0000570a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00011632 0000580a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-0001163a 0000590a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-0001164a 0000570a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00011668 00000203 R_ARM_REL32 00000000 .bss\n-0001166c 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00011670 0000481a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00011674 00000203 R_ARM_REL32 00000000 .bss\n-00011678 00004719 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0001167c 00003103 R_ARM_REL32 00000218 .LC11\n-00011680 00002a03 R_ARM_REL32 00000070 .LC4\n-00011684 00003003 R_ARM_REL32 000001b8 .LC10\n-00011688 00002c03 R_ARM_REL32 000000ec .LC6\n-0001168c 00002d03 R_ARM_REL32 000000f4 .LC7\n-00011690 00002e03 R_ARM_REL32 0000011c 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R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a122 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a1a4 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a1ee 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a796 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a7b4 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a834 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000a876 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000addc 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000adf6 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000ae28 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000ae42 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000ae58 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000aeb4 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000aed0 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000af98 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000afa6 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000b10c 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000b128 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000b1ac 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000b56a 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000b5ba 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000b5c4 0000490a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+0000b5ca 00004a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000b5de 00004b0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+0000b5f0 00004c0a R_ARM_THM_CALL 00000000 malloc\n+0000b608 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000b612 00004e0a R_ARM_THM_CALL 00000000 free\n+0000b620 00004c0a R_ARM_THM_CALL 00000000 malloc\n+0000b638 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000b63e 00004e0a R_ARM_THM_CALL 00000000 free\n+0000b654 00004e0a R_ARM_THM_CALL 00000000 free\n+0000b660 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000b6f8 00000e03 R_ARM_REL32 00000000 .LC0\n+0000b6fc 00000f03 R_ARM_REL32 00000044 .LC1\n+0000b700 00001003 R_ARM_REL32 0000004c .LC2\n+0000b704 00001103 R_ARM_REL32 00000054 .LC3\n+0000b708 00004f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000b70c 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000b710 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000b9ea 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000bd88 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000c022 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000c04e 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000c0d2 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000c104 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000d054 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000e1b8 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000e1ee 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000e7b4 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000e870 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000e87e 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000e888 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000e95c 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000e960 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000e964 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000e9ca 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000ea36 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000ea44 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000ebb4 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000ebd0 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000ec48 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000efb2 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000f2ca 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000f61c 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000f854 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000f8a0 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000f8ac 0000490a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+0000f8b2 00004a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000f8c6 00004b0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+0000f8da 00004c0a R_ARM_THM_CALL 00000000 malloc\n+0000f8f4 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000f900 00004e0a R_ARM_THM_CALL 00000000 free\n+0000f910 00004c0a R_ARM_THM_CALL 00000000 malloc\n+0000f92c 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000f932 00004e0a R_ARM_THM_CALL 00000000 free\n+0000f948 00004e0a R_ARM_THM_CALL 00000000 free\n+0000f958 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000f95c 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000f960 00000e03 R_ARM_REL32 00000000 .LC0\n+0000f964 00000f03 R_ARM_REL32 00000044 .LC1\n+0000f968 00001003 R_ARM_REL32 0000004c .LC2\n+0000f96c 00001103 R_ARM_REL32 00000054 .LC3\n+0000f970 00004f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000f9a6 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000f9d0 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000fa46 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+0000fa90 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+000108d4 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+000116c6 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+000116fa 0000420a R_ARM_THM_CALL 00000000 __aeabi_uidiv\n+00011cd0 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00011d16 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00011d26 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00011d30 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00011d68 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00011d72 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00011dc4 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00011dca 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00011e0e 0000530a R_ARM_THM_CALL 00000000 sincos\n+00011e7e 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00011e88 0000490a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00011e8e 00004a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00011ea0 00004b0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00011eb2 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00011eca 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00011ed4 00004e0a R_ARM_THM_CALL 00000000 free\n+00011ee2 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00011efa 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00011f00 00004e0a R_ARM_THM_CALL 00000000 free\n+00011f12 00004e0a R_ARM_THM_CALL 00000000 free\n+00011f2a 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00011f40 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00011f44 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00011f48 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00011f4c 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00011f50 00000e03 R_ARM_REL32 00000000 .LC0\n+00011f54 00000203 R_ARM_REL32 00000000 .bss\n+00011f58 00000f03 R_ARM_REL32 00000044 .LC1\n+00011f5c 00001003 R_ARM_REL32 0000004c .LC2\n+00011f60 00001103 R_ARM_REL32 00000054 .LC3\n+00011f64 00004f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00011fbe 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00011fce 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00011fd8 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00012018 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00012022 0000430a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0001207a 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00012080 0000440a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000120be 0000530a R_ARM_THM_CALL 00000000 sincos\n+00012124 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00012132 0000490a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+0001213a 00004a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00012146 00004b0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00012158 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00012170 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0001217a 00004e0a R_ARM_THM_CALL 00000000 free\n+00012188 00004c0a R_ARM_THM_CALL 00000000 malloc\n+000121a0 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000121a6 00004e0a R_ARM_THM_CALL 00000000 free\n+000121ba 00004e0a R_ARM_THM_CALL 00000000 free\n+000121d6 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000121e8 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000121ec 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000121f0 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000121f4 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000121f8 00000e03 R_ARM_REL32 00000000 .LC0\n+000121fc 00000203 R_ARM_REL32 00000000 .bss\n+00012200 00000f03 R_ARM_REL32 00000044 .LC1\n+00012204 00001003 R_ARM_REL32 0000004c .LC2\n+00012208 00001103 R_ARM_REL32 00000054 .LC3\n+0001220c 00004f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00012278 00004e0a R_ARM_THM_CALL 00000000 free\n+000122a6 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00012310 00004c0a R_ARM_THM_CALL 00000000 malloc\n+00012334 0000550a R_ARM_THM_CALL 00000000 _gfortran_stop_string\n+00012338 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00012346 0000560a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00012356 0000570a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+0001235e 0000580a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+0001236e 0000560a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00012374 00000203 R_ARM_REL32 00000000 .bss\n+00012378 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0001237c 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00012380 00000203 R_ARM_REL32 00000000 .bss\n+00012384 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012388 00002d03 R_ARM_REL32 00000218 .LC11\n+0001238c 00002603 R_ARM_REL32 00000070 .LC4\n+00012390 00002c03 R_ARM_REL32 000001b8 .LC10\n+00012394 00002803 R_ARM_REL32 000000ec .LC6\n+00012398 00002903 R_ARM_REL32 000000f4 .LC7\n+0001239c 00002a03 R_ARM_REL32 0000011c .LC8\n+000123a0 00002b03 R_ARM_REL32 00000174 .LC9\n+000123a4 00002603 R_ARM_REL32 00000070 .LC4\n+000123a8 00002703 R_ARM_REL32 0000008c .LC5\n+000124b6 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000124bc 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000124c0 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000124c4 00000103 R_ARM_REL32 00000000 .data\n+000124c8 00000203 R_ARM_REL32 00000000 .bss\n+000124cc 00000103 R_ARM_REL32 00000000 .data\n+000124d0 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000125de 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000125e4 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000125e8 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000125ec 00000103 R_ARM_REL32 00000000 .data\n+000125f0 00000203 R_ARM_REL32 00000000 .bss\n+000125f4 00000103 R_ARM_REL32 00000000 .data\n+000125f8 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000126b8 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000126bc 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000126c0 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000126c4 00000103 R_ARM_REL32 00000000 .data\n+000126c8 00000203 R_ARM_REL32 00000000 .bss\n+000126cc 00003c03 R_ARM_REL32 00000000 .rodata\n+000126d0 00000103 R_ARM_REL32 00000000 .data\n+000126d4 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012792 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00012798 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0001279c 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000127a0 00000103 R_ARM_REL32 00000000 .data\n+000127a4 00000203 R_ARM_REL32 00000000 .bss\n+000127a8 00003c03 R_ARM_REL32 00000000 .rodata\n+000127ac 00000103 R_ARM_REL32 00000000 .data\n+000127b0 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012824 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00012832 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00012844 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00012896 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000128a0 0000490a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+000128a6 00004a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000128b6 00004b0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+000128c8 00004c0a R_ARM_THM_CALL 00000000 malloc\n+000128de 00004d0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0001291e 0000410a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00012936 00004e0a R_ARM_THM_CALL 00000000 free\n+00012956 0000500a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0001295c 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012960 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012964 0000471a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00012968 00003c03 R_ARM_REL32 00000000 .rodata\n+0001296c 00000e03 R_ARM_REL32 00000000 .LC0\n+00012970 00000203 R_ARM_REL32 00000000 .bss\n+00012974 00000f03 R_ARM_REL32 00000044 .LC1\n+00012978 00003903 R_ARM_REL32 00000228 .LC14\n+0001297c 00004f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00012980 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012984 00004619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00012910 00004e1e R_ARM_THM_JUMP24 00000000 free\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,28 +1,25 @@\n-DDBDCD@D\n-\\DZDYDXD\n-TDRDQDPD\n-vFwF8D9D\n+:\n __gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tmov\tr6, r1\n-\tmov\tr1, r3\n+\tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n-\tsub\tsp, #276\t@ 0x114\n-\tldrd\tr4, r3, [sp, #380]\t@ 0x17c\n-\tstr\tr2, [sp, #168]\t@ 0xa8\n+\tsub.w\tip, sp, ip\n+\tstr.w\tr0, [ip, #3512]\t@ 0xdb8\n+\tsub\tsp, #484\t@ 0x1e4\n+\tmov\tr7, r3\n+\tldrd\tr6, r3, [sp, #588]\t@ 0x24c\n+\tstr\tr2, [sp, #376]\t@ 0x178\n \tcmp\tr3, #31\n-\tbhi.w\t309e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x309e>\n+\tbhi.w\t3334 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3334>\n \tmov\tr2, r3\n \tmovs\tr3, #1\n-\tmov\tfp, r0\n-\tlsl.w\tr0, r3, r2\n-\tmul.w\tr3, r1, r4\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n-\tsubs\tr3, r0, r4\n-\tmul.w\tr3, r1, r3\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tsdiv\tr3, r4, r0\n-\tstr\tr3, [sp, #120]\t@ 0x78\n-\tmul.w\tr3, r1, r3\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tands.w\tr3, r2, #1\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tbne.w\t2b0a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b0a>\n+\tmov\tr8, r0\n+\tmov\tr5, r1\n+\tlsl.w\tr4, r3, r2\n+\tmov\tr0, r6\n+\tmov\tr1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r4, r6\n+\tstr\tr0, [sp, #320]\t@ 0x140\n+\tmul.w\tr3, r7, r3\n+\tstr\tr3, [sp, #300]\t@ 0x12c\n+\tmul.w\tr3, r7, r6\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tmov\tr3, r0\n+\tmul.w\tr3, r7, r3\n+\tstr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr3, [sp, #592]\t@ 0x250\n+\tands.w\tr3, r3, #1\n+\tstr\tr3, [sp, #352]\t@ 0x160\n+\tbne.w\t2ce0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ce0>\n+\tldr\tr2, [sp, #592]\t@ 0x250\n+\tstr\tr3, [sp, #348]\t@ 0x15c\n \tasrs\tr2, r2, #1\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tstr\tr2, [sp, #160]\t@ 0xa0\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tldr\tr3, [sp, #388]\t@ 0x184\n+\tstr\tr2, [sp, #368]\t@ 0x170\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tldr\tr3, [sp, #596]\t@ 0x254\n \tsubs\tr2, #1\n-\tvldr\ts15, [sp, #392]\t@ 0x188\n+\tvldr\ts15, [sp, #600]\t@ 0x258\n \taddw\tr3, r3, #1022\t@ 0x3fe\n \tit\tpl\n \tmovpl\tr3, r2\n-\tldr\tr5, [sp, #388]\t@ 0x184\n+\tldr\tr1, [sp, #596]\t@ 0x254\n \tasrs\tr2, r3, #10\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tvcvt.f64.s32\td8, s15\n+\tldr\tr3, [sp, #368]\t@ 0x170\n+\tvcvt.f64.s32\td7, s15\n \tadds\tr3, #1\n \tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #400]\t@ 0x190\n \tmovw\tr3, #64514\t@ 0xfc02\n \tmovt\tr3, #65535\t@ 0xffff\n-\tcmp\tr5, r3\n-\tblt.w\t2b00 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b00>\n-\tsubs\tr3, r4, #1\n+\tcmp\tr1, r3\n+\tvstr\td7, [sp, #360]\t@ 0x168\n+\tblt.w\t2fd0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fd0>\n+\tsubs\tr3, r6, #1\n+\tldr\tr0, [sp, #320]\t@ 0x140\n \tadds\tr2, #2\n-\tvmov\tr5, s15\n-\tstr\tr2, [sp, #236]\t@ 0xec\n-\tvmov.f64\td16, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tmul.w\tr4, r1, r3\n-\tadd.w\tr3, r0, r0, lsr #31\n-\tldr\tr0, [sp, #120]\t@ 0x78\n-\tmov\tsl, fp\n-\tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #200]\t@ 0xc8\n+\tstr\tr2, [sp, #456]\t@ 0x1c8\n \tnegs\tr2, r0\n-\tand.w\tr3, r0, #3\n+\tvmov.f64\td6, #240\t@ 0xbf800000 -1.0\n+\tmul.w\tr6, r7, r3\n+\tadd.w\tr3, r4, r4, lsr #31\n \tand.w\tr1, r2, #3\n-\tmov\tr8, r6\n+\tldr\tr4, [sp, #600]\t@ 0x258\n+\tmov.w\tr3, r3, asr #1\n+\tstr\tr3, [sp, #428]\t@ 0x1ac\n+\tand.w\tr3, r0, #3\n \tit\tpl\n \tnegpl\tr3, r1\n \tand.w\tr1, r2, #7\n \trsb\tr2, r3, #4\n-\tstr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp.w\tr5, #4294967295\t@ 0xffffffff\n+\tcmp.w\tr4, #4294967295\t@ 0xffffffff\n \tit\teq\n \tmoveq\tr3, r2\n-\tlsrs\tr2, r4, #31\n+\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n \tcmp\tr3, #3\n-\tstr\tr2, [sp, #180]\t@ 0xb4\n-\trsb\tr2, r4, #0\n-\tstr\tr2, [sp, #164]\t@ 0xa4\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\tvseleq.f64\td16, d16, d17\n+\tmov.w\tr2, r6, lsr #31\n+\tstr\tr2, [sp, #404]\t@ 0x194\n+\trsb\tr2, r6, #0\n+\tstr\tr2, [sp, #372]\t@ 0x174\n+\tmov\tsl, r8\n+\tit\teq\n+\tvmoveq.f64\td12, d6\n+\tldr\tr2, [sp, #584]\t@ 0x248\n \tnegs\tr3, r0\n \tand.w\tr3, r0, #7\n \tit\tpl\n \tnegpl\tr3, r1\n-\tstr\tr3, [sp, #204]\t@ 0xcc\n+\tstr\tr3, [sp, #432]\t@ 0x1b0\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #28]\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #436]\t@ 0x1b4\n+\tsub.w\tr3, r8, #8\n+\tstr\tr3, [sp, #344]\t@ 0x158\n+\tmov\tr9, r5\n+\tldr\tr3, [sp, #596]\t@ 0x254\n \tlsls\tr2, r2, #3\n-\tstr\tr3, [sp, #208]\t@ 0xd0\n-\tvneg.f64\td18, d16\n-\tldr\tr3, [sp, #388]\t@ 0x184\n-\tstr\tr2, [sp, #156]\t@ 0x9c\n+\tstr\tr6, [sp, #316]\t@ 0x13c\n+\tstr\tr2, [sp, #356]\t@ 0x164\n \tcmp.w\tr3, #1024\t@ 0x400\n-\tble.w\t220 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x220>\n+\titt\tle\n+\tmovle\tr3, #0\n+\tstrle\tr3, [sp, #424]\t@ 0x1a8\n+\tble.n\t130 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x130>\n \tcmp.w\tr3, #2048\t@ 0x800\n-\tblt.w\t15c6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x15c6>\n+\tblt.w\t2d0a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d0a>\n \tsub.w\tr3, r3, #1024\t@ 0x400\n-\tstr\tr3, [sp, #196]\t@ 0xc4\n+\tstr\tr3, [sp, #424]\t@ 0x1a8\n \tmov.w\tr3, #1024\t@ 0x400\n-\tstr\tr3, [sp, #388]\t@ 0x184\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #596]\t@ 0x254\n+\tldr\tr3, [sp, #400]\t@ 0x190\n \tcmp\tr3, #0\n-\tbne.w\t22c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x22c>\n+\tbne.w\t1304 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1304>\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr3, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tldr\tr3, [sp, #348]\t@ 0x15c\n \tcmp\tr3, #0\n-\tbeq.w\t15da <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x15da>\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tbeq.w\t18cc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18cc>\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tldr\tr4, [sp, #280]\t@ 0x118\n \tlsls\tr3, r3, #1\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tsdiv\tr2, r1, r3\n-\tsubs\tr3, r2, r1\n-\tmovs.w\tip, r2, lsl #1\n-\tstr\tr3, [sp, #4]\n-\tbmi.w\t2b90 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b90>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tudiv\tr1, r3, ip\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r4\n+\tmov\tr6, r0\n+\tmovs.w\tr8, r0, lsl #1\n+\tstr\tr3, [sp, #0]\n+\tbmi.w\t18b4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18b4>\n+\tmov\tr1, r8\n+\tldr\tr0, [sp, #316]\t@ 0x13c\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #404]\t@ 0x194\n+\tmov\tr1, r0\n \tcmp\tr3, #0\n-\tbne.n\t1f2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f2>\n-\tldr\tr3, [sp, #120]\t@ 0x78\n+\tbne.n\t21c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x21c>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n \tcmp\tr3, #0\n-\tble.n\t1f2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f2>\n-\tldr\tr3, [sp, #376]\t@ 0x178\n+\tble.n\t21c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x21c>\n+\tldr\tr3, [sp, #584]\t@ 0x248\n \tcmp\tr3, #1\n-\tbne.w\t620 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x620>\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tsub.w\tr7, sl, #8\n-\tldr\tr0, [sp, #28]\n+\tbne.w\t1260 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1260>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tldr\tr0, [sp, #140]\t@ 0x8c\n+\tldr.w\tfp, [sp, #596]\t@ 0x254\n \tadds\tr3, #1\n \tstr\tr3, [sp, #8]\n-\tmov\tr4, r0\n-\tmov.w\tlr, #1\n-\tldr\tr3, [sp, #4]\n-\tldr\tr5, [sp, #28]\n-\tadd\tr3, r4\n-\tcmp\tr5, r3\n-\tble.n\t172 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x172>\n-\tldr\tr5, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r5\n-\tldr\tr5, [sp, #388]\t@ 0x184\n-\tcmp\tr5, #0\n-\tble.n\t1d2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d2>\n-\tmov\tr6, r5\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr5, r4, #536870912\t@ 0x20000000\n-\tsubs\tr3, #1\n-\tsubs\tr5, #1\n-\tadd.w\tfp, r6, r4\n-\tlsls\tr3, r3, #3\n-\tlsls\tr5, r5, #3\n-\tadd.w\tr9, sl, r3\n-\tadd.w\tr6, sl, r5\n-\tadd.w\tfp, r7, fp, lsl #3\n-\tadd\tr5, r8\n-\tadd\tr3, r8\n-\tvldr\td21, [r9]\n-\tvldr\td19, [r6]\n-\tvldr\td17, [r5]\n-\tvldr\td20, [r3]\n-\tvadd.f64\td22, d21, d19\n-\tvsub.f64\td19, d19, d21\n-\tvadd.f64\td21, d20, d17\n-\tvsub.f64\td17, d17, d20\n-\tvstmia\tr6!, {d22}\n-\tcmp\tr6, fp\n-\tvstmia\tr9!, {d19}\n-\tvstmia\tr5!, {d21}\n-\tvstmia\tr3!, {d17}\n-\tbne.n\t19e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x19e>\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr3, r4\n-\tble.n\t1e0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1e0>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #8]\n-\tadd.w\tlr, lr, #1\n-\tcmp\tlr, r3\n-\tbne.n\t164 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x164>\n-\tsubs\tr1, #1\n-\tadd\tr0, ip\n-\tadds\tr6, r1, #1\n-\tbne.n\t15e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x15e>\n-\tldr\tr3, [sp, #384]\t@ 0x180\n-\tcmp\tr3, #1\n-\tbne.w\t6c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x6c8>\n-\tldr\tr3, [sp, #28]\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tldr\tr1, [sp, #376]\t@ 0x178\n-\tmla\tr3, r1, r2, r3\n-\tldr\tr2, [sp, #236]\t@ 0xec\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #208]\t@ 0xd0\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #208]\t@ 0xd0\n-\tcmp\tr3, r2\n-\tbeq.w\t2b00 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b00>\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n-\tstr\tr3, [sp, #388]\t@ 0x184\n-\tcmp.w\tr3, #1024\t@ 0x400\n-\tbgt.w\tf8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf8>\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #196]\t@ 0xc4\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tcmp\tr3, #0\n-\tbeq.w\t114 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x114>\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tmovs\tr3, #1\n-\tldr\tr6, [sp, #136]\t@ 0x88\n-\tldr.w\tr9, [sp, #28]\n-\tadd\tr2, r3\n-\tldr.w\tip, [sp, #124]\t@ 0x7c\n-\tldr.w\tfp, [sp, #156]\t@ 0x9c\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tstr\tr2, [sp, #8]\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tstr.w\tr8, [sp, #12]\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tmov\tr0, r3\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tsdiv\tr1, r2, r3\n-\tsubs\tr3, r1, r2\n-\tlsls\tr7, r1, #2\n-\tstr\tr3, [sp, #4]\n-\tbmi.w\t2ba6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ba6>\n-\tudiv\tr3, ip, r7\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tcmp\tr2, #0\n-\tbne.w\t3c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3c8>\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tcmp\tr2, #0\n-\tble.w\t3c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3c8>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\tcmp\tr2, #1\n-\tmov\tr2, r9\n-\tbne.w\t2706 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2706>\n-\tsub.w\tr4, sl, #8\n-\tstr\tr4, [sp, #24]\n-\tmov\tr8, r2\n-\tmovs\tr4, #1\n-\tstr\tr6, [sp, #32]\n-\tstr\tr4, [sp, #16]\n-\tstrd\tr3, r1, [sp, #40]\t@ 0x28\n-\tstrd\tr7, ip, [sp, #48]\t@ 0x30\n-\tstr\tr0, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #4]\n-\tadd\tr3, r8\n-\tcmp\tr9, r3\n-\tble.n\t2a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a4>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #4]\n-\tadd\tr1, r3\n-\tcmp\tr9, r1\n-\tble.n\t2b0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b0>\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r0\n-\tldr\tr0, [sp, #4]\n-\tadd\tr0, r1\n-\tcmp\tr9, r0\n-\tble.n\t2bc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bc>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r4\n-\tldr\tr4, [sp, #388]\t@ 0x184\n-\tcmp\tr4, #0\n-\tble.n\t398 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x398>\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tadd.w\tr1, r1, #536870912\t@ 0x20000000\n-\tsubs\tr3, #1\n-\tsubs\tr0, #1\n-\tadd.w\tr5, r8, #536870912\t@ 0x20000000\n-\tldr\tr6, [sp, #12]\n-\tadd.w\tlr, r4, r8\n-\tsubs\tr1, #1\n-\tldr\tr4, [sp, #24]\n-\tsubs\tr5, #1\n-\tlsls\tr3, r3, #3\n-\tlsls\tr0, r0, #3\n-\tlsls\tr1, r1, #3\n-\tlsls\tr5, r5, #3\n-\tadd.w\tr7, sl, r3\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #20]\n-\tadd.w\tr3, sl, r0\n-\tadd.w\tlr, r4, lr, lsl #3\n-\tadd.w\tip, sl, r1\n-\tadd.w\tr4, sl, r5\n-\tadd\tr1, r6\n-\tadd\tr5, r6\n-\tadd\tr0, r6\n-\tmov\tr6, r3\n-\tldr\tr3, [sp, #20]\n-\tvldr\td22, [r4]\n-\tvldr\td19, [ip]\n-\tvldr\td25, [r3]\n-\tvldr\td26, [r5]\n-\tvldr\td20, [r0]\n-\tvsub.f64\td23, d22, d19\n-\tvldr\td17, [r1]\n-\tvadd.f64\td19, d19, d22\n-\tvldr\td27, [r7]\n-\tvldr\td21, [r6]\n-\tvsub.f64\td24, d25, d20\n-\tvsub.f64\td22, d26, d17\n-\tvadd.f64\td20, d20, d25\n-\tvmov.f64\td25, d23\n-\tvadd.f64\td17, d17, d26\n-\tvsub.f64\td28, d27, d21\n-\tvadd.f64\td21, d21, d27\n-\tvfma.f64\td25, d24, d18\n-\tvfma.f64\td23, d16, d24\n-\tvmov.f64\td24, d22\n-\tvfma.f64\td24, d16, d28\n-\tvfma.f64\td22, d28, d18\n-\tvadd.f64\td26, d21, d19\n-\tvsub.f64\td19, d19, d21\n-\tvadd.f64\td21, d20, d17\n-\tvsub.f64\td17, d17, d20\n-\tvstmia\tr4!, {d26}\n-\tcmp\tr4, lr\n-\tvstmia\tr5!, {d21}\n-\tvstmia\tip!, {d19}\n-\tvstmia\tr1!, {d17}\n-\tvstmia\tr7!, {d25}\n-\tvstmia\tr3!, {d24}\n-\tvstmia\tr6!, {d23}\n-\tvstmia\tr0!, {d22}\n-\tbne.n\t30c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x30c>\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr8, r3\n-\tcmp\tr9, r8\n-\tble.n\t3a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3a4>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr8, r3\n-\tldr\tr3, [sp, #16]\n-\tldr\tr1, [sp, #8]\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #16]\n-\tcmp\tr3, r1\n-\tbne.w\t298 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x298>\n-\tldrd\tr3, r1, [sp, #40]\t@ 0x28\n-\tldrd\tr7, ip, [sp, #48]\t@ 0x30\n-\tsubs\tr3, #1\n-\tldr\tr6, [sp, #32]\n-\tadds\tr5, r3, #1\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tadd\tr2, r7\n-\tbne.w\t286 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x286>\n-\tldr\tr3, [sp, #384]\t@ 0x180\n-\tcmp\tr3, #2\n-\tbeq.w\t2870 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2870>\n-\tlsls\tr3, r0, #1\n-\tsubs\tr2, r1, r6\n-\tcmp\tr6, #0\n-\tblt.w\t2aee <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2aee>\n-\tsubs\tr1, r2, r6\n-\tcmp\tr6, r2\n-\tudiv\tr1, r1, r6\n-\tstr\tr1, [sp, #16]\n-\tbgt.w\t2ac8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac8>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\tcmp\tr2, #1\n-\tmov.w\tr2, #24\n-\tmul.w\tr2, r2, r3\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tbne.w\t288a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x288a>\n-\tldr\tr4, [sp, #168]\t@ 0xa8\n-\tlsls\tr0, r3, #3\n-\tsub.w\tr8, ip, r6\n-\tlsls\tr3, r3, #4\n-\tadds\tr1, r4, r0\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tlr, r1, r0\n-\tadd.w\tr3, r2, #8\n-\tstr\tr0, [sp, #48]\t@ 0x30\n-\tmov\tr0, r8\n-\tldr.w\tr8, [sp, #12]\n-\tadd\tr3, r4\n-\tmov\tr2, lr\n-\tsub.w\tr4, r6, ip\n-\tstr\tr4, [sp, #32]\n-\tmov\tr4, r6\n-\tsub.w\tr5, sl, #8\n-\tstr\tr5, [sp, #20]\n-\tvldr\td29, [r1, #8]\n-\tcmp\tr7, #0\n-\tvldr\td28, [r2, #8]\n-\tvldr\td27, [r3]\n-\tvmul.f64\td29, d8, d29\n-\tvldr\td7, [r1]\n-\tvmul.f64\td28, d8, d28\n-\tvldr\td31, [r2]\n-\tvmul.f64\td27, d8, d27\n-\tvldr\td30, [r3, #-8]\n-\tblt.w\t2878 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2878>\n-\tudiv\tr1, r0, r7\n-\tcmp\tip, r4\n-\tblt.w\t5f8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x5f8>\n-\tldr\tr5, [sp, #120]\t@ 0x78\n-\tcmp\tr5, #0\n-\tble.w\t5f8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x5f8>\n-\tadd.w\tr5, r9, r4\n-\tstrd\tr6, ip, [sp, #52]\t@ 0x34\n-\tstr\tr5, [sp, #24]\n-\tstrd\tr4, r2, [sp, #60]\t@ 0x3c\n-\tstrd\tr0, r3, [sp, #68]\t@ 0x44\n-\tstrd\tfp, lr, [sp, #76]\t@ 0x4c\n-\tldr.w\tlr, [sp, #24]\n-\tmov.w\tfp, #1\n-\tstrd\tr7, r1, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #4]\n-\tadd\tr3, lr\n-\tcmp\tr9, r3\n-\tble.n\t494 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x494>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tmov\tr2, r0\n+\tmovs\tr7, #1\n+\tldr\tr3, [sp, #0]\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #4]\n-\tadd\tr2, r3\n-\tcmp\tr9, r2\n-\tble.n\t4a0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4a0>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #4]\n-\tadds\tr0, r1, r2\n-\tcmp\tr9, r0\n-\tble.n\t4ac <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4ac>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r1\n-\tldr\tr1, [sp, #388]\t@ 0x184\n-\tcmp\tr1, #0\n-\tble.w\t5be <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x5be>\n-\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tcmp\tr4, r3\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r4\n+\tcmp.w\tfp, #0\n+\tble.n\t1fe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fe>\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tadd.w\tr4, lr, #536870912\t@ 0x20000000\n-\tadd.w\tip, r1, lr\n-\tsubs\tr2, #1\n-\tldr\tr1, [sp, #20]\n+\tadd.w\tr4, r2, #536870912\t@ 0x20000000\n+\tldr\tr5, [sp, #344]\t@ 0x158\n \tsubs\tr3, #1\n-\tsubs\tr0, #1\n \tsubs\tr4, #1\n-\tlsls\tr2, r2, #3\n+\tadd.w\tlr, fp, r2\n \tlsls\tr3, r3, #3\n-\tlsls\tr0, r0, #3\n \tlsls\tr4, r4, #3\n-\tadd.w\tip, r1, ip, lsl #3\n-\tadd.w\tr7, sl, r2\n-\tadd.w\tr1, sl, r4\n-\tadd.w\tr6, sl, r3\n-\tadd.w\tr5, sl, r0\n-\tadd\tr4, r8\n-\tadd\tr2, r8\n-\tadd\tr3, r8\n-\tadd\tr0, r8\n-\tvldr\td23, [r4]\n-\tvldr\td17, [r2]\n-\tvldr\td24, [r6]\n-\tvldr\td26, [r3]\n-\tvldr\td25, [r1]\n-\tvsub.f64\td20, d23, d17\n-\tvldr\td22, [r5]\n-\tvsub.f64\td21, d17, d23\n-\tvldr\td19, [r0]\n-\tvadd.f64\td17, d17, d23\n-\tvldr\td5, [r7]\n-\tvsub.f64\td6, d24, d22\n-\tvmov.f64\td23, d20\n-\tvsub.f64\td4, d26, d19\n-\tvadd.f64\td19, d19, d26\n-\tvsub.f64\td26, d25, d5\n-\tvadd.f64\td22, d22, d24\n-\tvadd.f64\td5, d5, d25\n-\tvfma.f64\td23, d16, d6\n-\tvfma.f64\td21, d16, d6\n-\tvfma.f64\td20, d6, d18\n-\tvsub.f64\td25, d19, d17\n-\tvmov.f64\td6, d26\n-\tvfma.f64\td26, d16, d4\n-\tvfma.f64\td6, d4, d18\n-\tvsub.f64\td24, d17, d19\n-\tvsub.f64\td4, d5, d22\n-\tvmul.f64\td25, d25, d28\n-\tvadd.f64\td19, d19, d17\n-\tvadd.f64\td22, d22, d5\n-\tvmul.f64\td24, d24, d31\n-\tvnmul.f64\td5, d29, d23\n-\tvmul.f64\td21, d21, d27\n-\tvmul.f64\td23, d23, d7\n-\tvmul.f64\td17, d20, d30\n-\tvfma.f64\td25, d4, d31\n-\tvfma.f64\td24, d4, d28\n-\tvfma.f64\td5, d6, d7\n-\tvfma.f64\td23, d6, d29\n-\tvfma.f64\td21, d26, d30\n-\tvfma.f64\td17, d26, d27\n-\tvstmia\tr1!, {d22}\n-\tcmp\tr1, ip\n-\tvstmia\tr4!, {d19}\n-\tvstmia\tr6!, {d5}\n-\tvstmia\tr3!, {d23}\n-\tvstmia\tr7!, {d25}\n-\tvstmia\tr2!, {d24}\n-\tvstmia\tr5!, {d21}\n-\tvstmia\tr0!, {d17}\n-\tbne.n\t4f6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4f6>\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tlr, r3\n-\tcmp\tr9, lr\n-\tble.n\t5ca <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x5ca>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tlr, r3\n+\tadd.w\tlr, r5, lr, lsl #3\n+\tadd.w\tip, sl, r3\n+\tadd.w\tr5, sl, r4\n+\tadd\tr3, r9\n+\tadd\tr4, r9\n+\tvldr\td4, [ip]\n+\tvldr\td6, [r5]\n+\tvldr\td7, [r4]\n+\tvldr\td5, [r3]\n+\tvadd.f64\td3, d4, d6\n+\tvsub.f64\td6, d6, d4\n+\tvadd.f64\td4, d5, d7\n+\tvsub.f64\td7, d7, d5\n+\tvstmia\tr5!, {d3}\n+\tcmp\tr5, lr\n+\tvstmia\tip!, {d6}\n+\tvstmia\tr4!, {d4}\n+\tvstmia\tr3!, {d7}\n+\tbne.n\t1ca <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ca>\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n+\tadds\tr7, #1\n+\tadd\tr2, r3\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, r2\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r3\n \tldr\tr3, [sp, #8]\n-\tadd.w\tfp, fp, #1\n-\tcmp\tfp, r3\n-\tbne.w\t488 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x488>\n-\tldrd\tr7, r1, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #24]\n-\tsubs\tr1, #1\n-\tadd\tr3, r7\n-\tadds\tr0, r1, #1\n-\tstr\tr3, [sp, #24]\n-\tbne.w\t47c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x47c>\n-\tldrd\tr6, ip, [sp, #52]\t@ 0x34\n-\tldrd\tr4, r2, [sp, #60]\t@ 0x3c\n-\tldrd\tr0, r3, [sp, #68]\t@ 0x44\n-\tldrd\tfp, lr, [sp, #76]\t@ 0x4c\n-\tadd\tr4, r6\n-\tldr\tr1, [sp, #16]\n-\tsubs\tr0, r0, r6\n+\tcmp\tr7, r3\n+\tbne.n\t190 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x190>\n \tsubs\tr1, #1\n-\tstr\tr1, [sp, #16]\n-\tmov\tr5, r1\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tadds\tr5, #1\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #32]\n-\tadd\tr1, r6\n-\tstr\tr1, [sp, #32]\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r1\n-\tmov\tr1, lr\n-\tbeq.w\t2ac8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac8>\n-\tldr\tr5, [sp, #48]\t@ 0x30\n-\tadd\tlr, r5\n-\tb.n\t42a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x42a>\n-\tldr\tr0, [sp, #120]\t@ 0x78\n-\tldr\tr3, [sp, #28]\n-\tadds\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tldr\tr0, [sp, #388]\t@ 0x184\n-\tadds\tr7, r0, #1\n-\tldr.w\tr9, [sp, #148]\t@ 0x94\n-\tmov\tr4, r3\n-\tldr\tr0, [sp, #4]\n-\tldr\tr5, [sp, #28]\n-\tadd\tr0, r4\n-\tcmp\tr0, r5\n-\tbge.n\t640 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x640>\n-\tldr\tr5, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r5\n-\tldr\tr5, [sp, #388]\t@ 0x184\n-\tcmp\tr5, #0\n-\tble.n\t6a0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x6a0>\n-\tlsls\tr0, r0, #3\n-\tlsls\tr5, r4, #3\n-\tldr.w\tfp, [sp, #148]\t@ 0x94\n-\tadd.w\tlr, sl, r5\n-\tadd.w\tr6, sl, r0\n-\tadd\tr5, r8\n \tadd\tr0, r8\n-\tstr\tr3, [sp, #12]\n-\tvldr\td21, [r6, #-8]\n-\tadd.w\tfp, fp, #1\n-\tvldr\td19, [lr, #-8]\n-\tcmp\tfp, r7\n-\tvldr\td17, [r5, #-8]\n-\tvldr\td20, [r0, #-8]\n-\tvadd.f64\td22, d19, d21\n-\tvsub.f64\td19, d19, d21\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n-\tvadd.f64\td21, d17, d20\n-\tvsub.f64\td17, d17, d20\n-\tvstr\td22, [lr, #-8]\n-\tadd\tlr, r3\n-\tvstr\td19, [r6, #-8]\n-\tadd\tr6, r3\n-\tvstr\td21, [r5, #-8]\n-\tadd\tr5, r3\n-\tvstr\td17, [r0, #-8]\n-\tadd\tr0, r3\n-\tbne.n\t65c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x65c>\n-\tldr\tr3, [sp, #12]\n-\tldr\tr0, [sp, #112]\t@ 0x70\n-\tadd\tr4, r0\n-\tldr\tr0, [sp, #28]\n-\tcmp\tr4, r0\n-\tbge.n\t6ae <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x6ae>\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r0\n-\tldr\tr0, [sp, #8]\n-\tadd.w\tr9, r9, #1\n-\tcmp\tr9, r0\n-\tbne.n\t632 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x632>\n-\tsubs\tr1, #1\n-\tadd\tr3, ip\n-\tadds\tr5, r1, #1\n-\tbne.n\t62c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x62c>\n-\tldr\tr3, [sp, #384]\t@ 0x180\n+\tadds\tr4, r1, #1\n+\tbne.n\t18c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18c>\n+\tldr\tr3, [sp, #592]\t@ 0x250\n \tcmp\tr3, #1\n-\tbeq.w\t1fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa>\n-\tldr\tr0, [sp, #136]\t@ 0x88\n-\tsubs\tr3, r2, r0\n-\tcmp\tr0, #0\n-\tblt.w\t2bca <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bca>\n-\tsubs\tr2, r3, r0\n-\tcmp\tr0, r3\n-\tudiv\tr2, r2, r0\n-\tbgt.w\t81a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x81a>\n-\tldr\tr0, [sp, #140]\t@ 0x8c\n-\tldr\tr3, [sp, #376]\t@ 0x178\n-\tmov.w\tr9, r0, lsl #3\n+\tbeq.w\t1f12 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f12>\n+\tldr\tr4, [sp, #332]\t@ 0x14c\n+\tsubs\tr6, r6, r4\n+\tcmp\tr4, #0\n+\tblt.w\t2b78 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b78>\n+\tmov\tr1, r4\n+\tsubs\tr0, r6, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r6\n+\tmov\tr7, r0\n+\tbgt.w\t378 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x378>\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tldr\tr3, [sp, #584]\t@ 0x248\n+\tmov.w\tfp, r2, lsl #3\n \tcmp\tr3, #1\n-\tbne.w\t2be6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2be6>\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tmov\tfp, r0\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tsub.w\tlr, sl, #8\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n-\trsb\tr5, ip, #0\n-\tldr\tr0, [sp, #120]\t@ 0x78\n-\tsubs\tr6, r4, r1\n-\tsubs\tr7, r1, r4\n-\tadd\tr3, r9\n-\tmov\tr4, r2\n-\tadds\tr0, #1\n-\tstr\tr0, [sp, #8]\n-\tvldr\td23, [r3, #8]\n-\tcmp.w\tip, #0\n-\tvldr\td24, [r3]\n-\tvmul.f64\td23, d8, d23\n-\tblt.w\t2bba <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bba>\n-\tudiv\tr0, r6, ip\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tcmp\tr2, r1\n-\tblt.n\t804 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x804>\n-\tldr\tr2, [sp, #120]\t@ 0x78\n-\tcmp\tr2, #0\n-\tble.n\t804 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x804>\n-\tldr\tr2, [sp, #28]\n-\tstr.w\tr9, [sp, #20]\n-\tmov\tr9, r6\n-\tadd\tr2, r1\n-\tmov\tr6, r7\n-\tstrd\tr4, r1, [sp, #12]\n-\tmov\tr4, r2\n+\tbne.w\t2b96 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b96>\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr0, [sp, #376]\t@ 0x178\n+\tldr\tr1, [sp, #316]\t@ 0x13c\n+\tmov\tr4, r3\n+\tstr\tr2, [sp, #8]\n+\tadd.w\tr5, r0, fp\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tsubs\tr6, r1, r3\n+\tsubs\tr1, r3, r1\n+\tstr\tr1, [sp, #20]\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #24]\n+\trsb\tr2, r8, #0\n+\tstr\tr2, [sp, #28]\n+\tvldr\td8, [r5, #8]\n+\tcmp.w\tr8, #0\n+\tvldr\td7, [sp, #360]\t@ 0x168\n+\tvldr\td9, [r5]\n+\tvmul.f64\td8, d7, d8\n+\tblt.w\t2b64 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b64>\n+\tmov\tr1, r8\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tcmp\tr3, r4\n+\tblt.n\t35a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x35a>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tcmp\tr3, #0\n+\tble.n\t35a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x35a>\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tstr\tr7, [sp, #128]\t@ 0x80\n+\tadd.w\tip, r3, r4\n+\tmov\tr1, ip\n \tmovs\tr7, #1\n-\tstr.w\tip, [sp, #24]\n-\tstrd\tr0, r2, [sp, #32]\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #28]\n-\tadd\tr3, r4\n+\tstr.w\tr8, [sp, #32]\n+\tstr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tadd\tr3, r1\n+\tldr\tr0, [sp, #8]\n \tcmp\tr2, r3\n-\tble.n\t75a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x75a>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #200]\t@ 0xc8\n-\tcmp\tr2, fp\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tbeq.w\t2b26 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b26>\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #428]\t@ 0x1ac\n+\tcmp\tr2, r0\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tbeq.w\t2af6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2af6>\n \tcmp\tr2, #0\n-\tble.n\t7d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x7d0>\n-\tmov\tr1, r2\n+\tble.n\t334 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x334>\n+\tmov\tr0, r2\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr2, r4, #536870912\t@ 0x20000000\n+\tadd.w\tr2, r1, #536870912\t@ 0x20000000\n+\tadd.w\tlr, r0, r1\n \tsubs\tr3, #1\n+\tldr\tr0, [sp, #344]\t@ 0x158\n \tsubs\tr2, #1\n-\tadds\tr0, r1, r4\n \tlsls\tr3, r3, #3\n \tlsls\tr2, r2, #3\n-\tadd.w\tr1, lr, r0, lsl #3\n-\tadd.w\tip, sl, r3\n-\tadd.w\tr0, sl, r2\n-\tadd\tr3, r8\n-\tadd\tr2, r8\n-\tvldr\td22, [r2]\n-\tvldr\td19, [r3]\n-\tvldr\td21, [r0]\n-\tvldr\td20, [ip]\n-\tvsub.f64\td17, d22, d19\n-\tvadd.f64\td19, d19, d22\n-\tvsub.f64\td22, d21, d20\n-\tvadd.f64\td20, d20, d21\n-\tvnmul.f64\td21, d23, d17\n-\tvmul.f64\td17, d17, d24\n-\tvstmia\tr2!, {d19}\n-\tvfma.f64\td21, d22, d24\n-\tvfma.f64\td17, d22, d23\n-\tvstmia\tr0!, {d20}\n-\tcmp\tr0, r1\n-\tvstmia\tip!, {d21}\n-\tvstmia\tr3!, {d17}\n-\tbne.n\t78c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x78c>\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr3, r4\n-\tble.n\t7de <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x7de>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #8]\n+\tadd.w\tr0, r0, lr, lsl #3\n+\tadd.w\tr8, sl, r3\n+\tadd.w\tlr, sl, r2\n+\tadd\tr3, r9\n+\tadd\tr2, r9\n+\tvldr\td4, [r2]\n+\tvldr\td6, [r3]\n+\tvldr\td5, [lr]\n+\tvldr\td7, [r8]\n+\tvsub.f64\td3, d4, d6\n+\tvadd.f64\td6, d6, d4\n+\tvsub.f64\td4, d5, d7\n+\tvadd.f64\td7, d7, d5\n+\tvmul.f64\td5, d3, d8\n+\tvstmia\tr2!, {d6}\n+\tvmul.f64\td6, d4, d8\n+\tvstmia\tlr!, {d7}\n+\tvmla.f64\td6, d3, d9\n+\tcmp\tlr, r0\n+\tvnmls.f64\td5, d4, d9\n+\tvstmia\tr3!, {d6}\n+\tvstmia\tr8!, {d5}\n+\tbne.n\t2f0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f0>\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n \tadds\tr7, #1\n+\tadd\tr1, r3\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, r1\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #24]\n \tcmp\tr7, r3\n-\tbne.n\t74c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x74c>\n-\tldrd\tr0, r2, [sp, #32]\n-\tldr.w\tip, [sp, #24]\n+\tbne.n\t2aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2aa>\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr.w\tr8, [sp, #32]\n \tsubs\tr0, #1\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadd\tr2, ip\n-\tadds\tr1, r0, #1\n-\tbne.n\t73e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x73e>\n-\tmov\tr7, r6\n-\tmov\tr6, r9\n-\tldrd\tr4, r1, [sp, #12]\n-\tldr.w\tr9, [sp, #20]\n-\tldr\tr2, [sp, #140]\t@ 0x8c\n-\tsubs\tr4, #1\n-\tadd\tr3, r9\n-\tadd\tfp, r2\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tadd\tr1, r2\n-\tsubs\tr6, r6, r2\n-\tadd\tr7, r2\n-\tadds\tr2, r4, #1\n-\tbne.w\t70a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x70a>\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tadd\tip, r8\n+\tadds\tr2, r0, #1\n+\tbne.n\t2a0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a0>\n+\tldr\tr7, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #8]\n+\tsubs\tr7, #1\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tadd\tr5, fp\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #20]\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tadd\tr2, r3\n+\tadd\tr4, r3\n+\tsubs\tr6, r6, r3\n+\tstr\tr2, [sp, #20]\n+\tadds\tr3, r7, #1\n+\tbne.w\t26c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26c>\n+\tldr\tr3, [sp, #400]\t@ 0x190\n+\tadd.w\tfp, r3, #1\n+\tldr\tr3, [sp, #368]\t@ 0x170\n+\tcmp\tr3, fp\n+\tblt.w\t1f12 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f12>\n+\tldr\tr3, [sp, #596]\t@ 0x254\n+\tmov\tr7, fp\n+\tldr.w\tfp, [sp, #356]\t@ 0x164\n \tadds\tr3, #1\n+\tstr\tr3, [sp, #284]\t@ 0x11c\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tldr\tr6, [sp, #280]\t@ 0x118\n+\tmov\tr4, r3\n \tstr\tr3, [sp, #192]\t@ 0xc0\n-\tcmp\tr2, r3\n-\tblt.w\t1fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa>\n-\tldr.w\tfp, [sp, #156]\t@ 0x9c\n-\tmov\tr9, sl\n-\tmov\tr4, r8\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tmov\tr5, r3\n \tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tsdiv\tip, r3, r2\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tmul.w\tsl, r5, r2\n-\tmovs.w\tr7, ip, lsl #2\n-\tsub.w\tr1, sl, r3\n-\tsub.w\tlr, sl, r2\n-\tsub.w\tr3, ip, r3\n-\tstr\tr1, [sp, #104]\t@ 0x68\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tbmi.w\t26f0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26f0>\n-\tudiv\tr0, lr, r7\n-\tcmp.w\tlr, #0\n-\tblt.w\te50 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe50>\n-\tmov.w\tr3, sl, lsl #2\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n-\tnegs\tr1, r3\n-\tldr.w\tr8, [sp, #164]\t@ 0xa4\n-\tadds\tr2, #1\n-\tstr\tr3, [sp, #132]\t@ 0x84\n-\tmovs\tr3, #0\n-\tstr.w\tsl, [sp, #144]\t@ 0x90\n-\tmov\tsl, r9\n-\tmov\tr9, fp\n-\tmov\tfp, r4\n-\tstr\tr2, [sp, #100]\t@ 0x64\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tcmp\tr2, #0\n-\tblt.w\t2686 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2686>\n-\tudiv\tr2, r6, r2\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp\tr4, r3\n-\tblt.w\te38 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe38>\n-\tldr\tr4, [sp, #120]\t@ 0x78\n+\tmov\tr0, r6\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tmov\tr2, r0\n+\tstr\tr0, [sp, #176]\t@ 0xb0\n+\tsubs\tr0, r0, r6\n+\tstr\tr0, [sp, #276]\t@ 0x114\n+\tlsls\tr2, r2, #2\n+\tstr\tr2, [sp, #380]\t@ 0x17c\n+\tmul.w\tr5, r4, r3\n+\tsub.w\tr3, r5, r3\n+\tsub.w\tr1, r5, r6\n+\tmov\tr4, r3\n+\tstr\tr1, [sp, #292]\t@ 0x124\n+\tstr\tr3, [sp, #396]\t@ 0x18c\n+\tbmi.w\t2ae2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ae2>\n+\tmov\tr1, r2\n+\tmov\tr0, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n \tcmp\tr4, #0\n-\tble.w\te38 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe38>\n-\tldr\tr4, [sp, #28]\n-\tstr\tr3, [sp, #212]\t@ 0xd4\n-\tadd\tr4, r3\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tmov\tr3, fp\n-\tmov\tfp, sl\n-\tmov\tsl, r9\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #128]\t@ 0x80\n-\tldr\tr4, [sp, #4]\n-\tmov\tr9, r3\n-\tstr.w\tip, [sp, #172]\t@ 0xac\n-\tstrd\tr7, r0, [sp, #184]\t@ 0xb8\n-\tstrd\tlr, r1, [sp, #216]\t@ 0xd8\n+\tmov\tr6, r0\n+\tblt.w\t9a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9a4>\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tmov.w\tr8, r5, lsl #2\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\trsb\tr3, r8, #0\n+\tstr\tr3, [sp, #188]\t@ 0xbc\n+\tmovs\tr4, #0\n+\tldr\tr3, [sp, #372]\t@ 0x174\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tmov\tr3, sl\n+\tmov\tsl, fp\n+\tmov\tfp, r3\n+\tcmp.w\tr8, #0\n+\tblt.w\t2a68 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a68>\n+\tldr\tr0, [sp, #168]\t@ 0xa8\n+\tmov\tr1, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tblt.w\t986 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x986>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tcmp\tr3, #0\n+\tble.w\t986 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x986>\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tadds\tr1, r3, r4\n \tmov\tlr, fp\n \tmovs\tr3, #1\n-\tstr\tr4, [sp, #108]\t@ 0x6c\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\tstrd\tr2, r5, [sp, #224]\t@ 0xe0\n-\tstr\tr4, [sp, #232]\t@ 0xe8\n-\tstrd\tr8, r6, [sp, #240]\t@ 0xf0\n-\tstr.w\tsl, [sp, #68]\t@ 0x44\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n+\tstr\tr5, [sp, #196]\t@ 0xc4\n+\tstr\tr6, [sp, #216]\t@ 0xd8\n+\tstr.w\tr8, [sp, #200]\t@ 0xc8\n+\tstr\tr4, [sp, #208]\t@ 0xd0\n+\tstrd\tr2, r7, [sp, #220]\t@ 0xdc\n+\tstr\tr1, [sp, #232]\t@ 0xe8\n+\tstr.w\tsl, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #276]\t@ 0x114\n \tadds\tr1, r3, r2\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r1\n-\tble.n\t8f0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x8f0>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tadds\tr0, r3, r1\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r0\n-\tble.n\t8fe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x8fe>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tadd\tr3, r0\n \tstr\tr3, [sp, #8]\n \tcmp\tr2, r3\n-\tble.n\t910 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x910>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #8]\n-\tldrd\tr2, r3, [sp, #104]\t@ 0x68\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #292]\t@ 0x124\n+\tit\tgt\n+\tstrgt\tr3, [sp, #8]\n+\tldr\tr3, [sp, #148]\t@ 0x94\n \tadd.w\tip, r3, r2\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr3, ip\n-\tble.n\t922 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x922>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tip, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tadd.w\tfp, r3, ip\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, fp\n-\tble.n\t932 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x932>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tfp, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tadd.w\tsl, r3, fp\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, sl\n-\tble.n\t942 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x942>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tsl, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tsl, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n \tadd\tr3, sl\n-\tstr\tr3, [sp, #12]\n+\tstr\tr3, [sp, #20]\n \tcmp\tr2, r3\n-\tble.n\t954 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x954>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr2, [sp, #28]\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #20]\n+\tldr\tr3, [sp, #292]\t@ 0x124\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tadd\tr3, ip\n \tcmp\tr2, r3\n-\tble.n\t962 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x962>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n \tadd.w\tr8, r2, r3\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r8\n-\tble.n\t972 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x972>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr8, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tit\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\tldr\tr5, [sp, #140]\t@ 0x8c\n+\tit\tgt\n+\taddgt\tr8, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n \tadd.w\tr7, r2, r8\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r7\n-\tble.n\t982 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x982>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr7, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tldr\tr5, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr7, r7, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n \tadd\tr2, r7\n-\tstr\tr2, [sp, #16]\n+\tstr\tr2, [sp, #24]\n \tcmp\tr5, r2\n-\tble.n\t994 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x994>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r4\n-\tstr\tr2, [sp, #16]\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tldr\tr5, [sp, #28]\n+\tldr\tr5, [sp, #140]\t@ 0x8c\n+\tittt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r4\n+\tstrgt\tr2, [sp, #24]\n+\tldr\tr2, [sp, #292]\t@ 0x124\n \tadd\tr2, r3\n \tcmp\tr5, r2\n-\tble.n\t9a2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9a2>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r4\n-\tldr\tr5, [sp, #88]\t@ 0x58\n+\tldr\tr5, [sp, #276]\t@ 0x114\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r4\n \tadds\tr6, r5, r2\n-\tldr\tr5, [sp, #28]\n-\tstr\tr6, [sp, #4]\n+\tldr\tr5, [sp, #140]\t@ 0x8c\n+\tstr\tr6, [sp, #0]\n \tcmp\tr5, r6\n-\tble.n\t9b4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9b4>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r4\n-\tstr\tr6, [sp, #4]\n-\tldr\tr5, [sp, #88]\t@ 0x58\n-\tldr\tr4, [sp, #4]\n+\tldr\tr5, [sp, #276]\t@ 0x114\n+\tittt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r4\n+\tstrgt\tr6, [sp, #0]\n+\tldr\tr4, [sp, #0]\n \tadds\tr6, r5, r4\n-\tldr\tr5, [sp, #28]\n+\tldr\tr5, [sp, #140]\t@ 0x8c\n \tcmp\tr5, r6\n-\tble.n\t9c4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9c4>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r4\n-\tldr\tr5, [sp, #88]\t@ 0x58\n-\tldr\tr4, [sp, #28]\n+\tldr\tr5, [sp, #276]\t@ 0x114\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r4\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n \tadd\tr5, r6\n-\tstr\tr5, [sp, #20]\n+\tstr\tr5, [sp, #28]\n \tcmp\tr4, r5\n-\tble.n\t9d6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9d6>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r4\n-\tstr\tr5, [sp, #20]\n-\tldr\tr4, [sp, #388]\t@ 0x184\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr5, r5, r4\n+\tldr\tr4, [sp, #596]\t@ 0x254\n+\tit\tgt\n+\tstrgt\tr5, [sp, #28]\n \tcmp\tr4, #0\n-\tble.w\tde2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xde2>\n+\tble.w\t944 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x944>\n \tadd.w\tr5, sl, #536870912\t@ 0x20000000\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n \tsubs\tr2, #1\n \tsubs\tr5, #1\n-\tstr\tr2, [sp, #24]\n+\tstr\tr2, [sp, #128]\t@ 0x80\n \tadd.w\tr2, fp, #536870912\t@ 0x20000000\n \tstr\tr5, [sp, #32]\n \tsubs\tr2, #1\n-\tldr\tr5, [sp, #12]\n+\tldr\tr5, [sp, #20]\n \tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tstr\tr2, [sp, #36]\t@ 0x24\n+\tstr\tr2, [sp, #40]\t@ 0x28\n \tadd.w\tr2, r8, #536870912\t@ 0x20000000\n \tldr\tr4, [sp, #8]\n \tadd.w\tfp, r5, #536870912\t@ 0x20000000\n \tsubs\tr2, #1\n-\tldr\tr5, [sp, #16]\n-\tstr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr5, [sp, #24]\n+\tstr\tr2, [sp, #72]\t@ 0x48\n \tadd.w\tr4, r4, #536870912\t@ 0x20000000\n-\tldr\tr2, [sp, #4]\n+\tldr\tr2, [sp, #0]\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n \tsubs\tr4, #1\n \tsubs\tr3, #1\n \tadd.w\tr8, r5, #536870912\t@ 0x20000000\n \tsubs\tr0, #1\n \tadd.w\tr5, r2, #536870912\t@ 0x20000000\n-\tldr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #28]\n \tadd.w\tip, ip, #536870912\t@ 0x20000000\n \tadd.w\tr7, r7, #536870912\t@ 0x20000000\n \tadd.w\tsl, r2, #536870912\t@ 0x20000000\n \tlsls\tr2, r0, #3\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tstr\tr2, [sp, #56]\t@ 0x38\n \tlsls\tr2, r4, #3\n-\tstr\tr2, [sp, #40]\t@ 0x28\n+\tstr\tr2, [sp, #48]\t@ 0x30\n \tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tstr\tr2, [sp, #12]\n+\tstr\tr2, [sp, #20]\n \tadd.w\tr6, r6, #536870912\t@ 0x20000000\n \tmov.w\tr2, ip, lsl #3\n \tstr\tr2, [sp, #8]\n \tlsls\tr2, r3, #3\n \tldr\tr3, [sp, #32]\n-\tstr\tr2, [sp, #4]\n+\tstr\tr2, [sp, #0]\n \tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n \tsubs\tr7, #1\n \tsubs\tr6, #1\n \tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tstr\tr2, [sp, #20]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr2, [sp, #28]\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n \tsubs\tr1, #1\n \tsubs\tr5, #1\n \tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n \tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n \tlsls\tr1, r1, #3\n \tlsls\tr5, r5, #3\n \tlsls\tr3, r3, #3\n \tstr\tr3, [sp, #32]\n \tlsls\tr3, r7, #3\n-\tstr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #72]\t@ 0x48\n \tmov.w\tr3, r8, lsl #3\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tlsls\tr3, r6, #3\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #148]\t@ 0x94\n \tmov.w\tfp, fp, lsl #3\n-\tldr\tr4, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #104]\t@ 0x68\n \tmov.w\tsl, sl, lsl #3\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tstrd\tsl, fp, [sp, #60]\t@ 0x3c\n+\tstr.w\tfp, [sp, #96]\t@ 0x60\n \tsubs\tr3, #1\n \tmov\tfp, r5\n-\tstr\tr2, [sp, #48]\t@ 0x30\n+\tstr\tr2, [sp, #64]\t@ 0x40\n \tmov.w\tr8, r3, lsl #3\n-\tstr.w\tr8, [sp, #56]\t@ 0x38\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n \tmov\tr8, r1\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #16]\n-\tldr\tr2, [sp, #40]\t@ 0x28\n+\tstr.w\tsl, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #24]\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadd.w\tsl, lr, r8\n \tadd.w\tr0, r9, r8\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #24]\n \tadd.w\tr1, lr, r2\n \tadd.w\tr5, r9, r2\n-\tvldr\td20, [sl]\n+\tvldr\td4, [sl]\n \tadd\tr2, r4\n-\tstr\tr5, [sp, #76]\t@ 0x4c\n+\tstr\tr5, [sp, #120]\t@ 0x78\n \tadds\tr3, #1\n-\tvldr\td17, [r1]\n+\tvldr\td7, [r1]\n \tadd\tr8, r4\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tvsub.f64\td26, d20, d17\n-\tvadd.f64\td20, d20, d17\n-\tvldr\td17, [r5]\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n-\tvldr\td19, [r0]\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tvsub.f64\td1, d4, d7\n+\tvadd.f64\td4, d4, d7\n+\tvldr\td7, [r5]\n+\tldr\tr5, [sp, #56]\t@ 0x38\n+\tvldr\td5, [r0]\n \tadd.w\tr6, lr, r5\n-\tstr\tr1, [sp, #68]\t@ 0x44\n+\tstr\tr1, [sp, #104]\t@ 0x68\n \tadd.w\tr1, lr, r2\n-\tstr\tr3, [sp, #16]\n-\tvsub.f64\td21, d19, d17\n-\tvadd.f64\td19, d19, d17\n-\tvldr\td23, [r6]\n+\tstr\tr3, [sp, #24]\n+\tvsub.f64\td0, d5, d7\n+\tvadd.f64\td5, d5, d7\n+\tvldr\td3, [r6]\n \tadd.w\tr3, r9, r2\n-\tvldr\td17, [r1]\n+\tvldr\td7, [r1]\n \tadd\tr2, r4\n-\tstr\tr6, [sp, #96]\t@ 0x60\n+\tstr\tr6, [sp, #144]\t@ 0x90\n \tadd.w\tr6, r9, r5\n-\tvldr\td25, [r3]\n-\tvsub.f64\td22, d17, d23\n-\tvadd.f64\td17, d17, d23\n-\tstr\tr2, [sp, #56]\t@ 0x38\n+\tvmul.f64\td0, d0, d12\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tvadd.f64\td6, d7, d3\n+\tvsub.f64\td7, d7, d3\n \tadds\tr2, r5, r4\n-\tstr\tr6, [sp, #72]\t@ 0x48\n+\tstr\tr6, [sp, #112]\t@ 0x70\n \tldr\tr5, [sp, #8]\n-\tvadd.f64\td28, d17, d20\n-\tvsub.f64\td17, d17, d20\n-\tvldr\td20, [r6]\n-\tvmov.f64\td27, d22\n-\tvfma.f64\td27, d21, d18\n-\tldr\tr6, [sp, #12]\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tvfma.f64\td22, d16, d21\n-\tvsub.f64\td24, d25, d20\n-\tvadd.f64\td25, d25, d20\n+\tvmul.f64\td1, d1, d12\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tvadd.f64\td2, d6, d4\n+\tvsub.f64\td3, d7, d0\n+\tvsub.f64\td6, d6, d4\n+\tvadd.f64\td13, d7, d0\n+\tvldr\td4, [r6]\n+\tvldr\td7, [r3]\n+\tldr\tr6, [sp, #20]\n+\tvadd.f64\td11, d7, d4\n+\tvsub.f64\td7, d7, d4\n \tadd.w\tr2, lr, r6\n-\tvadd.f64\td20, d25, d19\n-\tvmov.f64\td23, d24\n-\tvfma.f64\td23, d26, d18\n-\tvldr\td21, [r2]\n-\tvsub.f64\td25, d25, d19\n-\tvfma.f64\td24, d16, d26\n-\tvstr\td20, [r3]\n+\tvadd.f64\td4, d11, d5\n+\tvldr\td8, [r2]\n+\tvsub.f64\td11, d11, d5\n+\tvadd.f64\td10, d1, d7\n+\tvstr\td4, [r3]\n \tadd.w\tr3, lr, r5\n-\tvldr\td20, [r3]\n-\tvstr\td28, [r1]\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tvstr\td17, [r2]\n-\tldr\tr2, [sp, #4]\n+\tvsub.f64\td4, d7, d1\n+\tvldr\td5, [r3]\n+\tvstr\td2, [r1]\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tvstr\td6, [r2]\n+\tldr\tr2, [sp, #0]\n \tadd.w\tr6, lr, r1\n-\tvstr\td27, [r3]\n+\tvstr\td3, [r3]\n \tadds\tr7, r1, r4\n \tadd.w\tr3, r9, r2\n \tadd.w\tr2, r9, r1\n-\tvldr\td19, [r3]\n-\tvstr\td23, [r3]\n-\tvldr\td17, [r6]\n-\tldr\tr5, [sp, #64]\t@ 0x40\n-\tstr\tr7, [sp, #48]\t@ 0x30\n+\tvldr\td0, [r3]\n+\tvstr\td4, [r3]\n+\tvldr\td4, [r6]\n+\tldr\tr5, [sp, #96]\t@ 0x60\n+\tvldr\td6, [r2]\n \tadd.w\tr3, lr, r5\n \tadd.w\tr1, r9, r5\n-\tstr\tr1, [sp, #84]\t@ 0x54\n-\tadds\tr7, r5, r4\n-\tvldr\td27, [r2]\n-\tvldr\td23, [r3]\n+\tstr\tr1, [sp, #136]\t@ 0x88\n \tstr\tr7, [sp, #64]\t@ 0x40\n+\tadds\tr7, r5, r4\n+\tvldr\td7, [r3]\n+\tstr\tr7, [sp, #96]\t@ 0x60\n \tldr\tr7, [sp, #8]\n-\tvsub.f64\td28, d17, d23\n-\tvadd.f64\td17, d17, d23\n-\tvldr\td23, [r1]\n+\tvsub.f64\td3, d4, d7\n+\tvadd.f64\td4, d4, d7\n+\tvldr\td7, [r1]\n \tadd.w\tip, r9, r7\n-\tldr\tr1, [sp, #20]\n+\tldr\tr1, [sp, #28]\n \tadd\tr7, r4\n \tstr\tr7, [sp, #8]\n \tadd.w\tr5, lr, r1\n-\tvsub.f64\td26, d27, d23\n-\tldr\tr1, [sp, #20]\n-\tvadd.f64\td27, d27, d23\n-\tvldr\td29, [r5]\n+\tvsub.f64\td1, d6, d7\n+\tldr\tr1, [sp, #28]\n+\tvadd.f64\td6, d6, d7\n+\tvmul.f64\td3, d3, d12\n+\tvldr\td7, [r5]\n \tadd.w\tr7, r9, r1\n+\tvmul.f64\td1, d1, d12\n \tadd\tr1, r4\n-\tstr\tr1, [sp, #20]\n+\tstr\tr1, [sp, #28]\n+\tvadd.f64\td2, d5, d7\n+\tvsub.f64\td5, d5, d7\n+\tvldr\td9, [r7]\n+\tvldr\td7, [ip]\n \tldr\tr1, [sp, #32]\n-\tvsub.f64\td23, d20, d29\n-\tvadd.f64\td20, d20, d29\n-\tstr\tr7, [sp, #80]\t@ 0x50\n-\tvmov.f64\td29, d23\n-\tvadd.f64\td30, d20, d17\n-\tvfma.f64\td29, d26, d18\n-\tvfma.f64\td23, d16, d26\n-\tvsub.f64\td26, d20, d17\n-\tvldr\td17, [ip]\n-\tvldr\td20, [r7]\n-\tadds\tr7, r1, r4\n-\tvstr\td24, [ip]\n+\tvstr\td10, [ip]\n+\tvadd.f64\td14, d5, d1\n+\tvadd.f64\td10, d2, d4\n+\tvsub.f64\td2, d2, d4\n+\tvsub.f64\td4, d5, d1\n+\tvadd.f64\td5, d7, d9\n \tadd.w\tip, lr, r1\n+\tvsub.f64\td7, d7, d9\n+\tstr\tr7, [sp, #132]\t@ 0x84\n+\tadds\tr7, r1, r4\n \tstr\tr7, [sp, #32]\n-\tvsub.f64\td24, d17, d20\n-\tvadd.f64\td17, d17, d20\n-\tvldr\td20, [ip]\n-\tvstr\td30, [sl]\n-\tvstr\td26, [ip]\n-\tvmov.f64\td31, d24\n-\tvfma.f64\td24, d28, d18\n-\tvfma.f64\td31, d16, d28\n-\tvadd.f64\td28, d17, d27\n-\tvsub.f64\td17, d17, d27\n-\tvstr\td29, [r6]\n+\tvldr\td1, [ip]\n+\tvstr\td10, [sl]\n+\tvsub.f64\td10, d7, d3\n+\tvstr\td2, [ip]\n+\tvstr\td4, [r6]\n+\tvadd.f64\td4, d5, d6\n+\tvsub.f64\td5, d5, d6\n \tadd.w\tr6, r9, r1\n-\tldr\tr1, [sp, #52]\t@ 0x34\n+\tvadd.f64\td6, d3, d7\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tvldr\td7, [r6]\n \tadd.w\tsl, lr, r1\n-\tvldr\td29, [r6]\n-\tvstr\td28, [r0]\n-\tvstr\td17, [r6]\n-\tldr\tr6, [sp, #24]\n-\tvldr\td17, [sl]\n-\tvstr\td31, [r2]\n+\tvstr\td4, [r0]\n+\tvstr\td5, [r6]\n+\tldr\tr6, [sp, #128]\t@ 0x80\n+\tvstr\td6, [r2]\n \tadd.w\tr2, lr, r6\n+\tvldr\td6, [sl]\n \tadd.w\tr0, r9, r6\n \tadds\tr7, r6, r4\n-\tvsub.f64\td26, d21, d17\n-\tvadd.f64\td21, d21, d17\n-\tvldr\td17, [r2]\n-\tstr\tr7, [sp, #24]\n+\tvldr\td5, [r2]\n+\tvadd.f64\td3, d8, d6\n+\tstr\tr7, [sp, #128]\t@ 0x80\n+\tvsub.f64\td6, d8, d6\n+\tldr\tr6, [sp, #20]\n \tadds\tr7, r1, r4\n-\tldr\tr6, [sp, #12]\n-\tvsub.f64\td27, d20, d17\n-\tvadd.f64\td17, d20, d17\n-\tvldr\td20, [r0]\n+\tvsub.f64\td4, d1, d5\n+\tvadd.f64\td5, d1, d5\n \tadd.w\tip, r9, r6\n \tadd\tr6, r4\n-\tstr\tr6, [sp, #12]\n+\tstr\tr6, [sp, #20]\n \tadd.w\tr6, r9, r1\n-\tvmov.f64\td30, d26\n-\tvadd.f64\td28, d21, d17\n-\tvsub.f64\td21, d21, d17\n-\tvsub.f64\td17, d29, d20\n-\tvadd.f64\td20, d29, d20\n-\tvldr\td29, [r6]\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tstr\tr7, [sp, #52]\t@ 0x34\n-\tvfma.f64\td26, d16, d17\n-\tvfma.f64\td30, d17, d18\n-\tvldr\td17, [ip]\n-\tvstr\td25, [ip]\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tvadd.f64\td8, d3, d5\n+\tvsub.f64\td3, d3, d5\n+\tvldr\td5, [r0]\n+\tvmul.f64\td4, d4, d12\n+\tstr\tr7, [sp, #72]\t@ 0x48\n+\tldr\tr7, [sp, #144]\t@ 0x90\n+\tvsub.f64\td2, d7, d5\n+\tvadd.f64\td5, d7, d5\n+\tvldr\td7, [ip]\n+\tvmul.f64\td2, d2, d12\n+\tvsub.f64\td1, d6, d2\n+\tvadd.f64\td6, d6, d2\n+\tvldr\td2, [r6]\n+\tvstr\td11, [ip]\n \tadd.w\tip, lr, r1\n-\tldr\tr7, [sp, #96]\t@ 0x60\n-\tvsub.f64\td25, d17, d29\n-\tvadd.f64\td17, d17, d29\n-\tvmov.f64\td29, d25\n-\tvfma.f64\td25, d27, d18\n-\tvfma.f64\td29, d16, d27\n-\tvadd.f64\td27, d17, d20\n-\tvsub.f64\td20, d17, d20\n-\tvldr\td17, [ip]\n-\tvstr\td28, [r7]\n-\tvstr\td21, [sl]\n-\tvstr\td30, [r5]\n+\tvadd.f64\td9, d7, d2\n+\tvsub.f64\td7, d7, d2\n+\tvldr\td2, [ip]\n+\tvstr\td8, [r7]\n+\tvstr\td3, [sl]\n+\tvstr\td1, [r5]\n \tadds\tr5, r1, r4\n-\tstr\tr5, [sp, #36]\t@ 0x24\n-\tldr\tr5, [sp, #72]\t@ 0x48\n-\tvstr\td26, [ip]\n+\tvstr\td6, [ip]\n+\tvadd.f64\td6, d9, d5\n+\tstr\tr5, [sp, #40]\t@ 0x28\n+\tvsub.f64\td9, d9, d5\n+\tldr\tr5, [sp, #112]\t@ 0x70\n \tadd.w\tip, r9, r1\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr7, [sp, #80]\t@ 0x50\n-\tvldr\td21, [ip]\n-\tvstr\td27, [r5]\n+\tldr\tr1, [sp, #88]\t@ 0x58\n+\tvadd.f64\td5, d4, d7\n+\tldr\tr7, [sp, #132]\t@ 0x84\n+\tvsub.f64\td7, d7, d4\n+\tvldr\td4, [ip]\n+\tvstr\td6, [r5]\n \tadd.w\tr5, lr, r1\n-\tvstr\td20, [r6]\n+\tvstr\td9, [r6]\n \tadd.w\tr6, lr, fp\n-\tvstr\td29, [r7]\n-\tvsub.f64\td20, d19, d21\n-\tvstr\td25, [ip]\n-\tvadd.f64\td19, d19, d21\n-\tvldr\td25, [r5]\n+\tvstr\td5, [r7]\n+\tvadd.f64\td3, d0, d4\n+\tvstr\td7, [ip]\n+\tvsub.f64\td7, d0, d4\n+\tvldr\td6, [r6]\n \tadd.w\tip, r9, fp\n-\tvldr\td21, [r6]\n+\tvldr\td4, [r5]\n \tadd.w\tr7, r9, r1\n-\tvmov.f64\td28, d20\n \tadd\tr1, r4\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n+\tstr\tr1, [sp, #88]\t@ 0x58\n+\tldr\tr1, [sp, #120]\t@ 0x78\n \tadd\tfp, r4\n-\tvsub.f64\td26, d21, d25\n-\tvadd.f64\td21, d21, d25\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tvfma.f64\td20, d26, d18\n-\tvfma.f64\td28, d16, d26\n-\tvldr\td26, [r7]\n-\tvmov.f64\td25, d20\n-\tvldr\td20, [ip]\n-\tvsub.f64\td27, d20, d26\n-\tvadd.f64\td20, d20, d26\n-\tvadd.f64\td26, d19, d20\n-\tvsub.f64\td19, d19, d20\n-\tvstr\td26, [r1]\n-\tvstr\td19, [r0]\n-\tvstr\td24, [ip]\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tldr\tr0, [sp, #4]\n-\tvstr\td28, [r1]\n+\tvsub.f64\td5, d6, d4\n+\tvldr\td0, [r7]\n+\tvadd.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d12\n+\tvadd.f64\td1, d5, d7\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td5, [ip]\n+\tvsub.f64\td4, d5, d0\n+\tvadd.f64\td5, d5, d0\n+\tvadd.f64\td0, d3, d5\n+\tvsub.f64\td3, d3, d5\n+\tvmul.f64\td4, d4, d12\n+\tvstr\td0, [r1]\n+\tvstr\td3, [r0]\n+\tvstr\td10, [ip]\n+\tldr\tr1, [sp, #136]\t@ 0x88\n+\tldr\tr0, [sp, #0]\n+\tvstr\td1, [r1]\n \tadd.w\tr1, lr, r0\n-\tvstr\td25, [r7]\n+\tvstr\td7, [r7]\n \tadd\tr0, r4\n-\tstr\tr0, [sp, #4]\n-\tvldr\td20, [r1]\n-\tvstr\td22, [r1]\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tvsub.f64\td19, d20, d17\n-\tvadd.f64\td17, d17, d20\n-\tvstr\td23, [r6]\n-\tvmov.f64\td20, d19\n-\tvfma.f64\td19, d16, d27\n-\tvfma.f64\td20, d27, d18\n-\tvadd.f64\td22, d17, d21\n-\tvsub.f64\td17, d17, d21\n-\tvstr\td22, [r1]\n-\tvstr\td17, [r2]\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tvstr\td20, [r3]\n-\tldr\tr3, [sp, #16]\n-\tvstr\td19, [r5]\n+\tstr\tr0, [sp, #0]\n+\tvldr\td7, [r1]\n+\tvstr\td13, [r1]\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tvadd.f64\td5, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvstr\td14, [r6]\n+\tvadd.f64\td3, d5, d6\n+\tvsub.f64\td5, d5, d6\n+\tvsub.f64\td6, d7, d4\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td3, [r1]\n+\tvstr\td5, [r2]\n+\tvstr\td6, [r3]\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tldr\tr3, [sp, #24]\n+\tvstr\td7, [r5]\n \tcmp\tr3, r2\n-\tbne.w\tab4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xab4>\n-\tstr\tr4, [sp, #68]\t@ 0x44\n-\tldrd\tr3, r2, [sp, #108]\t@ 0x6c\n+\tbne.w\t61a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x61a>\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #148]\t@ 0x94\n \tcmp\tr2, r3\n-\tble.n\tdf6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xdf6>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tble.n\t958 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x958>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr3, [sp, #116]\t@ 0x74\n-\tldr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n \tcmp\tr3, r2\n-\tbne.w\t8e0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x8e0>\n-\tldrd\tr1, r2, [sp, #220]\t@ 0xdc\n+\tbne.w\t43c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x43c>\n+\tldrd\tr2, r7, [sp, #220]\t@ 0xdc\n \tmov\tfp, lr\n-\tldr\tr4, [sp, #232]\t@ 0xe8\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tldr.w\tr8, [sp, #200]\t@ 0xc8\n+\tldr\tr1, [sp, #232]\t@ 0xe8\n \tsubs\tr2, #1\n-\tldr\tr5, [sp, #228]\t@ 0xe4\n+\tldr\tr5, [sp, #196]\t@ 0xc4\n \tadds\tr0, r2, #1\n-\tldrd\tr8, r6, [sp, #240]\t@ 0xf0\n+\tldr\tr6, [sp, #216]\t@ 0xd8\n+\tadd\tr1, r8\n+\tldr.w\tsl, [sp, #104]\t@ 0x68\n+\tldr\tr4, [sp, #208]\t@ 0xd0\n+\tbne.w\t420 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x420>\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tsubs\tr6, #1\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n \tadd\tr4, r3\n-\tldr.w\tsl, [sp, #68]\t@ 0x44\n-\tldr.w\tlr, [sp, #216]\t@ 0xd8\n-\tbne.w\t8c6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x8c6>\n-\tmov\tr2, r9\n-\tldr.w\tip, [sp, #172]\t@ 0xac\n-\tldrd\tr7, r0, [sp, #184]\t@ 0xb8\n-\tmov\tr9, sl\n-\tldr\tr3, [sp, #212]\t@ 0xd4\n-\tmov\tsl, fp\n-\tmov\tfp, r2\n-\tsubs\tr0, #1\n-\tadd\tr3, r7\n-\tadd\tr8, r7\n-\tsubs\tr6, r6, r7\n-\tadds\tr4, r0, #1\n-\tbne.w\t88a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x88a>\n-\tmov\tr4, fp\n-\tmov\tfp, r9\n+\tadd\tr2, r3\n+\tstr\tr2, [sp, #160]\t@ 0xa0\n+\tldr\tr2, [sp, #168]\t@ 0xa8\n+\tsubs\tr3, r2, r3\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tadds\tr3, r6, #1\n+\tbne.w\t3fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3fa>\n+\tmov\tr3, fp\n+\tmov\tfp, sl\n+\tmov\tsl, r3\n+\tldr\tr3, [sp, #368]\t@ 0x170\n+\tcmp\tr3, r7\n+\tbeq.w\t1f12 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f12>\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tldr\tr2, [sp, #176]\t@ 0xb0\n+\tlsls\tr6, r3, #1\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tsubs\tr4, r2, r3\n+\tcmp\tr3, #0\n+\tblt.w\t2ace <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ace>\n+\tmov\tr8, r3\n+\tmov\tr1, r3\n+\tsubs\tr0, r4, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr8, r4\n+\tstr\tr0, [sp, #420]\t@ 0x1a4\n+\tbgt.w\t2ac0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac0>\n+\tmovs\tr3, #24\n+\tldr\tr2, [sp, #376]\t@ 0x178\n+\tlsls\tr1, r5, #2\n+\tmov.w\tr8, r6, lsl #3\n+\tadd.w\tr0, r2, r8\n+\tstr\tr7, [sp, #460]\t@ 0x1cc\n+\tmul.w\tr5, r3, r6\n+\tlsls\tr3, r6, #4\n+\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tadd.w\tr4, r0, r8\n+\tadd.w\tr3, r5, #8\n+\tstr\tr4, [sp, #440]\t@ 0x1b8\n+\tadd\tr3, r2\n+\tstr\tr4, [sp, #408]\t@ 0x198\n+\tnegs\tr2, r1\n+\tldr\tr4, [sp, #396]\t@ 0x18c\n+\tstr\tr2, [sp, #452]\t@ 0x1c4\n+\tmov\tr7, r5\n+\tldr\tr2, [sp, #332]\t@ 0x14c\n+\tmov\tr5, r1\n+\tstr\tr2, [sp, #384]\t@ 0x180\n+\tsubs\tr4, r4, r2\n+\tstr\tr4, [sp, #392]\t@ 0x188\n+\tldr\tr4, [sp, #316]\t@ 0x13c\n+\tsubs\tr4, r2, r4\n+\tmov\tr2, r3\n+\tstr\tr4, [sp, #388]\t@ 0x184\n+\tmov\tr3, r9\n+\tldr\tr4, [sp, #320]\t@ 0x140\n \tmov\tr9, sl\n-\tldr.w\tsl, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tldr\tr2, [sp, #192]\t@ 0xc0\n-\tcmp\tr3, r2\n-\tbeq.w\t26d8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26d8>\n-\tlsls\tr2, r5, #1\n-\tldr\tr5, [sp, #136]\t@ 0x88\n-\tsub.w\tr3, ip, r5\n+\tmov\tsl, r3\n+\tadds\tr4, #1\n+\tstr\tr4, [sp, #312]\t@ 0x138\n+\tldr\tr3, [sp, #408]\t@ 0x198\n+\tvldr\td5, [r2, #-8]\n+\tvldr\td6, [r2]\n+\tvldr\td14, [r0, #8]\n+\tvldr\td7, [r3, #8]\n+\tvstr\td5, [sp, #304]\t@ 0x130\n+\tvldr\td5, [sp, #360]\t@ 0x168\n+\tvldr\td13, [r3]\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tvmul.f64\td7, d5, d7\n+\tvmul.f64\td14, d5, d14\n+\tvldr\td15, [r0]\n+\tcmp\tr3, #0\n+\tvmov.f64\td8, d7\n+\tvmul.f64\td7, d5, d6\n+\tvstr\td7, [sp]\n+\tblt.w\t2a96 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a96>\n+\tmov\tr1, r3\n+\tldr\tr0, [sp, #392]\t@ 0x188\n+\tstr\tr2, [sp, #8]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #384]\t@ 0x180\n+\tmov\tr3, r0\n+\tldr\tr1, [sp, #396]\t@ 0x18c\n+\tcmp\tr1, r2\n+\tldr\tr2, [sp, #8]\n+\tblt.w\t1228 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1228>\n+\tldr\tr0, [sp, #316]\t@ 0x13c\n+\tsubs\tr4, r0, r1\n+\tldr\tr1, [sp, #392]\t@ 0x188\n+\tvmov.f64\td11, d8\n+\tstrd\tr7, r2, [sp, #464]\t@ 0x1d0\n+\tmov\tr7, r9\n+\tadds\tr1, r4, r1\n+\tldr\tr4, [sp, #384]\t@ 0x180\n+\tstr\tr1, [sp, #412]\t@ 0x19c\n+\tmov\tr2, r4\n+\tldr\tr1, [sp, #388]\t@ 0x184\n+\tstr\tr1, [sp, #416]\t@ 0x1a0\n+\tstr\tr3, [sp, #444]\t@ 0x1bc\n+\tstr.w\tr8, [sp, #472]\t@ 0x1d8\n \tcmp\tr5, #0\n-\tblt.w\t26e0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26e0>\n-\tsubs\tr1, r3, r5\n-\tcmp\tr5, r3\n-\tudiv\tr8, r1, r5\n-\tbgt.w\t26ca <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26ca>\n-\tmovs\tr3, #24\n-\tldr\tr0, [sp, #168]\t@ 0xa8\n-\tmov.w\tr6, sl, lsl #2\n-\tstr.w\tr8, [sp, #216]\t@ 0xd8\n+\tstr\tr2, [sp, #8]\n+\tblt.w\t2a7e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a7e>\n+\tmov\tr1, r5\n+\tldr\tr0, [sp, #412]\t@ 0x19c\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #8]\n+\tmov\tr1, r0\n+\tcmp\tr3, r2\n+\tblt.w\t1202 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1202>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tcmp\tr3, #0\n+\tble.w\t1202 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1202>\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tmov\tr9, r7\n+\tstr\tr2, [sp, #476]\t@ 0x1dc\n+\tadds\tr0, r2, r3\n+\tmov\tr3, sl\n+\tmov\tlr, r0\n \tmov\tsl, fp\n-\tmov\tfp, r9\n-\tmul.w\tr1, r3, r2\n-\tlsls\tr3, r2, #3\n-\tlsls\tr2, r2, #4\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n-\tstr\tr2, [sp, #224]\t@ 0xe0\n-\tmov\tr2, r3\n-\tadds\tr3, r0, r3\n-\tmov\tr9, r4\n-\tadds\tr5, r3, r2\n-\tadd.w\tr2, r1, #8\n-\tadds\tr2, r0, r2\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tstr\tr2, [sp, #184]\t@ 0xb8\n-\tnegs\tr2, r6\n-\tstr\tr2, [sp, #232]\t@ 0xe8\n-\tmov\tr8, r5\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tstr\tr2, [sp, #172]\t@ 0xac\n-\tsub.w\tip, lr, r2\n-\tsubs\tr0, r2, r0\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tstr\tr1, [sp, #220]\t@ 0xdc\n-\tadds\tr2, #1\n-\tstr\tr5, [sp, #212]\t@ 0xd4\n-\tstr\tr2, [sp, #96]\t@ 0x60\n-\tvldr\td20, [r3, #8]\n-\tcmp\tr7, #0\n-\tvldr\td23, [r3]\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tvldr\td21, [r8, #8]\n-\tvmul.f64\td20, d8, d20\n-\tvldr\td24, [r8]\n-\tvldr\td22, [r3]\n-\tvmul.f64\td21, d8, d21\n-\tvldr\td25, [r3, #-8]\n-\tvmul.f64\td22, d8, d22\n-\tblt.w\t26aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26aa>\n-\tudiv\tr4, ip, r7\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tcmp\tlr, r3\n-\tblt.w\t1592 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1592>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tsub.w\tr3, r3, lr\n-\tadd.w\tr5, r3, ip\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tstr\tr0, [sp, #188]\t@ 0xbc\n-\tstr.w\tr8, [sp, #240]\t@ 0xf0\n-\tcmp\tr6, #0\n-\tblt.w\t2696 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2696>\n-\tudiv\tr2, r5, r6\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tcmp\tr1, r3\n-\tblt.w\t157c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x157c>\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tcmp\tr1, #0\n-\tble.w\t157c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x157c>\n-\tldr\tr1, [sp, #28]\n-\tstrd\tr4, r0, [sp, #244]\t@ 0xf4\n-\tadd.w\tr8, r3, r1\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tstrd\tip, r5, [sp, #252]\t@ 0xfc\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #116]\t@ 0x74\n-\tmov\tr1, r8\n-\tstrd\tlr, r7, [sp, #260]\t@ 0x104\n-\tstr\tr3, [sp, #268]\t@ 0x10c\n-\tstr\tr6, [sp, #144]\t@ 0x90\n+\tmov\tfp, r3\n+\tstr\tr5, [sp, #340]\t@ 0x154\n+\tstr.w\tlr, [sp, #288]\t@ 0x120\n \tmovs\tr3, #1\n-\tstr\tr1, [sp, #100]\t@ 0x64\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tstrd\tr2, r1, [sp, #128]\t@ 0x80\n-\tstr.w\tsl, [sp, #24]\n-\tstr.w\tfp, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tadds\tr5, r3, r2\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr3, r5\n-\tble.n\tf60 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf60>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadds\tr6, r3, r5\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr3, r6\n-\tble.n\tf6e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf6e>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #28]\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #4]\n+\tstrd\tr1, lr, [sp, #324]\t@ 0x144\n+\tmov\tlr, r9\n+\tstr\tr3, [sp, #296]\t@ 0x128\n+\tstr.w\tsl, [sp, #32]\n+\tldr\tr3, [sp, #276]\t@ 0x114\n+\tldr\tr2, [sp, #288]\t@ 0x120\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tadds\tr7, r3, r2\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, r7\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr7, r7, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n+\tadd.w\tip, r3, r7\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, ip\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #276]\t@ 0x114\n+\tadd\tr3, ip\n+\tstr\tr3, [sp, #20]\n \tcmp\tr2, r3\n-\tble.n\tf80 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf80>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #4]\n-\tldrd\tr2, r3, [sp, #100]\t@ 0x64\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #20]\n+\tldrd\tr2, r3, [sp, #288]\t@ 0x120\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r3\n-\tble.n\tf90 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf90>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd.w\tsl, r2, r3\n-\tldr\tr2, [sp, #28]\n-\tcmp\tr2, sl\n-\tble.n\tfa0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xfa0>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tsl, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd.w\tr0, r2, sl\n-\tldr\tr2, [sp, #28]\n-\tcmp\tr2, r0\n-\tble.n\tfb0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xfb0>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tldr\tr1, [sp, #28]\n-\tadd\tr2, r0\n-\tstr\tr2, [sp, #8]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n+\tadds\tr4, r2, r3\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr2, r4\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr4, r4, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n+\tadds\tr5, r2, r4\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr2, r5\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr5, r5, r2\n+\tldr\tr2, [sp, #276]\t@ 0x114\n+\tadd\tr2, r5\n+\tstr\tr2, [sp, #24]\n \tcmp\tr1, r2\n-\tble.n\tfc2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xfc2>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #8]\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tldr\tr1, [sp, #28]\n+\tittt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r1\n+\tstrgt\tr2, [sp, #24]\n+\tldr\tr2, [sp, #292]\t@ 0x124\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n \tadd\tr2, r3\n \tcmp\tr1, r2\n-\tble.n\tfd0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xfd0>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd.w\tfp, r1, r2\n-\tldr\tr1, [sp, #28]\n-\tcmp\tr1, fp\n-\tble.n\tfe0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xfe0>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tfp, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd.w\tr8, r1, fp\n-\tldr\tr1, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tadds\tr0, r1, r2\n+\tstr\tr0, [sp, #8]\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, r0\n+\tittt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r1\n+\tstrgt\tr0, [sp, #8]\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tldr\tr0, [sp, #8]\n+\tadd.w\tr8, r1, r0\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tldr\tr0, [sp, #140]\t@ 0x8c\n \tcmp\tr1, r8\n-\tble.n\tff0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xff0>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr8, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd.w\tr4, r1, r8\n-\tldr\tr1, [sp, #28]\n-\tstr\tr4, [sp, #12]\n-\tcmp\tr1, r4\n-\tble.n\t1004 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1004>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #12]\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tadds\tr4, r1, r2\n-\tldr\tr1, [sp, #28]\n-\tcmp\tr1, r4\n-\tble.n\t1012 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1012>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd.w\tip, r1, r4\n-\tldr\tr1, [sp, #28]\n-\tcmp\tr1, ip\n-\tble.n\t1022 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1022>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tip, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd.w\tlr, r1, ip\n-\tldr\tr1, [sp, #28]\n-\tcmp\tr1, lr\n-\tble.n\t1032 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1032>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tlr, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tldr\tr7, [sp, #28]\n-\tadd\tr1, lr\n-\tstr\tr1, [sp, #16]\n-\tcmp\tr7, r1\n-\tble.n\t1044 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1044>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r7\n-\tstr\tr1, [sp, #16]\n-\tldr\tr1, [sp, #388]\t@ 0x184\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr8, r1\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tadd.w\tr6, r1, r8\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tstr\tr6, [sp, #28]\n+\tcmp\tr1, r6\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r1\n+\tldr\tr1, [sp, #292]\t@ 0x124\n+\tit\tgt\n+\tstrgt\tr6, [sp, #28]\n+\tadds\tr6, r1, r2\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, r6\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r1\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tadd.w\tr9, r1, r6\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, r9\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr9, r1\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tadd.w\tsl, r1, r9\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, sl\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tsl, r1\n+\tldr\tr1, [sp, #276]\t@ 0x114\n+\tadd\tr1, sl\n+\tstr\tr1, [sp, #128]\t@ 0x80\n+\tcmp\tr0, r1\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r0\n+\tstrgt\tr1, [sp, #128]\t@ 0x80\n+\tldr\tr1, [sp, #596]\t@ 0x254\n \tcmp\tr1, #0\n-\tble.w\t1532 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1532>\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tldr\tr1, [sp, #4]\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #8]\n-\tadd.w\tr7, sl, #536870912\t@ 0x20000000\n+\tble.w\t11bc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x11bc>\n+\tldr\tr0, [sp, #24]\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tldr\tr1, [sp, #20]\n \tsubs\tr2, #1\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #8]\n-\tadd.w\tr3, r8, #536870912\t@ 0x20000000\n-\tlsls\tr2, r2, #3\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #12]\n-\tsubs\tr7, #1\n+\tstr\tr2, [sp, #20]\n+\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n+\tldr\tr2, [sp, #8]\n \tsubs\tr0, #1\n-\tadd.w\tlr, lr, #536870912\t@ 0x20000000\n-\tadd.w\tsl, r3, #536870912\t@ 0x20000000\n-\tldr\tr3, [sp, #16]\n-\tstr\tr2, [sp, #16]\n-\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n-\tadd.w\tr8, r3, #536870912\t@ 0x20000000\n-\tldr\tr3, [sp, #4]\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n-\tadd.w\tip, ip, #536870912\t@ 0x20000000\n-\tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #8]\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tlsls\tr2, r0, #3\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tlsls\tr2, r7, #3\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #20]\n+\tstr\tr0, [sp, #40]\t@ 0x28\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr0, r2, #536870912\t@ 0x20000000\n+\tadd.w\tr2, r8, #536870912\t@ 0x20000000\n+\tsubs\tr3, #1\n+\tsubs\tr2, #1\n \tsubs\tr1, #1\n-\tadd.w\tfp, fp, #536870912\t@ 0x20000000\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd.w\tr6, r6, #536870912\t@ 0x20000000\n+\tstr\tr2, [sp, #8]\n \tadd.w\tr5, r5, #536870912\t@ 0x20000000\n-\tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tmov.w\tr3, sl, lsl #3\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tmov.w\tr3, lr, lsl #3\n-\tstr\tr3, [sp, #32]\n-\tmov.w\tr3, r8, lsl #3\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [sp, #28]\n \tlsls\tr1, r1, #3\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tsubs\tr6, #1\n-\tsubs\tr3, #1\n+\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n+\tstr\tr1, [sp, #144]\t@ 0x90\n+\tadd.w\tr8, r2, #536870912\t@ 0x20000000\n+\tlsls\tr1, r3, #3\n+\tldr\tr2, [sp, #128]\t@ 0x80\n \tsubs\tr5, #1\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tsubs\tr4, #1\n-\tmov.w\tsl, ip, lsl #3\n-\tstr\tr1, [sp, #52]\t@ 0x34\n-\tmov.w\tfp, fp, lsl #3\n-\tldr\tr1, [sp, #24]\n-\tmov.w\tr8, r3, lsl #3\n-\tldr\tr7, [sp, #76]\t@ 0x4c\n+\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tstr\tr1, [sp, #148]\t@ 0x94\n+\tsubs\tr2, #1\n+\tlsls\tr1, r5, #3\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tadd.w\tsl, sl, #536870912\t@ 0x20000000\n+\tldr\tr2, [sp, #20]\n+\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tstr\tr1, [sp, #20]\n+\tlsls\tr1, r4, #3\n+\tstr\tr1, [sp, #24]\n+\tlsls\tr1, r3, #3\n+\tldr\tr3, [sp, #8]\n+\tadd.w\tr7, r7, #536870912\t@ 0x20000000\n+\tstr\tr1, [sp, #28]\n+\tmov.w\tr1, sl, lsl #3\n+\tadd.w\tr6, r6, #536870912\t@ 0x20000000\n+\tadd.w\tr9, r9, #536870912\t@ 0x20000000\n+\tlsls\tr4, r3, #3\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tsubs\tr0, #1\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tadd.w\tip, ip, #536870912\t@ 0x20000000\n+\tmov.w\tsl, r3, lsl #3\n+\tldr\tr3, [sp, #288]\t@ 0x120\n+\tsubs\tr7, #1\n+\tsubs\tr6, #1\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n+\tsubs\tr3, #1\n+\tlsls\tr5, r0, #3\n+\tlsls\tr7, r7, #3\n+\tmov.w\tr0, r8, lsl #3\n \tlsls\tr6, r6, #3\n-\tstr.w\tfp, [sp, #68]\t@ 0x44\n-\tmov\tfp, sl\n-\tlsls\tr5, r5, #3\n-\tlsls\tr4, r4, #3\n+\tmov.w\tr8, r9, lsl #3\n+\tlsls\tr2, r2, #3\n+\tmov.w\tr9, r3, lsl #3\n+\tmov.w\tip, ip, lsl #3\n \tmovs\tr3, #1\n-\tstr\tr6, [sp, #44]\t@ 0x2c\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tstr\tr2, [sp, #12]\n-\tstr\tr3, [sp, #4]\n-\tstr.w\tr8, [sp, #72]\t@ 0x48\n-\tstr\tr4, [sp, #20]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tadd.w\tip, r7, r2\n-\tadds\tr5, r2, r1\n-\tadds\tr0, r7, r4\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tadd.w\tr5, r9, r4\n-\tstr\tr0, [sp, #84]\t@ 0x54\n-\tvldr\td31, [ip]\n-\tadd\tr4, r1\n-\tvldr\td17, [r0]\n-\tadd.w\tr0, r9, r2\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tvsub.f64\td29, d31, d17\n-\tstr\tr5, [sp, #80]\t@ 0x50\n-\tvadd.f64\td31, d31, d17\n-\tvldr\td17, [r5]\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #184]\t@ 0xb8\n+\tstr\tr3, [sp, #8]\n+\tmov\tr3, sl\n+\tldr\tr1, [sp, #32]\n+\tmov\tsl, r8\n+\tstr.w\tr9, [sp, #128]\t@ 0x80\n+\tmov\tr8, r6\n+\tmov\tr9, r0\n+\tmov\tr6, r5\n+\tmov\tr0, lr\n+\tmov\tr5, r7\n+\tstr.w\tip, [sp, #32]\n+\tmov\tr7, r2\n+\tvldr\td10, [sp, #304]\t@ 0x130\n+\tmov\tlr, r4\n+\tmov\tip, fp\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #8]\n+\tadds\tr2, r0, r5\n+\tstr\tr2, [sp, #188]\t@ 0xbc\n \tadds\tr3, #1\n-\tvldr\td28, [r0]\n-\tadd.w\tsl, r9, r5\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr3, r9, r2\n-\tadd.w\tr8, r7, r5\n-\tvsub.f64\td6, d28, d17\n-\tvadd.f64\td28, d28, d17\n-\tvldr\td17, [sl]\n-\tvldr\td30, [r3]\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tadds\tr4, r7, r2\n-\tvldr\td7, [r8]\n-\tadd\tr2, r1\n-\tvsub.f64\td27, d30, d17\n-\tvadd.f64\td26, d30, d17\n-\tvsub.f64\td17, d17, d30\n-\tldr\tr6, [sp, #56]\t@ 0x38\n-\tvfma.f64\td17, d16, d29\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tadds\tr2, r5, r1\n-\tldr\tr5, [sp, #16]\n-\tvadd.f64\td30, d26, d28\n-\tvmov.f64\td19, d27\n-\tvfma.f64\td19, d16, d29\n-\tvfma.f64\td27, d29, d18\n-\tvsub.f64\td29, d28, d26\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tvsub.f64\td26, d26, d28\n-\tvldr\td28, [r4]\n-\tvstr\td30, [r3]\n-\tadds\tr2, r7, r6\n-\tadds\tr3, r7, r5\n-\tadd.w\tlr, r9, r6\n-\tvsub.f64\td30, d28, d7\n-\tvadd.f64\td28, d28, d7\n-\tvmul.f64\td29, d29, d21\n-\tvmul.f64\td2, d26, d24\n-\tvldr\td26, [r2]\n-\tvmul.f64\td1, d22, d17\n-\tvnmul.f64\td5, d19, d20\n-\tvmul.f64\td27, d25, d27\n-\tvmov.f64\td7, d30\n-\tvfma.f64\td30, d16, d6\n-\tvfma.f64\td7, d6, d18\n-\tvsub.f64\td6, d28, d31\n-\tvadd.f64\td28, d28, d31\n-\tvmul.f64\td19, d23, d19\n-\tvmov.f64\td31, d5\n-\tvldr\td5, [r3]\n-\tvfma.f64\td29, d24, d6\n-\tvfma.f64\td2, d21, d6\n-\tvstr\td28, [r4]\n-\tldr\tr4, [sp, #12]\n-\tvfma.f64\td27, d22, d30\n-\tvfma.f64\td1, d25, d30\n-\tvfma.f64\td31, d23, d7\n-\tvfma.f64\td19, d20, d7\n-\tvstr\td31, [r2]\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tvstr\td29, [r3]\n-\tadds\tr3, r7, r4\n-\tadds\tr5, r7, r2\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tvldr\td31, [r5]\n-\tvldr\td17, [r3]\n-\tldr\tr4, [sp, #20]\n-\tadd.w\tr3, r9, r4\n-\tvsub.f64\td28, d31, d17\n-\tvadd.f64\td31, d31, d17\n-\tvldr\td7, [r3]\n-\tvstr\td27, [r3]\n-\tadd.w\tr3, r9, r2\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #12]\n-\tvldr\td30, [r3]\n-\tadd.w\tr4, r9, r2\n-\tstr\tr4, [sp, #24]\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #12]\n-\tldr\tr2, [sp, #24]\n-\tldr\tr4, [sp, #60]\t@ 0x3c\n-\tvldr\td29, [lr]\n-\tvldr\td17, [r2]\n-\tadds\tr2, r6, r1\n-\tadd.w\tr6, r9, r4\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tadds\tr2, r4, r1\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tvsub.f64\td3, d30, d17\n-\tvadd.f64\td30, d30, d17\n-\tvldr\td17, [r6]\n-\tvstr\td19, [lr]\n-\tadd.w\tlr, r7, r4\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tvsub.f64\td19, d29, d17\n-\tvadd.f64\td6, d29, d17\n-\tvldr\td4, [lr]\n-\tvsub.f64\td17, d17, d29\n-\tvfma.f64\td17, d16, d28\n-\tadds\tr2, r4, r1\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tvmov.f64\td27, d19\n-\tvsub.f64\td29, d30, d6\n-\tvfma.f64\td27, d16, d28\n-\tvfma.f64\td19, d28, d18\n-\tvsub.f64\td28, d6, d30\n-\tvadd.f64\td6, d6, d30\n-\tvsub.f64\td30, d26, d4\n-\tvadd.f64\td26, d26, d4\n-\tvmul.f64\td29, d29, d21\n-\tvmul.f64\td28, d28, d24\n-\tvmul.f64\td0, d22, d17\n-\tvmov.f64\td4, d30\n-\tvfma.f64\td30, d16, d3\n-\tvfma.f64\td4, d3, d18\n-\tvsub.f64\td3, d26, d31\n-\tvstr\td6, [r0]\n-\tvnmul.f64\td6, d27, d20\n-\tvmul.f64\td27, d23, d27\n-\tvadd.f64\td26, d26, d31\n-\tadds\tr0, r7, r4\n-\tvmul.f64\td19, d25, d19\n-\tvfma.f64\td29, d24, d3\n-\tvfma.f64\td28, d21, d3\n-\tvldr\td17, [r0]\n-\tvstr\td26, [ip]\n-\tvfma.f64\td19, d22, d30\n-\tvfma.f64\td6, d23, d4\n-\tvfma.f64\td27, d20, d4\n-\tvfma.f64\td0, d25, d30\n-\tvstr\td6, [r5]\n-\tvstr\td29, [r0]\n-\tadd.w\tr0, r9, r4\n-\tldr\tr5, [sp, #36]\t@ 0x24\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tvldr\td30, [r0]\n-\tadds\tr2, r5, r1\n-\tadd.w\tip, r7, r4\n-\tvstr\td27, [r3]\n-\tvstr\td28, [r0]\n-\tadds\tr0, r7, r5\n-\tadd.w\tr3, r9, r5\n-\tvldr\td28, [ip]\n-\tvldr\td26, [r0]\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tvsub.f64\td6, d5, d28\n-\tvadd.f64\td28, d5, d28\n-\tvsub.f64\td31, d17, d26\n-\tvadd.f64\td17, d17, d26\n-\tvldr\td26, [r3]\n-\tldr\tr5, [sp, #16]\n-\tvmov.f64\td4, d6\n-\tvsub.f64\td5, d28, d17\n-\tvadd.f64\td28, d28, d17\n-\tvsub.f64\td17, d30, d26\n-\tadd.w\tr2, r9, r5\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvldr\td4, [r2]\n+\tadds\tr2, r0, r3\n+\tstr\tr2, [sp, #192]\t@ 0xc0\n+\tvldr\td6, [r2]\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tadd.w\tr4, ip, r2\n+\tldr\tr2, [sp, #32]\n+\tstr\tr4, [sp, #168]\t@ 0xa8\n+\tvsub.f64\td7, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvldr\td2, [r4]\n+\tadd.w\tr4, ip, r2\n+\tstr\tr4, [sp, #196]\t@ 0xc4\n+\tvmul.f64\td7, d7, d12\n+\tvldr\td6, [r4]\n+\tadd.w\tr4, ip, r5\n+\tstr\tr4, [sp, #176]\t@ 0xb0\n \tadd\tr5, r1\n-\tstr\tr5, [sp, #16]\n-\tadd.w\tr5, r9, r4\n-\tvadd.f64\td30, d30, d26\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tvfma.f64\td6, d16, d17\n-\tvfma.f64\td4, d17, d18\n-\tvldr\td29, [r5]\n-\tvldr\td17, [r2]\n-\tvstr\td2, [r2]\n-\tldr\tr4, [sp, #32]\n-\tvsub.f64\td26, d17, d29\n-\tvsub.f64\td27, d29, d17\n-\tvadd.f64\td17, d17, d29\n-\tvfma.f64\td27, d16, d31\n-\tldr\tr2, [sp, #8]\n-\tvmov.f64\td29, d26\n-\tvfma.f64\td26, d31, d18\n-\tvfma.f64\td29, d16, d31\n-\tvsub.f64\td3, d30, d17\n-\tvsub.f64\td31, d17, d30\n-\tvadd.f64\td17, d17, d30\n-\tvmul.f64\td3, d3, d21\n-\tvmul.f64\td27, d22, d27\n-\tvstr\td17, [sl]\n-\tvfma.f64\td3, d24, d5\n-\tvfma.f64\td27, d25, d6\n-\tadd.w\tsl, r7, r4\n-\tvmul.f64\td31, d31, d24\n-\tvmul.f64\td26, d25, d26\n-\tvnmul.f64\td17, d29, d20\n-\tvmul.f64\td29, d23, d29\n-\tvfma.f64\td17, d23, d4\n-\tvldr\td30, [sl]\n-\tvstr\td28, [r8]\n-\tvfma.f64\td31, d21, d5\n-\tvfma.f64\td26, d22, d6\n-\tvfma.f64\td29, d20, d4\n-\tadd.w\tr8, r9, r4\n-\tvstr\td17, [lr]\n-\tadd.w\tlr, r7, fp\n-\tvstr\td3, [ip]\n-\tadd.w\tip, r7, r2\n-\tvstr\td27, [sl]\n-\tadds\tr2, r4, r1\n-\tvldr\td6, [lr]\n-\tvldr\td17, [ip]\n-\tldr\tr4, [sp, #8]\n-\tstr\tr2, [sp, #32]\n-\tvsub.f64\td5, d6, d17\n-\tvadd.f64\td6, d6, d17\n-\tvldr\td17, [r8]\n+\tvsub.f64\td3, d2, d6\n+\tvadd.f64\td5, d2, d6\n+\tvsub.f64\td6, d6, d2\n+\tvadd.f64\td0, d7, d3\n+\tvadd.f64\td9, d6, d7\n+\tvldr\td6, [r4]\n+\tadd.w\tr4, ip, r3\n+\tvsub.f64\td7, d3, d7\n \tmov\tr2, r4\n-\tvstr\td29, [r6]\n-\tadd.w\tr6, r9, fp\n-\tvstr\td31, [r5]\n-\tadd.w\tr5, r9, r4\n-\tvstr\td26, [r8]\n-\tvsub.f64\td26, d7, d17\n-\tvsub.f64\td27, d17, d7\n-\tvadd.f64\td17, d7, d17\n-\tvldr\td29, [r5]\n-\tvfma.f64\td27, d16, d5\n-\tldr\tr4, [sp, #20]\n+\tadds\tr4, r3, r1\n+\tstr\tr2, [sp, #216]\t@ 0xd8\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvldr\td1, [r2]\n+\tldr\tr2, [sp, #32]\n+\tadd.w\tfp, r0, r3\n+\tadd\tr3, r1\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tadds\tr3, r0, r2\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tadds\tr3, r0, r7\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #148]\t@ 0x94\n \tadd\tr2, r1\n-\tvmov.f64\td28, d26\n-\tvfma.f64\td26, d5, d18\n-\tvfma.f64\td28, d16, d5\n-\tvldr\td5, [r6]\n-\tvstr\td19, [r6]\n-\tadd\tfp, r1\n-\tldr\tr6, [sp, #80]\t@ 0x50\n-\tvadd.f64\td19, d5, d29\n-\tstr\tr2, [sp, #8]\n-\tvsub.f64\td7, d5, d29\n-\tvmul.f64\td27, d22, d27\n-\tvsub.f64\td5, d19, d17\n-\tvsub.f64\td29, d17, d19\n-\tvadd.f64\td17, d17, d19\n-\tvnmul.f64\td31, d28, d20\n-\tvmul.f64\td28, d23, d28\n-\tvmul.f64\td26, d25, d26\n-\tvmul.f64\td29, d29, d24\n-\tvmul.f64\td5, d5, d21\n-\tvstr\td17, [r6]\n-\tadds\tr6, r7, r4\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #20]\n-\tvldr\td17, [r6]\n-\tvstr\td1, [r6]\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tvsub.f64\td19, d17, d30\n-\tvadd.f64\td17, d30, d17\n-\tvstr\td0, [lr]\n-\tldr\tr6, [sp, #76]\t@ 0x4c\n-\tvmov.f64\td30, d19\n-\tvfma.f64\td19, d16, d7\n-\tvfma.f64\td30, d7, d18\n-\tvsub.f64\td7, d17, d6\n-\tvadd.f64\td17, d17, d6\n-\tvfma.f64\td29, d21, d7\n-\tvfma.f64\td5, d24, d7\n-\tvstr\td17, [r2]\n+\tstr\tr2, [sp, #32]\n+\tvadd.f64\td2, d6, d1\n+\tadds\tr2, r0, r3\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n \tldr\tr2, [sp, #24]\n-\tvfma.f64\td27, d25, d19\n-\tvfma.f64\td26, d22, d19\n-\tvfma.f64\td28, d20, d30\n-\tvfma.f64\td31, d23, d30\n-\tvstr\td28, [r2]\n-\tvstr\td29, [r3]\n+\tvsub.f64\td6, d6, d1\n+\tstr\tr4, [sp, #144]\t@ 0x90\n+\tadd.w\tr4, ip, r8\n+\tadds\tr2, r0, r2\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #28]\n+\tvldr\td1, [fp]\n+\tvmul.f64\td6, d6, d12\n+\tadds\tr2, r0, r2\n+\tvstr\td9, [sp, #264]\t@ 0x108\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tvsub.f64\td9, d2, d5\n+\tstr\tr4, [sp, #208]\t@ 0xd0\n+\tadd.w\tr4, ip, r3\n+\tldr\tr2, [sp, #20]\n+\tstr\tr4, [sp, #224]\t@ 0xe0\n+\tadds\tr4, r3, r1\n+\tldr\tr3, [sp, #24]\n+\tstr\tr4, [sp, #148]\t@ 0x94\n+\tadd.w\tr4, ip, r2\n+\tldr\tr2, [sp, #28]\n+\tstr\tr4, [sp, #72]\t@ 0x48\n+\tadd.w\tr4, ip, r3\n+\tstr\tr4, [sp, #80]\t@ 0x50\n+\tadds\tr4, r3, r1\n+\tstr\tr4, [sp, #24]\n+\tadd.w\tr4, ip, r2\n+\tstr\tr4, [sp, #88]\t@ 0x58\n+\tadds\tr4, r2, r1\n+\tldr\tr2, [sp, #20]\n+\tstr\tr4, [sp, #28]\n+\tadds\tr3, r0, r2\n+\tadds\tr4, r2, r1\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tadds\tr3, r0, r6\n+\tldr\tr2, [sp, #184]\t@ 0xb8\n+\tstr\tr3, [sp, #220]\t@ 0xdc\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tstr\tr4, [sp, #20]\n+\tadd.w\tr4, ip, r6\n+\tstr\tr4, [sp, #232]\t@ 0xe8\n+\tadd.w\tr4, r0, lr\n+\tstr\tr4, [sp, #236]\t@ 0xec\n+\tadd.w\tr4, r0, r9\n+\tstr\tr4, [sp, #96]\t@ 0x60\n+\tadd.w\tr4, ip, r9\n+\tstr\tr4, [sp, #112]\t@ 0x70\n+\tadd.w\tr4, ip, r7\n+\tstr\tr4, [sp, #240]\t@ 0xf0\n+\tadd.w\tr4, ip, lr\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tadds\tr4, r0, r2\n+\tstr\tr4, [sp, #244]\t@ 0xf4\n+\tadd.w\tr4, r0, sl\n+\tstr\tr4, [sp, #252]\t@ 0xfc\n+\tadds\tr4, r0, r3\n+\tstr\tr4, [sp, #132]\t@ 0x84\n+\tadd.w\tr4, ip, r2\n+\tstr\tr4, [sp, #120]\t@ 0x78\n+\tadds\tr4, r2, r1\n+\tstr\tr4, [sp, #184]\t@ 0xb8\n+\tadd.w\tr4, ip, sl\n+\tstr\tr4, [sp, #272]\t@ 0x110\n+\tadd.w\tr4, ip, r3\n+\tadd\tr3, r1\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr6, r1\n+\tstr\tr4, [sp, #136]\t@ 0x88\n+\tadd.w\tr4, r0, r8\n+\tstr\tr4, [sp, #248]\t@ 0xf8\n+\tadd\tr9, r1\n+\tadd\tr7, r1\n+\tadd\tlr, r1\n+\tvldr\td8, [r3]\n+\tadd\tsl, r1\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tadd\tr8, r1\n+\tvstr\td7, [sp, #256]\t@ 0x100\n+\tvadd.f64\td3, d1, d8\n+\tldr\tr4, [sp, #200]\t@ 0xc8\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tvldr\td7, [r2]\n+\tvstr\td7, [sp, #160]\t@ 0xa0\n+\tvsub.f64\td7, d1, d8\n+\tvadd.f64\td1, d5, d2\n+\tvsub.f64\td5, d5, d2\n+\tvsub.f64\td2, d3, d4\n+\tvadd.f64\td3, d3, d4\n+\tvldr\td8, [r4]\n+\tvsub.f64\td4, d7, d6\n+\tvadd.f64\td7, d7, d6\n+\tvmul.f64\td6, d14, d0\n+\tvstr\td1, [r3]\n+\tvstr\td3, [fp]\n+\tvmul.f64\td0, d15, d0\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvldr\td3, [sp]\n+\tvmla.f64\td0, d14, d4\n+\tvnmls.f64\td6, d15, d4\n+\tvldr\td4, [sp, #256]\t@ 0x100\n+\tvstr\td6, [r4]\n+\tvmul.f64\td6, d13, d2\n+\tvmla.f64\td6, d9, d11\n+\tvmul.f64\td2, d11, d2\n+\tvmla.f64\td2, d5, d13\n+\tvmul.f64\td5, d3, d7\n+\tvmul.f64\td7, d10, d7\n+\tvmla.f64\td5, d4, d10\n+\tvldr\td9, [sp, #264]\t@ 0x108\n+\tvmov.f64\td1, d7\n+\tvmla.f64\td1, d9, d3\n+\tvstr\td6, [r2]\n+\tvldr\td6, [r3]\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tvstr\td2, [sp, #200]\t@ 0xc8\n+\tvldr\td4, [r3]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tvstr\td1, [sp, #256]\t@ 0x100\n+\tvldr\td9, [r3]\n+\tldr\tr3, [sp, #208]\t@ 0xd0\n+\tvldr\td2, [r3]\n+\tvstr\td5, [r3]\n+\tvsub.f64\td5, d4, d9\n+\tldr\tr3, [sp, #224]\t@ 0xe0\n+\tvadd.f64\td9, d4, d9\n+\tvldr\td4, [r2]\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tvstr\td2, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td5, d5, d12\n+\tvldr\td3, [r3]\n+\tvldr\td1, [r2]\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tvsub.f64\td2, d3, d4\n+\tldr\tr4, [sp, #220]\t@ 0xdc\n+\tvldr\td7, [r2]\n+\tvstr\td0, [r3]\n+\tvadd.f64\td0, d8, d6\n+\tvsub.f64\td8, d8, d6\n+\tvadd.f64\td6, d3, d4\n+\tvsub.f64\td4, d4, d3\n+\tvsub.f64\td3, d1, d7\n+\tvadd.f64\td7, d1, d7\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tldr\tr2, [sp, #188]\t@ 0xbc\n+\tvadd.f64\td4, d4, d5\n+\tvmul.f64\td3, d3, d12\n+\tvsub.f64\td1, d6, d7\n+\tvstr\td4, [sp, #208]\t@ 0xd0\n+\tvadd.f64\td4, d5, d2\n+\tvsub.f64\td5, d2, d5\n+\tvsub.f64\td2, d7, d6\n+\tvadd.f64\td6, d6, d7\n+\tvsub.f64\td7, d8, d3\n+\tvadd.f64\td8, d8, d3\n+\tvmul.f64\td3, d15, d4\n+\tvstr\td5, [sp, #224]\t@ 0xe0\n+\tvsub.f64\td5, d0, d9\n+\tvstr\td6, [r3]\n+\tvmul.f64\td6, d14, d4\n+\tvmla.f64\td3, d14, d7\n+\tvadd.f64\td0, d0, d9\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvldr\td4, [r4]\n+\tvnmls.f64\td6, d15, d7\n+\tvmul.f64\td7, d13, d5\n+\tvstr\td0, [r2]\n+\tvmla.f64\td7, d2, d11\n+\tldr\tr2, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td5, d11, d5\n+\tvmla.f64\td5, d1, d13\n+\tvstr\td8, [sp, #176]\t@ 0xb0\n+\tvldr\td2, [r2]\n+\tvstr\td6, [r3]\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tvstr\td7, [r4]\n+\tldr\tr4, [sp, #104]\t@ 0x68\n+\tvldr\td6, [sp, #200]\t@ 0xc8\n+\tvstr\td3, [r3]\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tvstr\td5, [r2]\n+\tldr\tr2, [sp, #236]\t@ 0xec\n+\tvldr\td5, [r4]\n+\tvldr\td0, [r3]\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvldr\td8, [r2]\n+\tvldr\td9, [r3]\n+\tldr\tr3, [sp, #240]\t@ 0xf0\n+\tvldr\td3, [r3]\n+\tvstr\td6, [r3]\n+\tvsub.f64\td6, d4, d0\n+\tvldr\td7, [sp, #160]\t@ 0xa0\n+\tvadd.f64\td0, d4, d0\n+\tvsub.f64\td1, d3, d5\n+\tvsub.f64\td4, d2, d9\n+\tvadd.f64\td9, d2, d9\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tvadd.f64\td2, d7, d8\n+\tvmul.f64\td6, d6, d12\n+\tvsub.f64\td7, d7, d8\n+\tvadd.f64\td8, d3, d5\n+\tvsub.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d12\n+\tldr\tr4, [sp, #244]\t@ 0xf4\n+\tvadd.f64\td3, d5, d6\n+\tvadd.f64\td5, d6, d1\n+\tvsub.f64\td1, d1, d6\n+\tvsub.f64\td6, d2, d0\n+\tvadd.f64\td0, d2, d0\n+\tvadd.f64\td2, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvsub.f64\td4, d9, d8\n+\tvstr\td3, [sp, #80]\t@ 0x50\n+\tvmul.f64\td3, d14, d5\n+\tvstr\td0, [sp, #56]\t@ 0x38\n+\tvmul.f64\td0, d15, d5\n+\tvmla.f64\td0, d14, d7\n+\tvmul.f64\td5, d13, d6\n+\tvnmls.f64\td3, d15, d7\n+\tvsub.f64\td7, d8, d9\n+\tvadd.f64\td8, d8, d9\n+\tvmla.f64\td5, d4, d11\n+\tvldr\td9, [sp, #80]\t@ 0x50\n+\tvmul.f64\td6, d11, d6\n+\tvldr\td4, [sp]\n+\tvmla.f64\td6, d7, d13\n+\tvmul.f64\td7, d10, d2\n+\tvstr\td8, [r3]\n+\tvmla.f64\td7, d9, d4\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvmul.f64\td2, d4, d2\n+\tvldr\td9, [r4]\n+\tvmla.f64\td2, d1, d10\n+\tvldr\td1, [sp, #56]\t@ 0x38\n+\tvstr\td1, [r3]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstr\td3, [r3]\n+\tvstr\td5, [r2]\n+\tvstr\td7, [r4]\n+\tldr\tr4, [sp, #132]\t@ 0x84\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #252]\t@ 0xfc\n+\tvldr\td8, [r4]\n+\tldr\tr4, [sp, #120]\t@ 0x78\n+\tvldr\td1, [r2]\n+\tvldr\td3, [r4]\n+\tvsub.f64\td4, d1, d8\n+\tldr\tr4, [sp, #104]\t@ 0x68\n+\tvadd.f64\td8, d1, d8\n+\tvstr\td0, [r3]\n+\tldr\tr3, [sp, #272]\t@ 0x110\n+\tvmul.f64\td4, d4, d12\n+\tvstr\td6, [r4]\n+\tldr\tr4, [sp, #120]\t@ 0x78\n+\tvstr\td2, [r4]\n+\tldr\tr4, [sp, #136]\t@ 0x88\n+\tvldr\td6, [r3]\n+\tvldr\td7, [r4]\n+\tldr\tr4, [sp, #248]\t@ 0xf8\n+\tvldr\td2, [sp, #168]\t@ 0xa8\n+\tvldr\td1, [sp, #256]\t@ 0x100\n+\tvsub.f64\td0, d6, d7\n+\tvadd.f64\td6, d6, d7\n+\tvadd.f64\td5, d2, d3\n+\tvldr\td7, [r4]\n+\tvstr\td1, [r4]\n+\tvsub.f64\td1, d2, d3\n+\tvsub.f64\td3, d3, d2\n+\tvmul.f64\td0, d0, d12\n+\tldr\tr4, [sp, #132]\t@ 0x84\n+\tvadd.f64\td2, d4, d1\n+\tvsub.f64\td1, d1, d4\n+\tvadd.f64\td3, d3, d4\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvmul.f64\td1, d14, d2\n+\tvstr\td3, [sp, #56]\t@ 0x38\n+\tvadd.f64\td3, d9, d7\n+\tvsub.f64\td7, d7, d9\n+\tvsub.f64\td9, d6, d5\n+\tvmul.f64\td2, d15, d2\n+\tvstr\td9, [sp, #48]\t@ 0x30\n+\tvsub.f64\td9, d5, d6\n+\tvadd.f64\td6, d5, d6\n+\tvadd.f64\td4, d7, d0\n+\tvsub.f64\td7, d7, d0\n+\tvldr\td5, [sp, #208]\t@ 0xd0\n+\tvldr\td0, [sp]\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvsub.f64\td6, d3, d8\n+\tvadd.f64\td3, d3, d8\n+\tvldr\td8, [sp, #176]\t@ 0xb0\n+\tvmla.f64\td2, d14, d7\n+\tvnmls.f64\td1, d15, d7\n+\tvmul.f64\td7, d10, d8\n+\tvmla.f64\td7, d5, d0\n+\tvldr\td5, [sp, #224]\t@ 0xe0\n+\tvstr\td7, [r2]\n+\tvmul.f64\td7, d0, d8\n+\tldr\tr2, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td7, d5, d10\n+\tvmul.f64\td5, d13, d6\n+\tvmul.f64\td6, d11, d6\n+\tvmla.f64\td6, d9, d13\n+\tvstr\td3, [r2]\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tvstr\td7, [r3]\n+\tvstr\td1, [r2]\n+\tldr\tr2, [sp, #216]\t@ 0xd8\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvstr\td7, [r2]\n+\tvmul.f64\td7, d10, d4\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tvmul.f64\td4, d0, d4\n+\tvstr\td2, [r2]\n+\tvldr\td2, [sp, #48]\t@ 0x30\n \tldr\tr2, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #4]\n-\tvstr\td31, [r6]\n-\tcmp\tr3, r2\n-\tvstr\td5, [r0]\n-\tvstr\td26, [r5]\n-\tvstr\td27, [ip]\n-\tbne.w\t1124 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1124>\n-\tstr\tr1, [sp, #24]\n-\tstr\tr7, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\tvmla.f64\td5, d2, d11\n+\tvstr\td5, [r2]\n \tldr\tr2, [sp, #112]\t@ 0x70\n+\tvstr\td6, [r2]\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmla.f64\td7, d6, d0\n+\tvstr\td7, [r4]\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tldr\tr4, [sp, #136]\t@ 0x88\n+\tldr\tr3, [sp, #8]\n+\tvmla.f64\td4, d1, d10\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tcmp\tr3, r2\n+\tvstr\td4, [r4]\n+\tbne.w\tcbe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xcbe>\n+\tmov\tlr, r0\n+\tmov\tfp, ip\n+\tstr\tr1, [sp, #32]\n+\tldr\tr3, [sp, #288]\t@ 0x120\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n-\tstr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #288]\t@ 0x120\n \tcmp\tr2, r3\n-\tble.n\t1546 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1546>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tble.n\t11d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x11d0>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr2, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #288]\t@ 0x120\n+\tldr\tr3, [sp, #296]\t@ 0x128\n+\tldr\tr2, [sp, #312]\t@ 0x138\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tcmp\tr2, r3\n-\tbne.w\tf50 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf50>\n-\tldr\tr2, [sp, #128]\t@ 0x80\n-\tldr\tr1, [sp, #132]\t@ 0x84\n-\tldr\tr3, [sp, #144]\t@ 0x90\n+\tstr\tr3, [sp, #296]\t@ 0x128\n+\tcmp\tr3, r2\n+\tbne.w\tada <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xada>\n+\tldr\tr1, [sp, #324]\t@ 0x144\n+\tmov\tr9, lr\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tldr.w\tlr, [sp, #328]\t@ 0x148\n+\tsubs\tr1, #1\n+\tldr.w\tsl, [sp, #32]\n+\tadds\tr2, r1, #1\n+\tadd\tlr, r3\n+\tbne.w\tac8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xac8>\n+\tmov\tr5, r3\n+\tldr\tr2, [sp, #476]\t@ 0x1dc\n+\tmov\tr3, fp\n+\tmov\tr7, r9\n+\tmov\tfp, sl\n+\tmov\tsl, r3\n+\tldr\tr3, [sp, #444]\t@ 0x1bc\n+\tldr\tr0, [sp, #416]\t@ 0x1a0\n+\tsubs\tr1, r3, #1\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n+\tstr\tr1, [sp, #444]\t@ 0x1bc\n+\tadds\tr1, #1\n+\tadd\tr0, r3\n+\tstr\tr0, [sp, #416]\t@ 0x1a0\n+\tldr\tr0, [sp, #412]\t@ 0x19c\n+\tadd\tr2, r3\n+\tsub.w\tr3, r0, r3\n+\tstr\tr3, [sp, #412]\t@ 0x19c\n+\tbne.w\ta92 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xa92>\n+\tmov\tr9, r7\n+\tldr\tr7, [sp, #464]\t@ 0x1d0\n+\tldrd\tr2, r8, [sp, #468]\t@ 0x1d4\n+\tadd\tr2, r7\n+\tldr\tr3, [sp, #420]\t@ 0x1a4\n+\tldr\tr0, [sp, #384]\t@ 0x180\n+\tsubs\tr1, r3, #1\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr4, [sp, #448]\t@ 0x1c0\n+\tadd\tr0, r3\n+\tstr\tr0, [sp, #384]\t@ 0x180\n+\tldr\tr0, [sp, #408]\t@ 0x198\n+\tstr\tr1, [sp, #420]\t@ 0x1a4\n+\tadds\tr1, #1\n+\tadd\tr0, r4\n+\tstr\tr0, [sp, #408]\t@ 0x198\n+\tldr\tr0, [sp, #392]\t@ 0x188\n+\tsub.w\tr0, r0, r3\n+\tstr\tr0, [sp, #392]\t@ 0x188\n+\tldr\tr0, [sp, #388]\t@ 0x184\n+\tadd\tr0, r3\n+\tldr\tr3, [sp, #440]\t@ 0x1b8\n+\tstr\tr0, [sp, #388]\t@ 0x184\n+\tmov\tr0, r3\n+\tbeq.w\t2ab8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ab8>\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #440]\t@ 0x1b8\n+\tb.w\ta1a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xa1a>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tadds\tr7, r2, #1\n+\tldr.w\tlr, [sp, #348]\t@ 0x15c\n+\tmov\tr0, r3\n+\tldr\tr2, [sp, #0]\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n+\tadd\tr2, r0\n+\tcmp\tr2, r4\n+\titt\tlt\n+\tldrlt\tr4, [sp, #280]\t@ 0x118\n+\taddlt\tr2, r2, r4\n+\tldr\tr4, [sp, #596]\t@ 0x254\n+\tcmp\tr4, #0\n+\tble.n\t12e0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x12e0>\n+\tlsls\tr2, r2, #3\n+\tlsls\tr4, r0, #3\n+\tldr.w\tfp, [sp, #348]\t@ 0x15c\n+\tadd.w\tip, sl, r4\n+\tadd.w\tr5, sl, r2\n+\tadd\tr4, r9\n+\tadd\tr2, r9\n+\tstr\tr3, [sp, #20]\n+\tvldr\td4, [r5, #-8]\n+\tadd.w\tfp, fp, #1\n+\tvldr\td6, [ip, #-8]\n+\tcmp\tfp, r7\n+\tvldr\td7, [r4, #-8]\n+\tvldr\td5, [r2, #-8]\n+\tvadd.f64\td3, d6, d4\n+\tvsub.f64\td6, d6, d4\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tvadd.f64\td4, d7, d5\n+\tvsub.f64\td7, d7, d5\n+\tvstr\td3, [ip, #-8]\n+\tadd\tip, r3\n+\tvstr\td6, [r5, #-8]\n+\tadd\tr5, r3\n+\tvstr\td4, [r4, #-8]\n+\tadd\tr4, r3\n+\tvstr\td7, [r2, #-8]\n+\tadd\tr2, r3\n+\tbne.n\t129c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x129c>\n+\tldr\tr3, [sp, #20]\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n+\tadd\tr0, r2\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr0, r2\n+\tbge.n\t12ee <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x12ee>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n+\tadd\tr0, r2\n+\tldr\tr2, [sp, #8]\n+\tadd.w\tlr, lr, #1\n+\tcmp\tlr, r2\n+\tbne.n\t1272 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1272>\n+\tsubs\tr1, #1\n+\tadd\tr3, r8\n+\tadds\tr0, r1, #1\n+\tbne.n\t126c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x126c>\n+\tb.w\t21c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x21c>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tmovs\tr3, #1\n+\tstr.w\tr9, [sp, #28]\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n+\tadd\tr2, r3\n+\tldr.w\tfp, [sp, #356]\t@ 0x164\n+\tldr.w\tr9, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tstr\tr2, [sp, #24]\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tldr\tr7, [sp, #280]\t@ 0x118\n+\tmov\tr4, r3\n+\tlsls\tr3, r3, #2\n+\tmov\tr0, r7\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r7\n+\tmov\tr5, r0\n+\tlsls\tr7, r0, #2\n+\tstr\tr3, [sp, #20]\n+\tbmi.w\t188c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x188c>\n+\tldr\tr0, [sp, #316]\t@ 0x13c\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #404]\t@ 0x194\n+\tmov\tr3, r0\n+\tcmp\tr2, #0\n+\tbne.w\t14a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x14a4>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tcmp\tr2, #0\n+\tble.w\t14a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x14a4>\n+\tldr\tr2, [sp, #584]\t@ 0x248\n+\tcmp\tr2, #1\n+\tmov\tr2, r9\n+\titt\teq\n+\tstreq\tr5, [sp, #128]\t@ 0x80\n+\tmoveq\tr5, r4\n+\tbne.w\t171a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x171a>\n+\tmov\tr8, r2\n+\tmovs\tr1, #1\n+\tstr\tr6, [sp, #32]\n+\tstr\tr1, [sp, #0]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr7, [sp, #48]\t@ 0x30\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #20]\n+\tadd\tr3, r8\n+\tcmp\tr9, r3\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #20]\n+\tadd\tr2, r3\n+\tcmp\tr9, r2\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #20]\n+\tadd\tr1, r2\n+\tcmp\tr9, r1\n+\titt\tgt\n+\tldrgt\tr0, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r0\n+\tldr\tr0, [sp, #596]\t@ 0x254\n+\tcmp\tr0, #0\n+\tble.n\t1474 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1474>\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr1, r1, #536870912\t@ 0x20000000\n+\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tsubs\tr3, #1\n+\tsubs\tr1, #1\n+\tadd.w\tr4, r8, #536870912\t@ 0x20000000\n+\tldr\tr6, [sp, #28]\n+\tadd.w\tlr, r0, r8\n \tsubs\tr2, #1\n-\tldr.w\tsl, [sp, #24]\n-\tadds\tr0, r2, #1\n-\tldr.w\tfp, [sp, #76]\t@ 0x4c\n-\tadd\tr1, r3\n-\tbne.w\tf3e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf3e>\n+\tldr\tr0, [sp, #344]\t@ 0x158\n+\tsubs\tr4, #1\n+\tlsls\tr3, r3, #3\n+\tlsls\tr1, r1, #3\n+\tlsls\tr2, r2, #3\n+\tlsls\tr4, r4, #3\n+\tadd.w\tr7, sl, r3\n+\tadd\tr3, r6\n+\tstr\tr3, [sp, #8]\n+\tadd.w\tr3, sl, r1\n+\tadd.w\tlr, r0, lr, lsl #3\n+\tadd.w\tip, sl, r2\n+\tadd.w\tr0, sl, r4\n+\tadd\tr2, r6\n+\tadd\tr4, r6\n+\tadd\tr1, r6\n \tmov\tr6, r3\n-\tldr\tr3, [sp, #268]\t@ 0x10c\n-\tldrd\tr4, r0, [sp, #244]\t@ 0xf4\n-\tldrd\tip, r5, [sp, #252]\t@ 0xfc\n-\tldrd\tlr, r7, [sp, #260]\t@ 0x104\n+\tldr\tr3, [sp, #8]\n+\tvldr\td8, [r6]\n+\tvldr\td0, [r1]\n+\tvldr\td6, [r7]\n+\tvldr\td3, [r3]\n+\tvldr\td9, [r0]\n+\tvsub.f64\td2, d6, d8\n+\tvldr\td4, [ip]\n+\tvsub.f64\td5, d3, d0\n+\tvldr\td7, [r4]\n+\tvldr\td10, [r2]\n+\tvadd.f64\td3, d0, d3\n+\tvadd.f64\td1, d4, d9\n+\tvadd.f64\td6, d8, d6\n+\tvsub.f64\td4, d9, d4\n+\tvmul.f64\td2, d2, d12\n+\tvadd.f64\td0, d10, d7\n+\tvmul.f64\td5, d5, d12\n+\tvsub.f64\td7, d7, d10\n+\tvadd.f64\td8, d6, d1\n+\tvsub.f64\td6, d1, d6\n+\tvadd.f64\td1, d3, d0\n+\tvsub.f64\td0, d0, d3\n+\tvsub.f64\td3, d4, d5\n+\tvadd.f64\td5, d5, d4\n+\tvadd.f64\td4, d7, d2\n+\tvsub.f64\td7, d7, d2\n+\tvstmia\tr0!, {d8}\n+\tcmp\tr0, lr\n+\tvstmia\tr4!, {d1}\n+\tvstmia\tip!, {d6}\n+\tvstmia\tr2!, {d0}\n+\tvstmia\tr7!, {d3}\n+\tvstmia\tr3!, {d4}\n+\tvstmia\tr6!, {d5}\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t13e8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x13e8>\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n+\tldr\tr2, [sp, #24]\n+\tadd\tr8, r3\n+\tcmp\tr9, r8\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #0]\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #0]\n+\tcmp\tr3, r2\n+\tbne.w\t1374 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1374>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr7, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tsubs\tr3, #1\n+\tldr\tr6, [sp, #32]\n+\tadds\tr0, r3, #1\n+\tadd\tr2, r7\n+\tbne.w\t1366 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1366>\n+\tmov\tr4, r5\n+\tldr\tr5, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #592]\t@ 0x250\n+\tcmp\tr3, #2\n+\tbeq.w\t1886 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1886>\n+\tlsls\tr4, r4, #1\n+\tsubs\tr5, r5, r6\n+\tcmp\tr6, #0\n+\tblt.w\t2d38 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d38>\n+\tmov\tr1, r6\n+\tsubs\tr0, r5, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tstr\tr0, [sp, #32]\n+\tbgt.w\t2d22 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d22>\n+\tldr\tr3, [sp, #584]\t@ 0x248\n+\tcmp\tr3, #1\n+\tmov.w\tr3, #24\n+\tbne.w\t2d52 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d52>\n+\tmul.w\tr5, r3, r4\n+\tlsls\tr2, r4, #3\n+\tlsls\tr3, r4, #4\n+\tldr\tr4, [sp, #376]\t@ 0x178\n+\tadd.w\tr0, r5, #8\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tip, r4, r0\n+\tldr\tr0, [sp, #316]\t@ 0x13c\n+\tadds\tr1, r4, r2\n+\tstr\tr5, [sp, #88]\t@ 0x58\n+\tsubs\tr4, r0, r6\n+\tadds\tr3, r1, r2\n+\tsubs\tr0, r6, r0\n+\tmov\tr5, r7\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tnegs\tr0, r7\n+\tldr\tr7, [sp, #28]\n+\tmov\tr8, r6\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tmov\tr4, ip\n+\tstr.w\tfp, [sp, #96]\t@ 0x60\n+\tmov\tfp, r3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr0, [sp, #72]\t@ 0x48\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tcmp\tr5, #0\n+\tvldr\td7, [r4, #-8]\n+\tvldr\td13, [r1, #8]\n+\tvldr\td10, [r4]\n+\tvldr\td15, [r3, #8]\n+\tvstr\td7, [sp, #8]\n+\tvldr\td7, [sp, #360]\t@ 0x168\n+\tvldr\td11, [r1]\n+\tvldr\td14, [r3]\n+\tvmul.f64\td13, d7, d13\n+\tvmul.f64\td15, d7, d15\n+\tvmul.f64\td10, d7, d10\n+\tblt.w\t18a0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18a0>\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t16ec <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16ec>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tcmp\tr2, #0\n+\tble.w\t16ec <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16ec>\n+\tadd.w\tr2, r9, r8\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr.w\tr8, [sp, #112]\t@ 0x70\n+\tstr.w\tfp, [sp, #120]\t@ 0x78\n+\tmov\tr8, r2\n+\tmov.w\tfp, #1\n+\tstrd\tr5, r3, [sp, #132]\t@ 0x84\n+\tstrd\tr2, r4, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #20]\n+\tadd\tr3, r8\n+\tcmp\tr9, r3\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #20]\n+\tadd\tr2, r3\n+\tcmp\tr9, r2\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #20]\n+\tadds\tr0, r1, r2\n+\tcmp\tr9, r0\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r1\n+\tldr\tr1, [sp, #596]\t@ 0x254\n+\tcmp\tr1, #0\n+\tble.w\t16b8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16b8>\n+\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n+\tadd.w\tr4, r8, #536870912\t@ 0x20000000\n+\tadd.w\tlr, r1, r8\n+\tsubs\tr2, #1\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tsubs\tr3, #1\n+\tsubs\tr0, #1\n \tsubs\tr4, #1\n-\tldr\tr2, [sp, #188]\t@ 0xbc\n-\tadd\tr3, r7\n-\tsubs\tr5, r5, r7\n+\tlsls\tr2, r2, #3\n+\tlsls\tr3, r3, #3\n+\tlsls\tr0, r0, #3\n+\tlsls\tr4, r4, #3\n+\tadd.w\tlr, r1, lr, lsl #3\n+\tadd.w\tip, sl, r2\n+\tadd.w\tr1, sl, r4\n+\tadd.w\tr6, sl, r3\n+\tadd.w\tr5, sl, r0\n+\tadd\tr4, r7\n \tadd\tr2, r7\n-\tstr\tr2, [sp, #188]\t@ 0xbc\n-\tadds\tr2, r4, #1\n-\tbne.w\tf06 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf06>\n-\tldr.w\tr8, [sp, #240]\t@ 0xf0\n-\tldr\tr3, [sp, #216]\t@ 0xd8\n-\tldr\tr1, [sp, #172]\t@ 0xac\n-\tsubs\tr2, r3, #1\n-\tldr\tr3, [sp, #136]\t@ 0x88\n-\tstr\tr2, [sp, #216]\t@ 0xd8\n-\tadds\tr2, #1\n-\tadd\tr1, r3\n-\tstr\tr1, [sp, #172]\t@ 0xac\n-\tldr\tr1, [sp, #224]\t@ 0xe0\n-\tsub.w\tip, ip, r3\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tadd\tr8, r1\n-\tldr\tr1, [sp, #220]\t@ 0xdc\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #212]\t@ 0xd4\n-\tstr\tr3, [sp, #184]\t@ 0xb8\n-\tmov\tr3, r1\n-\tbeq.w\t26c4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26c4>\n-\tmov\tr2, r1\n-\tldr\tr1, [sp, #228]\t@ 0xe4\n+\tadd\tr3, r7\n+\tadd\tr0, r7\n+\tvldr\td3, [r5]\n+\tvldr\td8, [r6]\n+\tvldr\td2, [r4]\n+\tvldr\td1, [r3]\n+\tvsub.f64\td4, d8, d3\n+\tvldr\td5, [r2]\n+\tvldr\td6, [r0]\n+\tvadd.f64\td8, d3, d8\n+\tvldr\td9, [r1]\n+\tvadd.f64\td3, d5, d2\n+\tvldr\td0, [ip]\n+\tvmul.f64\td4, d4, d12\n+\tvsub.f64\td7, d1, d6\n+\tvadd.f64\td6, d6, d1\n+\tvsub.f64\td1, d2, d5\n+\tvsub.f64\td5, d5, d2\n+\tvadd.f64\td2, d0, d9\n+\tvmul.f64\td7, d7, d12\n+\tvadd.f64\td5, d5, d4\n+\tvstr\td5, [sp]\n+\tvsub.f64\td5, d9, d0\n+\tvadd.f64\td0, d1, d4\n+\tvsub.f64\td9, d1, d4\n+\tvsub.f64\td1, d6, d3\n+\tvsub.f64\td4, d3, d6\n+\tvadd.f64\td6, d6, d3\n+\tvmul.f64\td3, d0, d13\n+\tvstmia\tr4!, {d6}\n+\tvsub.f64\td6, d5, d7\n+\tvadd.f64\td7, d7, d5\n+\tvsub.f64\td5, d2, d8\n+\tvadd.f64\td8, d8, d2\n+\tvnmls.f64\td3, d6, d11\n+\tvmul.f64\td6, d6, d13\n+\tvmla.f64\td6, d0, d11\n+\tvstmia\tr1!, {d8}\n+\tcmp\tr1, lr\n+\tvstmia\tr6!, {d3}\n+\tvmul.f64\td3, d5, d14\n+\tvmla.f64\td3, d1, d15\n+\tvmul.f64\td5, d5, d15\n+\tvldr\td1, [sp, #8]\n+\tvmla.f64\td5, d4, d14\n+\tvldr\td4, [sp]\n+\tvstmia\tr3!, {d6}\n+\tvmul.f64\td2, d7, d1\n+\tvmul.f64\td7, d7, d10\n+\tvmla.f64\td2, d4, d10\n+\tvmla.f64\td7, d9, d1\n+\tvstmia\tip!, {d3}\n+\tvstmia\tr2!, {d5}\n+\tvstmia\tr5!, {d2}\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t15e4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x15e4>\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n+\tadd.w\tfp, fp, #1\n+\tadd\tr8, r3\n+\tcmp\tr9, r8\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #24]\n+\tcmp\tfp, r3\n+\tbne.w\t1576 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1576>\n+\tldrd\tr5, r3, [sp, #132]\t@ 0x84\n+\tldrd\tr2, r4, [sp, #144]\t@ 0x90\n+\tsubs\tr3, #1\n+\tadds\tr6, r3, #1\n+\tadd\tr2, r5\n+\tbne.w\t1568 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1568>\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr.w\tr8, [sp, #112]\t@ 0x70\n+\tldr.w\tfp, [sp, #120]\t@ 0x78\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tadd\tr8, r6\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #32]\n \tadd\tr2, r1\n-\tstr\tr2, [sp, #212]\t@ 0xd4\n-\tb.n\tebc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xebc>\n-\tmov\tr2, r3\n-\tasrs\tr3, r3, #1\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tsubs\tr3, #1\n+\tmov\tr1, fp\n+\tstr\tr3, [sp, #32]\n+\tsubs\tr2, r2, r6\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadds\tr3, #1\n-\tbic.w\tr3, r3, #1\n-\tstr\tr3, [sp, #388]\t@ 0x184\n-\tsubs\tr2, r2, r3\n-\tstr\tr2, [sp, #196]\t@ 0xc4\n-\tb.w\t10c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x10c>\n-\tldr\tr3, [sp, #152]\t@ 0x98\n+\tadd\tr2, r6\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tadd\tr4, r2\n+\tbeq.w\t2d1e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d1e>\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tfp, r3\n+\tb.n\t150c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x150c>\n+\tldr\tr1, [sp, #596]\t@ 0x254\n+\tmov\tlr, sl\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #32]\n+\tmov\tr1, r2\n+\tmov.w\tr8, #1\n+\tmov\tsl, r4\n+\tmov\tip, r2\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tstr\tr7, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #20]\n+\tadd\tr3, r1\n+\tcmp\tr3, r9\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr3, r3, r2\n+\tldr\tr2, [sp, #20]\n+\tadd\tr2, r3\n+\tcmp\tr2, r9\n+\titt\tlt\n+\tldrlt\tr0, [sp, #280]\t@ 0x118\n+\taddlt\tr2, r2, r0\n+\tldr\tr0, [sp, #20]\n+\tadd\tr0, r2\n+\tcmp\tr0, r9\n+\titt\tlt\n+\tldrlt\tr4, [sp, #280]\t@ 0x118\n+\taddlt\tr0, r0, r4\n+\tldr\tr4, [sp, #596]\t@ 0x254\n+\tcmp\tr4, #0\n+\tble.n\t184e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x184e>\n+\tlsls\tr0, r0, #3\n+\tstr\tr0, [sp, #128]\t@ 0x80\n+\tldr\tr0, [sp, #28]\n+\tlsls\tr3, r3, #3\n+\tadd.w\tr6, lr, r3\n+\tlsls\tr5, r1, #3\n+\tadd\tr3, r0\n+\tstr\tr3, [sp, #8]\n+\tlsls\tr2, r2, #3\n+\tmovs\tr3, #1\n+\tstr\tr3, [sp, #0]\n+\tadd.w\tr7, lr, r2\n+\tldr\tr3, [sp, #8]\n+\tadd\tr2, r0\n+\tadd.w\tr4, lr, r5\n+\tadd\tr0, r5\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n+\tstr.w\tr9, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tstr\tr5, [sp, #104]\t@ 0x68\n+\tldr\tr1, [sp, #0]\n+\tldr\tr5, [sp, #104]\t@ 0x68\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #8]\n+\tstr\tr1, [sp, #0]\n+\tsub.w\tr8, r4, r5\n+\tldr\tr1, [sp, #128]\t@ 0x80\n+\tsub.w\tr9, r0, r5\n+\tvldr\td3, [r7, #-8]\n+\tvldr\td1, [r2, #-8]\n+\tadd\tr8, r1\n+\tvldr\td7, [r4, #-8]\n+\tadd\tr9, r1\n+\tvldr\td5, [r0, #-8]\n+\tvldr\td4, [r6, #-8]\n+\tvadd.f64\td2, d7, d3\n+\tvsub.f64\td7, d7, d3\n+\tvadd.f64\td3, d5, d1\n+\tvsub.f64\td5, d5, d1\n+\tvldr\td1, [r8, #-8]\n+\tvldr\td6, [r3, #-8]\n+\tldr\tr1, [sp, #8]\n+\tvsub.f64\td0, d4, d1\n+\tvadd.f64\td4, d4, d1\n+\tldr\tr5, [sp, #32]\n+\tcmp\tr1, r5\n+\tvadd.f64\td1, d2, d4\n+\tvsub.f64\td4, d2, d4\n+\tvmul.f64\td0, d0, d12\n+\tvstr\td1, [r4, #-8]\n+\tadd\tr4, fp\n+\tvldr\td1, [r9, #-8]\n+\tvadd.f64\td2, d0, d5\n+\tvstr\td4, [r7, #-8]\n+\tvsub.f64\td5, d5, d0\n+\tadd\tr7, fp\n+\tvsub.f64\td4, d6, d1\n+\tvadd.f64\td6, d6, d1\n+\tvmul.f64\td4, d4, d12\n+\tvadd.f64\td1, d3, d6\n+\tvsub.f64\td3, d3, d6\n+\tvsub.f64\td6, d7, d4\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td1, [r0, #-8]\n+\tadd\tr0, fp\n+\tvstr\td3, [r2, #-8]\n+\tadd\tr2, fp\n+\tvstr\td2, [r3, #-8]\n+\tadd\tr3, fp\n+\tvstr\td6, [r6, #-8]\n+\tadd\tr6, fp\n+\tvstr\td5, [r9, #-8]\n+\tvstr\td7, [r8, #-8]\n+\tbne.n\t1790 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1790>\n+\tldr.w\tr8, [sp, #80]\t@ 0x50\n+\tldr.w\tr9, [sp, #88]\t@ 0x58\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n+\tadd\tr1, r3\n+\tcmp\tr1, r9\n+\tbge.n\t185a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x185a>\n+\tldr\tr3, [sp, #280]\t@ 0x118\n+\tadd\tr1, r3\n+\tldr\tr3, [sp, #24]\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr8, r3\n+\tbne.w\t1734 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1734>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmov\tr2, ip\n+\tldr\tr7, [sp, #72]\t@ 0x48\n+\tmov\tr4, sl\n+\tsubs\tr3, #1\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tadd\tr2, r7\n+\tadds\tr1, r3, #1\n+\tbne.w\t1722 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1722>\n+\tldr\tr3, [sp, #592]\t@ 0x250\n+\tmov\tsl, lr\n+\tcmp\tr3, #2\n+\tbne.w\t14ac <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x14ac>\n+\tldr.w\tr9, [sp, #28]\n+\tb.n\t1f12 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f12>\n+\tldr\tr0, [sp, #372]\t@ 0x174\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, #0\n+\tble.w\t134e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x134e>\n+\tb.n\t14a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x14a4>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t1552 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1552>\n+\tb.n\t16ec <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16ec>\n+\trsb\tr1, r8, #0\n+\tldr\tr0, [sp, #372]\t@ 0x174\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tmov\tr1, r0\n \tcmp\tr3, #0\n-\tbeq.w\t81a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x81a>\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tble.w\t172 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x172>\n+\tb.w\t21c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x21c>\n+\tldr\tr3, [sp, #352]\t@ 0x160\n+\tcmp\tr3, #0\n+\tbeq.w\t378 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x378>\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n+\tldr\tr4, [sp, #280]\t@ 0x118\n+\tvldr\td14, [pc, #768]\t@ 1be0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1be0>\n \tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tsdiv\tr1, r2, r3\n-\tsubs\tr3, r1, r2\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #392]\t@ 0x188\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r4\n+\tstr\tr3, [sp, #0]\n+\tvmov.f64\td3, #240\t@ 0xbf800000 -1.0\n+\tldr\tr3, [sp, #600]\t@ 0x258\n+\tlsls\tr7, r0, #3\n+\tvldr\td6, [pc, #748]\t@ 1be8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1be8>\n \tadds\tr3, #1\n-\tldr\tr3, [sp, #204]\t@ 0xcc\n-\tbne.n\t15fe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x15fe>\n-\trsb\tr3, r3, #8\n-\tbic.w\tr2, r3, #4\n-\tvldr\td23, [pc, #772]\t@ 1908 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1908>\n-\tcmp\tr2, #3\n-\tvldr\td19, [pc, #772]\t@ 1910 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1910>\n-\tsub.w\tr3, r3, #3\n-\tvmov.f64\td17, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n+\tldr\tr3, [sp, #432]\t@ 0x1b0\n+\tit\teq\n+\trsbeq\tr3, r3, #8\n+\tbic.w\tr1, r3, #4\n+\tsubs\tr3, #3\n+\tcmp\tr1, #3\n \tbic.w\tr3, r3, #2\n-\tvseleq.f64\td20, d23, d19\n-\tvseleq.f64\td24, d19, d23\n-\tvseleq.f64\td17, d17, d21\n+\tite\tne\n+\tvmovne.f64\td5, d14\n+\tvmoveq.f64\td5, d6\n+\tite\tne\n+\tvmovne.f64\td13, d6\n+\tvmoveq.f64\td13, d14\n+\tit\teq\n+\tvmoveq.f64\td15, d3\n \tcmp\tr3, #0\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tvseleq.f64\td24, d24, d20\n-\tvseleq.f64\td23, d23, d19\n-\tsubs\tr0, r1, r2\n-\tcmp\tr2, #0\n-\tmov.w\tr1, r1, lsl #3\n-\tblt.w\t238c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x238c>\n-\tudiv\tr3, r0, r2\n-\tcmp\tr0, #0\n-\tblt.w\t1932 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1932>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\trsb\tlr, r1, #0\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tit\tne\n+\tvmovne.f64\td13, d5\n+\tit\teq\n+\tvmoveq.f64\td14, d6\n+\tsub.w\tr8, r0, r3\n+\tcmp\tr3, #0\n+\tblt.w\t275c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x275c>\n+\tmov\tr1, r3\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp.w\tr8, #0\n+\tmov\tr3, r0\n+\tblt.w\t1c54 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c54>\n+\tnegs\tr2, r7\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #584]\t@ 0x248\n \tcmp\tr2, #1\n-\tbne.w\t23a6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23a6>\n-\tldr.w\tr9, [sp, #124]\t@ 0x7c\n-\tmovs\tr2, #0\n-\tldr\tr5, [sp, #120]\t@ 0x78\n-\tmov\tip, r0\n-\tstr.w\tr8, [sp, #40]\t@ 0x28\n-\tmov\tr7, r9\n-\tldr\tr4, [sp, #164]\t@ 0xa4\n-\tadds\tr5, #1\n-\tldr.w\tr8, [sp, #136]\t@ 0x88\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tsub.w\tr5, sl, #8\n-\tstr.w\tsl, [sp, #32]\n-\tstr\tr5, [sp, #56]\t@ 0x38\n-\tcmp\tr1, #0\n-\tblt.w\t2016 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2016>\n-\tudiv\tr0, r7, r1\n-\tcmp\tr9, r2\n-\tblt.w\t1918 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1918>\n-\tldr\tr5, [sp, #120]\t@ 0x78\n-\tcmp\tr5, #0\n-\tble.w\t1918 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1918>\n-\tldr\tr5, [sp, #28]\n-\tadd\tr5, r2\n-\tmovs\tr6, #1\n-\tstr\tr5, [sp, #24]\n-\tstr\tr6, [sp, #36]\t@ 0x24\n-\tstrd\tr8, ip, [sp, #60]\t@ 0x3c\n-\tstrd\tr3, lr, [sp, #68]\t@ 0x44\n-\tstrd\tr9, r2, [sp, #76]\t@ 0x4c\n-\tstrd\tr0, r1, [sp, #84]\t@ 0x54\n-\tstrd\tr5, r7, [sp, #96]\t@ 0x60\n+\tbne.w\t277c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x277c>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tmovs\tr4, #0\n+\tstr.w\tsl, [sp, #56]\t@ 0x38\n+\tldr.w\tfp, [sp, #372]\t@ 0x174\n+\tadds\tr2, #1\n+\tldr\tr5, [sp, #316]\t@ 0x13c\n+\tldr.w\tsl, [sp, #332]\t@ 0x14c\n+\tstr.w\tr9, [sp, #32]\n+\tmov\tr9, r8\n+\tmov\tr8, r3\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tcmp\tr7, #0\n+\tblt.w\t1f34 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f34>\n+\tmov\tr1, r7\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tblt.w\t1c36 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c36>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tcmp\tr2, #0\n+\tble.w\t1c36 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c36>\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tadd\tr2, r4\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr1, [sp, #48]\t@ 0x30\n+\tstr.w\tsl, [sp, #80]\t@ 0x50\n+\tstr.w\tr9, [sp, #88]\t@ 0x58\n+\tstr.w\tr8, [sp, #96]\t@ 0x60\n \tstr\tr4, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #24]\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr7, [sp, #120]\t@ 0x78\n+\tstrd\tr2, r5, [sp, #132]\t@ 0x84\n+\tstr.w\tfp, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n \tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r0\n-\tble.n\t16c2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16c2>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #4]\n+\tldr\tr6, [sp, #140]\t@ 0x8c\n+\tldr\tr7, [sp, #140]\t@ 0x8c\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #0]\n \tadds\tr5, r3, r0\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r5\n-\tble.n\t16d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16d0>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr5, r5, r3\n+\tldr\tr3, [sp, #0]\n \tadds\tr2, r3, r5\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r2\n-\tble.n\t16de <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16de>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #4]\n-\tldr\tr1, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #0]\n \tadd\tr3, r2\n \tcmp\tr1, r3\n-\tble.n\t16ec <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16ec>\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #4]\n-\tldr\tr4, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr1, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r1\n+\tldr\tr1, [sp, #0]\n \tadd\tr1, r3\n \tcmp\tr4, r1\n-\tble.n\t16fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16fa>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r4\n-\tldr\tr4, [sp, #4]\n-\tldr\tr6, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r4\n+\tldr\tr4, [sp, #0]\n \tadd\tr4, r1\n \tcmp\tr6, r4\n-\tble.n\t1708 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1708>\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r6\n-\tldr\tr6, [sp, #4]\n-\tldr\tr7, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr6, [sp, #280]\t@ 0x118\n+\taddgt\tr4, r4, r6\n+\tldr\tr6, [sp, #0]\n \tadd\tr6, r4\n \tcmp\tr7, r6\n-\tble.n\t1716 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1716>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\titt\tgt\n+\tldrgt\tr7, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tcmp\tr7, #0\n-\tble.w\t18c0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18c0>\n-\tadd.w\tr5, r5, #536870912\t@ 0x20000000\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n+\tble.w\t1bf0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bf0>\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n \tadd.w\tr6, r6, #536870912\t@ 0x20000000\n-\tsubs\tr5, #1\n-\tsubs\tr0, #1\n \tsubs\tr2, #1\n \tsubs\tr6, #1\n+\tadd.w\tr5, r5, #536870912\t@ 0x20000000\n+\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n-\tlsls\tr7, r5, #3\n \tmov.w\tip, r2, lsl #3\n-\tlsls\tr5, r0, #3\n-\tldr\tr2, [sp, #24]\n-\tlsls\tr0, r6, #3\n+\tsubs\tr5, #1\n+\tlsls\tr2, r6, #3\n+\tsubs\tr0, #1\n+\tstr\tr2, [sp, #20]\n+\tldr\tr6, [sp, #596]\t@ 0x254\n \tsubs\tr1, #1\n-\tldr\tr6, [sp, #388]\t@ 0x184\n-\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tmov.w\tlr, r1, lsl #3\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tlsls\tr7, r5, #3\n+\tlsls\tr5, r0, #3\n+\tlsls\tr0, r1, #3\n \tadd.w\tr1, r2, #536870912\t@ 0x20000000\n \tadds\tr2, r6, r2\n-\tldr\tr6, [sp, #56]\t@ 0x38\n+\tldr\tr6, [sp, #344]\t@ 0x158\n \tsubs\tr1, #1\n-\tsubs\tr4, #1\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n+\tlsls\tr1, r1, #3\n \tsubs\tr3, #1\n \tadd.w\tr2, r6, r2, lsl #3\n-\tldr\tr6, [sp, #32]\n-\tlsls\tr1, r1, #3\n-\tstr\tr2, [sp, #20]\n+\tldr\tr6, [sp, #56]\t@ 0x38\n+\tsubs\tr4, #1\n+\tstr\tr2, [sp, #28]\n \tadds\tr2, r6, r1\n-\tstr\tr2, [sp, #16]\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tlsls\tr4, r4, #3\n+\tstr\tr2, [sp, #24]\n+\tldr\tr2, [sp, #32]\n \tlsls\tr3, r3, #3\n-\tadd.w\tr9, r6, r4\n-\tadds\tr4, r2, r4\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tmov\tr4, r6\n+\tlsls\tr4, r4, #3\n \tadd.w\tfp, r6, r3\n \tadd.w\tsl, r6, r7\n \tadd\tr3, r2\n+\tadd.w\tr9, r6, r4\n \tadd.w\tr8, r6, r5\n+\tadds\tr4, r2, r4\n \tadd\tr1, r2\n-\tadd\tr6, lr\n+\tstr\tr4, [sp, #64]\t@ 0x40\n \tadd\tr7, r2\n+\tmov\tr4, r2\n \tadd\tr5, r2\n-\tstr\tr6, [sp, #8]\n-\tadd.w\tr6, r2, lr\n-\tadd.w\tlr, r4, ip\n-\tstr\tr6, [sp, #12]\n-\tadd.w\tr4, r2, ip\n-\tmov\tr6, r2\n \tldr\tr2, [sp, #32]\n-\tadd.w\tip, r2, r0\n-\tadd\tr0, r6\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #16]\n-\tvldr\td27, [r1]\n-\tvldr\td20, [fp]\n-\tvldr\td28, [r2]\n-\tvldr\td19, [r3]\n-\tvadd.f64\td22, d20, d28\n-\tvsub.f64\td28, d28, d20\n-\tvadd.f64\td21, d19, d27\n-\tvsub.f64\td27, d27, d19\n-\tvstmia\tr2!, {d22}\n-\tvstmia\tr1!, {d21}\n-\tvldr\td19, [r7]\n-\tvldr\td22, [r6]\n-\tvldr\td20, [sl]\n-\tvldr\td21, [r9]\n-\tvadd.f64\td25, d22, d19\n-\tvadd.f64\td26, d21, d20\n-\tvsub.f64\td21, d20, d21\n-\tvsub.f64\td20, d19, d22\n-\tvstmia\tr3!, {d25}\n-\tstr\tr3, [sp, #16]\n+\tadd.w\tlr, r6, r0\n+\tadd\tr4, r0\n+\tadd.w\tr0, r6, ip\n+\tstr\tr0, [sp, #8]\n+\tadd.w\tr0, r2, ip\n+\tmov\tr2, r6\n+\tldr\tr6, [sp, #20]\n+\tadd.w\tip, r2, r6\n+\tldr\tr2, [sp, #32]\n+\tadd\tr2, r6\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tstr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #24]\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #24]\n+\tvldr\td6, [r1]\n+\tvldr\td5, [fp]\n+\tvldr\td3, [r2]\n+\tvldr\td10, [r3]\n+\tvadd.f64\td2, d5, d3\n+\tvsub.f64\td3, d3, d5\n+\tvadd.f64\td4, d10, d6\n+\tvsub.f64\td10, d6, d10\n+\tvstmia\tr2!, {d2}\n+\tvstmia\tr1!, {d4}\n+\tvldr\td5, [sl]\n+\tvldr\td4, [r9]\n+\tvldr\td7, [r6]\n+\tvldr\td1, [r7]\n+\tvadd.f64\td6, d4, d5\n+\tvsub.f64\td5, d5, d4\n+\tvadd.f64\td4, d7, d1\n+\tvsub.f64\td1, d1, d7\n+\tvstmia\tfp!, {d6}\n+\tvmul.f64\td5, d5, d15\n+\tvldr\td6, [r8]\n+\tvstmia\tr3!, {d4}\n+\tvmul.f64\td11, d1, d15\n+\tvldr\td4, [lr]\n+\tvldr\td2, [r4]\n+\tvldr\td7, [r5]\n+\tvadd.f64\td1, d4, d6\n+\tstr\tr3, [sp, #24]\n \tldr\tr3, [sp, #8]\n-\tvmul.f64\td29, d21, d17\n-\tvstmia\tfp!, {d26}\n-\tvmul.f64\td26, d20, d17\n-\tvldr\td19, [r8]\n-\tvldr\td25, [r5]\n-\tvldr\td30, [r3]\n-\tldr\tr3, [sp, #12]\n-\tvadd.f64\td21, d30, d19\n-\tvsub.f64\td19, d19, d30\n-\tvldr\td22, [r3]\n+\tvsub.f64\td6, d6, d4\n+\tvadd.f64\td4, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvstmia\tsl!, {d1}\n+\tvldr\td2, [r3]\n+\tldr\tr3, [sp, #20]\n+\tvstmia\tr7!, {d4}\n+\tvsub.f64\td4, d6, d2\n+\tvldr\td1, [ip]\n+\tvldr\td9, [r0]\n+\tvldr\td8, [r3]\n+\tvadd.f64\td0, d1, d2\n+\tvsub.f64\td6, d6, d1\n+\tvadd.f64\td4, d4, d1\n+\tvsub.f64\td1, d7, d9\n+\tvsub.f64\td7, d7, d8\n \tldr\tr3, [sp, #8]\n-\tvstmia\tsl!, {d21}\n-\tvadd.f64\td20, d22, d25\n-\tvsub.f64\td25, d25, d22\n-\tvldr\td7, [lr]\n-\tvldr\td6, [ip]\n-\tvstmia\tr7!, {d20}\n-\tvsub.f64\td22, d19, d7\n-\tvldr\td30, [r4]\n-\tvsub.f64\td21, d19, d6\n-\tvldr\td31, [r0]\n-\tvadd.f64\td5, d6, d7\n-\tvsub.f64\td20, d25, d30\n-\tvadd.f64\td22, d22, d6\n-\tvsub.f64\td19, d25, d31\n-\tvadd.f64\td25, d31, d30\n-\tvadd.f64\td21, d21, d7\n-\tvstmia\tr9!, {d5}\n-\tvstmia\tr8!, {d28}\n-\tvadd.f64\td20, d20, d31\n-\tvstmia\tr3!, {d29}\n-\tvadd.f64\td19, d19, d30\n-\tvstmia\tr6!, {d25}\n-\tvstmia\tr5!, {d27}\n-\tvmul.f64\td22, d22, d23\n+\tvadd.f64\td6, d6, d2\n+\tvadd.f64\td2, d8, d9\n+\tvmul.f64\td4, d4, d14\n+\tvadd.f64\td1, d1, d8\n+\tvadd.f64\td7, d7, d9\n+\tvstmia\tr9!, {d0}\n+\tvstmia\tr8!, {d3}\n+\tvstmia\tr6!, {d2}\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td1, d1, d14\n+\tvstmia\tlr!, {d5}\n+\tvmul.f64\td7, d7, d13\n+\tvstmia\tr5!, {d10}\n+\tvstmia\tr3!, {d4}\n \tstr\tr3, [sp, #8]\n-\tvmul.f64\td21, d21, d24\n-\tldr\tr3, [sp, #12]\n-\tvmul.f64\td20, d20, d23\n-\tvmul.f64\td19, d19, d24\n-\tvstmia\tlr!, {d22}\n-\tvstmia\tip!, {d21}\n-\tvstmia\tr3!, {d26}\n-\tstr\tr3, [sp, #12]\n \tldr\tr3, [sp, #20]\n-\tvstmia\tr4!, {d20}\n+\tvstmia\tr4!, {d11}\n+\tvstmia\tr0!, {d1}\n+\tvstmia\tip!, {d6}\n+\tvstmia\tr3!, {d7}\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #28]\n \tcmp\tr2, r3\n-\tvstmia\tr0!, {d19}\n-\tbne.w\t17b8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x17b8>\n-\tldr\tr3, [sp, #24]\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tbne.w\t1ad0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ad0>\n+\tb.n\t1bf0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bf0>\n+\tnop\n+\tnop.w\n+\t.word\t0x667f3bcd\n+\t.word\t0x3fe6a09e\n+\t.word\t0x667f3bcd\n+\t.word\t0xbfe6a09e\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n-\tstr\tr3, [sp, #24]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tcmp\tr2, r3\n-\tble.n\t18d4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x18d4>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #48]\t@ 0x30\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #72]\t@ 0x48\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, r2\n-\tbne.w\t16b2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x16b2>\n-\tldrd\tr0, r1, [sp, #84]\t@ 0x54\n-\tldrd\tr5, r7, [sp, #96]\t@ 0x60\n-\tsubs\tr0, #1\n-\tldrd\tr8, ip, [sp, #60]\t@ 0x3c\n-\tadd\tr5, r1\n-\tldrd\tr3, lr, [sp, #68]\t@ 0x44\n-\tadds\tr6, r0, #1\n-\tldrd\tr9, r2, [sp, #76]\t@ 0x4c\n-\tldr\tr4, [sp, #104]\t@ 0x68\n-\tbne.w\t1696 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1696>\n-\tb.n\t1918 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1918>\n-\tnop.w\n-\t.word\t0x667f3bcd\n-\t.word\t0xbfe6a09e\n-\t.word\t0x667f3bcd\n-\t.word\t0x3fe6a09e\n+\tbne.w\t19c6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x19c6>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tldrd\tr2, r5, [sp, #132]\t@ 0x84\n \tsubs\tr3, #1\n-\tadd\tr2, r8\n-\tsub.w\tr7, r7, r8\n-\tadd\tr4, r8\n-\tadds\tr6, r3, #1\n-\tbne.w\t167a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x167a>\n-\tldr.w\tsl, [sp, #32]\n-\tmov\tr0, ip\n-\tldr.w\tr8, [sp, #40]\t@ 0x28\n-\tcmp\tr1, #0\n-\tblt.w\t237a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x237a>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tudiv\tr3, r3, r1\n+\tldr\tr7, [sp, #120]\t@ 0x78\n+\tadds\tr1, r3, #1\n+\tldr.w\tsl, [sp, #80]\t@ 0x50\n+\tldr.w\tr9, [sp, #88]\t@ 0x58\n+\tadd\tr2, r7\n+\tldr.w\tr8, [sp, #96]\t@ 0x60\n+\tldr\tr4, [sp, #104]\t@ 0x68\n+\tldr.w\tfp, [sp, #144]\t@ 0x90\n+\tbne.w\t19a6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x19a6>\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tadd\tr4, sl\n+\tsub.w\tr5, r5, sl\n+\tadd\tfp, sl\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tbne.w\t1982 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1982>\n+\tmov\tr8, r9\n+\tldr.w\tsl, [sp, #56]\t@ 0x38\n+\tldr.w\tr9, [sp, #32]\n+\tcmp\tr7, #0\n+\tblt.w\t2746 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2746>\n+\tldr\tr0, [sp, #316]\t@ 0x13c\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #404]\t@ 0x194\n+\tmov\tr3, r0\n \tcmp\tr2, #0\n-\tbne.w\t1bfc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bfc>\n-\tldr\tr2, [sp, #120]\t@ 0x78\n+\tbne.w\t1f0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f0c>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n \tcmp\tr2, #0\n-\tble.w\t1bfc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bfc>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n+\tble.w\t1f0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f0c>\n+\tldr\tr2, [sp, #584]\t@ 0x248\n+\tldr\tr1, [sp, #320]\t@ 0x140\n \tcmp\tr2, #1\n-\tbne.w\t2d64 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d64>\n-\tldr.w\tr9, [sp, #28]\n-\tvneg.f64\td24, d17\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tmov\tfp, r8\n-\tmov\tr2, r9\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #8]\n-\tsub.w\tr4, sl, #8\n-\tstr\tr4, [sp, #64]\t@ 0x40\n-\tldr.w\tip, [sp, #92]\t@ 0x5c\n-\tmov\tr8, r2\n-\tmovs\tr4, #1\n-\tstrd\tr0, r3, [sp, #68]\t@ 0x44\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tstrd\tr1, r2, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #4]\n-\tadd.w\tr0, r3, r8\n-\tldr\tr3, [sp, #4]\n-\tcmp\tr9, r0\n-\tldr\tr4, [sp, #4]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tadd.w\tr1, r1, #1\n+\tit\teq\n+\tmoveq\tfp, sl\n+\tstr\tr1, [sp, #8]\n+\tbne.w\t3004 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3004>\n+\tldr.w\tip, [sp, #280]\t@ 0x118\n+\tmov\tsl, r2\n+\tldr.w\tlr, [sp, #140]\t@ 0x8c\n+\tmovs\tr1, #1\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr7, [sp, #96]\t@ 0x60\n+\tstr\tr2, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #0]\n+\tadd.w\tr0, r3, sl\n+\tldr\tr3, [sp, #0]\n+\tcmp\tlr, r0\n+\tldr\tr4, [sp, #0]\n \tit\tgt\n \taddgt\tr0, ip\n-\tldr\tr6, [sp, #4]\n+\tldr\tr6, [sp, #0]\n \tadds\tr5, r3, r0\n-\tldr\tr3, [sp, #4]\n-\tcmp\tr9, r5\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\tldr\tr3, [sp, #0]\n+\tcmp\tlr, r5\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tit\tgt\n \taddgt\tr5, ip\n \tadds\tr1, r3, r5\n-\tldr\tr3, [sp, #4]\n-\tcmp\tr9, r1\n+\tldr\tr3, [sp, #0]\n+\tcmp\tlr, r1\n \tit\tgt\n \taddgt\tr1, ip\n \tadd\tr3, r1\n-\tcmp\tr9, r3\n+\tcmp\tlr, r3\n \tit\tgt\n \taddgt\tr3, ip\n \tadd\tr2, r3\n-\tcmp\tr9, r2\n+\tcmp\tlr, r2\n \tit\tgt\n \taddgt\tr2, ip\n \tadd\tr4, r2\n-\tcmp\tr9, r4\n+\tcmp\tlr, r4\n \tit\tgt\n \taddgt\tr4, ip\n \tadd\tr6, r4\n-\tcmp\tr9, r6\n+\tcmp\tlr, r6\n \tit\tgt\n \taddgt\tr6, ip\n \tcmp\tr7, #0\n-\tble.w\t1bce <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bce>\n+\tble.w\t1edc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1edc>\n+\tadd.w\tr1, r1, #536870912\t@ 0x20000000\n+\tadd.w\tr6, r6, #536870912\t@ 0x20000000\n+\tsubs\tr1, #1\n+\tsubs\tr6, #1\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tsubs\tr3, #1\n+\tsubs\tr2, #1\n+\tlsls\tr7, r1, #3\n \tadd.w\tr5, r5, #536870912\t@ 0x20000000\n+\tlsls\tr1, r6, #3\n \tadd.w\tr4, r4, #536870912\t@ 0x20000000\n+\tldr\tr6, [sp, #596]\t@ 0x254\n+\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tlsls\tr3, r3, #3\n+\tlsls\tr2, r2, #3\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tstr\tr2, [sp, #32]\n \tsubs\tr5, #1\n \tsubs\tr4, #1\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tadd.w\tr1, r1, #536870912\t@ 0x20000000\n-\tlsls\tr7, r5, #3\n-\tldr\tr5, [sp, #388]\t@ 0x184\n-\tlsls\tr4, r4, #3\n-\tstr\tr4, [sp, #16]\n-\tadd.w\tr4, r5, r8\n-\tldr\tr5, [sp, #64]\t@ 0x40\n-\tadd.w\tlr, r6, #536870912\t@ 0x20000000\n \tsubs\tr0, #1\n-\tsubs\tr1, #1\n-\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n-\tadd.w\tr5, r5, r4, lsl #3\n-\tsubs\tr2, #1\n-\tadd.w\tr4, fp, r7\n-\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n-\tstr\tr4, [sp, #56]\t@ 0x38\n+\tadd\tr6, sl\n+\tadd.w\tr8, fp, r3\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #32]\n+\tlsls\tr5, r5, #3\n+\tlsls\tr4, r4, #3\n \tlsls\tr0, r0, #3\n-\tldr\tr4, [sp, #16]\n-\tlsls\tr1, r1, #3\n-\tstr\tr1, [sp, #24]\n-\tlsls\tr6, r2, #3\n-\tmov.w\tr1, lr, lsl #3\n-\tadd.w\tr2, r8, #536870912\t@ 0x20000000\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tadd.w\tr1, sl, r7\n-\tadd.w\tr7, sl, r4\n-\tadd\tr4, fp\n-\tstr\tr4, [sp, #16]\n-\tadd.w\tr4, sl, r0\n-\tstr\tr4, [sp, #20]\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tldr\tr4, [sp, #24]\n+\tadd.w\tr2, sl, #536870912\t@ 0x20000000\n+\tadd.w\tr1, r1, r6, lsl #3\n \tsubs\tr2, #1\n-\tstr.w\tr8, [sp, #84]\t@ 0x54\n-\tsubs\tr3, #1\n-\tstr\tr1, [sp, #12]\n-\tadd.w\tr1, sl, r4\n-\tstr\tr1, [sp, #24]\n+\tstr\tr1, [sp, #72]\t@ 0x48\n+\tadd.w\tr1, fp, r5\n+\tstr\tr1, [sp, #20]\n \tadd.w\tr1, fp, r4\n-\tstr\tr1, [sp, #36]\t@ 0x24\n-\tadd.w\tr1, sl, r6\n+\tstr\tr1, [sp, #24]\n+\tadd.w\tr1, fp, r0\n+\tstr\tr1, [sp, #28]\n+\tadd.w\tr1, fp, r7\n+\tstr\tr1, [sp, #128]\t@ 0x80\n+\tadd.w\tr1, fp, r3\n \tstr\tr1, [sp, #32]\n-\tadd.w\tr1, fp, r6\n-\tstr\tr1, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tadd\tr3, r9\n \tlsls\tr2, r2, #3\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tmov\tr8, r9\n-\tldr\tr4, [sp, #56]\t@ 0x38\n-\tlsls\tr3, r3, #3\n-\tldr.w\tr9, [sp, #84]\t@ 0x54\n-\tadd.w\tr6, sl, r1\n-\tstr\tr5, [sp, #60]\t@ 0x3c\n-\tadd\tr0, fp\n-\tadd.w\tr5, sl, r2\n-\tadd\tr1, fp\n-\tadd\tr2, fp\n-\tadd.w\tlr, sl, r3\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #12]\n-\tvldr\td21, [r5]\n-\tvldr\td23, [lr]\n-\tvldr\td25, [r4]\n-\tvldr\td27, [r3]\n-\tldr\tr3, [sp, #16]\n-\tvsub.f64\td22, d21, d23\n-\tvldr\td26, [r2]\n-\tvadd.f64\td23, d23, d21\n-\tvldr\td28, [r7]\n-\tvldr\td20, [r3]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tvsub.f64\td29, d27, d28\n-\tvadd.f64\td28, d28, d27\n-\tvsub.f64\td30, d25, d20\n-\tvadd.f64\td20, d20, d25\n-\tvldr\td19, [r3]\n-\tvsub.f64\td21, d26, d19\n-\tvadd.f64\td19, d19, d26\n-\tvmov.f64\td26, d22\n-\tvfma.f64\td22, d17, d30\n-\tvfma.f64\td26, d30, d24\n-\tvadd.f64\td27, d20, d19\n-\tvsub.f64\td19, d19, d20\n-\tvmov.f64\td25, d21\n-\tvfma.f64\td21, d29, d24\n-\tvfma.f64\td25, d17, d29\n-\tvadd.f64\td29, d28, d23\n-\tvsub.f64\td23, d23, d28\n-\tvstmia\tr2!, {d27}\n-\tvstmia\tr3!, {d19}\n \tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #12]\n-\tvstmia\tr5!, {d29}\n-\tvstmia\tlr!, {d23}\n-\tvstmia\tr4!, {d25}\n-\tvstmia\tr3!, {d26}\n-\tstr\tr3, [sp, #12]\n+\tadd.w\tr3, fp, r1\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tmov\tr3, r9\n+\tadd.w\tr6, fp, r2\n+\tadd\tr5, r9\n+\tadd\tr2, r9\n+\tadd\tr4, r9\n+\tadd\tr0, r9\n+\tadd\tr7, r9\n+\tadd\tr1, r9\n+\tmov\tr9, sl\n+\tmov\tsl, fp\n+\tmov\tfp, r3\n \tldr\tr3, [sp, #20]\n-\tvstmia\tr7!, {d22}\n-\tvldr\td22, [r3]\n-\tldr\tr3, [sp, #16]\n-\tvstmia\tr3!, {d21}\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #24]\n-\tvldr\td20, [r0]\n-\tvldr\td26, [r3]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tvsub.f64\td23, d22, d26\n-\tvadd.f64\td26, d26, d22\n-\tvldr\td19, [r3]\n-\tldr\tr3, [sp, #32]\n-\tvsub.f64\td21, d20, d19\n-\tvadd.f64\td19, d19, d20\n-\tvldr\td27, [r3]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tvldr\td28, [r6]\n-\tvldr\td31, [r1]\n-\tvsub.f64\td22, d21, d27\n+\tvldr\td1, [r4]\n+\tvldr\td8, [r8]\n+\tvldr\td9, [r2]\n \tvldr\td7, [r3]\n-\tvadd.f64\td30, d28, d27\n+\tldr\tr3, [sp, #24]\n+\tvldr\td4, [r5]\n+\tvldr\td5, [r6]\n+\tvldr\td0, [r3]\n+\tvsub.f64\td6, d4, d1\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tvadd.f64\td2, d8, d5\n+\tvadd.f64\td4, d1, d4\n+\tvsub.f64\td5, d5, d8\n+\tvsub.f64\td3, d7, d0\n+\tvadd.f64\td7, d0, d7\n+\tvmul.f64\td6, d6, d15\n+\tvldr\td10, [r3]\n+\tvadd.f64\td8, d7, d2\n+\tvsub.f64\td7, d2, d7\n+\tvadd.f64\td1, d10, d9\n+\tvsub.f64\td0, d9, d10\n+\tvmul.f64\td3, d3, d15\n+\tvstmia\tr6!, {d8}\n+\tvadd.f64\td2, d4, d1\n+\tvsub.f64\td1, d1, d4\n+\tvsub.f64\td4, d5, d6\n+\tvstmia\tr8!, {d7}\n+\tvadd.f64\td6, d6, d5\n+\tvadd.f64\td5, d0, d3\n+\tvsub.f64\td0, d0, d3\n+\tvstmia\tr2!, {d2}\n+\tvstmia\tr3!, {d1}\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tldr\tr3, [sp, #20]\n-\tvsub.f64\td25, d23, d31\n-\tvsub.f64\td21, d21, d28\n-\tvadd.f64\td22, d22, d28\n-\tvadd.f64\td20, d31, d7\n-\tvsub.f64\td23, d23, d7\n-\tvadd.f64\td29, d19, d30\n-\tvsub.f64\td19, d19, d30\n-\tvadd.f64\td25, d25, d7\n-\tvadd.f64\td21, d21, d27\n-\tvsub.f64\td30, d26, d20\n-\tvadd.f64\td20, d20, d26\n-\tvadd.f64\td23, d23, d31\n-\tvstmia\tr0!, {d29}\n-\tvstmia\tr1!, {d19}\n-\tvstmia\tr3!, {d30}\n+\tvstmia\tr5!, {d5}\n+\tvstmia\tr4!, {d0}\n+\tvldr\td8, [r0]\n+\tvstmia\tr3!, {d4}\n \tstr\tr3, [sp, #20]\n \tldr\tr3, [sp, #24]\n-\tvstmia\tr6!, {d20}\n-\tvstmia\tr3!, {d25}\n+\tvstmia\tr3!, {d6}\n \tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #28]\n+\tvldr\td6, [r7]\n+\tvldr\td2, [r3]\n+\tvsub.f64\td0, d8, d6\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvadd.f64\td6, d6, d8\n+\tvldr\td7, [r3]\n \tldr\tr3, [sp, #32]\n-\tvstmia\tr3!, {d23}\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tvstmia\tr3!, {d22}\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tvsub.f64\td5, d2, d7\n+\tvadd.f64\td7, d7, d2\n+\tvldr\td11, [r3]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvldr\td4, [r1]\n+\tvsub.f64\td9, d0, d11\n+\tvldr\td10, [r3]\n+\tvsub.f64\td8, d5, d4\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvadd.f64\td1, d10, d11\n+\tvsub.f64\td0, d0, d10\n+\tvadd.f64\td9, d9, d10\n+\tvldr\td3, [r3]\n+\tldr\tr3, [sp, #28]\n+\tvadd.f64\td13, d6, d1\n+\tvsub.f64\td6, d6, d1\n+\tvadd.f64\td2, d4, d3\n+\tvsub.f64\td5, d5, d3\n+\tvadd.f64\td3, d8, d3\n+\tvadd.f64\td0, d0, d11\n+\tvstmia\tr0!, {d13}\n+\tvsub.f64\td1, d7, d2\n+\tvadd.f64\td7, d2, d7\n+\tvadd.f64\td5, d5, d4\n+\tvstmia\tr1!, {d6}\n+\tvstmia\tr7!, {d9}\n+\tvstmia\tr3!, {d1}\n+\tstr\tr3, [sp, #28]\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tvstmia\tr3!, {d21}\n+\tvstmia\tr3!, {d7}\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr5, r3\n-\tbne.w\t1a82 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1a82>\n-\tmov\tr3, r9\n-\tmov\tr9, r8\n-\tmov\tr8, r3\n-\tldr\tr3, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvstmia\tr3!, {d3}\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #32]\n+\tvstmia\tr3!, {d5}\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstmia\tr3!, {d0}\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tcmp\tr6, r3\n+\tbne.w\t1d8e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d8e>\n+\tmov\tr3, fp\n+\tmov\tfp, sl\n+\tmov\tsl, r9\n+\tmov\tr9, r3\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n \tldr\tr2, [sp, #8]\n-\tadd\tr8, r3\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tcmp\tr9, r8\n+\tadd\tsl, r3\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tlr, sl\n \tadd.w\tr3, r3, #1\n \tit\tgt\n-\taddgt\tr8, ip\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\taddgt\tsl, ip\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tcmp\tr3, r2\n-\tbne.w\t1980 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1980>\n-\tldrd\tr0, r3, [sp, #68]\t@ 0x44\n-\tldrd\tr1, r2, [sp, #76]\t@ 0x4c\n+\tbne.w\t1ca2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ca2>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr7, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #104]\t@ 0x68\n \tsubs\tr3, #1\n-\tadds\tr7, r3, #1\n-\tadd\tr2, r1\n-\tbne.w\t196e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x196e>\n-\tmov\tr8, fp\n-\tldr\tr3, [sp, #384]\t@ 0x180\n+\tldr.w\tr8, [sp, #80]\t@ 0x50\n+\tadds\tr5, r3, #1\n+\tadd\tr2, r7\n+\tbne.w\t1c8a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c8a>\n+\tmov\tsl, fp\n+\tldr\tr3, [sp, #592]\t@ 0x250\n \tcmp\tr3, #3\n-\tbeq.w\t1fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa>\n+\tbne.n\t1f48 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f48>\n \tldr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr4, [sp, #136]\t@ 0x88\n-\tmov.w\tfp, r3, lsl #1\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tldr\tr1, [sp, #584]\t@ 0x248\n+\tmla\tr3, r1, r2, r3\n+\tldr\tr2, [sp, #456]\t@ 0x1c8\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr3, [sp, #436]\t@ 0x1b4\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #436]\t@ 0x1b4\n+\tcmp\tr3, r2\n+\tbeq.w\t2fd0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fd0>\n+\tldr\tr3, [sp, #424]\t@ 0x1a8\n+\tstr\tr3, [sp, #596]\t@ 0x254\n+\tb.w\t110 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x110>\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tble.w\t199a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x199a>\n+\tb.n\t1c36 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c36>\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tldr\tr4, [sp, #332]\t@ 0x14c\n+\tlsls\tr3, r3, #1\n \tcmp\tr4, #0\n-\tblt.w\t2d44 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d44>\n-\tsubs\tr3, r0, r4\n-\tcmp\tr4, r0\n-\tudiv\tip, r3, r4\n-\tbgt.w\t200e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x200e>\n-\tldr\tr6, [sp, #136]\t@ 0x88\n-\tvneg.f64\td10, d17\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tsub.w\tr3, sl, #8\n-\tstr.w\tr8, [sp, #12]\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n+\tblt.w\t2fda <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fda>\n+\tmov\tr1, r4\n+\tsub.w\tr0, r8, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r8\n+\tstr\tr0, [sp, #136]\t@ 0x88\n+\tbgt.w\t23c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23c8>\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr8, r3\n+\tldr\tr6, [sp, #184]\t@ 0xb8\n+\tsub.w\tfp, r3, r2\n+\tsubs\tr4, r2, r3\n+\tmov\tr2, r3\n+\tldr\tr3, [sp, #596]\t@ 0x254\n+\tstr.w\tr9, [sp, #20]\n \tmov\tr9, sl\n-\tldr.w\tr8, [sp, #120]\t@ 0x78\n-\tsub.w\tlr, r6, r2\n-\tsubs\tr4, r2, r6\n-\tmov\tr0, fp\n-\tmov\tr7, r6\n \tmov\tsl, r2\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n-\tlsls\tr2, r0, #3\n-\tcmp\tr1, #0\n-\tadd\tr3, r2\n-\tvldr\td0, [r3, #8]\n-\tvldr\td9, [r3]\n-\tadd\tr3, r2\n-\tvmul.f64\td0, d8, d0\n-\tvldr\td2, [r3, #8]\n-\tvldr\td1, [r3]\n-\tadd\tr3, r2\n-\tvmul.f64\td2, d8, d2\n-\tvldr\td23, [r3, #8]\n-\tvldr\td3, [r3]\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr3, [sp, #376]\t@ 0x178\n+\tlsls\tr2, r6, #3\n+\tvldr\td6, [sp, #360]\t@ 0x168\n+\tcmp\tr7, #0\n \tadd\tr3, r2\n-\tvmul.f64\td23, d8, d23\n-\tvldr\td24, [r3, #8]\n-\tvldr\td28, [r3]\n+\tvldr\td13, [r3, #8]\n+\tvldr\td11, [r3]\n \tadd\tr3, r2\n-\tvmul.f64\td24, d8, d24\n-\tvldr\td25, [r3, #8]\n-\tvldr\td29, [r3]\n+\tvmul.f64\td13, d6, d13\n+\tvldr\td7, [r3, #8]\n+\tvldr\td5, [r3]\n \tadd\tr3, r2\n+\tadd.w\tr0, r3, r2\n+\tvmul.f64\td7, d6, d7\n+\tadd.w\tr1, r0, r2\n+\tvstr\td5, [sp, #40]\t@ 0x28\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvldr\td7, [r3]\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tvldr\td7, [r3, #8]\n+\tadd.w\tr3, r1, r2\n \tadd\tr2, r3\n-\tvmul.f64\td25, d8, d25\n-\tvldr\td26, [r3, #8]\n-\tvldr\td27, [r2, #8]\n-\tvldr\td30, [r3]\n-\tvmul.f64\td26, d8, d26\n-\tvldr\td31, [r2]\n-\tvmul.f64\td27, d8, d27\n-\tblt.w\t236c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x236c>\n-\tudiv\tr3, r4, r1\n-\tcmp\tsl, r7\n-\tblt.w\t1ff4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ff4>\n-\tcmp.w\tr8, #0\n-\tble.w\t1ff4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ff4>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\tadd.w\tr5, r8, #1\n-\tstr\tr5, [sp, #40]\t@ 0x28\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td14, [r2, #8]\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvmul.f64\td14, d6, d14\n+\tvldr\td7, [r0, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvldr\td7, [r0]\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvldr\td7, [r1, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [r1]\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvldr\td7, [r3, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td7, [r3]\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvldr\td7, [r2]\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tblt.w\t2732 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2732>\n+\tmov\tr1, r7\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t23aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23aa>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tcmp\tr2, #0\n+\tble.w\t23aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23aa>\n+\tldr\tr2, [sp, #584]\t@ 0x248\n+\tldr\tr1, [sp, #320]\t@ 0x140\n \tcmp\tr2, #1\n-\tldr\tr2, [sp, #28]\n-\tadd\tr2, r7\n-\tbne.w\t2022 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2022>\n-\tstr.w\tr9, [sp, #32]\n-\tmovs\tr5, #1\n-\tstr\tr2, [sp, #24]\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tstr.w\tr8, [sp, #56]\t@ 0x38\n-\tstrd\tr6, r3, [sp, #64]\t@ 0x40\n-\tstrd\tip, fp, [sp, #72]\t@ 0x48\n-\tstrd\tr0, r7, [sp, #80]\t@ 0x50\n-\tstr.w\tsl, [sp, #88]\t@ 0x58\n-\tstrd\tr1, r2, [sp, #96]\t@ 0x60\n-\tstrd\tlr, r4, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #24]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tadd.w\tr1, r1, #1\n+\tit\teq\n+\tstreq.w\tr9, [sp, #132]\t@ 0x84\n+\tadd\tr2, r8\n+\tstr\tr1, [sp, #148]\t@ 0x94\n+\tbne.w\t23d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23d0>\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr1, [sp, #152]\t@ 0x98\n+\tstr.w\tsl, [sp, #176]\t@ 0xb0\n+\tstrd\tr3, r6, [sp, #188]\t@ 0xbc\n+\tstr.w\tr8, [sp, #196]\t@ 0xc4\n+\tstr\tr7, [sp, #216]\t@ 0xd8\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tstr.w\tfp, [sp, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #220]\t@ 0xdc\n+\tldr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n \tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r0\n-\tble.n\t1d08 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d08>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #4]\n+\tldr\tr6, [sp, #140]\t@ 0x8c\n+\tldr\tr7, [sp, #140]\t@ 0x8c\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #0]\n \tadds\tr5, r3, r0\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r5\n-\tble.n\t1d16 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d16>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr5, r5, r3\n+\tldr\tr3, [sp, #0]\n \tadds\tr1, r3, r5\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tcmp\tr3, r1\n-\tble.n\t1d24 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d24>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #0]\n \tadd\tr3, r1\n \tcmp\tr2, r3\n-\tble.n\t1d32 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d32>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #4]\n-\tldr\tr4, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #0]\n \tadd\tr2, r3\n \tcmp\tr4, r2\n-\tble.n\t1d40 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d40>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r4\n-\tldr\tr4, [sp, #4]\n-\tldr\tr6, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr4, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r4\n+\tldr\tr4, [sp, #0]\n \tadd\tr4, r2\n \tcmp\tr6, r4\n-\tble.n\t1d4e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d4e>\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r6\n-\tldr\tr6, [sp, #4]\n-\tldr\tr7, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr6, [sp, #280]\t@ 0x118\n+\taddgt\tr4, r4, r6\n+\tldr\tr6, [sp, #0]\n \tadd\tr6, r4\n \tcmp\tr7, r6\n-\tble.n\t1d5c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1d5c>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\titt\tgt\n+\tldrgt\tr7, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tcmp\tr7, #0\n-\tble.w\t1fa8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa8>\n+\tble.w\t2364 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2364>\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n \tadd.w\tr6, r6, #536870912\t@ 0x20000000\n \tsubs\tr1, #1\n \tsubs\tr6, #1\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n-\tldr\tr7, [sp, #24]\n+\tldr\tr7, [sp, #128]\t@ 0x80\n \tmov.w\tip, r1, lsl #3\n \tsubs\tr2, #1\n \tlsls\tr1, r6, #3\n-\tldr\tr6, [sp, #388]\t@ 0x184\n+\tldr\tr6, [sp, #596]\t@ 0x254\n \tlsls\tr2, r2, #3\n \tstr\tr2, [sp, #8]\n \tadd\tr6, r7\n \tadd.w\tr2, r7, #536870912\t@ 0x20000000\n-\tldr\tr7, [sp, #60]\t@ 0x3c\n+\tldr\tr7, [sp, #344]\t@ 0x158\n \tsubs\tr2, #1\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n \tadd.w\tr5, r5, #536870912\t@ 0x20000000\n \tadd.w\tr4, r4, #536870912\t@ 0x20000000\n \tadd.w\tr0, r0, #536870912\t@ 0x20000000\n \tadd.w\tr7, r7, r6, lsl #3\n-\tldr\tr6, [sp, #32]\n+\tldr\tr6, [sp, #132]\t@ 0x84\n \tlsls\tr2, r2, #3\n \tsubs\tr3, #1\n \tsubs\tr5, #1\n \tsubs\tr4, #1\n \tsubs\tr0, #1\n-\tstr\tr7, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #144]\t@ 0x90\n \tadds\tr7, r6, r2\n-\tstr\tr7, [sp, #20]\n-\tldr\tr7, [sp, #12]\n+\tstr\tr7, [sp, #28]\n+\tldr\tr7, [sp, #20]\n \tlsls\tr4, r4, #3\n \tlsls\tr0, r0, #3\n \tlsls\tr3, r3, #3\n \tlsls\tr5, r5, #3\n \tadd.w\tfp, r6, r3\n \tadd.w\tsl, r6, r5\n \tadd.w\tr9, r6, r4\n \tadds\tr5, r7, r5\n \tadd.w\tr8, r6, r0\n \tadd.w\tlr, r6, ip\n-\tstr\tr5, [sp, #48]\t@ 0x30\n+\tstr\tr5, [sp, #32]\n \tadds\tr5, r7, r4\n \tadds\tr4, r7, r0\n \tmov\tr0, r6\n \tldr\tr6, [sp, #8]\n \tadd\tr3, r7\n \tadd\tr2, r7\n \tadd\tr0, r6\n \tadd\tip, r7\n \tstr\tr0, [sp, #8]\n \tadds\tr0, r7, r6\n-\tldr\tr7, [sp, #32]\n+\tldr\tr7, [sp, #132]\t@ 0x84\n+\tvstr\td12, [sp, #224]\t@ 0xe0\n \tadds\tr6, r7, r1\n-\tldr\tr7, [sp, #12]\n-\tstr\tr6, [sp, #16]\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tadd\tr1, r7\n \tldr\tr7, [sp, #20]\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #20]\n-\tvldr\td14, [r9]\n-\tvldr\td15, [sl]\n-\tvldr\td11, [r2]\n+\tstr\tr6, [sp, #24]\n+\tldr\tr6, [sp, #32]\n+\tadd\tr1, r7\n+\tldr\tr7, [sp, #28]\n+\tstr\tr3, [sp, #28]\n+\tvldr\td1, [sl]\n+\tvldr\td5, [r9]\n+\tldr\tr3, [sp, #28]\n+\tvldr\td2, [r2]\n+\tvsub.f64\td4, d1, d5\n+\tvldr\td3, [r6]\n+\tvldr\td6, [r5]\n+\tvadd.f64\td5, d5, d1\n \tvldr\td7, [r3]\n-\tvsub.f64\td6, d15, d14\n-\tvldr\td13, [r7]\n-\tvldr\td12, [fp]\n-\tvadd.f64\td15, d14, d15\n-\tvsub.f64\td5, d11, d7\n-\tvldr\td19, [r5]\n-\tvldr\td20, [r6]\n-\tvadd.f64\td21, d7, d11\n-\tvsub.f64\td11, d7, d11\n-\tvadd.f64\td7, d12, d13\n-\tvfma.f64\td11, d17, d6\n-\tvmov.f64\td4, d5\n-\tvfma.f64\td5, d6, d10\n-\tvadd.f64\td22, d19, d20\n-\tvsub.f64\td20, d20, d19\n-\tvsub.f64\td19, d13, d12\n-\tvfma.f64\td4, d17, d6\n-\tvmul.f64\td11, d26, d11\n-\tvmul.f64\td12, d30, d5\n-\tvmov.f64\td5, d19\n-\tvfma.f64\td5, d20, d10\n-\tvfma.f64\td19, d17, d20\n-\tvnmul.f64\td13, d4, d2\n-\tvmul.f64\td14, d1, d4\n-\tvsub.f64\td20, d22, d21\n-\tvadd.f64\td4, d22, d21\n-\tvmul.f64\td20, d20, d24\n-\tvstmia\tr2!, {d4}\n-\tvfma.f64\td13, d1, d5\n-\tvfma.f64\td14, d2, d5\n-\tvsub.f64\td5, d21, d22\n-\tvfma.f64\td11, d30, d19\n-\tvfma.f64\td12, d26, d19\n-\tvsub.f64\td19, d7, d15\n-\tvadd.f64\td7, d15, d7\n-\tvmul.f64\td21, d5, d28\n-\tvfma.f64\td21, d24, d19\n-\tvfma.f64\td20, d28, d19\n-\tvstmia\tr7!, {d7}\n-\tvstmia\tr3!, {d21}\n-\tstr\tr3, [sp, #20]\n+\tvldr\td8, [r7]\n+\tvmul.f64\td4, d4, d15\n+\tvsub.f64\td0, d3, d6\n+\tvsub.f64\td1, d2, d7\n+\tvadd.f64\td6, d6, d3\n+\tvadd.f64\td3, d7, d2\n+\tvsub.f64\td7, d7, d2\n+\tvldr\td10, [fp]\n+\tvmul.f64\td0, d0, d15\n+\tvadd.f64\td2, d10, d8\n+\tvadd.f64\td9, d7, d4\n+\tvsub.f64\td7, d8, d10\n+\tvadd.f64\td8, d1, d4\n+\tvsub.f64\td10, d1, d4\n+\tvsub.f64\td4, d6, d3\n+\tvsub.f64\td1, d3, d6\n+\tvadd.f64\td6, d6, d3\n+\tvstmia\tr2!, {d6}\n+\tvsub.f64\td6, d2, d5\n+\tvadd.f64\td5, d5, d2\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvmul.f64\td3, d2, d8\n+\tvstmia\tr7!, {d5}\n+\tvadd.f64\td5, d0, d7\n+\tvsub.f64\td7, d7, d0\n+\tvldr\td0, [sp, #40]\t@ 0x28\n+\tvnmls.f64\td3, d0, d7\n+\tvmul.f64\td7, d2, d7\n+\tvmla.f64\td7, d0, d8\n+\tvldr\td0, [sp, #72]\t@ 0x48\n+\tvldr\td8, [sp, #80]\t@ 0x50\n+\tvmul.f64\td2, d0, d6\n+\tvmul.f64\td6, d8, d6\n+\tvmla.f64\td2, d4, d8\n+\tvmla.f64\td6, d1, d0\n+\tvldr\td4, [sp, #112]\t@ 0x70\n+\tvstmia\tfp!, {d2}\n+\tvstmia\tr3!, {d6}\n+\tvldr\td6, [sp, #104]\t@ 0x68\n+\tvstmia\tr6!, {d7}\n+\tstr\tr3, [sp, #28]\n+\tvmul.f64\td7, d6, d5\n+\tvmul.f64\td5, d4, d5\n+\tvmla.f64\td7, d9, d4\n+\tvmla.f64\td5, d10, d6\n \tldr\tr3, [sp, #8]\n-\tvstmia\tfp!, {d20}\n-\tvstmia\tr6!, {d14}\n-\tvstmia\tsl!, {d13}\n-\tvstmia\tr5!, {d12}\n-\tvstmia\tr9!, {d11}\n-\tvldr\td12, [r3]\n-\tldr\tr3, [sp, #16]\n-\tvldr\td11, [ip]\n-\tvldr\td20, [r8]\n-\tvldr\td19, [lr]\n-\tvldr\td13, [r3]\n-\tvldr\td4, [r4]\n-\tvsub.f64\td5, d20, d19\n-\tvldr\td14, [r0]\n-\tvsub.f64\td6, d12, d13\n-\tvldr\td15, [r1]\n-\tvadd.f64\td7, d11, d4\n-\tvsub.f64\td21, d4, d11\n-\tvadd.f64\td22, d13, d12\n-\tvadd.f64\td19, d19, d20\n-\tvsub.f64\td4, d6, d4\n-\tvsub.f64\td12, d21, d12\n-\tvadd.f64\td21, d21, d6\n-\tvsub.f64\td6, d22, d7\n-\tvadd.f64\td4, d4, d11\n-\tvsub.f64\td11, d5, d14\n-\tvsub.f64\td5, d5, d15\n-\tvadd.f64\td12, d12, d13\n-\tvmul.f64\td13, d29, d21\n-\tvmul.f64\td6, d6, d27\n-\tvmul.f64\td4, d4, d23\n-\tvadd.f64\td5, d5, d14\n-\tvadd.f64\td14, d15, d14\n-\tvadd.f64\td15, d11, d15\n-\tvnmul.f64\td11, d21, d25\n-\tvadd.f64\td21, d7, d22\n-\tvsub.f64\td7, d7, d22\n-\tvmul.f64\td12, d12, d3\n-\tvadd.f64\td22, d14, d19\n-\tvsub.f64\td19, d19, d14\n-\tvfma.f64\td4, d3, d5\n-\tvfma.f64\td11, d29, d15\n-\tvnmul.f64\td20, d21, d0\n-\tvmul.f64\td7, d7, d31\n-\tvmul.f64\td21, d9, d21\n-\tvfma.f64\td12, d23, d5\n-\tvfma.f64\td20, d9, d19\n-\tvfma.f64\td21, d0, d19\n-\tvfma.f64\td6, d31, d22\n-\tvfma.f64\td7, d27, d22\n-\tvfma.f64\td13, d25, d15\n-\tvstmia\tr8!, {d20}\n-\tvstmia\tr4!, {d21}\n+\tvstmia\tsl!, {d3}\n+\tvstmia\tr9!, {d7}\n+\tvldr\td8, [r3]\n+\tldr\tr3, [sp, #24]\n+\tvldr\td3, [lr]\n+\tvstmia\tr5!, {d5}\n+\tvldr\td5, [r8]\n+\tvldr\td9, [r3]\n+\tvldr\td0, [ip]\n+\tvldr\td7, [r4]\n+\tvsub.f64\td6, d5, d3\n+\tvsub.f64\td4, d8, d9\n+\tvadd.f64\td3, d3, d5\n+\tvldr\td10, [r0]\n+\tvadd.f64\td2, d9, d8\n+\tvsub.f64\td5, d7, d0\n+\tvadd.f64\td1, d0, d7\n+\tvldr\td12, [sp, #88]\t@ 0x58\n+\tvsub.f64\td7, d4, d7\n+\tvadd.f64\td4, d5, d4\n+\tvsub.f64\td5, d5, d8\n+\tvadd.f64\td7, d7, d0\n+\tvadd.f64\td0, d1, d2\n+\tvadd.f64\td9, d5, d9\n+\tvldr\td5, [r1]\n+\tvstr\td7, [sp, #32]\n+\tvsub.f64\td8, d6, d5\n+\tvadd.f64\td7, d5, d10\n+\tvsub.f64\td6, d6, d10\n+\tvadd.f64\td8, d8, d10\n+\tvsub.f64\td10, d2, d1\n+\tvsub.f64\td2, d1, d2\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvadd.f64\td6, d6, d5\n+\tvsub.f64\td5, d3, d7\n+\tvadd.f64\td7, d7, d3\n+\tvmul.f64\td3, d1, d4\n+\tvmul.f64\td1, d1, d6\n+\tvmla.f64\td1, d12, d4\n+\tvldr\td4, [sp, #32]\n+\tvnmls.f64\td3, d12, d6\n+\tvmul.f64\td6, d13, d0\n+\tvnmls.f64\td6, d11, d5\n+\tvmul.f64\td5, d13, d5\n+\tvmla.f64\td5, d11, d0\n+\tvstmia\tr8!, {d6}\n+\tvstmia\tr4!, {d5}\n+\tvldr\td5, [sp, #120]\t@ 0x78\n+\tvmul.f64\td6, d5, d7\n+\tvmul.f64\td7, d14, d7\n+\tvmla.f64\td6, d10, d14\n+\tvmla.f64\td7, d2, d5\n+\tvldr\td5, [sp, #64]\t@ 0x40\n \tvstmia\tr3!, {d6}\n-\tstr\tr3, [sp, #16]\n+\tvldr\td6, [sp, #56]\t@ 0x38\n \tvstmia\tr1!, {d7}\n+\tstr\tr3, [sp, #24]\n+\tvmul.f64\td7, d6, d8\n+\tvmul.f64\td8, d5, d8\n+\tvmla.f64\td7, d4, d5\n+\tvmla.f64\td8, d9, d6\n \tldr\tr3, [sp, #8]\n-\tvstmia\tlr!, {d4}\n-\tvstmia\tip!, {d12}\n-\tvstmia\tr0!, {d13}\n-\tvstmia\tr3!, {d11}\n+\tvstmia\tlr!, {d7}\n+\tvstmia\tr3!, {d3}\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvstmia\tip!, {d8}\n \tcmp\tr7, r3\n-\tbne.w\t1dfa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1dfa>\n-\tldr\tr3, [sp, #24]\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tvstmia\tr0!, {d1}\n+\tbne.w\t217e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x217e>\n+\tvldr\td12, [sp, #224]\t@ 0xe0\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n-\tstr\tr3, [sp, #24]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tcmp\tr2, r3\n-\tble.n\t1fbc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fbc>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #40]\t@ 0x28\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #148]\t@ 0x94\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r2\n-\tbne.w\t1cf8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1cf8>\n-\tldrd\tr6, r3, [sp, #64]\t@ 0x40\n-\tldrd\tr1, r2, [sp, #96]\t@ 0x60\n+\tbne.w\t2078 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2078>\n+\tldrd\tr3, r6, [sp, #188]\t@ 0xbc\n+\tldr\tr7, [sp, #216]\t@ 0xd8\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n \tsubs\tr3, #1\n-\tldr.w\tr8, [sp, #56]\t@ 0x38\n-\tadds\tr5, r3, #1\n-\tldrd\tip, fp, [sp, #72]\t@ 0x48\n-\tadd\tr2, r1\n-\tldrd\tr0, r7, [sp, #80]\t@ 0x50\n-\tldr.w\tsl, [sp, #88]\t@ 0x58\n-\tldrd\tlr, r4, [sp, #104]\t@ 0x68\n-\tbne.w\t1cd6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1cd6>\n-\tldr.w\tr9, [sp, #32]\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd\tr0, fp\n-\tadd\tr7, r6\n-\tadd\tlr, r6\n-\tsubs\tr4, r4, r6\n-\tcmp.w\tip, #4294967295\t@ 0xffffffff\n-\tbne.w\t1c42 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c42>\n-\tldr.w\tr8, [sp, #12]\n+\tldr.w\tsl, [sp, #176]\t@ 0xb0\n+\tadds\tr0, r3, #1\n+\tldr.w\tr8, [sp, #196]\t@ 0xc4\n+\tadd\tr2, r7\n+\tldr.w\tfp, [sp, #208]\t@ 0xd0\n+\tldr\tr4, [sp, #220]\t@ 0xdc\n+\tbne.w\t205c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x205c>\n+\tldr.w\tr9, [sp, #132]\t@ 0x84\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tadd\tr8, sl\n+\tldr\tr2, [sp, #184]\t@ 0xb8\n+\tadd\tfp, sl\n+\tsubs\tr3, #1\n+\tsub.w\tr4, r4, sl\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tadd\tr6, r2\n+\tadds\tr3, #1\n+\tbne.w\t1f86 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f86>\n \tmov\tsl, r9\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tb.w\t81a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x81a>\n-\tudiv\tr0, r4, lr\n-\tcmp\tr9, r2\n-\tble.w\t168a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x168a>\n-\tb.n\t1918 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1918>\n-\tldr\tr5, [sp, #388]\t@ 0x184\n-\tstr.w\tr8, [sp, #64]\t@ 0x40\n+\tldr.w\tr9, [sp, #20]\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr3, [sp, #336]\t@ 0x150\n+\tb.w\t378 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x378>\n+\tstr.w\tr8, [sp, #176]\t@ 0xb0\n \tmov\tr8, r9\n-\tldr.w\tr9, [sp, #156]\t@ 0x9c\n-\tadds\tr5, #1\n-\tstr\tr5, [sp, #56]\t@ 0x38\n-\tldr\tr5, [sp, #152]\t@ 0x98\n+\tldr.w\tr9, [sp, #356]\t@ 0x164\n+\tldr\tr1, [sp, #352]\t@ 0x160\n \tstr\tr2, [sp, #8]\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tstrd\tr6, r3, [sp, #68]\t@ 0x44\n-\tstrd\tip, fp, [sp, #76]\t@ 0x4c\n-\tstrd\tr0, r7, [sp, #84]\t@ 0x54\n-\tstrd\tsl, r1, [sp, #96]\t@ 0x60\n-\tstrd\tr2, lr, [sp, #104]\t@ 0x68\n-\tstr\tr4, [sp, #116]\t@ 0x74\n-\tldrd\tr3, r2, [sp, #4]\n+\tstr\tr1, [sp, #132]\t@ 0x84\n+\tstrd\tsl, r3, [sp, #188]\t@ 0xbc\n+\tstr\tr6, [sp, #196]\t@ 0xc4\n+\tstr\tr7, [sp, #216]\t@ 0xd8\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tstr.w\tfp, [sp, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #220]\t@ 0xdc\n+\tldr\tr2, [sp, #8]\n+\tldr\tr3, [sp, #0]\n+\tldr\tr6, [sp, #140]\t@ 0x8c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tldr\tr7, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r3\n-\tble.n\t205e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x205e>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #0]\n \tadds\tr1, r2, r3\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r1\n-\tble.n\t206c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x206c>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r2\n-\tldr\tr2, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr1, r1, r2\n+\tldr\tr2, [sp, #0]\n \tadds\tr5, r2, r1\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r5\n-\tble.n\t207a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x207a>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r2\n-\tldr\tr2, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr5, r5, r2\n+\tldr\tr2, [sp, #0]\n \tadds\tr0, r2, r5\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r0\n-\tble.n\t2088 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2088>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r2\n-\tldr\tr2, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr0, r0, r2\n+\tldr\tr2, [sp, #0]\n \tadds\tr4, r2, r0\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr2, r4\n-\tble.n\t2096 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2096>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r2\n-\tldr\tr2, [sp, #4]\n-\tldr\tr6, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #280]\t@ 0x118\n+\taddgt\tr4, r4, r2\n+\tldr\tr2, [sp, #0]\n \tadd\tr2, r4\n \tcmp\tr6, r2\n-\tble.n\t20a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x20a4>\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r6\n-\tldr\tr6, [sp, #4]\n-\tldr\tr7, [sp, #28]\n+\titt\tgt\n+\tldrgt\tr6, [sp, #280]\t@ 0x118\n+\taddgt\tr2, r2, r6\n+\tldr\tr6, [sp, #0]\n \tadd\tr6, r2\n \tcmp\tr7, r6\n-\tble.n\t20b2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x20b2>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\titt\tgt\n+\tldrgt\tr7, [sp, #280]\t@ 0x118\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tcmp\tr7, #0\n-\tble.w\t2322 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2322>\n+\tble.w\t26ee <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26ee>\n \tlsls\tr7, r6, #3\n \tldr\tr6, [sp, #8]\n \tlsls\tr5, r5, #3\n-\tstr\tr5, [sp, #20]\n+\tstr\tr5, [sp, #24]\n \tlsls\tr2, r2, #3\n-\tstr\tr7, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #28]\n \tlsls\tr5, r6, #3\n-\tldr\tr6, [sp, #12]\n+\tldr\tr6, [sp, #20]\n \tadd.w\tfp, r8, r5\n \tlsls\tr0, r0, #3\n \tadd\tr5, r6\n \tstr\tr5, [sp, #32]\n-\tldr\tr5, [sp, #20]\n+\tldr\tr5, [sp, #24]\n \tlsls\tr1, r1, #3\n \tlsls\tr3, r3, #3\n \tlsls\tr4, r4, #3\n \tadd.w\tip, r8, r2\n \tadd\tr2, r6\n-\tstr\tr2, [sp, #16]\n+\tstr\tr2, [sp, #144]\t@ 0x90\n \tmov\tr2, r6\n \tadd.w\tsl, r8, r0\n \tadd.w\tlr, r8, r1\n \tadd.w\tr7, r8, r3\n \tadd\tr0, r6\n \tadd\tr3, r6\n \tadd\tr1, r6\n \tadd.w\tr6, r8, r5\n \tadds\tr5, r2, r5\n-\tstr\tr5, [sp, #24]\n+\tstr\tr5, [sp, #128]\t@ 0x80\n \tadd.w\tr5, r8, r4\n-\tstr\tr5, [sp, #48]\t@ 0x30\n+\tstr\tr5, [sp, #152]\t@ 0x98\n \tadd\tr4, r2\n-\tldr\tr5, [sp, #36]\t@ 0x24\n-\tstr.w\tr8, [sp, #128]\t@ 0x80\n+\tldr\tr5, [sp, #28]\n+\tstr.w\tr8, [sp, #232]\t@ 0xe8\n \tadd.w\tr2, r8, r5\n-\tstr\tr2, [sp, #20]\n-\tldr\tr2, [sp, #12]\n+\tstr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #20]\n+\tvstr\td12, [sp, #224]\t@ 0xe0\n \tadd\tr2, r5\n-\tldr\tr5, [sp, #152]\t@ 0x98\n+\tldr\tr5, [sp, #352]\t@ 0x160\n \tmov\tr8, r2\n-\tstr\tr5, [sp, #36]\t@ 0x24\n+\tstr\tr5, [sp, #24]\n \tldr\tr5, [sp, #32]\n \tstr\tr3, [sp, #32]\n-\tvldr\td14, [lr, #-8]\n-\tvldr\td15, [ip, #-8]\n-\tvldr\td4, [r5, #-8]\n-\tvldr\td5, [r0, #-8]\n-\tvsub.f64\td21, d14, d15\n-\tldr\tr3, [sp, #16]\n-\tvldr\td20, [r1, #-8]\n-\tvadd.f64\td15, d14, d15\n-\tvsub.f64\td19, d5, d4\n-\tvldr\td11, [fp, #-8]\n-\tvldr\td13, [sl, #-8]\n-\tvsub.f64\td12, d4, d5\n-\tvfma.f64\td19, d17, d21\n-\tvldr\td6, [r3, #-8]\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tvadd.f64\td7, d11, d13\n-\tvadd.f64\td22, d20, d6\n-\tvsub.f64\td6, d20, d6\n-\tvadd.f64\td20, d4, d5\n+\tvldr\td1, [ip, #-8]\n+\tvldr\td5, [lr, #-8]\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvldr\td2, [r5, #-8]\n+\tvsub.f64\td3, d5, d1\n+\tvldr\td7, [r0, #-8]\n+\tvldr\td6, [r1, #-8]\n+\tvadd.f64\td5, d5, d1\n+\tvldr\td4, [r3, #-8]\n+\tvldr\td8, [fp, #-8]\n+\tvsub.f64\td1, d2, d7\n+\tvldr\td10, [sl, #-8]\n+\tvmul.f64\td3, d3, d15\n+\tvsub.f64\td0, d6, d4\n+\tvadd.f64\td6, d6, d4\n+\tvadd.f64\td4, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvadd.f64\td2, d8, d10\n+\tvldr\td12, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #24]\n+\tvmul.f64\td0, d0, d15\n+\tvadd.f64\td9, d7, d3\n+\tvsub.f64\td7, d8, d10\n+\tvadd.f64\td8, d3, d1\n+\tvsub.f64\td10, d1, d3\n+\tvsub.f64\td3, d6, d4\n+\tvsub.f64\td1, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvsub.f64\td6, d2, d5\n+\tvadd.f64\td2, d2, d5\n+\tvadd.f64\td5, d7, d0\n+\tvsub.f64\td7, d7, d0\n+\tvldr\td0, [sp, #48]\t@ 0x30\n \tadds\tr2, #1\n-\tvsub.f64\td5, d11, d13\n-\tvmov.f64\td4, d12\n-\tvfma.f64\td4, d17, d21\n-\tvfma.f64\td12, d21, d10\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tvmul.f64\td13, d26, d19\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tvmov.f64\td19, d5\n-\tvmov.f64\td21, d5\n-\tvfma.f64\td19, d6, d10\n-\tvfma.f64\td21, d17, d6\n-\tvadd.f64\td5, d20, d22\n-\tvnmul.f64\td6, d4, d2\n-\tvmul.f64\td12, d30, d12\n-\tvmul.f64\td14, d1, d4\n-\tvstr\td5, [r5, #-8]\n+\tstr\tr2, [sp, #24]\n+\tvstr\td4, [r5, #-8]\n \tadd\tr5, r9\n-\tvfma.f64\td6, d1, d19\n-\tvfma.f64\td13, d30, d21\n-\tvfma.f64\td12, d26, d21\n-\tvsub.f64\td21, d22, d20\n-\tvfma.f64\td14, d2, d19\n-\tvsub.f64\td19, d7, d15\n-\tvadd.f64\td7, d7, d15\n-\tvstr\td7, [fp, #-8]\n+\tvstr\td2, [fp, #-8]\n+\tvmul.f64\td4, d0, d8\n+\tvmul.f64\td2, d12, d8\n+\tvldr\td8, [sp, #80]\t@ 0x50\n+\tvmla.f64\td2, d0, d7\n+\tvldr\td0, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tadd\tfp, r9\n-\tvmov.f64\td4, d6\n-\tvsub.f64\td6, d20, d22\n-\tvmul.f64\td20, d21, d24\n-\tvfma.f64\td20, d28, d19\n-\tvmul.f64\td21, d6, d28\n-\tvfma.f64\td21, d24, d19\n-\tvstr\td20, [sl, #-8]\n-\tadd\tsl, r9\n+\tvnmls.f64\td4, d12, d7\n+\tvmul.f64\td7, d0, d6\n+\tvmla.f64\td7, d3, d8\n+\tvstr\td7, [sl, #-8]\n+\tvmul.f64\td7, d8, d6\n+\tvmla.f64\td7, d1, d0\n+\tvldr\td6, [sp, #104]\t@ 0x68\n \tvstr\td4, [lr, #-8]\n+\tadd\tsl, r9\n+\tvldr\td4, [sp, #112]\t@ 0x70\n \tadd\tlr, r9\n-\tvstr\td13, [ip, #-8]\n-\tadd\tip, r9\n-\tvstr\td21, [r0, #-8]\n+\tvstr\td7, [r0, #-8]\n+\tvmul.f64\td7, d6, d5\n+\tvmla.f64\td7, d9, d4\n+\tvstr\td2, [r1, #-8]\n \tadd\tr0, r9\n-\tvstr\td14, [r1, #-8]\n \tadd\tr1, r9\n-\tvstr\td12, [r3, #-8]\n-\tldr\tr3, [sp, #20]\n-\tvldr\td13, [r2, #-8]\n-\tvldr\td20, [r7, #-8]\n-\tvldr\td4, [r6, #-8]\n-\tvldr\td14, [r3, #-8]\n-\tldr\tr3, [sp, #32]\n-\tvsub.f64\td7, d20, d4\n-\tvldr\td19, [r8, #-8]\n-\tvsub.f64\td6, d13, d14\n-\tvldr\td15, [r4, #-8]\n-\tvadd.f64\td22, d13, d14\n-\tvadd.f64\td4, d20, d4\n-\tvldr\td11, [r3, #-8]\n-\tldr\tr3, [sp, #24]\n-\tvldr\td12, [r3, #-8]\n-\tldr\tr3, [sp, #16]\n-\tvsub.f64\td5, d11, d12\n-\tvadd.f64\td21, d11, d12\n-\tvsub.f64\td11, d6, d11\n+\tvstr\td7, [ip, #-8]\n+\tvmul.f64\td7, d4, d5\n+\tvmla.f64\td7, d10, d6\n+\tvldr\td8, [r2, #-8]\n+\tvldr\td5, [r6, #-8]\n+\tadd\tip, r9\n+\tvstr\td7, [r3, #-8]\n \tadd\tr3, r9\n-\tstr\tr3, [sp, #16]\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #28]\n+\tvldr\td7, [r7, #-8]\n+\tvldr\td9, [r3, #-8]\n+\tvsub.f64\td6, d7, d5\n \tldr\tr3, [sp, #32]\n-\tvsub.f64\td13, d5, d13\n-\tvadd.f64\td6, d6, d5\n-\tvadd.f64\td11, d11, d12\n-\tvsub.f64\td12, d7, d15\n-\tvsub.f64\td7, d7, d19\n-\tvadd.f64\td14, d13, d14\n-\tvmul.f64\td13, d29, d6\n-\tvmul.f64\td11, d11, d23\n-\tvadd.f64\td20, d7, d15\n-\tvadd.f64\td7, d12, d19\n-\tvadd.f64\td15, d15, d19\n-\tvnmul.f64\td12, d6, d25\n-\tvmul.f64\td19, d14, d3\n-\tvmov.f64\td5, d11\n-\tvfma.f64\td19, d23, d20\n-\tvfma.f64\td5, d3, d20\n-\tvadd.f64\td20, d4, d15\n-\tvsub.f64\td4, d4, d15\n-\tvfma.f64\td12, d29, d7\n-\tvfma.f64\td13, d25, d7\n-\tvsub.f64\td7, d22, d21\n-\tvmul.f64\td7, d7, d27\n-\tvmov.f64\td11, d19\n-\tvadd.f64\td19, d22, d21\n-\tvsub.f64\td21, d21, d22\n-\tvfma.f64\td7, d31, d20\n-\tvnmul.f64\td22, d19, d0\n-\tvmul.f64\td19, d9, d19\n-\tvfma.f64\td19, d0, d4\n-\tvfma.f64\td22, d9, d4\n-\tvmul.f64\td21, d21, d31\n-\tvfma.f64\td21, d27, d20\n-\tvstr\td19, [r3, #-8]\n-\tldr\tr3, [sp, #20]\n-\tvstr\td22, [r7, #-8]\n-\tadd\tr7, r9\n-\tvstr\td21, [r8, #-8]\n-\tadd\tr8, r9\n-\tvstr\td7, [r3, #-8]\n-\tldr\tr3, [sp, #24]\n-\tvstr\td5, [r6, #-8]\n-\tadd\tr6, r9\n-\tvstr\td12, [r2, #-8]\n-\tadd\tr2, r9\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvstr\td11, [r3, #-8]\n-\tldr\tr3, [sp, #20]\n-\tvstr\td13, [r4, #-8]\n-\tadd\tr4, r9\n-\tadd.w\tr2, r3, r9\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td10, [r4, #-8]\n+\tvsub.f64\td5, d8, d9\n+\tvadd.f64\td3, d8, d9\n+\tvldr\td12, [sp, #88]\t@ 0x58\n+\tvldr\td4, [r3, #-8]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvldr\td0, [r3, #-8]\n \tldr\tr3, [sp, #32]\n-\tstr\tr2, [sp, #20]\n+\tvsub.f64\td1, d4, d0\n+\tvadd.f64\td2, d4, d0\n+\tvsub.f64\td4, d5, d4\n+\tvadd.f64\td5, d5, d1\n+\tvsub.f64\td1, d1, d8\n+\tvadd.f64\td4, d4, d0\n+\tvldr\td0, [r8, #-8]\n+\tvadd.f64\td9, d1, d9\n+\tvsub.f64\td8, d6, d0\n+\tvldr\td1, [r8, #-8]\n+\tvsub.f64\td6, d6, d10\n+\tvstr\td4, [sp, #152]\t@ 0x98\n+\tvadd.f64\td4, d3, d2\n+\tvadd.f64\td1, d10, d1\n+\tvadd.f64\td8, d8, d10\n+\tvldr\td10, [sp, #96]\t@ 0x60\n+\tvadd.f64\td6, d6, d0\n+\tvadd.f64\td0, d7, d1\n+\tvsub.f64\td7, d7, d1\n+\tvsub.f64\td1, d3, d2\n+\tvsub.f64\td2, d2, d3\n+\tvmul.f64\td3, d10, d5\n+\tvmul.f64\td5, d12, d5\n+\tvmla.f64\td5, d10, d6\n+\tvnmls.f64\td3, d12, d6\n+\tvmul.f64\td6, d13, d4\n+\tvnmls.f64\td6, d11, d7\n+\tvmov.f64\td10, d5\n+\tvmul.f64\td5, d11, d4\n+\tvmla.f64\td5, d13, d7\n+\tvldr\td4, [sp, #152]\t@ 0x98\n+\tvstr\td6, [r7, #-8]\n+\tadd\tr7, r9\n+\tvldr\td6, [sp, #120]\t@ 0x78\n+\tvstr\td5, [r3, #-8]\n \tadd\tr3, r9\n \tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #24]\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tvmul.f64\td7, d6, d0\n+\tldr\tr3, [sp, #28]\n+\tvmla.f64\td7, d1, d14\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvstr\td7, [r3, #-8]\n+\tvmul.f64\td7, d14, d0\n+\tvmla.f64\td7, d2, d6\n+\tvldr\td6, [sp, #56]\t@ 0x38\n \tadd\tr3, r9\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvstr\td7, [r8, #-8]\n+\tvmul.f64\td7, d6, d8\n+\tvmla.f64\td7, d4, d5\n+\tadd\tr8, r9\n+\tvstr\td7, [r6, #-8]\n+\tvmul.f64\td7, d5, d8\n+\tvmla.f64\td7, d9, d6\n+\tvstr\td3, [r2, #-8]\n+\tadd\tr2, r9\n+\tstr\tr2, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #24]\n+\tadd\tr6, r9\n+\tvstr\td7, [r3, #-8]\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tvstr\td10, [r4, #-8]\n+\tadd\tr4, r9\n \tcmp\tr2, r3\n-\tbne.w\t2122 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2122>\n-\tldr.w\tr8, [sp, #128]\t@ 0x80\n+\tbne.w\t24c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x24c8>\n+\tldr.w\tr8, [sp, #232]\t@ 0xe8\n+\tvldr\td12, [sp, #224]\t@ 0xe0\n \tldr\tr3, [sp, #8]\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #28]\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tstr\tr3, [sp, #8]\n \tcmp\tr2, r3\n-\tble.n\t2336 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2336>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tble.n\t2702 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2702>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n \tadd\tr3, r2\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr2, [sp, #148]\t@ 0x94\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr3, [sp, #132]\t@ 0x84\n \tcmp\tr3, r2\n-\tbne.w\t204e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x204e>\n-\tldrd\tr6, r3, [sp, #68]\t@ 0x44\n-\tldrd\tsl, r1, [sp, #96]\t@ 0x60\n+\tbne.w\t23f0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23f0>\n+\tldrd\tsl, r3, [sp, #188]\t@ 0xbc\n+\tldr\tr7, [sp, #216]\t@ 0xd8\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n \tsubs\tr3, #1\n-\tldrd\tr2, lr, [sp, #104]\t@ 0x68\n-\tadds\tr5, r3, #1\n-\tldrd\tip, fp, [sp, #76]\t@ 0x4c\n-\tadd\tr2, r1\n-\tldrd\tr0, r7, [sp, #84]\t@ 0x54\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tbne.w\t2032 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2032>\n+\tldr\tr6, [sp, #196]\t@ 0xc4\n+\tadds\tr1, r3, #1\n+\tldr.w\tfp, [sp, #208]\t@ 0xd0\n+\tadd\tr2, r7\n+\tldr\tr4, [sp, #220]\t@ 0xdc\n+\tbne.w\t23da <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23da>\n \tmov\tr9, r8\n-\tldr.w\tr8, [sp, #64]\t@ 0x40\n-\tb.n\t1ff4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ff4>\n-\tnegs\tr3, r1\n-\tcmp\tsl, r7\n-\tudiv\tr3, lr, r3\n-\tble.w\t1cb8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1cb8>\n-\tb.n\t1ff4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1ff4>\n-\tldr\tr2, [sp, #164]\t@ 0xa4\n-\tnegs\tr3, r1\n-\tudiv\tr3, r2, r3\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tldr.w\tr8, [sp, #176]\t@ 0xb0\n+\tb.n\t23aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23aa>\n+\tnegs\tr1, r7\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t203a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x203a>\n+\tb.n\t23aa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23aa>\n+\tldr\tr0, [sp, #372]\t@ 0x174\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n \tcmp\tr2, #0\n-\tble.w\t1946 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1946>\n-\tb.n\t1bfc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bfc>\n-\tnegs\tr3, r0\n-\tnegs\tr2, r2\n-\tcmp\tr0, #0\n-\tudiv\tr3, r3, r2\n-\tbgt.w\t1932 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1932>\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\trsb\tlr, r1, #0\n+\tble.w\t1c6c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c6c>\n+\tb.w\t1f0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f0c>\n+\tnegs\tr1, r3\n+\trsb\tr0, r8, #0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp.w\tr8, #0\n+\tmov\tr3, r0\n+\tbgt.w\t1c54 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c54>\n+\tnegs\tr2, r7\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #584]\t@ 0x248\n \tcmp\tr2, #1\n-\tbeq.w\t1656 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1656>\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tmovs\tr2, #0\n-\tldr\tr5, [sp, #124]\t@ 0x7c\n-\tmov\tip, r0\n-\tadds\tr4, #1\n-\tldr\tr7, [sp, #164]\t@ 0xa4\n-\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tbeq.w\t1964 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1964>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tmovs\tr5, #0\n+\tldr\tr4, [sp, #316]\t@ 0x13c\n \tmov\tr6, r5\n-\tldr\tr4, [sp, #388]\t@ 0x184\n-\tmov\tfp, sl\n-\tldr.w\tr9, [sp, #28]\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #64]\t@ 0x40\n-\tcmp\tr1, #0\n-\tblt.w\t2d56 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d56>\n-\tudiv\tr0, r6, r1\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp\tr4, r2\n-\tblt.w\t266e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x266e>\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tcmp\tr4, #0\n-\tble.w\t266e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x266e>\n-\tadd.w\tr4, r9, r2\n-\tmov\tsl, fp\n-\tmov\tfp, r8\n+\tadds\tr2, #1\n+\tldr.w\tfp, [sp, #372]\t@ 0x174\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tmov\tr5, sl\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tstr.w\tr8, [sp, #88]\t@ 0x58\n+\tmov\tr8, r3\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tcmp\tr7, #0\n+\tblt.w\t2ff0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ff0>\n+\tmov\tr1, r7\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tblt.w\t2a48 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a48>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tcmp\tr2, #0\n+\tble.w\t2a48 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a48>\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tmov\tsl, r5\n+\tstr.w\tr8, [sp, #96]\t@ 0x60\n \tmov\tr8, r9\n-\tldr.w\tr9, [sp, #156]\t@ 0x9c\n-\tldr\tr5, [sp, #152]\t@ 0x98\n-\tstr\tr4, [sp, #8]\n-\tstr\tr5, [sp, #36]\t@ 0x24\n-\tstrd\tip, r3, [sp, #68]\t@ 0x44\n-\tstrd\tr2, lr, [sp, #76]\t@ 0x4c\n-\tstrd\tr0, r1, [sp, #84]\t@ 0x54\n-\tstrd\tr4, r7, [sp, #96]\t@ 0x60\n+\tldr.w\tr9, [sp, #356]\t@ 0x164\n+\tadd\tr2, r6\n \tstr\tr6, [sp, #104]\t@ 0x68\n-\tldrd\tr3, r2, [sp, #4]\n-\tadds\tr0, r3, r2\n-\tcmp\tr0, r8\n-\tbge.n\t2410 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2410>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr2, r3, r0\n-\tcmp\tr2, r8\n-\tbge.n\t241c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x241c>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr4, r3, r2\n-\tcmp\tr4, r8\n-\tbge.n\t2428 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2428>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr1, r3, r4\n-\tcmp\tr1, r8\n-\tbge.n\t2434 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2434>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr5, r3, r1\n-\tcmp\tr5, r8\n-\tbge.n\t2440 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2440>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #4]\n-\tadd\tr3, r5\n-\tcmp\tr3, r8\n-\tbge.n\t244c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x244c>\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r6\n-\tldr\tr6, [sp, #4]\n-\tadd\tr6, r3\n-\tcmp\tr6, r8\n-\tbge.n\t2458 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2458>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\tldr\tr1, [sp, #352]\t@ 0x160\n+\tstr\tr2, [sp, #8]\n+\tstr\tr1, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr7, [sp, #120]\t@ 0x78\n+\tstrd\tr2, fp, [sp, #132]\t@ 0x84\n+\tstr\tr4, [sp, #144]\t@ 0x90\n+\tldr\tr2, [sp, #8]\n+\tldr\tr3, [sp, #0]\n+\tldr\tr6, [sp, #140]\t@ 0x8c\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tldr\tr7, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr3, r3, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr1, r2, r3\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr1, r1, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr4, r2, r1\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr4, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr4, r4, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr0, r2, r4\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr0, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr0, r0, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr5, r2, r0\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr5, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr5, r5, r2\n+\tldr\tr2, [sp, #0]\n+\tadd\tr2, r5\n+\tcmp\tr2, r6\n+\titt\tlt\n+\tldrlt\tr6, [sp, #280]\t@ 0x118\n+\taddlt\tr2, r2, r6\n+\tldr\tr6, [sp, #0]\n+\tadd\tr6, r2\n+\tcmp\tr6, r7\n+\titt\tlt\n+\tldrlt\tr7, [sp, #280]\t@ 0x118\n+\taddlt\tr6, r6, r7\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tcmp\tr7, #0\n-\tble.w\t262c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x262c>\n+\tble.w\t2a08 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a08>\n+\tldr\tr7, [sp, #8]\n \tlsls\tr5, r5, #3\n+\tstr\tr5, [sp, #20]\n \tlsls\tr3, r3, #3\n-\tlsls\tr0, r0, #3\n-\tlsls\tr4, r4, #3\n-\tstr\tr4, [sp, #12]\n \tlsls\tr6, r6, #3\n-\tstr\tr6, [sp, #16]\n+\tstr\tr6, [sp, #24]\n+\tlsls\tr5, r7, #3\n \tadd.w\tr6, sl, r3\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #20]\n-\tadd.w\tr3, sl, r0\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tadd.w\tr3, sl, r5\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, fp, r5\n-\tldr\tr5, [sp, #12]\n-\tldr\tr7, [sp, #8]\n+\tadd.w\tfp, sl, r5\n+\tadd\tr5, r8\n+\tstr\tr5, [sp, #128]\t@ 0x80\n+\tadd\tr3, r8\n+\tldr\tr5, [sp, #20]\n+\tlsls\tr0, r0, #3\n+\tstr\tr3, [sp, #28]\n \tlsls\tr1, r1, #3\n-\tstr\tr3, [sp, #48]\t@ 0x30\n \tadd.w\tr3, sl, r5\n-\tstr\tr3, [sp, #12]\n-\tadd.w\tr3, fp, r5\n-\tldr\tr5, [sp, #16]\n-\tlsls\tr4, r7, #3\n-\tstr\tr6, [sp, #32]\n+\tldr\tr5, [sp, #20]\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tlsls\tr2, r2, #3\n-\tadd.w\tr6, sl, r5\n-\tstr\tr6, [sp, #16]\n-\tadd.w\tr6, fp, r5\n-\tstr\tr6, [sp, #56]\t@ 0x38\n-\tldr\tr5, [sp, #152]\t@ 0x98\n-\tadd.w\tlr, sl, r4\n+\tadd.w\tr3, r8, r5\n+\tldr\tr5, [sp, #24]\n+\tlsls\tr4, r4, #3\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tlr, sl, r0\n+\tadd.w\tr3, sl, r4\n \tadd.w\tip, sl, r1\n \tadd.w\tr7, sl, r2\n-\tadd\tr4, fp\n-\tadd\tr2, fp\n-\tadd\tr1, fp\n-\tadd\tr0, fp\n-\tstr.w\tr8, [sp, #108]\t@ 0x6c\n-\tldr.w\tr8, [sp, #48]\t@ 0x30\n-\tstr.w\tfp, [sp, #48]\t@ 0x30\n-\tldr.w\tfp, [sp, #56]\t@ 0x38\n-\tstr\tr5, [sp, #24]\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n-\tstr.w\tsl, [sp, #44]\t@ 0x2c\n+\tadd\tr0, r8\n+\tadd\tr2, r8\n+\tadd\tr1, r8\n+\tadd\tr4, r8\n+\tstr\tr3, [sp, #20]\n+\tadd.w\tr3, sl, r5\n+\tstr.w\tr8, [sp, #184]\t@ 0xb8\n+\tstr\tr3, [sp, #24]\n+\tadd.w\tr3, r8, r5\n+\tldr.w\tr8, [sp, #64]\t@ 0x40\n+\tldr\tr5, [sp, #352]\t@ 0x160\n+\tstr.w\tsl, [sp, #148]\t@ 0x94\n \tmov\tsl, r3\n-\tldr\tr6, [sp, #32]\n-\tstr\tr2, [sp, #32]\n-\tvldr\td20, [ip, #-8]\n-\tvldr\td28, [lr, #-8]\n-\tvldr\td19, [r1, #-8]\n-\tvldr\td27, [r4, #-8]\n-\tvadd.f64\td22, d28, d20\n-\tldr\tr3, [sp, #24]\n-\tldr\tr2, [sp, #32]\n-\tvsub.f64\td28, d28, d20\n-\tvadd.f64\td21, d27, d19\n+\tstr\tr5, [sp, #32]\n+\tldr\tr5, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tvldr\td5, [lr, #-8]\n+\tvldr\td3, [fp, #-8]\n+\tvldr\td6, [r5, #-8]\n+\tvldr\td10, [r0, #-8]\n+\tldr\tr3, [sp, #32]\n+\tvadd.f64\td2, d3, d5\n+\tvsub.f64\td3, d3, d5\n+\tldr\tr2, [sp, #28]\n+\tvadd.f64\td4, d6, d10\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #24]\n-\tvsub.f64\td27, d27, d19\n-\tvstr\td22, [lr, #-8]\n+\tstr\tr3, [sp, #32]\n+\tvsub.f64\td10, d6, d10\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvstr\td2, [fp, #-8]\n+\tadd\tfp, r9\n+\tvstr\td4, [r5, #-8]\n+\tadd\tr5, r9\n+\tvldr\td4, [r7, #-8]\n+\tvldr\td5, [ip, #-8]\n+\tvldr\td7, [r3, #-8]\n+\tvldr\td1, [r1, #-8]\n+\tvadd.f64\td6, d5, d4\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvsub.f64\td5, d5, d4\n+\tvadd.f64\td4, d1, d7\n+\tvsub.f64\td1, d1, d7\n+\tvstr\td6, [lr, #-8]\n \tadd\tlr, r9\n-\tldr\tr3, [sp, #20]\n-\tvstr\td21, [r4, #-8]\n-\tadd\tr4, r9\n-\tvldr\td20, [r7, #-8]\n-\tvldr\td21, [r6, #-8]\n-\tvldr\td22, [r3, #-8]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tvadd.f64\td26, d20, d21\n-\tvldr\td19, [r2, #-8]\n-\tvsub.f64\td21, d20, d21\n-\tldr\tr2, [sp, #12]\n-\tvadd.f64\td25, d19, d22\n-\tvsub.f64\td20, d19, d22\n-\tvstr\td26, [ip, #-8]\n-\tadd\tip, r9\n-\tvldr\td30, [r3, #-8]\n-\tvmul.f64\td29, d21, d17\n-\tvldr\td19, [r5, #-8]\n-\tvstr\td25, [r1, #-8]\n-\tvmul.f64\td26, d20, d17\n-\tvldr\td22, [r8, #-8]\n-\tadd\tr1, r9\n-\tvadd.f64\td21, d19, d30\n-\tvldr\td25, [r0, #-8]\n-\tvsub.f64\td19, d19, d30\n-\tvadd.f64\td20, d25, d22\n-\tvsub.f64\td25, d25, d22\n-\tvstr\td21, [r7, #-8]\n-\tadd\tr7, r9\n+\tvldr\td6, [r6, #-8]\n+\tvmul.f64\td5, d5, d15\n+\tvstr\td4, [r0, #-8]\n+\tvmul.f64\td11, d1, d15\n+\tvldr\td4, [r3, #-8]\n+\tadd\tr0, r9\n \tvldr\td7, [r2, #-8]\n-\tldr\tr2, [sp, #16]\n-\tvsub.f64\td22, d19, d7\n-\tvldr\td6, [r2, #-8]\n-\tldr\tr2, [sp, #32]\n-\tvadd.f64\td5, d7, d6\n-\tvsub.f64\td21, d19, d6\n-\tvadd.f64\td22, d22, d6\n-\tvstr\td20, [r2, #-8]\n-\tadd\tr2, r9\n-\tvldr\td30, [sl, #-8]\n-\tvldr\td31, [fp, #-8]\n-\tvadd.f64\td21, d21, d7\n-\tvstr\td5, [r6, #-8]\n-\tvmul.f64\td22, d22, d23\n-\tvsub.f64\td20, d25, d30\n-\tstr\tr2, [sp, #32]\n-\tvsub.f64\td19, d25, d31\n \tldr\tr2, [sp, #20]\n-\tvadd.f64\td25, d30, d31\n-\tvstr\td28, [r5, #-8]\n-\tvmul.f64\td21, d21, d24\n-\tvstr\td29, [r3, #-8]\n-\tvadd.f64\td20, d20, d31\n+\tvadd.f64\td1, d6, d4\n+\tvldr\td2, [r8, #-8]\n+\tvsub.f64\td6, d6, d4\n+\tvadd.f64\td4, d7, d2\n+\tvsub.f64\td7, d7, d2\n+\tvstr\td1, [ip, #-8]\n+\tadd\tip, r9\n+\tvldr\td2, [r2, #-8]\n+\tldr\tr2, [sp, #24]\n+\tvstr\td4, [r1, #-8]\n+\tadd\tr1, r9\n+\tvsub.f64\td4, d6, d2\n+\tvldr\td9, [r4, #-8]\n+\tvldr\td8, [sl, #-8]\n+\tvldr\td1, [r2, #-8]\n+\tvadd.f64\td0, d2, d1\n+\tvsub.f64\td6, d6, d1\n+\tvadd.f64\td4, d4, d1\n+\tvsub.f64\td1, d7, d9\n+\tvsub.f64\td7, d7, d8\n+\tvstr\td0, [r7, #-8]\n+\tvadd.f64\td6, d6, d2\n+\tvstr\td3, [r6, #-8]\n+\tvadd.f64\td2, d9, d8\n+\tvstr\td5, [r3, #-8]\n+\tvmul.f64\td4, d4, d14\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tvadd.f64\td1, d1, d8\n+\tvmul.f64\td6, d6, d13\n+\tvadd.f64\td7, d7, d9\n \tadd\tr3, r9\n-\tvadd.f64\td19, d19, d30\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tvstr\td25, [r2, #-8]\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr7, r9\n \tadd\tr6, r9\n-\tldr\tr2, [sp, #12]\n-\tadd\tr5, r9\n-\tvmul.f64\td20, d20, d23\n-\tvstr\td27, [r0, #-8]\n-\tvmul.f64\td19, d19, d24\n-\tvstr\td26, [r8, #-8]\n-\tadd\tr0, r9\n+\tvstr\td2, [r2, #-8]\n+\tvmul.f64\td1, d1, d14\n+\tldr\tr2, [sp, #28]\n+\tvmul.f64\td7, d7, d13\n+\tvstr\td10, [r2, #-8]\n+\tldr\tr2, [sp, #20]\n+\tvstr\td11, [r8, #-8]\n \tadd\tr8, r9\n-\tvstr\td22, [r2, #-8]\n-\tldr\tr2, [sp, #16]\n-\tvstr\td20, [sl, #-8]\n+\tvstr\td1, [r4, #-8]\n+\tadd\tr4, r9\n+\tvstr\td7, [sl, #-8]\n \tadd\tsl, r9\n-\tvstr\td19, [fp, #-8]\n-\tadd\tfp, r9\n-\tvstr\td21, [r2, #-8]\n-\tldr\tr2, [sp, #12]\n+\tvstr\td4, [r2, #-8]\n+\tldr\tr2, [sp, #24]\n+\tvstr\td6, [r2, #-8]\n+\tldr\tr2, [sp, #20]\n \tadd.w\tr3, r2, r9\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #24]\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #28]\n \tadd\tr2, r9\n-\tstr\tr2, [sp, #16]\n+\tstr\tr2, [sp, #24]\n \tadd\tr3, r9\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #24]\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #32]\n \tcmp\tr3, r2\n-\tbne.w\t24e0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x24e0>\n-\tldr.w\tr8, [sp, #108]\t@ 0x6c\n-\tldrd\tsl, fp, [sp, #44]\t@ 0x2c\n+\tbne.w\t28ba <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x28ba>\n+\tldr.w\tsl, [sp, #148]\t@ 0x94\n+\tldr.w\tr8, [sp, #184]\t@ 0xb8\n \tldr\tr3, [sp, #8]\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n \tadd\tr3, r2\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tstr\tr3, [sp, #8]\n-\tcmp\tr3, r8\n-\tbge.n\t263e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x263e>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tcmp\tr3, r2\n+\tbge.n\t2a1c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a1c>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n \tadd\tr3, r2\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #72]\t@ 0x48\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, r2\n-\tbne.w\t2402 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2402>\n-\tldrd\tr0, r1, [sp, #84]\t@ 0x54\n-\tldrd\tr4, r7, [sp, #96]\t@ 0x60\n-\tsubs\tr0, #1\n-\tldrd\tip, r3, [sp, #68]\t@ 0x44\n-\tadd\tr4, r1\n-\tldrd\tr2, lr, [sp, #76]\t@ 0x4c\n-\tadds\tr5, r0, #1\n-\tldr\tr6, [sp, #104]\t@ 0x68\n-\tbne.w\t23ea <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23ea>\n-\tmov\tr9, r8\n-\tmov\tr8, fp\n-\tmov\tfp, sl\n-\tldr\tr0, [sp, #136]\t@ 0x88\n+\tbne.w\t27dc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x27dc>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tldrd\tr2, fp, [sp, #132]\t@ 0x84\n \tsubs\tr3, #1\n-\tadd\tr2, r0\n-\tadd\tr7, r0\n-\tsubs\tr6, r6, r0\n-\tadds\tr0, r3, #1\n-\tbne.w\t23c2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23c2>\n-\tmov\tr0, ip\n-\tmov\tsl, fp\n-\tb.w\t1932 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1932>\n-\tudiv\tr2, r8, r1\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp\tr4, r3\n-\tble.w\t89e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x89e>\n-\tb.w\te38 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe38>\n-\tldr\tr1, [sp, #232]\t@ 0xe8\n-\tldr\tr2, [sp, #188]\t@ 0xbc\n-\tudiv\tr2, r2, r1\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tcmp\tr1, r3\n-\tble.w\tf18 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xf18>\n-\tb.w\t157c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x157c>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tnegs\tr2, r7\n-\tsub.w\tr3, r3, lr\n-\tadds\tr1, r3, r0\n-\tudiv\tr4, r1, r2\n-\tldr\tr2, [sp, #172]\t@ 0xac\n-\tcmp\tlr, r2\n-\tble.w\tefa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xefa>\n-\tb.w\t1592 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1592>\n-\tmov\tr4, r9\n-\tmov\tr9, fp\n-\tmov\tfp, sl\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n-\tldr\tr2, [sp, #160]\t@ 0xa0\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #192]\t@ 0xc0\n-\tcmp\tr2, r3\n-\tbge.w\t830 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x830>\n+\tldr\tr7, [sp, #120]\t@ 0x78\n+\tadds\tr6, r3, #1\n+\tldr\tr4, [sp, #144]\t@ 0x90\n+\tadd\tr2, r7\n+\tbne.w\t27cc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x27cc>\n+\tmov\tr9, r8\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr.w\tr8, [sp, #96]\t@ 0x60\n+\tmov\tr5, sl\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tadd\tr6, r3\n+\tadd\tfp, r3\n+\tsub.w\tr4, r4, r3\n+\tbne.w\t279a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x279a>\n+\tldr.w\tr8, [sp, #88]\t@ 0x58\n+\tmov\tsl, r5\n+\tb.w\t1c54 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c54>\n+\tldr\tr1, [sp, #188]\t@ 0xbc\n+\tldr\tr0, [sp, #160]\t@ 0xa0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tble.w\t414 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x414>\n+\tb.w\t986 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x986>\n+\tldr\tr1, [sp, #452]\t@ 0x1c4\n+\tldr\tr0, [sp, #416]\t@ 0x1a0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #8]\n+\tmov\tr1, r0\n+\tcmp\tr3, r2\n+\tble.w\taae <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xaae>\n+\tb.w\t1202 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1202>\n+\tldr\tr6, [sp, #396]\t@ 0x18c\n+\tnegs\tr1, r3\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tldr\tr3, [sp, #388]\t@ 0x184\n+\tsubs\tr4, r2, r6\n+\tadds\tr0, r4, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #384]\t@ 0x180\n+\tmov\tr3, r0\n+\tcmp\tr6, r2\n+\tldr\tr2, [sp, #8]\n+\tble.w\ta74 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xa74>\n+\tb.w\t1228 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1228>\n+\tmov\tr3, sl\n+\tldr\tr7, [sp, #460]\t@ 0x1cc\n \tmov\tsl, r9\n-\tmov\tr8, r4\n-\tb.w\t1fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa>\n-\tsubs\tr0, r5, r3\n-\tnegs\tr1, r5\n-\tcmp\tr5, r3\n-\tudiv\tr8, r0, r1\n-\tbge.w\te74 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe74>\n-\tb.n\t26ca <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26ca>\n-\trsb\tr3, lr, #0\n-\tnegs\tr2, r7\n-\tcmp.w\tlr, #0\n-\tudiv\tr0, r3, r2\n-\tble.w\t86a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x86a>\n-\tb.w\te50 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0xe50>\n-\tldr\tr4, [sp, #388]\t@ 0x184\n-\tmov\tlr, sl\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #32]\n-\tstrd\tr7, ip, [sp, #52]\t@ 0x34\n-\tmov\tr1, r2\n-\tmov.w\tr8, #1\n-\tmov\tsl, r0\n-\tmov\tip, r2\n-\tstrd\tr6, r3, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #4]\n-\tadd\tr3, r1\n-\tcmp\tr3, r9\n-\tbge.n\t272e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x272e>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #4]\n-\tadd\tr2, r3\n-\tcmp\tr2, r9\n-\tbge.n\t273a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x273a>\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #4]\n-\tadd\tr0, r2\n-\tcmp\tr0, r9\n-\tbge.n\t2746 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2746>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r4\n-\tldr\tr4, [sp, #388]\t@ 0x184\n+\tmov\tr9, r3\n+\tldr\tr3, [sp, #368]\t@ 0x170\n+\tadds\tr7, #1\n+\tcmp\tr3, r7\n+\tbge.w\t392 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x392>\n+\tb.w\t1f12 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f12>\n+\tnegs\tr1, r3\n+\tsubs\tr0, r3, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tstr\tr0, [sp, #420]\t@ 0x1a4\n+\tcmp\tr3, r4\n+\tbge.w\t9ce <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9ce>\n+\tb.n\t2ac0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac0>\n+\tnegs\tr1, r2\n+\tnegs\tr0, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n \tcmp\tr4, #0\n-\tble.n\t2834 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2834>\n-\tlsls\tr0, r0, #3\n-\tstr\tr0, [sp, #24]\n-\tldr\tr0, [sp, #12]\n+\tmov\tr6, r0\n+\tble.w\t3da <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3da>\n+\tb.w\t9a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x9a4>\n+\tcmp\tr2, #0\n+\tble.w\t334 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x334>\n+\tmov\tr0, r2\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr2, r1, #536870912\t@ 0x20000000\n+\tadd.w\tlr, r0, r1\n+\tsubs\tr3, #1\n+\tldr\tr0, [sp, #344]\t@ 0x158\n+\tsubs\tr2, #1\n \tlsls\tr3, r3, #3\n-\tadd.w\tr6, lr, r3\n-\tlsls\tr5, r1, #3\n-\tadd\tr3, r0\n-\tstr\tr3, [sp, #20]\n \tlsls\tr2, r2, #3\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #16]\n-\tadd.w\tr7, lr, r2\n-\tldr\tr3, [sp, #20]\n-\tadd\tr2, r0\n-\tadd.w\tr4, lr, r5\n+\tadd.w\tr0, r0, lr, lsl #3\n+\tadd.w\tr8, sl, r3\n+\tadd.w\tlr, sl, r2\n+\tadd\tr3, r9\n+\tadd\tr2, r9\n+\tvldr\td5, [lr]\n+\tvldr\td6, [r8]\n+\tvldr\td3, [r3]\n+\tvldr\td7, [r2]\n+\tvsub.f64\td4, d5, d6\n+\tvadd.f64\td6, d6, d5\n+\tvsub.f64\td5, d3, d7\n+\tvadd.f64\td7, d7, d3\n+\tvmul.f64\td4, d4, d12\n+\tvstmia\tlr!, {d6}\n+\tcmp\tlr, r0\n+\tvmul.f64\td5, d5, d12\n+\tvstmia\tr2!, {d7}\n+\tvstmia\tr3!, {d4}\n+\tvstmia\tr8!, {d5}\n+\tbne.n\t2b24 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b24>\n+\tb.w\t334 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x334>\n+\tldr\tr1, [sp, #28]\n+\tldr\tr0, [sp, #20]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tcmp\tr3, r4\n+\tble.w\t292 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x292>\n+\tb.w\t35a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x35a>\n+\tnegs\tr1, r4\n+\tsubs\tr0, r4, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r6\n+\tmov\tr7, r0\n+\tblt.w\t378 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x378>\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tldr\tr3, [sp, #584]\t@ 0x248\n+\tmov.w\tfp, r2, lsl #3\n+\tcmp\tr3, #1\n+\tbeq.w\t24c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x24c>\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #320]\t@ 0x140\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr1, [sp, #316]\t@ 0x13c\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #28]\n+\tmov\tr4, r3\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tsubs\tr5, r3, r1\n+\tldr\tr0, [sp, #376]\t@ 0x178\n+\tsubs\tr1, r1, r3\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #24]\n+\trsb\tr2, r8, #0\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tmov\tr2, r5\n+\tldr\tr5, [sp, #356]\t@ 0x164\n+\tadd.w\tr6, r0, fp\n+\tstr\tr1, [sp, #20]\n+\tvldr\td8, [r6, #8]\n+\tcmp.w\tr8, #0\n+\tvldr\td7, [sp, #360]\t@ 0x168\n+\tvldr\td9, [r6]\n+\tvmul.f64\td8, d7, d8\n+\tblt.w\t330e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x330e>\n+\tldr\tr0, [sp, #20]\n+\tmov\tr1, r8\n+\tstr\tr2, [sp, #32]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #32]\n+\tcmp\tr3, r4\n+\tblt.n\t2cbe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cbe>\n+\tldr\tr3, [sp, #320]\t@ 0x140\n+\tcmp\tr3, #0\n+\tble.n\t2cbe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cbe>\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tstr\tr7, [sp, #32]\n+\tmov\tr7, fp\n+\tadd\tr3, r4\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tldr.w\tip, [sp, #348]\t@ 0x15c\n+\tmov\tr4, r3\n+\tstr.w\tr8, [sp, #48]\t@ 0x30\n+\tstr\tr0, [sp, #56]\t@ 0x38\n+\tldr\tr1, [sp, #0]\n+\tldr\tr0, [sp, #140]\t@ 0x8c\n+\tadd.w\tlr, r1, r4\n+\tldr\tr1, [sp, #428]\t@ 0x1ac\n+\tcmp\tlr, r0\n+\titt\tlt\n+\tldrlt\tr0, [sp, #280]\t@ 0x118\n+\taddlt\tlr, r0\n+\tldr\tr0, [sp, #8]\n+\tcmp\tr0, r1\n+\tldr\tr1, [sp, #596]\t@ 0x254\n+\tbeq.w\t32a4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x32a4>\n+\tcmp\tr1, #0\n+\tble.n\t2c92 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c92>\n+\tmov.w\tr1, lr, lsl #3\n+\tlsls\tr0, r4, #3\n+\tldr.w\tfp, [sp, #348]\t@ 0x15c\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tlr, sl, r1\n+\tadd\tr0, r9\n+\tadd\tr1, r9\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\td4, [r1, #-8]\n+\tadd.w\tfp, fp, #1\n+\tvldr\td6, [r0, #-8]\n+\tvldr\td3, [lr, #-8]\n+\tvldr\td5, [r8, #-8]\n+\tvsub.f64\td7, d6, d4\n+\tvadd.f64\td6, d6, d4\n+\tldr\tr3, [sp, #24]\n+\tvsub.f64\td4, d5, d3\n+\tvadd.f64\td5, d5, d3\n+\tcmp\tfp, r3\n+\tvmul.f64\td3, d8, d7\n+\tvmul.f64\td7, d9, d7\n+\tvstr\td6, [r0, #-8]\n \tadd\tr0, r5\n-\tstrd\tr8, r9, [sp, #60]\t@ 0x3c\n-\tstrd\tr1, r5, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #16]\n-\tldr\tr5, [sp, #72]\t@ 0x48\n-\tadds\tr1, #1\n-\tstrd\tr1, r1, [sp, #16]\n-\tldr\tr1, [sp, #24]\n-\tsub.w\tr8, r4, r5\n-\tvldr\td21, [r7, #-8]\n-\tsub.w\tr9, r0, r5\n-\tadd\tr8, r1\n-\tvldr\td22, [r2, #-8]\n-\tvldr\td19, [r4, #-8]\n-\tadd\tr9, r1\n-\tvldr\td17, [r0, #-8]\n-\tvldr\td20, [r6, #-8]\n-\tvldr\td23, [r8, #-8]\n-\tvsub.f64\td25, d19, d21\n-\tvadd.f64\td19, d19, d21\n-\tvsub.f64\td21, d17, d22\n-\tvadd.f64\td17, d17, d22\n-\tvldr\td24, [r3, #-8]\n-\tvsub.f64\td22, d20, d23\n-\tvadd.f64\td20, d20, d23\n-\tvldr\td23, [r9, #-8]\n-\tvmov.f64\td26, d21\n-\tldr\tr1, [sp, #20]\n-\tldr\tr5, [sp, #32]\n-\tvfma.f64\td26, d22, d16\n-\tvfms.f64\td21, d22, d16\n-\tvadd.f64\td22, d19, d20\n-\tvsub.f64\td19, d19, d20\n-\tcmp\tr1, r5\n-\tvstr\td22, [r4, #-8]\n-\tvsub.f64\td22, d24, d23\n-\tvadd.f64\td24, d24, d23\n-\tvmov.f64\td23, d25\n-\tvstr\td19, [r7, #-8]\n-\tadd\tr4, fp\n-\tadd\tr7, fp\n-\tvfma.f64\td23, d22, d18\n-\tvfma.f64\td25, d16, d22\n-\tvadd.f64\td22, d17, d24\n-\tvsub.f64\td17, d17, d24\n-\tvstr\td22, [r0, #-8]\n-\tadd\tr0, fp\n-\tvstr\td17, [r2, #-8]\n-\tadd\tr2, fp\n-\tvstr\td26, [r3, #-8]\n-\tadd\tr3, fp\n-\tvstr\td23, [r6, #-8]\n-\tadd\tr6, fp\n-\tvstr\td21, [r9, #-8]\n-\tvstr\td25, [r8, #-8]\n-\tbne.n\t277a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x277a>\n-\tldrd\tr8, r9, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr1, r3\n-\tcmp\tr1, r9\n-\tbge.n\t2840 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2840>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r3\n+\tvmla.f64\td7, d8, d4\n+\tvstr\td5, [r8, #-8]\n+\tadd\tr8, r5\n+\tvnmls.f64\td3, d9, d4\n+\tvstr\td7, [r1, #-8]\n+\tadd\tr1, r5\n+\tvstr\td3, [lr, #-8]\n+\tadd\tlr, r5\n+\tbne.n\t2c3e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c3e>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr1, [sp, #300]\t@ 0x12c\n+\tadd\tr4, r1\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tcmp\tr4, r1\n+\tbge.n\t2ca0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ca0>\n+\tldr\tr1, [sp, #280]\t@ 0x118\n+\tadd\tr4, r1\n+\tldr\tr1, [sp, #28]\n+\tadd.w\tip, ip, #1\n+\tcmp\tip, r1\n+\tbne.n\t2c06 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c06>\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tldr.w\tr8, [sp, #48]\t@ 0x30\n+\tsubs\tr0, #1\n+\tadd\tr3, r8\n+\tadds\tr4, r0, #1\n+\tbne.n\t2bfa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bfa>\n+\tmov\tfp, r7\n+\tldr\tr4, [sp, #40]\t@ 0x28\n+\tldr\tr7, [sp, #32]\n \tldr\tr3, [sp, #8]\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr8, r3\n-\tbne.w\t2722 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2722>\n-\tldrd\tr6, r3, [sp, #44]\t@ 0x2c\n-\tmov\tr2, ip\n-\tldr\tr7, [sp, #52]\t@ 0x34\n-\tmov\tr0, sl\n-\tsubs\tr3, #1\n-\tldr.w\tip, [sp, #56]\t@ 0x38\n-\tadd\tr2, r7\n-\tadds\tr4, r3, #1\n-\tbne.w\t2710 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2710>\n-\tldr\tr3, [sp, #384]\t@ 0x180\n-\tmov\tsl, lr\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tcmp\tr3, #2\n-\tbne.w\t3d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3d0>\n-\tldr.w\tr8, [sp, #12]\n-\tb.w\t1fa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1fa>\n-\tldr\tr5, [sp, #32]\n-\tnegs\tr1, r7\n-\tcmp\tip, r4\n-\tudiv\tr1, r5, r1\n-\tble.w\t45e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x45e>\n-\tb.w\t5f8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x5f8>\n-\tldr\tr1, [sp, #168]\t@ 0xa8\n-\tadds\tr2, #8\n-\tmov.w\tr8, r3, lsl #3\n-\tlsls\tr3, r3, #4\n-\tadds\tr2, r1, r2\n-\tstr\tr2, [sp, #20]\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tsub.w\tr0, r6, ip\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, r1, r8\n-\tadds\tr2, #1\n+\tsubs\tr7, #1\n+\tldr\tr1, [sp, #336]\t@ 0x150\n+\tadd\tr6, fp\n+\tadd\tr3, r1\n+\tldr\tr1, [sp, #20]\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tadd\tr4, r3\n+\tadd\tr2, r3\n+\tsubs\tr3, r1, r3\n+\tadds\tr1, r7, #1\n+\tstr\tr3, [sp, #20]\n+\tbne.w\t2bc0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bc0>\n+\tb.w\t378 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x378>\n+\tldr\tr3, [sp, #592]\t@ 0x250\n+\tand.w\tr3, r3, #3\n+\tstr\tr3, [sp, #348]\t@ 0x15c\n+\tcmp\tr3, #1\n+\tbeq.w\t3324 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3324>\n+\tcmp\tr3, #3\n+\tittee\tne\n+\tmovne\tr3, #0\n+\tstrdne\tr3, r3, [sp, #348]\t@ 0x15c\n+\tldreq\tr3, [sp, #592]\t@ 0x250\n+\tsubeq\tr3, #3\n+\titttt\teq\n+\tasreq\tr3, r3, #1\n+\tstreq\tr3, [sp, #368]\t@ 0x170\n+\tmoveq\tr3, #0\n+\tstreq\tr3, [sp, #348]\t@ 0x15c\n+\tb.w\t64 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x64>\n+\tmov\tr2, r3\n+\tasrs\tr3, r3, #1\n+\tadds\tr3, #1\n+\tbic.w\tr3, r3, #1\n+\tstr\tr3, [sp, #596]\t@ 0x254\n+\tsubs\tr2, r2, r3\n+\tstr\tr2, [sp, #424]\t@ 0x1a8\n+\tb.w\t130 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x130>\n+\tldr.w\tfp, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #400]\t@ 0x190\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr2, r3\n+\tbge.w\t131e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x131e>\n+\tldr.w\tr9, [sp, #28]\n+\tb.w\t13c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x13c>\n+\tnegs\tr1, r6\n+\tsubs\tr0, r6, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tstr\tr0, [sp, #32]\n+\tblt.n\t2d22 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d22>\n+\tldr\tr3, [sp, #584]\t@ 0x248\n+\tcmp\tr3, #1\n+\tmov.w\tr3, #24\n+\tbeq.w\t14d2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x14d2>\n+\tmul.w\tip, r3, r4\n+\tldr\tr0, [sp, #376]\t@ 0x178\n+\tlsls\tr1, r4, #3\n+\tlsls\tr3, r4, #4\n+\tadd.w\tr2, ip, #8\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tadds\tr4, r0, r2\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tadds\tr3, r0, r1\n+\tstr.w\tr9, [sp, #128]\t@ 0x80\n+\tsubs\tr0, r6, r2\n+\tsubs\tr2, r2, r6\n \tstr\tr2, [sp, #48]\t@ 0x30\n-\tadd.w\tlr, r3, r8\n-\tstr\tr0, [sp, #24]\n-\tstr.w\tsl, [sp, #32]\n-\tmov\tr0, r9\n-\tldr.w\tsl, [sp, #48]\t@ 0x30\n-\tmov\tr4, lr\n-\tldr.w\tr9, [sp, #20]\n-\tsub.w\tr1, ip, r6\n-\tmov\tr5, r6\n-\tnegs\tr2, r7\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tvldr\td23, [r3, #8]\n+\tmov\tr8, r6\n+\tldr\tr2, [sp, #596]\t@ 0x254\n+\tmov\tr9, ip\n+\tstr.w\tsl, [sp, #72]\t@ 0x48\n+\tadds\tr5, r3, r1\n+\tadds\tr2, #1\n+\tstr\tr0, [sp, #40]\t@ 0x28\n+\tmov\tsl, r2\n+\tnegs\tr0, r7\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tstr\tr0, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tvldr\td7, [sp, #360]\t@ 0x168\n \tcmp\tr7, #0\n-\tvldr\td24, [r4, #8]\n-\tvldr\td25, [r9]\n-\tvmul.f64\td23, d8, d23\n-\tvldr\td26, [r3]\n-\tvmul.f64\td24, d8, d24\n-\tvldr\td27, [r4]\n-\tvmul.f64\td25, d8, d25\n-\tvldr\td28, [r9, #-8]\n-\tblt.w\t2ade <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ade>\n-\tudiv\tr3, r1, r7\n-\tcmp\tip, r5\n-\tblt.w\t2a9e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a9e>\n-\tldr\tr2, [sp, #120]\t@ 0x78\n+\tvldr\td5, [r3, #8]\n+\tvldr\td14, [r5, #8]\n+\tvldr\td11, [r4]\n+\tvmul.f64\td6, d7, d5\n+\tvldr\td10, [r3]\n+\tvmul.f64\td14, d7, d14\n+\tvldr\td15, [r5]\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td13, [r4, #-8]\n+\tvstr\td6, [sp]\n+\tblt.w\t2fbc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fbc>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t2f84 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f84>\n+\tldr\tr2, [sp, #320]\t@ 0x140\n \tcmp\tr2, #0\n-\tble.w\t2a9e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a9e>\n-\tadds\tr2, r0, r5\n-\tstr\tr6, [sp, #48]\t@ 0x30\n-\tstr\tr2, [sp, #20]\n-\tstrd\tr5, r8, [sp, #56]\t@ 0x38\n-\tstrd\tr1, r9, [sp, #64]\t@ 0x40\n-\tldr.w\tr9, [sp, #20]\n-\tmovs\tr1, #1\n-\tstrd\tr7, r3, [sp, #72]\t@ 0x48\n-\tstrd\tip, r4, [sp, #80]\t@ 0x50\n-\tstr.w\tlr, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #4]\n+\tble.w\t2f84 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f84>\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tmov\tr1, r9\n+\tadd\tr2, r8\n+\tmov\tr9, r2\n+\tmovs\tr0, #1\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr\tr7, [sp, #112]\t@ 0x70\n+\tstr.w\tr8, [sp, #120]\t@ 0x78\n+\tstrd\tr3, r2, [sp, #132]\t@ 0x84\n+\tstrd\tr5, r4, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #20]\n \tadd.w\tr4, r3, r9\n-\tcmp\tr4, r0\n-\tbge.n\t2932 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2932>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #4]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tcmp\tr4, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #280]\t@ 0x118\n+\taddlt\tr4, r4, r3\n+\tldr\tr3, [sp, #20]\n \tadds\tr5, r3, r4\n-\tcmp\tr5, r0\n-\tbge.n\t293e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x293e>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #4]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tcmp\tr5, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #280]\t@ 0x118\n+\taddlt\tr5, r5, r3\n+\tldr\tr3, [sp, #20]\n \tadd.w\tlr, r3, r5\n-\tcmp\tlr, r0\n-\tbge.n\t294c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x294c>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #388]\t@ 0x184\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tcmp\tlr, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #280]\t@ 0x118\n+\taddlt\tlr, r3\n+\tldr\tr3, [sp, #596]\t@ 0x254\n \tcmp\tr3, #0\n-\tble.w\t2a64 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a64>\n-\tldr\tr3, [sp, #32]\n+\tble.w\t2f50 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f50>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tlsls\tr5, r5, #3\n-\tldr\tr6, [sp, #12]\n+\tldr\tr6, [sp, #28]\n \tlsls\tr4, r4, #3\n \tmov.w\tr8, r9, lsl #3\n \tadds\tr7, r3, r5\n \tadd.w\tr2, r3, r8\n \tadd\tr5, r6\n \tadds\tr6, r3, r4\n-\tldr\tr3, [sp, #12]\n+\tldr\tr3, [sp, #28]\n \tmov.w\tlr, lr, lsl #3\n \tmov.w\tip, #1\n \tadd\tr4, r3\n \tadd\tr3, r8\n-\tstrd\tr1, r0, [sp, #96]\t@ 0x60\n-\tsub.w\tr0, r2, r8\n-\tvldr\td20, [r7, #-8]\n-\tvldr\td19, [r2, #-8]\n+\tstr\tr0, [sp, #184]\t@ 0xb8\n+\tstr.w\tr9, [sp, #152]\t@ 0x98\n+\tsub.w\tr9, r2, r8\n+\tvldr\td3, [r6, #-8]\n+\tadd\tr9, lr\n+\tvldr\td2, [r2, #-8]\n+\tvldr\td8, [r7, #-8]\n+\tsub.w\tr0, r3, r8\n+\tvldr\td5, [r3, #-8]\n \tadd\tr0, lr\n-\tvldr\td22, [r3, #-8]\n-\tsub.w\tr1, r3, r8\n-\tvldr\td31, [r6, #-8]\n-\tadd\tr1, lr\n-\tvldr\td17, [r5, #-8]\n-\tvsub.f64\td30, d19, d20\n-\tvadd.f64\td19, d19, d20\n-\tvldr\td20, [r0, #-8]\n-\tvldr\td29, [r4, #-8]\n+\tvldr\td7, [r9, #-8]\n \tadd.w\tip, ip, #1\n-\tvsub.f64\td5, d22, d17\n-\tvsub.f64\td6, d17, d22\n-\tvsub.f64\td7, d31, d20\n-\tvadd.f64\td20, d31, d20\n-\tvadd.f64\td17, d22, d17\n+\tvadd.f64\td4, d2, d8\n+\tvsub.f64\td8, d2, d8\n+\tvldr\td6, [r5, #-8]\n \tcmp\tip, sl\n-\tvmov.f64\td21, d5\n-\tvfma.f64\td5, d7, d18\n-\tvfma.f64\td21, d16, d7\n-\tvfma.f64\td6, d16, d7\n-\tvsub.f64\td7, d19, d20\n-\tvadd.f64\td19, d19, d20\n-\tvstr\td19, [r2, #-8]\n+\tvadd.f64\td2, d3, d7\n+\tvsub.f64\td7, d3, d7\n+\tvldr\td0, [r4, #-8]\n+\tvadd.f64\td3, d5, d6\n+\tvsub.f64\td9, d5, d6\n+\tvsub.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d12\n+\tvadd.f64\td6, d6, d7\n+\tvadd.f64\td5, d7, d9\n+\tvsub.f64\td9, d9, d7\n+\tvldr\td7, [r0, #-8]\n+\tvstr\td6, [sp, #8]\n+\tvsub.f64\td6, d4, d2\n+\tvadd.f64\td4, d4, d2\n+\tvsub.f64\td7, d0, d7\n+\tvldr\td2, [sp]\n+\tvstr\td4, [r2, #-8]\n+\tvmul.f64\td7, d7, d12\n+\tvldr\td4, [r0, #-8]\n+\tvmul.f64\td2, d2, d5\n+\tvmul.f64\td5, d10, d5\n \tadd\tr2, fp\n-\tvmul.f64\td19, d28, d5\n-\tvldr\td5, [r1, #-8]\n-\tvmul.f64\td20, d25, d6\n-\tvmov.f64\td6, d30\n-\tvnmul.f64\td31, d21, d23\n-\tvmul.f64\td21, d26, d21\n-\tvsub.f64\td22, d29, d5\n-\tvadd.f64\td5, d29, d5\n-\tvfma.f64\td6, d22, d18\n-\tvfma.f64\td30, d16, d22\n-\tvsub.f64\td29, d5, d17\n-\tvsub.f64\td22, d17, d5\n-\tvadd.f64\td17, d17, d5\n-\tvmul.f64\td29, d29, d24\n-\tvmul.f64\td22, d22, d27\n-\tvfma.f64\td29, d27, d7\n-\tvfma.f64\td22, d24, d7\n-\tvstr\td17, [r3, #-8]\n+\tvadd.f64\td4, d0, d4\n+\tvsub.f64\td1, d4, d3\n+\tvsub.f64\td0, d3, d4\n+\tvadd.f64\td3, d3, d4\n+\tvadd.f64\td4, d8, d7\n+\tvsub.f64\td7, d8, d7\n+\tvstr\td3, [r3, #-8]\n \tadd\tr3, fp\n-\tvfma.f64\td31, d26, d6\n-\tvfma.f64\td21, d23, d6\n-\tvfma.f64\td20, d28, d30\n-\tvfma.f64\td19, d25, d30\n-\tvstr\td31, [r6, #-8]\n+\tvldr\td3, [sp]\n+\tvnmls.f64\td2, d10, d7\n+\tvmla.f64\td5, d3, d7\n+\tvldr\td3, [sp, #8]\n+\tvmul.f64\td7, d15, d6\n+\tvmul.f64\td6, d14, d6\n+\tvmla.f64\td7, d1, d14\n+\tvmla.f64\td6, d0, d15\n+\tvstr\td2, [r6, #-8]\n \tadd\tr6, fp\n-\tvstr\td21, [r4, #-8]\n+\tvstr\td5, [r4, #-8]\n+\tvmul.f64\td5, d13, d4\n+\tvmul.f64\td4, d11, d4\n+\tvmla.f64\td5, d3, d11\n+\tvmla.f64\td4, d9, d13\n+\tvstr\td7, [r7, #-8]\n+\tvstr\td6, [r5, #-8]\n \tadd\tr4, fp\n-\tvstr\td29, [r7, #-8]\n \tadd\tr7, fp\n-\tvstr\td22, [r5, #-8]\n \tadd\tr5, fp\n-\tvstr\td20, [r0, #-8]\n-\tvstr\td19, [r1, #-8]\n-\tbne.n\t297c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x297c>\n-\tldrd\tr1, r0, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvstr\td5, [r9, #-8]\n+\tvstr\td4, [r0, #-8]\n+\tbne.n\t2e52 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2e52>\n+\tldr\tr0, [sp, #184]\t@ 0xb8\n+\tldr.w\tr9, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #300]\t@ 0x12c\n \tadd\tr9, r3\n-\tcmp\tr9, r0\n-\tbge.n\t2a70 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a70>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tcmp\tr9, r3\n+\tbge.n\t2f5e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f5e>\n+\tldr\tr3, [sp, #280]\t@ 0x118\n \tadd\tr9, r3\n-\tldr\tr3, [sp, #8]\n-\tadds\tr1, #1\n-\tcmp\tr1, r3\n-\tbne.w\t2924 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2924>\n-\tldrd\tr7, r3, [sp, #72]\t@ 0x48\n-\tldr\tr2, [sp, #20]\n+\tldr\tr3, [sp, #24]\n+\tadds\tr0, #1\n+\tcmp\tr0, r3\n+\tbne.w\t2df2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2df2>\n+\tldrd\tr3, r2, [sp, #132]\t@ 0x84\n+\tldr\tr7, [sp, #112]\t@ 0x70\n \tsubs\tr3, #1\n-\tldr.w\tlr, [sp, #88]\t@ 0x58\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr.w\tr8, [sp, #120]\t@ 0x78\n \tadd\tr2, r7\n-\tstr\tr2, [sp, #20]\n-\tldrd\tip, r4, [sp, #80]\t@ 0x50\n-\tadds\tr2, r3, #1\n-\tbne.w\t2912 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2912>\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tldrd\tr5, r8, [sp, #56]\t@ 0x38\n-\tldrd\tr1, r9, [sp, #64]\t@ 0x40\n-\tadd\tr5, r6\n-\tldr\tr3, [sp, #16]\n-\tsubs\tr1, r1, r6\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #16]\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldrd\tr5, r4, [sp, #144]\t@ 0x90\n+\tadds\tr0, r3, #1\n+\tbne.w\t2dde <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2dde>\n+\tmov\tr9, r1\n+\tldr\tr3, [sp, #32]\n+\tadd\tr8, r6\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tadd\tr4, r9\n+\tsubs\tr2, r3, #1\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tstr\tr2, [sp, #32]\n \tadds\tr2, #1\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #24]\n+\tadd\tr5, r3\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tadd\tr3, r6\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr9, r3\n-\tmov\tr3, lr\n-\tbeq.n\t2ac2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac2>\n-\tadd\tlr, r8\n-\tb.n\t28c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x28c8>\n-\tldr.w\tsl, [sp, #32]\n-\tmov\tr9, r0\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tr2, r3\n-\tbge.w\t24a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x24a>\n-\tldr.w\tr8, [sp, #12]\n-\tb.w\t118 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x118>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tcmp\tip, r5\n-\tldr\tr2, [sp, #24]\n-\tudiv\tr3, r2, r3\n-\tble.w\t28fc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x28fc>\n-\tb.n\t2a9e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a9e>\n-\tsubs\tr0, r6, r2\n-\tnegs\tr1, r6\n-\tcmp\tr6, r2\n-\tudiv\tr1, r0, r1\n-\tstr\tr1, [sp, #16]\n-\tbge.w\t3e8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3e8>\n-\tb.n\t2ac8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ac8>\n-\tadd\tsp, #276\t@ 0x114\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tsub.w\tr3, r3, r6\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tmov\tr3, r1\n+\tbeq.n\t2fb2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fb2>\n+\tmov\tr2, r1\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tb.n\t2d8c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d8c>\n+\tldr.w\tr9, [sp, #128]\t@ 0x80\n+\tldr.w\tsl, [sp, #72]\t@ 0x48\n+\tb.n\t2d22 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d22>\n+\tldr\tr1, [sp, #88]\t@ 0x58\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t2dd0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2dd0>\n+\tb.n\t2f84 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2f84>\n+\tadd\tsp, #484\t@ 0x1e4\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tand.w\tr3, r2, #3\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tcmp\tr3, #1\n-\tbeq.w\t3090 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3090>\n-\tcmp\tr3, #3\n-\tbeq.w\t3080 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3080>\n-\tmovs\tr3, #0\n-\tstrd\tr3, r3, [sp, #148]\t@ 0x94\n-\tb.w\t4e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4e>\n-\tcmp\tr2, #0\n-\tble.w\t7d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x7d0>\n-\tmov\tr1, r2\n-\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr2, r4, #536870912\t@ 0x20000000\n-\tsubs\tr3, #1\n-\tsubs\tr2, #1\n-\tadds\tr0, r1, r4\n-\tlsls\tr3, r3, #3\n-\tlsls\tr2, r2, #3\n-\tadd.w\tr1, lr, r0, lsl #3\n-\tadd.w\tip, sl, r3\n-\tadd.w\tr0, sl, r2\n-\tadd\tr3, r8\n-\tadd\tr2, r8\n-\tvldr\td20, [r0]\n-\tvldr\td19, [ip]\n-\tvldr\td22, [r3]\n-\tvldr\td17, [r2]\n-\tvsub.f64\td21, d20, d19\n-\tvadd.f64\td19, d19, d20\n-\tvsub.f64\td20, d22, d17\n-\tvadd.f64\td17, d17, d22\n-\tvmul.f64\td21, d21, d16\n-\tvstmia\tr0!, {d19}\n-\tcmp\tr0, r1\n-\tvmul.f64\td20, d20, d16\n-\tvstmia\tr2!, {d17}\n-\tvstmia\tr3!, {d21}\n-\tvstmia\tip!, {d20}\n-\tbne.n\t2b50 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2b50>\n-\tb.w\t7d0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x7d0>\n-\tldr\tr1, [sp, #164]\t@ 0xa4\n-\trsb\tr3, ip, #0\n-\tudiv\tr1, r1, r3\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tcmp\tr3, #0\n-\tble.w\t144 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x144>\n-\tb.w\t1f2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f2>\n-\tldr\tr2, [sp, #164]\t@ 0xa4\n-\tnegs\tr3, r7\n-\tcmp.w\tip, #0\n-\tudiv\tr3, r2, r3\n-\tble.w\t26e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x26e>\n-\tb.w\t3c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3c8>\n-\tudiv\tr0, r7, r5\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tcmp\tr2, r1\n-\tble.w\t728 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x728>\n-\tb.w\t804 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x804>\n-\tsubs\tr1, r0, r3\n-\tnegs\tr2, r0\n-\tcmp\tr0, r3\n-\tudiv\tr2, r1, r2\n-\tblt.w\t81a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x81a>\n-\tldr\tr0, [sp, #140]\t@ 0x8c\n-\tldr\tr3, [sp, #376]\t@ 0x178\n-\tmov.w\tr9, r0, lsl #3\n-\tcmp\tr3, #1\n-\tbeq.w\t6ec <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x6ec>\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n-\tmov\tfp, r0\n-\tldr\tr0, [sp, #120]\t@ 0x78\n-\trsb\tr5, ip, #0\n-\tadd\tr3, r9\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tadds\tr0, #1\n-\tstr\tr0, [sp, #16]\n-\tldr\tr0, [sp, #388]\t@ 0x184\n-\tvldr\td21, [r3, #8]\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tadd.w\tlr, r0, #1\n-\tmov\tr0, r5\n-\tmov\tr5, ip\n-\tvmul.f64\td21, d8, d21\n-\tldr.w\tip, [sp, #156]\t@ 0x9c\n-\tsubs\tr6, r1, r4\n-\tsubs\tr7, r4, r1\n-\tvldr\td23, [r3]\n-\tcmp\tr5, #0\n-\tstr.w\tlr, [sp, #12]\n-\tblt.w\t2d34 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d34>\n-\tudiv\tr4, r7, r5\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp\tr4, r1\n-\tblt.n\t2d0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d0c>\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tcmp\tr4, #0\n-\tble.n\t2d0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d0c>\n-\tldr\tr4, [sp, #28]\n-\tstrd\tr2, r1, [sp, #20]\n-\tadd.w\tlr, r4, r1\n-\tmov\tr1, r6\n-\tldr\tr4, [sp, #8]\n-\tstr.w\tr9, [sp, #32]\n-\tstr\tr3, [sp, #8]\n-\tldr\tr6, [sp, #148]\t@ 0x94\n-\tmov\tr2, lr\n-\tstrd\tr5, r4, [sp, #36]\t@ 0x24\n-\tstr.w\tlr, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #4]\n-\tldr\tr4, [sp, #28]\n-\tadd\tr3, r2\n-\tcmp\tr3, r4\n-\tbge.n\t2c62 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c62>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r4\n-\tldr\tr4, [sp, #200]\t@ 0xc8\n-\tcmp\tfp, r4\n-\tldr\tr4, [sp, #388]\t@ 0x184\n-\tbeq.w\t3018 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3018>\n-\tcmp\tr4, #0\n-\tble.n\t2cda <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cda>\n-\tlsls\tr3, r3, #3\n-\tlsls\tr4, r2, #3\n-\tldr.w\tr9, [sp, #148]\t@ 0x94\n-\tadd.w\tlr, sl, r4\n-\tadd.w\tr5, sl, r3\n-\tadd\tr4, r8\n-\tadd\tr3, r8\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvldr\td24, [r3, #-8]\n-\tadd.w\tr9, r9, #1\n-\tvldr\td19, [r4, #-8]\n-\tvldr\td22, [r5, #-8]\n-\tvldr\td20, [lr, #-8]\n-\tvsub.f64\td17, d19, d24\n-\tvadd.f64\td19, d19, d24\n-\tldr\tr2, [sp, #12]\n-\tvsub.f64\td24, d20, d22\n-\tvadd.f64\td20, d20, d22\n-\tcmp\tr9, r2\n-\tvnmul.f64\td22, d17, d21\n-\tvmul.f64\td17, d23, d17\n-\tvstr\td19, [r4, #-8]\n-\tadd\tr4, ip\n-\tvfma.f64\td22, d23, d24\n-\tvfma.f64\td17, d21, d24\n-\tvstr\td20, [lr, #-8]\n-\tadd\tlr, ip\n-\tvstr\td22, [r5, #-8]\n-\tadd\tr5, ip\n-\tvstr\td17, [r3, #-8]\n-\tadd\tr3, ip\n-\tbne.n\t2c86 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c86>\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr2, r3\n-\tbge.n\t2ce8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ce8>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #16]\n-\tadds\tr6, #1\n-\tcmp\tr6, r3\n-\tbne.n\t2c54 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c54>\n-\tldrd\tr5, r4, [sp, #36]\t@ 0x24\n-\tldr.w\tlr, [sp, #44]\t@ 0x2c\n-\tsubs\tr4, #1\n-\tadd\tlr, r5\n-\tadds\tr6, r4, #1\n-\tbne.n\t2c48 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c48>\n-\tmov\tr6, r1\n+\tnegs\tr1, r4\n+\tsub.w\tr0, r4, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r8\n+\tstr\tr0, [sp, #136]\t@ 0x88\n+\tbge.w\t1f68 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f68>\n+\tb.w\t23c8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23c8>\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tble.w\t27b2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x27b2>\n+\tb.n\t2a48 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2a48>\n+\tldr\tr1, [sp, #596]\t@ 0x254\n+\tmov\tfp, r9\n+\tldr.w\tr9, [sp, #356]\t@ 0x164\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr1, [sp, #352]\t@ 0x160\n+\tstr\tr2, [sp, #20]\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr7, [sp, #96]\t@ 0x60\n+\tstr\tr2, [sp, #104]\t@ 0x68\n \tldr\tr2, [sp, #20]\n-\tldr\tr3, [sp, #8]\n-\tldr.w\tr9, [sp, #32]\n-\tldr\tr1, [sp, #24]\n-\tldr\tr4, [sp, #140]\t@ 0x8c\n-\tsubs\tr2, #1\n-\tadd\tr3, r9\n-\tadd\tfp, r4\n-\tldr\tr4, [sp, #136]\t@ 0x88\n-\tadd\tr1, r4\n-\tadd\tr6, r4\n-\tsubs\tr7, r7, r4\n-\tadds\tr4, r2, #1\n-\tbeq.w\t81a <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x81a>\n-\tvldr\td21, [r3, #8]\n-\tcmp\tr5, #0\n-\tvldr\td23, [r3]\n-\tvmul.f64\td21, d8, d21\n-\tbge.w\t2c22 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c22>\n-\tudiv\tr4, r6, r0\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tcmp\tr4, r1\n-\tble.w\t2c2e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c2e>\n-\tb.n\t2d0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d0c>\n-\tsubs\tr2, r4, r0\n-\tnegs\tr3, r4\n-\tcmp\tr4, r0\n-\tudiv\tip, r2, r3\n-\tbge.w\t1c1e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1c1e>\n-\tb.w\t200e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x200e>\n-\tudiv\tr0, r7, lr\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #0]\n+\tldr\tr6, [sp, #140]\t@ 0x8c\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tldr\tr7, [sp, #140]\t@ 0x8c\n+\tcmp\tr3, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr3, r3, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr1, r2, r3\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr1, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr1, r1, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr5, r2, r1\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr5, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr5, r5, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr0, r2, r5\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tcmp\tr0, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr0, r0, r2\n+\tldr\tr2, [sp, #0]\n+\tadds\tr4, r2, r0\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n \tcmp\tr4, r2\n-\tble.w\t23d4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x23d4>\n-\tb.n\t266e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x266e>\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tmov\tr9, sl\n-\tvneg.f64\td25, d17\n-\tmov\tsl, r8\n-\tadds\tr4, #1\n-\tldr\tr2, [sp, #28]\n-\tstr\tr4, [sp, #8]\n-\tldr.w\tr8, [sp, #156]\t@ 0x9c\n-\tldr\tr4, [sp, #388]\t@ 0x184\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #60]\t@ 0x3c\n-\tldr\tr4, [sp, #152]\t@ 0x98\n-\tmov\tfp, r2\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tstrd\tr0, r3, [sp, #64]\t@ 0x40\n-\tstrd\tr1, r2, [sp, #72]\t@ 0x48\n-\tldr\tr3, [sp, #4]\n-\tadd.w\tr0, r3, fp\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr0, r3\n-\tbge.n\t2d9c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d9c>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr2, r3, r0\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr2, r3\n-\tbge.n\t2daa <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2daa>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr5, r3, r2\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr5, r3\n-\tbge.n\t2db8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2db8>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr1, r3, r5\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr1, r3\n-\tbge.n\t2dc6 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2dc6>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr4, r3, r1\n-\tldr\tr3, [sp, #28]\n-\tcmp\tr4, r3\n-\tbge.n\t2dd4 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2dd4>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #4]\n-\tldr\tr6, [sp, #28]\n-\tadd\tr3, r4\n-\tcmp\tr3, r6\n-\tbge.n\t2de2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2de2>\n-\tldr\tr6, [sp, #92]\t@ 0x5c\n-\tadd\tr3, r6\n-\tldr\tr6, [sp, #4]\n-\tldr\tr7, [sp, #28]\n-\tadd\tr6, r3\n+\titt\tlt\n+\tldrlt\tr2, [sp, #280]\t@ 0x118\n+\taddlt\tr4, r4, r2\n+\tldr\tr2, [sp, #0]\n+\tadd\tr2, r4\n+\tcmp\tr2, r6\n+\titt\tlt\n+\tldrlt\tr6, [sp, #280]\t@ 0x118\n+\taddlt\tr2, r2, r6\n+\tldr\tr6, [sp, #0]\n+\tadd\tr6, r2\n \tcmp\tr6, r7\n-\tbge.n\t2df0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2df0>\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #388]\t@ 0x184\n+\titt\tlt\n+\tldrlt\tr7, [sp, #280]\t@ 0x118\n+\taddlt\tr6, r6, r7\n+\tldr\tr7, [sp, #596]\t@ 0x254\n \tcmp\tr7, #0\n-\tble.w\t2fe2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2fe2>\n+\tble.w\t3268 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3268>\n+\tldr\tr7, [sp, #20]\n \tlsls\tr5, r5, #3\n+\tstr\tr5, [sp, #24]\n \tlsls\tr3, r3, #3\n-\tlsls\tr0, r0, #3\n-\tlsls\tr4, r4, #3\n-\tstr\tr4, [sp, #20]\n \tlsls\tr6, r6, #3\n-\tstr\tr6, [sp, #24]\n-\tadd.w\tr6, r9, r3\n-\tadd\tr3, sl\n-\tstr\tr3, [sp, #16]\n-\tadd.w\tr3, r9, r0\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr3, r9, r5\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, sl, r5\n-\tldr\tr5, [sp, #20]\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tmov.w\tr4, fp, lsl #3\n-\tadd.w\tr3, r9, r5\n-\tstr\tr3, [sp, #32]\n+\tstr\tr6, [sp, #28]\n+\tlsls\tr5, r7, #3\n+\tadd.w\tr6, sl, r3\n+\tadd.w\tr8, sl, r5\n+\tadd\tr5, fp\n+\tstr\tr5, [sp, #32]\n+\tadd\tr3, fp\n+\tldr\tr5, [sp, #24]\n+\tlsls\tr4, r4, #3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tlsls\tr0, r0, #3\n \tadd.w\tr3, sl, r5\n \tldr\tr5, [sp, #24]\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tlsls\tr1, r1, #3\n+\tadd.w\tr3, fp, r5\n+\tldr\tr5, [sp, #28]\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tlsls\tr2, r2, #3\n-\tstr\tr6, [sp, #12]\n-\tadd.w\tr6, r9, r5\n-\tstr\tr6, [sp, #20]\n-\tadd.w\tr6, sl, r5\n-\tldr\tr5, [sp, #152]\t@ 0x98\n-\tadd.w\tlr, r9, r4\n-\tadd.w\tip, r9, r1\n-\tadd.w\tr7, r9, r2\n-\tadd\tr4, sl\n-\tadd\tr2, sl\n-\tadd\tr1, sl\n-\tadd\tr0, sl\n-\tstr\tr5, [sp, #24]\n-\tstr.w\tfp, [sp, #80]\t@ 0x50\n-\tmov\tfp, r6\n-\tldr\tr5, [sp, #48]\t@ 0x30\n-\tstr.w\tr9, [sp, #48]\t@ 0x30\n-\tldr.w\tr9, [sp, #56]\t@ 0x38\n-\tstr.w\tsl, [sp, #56]\t@ 0x38\n-\tmov\tsl, r3\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #12]\n-\tvldr\td21, [ip, #-8]\n-\tvldr\td26, [r1, #-8]\n-\tvldr\td23, [lr, #-8]\n-\tvldr\td19, [r4, #-8]\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #16]\n-\tvsub.f64\td22, d23, d21\n-\tvldr\td27, [r3, #-8]\n-\tvadd.f64\td23, d23, d21\n-\tvldr\td28, [r7, #-8]\n-\tvsub.f64\td21, d19, d26\n-\tvldr\td20, [r6, #-8]\n-\tvadd.f64\td19, d19, d26\n-\tvldr\td24, [r2, #-8]\n-\tvmov.f64\td26, d22\n-\tvsub.f64\td29, d28, d27\n-\tvadd.f64\td28, d28, d27\n-\tldr\tr3, [sp, #24]\n-\tvsub.f64\td30, d20, d24\n-\tvadd.f64\td20, d20, d24\n-\tvmov.f64\td24, d21\n-\tadds\tr3, #1\n-\tvfma.f64\td24, d17, d29\n-\tvfma.f64\td21, d29, d25\n+\tadd.w\tr3, sl, r4\n \tstr\tr3, [sp, #24]\n-\tvadd.f64\td29, d23, d28\n-\tvadd.f64\td27, d19, d20\n-\tvfma.f64\td26, d30, d25\n-\tvfma.f64\td22, d17, d30\n-\tvsub.f64\td19, d19, d20\n-\tldr\tr3, [sp, #12]\n-\tvsub.f64\td23, d23, d28\n-\tvstr\td29, [lr, #-8]\n-\tvstr\td27, [r4, #-8]\n-\tadd\tlr, r8\n-\tvstr\td19, [r1, #-8]\n-\tadd\tr4, r8\n-\tvstr\td24, [r6, #-8]\n-\tadd\tr6, r8\n-\tvstr\td21, [r2, #-8]\n-\tadd\tr1, r8\n+\tadd.w\tr3, sl, r5\n+\tstr\tr3, [sp, #28]\n+\tadd.w\tr3, fp, r5\n+\tadd.w\tlr, sl, r0\n+\tldr\tr5, [sp, #352]\t@ 0x160\n+\tadd.w\tip, sl, r1\n+\tadd.w\tr7, sl, r2\n+\tadd\tr0, fp\n+\tadd\tr2, fp\n+\tadd\tr1, fp\n+\tadd\tr4, fp\n+\tstr.w\tsl, [sp, #112]\t@ 0x70\n+\tldr.w\tsl, [sp, #64]\t@ 0x40\n+\tstr.w\tfp, [sp, #64]\t@ 0x40\n+\tmov\tfp, r3\n+\tstr\tr5, [sp, #40]\t@ 0x28\n+\tldr\tr5, [sp, #32]\n+\tstr\tr2, [sp, #32]\n \tldr\tr2, [sp, #32]\n-\tvstr\td23, [ip, #-8]\n-\tadd\tip, r8\n-\tvstr\td26, [r7, #-8]\n-\tadd\tr7, r8\n-\tvstr\td22, [r3, #-8]\n+\tvldr\td1, [r1, #-8]\n+\tvldr\td0, [ip, #-8]\n+\tvldr\td7, [r7, #-8]\n+\tvldr\td4, [r2, #-8]\n+\tvldr\td9, [r5, #-8]\n+\tvsub.f64\td3, d0, d7\n+\tvldr\td10, [r0, #-8]\n+\tvsub.f64\td6, d1, d4\n+\tvldr\td8, [lr, #-8]\n+\tvldr\td5, [r8, #-8]\n+\tvadd.f64\td4, d1, d4\n+\tvadd.f64\td7, d0, d7\n+\tvadd.f64\td1, d9, d10\n+\tvsub.f64\td0, d9, d10\n+\tvmul.f64\td3, d3, d15\n+\tvadd.f64\td2, d5, d8\n+\tvmul.f64\td6, d6, d15\n+\tvsub.f64\td5, d5, d8\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tvldr\td26, [r2, #-8]\n-\tldr\tr2, [sp, #20]\n-\tvldr\td23, [r9, #-8]\n-\tvldr\td24, [r3, #-8]\n-\tvldr\td31, [sl, #-8]\n-\tvldr\td27, [r2, #-8]\n-\tvldr\td20, [r5, #-8]\n-\tvldr\td19, [r0, #-8]\n-\tvldr\td28, [fp, #-8]\n-\tvadd.f64\td30, d26, d27\n-\tvsub.f64\td22, d20, d24\n-\tvadd.f64\td20, d20, d24\n-\tvsub.f64\td21, d19, d23\n-\tvadd.f64\td19, d19, d23\n-\tvadd.f64\td7, d31, d28\n-\tstr\tr6, [sp, #44]\t@ 0x2c\n-\tldr\tr6, [sp, #16]\n-\tvsub.f64\td24, d22, d28\n-\tvsub.f64\td22, d22, d31\n-\tvadd.f64\td29, d30, d19\n-\tvsub.f64\td19, d19, d30\n-\tvsub.f64\td30, d20, d7\n-\tvadd.f64\td20, d20, d7\n-\tvsub.f64\td23, d21, d26\n-\tvsub.f64\td21, d21, d27\n-\tvadd.f64\td24, d24, d31\n-\tvadd.f64\td22, d22, d28\n-\tvstr\td29, [r0, #-8]\n-\tadd\tr6, r8\n-\tvstr\td30, [r5, #-8]\n-\tadd\tr0, r8\n-\tvstr\td20, [r2, #-8]\n-\tvadd.f64\td23, d23, d27\n-\tldr\tr2, [sp, #12]\n-\tvadd.f64\td21, d21, d26\n-\tvstr\td24, [r3, #-8]\n-\tadd\tr3, r8\n-\tadd\tr2, r8\n-\tstr\tr2, [sp, #12]\n-\tldr\tr2, [sp, #32]\n-\tadd\tr5, r8\n+\tadds\tr3, #1\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, r2, r8\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #24]\n-\tvstr\td22, [r2, #-8]\n-\tldr\tr2, [sp, #20]\n-\tvstr\td19, [fp, #-8]\n-\tadd\tfp, r8\n-\tadd\tr2, r8\n-\tstr\tr2, [sp, #20]\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tvstr\td23, [r9, #-8]\n-\tadd\tr9, r8\n-\tvstr\td21, [sl, #-8]\n+\tvadd.f64\td8, d2, d7\n+\tvsub.f64\td7, d2, d7\n+\tvadd.f64\td2, d1, d4\n+\tvsub.f64\td1, d1, d4\n+\tvsub.f64\td4, d5, d6\n+\tvadd.f64\td6, d5, d6\n+\tvadd.f64\td5, d3, d0\n+\tvsub.f64\td0, d0, d3\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstr\td2, [r5, #-8]\n+\tadd\tr5, r9\n+\tvstr\td1, [r0, #-8]\n+\tadd\tr0, r9\n+\tvstr\td5, [r1, #-8]\n+\tadd\tr1, r9\n+\tvstr\td0, [r2, #-8]\n+\tldr\tr2, [sp, #24]\n+\tvstr\td8, [r8, #-8]\n+\tadd\tr8, r9\n+\tvstr\td7, [lr, #-8]\n+\tadd\tlr, r9\n+\tvstr\td4, [ip, #-8]\n+\tadd\tip, r9\n+\tvstr\td6, [r7, #-8]\n+\tadd\tr7, r9\n+\tvldr\td2, [r3, #-8]\n+\tvldr\td11, [r2, #-8]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #28]\n+\tvldr\td8, [sl, #-8]\n+\tvldr\td3, [r4, #-8]\n+\tvldr\td4, [fp, #-8]\n+\tvldr\td6, [r3, #-8]\n+\tvldr\td10, [r2, #-8]\n+\tvldr\td7, [r6, #-8]\n+\tvsub.f64\td0, d6, d8\n+\tvadd.f64\td6, d6, d8\n+\tvadd.f64\td1, d11, d10\n+\tvsub.f64\td5, d7, d2\n+\tvadd.f64\td7, d7, d2\n+\tvadd.f64\td2, d3, d4\n+\tvsub.f64\td9, d0, d11\n+\tvsub.f64\td0, d0, d10\n+\tvadd.f64\td13, d1, d6\n+\tvsub.f64\td1, d6, d1\n+\tvsub.f64\td8, d5, d4\n+\tvsub.f64\td5, d5, d3\n+\tvsub.f64\td6, d7, d2\n+\tvadd.f64\td7, d7, d2\n+\tvadd.f64\td9, d9, d10\n+\tvadd.f64\td0, d0, d11\n+\tvstr\td13, [r3, #-8]\n+\tvadd.f64\td3, d8, d3\n+\tvadd.f64\td5, d5, d4\n+\tvstr\td6, [r6, #-8]\n+\tadd\tr6, r9\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstr\td7, [r2, #-8]\n+\tldr\tr2, [sp, #24]\n+\tvstr\td1, [fp, #-8]\n+\tadd\tfp, r9\n+\tvstr\td3, [r3, #-8]\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tvstr\td5, [r2, #-8]\n+\tldr\tr2, [sp, #32]\n+\tvstr\td9, [sl, #-8]\n+\tadd\tsl, r9\n+\tadd\tr2, r9\n+\tstr\tr2, [sp, #32]\n+\tldr\tr2, [sp, #24]\n+\tvstr\td0, [r4, #-8]\n+\tadd\tr4, r9\n+\tadd.w\tr3, r2, r9\n+\tldr\tr2, [sp, #28]\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tadd\tr2, r9\n+\tstr\tr2, [sp, #28]\n+\tadd\tr3, r9\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r2\n-\tadd\tsl, r8\n-\tstr\tr6, [sp, #16]\n-\tbne.w\t2e72 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2e72>\n-\tldr.w\tfp, [sp, #80]\t@ 0x50\n-\tldr.w\tr9, [sp, #48]\t@ 0x30\n-\tldr.w\tsl, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #28]\n-\tcmp\tfp, r3\n-\tbge.n\t2ff0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2ff0>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tbne.w\t30fe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x30fe>\n+\tldr.w\tsl, [sp, #112]\t@ 0x70\n+\tldr.w\tfp, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #20]\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #20]\n+\tcmp\tr3, r2\n+\tbge.n\t327c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x327c>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr2, [sp, #8]\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tcmp\tr3, r2\n-\tbne.w\t2d8c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d8c>\n-\tldrd\tr0, r3, [sp, #64]\t@ 0x40\n-\tldrd\tr1, r2, [sp, #72]\t@ 0x48\n+\tbne.w\t3020 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3020>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr7, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tsubs\tr3, #1\n+\tldr.w\tr8, [sp, #80]\t@ 0x50\n+\tadds\tr4, r3, #1\n+\tadd\tr2, r7\n+\tbne.w\t3010 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3010>\n+\tmov\tr9, fp\n+\tb.w\t1f0c <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1f0c>\n+\tcmp\tr1, #0\n+\tble.w\t2c92 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c92>\n+\tmov.w\tr1, lr, lsl #3\n+\tlsls\tr0, r4, #3\n+\tldr.w\tfp, [sp, #348]\t@ 0x15c\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tlr, sl, r1\n+\tadd\tr0, r9\n+\tadd\tr1, r9\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\td5, [lr, #-8]\n+\tadd.w\tfp, fp, #1\n+\tvldr\td6, [r8, #-8]\n+\tvldr\td7, [r1, #-8]\n+\tvldr\td3, [r0, #-8]\n+\tvsub.f64\td4, d6, d5\n+\tvadd.f64\td6, d6, d5\n+\tldr\tr3, [sp, #24]\n+\tvsub.f64\td5, d7, d3\n+\tvadd.f64\td7, d7, d3\n+\tcmp\tfp, r3\n+\tvmul.f64\td4, d4, d12\n+\tvstr\td6, [r8, #-8]\n+\tadd\tr8, r5\n+\tvmul.f64\td5, d5, d12\n+\tvstr\td7, [r0, #-8]\n+\tadd\tr0, r5\n+\tvstr\td4, [r1, #-8]\n+\tadd\tr1, r5\n+\tvstr\td5, [lr, #-8]\n+\tadd\tlr, r5\n+\tbne.n\t32c2 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x32c2>\n+\tb.n\t2c90 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2c90>\n+\tmov\tr0, r2\n+\tldr\tr1, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #32]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #32]\n+\tcmp\tr3, r4\n+\tble.w\t2bea <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2bea>\n+\tb.n\t2cbe <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cbe>\n+\tldr\tr3, [sp, #592]\t@ 0x250\n \tsubs\tr3, #1\n-\tadds\tr6, r3, #1\n-\tadd\tr2, r1\n-\tbne.w\t2d7e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2d7e>\n-\tmov\tr8, sl\n-\tmov\tsl, r9\n-\tb.w\t1bfc <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x1bfc>\n-\tcmp\tr4, #0\n-\tble.w\t2cda <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cda>\n-\tlsls\tr3, r3, #3\n-\tlsls\tr4, r2, #3\n-\tldr.w\tr9, [sp, #148]\t@ 0x94\n-\tadd.w\tlr, sl, r4\n-\tadd.w\tr5, sl, r3\n-\tadd\tr4, r8\n-\tadd\tr3, r8\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvldr\td20, [r5, #-8]\n-\tadd.w\tr9, r9, #1\n-\tvldr\td19, [lr, #-8]\n-\tvldr\td17, [r3, #-8]\n-\tvldr\td24, [r4, #-8]\n-\tvsub.f64\td22, d19, d20\n-\tvadd.f64\td19, d19, d20\n-\tldr\tr2, [sp, #12]\n-\tvsub.f64\td20, d17, d24\n-\tvadd.f64\td17, d17, d24\n-\tcmp\tr9, r2\n-\tvmul.f64\td22, d22, d16\n-\tvstr\td19, [lr, #-8]\n-\tadd\tlr, ip\n-\tvmul.f64\td20, d20, d16\n-\tvstr\td17, [r4, #-8]\n-\tadd\tr4, ip\n-\tvstr\td22, [r3, #-8]\n-\tadd\tr3, ip\n-\tvstr\td20, [r5, #-8]\n-\tadd\tr5, ip\n-\tbne.n\t3034 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x3034>\n-\tb.n\t2cd8 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x2cd8>\n-\tldr\tr3, [sp, #384]\t@ 0x180\n-\tsubs\tr3, #3\n-\tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tb.w\t4e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4e>\n-\tsubs\tr3, r2, #1\n \tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr3, [sp, #368]\t@ 0x170\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tb.w\t4e <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x4e>\n+\tstr\tr3, [sp, #352]\t@ 0x160\n+\tb.w\t64 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0+0x64>\n \tudf\t#255\t@ 0xff\n+\tnop\n \n-000030a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>:\n+00003338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>:\n __gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3832]\t@ 0xef8\n-\tsub\tsp, #228\t@ 0xe4\n+\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n+\tsub\tsp, #244\t@ 0xf4\n \tmov\tr5, r3\n-\tstrd\tr1, r0, [sp, #48]\t@ 0x30\n+\tvldr\td14, [pc, #756]\t@ 3648 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x310>\n+\tstr\tr1, [sp, #60]\t@ 0x3c\n+\tldrd\tr4, r1, [sp, #348]\t@ 0x15c\n+\tstr\tr0, [sp, #72]\t@ 0x48\n \tmovs\tr0, #3\n-\tldrd\tr4, r1, [sp, #268]\t@ 0x10c\n-\tstr\tr2, [sp, #116]\t@ 0x74\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n+\tmov\tr6, r0\n+\tmov\tr1, r6\n+\tstr\tr0, [sp, #192]\t@ 0xc0\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n \tmovw\tr3, #21846\t@ 0x5556\n \tmovt\tr3, #21845\t@ 0x5555\n-\tsubs\tr2, r0, r4\n-\tstr\tr0, [sp, #152]\t@ 0x98\n-\tmul.w\tr2, r5, r2\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tsdiv\tr2, r4, r0\n-\tmov\tr1, r2\n-\tstr\tr2, [sp, #104]\t@ 0x68\n-\tsmull\tr2, r3, r3, r2\n-\tmov\tr2, r1\n-\tsub.w\tr3, r3, r1, asr #31\n+\tvldr\ts15, [sp, #360]\t@ 0x168\n+\tvldr\td6, [pc, #720]\t@ 3650 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x318>\n+\tmov\tlr, r0\n+\tsmull\tr2, r3, r3, r0\n+\tsubs\tr2, r6, r4\n+\tvcvt.f64.s32\td7, s15\n \tmul.w\tr2, r5, r2\n-\tstr\tr2, [sp, #108]\t@ 0x6c\n+\tsub.w\tr3, r3, r0, asr #31\n+\tstr\tr2, [sp, #88]\t@ 0x58\n+\tmul.w\tr2, r5, r4\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tmul.w\tr2, r5, r0\n+\tstr\tr2, [sp, #124]\t@ 0x7c\n \tadd.w\tr3, r3, r3, lsl #1\n-\tldr\tr2, [sp, #280]\t@ 0x118\n-\tsubs\tr3, r1, r3\n-\tmul.w\tr1, r5, r4\n+\tldr\tr2, [sp, #360]\t@ 0x168\n+\tsubs\tr3, r0, r3\n+\tvstr\td7, [sp, #144]\t@ 0x90\n \tadds\tr2, #1\n-\tstr\tr1, [sp, #44]\t@ 0x2c\n-\tbne.n\t3104 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x64>\n-\trsb\tr3, r3, #3\n+\tldr\tr2, [sp, #356]\t@ 0x164\n+\tit\teq\n+\trsbeq\tr3, r3, #3\n \tcmp\tr3, #2\n-\tldr\tr3, [sp, #272]\t@ 0x110\n-\tvldr\td16, [pc, #628]\t@ 3380 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2e0>\n+\tldr\tr3, [sp, #352]\t@ 0x160\n \tadd.w\tr3, r3, #1\n-\tvldr\td17, [pc, #628]\t@ 3388 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2e8>\n-\tldr\tr2, [sp, #276]\t@ 0x114\n-\tadd.w\tr3, r3, r3, lsr #31\n-\tvldr\ts15, [sp, #280]\t@ 0x118\n-\tvseleq.f64\td16, d16, d17\n+\tit\teq\n+\tvmoveq.f64\td14, d6\n \tsubs\tr2, #1\n+\tadd.w\tr3, r3, r3, lsr #31\n \tmov.w\tr1, r3, asr #1\n-\tldr\tr3, [sp, #276]\t@ 0x114\n-\tvcvt.f64.s32\td28, s15\n-\tstr\tr1, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tstr\tr1, [sp, #196]\t@ 0xc4\n \tadd.w\tr3, r3, #126\t@ 0x7e\n \tit\tpl\n \tmovpl\tr3, r2\n-\tldr\tr2, [sp, #276]\t@ 0x114\n+\tldr\tr2, [sp, #356]\t@ 0x164\n \tasrs\tr3, r3, #7\n \tadds\tr2, #126\t@ 0x7e\n-\tblt.w\t44f2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1452>\n+\tblt.w\t49ba <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1682>\n \tsubs\tr4, #1\n-\tadds\tr6, r3, #2\n-\tvneg.f64\td23, d16\n-\tmovs\tr0, #1\n-\tstr\tr0, [sp, #60]\t@ 0x3c\n+\tstr\tr0, [sp, #112]\t@ 0x70\n \tmul.w\tr2, r5, r4\n-\tadds\tr5, r1, r0\n+\tadds\tr5, r3, #2\n+\tmovs\tr3, #1\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tadds\tr6, r1, r3\n+\tmov\tr8, r3\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tnegs\tr1, r2\n+\tstr\tr1, [sp, #152]\t@ 0x98\n+\tmov\tr7, r8\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tsubs\tr3, #8\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tlsls\tr1, r1, #3\n \tstr\tr2, [sp, #100]\t@ 0x64\n-\tmov\tr3, r2\n-\tstrd\tr5, r6, [sp, #172]\t@ 0xac\n-\tnegs\tr2, r2\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tlsrs\tr3, r3, #31\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tldr\tr3, [sp, #264]\t@ 0x108\n-\tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tldr\tr3, [sp, #276]\t@ 0x114\n+\tstr\tr1, [sp, #168]\t@ 0xa8\n+\tlsrs\tr2, r2, #31\n+\tstr\tr5, [sp, #208]\t@ 0xd0\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n \tcmp\tr3, #128\t@ 0x80\n \tit\tle\n \tmovle\tr4, #0\n-\tble.n\t3182 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe2>\n+\tble.n\t3436 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xfe>\n \tcmp\tr3, #255\t@ 0xff\n-\tble.w\t44f8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1458>\n-\tsub.w\tr4, r3, #128\t@ 0x80\n-\tmovs\tr3, #128\t@ 0x80\n-\tstr\tr3, [sp, #276]\t@ 0x114\n-\tldr\tr3, [sp, #272]\t@ 0x110\n+\tittte\tle\n+\tmovle\tr2, r3\n+\tasrle\tr3, r3, #1\n+\taddle\tr3, #1\n+\tsubgt.w\tr4, r3, #128\t@ 0x80\n+\titet\tle\n+\tbicle.w\tr3, r3, #1\n+\tmovgt\tr3, #128\t@ 0x80\n+\tsuble\tr4, r2, r3\n+\tstr\tr3, [sp, #356]\t@ 0x164\n+\tldr\tr3, [sp, #352]\t@ 0x160\n \tcmp\tr3, #0\n \tmov.w\tr3, #1\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tble.w\t3654 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5b4>\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tstrd\tr3, r0, [sp, #28]\n-\tadd.w\tsl, r2, r3\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tstr.w\tsl, [sp]\n-\tldr.w\tip, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #136]\t@ 0x88\n-\tldr.w\tfp, [sp, #48]\t@ 0x30\n-\tldr.w\tsl, [sp, #52]\t@ 0x34\n-\tstr\tr4, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tble.w\t3920 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5e8>\n \tldr\tr2, [sp, #112]\t@ 0x70\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tmov\tr5, r2\n-\tadd.w\tr2, r2, r2, lsl #1\n-\tstr\tr2, [sp, #112]\t@ 0x70\n-\tsdiv\tr4, r1, r2\n-\tsub.w\tr9, r4, r1\n-\tadds.w\tr6, r4, r4, lsl #1\n-\tbmi.w\t44de <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x143e>\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tldr\tr1, [sp, #160]\t@ 0xa0\n-\tudiv\tr2, r2, r6\n-\tcmp\tr1, #0\n-\tbne.w\t32f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x256>\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tcmp\tr1, #0\n-\tble.w\t32f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x256>\n-\tldr\tr1, [sp, #264]\t@ 0x108\n-\tvmov.f64\td25, #96\t@ 0x3f000000 0.5\n-\tcmp\tr1, #1\n-\tmov\tr1, ip\n-\tbne.w\t34fc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x45c>\n-\tsub.w\tr7, sl, #8\n-\tstrd\tr7, r0, [sp, #4]\n-\tmov\tlr, r1\n-\tmov.w\tr8, #1\n-\tstrd\tr4, r6, [sp, #12]\n-\tstrd\tr2, r5, [sp, #20]\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tadd.w\tr7, r9, lr\n-\tcmp\tip, r7\n-\tble.n\t3214 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x174>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r2\n-\tadd.w\tr2, r9, r7\n-\tcmp\tip, r2\n-\tble.n\t3220 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x180>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #276]\t@ 0x114\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tadd.w\tfp, r2, r3\n+\tstr\tr4, [sp, #52]\t@ 0x34\n+\tstr.w\tfp, [sp, #4]\n+\tldr\tr6, [sp, #124]\t@ 0x7c\n+\tldr.w\tr8, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #168]\t@ 0xa8\n+\tldr.w\tsl, [sp, #60]\t@ 0x3c\n+\tldr.w\tfp, [sp, #72]\t@ 0x48\n+\tvldr\td13, [sp, #144]\t@ 0x90\n+\tstr\tr3, [sp, #32]\n+\tstr\tr7, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr7, [sp, #56]\t@ 0x38\n+\tstr\tr3, [sp, #16]\n+\tadd.w\tr3, r3, r3, lsl #1\n+\tmov\tr0, r7\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r7\n+\tmov\tr5, r0\n+\tadds.w\tr7, r0, r0, lsl #1\n+\tstr\tr3, [sp, #8]\n+\tbmi.w\t38f4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5bc>\n+\tldr\tr0, [sp, #100]\t@ 0x64\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tmov\tr3, r0\n+\tcmp\tr2, #0\n+\tbne.w\t35b4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x27c>\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tcmp\tr2, #0\n+\tble.w\t35b4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x27c>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tcmp\tr2, #1\n+\tmov\tr2, r8\n+\tit\teq\n+\tmoveq\tr0, r4\n+\tbne.w\t37ba <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x482>\n+\tmov\tlr, r2\n+\tmov.w\tr9, #1\n+\tstr\tr6, [sp, #12]\n+\tstrd\tr5, r7, [sp, #20]\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #8]\n+\tadd.w\tip, r3, lr\n+\tcmp\tr8, ip\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #8]\n+\tadd\tr3, ip\n+\tcmp\tr8, r3\n+\titt\tgt\n+\tldrgt\tr1, [sp, #56]\t@ 0x38\n+\taddgt\tr3, r3, r1\n+\tldr\tr1, [sp, #356]\t@ 0x164\n \tcmp\tr1, #0\n-\tble.n\t32cc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x22c>\n-\tadd.w\tr4, r7, #536870912\t@ 0x20000000\n-\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n-\tadd.w\tr0, lr, #536870912\t@ 0x20000000\n-\tadd\tr7, r1\n-\tsubs\tr2, #1\n-\tldr\tr1, [sp, #4]\n+\tble.n\t358c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x254>\n+\tadd.w\tr5, ip, #536870912\t@ 0x20000000\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr4, lr, #536870912\t@ 0x20000000\n+\tadd\tip, r1\n+\tsubs\tr3, #1\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tsubs\tr5, #1\n \tsubs\tr4, #1\n-\tsubs\tr0, #1\n-\tlsls\tr2, r2, #3\n+\tlsls\tr3, r3, #3\n+\tlsls\tr5, r5, #3\n \tlsls\tr4, r4, #3\n-\tlsls\tr0, r0, #3\n-\tadd.w\tr7, r1, r7, lsl #3\n-\tadd.w\tr6, sl, r2\n-\tadd.w\tr1, sl, r4\n-\tadd.w\tr5, sl, r0\n-\tadd\tr4, fp\n-\tadd\tr2, fp\n-\tadd\tr0, fp\n-\tvldr\td24, [r6]\n-\tvldr\td17, [r1]\n-\tvldr\td20, [r2]\n-\tvldr\td18, [r4]\n-\tvldr\td19, [r5]\n-\tvadd.f64\td22, d24, d17\n-\tvldr\td21, [r0]\n-\tvsub.f64\td17, d17, d24\n-\tvadd.f64\td24, d20, d18\n-\tvsub.f64\td18, d18, d20\n-\tvmov.f64\td20, d19\n-\tvfms.f64\td20, d22, d25\n-\tvadd.f64\td22, d19, d22\n-\tvmov.f64\td19, d21\n-\tvfms.f64\td19, d24, d25\n-\tvadd.f64\td21, d21, d24\n-\tvstmia\tr5!, {d22}\n-\tvstmia\tr0!, {d21}\n-\tvmov.f64\td24, d20\n-\tvfma.f64\td20, d16, d18\n-\tvfma.f64\td24, d18, d23\n-\tvmov.f64\td18, d19\n-\tvfma.f64\td19, d17, d23\n-\tvfma.f64\td18, d16, d17\n-\tvstmia\tr1!, {d24}\n-\tcmp\tr1, r7\n-\tvstmia\tr6!, {d20}\n-\tvstmia\tr4!, {d18}\n-\tvstmia\tr2!, {d19}\n-\tbne.n\t3258 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1b8>\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadd\tlr, r2\n-\tcmp\tlr, ip\n-\tbge.n\t32d8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x238>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tlr, r2\n-\tldr\tr2, [sp, #0]\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr8, r2\n-\tbne.n\t3208 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x168>\n-\tldrd\tr2, r5, [sp, #20]\n-\tldrd\tr4, r6, [sp, #12]\n-\tsubs\tr2, #1\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tadds\tr0, r2, #1\n-\tadd\tr1, r6\n-\tbne.n\t31f8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x158>\n-\tldr\tr0, [sp, #8]\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tcmp\tr2, #3\n-\tbeq.w\t360c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x56c>\n-\tlsls\tr1, r5, #1\n-\tsubs\tr2, r4, r0\n-\tcmp\tr0, #0\n-\tblt.w\t44cc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x142c>\n-\tsubs\tr4, r2, r0\n-\tcmp\tr0, r2\n-\tudiv\tr7, r4, r0\n-\tbgt.w\t3642 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5a2>\n-\tldr\tr2, [sp, #264]\t@ 0x108\n-\tcmp\tr2, #1\n-\tbne.w\t3e66 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xdc6>\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tlsls\tr2, r1, #3\n-\tlsls\tr1, r1, #4\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tstr\tr1, [sp, #56]\t@ 0x38\n-\tmov\tr1, r2\n-\tadds\tr2, r4, r2\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tadd.w\tr8, r2, r1\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tsubs\tr5, r4, r0\n-\tsubs\tr1, r0, r4\n-\tmov\tr4, r8\n-\tstr\tr1, [sp, #12]\n-\tsub.w\tr1, sl, #8\n-\tstr\tr1, [sp, #4]\n-\tmov\tr1, r8\n-\tldr.w\tr8, [sp, #276]\t@ 0x114\n-\tstr\tr5, [sp, #8]\n-\tmov\tlr, r0\n-\tmov\tr5, r0\n-\tmov\tr3, r0\n-\tvldr\td24, [r2, #8]\n+\tadd.w\tip, r1, ip, lsl #3\n+\tadd.w\tr7, fp, r3\n+\tadd.w\tr1, fp, r5\n+\tadd.w\tr6, fp, r4\n+\tadd\tr5, sl\n+\tadd\tr3, sl\n+\tadd\tr4, sl\n+\tvldr\td1, [r7]\n+\tvldr\td6, [r3]\n+\tvldr\td5, [r1]\n+\tvldr\td7, [r5]\n+\tvldr\td3, [r6]\n+\tvldr\td4, [r4]\n+\tvadd.f64\td8, d1, d5\n+\tvadd.f64\td0, d6, d7\n+\tvsub.f64\td5, d5, d1\n+\tvsub.f64\td7, d7, d6\n+\tvmov.f64\td1, d3\n+\tvmov.f64\td6, d4\n+\tvmls.f64\td1, d8, d2\n+\tvadd.f64\td3, d3, d8\n+\tvmls.f64\td6, d0, d2\n+\tvmul.f64\td5, d5, d14\n+\tvmul.f64\td7, d7, d14\n+\tvadd.f64\td4, d4, d0\n+\tvstmia\tr6!, {d3}\n+\tvstmia\tr4!, {d4}\n+\tvsub.f64\td3, d1, d7\n+\tvadd.f64\td7, d7, d1\n+\tvadd.f64\td4, d6, d5\n+\tvsub.f64\td6, d6, d5\n+\tvstmia\tr1!, {d3}\n+\tcmp\tr1, ip\n+\tvstmia\tr5!, {d4}\n+\tvstmia\tr7!, {d7}\n+\tvstmia\tr3!, {d6}\n+\tbne.n\t3518 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1e0>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadd.w\tr9, r9, #1\n+\tadd\tlr, r3\n+\tcmp\tlr, r8\n+\titt\tlt\n+\tldrlt\tr3, [sp, #56]\t@ 0x38\n+\taddlt\tlr, r3\n+\tldr\tr3, [sp, #4]\n+\tcmp\tr9, r3\n+\tbne.n\t34c6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x18e>\n+\tldrd\tr5, r7, [sp, #20]\n+\tldr\tr3, [sp, #28]\n+\tldr\tr6, [sp, #12]\n+\tadd\tr2, r7\n+\tsubs\tr3, #1\n+\tadds\tr4, r3, #1\n+\tbne.n\t34b8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x180>\n+\tmov\tr4, r0\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tcmp\tr3, #3\n+\tbeq.w\t38be <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x586>\n+\tldr\tr3, [sp, #16]\n+\tsubs\tr5, r5, r6\n \tcmp\tr6, #0\n-\tvldr\td22, [r4, #8]\n-\tvldr\td26, [r2]\n-\tvmul.f64\td24, d28, d24\n-\tvldr\td25, [r4]\n-\tvmul.f64\td22, d28, d22\n-\tblt.w\t362c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x58c>\n-\tldr\tr2, [sp, #8]\n+\tmov.w\tr9, r3, lsl #1\n+\tblt.w\t49c4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x168c>\n+\tmov\tr1, r6\n+\tsubs\tr0, r5, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tstr\tr0, [sp, #12]\n+\tbgt.w\t390c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5d4>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n+\tcmp\tr3, #1\n+\tbne.w\t49e0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x16a8>\n+\tmov.w\tr3, r9, lsl #4\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tmov.w\tr1, r9, lsl #3\n \tldr\tr0, [sp, #100]\t@ 0x64\n-\tcmp\tr0, r3\n-\tudiv\tr2, r2, r6\n-\tblt.w\t34d8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x438>\n-\tb.n\t3390 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2f0>\n+\tadds\tr2, r3, r1\n+\tstr\tr6, [sp, #64]\t@ 0x40\n+\tadds\tr3, r2, r1\n+\tsubs\tr5, r0, r6\n+\tmov\tr9, r3\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr5, [sp, #16]\n+\tsubs\tr3, r6, r0\n+\tstrd\tr1, r4, [sp, #80]\t@ 0x50\n+\tmov\tr4, r9\n+\tldr\tr5, [sp, #8]\n+\tmov\tr9, r6\n+\tldr\tr6, [sp, #356]\t@ 0x164\n+\tstr\tr3, [sp, #20]\n+\tvldr\td9, [r2, #8]\n+\tcmp\tr7, #0\n+\tvldr\td8, [r4, #8]\n+\tvldr\td11, [r2]\n+\tvmul.f64\td9, d13, d9\n+\tvldr\td10, [r4]\n+\tvmul.f64\td8, d13, d8\n+\tblt.w\t38e0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5a8>\n+\tldr\tr0, [sp, #16]\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r9\n+\tblt.w\t378e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x456>\n+\tb.n\t3658 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x320>\n \tnop.w\n \t.word\t0xe8584c9c\n-\t.word\t0xbfebb67a\n-\t.word\t0xe8584c9c\n \t.word\t0x3febb67a\n-\tldr\tr0, [sp, #104]\t@ 0x68\n-\tcmp\tr0, #0\n-\tble.w\t34d8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x438>\n-\tadd.w\tr0, ip, r3\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tstrd\tr7, r5, [sp, #68]\t@ 0x44\n-\tstrd\tr3, r4, [sp, #80]\t@ 0x50\n-\tstr\tr1, [sp, #88]\t@ 0x58\n-\tmov\tr7, r0\n-\tmov.w\tlr, #1\n-\tstrd\tr6, r2, [sp, #16]\n-\tstr\tr0, [sp, #24]\n-\tadd.w\tr6, r9, r7\n-\tcmp\tip, r6\n-\tble.n\t33c2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x322>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr6, r3\n-\tadd.w\tr3, r9, r6\n-\tcmp\tip, r3\n-\tble.n\t33ce <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x32e>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r2\n-\tcmp.w\tr8, #0\n-\tble.n\t34a6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x406>\n-\tadd.w\tr0, r6, #536870912\t@ 0x20000000\n+\t.word\t0xe8584c9c\n+\t.word\t0xbfebb67a\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tcmp\tr2, #0\n+\tble.w\t378e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x456>\n+\tadd.w\tr2, r8, r9\n+\tstr.w\tr9, [sp, #96]\t@ 0x60\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tmov\tlr, r2\n+\tmov.w\tr9, #1\n+\tstr\tr7, [sp, #8]\n+\tstrd\tr3, r2, [sp, #24]\n+\tadd.w\tip, r5, lr\n+\tcmp\tr8, ip\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tip, r3\n+\tadd.w\tr3, r5, ip\n+\tcmp\tr8, r3\n+\titt\tgt\n+\tldrgt\tr2, [sp, #56]\t@ 0x38\n+\taddgt\tr3, r3, r2\n+\tcmp\tr6, #0\n+\tble.n\t3760 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x428>\n+\tadd.w\tr0, ip, #536870912\t@ 0x20000000\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tadd.w\tr1, r7, #536870912\t@ 0x20000000\n-\tldr\tr2, [sp, #4]\n+\tadd.w\tr1, lr, #536870912\t@ 0x20000000\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n \tsubs\tr3, #1\n \tsubs\tr0, #1\n \tsubs\tr1, #1\n-\tadd\tr6, r8\n+\tadd\tip, r6\n \tlsls\tr3, r3, #3\n \tlsls\tr0, r0, #3\n \tlsls\tr1, r1, #3\n-\tadd.w\tr6, r2, r6, lsl #3\n-\tadd.w\tr5, sl, r3\n-\tadd.w\tr2, sl, r0\n-\tadd.w\tr4, sl, r1\n-\tadd\tr0, fp\n-\tadd\tr3, fp\n-\tadd\tr1, fp\n-\tvldr\td18, [r3]\n-\tvldr\td29, [r0]\n-\tvldr\td17, [r5]\n-\tvldr\td20, [r2]\n-\tvldr\td19, [r1]\n-\tvadd.f64\td27, d18, d29\n-\tvldr\td30, [r4]\n-\tvsub.f64\td29, d29, d18\n-\tvadd.f64\td31, d17, d20\n-\tvsub.f64\td20, d20, d17\n-\tvmov.f64\td17, d19\n-\tvmov.f64\td18, d19\n-\tvfms.f64\td17, d27, d21\n-\tvmov.f64\td7, d30\n-\tvfnms.f64\td18, d27, d21\n-\tvadd.f64\td27, d19, d27\n-\tvfms.f64\td7, d31, d21\n-\tvadd.f64\td30, d30, d31\n-\tvfma.f64\td18, d16, d20\n-\tvstmia\tr1!, {d27}\n-\tvstmia\tr4!, {d30}\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td17, d20, d23\n-\tvfma.f64\td19, d16, d20\n-\tvmov.f64\td31, d7\n-\tvfma.f64\td7, d16, d29\n-\tvfma.f64\td31, d29, d23\n-\tvmul.f64\td18, d18, d22\n-\tvmul.f64\td17, d17, d25\n-\tvnmul.f64\td27, d24, d19\n-\tvmul.f64\td19, d19, d26\n-\tvfma.f64\td18, d7, d25\n-\tvfma.f64\td17, d7, d22\n-\tvfma.f64\td27, d31, d26\n-\tvfma.f64\td19, d31, d24\n-\tvstmia\tr2!, {d27}\n-\tcmp\tr2, r6\n-\tvstmia\tr0!, {d19}\n-\tvstmia\tr5!, {d18}\n-\tvstmia\tr3!, {d17}\n-\tbne.n\t3406 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x366>\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tadd\tr7, r3\n-\tcmp\tip, r7\n-\tble.n\t34b2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x412>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r3\n-\tldr\tr3, [sp, #0]\n-\tadd.w\tlr, lr, #1\n-\tcmp\tlr, r3\n-\tbne.w\t33b6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x316>\n-\tldrd\tr6, r2, [sp, #16]\n-\tldr\tr0, [sp, #24]\n-\tsubs\tr2, #1\n-\tadd\tr0, r6\n-\tadds\tr4, r2, #1\n-\tbne.w\t33aa <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x30a>\n-\tldrd\tr7, r5, [sp, #68]\t@ 0x44\n-\tldrd\tr3, r4, [sp, #80]\t@ 0x50\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tsubs\tr7, #1\n-\tadd\tr3, r5\n-\tadds\tr0, r7, #1\n-\tadd\tr4, r2\n-\tldr\tr2, [sp, #8]\n-\tsub.w\tr2, r2, r5\n-\tstr\tr2, [sp, #8]\n-\tldr\tr2, [sp, #12]\n-\tadd\tr2, r5\n-\tstr\tr2, [sp, #12]\n-\tmov\tr2, r1\n-\tbeq.w\t363e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x59e>\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tadd\tr1, r0\n-\tb.n\t334e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2ae>\n-\tldr\tr7, [sp, #276]\t@ 0x114\n-\tstr.w\tr9, [sp, #4]\n-\tadd.w\tr8, r7, #1\n-\tmov\tr9, r1\n-\tmovs\tr7, #1\n-\tstrd\tr4, r6, [sp, #16]\n-\tstrd\tr7, r0, [sp, #8]\n-\tstr\tr2, [sp, #24]\n-\tstr\tr5, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #4]\n-\tadd\tr2, r9\n+\tadd.w\tip, r2, ip, lsl #3\n+\tadd.w\tr7, fp, r3\n+\tadd.w\tr2, fp, r0\n+\tadd.w\tr4, fp, r1\n+\tadd\tr0, sl\n+\tadd\tr3, sl\n+\tadd\tr1, sl\n+\tvldr\td5, [r3]\n+\tvldr\td7, [r0]\n+\tvldr\td2, [r7]\n+\tvldr\td6, [r2]\n+\tvadd.f64\td4, d5, d7\n+\tvldr\td0, [r4]\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td1, [r1]\n+\tvadd.f64\td3, d2, d6\n+\tvsub.f64\td6, d6, d2\n+\tvmov.f64\td2, d0\n+\tvmul.f64\td5, d4, d12\n+\tvadd.f64\td4, d1, d4\n+\tvmul.f64\td7, d7, d14\n+\tvmls.f64\td2, d3, d12\n+\tvmul.f64\td6, d6, d14\n+\tvadd.f64\td0, d0, d3\n+\tvsub.f64\td3, d1, d5\n+\tvstmia\tr1!, {d4}\n+\tvsub.f64\td1, d5, d1\n+\tvstmia\tr4!, {d0}\n+\tvadd.f64\td4, d3, d6\n+\tvadd.f64\td1, d1, d6\n+\tvsub.f64\td5, d2, d7\n+\tvadd.f64\td7, d7, d2\n+\tvsub.f64\td2, d3, d6\n+\tvmul.f64\td0, d4, d9\n+\tvmul.f64\td3, d7, d10\n+\tvmul.f64\td6, d5, d9\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td6, d4, d11\n+\tvmla.f64\td3, d1, d8\n+\tvmla.f64\td7, d2, d10\n+\tvnmls.f64\td0, d5, d11\n+\tvstmia\tr0!, {d6}\n+\tvstmia\tr3!, {d7}\n+\tvstmia\tr2!, {d0}\n \tcmp\tr2, ip\n-\tbge.n\t3522 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x482>\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #4]\n-\tadd\tr0, r2\n-\tcmp\tr0, ip\n-\tbge.n\t352e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x48e>\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n+\tvstmia\tr7!, {d3}\n+\tbne.n\t36c4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x38c>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadd.w\tr9, r9, #1\n+\tadd\tlr, r3\n+\tcmp\tr8, lr\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tlr, r3\n+\tldr\tr3, [sp, #4]\n+\tcmp\tr9, r3\n+\tbne.w\t3676 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x33e>\n+\tldrd\tr3, r2, [sp, #24]\n+\tldr\tr7, [sp, #8]\n+\tsubs\tr3, #1\n+\tadd\tr2, r7\n+\tadds\tr1, r3, #1\n+\tbne.w\t366a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x332>\n+\tldr.w\tr9, [sp, #96]\t@ 0x60\n+\tldr\tr4, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #12]\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tsubs\tr1, r3, #1\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr4, r2\n+\tldr\tr2, [sp, #16]\n+\tadd\tr9, r3\n+\tstr\tr1, [sp, #12]\n+\tsubs\tr2, r2, r3\n+\tstr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #20]\n+\tadds\tr1, #1\n+\tadd\tr2, r3\n+\tldr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr2, [sp, #20]\n+\tmov\tr2, r3\n+\tbeq.w\t3908 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5d0>\n+\tldr\tr1, [sp, #80]\t@ 0x50\n+\tadd\tr3, r1\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tb.n\t3612 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2da>\n+\tldr\tr1, [sp, #356]\t@ 0x164\n+\tadd.w\tr9, r1, #1\n+\tmov\tlr, r2\n+\tmovs\tr1, #1\n+\tstrd\tr6, r5, [sp, #20]\n+\tstr\tr1, [sp, #12]\n+\tstr\tr7, [sp, #28]\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #8]\n+\tadd\tr3, lr\n+\tcmp\tr3, r8\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr3, r3, r1\n+\tldr\tr1, [sp, #8]\n+\tadd\tr1, r3\n+\tcmp\tr1, r8\n+\titt\tlt\n+\tldrlt\tr0, [sp, #56]\t@ 0x38\n+\taddlt\tr1, r1, r0\n+\tldr\tr0, [sp, #356]\t@ 0x164\n+\tcmp\tr0, #0\n+\tble.n\t388e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x556>\n+\tlsls\tr3, r3, #3\n+\tlsls\tr1, r1, #3\n+\tmov.w\tr0, lr, lsl #3\n+\tadd.w\tr7, fp, r3\n+\tadd.w\tr6, fp, r1\n+\tadd.w\tr5, fp, r0\n+\tadd\tr3, sl\n+\tadd\tr1, sl\n+\tadd\tr0, sl\n+\tmov.w\tip, #1\n+\tvldr\td4, [r6, #-8]\n+\tadd.w\tip, ip, #1\n+\tvldr\td5, [r1, #-8]\n+\tcmp\tip, r9\n+\tvldr\td7, [r7, #-8]\n+\tvldr\td6, [r3, #-8]\n+\tvldr\td8, [r5, #-8]\n+\tvldr\td0, [r0, #-8]\n+\tvadd.f64\td1, d7, d4\n+\tvadd.f64\td3, d6, d5\n+\tvsub.f64\td7, d7, d4\n+\tvsub.f64\td6, d6, d5\n+\tvmov.f64\td4, d8\n+\tvmov.f64\td5, d0\n+\tvmls.f64\td4, d1, d2\n+\tvadd.f64\td1, d1, d8\n+\tvmls.f64\td5, d3, d2\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td6, d6, d14\n+\tvadd.f64\td3, d3, d0\n+\tvstr\td1, [r5, #-8]\n+\tadd\tr5, r4\n+\tvstr\td3, [r0, #-8]\n \tadd\tr0, r4\n-\tldr\tr4, [sp, #276]\t@ 0x114\n-\tcmp\tr4, #0\n-\tble.n\t35d6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x536>\n-\tlsls\tr2, r2, #3\n-\tlsls\tr0, r0, #3\n-\tmov.w\tr4, r9, lsl #3\n-\tadd.w\tr7, sl, r2\n-\tadd.w\tr6, sl, r0\n-\tadd.w\tr5, sl, r4\n-\tadd\tr2, fp\n-\tadd\tr0, fp\n-\tadd\tr4, fp\n-\tmov.w\tlr, #1\n-\tvldr\td21, [r6, #-8]\n-\tadd.w\tlr, lr, #1\n-\tvldr\td17, [r7, #-8]\n+\tvsub.f64\td3, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvadd.f64\td6, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvstr\td3, [r7, #-8]\n+\tadd\tr7, r4\n+\tvstr\td6, [r3, #-8]\n+\tadd\tr3, r4\n+\tvstr\td4, [r6, #-8]\n+\tadd\tr6, r4\n+\tvstr\td5, [r1, #-8]\n+\tadd\tr1, r4\n+\tbne.n\t380a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x4d2>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadd\tlr, r3\n \tcmp\tlr, r8\n-\tvldr\td20, [r0, #-8]\n-\tvldr\td18, [r2, #-8]\n-\tvldr\td22, [r5, #-8]\n-\tvadd.f64\td19, d17, d21\n-\tvldr\td24, [r4, #-8]\n-\tvsub.f64\td17, d17, d21\n-\tvadd.f64\td21, d18, d20\n-\tvsub.f64\td18, d18, d20\n-\tvmov.f64\td20, d22\n-\tvfms.f64\td20, d19, d25\n-\tvadd.f64\td22, d19, d22\n-\tvmov.f64\td19, d24\n-\tvfms.f64\td19, d21, d25\n-\tvadd.f64\td21, d21, d24\n-\tvstr\td22, [r5, #-8]\n-\tadd\tr5, r3\n-\tvstr\td21, [r4, #-8]\n-\tadd\tr4, r3\n-\tvmov.f64\td24, d20\n-\tvfma.f64\td20, d16, d18\n-\tvfma.f64\td24, d18, d23\n-\tvmov.f64\td18, d19\n-\tvfms.f64\td19, d17, d16\n-\tvfma.f64\td18, d17, d16\n-\tvstr\td24, [r7, #-8]\n-\tadd\tr7, r3\n-\tvstr\td20, [r6, #-8]\n-\tadd\tr6, r3\n-\tvstr\td18, [r2, #-8]\n-\tadd\tr2, r3\n-\tvstr\td19, [r0, #-8]\n-\tadd\tr0, r3\n-\tbne.n\t3552 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x4b2>\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadd\tr9, r2\n-\tcmp\tr9, ip\n-\tbge.n\t35e2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x542>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr9, r2\n-\tldr\tr2, [sp, #8]\n-\tldr\tr0, [sp, #0]\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #8]\n-\tcmp\tr2, r0\n-\tbne.n\t3516 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x476>\n-\tldrd\tr6, r2, [sp, #20]\n-\tldrd\tr0, r4, [sp, #12]\n-\tsubs\tr2, #1\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tadd\tr1, r6\n-\tadds\tr7, r2, #1\n-\tbne.n\t3506 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x466>\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tldr.w\tr9, [sp, #4]\n-\tcmp\tr2, #3\n-\tbne.w\t32fe <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x25e>\n-\tldrd\tr0, r4, [sp, #32]\n-\tadds\tr0, #1\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr2, [sp, #276]\t@ 0x114\n-\tldr\tr1, [sp, #264]\t@ 0x108\n+\tbge.n\t389a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x562>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tlr, r3\n+\tldr\tr3, [sp, #12]\n+\tldr\tr1, [sp, #4]\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #12]\n+\tcmp\tr3, r1\n+\tbne.n\t37ce <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x496>\n+\tldr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr7, [sp, #28]\n+\tsubs\tr3, #1\n+\tldrd\tr6, r5, [sp, #20]\n+\tadd\tr2, r7\n+\tadds\tr0, r3, #1\n+\tbne.n\t37c0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x488>\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tcmp\tr3, #3\n+\tbne.w\t35bc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x284>\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tldrd\tr7, r4, [sp, #48]\t@ 0x30\n+\tadds\tr7, #1\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #356]\t@ 0x164\n+\tldr\tr1, [sp, #344]\t@ 0x158\n \tmla\tr3, r1, r2, r3\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #176]\t@ 0xb0\n-\tcmp\tr0, r3\n-\tbeq.w\t44f2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1452>\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #208]\t@ 0xd0\n+\tcmp\tr7, r3\n+\tbeq.w\t49ba <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1682>\n \tmov\tr3, r4\n-\tstr\tr4, [sp, #276]\t@ 0x114\n-\tb.n\t316c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcc>\n-\tldr\tr0, [sp, #12]\n-\tnegs\tr2, r6\n-\tudiv\tr2, r0, r2\n-\tldr\tr0, [sp, #100]\t@ 0x64\n-\tcmp\tr0, r3\n-\tble.w\t3390 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2f0>\n-\tb.n\t34d8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x438>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tmov\tr0, r5\n-\tldr\tr2, [sp, #28]\n-\tldr\tr1, [sp, #156]\t@ 0x9c\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #28]\n-\tcmp\tr1, r2\n-\tbge.w\t31b0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x110>\n-\tldrd\tr0, r4, [sp, #32]\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tldr\tr2, [sp, #272]\t@ 0x110\n-\tcmp\tr3, r2\n-\tbgt.n\t3610 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x570>\n-\tldr.w\tfp, [sp, #100]\t@ 0x64\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tstrd\tr0, r4, [sp, #144]\t@ 0x90\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tmov\tr5, r3\n+\tstr\tr4, [sp, #356]\t@ 0x164\n+\tb.n\t3414 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xdc>\n+\tldr\tr0, [sp, #20]\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r9\n+\tble.w\t3658 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x320>\n+\tb.n\t378e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x456>\n+\tldr\tr0, [sp, #152]\t@ 0x98\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, #0\n+\tble.w\t349e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x166>\n+\tb.n\t35b4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x27c>\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tldr\tr4, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #32]\n+\tldr\tr2, [sp, #196]\t@ 0xc4\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #32]\n+\tcmp\tr2, r3\n+\tbge.w\t346a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x132>\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tldrd\tr7, r4, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #352]\t@ 0x160\n+\tcmp\tr6, r3\n+\tbgt.n\t38c4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x58c>\n+\tstr\tr6, [sp, #156]\t@ 0x9c\n+\tstrd\tr6, r7, [sp, #180]\t@ 0xb4\n+\tstr\tr4, [sp, #188]\t@ 0xbc\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr5, [sp, #56]\t@ 0x38\n+\tmov\tr4, r3\n+\tstr\tr3, [sp, #96]\t@ 0x60\n \tadd.w\tr3, r3, r3, lsl #1\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tsdiv\tr7, r3, r2\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n-\tmul.w\tr6, r5, r2\n-\tadds.w\tlr, r7, r7, lsl #1\n-\tsub.w\tr1, r6, r3\n-\tsub.w\tsl, r6, r2\n-\tsub.w\tr3, r7, r3\n-\tstr\tr1, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tbmi.w\t48a2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1802>\n-\tudiv\tr0, sl, lr\n-\tcmp.w\tsl, #0\n-\tblt.w\t39f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x956>\n-\tadd.w\tr1, r6, r6, lsl #1\n-\tnegs\tr3, r1\n+\tmov\tr0, r5\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tsubs\tr1, r0, r5\n+\tmov\tr9, r0\n+\tadds.w\tfp, r0, r0, lsl #1\n+\tstr\tr1, [sp, #52]\t@ 0x34\n+\tmul.w\tr6, r4, r3\n+\tsub.w\tr2, r6, r5\n+\tsub.w\tr5, r6, r3\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tstr\tr5, [sp, #120]\t@ 0x78\n+\tbmi.w\t49a4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x166c>\n+\tmov\tr1, fp\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tr4, r0\n+\tblt.w\t402a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcf2>\n+\tadd.w\tsl, r6, r6, lsl #1\n+\tvmov.f64\td8, #96\t@ 0x3f000000 0.5\n+\trsb\tr3, sl, #0\n \tstr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #264]\t@ 0x108\n+\tldr\tr3, [sp, #344]\t@ 0x158\n \tcmp\tr3, #1\n-\tbne.w\t452c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x148c>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tmov\tr8, fp\n-\tldr.w\tip, [sp, #120]\t@ 0x78\n-\tmovs\tr4, #0\n-\tstr\tr6, [sp, #84]\t@ 0x54\n-\tmov\tr9, r7\n-\tmov\tr6, r5\n-\tsubs\tr3, #8\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tcmp\tr1, #0\n-\tblt.w\t4032 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf92>\n-\tudiv\tr2, r8, r1\n-\tcmp\tfp, r4\n-\tblt.w\t39e0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x940>\n-\tldr\tr3, [sp, #104]\t@ 0x68\n+\tbne.w\t3cce <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x996>\n+\tldr.w\tr8, [sp, #152]\t@ 0x98\n+\tmovs\tr7, #0\n+\tldr\tr5, [sp, #100]\t@ 0x64\n+\tcmp.w\tsl, #0\n+\tblt.w\t3cba <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x982>\n+\tmov\tr1, sl\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr2, r0\n+\tcmp\tr3, r7\n+\tblt.w\t3ca2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x96a>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n \tcmp\tr3, #0\n-\tble.w\t39e0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x940>\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tble.w\t3ca2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x96a>\n+\tldr\tr1, [sp, #68]\t@ 0x44\n \tadds\tr3, #1\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tadd\tr5, r4\n-\tstrd\tr0, fp, [sp, #88]\t@ 0x58\n+\tstr\tr7, [sp, #84]\t@ 0x54\n+\tadd\tr1, r7\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstrd\tfp, sl, [sp, #132]\t@ 0x84\n \tmovs\tr3, #1\n-\tldr.w\tfp, [sp, #60]\t@ 0x3c\n-\tstr\tr5, [sp, #32]\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tstr.w\tr9, [sp, #96]\t@ 0x60\n-\tstrd\tsl, lr, [sp, #128]\t@ 0x80\n-\tstr\tr1, [sp, #140]\t@ 0x8c\n-\tstrd\tr4, r2, [sp, #164]\t@ 0xa4\n-\tstrd\tr6, r5, [sp, #180]\t@ 0xb4\n-\tstrd\tr8, ip, [sp, #188]\t@ 0xbc\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #32]\n+\tldr.w\tfp, [sp, #68]\t@ 0x44\n+\tstr\tr1, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstrd\tr4, r9, [sp, #104]\t@ 0x68\n+\tstr\tr6, [sp, #116]\t@ 0x74\n+\tstrd\tr2, r1, [sp, #160]\t@ 0xa0\n+\tstrd\tr5, r8, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tldr\tr1, [sp, #36]\t@ 0x24\n \tadds\tr2, r3, r2\n+\tldr\tr5, [sp, #52]\t@ 0x34\n \tcmp\tfp, r2\n-\tble.n\t371c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x67c>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tadds\tr4, r3, r2\n \tcmp\tfp, r4\n-\tble.n\t3728 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x688>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #32]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr4, r4, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n \tadds\tr6, r3, r1\n+\tldr\tr1, [sp, #64]\t@ 0x40\n \tcmp\tfp, r6\n-\tble.n\t3736 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x696>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr6, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr6, r6, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadd\tr1, r6\n \tadds\tr0, r3, r6\n \tcmp\tfp, r0\n-\tble.n\t3742 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6a2>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tadd.w\tip, r3, r0\n \tcmp\tfp, ip\n-\tble.n\t3750 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6b0>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tip, r3\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tadd\tr1, r6\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tip, r3\n \tcmp\tfp, r1\n-\tble.n\t375c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6bc>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr1, r3\n-\tldr\tr5, [sp, #40]\t@ 0x28\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr1, r1, r3\n \tadds\tr7, r5, r1\n+\tldr\tr5, [sp, #52]\t@ 0x34\n \tcmp\tfp, r7\n-\tble.n\t3768 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6c8>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r3\n-\tldr\tr5, [sp, #40]\t@ 0x28\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr7, r7, r3\n \tadd\tr5, r7\n \tcmp\tfp, r5\n-\tble.n\t3774 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6d4>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #276]\t@ 0x114\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr5, r5, r3\n+\tldr\tr3, [sp, #356]\t@ 0x164\n \tcmp\tr3, #0\n-\tble.w\t399c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x8fc>\n+\tble.w\t3c64 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x92c>\n \tadd.w\tr3, ip, #536870912\t@ 0x20000000\n \tadd.w\tr7, r7, #536870912\t@ 0x20000000\n \tsubs\tr3, #1\n \tsubs\tr7, #1\n \tadd.w\tr4, r4, #536870912\t@ 0x20000000\n \tadd.w\tr6, r6, #536870912\t@ 0x20000000\n \tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #0]\n+\tstr\tr3, [sp, #4]\n \tlsls\tr3, r5, #3\n-\tstr\tr3, [sp, #12]\n-\tlsls\tr3, r1, #3\n \tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #32]\n+\tlsls\tr3, r1, #3\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #36]\t@ 0x24\n \tmov.w\tsl, r7, lsl #3\n \tadd.w\tr1, r2, #536870912\t@ 0x20000000\n \tadd.w\tr0, r0, #536870912\t@ 0x20000000\n \tadd.w\tr5, r3, #536870912\t@ 0x20000000\n-\tldr\tr3, [sp, #276]\t@ 0x114\n+\tldr\tr3, [sp, #356]\t@ 0x164\n \tsubs\tr1, #1\n \tsubs\tr4, #1\n \tadds\tr7, r3, r2\n-\tldr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tlsls\tr1, r1, #3\n \tlsls\tr2, r2, #3\n \tsubs\tr6, #1\n \tsubs\tr0, #1\n \tadd.w\tr3, r3, r7, lsl #3\n-\tldr\tr7, [sp, #52]\t@ 0x34\n+\tldr\tr7, [sp, #72]\t@ 0x48\n \tsubs\tr5, #1\n-\tstr\tr3, [sp, #28]\n+\tstr\tr3, [sp, #32]\n \tnegs\tr3, r2\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #28]\n \tadds\tr3, r7, r1\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tlsls\tr4, r4, #3\n \tlsls\tr6, r6, #3\n \tlsls\tr0, r0, #3\n \tmov\tr2, r3\n \tlsls\tr5, r5, #3\n \tadd.w\tr9, r7, r4\n \tadd.w\tr8, r7, r5\n \tadd.w\tlr, r7, r0\n \tadd\tr1, r3\n \tadd\tr0, r2\n \tadd\tr4, r3\n \tadd\tr5, r3\n \tadds\tr3, r7, r6\n \tadd\tr6, r2\n-\tstr\tr3, [sp, #4]\n+\tstr\tr3, [sp, #12]\n \tmov\tr3, r2\n-\tldr\tr2, [sp, #0]\n-\tstr.w\tfp, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #4]\n+\tstr.w\tfp, [sp, #48]\t@ 0x30\n \tmov\tfp, r6\n \tadd.w\tip, r7, r2\n-\tldr\tr7, [sp, #0]\n+\tldr\tr7, [sp, #4]\n \tmov\tr2, r3\n \tadd\tr7, r3\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tadd\tr3, sl\n \tadd\tsl, r2\n \tstr\tr3, [sp, #8]\n-\tldr\tr2, [sp, #20]\n-\tstr\tr0, [sp, #20]\n-\tvldr\td25, [r9]\n-\tvldr\td18, [r2]\n-\tvldr\td22, [r4]\n-\tvldr\td19, [r1]\n-\tvldr\td21, [r8]\n-\tvadd.f64\td24, d25, d18\n-\tvldr\td20, [r5]\n-\tvsub.f64\td18, d18, d25\n-\tvadd.f64\td25, d22, d19\n-\tvsub.f64\td19, d19, d22\n-\tvmov.f64\td22, d21\n-\tldr\tr3, [sp, #4]\n-\tvfms.f64\td22, d24, d17\n-\tvadd.f64\td21, d21, d24\n-\tvmov.f64\td24, d20\n-\tldr\tr0, [sp, #20]\n-\tvfms.f64\td24, d25, d17\n-\tvadd.f64\td20, d20, d25\n-\tvldr\td29, [r3]\n-\tvstmia\tr8!, {d21}\n-\tvldr\td30, [fp]\n-\tvstmia\tr5!, {d20}\n-\tvmov.f64\td25, d22\n-\tvfma.f64\td22, d16, d19\n-\tvfma.f64\td25, d19, d23\n-\tvmov.f64\td21, d24\n-\tvfma.f64\td24, d23, d18\n-\tvfma.f64\td21, d16, d18\n-\tvstmia\tr3!, {d25}\n-\tvldr\td27, [ip]\n-\tvstmia\tfp!, {d21}\n-\tvldr\td20, [lr]\n-\tvldr\td26, [r7]\n-\tvldr\td21, [r0]\n-\tvadd.f64\td25, d27, d20\n-\tvsub.f64\td20, d20, d27\n-\tstr\tr3, [sp, #4]\n-\tvadd.f64\td27, d26, d21\n-\tvsub.f64\td21, d21, d26\n-\tvmov.f64\td26, d29\n+\tldr\tr2, [sp, #24]\n+\tstr\tr0, [sp, #24]\n+\tvldr\td3, [r9]\n+\tvldr\td5, [r4]\n+\tvldr\td7, [r2]\n+\tvldr\td6, [r1]\n+\tvldr\td0, [r8]\n+\tvldr\td10, [r5]\n+\tvadd.f64\td4, d3, d7\n+\tvadd.f64\td1, d5, d6\n+\tvsub.f64\td7, d7, d3\n+\tvmov.f64\td2, d0\n+\tvsub.f64\td6, d6, d5\n+\tvmov.f64\td11, d10\n+\tldr\tr3, [sp, #12]\n+\tvmls.f64\td2, d4, d8\n+\tvadd.f64\td4, d0, d4\n+\tvmls.f64\td11, d1, d8\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td6, d6, d14\n+\tvadd.f64\td10, d10, d1\n+\tvldr\td9, [r3]\n+\tvldr\td5, [fp]\n+\tvstmia\tr8!, {d4}\n+\tvstmia\tr5!, {d10}\n+\tldr\tr0, [sp, #24]\n+\tvsub.f64\td4, d2, d6\n+\tvadd.f64\td10, d6, d2\n+\tvadd.f64\td6, d11, d7\n+\tvsub.f64\td11, d11, d7\n+\tvstmia\tr3!, {d4}\n+\tvstmia\tfp!, {d6}\n+\tvldr\td3, [ip]\n+\tvldr\td4, [lr]\n+\tvldr\td1, [r0]\n+\tvldr\td12, [r7]\n+\tvadd.f64\td2, d3, d4\n+\tvsub.f64\td4, d4, d3\n+\tstr\tr3, [sp, #12]\n+\tvadd.f64\td0, d12, d1\n+\tvsub.f64\td3, d1, d12\n+\tvmov.f64\td1, d9\n \tldr\tr3, [sp, #8]\n-\tvfms.f64\td26, d25, d17\n-\tvadd.f64\td29, d25, d29\n-\tvmov.f64\td25, d30\n-\tvldr\td19, [sl]\n-\tvfms.f64\td25, d27, d17\n-\tvadd.f64\td27, d27, d30\n-\tvldr\td18, [r3]\n-\tvstmia\tr2!, {d29}\n-\tvstmia\tr1!, {d27}\n-\tvmov.f64\td30, d26\n-\tvfma.f64\td26, d16, d21\n-\tvfma.f64\td30, d23, d21\n-\tvmov.f64\td21, d25\n-\tvfma.f64\td25, d20, d23\n-\tvfma.f64\td21, d16, d20\n-\tvstmia\tlr!, {d30}\n-\tvstmia\tr3!, {d26}\n+\tvmls.f64\td1, d2, d8\n+\tvadd.f64\td2, d2, d9\n+\tvmul.f64\td4, d4, d14\n+\tvldr\td7, [sl]\n+\tvadd.f64\td9, d0, d5\n+\tvmls.f64\td5, d0, d8\n+\tvmul.f64\td3, d3, d14\n+\tvldr\td6, [r3]\n+\tvstmia\tr2!, {d2}\n+\tvstmia\tr1!, {d9}\n+\tvsub.f64\td2, d1, d3\n+\tvadd.f64\td3, d3, d1\n+\tvadd.f64\td1, d5, d4\n+\tvsub.f64\td5, d5, d4\n+\tvstmia\tlr!, {d2}\n+\tvstmia\tr3!, {d3}\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #24]\n-\tvstmia\tr0!, {d21}\n-\tstr\tr0, [sp, #20]\n+\tldr\tr3, [sp, #28]\n+\tvstmia\tr0!, {d1}\n+\tstr\tr0, [sp, #24]\n \tadds\tr6, r2, r3\n-\tldr\tr0, [sp, #12]\n+\tldr\tr0, [sp, #16]\n \tadds\tr3, r1, r3\n-\tvstmia\tsl!, {d25}\n+\tvstmia\tsl!, {d5}\n \tadds\tr0, r6, r0\n-\tstr\tr0, [sp, #0]\n-\tldr\tr0, [sp, #16]\n+\tstr\tr0, [sp, #4]\n+\tldr\tr0, [sp, #20]\n \tadd\tr6, r0\n-\tldr\tr0, [sp, #0]\n-\tvldr\td20, [r6, #-8]\n-\tvldr\td21, [r0, #-8]\n-\tvstr\td22, [r6, #-8]\n-\tldr\tr6, [sp, #12]\n-\tvadd.f64\td22, d21, d18\n-\tvsub.f64\td18, d18, d21\n-\tvmov.f64\td21, d20\n+\tldr\tr0, [sp, #4]\n+\tvldr\td5, [r6, #-8]\n+\tvldr\td3, [r0, #-8]\n+\tvstr\td10, [r6, #-8]\n+\tldr\tr6, [sp, #16]\n+\tvadd.f64\td4, d3, d6\n+\tvsub.f64\td6, d6, d3\n+\tvmov.f64\td3, d5\n \tadds\tr6, r3, r6\n-\tldr\tr0, [sp, #16]\n-\tvadd.f64\td20, d20, d22\n+\tldr\tr0, [sp, #20]\n+\tvadd.f64\td5, d5, d4\n \tadd\tr3, r0\n-\tvfms.f64\td21, d22, d17\n-\tldr\tr0, [sp, #0]\n-\tvldr\td22, [r3, #-8]\n-\tvstmia\tr9!, {d20}\n-\tvldr\td20, [r6, #-8]\n-\tvstr\td24, [r3, #-8]\n-\tldr\tr3, [sp, #28]\n-\tvadd.f64\td24, d20, d19\n-\tvsub.f64\td19, d19, d20\n-\tvmov.f64\td20, d22\n-\tvmov.f64\td25, d21\n-\tcmp\tr2, r3\n-\tvfms.f64\td20, d24, d17\n-\tvfma.f64\td25, d23, d19\n-\tvfma.f64\td21, d16, d19\n-\tvadd.f64\td22, d22, d24\n-\tvstmia\tr4!, {d22}\n-\tvmov.f64\td19, d20\n-\tvfma.f64\td20, d23, d18\n-\tvfma.f64\td19, d16, d18\n-\tvstmia\tip!, {d25}\n-\tvstr\td21, [r0, #-8]\n-\tvstmia\tr7!, {d19}\n-\tvstr\td20, [r6, #-8]\n-\tbne.w\t3818 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x778>\n-\tldr.w\tfp, [sp, #64]\t@ 0x40\n+\tvmls.f64\td3, d4, d8\n+\tvmul.f64\td6, d6, d14\n+\tldr\tr0, [sp, #4]\n+\tvldr\td4, [r3, #-8]\n+\tvstmia\tr9!, {d5}\n+\tvldr\td5, [r6, #-8]\n+\tvstr\td11, [r3, #-8]\n \tldr\tr3, [sp, #32]\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tvadd.f64\td2, d5, d7\n+\tvsub.f64\td7, d7, d5\n+\tvmov.f64\td5, d4\n+\tcmp\tr2, r3\n+\tvmls.f64\td5, d2, d8\n+\tvadd.f64\td4, d4, d2\n+\tvmul.f64\td7, d7, d14\n+\tvstmia\tr4!, {d4}\n+\tvsub.f64\td2, d3, d7\n+\tvadd.f64\td7, d7, d3\n+\tvadd.f64\td4, d5, d6\n+\tvsub.f64\td5, d5, d6\n+\tvstmia\tip!, {d2}\n+\tvstr\td7, [r0, #-8]\n+\tvstmia\tr7!, {d4}\n+\tvstr\td5, [r6, #-8]\n+\tbne.w\t3ae4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x7ac>\n+\tldr.w\tfp, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #32]\n+\tstr\tr3, [sp, #36]\t@ 0x24\n \tcmp\tfp, r3\n-\tble.n\t39ae <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x90e>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #56]\t@ 0x38\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r2\n-\tbne.w\t370e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x66e>\n-\tldrd\tr4, r2, [sp, #164]\t@ 0xa4\n-\tldrd\tr6, r5, [sp, #180]\t@ 0xb4\n+\tbne.w\t39da <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x6a2>\n+\tldrd\tr2, r1, [sp, #160]\t@ 0xa0\n+\tldrd\tfp, sl, [sp, #132]\t@ 0x84\n \tsubs\tr2, #1\n-\tldr\tr1, [sp, #140]\t@ 0x8c\n-\tadds\tr3, r2, #1\n-\tldrd\tr0, fp, [sp, #88]\t@ 0x58\n-\tadd\tr5, r1\n-\tldr.w\tr9, [sp, #96]\t@ 0x60\n-\tldrd\tsl, lr, [sp, #128]\t@ 0x80\n-\tldrd\tr8, ip, [sp, #188]\t@ 0xbc\n-\tbne.w\t36ea <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x64a>\n-\tsubs\tr0, #1\n-\tadd\tr4, lr\n-\tsub.w\tr8, r8, lr\n-\tadd\tip, lr\n-\tadds\tr7, r0, #1\n-\tbne.w\t36c6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x626>\n+\tldrd\tr4, r9, [sp, #104]\t@ 0x68\n+\tadd\tr1, sl\n+\tldr\tr6, [sp, #116]\t@ 0x74\n+\tadds\tr7, r2, #1\n+\tldrd\tr5, r8, [sp, #172]\t@ 0xac\n+\tbne.w\t39be <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x686>\n+\tldr\tr7, [sp, #84]\t@ 0x54\n+\tsubs\tr4, #1\n+\tadd\tr7, fp\n+\tsub.w\tr5, r5, fp\n+\tadd\tr8, fp\n+\tadds\tr0, r4, #1\n+\tbeq.w\t402a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcf2>\n+\tcmp.w\tsl, #0\n+\tbge.w\t399a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x662>\n+\tldr\tr1, [sp, #80]\t@ 0x50\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr2, r0\n+\tcmp\tr3, r7\n+\tble.w\t39ac <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x674>\n+\tb.n\t3ca2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x96a>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmov.w\tr8, #0\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n \tmov\tr5, r6\n-\tldr\tr6, [sp, #84]\t@ 0x54\n-\tmov\tr7, r9\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr2, [sp, #272]\t@ 0x110\n-\tcmp\tr3, r2\n-\tbeq.w\t4524 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1484>\n-\tldr\tr4, [sp, #108]\t@ 0x6c\n-\tlsls\tr2, r5, #1\n-\tsubs\tr3, r7, r4\n-\tcmp\tr4, #0\n-\tblt.w\t4508 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1468>\n-\tsubs\tr1, r3, r4\n-\tcmp\tr4, r3\n-\tudiv\tr5, r1, r4\n-\tbgt.w\t4516 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1476>\n-\tadd.w\tr9, r6, r6, lsl #1\n-\trsb\tr3, r9, #0\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr3, [sp, #264]\t@ 0x108\n-\tcmp\tr3, #1\n-\tbne.w\t4068 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xfc8>\n-\tldr\tr1, [sp, #116]\t@ 0x74\n-\tlsls\tr3, r2, #3\n-\tlsls\tr2, r2, #4\n-\tstr\tr3, [sp, #164]\t@ 0xa4\n-\tstr\tr2, [sp, #168]\t@ 0xa8\n-\tmov\tr2, r3\n-\tadds\tr3, r1, r3\n-\tldr\tr1, [sp, #108]\t@ 0x6c\n-\tadds\tr4, r3, r2\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tsub.w\tr8, sl, r1\n-\tsub.w\tr6, r1, fp\n-\tmov\tr7, r4\n-\tmov\tip, r1\n-\tmov\tr0, r5\n-\tsubs\tr2, #8\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tvldr\td25, [r3, #8]\n-\tcmp.w\tlr, #0\n-\tvldr\td24, [r7, #8]\n-\tvldr\td27, [r3]\n-\tvmul.f64\td25, d28, d25\n-\tvldr\td26, [r7]\n-\tvmul.f64\td24, d28, d24\n-\tblt.w\t4050 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xfb0>\n-\tudiv\tr3, r8, lr\n-\tcmp\tsl, ip\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tblt.w\t3e48 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xda8>\n-\tsub.w\tr3, fp, sl\n-\tadd\tr3, r8\n-\tstrd\tsl, r0, [sp, #180]\t@ 0xb4\n-\tstr\tr4, [sp, #188]\t@ 0xbc\n-\tmov\tr0, ip\n-\tmov\tr4, r3\n-\tstr\tr6, [sp, #132]\t@ 0x84\n-\tcmp.w\tr9, #0\n-\tblt.w\t4040 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xfa0>\n-\tudiv\tr2, r4, r9\n-\tcmp\tfp, r0\n-\tblt.w\t3e2a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd8a>\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tcmp\tr3, #0\n-\tble.w\t3e2a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd8a>\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tmov\tr6, r8\n+\tldr\tr7, [sp, #100]\t@ 0x64\n \tadds\tr3, #1\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tadd\tr1, r0\n-\tstr.w\tr9, [sp, #96]\t@ 0x60\n-\tstrd\tfp, lr, [sp, #192]\t@ 0xc0\n-\tstrd\tip, r0, [sp, #200]\t@ 0xc8\n-\tstrd\tr4, r7, [sp, #208]\t@ 0xd0\n-\tstrd\tr8, r6, [sp, #216]\t@ 0xd8\n-\tldr.w\tsl, [sp, #60]\t@ 0x3c\n-\tmov\tfp, r1\n-\tmovs\tr3, #1\n-\tstrd\tr2, r1, [sp, #88]\t@ 0x58\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr2, r3, fp\n-\tcmp\tsl, r2\n-\tble.n\t3ae4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa44>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadds\tr4, r3, r2\n-\tcmp\tsl, r4\n-\tble.n\t3af0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa50>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tadd.w\tr6, r3, fp\n-\tcmp\tsl, r6\n-\tble.n\t3afe <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa5e>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr6, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadds\tr0, r3, r6\n-\tcmp\tsl, r0\n-\tble.n\t3b0a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa6a>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tip, r3, r0\n-\tcmp\tsl, ip\n-\tble.n\t3b18 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa78>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tip, r3\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tadd\tr1, r6\n-\tcmp\tsl, r1\n-\tble.n\t3b24 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa84>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr1, r3\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tadd\tr5, r1\n-\tcmp\tsl, r5\n-\tble.n\t3b30 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa90>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, r3\n-\tldr\tr7, [sp, #40]\t@ 0x28\n-\tadd\tr7, r5\n-\tcmp\tsl, r7\n-\tble.n\t3b3c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa9c>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r3\n-\tldr\tr3, [sp, #276]\t@ 0x114\n-\tcmp\tr3, #0\n-\tble.w\t3dee <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd4e>\n-\tadd.w\tr5, r5, #536870912\t@ 0x20000000\n-\tadd.w\tr3, ip, #536870912\t@ 0x20000000\n-\tsubs\tr5, #1\n-\tlsls\tr1, r1, #3\n-\tstr\tr1, [sp, #32]\n-\tadd.w\tr1, r2, #536870912\t@ 0x20000000\n+\tldr.w\tr8, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tcmp.w\tsl, #0\n+\tblt.w\t498e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1656>\n+\tmov\tr1, sl\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tblt.w\t4014 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcdc>\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tcmp\tr2, #0\n+\tble.w\t4014 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcdc>\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tadd\tr2, r6\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tstr\tr1, [sp, #48]\t@ 0x30\n+\tstr\tr4, [sp, #108]\t@ 0x6c\n+\tstr.w\tr9, [sp, #116]\t@ 0x74\n+\tstrd\tr5, fp, [sp, #132]\t@ 0x84\n+\tstrd\tsl, r3, [sp, #160]\t@ 0xa0\n+\tstrd\tr2, r7, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tadds\tr2, r3, r2\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #68]\t@ 0x44\n+\tcmp\tr2, r3\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\titt\tlt\n+\tldrlt\tr3, [sp, #56]\t@ 0x38\n+\taddlt\tr2, r2, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadds\tr0, r3, r2\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tcmp\tr0, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #56]\t@ 0x38\n+\taddlt\tr0, r0, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadds\tr7, r3, r1\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tcmp\tr7, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #56]\t@ 0x38\n+\taddlt\tr7, r7, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadd\tr3, r7\n+\tcmp\tr3, r1\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr3, r3, r1\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tadd.w\tip, r1, r3\n+\tcmp\tip, r4\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tadd\tr4, r7\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tip, r1\n+\tcmp\tr4, r5\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr4, r4, r1\n+\tadds\tr6, r5, r4\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\tcmp\tr6, r5\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr6, r6, r1\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tadd\tr5, r6\n+\tcmp\tr5, r1\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr5, r5, r1\n+\tldr\tr1, [sp, #356]\t@ 0x164\n+\tcmp\tr1, #0\n+\tble.w\t3fd4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xc9c>\n \tlsls\tr5, r5, #3\n \tstr\tr5, [sp, #8]\n-\tldr\tr5, [sp, #276]\t@ 0x114\n-\tsubs\tr1, #1\n-\tlsls\tr7, r7, #3\n-\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n-\tadd.w\tip, r5, r2\n-\tldr\tr5, [sp, #84]\t@ 0x54\n-\tstr\tr7, [sp, #28]\n-\tadd.w\tr7, fp, #536870912\t@ 0x20000000\n-\tlsls\tr1, r1, #3\n-\tsubs\tr4, #1\n-\tadd.w\tr5, r5, ip, lsl #3\n-\tstr\tr5, [sp, #36]\t@ 0x24\n-\tldr\tr5, [sp, #52]\t@ 0x34\n-\tsubs\tr7, #1\n+\tldr\tr5, [sp, #40]\t@ 0x28\n+\tmov.w\tr1, ip, lsl #3\n+\tlsls\tr4, r4, #3\n+\tstr\tr4, [sp, #12]\n+\tldr\tr4, [sp, #72]\t@ 0x48\n \tlsls\tr2, r2, #3\n-\tadd.w\tr6, r6, #536870912\t@ 0x20000000\n-\tnegs\tr2, r2\n+\tmov.w\tip, r5, lsl #3\n+\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tlsls\tr0, r0, #3\n+\tadd.w\tfp, r4, r2\n+\tadd\tr2, r5\n \tstr\tr2, [sp, #24]\n-\tadds\tr2, r5, r1\n-\tstr\tr2, [sp, #0]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n+\tmov\tr2, r5\n+\tadd.w\tsl, r4, r0\n+\tadd\tr0, r5\n+\tadd.w\tr5, r4, ip\n+\tadd\tip, r2\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tlsls\tr7, r7, #3\n-\tlsls\tr4, r4, #3\n-\tsubs\tr6, #1\n-\tadd.w\tr9, r5, r4\n-\tadd.w\tr8, r5, r7\n-\tadd.w\tr0, r0, #536870912\t@ 0x20000000\n-\tadds\tr5, r2, r7\n-\tldr\tr7, [sp, #52]\t@ 0x34\n+\tlsls\tr3, r3, #3\n \tlsls\tr6, r6, #3\n-\tsubs\tr0, #1\n-\tsubs\tr3, #1\n-\tadd\tr4, r2\n+\tstr\tr5, [sp, #16]\n+\tadd.w\tr9, r4, r3\n+\tadds\tr5, r4, r7\n+\tadd\tr3, r2\n+\tadd.w\tlr, r4, r1\n+\tstr\tr5, [sp, #32]\n \tadd\tr1, r2\n-\tadds\tr2, r7, r6\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tlsls\tr3, r3, #3\n-\tlsls\tr0, r0, #3\n-\tadd.w\tip, r7, r3\n-\tadd.w\tlr, r7, r0\n+\tadds\tr5, r2, r7\n+\tmov\tr7, r4\n+\tstr\tr5, [sp, #4]\n+\tadds\tr5, r4, r6\n \tadd\tr6, r2\n-\tadd\tr0, r2\n-\tadds\tr7, r2, r3\n+\tstr\tr5, [sp, #28]\n+\tmov\tr5, r2\n+\tmov\tr2, r4\n+\tldr\tr4, [sp, #8]\n+\tadd\tr7, r4\n+\tadd\tr4, r5\n+\tmov\tr5, r4\n+\tldr\tr4, [sp, #12]\n+\tadd\tr2, r4\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadd\tr2, r4\n+\tldr\tr4, [sp, #16]\n+\tstr\tr2, [sp, #12]\n+\tmovs\tr2, #1\n+\tstr\tr3, [sp, #16]\n+\tstr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #24]\n+\tvldr\td4, [sl, #-8]\n+\tvldr\td7, [r0, #-8]\n+\tvldr\td6, [fp, #-8]\n+\tvldr\td5, [r2, #-8]\n+\tvldr\td10, [ip, #-8]\n+\tvldr\td2, [r4, #-8]\n+\tvadd.f64\td9, d6, d4\n+\tvadd.f64\td3, d5, d7\n+\tvsub.f64\td6, d6, d4\n+\tvmov.f64\td11, d10\n+\tvsub.f64\td5, d5, d7\n+\tvmov.f64\td0, d2\n+\tldr\tr3, [sp, #4]\n+\tvmls.f64\td0, d9, d8\n+\tldr\tr2, [sp, #32]\n+\tvmls.f64\td11, d3, d8\n+\tvmul.f64\td6, d6, d14\n+\tvmul.f64\td5, d5, d14\n+\tvadd.f64\td3, d3, d10\n+\tvldr\td7, [r3, #-8]\n+\tvadd.f64\td2, d9, d2\n+\tldr\tr3, [sp, #20]\n+\tvldr\td4, [r2, #-8]\n+\tvstr\td3, [ip, #-8]\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #20]\n+\tadd\tip, r8\n+\tvsub.f64\td3, d0, d5\n+\tldr\tr3, [sp, #4]\n+\tvadd.f64\td10, d0, d5\n+\tvadd.f64\td5, d6, d11\n+\tvstr\td2, [r4, #-8]\n+\tvsub.f64\td11, d11, d6\n+\tadd\tr4, r8\n+\tvstr\td3, [r2, #-8]\n+\tadd\tr2, r8\n+\tvstr\td5, [r3, #-8]\n+\tldr\tr3, [sp, #16]\n+\tvldr\td5, [lr, #-8]\n+\tvldr\td6, [r9, #-8]\n+\tvldr\td12, [r1, #-8]\n+\tvldr\td1, [r3, #-8]\n+\tvadd.f64\td9, d6, d5\n+\tldr\tr3, [sp, #28]\n+\tvsub.f64\td6, d6, d5\n+\tstr\tr2, [sp, #32]\n+\tvadd.f64\td0, d1, d12\n+\tvsub.f64\td5, d1, d12\n+\tvmov.f64\td1, d4\n+\tvldr\td3, [r6, #-8]\n+\tvmls.f64\td1, d9, d8\n+\tvldr\td2, [r3, #-8]\n+\tldr\tr3, [sp, #4]\n+\tvadd.f64\td4, d4, d9\n+\tvmul.f64\td5, d5, d14\n+\tvadd.f64\td9, d7, d0\n+\tadd.w\tr2, r3, r8\n+\tvmls.f64\td7, d0, d8\n+\tstr\tr2, [sp, #4]\n+\tvmul.f64\td6, d6, d14\n+\tldr\tr2, [sp, #24]\n+\tvstr\td4, [fp, #-8]\n+\tadd\tfp, r8\n+\tvsub.f64\td4, d1, d5\n+\tvadd.f64\td5, d1, d5\n+\tvstr\td9, [r2, #-8]\n+\tadd\tr2, r8\n+\tstr\tr2, [sp, #24]\n+\tldr\tr3, [sp, #28]\n+\tvadd.f64\td1, d6, d7\n \tldr\tr2, [sp, #8]\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstrd\tsl, fp, [sp, #68]\t@ 0x44\n-\tadd\tr3, r2\n+\tvsub.f64\td7, d7, d6\n+\tvstr\td4, [r9, #-8]\n+\tadd\tr9, r8\n+\tvstr\td5, [r3, #-8]\n+\tadd\tr3, r8\n+\tvldr\td5, [r2, #-8]\n+\tldr\tr2, [sp, #16]\n+\tvldr\td6, [r7, #-8]\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #16]\n+\tvstr\td1, [r2, #-8]\n+\tvadd.f64\td1, d2, d6\n+\tldr\tr2, [sp, #12]\n+\tvsub.f64\td6, d2, d6\n+\tvstr\td7, [r6, #-8]\n+\tadd\tr3, r8\n+\tvldr\td7, [r5, #-8]\n+\tadd\tr6, r8\n+\tstr\tr3, [sp, #16]\n+\tvldr\td4, [r2, #-8]\n+\tvmul.f64\td6, d6, d14\n+\tvadd.f64\td2, d3, d7\n+\tldr\tr2, [sp, #8]\n+\tvsub.f64\td7, d3, d7\n+\tvmov.f64\td3, d5\n+\tvmls.f64\td3, d1, d8\n+\tvadd.f64\td1, d1, d5\n+\tvmov.f64\td5, d4\n+\tvmls.f64\td5, d2, d8\n+\tvstr\td10, [r2, #-8]\n+\tldr\tr2, [sp, #12]\n+\tvmul.f64\td7, d7, d14\n+\tvadd.f64\td2, d2, d4\n+\tvstr\td1, [sl, #-8]\n+\tadd\tsl, r8\n+\tvstr\td11, [r2, #-8]\n+\tldr\tr2, [sp, #8]\n+\tvsub.f64\td4, d3, d7\n+\tvadd.f64\td3, d3, d7\n+\tvstr\td2, [r0, #-8]\n+\tadd.w\tr3, r2, r8\n+\tvadd.f64\td7, d6, d5\n+\tldr\tr2, [sp, #12]\n+\tvsub.f64\td5, d5, d6\n \tstr\tr3, [sp, #8]\n+\tadd\tr0, r8\n+\tadd\tr2, r8\n+\tldr\tr3, [sp, #20]\n+\tstr\tr2, [sp, #12]\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tvstr\td4, [lr, #-8]\n+\tadd\tlr, r8\n+\tvstr\td7, [r1, #-8]\n+\tcmp\tr3, r2\n+\tvstr\td3, [r7, #-8]\n+\tadd\tr1, r8\n+\tvstr\td5, [r5, #-8]\n+\tadd\tr7, r8\n+\tadd\tr5, r8\n+\tbne.w\t3e20 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xae8>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tcmp\tr3, r2\n+\tbge.n\t3fe8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcb0>\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr4, [sp, #16]\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tcmp\tr3, r2\n+\tbne.w\t3d2c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9f4>\n+\tldrd\tsl, r3, [sp, #160]\t@ 0xa0\n+\tldrd\tr2, r7, [sp, #172]\t@ 0xac\n+\tsubs\tr3, #1\n+\tldr\tr4, [sp, #108]\t@ 0x6c\n+\tadds\tr1, r3, #1\n+\tldr.w\tr9, [sp, #116]\t@ 0x74\n+\tadd\tr2, sl\n+\tldrd\tr5, fp, [sp, #132]\t@ 0x84\n+\tbne.w\t3d14 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9dc>\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tsubs\tr4, #1\n+\tadd\tr6, fp\n+\tsub.w\tr7, r7, fp\n+\tadd\tr3, fp\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tadds\tr3, r4, #1\n+\tbne.w\t3cec <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9b4>\n+\tmov\tr6, r5\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tldr\tr2, [sp, #352]\t@ 0x160\n+\tcmp\tr3, r2\n+\tbeq.w\t4984 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x164c>\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr7, [sp, #124]\t@ 0x7c\n+\tlsls\tr5, r3, #1\n+\tsub.w\tr4, r9, r7\n+\tcmp\tr7, #0\n+\tblt.w\t4966 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x162e>\n+\tmov\tr1, r7\n+\tsubs\tr0, r4, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr7, r4\n+\tstr\tr0, [sp, #132]\t@ 0x84\n+\tbgt.w\t4976 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x163e>\n+\tadd.w\tr3, r6, r6, lsl #1\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tnegs\tr3, r3\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tlsls\tr2, r5, #4\n+\tvmov.f64\td13, #96\t@ 0x3f000000 0.5\n+\tcmp\tr3, #1\n+\tmov.w\tr3, r5, lsl #3\n+\tbne.w\t44de <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x11a6>\n+\tstr\tr2, [sp, #204]\t@ 0xcc\n+\tmov\tr8, r3\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tldrd\tr4, r1, [sp, #120]\t@ 0x78\n+\tadd\tr2, r3\n+\tadds\tr0, r2, r3\n+\tstr\tr0, [sp, #176]\t@ 0xb0\n+\tmov\tsl, r0\n+\tldr\tr0, [sp, #100]\t@ 0x64\n+\tldr\tr7, [sp, #96]\t@ 0x60\n+\tmov\tr9, r1\n+\tsubs\tr5, r1, r0\n+\tsubs\tr4, r4, r1\n+\tstr\tr4, [sp, #136]\t@ 0x88\n+\tvldr\td7, [sp, #144]\t@ 0x90\n+\tcmp.w\tfp, #0\n+\tvldr\td11, [r2, #8]\n+\tvldr\td15, [sl, #8]\n+\tvldr\td10, [r2]\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td12, [sl]\n+\tvmul.f64\td15, d7, d15\n+\tblt.w\t44c2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x118a>\n+\tldr\tr0, [sp, #136]\t@ 0x88\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tmov\tr6, r0\n+\tcmp\tr3, r9\n+\tblt.w\t4488 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1150>\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tsubs\tr4, r2, r3\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tadds\tr3, r4, r3\n+\tmov\tr4, r9\n+\tstrd\tr3, r5, [sp, #160]\t@ 0xa0\n+\tcmp\tr7, #0\n+\tblt.w\t44ae <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1176>\n+\tldr\tr0, [sp, #160]\t@ 0xa0\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tblt.w\t4470 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1138>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tr3, #0\n+\tble.w\t4470 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1138>\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tadds\tr3, #1\n+\tstr\tr7, [sp, #116]\t@ 0x74\n+\tadd\tr1, r4\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tstrd\tfp, r9, [sp, #212]\t@ 0xd4\n+\tstrd\tr6, r4, [sp, #220]\t@ 0xdc\n+\tstrd\tr8, sl, [sp, #228]\t@ 0xe4\n+\tstr\tr5, [sp, #236]\t@ 0xec\n+\tldr.w\tfp, [sp, #68]\t@ 0x44\n+\tmov\tsl, r1\n+\tmovs\tr3, #1\n+\tstrd\tr2, r1, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr7, [sp, #52]\t@ 0x34\n+\tadd.w\tr1, r3, sl\n+\tcmp\tfp, r1\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadds\tr6, r3, r1\n+\tcmp\tfp, r6\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr6, r6, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tr2, r3, sl\n+\tcmp\tfp, r2\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadds\tr4, r3, r2\n+\tcmp\tfp, r4\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr4, r4, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadd.w\tip, r3, r4\n+\tcmp\tfp, ip\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadds\tr0, r3, r2\n+\tcmp\tfp, r0\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadd\tr3, r0\n+\tcmp\tfp, r3\n+\titt\tgt\n+\tldrgt\tr5, [sp, #56]\t@ 0x38\n+\taddgt\tr3, r3, r5\n+\tadd\tr7, r3\n+\tcmp\tfp, r7\n+\titt\tgt\n+\tldrgt\tr5, [sp, #56]\t@ 0x38\n+\taddgt\tr7, r7, r5\n+\tldr\tr5, [sp, #356]\t@ 0x164\n+\tcmp\tr5, #0\n+\tble.w\t4436 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10fe>\n+\tadd.w\tr3, r3, #536870912\t@ 0x20000000\n+\tadd.w\tr5, ip, #536870912\t@ 0x20000000\n+\tsubs\tr3, #1\n+\tadd.w\tr6, r6, #536870912\t@ 0x20000000\n+\tsubs\tr6, #1\n+\tadd.w\tr2, r2, #536870912\t@ 0x20000000\n+\tlsls\tr3, r3, #3\n+\tstr\tr3, [sp, #4]\n+\tlsls\tr3, r7, #3\n+\tstr\tr3, [sp, #28]\n+\tlsls\tr3, r0, #3\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tadd.w\tr0, r1, #536870912\t@ 0x20000000\n+\tsubs\tr0, #1\n+\tadd.w\tr7, sl, #536870912\t@ 0x20000000\n+\tadd.w\tip, r3, r1\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tlsls\tr1, r1, #3\n+\tlsls\tr0, r0, #3\n+\tlsls\tr6, r6, #3\n+\tsubs\tr7, #1\n+\tadd.w\tr3, r3, ip, lsl #3\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tnegs\tr3, r1\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #24]\n+\tsubs\tr2, #1\n+\tadds\tr3, r1, r0\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr9, r1, r6\n+\tlsls\tr7, r7, #3\n+\tadd.w\tr4, r4, #536870912\t@ 0x20000000\n+\tadd\tr0, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tlsls\tr2, r2, #3\n+\tadd.w\tr8, r1, r7\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tsubs\tr4, #1\n+\tsubs\tr5, #1\n+\tadd\tr7, r3\n+\tmov\tr3, r1\n \tadd\tr3, r2\n-\tstr\tr0, [sp, #20]\n-\tldr\tr2, [sp, #0]\n \tstr\tr3, [sp, #12]\n-\tstr\tr5, [sp, #0]\n-\tldr\tr5, [sp, #16]\n-\tldr\tr3, [sp, #0]\n-\tvldr\td31, [r1]\n-\tvldr\td20, [r9]\n-\tvldr\td21, [r5]\n-\tvldr\td22, [r2]\n-\tvldr\td17, [r3]\n-\tvadd.f64\td30, d21, d31\n-\tvldr\td19, [r8]\n-\tvadd.f64\td29, d20, d22\n-\tvsub.f64\td31, d31, d21\n-\tvmov.f64\td21, d17\n-\tvsub.f64\td22, d22, d20\n-\tvmov.f64\td6, d19\n-\tldr\tr0, [sp, #0]\n-\tvfms.f64\td21, d30, d18\n-\tvadd.f64\td5, d17, d30\n-\tvfms.f64\td6, d29, d18\n-\tvadd.f64\td29, d19, d29\n-\tvfnms.f64\td17, d30, d18\n-\tldr\tr4, [sp, #20]\n-\tldr\tr3, [sp, #4]\n-\tvldr\td7, [r6]\n-\tvstmia\tr0!, {d5}\n-\tvfma.f64\td17, d16, d22\n-\tstr\tr0, [sp, #0]\n-\tvldr\td20, [r3]\n-\tvmov.f64\td5, d7\n-\tvmov.f64\td19, d21\n-\tvfma.f64\td21, d23, d22\n-\tvfma.f64\td19, d16, d22\n-\tvmov.f64\td30, d6\n-\tvfma.f64\td30, d31, d23\n-\tvfma.f64\td6, d16, d31\n-\tvstmia\tr8!, {d29}\n-\tldr\tr0, [sp, #8]\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td21, d21, d26\n-\tvmul.f64\td22, d19, d27\n-\tvnmul.f64\td19, d25, d19\n-\tvfma.f64\td22, d30, d25\n-\tvfma.f64\td19, d30, d27\n-\tvfma.f64\td17, d6, d26\n-\tvfma.f64\td21, d6, d24\n-\tvstmia\tr6!, {d22}\n-\tvldr\td31, [r7]\n-\tvldr\td4, [r4]\n-\tvstmia\tr3!, {d19}\n-\tvldr\td22, [ip]\n-\tvldr\td29, [lr]\n-\tvadd.f64\td6, d31, d4\n-\tvsub.f64\td4, d4, d31\n-\tvmov.f64\td31, d20\n-\tstr\tr3, [sp, #4]\n-\tvadd.f64\td3, d22, d29\n-\tvsub.f64\td29, d29, d22\n-\tvmov.f64\td22, d7\n-\tvfnms.f64\td5, d6, d18\n-\tvfms.f64\td22, d6, d18\n-\tvadd.f64\td6, d6, d7\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tlsls\tr4, r4, #3\n+\tlsls\tr5, r5, #3\n+\tadd.w\tlr, r1, r4\n+\tadds\tr2, r3, r2\n+\tadd.w\tip, r1, r5\n+\tstr\tr2, [sp, #16]\n+\tmov\tr2, r1\n+\tldr\tr1, [sp, #4]\n+\tadd\tr4, r3\n+\tadd\tr5, r3\n+\tstrd\tfp, sl, [sp, #80]\t@ 0x50\n+\tadd\tr2, r1\n+\tadd\tr3, r1\n+\tstr\tr2, [sp, #4]\n+\tldr\tr1, [sp, #8]\n+\tstr\tr3, [sp, #20]\n+\tstr\tr4, [sp, #8]\n+\tvldr\td6, [r9]\n+\tvldr\td7, [r1]\n+\tvldr\td8, [r8]\n+\tvldr\td4, [r6]\n+\tvadd.f64\td3, d6, d7\n+\tvldr\td5, [r0]\n+\tvsub.f64\td7, d7, d6\n+\tvmov.f64\td6, d8\n \tldr\tr3, [sp, #12]\n-\tvfms.f64\td31, d3, d18\n-\tvadd.f64\td3, d3, d20\n-\tvfma.f64\td5, d16, d29\n-\tvldr\td30, [r0]\n-\tvldr\td19, [r3]\n-\tvstmia\tr1!, {d6}\n-\tvstmia\tr2!, {d3}\n-\tvmov.f64\td20, d22\n-\tvfma.f64\td22, d29, d23\n-\tvfma.f64\td20, d16, d29\n-\tvmov.f64\td7, d31\n-\tvfma.f64\td31, d16, d4\n-\tvfma.f64\td7, d4, d23\n-\tvmul.f64\td29, d5, d24\n-\tvmul.f64\td22, d22, d26\n-\tvmul.f64\td6, d20, d27\n-\tvnmul.f64\td20, d25, d20\n-\tvfma.f64\td22, d31, d24\n-\tvfma.f64\td29, d31, d26\n-\tvfma.f64\td6, d7, d25\n-\tvfma.f64\td20, d7, d27\n-\tvstmia\tr4!, {d6}\n-\tvstmia\tr3!, {d22}\n-\tstr\tr4, [sp, #20]\n+\tvadd.f64\td1, d4, d5\n+\tvsub.f64\td5, d5, d4\n+\tvmls.f64\td6, d3, d13\n+\tvadd.f64\td3, d8, d3\n+\tvldr\td0, [r7]\n+\tvmul.f64\td7, d7, d14\n+\tvldr\td2, [r3]\n+\tvmul.f64\td4, d1, d13\n+\tvmul.f64\td5, d5, d14\n+\tvstmia\tr8!, {d3}\n+\tvadd.f64\td8, d0, d1\n+\tldr\tr4, [sp, #32]\n+\tvsub.f64\td3, d6, d5\n+\tvadd.f64\td6, d5, d6\n+\tvsub.f64\td5, d0, d4\n+\tvsub.f64\td4, d4, d0\n+\tvmul.f64\td9, d6, d12\n+\tvmul.f64\td6, d6, d15\n+\tvadd.f64\td4, d4, d7\n+\tvmul.f64\td1, d3, d11\n+\tvmla.f64\td9, d4, d15\n+\tvadd.f64\td4, d5, d7\n+\tvsub.f64\td5, d5, d7\n+\tvmul.f64\td7, d4, d11\n+\tvmla.f64\td1, d4, d10\n+\tvmla.f64\td6, d5, d12\n+\tvmov.f64\td4, d2\n+\tvnmls.f64\td7, d3, d10\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvstmia\tr3!, {d7}\n+\tvldr\td5, [ip]\n+\tvldr\td6, [lr]\n \tstr\tr3, [sp, #12]\n+\tldr\tr3, [sp, #4]\n+\tvadd.f64\td7, d5, d6\n+\tvsub.f64\td6, d6, d5\n+\tvldr\td5, [r3]\n+\tvmls.f64\td4, d7, d13\n+\tvadd.f64\td7, d7, d2\n \tldr\tr3, [sp, #24]\n-\tvstmia\tlr!, {d20}\n-\tvstmia\tr0!, {d29}\n-\tadd.w\tfp, r1, r3\n-\tstr\tr0, [sp, #8]\n-\tadds\tr3, r2, r3\n-\tldr\tr0, [sp, #28]\n+\tvmul.f64\td6, d6, d14\n+\tvstmia\tr1!, {d7}\n+\tadds\tr2, r1, r3\n+\tldr\tr3, [sp, #28]\n+\tadd.w\tfp, r2, r3\n+\tldr\tr3, [sp, #16]\n+\tadd\tr2, r4\n+\tldr\tr4, [sp, #8]\n+\tstr\tr2, [sp, #36]\t@ 0x24\n+\tldr\tr2, [sp, #20]\n+\tvldr\td2, [r3]\n+\tvstmia\tr7!, {d8}\n+\tvstmia\tr3!, {d1}\n+\tvldr\td3, [r4]\n+\tvldr\td7, [r5]\n+\tvldr\td0, [r2]\n+\tstr\tr3, [sp, #16]\n+\tvadd.f64\td1, d7, d3\n+\tvsub.f64\td7, d3, d7\n+\tvmul.f64\td3, d1, d13\n+\tvadd.f64\td1, d1, d2\n+\tvmul.f64\td7, d7, d14\n+\tvstmia\tr0!, {d1}\n+\tvsub.f64\td1, d2, d3\n+\tvsub.f64\td3, d3, d2\n+\tvsub.f64\td2, d4, d7\n+\tvadd.f64\td7, d7, d4\n+\tldr\tr3, [sp, #24]\n+\tldr\tr4, [sp, #28]\n+\tvadd.f64\td4, d1, d6\n+\tvsub.f64\td1, d1, d6\n+\tvadd.f64\td3, d3, d6\n+\tvmul.f64\td6, d2, d11\n+\tadds\tr3, r0, r3\n+\tadd.w\tsl, r3, r4\n \tldr\tr4, [sp, #32]\n-\tadd.w\tsl, fp, r0\n-\tadd\tfp, r4\n-\tvldr\td31, [sl, #-8]\n-\tvldr\td22, [fp, #-8]\n-\tvstr\td21, [fp, #-8]\n-\tadd.w\tfp, r3, r0\n-\tvadd.f64\td29, d31, d19\n+\tvmla.f64\td6, d4, d10\n+\tvmul.f64\td4, d4, d11\n \tadd\tr3, r4\n-\tvmov.f64\td20, d22\n-\tvmov.f64\td21, d22\n-\tvsub.f64\td31, d19, d31\n-\tvldr\td19, [fp, #-8]\n-\tvadd.f64\td22, d22, d29\n-\tvfms.f64\td20, d29, d18\n-\tvadd.f64\td7, d19, d30\n-\tvfnms.f64\td21, d29, d18\n-\tvsub.f64\td19, d30, d19\n-\tvstmia\tr5!, {d22}\n-\tvldr\td22, [r3, #-8]\n-\tvstr\td17, [r3, #-8]\n-\tvfma.f64\td21, d16, d19\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tvmov.f64\td29, d22\n-\tvmov.f64\td17, d20\n-\tvfms.f64\td29, d7, d18\n-\tvfma.f64\td17, d16, d19\n-\tvfma.f64\td20, d19, d23\n-\tvadd.f64\td22, d22, d7\n-\tcmp\tr2, r3\n-\tstr\tr5, [sp, #16]\n-\tvstmia\tr9!, {d22}\n-\tvmul.f64\td21, d21, d24\n-\tvmov.f64\td30, d29\n-\tvfma.f64\td29, d16, d31\n-\tvfma.f64\td30, d23, d31\n-\tvnmul.f64\td22, d25, d17\n-\tvmul.f64\td19, d20, d26\n-\tvmul.f64\td17, d17, d27\n-\tvfma.f64\td21, d29, d26\n-\tvfma.f64\td19, d29, d24\n-\tvfma.f64\td22, d30, d27\n-\tvfma.f64\td17, d30, d25\n-\tvstmia\tip!, {d22}\n-\tvstmia\tr7!, {d17}\n-\tvstr\td21, [fp, #-8]\n-\tvstr\td19, [sl, #-8]\n-\tbne.w\t3be0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xb40>\n-\tldrd\tsl, fp, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #8]\n+\tvnmls.f64\td4, d2, d10\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvstmia\tr4!, {d6}\n+\tvmul.f64\td6, d7, d15\n+\tvmla.f64\td6, d1, d12\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d3, d15\n+\tstr\tr4, [sp, #8]\n+\tvstmia\tlr!, {d4}\n+\tvstmia\tr2!, {d6}\n+\tstr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #4]\n+\tvldr\td6, [r3, #-8]\n+\tvstmia\tr2!, {d7}\n+\tstr\tr2, [sp, #4]\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tvldr\td3, [fp, #-8]\n+\tvldr\td7, [sl, #-8]\n+\tvstr\td2, [r3, #-8]\n+\tvldr\td4, [r2, #-8]\n+\tvadd.f64\td1, d3, d5\n+\tvsub.f64\td5, d5, d3\n+\tvadd.f64\td3, d7, d0\n+\tvsub.f64\td7, d0, d7\n+\tvstr\td9, [r2, #-8]\n+\tvmov.f64\td2, d4\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvmls.f64\td2, d1, d13\n+\tvadd.f64\td4, d4, d1\n+\tvadd.f64\td1, d6, d3\n+\tvmul.f64\td3, d3, d13\n+\tvmul.f64\td5, d5, d14\n+\tvmul.f64\td7, d7, d14\n+\tcmp\tr1, r3\n+\tvstmia\tr9!, {d4}\n+\tvsub.f64\td4, d3, d6\n+\tvsub.f64\td6, d6, d3\n+\tvstmia\tr6!, {d1}\n+\tvsub.f64\td3, d2, d7\n+\tvadd.f64\td7, d7, d2\n+\tvadd.f64\td2, d6, d5\n+\tvadd.f64\td4, d4, d5\n+\tvsub.f64\td6, d6, d5\n+\tvmul.f64\td1, d3, d11\n+\tvmul.f64\td5, d7, d12\n+\tvmul.f64\td0, d2, d11\n+\tvmul.f64\td7, d7, d15\n+\tvmla.f64\td1, d2, d10\n+\tvmla.f64\td5, d4, d15\n+\tvmla.f64\td7, d6, d12\n+\tvnmls.f64\td0, d3, d10\n+\tvstmia\tr5!, {d1}\n+\tvstr\td7, [sl, #-8]\n+\tvstmia\tip!, {d0}\n+\tvstr\td5, [fp, #-8]\n+\tbne.w\t4222 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xeea>\n+\tldrd\tfp, sl, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tadd\tsl, r3\n+\tcmp\tfp, sl\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tsl, r3\n \tldr\tr3, [sp, #76]\t@ 0x4c\n-\tadd\tfp, r3\n-\tcmp\tsl, fp\n-\tble.n\t3dfa <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd5a>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #80]\t@ 0x50\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr3, r2\n-\tbne.w\t3ad6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa36>\n-\tldrd\tr2, r1, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tbne.w\t4118 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xde0>\n+\tldrd\tr2, r1, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \tsubs\tr2, #1\n \tadd\tr1, r3\n \tadds\tr0, r2, #1\n-\tbne.w\t3ac8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa28>\n-\tldrd\tfp, lr, [sp, #192]\t@ 0xc0\n-\tmov\tr9, r3\n-\tldrd\tip, r0, [sp, #200]\t@ 0xc8\n-\tldrd\tr4, r7, [sp, #208]\t@ 0xd0\n-\tldrd\tr8, r6, [sp, #216]\t@ 0xd8\n-\tadd\tr0, lr\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tsub.w\tr4, r4, lr\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tadd\tr2, lr\n-\tadds\tr3, #1\n-\tstr\tr2, [sp, #132]\t@ 0x84\n-\tbne.w\t3a8e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9ee>\n-\tldrd\tsl, r0, [sp, #180]\t@ 0xb4\n-\tldr\tr4, [sp, #188]\t@ 0xbc\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tsubs\tr0, #1\n-\tldr\tr2, [sp, #168]\t@ 0xa8\n-\tadds\tr1, r0, #1\n-\tadd\tip, r3\n-\tsub.w\tr8, r8, r3\n-\tadd\tr6, r3\n-\tadd\tr7, r2\n-\tmov\tr3, r4\n-\tbeq.w\t4516 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1476>\n-\tldr\tr2, [sp, #164]\t@ 0xa4\n-\tadd\tr4, r2\n-\tb.n\t3a50 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9b0>\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tlsls\tr2, r1, #3\n-\tlsls\tr1, r1, #4\n-\tstr\tr2, [sp, #16]\n-\tstr\tr1, [sp, #20]\n-\tmov\tr1, r2\n-\tadds\tr2, r4, r2\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tadds\tr5, r2, r1\n-\tmov\tr8, r0\n-\tsubs\tr1, r0, r4\n-\tsubs\tr4, r4, r0\n-\tstr\tr4, [sp, #12]\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tldr\tr4, [sp, #276]\t@ 0x114\n-\tstr\tr1, [sp, #8]\n-\tmov\tr1, r5\n-\tadd.w\tlr, r4, #1\n-\tstr.w\tr9, [sp, #4]\n-\tvldr\td22, [r2, #8]\n-\tcmp\tr6, #0\n-\tvldr\td24, [r1, #8]\n-\tvldr\td25, [r2]\n-\tvmul.f64\td22, d28, d22\n-\tvldr\td26, [r1]\n-\tvmul.f64\td24, d28, d24\n-\tblt.w\t4020 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf80>\n-\tldr\tr2, [sp, #12]\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tcmp\tr4, r8\n-\tudiv\tr2, r2, r6\n-\tblt.w\t3ffc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf5c>\n-\tldr\tr4, [sp, #104]\t@ 0x68\n-\tcmp\tr4, #0\n-\tble.w\t3ffc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf5c>\n-\tadd.w\tr4, ip, r8\n-\tstr\tr7, [sp, #24]\n-\tstr\tr0, [sp, #40]\t@ 0x28\n-\tstr.w\tr8, [sp, #56]\t@ 0x38\n-\tmov\tr8, r4\n-\tmov.w\tr9, #1\n-\tstrd\tr6, r2, [sp, #64]\t@ 0x40\n-\tstr\tr4, [sp, #72]\t@ 0x48\n-\tstrd\tr1, r5, [sp, #80]\t@ 0x50\n-\tldr\tr2, [sp, #4]\n-\tadd\tr2, r8\n-\tcmp\tr2, ip\n-\tbge.n\t3eee <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe4e>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #4]\n-\tadd\tr1, r2\n-\tcmp\tr1, ip\n-\tbge.n\t3efa <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe5a>\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tadd\tr1, r0\n-\tldr\tr0, [sp, #276]\t@ 0x114\n-\tcmp\tr0, #0\n-\tble.n\t3fca <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf2a>\n-\tlsls\tr2, r2, #3\n-\tlsls\tr1, r1, #3\n-\tmov.w\tr0, r8, lsl #3\n-\tadd.w\tr6, sl, r2\n-\tadd.w\tr5, sl, r1\n-\tadd.w\tr4, sl, r0\n-\tadd\tr2, fp\n-\tadd\tr1, fp\n-\tadd\tr0, fp\n-\tmovs\tr7, #1\n-\tvldr\td18, [r1, #-8]\n-\tadds\tr7, #1\n-\tvldr\td29, [r2, #-8]\n-\tcmp\tr7, lr\n-\tvldr\td17, [r5, #-8]\n-\tvldr\td20, [r6, #-8]\n-\tvldr\td27, [r0, #-8]\n-\tvadd.f64\td19, d29, d18\n-\tvldr\td31, [r4, #-8]\n-\tvsub.f64\td29, d29, d18\n-\tvadd.f64\td30, d20, d17\n-\tvsub.f64\td20, d20, d17\n-\tvmov.f64\td17, d27\n-\tvmov.f64\td18, d27\n-\tvfms.f64\td17, d19, d21\n-\tvmov.f64\td7, d31\n-\tvfnms.f64\td18, d19, d21\n-\tvadd.f64\td27, d19, d27\n-\tvfms.f64\td7, d30, d21\n-\tvadd.f64\td30, d30, d31\n-\tvfma.f64\td18, d16, d20\n-\tvstr\td27, [r0, #-8]\n-\tvstr\td30, [r4, #-8]\n-\tadd\tr0, r3\n-\tadd\tr4, r3\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td17, d20, d23\n-\tvfma.f64\td19, d16, d20\n-\tvmov.f64\td31, d7\n-\tvfma.f64\td7, d16, d29\n-\tvfma.f64\td31, d29, d23\n-\tvmul.f64\td18, d24, d18\n-\tvmul.f64\td17, d26, d17\n-\tvnmul.f64\td27, d19, d22\n-\tvmul.f64\td19, d25, d19\n-\tvfma.f64\td18, d26, d7\n-\tvfma.f64\td17, d24, d7\n-\tvfma.f64\td27, d25, d31\n-\tvfma.f64\td19, d22, d31\n-\tvstr\td27, [r6, #-8]\n-\tadd\tr6, r3\n-\tvstr\td19, [r2, #-8]\n-\tadd\tr2, r3\n-\tvstr\td18, [r5, #-8]\n-\tadd\tr5, r3\n-\tvstr\td17, [r1, #-8]\n-\tadd\tr1, r3\n-\tbne.n\t3f1c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe7c>\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadd\tr8, r2\n-\tcmp\tr8, ip\n-\tbge.n\t3fd6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf36>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr8, r2\n-\tldr\tr2, [sp, #0]\n-\tadd.w\tr9, r9, #1\n-\tcmp\tr9, r2\n-\tbne.n\t3ee2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe42>\n-\tldrd\tr6, r2, [sp, #64]\t@ 0x40\n-\tldr\tr4, [sp, #72]\t@ 0x48\n-\tsubs\tr2, #1\n-\tldrd\tr1, r5, [sp, #80]\t@ 0x50\n-\tadd\tr4, r6\n-\tadds\tr7, r2, #1\n-\tbne.w\t3ed2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe32>\n-\tldr\tr7, [sp, #24]\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tldr.w\tr8, [sp, #56]\t@ 0x38\n-\tldr\tr2, [sp, #20]\n-\tsubs\tr7, #1\n-\tadd\tr8, r0\n-\tadds\tr4, r7, #1\n-\tadd\tr1, r2\n-\tldr\tr2, [sp, #8]\n-\tadd\tr2, r0\n-\tstr\tr2, [sp, #8]\n-\tldr\tr2, [sp, #12]\n-\tsub.w\tr2, r2, r0\n-\tstr\tr2, [sp, #12]\n-\tmov\tr2, r5\n-\tbeq.w\t3642 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5a2>\n-\tldr\tr4, [sp, #16]\n-\tadd\tr5, r4\n-\tb.n\t3e92 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xdf2>\n-\tldr\tr4, [sp, #8]\n-\tnegs\tr2, r6\n-\tudiv\tr2, r4, r2\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tcmp\tr4, r8\n-\tble.w\t3ebe <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe1e>\n-\tb.n\t3ffc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xf5c>\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tcmp\tfp, r4\n-\tudiv\tr2, ip, r3\n-\tble.w\t36d6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x636>\n-\tb.n\t39e0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x940>\n+\tbne.w\t410a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xdd2>\n+\tldrd\tfp, r9, [sp, #212]\t@ 0xd4\n+\tmov\tr7, r3\n+\tldrd\tr6, r4, [sp, #220]\t@ 0xdc\n+\tldrd\tr8, sl, [sp, #228]\t@ 0xe4\n+\tldr\tr5, [sp, #236]\t@ 0xec\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tsubs\tr6, #1\n+\tadd\tr4, fp\n+\tsub.w\tr3, r3, fp\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tadd\tr3, fp\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tadds\tr3, r6, #1\n+\tbne.w\t40d2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd9a>\n \tldr\tr3, [sp, #132]\t@ 0x84\n-\tcmp\tfp, r0\n-\tldr\tr2, [sp, #140]\t@ 0x8c\n-\tudiv\tr2, r3, r2\n-\tble.w\t3aa0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xa00>\n-\tb.n\t3e2a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd8a>\n-\tsub.w\tr3, fp, sl\n-\trsb\tr2, lr, #0\n-\tadds\tr1, r3, r6\n-\tcmp\tsl, ip\n-\tudiv\tr2, r1, r2\n-\tstr\tr2, [sp, #128]\t@ 0x80\n-\tble.w\t3a80 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9e0>\n-\tb.n\t3e48 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xda8>\n-\tldr\tr1, [sp, #116]\t@ 0x74\n-\tlsls\tr3, r2, #3\n-\tldr\tr4, [sp, #108]\t@ 0x6c\n-\tlsls\tr2, r2, #4\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tmov\tip, r5\n-\tstr\tr2, [sp, #128]\t@ 0x80\n-\tmov\tr2, r3\n-\tadds\tr3, r1, r3\n-\tldr.w\tr8, [sp, #136]\t@ 0x88\n-\tadds\tr7, r3, r2\n-\tldr\tr1, [sp, #276]\t@ 0x114\n-\tsub.w\tr2, r4, fp\n-\tmov\tr0, r7\n-\tmov\tr5, r7\n-\tsub.w\tr6, sl, r4\n-\tmov\tr7, r2\n+\tldr\tr2, [sp, #204]\t@ 0xcc\n+\tsubs\tr1, r3, #1\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tadd\tsl, r2\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tadd\tr9, r3\n+\tadd\tr5, r3\n+\tsubs\tr2, r2, r3\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tstr\tr1, [sp, #132]\t@ 0x84\n \tadds\tr1, #1\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tstr\tr1, [sp, #32]\n-\tvldr\td21, [r3, #8]\n-\tcmp.w\tlr, #0\n-\tvldr\td22, [r0, #8]\n-\tvldr\td24, [r3]\n-\tvmul.f64\td21, d28, d21\n-\tvldr\td25, [r0]\n-\tvmul.f64\td22, d28, d22\n-\tblt.w\t48ba <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x181a>\n-\tudiv\tr2, r6, lr\n-\tcmp\tsl, r4\n-\tblt.w\t449c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13fc>\n-\tsub.w\tr3, fp, sl\n-\tadds\tr1, r3, r6\n-\tstrd\tip, r4, [sp, #164]\t@ 0xa4\n-\tmov\tr3, r4\n-\tstr\tr0, [sp, #180]\t@ 0xb4\n-\tmov\tr4, r2\n-\tmov\tr0, r1\n-\tstr\tr7, [sp, #80]\t@ 0x50\n-\tstr.w\tsl, [sp, #132]\t@ 0x84\n-\tstr\tr6, [sp, #184]\t@ 0xb8\n-\tcmp.w\tr9, #0\n-\tblt.w\t44bc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x141c>\n-\tudiv\tr2, r0, r9\n-\tcmp\tfp, r3\n-\tblt.w\t447c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13dc>\n-\tldr\tr6, [sp, #104]\t@ 0x68\n-\tcmp\tr6, #0\n-\tble.w\t447c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13dc>\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tadds\tr6, #1\n-\tstrd\tfp, lr, [sp, #188]\t@ 0xbc\n-\tadd\tr1, r3\n-\tstr\tr6, [sp, #72]\t@ 0x48\n-\tstrd\tr4, r3, [sp, #196]\t@ 0xc4\n-\tstrd\tr0, r7, [sp, #204]\t@ 0xcc\n-\tstr\tr5, [sp, #212]\t@ 0xd4\n-\tmovs\tr3, #1\n-\tstr\tr1, [sp, #36]\t@ 0x24\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tstrd\tr9, r2, [sp, #84]\t@ 0x54\n-\tstr\tr1, [sp, #92]\t@ 0x5c\n-\tldrd\tr2, r3, [sp, #36]\t@ 0x24\n-\tadds\tr2, r3, r2\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr3, r2\n-\tble.n\t4128 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1088>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tmov\tr2, r3\n+\tbeq.w\t4976 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x163e>\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tb.n\t408e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd56>\n+\tldr\tr1, [sp, #172]\t@ 0xac\n+\tldr\tr0, [sp, #164]\t@ 0xa4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tble.w\t40ea <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xdb2>\n+\tb.n\t4470 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1138>\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\trsb\tr1, fp, #0\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tsubs\tr4, r2, r3\n+\tadds\tr0, r4, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tmov\tr6, r0\n+\tcmp\tr3, r9\n+\tble.w\t40c8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd90>\n+\tb.n\t4488 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1150>\n+\tldrd\tr1, r7, [sp, #120]\t@ 0x78\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tldr\tr0, [sp, #112]\t@ 0x70\n+\tldr\tr2, [sp, #140]\t@ 0x8c\n+\tsubs\tr1, r1, r7\n+\tadds\tr0, #1\n+\tstr\tr1, [sp, #104]\t@ 0x68\n+\tstr\tr0, [sp, #84]\t@ 0x54\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #100]\t@ 0x64\n+\tadds\tr5, r2, r3\n+\tldr\tr0, [sp, #356]\t@ 0x164\n+\tmov\tr6, r5\n+\tsubs\tr1, r7, r1\n+\tldr.w\tr8, [sp, #168]\t@ 0xa8\n+\tadds\tr0, #1\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr0, r3\n+\tmov\tsl, r5\n+\tmov\tr3, r7\n+\tmov\tr5, r1\n+\tmov\tr7, r0\n+\tvldr\td7, [sp, #144]\t@ 0x90\n+\tcmp.w\tfp, #0\n+\tvldr\td12, [r2, #8]\n+\tvldr\td10, [r6, #8]\n+\tvldr\td15, [r2]\n+\tvmul.f64\td12, d7, d12\n+\tvldr\td11, [r6]\n+\tvmul.f64\td10, d7, d10\n+\tstr\tr3, [sp, #4]\n+\tblt.w\t4948 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1610>\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tldr\tr3, [sp, #4]\n+\tmov\tr9, r0\n+\tcmp\tr2, r3\n+\tblt.w\t4914 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15dc>\n+\tldr\tr1, [sp, #100]\t@ 0x64\n+\tsubs\tr4, r1, r2\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tstr\tr5, [sp, #108]\t@ 0x6c\n+\tadds\tr2, r4, r2\n+\tmov\tr4, r3\n+\tstr\tr2, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tstr\tr7, [sp, #204]\t@ 0xcc\n+\tstr\tr6, [sp, #212]\t@ 0xd4\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tcmp\tr3, #0\n+\tblt.w\t4934 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15fc>\n+\tmov\tr1, r3\n+\tldr\tr0, [sp, #116]\t@ 0x74\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tblt.w\t48f2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15ba>\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tcmp\tr2, #0\n+\tble.w\t48f2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15ba>\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstrd\tfp, r9, [sp, #216]\t@ 0xd8\n+\tadd\tr2, r4\n+\tstrd\tr4, r5, [sp, #224]\t@ 0xe0\n+\tstr.w\tsl, [sp, #232]\t@ 0xe8\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr2, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\tadds\tr1, r3, r2\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tcmp\tr3, r1\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadds\tr4, r3, r1\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tcmp\tr3, r4\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr4, r4, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadds\tr6, r3, r2\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tcmp\tr3, r6\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr6, r6, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tadds\tr2, r3, r6\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tcmp\tr3, r2\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tcmp\tr3, r0\n-\tble.n\t4136 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1096>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tadds\tr7, r3, r1\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr3, r7\n-\tble.n\t4146 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10a6>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr3, r7\n-\tcmp\tr1, r3\n-\tble.n\t4154 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10b4>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tldr\tr4, [sp, #60]\t@ 0x3c\n-\tadd.w\tip, r1, r3\n-\tcmp\tr4, ip\n-\tble.n\t4164 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10c4>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tip, r1\n-\tldr\tr4, [sp, #56]\t@ 0x38\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tadd\tr4, r7\n-\tcmp\tr5, r4\n-\tble.n\t4172 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10d2>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr4, r1\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tadds\tr6, r5, r4\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tcmp\tr5, r6\n-\tble.n\t4180 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10e0>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr6, r1\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr5, r6\n-\tcmp\tr1, r5\n-\tble.n\t418e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x10ee>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr5, r1\n-\tldr\tr1, [sp, #276]\t@ 0x114\n-\tcmp\tr1, #0\n-\tble.w\t443c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x139c>\n-\tlsls\tr5, r5, #3\n-\tstr\tr5, [sp, #4]\n-\tldr\tr5, [sp, #36]\t@ 0x24\n-\tmov.w\tr1, ip, lsl #3\n-\tlsls\tr4, r4, #3\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tlsls\tr2, r2, #3\n-\tmov.w\tip, r5, lsl #3\n-\tldr\tr5, [sp, #48]\t@ 0x30\n+\titt\tgt\n+\tldrgt\tr3, [sp, #56]\t@ 0x38\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr3, r6\n+\tcmp\tr5, r3\n+\titt\tgt\n+\tldrgt\tr5, [sp, #56]\t@ 0x38\n+\taddgt\tr3, r3, r5\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\tadd.w\tsl, r5, r3\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\tcmp\tr5, sl\n+\titt\tgt\n+\tldrgt\tr5, [sp, #56]\t@ 0x38\n+\taddgt\tsl, r5\n+\tldr\tr5, [sp, #52]\t@ 0x34\n+\tadd.w\tfp, r5, sl\n+\tldr\tr5, [sp, #68]\t@ 0x44\n+\tcmp\tr5, fp\n+\titt\tgt\n+\tldrgt\tr5, [sp, #56]\t@ 0x38\n+\taddgt\tfp, r5\n+\tldr\tr5, [sp, #356]\t@ 0x164\n+\tcmp\tr5, #0\n+\tble.w\t48b4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x157c>\n \tlsls\tr3, r3, #3\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tlsls\tr6, r6, #3\n-\tadd.w\tfp, r4, r2\n-\tadd\tr2, r5\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tadd.w\tr2, r4, ip\n-\tstr\tr2, [sp, #24]\n-\tmov\tr2, r5\n-\tadd.w\tr9, r4, r3\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #0]\n-\tadds\tr3, r4, r6\n-\tstr\tr3, [sp, #12]\n+\tldr\tr7, [sp, #72]\t@ 0x48\n+\tlsls\tr1, r1, #3\n+\tlsls\tr4, r4, #3\n+\tlsls\tr2, r2, #3\n+\tlsls\tr5, r3, #3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tlsls\tr0, r0, #3\n-\tldr\tr3, [sp, #4]\n-\tlsls\tr7, r7, #3\n-\tadd\tip, r5\n-\tadd.w\tsl, r4, r0\n-\tadds\tr3, r4, r3\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #4]\n-\tadd\tr0, r5\n-\tadds\tr5, r4, r7\n-\tstr\tr5, [sp, #28]\n-\tadd\tr3, r2\n+\tadd.w\tr9, r7, r1\n+\tadd\tr1, r3\n+\tstr\tr1, [sp, #4]\n+\tadds\tr1, r7, r6\n+\tstr\tr1, [sp, #16]\n+\tadds\tr1, r3, r6\n+\tmov\tr6, r7\n+\tadd.w\tlr, r7, r4\n+\tadd.w\tip, r7, r5\n+\tadd\tr4, r3\n+\tadd\tr5, r3\n+\tadd\tr6, r0\n+\tstr\tr1, [sp, #20]\n+\tadd\tr0, r3\n+\tmov\tr1, r7\n \tadd\tr7, r2\n-\tmov\tr5, r3\n+\tadd\tr2, r3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tmov.w\tsl, sl, lsl #3\n+\tadd\tr1, sl\n+\tmov.w\tfp, fp, lsl #3\n+\tadd\tsl, r3\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr1, [sp, #24]\n+\tadd.w\tr1, r3, fp\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr1, [sp, #12]\n+\tadd\tfp, r3\n+\tldr\tr1, [sp, #8]\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tadds\tr1, r3, r1\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr1, [sp, #28]\n+\tldr\tr1, [sp, #8]\n+\tadd\tr1, r3\n+\tmov\tr3, r1\n+\tmovs\tr1, #1\n+\tstrd\tr2, r3, [sp, #32]\n+\tstr\tr1, [sp, #8]\n+\tvldr\td6, [lr, #-8]\n+\tvldr\td7, [r9, #-8]\n+\tldr\tr3, [sp, #4]\n+\tvldr\td8, [ip, #-8]\n+\tvadd.f64\td3, d7, d6\n+\tvldr\td4, [r4, #-8]\n+\tvsub.f64\td7, d7, d6\n+\tldr\tr2, [sp, #16]\n+\tvldr\td5, [r3, #-8]\n+\tvmov.f64\td6, d8\n+\tvldr\td0, [r5, #-8]\n+\tvmls.f64\td6, d3, d13\n+\tvadd.f64\td3, d3, d8\n+\tvadd.f64\td1, d5, d4\n+\tvsub.f64\td5, d5, d4\n+\tvldr\td2, [r2, #-8]\n+\tvmul.f64\td7, d7, d14\n \tldr\tr3, [sp, #8]\n-\tadd.w\tlr, r4, r1\n-\tadd\tr6, r2\n-\tadd\tr4, r3\n-\tadd\tr1, r2\n-\tadds\tr3, r2, r3\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #24]\n-\tstr.w\tip, [sp, #24]\n-\tmov\tip, r7\n-\tstr\tr3, [sp, #20]\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #8]\n-\tldr\tr7, [sp, #24]\n-\tvldr\td20, [r0, #-8]\n-\tvldr\td30, [r2, #-8]\n-\tvldr\td19, [sl, #-8]\n-\tvldr\td26, [fp, #-8]\n-\tvldr\td17, [r7, #-8]\n-\tvadd.f64\td29, d30, d20\n-\tvldr\td27, [r4, #-8]\n-\tvsub.f64\td30, d30, d20\n-\tvadd.f64\td20, d26, d19\n-\tvsub.f64\td26, d26, d19\n-\tvmov.f64\td19, d17\n-\tldr\tr7, [sp, #8]\n-\tvfms.f64\td19, d29, d18\n-\tvmov.f64\td31, d27\n-\tvadd.f64\td7, d29, d17\n-\tvfnms.f64\td17, d29, d18\n-\tvfms.f64\td31, d20, d18\n-\tvadd.f64\td27, d20, d27\n-\tadds\tr7, #1\n-\tstr\tr7, [sp, #8]\n-\tldr\tr7, [sp, #24]\n-\tvfma.f64\td17, d16, d26\n-\tvldr\td6, [ip, #-8]\n-\tldr\tr3, [sp, #28]\n-\tvmov.f64\td20, d19\n-\tvfma.f64\td19, d26, d23\n-\tvfma.f64\td20, d16, d26\n-\tvstr\td7, [r7, #-8]\n-\tvmov.f64\td29, d31\n-\tadd\tr7, r8\n-\tvfma.f64\td29, d30, d23\n-\tstr\tr7, [sp, #24]\n-\tldr\tr7, [sp, #0]\n-\tvmov.f64\td5, d6\n-\tvldr\td3, [r3, #-8]\n-\tvfma.f64\td31, d16, d30\n-\tvstr\td27, [r4, #-8]\n-\tvmul.f64\td17, d22, d17\n-\tadd\tr4, r8\n-\tvmul.f64\td19, d25, d19\n-\tvmul.f64\td26, d24, d20\n-\tvnmul.f64\td20, d20, d21\n-\tvfma.f64\td26, d21, d29\n-\tvfma.f64\td20, d24, d29\n-\tvmov.f64\td29, d3\n-\tvfma.f64\td17, d25, d31\n-\tvfma.f64\td19, d22, d31\n-\tvstr\td26, [ip, #-8]\n+\tvstr\td3, [ip, #-8]\n \tadd\tip, r8\n-\tvldr\td26, [r1, #-8]\n-\tvldr\td4, [r7, #-8]\n-\tvstr\td20, [r3, #-8]\n-\tadd\tr3, r8\n-\tvldr\td20, [lr, #-8]\n-\tvldr\td27, [r9, #-8]\n-\tvadd.f64\td7, d4, d26\n-\tvsub.f64\td4, d4, d26\n-\tvldr\td31, [r6, #-8]\n-\tldr\tr7, [sp, #12]\n-\tvadd.f64\td26, d27, d20\n-\tvsub.f64\td27, d27, d20\n-\tvmov.f64\td20, d6\n-\tvfnms.f64\td5, d7, d18\n-\tvfms.f64\td20, d7, d18\n-\tvadd.f64\td6, d6, d7\n-\tvldr\td30, [r7, #-8]\n-\tvfms.f64\td29, d26, d18\n-\tvadd.f64\td3, d3, d26\n-\tvfma.f64\td5, d16, d27\n-\tldr\tr7, [sp, #0]\n-\tvstr\td6, [r2, #-8]\n+\tvmul.f64\td4, d1, d13\n+\tvmul.f64\td5, d5, d14\n+\tvadd.f64\td8, d1, d0\n+\tldr\tr1, [sp, #32]\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #24]\n+\tvsub.f64\td3, d6, d5\n+\tvadd.f64\td6, d6, d5\n+\tvsub.f64\td5, d0, d4\n+\tvsub.f64\td4, d4, d0\n+\tvmul.f64\td9, d11, d6\n+\tvmul.f64\td6, d10, d6\n+\tvadd.f64\td4, d4, d7\n+\tvmla.f64\td9, d4, d10\n+\tvadd.f64\td4, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvmul.f64\td1, d12, d4\n+\tvmul.f64\td7, d15, d4\n+\tvmla.f64\td6, d5, d11\n+\tvmla.f64\td7, d12, d3\n+\tvnmls.f64\td1, d15, d3\n+\tvmov.f64\td3, d2\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvstr\td1, [r2, #-8]\n \tadd\tr2, r8\n-\tstr\tr3, [sp, #28]\n-\tvstr\td3, [fp, #-8]\n-\tadd\tfp, r8\n-\tvmov.f64\td26, d20\n-\tvfma.f64\td20, d23, d27\n-\tvfma.f64\td26, d16, d27\n-\tvmov.f64\td7, d29\n-\tvfma.f64\td29, d16, d4\n-\tvfma.f64\td7, d4, d23\n-\tvmul.f64\td27, d22, d5\n-\tvmul.f64\td20, d25, d20\n-\tvmul.f64\td6, d24, d26\n-\tvnmul.f64\td26, d26, d21\n-\tvfma.f64\td20, d22, d29\n-\tvfma.f64\td27, d25, d29\n-\tvfma.f64\td6, d21, d7\n-\tvfma.f64\td26, d24, d7\n-\tvstr\td6, [r7, #-8]\n-\tvstr\td20, [r6, #-8]\n-\tadd\tr6, r8\n-\tvldr\td20, [r5, #-8]\n-\tldr\tr7, [sp, #20]\n-\tldr\tr3, [sp, #16]\n-\tvstr\td26, [r9, #-8]\n+\tvldr\td4, [r6, #-8]\n+\tvldr\td6, [r7, #-8]\n+\tstr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #20]\n+\tvadd.f64\td5, d6, d4\n+\tvsub.f64\td6, d6, d4\n+\tvldr\td4, [r3, #-8]\n+\tvmls.f64\td3, d5, d13\n+\tvadd.f64\td5, d2, d5\n+\tvldr\td2, [r2, #-8]\n+\tvmul.f64\td6, d6, d14\n+\tvstr\td8, [r5, #-8]\n+\tadd\tr5, r8\n+\tvstr\td7, [r2, #-8]\n+\tadd\tr2, r8\n+\tvldr\td7, [r0, #-8]\n+\tvstr\td5, [r9, #-8]\n \tadd\tr9, r8\n-\tvldr\td29, [r7, #-8]\n-\tldr\tr7, [sp, #12]\n-\tvstr\td27, [r7, #-8]\n-\tvadd.f64\td27, d31, d20\n-\tvldr\td26, [r3, #-8]\n-\tvsub.f64\td31, d31, d20\n-\tldr\tr3, [sp, #4]\n-\tadd\tr7, r8\n-\tstr\tr7, [sp, #12]\n-\tvadd.f64\td20, d30, d26\n-\tvsub.f64\td26, d30, d26\n-\tldr\tr7, [sp, #0]\n-\tvldr\td7, [r3, #-8]\n-\tvstr\td17, [r3, #-8]\n-\tvmov.f64\td17, d29\n-\tldr\tr3, [sp, #20]\n-\tvfms.f64\td17, d27, d18\n-\tvmov.f64\td6, d7\n-\tvadd.f64\td7, d20, d7\n-\tvfms.f64\td6, d20, d18\n+\tvldr\td5, [r1, #-8]\n+\tstr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #4]\n+\tvadd.f64\td1, d5, d7\n+\tvsub.f64\td7, d5, d7\n+\tvldr\td0, [sl, #-8]\n+\tvmul.f64\td5, d1, d13\n+\tvadd.f64\td1, d2, d1\n+\tvmul.f64\td7, d7, d14\n+\tvstr\td1, [r2, #-8]\n+\tvsub.f64\td1, d2, d5\n+\tvsub.f64\td5, d5, d2\n+\tadd\tr2, r8\n+\tstr\tr2, [sp, #4]\n+\tvadd.f64\td2, d6, d1\n+\tvsub.f64\td1, d1, d6\n+\tvadd.f64\td5, d5, d6\n+\tvadd.f64\td6, d3, d7\n+\tvsub.f64\td7, d3, d7\n+\tvmul.f64\td3, d12, d2\n+\tvmul.f64\td2, d15, d2\n+\tvmla.f64\td2, d12, d7\n+\tvnmls.f64\td3, d15, d7\n+\tvmul.f64\td7, d10, d6\n+\tvmul.f64\td6, d11, d6\n+\tvmla.f64\td7, d1, d11\n+\tvmla.f64\td6, d5, d10\n+\tvstr\td2, [r1, #-8]\n+\tadd\tr1, r8\n+\tldr\tr2, [sp, #12]\n+\tvstr\td3, [r7, #-8]\n \tadd\tr7, r8\n-\tstr\tr7, [sp, #0]\n-\tvstr\td19, [r3, #-8]\n-\tvmov.f64\td19, d29\n-\tvfnms.f64\td19, d27, d18\n-\tvadd.f64\td27, d27, d29\n-\tldr\tr7, [sp, #4]\n+\tstr\tr1, [sp, #32]\n+\tvstr\td6, [r3, #-8]\n+\tadd\tr3, r8\n+\tvldr\td6, [r2, #-8]\n+\tldr\tr1, [sp, #36]\t@ 0x24\n+\tldr\tr2, [sp, #28]\n+\tvldr\td2, [sp, #40]\t@ 0x28\n \tvstr\td7, [sl, #-8]\n \tadd\tsl, r8\n-\tvmov.f64\td20, d17\n-\tvfma.f64\td17, d26, d23\n-\tvfma.f64\td20, d16, d26\n-\tvfma.f64\td19, d16, d26\n-\tvmov.f64\td30, d6\n-\tvfma.f64\td6, d16, d31\n-\tvfma.f64\td30, d31, d23\n-\tvstr\td27, [r0, #-8]\n-\tadd\tr7, r8\n-\tstr\tr7, [sp, #4]\n-\tadd.w\tr7, r3, r8\n-\tldr\tr3, [sp, #16]\n-\tstr\tr7, [sp, #20]\n-\tadd\tr0, r8\n-\tldr\tr7, [sp, #8]\n-\tvmul.f64\td17, d25, d17\n-\tvnmul.f64\td27, d20, d21\n-\tvmul.f64\td19, d22, d19\n-\tvfma.f64\td19, d25, d6\n-\tvmul.f64\td20, d24, d20\n-\tvfma.f64\td27, d24, d30\n-\tvfma.f64\td20, d21, d30\n-\tvfma.f64\td17, d22, d6\n-\tvstr\td27, [lr, #-8]\n+\tvldr\td7, [fp, #-8]\n+\tvldr\td5, [r2, #-8]\n+\tvldr\td3, [r1, #-8]\n+\tvstr\td2, [r1, #-8]\n+\tvadd.f64\td2, d4, d6\n+\tvsub.f64\td6, d4, d6\n+\tvadd.f64\td4, d0, d7\n+\tvmov.f64\td1, d5\n+\tvsub.f64\td7, d0, d7\n+\tvstr\td9, [r2, #-8]\n+\tadd\tr2, r8\n+\tvmls.f64\td1, d2, d13\n+\tvadd.f64\td2, d2, d5\n+\tvadd.f64\td5, d4, d3\n+\tvmul.f64\td4, d4, d13\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td6, d6, d14\n+\tstr\tr2, [sp, #28]\n+\tvstr\td2, [lr, #-8]\n \tadd\tlr, r8\n-\tvstr\td19, [r3, #-8]\n+\tvsub.f64\td2, d4, d3\n+\tvsub.f64\td4, d3, d4\n+\tvstr\td5, [r4, #-8]\n+\tadd\tr4, r8\n+\tldr\tr2, [sp, #12]\n+\tvadd.f64\td5, d1, d7\n+\tvsub.f64\td7, d1, d7\n+\tvadd.f64\td3, d6, d4\n+\tvadd.f64\td2, d2, d6\n+\tvsub.f64\td4, d4, d6\n+\tstr\tr3, [sp, #24]\n+\tmov\tr3, r1\n+\tvmul.f64\td6, d11, d5\n+\tvmul.f64\td5, d10, d5\n+\tvmla.f64\td6, d2, d10\n+\tvmul.f64\td2, d12, d3\n+\tvmul.f64\td3, d15, d3\n+\tvmla.f64\td5, d4, d11\n+\tvmla.f64\td3, d12, d7\n \tadd\tr3, r8\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #32]\n-\tvstr\td20, [r1, #-8]\n-\tadd\tr1, r8\n-\tvstr\td17, [r5, #-8]\n-\tcmp\tr7, r3\n-\tadd\tr5, r8\n-\tbne.w\t420c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x116c>\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n \tstr\tr3, [sp, #36]\t@ 0x24\n+\tvnmls.f64\td2, d15, d7\n+\tldr\tr3, [sp, #8]\n+\tvstr\td3, [r0, #-8]\n+\tadd\tr0, r8\n+\tvstr\td5, [fp, #-8]\n+\tadd\tfp, r8\n+\tvstr\td2, [r6, #-8]\n+\tadd\tr6, r8\n+\tvstr\td6, [r2, #-8]\n+\tadd\tr2, r8\n+\tstr\tr2, [sp, #12]\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tcmp\tr3, r2\n+\tbne.w\t468a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1352>\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tadd\tr3, r2\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr2, r3\n-\tble.n\t4450 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13b0>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tble.n\t48c8 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1590>\n+\tldr\tr2, [sp, #56]\t@ 0x38\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #80]\t@ 0x50\n \tcmp\tr3, r2\n-\tbne.w\t4118 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1078>\n-\tldrd\tr9, r2, [sp, #84]\t@ 0x54\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tsubs\tr2, #1\n-\tadd\tr1, r9\n-\tadds\tr3, r2, #1\n-\tbne.w\t410c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x106c>\n-\tldrd\tfp, lr, [sp, #188]\t@ 0xbc\n-\tldrd\tr4, r3, [sp, #196]\t@ 0xc4\n-\tldrd\tr0, r7, [sp, #204]\t@ 0xcc\n-\tldr\tr5, [sp, #212]\t@ 0xd4\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tsubs\tr4, #1\n-\tadd\tr3, lr\n-\tsub.w\tr0, r0, lr\n-\tadd\tr2, lr\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tadds\tr2, r4, #1\n-\tbne.w\t40dc <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x103c>\n-\tldr.w\tsl, [sp, #132]\t@ 0x84\n-\tldrd\tip, r4, [sp, #164]\t@ 0xa4\n-\tldrd\tr0, r6, [sp, #180]\t@ 0xb4\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n+\tbne.w\t4598 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1260>\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tsubs\tr3, #1\n+\tadd\tr2, r1\n+\tadds\tr1, r3, #1\n+\tbne.w\t458e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1256>\n+\tldrd\tfp, r9, [sp, #216]\t@ 0xd8\n+\tldrd\tr4, r5, [sp, #224]\t@ 0xe0\n+\tldr.w\tsl, [sp, #232]\t@ 0xe8\n \tldr\tr3, [sp, #108]\t@ 0x6c\n-\tcmp.w\tip, #4294967295\t@ 0xffffffff\n-\tldr\tr2, [sp, #128]\t@ 0x80\n-\tadd\tr4, r3\n-\tsub.w\tr6, r6, r3\n-\tadd\tr7, r3\n-\tadd\tr0, r2\n-\tmov\tr3, r5\n-\tbeq.n\t4516 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1476>\n-\tldr\tr2, [sp, #96]\t@ 0x60\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tadd\tr4, fp\n+\tcmp.w\tr9, #4294967295\t@ 0xffffffff\n+\tadd\tr3, fp\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tsub.w\tr3, r3, fp\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tbne.w\t455c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1224>\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tldr\tr7, [sp, #204]\t@ 0xcc\n+\tldr\tr6, [sp, #212]\t@ 0xd4\n+\tldr\tr2, [sp, #132]\t@ 0x84\n+\tldr\tr0, [sp, #164]\t@ 0xa4\n+\tsubs\tr1, r2, #1\n+\tldr\tr2, [sp, #124]\t@ 0x7c\n+\tadd\tr6, r0\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tadd\tr3, r2\n \tadd\tr5, r2\n-\tb.n\t4098 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xff8>\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tcmp\tfp, r3\n-\tldr\tr1, [sp, #140]\t@ 0x8c\n-\tudiv\tr2, r2, r1\n-\tble.w\t40ee <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x104e>\n-\tb.n\t447c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13dc>\n-\tsubs\tr5, r0, r2\n-\tnegs\tr4, r0\n-\tcmp\tr0, r2\n-\tudiv\tr7, r5, r4\n-\tbge.w\t3314 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x274>\n-\tb.w\t3642 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5a2>\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tnegs\tr2, r6\n-\tudiv\tr2, r1, r2\n-\tldr\tr1, [sp, #100]\t@ 0x64\n-\tcmp\tr1, #0\n-\tble.w\t31da <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13a>\n-\tb.w\t32f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x256>\n-\tadd\tsp, #228\t@ 0xe4\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tasrs\tr2, r3, #1\n-\tadds\tr2, #1\n-\tbic.w\tr2, r2, #1\n-\tstr\tr2, [sp, #276]\t@ 0x114\n+\tsubs\tr0, r0, r2\n+\tstr\tr1, [sp, #132]\t@ 0x84\n+\tmov\tr2, sl\n+\tadds\tr1, #1\n+\tstr\tr0, [sp, #104]\t@ 0x68\n+\tbeq.n\t4976 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x163e>\n+\tadd\tsl, r7\n+\tb.n\t450e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x11d6>\n+\tldr\tr1, [sp, #172]\t@ 0xac\n+\tldr\tr0, [sp, #108]\t@ 0x6c\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tble.w\t4576 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x123e>\n+\tb.n\t48f2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15ba>\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\trsb\tr1, fp, #0\n+\tldr\tr2, [sp, #120]\t@ 0x78\n \tsubs\tr4, r3, r2\n-\tb.w\t3182 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xe2>\n-\tsubs\tr0, r4, r3\n-\tnegs\tr1, r4\n-\tcmp\tr4, r3\n-\tudiv\tr5, r0, r1\n-\tbge.w\t3a18 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x978>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr2, [sp, #272]\t@ 0x110\n+\tadds\tr0, r4, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tldr\tr3, [sp, #4]\n+\tmov\tr9, r0\n+\tcmp\tr2, r3\n+\tble.w\t454c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1214>\n+\tb.n\t4914 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15dc>\n+\tnegs\tr1, r7\n+\tsubs\tr0, r7, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr7, r4\n+\tstr\tr0, [sp, #132]\t@ 0x84\n+\tbge.w\t4054 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xd1c>\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tldr\tr2, [sp, #352]\t@ 0x160\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n \tcmp\tr3, r2\n-\tble.w\t3666 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5c6>\n-\tldrd\tr0, r4, [sp, #144]\t@ 0x90\n-\tb.w\t3610 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x570>\n-\tldr\tr4, [sp, #276]\t@ 0x114\n-\tmov\tr9, r7\n-\tldr.w\tip, [sp, #120]\t@ 0x78\n-\tmov\tr2, fp\n-\tldr.w\tr8, [sp, #136]\t@ 0x88\n-\tmovs\tr3, #0\n-\tmov\tr7, r5\n-\tadds\tr4, #1\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tstr\tr4, [sp, #32]\n-\tstr\tr6, [sp, #72]\t@ 0x48\n-\tcmp\tr1, #0\n-\tblt.w\t4894 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x17f4>\n-\tudiv\tr4, r2, r1\n-\tcmp\tfp, r3\n-\tblt.w\t487a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x17da>\n-\tldr\tr5, [sp, #104]\t@ 0x68\n+\tble.w\t392e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5f6>\n+\tldrd\tr6, r7, [sp, #180]\t@ 0xb4\n+\tldr\tr4, [sp, #188]\t@ 0xbc\n+\tb.w\t38c4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x58c>\n+\tldrd\tr0, r1, [sp, #76]\t@ 0x4c\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tble.w\t3d06 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x9ce>\n+\tb.w\t4014 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcdc>\n+\trsb\tr1, fp, #0\n+\tnegs\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n \tcmp\tr5, #0\n-\tble.w\t487a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x17da>\n-\tldr\tr6, [sp, #60]\t@ 0x3c\n-\tadds\tr5, #1\n-\tstr\tr0, [sp, #84]\t@ 0x54\n-\tadd\tr6, r3\n-\tstr\tr5, [sp, #68]\t@ 0x44\n-\tmovs\tr0, #1\n-\tstr\tr6, [sp, #36]\t@ 0x24\n-\tstr\tr0, [sp, #64]\t@ 0x40\n-\tstrd\tfp, r9, [sp, #88]\t@ 0x58\n-\tstr.w\tsl, [sp, #96]\t@ 0x60\n-\tstrd\tlr, r1, [sp, #128]\t@ 0x80\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tstrd\tr4, r7, [sp, #164]\t@ 0xa4\n-\tstrd\tr6, ip, [sp, #180]\t@ 0xb4\n-\tstr\tr2, [sp, #188]\t@ 0xbc\n-\tldrd\tr2, r3, [sp, #36]\t@ 0x24\n-\tadds\tr2, r3, r2\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr2, r3\n-\tbge.n\t4598 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x14f8>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr0, r3\n-\tbge.n\t45a6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1506>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tadds\tr7, r3, r1\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tcmp\tr7, r3\n-\tbge.n\t45b6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1516>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr7, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr3, r7\n-\tcmp\tr3, r1\n-\tbge.n\t45c4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1524>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tldr\tr4, [sp, #60]\t@ 0x3c\n-\tadd.w\tip, r1, r3\n-\tcmp\tip, r4\n-\tbge.n\t45d4 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1534>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tip, r1\n-\tldr\tr4, [sp, #56]\t@ 0x38\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tadd\tr4, r7\n-\tcmp\tr4, r5\n-\tbge.n\t45e2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1542>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr4, r1\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tadds\tr6, r5, r4\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n+\tmov\tr4, r0\n+\tble.w\t3974 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x63c>\n+\tb.w\t402a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0xcf2>\n+\tadd\tsp, #244\t@ 0xf4\n+\tvpop\t{d8-d15}\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tnegs\tr1, r6\n+\tsubs\tr0, r6, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n \tcmp\tr6, r5\n-\tbge.n\t45f0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1550>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr6, r1\n-\tldr\tr5, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr5, r6\n-\tcmp\tr5, r1\n-\tbge.n\t45fe <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x155e>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tadd\tr5, r1\n-\tldr\tr1, [sp, #276]\t@ 0x114\n+\tstr\tr0, [sp, #12]\n+\tblt.w\t390c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5d4>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n+\tcmp\tr3, #1\n+\tbeq.w\t35e6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x2ae>\n+\tmov.w\tr3, r9, lsl #4\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tmov.w\tr5, r9, lsl #3\n+\tstr\tr5, [sp, #76]\t@ 0x4c\n+\tadds\tr0, r3, r5\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tadds\tr2, r0, r5\n+\tstr\tr6, [sp, #16]\n+\tsubs\tr1, r6, r3\n+\tsubs\tr3, r3, r6\n+\tstr\tr3, [sp, #24]\n+\tmov\tr5, r2\n+\tldr\tr3, [sp, #356]\t@ 0x164\n+\tstr\tr2, [sp, #28]\n+\tadd.w\tr9, r3, #1\n+\tstr\tr1, [sp, #20]\n+\tnegs\tr3, r7\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\td8, [r0, #8]\n+\tcmp\tr7, #0\n+\tvldr\td9, [r5, #8]\n+\tvldr\td10, [r0]\n+\tvmul.f64\td8, d13, d8\n+\tvldr\td11, [r5]\n+\tvmul.f64\td9, d13, d9\n+\tblt.w\t4ba0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1868>\n+\tmov\tr1, r7\n+\tldr\tr0, [sp, #24]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #16]\n+\tmov\tr1, r0\n+\tcmp\tr3, r2\n+\tblt.w\t4b6e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1836>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tcmp\tr3, #0\n+\tble.w\t4b6e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1836>\n+\tldr\tr3, [sp, #16]\n+\tmov\tr0, r1\n+\tmov\tr1, r7\n+\tadd\tr3, r8\n+\tmov\tip, r3\n+\tmov.w\tlr, #1\n+\tstrd\tr6, r1, [sp, #80]\t@ 0x50\n+\tstr\tr0, [sp, #96]\t@ 0x60\n+\tstrd\tr3, r5, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #8]\n+\tadd\tr3, ip\n+\tcmp\tr3, r8\n+\titt\tlt\n+\tldrlt\tr2, [sp, #56]\t@ 0x38\n+\taddlt\tr3, r3, r2\n+\tldr\tr2, [sp, #8]\n+\tadd\tr2, r3\n+\tcmp\tr2, r8\n+\titt\tlt\n+\tldrlt\tr1, [sp, #56]\t@ 0x38\n+\taddlt\tr2, r2, r1\n+\tldr\tr1, [sp, #356]\t@ 0x164\n \tcmp\tr1, #0\n-\tble.w\t4834 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1794>\n-\tlsls\tr5, r5, #3\n-\tstr\tr5, [sp, #4]\n-\tldr\tr5, [sp, #36]\t@ 0x24\n-\tmov.w\tr1, ip, lsl #3\n-\tlsls\tr4, r4, #3\n-\tstr\tr4, [sp, #8]\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tlsls\tr2, r2, #3\n-\tmov.w\tip, r5, lsl #3\n-\tldr\tr5, [sp, #48]\t@ 0x30\n-\tlsls\tr0, r0, #3\n-\tadd.w\tfp, r4, r2\n-\tadd\tr2, r5\n-\tstr\tr2, [sp, #20]\n-\tmov\tr2, r5\n-\tadd.w\tsl, r4, r0\n-\tadd\tr0, r5\n-\tadd.w\tr5, r4, ip\n-\tadd\tip, r2\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tlsls\tr7, r7, #3\n+\tble.n\t4b42 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x180a>\n \tlsls\tr3, r3, #3\n-\tlsls\tr6, r6, #3\n-\tstr\tr5, [sp, #12]\n-\tadd.w\tr9, r4, r3\n-\tadds\tr5, r4, r7\n-\tadd\tr3, r2\n-\tadd.w\tlr, r4, r1\n-\tstr\tr5, [sp, #28]\n-\tadd\tr1, r2\n-\tadds\tr5, r2, r7\n-\tmov\tr7, r4\n-\tstr\tr5, [sp, #0]\n-\tadds\tr5, r4, r6\n-\tadd\tr6, r2\n-\tstr\tr5, [sp, #24]\n-\tmov\tr5, r2\n-\tmov\tr2, r4\n-\tldr\tr4, [sp, #4]\n-\tadd\tr7, r4\n-\tadd\tr4, r5\n-\tmov\tr5, r4\n-\tldr\tr4, [sp, #8]\n-\tadd\tr2, r4\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #48]\t@ 0x30\n+\tlsls\tr2, r2, #3\n+\tmov.w\tr1, ip, lsl #3\n+\tadd.w\tr6, fp, r3\n+\tadd.w\tr5, fp, r2\n+\tadd.w\tr0, fp, r1\n+\tadd\tr3, sl\n+\tadd\tr2, sl\n+\tadd\tr1, sl\n+\tmovs\tr7, #1\n+\tvldr\td5, [r2, #-8]\n+\tadds\tr7, #1\n+\tvldr\td7, [r3, #-8]\n+\tcmp\tr7, r9\n+\tvldr\td6, [r6, #-8]\n+\tvldr\td4, [r5, #-8]\n+\tvadd.f64\td3, d7, d5\n+\tvldr\td0, [r0, #-8]\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td1, [r1, #-8]\n+\tvadd.f64\td2, d6, d4\n+\tvsub.f64\td4, d6, d4\n+\tvmov.f64\td6, d0\n+\tvmul.f64\td5, d3, d12\n+\tvadd.f64\td3, d3, d1\n+\tvmul.f64\td7, d7, d14\n+\tvmls.f64\td6, d2, d12\n+\tvmul.f64\td4, d4, d14\n+\tvadd.f64\td0, d2, d0\n+\tvsub.f64\td2, d1, d5\n+\tvsub.f64\td1, d5, d1\n+\tvstr\td3, [r1, #-8]\n+\tadd\tr1, r4\n+\tvstr\td0, [r0, #-8]\n+\tadd\tr0, r4\n+\tvadd.f64\td5, d4, d2\n+\tvadd.f64\td1, d1, d4\n+\tvsub.f64\td4, d2, d4\n+\tvadd.f64\td3, d6, d7\n+\tvsub.f64\td6, d6, d7\n+\tvmul.f64\td2, d8, d5\n+\tvmul.f64\td5, d10, d5\n+\tvmul.f64\td7, d11, d3\n+\tvmul.f64\td3, d9, d3\n+\tvmla.f64\td5, d8, d6\n+\tvmla.f64\td7, d1, d9\n+\tvmla.f64\td3, d4, d11\n+\tvnmls.f64\td2, d10, d6\n+\tvstr\td5, [r3, #-8]\n+\tadd\tr3, r4\n+\tvstr\td2, [r6, #-8]\n+\tadd\tr6, r4\n+\tvstr\td3, [r2, #-8]\n \tadd\tr2, r4\n-\tldr\tr4, [sp, #12]\n-\tstr\tr2, [sp, #8]\n-\tmovs\tr2, #1\n-\tstr\tr3, [sp, #12]\n+\tvstr\td7, [r5, #-8]\n+\tadd\tr5, r4\n+\tbne.n\t4a98 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1760>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadd\tip, r3\n+\tcmp\tip, r8\n+\tbge.n\t4b4e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1816>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tip, r3\n+\tldr\tr3, [sp, #4]\n+\tadd.w\tlr, lr, #1\n+\tcmp\tlr, r3\n+\tbne.n\t4a5e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1726>\n+\tldrd\tr6, r1, [sp, #80]\t@ 0x50\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldrd\tr3, r5, [sp, #104]\t@ 0x68\n+\tsubs\tr0, #1\n+\tadds\tr2, r0, #1\n+\tadd\tr3, r1\n+\tbne.w\t4a4e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1716>\n+\tmov\tr7, r1\n+\tldr\tr2, [sp, #16]\n+\tldr\tr3, [sp, #12]\n+\tadd\tr2, r6\n \tstr\tr2, [sp, #16]\n-\tldr\tr2, [sp, #20]\n-\tvldr\td20, [sl, #-8]\n-\tvldr\td18, [fp, #-8]\n-\tvldr\td24, [r0, #-8]\n-\tvldr\td19, [r2, #-8]\n-\tvldr\td22, [r4, #-8]\n-\tvadd.f64\td21, d18, d20\n-\tvldr\td27, [ip, #-8]\n-\tvsub.f64\td18, d18, d20\n-\tvadd.f64\td20, d19, d24\n-\tvsub.f64\td19, d19, d24\n-\tvmov.f64\td24, d22\n-\tldr\tr2, [sp, #28]\n-\tvfms.f64\td24, d21, d17\n-\tvadd.f64\td22, d21, d22\n-\tvmov.f64\td21, d27\n-\tldr\tr3, [sp, #0]\n-\tvfms.f64\td21, d20, d17\n-\tvadd.f64\td20, d20, d27\n-\tvldr\td26, [r2, #-8]\n-\tvstr\td22, [r4, #-8]\n-\tadd\tr4, r8\n-\tvldr\td25, [r3, #-8]\n-\tldr\tr3, [sp, #16]\n-\tvstr\td20, [ip, #-8]\n-\tadd\tip, r8\n-\tvmov.f64\td27, d24\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tsubs\tr3, #1\n+\tstr\tr3, [sp, #12]\n \tadds\tr3, #1\n-\tvfma.f64\td27, d19, d23\n-\tstr\tr3, [sp, #16]\n-\tvmov.f64\td22, d21\n-\tldr\tr3, [sp, #0]\n-\tvfma.f64\td22, d16, d18\n-\tvfma.f64\td21, d18, d23\n-\tvfma.f64\td24, d16, d19\n-\tvstr\td27, [r2, #-8]\n-\tadd\tr2, r8\n-\tvldr\td30, [lr, #-8]\n-\tvstr\td22, [r3, #-8]\n-\tldr\tr3, [sp, #12]\n-\tvldr\td27, [r9, #-8]\n-\tvldr\td22, [r1, #-8]\n-\tstr\tr2, [sp, #28]\n-\tvldr\td18, [r3, #-8]\n-\tvadd.f64\td20, d27, d30\n-\tvsub.f64\td27, d27, d30\n-\tldr\tr3, [sp, #24]\n-\tvldr\td19, [r6, #-8]\n-\tvadd.f64\td30, d18, d22\n-\tvsub.f64\td18, d18, d22\n-\tvmov.f64\td22, d26\n-\tvadd.f64\td26, d26, d20\n-\tvfms.f64\td22, d20, d17\n-\tvmov.f64\td20, d25\n-\tvldr\td29, [r3, #-8]\n-\tvfms.f64\td20, d30, d17\n-\tldr\tr3, [sp, #0]\n-\tvadd.f64\td25, d25, d30\n-\tvstr\td26, [fp, #-8]\n-\tadd.w\tr2, r3, r8\n-\tstr\tr2, [sp, #0]\n+\tadd\tr5, r2\n \tldr\tr2, [sp, #20]\n-\tadd\tfp, r8\n-\tvmov.f64\td30, d22\n-\tvfma.f64\td22, d16, d18\n-\tvfma.f64\td30, d23, d18\n-\tvstr\td25, [r2, #-8]\n-\tvmov.f64\td18, d20\n-\tadd\tr2, r8\n-\tvfma.f64\td18, d16, d27\n+\tadd\tr2, r6\n \tstr\tr2, [sp, #20]\n-\tldr\tr2, [sp, #12]\n-\tvfma.f64\td20, d27, d23\n-\tldr\tr3, [sp, #24]\n-\tvstr\td30, [r9, #-8]\n-\tadd\tr9, r8\n-\tvstr\td22, [r3, #-8]\n-\tadd\tr3, r8\n-\tvstr\td18, [r2, #-8]\n-\tldr\tr2, [sp, #4]\n-\tvstr\td20, [r6, #-8]\n-\tadd\tr6, r8\n-\tvldr\td18, [r7, #-8]\n-\tvldr\td27, [r5, #-8]\n-\tvldr\td26, [r2, #-8]\n-\tldr\tr2, [sp, #8]\n-\tvadd.f64\td20, d29, d18\n-\tvadd.f64\td22, d19, d27\n-\tvsub.f64\td19, d19, d27\n-\tvsub.f64\td18, d29, d18\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #12]\n-\tvldr\td25, [r2, #-8]\n-\tldr\tr2, [sp, #4]\n-\tadd\tr3, r8\n-\tstr\tr3, [sp, #12]\n-\tvstr\td24, [r2, #-8]\n-\tldr\tr2, [sp, #8]\n-\tvstr\td21, [r2, #-8]\n-\tvmov.f64\td21, d26\n-\tvfms.f64\td21, d20, d17\n-\tvadd.f64\td26, d20, d26\n-\tvmov.f64\td20, d25\n-\tldr\tr2, [sp, #4]\n-\tvfms.f64\td20, d22, d17\n-\tvadd.f64\td22, d22, d25\n-\tadd.w\tr3, r2, r8\n-\tldr\tr2, [sp, #8]\n-\tstr\tr3, [sp, #4]\n-\tadd\tr2, r8\n-\tldr\tr3, [sp, #16]\n-\tstr\tr2, [sp, #8]\n-\tldr\tr2, [sp, #32]\n-\tvmov.f64\td25, d21\n-\tvfma.f64\td21, d16, d19\n-\tvfma.f64\td25, d23, d19\n-\tvstr\td26, [sl, #-8]\n-\tvmov.f64\td19, d20\n-\tvfma.f64\td20, d18, d23\n-\tvfma.f64\td19, d16, d18\n-\tvstr\td22, [r0, #-8]\n-\tadd\tsl, r8\n-\tadd\tr0, r8\n-\tcmp\tr3, r2\n-\tvstr\td25, [lr, #-8]\n-\tadd\tlr, r8\n-\tvstr\td21, [r7, #-8]\n-\tadd\tr7, r8\n-\tvstr\td19, [r1, #-8]\n-\tadd\tr1, r8\n-\tvstr\td20, [r5, #-8]\n-\tadd\tr5, r8\n-\tbne.w\t467c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x15dc>\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr2, [sp, #24]\n+\tsub.w\tr2, r2, r6\n+\tstr\tr2, [sp, #24]\n+\tldr\tr2, [sp, #28]\n+\tmov\tr0, r2\n+\tbeq.w\t390c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x5d4>\n+\tmov\tr3, r2\n \tldr\tr2, [sp, #76]\t@ 0x4c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tr3, r2\n-\tbge.n\t4848 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x17a8>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #28]\n+\tb.n\t4a0c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x16d4>\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr\tr0, [sp, #20]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #16]\n+\tmov\tr1, r0\n \tcmp\tr3, r2\n-\tbne.w\t4588 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x14e8>\n-\tldrd\tr4, r7, [sp, #164]\t@ 0xa4\n-\tldrd\tlr, r1, [sp, #128]\t@ 0x80\n-\tsubs\tr4, #1\n-\tldrd\tr6, ip, [sp, #180]\t@ 0xb4\n-\tadds\tr5, r4, #1\n-\tldrd\tfp, r9, [sp, #88]\t@ 0x58\n-\tadd\tr6, r1\n-\tldr.w\tsl, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr2, [sp, #188]\t@ 0xbc\n-\tbne.w\t456a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x14ca>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tsubs\tr0, #1\n-\tadd\tr3, lr\n-\tadd\tip, lr\n-\tsub.w\tr2, r2, lr\n-\tadds\tr4, r0, #1\n-\tbne.w\t4548 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x14a8>\n-\tmov\tr5, r7\n-\tldr\tr6, [sp, #72]\t@ 0x48\n-\tmov\tr7, r9\n-\tb.w\t39f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x956>\n-\tldr\tr4, [sp, #80]\t@ 0x50\n-\tcmp\tfp, r3\n-\tudiv\tr4, ip, r4\n-\tble.w\t4558 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x14b8>\n-\tb.n\t487a <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x17da>\n-\trsb\tr3, sl, #0\n-\trsb\tr2, lr, #0\n-\tcmp.w\tsl, #0\n-\tudiv\tr0, r3, r2\n-\tble.w\t36a2 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x602>\n-\tb.w\t39f6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x956>\n-\tsub.w\tr3, fp, sl\n-\trsb\tr2, lr, #0\n-\tadds\tr1, r3, r7\n-\tcmp\tsl, r4\n-\tudiv\tr2, r1, r2\n-\tble.w\t40c6 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1026>\n-\tb.n\t449c <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x13fc>\n+\tble.w\t4a3e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1706>\n+\tb.n\t4b6e <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0+0x1836>\n+\tnop\n \n-000048d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>:\n+00004bb8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>:\n __gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n+\tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n-\tsub\tsp, #292\t@ 0x124\n-\tstrd\tr0, r1, [sp, #120]\t@ 0x78\n-\tmov\tr1, r3\n-\tldrd\tr4, r3, [sp, #396]\t@ 0x18c\n-\tstr\tr2, [sp, #184]\t@ 0xb8\n+\tsub.w\tip, sp, ip\n+\tstr.w\tr0, [ip, #3488]\t@ 0xda0\n+\tsub\tsp, #508\t@ 0x1fc\n+\tmov\tr5, r3\n+\tldrd\tr6, r3, [sp, #612]\t@ 0x264\n+\tstrd\tr0, r1, [sp, #332]\t@ 0x14c\n+\tstr\tr2, [sp, #404]\t@ 0x194\n \tcmp\tr3, #31\n-\tbhi.w\t86ea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3e1a>\n+\tbhi.w\t8ad8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3f20>\n \tmov\tr2, r3\n \tmovs\tr3, #1\n-\tlsl.w\tr0, r3, r2\n-\tmul.w\tr3, r1, r4\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tsubs\tr3, r0, r4\n-\tmul.w\tr3, r1, r3\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tsdiv\tr3, r4, r0\n-\tstr\tr3, [sp, #132]\t@ 0x84\n-\tmul.w\tr3, r1, r3\n-\tstr\tr3, [sp, #144]\t@ 0x90\n-\tands.w\tr3, r2, #1\n-\tstr\tr3, [sp, #164]\t@ 0xa4\n-\tbne.w\t82d2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a02>\n+\tmov\tr0, r6\n+\tlsl.w\tr4, r3, r2\n+\tmov\tr1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r4, r6\n+\tstr\tr0, [sp, #344]\t@ 0x158\n+\tmul.w\tr3, r5, r3\n+\tstr\tr3, [sp, #316]\t@ 0x13c\n+\tmul.w\tr3, r5, r6\n+\tstr\tr3, [sp, #296]\t@ 0x128\n+\tmov\tr3, r0\n+\tmul.w\tr3, r5, r3\n+\tstr\tr3, [sp, #360]\t@ 0x168\n+\tldr\tr3, [sp, #616]\t@ 0x268\n+\tands.w\tr3, r3, #1\n+\tstr\tr3, [sp, #376]\t@ 0x178\n+\tbne.w\t86be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b06>\n+\tldr\tr2, [sp, #616]\t@ 0x268\n+\tstr\tr3, [sp, #372]\t@ 0x174\n \tasrs\tr2, r2, #1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tstr\tr2, [sp, #180]\t@ 0xb4\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tldr\tr3, [sp, #404]\t@ 0x194\n+\tstr\tr2, [sp, #388]\t@ 0x184\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n \tsubs\tr2, #1\n-\tvldr\ts15, [sp, #408]\t@ 0x198\n+\tvldr\ts15, [sp, #624]\t@ 0x270\n \taddw\tr3, r3, #1022\t@ 0x3fe\n \tit\tpl\n \tmovpl\tr3, r2\n-\tldr\tr5, [sp, #404]\t@ 0x194\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n \tasrs\tr2, r3, #10\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tvcvt.f64.s32\td0, s15\n+\tldr\tr3, [sp, #388]\t@ 0x184\n+\tvcvt.f64.s32\td7, s15\n \tadds\tr3, #1\n \tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #424]\t@ 0x1a8\n \tmovw\tr3, #64514\t@ 0xfc02\n \tmovt\tr3, #65535\t@ 0xffff\n-\tcmp\tr5, r3\n-\tblt.w\t82ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a1e>\n-\tsubs\tr3, r4, #1\n+\tcmp\tr1, r3\n+\tvstr\td7, [sp, #392]\t@ 0x188\n+\tblt.w\t86fc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b44>\n+\tldr\tr0, [sp, #344]\t@ 0x158\n+\tadd.w\tr3, r4, r4, lsr #31\n \tadds\tr2, #2\n-\tvmov\tr5, s15\n-\tstr\tr2, [sp, #256]\t@ 0x100\n-\tvmov.f64\td18, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tmul.w\tr4, r1, r3\n-\tadd.w\tr3, r0, r0, lsr #31\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #220]\t@ 0xdc\n+\tstr\tr2, [sp, #476]\t@ 0x1dc\n \tnegs\tr2, r0\n-\tand.w\tr3, r0, #3\n+\tmov.w\tr3, r3, asr #1\n \tand.w\tr1, r2, #3\n-\tstr\tr4, [sp, #148]\t@ 0x94\n+\tldr\tr4, [sp, #624]\t@ 0x270\n+\tstr\tr3, [sp, #448]\t@ 0x1c0\n+\tand.w\tr3, r0, #3\n \tit\tpl\n \tnegpl\tr3, r1\n \tand.w\tr1, r2, #7\n \trsb\tr2, r3, #4\n-\tcmp.w\tr5, #4294967295\t@ 0xffffffff\n+\tsubs\tr6, #1\n+\tcmp.w\tr4, #4294967295\t@ 0xffffffff\n \tit\teq\n \tmoveq\tr3, r2\n-\tlsrs\tr2, r4, #31\n+\tvmov.f64\td6, #240\t@ 0xbf800000 -1.0\n \tcmp\tr3, #3\n-\tstr\tr2, [sp, #196]\t@ 0xc4\n-\trsb\tr2, r4, #0\n-\tstr\tr2, [sp, #176]\t@ 0xb0\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\tvseleq.f64\td18, d18, d16\n+\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n+\tmul.w\tr5, r5, r6\n+\tstr\tr5, [sp, #340]\t@ 0x154\n+\tit\teq\n+\tvmoveq.f64\td13, d6\n \tnegs\tr3, r0\n \tand.w\tr3, r0, #7\n \tit\tpl\n \tnegpl\tr3, r1\n-\tstr\tr3, [sp, #224]\t@ 0xe0\n+\tstr\tr3, [sp, #452]\t@ 0x1c4\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #16]\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tlsrs\tr2, r5, #31\n+\tstr\tr3, [sp, #456]\t@ 0x1c8\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tstr\tr2, [sp, #428]\t@ 0x1ac\n+\tnegs\tr2, r5\n+\tstr\tr2, [sp, #384]\t@ 0x180\n+\tsubs\tr3, #4\n+\tldr\tr2, [sp, #608]\t@ 0x260\n+\tstr\tr3, [sp, #356]\t@ 0x164\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n \tlsls\tr2, r2, #2\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n-\tvneg.f64\td20, d18\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tstr\tr2, [sp, #172]\t@ 0xac\n-\tmov.w\tr9, #0\n+\tstr\tr2, [sp, #380]\t@ 0x17c\n \tcmp.w\tr3, #1024\t@ 0x400\n-\tble.n\t49d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x108>\n+\titt\tle\n+\tmovle\tr3, #0\n+\tstrle\tr3, [sp, #440]\t@ 0x1b8\n+\tble.n\t4ce0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x128>\n \tcmp.w\tr3, #2048\t@ 0x800\n-\tblt.w\t82f8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a28>\n-\tsub.w\tr9, r3, #1024\t@ 0x400\n+\tblt.w\t86e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b30>\n+\tsub.w\tr3, r3, #1024\t@ 0x400\n+\tstr\tr3, [sp, #440]\t@ 0x1b8\n \tmov.w\tr3, #1024\t@ 0x400\n-\tstr\tr3, [sp, #404]\t@ 0x194\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #620]\t@ 0x26c\n+\tldr\tr3, [sp, #424]\t@ 0x1a8\n \tcmp\tr3, #0\n-\tbne.w\t77f4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f24>\n+\tbne.w\t607c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14c4>\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tldr\tr3, [sp, #372]\t@ 0x174\n \tcmp\tr3, #0\n-\tbeq.w\t652a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c5a>\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tbeq.w\t69d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1e20>\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tldr\tr4, [sp, #296]\t@ 0x128\n \tlsls\tr3, r3, #1\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tsdiv\tr0, r2, r3\n-\tsub.w\tsl, r0, r2\n-\tmovs.w\tip, r0, lsl #1\n-\tbmi.w\t6514 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c44>\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tudiv\tr1, r3, ip\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr6, r0\n+\tsub.w\tsl, r0, r4\n+\tlsls\tr7, r0, #1\n+\tbmi.w\t69c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1e0a>\n+\tmov\tr1, r7\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #428]\t@ 0x1ac\n+\tmov\tr1, r0\n \tcmp\tr3, #0\n-\tbne.n\t4b0e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23e>\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tbne.n\t4ddc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x224>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n \tcmp\tr3, #0\n-\tble.n\t4b0e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23e>\n-\tldr\tr3, [sp, #392]\t@ 0x188\n+\tble.n\t4ddc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x224>\n+\tldr\tr3, [sp, #608]\t@ 0x260\n \tcmp\tr3, #1\n-\tbne.w\t646c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b9c>\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tstr.w\tsl, [sp, #8]\n-\tldr\tr2, [sp, #16]\n-\tlsrs\tr3, r3, #2\n-\tldr.w\tsl, [sp, #124]\t@ 0x7c\n-\tlsls\tr3, r3, #4\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tbic.w\tlr, r3, #3\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tbne.w\t5fae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13f6>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tldr\tr0, [sp, #152]\t@ 0x98\n+\tldr.w\tr9, [sp, #336]\t@ 0x150\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tsubs\tr4, r3, #4\n-\tstr\tr4, [sp, #32]\n-\tldr\tr4, [sp, #404]\t@ 0x194\n-\tand.w\tfp, r4, #3\n-\tmov\tr4, ip\n-\tmov\tip, r3\n-\tmov\tr5, r2\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tmovs\tr3, #1\n-\tstr.w\tr9, [sp, #44]\t@ 0x2c\n-\tmov\tr9, r0\n-\tstr\tr3, [sp, #0]\n-\tstrd\tr4, r1, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #8]\n-\tldr\tr1, [sp, #16]\n-\tadd\tr3, r5\n-\tcmp\tr1, r3\n-\tble.n\t4a74 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1a4>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr3, r1\n-\tcmp\tr2, #0\n-\tble.n\t4adc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x20c>\n-\tcmp\tr2, #1\n-\tbeq.n\t4a84 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b4>\n-\tadds\tr1, r5, #3\n-\tsubs\tr1, r1, r3\n-\tcmp\tr1, #6\n-\tbhi.n\t4b38 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x268>\n+\tldr.w\tfp, [sp, #620]\t@ 0x26c\n+\tstr\tr3, [sp, #8]\n+\tmov\tr2, r0\n+\tmov.w\tip, #1\n+\tstr\tr0, [sp, #0]\n+\tldr\tr4, [sp, #152]\t@ 0x98\n+\tadd.w\tr3, sl, r2\n+\tcmp\tr4, r3\n+\titt\tgt\n+\tldrgt\tr4, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r4\n+\tcmp.w\tfp, #0\n+\tble.n\t4dba <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x202>\n+\tldr\tr5, [sp, #356]\t@ 0x164\n+\tadd.w\tr4, r2, #1073741824\t@ 0x40000000\n+\tadd.w\tr8, fp, r2\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tadd.w\tr1, r5, #1073741824\t@ 0x40000000\n-\tldr\tr4, [sp, #32]\n+\tsubs\tr4, #1\n \tsubs\tr3, #1\n-\tsubs\tr1, #1\n-\tadds\tr0, r2, r5\n+\tadd.w\tr8, r5, r8, lsl #2\n+\tldr\tr5, [sp, #332]\t@ 0x14c\n+\tlsls\tr4, r4, #2\n \tlsls\tr3, r3, #2\n-\tlsls\tr1, r1, #2\n-\tadd.w\tr6, r4, r0, lsl #2\n-\tadd.w\tr0, ip, r1\n-\tadd.w\tr4, ip, r3\n-\tadd\tr1, sl\n-\tadd\tr3, sl\n-\tvldr\ts12, [r4]\n-\tvldr\ts14, [r0]\n-\tvldr\ts15, [r1]\n+\tadds\tr0, r5, r4\n+\tadd.w\tlr, r5, r3\n+\tmov\tr5, r0\n+\tldr\tr0, [sp, #0]\n+\tadd\tr4, r9\n+\tadd\tr3, r9\n+\tvldr\ts12, [lr]\n+\tvldr\ts14, [r5]\n+\tvldr\ts15, [r4]\n \tvldr\ts13, [r3]\n \tvadd.f32\ts11, s12, s14\n \tvsub.f32\ts14, s14, s12\n \tvadd.f32\ts12, s13, s15\n \tvsub.f32\ts15, s15, s13\n-\tvstmia\tr0!, {s11}\n-\tcmp\tr0, r6\n-\tvstmia\tr4!, {s14}\n-\tvstmia\tr1!, {s12}\n+\tvstmia\tr5!, {s11}\n+\tcmp\tr5, r8\n+\tvstmia\tlr!, {s14}\n+\tvstmia\tr4!, {s12}\n \tvstmia\tr3!, {s15}\n-\tbne.n\t4aa8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d8>\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, r5\n-\tble.n\t4aea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #0]\n-\tldr\tr1, [sp, #4]\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tcmp\tr3, r1\n-\tbne.n\t4a66 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x196>\n-\tldrd\tr4, r1, [sp, #36]\t@ 0x24\n-\tmov\tr0, r9\n-\tldrd\tr9, r2, [sp, #44]\t@ 0x2c\n-\tsubs\tr1, #1\n-\tadds\tr5, r1, #1\n-\tadd\tr2, r4\n-\tbne.n\t4a52 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x182>\n-\tldr.w\tsl, [sp, #8]\n-\tmov\tip, r4\n-\tldr\tr3, [sp, #400]\t@ 0x190\n-\tcmp\tr3, #1\n-\tbne.w\t4c5e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38e>\n-\tldr\tr3, [sp, #16]\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tldr\tr1, [sp, #392]\t@ 0x188\n-\tmla\tr3, r1, r2, r3\n-\tldr\tr2, [sp, #256]\t@ 0x100\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #228]\t@ 0xe4\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n+\tbne.n\t4d84 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1cc>\n+\tstr\tr0, [sp, #0]\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd.w\tip, ip, #1\n+\tadd\tr2, r3\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r2\n-\tbeq.w\t82ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a1e>\n-\tmov\tr3, r9\n-\tstr.w\tr9, [sp, #404]\t@ 0x194\n-\tb.n\t49bc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xec>\n-\tldr\tr1, [sp, #12]\n-\tcmp\tr1, #2\n-\tbls.w\t4c46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x376>\n-\tadd.w\tr0, r5, #1073741824\t@ 0x40000000\n-\tadd.w\tr1, r3, #1073741824\t@ 0x40000000\n-\tsubs\tr0, #1\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #8]\n+\tcmp\tip, r3\n+\tbne.n\t4d46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x18e>\n+\tldr\tr0, [sp, #0]\n \tsubs\tr1, #1\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tlsls\tr4, r0, #2\n-\tlsls\tr6, r1, #2\n-\tadd.w\tr8, sl, r4\n-\tadd\tr4, ip\n-\tstr\tr4, [sp, #20]\n-\tadd.w\tr7, sl, r6\n-\tldr\tr4, [sp, #24]\n-\tadd\tr6, ip\n-\tadds\tr4, r7, r4\n-\tstr\tr4, [sp, #28]\n-\tldr\tr4, [sp, #20]\n-\tvld1.32\t{d26-d27}, [r6]\n-\tvld1.32\t{d22-d23}, [r4]\n-\tvld1.32\t{d16-d17}, [r8]\n-\tvld1.32\t{d24-d25}, [r7]\n-\tvadd.f32\tq14, q13, q11\n-\tldr\tr3, [sp, #28]\n-\tvsub.f32\tq11, q11, q13\n-\tvadd.f32\tq13, q8, q12\n-\tvsub.f32\tq8, q8, q12\n-\tvst1.32\t{d28-d29}, [r4]!\n-\tvst1.32\t{d26-d27}, [r8]!\n-\tvst1.32\t{d22-d23}, [r6]!\n-\tvst1.32\t{d16-d17}, [r7]!\n-\tcmp\tr7, r3\n-\tbne.n\t4b68 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x298>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tcmp\tlr, r2\n-\tbeq.n\t4adc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x20c>\n-\tmov\tr4, fp\n-\tcmp.w\tfp, #1\n-\tbeq.n\t4c5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38a>\n-\tmov\tr6, lr\n-\tmov\tr7, lr\n+\tadds\tr4, r1, #1\n \tadd\tr0, r7\n-\tadd\tr1, r7\n-\tlsls\tr0, r0, #2\n-\tlsls\tr1, r1, #2\n-\tadd.w\tr7, ip, r1\n-\tadd.w\tr8, ip, r0\n-\tadd\tr1, sl\n-\tadd\tr0, sl\n-\tvld1.32\t{d21}, [r7]\n-\tvld1.32\t{d17}, [r8]\n-\tvld1.32\t{d16}, [r0]\n-\tvld1.32\t{d19}, [r1]\n-\tvadd.f32\td22, d21, d17\n-\tvsub.f32\td17, d17, d21\n-\tvst1.32\t{d22}, [r8]\n-\tvst1.32\t{d17}, [r7]\n-\tvadd.f32\td17, d16, d19\n-\tvsub.f32\td16, d16, d19\n-\tlsls\tr7, r4, #31\n-\tvst1.32\t{d17}, [r0]\n-\tvst1.32\t{d16}, [r1]\n-\tbpl.w\t4adc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x20c>\n-\tbic.w\tr0, r4, #1\n-\tadd\tr0, r6\n-\tadds\tr1, r0, r3\n-\tadds\tr3, r0, r5\n-\tlsls\tr1, r1, #2\n-\tlsls\tr3, r3, #2\n-\tadd.w\tr4, ip, r3\n-\tadd.w\tr0, ip, r1\n-\tadd\tr3, sl\n-\tadd\tr1, sl\n-\tvldr\ts14, [r4, #-4]\n-\tvldr\ts12, [r0, #-4]\n-\tvldr\ts15, [r3, #-4]\n-\tvldr\ts13, [r1, #-4]\n-\tvadd.f32\ts11, s12, s14\n-\tvsub.f32\ts14, s14, s12\n-\tvstr\ts11, [r4, #-4]\n-\tvstr\ts14, [r0, #-4]\n-\tvadd.f32\ts14, s15, s13\n-\tvsub.f32\ts15, s15, s13\n-\tvstr\ts14, [r3, #-4]\n-\tvstr\ts15, [r1, #-4]\n-\tb.n\t4adc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x20c>\n-\tmovs\tr6, #0\n-\tadd.w\tr0, r5, #1073741824\t@ 0x40000000\n-\tadd.w\tr1, r3, #1073741824\t@ 0x40000000\n-\tsubs\tr0, #1\n-\tsubs\tr1, #1\n-\tmov\tr4, r2\n-\tmov\tr7, r6\n-\tb.n\t4bb0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e0>\n-\tmov\tr0, lr\n-\tb.n\t4c00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x330>\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tsubs\tr3, r0, r2\n-\tcmp\tr2, #0\n-\tmov\tr0, r2\n-\tblt.w\t8152 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3882>\n-\tsubs\tr2, r3, r2\n-\tcmp\tr0, r3\n-\tudiv\tr2, r2, r0\n-\tbgt.w\t4dde <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x50e>\n-\tldr\tr0, [sp, #152]\t@ 0x98\n-\tldr\tr3, [sp, #392]\t@ 0x188\n-\tmov.w\tr8, r0, lsl #3\n+\tbne.n\t4d3e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x186>\n+\tldr\tr3, [sp, #616]\t@ 0x268\n \tcmp\tr3, #1\n-\tbne.w\t816e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x389e>\n-\tmov\tlr, r0\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tldrd\tr1, r4, [sp, #144]\t@ 0x90\n-\tadds\tr0, #1\n+\tbeq.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n+\tldr\tr4, [sp, #360]\t@ 0x168\n+\tsubs\tr6, r6, r4\n+\tcmp\tr4, #0\n+\tblt.w\t8534 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x397c>\n+\tmov\tr1, r4\n+\tsubs\tr0, r6, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r6\n+\tmov\tfp, r0\n+\tbgt.w\t4f5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a2>\n+\tldr\tr1, [sp, #364]\t@ 0x16c\n+\tldr\tr3, [sp, #608]\t@ 0x260\n+\tcmp\tr3, #1\n+\tmov.w\tr3, r1, lsl #3\n+\tbne.w\t8552 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x399a>\n+\tldr\tr2, [sp, #360]\t@ 0x168\n+\tmov\tr8, r1\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tldr\tr4, [sp, #404]\t@ 0x194\n+\tmov\tr9, r2\n+\tsubs\tr6, r0, r2\n+\tsubs\tr0, r2, r0\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tadds\tr5, r4, r3\n+\tmov\tr4, r3\n \tstr\tr0, [sp, #8]\n-\trsb\tr5, ip, #0\n-\tldr\tr0, [sp, #120]\t@ 0x78\n-\tsubs\tr6, r4, r1\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tsubs\tr7, r1, r4\n-\tsub.w\tfp, r0, #4\n-\tstr.w\tsl, [sp, #12]\n-\tadd\tr3, r8\n-\tmov\tr4, r8\n-\tmov\tsl, fp\n-\tstr.w\tr9, [sp, #20]\n-\tvldr\td21, [r3, #8]\n-\tcmp.w\tip, #0\n-\tvldr\td22, [r3]\n-\tvmul.f64\td21, d0, d21\n-\tblt.w\t5d76 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a6>\n-\tudiv\tr8, r6, ip\n-\tldr\tr0, [sp, #148]\t@ 0x94\n-\tcmp\tr0, r1\n-\tblt.n\t4dc4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4f4>\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tcmp\tr0, #0\n-\tble.n\t4dc4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4f4>\n-\tldr\tr0, [sp, #16]\n-\tmov\tfp, r3\n-\tstrd\tr2, r1, [sp, #24]\n-\tadd.w\tr9, r0, r1\n-\tstr\tr6, [sp, #32]\n-\tmov\tr1, r9\n-\tmovs\tr6, #1\n-\tstrd\tip, r8, [sp, #36]\t@ 0x24\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #24]\n+\tnegs\tr2, r7\n+\tstrd\tr2, sl, [sp, #28]\n+\tvldr\td8, [r5, #8]\n+\tcmp\tr7, #0\n+\tvldr\td7, [sp, #392]\t@ 0x188\n+\tvldr\td9, [r5]\n+\tvmul.f64\td8, d7, d8\n+\tblt.w\t8520 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3968>\n+\tmov\tr1, r7\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tcmp\tr3, r9\n+\tblt.n\t4f3a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x382>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tcmp\tr3, #0\n+\tble.n\t4f3a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x382>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tmov\tlr, fp\n+\tadd.w\tip, r3, r9\n+\tmov\tr1, ip\n+\tmov.w\tsl, #1\n+\tstr\tr7, [sp, #40]\t@ 0x28\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tstr\tr4, [sp, #0]\n-\tldr\tr3, [sp, #12]\n-\tldr\tr2, [sp, #16]\n+\tldr\tr3, [sp, #32]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tadd\tr3, r1\n \tcmp\tr2, r3\n-\tble.n\t4cf8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x428>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #220]\t@ 0xdc\n-\tcmp\tr2, lr\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tbeq.w\t5ce8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1418>\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #448]\t@ 0x1c0\n+\tcmp\tr2, r8\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n+\tbeq.w\t8494 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38dc>\n \tcmp\tr2, #0\n-\tble.n\t4d94 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4c4>\n+\tble.n\t4f12 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35a>\n \tmov\tr0, r2\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tadd.w\tip, r0, r1\n+\tadds\tr7, r0, r1\n+\tldr\tr0, [sp, #356]\t@ 0x164\n \tadd.w\tr2, r1, #1073741824\t@ 0x40000000\n \tsubs\tr3, #1\n \tsubs\tr2, #1\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tadd.w\tr0, sl, ip, lsl #2\n-\tstr\tr0, [sp, #4]\n+\tldr\tr4, [sp, #332]\t@ 0x14c\n+\tadd.w\tr0, r0, r7, lsl #2\n+\tstr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #336]\t@ 0x150\n \tlsls\tr3, r3, #2\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n \tlsls\tr2, r2, #2\n-\tadd.w\tip, r4, r2\n-\tadd.w\tr8, r4, r3\n-\tadd\tr2, r0\n+\tadd.w\tfp, r4, r3\n+\tadds\tr7, r4, r2\n \tadd\tr3, r0\n-\tldrd\tr4, r0, [sp]\n+\tadd\tr2, r0\n+\tldr\tr4, [sp, #0]\n+\tldr\tr0, [sp, #16]\n \tvldr\ts13, [r2]\n \tvldr\ts15, [r3]\n-\tvldr\ts12, [ip]\n-\tvldr\ts14, [r8]\n-\tvcvt.f64.f32\td16, s13\n-\tvcvt.f64.f32\td23, s15\n+\tvldr\ts12, [r7]\n+\tvldr\ts14, [fp]\n+\tvcvt.f64.f32\td4, s13\n+\tvcvt.f64.f32\td2, s15\n \tvadd.f32\ts15, s15, s13\n-\tvcvt.f64.f32\td19, s12\n-\tvcvt.f64.f32\td17, s14\n+\tvcvt.f64.f32\td5, s12\n+\tvcvt.f64.f32\td3, s14\n \tvadd.f32\ts14, s14, s12\n-\tvsub.f64\td16, d16, d23\n+\tvsub.f64\td4, d4, d2\n \tvstmia\tr2!, {s15}\n-\tvsub.f64\td19, d19, d17\n-\tvstmia\tip!, {s14}\n-\tcmp\tip, r0\n-\tvnmul.f64\td17, d21, d16\n-\tvmul.f64\td16, d16, d22\n-\tvfma.f64\td17, d19, d22\n-\tvfma.f64\td16, d19, d21\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts15, d16\n-\tvstmia\tr8!, {s14}\n-\tvstmia\tr3!, {s15}\n-\tbne.n\t4d36 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x466>\n+\tvsub.f64\td5, d5, d3\n+\tvstmia\tr7!, {s14}\n+\tcmp\tr7, r0\n+\tvmul.f64\td7, d4, d8\n+\tvmul.f64\td6, d5, d8\n+\tvmla.f64\td6, d4, d9\n+\tvnmls.f64\td7, d5, d9\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr3!, {s12}\n+\tvstmia\tfp!, {s14}\n+\tbne.n\t4eb4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2fc>\n \tstr\tr4, [sp, #0]\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd.w\tsl, sl, #1\n \tadd\tr1, r3\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r1\n-\tble.n\t4da2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4d2>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #8]\n-\tadds\tr6, #1\n-\tcmp\tr6, r3\n-\tbne.n\t4cea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x41a>\n-\tldrd\tip, r8, [sp, #36]\t@ 0x24\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #24]\n+\tcmp\tsl, r3\n+\tbne.n\t4e6a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2b2>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr7, [sp, #40]\t@ 0x28\n+\tsubs\tr0, #1\n \tldr\tr4, [sp, #0]\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tadd\tr9, ip\n-\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n-\tbne.n\t4ce0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x410>\n-\tldrd\tr2, r1, [sp, #24]\n-\tmov\tr3, fp\n-\tldr\tr6, [sp, #32]\n-\tldr\tr0, [sp, #152]\t@ 0x98\n-\tsubs\tr2, #1\n-\tadd\tr3, r4\n-\tadd\tlr, r0\n-\tldr\tr0, [sp, #144]\t@ 0x90\n-\tadd\tr1, r0\n-\tsubs\tr6, r6, r0\n-\tadd\tr7, r0\n-\tadds\tr0, r2, #1\n-\tbne.w\t4cae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3de>\n-\tldr.w\tr9, [sp, #20]\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #204]\t@ 0xcc\n-\tcmp\tr2, r3\n-\tblt.w\t4b16 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x246>\n-\tldr.w\tfp, [sp, #148]\t@ 0x94\n-\tstr.w\tr9, [sp, #236]\t@ 0xec\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tmov\tr6, r3\n+\tadd\tip, r7\n+\tadds\tr3, r0, #1\n+\tbne.n\t4e5e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a6>\n+\tmov\tfp, lr\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [sp, #8]\n+\tadd\tr5, r4\n+\tadd\tr8, r3\n+\tldr\tr3, [sp, #360]\t@ 0x168\n+\tcmp.w\tfp, #4294967295\t@ 0xffffffff\n+\tadd\tr2, r3\n+\tadd\tr9, r3\n+\tsub.w\tr6, r6, r3\n+\tstr\tr2, [sp, #8]\n+\tbne.w\t4e2c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x274>\n+\tldr\tr3, [sp, #424]\t@ 0x1a8\n+\tadd.w\tsl, r3, #1\n+\tldr\tr3, [sp, #388]\t@ 0x184\n+\tcmp\tr3, sl\n+\tblt.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n+\tmov\tr8, sl\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tldr\tr5, [sp, #296]\t@ 0x128\n+\tmov\tr4, r3\n+\tstr\tr3, [sp, #196]\t@ 0xc4\n \tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tsdiv\tlr, r3, r2\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tmul.w\tsl, r6, r2\n-\tmovs.w\tip, lr, lsl #2\n-\tsub.w\tr2, sl, r2\n-\tsub.w\tr1, sl, r3\n-\tstr\tr2, [sp, #188]\t@ 0xbc\n-\tsub.w\tr3, lr, r3\n-\tstr\tr1, [sp, #100]\t@ 0x64\n+\tmov\tr0, r5\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #360]\t@ 0x168\n+\tmov\tr2, r0\n+\tstr\tr0, [sp, #192]\t@ 0xc0\n+\tsubs\tr0, r0, r5\n+\tstr\tr0, [sp, #284]\t@ 0x11c\n+\tlsls\tr2, r2, #2\n+\tstr\tr2, [sp, #400]\t@ 0x190\n+\tmul.w\tr6, r4, r3\n+\tsub.w\tr3, r6, r3\n+\tsub.w\tr1, r6, r5\n+\tstr\tr3, [sp, #408]\t@ 0x198\n+\tmov\tr5, r3\n+\tstr\tr1, [sp, #308]\t@ 0x134\n+\tbmi.w\t8480 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38c8>\n \tmov\tr1, r2\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tbmi.w\t748c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2bbc>\n-\tudiv\tr4, r2, ip\n-\tcmp\tr2, #0\n-\tblt.w\t5466 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb96>\n-\tmov.w\tr0, sl, lsl #2\n-\tnegs\tr3, r0\n-\tstr\tr3, [sp, #200]\t@ 0xc8\n-\tldr\tr3, [sp, #392]\t@ 0x188\n+\tmov\tr0, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tr4, r0\n+\tblt.w\t55f0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa38>\n+\tmov.w\tr9, r6, lsl #2\n+\trsb\tr3, r9, #0\n+\tstr\tr3, [sp, #184]\t@ 0xb8\n+\tldr\tr3, [sp, #608]\t@ 0x260\n \tcmp\tr3, #1\n-\tbne.w\t5d96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14c6>\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tmov\tr8, fp\n-\tldr\tr7, [sp, #176]\t@ 0xb0\n-\tmovs\tr5, #0\n-\tsub.w\tr9, r3, #4\n-\tstr.w\tr9, [sp, #168]\t@ 0xa8\n-\tcmp\tr0, #0\n-\tblt.w\t5d86 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14b6>\n-\tudiv\tr3, r8, r0\n-\tcmp\tfp, r5\n-\tblt.w\t5456 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb86>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n+\tbne.w\t7d52 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x319a>\n+\tldr\tr3, [sp, #384]\t@ 0x180\n+\tmovs\tr7, #0\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tmov\tsl, r3\n+\tldr\tr5, [sp, #400]\t@ 0x190\n+\tstr.w\tr8, [sp, #200]\t@ 0xc8\n+\tmov\tr8, r2\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #180]\t@ 0xb4\n+\tcmp.w\tr9, #0\n+\tblt.w\t7d3c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3184>\n+\tmov\tr1, r9\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r7\n+\tblt.w\t55dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa24>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n \tcmp\tr2, #0\n-\tble.w\t5456 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb86>\n-\tldr\tr1, [sp, #16]\n-\tadds\tr2, #1\n-\tstrd\tlr, r4, [sp, #208]\t@ 0xd0\n-\tadd\tr1, r5\n-\tstr\tr2, [sp, #156]\t@ 0x9c\n+\tble.w\t55dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa24>\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr4, [sp, #204]\t@ 0xcc\n+\tadds\tr1, r2, r7\n \tmovs\tr2, #1\n-\tstr\tr1, [sp, #128]\t@ 0x80\n-\tstr\tr2, [sp, #136]\t@ 0x88\n-\tstr\tr5, [sp, #216]\t@ 0xd8\n-\tstr.w\tsl, [sp, #232]\t@ 0xe8\n-\tstrd\tip, r0, [sp, #240]\t@ 0xf0\n-\tstrd\tfp, r6, [sp, #248]\t@ 0xf8\n-\tstrd\tr3, r1, [sp, #260]\t@ 0x104\n-\tstrd\tr8, r7, [sp, #268]\t@ 0x10c\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr1, [sp, #172]\t@ 0xac\n+\tstr\tr2, [sp, #176]\t@ 0xb0\n+\tstr\tr7, [sp, #208]\t@ 0xd0\n+\tstr\tr6, [sp, #216]\t@ 0xd8\n+\tstrd\tr5, r9, [sp, #224]\t@ 0xe0\n+\tstrd\tr3, r1, [sp, #232]\t@ 0xe8\n+\tstrd\tr8, sl, [sp, #240]\t@ 0xf0\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tldr\tr2, [sp, #172]\t@ 0xac\n \tadds\tr6, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r6\n-\tble.n\t4ea0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x5d0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr6, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadds\tr0, r3, r6\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r0\n-\tble.n\t4eae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x5de>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr0, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadds\tr2, r3, r0\n-\tldr\tr3, [sp, #16]\n-\tstr\tr2, [sp, #8]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tstr\tr2, [sp, #16]\n \tcmp\tr3, r2\n-\tble.n\t4ec0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x5f0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr2, r3\n-\tstr\tr2, [sp, #8]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr2, [sp, #128]\t@ 0x80\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #308]\t@ 0x134\n+\tit\tgt\n+\tstrgt\tr2, [sp, #16]\n+\tldr\tr2, [sp, #172]\t@ 0xac\n \tadds\tr2, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r2\n-\tble.n\t4ed0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x600>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tfp, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, fp\n-\tble.n\t4ee0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x610>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tfp, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tip, r3, fp\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, ip\n-\tble.n\t4ef0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x620>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tip, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tsl, r3, ip\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, sl\n-\tble.n\t4f00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x630>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tsl, r3\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tsl, r3\n+\tldr\tr3, [sp, #308]\t@ 0x134\n \tadds\tr5, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r5\n-\tble.n\t4f0e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x63e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tr9, r3, r5\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r9\n-\tble.n\t4f1e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x64e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr9, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr9, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tr8, r3, r9\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr1, [sp, #152]\t@ 0x98\n \tcmp\tr3, r8\n-\tble.n\t4f2e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x65e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr8, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd.w\tlr, r3, r8\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, lr\n-\tble.n\t4f3e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x66e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr1, [sp, #16]\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tlr, r3\n+\tldr\tr3, [sp, #308]\t@ 0x134\n \tadds\tr4, r3, r5\n \tstr\tr4, [sp, #0]\n \tcmp\tr1, r4\n-\tble.n\t4f50 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x680>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr4, r3\n-\tstr\tr4, [sp, #0]\n-\tldr\tr1, [sp, #84]\t@ 0x54\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tittt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r3\n+\tstrgt\tr4, [sp, #0]\n+\tldr\tr4, [sp, #152]\t@ 0x98\n \tldr\tr3, [sp, #0]\n-\tldr\tr4, [sp, #16]\n \tadd\tr1, r3\n \tcmp\tr4, r1\n-\tble.n\t4f60 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x690>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr1, r3\n-\tldr\tr4, [sp, #84]\t@ 0x54\n+\tldr\tr4, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r3\n \tadds\tr7, r4, r1\n-\tldr\tr4, [sp, #16]\n+\tldr\tr4, [sp, #152]\t@ 0x98\n \tcmp\tr4, r7\n-\tble.n\t4f6e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x69e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr7, r3\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #16]\n+\tldr\tr4, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr7, r7, r3\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tadd\tr4, r7\n-\tstr\tr4, [sp, #4]\n+\tstr\tr4, [sp, #8]\n \tcmp\tr3, r4\n-\tble.n\t4f80 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x6b0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr4, r3\n-\tstr\tr4, [sp, #4]\n-\tldr\tr3, [sp, #404]\t@ 0x194\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r3\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tit\tgt\n+\tstrgt\tr4, [sp, #8]\n \tcmp\tr3, #0\n-\tble.w\t5410 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb40>\n-\tldr\tr3, [sp, #8]\n+\tble.w\t559e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x9e6>\n+\tldr\tr3, [sp, #16]\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tsubs\tr2, #1\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n \tadd.w\tr4, r3, #1073741824\t@ 0x40000000\n \tldr\tr3, [sp, #0]\n \tlsls\tr2, r2, #2\n-\tstr\tr2, [sp, #12]\n+\tstr\tr2, [sp, #24]\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n \tsubs\tr0, #1\n \tsubs\tr3, #1\n \tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tlsls\tr0, r0, #2\n \tsubs\tr6, #1\n \tlsls\tr2, r3, #2\n \tmov.w\tr3, ip, lsl #2\n-\tstr\tr3, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tmov.w\tr3, fp, lsl #2\n-\tstr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tmov.w\tr3, sl, lsl #2\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #32]\n \tmov.w\tr3, r9, lsl #2\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #136]\t@ 0x88\n \tmov.w\tr3, r8, lsl #2\n-\tstr\tr3, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #144]\t@ 0x90\n \tmov.w\tr3, lr, lsl #2\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n \tlsls\tr3, r7, #2\n-\tstr\tr3, [sp, #28]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tlsls\tr3, r1, #2\n-\tstr\tr3, [sp, #96]\t@ 0x60\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n \tlsls\tr6, r6, #2\n-\tldr\tr3, [sp, #4]\n+\tldr\tr3, [sp, #8]\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n-\tldr\tr1, [sp, #404]\t@ 0x194\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n \tsubs\tr5, #1\n-\tstr\tr2, [sp, #20]\n+\tstr\tr2, [sp, #28]\n \tsubs\tr4, #1\n \tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr3, [sp, #172]\t@ 0xac\n \tlsls\tr5, r5, #2\n-\tldr\tr2, [sp, #168]\t@ 0xa8\n+\tldr\tr2, [sp, #356]\t@ 0x164\n \tlsls\tr4, r4, #2\n \tadd\tr1, r3\n \tadd.w\tr7, r3, #1073741824\t@ 0x40000000\n \tsubs\tr7, #1\n \tadd.w\tr2, r2, r1, lsl #2\n \tlsls\tr1, r3, #2\n-\tstr\tr2, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #168]\t@ 0xa8\n \tnegs\tr3, r1\n-\tldr\tr2, [sp, #120]\t@ 0x78\n+\tldr\tr2, [sp, #332]\t@ 0x14c\n \tlsls\tr7, r7, #2\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #336]\t@ 0x150\n \tmov\tr1, r2\n \tadd\tr1, r7\n \tadd\tr2, r0\n \tadd\tr7, r3\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #336]\t@ 0x150\n \tstr\tr2, [sp, #0]\n \tadd\tr0, r3\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tadds\tr2, r3, r6\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tstr\tr2, [sp, #4]\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n \tadds\tr2, r3, r6\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tldr\tr3, [sp, #336]\t@ 0x150\n \tstr\tr2, [sp, #8]\n+\tadds\tr2, r3, r6\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n+\tstr\tr2, [sp, #16]\n \tadd.w\tip, r3, r5\n-\tldr\tr2, [sp, #12]\n+\tldr\tr2, [sp, #24]\n \tadd.w\tr9, r6, r5\n \tadd.w\tfp, r6, r4\n-\tstr.w\tr9, [sp, #32]\n+\tstr.w\tr9, [sp, #48]\t@ 0x30\n \tadd.w\tlr, r6, r2\n \tmov\tr5, r2\n-\tldr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #28]\n \tadd\tr4, r3\n \tadd\tr5, r3\n \tmov\tsl, lr\n \tadd\tr3, r2\n \tmov\tr9, r0\n \tadd\tr2, r6\n \tmov\tr6, r7\n-\tstr\tr3, [sp, #20]\n-\tstr\tr4, [sp, #12]\n-\tstrd\tr5, ip, [sp, #36]\t@ 0x24\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #12]\n-\tldr\tr3, [sp, #0]\n-\tldr\tr7, [sp, #8]\n-\tvldr\ts10, [fp]\n+\tstr\tr3, [sp, #28]\n+\tstr\tr4, [sp, #24]\n+\tstr\tr5, [sp, #56]\t@ 0x38\n+\tstr.w\tip, [sp, #64]\t@ 0x40\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #24]\n+\tldr\tr7, [sp, #16]\n+\tvldr\ts0, [fp]\n+\tvldr\ts14, [r9]\n \tvldr\ts12, [r2]\n-\tldr\tr2, [sp, #4]\n-\tvldr\ts8, [r3]\n+\tldr\tr2, [sp, #8]\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts6, [r7]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts4, [r6]\n+\tvcvt.f64.f32\td6, s12\n+\tldr\tr3, [sp, #0]\n+\tvldr\ts10, [r2]\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts8, [r1]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tvcvt.f64.f32\td5, s10\n-\tvldr\ts13, [r9]\n-\tvldr\ts15, [r1]\n-\tvldr\ts6, [r2]\n+\tvldr\ts2, [r3]\n \tvcvt.f64.f32\td4, s8\n-\tvldr\ts14, [r6]\n-\tvcvt.f64.f32\td22, s13\n-\tvldr\ts7, [r7]\n-\tvcvt.f64.f32\td17, s15\n-\tvcvt.f64.f32\td19, s6\n-\tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td16, s14\n-\tldr\tr3, [sp, #32]\n-\tvcvt.f64.f32\td23, s7\n-\tvldr\ts6, [sl]\n-\tvadd.f64\td21, d4, d17\n-\tvsub.f64\td17, d17, d4\n-\tvadd.f64\td28, d5, d19\n-\tvsub.f64\td19, d19, d5\n-\tvadd.f64\td25, d22, d16\n-\tvsub.f64\td16, d16, d22\n-\tvadd.f64\td27, d6, d23\n-\tvsub.f64\td23, d23, d6\n-\tvldr\ts7, [r3]\n-\tvcvt.f64.f32\td26, s6\n-\tvadd.f64\td7, d28, d21\n-\tvsub.f64\td22, d21, d28\n-\tvmov.f64\td24, d16\n-\tvmov.f64\td28, d17\n-\tvfma.f64\td24, d19, d20\n-\tvfma.f64\td28, d23, d20\n-\tvadd.f64\td29, d27, d25\n-\tldr\tr0, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #28]\n+\tvadd.f64\td10, d7, d2\n+\tvsub.f64\td7, d2, d7\n+\tvcvt.f64.f32\td1, s2\n+\tvadd.f64\td2, d6, d3\n+\tvadd.f64\td8, d0, d5\n+\tvsub.f64\td6, d3, d6\n+\tvsub.f64\td5, d5, d0\n+\tldr\tr5, [sp, #128]\t@ 0x80\n+\tldr\tr7, [sp, #32]\n+\tvadd.f64\td9, d1, d4\n+\tvsub.f64\td4, d4, d1\n+\tvmul.f64\td6, d6, d13\n+\tvldr\ts23, [r0]\n+\tvmul.f64\td5, d5, d13\n+\tvldr\ts22, [sl]\n+\tvadd.f64\td3, d8, d9\n+\tvsub.f64\td9, d9, d8\n+\tvadd.f64\td8, d2, d10\n+\tvsub.f64\td2, d10, d2\n+\tvsub.f64\td10, d4, d6\n+\tvadd.f64\td6, d6, d4\n+\tvsub.f64\td4, d7, d5\n+\tvadd.f64\td7, d7, d5\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts18, d9\n+\tvcvt.f32.f64\ts16, d8\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts20, d10\n+\tvcvt.f32.f64\ts5, d6\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f64.f32\td1, s22\n+\tvstmia\tr1!, {s6}\n+\tvcvt.f64.f32\td0, s23\n+\tvstmia\tr6!, {s16}\n \tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d22\n-\tvfma.f64\td16, d18, d19\n-\tldr\tr5, [sp, #72]\t@ 0x48\n-\tvfma.f64\td17, d18, d23\n-\tldr\tr7, [sp, #24]\n-\tvcvt.f32.f64\ts10, d29\n-\tvsub.f64\td25, d25, d27\n-\tvstmia\tr1!, {s14}\n-\tvcvt.f64.f32\td21, s7\n-\tvstmia\tr3!, {s15}\n-\tvcvt.f32.f64\ts14, d24\n-\tstr\tr3, [sp, #32]\n-\tvcvt.f32.f64\ts13, d28\n-\tldr\tr3, [sp, #20]\n-\tvstmia\tr6!, {s10}\n-\tvcvt.f32.f64\ts11, d25\n-\tvcvt.f32.f64\ts12, d16\n-\tvcvt.f32.f64\ts15, d17\n-\tvstmia\tsl!, {s13}\n-\tvldr\ts13, [r3]\n-\tvstmia\tr3!, {s14}\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvcvt.f64.f32\td19, s13\n-\tvldr\ts14, [r0]\n+\tvldr\ts16, [r3]\n+\tvstmia\tr3!, {s8}\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvcvt.f64.f32\td8, s16\n+\tvstmia\tr0!, {s18}\n \tadds\tr2, r1, r3\n-\tadds\tr3, r6, r3\n+\tvstmia\tsl!, {s20}\n \tadds\tr4, r2, r5\n \tadds\tr7, r2, r7\n-\tvcvt.f64.f32\td24, s14\n+\tadds\tr3, r6, r3\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr0, [sp, #56]\t@ 0x38\n \tadds\tr5, r3, r5\n-\tstr\tr7, [sp, #48]\t@ 0x30\n-\tvldr\ts14, [r4, #-4]\n-\tvcvt.f64.f32\td16, s14\n-\tvldr\ts14, [r7, #-4]\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts14, [r5, #-4]\n-\tldr\tr7, [sp, #24]\n+\tvldr\ts12, [r4, #-4]\n+\tvldr\ts8, [r7, #-4]\n+\tstr\tr7, [sp, #80]\t@ 0x50\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts20, [r0]\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f64.f32\td10, s20\n+\tvsub.f64\td9, d6, d4\n+\tvadd.f64\td4, d4, d6\n+\tvldr\ts12, [r5, #-4]\n+\tldr\tr7, [sp, #32]\n \tadds\tr7, r3, r7\n-\tstr\tr7, [sp, #56]\t@ 0x38\n-\tvsub.f64\td23, d16, d17\n-\tvadd.f64\td17, d17, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvldr\ts14, [r7, #-4]\n-\tldr\tr7, [sp, #68]\t@ 0x44\n+\tstr\tr7, [sp, #96]\t@ 0x60\n+\tvcvt.f64.f32\td6, s12\n+\tvmul.f64\td9, d9, d13\n+\tvldr\ts10, [r7, #-4]\n+\tldr\tr7, [sp, #120]\t@ 0x78\n+\tvcvt.f64.f32\td5, s10\n \tadd.w\tip, r2, r7\n-\tvcvt.f64.f32\td22, s14\n \tadds\tr7, r3, r7\n-\tstr\tr7, [sp, #52]\t@ 0x34\n-\tvldr\ts14, [ip, #-4]\n-\tvsub.f64\td27, d16, d22\n-\tvadd.f64\td22, d22, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvldr\ts14, [r7, #-4]\n-\tldr\tr7, [sp, #76]\t@ 0x4c\n-\tvstmia\tr0!, {s12}\n-\tstr\tr0, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #88]\t@ 0x58\n+\tvsub.f64\td11, d6, d5\n+\tvadd.f64\td5, d5, d6\n+\tvldr\ts12, [ip, #-4]\n+\tvcvt.f64.f32\td6, s12\n+\tvmul.f64\td11, d11, d13\n+\tvadd.f64\td3, d6, d1\n+\tvsub.f64\td6, d1, d6\n+\tvldr\ts2, [r7, #-4]\n+\tvstmia\tr0!, {s14}\n+\tldr\tr7, [sp, #136]\t@ 0x88\n+\tvcvt.f64.f32\td1, s2\n+\tvadd.f64\td7, d4, d3\n+\tvsub.f64\td3, d3, d4\n+\tvsub.f64\td4, d6, d11\n+\tvadd.f64\td6, d11, d6\n+\tstr\tr0, [sp, #56]\t@ 0x38\n+\tldr\tr0, [sp, #8]\n \tadd.w\tlr, r2, r7\n-\tvsub.f64\td25, d26, d16\n-\tvadd.f64\td16, d16, d26\n-\tldr\tr0, [sp, #4]\n-\tadds\tr7, r3, r7\n-\tvmov.f64\td4, d25\n-\tvfma.f64\td25, d18, d27\n-\tvfma.f64\td4, d27, d20\n-\tvcvt.f32.f64\ts13, d25\n-\tvadd.f64\td25, d17, d16\n-\tvsub.f64\td16, d16, d17\n+\tvadd.f64\td11, d1, d10\n+\tvsub.f64\td1, d10, d1\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts6, d3\n \tvcvt.f32.f64\ts8, d4\n-\tvldr\ts9, [lr, #-4]\n-\tvcvt.f32.f64\ts7, d25\n-\tvcvt.f32.f64\ts10, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvcvt.f64.f32\td26, s9\n-\tvstmia\tr0!, {s7}\n-\tvsub.f64\td17, d24, d16\n-\tvadd.f64\td16, d16, d24\n-\tstr\tr0, [sp, #4]\n-\tldr\tr0, [sp, #8]\n-\tvstr\ts10, [lr, #-4]\n-\tvmov.f64\td24, d17\n-\tvfma.f64\td17, d20, d23\n-\tvfma.f64\td24, d18, d23\n-\tvldr\ts10, [r7, #-4]\n+\tadds\tr7, r3, r7\n+\tvcvt.f32.f64\ts12, d6\n+\tvadd.f64\td10, d5, d11\n+\tvsub.f64\td11, d11, d5\n+\tvadd.f64\td5, d1, d9\n+\tvsub.f64\td1, d1, d9\n+\tvldr\ts18, [r7, #-4]\n+\tvcvt.f32.f64\ts15, d11\n+\tvcvt.f32.f64\ts20, d10\n+\tvldr\ts22, [lr, #-4]\n+\tvcvt.f32.f64\ts10, d5\n+\tvstmia\tr0!, {s14}\n+\tvcvt.f64.f32\td9, s18\n+\tstr\tr0, [sp, #8]\n+\tvcvt.f32.f64\ts2, d1\n+\tldr\tr0, [sp, #16]\n+\tvcvt.f64.f32\td11, s22\n+\tvstr\ts6, [lr, #-4]\n \tvstr\ts8, [r4, #-4]\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tvcvt.f64.f32\td25, s10\n-\tvcvt.f32.f64\ts12, d17\n-\tvadd.f64\td17, d22, d16\n-\tvsub.f64\td16, d16, d22\n-\tvcvt.f32.f64\ts6, d24\n-\tvcvt.f32.f64\ts5, d17\n-\tvcvt.f32.f64\ts14, d16\n-\tvstmia\tr0!, {s5}\n-\tvstr\ts14, [r7, #-4]\n+\tldr\tr4, [sp, #156]\t@ 0x9c\n+\tvstmia\tr0!, {s20}\n+\tvstr\ts15, [r7, #-4]\n \tadds\tr7, r2, r4\n-\tvstr\ts6, [r5, #-4]\n+\tvstr\ts10, [r5, #-4]\n \tadds\tr4, r3, r4\n-\tldr\tr5, [sp, #80]\t@ 0x50\n-\tstr\tr0, [sp, #8]\n-\tadd.w\tlr, r2, r5\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tstr\tr4, [sp, #60]\t@ 0x3c\n-\tvldr\ts14, [lr, #-4]\n-\tvldr\ts10, [r0]\n-\tvcvt.f64.f32\td16, s14\n+\tldr\tr5, [sp, #144]\t@ 0x90\n \tvldr\ts14, [r7, #-4]\n-\tvcvt.f64.f32\td22, s10\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts14, [r4, #-4]\n-\tvsub.f64\td24, d21, d16\n-\tvadd.f64\td16, d16, d21\n+\tadd.w\tlr, r2, r5\n+\tstr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tvcvt.f64.f32\td7, s14\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tvldr\ts10, [lr, #-4]\n+\tvldr\ts6, [r0]\n+\tvcvt.f64.f32\td5, s10\n+\tvsub.f64\td4, d11, d7\n+\tvadd.f64\td7, d7, d11\n+\tvldr\ts22, [r4, #-4]\n \tadds\tr4, r3, r5\n-\tvsub.f64\td23, d26, d17\n-\tvadd.f64\td17, d17, d26\n-\tvmov.f64\td3, d24\n-\tvadd.f64\td4, d17, d16\n-\tvsub.f64\td16, d16, d17\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts14, [r4, #-4]\n-\tvstmia\tr0!, {s11}\n-\tstr\tr0, [sp, #40]\t@ 0x28\n-\tvcvt.f32.f64\ts10, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvsub.f64\td21, d25, d17\n-\tvadd.f64\td17, d17, d25\n-\tldr\tr0, [sp, #28]\n-\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f64.f32\td3, s6\n+\tvadd.f64\td10, d5, d0\n+\tvcvt.f64.f32\td11, s22\n+\tvsub.f64\td5, d0, d5\n+\tvmul.f64\td4, d4, d13\n+\tvadd.f64\td0, d7, d10\n+\tvsub.f64\td7, d10, d7\n+\tvsub.f64\td10, d9, d11\n+\tvadd.f64\td9, d11, d9\n+\tvcvt.f32.f64\ts15, d7\n+\tvcvt.f32.f64\ts0, d0\n+\tvmul.f64\td10, d10, d13\n+\tvsub.f64\td11, d5, d10\n+\tvadd.f64\td10, d10, d5\n+\tvldr\ts10, [r4, #-4]\n+\tvstmia\tr0!, {s4}\n+\tstr\tr0, [sp, #64]\t@ 0x40\n+\tvcvt.f64.f32\td5, s10\n+\tldr\tr0, [sp, #40]\t@ 0x28\n \tldr\tr5, [sp, #0]\n+\tvcvt.f32.f64\ts22, d11\n \tadd.w\tr8, r2, r0\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tvfma.f64\td3, d20, d21\n-\tvfma.f64\td24, d18, d21\n-\tvsub.f64\td21, d22, d16\n-\tvadd.f64\td16, d16, d22\n-\tvldr\ts11, [r8, #-4]\n-\tvstmia\tr5!, {s8}\n+\tvcvt.f32.f64\ts20, d10\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tvadd.f64\td12, d5, d3\n+\tvsub.f64\td5, d3, d5\n+\tvldr\ts14, [r8, #-4]\n+\tvstmia\tr5!, {s0}\n+\tvstr\ts15, [lr, #-4]\n+\tvadd.f64\td3, d5, d4\n+\tvadd.f64\td14, d9, d12\n+\tvsub.f64\td12, d12, d9\n+\tvstr\ts22, [ip, #-4]\n+\tvsub.f64\td5, d5, d4\n+\tvstr\ts20, [r8, #-4]\n+\tvldr\ts8, [r0]\n+\tvcvt.f64.f32\td7, s14\n \tstr\tr5, [sp, #0]\n-\tvmov.f64\td22, d21\n-\tvfma.f64\td21, d20, d23\n-\tvfma.f64\td22, d18, d23\n-\tvadd.f64\td23, d17, d16\n-\tvsub.f64\td16, d16, d17\n-\tldr\tr5, [sp, #28]\n \tvcvt.f32.f64\ts6, d3\n-\tvcvt.f32.f64\ts9, d24\n-\tvstr\ts10, [lr, #-4]\n-\tvcvt.f32.f64\ts7, d23\n-\tvcvt.f32.f64\ts5, d16\n-\tvcvt.f64.f32\td16, s11\n-\tvstr\ts6, [ip, #-4]\n-\tvstr\ts9, [r8, #-4]\n+\tldr\tr5, [sp, #40]\t@ 0x28\n+\tvcvt.f32.f64\ts28, d14\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f32.f64\ts24, d12\n \tadd.w\tr8, r3, r5\n-\tvcvt.f32.f64\ts4, d22\n-\tldr\tr5, [sp, #52]\t@ 0x34\n-\tvldr\ts10, [r0]\n-\tvcvt.f32.f64\ts14, d21\n-\tvldr\ts11, [r8, #-4]\n-\tvstmia\tr9!, {s7}\n-\tvcvt.f64.f32\td17, s10\n-\tvstr\ts5, [r4, #-4]\n-\tvstr\ts4, [r5, #-4]\n-\tldr\tr4, [sp, #96]\t@ 0x60\n-\tldr\tr5, [sp, #104]\t@ 0x68\n+\tldr\tr5, [sp, #88]\t@ 0x58\n+\tvcvt.f32.f64\ts10, d5\n+\tvadd.f64\td0, d4, d7\n+\tvsub.f64\td4, d4, d7\n+\tvldr\ts14, [r8, #-4]\n+\tvstmia\tr9!, {s28}\n+\tvstr\ts24, [r4, #-4]\n+\tvstr\ts6, [r5, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tldr\tr4, [sp, #160]\t@ 0xa0\n+\tldr\tr5, [sp, #164]\t@ 0xa4\n \tadd.w\tip, r2, r4\n-\tvsub.f64\td22, d17, d16\n+\tvstr\ts10, [r8, #-4]\n \tadd\tr2, r5\n-\tvadd.f64\td17, d17, d16\n-\tvcvt.f64.f32\td16, s11\n-\tvstr\ts14, [r8, #-4]\n-\tvldr\ts11, [ip, #-4]\n-\tvldr\ts14, [r2, #-4]\n-\tvstmia\tr0!, {s15}\n-\tvsub.f64\td21, d19, d16\n-\tvcvt.f64.f32\td23, s11\n-\tvadd.f64\td16, d16, d19\n-\tvcvt.f64.f32\td19, s14\n-\tvstr\ts13, [ip, #-4]\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td25, d21\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tvsub.f64\td24, d23, d19\n-\tvadd.f64\td19, d19, d23\n-\tvmov.f64\td23, d22\n-\tvadd.f64\td7, d19, d17\n-\tvsub.f64\td17, d17, d19\n-\tvfma.f64\td21, d20, d24\n-\tvfma.f64\td25, d18, d24\n-\tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d17\n-\tvstmia\tfp!, {s14}\n-\tvstr\ts15, [r7, #-4]\n+\tvadd.f64\td3, d7, d8\n+\tvsub.f64\td7, d8, d7\n+\tvldr\ts4, [ip, #-4]\n+\tvldr\ts13, [r2, #-4]\n+\tvstmia\tr0!, {s5}\n+\tvstr\ts12, [ip, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td6, s13\n+\tstr\tr0, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #80]\t@ 0x50\n+\tvsub.f64\td5, d2, d6\n+\tvadd.f64\td6, d6, d2\n+\tvadd.f64\td2, d6, d0\n+\tvsub.f64\td6, d0, d6\n+\tvmul.f64\td5, d5, d13\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts12, d6\n+\tvadd.f64\td0, d7, d5\n+\tvsub.f64\td7, d7, d5\n+\tvstmia\tfp!, {s4}\n+\tvstr\ts12, [r7, #-4]\n \tadds\tr7, r3, r4\n \tadd\tr3, r5\n-\tvcvt.f32.f64\ts13, d21\n-\tvcvt.f32.f64\ts11, d25\n-\tvldr\ts14, [r7, #-4]\n+\tvcvt.f32.f64\ts3, d0\n+\tvcvt.f32.f64\ts14, d7\n+\tvldr\ts4, [r7, #-4]\n \tvldr\ts10, [r3, #-4]\n-\tvcvt.f64.f32\td7, s14\n-\tvcvt.f64.f32\td17, s10\n-\tvsub.f64\td24, d7, d17\n-\tvadd.f64\td17, d17, d7\n-\tvfma.f64\td23, d20, d24\n-\tvfma.f64\td22, d18, d24\n-\tvadd.f64\td21, d17, d16\n-\tvsub.f64\td16, d16, d17\n-\tvcvt.f32.f64\ts10, d21\n-\tvcvt.f32.f64\ts15, d16\n-\tvcvt.f32.f64\ts14, d23\n-\tvstr\ts14, [r0, #-4]\n-\tvcvt.f32.f64\ts14, d22\n-\tvstr\ts14, [r2, #-4]\n-\tldr\tr2, [sp, #12]\n-\tvstmia\tr2!, {s10}\n-\tstr\tr2, [sp, #12]\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tvstr\ts15, [r2, #-4]\n-\tvstr\ts12, [r7, #-4]\n-\tldr\tr7, [sp, #56]\t@ 0x38\n-\tvstr\ts11, [r7, #-4]\n-\tvstr\ts13, [r3, #-4]\n-\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td5, s10\n+\tvsub.f64\td6, d2, d5\n+\tvadd.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d13\n+\tvadd.f64\td2, d5, d3\n+\tvsub.f64\td3, d3, d5\n+\tvsub.f64\td5, d4, d6\n+\tvadd.f64\td6, d6, d4\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts10, [r0, #-4]\n+\tvstr\ts12, [r2, #-4]\n+\tldr\tr2, [sp, #24]\n+\tldr\tr4, [sp, #104]\t@ 0x68\n+\tvstmia\tr2!, {s4}\n+\tvstr\ts6, [r4, #-4]\n+\tvstr\ts2, [r7, #-4]\n+\tldr\tr7, [sp, #96]\t@ 0x60\n+\tstr\tr2, [sp, #24]\n+\tvstr\ts3, [r7, #-4]\n+\tvstr\ts14, [r3, #-4]\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n \tcmp\tr1, r3\n-\tbne.w\t5060 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x790>\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tbne.w\t51ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x636>\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #172]\t@ 0xac\n \tcmp\tr2, r3\n-\tble.n\t5424 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb54>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #136]\t@ 0x88\n-\tldr\tr2, [sp, #156]\t@ 0x9c\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tldr\tr2, [sp, #180]\t@ 0xb4\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n \tcmp\tr3, r2\n-\tbne.w\t4e90 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x5c0>\n-\tldrd\tr3, r1, [sp, #260]\t@ 0x104\n-\tldrd\tip, r0, [sp, #240]\t@ 0xf0\n+\tbne.w\t5018 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x460>\n+\tldrd\tr3, r1, [sp, #232]\t@ 0xe8\n+\tldrd\tr5, r9, [sp, #224]\t@ 0xe0\n \tsubs\tr3, #1\n-\tldr\tr5, [sp, #216]\t@ 0xd8\n-\tadds\tr4, r3, #1\n-\tldr.w\tsl, [sp, #232]\t@ 0xe8\n-\tadd\tr1, r0\n-\tldrd\tfp, r6, [sp, #248]\t@ 0xf8\n-\tldrd\tr8, r7, [sp, #268]\t@ 0x10c\n-\tbne.w\t4e74 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x5a4>\n-\tldrd\tlr, r4, [sp, #208]\t@ 0xd0\n+\tldr\tr7, [sp, #208]\t@ 0xd0\n+\tadds\tr2, r3, #1\n+\tldr\tr6, [sp, #216]\t@ 0xd8\n+\tadd\tr1, r9\n+\tldrd\tr8, sl, [sp, #240]\t@ 0xf0\n+\tbne.w\t5002 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x44a>\n+\tldr\tr4, [sp, #204]\t@ 0xcc\n \tsubs\tr4, #1\n-\tadd\tr5, ip\n-\tsub.w\tr8, r8, ip\n-\tadd\tr7, ip\n-\tadds\tr2, r4, #1\n-\tbne.w\t4e50 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x580>\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tldr\tr2, [sp, #204]\t@ 0xcc\n-\tcmp\tr3, r2\n-\tbeq.w\t6454 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b84>\n-\tldr\tr4, [sp, #144]\t@ 0x90\n-\tlsls\tr2, r6, #1\n-\tsub.w\tr3, lr, r4\n-\tcmp\tr4, #0\n-\tblt.w\t8140 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3870>\n-\tsubs\tr1, r3, r4\n-\tcmp\tr4, r3\n-\tudiv\tr1, r1, r4\n-\tstr\tr1, [sp, #200]\t@ 0xc8\n-\tbgt.w\t812a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x385a>\n+\tadd\tr7, r5\n+\tsub.w\tr8, r8, r5\n+\tadd\tsl, r5\n+\tadds\tr3, r4, #1\n+\tbne.w\t4fda <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x422>\n+\tldr.w\tr8, [sp, #200]\t@ 0xc8\n+\tldr\tr3, [sp, #388]\t@ 0x184\n+\tcmp\tr3, r8\n+\tbeq.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tldr\tr7, [sp, #360]\t@ 0x168\n+\tlsls\tr5, r3, #1\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tcmp\tr7, #0\n+\tsub.w\tr4, r3, r7\n+\tblt.w\t846e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38b6>\n+\tmov\tr1, r7\n+\tsubs\tr0, r4, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr7, r4\n+\tstr\tr0, [sp, #436]\t@ 0x1b4\n+\tbgt.w\t845e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38a6>\n \tmovs\tr3, #24\n-\tldr\tr0, [sp, #184]\t@ 0xb8\n-\tmov.w\tr7, sl, lsl #2\n-\tmul.w\tr1, r3, r2\n-\tlsls\tr3, r2, #3\n-\tlsls\tr2, r2, #4\n-\tstr\tr3, [sp, #244]\t@ 0xf4\n-\tstr\tr2, [sp, #248]\t@ 0xf8\n-\tmov\tr2, r3\n-\tadds\tr3, r0, r3\n-\tstr\tr1, [sp, #252]\t@ 0xfc\n-\tadds\tr4, r3, r2\n-\tadd.w\tr2, r1, #8\n-\tadd.w\tr9, r0, r2\n-\tldr\tr1, [sp, #188]\t@ 0xbc\n-\tnegs\tr2, r7\n-\tstr\tr2, [sp, #240]\t@ 0xf0\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tmov\tr8, r4\n-\tstr\tr4, [sp, #232]\t@ 0xe8\n-\tmov\tlr, r2\n-\tsubs\tr5, r1, r2\n-\tsub.w\tr4, r2, fp\n-\tstr.w\tr9, [sp, #212]\t@ 0xd4\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tldr.w\tr9, [sp, #124]\t@ 0x7c\n-\tstr.w\tr8, [sp, #208]\t@ 0xd0\n-\tmov\tr8, fp\n-\tadds\tr2, #1\n-\tstr.w\tlr, [sp, #168]\t@ 0xa8\n-\tstr\tr2, [sp, #92]\t@ 0x5c\n-\tldr\tr2, [sp, #212]\t@ 0xd4\n-\tcmp.w\tip, #0\n-\tvldr\td22, [r3, #8]\n-\tvldr\td25, [r3]\n-\tldr\tr3, [sp, #208]\t@ 0xd0\n-\tvldr\td24, [r2]\n-\tvmul.f64\td22, d0, d22\n-\tvldr\td27, [r2, #-8]\n-\tvldr\td23, [r3, #8]\n-\tvmul.f64\td24, d0, d24\n-\tvldr\td26, [r3]\n-\tvmul.f64\td23, d0, d23\n-\tblt.w\t810c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x383c>\n-\tldr\tr3, [sp, #188]\t@ 0xbc\n-\tudiv\tr6, r5, ip\n-\tldr\tr2, [sp, #168]\t@ 0xa8\n+\tlsls\tr0, r6, #2\n+\tldr\tr4, [sp, #404]\t@ 0x194\n+\tlsls\tr7, r5, #3\n+\tmov\tr9, r7\n+\tstr.w\tr8, [sp, #484]\t@ 0x1e4\n+\tmul.w\tr6, r3, r5\n+\tlsls\tr3, r5, #4\n+\tstr\tr3, [sp, #468]\t@ 0x1d4\n+\tadds\tr1, r4, r7\n+\tadd.w\tr3, r6, #8\n+\tmov\tr5, r0\n+\tadd\tr3, r4\n+\tnegs\tr0, r0\n+\tldr\tr4, [sp, #408]\t@ 0x198\n+\tadds\tr2, r1, r7\n+\tstr\tr0, [sp, #472]\t@ 0x1d8\n+\tmov\tr7, r2\n+\tldr\tr0, [sp, #360]\t@ 0x168\n+\tstr\tr6, [sp, #480]\t@ 0x1e0\n+\tmov\tr6, r3\n+\tsubs\tr4, r4, r0\n+\tstr\tr4, [sp, #416]\t@ 0x1a0\n+\tldr\tr4, [sp, #340]\t@ 0x154\n+\tmov\tfp, r0\n+\tstr\tr2, [sp, #460]\t@ 0x1cc\n+\tsub.w\tsl, r0, r4\n+\tldr\tr0, [sp, #344]\t@ 0x158\n+\tstr.w\tsl, [sp, #420]\t@ 0x1a4\n+\tadds\tr0, #1\n+\tstr\tr0, [sp, #328]\t@ 0x148\n+\tldr\tr0, [sp, #620]\t@ 0x26c\n+\tstr.w\tfp, [sp, #412]\t@ 0x19c\n+\tadds\tr0, #1\n+\tstr\tr0, [sp, #300]\t@ 0x12c\n+\tvldr\td5, [r7]\n+\tvldr\td7, [r7, #8]\n+\tvldr\td6, [r6]\n+\tvmov.f64\td8, d5\n+\tvldr\td5, [r6, #-8]\n+\tvldr\td11, [r1, #8]\n+\tldr\tr3, [sp, #400]\t@ 0x190\n+\tvstr\td5, [sp, #288]\t@ 0x120\n+\tvldr\td5, [sp, #392]\t@ 0x188\n+\tcmp\tr3, #0\n+\tvldr\td15, [r1]\n+\tvmul.f64\td7, d5, d7\n+\tvmul.f64\td11, d5, d11\n+\tvstr\td7, [sp, #320]\t@ 0x140\n+\tvmul.f64\td7, d5, d6\n+\tvstr\td7, [sp, #16]\n+\tblt.w\t843a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3882>\n+\tmov\tr1, r3\n+\tldr\tr0, [sp, #416]\t@ 0x1a0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tmov\tfp, r0\n+\tldrd\tr3, r2, [sp, #408]\t@ 0x198\n \tcmp\tr3, r2\n-\tblt.w\t5cb0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13e0>\n-\tsub.w\tr3, r8, r3\n-\tldr\tr0, [sp, #168]\t@ 0xa8\n-\tadd.w\tlr, r3, r5\n-\tldr.w\tfp, [sp, #172]\t@ 0xac\n-\tmov\tr3, r8\n-\tldr.w\tsl, [sp, #120]\t@ 0x78\n-\tstr.w\tlr, [sp, #216]\t@ 0xd8\n-\tstrd\tr5, r4, [sp, #260]\t@ 0x104\n-\tcmp\tr7, #0\n-\tblt.w\t80fc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x382c>\n-\tldr\tr2, [sp, #216]\t@ 0xd8\n-\tcmp\tr3, r0\n-\tudiv\tr2, r2, r7\n-\tblt.w\t5c96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13c6>\n-\tldr\tr5, [sp, #132]\t@ 0x84\n+\tblt.w\t5f78 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13c0>\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tsubs\tr4, r2, r3\n+\tldr\tr3, [sp, #416]\t@ 0x1a0\n+\tvmov.f64\td14, d8\n+\tstr.w\tfp, [sp, #464]\t@ 0x1d0\n+\tadds\tr3, r4, r3\n+\tldr\tr4, [sp, #412]\t@ 0x19c\n+\tstr\tr3, [sp, #432]\t@ 0x1b0\n+\tldr\tr3, [sp, #420]\t@ 0x1a4\n+\tstr\tr3, [sp, #444]\t@ 0x1bc\n+\tstr.w\tr9, [sp, #488]\t@ 0x1e8\n \tcmp\tr5, #0\n-\tble.w\t5c96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13c6>\n-\tldr\tr1, [sp, #16]\n-\tadds\tr5, #1\n-\tstrd\tr6, ip, [sp, #268]\t@ 0x10c\n-\tadd\tr1, r0\n-\tstr\tr5, [sp, #112]\t@ 0x70\n-\tstrd\tr0, r3, [sp, #276]\t@ 0x114\n-\tstr\tr7, [sp, #156]\t@ 0x9c\n-\tstr\tr4, [sp, #284]\t@ 0x11c\n+\tblt.w\t8424 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x386c>\n+\tldr\tr0, [sp, #432]\t@ 0x1b0\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tblt.w\t5f56 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x139e>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tcmp\tr3, #0\n+\tble.w\t5f56 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x139e>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr.w\tip, [sp, #380]\t@ 0x17c\n+\tldrd\tsl, r9, [sp, #332]\t@ 0x14c\n+\tadds\tr1, r3, r4\n+\tstrd\tr7, r6, [sp, #492]\t@ 0x1ec\n+\tstr\tr4, [sp, #500]\t@ 0x1f4\n+\tstr\tr5, [sp, #368]\t@ 0x170\n+\tmov\tlr, sl\n+\tmov\tfp, r9\n \tmovs\tr3, #1\n-\tstr\tr1, [sp, #96]\t@ 0x60\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tstr\tr2, [sp, #128]\t@ 0x80\n-\tstr\tr1, [sp, #136]\t@ 0x88\n-\tstrd\tfp, sl, [sp, #68]\t@ 0x44\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tadds\tr5, r3, r2\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, r5\n-\tble.n\t5582 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xcb2>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadds\tr6, r3, r5\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, r6\n-\tble.n\t5590 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xcc0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr6, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr2, [sp, #16]\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #0]\n+\tstr\tr1, [sp, #304]\t@ 0x130\n+\tstr\tr3, [sp, #312]\t@ 0x138\n+\tstrd\tr2, r1, [sp, #348]\t@ 0x15c\n+\tstr.w\tip, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tldr\tr2, [sp, #304]\t@ 0x130\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tadds\tr7, r3, r2\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr3, r7\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr7, r7, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadd.w\tip, r3, r7\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr3, ip\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tip, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadd\tr3, ip\n+\tstr\tr3, [sp, #8]\n \tcmp\tr2, r3\n-\tble.n\t55a2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xcd2>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #0]\n-\tldrd\tr2, r3, [sp, #96]\t@ 0x60\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #8]\n+\tldrd\tr2, r3, [sp, #304]\t@ 0x130\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r3\n-\tble.n\t55b2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xce2>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadd.w\tsl, r2, r3\n-\tldr\tr2, [sp, #16]\n-\tcmp\tr2, sl\n-\tble.n\t55c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xcf2>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tsl, r2\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadd.w\tr0, r2, sl\n-\tldr\tr2, [sp, #16]\n-\tcmp\tr2, r0\n-\tble.n\t55d2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd02>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr0, r2\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tldr\tr1, [sp, #16]\n-\tadd\tr2, r0\n-\tstr\tr2, [sp, #4]\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tadds\tr4, r2, r3\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr2, r4\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r2\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tadds\tr5, r2, r4\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr2, r5\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r2\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tadd\tr2, r5\n+\tstr\tr2, [sp, #24]\n \tcmp\tr1, r2\n-\tble.n\t55e4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd14>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tldr\tr1, [sp, #16]\n+\tittt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r1\n+\tstrgt\tr2, [sp, #24]\n+\tldr\tr2, [sp, #308]\t@ 0x134\n+\tldr\tr1, [sp, #152]\t@ 0x98\n \tadd\tr2, r3\n \tcmp\tr1, r2\n-\tble.n\t55f2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd22>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd.w\tfp, r1, r2\n-\tldr\tr1, [sp, #16]\n-\tcmp\tr1, fp\n-\tble.n\t5602 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd32>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tfp, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd.w\tr8, r1, fp\n-\tldr\tr1, [sp, #16]\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tadds\tr0, r1, r2\n+\tstr\tr0, [sp, #0]\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r0\n+\tittt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r1\n+\tstrgt\tr0, [sp, #0]\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tldr\tr0, [sp, #0]\n+\tadd.w\tr8, r1, r0\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tldr\tr0, [sp, #152]\t@ 0x98\n \tcmp\tr1, r8\n-\tble.n\t5612 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd42>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr8, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd.w\tr4, r1, r8\n-\tldr\tr1, [sp, #16]\n-\tstr\tr4, [sp, #8]\n-\tcmp\tr1, r4\n-\tble.n\t5626 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd56>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #8]\n-\tldr\tr1, [sp, #100]\t@ 0x64\n-\tadds\tr4, r1, r2\n-\tldr\tr1, [sp, #16]\n-\tcmp\tr1, r4\n-\tble.n\t5634 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd64>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr4, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd.w\tip, r1, r4\n-\tldr\tr1, [sp, #16]\n-\tcmp\tr1, ip\n-\tble.n\t5644 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd74>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tip, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd.w\tlr, r1, ip\n-\tldr\tr1, [sp, #16]\n-\tcmp\tr1, lr\n-\tble.n\t5654 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd84>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tlr, r1\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tldr\tr7, [sp, #16]\n-\tadd\tr1, lr\n-\tstr\tr1, [sp, #12]\n-\tcmp\tr7, r1\n-\tble.n\t5666 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd96>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr1, r7\n-\tstr\tr1, [sp, #12]\n-\tldr\tr1, [sp, #404]\t@ 0x194\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr8, r1\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tadd.w\tr6, r1, r8\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tstr\tr6, [sp, #28]\n+\tcmp\tr1, r6\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r1\n+\tldr\tr1, [sp, #308]\t@ 0x134\n+\tit\tgt\n+\tstrgt\tr6, [sp, #28]\n+\tadds\tr6, r1, r2\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r6\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r1\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tadd.w\tr9, r1, r6\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r9\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr9, r1\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tadd.w\tsl, r1, r9\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tcmp\tr1, sl\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tsl, r1\n+\tldr\tr1, [sp, #284]\t@ 0x11c\n+\tadd\tr1, sl\n+\tstr\tr1, [sp, #32]\n+\tcmp\tr0, r1\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r0\n+\tstrgt\tr1, [sp, #32]\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n \tcmp\tr1, #0\n-\tble.w\t5c50 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1380>\n+\tble.w\t5f14 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x135c>\n+\tldr\tr1, [sp, #8]\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tldr\tr0, [sp, #24]\n+\tsubs\tr2, #1\n+\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n+\tstr\tr2, [sp, #8]\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tldr\tr1, [sp, #0]\n+\tldr\tr2, [sp, #0]\n \tsubs\tr3, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #4]\n-\tadd.w\tr7, sl, #1073741824\t@ 0x40000000\n-\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tsubs\tr1, #1\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tadd.w\tr9, r9, #1073741824\t@ 0x40000000\n+\tsubs\tr0, #1\n+\tstr\tr0, [sp, #24]\n+\tadd.w\tr0, r2, #1073741824\t@ 0x40000000\n+\tadd.w\tr2, r8, #1073741824\t@ 0x40000000\n \tsubs\tr2, #1\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #4]\n-\tadd.w\tr3, r8, #1073741824\t@ 0x40000000\n-\tlsls\tr2, r2, #2\n-\tsubs\tr3, #1\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #8]\n-\tsubs\tr7, #1\n-\tstr\tr2, [sp, #8]\n+\tlsls\tr1, r1, #2\n+\tstr\tr2, [sp, #0]\n \tsubs\tr0, #1\n-\tadd.w\tr8, r3, #1073741824\t@ 0x40000000\n-\tldr\tr3, [sp, #12]\n-\tadd.w\tlr, lr, #1073741824\t@ 0x40000000\n-\tadd.w\tip, ip, #1073741824\t@ 0x40000000\n-\tadd.w\tsl, r3, #1073741824\t@ 0x40000000\n-\tldr\tr3, [sp, #0]\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tlsls\tr2, r3, #2\n-\tldr\tr3, [sp, #4]\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tlsls\tr2, r0, #2\n-\tstr\tr2, [sp, #32]\n-\tlsls\tr2, r7, #2\n-\tstr\tr2, [sp, #20]\n-\tlsls\tr2, r3, #2\n+\tldr\tr2, [sp, #28]\n+\tadd.w\tr7, r7, #1073741824\t@ 0x40000000\n+\tstr\tr1, [sp, #144]\t@ 0x90\n+\tlsls\tr1, r3, #2\n \tldr\tr3, [sp, #24]\n-\tsubs\tr1, #1\n-\tadd.w\tfp, fp, #1073741824\t@ 0x40000000\n-\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tadd.w\tr8, r2, #1073741824\t@ 0x40000000\n+\tldr\tr2, [sp, #32]\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tstr\tr1, [sp, #128]\t@ 0x80\n+\tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n+\tlsls\tr1, r3, #2\n+\tldr\tr3, [sp, #0]\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tstr\tr1, [sp, #156]\t@ 0x9c\n+\tsubs\tr2, #1\n+\tstr\tr2, [sp, #28]\n+\tlsls\tr1, r0, #2\n+\tstr\tr1, [sp, #112]\t@ 0x70\n+\tlsls\tr1, r3, #2\n+\tldr\tr3, [sp, #28]\n+\tadd.w\tsl, sl, #1073741824\t@ 0x40000000\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [sp, #8]\n+\tadd.w\tip, ip, #1073741824\t@ 0x40000000\n+\tlsls\tr0, r3, #2\n+\tldr\tr3, [sp, #304]\t@ 0x130\n+\tsubs\tr7, #1\n \tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #4]\n-\tmov.w\tr3, r8, lsl #2\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tmov.w\tr3, lr, lsl #2\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tmov.w\tr3, ip, lsl #2\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #96]\t@ 0x60\n-\tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n-\tlsls\tr1, r1, #2\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tsubs\tr4, #1\n+\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tsubs\tr6, #1\n-\tsubs\tr3, #1\n \tsubs\tr5, #1\n-\tsubs\tr4, #1\n-\tmov.w\tsl, sl, lsl #2\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tmov.w\tfp, fp, lsl #2\n-\tldrd\tr1, r7, [sp, #68]\t@ 0x44\n-\tmov.w\tr8, r3, lsl #2\n-\tstrd\tr8, fp, [sp, #60]\t@ 0x3c\n-\tmov\tfp, sl\n+\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tstr\tr1, [sp, #120]\t@ 0x78\n+\tmov.w\tr1, r8, lsl #2\n+\tstr\tr1, [sp, #136]\t@ 0x88\n+\tmov.w\tr1, r9, lsl #2\n+\tstr\tr1, [sp, #160]\t@ 0xa0\n+\tldr\tr1, [sp, #48]\t@ 0x30\n+\tlsls\tr7, r7, #2\n+\tmov.w\tr8, sl, lsl #2\n+\tlsls\tr4, r4, #2\n+\tsubs\tr3, #1\n+\tmov.w\tip, ip, lsl #2\n \tlsls\tr6, r6, #2\n \tlsls\tr5, r5, #2\n-\tlsls\tr4, r4, #2\n-\tmovs\tr3, #1\n-\tstr\tr6, [sp, #56]\t@ 0x38\n-\tstr\tr5, [sp, #36]\t@ 0x24\n-\tstr\tr2, [sp, #28]\n-\tstr\tr3, [sp, #0]\n-\tstr\tr4, [sp, #12]\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tadds\tr0, r7, r4\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tadd.w\tip, r7, r2\n-\tldr\tr3, [sp, #0]\n-\tadds\tr5, r4, r1\n+\tlsls\tr2, r2, #2\n+\tvldr\td7, [sp, #320]\t@ 0x140\n \tstr\tr5, [sp, #40]\t@ 0x28\n-\tvldr\ts15, [r0]\n-\tadd.w\tr0, r9, r2\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tadd.w\tr2, r9, r4\n-\tvldr\ts12, [ip]\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r0]\n-\tstr\tr2, [sp, #72]\t@ 0x48\n+\tmov\tr5, r8\n+\tstrd\tr2, r6, [sp, #28]\n+\tmov\tr8, fp\n+\tstr.w\tip, [sp, #172]\t@ 0xac\n+\tmov\tr6, r4\n+\tmov\tip, r7\n+\tmov\tr7, r1\n+\tlsls\tr3, r3, #2\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tmovs\tr3, #1\n+\tstr\tr3, [sp, #24]\n+\tvstr\td11, [sp]\n+\tvstr\td7, [sp, #8]\n+\tldr\tr3, [sp, #24]\n+\tadd.w\tr2, lr, ip\n+\tldr\tr0, [sp, #164]\t@ 0xa4\n \tadds\tr3, #1\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tadd.w\tfp, r8, r0\n+\tvldr\ts8, [r2]\n+\tadd.w\tsl, lr, r0\n+\tadd.w\tr1, lr, r3\n+\tldr\tr4, [sp, #172]\t@ 0xac\n+\tstr\tr1, [sp, #180]\t@ 0xb4\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts10, [fp]\n+\tvldr\ts12, [r1]\n+\tadd.w\tr1, r8, r4\n+\tstr\tr1, [sp, #192]\t@ 0xc0\n+\tvcvt.f64.f32\td5, s10\n+\tstr\tr2, [sp, #104]\t@ 0x68\n \tvcvt.f64.f32\td6, s12\n-\tstr\tr3, [sp, #0]\n-\tvcvt.f64.f32\td17, s15\n-\tvldr\ts15, [r2]\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr5, [sp, #56]\t@ 0x38\n-\tadd.w\tr3, r9, r2\n-\tvsub.f64\td31, d6, d16\n-\tadd.w\tsl, r9, r5\n-\tvadd.f64\td6, d6, d16\n-\tvcvt.f64.f32\td16, s15\n-\tadds\tr4, r7, r2\n-\tvldr\ts15, [r3]\n-\tadd.w\tr8, r7, r5\n-\tadds\tr6, r2, r1\n-\tldr\tr2, [sp, #8]\n-\tvldr\ts11, [r4]\n-\tadd\tr5, r1\n-\tvcvt.f64.f32\td28, s15\n-\tvldr\ts15, [sl]\n-\tvsub.f64\td29, d17, d16\n-\tvadd.f64\td17, d17, d16\n-\tvldr\ts10, [r8]\n-\tvcvt.f64.f32\td19, s15\n-\tstr\tr6, [sp, #60]\t@ 0x3c\n-\tldr\tr6, [sp, #52]\t@ 0x34\n-\tstr\tr5, [sp, #56]\t@ 0x38\n-\tadd.w\tlr, r9, r6\n-\tvsub.f64\td16, d28, d19\n-\tvadd.f64\td21, d28, d19\n-\tvsub.f64\td19, d19, d28\n-\tvfma.f64\td19, d18, d31\n-\tvmov.f64\td30, d16\n-\tvfma.f64\td16, d31, d20\n-\tvfma.f64\td30, d18, d31\n-\tvadd.f64\td28, d21, d17\n-\tvsub.f64\td31, d17, d21\n-\tvsub.f64\td21, d21, d17\n-\tvcvt.f32.f64\ts15, d28\n-\tvmul.f64\td17, d31, d23\n-\tvmul.f64\td19, d24, d19\n-\tvmul.f64\td21, d21, d26\n-\tvmul.f64\td31, d27, d16\n-\tvcvt.f64.f32\td16, s11\n+\tvsub.f64\td7, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvldr\ts12, [r1]\n+\tadd.w\tr1, r8, ip\n+\tstr\tr1, [sp, #196]\t@ 0xc4\n+\tadd\tip, r7\n+\tvcvt.f64.f32\td6, s12\n+\tvmul.f64\td7, d7, d13\n+\tvadd.f64\td2, d5, d6\n+\tvsub.f64\td9, d5, d6\n+\tvsub.f64\td6, d6, d5\n+\tvadd.f64\td6, d6, d7\n+\tvstr\td6, [sp, #272]\t@ 0x110\n+\tvldr\ts12, [r1]\n+\tadd.w\tr1, r8, r3\n+\tmov\tr2, r1\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tadds\tr1, r3, r7\n+\tstr\tr1, [sp, #144]\t@ 0x90\n+\tvcvt.f64.f32\td6, s12\n+\tadds\tr1, r0, r7\n+\tvldr\ts10, [r2]\n+\tldr\tr2, [sp, #28]\n+\tstr\tr1, [sp, #164]\t@ 0xa4\n+\tadd.w\tr1, lr, r4\n \tvcvt.f64.f32\td5, s10\n-\tvstr\ts15, [r3]\n-\tvnmul.f64\td28, d30, d22\n-\tvmul.f64\td7, d25, d30\n-\tadds\tr3, r7, r2\n-\tadds\tr2, r7, r6\n-\tadd\tr6, r1\n-\tvsub.f64\td30, d16, d5\n-\tvadd.f64\td16, d16, d5\n-\tvmov.f64\td4, d30\n-\tvfma.f64\td30, d18, d29\n-\tvfma.f64\td4, d29, d20\n-\tvsub.f64\td29, d16, d6\n-\tvadd.f64\td6, d16, d6\n-\tvfma.f64\td17, d26, d29\n-\tvfma.f64\td21, d23, d29\n+\tmov\tr3, r1\n+\tadd.w\tr1, lr, r2\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tadd\tr4, r7\n+\tstr\tr4, [sp, #172]\t@ 0xac\n+\tadd.w\tr9, lr, r2\n+\tmov\tr4, r1\n+\tvadd.f64\td0, d6, d5\n+\tvsub.f64\td6, d6, d5\n+\tvldr\ts10, [r3]\n+\tadd.w\tr1, lr, r6\n+\tvldr\ts6, [r9]\n+\tvldr\ts7, [r4]\n+\tvmul.f64\td8, d6, d13\n+\tvldr\ts12, [sl]\n+\tstr\tr1, [sp, #204]\t@ 0xcc\n+\tvcvt.f64.f32\td5, s10\n+\tldr\tr1, [sp, #32]\n+\tvcvt.f64.f32\td10, s6\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tvcvt.f64.f32\td6, s12\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tvcvt.f64.f32\td3, s7\n+\tstr\tr4, [sp, #184]\t@ 0xb8\n+\tadds\tr4, r2, r7\n+\tadd.w\tr0, lr, r3\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tadd.w\tr0, r8, r1\n+\tvsub.f64\td1, d0, d2\n+\tmov\tr1, r0\n+\tadd.w\tr0, r8, r2\n+\tstr\tr0, [sp, #208]\t@ 0xd0\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tstr\tr4, [sp, #128]\t@ 0x80\n+\tadd.w\tr4, r8, r6\n+\tstr\tr4, [sp, #216]\t@ 0xd8\n+\tadd.w\tr4, r8, r3\n+\tstr\tr4, [sp, #72]\t@ 0x48\n+\tadds\tr4, r3, r7\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd.w\tr0, r8, r2\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvadd.f64\td3, d6, d5\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tvsub.f64\td6, d6, d5\n+\tvadd.f64\td5, d7, d9\n+\tvsub.f64\td9, d9, d7\n+\tvadd.f64\td7, d2, d0\n+\tstr\tr4, [sp, #156]\t@ 0x9c\n+\tadd.w\tr4, lr, r3\n+\tstr\tr0, [sp, #64]\t@ 0x40\n+\tadd\tr3, r7\n+\tmov\tr0, r4\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tadd.w\tr4, lr, r2\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tvcvt.f32.f64\ts14, d7\n+\tstr\tr4, [sp, #56]\t@ 0x38\n+\tadd.w\tr4, r8, r2\n+\tstr\tr4, [sp, #224]\t@ 0xe0\n+\tadds\tr4, r2, r7\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tvsub.f64\td2, d2, d0\n+\tstr\tr4, [sp, #112]\t@ 0x70\n+\tadd\tr6, r7\n+\tadd.w\tr4, lr, r2\n+\tstr\tr4, [sp, #228]\t@ 0xe4\n+\tadd.w\tr4, lr, r3\n+\tstr\tr4, [sp, #80]\t@ 0x50\n+\tadd.w\tr4, r8, r3\n+\tstr\tr4, [sp, #88]\t@ 0x58\n+\tadds\tr4, r3, r7\n+\tldr\tr3, [sp, #28]\n+\tstr\tr4, [sp, #136]\t@ 0x88\n+\tadd.w\tr4, r8, r3\n+\tadd\tr3, r7\n+\tstr\tr4, [sp, #232]\t@ 0xe8\n+\tadd.w\tr4, r8, r2\n+\tstr\tr3, [sp, #28]\n+\tstr\tr4, [sp, #236]\t@ 0xec\n+\tadds\tr4, r2, r7\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tstr\tr4, [sp, #120]\t@ 0x78\n+\tadd.w\tr4, lr, r5\n+\tstr\tr4, [sp, #240]\t@ 0xf0\n+\tadd.w\tr4, lr, r2\n+\tstr\tr4, [sp, #252]\t@ 0xfc\n+\tadd.w\tr4, lr, r3\n+\tstr\tr4, [sp, #256]\t@ 0x100\n+\tadd.w\tr4, r8, r5\n+\tstr\tr4, [sp, #244]\t@ 0xf4\n+\tadd.w\tr4, r8, r2\n+\tstr\tr4, [sp, #260]\t@ 0x104\n+\tadds\tr4, r2, r7\n+\tstr\tr4, [sp, #160]\t@ 0xa0\n+\tadd.w\tr4, r8, r3\n+\tstr\tr4, [sp, #96]\t@ 0x60\n+\tmov\tr2, r1\n+\tvstr\ts14, [fp]\n+\tadd\tr3, r7\n+\tvldr\ts15, [r1]\n+\tadd\tr5, r7\n+\tldr\tr1, [sp, #184]\t@ 0xb8\n+\tvldr\td11, [sp, #288]\t@ 0x120\n+\tvcvt.f64.f32\td12, s15\n+\tvsub.f64\td7, d3, d4\n+\tvadd.f64\td3, d3, d4\n+\tvsub.f64\td4, d6, d8\n+\tvadd.f64\td6, d6, d8\n+\tvldr\td8, [sp]\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr3, [sp, #32]\n+\tvcvt.f32.f64\ts6, d3\n+\tadd.w\tr4, lr, r3\n+\tadd\tr3, r7\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstr\ts6, [sl]\n+\tvmul.f64\td3, d8, d5\n+\tvmul.f64\td5, d15, d5\n+\tstr\tr4, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td5, d8, d4\n+\tldr\tr4, [sp, #216]\t@ 0xd8\n+\tvnmls.f64\td3, d15, d4\n+\tvmul.f64\td4, d14, d7\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts6, [r9]\n+\tmov\tr9, r0\n+\tvldr\td3, [sp, #8]\n+\tvmla.f64\td4, d1, d3\n+\tvmul.f64\td7, d3, d7\n+\tvldr\td3, [sp, #16]\n+\tvmla.f64\td7, d2, d14\n+\tvldr\td2, [sp, #272]\t@ 0x110\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts15, d7\n+\tvstr\ts8, [r1]\n+\tvldr\ts9, [r0]\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tldr\tr1, [sp, #204]\t@ 0xcc\n+\tvcvt.f64.f32\td8, s9\n+\tvldr\ts2, [r3]\n+\tldr\tr3, [sp, #208]\t@ 0xd0\n+\tvldr\ts11, [r0]\n+\tvldr\ts14, [r1]\n+\tvcvt.f64.f32\td1, s2\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tvcvt.f64.f32\td4, s11\n+\tvstr\ts15, [sp, #280]\t@ 0x118\n+\tvcvt.f64.f32\td7, s14\n+\tvstr\td4, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td4, d3, d6\n+\tvmul.f64\td6, d11, d6\n+\tvmla.f64\td4, d9, d11\n+\tvmla.f64\td6, d2, d3\n+\tvsub.f64\td3, d7, d1\n+\tvadd.f64\td7, d7, d1\n+\tvmul.f64\td3, d3, d13\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts13, d6\n+\tvstr\ts8, [r2]\n+\tvstr\ts13, [sp, #204]\t@ 0xcc\n+\tvldr\ts4, [r3]\n+\tvldr\ts8, [r4]\n+\tvldr\ts12, [r0]\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td4, s8\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts11, [r0]\n+\tvstr\ts10, [r3]\n+\tvsub.f64\td0, d2, d6\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tvcvt.f64.f32\td9, s11\n+\tvadd.f64\td5, d10, d8\n+\tvsub.f64\td10, d10, d8\n+\tvadd.f64\td8, d2, d6\n+\tvsub.f64\td6, d6, d2\n+\tldr\tr0, [sp, #228]\t@ 0xe4\n+\tvsub.f64\td1, d4, d9\n+\tvadd.f64\td9, d4, d9\n+\tvadd.f64\td2, d6, d3\n+\tvadd.f64\td6, d3, d0\n+\tvsub.f64\td0, d0, d3\n+\tvsub.f64\td3, d5, d7\n+\tvadd.f64\td5, d5, d7\n+\tvmul.f64\td1, d1, d13\n+\tvstr\td2, [sp, #208]\t@ 0xd0\n+\tvsub.f64\td2, d9, d8\n+\tvstr\td0, [sp, #216]\t@ 0xd8\n+\tvcvt.f32.f64\ts10, d5\n+\tvadd.f64\td7, d10, d1\n+\tvstr\ts10, [r2]\n+\tvsub.f64\td5, d10, d1\n+\tvldr\td1, [sp]\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvldr\td7, [sp, #8]\n+\tvmul.f64\td4, d1, d6\n+\tvmul.f64\td6, d15, d6\n+\tvmla.f64\td6, d1, d5\n+\tvmul.f64\td1, d14, d3\n+\tvmla.f64\td1, d2, d7\n+\tvmul.f64\td3, d7, d3\n+\tldr\tr2, [sp, #240]\t@ 0xf0\n+\tvnmls.f64\td4, d15, d5\n+\tvsub.f64\td5, d8, d9\n+\tvadd.f64\td8, d8, d9\n+\tvldr\ts15, [sp, #280]\t@ 0x118\n+\tvmla.f64\td3, d5, d14\n+\tvcvt.f32.f64\ts16, d8\n \tvcvt.f32.f64\ts12, d6\n-\tvmov.f64\td5, d30\n-\tvfma.f64\td31, d24, d30\n-\tvfma.f64\td28, d25, d4\n-\tvmov.f64\td30, d7\n-\tvfma.f64\td30, d22, d4\n-\tvldr\ts8, [r2]\n-\tvfma.f64\td19, d27, d5\n-\tvldr\ts11, [r3]\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts16, [r3]\n+\tldr\tr3, [sp, #224]\t@ 0xe0\n+\tvstr\ts8, [r1]\n+\tvcvt.f32.f64\ts6, d3\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tvldr\ts8, [r3]\n \tvstr\ts12, [r4]\n-\tvcvt.f32.f64\ts9, d17\n-\tldr\tr4, [sp, #20]\n-\tvcvt.f32.f64\ts15, d21\n-\tadds\tr5, r7, r4\n-\tvcvt.f32.f64\ts13, d31\n-\tvcvt.f32.f64\ts7, d28\n-\tvcvt.f32.f64\ts14, d30\n-\tvcvt.f32.f64\ts3, d19\n-\tvcvt.f64.f32\td19, s11\n-\tvstr\ts7, [r2]\n-\tldr\tr2, [sp, #28]\n-\tvstr\ts9, [r3]\n+\tldr\tr4, [sp, #80]\t@ 0x50\n+\tvstr\ts2, [r1]\n \tvcvt.f64.f32\td4, s8\n-\tadds\tr3, r7, r2\n-\tvldr\ts12, [r5]\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tvcvt.f64.f32\td30, s12\n-\tvldr\ts12, [r3]\n-\tldr\tr3, [sp, #12]\n-\tstr\tr6, [sp, #52]\t@ 0x34\n-\tadd\tr3, r9\n-\tvcvt.f64.f32\td16, s12\n-\tvldr\ts12, [r3]\n-\tvstr\ts13, [r3]\n-\tadd.w\tr3, r9, r4\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #20]\n-\tmov\tr4, r2\n-\tvldr\ts7, [lr]\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #28]\n-\tldr\tr4, [sp, #32]\n-\tadd\tr2, r9\n-\tvcvt.f64.f32\td31, s12\n-\tvcvt.f64.f32\td29, s7\n-\tadd.w\tr6, r9, r4\n-\tvldr\ts12, [r3]\n-\tvldr\ts13, [r2]\n-\tvsub.f64\td28, d30, d16\n-\tvadd.f64\td30, d30, d16\n-\tstr\tr6, [sp, #80]\t@ 0x50\n-\tvldr\ts7, [r6]\n-\tvcvt.f64.f32\td17, s12\n-\tvcvt.f64.f32\td6, s13\n-\tvstr\ts14, [lr]\n-\tadd.w\tlr, r7, r4\n-\tadds\tr6, r4, r1\n-\tvcvt.f64.f32\td16, s7\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tstr\tr6, [sp, #32]\n-\tvsub.f64\td5, d17, d6\n-\tvadd.f64\td6, d17, d6\n-\tvsub.f64\td17, d29, d16\n-\tvadd.f64\td3, d29, d16\n-\tvsub.f64\td16, d16, d29\n-\tvfma.f64\td16, d18, d28\n-\tvmov.f64\td21, d17\n-\tvsub.f64\td29, d6, d3\n-\tvfma.f64\td21, d18, d28\n-\tvfma.f64\td17, d20, d28\n-\tvsub.f64\td28, d3, d6\n-\tvadd.f64\td3, d3, d6\n-\tvmul.f64\td29, d29, d23\n-\tvmul.f64\td28, d28, d26\n-\tvmul.f64\td16, d24, d16\n-\tvcvt.f32.f64\ts14, d3\n-\tvmul.f64\td3, d27, d17\n-\tvnmul.f64\td6, d21, d22\n-\tvmul.f64\td21, d25, d21\n+\tvstr\ts6, [r3]\n+\tldr\tr1, [sp, #232]\t@ 0xe8\n+\tvldr\ts12, [r4]\n+\tldr\tr4, [sp, #88]\t@ 0x58\n+\tvldr\ts14, [r0]\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts4, [r1]\n+\tvldr\ts0, [r4]\n+\tldr\tr4, [sp, #236]\t@ 0xec\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts10, [r4]\n+\tvstr\ts15, [r1]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts7, [r2]\n+\tvadd.f64\td9, d4, d0\n+\tvldr\td1, [sp, #184]\t@ 0xb8\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\td8, [sp, #264]\t@ 0x108\n+\tvcvt.f64.f32\td10, s7\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tvsub.f64\td3, d1, d6\n+\tvadd.f64\td6, d1, d6\n+\tvsub.f64\td1, d4, d0\n+\tvadd.f64\td4, d8, d7\n+\tvsub.f64\td0, d2, d5\n+\tvsub.f64\td7, d8, d7\n+\tvadd.f64\td8, d2, d5\n+\tvsub.f64\td2, d5, d2\n+\tvmul.f64\td3, d3, d13\n+\tldr\tr1, [sp, #252]\t@ 0xfc\n+\tvmul.f64\td1, d1, d13\n+\tvadd.f64\td2, d2, d3\n+\tvadd.f64\td5, d3, d0\n+\tvsub.f64\td0, d0, d3\n+\tvsub.f64\td3, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvadd.f64\td6, d7, d1\n+\tvsub.f64\td7, d7, d1\n+\tvldr\td1, [sp]\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r3]\n+\tvmul.f64\td4, d1, d5\n+\tvmul.f64\td5, d15, d5\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td5, d1, d7\n+\tvldr\td1, [sp, #8]\n+\tvnmls.f64\td4, d15, d7\n+\tvmul.f64\td7, d14, d3\n+\tvmul.f64\td3, d1, d3\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r9]\n+\tvsub.f64\td4, d9, d8\n+\tvmla.f64\td7, d4, d1\n+\tvadd.f64\td4, d8, d9\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts8, [r3]\n+\tldr\tr3, [sp, #244]\t@ 0xf4\n \tvstr\ts14, [r0]\n-\tadds\tr0, r7, r4\n-\tvldr\ts14, [lr]\n-\tvcvt.f64.f32\td17, s14\n-\tvsub.f64\td2, d4, d17\n-\tvadd.f64\td17, d4, d17\n-\tvmov.f64\td4, d2\n-\tvfma.f64\td2, d18, d5\n-\tvfma.f64\td4, d5, d20\n-\tvsub.f64\td5, d17, d30\n-\tvadd.f64\td17, d17, d30\n-\tvfma.f64\td29, d26, d5\n-\tvfma.f64\td28, d23, d5\n-\tvcvt.f32.f64\ts14, d17\n-\tvfma.f64\td16, d27, d2\n-\tvfma.f64\td3, d24, d2\n-\tvfma.f64\td6, d25, d4\n-\tvfma.f64\td21, d22, d4\n-\tvldr\ts8, [r0]\n-\tvstr\ts14, [ip]\n-\tvcvt.f32.f64\ts11, d29\n-\tvcvt.f32.f64\ts9, d28\n-\tvcvt.f32.f64\ts10, d16\n-\tvcvt.f64.f32\td16, s8\n-\tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d21\n+\tvsub.f64\td7, d8, d9\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tvmla.f64\td3, d7, d14\n+\tvldr\ts15, [r3]\n+\tvstr\ts10, [r0]\n+\tldr\tr0, [sp, #260]\t@ 0x104\n+\tvcvt.f64.f32\td5, s15\n+\tvmul.f64\td7, d11, d6\n+\tvadd.f64\td9, d12, d5\n \tvcvt.f32.f64\ts6, d3\n-\tvstr\ts12, [r5]\n-\tadds\tr5, r4, r1\n-\tvstr\ts11, [r0]\n-\tadd.w\tr0, r9, r4\n-\tstr\tr5, [sp, #64]\t@ 0x40\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n-\tvldr\ts14, [r0]\n-\tvstr\ts13, [r3]\n-\tadd.w\tr3, r9, r5\n-\tvstr\ts9, [r0]\n-\tldr\tr0, [sp, #4]\n-\tvcvt.f64.f32\td21, s14\n-\tadd.w\tip, r7, r0\n-\tadds\tr0, r7, r5\n-\tadd\tr5, r1\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tvldr\ts14, [ip]\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts14, [r0]\n-\tvsub.f64\td28, d19, d17\n-\tvadd.f64\td19, d19, d17\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts14, [r3]\n-\tldr\tr6, [sp, #8]\n-\tldr\tr4, [sp, #4]\n-\tadd.w\tr5, r9, r6\n-\tadd\tr6, r1\n-\tvsub.f64\td29, d16, d17\n-\tvadd.f64\td16, d16, d17\n-\tvcvt.f64.f32\td17, s14\n-\tstr\tr6, [sp, #8]\n-\tadd.w\tr6, r9, r4\n-\tvldr\ts14, [r5]\n-\tvmov.f64\td4, d28\n-\tadd\tr4, r1\n-\tvsub.f64\td30, d19, d16\n-\tvadd.f64\td19, d19, d16\n-\tvsub.f64\td16, d21, d17\n-\tvldr\ts12, [r6]\n-\tvstr\ts15, [r5]\n-\tvadd.f64\td21, d21, d17\n-\tldr\tr5, [sp, #48]\t@ 0x30\n-\tvcvt.f32.f64\ts13, d19\n-\tstr\tr4, [sp, #4]\n-\tvfma.f64\td4, d16, d20\n-\tvfma.f64\td28, d18, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvcvt.f64.f32\td7, s12\n-\tldr\tr4, [sp, #24]\n-\tvsub.f64\td17, d16, d7\n-\tvsub.f64\td19, d7, d16\n-\tvadd.f64\td16, d16, d7\n-\tvfma.f64\td19, d18, d29\n-\tvmov.f64\td7, d17\n-\tvfma.f64\td17, d29, d20\n-\tvfma.f64\td7, d18, d29\n-\tvsub.f64\td2, d21, d16\n-\tvsub.f64\td29, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvmul.f64\td2, d2, d23\n-\tvmul.f64\td19, d24, d19\n-\tvfma.f64\td19, d27, d28\n-\tvfma.f64\td2, d26, d30\n-\tvcvt.f32.f64\ts12, d16\n-\tvmul.f64\td29, d29, d26\n-\tvfma.f64\td29, d23, d30\n-\tvmul.f64\td17, d27, d17\n-\tvnmul.f64\td21, d7, d22\n-\tvmul.f64\td7, d25, d7\n-\tvfma.f64\td21, d25, d4\n-\tvfma.f64\td7, d22, d4\n-\tvstr\ts12, [sl]\n-\tadd.w\tsl, r7, r5\n-\tvfma.f64\td17, d24, d28\n-\tvcvt.f32.f64\ts11, d19\n-\tvcvt.f32.f64\ts4, d2\n-\tvcvt.f32.f64\ts9, d29\n-\tvcvt.f32.f64\ts12, d21\n+\tvstr\ts6, [r4]\n+\tvldr\td3, [sp, #16]\n+\tldr\tr4, [sp, #96]\t@ 0x60\n+\tvmul.f64\td6, d3, d6\n+\tvmla.f64\td7, d2, d3\n+\tvmla.f64\td6, d0, d11\n+\tvsub.f64\td0, d12, d5\n+\tvsub.f64\td5, d5, d12\n \tvcvt.f32.f64\ts14, d7\n-\tvldr\ts15, [sl]\n-\tvstr\ts13, [r8]\n-\tadd.w\tr8, r9, r5\n-\tadd\tr5, r1\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tvstr\ts12, [lr]\n-\tadd.w\tlr, r7, r4\n-\tvstr\ts4, [ip]\n-\tvcvt.f64.f32\td29, s15\n-\tvstr\ts11, [sl]\n-\tadd.w\tip, r7, fp\n-\tvldr\ts15, [lr]\n-\tvcvt.f32.f64\ts8, d17\n-\tldr\tr5, [sp, #80]\t@ 0x50\n-\tvcvt.f64.f32\td28, s15\n-\tvldr\ts15, [ip]\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r8]\n-\tvstr\ts14, [r5]\n-\tadds\tr5, r4, r1\n-\tvstr\ts9, [r6]\n-\tadd.w\tr6, r9, r4\n-\tstr\tr5, [sp, #24]\n-\tadd.w\tr5, r9, fp\n-\tvsub.f64\td30, d28, d16\n-\tvadd.f64\td28, d28, d16\n-\tvcvt.f64.f32\td16, s15\n-\tvstr\ts8, [r8]\n-\tvldr\ts14, [r6]\n-\tadd\tfp, r1\n-\tvldr\ts13, [r5]\n-\tvstr\ts6, [r6]\n-\tvsub.f64\td17, d31, d16\n-\tvsub.f64\td19, d16, d31\n-\tvfma.f64\td19, d18, d30\n-\tvcvt.f64.f32\td7, s14\n-\tvadd.f64\td16, d31, d16\n-\tldr\tr6, [sp, #72]\t@ 0x48\n-\tldr\tr4, [sp, #12]\n-\tvmov.f64\td21, d17\n-\tvfma.f64\td17, d30, d20\n-\tvfma.f64\td21, d18, d30\n-\tvcvt.f64.f32\td30, s13\n-\tvsub.f64\td4, d7, d30\n-\tvmul.f64\td19, d24, d19\n-\tvadd.f64\td7, d7, d30\n-\tvmul.f64\td17, d27, d17\n-\tvnmul.f64\td31, d21, d22\n-\tvmul.f64\td21, d25, d21\n-\tvsub.f64\td6, d7, d16\n-\tvsub.f64\td30, d16, d7\n-\tvadd.f64\td7, d16, d7\n-\tvmul.f64\td6, d6, d23\n-\tvmul.f64\td30, d30, d26\n-\tvcvt.f32.f64\ts15, d7\n-\tvstr\ts15, [r6]\n-\tadds\tr6, r7, r4\n-\tadd\tr4, r1\n-\tstr\tr4, [sp, #12]\n-\tvldr\ts15, [r6]\n-\tvstr\ts3, [r6]\n-\tvstr\ts10, [lr]\n-\tvcvt.f64.f32\td16, s15\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tvsub.f64\td7, d16, d29\n-\tvadd.f64\td16, d29, d16\n-\tvmov.f64\td5, d7\n-\tvmov.f64\td29, d7\n-\tvfma.f64\td5, d4, d20\n-\tvsub.f64\td7, d16, d28\n-\tvfma.f64\td29, d18, d4\n-\tvadd.f64\td16, d16, d28\n-\tvfma.f64\td6, d26, d7\n-\tvfma.f64\td30, d23, d7\n-\tvcvt.f32.f64\ts15, d16\n-\tvfma.f64\td31, d25, d5\n-\tvfma.f64\td21, d22, d5\n-\tvstr\ts15, [r4]\n-\tvfma.f64\td19, d27, d29\n-\tldr\tr4, [sp, #76]\t@ 0x4c\n-\tvfma.f64\td17, d24, d29\n-\tvcvt.f32.f64\ts15, d30\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts14, d31\n-\tvstr\ts14, [r4]\n-\tvcvt.f32.f64\ts14, d21\n-\tvstr\ts12, [r0]\n+\tvldr\ts13, [sp, #204]\t@ 0xcc\n \tvstr\ts14, [r2]\n-\tvstr\ts15, [r3]\n-\tvcvt.f32.f64\ts15, d19\n-\tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tvstr\ts15, [ip]\n-\tvcvt.f32.f64\ts15, d17\n-\tcmp\tr3, r2\n-\tvstr\ts15, [r5]\n-\tbne.w\t5742 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xe72>\n-\tstrd\tr1, r7, [sp, #68]\t@ 0x44\n-\tldr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tvstr\ts12, [r3]\n+\tldr\tr2, [sp, #248]\t@ 0xf8\n+\tldr\tr3, [sp, #256]\t@ 0x100\n+\tvldr\ts2, [r1]\n+\tvldr\ts4, [r0]\n+\tvldr\ts6, [r2]\n+\tvldr\ts12, [r3]\n+\tvcvt.f64.f32\td1, s2\n+\tvstr\ts13, [r2]\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts14, [r4]\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td8, d3, d10\n+\tvadd.f64\td4, d10, d3\n+\tvsub.f64\td3, d1, d6\n+\tvadd.f64\td6, d1, d6\n+\tvmul.f64\td3, d3, d13\n+\tvadd.f64\td10, d5, d3\n+\tvsub.f64\td5, d2, d7\n+\tvadd.f64\td7, d2, d7\n+\tvmul.f64\td2, d5, d13\n+\tvadd.f64\td5, d3, d0\n+\tvsub.f64\td3, d0, d3\n+\tvsub.f64\td12, d9, d7\n+\tvstr\td3, [sp, #64]\t@ 0x40\n+\tvsub.f64\td3, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvadd.f64\td6, d8, d2\n+\tvsub.f64\td2, d8, d2\n+\tvldr\td8, [sp]\n+\tvldr\td1, [sp, #16]\n+\tldr\tr2, [sp, #180]\t@ 0xb4\n+\tvmul.f64\td0, d8, d5\n+\tvmul.f64\td5, d15, d5\n+\tvmla.f64\td5, d8, d2\n+\tvsub.f64\td8, d7, d9\n+\tvadd.f64\td9, d9, d7\n+\tvldr\td7, [sp, #104]\t@ 0x68\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\td12, [sp, #56]\t@ 0x38\n+\tvnmls.f64\td0, d15, d2\n+\tvldr\td2, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td7, d11, d7\n+\tldr\tr4, [sp, #80]\t@ 0x50\n+\tvcvt.f32.f64\ts18, d9\n+\tvmla.f64\td7, d2, d1\n+\tvldr\td2, [sp, #216]\t@ 0xd8\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r1]\n+\tvldr\td7, [sp, #104]\t@ 0x68\n+\tvstr\ts8, [r2]\n+\tldr\tr2, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td7, d1, d7\n+\tvldr\td4, [sp, #64]\t@ 0x40\n+\tvmla.f64\td7, d2, d11\n+\tvldr\td2, [sp, #8]\n+\tldr\tr1, [sp, #48]\t@ 0x30\n+\tvstr\ts0, [r1]\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r0]\n+\tvmul.f64\td7, d11, d6\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tvmla.f64\td7, d10, d1\n+\tvstr\ts18, [r2]\n+\tvmul.f64\td6, d1, d6\n+\tvmla.f64\td6, d4, d11\n+\tldr\tr2, [sp, #300]\t@ 0x12c\n+\tvstr\ts10, [r0]\n+\tvmul.f64\td5, d14, d3\n+\tvmla.f64\td5, d8, d2\n+\tvmul.f64\td3, d2, d3\n+\tvldr\td2, [sp, #56]\t@ 0x38\n+\tvcvt.f32.f64\ts14, d7\n+\tvmla.f64\td3, d2, d14\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts10, [r4]\n+\tldr\tr4, [sp, #88]\t@ 0x58\n+\tvstr\ts14, [r3]\n+\tldr\tr3, [sp, #24]\n+\tvstr\ts6, [r4]\n+\tcmp\tr2, r3\n+\tldr\tr4, [sp, #96]\t@ 0x60\n+\tvstr\ts12, [r4]\n+\tbne.w\t5906 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xd4e>\n+\tvldr\td11, [sp]\n+\tmov\tfp, r8\n+\tstr\tr7, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #304]\t@ 0x130\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #304]\t@ 0x130\n \tcmp\tr2, r3\n-\tble.n\t5c64 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1394>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tble.n\t5f28 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1370>\n+\tldr\tr2, [sp, #296]\t@ 0x128\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #304]\t@ 0x130\n+\tldr\tr3, [sp, #312]\t@ 0x138\n+\tldr\tr2, [sp, #328]\t@ 0x148\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #312]\t@ 0x138\n \tcmp\tr3, r2\n-\tbne.w\t5572 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xca2>\n-\tldr\tr2, [sp, #128]\t@ 0x80\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tbne.w\t5722 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb6a>\n+\tldr\tr2, [sp, #348]\t@ 0x15c\n+\tmov\tsl, lr\n+\tldr\tr1, [sp, #352]\t@ 0x160\n+\tmov\tr9, fp\n+\tldr\tr3, [sp, #368]\t@ 0x170\n \tsubs\tr2, #1\n-\tldr.w\tfp, [sp, #68]\t@ 0x44\n+\tldr.w\tip, [sp, #48]\t@ 0x30\n \tadds\tr0, r2, #1\n-\tldr.w\tsl, [sp, #72]\t@ 0x48\n \tadd\tr1, r3\n-\tbne.w\t5564 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xc94>\n-\tmov\tr7, r3\n-\tldr\tr4, [sp, #284]\t@ 0x11c\n-\tldrd\tr6, ip, [sp, #268]\t@ 0x10c\n-\tldrd\tr0, r3, [sp, #276]\t@ 0x114\n-\tsubs\tr6, #1\n-\tldr\tr2, [sp, #216]\t@ 0xd8\n-\tadd\tr0, ip\n-\tadd\tr4, ip\n-\tadds\tr5, r6, #1\n-\tsub.w\tr2, r2, ip\n-\tstr\tr2, [sp, #216]\t@ 0xd8\n-\tbne.w\t5536 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xc66>\n-\tldrd\tr5, r4, [sp, #260]\t@ 0x104\n-\tmov\tr8, r3\n-\tldr\tr3, [sp, #200]\t@ 0xc8\n-\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tbne.w\t5710 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb58>\n+\tldrd\tr7, r6, [sp, #492]\t@ 0x1ec\n+\tmov\tr5, r3\n+\tldr\tr4, [sp, #500]\t@ 0x1f4\n+\tldr\tr3, [sp, #464]\t@ 0x1d0\n+\tldr\tr1, [sp, #444]\t@ 0x1bc\n \tsubs\tr2, r3, #1\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr0, [sp, #248]\t@ 0xf8\n+\tldr\tr3, [sp, #400]\t@ 0x190\n+\tstr\tr2, [sp, #464]\t@ 0x1d0\n+\tadds\tr2, #1\n \tadd\tr1, r3\n-\tstr\tr1, [sp, #168]\t@ 0xa8\n-\tldr\tr1, [sp, #208]\t@ 0xd0\n-\tsubs\tr5, r5, r3\n+\tstr\tr1, [sp, #444]\t@ 0x1bc\n+\tldr\tr1, [sp, #432]\t@ 0x1b0\n \tadd\tr4, r3\n-\tldr\tr3, [sp, #212]\t@ 0xd4\n-\tadd\tr1, r0\n-\tstr\tr1, [sp, #208]\t@ 0xd0\n-\tldr\tr1, [sp, #252]\t@ 0xfc\n-\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tsub.w\tr3, r1, r3\n+\tstr\tr3, [sp, #432]\t@ 0x1b0\n+\tbne.w\t56dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb24>\n+\tldr.w\tr9, [sp, #488]\t@ 0x1e8\n+\tldr\tr3, [sp, #436]\t@ 0x1b4\n+\tldr\tr1, [sp, #412]\t@ 0x19c\n+\tsubs\tr2, r3, #1\n+\tldr\tr3, [sp, #360]\t@ 0x168\n+\tstr\tr2, [sp, #436]\t@ 0x1b4\n \tadds\tr2, #1\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #232]\t@ 0xe8\n-\tstr\tr3, [sp, #212]\t@ 0xd4\n-\tmov\tr3, r1\n-\tbeq.w\t8128 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3858>\n-\tmov\tr2, r1\n-\tldr\tr1, [sp, #244]\t@ 0xf4\n-\tadd\tr2, r1\n-\tstr\tr2, [sp, #232]\t@ 0xe8\n-\tb.w\t54dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xc0c>\n+\tadd\tr1, r3\n+\tstr\tr1, [sp, #412]\t@ 0x19c\n+\tldr\tr1, [sp, #468]\t@ 0x1d4\n+\tadd\tr7, r1\n+\tldr\tr1, [sp, #416]\t@ 0x1a0\n+\tsub.w\tr1, r1, r3\n+\tstr\tr1, [sp, #416]\t@ 0x1a0\n+\tldr\tr1, [sp, #420]\t@ 0x1a4\n+\tadd\tr1, r3\n+\tldr\tr3, [sp, #480]\t@ 0x1e0\n+\tstr\tr1, [sp, #420]\t@ 0x1a4\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #460]\t@ 0x1cc\n+\tmov\tr1, r3\n+\tbeq.w\t845a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38a2>\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #460]\t@ 0x1cc\n+\tb.w\t566c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xab4>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n+\tldr.w\tr8, [sp, #380]\t@ 0x17c\n+\tadd.w\tip, r2, #1\n+\tldr.w\tr9, [sp, #372]\t@ 0x174\n+\tmov\tr0, r3\n+\tldr\tr4, [sp, #152]\t@ 0x98\n+\tadd.w\tr2, sl, r0\n+\tcmp\tr2, r4\n+\titt\tlt\n+\tldrlt\tr4, [sp, #296]\t@ 0x128\n+\taddlt\tr2, r2, r4\n+\tldr\tr4, [sp, #620]\t@ 0x26c\n+\tcmp\tr4, #0\n+\tble.n\t6032 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x147a>\n+\tmov.w\tfp, r2, lsl #2\n+\tldr\tr5, [sp, #332]\t@ 0x14c\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tlsls\tr4, r0, #2\n+\tadd.w\tlr, r5, r4\n+\tadd\tr5, fp\n+\tadd\tr4, r2\n+\tadd\tr2, fp\n+\tldr.w\tfp, [sp, #372]\t@ 0x174\n+\tvldr\ts12, [r5, #-4]\n+\tadd.w\tfp, fp, #1\n+\tvldr\ts14, [lr, #-4]\n+\tcmp\tfp, ip\n+\tvldr\ts15, [r4, #-4]\n+\tvldr\ts13, [r2, #-4]\n+\tvadd.f32\ts11, s14, s12\n+\tvsub.f32\ts14, s14, s12\n+\tvadd.f32\ts12, s15, s13\n+\tvsub.f32\ts15, s15, s13\n+\tvstr\ts11, [lr, #-4]\n+\tadd\tlr, r8\n+\tvstr\ts14, [r5, #-4]\n+\tadd\tr5, r8\n+\tvstr\ts12, [r4, #-4]\n+\tadd\tr4, r8\n+\tvstr\ts15, [r2, #-4]\n+\tadd\tr2, r8\n+\tbne.n\t5ff2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x143a>\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n+\tadd\tr0, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr0, r2\n+\tbge.n\t6040 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1488>\n+\tldr\tr2, [sp, #296]\t@ 0x128\n+\tadd\tr0, r2\n+\tldr\tr2, [sp, #8]\n+\tadd.w\tr9, r9, #1\n+\tcmp\tr9, r2\n+\tbne.n\t5fc6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x140e>\n+\tsubs\tr1, #1\n+\tadd\tr3, r7\n+\tadds\tr2, r1, #1\n+\tbne.n\t5fc0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1408>\n+\tldr\tr3, [sp, #616]\t@ 0x268\n+\tcmp\tr3, #1\n+\tbne.w\t4de4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x22c>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n+\tldr\tr1, [sp, #608]\t@ 0x260\n+\tmla\tr3, r1, r2, r3\n+\tldr\tr2, [sp, #476]\t@ 0x1dc\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #456]\t@ 0x1c8\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #456]\t@ 0x1c8\n+\tcmp\tr3, r2\n+\tbeq.w\t86fc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b44>\n+\tldr\tr3, [sp, #440]\t@ 0x1b8\n+\tstr\tr3, [sp, #620]\t@ 0x26c\n+\tb.w\t4cc0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x108>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tmovs\tr3, #1\n+\tldr\tr6, [sp, #360]\t@ 0x168\n+\tldr.w\tr9, [sp, #152]\t@ 0x98\n+\tadd\tr2, r3\n+\tldr.w\tfp, [sp, #380]\t@ 0x17c\n+\tldr.w\tsl, [sp, #332]\t@ 0x14c\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tstr\tr2, [sp, #24]\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tldr\tr7, [sp, #296]\t@ 0x128\n+\tmov\tr4, r3\n+\tlsls\tr3, r3, #2\n+\tmov\tr0, r7\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r7\n+\tmov\tr5, r0\n+\tlsls\tr7, r0, #2\n+\tstr\tr3, [sp, #16]\n+\tbmi.w\t69ae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1df6>\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #428]\t@ 0x1ac\n+\tmov\tr3, r0\n \tcmp\tr2, #0\n-\tble.w\t4d94 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4c4>\n-\tmov\tr0, r2\n-\tadd.w\tr2, r1, #1073741824\t@ 0x40000000\n-\tsubs\tr2, #1\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tadd.w\tip, r0, r1\n+\tbne.w\t625e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16a6>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tcmp\tr2, #0\n+\tble.w\t625e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16a6>\n+\tldr\tr2, [sp, #608]\t@ 0x260\n+\tcmp\tr2, #1\n+\tmov\tr2, r9\n+\titt\teq\n+\tstreq\tr5, [sp, #28]\n+\tmoveq\tr5, r4\n+\tbne.w\t6516 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x195e>\n+\tmov\tr8, r2\n+\tmovs\tr1, #1\n+\tstr\tr6, [sp, #32]\n+\tstr\tr1, [sp, #0]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr7, [sp, #48]\t@ 0x30\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #16]\n+\tadd\tr3, r8\n+\tcmp\tr9, r3\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #16]\n+\tadd\tr2, r3\n+\tcmp\tr9, r2\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #16]\n+\tadd\tr1, r2\n+\tcmp\tr9, r1\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r0\n+\tldr\tr0, [sp, #620]\t@ 0x26c\n+\tcmp\tr0, #0\n+\tble.w\t622e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1676>\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tlsls\tr2, r2, #2\n+\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tsubs\tr3, #1\n-\tadd.w\tr0, sl, ip, lsl #2\n-\tadd.w\tip, r4, r2\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n+\tsubs\tr1, #1\n+\tadd.w\tr4, r8, #1073741824\t@ 0x40000000\n+\tldr\tr6, [sp, #336]\t@ 0x150\n+\tadd.w\tlr, r0, r8\n+\tsubs\tr2, #1\n+\tldr\tr0, [sp, #356]\t@ 0x164\n+\tsubs\tr4, #1\n \tlsls\tr3, r3, #2\n-\tadd\tr2, r4\n-\tldr\tr4, [sp, #120]\t@ 0x78\n-\tadd.w\tr8, r4, r3\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n-\tadd\tr3, r4\n-\tldr\tr4, [sp, #0]\n-\tvldr\ts12, [ip]\n-\tvldr\ts14, [r8]\n-\tvldr\ts13, [r3]\n-\tvldr\ts15, [r2]\n-\tvcvt.f64.f32\td17, s12\n-\tvcvt.f64.f32\td23, s14\n-\tvadd.f32\ts14, s14, s12\n-\tvcvt.f64.f32\td16, s13\n-\tvcvt.f64.f32\td19, s15\n-\tvadd.f32\ts15, s15, s13\n-\tvsub.f64\td17, d17, d23\n-\tvstmia\tip!, {s14}\n-\tcmp\tip, r0\n-\tvsub.f64\td16, d16, d19\n-\tvstmia\tr2!, {s15}\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts15, d16\n-\tvstmia\tr3!, {s14}\n-\tvstmia\tr8!, {s15}\n-\tbne.n\t5d1e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x144e>\n-\tb.w\t4d92 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4c2>\n-\tudiv\tr8, r7, r5\n-\tldr\tr0, [sp, #148]\t@ 0x94\n-\tcmp\tr0, r1\n-\tble.w\t4ccc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3fc>\n-\tb.w\t4dc4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4f4>\n-\tldr\tr3, [sp, #200]\t@ 0xc8\n-\tcmp\tfp, r5\n-\tudiv\tr3, r7, r3\n-\tble.w\t4e60 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x590>\n-\tb.w\t5456 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb86>\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tmov\tr7, fp\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tmovs\tr5, #0\n-\tstr.w\tlr, [sp, #156]\t@ 0x9c\n-\tmov\tlr, r6\n-\tadds\tr3, #1\n-\tstr.w\tsl, [sp, #168]\t@ 0xa8\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tstr.w\tfp, [sp, #128]\t@ 0x80\n-\tcmp\tr0, #0\n-\tblt.w\t645c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b8c>\n-\tudiv\tr1, r7, r0\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tcmp\tr3, r5\n-\tblt.w\t642c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b5c>\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tcmp\tr3, #0\n-\tble.w\t642c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b5c>\n-\tldr\tr6, [sp, #16]\n+\tlsls\tr1, r1, #2\n+\tlsls\tr2, r2, #2\n+\tlsls\tr4, r4, #2\n+\tadd.w\tr7, sl, r3\n+\tadd\tr3, r6\n+\tstr\tr3, [sp, #8]\n+\tadd.w\tr3, sl, r1\n+\tadd.w\tlr, r0, lr, lsl #2\n+\tadd.w\tip, sl, r2\n+\tadd.w\tr0, sl, r4\n+\tadd\tr2, r6\n+\tadd\tr4, r6\n+\tadd\tr1, r6\n+\tmov\tr6, r3\n+\tldr\tr3, [sp, #8]\n+\tvldr\ts12, [r7]\n+\tvldr\ts6, [r6]\n+\tvldr\ts2, [r3]\n+\tvldr\ts8, [r1]\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts10, [r0]\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts4, [ip]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts16, [r4]\n+\tvldr\ts14, [r2]\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td2, s4\n+\tvsub.f64\td0, d6, d3\n+\tvcvt.f64.f32\td8, s16\n+\tvadd.f64\td3, d3, d6\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td6, d1, d4\n+\tvadd.f64\td4, d4, d1\n+\tvmul.f64\td0, d0, d13\n+\tvadd.f64\td1, d2, d5\n+\tvsub.f64\td5, d5, d2\n+\tvmul.f64\td6, d6, d13\n+\tvadd.f64\td2, d7, d8\n+\tvsub.f64\td7, d8, d7\n+\tvadd.f64\td8, d3, d1\n+\tvsub.f64\td1, d1, d3\n+\tvadd.f64\td3, d4, d2\n+\tvsub.f64\td2, d2, d4\n+\tvsub.f64\td4, d5, d6\n+\tvadd.f64\td6, d6, d5\n+\tvadd.f64\td5, d7, d0\n+\tvsub.f64\td7, d7, d0\n+\tvcvt.f32.f64\ts16, d8\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr0!, {s16}\n+\tcmp\tr0, lr\n+\tvstmia\tr4!, {s6}\n+\tvstmia\tip!, {s2}\n+\tvstmia\tr2!, {s4}\n+\tvstmia\tr7!, {s8}\n+\tvstmia\tr3!, {s10}\n+\tvstmia\tr6!, {s12}\n+\tvstmia\tr1!, {s14}\n+\tbne.n\t6162 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15aa>\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #24]\n+\tadd\tr8, r3\n+\tcmp\tr9, r8\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #0]\n \tadds\tr3, #1\n-\tldr.w\tr9, [sp, #124]\t@ 0x7c\n-\tadd\tr6, r5\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tldr.w\tr8, [sp, #120]\t@ 0x78\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tstr\tr6, [sp, #104]\t@ 0x68\n-\tstrd\tip, r4, [sp, #208]\t@ 0xd0\n-\tstr\tr0, [sp, #216]\t@ 0xd8\n-\tstr\tr5, [sp, #232]\t@ 0xe8\n-\tstrd\tr1, lr, [sp, #240]\t@ 0xf0\n-\tstrd\tr6, r2, [sp, #248]\t@ 0xf8\n-\tstr\tr7, [sp, #260]\t@ 0x104\n+\tstr\tr3, [sp, #0]\n+\tcmp\tr3, r2\n+\tbne.w\t60ec <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1534>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr7, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tsubs\tr3, #1\n+\tldr\tr6, [sp, #32]\n+\tadds\tr0, r3, #1\n+\tadd\tr2, r7\n+\tbne.w\t60de <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1526>\n+\tmov\tr4, r5\n+\tldr\tr5, [sp, #28]\n+\tldr\tr3, [sp, #616]\t@ 0x268\n+\tcmp\tr3, #2\n+\tbeq.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n+\tlsls\tr4, r4, #1\n+\tsubs\tr5, r5, r6\n+\tcmp\tr6, #0\n+\tblt.w\t699c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1de4>\n+\tmov\tr1, r6\n+\tsubs\tr0, r5, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tstr\tr0, [sp, #32]\n+\tbgt.w\t66d6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b1e>\n+\tldr\tr3, [sp, #608]\t@ 0x260\n+\tcmp\tr3, #1\n+\tmov.w\tr3, #24\n+\tbne.w\t66e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b30>\n+\tmul.w\tr5, r3, r4\n+\tlsls\tr2, r4, #3\n+\tlsls\tr3, r4, #4\n+\tldr\tr4, [sp, #404]\t@ 0x194\n+\tadd.w\tr0, r5, #8\n \tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadds\tr2, r3, r2\n+\tadd.w\tip, r4, r0\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tadds\tr1, r4, r2\n+\tstr\tr5, [sp, #88]\t@ 0x58\n+\tsubs\tr4, r0, r6\n+\tadds\tr3, r1, r2\n+\tsubs\tr0, r6, r0\n+\tmov\tr5, r7\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tnegs\tr0, r7\n+\tldr\tr7, [sp, #336]\t@ 0x150\n+\tmov\tr8, r6\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tmov\tr4, ip\n+\tstr.w\tfp, [sp, #96]\t@ 0x60\n+\tmov\tfp, r3\n+\tstr\tr3, [sp, #28]\n+\tstr\tr0, [sp, #72]\t@ 0x48\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #28]\n+\tcmp\tr5, #0\n+\tvldr\td7, [sp, #392]\t@ 0x188\n+\tvldr\td11, [r1, #8]\n+\tvldr\td6, [r4]\n+\tvldr\td14, [r3, #8]\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td10, [r1]\n+\tvldr\td12, [r3]\n+\tvmul.f64\td14, d7, d14\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td15, [r4, #-8]\n+\tvstr\td7, [sp, #8]\n+\tblt.w\t66be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b06>\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t64e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1930>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tcmp\tr2, #0\n+\tble.w\t64e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1930>\n+\tadd.w\tr2, r9, r8\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr.w\tr8, [sp, #112]\t@ 0x70\n+\tstr.w\tfp, [sp, #120]\t@ 0x78\n+\tmov\tr8, r2\n+\tmov.w\tfp, #1\n+\tstr\tr5, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr2, [sp, #144]\t@ 0x90\n+\tstr\tr4, [sp, #156]\t@ 0x9c\n \tldr\tr3, [sp, #16]\n-\tcmp\tr3, r2\n-\tble.n\t5e06 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1536>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tadd\tr3, r8\n+\tcmp\tr9, r3\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tldr\tr2, [sp, #16]\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadds\tr1, r3, r2\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, r1\n-\tble.n\t5e14 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1544>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr4, [sp, #16]\n-\tadd\tr3, r1\n-\tstr\tr3, [sp, #4]\n-\tcmp\tr4, r3\n-\tble.n\t5e26 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1556>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr3, r0\n-\tstr\tr3, [sp, #4]\n-\tldrd\tr4, r3, [sp, #100]\t@ 0x64\n-\tadd.w\tsl, r3, r4\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, sl\n-\tble.n\t5e38 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1568>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tsl, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadd.w\tlr, r3, sl\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, lr\n-\tble.n\t5e48 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1578>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadd.w\tfp, r3, lr\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, fp\n-\tble.n\t5e58 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1588>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tfp, r3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr4, [sp, #16]\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #8]\n-\tcmp\tr4, r3\n-\tble.n\t5e6a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x159a>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr3, r0\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr4, [sp, #16]\n-\tadd\tr3, sl\n-\tcmp\tr4, r3\n-\tble.n\t5e78 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15a8>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr3, r0\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tadds\tr7, r4, r3\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr4, r7\n-\tble.n\t5e86 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15b6>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr7, r0\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tadds\tr6, r4, r7\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr4, r6\n-\tble.n\t5e94 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15c4>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr6, r0\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tldr\tr5, [sp, #16]\n-\tadd\tr4, r6\n-\tstr\tr4, [sp, #12]\n-\tcmp\tr5, r4\n-\tble.n\t5ea6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15d6>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #12]\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tadd.w\tip, r4, r3\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr4, ip\n-\tble.n\t5eb6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15e6>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tip, r0\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tadd.w\tr5, r4, ip\n-\tldr\tr4, [sp, #16]\n-\tstr\tr5, [sp, #0]\n-\tcmp\tr4, r5\n-\tble.n\t5eca <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x15fa>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr5, r0\n-\tstr\tr5, [sp, #0]\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tldr\tr0, [sp, #0]\n-\tadds\tr5, r4, r0\n-\tldr\tr4, [sp, #16]\n-\tcmp\tr4, r5\n-\tble.n\t5eda <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x160a>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr5, r0\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tldr\tr0, [sp, #16]\n-\tadd\tr4, r5\n-\tstr\tr4, [sp, #20]\n-\tcmp\tr0, r4\n-\tble.n\t5eec <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x161c>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #20]\n-\tldr\tr0, [sp, #404]\t@ 0x194\n-\tcmp\tr0, #0\n-\tble.w\t63ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b1e>\n-\tadd.w\tr4, lr, #1073741824\t@ 0x40000000\n+\tcmp\tr9, r2\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r1\n+\tldr\tr1, [sp, #16]\n+\tadds\tr0, r1, r2\n+\tcmp\tr9, r0\n+\titt\tgt\n+\tldrgt\tr1, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r1\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n+\tcmp\tr1, #0\n+\tble.w\t64b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x18fc>\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n-\tsubs\tr4, #1\n-\tstr\tr4, [sp, #28]\n-\tldr\tr4, [sp, #8]\n-\tsubs\tr2, #1\n-\tstr\tr2, [sp, #24]\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tadd.w\tr2, r4, #1073741824\t@ 0x40000000\n-\tldr\tr4, [sp, #12]\n-\tsubs\tr2, #1\n-\tstr\tr2, [sp, #32]\n-\tadd.w\tr2, r4, #1073741824\t@ 0x40000000\n-\tldr\tr0, [sp, #4]\n-\tsubs\tr2, #1\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #0]\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n-\tsubs\tr0, #1\n+\tadd.w\tr4, r8, #1073741824\t@ 0x40000000\n+\tadd.w\tlr, r1, r8\n+\tsubs\tr2, #1\n+\tldr\tr1, [sp, #356]\t@ 0x164\n \tsubs\tr3, #1\n-\tadd.w\tr4, r2, #1073741824\t@ 0x40000000\n-\tldr\tr2, [sp, #20]\n-\tadd.w\tsl, sl, #1073741824\t@ 0x40000000\n-\tadd.w\tip, ip, #1073741824\t@ 0x40000000\n-\tadd.w\tlr, r2, #1073741824\t@ 0x40000000\n-\tldr\tr2, [sp, #24]\n-\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n-\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n+\tsubs\tr0, #1\n+\tsubs\tr4, #1\n \tlsls\tr2, r2, #2\n-\tstr\tr2, [sp, #20]\n-\tlsls\tr2, r0, #2\n-\tstr\tr2, [sp, #24]\n-\tlsls\tr2, r3, #2\n-\tldr\tr3, [sp, #28]\n-\tstr\tr2, [sp, #4]\n-\tmov.w\tr2, sl, lsl #2\n-\tstr\tr2, [sp, #8]\n-\tmov.w\tr2, ip, lsl #2\n-\tstr\tr2, [sp, #12]\n-\tlsls\tr2, r3, #2\n+\tlsls\tr3, r3, #2\n+\tlsls\tr0, r0, #2\n+\tlsls\tr4, r4, #2\n+\tadd.w\tlr, r1, lr, lsl #2\n+\tadd.w\tip, sl, r2\n+\tadd.w\tr1, sl, r4\n+\tadd.w\tr6, sl, r3\n+\tadd.w\tr5, sl, r0\n+\tadd\tr4, r7\n+\tadd\tr2, r7\n+\tadd\tr3, r7\n+\tadd\tr0, r7\n+\tvldr\ts2, [r6]\n+\tvldr\ts12, [r5]\n+\tvldr\ts16, [r1]\n+\tvldr\ts8, [ip]\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts6, [r4]\n+\tvcvt.f64.f32\td8, s16\n+\tvldr\ts10, [r2]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts4, [r3]\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts14, [r0]\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td2, s4\n+\tvadd.f64\td0, d4, d8\n+\tvsub.f64\td9, d8, d4\n+\tvsub.f64\td4, d1, d6\n+\tvadd.f64\td6, d6, d1\n+\tvadd.f64\td8, d5, d3\n+\tvsub.f64\td1, d3, d5\n+\tvsub.f64\td5, d5, d3\n+\tvcvt.f64.f32\td7, s14\n+\tvmul.f64\td4, d4, d13\n+\tvadd.f64\td5, d5, d4\n+\tvadd.f64\td3, d1, d4\n+\tvsub.f64\td1, d1, d4\n+\tvsub.f64\td4, d0, d6\n+\tvadd.f64\td6, d6, d0\n+\tvldr\td0, [sp, #8]\n+\tvstr\td5, [sp]\n+\tvsub.f64\td5, d2, d7\n+\tvadd.f64\td7, d7, d2\n+\tvmul.f64\td2, d3, d11\n+\tvcvt.f32.f64\ts12, d6\n+\tvmul.f64\td5, d5, d13\n+\tvstmia\tr1!, {s12}\n+\tcmp\tr1, lr\n+\tvsub.f64\td6, d9, d5\n+\tvadd.f64\td5, d5, d9\n+\tvnmls.f64\td2, d6, d10\n+\tvmul.f64\td6, d6, d11\n+\tvmla.f64\td6, d3, d10\n+\tvsub.f64\td3, d7, d8\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts12, d6\n+\tvstmia\tr6!, {s4}\n+\tvmul.f64\td2, d4, d12\n+\tvmla.f64\td2, d3, d14\n+\tvsub.f64\td3, d8, d7\n+\tvadd.f64\td7, d7, d8\n+\tvldr\td8, [sp]\n+\tvmul.f64\td4, d4, d14\n+\tvmla.f64\td4, d3, d12\n+\tvmul.f64\td3, d5, d15\n+\tvmul.f64\td5, d5, d0\n+\tvmla.f64\td3, d8, d0\n+\tvmla.f64\td5, d1, d15\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts4, d2\n+\tvstmia\tr4!, {s14}\n+\tvstmia\tr3!, {s12}\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tip!, {s4}\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts10, d5\n+\tvstmia\tr2!, {s8}\n+\tvstmia\tr5!, {s6}\n+\tvstmia\tr0!, {s10}\n+\tbne.w\t639e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x17e6>\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd.w\tfp, fp, #1\n+\tadd\tr8, r3\n+\tcmp\tr9, r8\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #24]\n+\tcmp\tfp, r3\n+\tbne.w\t6330 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1778>\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tldr\tr5, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #144]\t@ 0x90\n+\tsubs\tr3, #1\n+\tldr\tr4, [sp, #156]\t@ 0x9c\n+\tadds\tr6, r3, #1\n+\tadd\tr2, r5\n+\tbne.w\t6322 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x176a>\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr.w\tr8, [sp, #112]\t@ 0x70\n+\tldr.w\tfp, [sp, #120]\t@ 0x78\n+\tldr\tr2, [sp, #28]\n+\tadd\tr8, r6\n+\tldr\tr1, [sp, #64]\t@ 0x40\n \tldr\tr3, [sp, #32]\n-\tsubs\tr5, #1\n+\tadd\tr2, r1\n \tstr\tr2, [sp, #28]\n-\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tsubs\tr1, #1\n-\tadd.w\tfp, fp, #1073741824\t@ 0x40000000\n-\tlsls\tr2, r3, #2\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n-\tadd.w\tr7, r7, #1073741824\t@ 0x40000000\n-\tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n-\tsubs\tr7, #1\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tlsls\tr3, r5, #2\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tmov.w\tr3, lr, lsl #2\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tsubs\tr6, #1\n-\tsubs\tr4, #1\n-\tlsls\tr1, r1, #2\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tldr\tr0, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #40]\t@ 0x28\n \tsubs\tr3, #1\n-\tmov.w\tfp, fp, lsl #2\n-\tlsls\tr5, r4, #2\n-\tstr\tr2, [sp, #32]\n-\tmov.w\tlr, r3, lsl #2\n-\tstr.w\tlr, [sp, #56]\t@ 0x38\n-\tmov\tlr, r1\n-\tlsls\tr2, r7, #2\n-\tmovs\tr3, #1\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tstr\tr3, [sp, #0]\n-\tlsls\tr2, r6, #2\n-\tstr\tr5, [sp, #60]\t@ 0x3c\n+\tmov\tr1, fp\n+\tstr\tr3, [sp, #32]\n+\tsubs\tr2, r2, r6\n \tstr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #20]\n-\tadd.w\tr6, r8, lr\n-\tldr\tr5, [sp, #24]\n-\tadd.w\tsl, r8, r2\n-\tldr\tr3, [sp, #0]\n-\tadd.w\tr1, r8, r5\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tadds\tr4, r5, r0\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadds\tr3, #1\n-\tvldr\ts15, [sl]\n+\tadd\tr2, r6\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tadd\tr4, r2\n+\tbeq.w\t66d2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b1a>\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tfp, r3\n+\tb.n\t62c6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x170e>\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n+\tmov\tlr, sl\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #32]\n+\tmov\tr1, r2\n+\tmov.w\tr8, #1\n+\tmov\tsl, r4\n+\tmov\tip, r2\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tstr\tr7, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #16]\n+\tadd\tr3, r1\n+\tcmp\tr3, r9\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr3, r3, r2\n+\tldr\tr2, [sp, #16]\n+\tadd\tr2, r3\n+\tcmp\tr2, r9\n+\titt\tlt\n+\tldrlt\tr0, [sp, #296]\t@ 0x128\n+\taddlt\tr2, r2, r0\n+\tldr\tr0, [sp, #16]\n+\tadd\tr0, r2\n+\tcmp\tr0, r9\n+\titt\tlt\n+\tldrlt\tr4, [sp, #296]\t@ 0x128\n+\taddlt\tr0, r0, r4\n+\tldr\tr4, [sp, #620]\t@ 0x26c\n+\tcmp\tr4, #0\n+\tble.w\t668c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ad4>\n+\tlsls\tr0, r0, #2\n+\tstr\tr0, [sp, #28]\n+\tldr\tr0, [sp, #336]\t@ 0x150\n+\tlsls\tr3, r3, #2\n+\tadd.w\tr6, lr, r3\n+\tlsls\tr5, r1, #2\n+\tadd\tr3, r0\n+\tstr\tr3, [sp, #8]\n+\tlsls\tr2, r2, #2\n+\tmovs\tr3, #1\n \tstr\tr3, [sp, #0]\n-\tstr\tr4, [sp, #24]\n-\tadd.w\tr4, r9, lr\n-\tvcvt.f64.f32\td17, s15\n-\tvldr\ts15, [r1]\n-\tadd.w\tr1, r9, r2\n-\tadd\tr2, r0\n-\tstr\tr2, [sp, #20]\n-\tadd.w\tr2, r9, r5\n-\tvcvt.f64.f32\td16, s15\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tvldr\ts15, [r1]\n-\tadd\tlr, r0\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tstr\tr4, [sp, #72]\t@ 0x48\n-\tvcvt.f64.f32\td19, s15\n-\tvldr\ts15, [r2]\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tvsub.f64\td22, d17, d16\n-\tvadd.f64\td17, d17, d16\n-\tadd.w\tr5, r8, r2\n-\tvcvt.f64.f32\td16, s15\n-\tadd.w\tr3, r9, r2\n-\tadd\tr2, r0\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tvldr\ts15, [r5]\n-\tvsub.f64\td23, d19, d16\n-\tvadd.f64\td19, d19, d16\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r6]\n-\tldr\tr6, [sp, #4]\n-\tvcvt.f64.f32\td21, s15\n-\tadd.w\tr2, r8, r6\n-\tvldr\ts8, [r2]\n-\tvsub.f64\td7, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvmov.f64\td5, d7\n-\tvfma.f64\td7, d18, d23\n-\tvadd.f64\td21, d16, d17\n-\tvsub.f64\td16, d16, d17\n-\tvfma.f64\td5, d23, d20\n-\tvcvt.f32.f64\ts13, d16\n-\tvcvt.f32.f64\ts9, d21\n-\tvcvt.f32.f64\ts14, d7\n-\tvldr\ts15, [r3]\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r4]\n-\tvcvt.f64.f32\td21, s15\n-\tvsub.f64\td17, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvmov.f64\td21, d17\n-\tvfma.f64\td17, d18, d22\n-\tvfma.f64\td21, d20, d22\n-\tvadd.f64\td22, d16, d19\n-\tvsub.f64\td16, d16, d19\n-\tvcvt.f32.f64\ts15, d22\n-\tvcvt.f64.f32\td22, s8\n-\tvcvt.f32.f64\ts11, d16\n-\tvcvt.f32.f64\ts12, d17\n-\tvstr\ts15, [r3]\n-\tvcvt.f32.f64\ts15, d21\n+\tadd.w\tr7, lr, r2\n \tldr\tr3, [sp, #8]\n-\tadd\tr3, r8\n-\tvldr\ts8, [r3]\n-\tvstr\ts9, [r5]\n-\tldr\tr5, [sp, #28]\n-\tvstr\ts13, [r2]\n-\tvcvt.f64.f32\td17, s8\n-\tldr\tr2, [sp, #12]\n-\tadd.w\tr6, r8, r5\n-\tvstr\ts10, [r3]\n-\tadd.w\tr3, r9, r2\n-\tvldr\ts13, [r3]\n-\tvstr\ts15, [r3]\n-\tadd.w\tr3, r9, r5\n-\tvldr\ts15, [r6]\n-\tadd\tr5, r0\n-\tldr\tr4, [sp, #32]\n-\tvcvt.f64.f32\td19, s13\n-\tstr\tr5, [sp, #28]\n-\tadd.w\tr7, r8, r4\n-\tvcvt.f64.f32\td21, s15\n-\tadd.w\tr2, r9, r4\n-\tadds\tr5, r4, r0\n-\tstr\tr5, [sp, #32]\n-\tadd.w\tr5, r8, fp\n-\tvldr\ts15, [r7]\n-\tldr\tr4, [sp, #8]\n-\tstr\tr7, [sp, #80]\t@ 0x50\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r3]\n-\tadd.w\tip, r9, r4\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #8]\n-\tadd.w\tr4, r9, fp\n-\tvcvt.f64.f32\td23, s15\n-\tvldr\ts15, [r2]\n-\tvsub.f64\td24, d21, d16\n-\tvadd.f64\td21, d21, d16\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n-\tadd\tfp, r0\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r5]\n-\tvcvt.f64.f32\td25, s15\n-\tvldr\ts15, [ip]\n-\tvsub.f64\td26, d23, d16\n-\tvadd.f64\td23, d23, d16\n-\tvsub.f64\td16, d17, d25\n-\tvadd.f64\td17, d17, d25\n-\tvmov.f64\td4, d16\n-\tvfma.f64\td16, d18, d26\n-\tvfma.f64\td4, d26, d20\n-\tvcvt.f32.f64\ts13, d16\n-\tvadd.f64\td16, d17, d21\n-\tvsub.f64\td17, d17, d21\n-\tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts7, d16\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r4]\n-\tvcvt.f32.f64\ts9, d17\n-\tvstr\ts12, [ip]\n-\tldr\tr4, [sp, #36]\t@ 0x24\n-\tvcvt.f64.f32\td21, s15\n-\tadd.w\tip, r8, r4\n-\tvsub.f64\td17, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvldr\ts10, [ip]\n-\tvstr\ts7, [sl]\n-\tvstr\ts9, [ip]\n-\tvmov.f64\td21, d17\n-\tvfma.f64\td17, d24, d20\n-\tvfma.f64\td21, d18, d24\n-\tvstr\ts8, [r6]\n-\tadd.w\tr6, r9, r4\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tadd.w\tsl, r8, r4\n-\tvcvt.f32.f64\ts12, d17\n-\tvadd.f64\td17, d16, d23\n-\tvsub.f64\td16, d16, d23\n-\tvcvt.f32.f64\ts6, d21\n-\tvcvt.f32.f64\ts5, d17\n-\tvcvt.f64.f32\td17, s10\n-\tvcvt.f32.f64\ts15, d16\n-\tvldr\ts10, [r6]\n-\tvstr\ts5, [r1]\n-\tvcvt.f64.f32\td25, s10\n-\tvstr\ts15, [r6]\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tvstr\ts6, [r3]\n-\tvldr\ts15, [sl]\n-\tadd.w\tr3, r8, r6\n-\tadd.w\tr1, r9, r6\n-\tadd\tr6, r0\n-\tstr\tr6, [sp, #44]\t@ 0x2c\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts15, [r3]\n-\tldr\tr6, [sp, #4]\n-\tvcvt.f64.f32\td21, s15\n-\tvldr\ts15, [r1]\n-\tvsub.f64\td24, d22, d16\n-\tvadd.f64\td16, d22, d16\n-\tadd.w\tip, r9, r6\n-\tadd\tr6, r0\n-\tstr\tr6, [sp, #4]\n-\tadd.w\tr6, r9, r4\n-\tvsub.f64\td23, d17, d21\n-\tvadd.f64\td17, d17, d21\n-\tvcvt.f64.f32\td21, s15\n-\tvldr\ts15, [ip]\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tldr\tr4, [sp, #48]\t@ 0x30\n-\tvadd.f64\td4, d16, d17\n-\tvsub.f64\td16, d16, d17\n-\tvsub.f64\td22, d25, d21\n-\tvadd.f64\td25, d25, d21\n-\tvmov.f64\td21, d24\n-\tldr\tr7, [sp, #64]\t@ 0x40\n-\tvcvt.f32.f64\ts10, d16\n-\tvcvt.f64.f32\td16, s15\n-\tvfma.f64\td21, d22, d20\n-\tvldr\ts15, [r6]\n-\tvfma.f64\td24, d18, d22\n+\tadd\tr2, r0\n+\tadd.w\tr4, lr, r5\n+\tadd\tr0, r5\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n+\tstr.w\tr9, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tstr\tr5, [sp, #104]\t@ 0x68\n+\tldr\tr1, [sp, #0]\n+\tldr\tr5, [sp, #104]\t@ 0x68\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #8]\n+\tstr\tr1, [sp, #0]\n+\tsub.w\tr8, r4, r5\n+\tldr\tr1, [sp, #28]\n+\tsub.w\tr9, r0, r5\n+\tvldr\ts4, [r6, #-4]\n+\tadd\tr8, r1\n+\tvldr\ts14, [r4, #-4]\n+\tvldr\ts10, [r7, #-4]\n+\tadd\tr9, r1\n+\tvldr\ts12, [r0, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts2, [r2, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts0, [r8, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts8, [r3, #-4]\n+\tvcvt.f64.f32\td1, s2\n+\tldr\tr1, [sp, #8]\n+\tvcvt.f64.f32\td0, s0\n+\tldr\tr5, [sp, #32]\n+\tvcvt.f64.f32\td3, s8\n+\tvadd.f64\td4, d7, d5\n+\tvsub.f64\td7, d7, d5\n+\tcmp\tr1, r5\n+\tvadd.f64\td5, d6, d1\n+\tvsub.f64\td6, d6, d1\n+\tvsub.f64\td1, d2, d0\n+\tvadd.f64\td2, d2, d0\n+\tvadd.f64\td0, d4, d2\n+\tvsub.f64\td4, d4, d2\n+\tvmul.f64\td1, d1, d13\n \tvcvt.f32.f64\ts8, d4\n-\tvstr\ts11, [ip]\n-\tadd.w\tip, r8, r4\n-\tvcvt.f64.f32\td22, s15\n-\tvldr\ts4, [ip]\n-\tvstr\ts8, [r7]\n-\tvstr\ts10, [sl]\n-\tvcvt.f32.f64\ts7, d21\n-\tvsub.f64\td21, d16, d22\n-\tvadd.f64\td16, d16, d22\n-\tvcvt.f32.f64\ts9, d24\n-\tldr\tr7, [sp, #52]\t@ 0x34\n-\tvcvt.f64.f32\td17, s4\n-\tvmov.f64\td22, d21\n-\tvfma.f64\td21, d23, d20\n-\tvfma.f64\td22, d18, d23\n-\tvadd.f64\td23, d16, d25\n-\tvsub.f64\td16, d16, d25\n-\tvstr\ts7, [r5]\n-\tvstr\ts9, [ip]\n-\tadds\tr5, r4, r0\n-\tadd.w\tip, r9, r4\n-\tldr\tr4, [sp, #72]\t@ 0x48\n-\tvcvt.f32.f64\ts5, d23\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tvcvt.f32.f64\ts15, d16\n-\tldr\tr5, [sp, #92]\t@ 0x5c\n-\tvldr\ts10, [ip]\n-\tvcvt.f32.f64\ts11, d21\n-\tvstr\ts5, [r4]\n-\tvcvt.f32.f64\ts6, d22\n-\tldr\tr4, [sp, #60]\t@ 0x3c\n-\tvcvt.f64.f32\td16, s10\n-\tvstr\ts15, [r6]\n-\tadd.w\tr6, r8, r4\n-\tvstr\ts6, [r5]\n-\tadd.w\tr5, r8, r7\n-\tvsub.f64\td21, d19, d16\n-\tvadd.f64\td16, d19, d16\n-\tvldr\ts15, [r6]\n-\tvstr\ts11, [ip]\n-\tadd.w\tip, r9, r4\n-\tadd\tr4, r0\n-\tstr\tr4, [sp, #60]\t@ 0x3c\n-\tvcvt.f64.f32\td22, s15\n-\tvldr\ts15, [r5]\n-\tvmov.f64\td5, d21\n-\tmov\tr4, r7\n-\tadd\tr7, r9\n-\tadd\tr4, r0\n-\tvcvt.f64.f32\td19, s15\n-\tvldr\ts15, [ip]\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tldr\tr4, [sp, #76]\t@ 0x4c\n-\tvsub.f64\td23, d22, d19\n-\tvadd.f64\td22, d22, d19\n-\tvcvt.f64.f32\td19, s15\n-\tvldr\ts15, [r7]\n-\tvfma.f64\td5, d18, d23\n-\tvfma.f64\td21, d23, d20\n+\tvcvt.f32.f64\ts0, d0\n+\tvadd.f64\td2, d1, d6\n+\tvsub.f64\td6, d6, d1\n+\tvstr\ts0, [r4, #-4]\n+\tadd\tr4, fp\n+\tvstr\ts8, [r7, #-4]\n+\tvcvt.f32.f64\ts3, d2\n+\tvldr\ts8, [r9, #-4]\n+\tvcvt.f32.f64\ts12, d6\n+\tadd\tr7, fp\n+\tvcvt.f64.f32\td4, s8\n+\tvsub.f64\td2, d3, d4\n+\tvadd.f64\td4, d3, d4\n+\tvmul.f64\td3, d2, d13\n+\tvadd.f64\td2, d5, d4\n+\tvsub.f64\td5, d5, d4\n+\tvsub.f64\td4, d7, d3\n+\tvadd.f64\td7, d7, d3\n+\tvcvt.f32.f64\ts4, d2\n \tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts11, d21\n-\tvcvt.f64.f32\td21, s15\n-\tvsub.f64\td23, d19, d21\n-\tvadd.f64\td19, d19, d21\n-\tvadd.f64\td21, d16, d19\n-\tvsub.f64\td16, d16, d19\n-\tvcvt.f32.f64\ts15, d21\n-\tvstr\ts15, [r4]\n-\tvcvt.f32.f64\ts15, d16\n-\tvstr\ts15, [r1]\n-\tvstr\ts12, [ip]\n-\tvstr\ts10, [r2]\n-\tvstr\ts11, [r7]\n-\tldr\tr1, [sp, #12]\n-\tldr\tr7, [sp, #80]\t@ 0x50\n-\tadd.w\tr2, r8, r1\n-\tadds\tr4, r1, r0\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr4, [sp, #12]\n-\tvldr\ts15, [r2]\n-\tvstr\ts14, [r2]\n-\tvstr\ts13, [r6]\n-\tvcvt.f64.f32\td16, s15\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tvsub.f64\td19, d16, d17\n-\tvadd.f64\td16, d17, d16\n-\tvadd.f64\td21, d16, d22\n-\tvmov.f64\td17, d19\n-\tvfma.f64\td17, d23, d20\n-\tvsub.f64\td16, d16, d22\n-\tvfma.f64\td19, d18, d23\n-\tvcvt.f32.f64\ts15, d21\n-\tvstr\ts15, [r1]\n-\tvcvt.f32.f64\ts15, d16\n-\tvstr\ts15, [r3]\n-\tvcvt.f32.f64\ts15, d17\n-\tldr\tr3, [sp, #0]\n-\tcmp\tr3, r2\n-\tvstr\ts15, [r7]\n-\tvcvt.f32.f64\ts15, d19\n-\tvstr\ts15, [r5]\n-\tbne.w\t5fc8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16f8>\n-\tstr\tr0, [sp, #64]\t@ 0x40\n-\tldrd\tr3, r2, [sp, #104]\t@ 0x68\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tcmp\tr2, r3\n-\tble.n\t6402 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b32>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr2, [sp, #136]\t@ 0x88\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts4, [r0, #-4]\n+\tadd\tr0, fp\n+\tvstr\ts10, [r2, #-4]\n+\tadd\tr2, fp\n+\tvstr\ts3, [r3, #-4]\n+\tadd\tr3, fp\n+\tvstr\ts8, [r6, #-4]\n+\tadd\tr6, fp\n+\tvstr\ts12, [r9, #-4]\n+\tvstr\ts14, [r8, #-4]\n+\tbne.n\t658e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x19d6>\n+\tldr.w\tr8, [sp, #80]\t@ 0x50\n+\tldr.w\tr9, [sp, #88]\t@ 0x58\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd\tr1, r3\n+\tcmp\tr1, r9\n+\tbge.n\t6698 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ae0>\n+\tldr\tr3, [sp, #296]\t@ 0x128\n+\tadd\tr1, r3\n+\tldr\tr3, [sp, #24]\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr8, r3\n+\tbne.w\t6530 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1978>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmov\tr2, ip\n+\tldr\tr7, [sp, #72]\t@ 0x48\n+\tmov\tr4, sl\n+\tsubs\tr3, #1\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tadd\tr2, r7\n+\tadds\tr1, r3, #1\n+\tbne.w\t651e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1966>\n+\tmov\tsl, lr\n+\tb.n\t625e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16a6>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t630c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1754>\n+\tb.n\t64e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1930>\n+\tldr.w\tfp, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #424]\t@ 0x1a8\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tcmp\tr3, r2\n-\tbne.w\t5df6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1526>\n-\tldrd\tr1, lr, [sp, #240]\t@ 0xf0\n-\tldrd\tr6, r2, [sp, #248]\t@ 0xf8\n-\tsubs\tr1, #1\n-\tldr\tr0, [sp, #216]\t@ 0xd8\n-\tadds\tr3, r1, #1\n-\tldrd\tip, r4, [sp, #208]\t@ 0xd0\n-\tadd\tr6, r0\n-\tldr\tr5, [sp, #232]\t@ 0xe8\n-\tldr\tr7, [sp, #260]\t@ 0x104\n-\tbne.w\t5dd6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1506>\n-\tsubs\tr4, #1\n-\tadd\tr5, ip\n-\tadd\tr2, ip\n-\tsub.w\tr7, r7, ip\n-\tadds\tr6, r4, #1\n-\tbne.w\t5db0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14e0>\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n-\tmov\tr6, lr\n-\tldr\tr2, [sp, #204]\t@ 0xcc\n-\tldr.w\tsl, [sp, #168]\t@ 0xa8\n-\tldr.w\tfp, [sp, #128]\t@ 0x80\n-\tcmp\tr3, r2\n-\tldr.w\tlr, [sp, #156]\t@ 0x9c\n-\tbne.w\t5470 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xba0>\n-\tldr.w\tr9, [sp, #236]\t@ 0xec\n-\tb.w\t4b16 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x246>\n-\tldr\tr3, [sp, #200]\t@ 0xc8\n-\tudiv\tr1, r2, r3\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tcmp\tr3, r5\n-\tble.w\t5dc2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14f2>\n-\tb.n\t642c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b5c>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tldr\tr3, [sp, #16]\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr2, r3\n+\tbge.w\t6096 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14de>\n+\tb.w\t4cec <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x134>\n+\tmul.w\tip, r3, r4\n+\tldr\tr0, [sp, #404]\t@ 0x194\n+\tlsls\tr1, r4, #3\n+\tlsls\tr3, r4, #4\n+\tadd.w\tr2, ip, #8\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tadds\tr4, r0, r2\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tadds\tr3, r0, r1\n+\tstr.w\tr9, [sp, #28]\n+\tsubs\tr0, r6, r2\n+\tsubs\tr2, r2, r6\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tmov\tr8, r6\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n+\tmov\tr9, ip\n+\tstr.w\tsl, [sp, #72]\t@ 0x48\n+\tadds\tr5, r3, r1\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tadds\tr7, r2, #1\n-\tldr.w\tr8, [sp, #160]\t@ 0xa0\n-\tmov\tr4, r3\n-\tldr\tr5, [sp, #16]\n-\tadd.w\tr2, sl, r4\n-\tcmp\tr2, r5\n-\tbge.n\t648c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bbc>\n-\tldr\tr5, [sp, #88]\t@ 0x58\n-\tadd\tr2, r5\n-\tldr\tr5, [sp, #404]\t@ 0x194\n-\tcmp\tr5, #0\n-\tble.n\t64f0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c20>\n-\tmov.w\tfp, r2, lsl #2\n-\tldr\tr6, [sp, #120]\t@ 0x78\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tlsls\tr5, r4, #2\n-\tadd.w\tlr, r6, r5\n-\tadd\tr6, fp\n-\tadd\tr5, r2\n+\tstr\tr0, [sp, #40]\t@ 0x28\n+\tmov\tsl, r2\n+\tnegs\tr0, r7\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tstr\tr0, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tvldr\td7, [r3]\n+\tcmp\tr7, #0\n+\tvldr\td15, [r3, #8]\n+\tvldr\td12, [r5, #8]\n+\tvldr\td10, [r4]\n+\tvstr\td7, [sp, #8]\n+\tvldr\td7, [sp, #392]\t@ 0x188\n+\tvldr\td14, [r5]\n+\tvldr\td11, [r4, #-8]\n+\tvmul.f64\td15, d7, d15\n+\tvmul.f64\td12, d7, d12\n+\tvmul.f64\td10, d7, d10\n+\tblt.w\t697e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1dc6>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t6950 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d98>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tcmp\tr2, #0\n+\tble.w\t6950 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d98>\n+\tldr\tr2, [sp, #28]\n+\tmov\tr1, r9\n+\tadd\tr2, r8\n+\tmov\tr9, r2\n+\tmovs\tr0, #1\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr\tr7, [sp, #112]\t@ 0x70\n+\tstr.w\tr8, [sp, #120]\t@ 0x78\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tstr\tr5, [sp, #144]\t@ 0x90\n+\tstr\tr4, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #16]\n+\tadd.w\tr4, r3, r9\n+\tldr\tr3, [sp, #28]\n+\tcmp\tr4, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #296]\t@ 0x128\n+\taddlt\tr4, r4, r3\n+\tldr\tr3, [sp, #16]\n+\tadds\tr5, r3, r4\n+\tldr\tr3, [sp, #28]\n+\tcmp\tr5, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #296]\t@ 0x128\n+\taddlt\tr5, r5, r3\n+\tldr\tr3, [sp, #16]\n+\tadd.w\tlr, r3, r5\n+\tldr\tr3, [sp, #28]\n+\tcmp\tlr, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #296]\t@ 0x128\n+\taddlt\tlr, r3\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tcmp\tr3, #0\n+\tble.w\t691c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d64>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tlsls\tr5, r5, #2\n+\tldr\tr6, [sp, #336]\t@ 0x150\n+\tlsls\tr4, r4, #2\n+\tmov.w\tr8, r9, lsl #2\n+\tadds\tr7, r3, r5\n+\tadd.w\tr2, r3, r8\n+\tadd\tr5, r6\n+\tadds\tr6, r3, r4\n+\tldr\tr3, [sp, #336]\t@ 0x150\n+\tmov.w\tlr, lr, lsl #2\n+\tmov.w\tip, #1\n+\tadd\tr4, r3\n+\tadd\tr3, r8\n+\tstrd\tr0, r9, [sp, #160]\t@ 0xa0\n+\tvldr\ts2, [r2, #-4]\n+\tsub.w\tr9, r2, r8\n+\tvldr\ts12, [r7, #-4]\n+\tadd\tr9, lr\n+\tvldr\ts14, [r6, #-4]\n+\tsub.w\tr0, r3, r8\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts6, [r3, #-4]\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts10, [r5, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tadd\tr0, lr\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts4, [r4, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tadd.w\tip, ip, #1\n+\tvadd.f64\td4, d1, d6\n+\tvsub.f64\td9, d1, d6\n+\tvldr\ts12, [r9, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tcmp\tip, sl\n+\tvadd.f64\td8, d3, d5\n+\tvsub.f64\td1, d3, d5\n+\tvcvt.f64.f32\td6, s12\n+\tvsub.f64\td5, d5, d3\n+\tvadd.f64\td0, d7, d6\n+\tvsub.f64\td6, d7, d6\n+\tvldr\ts14, [r0, #-4]\n+\tvmul.f64\td6, d6, d13\n+\tvcvt.f64.f32\td7, s14\n+\tvadd.f64\td5, d5, d6\n+\tvsub.f64\td3, d2, d7\n+\tvadd.f64\td7, d2, d7\n+\tvstr\td5, [sp]\n+\tvadd.f64\td5, d6, d1\n+\tvsub.f64\td1, d1, d6\n+\tvsub.f64\td6, d4, d0\n+\tvadd.f64\td4, d4, d0\n+\tvmul.f64\td3, d3, d13\n+\tvldr\td0, [sp, #8]\n+\tvmul.f64\td2, d15, d5\n+\tvcvt.f32.f64\ts8, d4\n+\tvmul.f64\td5, d0, d5\n+\tvstr\ts8, [r2, #-4]\n+\tvadd.f64\td4, d9, d3\n+\tvsub.f64\td3, d9, d3\n \tadd\tr2, fp\n-\tldr.w\tfp, [sp, #160]\t@ 0xa0\n-\tstr\tr3, [sp, #0]\n-\tvldr\ts12, [r6, #-4]\n-\tadd.w\tfp, fp, #1\n-\tvldr\ts14, [lr, #-4]\n-\tcmp\tfp, r7\n-\tvldr\ts15, [r5, #-4]\n-\tvldr\ts13, [r2, #-4]\n-\tvadd.f32\ts11, s14, s12\n-\tvsub.f32\ts14, s14, s12\n-\tldr\tr3, [sp, #172]\t@ 0xac\n-\tvadd.f32\ts12, s15, s13\n-\tvsub.f32\ts15, s15, s13\n-\tvstr\ts11, [lr, #-4]\n-\tadd\tlr, r3\n-\tvstr\ts14, [r6, #-4]\n-\tadd\tr6, r3\n+\tvnmls.f64\td2, d0, d3\n+\tvmla.f64\td5, d15, d3\n+\tvmul.f64\td3, d14, d6\n+\tvldr\td0, [sp]\n+\tvmul.f64\td6, d12, d6\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts10, d5\n+\tvstr\ts4, [r6, #-4]\n+\tvsub.f64\td2, d7, d8\n+\tadd\tr6, fp\n+\tvmla.f64\td3, d2, d12\n+\tvsub.f64\td2, d8, d7\n+\tvadd.f64\td7, d8, d7\n+\tvmla.f64\td6, d2, d14\n+\tvmul.f64\td2, d11, d4\n+\tvmul.f64\td4, d10, d4\n+\tvmla.f64\td2, d0, d10\n+\tvmla.f64\td4, d1, d11\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts14, [r3, #-4]\n+\tadd\tr3, fp\n+\tvstr\ts10, [r4, #-4]\n+\tadd\tr4, fp\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts6, [r7, #-4]\n+\tvcvt.f32.f64\ts4, d2\n+\tadd\tr7, fp\n+\tvcvt.f32.f64\ts8, d4\n \tvstr\ts12, [r5, #-4]\n+\tadd\tr5, fp\n+\tvstr\ts4, [r9, #-4]\n+\tvstr\ts8, [r0, #-4]\n+\tbne.w\t67e6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c2e>\n+\tldrd\tr0, r9, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #28]\n+\tcmp\tr9, r3\n+\tbge.n\t692a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d72>\n+\tldr\tr3, [sp, #296]\t@ 0x128\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #24]\n+\tadds\tr0, #1\n+\tcmp\tr0, r3\n+\tbne.w\t6788 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bd0>\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr7, [sp, #112]\t@ 0x70\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tsubs\tr3, #1\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tadds\tr0, r3, #1\n+\tldr.w\tr8, [sp, #120]\t@ 0x78\n+\tadd\tr2, r7\n+\tldr\tr5, [sp, #144]\t@ 0x90\n+\tldr\tr4, [sp, #156]\t@ 0x9c\n+\tbne.w\t6774 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bbc>\n+\tmov\tr9, r1\n+\tldr\tr3, [sp, #32]\n+\tadd\tr8, r6\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tadd\tr4, r9\n+\tsubs\tr2, r3, #1\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tstr\tr2, [sp, #32]\n+\tadds\tr2, #1\n \tadd\tr5, r3\n-\tvstr\ts15, [r2, #-4]\n-\tadd\tr2, r3\n-\tbne.n\t64ac <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bdc>\n-\tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n-\tadd\tr4, r2\n-\tldr\tr2, [sp, #16]\n-\tcmp\tr4, r2\n-\tbge.n\t64fe <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c2e>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr4, r2\n-\tldr\tr2, [sp, #4]\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr8, r2\n-\tbne.n\t647e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bae>\n-\tsubs\tr1, #1\n-\tadd\tr3, ip\n-\tadds\tr4, r1, #1\n-\tbne.n\t6478 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ba8>\n-\tb.w\t4b0e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23e>\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\trsb\tr3, ip, #0\n-\tudiv\tr1, r2, r3\n-\tldr\tr3, [sp, #148]\t@ 0x94\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr3, r6\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tsub.w\tr3, r3, r6\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tmov\tr3, r1\n+\tbeq.n\t6992 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1dda>\n+\tmov\tr2, r1\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tadd\tr2, r1\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tb.n\t6722 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b6a>\n+\tldr\tr1, [sp, #88]\t@ 0x58\n+\tldr\tr0, [sp, #40]\t@ 0x28\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t6766 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1bae>\n+\tb.n\t6950 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d98>\n+\tldr.w\tr9, [sp, #28]\n+\tldr.w\tsl, [sp, #72]\t@ 0x48\n+\tb.n\t66d6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b1e>\n+\tnegs\tr1, r6\n+\tsubs\tr0, r6, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tstr\tr0, [sp, #32]\n+\tbge.w\t6280 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16c8>\n+\tb.n\t66d6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1b1e>\n+\tldr\tr0, [sp, #384]\t@ 0x180\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, #0\n+\tble.w\t60c6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x150e>\n+\tb.n\t625e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x16a6>\n+\tnegs\tr1, r7\n+\tldr\tr0, [sp, #384]\t@ 0x180\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr1, r0\n \tcmp\tr3, #0\n-\tble.w\t4a10 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x140>\n-\tb.w\t4b0e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23e>\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tble.w\t4d20 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x168>\n+\tb.w\t4ddc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x224>\n+\tldr\tr3, [sp, #376]\t@ 0x178\n \tcmp\tr3, #0\n-\tbeq.w\t4dde <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x50e>\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tbeq.w\t4f5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a2>\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n+\tldr\tr4, [sp, #296]\t@ 0x128\n+\tvldr\td8, [pc, #188]\t@ 6aa8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ef0>\n \tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tsdiv\tr1, r2, r3\n-\tsubs\tr3, r1, r2\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r4\n \tstr\tr3, [sp, #0]\n-\tldr\tr3, [sp, #408]\t@ 0x198\n+\tvmov.f64\td4, #240\t@ 0xbf800000 -1.0\n+\tldr\tr3, [sp, #624]\t@ 0x270\n+\tlsls\tr7, r0, #3\n+\tvldr\td7, [pc, #168]\t@ 6ab0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ef8>\n \tadds\tr3, #1\n-\tldr\tr3, [sp, #224]\t@ 0xe0\n-\tbne.n\t654e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1c7e>\n-\trsb\tr3, r3, #8\n-\tbic.w\tr2, r3, #4\n-\tvldr\td24, [pc, #780]\t@ 6860 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f90>\n-\tcmp\tr2, #3\n-\tvldr\td17, [pc, #780]\t@ 6868 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f98>\n-\tsub.w\tr3, r3, #3\n-\tvmov.f64\td16, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n+\tldr\tr3, [sp, #452]\t@ 0x1c4\n+\tit\teq\n+\trsbeq\tr3, r3, #8\n+\tbic.w\tr1, r3, #4\n+\tsubs\tr3, #3\n+\tcmp\tr1, #3\n \tbic.w\tr3, r3, #2\n-\tvseleq.f64\td19, d24, d17\n-\tvseleq.f64\td25, d17, d24\n-\tvseleq.f64\td16, d16, d21\n+\tite\tne\n+\tvmovne.f64\td6, d7\n+\tvmoveq.f64\td6, d8\n+\tite\tne\n+\tvmovne.f64\td9, d8\n+\tvmoveq.f64\td9, d7\n+\tit\teq\n+\tvmoveq.f64\td14, d4\n \tcmp\tr3, #0\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tvseleq.f64\td25, d25, d19\n-\tvseleq.f64\td24, d24, d17\n-\tsubs\tr0, r1, r2\n+\tldr\tr3, [sp, #360]\t@ 0x168\n+\tit\tne\n+\tvmovne.f64\td9, d6\n+\tit\tne\n+\tvmovne.f64\td8, d7\n+\tsub.w\tr8, r0, r3\n+\tcmp\tr3, #0\n+\tblt.w\t79ec <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e34>\n+\tmov\tr1, r3\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp.w\tr8, #0\n+\tmov\tr9, r0\n+\tblt.w\t6da4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21ec>\n+\tnegs\tr3, r7\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #608]\t@ 0x260\n+\tcmp\tr3, #1\n+\tbne.w\t7a0c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e54>\n+\tldr\tr6, [sp, #384]\t@ 0x180\n+\tmov\tsl, r8\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tmov\tr8, r7\n+\tldr\tr5, [sp, #340]\t@ 0x154\n+\tmovs\tr4, #0\n+\tldr.w\tfp, [sp, #360]\t@ 0x168\n+\tmov\tr7, r6\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tcmp.w\tr8, #0\n+\tblt.w\t75dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a24>\n+\tmov\tr1, r8\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tblt.w\t6d8c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21d4>\n+\tb.n\t6ab8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f00>\n+\tnop\n+\tnop.w\n+\t.word\t0x667f3bcd\n+\t.word\t0xbfe6a09e\n+\t.word\t0x667f3bcd\n+\t.word\t0x3fe6a09e\n+\tldr\tr2, [sp, #344]\t@ 0x158\n \tcmp\tr2, #0\n-\tmov.w\tr1, r1, lsl #3\n-\tblt.w\t74b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2be4>\n-\tudiv\tr3, r0, r2\n-\tcmp\tr0, #0\n-\tblt.w\t68c6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ff6>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\trsb\tlr, r1, #0\n-\tcmp\tr2, #1\n-\tbne.w\t74ce <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2bfe>\n-\tldr\tr5, [sp, #132]\t@ 0x84\n-\tmovs\tr2, #0\n-\tldr.w\tsl, [sp, #148]\t@ 0x94\n-\tmov\tip, r0\n-\tadds\tr5, #1\n-\tldr\tr4, [sp, #176]\t@ 0xb0\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tmov\tr7, sl\n-\tldr\tr5, [sp, #120]\t@ 0x78\n-\tldr.w\tr8, [sp, #144]\t@ 0x90\n-\tsubs\tr5, #4\n-\tstr\tr5, [sp, #52]\t@ 0x34\n-\tcmp\tr1, #0\n-\tblt.w\t70a8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27d8>\n-\tudiv\tr0, r7, r1\n-\tcmp\tsl, r2\n-\tblt.w\t68b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fe4>\n-\tldr\tr5, [sp, #132]\t@ 0x84\n-\tcmp\tr5, #0\n-\tble.w\t68b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fe4>\n-\tldr\tr5, [sp, #16]\n-\tadd\tr5, r2\n-\tmovs\tr6, #1\n-\tstr\tr5, [sp, #32]\n-\tstr\tr6, [sp, #36]\t@ 0x24\n-\tstrd\tr8, ip, [sp, #56]\t@ 0x38\n-\tstrd\tr3, lr, [sp, #64]\t@ 0x40\n-\tstrd\tsl, r2, [sp, #72]\t@ 0x48\n-\tstrd\tr0, r9, [sp, #80]\t@ 0x50\n-\tstrd\tr1, r5, [sp, #92]\t@ 0x5c\n-\tstrd\tr7, r4, [sp, #100]\t@ 0x64\n+\tble.w\t6d8c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21d4>\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tadd\tr2, r4\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tstr\tr1, [sp, #64]\t@ 0x40\n+\tstr.w\tfp, [sp, #88]\t@ 0x58\n+\tstr.w\tsl, [sp, #96]\t@ 0x60\n+\tstr.w\tr9, [sp, #104]\t@ 0x68\n+\tstr\tr4, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tstr.w\tr8, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tstr\tr5, [sp, #144]\t@ 0x90\n+\tstr\tr7, [sp, #156]\t@ 0x9c\n \tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #32]\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr4, [sp, #152]\t@ 0x98\n \tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr3, r0\n-\tble.n\t660c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d3c>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr0, r3\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tldr\tr7, [sp, #152]\t@ 0x98\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r3\n \tldr\tr3, [sp, #0]\n \tadds\tr5, r3, r0\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r5\n-\tble.n\t661a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d4a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r3\n \tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #16]\n \tadd\tr3, r5\n \tcmp\tr2, r3\n-\tble.n\t6628 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d58>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr1, r2, r3\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r1\n-\tble.n\t6636 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d66>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr1, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r2\n \tldr\tr2, [sp, #0]\n-\tldr\tr4, [sp, #16]\n \tadd\tr2, r1\n \tcmp\tr4, r2\n-\tble.n\t6644 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d74>\n-\tldr\tr4, [sp, #88]\t@ 0x58\n-\tadd\tr2, r4\n+\titt\tgt\n+\tldrgt\tr4, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r4\n \tldr\tr4, [sp, #0]\n-\tldr\tr6, [sp, #16]\n \tadd\tr4, r2\n \tcmp\tr6, r4\n-\tble.n\t6652 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d82>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tadd\tr4, r6\n+\titt\tgt\n+\tldrgt\tr6, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r6\n \tldr\tr6, [sp, #0]\n-\tldr\tr7, [sp, #16]\n \tadd\tr6, r4\n \tcmp\tr7, r6\n-\tble.n\t6660 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d90>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\titt\tgt\n+\tldrgt\tr7, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tcmp\tr7, #0\n-\tble.w\t6870 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fa0>\n+\tble.w\t6d46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x218e>\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n \tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tsubs\tr3, #1\n \tsubs\tr6, #1\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tmov.w\tip, r3, lsl #2\n \tsubs\tr5, #1\n \tlsls\tr3, r6, #2\n \tsubs\tr0, #1\n-\tstr\tr3, [sp, #8]\n-\tldr\tr6, [sp, #404]\t@ 0x194\n+\tstr\tr3, [sp, #16]\n+\tldr\tr6, [sp, #620]\t@ 0x26c\n \tsubs\tr2, #1\n-\tldr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tlsls\tr7, r5, #2\n \tlsls\tr5, r0, #2\n \tlsls\tr0, r2, #2\n \tadd.w\tr2, r3, #1073741824\t@ 0x40000000\n \tadds\tr3, r6, r3\n-\tldr\tr6, [sp, #52]\t@ 0x34\n+\tldr\tr6, [sp, #356]\t@ 0x164\n \tsubs\tr2, #1\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n \tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n \tlsls\tr2, r2, #2\n \tsubs\tr1, #1\n \tadd.w\tr3, r6, r3, lsl #2\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tsubs\tr4, #1\n-\tstr\tr3, [sp, #28]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tadds\tr3, r6, r2\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #336]\t@ 0x150\n \tlsls\tr1, r1, #2\n \tlsls\tr4, r4, #2\n \tadd.w\tfp, r6, r7\n \tadd\tr2, r3\n \tadd.w\tsl, r6, r4\n \tadd.w\tr9, r6, r5\n \tadds\tr4, r3, r4\n \tadd.w\tr8, r6, r0\n \tadd.w\tlr, r6, ip\n-\tstr\tr4, [sp, #40]\t@ 0x28\n+\tstr\tr4, [sp, #72]\t@ 0x48\n \tadd\tr7, r3\n \tadds\tr4, r3, r0\n \tadd\tr5, r3\n \tadd.w\tr0, r3, ip\n-\tstr\tr2, [sp, #20]\n+\tstr\tr2, [sp, #28]\n \tadds\tr2, r6, r1\n \tadd\tr1, r3\n-\tstr\tr2, [sp, #12]\n+\tstr\tr2, [sp, #24]\n \tmov\tr2, r3\n \tmov\tr3, r6\n-\tldr\tr6, [sp, #8]\n-\tstr\tr0, [sp, #8]\n+\tldr\tr6, [sp, #16]\n+\tstr\tr0, [sp, #16]\n \tadd.w\tip, r3, r6\n \tmov\tr3, r2\n \tadd\tr3, r6\n-\tldr\tr6, [sp, #40]\t@ 0x28\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #4]\n-\tstr\tr1, [sp, #4]\n-\tldr\tr2, [sp, #12]\n-\tldr\tr1, [sp, #20]\n-\tldr\tr0, [sp, #4]\n-\tvldr\ts11, [r3]\n-\tvldr\ts13, [r2]\n-\tvldr\ts14, [r1]\n-\tvldr\ts15, [r0]\n-\tvadd.f32\ts12, s13, s11\n-\tvsub.f32\ts11, s11, s13\n-\tvadd.f32\ts13, s15, s14\n-\tvsub.f32\ts14, s14, s15\n-\tvstmia\tr3!, {s12}\n-\tvldr\ts12, [fp]\n-\tvstmia\tr1!, {s13}\n-\tvldr\ts13, [sl]\n-\tvldr\ts10, [r7]\n-\tvcvt.f64.f32\td30, s12\n-\tvldr\ts15, [r6]\n-\tvadd.f32\ts12, s13, s12\n-\tvcvt.f64.f32\td19, s13\n-\tvcvt.f64.f32\td17, s10\n-\tstr\tr1, [sp, #20]\n-\tvadd.f32\ts13, s15, s10\n-\tvcvt.f64.f32\td22, s15\n-\tvstmia\tr2!, {s12}\n-\tvsub.f64\td30, d30, d19\n-\tstr\tr2, [sp, #12]\n-\tmov\tr2, r0\n-\tvldr\ts15, [r8]\n-\tvsub.f64\td17, d17, d22\n-\tvldr\ts12, [r9]\n-\tvstmia\tr2!, {s13}\n-\tvmul.f64\td30, d30, d16\n-\tvldr\ts10, [r5]\n-\tvcvt.f64.f32\td21, s15\n-\tvldr\ts13, [r4]\n-\tvcvt.f64.f32\td26, s12\n-\tstr\tr2, [sp, #4]\n-\tvadd.f32\ts12, s15, s12\n-\tldr\tr2, [sp, #8]\n-\tvcvt.f64.f32\td19, s10\n-\tvadd.f32\ts15, s13, s10\n-\tvcvt.f64.f32\td23, s13\n-\tvsub.f64\td22, d26, d21\n-\tvmul.f64\td17, d17, d16\n-\tvstmia\tfp!, {s12}\n-\tvcvt.f32.f64\ts13, d30\n-\tvldr\ts9, [lr]\n-\tvstmia\tr7!, {s15}\n-\tvsub.f64\td19, d19, d23\n-\tvldr\ts15, [r2]\n+\tldr\tr6, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #8]\n+\tstr\tr1, [sp, #8]\n \tldr\tr2, [sp, #24]\n-\tvcvt.f64.f32\td28, s9\n-\tvldr\ts10, [ip]\n-\tvcvt.f64.f32\td26, s15\n-\tvldr\ts12, [r2]\n-\tvcvt.f64.f32\td29, s10\n-\tvsub.f64\td23, d22, d28\n-\tvadd.f32\ts10, s10, s9\n-\tvsub.f64\td21, d19, d26\n-\tvcvt.f64.f32\td27, s12\n-\tvadd.f32\ts12, s12, s15\n-\tvsub.f64\td22, d22, d29\n-\tvcvt.f32.f64\ts15, d17\n-\tvadd.f64\td23, d23, d29\n-\tvstmia\tsl!, {s10}\n-\tvstmia\tr9!, {s11}\n-\tvsub.f64\td19, d19, d27\n-\tvadd.f64\td21, d21, d27\n-\tvadd.f64\td22, d22, d28\n-\tvstmia\tr6!, {s12}\n-\tvmul.f64\td23, d23, d24\n-\tvstmia\tr5!, {s14}\n-\tldr\tr1, [sp, #8]\n-\tvadd.f64\td17, d19, d26\n-\tvmul.f64\td21, d21, d24\n-\tvmul.f64\td22, d22, d25\n-\tvstmia\tr4!, {s15}\n-\tvstmia\tr8!, {s13}\n-\tvcvt.f32.f64\ts12, d23\n-\tvmul.f64\td17, d17, d25\n-\tvcvt.f32.f64\ts14, d21\n-\tvcvt.f32.f64\ts13, d22\n-\tvstmia\tlr!, {s12}\n-\tvcvt.f32.f64\ts15, d17\n+\tldr\tr1, [sp, #28]\n+\tldr\tr0, [sp, #8]\n+\tvldr\ts23, [r3]\n+\tvldr\ts14, [r2]\n+\tvldr\ts22, [r1]\n+\tvldr\ts15, [r0]\n+\tvadd.f32\ts13, s14, s23\n+\tvsub.f32\ts23, s23, s14\n+\tvadd.f32\ts14, s15, s22\n+\tvsub.f32\ts22, s22, s15\n+\tvstmia\tr3!, {s13}\n+\tvldr\ts15, [fp]\n \tvstmia\tr1!, {s14}\n-\tvstmia\tip!, {s13}\n-\tstr\tr1, [sp, #8]\n-\tvstmia\tr2!, {s15}\n+\tvldr\ts14, [sl]\n+\tvldr\ts12, [r7]\n+\tvcvt.f64.f32\td4, s15\n+\tvldr\ts10, [r6]\n+\tvadd.f32\ts7, s14, s15\n+\tvcvt.f64.f32\td7, s14\n+\tstr\tr1, [sp, #28]\n+\tvadd.f32\ts6, s10, s12\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td6, s12\n+\tvstmia\tr2!, {s7}\n+\tvsub.f64\td4, d4, d7\n \tstr\tr2, [sp, #24]\n-\tldr\tr2, [sp, #28]\n+\tmov\tr2, r0\n+\tvsub.f64\td6, d6, d5\n+\tvldr\ts10, [r9]\n+\tvstmia\tr2!, {s6}\n+\tvmul.f64\td4, d4, d14\n+\tvldr\ts5, [r5]\n+\tvldr\ts4, [r4]\n+\tstr\tr2, [sp, #8]\n+\tvmul.f64\td6, d6, d14\n+\tldr\tr2, [sp, #16]\n+\tvcvt.f32.f64\ts21, d4\n+\tvadd.f32\ts3, s4, s5\n+\tvldr\ts6, [r8]\n+\tvcvt.f64.f32\td7, s5\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f32.f64\ts20, d6\n+\tvadd.f32\ts2, s6, s10\n+\tvcvt.f64.f32\td3, s6\n+\tvstmia\tr7!, {s3}\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts9, [r2]\n+\tvsub.f64\td7, d7, d2\n+\tldr\tr2, [sp, #32]\n+\tvstmia\tfp!, {s2}\n+\tvldr\ts8, [lr]\n+\tvcvt.f64.f32\td1, s9\n+\tvldr\ts12, [ip]\n+\tvsub.f64\td5, d5, d3\n+\tvldr\ts13, [r2]\n+\tvcvt.f64.f32\td3, s8\n+\tvcvt.f64.f32\td2, s12\n+\tvadd.f32\ts12, s12, s8\n+\tvcvt.f64.f32\td0, s13\n+\tvadd.f32\ts13, s13, s9\n+\tvsub.f64\td4, d7, d1\n+\tvstmia\tsl!, {s12}\n+\tvsub.f64\td7, d7, d0\n+\tvstmia\tr6!, {s13}\n+\tvsub.f64\td6, d5, d3\n+\tvsub.f64\td5, d5, d2\n+\tvadd.f64\td4, d4, d0\n+\tvstmia\tr9!, {s23}\n+\tldr\tr1, [sp, #16]\n+\tvadd.f64\td1, d7, d1\n+\tvstmia\tr5!, {s22}\n+\tvadd.f64\td6, d6, d2\n+\tvadd.f64\td7, d5, d3\n+\tvmul.f64\td4, d4, d8\n+\tvstmia\tr4!, {s20}\n+\tvstmia\tr8!, {s21}\n+\tvmul.f64\td1, d1, d9\n+\tvmul.f64\td6, d6, d8\n+\tvmul.f64\td7, d7, d9\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr1!, {s8}\n+\tstr\tr1, [sp, #16]\n+\tvstmia\tr2!, {s2}\n+\tstr\tr2, [sp, #32]\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tvstmia\tlr!, {s12}\n \tcmp\tr3, r2\n-\tbne.w\t6706 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1e36>\n-\tb.n\t6870 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fa0>\n-\t.word\t0x667f3bcd\n-\t.word\t0xbfe6a09e\n-\t.word\t0x667f3bcd\n-\t.word\t0x3fe6a09e\n-\tldr\tr3, [sp, #32]\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tvstmia\tip!, {s14}\n+\tbne.w\t6bee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2036>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #32]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr2, r3\n-\tble.n\t6884 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fb4>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #80]\t@ 0x50\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, r2\n-\tbne.w\t65fc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d2c>\n-\tldrd\tr0, r9, [sp, #80]\t@ 0x50\n-\tldrd\tr1, r5, [sp, #92]\t@ 0x5c\n-\tsubs\tr0, #1\n-\tldrd\tr8, ip, [sp, #56]\t@ 0x38\n-\tadd\tr5, r1\n-\tldrd\tr3, lr, [sp, #64]\t@ 0x40\n-\tadds\tr6, r0, #1\n-\tldrd\tsl, r2, [sp, #72]\t@ 0x48\n-\tldrd\tr7, r4, [sp, #100]\t@ 0x64\n-\tbne.w\t65de <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d0e>\n+\tbne.w\t6ae4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f2c>\n+\tldr\tr3, [sp, #120]\t@ 0x78\n+\tldr.w\tr8, [sp, #128]\t@ 0x80\n+\tldr\tr2, [sp, #136]\t@ 0x88\n \tsubs\tr3, #1\n-\tadd\tr2, r8\n-\tsub.w\tr7, r7, r8\n-\tadd\tr4, r8\n+\tldr.w\tfp, [sp, #88]\t@ 0x58\n \tadds\tr6, r3, #1\n-\tbne.w\t65c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1cf2>\n-\tmov\tr0, ip\n-\tcmp\tr1, #0\n-\tblt.w\t74a0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2bd0>\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tldr\tr2, [sp, #196]\t@ 0xc4\n-\tudiv\tr3, r3, r1\n+\tldr.w\tsl, [sp, #96]\t@ 0x60\n+\tadd\tr2, r8\n+\tldr.w\tr9, [sp, #104]\t@ 0x68\n+\tldr\tr4, [sp, #112]\t@ 0x70\n+\tldr\tr5, [sp, #144]\t@ 0x90\n+\tldr\tr7, [sp, #156]\t@ 0x9c\n+\tbne.w\t6ac4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f0c>\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tadd\tr4, fp\n+\tsub.w\tr5, r5, fp\n+\tadd\tr7, fp\n+\tcmp.w\tr9, #4294967295\t@ 0xffffffff\n+\tbne.w\t6a86 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ece>\n+\tmov\tr7, r8\n+\tmov\tr8, sl\n+\tcmp\tr7, #0\n+\tblt.w\t79d6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e1e>\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #428]\t@ 0x1ac\n+\tmov\tr3, r0\n \tcmp\tr2, #0\n-\tbne.w\t6c00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2330>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n+\tbne.w\t70dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2524>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n \tcmp\tr2, #0\n-\tble.w\t6c00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2330>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n+\tble.w\t70dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2524>\n+\tldr\tr2, [sp, #608]\t@ 0x260\n \tcmp\tr2, #1\n-\tbne.w\t83b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ae4>\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tvneg.f64\td23, d16\n-\tldr.w\tsl, [sp, #16]\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #120]\t@ 0x78\n+\tbne.w\t87b8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3c00>\n+\tldr.w\tsl, [sp, #152]\t@ 0x98\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tldr.w\tfp, [sp, #332]\t@ 0x14c\n \tmov\tr2, sl\n-\tmov\tfp, r4\n-\tsubs\tr5, r4, #4\n-\tstr\tr5, [sp, #56]\t@ 0x38\n-\tldr.w\tip, [sp, #88]\t@ 0x58\n-\tmov\tr8, r2\n-\tldr.w\tlr, [sp, #124]\t@ 0x7c\n-\tmovs\tr4, #1\n-\tstrd\tr0, r3, [sp, #60]\t@ 0x3c\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tstrd\tr9, r1, [sp, #68]\t@ 0x44\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #8]\n+\tldr.w\tip, [sp, #296]\t@ 0x128\n+\tmov\tr9, r2\n+\tldr.w\tlr, [sp, #336]\t@ 0x150\n+\tmovs\tr1, #1\n+\tstr.w\tr8, [sp, #88]\t@ 0x58\n+\tstr\tr1, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tstr\tr7, [sp, #104]\t@ 0x68\n+\tstr\tr2, [sp, #112]\t@ 0x70\n \tldr\tr3, [sp, #0]\n \tldr\tr2, [sp, #0]\n-\tadd.w\tr0, r3, r8\n+\tadd.w\tr0, r3, r9\n \tldr\tr3, [sp, #0]\n \tcmp\tsl, r0\n \tldr\tr4, [sp, #0]\n \tit\tgt\n \taddgt\tr0, ip\n \tldr\tr6, [sp, #0]\n \tadds\tr5, r3, r0\n \tldr\tr3, [sp, #0]\n \tcmp\tsl, r5\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tit\tgt\n \taddgt\tr5, ip\n \tadds\tr1, r3, r5\n \tldr\tr3, [sp, #0]\n \tcmp\tsl, r1\n \tit\tgt\n \taddgt\tr1, ip\n@@ -9309,14000 +10066,14685 @@\n \tit\tgt\n \taddgt\tr4, ip\n \tadd\tr6, r4\n \tcmp\tsl, r6\n \tit\tgt\n \taddgt\tr6, ip\n \tcmp\tr7, #0\n-\tble.w\t6bd2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2302>\n+\tble.w\t70ae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x24f6>\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n \tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tsubs\tr1, #1\n \tsubs\tr6, #1\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tsubs\tr3, #1\n \tsubs\tr2, #1\n \tlsls\tr7, r1, #2\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n \tlsls\tr1, r6, #2\n \tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n-\tldr\tr6, [sp, #404]\t@ 0x194\n+\tldr\tr6, [sp, #620]\t@ 0x26c\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n-\tstr\tr1, [sp, #32]\n+\tstr\tr1, [sp, #48]\t@ 0x30\n \tlsls\tr3, r3, #2\n \tlsls\tr2, r2, #2\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tstr\tr2, [sp, #28]\n+\tldr\tr1, [sp, #356]\t@ 0x164\n+\tstr\tr2, [sp, #40]\t@ 0x28\n \tsubs\tr5, #1\n \tsubs\tr4, #1\n \tsubs\tr0, #1\n-\tadd\tr6, r8\n-\tadd.w\tr9, fp, r3\n+\tadd\tr6, r9\n+\tadd.w\tr8, fp, r3\n \tadd\tr3, lr\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #28]\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tlsls\tr5, r5, #2\n \tlsls\tr4, r4, #2\n \tlsls\tr0, r0, #2\n-\tadd.w\tr2, r8, #1073741824\t@ 0x40000000\n+\tadd.w\tr2, r9, #1073741824\t@ 0x40000000\n \tadd.w\tr1, r1, r6, lsl #2\n \tsubs\tr2, #1\n-\tstr\tr1, [sp, #52]\t@ 0x34\n+\tstr\tr1, [sp, #80]\t@ 0x50\n \tadd.w\tr1, fp, r5\n-\tstr\tr1, [sp, #8]\n+\tstr\tr1, [sp, #16]\n \tadd.w\tr1, fp, r4\n-\tstr\tr1, [sp, #12]\n+\tstr\tr1, [sp, #24]\n \tadd.w\tr1, fp, r0\n-\tstr\tr1, [sp, #20]\n+\tstr\tr1, [sp, #28]\n \tadd.w\tr1, fp, r7\n-\tstr\tr1, [sp, #24]\n+\tstr\tr1, [sp, #32]\n \tadd.w\tr1, fp, r3\n-\tstr\tr1, [sp, #28]\n-\tldr\tr1, [sp, #32]\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #48]\t@ 0x30\n \tadd\tr3, lr\n \tlsls\tr2, r2, #2\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tadd.w\tr3, fp, r1\n-\tstr\tr3, [sp, #32]\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tmov\tr3, lr\n \tadd.w\tr6, fp, r2\n \tadd\tr5, lr\n \tadd\tr2, lr\n \tadd\tr4, lr\n \tadd\tr0, lr\n \tadd\tr7, lr\n \tadd\tr1, lr\n \tmov\tlr, sl\n \tmov\tsl, fp\n \tmov\tfp, r3\n-\tldr\tr3, [sp, #8]\n-\tvldr\ts7, [r2]\n-\tvldr\ts11, [r5]\n-\tvldr\ts10, [r4]\n-\tvldr\ts9, [r3]\n-\tvcvt.f64.f32\td21, s7\n-\tldr\tr3, [sp, #12]\n-\tvcvt.f64.f32\td24, s11\n-\tvldr\ts14, [r9]\n-\tvcvt.f64.f32\td25, s10\n-\tvldr\ts12, [r6]\n-\tvcvt.f64.f32\td26, s9\n-\tvldr\ts8, [r3]\n-\tvcvt.f64.f32\td19, s14\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #16]\n+\tvldr\ts2, [r5]\n+\tvldr\ts8, [r4]\n+\tvldr\ts10, [r6]\n+\tvldr\ts12, [r3]\n+\tvcvt.f64.f32\td1, s2\n+\tldr\tr3, [sp, #24]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts4, [r8]\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts16, [r2]\n \tvcvt.f64.f32\td6, s12\n-\tvsub.f64\td29, d24, d25\n-\tvadd.f64\td25, d25, d24\n-\tvcvt.f64.f32\td27, s8\n-\tvldr\ts15, [r3]\n-\tvsub.f64\td24, d6, d19\n-\tvadd.f64\td19, d19, d6\n-\tvsub.f64\td28, d26, d27\n-\tvadd.f64\td27, d27, d26\n-\tvcvt.f64.f32\td17, s15\n-\tvadd.f64\td4, d27, d19\n-\tvsub.f64\td19, d19, d27\n-\tvsub.f64\td26, d21, d17\n-\tvadd.f64\td17, d17, d21\n+\tvldr\ts6, [r3]\n+\tvcvt.f64.f32\td2, s4\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tvcvt.f64.f32\td8, s16\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts14, [r3]\n+\tvsub.f64\td0, d6, d3\n+\tvadd.f64\td3, d3, d6\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td6, d1, d4\n+\tvadd.f64\td4, d4, d1\n+\tvadd.f64\td1, d2, d5\n+\tvsub.f64\td5, d5, d2\n+\tvmul.f64\td0, d0, d14\n+\tvadd.f64\td2, d7, d8\n+\tvmul.f64\td6, d6, d14\n+\tvsub.f64\td7, d8, d7\n+\tvadd.f64\td8, d3, d1\n+\tvsub.f64\td1, d1, d3\n+\tvadd.f64\td3, d4, d2\n+\tvsub.f64\td2, d2, d4\n+\tvsub.f64\td4, d5, d6\n+\tvcvt.f32.f64\ts16, d8\n+\tvadd.f64\td6, d6, d5\n+\tvcvt.f32.f64\ts2, d1\n+\tvadd.f64\td5, d7, d0\n+\tvsub.f64\td7, d7, d0\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts4, d2\n \tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts14, d19\n-\tvmov.f64\td5, d26\n-\tvfma.f64\td26, d28, d23\n-\tvfma.f64\td5, d16, d28\n-\tvmov.f64\td28, d24\n-\tvadd.f64\td21, d25, d17\n-\tvfma.f64\td28, d29, d23\n-\tvsub.f64\td17, d17, d25\n-\tvfma.f64\td24, d16, d29\n-\tvstmia\tr6!, {s8}\n-\tvstmia\tr9!, {s14}\n-\tvcvt.f32.f64\ts9, d21\n-\tvcvt.f32.f64\ts15, d17\n+\tvstmia\tr6!, {s16}\n+\tvcvt.f32.f64\ts12, d6\n+\tvstmia\tr8!, {s2}\n \tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts11, d26\n-\tvstmia\tr2!, {s9}\n-\tvcvt.f32.f64\ts13, d28\n-\tvstmia\tr3!, {s15}\n-\tvcvt.f32.f64\ts12, d24\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #8]\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr2!, {s6}\n+\tvstmia\tr3!, {s4}\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #16]\n \tvstmia\tr5!, {s10}\n-\tvstmia\tr4!, {s11}\n-\tvstmia\tr3!, {s13}\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #12]\n-\tvldr\ts13, [r0]\n-\tvstmia\tr3!, {s12}\n-\tvcvt.f64.f32\td24, s13\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #20]\n-\tvldr\ts12, [r7]\n-\tvldr\ts15, [r3]\n-\tvcvt.f64.f32\td19, s12\n+\tvstmia\tr4!, {s14}\n+\tvldr\ts10, [r7]\n+\tvstmia\tr3!, {s8}\n+\tstr\tr3, [sp, #16]\n \tldr\tr3, [sp, #24]\n-\tvcvt.f64.f32\td26, s15\n-\tvsub.f64\td17, d24, d19\n-\tvadd.f64\td19, d19, d24\n-\tvldr\ts14, [r3]\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts4, [r0]\n+\tvstmia\tr3!, {s12}\n+\tvcvt.f64.f32\td2, s4\n+\tstr\tr3, [sp, #24]\n \tldr\tr3, [sp, #28]\n-\tvcvt.f64.f32\td22, s14\n-\tvldr\ts11, [r3]\n+\tvldr\ts2, [r3]\n \tldr\tr3, [sp, #32]\n-\tvldr\ts12, [r1]\n-\tvsub.f64\td31, d26, d22\n-\tvcvt.f64.f32\td25, s11\n-\tvadd.f64\td26, d22, d26\n-\tvldr\ts13, [r3]\n-\tvcvt.f64.f32\td27, s12\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tvsub.f64\td5, d17, d25\n-\tvcvt.f64.f32\td29, s13\n-\tvsub.f64\td24, d31, d27\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts0, [r3]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvcvt.f64.f32\td0, s0\n \tvldr\ts14, [r3]\n-\tvadd.f64\td30, d29, d25\n-\tvsub.f64\td17, d17, d29\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvldr\ts8, [r1]\n+\tvsub.f64\td8, d1, d0\n \tvcvt.f64.f32\td7, s14\n-\tvadd.f64\td5, d5, d29\n-\tvadd.f64\td4, d19, d30\n-\tvadd.f64\td17, d17, d25\n-\tvadd.f64\td21, d27, d7\n-\tvsub.f64\td19, d19, d30\n-\tvsub.f64\td22, d31, d7\n-\tvadd.f64\td24, d24, d7\n+\tvadd.f64\td9, d0, d1\n+\tvsub.f64\td0, d2, d5\n+\tvadd.f64\td5, d5, d2\n+\tvldr\ts12, [r3]\n+\tvcvt.f64.f32\td4, s8\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvcvt.f64.f32\td6, s12\n+\tvsub.f64\td11, d0, d7\n+\tvsub.f64\td10, d8, d4\n+\tvldr\ts6, [r3]\n+\tldr\tr3, [sp, #28]\n+\tvadd.f64\td1, d6, d7\n+\tvsub.f64\td0, d0, d6\n+\tvcvt.f64.f32\td3, s6\n+\tvadd.f64\td6, d11, d6\n+\tvadd.f64\td12, d5, d1\n+\tvsub.f64\td5, d5, d1\n+\tvadd.f64\td2, d4, d3\n+\tvsub.f64\td8, d8, d3\n+\tvadd.f64\td3, d10, d3\n+\tvadd.f64\td7, d0, d7\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts24, d12\n \tvcvt.f32.f64\ts10, d5\n+\tvsub.f64\td1, d9, d2\n+\tvadd.f64\td2, d2, d9\n+\tvadd.f64\td4, d8, d4\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr0!, {s24}\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts4, d2\n \tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts15, d17\n-\tvsub.f64\td25, d26, d21\n-\tvcvt.f32.f64\ts9, d19\n-\tvadd.f64\td21, d21, d26\n-\tvadd.f64\td22, d22, d27\n-\tvcvt.f32.f64\ts12, d24\n-\tvstmia\tr0!, {s8}\n-\tvcvt.f32.f64\ts11, d25\n-\tvstmia\tr1!, {s9}\n-\tvstmia\tr7!, {s10}\n-\tvcvt.f32.f64\ts14, d21\n-\tvstmia\tr3!, {s15}\n-\tvcvt.f32.f64\ts13, d22\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #20]\n-\tvstmia\tr3!, {s11}\n-\tstr\tr3, [sp, #20]\n+\tvstmia\tr1!, {s10}\n+\tvstmia\tr7!, {s12}\n+\tvstmia\tr3!, {s2}\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvstmia\tr3!, {s4}\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tldr\tr3, [sp, #32]\n-\tvstmia\tr3!, {s14}\n+\tvstmia\tr3!, {s6}\n \tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #24]\n-\tvstmia\tr3!, {s12}\n-\tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #28]\n-\tvstmia\tr3!, {s13}\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvstmia\tr3!, {s8}\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvstmia\tr3!, {s14}\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tcmp\tr6, r3\n-\tbne.w\t6a06 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2136>\n+\tbne.w\t6ee0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2328>\n \tmov\tr3, fp\n \tmov\tfp, sl\n \tmov\tsl, lr\n \tmov\tlr, r3\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr2, [sp, #4]\n-\tadd\tr8, r3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tsl, r8\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tldr\tr2, [sp, #8]\n+\tadd\tr9, r3\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp\tsl, r9\n \tadd.w\tr3, r3, #1\n \tit\tgt\n-\taddgt\tr8, ip\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\taddgt\tr9, ip\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, r2\n-\tbne.w\t691a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x204a>\n-\tldrd\tr0, r3, [sp, #60]\t@ 0x3c\n-\tldrd\tr9, r1, [sp, #68]\t@ 0x44\n+\tbne.w\t6df4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x223c>\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr7, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #112]\t@ 0x70\n \tsubs\tr3, #1\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tadds\tr7, r3, #1\n-\tadd\tr2, r1\n-\tbne.w\t6902 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2032>\n-\tldr\tr3, [sp, #400]\t@ 0x190\n+\tldr.w\tr8, [sp, #88]\t@ 0x58\n+\tadds\tr1, r3, #1\n+\tadd\tr2, r7\n+\tbne.w\t6ddc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2224>\n+\tldr\tr3, [sp, #616]\t@ 0x268\n \tcmp\tr3, #3\n-\tbeq.w\t4b16 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x246>\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr4, [sp, #144]\t@ 0x90\n-\tmov.w\tr8, r3, lsl #1\n+\tbeq.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n+\tldr\tr4, [sp, #360]\t@ 0x168\n+\tlsls\tr3, r3, #1\n \tcmp\tr4, #0\n-\tblt.w\t83a2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ad2>\n-\tsubs\tr3, r0, r4\n-\tcmp\tr4, r0\n-\tudiv\tip, r3, r4\n-\tbgt.w\t70a0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27d0>\n-\tldr\tr4, [sp, #144]\t@ 0x90\n-\tvneg.f64\td15, d16\n-\tldr\tr2, [sp, #148]\t@ 0x94\n-\tmov\tr0, r8\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tmov\tr7, r4\n-\tldr\tr6, [sp, #132]\t@ 0x84\n-\tsub.w\tlr, r4, r2\n-\tsub.w\tfp, r2, r4\n-\tmov\tsl, r2\n-\tsubs\tr3, #4\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tlsls\tr2, r0, #3\n-\tcmp\tr1, #0\n-\tadd\tr3, r2\n-\tvldr\td13, [r3, #8]\n-\tvldr\td14, [r3]\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tblt.w\t87a2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3bea>\n+\tmov\tr1, r4\n+\tsub.w\tr0, r8, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r8\n+\tmov\tsl, r0\n+\tbgt.w\t75d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a1c>\n+\tldr\tr6, [sp, #360]\t@ 0x168\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tmov\tfp, r6\n+\tldr.w\tr9, [sp, #160]\t@ 0xa0\n+\tsub.w\tr8, r6, r2\n+\tsubs\tr4, r2, r6\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #404]\t@ 0x194\n+\tmov.w\tr2, r9, lsl #3\n+\tvldr\td6, [sp, #392]\t@ 0x188\n+\tcmp\tr7, #0\n \tadd\tr3, r2\n-\tvmul.f64\td13, d0, d13\n-\tvldr\td11, [r3, #8]\n+\tvldr\td7, [r3, #8]\n \tvldr\td12, [r3]\n \tadd\tr3, r2\n-\tvmul.f64\td11, d0, d11\n-\tvldr\td9, [r3, #8]\n-\tvldr\td10, [r3]\n-\tadd\tr3, r2\n-\tvmul.f64\td9, d0, d9\n-\tvldr\td1, [r3, #8]\n-\tvldr\td8, [r3]\n-\tadd\tr3, r2\n-\tvmul.f64\td1, d0, d1\n-\tvldr\td3, [r3, #8]\n-\tvldr\td2, [r3]\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td5, [r3]\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvldr\td7, [r3, #8]\n \tadd\tr3, r2\n+\tadd.w\tr0, r3, r2\n+\tvstr\td5, [sp, #56]\t@ 0x38\n+\tadd.w\tr1, r0, r2\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvldr\td7, [r3]\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvldr\td7, [r3, #8]\n+\tadd.w\tr3, r1, r2\n \tadd\tr2, r3\n-\tvmul.f64\td3, d0, d3\n-\tvldr\td30, [r3, #8]\n-\tvldr\td31, [r2, #8]\n-\tvldr\td6, [r3]\n-\tvmul.f64\td30, d0, d30\n-\tvldr\td5, [r2]\n-\tvmul.f64\td31, d0, d31\n-\tblt.w\t77e6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f16>\n-\tudiv\tr3, fp, r1\n-\tcmp\tsl, r7\n-\tblt.w\t708a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27ba>\n-\tcmp\tr6, #0\n-\tble.w\t708a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27ba>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\tadds\tr5, r6, #1\n-\tstr\tr5, [sp, #36]\t@ 0x24\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td15, [r2, #8]\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvmul.f64\td15, d6, d15\n+\tvldr\td7, [r0, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [r0]\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvldr\td7, [r1, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td7, [r1]\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvldr\td7, [r3, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tvldr\td7, [r3]\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvldr\td7, [r2]\n+\tvstr\td7, [sp, #136]\t@ 0x88\n+\tblt.w\t79c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e0a>\n+\tmov\tr1, r7\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, fp\n+\tblt.w\t75be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a06>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tcmp\tr2, #0\n+\tble.w\t75be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a06>\n+\tldr\tr2, [sp, #608]\t@ 0x260\n+\tldr\tr1, [sp, #344]\t@ 0x158\n \tcmp\tr2, #1\n-\tldr\tr2, [sp, #16]\n-\tadd\tr2, r7\n-\tbne.w\t70b6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27e6>\n-\tmovs\tr5, #1\n-\tstr\tr2, [sp, #20]\n-\tstrd\tr5, r6, [sp, #40]\t@ 0x28\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tstrd\tr3, ip, [sp, #60]\t@ 0x3c\n-\tstrd\tr8, r0, [sp, #68]\t@ 0x44\n-\tstrd\tr7, sl, [sp, #76]\t@ 0x4c\n-\tstr.w\tr9, [sp, #84]\t@ 0x54\n-\tstrd\tr1, r2, [sp, #92]\t@ 0x5c\n-\tstrd\tlr, fp, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tadd.w\tr1, r1, #1\n+\tstr\tr1, [sp, #156]\t@ 0x9c\n+\tadd\tr2, fp\n+\tbne.w\t75f2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a3a>\n+\tmovs\tr1, #1\n+\tstr\tr2, [sp, #28]\n+\tstr\tr1, [sp, #164]\t@ 0xa4\n+\tstrd\tr6, r3, [sp, #176]\t@ 0xb0\n+\tstr.w\tsl, [sp, #184]\t@ 0xb8\n+\tstrd\tr9, fp, [sp, #192]\t@ 0xc0\n+\tstrd\tr7, r2, [sp, #200]\t@ 0xc8\n+\tstr.w\tr8, [sp, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #216]\t@ 0xd8\n \tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #28]\n+\tldr\tr4, [sp, #152]\t@ 0x98\n \tadds\tr0, r3, r2\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr3, r0\n-\tble.n\t6cfe <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x242e>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr0, r3\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tldr\tr7, [sp, #152]\t@ 0x98\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r3\n \tldr\tr3, [sp, #0]\n \tadds\tr5, r3, r0\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r5\n-\tble.n\t6d0c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x243c>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r3\n \tldr\tr3, [sp, #0]\n \tadds\tr1, r3, r5\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr3, r1\n-\tble.n\t6d1a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x244a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr1, r3\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r3\n \tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #16]\n \tadd\tr3, r1\n \tcmp\tr2, r3\n-\tble.n\t6d28 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2458>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n \tldr\tr2, [sp, #0]\n-\tldr\tr4, [sp, #16]\n \tadd\tr2, r3\n \tcmp\tr4, r2\n-\tble.n\t6d36 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2466>\n-\tldr\tr4, [sp, #88]\t@ 0x58\n-\tadd\tr2, r4\n+\titt\tgt\n+\tldrgt\tr4, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r4\n \tldr\tr4, [sp, #0]\n-\tldr\tr6, [sp, #16]\n \tadd\tr4, r2\n \tcmp\tr6, r4\n-\tble.n\t6d44 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2474>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tadd\tr4, r6\n+\titt\tgt\n+\tldrgt\tr6, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r6\n \tldr\tr6, [sp, #0]\n-\tldr\tr7, [sp, #16]\n \tadd\tr6, r4\n \tcmp\tr7, r6\n-\tble.n\t6d52 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2482>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\titt\tgt\n+\tldrgt\tr7, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tcmp\tr7, #0\n-\tble.w\t7042 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2772>\n+\tble.w\t757c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x29c4>\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n \tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tsubs\tr1, #1\n \tsubs\tr6, #1\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n-\tldr\tr7, [sp, #20]\n+\tldr\tr7, [sp, #28]\n \tmov.w\tip, r1, lsl #2\n \tsubs\tr2, #1\n \tlsls\tr1, r6, #2\n-\tldr\tr6, [sp, #404]\t@ 0x194\n+\tldr\tr6, [sp, #620]\t@ 0x26c\n \tlsls\tr2, r2, #2\n-\tstr\tr2, [sp, #4]\n+\tstr\tr2, [sp, #8]\n \tadd\tr6, r7\n \tadd.w\tr2, r7, #1073741824\t@ 0x40000000\n-\tldr\tr7, [sp, #56]\t@ 0x38\n+\tldr\tr7, [sp, #356]\t@ 0x164\n \tsubs\tr2, #1\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n \tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n \tadd.w\tr7, r7, r6, lsl #2\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tlsls\tr2, r2, #2\n \tsubs\tr3, #1\n \tsubs\tr5, #1\n \tsubs\tr4, #1\n \tsubs\tr0, #1\n-\tstr\tr7, [sp, #32]\n+\tstr\tr7, [sp, #144]\t@ 0x90\n \tadds\tr7, r6, r2\n-\tstr\tr7, [sp, #12]\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n+\tstr\tr7, [sp, #24]\n+\tldr\tr7, [sp, #336]\t@ 0x150\n \tlsls\tr4, r4, #2\n \tlsls\tr0, r0, #2\n \tlsls\tr3, r3, #2\n \tlsls\tr5, r5, #2\n \tadd.w\tfp, r6, r3\n \tadd.w\tsl, r6, r5\n \tadd.w\tr9, r6, r4\n \tadds\tr5, r7, r5\n \tadd.w\tr8, r6, r0\n \tadd.w\tlr, r6, ip\n-\tstr\tr5, [sp, #24]\n+\tstr\tr5, [sp, #32]\n \tadds\tr5, r7, r4\n \tadds\tr4, r7, r0\n \tmov\tr0, r6\n-\tldr\tr6, [sp, #4]\n+\tldr\tr6, [sp, #8]\n \tadd\tr3, r7\n \tadd\tr2, r7\n \tadd\tr0, r6\n \tadd\tip, r7\n-\tstr\tr0, [sp, #4]\n+\tstr\tr0, [sp, #8]\n \tadds\tr0, r7, r6\n-\tldr\tr7, [sp, #120]\t@ 0x78\n-\tvstr\td0, [sp, #112]\t@ 0x70\n+\tldr\tr7, [sp, #332]\t@ 0x14c\n \tadds\tr6, r7, r1\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n-\tstr\tr6, [sp, #8]\n-\tldr\tr6, [sp, #24]\n+\tldr\tr7, [sp, #336]\t@ 0x150\n+\tstr\tr6, [sp, #16]\n+\tldr\tr6, [sp, #32]\n \tadd\tr1, r7\n-\tldr\tr7, [sp, #12]\n-\tstr\tr3, [sp, #12]\n-\tvldr\ts15, [r9]\n-\tldr\tr3, [sp, #12]\n-\tvldr\ts14, [sl]\n-\tvcvt.f64.f32\td19, s15\n-\tvldr\ts15, [r2]\n-\tvldr\ts9, [r6]\n-\tvldr\ts8, [r5]\n-\tvcvt.f64.f32\td26, s14\n-\tvcvt.f64.f32\td23, s15\n-\tvldr\ts15, [r3]\n+\tldr\tr7, [sp, #24]\n+\tstr\tr3, [sp, #24]\n+\tvldr\ts15, [r6]\n+\tvldr\ts2, [sl]\n+\tvldr\ts0, [r9]\n+\tvldr\ts12, [r5]\n+\tvcvt.f64.f32\td8, s15\n+\tldr\tr3, [sp, #24]\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts6, [r2]\n+\tvcvt.f64.f32\td6, s12\n \tvldr\ts14, [r7]\n-\tvcvt.f64.f32\td27, s9\n-\tvldr\ts9, [fp]\n-\tvcvt.f64.f32\td22, s8\n-\tvcvt.f64.f32\td21, s15\n-\tvsub.f64\td25, d26, d19\n+\tvldr\ts4, [fp]\n+\tvldr\ts10, [r3]\n+\tvcvt.f64.f32\td3, s6\n+\tvadd.f64\td9, d0, d1\n+\tvsub.f64\td4, d1, d0\n+\tvcvt.f64.f32\td2, s4\n+\tvsub.f64\td1, d8, d6\n+\tvcvt.f64.f32\td5, s10\n \tvcvt.f64.f32\td7, s14\n-\tvadd.f64\td19, d19, d26\n-\tvcvt.f64.f32\td17, s9\n-\tvsub.f64\td26, d27, d22\n-\tvadd.f64\td22, d22, d27\n-\tvsub.f64\td27, d23, d21\n-\tvsub.f64\td29, d21, d23\n-\tvadd.f64\td21, d21, d23\n-\tvfma.f64\td29, d16, d25\n-\tvsub.f64\td23, d7, d17\n-\tvadd.f64\td17, d17, d7\n-\tvmov.f64\td28, d27\n-\tvfma.f64\td27, d25, d15\n-\tvfma.f64\td28, d16, d25\n-\tvsub.f64\td24, d22, d21\n-\tvmov.f64\td25, d23\n-\tvfma.f64\td23, d16, d26\n-\tvfma.f64\td25, d26, d15\n-\tvadd.f64\td4, d22, d21\n-\tvsub.f64\td26, d21, d22\n-\tvadd.f64\td7, d19, d17\n-\tvsub.f64\td21, d17, d19\n-\tvmul.f64\td17, d24, d1\n-\tvmul.f64\td19, d26, d8\n-\tvmul.f64\td26, d30, d29\n-\tvmul.f64\td24, d12, d28\n-\tvcvt.f32.f64\ts15, d7\n-\tvfma.f64\td19, d1, d21\n-\tvfma.f64\td26, d6, d23\n-\tvfma.f64\td24, d11, d25\n-\tvnmul.f64\td22, d28, d11\n-\tvmul.f64\td27, d6, d27\n-\tvfma.f64\td17, d8, d21\n-\tvstmia\tr7!, {s15}\n-\tvfma.f64\td22, d12, d25\n-\tvfma.f64\td27, d30, d23\n-\tvcvt.f32.f64\ts14, d4\n-\tvcvt.f32.f64\ts9, d19\n-\tvcvt.f32.f64\ts15, d24\n-\tvstmia\tr2!, {s14}\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts8, d22\n-\tvstmia\tr3!, {s9}\n-\tvmov.f32\ts0, s15\n-\tvcvt.f32.f64\ts15, d26\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #4]\n-\tvstmia\tfp!, {s14}\n-\tvmov.f32\ts1, s15\n-\tvcvt.f32.f64\ts15, d27\n-\tvstmia\tsl!, {s8}\n-\tvstmia\tr6!, {s0}\n-\tvstmia\tr9!, {s1}\n-\tvstmia\tr5!, {s15}\n-\tvldr\ts15, [r3]\n-\tldr\tr3, [sp, #8]\n-\tvldr\ts9, [ip]\n-\tvldr\ts8, [r4]\n-\tvmov.f32\ts1, s15\n-\tvldr\ts14, [r8]\n-\tvldr\ts0, [r3]\n-\tvcvt.f64.f32\td26, s9\n-\tvldr\ts15, [lr]\n-\tvcvt.f64.f32\td21, s8\n-\tvcvt.f64.f32\td25, s1\n-\tvcvt.f64.f32\td27, s14\n-\tvcvt.f64.f32\td24, s0\n-\tvldr\ts14, [r1]\n-\tvcvt.f64.f32\td17, s15\n-\tvldr\ts15, [r0]\n-\tvsub.f64\td4, d21, d26\n-\tvadd.f64\td29, d26, d21\n-\tvcvt.f64.f32\td23, s14\n-\tvsub.f64\td22, d25, d24\n-\tvcvt.f64.f32\td19, s15\n-\tvsub.f64\td7, d27, d17\n-\tvadd.f64\td28, d24, d25\n-\tvsub.f64\td25, d4, d25\n-\tvadd.f64\td17, d17, d27\n-\tvsub.f64\td21, d22, d21\n-\tvadd.f64\td22, d4, d22\n-\tvsub.f64\td27, d7, d19\n-\tvsub.f64\td7, d7, d23\n-\tvadd.f64\td24, d25, d24\n-\tvadd.f64\td26, d21, d26\n-\tvnmul.f64\td25, d22, d3\n-\tvadd.f64\td21, d7, d19\n-\tvadd.f64\td19, d23, d19\n-\tvadd.f64\td23, d27, d23\n-\tvmul.f64\td27, d2, d22\n-\tvmul.f64\td22, d24, d10\n-\tvsub.f64\td24, d29, d28\n-\tvmul.f64\td26, d26, d9\n-\tvfma.f64\td22, d9, d21\n-\tvfma.f64\td26, d10, d21\n-\tvfma.f64\td25, d2, d23\n-\tvfma.f64\td27, d3, d23\n-\tvadd.f64\td21, d29, d28\n-\tvsub.f64\td23, d28, d29\n-\tvmul.f64\td24, d24, d5\n-\tvmul.f64\td23, d23, d31\n-\tvcvt.f32.f64\ts0, d22\n-\tvadd.f64\td22, d19, d17\n-\tvsub.f64\td17, d17, d19\n-\tvnmul.f64\td19, d21, d13\n-\tvmul.f64\td21, d14, d21\n-\tvcvt.f32.f64\ts14, d27\n-\tvcvt.f32.f64\ts15, d25\n-\tvcvt.f32.f64\ts1, d26\n-\tvfma.f64\td23, d5, d22\n-\tvfma.f64\td24, d31, d22\n-\tvfma.f64\td19, d14, d17\n-\tvfma.f64\td21, d13, d17\n-\tvstr\ts14, [sp, #28]\n-\tvstr\ts15, [sp, #24]\n-\tvcvt.f32.f64\ts8, d23\n-\tvcvt.f32.f64\ts15, d24\n-\tvcvt.f32.f64\ts14, d19\n-\tvcvt.f32.f64\ts9, d21\n-\tvstmia\tr8!, {s14}\n-\tvstmia\tr4!, {s9}\n+\tvadd.f64\td6, d6, d8\n+\tvmul.f64\td4, d4, d14\n+\tvmul.f64\td8, d1, d14\n+\tvsub.f64\td11, d3, d5\n+\tvadd.f64\td1, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvadd.f64\td2, d5, d3\n+\tvsub.f64\td5, d5, d3\n+\tvadd.f64\td3, d8, d7\n+\tvsub.f64\td7, d7, d8\n+\tvadd.f64\td10, d5, d4\n+\tvadd.f64\td5, d11, d4\n+\tvsub.f64\td11, d11, d4\n+\tvsub.f64\td4, d1, d9\n+\tvadd.f64\td9, d9, d1\n+\tvldr\td8, [sp, #64]\t@ 0x40\n+\tvsub.f64\td0, d6, d2\n+\tvmul.f64\td1, d8, d5\n+\tvcvt.f32.f64\ts18, d9\n+\tvstmia\tr7!, {s18}\n+\tvldr\td9, [sp, #56]\t@ 0x38\n+\tvnmls.f64\td1, d9, d7\n+\tvmul.f64\td7, d8, d7\n+\tvmla.f64\td7, d9, d5\n+\tvsub.f64\td5, d2, d6\n+\tvadd.f64\td6, d6, d2\n+\tvldr\td2, [sp, #88]\t@ 0x58\n+\tvldr\td8, [sp, #96]\t@ 0x60\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr2!, {s12}\n+\tvmul.f64\td6, d2, d4\n+\tvmla.f64\td6, d0, d8\n+\tvmul.f64\td4, d8, d4\n+\tvmla.f64\td4, d5, d2\n+\tvldr\td5, [sp, #128]\t@ 0x80\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tfp!, {s12}\n+\tvldr\td6, [sp, #120]\t@ 0x78\n \tvstmia\tr3!, {s8}\n+\tvstmia\tr6!, {s14}\n+\tvmul.f64\td7, d6, d3\n+\tvmul.f64\td3, d5, d3\n+\tvmla.f64\td7, d10, d5\n+\tvmla.f64\td3, d11, d6\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #8]\n+\tvstmia\tsl!, {s2}\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts6, d3\n+\tvstmia\tr9!, {s14}\n+\tvldr\ts10, [r3]\n+\tldr\tr3, [sp, #16]\n+\tvldr\ts8, [r8]\n+\tvldr\ts0, [lr]\n+\tvcvt.f64.f32\td5, s10\n+\tvstmia\tr5!, {s6}\n+\tvldr\ts12, [r3]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts7, [ip]\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts14, [r4]\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts6, [r0]\n+\tvcvt.f64.f32\td1, s7\n+\tvldr\ts16, [r1]\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td10, d4, d0\n+\tvadd.f64\td11, d0, d4\n+\tvcvt.f64.f32\td2, s6\n+\tvsub.f64\td0, d5, d6\n+\tvcvt.f64.f32\td3, s16\n+\tvadd.f64\td9, d6, d5\n+\tvsub.f64\td4, d7, d1\n+\tvadd.f64\td8, d1, d7\n+\tvsub.f64\td7, d0, d7\n+\tvadd.f64\td0, d4, d0\n+\tvsub.f64\td4, d4, d5\n+\tvadd.f64\td5, d8, d9\n+\tvadd.f64\td7, d7, d1\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvadd.f64\td6, d4, d6\n+\tvsub.f64\td4, d10, d3\n+\tvsub.f64\td10, d10, d2\n+\tvstr\td7, [sp, #32]\n+\tvadd.f64\td7, d3, d2\n+\tvadd.f64\td4, d4, d2\n+\tvmul.f64\td2, d1, d0\n+\tvadd.f64\td10, d10, d3\n+\tvsub.f64\td3, d9, d8\n+\tvsub.f64\td8, d8, d9\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvsub.f64\td6, d11, d7\n+\tvadd.f64\td7, d7, d11\n+\tvnmls.f64\td2, d9, d10\n+\tvmul.f64\td10, d1, d10\n+\tvmla.f64\td10, d9, d0\n+\tvldr\td0, [sp, #48]\t@ 0x30\n+\tvmul.f64\td1, d0, d5\n+\tvnmls.f64\td1, d12, d6\n+\tvmul.f64\td6, d0, d6\n+\tvmla.f64\td6, d12, d5\n+\tvldr\td5, [sp, #136]\t@ 0x88\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts20, d10\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts12, d6\n+\tvstmia\tr8!, {s2}\n+\tvstmia\tr4!, {s12}\n+\tvmul.f64\td6, d5, d7\n+\tvmla.f64\td6, d3, d15\n+\tvmul.f64\td7, d15, d7\n+\tvmla.f64\td7, d8, d5\n+\tvldr\td3, [sp, #32]\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr3!, {s12}\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvstmia\tr1!, {s14}\n+\tstr\tr3, [sp, #16]\n+\tvmul.f64\td7, d6, d4\n+\tvmul.f64\td4, d5, d4\n+\tvmla.f64\td7, d3, d5\n+\tldr\tr3, [sp, #8]\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tlr!, {s14}\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvstmia\tr3!, {s4}\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #4]\n-\tvstmia\tr1!, {s15}\n-\tvldr\ts15, [sp, #24]\n-\tvldr\ts14, [sp, #28]\n-\tvstmia\tlr!, {s1}\n-\tvstmia\tr3!, {s15}\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #32]\n-\tvstmia\tip!, {s0}\n+\tvmla.f64\td4, d7, d6\n+\tldr\tr3, [sp, #144]\t@ 0x90\n \tcmp\tr7, r3\n-\tvstmia\tr0!, {s14}\n-\tbne.w\t6df4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2524>\n-\tvldr\td0, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #20]\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tip!, {s8}\n+\tvstmia\tr0!, {s20}\n+\tbne.w\t730e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2756>\n+\tldr\tr3, [sp, #28]\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #20]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #28]\n \tcmp\tr2, r3\n-\tble.n\t7056 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2786>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tittt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n+\tstrgt\tr3, [sp, #28]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n \tcmp\tr3, r2\n-\tbne.w\t6cee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x241e>\n-\tldrd\tr3, ip, [sp, #60]\t@ 0x3c\n-\tldrd\tr1, r2, [sp, #92]\t@ 0x5c\n+\tbne.w\t720c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2654>\n+\tldrd\tr6, r3, [sp, #176]\t@ 0xb0\n+\tldrd\tr7, r2, [sp, #200]\t@ 0xc8\n \tsubs\tr3, #1\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tldr.w\tsl, [sp, #184]\t@ 0xb8\n \tadds\tr5, r3, #1\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tadd\tr2, r1\n-\tldrd\tr8, r0, [sp, #68]\t@ 0x44\n-\tldrd\tr7, sl, [sp, #76]\t@ 0x4c\n-\tldr.w\tr9, [sp, #84]\t@ 0x54\n-\tldrd\tlr, fp, [sp, #100]\t@ 0x64\n-\tbne.w\t6ccc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23fc>\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd\tr0, r8\n-\tadd\tr7, r4\n-\tadd\tlr, r4\n-\tsub.w\tfp, fp, r4\n-\tcmp.w\tip, #4294967295\t@ 0xffffffff\n-\tbne.w\t6c40 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2370>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tb.w\t4dde <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x50e>\n-\tudiv\tr0, r4, lr\n-\tcmp\tsl, r2\n-\tble.w\t65d2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1d02>\n-\tb.w\t68b4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1fe4>\n-\tldr\tr5, [sp, #404]\t@ 0x194\n-\tstr.w\tr8, [sp, #60]\t@ 0x3c\n-\tldr.w\tr8, [sp, #172]\t@ 0xac\n-\tadds\tr5, #1\n-\tstr\tr5, [sp, #52]\t@ 0x34\n-\tldr\tr5, [sp, #164]\t@ 0xa4\n-\tstr\tr2, [sp, #4]\n-\tstr\tr5, [sp, #32]\n-\tstrd\tr6, r4, [sp, #64]\t@ 0x40\n-\tstrd\tr3, ip, [sp, #72]\t@ 0x48\n-\tstrd\tr0, r7, [sp, #80]\t@ 0x50\n-\tstrd\tsl, r9, [sp, #92]\t@ 0x5c\n-\tstrd\tr1, r2, [sp, #100]\t@ 0x64\n-\tstr.w\tlr, [sp, #112]\t@ 0x70\n-\tstr.w\tfp, [sp, #128]\t@ 0x80\n-\tldrd\tr3, r2, [sp]\n+\tldrd\tr9, fp, [sp, #192]\t@ 0xc0\n+\tadd\tr2, r7\n+\tldr.w\tr8, [sp, #208]\t@ 0xd0\n+\tldr\tr4, [sp, #216]\t@ 0xd8\n+\tbne.w\t71f0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2638>\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tadd\tfp, r6\n+\tadd\tr8, r6\n+\tadd\tr9, r3\n+\tsubs\tr4, r4, r6\n+\tcmp.w\tsl, #4294967295\t@ 0xffffffff\n+\tbne.w\t711a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2562>\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n+\tb.w\t4f5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a2>\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tble.w\t6ab8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1f00>\n+\tb.w\t6d8c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21d4>\n+\tstr.w\tr8, [sp, #176]\t@ 0xb0\n+\tldr.w\tr8, [sp, #380]\t@ 0x17c\n+\tldr\tr1, [sp, #376]\t@ 0x178\n+\tstr\tr2, [sp, #8]\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tstrd\tr6, r3, [sp, #180]\t@ 0xb4\n+\tstrd\tsl, r9, [sp, #192]\t@ 0xc0\n+\tstrd\tfp, r7, [sp, #200]\t@ 0xc8\n+\tstr\tr2, [sp, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #216]\t@ 0xd8\n+\tldr\tr2, [sp, #8]\n+\tldr\tr3, [sp, #0]\n+\tldr\tr6, [sp, #152]\t@ 0x98\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tldr\tr7, [sp, #152]\t@ 0x98\n \tcmp\tr2, r3\n-\tble.n\t70f6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2826>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr1, r2, r3\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r1\n-\tble.n\t7104 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2834>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr1, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr5, r2, r1\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r5\n-\tble.n\t7112 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2842>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr5, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr0, r2, r5\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r0\n-\tble.n\t7120 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2850>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr0, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr0, r0, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr4, r2, r0\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr2, r4\n-\tble.n\t712e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x285e>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr4, r2\n+\titt\tgt\n+\tldrgt\tr2, [sp, #296]\t@ 0x128\n+\taddgt\tr4, r4, r2\n \tldr\tr2, [sp, #0]\n-\tldr\tr6, [sp, #16]\n \tadd\tr2, r4\n \tcmp\tr6, r2\n-\tble.n\t713c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x286c>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tadd\tr2, r6\n+\titt\tgt\n+\tldrgt\tr6, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r6\n \tldr\tr6, [sp, #0]\n-\tldr\tr7, [sp, #16]\n \tadd\tr6, r2\n \tcmp\tr7, r6\n-\tble.n\t714a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x287a>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\titt\tgt\n+\tldrgt\tr7, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r7\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tcmp\tr7, #0\n-\tble.w\t743e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2b6e>\n+\tble.w\t7980 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2dc8>\n \tlsls\tr4, r4, #2\n-\tstr\tr4, [sp, #8]\n+\tstr\tr4, [sp, #16]\n \tlsls\tr4, r6, #2\n-\tldr\tr6, [sp, #4]\n-\tldr\tr7, [sp, #120]\t@ 0x78\n+\tldr\tr6, [sp, #8]\n+\tldr\tr7, [sp, #332]\t@ 0x14c\n \tlsls\tr3, r3, #2\n-\tstr\tr4, [sp, #20]\n+\tstr\tr4, [sp, #24]\n \tlsls\tr0, r0, #2\n-\tldr\tr4, [sp, #124]\t@ 0x7c\n+\tldr\tr4, [sp, #336]\t@ 0x150\n \tlsls\tr6, r6, #2\n \tadd.w\tfp, r7, r6\n \tadd.w\tip, r7, r3\n \tadd\tr6, r4\n-\tstr\tr6, [sp, #24]\n+\tstr\tr6, [sp, #164]\t@ 0xa4\n \tadds\tr6, r3, r4\n-\tldr\tr3, [sp, #8]\n-\tstr\tr6, [sp, #12]\n+\tldr\tr3, [sp, #16]\n+\tstr\tr6, [sp, #32]\n \tmov\tr6, r7\n \tadds\tr3, r6, r3\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #8]\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #16]\n \tlsls\tr1, r1, #2\n \tlsls\tr2, r2, #2\n \tlsls\tr5, r5, #2\n \tadd\tr3, r4\n \tadd.w\tsl, r7, r0\n \tadd.w\tr9, r7, r1\n \tadd.w\tlr, r7, r2\n \tadd\tr0, r4\n \tadd\tr2, r4\n \tadd\tr1, r4\n \tadd\tr7, r5\n \tadd\tr5, r4\n \tmov\tr4, r3\n-\tldr\tr3, [sp, #20]\n-\tvstr\td0, [sp, #136]\t@ 0x88\n+\tldr\tr3, [sp, #24]\n \tadds\tr3, r6, r3\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #20]\n+\tldr\tr6, [sp, #336]\t@ 0x150\n+\tstr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #24]\n \tadds\tr3, r6, r3\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tldr\tr6, [sp, #24]\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #376]\t@ 0x178\n+\tldr\tr6, [sp, #164]\t@ 0xa4\n \tstr\tr3, [sp, #28]\n-\tstr\tr2, [sp, #24]\n-\tvldr\ts1, [lr, #-4]\n-\tldr\tr2, [sp, #24]\n-\tvldr\ts9, [r1, #-4]\n-\tvcvt.f64.f32\td29, s1\n-\tvldr\ts1, [r6, #-4]\n-\tvldr\ts14, [r9, #-4]\n-\tvldr\ts8, [r2, #-4]\n-\tvcvt.f64.f32\td24, s9\n-\tvcvt.f64.f32\td17, s1\n-\tvldr\ts1, [r0, #-4]\n-\tvcvt.f64.f32\td7, s14\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n \tldr\tr3, [sp, #28]\n-\tvcvt.f64.f32\td4, s8\n-\tvcvt.f64.f32\td19, s1\n-\tvldr\ts1, [fp, #-4]\n+\tvldr\ts0, [r9, #-4]\n+\tvldr\ts2, [lr, #-4]\n \tadds\tr3, #1\n \tstr\tr3, [sp, #28]\n-\tvsub.f64\td21, d7, d29\n-\tvadd.f64\td29, d7, d29\n-\tvcvt.f64.f32\td27, s1\n-\tvldr\ts1, [sl, #-4]\n-\tvadd.f64\td22, d24, d4\n-\tvsub.f64\td26, d24, d4\n-\tvsub.f64\td4, d17, d19\n-\tvsub.f64\td7, d19, d17\n-\tvcvt.f64.f32\td28, s1\n-\tvadd.f64\td17, d17, d19\n-\tvfma.f64\td7, d16, d21\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tvmov.f64\td24, d4\n-\tvfma.f64\td4, d21, d15\n-\tvsub.f64\td19, d27, d28\n-\tvfma.f64\td24, d16, d21\n-\tvadd.f64\td27, d27, d28\n-\tvsub.f64\td25, d22, d17\n-\tvadd.f64\td28, d17, d22\n-\tvmov.f64\td21, d19\n-\tvfma.f64\td19, d16, d26\n-\tvfma.f64\td21, d26, d15\n-\tvsub.f64\td26, d17, d22\n-\tvsub.f64\td17, d27, d29\n-\tvadd.f64\td29, d27, d29\n-\tvmul.f64\td27, d6, d4\n-\tvmul.f64\td22, d26, d8\n-\tvmul.f64\td26, d30, d7\n-\tvfma.f64\td22, d1, d17\n-\tvcvt.f32.f64\ts15, d29\n-\tvcvt.f32.f64\ts14, d28\n-\tvmov.f64\td23, d19\n-\tvmul.f64\td19, d25, d1\n-\tvnmul.f64\td25, d24, d11\n-\tvmul.f64\td24, d12, d24\n-\tvfma.f64\td24, d11, d21\n-\tvfma.f64\td19, d8, d17\n-\tvfma.f64\td25, d12, d21\n-\tvstr\ts15, [fp, #-4]\n-\tvfma.f64\td27, d30, d23\n-\tvfma.f64\td26, d6, d23\n-\tvstr\ts14, [r6, #-4]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tvcvt.f64.f32\td0, s0\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts11, [sl, #-4]\n+\tvldr\ts4, [r1, #-4]\n+\tvldr\ts8, [r6, #-4]\n+\tvldr\ts14, [r3, #-4]\n+\tvcvt.f64.f32\td8, s11\n+\tvldr\ts12, [r0, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts6, [fp, #-4]\n+\tvcvt.f64.f32\td4, s8\n+\tvsub.f64\td5, d0, d1\n+\tvcvt.f64.f32\td7, s14\n+\tvcvt.f64.f32\td6, s12\n+\tvadd.f64\td0, d0, d1\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\td1, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #16]\n+\tvmul.f64\td5, d5, d14\n+\tvsub.f64\td9, d2, d7\n+\tvsub.f64\td11, d4, d6\n+\tvadd.f64\td7, d2, d7\n+\tvadd.f64\td2, d3, d8\n+\tvsub.f64\td8, d3, d8\n+\tvadd.f64\td3, d4, d6\n+\tvsub.f64\td6, d6, d4\n+\tvmul.f64\td9, d9, d14\n+\tvadd.f64\td10, d6, d5\n+\tvadd.f64\td6, d5, d11\n+\tvsub.f64\td11, d11, d5\n+\tvsub.f64\td5, d2, d0\n+\tvadd.f64\td2, d2, d0\n+\tvadd.f64\td4, d8, d9\n+\tvsub.f64\td8, d8, d9\n+\tvldr\td9, [sp, #56]\t@ 0x38\n+\tvsub.f64\td0, d7, d3\n+\tvcvt.f32.f64\ts4, d2\n+\tvstr\ts4, [fp, #-4]\n+\tvmul.f64\td2, d1, d6\n+\tvmul.f64\td6, d9, d6\n \tadd\tfp, r8\n+\tvmla.f64\td6, d1, d8\n+\tvsub.f64\td1, d3, d7\n+\tvadd.f64\td3, d3, d7\n+\tvnmls.f64\td2, d9, d8\n+\tvldr\td8, [sp, #96]\t@ 0x60\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts6, [r6, #-4]\n \tadd\tr6, r8\n-\tvcvt.f32.f64\ts9, d22\n-\tvcvt.f32.f64\ts1, d24\n-\tvcvt.f32.f64\ts14, d19\n-\tvstr\ts9, [r0, #-4]\n-\tvcvt.f32.f64\ts8, d25\n-\tvcvt.f32.f64\ts15, d27\n-\tvcvt.f32.f64\ts0, d26\n-\tadd\tr0, r8\n-\tvstr\ts1, [r1, #-4]\n-\tadd\tr1, r8\n+\tvldr\td3, [sp, #88]\t@ 0x58\n+\tvcvt.f32.f64\ts4, d2\n+\tvmul.f64\td7, d3, d5\n+\tvmla.f64\td7, d0, d8\n+\tvcvt.f32.f64\ts14, d7\n \tvstr\ts14, [sl, #-4]\n+\tvmul.f64\td7, d8, d5\n+\tvmla.f64\td7, d1, d3\n+\tvldr\td5, [sp, #128]\t@ 0x80\n+\tvstr\ts4, [r9, #-4]\n \tadd\tsl, r8\n-\tvstr\ts15, [r2, #-4]\n-\tldr\tr2, [sp, #8]\n-\tvstr\ts8, [r9, #-4]\n \tadd\tr9, r8\n-\tvstr\ts0, [lr, #-4]\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r0, #-4]\n+\tadd\tr0, r8\n+\tvstr\ts12, [r1, #-4]\n+\tadd\tr1, r8\n+\tvldr\td6, [sp, #120]\t@ 0x78\n+\tvmul.f64\td7, d6, d4\n+\tvmla.f64\td7, d10, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [lr, #-4]\n+\tvmul.f64\td7, d5, d4\n+\tvmla.f64\td7, d11, d6\n+\tvldr\ts0, [ip, #-4]\n+\tvldr\ts2, [r7, #-4]\n \tadd\tlr, r8\n-\tvldr\ts1, [r3, #-4]\n-\tvldr\ts0, [r2, #-4]\n-\tldr\tr2, [sp, #12]\n-\tvcvt.f64.f32\td21, s1\n-\tvldr\ts9, [r5, #-4]\n-\tvcvt.f64.f32\td22, s0\n-\tvldr\ts14, [ip, #-4]\n-\tvldr\ts15, [r7, #-4]\n \tvldr\ts8, [r2, #-4]\n-\tvcvt.f64.f32\td19, s9\n-\tldr\tr2, [sp, #20]\n-\tvcvt.f64.f32\td27, s14\n-\tvcvt.f64.f32\td28, s15\n-\tvldr\ts0, [r4, #-4]\n-\tvcvt.f64.f32\td17, s8\n-\tvsub.f64\td4, d21, d22\n-\tvadd.f64\td26, d21, d22\n-\tvldr\ts1, [r2, #-4]\n-\tvcvt.f64.f32\td23, s0\n-\tvsub.f64\td29, d27, d28\n-\tvadd.f64\td27, d27, d28\n-\tvadd.f64\td25, d17, d19\n-\tvsub.f64\td7, d17, d19\n-\tvsub.f64\td17, d4, d17\n-\tvcvt.f64.f32\td24, s1\n+\tvcvt.f64.f32\td0, s0\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f32.f64\ts14, d7\n+\tvsub.f64\td10, d0, d1\n+\tvadd.f64\td11, d0, d1\n+\tvstr\ts14, [r3, #-4]\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvldr\ts6, [r3, #-4]\n+\tldr\tr2, [sp, #32]\n+\tvldr\ts4, [r5, #-4]\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts10, [r4, #-4]\n+\tvldr\ts14, [r2, #-4]\n+\tvcvt.f64.f32\td2, s4\n \tldr\tr2, [sp, #24]\n-\tvadd.f64\td4, d4, d7\n+\tvcvt.f64.f32\td5, s10\n+\tvsub.f64\td8, d3, d4\n+\tvadd.f64\td1, d3, d4\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts12, [r2, #-4]\n+\tldr\tr2, [sp, #32]\n+\tvadd.f64\td0, d7, d2\n+\tvsub.f64\td9, d7, d2\n+\tvsub.f64\td7, d8, d7\n+\tvcvt.f64.f32\td6, s12\n+\tvadd.f64\td7, d7, d2\n+\tvadd.f64\td2, d8, d9\n+\tvsub.f64\td9, d9, d3\n+\tvldr\td8, [sp, #104]\t@ 0x68\n+\tvstr\td7, [sp, #144]\t@ 0x90\n+\tvadd.f64\td7, d5, d6\n+\tvadd.f64\td9, d9, d4\n+\tvsub.f64\td4, d10, d6\n+\tvsub.f64\td10, d10, d5\n+\tvadd.f64\td4, d4, d5\n+\tvadd.f64\td5, d1, d0\n+\tvadd.f64\td10, d10, d6\n+\tvadd.f64\td6, d11, d7\n+\tvsub.f64\td11, d11, d7\n+\tvsub.f64\td7, d1, d0\n+\tvsub.f64\td1, d0, d1\n+\tvldr\td0, [sp, #112]\t@ 0x70\n+\tvmul.f64\td3, d0, d2\n+\tvmul.f64\td2, d8, d2\n+\tvmla.f64\td2, d0, d10\n+\tvnmls.f64\td3, d8, d10\n+\tvldr\td8, [sp, #48]\t@ 0x30\n+\tvmul.f64\td0, d8, d5\n+\tvmul.f64\td5, d12, d5\n+\tvmla.f64\td5, d8, d11\n+\tvcvt.f32.f64\ts4, d2\n+\tvnmls.f64\td0, d12, d11\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts0, d0\n+\tvstr\ts10, [r2, #-4]\n \tadd\tr2, r8\n-\tvadd.f64\td28, d17, d19\n-\tvsub.f64\td19, d7, d21\n-\tvsub.f64\td21, d29, d24\n-\tvsub.f64\td17, d29, d23\n-\tstr\tr2, [sp, #24]\n-\tldr\tr2, [sp, #12]\n-\tvadd.f64\td19, d19, d22\n-\tvadd.f64\td22, d23, d24\n-\tvadd.f64\td21, d21, d23\n-\tvadd.f64\td7, d17, d24\n-\tvnmul.f64\td23, d4, d3\n-\tvmul.f64\td28, d28, d9\n-\tvmul.f64\td24, d2, d4\n-\tvmul.f64\td17, d19, d10\n-\tvadd.f64\td19, d27, d22\n-\tvfma.f64\td17, d9, d21\n-\tvfma.f64\td23, d2, d7\n-\tvsub.f64\td27, d27, d22\n-\tvfma.f64\td28, d10, d21\n-\tvsub.f64\td21, d26, d25\n-\tvfma.f64\td24, d3, d7\n-\tvmul.f64\td21, d21, d31\n-\tvfma.f64\td21, d5, d19\n-\tvcvt.f32.f64\ts0, d17\n-\tvadd.f64\td17, d26, d25\n-\tvcvt.f32.f64\ts15, d23\n-\tvsub.f64\td23, d25, d26\n-\tvcvt.f32.f64\ts14, d24\n-\tvcvt.f32.f64\ts1, d28\n-\tvnmul.f64\td22, d17, d13\n-\tvmul.f64\td17, d14, d17\n-\tvfma.f64\td17, d13, d27\n-\tvfma.f64\td22, d14, d27\n-\tvmul.f64\td23, d23, d5\n-\tvstr\ts14, [sp, #44]\t@ 0x2c\n-\tvfma.f64\td23, d31, d19\n-\tvcvt.f32.f64\ts8, d21\n-\tvstr\ts15, [sp, #40]\t@ 0x28\n-\tvcvt.f32.f64\ts9, d17\n-\tvcvt.f32.f64\ts14, d22\n-\tvcvt.f32.f64\ts15, d23\n-\tvstr\ts9, [r2, #-4]\n-\tldr\tr2, [sp, #8]\n-\tvstr\ts14, [ip, #-4]\n+\tstr\tr2, [sp, #32]\n+\tldr\tr2, [sp, #16]\n+\tvstr\ts0, [ip, #-4]\n \tadd\tip, r8\n-\tvldr\ts14, [sp, #44]\t@ 0x2c\n-\tvstr\ts8, [r2, #-4]\n-\tldr\tr2, [sp, #20]\n-\tvstr\ts1, [r7, #-4]\n-\tadd\tr7, r8\n-\tvstr\ts15, [r2, #-4]\n-\tvldr\ts15, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #8]\n-\tvstr\ts0, [r5, #-4]\n-\tadd\tr5, r8\n-\tvstr\ts15, [r3, #-4]\n-\tadd\tr3, r8\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, r2, r8\n-\tldr\tr2, [sp, #20]\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #12]\n+\tvldr\td0, [sp, #136]\t@ 0x88\n+\tvmul.f64\td5, d0, d6\n+\tvmla.f64\td5, d7, d15\n+\tvmul.f64\td7, d15, d6\n+\tvmla.f64\td7, d1, d0\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvldr\td1, [sp, #144]\t@ 0x90\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts10, [r2, #-4]\n+\tldr\tr2, [sp, #24]\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvstr\ts14, [r2, #-4]\n+\tvmul.f64\td7, d6, d4\n+\tvmla.f64\td7, d1, d5\n+\tldr\tr2, [sp, #16]\n \tadd\tr2, r8\n-\tstr\tr2, [sp, #20]\n-\tadd\tr3, r8\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tstr\tr3, [sp, #12]\n+\tstr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #24]\n+\tadd\tr2, r8\n+\tstr\tr2, [sp, #24]\n+\tadd.w\tr2, r3, r8\n+\tstr\tr2, [sp, #144]\t@ 0x90\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r7, #-4]\n+\tvmul.f64\td7, d5, d4\n+\tvmla.f64\td7, d9, d6\n+\tvstr\ts6, [r3, #-4]\n \tldr\tr3, [sp, #28]\n-\tvstr\ts14, [r4, #-4]\n+\tadd\tr7, r8\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r5, #-4]\n+\tadd\tr5, r8\n+\tvstr\ts4, [r4, #-4]\n \tadd\tr4, r8\n+\tldr\tr2, [sp, #172]\t@ 0xac\n \tcmp\tr3, r2\n-\tbne.w\t71ba <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x28ea>\n-\tvldr\td0, [sp, #136]\t@ 0x88\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tbne.w\t76e0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2b28>\n+\tldr\tr3, [sp, #8]\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n-\tstr\tr3, [sp, #4]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #8]\n \tcmp\tr2, r3\n-\tble.n\t7452 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2b82>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tble.n\t7994 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ddc>\n+\tldr\tr2, [sp, #296]\t@ 0x128\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #32]\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #32]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r2\n-\tbne.w\t70e6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2816>\n-\tldrd\tr3, ip, [sp, #72]\t@ 0x48\n-\tldrd\tr1, r2, [sp, #100]\t@ 0x64\n+\tbne.w\t7610 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a58>\n+\tldrd\tr6, r3, [sp, #180]\t@ 0xb4\n+\tldrd\tfp, r7, [sp, #200]\t@ 0xc8\n \tsubs\tr3, #1\n-\tldrd\tr6, r4, [sp, #64]\t@ 0x40\n-\tadd\tr2, r1\n-\tldrd\tr0, r7, [sp, #80]\t@ 0x50\n-\tadds\tr5, r3, #1\n-\tldrd\tsl, r9, [sp, #92]\t@ 0x5c\n-\tldr.w\tlr, [sp, #112]\t@ 0x70\n-\tldr.w\tfp, [sp, #128]\t@ 0x80\n-\tbne.w\t70c4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27f4>\n-\tldr.w\tr8, [sp, #60]\t@ 0x3c\n-\tb.n\t708a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27ba>\n-\tnegs\tr3, r2\n-\trsb\tr2, ip, #0\n-\tcmp\tr1, #0\n-\tudiv\tr4, r3, r2\n-\tble.w\t4e30 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x560>\n-\tb.w\t5466 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb96>\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tnegs\tr3, r1\n-\tudiv\tr3, r2, r3\n-\tldr\tr2, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #208]\t@ 0xd0\n+\tadds\tr0, r3, #1\n+\tldrd\tsl, r9, [sp, #192]\t@ 0xc0\n+\tadd\tr2, r7\n+\tldr\tr4, [sp, #216]\t@ 0xd8\n+\tbne.w\t75fa <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a42>\n+\tldr.w\tr8, [sp, #176]\t@ 0xb0\n+\tb.n\t75be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a06>\n+\tnegs\tr1, r7\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, fp\n+\tble.w\t71d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x261c>\n+\tb.n\t75be <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a06>\n+\tldr\tr0, [sp, #384]\t@ 0x180\n+\tnegs\tr1, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n \tcmp\tr2, #0\n-\tble.w\t68da <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x200a>\n-\tb.w\t6c00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2330>\n-\tnegs\tr3, r0\n-\tnegs\tr2, r2\n-\tcmp\tr0, #0\n-\tudiv\tr3, r3, r2\n-\tbgt.w\t68c6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ff6>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\trsb\tlr, r1, #0\n-\tcmp\tr2, #1\n-\tbeq.w\t65a6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1cd6>\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tmovs\tr2, #0\n-\tldr\tr5, [sp, #148]\t@ 0x94\n-\tmov\tip, r0\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tldr\tr4, [sp, #404]\t@ 0x194\n+\tble.w\t6dbc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2204>\n+\tb.w\t70dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2524>\n+\tnegs\tr1, r3\n+\trsb\tr0, r8, #0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp.w\tr8, #0\n+\tmov\tr9, r0\n+\tbgt.w\t6da4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21ec>\n+\tnegs\tr3, r7\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #608]\t@ 0x260\n+\tcmp\tr3, #1\n+\tbeq.w\t6a70 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1eb8>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tmovs\tr5, #0\n+\tldr\tr6, [sp, #340]\t@ 0x154\n+\tmov\tsl, r8\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tmov\tr8, r7\n+\tldr\tr4, [sp, #384]\t@ 0x180\n+\tmov\tr7, r6\n+\tadds\tr3, #1\n \tmov\tr6, r5\n-\tldr\tr7, [sp, #176]\t@ 0xb0\n-\tcmp\tr1, #0\n-\tadd.w\tr4, r4, #1\n-\tldr.w\tr8, [sp, #144]\t@ 0x90\n-\tldr.w\tsl, [sp, #16]\n-\tldr.w\tfp, [sp, #172]\t@ 0xac\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tblt.w\t77d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f08>\n-\tudiv\tr0, r6, r1\n-\tldr\tr4, [sp, #148]\t@ 0x94\n-\tcmp\tr4, r2\n-\tblt.w\t77c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ef2>\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tcmp\tr4, #0\n-\tble.w\t77c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ef2>\n-\tadd.w\tr4, sl, r2\n-\tldr\tr5, [sp, #164]\t@ 0xa4\n-\tstr\tr4, [sp, #4]\n-\tstr\tr5, [sp, #32]\n-\tstrd\tr8, ip, [sp, #56]\t@ 0x38\n-\tstrd\tr3, r2, [sp, #64]\t@ 0x40\n-\tstrd\tlr, r0, [sp, #72]\t@ 0x48\n-\tstrd\tr9, r1, [sp, #80]\t@ 0x50\n-\tstrd\tr4, r7, [sp, #92]\t@ 0x5c\n-\tstr\tr6, [sp, #100]\t@ 0x64\n-\tldrd\tr3, r2, [sp]\n-\tadd\tr3, r2\n-\tcmp\tr3, sl\n-\tbge.n\t753a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c6a>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n+\tcmp.w\tr8, #0\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tblt.w\t7d28 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3170>\n+\tmov\tr1, r8\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tblt.w\t7d0a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3152>\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tcmp\tr2, #0\n+\tble.w\t7d0a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3152>\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tldr.w\tlr, [sp, #380]\t@ 0x17c\n+\tadd\tr2, r6\n+\tldr\tr1, [sp, #376]\t@ 0x178\n+\tmov\tfp, r2\n+\tstr\tr1, [sp, #40]\t@ 0x28\n+\tstr.w\tsl, [sp, #88]\t@ 0x58\n+\tstr.w\tr9, [sp, #96]\t@ 0x60\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr.w\tr8, [sp, #120]\t@ 0x78\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr4, [sp, #136]\t@ 0x88\n+\tstr\tr7, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #0]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tadd\tr3, fp\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tcmp\tr3, r2\n+\tldr\tr7, [sp, #152]\t@ 0x98\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr3, r3, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr1, r2, r3\n-\tcmp\tr1, sl\n-\tbge.n\t7546 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c76>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr1, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr1, r1, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr4, r2, r1\n-\tcmp\tr4, sl\n-\tbge.n\t7552 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c82>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr4, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr4, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr4, r4, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr0, r2, r4\n-\tcmp\tr0, sl\n-\tbge.n\t755e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c8e>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr0, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr0, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr0, r0, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr5, r2, r0\n-\tcmp\tr5, sl\n-\tbge.n\t756a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c9a>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr5, r2\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tcmp\tr5, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr5, r5, r2\n \tldr\tr2, [sp, #0]\n \tadd\tr2, r5\n-\tcmp\tr2, sl\n-\tbge.n\t7576 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ca6>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tadd\tr2, r6\n+\tcmp\tr2, r6\n+\titt\tlt\n+\tldrlt\tr6, [sp, #296]\t@ 0x128\n+\taddlt\tr2, r2, r6\n \tldr\tr6, [sp, #0]\n \tadd\tr6, r2\n-\tcmp\tr6, sl\n-\tbge.n\t7582 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2cb2>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\tcmp\tr6, r7\n+\titt\tlt\n+\tldrlt\tr7, [sp, #296]\t@ 0x128\n+\taddlt\tr6, r6, r7\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tcmp\tr7, #0\n-\tble.w\t7782 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2eb2>\n+\tble.w\t7cce <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3116>\n \tlsls\tr7, r5, #2\n \tlsls\tr5, r6, #2\n-\tldr\tr6, [sp, #4]\n+\tstr\tr7, [sp, #16]\n \tlsls\tr0, r0, #2\n-\tstr\tr7, [sp, #8]\n+\tldr\tr7, [sp, #336]\t@ 0x150\n \tlsls\tr1, r1, #2\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tlsls\tr2, r2, #2\n-\tstr\tr5, [sp, #12]\n-\tlsls\tr5, r6, #2\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tstr\tr5, [sp, #32]\n \tlsls\tr3, r3, #2\n-\tlsls\tr4, r4, #2\n-\tstr.w\tsl, [sp, #104]\t@ 0x68\n-\tadd.w\tr9, r6, r5\n-\tadd.w\tr8, r6, r0\n-\tadd.w\tlr, r6, r1\n+\tmov.w\tr5, fp, lsl #2\n+\tadd.w\tr9, r6, r0\n+\tadd.w\tsl, r6, r5\n+\tadd.w\tr8, r6, r1\n \tadd.w\tip, r6, r2\n \tadd\tr5, r7\n \tadd\tr2, r7\n \tadd\tr0, r7\n-\tstr\tr2, [sp, #40]\t@ 0x28\n \tadd\tr1, r7\n+\tstr\tr2, [sp, #8]\n \tadds\tr2, r6, r3\n \tadd\tr3, r7\n-\tstr\tr2, [sp, #20]\n+\tstr\tr2, [sp, #64]\t@ 0x40\n \tmov\tr2, r7\n-\tldr\tr7, [sp, #8]\n+\tldr\tr7, [sp, #16]\n+\tlsls\tr4, r4, #2\n+\tstr.w\tfp, [sp, #156]\t@ 0x9c\n \tadd\tr6, r7\n-\tstr\tr6, [sp, #28]\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tstr\tr6, [sp, #24]\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tadds\tr7, r2, r7\n-\tstr\tr7, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #48]\t@ 0x30\n \tadds\tr7, r6, r4\n-\tstr\tr7, [sp, #8]\n-\tldr\tr7, [sp, #12]\n+\tstr\tr7, [sp, #28]\n+\tldr\tr7, [sp, #32]\n \tadd\tr4, r2\n \tadd\tr6, r7\n-\tstr\tr6, [sp, #12]\n+\tstr\tr6, [sp, #32]\n \tmov\tr6, r2\n-\tldr\tr2, [sp, #40]\t@ 0x28\n \tadd\tr6, r7\n-\tldr\tr7, [sp, #164]\t@ 0xa4\n-\tmov\tsl, r6\n-\tstr\tr7, [sp, #24]\n-\tldr\tr7, [sp, #20]\n-\tstr\tr3, [sp, #20]\n-\tvldr\ts13, [r8, #-4]\n-\tvldr\ts11, [r9, #-4]\n+\tldr\tr7, [sp, #376]\t@ 0x178\n+\tmov\tfp, r6\n+\tstr\tr7, [sp, #16]\n+\tldr\tr7, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\ts14, [r9, #-4]\n+\tvldr\ts23, [sl, #-4]\n \tvldr\ts15, [r0, #-4]\n-\tvldr\ts14, [r5, #-4]\n-\tvadd.f32\ts12, s11, s13\n-\tvsub.f32\ts11, s11, s13\n-\tldr\tr3, [sp, #28]\n-\tvadd.f32\ts13, s14, s15\n-\tvsub.f32\ts14, s14, s15\n-\tldr\tr6, [sp, #24]\n-\tvstr\ts12, [r9, #-4]\n-\tadd\tr9, fp\n-\tvldr\ts12, [lr, #-4]\n-\tadds\tr6, #1\n-\tvstr\ts13, [r5, #-4]\n-\tadd\tr5, fp\n-\tvldr\ts13, [ip, #-4]\n-\tvcvt.f64.f32\td28, s12\n-\tvldr\ts10, [r1, #-4]\n-\tvldr\ts15, [r2, #-4]\n-\tvadd.f32\ts12, s12, s13\n-\tvcvt.f64.f32\td17, s13\n-\tstr\tr6, [sp, #24]\n-\tvcvt.f64.f32\td21, s10\n-\tvadd.f32\ts9, s10, s15\n-\tvcvt.f64.f32\td23, s15\n-\tldr\tr6, [sp, #36]\t@ 0x24\n-\tvstr\ts12, [r8, #-4]\n-\tvsub.f64\td28, d28, d17\n-\tvldr\ts15, [r3, #-4]\n-\tadd\tr8, fp\n-\tldr\tr3, [sp, #20]\n-\tvsub.f64\td23, d21, d23\n-\tvldr\ts13, [r7, #-4]\n-\tvstr\ts9, [r0, #-4]\n-\tvcvt.f64.f32\td17, s15\n-\tvldr\ts10, [r6, #-4]\n-\tvmul.f64\td19, d28, d16\n-\tvldr\ts9, [r3, #-4]\n-\tvcvt.f64.f32\td27, s13\n+\tvldr\ts22, [r5, #-4]\n+\tvadd.f32\ts13, s23, s14\n \tldr\tr3, [sp, #8]\n-\tvadd.f32\ts13, s13, s15\n-\tvcvt.f64.f32\td22, s10\n-\tvmul.f64\td23, d23, d16\n-\tvadd.f32\ts12, s9, s10\n-\tvcvt.f64.f32\td26, s9\n-\tvsub.f64\td21, d27, d17\n-\tvcvt.f32.f64\ts15, d19\n-\tvstr\ts13, [lr, #-4]\n-\tadd\tr0, fp\n+\tvsub.f32\ts23, s23, s14\n+\tldr\tr2, [sp, #24]\n+\tvadd.f32\ts14, s22, s15\n+\tvsub.f32\ts22, s22, s15\n+\tldr\tr6, [sp, #16]\n+\tvstr\ts13, [sl, #-4]\n+\tadd\tsl, lr\n+\tvldr\ts15, [r8, #-4]\n+\tadds\tr6, #1\n+\tvstr\ts14, [r5, #-4]\n+\tadd\tr5, lr\n+\tvldr\ts14, [ip, #-4]\n+\tvldr\ts12, [r1, #-4]\n+\tvcvt.f64.f32\td1, s15\n \tvldr\ts10, [r3, #-4]\n-\tadd\tlr, fp\n-\tldr\tr3, [sp, #12]\n-\tvsub.f64\td17, d26, d22\n-\tvstr\ts12, [r1, #-4]\n-\tadd\tr1, fp\n-\tvcvt.f64.f32\td28, s10\n-\tvldr\ts13, [sl, #-4]\n-\tvldr\ts12, [r4, #-4]\n-\tvldr\ts9, [r3, #-4]\n-\tvcvt.f64.f32\td27, s13\n-\tvcvt.f64.f32\td26, s12\n-\tvsub.f64\td22, d21, d28\n-\tvadd.f32\ts12, s12, s13\n-\tvcvt.f64.f32\td29, s9\n-\tvadd.f32\ts10, s10, s9\n-\tvcvt.f32.f64\ts13, d23\n-\tvsub.f64\td19, d17, d26\n-\tvsub.f64\td17, d17, d27\n-\tvstr\ts12, [r2, #-4]\n-\tvadd.f64\td22, d22, d29\n-\tvstr\ts10, [ip, #-4]\n-\tvsub.f64\td21, d21, d29\n-\tvstr\ts11, [r7, #-4]\n-\tadd\tip, fp\n-\tldr\tr3, [sp, #20]\n-\tvadd.f64\td19, d19, d27\n-\tvmul.f64\td22, d22, d24\n-\tvadd.f64\td17, d17, d26\n-\tvadd.f64\td21, d21, d28\n-\tadd\tr7, fp\n-\tadd\tr2, fp\n-\tvstr\ts14, [r3, #-4]\n-\tvmul.f64\td19, d19, d24\n+\tvadd.f32\ts9, s15, s14\n+\tvcvt.f64.f32\td7, s14\n+\tstr\tr6, [sp, #16]\n+\tvadd.f32\ts8, s12, s10\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td6, s12\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tvstr\ts9, [r9, #-4]\n+\tadd\tr9, lr\n+\tvldr\ts9, [r7, #-4]\n+\tvldr\ts6, [r2, #-4]\n+\tvsub.f64\td6, d6, d5\n+\tvsub.f64\td5, d1, d7\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tvcvt.f64.f32\td7, s9\n+\tvadd.f32\ts2, s9, s6\n \tldr\tr3, [sp, #28]\n-\tvcvt.f32.f64\ts12, d22\n-\tvmul.f64\td21, d21, d25\n-\tvstr\ts13, [r6, #-4]\n-\tvmul.f64\td17, d17, d25\n-\tvcvt.f32.f64\ts14, d19\n-\tvstr\ts15, [r3, #-4]\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #28]\n-\tvcvt.f32.f64\ts13, d21\n+\tvstr\ts8, [r0, #-4]\n+\tvcvt.f64.f32\td3, s6\n+\tvmul.f64\td5, d5, d14\n+\tvldr\ts4, [r6, #-4]\n+\tvldr\ts8, [r2, #-4]\n+\tvmul.f64\td6, d6, d14\n+\tvstr\ts2, [r8, #-4]\n+\tadd\tr0, lr\n+\tvsub.f64\td7, d7, d3\n+\tadd\tr8, lr\n+\tvadd.f32\ts3, s8, s4\n+\tvcvt.f32.f64\ts10, d5\n+\tvldr\ts11, [r3, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tldr\tr3, [sp, #32]\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts3, [r1, #-4]\n+\tadd\tr1, lr\n+\tvldr\ts13, [r4, #-4]\n+\tvldr\ts25, [r3, #-4]\n+\tvsub.f64\td4, d4, d2\n+\tvldr\ts24, [fp, #-4]\n+\tvcvt.f64.f32\td2, s11\n+\tvcvt.f64.f32\td0, s13\n \tldr\tr3, [sp, #8]\n-\tvcvt.f32.f64\ts15, d17\n-\tvstr\ts14, [r4, #-4]\n-\tadd\tr4, fp\n-\tvstr\ts12, [r3, #-4]\n-\tldr\tr3, [sp, #20]\n-\tvstr\ts15, [sl, #-4]\n-\tadd\tsl, fp\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #12]\n+\tvadd.f32\ts11, s11, s25\n+\tvcvt.f64.f32\td1, s25\n+\tvadd.f32\ts13, s13, s24\n+\tvcvt.f64.f32\td10, s24\n+\tvsub.f64\td3, d4, d0\n+\tvstr\ts11, [ip, #-4]\n+\tadd\tip, lr\n \tvstr\ts13, [r3, #-4]\n-\tldr\tr3, [sp, #8]\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #12]\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #12]\n-\tadd.w\tr3, r6, fp\n-\tldr\tr6, [sp, #24]\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tmov\tr3, r2\n+\tvstr\ts22, [r2, #-4]\n+\tvsub.f64\td4, d4, d10\n+\tldr\tr2, [sp, #24]\n+\tvadd.f64\td3, d3, d10\n+\tvstr\ts23, [r7, #-4]\n+\tadd\tr3, lr\n+\tvstr\ts12, [r6, #-4]\n+\tadd\tr6, lr\n+\tvadd.f64\td4, d4, d0\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tvstr\ts10, [r2, #-4]\n+\tvsub.f64\td5, d7, d2\n+\tvsub.f64\td7, d7, d1\n+\tvmul.f64\td3, d3, d8\n+\tadd\tr2, lr\n+\tstr\tr2, [sp, #24]\n+\tvmul.f64\td4, d4, d9\n+\tldr\tr2, [sp, #8]\n+\tvadd.f64\td6, d5, d1\n+\tldr\tr6, [sp, #28]\n+\tvadd.f64\td7, d7, d2\n+\tadd\tr2, lr\n+\tstr\tr2, [sp, #8]\n+\tvcvt.f32.f64\ts6, d3\n+\tldr\tr2, [sp, #32]\n+\tvcvt.f32.f64\ts8, d4\n+\tvmul.f64\td6, d6, d8\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvmul.f64\td7, d7, d9\n+\tmov\tr3, r2\n+\tadd\tr3, lr\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tr7, lr\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts6, [r4, #-4]\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts8, [fp, #-4]\n+\tadd\tr4, lr\n+\tadd\tfp, lr\n+\tvstr\ts12, [r6, #-4]\n+\tadd\tr6, lr\n+\tstr\tr6, [sp, #28]\n+\tldr\tr6, [sp, #16]\n+\tvstr\ts14, [r2, #-4]\n \tcmp\tr6, r3\n-\tbne.w\t75f2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2d22>\n-\tldr.w\tsl, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #4]\n-\tldr\tr2, [sp, #108]\t@ 0x6c\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #4]\n-\tcmp\tr3, sl\n-\tbge.n\t7794 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ec4>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #32]\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tbne.w\t7b3c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f84>\n+\tldr.w\tfp, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd\tfp, r3\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tfp, r3\n+\tbge.n\t7cdc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3124>\n+\tldr\tr3, [sp, #296]\t@ 0x128\n+\tadd\tfp, r3\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #72]\t@ 0x48\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #32]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r2\n-\tbne.w\t752c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c5c>\n-\tldrd\tlr, r0, [sp, #72]\t@ 0x48\n-\tldrd\tr9, r1, [sp, #80]\t@ 0x50\n-\tsubs\tr0, #1\n-\tldrd\tr4, r7, [sp, #92]\t@ 0x5c\n-\tadds\tr5, r0, #1\n-\tldrd\tr8, ip, [sp, #56]\t@ 0x38\n-\tadd\tr4, r1\n-\tldrd\tr3, r2, [sp, #64]\t@ 0x40\n-\tldr\tr6, [sp, #100]\t@ 0x64\n-\tbne.w\t7510 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c40>\n+\tbne.w\t7a6c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2eb4>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tldr.w\tr8, [sp, #120]\t@ 0x78\n+\tldr\tr2, [sp, #128]\t@ 0x80\n \tsubs\tr3, #1\n-\tadd\tr2, r8\n-\tadd\tr7, r8\n-\tsub.w\tr6, r6, r8\n+\tldr.w\tsl, [sp, #88]\t@ 0x58\n \tadds\tr0, r3, #1\n-\tbeq.w\t68c4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x1ff4>\n-\tcmp\tr1, #0\n-\tbge.w\t74f8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c28>\n-\tudiv\tr0, r7, lr\n-\tldr\tr4, [sp, #148]\t@ 0x94\n-\tcmp\tr4, r2\n-\tble.w\t7504 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2c34>\n-\tb.n\t77c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2ef2>\n-\tnegs\tr3, r1\n-\tcmp\tsl, r7\n-\tudiv\tr3, lr, r3\n-\tble.w\t6cb6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x23e6>\n-\tb.n\t708a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27ba>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n+\tldr.w\tr9, [sp, #96]\t@ 0x60\n+\tadd\tr2, r8\n+\tldr\tr6, [sp, #104]\t@ 0x68\n+\tldr\tr4, [sp, #136]\t@ 0x88\n+\tldr\tr7, [sp, #144]\t@ 0x90\n+\tbne.w\t7a50 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e98>\n+\tldr\tr3, [sp, #360]\t@ 0x168\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tcmp.w\tr9, #4294967295\t@ 0xffffffff\n+\tadd\tr6, r3\n+\tadd\tr4, r3\n+\tsub.w\tr7, r7, r3\n+\tbeq.w\t6da0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x21e8>\n+\tcmp.w\tr8, #0\n+\tbge.w\t7a2e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e76>\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tble.w\t7a40 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2e88>\n+\tb.n\t7d0a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3152>\n+\tldr\tr1, [sp, #184]\t@ 0xb8\n+\tmov\tr0, sl\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr2, [sp, #340]\t@ 0x154\n+\tmov\tr3, r0\n+\tcmp\tr2, r7\n+\tble.w\t4ff4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x43c>\n+\tb.w\t55dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa24>\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmovs\tr7, #0\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tcmp.w\tr9, #0\n+\tldr\tr3, [sp, #384]\t@ 0x180\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tldr.w\tfp, [sp, #380]\t@ 0x17c\n+\tadd.w\tr3, r3, #1\n+\tstr\tr3, [sp, #180]\t@ 0xb4\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tldr.w\tsl, [sp, #332]\t@ 0x14c\n+\tadd.w\tr3, r3, #1\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tblt.w\t8410 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3858>\n+\tldr\tr0, [sp, #176]\t@ 0xb0\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr2, r0\n+\tcmp\tr3, r7\n+\tblt.w\t83ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3836>\n+\tldr\tr3, [sp, #344]\t@ 0x158\n+\tcmp\tr3, #0\n+\tble.w\t83ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3836>\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr0, [sp, #336]\t@ 0x150\n+\tadds\tr1, r3, r7\n+\tstrd\tr6, r4, [sp, #200]\t@ 0xc8\n+\tmov\tr4, fp\n+\tstr.w\tr9, [sp, #208]\t@ 0xd0\n+\tmov\tr9, sl\n \tmovs\tr3, #1\n-\tstr.w\tr9, [sp, #32]\n-\tldrd\tr6, ip, [sp, #144]\t@ 0x90\n-\tadd\tr2, r3\n-\tldr.w\tr9, [sp, #16]\n-\tldr.w\tfp, [sp, #172]\t@ 0xac\n-\tldr.w\tsl, [sp, #120]\t@ 0x78\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tstr\tr2, [sp, #4]\n-\tstr\tr3, [sp, #28]\n+\tstr\tr1, [sp, #164]\t@ 0xa4\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tstr\tr7, [sp, #216]\t@ 0xd8\n+\tstrd\tr2, r8, [sp, #224]\t@ 0xe0\n+\tstr\tr1, [sp, #232]\t@ 0xe8\n+\tstr\tr0, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr2, [sp, #284]\t@ 0x11c\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tadds\tr2, r3, r2\n \tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tmov\tr0, r3\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tsdiv\tr1, r2, r3\n-\tsubs\tr3, r1, r2\n-\tlsls\tr7, r1, #2\n-\tstr\tr3, [sp, #0]\n-\tbmi.w\t80ea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x381a>\n-\tudiv\tr3, ip, r7\n-\tldr\tr2, [sp, #196]\t@ 0xc4\n-\tcmp\tr2, #0\n-\tbne.w\t79d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3104>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tcmp\tr2, #0\n-\tble.w\t79d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3104>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\tcmp\tr2, #1\n-\tmov\tr2, r9\n-\tbne.w\t7c6e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x339e>\n-\tsub.w\tr4, sl, #4\n-\tstr\tr4, [sp, #20]\n-\tmov\tr8, r2\n-\tmovs\tr4, #1\n-\tstr\tr6, [sp, #24]\n-\tstr\tr4, [sp, #8]\n-\tstrd\tr3, r1, [sp, #36]\t@ 0x24\n-\tstrd\tr7, ip, [sp, #44]\t@ 0x2c\n-\tstr\tr0, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #0]\n-\tadd\tr3, r8\n-\tcmp\tr9, r3\n-\tble.n\t786e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f9e>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n+\tcmp\tr3, r2\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr2, r2, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadds\tr1, r3, r2\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr3, r1\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr1, r1, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tadd\tr3, r1\n-\tldr\tr1, [sp, #0]\n-\tadd\tr1, r3\n-\tcmp\tr9, r1\n-\tble.n\t787a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2faa>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr1, r0\n+\tstr\tr3, [sp, #8]\n+\tcmp\tr5, r3\n+\tldr\tr5, [sp, #308]\t@ 0x134\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r0\n+\tstrgt\tr3, [sp, #8]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tadd.w\tsl, r3, r5\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tcmp\tr3, sl\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tsl, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadd.w\tr8, r3, sl\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr3, r8\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tr8, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadd.w\tfp, r3, r8\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr3, fp\n+\titt\tgt\n+\tldrgt\tr3, [sp, #296]\t@ 0x128\n+\taddgt\tfp, r3\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n+\tadd\tr3, fp\n+\tstr\tr3, [sp, #16]\n+\tcmp\tr5, r3\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r0\n+\tstrgt\tr3, [sp, #16]\n+\tldr\tr3, [sp, #308]\t@ 0x134\n+\tadd\tr3, sl\n+\tcmp\tr5, r3\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr3, r3, r0\n+\tadd.w\tip, r5, r3\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tcmp\tr5, ip\n+\tit\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\tit\tgt\n+\taddgt\tip, r0\n+\tldr\tr6, [sp, #152]\t@ 0x98\n+\tadd.w\tr7, r5, ip\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tcmp\tr5, r7\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr7, r7, r0\n+\tadd\tr5, r7\n+\tstr\tr5, [sp, #24]\n+\tcmp\tr6, r5\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r0\n+\tstrgt\tr5, [sp, #24]\n+\tldr\tr5, [sp, #308]\t@ 0x134\n+\tadd.w\tlr, r5, r3\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tcmp\tr5, lr\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tlr, r0\n+\tadd.w\tr6, r5, lr\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tstr\tr6, [sp, #0]\n+\tcmp\tr5, r6\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\tittt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r0\n+\tstrgt\tr6, [sp, #0]\n \tldr\tr0, [sp, #0]\n-\tadd\tr0, r1\n-\tcmp\tr9, r0\n-\tble.n\t7886 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2fb6>\n-\tldr\tr4, [sp, #88]\t@ 0x58\n-\tadd\tr0, r4\n-\tldr\tr4, [sp, #404]\t@ 0x194\n-\tcmp\tr4, #0\n-\tble.w\t79a4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x30d4>\n+\tadds\tr6, r5, r0\n+\tldr\tr5, [sp, #152]\t@ 0x98\n+\tcmp\tr5, r6\n+\tldr\tr5, [sp, #284]\t@ 0x11c\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr6, r6, r0\n+\tldr\tr0, [sp, #152]\t@ 0x98\n+\tadd\tr5, r6\n+\tstr\tr5, [sp, #28]\n+\tcmp\tr0, r5\n+\titt\tgt\n+\tldrgt\tr0, [sp, #296]\t@ 0x128\n+\taddgt\tr5, r5, r0\n+\tldr\tr0, [sp, #620]\t@ 0x26c\n+\tit\tgt\n+\tstrgt\tr5, [sp, #28]\n+\tcmp\tr0, #0\n+\tble.w\t83ac <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37f4>\n+\tadd.w\tr5, r8, #1073741824\t@ 0x40000000\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tsubs\tr5, #1\n+\tstr\tr5, [sp, #48]\t@ 0x30\n+\tldr\tr5, [sp, #16]\n+\tsubs\tr2, #1\n+\tstr\tr2, [sp, #32]\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tadd.w\tr2, r5, #1073741824\t@ 0x40000000\n+\tldr\tr5, [sp, #24]\n+\tsubs\tr2, #1\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tadd.w\tr2, r5, #1073741824\t@ 0x40000000\n+\tldr\tr0, [sp, #8]\n+\tsubs\tr2, #1\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr2, [sp, #0]\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n-\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tsubs\tr3, #1\n \tsubs\tr0, #1\n-\tadd.w\tr5, r8, #1073741824\t@ 0x40000000\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n-\tadd.w\tlr, r4, r8\n+\tsubs\tr3, #1\n+\tadd.w\tr5, r2, #1073741824\t@ 0x40000000\n+\tldr\tr2, [sp, #28]\n+\tadd.w\tsl, sl, #1073741824\t@ 0x40000000\n+\tadd.w\tlr, lr, #1073741824\t@ 0x40000000\n+\tadd.w\tr8, r2, #1073741824\t@ 0x40000000\n+\tldr\tr2, [sp, #32]\n+\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n+\tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tlsls\tr2, r2, #2\n+\tstr\tr2, [sp, #32]\n+\tlsls\tr2, r0, #2\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tlsls\tr2, r3, #2\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr2, [sp, #8]\n+\tmov.w\tr2, sl, lsl #2\n+\tstr\tr2, [sp, #16]\n+\tmov.w\tr2, lr, lsl #2\n+\tstr\tr2, [sp, #24]\n+\tlsls\tr2, r3, #2\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tsubs\tr6, #1\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n \tsubs\tr1, #1\n-\tldr\tr4, [sp, #20]\n-\tsubs\tr5, #1\n+\tadd.w\tfp, fp, #1073741824\t@ 0x40000000\n+\tlsls\tr2, r3, #2\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n+\tadd.w\tip, ip, #1073741824\t@ 0x40000000\n+\tadd.w\tr7, r7, #1073741824\t@ 0x40000000\n+\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n \tlsls\tr3, r3, #2\n-\tlsls\tr0, r0, #2\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tlsls\tr3, r6, #2\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tmov.w\tr3, r8, lsl #2\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tsubs\tr7, #1\n+\tsubs\tr5, #1\n \tlsls\tr1, r1, #2\n-\tlsls\tr5, r5, #2\n-\tadd.w\tr7, sl, r3\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #12]\n-\tadd.w\tr3, sl, r0\n-\tadd.w\tlr, r4, lr, lsl #2\n-\tadd.w\tip, sl, r1\n-\tadd.w\tr4, sl, r5\n-\tadd\tr1, r6\n-\tadd\tr5, r6\n-\tadd\tr0, r6\n-\tmov\tr6, r3\n-\tldr\tr3, [sp, #12]\n-\tvldr\ts11, [r3]\n-\tvldr\ts10, [r0]\n-\tvldr\ts14, [ip]\n-\tvldr\ts15, [r1]\n-\tvcvt.f64.f32\td21, s11\n-\tvldr\ts12, [r4]\n-\tvcvt.f64.f32\td19, s10\n-\tvldr\ts7, [r5]\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts9, [r7]\n-\tvcvt.f64.f32\td16, s15\n-\tvldr\ts8, [r6]\n-\tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td23, s7\n-\tvsub.f64\td26, d21, d19\n-\tvcvt.f64.f32\td25, s9\n-\tvadd.f64\td19, d19, d21\n-\tvcvt.f64.f32\td24, s8\n-\tvsub.f64\td21, d6, d17\n-\tvadd.f64\td17, d17, d6\n-\tvsub.f64\td22, d23, d16\n-\tvadd.f64\td16, d16, d23\n-\tvsub.f64\td27, d25, d24\n-\tvadd.f64\td24, d24, d25\n-\tvmov.f64\td23, d21\n-\tvfma.f64\td21, d18, d26\n-\tvmov.f64\td5, d22\n-\tvfma.f64\td23, d20, d26\n-\tvfma.f64\td5, d18, d27\n-\tvfma.f64\td22, d27, d20\n-\tvadd.f64\td4, d24, d17\n-\tvsub.f64\td17, d17, d24\n-\tvadd.f64\td24, d19, d16\n-\tvsub.f64\td16, d16, d19\n-\tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts13, d21\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts9, d24\n-\tvcvt.f32.f64\ts15, d16\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts12, d22\n-\tvcvt.f32.f64\ts11, d23\n-\tvstmia\tr4!, {s8}\n-\tvstmia\tip!, {s14}\n-\tcmp\tr4, lr\n-\tvstmia\tr5!, {s9}\n-\tvstmia\tr1!, {s15}\n-\tvstmia\tr7!, {s11}\n-\tvstmia\tr3!, {s10}\n-\tvstmia\tr6!, {s13}\n-\tvstmia\tr0!, {s12}\n-\tbne.n\t78d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3008>\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr8, r3\n-\tcmp\tr9, r8\n-\tble.n\t79b0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x30e0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr8, r3\n-\tldr\tr3, [sp, #8]\n-\tldr\tr1, [sp, #4]\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #8]\n-\tcmp\tr3, r1\n-\tbne.w\t7862 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f92>\n-\tldrd\tr3, r1, [sp, #36]\t@ 0x24\n-\tldrd\tr7, ip, [sp, #44]\t@ 0x2c\n-\tsubs\tr3, #1\n-\tldr\tr6, [sp, #24]\n-\tadds\tr5, r3, #1\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tadd\tr2, r7\n-\tbne.w\t7850 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f80>\n-\tldr\tr3, [sp, #400]\t@ 0x190\n-\tcmp\tr3, #2\n-\tbeq.w\t7e1a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x354a>\n-\tlsls\tr3, r0, #1\n-\tsubs\tr2, r1, r6\n-\tcmp\tr6, #0\n-\tblt.w\t80d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3808>\n-\tsubs\tr1, r2, r6\n-\tcmp\tr6, r2\n-\tudiv\tr1, r1, r6\n-\tstr\tr1, [sp, #8]\n-\tbgt.w\t80c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37f2>\n-\tldr\tr2, [sp, #392]\t@ 0x188\n-\tcmp\tr2, #1\n-\tmov.w\tr2, #24\n-\tmul.w\tr2, r2, r3\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tbne.w\t7e32 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3562>\n-\tldr\tr4, [sp, #184]\t@ 0xb8\n-\tlsls\tr0, r3, #3\n-\tsub.w\tr8, ip, r6\n-\tlsls\tr3, r3, #4\n-\tadds\tr1, r4, r0\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd.w\tlr, r1, r0\n-\tadd.w\tr3, r2, #8\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n-\tmov\tr0, r8\n-\tldr.w\tr8, [sp, #124]\t@ 0x7c\n-\tadd\tr3, r4\n-\tmov\tr2, lr\n-\tsub.w\tr4, r6, ip\n-\tstr\tr4, [sp, #24]\n-\tmov\tr4, r6\n-\tsub.w\tr5, sl, #4\n-\tstr\tr5, [sp, #12]\n-\tvldr\td30, [r1, #8]\n-\tcmp\tr7, #0\n-\tvldr\td29, [r2, #8]\n-\tvldr\td28, [r3]\n-\tvmul.f64\td30, d0, d30\n-\tvldr\td6, [r1]\n-\tvmul.f64\td29, d0, d29\n-\tvldr\td7, [r2]\n-\tvmul.f64\td28, d0, d28\n-\tvldr\td31, [r3, #-8]\n-\tblt.w\t7e22 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3552>\n-\tudiv\tr1, r0, r7\n-\tcmp\tip, r4\n-\tblt.w\t7c46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3376>\n-\tldr\tr5, [sp, #132]\t@ 0x84\n-\tcmp\tr5, #0\n-\tble.w\t7c46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3376>\n-\tadd.w\tr5, r9, r4\n-\tstrd\tr6, ip, [sp, #48]\t@ 0x30\n-\tstr\tr5, [sp, #20]\n-\tstrd\tr4, r2, [sp, #56]\t@ 0x38\n-\tstrd\tr0, r3, [sp, #64]\t@ 0x40\n-\tstrd\tfp, lr, [sp, #72]\t@ 0x48\n-\tldr.w\tlr, [sp, #20]\n-\tmov.w\tfp, #1\n-\tstrd\tr7, r1, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #0]\n-\tadd\tr3, lr\n-\tcmp\tr9, r3\n-\tble.n\t7aa0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31d0>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #0]\n-\tadd\tr2, r3\n-\tcmp\tr9, r2\n-\tble.n\t7aac <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31dc>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr2, r1\n-\tldr\tr1, [sp, #0]\n-\tadds\tr0, r1, r2\n-\tcmp\tr9, r0\n-\tble.n\t7ab8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31e8>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr0, r1\n-\tldr\tr1, [sp, #404]\t@ 0x194\n-\tcmp\tr1, #0\n-\tble.w\t7c0c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x333c>\n-\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n-\tadd.w\tr4, lr, #1073741824\t@ 0x40000000\n-\tadd.w\tip, r1, lr\n-\tsubs\tr2, #1\n-\tldr\tr1, [sp, #12]\n+\tldr\tr0, [sp, #112]\t@ 0x70\n \tsubs\tr3, #1\n-\tsubs\tr0, #1\n-\tsubs\tr4, #1\n-\tlsls\tr2, r2, #2\n-\tlsls\tr3, r3, #2\n-\tlsls\tr0, r0, #2\n-\tlsls\tr4, r4, #2\n-\tadd.w\tip, r1, ip, lsl #2\n-\tadd.w\tr7, sl, r2\n-\tadd.w\tr1, sl, r4\n-\tadd.w\tr6, sl, r3\n-\tadd.w\tr5, sl, r0\n-\tadd\tr4, r8\n-\tadd\tr2, r8\n-\tadd\tr3, r8\n-\tadd\tr0, r8\n-\tvldr\ts10, [r4]\n-\tvldr\ts11, [r2]\n-\tvldr\ts7, [r5]\n-\tvldr\ts8, [r6]\n-\tvcvt.f64.f32\td17, s10\n-\tvldr\ts4, [r1]\n-\tvcvt.f64.f32\td16, s11\n-\tvldr\ts5, [r7]\n-\tvcvt.f64.f32\td26, s7\n-\tvldr\ts6, [r3]\n+\tmov.w\tfp, fp, lsl #2\n+\tlsls\tr6, r5, #2\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tmov.w\tr8, r3, lsl #2\n+\tstr.w\tr8, [sp, #96]\t@ 0x60\n+\tmov\tr8, r1\n+\tmov.w\tr2, ip, lsl #2\n+\tmovs\tr3, #1\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #0]\n+\tlsls\tr2, r7, #2\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tadd.w\tr7, r9, r8\n+\tldr\tr2, [sp, #32]\n+\tadd.w\tip, r0, r8\n+\tadd.w\tr1, r9, r6\n+\tstr\tr1, [sp, #120]\t@ 0x78\n+\tadd.w\tsl, r9, r2\n+\tadds\tr5, r6, r4\n+\tvldr\ts4, [r7]\n+\tadd\tr8, r4\n+\tvldr\ts14, [r1]\n+\tadds\tr1, r0, r2\n+\tvldr\ts8, [sl]\n+\tadd\tr2, r4\n+\tstr\tr2, [sp, #32]\n+\tadds\tr2, r0, r6\n+\tvcvt.f64.f32\td7, s14\n+\tstr\tr2, [sp, #128]\t@ 0x80\n \tvcvt.f64.f32\td4, s8\n-\tvldr\ts3, [r0]\n-\tvcvt.f64.f32\td19, s4\n-\tvcvt.f64.f32\td21, s5\n-\tvsub.f64\td22, d17, d16\n+\tvldr\ts12, [r1]\n+\tvcvt.f64.f32\td2, s4\n+\tldr\tr3, [sp, #0]\n+\tstr\tr7, [sp, #112]\t@ 0x70\n+\tvcvt.f64.f32\td6, s12\n+\tadds\tr3, #1\n+\tvsub.f64\td5, d4, d7\n+\tvadd.f64\td4, d4, d7\n+\tvldr\ts14, [r2]\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tstr\tr3, [sp, #0]\n+\tadd.w\tr6, r9, r2\n+\tvcvt.f64.f32\td7, s14\n+\tadds\tr3, r0, r2\n+\tvmul.f64\td5, d5, d13\n+\tldr\tr7, [sp, #8]\n+\tadd\tr2, r4\n+\tvldr\ts22, [r6]\n+\tvsub.f64\td3, d6, d7\n+\tvadd.f64\td6, d6, d7\n+\tstr\tr2, [sp, #96]\t@ 0x60\n+\tadd.w\tr2, r9, r7\n+\tvcvt.f64.f32\td11, s22\n+\tstr\tr5, [sp, #40]\t@ 0x28\n+\tvmul.f64\td3, d3, d13\n+\tvadd.f64\td7, d11, d2\n+\tvsub.f64\td11, d11, d2\n+\tvldr\ts4, [r2]\n+\tvadd.f64\td1, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvsub.f64\td4, d11, d3\n+\tvadd.f64\td11, d11, d3\n+\tvldr\ts6, [ip]\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts3, d7\n+\tvldr\ts14, [r3]\n \tvcvt.f64.f32\td3, s6\n-\tvsub.f64\td23, d16, d17\n-\tvcvt.f64.f32\td25, s3\n-\tvsub.f64\td5, d4, d26\n-\tvadd.f64\td26, d26, d4\n-\tvadd.f64\td16, d16, d17\n-\tvsub.f64\td27, d19, d21\n-\tvmov.f64\td24, d22\n-\tvadd.f64\td21, d21, d19\n-\tvsub.f64\td4, d3, d25\n-\tvfma.f64\td24, d18, d5\n-\tvadd.f64\td25, d25, d3\n-\tvfma.f64\td23, d18, d5\n-\tvfma.f64\td22, d5, d20\n-\tvmov.f64\td5, d27\n-\tvfma.f64\td5, d20, d4\n-\tvfma.f64\td27, d18, d4\n-\tvsub.f64\td19, d25, d16\n-\tvsub.f64\td17, d16, d25\n-\tvadd.f64\td16, d25, d16\n-\tvsub.f64\td25, d21, d26\n-\tvmul.f64\td19, d19, d29\n-\tvadd.f64\td21, d26, d21\n-\tvmul.f64\td17, d17, d7\n-\tvnmul.f64\td26, d30, d24\n-\tvmul.f64\td23, d23, d28\n-\tvmul.f64\td24, d24, d6\n-\tvmul.f64\td22, d22, d31\n-\tvfma.f64\td26, d5, d6\n-\tvfma.f64\td24, d5, d30\n-\tvfma.f64\td19, d25, d7\n-\tvfma.f64\td17, d25, d29\n-\tvfma.f64\td23, d27, d31\n-\tvfma.f64\td22, d27, d28\n-\tvcvt.f32.f64\ts11, d21\n-\tvcvt.f32.f64\ts10, d16\n-\tvstmia\tr1!, {s11}\n-\tcmp\tr1, ip\n-\tvstmia\tr4!, {s10}\n-\tvcvt.f32.f64\ts8, d26\n-\tvcvt.f32.f64\ts6, d24\n-\tvcvt.f32.f64\ts7, d19\n-\tvcvt.f32.f64\ts9, d17\n-\tvcvt.f32.f64\ts10, d23\n-\tvcvt.f32.f64\ts11, d22\n-\tvstmia\tr6!, {s8}\n-\tvstmia\tr3!, {s6}\n-\tvstmia\tr7!, {s7}\n-\tvstmia\tr2!, {s9}\n-\tvstmia\tr5!, {s10}\n-\tvstmia\tr0!, {s11}\n-\tbne.w\t7b02 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3232>\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tlr, r3\n-\tcmp\tr9, lr\n-\tble.n\t7c18 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3348>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #4]\n-\tadd.w\tfp, fp, #1\n-\tcmp\tfp, r3\n-\tbne.w\t7a94 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31c4>\n-\tldrd\tr7, r1, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #20]\n-\tsubs\tr1, #1\n-\tadd\tr3, r7\n-\tadds\tr0, r1, #1\n-\tstr\tr3, [sp, #20]\n-\tbne.w\t7a88 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31b8>\n-\tldrd\tr6, ip, [sp, #48]\t@ 0x30\n-\tldrd\tr4, r2, [sp, #56]\t@ 0x38\n-\tldrd\tr0, r3, [sp, #64]\t@ 0x40\n-\tldrd\tfp, lr, [sp, #72]\t@ 0x48\n-\tadd\tr4, r6\n-\tldr\tr1, [sp, #8]\n-\tsubs\tr0, r0, r6\n-\tsubs\tr1, #1\n-\tstr\tr1, [sp, #8]\n-\tmov\tr5, r1\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tadds\tr5, #1\n-\tadd\tr2, r1\n+\tvcvt.f32.f64\ts1, d4\n+\tvcvt.f32.f64\ts22, d11\n+\tvcvt.f64.f32\td7, s14\n+\tvadd.f64\td4, d7, d3\n+\tvsub.f64\td7, d7, d3\n+\tvadd.f64\td3, d4, d6\n+\tvsub.f64\td4, d4, d6\n+\tvsub.f64\td6, d7, d5\n+\tvadd.f64\td5, d5, d7\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts23, d4\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts18, d5\n+\tvstr\ts6, [r3]\n+\tldr\tr3, [sp, #16]\n+\tadd\tr3, r9\n+\tvldr\ts14, [r3]\n+\tvstr\ts2, [r6]\n+\tvstr\ts3, [r2]\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tvcvt.f64.f32\td7, s14\n+\tldr\tr2, [sp, #24]\n+\tvstr\ts1, [r3]\n+\tadd.w\tr7, r9, r6\n+\tadds\tr3, r0, r2\n+\tvldr\ts16, [r7]\n+\tvldr\ts6, [r3]\n+\tvstr\ts12, [r3]\n+\tadds\tr3, r0, r6\n+\tldr\tr5, [sp, #56]\t@ 0x38\n+\tvcvt.f64.f32\td8, s16\n+\tadd\tr6, r4\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tadd.w\tlr, r9, r5\n+\tadds\tr2, r0, r5\n+\tvldr\ts10, [r3]\n+\tadds\tr6, r5, r4\n+\tstr\tr6, [sp, #56]\t@ 0x38\n+\tadd.w\tr6, r9, fp\n+\tvldr\ts12, [lr]\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td5, s10\n+\tldr\tr5, [sp, #16]\n+\tstr.w\tlr, [sp, #136]\t@ 0x88\n+\tvcvt.f64.f32\td6, s12\n+\tadd.w\tlr, r0, r5\n+\tadd\tr5, r4\n+\tstr\tr5, [sp, #16]\n+\tadd.w\tr5, r0, fp\n+\tstr\tr5, [sp, #144]\t@ 0x90\n+\tvldr\ts0, [lr]\n+\tadd\tfp, r4\n+\tvsub.f64\td1, d8, d6\n+\tvadd.f64\td8, d8, d6\n+\tvldr\ts12, [r2]\n+\tvcvt.f64.f32\td0, s0\n+\tvcvt.f64.f32\td6, s12\n+\tvmul.f64\td1, d1, d13\n+\tvsub.f64\td10, d5, d6\n+\tvadd.f64\td5, d5, d6\n+\tvldr\ts12, [r6]\n+\tvcvt.f64.f32\td6, s12\n+\tvmul.f64\td10, d10, d13\n+\tvadd.f64\td4, d7, d6\n+\tvsub.f64\td7, d7, d6\n+\tvldr\ts12, [r5]\n+\tvstr\ts18, [lr]\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tvcvt.f64.f32\td6, s12\n+\tvadd.f64\td9, d4, d8\n+\tvsub.f64\td4, d4, d8\n+\tvsub.f64\td8, d7, d10\n+\tvadd.f64\td7, d7, d10\n+\tadd.w\tlr, r9, r5\n+\tvadd.f64\td10, d0, d6\n+\tvsub.f64\td6, d0, d6\n+\tvcvt.f32.f64\ts18, d9\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts16, d8\n+\tvcvt.f32.f64\ts15, d7\n+\tvadd.f64\td0, d10, d5\n+\tvsub.f64\td10, d10, d5\n+\tvadd.f64\td5, d1, d6\n+\tvsub.f64\td6, d6, d1\n+\tvcvt.f32.f64\ts9, d0\n+\tvcvt.f32.f64\ts20, d10\n+\tvcvt.f32.f64\ts14, d6\n+\tvcvt.f32.f64\ts13, d5\n+\tvldr\ts10, [lr]\n+\tvstr\ts18, [sl]\n+\tvstr\ts8, [lr]\n+\tvstr\ts16, [r7]\n+\tadds\tr7, r0, r5\n+\tadd\tr5, r4\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tldr\tr5, [sp, #72]\t@ 0x48\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts0, [r7]\n+\tadd.w\tsl, r9, r5\n+\tvstr\ts9, [r1]\n+\tvstr\ts20, [r7]\n+\tldr\tr7, [sp, #80]\t@ 0x50\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts12, [sl]\n+\tvstr\ts13, [r3]\n+\tadd.w\tr3, r9, r7\n+\tadds\tr1, r0, r7\n+\tadd\tr7, r4\n+\tvcvt.f64.f32\td6, s12\n+\tstr\tr7, [sp, #80]\t@ 0x50\n+\tldr\tr7, [sp, #8]\n+\tadd.w\tlr, r0, r7\n+\tadd\tr7, r4\n+\tvadd.f64\td4, d2, d6\n+\tvsub.f64\td6, d2, d6\n+\tvldr\ts4, [r3]\n+\tstr\tr7, [sp, #8]\n+\tadds\tr7, r0, r5\n+\tadd\tr5, r4\n+\tvcvt.f64.f32\td2, s4\n+\tvsub.f64\td1, d5, d2\n+\tvadd.f64\td5, d5, d2\n+\tvldr\ts4, [r1]\n+\tvldr\ts18, [lr]\n+\tstr\tr5, [sp, #72]\t@ 0x48\n+\tvcvt.f64.f32\td2, s4\n+\tvadd.f64\td8, d4, d5\n+\tvsub.f64\td4, d4, d5\n+\tvcvt.f64.f32\td9, s18\n+\tvmul.f64\td1, d1, d13\n+\tldr\tr5, [sp, #88]\t@ 0x58\n+\tstr\tr7, [sp, #156]\t@ 0x9c\n+\tvsub.f64\td5, d0, d2\n+\tvadd.f64\td2, d0, d2\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts16, d8\n+\tvmul.f64\td5, d5, d13\n+\tvsub.f64\td0, d6, d5\n+\tvadd.f64\td6, d6, d5\n+\tvcvt.f32.f64\ts9, d6\n+\tvldr\ts12, [r7]\n+\tvcvt.f32.f64\ts0, d0\n+\tldr\tr7, [sp, #112]\t@ 0x70\n+\tvstr\ts23, [lr]\n+\tadd.w\tlr, r9, r5\n+\tvcvt.f64.f32\td6, s12\n+\tvadd.f64\td5, d9, d6\n+\tvsub.f64\td6, d9, d6\n+\tvadd.f64\td9, d5, d2\n+\tvsub.f64\td5, d5, d2\n+\tvadd.f64\td2, d1, d6\n+\tvsub.f64\td6, d6, d1\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts18, d9\n+\tvcvt.f32.f64\ts11, d2\n+\tvldr\ts4, [lr]\n+\tvstr\ts16, [r7]\n+\tadds\tr7, r5, r4\n+\tvstr\ts8, [sl]\n+\tvcvt.f32.f64\ts13, d6\n+\tvstr\ts0, [r6]\n+\tvcvt.f64.f32\td2, s4\n+\tvstr\ts9, [lr]\n+\tadd.w\tlr, r0, r5\n+\tldr\tr6, [sp, #144]\t@ 0x90\n+\tstr\tr7, [sp, #88]\t@ 0x58\n+\tldr\tr7, [sp, #156]\t@ 0x9c\n+\tvldr\ts12, [lr]\n+\tldr\tr5, [sp, #104]\t@ 0x68\n+\tvstr\ts18, [ip]\n+\tvstr\ts10, [r7]\n+\tadd.w\tr7, r9, r5\n+\tvstr\ts11, [r6]\n+\tldr\tr6, [sp, #28]\n+\tvstr\ts13, [lr]\n+\tvcvt.f64.f32\td6, s12\n+\tadd\tr6, r9\n+\tvldr\ts10, [r7]\n+\tadd.w\tlr, r0, r5\n+\tadd\tr5, r4\n+\tstr\tr5, [sp, #104]\t@ 0x68\n+\tvadd.f64\td1, d3, d6\n+\tvsub.f64\td6, d3, d6\n+\tvldr\ts6, [r6]\n+\tvcvt.f64.f32\td5, s10\n+\tldr\tr5, [sp, #28]\n+\tvcvt.f64.f32\td3, s6\n+\tadd.w\tip, r0, r5\n+\tadd\tr5, r4\n+\tstr\tr5, [sp, #28]\n+\tldr\tr5, [sp, #128]\t@ 0x80\n+\tvldr\ts0, [ip]\n+\tvsub.f64\td4, d5, d3\n+\tvadd.f64\td5, d5, d3\n+\tvcvt.f64.f32\td0, s0\n+\tvmul.f64\td4, d4, d13\n+\tvadd.f64\td8, d4, d6\n+\tvsub.f64\td6, d6, d4\n+\tvldr\ts8, [lr]\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f32.f64\ts16, d8\n+\tvcvt.f32.f64\ts12, d6\n+\tvsub.f64\td3, d4, d0\n+\tvadd.f64\td4, d4, d0\n+\tvadd.f64\td0, d1, d4\n+\tvsub.f64\td1, d1, d4\n+\tvmul.f64\td3, d3, d13\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts2, d1\n+\tvstr\ts0, [r5]\n+\tvstr\ts2, [r1]\n+\tvstr\ts14, [lr]\n \tldr\tr1, [sp, #24]\n-\tadd\tr1, r6\n-\tstr\tr1, [sp, #24]\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tadd\tr3, r1\n-\tmov\tr1, lr\n-\tbeq.w\t80c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37f2>\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n-\tadd\tlr, r5\n-\tb.n\t7a36 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3166>\n-\tldr\tr4, [sp, #404]\t@ 0x194\n-\tmov\tlr, sl\n-\tstr\tr1, [sp, #36]\t@ 0x24\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #24]\n-\tstrd\tr7, ip, [sp, #48]\t@ 0x30\n-\tmov\tr1, r2\n-\tmov.w\tr8, #1\n-\tmov\tsl, r0\n-\tmov\tip, r2\n-\tstrd\tr6, r3, [sp, #40]\t@ 0x28\n+\tvstr\ts16, [r2]\n+\tadd.w\tr2, r9, r1\n+\tvstr\ts12, [ip]\n+\tadds\tr5, r1, r4\n+\tldr\tr1, [sp, #120]\t@ 0x78\n+\tstr\tr5, [sp, #24]\n+\tvldr\ts14, [r2]\n+\tvstr\ts22, [r2]\n+\tvstr\ts15, [r7]\n+\tvcvt.f64.f32\td7, s14\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tvadd.f64\td6, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvadd.f64\td4, d6, d5\n+\tvsub.f64\td6, d6, d5\n+\tvsub.f64\td5, d7, d3\n+\tvadd.f64\td7, d7, d3\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts8, [r1]\n+\tvstr\ts12, [r3]\n+\tvstr\ts10, [r2]\n \tldr\tr3, [sp, #0]\n-\tadd\tr3, r1\n-\tcmp\tr3, r9\n-\tbge.n\t7c96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33c6>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tvstr\ts14, [r6]\n+\tcmp\tr3, r2\n+\tbne.w\t7f96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33de>\n+\tstr\tr0, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr2, [sp, #316]\t@ 0x13c\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #0]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tcmp\tr2, r3\n+\tble.n\t83c0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3808>\n+\tldr\tr2, [sp, #296]\t@ 0x128\n+\tadd\tr3, r2\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr2, [sp, #180]\t@ 0xb4\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tcmp\tr3, r2\n+\tbne.w\t7db8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3200>\n+\tldrd\tr2, r8, [sp, #224]\t@ 0xe0\n+\tmov\tsl, r9\n+\tldr\tr1, [sp, #232]\t@ 0xe8\n+\tmov\tfp, r4\n+\tldr.w\tr9, [sp, #208]\t@ 0xd0\n+\tsubs\tr2, #1\n+\tldr\tr6, [sp, #200]\t@ 0xc8\n+\tadds\tr5, r2, #1\n+\tldr\tr7, [sp, #216]\t@ 0xd8\n+\tadd\tr1, r9\n+\tldr\tr4, [sp, #204]\t@ 0xcc\n+\tldr\tr0, [sp, #112]\t@ 0x70\n+\tbne.w\t7d9c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31e4>\n+\tldr\tr3, [sp, #400]\t@ 0x190\n+\tsubs\tr4, #1\n+\tldr\tr2, [sp, #172]\t@ 0xac\n+\tadds\tr1, r4, #1\n+\tadd\tr7, r3\n \tadd\tr2, r3\n-\tcmp\tr2, r9\n-\tbge.n\t7ca2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33d2>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #0]\n-\tadd\tr0, r2\n-\tcmp\tr0, r9\n-\tbge.n\t7cae <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33de>\n-\tldr\tr4, [sp, #88]\t@ 0x58\n-\tadd\tr0, r4\n-\tldr\tr4, [sp, #404]\t@ 0x194\n-\tcmp\tr4, #0\n-\tble.w\t7dde <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x350e>\n-\tlsls\tr0, r0, #2\n-\tstr\tr0, [sp, #20]\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tlsls\tr3, r3, #2\n-\tadd.w\tr6, lr, r3\n-\tlsls\tr5, r1, #2\n-\tadd\tr3, r0\n-\tstr\tr3, [sp, #12]\n-\tlsls\tr2, r2, #2\n-\tmovs\tr3, #1\n-\tstr\tr3, [sp, #8]\n-\tadd.w\tr7, lr, r2\n-\tldr\tr3, [sp, #12]\n-\tadd\tr2, r0\n-\tadd.w\tr4, lr, r5\n-\tadd\tr0, r5\n-\tstrd\tr8, r9, [sp, #56]\t@ 0x38\n-\tstrd\tr1, r5, [sp, #64]\t@ 0x40\n-\tldr\tr1, [sp, #8]\n-\tldr\tr5, [sp, #68]\t@ 0x44\n-\tadds\tr1, #1\n-\tstrd\tr1, r1, [sp, #8]\n-\tldr\tr1, [sp, #20]\n-\tsub.w\tr8, r4, r5\n-\tvldr\ts15, [r4, #-4]\n-\tsub.w\tr9, r0, r5\n-\tvldr\ts11, [r7, #-4]\n-\tadd\tr8, r1\n-\tvldr\ts12, [r0, #-4]\n-\tadd\tr9, r1\n-\tvldr\ts13, [r2, #-4]\n-\tvcvt.f64.f32\td16, s15\n-\tvcvt.f64.f32\td21, s11\n-\tvldr\ts14, [r6, #-4]\n-\tvcvt.f64.f32\td23, s12\n-\tvldr\ts15, [r8, #-4]\n-\tvcvt.f64.f32\td22, s13\n-\tvldr\ts10, [r3, #-4]\n-\tvcvt.f64.f32\td17, s14\n-\tldr\tr1, [sp, #12]\n-\tvsub.f64\td24, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvcvt.f64.f32\td19, s10\n-\tldr\tr5, [sp, #24]\n-\tvsub.f64\td21, d23, d22\n-\tvadd.f64\td23, d23, d22\n-\tvcvt.f64.f32\td22, s15\n-\tcmp\tr1, r5\n-\tvmov.f64\td26, d21\n-\tvsub.f64\td25, d17, d22\n-\tvadd.f64\td17, d17, d22\n-\tvadd.f64\td7, d16, d17\n-\tvsub.f64\td16, d16, d17\n-\tvfms.f64\td21, d25, d18\n-\tvfma.f64\td26, d25, d18\n-\tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d16\n-\tvstr\ts14, [r4, #-4]\n-\tadd\tr4, fp\n-\tvstr\ts15, [r7, #-4]\n-\tvcvt.f32.f64\ts13, d21\n-\tvldr\ts15, [r9, #-4]\n-\tvcvt.f32.f64\ts11, d26\n-\tadd\tr7, fp\n-\tvcvt.f64.f32\td21, s15\n-\tvsub.f64\td17, d19, d21\n-\tvadd.f64\td19, d19, d21\n-\tvmov.f64\td21, d24\n-\tvfma.f64\td21, d17, d20\n-\tvfma.f64\td24, d18, d17\n-\tvadd.f64\td22, d23, d19\n-\tvsub.f64\td19, d23, d19\n-\tvcvt.f32.f64\ts10, d22\n-\tvcvt.f32.f64\ts14, d19\n-\tvcvt.f32.f64\ts12, d21\n-\tvcvt.f32.f64\ts15, d24\n-\tvstr\ts10, [r0, #-4]\n-\tadd\tr0, fp\n-\tvstr\ts14, [r2, #-4]\n-\tadd\tr2, fp\n-\tvstr\ts11, [r3, #-4]\n-\tadd\tr3, fp\n-\tvstr\ts12, [r6, #-4]\n-\tadd\tr6, fp\n-\tvstr\ts13, [r9, #-4]\n-\tvstr\ts15, [r8, #-4]\n-\tbne.n\t7ce4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3414>\n-\tldrd\tr8, r9, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr1, r3\n-\tcmp\tr1, r9\n-\tbge.n\t7dea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x351a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #4]\n+\tstr\tr2, [sp, #172]\t@ 0xac\n+\tldr\tr2, [sp, #176]\t@ 0xb0\n+\tsub.w\tr3, r2, r3\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tbeq.w\t55f0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa38>\n+\tcmp.w\tr9, #0\n+\tbge.w\t7d7c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31c4>\n+\tldr\tr1, [sp, #184]\t@ 0xb8\n+\tldr\tr0, [sp, #172]\t@ 0xac\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr2, r0\n+\tcmp\tr3, r7\n+\tble.w\t7d8e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x31d6>\n+\tb.n\t83ee <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3836>\n+\tldr\tr1, [sp, #472]\t@ 0x1d8\n+\tldr\tr0, [sp, #444]\t@ 0x1bc\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr2, r0\n+\tcmp\tr3, r4\n+\tble.w\t56f4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb3c>\n+\tb.w\t5f56 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x139e>\n+\tldr\tr2, [sp, #408]\t@ 0x198\n+\tldr\tr1, [sp, #340]\t@ 0x154\n+\tsubs\tr4, r1, r2\n+\tnegs\tr1, r3\n+\tldr\tr3, [sp, #420]\t@ 0x1a4\n+\tadds\tr0, r4, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tmov\tfp, r0\n+\tldrd\tr2, r3, [sp, #408]\t@ 0x198\n+\tcmp\tr2, r3\n+\tble.w\t56c4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xb0c>\n+\tb.w\t5f78 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13c0>\n+\tldr.w\tr8, [sp, #484]\t@ 0x1e4\n+\tldr\tr3, [sp, #388]\t@ 0x184\n \tadd.w\tr8, r8, #1\n-\tcmp\tr8, r3\n-\tbne.w\t7c8a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33ba>\n-\tldrd\tr6, r3, [sp, #40]\t@ 0x28\n-\tmov\tr2, ip\n-\tldr\tr7, [sp, #48]\t@ 0x30\n-\tmov\tr0, sl\n-\tsubs\tr3, #1\n-\tldr.w\tip, [sp, #52]\t@ 0x34\n-\tadd\tr2, r7\n-\tadds\tr4, r3, #1\n-\tbne.w\t7c78 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x33a8>\n-\tldr\tr3, [sp, #400]\t@ 0x190\n-\tmov\tsl, lr\n-\tldr\tr1, [sp, #36]\t@ 0x24\n-\tcmp\tr3, #2\n-\tbne.w\t79dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x310c>\n-\tldr.w\tr9, [sp, #32]\n-\tb.w\t4b16 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x246>\n-\tldr\tr5, [sp, #24]\n+\tcmp\tr3, r8\n+\tbge.w\t4f6a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b2>\n+\tb.w\t605a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x14a2>\n \tnegs\tr1, r7\n-\tcmp\tip, r4\n-\tudiv\tr1, r5, r1\n-\tble.w\t7a6a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x319a>\n-\tb.n\t7c46 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3376>\n-\tldr\tr1, [sp, #184]\t@ 0xb8\n-\tadds\tr2, #8\n-\tmov.w\tr8, r3, lsl #3\n-\tlsls\tr3, r3, #4\n-\tadds\tr2, r1, r2\n-\tstr\tr2, [sp, #12]\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tsub.w\tr0, r6, ip\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd.w\tr3, r1, r8\n-\tadds\tr2, #1\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tadd.w\tlr, r3, r8\n-\tstr\tr0, [sp, #20]\n-\tstr.w\tsl, [sp, #24]\n-\tmov\tr0, r9\n-\tldr.w\tsl, [sp, #44]\t@ 0x2c\n-\tmov\tr4, lr\n-\tldr.w\tr9, [sp, #12]\n-\tsub.w\tr1, ip, r6\n-\tmov\tr5, r6\n-\tnegs\tr2, r7\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvldr\td23, [r3, #8]\n-\tcmp\tr7, #0\n-\tvldr\td24, [r4, #8]\n-\tvldr\td25, [r9]\n-\tvmul.f64\td23, d0, d23\n-\tvldr\td26, [r3]\n-\tvmul.f64\td24, d0, d24\n-\tvldr\td27, [r4]\n-\tvmul.f64\td25, d0, d25\n-\tvldr\td28, [r9, #-8]\n-\tblt.w\t80ac <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37dc>\n-\tudiv\tr3, r1, r7\n-\tcmp\tip, r5\n-\tblt.w\t8088 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37b8>\n-\tldr\tr2, [sp, #132]\t@ 0x84\n+\tsubs\tr0, r7, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr7, r4\n+\tstr\tr0, [sp, #436]\t@ 0x1b4\n+\tbge.w\t561a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa62>\n+\tb.n\t845e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38a6>\n+\tnegs\tr1, r2\n+\tnegs\tr0, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tr4, r0\n+\tble.w\t4fb2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3fa>\n+\tb.w\t55f0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xa38>\n \tcmp\tr2, #0\n-\tble.w\t8088 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37b8>\n-\tadds\tr2, r0, r5\n-\tstr\tr6, [sp, #44]\t@ 0x2c\n-\tstr\tr2, [sp, #12]\n-\tstrd\tr5, r8, [sp, #52]\t@ 0x34\n-\tstrd\tr1, r9, [sp, #60]\t@ 0x3c\n-\tldr.w\tr9, [sp, #12]\n-\tmovs\tr1, #1\n-\tstrd\tr7, r3, [sp, #68]\t@ 0x44\n-\tstrd\tip, r4, [sp, #76]\t@ 0x4c\n-\tstr.w\tlr, [sp, #84]\t@ 0x54\n-\tldr\tr3, [sp, #0]\n-\tadd.w\tr4, r3, r9\n-\tcmp\tr4, r0\n-\tbge.n\t7eda <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x360a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #0]\n-\tadds\tr5, r3, r4\n-\tcmp\tr5, r0\n-\tbge.n\t7ee6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3616>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr5, r3\n-\tldr\tr3, [sp, #0]\n-\tadd.w\tlr, r3, r5\n-\tcmp\tlr, r0\n-\tbge.n\t7ef4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3624>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tlr, r3\n-\tldr\tr3, [sp, #404]\t@ 0x194\n-\tcmp\tr3, #0\n-\tble.w\t804e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x377e>\n-\tldr\tr3, [sp, #24]\n-\tlsls\tr5, r5, #2\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n-\tlsls\tr4, r4, #2\n-\tmov.w\tr8, r9, lsl #2\n-\tadds\tr7, r3, r5\n-\tadd.w\tr2, r3, r8\n-\tadd\tr5, r6\n-\tadds\tr6, r3, r4\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tmov.w\tlr, lr, lsl #2\n-\tmov.w\tip, #1\n-\tadd\tr4, r3\n-\tadd\tr3, r8\n-\tstrd\tr1, r0, [sp, #92]\t@ 0x5c\n-\tvldr\ts10, [r2, #-4]\n-\tsub.w\tr0, r2, r8\n-\tvldr\ts11, [r7, #-4]\n-\tadd\tr0, lr\n-\tvldr\ts15, [r5, #-4]\n-\tsub.w\tr1, r3, r8\n-\tvcvt.f64.f32\td29, s10\n-\tvldr\ts12, [r6, #-4]\n-\tvcvt.f64.f32\td17, s11\n-\tvldr\ts14, [r3, #-4]\n-\tvcvt.f64.f32\td21, s15\n-\tvldr\ts15, [r0, #-4]\n-\tvcvt.f64.f32\td6, s12\n-\tadd\tr1, lr\n-\tvcvt.f64.f32\td22, s14\n-\tvldr\ts9, [r4, #-4]\n-\tvsub.f64\td30, d29, d17\n-\tvadd.f64\td29, d29, d17\n-\tvcvt.f64.f32\td17, s15\n-\tadd.w\tip, ip, #1\n-\tvcvt.f64.f32\td31, s9\n-\tcmp\tip, sl\n-\tvsub.f64\td16, d22, d21\n-\tvsub.f64\td5, d21, d22\n-\tvadd.f64\td22, d22, d21\n-\tvsub.f64\td7, d6, d17\n-\tvadd.f64\td17, d6, d17\n-\tvmov.f64\td21, d16\n-\tvsub.f64\td6, d29, d17\n-\tvadd.f64\td29, d29, d17\n-\tvfma.f64\td16, d7, d20\n-\tvfma.f64\td21, d18, d7\n-\tvfma.f64\td5, d18, d7\n-\tvcvt.f32.f64\ts15, d29\n-\tvstr\ts15, [r2, #-4]\n-\tadd\tr2, fp\n-\tvldr\ts15, [r1, #-4]\n-\tvmul.f64\td17, d28, d16\n-\tvmul.f64\td19, d25, d5\n-\tvnmul.f64\td29, d21, d23\n-\tvmul.f64\td21, d26, d21\n-\tvcvt.f64.f32\td16, s15\n-\tvsub.f64\td7, d31, d16\n-\tvadd.f64\td16, d31, d16\n-\tvmov.f64\td31, d30\n-\tvfma.f64\td31, d7, d20\n-\tvfma.f64\td30, d18, d7\n-\tvsub.f64\td5, d16, d22\n-\tvsub.f64\td7, d22, d16\n-\tvadd.f64\td16, d22, d16\n-\tvmul.f64\td5, d5, d24\n-\tvmul.f64\td22, d7, d27\n-\tvfma.f64\td5, d27, d6\n-\tvfma.f64\td22, d24, d6\n-\tvcvt.f32.f64\ts15, d16\n-\tvfma.f64\td29, d26, d31\n-\tvfma.f64\td21, d23, d31\n-\tvfma.f64\td19, d28, d30\n-\tvfma.f64\td17, d25, d30\n-\tvstr\ts15, [r3, #-4]\n-\tadd\tr3, fp\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts12, d22\n-\tvcvt.f32.f64\ts11, d29\n-\tvcvt.f32.f64\ts13, d21\n-\tvcvt.f32.f64\ts14, d19\n-\tvcvt.f32.f64\ts15, d17\n-\tvstr\ts11, [r6, #-4]\n-\tadd\tr6, fp\n-\tvstr\ts13, [r4, #-4]\n-\tadd\tr4, fp\n-\tvstr\ts10, [r7, #-4]\n-\tadd\tr7, fp\n-\tvstr\ts12, [r5, #-4]\n-\tadd\tr5, fp\n-\tvstr\ts14, [r0, #-4]\n-\tvstr\ts15, [r1, #-4]\n-\tbne.w\t7f24 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3654>\n-\tldrd\tr1, r0, [sp, #92]\t@ 0x5c\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr9, r3\n-\tcmp\tr9, r0\n-\tbge.n\t805a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x378a>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr9, r3\n-\tldr\tr3, [sp, #4]\n-\tadds\tr1, #1\n-\tcmp\tr1, r3\n-\tbne.w\t7ecc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35fc>\n-\tldrd\tr7, r3, [sp, #68]\t@ 0x44\n-\tldr\tr2, [sp, #12]\n-\tsubs\tr3, #1\n-\tldr.w\tlr, [sp, #84]\t@ 0x54\n-\tadd\tr2, r7\n-\tstr\tr2, [sp, #12]\n-\tldrd\tip, r4, [sp, #76]\t@ 0x4c\n-\tadds\tr2, r3, #1\n-\tbne.w\t7eba <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35ea>\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tldrd\tr5, r8, [sp, #52]\t@ 0x34\n-\tldrd\tr1, r9, [sp, #60]\t@ 0x3c\n-\tadd\tr5, r6\n-\tldr\tr3, [sp, #8]\n-\tsubs\tr1, r1, r6\n+\tble.w\t4f12 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35a>\n+\tmov\tr0, r2\n+\tadd.w\tr2, r1, #1073741824\t@ 0x40000000\n+\tadds\tr7, r0, r1\n+\tldr\tr0, [sp, #356]\t@ 0x164\n+\tsubs\tr2, #1\n+\tldr\tr4, [sp, #336]\t@ 0x150\n+\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tadd.w\tr0, r0, r7, lsl #2\n+\tldr\tr7, [sp, #332]\t@ 0x14c\n+\tlsls\tr2, r2, #2\n \tsubs\tr3, #1\n-\tstr\tr3, [sp, #8]\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tadds\tr2, #1\n-\tadd\tr4, r3\n-\tldr\tr3, [sp, #20]\n-\tadd\tr3, r6\n-\tstr\tr3, [sp, #20]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tadd\tr9, r3\n-\tmov\tr3, lr\n-\tbeq.n\t80bc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37ec>\n-\tadd\tlr, r8\n-\tb.n\t7e70 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35a0>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tcmp\tip, r5\n-\tldr\tr2, [sp, #20]\n-\tudiv\tr3, r2, r3\n-\tble.w\t7ea4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x35d4>\n-\tb.n\t8088 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37b8>\n-\tldr.w\tsl, [sp, #24]\n-\tmov\tr9, r0\n-\tldr\tr3, [sp, #28]\n-\tldr\tr2, [sp, #192]\t@ 0xc0\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #28]\n-\tcmp\tr2, r3\n-\tbge.w\t7814 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f44>\n-\tldr.w\tr9, [sp, #32]\n-\tb.w\t49e4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x114>\n-\tsubs\tr0, r6, r2\n-\tnegs\tr1, r6\n-\tcmp\tr6, r2\n-\tudiv\tr1, r0, r1\n-\tstr\tr1, [sp, #8]\n-\tbge.w\t79f4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3124>\n-\tb.n\t80c2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x37f2>\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tnegs\tr3, r7\n-\tcmp.w\tip, #0\n-\tudiv\tr3, r2, r3\n-\tble.w\t7838 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2f68>\n-\tb.n\t79d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3104>\n-\tldr\tr2, [sp, #240]\t@ 0xf0\n-\tcmp\tr3, r0\n-\tudiv\tr2, r4, r2\n-\tble.w\t5548 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xc78>\n-\tb.w\t5c96 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13c6>\n-\tldr\tr0, [sp, #188]\t@ 0xbc\n-\trsb\tr2, ip, #0\n-\tsub.w\tr3, r8, r0\n-\tadds\tr1, r3, r4\n-\tudiv\tr6, r1, r2\n-\tldr\tr2, [sp, #168]\t@ 0xa8\n-\tcmp\tr0, r2\n-\tble.w\t551e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xc4e>\n-\tb.w\t5cb0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x13e0>\n-\tmov\tfp, r8\n-\tldr\tr3, [sp, #204]\t@ 0xcc\n-\tldr\tr2, [sp, #180]\t@ 0xb4\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #204]\t@ 0xcc\n-\tcmp\tr2, r3\n-\tbge.w\t4df4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x524>\n-\tldr.w\tr9, [sp, #236]\t@ 0xec\n-\tb.w\t4b16 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x246>\n-\tsubs\tr0, r4, r3\n+\tadd\tr7, r2\n+\tadd\tr2, r4\n+\tldr\tr4, [sp, #332]\t@ 0x14c\n+\tlsls\tr3, r3, #2\n+\tadd.w\tfp, r4, r3\n+\tldr\tr4, [sp, #336]\t@ 0x150\n+\tadd\tr3, r4\n+\tldr\tr4, [sp, #0]\n+\tvldr\ts8, [r7]\n+\tvldr\ts10, [fp]\n+\tvldr\ts9, [r3]\n+\tvldr\ts11, [r2]\n+\tvcvt.f64.f32\td6, s8\n+\tvcvt.f64.f32\td2, s10\n+\tvadd.f32\ts10, s10, s8\n+\tvcvt.f64.f32\td7, s9\n+\tvcvt.f64.f32\td3, s11\n+\tvadd.f32\ts11, s11, s9\n+\tvsub.f64\td6, d6, d2\n+\tvstmia\tr7!, {s10}\n+\tcmp\tr7, r0\n+\tvsub.f64\td7, d7, d3\n+\tvstmia\tr2!, {s11}\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td7, d7, d13\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr3!, {s12}\n+\tvstmia\tfp!, {s14}\n+\tbne.n\t84c8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3910>\n+\tb.w\t4f10 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x358>\n+\tldr\tr1, [sp, #28]\n+\tldr\tr0, [sp, #8]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tcmp\tr3, r9\n+\tble.w\t4e50 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x298>\n+\tb.w\t4f3a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x382>\n \tnegs\tr1, r4\n-\tcmp\tr4, r3\n-\tudiv\tr1, r0, r1\n-\tstr\tr1, [sp, #200]\t@ 0xc8\n-\tbge.w\t548c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0xbbc>\n-\tb.n\t812a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x385a>\n-\tsubs\tr1, r2, r3\n-\tnegs\tr2, r2\n-\tcmp\tr0, r3\n-\tudiv\tr2, r1, r2\n-\tblt.w\t4dde <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x50e>\n-\tldr\tr0, [sp, #152]\t@ 0x98\n-\tldr\tr3, [sp, #392]\t@ 0x188\n-\tmov.w\tr8, r0, lsl #3\n+\tsubs\tr0, r4, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r6\n+\tmov\tfp, r0\n+\tblt.w\t4f5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a2>\n+\tldr\tr1, [sp, #364]\t@ 0x16c\n+\tldr\tr3, [sp, #608]\t@ 0x260\n \tcmp\tr3, #1\n-\tbeq.w\t4c84 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b4>\n-\tldrd\tr1, r4, [sp, #144]\t@ 0x90\n-\tmov\tlr, r0\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\trsb\tr5, ip, #0\n-\tldr\tr3, [sp, #184]\t@ 0xb8\n-\tsubs\tr6, r1, r4\n-\tadds\tr0, #1\n-\tstr.w\tr9, [sp, #20]\n+\tmov.w\tr3, r1, lsl #3\n+\tbeq.w\t4e0c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x254>\n+\tldr\tr2, [sp, #360]\t@ 0x168\n+\tmov\tr8, r1\n+\tldr\tr0, [sp, #340]\t@ 0x154\n+\tldr\tr4, [sp, #404]\t@ 0x194\n+\tmov\tr9, r2\n+\tsubs\tr5, r2, r0\n+\tsubs\tr0, r0, r2\n+\tldr\tr2, [sp, #344]\t@ 0x158\n+\tadds\tr6, r4, r3\n+\tmov\tr4, r3\n+\tmov\tr3, r5\n+\tadds\tr2, #1\n+\tldr\tr5, [sp, #380]\t@ 0x17c\n+\tstr\tr2, [sp, #24]\n+\tldr\tr2, [sp, #620]\t@ 0x26c\n \tstr\tr0, [sp, #8]\n-\tsubs\tr7, r4, r1\n-\tldr\tr0, [sp, #404]\t@ 0x194\n-\tadd\tr3, r8\n-\tldr.w\tr9, [sp, #172]\t@ 0xac\n-\tmov\tr4, r8\n-\tadd.w\tfp, r0, #1\n-\tstr.w\tsl, [sp, #12]\n-\tstr.w\tfp, [sp, #4]\n-\tvldr\td19, [r3, #8]\n-\tcmp.w\tip, #0\n-\tvldr\td22, [r3]\n-\tvmul.f64\td19, d0, d19\n-\tblt.w\t8394 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ac4>\n-\tudiv\tr8, r7, ip\n-\tldr\tr0, [sp, #148]\t@ 0x94\n-\tcmp\tr0, r1\n-\tblt.n\t82b8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39e8>\n-\tldr\tr0, [sp, #132]\t@ 0x84\n-\tcmp\tr0, #0\n-\tble.n\t82b8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39e8>\n-\tldr\tr0, [sp, #16]\n-\tmov\tsl, r4\n-\tstrd\tr2, r1, [sp, #24]\n-\tmov\tr4, r6\n-\tadd\tr0, r1\n-\tmov\tr1, r3\n-\tldr\tr6, [sp, #160]\t@ 0xa0\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #16]\n+\tnegs\tr2, r7\n+\tstrd\tr2, sl, [sp, #28]\n+\tvldr\td8, [r6, #8]\n+\tcmp\tr7, #0\n+\tvldr\td7, [sp, #392]\t@ 0x188\n+\tvldr\td9, [r6]\n+\tvmul.f64\td8, d7, d8\n+\tblt.w\t878a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3bd2>\n+\tldr\tr0, [sp, #8]\n+\tmov\tr1, r7\n+\tstr\tr3, [sp, #0]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n \tmov\tr2, r0\n-\tstrd\tip, r8, [sp, #32]\n-\tstr\tr0, [sp, #40]\t@ 0x28\n-\tstr\tr1, [sp, #0]\n-\tldr\tr3, [sp, #12]\n-\tldr\tr1, [sp, #16]\n-\tadd\tr3, r2\n-\tcmp\tr3, r1\n-\tbge.n\t81ea <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x391a>\n-\tldr\tr1, [sp, #88]\t@ 0x58\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #220]\t@ 0xdc\n-\tcmp\tlr, r1\n-\tldr\tr1, [sp, #404]\t@ 0x194\n-\tbeq.w\t830c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a3c>\n+\tcmp\tr3, r9\n+\tldr\tr3, [sp, #0]\n+\tblt.n\t869a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ae2>\n+\tldr\tr1, [sp, #344]\t@ 0x158\n \tcmp\tr1, #0\n-\tble.n\t8284 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39b4>\n-\tmov.w\tfp, r3, lsl #2\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tlsls\tr0, r2, #2\n-\tadd.w\tr8, r1, r0\n-\tadd.w\tip, r1, fp\n-\tadd\tr0, r3\n-\tldr\tr1, [sp, #0]\n-\tadd\tr3, fp\n-\tldr.w\tfp, [sp, #160]\t@ 0xa0\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tvldr\ts15, [r0, #-4]\n+\tble.n\t869a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ae2>\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tmov\tlr, r6\n+\tstr.w\tfp, [sp, #40]\t@ 0x28\n+\tadd.w\tr0, r1, r9\n+\tstr.w\tr9, [sp, #48]\t@ 0x30\n+\tldr.w\tr9, [sp, #372]\t@ 0x174\n+\tmov\tr6, r0\n+\tstr\tr7, [sp, #56]\t@ 0x38\n+\tstr\tr2, [sp, #0]\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #32]\n+\tadds\tr1, r3, r6\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr1, r3\n+\titt\tlt\n+\tldrlt\tr3, [sp, #296]\t@ 0x128\n+\taddlt\tr1, r1, r3\n+\tldr\tr3, [sp, #448]\t@ 0x1c0\n+\tcmp\tr8, r3\n+\tldr\tr3, [sp, #620]\t@ 0x26c\n+\tbeq.w\t8706 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b4e>\n+\tcmp\tr3, #0\n+\tble.n\t866a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ab2>\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tlsls\tr1, r1, #2\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tlsls\tr7, r6, #2\n+\tldr.w\tfp, [sp, #372]\t@ 0x174\n+\tadd.w\tsl, r3, r7\n+\tadd.w\tip, r3, r1\n+\tadd\tr7, r2\n+\tadd\tr1, r2\n+\tldr\tr2, [sp, #0]\n+\tvldr\ts13, [r7, #-4]\n \tadd.w\tfp, fp, #1\n-\tvldr\ts13, [r3, #-4]\n-\tvldr\ts14, [r8, #-4]\n-\tvldr\ts12, [ip, #-4]\n-\tvcvt.f64.f32\td16, s15\n-\tvcvt.f64.f32\td23, s13\n-\tvadd.f32\ts15, s15, s13\n-\tvcvt.f64.f32\td21, s14\n-\tldr\tr2, [sp, #4]\n-\tvcvt.f64.f32\td17, s12\n-\tvadd.f32\ts14, s14, s12\n-\tcmp\tfp, r2\n-\tvsub.f64\td16, d16, d23\n-\tvstr\ts15, [r0, #-4]\n-\tadd\tr0, r9\n-\tvsub.f64\td21, d21, d17\n-\tvstr\ts14, [r8, #-4]\n-\tadd\tr8, r9\n-\tvnmul.f64\td17, d16, d19\n-\tvmul.f64\td16, d22, d16\n-\tvfma.f64\td17, d22, d21\n-\tvfma.f64\td16, d19, d21\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts15, d16\n-\tvstr\ts14, [ip, #-4]\n-\tadd\tip, r9\n-\tvstr\ts15, [r3, #-4]\n-\tadd\tr3, r9\n-\tbne.n\t8216 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3946>\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tstr\tr1, [sp, #0]\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr2, r3\n+\tvldr\ts9, [r1, #-4]\n+\tvldr\ts12, [sl, #-4]\n+\tvcvt.f64.f32\td7, s13\n+\tvldr\ts8, [ip, #-4]\n+\tvcvt.f64.f32\td2, s9\n+\tvadd.f32\ts13, s13, s9\n+\tvcvt.f64.f32\td5, s12\n \tldr\tr3, [sp, #16]\n-\tcmp\tr2, r3\n-\tbge.n\t8292 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39c2>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #8]\n-\tadds\tr6, #1\n+\tvadd.f32\ts12, s12, s8\n+\tvcvt.f64.f32\td3, s8\n+\tcmp\tfp, r3\n+\tvsub.f64\td7, d7, d2\n+\tvstr\ts13, [r7, #-4]\n+\tadd\tr7, r5\n+\tvstr\ts12, [sl, #-4]\n+\tvsub.f64\td5, d5, d3\n+\tadd\tsl, r5\n+\tvmul.f64\td6, d8, d7\n+\tvmul.f64\td7, d9, d7\n+\tvmla.f64\td7, d8, d5\n+\tvnmls.f64\td6, d9, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts14, [r1, #-4]\n+\tadd\tr1, r5\n+\tvstr\ts12, [ip, #-4]\n+\tadd\tip, r5\n+\tbne.n\t85fe <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a46>\n+\tstr\tr2, [sp, #0]\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tr6, r3\n-\tbne.n\t81dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x390c>\n-\tldrd\tip, r8, [sp, #32]\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tldr\tr1, [sp, #0]\n-\tadd\tr0, ip\n-\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n-\tbne.n\t81d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3900>\n-\tmov\tr3, r1\n-\tldr\tr2, [sp, #24]\n-\tldr\tr1, [sp, #28]\n-\tmov\tr6, r4\n-\tmov\tr4, sl\n-\tldr\tr0, [sp, #152]\t@ 0x98\n+\tbge.n\t8678 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ac0>\n+\tldr\tr3, [sp, #296]\t@ 0x128\n+\tadd\tr6, r3\n+\tldr\tr3, [sp, #24]\n+\tadd.w\tr9, r9, #1\n+\tcmp\tr9, r3\n+\tbne.n\t85c8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a10>\n+\tldr\tr2, [sp, #0]\n+\tldr\tr7, [sp, #56]\t@ 0x38\n \tsubs\tr2, #1\n-\tadd\tr3, r4\n-\tadd\tlr, r0\n-\tldr\tr0, [sp, #144]\t@ 0x90\n-\tadd\tr1, r0\n-\tadd\tr6, r0\n-\tsubs\tr7, r7, r0\n-\tadds\tr0, r2, #1\n-\tbne.w\t819e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38ce>\n-\tb.w\t4dda <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x50a>\n-\tand.w\tr3, r2, #3\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr0, r7\n+\tadds\tr1, r2, #1\n+\tbne.n\t85bc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a04>\n+\tldr.w\tfp, [sp, #40]\t@ 0x28\n+\tmov\tr6, lr\n+\tldr.w\tr9, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #364]\t@ 0x16c\n+\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n+\tldr\tr1, [sp, #8]\n+\tadd\tr6, r4\n+\tadd\tr8, r2\n+\tldr\tr2, [sp, #360]\t@ 0x168\n+\tcmp.w\tfp, #4294967295\t@ 0xffffffff\n+\tadd\tr9, r2\n+\tadd\tr3, r2\n+\tsub.w\tr2, r1, r2\n+\tstr\tr2, [sp, #8]\n+\tbne.w\t857c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39c4>\n+\tb.w\t4f5a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a2>\n+\tldr\tr3, [sp, #616]\t@ 0x268\n+\tand.w\tr3, r3, #3\n+\tstr\tr3, [sp, #372]\t@ 0x174\n \tcmp\tr3, #1\n-\tbeq.w\t86cc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3dfc>\n+\tbeq.w\t8ac8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3f10>\n \tcmp\tr3, #3\n-\tbeq.w\t86da <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3e0a>\n-\tmovs\tr3, #0\n-\tstrd\tr3, r3, [sp, #160]\t@ 0xa0\n-\tb.w\t491e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4e>\n-\tadd\tsp, #292\t@ 0x124\n-\tvpop\t{d8-d15}\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tittee\tne\n+\tmovne\tr3, #0\n+\tstrdne\tr3, r3, [sp, #372]\t@ 0x174\n+\tldreq\tr3, [sp, #616]\t@ 0x268\n+\tsubeq\tr3, #3\n+\titttt\teq\n+\tasreq\tr3, r3, #1\n+\tstreq\tr3, [sp, #388]\t@ 0x184\n+\tmoveq\tr3, #0\n+\tstreq\tr3, [sp, #372]\t@ 0x174\n+\tb.w\t4c1c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x64>\n \tmov\tr2, r3\n \tasrs\tr3, r3, #1\n \tadds\tr3, #1\n \tbic.w\tr3, r3, #1\n-\tstr\tr3, [sp, #404]\t@ 0x194\n-\tsub.w\tr9, r2, r3\n-\tb.w\t49d8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x108>\n-\tcmp\tr1, #0\n-\tble.n\t8284 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39b4>\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tlsls\tr0, r2, #2\n-\tlsls\tr3, r3, #2\n-\tldr.w\tfp, [sp, #160]\t@ 0xa0\n-\tadd.w\tr8, r1, r0\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tr0, r1\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tadd.w\tip, r1, r3\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tadd\tr3, r1\n-\tldr\tr1, [sp, #0]\n-\tvldr\ts14, [r8, #-4]\n+\tstr\tr3, [sp, #620]\t@ 0x26c\n+\tsubs\tr2, r2, r3\n+\tstr\tr2, [sp, #440]\t@ 0x1b8\n+\tb.w\t4ce0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x128>\n+\tadd\tsp, #508\t@ 0x1fc\n+\tvpop\t{d8-d15}\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tcmp\tr3, #0\n+\tble.n\t866a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ab2>\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tlsls\tr7, r6, #2\n+\tldr\tr2, [sp, #336]\t@ 0x150\n+\tlsls\tr1, r1, #2\n+\tadd.w\tsl, r3, r7\n+\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tadd\tr7, r2\n+\tldr.w\tfp, [sp, #372]\t@ 0x174\n+\tadd.w\tip, r3, r1\n+\tadd\tr1, r2\n+\tldr\tr2, [sp, #0]\n+\tvldr\ts10, [sl, #-4]\n \tadd.w\tfp, fp, #1\n-\tvldr\ts12, [ip, #-4]\n-\tvldr\ts15, [r3, #-4]\n-\tvldr\ts13, [r0, #-4]\n-\tvcvt.f64.f32\td17, s14\n-\tvcvt.f64.f32\td23, s12\n-\tvadd.f32\ts14, s14, s12\n-\tvcvt.f64.f32\td16, s15\n-\tldr\tr2, [sp, #4]\n-\tvcvt.f64.f32\td21, s13\n-\tvadd.f32\ts15, s15, s13\n-\tcmp\tfp, r2\n-\tvsub.f64\td17, d17, d23\n-\tvstr\ts14, [r8, #-4]\n-\tadd\tr8, r9\n-\tvsub.f64\td16, d16, d21\n-\tvstr\ts15, [r0, #-4]\n-\tadd\tr0, r9\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts15, d16\n-\tvstr\ts14, [r3, #-4]\n-\tadd\tr3, r9\n-\tvstr\ts15, [ip, #-4]\n-\tadd\tip, r9\n-\tbne.n\t8330 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3a60>\n-\tb.n\t8280 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39b0>\n-\tudiv\tr8, r6, r5\n-\tldr\tr0, [sp, #148]\t@ 0x94\n-\tcmp\tr0, r1\n-\tble.w\t81bc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x38ec>\n-\tb.n\t82b8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39e8>\n-\tsubs\tr2, r4, r0\n-\tnegs\tr3, r4\n-\tcmp\tr4, r0\n-\tudiv\tip, r2, r3\n-\tbge.w\t6c22 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2352>\n-\tb.w\t70a0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x27d0>\n-\tldr\tr4, [sp, #132]\t@ 0x84\n-\tvneg.f64\td22, d16\n-\tldr\tr2, [sp, #16]\n-\tadds\tr4, #1\n-\tldr.w\tr8, [sp, #172]\t@ 0xac\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #404]\t@ 0x194\n-\tadds\tr4, #1\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tldr\tr4, [sp, #164]\t@ 0xa4\n+\tvldr\ts8, [ip, #-4]\n+\tvldr\ts11, [r1, #-4]\n+\tvldr\ts9, [r7, #-4]\n+\tvcvt.f64.f32\td6, s10\n+\tvcvt.f64.f32\td2, s8\n+\tvadd.f32\ts10, s10, s8\n+\tvcvt.f64.f32\td7, s11\n+\tldr\tr3, [sp, #16]\n+\tvcvt.f64.f32\td3, s9\n+\tvadd.f32\ts11, s11, s9\n+\tcmp\tfp, r3\n+\tvsub.f64\td6, d6, d2\n+\tvstr\ts10, [sl, #-4]\n+\tadd\tsl, r5\n+\tvsub.f64\td7, d7, d3\n+\tvstr\ts11, [r7, #-4]\n+\tadd\tr7, r5\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td7, d7, d13\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts12, [r1, #-4]\n+\tadd\tr1, r5\n+\tvstr\ts14, [ip, #-4]\n+\tadd\tip, r5\n+\tbne.n\t8726 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b6e>\n+\tb.n\t8668 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ab0>\n+\tmov\tr0, r3\n+\tldr\tr1, [sp, #28]\n+\tstr\tr3, [sp, #0]\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [sp, #340]\t@ 0x154\n+\tmov\tr2, r0\n+\tcmp\tr3, r9\n+\tldr\tr3, [sp, #0]\n+\tble.w\t85a6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x39ee>\n+\tb.n\t869a <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3ae2>\n+\tnegs\tr1, r4\n+\tsub.w\tr0, r4, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r8\n+\tmov\tsl, r0\n+\tbge.w\t7104 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x254c>\n+\tb.w\t75d4 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2a1c>\n+\tldr\tr1, [sp, #344]\t@ 0x158\n+\tldr\tr2, [sp, #152]\t@ 0x98\n+\tadds\tr1, #1\n+\tldr.w\tr9, [sp, #380]\t@ 0x17c\n+\tstr\tr1, [sp, #8]\n+\tldr\tr1, [sp, #620]\t@ 0x26c\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr1, [sp, #376]\t@ 0x178\n \tmov\tsl, r2\n-\tstr\tr4, [sp, #36]\t@ 0x24\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n-\tstrd\tr3, r9, [sp, #52]\t@ 0x34\n-\tstrd\tr1, r2, [sp, #60]\t@ 0x3c\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tstr.w\tr8, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr7, [sp, #96]\t@ 0x60\n+\tstr\tr2, [sp, #104]\t@ 0x68\n \tldr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tadd\tr3, sl\n+\tldr\tr6, [sp, #152]\t@ 0x98\n \tcmp\tr3, r2\n-\tbge.n\t83e8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b18>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr3, r2\n+\tldr\tr7, [sp, #152]\t@ 0x98\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr3, r3, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr1, r2, r3\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr1, r2\n-\tbge.n\t83f6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b26>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr1, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr1, r1, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr5, r2, r1\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr5, r2\n-\tbge.n\t8404 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b34>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr5, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr5, r5, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr0, r2, r5\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr0, r2\n-\tbge.n\t8412 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b42>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr0, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr0, r0, r2\n \tldr\tr2, [sp, #0]\n \tadds\tr4, r2, r0\n-\tldr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #152]\t@ 0x98\n \tcmp\tr4, r2\n-\tbge.n\t8420 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b50>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tadd\tr4, r2\n+\titt\tlt\n+\tldrlt\tr2, [sp, #296]\t@ 0x128\n+\taddlt\tr4, r4, r2\n \tldr\tr2, [sp, #0]\n-\tldr\tr6, [sp, #16]\n \tadd\tr2, r4\n \tcmp\tr2, r6\n-\tbge.n\t842e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b5e>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tadd\tr2, r6\n+\titt\tlt\n+\tldrlt\tr6, [sp, #296]\t@ 0x128\n+\taddlt\tr2, r2, r6\n \tldr\tr6, [sp, #0]\n-\tldr\tr7, [sp, #16]\n \tadd\tr6, r2\n \tcmp\tr6, r7\n-\tbge.n\t843c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b6c>\n-\tldr\tr7, [sp, #88]\t@ 0x58\n-\tadd\tr6, r7\n-\tldr\tr7, [sp, #404]\t@ 0x194\n+\titt\tlt\n+\tldrlt\tr7, [sp, #296]\t@ 0x128\n+\taddlt\tr6, r6, r7\n+\tldr\tr7, [sp, #620]\t@ 0x26c\n \tcmp\tr7, #0\n-\tble.w\t8698 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3dc8>\n+\tble.w\t8a94 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3edc>\n \tlsls\tr7, r5, #2\n \tlsls\tr5, r6, #2\n-\tstr\tr7, [sp, #12]\n+\tstr\tr7, [sp, #24]\n \tlsls\tr0, r0, #2\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n+\tldr\tr7, [sp, #336]\t@ 0x150\n \tlsls\tr1, r1, #2\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tlsls\tr2, r2, #2\n-\tstr\tr5, [sp, #20]\n+\tstr\tr5, [sp, #28]\n \tlsls\tr3, r3, #2\n \tmov.w\tr5, sl, lsl #2\n-\tadd.w\tr9, r6, r0\n+\tadd.w\tr8, r6, r0\n \tadd.w\tfp, r6, r5\n \tadd.w\tlr, r6, r1\n \tadd.w\tip, r6, r2\n \tadd\tr5, r7\n \tadd\tr2, r7\n \tadd\tr0, r7\n \tadd\tr1, r7\n-\tstr\tr2, [sp, #8]\n+\tstr\tr2, [sp, #16]\n \tadds\tr2, r6, r3\n \tadd\tr3, r7\n-\tstr\tr2, [sp, #24]\n+\tstr\tr2, [sp, #32]\n \tmov\tr2, r7\n-\tldr\tr7, [sp, #12]\n+\tldr\tr7, [sp, #24]\n \tlsls\tr4, r4, #2\n-\tstr.w\tsl, [sp, #68]\t@ 0x44\n+\tstr.w\tsl, [sp, #112]\t@ 0x70\n \tadd\tr6, r7\n-\tstr\tr6, [sp, #32]\n-\tldr\tr6, [sp, #120]\t@ 0x78\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tldr\tr6, [sp, #332]\t@ 0x14c\n \tadds\tr7, r2, r7\n-\tmov\tr2, r7\n+\tstr\tr7, [sp, #64]\t@ 0x40\n \tadds\tr7, r6, r4\n-\tstr\tr7, [sp, #12]\n-\tldr\tr7, [sp, #124]\t@ 0x7c\n-\tadd\tr4, r7\n-\tldr\tr7, [sp, #20]\n+\tstr\tr7, [sp, #24]\n+\tldr\tr7, [sp, #28]\n+\tadd\tr4, r2\n \tadd\tr6, r7\n-\tstr\tr6, [sp, #20]\n-\tldr\tr6, [sp, #124]\t@ 0x7c\n+\tstr\tr6, [sp, #28]\n+\tmov\tr6, r2\n \tadd\tr6, r7\n-\tldr\tr7, [sp, #164]\t@ 0xa4\n+\tldr\tr7, [sp, #376]\t@ 0x178\n \tmov\tsl, r6\n-\tstr\tr7, [sp, #28]\n-\tldr\tr7, [sp, #24]\n-\tstr\tr3, [sp, #24]\n-\tvldr\ts15, [r5, #-4]\n-\tvldr\ts7, [r0, #-4]\n-\tvldr\ts8, [lr, #-4]\n-\tvldr\ts9, [ip, #-4]\n-\tvcvt.f64.f32\td17, s15\n-\tldr\tr3, [sp, #8]\n-\tvcvt.f64.f32\td24, s7\n-\tvldr\ts14, [fp, #-4]\n-\tvcvt.f64.f32\td26, s8\n-\tvldr\ts12, [r9, #-4]\n-\tvcvt.f64.f32\td27, s9\n-\tvldr\ts10, [r1, #-4]\n-\tvldr\ts11, [r3, #-4]\n-\tvsub.f64\td23, d17, d24\n-\tvcvt.f64.f32\td19, s14\n+\tstr\tr7, [sp, #40]\t@ 0x28\n+\tldr\tr7, [sp, #32]\n+\tstr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #16]\n+\tvldr\ts6, [lr, #-4]\n+\tvldr\ts12, [ip, #-4]\n+\tvldr\ts8, [r1, #-4]\n+\tvldr\ts2, [r3, #-4]\n+\tvcvt.f64.f32\td3, s6\n \tvcvt.f64.f32\td6, s12\n-\tvsub.f64\td28, d26, d27\n-\tvcvt.f64.f32\td21, s10\n-\tvcvt.f64.f32\td25, s11\n-\tvadd.f64\td26, d26, d27\n-\tvmov.f64\td5, d23\n-\tvadd.f64\td17, d17, d24\n-\tvsub.f64\td29, d19, d6\n-\tvadd.f64\td19, d19, d6\n-\tvfma.f64\td5, d16, d28\n-\tvfma.f64\td23, d22, d28\n-\tvsub.f64\td27, d21, d25\n-\tvadd.f64\td21, d21, d25\n-\tldr\tr6, [sp, #28]\n-\tvmov.f64\td6, d29\n-\tvadd.f64\td4, d19, d26\n+\tvldr\ts10, [fp, #-4]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts4, [r8, #-4]\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts16, [r5, #-4]\n+\tvldr\ts14, [r0, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td2, s4\n+\tvsub.f64\td0, d3, d6\n+\tvcvt.f64.f32\td8, s16\n+\tvadd.f64\td3, d3, d6\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td6, d4, d1\n+\tvadd.f64\td4, d4, d1\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tvadd.f64\td1, d5, d2\n+\tvmul.f64\td0, d0, d14\n+\tvsub.f64\td5, d5, d2\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tvadd.f64\td2, d8, d7\n+\tvmul.f64\td6, d6, d14\n+\tvsub.f64\td7, d8, d7\n \tadds\tr6, #1\n-\tstr\tr6, [sp, #28]\n-\tvfma.f64\td6, d27, d22\n-\tvsub.f64\td19, d19, d26\n-\tvadd.f64\td26, d17, d21\n-\tvsub.f64\td17, d17, d21\n-\tvfma.f64\td29, d16, d27\n+\tvadd.f64\td8, d1, d3\n+\tvsub.f64\td1, d1, d3\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tvadd.f64\td3, d2, d4\n+\tvsub.f64\td2, d2, d4\n+\tvsub.f64\td4, d5, d6\n+\tvadd.f64\td6, d5, d6\n+\tvadd.f64\td5, d0, d7\n+\tvsub.f64\td7, d7, d0\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts16, d8\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts4, d2\n \tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts11, d23\n-\tvcvt.f32.f64\ts14, d19\n-\tmov\tr6, r2\n-\tvcvt.f32.f64\ts9, d26\n-\tvcvt.f32.f64\ts15, d17\n-\tvstr\ts8, [fp, #-4]\n-\tadd\tfp, r8\n \tvcvt.f32.f64\ts12, d6\n-\tvstr\ts14, [r9, #-4]\n-\tvstr\ts9, [r5, #-4]\n-\tadd\tr9, r8\n-\tvstr\ts15, [r0, #-4]\n-\tvcvt.f32.f64\ts13, d29\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts16, [fp, #-4]\n+\tadd\tfp, r9\n+\tvstr\ts6, [r5, #-4]\n+\tadd\tr5, r9\n+\tvstr\ts4, [r0, #-4]\n+\tadd\tr0, r9\n \tvstr\ts10, [r1, #-4]\n-\tadd\tr5, r8\n-\tvstr\ts11, [r3, #-4]\n-\tadd\tr0, r8\n+\tadd\tr1, r9\n+\tvstr\ts14, [r3, #-4]\n \tldr\tr3, [sp, #24]\n-\tadd\tr1, r8\n-\tvstr\ts12, [lr, #-4]\n-\tadd\tlr, r8\n-\tvstr\ts13, [ip, #-4]\n-\tadd\tip, r8\n-\tvldr\ts13, [r2, #-4]\n-\tvldr\ts12, [r3, #-4]\n-\tldr\tr3, [sp, #12]\n+\tvstr\ts2, [r8, #-4]\n+\tadd\tr8, r9\n+\tvstr\ts8, [lr, #-4]\n+\tadd\tlr, r9\n+\tvstr\ts12, [ip, #-4]\n+\tadd\tip, r9\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tvldr\ts0, [r2, #-4]\n+\tvldr\ts14, [r3, #-4]\n \tldr\tr2, [sp, #32]\n-\tvcvt.f64.f32\td24, s13\n-\tvcvt.f64.f32\td21, s12\n-\tvldr\ts14, [r7, #-4]\n+\tldr\tr3, [sp, #28]\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts10, [r7, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts2, [r6, #-4]\n+\tvldr\ts8, [r2, #-4]\n \tvldr\ts12, [r3, #-4]\n-\tldr\tr3, [sp, #20]\n-\tvcvt.f64.f32\td17, s14\n-\tvldr\ts15, [r2, #-4]\n-\tvsub.f64\td19, d21, d24\n-\tvldr\ts14, [r4, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts4, [r4, #-4]\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts6, [sl, #-4]\n+\tvcvt.f64.f32\td4, s8\n \tvcvt.f64.f32\td6, s12\n-\tvadd.f64\td21, d21, d24\n-\tldr\tr2, [sp, #24]\n-\tvcvt.f64.f32\td23, s15\n-\tvldr\ts11, [r3, #-4]\n-\tvldr\ts15, [sl, #-4]\n-\tvcvt.f64.f32\td28, s14\n-\tvsub.f64\td26, d19, d6\n-\tvcvt.f64.f32\td29, s11\n-\tvcvt.f64.f32\td27, s15\n-\tvsub.f64\td7, d17, d23\n-\tvadd.f64\td17, d17, d23\n-\tvadd.f64\td31, d6, d29\n-\tvsub.f64\td19, d19, d29\n-\tvadd.f64\td30, d28, d27\n-\tvsub.f64\td24, d7, d27\n-\tvsub.f64\td23, d7, d28\n-\tvadd.f64\td26, d26, d29\n-\tvadd.f64\td4, d31, d21\n-\tvadd.f64\td19, d19, d6\n-\tvsub.f64\td25, d17, d30\n-\tvadd.f64\td17, d17, d30\n-\tvadd.f64\td24, d24, d28\n-\tvadd.f64\td23, d23, d27\n-\tvsub.f64\td21, d21, d31\n-\tvcvt.f32.f64\ts11, d26\n+\tvcvt.f64.f32\td2, s4\n+\tvsub.f64\td8, d5, d0\n+\tvcvt.f64.f32\td3, s6\n+\tvadd.f64\td5, d5, d0\n+\tvsub.f64\td0, d4, d1\n+\tvadd.f64\td4, d4, d1\n+\tvadd.f64\td1, d7, d6\n+\tvadd.f64\td9, d2, d3\n+\tvsub.f64\td10, d8, d3\n+\tvsub.f64\td8, d8, d2\n+\tvsub.f64\td11, d0, d7\n+\tvadd.f64\td12, d1, d4\n+\tvsub.f64\td4, d4, d1\n+\tvsub.f64\td0, d0, d6\n+\tvsub.f64\td1, d5, d9\n+\tvadd.f64\td5, d5, d9\n+\tvadd.f64\td2, d10, d2\n+\tvadd.f64\td3, d8, d3\n+\tvcvt.f32.f64\ts24, d12\n+\tvadd.f64\td6, d11, d6\n+\tvadd.f64\td7, d0, d7\n \tvcvt.f32.f64\ts8, d4\n-\tvcvt.f32.f64\ts15, d19\n-\tvcvt.f32.f64\ts10, d25\n-\tvcvt.f32.f64\ts14, d17\n-\tvcvt.f32.f64\ts12, d24\n-\tvcvt.f32.f64\ts13, d23\n-\tvcvt.f32.f64\ts9, d21\n-\tvstr\ts8, [r2, #-4]\n-\tvstr\ts10, [r7, #-4]\n-\tadd\tr7, r8\n-\tldr\tr2, [sp, #32]\n-\tvstr\ts14, [r3, #-4]\n-\tldr\tr3, [sp, #12]\n-\tvstr\ts9, [sl, #-4]\n-\tadd\tsl, r8\n-\tvstr\ts12, [r2, #-4]\n-\tadd\tr2, r8\n-\tvstr\ts11, [r6, #-4]\n-\tvstr\ts13, [r3, #-4]\n-\tldr\tr3, [sp, #8]\n-\tstr\tr2, [sp, #32]\n-\tadd\tr3, r8\n-\tstr\tr3, [sp, #8]\n-\tldr\tr3, [sp, #12]\n-\tvstr\ts15, [r4, #-4]\n-\tadd\tr4, r8\n-\tadd\tr3, r8\n-\tstr\tr3, [sp, #12]\n-\tldr\tr3, [sp, #20]\n-\tadd\tr3, r8\n-\tstr\tr3, [sp, #20]\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts24, [r2, #-4]\n+\tvcvt.f32.f64\ts12, d6\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts2, [r7, #-4]\n+\tadd\tr7, r9\n+\tvstr\ts10, [r3, #-4]\n \tldr\tr3, [sp, #24]\n-\tadd\tr3, r8\n+\tvstr\ts4, [r2, #-4]\n+\tadd\tr2, r9\n+\tvstr\ts8, [sl, #-4]\n+\tadd\tsl, r9\n+\tvstr\ts12, [r6, #-4]\n+\tvstr\ts6, [r3, #-4]\n+\tldr\tr3, [sp, #16]\n+\tvstr\ts14, [r4, #-4]\n+\tadd\tr4, r9\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #24]\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tadd\tr3, r9\n \tstr\tr3, [sp, #24]\n-\tadd.w\tr3, r6, r8\n-\tldr\tr6, [sp, #28]\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #28]\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #32]\n+\tadd\tr3, r9\n+\tstr\tr3, [sp, #32]\n+\tadd.w\tr3, r6, r9\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tcmp\tr6, r3\n-\tbne.w\t84ac <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3bdc>\n-\tldr.w\tsl, [sp, #68]\t@ 0x44\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tbne.w\t88aa <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3cf2>\n+\tldr.w\tsl, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #316]\t@ 0x13c\n \tadd\tsl, r3\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tcmp\tsl, r3\n-\tbge.n\t86a6 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3dd6>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tbge.n\t8aa2 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3eea>\n+\tldr\tr3, [sp, #296]\t@ 0x128\n \tadd\tsl, r3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #4]\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #8]\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tcmp\tr3, r2\n-\tbne.w\t83da <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3b0a>\n-\tldrd\tr3, r9, [sp, #52]\t@ 0x34\n-\tldrd\tr1, r2, [sp, #60]\t@ 0x3c\n+\tbne.w\t87da <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3c22>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr7, [sp, #96]\t@ 0x60\n+\tldr\tr2, [sp, #104]\t@ 0x68\n \tsubs\tr3, #1\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr.w\tr8, [sp, #80]\t@ 0x50\n \tadds\tr6, r3, #1\n-\tadd\tr2, r1\n-\tbne.w\t83ca <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3afa>\n-\tb.w\t6c00 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2330>\n-\tsubs\tr3, r2, #1\n-\tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #180]\t@ 0xb4\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #164]\t@ 0xa4\n-\tb.w\t491e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4e>\n-\tldr\tr3, [sp, #400]\t@ 0x190\n-\tsubs\tr3, #3\n+\tadd\tr2, r7\n+\tbne.w\t87ca <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x3c12>\n+\tb.w\t70dc <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x2524>\n+\tldr\tr3, [sp, #616]\t@ 0x268\n+\tsubs\tr3, #1\n \tasrs\tr3, r3, #1\n-\tstr\tr3, [sp, #180]\t@ 0xb4\n+\tstr\tr3, [sp, #388]\t@ 0x184\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tb.w\t491e <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x4e>\n+\tstr\tr3, [sp, #376]\t@ 0x178\n+\tb.w\t4c1c <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0+0x64>\n \tudf\t#255\t@ 0xff\n+\tnop\n \n-000086ec <__gridxc_gpfa_core_sp_MOD_gpfa_>:\n+00008adc <__gridxc_gpfa_core_sp_MOD_gpfa_>:\n __gridxc_gpfa_core_sp_MOD_gpfa_.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3008]\t@ 0xbc0\n-\tsub.w\tsp, sp, #988\t@ 0x3dc\n+\tstr.w\tr0, [ip, #2784]\t@ 0xae0\n+\tsubw\tsp, sp, #1212\t@ 0x4bc\n \tadd\tr7, sp, #24\n-\tldr.w\tr8, [pc, #344]\t@ 8860 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x174>\n-\tadd\tr8, pc\n-\tstrd\tr3, r2, [r7, #468]\t@ 0x1d4\n-\tldr\tr2, [pc, #336]\t@ (8864 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x178>)\n-\tldr\tr3, [pc, #340]\t@ (8868 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x17c>)\n+\tmov.w\tr9, #1\n+\tadd.w\tsl, r7, #804\t@ 0x324\n+\tmov\tr8, sl\n+\tstrd\tr3, r2, [r7, #668]\t@ 0x29c\n+\tldr\tr2, [pc, #344]\t@ (8c60 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x184>)\n+\tldr\tr3, [pc, #348]\t@ (8c64 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x188>)\n \tadd\tr2, pc\n-\tldr.w\tr4, [r7, #1064]\t@ 0x428\n-\tstr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tadd.w\tr4, r7, #580\t@ 0x244\n-\tldr.w\tsl, [r7, #1068]\t@ 0x42c\n-\tmov\tip, r4\n+\tldr.w\tr4, [r7, #1288]\t@ 0x508\n+\tstr.w\tr4, [r7, #664]\t@ 0x298\n+\tldr.w\tfp, [r7, #1292]\t@ 0x50c\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #956]\t@ 0x3bc\n+\tstr.w\tr3, [r7, #1180]\t@ 0x49c\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #24]\n+\tldr.w\tr5, [fp]\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr3, #1\n-\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #736]\t@ 0x2e0\n \tldr\tr3, [r1, #24]\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr3, #1\n-\tstr.w\tr3, [r7, #532]\t@ 0x214\n+\tstr.w\tr3, [r7, #744]\t@ 0x2e8\n \tldrd\tr3, r2, [r0, #28]\n-\tsubs\tr5, r2, r3\n+\tsubs\tr4, r2, r3\n \tldr\tr3, [r0, #0]\n-\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tstr.w\tr3, [r7, #740]\t@ 0x2e4\n \tldrd\tr3, r2, [r1, #28]\n-\tstr.w\tr5, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr4, [r7, #684]\t@ 0x2ac\n \tsubs\tr3, r2, r3\n \tldr\tr2, [r1, #0]\n-\tstr.w\tr2, [r7, #512]\t@ 0x200\n-\tldr.w\tr2, [r7, #1072]\t@ 0x430\n-\tstr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr2, [r7, #1076]\t@ 0x434\n-\tstr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr3, [r7, #680]\t@ 0x2a8\n \tadds\tr3, #1\n-\tstr.w\tr2, [r7, #464]\t@ 0x1d0\n-\tadds\tr2, r5, #1\n-\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tmovs\tr3, #2\n-\tstr.w\tr2, [r7, #436]\t@ 0x1b4\n-\tmovs\tr2, #1\n-\tldr.w\tr1, [sl]\n-\tsdiv\tr5, r1, r3\n-\tmls\tr0, r3, r5, r1\n-\tcmp\tr0, #0\n-\tbne.n\t8850 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x164>\n-\tmov\tr1, r5\n-\tadds\tr0, #1\n-\tsdiv\tr5, r5, r3\n-\tmls\tr6, r3, r5, r1\n-\tcmp\tr6, #0\n-\tbeq.n\t879c <__gridxc_gpfa_core_sp_MOD_gpfa_+0xb0>\n-\tadd\tr3, r2\n-\tadds\tr2, #1\n-\tcmp\tr2, #4\n-\tstr.w\tr0, [ip], #4\n-\tbne.n\t8790 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa4>\n-\tcmp\tr1, #1\n-\tbne.w\tb0e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x29f6>\n-\tldrd\tr5, r3, [r4]\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tldr\tr3, [r4, #8]\n-\tcmp\tr5, #0\n-\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tble.n\t886c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x180>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr3, [r7, #652]\t@ 0x28c\n+\tldr.w\tr2, [r7, #1296]\t@ 0x510\n+\tldr\tr3, [pc, #252]\t@ (8c68 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x18c>)\n+\tstr.w\tr2, [r7, #660]\t@ 0x294\n+\tldr.w\tr2, [r7, #1300]\t@ 0x514\n+\tadd\tr3, pc\n+\tstr.w\tr2, [r7, #648]\t@ 0x288\n+\tadds\tr2, r4, #1\n+\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmovs\tr4, #2\n+\tstr.w\tr2, [r7, #656]\t@ 0x290\n+\tmov\tr1, r4\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr6, r1\n+\tcmp\tr1, #0\n+\tbne.n\t8c4c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x170>\n+\tmov\tr0, r5\n+\tmov\tr1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, r4\n+\tadds\tr6, #1\n+\tmov\tr5, r0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.n\t8b92 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xb6>\n+\tadd\tr4, r9\n+\tadd.w\tr9, r9, #1\n+\tcmp.w\tr9, #4\n+\tstr.w\tr6, [r8], #4\n+\tbne.n\t8b84 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa8>\n+\tcmp\tr5, #1\n+\tbne.w\tb57e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2aa2>\n+\tldrd\tr4, r3, [sl]\n+\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr3, [sl, #8]\n+\tcmp\tr4, #0\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tble.n\t8c6c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x190>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tmov\tr8, sp\n \tcmp\tr3, #1\n-\tbne.w\td75e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5072>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tldr.w\tr0, [r7, #528]\t@ 0x210\n+\tbne.w\te1fe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5722>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\tdc28 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x553c>\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tvstr\td0, [r7, #560]\t@ 0x230\n+\tit\tne\n+\tldrne.w\tr0, [r7, #740]\t@ 0x2e4\n+\tbne.w\te6be <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5be2>\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tldr\tr3, [r3, #0]\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr1, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tldr.w\tr1, [r7, #660]\t@ 0x294\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n \tldr\tr1, [r1, #0]\n-\tstrd\tr5, r1, [sp, #8]\n-\tldr.w\tr6, [sl]\n-\tldr.w\tr1, [r7, #512]\t@ 0x200\n-\tldr.w\tr0, [r7, #528]\t@ 0x210\n-\tstr\tr6, [sp, #4]\n-\tldr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr\tr6, [r4, #0]\n-\tstr\tr6, [sp, #0]\n-\tbl\t48d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n-\tcmp\tr5, #31\n-\tvldr\td0, [r7, #560]\t@ 0x230\n-\tbgt.w\tdbd8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54ec>\n+\tstrd\tr4, r1, [sp, #8]\n+\tldr.w\tr5, [fp]\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tstr\tr5, [sp, #4]\n+\tldr.w\tr5, [r7, #664]\t@ 0x298\n+\tldr\tr5, [r5, #0]\n+\tstr\tr5, [sp, #0]\n+\tbl\t4bb8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n+\tcmp\tr4, #31\n+\tbgt.w\te676 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b9a>\n \tmovs\tr3, #2\n-\tlsl.w\tr5, r3, r5\n-\tadds\tr3, r5, #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tlsl.w\tr5, r3, r4\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tadd.w\tr8, r5, #1\n \tcmp\tr3, #0\n-\tble.w\taaf6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x240a>\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tmov\tr9, sp\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tb.n\t889c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b0>\n-\tadd\tr3, r2\n-\tadds\tr2, #1\n-\tmovs\tr0, #0\n-\tcmp\tr2, #4\n-\tstr.w\tr0, [ip], #4\n-\tbne.n\t8790 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa4>\n-\tb.n\t87b8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xcc>\n-\t.word\t0x00000152\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000014c\n+\tble.w\taf14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2438>\n+\tldr.w\tr3, [r7, #740]\t@ 0x2e4\n+\tstr.w\tsp, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tb.n\t8c9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c2>\n+\tadd\tr4, r9\n+\tadd.w\tr9, r9, #1\n+\tmovs\tr6, #0\n+\tcmp.w\tr9, #4\n+\tstr.w\tr6, [r8], #4\n+\tbne.n\t8b84 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa8>\n+\tb.n\t8bb8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xdc>\n+\t.word\t0x00000154\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000000f2\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \tmovs\tr5, #0\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tmov.w\tr8, #1\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n \tcmp\tr3, #0\n-\tble.w\taaf6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x240a>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tmov\tr9, sp\n+\tble.w\taf14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2438>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tstr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #1\n-\tbne.w\tda28 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x533c>\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\titt\teq\n+\tldreq.w\tr3, [r7, #740]\t@ 0x2e4\n+\tstreq.w\tr3, [r7, #752]\t@ 0x2f0\n+\tbne.w\te4c0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59e4>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\tdaa4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x53b8>\n-\tldr.w\tr6, [r7, #512]\t@ 0x200\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tbne.w\te53e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a62>\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n \tmovs\tr0, #3\n-\tldr.w\tr4, [sl]\n-\tldr.w\tr1, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tvldr\td15, [pc, #836]\t@ 8ff8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51c>\n \tadd.w\tr3, r3, r5, lsl #3\n-\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tvstr\td0, [r7, #560]\t@ 0x230\n-\tldr.w\tr8, [r3]\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr.w\tr5, [fp]\n+\tldr\tr2, [r3, #0]\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tstr.w\tr2, [r7, #788]\t@ 0x314\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n+\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tldr\tr5, [r3, #0]\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tldr\tr4, [r3, #0]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tsubs\tr2, r0, r4\n-\tmovw\tr3, #21846\t@ 0x5556\n-\tmovt\tr3, #21845\t@ 0x5555\n-\tmul.w\tr1, r4, r8\n-\tstr.w\tr1, [r7, #556]\t@ 0x22c\n-\tmul.w\tr2, r8, r2\n-\tvldr\td0, [r7, #560]\t@ 0x230\n-\tstr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tsdiv\tr2, r4, r0\n-\tstr.w\tr0, [r7, #332]\t@ 0x14c\n-\tmov\tr1, r2\n-\tstr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tsmull\tr2, r3, r3, r2\n-\tmul.w\tr2, r1, r8\n-\tsub.w\tr3, r3, r1, asr #31\n-\tstr.w\tr2, [r7, #328]\t@ 0x148\n-\tadds\tr2, r5, #1\n-\tadd.w\tr3, r3, r3, lsl #1\n-\tsub.w\tr3, r1, r3\n-\tbne.n\t892c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x240>\n-\trsb\tr3, r3, #3\n-\tcmp\tr3, #2\n-\tvldr\td16, [pc, #768]\t@ 8c30 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x544>\n-\tvldr\td17, [pc, #772]\t@ 8c38 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54c>\n-\tvmov\ts15, r5\n-\tldr.w\tr1, [r7, #536]\t@ 0x218\n-\tvcvt.f64.s32\td18, s15\n-\tvseleq.f64\td16, d16, d17\n-\tsubs\tr2, r1, #1\n-\tadd.w\tr3, r1, #126\t@ 0x7e\n+\tmov\tr6, r0\n+\tstr.w\tr0, [r7, #392]\t@ 0x188\n+\tmov\tr1, r6\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tlr, r0\n+\tmovw\tr0, #21846\t@ 0x5556\n+\tmovt\tr0, #21845\t@ 0x5555\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tvmov\ts15, r4\n+\tvldr\td6, [pc, #756]\t@ 9000 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x524>\n+\tsmull\tr0, r1, r0, lr\n+\tsubs\tr0, r6, r5\n+\tvcvt.f64.s32\td14, s15\n+\tmul.w\tr3, r5, r2\n+\tsub.w\tr1, r1, lr, asr #31\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tmul.w\tr3, r2, r0\n+\tadds\tr0, r4, #1\n+\tadd.w\tr1, r1, r1, lsl #1\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tsub.w\tr1, lr, r1\n+\tmul.w\tr3, lr, r2\n+\tit\teq\n+\trsbeq\tr1, r1, #3\n+\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tcmp\tr1, #2\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tadd.w\tr1, r3, #126\t@ 0x7e\n+\tit\teq\n+\tvmoveq.f64\td15, d6\n+\tsubs\tr0, r3, #1\n \tit\tpl\n-\tmovpl\tr3, r2\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tadds\tr1, #126\t@ 0x7e\n-\tmov.w\tr3, r3, asr #7\n-\tadd.w\tr2, r2, #1\n-\tmov.w\tr2, r2, asr #1\n-\tblt.w\ta9e8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22fc>\n-\tldr.w\tr1, [r7, #556]\t@ 0x22c\n-\tadds\tr2, #1\n+\tmovpl\tr1, r0\n+\tldr.w\tr0, [r7, #708]\t@ 0x2c4\n+\tadds\tr3, #126\t@ 0x7e\n+\tadd.w\tr0, r0, #1\n+\tmov.w\tr1, r1, asr #7\n+\tmov.w\tr0, r0, asr #1\n+\tblt.w\tae76 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x239a>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tmovs\tr4, #1\n+\tstr.w\tr8, [r7, #288]\t@ 0x120\n+\tmov\tr8, r4\n+\tsubs\tr3, r3, r2\n+\tadds\tr2, r0, #1\n+\tstr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tstr.w\tr2, [r7, #376]\t@ 0x178\n+\tadds\tr2, r1, #2\n+\tstr.w\tr2, [r7, #308]\t@ 0x134\n+\tlsrs\tr2, r3, #31\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r7, #328]\t@ 0x148\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n \tstr.w\tr2, [r7, #320]\t@ 0x140\n-\tvneg.f64\td17, d16\n-\tsub.w\tr0, r1, r8\n-\tadds\tr1, r3, #2\n-\tmovs\tr3, #1\n-\tstr.w\tr6, [r7, #524]\t@ 0x20c\n-\tlsrs\tr2, r0, #31\n-\tstr.w\tr2, [r7, #292]\t@ 0x124\n-\tnegs\tr2, r0\n-\tstr.w\tr2, [r7, #296]\t@ 0x128\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tmov\tr6, r3\n-\tmov\tfp, r3\n-\tstr.w\tr0, [r7, #324]\t@ 0x144\n-\tstrd\tr1, r9, [r7, #268]\t@ 0x10c\n-\tlsls\tr2, r2, #2\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n-\tldr.w\tr2, [r7, #536]\t@ 0x218\n-\tstr.w\tsl, [r7, #264]\t@ 0x108\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tlsls\tr3, r3, #2\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr4, [r7, #788]\t@ 0x314\n+\tsubs\tr3, #4\n+\tstr.w\tlr, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #640]\t@ 0x280\n+\tstr.w\tfp, [r7, #284]\t@ 0x11c\n \tcmp\tr2, #128\t@ 0x80\n \tit\tle\n \tmovle\tr5, #0\n-\tble.n\t89c6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2da>\n+\tble.n\t8de0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x304>\n \tcmp\tr2, #255\t@ 0xff\n-\tbgt.w\taa24 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2338>\n-\tasrs\tr3, r2, #1\n-\tadds\tr3, #1\n-\tbic.w\tr3, r3, #1\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tsubs\tr5, r2, r3\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\titete\tle\n+\tasrle\tr3, r2, #1\n+\tmovgt\tr3, r2\n+\taddle\tr3, #1\n+\tsubgt.w\tr5, r3, #128\t@ 0x80\n+\titet\tle\n+\tbicle.w\tr3, r3, #1\n+\tmovgt\tr3, #128\t@ 0x80\n+\tsuble\tr5, r2, r3\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n \tmovs\tr3, #1\n-\tldr.w\tsl, [r7, #552]\t@ 0x228\n+\tstr.w\tr8, [r7, #584]\t@ 0x248\n+\tstr.w\tr5, [r7, #576]\t@ 0x240\n \tadd\tr2, r3\n-\tstr.w\tr3, [r7, #408]\t@ 0x198\n-\tstr.w\tr3, [r7, #412]\t@ 0x19c\n-\tldrd\tr8, r0, [r7, #324]\t@ 0x144\n-\tstr.w\tr2, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tstr.w\tr6, [r7, #420]\t@ 0x1a4\n-\tstr.w\tr5, [r7, #404]\t@ 0x194\n-\tldr.w\tr2, [r7, #408]\t@ 0x198\n-\tmov\tr4, r2\n-\tadd.w\tr2, r2, r2, lsl #1\n-\tstr.w\tr2, [r7, #408]\t@ 0x198\n-\tsdiv\tr2, r3, r2\n-\tsubs\tr1, r2, r3\n-\tadds.w\tr9, r2, r2, lsl #1\n-\tstr.w\tr1, [r7, #560]\t@ 0x230\n-\tbmi.w\tb1f2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b06>\n-\tudiv\tr6, r8, r9\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tcmp\tr1, #0\n-\tbne.w\t8b96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4aa>\n-\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n-\tcmp\tr1, #0\n-\tble.w\t8b96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4aa>\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tcmp\tr1, #1\n-\tbne.w\t8e2e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x742>\n-\tmov\tr1, fp\n-\tmov\tip, r6\n-\tmov\tlr, r9\n-\tsub.w\tr5, sl, #4\n-\tvmov.f64\td24, #96\t@ 0x3f000000 0.5\n-\tstr.w\tr5, [r7, #516]\t@ 0x204\n-\tstr.w\tr0, [r7, #492]\t@ 0x1ec\n-\tstr.w\tr8, [r7, #444]\t@ 0x1bc\n-\tstr.w\tr4, [r7, #440]\t@ 0x1b8\n-\tmov\tr6, r1\n-\tstrd\tr1, lr, [r7, #396]\t@ 0x18c\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n-\tmov.w\tr9, #1\n-\tstrd\tr2, ip, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr4, [r7, #536]\t@ 0x218\n-\tadds\tr0, r2, r6\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tcmp\tfp, r0\n+\tldr.w\tr4, [r7, #768]\t@ 0x300\n+\tldr.w\tr8, [r7, #384]\t@ 0x180\n+\tldr.w\tr5, [r7, #788]\t@ 0x314\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tmov\tr0, r4\n+\tmov\tsl, r3\n+\tadd.w\tr3, r3, r3, lsl #1\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tmov\tr1, r3\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r4\n+\tmov\tr6, r0\n+\tadds.w\tr9, r0, r0, lsl #1\n+\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tbmi.w\taec8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ec>\n+\tldr.w\tr0, [r7, #756]\t@ 0x2f4\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #320]\t@ 0x140\n+\tmov\tip, r0\n+\tcmp\tr3, #0\n+\tbne.w\t8fbe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4e2>\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tcmp\tr3, #0\n+\tble.w\t8fbe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4e2>\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tcmp\tr3, #1\n+\tbne.w\t9254 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x778>\n+\tmov\tr3, r5\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tstr.w\tr8, [r7, #704]\t@ 0x2c0\n+\tmov\tlr, r3\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tr8, [r7, #752]\t@ 0x2f0\n+\tmov.w\tfp, #1\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tstr.w\tip, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr6, [r7, #632]\t@ 0x278\n+\tstr.w\tr9, [r7, #624]\t@ 0x270\n+\tstr.w\tsl, [r7, #608]\t@ 0x260\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n+\tadd.w\tr1, r2, lr\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tcmp\tr5, r1\n \tit\tgt\n-\taddgt\tr0, r0, r3\n-\tadd\tr2, r0\n-\tcmp\tfp, r2\n+\taddgt\tr1, r1, r4\n+\tadd\tr2, r1\n+\tcmp\tr5, r2\n \tit\tgt\n-\taddgt\tr2, r2, r3\n-\tcmp\tr4, #0\n-\tble.n\t8b58 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x46c>\n-\tadd.w\tr5, r0, #1073741824\t@ 0x40000000\n-\tadd\tr0, r4\n-\tldr.w\tr4, [r7, #516]\t@ 0x204\n+\taddgt\tr2, r2, r4\n+\tcmp\tr0, #0\n+\tble.n\t8f7e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4a2>\n+\tadd.w\tr6, r1, #1073741824\t@ 0x40000000\n+\tadd\tr1, r0\n+\tldr.w\tr0, [r7, #640]\t@ 0x280\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n \tsubs\tr2, #1\n-\tsubs\tr5, #1\n-\tadd.w\tr0, r4, r0, lsl #2\n-\tadd.w\tr4, r6, #1073741824\t@ 0x40000000\n-\tsubs\tr4, #1\n+\tsubs\tr6, #1\n+\tadd.w\tr1, r0, r1, lsl #2\n+\tadd.w\tr0, lr, #1073741824\t@ 0x40000000\n+\tsubs\tr0, #1\n \tlsls\tr2, r2, #2\n-\tlsls\tr5, r5, #2\n-\tadd.w\tr8, sl, r2\n-\tlsls\tr4, r4, #2\n-\tadd.w\tip, sl, r5\n-\tadd.w\tlr, sl, r4\n-\tadd\tr5, r1\n-\tadd\tr2, r1\n-\tadd\tr4, r1\n-\tvldr\ts10, [ip]\n-\tvldr\ts11, [r8]\n-\tvldr\ts13, [r5]\n-\tvldr\ts12, [r2]\n-\tvcvt.f64.f32\td25, s10\n-\tvldr\ts14, [lr]\n-\tvcvt.f64.f32\td23, s11\n-\tvldr\ts15, [r4]\n-\tvcvt.f64.f32\td21, s13\n+\tlsls\tr6, r6, #2\n+\tadd.w\tsl, r8, r2\n+\tlsls\tr0, r0, #2\n+\tadd.w\tip, r8, r6\n+\tadd.w\tr9, r8, r0\n+\tadd\tr6, r3\n+\tadd\tr2, r3\n+\tadd\tr0, r3\n+\tvldr\ts8, [ip]\n+\tvldr\ts2, [sl]\n+\tvldr\ts14, [r6]\n+\tvldr\ts4, [r2]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts10, [r9]\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts12, [r0]\n+\tvcvt.f64.f32\td7, s14\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td5, s10\n \tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td20, s14\n-\tvadd.f64\td27, d23, d25\n-\tvcvt.f64.f32\td19, s15\n-\tvsub.f64\td25, d25, d23\n-\tvadd.f64\td26, d6, d21\n-\tvsub.f64\td21, d21, d6\n-\tvmov.f64\td23, d20\n-\tvfms.f64\td23, d27, d24\n-\tvmov.f64\td22, d19\n-\tvadd.f64\td20, d20, d27\n-\tvfms.f64\td22, d26, d24\n-\tvadd.f64\td19, d19, d26\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts15, d19\n-\tvmov.f64\td6, d23\n-\tvfma.f64\td23, d16, d21\n-\tvfma.f64\td6, d17, d21\n-\tvstmia\tlr!, {s14}\n-\tvmov.f64\td21, d22\n-\tvfma.f64\td22, d17, d25\n-\tvfma.f64\td21, d16, d25\n-\tvstmia\tr4!, {s15}\n-\tvcvt.f32.f64\ts14, d23\n+\tvadd.f64\td8, d1, d4\n+\tvsub.f64\td4, d4, d1\n+\tvadd.f64\td0, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvmov.f64\td1, d5\n+\tvmov.f64\td2, d6\n+\tvmls.f64\td1, d8, d3\n+\tvmul.f64\td4, d4, d15\n+\tvadd.f64\td5, d5, d8\n+\tvmls.f64\td2, d0, d3\n+\tvadd.f64\td6, d6, d0\n+\tvmul.f64\td7, d7, d15\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts11, d6\n+\tvsub.f64\td0, d1, d7\n+\tvadd.f64\td7, d7, d1\n+\tvstmia\tr9!, {s10}\n+\tvadd.f64\td1, d2, d4\n+\tvsub.f64\td6, d2, d4\n+\tvstmia\tr0!, {s11}\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts2, d1\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts15, d22\n-\tvcvt.f32.f64\ts13, d21\n-\tvstmia\tip!, {s12}\n-\tcmp\tip, r0\n-\tvstmia\tr8!, {s14}\n-\tvstmia\tr5!, {s13}\n-\tvstmia\tr2!, {s15}\n-\tbne.n\t8ab4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3c8>\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tadd.w\tr9, r9, #1\n-\tadd\tr6, r2\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tcmp\tfp, r6\n+\tvstmia\tip!, {s0}\n+\tcmp\tip, r1\n+\tvstmia\tsl!, {s14}\n+\tvstmia\tr6!, {s2}\n+\tvstmia\tr2!, {s12}\n+\tbne.n\t8eda <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3fe>\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tadd.w\tfp, fp, #1\n+\tadd\tlr, r2\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tcmp\tr5, lr\n \tit\tgt\n-\taddgt\tr6, r6, r3\n-\tcmp\tr9, r2\n-\tbne.w\t8a60 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x374>\n-\tldrd\tr2, ip, [r7, #424]\t@ 0x1a8\n-\tldrd\tr1, lr, [r7, #396]\t@ 0x18c\n+\taddgt\tlr, r4\n+\tcmp\tfp, r2\n+\tbne.w\t8e84 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3a8>\n+\tldr.w\tip, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr9, [r7, #624]\t@ 0x270\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n+\tldr.w\tr6, [r7, #632]\t@ 0x278\n \tcmp.w\tip, #4294967295\t@ 0xffffffff\n-\tadd\tr1, lr\n-\tbne.w\t8a4e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x362>\n-\tldr.w\tr0, [r7, #492]\t@ 0x1ec\n-\tmov\tr9, lr\n-\tldr.w\tr8, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr4, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr1, [r7, #332]\t@ 0x14c\n-\tcmp\tr1, #3\n-\tbeq.w\t8fb2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8c6>\n-\tlsls\tr1, r4, #1\n-\tcmp\tr0, #0\n-\tsub.w\tr4, r2, r0\n-\tblt.w\tb1e0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2af4>\n-\tsubs\tr2, r4, r0\n-\tcmp\tr0, r4\n-\tudiv\tr2, r2, r0\n-\tbgt.w\t8fda <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8ee>\n-\tldr.w\tr4, [r7, #476]\t@ 0x1dc\n-\tcmp\tr4, #1\n-\tbne.w\t955a <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe6e>\n-\tldr.w\tr5, [r7, #416]\t@ 0x1a0\n-\tlsls\tr4, r1, #3\n-\tlsls\tr1, r1, #4\n-\tstr.w\tr4, [r7, #400]\t@ 0x190\n-\tstr.w\tr1, [r7, #396]\t@ 0x18c\n-\tmov\tr1, r4\n-\tadds\tr4, r5, r4\n-\tmov\tip, r0\n-\tadd.w\tlr, r4, r1\n-\tsub.w\tr5, r8, r0\n-\tmov\tr1, r0\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tmov\tr6, lr\n-\tsub.w\tr5, sl, #4\n-\tmov\tr0, r8\n-\tstr.w\tr5, [r7, #392]\t@ 0x188\n-\tmov\tr5, lr\n-\tstr.w\tsl, [r7, #492]\t@ 0x1ec\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tvldr\td25, [r4, #8]\n-\tcmp.w\tr9, #0\n-\tvldr\td24, [r6, #8]\n-\tvldr\td27, [r4]\n-\tvmul.f64\td25, d18, d25\n-\tvldr\td26, [r6]\n-\tvmul.f64\td24, d18, d24\n-\tblt.w\t8fbc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8d0>\n-\tldr.w\tr4, [r7, #444]\t@ 0x1bc\n-\tcmp\tr0, r1\n-\tudiv\tlr, r4, r9\n-\tblt.w\t8e08 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x71c>\n-\tb.n\t8c40 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x554>\n+\tldr.w\tsl, [r7, #608]\t@ 0x260\n+\tadd\tr3, r9\n+\tbne.w\t8e62 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x386>\n+\tldr.w\tr8, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tcmp\tr3, #3\n+\tbeq.w\t93e4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x908>\n+\tmov.w\tr3, sl, lsl #1\n+\tsub.w\tr6, r6, r8\n+\tcmp.w\tr8, #0\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tblt.w\taeac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23d0>\n+\tmov\tr1, r8\n+\tsub.w\tr0, r6, r8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tmov\tsl, r0\n+\tcmp\tr8, r6\n+\tbgt.w\t9412 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x936>\n+\tb.n\t9008 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x52c>\n \tnop.w\n \t.word\t0xe8584c9c\n-\t.word\t0xbfebb67a\n-\t.word\t0xe8584c9c\n \t.word\t0x3febb67a\n-\tldr.w\tr4, [r7, #488]\t@ 0x1e8\n-\tcmp\tr4, #0\n-\tble.w\t8e08 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x71c>\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tadd.w\tsl, fp, r1\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tstrd\tr0, ip, [r7, #384]\t@ 0x180\n-\tstrd\tr1, r2, [r7, #376]\t@ 0x178\n-\tmov\tr0, sl\n-\tmov.w\tip, #1\n-\tstr.w\tr9, [r7, #440]\t@ 0x1b8\n-\tstr.w\tlr, [r7, #428]\t@ 0x1ac\n-\tstr.w\tr5, [r7, #516]\t@ 0x204\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr4, [r7, #536]\t@ 0x218\n-\tadds\tr1, r2, r0\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tcmp\tfp, r1\n+\t.word\t0xe8584c9c\n+\t.word\t0xbfebb67a\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tcmp\tr2, #1\n+\tbne.w\t9998 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xebc>\n+\tlsls\tr1, r3, #3\n+\tlsls\tr3, r3, #4\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tmov\tr6, r8\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n+\tstr.w\tr8, [r7, #568]\t@ 0x238\n+\tadds\tr0, r3, r1\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tadds\tr2, r0, r1\n+\tstr.w\tr1, [r7, #552]\t@ 0x228\n+\tsub.w\tr3, r3, r8\n+\tmov\tr8, sl\n+\tmov\tsl, r2\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tvldr\td9, [r0, #8]\n+\tcmp.w\tr9, #0\n+\tvldr\td11, [sl, #8]\n+\tvldr\td8, [r0]\n+\tvmul.f64\td9, d14, d9\n+\tvldr\td10, [sl]\n+\tvmul.f64\td11, d14, d11\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tblt.w\t93ee <__gridxc_gpfa_core_sp_MOD_gpfa_+0x912>\n+\tldr.w\tr0, [r7, #704]\t@ 0x2c0\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tmov\tlr, r0\n+\tcmp\tr3, r6\n+\tblt.w\t9226 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x74a>\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tcmp\tr3, #0\n+\tble.w\t9226 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x74a>\n+\tadd.w\tfp, r5, r6\n+\tstr.w\tr8, [r7, #548]\t@ 0x224\n+\tstr.w\tr6, [r7, #536]\t@ 0x218\n+\tmov\tr1, fp\n+\tmov.w\tr8, #1\n+\tstr.w\tr9, [r7, #688]\t@ 0x2b0\n+\tstr.w\tlr, [r7, #632]\t@ 0x278\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr6, [r7, #784]\t@ 0x310\n+\tadds\tr0, r3, r1\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tcmp\tr5, r0\n \tit\tgt\n-\taddgt\tr1, r1, r3\n-\tadd\tr2, r1\n-\tcmp\tfp, r2\n+\taddgt\tr0, r0, r4\n+\tadd\tr3, r0\n+\tcmp\tr5, r3\n \tit\tgt\n-\taddgt\tr2, r2, r3\n-\tcmp\tr4, #0\n-\tble.w\t8dc8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x6dc>\n-\tmov\tr5, r4\n-\tadd.w\tr4, r1, #1073741824\t@ 0x40000000\n-\tadd\tr1, r5\n-\tldr.w\tr5, [r7, #392]\t@ 0x188\n-\tsubs\tr4, #1\n-\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n-\tsubs\tr2, #1\n-\tstr.w\tr3, [r7, #368]\t@ 0x170\n-\tadd.w\tr1, r5, r1, lsl #2\n-\tldr.w\tr5, [r7, #492]\t@ 0x1ec\n-\tlsls\tr4, r4, #2\n-\tlsls\tr2, r2, #2\n-\tadd.w\tlr, r5, r4\n-\tldr.w\tr5, [r7, #524]\t@ 0x20c\n-\tstr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tadd.w\tr1, r0, #1073741824\t@ 0x40000000\n-\tadd\tr4, r5\n-\tldr.w\tr5, [r7, #492]\t@ 0x1ec\n-\tsubs\tr1, #1\n-\tadd.w\tr9, r5, r2\n-\tldr.w\tr5, [r7, #524]\t@ 0x20c\n-\tlsls\tr1, r1, #2\n-\tadd\tr2, r5\n-\tldr.w\tr5, [r7, #492]\t@ 0x1ec\n-\tadd.w\tr8, r5, r1\n-\tldr.w\tr5, [r7, #524]\t@ 0x20c\n-\tadd\tr1, r5\n-\tldr.w\tr5, [r7, #516]\t@ 0x204\n-\tvldr\ts11, [r2]\n-\tvldr\ts12, [r4]\n-\tvldr\ts14, [lr]\n-\tvldr\ts15, [r9]\n-\tvcvt.f64.f32\td31, s11\n+\taddgt\tr3, r3, r4\n+\tcmp\tr6, #0\n+\tble.w\t91ea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x70e>\n+\tmov\tr2, r6\n+\tadd.w\tr6, r0, #1073741824\t@ 0x40000000\n+\tadd\tr0, r2\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tsubs\tr6, #1\n+\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tsubs\tr3, #1\n+\tadd.w\tr2, r2, r0, lsl #2\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tlsls\tr6, r6, #2\n+\tlsls\tr3, r3, #2\n+\tadd.w\tr0, r1, #1073741824\t@ 0x40000000\n+\tadd.w\tip, r2, r6\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n+\tsubs\tr0, #1\n+\tadd\tr6, r2\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tlsls\tr0, r0, #2\n+\tadd.w\tr9, r2, r3\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tadd.w\tlr, r2, r0\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n+\tadd\tr0, r2\n+\tvldr\ts4, [r6]\n+\tvldr\ts12, [r3]\n+\tvldr\ts14, [ip]\n+\tvldr\ts6, [r9]\n+\tvcvt.f64.f32\td2, s4\n \tvcvt.f64.f32\td6, s12\n-\tvldr\ts10, [r1]\n-\tvldr\ts9, [r8]\n-\tvcvt.f64.f32\td20, s14\n-\tvcvt.f64.f32\td19, s15\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tvldr\ts8, [lr]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts10, [r0]\n+\tvcvt.f64.f32\td3, s6\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tvcvt.f64.f32\td4, s8\n+\tvadd.f64\td1, d6, d2\n+\tvsub.f64\td2, d2, d6\n \tvcvt.f64.f32\td5, s10\n-\tvadd.f64\td28, d31, d6\n-\tvcvt.f64.f32\td30, s9\n-\tvsub.f64\td31, d6, d31\n-\tvadd.f64\td7, d19, d20\n-\tvsub.f64\td20, d20, d19\n-\tvmov.f64\td21, d5\n-\tvmov.f64\td22, d5\n-\tvfms.f64\td21, d28, d23\n-\tvmov.f64\td29, d30\n-\tvfnms.f64\td22, d28, d23\n-\tvadd.f64\td28, d5, d28\n-\tvfms.f64\td29, d7, d23\n-\tvadd.f64\td7, d30, d7\n-\tvfma.f64\td22, d16, d20\n-\tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d28\n-\tvmov.f64\td19, d21\n-\tvfma.f64\td21, d17, d20\n-\tvfma.f64\td19, d16, d20\n-\tvmov.f64\td30, d29\n-\tvfma.f64\td29, d16, d31\n-\tvfma.f64\td30, d17, d31\n-\tvstmia\tr8!, {s14}\n-\tvstmia\tr1!, {s15}\n-\tvmul.f64\td22, d22, d24\n-\tvmul.f64\td20, d21, d26\n-\tvnmul.f64\td28, d25, d19\n-\tvmul.f64\td19, d19, d27\n-\tvfma.f64\td22, d29, d26\n-\tvfma.f64\td20, d29, d24\n-\tvfma.f64\td28, d30, d27\n-\tvfma.f64\td19, d30, d25\n-\tvcvt.f32.f64\ts13, d22\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts12, d28\n-\tvcvt.f32.f64\ts15, d19\n+\tvadd.f64\td6, d3, d7\n+\tvsub.f64\td7, d7, d3\n+\tvmov.f64\td0, d4\n+\tvmul.f64\td3, d1, d12\n+\tvmul.f64\td2, d2, d15\n+\tvadd.f64\td1, d5, d1\n+\tvmls.f64\td0, d6, d12\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td6, d4, d6\n+\tvsub.f64\td4, d5, d3\n+\tvsub.f64\td3, d3, d5\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts13, d1\n+\tvadd.f64\td5, d4, d7\n+\tvadd.f64\td13, d3, d7\n+\tvsub.f64\td1, d4, d7\n+\tvsub.f64\td3, d0, d2\n+\tvadd.f64\td2, d2, d0\n \tvstmia\tlr!, {s12}\n-\tcmp\tlr, r3\n-\tvstmia\tr4!, {s15}\n-\tvstmia\tr9!, {s13}\n-\tvstmia\tr2!, {s14}\n-\tbne.n\t8cec <__gridxc_gpfa_core_sp_MOD_gpfa_+0x600>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tstr.w\tr5, [r7, #516]\t@ 0x204\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tadd.w\tip, ip, #1\n-\tadd\tr0, r2\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tcmp\tfp, r0\n-\tit\tgt\n-\taddgt\tr0, r0, r3\n+\tvmul.f64\td4, d5, d9\n+\tvstmia\tr0!, {s13}\n+\tvmul.f64\td7, d2, d10\n+\tvmul.f64\td6, d3, d9\n+\tvmul.f64\td2, d2, d11\n+\tvmla.f64\td6, d5, d8\n+\tvnmls.f64\td4, d3, d8\n+\tvmla.f64\td7, d13, d11\n+\tvmla.f64\td2, d1, d10\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts10, d4\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts8, d2\n+\tvstmia\tr6!, {s12}\n+\tvstmia\tip!, {s10}\n \tcmp\tip, r2\n-\tbne.w\t8c70 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x584>\n-\tldr.w\tlr, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr9, [r7, #440]\t@ 0x1b8\n+\tvstmia\tr3!, {s8}\n+\tvstmia\tr9!, {s14}\n+\tbne.n\t911a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x63e>\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tadd.w\tr8, r8, #1\n+\tadd\tr1, r3\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tcmp\tr5, r1\n+\tit\tgt\n+\taddgt\tr1, r1, r4\n+\tcmp\tr8, r3\n+\tbne.w\t90a6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5ca>\n+\tldr.w\tlr, [r7, #632]\t@ 0x278\n+\tldr.w\tr9, [r7, #688]\t@ 0x2b0\n \tadd.w\tlr, lr, #4294967295\t@ 0xffffffff\n-\tldr.w\tr5, [r7, #516]\t@ 0x204\n-\tadd\tsl, r9\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tadd\tfp, r9\n \tcmp.w\tlr, #4294967295\t@ 0xffffffff\n-\tbne.w\t8c5e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x572>\n-\tldrd\tr0, ip, [r7, #384]\t@ 0x180\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldrd\tr1, r2, [r7, #376]\t@ 0x178\n-\tsubs\tr2, #1\n-\tldr.w\tr4, [r7, #396]\t@ 0x18c\n-\tadd\tr1, ip\n-\tadds\tr3, r2, #1\n-\tadd\tr6, r4\n-\tldr.w\tr4, [r7, #444]\t@ 0x1bc\n-\tsub.w\tr4, r4, ip\n-\tstr.w\tr4, [r7, #444]\t@ 0x1bc\n-\tmov\tr4, r5\n-\tbeq.w\t8fce <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8e2>\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tadd\tr5, r3\n-\tb.n\t8bfc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x510>\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n-\tmov\tr1, fp\n-\tmov\tip, r9\n-\tvmov.f64\td25, #96\t@ 0x3f000000 0.5\n-\tadds\tr5, #1\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tmovs\tr5, #1\n-\tstrd\tr2, r0, [r7, #424]\t@ 0x1a8\n-\tstr.w\tr5, [r7, #516]\t@ 0x204\n-\tmov\tlr, r1\n-\tldr.w\tr2, [r7, #372]\t@ 0x174\n-\tmov\tr5, r1\n-\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tstrd\tip, r8, [r7, #396]\t@ 0x18c\n-\tstr.w\tr1, [r7, #392]\t@ 0x188\n-\tstr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tbne.w\t9094 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b8>\n+\tldr.w\tr8, [r7, #548]\t@ 0x224\n+\tldr.w\tr6, [r7, #536]\t@ 0x218\n \tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tadd\tr2, r5\n-\tcmp\tfp, r2\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tmov\tr0, r2\n+\tadd\tsl, r1\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tadd\tr6, r3\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tsub.w\tr3, r1, r3\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tbeq.w\t940e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x932>\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tadd\tr2, r3\n+\tb.n\t9040 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x564>\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tmov\tr3, r5\n+\tldr.w\tfp, [r7, #520]\t@ 0x208\n+\tmov\tr0, sl\n+\tadds\tr2, #1\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr6, [r7, #632]\t@ 0x278\n+\tmov\tr6, r3\n+\tmovs\tr2, #1\n+\tstr.w\tip, [r7, #624]\t@ 0x270\n+\tstr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr8, [r7, #608]\t@ 0x260\n+\tstr.w\tr9, [r7, #568]\t@ 0x238\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadds\tr2, r3, r6\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tcmp\tr5, r2\n \tit\tgt\n-\taddgt\tr2, r2, r3\n-\tadds\tr0, r1, r2\n-\tldr.w\tr1, [r7, #536]\t@ 0x218\n-\tcmp\tfp, r0\n+\taddgt\tr2, r2, r4\n+\tadds\tr1, r3, r2\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tcmp\tr5, r1\n \tit\tgt\n-\taddgt\tr0, r0, r3\n-\tcmp\tr1, #0\n-\tble.n\t8f6a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x87e>\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\taddgt\tr1, r1, r4\n+\tcmp\tr3, #0\n+\tble.n\t9394 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8b8>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n \tlsls\tr2, r2, #2\n-\tlsls\tr0, r0, #2\n-\tlsls\tr6, r5, #2\n-\tadd.w\tr8, sl, r2\n-\tadd.w\tlr, sl, r0\n-\tadd\tr2, r1\n-\tadd\tr0, r1\n-\tadd.w\tip, sl, r6\n-\tadd\tr6, r1\n-\tldr.w\tr1, [r7, #492]\t@ 0x1ec\n-\tmov.w\tr9, #1\n-\tstr.w\tr3, [r7, #388]\t@ 0x184\n-\tvldr\ts10, [r8, #-4]\n-\tadd.w\tr9, r9, #1\n-\tvldr\ts11, [lr, #-4]\n-\tvldr\ts15, [r2, #-4]\n-\tvldr\ts12, [r0, #-4]\n-\tvcvt.f64.f32\td26, s10\n-\tvldr\ts9, [ip, #-4]\n-\tvcvt.f64.f32\td22, s11\n-\tvldr\ts14, [r6, #-4]\n-\tvcvt.f64.f32\td19, s15\n-\tvcvt.f64.f32\td6, s12\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvcvt.f64.f32\td23, s9\n-\tvadd.f64\td20, d26, d22\n+\tlsls\tr1, r1, #2\n+\tmov.w\tip, r6, lsl #2\n+\tadd.w\tr9, r3, r2\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tmov.w\tsl, #1\n+\tadd\tr2, r3\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tadd.w\tr8, r3, r1\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tadd\tr1, r3\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tadd.w\tlr, r3, ip\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tadd\tip, r3\n+\tvldr\ts14, [r9, #-4]\n+\tadd.w\tsl, sl, #1\n+\tvldr\ts8, [r8, #-4]\n+\tvldr\ts12, [r2, #-4]\n+\tvldr\ts10, [r1, #-4]\n \tvcvt.f64.f32\td7, s14\n-\tvsub.f64\td26, d26, d22\n-\tcmp\tr9, r3\n-\tvadd.f64\td22, d19, d6\n-\tvsub.f64\td19, d19, d6\n-\tvmov.f64\td21, d23\n-\tvfms.f64\td21, d20, d25\n-\tvadd.f64\td23, d20, d23\n-\tvmov.f64\td20, d7\n-\tvfms.f64\td20, d22, d25\n-\tvadd.f64\td22, d22, d7\n-\tvcvt.f32.f64\ts14, d23\n-\tvcvt.f32.f64\ts15, d22\n-\tvmov.f64\td6, d21\n-\tvfma.f64\td21, d16, d19\n-\tvfma.f64\td6, d19, d17\n-\tvstr\ts14, [ip, #-4]\n-\tvmov.f64\td19, d20\n-\tvfms.f64\td20, d26, d16\n-\tvfma.f64\td19, d26, d16\n-\tvstr\ts15, [r6, #-4]\n-\tadd\tip, r1\n-\tadd\tr6, r1\n-\tvcvt.f32.f64\ts14, d21\n+\tvldr\ts16, [lr, #-4]\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts0, [ip, #-4]\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tvcvt.f64.f32\td8, s16\n+\tvcvt.f64.f32\td0, s0\n+\tvadd.f64\td1, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tcmp\tsl, r3\n+\tvadd.f64\td3, d6, d5\n+\tvsub.f64\td6, d6, d5\n+\tvmov.f64\td4, d8\n+\tvmov.f64\td5, d0\n+\tvmls.f64\td4, d1, d2\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td1, d1, d8\n+\tvmls.f64\td5, d3, d2\n+\tvmul.f64\td6, d6, d15\n+\tvadd.f64\td3, d3, d0\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts6, d3\n+\tvsub.f64\td0, d4, d6\n+\tvadd.f64\td4, d4, d6\n+\tvstr\ts2, [lr, #-4]\n+\tadd\tlr, fp\n+\tvadd.f64\td6, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvstr\ts6, [ip, #-4]\n+\tadd\tip, fp\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts8, d4\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts15, d20\n-\tvcvt.f32.f64\ts13, d19\n-\tvstr\ts12, [r8, #-4]\n-\tadd\tr8, r1\n-\tvstr\ts14, [lr, #-4]\n-\tadd\tlr, r1\n-\tvstr\ts13, [r2, #-4]\n-\tadd\tr2, r1\n-\tvstr\ts15, [r0, #-4]\n-\tadd\tr0, r1\n-\tbne.n\t8eaa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x7be>\n-\tldr.w\tr3, [r7, #388]\t@ 0x184\n-\tstr.w\tr1, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n-\tadd\tr5, r2\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tcmp\tfp, r5\n-\tadd.w\tr2, r2, #1\n+\tvcvt.f32.f64\ts10, d5\n+\tvstr\ts0, [r9, #-4]\n+\tadd\tr9, fp\n+\tvstr\ts8, [r8, #-4]\n+\tadd\tr8, fp\n+\tvstr\ts12, [r2, #-4]\n+\tadd\tr2, fp\n+\tvstr\ts10, [r1, #-4]\n+\tadd\tr1, fp\n+\tbne.n\t92dc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x800>\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tadd\tr6, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tcmp\tr5, r6\n+\tadd.w\tr3, r3, #1\n \tit\tgt\n-\taddgt\tr5, r5, r3\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n-\tcmp\tr2, r1\n-\tbne.w\t8e62 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x776>\n-\tldr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tldrd\tip, r8, [r7, #396]\t@ 0x18c\n-\tsubs\tr6, #1\n-\tldr.w\tr1, [r7, #392]\t@ 0x188\n-\tadds\tr5, r6, #1\n-\tldrd\tr2, r0, [r7, #424]\t@ 0x1a8\n-\tadd\tr1, ip\n-\tbne.w\t8e40 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x754>\n-\tldr.w\tr1, [r7, #332]\t@ 0x14c\n-\tmov\tr9, ip\n-\tcmp\tr1, #3\n-\tbne.w\t8ba0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4b4>\n-\tldr.w\tr6, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr5, [r7, #404]\t@ 0x194\n-\tb.n\t9538 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe4c>\n-\tsubs\tr4, r1, r0\n-\trsb\tlr, r9, #0\n-\tcmp\tr0, r1\n-\tudiv\tlr, r4, lr\n-\tble.w\t8c40 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x554>\n-\tb.n\t8e08 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x71c>\n-\tldr.w\tsl, [r7, #492]\t@ 0x1ec\n+\taddgt\tr6, r6, r4\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tcmp\tr3, r2\n+\tbne.w\t9286 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x7aa>\n+\tldr.w\tip, [r7, #624]\t@ 0x270\n+\tldr.w\tr9, [r7, #568]\t@ 0x238\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n+\tldr.w\tr8, [r7, #608]\t@ 0x260\n+\tcmp.w\tip, #4294967295\t@ 0xffffffff\n+\tadd\tr3, r9\n+\tbne.w\t926e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x792>\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tmov\tsl, r0\n+\tldr.w\tr6, [r7, #632]\t@ 0x278\n+\tcmp\tr3, #3\n+\tbne.w\t8fc8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4ec>\n+\tldr.w\tr8, [r7, #584]\t@ 0x248\n+\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tb.n\t9970 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe94>\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\trsb\tr1, r9, #0\n+\tsubs\tr0, r6, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tmov\tlr, r0\n+\tcmp\tr3, r6\n+\tble.w\t907e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a2>\n+\tb.n\t9226 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x74a>\n+\tldr.w\tr8, [r7, #568]\t@ 0x238\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tldr.w\tr2, [r7, #376]\t@ 0x178\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tcmp\tr3, r2\n+\tbne.w\t8e08 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x32c>\n+\tmov\tr3, r2\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr8, [r7, #584]\t@ 0x248\n+\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tcmp\tr2, r3\n+\tblt.w\t9970 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe94>\n+\tstr.w\tr5, [r7, #344]\t@ 0x158\n+\tldr.w\tr5, [r7, #384]\t@ 0x180\n+\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr8, [r7, #352]\t@ 0x160\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr8, [r7, #768]\t@ 0x300\n+\tmov\tr6, r3\n+\tstr.w\tr3, [r7, #368]\t@ 0x170\n+\tadd.w\tr3, r3, r3, lsl #1\n+\tmov\tr0, r8\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmul.w\tr3, r6, r5\n+\tmov\tr2, r8\n+\tmov\tr4, r0\n+\tsubs\tr1, r0, r2\n+\tsubs\tr6, r3, r5\n+\tsubs\tr2, r3, r2\n+\tadds.w\tsl, r0, r0, lsl #1\n+\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr6, [r7, #688]\t@ 0x2b0\n+\tbmi.w\tae52 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2376>\n+\tmov\tr1, sl\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, #0\n \tmov\tr8, r0\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tmov\tr0, ip\n-\tldr.w\tr2, [r7, #412]\t@ 0x19c\n-\tldr.w\tr1, [r7, #320]\t@ 0x140\n-\tadds\tr2, #1\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tcmp\tr2, r1\n-\tbne.w\t89ee <__gridxc_gpfa_core_sp_MOD_gpfa_+0x302>\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr6, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr5, [r7, #404]\t@ 0x194\n-\tcmp\tr2, r1\n-\tblt.w\t9538 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe4c>\n-\tldr.w\tr8, [r7, #328]\t@ 0x148\n-\tldr.w\tr9, [r7, #324]\t@ 0x144\n-\tstr.w\tr6, [r7, #308]\t@ 0x134\n-\tmov\tr6, r1\n-\tstr.w\tfp, [r7, #560]\t@ 0x230\n-\tstr.w\tr5, [r7, #304]\t@ 0x130\n-\tldr.w\tr3, [r7, #408]\t@ 0x198\n+\tblt.w\ta100 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1624>\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n+\tadd.w\tr9, r3, r3, lsl #1\n+\trsb\tr3, r9, #0\n+\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tcmp\tr3, #1\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tbne.w\t9c16 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x113a>\n+\tstr.w\tr3, [r7, #548]\t@ 0x224\n+\tmovs\tr3, #0\n+\tldr.w\tfp, [r7, #748]\t@ 0x2ec\n+\tmov\tr6, r4\n \tmov\tr4, r3\n-\tadd.w\tr3, r3, r3, lsl #1\n-\tstr.w\tr3, [r7, #408]\t@ 0x198\n-\tmov\tr2, r3\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tmul.w\tfp, r4, r8\n-\tsub.w\tlr, fp, r8\n-\tsdiv\tr5, r3, r2\n-\tsub.w\tr2, fp, r3\n-\tstr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tsubs\tr3, r5, r3\n-\tadds.w\tr0, r5, r5, lsl #1\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tbmi.w\ta9c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22d6>\n-\tudiv\tr1, lr, r0\n-\tcmp.w\tlr, #0\n-\tblt.w\t9cc0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15d4>\n-\tadd.w\tr3, fp, fp, lsl #1\n-\tnegs\tr2, r3\n-\tstr.w\tr2, [r7, #344]\t@ 0x158\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tcmp\tr2, #1\n-\tbne.w\t97dc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10f0>\n-\tldr.w\tr2, [r7, #552]\t@ 0x228\n-\tmov\tsl, r9\n-\tstr.w\tr9, [r7, #428]\t@ 0x1ac\n-\tmov.w\tip, #0\n-\tsubs\tr2, #4\n-\tldr.w\tr9, [r7, #552]\t@ 0x228\n-\tstrd\tr8, r2, [r7, #356]\t@ 0x164\n-\tmov\tr8, lr\n-\tmov\tlr, r6\n-\tmov\tr6, fp\n-\tldr.w\tfp, [r7, #524]\t@ 0x20c\n-\tstr.w\tsl, [r7, #384]\t@ 0x180\n-\tmov\tsl, r4\n-\tcmp\tr3, #0\n-\tblt.w\t97c0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10d4>\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n-\tldr.w\tr4, [r7, #428]\t@ 0x1ac\n-\tcmp\tr4, ip\n-\tudiv\tr2, r2, r3\n-\tblt.w\t94fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe10>\n-\tldr.w\tr4, [r7, #488]\t@ 0x1e8\n-\tcmp\tr4, #0\n-\tble.w\t94fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe10>\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tstrd\tr0, r5, [r7, #312]\t@ 0x138\n-\tadd\tr4, ip\n-\tstr.w\tr4, [r7, #388]\t@ 0x184\n-\tldr.w\tr4, [r7, #488]\t@ 0x1e8\n-\tstr.w\tr1, [r7, #300]\t@ 0x12c\n-\tadds\tr4, #1\n-\tstr.w\tr4, [r7, #352]\t@ 0x160\n-\tstr.w\tsl, [r7, #260]\t@ 0x104\n-\tmovs\tr0, #1\n-\tldr.w\tsl, [r7, #556]\t@ 0x22c\n-\tldr.w\tr1, [r7, #388]\t@ 0x184\n-\tstr.w\tr0, [r7, #380]\t@ 0x17c\n-\tstrd\tr8, r6, [r7, #284]\t@ 0x11c\n-\tstrd\tlr, r3, [r7, #276]\t@ 0x114\n-\tstr.w\tip, [r7, #256]\t@ 0x100\n-\tstr.w\tr2, [r7, #244]\t@ 0xf4\n-\tstr.w\tr1, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tldr.w\tr1, [r7, #516]\t@ 0x204\n+\tstr.w\tr5, [r7, #504]\t@ 0x1f8\n+\tstr.w\tsl, [r7, #508]\t@ 0x1fc\n+\tcmp.w\tr9, #0\n+\tblt.w\t9bfe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1122>\n+\tldr.w\tr0, [r7, #548]\t@ 0x224\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr3, r0\n+\tcmp\tr2, r4\n+\tblt.w\t9932 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe56>\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tcmp\tr1, #0\n+\tble.w\t9932 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe56>\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tmov\tip, r9\n+\tldr.w\tsl, [r7, #752]\t@ 0x2f0\n+\tadds\tr1, #1\n+\tadd\tr2, r4\n+\tstr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr9, [r7, #768]\t@ 0x300\n+\tmovs\tr1, #1\n+\tstr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tstr.w\tr8, [r7, #416]\t@ 0x1a0\n+\tstr.w\tip, [r7, #408]\t@ 0x198\n+\tstr.w\tr4, [r7, #360]\t@ 0x168\n+\tstr.w\tr3, [r7, #336]\t@ 0x150\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr2, [r7, #312]\t@ 0x138\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n \tadd.w\tlr, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n \tcmp\tr3, lr\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tlr, sl\n+\taddgt\tlr, r9\n+\tldr.w\tr0, [r7, #788]\t@ 0x314\n \tadd\tr3, lr\n \tcmp\tr2, r3\n-\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n \tit\tgt\n-\taddgt\tr3, sl\n+\taddgt\tr3, r9\n \tadd\tr2, r1\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n \tcmp\tr1, r2\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tr2, sl\n+\taddgt\tr2, r9\n \tadds\tr4, r1, r2\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n \tcmp\tr1, r4\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tr4, sl\n+\taddgt\tr4, r9\n \tadds\tr5, r1, r4\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n \tcmp\tr1, r5\n-\tldr.w\tr1, [r7, #492]\t@ 0x1ec\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n \tit\tgt\n-\taddgt\tr5, sl\n+\taddgt\tr5, r9\n \tadds\tr6, r1, r2\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n \tcmp\tr1, r6\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tr6, sl\n-\tadds\tr0, r1, r6\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tcmp\tr1, r0\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\taddgt\tr6, r9\n+\tadd\tr1, r6\n+\tcmp\tr0, r1\n+\tldr.w\tr0, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tr0, sl\n-\tadd.w\tip, r1, r0\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tcmp\tr1, ip\n-\tldr.w\tr1, [r7, #536]\t@ 0x218\n+\taddgt\tr1, r9\n+\tadd.w\tip, r0, r1\n+\tldr.w\tr0, [r7, #788]\t@ 0x314\n+\tcmp\tr0, ip\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n \tit\tgt\n-\taddgt\tip, sl\n-\tcmp\tr1, #0\n-\tble.w\t94a0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xdb4>\n-\tmov.w\tr1, ip, lsl #2\n-\tstr.w\tr1, [r7, #392]\t@ 0x188\n-\tlsls\tr1, r6, #2\n-\tstr.w\tr1, [r7, #368]\t@ 0x170\n-\tldr.w\tr1, [r7, #516]\t@ 0x204\n+\taddgt\tip, r9\n+\tcmp\tr0, #0\n+\tble.w\t98da <__gridxc_gpfa_core_sp_MOD_gpfa_+0xdfe>\n+\tmov.w\tr0, ip, lsl #2\n+\tstr.w\tr0, [r7, #552]\t@ 0x228\n+\tlsls\tr0, r6, #2\n+\tstr.w\tr0, [r7, #516]\t@ 0x204\n+\tldr.w\tr0, [r7, #720]\t@ 0x2d0\n \tadd.w\tr6, lr, #1073741824\t@ 0x40000000\n \tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n \tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n-\tadd.w\tip, r1, #1073741824\t@ 0x40000000\n-\tldr.w\tr1, [r7, #536]\t@ 0x218\n+\tadd.w\tip, r0, #1073741824\t@ 0x40000000\n+\tldr.w\tr0, [r7, #784]\t@ 0x310\n \tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n \tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n-\tadd.w\tr8, r1, lr\n+\tadd.w\tr8, r0, lr\n \tsubs\tr3, #1\n-\tldr.w\tr1, [r7, #360]\t@ 0x168\n+\tldr.w\tr0, [r7, #640]\t@ 0x280\n \tsubs\tr2, #1\n \tsubs\tr4, #1\n \tsubs\tr5, #1\n-\tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n+\tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n \tsubs\tr6, #1\n \tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tsubs\tr0, #1\n+\tsubs\tr1, #1\n \tlsls\tr3, r3, #2\n \tlsls\tr2, r2, #2\n \tlsls\tr4, r4, #2\n \tlsls\tr5, r5, #2\n \tlsls\tr6, r6, #2\n \tmov.w\tip, ip, lsl #2\n \tmov.w\tlr, lr, lsl #2\n-\tadd.w\tr1, r1, r8, lsl #2\n-\tlsls\tr0, r0, #2\n-\tadd.w\tr8, r9, ip\n-\tstr.w\tr1, [r7, #364]\t@ 0x16c\n+\tadd.w\tr0, r0, r8, lsl #2\n+\tlsls\tr1, r1, #2\n+\tadd.w\tr8, sl, ip\n+\tstr.w\tr0, [r7, #512]\t@ 0x200\n \tadd\tip, fp\n-\trsb\tr1, lr, #0\n-\tadd.w\tlr, r9, r6\n-\tstr.w\tr1, [r7, #376]\t@ 0x178\n+\trsb\tr0, lr, #0\n+\tadd.w\tlr, sl, r6\n+\tstr.w\tr0, [r7, #528]\t@ 0x210\n \tadd\tr6, fp\n-\tadd.w\tr1, r9, r3\n-\tstr.w\tr1, [r7, #444]\t@ 0x1bc\n-\tadd.w\tr1, r9, r2\n+\tadd.w\tr0, sl, r3\n+\tstr.w\tr0, [r7, #632]\t@ 0x278\n+\tadd.w\tr0, sl, r2\n \tadd\tr2, fp\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tadd.w\tr2, r9, r4\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tadd.w\tr2, sl, r4\n \tadd\tr4, fp\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tadd.w\tr2, r9, r5\n+\tstr.w\tr2, [r7, #576]\t@ 0x240\n+\tadd.w\tr2, sl, r5\n \tadd\tr5, fp\n \tadd\tr3, fp\n-\tstr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tstr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tadd.w\tr2, r9, r0\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tstr.w\tr2, [r7, #400]\t@ 0x190\n-\tadd.w\tr2, fp, r0\n-\tstr.w\tr2, [r7, #396]\t@ 0x18c\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tvldr\ts11, [lr]\n-\tvldr\ts9, [r6]\n-\tvldr\ts15, [r8]\n-\tvldr\ts12, [r2]\n-\tvcvt.f64.f32\td25, s11\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvcvt.f64.f32\td23, s9\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tstr.w\tr0, [r7, #608]\t@ 0x260\n+\tadd.w\tr2, sl, r1\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tr2, [r7, #568]\t@ 0x238\n+\tadd.w\tr2, fp, r1\n+\tstr.w\tr2, [r7, #560]\t@ 0x230\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n+\tvldr\ts14, [lr]\n+\tvldr\ts8, [r6]\n+\tvldr\ts2, [r8]\n+\tvldr\ts0, [r2]\n+\tvcvt.f64.f32\td7, s14\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvcvt.f64.f32\td4, s8\n \tvldr\ts10, [ip]\n-\tvcvt.f64.f32\td20, s15\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td0, s0\n+\tldr.w\tr1, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tvldr\ts12, [r2]\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tvadd.f64\td3, d0, d7\n+\tvsub.f64\td7, d7, d0\n \tvcvt.f64.f32\td6, s12\n-\tldr.w\tr0, [r7, #412]\t@ 0x19c\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tvldr\ts14, [r2]\n-\tvcvt.f64.f32\td19, s10\n-\tvmov.f64\td24, d20\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvadd.f64\td29, d6, d25\n-\tvldr\ts15, [r0]\n-\tvcvt.f64.f32\td26, s14\n-\tvsub.f64\td25, d25, d6\n-\tvmov.f64\td22, d19\n-\tvcvt.f64.f32\td27, s15\n+\tvmov.f64\td0, d1\n+\tvldr\ts18, [r1]\n+\tvldr\ts4, [r2]\n+\tvmls.f64\td0, d3, d10\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td8, d6, d4\n+\tvsub.f64\td6, d4, d6\n+\tvmov.f64\td4, d5\n+\tvadd.f64\td3, d1, d3\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td9, s18\n+\tvmls.f64\td4, d8, d10\n+\tvmul.f64\td6, d6, d15\n+\tvadd.f64\td5, d5, d8\n+\tvcvt.f32.f64\ts6, d3\n+\tvsub.f64\td1, d0, d6\n+\tvadd.f64\td6, d6, d0\n+\tvcvt.f32.f64\ts10, d5\n+\tvstmia\tr8!, {s6}\n+\tvadd.f64\td0, d4, d7\n+\tvcvt.f32.f64\ts2, d1\n+\tvstmia\tip!, {s10}\n+\tvsub.f64\td4, d4, d7\n+\tvcvt.f32.f64\ts23, d6\n+\tvcvt.f32.f64\ts0, d0\n+\tvstmia\tr2!, {s2}\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tvcvt.f32.f64\ts22, d4\n+\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tvstmia\tr1!, {s0}\n+\tstr.w\tr1, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n \tvldr\ts14, [r2]\n-\tvfms.f64\td24, d29, d21\n-\tvadd.f64\td20, d20, d29\n-\tvadd.f64\td28, d26, d23\n-\tvsub.f64\td26, d23, d26\n-\tvcvt.f64.f32\td23, s14\n-\tvcvt.f32.f64\ts15, d20\n-\tvfms.f64\td22, d28, d21\n-\tvadd.f64\td19, d19, d28\n-\tvmov.f64\td28, d24\n-\tvstmia\tr8!, {s15}\n-\tvfma.f64\td28, d17, d26\n-\tvcvt.f32.f64\ts12, d19\n-\tvfma.f64\td24, d16, d26\n-\tvmov.f64\td20, d22\n-\tvstmia\tip!, {s12}\n-\tvfma.f64\td20, d16, d25\n-\tvfma.f64\td22, d17, d25\n-\tvcvt.f32.f64\ts12, d28\n-\tvcvt.f32.f64\ts13, d24\n-\tvstmia\tr2!, {s12}\n-\tvcvt.f32.f64\ts15, d20\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tvcvt.f32.f64\ts14, d22\n-\tvstmia\tr0!, {s15}\n-\tstr.w\tr0, [r7, #412]\t@ 0x19c\n-\tldr.w\tr0, [r7, #440]\t@ 0x1b8\n-\tvldr\ts10, [r2]\n-\tvldr\ts12, [r5]\n-\tvldr\ts15, [r4]\n-\tvldr\ts11, [r0]\n-\tvcvt.f64.f32\td22, s10\n-\tvcvt.f64.f32\td24, s12\n-\tldr.w\tr0, [r7, #400]\t@ 0x190\n-\tvcvt.f64.f32\td19, s15\n-\tvcvt.f64.f32\td25, s11\n-\tvldr\ts11, [r3]\n-\tvldr\ts10, [r0]\n-\tvcvt.f64.f32\td20, s11\n-\tvadd.f64\td28, d25, d22\n-\tvsub.f64\td22, d22, d25\n-\tvadd.f64\td25, d24, d19\n-\tvsub.f64\td19, d19, d24\n-\tvmov.f64\td24, d23\n-\tvcvt.f64.f32\td26, s10\n-\tvfms.f64\td24, d28, d21\n-\tvadd.f64\td28, d28, d23\n-\tvmov.f64\td23, d27\n-\tvfms.f64\td23, d25, d21\n-\tvadd.f64\td25, d25, d27\n-\tvcvt.f32.f64\ts12, d28\n-\tvcvt.f32.f64\ts15, d25\n-\tvmov.f64\td5, d24\n-\tvfma.f64\td24, d16, d19\n-\tvfma.f64\td5, d17, d19\n-\tvstmia\tlr!, {s12}\n-\tvmov.f64\td19, d23\n-\tvfma.f64\td23, d17, d22\n-\tvfma.f64\td19, d16, d22\n-\tvstmia\tr6!, {s15}\n-\tvcvt.f32.f64\ts12, d24\n+\tvldr\ts10, [r5]\n+\tvldr\ts2, [r4]\n+\tvldr\ts8, [r1]\n+\tvcvt.f64.f32\td7, s14\n+\tvcvt.f64.f32\td5, s10\n+\tvldr\ts1, [r3]\n+\tvcvt.f64.f32\td1, s2\n+\tldr.w\tr1, [r7, #568]\t@ 0x238\n+\tvcvt.f64.f32\td4, s8\n+\tvcvt.f64.f32\td8, s1\n+\tvmov.f64\td0, d2\n+\tvldr\ts12, [r1]\n+\tvadd.f64\td3, d4, d7\n+\tvsub.f64\td7, d7, d4\n+\tvadd.f64\td4, d5, d1\n+\tvsub.f64\td5, d1, d5\n+\tvmov.f64\td1, d9\n+\tvcvt.f64.f32\td6, s12\n+\tvmls.f64\td0, d3, d10\n+\tvmul.f64\td7, d7, d15\n+\tvmls.f64\td1, d4, d10\n+\tvmul.f64\td5, d5, d15\n+\tvadd.f64\td3, d3, d2\n+\tvadd.f64\td4, d4, d9\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts8, d4\n+\tvsub.f64\td2, d0, d5\n+\tvadd.f64\td5, d5, d0\n+\tvadd.f64\td0, d1, d7\n+\tvsub.f64\td7, d1, d7\n+\tvstmia\tlr!, {s6}\n+\tvstmia\tr6!, {s8}\n \tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts15, d23\n-\tvcvt.f32.f64\ts11, d19\n-\tvstmia\tr2!, {s10}\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tvstmia\tr0!, {s12}\n-\tvstmia\tr4!, {s11}\n-\tvstmia\tr3!, {s15}\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldr.w\tr3, [r7, #376]\t@ 0x178\n-\tstr.w\tr0, [r7, #400]\t@ 0x190\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts0, d0\n+\tvstmia\tr2!, {s4}\n+\tstr.w\tr2, [r7, #576]\t@ 0x240\n+\tvstmia\tr1!, {s10}\n+\tvstmia\tr4!, {s0}\n+\tvstmia\tr3!, {s14}\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tstr.w\tr1, [r7, #568]\t@ 0x238\n \tadds\tr2, r6, r3\n-\tadd.w\tr0, lr, r3\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n-\tldr.w\tr1, [r7, #368]\t@ 0x170\n-\tadds\tr3, r0, r3\n-\tadd\tr0, r1\n-\tvldr\ts12, [r3, #-4]\n-\tvldr\ts15, [r0, #-4]\n-\tvstr\ts13, [r0, #-4]\n-\tvcvt.f64.f32\td24, s12\n-\tldr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tvcvt.f64.f32\td19, s15\n-\tvadd.f64\td25, d24, d26\n-\tvsub.f64\td24, d26, d24\n-\tvmov.f64\td23, d19\n-\tvadd.f64\td19, d19, d25\n-\tvfms.f64\td23, d25, d21\n-\tvcvt.f32.f64\ts15, d19\n-\tvstmia\tr0!, {s15}\n-\tstr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr0, [r7, #392]\t@ 0x188\n-\tadds\tr0, r2, r0\n-\tadd\tr2, r1\n-\tvldr\ts13, [r0, #-4]\n-\tvldr\ts15, [r2, #-4]\n-\tvstr\ts14, [r2, #-4]\n-\tvcvt.f64.f32\td22, s13\n-\tvmov.f64\td6, d23\n-\tvcvt.f64.f32\td19, s15\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvadd.f64\td26, d22, d20\n-\tvsub.f64\td20, d20, d22\n-\tvmov.f64\td22, d19\n-\tvfms.f64\td22, d26, d21\n-\tvfma.f64\td6, d17, d20\n-\tvfma.f64\td23, d16, d20\n-\tvadd.f64\td19, d19, d26\n-\tvcvt.f32.f64\ts15, d19\n-\tvmov.f64\td20, d22\n-\tvfma.f64\td22, d17, d24\n-\tvfma.f64\td20, d16, d24\n-\tvstmia\tr2!, {s15}\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr0, [r7, #516]\t@ 0x204\n+\tadds\tr3, r1, r3\n+\tadd\tr1, r0\n+\tvldr\ts10, [r3, #-4]\n+\tvldr\ts14, [r1, #-4]\n+\tvstr\ts23, [r1, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr1, [r7, #632]\t@ 0x278\n+\tvcvt.f64.f32\td7, s14\n+\tvadd.f64\td3, d5, d6\n+\tvsub.f64\td5, d6, d5\n+\tvmov.f64\td4, d7\n+\tvadd.f64\td7, d7, d3\n+\tvmls.f64\td4, d3, d10\n+\tvmul.f64\td5, d5, d15\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tr1!, {s14}\n+\tstr.w\tr1, [r7, #632]\t@ 0x278\n+\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tadds\tr1, r2, r1\n+\tadd\tr2, r0\n+\tvldr\ts14, [r1, #-4]\n+\tvldr\ts12, [r2, #-4]\n+\tvstr\ts22, [r2, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvcvt.f64.f32\td6, s12\n+\tvadd.f64\td2, d7, d8\n+\tvsub.f64\td7, d8, d7\n+\tvmov.f64\td3, d6\n+\tvmls.f64\td3, d2, d10\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td6, d6, d2\n+\tvsub.f64\td2, d4, d7\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts14, d23\n-\tstr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tvcvt.f32.f64\ts15, d22\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td4, d3, d5\n+\tvsub.f64\td3, d3, d5\n \tvstmia\tr2!, {s12}\n-\tvcvt.f32.f64\ts13, d20\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts14, d7\n+\tstr.w\tr2, [r7, #616]\t@ 0x268\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts6, d3\n+\tvstmia\tr2!, {s4}\n \tvstr\ts14, [r3, #-4]\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tstr.w\tr2, [r7, #440]\t@ 0x1b8\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tvstmia\tr5!, {s8}\n \tcmp\tlr, r3\n-\tvstmia\tr5!, {s13}\n-\tvstr\ts15, [r0, #-4]\n-\tbne.w\t924c <__gridxc_gpfa_core_sp_MOD_gpfa_+0xb60>\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tvstr\ts6, [r1, #-4]\n+\tbne.w\t9686 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xbaa>\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n \tadd\tr2, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n \tcmp\tr3, r2\n-\tble.n\t94be <__gridxc_gpfa_core_sp_MOD_gpfa_+0xdd2>\n-\tmov\tr3, r2\n-\tadd\tr3, sl\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n-\tldr.w\tr2, [r7, #352]\t@ 0x160\n+\tit\tgt\n+\tmovgt\tr3, r2\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\titt\tgt\n+\taddgt\tr3, r9\n+\tstrgt.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #380]\t@ 0x17c\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n \tcmp\tr3, r2\n-\tbne.w\t90fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa10>\n-\tldrd\tlr, r3, [r7, #276]\t@ 0x114\n-\tldr.w\tr2, [r7, #244]\t@ 0xf4\n-\tldr.w\tr1, [r7, #388]\t@ 0x184\n-\tsubs\tr2, #1\n-\tadd\tr1, r3\n-\tadds\tr5, r2, #1\n-\tldrd\tr8, r6, [r7, #284]\t@ 0x11c\n-\tstr.w\tr1, [r7, #388]\t@ 0x184\n-\tldrd\tip, sl, [r7, #256]\t@ 0x100\n-\tbne.w\t90d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x9ea>\n-\tldrd\tr0, r5, [r7, #312]\t@ 0x138\n-\tldr.w\tr1, [r7, #300]\t@ 0x12c\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n-\tsubs\tr1, #1\n-\tadd\tip, r0\n-\tadds\tr4, r1, #1\n-\tsub.w\tr2, r2, r0\n-\tstr.w\tr2, [r7, #384]\t@ 0x180\n-\tbne.w\t9094 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x9a8>\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tmov\tfp, r6\n-\tmov\tr6, lr\n-\tldr.w\tr9, [r7, #428]\t@ 0x1ac\n-\tmov\tlr, r8\n-\tmov\tr4, sl\n-\tldr.w\tr8, [r7, #356]\t@ 0x164\n-\tcmp\tr3, r6\n-\tbne.w\t9cca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15de>\n-\tldr.w\tr6, [r7, #308]\t@ 0x134\n-\tldr.w\tfp, [r7, #560]\t@ 0x230\n-\tldr.w\tr5, [r7, #304]\t@ 0x130\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tadds\tr6, #1\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tmla\tfp, r2, r3, fp\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tcmp\tr6, r3\n-\tbeq.w\ta9e0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22f4>\n+\tbne.w\t9536 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa5a>\n+\tldr.w\tr3, [r7, #336]\t@ 0x150\n+\tldr.w\tip, [r7, #408]\t@ 0x198\n+\tldr.w\tr2, [r7, #312]\t@ 0x138\n+\tsubs\tr3, #1\n+\tldr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tadds\tr0, r3, #1\n+\tldr.w\tr8, [r7, #416]\t@ 0x1a0\n+\tadd\tr2, ip\n+\tldr.w\tr4, [r7, #360]\t@ 0x168\n+\tbne.w\t9510 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa34>\n+\tmov\tr9, ip\n+\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #548]\t@ 0x224\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tadd\tr4, r3\n+\tsub.w\tr3, r2, r3\n+\tstr.w\tr3, [r7, #548]\t@ 0x224\n+\tbne.w\t94d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x9fa>\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tmov\tr4, r6\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tldr.w\tr5, [r7, #504]\t@ 0x1f8\n+\tldr.w\tsl, [r7, #508]\t@ 0x1fc\n+\tcmp\tr3, r2\n+\tbne.w\ta10e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1632>\n+\tldr.w\tr8, [r7, #352]\t@ 0x160\n+\tldr.w\tr5, [r7, #344]\t@ 0x158\n+\tldrd\tr2, r3, [r7, #784]\t@ 0x310\n+\tadd.w\tr8, r8, #1\n+\tldr.w\tr1, [r7, #676]\t@ 0x2a4\n+\tmla\tr3, r1, r2, r3\n+\tstr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr3, [r7, #308]\t@ 0x134\n+\tcmp\tr8, r3\n+\tbeq.w\tae72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2396>\n \tmov\tr2, r5\n-\tstr.w\tr5, [r7, #536]\t@ 0x218\n-\tb.w\t89aa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2be>\n-\tldr.w\tr5, [r7, #416]\t@ 0x1a0\n-\tlsls\tr4, r1, #3\n-\tlsls\tr1, r1, #4\n-\tstr.w\tr4, [r7, #424]\t@ 0x1a8\n-\tstr.w\tr1, [r7, #400]\t@ 0x190\n-\tmov\tr1, r4\n-\tadds\tr4, r5, r4\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n-\tadd.w\tlr, r4, r1\n-\tsub.w\tr1, r8, r0\n-\tadds\tr5, #1\n-\tstr.w\tr5, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr5, [r7, #372]\t@ 0x174\n-\tmov\tip, lr\n-\tstr.w\tr1, [r7, #492]\t@ 0x1ec\n-\tmov\tr1, r0\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tstr.w\tsl, [r7, #516]\t@ 0x204\n-\tvldr\td24, [r4, #8]\n-\tcmp.w\tr9, #0\n-\tvldr\td25, [ip, #8]\n-\tvldr\td26, [r4]\n-\tvmul.f64\td24, d18, d24\n-\tvldr\td27, [ip]\n-\tvmul.f64\td25, d18, d25\n-\tblt.w\t97ac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10c0>\n-\tldr.w\tr4, [r7, #492]\t@ 0x1ec\n-\tcmp\tr8, r1\n-\tudiv\tr4, r4, r9\n-\tblt.w\t9786 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x109a>\n-\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n-\tcmp\tr6, #0\n-\tble.w\t9786 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x109a>\n-\tstr.w\tr0, [r7, #396]\t@ 0x18c\n-\tadd.w\tsl, fp, r1\n-\tmov\tr0, ip\n-\tmov\tip, r9\n-\tmovs\tr6, #1\n-\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr5, [r7, #784]\t@ 0x310\n+\tb.w\t8dbc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e0>\n+\tlsls\tr1, r3, #3\n+\tlsls\tr3, r3, #4\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tvmov.f64\td13, #96\t@ 0x3f000000 0.5\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tldr.w\tr6, [r7, #784]\t@ 0x310\n+\tadds\tr0, r3, r1\n+\tldr.w\tfp, [r7, #520]\t@ 0x208\n+\tadds\tr2, r0, r1\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tadds\tr6, #1\n+\tstr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr6, [r7, #624]\t@ 0x270\n+\tmov\tr5, r9\n+\trsb\tr6, r9, #0\n+\tmov\tr9, r2\n+\tstr.w\tr6, [r7, #568]\t@ 0x238\n \tmov\tr6, sl\n-\tstrd\tip, r8, [r7, #388]\t@ 0x184\n-\tstrd\tr1, r2, [r7, #380]\t@ 0x17c\n-\tstr.w\tr4, [r7, #376]\t@ 0x178\n-\tstr.w\tsl, [r7, #368]\t@ 0x170\n-\tstr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tadd\tr2, r6\n-\tldr.w\tr0, [r7, #536]\t@ 0x218\n-\tcmp\tfp, r2\n+\tmov\tsl, r8\n+\tsub.w\tr3, r3, r8\n+\tstr.w\tr2, [r7, #632]\t@ 0x278\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr1, [r7, #560]\t@ 0x230\n+\tvldr\td11, [r0, #8]\n+\tcmp\tr5, #0\n+\tvldr\td8, [r9, #8]\n+\tvldr\td12, [r0]\n+\tvmul.f64\td11, d14, d11\n+\tvldr\td9, [r9]\n+\tvmul.f64\td8, d14, d8\n+\tblt.w\t9be0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1104>\n+\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tblt.w\t9bb2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10d6>\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tcmp\tr2, #0\n+\tble.w\t9bb2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10d6>\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tmov\tr1, r5\n+\tstr.w\tsl, [r7, #552]\t@ 0x228\n+\tadd\tr2, r8\n+\tmov\tip, r2\n+\tmovs\tr5, #1\n+\tstr.w\tr1, [r7, #548]\t@ 0x224\n+\tstr.w\tr6, [r7, #536]\t@ 0x218\n+\tstr.w\tr8, [r7, #528]\t@ 0x210\n+\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr2, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tadd\tr3, ip\n+\tcmp\tr2, r3\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n \tit\tgt\n-\taddgt\tr2, r2, r3\n-\tadd\tr1, r2\n-\tcmp\tfp, r1\n+\taddgt\tr3, r3, r4\n+\tadds\tr1, r2, r3\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tcmp\tr2, r1\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tit\tgt\n-\taddgt\tr1, r1, r3\n-\tcmp\tr0, #0\n-\tble.w\t973e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1052>\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tlsls\tr2, r2, #2\n+\taddgt\tr1, r1, r4\n+\tcmp\tr2, #0\n+\tble.w\t9b72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1096>\n+\tldr.w\tr6, [r7, #752]\t@ 0x2f0\n+\tlsls\tr3, r3, #2\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n \tlsls\tr1, r1, #2\n-\tlsls\tr4, r6, #2\n-\tadd.w\tr9, r0, r2\n-\tldr.w\tr0, [r7, #524]\t@ 0x20c\n+\tmov.w\tr0, ip, lsl #2\n+\tadd.w\tr8, r6, r3\n+\tadd.w\tlr, r6, r1\n+\tadd\tr3, r2\n+\tadd\tr6, r0\n+\tadd\tr1, r2\n+\tadd\tr0, r2\n \tmov.w\tsl, #1\n-\tstr.w\tr3, [r7, #364]\t@ 0x16c\n-\tadd\tr2, r0\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tadd.w\tr8, r0, r1\n-\tldr.w\tr0, [r7, #524]\t@ 0x20c\n-\tadd\tr1, r0\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tadd.w\tip, r0, r4\n-\tldr.w\tr0, [r7, #524]\t@ 0x20c\n-\tadd\tr4, r0\n-\tldr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tvldr\ts11, [r1, #-4]\n+\tvldr\ts4, [r3, #-4]\n \tadd.w\tsl, sl, #1\n-\tvldr\ts12, [r2, #-4]\n-\tvldr\ts14, [r9, #-4]\n-\tvldr\ts15, [r8, #-4]\n-\tvcvt.f64.f32\td31, s11\n-\tvldr\ts10, [r4, #-4]\n+\tvldr\ts12, [r1, #-4]\n+\tvldr\ts14, [r8, #-4]\n+\tvldr\ts6, [lr, #-4]\n+\tvcvt.f64.f32\td2, s4\n \tvcvt.f64.f32\td6, s12\n-\tvldr\ts9, [ip, #-4]\n-\tvcvt.f64.f32\td20, s14\n-\tvcvt.f64.f32\td19, s15\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tvldr\ts8, [r6, #-4]\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts10, [r0, #-4]\n+\tvcvt.f64.f32\td3, s6\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tvcvt.f64.f32\td4, s8\n+\tvadd.f64\td1, d2, d6\n+\tvsub.f64\td2, d2, d6\n \tvcvt.f64.f32\td5, s10\n-\tvadd.f64\td28, d6, d31\n-\tvcvt.f64.f32\td30, s9\n-\tvsub.f64\td31, d6, d31\n-\tcmp\tsl, r3\n-\tvadd.f64\td7, d20, d19\n-\tvsub.f64\td20, d20, d19\n-\tvmov.f64\td21, d5\n-\tvmov.f64\td22, d5\n-\tvfms.f64\td21, d28, d23\n-\tvmov.f64\td29, d30\n-\tvfnms.f64\td22, d28, d23\n-\tvadd.f64\td28, d28, d5\n-\tvfms.f64\td29, d7, d23\n-\tvadd.f64\td7, d7, d30\n-\tvfma.f64\td22, d16, d20\n-\tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d28\n-\tvmov.f64\td19, d21\n-\tvfma.f64\td21, d20, d17\n-\tvfma.f64\td19, d16, d20\n-\tvmov.f64\td30, d29\n-\tvfma.f64\td29, d16, d31\n-\tvfma.f64\td30, d31, d17\n-\tvstr\ts14, [ip, #-4]\n-\tvstr\ts15, [r4, #-4]\n-\tadd\tip, r5\n-\tvmul.f64\td22, d25, d22\n-\tadd\tr4, r5\n-\tvmul.f64\td20, d27, d21\n-\tvnmul.f64\td28, d19, d24\n-\tvmul.f64\td19, d26, d19\n-\tvfma.f64\td22, d27, d29\n-\tvfma.f64\td20, d25, d29\n-\tvfma.f64\td28, d26, d30\n-\tvfma.f64\td19, d24, d30\n-\tvcvt.f32.f64\ts13, d22\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts12, d28\n-\tvcvt.f32.f64\ts15, d19\n-\tvstr\ts12, [r9, #-4]\n-\tadd\tr9, r5\n-\tvstr\ts15, [r2, #-4]\n-\tadd\tr2, r5\n-\tvstr\ts13, [r8, #-4]\n-\tadd\tr8, r5\n-\tvstr\ts14, [r1, #-4]\n-\tadd\tr1, r5\n-\tbne.n\t9652 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf66>\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tstr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n-\tadd\tr6, r2\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tcmp\tfp, r6\n-\tadd.w\tr2, r2, #1\n+\tcmp\tsl, r2\n+\tvadd.f64\td6, d7, d3\n+\tvsub.f64\td7, d7, d3\n+\tvmul.f64\td3, d1, d13\n+\tvmul.f64\td0, d2, d15\n+\tvmov.f64\td2, d4\n+\tvadd.f64\td1, d1, d5\n+\tvmls.f64\td2, d6, d13\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td6, d6, d4\n+\tvsub.f64\td4, d5, d3\n+\tvsub.f64\td3, d3, d5\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts12, d6\n+\tvadd.f64\td5, d7, d4\n+\tvadd.f64\td10, d3, d7\n+\tvsub.f64\td7, d4, d7\n+\tvstr\ts2, [r0, #-4]\n+\tvadd.f64\td3, d2, d0\n+\tvsub.f64\td2, d2, d0\n+\tvstr\ts12, [r6, #-4]\n+\tadd\tr0, fp\n+\tvmul.f64\td4, d11, d5\n+\tvmul.f64\td5, d12, d5\n+\tadd\tr6, fp\n+\tvmul.f64\td6, d9, d3\n+\tvmul.f64\td3, d8, d3\n+\tvmla.f64\td3, d7, d9\n+\tvmla.f64\td5, d11, d2\n+\tvmla.f64\td6, d10, d8\n+\tvnmls.f64\td4, d12, d2\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts14, d4\n+\tvstr\ts10, [r3, #-4]\n+\tadd\tr3, fp\n+\tvstr\ts14, [r8, #-4]\n+\tadd\tr8, fp\n+\tvstr\ts6, [r1, #-4]\n+\tadd\tr1, fp\n+\tvstr\ts12, [lr, #-4]\n+\tadd\tlr, fp\n+\tbne.n\t9a92 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xfb6>\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tadds\tr5, #1\n+\tadd\tip, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tcmp\tr3, ip\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tit\tgt\n-\taddgt\tr6, r6, r3\n-\tstr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tcmp\tr2, r1\n-\tbne.w\t95f4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf08>\n-\tldrd\tip, r8, [r7, #388]\t@ 0x184\n-\tldr.w\tr4, [r7, #376]\t@ 0x178\n-\tldr.w\tsl, [r7, #368]\t@ 0x170\n-\tsubs\tr4, #1\n-\tldr.w\tr0, [r7, #444]\t@ 0x1bc\n-\tldrd\tr1, r2, [r7, #380]\t@ 0x17c\n-\tadd\tsl, ip\n-\tadds\tr6, r4, #1\n-\tbne.w\t95d8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xeec>\n-\tmov\tr9, ip\n-\tmov\tip, r0\n-\tldr.w\tr0, [r7, #396]\t@ 0x18c\n-\tldr.w\tr4, [r7, #400]\t@ 0x190\n-\tsubs\tr2, #1\n-\tadd\tr1, r0\n-\tadds\tr6, r2, #1\n-\tadd\tip, r4\n-\tldr.w\tr4, [r7, #492]\t@ 0x1ec\n-\tsub.w\tr4, r4, r0\n-\tstr.w\tr4, [r7, #492]\t@ 0x1ec\n-\tmov\tr4, lr\n-\tbeq.w\ta9d8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22ec>\n-\tldr.w\tr6, [r7, #424]\t@ 0x1a8\n-\tadd\tlr, r6\n-\tb.n\t9594 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xea8>\n-\tsub.w\tr4, r1, r8\n-\trsb\tr6, r9, #0\n-\tcmp\tr8, r1\n-\tudiv\tr4, r4, r6\n-\tble.w\t95c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xed6>\n-\tb.n\t9786 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x109a>\n-\tldr.w\tr4, [r7, #428]\t@ 0x1ac\n-\tsub.w\tr2, ip, r4\n-\tldr.w\tr4, [r7, #344]\t@ 0x158\n-\tudiv\tr2, r2, r4\n-\tldr.w\tr4, [r7, #428]\t@ 0x1ac\n-\tcmp\tr4, ip\n-\tble.w\t90ac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x9c0>\n-\tb.n\t94fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe10>\n-\tldr.w\tr2, [r7, #536]\t@ 0x218\n-\tmov.w\tsl, #0\n-\tmov\tip, r9\n-\tstr.w\tr9, [r7, #368]\t@ 0x170\n-\tadds\tr2, #1\n-\tstr.w\tsl, [r7, #444]\t@ 0x1bc\n-\tstrd\tr8, r2, [r7, #312]\t@ 0x138\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tldr.w\tr8, [r7, #524]\t@ 0x20c\n-\tldr.w\tr9, [r7, #560]\t@ 0x230\n-\tldr.w\tsl, [r7, #372]\t@ 0x174\n-\tstr.w\tfp, [r7, #300]\t@ 0x12c\n-\tstr.w\tlr, [r7, #288]\t@ 0x120\n-\tstrd\tr4, r6, [r7, #280]\t@ 0x118\n-\tcmp\tr3, #0\n-\tblt.w\ta9a2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22b6>\n-\tldr.w\tr4, [r7, #368]\t@ 0x170\n-\tudiv\tr2, ip, r3\n-\tldr.w\tr6, [r7, #444]\t@ 0x1bc\n-\tcmp\tr4, r6\n-\tblt.w\t9c96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15aa>\n-\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n-\tcmp\tr6, #0\n-\tble.w\t9c96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15aa>\n-\tldr.w\tr4, [r7, #444]\t@ 0x1bc\n-\tmov\tfp, r9\n-\tadds\tr6, #1\n-\tmov\tlr, r1\n-\tadd\tr4, r9\n-\tldr.w\tr9, [r7, #552]\t@ 0x228\n-\tstr.w\tr6, [r7, #352]\t@ 0x160\n-\tmov\tr6, sl\n-\tmovs\tr1, #1\n-\tstr.w\tr5, [r7, #276]\t@ 0x114\n-\tstr.w\tr1, [r7, #404]\t@ 0x194\n-\tstrd\tlr, r0, [r7, #256]\t@ 0x100\n-\tstrd\tr2, r3, [r7, #240]\t@ 0xf0\n-\tstr.w\tr4, [r7, #516]\t@ 0x204\n-\tstrd\tip, r4, [r7, #232]\t@ 0xe8\n-\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n+\taddgt\tip, r4\n+\tcmp\tr5, r3\n+\tbne.w\t9a44 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf68>\n \tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n \tldr.w\tr2, [r7, #516]\t@ 0x204\n+\tsubs\tr3, #1\n+\tldr.w\tr6, [r7, #536]\t@ 0x218\n+\tadds\tr5, r3, #1\n+\tldr.w\tr8, [r7, #528]\t@ 0x210\n+\tadd\tr2, r1\n+\tbne.w\t9a2c <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf50>\n+\tldr.w\tsl, [r7, #552]\t@ 0x228\n+\tmov\tr5, r1\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tsubs\tr6, #1\n+\tadd\tr8, sl\n+\tadds\tr2, r6, #1\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tsub.w\tr3, r3, sl\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tmov\tr0, r3\n+\tbeq.w\tae68 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x238c>\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tb.n\t99e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf06>\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #568]\t@ 0x238\n+\tsub.w\tr0, r8, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr3, r0\n+\tcmp\tr2, r8\n+\tble.w\t9a16 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xf3a>\n+\tb.n\t9bb2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x10d6>\n+\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tsubs\tr0, r4, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, r4\n+\tmov\tr3, r0\n+\tble.w\t94f4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xa18>\n+\tb.n\t9932 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe56>\n+\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tmovs\tr6, #0\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr9, [r7, #500]\t@ 0x1f4\n+\tadds\tr3, #1\n+\tldr.w\tr9, [r7, #788]\t@ 0x314\n+\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tstr.w\tr5, [r7, #336]\t@ 0x150\n+\tmov\tr5, r4\n+\tadds\tr3, #1\n+\tstr.w\tsl, [r7, #416]\t@ 0x1a0\n+\tstr.w\tr3, [r7, #360]\t@ 0x168\n+\tstr.w\tr8, [r7, #408]\t@ 0x198\n+\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tcmp\tr3, #0\n+\tblt.w\tae38 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x235c>\n+\tmov\tr1, r3\n+\tldr.w\tr0, [r7, #504]\t@ 0x1f8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr3, r0\n+\tcmp\tr2, r6\n+\tblt.w\ta0d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15fa>\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tcmp\tr2, #0\n+\tble.w\ta0d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15fa>\n+\tadd.w\tr2, r9, r6\n+\tmov\tsl, r9\n+\tldr.w\tlr, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr9, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr8, [r7, #520]\t@ 0x208\n+\tstr.w\tr6, [r7, #312]\t@ 0x138\n+\tmovs\tr1, #1\n+\tstr.w\tr5, [r7, #296]\t@ 0x128\n+\tstr.w\tr1, [r7, #584]\t@ 0x248\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr2, [r7, #292]\t@ 0x124\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n \tadds\tr4, r3, r2\n-\tcmp\tfp, r4\n-\tble.n\t987a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x118e>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tlr, r3, r4\n-\tcmp\tfp, lr\n-\tble.n\t988c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11a0>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tlr, r3\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tcmp\tsl, r4\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr4, r4, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd.w\tip, r3, r4\n+\tcmp\tsl, ip\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tip, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tadds\tr2, r3, r2\n-\tcmp\tfp, r2\n-\tble.n\t98a0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11b4>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tcmp\tsl, r2\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tadds\tr0, r3, r2\n-\tcmp\tfp, r0\n-\tble.n\t98b0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11c4>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr0, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tip, r3, r0\n-\tcmp\tfp, ip\n-\tble.n\t98c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11d6>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tip, r3\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tcmp\tsl, r0\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr0, r0, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadds\tr6, r3, r0\n+\tcmp\tsl, r6\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr6, r6, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tadd\tr3, r2\n-\tcmp\tfp, r3\n-\tble.n\t98d2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11e6>\n-\tldr.w\tr1, [r7, #556]\t@ 0x22c\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tcmp\tsl, r3\n+\titt\tgt\n+\tldrgt.w\tr1, [r7, #768]\t@ 0x300\n+\taddgt\tr3, r3, r1\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n \tadd\tr1, r3\n-\tcmp\tfp, r1\n-\tble.n\t98e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11f6>\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tadd\tr1, r5\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tadd\tr5, r1\n-\tcmp\tfp, r5\n-\tble.n\t98f2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1206>\n-\tldr.w\tr6, [r7, #556]\t@ 0x22c\n-\tadd\tr5, r6\n-\tldr.w\tr6, [r7, #536]\t@ 0x218\n-\tcmp\tr6, #0\n-\tble.w\t9c42 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1556>\n-\tldr.w\tr6, [r7, #516]\t@ 0x204\n+\tcmp\tsl, r1\n+\titt\tgt\n+\tldrgt.w\tr5, [r7, #768]\t@ 0x300\n+\taddgt\tr1, r1, r5\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n+\tadd.w\tfp, r5, r1\n+\tcmp\tsl, fp\n+\titt\tgt\n+\tldrgt.w\tr5, [r7, #768]\t@ 0x300\n+\taddgt\tfp, r5\n+\tldr.w\tr5, [r7, #784]\t@ 0x310\n+\tcmp\tr5, #0\n+\tble.w\ta086 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15aa>\n+\tlsls\tr3, r3, #2\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tmov.w\tr5, fp, lsl #2\n \tlsls\tr4, r4, #2\n-\tmov.w\tlr, lr, lsl #2\n+\tmov.w\tip, ip, lsl #2\n \tlsls\tr2, r2, #2\n \tlsls\tr0, r0, #2\n-\tmov.w\tip, ip, lsl #2\n-\tmov.w\tsl, r6, lsl #2\n+\tmov.w\tfp, r3, lsl #2\n+\tlsls\tr6, r6, #2\n \tlsls\tr1, r1, #2\n-\tlsls\tr5, r5, #2\n-\tlsls\tr3, r3, #2\n-\tadd.w\tr6, r9, r4\n-\tstr.w\tr6, [r7, #400]\t@ 0x190\n-\tadd.w\tr6, r9, lr\n-\tstr.w\tr6, [r7, #396]\t@ 0x18c\n-\tadd.w\tr6, r9, sl\n-\tstr.w\tr6, [r7, #364]\t@ 0x16c\n-\tadd.w\tr6, r9, r2\n-\tstr.w\tr6, [r7, #392]\t@ 0x188\n-\tadd.w\tr6, r9, r0\n-\tstr.w\tr6, [r7, #388]\t@ 0x184\n-\tadd.w\tr6, r9, ip\n-\tstr.w\tr6, [r7, #384]\t@ 0x180\n-\tadd.w\tr6, r9, r1\n-\tstr.w\tr6, [r7, #380]\t@ 0x17c\n-\tadd.w\tr6, r9, r5\n-\tstr.w\tr6, [r7, #376]\t@ 0x178\n-\tadd.w\tr6, r9, r3\n-\tstr.w\tr6, [r7, #360]\t@ 0x168\n-\tmovs\tr6, #1\n-\tstr.w\tr6, [r7, #412]\t@ 0x19c\n-\tldr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tadd\tr4, r8\n-\tadd\tlr, r8\n-\tadd\tsl, r8\n-\tadd\tip, r8\n-\tadd\tr5, r8\n-\tadd\tr2, r8\n-\tadd\tr0, r8\n-\tadd\tr1, r8\n-\tadd\tr3, r8\n-\tstrd\tr0, r2, [r7, #424]\t@ 0x1a8\n-\tstr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tstr.w\tr3, [r7, #356]\t@ 0x164\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tvldr\ts9, [r4, #-4]\n-\tvldr\ts14, [lr, #-4]\n-\tvldr\ts10, [sl, #-4]\n-\tvldr\ts11, [r3, #-4]\n-\tvcvt.f64.f32\td24, s9\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tvcvt.f64.f32\td27, s14\n-\tldr.w\tr2, [r7, #392]\t@ 0x188\n-\tvcvt.f64.f32\td22, s11\n+\tadd.w\tr3, r9, r4\n+\tstr.w\tr3, [r7, #576]\t@ 0x240\n+\tadd.w\tr3, r9, ip\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tadd.w\tr3, r9, fp\n+\tstr.w\tr3, [r7, #516]\t@ 0x204\n+\tadd.w\tr3, r9, r2\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tadd.w\tr3, r9, r0\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tadd.w\tr3, r9, r6\n+\tstr.w\tr3, [r7, #548]\t@ 0x224\n+\tadd.w\tr3, r9, r1\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n+\tadd.w\tr3, r9, r5\n+\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tadd\tr4, lr\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tadd\tip, lr\n+\tadd\tfp, lr\n+\tadd\tr6, lr\n+\tadd\tr3, r9\n+\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tadd\tr5, lr\n+\tadd\tr2, lr\n+\tadd\tr0, lr\n+\tadd\tr3, lr\n+\tadd\tr1, lr\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tmovs\tr3, #1\n+\tstr.w\tr2, [r7, #632]\t@ 0x278\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tstr.w\tr0, [r7, #624]\t@ 0x270\n+\tstr.w\tr1, [r7, #616]\t@ 0x268\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tldr.w\tr0, [r7, #632]\t@ 0x278\n+\tvldr\ts10, [r4, #-4]\n+\tvldr\ts12, [ip, #-4]\n+\tvldr\ts14, [r3, #-4]\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n \tvcvt.f64.f32\td5, s10\n-\tldr.w\tr0, [r7, #428]\t@ 0x1ac\n-\tvldr\ts12, [r3, #-4]\n-\tvadd.f64\td19, d24, d27\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tvsub.f64\td27, d24, d27\n-\tvldr\ts14, [r2, #-4]\n+\tvldr\ts16, [r0, #-4]\n \tvcvt.f64.f32\td6, s12\n-\tldr.w\tr2, [r7, #412]\t@ 0x19c\n-\tadds\tr1, r3, r6\n-\tstr.w\tr1, [r7, #364]\t@ 0x16c\n-\tvldr\ts15, [r3, #-4]\n-\tvcvt.f64.f32\td24, s14\n+\tvcvt.f64.f32\td7, s14\n+\tvldr\ts2, [fp, #-4]\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tvldr\ts8, [r3, #-4]\n+\tvcvt.f64.f32\td9, s16\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts4, [r2, #-4]\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tadd.w\tr1, r3, r8\n+\tvldr\ts0, [r3, #-4]\n \tadds\tr2, #1\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tvadd.f64\td21, d22, d6\n-\tvsub.f64\td22, d22, d6\n-\tvcvt.f64.f32\td25, s15\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n-\tvldr\ts15, [r0, #-4]\n-\tvmov.f64\td6, d25\n-\tvcvt.f64.f32\td23, s15\n-\tvfms.f64\td6, d21, d20\n-\tvadd.f64\td21, d21, d25\n-\tvmov.f64\td25, d5\n-\tvfms.f64\td25, d19, d20\n-\tvadd.f64\td19, d19, d5\n-\tvcvt.f32.f64\ts14, d21\n-\tvcvt.f32.f64\ts15, d19\n-\tvmov.f64\td26, d6\n-\tvstr\ts14, [r3, #-4]\n-\tvfma.f64\td26, d27, d17\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n-\tvmov.f64\td21, d25\n-\tvstr\ts15, [sl, #-4]\n-\tvfma.f64\td21, d16, d22\n-\tvfma.f64\td6, d16, d27\n-\tvfma.f64\td25, d22, d17\n-\tadds\tr1, r3, r6\n-\tadd\tsl, r6\n-\tvcvt.f32.f64\ts14, d26\n-\tvcvt.f32.f64\ts15, d21\n-\tvmov.f64\td21, d23\n-\tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d25\n-\tvstr\ts14, [r3, #-4]\n-\tvldr\ts10, [r2, #-4]\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n-\tvstr\ts15, [r0, #-4]\n-\tvldr\ts14, [ip, #-4]\n-\tvcvt.f64.f32\td27, s10\n-\tldr.w\tr0, [r7, #420]\t@ 0x1a4\n-\tvldr\ts11, [r2, #-4]\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvcvt.f64.f32\td22, s11\n-\tvldr\ts11, [r0, #-4]\n-\tvldr\ts15, [r2, #-4]\n-\tldr.w\tr2, [r7, #380]\t@ 0x17c\n-\tvcvt.f64.f32\td25, s11\n-\tvadd.f64\td29, d27, d22\n-\tvsub.f64\td27, d27, d22\n-\tvcvt.f64.f32\td19, s15\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tvadd.f64\td3, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvcvt.f64.f32\td0, s0\n+\tvadd.f64\td4, d5, d6\n+\tvsub.f64\td6, d5, d6\n+\tvmov.f64\td5, d1\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tvcvt.f64.f32\td2, s4\n+\tvmul.f64\td7, d7, d15\n+\tstr.w\tr1, [r7, #516]\t@ 0x204\n+\tvmov.f64\td8, d0\n+\tvmls.f64\td5, d4, d10\n+\tvmls.f64\td8, d3, d10\n+\tvmul.f64\td6, d6, d15\n+\tvadd.f64\td3, d3, d0\n+\tvadd.f64\td4, d4, d1\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts8, d4\n+\tvadd.f64\td0, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvsub.f64\td1, d8, d6\n+\tvadd.f64\td6, d8, d6\n+\tvstr\ts6, [r3, #-4]\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tvstr\ts8, [fp, #-4]\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts22, d5\n+\tvcvt.f32.f64\ts23, d6\n+\tadd.w\tr1, r3, r8\n+\tstr.w\tr1, [r7, #560]\t@ 0x230\n+\tadd\tfp, r8\n+\tvstr\ts0, [r0, #-4]\n+\tvstr\ts2, [r3, #-4]\n+\tvldr\ts14, [r2, #-4]\n+\tldr.w\tr2, [r7, #548]\t@ 0x224\n+\tvldr\ts10, [r6, #-4]\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n \tvcvt.f64.f32\td7, s14\n-\tvmov.f64\td22, d24\n-\tvldr\ts10, [r2, #-4]\n-\tvfms.f64\td22, d29, d20\n-\tstr.w\tr1, [r7, #392]\t@ 0x188\n-\tvadd.f64\td28, d19, d7\n-\tvsub.f64\td19, d19, d7\n-\tvcvt.f64.f32\td26, s10\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tvadd.f64\td24, d24, d29\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n-\tadd\tr3, r6\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tvfms.f64\td21, d28, d20\n-\tvadd.f64\td23, d23, d28\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tvcvt.f32.f64\ts14, d24\n-\tvmov.f64\td5, d22\n-\tvfma.f64\td22, d16, d19\n-\tvfma.f64\td5, d19, d17\n-\tvcvt.f32.f64\ts15, d23\n-\tadds\tr1, r3, r6\n-\tstr.w\tr1, [r7, #400]\t@ 0x190\n-\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tvstr\ts14, [r3, #-4]\n-\tvmov.f64\td19, d21\n-\tvfma.f64\td21, d27, d17\n-\tvfma.f64\td19, d16, d27\n-\tvstr\ts15, [r4, #-4]\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n-\tadd\tr4, r6\n-\tvcvt.f32.f64\ts14, d22\n+\tvldr\ts8, [r2, #-4]\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts2, [r2, #-4]\n+\tldr.w\tr2, [r7, #536]\t@ 0x218\n+\tvadd.f64\td3, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts12, [r2, #-4]\n+\tvldr\ts1, [r0, #-4]\n+\tvmul.f64\td7, d7, d15\n+\tvadd.f64\td4, d1, d5\n+\tvsub.f64\td5, d1, d5\n+\tvmov.f64\td1, d9\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tvcvt.f64.f32\td8, s1\n+\tvmov.f64\td0, d2\n+\tvmls.f64\td0, d3, d10\n+\tvadd.f64\td3, d2, d3\n+\tvmls.f64\td1, d4, d10\n+\tvmul.f64\td5, d5, d15\n+\tvadd.f64\td4, d9, d4\n+\tadd\tr3, r8\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tvcvt.f64.f32\td6, s12\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tvcvt.f32.f64\ts6, d3\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tadd.w\tr1, r3, r8\n+\tvcvt.f32.f64\ts8, d4\n+\tstr.w\tr1, [r7, #576]\t@ 0x240\n+\tvsub.f64\td2, d0, d5\n+\tvadd.f64\td5, d0, d5\n+\tvadd.f64\td0, d7, d1\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n+\tvsub.f64\td7, d1, d7\n+\tvstr\ts6, [r3, #-4]\n+\tvstr\ts8, [r4, #-4]\n+\tadd\tr4, r8\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts0, d0\n \tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts15, d21\n-\tvstr\ts10, [r2, #-4]\n-\tvcvt.f32.f64\ts11, d19\n-\tvstr\ts14, [r3, #-4]\n-\tadd\tr2, r6\n-\tstr.w\tr2, [r7, #388]\t@ 0x184\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts4, [r2, #-4]\n+\tadd\tr2, r8\n+\tvstr\ts0, [r1, #-4]\n+\tldr.w\tr1, [r7, #528]\t@ 0x210\n+\tvstr\ts10, [r3, #-4]\n+\tvstr\ts14, [r0, #-4]\n+\tldr.w\tr0, [r7, #508]\t@ 0x1fc\n+\tvldr\ts15, [r1, #-4]\n+\tldr.w\tr1, [r7, #512]\t@ 0x200\n+\tvldr\ts10, [r5, #-4]\n+\tvcvt.f64.f32\td7, s15\n+\tvldr\ts4, [r0, #-4]\n+\tstr.w\tr2, [r7, #552]\t@ 0x228\n \tmov\tr2, r3\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tadd\tr2, r6\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tvstr\ts11, [r1, #-4]\n-\tadd\tr3, r6\n-\tldr.w\tr1, [r7, #376]\t@ 0x178\n-\tvstr\ts15, [r0, #-4]\n-\tldr.w\tr0, [r7, #356]\t@ 0x164\n-\tvldr\ts9, [r5, #-4]\n-\tvldr\ts10, [r1, #-4]\n-\tldr.w\tr1, [r7, #360]\t@ 0x168\n-\tvldr\ts15, [r0, #-4]\n-\tvcvt.f64.f32\td21, s9\n+\tvldr\ts2, [r1, #-4]\n \tvcvt.f64.f32\td5, s10\n-\tvstr\ts13, [r0, #-4]\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tvcvt.f64.f32\td2, s4\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tvadd.f64\td3, d6, d7\n+\tvsub.f64\td7, d6, d7\n+\tvcvt.f64.f32\td1, s2\n+\tadd\tr3, r8\n+\tvadd.f64\td0, d8, d5\n+\tvsub.f64\td8, d8, d5\n+\tvmov.f64\td5, d2\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tvmul.f64\td7, d7, d15\n \tmov\tr3, r0\n-\tvldr\ts14, [r1, #-4]\n-\tvcvt.f64.f32\td27, s15\n-\tvadd.f64\td22, d25, d21\n-\tvsub.f64\td25, d25, d21\n-\tvadd.f64\td19, d26, d5\n-\tvstr\ts12, [r1, #-4]\n-\tvcvt.f64.f32\td23, s14\n-\tvsub.f64\td26, d26, d5\n-\tadd\tr3, r6\n-\tstr.w\tr3, [r7, #356]\t@ 0x164\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tadd\tr1, r6\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvmov.f64\td21, d23\n-\tvadd.f64\td23, d19, d23\n-\tvfms.f64\td21, d19, d20\n-\tvmov.f64\td19, d27\n-\tvfms.f64\td19, d22, d20\n-\tvadd.f64\td22, d22, d27\n-\tadd\tr2, r6\n-\tstr.w\tr1, [r7, #360]\t@ 0x168\n-\tvcvt.f32.f64\ts14, d23\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvcvt.f32.f64\ts15, d22\n-\tvstr\ts14, [r3, #-4]\n-\tadd\tr3, r6\n-\tvmov.f64\td6, d21\n-\tvfma.f64\td21, d16, d25\n-\tvfma.f64\td6, d25, d17\n-\tvmov.f64\td24, d19\n-\tvfma.f64\td24, d16, d26\n-\tvfma.f64\td19, d26, d17\n-\tvstr\ts15, [lr, #-4]\n-\tadd\tlr, r6\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tldr.w\tr3, [r7, #384]\t@ 0x180\n-\tldr.w\tr2, [r7, #376]\t@ 0x178\n-\tvcvt.f32.f64\ts14, d21\n+\tvmov.f64\td4, d1\n+\tadd\tr3, r8\n+\tvmls.f64\td4, d3, d10\n+\tvmls.f64\td5, d0, d10\n+\tvmul.f64\td8, d8, d15\n+\tvadd.f64\td3, d3, d1\n+\tvadd.f64\td0, d0, d2\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tadd\tr2, r8\n+\tstr.w\tr2, [r7, #536]\t@ 0x218\n+\tvcvt.f32.f64\ts6, d3\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvstr\ts23, [r1, #-4]\n+\tadd\tr1, r8\n+\tadd\tr2, r8\n+\tstr.w\tr1, [r7, #512]\t@ 0x200\n+\tvsub.f64\td2, d4, d8\n+\tvadd.f64\td4, d4, d8\n+\tvadd.f64\td6, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tstr.w\tr2, [r7, #616]\t@ 0x268\n+\tvcvt.f32.f64\ts0, d0\n+\tvstr\ts22, [r0, #-4]\n+\tvcvt.f32.f64\ts4, d2\n+\tvstr\ts6, [r3, #-4]\n+\tadd\tr3, r8\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tr3, [r7, #548]\t@ 0x224\n+\tvcvt.f32.f64\ts8, d4\n+\tldr.w\tr2, [r7, #528]\t@ 0x210\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts15, d19\n-\tvcvt.f32.f64\ts13, d24\n-\tvstr\ts12, [r3, #-4]\n-\tadd\tr3, r6\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tvcvt.f32.f64\ts10, d5\n+\tvstr\ts0, [ip, #-4]\n+\tmov\tr1, r2\n+\tadd\tip, r8\n+\tvstr\ts4, [r3, #-4]\n+\tadd\tr3, r8\n+\tstr.w\tr3, [r7, #548]\t@ 0x224\n \tmov\tr3, r2\n-\tadd\tr3, r6\n-\tvstr\ts14, [r2, #-4]\n-\tstr.w\tr3, [r7, #376]\t@ 0x178\n-\tldr.w\tr2, [r7, #412]\t@ 0x19c\n-\tldr.w\tr3, [r7, #316]\t@ 0x13c\n-\tvstr\ts13, [ip, #-4]\n-\tadd\tip, r6\n-\tvstr\ts15, [r5, #-4]\n+\tadd\tr3, r8\n+\tvstr\ts8, [r2, #-4]\n+\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tvstr\ts12, [r6, #-4]\n+\tadd\tr6, r8\n+\tvstr\ts10, [r5, #-4]\n \tcmp\tr2, r3\n-\tadd\tr5, r6\n-\tbne.w\t9988 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x129c>\n-\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n+\tadd\tr5, r8\n+\tbne.w\t9dc8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x12ec>\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tcmp\tfp, r3\n-\tble.n\t9c5e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1572>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tcmp\tsl, r3\n+\tble.n\ta0a2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15c6>\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #404]\t@ 0x194\n-\tldr.w\tr2, [r7, #352]\t@ 0x160\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #404]\t@ 0x194\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n \tcmp\tr3, r2\n-\tbne.w\t9866 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x117a>\n-\tldrd\tr2, r3, [r7, #240]\t@ 0xf0\n-\tldrd\tip, r4, [r7, #232]\t@ 0xe8\n-\tsubs\tr2, #1\n-\tldr.w\tr5, [r7, #276]\t@ 0x114\n-\tadds\tr1, r2, #1\n-\tldrd\tlr, r0, [r7, #256]\t@ 0x100\n-\tadd\tr4, r3\n-\tldr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tbne.w\t9848 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x115c>\n-\tmov\tr9, fp\n-\tmov\tr1, lr\n-\tmov\tsl, r6\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tsubs\tr1, #1\n-\tsub.w\tip, ip, r0\n-\tadds\tr6, r1, #1\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tbne.w\t9810 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1124>\n-\tldr.w\tr8, [r7, #312]\t@ 0x138\n-\tldr.w\tr9, [r7, #368]\t@ 0x170\n-\tldr.w\tfp, [r7, #300]\t@ 0x12c\n-\tldrd\tr6, lr, [r7, #284]\t@ 0x11c\n-\tldr.w\tr4, [r7, #280]\t@ 0x118\n+\tbne.w\t9c9c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11c0>\n+\tldr.w\tr3, [r7, #304]\t@ 0x130\n+\tldr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tsubs\tr3, #1\n+\tldr.w\tr5, [r7, #296]\t@ 0x128\n+\tadd\tr2, r1\n+\tadds\tr1, r3, #1\n+\tbne.w\t9c86 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x11aa>\n+\tldr.w\tr6, [r7, #312]\t@ 0x138\n+\tmov\tr9, sl\n+\tldr.w\tr3, [r7, #408]\t@ 0x198\n+\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tsubs\tr3, #1\n+\tadd\tr6, r2\n+\tstr.w\tr3, [r7, #408]\t@ 0x198\n+\tsubs\tr2, r1, r2\n+\tadds\tr3, #1\n+\tstr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tbne.w\t9c46 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x116a>\n+\tmov\tr4, r5\n+\tldr.w\tsl, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr5, [r7, #336]\t@ 0x150\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tcmp\tr3, r2\n+\tbeq.w\t9968 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe8c>\n+\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tsubs\tr4, r4, r5\n+\tcmp\tr5, #0\n+\tmov.w\tr6, r3, lsl #1\n+\tblt.w\tae24 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2348>\n+\tmov\tr1, r5\n+\tsubs\tr0, r4, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, r4\n+\tstr.w\tr0, [r7, #632]\t@ 0x278\n+\tbgt.w\tae0c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2330>\n \tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tcmp\tr3, r6\n-\tbeq.w\t952c <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe40>\n-\tlsls\tr2, r4, #1\n-\tsub.w\tr3, r5, r8\n-\tcmp.w\tr8, #0\n-\tblt.w\ta98e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22a2>\n-\tsub.w\tr1, r3, r8\n-\tcmp\tr8, r3\n-\tudiv\tr5, r1, r8\n-\tbgt.w\ta348 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c5c>\n-\tadd.w\tsl, fp, fp, lsl #1\n-\trsb\tr3, sl, #0\n-\tstr.w\tr3, [r7, #316]\t@ 0x13c\n-\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n+\tadd.w\tr3, r3, r3, lsl #1\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r7, #368]\t@ 0x170\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n \tcmp\tr3, #1\n-\tmov.w\tr3, r2, lsl #3\n-\tbne.w\ta358 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c6c>\n-\tldr.w\tr1, [r7, #416]\t@ 0x1a0\n-\tlsls\tr2, r2, #4\n-\tstr.w\tr3, [r7, #352]\t@ 0x160\n-\tmov\tip, r8\n-\tstr.w\tr2, [r7, #312]\t@ 0x138\n-\tmov\tr2, r3\n-\tadds\tr3, r1, r3\n-\tsub.w\tr1, lr, r8\n-\tadds\tr2, r3, r2\n-\tmov\tr4, r1\n-\tmov\tr1, r0\n-\tmov\tfp, r2\n-\tstr.w\tr2, [r7, #368]\t@ 0x170\n-\tsub.w\tr2, r9, lr\n-\tstrd\tr6, r2, [r7, #280]\t@ 0x118\n-\tvldr\td24, [r3, #8]\n-\tcmp\tr1, #0\n-\tvldr\td23, [fp, #8]\n-\tvldr\td26, [r3]\n-\tvmul.f64\td24, d18, d24\n-\tvldr\td25, [fp]\n-\tvmul.f64\td23, d18, d23\n-\tblt.w\ta332 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c46>\n-\tudiv\tr6, r4, r1\n-\tcmp\tlr, ip\n-\tblt.w\ta2fa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c0e>\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tmov\tr0, r4\n-\tldr.w\tr2, [r7, #552]\t@ 0x228\n-\tadd\tr3, r4\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n-\tsubs\tr2, #4\n-\tmov\tr3, ip\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n-\tmov\tr2, r6\n-\tstr.w\tr8, [r7, #276]\t@ 0x114\n-\tstrd\tr5, lr, [r7, #256]\t@ 0x100\n+\tbne.w\ta7c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ce6>\n+\tlsls\tr3, r6, #4\n+\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tmov.w\tip, r6, lsl #3\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tmov\tr9, r5\n+\tadd\tr3, ip\n+\tmov\tr6, ip\n+\tsubs\tr1, r2, r5\n+\tstr.w\tr1, [r7, #616]\t@ 0x268\n+\tadd.w\tr1, r3, ip\n+\tstr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tmov\tr8, r1\n+\tldr.w\tr1, [r7, #756]\t@ 0x2f4\n+\tsubs\tr2, r1, r2\n+\tstr.w\tr2, [r7, #360]\t@ 0x168\n+\tvldr\td9, [r3, #8]\n \tcmp.w\tsl, #0\n-\tblt.w\ta31e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c32>\n-\tldr.w\tr4, [r7, #400]\t@ 0x190\n-\tcmp\tr9, r3\n-\tudiv\tr6, r4, sl\n-\tblt.w\ta2da <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1bee>\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n-\tcmp\tr5, #0\n-\tble.w\ta2da <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1bee>\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tadds\tr5, #1\n-\tvmov.f64\td22, #96\t@ 0x3f000000 0.5\n-\tstr.w\tr5, [r7, #300]\t@ 0x12c\n-\tadd\tr4, r3\n-\tstrd\tr1, r9, [r7, #240]\t@ 0xf0\n-\tstrd\tr3, ip, [r7, #232]\t@ 0xe8\n-\tmovs\tr3, #1\n-\tstr.w\tr4, [r7, #516]\t@ 0x204\n-\tstrd\tr3, r2, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tadd.w\tr8, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, r8\n-\tble.n\t9dd2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16e6>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr8, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tip, r3, r8\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, ip\n-\tble.n\t9de8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16fc>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tip, r3\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tadds\tr1, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, r1\n-\tble.n\t9e00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1714>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr1, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tr9, r3, r1\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tvldr\td11, [r8, #8]\n+\tvldr\td8, [r3]\n+\tvmul.f64\td9, d14, d9\n+\tvldr\td10, [r8]\n+\tvmul.f64\td11, d14, d11\n+\tblt.w\ta7a8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ccc>\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tmov\tfp, r0\n \tcmp\tr3, r9\n-\tble.n\t9e16 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x172a>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr9, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tadd\tr3, r9\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tcmp\tr2, r3\n-\tble.n\t9e32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1746>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n+\tblt.w\ta754 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c78>\n+\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tmov\tr4, r9\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvmov.f64\td13, #96\t@ 0x3f000000 0.5\n+\tstr.w\tr8, [r7, #296]\t@ 0x128\n+\tldr.w\tr8, [r7, #720]\t@ 0x2d0\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tadd.w\tlr, r3, r1\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tstr.w\tr9, [r7, #312]\t@ 0x138\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tmov\tr3, r9\n+\tmov\tr9, r6\n+\tstr.w\tr5, [r7, #336]\t@ 0x150\n+\tcmp.w\tr8, #0\n+\tblt.w\ta788 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1cac>\n+\tldr.w\tr0, [r7, #552]\t@ 0x228\n+\tmov\tr1, r8\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr5, r0\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tcmp\tr2, r3\n+\tblt.w\ta72c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c50>\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tcmp\tr2, #0\n+\tble.w\ta72c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c50>\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tadds\tr2, #1\n+\tstr.w\tsl, [r7, #304]\t@ 0x130\n+\tadds\tr0, r1, r3\n+\tstr.w\tr2, [r7, #408]\t@ 0x198\n+\tstr.w\tfp, [r7, #292]\t@ 0x124\n+\tstr.w\tr3, [r7, #280]\t@ 0x118\n+\tmov\tsl, r0\n+\tmov\tfp, r8\n+\tmovs\tr3, #1\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tadd.w\tlr, r3, sl\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tr3, lr\n-\tble.n\t9e48 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x175c>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tlr, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tr5, r3, lr\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, r5\n-\tble.n\t9e5e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1772>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr5, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tlr, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd.w\tr6, r3, lr\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, r6\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr6, r6, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tadd.w\tr1, r3, sl\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, r1\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr1, r1, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd.w\tr8, r3, r1\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, r8\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr8, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd\tr3, r8\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n \tcmp\tr2, r3\n-\tble.n\t9e7a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x178e>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tittt\tgt\n+\tldrgt.w\tr2, [r7, #768]\t@ 0x300\n+\taddgt\tr3, r3, r2\n+\tstrgt.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tadd.w\tip, r3, r1\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, ip\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tip, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd.w\tr4, r3, ip\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, r4\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr4, r4, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tadd\tr3, r4\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tcmp\tr2, r3\n+\tittt\tgt\n+\tldrgt.w\tr2, [r7, #768]\t@ 0x300\n+\taddgt\tr3, r3, r2\n+\tstrgt.w\tr3, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n \tcmp\tr3, #0\n-\tble.w\ta290 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ba4>\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tadd.w\tip, ip, #1073741824\t@ 0x40000000\n-\tadd.w\tr5, r5, #1073741824\t@ 0x40000000\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tble.w\ta6ec <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c10>\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tsubs\tr3, #1\n-\tsubs\tr5, #1\n+\tadd.w\tr6, r6, #1073741824\t@ 0x40000000\n \tsubs\tr1, #1\n-\tadd.w\tr9, r9, #1073741824\t@ 0x40000000\n+\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n+\tsubs\tr6, #1\n+\tsubs\tr3, #1\n+\tlsls\tr1, r1, #2\n+\tstr.w\tr1, [r7, #576]\t@ 0x240\n+\tlsls\tr6, r6, #2\n \tlsls\tr3, r3, #2\n-\tstr.w\tr3, [r7, #404]\t@ 0x194\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tmov.w\tr2, ip, lsl #2\n-\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n-\tlsls\tr5, r5, #2\n-\tadd.w\tip, r8, #1073741824\t@ 0x40000000\n-\tstr.w\tr5, [r7, #364]\t@ 0x16c\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tadd.w\tr2, r8, #1073741824\t@ 0x40000000\n+\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tadd.w\tr4, r4, #1073741824\t@ 0x40000000\n+\tstr.w\tr6, [r7, #584]\t@ 0x248\n+\tadd.w\tr6, lr, #1073741824\t@ 0x40000000\n \tlsls\tr3, r3, #2\n-\tstr.w\tr3, [r7, #356]\t@ 0x164\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tmov.w\tr3, ip, lsl #2\n+\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tsubs\tr6, #1\n+\tsubs\tr4, #1\n+\tsubs\tr2, #1\n+\tadd.w\tip, r3, lr\n+\tlsls\tr6, r6, #2\n \tmov.w\tr3, lr, lsl #2\n-\tstr.w\tr3, [r7, #376]\t@ 0x178\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tlsls\tr1, r1, #2\n-\tadd.w\tip, ip, #4294967295\t@ 0xffffffff\n-\tstr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tadd.w\tr5, r3, #1073741824\t@ 0x40000000\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr1, [r7, #288]\t@ 0x120\n-\tmov.w\tip, ip, lsl #2\n-\tadd.w\tlr, r3, r8\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tmov.w\tr2, r9, lsl #2\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n-\tmov.w\tr3, r8, lsl #2\n-\tsubs\tr5, #1\n-\tadd.w\tr1, r1, lr, lsl #2\n-\tnegs\tr3, r3\n-\tadd.w\tr8, r2, ip\n-\tstr.w\tr1, [r7, #344]\t@ 0x158\n-\tlsls\tr5, r5, #2\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n-\tldr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tstr.w\tr3, [r7, #360]\t@ 0x168\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tadd.w\tr9, r3, r1\n-\tadds\tr1, r2, r1\n+\tlsls\tr2, r2, #2\n+\tadd.w\tr1, r1, ip, lsl #2\n \tstr.w\tr1, [r7, #428]\t@ 0x1ac\n-\tadds\tr1, r3, r5\n-\tstr.w\tr1, [r7, #396]\t@ 0x18c\n-\tadd.w\tlr, r3, ip\n-\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tadd.w\tip, r5, r2\n-\tmov\tr5, r2\n+\tldr.w\tr1, [r7, #748]\t@ 0x2ec\n+\tnegs\tr3, r3\n+\tstr.w\tr2, [r7, #568]\t@ 0x238\n+\tlsls\tr2, r4, #2\n+\tadd.w\tr8, r1, r6\n+\tadd.w\tr4, sl, #1073741824\t@ 0x40000000\n+\tldr.w\tr1, [r7, #584]\t@ 0x248\n+\tsubs\tr4, #1\n+\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tlsls\tr4, r4, #2\n+\tstr.w\tr0, [r7, #276]\t@ 0x114\n+\tadd.w\tlr, r3, r6\n+\tadds\tr6, r3, r1\n+\tstr.w\tr6, [r7, #608]\t@ 0x260\n+\tadd.w\tip, r3, r2\n+\tldr.w\tr6, [r7, #748]\t@ 0x2ec\n+\tadds\tr1, r6, r1\n+\tstr.w\tr1, [r7, #584]\t@ 0x248\n+\tadds\tr1, r3, r4\n+\tstr.w\tr1, [r7, #548]\t@ 0x224\n+\tmov\tr1, r6\n+\tadd\tr1, r4\n+\tstr.w\tr1, [r7, #528]\t@ 0x210\n+\tldr.w\tr1, [r7, #576]\t@ 0x240\n+\tmov\tr4, r6\n \tadds\tr1, r3, r1\n-\tstr.w\tr1, [r7, #392]\t@ 0x188\n-\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tadd\tr1, r2\n-\tldr.w\tr2, [r7, #412]\t@ 0x19c\n-\tstr.w\tr1, [r7, #388]\t@ 0x184\n-\tadds\tr1, r3, r2\n-\tadds\tr2, r5, r2\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tstr.w\tr1, [r7, #384]\t@ 0x180\n-\tmov\tr1, r5\n-\tadds\tr5, r3, r2\n-\tadds\tr2, r1, r2\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n-\tstr.w\tr5, [r7, #424]\t@ 0x1a8\n-\tmov\tr5, ip\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tadds\tr3, r1, r2\n-\tstr.w\tr3, [r7, #404]\t@ 0x194\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tvldr\ts10, [r8]\n-\tldr.w\tr1, [r7, #396]\t@ 0x18c\n-\tvldr\ts11, [lr]\n-\tvldr\ts15, [r3]\n-\tvcvt.f64.f32\td30, s10\n-\tvldr\ts12, [r9]\n-\tvldr\ts9, [r5]\n-\tvcvt.f64.f32\td27, s11\n-\tvcvt.f64.f32\td28, s15\n-\tvldr\ts14, [r1]\n+\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tmov\tr1, r6\n+\tldr.w\tr6, [r7, #576]\t@ 0x240\n+\tadd\tr1, r6\n+\tldr.w\tr6, [r7, #568]\t@ 0x238\n+\tstr.w\tr1, [r7, #516]\t@ 0x204\n+\tadds\tr1, r3, r6\n+\tadds\tr6, r4, r6\n+\tstr.w\tr1, [r7, #576]\t@ 0x240\n+\tmov\tr1, r4\n+\tldr.w\tr4, [r7, #560]\t@ 0x230\n+\tstr.w\tr6, [r7, #512]\t@ 0x200\n+\tadds\tr6, r3, r4\n+\tstr.w\tr6, [r7, #568]\t@ 0x238\n+\tadds\tr6, r1, r2\n+\tadds\tr4, r1, r4\n+\tstr.w\tr4, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tvldr\ts4, [r8]\n+\tvldr\ts6, [r3]\n+\tvldr\ts10, [r2]\n+\tvldr\ts8, [lr]\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts12, [r1]\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr4, [r7, #528]\t@ 0x210\n+\tvcvt.f64.f32\td4, s8\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n \tvcvt.f64.f32\td6, s12\n-\tldr.w\tr2, [r7, #392]\t@ 0x188\n-\tvcvt.f64.f32\td20, s9\n-\tldr.w\tr3, [r7, #388]\t@ 0x184\n-\tvcvt.f64.f32\td19, s14\n-\tvadd.f64\td7, d28, d30\n-\tvsub.f64\td30, d30, d28\n-\tvadd.f64\td5, d6, d27\n-\tvsub.f64\td27, d27, d6\n-\tvmov.f64\td6, d20\n-\tvldr\ts9, [r2]\n-\tvmov.f64\td28, d19\n-\tvldr\ts8, [r3]\n-\tvfms.f64\td6, d7, d22\n-\tvadd.f64\td31, d20, d7\n-\tvfms.f64\td28, d5, d22\n-\tvfnms.f64\td20, d7, d22\n-\tvadd.f64\td19, d19, d5\n-\tvcvt.f64.f32\td21, s8\n-\tvcvt.f64.f32\td29, s9\n-\tvcvt.f32.f64\ts10, d31\n-\tvfma.f64\td20, d16, d27\n-\tvcvt.f32.f64\ts11, d19\n-\tvmov.f64\td7, d6\n-\tvmov.f64\td19, d6\n-\tvfma.f64\td7, d16, d27\n-\tvmov.f64\td31, d28\n-\tvfma.f64\td31, d30, d17\n-\tvfma.f64\td28, d16, d30\n-\tvfma.f64\td19, d27, d17\n-\tvstmia\tr1!, {s11}\n-\tstr.w\tr1, [r7, #396]\t@ 0x18c\n+\tvadd.f64\td1, d3, d2\n+\tvsub.f64\td2, d2, d3\n+\tvldr\ts14, [r4]\n+\tvadd.f64\td3, d5, d4\n+\tvsub.f64\td12, d4, d5\n+\tvmov.f64\td4, d6\n+\tvldr\ts1, [r3]\n+\tvcvt.f64.f32\td7, s14\n+\tvmul.f64\td5, d2, d15\n+\tvmul.f64\td2, d1, d13\n+\tvmls.f64\td4, d3, d13\n+\tvadd.f64\td6, d6, d3\n+\tvmul.f64\td3, d12, d15\n+\tvcvt.f64.f32\td0, s1\n+\tvadd.f64\td12, d7, d1\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts24, d12\n+\tvsub.f64\td1, d4, d5\n+\tvadd.f64\td5, d5, d4\n+\tvstmia\tr1!, {s12}\n+\tvsub.f64\td4, d7, d2\n+\tstr.w\tr1, [r7, #548]\t@ 0x224\n+\tvsub.f64\td7, d2, d7\n+\tldr.w\tr1, [r7, #516]\t@ 0x204\n+\tvmul.f64\td2, d5, d10\n+\tvldr\ts12, [r1]\n+\tvstmia\tr4!, {s24}\n+\tvmul.f64\td12, d5, d11\n+\tvadd.f64\td5, d7, d3\n+\tvmov.f64\td7, d2\n+\tstr.w\tr4, [r7, #528]\t@ 0x210\n+\tvcvt.f64.f32\td6, s12\n+\tldr.w\tr4, [r7, #568]\t@ 0x238\n+\tvmla.f64\td7, d5, d11\n+\tvadd.f64\td5, d4, d3\n+\tvsub.f64\td4, d4, d3\n+\tvmul.f64\td3, d5, d9\n+\tvmla.f64\td12, d4, d10\n+\tvmul.f64\td4, d1, d9\n+\tvmla.f64\td4, d5, d8\n+\tvmov.f64\td5, d3\n+\tvcvt.f32.f64\ts14, d7\n+\tvnmls.f64\td5, d1, d8\n+\tvcvt.f32.f64\ts15, d12\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tr1!, {s8}\n+\tstr.w\tr1, [r7, #516]\t@ 0x204\n \tmov\tr1, r3\n-\tvstmia\tr5!, {s10}\n-\tvmul.f64\td20, d20, d23\n-\tldr.w\tr3, [r7, #384]\t@ 0x180\n-\tvmul.f64\td30, d7, d26\n-\tvnmul.f64\td27, d24, d7\n-\tvfma.f64\td30, d31, d24\n-\tvfma.f64\td27, d31, d26\n-\tvmul.f64\td19, d19, d25\n-\tvfma.f64\td20, d28, d25\n-\tvfma.f64\td19, d28, d23\n-\tvcvt.f32.f64\ts14, d30\n-\tvcvt.f32.f64\ts15, d27\n-\tvcvt.f32.f64\ts9, d20\n-\tvmov.f64\td20, d21\n-\tvcvt.f32.f64\ts8, d19\n-\tvstmia\tr1!, {s14}\n-\tstr.w\tr1, [r7, #388]\t@ 0x184\n-\tldr.w\tr1, [r7, #412]\t@ 0x19c\n-\tvstmia\tr2!, {s15}\n-\tstr.w\tr2, [r7, #392]\t@ 0x188\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n+\tvcvt.f32.f64\ts10, d5\n+\tvstmia\tr1!, {s10}\n+\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tldr.w\tr1, [r7, #576]\t@ 0x240\n+\tvldr\ts4, [r4]\n+\tldr.w\tr4, [r7, #560]\t@ 0x230\n+\tvldr\ts24, [ip]\n+\tvldr\ts2, [r1]\n+\tvcvt.f64.f32\td2, s4\n+\tldr.w\tr1, [r7, #512]\t@ 0x200\n+\tvldr\ts6, [r4]\n+\tvcvt.f64.f32\td12, s24\n+\tvcvt.f64.f32\td1, s2\n \tvldr\ts10, [r1]\n-\tldr.w\tr1, [r7, #380]\t@ 0x17c\n-\tvldr\ts13, [r3]\n-\tvldr\ts7, [r2]\n+\tvcvt.f64.f32\td3, s6\n+\tvadd.f64\td4, d2, d1\n+\tvsub.f64\td1, d1, d2\n+\tvmov.f64\td2, d0\n \tvcvt.f64.f32\td5, s10\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tvldr\ts14, [r1]\n-\tvcvt.f64.f32\td27, s13\n-\tvcvt.f64.f32\td19, s7\n-\tvldr\ts12, [r2]\n-\tvcvt.f64.f32\td7, s14\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvcvt.f64.f32\td30, s12\n-\tvadd.f64\td31, d5, d7\n-\tvsub.f64\td7, d7, d5\n-\tvldr\ts13, [r2]\n-\tvmov.f64\td5, d29\n-\tmov\tr2, r1\n-\tvcvt.f64.f32\td28, s13\n-\tvadd.f64\td6, d19, d27\n-\tvsub.f64\td27, d27, d19\n-\tvmov.f64\td19, d21\n-\tvfms.f64\td19, d31, d22\n-\tvfnms.f64\td20, d31, d22\n-\tvadd.f64\td31, d31, d21\n-\tvfms.f64\td5, d6, d22\n-\tvadd.f64\td6, d6, d29\n-\tvfma.f64\td20, d16, d27\n-\tvcvt.f32.f64\ts7, d31\n-\tvcvt.f32.f64\ts12, d6\n-\tvmov.f64\td21, d19\n-\tvfma.f64\td19, d27, d17\n-\tvfma.f64\td21, d16, d27\n-\tvstmia\tr8!, {s7}\n-\tvmov.f64\td27, d5\n-\tvfma.f64\td5, d16, d7\n-\tvfma.f64\td27, d7, d17\n-\tvstmia\tlr!, {s12}\n-\tvmul.f64\td20, d20, d23\n-\tldr.w\tr1, [r7, #360]\t@ 0x168\n-\tadd.w\tip, r8, r1\n-\tvmul.f64\td19, d19, d25\n-\tvmul.f64\td29, d21, d26\n-\tvnmul.f64\td21, d24, d21\n-\tvfma.f64\td19, d5, d23\n-\tvfma.f64\td20, d5, d25\n-\tvfma.f64\td29, d27, d24\n-\tvfma.f64\td21, d27, d26\n-\tvcvt.f32.f64\ts13, d19\n-\tvcvt.f32.f64\ts15, d20\n-\tvcvt.f32.f64\ts12, d29\n-\tvcvt.f32.f64\ts14, d21\n-\tvstmia\tr2!, {s12}\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tvstmia\tr2!, {s13}\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tmov\tr2, r3\n-\tldr.w\tr3, [r7, #376]\t@ 0x178\n+\tvmls.f64\td2, d4, d13\n+\tvadd.f64\td4, d4, d0\n+\tvmul.f64\td1, d1, d15\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tlr!, {s8}\n+\tvldr\ts9, [r6]\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n+\tvcvt.f64.f32\td0, s9\n+\tvadd.f64\td4, d3, d5\n+\tvsub.f64\td5, d5, d3\n+\tadd.w\tr2, lr, r3\n+\tadds\tr4, r2, r4\n+\tldr.w\tr0, [r7, #504]\t@ 0x1f8\n+\tvmul.f64\td3, d4, d13\n+\tvadd.f64\td4, d4, d6\n+\tvmul.f64\td5, d5, d15\n+\tadd\tr2, r0\n+\tldr.w\tr0, [r7, #508]\t@ 0x1fc\n+\tvcvt.f32.f64\ts8, d4\n+\tvstmia\tr8!, {s8}\n+\tvsub.f64\td4, d2, d5\n+\tvadd.f64\td5, d5, d2\n+\tvsub.f64\td2, d3, d6\n+\tvsub.f64\td3, d6, d3\n+\tadd\tr3, r8\n+\tadds\tr0, r3, r0\n+\tstr.w\tr0, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr0, [r7, #504]\t@ 0x1f8\n+\tvadd.f64\td2, d2, d1\n+\tvadd.f64\td6, d3, d1\n+\tvsub.f64\td3, d3, d1\n+\tvmul.f64\td1, d5, d11\n+\tvmul.f64\td5, d5, d10\n+\tadd\tr3, r0\n+\tvmla.f64\td5, d2, d11\n+\tvmov.f64\td2, d1\n+\tvmul.f64\td1, d4, d9\n+\tvmla.f64\td1, d6, d8\n+\tvmla.f64\td2, d3, d10\n+\tvmul.f64\td3, d6, d9\n+\tvnmls.f64\td3, d4, d8\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f32.f64\ts4, d2\n+\tvstmia\tr1!, {s2}\n+\tvcvt.f32.f64\ts6, d3\n+\tstr.w\tr1, [r7, #512]\t@ 0x200\n+\tldr.w\tr1, [r7, #576]\t@ 0x240\n+\tvstmia\tr6!, {s4}\n+\tvldr\ts12, [r3, #-4]\n+\tvstmia\tr1!, {s6}\n+\tvstmia\tip!, {s10}\n+\tvcvt.f64.f32\td6, s12\n+\tvldr\ts6, [r4, #-4]\n+\tvldr\ts8, [r2, #-4]\n+\tstr.w\tr1, [r7, #576]\t@ 0x240\n+\tvcvt.f64.f32\td3, s6\n+\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tvcvt.f64.f32\td4, s8\n+\tvstr\ts14, [r2, #-4]\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tvldr\ts10, [r1, #-4]\n+\tvstr\ts15, [r3, #-4]\n+\tvadd.f64\td7, d3, d12\n+\tvsub.f64\td12, d12, d3\n+\tvmov.f64\td3, d4\n+\tvcvt.f64.f32\td5, s10\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tvmls.f64\td3, d7, d13\n+\tvadd.f64\td7, d4, d7\n+\tvmul.f64\td4, d12, d15\n+\tvadd.f64\td1, d5, d0\n+\tvcvt.f32.f64\ts14, d7\n \tvstmia\tr2!, {s14}\n-\tstr.w\tr2, [r7, #384]\t@ 0x180\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvstmia\tr2!, {s15}\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tadd.w\tr2, lr, r1\n-\tstr.w\tr2, [r7, #364]\t@ 0x16c\n-\tldr.w\tr2, [r7, #356]\t@ 0x164\n-\tadd.w\tr1, ip, r2\n-\tadd\tip, r3\n+\tvsub.f64\td7, d0, d5\n+\tvmul.f64\td5, d1, d13\n+\tvadd.f64\td1, d6, d1\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tvmul.f64\td7, d7, d15\n+\tvsub.f64\td0, d6, d5\n+\tvcvt.f32.f64\ts2, d1\n+\tvsub.f64\td5, d5, d6\n+\tvsub.f64\td6, d3, d7\n+\tvadd.f64\td7, d7, d3\n+\tvadd.f64\td3, d0, d4\n+\tvstmia\tr3!, {s2}\n+\tvadd.f64\td5, d5, d4\n+\tvsub.f64\td0, d0, d4\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tvmul.f64\td4, d7, d10\n+\tvmul.f64\td2, d6, d9\n+\tvmul.f64\td1, d3, d9\n+\tvmul.f64\td7, d7, d11\n+\tvmla.f64\td4, d5, d11\n+\tvmla.f64\td2, d3, d8\n+\tvmla.f64\td7, d0, d10\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tvmov.f64\td5, d1\n+\tvnmls.f64\td5, d6, d8\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts10, d5\n+\tvstmia\tr3!, {s10}\n+\tvstr\ts8, [r4, #-4]\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tr4, [r7, #560]\t@ 0x230\n \tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tvldr\ts14, [r1, #-4]\n-\tvldr\ts15, [ip, #-4]\n-\tvstr\ts8, [ip, #-4]\n-\tvcvt.f64.f32\td20, s14\n-\tvcvt.f64.f32\td19, s15\n-\tvadd.f64\td27, d20, d30\n-\tvsub.f64\td30, d30, d20\n-\tvmov.f64\td21, d19\n-\tvmov.f64\td20, d19\n-\tvadd.f64\td19, d19, d27\n-\tvfms.f64\td20, d27, d22\n-\tvfnms.f64\td21, d27, d22\n-\tvcvt.f32.f64\ts15, d19\n-\tvstmia\tr3!, {s15}\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tmov\tr3, r2\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n-\tadd.w\tip, r2, r3\n-\tldr.w\tr3, [r7, #376]\t@ 0x178\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tvldr\ts15, [ip, #-4]\n-\tvldr\ts14, [r2, #-4]\n-\tvcvt.f64.f32\td19, s15\n-\tvstr\ts9, [r2, #-4]\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvcvt.f64.f32\td27, s14\n-\tvadd.f64\td29, d19, d28\n-\tvsub.f64\td28, d28, d19\n-\tvmov.f64\td19, d20\n-\tvmov.f64\td31, d27\n-\tvfms.f64\td31, d29, d22\n-\tvadd.f64\td27, d27, d29\n-\tvfma.f64\td19, d16, d28\n-\tvfma.f64\td21, d16, d28\n-\tvfma.f64\td20, d28, d17\n-\tvcvt.f32.f64\ts15, d27\n-\tvmov.f64\td29, d31\n-\tvfma.f64\td31, d16, d30\n-\tvfma.f64\td29, d30, d17\n-\tvnmul.f64\td27, d24, d19\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td19, d19, d26\n-\tvmul.f64\td20, d20, d25\n-\tvstmia\tr9!, {s15}\n-\tvfma.f64\td21, d31, d25\n-\tvfma.f64\td20, d31, d23\n-\tvfma.f64\td27, d29, d26\n-\tvfma.f64\td19, d29, d24\n-\tvcvt.f32.f64\ts13, d21\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts12, d27\n-\tvcvt.f32.f64\ts15, d19\n-\tvstmia\tr2!, {s12}\n-\tvstmia\tr3!, {s15}\n-\tstr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvstr\ts13, [ip, #-4]\n-\tstr.w\tr3, [r7, #412]\t@ 0x19c\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n-\tvstr\ts14, [r1, #-4]\n \tcmp\tlr, r3\n-\tbne.w\t9f8a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x189e>\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tcmp\tr2, r3\n-\tble.n\ta2b0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1bc4>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tvstmia\tr4!, {s4}\n+\tvstr\ts14, [r1, #-4]\n+\tstr.w\tr4, [r7, #560]\t@ 0x230\n+\tbne.w\ta3e6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x190a>\n+\tldr.w\tr0, [r7, #276]\t@ 0x114\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr2, [r7, #408]\t@ 0x198\n+\tadd\tsl, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, sl\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tsl, r3\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #440]\t@ 0x1b8\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n \tcmp\tr3, r2\n-\tbne.w\t9db8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16cc>\n-\tsubs\tr6, #1\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tadd\tr4, sl\n-\tadds\tr5, r6, #1\n-\tbne.w\t9dae <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16c2>\n-\tldrd\tr1, r9, [r7, #240]\t@ 0xf0\n-\tldrd\tr3, ip, [r7, #232]\t@ 0xe8\n-\tsubs\tr2, #1\n-\tldr.w\tr4, [r7, #400]\t@ 0x190\n-\tadd\tr3, r1\n-\tadds\tr6, r2, #1\n-\tsub.w\tr4, r4, r1\n-\tstr.w\tr4, [r7, #400]\t@ 0x190\n-\tbne.w\t9d76 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x168a>\n-\tldr.w\tr8, [r7, #276]\t@ 0x114\n-\tmov\tr4, r0\n-\tldrd\tr5, lr, [r7, #256]\t@ 0x100\n+\tbne.w\ta22e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1752>\n \tsubs\tr5, #1\n-\tldr.w\tr3, [r7, #312]\t@ 0x138\n-\tadd\tip, r8\n-\tldr.w\tr2, [r7, #368]\t@ 0x170\n-\tsub.w\tr4, r4, r8\n-\tadd\tfp, r3\n-\tadds\tr0, r5, #1\n-\tmov\tr3, r2\n-\tbeq.n\ta344 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c58>\n-\tldr.w\tr0, [r7, #352]\t@ 0x160\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r7, #368]\t@ 0x170\n-\tb.n\t9d2c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1640>\n-\tldr.w\tr5, [r7, #316]\t@ 0x13c\n-\tsub.w\tr4, r3, r9\n-\tcmp\tr9, r3\n-\tudiv\tr6, r4, r5\n-\tble.w\t9d8c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16a0>\n-\tb.n\ta2da <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1bee>\n-\tsub.w\tr3, ip, lr\n-\tnegs\tr2, r1\n-\tcmp\tlr, ip\n-\tudiv\tr6, r3, r2\n-\tble.w\t9d54 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1668>\n-\tb.n\ta2fa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c0e>\n-\tldr.w\tr6, [r7, #280]\t@ 0x118\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tadds\tr6, #1\n-\tcmp\tr3, r6\n-\tbge.w\t9016 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x92a>\n-\tb.w\t952c <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe40>\n-\tldr.w\tr1, [r7, #416]\t@ 0x1a0\n-\tlsls\tr2, r2, #4\n-\tstr.w\tr3, [r7, #288]\t@ 0x120\n-\tsub.w\tip, lr, r8\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tmov\tr2, r3\n-\tadds\tr3, r1, r3\n-\tmov\tr1, r8\n-\tadds\tr2, r3, r2\n-\tstr.w\tr2, [r7, #312]\t@ 0x138\n-\tmov\tfp, r2\n-\tsub.w\tr2, r9, lr\n-\tstr.w\tr2, [r7, #280]\t@ 0x118\n-\tldr.w\tr2, [r7, #536]\t@ 0x218\n-\tstr.w\tsl, [r7, #388]\t@ 0x184\n-\tadds\tr2, #1\n-\tstr.w\tlr, [r7, #300]\t@ 0x12c\n-\tstr.w\tr2, [r7, #276]\t@ 0x114\n-\tstr.w\tr6, [r7, #260]\t@ 0x104\n-\tstr.w\tfp, [r7, #360]\t@ 0x168\n-\tvldr\td23, [r3, #8]\n-\tcmp\tr0, #0\n-\tvldr\td25, [r3]\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n-\tvmul.f64\td23, d18, d23\n-\tvldr\td24, [r3, #8]\n-\tvldr\td26, [r3]\n-\tvmul.f64\td24, d18, d24\n-\tblt.w\ta97a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x228e>\n-\tudiv\tr6, ip, r0\n-\tldr.w\tr3, [r7, #300]\t@ 0x12c\n-\tcmp\tr3, r1\n-\tblt.w\ta932 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2246>\n+\tmov\tr8, fp\n+\tadd\tr0, fp\n+\tadds\tr3, r5, #1\n+\tbne.w\ta224 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1748>\n+\tldr.w\tsl, [r7, #304]\t@ 0x130\n+\tldr.w\tfp, [r7, #292]\t@ 0x124\n \tldr.w\tr3, [r7, #280]\t@ 0x118\n-\tmov\tr4, r0\n-\tmov\tr0, r6\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tadd\tr3, ip\n-\tstr.w\tr3, [r7, #364]\t@ 0x16c\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n+\tadd\tr3, sl\n+\tcmp.w\tfp, #4294967295\t@ 0xffffffff\n+\tsub.w\tr2, r2, sl\n+\tstr.w\tr2, [r7, #552]\t@ 0x228\n+\tbne.w\ta1dc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1700>\n+\tmov\tr6, r9\n+\tldr.w\tr5, [r7, #336]\t@ 0x150\n+\tldr.w\tr9, [r7, #312]\t@ 0x138\n+\tldr.w\tr8, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tadd\tr9, r5\n+\tldr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tsubs\tr2, r3, #1\n+\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tstr.w\tr2, [r7, #632]\t@ 0x278\n+\tadds\tr2, #1\n+\tadd\tr8, r3\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tsub.w\tr3, r3, r5\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n \tmov\tr3, r1\n-\tstr.w\tr8, [r7, #256]\t@ 0x100\n-\tstr.w\tr9, [r7, #356]\t@ 0x164\n-\tstrd\tr1, r5, [r7, #240]\t@ 0xf0\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n+\tbeq.w\tae0c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2330>\n+\tmov\tr2, r1\n+\tadd\tr2, r6\n+\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tb.n\ta17e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16a2>\n+\tldr.w\tr4, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #368]\t@ 0x170\n+\tsubs\tr0, r3, r4\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tmov\tr5, r0\n+\tcmp\tr4, r3\n+\tble.w\ta202 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1726>\n+\tb.n\ta72c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c50>\n+\tldr.w\tr4, [r7, #688]\t@ 0x2b0\n+\trsb\tr1, sl, #0\n+\tsub.w\tr0, r9, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r9\n+\tmov\tfp, r0\n+\tble.w\ta1b4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x16d8>\n+\tb.n\ta754 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c78>\n+\tlsls\tr3, r6, #4\n+\tstr.w\tr3, [r7, #312]\t@ 0x138\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tlsls\tr2, r6, #3\n+\tldr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tmov\tr6, r5\n+\tadds\tr1, r3, r2\n+\tvmov.f64\td13, #96\t@ 0x3f000000 0.5\n+\tadds\tr3, r1, r2\n+\tstr.w\tr3, [r7, #360]\t@ 0x168\n+\tmov\tfp, r3\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tsubs\tr4, r0, r5\n+\tstr.w\tr4, [r7, #548]\t@ 0x224\n+\tsubs\tr3, r3, r0\n+\tstr.w\tr3, [r7, #304]\t@ 0x130\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tmov\tr4, r2\n+\tmov\tr2, fp\n+\tstr.w\tr5, [r7, #336]\t@ 0x150\n+\tadds\tr3, #1\n+\tstr.w\tsl, [r7, #496]\t@ 0x1f0\n+\tstr.w\tr3, [r7, #292]\t@ 0x124\n+\tvldr\td10, [r1, #8]\n+\tvldr\td8, [r2, #8]\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tvmul.f64\td10, d14, d10\n+\tvldr\td11, [r1]\n+\tvmul.f64\td8, d14, d8\n+\tvldr\td9, [r2]\n+\tcmp\tr3, #0\n+\tblt.w\tadea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x230e>\n+\tmov\tr1, r3\n+\tldr.w\tr0, [r7, #548]\t@ 0x224\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tmov\tr9, r0\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tcmp\tr3, r6\n+\tblt.w\tad9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22c2>\n+\tldr.w\tr3, [r7, #304]\t@ 0x130\n+\tmov\tr5, r6\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tstrd\tr2, r6, [r7, #276]\t@ 0x114\n+\tadd\tr3, r1\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #296]\t@ 0x128\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tcmp\tr3, #0\n+\tblt.w\tadd2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22f6>\n+\tmov\tr1, r3\n+\tldr.w\tr0, [r7, #500]\t@ 0x1f4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tmov\tr3, r0\n+\tcmp\tr2, r5\n+\tblt.w\tad7c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22a0>\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n \tcmp\tr2, #0\n-\tblt.w\ta95e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2272>\n-\tmov\tr1, r2\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n-\tudiv\tr2, r2, r1\n-\tldr.w\tr1, [r7, #356]\t@ 0x164\n-\tcmp\tr1, r3\n-\tblt.w\ta910 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2224>\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n-\tcmp\tr5, #0\n-\tble.w\ta910 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2224>\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tadds\tr5, #1\n-\tldr.w\tr8, [r7, #524]\t@ 0x20c\n-\tldr.w\tfp, [r7, #552]\t@ 0x228\n-\tadd\tr1, r3\n-\tldr.w\tr9, [r7, #372]\t@ 0x174\n-\tstr.w\tr5, [r7, #236]\t@ 0xec\n-\tstrd\tr0, r4, [r7, #228]\t@ 0xe4\n-\tstrd\tip, r3, [r7, #220]\t@ 0xdc\n-\tmov\tsl, r1\n-\tmovs\tr3, #1\n-\tstr.w\tr2, [r7, #344]\t@ 0x158\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n-\tstr.w\tr1, [r7, #352]\t@ 0x160\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd.w\tr4, r3, sl\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tble.w\tad7c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22a0>\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tldrd\tr8, sl, [r7, #748]\t@ 0x2ec\n+\tadd\tr2, r5\n+\tldr.w\tfp, [r7, #520]\t@ 0x208\n+\tstrd\tr5, r9, [r7, #268]\t@ 0x10c\n+\tstr.w\tr4, [r7, #256]\t@ 0x100\n+\tmov\tr9, r2\n+\tmovs\tr1, #1\n+\tstrd\tr2, r3, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tadd.w\tr4, r3, r9\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr5, [r7, #788]\t@ 0x314\n \tcmp\tr3, r4\n-\tble.n\ta458 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d6c>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tr6, [r7, #788]\t@ 0x314\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr4, r4, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tadd.w\tip, r3, r4\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tr3, ip\n-\tble.n\ta46e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d82>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tip, r3\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tadd.w\tr2, r3, sl\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tip, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tadd.w\tr2, r3, r9\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tr3, r2\n-\tble.n\ta484 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d98>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tadds\tr0, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tr3, r0\n-\tble.n\ta498 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dac>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr0, r3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr0, r0, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tadd.w\tlr, r3, r0\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tr3, lr\n-\tble.n\ta4ae <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dc2>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tlr, r3\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tlr, r3\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tadd\tr3, r2\n \tcmp\tr1, r3\n-\tble.n\ta4c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dd6>\n-\tldr.w\tr1, [r7, #556]\t@ 0x22c\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n-\tldr.w\tr5, [r7, #560]\t@ 0x230\n+\titt\tgt\n+\tldrgt.w\tr1, [r7, #768]\t@ 0x300\n+\taddgt\tr3, r3, r1\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n \tadd\tr1, r3\n \tcmp\tr5, r1\n-\tble.n\ta4d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dea>\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tadd\tr1, r5\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tldr.w\tr6, [r7, #560]\t@ 0x230\n+\titt\tgt\n+\tldrgt.w\tr5, [r7, #768]\t@ 0x300\n+\taddgt\tr1, r1, r5\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n \tadd\tr5, r1\n \tcmp\tr6, r5\n-\tble.n\ta4ea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dfe>\n-\tldr.w\tr6, [r7, #556]\t@ 0x22c\n-\tadd\tr5, r6\n-\tldr.w\tr6, [r7, #536]\t@ 0x218\n+\titt\tgt\n+\tldrgt.w\tr6, [r7, #768]\t@ 0x300\n+\taddgt\tr5, r5, r6\n+\tldr.w\tr6, [r7, #784]\t@ 0x310\n \tcmp\tr6, #0\n-\tble.w\ta8ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x21de>\n+\tble.w\tad3a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x225e>\n+\tlsls\tr2, r2, #2\n \tmov.w\tr6, lr, lsl #2\n \tlsls\tr4, r4, #2\n-\tmov.w\tlr, sl, lsl #2\n+\tmov.w\tlr, r9, lsl #2\n \tmov.w\tip, ip, lsl #2\n-\tlsls\tr2, r2, #2\n-\tlsls\tr0, r0, #2\n \tlsls\tr1, r1, #2\n \tlsls\tr5, r5, #2\n \tlsls\tr3, r3, #2\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tadd.w\tr3, sl, r4\n+\tstr.w\tr3, [r7, #576]\t@ 0x240\n+\tadd.w\tr3, sl, ip\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tadd.w\tr3, sl, lr\n+\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tadd.w\tr3, sl, r2\n \tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tadd.w\tr3, fp, r4\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tadd.w\tr3, fp, ip\n-\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tadd.w\tr3, fp, lr\n-\tstr.w\tr3, [r7, #380]\t@ 0x17c\n-\tadd.w\tr3, fp, r2\n-\tstr.w\tr3, [r7, #412]\t@ 0x19c\n-\tadd.w\tr3, fp, r0\n-\tstr.w\tr3, [r7, #404]\t@ 0x194\n-\tadd.w\tr3, fp, r6\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n-\tadd.w\tr3, fp, r1\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n-\tadd.w\tr3, fp, r5\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tadd.w\tr3, r8, r2\n+\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tadd.w\tr3, sl, r6\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tadd.w\tr3, sl, r1\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tadd.w\tr3, sl, r5\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tlsls\tr0, r0, #2\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tadd.w\tr2, sl, r0\n \tadd\tr4, r8\n \tadd\tip, r8\n+\tadd\tr3, sl\n+\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n \tadd\tlr, r8\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #376]\t@ 0x178\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n \tadd\tr6, r8\n \tadd\tr5, r8\n-\tadd\tr2, r8\n \tadd\tr3, r8\n-\tstr.w\tr3, [r7, #368]\t@ 0x170\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tmov\tr3, sl\n-\tmov\tsl, fp\n-\tmov\tfp, r3\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tmov\tr3, r9\n+\tmov\tr9, sl\n+\tmov\tsl, r3\n \tadd\tr0, r8\n \tadd\tr1, r8\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n-\tstrd\tr1, r0, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tvldr\ts14, [r4, #-4]\n-\tvldr\ts15, [ip, #-4]\n-\tvldr\ts13, [lr, #-4]\n-\tvldr\ts11, [r3, #-4]\n-\tvcvt.f64.f32\td27, s14\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tvcvt.f64.f32\td7, s15\n-\tvcvt.f64.f32\td20, s13\n-\tldr.w\tr2, [r7, #412]\t@ 0x19c\n-\tvcvt.f64.f32\td30, s11\n+\tstr.w\tr2, [r7, #616]\t@ 0x268\n+\tstr.w\tr0, [r7, #608]\t@ 0x260\n+\tstr.w\tr1, [r7, #408]\t@ 0x198\n+\tvstr\td14, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tvldr\ts4, [r4, #-4]\n+\tvldr\ts6, [ip, #-4]\n+\tvldr\ts14, [lr, #-4]\n+\tvldr\ts8, [r3, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td7, s14\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tvcvt.f64.f32\td4, s8\n \tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tvldr\ts12, [r3, #-4]\n-\tvadd.f64\td28, d27, d7\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n-\tvsub.f64\td7, d27, d7\n-\tvldr\ts9, [r2, #-4]\n-\tvcvt.f64.f32\td19, s12\n-\tadd.w\tr1, r3, r9\n-\tvadd.f64\td31, d28, d20\n-\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n-\tvldr\ts10, [r3, #-4]\n-\tvcvt.f64.f32\td27, s9\n-\tvldr\ts8, [r0, #-4]\n \tadds\tr2, #1\n-\tvadd.f64\td6, d30, d19\n-\tvsub.f64\td30, d30, d19\n+\tstr.w\tr2, [r7, #584]\t@ 0x248\n+\tvldr\ts10, [r3, #-4]\n+\tvadd.f64\td1, d2, d3\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tvsub.f64\td2, d2, d3\n+\tldr.w\tr2, [r7, #512]\t@ 0x200\n \tvcvt.f64.f32\td5, s10\n-\tvmov.f64\td19, d20\n-\tvfms.f64\td19, d28, d21\n-\tvfnms.f64\td20, d28, d21\n-\tstr.w\tr2, [r7, #428]\t@ 0x1ac\n-\tvcvt.f64.f32\td22, s8\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tvmov.f64\td29, d5\n-\tstr.w\tr1, [r7, #380]\t@ 0x17c\n-\tvfms.f64\td29, d6, d21\n-\tvfma.f64\td20, d16, d30\n-\tvadd.f64\td6, d6, d5\n-\tvcvt.f32.f64\ts11, d31\n-\tvmov.f64\td28, d19\n-\tvfma.f64\td19, d30, d17\n-\tvfma.f64\td28, d16, d30\n+\tvldr\ts1, [r0, #-4]\n+\tvadd.f64\td12, d1, d7\n+\tadd.w\tr1, r3, fp\n+\tvldr\ts12, [r3, #-4]\n+\tvmul.f64\td2, d2, d15\n+\tstr.w\tr1, [r7, #528]\t@ 0x210\n+\tadd.w\tr1, r2, fp\n+\tvadd.f64\td3, d4, d5\n+\tvsub.f64\td5, d4, d5\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f32.f64\ts24, d12\n+\tvcvt.f64.f32\td0, s1\n+\tstr.w\tr1, [r7, #512]\t@ 0x200\n+\tvmul.f64\td5, d5, d15\n+\tvmov.f64\td4, d6\n+\tvadd.f64\td6, d3, d6\n+\tvmls.f64\td4, d3, d13\n+\tvmul.f64\td3, d1, d13\n \tvcvt.f32.f64\ts12, d6\n-\tvstr\ts11, [lr, #-4]\n-\tadd\tlr, r9\n-\tvmov.f64\td31, d29\n-\tvfma.f64\td29, d16, d7\n-\tvfma.f64\td31, d7, d17\n-\tvmul.f64\td20, d24, d20\n \tvstr\ts12, [r3, #-4]\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvmul.f64\td19, d26, d19\n-\tvmul.f64\td30, d25, d28\n-\tvnmul.f64\td28, d28, d23\n-\tvfma.f64\td19, d24, d29\n-\tvfma.f64\td20, d26, d29\n-\tvfma.f64\td30, d23, d31\n-\tvfma.f64\td28, d25, d31\n-\tvcvt.f32.f64\ts9, d19\n-\tvmov.f64\td19, d22\n-\tvcvt.f32.f64\ts14, d30\n-\tvcvt.f32.f64\ts15, d28\n-\tvcvt.f32.f64\ts8, d20\n-\tvmov.f64\td20, d22\n-\tvstr\ts14, [r0, #-4]\n-\tvldr\ts12, [r3, #-4]\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tvldr\ts14, [r6, #-4]\n+\tmov\tr3, r0\n+\tvsub.f64\td1, d4, d2\n+\tvadd.f64\td4, d4, d2\n+\tvsub.f64\td2, d7, d3\n+\tvldr\ts12, [r2, #-4]\n+\tvsub.f64\td7, d3, d7\n+\tvstr\ts24, [lr, #-4]\n+\tadd.w\tr1, r3, fp\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tvmul.f64\td3, d9, d4\n+\tvmul.f64\td12, d8, d4\n+\tvadd.f64\td4, d5, d2\n+\tvsub.f64\td2, d2, d5\n+\tvadd.f64\td7, d7, d5\n \tvcvt.f64.f32\td6, s12\n-\tldr.w\tr0, [r7, #440]\t@ 0x1b8\n-\tadd.w\tr1, r3, r9\n-\tvstr\ts15, [r3, #-4]\n-\tvcvt.f64.f32\td7, s14\n-\tvldr\ts11, [r2, #-4]\n-\tldr.w\tr2, [r7, #400]\t@ 0x190\n-\tvldr\ts6, [r0, #-4]\n-\tvcvt.f64.f32\td30, s11\n-\tvadd.f64\td31, d6, d7\n-\tvsub.f64\td7, d6, d7\n+\tstr.w\tr1, [r7, #516]\t@ 0x204\n+\tadd.w\tr1, r3, fp\n+\tadd\tlr, fp\n+\tvmul.f64\td5, d10, d4\n+\tvmul.f64\td4, d11, d4\n+\tvmla.f64\td4, d10, d1\n+\tvmla.f64\td3, d7, d8\n+\tvmla.f64\td12, d2, d9\n+\tvnmls.f64\td5, d11, d1\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts29, d3\n+\tvcvt.f32.f64\ts28, d12\n+\tvcvt.f32.f64\ts10, d5\n+\tvstr\ts8, [r2, #-4]\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tvldr\ts4, [r6, #-4]\n+\tvstr\ts10, [r0, #-4]\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n+\tvldr\ts6, [r2, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tvldr\ts2, [r0, #-4]\n+\tvcvt.f64.f32\td3, s6\n \tvldr\ts10, [r2, #-4]\n-\tvcvt.f64.f32\td29, s6\n-\tldr.w\tr2, [r7, #396]\t@ 0x18c\n-\tvfms.f64\td19, d31, d21\n-\tvfnms.f64\td20, d31, d21\n+\tvcvt.f64.f32\td1, s2\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n \tvcvt.f64.f32\td5, s10\n-\tvadd.f64\td31, d22, d31\n-\tvldr\ts7, [r2, #-4]\n-\tstr.w\tr1, [r7, #412]\t@ 0x19c\n-\tvadd.f64\td6, d30, d5\n-\tvsub.f64\td30, d30, d5\n-\tvmov.f64\td5, d27\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n-\tvcvt.f64.f32\td28, s7\n-\tvcvt.f32.f64\ts7, d31\n-\tvmov.f64\td22, d19\n-\tadd\tr3, r9\n-\tvfms.f64\td5, d6, d21\n-\tvfma.f64\td22, d16, d30\n-\tvadd.f64\td6, d27, d6\n-\tvfma.f64\td19, d30, d17\n-\tvfma.f64\td20, d16, d30\n-\tstr.w\tr3, [r7, #516]\t@ 0x204\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tvstr\ts7, [r4, #-4]\n-\tadd\tr4, r9\n+\tvadd.f64\td4, d1, d3\n+\tvsub.f64\td7, d1, d3\n+\tvldr\ts24, [r2, #-4]\n+\tvmov.f64\td3, d0\n+\tvadd.f64\td1, d0, d4\n+\tvmls.f64\td3, d4, d13\n+\tvmul.f64\td4, d7, d15\n+\tvcvt.f64.f32\td12, s24\n+\tvcvt.f32.f64\ts2, d1\n+\tvstr\ts2, [r3, #-4]\n+\tvadd.f64\td1, d5, d2\n+\tvsub.f64\td5, d5, d2\n+\tldr.w\tr3, [r7, #408]\t@ 0x198\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tstr.w\tr1, [r7, #576]\t@ 0x240\n+\tvmul.f64\td2, d1, d13\n+\tvadd.f64\td1, d6, d1\n+\tvmul.f64\td5, d5, d15\n+\tvldr\ts15, [r3, #-4]\n+\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tvcvt.f32.f64\ts2, d1\n+\tvcvt.f64.f32\td0, s15\n+\tvstr\ts2, [r4, #-4]\n+\tvsub.f64\td1, d3, d5\n+\tvadd.f64\td3, d3, d5\n+\tvsub.f64\td5, d2, d6\n+\tvsub.f64\td6, d6, d2\n+\tadd\tr4, fp\n+\tvadd.f64\td5, d5, d4\n+\tvmul.f64\td2, d8, d3\n+\tvmul.f64\td3, d9, d3\n+\tvmla.f64\td3, d5, d8\n+\tvsub.f64\td5, d6, d4\n+\tvadd.f64\td4, d4, d6\n+\tvmla.f64\td2, d5, d9\n+\tvmul.f64\td6, d10, d4\n+\tvmul.f64\td4, d11, d4\n+\tvcvt.f32.f64\ts6, d3\n+\tvmov.f64\td5, d4\n+\tvnmls.f64\td6, d11, d1\n+\tvmla.f64\td5, d10, d1\n+\tvcvt.f32.f64\ts4, d2\n \tvcvt.f32.f64\ts12, d6\n-\tadd.w\tr1, r3, r9\n-\tldr.w\tr2, [r7, #404]\t@ 0x194\n-\tstr.w\tr1, [r7, #424]\t@ 0x1a8\n-\tvmov.f64\td27, d5\n-\tvfma.f64\td5, d16, d7\n-\tvfma.f64\td27, d7, d17\n-\tvmul.f64\td30, d25, d22\n-\tvmul.f64\td19, d26, d19\n-\tvnmul.f64\td22, d22, d23\n-\tvmul.f64\td20, d24, d20\n-\tvstr\ts12, [r3, #-4]\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr1, [r7, #392]\t@ 0x188\n-\tvfma.f64\td19, d24, d5\n-\tvfma.f64\td20, d26, d5\n-\tvfma.f64\td30, d23, d27\n-\tvfma.f64\td22, d25, d27\n-\tvcvt.f32.f64\ts14, d19\n-\tvcvt.f32.f64\ts15, d20\n-\tvcvt.f32.f64\ts12, d30\n-\tvcvt.f32.f64\ts13, d22\n-\tvstr\ts12, [r3, #-4]\n-\tldr.w\tr3, [r7, #396]\t@ 0x18c\n-\tvstr\ts14, [r0, #-4]\n-\tldr.w\tr0, [r7, #368]\t@ 0x170\n-\tvstr\ts13, [r2, #-4]\n-\tadd\tr2, r9\n-\tvstr\ts15, [r3, #-4]\n-\tvldr\ts14, [r5, #-4]\n-\tvldr\ts15, [r1, #-4]\n-\tldr.w\tr1, [r7, #376]\t@ 0x178\n-\tvcvt.f64.f32\td31, s14\n-\tvldr\ts12, [r0, #-4]\n-\tvcvt.f64.f32\td27, s15\n-\tstr.w\tr2, [r7, #404]\t@ 0x194\n-\tmov\tr2, r3\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvldr\ts11, [r1, #-4]\n+\tvcvt.f32.f64\ts10, d5\n+\tvstr\ts12, [r0, #-4]\n+\tvstr\ts10, [r2, #-4]\n+\tadd\tr2, fp\n+\tvstr\ts4, [r3, #-4]\n+\tadd\tr3, fp\n+\tstr.w\tr2, [r7, #608]\t@ 0x260\n+\tstr.w\tr3, [r7, #408]\t@ 0x198\n+\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr0, [r7, #624]\t@ 0x270\n+\tvstr\ts6, [r3, #-4]\n+\tadd\tr3, fp\n+\tvldr\ts12, [r2, #-4]\n+\tvldr\ts8, [r1, #-4]\n+\tvldr\ts6, [r5, #-4]\n \tvcvt.f64.f32\td6, s12\n-\tvadd.f64\td30, d29, d31\n-\tvsub.f64\td31, d29, d31\n-\tvadd.f64\td7, d28, d27\n-\tvsub.f64\td27, d28, d27\n-\tvcvt.f64.f32\td19, s11\n-\tadd\tr3, r9\n-\tvmov.f64\td20, d6\n-\tvmov.f64\td22, d6\n-\tvfms.f64\td20, d30, d21\n-\tvfnms.f64\td22, d30, d21\n-\tstr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvadd.f64\td30, d30, d6\n-\tvmov.f64\td28, d19\n-\tmov\tr3, r0\n-\tvfms.f64\td28, d7, d21\n-\tvadd.f64\td7, d7, d19\n-\tvfma.f64\td22, d16, d27\n-\tadd\tr3, r9\n-\tstr.w\tr3, [r7, #368]\t@ 0x170\n-\tadd\tr2, r9\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tvldr\ts10, [r0, #-4]\n+\tvcvt.f64.f32\td4, s8\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tvcvt.f64.f32\td3, s6\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tvcvt.f64.f32\td5, s10\n+\tvstr\ts29, [r1, #-4]\n+\tvadd.f64\td7, d12, d6\n+\tvsub.f64\td12, d12, d6\n+\tvmov.f64\td6, d4\n+\tadd\tr3, fp\n+\tstr.w\tr3, [r7, #624]\t@ 0x270\n+\tadd\tr1, fp\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tvmls.f64\td6, d7, d13\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td4, d0, d3\n+\tvsub.f64\td3, d0, d3\n+\tstr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tadd.w\tr1, r3, fp\n+\tvstr\ts28, [r0, #-4]\n \tvcvt.f32.f64\ts14, d7\n-\tstr.w\tr2, [r7, #396]\t@ 0x18c\n-\tvmov.f64\td19, d20\n-\tvfma.f64\td20, d27, d17\n-\tvfma.f64\td19, d16, d27\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tvcvt.f32.f64\ts15, d30\n-\tvstr\ts8, [r1, #-4]\n-\tvmov.f64\td29, d28\n-\tvfma.f64\td28, d16, d31\n-\tvfma.f64\td29, d31, d17\n-\tvmul.f64\td22, d24, d22\n+\tldr.w\tr0, [r7, #616]\t@ 0x268\n+\tvmul.f64\td2, d4, d13\n+\tvmul.f64\td3, d3, d15\n+\tvadd.f64\td0, d4, d5\n+\tadd\tr0, fp\n+\tstr.w\tr1, [r7, #568]\t@ 0x238\n \tvstr\ts14, [r3, #-4]\n-\tadd\tr2, r9\n-\tadd\tr3, r9\n-\tstr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tadd\tr1, r9\n-\tvstr\ts9, [r0, #-4]\n-\tvmul.f64\td20, d26, d20\n-\tstr.w\tr1, [r7, #376]\t@ 0x178\n-\tvnmul.f64\td27, d19, d23\n-\tvmul.f64\td19, d25, d19\n-\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tvfma.f64\td22, d26, d28\n-\tvfma.f64\td20, d24, d28\n-\tvfma.f64\td27, d25, d29\n-\tvfma.f64\td19, d23, d29\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tldr.w\tr2, [r7, #392]\t@ 0x188\n-\tvstr\ts15, [ip, #-4]\n-\tadd\tip, r9\n-\tvcvt.f32.f64\ts13, d22\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts12, d27\n-\tvcvt.f32.f64\ts15, d19\n-\tvstr\ts12, [r3, #-4]\n-\tadd\tr3, r9\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tvmul.f64\td7, d12, d15\n+\tvsub.f64\td1, d5, d2\n+\tvsub.f64\td2, d2, d5\n+\tvadd.f64\td5, d6, d3\n+\tvsub.f64\td6, d6, d3\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tvcvt.f32.f64\ts0, d0\n+\tstr.w\tr0, [r7, #616]\t@ 0x268\n+\tvadd.f64\td4, d7, d1\n+\tvadd.f64\td3, d2, d7\n+\tvsub.f64\td7, d1, d7\n+\tvmul.f64\td2, d9, d5\n+\tvmul.f64\td5, d8, d5\n+\tvstr\ts0, [ip, #-4]\n+\tadd\tip, fp\n+\tvmul.f64\td1, d10, d4\n+\tvmla.f64\td2, d3, d8\n+\tvmla.f64\td5, d7, d9\n+\tvmul.f64\td4, d11, d4\n+\tvmla.f64\td4, d10, d6\n+\tvmov.f64\td7, d1\n+\tvnmls.f64\td7, d11, d6\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r3, #-4]\n+\tadd\tr3, fp\n+\tstr.w\tr3, [r7, #560]\t@ 0x230\n \tmov\tr3, r2\n-\tadd\tr3, r9\n-\tvstr\ts13, [r2, #-4]\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n-\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr3, [r7, #276]\t@ 0x114\n-\tvstr\ts15, [r6, #-4]\n-\tadd\tr6, r9\n-\tvstr\ts14, [r5, #-4]\n+\tadd\tr3, fp\n+\tvstr\ts4, [r2, #-4]\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #292]\t@ 0x124\n+\tvstr\ts8, [r6, #-4]\n+\tadd\tr6, fp\n+\tvstr\ts10, [r5, #-4]\n \tcmp\tr2, r3\n-\tadd\tr5, r9\n-\tbne.w\ta588 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1e9c>\n-\tmov\tr3, fp\n-\tmov\tfp, sl\n-\tmov\tsl, r3\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tadd\tsl, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, sl\n-\tble.n\ta8de <__gridxc_gpfa_core_sp_MOD_gpfa_+0x21f2>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tsl, r3\n-\tldr.w\tr3, [r7, #384]\t@ 0x180\n-\tldr.w\tr2, [r7, #236]\t@ 0xec\n+\tadd\tr5, fp\n+\tbne.w\taa02 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1f26>\n+\tmov\tr3, sl\n+\tvldr\td14, [r7, #416]\t@ 0x1a0\n+\tmov\tsl, r9\n+\tmov\tr9, r3\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tcmp\tr3, r9\n+\tble.n\tad4e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2272>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tldr.w\tr2, [r7, #296]\t@ 0x128\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #384]\t@ 0x180\n+\tstr.w\tr3, [r7, #536]\t@ 0x218\n \tcmp\tr3, r2\n-\tbne.w\ta442 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d56>\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n-\tldr.w\tr1, [r7, #352]\t@ 0x160\n-\tldr.w\tr3, [r7, #388]\t@ 0x184\n-\tsubs\tr2, #1\n-\tadds\tr6, r2, #1\n-\tadd\tr1, r3\n-\tbne.w\ta432 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d46>\n-\tldrd\tr0, r4, [r7, #228]\t@ 0xe4\n-\tldrd\tip, r3, [r7, #220]\t@ 0xdc\n-\tsubs\tr0, #1\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n+\tbne.w\ta8b2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dd6>\n+\tldrd\tr2, r3, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n+\tsubs\tr3, #1\n+\tadd\tr2, r1\n+\tadds\tr6, r3, #1\n+\tbne.w\ta8a6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1dca>\n+\tldrd\tr5, r9, [r7, #268]\t@ 0x10c\n+\tldr.w\tr4, [r7, #256]\t@ 0x100\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\tcmp.w\tr9, #4294967295\t@ 0xffffffff\n+\tadd\tr5, r3\n+\tsub.w\tr3, r2, r3\n+\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tbne.w\ta866 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d8a>\n+\tldrd\tr2, r6, [r7, #276]\t@ 0x114\n+\tldr.w\tr0, [r7, #312]\t@ 0x138\n+\tldr.w\tr1, [r7, #336]\t@ 0x150\n+\tadd\tr2, r0\n+\tldr.w\tr0, [r7, #548]\t@ 0x224\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tadd\tr6, r1\n+\tsubs\tr1, r0, r1\n+\tldr.w\tr0, [r7, #360]\t@ 0x168\n+\tsubs\tr3, #1\n+\tstr.w\tr1, [r7, #548]\t@ 0x224\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tmov\tr1, r0\n+\tadds\tr3, #1\n+\tbeq.n\tae08 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x232c>\n+\tmov\tr3, r0\n \tadd\tr3, r4\n-\tsubs\tr2, r2, r4\n-\tstr.w\tr2, [r7, #364]\t@ 0x16c\n-\tadds\tr2, r0, #1\n-\tbne.w\ta3ea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1cfe>\n-\tldr.w\tr8, [r7, #256]\t@ 0x100\n-\tmov\tr0, r4\n-\tldr.w\tr9, [r7, #356]\t@ 0x164\n-\tldrd\tr1, r5, [r7, #240]\t@ 0xf0\n-\tsubs\tr5, #1\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n-\tadd\tr1, r8\n-\tldr.w\tr2, [r7, #284]\t@ 0x11c\n-\tsub.w\tip, ip, r8\n-\tadds\tr4, r5, #1\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #312]\t@ 0x138\n \tstr.w\tr3, [r7, #360]\t@ 0x168\n-\tmov\tr3, r2\n-\tbeq.n\ta974 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2288>\n-\tldr.w\tr4, [r7, #288]\t@ 0x120\n-\tadd\tr2, r4\n-\tstr.w\tr2, [r7, #312]\t@ 0x138\n-\tb.n\ta39a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1cae>\n-\tldr.w\tr1, [r7, #356]\t@ 0x164\n-\tldr.w\tr5, [r7, #316]\t@ 0x13c\n-\tsubs\tr2, r3, r1\n-\tcmp\tr1, r3\n-\tudiv\tr2, r2, r5\n-\tble.w\ta408 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d1c>\n-\tb.n\ta910 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2224>\n-\tldr.w\tr6, [r7, #260]\t@ 0x104\n-\tb.n\ta348 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c5c>\n-\tldr.w\tr4, [r7, #300]\t@ 0x12c\n-\tnegs\tr2, r0\n-\tsubs\tr3, r1, r4\n-\tcmp\tr4, r1\n-\tudiv\tr6, r3, r2\n-\tble.w\ta3ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1cde>\n-\tb.n\ta932 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2246>\n-\tsub.w\tr4, r8, r3\n-\trsb\tr1, r8, #0\n-\tcmp\tr8, r3\n-\tudiv\tr5, r4, r1\n-\tbge.w\t9ce6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15fa>\n-\tb.n\ta348 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c5c>\n-\tldr.w\tr4, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr6, [r7, #368]\t@ 0x170\n-\tsubs\tr2, r4, r6\n-\tldr.w\tr6, [r7, #344]\t@ 0x158\n-\tudiv\tr2, r2, r6\n-\tldr.w\tr6, [r7, #368]\t@ 0x170\n-\tcmp\tr6, r4\n-\tble.w\t9828 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x113c>\n-\tb.w\t9c96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15aa>\n-\trsb\tr3, lr, #0\n-\tnegs\tr2, r0\n-\tcmp.w\tlr, #0\n-\tudiv\tr1, r3, r2\n-\tble.w\t9058 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x96c>\n-\tb.w\t9cc0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15d4>\n-\tldr.w\tsl, [r7, #516]\t@ 0x204\n-\tb.w\t8fda <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8ee>\n-\tldr.w\tr9, [r7, #272]\t@ 0x110\n-\tldr.w\tsl, [r7, #264]\t@ 0x108\n-\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr2, [r7, #332]\t@ 0x14c\n-\tadd.w\tr3, r3, r2, lsl #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tcmp\tr3, #1\n-\tbne.w\tdb24 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5438>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tcmp\tr3, #1\n-\tbne.n\taac8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23dc>\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tmov\tsp, r9\n-\tcmp\tr3, #0\n-\tble.n\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n-\tmov\tr6, sp\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tb.n\tab32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2446>\n-\tmovs\tr3, #128\t@ 0x80\n-\tsub.w\tr5, r2, #128\t@ 0x80\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tb.w\t89c6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2da>\n-\tmov\tfp, ip\n-\tmov\tr8, r5\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tldr\tr2, [r7, #96]\t@ 0x60\n+\tb.n\ta808 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d2c>\n+\tldr.w\tr6, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #368]\t@ 0x170\n+\tsubs\tr0, r5, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, r5\n+\tmov\tr3, r0\n+\tble.w\ta886 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1daa>\n+\tb.n\tad7c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22a0>\n+\tldr.w\tr5, [r7, #688]\t@ 0x2b0\n+\tnegs\tr1, r3\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tsubs\tr0, r6, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tmov\tr9, r0\n+\tcmp\tr5, r6\n+\tble.w\ta848 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1d6c>\n+\tb.n\tad9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x22c2>\n+\tldr.w\tr5, [r7, #336]\t@ 0x150\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tcmp\tr3, r2\n-\tbne.w\taca0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x25b4>\n-\tldr.w\tr2, [r7, #224]\t@ 0xe0\n-\tmov\tr4, fp\n-\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr1, [r7, #412]\t@ 0x19c\n-\tcmp\tr2, #5\n-\tvstr\td7, [r7, #200]\t@ 0xc8\n-\tvstr\td31, [r7, #192]\t@ 0xc0\n-\tbne.w\tbaf0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3404>\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tadds\tr1, #1\n-\tldr.w\tr0, [r7, #552]\t@ 0x228\n-\tldr.w\tr5, [r7, #228]\t@ 0xe4\n-\tmla\tr2, r5, r0, r2\n-\tstr.w\tr2, [r7, #516]\t@ 0x204\n-\tldr\tr2, [r7, #48]\t@ 0x30\n-\tcmp\tr1, r2\n-\tbne.w\tac5e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2572>\n-\tldr\tr6, [r7, #52]\t@ 0x34\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n+\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tcmp\tr2, r3\n+\tbge.w\t944a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x96e>\n+\tb.w\t9968 <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe8c>\n+\tnegs\tr1, r5\n+\tsubs\tr0, r5, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, r4\n+\tstr.w\tr0, [r7, #632]\t@ 0x278\n+\tbge.w\ta130 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1654>\n+\tb.n\tae0c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2330>\n+\tldr.w\tr4, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tsubs\tr0, r6, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, r6\n+\tmov\tr3, r0\n+\tble.w\t9c66 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x118a>\n+\tb.w\ta0d6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x15fa>\n+\trsb\tr1, sl, #0\n+\tnegs\tr0, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr6, #0\n+\tmov\tr8, r0\n+\tble.w\t949e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x9c2>\n+\tb.w\ta100 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1624>\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tmov\tr8, sl\n+\tb.w\t9412 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x936>\n+\tldrd\tfp, r8, [r7, #284]\t@ 0x11c\n+\tldr.w\tr3, [r7, #392]\t@ 0x188\n+\tadd.w\tr8, r8, r3, lsl #1\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #1\n-\tbne.w\td890 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51a4>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tbne.w\te5b6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5ada>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\td7ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x50de>\n-\tmov\tsp, r6\n-\tldr\tr2, [pc, #36]\t@ (aac0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23d4>)\n-\tldr\tr3, [pc, #36]\t@ (aac4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23d8>)\n-\tadd\tr2, pc\n-\tldr\tr3, [r2, r3]\n-\tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #956]\t@ 0x3bc\n-\teors\tr2, r3\n-\tmov.w\tr3, #0\n-\tbne.w\tdd10 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5624>\n-\tadd.w\tr7, r7, #964\t@ 0x3c4\n-\tmov\tsp, r7\n-\tvpop\t{d8-d15}\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\t.word\t0x0000001e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tbne.n\taee4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2408>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tble.w\tdcee <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5602>\n-\tldr.w\tr2, [r7, #532]\t@ 0x214\n-\tldr.w\tr3, [r7, #336]\t@ 0x150\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tlsls\tr0, r2, #2\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tadd.w\tr1, r3, r1, lsl #2\n-\tldr.w\tr4, [r3], #4\n-\tstr\tr4, [r2, #0]\n-\tadd\tr2, r0\n-\tcmp\tr3, r1\n-\tbne.n\taae8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23fc>\n-\tmov\tsp, r9\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tldr.w\tr4, [r7, #740]\t@ 0x2e4\n+\tldr.w\tr5, [r7, #732]\t@ 0x2dc\n+\tstr.w\tsp, [r7, #500]\t@ 0x1f4\n+\tb.n\taf54 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2478>\n+\trsb\tr1, r8, #0\n+\tsub.w\tr0, r8, r6\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tmov\tsl, r0\n+\tcmp\tr8, r6\n+\tbge.w\t9008 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x52c>\n+\tb.w\t9412 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x936>\n+\tldr.w\tr0, [r7, #328]\t@ 0x148\n+\trsb\tr1, r9, #0\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tmov\tip, r0\n \tcmp\tr3, #0\n-\tble.n\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tmov\tr6, sp\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tble.w\t8e44 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x368>\n+\tb.w\t8fbe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4e2>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tcmp\tr3, #0\n+\tble.w\te780 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5ca4>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tlsls\tr4, r3, #2\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tadd.w\tr0, r2, r3, lsl #2\n+\tldr.w\tr3, [r2], #4\n+\tstr\tr3, [r1, #0]\n+\tadd\tr1, r4\n+\tcmp\tr2, r0\n+\tbne.n\taf04 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2428>\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tcmp\tr3, #0\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tstr.w\tsp, [r7, #500]\t@ 0x1f4\n \tcmp\tr3, #1\n-\tbeq.n\tab20 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2434>\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tit\teq\n+\tldreq.w\tr4, [r7, #740]\t@ 0x2e4\n+\tbeq.n\taf46 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x246a>\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tcmp\tr3, #0\n-\tbge.w\tdd1e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5632>\n-\tadd.w\tr3, r7, #576\t@ 0x240\n-\tstr.w\tr3, [r7, #252]\t@ 0xfc\n-\tmov\tr5, r3\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tittt\tlt\n+\taddlt.w\tr3, r7, #800\t@ 0x320\n+\tstrlt.w\tr3, [r7, #228]\t@ 0xe4\n+\tmovlt\tr4, r3\n+\tbge.w\te7ac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5cd0>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\td8ba <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51ce>\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tsubs\tr3, #1\n-\tldr.w\tr0, [sl]\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tstr.w\tr3, [r7, #240]\t@ 0xf0\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tstr.w\tr0, [r7, #224]\t@ 0xe0\n+\tbne.w\te34e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5872>\n+\tldr.w\tr5, [r7, #732]\t@ 0x2dc\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tadd.w\tr3, r8, #4294967295\t@ 0xffffffff\n+\tldr.w\tr1, [r7, #660]\t@ 0x294\n \tmovs\tr0, #5\n-\tvstr\td0, [r7, #560]\t@ 0x230\n-\tldr\tr4, [r3, #0]\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n+\tvldr\td14, [pc, #604]\t@ b1c0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26e4>\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr.w\tsl, [r1]\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tldr.w\tr9, [r3]\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr8, [r1]\n+\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #228]\t@ 0xe4\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tldr.w\tfp, [r3]\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tldr.w\tr8, [r3]\n+\tstr.w\tr3, [r7, #208]\t@ 0xd0\n+\tldr.w\tr3, [fp]\n+\tstr.w\tr3, [r7, #204]\t@ 0xcc\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tmov\tr1, r0\n-\tldr.w\tr0, [r7, #224]\t@ 0xe0\n-\tmovw\tr3, #26215\t@ 0x6667\n-\tmovt\tr3, #26214\t@ 0x6666\n-\tsubs\tr2, r1, r0\n+\tldr.w\tfp, [r7, #204]\t@ 0xcc\n+\tmov\tr6, r0\n+\tmov\tr1, r6\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, fp\n+\tsubs\tr3, r6, r2\n+\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n \tcmp.w\tr8, #4294967295\t@ 0xffffffff\n-\tvldr\td0, [r7, #560]\t@ 0x230\n-\tsdiv\tr1, r0, r1\n-\tmul.w\tr2, r4, r2\n-\tstr.w\tr2, [r7, #380]\t@ 0x17c\n-\tsmull\tr3, r2, r3, r1\n-\tmov.w\tr3, r1, asr #31\n-\tstr.w\tr1, [r7, #364]\t@ 0x16c\n-\trsb\tr3, r3, r2, asr #1\n-\tmov\tr2, r1\n-\tadd.w\tr3, r3, r3, lsl #2\n-\tmul.w\tr2, r2, r4\n-\tsub.w\tr3, r1, r3\n-\tmul.w\tr1, r0, r4\n-\tstr.w\tr2, [r7, #360]\t@ 0x168\n-\tstr.w\tr1, [r7, #524]\t@ 0x20c\n-\tbne.n\tabce <__gridxc_gpfa_core_sp_MOD_gpfa_+0x24e2>\n-\trsb\tr3, r3, #5\n-\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n-\tadds\tr2, #1\n-\tasrs\tr1, r2, #1\n-\tsubs\tr2, r3, #2\n-\tcmp\tr2, #1\n-\tbls.w\tba92 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33a6>\n-\tvldr\td1, [pc, #368]\t@ ad50 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2664>\n-\tvldr\td8, [pc, #372]\t@ ad58 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x266c>\n-\tvldr\td16, [pc, #376]\t@ ad60 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2674>\n-\tvldr\td17, [pc, #380]\t@ ad68 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x267c>\n-\tvldr\td10, [pc, #384]\t@ ad70 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2684>\n-\tsubs\tr3, #3\n-\tcmp\tr3, #1\n-\tbls.n\tabfc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2510>\n-\tvmov.f64\td8, d17\n-\tbics.w\tr3, r2, #2\n-\tvmov\ts15, r8\n-\tadd.w\tr3, fp, #126\t@ 0x7e\n-\tvcvt.f64.s32\td17, s15\n-\tvseleq.f64\td1, d1, d16\n-\tsubs.w\tr2, fp, #1\n+\tvmov\ts11, r8\n+\tvldr\td2, [pc, #524]\t@ b1c8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26ec>\n+\tmul.w\tr2, fp, r9\n+\tmul.w\tr1, r9, r3\n+\tmov\tr3, r0\n+\tstr.w\tr1, [r7, #428]\t@ 0x1ac\n+\tmovw\tr1, #26215\t@ 0x6667\n+\tmovt\tr1, #26214\t@ 0x6666\n+\tvcvt.f64.s32\td5, s11\n+\tvldr\td3, [pc, #500]\t@ b1d0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26f4>\n+\tvldr\td4, [pc, #504]\t@ b1d8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26fc>\n+\tsmull\tr1, r0, r1, r0\n+\tmov.w\tr1, r3, asr #31\n+\tvstr\td5, [r7, #192]\t@ 0xc0\n+\tvldr\td7, [pc, #496]\t@ b1e0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2704>\n+\trsb\tr1, r1, r0, asr #1\n+\tvldr\td6, [pc, #496]\t@ b1e8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x270c>\n+\tstr.w\tr2, [r7, #752]\t@ 0x2f0\n+\tadd.w\tr1, r1, r1, lsl #2\n+\tsub.w\tr1, r3, r1\n+\tmul.w\tr3, r3, r9\n+\tit\teq\n+\trsbeq\tr1, r1, #5\n+\tstr.w\tr3, [r7, #648]\t@ 0x288\n+\tsubs\tr0, r1, #2\n+\tsubs\tr1, #3\n+\tcmp\tr0, #2\n+\tite\tcs\n+\tvmovcs.f64\td5, d3\n+\tvmovcc.f64\td5, d2\n+\tite\tcs\n+\tvmovcs.f64\td15, d4\n+\tvmovcc.f64\td15, d14\n+\tit\tcc\n+\tvmovcc.f64\td14, d4\n+\tvstr\td5, [r7, #184]\t@ 0xb8\n+\tite\tcs\n+\tvmovcs.f64\td5, d7\n+\tvmovcc.f64\td5, d6\n+\tit\tcs\n+\tvmovcs.f64\td7, d6\n+\tcmp\tr1, #2\n+\tadd.w\tr1, sl, #126\t@ 0x7e\n+\tit\tcs\n+\tvmovcs.f64\td14, d5\n+\tbics.w\tr3, r0, #2\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tit\tne\n+\tvmovne.f64\td15, d7\n+\tsubs.w\tr0, sl, #1\n \tit\tpl\n-\tmovpl\tr3, r2\n-\tcmn.w\tfp, #126\t@ 0x7e\n-\tmov.w\tr3, r3, asr #7\n-\tvstr\td17, [r7, #88]\t@ 0x58\n-\tblt.w\taa84 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2398>\n-\tadds\tr2, r1, #1\n-\tstr\tr2, [r7, #96]\t@ 0x60\n-\tadds\tr2, r3, #2\n-\tldr.w\tr3, [r7, #224]\t@ 0xe0\n-\tvneg.f64\td11, d10\n-\tvneg.f64\td12, d1\n-\tsubs\tr3, #1\n-\tvldr\td2, [r7, #208]\t@ 0xd0\n-\tmovs\tr1, #1\n-\tstr\tr6, [r7, #52]\t@ 0x34\n-\tstr.w\tr1, [r7, #516]\t@ 0x204\n-\tmul.w\tr3, r4, r3\n-\tmov\tr4, r5\n-\tstr.w\tr3, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr3, [r7, #228]\t@ 0xe4\n-\tstr\tr2, [r7, #48]\t@ 0x30\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tmov\tr3, fp\n-\tcmp\tr3, #128\t@ 0x80\n-\tble.w\tba88 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x339c>\n-\tcmp\tr3, #255\t@ 0xff\n-\tbgt.w\tba7c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3390>\n-\tasrs\tr0, r3, #1\n-\tadds\tr0, #1\n-\tbic.w\tr2, r0, #1\n-\tstr.w\tr2, [r7, #552]\t@ 0x228\n-\tsubs\tr3, r3, r2\n-\tldr.w\tr8, [r7, #360]\t@ 0x168\n-\tmov\tfp, r4\n-\tvldr\td16, [r7, #88]\t@ 0x58\n-\tmovs\tr2, #1\n-\tvldr\td7, [r7, #200]\t@ 0xc8\n-\tvldr\td31, [r7, #192]\t@ 0xc0\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n-\tstr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tstr.w\tr1, [r7, #412]\t@ 0x19c\n-\tvstr\td16, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tcmp.w\tr8, #0\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n-\tmov\tr0, r3\n-\tadd.w\tr3, r3, r3, lsl #2\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n-\tsdiv\tr3, r2, r3\n-\tsub.w\tr2, r3, r2\n-\tstr.w\tr2, [r7, #560]\t@ 0x230\n-\tsub.w\tr2, r3, r8\n-\tblt.w\tbaaa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33be>\n-\tudiv\tr1, r2, r8\n-\tcmp\tr2, #0\n-\tblt.w\taa36 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x234a>\n-\tadd.w\tr2, r3, r3, lsl #2\n-\tlsls\tr3, r0, #1\n-\tnegs\tr4, r2\n-\tstr.w\tr4, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr4, [r7, #228]\t@ 0xe4\n-\tcmp\tr4, #1\n-\tmov.w\tr4, #24\n-\tbne.w\tb474 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d88>\n-\tmul.w\tr3, r4, r3\n-\tldr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tlsls\tr6, r0, #4\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n-\tnegs\tr4, r5\n-\tmov\tsl, r5\n-\tmov\tip, fp\n-\tadds\tr3, #8\n-\tmovs\tr5, #0\n-\tmov\tfp, r1\n-\tstr.w\tr6, [r7, #444]\t@ 0x1bc\n-\tmov\tr1, r4\n-\tlsls\tr6, r0, #5\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tlsls\tr0, r0, #6\n-\tstr.w\tr6, [r7, #428]\t@ 0x1ac\n+\tmovpl\tr1, r0\n+\tadds\tr0, r3, #1\n+\tcmn.w\tsl, #126\t@ 0x7e\n+\tmov.w\tr1, r1, asr #7\n+\tmov.w\tr0, r0, asr #1\n+\tblt.w\tb6b2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bd6>\n+\tadds\tr3, r0, #1\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tadds\tr3, r1, #2\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tmov\tr6, r4\n+\tldr.w\tr2, [r7, #208]\t@ 0xd0\n+\tsubs\tr1, r3, #1\n+\tlsls\tr2, r2, #2\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tmul.w\tr3, r9, r1\n+\tstr.w\tr3, [r7, #660]\t@ 0x294\n+\tmovs\tr3, #1\n \tmov\tr9, r3\n-\tstr.w\tr0, [r7, #420]\t@ 0x1a4\n-\tmov\tlr, r3\n-\tmov\tr0, r3\n-\tmov\tr5, r8\n-\tmov\tr6, r3\n-\tmov\tr4, r3\n-\tstr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tsubs\tr3, r4, #4\n+\tmov\tr4, r9\n+\tstr\tr3, [r7, #64]\t@ 0x40\n+\tcmp.w\tsl, #128\t@ 0x80\n+\titt\tle\n+\tstrle.w\tsl, [r7, #756]\t@ 0x2f4\n+\tmovle.w\tsl, #0\n+\tble.n\tb0dc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2600>\n+\tcmp.w\tsl, #255\t@ 0xff\n+\titete\tle\n+\tmovle.w\tr3, sl, asr #1\n+\tsubgt.w\tsl, sl, #128\t@ 0x80\n+\taddle\tr3, #1\n+\tmovgt\tr3, #128\t@ 0x80\n+\titett\tle\n+\tbicle.w\tr3, r3, #1\n+\tstrgt.w\tr3, [r7, #756]\t@ 0x2f4\n+\tsuble.w\tsl, sl, r3\n+\tstrle.w\tr3, [r7, #756]\t@ 0x2f4\n+\tvldr\td13, [r7, #184]\t@ 0xb8\n+\tmovs\tr3, #1\n+\tstr.w\tsl, [r7, #584]\t@ 0x248\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tstr.w\tr3, [r7, #668]\t@ 0x29c\n+\tstrd\tr5, r6, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr4, [r7, #576]\t@ 0x240\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr.w\tr4, [r7, #752]\t@ 0x2f0\n+\tmov\tsl, r3\n+\tadd.w\tr3, r3, r3, lsl #2\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r4\n+\tstr.w\tr3, [r7, #788]\t@ 0x314\n+\tmov\tr9, r0\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tsubs\tr5, r0, r3\n \tcmp\tr3, #0\n-\tblt.w\tb0ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x29de>\n-\tudiv\tr8, sl, r3\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #440]\t@ 0x1b8\n+\tblt.w\tb65c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b80>\n+\tmov\tr1, r3\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tr8, r0\n+\tblt.w\tb66c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b90>\n+\tadd.w\tr9, r9, r9, lsl #2\n+\tmov.w\tr3, sl, lsl #1\n+\trsb\tr2, r9, #0\n+\tstr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr2, [r7, #208]\t@ 0xd0\n+\tcmp\tr2, #1\n+\tmov.w\tr2, #24\n+\tmul.w\tr3, r2, r3\n+\tbne.w\tb986 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2eaa>\n+\tstr.w\tr3, [r7, #600]\t@ 0x258\n+\tmov\tr5, r8\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n+\tadd.w\tr6, r3, #8\n+\tldr.w\tr8, [r7, #748]\t@ 0x2ec\n+\tnegs\tr3, r2\n+\tmov\tfp, r6\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tmov\tr4, r6\n+\tmov.w\tr3, sl, lsl #4\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tmov.w\tr3, sl, lsl #5\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tmov.w\tr3, sl, lsl #6\n+\tmov\tsl, r6\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tmovs\tr2, #0\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tcmp.w\tr9, #0\n+\tblt.w\tb562 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2a86>\n+\tldr.w\tr0, [r7, #700]\t@ 0x2bc\n+\tmov\tr1, r9\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n \tcmp\tr3, r2\n-\tblt.w\tb04e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2962>\n-\tb.n\tad78 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x268c>\n-\t.word\t0x04755a5d\n-\t.word\t0xbfe2cf23\n+\tblt.w\tb4b8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x29dc>\n+\tb.n\tb1f0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2714>\n \t.word\t0x13445503\n \t.word\t0xbfee6f0e\n+\t.word\t0x9b97f4a4\n+\t.word\t0xbfe1e377\n+\t.word\t0x9b97f4a4\n+\t.word\t0x3fe1e377\n \t.word\t0x04755a5d\n-\t.word\t0x3fe2cf23\n+\t.word\t0xbfe2cf23\n \t.word\t0x13445503\n \t.word\t0x3fee6f0e\n-\t.word\t0x9b97f4a4\n-\t.word\t0x3fe1e377\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n+\t.word\t0x04755a5d\n+\t.word\t0x3fe2cf23\n+\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n \tcmp\tr3, #0\n-\tble.w\tb04e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2962>\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tvmov.f64\td25, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tstrd\tr1, sl, [r7, #396]\t@ 0x18c\n-\tmov\tr1, r4\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tstrd\tr5, fp, [r7, #404]\t@ 0x194\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tsub.w\tr3, ip, #4\n-\tstr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tmov\tr3, r2\n-\tstr.w\tr6, [r7, #392]\t@ 0x188\n-\tstrd\tr0, r9, [r7, #384]\t@ 0x180\n-\tldr.w\tr9, [r7, #516]\t@ 0x204\n-\tmovs\tr2, #1\n-\tmov\tr4, r3\n-\tstr.w\tr2, [r7, #536]\t@ 0x218\n-\tmov\tlr, r1\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n-\tstr.w\tr2, [r7, #556]\t@ 0x22c\n-\tstrd\tr3, r8, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tadds\tr6, r3, r4\n-\tcmp\tr9, r6\n-\tble.n\tade0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26f4>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr6, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tadds\tr1, r3, r6\n-\tcmp\tr9, r1\n-\tble.n\tadf0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2704>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr1, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tadd\tr3, r1\n-\tcmp\tr9, r3\n-\tble.n\tae00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2714>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tadd\tr3, r2\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tadds\tr0, r2, r3\n-\tcmp\tr9, r0\n-\tble.n\tae10 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2724>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tadd\tr0, r2\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tcmp\tr2, #0\n-\tbne.w\tb20a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b1e>\n-\tldr.w\tr2, [r7, #552]\t@ 0x228\n-\tcmp\tr2, #0\n-\tble.w\taffc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2910>\n-\tadd.w\tr8, r2, r6\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n-\tadd.w\tr5, r6, #1073741824\t@ 0x40000000\n+\tble.w\tb4b8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x29dc>\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tadd.w\tlr, r3, #1\n+\tstr.w\tr6, [r7, #560]\t@ 0x230\n+\tmov\tr6, r8\n+\tadd\tr2, r8\n+\tstr.w\tr5, [r7, #568]\t@ 0x238\n+\tstr.w\tsl, [r7, #552]\t@ 0x228\n+\tstr.w\tlr, [r7, #624]\t@ 0x270\n+\tmovs\tr3, #1\n+\tmov\tip, r2\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tmov\tlr, r4\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tmov\tr8, fp\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tstrd\tr0, r9, [r7, #680]\t@ 0x2a8\n+\tstr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tadd.w\tr5, r3, ip\n+\tcmp\tr6, r5\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr5, r5, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tadds\tr1, r3, r5\n+\tcmp\tr6, r1\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr1, r1, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tadds\tr2, r3, r1\n+\tcmp\tr6, r2\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tadds\tr0, r3, r2\n+\tcmp\tr6, r0\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tr0, r0, r3\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tcmp\tr3, #0\n+\tbne.w\tb714 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c38>\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tcmp\tr3, #0\n+\tble.w\tb46e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2992>\n+\tadd.w\tr9, r3, r5\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr4, r5, #1073741824\t@ 0x40000000\n+\tlsls\tr5, r5, #2\n+\tsubs\tr4, #1\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n+\tadd.w\tr3, r3, r9, lsl #2\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tlsls\tr6, r6, #2\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tnegs\tr3, r5\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tlsls\tr4, r4, #2\n \tsubs\tr0, #1\n \tsubs\tr1, #1\n-\tsubs\tr3, #1\n-\tsubs\tr5, #1\n-\tadd.w\tr2, r2, r8, lsl #2\n-\tstr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tnegs\tr2, r6\n-\tstr.w\tr2, [r7, #508]\t@ 0x1fc\n+\tsubs\tr2, #1\n+\tadds\tr5, r3, r4\n+\tstr.w\tr5, [r7, #784]\t@ 0x310\n \tlsls\tr0, r0, #2\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n \tlsls\tr1, r1, #2\n-\tlsls\tr3, r3, #2\n-\tlsls\tr5, r5, #2\n-\tadd.w\tr6, ip, r5\n-\tadd.w\tfp, ip, r0\n-\tadd\tr5, r2\n-\tadd\tr0, r2\n-\tadd.w\tsl, ip, r1\n-\tadd.w\tr8, ip, r3\n-\tadd\tr1, r2\n-\tadd\tr3, r2\n-\tstr.w\tip, [r7, #468]\t@ 0x1d4\n-\tlsls\tr2, r4, #2\n-\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tvldr\ts13, [fp]\n-\tvldmia\tr6!, {s12}\n-\tvldmia\tr5!, {s6}\n-\tvcvt.f64.f32\td17, s13\n-\tvldr\ts13, [sl]\n-\tvcvt.f64.f32\td20, s12\n-\tvldr\ts10, [r1]\n-\tvldr\ts11, [r3]\n-\tvcvt.f64.f32\td18, s6\n-\tvcvt.f64.f32\td16, s13\n-\tvldr\ts13, [r8]\n-\tvldr\ts7, [r0]\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tvadd.f64\td24, d17, d20\n-\tvcvt.f64.f32\td19, s13\n-\tvsub.f64\td20, d20, d17\n-\tvcvt.f64.f32\td26, s11\n-\tvcvt.f64.f32\td22, s7\n-\tvcvt.f64.f32\td17, s10\n-\tadd.w\tip, r6, r2\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tvadd.f64\td23, d19, d16\n-\tvsub.f64\td16, d16, d19\n-\tadd\tip, r2\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tvadd.f64\td19, d26, d17\n-\tvsub.f64\td17, d17, d26\n-\tvadd.f64\td21, d23, d24\n-\tvmul.f64\td28, d8, d16\n-\tvsub.f64\td24, d24, d23\n-\tvadd.f64\td23, d22, d18\n-\tvldr\ts13, [ip, #-4]\n-\tvsub.f64\td18, d18, d22\n-\tvmul.f64\td16, d1, d16\n-\tvmov.f64\td22, d28\n-\tvfma.f64\td16, d8, d20\n-\tvadd.f64\td26, d19, d23\n-\tvsub.f64\td23, d23, d19\n-\tvmul.f64\td19, d8, d17\n-\tvfnms.f64\td22, d1, d20\n-\tvfma.f64\td28, d12, d20\n-\tvcvt.f64.f32\td20, s13\n-\tvmul.f64\td17, d1, d17\n-\tvfma.f64\td17, d8, d18\n-\tvmov.f64\td27, d19\n-\tvfma.f64\td19, d18, d12\n-\tvfnms.f64\td27, d1, d18\n-\tvmov.f64\td18, d20\n-\tvfms.f64\td18, d21, d25\n-\tvadd.f64\td20, d20, d21\n-\tvcvt.f32.f64\ts13, d20\n-\tvmov.f64\td21, d18\n-\tvfma.f64\td18, d11, d24\n-\tvfma.f64\td21, d10, d24\n-\tvstr\ts13, [ip, #-4]\n-\tadd.w\tip, r5, r2\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tadd\tip, r2\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tcmp\tr6, r2\n-\tvadd.f64\td19, d19, d18\n-\tvadd.f64\td18, d27, d18\n-\tvsub.f64\td5, d21, d17\n-\tvadd.f64\td21, d17, d21\n-\tvcvt.f32.f64\ts12, d19\n-\tvcvt.f32.f64\ts13, d18\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts11, d21\n-\tvstr\ts10, [r6, #-4]\n-\tvstmia\tfp!, {s11}\n-\tvstmia\tsl!, {s12}\n-\tvstmia\tr8!, {s13}\n-\tvldr\ts13, [ip, #-4]\n-\tvcvt.f64.f32\td17, s13\n-\tvmov.f64\td19, d17\n-\tvadd.f64\td17, d17, d26\n-\tvfms.f64\td19, d26, d25\n-\tvcvt.f32.f64\ts13, d17\n-\tvstr\ts13, [ip, #-4]\n-\tvmov.f64\td18, d19\n-\tvfma.f64\td19, d23, d11\n-\tvfma.f64\td18, d10, d23\n-\tvadd.f64\td22, d19, d22\n-\tvadd.f64\td28, d28, d19\n-\tvadd.f64\td5, d18, d16\n-\tvsub.f64\td18, d18, d16\n-\tvcvt.f32.f64\ts12, d28\n-\tvcvt.f32.f64\ts10, d5\n-\tvcvt.f32.f64\ts13, d18\n-\tvcvt.f32.f64\ts11, d22\n-\tvstr\ts10, [r5, #-4]\n-\tvstmia\tr0!, {s13}\n-\tvstmia\tr1!, {s11}\n-\tvstmia\tr3!, {s12}\n-\tbne.w\tae82 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2796>\n-\tldr.w\tip, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr3, [r7, #380]\t@ 0x17c\n-\tadd\tr4, r3\n-\tcmp\tr9, r4\n-\tble.n\tb00c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2920>\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr2, [r7, #464]\t@ 0x1d0\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tcmp\tr3, r2\n-\tbne.w\tadd0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26e4>\n-\tldrd\tr3, r8, [r7, #480]\t@ 0x1e0\n-\tmov\tr1, lr\n-\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tlsls\tr2, r2, #2\n+\tadd.w\tfp, r3, r0\n+\tadd.w\tsl, r3, r1\n+\tadd.w\tr9, r3, r2\n+\tadd\tr4, r5\n+\tadd\tr2, r5\n+\tadd\tr0, r5\n+\tadd\tr1, r5\n+\tmov.w\tr3, ip, lsl #2\n+\tldr.w\tr5, [r7, #784]\t@ 0x310\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr6, [r7, #640]\t@ 0x280\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tvldmia\tr5!, {s0}\n+\tvldmia\tr4!, {s8}\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tvldr\ts14, [r3]\n+\tvcvt.f64.f32\td0, s0\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts2, [fp]\n+\tvldr\ts4, [sl]\n+\tadds\tr6, r5, r3\n+\tvldr\ts6, [r9]\n+\tadds\tr3, r4, r3\n+\tvldr\ts10, [r0]\n \tadd\tr3, r2\n-\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n-\tbne.w\tadb6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26ca>\n-\tldrd\tr5, fp, [r7, #404]\t@ 0x194\n+\tvldr\ts12, [r1]\n+\tadd\tr6, r2\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td5, s10\n+\tvcvt.f64.f32\td7, s14\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts17, [r6, #-4]\n+\tvldr\ts16, [r3, #-4]\n+\tvcvt.f64.f32\td9, s17\n+\tvsub.f64\td11, d6, d7\n+\tvcvt.f64.f32\td10, s16\n+\tvadd.f64\td8, d1, d0\n+\tvsub.f64\td0, d0, d1\n+\tvadd.f64\td1, d3, d2\n+\tvsub.f64\td2, d2, d3\n+\tvadd.f64\td3, d5, d4\n+\tvsub.f64\td4, d4, d5\n+\tvadd.f64\td5, d7, d6\n+\tvadd.f64\td7, d1, d8\n+\tvsub.f64\td1, d8, d1\n+\tvadd.f64\td6, d5, d3\n+\tvsub.f64\td3, d3, d5\n+\tvmov.f64\td5, d9\n+\tvmul.f64\td8, d14, d4\n+\tvmls.f64\td5, d7, d12\n+\tvadd.f64\td9, d9, d7\n+\tvmov.f64\td7, d10\n+\tvmla.f64\td8, d15, d11\n+\tvadd.f64\td10, d10, d6\n+\tvmls.f64\td7, d6, d12\n+\tvmul.f64\td1, d1, d13\n+\tvmul.f64\td6, d15, d4\n+\tvmul.f64\td3, d3, d13\n+\tvcvt.f32.f64\ts18, d9\n+\tvmul.f64\td11, d14, d11\n+\tvcvt.f32.f64\ts20, d10\n+\tvstr\ts18, [r6, #-4]\n+\tvadd.f64\td9, d5, d1\n+\tvsub.f64\td5, d5, d1\n+\tvstr\ts20, [r3, #-4]\n+\tvmul.f64\td10, d14, d0\n+\tvmla.f64\td10, d15, d2\n+\tvmul.f64\td0, d15, d0\n+\tvmul.f64\td2, d14, d2\n+\tvadd.f64\td1, d7, d3\n+\tvsub.f64\td7, d7, d3\n+\tvsub.f64\td3, d11, d6\n+\tvsub.f64\td11, d6, d11\n+\tvsub.f64\td6, d9, d8\n+\tvadd.f64\td8, d8, d9\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tvsub.f64\td4, d0, d2\n+\tvsub.f64\td2, d2, d0\n+\tvadd.f64\td3, d3, d5\n+\tvcvt.f32.f64\ts12, d6\n+\tvcvt.f32.f64\ts16, d8\n+\tvadd.f64\td4, d4, d7\n+\tvadd.f64\td2, d2, d7\n+\tvadd.f64\td7, d11, d5\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts12, [r5, #-4]\n+\tvstmia\tfp!, {s16}\n+\tvcvt.f32.f64\ts8, d4\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts14, d7\n+\tvstmia\tsl!, {s6}\n+\tvstmia\tr9!, {s14}\n+\tvadd.f64\td7, d1, d10\n+\tvsub.f64\td1, d1, d10\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts2, d1\n+\tvstr\ts14, [r4, #-4]\n+\tvstmia\tr0!, {s2}\n+\tvstmia\tr1!, {s8}\n+\tvstmia\tr3!, {s4}\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tcmp\tr5, r3\n+\tbne.w\tb2f4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2818>\n+\tldr.w\tr6, [r7, #640]\t@ 0x280\n+\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tadd\tip, r3\n+\tcmp\tr6, ip\n+\tadd.w\tr2, r2, #1\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\titt\tgt\n+\tldrgt.w\tr3, [r7, #768]\t@ 0x300\n+\taddgt\tip, r3\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tcmp\tr2, r3\n+\tbne.w\tb232 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2756>\n+\tldrd\tr0, r9, [r7, #680]\t@ 0x2a8\n \tmov\tr4, lr\n-\tldr.w\tsl, [r7, #400]\t@ 0x190\n-\tldr.w\tr6, [r7, #392]\t@ 0x188\n-\tldr.w\tr1, [r7, #396]\t@ 0x18c\n-\tldrd\tr0, r9, [r7, #384]\t@ 0x180\n-\tadd.w\tfp, fp, #4294967295\t@ 0xffffffff\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tsub.w\tsl, sl, r5\n-\tadd\tr1, r5\n-\tcmp.w\tfp, #4294967295\t@ 0xffffffff\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tmov\tfp, r8\n+\tsubs\tr0, #1\n+\tadd\tr2, r9\n+\tadds\tr5, r0, #1\n+\tbne.w\tb216 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x273a>\n+\tmov\tr8, r6\n+\tldr.w\tr5, [r7, #568]\t@ 0x238\n+\tldr.w\tr6, [r7, #560]\t@ 0x230\n+\tldr.w\tsl, [r7, #552]\t@ 0x228\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tsubs\tr5, #1\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tadds\tr0, r5, #1\n+\tadd\tr2, r3\n+\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tsub.w\tr2, r2, r3\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tadd\tr2, r3\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n \tadd\tr6, r3\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n \tadd\tr4, r3\n-\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tadd\tr9, r3\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n-\tadd\tr0, r3\n-\tbeq.w\taa32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2346>\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tcmp\tr3, #0\n-\tble.w\tad32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2646>\n-\tvldr\td16, [r7, #448]\t@ 0x1c0\n-\tvldr\td31, [r6]\n-\tvldr\td15, [r4]\n-\tvldr\td14, [r9]\n-\tvldr\td13, [r0]\n-\tvmul.f64\td31, d16, d31\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tvmul.f64\td15, d16, d15\n-\tvmul.f64\td14, d16, d14\n-\tvldr\td9, [r6, #-8]\n-\tvmul.f64\td13, d16, d13\n-\tvldr\td0, [r4, #-8]\n-\tvldr\td2, [r9, #-8]\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n+\tadd\tfp, r3\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tadd\tsl, r3\n+\tbeq.w\tb66c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b90>\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n \tcmp\tr3, #0\n-\tvldr\td7, [r0, #-8]\n-\tbge.w\tad3c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2650>\n-\tldr.w\tr3, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tudiv\tr8, r1, r3\n-\tldr.w\tr3, [r7, #440]\t@ 0x1b8\n+\tble.w\tb19e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26c2>\n+\tvldr\td3, [r6, #-8]\n+\tcmp.w\tr9, #0\n+\tvldr\td7, [fp]\n+\tvldr\td4, [sl]\n+\tvstr\td3, [r7, #776]\t@ 0x308\n+\tvldr\td3, [r4, #-8]\n+\tvldr\td5, [r6]\n+\tvldr\td6, [r4]\n+\tvstr\td3, [r7, #488]\t@ 0x1e8\n+\tvldr\td3, [r7, #192]\t@ 0xc0\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td5, d3, d5\n+\tvmul.f64\td6, d3, d6\n+\tvstr\td7, [r7, #448]\t@ 0x1c0\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td5, [r7, #464]\t@ 0x1d0\n+\tvstr\td6, [r7, #456]\t@ 0x1c8\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvldr\td7, [fp, #-8]\n+\tvstr\td7, [r7, #480]\t@ 0x1e0\n+\tvldr\td7, [sl, #-8]\n+\tvstr\td7, [r7, #472]\t@ 0x1d8\n+\tbge.w\tb1a6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x26ca>\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n \tcmp\tr3, r2\n-\tble.w\tad78 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x268c>\n-\tb.n\tb04e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2962>\n-\tldr\tr3, [pc, #892]\t@ (b460 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d74>)\n-\tadd.w\tfp, r7, #592\t@ 0x250\n-\tvldr\td16, [pc, #876]\t@ b458 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d6c>\n-\tmov\tr0, fp\n+\tble.w\tb1f0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2714>\n+\tb.n\tb4b8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x29dc>\n+\tldr\tr3, [pc, #376]\t@ (b6f8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c1c>)\n+\tadd.w\tr4, r7, #816\t@ 0x330\n+\tvldr\td7, [pc, #360]\t@ b6f0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c14>\n+\tmov\tr0, r4\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #600]\t@ 0x258\n-\tldr\tr3, [pc, #876]\t@ (b464 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d78>)\n-\tadd.w\tr6, r7, #936\t@ 0x3a8\n-\tvstr\td0, [r7, #544]\t@ 0x220\n-\tmovs\tr5, #20\n-\tvstr\td16, [r7, #592]\t@ 0x250\n+\tstr.w\tr3, [r7, #824]\t@ 0x338\n+\tldr\tr3, [pc, #360]\t@ (b6fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c20>)\n+\tadd.w\tr5, r7, #1160\t@ 0x488\n+\tvstr\td7, [r7, #816]\t@ 0x330\n+\tmovs\tr6, #20\n \tadd\tr3, pc\n-\tstr.w\tr2, [r7, #648]\t@ 0x288\n-\tstr.w\tr2, [r7, #560]\t@ 0x230\n-\tstr.w\tr3, [r7, #644]\t@ 0x284\n+\tstr.w\tr5, [r7, #884]\t@ 0x374\n+\tstr.w\tr3, [r7, #868]\t@ 0x364\n \tmovs\tr3, #156\t@ 0x9c\n-\tstr.w\tr6, [r7, #660]\t@ 0x294\n-\tstr.w\tr3, [r7, #604]\t@ 0x25c\n+\tstr.w\tr6, [r7, #888]\t@ 0x378\n+\tstr.w\tr3, [r7, #828]\t@ 0x33c\n \tmovs\tr3, #0\n-\tstr.w\tr5, [r7, #664]\t@ 0x298\n-\tstr.w\tr3, [r7, #640]\t@ 0x280\n+\tstr.w\tr9, [r7, #872]\t@ 0x368\n+\tstr.w\tr3, [r7, #864]\t@ 0x360\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tmov\tr1, sl\n-\tmov\tr0, fp\n+\tmov\tr2, r9\n+\tmov\tr1, fp\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tmov\tr0, fp\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, r5\n-\tmov\tr3, r6\n-\tadd.w\tr5, r7, #572\t@ 0x23c\n-\tadd.w\tr6, r7, #568\t@ 0x238\n-\tmov\tr0, r5\n-\tmov\tr1, r6\n+\tadd.w\tr4, r7, #796\t@ 0x31c\n+\tmov\tr3, r5\n+\tadd.w\tr5, r7, #792\t@ 0x318\n+\tmov\tr2, r6\n+\tmov\tr1, r5\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr.w\tr5, [r7, #572]\t@ 0x23c\n-\tadds\tr3, r5, #6\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tcmp\tr3, #1\n+\tldr.w\tr4, [r7, #796]\t@ 0x31c\n+\tadds\tr6, r4, #6\n+\tcmp\tr6, #1\n+\tmov\tr0, r6\n \tit\tcc\n-\tmovcc\tr3, #1\n-\tmov\tr0, r3\n+\tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr6, [r7, #568]\t@ 0x238\n-\tstrd\tr5, r6, [sp]\n+\tldr\tr3, [pc, #264]\t@ (b700 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c24>)\n+\tldr.w\tr5, [r7, #792]\t@ 0x318\n \tmov\tr1, r0\n-\tldr\tr3, [pc, #756]\t@ (b468 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d7c>)\n-\tmov\tfp, r0\n-\tmovs\tr2, #6\n-\tldr.w\tr0, [r7, #560]\t@ 0x230\n+\tmov\tr8, r0\n \tadd\tr3, pc\n+\tmovs\tr2, #6\n+\tmov\tr0, r6\n+\tstrd\tr4, r5, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tcmp\tr5, #0\n-\tvldr\td0, [r7, #544]\t@ 0x220\n-\tble.n\tb192 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2aa6>\n-\tmov\tr0, r6\n+\tcmp\tr4, #0\n+\tble.n\tb616 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b3a>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvldr\td0, [r7, #544]\t@ 0x220\n-\tadds\tr5, #32\n-\tvstr\td0, [r7, #544]\t@ 0x220\n-\tcmp\tr5, #1\n-\tmov\tr0, r5\n+\tadds\tr4, #32\n+\tcmp\tr4, #1\n+\tmov\tr0, r4\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #708]\t@ (b46c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d80>)\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tldr\tr3, [pc, #220]\t@ (b704 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c28>)\n+\tmov\tr5, r0\n+\tmov\tr2, r6\n \tmov\tr1, r0\n-\tmov\tr6, r0\n \tadd\tr3, pc\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #26\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, fp\n+\tmov\tr3, r8\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, fp\n+\tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #680]\t@ (b470 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2d84>)\n-\tmov\tr1, r5\n-\tmov\tr0, r6\n-\tldr.w\tr3, [r8, r3]\n+\tldr\tr3, [pc, #196]\t@ (b708 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c2c>)\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tmov\tr0, r5\n+\tmov\tr1, r4\n+\tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tmov\tr0, r6\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvldr\td0, [r7, #544]\t@ 0x220\n-\tb.w\t87be <__gridxc_gpfa_core_sp_MOD_gpfa_+0xd2>\n-\tsubs\tr5, r0, r4\n-\tnegs\tr2, r0\n-\tcmp\tr0, r4\n-\tudiv\tr2, r5, r2\n-\tbge.w\t8bb8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4cc>\n-\tb.w\t8fda <__gridxc_gpfa_core_sp_MOD_gpfa_+0x8ee>\n-\tldr.w\tr5, [r7, #296]\t@ 0x128\n-\trsb\tr1, r9, #0\n-\tcmp.w\tr8, #0\n-\tudiv\tr6, r5, r1\n-\tble.w\t8a1c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x330>\n-\tb.w\t8b96 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4aa>\n-\tldr.w\tr2, [r7, #552]\t@ 0x228\n-\tcmp\tr2, #0\n-\tble.w\taffc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2910>\n-\tadd.w\tr8, r2, r6\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n-\tadd.w\tr5, r6, #1073741824\t@ 0x40000000\n+\tb.w\t8bbe <__gridxc_gpfa_core_sp_MOD_gpfa_+0xe2>\n+\tnegs\tr1, r3\n+\tnegs\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tr8, r0\n+\tble.w\tb134 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2658>\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #668]\t@ 0x29c\n+\tcmp\tr3, r2\n+\tbne.w\tb0f6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x261a>\n+\tldr.w\tr3, [r7, #204]\t@ 0xcc\n+\tldr.w\tsl, [r7, #584]\t@ 0x248\n+\tldrd\tr5, r6, [r7, #704]\t@ 0x2c0\n+\tcmp\tr3, #5\n+\tldr.w\tr4, [r7, #576]\t@ 0x240\n+\tbne.w\tbfe8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x350c>\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tadds\tr4, #1\n+\tldr.w\tr2, [r7, #756]\t@ 0x2f4\n+\tldr.w\tr1, [r7, #208]\t@ 0xd0\n+\tmla\tr3, r1, r2, r3\n+\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tcmp\tr4, r3\n+\tbne.w\tb0a8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x25cc>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tcmp\tr3, #1\n+\tbne.w\te324 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5848>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tcmp\tr3, #1\n+\tbne.w\te26a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x578e>\n+\tldr.w\tsp, [r7, #500]\t@ 0x1f4\n+\tldr\tr2, [pc, #64]\t@ (b70c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c30>)\n+\tldr\tr3, [pc, #64]\t@ (b710 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2c34>)\n+\tadd\tr2, pc\n+\tldr\tr3, [r2, r3]\n+\tldr\tr2, [r3, #0]\n+\tldr.w\tr3, [r7, #1180]\t@ 0x49c\n+\teors\tr2, r3\n+\tmov.w\tr3, #0\n+\tbne.w\te7b4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5cd8>\n+\taddw\tr7, r7, #1188\t@ 0x4a4\n+\tmov\tsp, r7\n+\tvpop\t{d8-d15}\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\t.word\t0x00005000\n+\t.word\t0xffffffff\n+\t.word\t0x0000016a\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x0000015c\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x000000fe\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x000000d4\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x0000003a\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tcmp\tr3, #0\n+\tble.w\tb46e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2992>\n+\tadd.w\tr9, r3, r5\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tadd.w\tr4, r5, #1073741824\t@ 0x40000000\n+\tlsls\tr5, r5, #2\n+\tsubs\tr4, #1\n \tadd.w\tr0, r0, #1073741824\t@ 0x40000000\n+\tadd.w\tr3, r3, r9, lsl #2\n \tadd.w\tr1, r1, #1073741824\t@ 0x40000000\n-\tadd.w\tr3, r3, #1073741824\t@ 0x40000000\n-\tlsls\tr6, r6, #2\n+\tadd.w\tr2, r2, #1073741824\t@ 0x40000000\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tnegs\tr3, r5\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tlsls\tr4, r4, #2\n \tsubs\tr0, #1\n \tsubs\tr1, #1\n-\tsubs\tr3, #1\n-\tsubs\tr5, #1\n-\tadd.w\tr2, r2, r8, lsl #2\n-\tstr.w\tr2, [r7, #468]\t@ 0x1d4\n-\tnegs\tr2, r6\n-\tstr.w\tr2, [r7, #508]\t@ 0x1fc\n+\tsubs\tr2, #1\n+\tadds\tr5, r3, r4\n+\tstr.w\tr5, [r7, #784]\t@ 0x310\n \tlsls\tr0, r0, #2\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n \tlsls\tr1, r1, #2\n-\tlsls\tr3, r3, #2\n-\tlsls\tr5, r5, #2\n-\tadd.w\tr6, ip, r5\n-\tadd.w\tfp, ip, r0\n-\tadd\tr5, r2\n-\tadd\tr0, r2\n-\tadd.w\tsl, ip, r1\n-\tadd.w\tr8, ip, r3\n-\tadd\tr1, r2\n-\tadd\tr3, r2\n-\tstr.w\tip, [r7, #376]\t@ 0x178\n-\tlsls\tr2, r4, #2\n-\tstr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tvldr\ts7, [sl]\n-\tvldmia\tr6!, {s6}\n-\tvldr\ts13, [fp]\n-\tvcvt.f64.f32\td21, s7\n-\tvldr\ts7, [r8]\n-\tvldr\ts11, [r0]\n-\tvldmia\tr5!, {s10}\n-\tvcvt.f64.f32\td20, s13\n-\tvcvt.f64.f32\td18, s7\n+\tlsls\tr2, r2, #2\n+\tadd.w\tfp, r3, r0\n+\tadd.w\tsl, r3, r1\n+\tadd.w\tr9, r3, r2\n+\tadd\tr4, r5\n+\tadd\tr2, r5\n+\tadd\tr0, r5\n+\tadd\tr1, r5\n+\tmov.w\tr3, ip, lsl #2\n+\tldr.w\tr5, [r7, #784]\t@ 0x310\n+\tstr.w\tr3, [r7, #640]\t@ 0x280\n+\tstr.w\tr6, [r7, #548]\t@ 0x224\n+\tstr.w\tr2, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tvldmia\tr5!, {s8}\n+\tvldmia\tr4!, {s0}\n+\tldr.w\tr2, [r7, #640]\t@ 0x280\n+\tvldr\ts6, [r3]\n+\tvcvt.f64.f32\td4, s8\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts2, [r0]\n+\tvldr\ts4, [r1]\n+\tadds\tr6, r4, r3\n+\tadds\tr3, r5, r3\n \tvcvt.f64.f32\td3, s6\n-\tvldr\ts12, [r1]\n-\tvcvt.f64.f32\td17, s11\n-\tvldr\ts11, [r3]\n-\tvcvt.f64.f32\td19, s10\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tvsub.f64\td28, d21, d18\n-\tvsub.f64\td24, d3, d20\n+\tadd\tr3, r2\n+\tvcvt.f64.f32\td1, s2\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts11, [r9]\n+\tvldr\ts14, [fp]\n+\tadd\tr6, r2\n+\tvldr\ts18, [r3, #-4]\n+\tvldr\ts12, [sl]\n+\tvsub.f64\td11, d0, d1\n+\tvcvt.f64.f32\td8, s11\n+\tvcvt.f64.f32\td7, s14\n+\tvcvt.f64.f32\td10, s18\n+\tvadd.f64\td9, d1, d0\n \tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td16, s11\n-\tvadd.f64\td27, d17, d19\n-\tvsub.f64\td19, d19, d17\n-\tvadd.f64\td18, d18, d21\n-\tvadd.f64\td20, d20, d3\n-\tvmul.f64\td22, d8, d28\n-\tvmul.f64\td28, d1, d28\n-\tvadd.f64\td21, d16, d6\n-\tvsub.f64\td16, d6, d16\n-\tadd.w\tip, r5, r2\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tvadd.f64\td26, d18, d20\n-\tvsub.f64\td18, d20, d18\n-\tvmov.f64\td17, d22\n-\tadd\tip, r2\n-\tvfnms.f64\td17, d1, d24\n-\tvadd.f64\td23, d21, d27\n-\tvsub.f64\td21, d27, d21\n-\tvmov.f64\td20, d28\n-\tvmul.f64\td28, d8, d16\n-\tvldr\ts13, [ip, #-4]\n-\tvfma.f64\td20, d8, d24\n-\tvfma.f64\td22, d24, d12\n-\tvmul.f64\td24, d1, d16\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tvfma.f64\td24, d8, d19\n-\tvmov.f64\td29, d28\n-\tvfma.f64\td28, d12, d19\n-\tvfnms.f64\td29, d1, d19\n-\tvmov.f64\td27, d17\n-\tvcvt.f64.f32\td19, s13\n-\tvfma.f64\td27, d23, d25\n-\tvmov.f64\td16, d19\n-\tvfma.f64\td27, d10, d21\n-\tvfms.f64\td16, d23, d25\n-\tvsub.f64\td27, d27, d19\n-\tvadd.f64\td19, d19, d23\n-\tvmov.f64\td23, d16\n-\tvfma.f64\td16, d21, d11\n-\tvfma.f64\td23, d10, d21\n-\tvcvt.f32.f64\ts13, d19\n-\tvmul.f64\td27, d27, d14\n-\tvstr\ts13, [ip, #-4]\n-\tadd.w\tip, r6, r2\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n-\tvadd.f64\td17, d16, d17\n-\tvadd.f64\td16, d22, d16\n-\tvadd.f64\td6, d23, d20\n-\tadd\tip, r2\n-\tvsub.f64\td5, d20, d23\n-\tvsub.f64\td23, d23, d20\n-\tldr.w\tr2, [r7, #468]\t@ 0x1d4\n-\tvnmul.f64\td20, d15, d17\n-\tvmul.f64\td17, d17, d0\n-\tvldr\ts7, [ip, #-4]\n-\tvmul.f64\td21, d16, d2\n-\tvnmul.f64\td30, d31, d6\n-\tvmul.f64\td6, d6, d9\n-\tvmul.f64\td23, d23, d7\n-\tvmul.f64\td5, d5, d13\n-\tvcvt.f64.f32\td19, s7\n-\tcmp\tr6, r2\n-\tvmov.f64\td16, d19\n-\tvadd.f64\td19, d19, d26\n-\tvfms.f64\td16, d26, d25\n-\tvcvt.f32.f64\ts7, d19\n-\tvstr\ts7, [ip, #-4]\n-\tvmov.f64\td22, d16\n-\tvfma.f64\td16, d18, d11\n-\tvfma.f64\td22, d10, d18\n-\tvadd.f64\td28, d28, d16\n-\tvadd.f64\td16, d29, d16\n-\tvfma.f64\td27, d16, d2\n-\tvfma.f64\td21, d16, d14\n-\tvsub.f64\td16, d22, d24\n-\tvadd.f64\td22, d24, d22\n-\tvfma.f64\td20, d28, d0\n-\tvfma.f64\td17, d28, d15\n-\tvfma.f64\td6, d16, d31\n-\tvfma.f64\td23, d22, d13\n-\tvfma.f64\td30, d16, d9\n-\tvfma.f64\td5, d22, d7\n-\tvcvt.f32.f64\ts7, d20\n-\tvcvt.f32.f64\ts6, d17\n-\tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d23\n-\tvcvt.f32.f64\ts9, d30\n+\tvadd.f64\td1, d3, d2\n+\tvsub.f64\td3, d2, d3\n+\tvldr\ts10, [r6, #-4]\n+\tvadd.f64\td2, d1, d9\n+\tvcvt.f64.f32\td5, s10\n+\tvstr\td3, [r7, #712]\t@ 0x2c8\n+\tvadd.f64\td3, d7, d4\n+\tvsub.f64\td7, d4, d7\n+\tvadd.f64\td4, d8, d6\n+\tvsub.f64\td1, d9, d1\n+\tvsub.f64\td6, d6, d8\n+\tvmov.f64\td8, d10\n+\tvadd.f64\td0, d4, d3\n+\tvsub.f64\td3, d3, d4\n+\tvmul.f64\td4, d15, d7\n+\tvmul.f64\td7, d14, d7\n+\tvmla.f64\td7, d15, d6\n+\tvmul.f64\td6, d14, d6\n+\tvmul.f64\td1, d1, d13\n+\tvmul.f64\td9, d3, d13\n+\tvmul.f64\td3, d2, d12\n+\tvadd.f64\td2, d5, d2\n+\tvadd.f64\td10, d10, d0\n+\tvmls.f64\td8, d0, d12\n+\tvmul.f64\td0, d14, d11\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts20, d10\n+\tvstr\ts4, [r6, #-4]\n+\tvsub.f64\td2, d4, d6\n+\tvstr\ts20, [r3, #-4]\n+\tvsub.f64\td10, d6, d4\n+\tvsub.f64\td6, d5, d3\n+\tvadd.f64\td4, d3, d2\n+\tvadd.f64\td4, d4, d1\n+\tvsub.f64\td5, d4, d5\n+\tvldr\td4, [r7, #712]\t@ 0x2c8\n+\tvmul.f64\td3, d14, d4\n+\tvmla.f64\td0, d15, d4\n+\tvstr\td5, [r7, #688]\t@ 0x2b0\n+\tvadd.f64\td4, d6, d1\n+\tvmul.f64\td5, d15, d11\n+\tvsub.f64\td6, d6, d1\n+\tvldr\td11, [r7, #488]\t@ 0x1e8\n+\tvadd.f64\td1, d6, d2\n+\tvadd.f64\td10, d10, d6\n+\tvsub.f64\td2, d3, d5\n+\tvadd.f64\td6, d8, d9\n+\tvsub.f64\td5, d5, d3\n+\tvsub.f64\td8, d8, d9\n+\tvldr\td9, [r7, #456]\t@ 0x1c8\n+\tvadd.f64\td3, d4, d7\n+\tvadd.f64\td2, d2, d8\n+\tvadd.f64\td8, d5, d8\n+\tvsub.f64\td5, d6, d0\n+\tvadd.f64\td0, d0, d6\n+\tvsub.f64\td6, d7, d4\n+\tvsub.f64\td4, d4, d7\n+\tvmul.f64\td7, d1, d9\n+\tvnmls.f64\td7, d2, d11\n+\tvmul.f64\td2, d2, d9\n+\tvldr\td9, [r7, #464]\t@ 0x1d0\n+\tvmla.f64\td2, d1, d11\n+\tvldr\td11, [r7, #776]\t@ 0x308\n+\tvmul.f64\td1, d3, d9\n+\tvnmls.f64\td1, d5, d11\n+\tvmul.f64\td5, d5, d9\n+\tvmla.f64\td5, d3, d11\n+\tvldr\td3, [r7, #472]\t@ 0x1d8\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts2, d1\n \tvcvt.f32.f64\ts10, d5\n-\tvmov.f32\ts8, s6\n-\tvstr\ts7, [r7, #488]\t@ 0x1e8\n-\tvcvt.f32.f64\ts6, d27\n-\tvcvt.f32.f64\ts7, d21\n-\tvstr\ts12, [r5, #-4]\n-\tvstmia\tr0!, {s13}\n-\tvldr\ts13, [r7, #488]\t@ 0x1e8\n-\tvstr\ts9, [r6, #-4]\n-\tvstmia\tr1!, {s8}\n+\tvstr\ts2, [r5, #-4]\n+\tvldr\td1, [r7, #440]\t@ 0x1b8\n+\tvstr\ts10, [r4, #-4]\n+\tvmul.f64\td5, d0, d3\n+\tvmul.f64\td0, d0, d1\n+\tvmla.f64\td5, d6, d1\n+\tvmla.f64\td0, d4, d3\n+\tvldr\td6, [r7, #480]\t@ 0x1e0\n+\tvldr\td4, [r7, #688]\t@ 0x2b0\n+\tvcvt.f32.f64\ts10, d5\n+\tvcvt.f32.f64\ts0, d0\n \tvstmia\tfp!, {s10}\n-\tvstmia\tr3!, {s7}\n-\tvstmia\tsl!, {s13}\n-\tvstmia\tr8!, {s6}\n-\tbne.w\tb272 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b86>\n-\tldr.w\tip, [r7, #376]\t@ 0x178\n-\tb.n\taffc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2910>\n-\tnop\n-\tnop.w\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x0000036e\n- R_ARM_REL32\t.LC0\n-\t.word\t0x0000035c\n- R_ARM_REL32\t.LC1\n-\t.word\t0x000002ea\n- R_ARM_REL32\t.LC2\n-\t.word\t0x000002ba\n- R_ARM_REL32\t.LC3\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\tldr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tmul.w\tr6, r4, r3\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n-\tlsls\tr4, r0, #4\n-\trsb\tr9, r5, #0\n-\tmov\tsl, r5\n-\tmovs\tr5, #0\n-\tstr.w\tr5, [r7, #536]\t@ 0x218\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n-\tadds\tr3, #8\n-\tstr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tmov\tlr, r3\n-\tlsls\tr4, r0, #5\n-\tadds\tr5, #1\n-\tlsls\tr0, r0, #6\n-\tstr.w\tr4, [r7, #468]\t@ 0x1d4\n-\tstr.w\tr0, [r7, #456]\t@ 0x1c8\n-\tmov\tr4, r3\n-\tstr.w\tr5, [r7, #492]\t@ 0x1ec\n-\tmov\tr0, r3\n-\tldr\tr5, [r7, #84]\t@ 0x54\n-\tmov\tip, fp\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tstr.w\tr6, [r7, #464]\t@ 0x1d0\n+\tvstmia\tr0!, {s0}\n+\tvstmia\tsl!, {s14}\n+\tvmul.f64\td7, d8, d6\n+\tvstmia\tr1!, {s4}\n+\tvldr\td5, [r7, #448]\t@ 0x1c0\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tvmul.f64\td8, d8, d5\n+\tvmla.f64\td7, d4, d5\n+\tvmla.f64\td8, d10, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts16, d8\n+\tvstmia\tr9!, {s14}\n+\tvstmia\tr3!, {s16}\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tcmp\tr5, r3\n+\tbne.w\tb78a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2cae>\n+\tldr.w\tr6, [r7, #548]\t@ 0x224\n+\tb.n\tb46e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2992>\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tldr.w\tfp, [r7, #68]\t@ 0x44\n+\tadd.w\tr4, r3, #8\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tmov\tr6, r4\n+\tnegs\tr2, r3\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tmov\tr5, r4\n+\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tmov.w\tr2, sl, lsl #4\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tmov.w\tr2, sl, lsl #5\n+\tstr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tmov.w\tr2, sl, lsl #6\n+\tmov\tsl, r4\n+\tadds\tr3, #1\n+\tstr.w\tr2, [r7, #640]\t@ 0x280\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tcmp.w\tr9, #0\n+\tblt.w\tbd80 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x32a4>\n+\tmov\tr1, r9\n+\tldr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tmov\tr3, r0\n+\tcmp\tr2, r1\n+\tblt.w\tbcd2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x31f6>\n+\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n \tcmp\tr2, #0\n-\tblt.w\tb834 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3148>\n-\tudiv\tr5, sl, r2\n-\tldr.w\tr6, [r7, #536]\t@ 0x218\n-\tstr.w\tr5, [r7, #556]\t@ 0x22c\n-\tldr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tcmp\tr5, r6\n-\tblt.w\tb7c4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x30d8>\n-\tldr.w\tr5, [r7, #364]\t@ 0x16c\n-\tcmp\tr5, #0\n-\tble.w\tb7c4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x30d8>\n-\tldr.w\tr6, [r7, #516]\t@ 0x204\n-\tvmov.f64\td23, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n-\tstr.w\tr4, [r7, #420]\t@ 0x1a4\n-\tadd.w\tfp, r6, r5\n-\tldr.w\tr5, [r7, #364]\t@ 0x16c\n-\tldr.w\tr6, [r7, #556]\t@ 0x22c\n-\tmov\tr4, fp\n-\tadds\tr5, #1\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tstr.w\tr1, [r7, #428]\t@ 0x1ac\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tstr.w\tr4, [r7, #556]\t@ 0x22c\n+\tble.w\tbcd2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x31f6>\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr4, [r7, #624]\t@ 0x270\n+\tstr.w\tsl, [r7, #608]\t@ 0x260\n+\tadd\tr2, r1\n+\tldr.w\tr4, [r7, #704]\t@ 0x2c0\n+\tldr.w\tsl, [r7, #708]\t@ 0x2c4\n+\tstr.w\tr5, [r7, #616]\t@ 0x268\n+\tmov\tr5, r3\n \tmovs\tr3, #1\n-\tstr.w\tr4, [r7, #396]\t@ 0x18c\n-\tldr.w\tr4, [r7, #496]\t@ 0x1f0\n-\tstr.w\tr3, [r7, #484]\t@ 0x1e4\n-\tstrd\tr8, r6, [r7, #404]\t@ 0x194\n-\tstr.w\tr2, [r7, #400]\t@ 0x190\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tstrd\tr0, lr, [r7, #388]\t@ 0x184\n-\tstr.w\tr9, [r7, #384]\t@ 0x180\n-\tstr.w\tsl, [r7, #376]\t@ 0x178\n-\tldrd\tr2, r3, [r7, #556]\t@ 0x22c\n+\tstr.w\tr2, [r7, #768]\t@ 0x300\n+\tstr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tstr.w\tr8, [r7, #600]\t@ 0x258\n+\tstr.w\tr5, [r7, #592]\t@ 0x250\n+\tstr.w\tr9, [r7, #568]\t@ 0x238\n+\tstr.w\tr2, [r7, #560]\t@ 0x230\n+\tstr.w\tr6, [r7, #552]\t@ 0x228\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n+\tldr.w\tr0, [r7, #748]\t@ 0x2ec\n \tadds\tr1, r3, r2\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tldr.w\tr5, [r7, #748]\t@ 0x2ec\n \tcmp\tr1, r3\n-\tbge.n\tb550 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e64>\n-\tldr.w\tr3, [r7, #524]\t@ 0x20c\n-\tadd\tr1, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #752]\t@ 0x2f0\n+\taddlt\tr1, r1, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tadds\tr2, r3, r1\n-\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n \tcmp\tr2, r3\n-\tbge.n\tb564 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e78>\n-\tldr.w\tr3, [r7, #524]\t@ 0x20c\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #752]\t@ 0x2f0\n+\taddlt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tadd\tr3, r2\n \tcmp\tr3, r0\n-\tbge.n\tb578 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e8c>\n-\tldr.w\tr0, [r7, #524]\t@ 0x20c\n-\tadd\tr3, r0\n-\tldr.w\tr0, [r7, #560]\t@ 0x230\n-\tldr.w\tr5, [r7, #516]\t@ 0x204\n+\titt\tlt\n+\tldrlt.w\tr0, [r7, #752]\t@ 0x2f0\n+\taddlt\tr3, r3, r0\n+\tldr.w\tr0, [r7, #788]\t@ 0x314\n \tadd\tr0, r3\n \tcmp\tr0, r5\n-\tbge.n\tb58c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2ea0>\n-\tldr.w\tr6, [r7, #524]\t@ 0x20c\n-\tadd\tr0, r6\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\titt\tlt\n+\tldrlt.w\tr5, [r7, #752]\t@ 0x2f0\n+\taddlt\tr0, r0, r5\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n \tcmp\tr5, #0\n-\tbne.w\tb850 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3164>\n-\tldr.w\tr6, [r7, #552]\t@ 0x228\n-\tcmp\tr6, #0\n-\tble.w\tb766 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x307a>\n-\tldr.w\tr6, [r7, #556]\t@ 0x22c\n+\tbne.w\tbd9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x32c2>\n+\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n+\tcmp\tr5, #0\n+\tble.w\tbc74 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3198>\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n \tlsls\tr1, r1, #2\n \tlsls\tr0, r0, #2\n \tlsls\tr2, r2, #2\n-\tmovs\tr5, #1\n-\tstr.w\tr5, [r7, #508]\t@ 0x1fc\n-\tlsls\tr6, r6, #2\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n \tlsls\tr3, r3, #2\n-\tadd.w\tfp, ip, r1\n-\tadd.w\tsl, ip, r0\n-\tadd.w\tr9, ip, r2\n-\tadd.w\tlr, ip, r6\n+\tadd.w\tr9, sl, r1\n+\tlsls\tr5, r5, #2\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tlr, sl, r2\n+\tadd.w\tr6, sl, r5\n \tadd\tr1, r4\n \tadd\tr0, r4\n \tadd\tr2, r4\n-\tadd\tr6, r4\n-\tadd.w\tr8, ip, r3\n-\tstr.w\tr4, [r7, #488]\t@ 0x1e8\n+\tadd\tr5, r4\n+\tadd.w\tip, sl, r3\n+\tstr.w\tr4, [r7, #688]\t@ 0x2b0\n \tadd\tr3, r4\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tvldr\ts11, [fp, #-4]\n-\tvldr\ts6, [r9, #-4]\n-\tvldr\ts13, [r8, #-4]\n-\tvcvt.f64.f32\td19, s11\n-\tvldr\ts11, [sl, #-4]\n-\tvcvt.f64.f32\td24, s6\n-\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tvcvt.f64.f32\td25, s13\n-\tvldr\ts6, [lr, #-4]\n-\tvcvt.f64.f32\td20, s11\n-\tvldr\ts13, [r2, #-4]\n-\tvldr\ts7, [r1, #-4]\n-\tvldr\ts12, [r3, #-4]\n-\tvadd.f64\td21, d24, d25\n-\tvsub.f64\td24, d24, d25\n-\tvadd.f64\td22, d19, d20\n-\tvcvt.f64.f32\td25, s6\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tmovs\tr3, #1\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tvldr\ts0, [r9, #-4]\n+\tvldr\ts2, [r8, #-4]\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts17, [r6, #-4]\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts16, [r5, #-4]\n+\tvldr\ts4, [lr, #-4]\n+\tvldr\ts6, [ip, #-4]\n+\tvcvt.f64.f32\td9, s17\n+\tvldr\ts8, [r1, #-4]\n+\tvcvt.f64.f32\td10, s16\n \tvldr\ts10, [r0, #-4]\n-\tvsub.f64\td19, d19, d20\n-\tvcvt.f64.f32\td16, s13\n-\tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td18, s7\n-\tvmul.f64\td29, d24, d8\n-\tvadd.f64\td20, d22, d21\n+\tvadd.f64\td8, d0, d1\n+\tvldr\ts12, [r2, #-4]\n+\tvsub.f64\td0, d0, d1\n+\tvldr\ts14, [r3, #-4]\n+\tvcvt.f64.f32\td3, s6\n+\tvcvt.f64.f32\td4, s8\n \tvcvt.f64.f32\td5, s10\n-\tvmov.f64\td17, d25\n-\tvldr\ts7, [r6, #-4]\n-\tvadd.f64\td28, d16, d6\n-\tvsub.f64\td16, d16, d6\n-\tvsub.f64\td22, d22, d21\n-\tvmul.f64\td30, d24, d1\n-\tvfms.f64\td17, d20, d23\n-\tvadd.f64\td21, d18, d5\n-\tvcvt.f64.f32\td24, s7\n-\tvsub.f64\td18, d18, d5\n-\tvmul.f64\td27, d8, d16\n-\tvmov.f64\td6, d29\n-\tvfma.f64\td30, d19, d8\n-\tvfnms.f64\td6, d19, d1\n-\tvfms.f64\td29, d19, d1\n-\tvadd.f64\td19, d21, d28\n-\tvmul.f64\td16, d1, d16\n-\tvsub.f64\td21, d21, d28\n-\tvfma.f64\td16, d8, d18\n-\tvadd.f64\td20, d20, d25\n-\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n-\tvmov.f64\td26, d17\n-\tvfms.f64\td17, d22, d10\n-\tvfma.f64\td26, d22, d10\n-\tvmov.f64\td22, d27\n-\tvfnms.f64\td22, d1, d18\n-\tvfma.f64\td27, d18, d12\n-\tvmov.f64\td18, d24\n-\tvcvt.f32.f64\ts11, d20\n-\tvfms.f64\td18, d19, d23\n-\tvadd.f64\td19, d19, d24\n+\tvcvt.f64.f32\td6, s12\n+\tvcvt.f64.f32\td2, s4\n+\tvcvt.f64.f32\td7, s14\n+\tldr.w\tr4, [r7, #784]\t@ 0x310\n+\tvsub.f64\td11, d4, d5\n \tadds\tr4, #1\n-\tstr.w\tr4, [r7, #508]\t@ 0x1fc\n-\tvstr\ts11, [lr, #-4]\n-\tadd\tlr, r5\n-\tvcvt.f32.f64\ts10, d19\n-\tvsub.f64\td3, d26, d16\n-\tvadd.f64\td16, d26, d16\n-\tvadd.f64\td22, d17, d22\n-\tvadd.f64\td17, d17, d27\n-\tvmov.f64\td24, d18\n-\tvfma.f64\td18, d21, d11\n-\tvfma.f64\td24, d10, d21\n-\tvstr\ts10, [r6, #-4]\n+\tvadd.f64\td1, d2, d3\n+\tvsub.f64\td2, d2, d3\n+\tvadd.f64\td3, d4, d5\n+\tvadd.f64\td5, d6, d7\n+\tvsub.f64\td4, d6, d7\n+\tvmul.f64\td7, d0, d15\n+\tstr.w\tr4, [r7, #784]\t@ 0x310\n+\tvadd.f64\td6, d3, d5\n+\tvsub.f64\td3, d3, d5\n+\tvmov.f64\td12, d7\n+\tvadd.f64\td7, d8, d1\n+\tvsub.f64\td1, d8, d1\n+\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n+\tvmov.f64\td5, d9\n+\tvmul.f64\td3, d3, d13\n+\tvmls.f64\td5, d7, d8\n+\tvadd.f64\td7, d7, d9\n+\tvmul.f64\td1, d1, d13\n+\tvcvt.f32.f64\ts14, d7\n+\tvstr\ts14, [r6, #-4]\n+\tvmov.f64\td7, d10\n+\tvmls.f64\td7, d6, d8\n+\tvadd.f64\td6, d6, d10\n+\tvmul.f64\td8, d2, d15\n+\tvmul.f64\td2, d2, d14\n+\tvmla.f64\td8, d0, d14\n+\tvmul.f64\td0, d15, d4\n+\tvmla.f64\td0, d14, d11\n+\tvmul.f64\td4, d14, d4\n+\tvcvt.f32.f64\ts12, d6\n+\tvmul.f64\td11, d15, d11\n+\tadd\tr6, fp\n+\tvstr\ts12, [r5, #-4]\n+\tvsub.f64\td9, d4, d11\n+\tvadd.f64\td6, d1, d5\n+\tvsub.f64\td11, d11, d4\n+\tvsub.f64\td5, d5, d1\n+\tvadd.f64\td1, d3, d7\n+\tvsub.f64\td7, d7, d3\n+\tvsub.f64\td3, d12, d2\n+\tvsub.f64\td2, d2, d12\n+\tadd\tr5, fp\n+\tvadd.f64\td9, d9, d5\n+\tvadd.f64\td3, d3, d7\n+\tvadd.f64\td2, d2, d7\n+\tvadd.f64\td7, d11, d5\n+\tvsub.f64\td5, d6, d0\n+\tvadd.f64\td6, d6, d0\n+\tvcvt.f32.f64\ts18, d9\n \tvcvt.f32.f64\ts6, d3\n-\tvcvt.f32.f64\ts11, d22\n-\tvcvt.f32.f64\ts7, d16\n-\tvcvt.f32.f64\ts10, d17\n-\tadd\tr6, r5\n-\tvstr\ts6, [fp, #-4]\n-\tadd\tfp, r5\n-\tvstr\ts7, [sl, #-4]\n-\tadd\tsl, r5\n-\tvadd.f64\td6, d6, d18\n-\tvadd.f64\td18, d18, d29\n-\tvadd.f64\td16, d30, d24\n-\tvsub.f64\td24, d24, d30\n-\tvstr\ts10, [r9, #-4]\n-\tadd\tr9, r5\n-\tvstr\ts11, [r8, #-4]\n-\tadd\tr8, r5\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts10, d5\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d18\n-\tvcvt.f32.f64\ts10, d16\n-\tvcvt.f32.f64\ts11, d24\n-\tvstr\ts10, [r1, #-4]\n-\tadd\tr1, r5\n-\tvstr\ts11, [r0, #-4]\n-\tadd\tr0, r5\n-\tvstr\ts12, [r2, #-4]\n-\tadd\tr2, r5\n-\tvstr\ts13, [r3, #-4]\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tvstr\ts10, [r9, #-4]\n+\tadd\tr9, fp\n+\tvstr\ts12, [r8, #-4]\n+\tadd\tr8, fp\n+\tvstr\ts18, [lr, #-4]\n+\tadd\tlr, fp\n+\tvstr\ts14, [ip, #-4]\n+\tvadd.f64\td7, d8, d1\n+\tvsub.f64\td1, d1, d8\n+\tadd\tip, fp\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts2, d1\n+\tvstr\ts14, [r1, #-4]\n+\tadd\tr1, fp\n+\tvstr\ts2, [r0, #-4]\n+\tadd\tr0, fp\n+\tvstr\ts6, [r2, #-4]\n+\tadd\tr2, fp\n+\tvstr\ts4, [r3, #-4]\n+\tadd\tr3, fp\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n \tcmp\tr4, r3\n-\tbne.w\tb5de <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2ef2>\n-\tldr.w\tr4, [r7, #488]\t@ 0x1e8\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tldr.w\tr2, [r7, #380]\t@ 0x17c\n+\tbne.w\tbae8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x300c>\n+\tldr.w\tr4, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #516]\t@ 0x204\n-\tstr.w\tr3, [r7, #556]\t@ 0x22c\n+\tldr.w\tr2, [r7, #748]\t@ 0x2ec\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n \tcmp\tr2, r3\n-\tble.n\tb786 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x309a>\n-\tldr.w\tr2, [r7, #524]\t@ 0x20c\n+\tble.n\tbc94 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x31b8>\n+\tldr.w\tr2, [r7, #752]\t@ 0x2f0\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #556]\t@ 0x22c\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr3, [r7, #684]\t@ 0x2ac\n \tcmp\tr3, r2\n-\tbne.w\tb53c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e50>\n-\tldrd\tr8, r6, [r7, #404]\t@ 0x194\n-\tldrd\tlr, r4, [r7, #392]\t@ 0x188\n-\tsubs\tr6, #1\n-\tldr.w\tr2, [r7, #400]\t@ 0x190\n-\tadds\tr1, r6, #1\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tldrd\tr9, r0, [r7, #384]\t@ 0x180\n-\tadd\tr4, r2\n-\tldr.w\tsl, [r7, #376]\t@ 0x178\n-\tbne.w\tb512 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2e26>\n-\tldrd\tr3, r1, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr4, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n-\tsubs\tr1, #1\n-\tldr.w\tr6, [r7, #536]\t@ 0x218\n-\tadd\tr9, r8\n-\tadd\tr3, r5\n-\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n-\tadd\tr6, r8\n-\tsub.w\tsl, sl, r8\n-\tadd\tlr, r5\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr6, [r7, #536]\t@ 0x218\n-\tadd\tr4, r5\n-\tldr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tadd\tr0, r5\n-\tadds\tr5, r1, #1\n-\tbeq.w\tbabe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33d2>\n-\tcmp\tr6, #0\n-\tble.w\tb4bc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2dd0>\n-\tvldr\td16, [r7, #448]\t@ 0x1c0\n-\tcmp\tr2, #0\n-\tvldr\td31, [r3]\n-\tvldr\td15, [lr]\n-\tvldr\td14, [r4]\n-\tvldr\td13, [r0]\n-\tvmul.f64\td31, d16, d31\n-\tvmul.f64\td15, d16, d15\n-\tvldr\td9, [r3, #-8]\n-\tvmul.f64\td14, d16, d14\n-\tvldr\td0, [lr, #-8]\n-\tvmul.f64\td13, d16, d13\n-\tvldr\td2, [r4, #-8]\n-\tvldr\td7, [r0, #-8]\n-\tbge.w\tb4c2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2dd6>\n-\tldr.w\tr5, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr6, [r7, #536]\t@ 0x218\n-\tudiv\tr5, r9, r5\n-\tstr.w\tr5, [r7, #556]\t@ 0x22c\n-\tldr.w\tr5, [r7, #440]\t@ 0x1b8\n-\tcmp\tr5, r6\n-\tble.w\tb4d8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2dec>\n-\tb.n\tb7c4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x30d8>\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n+\tbne.w\tba46 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2f6a>\n+\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\tldr.w\tr9, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tsubs\tr5, #1\n+\tldr.w\tr8, [r7, #600]\t@ 0x258\n+\tadds\tr1, r5, #1\n+\tldr.w\tr6, [r7, #552]\t@ 0x228\n+\tadd\tr2, r9\n+\tbne.w\tba28 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2f4c>\n+\tldr.w\tr4, [r7, #624]\t@ 0x270\n+\tldr.w\tr5, [r7, #616]\t@ 0x268\n+\tldr.w\tsl, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tadd\tr2, r3\n+\tstr.w\tr2, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tadd\tr2, r3\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tsub.w\tr3, r2, r3\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tadd\tr4, r3\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tadd\tr5, r3\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tadd\tr6, r3\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tadd\tsl, r3\n+\tbeq.w\tb66c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2b90>\n+\tldr.w\tr3, [r7, #760]\t@ 0x2f8\n+\tcmp\tr3, #0\n+\tble.w\tb9dc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2f00>\n+\tvldr\td5, [r4, #-8]\n+\tcmp.w\tr9, #0\n+\tvldr\td7, [r5]\n+\tvldr\td6, [r4]\n+\tvstr\td5, [r7, #776]\t@ 0x308\n+\tvldr\td5, [r7, #192]\t@ 0xc0\n+\tvmul.f64\td7, d5, d7\n+\tvmul.f64\td6, d5, d6\n+\tvstr\td7, [r7, #456]\t@ 0x1c8\n+\tvldr\td7, [r6]\n+\tvstr\td6, [r7, #464]\t@ 0x1d0\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [r7, #448]\t@ 0x1c0\n+\tvldr\td7, [sl]\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvldr\td7, [r5, #-8]\n+\tvstr\td7, [r7, #488]\t@ 0x1e8\n+\tvldr\td7, [r6, #-8]\n+\tvstr\td7, [r7, #480]\t@ 0x1e0\n+\tvldr\td7, [sl, #-8]\n+\tvstr\td7, [r7, #472]\t@ 0x1d8\n+\tbge.w\tb9e4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2f08>\n+\tldr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr0, [r7, #700]\t@ 0x2bc\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n+\tldr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tmov\tr3, r0\n+\tcmp\tr2, r1\n+\tble.w\tb9fe <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2f22>\n+\tb.n\tbcd2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x31f6>\n+\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n \tcmp\tr5, #0\n-\tble.n\tb766 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x307a>\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n+\tble.w\tbc74 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3198>\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n \tlsls\tr1, r1, #2\n \tlsls\tr0, r0, #2\n \tlsls\tr2, r2, #2\n \tlsls\tr3, r3, #2\n-\tadd.w\tfp, ip, r1\n-\tlsls\tr6, r5, #2\n-\tadd.w\tsl, ip, r0\n-\tadd.w\tr9, ip, r2\n-\tadd.w\tlr, ip, r6\n+\tadd.w\tr9, sl, r1\n+\tlsls\tr5, r5, #2\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tlr, sl, r2\n+\tadd.w\tr6, sl, r5\n \tadd\tr1, r4\n \tadd\tr0, r4\n \tadd\tr2, r4\n-\tadd\tr6, r4\n-\tmovs\tr5, #1\n-\tadd.w\tr8, ip, r3\n-\tstr.w\tr5, [r7, #508]\t@ 0x1fc\n+\tadd\tr5, r4\n+\tadd.w\tip, sl, r3\n+\tstr.w\tr4, [r7, #688]\t@ 0x2b0\n \tadd\tr3, r4\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tstr.w\tr4, [r7, #500]\t@ 0x1f4\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tvldr\ts9, [r9, #-4]\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n-\tvldr\ts6, [fp, #-4]\n-\tvcvt.f64.f32\td18, s9\n-\tvldr\ts9, [r8, #-4]\n-\tvldr\ts13, [sl, #-4]\n-\tvldr\ts10, [r0, #-4]\n-\tvcvt.f64.f32\td21, s6\n-\tvcvt.f64.f32\td17, s9\n-\tvldr\ts11, [r2, #-4]\n-\tvldr\ts12, [r3, #-4]\n-\tvcvt.f64.f32\td24, s13\n-\tvldr\ts7, [r1, #-4]\n-\tvcvt.f64.f32\td19, s10\n-\tvcvt.f64.f32\td16, s11\n-\tvldr\ts6, [lr, #-4]\n-\tvsub.f64\td29, d18, d17\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tmovs\tr3, #1\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tvldr\ts0, [r1, #-4]\n+\tvldr\ts2, [r0, #-4]\n+\tvldr\ts4, [r2, #-4]\n+\tvldr\ts6, [r3, #-4]\n+\tvcvt.f64.f32\td0, s0\n+\tvcvt.f64.f32\td1, s2\n+\tvldr\ts11, [ip, #-4]\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts18, [r6, #-4]\n+\tvcvt.f64.f32\td3, s6\n+\tvldr\ts8, [r9, #-4]\n+\tvldr\ts12, [r8, #-4]\n+\tvcvt.f64.f32\td8, s11\n+\tvldr\ts14, [lr, #-4]\n+\tvsub.f64\td11, d0, d1\n+\tvcvt.f64.f32\td10, s18\n+\tvcvt.f64.f32\td4, s8\n+\tvadd.f64\td9, d0, d1\n \tvcvt.f64.f32\td6, s12\n-\tvsub.f64\td26, d21, d24\n-\tvcvt.f64.f32\td20, s7\n-\tvadd.f64\td21, d21, d24\n-\tvadd.f64\td18, d18, d17\n-\tvldr\ts7, [r6, #-4]\n-\tvcvt.f64.f32\td25, s6\n-\tvmul.f64\td5, d8, d29\n-\tvadd.f64\td24, d16, d6\n-\tvsub.f64\td16, d16, d6\n-\tvmul.f64\td29, d1, d29\n-\tvadd.f64\td27, d20, d19\n-\tvadd.f64\td22, d21, d18\n-\tvsub.f64\td20, d20, d19\n-\tvcvt.f64.f32\td19, s7\n-\tvmov.f64\td17, d5\n-\tvfma.f64\td5, d26, d12\n-\tvfnms.f64\td17, d1, d26\n-\tvmul.f64\td30, d8, d16\n-\tvmov.f64\td28, d29\n-\tvsub.f64\td18, d21, d18\n-\tvfma.f64\td28, d8, d26\n-\tvadd.f64\td26, d27, d24\n-\tvmov.f64\td21, d25\n-\tvmul.f64\td16, d1, d16\n-\tvmov.f64\td6, d30\n-\tvfma.f64\td16, d8, d20\n-\tvfnms.f64\td6, d1, d20\n-\tvfms.f64\td21, d22, d23\n-\tvfma.f64\td30, d20, d12\n-\tvmov.f64\td20, d19\n-\tvfms.f64\td20, d26, d23\n-\tvsub.f64\td24, d27, d24\n-\tvmov.f64\td29, d17\n-\tldr.w\tr4, [r7, #508]\t@ 0x1fc\n-\tvfma.f64\td29, d26, d23\n-\tvadd.f64\td26, d26, d19\n+\tvadd.f64\td1, d2, d3\n+\tvcvt.f64.f32\td7, s14\n+\tvsub.f64\td3, d2, d3\n+\tvmul.f64\td2, d15, d11\n+\tvldr\ts10, [r5, #-4]\n+\tldr.w\tr4, [r7, #784]\t@ 0x310\n+\tvstr\td3, [r7, #720]\t@ 0x2d0\n+\tvadd.f64\td3, d4, d6\n+\tvsub.f64\td6, d4, d6\n+\tvadd.f64\td4, d7, d8\n+\tvsub.f64\td7, d7, d8\n+\tvcvt.f64.f32\td5, s10\n+\tvmov.f64\td12, d2\n+\tvadd.f64\td2, d9, d1\n+\tvsub.f64\td1, d9, d1\n+\tvmov.f64\td8, d10\n+\tvadd.f64\td0, d3, d4\n+\tvsub.f64\td3, d3, d4\n+\tvmul.f64\td4, d14, d7\n+\tvmul.f64\td7, d15, d7\n+\tvmla.f64\td7, d14, d6\n \tadds\tr4, #1\n-\tvadd.f64\td22, d22, d25\n-\tstr.w\tr4, [r7, #508]\t@ 0x1fc\n-\tvmov.f64\td27, d21\n-\tvfma.f64\td21, d18, d11\n-\tvfma.f64\td27, d10, d18\n-\tvmov.f64\td18, d20\n-\tvcvt.f32.f64\ts7, d22\n-\tvfma.f64\td18, d10, d24\n-\tvfma.f64\td20, d24, d11\n-\tvsub.f64\td19, d29, d19\n-\tvfma.f64\td19, d10, d24\n-\tvstr\ts7, [lr, #-4]\n-\tadd\tlr, r5\n-\tvadd.f64\td30, d21, d30\n-\tvadd.f64\td21, d21, d6\n-\tvcvt.f32.f64\ts13, d26\n-\tvadd.f64\td17, d17, d20\n-\tvsub.f64\td24, d28, d18\n-\tvadd.f64\td20, d20, d5\n-\tvmov.f64\td22, d19\n-\tvsub.f64\td19, d27, d16\n-\tvadd.f64\td27, d27, d16\n-\tvadd.f64\td16, d28, d18\n-\tvstr\ts13, [r6, #-4]\n-\tvsub.f64\td18, d18, d28\n-\tvmul.f64\td20, d20, d2\n-\tvmul.f64\td24, d24, d13\n-\tvmul.f64\td6, d22, d14\n-\tvnmul.f64\td22, d15, d17\n-\tvnmul.f64\td25, d31, d16\n-\tvfma.f64\td6, d21, d2\n-\tvfma.f64\td25, d19, d9\n-\tvmul.f64\td16, d9, d16\n-\tvfma.f64\td16, d19, d31\n-\tvmul.f64\td18, d18, d7\n-\tvmul.f64\td17, d0, d17\n-\tvfma.f64\td18, d27, d13\n-\tvfma.f64\td17, d30, d15\n-\tvfma.f64\td20, d21, d14\n-\tvfma.f64\td24, d27, d7\n-\tvfma.f64\td22, d30, d0\n-\tadd\tr6, r5\n+\tvmul.f64\td1, d1, d13\n+\tstr.w\tr4, [r7, #784]\t@ 0x310\n+\tvmul.f64\td9, d3, d13\n+\tvmul.f64\td3, d15, d6\n+\tvmov.f64\td6, #80\t@ 0x3e800000 0.250\n+\tvmul.f64\td6, d2, d6\n+\tvadd.f64\td2, d2, d5\n+\tvcvt.f32.f64\ts4, d2\n+\tvstr\ts4, [r5, #-4]\n+\tvmov.f64\td2, #80\t@ 0x3e800000 0.250\n+\tadd\tr5, fp\n+\tvmls.f64\td8, d0, d2\n+\tvadd.f64\td0, d0, d10\n+\tvsub.f64\td2, d3, d4\n+\tvcvt.f32.f64\ts0, d0\n+\tvstr\ts0, [r6, #-4]\n+\tvsub.f64\td0, d4, d3\n+\tvsub.f64\td4, d5, d6\n+\tvadd.f64\td6, d2, d6\n+\tadd\tr6, fp\n+\tvsub.f64\td6, d6, d5\n+\tvadd.f64\td5, d1, d4\n+\tvsub.f64\td4, d4, d1\n+\tvadd.f64\td10, d6, d1\n+\tvldr\td6, [r7, #720]\t@ 0x2d0\n+\tvadd.f64\td1, d2, d4\n+\tvadd.f64\td2, d7, d5\n+\tvmul.f64\td3, d15, d6\n+\tvmul.f64\td6, d14, d6\n+\tvmla.f64\td3, d14, d11\n+\tvadd.f64\td11, d0, d4\n+\tvadd.f64\td4, d9, d8\n+\tvsub.f64\td8, d8, d9\n+\tvldr\td0, [r7, #456]\t@ 0x1c8\n+\tvsub.f64\td9, d12, d6\n+\tvsub.f64\td6, d6, d12\n+\tvldr\td12, [r7, #488]\t@ 0x1e8\n+\tvadd.f64\td9, d9, d8\n+\tvadd.f64\td8, d6, d8\n+\tvadd.f64\td6, d4, d3\n+\tvsub.f64\td4, d4, d3\n+\tvsub.f64\td3, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvmul.f64\td7, d1, d0\n+\tvmul.f64\td1, d12, d1\n+\tvmla.f64\td1, d8, d0\n+\tvnmls.f64\td7, d8, d12\n+\tvldr\td8, [r7, #464]\t@ 0x1d0\n+\tvldr\td12, [r7, #776]\t@ 0x308\n+\tvmul.f64\td0, d2, d8\n+\tvmul.f64\td2, d12, d2\n+\tvmla.f64\td2, d4, d8\n+\tvcvt.f32.f64\ts2, d1\n+\tvnmls.f64\td0, d4, d12\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts0, d0\n+\tvstr\ts4, [r1, #-4]\n+\tadd\tr1, fp\n+\tvldr\td2, [r7, #472]\t@ 0x1d8\n+\tvstr\ts0, [r9, #-4]\n+\tadd\tr9, fp\n+\tvldr\td0, [r7, #440]\t@ 0x1b8\n+\tvmul.f64\td4, d6, d2\n+\tvmul.f64\td6, d6, d0\n+\tvmla.f64\td4, d3, d0\n+\tvmla.f64\td6, d5, d2\n+\tvldr\td5, [r7, #448]\t@ 0x1c0\n+\tvcvt.f32.f64\ts8, d4\n \tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d25\n-\tvcvt.f32.f64\ts7, d18\n-\tvcvt.f32.f64\ts11, d17\n-\tvcvt.f32.f64\ts6, d24\n-\tvcvt.f32.f64\ts10, d22\n-\tvstr\ts13, [fp, #-4]\n-\tvcvt.f32.f64\ts13, d16\n-\tadd\tfp, r5\n-\tvstr\ts6, [sl, #-4]\n-\tadd\tsl, r5\n-\tvstr\ts13, [r1, #-4]\n-\tvcvt.f32.f64\ts13, d20\n-\tvstr\ts7, [r0, #-4]\n-\tadd\tr1, r5\n-\tvstr\ts11, [r2, #-4]\n-\tadd\tr0, r5\n-\tvstr\ts10, [r9, #-4]\n-\tadd\tr2, r5\n-\tvstr\ts13, [r3, #-4]\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tadd\tr9, r5\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tvstr\ts12, [r8, #-4]\n-\tadd\tr8, r5\n+\tvstr\ts8, [r8, #-4]\n+\tadd\tr8, fp\n+\tvstr\ts12, [r0, #-4]\n+\tadd\tr0, fp\n+\tvldr\td6, [r7, #480]\t@ 0x1e0\n+\tvstr\ts14, [lr, #-4]\n+\tadd\tlr, fp\n+\tvstr\ts2, [r2, #-4]\n+\tadd\tr2, fp\n+\tvmul.f64\td7, d9, d6\n+\tvmul.f64\td9, d9, d5\n+\tvmla.f64\td7, d10, d5\n+\tvmla.f64\td9, d11, d6\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts18, d9\n+\tvstr\ts14, [ip, #-4]\n+\tadd\tip, fp\n+\tvstr\ts18, [r3, #-4]\n+\tadd\tr3, fp\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n \tcmp\tr4, r3\n-\tbne.w\tb896 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x31aa>\n-\tldr.w\tr4, [r7, #500]\t@ 0x1f4\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tb.n\tb766 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x307a>\n-\tmovs\tr2, #128\t@ 0x80\n-\tsubs\tr3, #128\t@ 0x80\n-\tstr.w\tr2, [r7, #552]\t@ 0x228\n-\tb.w\tac78 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x258c>\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tmovs\tr3, #0\n-\tb.w\tac78 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x258c>\n-\tvldr\td1, [pc, #52]\t@ bac8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33dc>\n-\tvldr\td8, [pc, #56]\t@ bad0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33e4>\n-\tvldr\td16, [pc, #60]\t@ bad8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33ec>\n-\tvldr\td17, [pc, #64]\t@ bae0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33f4>\n-\tvldr\td10, [pc, #68]\t@ bae8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x33fc>\n-\tb.w\tabf2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2506>\n-\tnegs\tr4, r2\n-\trsb\tr1, r8, #0\n-\tcmp\tr2, #0\n-\tudiv\tr1, r4, r1\n-\tble.w\tacd4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x25e8>\n-\tb.w\taa36 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x234a>\n-\tmov\tfp, ip\n-\tb.w\taa36 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x234a>\n-\tnop.w\n-\t.word\t0x13445503\n-\t.word\t0xbfee6f0e\n-\t.word\t0x04755a5d\n-\t.word\t0xbfe2cf23\n-\t.word\t0x13445503\n-\t.word\t0x3fee6f0e\n-\t.word\t0x04755a5d\n-\t.word\t0x3fe2cf23\n-\t.word\t0x9b97f4a4\n-\t.word\t0xbfe1e377\n-\tldr.w\tr0, [r7, #504]\t@ 0x1f8\n-\tldr\tr2, [r7, #96]\t@ 0x60\n-\tcmp\tr0, r2\n-\tblt.w\taa64 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2378>\n-\tmov\tr6, r3\n-\tmov\tr8, r2\n-\tstr\tr1, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #264]\t@ 0x108\n-\tldr.w\tr1, [r7, #524]\t@ 0x20c\n+\tbne.w\tbde2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3306>\n+\tb.n\tbc70 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3194>\n+\tmov\tr3, r2\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tcmp\tr2, r3\n+\tblt.w\tb694 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bb8>\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tmov\tfp, r6\n+\tldr.w\tr3, [r7, #756]\t@ 0x2f4\n+\tstr.w\tsl, [r7, #32]\n+\tmov\tsl, r5\n+\tadds\tr3, #1\n+\tstr\tr4, [r7, #28]\n+\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr3, [r7, #240]\t@ 0xf0\n+\tldr.w\tr8, [r7, #752]\t@ 0x2f0\n+\tmov\tr5, r3\n \tmov\tr9, r3\n \tadd.w\tr3, r3, r3, lsl #2\n-\tstr.w\tr3, [r7, #264]\t@ 0x108\n-\tsdiv\tip, r1, r3\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tmov\tr0, r8\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #240]\t@ 0xf0\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tmov\tr2, r8\n+\tmov\tr4, r0\n+\tsubs\tr1, r0, r2\n \tcmp\tr3, #0\n-\tmul.w\tr2, r9, r3\n-\tsub.w\tr0, r2, r1\n-\tsub.w\tr1, ip, r1\n-\tstr.w\tr0, [r7, #508]\t@ 0x1fc\n-\tsub.w\tr0, ip, r3\n-\tstr.w\tr1, [r7, #560]\t@ 0x230\n-\tblt.w\td74a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x505e>\n-\tudiv\tr3, r0, r3\n-\tcmp\tr0, #0\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tblt.w\td734 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5048>\n-\tmovs\tr0, #24\n-\tmov.w\tr3, r9, lsl #1\n-\tadd.w\tr1, r2, r2, lsl #2\n-\tadd.w\tip, ip, ip, lsl #2\n-\tstr.w\tr1, [r7, #260]\t@ 0x104\n-\tmov\tlr, r6\n-\tmul.w\tr3, r0, r3\n-\tldr.w\tr0, [r7, #360]\t@ 0x168\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n-\tmov.w\tfp, #0\n-\tldr.w\tr3, [r7, #240]\t@ 0xf0\n-\tsubs\tr0, r2, r0\n-\trsb\tr2, ip, #0\n-\tstr\tr0, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #788]\t@ 0x314\n+\tmul.w\tr6, r5, r3\n+\tsub.w\tr5, r0, r3\n+\tsub.w\tr2, r6, r2\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tblt.w\te1ea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x570e>\n+\tmov\tr1, r3\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tstr.w\tr0, [r7, #180]\t@ 0xb4\n+\tblt.w\te1ce <__gridxc_gpfa_core_sp_MOD_gpfa_+0x56f2>\n+\tmov\tr1, r9\n+\tmovs\tr2, #24\n+\tadd.w\tip, r6, r6, lsl #2\n+\tadd.w\tlr, r4, r4, lsl #2\n+\tlsls\tr3, r1, #1\n+\tmov\tr9, sl\n+\tmov.w\tr8, #0\n+\tstr.w\tlr, [r7, #92]\t@ 0x5c\n+\tstr.w\tr8, [r7, #664]\t@ 0x298\n+\tmul.w\tr3, r2, r3\n+\tldr.w\tr2, [r7, #648]\t@ 0x288\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tsubs\tr2, r6, r2\n+\tstr.w\tr2, [r7, #176]\t@ 0xb0\n+\trsb\tr2, lr, #0\n \tadds\tr3, #8\n-\tstr\tr2, [r7, #76]\t@ 0x4c\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\trsb\tr2, ip, #0\n+\tstr\tr2, [r7, #56]\t@ 0x38\n+\tlsls\tr2, r1, #4\n+\tstr\tr2, [r7, #52]\t@ 0x34\n+\tlsls\tr2, r1, #5\n+\tstr\tr2, [r7, #48]\t@ 0x30\n+\tlsls\tr2, r1, #6\n+\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n+\tmov\tr6, r3\n \tmov\tr5, r3\n+\tadds\tr1, #1\n+\tstr\tr3, [r7, #104]\t@ 0x68\n+\tstr\tr2, [r7, #40]\t@ 0x28\n+\tstr\tr3, [r7, #100]\t@ 0x64\n+\tstr\tr1, [r7, #96]\t@ 0x60\n+\tstr.w\tip, [r7, #24]\n+\tstr.w\tr8, [r7, #236]\t@ 0xec\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tcmp\tr3, #0\n+\tblt.w\td048 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x456c>\n+\tldr.w\tr4, [r7, #176]\t@ 0xb0\n+\tmov\tr1, r3\n+\tldr.w\tr3, [r7, #236]\t@ 0xec\n+\tadds\tr0, r4, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tmov\tr8, r0\n+\tcmp\tr4, r3\n+\tblt.w\tcf9c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x44c0>\n+\tldrd\tr2, r3, [r7, #660]\t@ 0x294\n+\tstrd\tr5, r6, [r7, #16]\n+\tldr\tr5, [r7, #24]\n+\tsubs\tr1, r3, r2\n+\tstr\tr1, [r7, #112]\t@ 0x70\n+\tldr.w\tr1, [r7, #236]\t@ 0xec\n \tmov\tsl, r3\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tnegs\tr2, r1\n-\tmov\tr0, r5\n-\tmov\tr1, r8\n-\tmov\tr8, r4\n-\tmov\tr4, r5\n-\tadds\tr3, #1\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tstr.w\tfp, [r7, #444]\t@ 0x1bc\n-\tmov.w\tr2, r9, lsl #4\n-\tstr.w\tr3, [r7, #376]\t@ 0x178\n-\tstr\tr2, [r7, #68]\t@ 0x44\n-\tmov.w\tr2, r9, lsl #5\n-\tstr\tr5, [r7, #112]\t@ 0x70\n-\tstr\tr2, [r7, #64]\t@ 0x40\n-\tmov.w\tr2, r9, lsl #6\n-\tstr\tr2, [r7, #56]\t@ 0x38\n-\tcmp.w\tip, #0\n-\tblt.w\tca00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4314>\n-\tldr\tr5, [r7, #80]\t@ 0x50\n-\tadd.w\tr2, r5, fp\n-\tudiv\tr3, r2, ip\n-\tstr.w\tr3, [r7, #244]\t@ 0xf4\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tcmp\tr5, r3\n-\tblt.w\tc97c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4290>\n-\tldrd\tr5, r2, [r7, #440]\t@ 0x1b8\n-\tstr\tr4, [r7, #32]\n-\tmov\tr3, lr\n-\tmov\tr4, r8\n-\tsub.w\tr9, r2, r5\n-\tstrd\tsl, r0, [r7, #36]\t@ 0x24\n-\tadd\tr5, fp\n-\tstr\tr5, [r7, #108]\t@ 0x6c\n-\tldr.w\tr0, [r7, #260]\t@ 0x104\n-\tcmp\tr0, #0\n-\tblt.w\td718 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x502c>\n-\tmov\tr5, r0\n-\tldr\tr0, [r7, #108]\t@ 0x6c\n-\tudiv\tr0, r0, r5\n-\tmov\tr6, r0\n-\tldr.w\tr0, [r7, #440]\t@ 0x1b8\n-\tcmp\tr0, r2\n-\tblt.w\tc956 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x426a>\n-\tldr.w\tr5, [r7, #364]\t@ 0x16c\n+\tadd\tr2, r1\n+\tstr\tr2, [r7, #108]\t@ 0x6c\n \tcmp\tr5, #0\n-\tble.w\tc956 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x426a>\n-\tldr.w\tr0, [r7, #516]\t@ 0x204\n-\tmov\tr8, r4\n-\tldr.w\tlr, [r7, #84]\t@ 0x54\n-\tadds\tr5, #1\n-\tldr.w\tr4, [r7, #496]\t@ 0x1f0\n-\tadd\tr0, r2\n-\tvmov.f64\td31, #80\t@ 0x3e800000 0.250\n-\tstr\tr5, [r7, #116]\t@ 0x74\n-\tstr\tr3, [r7, #28]\n-\tstrd\tr2, ip, [r7, #20]\n-\tstrd\tr9, r1, [r7, #12]\n-\tstr.w\tfp, [r7, #8]\n-\tldr.w\tfp, [r7, #524]\t@ 0x20c\n-\tmov\tr9, r8\n-\tldr.w\tsl, [r7, #516]\t@ 0x204\n-\tmov\tip, r4\n-\tstr.w\tr0, [r7, #544]\t@ 0x220\n+\tblt.w\te1b4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x56d8>\n+\tmov\tr1, r5\n+\tldr\tr0, [r7, #108]\t@ 0x6c\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tmov\tr1, r0\n+\tcmp\tr3, sl\n+\tblt.w\tcf7a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x449e>\n+\tldr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tcmp\tr3, #0\n+\tble.w\tcf7a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x449e>\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tmov\tr6, fp\n+\tldr.w\tfp, [r7, #68]\t@ 0x44\n+\tmov\tip, r9\n+\tadd.w\tr0, r3, sl\n+\tstr.w\tr8, [r7, #12]\n+\tstr.w\tsl, [r7, #8]\n+\tstr.w\tr0, [r7, #784]\t@ 0x310\n+\tmov\tr9, r6\n+\tstrd\tr0, r5, [r7, #80]\t@ 0x50\n+\tmov\tr0, fp\n+\tldr.w\tsl, [r7, #748]\t@ 0x2ec\n+\tmov\tlr, ip\n+\tldr.w\tfp, [r7, #752]\t@ 0x2f0\n \tmovs\tr3, #1\n-\tstr\tr0, [r7, #100]\t@ 0x64\n-\tmov\tr0, lr\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n-\tstr\tr6, [r7, #104]\t@ 0x68\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tstr\tr1, [r7, #88]\t@ 0x58\n+\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tldrd\tr2, r3, [r7, #784]\t@ 0x310\n \tadd.w\tr8, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tsl, r8\n \tit\tgt\n \taddgt\tr8, fp\n \tadd\tr3, r8\n-\tstr.w\tr3, [r7, #556]\t@ 0x22c\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n \tcmp\tsl, r3\n-\tble.n\tbc72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3586>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #556]\t@ 0x22c\n-\tldrd\tr2, r3, [r7, #556]\t@ 0x22c\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #768]\t@ 0x300\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n+\tstr.w\tr3, [r7, #760]\t@ 0x2f8\n \tcmp\tsl, r3\n-\tble.n\tbc86 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x359a>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #536]\t@ 0x218\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #760]\t@ 0x2f8\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n \tcmp\tsl, r3\n-\tble.n\tbc9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x35b2>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tstr.w\tr3, [r7, #640]\t@ 0x280\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #640]\t@ 0x280\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tadds\tr4, r3, r2\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n \tcmp\tsl, r4\n \tit\tgt\n \taddgt\tr4, fp\n \tadd\tr3, r4\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n \tcmp\tsl, r3\n-\tble.n\tbcc2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x35d6>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #500]\t@ 0x1f4\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr3, [r7, #708]\t@ 0x2c4\n \tcmp\tsl, r3\n-\tble.n\tbcda <__gridxc_gpfa_core_sp_MOD_gpfa_+0x35ee>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #492]\t@ 0x1ec\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #708]\t@ 0x2c4\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #708]\t@ 0x2c4\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n \tcmp\tsl, r3\n-\tble.n\tbcf2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3606>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n \tcmp\tsl, r3\n-\tble.n\tbd0a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x361e>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr3, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tadd\tr3, r4\n \tcmp\tsl, r3\n \tit\tgt\n \taddgt\tr3, fp\n \tadd\tr2, r3\n-\tstr.w\tr2, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n \tcmp\tsl, r2\n-\tble.n\tbd2a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x363e>\n-\tadd\tr2, fp\n-\tstr.w\tr2, [r7, #484]\t@ 0x1e4\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n+\titt\tgt\n+\taddgt\tr2, fp\n+\tstrgt.w\tr2, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tldr.w\tr1, [r7, #700]\t@ 0x2bc\n \tadd\tr2, r1\n-\tstr.w\tr2, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n \tcmp\tsl, r2\n-\tble.n\tbd42 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3656>\n-\tadd\tr2, fp\n-\tstr.w\tr2, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n+\titt\tgt\n+\taddgt\tr2, fp\n+\tstrgt.w\tr2, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n \tadd\tr2, r1\n-\tstr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr2, [r7, #688]\t@ 0x2b0\n \tcmp\tsl, r2\n-\tble.n\tbd5a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x366e>\n-\tadd\tr2, fp\n-\tstr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n+\titt\tgt\n+\taddgt\tr2, fp\n+\tstrgt.w\tr2, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr2, [r7, #788]\t@ 0x314\n+\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n \tadd\tr2, r1\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n \tcmp\tsl, r2\n-\tble.n\tbd72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3686>\n-\tadd\tr2, fp\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr2, [r7, #508]\t@ 0x1fc\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\titt\tgt\n+\taddgt\tr2, fp\n+\tstrgt.w\tr2, [r7, #624]\t@ 0x270\n+\tldr.w\tr2, [r7, #720]\t@ 0x2d0\n \tadd\tr2, r3\n \tcmp\tsl, r2\n \tit\tgt\n \taddgt\tr2, fp\n-\tadd.w\tlr, r1, r2\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tcmp\tsl, lr\n-\tit\tgt\n-\taddgt\tlr, fp\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #472]\t@ 0x1d8\n+\tadd\tr1, r2\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n \tcmp\tsl, r1\n-\tble.n\tbda0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x36b4>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n-\tadd\tr1, r5\n-\tstr.w\tr1, [r7, #468]\t@ 0x1d4\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tldr.w\tr5, [r7, #684]\t@ 0x2ac\n+\tadd.w\tip, r1, r5\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tcmp\tsl, ip\n+\tit\tgt\n+\taddgt\tip, fp\n+\tadd\tr1, ip\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n \tcmp\tsl, r1\n-\tble.n\tbdb8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x36cc>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n \tadd\tr1, r5\n-\tstr.w\tr1, [r7, #416]\t@ 0x1a0\n+\tstr.w\tr1, [r7, #616]\t@ 0x268\n \tcmp\tsl, r1\n-\tble.n\tbdd0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x36e4>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #616]\t@ 0x268\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n \tadd\tr1, r2\n-\tstr.w\tr1, [r7, #456]\t@ 0x1c8\n+\tstr.w\tr1, [r7, #676]\t@ 0x2a4\n \tcmp\tsl, r1\n-\tble.n\tbde4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x36f8>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tldr.w\tr6, [r7, #456]\t@ 0x1c8\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tldr.w\tr6, [r7, #676]\t@ 0x2a4\n \tadd\tr1, r6\n-\tstr.w\tr1, [r7, #448]\t@ 0x1c0\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n \tcmp\tsl, r1\n-\tble.n\tbdfc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3710>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tldr.w\tr6, [r7, #448]\t@ 0x1c0\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tldr.w\tr6, [r7, #672]\t@ 0x2a0\n \tadds\tr6, r1, r6\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n \tcmp\tsl, r6\n \tit\tgt\n \taddgt\tr6, fp\n \tadd\tr1, r6\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr1, [r7, #668]\t@ 0x29c\n \tcmp\tsl, r1\n-\tble.n\tbe20 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3734>\n-\tadd\tr1, fp\n-\tstr.w\tr1, [r7, #464]\t@ 0x1d0\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\titt\tgt\n+\taddgt\tr1, fp\n+\tstrgt.w\tr1, [r7, #668]\t@ 0x29c\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tldr.w\tr5, [r7, #668]\t@ 0x29c\n \tadd\tr1, r5\n-\tldr.w\tr5, [r7, #444]\t@ 0x1bc\n+\tldr.w\tr5, [r7, #664]\t@ 0x298\n \tcmp\tsl, r1\n \tit\tgt\n \taddgt\tr1, fp\n \tcmp\tr5, #0\n-\tbne.w\tca1a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x432e>\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n+\tbne.w\td066 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x458a>\n+\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n \tcmp\tr5, #0\n-\tble.w\tc904 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4218>\n-\tldr.w\tr5, [r7, #428]\t@ 0x1ac\n+\tble.w\tcf2e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4452>\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n \tlsls\tr3, r3, #2\n \tlsls\tr6, r6, #2\n-\tstr.w\tr3, [r7, #312]\t@ 0x138\n-\tstr.w\tr6, [r7, #280]\t@ 0x118\n+\tstr.w\tr3, [r7, #288]\t@ 0x120\n+\tstr.w\tr6, [r7, #248]\t@ 0xf8\n \tlsls\tr2, r2, #2\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #412]\t@ 0x19c\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tmov.w\tlr, lr, lsl #2\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tstr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n+\tmov.w\tip, ip, lsl #2\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tmov.w\tr8, r8, lsl #2\n-\tldr.w\tr6, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr6, [r7, #616]\t@ 0x268\n \tlsls\tr4, r4, #2\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\tstr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n \tlsls\tr6, r6, #2\n-\tstr.w\tr6, [r7, #284]\t@ 0x11c\n+\tstr.w\tr6, [r7, #264]\t@ 0x108\n \tlsls\tr6, r3, #2\n-\tstr.w\tr6, [r7, #288]\t@ 0x120\n+\tstr.w\tr6, [r7, #256]\t@ 0x100\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #556]\t@ 0x22c\n-\tldr.w\tr5, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr6, [r7, #464]\t@ 0x1d0\n-\tstr.w\tlr, [r7, #236]\t@ 0xec\n+\tstr.w\tr5, [r7, #768]\t@ 0x300\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr6, [r7, #668]\t@ 0x29c\n+\tstr.w\tip, [r7, #244]\t@ 0xf4\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #184]\t@ 0xb8\n-\tldr.w\tr5, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr5, [r7, #156]\t@ 0x9c\n+\tldr.w\tr5, [r7, #632]\t@ 0x278\n \tlsls\tr6, r6, #2\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #188]\t@ 0xbc\n-\tldr.w\tr5, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr5, [r7, #160]\t@ 0xa0\n+\tldr.w\tr5, [r7, #708]\t@ 0x2c4\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #216]\t@ 0xd8\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr5, [r7, #164]\t@ 0xa4\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #220]\t@ 0xdc\n-\tldr.w\tr5, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr5, [r7, #168]\t@ 0xa8\n+\tldr.w\tr5, [r7, #700]\t@ 0x2bc\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #232]\t@ 0xe8\n-\tldr.w\tr5, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr5, [r7, #172]\t@ 0xac\n+\tldr.w\tr5, [r7, #684]\t@ 0x2ac\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #256]\t@ 0x100\n-\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr5, [r7, #200]\t@ 0xc8\n+\tldr.w\tr5, [r7, #624]\t@ 0x270\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #268]\t@ 0x10c\n-\tldr.w\tr5, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr5, [r7, #212]\t@ 0xd4\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #272]\t@ 0x110\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr5, [r7, #216]\t@ 0xd8\n+\tldr.w\tr5, [r7, #688]\t@ 0x2b0\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #276]\t@ 0x114\n-\tstr.w\tr6, [r7, #292]\t@ 0x124\n-\tstr.w\tr2, [r7, #296]\t@ 0x128\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr5, [r7, #412]\t@ 0x19c\n+\tstr.w\tr5, [r7, #232]\t@ 0xe8\n+\tstr.w\tr6, [r7, #268]\t@ 0x10c\n+\tstr.w\tr2, [r7, #272]\t@ 0x110\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tldr.w\tr5, [r7, #608]\t@ 0x260\n \tlsls\tr2, r2, #2\n-\tstr.w\tr2, [r7, #300]\t@ 0x12c\n+\tstr.w\tr2, [r7, #276]\t@ 0x114\n \tlsls\tr2, r1, #2\n-\tstr.w\tr2, [r7, #304]\t@ 0x130\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n+\tstr.w\tr2, [r7, #280]\t@ 0x118\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n \tadd.w\tr1, r9, r8\n-\tstr.w\tr1, [r7, #468]\t@ 0x1d4\n-\tadd.w\tr1, ip, r8\n-\tstr.w\tr1, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n \tadd.w\tr1, r9, r5\n+\tstr.w\tr1, [r7, #676]\t@ 0x2a4\n+\tadd.w\tr1, lr, r5\n \tlsls\tr2, r2, #2\n-\tstr.w\tr1, [r7, #472]\t@ 0x1d8\n-\tstr.w\tr2, [r7, #308]\t@ 0x134\n-\tadd.w\tr1, ip, r5\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tstr.w\tr1, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr1, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr2, [r7, #284]\t@ 0x11c\n \tadd.w\tr1, r9, r3\n-\tstr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tadd.w\tr1, ip, r3\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd\tr8, lr\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr.w\tr1, [r7, #704]\t@ 0x2c0\n \tlsls\tr2, r2, #2\n-\tstr.w\tr1, [r7, #492]\t@ 0x1ec\n \tadd.w\tr1, r9, r3\n-\tstr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tadd.w\tr1, ip, r3\n-\tldr.w\tr3, [r7, #312]\t@ 0x138\n-\tstr.w\tr2, [r7, #180]\t@ 0xb4\n-\tadd\tr2, r9\n+\tldr.w\tr6, [r7, #664]\t@ 0x298\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #288]\t@ 0x120\n+\tvldr\td7, [r7, #184]\t@ 0xb8\n \tadd\tr3, r9\n-\tstr.w\tr1, [r7, #500]\t@ 0x1f4\n-\tstr.w\tr3, [r7, #396]\t@ 0x18c\n+\tstr.w\tr2, [r7, #152]\t@ 0x98\n+\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n+\tadd\tr2, r9\n \tadd.w\tr1, r9, r4\n-\tldr.w\tr6, [r7, #444]\t@ 0x1bc\n+\tstr.w\tr3, [r7, #508]\t@ 0x1fc\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n \tmovs\tr3, #1\n-\tstr.w\tr1, [r7, #388]\t@ 0x184\n-\tadd.w\tr1, ip, r4\n-\tstr.w\tr2, [r7, #392]\t@ 0x188\n-\tstr.w\tr1, [r7, #404]\t@ 0x194\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n-\tstr.w\tfp, [r7, #176]\t@ 0xb0\n-\tstr.w\tsl, [r7, #164]\t@ 0xa4\n-\tvstr\td9, [r7, #168]\t@ 0xa8\n-\tvstr\td0, [r7, #152]\t@ 0x98\n-\tvstr\td2, [r7, #144]\t@ 0x90\n-\tvstr\td13, [r7, #136]\t@ 0x88\n-\tstr.w\tr0, [r7, #556]\t@ 0x22c\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n-\tvldr\ts14, [r3, #-4]\n-\tvldr\ts15, [r2, #-4]\n-\tvldr\ts10, [r1, #-4]\n+\tadd.w\tr1, lr, r4\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tstr.w\tfp, [r7, #148]\t@ 0x94\n+\tstr.w\tsl, [r7, #144]\t@ 0x90\n+\tstr.w\tr1, [r7, #668]\t@ 0x29c\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n+\tvstr\td7, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr4, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr5, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr0, [r7, #152]\t@ 0x98\n+\tvldr\ts0, [r2, #-4]\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tvldr\ts2, [r4, #-4]\n+\tvldr\ts4, [r5, #-4]\n+\tvcvt.f64.f32\td0, s0\n+\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n+\tvldr\ts14, [r2, #-4]\n+\tvcvt.f64.f32\td1, s2\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tadds\tr4, #1\n+\tldr.w\tr5, [r7, #700]\t@ 0x2bc\n+\tvcvt.f64.f32\td2, s4\n+\tstr.w\tr4, [r7, #712]\t@ 0x2c8\n+\tvcvt.f64.f32\td7, s14\n+\tldr.w\tr4, [r7, #708]\t@ 0x2c4\n+\tvldr\ts9, [r2, #-4]\n+\tadds\tr2, r6, r0\n+\tldr.w\tr0, [r7, #156]\t@ 0x9c\n+\tadd\tr2, lr\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tvsub.f64\td12, d1, d2\n+\tadd.w\tip, r0, r6\n+\tldr.w\tr0, [r7, #160]\t@ 0xa0\n \tvldr\ts12, [r5, #-4]\n-\tvcvt.f64.f32\td24, s14\n-\tldr.w\tr4, [r7, #392]\t@ 0x188\n-\tvcvt.f64.f32\td16, s15\n-\tldr.w\tr5, [r7, #484]\t@ 0x1e4\n-\tvcvt.f64.f32\td17, s10\n-\tvcvt.f64.f32\td18, s12\n-\tldr.w\tr0, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr3, [r7, #492]\t@ 0x1ec\n-\tvadd.f64\td20, d24, d16\n-\tvldr\ts12, [r4, #-4]\n-\tvldr\ts11, [r5, #-4]\n-\tvsub.f64\td24, d24, d16\n-\tvldr\ts9, [r0, #-4]\n-\tvadd.f64\td23, d17, d18\n-\tldr.w\tr5, [r7, #500]\t@ 0x1f4\n+\tvcvt.f64.f32\td10, s9\n+\tadds\tr5, r0, r6\n+\tldr.w\tr0, [r7, #164]\t@ 0xa4\n+\tvldr\ts8, [r4, #-4]\n+\tadds\tr4, r0, r6\n+\tldr.w\tr0, [r7, #168]\t@ 0xa8\n+\tvldr\ts16, [r3, #-4]\n \tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td21, s11\n-\tvsub.f64\td17, d17, d18\n-\tvcvt.f64.f32\td19, s9\n-\tvldr\ts14, [r3, #-4]\n-\tvadd.f64\td18, d20, d23\n-\tldr.w\tr2, [r7, #388]\t@ 0x184\n-\tvldr\ts15, [r5, #-4]\n-\tvsub.f64\td20, d20, d23\n-\tldr.w\tr5, [r7, #404]\t@ 0x194\n-\tvcvt.f64.f32\td16, s14\n-\tvadd.f64\td25, d21, d19\n-\tvsub.f64\td21, d21, d19\n-\tvmov.f64\td19, d6\n-\tvcvt.f64.f32\td27, s15\n-\tvfms.f64\td19, d18, d31\n-\tvadd.f64\td18, d18, d6\n-\tvldr\ts15, [r5, #-4]\n-\tvmul.f64\td30, d8, d17\n-\tldr.w\tr0, [r7, #536]\t@ 0x218\n-\tvmul.f64\td17, d1, d17\n-\tvadd.f64\td23, d16, d27\n-\tvsub.f64\td16, d16, d27\n-\tvcvt.f64.f32\td27, s15\n-\tadds\tr0, #1\n-\tvcvt.f32.f64\ts15, d18\n+\tadds\tr3, r0, r6\n+\tvldr\ts9, [r2, #-4]\n+\tvldr\ts6, [r8, #-4]\n+\tadd.w\tr0, r9, ip\n+\tstr.w\tr0, [r7, #320]\t@ 0x140\n+\tadd.w\tr0, lr, ip\n+\tstr.w\tr0, [r7, #376]\t@ 0x178\n+\tadd.w\tr0, r9, r5\n+\tstr.w\tr0, [r7, #512]\t@ 0x200\n+\tadd.w\tr0, lr, r5\n+\tstr.w\tr0, [r7, #528]\t@ 0x210\n+\tadd.w\tr0, r9, r4\n+\tstr.w\tr0, [r7, #516]\t@ 0x204\n+\tadd.w\tr0, lr, r4\n \tstr.w\tr0, [r7, #536]\t@ 0x218\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tvmov.f64\td29, d30\n-\tldr.w\tr1, [r7, #396]\t@ 0x18c\n-\tvfma.f64\td17, d8, d24\n-\tvldr\ts14, [r2, #-4]\n-\tvfma.f64\td30, d24, d12\n-\tvstr\ts15, [r4, #-4]\n-\tadd\tr4, r0\n-\tstr.w\tr4, [r7, #392]\t@ 0x188\n-\tvfnms.f64\td29, d1, d24\n-\tldr.w\tr4, [r7, #180]\t@ 0xb4\n-\tvadd.f64\td24, d25, d23\n-\tvldr\ts15, [r1, #-4]\n-\tvsub.f64\td25, d25, d23\n-\tadds\tr3, r6, r4\n-\tvmov.f64\td23, d19\n-\tadd\tr3, ip\n-\tvfma.f64\td23, d10, d20\n-\tvcvt.f64.f32\td26, s15\n-\tvfma.f64\td19, d20, d11\n-\tvcvt.f64.f32\td28, s14\n-\tmov\tr4, r1\n-\tvldr\ts15, [r3, #-4]\n-\tadd\tr4, r0\n-\tvcvt.f64.f32\td20, s15\n-\tvmov.f64\td18, d20\n-\tvfms.f64\td18, d24, d31\n-\tvadd.f64\td24, d24, d20\n-\tvmul.f64\td20, d8, d16\n-\tvmul.f64\td16, d1, d16\n-\tvfma.f64\td16, d8, d21\n-\tvcvt.f32.f64\ts15, d24\n-\tvmov.f64\td22, d18\n-\tvfma.f64\td18, d25, d11\n-\tvfma.f64\td22, d10, d25\n-\tvmov.f64\td25, d20\n-\tvfma.f64\td20, d21, d12\n-\tvfnms.f64\td25, d1, d21\n-\tvstr\ts15, [r3, #-4]\n-\tvadd.f64\td29, d29, d18\n-\tvadd.f64\td18, d18, d30\n-\tvadd.f64\td6, d17, d22\n-\tvsub.f64\td22, d22, d17\n-\tvsub.f64\td17, d23, d16\n-\tvadd.f64\td20, d19, d20\n-\tvadd.f64\td19, d19, d25\n-\tvadd.f64\td23, d23, d16\n-\tvcvt.f32.f64\ts19, d18\n-\tvcvt.f32.f64\ts12, d6\n-\tvcvt.f32.f64\ts13, d29\n-\tvcvt.f32.f64\ts11, d17\n-\tvcvt.f32.f64\ts14, d20\n-\tvcvt.f32.f64\ts15, d19\n-\tvcvt.f32.f64\ts6, d23\n-\tvmov.f64\td23, d28\n-\tvcvt.f32.f64\ts7, d22\n-\tvstr\ts11, [r2, #-4]\n-\tadd\tr2, r0\n-\tstr.w\tr4, [r7, #396]\t@ 0x18c\n-\tldr.w\tr4, [r7, #184]\t@ 0xb8\n-\tvstr\ts14, [r1, #-4]\n-\tadds\tr1, r4, r6\n-\tldr.w\tr4, [r7, #188]\t@ 0xbc\n-\tadd.w\tlr, r9, r1\n-\tstr.w\tr2, [r7, #388]\t@ 0x184\n+\tadd.w\tr0, r9, r3\n+\tstr.w\tr0, [r7, #544]\t@ 0x220\n+\tadd.w\tr0, lr, r3\n+\tstr.w\tr0, [r7, #548]\t@ 0x224\n+\tvcvt.f64.f32\td9, s8\n+\tldr.w\tr0, [r7, #288]\t@ 0x120\n+\tvcvt.f64.f32\td8, s16\n+\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tvcvt.f64.f32\td11, s9\n+\tadds\tr3, r6, r0\n+\tldr.w\tr0, [r7, #172]\t@ 0xac\n+\tvcvt.f64.f32\td3, s6\n+\tadd\tr3, lr\n+\tadd.w\tfp, r0, r6\n+\tldr.w\tr0, [r7, #200]\t@ 0xc8\n+\tvldr\ts8, [r1, #-4]\n+\tadd.w\tsl, r0, r6\n+\tldr.w\tr0, [r7, #212]\t@ 0xd4\n+\tldr.w\tr1, [r7, #668]\t@ 0x29c\n+\tadd.w\tip, r0, r6\n+\tldr.w\tr0, [r7, #216]\t@ 0xd8\n+\tvcvt.f64.f32\td13, s8\n+\tadds\tr5, r0, r6\n+\tldr.w\tr0, [r7, #232]\t@ 0xe8\n+\tvldr\ts9, [r1, #-4]\n+\tadds\tr4, r0, r6\n+\tadd.w\tr0, r9, fp\n+\tstr.w\tr0, [r7, #520]\t@ 0x208\n+\tadd.w\tr0, r9, sl\n+\tstr.w\tr0, [r7, #368]\t@ 0x170\n+\tadd.w\tr0, lr, sl\n+\tstr.w\tr0, [r7, #552]\t@ 0x228\n+\tadd.w\tr0, r9, ip\n+\tadd\tip, lr\n+\tstr.w\tip, [r7, #592]\t@ 0x250\n+\tadd.w\tip, r9, r5\n+\tstr.w\tip, [r7, #568]\t@ 0x238\n+\tadd.w\tip, lr, r5\n+\tstr.w\tip, [r7, #336]\t@ 0x150\n+\tadd.w\tip, r9, r4\n+\tstr.w\tip, [r7, #576]\t@ 0x240\n+\tadd.w\tip, lr, r4\n+\tldr.w\tr4, [r7, #244]\t@ 0xf4\n+\tstr.w\tip, [r7, #600]\t@ 0x258\n+\tvcvt.f64.f32\td5, s9\n+\tadd.w\tsl, r4, r6\n+\tldr.w\tr4, [r7, #248]\t@ 0xf8\n+\tvadd.f64\td4, d8, d0\n+\tvsub.f64\td8, d8, d0\n+\tadd.w\tip, r4, r6\n+\tldr.w\tr4, [r7, #264]\t@ 0x108\n+\tvadd.f64\td0, d1, d2\n+\tstr.w\tr0, [r7, #560]\t@ 0x230\n+\tadds\tr5, r4, r6\n+\tldr.w\tr4, [r7, #256]\t@ 0x100\n+\tadd.w\tr0, r9, sl\n+\tstr.w\tr0, [r7, #584]\t@ 0x248\n \tadd\tr4, r6\n-\tldr.w\tr2, [r7, #216]\t@ 0xd8\n-\tadd.w\tr8, r9, r4\n-\tldr.w\tr3, [r7, #220]\t@ 0xdc\n-\tvldr\ts14, [lr, #-4]\n-\tmov\tr0, r8\n-\tadd\tr2, r6\n-\tadd.w\tr8, ip, r4\n-\tstr.w\tr8, [r7, #408]\t@ 0x198\n-\tadd.w\tr8, r9, r2\n-\tvcvt.f64.f32\td19, s14\n-\tvldr\ts14, [r0, #-4]\n-\tmov\tr4, r8\n-\tadd\tr3, r6\n-\tadd.w\tr8, ip, r2\n-\tstr.w\tr0, [r7, #316]\t@ 0x13c\n-\tvcvt.f64.f32\td16, s14\n-\tmov\tr0, r8\n-\tadd.w\tr8, r9, r3\n-\tvldr\ts14, [r4, #-4]\n-\tmov\tr2, r8\n-\tstr.w\tr2, [r7, #324]\t@ 0x144\n-\tadd.w\tr8, ip, r3\n-\tadd\tr1, ip\n-\tvadd.f64\td18, d19, d16\n-\tvsub.f64\td19, d19, d16\n-\tvcvt.f64.f32\td16, s14\n-\tvldr\ts14, [r2, #-4]\n-\tldr.w\tr2, [r7, #312]\t@ 0x138\n-\tstr.w\tr4, [r7, #320]\t@ 0x140\n-\tmov\tr4, r5\n-\tvcvt.f64.f32\td17, s14\n-\tadds\tr3, r6, r2\n-\tadd\tr3, ip\n-\tldr.w\tr2, [r7, #408]\t@ 0x198\n-\tstr.w\tr8, [r7, #412]\t@ 0x19c\n+\tadd.w\tr0, r9, ip\n \tstr.w\tr0, [r7, #328]\t@ 0x148\n-\tvadd.f64\td21, d16, d17\n-\tvldr\ts14, [r3, #-4]\n-\tvsub.f64\td17, d16, d17\n-\tvstr\ts12, [r5, #-4]\n-\tvstr\ts13, [r3, #-4]\n-\tvcvt.f64.f32\td29, s14\n-\tvldr\ts11, [r1, #-4]\n-\tvadd.f64\td20, d18, d21\n-\tvldr\ts10, [r0, #-4]\n-\tvldr\ts14, [r8, #-4]\n-\tvmul.f64\td24, d8, d17\n-\tvldr\ts12, [r2, #-4]\n-\tvsub.f64\td18, d18, d21\n-\tvcvt.f64.f32\td16, s10\n-\tvmul.f64\td17, d1, d17\n-\tvfms.f64\td23, d20, d31\n-\tvadd.f64\td20, d28, d20\n-\tvcvt.f64.f32\td6, s12\n-\tvcvt.f64.f32\td21, s14\n-\tvmov.f64\td22, d24\n-\tvfma.f64\td17, d8, d19\n-\tvfma.f64\td24, d19, d12\n-\tvfnms.f64\td22, d1, d19\n-\tvcvt.f32.f64\ts9, d20\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tvcvt.f64.f32\td20, s11\n-\tadds\tr5, r4, r5\n-\tldr.w\tr4, [r7, #232]\t@ 0xe8\n-\tstr.w\tr5, [r7, #404]\t@ 0x194\n-\tvmov.f64\td25, d23\n-\tvfma.f64\td23, d18, d11\n-\tvadd.f64\td19, d20, d6\n-\tvfma.f64\td25, d10, d18\n-\tvadd.f64\td18, d16, d21\n-\tvsub.f64\td16, d16, d21\n-\tvsub.f64\td20, d20, d6\n-\tadds\tr2, r4, r6\n-\tldr.w\tr4, [r7, #236]\t@ 0xec\n-\tadd.w\tr5, r9, r2\n-\tadd\tr2, ip\n-\tvadd.f64\td21, d19, d18\n-\tvsub.f64\td19, d19, d18\n-\tvmov.f64\td18, d27\n-\tadds\tr3, r4, r6\n-\tldr.w\tr4, [r7, #256]\t@ 0x100\n-\tvfms.f64\td18, d21, d31\n-\tvadd.f64\td27, d27, d21\n-\tadd.w\tfp, r4, r6\n-\tldr.w\tr4, [r7, #268]\t@ 0x10c\n-\tadd.w\tsl, r4, r6\n+\tadd.w\tr0, r9, r5\n+\tadd\tr5, lr\n+\tstr.w\tr5, [r7, #624]\t@ 0x270\n+\tadd.w\tr5, r9, r4\n+\tadd\tr4, lr\n+\tstr.w\tr4, [r7, #360]\t@ 0x168\n+\tvadd.f64\td1, d4, d0\n \tldr.w\tr4, [r7, #272]\t@ 0x110\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tvcvt.f32.f64\ts8, d27\n-\tadd.w\tr8, r4, r6\n-\tldr.w\tr4, [r7, #468]\t@ 0x1d4\n-\tvldr\ts12, [r5, #-4]\n-\tvmov.f64\td21, d18\n-\tvfma.f64\td18, d19, d11\n-\tvfma.f64\td21, d10, d19\n-\tvmul.f64\td19, d8, d16\n-\tvmul.f64\td16, d1, d16\n-\tvstr\ts9, [r4, #-4]\n-\tvfma.f64\td16, d8, d20\n-\tadd\tr4, r0\n-\tstr.w\tr4, [r7, #468]\t@ 0x1d4\n-\tadd.w\tr4, r9, r3\n-\tvmov.f64\td28, d19\n-\tvfma.f64\td19, d20, d12\n-\tvfnms.f64\td28, d1, d20\n-\tadd.w\tr0, r9, fp\n-\tstr.w\tr0, [r7, #416]\t@ 0x1a0\n-\tadd.w\tr0, r9, sl\n-\tvadd.f64\td22, d22, d18\n-\tstr.w\tr0, [r7, #420]\t@ 0x1a4\n-\tadd.w\tr0, r9, r8\n-\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n-\tldr.w\tr0, [r7, #484]\t@ 0x1e4\n-\tvadd.f64\td18, d18, d24\n-\tadd\tr3, ip\n-\tadd\tfp, ip\n-\tvcvt.f32.f64\ts13, d22\n-\tadd\tsl, ip\n-\tvadd.f64\td19, d23, d19\n-\tadd\tr8, ip\n-\tvadd.f64\td28, d23, d28\n-\tvsub.f64\td23, d25, d16\n-\tvadd.f64\td16, d25, d16\n-\tvcvt.f32.f64\ts14, d18\n-\tvadd.f64\td18, d17, d21\n-\tvsub.f64\td21, d21, d17\n-\tvcvt.f32.f64\ts10, d19\n-\tvcvt.f64.f32\td19, s12\n-\tvldr\ts12, [r4, #-4]\n-\tvcvt.f32.f64\ts11, d28\n-\tvcvt.f32.f64\ts1, d16\n-\tvcvt.f32.f64\ts5, d21\n-\tvcvt.f64.f32\td22, s12\n-\tvldr\ts12, [r2, #-4]\n-\tvstr\ts8, [r0, #-4]\n-\tvldr\ts27, [r3, #-4]\n-\tvcvt.f64.f32\td20, s12\n-\tvcvt.f32.f64\ts12, d23\n-\tvstr\ts12, [lr, #-4]\n-\tvcvt.f32.f64\ts12, d18\n-\tvstr\ts10, [r5, #-4]\n-\tvstr\ts11, [r4, #-4]\n-\tldr.w\tr4, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr5, [r7, #420]\t@ 0x1a4\n-\tvstr\ts12, [r1, #-4]\n-\tvstr\ts13, [r2, #-4]\n-\tvldr\ts10, [r4, #-4]\n-\tldr.w\tr4, [r7, #424]\t@ 0x1a8\n-\tvldr\ts8, [r5, #-4]\n-\tvcvt.f64.f32\td5, s10\n-\tvstr\ts14, [r3, #-4]\n-\tvldr\ts12, [sl, #-4]\n-\tvldr\ts9, [r4, #-4]\n-\tvcvt.f64.f32\td16, s8\n-\tvldr\ts14, [r8, #-4]\n-\tvadd.f64\td21, d19, d5\n-\tvsub.f64\td17, d19, d5\n-\tvcvt.f64.f32\td23, s9\n-\tvmov.f64\td19, d26\n-\tvldr\ts13, [fp, #-4]\n-\tvcvt.f64.f32\td18, s12\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tvadd.f64\td24, d16, d23\n-\tvsub.f64\td16, d16, d23\n-\tadds\tr5, r0, r5\n-\tstr.w\tr5, [r7, #484]\t@ 0x1e4\n-\tldr.w\tr5, [r7, #276]\t@ 0x114\n-\tvadd.f64\td23, d21, d24\n-\tvmul.f64\td4, d8, d16\n-\tvsub.f64\td21, d21, d24\n-\tvmul.f64\td16, d1, d16\n-\tvfma.f64\td16, d8, d17\n-\tadds\tr1, r5, r6\n-\tldr.w\tr5, [r7, #280]\t@ 0x118\n-\tadd.w\tlr, r9, r1\n-\tvfms.f64\td19, d23, d31\n-\tvmov.f64\td5, d4\n-\tvfnms.f64\td5, d1, d17\n-\tvfma.f64\td4, d17, d12\n-\tvcvt.f64.f32\td17, s13\n-\tadds\tr3, r5, r6\n-\tvadd.f64\td23, d26, d23\n-\tldr.w\tr5, [r7, #284]\t@ 0x11c\n-\tadds\tr4, r5, r6\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvadd.f64\td26, d20, d17\n-\tvsub.f64\td20, d20, d17\n-\tadds\tr2, r5, r6\n-\tmov\tr5, lr\n-\tvmov.f64\td27, d19\n-\tvfma.f64\td19, d21, d11\n-\tvfma.f64\td27, d10, d21\n-\tvcvt.f64.f32\td21, s14\n-\tadd.w\tlr, ip, r1\n-\tvcvt.f32.f64\ts14, d23\n-\tldr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tadd.w\tr0, r9, r4\n-\tadd\tr4, ip\n-\tstr.w\tr4, [r7, #448]\t@ 0x1c0\n-\tvsub.f64\td17, d18, d21\n-\tldr.w\tr4, [r7, #296]\t@ 0x128\n-\tvadd.f64\td18, d18, d21\n-\tvldr\ts13, [r5, #-4]\n-\tstr.w\tr5, [r7, #332]\t@ 0x14c\n+\tvadd.f64\td2, d3, d6\n+\tstr.w\tr0, [r7, #608]\t@ 0x260\n+\tvsub.f64\td6, d3, d6\n \tadd\tr4, r6\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tvcvt.f64.f32\td23, s27\n-\tvmul.f64\td25, d8, d17\n-\tvmul.f64\td17, d1, d17\n-\tvfma.f64\td17, d8, d20\n-\tvstr\ts14, [r1, #-4]\n-\tadd\tr1, r5\n-\tadd.w\tr5, r9, r2\n-\tstr.w\tr5, [r7, #336]\t@ 0x150\n+\tstr.w\tr5, [r7, #344]\t@ 0x158\n+\tvstr\td5, [r7, #632]\t@ 0x278\n \tadd.w\tr5, r9, r4\n-\tvmov.f64\td21, d25\n-\tvfma.f64\td25, d20, d12\n-\tvfnms.f64\td21, d1, d20\n-\tadd\tr4, ip\n-\tstr.w\tr4, [r7, #352]\t@ 0x160\n-\tvcvt.f64.f32\td24, s13\n-\tldr.w\tr4, [r7, #292]\t@ 0x124\n-\tvmov.f64\td20, d29\n-\tstr.w\tr0, [r7, #428]\t@ 0x1ac\n-\tadd\tr2, ip\n+\tadd\tr4, lr\n+\tstr.w\tr5, [r7, #352]\t@ 0x160\n+\tstr.w\tr4, [r7, #392]\t@ 0x188\n+\tvadd.f64\td3, d7, d9\n+\tldr.w\tr4, [r7, #268]\t@ 0x10c\n+\tvsub.f64\td7, d7, d9\n+\tvmov.f64\td9, #80\t@ 0x3e800000 0.250\n+\tvsub.f64\td0, d4, d0\n \tadd\tr4, r6\n-\tstr.w\tr5, [r7, #340]\t@ 0x154\n+\tvmov.f64\td4, d10\n+\tvmls.f64\td4, d1, d9\n \tadd.w\tr0, r9, r4\n-\tadd\tr4, ip\n-\tstr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr4, [r7, #300]\t@ 0x12c\n-\tvadd.f64\td21, d19, d21\n-\tvadd.f64\td19, d19, d25\n-\tadds\tr5, r4, r6\n-\tldr.w\tr4, [r7, #304]\t@ 0x130\n-\tstr.w\tr0, [r7, #464]\t@ 0x1d0\n+\tvadd.f64\td1, d1, d10\n+\tldr.w\tr5, [r7, #276]\t@ 0x114\n+\tadd\tr4, lr\n+\tstr.w\tr4, [r7, #640]\t@ 0x280\n+\tldr.w\tr4, [r7, #280]\t@ 0x118\n+\tadd\tr5, r6\n+\tstr.w\tr0, [r7, #616]\t@ 0x268\n \tadd.w\tr0, r9, r5\n \tadd\tr4, r6\n-\tstr.w\tr0, [r7, #344]\t@ 0x158\n-\tvcvt.f32.f64\ts13, d19\n-\tvsub.f64\td19, d27, d17\n-\tadd.w\tr0, r5, ip\n-\tadd.w\tr5, r9, r4\n-\tadd\tr4, ip\n-\tstr.w\tr4, [r7, #384]\t@ 0x180\n-\tldr.w\tr4, [r7, #308]\t@ 0x134\n-\tvadd.f64\td17, d27, d17\n-\tvcvt.f32.f64\ts12, d19\n-\tstr.w\tr0, [r7, #372]\t@ 0x174\n+\tstr.w\tr0, [r7, #400]\t@ 0x190\n+\tadd.w\tr0, r9, r4\n+\tadd\tr4, lr\n+\tstr.w\tr4, [r7, #504]\t@ 0x1f8\n+\tvcvt.f32.f64\ts2, d1\n+\tldr.w\tr4, [r7, #284]\t@ 0x11c\n+\tvmov.f64\td9, d11\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tadd\tfp, lr\n+\tstr.w\tr0, [r7, #408]\t@ 0x198\n \tadd\tr4, r6\n-\tstr.w\tr1, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tadd\tsl, lr\n+\tvldr\td5, [r7, #760]\t@ 0x2f8\n+\tadd\tip, lr\n+\tadd\tr6, r0\n \tadd.w\tr0, r9, r4\n-\tstr.w\tr0, [r7, #368]\t@ 0x170\n-\tldr.w\tr0, [r7, #320]\t@ 0x140\n-\tadd.w\tr1, r9, r3\n-\tstr.w\tr5, [r7, #356]\t@ 0x164\n-\tadd\tr3, ip\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n-\tadd\tr4, ip\n-\tvldr\ts14, [r1, #-4]\n-\tvstr\ts12, [r0, #-4]\n-\tvcvt.f32.f64\ts12, d17\n-\tadd\tr6, r5\n-\tvcvt.f64.f32\td30, s14\n-\tvldr\ts14, [lr, #-4]\n-\tvstr\ts12, [r1, #-4]\n-\tldr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tvcvt.f64.f32\td28, s14\n-\tvcvt.f32.f64\ts14, d21\n-\tldr.w\tr0, [r7, #336]\t@ 0x150\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tvstr\ts13, [r1, #-4]\n-\tldr.w\tr1, [r7, #332]\t@ 0x14c\n-\tvstr\ts14, [r1, #-4]\n-\tldr.w\tr1, [r7, #428]\t@ 0x1ac\n+\tstr.w\tr0, [r7, #432]\t@ 0x1b0\n+\tadd\tr5, lr\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tvmul.f64\td0, d0, d5\n+\tvstr\ts2, [r1, #-4]\n+\tadd\tr4, lr\n+\tadd\tr1, r0\n+\tldr.w\tr0, [r7, #508]\t@ 0x1fc\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tvldr\ts3, [r0, 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d6\n+\tvcvt.f32.f64\ts2, d1\n+\tvstr\ts12, [r1, #-4]\n+\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tvstr\ts2, [r1, #-4]\n+\tldr.w\tr1, [r7, #600]\t@ 0x258\n+\tvstr\ts7, [r1, #-4]\n+\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tvstr\ts6, [r2, #-4]\n+\tvldr\ts4, [r5, #-4]\n+\tvldr\ts6, [r1, #-4]\n+\tvldr\ts13, [r7, #304]\t@ 0x130\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\ts11, [r7, #292]\t@ 0x124\n+\tvcvt.f64.f32\td3, s6\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tvstr\ts13, [r5, #-4]\n+\tvldr\ts13, [r4, #-4]\n+\tvstr\ts11, [r4, #-4]\n+\tvldr\td5, [r7, #584]\t@ 0x248\n+\tvcvt.f64.f32\td8, s13\n+\tvadd.f64\td6, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tldr.w\tr5, [r7, #700]\t@ 0x2bc\n+\tvsub.f64\td10, d5, d13\n+\tvadd.f64\td4, d5, d13\n+\tvmul.f64\td13, d15, d9\n+\tvmul.f64\td9, d14, d9\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tvmla.f64\td13, d14, d7\n+\tvmul.f64\td12, d15, d7\n+\tvadd.f64\td7, d2, d3\n+\tvsub.f64\td2, d2, d3\n+\tvadd.f64\td3, d6, d11\n+\tvsub.f64\td6, d6, d11\n+\tvldr\td11, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n+\tvmul.f64\td1, d6, d11\n+\tvadd.f64\td6, d7, d4\n+\tvsub.f64\td4, d7, d4\n+\tvmov.f64\td7, d0\n+\tvmul.f64\td4, d4, d11\n+\tvmov.f64\td11, #80\t@ 0x3e800000 0.250\n+\tvmls.f64\td7, d3, d11\n+\tvadd.f64\td3, d3, d0\n+\tvmul.f64\td0, d14, d10\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts6, [r2, #-4]\n+\tvmov.f64\td3, d8\n+\tvmls.f64\td3, d6, d11\n+\tvadd.f64\td6, d6, d8\n+\tvmul.f64\td8, d15, d10\n+\tadd\tr2, r0\n+\tvmla.f64\td8, d14, d2\n+\tvmul.f64\td2, d15, d2\n+\tstr.w\tr2, [r7, #676]\t@ 0x2a4\n+\tvcvt.f32.f64\ts12, d6\n+\tldr.w\tr2, [r7, #512]\t@ 0x200\n+\tvstr\ts12, [r5, #-4]\n+\tvadd.f64\td10, d4, d3\n+\tvadd.f64\td6, d1, d7\n+\tvsub.f64\td3, d3, d4\n+\tvsub.f64\td7, d7, d1\n+\tvsub.f64\td4, d12, d9\n+\tvsub.f64\td1, d9, d12\n+\tadd\tr5, r0\n+\tldr.w\tr0, [r7, #560]\t@ 0x230\n+\tstr.w\tr5, [r7, #700]\t@ 0x2bc\n+\tvadd.f64\td4, d4, d3\n+\tvadd.f64\td1, d1, d3\n+\tvsub.f64\td3, d0, d2\n+\tvsub.f64\td2, d2, d0\n+\tvcvt.f32.f64\ts8, d4\n+\tvadd.f64\td3, d3, d7\n+\tvcvt.f32.f64\ts2, d1\n+\tvadd.f64\td2, d2, d7\n+\tvsub.f64\td7, d6, d8\n+\tvadd.f64\td6, d6, d8\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts14, d7\n+\tvcvt.f32.f64\ts4, d2\n+\tvcvt.f32.f64\ts12, d6\n+\tvstr\ts14, [r2, #-4]\n+\tvadd.f64\td7, d13, d10\n+\tvsub.f64\td10, d10, d13\n+\tvstr\ts12, [r3, #-4]\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tvstr\ts6, [r0, #-4]\n+\tvcvt.f32.f64\ts14, d7\n+\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\tvcvt.f32.f64\ts20, d10\n+\tvstr\ts14, [r3, #-4]\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tvstr\ts20, [r1, #-4]\n+\tvstr\ts8, [r0, #-4]\n+\tldr.w\tr0, [r7, #608]\t@ 0x260\n+\tvstr\ts2, [r3, #-4]\n+\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tvstr\ts4, [r0, #-4]\n+\tcmp\tr3, r4\n+\tbne.w\tc4aa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x39ce>\n+\tldrd\tsl, fp, [r7, #144]\t@ 0x90\n+\tldr.w\tr0, [r7, #768]\t@ 0x300\n+\tldr.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr2, [r7, #428]\t@ 0x1ac\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr3, [r7, #784]\t@ 0x310\n \tcmp\tsl, r3\n-\tble.n\tc91c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4230>\n-\tadd\tr3, fp\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tldr\tr2, [r7, #116]\t@ 0x74\n+\tldr\tr2, [r7, #96]\t@ 0x60\n+\titt\tgt\n+\taddgt\tr3, fp\n+\tstrgt.w\tr3, [r7, #784]\t@ 0x310\n+\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n \tcmp\tr3, r2\n-\tbne.w\tbc4c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3560>\n-\tldr\tr6, [r7, #104]\t@ 0x68\n-\tmov\tlr, r0\n-\tldr.w\tr3, [r7, #260]\t@ 0x104\n-\tmov\tr8, r9\n-\tldr\tr0, [r7, #100]\t@ 0x64\n-\tsubs\tr6, #1\n-\tmov\tr4, ip\n-\tadd\tr0, r3\n-\tadds\tr3, r6, #1\n-\tbne.w\tbc30 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3544>\n-\tmov\tr4, r9\n-\tldr\tr3, [r7, #28]\n-\tldrd\tr2, ip, [r7, #20]\n-\tldrd\tr9, r1, [r7, #12]\n-\tldr.w\tfp, [r7, #8]\n-\tldr.w\tr0, [r7, #244]\t@ 0xf4\n-\tadd\tr2, ip\n-\tldr\tr5, [r7, #108]\t@ 0x6c\n-\tadd\tr9, ip\n-\tsubs\tr0, #1\n-\tstr.w\tr0, [r7, #244]\t@ 0xf4\n-\tsub.w\tr5, r5, ip\n-\tadds\tr0, #1\n-\tstr\tr5, [r7, #108]\t@ 0x6c\n-\tbne.w\tbbe2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x34f6>\n-\tmov\tr8, r4\n-\tldr\tr4, [r7, #32]\n-\tldrd\tsl, r0, [r7, #36]\t@ 0x24\n-\tmov\tlr, r3\n-\tldr.w\tr3, [r7, #208]\t@ 0xd0\n-\tldr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tsubs\tr2, r3, #1\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tldr.w\tr6, [r7, #360]\t@ 0x168\n-\tadd\tr0, r3\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tadd\tr5, r6\n-\tstr.w\tr5, [r7, #444]\t@ 0x1bc\n+\tbne.w\tc154 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3678>\n+\tldrd\tr5, r1, [r7, #84]\t@ 0x54\n+\tmov\tfp, r0\n+\tldr\tr0, [r7, #80]\t@ 0x50\n+\tmov\tr6, r9\n+\tsubs\tr1, #1\n+\tmov\tip, lr\n+\tadd\tr0, r5\n+\tadds\tr3, r1, #1\n+\tbne.w\tc136 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x365a>\n+\tldr.w\tr8, [r7, #12]\n+\tmov\tfp, r9\n+\tldr.w\tsl, [r7, #8]\n+\tmov\tr9, lr\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [r7, #112]\t@ 0x70\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n \tadd\tsl, r3\n-\tldr\tr5, [r7, #112]\t@ 0x70\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n-\tsub.w\tfp, fp, r6\n-\tstr.w\tr2, [r7, #208]\t@ 0xd0\n-\tadds\tr2, #1\n-\tadd\tr5, r3\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tstr\tr5, [r7, #112]\t@ 0x70\n-\tadd\tr4, r3\n-\tbeq.w\td72e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5042>\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tcmp\tr2, #0\n-\tble.w\tbbac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x34c0>\n-\tvldr\td17, [r7, #88]\t@ 0x58\n-\tcmp.w\tip, #0\n-\tvldr\td16, [r0]\n-\tvldr\td15, [sl]\n-\tvldr\td14, [r5]\n-\tvmul.f64\td16, d17, d16\n-\tvldr\td13, [r4]\n-\tvmul.f64\td15, d17, d15\n-\tvldr\td9, [r0, #-8]\n-\tvmul.f64\td14, d17, d14\n-\tvldr\td0, [sl, #-8]\n-\tvmul.f64\td13, d17, d13\n-\tvldr\td2, [r5, #-8]\n-\tvstr\td16, [r7, #192]\t@ 0xc0\n-\tvldr\td16, [r4, #-8]\n-\tvstr\td16, [r7, #200]\t@ 0xc8\n-\tbge.w\tbbb4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x34c8>\n-\tldr.w\tr5, [r7, #444]\t@ 0x1bc\n-\tldr\tr6, [r7, #80]\t@ 0x50\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n-\tsubs\tr2, r5, r6\n-\tcmp\tr6, r5\n-\tudiv\tr3, r2, r3\n-\tstr.w\tr3, [r7, #244]\t@ 0xf4\n-\tble.w\tbbcc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x34e0>\n-\tb.n\tc97c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4290>\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n+\tadd\tr2, r3\n+\tstr\tr2, [r7, #112]\t@ 0x70\n+\tldr\tr2, [r7, #108]\t@ 0x6c\n+\tsub.w\tr3, r2, r3\n+\tstr\tr3, [r7, #108]\t@ 0x6c\n+\tbne.w\tc0fa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x361e>\n+\tldrd\tr5, r6, [r7, #16]\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr.w\tr1, [r7, #648]\t@ 0x288\n+\tldr\tr0, [r7, #52]\t@ 0x34\n+\tadd\tr2, r1\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr\tr2, [r7, #104]\t@ 0x68\n+\tldr.w\tr3, [r7, #180]\t@ 0xb4\n+\tadd\tr2, r0\n+\tstr\tr2, [r7, #104]\t@ 0x68\n+\tldr\tr2, [r7, #48]\t@ 0x30\n+\tsubs\tr3, #1\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tadd\tr6, r2\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n+\tstr.w\tr3, [r7, #180]\t@ 0xb4\n+\tadds\tr3, #1\n+\tadd\tr5, r2\n+\tldr\tr2, [r7, #100]\t@ 0x64\n+\tadd\tr2, r0\n+\tstr\tr2, [r7, #100]\t@ 0x64\n+\tldr.w\tr2, [r7, #236]\t@ 0xec\n+\tsub.w\tr2, r2, r1\n+\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tbeq.w\te1cc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x56f0>\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tcmp\tr3, #0\n+\tble.w\tc0be <__gridxc_gpfa_core_sp_MOD_gpfa_+0x35e2>\n+\tldr\tr3, [r7, #104]\t@ 0x68\n+\tldr\tr2, [r7, #100]\t@ 0x64\n+\tvldr\td7, [r6]\n+\tvldr\td5, [r5]\n+\tvldr\td3, [r3, #-8]\n+\tvldr\td4, [r2]\n+\tvldr\td6, [r3]\n+\tvstr\td3, [r7, #776]\t@ 0x308\n+\tvldr\td3, [r6, #-8]\n+\tldr\tr3, [r7, #92]\t@ 0x5c\n+\tvstr\td3, [r7, #488]\t@ 0x1e8\n+\tcmp\tr3, #0\n+\tvldr\td3, [r7, #192]\t@ 0xc0\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td6, d3, d6\n+\tvstr\td7, [r7, #456]\t@ 0x1c8\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td6, [r7, #464]\t@ 0x1d0\n+\tvmul.f64\td6, d3, d5\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvldr\td7, [r5, #-8]\n+\tvstr\td6, [r7, #448]\t@ 0x1c0\n+\tvstr\td7, [r7, #480]\t@ 0x1e0\n+\tvldr\td7, [r2, #-8]\n+\tvstr\td7, [r7, #472]\t@ 0x1d8\n+\tbge.w\tc0c6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x35ea>\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n+\tldr.w\tr4, [r7, #664]\t@ 0x298\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n+\tsubs\tr0, r4, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #176]\t@ 0xb0\n+\tmov\tr8, r0\n+\tcmp\tr3, r4\n+\tble.w\tc0e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3606>\n+\tb.n\tcf9c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x44c0>\n+\tldr.w\tr5, [r7, #756]\t@ 0x2f4\n \tcmp\tr5, #0\n-\tble.w\tc904 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4218>\n-\tldr.w\tr5, [r7, #428]\t@ 0x1ac\n+\tble.w\tcf2e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4452>\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n \tlsls\tr3, r3, #2\n \tlsls\tr6, r6, #2\n-\tstr.w\tr3, [r7, #268]\t@ 0x10c\n-\tstr.w\tr6, [r7, #152]\t@ 0x98\n-\tmov.w\tlr, lr, lsl #2\n-\tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #412]\t@ 0x19c\n-\tldr.w\tr5, [r7, #556]\t@ 0x22c\n+\tstr.w\tr3, [r7, #244]\t@ 0xf4\n+\tstr.w\tr6, [r7, #144]\t@ 0x90\n \tlsls\tr2, r2, #2\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tlsls\tr5, r5, #2\n+\tstr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n+\tmov.w\tip, ip, lsl #2\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tmov.w\tr8, r8, lsl #2\n-\tldr.w\tr6, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr6, [r7, #616]\t@ 0x268\n \tlsls\tr4, r4, #2\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\tstr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr5, [r7, #760]\t@ 0x2f8\n \tlsls\tr6, r6, #2\n-\tstr.w\tr6, [r7, #144]\t@ 0x90\n+\tstr.w\tr6, [r7, #140]\t@ 0x8c\n \tlsls\tr6, r3, #2\n \tstr.w\tr6, [r7, #136]\t@ 0x88\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #556]\t@ 0x22c\n-\tldr.w\tr5, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr6, [r7, #464]\t@ 0x1d0\n-\tstr.w\tlr, [r7, #216]\t@ 0xd8\n-\tmov.w\tlr, #0\n+\tstr.w\tr5, [r7, #768]\t@ 0x300\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr6, [r7, #668]\t@ 0x29c\n+\tstr.w\tip, [r7, #148]\t@ 0x94\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #188]\t@ 0xbc\n-\tldr.w\tr5, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr5, [r7, #168]\t@ 0xa8\n+\tldr.w\tr5, [r7, #632]\t@ 0x278\n \tlsls\tr6, r6, #2\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #184]\t@ 0xb8\n-\tldr.w\tr5, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr5, [r7, #164]\t@ 0xa4\n+\tldr.w\tr5, [r7, #708]\t@ 0x2c4\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #232]\t@ 0xe8\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr5, [r7, #212]\t@ 0xd4\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #256]\t@ 0x100\n-\tldr.w\tr5, [r7, #484]\t@ 0x1e4\n+\tstr.w\tr5, [r7, #232]\t@ 0xe8\n+\tldr.w\tr5, [r7, #700]\t@ 0x2bc\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #220]\t@ 0xdc\n-\tldr.w\tr5, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr5, [r7, #200]\t@ 0xc8\n+\tldr.w\tr5, [r7, #684]\t@ 0x2ac\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #180]\t@ 0xb4\n-\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr5, [r7, #172]\t@ 0xac\n+\tldr.w\tr5, [r7, #624]\t@ 0x270\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #168]\t@ 0xa8\n-\tldr.w\tr5, [r7, #476]\t@ 0x1dc\n+\tstr.w\tr5, [r7, #160]\t@ 0xa0\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #176]\t@ 0xb0\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr5, [r7, #156]\t@ 0x9c\n+\tldr.w\tr5, [r7, #688]\t@ 0x2b0\n \tlsls\tr5, r5, #2\n-\tstr.w\tr5, [r7, #164]\t@ 0xa4\n-\tstr.w\tr6, [r7, #160]\t@ 0xa0\n-\tstr.w\tr2, [r7, #132]\t@ 0x84\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n-\tldr.w\tr5, [r7, #412]\t@ 0x19c\n-\tlsls\tr2, r2, #2\n+\tstr.w\tr5, [r7, #152]\t@ 0x98\n+\tstr.w\tr6, [r7, #132]\t@ 0x84\n \tstr.w\tr2, [r7, #128]\t@ 0x80\n-\tlsls\tr2, r1, #2\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tlsls\tr2, r2, #2\n \tstr\tr2, [r7, #124]\t@ 0x7c\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n+\tlsls\tr2, r1, #2\n+\tstr\tr2, [r7, #120]\t@ 0x78\n+\tldr.w\tr2, [r7, #676]\t@ 0x2a4\n \tadd.w\tr1, r9, r8\n-\tstr.w\tr1, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr1, [r7, #676]\t@ 0x2a4\n+\tadd.w\tr1, lr, r8\n+\tstr.w\tr1, [r7, #704]\t@ 0x2c0\n \tadd.w\tr1, r9, r5\n-\tstr.w\tr1, [r7, #476]\t@ 0x1dc\n-\tadd.w\tr1, ip, r5\n \tlsls\tr2, r2, #2\n-\tstr.w\tr1, [r7, #488]\t@ 0x1e8\n-\tstr\tr2, [r7, #120]\t@ 0x78\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tstr\tr2, [r7, #116]\t@ 0x74\n+\tadd.w\tr1, lr, r5\n+\tldr.w\tr2, [r7, #784]\t@ 0x310\n+\tadd.w\tr5, lr, r4\n+\tstr.w\tr1, [r7, #708]\t@ 0x2c4\n \tadd.w\tr1, r9, r3\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tadd\tr8, ip\n-\tstr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tadd.w\tr1, ip, r3\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tstr.w\tr1, [r7, #492]\t@ 0x1ec\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n \tlsls\tr2, r2, #2\n+\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tmov.w\tr8, #0\n \tadd.w\tr1, r9, r3\n-\tstr.w\tr1, [r7, #484]\t@ 0x1e4\n-\tadd.w\tr1, ip, r3\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tvldr\td16, [r7, #192]\t@ 0xc0\n-\tvldr\td5, [r7, #200]\t@ 0xc8\n-\tadd\tr3, r9\n-\tstr.w\tr2, [r7, #236]\t@ 0xec\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #244]\t@ 0xf4\n+\tstr.w\tr2, [r7, #216]\t@ 0xd8\n \tadd\tr2, r9\n-\tstr.w\tr1, [r7, #500]\t@ 0x1f4\n+\tadd\tr3, r9\n+\tstr.w\tr1, [r7, #760]\t@ 0x2f8\n+\tstr.w\tr3, [r7, #432]\t@ 0x1b0\n \tadd.w\tr1, r9, r4\n-\tstr.w\tr3, [r7, #392]\t@ 0x188\n \tmovs\tr3, #1\n-\tstr.w\tr1, [r7, #384]\t@ 0x180\n-\tadd.w\tr1, ip, r4\n-\tstr.w\tr2, [r7, #388]\t@ 0x184\n-\tstr.w\tr1, [r7, #396]\t@ 0x18c\n-\tstr.w\tr3, [r7, #468]\t@ 0x1d4\n-\tstrd\tsl, fp, [r7]\n-\tstr.w\tr0, [r7, #556]\t@ 0x22c\n-\tvstr\td16, [r7, #536]\t@ 0x218\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr5, [r7, #484]\t@ 0x1e4\n-\tvldr\ts15, [r2, #-4]\n-\tvldr\ts9, [r3, #-4]\n+\tvldr\td13, [r7, #184]\t@ 0xb8\n+\tvldr\td12, [r7, #488]\t@ 0x1e8\n+\tvldr\td11, [r7, #480]\t@ 0x1e0\n+\tvldr\td10, [r7, #472]\t@ 0x1d8\n+\tvldr\td9, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr2, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tstr.w\tr5, [r7, #408]\t@ 0x198\n+\tstr.w\tfp, [r7, #4]\n+\tstr.w\tsl, [r7]\n+\tvldr\td7, [r7, #456]\t@ 0x1c8\n+\tvldr\td6, [r7, #448]\t@ 0x1c0\n+\tvldr\td5, [r7, #440]\t@ 0x1b8\n+\tldr.w\tr3, [r7, #676]\t@ 0x2a4\n+\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr4, [r7, #684]\t@ 0x2ac\n+\tldr.w\tr6, [r7, #688]\t@ 0x2b0\n+\tvldr\ts7, [r3, #-4]\n+\tvldr\ts9, [r2, #-4]\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tvcvt.f64.f32\td2, s7\n \tvldr\ts6, [r4, #-4]\n-\tvmov.f32\ts12, s15\n-\tvldr\ts15, [r5, #-4]\n-\tldr.w\tr1, [r7, #492]\t@ 0x1ec\n-\tvcvt.f64.f32\td26, s9\n-\tldr.w\tr5, [r7, #388]\t@ 0x184\n-\tvcvt.f64.f32\td18, s6\n-\tvcvt.f64.f32\td24, s15\n-\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n-\tvcvt.f64.f32\td17, s12\n-\tldr.w\tr4, [r7, #500]\t@ 0x1f4\n-\tvldr\ts14, [r1, #-4]\n-\tvldr\ts6, [r5, #-4]\n-\tvadd.f64\td23, d18, d24\n-\tvsub.f64\td18, d18, d24\n-\tvadd.f64\td19, d26, d17\n-\tldr.w\tr1, [r7, #556]\t@ 0x22c\n-\tvmov.f32\ts13, s14\n-\tvldr\ts7, [r8, #-4]\n-\tvcvt.f64.f32\td24, s6\n+\tvcvt.f64.f32\td8, s9\n+\tldr.w\tr4, [r7, #760]\t@ 0x2f8\n+\tldr.w\tr5, [r7, #216]\t@ 0xd8\n \tvldr\ts8, [r6, #-4]\n-\tvldr\ts14, [r4, #-4]\n-\tvsub.f64\td26, d26, d17\n-\tadds\tr0, r5, r1\n-\tvadd.f64\td17, d19, d23\n-\tvmul.f64\td29, d8, d18\n-\tstr.w\tr0, [r7, #388]\t@ 0x184\n-\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tvcvt.f64.f32\td1, s6\n+\tvstr\td2, [r7, #616]\t@ 0x268\n+\tvldr\ts5, [r2, #-4]\n+\tldr.w\tr6, [r7, #672]\t@ 0x2a0\n \tvcvt.f64.f32\td4, s8\n-\tvcvt.f64.f32\td7, s14\n-\tvcvt.f64.f32\td22, s7\n-\tvcvt.f64.f32\td16, s13\n-\tadd.w\tr3, lr, r0\n-\tadd\tr3, ip\n-\tvmov.f64\td21, d24\n-\tvfms.f64\td21, d17, d31\n-\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvmov.f64\td20, d29\n-\tvsub.f64\td19, d19, d23\n-\tvfnms.f64\td20, d1, d26\n-\tvadd.f64\td25, d16, d7\n-\tvadd.f64\td23, d22, d4\n+\tvldr\ts4, [r4, #-4]\n+\tadd.w\tr4, r8, r5\n \tadds\tr6, #1\n-\tvsub.f64\td22, d22, d4\n-\tstr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvldr\ts9, [r3, #-4]\n-\tvadd.f64\td17, d17, d24\n-\tldr.w\tr6, [r7, #396]\t@ 0x18c\n-\tvsub.f64\td16, d16, d7\n-\tvadd.f64\td27, d23, d25\n-\tvsub.f64\td23, d23, d25\n-\tvcvt.f64.f32\td24, s9\n-\tvmov.f64\td28, d21\n-\tvfma.f64\td28, d10, d19\n-\tvfma.f64\td21, d19, d11\n-\tvldr\ts15, [r6, #-4]\n-\tvmov.f64\td19, d20\n-\tvfma.f64\td19, d27, d31\n-\tvmul.f64\td18, d1, d18\n-\tvfma.f64\td18, d8, d26\n-\tvfma.f64\td29, d26, d12\n-\tldr.w\tr2, [r7, #384]\t@ 0x180\n-\tvcvt.f64.f32\td30, s15\n-\tvcvt.f32.f64\ts15, d17\n-\tvmov.f64\td17, d24\n-\tldr.w\tr4, [r7, #392]\t@ 0x188\n-\tvfms.f64\td17, d27, d31\n-\tadds\tr0, r2, r1\n-\tvadd.f64\td26, d27, d24\n-\tvldr\ts7, [r2, #-4]\n-\tvstr\ts15, [r5, #-4]\n-\tvsub.f64\td19, d19, d24\n-\tvldr\ts15, [r4, #-4]\n-\tvfma.f64\td19, d10, d23\n-\tvcvt.f64.f32\td25, s7\n-\tvcvt.f32.f64\ts9, d26\n-\tvcvt.f64.f32\td7, s15\n-\tvmov.f64\td24, d17\n-\tvfma.f64\td17, d23, d11\n-\tvfma.f64\td24, d10, d23\n-\tvmul.f64\td23, d8, d16\n-\tvmul.f64\td16, d1, d16\n-\tvstr\ts9, [r3, #-4]\n-\tvfma.f64\td16, d8, d22\n-\tvmul.f64\td19, d19, d14\n-\tvmov.f64\td26, d23\n-\tvfma.f64\td23, d22, d12\n-\tvfnms.f64\td26, d1, d22\n-\tvadd.f64\td20, d20, d17\n-\tvadd.f64\td17, d17, d29\n-\tvsub.f64\td29, d18, d24\n-\tvsub.f64\td27, d28, d16\n-\tvadd.f64\td16, d28, d16\n-\tvnmul.f64\td22, d15, d20\n-\tvmul.f64\td17, d17, d2\n-\tvmul.f64\td20, d0, d20\n-\tvmul.f64\td29, d29, d13\n-\tvadd.f64\td26, d21, d26\n-\tvadd.f64\td21, d21, d23\n-\tvadd.f64\td23, d18, d24\n-\tvsub.f64\td24, d24, d18\n-\tvfma.f64\td29, d16, d5\n-\tvfma.f64\td19, d26, d2\n-\tvfma.f64\td22, d21, d0\n-\tvfma.f64\td17, d26, d14\n-\tvfma.f64\td20, d21, d15\n-\tvmul.f64\td24, d24, d5\n-\tvfma.f64\td24, d16, d13\n-\tvcvt.f32.f64\ts13, d29\n-\tvcvt.f32.f64\ts9, d19\n-\tvcvt.f32.f64\ts7, d22\n-\tvcvt.f32.f64\ts8, d17\n-\tvmov.f64\td22, d25\n-\tvcvt.f32.f64\ts12, d24\n-\tvstr\ts9, [r7, #284]\t@ 0x11c\n-\tvcvt.f32.f64\ts9, d20\n-\tvldr\td19, [r7, #536]\t@ 0x218\n-\tstr.w\tr0, [r7, #384]\t@ 0x180\n-\tadds\tr0, r4, r1\n-\tstr.w\tr0, [r7, #392]\t@ 0x188\n-\tvnmul.f64\td18, d19, d23\n-\tldr.w\tr0, [r7, #232]\t@ 0xe8\n-\tvfma.f64\td18, d27, d9\n-\tvmul.f64\td23, d9, d23\n-\tvfma.f64\td23, d27, d19\n-\tvstr\ts8, [r7, #280]\t@ 0x118\n-\tvstr\ts13, [r7, #272]\t@ 0x110\n-\tvcvt.f32.f64\ts6, d18\n-\tvcvt.f32.f64\ts8, d23\n-\tvstr\ts6, [r2, #-4]\n-\tvstr\ts7, [r4, #-4]\n-\tadd.w\tr4, lr, r0\n-\tldr.w\tr0, [r7, #256]\t@ 0x100\n-\tadd.w\tr1, r0, lr\n-\tldr.w\tr0, [r7, #188]\t@ 0xbc\n-\tadd.w\tr2, lr, r0\n-\tldr.w\tr0, [r7, #184]\t@ 0xb8\n-\tadd.w\tr3, lr, r0\n-\tldr.w\tr0, [r7, #268]\t@ 0x10c\n-\tadd.w\tsl, r9, r3\n-\tadd.w\tr5, lr, r0\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tadd\tr5, ip\n-\tadds\tr0, r6, r0\n-\tstr.w\tr0, [r7, #396]\t@ 0x18c\n-\tadd.w\tr0, r9, r1\n-\tvldr\ts7, [r5, #-4]\n-\tvstr\ts8, [r6, #-4]\n-\tvstr\ts9, [r5, #-4]\n-\tadd.w\tr5, r9, r4\n-\tstr.w\tr5, [r7, #368]\t@ 0x170\n-\tadd\tr4, ip\n-\tvcvt.f64.f32\td28, s7\n-\tvldr\ts9, [r5, #-4]\n-\tmov\tr5, r0\n-\tadd.w\tr0, ip, r1\n-\tstr.w\tr0, [r7, #332]\t@ 0x14c\n-\tvldr\ts8, [r4, #-4]\n-\tvcvt.f64.f32\td17, s9\n-\tvldr\ts9, [r5, #-4]\n-\tldr.w\tr1, [r7, #220]\t@ 0xdc\n-\tstr.w\tr5, [r7, #356]\t@ 0x164\n-\tvcvt.f64.f32\td16, s9\n-\tvldr\ts9, [r0, #-4]\n-\tadd.w\tr0, r9, r2\n-\tstr.w\tr0, [r7, #340]\t@ 0x154\n-\tadd\tr2, ip\n-\tadd\tr1, lr\n-\tvcvt.f64.f32\td19, s9\n-\tadd.w\tfp, r9, r1\n-\tvldr\ts9, [r0, #-4]\n-\tmov\tr0, sl\n-\tvsub.f64\td18, d17, d16\n-\tvadd.f64\td17, d17, d16\n-\tvcvt.f64.f32\td16, s8\n-\tadd.w\tsl, ip, r3\n-\tvcvt.f64.f32\td21, s9\n-\tvldr\ts9, [r0, #-4]\n-\tvldr\ts8, [r2, #-4]\n-\tvmul.f64\td24, d8, d18\n-\tvmul.f64\td18, d1, d18\n-\tvadd.f64\td20, d16, d19\n-\tvsub.f64\td16, d16, d19\n-\tvcvt.f64.f32\td19, s9\n-\tvldr\ts9, [sl, #-4]\n-\tstr.w\tr0, [r7, #372]\t@ 0x174\n-\tmov\tr0, fp\n-\tstr.w\tsl, [r7, #336]\t@ 0x150\n-\tadd.w\tfp, ip, r1\n-\tldr.w\tr5, [r7, #216]\t@ 0xd8\n-\tvsub.f64\td23, d21, d19\n-\tvadd.f64\td19, d21, d19\n-\tadd.w\tr3, lr, r5\n+\tvstr\td8, [r7, #600]\t@ 0x258\n+\tstr.w\tr6, [r7, #672]\t@ 0x2a0\n+\tvcvt.f64.f32\td8, s5\n+\tldr.w\tr6, [r7, #700]\t@ 0x2bc\n+\tadd\tr4, lr\n \tldr.w\tr5, [r7, #168]\t@ 0xa8\n-\tldr.w\tr1, [r7, #472]\t@ 0x1d8\n-\tadd.w\tsl, lr, r5\n-\tldr.w\tr5, [r7, #176]\t@ 0xb0\n-\tvadd.f64\td21, d19, d17\n-\tvsub.f64\td19, d19, d17\n-\tvmov.f64\td17, d24\n-\tvfma.f64\td18, d8, d23\n-\tvfnms.f64\td17, d1, d23\n-\tvfma.f64\td24, d23, d12\n-\tvcvt.f64.f32\td23, s9\n-\tvldr\ts7, [r0, #-4]\n-\tvfms.f64\td22, d21, d31\n-\tvadd.f64\td21, d25, d21\n-\tstr.w\tr0, [r7, #352]\t@ 0x160\n-\tadd.w\tr6, lr, r5\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tldr.w\tr5, [r7, #180]\t@ 0xb4\n-\tstr.w\tfp, [r7, #456]\t@ 0x1c8\n-\tadd.w\tfp, r9, sl\n-\tadd\tr5, lr\n-\tadd\tsl, ip\n-\tstr.w\tsl, [r7, #324]\t@ 0x144\n-\tadd.w\tsl, r9, r6\n-\tstr.w\tsl, [r7, #464]\t@ 0x1d0\n-\tadd.w\tsl, ip, r6\n-\tvmov.f64\td27, d22\n-\tvfma.f64\td22, d19, d11\n-\tvfma.f64\td27, d10, d19\n-\tvcvt.f64.f32\td19, s8\n-\tvcvt.f32.f64\ts8, d21\n-\tstr.w\tsl, [r7, #416]\t@ 0x1a0\n-\tadd.w\tsl, r9, r5\n-\tstr.w\tsl, [r7, #448]\t@ 0x1c0\n-\tadd.w\tsl, ip, r5\n-\tldr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tvadd.f64\td21, d19, d23\n-\tstr.w\tfp, [r7, #328]\t@ 0x148\n-\tvsub.f64\td19, d19, d23\n-\tvmov.f64\td23, d17\n-\tvstr\ts8, [r1, #-4]\n-\tadd\tr1, r0\n-\tstr.w\tr1, [r7, #472]\t@ 0x1d8\n-\tadd.w\tr1, r9, r3\n-\tvadd.f64\td26, d21, d20\n-\tvsub.f64\td21, d21, d20\n-\tvmov.f64\td20, d30\n-\tadd\tr3, ip\n-\tvldr\ts8, [r1, #-4]\n-\tstr.w\tsl, [r7, #420]\t@ 0x1a4\n-\tvadd.f64\td25, d30, d26\n-\tvfma.f64\td23, d26, d31\n-\tvfms.f64\td20, d26, d31\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tvcvt.f32.f64\ts9, d25\n-\tvsub.f64\td23, d23, d30\n-\tvcvt.f64.f32\td30, s8\n-\tvldr\ts8, [r5, #-4]\n-\tvmov.f64\td25, d20\n-\tvstr\ts9, [r8, #-4]\n-\tvfma.f64\td25, d10, d21\n-\tvldr\ts9, [r3, #-4]\n-\tvfma.f64\td20, d21, d11\n-\tvfma.f64\td23, d10, d21\n+\tvcvt.f64.f32\td2, s4\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tadd.w\tr2, r8, r5\n \tldr.w\tr5, [r7, #164]\t@ 0xa4\n-\tadd\tr8, r0\n-\tvcvt.f64.f32\td21, s9\n-\tadd.w\tfp, lr, r5\n+\tvstr\td8, [r7, #584]\t@ 0x248\n+\tvldr\ts16, [r4, #-4]\n+\tadd.w\tip, r8, r5\n+\tvldr\ts17, [r6, #-4]\n+\tldr.w\tr5, [r7, #212]\t@ 0xd4\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tadd.w\tr6, r8, r5\n+\tvstr\ts16, [r7, #768]\t@ 0x300\n+\tldr.w\tr5, [r7, #232]\t@ 0xe8\n+\tvcvt.f64.f32\td8, s17\n+\tvldr\ts7, [r3, #-4]\n+\tadd.w\tr3, r5, r8\n+\tldr.w\tr5, [r7, #244]\t@ 0xf4\n+\tvldr\ts1, [r1, #-4]\n+\tvstr\td8, [r7, #392]\t@ 0x188\n+\tadd.w\tr1, r8, r5\n+\tadd.w\tr5, r9, r2\n+\tstr.w\tr5, [r7, #352]\t@ 0x160\n+\tvldr\ts16, [r7, #768]\t@ 0x300\n+\tadd.w\tr5, r9, ip\n+\tadd\tip, lr\n+\tstr.w\tip, [r7, #568]\t@ 0x238\n+\tadd.w\tip, r9, r6\n+\tstr.w\tip, [r7, #640]\t@ 0x280\n+\tvcvt.f64.f32\td8, s16\n+\tadd.w\tip, lr, r6\n+\tldr.w\tr6, [r7, #696]\t@ 0x2b8\n+\tadd\tr2, lr\n+\tstr.w\tr5, [r7, #668]\t@ 0x29c\n+\tvcvt.f64.f32\td3, s7\n+\tldr.w\tr5, [r7, #200]\t@ 0xc8\n+\tvcvt.f64.f32\td0, s1\n+\tvstr\td8, [r7, #768]\t@ 0x300\n+\tadd\tr1, lr\n+\tvldr\ts17, [r6, #-4]\n+\tstr.w\tip, [r7, #560]\t@ 0x230\n+\tadd.w\tip, r9, r3\n+\tstr.w\tip, [r7, #624]\t@ 0x270\n+\tadd.w\tip, lr, r3\n+\tadd.w\tr3, r8, r5\n+\tldr.w\tr5, [r7, #172]\t@ 0xac\n+\tvcvt.f64.f32\td8, s17\n+\tstr.w\tr2, [r7, #576]\t@ 0x240\n+\tadd.w\tfp, r8, r5\n+\tldr.w\tr5, [r7, #160]\t@ 0xa0\n+\tldr.w\tr2, [r7, #408]\t@ 0x198\n+\tadd.w\tsl, r8, r5\n+\tldr.w\tr5, [r7, #156]\t@ 0x9c\n+\tstr.w\tip, [r7, #552]\t@ 0x228\n+\tadd.w\tip, r8, r5\n \tldr.w\tr5, [r7, #152]\t@ 0x98\n-\tadd.w\tr0, r9, fp\n-\tstr.w\tr0, [r7, #428]\t@ 0x1ac\n-\tadd\tfp, ip\n-\tadd.w\tsl, lr, r5\n-\tldr.w\tr5, [r7, #144]\t@ 0x90\n-\tvstr\td21, [r7, #344]\t@ 0x158\n-\tvmul.f64\td21, d8, d16\n-\tvmul.f64\td16, d1, d16\n-\tvadd.f64\td17, d17, d20\n-\tvmul.f64\td26, d14, d23\n-\tvfma.f64\td16, d8, d19\n-\tvadd.f64\td20, d20, d24\n-\tadd.w\tr6, lr, r5\n-\tvmov.f64\td23, d21\n-\tvfma.f64\td21, d19, d12\n-\tvfnms.f64\td23, d1, d19\n-\tldr.w\tr5, [r7, #136]\t@ 0x88\n-\tvadd.f64\td19, d18, d25\n-\tadd.w\tr0, r9, sl\n-\tadd\tr5, lr\n-\tvmul.f64\td29, d20, d2\n-\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n-\tadd.w\tr0, r9, r6\n-\tadd\tr6, ip\n-\tstr.w\tr0, [r7, #412]\t@ 0x19c\n-\tstr.w\tr6, [r7, #408]\t@ 0x198\n-\tadd.w\tr6, r9, r5\n-\tstr.w\tr6, [r7, #320]\t@ 0x140\n-\tadd\tr5, ip\n+\tvstr\td8, [r7, #400]\t@ 0x190\n+\tvldr\ts17, [r2, #-4]\n+\tadd.w\tr6, r8, r5\n+\tadd.w\tr5, r9, r3\n+\tstr.w\tr5, [r7, #360]\t@ 0x168\n+\tadd.w\tr5, r9, fp\n+\tadd\tfp, lr\n+\tstr.w\tfp, [r7, #320]\t@ 0x140\n+\tadd.w\tfp, lr, sl\n+\tadd\tsl, r9\n+\tstr.w\tsl, [r7, #548]\t@ 0x224\n+\tadd.w\tsl, lr, ip\n+\tadd\tip, r9\n+\tstr.w\tip, [r7, #312]\t@ 0x138\n+\tadd.w\tip, lr, r6\n+\tstr.w\tip, [r7, #304]\t@ 0x130\n+\tadd.w\tip, r9, r6\n+\tldr.w\tr6, [r7, #148]\t@ 0x94\n+\tvcvt.f64.f32\td8, s17\n+\tstr.w\tfp, [r7, #520]\t@ 0x208\n+\tadd\tr3, lr\n+\tadd.w\tfp, r8, r6\n+\tldr.w\tr6, [r7, #144]\t@ 0x90\n+\tstr.w\tsl, [r7, #296]\t@ 0x128\n+\tadd.w\tsl, r8, r6\n+\tldr.w\tr6, [r7, #140]\t@ 0x8c\n+\tvstr\td8, [r7, #608]\t@ 0x260\n+\tvadd.f64\td8, d0, d3\n+\tvsub.f64\td0, d0, d3\n+\tstr.w\tr5, [r7, #632]\t@ 0x278\n+\tstr.w\tip, [r7, #536]\t@ 0x218\n+\tadd.w\tip, r8, r6\n+\tldr.w\tr6, [r7, #136]\t@ 0x88\n+\tadd.w\tr5, r9, fp\n+\tvldr\td3, [r7, #584]\t@ 0x248\n+\tadd\tfp, lr\n+\tvstr\td0, [r7, #384]\t@ 0x180\n+\tadd\tr6, r8\n+\tvstr\td8, [r7, #592]\t@ 0x250\n+\tvadd.f64\td0, d3, d2\n+\tvsub.f64\td3, d3, d2\n+\tvldr\td8, [r7, #600]\t@ 0x258\n+\tvldr\td2, [r7, #616]\t@ 0x268\n+\tstr.w\tr5, [r7, #528]\t@ 0x210\n+\tadd.w\tr5, r9, sl\n+\tvstr\td3, [r7, #376]\t@ 0x178\n+\tadd\tsl, lr\n+\tvadd.f64\td3, d2, d8\n+\tvsub.f64\td2, d2, d8\n \tstr.w\tr5, [r7, #308]\t@ 0x134\n-\tvadd.f64\td21, d22, d21\n-\tvadd.f64\td23, d22, d23\n-\tldr.w\tr5, [r7, #132]\t@ 0x84\n-\tvcvt.f64.f32\td20, s7\n-\tvcvt.f64.f32\td24, s8\n-\tadd\tr5, lr\n-\tadd\tsl, ip\n-\tadd.w\tr6, r9, r5\n-\tadd\tr5, ip\n-\tvfma.f64\td26, d2, d23\n-\tvfma.f64\td29, d14, d23\n-\tvsub.f64\td23, d27, d16\n-\tstr.w\tr5, [r7, #304]\t@ 0x130\n-\tldr.w\tr5, [r7, #160]\t@ 0xa0\n-\tvadd.f64\td16, d27, d16\n-\tstr.w\tr6, [r7, #312]\t@ 0x138\n-\tadd\tr5, lr\n+\tadd.w\tr5, r9, ip\n+\tadd\tip, lr\n+\tstr.w\tip, [r7, #512]\t@ 0x200\n+\tadd.w\tip, r9, r6\n+\tstr.w\tip, [r7, #292]\t@ 0x124\n+\tvstr\td2, [r7, #616]\t@ 0x268\n+\tvadd.f64\td2, d1, d4\n+\tvsub.f64\td1, d1, d4\n+\tadd.w\tip, lr, r6\n \tldr.w\tr6, [r7, #128]\t@ 0x80\n-\tadd.w\tr0, r9, r5\n-\tadd\tr5, ip\n-\tstr.w\tr5, [r7, #404]\t@ 0x194\n-\tadd\tr6, lr\n+\tstr.w\tip, [r7, #284]\t@ 0x11c\n+\tvmov.f64\td8, d2\n+\tvldr\td2, [r7, #592]\t@ 0x250\n+\tadd\tr6, r8\n+\tstr.w\tr5, [r7, #544]\t@ 0x220\n+\tadd.w\tip, r9, r6\n+\tstr.w\tip, [r7, #288]\t@ 0x120\n+\tvadd.f64\td4, d2, d0\n+\tvsub.f64\td0, d2, d0\n+\tvadd.f64\td2, d3, d8\n+\tvsub.f64\td3, d3, d8\n+\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n+\tadd.w\tip, lr, r6\n+\tldr.w\tr6, [r7, #132]\t@ 0x84\n \tldr\tr5, [r7, #124]\t@ 0x7c\n-\tvcvt.f32.f64\ts6, d26\n-\tvldr\td26, [r7, #536]\t@ 0x218\n-\tadd\tr5, lr\n-\tstr.w\tr0, [r7, #316]\t@ 0x13c\n-\tadd.w\tr0, r9, r6\n-\tstr.w\tr0, [r7, #300]\t@ 0x12c\n-\tvnmul.f64\td22, d19, d26\n-\tvmul.f64\td19, d9, d19\n-\tvfma.f64\td22, d9, d23\n-\tvfma.f64\td19, d26, d23\n-\tadd.w\tr0, r9, r5\n-\tadd\tr5, ip\n-\tstr.w\tr5, [r7, #292]\t@ 0x124\n-\tvcvt.f32.f64\ts7, d29\n-\tldr\tr5, [r7, #120]\t@ 0x78\n-\tadd\tr6, ip\n-\tstr.w\tr0, [r7, #296]\t@ 0x128\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tadd\tr5, lr\n-\tadd\tlr, r0\n-\tadd.w\tr0, ip, r5\n-\tvcvt.f32.f64\ts13, d22\n-\tvnmul.f64\td22, d17, d15\n-\tvfma.f64\td22, d0, d21\n-\tstr.w\tr0, [r7, #288]\t@ 0x120\n-\tldr.w\tr0, [r7, #340]\t@ 0x154\n-\tvmul.f64\td17, d0, d17\n-\tvfma.f64\td17, d15, d21\n-\tadd\tr5, r9\n-\tvstr\ts13, [r0, #-4]\n-\tvcvt.f32.f64\ts13, d19\n-\tvsub.f64\td19, d25, d18\n-\tldr.w\tr0, [r7, #448]\t@ 0x1c0\n-\tvsub.f64\td25, d18, d25\n-\tvcvt.f32.f64\ts9, d22\n-\tvstr\ts13, [r2, #-4]\n-\tldr.w\tr2, [r7, #352]\t@ 0x160\n-\tvmul.f64\td19, d19, d5\n-\tvmul.f64\td25, d25, d13\n-\tvfma.f64\td19, d13, d16\n-\tvfma.f64\td25, d5, d16\n-\tvstr\ts9, [r2, #-4]\n-\tvstr\ts6, [r1, #-4]\n-\tvcvt.f32.f64\ts6, d17\n-\tldr.w\tr2, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n-\tvcvt.f32.f64\ts13, d19\n+\tvmul.f64\td0, d0, d13\n+\tvmul.f64\td3, d3, d13\n+\tadd\tr6, r8\n+\tstr.w\tip, [r7, #280]\t@ 0x118\n+\tadd.w\tip, r8, r5\n+\tadd.w\tr5, r9, r6\n+\tadd\tr6, lr\n+\tstr.w\tr6, [r7, #508]\t@ 0x1fc\n+\tvstr\td3, [r7, #584]\t@ 0x248\n+\tvmul.f64\td3, d4, d8\n+\tldr\tr6, [r7, #120]\t@ 0x78\n+\tstr.w\tr5, [r7, #516]\t@ 0x204\n+\tadd.w\tr5, lr, ip\n+\tadd\tr6, r8\n+\tstr.w\tr5, [r7, #272]\t@ 0x110\n+\tvstr\td3, [r7, #368]\t@ 0x170\n+\tadd.w\tr5, lr, r6\n+\tvldr\td3, [r7, #768]\t@ 0x300\n+\tadd\tr6, r9\n+\tstr.w\tr6, [r7, #276]\t@ 0x114\n+\tadd\tip, r9\n+\tldr\tr6, [r7, #116]\t@ 0x74\n+\tvadd.f64\td4, d4, d3\n+\tstr.w\tr5, [r7, #504]\t@ 0x1f8\n+\tadd\tr6, r8\n+\tadd\tr8, r0\n+\tadd.w\tr5, lr, r6\n+\tstr.w\tr5, [r7, #268]\t@ 0x10c\n+\tadd\tr6, r9\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r4, #-4]\n+\tvldr\ts9, [r1, #-4]\n+\tldr.w\tr5, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr4, [r7, #700]\t@ 0x2bc\n+\tvcvt.f64.f32\td3, s9\n+\tvmul.f64\td4, d15, d1\n+\tvmul.f64\td1, d14, d1\n+\tvstr\td3, [r7, #592]\t@ 0x250\n+\tvmov.f64\td3, d4\n+\tvldr\td4, [r7, #616]\t@ 0x268\n+\tvmla.f64\td3, d14, d4\n+\tvmul.f64\td4, d15, d4\n+\tvstr\td4, [r7, #600]\t@ 0x258\n+\tvldr\td4, [r7, #392]\t@ 0x188\n+\tvstr\td3, [r7, #616]\t@ 0x268\n+\tvmov.f64\td3, d4\n+\tvadd.f64\td4, d2, d4\n+\tvmls.f64\td3, d2, d8\n+\tvldr\td8, [r7, #384]\t@ 0x180\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r4, #-4]\n+\tadd\tr4, r0\n+\tvldr\ts9, [r5, #-4]\n+\tvstr\td3, [r7, #408]\t@ 0x198\n+\tvldr\td3, [r7, #368]\t@ 0x170\n+\tvcvt.f64.f32\td2, s9\n+\tstr.w\tr4, [r7, #700]\t@ 0x2bc\n+\tvstr\td2, [r7, #392]\t@ 0x188\n+\tvldr\td2, [r7, #768]\t@ 0x300\n+\tvsub.f64\td4, d2, d3\n+\tvldr\td2, [r7, #376]\t@ 0x178\n+\tvstr\td4, [r7, #368]\t@ 0x170\n+\tvmul.f64\td4, d15, d2\n+\tvmla.f64\td4, d14, d8\n+\tvmul.f64\td2, d14, d2\n+\tvstr\td4, [r7, #376]\t@ 0x178\n+\tvmul.f64\td4, d15, d8\n+\tvstr\td4, [r7, #384]\t@ 0x180\n+\tvldr\td4, [r7, #600]\t@ 0x258\n+\tvsub.f64\td8, d4, d1\n+\tvsub.f64\td1, d1, d4\n+\tvadd.f64\td4, d8, d3\n+\tvldr\td3, [r7, #768]\t@ 0x300\n+\tvstr\td8, [r7, #432]\t@ 0x1b0\n+\tvldr\td8, [r7, #368]\t@ 0x170\n+\tvsub.f64\td4, d4, d3\n+\tvldr\td3, [r7, #408]\t@ 0x198\n+\tvadd.f64\td4, d4, d0\n+\tvstr\td4, [r7, #256]\t@ 0x100\n+\tvadd.f64\td4, d0, d8\n+\tvsub.f64\td0, d8, d0\n+\tvldr\td8, [r7, #432]\t@ 0x1b0\n+\tvstr\td4, [r7, #600]\t@ 0x258\n+\tvadd.f64\td1, d1, d0\n+\tvldr\td4, [r7, #584]\t@ 0x248\n+\tvadd.f64\td8, d8, d0\n+\tvstr\td1, [r7, #248]\t@ 0xf8\n+\tvadd.f64\td1, d4, d3\n+\tvsub.f64\td4, d3, d4\n+\tvldr\td3, [r7, #616]\t@ 0x268\n+\tvstr\td4, [r7, #768]\t@ 0x300\n+\tvldr\td0, [r7, #600]\t@ 0x258\n+\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tvadd.f64\td3, d3, d0\n+\tvldr\td0, [r7, #384]\t@ 0x180\n+\tvsub.f64\td4, d2, d0\n+\tvsub.f64\td2, d0, d2\n+\tvmov.f64\td0, d4\n+\tvldr\td4, [r7, #768]\t@ 0x300\n+\tvadd.f64\td0, d0, d4\n+\tvadd.f64\td4, d2, d4\n+\tvldr\td2, [r7, #376]\t@ 0x178\n+\tvstr\td4, [r7, #368]\t@ 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d0\n+\tvmul.f64\td0, d9, d2\n+\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tvnmls.f64\td3, d12, d4\n+\tvldr\td4, [r7, #776]\t@ 0x308\n+\tvcvt.f32.f64\ts3, d1\n+\tvnmls.f64\td0, d4, d8\n+\tvmul.f64\td2, d4, d2\n+\tvmla.f64\td2, d9, d8\n+\tvldr\td8, [r7, #400]\t@ 0x190\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts0, d0\n+\tvcvt.f32.f64\ts9, d2\n+\tvstr\ts0, [r4, #-4]\n+\tvstr\ts6, [r2, #-4]\n+\tvldr\td3, [r7, #360]\t@ 0x168\n+\tvstr\ts9, [r5, #-4]\n+\tvmul.f64\td4, d6, d8\n+\tvstr\ts3, [r3, #-4]\n+\tvmla.f64\td4, d3, d11\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n+\tldr.w\tr4, [r7, #536]\t@ 0x218\n+\tldr.w\tr3, [r7, #296]\t@ 0x128\n+\tldr.w\tr5, [r7, #304]\t@ 0x130\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r1, #-4]\n+\tvmul.f64\td4, d11, d8\n+\tvldr\td8, [r7, #256]\t@ 0x100\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tvmla.f64\td4, d8, d6\n+\tvcvt.f32.f64\ts8, d4\n+\tvldr\ts9, [r3, #-4]\n+\tvcvt.f64.f32\td1, s9\n+\tvstr\ts8, [r2, #-4]\n+\tvldr\ts1, [r4, #-4]\n+\tvldr\ts5, [r1, #-4]\n+\tldr.w\tr1, [r7, #528]\t@ 0x210\n+\tvcvt.f64.f32\td0, s1\n+\tldr.w\tr2, [r7, #520]\t@ 0x208\n+\tvcvt.f64.f32\td8, s5\n+\tvldr\ts8, [r5, #-4]\n+\tvstr\td0, [r7, #576]\t@ 0x240\n+\tvcvt.f64.f32\td4, s8\n+\tvldr\ts0, [r1, #-4]\n+\tvstr\td8, [r7, #632]\t@ 0x278\n+\tvldr\ts17, [fp, #-4]\n+\tvcvt.f64.f32\td0, s0\n+\tvldr\ts6, [r2, #-4]\n+\tldr.w\tr2, [r7, #312]\t@ 0x138\n+\tvcvt.f64.f32\td3, s6\n+\tvstr\td0, [r7, #400]\t@ 0x190\n+\tvcvt.f64.f32\td0, s17\n+\tvldr\ts4, [r2, #-4]\n+\tvstr\td0, [r7, #336]\t@ 0x150\n+\tvcvt.f64.f32\td2, s4\n+\tvldr\td0, [r7, #328]\t@ 0x148\n+\tvadd.f64\td8, d0, d3\n+\tvsub.f64\td3, d0, d3\n+\tvadd.f64\td0, d1, d4\n+\tvsub.f64\td1, d1, d4\n+\tvstr\td8, [r7, #376]\t@ 0x178\n+\tvldr\td8, [r7, #632]\t@ 0x278\n+\tvstr\td1, [r7, #344]\t@ 0x158\n+\tvldr\td1, [r7, #352]\t@ 0x160\n+\tvstr\td3, [r7, #360]\t@ 0x168\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tvadd.f64\td3, d1, d8\n+\tvsub.f64\td1, d1, d8\n+\tvldr\td8, [r7, #576]\t@ 0x240\n+\tldr.w\tr4, [r7, #684]\t@ 0x2ac\n+\tvstr\td1, [r7, #632]\t@ 0x278\n+\tvsub.f64\td4, d2, d8\n+\tvadd.f64\td1, d2, d8\n+\tvldr\td2, [r7, #608]\t@ 0x260\n+\tvldr\td8, [r7, #768]\t@ 0x300\n+\tvsub.f64\td8, d2, d8\n+\tvstr\td8, [r7, #296]\t@ 0x128\n+\tvldr\td8, [r7, #768]\t@ 0x300\n+\tvsub.f64\td2, d8, d2\n+\tvstr\td2, [r7, #312]\t@ 0x138\n+\tvldr\td2, [r7, #376]\t@ 0x178\n+\tvadd.f64\td8, d2, d0\n+\tvsub.f64\td0, d2, d0\n+\tvadd.f64\td2, d3, d1\n+\tvsub.f64\td3, d3, d1\n+\tvldr\td1, [r7, #632]\t@ 0x278\n+\tvmul.f64\td0, d0, d13\n+\tvmul.f64\td3, d3, d13\n+\tvstr\td3, [r7, #768]\t@ 0x300\n+\tvmul.f64\td3, d15, d1\n+\tvstr\td3, [r7, #576]\t@ 0x240\n+\tvmul.f64\td3, d14, d4\n+\tvmul.f64\td4, d15, d4\n+\tvmov.f64\td1, d4\n+\tvldr\td4, [r7, #632]\t@ 0x278\n+\tvmla.f64\td1, d14, d4\n+\tvmov.f64\td4, #80\t@ 0x3e800000 0.250\n+\tvmul.f64\td4, d8, d4\n+\tvstr\td4, [r7, #352]\t@ 0x160\n+\tvstr\td1, [r7, #376]\t@ 0x178\n+\tvldr\td1, [r7, #592]\t@ 0x250\n+\tvadd.f64\td4, d1, d8\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r1, #-4]\n+\tadd\tr1, r0\n+\tvldr\ts9, [sl, #-4]\n+\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tadds\tr1, r4, r0\n+\tstr.w\tr1, [r7, #684]\t@ 0x2ac\n+\tvcvt.f64.f32\td8, s9\n+\tvmov.f64\td4, #80\t@ 0x3e800000 0.250\n+\tvstr\td8, [r7, #328]\t@ 0x148\n+\tvldr\td8, [r7, #392]\t@ 0x188\n+\tvmov.f64\td1, d8\n+\tvmls.f64\td1, d2, d4\n+\tvadd.f64\td4, d8, d2\n+\tvcvt.f32.f64\ts8, d4\n \tvstr\ts8, [r4, #-4]\n-\tldr.w\tr4, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tvadd.f64\td24, d17, d24\n-\tvadd.f64\td17, d17, d16\n-\tvmov.f64\td16, d18\n-\tvfma.f64\td16, d25, d31\n-\tvsub.f64\td16, d16, d28\n-\tvfma.f64\td16, d10, d21\n-\tvmul.f64\td16, d14, d16\n-\tvfma.f64\td16, d2, d24\n-\tvcvt.f32.f64\ts7, d16\n-\tvmov.f64\td16, d28\n-\tvfms.f64\td16, d25, d31\n-\tvadd.f64\td25, d25, d28\n-\tvcvt.f32.f64\ts15, d25\n-\tvsub.f64\td25, d22, d19\n-\tvadd.f64\td22, d22, d19\n-\tvmov.f64\td19, d16\n-\tvfma.f64\td16, d21, d11\n-\tvfma.f64\td19, d10, d21\n-\tvstr\ts15, [r4, #-4]\n-\tadd\tr4, r3\n-\tldr.w\tr3, [r7, #356]\t@ 0x164\n-\tstr.w\tr4, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr4, [r7, #404]\t@ 0x194\n-\tvadd.f64\td21, d18, d16\n-\tvadd.f64\td16, d16, d27\n-\tvldr\td18, [r7, #456]\t@ 0x1c8\n-\tvmul.f64\td16, d16, d2\n-\tvadd.f64\td28, d18, d26\n-\tvfma.f64\td16, d14, d24\n-\tvsub.f64\td24, d20, d19\n-\tvsub.f64\td18, d18, d26\n-\tvmul.f64\td24, d24, d13\n-\tvfma.f64\td24, d5, d22\n-\tvmul.f64\td27, d8, d18\n-\tvmul.f64\td18, d1, d18\n-\tvcvt.f32.f64\ts9, d16\n-\tvadd.f64\td16, d20, d19\n-\tvsub.f64\td19, d19, d20\n-\tvnmul.f64\td20, d21, d15\n-\tvmul.f64\td21, d0, d21\n-\tvfma.f64\td20, d0, d17\n-\tvfma.f64\td21, d15, d17\n-\tvnmul.f64\td17, d16, d30\n-\tvmul.f64\td16, d9, d16\n-\tvfma.f64\td17, d9, d25\n-\tvfma.f64\td16, d30, d25\n-\tvmul.f64\td19, d19, d5\n-\tvfma.f64\td19, d13, d22\n-\tvadd.f64\td22, d29, d23\n-\tvcvt.f32.f64\ts15, d20\n-\tvcvt.f32.f64\ts8, d21\n-\tvcvt.f32.f64\ts14, d17\n-\tvstr\ts14, [r3, #-4]\n-\tvcvt.f32.f64\ts14, d16\n-\tldr.w\tr3, [r7, #332]\t@ 0x14c\n-\tvsub.f64\td16, d29, d23\n-\tvstr\ts14, [r3, #-4]\n-\tvcvt.f32.f64\ts14, d24\n-\tvstr\ts14, [r1, #-4]\n-\tldr.w\tr1, [r7, #464]\t@ 0x1d0\n-\tvstr\ts15, [r1, #-4]\n-\tvcvt.f32.f64\ts15, d19\n-\tldr.w\tr1, [r7, #416]\t@ 0x1a0\n-\tvstr\ts7, [r2, #-4]\n-\tvstr\ts15, [r4, #-4]\n+\tldr.w\tr4, [r7, #308]\t@ 0x134\n+\tvstr\td1, [r7, #632]\t@ 0x278\n+\tvldr\ts9, [r4, #-4]\n+\tvcvt.f64.f32\td2, s9\n+\tvstr\td2, [r7, #608]\t@ 0x260\n+\tvldr\td4, [r7, #576]\t@ 0x240\n+\tvldr\td2, [r7, #592]\t@ 0x250\n+\tvldr\td1, [r7, #344]\t@ 0x158\n+\tvsub.f64\td8, d4, d3\n+\tvsub.f64\td4, d3, d4\n+\tldr.w\tr1, [r7, #560]\t@ 0x230\n+\tvstr\td4, [r7, #392]\t@ 0x188\n+\tvldr\td4, [r7, #352]\t@ 0x160\n+\tvsub.f64\td3, d2, d4\n+\tvadd.f64\td4, d8, d4\n+\tvsub.f64\td4, d4, d2\n+\tvadd.f64\td4, d4, d0\n+\tvstr\td4, [r7, #352]\t@ 0x160\n+\tvmul.f64\td4, d15, d1\n+\tvmov.f64\td2, d4\n+\tvldr\td4, [r7, #360]\t@ 0x168\n+\tvmla.f64\td2, d14, d4\n+\tvstr\td2, [r7, #592]\t@ 0x250\n+\tvmul.f64\td2, d15, d4\n+\tvmul.f64\td4, d14, d1\n+\tvadd.f64\td1, d0, d3\n+\tvsub.f64\td3, d3, d0\n+\tvldr\td0, [r7, #392]\t@ 0x188\n+\tvadd.f64\td8, d8, d3\n+\tvadd.f64\td0, d0, d3\n+\tvldr\td3, [r7, #768]\t@ 0x300\n+\tvstr\td8, [r7, #576]\t@ 0x240\n+\tvldr\td8, [r7, #632]\t@ 0x278\n+\tvstr\td0, [r7, #360]\t@ 0x168\n+\tvadd.f64\td0, d3, d8\n+\tvsub.f64\td3, d8, d3\n+\tvsub.f64\td8, d2, d4\n+\tvsub.f64\td2, d4, d2\n+\tvadd.f64\td4, d8, d3\n+\tvldr\td8, [r7, #376]\t@ 0x178\n+\tvadd.f64\td2, d2, d3\n+\tvldr\td3, [r7, #592]\t@ 0x250\n+\tvstr\td4, [r7, #392]\t@ 0x188\n+\tvadd.f64\td4, d8, d1\n+\tvstr\td4, [r7, #768]\t@ 0x300\n+\tvadd.f64\td4, d0, d3\n+\tvsub.f64\td0, d0, d3\n+\tvsub.f64\td3, d8, d1\n+\tvsub.f64\td1, d1, d8\n+\tvldr\td8, [r7, #576]\t@ 0x240\n+\tvstr\td4, [r7, #632]\t@ 0x278\n+\tvmul.f64\td4, d7, d8\n+\tvstr\td3, [r7, #592]\t@ 0x250\n+\tvmul.f64\td3, d12, d8\n+\tvldr\td8, [r7, #768]\t@ 0x300\n+\tvmla.f64\td3, d7, d2\n+\tvnmls.f64\td4, d12, d2\n+\tvcvt.f32.f64\ts5, d3\n+\tvmul.f64\td3, d9, d8\n+\tvcvt.f32.f64\ts4, d4\n+\tvldr\td4, [r7, #776]\t@ 0x308\n+\tvmul.f64\td4, d4, d8\n+\tvldr\td8, [r7, #776]\t@ 0x308\n+\tvmla.f64\td4, d9, d0\n+\tvnmls.f64\td3, d8, d0\n+\tvldr\td8, [r7, #592]\t@ 0x250\n+\tvcvt.f32.f64\ts9, d4\n+\tvstr\ts9, [r1, #-4]\n+\tvcvt.f32.f64\ts9, d3\n+\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tvstr\ts9, [r1, #-4]\n+\tvldr\td4, [r7, #632]\t@ 0x278\n+\tvmul.f64\td3, d10, d4\n+\tvmul.f64\td4, d5, d4\n+\tvmla.f64\td3, d8, d5\n+\tvmla.f64\td4, d1, d10\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts6, [r4, #-4]\n+\tvstr\ts8, [sl, #-4]\n+\tvstr\ts4, [r2, #-4]\n+\tvstr\ts5, [r3, #-4]\n+\tvldr\td2, [r7, #392]\t@ 0x188\n+\tvldr\td3, [r7, #352]\t@ 0x160\n+\tldr.w\tr1, [r7, #528]\t@ 0x210\n+\tvmul.f64\td4, d11, d2\n+\tldr.w\tr4, [r7, #516]\t@ 0x204\n+\tvmla.f64\td4, d3, d6\n+\tvldr\td3, [r7, #360]\t@ 0x168\n+\tvldr\td8, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #292]\t@ 0x124\n+\tvcvt.f32.f64\ts8, d4\n \tvstr\ts8, [r1, #-4]\n-\tldr.w\tr4, [r7, #296]\t@ 0x128\n-\tldr.w\tr1, [r7, #300]\t@ 0x12c\n-\tvldr\ts15, [r7, #276]\t@ 0x114\n-\tvstr\ts9, [r0, #-4]\n-\tvldr\ts14, [r4, #-4]\n+\tvmul.f64\td4, d6, d2\n+\tvmla.f64\td4, d3, d11\n+\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tvldr\ts5, [r7, #264]\t@ 0x108\n+\tvldr\ts7, [r2, #-4]\n+\tvldr\ts6, [r1, #-4]\n+\tldr.w\tr1, [r7, #288]\t@ 0x120\n+\tvcvt.f32.f64\ts8, d4\n+\tvldr\ts9, [r4, #-4]\n+\tvcvt.f64.f32\td1, s9\n+\tvstr\ts8, [fp, #-4]\n \tvldr\ts8, [r1, #-4]\n-\tvstr\ts15, [r1, #-4]\n-\tldr.w\tr1, [r7, #292]\t@ 0x124\n-\tvcvt.f64.f32\td17, s14\n-\tvcvt.f64.f32\td19, s8\n-\tvldr\ts9, [r6, #-4]\n-\tvldr\ts15, [r1, #-4]\n-\tvcvt.f64.f32\td21, s9\n-\tvstr\ts13, [r6, #-4]\n-\tvsub.f64\td25, d19, d17\n-\tvldr\ts14, [r5, #-4]\n-\tvadd.f64\td19, d19, d17\n-\tvcvt.f64.f32\td20, s15\n-\tvldr\ts13, [r7, #272]\t@ 0x110\n-\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n-\tvcvt.f64.f32\td17, s14\n-\tvfma.f64\td18, d8, d25\n-\tvadd.f64\td23, d19, d28\n-\tvstr\ts13, [r5, #-4]\n-\tvadd.f64\td24, d21, d20\n-\tldr.w\tr5, [r7, #288]\t@ 0x120\n-\tvsub.f64\td21, d21, d20\n-\tvmov.f64\td20, d27\n-\tvfma.f64\td27, d25, d12\n-\tvfnms.f64\td20, d1, d25\n-\tvmov.f64\td25, d17\n-\tvsub.f64\td19, d19, d28\n-\tvfms.f64\td25, d23, d31\n-\tvldr\ts15, [r5, #-4]\n-\tvadd.f64\td23, d23, d17\n-\tldr.w\tr0, [r7, #372]\t@ 0x174\n-\tldr.w\tr6, [r7, #488]\t@ 0x1e8\n-\tvcvt.f64.f32\td26, s15\n-\tldr.w\tr3, [r7, #556]\t@ 0x22c\n-\tvstr\ts12, [r5, #-4]\n-\tadds\tr5, r6, r3\n-\tstr.w\tr5, [r7, #488]\t@ 0x1e8\n-\tvmov.f64\td29, d27\n-\tvadd.f64\td27, d24, d22\n-\tvmov.f64\td17, d26\n-\tvsub.f64\td24, d24, d22\n-\tvmov.f64\td28, d25\n-\tvfma.f64\td25, d11, d19\n-\tvfma.f64\td28, d10, d19\n-\tvmov.f64\td19, d20\n-\tvfms.f64\td17, d27, d31\n-\tvfma.f64\td19, d27, d31\n-\tvadd.f64\td7, d27, d26\n-\tvmul.f64\td22, d8, d16\n-\tvmul.f64\td16, d1, d16\n-\tadds\tr5, r2, r3\n-\tvfma.f64\td16, d8, d21\n-\tldr.w\tr3, [r7, #336]\t@ 0x150\n-\tstr.w\tr5, [r7, #476]\t@ 0x1dc\n-\tvcvt.f32.f64\ts14, d7\n-\tvcvt.f32.f64\ts15, d23\n-\tvsub.f64\td19, d19, d26\n-\tvmov.f64\td26, d17\n-\tvfma.f64\td26, d10, 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0x258\n+\tvmul.f64\td0, d14, d2\n+\tvmul.f64\td2, d15, d2\n+\tvmla.f64\td2, d14, d4\n+\tvstr\td0, [r7, #616]\t@ 0x268\n+\tvldr\td0, [r7, #592]\t@ 0x250\n+\tvstr\td2, [r7, #608]\t@ 0x260\n+\tvmul.f64\td2, d15, d4\n+\tvadd.f64\td4, d3, d0\n+\tvsub.f64\td3, d3, d0\n+\tvldr\td0, [r7, #576]\t@ 0x240\n+\tvmul.f64\td3, d3, d13\n+\tvstr\td3, [r7, #640]\t@ 0x280\n+\tvadd.f64\td3, d1, d0\n+\tvsub.f64\td1, d1, d0\n+\tvmul.f64\td0, d1, d13\n+\tvmov.f64\td1, #80\t@ 0x3e800000 0.250\n+\tvmul.f64\td1, d4, d1\n+\tvadd.f64\td4, d4, d8\n+\tvstr\td0, [r7, #632]\t@ 0x278\n+\tvldr\td0, [r7, #768]\t@ 0x300\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r3, #-4]\n+\tvmov.f64\td4, #80\t@ 0x3e800000 0.250\n+\tvmls.f64\td0, d3, d4\n+\tvldr\td4, [r7, #768]\t@ 0x300\n+\tvadd.f64\td3, d3, d4\n+\tvldr\td4, [r7, #616]\t@ 0x268\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\td0, [r7, #624]\t@ 0x270\n+\tvstr\ts6, [r2, #-4]\n+\tvsub.f64\td3, d2, d4\n+\tvsub.f64\td4, d4, d2\n+\tadd\tr2, r0\n+\tstr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tvmov.f64\td0, d3\n+\tvsub.f64\td3, d8, d1\n+\tvstr\td4, [r7, #584]\t@ 0x248\n+\tvadd.f64\td4, d0, d1\n+\tvldr\td1, [r7, #600]\t@ 0x258\n+\tvmul.f64\td2, d15, d1\n+\tvsub.f64\td4, d4, d8\n+\tvldr\td8, [r7, #640]\t@ 0x280\n+\tvadd.f64\td4, d4, d8\n+\tvldr\td8, [r7, #528]\t@ 0x210\n+\tvstr\td4, [r7, #592]\t@ 0x250\n+\tvmul.f64\td4, d15, d8\n+\tvmla.f64\td4, d14, d1\n+\tvstr\td4, [r7, #768]\t@ 0x300\n+\tvmul.f64\td4, d14, d8\n+\tvldr\td8, [r7, #640]\t@ 0x280\n+\tvadd.f64\td1, d8, d3\n+\tvsub.f64\td3, d3, d8\n+\tvadd.f64\td8, d0, d3\n+\tvldr\td0, [r7, #584]\t@ 0x248\n+\tvadd.f64\td0, d0, d3\n+\tvldr\td3, [r7, #624]\t@ 0x270\n+\tvstr\td8, [r7, #616]\t@ 0x268\n+\tvldr\td8, [r7, #632]\t@ 0x278\n+\tvstr\td0, [r7, #600]\t@ 0x258\n+\tvadd.f64\td0, d8, d3\n+\tvsub.f64\td3, d3, d8\n+\tvsub.f64\td8, d2, d4\n+\tvsub.f64\td2, d4, d2\n+\tvadd.f64\td4, d8, d3\n+\tvadd.f64\td2, d2, d3\n+\tvstr\td4, [r7, #632]\t@ 0x278\n+\tvldr\td4, [r7, #608]\t@ 0x260\n+\tldr.w\tr5, [r7, #668]\t@ 0x29c\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tvadd.f64\td3, d4, d1\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tldr.w\tr2, [r7, #520]\t@ 0x208\n+\tldr.w\tr6, [r7, #672]\t@ 0x2a0\n+\tvstr\td3, [r7, #640]\t@ 0x280\n+\tvldr\td3, [r7, #768]\t@ 0x300\n+\tvadd.f64\td8, d0, d3\n+\tvsub.f64\td0, d0, d3\n+\tvldr\td3, [r7, #616]\t@ 0x268\n+\tvstr\td8, [r7, #768]\t@ 0x300\n+\tvsub.f64\td8, d4, d1\n+\tvsub.f64\td1, d1, d4\n+\tvmul.f64\td4, d7, d3\n+\tvmul.f64\td3, d12, d3\n+\tvmla.f64\td3, d7, d2\n+\tvnmls.f64\td4, d12, d2\n+\tvstr\td1, [r7, #624]\t@ 0x270\n+\tvldr\td2, [r7, #776]\t@ 0x308\n+\tvcvt.f32.f64\ts3, d3\n+\tvcvt.f32.f64\ts2, d4\n+\tvldr\td4, [r7, #640]\t@ 0x280\n+\tvmul.f64\td3, d9, d4\n+\tvmul.f64\td4, d2, d4\n+\tvmla.f64\td4, d9, d0\n+\tvnmls.f64\td3, d2, d0\n+\tvldr\td0, [r7, #600]\t@ 0x258\n+\tvcvt.f32.f64\ts4, d4\n+\tvldr\td4, [r7, #768]\t@ 0x300\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts4, [r3, #-4]\n+\tvldr\td2, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tvstr\ts6, [r5, #-4]\n+\tvmul.f64\td3, d10, d4\n+\tvmla.f64\td3, d8, d5\n+\tvmul.f64\td4, d5, d4\n+\tvcvt.f32.f64\ts6, d3\n+\tvstr\ts6, [r4, #-4]\n+\tvldr\td3, [r7, #624]\t@ 0x270\n+\tldr.w\tr4, [r7, #504]\t@ 0x1f8\n+\tvstr\ts2, [r1, #-4]\n+\tvmla.f64\td4, d3, d10\n+\tvmul.f64\td3, d11, d2\n+\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts8, [r4, #-4]\n+\tvldr\td4, [r7, #592]\t@ 0x250\n+\tvstr\ts3, [r2, #-4]\n+\tvmla.f64\td3, d4, d6\n+\tvmul.f64\td4, d6, d2\n+\tvmla.f64\td4, d0, d11\n+\tvcvt.f32.f64\ts6, d3\n+\tvcvt.f32.f64\ts8, d4\n+\tvstr\ts6, [r1, #-4]\n+\tvstr\ts8, [r3, #-4]\n+\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n \tcmp\tr6, r3\n-\tvstr\ts15, [r4, #-4]\n-\tvcvt.f32.f64\ts15, d26\n-\tldr.w\tr4, [r7, #408]\t@ 0x198\n-\tvstr\ts15, [r1, #-4]\n-\tvcvt.f32.f64\ts15, d18\n-\tldr.w\tr1, [r7, #420]\t@ 0x1a4\n-\tvstr\ts15, [r0, #-4]\n-\tvcvt.f32.f64\ts15, d20\n-\tvstr\ts15, [r1, #-4]\n-\tvcvt.f32.f64\ts15, d19\n-\tvstr\ts15, [r2, #-4]\n-\tvcvt.f32.f64\ts15, d17\n-\tvstr\ts15, [r4, #-4]\n-\tbne.w\tcb7e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4492>\n+\tbne.w\td1e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4706>\n \tldrd\tsl, fp, [r7]\n-\tldr.w\tr0, [r7, #556]\t@ 0x22c\n-\tb.w\tc904 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4218>\n-\tldr\tr0, [r7, #72]\t@ 0x48\n-\tudiv\tr0, r9, r0\n-\tmov\tr6, r0\n-\tldr.w\tr0, [r7, #440]\t@ 0x1b8\n-\tcmp\tr0, r2\n-\tble.w\tbc00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3514>\n-\tb.w\tc956 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x426a>\n-\tmov\tr4, r8\n-\tmov\tr6, lr\n-\tmov\tr8, r1\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tadd.w\tr8, r8, #1\n-\tcmp\tr3, r8\n-\tbge.w\tbb02 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3416>\n-\tldr\tr1, [r7, #44]\t@ 0x2c\n-\tmov\tr3, r6\n-\tb.w\taa64 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2378>\n-\tnegs\tr1, r0\n-\tnegs\tr3, r3\n-\tcmp\tr0, #0\n-\tudiv\tr3, r1, r3\n-\tstr.w\tr3, [r7, #208]\t@ 0xd0\n-\tble.w\tbb48 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x345c>\n-\tb.n\td734 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5048>\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tb.w\tcf2e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x4452>\n+\tldr\tr1, [r7, #56]\t@ 0x38\n+\tldr\tr0, [r7, #112]\t@ 0x70\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n+\tmov\tr1, r0\n+\tcmp\tr3, sl\n+\tble.w\tc114 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3638>\n+\tb.w\tcf7a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x449e>\n+\tmov\tsl, r9\n+\tldr\tr3, [r7, #72]\t@ 0x48\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tadds\tr3, #1\n+\tstr\tr3, [r7, #72]\t@ 0x48\n+\tcmp\tr2, r3\n+\tbge.w\tc00a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x352e>\n+\tmov\tr5, sl\n+\tmov\tr6, fp\n+\tldrd\tr4, sl, [r7, #28]\n+\tb.w\tb694 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bb8>\n+\tnegs\tr1, r3\n+\tnegs\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tstr.w\tr0, [r7, #180]\t@ 0xb4\n+\tble.w\tc05c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x3580>\n+\tb.n\te1ce <__gridxc_gpfa_core_sp_MOD_gpfa_+0x56f2>\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tcmp\tr3, #0\n-\tblt.n\td7f6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x510a>\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n+\tblt.n\te294 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x57b8>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n \tmov\tr1, sp\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\td792 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x50a6>\n+\tbeq.n\te232 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5756>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\td784 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5098>\n+\tbne.n\te224 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5748>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, d7a2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x50b6>\n+\tcbz\tr3, e242 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5766>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tadd\tr0, sp, #24\n-\tldr.w\tr1, [r7, #528]\t@ 0x210\n-\tmov\tr6, r0\n-\tmovs\tr2, #0\n-\tlsls\tr3, r3, #2\n-\tldr\tr4, [r1, #0]\n-\tadds\tr2, #1\n-\tstr.w\tr4, [r6], #4\n-\tadd\tr1, r3\n-\tldr.w\tr4, [r7, #484]\t@ 0x1e4\n-\tcmp\tr4, r2\n-\tbge.n\td7b2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x50c6>\n-\tstr.w\tr0, [r7, #556]\t@ 0x22c\n-\tb.n\td800 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5114>\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tmov\tr5, r0\n+\tlsls\tr2, r3, #2\n+\tmovs\tr3, #0\n+\tldr\tr6, [r1, #0]\n+\tadds\tr3, #1\n+\tstr.w\tr6, [r5], #4\n+\tadd\tr1, r2\n+\tldr.w\tr6, [r7, #684]\t@ 0x2ac\n+\tcmp\tr6, r3\n+\tbge.n\te252 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5776>\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n+\tb.n\te29e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x57c2>\n+\tldr.w\tr1, [r7, #652]\t@ 0x28c\n \tcmp\tr1, #0\n-\tble.w\taa98 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ac>\n+\tble.w\tb6c6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bea>\n \tmov\tr2, r3\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tldr.w\tr3, [r7, #224]\t@ 0xe0\n \tlsls\tr0, r2, #2\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n \tadd.w\tr1, r3, r1, lsl #2\n \tldr.w\tr4, [r3], #4\n \tstr\tr4, [r2, #0]\n \tadd\tr2, r0\n \tcmp\tr3, r1\n-\tbne.n\td7e4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x50f8>\n-\tmov\tsp, r6\n-\tb.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tadd.w\tr3, r7, #576\t@ 0x240\n-\tstr.w\tr3, [r7, #556]\t@ 0x22c\n+\tbne.n\te284 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x57a8>\n+\tb.w\tb6c6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bea>\n+\tadd.w\tr3, r7, #800\t@ 0x320\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n \tmov\tr0, r3\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\tdc28 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x553c>\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tvstr\td0, [r7, #560]\t@ 0x230\n+\tbne.w\te6be <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5be2>\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tldr\tr3, [r3, #0]\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n \tldr\tr2, [r2, #0]\n-\tstrd\tr5, r2, [sp, #8]\n-\tldr.w\tr6, [sl]\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr1, [r7, #512]\t@ 0x200\n-\tstr\tr6, [sp, #4]\n-\tldr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr\tr6, [r4, #0]\n-\tstr\tr6, [sp, #0]\n-\tbl\t48d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n-\tvldr\td0, [r7, #560]\t@ 0x230\n+\tstrd\tr4, r2, [sp, #8]\n+\tldr.w\tr5, [fp]\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tstr\tr5, [sp, #4]\n+\tldr.w\tr5, [r7, #664]\t@ 0x298\n+\tldr\tr5, [r5, #0]\n+\tstr\tr5, [sp, #0]\n+\tbl\t4bb8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n \tcmp\tr3, #0\n-\tble.n\td878 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x518c>\n-\tldr.w\tr2, [r7, #556]\t@ 0x22c\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tldr.w\tr0, [r7, #436]\t@ 0x1b4\n-\tldr.w\tr1, [r7, #528]\t@ 0x210\n-\tlsls\tr3, r3, #2\n-\tadd.w\tr0, r2, r0, lsl #2\n-\tldr.w\tr4, [r2], #4\n-\tstr\tr4, [r1, #0]\n-\tadd\tr1, r3\n-\tcmp\tr2, r0\n-\tbne.n\td862 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5176>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tble.n\te30e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5832>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tldr.w\tr1, [r7, #740]\t@ 0x2e4\n+\tlsls\tr2, r2, #2\n+\tadd.w\tr0, r3, r0, lsl #2\n+\tldr.w\tr5, [r3], #4\n+\tstr\tr5, [r1, #0]\n+\tadd\tr1, r2\n+\tcmp\tr3, r0\n+\tbne.n\te2f8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x581c>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.w\td9d8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x52ec>\n-\tcmp\tr5, #31\n+\tbne.w\te470 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5994>\n+\tcmp\tr4, #31\n \tmov\tsp, r8\n-\tbgt.w\tda14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5328>\n+\tbgt.w\te4ac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59d0>\n \tmovs\tr3, #2\n-\tlsl.w\tr5, r3, r5\n-\tadds\tr3, r5, #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tb.w\t8874 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x188>\n-\tldr.w\tr1, [r7, #436]\t@ 0x1b4\n+\tlsl.w\tr5, r3, r4\n+\tadd.w\tr8, r5, #1\n+\tb.w\t8c72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x196>\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n \tcmp\tr1, #0\n-\tble.w\taa8e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23a2>\n+\tble.w\tb6bc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2be0>\n \tmov\tr2, r3\n-\tldr.w\tr3, [r7, #252]\t@ 0xfc\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tlsls\tr0, r2, #2\n-\tldr.w\tr2, [r7, #528]\t@ 0x210\n+\tldr.w\tr2, [r7, #740]\t@ 0x2e4\n \tadd.w\tr1, r3, r1, lsl #2\n \tldr.w\tr4, [r3], #4\n \tstr\tr4, [r2, #0]\n \tadd\tr2, r0\n \tcmp\tr1, r3\n-\tbne.n\td8aa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51be>\n-\tb.w\taa8e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23a2>\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tbne.n\te33e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5862>\n+\tb.w\tb6bc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2be0>\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tcmp\tr3, #0\n-\tblt.w\tdb14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5428>\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tmov\tr1, sp\n-\tlsls\tr3, r3, #2\n-\tadds\tr3, #7\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr3, r3, #7\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n-\tbeq.n\td8f0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5204>\n+\tblt.n\te3be <__gridxc_gpfa_core_sp_MOD_gpfa_+0x58e2>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tlsls\tr2, r3, #2\n+\tmov\tr3, sp\n+\tadds\tr2, #7\n+\tbic.w\tr1, r2, #4080\t@ 0xff0\n+\tbic.w\tr2, r2, #7\n+\tbic.w\tr1, r1, #15\n+\tsub.w\tr1, sp, r1\n+\tcmp\tr3, r1\n+\tbeq.n\te382 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x58a6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n+\tmov\tr3, sp\n+\tcmp\tr3, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\td8e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51f6>\n-\tubfx\tr3, r3, #0, #12\n-\tsub.w\tsp, sp, r3\n-\tcbz\tr3, d900 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5214>\n-\tsubs\tr3, #4\n-\tadd\tr3, sp\n+\tbne.n\te374 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5898>\n+\tubfx\tr2, r2, #0, #12\n+\tsub.w\tsp, sp, r2\n+\tcbz\tr2, e394 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x58b8>\n+\tsubs\tr2, #4\n+\tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tadd\tr1, sp, #24\n-\tldr.w\tr4, [r7, #512]\t@ 0x200\n-\tstr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tlsls\tr0, r3, #2\n-\tmovs\tr3, #0\n-\tldr\tr2, [r4, #0]\n-\tadds\tr3, #1\n-\tstr.w\tr2, [r1], #4\n-\tadd\tr4, r0\n-\tldr.w\tr2, [r7, #480]\t@ 0x1e0\n-\tcmp\tr2, r3\n-\tbge.n\td912 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5226>\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tb.w\tab32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2446>\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tadd\tr5, sp, #24\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tmov\tr0, r5\n+\tmovs\tr2, #0\n+\tlsls\tr6, r3, #2\n+\tldr\tr3, [r1, #0]\n+\tadds\tr2, #1\n+\tstr.w\tr3, [r0], #4\n+\tadd\tr1, r6\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tcmp\tr3, r2\n+\tbge.n\te3a4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x58c8>\n+\tstr.w\tr5, [r7, #224]\t@ 0xe0\n+\tb.w\taf54 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2478>\n+\tadd.w\tr3, r7, #816\t@ 0x330\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tmov\tr5, r3\n+\tb.w\taf54 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2478>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n \tmov\tr1, sp\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\td95c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5270>\n+\tbeq.n\te3f8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x591c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\td94e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5262>\n+\tbne.n\te3ea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x590e>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, d96c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5280>\n+\tcbz\tr3, e408 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x592c>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tadd\tr1, sp, #24\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tmov\tr9, r1\n-\tlsls\tr6, r3, #2\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tstr.w\tr1, [r7, #788]\t@ 0x314\n+\tlsls\tr5, r3, #2\n \tmovs\tr3, #0\n-\tldr\tr4, [r2, #0]\n+\tldr\tr6, [r2, #0]\n \tadds\tr3, #1\n-\tstr.w\tr4, [r1], #4\n-\tadd\tr2, r6\n-\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tcmp\tr4, r3\n-\tbge.n\td97c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5290>\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tmov\tr1, r9\n-\tvstr\td0, [r7, #560]\t@ 0x230\n+\tstr.w\tr6, [r1], #4\n+\tadd\tr2, r5\n+\tldr.w\tr6, [r7, #680]\t@ 0x2a8\n+\tcmp\tr6, r3\n+\tbge.n\te41a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x593e>\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tldr\tr3, [r3, #0]\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n \tldr\tr2, [r2, #0]\n-\tstrd\tr5, r2, [sp, #8]\n-\tldr.w\tr4, [sl]\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tstr\tr4, [sp, #4]\n-\tldr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #0]\n-\tbl\t48d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tvldr\td0, [r7, #560]\t@ 0x230\n+\tstrd\tr4, r2, [sp, #8]\n+\tldr.w\tr6, [fp]\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr1, [r7, #788]\t@ 0x314\n+\tstr\tr6, [sp, #4]\n+\tldr.w\tr6, [r7, #664]\t@ 0x298\n+\tldr\tr6, [r6, #0]\n+\tstr\tr6, [sp, #0]\n+\tbl\t4bb8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #1\n-\tbeq.n\td9e6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x52fa>\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n+\tbeq.n\te47e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59a2>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n \tcmp\tr3, #0\n-\tbgt.w\td84c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5160>\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tbgt.w\te2e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5806>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n \tcmp\tr3, #0\n-\tble.n\tda00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5314>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tlsls\tr6, r3, #2\n-\tldr.w\tr1, [r7, #432]\t@ 0x1b0\n-\tmov\tr3, r9\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tadd.w\tr1, r9, r1, lsl #2\n+\tble.n\te49a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59be>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tlsls\tr5, r3, #2\n+\tldr.w\tr3, [r7, #788]\t@ 0x314\n+\tldr.w\tr1, [r7, #652]\t@ 0x28c\n+\tldr.w\tr2, [r7, #732]\t@ 0x2dc\n+\tadd.w\tr1, r3, r1, lsl #2\n \tldr.w\tr0, [r3], #4\n \tstr\tr0, [r2, #0]\n-\tadd\tr2, r6\n+\tadd\tr2, r5\n \tcmp\tr3, r1\n-\tbne.n\td9f4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5308>\n-\tcmp\tr5, #31\n+\tbne.n\te48e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59b2>\n+\tcmp\tr4, #31\n \tmov\tsp, r8\n-\tble.w\td880 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5194>\n-\tmovs\tr3, #1\n-\tmovs\tr5, #0\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tb.w\t8874 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x188>\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\titt\tgt\n+\tmovgt\tr5, #0\n+\tmovgt.w\tr8, #1\n+\tbgt.w\t8c72 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x196>\n+\tb.n\te316 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x583a>\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n \tcmp\tr3, #0\n-\tble.w\tdd14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5628>\n-\tmov\tr9, sp\n+\tble.w\te7a4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5cc8>\n \tmovs\tr5, #0\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tldr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tmov.w\tr8, #1\n+\tstr.w\tsp, [r7, #700]\t@ 0x2bc\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tcmp\tr3, #0\n-\tblt.w\tdbfc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5510>\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n-\tmov\tr1, sp\n-\tlsls\tr3, r3, #2\n-\tadds\tr3, #7\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr3, r3, #7\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n-\tbeq.n\tda5e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5372>\n+\tblt.w\te698 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5bbc>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tlsls\tr2, r3, #2\n+\tmov\tr3, sp\n+\tadds\tr2, #7\n+\tbic.w\tr1, r2, #4080\t@ 0xff0\n+\tbic.w\tr2, r2, #7\n+\tbic.w\tr1, r1, #15\n+\tsub.w\tr1, sp, r1\n+\tcmp\tr3, r1\n+\tbeq.n\te4f6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a1a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n+\tmov\tr3, sp\n+\tcmp\tr3, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tda50 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5364>\n-\tubfx\tr3, r3, #0, #12\n-\tsub.w\tsp, sp, r3\n-\tcbz\tr3, da6e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5382>\n-\tsubs\tr3, #4\n-\tadd\tr3, sp\n+\tbne.n\te4e8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a0c>\n+\tubfx\tr2, r2, #0, #12\n+\tsub.w\tsp, sp, r2\n+\tcbz\tr2, e508 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a2c>\n+\tsubs\tr2, #4\n+\tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tmovs\tr2, #0\n-\tldr.w\tr1, [r7, #528]\t@ 0x210\n-\tadd\tr0, sp, #24\n-\tstr.w\tr0, [r7, #552]\t@ 0x228\n-\tlsls\tr3, r3, #2\n-\tldr\tr4, [r1, #0]\n-\tadds\tr2, #1\n-\tstr.w\tr4, [r0], #4\n-\tadd\tr1, r3\n-\tldr.w\tr4, [r7, #484]\t@ 0x1e4\n-\tcmp\tr4, r2\n-\tbge.n\tda80 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5394>\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tstr.w\tr3, [r7, #340]\t@ 0x154\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tmovs\tr1, #0\n+\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tadd\tr4, sp, #24\n+\tstr.w\tr4, [r7, #752]\t@ 0x2f0\n+\tlsls\tr2, r3, #2\n+\tldr\tr3, [r0, #0]\n+\tadds\tr1, #1\n+\tstr.w\tr3, [r4], #4\n+\tadd\tr0, r2\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tcmp\tr3, r1\n+\tbge.n\te51a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a3e>\n+\tldr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbeq.w\t889c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b0>\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tbeq.w\t8c9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1c2>\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tcmp\tr3, #0\n-\tblt.w\tdbca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54de>\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tmov\tr1, sp\n-\tlsls\tr3, r3, #2\n-\tadds\tr3, #7\n-\tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tbic.w\tr3, r3, #7\n-\tbic.w\tr2, r2, #15\n-\tsub.w\tr2, sp, r2\n-\tcmp\tr1, r2\n-\tbeq.n\tdada <__gridxc_gpfa_core_sp_MOD_gpfa_+0x53ee>\n-\tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr1, sp\n-\tcmp\tr1, r2\n-\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tdacc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x53e0>\n-\tubfx\tr3, r3, #0, #12\n-\tsub.w\tsp, sp, r3\n-\tcbz\tr3, daea <__gridxc_gpfa_core_sp_MOD_gpfa_+0x53fe>\n-\tsubs\tr3, #4\n-\tadd\tr3, sp\n-\tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tadd\tr6, sp, #24\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tmov\tr1, r6\n-\tlsls\tr0, r3, #2\n-\tmovs\tr3, #0\n-\tldr\tr4, [r2, #0]\n-\tadds\tr3, #1\n-\tstr.w\tr4, [r1], #4\n-\tadd\tr2, r0\n-\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tcmp\tr4, r3\n-\tbge.n\tdafa <__gridxc_gpfa_core_sp_MOD_gpfa_+0x540e>\n-\tstr.w\tr6, [r7, #336]\t@ 0x150\n-\tb.w\t88a0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b4>\n-\tadd.w\tr3, r7, #592\t@ 0x250\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tb.w\tab32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2446>\n-\tldr.w\tr0, [r7, #436]\t@ 0x1b4\n-\tcmp\tr0, #0\n-\tble.w\tdcca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x55de>\n-\tldr.w\tr2, [r7, #340]\t@ 0x154\n-\tlsls\tr3, r3, #2\n-\tldr.w\tr1, [r7, #528]\t@ 0x210\n-\tadd.w\tr0, r2, r0, lsl #2\n-\tldr.w\tr4, [r2], #4\n-\tstr\tr4, [r1, #0]\n-\tadd\tr1, r3\n-\tcmp\tr2, r0\n-\tbne.n\tdb3c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5450>\n-\tldr.w\tr2, [r7, #532]\t@ 0x214\n-\tcmp\tr2, #1\n-\tbne.w\tdcac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x55c0>\n-\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n-\tmov\tsp, r9\n-\tcmp\tr2, #0\n-\tit\tgt\n-\tmovgt\tr6, sp\n-\tble.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tldr.w\tr2, [r7, #436]\t@ 0x1b4\n-\tmov\tr0, sp\n-\tlsls\tr2, r2, #2\n+\tblt.w\te666 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b8a>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tlsls\tr2, r3, #2\n+\tmov\tr3, sp\n \tadds\tr2, #7\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n-\tcmp\tr0, r1\n-\tbeq.n\tdb8e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54a2>\n+\tcmp\tr3, r1\n+\tbeq.n\te574 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a98>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr0, sp\n-\tcmp\tr0, r1\n+\tmov\tr3, sp\n+\tcmp\tr3, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tdb80 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5494>\n+\tbne.n\te566 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5a8a>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, db9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54b2>\n+\tcbz\tr2, e586 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5aaa>\n \tsubs\tr2, #4\n-\tadd\tr2, sp\n-\tstr\tr0, [r2, #0]\n-\tadd\tr5, sp, #24\n-\tldr.w\tr1, [r7, #528]\t@ 0x210\n-\tmov\tr0, r5\n+\tadd.w\tr3, sp, r2\n+\tstr\tr0, [r3, #0]\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tmovs\tr2, #0\n-\tldr\tr4, [r1, #0]\n+\tldr.w\tr1, [r7, #732]\t@ 0x2dc\n+\tadd\tr0, sp, #24\n+\tstr.w\tr0, [r7, #748]\t@ 0x2ec\n+\tlsls\tr4, r3, #2\n+\tldr\tr3, [r1, #0]\n \tadds\tr2, #1\n-\tstr.w\tr4, [r0], #4\n-\tadd\tr1, r3\n-\tldr.w\tr4, [r7, #484]\t@ 0x1e4\n-\tcmp\tr4, r2\n-\tbge.n\tdba8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x54bc>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tstr.w\tr5, [r7, #252]\t@ 0xfc\n+\tstr.w\tr3, [r0], #4\n+\tadd\tr1, r4\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n+\tcmp\tr3, r2\n+\tbge.n\te598 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5abc>\n+\tldr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tb.w\t8ca6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ca>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tcmp\tr3, #0\n+\tble.w\te758 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5c7c>\n+\tldr.w\tr1, [r7, #424]\t@ 0x1a8\n+\tldr.w\tr2, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tadd.w\tr4, r1, r3, lsl #2\n+\tlsls\tr2, r2, #2\n+\tldr.w\tr3, [r1], #4\n+\tstr\tr3, [r0, #0]\n+\tadd\tr0, r2\n+\tcmp\tr1, r4\n+\tbne.n\te5d2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5af6>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbeq.w\tab2a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x243e>\n-\tb.n\td8ba <__gridxc_gpfa_core_sp_MOD_gpfa_+0x51ce>\n-\tadd.w\tr3, r7, #592\t@ 0x250\n-\tstr.w\tr3, [r7, #336]\t@ 0x150\n-\tmov\tr6, r3\n-\tb.w\t88a0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b4>\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tbne.w\te736 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5c5a>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tble.n\tdc0c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5520>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tmov\tr9, sp\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tit\tgt\n+\tstrgt.w\tsp, [r7, #500]\t@ 0x1f4\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tlsls\tr1, r3, #2\n+\tmov\tr3, sp\n+\tadds\tr1, #7\n+\tbic.w\tr0, r1, #4080\t@ 0xff0\n+\tbic.w\tr1, r1, #7\n+\tbic.w\tr0, r0, #15\n+\tsub.w\tr0, sp, r0\n+\tcmp\tr3, r0\n+\tbeq.n\te628 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b4c>\n+\tsub.w\tsp, sp, #4096\t@ 0x1000\n+\tmov\tr3, sp\n+\tcmp\tr3, r0\n+\tstr.w\tr0, [sp, #4092]\t@ 0xffc\n+\tbne.n\te61a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b3e>\n+\tubfx\tr1, r1, #0, #12\n+\tsub.w\tsp, sp, r1\n+\tcbz\tr1, e63a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b5e>\n+\tsubs\tr1, #4\n+\tadd.w\tr3, sp, r1\n+\tstr\tr0, [r3, #0]\n+\tadd\tr4, sp, #24\n+\tldr.w\tr0, [r7, #740]\t@ 0x2e4\n+\tmov\tr5, r4\n+\tmovs\tr1, #0\n+\tldr\tr3, [r0, #0]\n+\tadds\tr1, #1\n+\tstr.w\tr3, [r5], #4\n+\tadd\tr0, r2\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n+\tcmp\tr3, r1\n+\tbge.n\te644 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b68>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n+\tstr.w\tr4, [r7, #228]\t@ 0xe4\n+\tcmp\tr3, #1\n+\tbeq.w\taf50 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2474>\n+\tb.n\te34e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5872>\n+\tadd.w\tr3, r7, #816\t@ 0x330\n+\tstr.w\tr3, [r7, #400]\t@ 0x190\n+\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tb.w\t8ca6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ca>\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n+\tcmp\tr3, #0\n+\tble.n\te6a8 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5bcc>\n+\tldrd\tr3, r8, [r7, #740]\t@ 0x2e4\n+\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tldr.w\tr3, [r7, #732]\t@ 0x2dc\n \tmovs\tr5, #0\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tldr.w\tr6, [r7, #512]\t@ 0x200\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tb.w\t88a0 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b4>\n-\tadd.w\tr3, r7, #576\t@ 0x240\n-\tstr.w\tr3, [r7, #340]\t@ 0x154\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tb.w\t8892 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1a6>\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tstr.w\tsp, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr3, [r7, #748]\t@ 0x2ec\n+\tb.w\t8ca6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1ca>\n+\tadd.w\tr3, r7, #800\t@ 0x320\n+\tstr.w\tr3, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tb.w\t8c94 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b8>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, #0\n-\tble.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n-\tmov\tr6, sp\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tb.w\tab2a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x243e>\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tldrd\tr4, r8, [r7, #740]\t@ 0x2e4\n+\tstr.w\tsp, [r7, #500]\t@ 0x1f4\n+\tb.w\taf50 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2474>\n+\tldr.w\tr3, [r7, #680]\t@ 0x2a8\n \tcmp\tr3, #0\n-\tbge.w\td930 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5244>\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tadd.w\tr6, r7, #592\t@ 0x250\n-\tvstr\td0, [r7, #560]\t@ 0x230\n+\tbge.w\te3cc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x58f0>\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tadd.w\tr5, r7, #816\t@ 0x330\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n \tldr\tr3, [r3, #0]\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n+\tldr.w\tr2, [r7, #660]\t@ 0x294\n \tldr\tr2, [r2, #0]\n-\tstrd\tr5, r2, [sp, #8]\n-\tldr.w\tr1, [sl]\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tstrd\tr4, r2, [sp, #8]\n+\tldr.w\tr1, [fp]\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n \tstr\tr1, [sp, #4]\n-\tmov\tr1, r6\n-\tldr.w\tr4, [r7, #456]\t@ 0x1c8\n-\tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #0]\n-\tbl\t48d0 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tvldr\td0, [r7, #560]\t@ 0x230\n+\tmov\tr1, r5\n+\tldr.w\tr6, [r7, #664]\t@ 0x298\n+\tldr\tr6, [r6, #0]\n+\tstr\tr6, [sp, #0]\n+\tbl\t4bb8 <__gridxc_gpfa_core_sp_MOD_gpfa2f.isra.0>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n \tcmp\tr3, #1\n-\tbne.n\tdc9e <__gridxc_gpfa_core_sp_MOD_gpfa_+0x55b2>\n-\tcmp\tr5, #31\n+\tbne.n\te726 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5c4a>\n+\tcmp\tr4, #31\n \tmov\tsp, r8\n-\tble.w\td880 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5194>\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n+\tble.w\te316 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x583a>\n+\tldr.w\tr3, [r7, #708]\t@ 0x2c4\n \tcmp\tr3, #0\n-\tble.n\tdd14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5628>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tmov\tr9, sp\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tble.n\te7a4 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5cc8>\n+\tldrd\tr8, r3, [r7, #736]\t@ 0x2e0\n \tmovs\tr5, #0\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tb.w\t8892 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1a6>\n-\tldr.w\tr3, [r7, #436]\t@ 0x1b4\n+\tstr.w\tsp, [r7, #700]\t@ 0x2bc\n+\tstr.w\tr3, [r7, #752]\t@ 0x2f0\n+\tb.w\t8c94 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x1b8>\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n \tcmp\tr3, #0\n-\tble.w\tda00 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5314>\n-\tmov\tr9, r6\n-\tb.n\td84c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5160>\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tble.w\te49a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x59be>\n+\tstr.w\tr5, [r7, #788]\t@ 0x314\n+\tb.n\te2e2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5806>\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n \tcmp\tr3, #0\n-\tbgt.w\taad2 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23e6>\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tmov\tsp, r9\n+\tbgt.w\taeee <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2412>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n \tit\tgt\n-\tmovgt\tr6, sp\n-\tbgt.w\tab0c <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2420>\n-\tb.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tldr.w\tr3, [r7, #532]\t@ 0x214\n+\tstrgt.w\tsp, [r7, #500]\t@ 0x1f4\n+\tbgt.w\taf30 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2454>\n+\tb.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr3, #1\n-\tbne.n\tdcac <__gridxc_gpfa_core_sp_MOD_gpfa_+0x55c0>\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tmov\tsp, r9\n+\tbne.n\te736 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5c5a>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tble.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tadd.w\tr3, r7, #576\t@ 0x240\n-\tmov\tr6, sp\n-\tmov\tr5, r3\n-\tstr.w\tr3, [r7, #252]\t@ 0xfc\n-\tb.w\tab2a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x243e>\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tmov\tsp, r9\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tadd.w\tr3, r7, #800\t@ 0x320\n+\tstr.w\tsp, [r7, #500]\t@ 0x1f4\n+\tmov\tr4, r3\n+\tstr.w\tr3, [r7, #228]\t@ 0xe4\n+\tb.w\taf50 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2474>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tsp, [r7, #700]\t@ 0x2bc\n \tcmp\tr3, #0\n-\tble.w\taa9a <__gridxc_gpfa_core_sp_MOD_gpfa_+0x23ae>\n-\tadd.w\tr3, r7, #592\t@ 0x250\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n-\tmov\tr6, sp\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tstr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tb.w\tab32 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2446>\n+\tble.w\tb6ca <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2bee>\n+\tadd.w\tr3, r7, #816\t@ 0x330\n+\tldr.w\tr4, [r7, #740]\t@ 0x2e4\n+\tmov\tr5, r3\n+\tstr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tsp, [r7, #500]\t@ 0x1f4\n+\tb.w\taf54 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2478>\n+\tmov.w\tr8, #1\n+\tb.w\taf14 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x2438>\n+\tldr.w\tr3, [r7, #736]\t@ 0x2e0\n+\tlsls\tr2, r3, #2\n+\tb.n\te5fc <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5b20>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #500]\t@ 0x1f4\n-\tb.w\taaf6 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x240a>\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tlsls\tr3, r3, #2\n-\tb.n\tdb62 <__gridxc_gpfa_core_sp_MOD_gpfa_+0x5476>\n-\tnop\n \n-0000dd28 <__gridxc_gpfa_core_dp_MOD_gpfa_>:\n+0000e7b8 <__gridxc_gpfa_core_dp_MOD_gpfa_>:\n __gridxc_gpfa_core_dp_MOD_gpfa_.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #2976]\t@ 0xba0\n-\tsub.w\tsp, sp, #1020\t@ 0x3fc\n+\tstr.w\tr0, [ip, #2792]\t@ 0xae8\n+\tsubw\tsp, sp, #1204\t@ 0x4b4\n \tadd\tr7, sp, #24\n-\tmov.w\tfp, #1\n-\tadd.w\tr5, r7, #612\t@ 0x264\n-\tmov\tlr, r5\n-\tldr.w\tr4, [r7, #1096]\t@ 0x448\n-\tstrd\tr2, r4, [r7, #584]\t@ 0x248\n-\tldr\tr2, [pc, #336]\t@ (dea8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x180>)\n-\tstr.w\tr3, [r7, #592]\t@ 0x250\n-\tldr\tr3, [pc, #336]\t@ (deac <__gridxc_gpfa_core_dp_MOD_gpfa_+0x184>)\n+\tmov.w\tsl, #2\n+\tadd.w\tr5, r7, #796\t@ 0x31c\n+\tstr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr\tr2, [pc, #380]\t@ (e95c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1a4>)\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr\tr3, [pc, #376]\t@ (e960 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1a8>)\n \tadd\tr2, pc\n-\tldr.w\tr6, [r7, #1100]\t@ 0x44c\n-\tstr.w\tr6, [r7, #596]\t@ 0x254\n+\tldr.w\tr6, [r7, #1284]\t@ 0x504\n+\tldr.w\tr4, [r7, #1280]\t@ 0x500\n+\tstr.w\tr6, [r7, #780]\t@ 0x30c\n+\tstr.w\tr4, [r7, #772]\t@ 0x304\n \tldr\tr4, [r1, #24]\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr8, [r7, #1104]\t@ 0x450\n+\tldr.w\tfp, [r6]\n+\tmovs\tr6, #1\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #988]\t@ 0x3dc\n+\tstr.w\tr3, [r7, #1172]\t@ 0x494\n \tmov.w\tr3, #0\n \tldr\tr3, [r0, #24]\n-\tldr.w\tr9, [r7, #1108]\t@ 0x454\n+\tldr.w\tr8, [r7, #1288]\t@ 0x508\n \tcmp\tr3, #0\n+\tldr.w\tr9, [r7, #1292]\t@ 0x50c\n \tit\teq\n \tmoveq\tr3, #1\n-\tstr.w\tr3, [r7, #368]\t@ 0x170\n+\tstr.w\tr3, [r7, #420]\t@ 0x1a4\n \tldrd\tr3, r2, [r0, #28]\n \tcmp\tr4, #0\n+\tstr.w\tr5, [r7, #768]\t@ 0x300\n \tit\teq\n \tmoveq\tr4, #1\n \tsubs\tr3, r2, r3\n \tldr\tr2, [r0, #0]\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tstr.w\tr2, [r7, #348]\t@ 0x15c\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tstr.w\tr2, [r7, #404]\t@ 0x194\n \tldrd\tr3, r2, [r1, #28]\n-\tsubs\tr0, r2, r3\n-\tldr\tr2, [r1, #0]\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr\tr1, [pc, #260]\t@ (deb0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x188>)\n+\tstr.w\tr4, [r7, #680]\t@ 0x2a8\n+\tldr\tr1, [r1, #0]\n+\tsubs\tr2, r2, r3\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n \tadds\tr3, #1\n-\tstr.w\tr2, [r7, #344]\t@ 0x158\n-\tadd\tr1, pc\n-\tstr.w\tr3, [r7, #248]\t@ 0xf8\n-\tstr.w\tr0, [r7, #568]\t@ 0x238\n-\tadds\tr3, r0, #1\n-\tldr\tr2, [r6, #0]\n+\tstr.w\tr3, [r7, #252]\t@ 0xfc\n+\tadds\tr3, r2, #1\n \tstr.w\tr3, [r7, #160]\t@ 0xa0\n-\tmovs\tr3, #2\n-\tstr.w\tr1, [r7, #520]\t@ 0x208\n-\tsdiv\tr0, r2, r3\n-\tmls\tr1, r3, r0, r2\n+\tldr\tr3, [pc, #264]\t@ (e964 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ac>)\n+\tstr.w\tr1, [r7, #400]\t@ 0x190\n+\tadd\tr3, pc\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tmov\tr3, r5\n+\tmov\tr5, r6\n+\tmov\tr6, r3\n+\tmov\tr1, sl\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr4, r1\n \tcmp\tr1, #0\n-\tbne.n\tde92 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x16a>\n-\tmov\tr2, r0\n-\tadds\tr1, #1\n-\tsdiv\tr0, r0, r3\n-\tmls\tr6, r3, r0, r2\n-\tcmp\tr6, #0\n-\tbeq.n\tddd6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xae>\n-\tadd\tr3, fp\n-\tadd.w\tfp, fp, #1\n-\tcmp.w\tfp, #4\n-\tstr.w\tr1, [lr], #4\n-\tbne.n\tddca <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa2>\n-\tcmp\tr2, #1\n-\tbne.w\tecbe <__gridxc_gpfa_core_dp_MOD_gpfa_+0xf96>\n+\tbne.n\te958 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1a0>\n+\tmov\tr0, fp\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, sl\n+\tadds\tr4, #1\n+\tmov\tfp, r0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.n\te87a <__gridxc_gpfa_core_dp_MOD_gpfa_+0xc2>\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tadd\tsl, r5\n+\tadds\tr5, #1\n+\tcmp\tr5, #4\n+\tstr.w\tr4, [r3], #4\n+\tstr.w\tr3, [r7, #768]\t@ 0x300\n+\tbne.n\te86c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb4>\n+\tmov\tr3, r6\n+\tldr.w\tr4, [r7, #680]\t@ 0x2a8\n+\tmov\tr6, r5\n+\tcmp.w\tfp, #1\n+\tmov\tr5, r3\n+\tbne.w\tf862 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x10aa>\n \tldrd\tfp, sl, [r5]\n \tldr\tr3, [r5, #8]\n \tcmp.w\tfp, #0\n \tstr.w\tr3, [r7, #140]\t@ 0x8c\n-\tble.n\tdeb4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x18c>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tstr.w\tsp, [r7, #560]\t@ 0x230\n+\tble.n\te968 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1b0>\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tstr.w\tsp, [r7, #768]\t@ 0x300\n \tcmp\tr3, #1\n-\tbne.w\t108de <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2bb6>\n-\tldr.w\tr0, [r7, #348]\t@ 0x15c\n+\tbne.w\t11708 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f50>\n \tcmp\tr4, #1\n-\tbne.w\t10eec <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31c4>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tit\tne\n+\tldrne.w\tr0, [r7, #404]\t@ 0x194\n+\tbne.w\t11c28 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3470>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr2, [r9]\n-\tvstr\td3, [r7, #528]\t@ 0x210\n-\tvstr\td0, [r7, #544]\t@ 0x220\n-\tvstr\td1, [r7, #552]\t@ 0x228\n-\tvstr\td2, [r7, #560]\t@ 0x230\n \tldr\tr3, [r3, #0]\n \tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tldr.w\tr1, [r8]\n \tstrd\tfp, r1, [sp, #8]\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tldrd\tr1, r0, [r7, #344]\t@ 0x158\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n+\tldrd\tr1, r0, [r7, #400]\t@ 0x190\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #4]\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n+\tldr.w\tr5, [r7, #772]\t@ 0x304\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0>\n \tcmp.w\tfp, #31\n-\tvldr\td2, [r7, #560]\t@ 0x230\n-\tvldr\td1, [r7, #552]\t@ 0x228\n-\tvldr\td0, [r7, #544]\t@ 0x220\n-\tvldr\td3, [r7, #528]\t@ 0x210\n-\tbgt.w\t10e8c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3164>\n-\tmovs\tr2, #2\n+\tble.w\t119a2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31ea>\n \tcmp.w\tsl, #0\n-\tlsl.w\tr2, r2, fp\n-\tadd.w\tfp, r2, #1\n-\tble.n\tdf5c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x234>\n-\tstr.w\tsp, [r7, #560]\t@ 0x230\n-\tb.n\tdece <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1a6>\n-\tadd\tr3, fp\n-\tadd.w\tfp, fp, #1\n-\tmovs\tr1, #0\n-\tcmp.w\tfp, #4\n-\tstr.w\tr1, [lr], #4\n-\tbne.n\tddca <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa2>\n-\tb.n\tddf6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xce>\n-\tnop\n-\t.word\t0x00000148\n+\tble.w\t11ca0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x34e8>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tmov\tfp, r4\n+\tldr.w\tr2, [r9]\n+\tldr\tr3, [r3, #0]\n+\tstr\tr2, [sp, #16]\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr1, [r8]\n+\tstrd\tsl, r1, [sp, #8]\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n+\tldrd\tr1, r0, [r7, #400]\t@ 0x190\n+\tldr\tr5, [r5, #0]\n+\tstr\tr5, [sp, #4]\n+\tldr.w\tr5, [r7, #772]\t@ 0x304\n+\tstr.w\tsp, [r7, #768]\t@ 0x300\n+\tldr\tr5, [r5, #0]\n+\tstr\tr5, [sp, #0]\n+\tbl\t3338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n+\tb.n\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n+\tmovs\tr4, #0\n+\tb.n\te890 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd8>\n+\t.word\t0x00000172\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000fa\n+\t.word\t0x00000100\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \tmovs\tr2, #0\n \tmov.w\tfp, #1\n \tcmp.w\tsl, #0\n-\tble.n\tdf5c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x234>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tstr.w\tsp, [r7, #560]\t@ 0x230\n+\tble.n\te9d2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x21a>\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tstr.w\tsp, [r7, #768]\t@ 0x300\n \tcmp\tr3, #1\n-\tbne.w\t10ac6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d9e>\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tbne.w\t118c8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3110>\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr4, #1\n-\tldr.w\tr0, [r7, #348]\t@ 0x15c\n \tadd.w\tr2, r3, r2, lsl #3\n-\tbne.w\t10c9c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f74>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tit\tne\n+\tldrne.w\tr0, [r7, #404]\t@ 0x194\n+\tbne.w\t11a9a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32e2>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr1, [r9]\n-\tvstr\td3, [r7, #528]\t@ 0x210\n-\tvstr\td0, [r7, #536]\t@ 0x218\n-\tvstr\td1, [r7, #544]\t@ 0x220\n-\tvstr\td2, [r7, #552]\t@ 0x228\n \tldr\tr3, [r3, #0]\n \tstr\tr1, [sp, #16]\n \tldr.w\tr1, [r8]\n \tstrd\tsl, r1, [sp, #8]\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tldrd\tr1, r0, [r7, #344]\t@ 0x158\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n+\tldrd\tr1, r0, [r7, #400]\t@ 0x190\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #4]\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n+\tldr.w\tr5, [r7, #772]\t@ 0x304\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #0]\n-\tbl\t30a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n-\tvldr\td2, [r7, #552]\t@ 0x228\n-\tvldr\td1, [r7, #544]\t@ 0x220\n-\tvldr\td0, [r7, #536]\t@ 0x218\n-\tvldr\td3, [r7, #528]\t@ 0x210\n-\tvstr\td3, [r7, #528]\t@ 0x210\n+\tbl\t3338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n \tmov\tr1, sl\n-\tvstr\td0, [r7, #536]\t@ 0x218\n \tmovs\tr0, #3\n-\tvstr\td1, [r7, #544]\t@ 0x220\n-\tvstr\td2, [r7, #552]\t@ 0x228\n-\tldr.w\tsp, [r7, #560]\t@ 0x230\n+\tldr.w\tsp, [r7, #768]\t@ 0x300\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tvldr\td2, [r7, #552]\t@ 0x228\n \tadd.w\tfp, fp, r0, lsl #1\n-\tvldr\td1, [r7, #544]\t@ 0x220\n-\tvldr\td0, [r7, #536]\t@ 0x218\n-\tvldr\td3, [r7, #528]\t@ 0x210\n \tldr.w\tr3, [r7, #140]\t@ 0x8c\n \tcmp\tr3, #0\n-\tble.w\te736 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa0e>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tldr.w\tr6, [r7, #348]\t@ 0x15c\n+\tble.w\tf232 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa7a>\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tstr.w\tsp, [r7, #64]\t@ 0x40\n \tcmp\tr3, #1\n-\tstr.w\tsp, [r7, #96]\t@ 0x60\n-\tbne.w\t10b32 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e0a>\n+\tit\teq\n+\tldreq.w\tr6, [r7, #404]\t@ 0x194\n+\tbne.w\t11934 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x317c>\n \tcmp\tr4, #1\n-\tbne.w\t10a44 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d1c>\n-\tldr.w\tr3, [r7, #344]\t@ 0x158\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tbne.w\t1184e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3096>\n+\tldr.w\tr5, [r7, #400]\t@ 0x190\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tadd.w\tr3, fp, #4294967295\t@ 0xffffffff\n \tldr.w\tr1, [r7, #140]\t@ 0x8c\n-\tvstr\td3, [r7, #544]\t@ 0x220\n-\tadd.w\tr3, r2, r3, lsl #3\n-\tstr.w\tr3, [r7, #132]\t@ 0x84\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tvstr\td0, [r7, #552]\t@ 0x228\n-\tvstr\td1, [r7, #560]\t@ 0x230\n-\tldr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tmov\tfp, r0\n \tmovs\tr0, #5\n-\tvstr\td2, [r7, #568]\t@ 0x238\n-\tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [r7, #128]\t@ 0x80\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tldr.w\tr5, [r9]\n-\tldr.w\tr8, [r8]\n+\tldr.w\tr9, [r9]\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr\tr3, [r7, #120]\t@ 0x78\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tvldr\td8, [pc, #584]\t@ ec60 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4a8>\n \tldr.w\tsl, [r3]\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr\tr3, [r3, #0]\n+\tstr\tr3, [r7, #116]\t@ 0x74\n+\tldr.w\tr3, [r7, #780]\t@ 0x30c\n+\tldr.w\tfp, [r3]\n+\tldr.w\tr3, [r8]\n+\tstr.w\tr3, [r7, #772]\t@ 0x304\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n+\tmov\tr8, r0\n+\tmov\tr0, fp\n+\tmov\tr1, r8\n+\tsub.w\tr8, r8, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp.w\tr9, #4294967295\t@ 0xffffffff\n+\tvmov\ts11, r9\n+\tvldr\td2, [pc, #532]\t@ ec68 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4b0>\n+\tmul.w\tr3, sl, r8\n+\tvldr\td3, [pc, #532]\t@ ec70 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4b8>\n+\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n \tmovw\tr3, #26215\t@ 0x6667\n \tmovt\tr3, #26214\t@ 0x6666\n-\tsub.w\tr2, r0, sl\n-\tvldr\td2, [r7, #568]\t@ 0x238\n-\tvldr\td1, [r7, #560]\t@ 0x230\n-\tsdiv\tr1, sl, r0\n-\tmov\tr0, fp\n-\tvldr\td0, [r7, #552]\t@ 0x228\n-\tvldr\td3, [r7, #544]\t@ 0x220\n-\tmul.w\tr2, r0, r2\n-\tstr.w\tr2, [r7, #364]\t@ 0x16c\n-\tsmull\tr3, r2, r3, r1\n-\tasrs\tr3, r1, #31\n-\tstr.w\tr1, [r7, #152]\t@ 0x98\n+\tvcvt.f64.s32\td5, s11\n+\tvldr\td4, [pc, #520]\t@ ec78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4c0>\n+\tmov\tlr, r0\n+\tvldr\td7, [pc, #524]\t@ ec80 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4c8>\n+\tsmull\tr3, r2, r3, r0\n+\tmov.w\tr3, r0, asr #31\n+\tvstr\td5, [r7, #104]\t@ 0x68\n+\tvldr\td6, [pc, #516]\t@ ec88 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4d0>\n \trsb\tr3, r3, r2, asr #1\n-\tmov\tr2, r1\n+\tmul.w\tr2, fp, sl\n+\tstr.w\tr2, [r7, #780]\t@ 0x30c\n+\tmul.w\tr2, r0, sl\n \tadd.w\tr3, r3, r3, lsl #2\n-\tmul.w\tr2, r2, fp\n-\tsubs\tr3, r1, r3\n-\tmul.w\tr1, sl, fp\n-\tstr.w\tr2, [r7, #136]\t@ 0x88\n-\tstr.w\tr1, [r7, #596]\t@ 0x254\n-\tadds\tr2, r5, #1\n-\tbne.n\te02a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x302>\n-\trsb\tr3, r3, #5\n-\tldr.w\tr2, [r7, #140]\t@ 0x8c\n-\tadds\tr2, #1\n-\tasrs\tr1, r2, #1\n+\tstr.w\tr2, [r7, #164]\t@ 0xa4\n+\tsub.w\tr3, r0, r3\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n+\tit\teq\n+\trsbeq\tr3, r3, #5\n \tsubs\tr2, r3, #2\n-\tcmp\tr2, #1\n-\tbls.w\teca6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xf7e>\n-\tvldr\td8, [pc, #940]\t@ e3e8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6c0>\n-\tvldr\td9, [pc, #944]\t@ e3f0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6c8>\n-\tvldr\td16, [pc, #948]\t@ e3f8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6d0>\n-\tvldr\td17, [pc, #952]\t@ e400 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6d8>\n-\tvldr\td10, [pc, #956]\t@ e408 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6e0>\n \tsubs\tr3, #3\n-\tcmp\tr3, #1\n-\tbls.n\te058 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x330>\n-\tvmov.f64\td9, d17\n+\tcmp\tr2, #2\n+\tite\tcs\n+\tvmovcs.f64\td5, d3\n+\tvmovcc.f64\td5, d2\n+\tite\tcs\n+\tvmovcs.f64\td15, d4\n+\tvmovcc.f64\td15, d8\n+\tit\tcc\n+\tvmovcc.f64\td8, d4\n+\tvstr\td5, [r7, #744]\t@ 0x2e8\n+\tite\tcs\n+\tvmovcs.f64\td5, d7\n+\tvmovcc.f64\td5, d6\n+\tit\tcs\n+\tvmovcs.f64\td7, d6\n+\tcmp\tr3, #2\n+\tit\tcs\n+\tvmovcs.f64\td8, d5\n \tbics.w\tr3, r2, #2\n-\tvmov\ts15, r5\n-\tadd.w\tr3, r8, #126\t@ 0x7e\n-\tvcvt.f64.s32\td17, s15\n-\tvseleq.f64\td8, d8, d16\n-\tsubs.w\tr2, r8, #1\n+\tadd.w\tr3, r1, #126\t@ 0x7e\n+\tit\tne\n+\tvmovne.f64\td15, d7\n+\tsubs\tr2, r1, #1\n \tit\tpl\n \tmovpl\tr3, r2\n-\tcmn.w\tr8, #126\t@ 0x7e\n+\tldr.w\tr2, [r7, #140]\t@ 0x8c\n+\tadds\tr1, #126\t@ 0x7e\n+\tadd.w\tr2, r2, #1\n \tmov.w\tr3, r3, asr #7\n-\tvstr\td17, [r7, #88]\t@ 0x58\n-\tblt.w\te722 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9fa>\n-\tadds\tr2, r1, #1\n-\tmov\tr1, fp\n-\tstr\tr2, [r7, #84]\t@ 0x54\n-\tadds\tr2, r3, #2\n-\tadd.w\tr3, sl, #4294967295\t@ 0xffffffff\n-\tvneg.f64\td11, d10\n-\tvneg.f64\td12, d8\n-\tldr.w\tlr, [r7, #580]\t@ 0x244\n-\tstr\tr4, [r7, #44]\t@ 0x2c\n-\tmov\tr4, r6\n-\tmul.w\tr1, r3, r1\n-\tvldr\td4, [r7, #480]\t@ 0x1e0\n-\tstr.w\tr1, [r7, #164]\t@ 0xa4\n+\tmov.w\tr2, r2, asr #1\n+\tblt.w\tf21e <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa66>\n+\tadd.w\tr8, r3, #2\n+\tadd.w\tr3, fp, #4294967295\t@ 0xffffffff\n+\tadds\tr2, #1\n+\tstr\tr2, [r7, #56]\t@ 0x38\n+\tldr\tr2, [r7, #116]\t@ 0x74\n+\tmul.w\tr3, sl, r3\n+\tstr.w\tr8, [r7, #20]\n+\tstr.w\tr3, [r7, #168]\t@ 0xa8\n \tmovs\tr3, #1\n-\tldr.w\tr1, [r7, #128]\t@ 0x80\n-\tstr.w\tr3, [r7, #592]\t@ 0x250\n-\tstr.w\tsl, [r7, #40]\t@ 0x28\n-\tlsls\tr1, r1, #3\n-\tstr\tr2, [r7, #36]\t@ 0x24\n-\tstr\tr1, [r7, #76]\t@ 0x4c\n+\tmov\tr9, r3\n+\tldr.w\tr8, [r7, #772]\t@ 0x304\n+\tmov\tsl, r9\n+\tlsls\tr2, r2, #3\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tsub.w\tr3, r6, #8\n+\tstr\tr2, [r7, #92]\t@ 0x5c\n+\tstr.w\tr3, [r7, #156]\t@ 0x9c\n+\tstr.w\tr5, [r7, #128]\t@ 0x80\n+\tstrd\tfp, r4, [r7, #24]\n+\tstr.w\tr0, [r7, #148]\t@ 0x94\n \tcmp.w\tr8, #128\t@ 0x80\n-\tble.w\tee10 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x10e8>\n+\titt\tle\n+\tstrle.w\tr8, [r7, #768]\t@ 0x300\n+\tmovle.w\tr8, #0\n+\tble.n\teb86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3ce>\n \tcmp.w\tr8, #255\t@ 0xff\n-\tbgt.w\tee02 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x10da>\n-\tmov.w\tr1, r8, asr #1\n-\tadds\tr1, #1\n-\tbic.w\tr2, r1, #1\n-\tstr.w\tr2, [r7, #568]\t@ 0x238\n-\tsub.w\tr8, r8, r2\n-\tstr.w\tr8, [r7, #456]\t@ 0x1c8\n-\tmov\tip, lr\n-\tldr.w\tr8, [r7, #136]\t@ 0x88\n-\tmov\tfp, r4\n-\tvldr\td7, [r7, #88]\t@ 0x58\n-\tmovs\tr2, #1\n-\tstr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tstr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tstr.w\tr2, [r7, #576]\t@ 0x240\n-\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n-\tcmp.w\tr8, #0\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tmov\tr0, r3\n-\tadd.w\tr3, r3, r3, lsl #2\n-\tstr.w\tr3, [r7, #488]\t@ 0x1e8\n-\tsdiv\tr3, r2, r3\n-\tsub.w\tr2, r3, r2\n-\tstr.w\tr2, [r7, #584]\t@ 0x248\n-\tsub.w\tr2, r3, r8\n-\tblt.w\tee1c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x10f4>\n-\tudiv\tr1, r2, r8\n-\tcmp\tr2, #0\n-\tblt.w\te6dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9b4>\n+\titete\tle\n+\tmovle.w\tr3, r8, asr #1\n+\tsubgt.w\tr8, r8, #128\t@ 0x80\n+\taddle\tr3, #1\n+\tmovgt\tr3, #128\t@ 0x80\n+\titett\tle\n+\tbicle.w\tr3, r3, #1\n+\tstrgt.w\tr3, [r7, #768]\t@ 0x300\n+\tsuble.w\tr8, r8, r3\n+\tstrle.w\tr3, [r7, #768]\t@ 0x300\n+\tmov\tfp, r6\n+\tvldr\td14, [r7, #744]\t@ 0x2e8\n+\tmovs\tr3, #1\n+\tstr.w\tr8, [r7, #576]\t@ 0x240\n+\tstr.w\tr3, [r7, #136]\t@ 0x88\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n+\tstr.w\tsl, [r7, #600]\t@ 0x258\n+\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n+\tmov\tr6, r3\n \tadd.w\tr3, r3, r3, lsl #2\n-\tlsls\tr2, r0, #1\n-\tnegs\tr4, r3\n-\tstr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr4, [r7, #128]\t@ 0x80\n-\tcmp\tr4, #1\n-\tmov.w\tr4, #24\n-\tmul.w\tr2, r4, r2\n-\tbne.w\te760 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa38>\n-\tstr.w\tr2, [r7, #464]\t@ 0x1d0\n-\tlsls\tr4, r0, #4\n-\tldr.w\tr2, [r7, #132]\t@ 0x84\n-\tmov\tlr, ip\n-\tldr.w\tr5, [r7, #164]\t@ 0xa4\n-\tmov\tip, fp\n-\tadds\tr2, #8\n-\tmov\tfp, r8\n-\trsb\tr9, r5, #0\n-\tmov\tsl, r5\n-\tmov\tr8, r1\n-\tmovs\tr5, #0\n-\tstr.w\tr4, [r7, #472]\t@ 0x1d8\n-\tmov\tr1, r2\n-\tlsls\tr4, r0, #5\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tstr.w\tr4, [r7, #468]\t@ 0x1d4\n-\tmov\tr5, r2\n-\tmov\tr4, r2\n-\tlsls\tr0, r0, #6\n-\tstr.w\tr0, [r7, #460]\t@ 0x1cc\n+\tmov\tr0, r5\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #136]\t@ 0x88\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr3, r0, r5\n+\tstr.w\tr3, [r7, #772]\t@ 0x304\n+\tmov\tr4, r0\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tsubs\tr5, r0, r3\n \tcmp\tr3, #0\n-\tblt.w\te4e0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x7b8>\n-\tudiv\tr0, sl, r3\n-\tldr.w\tr6, [r7, #544]\t@ 0x220\n-\tstr.w\tr0, [r7, #588]\t@ 0x24c\n-\tldr.w\tr0, [r7, #164]\t@ 0xa4\n-\tcmp\tr0, r6\n-\tblt.w\te46c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x744>\n-\tldr.w\tr6, [r7, #152]\t@ 0x98\n-\tcmp\tr6, #0\n-\tble.w\te46c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x744>\n-\tldr.w\tr6, [r7, #544]\t@ 0x220\n-\tvmov.f64\td25, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n-\tstr.w\tfp, [r7, #444]\t@ 0x1bc\n-\tmov\tfp, ip\n-\tadd\tr0, r6\n-\tldr.w\tr6, [r7, #152]\t@ 0x98\n-\tstr.w\tr0, [r7, #580]\t@ 0x244\n-\tadds\tr0, r6, #1\n-\tldr.w\tr6, [r7, #580]\t@ 0x244\n-\tstr.w\tr0, [r7, #496]\t@ 0x1f0\n-\tsub.w\tr0, ip, #8\n-\tstr.w\tr0, [r7, #512]\t@ 0x200\n-\tmov\tip, lr\n-\tldr.w\tr0, [r7, #588]\t@ 0x24c\n-\tstr.w\tr8, [r7, #440]\t@ 0x1b8\n-\tstr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tstrd\tr9, sl, [r7, #432]\t@ 0x1b0\n-\tstrd\tr1, r5, [r7, #420]\t@ 0x1a4\n-\tstrd\tr2, r4, [r7, #412]\t@ 0x19c\n-\tstr.w\tr6, [r7, #588]\t@ 0x24c\n+\tblt.w\tf850 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1098>\n+\tmov\tr1, r3\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tsl, r0\n+\tblt.w\tf1da <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa22>\n+\tadd.w\tr4, r4, r4, lsl #2\n+\tlsls\tr3, r6, #1\n+\tnegs\tr2, r4\n+\tstr.w\tr2, [r7, #624]\t@ 0x270\n+\tldr\tr2, [r7, #116]\t@ 0x74\n+\tcmp\tr2, #1\n+\tmov.w\tr2, #24\n+\tmul.w\tr3, r2, r3\n+\tbne.w\tf25c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xaa4>\n+\tstr.w\tr3, [r7, #592]\t@ 0x250\n+\tmov\tr5, r4\n+\tldr\tr3, [r7, #120]\t@ 0x78\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr2, [r7, #168]\t@ 0xa8\n+\tadd.w\tr9, r3, #8\n+\tstr.w\tfp, [r7, #712]\t@ 0x2c8\n+\tstr.w\tsl, [r7, #648]\t@ 0x288\n+\tmov\tfp, r9\n+\tmov\tsl, r9\n+\tmov\tr4, r9\n+\tnegs\tr3, r2\n+\tstr.w\tr2, [r7, #640]\t@ 0x280\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tmovs\tr2, #0\n+\tlsls\tr3, r6, #4\n+\tstr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr3, [r7, #608]\t@ 0x260\n+\tlsls\tr3, r6, #5\n+\tstr.w\tr3, [r7, #604]\t@ 0x25c\n+\tlsls\tr3, r6, #6\n+\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tcmp\tr5, #0\n+\tblt.w\tefaa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x7f2>\n+\tldr.w\tr0, [r7, #640]\t@ 0x280\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tcmp\tr3, r2\n+\tblt.w\teefa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x742>\n+\tb.n\tec90 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4d8>\n+\tnop.w\n+\t.word\t0x13445503\n+\t.word\t0xbfee6f0e\n+\t.word\t0x9b97f4a4\n+\t.word\t0xbfe1e377\n+\t.word\t0x9b97f4a4\n+\t.word\t0x3fe1e377\n+\t.word\t0x04755a5d\n+\t.word\t0xbfe2cf23\n+\t.word\t0x13445503\n+\t.word\t0x3fee6f0e\n+\t.word\t0x04755a5d\n+\t.word\t0x3fe2cf23\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tcmp\tr3, #0\n+\tble.w\teefa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x742>\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tadd.w\tlr, r3, #1\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tstr.w\tfp, [r7, #560]\t@ 0x230\n+\tadds\tr6, r2, r1\n+\tldr.w\tfp, [r7, #128]\t@ 0x80\n+\tstr.w\tr5, [r7, #656]\t@ 0x290\n+\tmov\tr5, r0\n+\tmov\tr0, r6\n+\tstr.w\tsl, [r7, #568]\t@ 0x238\n+\tstrd\tr4, r9, [r7, #548]\t@ 0x224\n+\tstr.w\tlr, [r7, #652]\t@ 0x28c\n+\tldr.w\tlr, [r7, #780]\t@ 0x30c\n+\tmov\tip, r0\n+\tmov\tr6, r0\n \tmovs\tr3, #1\n-\tstr.w\tr6, [r7, #528]\t@ 0x210\n-\tldr.w\tr6, [r7, #596]\t@ 0x254\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tstr.w\tr0, [r7, #536]\t@ 0x218\n-\tldrd\tr3, r2, [r7, #584]\t@ 0x248\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n-\tadds\tr5, r3, r2\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n-\tcmp\tr3, r5\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tstr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tadd.w\tr4, r3, ip\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n+\tcmp\tr3, r4\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tit\tgt\n-\taddgt\tr5, r5, r6\n-\tldr.w\tr4, [r7, #568]\t@ 0x238\n-\tadds\tr2, r3, r5\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\taddgt\tr4, lr\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n+\tadds\tr2, r3, r4\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tcmp\tr3, r2\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tit\tgt\n-\taddgt\tr2, r2, r6\n+\taddgt\tr2, lr\n \tadd\tr3, r2\n \tcmp\tr1, r3\n-\tldr.w\tr1, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n \tit\tgt\n-\taddgt\tr3, r3, r6\n+\taddgt\tr3, lr\n \tadd\tr1, r3\n \tcmp\tr0, r1\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n+\tldr.w\tr0, [r7, #704]\t@ 0x2c0\n \tit\tgt\n-\taddgt\tr1, r1, r6\n+\taddgt\tr1, lr\n \tcmp\tr0, #0\n-\tbne.w\te4fc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x7d4>\n-\tcmp\tr4, #0\n-\tble.w\te410 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6e8>\n-\tadd.w\tlr, r4, r5\n-\tldr.w\tr4, [r7, #512]\t@ 0x200\n-\tadd.w\tr0, r5, #536870912\t@ 0x20000000\n+\tbne.w\tefc6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x80e>\n+\tcmp\tr5, #0\n+\tble.w\teeb4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6fc>\n+\tadd\tr5, r4\n+\tmov.w\tr8, r4, lsl #3\n+\tadd.w\tr0, r4, #536870912\t@ 0x20000000\n+\tldr.w\tr4, [r7, #156]\t@ 0x9c\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tlsls\tr5, r5, #3\n \tsubs\tr1, #1\n \tsubs\tr2, #1\n \tsubs\tr3, #1\n \tsubs\tr0, #1\n-\tadd.w\tr4, r4, lr, lsl #3\n-\tstr.w\tr4, [r7, #520]\t@ 0x208\n-\tnegs\tr4, r5\n-\tstr.w\tr4, [r7, #560]\t@ 0x230\n+\tadd.w\tr4, r4, r5, lsl #3\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n \tlsls\tr1, r1, #3\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n \tlsls\tr2, r2, #3\n \tlsls\tr3, r3, #3\n \tlsls\tr0, r0, #3\n-\tadd.w\tr5, fp, r0\n-\tadd.w\tsl, fp, r1\n-\tadd.w\tr9, fp, r2\n-\tadd.w\tr8, fp, r3\n-\tadd\tr0, ip\n-\tadd\tr1, ip\n-\tadd\tr2, ip\n-\tadd\tr3, ip\n-\tlsls\tr4, r4, #3\n-\tstr.w\tr4, [r7, #552]\t@ 0x228\n-\tvldmia\tr5!, {d23}\n-\tvldr\td17, [sl]\n-\tvldr\td20, [r8]\n-\tvldr\td16, [r9]\n-\tvadd.f64\td22, d17, d23\n-\tvldmia\tr0!, {d21}\n-\tvldr\td18, [r1]\n-\tvsub.f64\td23, d23, d17\n-\tvadd.f64\td19, d20, d16\n-\tvldr\td24, [r3]\n-\tvldr\td17, [r2]\n-\tvsub.f64\td16, d16, d20\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tvadd.f64\td20, d18, d21\n-\tvsub.f64\td21, d21, d18\n-\tvadd.f64\td28, d19, d22\n-\tvsub.f64\td22, d22, d19\n-\tvadd.f64\td19, d24, d17\n-\tvsub.f64\td17, d17, d24\n-\tvmul.f64\td18, d9, d16\n-\tadd.w\tlr, r5, r4\n-\tldr.w\tr4, [r7, #552]\t@ 0x228\n-\tvmul.f64\td16, d8, d16\n-\tvfma.f64\td16, d9, d23\n-\tadd\tlr, r4\n-\tvadd.f64\td27, d19, d20\n-\tvsub.f64\td20, d20, d19\n-\tvmul.f64\td19, d9, d17\n-\tvmov.f64\td24, d18\n-\tvfma.f64\td18, d12, d23\n-\tvfnms.f64\td24, d8, d23\n-\tvldr\td23, [lr, #-8]\n-\tvmul.f64\td17, d8, d17\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tvmov.f64\td26, d19\n-\tvfma.f64\td17, d9, d21\n-\tvfnms.f64\td26, d8, d21\n-\tvfma.f64\td19, d12, d21\n-\tvmov.f64\td21, d23\n-\tvfms.f64\td21, d28, d25\n-\tvadd.f64\td23, d23, d28\n-\tvstr\td23, [lr, #-8]\n-\tadd.w\tlr, r0, r4\n-\tldr.w\tr4, [r7, #552]\t@ 0x228\n-\tadd\tlr, r4\n-\tldr.w\tr4, [r7, #520]\t@ 0x208\n-\tvmov.f64\td23, d21\n-\tvfma.f64\td21, d11, d22\n-\tvfma.f64\td23, d10, d22\n-\tcmp\tr5, r4\n-\tvadd.f64\td19, d19, d21\n-\tvadd.f64\td26, d26, d21\n-\tvsub.f64\td22, d23, d17\n-\tvadd.f64\td23, d17, d23\n-\tvstr\td22, [r5, #-8]\n-\tvstmia\tsl!, {d23}\n-\tvstmia\tr9!, {d19}\n-\tvldr\td19, [lr, #-8]\n-\tvstmia\tr8!, {d26}\n-\tvmov.f64\td17, d19\n-\tvadd.f64\td19, d19, d27\n-\tvfms.f64\td17, d27, d25\n-\tvstr\td19, [lr, #-8]\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td17, d11, d20\n-\tvfma.f64\td19, d10, d20\n-\tvadd.f64\td24, d17, d24\n-\tvadd.f64\td18, d18, d17\n-\tvadd.f64\td20, d19, d16\n-\tvsub.f64\td19, d19, d16\n-\tvstr\td20, [r0, #-8]\n-\tvstmia\tr1!, {d19}\n-\tvstmia\tr2!, {d24}\n-\tvstmia\tr3!, {d18}\n-\tbne.w\te2be <__gridxc_gpfa_core_dp_MOD_gpfa_+0x596>\n-\tb.n\te410 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6e8>\n-\tnop\n-\t.word\t0x04755a5d\n-\t.word\t0xbfe2cf23\n-\t.word\t0x13445503\n-\t.word\t0xbfee6f0e\n-\t.word\t0x04755a5d\n-\t.word\t0x3fe2cf23\n-\t.word\t0x13445503\n-\t.word\t0x3fee6f0e\n-\t.word\t0x9b97f4a4\n-\t.word\t0x3fe1e377\n-\tldr.w\tr3, [r7, #364]\t@ 0x16c\n-\tldr.w\tr2, [r7, #588]\t@ 0x24c\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tstr.w\tr2, [r7, #588]\t@ 0x24c\n-\tcmp\tr3, r2\n-\tble.n\te42e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x706>\n-\tmov\tr3, r2\n-\tadd\tr3, r6\n-\tstr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tadd.w\tsl, r5, r1\n+\tadd.w\tr9, r5, r2\n+\tstr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tadd\tr1, fp\n+\trsb\tr4, r8, #0\n+\tadd\tr2, fp\n+\tadd.w\tr8, r5, r3\n+\tstr.w\tr4, [r7, #720]\t@ 0x2d0\n+\tadd\tr3, fp\n+\tadds\tr4, r5, r0\n+\tadd\tr0, fp\n+\tmov.w\tr5, ip, lsl #3\n+\tstr.w\tfp, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tstr.w\tr6, [r7, #672]\t@ 0x2a0\n+\tvldmia\tr4!, {d1}\n+\tvldr\td7, [sl]\n+\tvldr\td2, [r9]\n+\tldr.w\tr5, [r7, #720]\t@ 0x2d0\n+\tvadd.f64\td3, d7, d1\n+\tvsub.f64\td1, d1, d7\n+\tvldr\td7, [r8]\n+\tadd.w\tfp, r4, r5\n+\tvldmia\tr0!, {d5}\n+\tvldr\td6, [r1]\n+\tvldr\td10, [r2]\n+\tvmul.f64\td9, d15, d1\n+\tvldr\td13, [r3]\n+\tvmul.f64\td11, d8, d1\n+\tldr.w\tr6, [r7, #716]\t@ 0x2cc\n+\tvadd.f64\td1, d7, d2\n+\tvadd.f64\td4, d6, d5\n+\tvsub.f64\td7, d2, d7\n+\tadd\tfp, r6\n+\tvadd.f64\td0, d13, d10\n+\tvsub.f64\td5, d5, d6\n+\tvsub.f64\td6, d10, d13\n+\tvadd.f64\td2, d1, d3\n+\tvsub.f64\td3, d3, d1\n+\tvldr\td10, [fp, #-8]\n+\tadds\tr5, r0, r5\n+\tvadd.f64\td1, d0, d4\n+\tvsub.f64\td4, d4, d0\n+\tvldr\td0, [fp, #-8]\n+\tadd\tr5, r6\n+\tvmls.f64\td0, d2, d12\n+\tvadd.f64\td2, d10, d2\n+\tvmla.f64\td11, d15, d7\n+\tvmul.f64\td3, d3, d14\n+\tvldr\td10, [r5, #-8]\n+\tvmul.f64\td4, d4, d14\n+\tvmul.f64\td7, d8, d7\n+\tvstr\td2, [fp, #-8]\n+\tvldr\td2, [r5, #-8]\n+\tvmls.f64\td2, d1, d12\n+\tvadd.f64\td1, d10, d1\n+\tvmul.f64\td10, d8, d5\n+\tvmul.f64\td5, d15, d5\n+\tvmla.f64\td10, d15, d6\n+\tvmul.f64\td6, d8, d6\n+\tvstr\td1, [r5, #-8]\n+\tvadd.f64\td1, d0, d3\n+\tvsub.f64\td3, d0, d3\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n+\tcmp\tr4, r5\n+\tvadd.f64\td0, d2, d4\n+\tvsub.f64\td2, d2, d4\n+\tvsub.f64\td4, d9, d7\n+\tvsub.f64\td7, d7, d9\n+\tvadd.f64\td4, d4, d2\n+\tvadd.f64\td2, d7, d2\n+\tvsub.f64\td7, d6, d5\n+\tvsub.f64\td6, d5, d6\n+\tvsub.f64\td5, d1, d10\n+\tvadd.f64\td10, d10, d1\n+\tvadd.f64\td7, d7, d3\n+\tvadd.f64\td6, d6, d3\n+\tvstr\td5, [r4, #-8]\n+\tvstmia\tsl!, {d10}\n+\tvstmia\tr9!, {d7}\n+\tvadd.f64\td7, d0, d11\n+\tvsub.f64\td0, d0, d11\n+\tvstmia\tr8!, {d6}\n+\tvstr\td7, [r0, #-8]\n+\tvstmia\tr1!, {d0}\n+\tvstmia\tr2!, {d4}\n+\tvstmia\tr3!, {d2}\n+\tbne.w\ted90 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x5d8>\n+\tldr.w\tfp, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr6, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tldr.w\tr2, [r7, #652]\t@ 0x28c\n+\tadd\tip, r3\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tcmp\tr3, ip\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tit\tgt\n+\taddgt\tip, lr\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, r2\n-\tbne.w\te210 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4e8>\n-\tldr.w\tr0, [r7, #536]\t@ 0x218\n-\tldr.w\tr6, [r7, #528]\t@ 0x210\n-\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n-\tsubs\tr0, #1\n-\tadds\tr1, r0, #1\n-\tadd\tr6, r3\n-\tbne.w\te1fa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4d2>\n-\tmov\tlr, ip\n-\tmov\tip, fp\n-\tldrd\tr9, sl, [r7, #432]\t@ 0x1b0\n-\tldrd\tr8, fp, [r7, #440]\t@ 0x1b8\n-\tldrd\tr1, r5, [r7, #420]\t@ 0x1a4\n-\tldrd\tr2, r4, [r7, #412]\t@ 0x19c\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tsub.w\tsl, sl, fp\n-\tadd\tr9, fp\n-\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n-\tadd\tr0, fp\n-\tstr.w\tr0, [r7, #544]\t@ 0x220\n-\tldr.w\tr0, [r7, #472]\t@ 0x1d8\n-\tadd\tr5, r0\n-\tldr.w\tr0, [r7, #468]\t@ 0x1d4\n-\tadd\tr1, r0\n-\tldr.w\tr0, [r7, #464]\t@ 0x1d0\n-\tadd\tr4, r0\n-\tldr.w\tr0, [r7, #460]\t@ 0x1cc\n-\tadd\tr2, r0\n-\tbeq.w\te6d6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9ae>\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tcmp\tr0, #0\n-\tble.w\te18c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x464>\n-\tvldr\td4, [r5]\n+\tbne.w\tecd6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x51e>\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tmov\tr0, r6\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tsubs\tr5, #1\n+\tadd\tr0, r3\n+\tadds\tr4, r5, #1\n+\tbne.w\tecc4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x50c>\n+\tldr.w\tsl, [r7, #568]\t@ 0x238\n+\tmov\tr5, r3\n+\tldr.w\tfp, [r7, #560]\t@ 0x230\n+\tldrd\tr4, r9, [r7, #548]\t@ 0x224\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tsubs\tr2, r3, #1\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tstr.w\tr2, [r7, #648]\t@ 0x288\n+\tadds\tr2, #1\n+\tadd\tr1, r3\n+\tstr.w\tr1, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tsub.w\tr1, r1, r3\n+\tstr.w\tr1, [r7, #640]\t@ 0x280\n+\tldr.w\tr1, [r7, #632]\t@ 0x278\n+\tadd\tr1, r3\n+\tldr.w\tr3, [r7, #608]\t@ 0x260\n+\tstr.w\tr1, [r7, #632]\t@ 0x278\n+\tadd\tsl, r3\n+\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tadd\tfp, r3\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tadd\tr4, r3\n+\tbeq.w\tf1d6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa1e>\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tcmp\tr3, #0\n-\tvldr\td15, [r1]\n-\tvldr\td14, [r4]\n-\tvldr\td13, [r2]\n-\tvmul.f64\td4, d7, d4\n-\tvmul.f64\td15, d7, d15\n-\tvldr\td2, [r5, #-8]\n-\tvmul.f64\td14, d7, d14\n-\tvldr\td1, [r1, #-8]\n-\tvmul.f64\td13, d7, d13\n-\tvldr\td0, [r4, #-8]\n-\tvldr\td3, [r2, #-8]\n-\tbge.w\te192 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x46a>\n-\tldr.w\tr0, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr6, [r7, #164]\t@ 0xa4\n-\tudiv\tr0, r9, r0\n-\tstr.w\tr0, [r7, #588]\t@ 0x24c\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tcmp\tr6, r0\n-\tble.w\te1a8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x480>\n-\tb.n\te46c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x744>\n-\tcmp\tr4, #0\n-\tble.n\te410 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6e8>\n-\tadd.w\tlr, r4, r5\n-\tldr.w\tr4, [r7, #512]\t@ 0x200\n-\tadd.w\tr0, r5, #536870912\t@ 0x20000000\n+\tble.w\tec3c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x484>\n+\tvldr\td3, [sl, #-8]\n+\tcmp\tr5, #0\n+\tvldr\td7, [fp]\n+\tvldr\td4, [r4]\n+\tvstr\td3, [r7, #760]\t@ 0x2f8\n+\tvldr\td3, [fp, #-8]\n+\tvldr\td6, [sl]\n+\tvldr\td5, [r9]\n+\tvstr\td3, [r7, #752]\t@ 0x2f0\n+\tvldr\td3, [r7, #104]\t@ 0x68\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td6, d3, d6\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td6, [r7, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d3, d5\n+\tvstr\td7, [r7, #424]\t@ 0x1a8\n+\tvldr\td7, [r9, #-8]\n+\tvstr\td6, [r7, #432]\t@ 0x1b0\n+\tvstr\td7, [r7, #736]\t@ 0x2e0\n+\tvldr\td7, [r4, #-8]\n+\tvstr\td7, [r7, #456]\t@ 0x1c8\n+\tbge.w\tec42 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x48a>\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n+\tldr.w\tr0, [r7, #632]\t@ 0x278\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tcmp\tr3, r2\n+\tble.w\tec90 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x4d8>\n+\tb.n\teefa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x742>\n+\tcmp\tr5, #0\n+\tble.w\teeb4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6fc>\n+\tadd\tr5, r4\n+\tmov.w\tr8, r4, lsl #3\n+\tadd.w\tr0, r4, #536870912\t@ 0x20000000\n+\tldr.w\tr4, [r7, #156]\t@ 0x9c\n \tadd.w\tr1, r1, #536870912\t@ 0x20000000\n \tadd.w\tr2, r2, #536870912\t@ 0x20000000\n \tadd.w\tr3, r3, #536870912\t@ 0x20000000\n-\tlsls\tr5, r5, #3\n \tsubs\tr1, #1\n \tsubs\tr2, #1\n \tsubs\tr3, #1\n \tsubs\tr0, #1\n-\tadd.w\tr4, r4, lr, lsl #3\n-\tstr.w\tr4, [r7, #520]\t@ 0x208\n-\tnegs\tr4, r5\n-\tstr.w\tr4, [r7, #560]\t@ 0x230\n+\tadd.w\tr4, r4, r5, lsl #3\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n \tlsls\tr1, r1, #3\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n \tlsls\tr2, r2, #3\n \tlsls\tr3, r3, #3\n \tlsls\tr0, r0, #3\n-\tadd.w\tr5, fp, r0\n-\tadd.w\tsl, fp, r1\n-\tadd.w\tr9, fp, r2\n-\tadd.w\tr8, fp, r3\n-\tadd\tr0, ip\n-\tadd\tr1, ip\n-\tadd\tr2, ip\n-\tadd\tr3, ip\n-\tlsls\tr4, r4, #3\n-\tstr.w\tr4, [r7, #552]\t@ 0x228\n-\tvldr\td22, [r9]\n-\tvldr\td24, [r8]\n-\tvldmia\tr5!, {d23}\n-\tvldr\td18, [r3]\n-\tvsub.f64\td20, d22, d24\n-\tvldr\td19, [sl]\n-\tvldr\td17, [r2]\n-\tvadd.f64\td24, d24, d22\n-\tvldmia\tr0!, {d16}\n-\tvldr\td27, [r1]\n-\tvsub.f64\td21, d23, d19\n-\tvmul.f64\td26, d9, d20\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tvadd.f64\td19, d19, d23\n-\tvadd.f64\td23, d18, d17\n-\tvsub.f64\td17, d17, d18\n-\tadd.w\tlr, r0, r4\n-\tldr.w\tr4, [r7, #552]\t@ 0x228\n-\tvadd.f64\td22, d27, d16\n-\tvmov.f64\td18, d26\n-\tvmul.f64\td20, d8, d20\n-\tadd\tlr, r4\n-\tvfma.f64\td20, d9, d21\n-\tvfnms.f64\td18, d8, d21\n-\tvfma.f64\td26, d12, d21\n-\tvmul.f64\td21, d9, d17\n-\tvsub.f64\td16, d16, d27\n-\tvadd.f64\td28, d24, d19\n-\tvsub.f64\td19, d19, d24\n-\tvadd.f64\td24, d23, d22\n-\tvmul.f64\td17, d8, d17\n-\tldr.w\tr4, [r7, #560]\t@ 0x230\n-\tvsub.f64\td22, d22, d23\n-\tvldr\td23, [lr, #-8]\n-\tvmov.f64\td29, d21\n-\tvfma.f64\td17, d9, d16\n-\tvfnms.f64\td29, d8, d16\n-\tvfma.f64\td21, d12, d16\n-\tvmov.f64\td16, d23\n-\tvmov.f64\td27, d18\n-\tvfms.f64\td16, d24, d25\n-\tvfma.f64\td27, d24, d25\n-\tvadd.f64\td24, d23, d24\n-\tvfma.f64\td27, d10, d22\n-\tvstr\td24, [lr, #-8]\n-\tadd.w\tlr, r5, r4\n-\tldr.w\tr4, [r7, #552]\t@ 0x228\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td16, d11, d22\n-\tvfma.f64\td24, d10, d22\n-\tadd\tlr, r4\n-\tldr.w\tr4, [r7, #520]\t@ 0x208\n-\tvsub.f64\td27, d27, d23\n-\tcmp\tr5, r4\n-\tvadd.f64\td18, d16, d18\n-\tvadd.f64\td16, d26, d16\n-\tvadd.f64\td22, d24, d20\n-\tvsub.f64\td30, d20, d24\n-\tvsub.f64\td24, d24, d20\n-\tvmul.f64\td27, d27, d14\n-\tvnmul.f64\td23, d15, d18\n-\tvmul.f64\td18, d18, d1\n-\tvnmul.f64\td20, d4, d22\n-\tvmul.f64\td26, d22, d2\n-\tvmul.f64\td31, d24, d3\n-\tvldr\td24, [lr, #-8]\n-\tvmul.f64\td22, d16, d0\n-\tvmul.f64\td30, d30, d13\n-\tvmov.f64\td16, d24\n-\tvadd.f64\td24, d24, d28\n-\tvfms.f64\td16, d28, d25\n-\tvstr\td24, [lr, #-8]\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td16, d11, d19\n-\tvfma.f64\td24, d10, d19\n-\tvadd.f64\td21, d21, d16\n-\tvadd.f64\td16, d29, d16\n-\tvfma.f64\td27, d16, d0\n-\tvfma.f64\td22, d16, d14\n-\tvsub.f64\td16, d24, d17\n-\tvadd.f64\td24, d17, d24\n-\tvfma.f64\td23, d21, d1\n-\tvfma.f64\td18, d21, d15\n-\tvfma.f64\td20, d16, d2\n-\tvfma.f64\td26, d16, d4\n-\tvfma.f64\td30, d24, d3\n-\tvfma.f64\td31, d24, d13\n-\tvstr\td20, [r5, #-8]\n-\tvstr\td26, [r0, #-8]\n-\tvstmia\tsl!, {d30}\n-\tvstmia\tr1!, {d31}\n-\tvstmia\tr9!, {d23}\n-\tvstmia\tr2!, {d18}\n-\tvstmia\tr8!, {d27}\n-\tvstmia\tr3!, {d22}\n-\tbne.w\te55a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x832>\n-\tb.n\te410 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6e8>\n-\tmov\tr8, fp\n-\tmov\tfp, ip\n-\tmov\tip, lr\n-\tldr.w\tr3, [r7, #576]\t@ 0x240\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r7, #576]\t@ 0x240\n-\tcmp\tr3, r2\n-\tbne.w\te100 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3d8>\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tmov\tr4, fp\n-\tldr.w\tr8, [r7, #456]\t@ 0x1c8\n-\tmov\tlr, ip\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tcmp\tr2, #5\n-\tbne.w\tee7c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1154>\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n+\tadd.w\tsl, r5, r1\n+\tadd.w\tr9, r5, r2\n+\tstr.w\tr4, [r7, #672]\t@ 0x2a0\n+\tadd\tr1, fp\n+\trsb\tr4, r8, #0\n+\tadd\tr2, fp\n+\tadd.w\tr8, r5, r3\n+\tstr.w\tr4, [r7, #720]\t@ 0x2d0\n+\tadd\tr3, fp\n+\tadds\tr4, r5, r0\n+\tadd\tr0, fp\n+\tmov.w\tr5, ip, lsl #3\n+\tstrd\tr6, fp, [r7, #664]\t@ 0x298\n+\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tvldmia\tr4!, {d7}\n+\tldr.w\tr5, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr6, [r7, #716]\t@ 0x2cc\n+\tvldmia\tr0!, {d0}\n+\tadds\tr5, r4, r5\n+\tvldr\td6, [sl]\n+\tadd\tr5, r6\n+\tvldr\td2, [r2]\n+\tvldr\td10, [r3]\n+\tvldr\td11, [r9]\n+\tvadd.f64\td4, d6, d7\n+\tvldr\td5, [r8]\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td9, [r1]\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tvadd.f64\td6, d9, d0\n+\tadd.w\tfp, r0, r6\n+\tvsub.f64\td9, d0, d9\n+\tldr.w\tr6, [r7, #716]\t@ 0x2cc\n+\tvadd.f64\td0, d10, d2\n+\tvsub.f64\td10, d2, d10\n+\tvadd.f64\td2, d5, d11\n+\tadd\tfp, r6\n+\tvsub.f64\td5, d11, d5\n+\tvmul.f64\td1, d15, d7\n+\tvmul.f64\td7, d8, d7\n+\tvldr\td11, [r5, #-8]\n+\tvadd.f64\td3, d0, d6\n+\tvsub.f64\td6, d6, d0\n+\tvadd.f64\td0, d2, d4\n+\tvsub.f64\td4, d4, d2\n+\tvldr\td2, [fp, #-8]\n+\tvmla.f64\td7, d15, d5\n+\tvmul.f64\td5, d8, d5\n+\tvmul.f64\td6, d6, d14\n+\tvmul.f64\td13, d4, d14\n+\tvmul.f64\td4, d3, d12\n+\tvadd.f64\td3, d2, d3\n+\tvmls.f64\td11, d0, d12\n+\tvstr\td3, [fp, #-8]\n+\tvldr\td3, [r5, #-8]\n+\tvadd.f64\td0, d3, d0\n+\tvsub.f64\td3, d1, d5\n+\tvstr\td0, [r5, #-8]\n+\tvsub.f64\td0, d5, d1\n+\tvsub.f64\td5, d2, d4\n+\tvadd.f64\td4, d4, d3\n+\tvmul.f64\td1, d8, d9\n+\tvmul.f64\td9, d15, d9\n+\tvmla.f64\td1, d15, d10\n+\tvmul.f64\td10, d8, d10\n+\tvadd.f64\td4, d4, d6\n+\tvsub.f64\td4, d4, d2\n+\tvadd.f64\td2, d5, d6\n+\tvsub.f64\td5, d5, d6\n+\tvadd.f64\td6, d11, d13\n+\tvsub.f64\td11, d11, d13\n+\tvstr\td4, [r7, #696]\t@ 0x2b8\n+\tvadd.f64\td3, d5, d3\n+\tvadd.f64\td5, d0, d5\n+\tvsub.f64\td4, d6, d1\n+\tvadd.f64\td0, d2, d7\n+\tvadd.f64\td1, d1, d6\n+\tvsub.f64\td6, d7, d2\n+\tvsub.f64\td2, d2, d7\n+\tvstr\td5, [r7, #688]\t@ 0x2b0\n+\tvsub.f64\td5, d10, d9\n+\tvsub.f64\td10, d9, d10\n+\tvadd.f64\td5, d5, d11\n+\tvadd.f64\td9, d10, d11\n+\tvldr\td10, [r7, #440]\t@ 0x1b8\n+\tvldr\td11, [r7, #752]\t@ 0x2f0\n+\tvmul.f64\td7, d3, d10\n+\tvmul.f64\td10, d5, d10\n+\tvmla.f64\td10, d3, d11\n+\tvldr\td3, [r7, #448]\t@ 0x1c0\n+\tvnmls.f64\td7, d5, d11\n+\tvmul.f64\td5, d0, d3\n+\tvldr\td11, [r7, #760]\t@ 0x2f8\n+\tvnmls.f64\td5, d4, d11\n+\tvmul.f64\td4, d4, d3\n+\tvmla.f64\td4, d0, d11\n+\tvldr\td3, [r7, #424]\t@ 0x1a8\n+\tvstr\td5, [r4, #-8]\n+\tvstr\td4, [r0, #-8]\n+\tvldr\td4, [r7, #456]\t@ 0x1c8\n+\tvmul.f64\td5, d1, d4\n+\tvmul.f64\td1, d1, d3\n+\tvmla.f64\td5, d6, d3\n+\tvmla.f64\td1, d2, d4\n+\tvldr\td6, [r7, #736]\t@ 0x2e0\n+\tvstmia\tsl!, {d5}\n+\tvstmia\tr1!, {d1}\n+\tvstmia\tr9!, {d7}\n+\tvmul.f64\td7, d9, d6\n+\tvstmia\tr2!, {d10}\n+\tvldr\td4, [r7, #696]\t@ 0x2b8\n+\tvldr\td5, [r7, #432]\t@ 0x1b0\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tvmla.f64\td7, d4, d5\n+\tvmul.f64\td9, d9, d5\n+\tvldr\td5, [r7, #688]\t@ 0x2b0\n+\tcmp\tr4, r5\n+\tvmla.f64\td9, d5, d6\n+\tvstmia\tr8!, {d7}\n+\tvstmia\tr3!, {d9}\n+\tbne.w\tf02c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x874>\n+\tldrd\tr6, fp, [r7, #664]\t@ 0x298\n+\tb.n\teeb4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x6fc>\n+\tldr.w\tfp, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr3, [r7, #616]\t@ 0x268\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tadds\tr3, #1\n-\tldr.w\tr1, [r7, #128]\t@ 0x80\n-\tldr.w\tr0, [r7, #568]\t@ 0x238\n-\tmla\tr2, r0, r1, r2\n-\tstr.w\tr2, [r7, #592]\t@ 0x250\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tstr.w\tr3, [r7, #616]\t@ 0x268\n \tcmp\tr3, r2\n-\tbne.w\te0c0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x398>\n-\tldr\tr4, [r7, #44]\t@ 0x2c\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tbne.w\teb9e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3e6>\n+\tldr\tr3, [r7, #24]\n+\tmov\tr6, fp\n+\tldr.w\tr8, [r7, #576]\t@ 0x240\n+\tldr.w\tsl, [r7, #600]\t@ 0x258\n+\tcmp\tr3, #5\n+\tbne.w\tf974 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11bc>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tsl, sl, #1\n+\tldr\tr2, [r7, #116]\t@ 0x74\n+\tldr.w\tr1, [r7, #768]\t@ 0x300\n+\tmla\tr3, r1, r2, r3\n+\tstr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr\tr3, [r7, #20]\n+\tcmp\tsl, r3\n+\tbne.w\teb52 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x39a>\n+\tldr\tr4, [r7, #28]\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tcmp\tr3, #1\n-\tbne.w\t10a1a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2cf2>\n+\tbne.w\t11824 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x306c>\n \tcmp\tr4, #1\n-\tbne.w\t10948 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2c20>\n-\tldr.w\tsp, [r7, #96]\t@ 0x60\n-\tldr.w\tr2, [pc, #1832]\t@ ee60 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1138>\n-\tldr.w\tr3, [pc, #1832]\t@ ee64 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x113c>\n+\tbne.w\t11772 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fba>\n+\tldr.w\tsp, [r7, #64]\t@ 0x40\n+\tldr.w\tr2, [pc, #1828]\t@ f958 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11a0>\n+\tldr.w\tr3, [pc, #1828]\t@ f95c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11a4>\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #988]\t@ 0x3dc\n+\tldr.w\tr3, [r7, #1172]\t@ 0x494\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t10fb6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x328e>\n-\tadd.w\tr7, r7, #996\t@ 0x3e4\n+\tbne.w\t11cd0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3518>\n+\taddw\tr7, r7, #1180\t@ 0x49c\n \tmov\tsp, r7\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr.w\tr6, [r7, #164]\t@ 0xa4\n-\tlsls\tr4, r0, #4\n-\tstr.w\tr2, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr2, [r7, #132]\t@ 0x84\n-\trsb\tr9, r6, #0\n-\tmov\tsl, r6\n-\tldr.w\tlr, [r7, #76]\t@ 0x4c\n-\tadds\tr2, #8\n-\tmovs\tr6, #0\n-\tstr.w\tr6, [r7, #544]\t@ 0x220\n-\tldr.w\tr6, [r7, #568]\t@ 0x238\n-\tstr.w\tr4, [r7, #496]\t@ 0x1f0\n-\tlsls\tr4, r0, #5\n-\tstr.w\tip, [r7, #588]\t@ 0x24c\n-\tlsls\tr0, r0, #6\n-\tstr.w\tr4, [r7, #472]\t@ 0x1d8\n-\tmov\tip, fp\n-\tstr.w\tr0, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr3, [r7, #604]\t@ 0x25c\n+\tmov\tr5, fp\n+\tldr\tr3, [r7, #120]\t@ 0x78\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tldr.w\tfp, [r7, #128]\t@ 0x80\n+\tadd.w\tr2, r3, #8\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tmov\tr8, r2\n+\tnegs\tr1, r3\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tmov\tr9, r2\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tstr.w\tr1, [r7, #664]\t@ 0x298\n+\tlsls\tr1, r6, #4\n+\tadds\tr3, #1\n+\tstr.w\tr1, [r7, #648]\t@ 0x288\n+\tstr.w\tr3, [r7, #652]\t@ 0x28c\n+\tlsls\tr1, r6, #5\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstr.w\tr1, [r7, #608]\t@ 0x260\n+\tlsls\tr1, r6, #6\n+\tldr\tr6, [r7, #92]\t@ 0x5c\n+\tadds\tr3, #1\n+\tstr.w\tr4, [r7, #640]\t@ 0x280\n \tmov\tr4, r2\n-\tmov\tr0, r1\n+\tstr.w\tr1, [r7, #592]\t@ 0x250\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr2, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tcmp\tr3, #0\n+\tblt.w\tf614 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xe5c>\n \tmov\tr1, r3\n-\tmov\tr3, r2\n-\tadds\tr6, #1\n-\tstr.w\tr2, [r7, #512]\t@ 0x200\n-\tstr.w\tr6, [r7, #552]\t@ 0x228\n-\tcmp\tr1, #0\n-\tblt.w\teabe <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd96>\n-\tldr.w\tr5, [r7, #164]\t@ 0xa4\n-\tudiv\tfp, sl, r1\n-\tldr.w\tr6, [r7, #544]\t@ 0x220\n-\tcmp\tr5, r6\n-\tblt.w\tea46 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd1e>\n-\tldr.w\tr5, [r7, #152]\t@ 0x98\n-\tcmp\tr5, #0\n-\tble.w\tea46 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd1e>\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tvmov.f64\td22, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr6, [r7, #592]\t@ 0x250\n-\tstr.w\tr0, [r7, #460]\t@ 0x1cc\n-\tadd\tr6, r5\n-\tldr.w\tr5, [r7, #152]\t@ 0x98\n-\tstr.w\tr6, [r7, #520]\t@ 0x208\n-\tmov\tr6, fp\n-\tadds\tr5, #1\n-\tstr.w\tr5, [r7, #504]\t@ 0x1f8\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n-\tmov\tfp, ip\n-\tstrd\tr3, r2, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tstr.w\tr3, [r7, #588]\t@ 0x24c\n-\tmovs\tr3, #1\n-\tstrd\tr8, r6, [r7, #432]\t@ 0x1b0\n-\tstr.w\tr3, [r7, #528]\t@ 0x210\n-\tstrd\tr9, r1, [r7, #420]\t@ 0x1a4\n-\tstrd\tr4, sl, [r7, #412]\t@ 0x19c\n-\tldrd\tr3, r2, [r7, #584]\t@ 0x248\n+\tldr.w\tr0, [r7, #656]\t@ 0x290\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #168]\t@ 0xa8\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tmov\tr3, r0\n+\tcmp\tr2, r1\n+\tblt.w\tf558 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xda0>\n+\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tcmp\tr2, #0\n+\tble.w\tf558 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xda0>\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tstr.w\tsl, [r7, #584]\t@ 0x248\n+\tmov\tsl, r5\n+\tadd\tr2, r1\n+\tmovs\tr1, #1\n+\tstr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tstr.w\tr1, [r7, #668]\t@ 0x29c\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tstr.w\tr4, [r7, #560]\t@ 0x230\n+\tstrd\tr8, r9, [r7, #548]\t@ 0x224\n+\tstr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr2, [r7, #544]\t@ 0x220\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr0, [r7, #776]\t@ 0x308\n \tadds\tr1, r3, r2\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tcmp\tr1, r3\n-\tbge.n\te828 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb00>\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tadd\tr1, r3\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #780]\t@ 0x30c\n+\taddlt\tr1, r1, r3\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tadds\tr2, r3, r1\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tcmp\tr2, r3\n-\tbge.n\te83c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb14>\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n-\tldr.w\tr0, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #780]\t@ 0x30c\n+\taddlt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tadd\tr3, r2\n \tcmp\tr3, r0\n-\tbge.n\te850 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb28>\n-\tldr.w\tr0, [r7, #596]\t@ 0x254\n-\tadd\tr3, r0\n-\tldr.w\tr0, [r7, #584]\t@ 0x248\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr0, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r0\n+\tldr.w\tr0, [r7, #772]\t@ 0x304\n \tadd\tr0, r3\n \tcmp\tr0, r4\n-\tbge.n\te864 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb3c>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tr0, r4\n-\tldr.w\tr4, [r7, #544]\t@ 0x220\n+\titt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr0, r0, r4\n+\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n \tcmp\tr4, #0\n-\tbne.w\tead6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xdae>\n-\tldr.w\tr4, [r7, #568]\t@ 0x238\n+\tbne.w\tf632 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xe7a>\n+\tldr.w\tr4, [r7, #768]\t@ 0x300\n \tcmp\tr4, #0\n-\tble.w\te9e6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xcbe>\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n+\tble.w\tf4fc <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd44>\n+\tldr.w\tr4, [r7, #728]\t@ 0x2d8\n \tlsls\tr1, r1, #3\n \tlsls\tr0, r0, #3\n+\tmovs\tr6, #1\n+\tstr.w\tr6, [r7, #716]\t@ 0x2cc\n \tlsls\tr2, r2, #3\n-\tlsls\tr3, r3, #3\n-\tadd.w\tsl, fp, r1\n \tlsls\tr4, r4, #3\n-\tadd.w\tr9, fp, r0\n-\tadd.w\tr8, fp, r2\n-\tadd.w\tr6, fp, r4\n-\tadd\tr1, r5\n-\tadd\tr0, r5\n-\tadd\tr2, r5\n-\tadd\tr4, r5\n-\tadd.w\tip, fp, r3\n-\tstr.w\tr5, [r7, #536]\t@ 0x218\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tvldr\td21, [r9, #-8]\n-\tvldr\td25, [ip, #-8]\n-\tvldr\td24, [sl, #-8]\n-\tvldr\td17, [r8, #-8]\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tvadd.f64\td18, d24, d21\n-\tvldr\td20, [r0, #-8]\n-\tvadd.f64\td19, d17, d25\n-\tvldr\td23, [r1, #-8]\n-\tvldr\td30, [r6, #-8]\n-\tvsub.f64\td17, d17, d25\n-\tvldr\td26, [r3, #-8]\n-\tvsub.f64\td24, d24, d21\n-\tvldr\td16, [r2, #-8]\n-\tvadd.f64\td21, d23, d20\n-\tvadd.f64\td25, d18, d19\n-\tvsub.f64\td23, d23, d20\n-\tvmov.f64\td20, d30\n-\tvmul.f64\td29, d17, d9\n-\tvsub.f64\td18, d18, d19\n-\tvadd.f64\td19, d16, d26\n-\tvmul.f64\td17, d17, d8\n-\tvsub.f64\td16, d16, d26\n-\tvfms.f64\td20, d25, d22\n-\tvldr\td31, [r4, #-8]\n-\tvmov.f64\td26, d29\n-\tvfma.f64\td17, d24, d9\n-\tvfnms.f64\td26, d24, d8\n-\tvfms.f64\td29, d24, d8\n-\tvadd.f64\td24, d21, d19\n-\tvsub.f64\td21, d21, d19\n-\tvmul.f64\td19, d9, d16\n-\tvmul.f64\td16, d8, d16\n-\tvfma.f64\td16, d9, d23\n-\tvadd.f64\td25, d25, d30\n-\tldr.w\tr5, [r7, #580]\t@ 0x244\n-\tvmov.f64\td28, d20\n-\tvfms.f64\td20, d18, d10\n-\tvfma.f64\td28, d18, d10\n-\tvmov.f64\td18, d31\n-\tvfms.f64\td18, d24, d22\n-\tvmov.f64\td27, d19\n-\tvfnms.f64\td27, d8, d23\n-\tvfma.f64\td19, d23, d12\n-\tvstr\td25, [r6, #-8]\n-\tvadd.f64\td24, d24, d31\n-\tadds\tr5, #1\n-\tadd\tr6, lr\n-\tstr.w\tr5, [r7, #580]\t@ 0x244\n-\tvstr\td24, [r4, #-8]\n-\tadd\tr4, lr\n-\tvmov.f64\td23, d18\n-\tvfma.f64\td18, d21, d11\n-\tvfma.f64\td23, d10, d21\n-\tvsub.f64\td21, d28, d16\n-\tvadd.f64\td16, d28, d16\n-\tvadd.f64\td27, d20, d27\n-\tvadd.f64\td19, d20, d19\n-\tvstr\td21, [sl, #-8]\n-\tadd\tsl, lr\n-\tvstr\td16, [r9, #-8]\n-\tadd\tr9, lr\n-\tvstr\td19, [r8, #-8]\n-\tadd\tr8, lr\n-\tvadd.f64\td26, d26, d18\n-\tvadd.f64\td18, d18, d29\n-\tvadd.f64\td16, d17, d23\n-\tvsub.f64\td23, d23, d17\n-\tvstr\td27, [ip, #-8]\n-\tadd\tip, lr\n-\tvstr\td16, [r1, #-8]\n-\tadd\tr1, lr\n-\tvstr\td23, [r0, #-8]\n-\tadd\tr0, lr\n-\tvstr\td26, [r2, #-8]\n-\tadd\tr2, lr\n-\tvstr\td18, [r3, #-8]\n-\tadd\tr3, lr\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tcmp\tr5, r3\n-\tbne.w\te8b2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb8a>\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tlsls\tr3, r3, #3\n+\tadd.w\tr9, sl, r1\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tr5, sl, r4\n+\tadd\tr1, fp\n+\tadd\tr0, fp\n+\tadd\tr4, fp\n+\tadd.w\tlr, sl, r2\n+\tadd.w\tip, sl, r3\n+\tadd\tr2, fp\n+\tadd\tr3, fp\n+\tstr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tvldr\td7, [r8, #-8]\n+\tvldr\td5, [r9, #-8]\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tadds\tr3, #1\n+\tstrd\tr3, r3, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tvadd.f64\td2, d5, d7\n+\tvldr\td3, [ip, #-8]\n+\tvsub.f64\td5, d5, d7\n+\tvldr\td7, [lr, #-8]\n+\tvldr\td1, [r1, #-8]\n+\tvldr\td10, [r3, #-8]\n+\tvldr\td9, [r0, #-8]\n+\tvadd.f64\td0, d7, d3\n+\tvldr\td6, [r2, #-8]\n+\tvsub.f64\td7, d7, d3\n+\tvldr\td11, [r4, #-8]\n+\tvadd.f64\td3, d1, d9\n+\tvsub.f64\td9, d1, d9\n+\tvadd.f64\td1, d10, d6\n+\tvadd.f64\td4, d2, d0\n+\tvsub.f64\td6, d10, d6\n+\tvldr\td10, [r5, #-8]\n+\tvsub.f64\td0, d2, d0\n+\tvadd.f64\td2, d3, d1\n+\tvsub.f64\td1, d3, d1\n+\tvmov.f64\td3, d10\n+\tvmls.f64\td3, d4, d12\n+\tvadd.f64\td4, d4, d10\n+\tvmul.f64\td0, d0, d14\n+\tvmul.f64\td10, d15, d6\n+\tvmul.f64\td1, d1, d14\n+\tvmla.f64\td10, d8, d9\n+\tvmul.f64\td6, d8, d6\n+\tvmul.f64\td9, d15, d9\n+\tvstr\td4, [r5, #-8]\n+\tvmov.f64\td4, d11\n+\tvmls.f64\td4, d2, d12\n+\tvadd.f64\td2, d2, d11\n+\tvmul.f64\td11, d7, d15\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td11, d5, d8\n+\tvmul.f64\td5, d5, d15\n+\tadd\tr5, r6\n+\tvstr\td2, [r4, #-8]\n+\tvadd.f64\td2, d0, d3\n+\tvsub.f64\td3, d3, d0\n+\tadd\tr4, r6\n+\tvadd.f64\td0, d1, d4\n+\tvsub.f64\td4, d4, d1\n+\tvsub.f64\td1, d5, d7\n+\tvsub.f64\td7, d7, d5\n+\tvadd.f64\td1, d1, d4\n+\tvadd.f64\td4, d7, d4\n+\tvsub.f64\td7, d6, d9\n+\tvsub.f64\td9, d9, d6\n+\tvsub.f64\td6, d2, d10\n+\tvadd.f64\td2, d2, d10\n+\tvadd.f64\td7, d7, d3\n+\tvadd.f64\td9, d9, d3\n+\tvstr\td6, [r9, #-8]\n+\tadd\tr9, r6\n+\tvstr\td2, [r8, #-8]\n+\tadd\tr8, r6\n+\tvstr\td7, [lr, #-8]\n+\tvadd.f64\td7, d11, d0\n+\tvsub.f64\td0, d0, d11\n+\tvstr\td9, [ip, #-8]\n+\tadd\tlr, r6\n+\tadd\tip, r6\n+\tvstr\td7, [r1, #-8]\n+\tadd\tr1, r6\n+\tvstr\td0, [r0, #-8]\n+\tadd\tr0, r6\n+\tvstr\td1, [r3, #-8]\n+\tadd\tr3, r6\n+\tvstr\td4, [r2, #-8]\n+\tadd\tr2, r6\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr2, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tcmp\tr3, r2\n+\tbne.w\tf3bc <__gridxc_gpfa_core_dp_MOD_gpfa_+0xc04>\n+\tstr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tstr.w\tr3, [r7, #588]\t@ 0x24c\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, r2\n-\tbge.n\tea06 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xcde>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n+\tbge.n\tf51c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd64>\n+\tldr.w\tr2, [r7, #780]\t@ 0x30c\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tldr.w\tr2, [r7, #652]\t@ 0x28c\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tstr.w\tr3, [r7, #668]\t@ 0x29c\n \tcmp\tr3, r2\n-\tbne.w\te814 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xaec>\n-\tldrd\tr8, r6, [r7, #432]\t@ 0x1b0\n-\tldrd\tr9, r1, [r7, #420]\t@ 0x1a4\n-\tsubs\tr6, #1\n-\tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tadds\tr2, r6, #1\n-\tldrd\tr4, sl, [r7, #412]\t@ 0x19c\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r7, #520]\t@ 0x208\n-\tbne.w\te7fa <__gridxc_gpfa_core_dp_MOD_gpfa_+0xad2>\n-\tldr.w\tr0, [r7, #460]\t@ 0x1cc\n-\tmov\tip, fp\n-\tldrd\tr3, r2, [r7, #440]\t@ 0x1b8\n-\tstr.w\tr5, [r7, #588]\t@ 0x24c\n-\tldr.w\tr6, [r7, #544]\t@ 0x220\n-\tsubs\tr0, #1\n-\tldr.w\tr5, [r7, #496]\t@ 0x1f0\n-\tadd\tr9, r8\n-\tadd\tr6, r8\n-\tstr.w\tr6, [r7, #544]\t@ 0x220\n-\tadd\tr2, r5\n-\tldr.w\tr6, [r7, #512]\t@ 0x200\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n-\tsub.w\tsl, sl, r8\n-\tadd\tr6, r5\n-\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n-\tstr.w\tr6, [r7, #512]\t@ 0x200\n-\tadd\tr4, r5\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tadd\tr3, r5\n-\tadds\tr5, r0, #1\n-\tbeq.w\tec9e <__gridxc_gpfa_core_dp_MOD_gpfa_+0xf76>\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n-\tcmp\tr5, #0\n-\tble.w\te7ac <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa84>\n-\tvldr\td4, [r2]\n-\tcmp\tr1, #0\n-\tvldr\td15, [r6]\n-\tvldr\td14, [r4]\n-\tvldr\td13, [r3]\n-\tvmul.f64\td4, d7, d4\n-\tvmul.f64\td15, d7, d15\n-\tvldr\td2, [r2, #-8]\n-\tvmul.f64\td14, d7, d14\n-\tvldr\td1, [r6, #-8]\n-\tvmul.f64\td13, d7, d13\n-\tvldr\td0, [r4, #-8]\n+\tbne.w\tf316 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb5e>\n+\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tr1, [r7, #640]\t@ 0x280\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tsubs\tr3, #1\n+\tldr.w\tr4, [r7, #560]\t@ 0x230\n+\tadd\tr2, r1\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tldrd\tr8, r9, [r7, #548]\t@ 0x224\n+\tadds\tr1, r3, #1\n+\tbne.w\tf2f8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb40>\n+\tmov\tr5, sl\n+\tldr.w\tsl, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tadd.w\tsl, sl, #4294967295\t@ 0xffffffff\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tcmp.w\tsl, #4294967295\t@ 0xffffffff\n+\tadd\tr2, r3\n+\tstr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr2, [r7, #664]\t@ 0x298\n+\tadd\tr2, r3\n+\tstr.w\tr2, [r7, #664]\t@ 0x298\n+\tldr.w\tr2, [r7, #656]\t@ 0x290\n+\tsub.w\tr3, r2, r3\n+\tstr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tadd\tr4, r3\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tadd\tr3, r2\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #604]\t@ 0x25c\n+\tadd\tr9, r3\n+\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tadd\tr8, r3\n+\tbeq.w\tf84c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1094>\n+\tldr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tcmp\tr3, #0\n+\tble.w\tf2ba <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb02>\n+\tldr.w\tr3, [r7, #632]\t@ 0x278\n+\tvldr\td3, [r4, #-8]\n+\tvldr\td4, [r8]\n+\tvldr\td6, [r4]\n+\tvstr\td3, [r7, #760]\t@ 0x2f8\n \tvldr\td3, [r3, #-8]\n-\tbge.w\te7b2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa8a>\n-\tldr.w\tr5, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr6, [r7, #544]\t@ 0x220\n-\tudiv\tfp, r9, r5\n-\tldr.w\tr5, [r7, #164]\t@ 0xa4\n-\tcmp\tr5, r6\n-\tble.w\te7c4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa9c>\n-\tb.n\tea46 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd1e>\n-\tldr.w\tr4, [r7, #568]\t@ 0x238\n+\tvldr\td7, [r3]\n+\tvldr\td5, [r9]\n+\tvstr\td3, [r7, #752]\t@ 0x2f0\n+\tvldr\td3, [r7, #104]\t@ 0x68\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td6, d3, d6\n+\tcmp\tr3, #0\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td6, [r7, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d3, d5\n+\tvstr\td7, [r7, #424]\t@ 0x1a8\n+\tvldr\td7, [r9, #-8]\n+\tvstr\td6, [r7, #432]\t@ 0x1b0\n+\tvstr\td7, [r7, #736]\t@ 0x2e0\n+\tvldr\td7, [r8, #-8]\n+\tvstr\td7, [r7, #456]\t@ 0x1c8\n+\tbge.w\tf2c4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb0c>\n+\tldr.w\tr1, [r7, #624]\t@ 0x270\n+\tldr.w\tr0, [r7, #664]\t@ 0x298\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr2, [r7, #168]\t@ 0xa8\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tmov\tr3, r0\n+\tcmp\tr2, r1\n+\tble.w\tf2de <__gridxc_gpfa_core_dp_MOD_gpfa_+0xb26>\n+\tb.n\tf558 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xda0>\n+\tldr.w\tr4, [r7, #768]\t@ 0x300\n \tcmp\tr4, #0\n-\tble.n\te9e6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xcbe>\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n+\tble.w\tf4fc <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd44>\n+\tldr.w\tr4, [r7, #728]\t@ 0x2d8\n \tlsls\tr1, r1, #3\n \tlsls\tr0, r0, #3\n \tlsls\tr2, r2, #3\n \tlsls\tr3, r3, #3\n-\tadd.w\tsl, fp, r1\n+\tadd.w\tr9, sl, r1\n \tlsls\tr4, r4, #3\n-\tadd.w\tr9, fp, r0\n-\tadd.w\tr8, fp, r2\n-\tadd.w\tr6, fp, r4\n-\tadd\tr1, r5\n-\tadd\tr0, r5\n-\tadd\tr2, r5\n-\tadd\tr4, r5\n-\tadd.w\tip, fp, r3\n-\tstr.w\tr5, [r7, #536]\t@ 0x218\n-\tadd\tr3, r5\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tvldr\td18, [ip, #-8]\n-\tvldr\td21, [r9, #-8]\n-\tvldr\td19, [r8, #-8]\n-\tvldr\td16, [sl, #-8]\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n-\tvsub.f64\td20, d19, d18\n-\tvadd.f64\td19, d19, d18\n-\tvsub.f64\td27, d16, d21\n-\tvadd.f64\td16, d16, d21\n-\tvldr\td30, [r6, #-8]\n-\tvldr\td29, [r0, #-8]\n-\tvldr\td26, [r3, #-8]\n-\tvmul.f64\td31, d9, d20\n-\tvldr\td24, [r1, #-8]\n-\tvadd.f64\td25, d16, d19\n-\tvldr\td17, [r2, #-8]\n-\tvsub.f64\td16, d16, d19\n-\tvmov.f64\td19, d30\n-\tvmul.f64\td20, d8, d20\n-\tvadd.f64\td23, d24, d29\n-\tvmov.f64\td18, d31\n-\tvadd.f64\td21, d17, d26\n-\tvsub.f64\td17, d17, d26\n-\tvfms.f64\td19, d25, d22\n-\tvfnms.f64\td18, d8, d27\n-\tvfma.f64\td20, d9, d27\n-\tvfma.f64\td31, d27, d12\n-\tvsub.f64\td24, d24, d29\n-\tvldr\td26, [r4, #-8]\n-\tvadd.f64\td27, d23, d21\n-\tvsub.f64\td23, d23, d21\n-\tvmul.f64\td21, d9, d17\n-\tvmul.f64\td17, d8, d17\n-\tldr.w\tr5, [r7, #580]\t@ 0x244\n-\tvfma.f64\td17, d9, d24\n-\tvadd.f64\td29, d25, d30\n-\tvadd.f64\td30, d27, d26\n-\tadds\tr5, #1\n-\tvmov.f64\td28, d21\n-\tvfma.f64\td21, d24, d12\n-\tvfnms.f64\td28, d8, d24\n-\tvmov.f64\td24, d19\n-\tvfma.f64\td24, d10, d16\n-\tvfma.f64\td19, d16, d11\n-\tvmov.f64\td25, d18\n-\tvmov.f64\td16, d26\n-\tvfms.f64\td16, d27, d22\n-\tvfma.f64\td25, d27, d22\n-\tvstr\td30, [r4, #-8]\n-\tadd\tr4, lr\n-\tvstr\td29, [r6, #-8]\n-\tadd\tr6, lr\n-\tstr.w\tr5, [r7, #580]\t@ 0x244\n-\tvadd.f64\td21, d19, d21\n-\tvadd.f64\td19, d19, d28\n-\tvsub.f64\td25, d25, d26\n-\tvmov.f64\td26, d16\n-\tvfma.f64\td26, d10, d23\n-\tvfma.f64\td16, d23, d11\n-\tvfma.f64\td25, d10, d23\n-\tvsub.f64\td23, d24, d17\n-\tvadd.f64\td24, d24, d17\n-\tvsub.f64\td27, d20, d26\n-\tvadd.f64\td17, d20, d26\n-\tvadd.f64\td18, d18, d16\n-\tvsub.f64\td26, d26, d20\n-\tvadd.f64\td16, d16, d31\n-\tvmul.f64\td25, d25, d14\n-\tvfma.f64\td25, d19, d0\n-\tvnmul.f64\td28, d4, d17\n-\tvmul.f64\td17, d2, d17\n-\tvnmul.f64\td20, d15, d18\n-\tvmul.f64\td26, d26, d3\n-\tvmul.f64\td18, d1, d18\n-\tvmul.f64\td16, d16, d0\n-\tvfma.f64\td17, d23, d4\n-\tvfma.f64\td26, d24, d13\n-\tvfma.f64\td18, d21, d15\n-\tvfma.f64\td16, d19, d14\n-\tvmul.f64\td27, d27, d13\n-\tvfma.f64\td28, d23, d2\n-\tvfma.f64\td27, d24, d3\n-\tvfma.f64\td20, d21, d1\n-\tvstr\td17, [r1, #-8]\n-\tadd\tr1, lr\n-\tvstr\td26, [r0, #-8]\n-\tadd\tr0, lr\n-\tvstr\td18, [r2, #-8]\n-\tadd\tr2, lr\n-\tvstr\td16, [r3, #-8]\n-\tadd\tr3, lr\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n-\tvstr\td28, [sl, #-8]\n-\tadd\tsl, lr\n-\tvstr\td27, [r9, #-8]\n-\tcmp\tr5, r3\n-\tvstr\td20, [r8, #-8]\n-\tadd\tr9, lr\n-\tvstr\td25, [ip, #-8]\n-\tadd\tr8, lr\n-\tadd\tip, lr\n-\tbne.w\teb18 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xdf0>\n-\tb.n\te9e2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xcba>\n-\tmov\tfp, ip\n-\tldr.w\tip, [r7, #588]\t@ 0x24c\n-\tb.n\te6dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9b4>\n-\tvldr\td8, [pc, #392]\t@ ee30 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1108>\n-\tvldr\td9, [pc, #396]\t@ ee38 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1110>\n-\tvldr\td16, [pc, #400]\t@ ee40 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1118>\n-\tvldr\td17, [pc, #404]\t@ ee48 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1120>\n-\tvldr\td10, [pc, #408]\t@ ee50 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1128>\n-\tb.w\te04e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x326>\n-\tldr\tr3, [pc, #424]\t@ (ee68 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1140>)\n-\tadd.w\tsl, r7, #624\t@ 0x270\n-\tvldr\td16, [pc, #400]\t@ ee58 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1130>\n+\tadd.w\tr8, sl, r0\n+\tadd.w\tr5, sl, r4\n+\tadd\tr1, fp\n+\tadd\tr0, fp\n+\tadd\tr4, fp\n+\tmovs\tr6, #1\n+\tadd.w\tlr, sl, r2\n+\tadd.w\tip, sl, r3\n+\tadd\tr2, fp\n+\tadd\tr3, fp\n+\tstr.w\tr6, [r7, #716]\t@ 0x2cc\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr2, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tvldr\td0, [r1, #-8]\n+\tvldr\td10, [r0, #-8]\n+\tadds\tr3, #1\n+\tldr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tvadd.f64\td6, d0, d10\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tvsub.f64\td10, d0, d10\n+\tvldr\td7, [r8, #-8]\n+\tvldr\td5, [r9, #-8]\n+\tvldr\td9, [lr, #-8]\n+\tvldr\td2, [r3, #-8]\n+\tvmul.f64\td4, d15, d10\n+\tvldr\td11, [r2, #-8]\n+\tvadd.f64\td3, d5, d7\n+\tvsub.f64\td5, d5, d7\n+\tvldr\td7, [ip, #-8]\n+\tvldr\td13, [r5, #-8]\n+\tvadd.f64\td0, d2, d11\n+\tvstr\td4, [r7, #704]\t@ 0x2c0\n+\tvadd.f64\td1, d9, d7\n+\tvsub.f64\td7, d9, d7\n+\tvsub.f64\td11, d2, d11\n+\tvldr\td2, [r4, #-8]\n+\tvmul.f64\td9, d15, d5\n+\tvadd.f64\td4, d6, d0\n+\tvsub.f64\td6, d6, d0\n+\tvadd.f64\td0, d3, d1\n+\tvsub.f64\td3, d3, d1\n+\tvmul.f64\td6, d6, d14\n+\tvmul.f64\td1, d3, d14\n+\tvmul.f64\td3, d8, d7\n+\tvmul.f64\td7, d15, d7\n+\tvmls.f64\td13, d0, d12\n+\tvmla.f64\td7, d8, d5\n+\tvmul.f64\td5, d4, d12\n+\tvadd.f64\td4, d4, d2\n+\tvstr\td1, [r7, #720]\t@ 0x2d0\n+\tvsub.f64\td1, d2, d5\n+\tvstr\td4, [r4, #-8]\n+\tadd\tr4, r6\n+\tvldr\td4, [r5, #-8]\n+\tvadd.f64\td0, d0, d4\n+\tvsub.f64\td4, d9, d3\n+\tvsub.f64\td3, d3, d9\n+\tvadd.f64\td5, d4, d5\n+\tvstr\td0, [r5, #-8]\n+\tadd\tr5, r6\n+\tvsub.f64\td5, d5, d2\n+\tvmul.f64\td2, d15, d11\n+\tvmul.f64\td11, d8, d11\n+\tvmla.f64\td2, d8, d10\n+\tvadd.f64\td5, d5, d6\n+\tvstr\td5, [r7, #680]\t@ 0x2a8\n+\tvadd.f64\td5, d6, d1\n+\tvsub.f64\td1, d1, d6\n+\tvadd.f64\td0, d7, d5\n+\tvadd.f64\td6, d3, d1\n+\tvadd.f64\td4, d4, d1\n+\tvldr\td3, [r7, #704]\t@ 0x2c0\n+\tvldr\td1, [r7, #720]\t@ 0x2d0\n+\tvsub.f64\td9, d3, d11\n+\tvstr\td6, [r7, #672]\t@ 0x2a0\n+\tvsub.f64\td11, d11, d3\n+\tvadd.f64\td6, d1, d13\n+\tvsub.f64\td13, d13, d1\n+\tvldr\td3, [r7, #440]\t@ 0x1b8\n+\tvadd.f64\td1, d6, d2\n+\tvsub.f64\td6, d6, d2\n+\tvadd.f64\td11, d11, d13\n+\tvadd.f64\td9, d9, d13\n+\tvldr\td13, [r7, #752]\t@ 0x2f0\n+\tvsub.f64\td2, d7, d5\n+\tvsub.f64\td5, d5, d7\n+\tvmul.f64\td7, d4, d3\n+\tvmul.f64\td10, d13, d4\n+\tvmla.f64\td10, d11, d3\n+\tvldr\td3, [r7, #448]\t@ 0x1c0\n+\tvnmls.f64\td7, d11, d13\n+\tvldr\td11, [r7, #760]\t@ 0x2f8\n+\tvmul.f64\td4, d0, d3\n+\tvmul.f64\td0, d11, d0\n+\tvmla.f64\td0, d6, d3\n+\tvldr\td3, [r7, #424]\t@ 0x1a8\n+\tvnmls.f64\td4, d6, d11\n+\tvstr\td0, [r1, #-8]\n+\tadd\tr1, r6\n+\tvstr\td4, [r9, #-8]\n+\tadd\tr9, r6\n+\tvldr\td4, [r7, #456]\t@ 0x1c8\n+\tvmul.f64\td6, d1, d4\n+\tvmul.f64\td1, d1, d3\n+\tvmla.f64\td6, d2, d3\n+\tvmla.f64\td1, d5, d4\n+\tvstr\td6, [r8, #-8]\n+\tadd\tr8, r6\n+\tvldr\td6, [r7, #736]\t@ 0x2e0\n+\tvldr\td5, [r7, #432]\t@ 0x1b0\n+\tvldr\td4, [r7, #680]\t@ 0x2a8\n+\tvstr\td7, [lr, #-8]\n+\tvmul.f64\td7, d9, d6\n+\tvmul.f64\td9, d9, d5\n+\tvstr\td1, [r0, #-8]\n+\tvmla.f64\td7, d4, d5\n+\tvldr\td5, [r7, #672]\t@ 0x2a0\n+\tvstr\td10, [r3, #-8]\n+\tadd\tr3, r6\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tadd\tlr, r6\n+\tvmla.f64\td9, d5, d6\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tadd\tr0, r6\n+\tvstr\td7, [ip, #-8]\n+\tadd\tip, r6\n+\tvstr\td9, [r2, #-8]\n+\tadd\tr2, r6\n+\tstr.w\tr2, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tcmp\tr3, r2\n+\tbne.w\tf67a <__gridxc_gpfa_core_dp_MOD_gpfa_+0xec2>\n+\tb.n\tf4f8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd40>\n+\tmov\tfp, r5\n+\tb.n\tf1da <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa22>\n+\tnegs\tr1, r3\n+\tnegs\tr0, r5\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr5, #0\n+\tmov\tsl, r0\n+\tble.w\tebdc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x424>\n+\tb.n\tf1da <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa22>\n+\tldr\tr3, [pc, #252]\t@ (f960 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11a8>)\n+\tadd.w\tsl, r7, #808\t@ 0x328\n+\tvldr\td7, [pc, #228]\t@ f950 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1198>\n \tmov\tr0, sl\n \tadd\tr3, pc\n-\tstr.w\tr3, [r7, #632]\t@ 0x278\n-\tldr\tr3, [pc, #408]\t@ (ee6c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1144>)\n-\tmovs\tr6, #20\n-\tvstr\td3, [r7, #488]\t@ 0x1e8\n-\tmovs\tr2, #0\n-\tvstr\td0, [r7, #496]\t@ 0x1f0\n+\tstr.w\tr3, [r7, #816]\t@ 0x330\n+\tldr\tr3, [pc, #236]\t@ (f964 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11ac>)\n+\tadd.w\tfp, r7, #1152\t@ 0x480\n+\tvstr\td7, [r7, #808]\t@ 0x328\n \tadd\tr3, pc\n-\tvstr\td1, [r7, #504]\t@ 0x1f8\n-\tvstr\td2, [r7, #512]\t@ 0x200\n-\tvstr\td16, [r7, #624]\t@ 0x270\n-\tstr.w\tfp, [r7, #680]\t@ 0x2a8\n-\tstr.w\tr3, [r7, #676]\t@ 0x2a4\n-\tadd.w\tr3, r7, #968\t@ 0x3c8\n-\tstr.w\tr6, [r7, #696]\t@ 0x2b8\n-\tstr.w\tr3, [r7, #692]\t@ 0x2b4\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tstr.w\tr2, [r7, #672]\t@ 0x2a0\n-\tmovw\tr2, #2615\t@ 0xa37\n-\tstr.w\tr2, [r7, #636]\t@ 0x27c\n+\tstr.w\tr6, [r7, #864]\t@ 0x360\n+\tstr.w\tr3, [r7, #860]\t@ 0x35c\n+\tmovs\tr3, #20\n+\tstr.w\tfp, [r7, #876]\t@ 0x36c\n+\tstr.w\tr3, [r7, #880]\t@ 0x370\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #856]\t@ 0x358\n+\tmovw\tr3, #2615\t@ 0xa37\n+\tstr.w\tr3, [r7, #820]\t@ 0x334\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr2, fp\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n+\tmov\tr2, r6\n+\tldr.w\tr1, [r7, #780]\t@ 0x30c\n \tmov\tr0, sl\n-\tadd.w\tfp, r7, #600\t@ 0x258\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n \tmov\tr0, sl\n-\tadd.w\tsl, r7, #604\t@ 0x25c\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr2, r6\n+\tadd.w\tsl, r7, #788\t@ 0x314\n+\tmov\tr3, fp\n+\tadd.w\tfp, r7, #784\t@ 0x310\n \tmov\tr1, fp\n-\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tmovs\tr2, #20\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr.w\tsl, [r7, #604]\t@ 0x25c\n+\tldr.w\tsl, [r7, #788]\t@ 0x314\n \tadd.w\tr6, sl, #6\n \tcmp\tr6, #1\n \tmov\tr0, r6\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #284]\t@ (ee70 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1148>)\n-\tldr.w\tfp, [r7, #600]\t@ 0x258\n+\tldr\tr3, [pc, #136]\t@ (f968 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11b0>)\n+\tldr.w\tfp, [r7, #784]\t@ 0x310\n \tmov\tr1, r0\n-\tstr.w\tr0, [r7, #560]\t@ 0x230\n+\tstr.w\tr0, [r7, #768]\t@ 0x300\n \tadd\tr3, pc\n \tmovs\tr2, #6\n \tmov\tr0, r6\n \tstrd\tsl, fp, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tcmp.w\tsl, #0\n-\tvldr\td2, [r7, #512]\t@ 0x200\n-\tvldr\td1, [r7, #504]\t@ 0x1f8\n-\tvldr\td0, [r7, #496]\t@ 0x1f0\n-\tvldr\td3, [r7, #488]\t@ 0x1e8\n-\tble.n\ted96 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x106e>\n+\tble.n\tf904 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x114c>\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvldr\td3, [r7, #488]\t@ 0x1e8\n-\tvldr\td0, [r7, #496]\t@ 0x1f0\n-\tvldr\td1, [r7, #504]\t@ 0x1f8\n-\tvldr\td2, [r7, #512]\t@ 0x200\n \tadd.w\tsl, sl, #32\n-\tvstr\td3, [r7, #488]\t@ 0x1e8\n \tmov\tr0, sl\n-\tvstr\td0, [r7, #496]\t@ 0x1f0\n \tcmp\tr0, #1\n-\tvstr\td1, [r7, #504]\t@ 0x1f8\n \tit\tcc\n \tmovcc\tr0, #1\n-\tvstr\td2, [r7, #512]\t@ 0x200\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #188]\t@ (ee74 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x114c>)\n+\tldr\tr3, [pc, #84]\t@ (f96c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11b4>)\n \tmov\tr2, r6\n-\tmov\tr1, r0\n+\tmov\tfp, r0\n \tadd\tr3, pc\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #26\n \tstr\tr3, [sp, #0]\n-\tldr.w\tr6, [r7, #560]\t@ 0x230\n-\tmov\tfp, r0\n+\tldr.w\tr6, [r7, #768]\t@ 0x300\n+\tmov\tr1, r0\n \tmov\tr0, sl\n \tmov\tr3, r6\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #156]\t@ (ee78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1150>)\n-\tldr.w\tr2, [r7, #520]\t@ 0x208\n-\tmov\tr1, sl\n+\tldr\tr3, [pc, #56]\t@ (f970 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11b8>)\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n \tmov\tr0, fp\n+\tmov\tr1, sl\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvldr\td3, [r7, #488]\t@ 0x1e8\n-\tvldr\td0, [r7, #496]\t@ 0x1f0\n-\tvldr\td1, [r7, #504]\t@ 0x1f8\n-\tvldr\td2, [r7, #512]\t@ 0x200\n-\tb.w\tddfc <__gridxc_gpfa_core_dp_MOD_gpfa_+0xd4>\n-\tmovs\tr2, #128\t@ 0x80\n-\tsub.w\tr8, r8, #128\t@ 0x80\n-\tstr.w\tr2, [r7, #568]\t@ 0x238\n-\tb.w\te0e2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3ba>\n-\tstr.w\tr8, [r7, #568]\t@ 0x238\n-\tmov.w\tr8, #0\n-\tb.w\te0e2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3ba>\n-\tnegs\tr4, r2\n-\trsb\tr1, r8, #0\n-\tcmp\tr2, #0\n-\tudiv\tr1, r4, r1\n-\tble.w\te134 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x40c>\n-\tb.n\te6dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9b4>\n-\tnop\n-\t.word\t0x13445503\n-\t.word\t0xbfee6f0e\n-\t.word\t0x04755a5d\n-\t.word\t0xbfe2cf23\n-\t.word\t0x13445503\n-\t.word\t0x3fee6f0e\n-\t.word\t0x04755a5d\n-\t.word\t0x3fe2cf23\n-\t.word\t0x9b97f4a4\n-\t.word\t0xbfe1e377\n+\tb.w\te8b6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xfe>\n \t.word\t0x00005000\n \t.word\t0xffffffff\n-\t.word\t0x0000071e\n+\t.word\t0x0000071a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000019a\n+\t.word\t0x000000ee\n R_ARM_REL32\t.LC0\n-\t.word\t0x0000018a\n+\t.word\t0x000000e2\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000110\n+\t.word\t0x0000007a\n R_ARM_REL32\t.LC2\n-\t.word\t0x000000b4\n+\t.word\t0x0000004e\n R_ARM_REL32\t.LC3\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\tldr.w\tr1, [r7, #140]\t@ 0x8c\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tcmp\tr1, r2\n-\tblt.w\te702 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9da>\n-\tldr.w\tfp, [r7, #488]\t@ 0x1e8\n-\tmov\tr9, r4\n-\tstr.w\tr8, [r7, #32]\n-\tmov\tr8, ip\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tstr\tr3, [r7, #28]\n-\tldr.w\tr0, [r7, #596]\t@ 0x254\n-\tmov\tr5, fp\n-\tadd.w\tfp, fp, fp, lsl #2\n-\tldr.w\tr1, [r7, #136]\t@ 0x88\n-\tsdiv\tr2, r0, fp\n-\tmul.w\tr3, r1, r5\n-\tsubs\tr4, r3, r0\n-\tstr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tsubs\tr0, r2, r0\n-\tstr.w\tr0, [r7, #588]\t@ 0x24c\n-\tmov\tr0, r1\n-\tsubs\tr1, r2, r1\n-\tcmp\tr0, #0\n-\tblt.w\t108ce <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2ba6>\n-\tldr.w\tr0, [r7, #136]\t@ 0x88\n-\tcmp\tr1, #0\n-\tudiv\tr0, r1, r0\n-\tblt.w\t108b2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2b8a>\n-\tadd.w\tip, r2, r2, lsl #2\n-\tmovs\tr1, #24\n-\tlsls\tr2, r5, #1\n-\tadd.w\tlr, r3, r3, lsl #2\n-\tstr.w\tfp, [r7, #24]\n-\tmov\tsl, r8\n-\tmov\tfp, r9\n-\tstr.w\tip, [r7, #120]\t@ 0x78\n-\tmul.w\tr2, r1, r2\n-\tmov\tr4, r0\n-\tstr\tr2, [r7, #52]\t@ 0x34\n-\tldr.w\tr2, [r7, #132]\t@ 0x84\n-\tadd.w\tr1, r2, #8\n-\tldr.w\tr2, [r7, #136]\t@ 0x88\n-\tmov\tr6, r1\n-\tmov\tr9, r1\n-\tsubs\tr3, r3, r2\n-\tmovs\tr2, #0\n-\tstr\tr3, [r7, #80]\t@ 0x50\n-\trsb\tr3, ip, #0\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\trsb\tr3, lr, #0\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tlsls\tr3, r5, #4\n+\tmov\tr3, r2\n+\tldr.w\tr2, [r7, #140]\t@ 0x8c\n+\tcmp\tr2, r3\n+\tblt.w\tf1fe <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa46>\n \tstr\tr3, [r7, #60]\t@ 0x3c\n-\tlsls\tr3, r5, #5\n-\tstr\tr3, [r7, #56]\t@ 0x38\n-\tlsls\tr3, r5, #6\n-\tstr\tr3, [r7, #48]\t@ 0x30\n-\tmov\tip, r1\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n-\tmov\tr5, r2\n-\tstr\tr1, [r7, #124]\t@ 0x7c\n+\tldr.w\tr3, [r7, #768]\t@ 0x300\n+\tstrd\tsl, r8, [r7, #12]\n \tadds\tr3, #1\n-\tstr.w\tr2, [r7, #372]\t@ 0x174\n-\tstr.w\tr3, [r7, #360]\t@ 0x168\n-\tldr\tr3, [r7, #120]\t@ 0x78\n+\tstr.w\tr3, [r7, #408]\t@ 0x198\n+\tldr.w\tr3, [r7, #136]\t@ 0x88\n+\tldr.w\tr4, [r7, #780]\t@ 0x30c\n+\tmov\tr6, r3\n+\tadd.w\tr3, r3, r3, lsl #2\n+\tmov\tr0, r4\n+\tmov\tr1, r3\n+\tstr.w\tr3, [r7, #136]\t@ 0x88\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r7, #164]\t@ 0xa4\n+\tmov\tr2, r4\n+\tsubs\tr1, r0, r4\n+\tmov\tr9, r0\n+\tsubs\tr4, r0, r3\n \tcmp\tr3, #0\n-\tblt.w\tfd1e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ff6>\n-\tldr\tr2, [r7, #80]\t@ 0x50\n+\tstr.w\tr1, [r7, #772]\t@ 0x304\n+\tmul.w\tr5, r3, r6\n+\tsub.w\tr2, r5, r2\n+\tstr.w\tr2, [r7, #652]\t@ 0x28c\n+\tblt.w\t116f6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f3e>\n \tmov\tr1, r3\n-\tadds\tr3, r2, r5\n-\tudiv\tr3, r3, r1\n-\tldr.w\tr1, [r7, #372]\t@ 0x174\n-\tcmp\tr2, r1\n-\tblt.w\tfcaa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f82>\n-\tldr.w\tr1, [r7, #164]\t@ 0xa4\n-\tldr.w\tr2, [r7, #372]\t@ 0x174\n-\tadd.w\tr8, r1, r5\n-\tstr.w\tr9, [r7, #8]\n-\tstr\tr5, [r7, #4]\n-\tmov\tr9, sl\n-\tldr\tr5, [r7, #120]\t@ 0x78\n-\tsubs\tr0, r2, r1\n-\tldr.w\tsl, [r7, #76]\t@ 0x4c\n-\tstr\tr4, [r7, #20]\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, #0\n+\tstr\tr0, [r7, #124]\t@ 0x7c\n+\tblt.w\t116dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f24>\n+\tlsls\tr3, r6, #1\n+\tmovs\tr2, #24\n+\tldr.w\tr0, [r7, #164]\t@ 0xa4\n+\tadd.w\tr1, r9, r9, lsl #2\n+\tstr\tr1, [r7, #100]\t@ 0x64\n+\tnegs\tr1, r1\n+\tmul.w\tr3, r2, r3\n+\tsubs\tr0, r5, r0\n+\tstr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr3, [r7, #120]\t@ 0x78\n+\tstr\tr0, [r7, #112]\t@ 0x70\n+\tmovs\tr0, #0\n+\tadd.w\tr2, r3, #8\n+\tadd.w\tr3, r5, r5, lsl #2\n+\tstr.w\tr3, [r7, #248]\t@ 0xf8\n+\tnegs\tr3, r3\n+\tstr\tr3, [r7, #48]\t@ 0x30\n+\tlsls\tr3, r6, #4\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tlsls\tr3, r6, #5\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tlsls\tr3, r6, #6\n+\tstr\tr3, [r7, #32]\n \tmov\tr4, r2\n-\tstrd\tip, r6, [r7, #12]\n-\tmov\tip, fp\n-\tstr.w\tr0, [r7, #148]\t@ 0x94\n-\tstr.w\tr8, [r7, #144]\t@ 0x90\n-\tcmp.w\tlr, #0\n-\tblt.w\t10890 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2b68>\n-\tldr.w\tr2, [r7, #144]\t@ 0x90\n-\tudiv\tr2, r2, lr\n-\tmov\tr6, r2\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n-\tcmp\tr2, r4\n-\tblt.w\tfc7c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f54>\n-\tldr.w\tr2, [r7, #152]\t@ 0x98\n-\tcmp\tr2, #0\n-\tble.w\tfc7c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f54>\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n-\tadds\tr2, #1\n-\tstr\tr3, [r7, #116]\t@ 0x74\n-\tmov\tr3, r6\n-\tadds\tr0, r1, r4\n-\tmov\tr6, r9\n-\tmov\tr9, sl\n-\tmov\tsl, ip\n-\tvmov.f64\td5, #80\t@ 0x3e800000 0.250\n-\tstr.w\tr2, [r7, #156]\t@ 0x9c\n-\tstr.w\tlr, [r7, #168]\t@ 0xa8\n-\tstrd\tr4, r5, [r7, #108]\t@ 0x6c\n-\tmov\tlr, r6\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tmov\tr8, r2\n+\tmov\tr9, r2\n+\tmov\tr6, fp\n+\tadds\tr3, #1\n+\tstr.w\tr0, [r7, #132]\t@ 0x84\n+\tstr\tr1, [r7, #52]\t@ 0x34\n+\tstr\tr2, [r7, #96]\t@ 0x60\n+\tstr.w\tr0, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr3, [r7, #152]\t@ 0x98\n+\tldr\tr3, [r7, #100]\t@ 0x64\n+\tcmp\tr3, #0\n+\tblt.w\t108ca <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2112>\n+\tmov\tr1, r3\n+\tldr\tr5, [r7, #112]\t@ 0x70\n+\tldr.w\tr3, [r7, #132]\t@ 0x84\n+\tadds\tr0, r5, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n+\tmov\tr1, r0\n+\tcmp\tr5, r3\n+\tblt.w\t10828 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2070>\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr2, [r7, #132]\t@ 0x84\n+\tsub.w\tsl, r5, r3\n+\tstrd\tr8, r4, [r7, #4]\n+\tadd.w\tfp, r3, r2\n+\tstr.w\tfp, [r7, #144]\t@ 0x90\n \tmov\tfp, sl\n-\tmov\tr6, r9\n-\tmovs\tr2, #1\n-\tstr.w\tr0, [r7, #580]\t@ 0x244\n-\tstr.w\tr2, [r7, #460]\t@ 0x1cc\n-\tstr.w\tr3, [r7, #256]\t@ 0x100\n-\tstr.w\tr0, [r7, #252]\t@ 0xfc\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr2, [r7, #588]\t@ 0x24c\n+\tldr.w\tsl, [r7, #100]\t@ 0x64\n+\tstr.w\tr9, [r7]\n+\tmov\tr8, r1\n+\tmov\tr9, r6\n+\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tcmp\tr3, #0\n+\tblt.w\t116c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f0a>\n+\tmov\tr1, r3\n+\tldr.w\tr0, [r7, #144]\t@ 0x90\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tmov\tr1, r0\n+\tcmp\tr3, r5\n+\tblt.w\t10802 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204a>\n+\tldr.w\tr3, [r7, #148]\t@ 0x94\n+\tcmp\tr3, #0\n+\tble.w\t10802 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204a>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tmov\tip, r9\n+\tstr.w\tr8, [r7, #88]\t@ 0x58\n+\tldr.w\tlr, [r7, #128]\t@ 0x80\n+\tadds\tr0, r3, r5\n+\tldr.w\tr8, [r7, #92]\t@ 0x5c\n+\tstrd\tr5, sl, [r7, #80]\t@ 0x50\n+\tstr.w\tfp, [r7, #76]\t@ 0x4c\n+\tmov\tfp, ip\n+\tmov\tr6, r8\n+\tmovs\tr3, #1\n+\tstr.w\tr0, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr3, [r7, #648]\t@ 0x288\n+\tstr.w\tr1, [r7, #260]\t@ 0x104\n+\tstr.w\tr0, [r7, #256]\t@ 0x100\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr2, [r7, #772]\t@ 0x304\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tadds\tr0, r3, r2\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n \tcmp\tr0, r3\n-\tbge.n\teff6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x12ce>\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tadd\tr0, r3\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #780]\t@ 0x30c\n+\taddlt\tr0, r0, r3\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tadd\tr3, r0\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, r2\n-\tbge.n\tf012 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x12ea>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #584]\t@ 0x248\n-\tldrd\tr2, r3, [r7, #584]\t@ 0x248\n+\tittt\tlt\n+\tldrlt.w\tr2, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r2\n+\tstrlt.w\tr3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n \tcmp\tr3, r2\n-\tbge.n\tf02e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1306>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tldr.w\tr2, [r7, #560]\t@ 0x230\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tittt\tlt\n+\tldrlt.w\tr2, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r2\n+\tstrlt.w\tr3, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr2, [r7, #716]\t@ 0x2cc\n \tadd\tr3, r2\n-\tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tstr.w\tr3, [r7, #576]\t@ 0x240\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #640]\t@ 0x280\n \tcmp\tr3, r2\n-\tbge.n\tf04e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1326>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #576]\t@ 0x240\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr2, [r7, #480]\t@ 0x1e0\n+\titt\tlt\n+\tldrlt.w\tr2, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r2\n+\tldr.w\tr2, [r7, #652]\t@ 0x28c\n+\tit\tlt\n+\tstrlt.w\tr3, [r7, #640]\t@ 0x280\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tadds\tr2, r3, r2\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tcmp\tr2, r3\n-\tbge.n\tf066 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x133e>\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tadd\tr2, r3\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #780]\t@ 0x30c\n+\taddlt\tr2, r2, r3\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n \tcmp\tr3, r1\n-\tbge.n\tf082 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x135a>\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n-\tldr.w\tr1, [r7, #552]\t@ 0x228\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n+\tittt\tlt\n+\tldrlt.w\tr1, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r1\n+\tstrlt.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n \tadd\tr3, r1\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tcmp\tr3, r1\n-\tbge.n\tf0a2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x137a>\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tittt\tlt\n+\tldrlt.w\tr1, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r1\n+\tstrlt.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n \tadd.w\tsl, r3, r1\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tcmp\tsl, r3\n-\tbge.n\tf0bc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1394>\n-\tldr.w\tr3, [r7, #596]\t@ 0x254\n-\tadd\tsl, r3\n-\tldr.w\tr3, [r7, #588]\t@ 0x24c\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr3, [r7, #780]\t@ 0x30c\n+\taddlt\tsl, r3\n+\tldr.w\tr3, [r7, #772]\t@ 0x304\n \tadd\tr3, sl\n-\tstr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr3, [r7, #632]\t@ 0x278\n \tcmp\tr3, r1\n-\tbge.n\tf0d8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x13b0>\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tldr.w\tr3, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tittt\tlt\n+\tldrlt.w\tr1, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r1\n+\tstrlt.w\tr3, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #652]\t@ 0x28c\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tadd\tr3, r2\n \tcmp\tr3, r1\n-\tbge.n\tf0ec <__gridxc_gpfa_core_dp_MOD_gpfa_+0x13c4>\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tadd\tr3, r1\n-\tldr.w\tr1, [r7, #588]\t@ 0x24c\n+\titt\tlt\n+\tldrlt.w\tr1, [r7, #780]\t@ 0x30c\n+\taddlt\tr3, r3, r1\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n \tadd.w\tr9, r1, r3\n-\tldr.w\tr1, [r7, #592]\t@ 0x250\n+\tldr.w\tr1, [r7, #776]\t@ 0x308\n \tcmp\tr9, r1\n-\tbge.n\tf102 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x13da>\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tadd\tr9, r1\n-\tldr.w\tr1, [r7, #588]\t@ 0x24c\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr1, [r7, #780]\t@ 0x30c\n+\taddlt\tr9, r1\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n \tadd\tr1, r9\n-\tstr.w\tr1, [r7, #536]\t@ 0x218\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n \tcmp\tr1, r4\n-\tbge.n\tf11e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x13f6>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n+\tittt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr1, r1, r4\n+\tstrlt.w\tr1, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n+\tldr.w\tr4, [r7, #688]\t@ 0x2b0\n \tadd\tr1, r4\n-\tstr.w\tr1, [r7, #536]\t@ 0x218\n-\tldr.w\tr4, [r7, #536]\t@ 0x218\n-\tldr.w\tr1, [r7, #588]\t@ 0x24c\n-\tadd\tr1, r4\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n-\tstr.w\tr1, [r7, #528]\t@ 0x210\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n \tcmp\tr1, r4\n-\tbge.n\tf13e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1416>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n+\tittt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr1, r1, r4\n+\tstrlt.w\tr1, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr1, [r7, #772]\t@ 0x304\n+\tldr.w\tr4, [r7, #712]\t@ 0x2c8\n \tadd\tr1, r4\n-\tstr.w\tr1, [r7, #528]\t@ 0x210\n-\tldr.w\tr4, [r7, #528]\t@ 0x210\n-\tldr.w\tr1, [r7, #588]\t@ 0x24c\n-\tadd\tr1, r4\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n-\tstr.w\tr1, [r7, #468]\t@ 0x1d4\n+\tstr.w\tr1, [r7, #624]\t@ 0x270\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n \tcmp\tr1, r4\n-\tbge.n\tf15e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1436>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tr1, r4\n-\tstr.w\tr1, [r7, #468]\t@ 0x1d4\n-\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\tittt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr1, r1, r4\n+\tstrlt.w\tr1, [r7, #624]\t@ 0x270\n+\tldr.w\tr1, [r7, #652]\t@ 0x28c\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tadd\tr1, r3\n \tcmp\tr1, r4\n-\tbge.n\tf172 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x144a>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tr1, r4\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n+\titt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr1, r1, r4\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n \tadd.w\tr8, r4, r1\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n \tcmp\tr8, r4\n-\tbge.n\tf188 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1460>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tr8, r4\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr8, r4\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n \tadd\tr4, r8\n-\tstr.w\tr4, [r7, #520]\t@ 0x208\n+\tstr.w\tr4, [r7, #680]\t@ 0x2a8\n \tcmp\tr4, r5\n-\tbge.n\tf1a4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x147c>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n+\tittt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tstrlt.w\tr4, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n \tadd\tr4, r5\n-\tstr.w\tr4, [r7, #520]\t@ 0x208\n-\tldr.w\tr5, [r7, #520]\t@ 0x208\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n-\tadd\tr4, r5\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n-\tstr.w\tr4, [r7, #512]\t@ 0x200\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n+\tstr.w\tr4, [r7, #672]\t@ 0x2a0\n \tcmp\tr4, r5\n-\tbge.n\tf1c4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x149c>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tadd\tr4, r5\n-\tstr.w\tr4, [r7, #512]\t@ 0x200\n-\tldr.w\tr5, [r7, #512]\t@ 0x200\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n+\tittt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tstrlt.w\tr4, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n \tadd\tr4, r5\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n-\tstr.w\tr4, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n+\tstr.w\tr4, [r7, #616]\t@ 0x268\n \tcmp\tr4, r5\n-\tbge.n\tf1e4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x14bc>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tadd\tr4, r5\n-\tstr.w\tr4, [r7, #464]\t@ 0x1d0\n-\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\tittt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tstrlt.w\tr4, [r7, #616]\t@ 0x268\n+\tldr.w\tr4, [r7, #652]\t@ 0x28c\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n \tadd\tr4, r1\n-\tstr.w\tr4, [r7, #504]\t@ 0x1f8\n+\tstr.w\tr4, [r7, #668]\t@ 0x29c\n \tcmp\tr4, r5\n-\tbge.n\tf200 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x14d8>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tadd\tr4, r5\n-\tstr.w\tr4, [r7, #504]\t@ 0x1f8\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n-\tldr.w\tr5, [r7, #504]\t@ 0x1f8\n+\tittt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tstrlt.w\tr4, [r7, #668]\t@ 0x29c\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n+\tldr.w\tr5, [r7, #668]\t@ 0x29c\n \tadds\tr5, r4, r5\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n-\tstr.w\tr5, [r7, #496]\t@ 0x1f0\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n+\tstr.w\tr5, [r7, #664]\t@ 0x298\n \tcmp\tr5, r4\n-\tbge.n\tf220 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x14f8>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tr5, r4\n-\tstr.w\tr5, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr5, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n+\tittt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tr5, r5, r4\n+\tstrlt.w\tr5, [r7, #664]\t@ 0x298\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n+\tldr.w\tr5, [r7, #664]\t@ 0x298\n \tadd\tr4, r5\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n-\tstr.w\tr4, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n+\tstr.w\tr4, [r7, #656]\t@ 0x290\n \tcmp\tr4, r5\n-\tbge.n\tf240 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1518>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tadd\tr4, r5\n-\tstr.w\tr4, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n+\tittt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tstrlt.w\tr4, [r7, #656]\t@ 0x290\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n+\tldr.w\tr5, [r7, #656]\t@ 0x290\n \tadd.w\tip, r4, r5\n-\tldr.w\tr4, [r7, #592]\t@ 0x250\n+\tldr.w\tr4, [r7, #776]\t@ 0x308\n+\tldr.w\tr5, [r7, #776]\t@ 0x308\n \tcmp\tip, r4\n-\tbge.n\tf25a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1532>\n-\tldr.w\tr4, [r7, #596]\t@ 0x254\n-\tadd\tip, r4\n-\tldr.w\tr4, [r7, #588]\t@ 0x24c\n-\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\titt\tlt\n+\tldrlt.w\tr4, [r7, #780]\t@ 0x30c\n+\taddlt\tip, r4\n+\tldr.w\tr4, [r7, #772]\t@ 0x304\n \tadd\tr4, ip\n \tcmp\tr4, r5\n-\tbge.n\tf26e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1546>\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tadd\tr4, r5\n-\tldr.w\tr5, [r7, #372]\t@ 0x174\n+\titt\tlt\n+\tldrlt.w\tr5, [r7, #780]\t@ 0x30c\n+\taddlt\tr4, r4, r5\n+\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n \tcmp\tr5, #0\n-\tbne.w\tfd34 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x200c>\n-\tldr.w\tr5, [r7, #568]\t@ 0x238\n+\tbne.w\t108e4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x212c>\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n \tcmp\tr5, #0\n-\tble.w\tfc1e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ef6>\n-\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tble.w\t107a6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1fee>\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n \tlsls\tr3, r3, #3\n \tmov.w\tsl, sl, lsl #3\n \tmov.w\tr9, r9, lsl #3\n-\tmov.w\tr8, r8, lsl #3\n \tlsls\tr1, r1, #3\n+\tstr.w\tsl, [r7, #212]\t@ 0xd4\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr5, [r7, #584]\t@ 0x248\n+\tstr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr5, [r7, #728]\t@ 0x2d8\n+\tmov.w\tr8, r8, lsl #3\n+\tstr.w\tr9, [r7, #216]\t@ 0xd8\n \tmov.w\tip, ip, lsl #3\n-\tstr.w\tsl, [r7, #188]\t@ 0xbc\n+\tstr.w\tr1, [r7, #280]\t@ 0x118\n \tlsls\tr0, r0, #3\n-\tstr.w\tr9, [r7, #192]\t@ 0xc0\n-\tlsls\tr2, r2, #3\n-\tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #576]\t@ 0x240\n-\tldr.w\tr5, [r7, #560]\t@ 0x230\n-\tstr.w\tr8, [r7, #196]\t@ 0xc4\n-\tstr.w\tr1, [r7, #232]\t@ 0xe8\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #584]\t@ 0x248\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n-\tstr.w\tr3, [r7, #408]\t@ 0x198\n-\tstr.w\tip, [r7, #228]\t@ 0xe4\n-\tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #176]\t@ 0xb0\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n-\tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #180]\t@ 0xb4\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n+\tstr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tlsls\tr2, r2, #3\n+\tstr.w\tr3, [r7, #512]\t@ 0x200\n+\tstr.w\tr8, [r7, #220]\t@ 0xdc\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #184]\t@ 0xb8\n-\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n+\tstr.w\tr5, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tstr.w\tip, [r7, #272]\t@ 0x110\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #200]\t@ 0xc8\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\tldr.w\tr5, [r7, #632]\t@ 0x278\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #204]\t@ 0xcc\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #208]\t@ 0xd0\n-\tldr.w\tr5, [r7, #520]\t@ 0x208\n+\tldr.w\tr5, [r7, #624]\t@ 0x270\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #212]\t@ 0xd4\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr5, [r7, #224]\t@ 0xe0\n+\tldr.w\tr5, [r7, #688]\t@ 0x2b0\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #216]\t@ 0xd8\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tstr.w\tr5, [r7, #228]\t@ 0xe4\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n+\tlsls\tr5, r5, #3\n+\tstr.w\tr5, [r7, #232]\t@ 0xe8\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #220]\t@ 0xdc\n-\tldr.w\tr5, [r7, #512]\t@ 0x200\n+\tstr.w\tr5, [r7, #236]\t@ 0xec\n+\tldr.w\tr5, [r7, #656]\t@ 0x290\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #224]\t@ 0xe0\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr8, [r7, #372]\t@ 0x174\n+\tstr.w\tr5, [r7, #240]\t@ 0xf0\n+\tldr.w\tr5, [r7, #616]\t@ 0x268\n+\tlsls\tr5, r5, #3\n+\tstr.w\tr5, [r7, #244]\t@ 0xf4\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tlsls\tr5, r5, #3\n+\tstr.w\tr5, [r7, #264]\t@ 0x108\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr9, [r7, #464]\t@ 0x1d0\n \tlsls\tr1, r3, #3\n-\tstr.w\tr1, [r7, #236]\t@ 0xec\n+\tstr.w\tr1, [r7, #288]\t@ 0x120\n \tlsls\tr1, r4, #3\n-\tstr.w\tr1, [r7, #240]\t@ 0xf0\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tadd.w\tr4, fp, r0\n-\tldr.w\tr3, [r7, #576]\t@ 0x240\n-\tadd\tr0, lr\n-\tstr.w\tr0, [r7, #544]\t@ 0x220\n-\tadd.w\tr0, fp, r5\n-\tlsls\tr1, r1, #3\n-\tstr.w\tr1, [r7, #244]\t@ 0xf4\n-\tldr.w\tr1, [r7, #580]\t@ 0x244\n-\tstr.w\tr0, [r7, #520]\t@ 0x208\n-\tadd.w\tr0, lr, r5\n-\tstr.w\tr0, [r7, #552]\t@ 0x228\n-\tadd.w\tr0, fp, r3\n-\tstr.w\tr0, [r7, #528]\t@ 0x210\n-\tadd.w\tr0, lr, r3\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tstr.w\tr1, [r7, #296]\t@ 0x128\n+\tldr.w\tr1, [r7, #668]\t@ 0x29c\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n+\tvldr\td7, [r7, #744]\t@ 0x2e8\n \tlsls\tr1, r1, #3\n-\tstr.w\tr4, [r7, #512]\t@ 0x200\n-\tadd.w\tsl, fp, r1\n-\tadd.w\tr4, fp, r3\n-\tadd.w\tr9, lr, r3\n-\tldr.w\tr3, [r7, #408]\t@ 0x198\n-\tstr.w\tr4, [r7, #536]\t@ 0x218\n-\tadd.w\tr4, fp, r2\n-\tadd\tr3, fp\n+\tstr.w\tr1, [r7, #300]\t@ 0x12c\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n+\tlsls\tr4, r1, #3\n+\tadd.w\tr1, fp, r0\n+\tstr.w\tr1, [r7, #668]\t@ 0x29c\n+\tadd.w\tr1, lr, r0\n+\tstr.w\tr1, [r7, #516]\t@ 0x204\n+\tadd.w\tr1, fp, r5\n+\tstr.w\tr1, [r7, #672]\t@ 0x2a0\n+\tadd.w\tr1, lr, r5\n+\tstr.w\tr1, [r7, #688]\t@ 0x2b0\n+\tadd.w\tr1, fp, r3\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tadd.w\tsl, fp, r4\n+\tstr.w\tr1, [r7, #520]\t@ 0x208\n+\tadd.w\tr0, fp, r2\n+\tadd.w\tr1, fp, r3\n+\tstr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tadd.w\tr1, lr, r3\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n \tadd\tr2, lr\n-\tstr.w\tr3, [r7, #416]\t@ 0x1a0\n+\tstr.w\tr4, [r7, #196]\t@ 0xc4\n+\tadd\tr3, fp\n+\tstr.w\tr0, [r7, #704]\t@ 0x2c0\n+\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n \tmovs\tr3, #1\n-\tstr.w\tr1, [r7, #172]\t@ 0xac\n-\tstr.w\tr4, [r7, #412]\t@ 0x19c\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n-\tstr.w\tr0, [r7, #504]\t@ 0x1f8\n-\tstr.w\tr6, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n-\tldr.w\tr1, [r7, #520]\t@ 0x208\n-\tldr.w\tr0, [r7, #528]\t@ 0x210\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n-\tvldr\td19, [r3, #-8]\n-\tvldr\td20, [r1, #-8]\n-\tvldr\td17, [r0, #-8]\n-\tvldr\td16, [r5, #-8]\n-\tvadd.f64\td22, d19, d20\n-\tldr.w\tr0, [r7, #544]\t@ 0x220\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n-\tvsub.f64\td19, d19, d20\n-\tvadd.f64\td21, d17, d16\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tvldr\td28, [sl, #-8]\n-\tvsub.f64\td17, d17, d16\n-\tvldr\td18, [r0, #-8]\n-\tvldr\td20, [r5, #-8]\n-\tvadd.f64\td24, d22, d21\n-\tvldr\td27, [r9, #-8]\n-\tvldr\td16, [r1, #-8]\n-\tvmul.f64\td23, d9, d17\n-\tvadd.f64\td26, d18, d20\n-\tvsub.f64\td18, d18, d20\n-\tvmov.f64\td20, d28\n-\tldr.w\tr2, [r7, #172]\t@ 0xac\n-\tvfms.f64\td20, d24, d5\n-\tldr.w\tr0, [r7, #412]\t@ 0x19c\n-\tvsub.f64\td22, d22, d21\n-\tvadd.f64\td24, d24, d28\n-\tvadd.f64\td21, d16, d27\n-\tadd.w\tr3, r8, r2\n-\tadd\tr3, lr\n-\tvsub.f64\td16, d16, d27\n-\tvmul.f64\td17, d8, d17\n-\tvmov.f64\td27, d23\n-\tvldr\td25, [r0, #-8]\n-\tvfma.f64\td17, d9, d19\n-\tvstr\td24, [sl, #-8]\n-\tvfma.f64\td23, d19, d12\n-\tvldr\td24, [r3, #-8]\n-\tvfnms.f64\td27, d8, d19\n-\tvadd.f64\td19, d26, d21\n-\tvsub.f64\td21, d26, d21\n-\tvmov.f64\td26, d20\n-\tvfma.f64\td20, d22, d11\n-\tvfma.f64\td26, d10, d22\n-\tvmov.f64\td22, d24\n-\tldr.w\tr5, [r7, #420]\t@ 0x1a4\n-\tvfms.f64\td22, d19, d5\n-\tvadd.f64\td19, d19, d24\n-\tldr.w\tr4, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tvldr\td28, [r5, #-8]\n-\tvstr\td19, [r3, #-8]\n-\tvmul.f64\td19, d9, d16\n-\tvmul.f64\td16, d8, d16\n-\tadds\tr1, #1\n-\tvfma.f64\td16, d9, d18\n-\tstr.w\tr1, [r7, #560]\t@ 0x230\n-\tldr.w\tr1, [r7, #584]\t@ 0x248\n-\tvmov.f64\td24, d22\n-\tvfma.f64\td22, d21, d11\n-\tvfma.f64\td24, d10, d21\n-\tvmov.f64\td21, d19\n-\tvfnms.f64\td21, d8, d18\n-\tvfma.f64\td19, d18, d12\n-\tvldr\td29, [r4, #-8]\n-\tadds\tr2, r0, r1\n-\tadd\tsl, r1\n-\tvadd.f64\td27, d27, d22\n-\tvadd.f64\td18, d17, d24\n-\tvsub.f64\td17, d24, d17\n-\tvadd.f64\td19, d20, d19\n-\tvadd.f64\td20, d20, d21\n-\tvadd.f64\td21, d22, d23\n-\tvstr\td17, [r7, #384]\t@ 0x180\n-\tvsub.f64\td17, d26, d16\n-\tvadd.f64\td16, d26, d16\n-\tvstr\td20, [r7, #376]\t@ 0x178\n-\tvstr\td21, [r7, #352]\t@ 0x160\n-\tvstr\td16, [r7, #392]\t@ 0x188\n-\tstr.w\tr2, [r7, #412]\t@ 0x19c\n-\tadds\tr2, r4, r1\n-\tstr.w\tr2, [r7, #416]\t@ 0x1a0\n-\tldr.w\tr2, [r7, #176]\t@ 0xb0\n-\tvstr\td17, [r0, #-8]\n-\tadd.w\tr3, r2, r8\n-\tldr.w\tr2, [r7, #180]\t@ 0xb4\n-\tvstr\td19, [r4, #-8]\n-\tadd.w\tr4, r2, r8\n-\tldr.w\tr2, [r7, #184]\t@ 0xb8\n-\tadd.w\tr6, fp, r4\n-\tadd.w\tr0, r2, r8\n-\tldr.w\tr2, [r7, #188]\t@ 0xbc\n-\tadd.w\tr1, r2, r8\n-\tadd.w\tr2, fp, r3\n-\tstr.w\tr2, [r7, #260]\t@ 0x104\n+\tstr.w\tr2, [r7, #536]\t@ 0x218\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tstr.w\tr1, [r7, #664]\t@ 0x298\n+\tvstr\td7, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tvmov.f64\td11, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr1, [r7, #196]\t@ 0xc4\n+\tldr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tadd.w\tr2, r9, r1\n+\tldr.w\tr1, [r7, #200]\t@ 0xc8\n+\tvldr\td6, [r3, #-8]\n+\tadd\tr2, lr\n+\tadd.w\tr3, r1, r9\n+\tldr.w\tr1, [r7, #204]\t@ 0xcc\n+\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tadd.w\tr5, r1, r9\n+\tldr.w\tr1, [r7, #208]\t@ 0xd0\n+\tadds\tr4, #1\n+\tstr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tadd.w\tr4, r1, r9\n+\tldr.w\tr1, [r7, #212]\t@ 0xd4\n+\tvldr\td9, [r0, #-8]\n+\tadd.w\tip, fp, r4\n+\tadd.w\tr0, r1, r9\n+\tadd.w\tr1, fp, r3\n \tadd\tr3, lr\n-\tvldr\td19, [r2, #-8]\n-\tmov\tr2, r6\n-\tadd.w\tr6, lr, r4\n-\tstr.w\tr2, [r7, #264]\t@ 0x108\n-\tmov\tr4, r6\n-\tadd.w\tr6, fp, r0\n-\tvldr\td16, [r2, #-8]\n-\tmov\tr2, r6\n-\tadd.w\tr6, lr, r0\n-\tstr.w\tr6, [r7, #432]\t@ 0x1b0\n-\tadd.w\tr6, fp, r1\n-\tstr.w\tr2, [r7, #268]\t@ 0x10c\n-\tmov\tr0, r6\n-\tvadd.f64\td17, d19, d16\n-\tvsub.f64\td19, d19, d16\n-\tvldr\td16, [r2, #-8]\n-\tadd.w\tr6, lr, r1\n-\tstr.w\tr0, [r7, #272]\t@ 0x110\n-\tvldr\td21, [r0, #-8]\n-\tmov\tr2, r6\n-\tldr.w\tr6, [r7, #408]\t@ 0x198\n-\tstr.w\tr4, [r7, #280]\t@ 0x118\n-\tvadd.f64\td20, d16, d21\n-\tvsub.f64\td16, d16, d21\n-\tvmov.f64\td21, d25\n-\tadd.w\tr1, r8, r6\n-\tadd\tr1, lr\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\tstr.w\tr2, [r7, #284]\t@ 0x11c\n-\tvadd.f64\td24, d17, d20\n-\tvmul.f64\td7, d9, d16\n-\tvldr\td30, [r1, #-8]\n-\tvsub.f64\td17, d17, d20\n-\tvstr\td18, [r5, #-8]\n-\tadds\tr6, r5, r6\n-\tldr.w\tr5, [r7, #432]\t@ 0x1b0\n-\tvmul.f64\td16, d8, d16\n-\tvfms.f64\td21, d24, d5\n-\tstr.w\tr6, [r7, #420]\t@ 0x1a4\n-\tldr.w\tr6, [r7, #192]\t@ 0xc0\n-\tvmov.f64\td31, d7\n-\tvstr\td27, [r1, #-8]\n-\tvfma.f64\td16, d9, d19\n-\tadd.w\tip, r6, r8\n-\tldr.w\tr6, [r7, #196]\t@ 0xc4\n-\tvldr\td18, [r4, #-8]\n-\tvfma.f64\td7, d19, d12\n-\tvldr\td23, [r2, #-8]\n-\tvfnms.f64\td31, d8, d19\n-\tvldr\td19, [r3, #-8]\n-\tvadd.f64\td24, d25, d24\n-\tvmov.f64\td22, d21\n-\tvfma.f64\td21, d17, d11\n-\tvfma.f64\td22, d10, d17\n-\tvldr\td17, [r5, #-8]\n-\tadd.w\tr5, r6, r8\n-\tldr.w\tr6, [r7, #200]\t@ 0xc8\n-\tvadd.f64\td20, d19, d18\n-\tvsub.f64\td19, d19, d18\n-\tadd.w\tr4, r6, r8\n-\tldr.w\tr6, [r7, #204]\t@ 0xcc\n-\tvadd.f64\td18, d17, d23\n-\tadd.w\tr0, r6, r8\n-\tldr.w\tr6, [r7, #208]\t@ 0xd0\n-\tvsub.f64\td17, d17, d23\n-\tadd.w\tr1, r6, r8\n-\tadd.w\tr6, fp, ip\n-\tmov\tr2, r6\n-\tadd.w\tr6, lr, ip\n-\tstr.w\tr6, [r7, #336]\t@ 0x150\n-\tadd.w\tr6, lr, r0\n-\tstr.w\tr6, [r7, #304]\t@ 0x130\n-\tadd.w\tr6, fp, r1\n-\tstr.w\tr6, [r7, #292]\t@ 0x124\n-\tadd.w\tr6, lr, r1\n-\tstr.w\tr6, [r7, #444]\t@ 0x1bc\n+\tstr.w\tr3, [r7, #568]\t@ 0x238\n+\tadd.w\tr3, fp, r5\n+\tstr.w\tr3, [r7, #540]\t@ 0x21c\n+\tldr.w\tr3, [r7, #216]\t@ 0xd8\n+\tvadd.f64\td5, d6, d9\n+\tstr.w\tip, [r7, #544]\t@ 0x220\n+\tadd.w\tip, lr, r4\n+\tstr.w\tip, [r7, #576]\t@ 0x240\n+\tadd.w\tip, fp, r0\n+\tstr.w\tip, [r7, #548]\t@ 0x224\n+\tadd.w\tip, lr, r0\n+\tldr.w\tr0, [r7, #512]\t@ 0x200\n+\tadd.w\tr8, r3, r9\n+\tldr.w\tr3, [r7, #220]\t@ 0xdc\n+\tvsub.f64\td9, d6, d9\n+\tadd\tr0, r9\n+\tstr.w\tip, [r7, #584]\t@ 0x248\n+\tadd.w\tip, lr, r0\n+\tstr.w\tip, [r7, #496]\t@ 0x1f0\n+\tadd.w\tip, r3, r9\n+\tldr.w\tr3, [r7, #224]\t@ 0xe0\n+\tstr.w\tr1, [r7, #528]\t@ 0x210\n+\tadd.w\tr1, lr, r5\n+\tadd.w\tr5, r3, r9\n+\tldr.w\tr3, [r7, #228]\t@ 0xe4\n+\tvldr\td13, [r2, #-8]\n+\tvmul.f64\td12, d15, d9\n+\tadd.w\tr4, r3, r9\n+\tldr.w\tr3, [r7, #232]\t@ 0xe8\n+\tstr.w\tr1, [r7, #600]\t@ 0x258\n+\tadd.w\tr0, r3, r9\n+\tadd.w\tr3, fp, r8\n+\tadd\tr8, lr\n+\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tstr.w\tr8, [r7, #592]\t@ 0x250\n+\tadd.w\tr8, fp, ip\n+\tadd\tip, lr\n+\tstr.w\tr8, [r7, #560]\t@ 0x230\n+\tstr.w\tip, [r7, #344]\t@ 0x158\n \tadd.w\tip, fp, r5\n-\tldr.w\tr6, [r7, #212]\t@ 0xd4\n-\tstr.w\tip, [r7, #424]\t@ 0x1a8\n+\tstr.w\tip, [r7, #604]\t@ 0x25c\n \tadd.w\tip, lr, r5\n-\tadd.w\tr5, r6, r8\n-\tldr.w\tr6, [r7, #216]\t@ 0xd8\n-\tstr.w\tip, [r7, #288]\t@ 0x120\n+\tstr.w\tip, [r7, #616]\t@ 0x268\n+\tadd.w\tip, lr, r4\n+\tstr.w\tip, [r7, #624]\t@ 0x270\n+\tadd.w\tip, fp, r0\n+\tstr.w\tip, [r7, #608]\t@ 0x260\n+\tadd.w\tip, lr, r0\n+\tldr.w\tr0, [r7, #236]\t@ 0xec\n+\tadd.w\tr8, fp, r4\n+\tstr.w\tip, [r7, #632]\t@ 0x278\n+\tadd.w\tip, r0, r9\n+\tldr.w\tr0, [r7, #240]\t@ 0xf0\n+\tadd.w\tr3, fp, ip\n+\tadd\tip, lr\n+\tadd.w\tr5, r0, r9\n+\tldr.w\tr0, [r7, #244]\t@ 0xf4\n+\tstr.w\tip, [r7, #368]\t@ 0x170\n+\tadd.w\tip, fp, r5\n+\tadd.w\tr4, r0, r9\n+\tldr.w\tr0, [r7, #264]\t@ 0x108\n+\tstr.w\tip, [r7, #360]\t@ 0x168\n+\tadd.w\tip, lr, r5\n+\tadd\tr0, r9\n+\tstr.w\tip, [r7, #376]\t@ 0x178\n \tadd.w\tip, fp, r4\n-\tstr.w\tip, [r7, #436]\t@ 0x1b4\n+\tstr.w\tip, [r7, #640]\t@ 0x280\n \tadd.w\tip, lr, r4\n-\tadd.w\tr4, r6, r8\n-\tldr.w\tr6, [r7, #220]\t@ 0xdc\n-\tstr.w\tip, [r7, #300]\t@ 0x12c\n+\tstr.w\tip, [r7, #656]\t@ 0x290\n \tadd.w\tip, fp, r0\n-\tadd.w\tr0, r6, r8\n-\tldr.w\tr6, [r7, #224]\t@ 0xe0\n-\tadd.w\tr1, r6, r8\n-\tadd.w\tr6, fp, r5\n-\tstr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tadd.w\tr6, lr, r5\n-\tadd.w\tr5, fp, r0\n \tadd\tr0, lr\n-\tstr.w\tr5, [r7, #464]\t@ 0x1d0\n-\tadd.w\tr5, lr, r1\n-\tstr.w\tr0, [r7, #576]\t@ 0x240\n-\tadd.w\tr0, fp, r1\n-\tldr.w\tr1, [r7, #232]\t@ 0xe8\n-\tstr.w\tr0, [r7, #308]\t@ 0x134\n-\tadd.w\tr0, r1, r8\n-\tldr.w\tr1, [r7, #228]\t@ 0xe4\n-\tstr.w\tr6, [r7, #448]\t@ 0x1c0\n-\tadd.w\tr6, fp, r4\n-\tadd\tr1, r8\n-\tstr.w\tr6, [r7, #296]\t@ 0x128\n-\tadd.w\tr6, lr, r4\n+\tstr.w\tr0, [r7, #412]\t@ 0x19c\n+\tldr.w\tr0, [r7, #280]\t@ 0x118\n+\tstr.w\tr3, [r7, #352]\t@ 0x160\n+\tadd.w\tr4, r0, r9\n+\tldr.w\tr0, [r7, #272]\t@ 0x110\n+\tadd.w\tr1, fp, r4\n+\tadd\tr4, lr\n+\tadd\tr0, r9\n+\tstr.w\tr4, [r7, #472]\t@ 0x1d8\n \tadd.w\tr4, fp, r0\n \tadd\tr0, lr\n-\tstr.w\tr0, [r7, #312]\t@ 0x138\n-\tadd.w\tr0, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #488]\t@ 0x1e8\n-\tldr.w\tr1, [r7, #236]\t@ 0xec\n \tstr.w\tr0, [r7, #468]\t@ 0x1d4\n-\tadd.w\tr0, r1, r8\n-\tldr.w\tr1, [r7, #240]\t@ 0xf0\n-\tstr.w\tr6, [r7, #456]\t@ 0x1c8\n-\tadd\tr1, r8\n-\tstr.w\tr4, [r7, #472]\t@ 0x1d8\n-\tadd.w\tr4, fp, r0\n-\tstr.w\tr4, [r7, #320]\t@ 0x140\n-\tadd.w\tr4, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr4, [r7, #328]\t@ 0x148\n+\tldr.w\tr0, [r7, #288]\t@ 0x120\n+\tstr.w\tr4, [r7, #384]\t@ 0x180\n+\tadd.w\tr4, r0, r9\n+\tstr.w\tr1, [r7, #392]\t@ 0x188\n+\tadd.w\tr1, fp, r4\n+\tstr.w\tr1, [r7, #480]\t@ 0x1e0\n+\tldr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tadd\tr4, lr\n+\tldr.w\tr0, [r7, #296]\t@ 0x128\n+\tadd\tr0, r9\n+\tvldr\td0, [r1, #-8]\n+\tadd.w\tr3, fp, r0\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n \tadd\tr0, lr\n-\tstr.w\tr1, [r7, #404]\t@ 0x194\n-\tldr.w\tr1, [r7, #244]\t@ 0xf4\n-\tvldr\td23, [r2, #-8]\n-\tadd\tr1, r8\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\tadd.w\tr4, fp, r1\n-\tstr.w\tr4, [r7, #400]\t@ 0x190\n-\tldr.w\tr4, [r7, #512]\t@ 0x200\n-\tadd\tr1, lr\n-\tstr.w\tr2, [r7, #276]\t@ 0x114\n-\tadd\tr8, r6\n-\tadds\tr2, r4, r6\n-\tstr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr6, [r7, #424]\t@ 0x1a8\n-\tvstr\td24, [r4, #-8]\n-\tvadd.f64\td24, d20, d18\n-\tvsub.f64\td20, d20, d18\n-\tvmul.f64\td18, d9, d17\n-\tvmul.f64\td17, d8, d17\n-\tldr.w\tr1, [r7, #336]\t@ 0x150\n-\tvfma.f64\td17, d9, d19\n-\tldr.w\tr4, [r7, #544]\t@ 0x220\n-\tstr.w\tr2, [r7, #512]\t@ 0x200\n-\tvmov.f64\td25, d18\n-\tvfma.f64\td18, d19, d12\n-\tvfnms.f64\td25, d8, d19\n-\tvmov.f64\td19, d28\n-\tvfms.f64\td19, d24, d5\n-\tvadd.f64\td28, d28, d24\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tvldr\td27, [r6, #-8]\n-\tvldr\td26, [r1, #-8]\n-\tadds\tr2, r4, r2\n-\tvsub.f64\td24, d22, d17\n-\tldr.w\tr6, [r7, #424]\t@ 0x1a8\n-\tvstr\td28, [r4, #-8]\n-\tvadd.f64\td22, d22, d17\n-\tvadd.f64\td18, d21, d18\n-\tldr.w\tr4, [r7, #276]\t@ 0x114\n-\tvadd.f64\td25, d21, d25\n-\tstr.w\tr2, [r7, #544]\t@ 0x220\n-\tvmov.f64\td21, d19\n-\tvfma.f64\td19, d20, d11\n-\tvfma.f64\td21, d10, d20\n-\tldr.w\tr2, [r7, #260]\t@ 0x104\n-\tvstr\td22, [r7, #336]\t@ 0x150\n-\tvstr\td24, [r2, #-8]\n-\tvstr\td18, [r4, #-8]\n-\tldr.w\tr2, [r7, #292]\t@ 0x124\n-\tvstr\td25, [r6, #-8]\n-\tvadd.f64\td31, d31, d19\n-\tldr.w\tr6, [r7, #436]\t@ 0x1b4\n-\tvsub.f64\td24, d21, d16\n-\tldr.w\tr4, [r7, #288]\t@ 0x120\n-\tvadd.f64\td19, d19, d7\n-\tvadd.f64\td16, d16, d21\n-\tvldr\td17, [r2, #-8]\n-\tvldr\td22, [ip, #-8]\n-\tvldr\td18, [r6, #-8]\n-\tvldr\td28, [r4, #-8]\n-\tvstr\td24, [r7, #424]\t@ 0x1a8\n-\tvadd.f64\td21, d23, d18\n-\tvstr\td16, [r3, #-8]\n-\tvstr\td31, [r1, #-8]\n-\tvsub.f64\td16, d22, d17\n-\tvstr\td19, [r4, #-8]\n-\tvadd.f64\td19, d22, d17\n-\tldr.w\tr6, [r7, #440]\t@ 0x1b8\n-\tvsub.f64\td18, d23, d18\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tvmul.f64\td6, d9, d16\n-\tldr.w\tr1, [r7, #296]\t@ 0x128\n-\tvadd.f64\td17, d21, d19\n-\tvsub.f64\td19, d21, d19\n-\tvmov.f64\td21, d29\n-\tvldr\td20, [r6, #-8]\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\tvmov.f64\td7, d6\n-\tvfma.f64\td6, d18, d12\n-\tvfms.f64\td21, d17, d5\n-\tvadd.f64\td29, d29, d17\n-\tadds\tr4, r3, r6\n-\tldr.w\tr6, [r7, #304]\t@ 0x130\n-\tstr.w\tr4, [r7, #528]\t@ 0x210\n-\tvmul.f64\td17, d8, d16\n-\tldr.w\tr4, [r7, #300]\t@ 0x12c\n-\tvfma.f64\td17, d9, d18\n-\tvstr\td29, [r3, #-8]\n-\tvfnms.f64\td7, d8, d18\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvldr\td24, [r6, #-8]\n-\tvldr\td16, [r4, #-8]\n-\tvmov.f64\td22, d21\n-\tvfma.f64\td21, d19, d11\n-\tvfma.f64\td22, d10, d19\n-\tvldr\td19, [r3, #-8]\n-\tvsub.f64\td23, d26, d16\n-\tldr.w\tr3, [r7, #448]\t@ 0x1c0\n-\tvadd.f64\td16, d26, d16\n-\tvldr\td31, [r1, #-8]\n-\tvsub.f64\td18, d24, d19\n-\tvadd.f64\td19, d24, d19\n-\tvldr\td29, [r3, #-8]\n-\tldr.w\tr3, [r7, #268]\t@ 0x10c\n-\tvmul.f64\td24, d9, d18\n-\tvmul.f64\td18, d8, d18\n-\tvfma.f64\td18, d9, d23\n-\tvmov.f64\td25, d24\n-\tvfma.f64\td24, d23, d12\n-\tvfnms.f64\td25, d8, d23\n-\tvadd.f64\td24, d21, d24\n-\tvadd.f64\td25, d21, d25\n-\tvadd.f64\td21, d16, d19\n-\tvsub.f64\td16, d16, d19\n-\tvsub.f64\td19, d22, d18\n-\tvadd.f64\td22, d22, d18\n-\tvmov.f64\td18, d30\n-\tvfms.f64\td18, d21, d5\n-\tvadd.f64\td30, d30, d21\n-\tvstr\td19, [r3, #-8]\n-\tldr.w\tr3, [r7, #440]\t@ 0x1b8\n-\tvstr\td22, [r1, #-8]\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tvstr\td24, [ip, #-8]\n-\tvstr\td25, [r3, #-8]\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvstr\td30, [r1, #-8]\n-\tvmov.f64\td21, d18\n-\tvfma.f64\td21, d10, d16\n-\tvfma.f64\td18, d16, d11\n-\tvldr\td30, [r3, #-8]\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n-\tadd\tr1, r3\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tstr.w\tr1, [r7, #504]\t@ 0x1f8\n-\tvadd.f64\td24, d17, d21\n-\tvadd.f64\td7, d7, d18\n-\tvldr\td16, [r3, #-8]\n-\tvsub.f64\td21, d21, d17\n-\tldr.w\tr1, [r7, #308]\t@ 0x134\n-\tvadd.f64\td18, d18, d6\n-\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n-\tvldr\td23, [r1, #-8]\n-\tvldr\td19, [r3, #-8]\n-\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n-\tvsub.f64\td17, d20, d23\n-\tvstr\td24, [r3, #-8]\n-\tldr.w\tr3, [r7, #456]\t@ 0x1c8\n-\tvmul.f64\td26, d9, d17\n-\tvmul.f64\td17, d8, d17\n-\tvstr\td21, [r3, #-8]\n-\tvadd.f64\td21, d20, d23\n-\tvstr\td7, [r6, #-8]\n-\tldr.w\tr6, [r7, #448]\t@ 0x1c0\n-\tvldr\td20, [r7, #376]\t@ 0x178\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tvstr\td18, [r6, #-8]\n-\tvadd.f64\td18, d27, d16\n-\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvsub.f64\td16, d27, d16\n-\tvadd.f64\td23, d18, d21\n-\tvsub.f64\td21, d18, d21\n-\tvldr\td22, [r6, #-8]\n-\tvfma.f64\td17, d9, d16\n-\tldr.w\tr6, [r7, #472]\t@ 0x1d8\n-\tvadd.f64\td18, d23, d19\n-\tvfms.f64\td19, d23, d5\n-\tvstr\td20, [r6, #-8]\n-\tldr.w\tr6, [r7, #576]\t@ 0x240\n-\tvstr\td18, [r3, #-8]\n-\tvldr\td18, [r5, #-8]\n-\tvldr\td20, [r6, #-8]\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\tvmov.f64\td23, d19\n-\tvfma.f64\td23, d10, d21\n-\tvfma.f64\td19, d21, d11\n-\tvadd.f64\td24, d28, d20\n-\tvsub.f64\td20, d28, d20\n-\tvmov.f64\td28, d26\n-\tvfma.f64\td26, d16, d12\n-\tvadd.f64\td21, d29, d18\n-\tadds\tr6, r3, r6\n-\tldr.w\tr3, [r7, #488]\t@ 0x1e8\n-\tvfnms.f64\td28, d8, d16\n-\tvsub.f64\td18, d29, d18\n-\tstr.w\tr6, [r7, #536]\t@ 0x218\n-\tldr.w\tr6, [r7, #312]\t@ 0x138\n-\tvldr\td16, [r3, #-8]\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n-\tvmov.f64\td29, d26\n-\tvldr\td26, [r7, #352]\t@ 0x160\n-\tvldr\td25, [r6, #-8]\n-\tvstr\td26, [r6, #-8]\n-\tvadd.f64\td26, d24, d21\n-\tvsub.f64\td21, d24, d21\n-\tvmul.f64\td24, d9, d18\n-\tvmul.f64\td18, d8, d18\n-\tvfma.f64\td18, d9, d20\n-\tvmov.f64\td27, d24\n-\tvfma.f64\td24, d20, d12\n-\tvfnms.f64\td27, d8, d20\n-\tvadd.f64\td24, d19, d24\n-\tvadd.f64\td27, d19, d27\n-\tvmov.f64\td19, d25\n-\tvfms.f64\td19, d26, d5\n-\tvadd.f64\td26, d26, d25\n-\tvsub.f64\td25, d23, d18\n-\tvadd.f64\td23, d23, d18\n-\tvstr\td26, [r9, #-8]\n-\tadd\tr9, r3\n-\tldr.w\tr3, [r7, #272]\t@ 0x110\n-\tvmov.f64\td20, d19\n-\tvfma.f64\td19, d11, d21\n-\tvfma.f64\td20, d10, d21\n-\tvstr\td25, [r3, #-8]\n-\tldr.w\tr3, [r7, #284]\t@ 0x11c\n-\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvldr\td18, [r7, #392]\t@ 0x188\n-\tvstr\td23, [r6, #-8]\n-\tvadd.f64\td28, d28, d19\n-\tvstr\td24, [r2, #-8]\n-\tvadd.f64\td25, d17, d20\n-\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n-\tvsub.f64\td20, d20, d17\n-\tldr.w\tr6, [r7, #328]\t@ 0x148\n-\tvadd.f64\td19, d19, d29\n-\tvstr\td27, [r1, #-8]\n-\tvldr\td24, [r7, #424]\t@ 0x1a8\n-\tvstr\td25, [r3, #-8]\n-\tldr.w\tr3, [r7, #444]\t@ 0x1bc\n-\tvstr\td20, [r2, #-8]\n-\tvldr\td20, [r7, #336]\t@ 0x150\n-\tvldr\td23, [r6, #-8]\n-\tvstr\td28, [r3, #-8]\n-\tldr.w\tr3, [r7, #320]\t@ 0x140\n-\tvstr\td19, [r5, #-8]\n+\tstr.w\tr0, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr0, [r7, #300]\t@ 0x12c\n+\tstr.w\tr3, [r7, #484]\t@ 0x1e4\n+\tvldr\td1, [r1, #-8]\n+\tadd\tr0, r9\n+\tldr.w\tr1, [r7, #516]\t@ 0x204\n+\tadd.w\tr5, fp, r0\n+\tstr.w\tr5, [r7, #504]\t@ 0x1f8\n+\tadd\tr0, lr\n+\tvadd.f64\td4, d0, d1\n+\tvsub.f64\td0, d0, d1\n+\tadd\tr9, r6\n+\tvldr\td2, [r1, #-8]\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr5, [r7, #664]\t@ 0x298\n+\tvldr\td14, [sl, #-8]\n+\tvldr\td10, [r7, #728]\t@ 0x2d8\n+\tvldr\td6, [r3, #-8]\n+\tldr.w\tr3, [r7, #520]\t@ 0x208\n+\tvldr\td7, [r5, #-8]\n+\tvadd.f64\td1, d2, d6\n+\tvsub.f64\td6, d2, d6\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tvldr\td3, [r3, #-8]\n+\tvadd.f64\td2, d3, d7\n+\tvsub.f64\td7, d3, d7\n+\tvadd.f64\td3, d5, d4\n+\tvsub.f64\td5, d5, d4\n+\tvmov.f64\td4, d14\n+\tvmls.f64\td4, d3, d11\n+\tvadd.f64\td14, d3, d14\n+\tvadd.f64\td3, d1, d2\n+\tvsub.f64\td2, d1, d2\n+\tvmul.f64\td5, d5, d10\n+\tvmul.f64\td1, d15, d7\n+\tvmla.f64\td1, d8, d6\n+\tvmul.f64\td7, d8, d7\n+\tvmul.f64\td6, d15, d6\n+\tvmul.f64\td2, d2, d10\n+\tvmov.f64\td10, d13\n+\tvmls.f64\td10, d3, d11\n+\tvmov.f64\td11, d10\n+\tvadd.f64\td10, d3, d13\n+\tvadd.f64\td3, d5, d4\n+\tvsub.f64\td4, d4, d5\n+\tvsub.f64\td5, d7, d6\n+\tvsub.f64\td7, d6, d7\n+\tvmul.f64\td13, d15, d0\n+\tvmul.f64\td0, d8, d0\n+\tvmla.f64\td13, d8, d9\n+\tvldr\td9, [r5, #-8]\n+\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tvadd.f64\td5, d5, d4\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td4, d3, d1\n+\tvstr\td14, [sl, #-8]\n+\tvmov.f64\td14, #80\t@ 0x3e800000 0.250\n+\tadd\tsl, r6\n+\tvstr\td7, [r7, #336]\t@ 0x150\n+\tvsub.f64\td7, d3, d1\n+\tvstr\td4, [r7, #312]\t@ 0x138\n+\tvsub.f64\td1, d12, d0\n+\tvadd.f64\td4, d2, d11\n+\tvsub.f64\td0, d0, d12\n+\tvsub.f64\td11, d11, d2\n+\tvadd.f64\td2, d13, d4\n+\tvadd.f64\td3, d0, d11\n+\tvadd.f64\td1, d1, d11\n+\tvsub.f64\td0, d4, d13\n+\tvmov.f64\td13, d9\n+\tvstr\td3, [r7, #328]\t@ 0x148\n+\tvldr\td3, [r5, #-8]\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tvstr\td3, [r7, #520]\t@ 0x208\n+\tvstr\td7, [r5, #-8]\n+\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tvstr\td5, [r5, #-8]\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tadd\tr5, r6\n+\tstr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tadd\tr5, r6\n+\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tvldr\td3, [r5, #-8]\n+\tldr.w\tr5, [r7, #540]\t@ 0x21c\n+\tvldr\td11, [r5, #-8]\n+\tldr.w\tr5, [r7, #544]\t@ 0x220\n+\tvadd.f64\td5, d3, d11\n+\tvsub.f64\td11, d3, d11\n+\tvldr\td6, [r5, #-8]\n+\tldr.w\tr5, [r7, #548]\t@ 0x224\n+\tvstr\td0, [r7, #304]\t@ 0x130\n+\tvldr\td7, [r5, #-8]\n+\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\tvadd.f64\td3, d6, d7\n+\tvsub.f64\td6, d6, d7\n+\tvldr\td12, [r5, #-8]\n+\tvstr\td10, [r2, #-8]\n \tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tvldr\td28, [r7, #384]\t@ 0x180\n-\tvldr\td19, [r3, #-8]\n-\tvstr\td20, [r3, #-8]\n-\tvadd.f64\td20, d31, d22\n-\tldr.w\tr3, [r7, #400]\t@ 0x190\n-\tvsub.f64\td22, d31, d22\n-\tvadd.f64\td21, d19, d23\n-\tvsub.f64\td19, d19, d23\n-\tldr.w\tr1, [r7, #520]\t@ 0x208\n-\tvldr\td25, [r3, #-8]\n-\tvmul.f64\td26, d9, d22\n-\tvstr\td18, [r3, #-8]\n-\tvadd.f64\td23, d21, d20\n-\tldr.w\tr3, [r7, #404]\t@ 0x194\n-\tvsub.f64\td21, d21, d20\n-\tvldr\td18, [r0, #-8]\n-\tvadd.f64\td20, d30, d16\n-\tvmov.f64\td29, d26\n-\tvfma.f64\td26, d19, d12\n-\tvfnms.f64\td29, d8, d19\n-\tvsub.f64\td16, d30, d16\n-\tvldr\td17, [r3, #-8]\n-\tvstr\td24, [r0, #-8]\n-\tvldr\td24, [r2, #-8]\n-\tvadd.f64\td27, d18, d17\n-\tvstr\td28, [r2, #-8]\n-\tvsub.f64\td18, d18, d17\n-\tvmov.f64\td17, d25\n-\tvfms.f64\td17, d23, d5\n-\tvmul.f64\td28, d8, d22\n-\tvfma.f64\td28, d9, d19\n-\tvadd.f64\td23, d23, d25\n-\tvadd.f64\td22, d27, d20\n-\tvmul.f64\td25, d9, d16\n-\tvmul.f64\td16, d8, d16\n-\tvsub.f64\td20, d27, d20\n-\tvfma.f64\td16, d9, d18\n-\tvmov.f64\td27, d26\n-\tvstr\td23, [r1, #-8]\n-\tvmov.f64\td26, d25\n-\tvfma.f64\td25, d18, d12\n-\tvfnms.f64\td26, d8, d18\n+\tvldr\td10, [r7, #728]\t@ 0x2d8\n+\tvldr\td7, [r2, #-8]\n+\tvstr\td2, [r5, #-8]\n+\tvadd.f64\td2, d5, d3\n+\tvstr\td1, [r2, #-8]\n+\tadds\tr2, r5, r6\n+\tstr.w\tr2, [r7, #536]\t@ 0x218\n+\tvsub.f64\td5, d5, d3\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tvstr\td7, [r7, #496]\t@ 0x1f0\n+\tvmls.f64\td13, d2, d14\n+\tvadd.f64\td9, d9, d2\n+\tvmul.f64\td2, d15, d6\n+\tvmla.f64\td2, d8, d11\n+\tvmul.f64\td5, d5, d10\n+\tvldr\td4, [r2, #-8]\n+\tvmul.f64\td6, d8, d6\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tvldr\td0, [r2, #-8]\n+\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tvstr\td2, [r7, #488]\t@ 0x1e8\n+\tvmul.f64\td2, d15, d11\n+\tvadd.f64\td3, d4, d0\n+\tvsub.f64\td4, d4, d0\n+\tvldr\td7, [r2, #-8]\n \tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td17, d21, d11\n-\tvfma.f64\td19, d10, d21\n-\tvmov.f64\td21, d24\n-\tvfms.f64\td21, d22, d5\n+\tvldr\td1, [r2, #-8]\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tvadd.f64\td0, d7, d1\n+\tvsub.f64\td7, d7, d1\n+\tvadd.f64\td1, d3, d0\n+\tvsub.f64\td3, d3, d0\n+\tvmul.f64\td11, d15, d7\n+\tvadd.f64\td0, d5, d13\n+\tvmla.f64\td11, d8, d4\n+\tvmul.f64\td7, d8, d7\n+\tvmul.f64\td4, d15, d4\n+\tvsub.f64\td5, d13, d5\n+\tvmul.f64\td3, d3, d10\n+\tvmov.f64\td10, d12\n+\tvmls.f64\td10, d1, d14\n+\tvadd.f64\td12, d12, d1\n+\tvldr\td1, [r2, #-8]\n+\tvsub.f64\td13, d2, d6\n+\tldr.w\tr2, [r7, #668]\t@ 0x29c\n+\tvsub.f64\td6, d6, d2\n+\tvsub.f64\td2, d7, d4\n+\tvsub.f64\td7, d4, d7\n+\tvstr\td9, [r2, #-8]\n+\tadd\tr2, r6\n+\tstr.w\tr2, [r7, #668]\t@ 0x29c\n+\tvadd.f64\td9, d0, d11\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tvmov.f64\td14, d10\n+\tvmov.f64\td10, d12\n+\tvadd.f64\td2, d2, d5\n+\tvadd.f64\td7, d7, d5\n+\tvsub.f64\td5, d0, d11\n+\tvstr\td9, [r7, #320]\t@ 0x140\n+\tvldr\td12, [r2, #-8]\n+\tvadd.f64\td4, d3, d14\n+\tldr.w\tr2, [r7, #592]\t@ 0x250\n+\tvsub.f64\td14, d14, d3\n+\tvldr\td0, [r2, #-8]\n+\tmov\tr2, r1\n+\tvstr\td10, [r1, #-8]\n+\tadd\tr2, r6\n+\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tvadd.f64\td13, d13, d14\n+\tstr.w\tr2, [r7, #516]\t@ 0x204\n+\tvadd.f64\td14, d6, d14\n+\tldr.w\tr2, [r7, #608]\t@ 0x260\n+\tldr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tvstr\td5, [r5, #-8]\n \tldr.w\tr5, [r7, #552]\t@ 0x228\n-\tvadd.f64\td22, d22, d24\n-\tadd\tr1, r2\n-\tldr.w\tr0, [r7, #280]\t@ 0x118\n-\tstr.w\tr1, [r7, #520]\t@ 0x208\n-\tldr.w\tr1, [r7, #560]\t@ 0x230\n-\tvstr\td22, [r5, #-8]\n-\tadd\tr5, r2\n-\tldr.w\tr2, [r7, #264]\t@ 0x108\n-\tvadd.f64\td25, d17, d25\n-\tvadd.f64\td17, d17, d26\n-\tstr.w\tr5, [r7, #552]\t@ 0x228\n-\tvmov.f64\td18, d21\n-\tvfma.f64\td21, d20, d11\n-\tvfma.f64\td18, d10, d20\n-\tvsub.f64\td20, d19, d16\n-\tvadd.f64\td19, d19, d16\n-\tvstr\td20, [r2, #-8]\n-\tvstr\td19, [r6, #-8]\n-\tldr.w\tr6, [r7, #436]\t@ 0x1b4\n-\tvadd.f64\td29, d29, d21\n-\tvadd.f64\td21, d21, d27\n-\tvadd.f64\td20, d28, d18\n-\tvsub.f64\td18, d18, d28\n-\tvstr\td25, [r6, #-8]\n-\tldr.w\tr6, [r7, #576]\t@ 0x240\n-\tvstr\td20, [r0, #-8]\n-\tvstr\td18, [r3, #-8]\n-\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n-\tvstr\td29, [r4, #-8]\n-\tvstr\td21, [r6, #-8]\n-\tvstr\td17, [r3, #-8]\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n-\tcmp\tr3, r1\n-\tbne.w\tf3c8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x16a0>\n-\tldr.w\tr6, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr2, [r7, #364]\t@ 0x16c\n-\tadd\tr3, r2\n+\tvldr\td5, [r7, #488]\t@ 0x1e8\n+\tvstr\td2, [r5, #-8]\n+\tvadd.f64\td3, d5, d4\n+\tldr.w\tr5, [r7, #560]\t@ 0x230\n+\tvsub.f64\td2, d4, d5\n+\tvstr\td7, [r5, #-8]\n+\tldr.w\tr5, [r7, #604]\t@ 0x25c\n+\tvldr\td11, [r2, #-8]\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tvldr\td6, [r8, #-8]\n+\tvldr\td9, [r5, #-8]\n+\tldr.w\tr5, [r7, #344]\t@ 0x158\n+\tvadd.f64\td5, d6, d11\n+\tvstr\td2, [r7, #560]\t@ 0x230\n+\tvadd.f64\td4, d1, d9\n+\tvsub.f64\td9, d1, d9\n+\tvsub.f64\td11, d6, d11\n+\tvldr\td10, [r5, #-8]\n+\tvstr\td3, [r2, #-8]\n \tldr.w\tr2, [r7, #592]\t@ 0x250\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tvsub.f64\td7, d4, d5\n+\tvadd.f64\td1, d4, d5\n+\tvldr\td5, [r7, #728]\t@ 0x2d8\n+\tvldr\td3, [r7, #520]\t@ 0x208\n+\tvstr\td13, [r2, #-8]\n+\tvmul.f64\td7, d7, d5\n+\tldr.w\tr2, [r7, #624]\t@ 0x270\n+\tvstr\td14, [r5, #-8]\n+\tvmov.f64\td14, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr5, [r7, #632]\t@ 0x278\n+\tvldr\td2, [r2, #-8]\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvldr\td6, [r5, #-8]\n+\tvldr\td5, [r2, #-8]\n+\tvsub.f64\td4, d2, d6\n+\tvadd.f64\td6, d2, d6\n+\tvmov.f64\td2, d3\n+\tvmls.f64\td2, d1, d14\n+\tldr.w\tr2, [r7, #352]\t@ 0x160\n+\tvadd.f64\td1, d3, d1\n+\tvsub.f64\td3, d0, d5\n+\tvadd.f64\td5, d0, d5\n+\tvldr\td13, [r2, #-8]\n+\tvstr\td1, [r1, #-8]\n+\tvmul.f64\td1, d15, d4\n+\tvadd.f64\td0, d5, d6\n+\tvmla.f64\td1, d8, d3\n+\tvsub.f64\td5, d5, d6\n+\tvldr\td6, [r7, #728]\t@ 0x2d8\n+\tvmul.f64\td4, d8, d4\n+\tvmul.f64\td3, d15, d3\n+\tldr.w\tr5, [r7, #544]\t@ 0x220\n+\tadd\tr1, r6\n+\tstr.w\tr1, [r7, #680]\t@ 0x2a8\n+\tvmul.f64\td14, d5, d6\n+\tvadd.f64\td6, d7, d2\n+\tldr.w\tr1, [r7, #360]\t@ 0x168\n+\tvsub.f64\td2, d2, d7\n+\tvsub.f64\td7, d4, d3\n+\tvsub.f64\td3, d3, d4\n+\tvsub.f64\td5, d6, d1\n+\tvadd.f64\td6, d6, d1\n+\tvldr\td1, [r7, #496]\t@ 0x1f0\n+\tvadd.f64\td7, d7, d2\n+\tvadd.f64\td3, d3, d2\n+\tvmov.f64\td2, #80\t@ 0x3e800000 0.250\n+\tvmov.f64\td4, d1\n+\tvadd.f64\td1, d1, d0\n+\tvmls.f64\td4, d0, d2\n+\tvmul.f64\td2, d15, d11\n+\tvmla.f64\td2, d8, d9\n+\tvmul.f64\td11, d8, d11\n+\tvstr\td1, [r7, #568]\t@ 0x238\n+\tvldr\td1, [r1, #-8]\n+\tvstr\td5, [r5, #-8]\n+\tvmul.f64\td5, d15, d9\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n+\tvstr\td6, [r1, #-8]\n+\tvstr\td7, [r8, #-8]\n+\tvadd.f64\td7, d14, d4\n+\tvstr\td3, [r2, #-8]\n+\tvsub.f64\td4, d4, d14\n+\tvldr\td6, [r5, #-8]\n+\tvldr\td0, [ip, #-8]\n+\tldr.w\tr1, [r7, #392]\t@ 0x188\n+\tvsub.f64\td9, d12, d6\n+\tvadd.f64\td3, d12, d6\n+\tvadd.f64\td6, d13, d0\n+\tvstr\td1, [r7, #592]\t@ 0x250\n+\tvsub.f64\td1, d5, d11\n+\tvsub.f64\td11, d11, d5\n+\tvsub.f64\td0, d13, d0\n+\tvldr\td13, [r1, #-8]\n+\tldr.w\tr5, [r7, #368]\t@ 0x170\n+\tvadd.f64\td5, d3, d6\n+\tvsub.f64\td3, d3, d6\n+\tvldr\td6, [r7, #728]\t@ 0x2d8\n+\tvadd.f64\td1, d1, d4\n+\tvadd.f64\td11, d11, d4\n+\tldr.w\tr2, [r7, #576]\t@ 0x240\n+\tvmul.f64\td12, d3, d6\n+\tvadd.f64\td4, d5, d13\n+\tvmov.f64\td3, d13\n+\tvldr\td13, [r7, #568]\t@ 0x238\n+\tvadd.f64\td6, d2, d7\n+\tvsub.f64\td7, d7, d2\n+\tvmov.f64\td2, #80\t@ 0x3e800000 0.250\n+\tvmls.f64\td3, d5, d2\n+\tvldr\td5, [r5, #-8]\n+\tvstr\td13, [r3, #-8]\n+\tadd\tr3, r6\n+\tstr.w\tr3, [r7, #520]\t@ 0x208\n+\tvmul.f64\td2, d8, d0\n+\tldr.w\tr3, [r7, #376]\t@ 0x178\n+\tvldr\td13, [r3, #-8]\n+\tvstr\td6, [r2, #-8]\n+\tvstr\td7, [r3, #-8]\n+\tldr.w\tr3, [r7, #624]\t@ 0x270\n+\tvstr\td13, [r7, #568]\t@ 0x238\n+\tvmul.f64\td13, d15, d0\n+\tvmla.f64\td13, d8, d9\n+\tvstr\td1, [r3, #-8]\n+\tvmul.f64\td1, d15, d9\n+\tvstr\td11, [r5, #-8]\n+\tvadd.f64\td9, d12, d3\n+\tldr.w\tr2, [r7, #384]\t@ 0x180\n+\tvsub.f64\td3, d3, d12\n+\tvldr\td6, [r7, #336]\t@ 0x150\n+\tvsub.f64\td12, d1, d2\n+\tvsub.f64\td1, d2, d1\n+\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n+\tvldr\td14, [r2, #-8]\n+\tvstr\td6, [r1, #-8]\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tvstr\td12, [r7, #624]\t@ 0x270\n+\tadds\tr3, r1, r6\n+\tstr.w\tr3, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tvstr\td4, [r1, #-8]\n+\tldr.w\tr1, [r7, #472]\t@ 0x1d8\n+\tvldr\td12, [r5, #-8]\n+\tvldr\td7, [r3, #-8]\n+\tldr.w\tr3, [r7, #412]\t@ 0x19c\n+\tvldr\td6, [r1, #-8]\n+\tvadd.f64\td4, d10, d7\n+\tvsub.f64\td7, d10, d7\n+\tvldr\td10, [r7, #328]\t@ 0x148\n+\tvldr\td11, [r3, #-8]\n+\tvstr\td1, [r7, #576]\t@ 0x240\n+\tvstr\td10, [r1, #-8]\n+\tvmul.f64\td1, d15, d7\n+\tvadd.f64\td0, d5, d11\n+\tvsub.f64\td5, d5, d11\n+\tvmov.f64\td11, #80\t@ 0x3e800000 0.250\n+\tvldr\td10, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tvadd.f64\td2, d4, d0\n+\tvsub.f64\td0, d4, d0\n+\tvmov.f64\td4, d6\n+\tvmls.f64\td4, d2, d11\n+\tvmul.f64\td0, d0, d10\n+\tvmul.f64\td11, d15, d5\n+\tvadd.f64\td2, d2, d6\n+\tvmla.f64\td11, d8, d7\n+\tvmul.f64\td5, d8, d5\n+\tvstr\td2, [r1, #-8]\n+\tadd\tr1, r6\n+\tstr.w\tr1, [r7, #664]\t@ 0x298\n+\tldr.w\tr1, [r7, #548]\t@ 0x224\n+\tvsub.f64\td7, d4, d0\n+\tvadd.f64\td6, d0, d4\n+\tvldr\td4, [r7, #624]\t@ 0x270\n+\tvmov.f64\td0, #80\t@ 0x3e800000 0.250\n+\tvadd.f64\td2, d4, d7\n+\tvldr\td4, [r7, #576]\t@ 0x240\n+\tvadd.f64\td7, d4, d7\n+\tvsub.f64\td4, d5, d1\n+\tvsub.f64\td5, d1, d5\n+\tvadd.f64\td4, d4, d3\n+\tvadd.f64\td5, d5, d3\n+\tvsub.f64\td3, d9, d11\n+\tvadd.f64\td9, d9, d11\n+\tvstr\td3, [r1, #-8]\n+\tldr.w\tr1, [r7, #608]\t@ 0x260\n+\tvstr\td9, [r2, #-8]\n+\tvstr\td4, [r1, #-8]\n+\tldr.w\tr1, [r7, #584]\t@ 0x248\n+\tvstr\td5, [ip, #-8]\n+\tvadd.f64\td5, d13, d6\n+\tvsub.f64\td6, d6, d13\n+\tvstr\td5, [r1, #-8]\n+\tldr.w\tr1, [r7, #632]\t@ 0x278\n+\tvstr\td6, [r5, #-8]\n+\tldr.w\tr2, [r7, #484]\t@ 0x1e4\n+\tvldr\td6, [r7, #320]\t@ 0x140\n+\tvstr\td2, [r1, #-8]\n+\tldr.w\tr1, [r7, #480]\t@ 0x1e0\n+\tvldr\td9, [r2, #-8]\n+\tvstr\td7, [r3, #-8]\n+\tvldr\td5, [r7, #568]\t@ 0x238\n+\tvldr\td3, [r1, #-8]\n+\tvstr\td6, [r1, #-8]\n+\tldr.w\tr1, [r7, #508]\t@ 0x1fc\n+\tvadd.f64\td1, d5, d12\n+\tvldr\td4, [r4, #-8]\n+\tvldr\td7, [r7, #592]\t@ 0x250\n+\tvldr\td2, [r7, #560]\t@ 0x230\n+\tvldr\td11, [r1, #-8]\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tvstr\td2, [r4, #-8]\n+\tvadd.f64\td2, d7, d14\n+\tvadd.f64\td6, d4, d11\n+\tvsub.f64\td14, d7, d14\n+\tldr.w\tr4, [r7, #504]\t@ 0x1f8\n+\tvadd.f64\td7, d3, d9\n+\tvsub.f64\td9, d3, d9\n+\tvsub.f64\td3, d5, d12\n+\tvldr\td5, [r7, #312]\t@ 0x138\n+\tvsub.f64\td11, d4, d11\n+\tldr.w\tr5, [r7, #540]\t@ 0x21c\n+\tvldr\td4, [r4, #-8]\n+\tvstr\td5, [r4, #-8]\n+\tvadd.f64\td5, d7, d2\n+\tvsub.f64\td7, d7, d2\n+\tvadd.f64\td2, d6, d1\n+\tvsub.f64\td6, d6, d1\n+\tvmov.f64\td12, d4\n+\tvldr\td1, [r0, #-8]\n+\tvmls.f64\td12, d5, d0\n+\tvadd.f64\td5, d5, d4\n+\tvmul.f64\td7, d7, d10\n+\tvmul.f64\td4, d15, d11\n+\tvmul.f64\td6, d6, d10\n+\tvldr\td10, [r7, #304]\t@ 0x130\n+\tvmov.f64\td13, d1\n+\tvmls.f64\td13, d2, d0\n+\tvadd.f64\td2, d2, d1\n+\tvstr\td10, [r0, #-8]\n+\tldr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tvstr\td2, [r3, #-8]\n+\tvmul.f64\td2, d8, d14\n+\tvadd.f64\td0, d7, d12\n+\tvsub.f64\td7, d12, d7\n+\tvstr\td5, [r0, #-8]\n+\tvmul.f64\td5, d15, d14\n+\tvmla.f64\td5, d8, d9\n+\tvmul.f64\td14, d15, d3\n+\tvadd.f64\td1, d6, d13\n+\tvmla.f64\td14, d8, d11\n+\tvsub.f64\td6, d13, d6\n+\tvmul.f64\td3, d8, d3\n+\tadd\tr0, r6\n+\tstr.w\tr0, [r7, #672]\t@ 0x2a0\n+\tadds\tr0, r3, r6\n+\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tvmov.f64\td10, d5\n+\tvmul.f64\td5, d15, d9\n+\tvsub.f64\td9, d5, d2\n+\tvsub.f64\td5, d2, d5\n+\tvadd.f64\td9, d9, d6\n+\tvadd.f64\td5, d5, d6\n+\tvsub.f64\td6, d3, d4\n+\tvsub.f64\td4, d4, d3\n+\tvadd.f64\td6, d6, d7\n+\tvadd.f64\td4, d4, d7\n+\tvsub.f64\td7, d0, d14\n+\tvadd.f64\td0, d0, d14\n+\tvstr\td7, [r5, #-8]\n+\tvadd.f64\td7, d10, d1\n+\tvstr\td0, [r2, #-8]\n+\tvsub.f64\td1, d1, d10\n+\tldr.w\tr2, [r7, #600]\t@ 0x258\n+\tldr.w\tr5, [r7, #604]\t@ 0x25c\n+\tldr.w\tr3, [r7, #656]\t@ 0x290\n+\tldr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tvstr\td7, [r2, #-8]\n+\tldr.w\tr2, [r7, #616]\t@ 0x268\n+\tvstr\td6, [r5, #-8]\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n+\tvstr\td1, [r1, #-8]\n+\tvstr\td9, [r2, #-8]\n+\tvstr\td5, [r3, #-8]\n+\tldr.w\tr3, [r7, #408]\t@ 0x198\n+\tvstr\td4, [r5, #-8]\n+\tcmp\tr3, r4\n+\tbne.w\tfed6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x171e>\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr2, [r7, #416]\t@ 0x1a0\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #776]\t@ 0x308\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n \tcmp\tr3, r2\n-\tbge.n\tfc3e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f16>\n-\tldr.w\tr2, [r7, #596]\t@ 0x254\n+\tbge.n\t107c6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x200e>\n+\tldr.w\tr2, [r7, #780]\t@ 0x30c\n \tadd\tr3, r2\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tldr.w\tr3, [r7, #460]\t@ 0x1cc\n-\tldr.w\tr2, [r7, #156]\t@ 0x9c\n+\tstr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tldr.w\tr3, [r7, #648]\t@ 0x288\n+\tldr.w\tr2, [r7, #152]\t@ 0x98\n \tadds\tr3, #1\n-\tstr.w\tr3, [r7, #460]\t@ 0x1cc\n+\tstr.w\tr3, [r7, #648]\t@ 0x288\n \tcmp\tr3, r2\n-\tbne.w\tefde <__gridxc_gpfa_core_dp_MOD_gpfa_+0x12b6>\n-\tldr.w\tr3, [r7, #256]\t@ 0x100\n-\tmov\tr9, r6\n-\tldr.w\tr0, [r7, #252]\t@ 0xfc\n-\tmov\tsl, fp\n-\tldr.w\tr2, [r7, #168]\t@ 0xa8\n-\tsubs\tr3, #1\n-\tmov\tr6, lr\n-\tadds\tr1, r3, #1\n-\tadd\tr0, r2\n-\tbne.w\tefc6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x129e>\n-\tldr\tr3, [r7, #116]\t@ 0x74\n-\tmov\tsl, r9\n-\tldrd\tr4, r5, [r7, #108]\t@ 0x6c\n-\tmov\tlr, r2\n+\tbne.w\tfadc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1324>\n+\tldr.w\tr1, [r7, #260]\t@ 0x104\n \tmov\tip, fp\n-\tmov\tr9, r6\n-\tldr.w\tr2, [r7, #148]\t@ 0x94\n-\tsubs\tr3, #1\n-\tadd\tr4, r5\n-\tadds\tr0, r3, #1\n-\tadd\tr2, r5\n-\tstr.w\tr2, [r7, #148]\t@ 0x94\n-\tldr.w\tr2, [r7, #144]\t@ 0x90\n-\tsub.w\tr2, r2, r5\n-\tstr.w\tr2, [r7, #144]\t@ 0x90\n-\tbne.w\tef7e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1256>\n-\tmov\tfp, ip\n-\tmov\tsl, r9\n-\tldr\tr4, [r7, #20]\n-\tldrd\tip, r6, [r7, #12]\n-\tldrd\tr5, r9, [r7, #4]\n-\tsubs\tr4, #1\n-\tldr.w\tr3, [r7, #372]\t@ 0x174\n-\tldr.w\tr2, [r7, #136]\t@ 0x88\n-\tldr\tr1, [r7, #60]\t@ 0x3c\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r7, #372]\t@ 0x174\n+\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tmov\tr8, r6\n+\tldr.w\tr0, [r7, #256]\t@ 0x100\n+\tsubs\tr1, #1\n+\tadd\tr0, r3\n+\tadds\tr3, r1, #1\n+\tbne.w\tfac6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x130e>\n+\tmov\tr9, fp\n+\tldr.w\tr8, [r7, #88]\t@ 0x58\n+\tldrd\tr5, sl, [r7, #80]\t@ 0x50\n+\tldr.w\tfp, [r7, #76]\t@ 0x4c\n+\tldr.w\tr3, [r7, #144]\t@ 0x90\n+\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n+\tadd\tr5, sl\n+\tadd\tfp, sl\n+\tsub.w\tr3, r3, sl\n+\tcmp.w\tr8, #4294967295\t@ 0xffffffff\n+\tstr.w\tr3, [r7, #144]\t@ 0x90\n+\tbne.w\tfa80 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x12c8>\n+\tmov\tr6, r9\n+\tldr.w\tr9, [r7]\n+\tldrd\tr8, r4, [r7, #4]\n+\tldr.w\tr2, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr1, [r7, #164]\t@ 0xa4\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tadd\tr2, r1\n+\tstr.w\tr2, [r7, #464]\t@ 0x1d0\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r7, #124]\t@ 0x7c\n-\tsubs\tr5, r5, r2\n-\tadd\tr3, r1\n+\tadd\tr4, r2\n+\tldr\tr2, [r7, #96]\t@ 0x60\n+\tsubs\tr3, #1\n \tstr\tr3, [r7, #124]\t@ 0x7c\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tadd\tr6, r3\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tadd\tip, r3\n-\tldr\tr3, [r7, #48]\t@ 0x30\n-\tadd\tr9, r3\n-\tadds\tr3, r4, #1\n-\tbeq.w\t108aa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2b82>\n-\tldr.w\tr3, [r7, #372]\t@ 0x174\n+\tadd\tr2, r0\n+\tstr\tr2, [r7, #96]\t@ 0x60\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tadds\tr3, #1\n+\tadd\tr8, r2\n+\tldr\tr2, [r7, #32]\n+\tadd\tr9, r2\n+\tldr.w\tr2, [r7, #132]\t@ 0x84\n+\tsub.w\tr2, r2, r1\n+\tstr.w\tr2, [r7, #132]\t@ 0x84\n+\tbeq.w\t116da <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f22>\n+\tldr.w\tr3, [r7, #464]\t@ 0x1d0\n \tcmp\tr3, #0\n-\tble.w\tef34 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x120c>\n-\tldr\tr3, [r7, #124]\t@ 0x7c\n-\tvldr\td16, [r7, #88]\t@ 0x58\n-\tvldr\td15, [r6]\n-\tvldr\td14, [ip]\n-\tvldr\td4, [r3]\n-\tvldr\td13, [r9]\n-\tvmul.f64\td15, d16, d15\n-\tvldr\td2, [r3, #-8]\n-\tvmul.f64\td14, d16, d14\n-\tldr\tr3, [r7, #120]\t@ 0x78\n-\tvmul.f64\td4, d16, d4\n-\tvmul.f64\td13, d16, d13\n-\tvldr\td1, [r6, #-8]\n-\tvldr\td0, [ip, #-8]\n+\tble.w\tfa34 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x127c>\n+\tldr\tr3, [r7, #96]\t@ 0x60\n+\tvldr\td3, [r4, #-8]\n+\tvldr\td4, [r9]\n+\tvldr\td6, [r4]\n+\tvstr\td3, [r7, #760]\t@ 0x2f8\n+\tvldr\td3, [r3, #-8]\n+\tvldr\td7, [r3]\n+\tvldr\td5, [r8]\n+\tvstr\td3, [r7, #752]\t@ 0x2f0\n+\tvldr\td3, [r7, #104]\t@ 0x68\n+\tldr\tr3, [r7, #100]\t@ 0x64\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td6, d3, d6\n \tcmp\tr3, #0\n-\tvldr\td3, [r9, #-8]\n-\tbge.w\tef3c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1214>\n-\tldr.w\tr2, [r7, #372]\t@ 0x174\n-\tldr\tr1, [r7, #80]\t@ 0x50\n-\tldr\tr0, [r7, #68]\t@ 0x44\n-\tsubs\tr3, r2, r1\n-\tcmp\tr1, r2\n-\tudiv\tr3, r3, r0\n-\tble.w\tef50 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1228>\n-\tb.n\tfcaa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f82>\n-\tldr.w\tr5, [r7, #568]\t@ 0x238\n+\tvstr\td7, [r7, #440]\t@ 0x1b8\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td6, [r7, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d3, d5\n+\tvstr\td7, [r7, #424]\t@ 0x1a8\n+\tvldr\td7, [r8, #-8]\n+\tvstr\td6, [r7, #432]\t@ 0x1b0\n+\tvstr\td7, [r7, #736]\t@ 0x2e0\n+\tvldr\td7, [r9, #-8]\n+\tvstr\td7, [r7, #456]\t@ 0x1c8\n+\tbge.w\tfa3c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1284>\n+\tldr\tr3, [r7, #112]\t@ 0x70\n+\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tldr\tr1, [r7, #52]\t@ 0x34\n+\tsubs\tr0, r5, r3\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr\tr3, [r7, #112]\t@ 0x70\n+\tmov\tr1, r0\n+\tcmp\tr3, r5\n+\tble.w\tfa56 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x129e>\n+\tb.n\t10828 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2070>\n+\tldr.w\tr5, [r7, #768]\t@ 0x300\n \tcmp\tr5, #0\n-\tble.w\tfc1e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ef6>\n-\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tble.w\t107a6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1fee>\n+\tldr.w\tr5, [r7, #640]\t@ 0x280\n \tlsls\tr3, r3, #3\n \tmov.w\tsl, sl, lsl #3\n \tmov.w\tr9, r9, lsl #3\n-\tmov.w\tr8, r8, lsl #3\n \tlsls\tr1, r1, #3\n+\tstr.w\tsl, [r7, #228]\t@ 0xe4\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #456]\t@ 0x1c8\n-\tldr.w\tr5, [r7, #584]\t@ 0x248\n+\tstr.w\tr5, [r7, #608]\t@ 0x260\n+\tldr.w\tr5, [r7, #728]\t@ 0x2d8\n+\tmov.w\tr8, r8, lsl #3\n+\tstr.w\tr9, [r7, #224]\t@ 0xe0\n \tmov.w\tip, ip, lsl #3\n-\tstr.w\tsl, [r7, #228]\t@ 0xe4\n+\tstr.w\tr1, [r7, #184]\t@ 0xb8\n \tlsls\tr0, r0, #3\n-\tstr.w\tr9, [r7, #224]\t@ 0xe0\n-\tlsls\tr2, r2, #3\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #576]\t@ 0x240\n-\tldr.w\tr5, [r7, #560]\t@ 0x230\n+\tstr.w\tr5, [r7, #640]\t@ 0x280\n+\tldr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tlsls\tr2, r2, #3\n+\tstr.w\tr3, [r7, #412]\t@ 0x19c\n+\tmov.w\tr9, #0\n \tstr.w\tr8, [r7, #220]\t@ 0xdc\n-\tmov.w\tr8, #0\n-\tstr.w\tr1, [r7, #184]\t@ 0xb8\n \tlsls\tr5, r5, #3\n-\tstr.w\tr5, [r7, #584]\t@ 0x248\n-\tldr.w\tr5, [r7, #552]\t@ 0x228\n-\tstr.w\tr3, [r7, #352]\t@ 0x160\n+\tstr.w\tr5, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr5, [r7, #704]\t@ 0x2c0\n \tstr.w\tip, [r7, #188]\t@ 0xbc\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #240]\t@ 0xf0\n-\tldr.w\tr5, [r7, #472]\t@ 0x1d8\n+\tldr.w\tr5, [r7, #632]\t@ 0x278\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #236]\t@ 0xec\n-\tldr.w\tr5, [r7, #544]\t@ 0x220\n+\tldr.w\tr5, [r7, #696]\t@ 0x2b8\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #232]\t@ 0xe8\n-\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n+\tldr.w\tr5, [r7, #624]\t@ 0x270\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #216]\t@ 0xd8\n-\tldr.w\tr5, [r7, #536]\t@ 0x218\n+\tldr.w\tr5, [r7, #688]\t@ 0x2b0\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #212]\t@ 0xd4\n-\tldr.w\tr5, [r7, #528]\t@ 0x210\n+\tldr.w\tr5, [r7, #712]\t@ 0x2c8\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #208]\t@ 0xd0\n-\tldr.w\tr5, [r7, #520]\t@ 0x208\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #204]\t@ 0xcc\n-\tldr.w\tr5, [r7, #488]\t@ 0x1e8\n+\tldr.w\tr5, [r7, #656]\t@ 0x290\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #200]\t@ 0xc8\n-\tldr.w\tr5, [r7, #464]\t@ 0x1d0\n+\tldr.w\tr5, [r7, #616]\t@ 0x268\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #196]\t@ 0xc4\n-\tldr.w\tr5, [r7, #512]\t@ 0x200\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n \tlsls\tr5, r5, #3\n \tstr.w\tr5, [r7, #192]\t@ 0xc0\n-\tldr.w\tr3, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr5, [r7, #456]\t@ 0x1c8\n+\tldr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr5, [r7, #608]\t@ 0x260\n+\tvldr\td14, [r7, #456]\t@ 0x1c8\n \tlsls\tr1, r3, #3\n \tstr.w\tr1, [r7, #180]\t@ 0xb4\n \tlsls\tr1, r4, #3\n \tstr.w\tr1, [r7, #176]\t@ 0xb0\n-\tldr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tldr.w\tr1, [r7, #668]\t@ 0x29c\n \tadd.w\tr4, fp, r0\n-\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tldr.w\tr3, [r7, #640]\t@ 0x280\n \tadd\tr0, lr\n-\tstr.w\tr0, [r7, #504]\t@ 0x1f8\n+\tstr.w\tr0, [r7, #712]\t@ 0x2c8\n \tadd.w\tr0, fp, r5\n \tlsls\tr1, r1, #3\n \tstr.w\tr1, [r7, #172]\t@ 0xac\n-\tldr.w\tr1, [r7, #580]\t@ 0x244\n-\tstr.w\tr0, [r7, #520]\t@ 0x208\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n+\tstr.w\tr0, [r7, #696]\t@ 0x2b8\n \tadd.w\tr0, lr, r5\n-\tstr.w\tr0, [r7, #496]\t@ 0x1f0\n+\tstr.w\tr0, [r7, #656]\t@ 0x290\n \tadd.w\tr0, fp, r3\n-\tstr.w\tr0, [r7, #528]\t@ 0x210\n+\tstr.w\tr0, [r7, #704]\t@ 0x2c0\n \tadd.w\tr0, lr, r3\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n \tlsls\tr1, r1, #3\n-\tstr.w\tr0, [r7, #488]\t@ 0x1e8\n+\tstr.w\tr0, [r7, #672]\t@ 0x2a0\n \tadd.w\tsl, fp, r1\n \tadd.w\tr0, fp, r3\n-\tadd.w\tr9, lr, r3\n-\tldr.w\tr3, [r7, #352]\t@ 0x160\n-\tstr.w\tr0, [r7, #536]\t@ 0x218\n-\tadd.w\tr0, fp, r2\n+\tstr.w\tr0, [r7, #716]\t@ 0x2cc\n+\tadd.w\tr0, lr, r3\n+\tldr.w\tr3, [r7, #412]\t@ 0x19c\n+\tvldr\td13, [r7, #448]\t@ 0x1c0\n+\tvldr\td12, [r7, #440]\t@ 0x1b8\n \tadd\tr3, fp\n+\tvldr\td11, [r7, #432]\t@ 0x1b0\n+\tvldr\td10, [r7, #424]\t@ 0x1a8\n+\tstr.w\tr0, [r7, #680]\t@ 0x2a8\n+\tadd.w\tr0, fp, r2\n+\tstr.w\tr3, [r7, #468]\t@ 0x1d4\n \tadd\tr2, lr\n-\tstr.w\tr3, [r7, #560]\t@ 0x230\n \tmovs\tr3, #1\n \tstr.w\tr1, [r7, #244]\t@ 0xf4\n-\tstr.w\tr4, [r7, #512]\t@ 0x200\n-\tstr.w\tr0, [r7, #544]\t@ 0x220\n-\tstr.w\tr2, [r7, #552]\t@ 0x228\n-\tstr.w\tr3, [r7, #576]\t@ 0x240\n-\tstr.w\tr6, [r7, #584]\t@ 0x248\n-\tldr.w\tr3, [r7, #512]\t@ 0x200\n-\tldr.w\tr1, [r7, #520]\t@ 0x208\n-\tldr.w\tr0, [r7, #528]\t@ 0x210\n-\tldr.w\tr4, [r7, #536]\t@ 0x218\n-\tvldr\td27, [r3, #-8]\n-\tvldr\td20, [r1, #-8]\n-\tvldr\td17, [r0, #-8]\n-\tvldr\td25, [r4, #-8]\n-\tldr.w\tr5, [r7, #504]\t@ 0x1f8\n-\tvadd.f64\td19, d27, d20\n-\tldr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tvsub.f64\td27, d27, d20\n-\tldr.w\tr0, [r7, #488]\t@ 0x1e8\n-\tvadd.f64\td23, d17, d25\n-\tvsub.f64\td17, d17, d25\n-\tvldr\td24, [r9, #-8]\n-\tvldr\td22, [r5, #-8]\n-\tvldr\td18, [r1, #-8]\n-\tvldr\td16, [r0, #-8]\n-\tvadd.f64\td20, d19, d23\n-\tldr.w\tr0, [r7, #244]\t@ 0xf4\n-\tvmul.f64\td25, d9, d17\n-\tvldr\td21, [sl, #-8]\n-\tvsub.f64\td19, d19, d23\n-\tvadd.f64\td26, d16, d24\n-\tvadd.f64\td23, d22, d18\n-\tadd.w\tr3, r0, r8\n-\tvsub.f64\td22, d22, d18\n-\tadd\tr3, lr\n-\tvmov.f64\td18, d21\n-\tvfms.f64\td18, d20, d5\n-\tvsub.f64\td16, d16, d24\n-\tvmul.f64\td17, d8, d17\n-\tvmov.f64\td24, d25\n-\tvfma.f64\td17, d9, d27\n-\tvfnms.f64\td24, d8, d27\n-\tvfma.f64\td25, d27, d12\n-\tvadd.f64\td27, d23, d26\n-\tvsub.f64\td23, d23, d26\n-\tvldr\td26, [r3, #-8]\n-\tvadd.f64\td20, d20, d21\n-\tldr.w\tr4, [r7, #544]\t@ 0x220\n-\tldr.w\tr1, [r7, #552]\t@ 0x228\n-\tvmov.f64\td21, d26\n-\tldr.w\tr6, [r7, #560]\t@ 0x230\n-\tvfms.f64\td21, d27, d5\n-\tvmov.f64\td28, d18\n-\tvfma.f64\td28, d10, d19\n-\tvfma.f64\td18, d11, d19\n-\tvadd.f64\td19, d27, d26\n-\tvldr\td29, [r4, #-8]\n-\tvstr\td20, [sl, #-8]\n-\tvmov.f64\td20, d24\n-\tvfma.f64\td20, d27, d5\n-\tvldr\td31, [r1, #-8]\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tvstr\td19, [r3, #-8]\n-\tldr.w\tr4, [r7, #228]\t@ 0xe4\n-\tadd\tsl, r2\n-\tvmov.f64\td19, d21\n-\tvfma.f64\td21, d23, d11\n-\tadd.w\tr2, r8, r4\n-\tldr.w\tr5, [r7, #576]\t@ 0x240\n+\tstr.w\tr4, [r7, #688]\t@ 0x2b0\n+\tstr.w\tr0, [r7, #472]\t@ 0x1d8\n+\tstr.w\tr2, [r7, #668]\t@ 0x29c\n+\tstr.w\tr3, [r7, #664]\t@ 0x298\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr4, [r7, #244]\t@ 0xf4\n+\tldr.w\tr1, [r7, #696]\t@ 0x2b8\n+\tadd.w\tr2, r4, r9\n \tldr.w\tr4, [r7, #240]\t@ 0xf0\n-\tvfma.f64\td19, d10, d23\n-\tvldr\td6, [r6, #-8]\n-\tadds\tr5, #1\n-\tadd.w\tr3, r8, r4\n-\tldr.w\tr0, [r7, #232]\t@ 0xe8\n-\tstr.w\tr5, [r7, #576]\t@ 0x240\n-\tvsub.f64\td20, d20, d26\n+\tvldr\td4, [r3, #-8]\n+\tadd\tr2, lr\n+\tadd.w\tr3, r9, r4\n \tldr.w\tr4, [r7, #236]\t@ 0xec\n-\tvfma.f64\td20, d10, d23\n-\tvmul.f64\td23, d9, d16\n-\tadd\tr0, r8\n-\tadd.w\tr1, r8, r4\n-\tldr.w\tr4, [r7, #352]\t@ 0x160\n-\tvadd.f64\td24, d24, d21\n-\tvadd.f64\td21, d21, d25\n-\tadd\tr4, r8\n-\tvmul.f64\td16, d8, d16\n-\tadd.w\tip, lr, r4\n-\tstr.w\tip, [r7, #308]\t@ 0x134\n-\tvfma.f64\td16, d9, d22\n-\tvadd.f64\td25, d17, d19\n-\tvmul.f64\td26, d21, d0\n-\tvmov.f64\td21, d23\n-\tvldr\td7, [ip, #-8]\n-\tvfnms.f64\td21, d8, d22\n-\tadd.w\tip, fp, r0\n-\tstr.w\tip, [r7, #464]\t@ 0x1d0\n+\tvldr\td6, [r1, #-8]\n+\tadd.w\tr5, r9, r4\n+\tldr.w\tr0, [r7, #664]\t@ 0x298\n+\tldr.w\tr1, [r7, #228]\t@ 0xe4\n+\tadd.w\tip, fp, r5\n+\tldr.w\tr4, [r7, #232]\t@ 0xe8\n+\tadds\tr0, #1\n+\tstr.w\tr0, [r7, #664]\t@ 0x298\n+\tadd.w\tr0, r9, r1\n+\tadd\tr4, r9\n+\tstr.w\tip, [r7, #604]\t@ 0x25c\n+\tadd.w\tip, fp, r4\n+\tadd\tr4, lr\n+\tstr.w\tr4, [r7, #568]\t@ 0x238\n+\tadd.w\tr4, fp, r0\n+\tstr.w\tr4, [r7, #584]\t@ 0x248\n+\tadd\tr5, lr\n+\tldr.w\tr4, [r7, #224]\t@ 0xe0\n+\tvadd.f64\td7, d4, d6\n+\tldr.w\tr1, [r7, #412]\t@ 0x19c\n+\tvsub.f64\td4, d4, d6\n+\tadd.w\tr8, r9, r4\n+\tldr.w\tr4, [r7, #220]\t@ 0xdc\n+\tstr.w\tip, [r7, #592]\t@ 0x250\n \tadd.w\tip, lr, r0\n-\tstr.w\tip, [r7, #436]\t@ 0x1b4\n-\tadd.w\tip, fp, r2\n-\tstr.w\tip, [r7, #456]\t@ 0x1c8\n-\tadd.w\tip, fp, r3\n-\tstr.w\tip, [r7, #472]\t@ 0x1d8\n-\tadd.w\tip, fp, r1\n-\tstr.w\tip, [r7, #468]\t@ 0x1d4\n-\tadd.w\tip, lr, r1\n-\tldr.w\tr1, [r7, #224]\t@ 0xe0\n-\tstr.w\tip, [r7, #440]\t@ 0x1b8\n-\tadd.w\tr0, r2, lr\n-\tadd.w\tip, r8, r1\n-\tldr.w\tr1, [r7, #220]\t@ 0xdc\n-\tvadd.f64\td21, d18, d21\n-\tstr.w\tr0, [r7, #432]\t@ 0x1b0\n-\tadd.w\tr5, r8, r1\n-\tldr.w\tr1, [r7, #212]\t@ 0xd4\n-\tadd.w\tr2, fp, ip\n-\tvmul.f64\td20, d20, d14\n-\tadd.w\tr4, r8, r1\n+\tstr.w\tip, [r7, #560]\t@ 0x230\n+\tadd.w\tip, r9, r4\n+\tldr.w\tr4, [r7, #216]\t@ 0xd8\n+\tadd\tr1, r9\n+\tstr.w\tr5, [r7, #600]\t@ 0x258\n+\tadd\tr1, lr\n+\tadd.w\tr5, r9, r4\n+\tldr.w\tr4, [r7, #212]\t@ 0xd4\n+\tstr.w\tr1, [r7, #368]\t@ 0x170\n+\tadd.w\tr1, fp, r3\n+\tstr.w\tr1, [r7, #608]\t@ 0x260\n+\tadd\tr4, r9\n \tldr.w\tr1, [r7, #208]\t@ 0xd0\n+\tadd\tr3, lr\n+\tstr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tadd.w\tr0, r9, r1\n+\tadd.w\tr1, fp, r8\n+\tadd\tr8, lr\n+\tstr.w\tr1, [r7, #360]\t@ 0x168\n+\tstr.w\tr8, [r7, #552]\t@ 0x228\n+\tadd.w\tr8, fp, ip\n \tadd\tip, lr\n-\tstr.w\tip, [r7, #304]\t@ 0x130\n-\tadd.w\tr0, r8, r1\n-\tldr.w\tr1, [r7, #216]\t@ 0xd8\n+\tstr.w\tr8, [r7, #576]\t@ 0x240\n+\tstr.w\tip, [r7, #336]\t@ 0x150\n+\tadd.w\tr8, fp, r4\n+\tadd.w\tip, lr, r5\n+\tstr.w\tip, [r7, #540]\t@ 0x21c\n \tadd.w\tip, fp, r5\n-\tstr.w\tip, [r7, #444]\t@ 0x1bc\n-\tadd\tr1, r8\n+\tstr.w\tip, [r7, #548]\t@ 0x224\n+\tadd.w\tip, lr, r4\n+\tstr.w\tip, [r7, #528]\t@ 0x210\n+\tldr.w\tr4, [r7, #204]\t@ 0xcc\n+\tadd.w\tip, lr, r0\n+\tstr.w\tip, [r7, #536]\t@ 0x218\n+\tadd.w\tip, fp, r0\n+\tstr.w\tip, [r7, #544]\t@ 0x220\n+\tadd.w\tip, r9, r4\n+\tldr.w\tr4, [r7, #200]\t@ 0xc8\n+\tadd.w\tr1, fp, ip\n+\tldr.w\tr0, [r7, #192]\t@ 0xc0\n+\tadd\tip, lr\n+\tadd.w\tr5, r9, r4\n+\tldr.w\tr4, [r7, #196]\t@ 0xc4\n+\tadd\tr0, r9\n+\tstr.w\tip, [r7, #520]\t@ 0x208\n+\tadd\tr4, r9\n+\tadd.w\tip, fp, r5\n+\tstr.w\tip, [r7, #320]\t@ 0x140\n \tadd.w\tip, lr, r5\n-\tadd.w\tr5, fp, r0\n-\tadd\tr0, lr\n-\tstr.w\tr0, [r7, #404]\t@ 0x194\n-\tadd.w\tr0, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #408]\t@ 0x198\n-\tldr.w\tr1, [r7, #204]\t@ 0xcc\n-\tvfma.f64\td23, d22, d12\n-\tvfma.f64\td20, d21, d0\n-\tvfma.f64\td26, d21, d14\n-\tstr.w\tr5, [r7, #420]\t@ 0x1a4\n-\tadd.w\tr5, r8, r1\n-\tldr.w\tr1, [r7, #200]\t@ 0xc8\n-\tvnmul.f64\td27, d15, d24\n-\tstr.w\tip, [r7, #300]\t@ 0x12c\n+\tstr.w\tip, [r7, #312]\t@ 0x138\n \tadd.w\tip, fp, r4\n+\tstr.w\tip, [r7, #516]\t@ 0x204\n+\tadd.w\tip, lr, r4\n+\tstr.w\tip, [r7, #496]\t@ 0x1f0\n+\tadd.w\tip, fp, r0\n+\tstr.w\tip, [r7, #512]\t@ 0x200\n+\tadd.w\tip, lr, r0\n+\tldr.w\tr0, [r7, #184]\t@ 0xb8\n+\tstr.w\tr1, [r7, #328]\t@ 0x148\n+\tadd.w\tr4, r9, r0\n+\tldr.w\tr0, [r7, #188]\t@ 0xbc\n+\tadd.w\tr1, fp, r4\n \tadd\tr4, lr\n-\tstr.w\tr4, [r7, #296]\t@ 0x128\n-\tadd.w\tr4, r8, r1\n-\tldr.w\tr1, [r7, #196]\t@ 0xc4\n-\tstr.w\tr0, [r7, #424]\t@ 0x1a8\n-\tvmul.f64\td24, d1, d24\n-\tadd.w\tr0, r8, r1\n-\tldr.w\tr1, [r7, #192]\t@ 0xc0\n-\tvadd.f64\td18, d18, d23\n-\tstr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tadd\tr1, r8\n-\tadd.w\tr2, fp, r5\n-\tvstr\td20, [r7, #320]\t@ 0x140\n-\tadd\tr5, lr\n-\tstr.w\tr2, [r7, #416]\t@ 0x1a0\n-\tvsub.f64\td22, d17, d19\n-\tvstr\td26, [r7, #312]\t@ 0x138\n-\tvfma.f64\td27, d18, d1\n-\tstr.w\tr5, [r7, #400]\t@ 0x190\n-\tadd.w\tr5, fp, r4\n-\tadd\tr4, lr\n-\tstr.w\tr5, [r7, #412]\t@ 0x19c\n-\tstr.w\tr4, [r7, #292]\t@ 0x124\n-\tadd.w\tr5, lr, r1\n+\tadd\tr0, r9\n+\tstr.w\tr4, [r7, #304]\t@ 0x130\n \tadd.w\tr4, fp, r0\n-\tstr.w\tr4, [r7, #392]\t@ 0x188\n-\tadd.w\tr4, fp, r1\n-\tldr.w\tr1, [r7, #184]\t@ 0xb8\n \tadd\tr0, lr\n-\tstr.w\tr0, [r7, #384]\t@ 0x180\n-\tadd\tr1, r8\n-\tvfma.f64\td24, d18, d15\n-\tadd.w\tr0, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #276]\t@ 0x114\n-\tvsub.f64\td18, d28, d16\n-\tldr.w\tr1, [r7, #188]\t@ 0xbc\n-\tvnmul.f64\td30, d4, d25\n-\tstr.w\tr0, [r7, #284]\t@ 0x11c\n-\tvsub.f64\td19, d19, d17\n-\tadd\tr1, r8\n+\tstr.w\tr0, [r7, #488]\t@ 0x1e8\n \tldr.w\tr0, [r7, #180]\t@ 0xb4\n-\tadd.w\tr2, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #280]\t@ 0x118\n-\tadd\tr0, r8\n-\tldr.w\tr1, [r7, #176]\t@ 0xb0\n-\tvfma.f64\td30, d18, d2\n-\tstr.w\tr2, [r7, #288]\t@ 0x120\n-\tadd.w\tr2, fp, r0\n-\tadd\tr1, r8\n-\tstr.w\tr2, [r7, #272]\t@ 0x110\n-\tadd.w\tr2, r0, lr\n-\tstr.w\tr2, [r7, #376]\t@ 0x178\n-\tadd.w\tr2, fp, r1\n-\tadd\tr1, lr\n-\tstr.w\tr1, [r7, #264]\t@ 0x108\n-\tvmul.f64\td19, d19, d3\n-\tldr.w\tr1, [r7, #172]\t@ 0xac\n-\tvadd.f64\td16, d28, d16\n-\tstr.w\tr2, [r7, #268]\t@ 0x10c\n-\tvmul.f64\td25, d2, d25\n-\tadd\tr1, r8\n-\tvfma.f64\td25, d18, d4\n-\tadd.w\tr2, lr, r1\n-\tstr.w\tr2, [r7, #260]\t@ 0x104\n-\tldr.w\tr2, [r7, #544]\t@ 0x220\n-\tvmov.f64\td17, d19\n-\tvfma.f64\td17, d16, d13\n-\tvmul.f64\td22, d22, d13\n-\tvfma.f64\td22, d16, d3\n-\tldr.w\tr0, [r7, #584]\t@ 0x248\n-\tadd\tr3, lr\n-\tadd\tr1, fp\n-\tvstr\td30, [r2, #-8]\n-\tadd\tr8, r0\n-\tvstr\td27, [r6, #-8]\n-\tldr.w\tr6, [r7, #464]\t@ 0x1d0\n-\tvstr\td17, [r7, #328]\t@ 0x148\n-\tvldr\td21, [r6, #-8]\n-\tldr.w\tr6, [r7, #456]\t@ 0x1c8\n-\tvstr\td22, [r7, #336]\t@ 0x150\n-\tvldr\td17, [r6, #-8]\n-\tldr.w\tr6, [r7, #552]\t@ 0x228\n-\tvsub.f64\td18, d21, d17\n-\tvadd.f64\td17, d21, d17\n-\tvmov.f64\td21, d29\n-\tvstr\td25, [r6, #-8]\n-\tldr.w\tr6, [r7, #308]\t@ 0x134\n-\tvstr\td24, [r6, #-8]\n-\tldr.w\tr6, [r7, #472]\t@ 0x1d8\n-\tvldr\td16, [r6, #-8]\n-\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvldr\td19, [r6, #-8]\n-\tldr.w\tr6, [r7, #448]\t@ 0x1c0\n-\tvsub.f64\td23, d16, d19\n-\tvadd.f64\td16, d16, d19\n-\tvldr\td26, [r6, #-8]\n-\tadds\tr6, r2, r0\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tvadd.f64\td20, d16, d17\n-\tstr.w\tr6, [r7, #544]\t@ 0x220\n-\tldr.w\tr6, [r7, #560]\t@ 0x230\n-\tvsub.f64\td16, d16, d17\n-\tadd\tr6, r0\n-\tstr.w\tr6, [r7, #560]\t@ 0x230\n-\tvfms.f64\td21, d20, d5\n-\tldr.w\tr6, [r7, #552]\t@ 0x228\n-\tvldr\td19, [r2, #-8]\n-\tvadd.f64\td20, d29, d20\n-\tldr.w\tr2, [r7, #512]\t@ 0x200\n-\tadd\tr6, r0\n-\tstr.w\tr6, [r7, #552]\t@ 0x228\n-\tvmul.f64\td29, d9, d18\n-\tldr.w\tr6, [r7, #444]\t@ 0x1bc\n-\tvmul.f64\td18, d8, d18\n-\tvfma.f64\td18, d9, d23\n-\tvstr\td20, [r2, #-8]\n-\tvmov.f64\td17, d29\n-\tvfma.f64\td29, d23, d12\n-\tvmov.f64\td22, d21\n-\tvldr\td28, [r6, #-8]\n-\tadds\tr6, r2, r0\n-\tldr.w\tr0, [r7, #432]\t@ 0x1b0\n-\tstr.w\tr6, [r7, #512]\t@ 0x200\n-\tvfnms.f64\td17, d8, d23\n-\tldr.w\tr6, [r7, #436]\t@ 0x1b4\n-\tvmov.f64\td25, d22\n-\tvldr\td21, [r3, #-8]\n-\tvldr\td23, [r0, #-8]\n-\tvfma.f64\td25, d10, d16\n-\tvfma.f64\td22, d16, d11\n-\tldr.w\tr2, [r7, #504]\t@ 0x1f8\n-\tvldr\td16, [r6, #-8]\n-\tvadd.f64\td20, d21, d19\n-\tvsub.f64\td21, d21, d19\n-\tldr.w\tr6, [r7, #304]\t@ 0x130\n-\tldr.w\tr0, [r7, #584]\t@ 0x248\n-\tvadd.f64\td19, d16, d23\n-\tvsub.f64\td16, d16, d23\n-\tvldr\td27, [r6, #-8]\n-\tvadd.f64\td24, d20, d19\n-\tvsub.f64\td20, d20, d19\n-\tvmul.f64\td19, d9, d16\n-\tvmul.f64\td16, d8, d16\n-\tvfma.f64\td16, d9, d21\n-\tvmov.f64\td23, d19\n-\tvfma.f64\td19, d21, d12\n-\tvfnms.f64\td23, d8, d21\n-\tvmov.f64\td21, d17\n-\tvfma.f64\td21, d24, d5\n-\tvadd.f64\td19, d22, d19\n-\tvadd.f64\td23, d22, d23\n-\tvsub.f64\td21, d21, d31\n-\tvfma.f64\td21, d10, d20\n-\tvmul.f64\td30, d14, d21\n-\tvmov.f64\td21, d31\n-\tvfms.f64\td21, d24, d5\n-\tvfma.f64\td30, d0, d23\n-\tvadd.f64\td31, d31, d24\n-\tvstr\td31, [r2, #-8]\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r7, #504]\t@ 0x1f8\n-\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n-\tvmov.f64\td22, d21\n-\tvfma.f64\td21, d20, d11\n-\tvfma.f64\td22, d10, d20\n-\tvadd.f64\td20, d21, d29\n-\tvadd.f64\td17, d17, d21\n-\tvadd.f64\td21, d18, d22\n-\tvmul.f64\td20, d20, d0\n-\tvnmul.f64\td24, d17, d15\n-\tvfma.f64\td20, d14, d23\n-\tvsub.f64\td23, d25, d16\n-\tvmul.f64\td17, d1, d17\n-\tvfma.f64\td24, d1, d19\n-\tvfma.f64\td17, d15, d19\n-\tvnmul.f64\td19, d21, d4\n-\tvadd.f64\td16, d25, d16\n-\tvmul.f64\td21, d2, d21\n-\tvfma.f64\td19, d2, d23\n-\tvfma.f64\td21, d4, d23\n-\tvstr\td19, [r2, #-8]\n-\tvsub.f64\td19, d22, d18\n-\tldr.w\tr2, [r7, #448]\t@ 0x1c0\n-\tvsub.f64\td22, d18, d22\n-\tvmul.f64\td19, d19, d3\n-\tvstr\td24, [r2, #-8]\n-\tvmul.f64\td22, d22, d13\n-\tldr.w\tr2, [r7, #444]\t@ 0x1bc\n-\tvfma.f64\td22, d3, d16\n-\tvmov.f64\td18, d19\n-\tvfma.f64\td18, d13, d16\n-\tvstr\td30, [r2, #-8]\n-\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n-\tvldr\td16, [ip, #-8]\n-\tvstr\td22, [r7, #472]\t@ 0x1d8\n-\tvldr\td19, [r2, #-8]\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvstr\td18, [r7, #448]\t@ 0x1c0\n-\tvldr\td18, [r2, #-8]\n-\tldr.w\tr2, [r7, #300]\t@ 0x12c\n-\tvldr\td30, [r2, #-8]\n-\tvstr\td21, [r3, #-8]\n-\tvmov.f64\td21, d6\n-\tvstr\td17, [r6, #-8]\n-\tvadd.f64\td17, d16, d19\n-\tvsub.f64\td16, d16, d19\n-\tvsub.f64\td19, d26, d18\n-\tvadd.f64\td26, d26, d18\n-\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tvstr\td20, [r2, #-8]\n-\tldr.w\tr2, [r7, #528]\t@ 0x210\n-\tvadd.f64\td18, d26, d17\n-\tvldr\td29, [r3, #-8]\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tvsub.f64\td17, d26, d17\n-\tadds\tr6, r2, r0\n-\tstr.w\tr6, [r7, #528]\t@ 0x210\n-\tldr.w\tr6, [r7, #400]\t@ 0x190\n-\tvfms.f64\td21, d18, d5\n-\tvadd.f64\td18, d6, d18\n-\tvmul.f64\td6, d9, d16\n-\tvldr\td26, [r6, #-8]\n-\tvstr\td18, [r2, #-8]\n-\tvldr\td31, [r3, #-8]\n-\tvmov.f64\td18, d6\n-\tldr.w\tr3, [r7, #408]\t@ 0x198\n-\tvfnms.f64\td18, d8, d19\n-\tldr.w\tr2, [r7, #296]\t@ 0x128\n-\tvfma.f64\td6, d19, d12\n-\tvmov.f64\td22, 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#464]\t@ 0x1d0\n-\tldr.w\tr3, [r7, #412]\t@ 0x19c\n-\tldr.w\tr0, [r7, #284]\t@ 0x11c\n-\tvmov.f64\td25, d21\n-\tvfma.f64\td21, d20, d11\n-\tvfma.f64\td25, d10, d20\n-\tvadd.f64\td18, d18, d21\n-\tvadd.f64\td21, d21, d6\n-\tvmov.f64\td22, d25\n-\tvmul.f64\td25, d21, d0\n-\tvadd.f64\td20, d17, d22\n-\tvsub.f64\td21, d17, d22\n-\tvsub.f64\td17, d22, d17\n-\tvsub.f64\td22, d24, d16\n-\tvadd.f64\td16, d24, d16\n-\tvfma.f64\td25, d14, d23\n-\tvmul.f64\td21, d21, d13\n-\tvmul.f64\td17, d17, d3\n-\tvfma.f64\td21, d3, d16\n-\tvfma.f64\td17, d13, d16\n-\tvnmul.f64\td16, d20, d4\n-\tvmul.f64\td20, d2, d20\n-\tvfma.f64\td16, d2, d22\n-\tvfma.f64\td20, d4, d22\n-\tvstr\td16, [r6, #-8]\n-\tvnmul.f64\td16, d18, d15\n-\tvfma.f64\td16, d1, d19\n-\tvstr\td21, [r3, #-8]\n-\tldr.w\tr3, [r7, #416]\t@ 0x1a0\n-\tvmul.f64\td18, d1, d18\n-\tvfma.f64\td18, d15, d19\n-\tldr.w\tr6, [r7, #436]\t@ 0x1b4\n-\tvstr\td16, [ip, #-8]\n-\tvstr\td27, [r3, #-8]\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n-\tvldr\td22, [r4, #-8]\n-\tvldr\td16, [r0, #-8]\n-\tvldr\td21, [r3, #-8]\n-\tldr.w\tr3, [r7, #292]\t@ 0x124\n-\tvadd.f64\td19, d28, d21\n-\tvsub.f64\td21, d28, d21\n+\tstr.w\tr4, [r7, #508]\t@ 0x1fc\n+\tadd.w\tr4, r9, r0\n+\tstr.w\tr1, [r7, #504]\t@ 0x1f8\n+\tadd.w\tr1, lr, r4\n+\tstr.w\tr1, [r7, #296]\t@ 0x128\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n+\tadd\tr4, fp\n+\tldr.w\tr5, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr0, [r7, #176]\t@ 0xb0\n+\tstr.w\tr4, [r7, #300]\t@ 0x12c\n+\tvldr\td9, [r1, #-8]\n+\tadd\tr0, r9\n+\tldr.w\tr1, [r7, #656]\t@ 0x290\n+\tadd.w\tr4, lr, r0\n+\tvldr\td1, [r5, #-8]\n+\tadd\tr0, fp\n+\tstr.w\tr4, [r7, #480]\t@ 0x1e0\n+\tstr.w\tr0, [r7, #484]\t@ 0x1e4\n+\tvldr\td0, [r1, #-8]\n+\tldr.w\tr0, [r7, #172]\t@ 0xac\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tvadd.f64\td5, d9, d0\n+\tvsub.f64\td9, d9, d0\n+\tadd\tr0, r9\n+\tadd.w\tr4, lr, r0\n+\tadd\tr0, fp\n+\tvldr\td2, [r5, #-8]\n+\tadd\tr9, r6\n+\tvldr\td3, [r3, #-8]\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n+\tvadd.f64\td0, d1, d2\n+\tvsub.f64\td1, d1, d2\n+\tvldr\td6, [r3, #-8]\n+\tvstr\td1, [r7, #616]\t@ 0x268\n+\tvmul.f64\td1, d15, d9\n+\tldr.w\tr3, [r7, #472]\t@ 0x1d8\n+\tvadd.f64\td2, d3, d6\n+\tvsub.f64\td6, d3, d6\n+\tvmul.f64\td3, d15, d4\n+\tvstr\td1, [r7, #384]\t@ 0x180\n+\tvldr\td1, [r3, #-8]\n+\tvstr\td3, [r7, #640]\t@ 0x280\n+\tvadd.f64\td3, d7, d2\n+\tvstr\td1, [r7, #656]\t@ 0x290\n+\tvsub.f64\td7, d7, d2\n+\tvadd.f64\td1, d5, d0\n+\tvsub.f64\td5, d5, d0\n+\tvldr\td0, [r7, #744]\t@ 0x2e8\n+\tvmov.f64\td2, #80\t@ 0x3e800000 0.250\n+\tvstr\td3, [r7, #624]\t@ 0x270\n+\tvmov.f64\td3, d2\n+\tvmul.f64\td5, d5, d0\n+\tvmul.f64\td7, d7, d0\n+\tvldr\td0, [r2, #-8]\n+\tvmul.f64\td2, d1, d2\n+\tvadd.f64\td1, d1, d0\n+\tvldr\td0, [r7, #624]\t@ 0x270\n+\tvstr\td1, [r7, #472]\t@ 0x1d8\n+\tvmul.f64\td1, d15, d6\n+\tvmla.f64\td1, d8, d4\n+\tvldr\td4, [sl, #-8]\n+\tvmul.f64\td6, d8, d6\n+\tvstr\td1, [r7, #632]\t@ 0x278\n+\tvldr\td1, [sl, #-8]\n+\tvmls.f64\td1, d0, d3\n+\tvadd.f64\td0, d0, d4\n+\tvldr\td4, [r2, #-8]\n+\tvldr\td3, [r7, #640]\t@ 0x280\n+\tvstr\td0, [sl, #-8]\n+\tvsub.f64\td0, d4, d2\n+\tadd\tsl, r6\n+\tvstr\td1, [r7, #624]\t@ 0x270\n+\tvldr\td1, [r7, #616]\t@ 0x268\n+\tvmul.f64\td4, d15, d1\n+\tvmul.f64\td1, d8, d1\n+\tvmla.f64\td4, d8, d9\n+\tvmov.f64\td9, d4\n+\tvldr\td4, [r7, #640]\t@ 0x280\n+\tvsub.f64\td4, d4, d6\n+\tvsub.f64\td6, d6, d3\n+\tvadd.f64\td3, d4, d2\n+\tvldr\td2, [r2, #-8]\n+\tvsub.f64\td3, d3, d2\n+\tvadd.f64\td2, d5, d0\n+\tvsub.f64\td0, d0, d5\n+\tvadd.f64\td3, d3, d5\n+\tvstr\td2, [r7, #392]\t@ 0x188\n+\tvadd.f64\td6, d6, d0\n+\tvadd.f64\td4, d4, d0\n+\tvstr\td3, [r7, #272]\t@ 0x110\n+\tvstr\td6, [r7, #264]\t@ 0x108\n+\tvldr\td6, [r7, #624]\t@ 0x270\n+\tvadd.f64\td3, d7, d6\n+\tvsub.f64\td7, d6, d7\n+\tvldr\td6, [r7, #632]\t@ 0x278\n+\tvldr\td5, [r7, #384]\t@ 0x180\n+\tldr.w\tr5, [r7, #668]\t@ 0x29c\n+\tvadd.f64\td2, d6, d2\n+\tvldr\td0, [r7, #472]\t@ 0x1d8\n+\tvsub.f64\td6, d1, d5\n+\tvsub.f64\td1, d5, d1\n+\tvadd.f64\td5, d3, d9\n+\tvadd.f64\td6, d6, d7\n+\tvadd.f64\td7, d1, d7\n+\tvstr\td5, [r7, #384]\t@ 0x180\n+\tvldr\td5, [r7, #760]\t@ 0x2f8\n+\tvstr\td7, [r7, #376]\t@ 0x178\n+\tvsub.f64\td7, d3, d9\n+\tvmul.f64\td3, d2, d13\n+\tvmul.f64\td2, d5, d2\n+\tvldr\td9, [r7, #752]\t@ 0x2f0\n+\tvmla.f64\td2, d7, d13\n+\tvnmls.f64\td3, d7, d5\n+\tvmul.f64\td7, d4, d12\n+\tvmul.f64\td4, d9, d4\n+\tvmla.f64\td4, d6, d12\n+\tvnmls.f64\td7, d6, d9\n+\tvldr\td9, [r5, #-8]\n+\tldr.w\tr5, [r7, #468]\t@ 0x1d4\n+\tvstr\td0, [r2, #-8]\n+\tadds\tr2, r3, r6\n+\tstr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tldr.w\tr2, [r7, #368]\t@ 0x170\n+\tvldr\td6, [r5, #-8]\n+\tvstr\td3, [r3, #-8]\n+\tldr.w\tr3, [r7, #668]\t@ 0x29c\n+\tvstr\td7, [r5, #-8]\n+\tadd\tr5, r6\n+\tstr.w\tr5, [r7, #468]\t@ 0x1d4\n+\tmov\tr5, r3\n+\tadd\tr5, r6\n+\tstr.w\tr5, [r7, #668]\t@ 0x29c\n+\tldr.w\tr5, [r7, #608]\t@ 0x260\n+\tvldr\td3, [r2, #-8]\n+\tvstr\td2, [r3, #-8]\n+\tvstr\td4, [r2, #-8]\n+\tvldr\td4, [r5, #-8]\n+\tldr.w\tr5, [r7, #604]\t@ 0x25c\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tvstr\td6, [r7, #640]\t@ 0x280\n+\tvstr\td3, [r7, #624]\t@ 0x270\n+\tvldr\td7, [r5, #-8]\n+\tldr.w\tr5, [r7, #592]\t@ 0x250\n+\tvldr\td5, [r2, #-8]\n+\tvadd.f64\td3, d4, d7\n+\tvsub.f64\td4, d4, d7\n+\tvldr\td1, [r5, #-8]\n+\tldr.w\tr5, [r7, #600]\t@ 0x258\n+\tvldr\td2, [r5, #-8]\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tldr.w\tr5, [r7, #568]\t@ 0x238\n+\tldr.w\tr2, [r7, #688]\t@ 0x2b0\n+\tvldr\td6, [r3, #-8]\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n+\tvldr\td0, [r5, #-8]\n+\tvstr\td0, [r7, #616]\t@ 0x268\n+\tvadd.f64\td0, d1, d5\n+\tvsub.f64\td5, d1, d5\n+\tvldr\td1, [r3, #-8]\n \tvldr\td7, [r3, #-8]\n-\tvstr\td20, [r6, #-8]\n-\tvstr\td17, [r3, #-8]\n-\tvstr\td18, [r2, #-8]\n-\tvadd.f64\td18, d29, d22\n-\tvsub.f64\td29, d29, d22\n-\tldr.w\tr6, [r7, #400]\t@ 0x190\n-\tldr.w\tr3, [r7, #288]\t@ 0x120\n-\tvldr\td20, [r7, #320]\t@ 0x140\n-\tvadd.f64\td22, d19, d18\n-\tvsub.f64\td18, d19, d18\n-\tvmul.f64\td28, d9, d29\n+\tldr.w\tr3, [r7, #360]\t@ 0x168\n+\tvsub.f64\td1, d1, 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0x260\n+\tvstr\td0, [r7, #352]\t@ 0x160\n+\tvmul.f64\td0, d1, d5\n+\tvmul.f64\td5, d13, d3\n+\tvnmls.f64\td4, d1, d7\n+\tvmla.f64\td0, d12, d7\n+\tvldr\td7, [r7, #760]\t@ 0x2f8\n+\tvldr\td1, [r7, #280]\t@ 0x118\n+\tvnmls.f64\td5, d7, d2\n+\tvmul.f64\td3, d7, d3\n+\tvldr\td7, [r7, #736]\t@ 0x2e0\n+\tvmla.f64\td3, d13, d2\n+\tvmul.f64\td2, d11, d6\n+\tvmul.f64\td6, d7, d6\n+\tvmla.f64\td2, d9, d7\n+\tvmla.f64\td6, d1, d11\n+\tvldr\td9, [r2, #-8]\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tvstr\td5, [r5, #-8]\n+\tvstr\td4, [r3, #-8]\n+\tvldr\td1, [r2, #-8]\n+\tldr.w\tr3, [r7, #576]\t@ 0x240\n+\tldr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tvstr\td9, [r7, #360]\t@ 0x168\n+\tvldr\td9, [r7, #288]\t@ 0x120\n+\tvstr\td6, [r3, #-8]\n+\tldr.w\tr3, [r7, #336]\t@ 0x150\n+\tvstr\td9, [r2, #-8]\n+\tadd\tr2, r6\n+\tstr.w\tr2, [r7, #712]\t@ 0x2c8\n+\tldr.w\tr2, [r7, #728]\t@ 0x2d8\n+\tvldr\td5, [r3, #-8]\n+\tvstr\td3, [r2, #-8]\n+\tldr.w\tr2, [r7, #552]\t@ 0x228\n+\tvstr\td5, [r7, #608]\t@ 0x260\n+\tvstr\td0, [r2, #-8]\n+\tldr.w\tr2, [r7, #540]\t@ 0x21c\n+\tvstr\td2, [r3, #-8]\n+\tvldr\td0, [r2, #-8]\n+\tldr.w\tr2, [r7, #528]\t@ 0x210\n+\tvadd.f64\td7, d1, d0\n+\tvsub.f64\td0, d1, d0\n+\tvldr\td2, [r2, #-8]\n \tldr.w\tr2, [r7, #536]\t@ 0x218\n-\tvstr\td25, [r6, #-8]\n-\tldr.w\tr6, [r7, #384]\t@ 0x180\n-\tvadd.f64\td19, d22, d16\n-\tvfms.f64\td16, d22, d5\n-\tvldr\td27, [r3, #-8]\n-\tvstr\td20, [r0, #-8]\n-\tldr.w\tr0, [r7, #584]\t@ 0x248\n-\tvldr\td20, [r6, #-8]\n-\tvstr\td19, [r2, #-8]\n-\tadds\tr6, r2, r0\n-\tldr.w\tr2, [r7, #276]\t@ 0x114\n-\tvldr\td25, [r5, #-8]\n-\tvadd.f64\td23, d30, d20\n-\tvmov.f64\td24, d16\n-\tstr.w\tr6, [r7, #536]\t@ 0x218\n-\tvfma.f64\td24, d10, d18\n-\tvfma.f64\td16, d18, d11\n-\tvadd.f64\td17, d26, d25\n-\tvsub.f64\td25, d26, d25\n-\tvmul.f64\td18, d8, d29\n-\tvsub.f64\td20, d30, d20\n-\tvfma.f64\td18, d9, d21\n-\tvmov.f64\td22, d24\n-\tvmov.f64\td24, d28\n-\tvfnms.f64\td24, d8, d21\n-\tvfma.f64\td28, d21, d12\n-\tvadd.f64\td21, d23, d17\n-\tvsub.f64\td23, d23, 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d9\n+\tvldr\td6, [r7, #360]\t@ 0x168\n+\tvstr\td5, [r7, #624]\t@ 0x270\n+\tvldr\td5, [r2, #-8]\n+\tvldr\td9, [r3, #-8]\n+\tldr.w\tr2, [r7, #672]\t@ 0x2a0\n \tldr.w\tr3, [r7, #520]\t@ 0x208\n-\tvldr\td21, [r0, #-8]\n-\tvsub.f64\td18, d18, d22\n-\tvstr\td16, [r0, #-8]\n-\tvsub.f64\td16, d7, d29\n-\tvmov.f64\td29, d31\n-\tvfma.f64\td31, d24, d12\n-\tvfnms.f64\td29, d8, d24\n-\tvadd.f64\td24, d25, d19\n-\tvmov.f64\td22, d28\n-\tvsub.f64\td19, d25, d19\n-\tvmul.f64\td27, d9, d16\n-\tvmul.f64\td16, d8, d16\n-\tvfma.f64\td16, d9, d20\n-\tvfms.f64\td22, d23, d5\n-\tvadd.f64\td23, d23, d28\n+\tvldr\td1, [r7, #728]\t@ 0x2d8\n+\tvstr\td7, [r7, #376]\t@ 0x178\n+\tvadd.f64\td7, d6, d3\n+\tvsub.f64\td6, d6, d3\n+\tvldr\td3, [r7, #336]\t@ 0x150\n+\tvstr\td6, [r7, #640]\t@ 0x280\n+\tvadd.f64\td6, d1, d5\n+\tvsub.f64\td5, d1, d5\n+\tvldr\td1, [r3, #-8]\n+\tvstr\td3, [r2, #-8]\n+\tadd\tr2, r6\n+\tstr.w\tr2, [r7, #672]\t@ 0x2a0\n+\tldr.w\tr3, [r7, #312]\t@ 0x138\n+\tldr.w\tr2, [r7, #568]\t@ 0x238\n+\tldr.w\tr5, [r7, #520]\t@ 0x208\n+\tvldr\td3, [r3, #-8]\n+\tvstr\td3, [r7, #592]\t@ 0x250\n+\tvldr\td3, [r7, #576]\t@ 0x240\n+\tvstr\td3, [r2, #-8]\n+\tvmul.f64\td3, d8, d5\n+\tvstr\td2, [r3, #-8]\n+\tvmul.f64\td5, d15, d5\n+\tldr.w\tr3, [r7, #528]\t@ 0x210\n+\tvldr\td2, [r7, #552]\t@ 0x228\n+\tldr.w\tr2, [r7, #716]\t@ 0x2cc\n+\tvstr\td2, [r3, #-8]\n+\tvstr\td4, [r5, #-8]\n+\tvadd.f64\td4, d7, d6\n+\tvsub.f64\td6, d7, d6\n+\tvldr\td2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr5, [r7, #508]\t@ 0x1fc\n+\tldr.w\tr3, [r7, #504]\t@ 0x1f8\n+\tvmul.f64\td7, d6, d2\n+\tvldr\td6, [r7, #640]\t@ 0x280\n+\tvmov.f64\td2, #80\t@ 0x3e800000 0.250\n+\tvstr\td3, [r7, #640]\t@ 0x280\n+\tvldr\td3, [r7, #608]\t@ 0x260\n+\tvmla.f64\td5, d8, d6\n+\tvstr\td7, [r7, #728]\t@ 0x2d8\n+\tvadd.f64\td7, d4, d9\n+\tvmls.f64\td9, d4, d2\n+\tvldr\td4, [r5, #-8]\n+\tvstr\td0, [r3, #-8]\n+\tadds\tr5, r2, r6\n+\tvmul.f64\td0, d15, d6\n+\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n+\tvstr\td7, [r2, #-8]\n \tldr.w\tr2, [r7, #496]\t@ 0x1f0\n-\tldr.w\tr0, [r7, #584]\t@ 0x248\n-\tvmov.f64\td30, d27\n-\tvfma.f64\td27, d12, d20\n-\tvfnms.f64\td30, d8, d20\n-\tadds\tr1, r3, r0\n-\tvmov.f64\td20, d21\n-\tvmov.f64\td26, d29\n-\tvfms.f64\td20, d24, d5\n-\tvstr\td23, [r3, #-8]\n-\tvfma.f64\td26, d24, d5\n-\tvadd.f64\td24, d24, d21\n-\tvmov.f64\td25, d22\n-\tvfma.f64\td22, d18, d11\n-\tvfma.f64\td25, d10, d18\n+\tvstr\td4, [r7, #576]\t@ 0x240\n+\tvstr\td5, [r7, #568]\t@ 0x238\n+\tldr.w\tr5, [r7, #304]\t@ 0x130\n+\tvldr\td4, [r2, #-8]\n+\tvldr\td7, [ip, #-8]\n+\tvadd.f64\td5, d3, d4\n+\tvsub.f64\td4, d3, d4\n+\tvldr\td3, [r7, #640]\t@ 0x280\n+\tvadd.f64\td2, d1, d7\n+\tvsub.f64\td7, d1, d7\n+\tvldr\td1, [r5, #-8]\n+\tvsub.f64\td6, d0, d3\n+\tvsub.f64\td3, d3, d0\n+\tvadd.f64\td0, d5, d2\n+\tvsub.f64\td5, d5, d2\n+\tvstr\td6, [r7, #640]\t@ 0x280\n+\tvldr\td6, [r7, #728]\t@ 0x2d8\n+\tvstr\td3, [r7, #528]\t@ 0x210\n+\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tvadd.f64\td3, d6, d9\n+\tvldr\td2, [r7, #744]\t@ 0x2e8\n+\tvsub.f64\td6, d9, d6\n+\tvmov.f64\td9, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr3, [r7, #560]\t@ 0x230\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td2, d0, d9\n+\tvstr\td3, [r7, #608]\t@ 0x260\n+\tvadd.f64\td0, d0, d1\n+\tvldr\td3, [r2, #-8]\n+\tvmul.f64\td9, d15, d7\n+\tvmla.f64\td9, d8, d4\n+\tvmul.f64\td7, d8, d7\n+\tvmul.f64\td4, d15, d4\n+\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tvstr\td3, [r7, #728]\t@ 0x2d8\n+\tvldr\td3, [r7, #376]\t@ 0x178\n+\tvstr\td3, [r5, #-8]\n+\tldr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tvldr\td3, [r7, #640]\t@ 0x280\n+\tvstr\td0, [r5, #-8]\n+\tvsub.f64\td0, d1, d2\n+\tvadd.f64\td2, d3, d2\n+\tadd\tr5, r6\n+\tstr.w\tr5, [r7, #680]\t@ 0x2a8\n+\tldr.w\tr5, [r7, #508]\t@ 0x1fc\n+\tvsub.f64\td2, d2, d1\n+\tvldr\td1, [r7, #528]\t@ 0x210\n+\tvadd.f64\td3, d2, d5\n+\tvadd.f64\td2, d5, d0\n+\tvsub.f64\td0, d0, d5\n+\tvstr\td3, [r7, #552]\t@ 0x228\n+\tvadd.f64\td1, d1, d0\n+\tvldr\td3, [r7, #640]\t@ 0x280\n+\tvadd.f64\td3, d3, d0\n+\tvsub.f64\td0, d4, d7\n+\tvsub.f64\td7, d7, d4\n+\tvstr\td1, [r7, #528]\t@ 0x210\n+\tvldr\td4, [r7, #608]\t@ 0x260\n+\tvldr\td1, [r7, #568]\t@ 0x238\n+\tvadd.f64\td0, d0, d6\n+\tvadd.f64\td7, d7, d6\n+\tvadd.f64\td6, d4, d9\n+\tvsub.f64\td4, d4, d9\n+\tvsub.f64\td9, d2, d1\n+\tvadd.f64\td5, d1, d2\n+\tvstr\td9, [r7, #640]\t@ 0x280\n+\tvsub.f64\td9, d1, d2\n+\tvmul.f64\td2, d12, d3\n+\tvldr\td1, [r7, #752]\t@ 0x2f0\n+\tvmul.f64\td3, d1, d3\n+\tvnmls.f64\td2, d1, d7\n+\tvldr\td1, [r7, #760]\t@ 0x2f8\n+\tvmla.f64\td3, d12, d7\n+\tvmul.f64\td7, d13, d5\n+\tvmul.f64\td5, d1, d5\n+\tvmla.f64\td5, d13, d4\n+\tvnmls.f64\td7, d1, d4\n+\tvstr\td5, [r3, #-8]\n+\tvldr\td5, [r7, #640]\t@ 0x280\n+\tvstr\td7, [r2, #-8]\n+\tvmul.f64\td7, d10, d6\n+\tvmul.f64\td6, d14, d6\n+\tldr.w\tr2, [r7, #488]\t@ 0x1e8\n+\tvmla.f64\td7, d5, d14\n+\tvmla.f64\td6, d9, d10\n+\tldr.w\tr3, [r7, #536]\t@ 0x218\n+\tvstr\td7, [r2, #-8]\n+\tvmul.f64\td7, d11, d0\n+\tvstr\td3, [r3, #-8]\n+\tvstr\td6, [r5, #-8]\n+\tvldr\td5, [r7, #736]\t@ 0x2e0\n+\tvldr\td6, [r7, #528]\t@ 0x210\n+\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tvldr\td4, [r7, #656]\t@ 0x290\n+\tvmla.f64\td7, d6, d5\n+\tvldr\td6, [r7, #552]\t@ 0x228\n+\tldr.w\tr2, [r7, #480]\t@ 0x1e0\n+\tvstr\td2, [r3, #-8]\n+\tldr.w\tr3, [r7, #512]\t@ 0x200\n+\tldr.w\tr5, [r7, #484]\t@ 0x1e4\n+\tvstr\td7, [ip, #-8]\n+\tvmul.f64\td7, d5, d0\n+\tvmla.f64\td7, d6, d11\n+\tvldr\td9, [r2, #-8]\n+\tldr.w\tr2, [r7, #300]\t@ 0x12c\n+\tvstr\td7, [r3, #-8]\n+\tvldr\td7, [r7, #616]\t@ 0x268\n+\tldr.w\tr3, [r7, #296]\t@ 0x128\n+\tvldr\td3, [r5, #-8]\n+\tvsub.f64\td1, d7, d4\n+\tvsub.f64\td2, d4, d7\n+\tvldr\td4, [r7, #728]\t@ 0x2d8\n+\tvldr\td7, [r7, #592]\t@ 0x250\n+\tvldr\td0, [r3, #-8]\n+\tvldr\td6, [r2, #-8]\n+\tvadd.f64\td5, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvstr\td7, [r7, #616]\t@ 0x268\n+\tvadd.f64\td7, d0, d9\n+\tvsub.f64\td9, d0, d9\n+\tvldr\td0, [r7, #352]\t@ 0x160\n+\tvmul.f64\td4, d10, d0\n+\tvmla.f64\td4, d1, d14\n+\tvldr\td1, [r7, #576]\t@ 0x240\n+\tvstr\td4, [r3, #-8]\n+\tvmul.f64\td4, d14, d0\n+\tvmla.f64\td4, d2, d10\n+\tvldr\td2, [r7, #624]\t@ 0x270\n+\tvsub.f64\td0, d2, d1\n+\tvstr\td4, [r2, #-8]\n+\tvadd.f64\td4, d6, d3\n+\tvsub.f64\td6, d6, d3\n+\tvadd.f64\td3, d2, d1\n+\tvadd.f64\td1, d7, d5\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td2, [r7, #744]\t@ 0x2e8\n+\tvadd.f64\td5, d4, d3\n+\tvsub.f64\td4, d4, d3\n+\tvmul.f64\td7, d7, d2\n+\tvmul.f64\td3, d4, d2\n+\tvldr\td2, [r4, #-8]\n+\tvmul.f64\td4, d15, d6\n+\tvstr\td3, [r7, #656]\t@ 0x290\n+\tvmul.f64\td3, d8, d0\n+\tvmul.f64\td0, d15, d0\n+\tvmla.f64\td0, d8, d6\n+\tvmov.f64\td6, #80\t@ 0x3e800000 0.250\n+\tvstr\td0, [r7, #728]\t@ 0x2d8\n+\tvmov.f64\td0, d6\n+\tvmul.f64\td6, d1, d6\n+\tvadd.f64\td1, d1, d2\n+\tvstr\td1, [r7, #592]\t@ 0x250\n+\tvldr\td1, [r0, #-8]\n+\tvstr\td1, [r7, #640]\t@ 0x280\n+\tvmls.f64\td1, d5, d0\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr5, [r7, #604]\t@ 0x25c\n+\tvmov.f64\td0, d1\n+\tvldr\td1, [r7, #640]\t@ 0x280\n+\tvadd.f64\td5, d5, d1\n+\tvmul.f64\td1, d15, d9\n+\tvstr\td5, [r7, #608]\t@ 0x260\n+\tvsub.f64\td5, d4, d3\n+\tvsub.f64\td3, d3, d4\n+\tvsub.f64\td4, d2, d6\n+\tvadd.f64\td6, d5, d6\n+\tvsub.f64\td6, d6, d2\n+\tvldr\td2, [r7, #616]\t@ 0x268\n+\tvadd.f64\td6, d6, d7\n+\tvstr\td6, [r7, #584]\t@ 0x248\n+\tvmul.f64\td6, d15, d2\n+\tvmla.f64\td6, d8, d9\n+\tvstr\td6, [r7, #640]\t@ 0x280\n+\tvmul.f64\td6, d8, d2\n+\tvadd.f64\td2, d7, d4\n+\tvsub.f64\td4, d4, d7\n+\tvsub.f64\td9, d1, d6\n+\tvsub.f64\td6, d6, d1\n+\tvadd.f64\td5, d5, d4\n+\tvadd.f64\td4, d3, d4\n+\tvldr\td3, [r7, #656]\t@ 0x290\n+\tvstr\td4, [r7, #616]\t@ 0x268\n+\tvsub.f64\td4, d0, d3\n+\tvadd.f64\td7, d3, d0\n+\tvldr\td0, [r7, #632]\t@ 0x278\n+\tvadd.f64\td3, d9, d4\n+\tvldr\td9, [r7, #728]\t@ 0x2d8\n+\tvadd.f64\td6, d6, d4\n+\tvadd.f64\td4, d9, d2\n+\tvldr\td9, [r7, #392]\t@ 0x188\n+\tvstr\td3, [r7, #624]\t@ 0x270\n+\tvldr\td3, [r7, #640]\t@ 0x280\n+\tvadd.f64\td1, d7, d3\n+\tvsub.f64\td7, d7, d3\n+\tvsub.f64\td3, d0, d9\n+\tvsub.f64\td9, d9, d0\n+\tvstr\td9, [r7, #656]\t@ 0x290\n+\tvldr\td9, [r7, #728]\t@ 0x2d8\n+\tvsub.f64\td0, d9, d2\n+\tvsub.f64\td2, d2, d9\n+\tvldr\td9, [r7, #384]\t@ 0x180\n+\tvstr\td0, [r7, #728]\t@ 0x2d8\n+\tvstr\td2, [r7, #640]\t@ 0x280\n+\tvmul.f64\td2, d12, d5\n+\tvldr\td0, [r7, #752]\t@ 0x2f0\n+\tvmul.f64\td5, d0, d5\n+\tvnmls.f64\td2, d0, d6\n+\tvmla.f64\td5, d12, d6\n+\tvldr\td0, [r7, #760]\t@ 0x2f8\n+\tvmul.f64\td6, d13, d4\n+\tvmul.f64\td4, d0, d4\n+\tvmla.f64\td4, d13, d7\n+\tvnmls.f64\td6, d0, d7\n+\tvmul.f64\td7, d9, d14\n+\tvmla.f64\td7, d3, d10\n+\tvldr\td3, [r7, #608]\t@ 0x260\n+\tvstr\td7, [r0, #-8]\n+\tvmul.f64\td7, d9, d10\n+\tvldr\td9, [r7, #656]\t@ 0x290\n+\tvstr\td3, [r3, #-8]\n+\tvstr\td6, [r5, #-8]\n+\tvmla.f64\td7, d9, d14\n+\tldr.w\tr5, [r7, #600]\t@ 0x258\n+\tvstr\td7, [r4, #-8]\n+\tadds\tr4, r3, r6\n+\tvldr\td7, [r7, #592]\t@ 0x250\n+\tstr.w\tr4, [r7, #696]\t@ 0x2b8\n+\tvstr\td7, [r1, #-8]\n+\tadd\tr1, r6\n+\tvstr\td4, [r5, #-8]\n+\tvmul.f64\td7, d14, d1\n+\tstr.w\tr1, [r7, #656]\t@ 0x290\n+\tvldr\td3, [r7, #728]\t@ 0x2d8\n+\tldr.w\tr1, [r7, #484]\t@ 0x1e4\n+\tvldr\td6, [r7, #640]\t@ 0x280\n+\tvmla.f64\td7, d3, d10\n+\tldr.w\tr2, [r7, #540]\t@ 0x21c\n+\tldr.w\tr4, [r7, #480]\t@ 0x1e0\n+\tvldr\td0, [r7, #736]\t@ 0x2e0\n+\tldr.w\tr3, [r7, #516]\t@ 0x204\n+\tldr.w\tr5, [r7, #548]\t@ 0x224\n+\tldr.w\tr0, [r7, #664]\t@ 0x298\n+\tvstr\td7, [r1, #-8]\n+\tvmul.f64\td7, d10, d1\n+\tvmla.f64\td7, d6, d14\n+\tvldr\td6, [r7, #584]\t@ 0x248\n+\tvstr\td2, [r5, #-8]\n+\tvstr\td7, [r4, #-8]\n+\tvstr\td5, [r2, #-8]\n+\tvldr\td5, [r7, #624]\t@ 0x270\n+\tldr.w\tr2, [r7, #496]\t@ 0x1f0\n+\tvmul.f64\td7, d0, d5\n+\tvmla.f64\td7, d6, d11\n+\tvldr\td6, [r7, #616]\t@ 0x268\n+\tvstr\td7, [r3, #-8]\n+\tvmul.f64\td7, d11, d5\n+\tvmla.f64\td7, d6, d0\n \tldr.w\tr3, [r7, #408]\t@ 0x198\n-\tstr.w\tr1, [r7, #520]\t@ 0x208\n-\tadds\tr1, r2, r0\n-\tvstr\td24, [r2, #-8]\n-\tldr.w\tr2, [r7, #440]\t@ 0x1b8\n-\tldr.w\tr6, [r7, #468]\t@ 0x1d4\n-\tvmov.f64\td23, d20\n-\tvfma.f64\td20, d11, d19\n-\tvfma.f64\td23, d10, d19\n-\tvsub.f64\td21, d26, d21\n-\tvfma.f64\td21, d10, d19\n-\tstr.w\tr1, [r7, #496]\t@ 0x1f0\n-\tvsub.f64\td19, d25, d16\n-\tvadd.f64\td25, d25, d16\n-\tvadd.f64\td16, d22, d27\n-\tvadd.f64\td22, d22, d30\n-\tvadd.f64\td18, d29, d20\n-\tvadd.f64\td20, d20, d31\n-\tvadd.f64\td24, d17, d23\n-\tvsub.f64\td26, d17, d23\n-\tvsub.f64\td23, d23, d17\n-\tvmul.f64\td21, d14, d21\n-\tvfma.f64\td21, d0, d22\n-\tvnmul.f64\td17, d18, d15\n-\tvmul.f64\td18, d1, d18\n-\tvnmul.f64\td27, d24, d4\n-\tvmul.f64\td24, d2, d24\n-\tvmul.f64\td23, d23, d3\n-\tvfma.f64\td24, d4, d19\n-\tvfma.f64\td23, d13, d25\n-\tvfma.f64\td18, d15, d16\n-\tvfma.f64\td27, d2, d19\n-\tvmul.f64\td26, d26, d13\n-\tvfma.f64\td26, d3, d25\n-\tvfma.f64\td17, d1, d16\n-\tvmul.f64\td20, d20, d0\n-\tvfma.f64\td20, d14, d22\n-\tvstr\td24, [r2, #-8]\n-\tvstr\td23, [r4, #-8]\n-\tldr.w\tr2, [r7, #424]\t@ 0x1a8\n-\tvstr\td18, [r3, #-8]\n-\tldr.w\tr3, [r7, #392]\t@ 0x188\n-\tvstr\td27, [r6, #-8]\n-\tldr.w\tr6, [r7, #384]\t@ 0x180\n-\tvstr\td26, [r5, #-8]\n-\tldr.w\tr5, [r7, #576]\t@ 0x240\n-\tvstr\td17, [r2, #-8]\n-\tvstr\td21, [r3, #-8]\n-\tldr.w\tr3, [r7, #360]\t@ 0x168\n-\tvstr\td20, [r6, #-8]\n-\tcmp\tr5, r3\n-\tbne.w\tfe84 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x215c>\n-\tmov\tr6, r0\n-\tb.w\tfc1e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ef6>\n-\tldr.w\tr2, [r7, #148]\t@ 0x94\n-\tldr\tr1, [r7, #64]\t@ 0x40\n-\tudiv\tr2, r2, r1\n-\tmov\tr6, r2\n-\tldr.w\tr2, [r7, #164]\t@ 0xa4\n-\tcmp\tr2, r4\n-\tble.w\tef9a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1272>\n-\tb.w\tfc7c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1f54>\n-\tmov\tr9, fp\n-\tldr.w\tfp, [r7, #24]\n-\tmov\tr8, sl\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tcmp\tr0, r3\n+\tvstr\td7, [r2, #-8]\n+\tbne.w\t10a48 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2290>\n+\tb.w\t107a6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1fee>\n+\tldr\tr1, [r7, #48]\t@ 0x30\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tldr.w\tr3, [r7, #168]\t@ 0xa8\n+\tmov\tr1, r0\n+\tcmp\tr3, r5\n+\tble.w\tfaa0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x12e8>\n+\tb.w\t10802 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204a>\n+\tmov\tfp, r6\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tldr.w\tr2, [r7, #140]\t@ 0x8c\n \tadds\tr3, #1\n-\tstr\tr3, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n \tcmp\tr2, r3\n-\tbge.w\tee98 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1170>\n-\tmov\tlr, r8\n-\tmov\tr4, r9\n-\tldrd\tr3, r8, [r7, #28]\n-\tb.w\te702 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x9da>\n-\tnegs\tr4, r1\n-\tnegs\tr0, r0\n-\tcmp\tr1, #0\n-\tudiv\tr0, r4, r0\n-\tble.w\teed2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11aa>\n-\tb.n\t108b2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2b8a>\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tbge.w\tf990 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x11d8>\n+\tldrd\tsl, r8, [r7, #12]\n+\tmov\tr6, fp\n+\tb.w\tf1fe <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa46>\n+\tnegs\tr1, r3\n+\tnegs\tr0, r4\n+\tbl\t0 <__aeabi_uidiv>\n+ R_ARM_THM_CALL\t__aeabi_uidiv\n+\tcmp\tr4, #0\n+\tstr\tr0, [r7, #124]\t@ 0x7c\n+\tble.w\tf9dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1224>\n+\tb.n\t116dc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f24>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, #0\n-\tblt.n\t10970 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2c48>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tblt.n\t1179a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fe2>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tmov\tr1, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t1090c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2be4>\n+\tbeq.n\t11736 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f7e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t108fe <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2bd6>\n+\tbne.n\t11728 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f70>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 1091c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2bf4>\n+\tcbz\tr3, 11746 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f8e>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tadd\tr0, sp, #24\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n \tmov\tr1, r0\n \tmov.w\tip, r3, lsl #3\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadds\tr3, #1\n-\tldr.w\tr5, [r7, #580]\t@ 0x244\n+\tldr.w\tr5, [r7, #728]\t@ 0x2d8\n \tadd\tr2, ip\n \tcmp\tr5, r3\n-\tvstmia\tr1!, {d16}\n-\tbge.n\t1092e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2c06>\n-\tstr.w\tr0, [r7, #528]\t@ 0x210\n-\tb.n\t1097a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2c52>\n+\tvstmia\tr1!, {d7}\n+\tbge.n\t11758 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fa0>\n+\tstr.w\tr0, [r7, #688]\t@ 0x2b0\n+\tb.n\t117a4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fec>\n \tldr.w\tr1, [r7, #160]\t@ 0xa0\n \tcmp\tr1, #0\n-\tble.w\te732 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa0a>\n-\tldr\tr3, [r7, #100]\t@ 0x64\n+\tble.w\tf22e <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa76>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tlsls\tr0, r4, #3\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n \tadd.w\tr1, r3, r1, lsl #3\n \tldrd\tr4, r5, [r3], #8\n \tstrd\tr4, r5, [r2]\n \tadd\tr2, r0\n \tcmp\tr1, r3\n-\tbne.n\t1095e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2c36>\n-\tb.w\te732 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa0a>\n-\tadd.w\tr3, r7, #608\t@ 0x260\n-\tstr.w\tr3, [r7, #528]\t@ 0x210\n+\tbne.n\t11788 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fd0>\n+\tb.w\tf22e <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa76>\n+\tadd.w\tr3, r7, #792\t@ 0x318\n+\tstr.w\tr3, [r7, #688]\t@ 0x2b0\n \tmov\tr0, r3\n \tcmp\tr4, #1\n-\tbne.w\t10eec <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31c4>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tbne.w\t11c28 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3470>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr2, [r9]\n-\tvstr\td3, [r7, #496]\t@ 0x1f0\n \tldr\tr3, [r3, #0]\n-\tvstr\td0, [r7, #504]\t@ 0x1f8\n-\tvstr\td1, [r7, #512]\t@ 0x200\n-\tvstr\td2, [r7, #520]\t@ 0x208\n \tstr\tr2, [sp, #16]\n \tldr.w\tr2, [r8]\n \tstrd\tfp, r2, [sp, #8]\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tldr.w\tr1, [r7, #344]\t@ 0x158\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #4]\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n+\tldr.w\tr5, [r7, #772]\t@ 0x304\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n-\tvldr\td2, [r7, #520]\t@ 0x208\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tcmp\tr3, #0\n-\tvldr\td1, [r7, #512]\t@ 0x200\n-\tvldr\td0, [r7, #504]\t@ 0x1f8\n-\tvldr\td3, [r7, #496]\t@ 0x1f0\n-\tble.n\t10a02 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2cda>\n-\tldr.w\tr2, [r7, #368]\t@ 0x170\n-\tldr.w\tr3, [r7, #528]\t@ 0x210\n-\tldr.w\tr1, [r7, #248]\t@ 0xf8\n+\tble.n\t1180c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3054>\n+\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tldr.w\tr3, [r7, #688]\t@ 0x2b0\n+\tldr.w\tr1, [r7, #252]\t@ 0xfc\n \tlsls\tr0, r2, #3\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n \tadd.w\tr1, r3, r1, lsl #3\n-\tvldmia\tr3!, {d16}\n-\tvstr\td16, [r2]\n+\tvldmia\tr3!, {d7}\n+\tvstr\td7, [r2]\n \tcmp\tr3, r1\n \tadd\tr2, r0\n-\tbne.n\t109ee <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2cc6>\n+\tbne.n\t117f8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3040>\n \tcmp\tr4, #1\n-\tbne.w\t10c5c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f34>\n+\tbne.w\t11a5a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32a2>\n \tcmp.w\tfp, #31\n-\tldr.w\tsp, [r7, #560]\t@ 0x230\n-\tbgt.n\t10ab8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d90>\n+\tldr.w\tsp, [r7, #768]\t@ 0x300\n+\tbgt.n\t118b8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3100>\n \tmovs\tr2, #2\n \tlsl.w\tr2, r2, fp\n \tadd.w\tfp, r2, #1\n-\tb.w\tdeba <__gridxc_gpfa_core_dp_MOD_gpfa_+0x192>\n-\tldr.w\tr1, [r7, #248]\t@ 0xf8\n+\tb.w\te96e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1b6>\n+\tldr.w\tr1, [r7, #252]\t@ 0xfc\n \tcmp\tr1, #0\n-\tble.w\te72c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa04>\n+\tble.w\tf228 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa70>\n \tmov\tr2, r3\n-\tldr\tr3, [r7, #104]\t@ 0x68\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tlsls\tr0, r2, #3\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n \tadd.w\tr1, r3, r1, lsl #3\n \tldrd\tr8, r9, [r3], #8\n \tstrd\tr8, r9, [r2]\n \tadd\tr2, r0\n \tcmp\tr1, r3\n-\tbne.n\t10a32 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d0a>\n-\tb.w\te72c <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa04>\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tbne.n\t1183c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3084>\n+\tb.w\tf228 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa70>\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tcmp\tr3, #0\n-\tblt.w\t10f6c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3244>\n+\tblt.w\t11c88 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x34d0>\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tmov\tr1, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t10a74 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d4c>\n+\tbeq.n\t1187e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30c6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10a66 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d3e>\n+\tbne.n\t11870 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30b8>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10a84 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d5c>\n+\tcbz\tr3, 1188e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30d6>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tadd\tr3, sp, #24\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n-\tmov\tr1, r3\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n+\tadd\tr5, sp, #24\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n \tlsls\tr0, r4, #3\n \tmovs\tr3, #0\n-\tmov\tr5, fp\n-\tmov\tip, r1\n-\tldr.w\tr1, [r7, #568]\t@ 0x238\n+\tmov\tip, fp\n+\tmov\tlr, r5\n+\tldr.w\tr1, [r7, #720]\t@ 0x2d0\n \tadds\tr3, #1\n \tldrd\tsl, fp, [r2]\n \tcmp\tr1, r3\n \tadd\tr2, r0\n-\tstrd\tsl, fp, [ip], #8\n-\tbge.n\t10a98 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2d70>\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n-\tmov\tfp, r5\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\tb.w\tdf86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x25e>\n-\tmovs\tr2, #0\n-\tmov.w\tfp, #1\n+\tstrd\tsl, fp, [lr], #8\n+\tbge.n\t1189c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30e4>\n+\tmov\tfp, ip\n+\tstr\tr5, [r7, #68]\t@ 0x44\n+\tb.w\te9fa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x242>\n \tcmp.w\tsl, #0\n-\tble.w\t10fae <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3286>\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\titt\tgt\n+\tmovgt\tr2, #0\n+\tmovgt.w\tfp, #1\n+\tble.w\t11cc8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3510>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, #0\n-\tblt.w\t10d3a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3012>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tblt.w\t11b16 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x335e>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tmov\tr0, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tcmp\tr0, r1\n-\tbeq.n\t10af6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2dce>\n+\tbeq.n\t118f8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3140>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10ae8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2dc0>\n+\tbne.n\t118ea <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3132>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10b06 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2dde>\n+\tcbz\tr3, 11908 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3150>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tadd\tr0, sp, #24\n-\tldr.w\tr1, [r7, #348]\t@ 0x15c\n+\tldr.w\tr1, [r7, #404]\t@ 0x194\n \tmov\tip, r0\n \tmov.w\tlr, r3, lsl #3\n \tmovs\tr3, #0\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr3, #1\n-\tldr.w\tr5, [r7, #580]\t@ 0x244\n+\tldr.w\tr5, [r7, #728]\t@ 0x2d8\n \tadd\tr1, lr\n \tcmp\tr5, r3\n-\tvstmia\tip!, {d16}\n-\tbge.n\t10b18 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2df0>\n-\tstr.w\tr0, [r7, #536]\t@ 0x218\n-\tb.n\t10d44 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x301c>\n-\tldr.w\tr3, [r7, #580]\t@ 0x244\n+\tvstmia\tip!, {d7}\n+\tbge.n\t1191a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3162>\n+\tstr.w\tr0, [r7, #696]\t@ 0x2b8\n+\tb.n\t11b20 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3368>\n+\tldr.w\tr3, [r7, #728]\t@ 0x2d8\n \tcmp\tr3, #0\n-\tblt.w\t10f7a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3252>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tblt.w\t11c94 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x34dc>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tmov\tr1, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t10b62 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e3a>\n+\tbeq.n\t11964 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31ac>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10b54 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e2c>\n+\tbne.n\t11956 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x319e>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10b72 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e4a>\n+\tcbz\tr3, 11974 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31bc>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tadd\tr6, sp, #24\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n \tmov\tr5, fp\n \tmov\tip, r6\n \tlsls\tr0, r3, #3\n \tmovs\tr3, #0\n-\tldr.w\tr1, [r7, #580]\t@ 0x244\n+\tldr.w\tr1, [r7, #728]\t@ 0x2d8\n \tadds\tr3, #1\n \tldrd\tsl, fp, [r2]\n \tcmp\tr1, r3\n \tadd\tr2, r0\n \tstrd\tsl, fp, [ip], #8\n-\tbge.n\t10b84 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e5c>\n+\tbge.n\t11986 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x31ce>\n \tmov\tfp, r5\n-\tstr\tr6, [r7, #104]\t@ 0x68\n-\tb.w\tdf78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x250>\n+\tstr\tr6, [r7, #72]\t@ 0x48\n+\tb.w\te9f0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x238>\n+\tmovs\tr2, #2\n+\tcmp.w\tsl, #0\n+\tit\tgt\n+\tstrgt.w\tsp, [r7, #768]\t@ 0x300\n+\tlsl.w\tr2, r2, fp\n+\tadd.w\tfp, r2, #1\n+\tbgt.w\te982 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ca>\n+\tb.w\te9d2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x21a>\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tmov\tr1, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t10bc6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e9e>\n+\tbeq.n\t119e4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x322c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10bb8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e90>\n+\tbne.n\t119d6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x321e>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10bd6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2eae>\n+\tcbz\tr3, 119f4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x323c>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #24\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n-\tmov\tr1, r3\n-\tstr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tip, [r7, #400]\t@ 0x190\n \tlsls\tr5, r4, #3\n-\tmovs\tr3, #0\n-\tvldr\td16, [r2]\n-\tadds\tr3, #1\n-\tldr.w\tr6, [r7, #568]\t@ 0x238\n-\tadd\tr2, r5\n-\tcmp\tr6, r3\n-\tvstmia\tr1!, {d16}\n-\tbge.n\t10be6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2ebe>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tmov\tlr, r3\n+\tmovs\tr1, #0\n+\tstr.w\tr3, [r7, #704]\t@ 0x2c0\n+\tldrd\tr2, r3, [ip]\n+\tstrd\tr2, r3, [lr], #8\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n+\tadds\tr1, #1\n+\tadd\tip, r5\n+\tcmp\tr3, r1\n+\tbge.n\t11a04 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x324c>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr2, [r9]\n-\tvstr\td2, [r7, #496]\t@ 0x1f0\n \tldr\tr3, [r3, #0]\n-\tvstr\td1, [r7, #504]\t@ 0x1f8\n-\tvstr\td0, [r7, #512]\t@ 0x200\n-\tvstr\td3, [r7, #520]\t@ 0x208\n \tstr\tr2, [sp, #16]\n \tldr.w\tr2, [r8]\n \tstrd\tfp, r2, [sp, #8]\n-\tldr.w\tr6, [r7, #596]\t@ 0x254\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tldr.w\tr1, [r7, #544]\t@ 0x220\n+\tldr.w\tr6, [r7, #780]\t@ 0x30c\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n+\tldr.w\tr1, [r7, #704]\t@ 0x2c0\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #4]\n-\tldr.w\tr6, [r7, #588]\t@ 0x24c\n+\tldr.w\tr6, [r7, #772]\t@ 0x304\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tvldr\td3, [r7, #520]\t@ 0x208\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tcmp\tr3, #1\n-\tvldr\td0, [r7, #512]\t@ 0x200\n-\tvldr\td1, [r7, #504]\t@ 0x1f8\n-\tvldr\td2, [r7, #496]\t@ 0x1f0\n-\tbeq.n\t10c66 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f3e>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tbeq.n\t11a64 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32ac>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tcmp\tr3, #0\n-\tbgt.w\t109d8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2cb0>\n+\tbgt.w\t117e2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x302a>\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tcmp\tr3, #0\n-\tble.n\t10c86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f5e>\n+\tble.n\t11a84 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32cc>\n \tlsls\tr5, r4, #3\n-\tldr.w\tr3, [r7, #544]\t@ 0x220\n+\tldr.w\tr3, [r7, #704]\t@ 0x2c0\n \tldr.w\tr1, [r7, #160]\t@ 0xa0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n \tadd.w\tr1, r3, r1, lsl #3\n \tmov\tr6, r1\n \tldrd\tr0, r1, [r3], #8\n \tstrd\tr0, r1, [r2]\n \tadd\tr2, r5\n \tcmp\tr3, r6\n-\tbne.n\t10c78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f50>\n+\tbne.n\t11a76 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32be>\n \tcmp.w\tfp, #31\n-\tldr.w\tsp, [r7, #560]\t@ 0x230\n-\tble.w\t10a0c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2ce4>\n-\tmov.w\tfp, #1\n-\tmovs\tr2, #0\n-\tb.w\tdeba <__gridxc_gpfa_core_dp_MOD_gpfa_+0x192>\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tsp, [r7, #768]\t@ 0x300\n+\titt\tgt\n+\tmovgt.w\tfp, #1\n+\tmovgt\tr2, #0\n+\tbgt.w\te96e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1b6>\n+\tb.n\t11816 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x305e>\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tcmp\tr3, #0\n-\tbge.w\t10dd2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30aa>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tadd.w\tr5, r7, #624\t@ 0x270\n+\tbge.n\t11b8e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33d6>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tr5, r7, #808\t@ 0x328\n \tldr.w\tr1, [r9]\n-\tvstr\td3, [r7, #520]\t@ 0x208\n \tldr\tr3, [r3, #0]\n-\tvstr\td0, [r7, #528]\t@ 0x210\n-\tvstr\td1, [r7, #544]\t@ 0x220\n-\tvstr\td2, [r7, #552]\t@ 0x228\n \tstr\tr1, [sp, #16]\n \tldr.w\tr1, [r8]\n \tstrd\tsl, r1, [sp, #8]\n \tmov\tr1, r5\n-\tldr.w\tr6, [r7, #596]\t@ 0x254\n+\tldr.w\tr6, [r7, #780]\t@ 0x30c\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #4]\n-\tldr.w\tr6, [r7, #588]\t@ 0x24c\n+\tldr.w\tr6, [r7, #772]\t@ 0x304\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #0]\n-\tbl\t30a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tvldr\td2, [r7, #552]\t@ 0x228\n+\tbl\t3338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tcmp\tr3, #1\n-\tvldr\td1, [r7, #544]\t@ 0x220\n-\tvldr\td0, [r7, #528]\t@ 0x210\n-\tvldr\td3, [r7, #520]\t@ 0x208\n-\tbeq.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n-\tstr.w\tr5, [r7, #552]\t@ 0x228\n+\tbeq.w\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n+\tstr.w\tr5, [r7, #716]\t@ 0x2cc\n \tcmp\tr3, #0\n-\tbgt.n\t10da6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x307e>\n+\tbgt.n\t11b62 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33aa>\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tcmp\tr3, #0\n-\tble.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n+\tble.w\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n \tlsls\tr5, r4, #3\n-\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr3, [r7, #716]\t@ 0x2cc\n \tldr.w\tr1, [r7, #160]\t@ 0xa0\n-\tldr.w\tr2, [r7, #344]\t@ 0x158\n+\tldr.w\tr2, [r7, #400]\t@ 0x190\n \tadd.w\tr1, r3, r1, lsl #3\n \tmov\tr6, r1\n \tldrd\tr0, r1, [r3], #8\n \tstrd\tr0, r1, [r2]\n \tadd\tr2, r5\n \tcmp\tr3, r6\n-\tbne.n\t10d28 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3000>\n-\tb.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n-\tadd.w\tr3, r7, #608\t@ 0x260\n-\tstr.w\tr3, [r7, #536]\t@ 0x218\n+\tbne.n\t11b04 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x334c>\n+\tb.w\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n+\tadd.w\tr3, r7, #792\t@ 0x318\n+\tstr.w\tr3, [r7, #696]\t@ 0x2b8\n \tmov\tr0, r3\n-\tldr.w\tr3, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [r7, #744]\t@ 0x2e8\n \tcmp\tr4, #1\n \tadd.w\tr2, r3, r2, lsl #3\n-\tbne.n\t10c9c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f74>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tbne.n\t11a9a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32e2>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr1, [r9]\n-\tvstr\td3, [r7, #512]\t@ 0x200\n \tldr\tr3, [r3, #0]\n-\tvstr\td0, [r7, #520]\t@ 0x208\n-\tvstr\td1, [r7, #528]\t@ 0x210\n-\tvstr\td2, [r7, #544]\t@ 0x220\n \tstr\tr1, [sp, #16]\n-\tldr.w\tr1, [r7, #344]\t@ 0x158\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tldr.w\tr5, [r8]\n \tstrd\tsl, r5, [sp, #8]\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n+\tldr.w\tr5, [r7, #780]\t@ 0x30c\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #4]\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n+\tldr.w\tr5, [r7, #772]\t@ 0x304\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #0]\n-\tbl\t30a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n-\tvldr\td2, [r7, #544]\t@ 0x220\n+\tbl\t3338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tcmp\tr3, #0\n-\tvldr\td1, [r7, #528]\t@ 0x210\n-\tvldr\td0, [r7, #520]\t@ 0x208\n-\tvldr\td3, [r7, #512]\t@ 0x200\n-\tble.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n-\tldr.w\tr2, [r7, #368]\t@ 0x170\n-\tldr.w\tr3, [r7, #536]\t@ 0x218\n-\tldr.w\tr1, [r7, #248]\t@ 0xf8\n+\tble.w\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n+\tldr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tldr.w\tr3, [r7, #696]\t@ 0x2b8\n+\tldr.w\tr1, [r7, #252]\t@ 0xfc\n \tlsls\tr0, r2, #3\n-\tldr.w\tr2, [r7, #348]\t@ 0x15c\n+\tldr.w\tr2, [r7, #404]\t@ 0x194\n \tadd.w\tr1, r3, r1, lsl #3\n-\tvldmia\tr3!, {d16}\n-\tvstr\td16, [r2]\n+\tvldmia\tr3!, {d7}\n+\tvstr\td7, [r2]\n \tcmp\tr3, r1\n \tadd\tr2, r0\n-\tbne.n\t10dbc <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3094>\n+\tbne.n\t11b78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33c0>\n \tcmp\tr4, #1\n-\tbeq.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n-\tb.n\t10d0a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fe2>\n+\tbeq.w\te9c2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x20a>\n+\tb.n\t11ae6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x332e>\n \tldr.w\tr3, [r7, #160]\t@ 0xa0\n \tmov\tr5, sp\n \tlsls\tr3, r3, #3\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tcmp\tr5, r1\n-\tbeq.n\t10df8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30d0>\n+\tbeq.n\t11bb4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33fc>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr5, sp\n \tcmp\tr5, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10dea <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30c2>\n+\tbne.n\t11ba6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33ee>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10e08 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30e0>\n+\tcbz\tr3, 11bc4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x340c>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #24\n-\tldr.w\tr1, [r7, #344]\t@ 0x158\n+\tldr.w\tr1, [r7, #400]\t@ 0x190\n \tmov\tip, r3\n-\tstr.w\tr3, [r7, #552]\t@ 0x228\n+\tstr.w\tr3, [r7, #716]\t@ 0x2cc\n \tlsls\tr5, r4, #3\n \tmovs\tr3, #0\n-\tvldr\td16, [r1]\n+\tvldr\td7, [r1]\n \tadds\tr3, #1\n-\tldr.w\tr6, [r7, #568]\t@ 0x238\n+\tldr.w\tr6, [r7, #720]\t@ 0x2d0\n \tadd\tr1, r5\n \tcmp\tr6, r3\n-\tvstmia\tip!, {d16}\n-\tbge.n\t10e18 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x30f0>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n+\tvstmia\tip!, {d7}\n+\tbge.n\t11bd4 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x341c>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n \tldr.w\tr1, [r9]\n-\tvstr\td2, [r7, #512]\t@ 0x200\n \tldr\tr3, [r3, #0]\n-\tvstr\td1, [r7, #520]\t@ 0x208\n-\tvstr\td0, [r7, #528]\t@ 0x210\n-\tvstr\td3, [r7, #544]\t@ 0x220\n \tstr\tr1, [sp, #16]\n-\tldr.w\tr1, [r7, #552]\t@ 0x228\n+\tldr.w\tr1, [r7, #716]\t@ 0x2cc\n \tldr.w\tr6, [r8]\n \tstrd\tsl, r6, [sp, #8]\n-\tldr.w\tr6, [r7, #596]\t@ 0x254\n+\tldr.w\tr6, [r7, #780]\t@ 0x30c\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #4]\n-\tldr.w\tr6, [r7, #588]\t@ 0x24c\n+\tldr.w\tr6, [r7, #772]\t@ 0x304\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #0]\n-\tbl\t30a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tvldr\td3, [r7, #544]\t@ 0x220\n+\tbl\t3338 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tcmp\tr3, #1\n-\tvldr\td0, [r7, #528]\t@ 0x210\n-\tvldr\td1, [r7, #520]\t@ 0x208\n-\tvldr\td2, [r7, #512]\t@ 0x200\n-\tbeq.w\t10d16 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fee>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tbeq.w\t11af2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x333a>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tcmp\tr3, #0\n-\tbgt.n\t10da6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x307e>\n-\tb.n\t10d0a <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2fe2>\n-\tcmp.w\tsl, #0\n-\tble.n\t10f86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x325e>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tmov\tfp, r4\n-\tldr.w\tr2, [r9]\n-\tvstr\td3, [r7, #528]\t@ 0x210\n-\tvstr\td0, [r7, #536]\t@ 0x218\n-\tvstr\td1, [r7, #544]\t@ 0x220\n-\tvstr\td2, [r7, #552]\t@ 0x228\n-\tldr\tr3, [r3, #0]\n-\tstr\tr2, [sp, #16]\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n-\tldr.w\tr1, [r8]\n-\tstrd\tsl, r1, [sp, #8]\n-\tldr.w\tr5, [r7, #596]\t@ 0x254\n-\tldrd\tr1, r0, [r7, #344]\t@ 0x158\n-\tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #4]\n-\tldr.w\tr5, [r7, #588]\t@ 0x24c\n-\tstr.w\tsp, [r7, #560]\t@ 0x230\n-\tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #0]\n-\tbl\t30a0 <__gridxc_gpfa_core_dp_MOD_gpfa3f.isra.0>\n-\tvldr\td2, [r7, #552]\t@ 0x228\n-\tvldr\td1, [r7, #544]\t@ 0x220\n-\tvldr\td0, [r7, #536]\t@ 0x218\n-\tvldr\td3, [r7, #528]\t@ 0x210\n-\tb.w\tdf2c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x204>\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tbgt.n\t11b62 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x33aa>\n+\tb.n\t11ae6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x332e>\n+\tldr.w\tr3, [r7, #720]\t@ 0x2d0\n \tcmp\tr3, #0\n-\tbge.w\t10ba0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2e78>\n-\tldr.w\tr3, [r7, #592]\t@ 0x250\n-\tadd.w\tr5, r7, #624\t@ 0x270\n+\tbge.w\t119be <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3206>\n+\tldr.w\tr3, [r7, #776]\t@ 0x308\n+\tadd.w\tr5, r7, #808\t@ 0x328\n \tldr.w\tr2, [r9]\n-\tvstr\td3, [r7, #504]\t@ 0x1f8\n \tldr\tr3, [r3, #0]\n-\tvstr\td0, [r7, #512]\t@ 0x200\n-\tvstr\td1, [r7, #520]\t@ 0x208\n-\tvstr\td2, [r7, #544]\t@ 0x220\n \tstr\tr2, [sp, #16]\n \tldr.w\tr2, [r8]\n \tstrd\tfp, r2, [sp, #8]\n-\tldr.w\tr1, [r7, #596]\t@ 0x254\n-\tldr.w\tr2, [r7, #584]\t@ 0x248\n+\tldr.w\tr1, [r7, #780]\t@ 0x30c\n+\tldr.w\tr2, [r7, #744]\t@ 0x2e8\n \tldr\tr1, [r1, #0]\n \tstr\tr1, [sp, #4]\n \tmov\tr1, r5\n-\tldr.w\tr6, [r7, #588]\t@ 0x24c\n+\tldr.w\tr6, [r7, #772]\t@ 0x304\n \tldr\tr6, [r6, #0]\n \tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_gpfa_core_dp_MOD_gpfa2f.isra.0>\n-\tldr.w\tr3, [r7, #368]\t@ 0x170\n-\tvldr\td2, [r7, #544]\t@ 0x220\n+\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n \tcmp\tr3, #1\n-\tvldr\td1, [r7, #520]\t@ 0x208\n-\tvldr\td0, [r7, #512]\t@ 0x200\n-\tvldr\td3, [r7, #504]\t@ 0x1f8\n-\tbne.n\t10f9e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3276>\n+\tbne.n\t11cb8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3500>\n \tcmp.w\tfp, #31\n-\tldr.w\tsp, [r7, #560]\t@ 0x230\n-\tble.w\t10a0c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2ce4>\n+\tldr.w\tsp, [r7, #768]\t@ 0x300\n+\tble.w\t11816 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x305e>\n \tcmp.w\tsl, #0\n-\tble.n\t10fae <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3286>\n-\tldr.w\tfp, [r7, #368]\t@ 0x170\n+\tble.n\t11cc8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x3510>\n+\tldr.w\tfp, [r7, #420]\t@ 0x1a4\n \tmovs\tr2, #0\n-\tb.w\tdece <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1a6>\n-\tadd.w\tr3, r7, #624\t@ 0x270\n-\tstr\tr3, [r7, #100]\t@ 0x64\n-\tstr.w\tr3, [r7, #580]\t@ 0x244\n-\tb.w\tdf86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x25e>\n-\tadd.w\tr3, r7, #608\t@ 0x260\n-\tstr\tr3, [r7, #104]\t@ 0x68\n+\tb.w\te982 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x1ca>\n+\tadd.w\tr3, r7, #808\t@ 0x328\n+\tstr\tr3, [r7, #68]\t@ 0x44\n+\tmov\tr5, r3\n+\tb.w\te9fa <__gridxc_gpfa_core_dp_MOD_gpfa_+0x242>\n+\tadd.w\tr3, r7, #792\t@ 0x318\n+\tstr\tr3, [r7, #72]\t@ 0x48\n \tmov\tr6, r3\n-\tb.w\tdf78 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x250>\n+\tb.w\te9f0 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x238>\n \tldr.w\tr3, [r7, #140]\t@ 0x8c\n \tcmp\tr3, #0\n-\tble.w\te736 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa0e>\n-\tldr.w\tr6, [r7, #348]\t@ 0x15c\n+\tble.w\tf232 <__gridxc_gpfa_core_dp_MOD_gpfa_+0xa7a>\n+\tldr.w\tr6, [r7, #404]\t@ 0x194\n \tmov\tfp, r4\n-\tstr.w\tsp, [r7, #96]\t@ 0x60\n-\tb.w\tdf7e <__gridxc_gpfa_core_dp_MOD_gpfa_+0x256>\n-\tldr.w\tr3, [r7, #248]\t@ 0xf8\n+\tstr.w\tsp, [r7, #64]\t@ 0x40\n+\tb.w\te9f6 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x23e>\n+\tldr.w\tr3, [r7, #252]\t@ 0xfc\n \tcmp\tr3, #0\n-\tble.w\t10c86 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2f5e>\n-\tstr.w\tr5, [r7, #544]\t@ 0x220\n-\tb.n\t109d8 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x2cb0>\n+\tble.w\t11a84 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x32cc>\n+\tstr.w\tr5, [r7, #704]\t@ 0x2c0\n+\tb.n\t117e2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x302a>\n \tmov.w\tfp, #1\n-\tb.w\tdf5c <__gridxc_gpfa_core_dp_MOD_gpfa_+0x234>\n+\tb.w\te9d2 <__gridxc_gpfa_core_dp_MOD_gpfa_+0x21a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \n-00010fbc <__gridxc_fft_gpfa_MOD_setgpfa>:\n+00011cd4 <__gridxc_fft_gpfa_MOD_setgpfa>:\n __gridxc_fft_gpfa_MOD_setgpfa():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d10}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3608]\t@ 0xe18\n-\tldr\tr2, [pc, #588]\t@ (11220 <__gridxc_fft_gpfa_MOD_setgpfa+0x264>)\n+\tldr\tr2, [pc, #596]\t@ (11f40 <__gridxc_fft_gpfa_MOD_setgpfa+0x26c>)\n \tsub\tsp, #428\t@ 0x1ac\n-\tldr\tr3, [pc, #588]\t@ (11224 <__gridxc_fft_gpfa_MOD_setgpfa+0x268>)\n-\tadd\tr4, sp, #60\t@ 0x3c\n+\tldr\tr3, [pc, #596]\t@ (11f44 <__gridxc_fft_gpfa_MOD_setgpfa+0x270>)\n+\tadd\tr6, sp, #60\t@ 0x3c\n \tadd\tr2, pc\n-\tldr\tr7, [r1, #0]\n-\tstr\tr1, [sp, #12]\n-\tmov\tr5, r4\n+\tmovs\tr4, #2\n+\tstr\tr1, [sp, #20]\n+\tmov\tr9, r6\n \tstr\tr0, [sp, #28]\n-\tmov\tip, r4\n-\tmov.w\tr8, #1\n-\tmovs\tr1, #2\n+\tmov\tr8, r6\n+\tldr.w\tfp, [r1]\n+\tmovs\tr5, #1\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr9, [pc, #568]\t@ 11228 <__gridxc_fft_gpfa_MOD_setgpfa+0x26c>\n+\tmov\tsl, r4\n+\tldr\tr7, [pc, #576]\t@ (11f48 <__gridxc_fft_gpfa_MOD_setgpfa+0x274>)\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #420]\t@ 0x1a4\n \tmov.w\tr3, #0\n-\tadd\tr9, pc\n-\tsdiv\tr3, r7, r1\n-\tmls\tr2, r1, r3, r7\n-\tcmp\tr2, #0\n-\tbne.w\t111f4 <__gridxc_fft_gpfa_MOD_setgpfa+0x238>\n-\tmov\tr7, r3\n-\tadds\tr2, #1\n-\tsdiv\tr3, r3, r1\n-\tmls\tr0, r1, r3, r7\n-\tcmp\tr0, #0\n-\tbeq.n\t11008 <__gridxc_fft_gpfa_MOD_setgpfa+0x4c>\n-\tadd\tr1, r8\n-\tadd.w\tr8, r8, #1\n-\tcmp.w\tr8, #4\n-\tstr.w\tr2, [ip], #4\n-\tbne.n\t10ffa <__gridxc_fft_gpfa_MOD_setgpfa+0x3e>\n-\tcmp\tr7, #1\n-\tbne.n\t11120 <__gridxc_fft_gpfa_MOD_setgpfa+0x164>\n-\tldrd\tr2, r1, [r4]\n+\tadd\tr7, pc\n+\tmov\tr1, sl\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr4, r1\n+\tcmp\tr1, #0\n+\tbne.w\t11f18 <__gridxc_fft_gpfa_MOD_setgpfa+0x244>\n+\tmov\tr1, sl\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, sl\n+\tadds\tr4, #1\n+\tmov\tfp, r0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.n\t11d22 <__gridxc_fft_gpfa_MOD_setgpfa+0x4e>\n+\tadd\tsl, r5\n+\tadds\tr5, #1\n+\tcmp\tr5, #4\n+\tstr.w\tr4, [r8], #4\n+\tbne.n\t11d12 <__gridxc_fft_gpfa_MOD_setgpfa+0x3e>\n+\tcmp.w\tfp, #1\n+\tbne.n\t11e44 <__gridxc_fft_gpfa_MOD_setgpfa+0x170>\n+\tldrd\tr2, r1, [r6]\n \tmovs\tr0, #3\n-\tldr\tr7, [r4, #8]\n-\tvmov.i64\td10, #0x0000000000000000\n+\tldr\tr4, [r6, #8]\n \tcmp\tr2, #31\n-\tvldr\td9, [pc, #468]\t@ 11210 <__gridxc_fft_gpfa_MOD_setgpfa+0x254>\n-\tit\tls\n+\tvldr\td9, [pc, #472]\t@ 11f30 <__gridxc_fft_gpfa_MOD_setgpfa+0x25c>\n+\tite\tls\n \tmovls\tr3, #1\n-\tit\thi\n \tmovhi\tr3, #0\n-\tmov\tfp, r5\n+\tvldr\td10, [pc, #472]\t@ 11f38 <__gridxc_fft_gpfa_MOD_setgpfa+0x264>\n \tit\tls\n \tlslls\tr3, r2\n-\tstr\tr3, [r4, #0]\n+\tstr\tr3, [r6, #0]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tmov\tr1, r7\n-\tstr\tr0, [r4, #4]\n+\tmov\tr1, r4\n+\tstr\tr0, [r6, #4]\n \tmovs\tr0, #5\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tadd.w\tr1, r4, #12\n-\tmovs\tr2, #1\n-\tstr\tr0, [r4, #8]\n-\tldr.w\tr5, [fp], #4\n-\tcmp\tr5, #1\n-\tbne.n\t11090 <__gridxc_fft_gpfa_MOD_setgpfa+0xd4>\n-\tcmp\tfp, r1\n-\tbne.n\t11064 <__gridxc_fft_gpfa_MOD_setgpfa+0xa8>\n-\tldr\tr2, [pc, #440]\t@ (1122c <__gridxc_fft_gpfa_MOD_setgpfa+0x270>)\n-\tldr\tr3, [pc, #432]\t@ (11224 <__gridxc_fft_gpfa_MOD_setgpfa+0x268>)\n+\tadd.w\tr3, r6, #12\n+\tstr\tr0, [r6, #8]\n+\tstr\tr3, [sp, #16]\n+\tmovs\tr3, #1\n+\tstr\tr3, [sp, #12]\n+\tldr.w\tfp, [r9], #4\n+\tcmp.w\tfp, #1\n+\tbne.n\t11db2 <__gridxc_fft_gpfa_MOD_setgpfa+0xde>\n+\tldr\tr3, [sp, #16]\n+\tcmp\tr9, r3\n+\tbne.n\t11d82 <__gridxc_fft_gpfa_MOD_setgpfa+0xae>\n+\tldr\tr2, [pc, #440]\t@ (11f4c <__gridxc_fft_gpfa_MOD_setgpfa+0x278>)\n+\tldr\tr3, [pc, #428]\t@ (11f44 <__gridxc_fft_gpfa_MOD_setgpfa+0x270>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #420]\t@ 0x1a4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1120a <__gridxc_fft_gpfa_MOD_setgpfa+0x24e>\n+\tbne.w\t11f2a <__gridxc_fft_gpfa_MOD_setgpfa+0x256>\n \tadd\tsp, #428\t@ 0x1ac\n \tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [sp, #12]\n-\tvmov\ts15, r5\n-\tcmp\tr5, #0\n-\tvcvt.f64.s32\td16, s15\n-\tldr\tr3, [r3, #0]\n-\tvdiv.f64\td8, d9, d16\n-\tsdiv\tr3, r3, r5\n-\tsdiv\tr0, r3, r5\n-\tmls\tr9, r5, r0, r3\n-\tble.n\t1106c <__gridxc_fft_gpfa_MOD_setgpfa+0xb0>\n+\tvmov\ts15, fp\n+\tldr\tr3, [sp, #20]\n+\tmov\tr1, fp\n+\tvcvt.f64.s32\td7, s15\n+\tldr\tr0, [r3, #0]\n+\tvdiv.f64\td8, d9, d7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp.w\tfp, #0\n+\tmov\tr8, r1\n+\tble.n\t11d8c <__gridxc_fft_gpfa_MOD_setgpfa+0xb8>\n \tldr\tr3, [sp, #28]\n-\tmovs\tr7, #1\n \tadd.w\tsl, sp, #40\t@ 0x28\n-\tstrd\tfp, r2, [sp, #16]\n-\tvmov.f64\td17, d10\n-\tmov\tfp, sl\n-\tadd.w\tr6, r3, r2, lsl #3\n-\tadd\tr3, sp, #32\n-\tmov\tsl, r7\n-\tadd.w\tr8, r5, #1\n-\tmov\tr7, r6\n+\tldr\tr2, [sp, #12]\n+\tvmov.f64\td6, d10\n+\tstr.w\tr9, [sp, #24]\n+\tadd.w\tr7, fp, #1\n+\tmov\tr9, sl\n \tmovs\tr4, #0\n-\tmov\tr6, r3\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tstr\tr1, [sp, #24]\n-\tb.n\t110f8 <__gridxc_fft_gpfa_MOD_setgpfa+0x13c>\n+\tadd.w\tr5, r3, r2, lsl #3\n+\tadd\tr3, sp, #32\n+\tmovs\tr6, #1\n+\tmov\tsl, r3\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tb.n\t11e1a <__gridxc_fft_gpfa_MOD_setgpfa+0x146>\n \tvmov\ts15, r4\n-\tmov\tr1, r6\n-\tmov\tr0, fp\n+\tmov\tr1, sl\n+\tmov\tr0, r9\n \tvcvt.f64.s32\td0, s15\n \tvmul.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvldr\td16, [fp, #-8]\n-\tvldr\td17, [fp]\n-\tadd\tr4, r9\n-\tadd.w\tsl, sl, #1\n-\tcmp\tr5, r4\n-\tvstr\td16, [r7, #-8]\n+\tvldr\td7, [r9, #-8]\n+\tvldr\td6, [r9]\n+\tadd\tr4, r8\n+\tadds\tr6, #1\n+\tcmp\tfp, r4\n+\tvstr\td7, [r5, #-8]\n \tit\tlt\n-\tsublt\tr4, r4, r5\n-\tvstr\td17, [r7]\n-\tcmp\tr8, sl\n-\tadd.w\tr7, r7, #16\n-\tbne.n\t110dc <__gridxc_fft_gpfa_MOD_setgpfa+0x120>\n-\tldrd\tfp, r2, [sp, #16]\n-\tldr\tr1, [sp, #24]\n-\tadd.w\tr2, r2, r5, lsl #1\n-\tb.n\t1106c <__gridxc_fft_gpfa_MOD_setgpfa+0xb0>\n-\tldr\tr3, [pc, #268]\t@ (11230 <__gridxc_fft_gpfa_MOD_setgpfa+0x274>)\n-\tadd\tr7, sp, #72\t@ 0x48\n-\tvldr\td16, [pc, #240]\t@ 11218 <__gridxc_fft_gpfa_MOD_setgpfa+0x25c>\n-\tmov\tr0, r7\n+\tsublt.w\tr4, r4, fp\n+\tvstr\td6, [r5]\n+\tcmp\tr7, r6\n+\tadd.w\tr5, r5, #16\n+\tbne.n\t11dfe <__gridxc_fft_gpfa_MOD_setgpfa+0x12a>\n+\tldr\tr3, [sp, #12]\n+\tldr.w\tr9, [sp, #24]\n+\tadd.w\tr3, r3, fp, lsl #1\n+\tstr\tr3, [sp, #12]\n+\tb.n\t11d8c <__gridxc_fft_gpfa_MOD_setgpfa+0xb8>\n+\tldr\tr3, [pc, #264]\t@ (11f50 <__gridxc_fft_gpfa_MOD_setgpfa+0x27c>)\n+\tadd\tr4, sp, #72\t@ 0x48\n+\tldr.w\tfp, [pc, #264]\t@ 11f54 <__gridxc_fft_gpfa_MOD_setgpfa+0x280>\n+\tmov\tr0, r4\n \tadd\tr3, pc\n-\tldr.w\tfp, [pc, #260]\t@ 11234 <__gridxc_fft_gpfa_MOD_setgpfa+0x278>\n \tstr\tr3, [sp, #80]\t@ 0x50\n-\tmov.w\tsl, #20\n-\tldr\tr3, [pc, #256]\t@ (11238 <__gridxc_fft_gpfa_MOD_setgpfa+0x27c>)\n+\tldr\tr3, [pc, #260]\t@ (11f58 <__gridxc_fft_gpfa_MOD_setgpfa+0x284>)\n \tadd\tfp, pc\n-\tvstr\td16, [sp, #72]\t@ 0x48\n+\tmov.w\tr8, #20\n+\tmov.w\tr2, #20480\t@ 0x5000\n \tadd\tr3, pc\n-\tstr.w\tr8, [sp, #128]\t@ 0x80\n+\tstr\tr5, [sp, #128]\t@ 0x80\n \tstr.w\tfp, [sp, #140]\t@ 0x8c\n \tstr\tr3, [sp, #124]\t@ 0x7c\n \tmovs\tr3, #0\n-\tstr.w\tsl, [sp, #144]\t@ 0x90\n+\tstr.w\tr8, [sp, #144]\t@ 0x90\n \tstr\tr3, [sp, #120]\t@ 0x78\n \tmovw\tr3, #5324\t@ 0x14cc\n \tstr\tr3, [sp, #84]\t@ 0x54\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #72]\t@ 0x48\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr2, r8\n-\tldr\tr1, [sp, #12]\n-\tmov\tr0, r7\n+\tmov\tr2, r5\n+\tldr\tr1, [sp, #20]\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tmov\tr0, r7\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tadd\tr7, sp, #56\t@ 0x38\n+\tadd\tr4, sp, #56\t@ 0x38\n \tmov\tr3, fp\n \tadd.w\tfp, sp, #52\t@ 0x34\n-\tmov\tr2, sl\n+\tmov\tr2, r8\n \tmov\tr1, fp\n-\tmov\tr0, r7\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr7, [sp, #56]\t@ 0x38\n-\tadd.w\tsl, r7, #6\n-\tmov\tr0, sl\n+\tldr\tr4, [sp, #56]\t@ 0x38\n+\tadd.w\tr8, r4, #6\n+\tmov\tr0, r8\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #168]\t@ (1123c <__gridxc_fft_gpfa_MOD_setgpfa+0x280>)\n+\tldr\tr3, [pc, #164]\t@ (11f5c <__gridxc_fft_gpfa_MOD_setgpfa+0x288>)\n \tldr.w\tfp, [sp, #52]\t@ 0x34\n \tmov\tr1, r0\n-\tmov\tr8, r0\n+\tmov\tr5, r0\n \tadd\tr3, pc\n \tmovs\tr2, #6\n-\tmov\tr0, sl\n-\tstrd\tr7, fp, [sp]\n+\tmov\tr0, r8\n+\tstrd\tr4, fp, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tcmp\tr7, #0\n-\tble.n\t111b2 <__gridxc_fft_gpfa_MOD_setgpfa+0x1f6>\n+\tcmp\tr4, #0\n+\tble.n\t11ed8 <__gridxc_fft_gpfa_MOD_setgpfa+0x204>\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tadds\tr7, #32\n-\tcmp\tr7, #1\n-\tmov\tr0, r7\n+\tadds\tr4, #32\n+\tcmp\tr4, #1\n+\tmov\tr0, r4\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #124]\t@ (11240 <__gridxc_fft_gpfa_MOD_setgpfa+0x284>)\n+\tldr\tr3, [pc, #120]\t@ (11f60 <__gridxc_fft_gpfa_MOD_setgpfa+0x28c>)\n \tmov\tfp, r0\n-\tmov\tr2, sl\n+\tmov\tr2, r8\n \tmov\tr1, r0\n \tadd\tr3, pc\n-\tmov\tr0, r7\n+\tmov\tr0, r4\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #26\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r8\n+\tmov\tr3, r5\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, r8\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #100]\t@ (11244 <__gridxc_fft_gpfa_MOD_setgpfa+0x288>)\n+\tldr\tr3, [pc, #92]\t@ (11f64 <__gridxc_fft_gpfa_MOD_setgpfa+0x290>)\n \tmov\tr0, fp\n-\tmov\tr1, r7\n-\tldr.w\tr3, [r9, r3]\n+\tmov\tr1, r4\n+\tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t1102c <__gridxc_fft_gpfa_MOD_setgpfa+0x70>\n-\tadd\tr1, r8\n-\tadd.w\tr8, r8, #1\n-\tmovs\tr2, #0\n-\tcmp.w\tr8, #4\n-\tstr.w\tr2, [ip], #4\n-\tbne.w\t10ffa <__gridxc_fft_gpfa_MOD_setgpfa+0x3e>\n-\tb.n\t11028 <__gridxc_fft_gpfa_MOD_setgpfa+0x6c>\n+\tb.n\t11d4a <__gridxc_fft_gpfa_MOD_setgpfa+0x76>\n+\tadd\tsl, r5\n+\tadds\tr5, #1\n+\tmovs\tr4, #0\n+\tcmp\tr5, #4\n+\tstr.w\tr4, [r8], #4\n+\tbne.w\t11d12 <__gridxc_fft_gpfa_MOD_setgpfa+0x3e>\n+\tb.n\t11d44 <__gridxc_fft_gpfa_MOD_setgpfa+0x70>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \t.word\t0x54442d18\n \t.word\t0x401921fb\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x00000244\n+\t...\n+\t.word\t0x0000024c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000022c\n+\t.word\t0x00000234\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001b4\n+\t.word\t0x000001b2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000102\n+\t.word\t0x000000fe\n R_ARM_REL32\t.LC0\n-\t.word\t0x000000f8\n+\t.word\t0x000000fc\n R_ARM_REL32\t.bss\n \t.word\t0x000000f6\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000009e\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000074\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC3\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \n-00011248 <__gridxc_fft_gpfa_MOD_setgpfa_check>:\n+00011f68 <__gridxc_fft_gpfa_MOD_setgpfa_check>:\n __gridxc_fft_gpfa_MOD_setgpfa_check.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3608]\t@ 0xe18\n \tsub\tsp, #436\t@ 0x1b4\n-\tmov\tr9, r2\n-\tldr\tr2, [pc, #596]\t@ (114b8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x270>)\n-\tmov\tfp, r3\n-\tldr\tr3, [pc, #596]\t@ (114bc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x274>)\n+\tmov\tr8, r3\n+\tldr\tr3, [pc, #612]\t@ (121e8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x280>)\n \tadd\tr4, sp, #68\t@ 0x44\n-\tadd\tr2, pc\n+\tmov.w\tfp, #1\n+\tmovs\tr5, #2\n+\tstr\tr2, [sp, #36]\t@ 0x24\n+\tmov\tr6, r5\n+\tldr\tr2, [pc, #604]\t@ (121ec <__gridxc_fft_gpfa_MOD_setgpfa_check+0x284>)\n \tstr\tr0, [sp, #32]\n-\tldr\tr5, [r1, #0]\n-\tmov\tip, r4\n-\tmovs\tr1, #2\n-\tldr\tr6, [pc, #588]\t@ (114c0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x278>)\n+\tadd\tr2, pc\n+\tldr.w\tr9, [r1]\n+\tldr.w\tsl, [pc, #596]\t@ 121f0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x288>\n \tldr\tr3, [r2, r3]\n-\tmovs\tr2, #1\n-\tmov\tlr, r2\n-\tadd\tr6, pc\n+\tadd\tsl, pc\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #428]\t@ 0x1ac\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [fp]\n-\tstr\tr3, [sp, #16]\n+\tldr.w\tr3, [r8]\n+\tstr.w\tr8, [sp, #16]\n+\tmov\tr8, fp\n \tmov\tr7, r3\n+\tmov\tfp, r4\n+\tstr\tr3, [sp, #24]\n \tstr\tr4, [sp, #12]\n-\tsdiv\tr3, r7, r1\n-\tmls\tr0, r1, r3, r7\n-\tcmp\tr0, #0\n-\tbne.w\t1148a <__gridxc_fft_gpfa_MOD_setgpfa_check+0x242>\n-\tmov\tr7, r3\n-\tadds\tr0, #1\n-\tsdiv\tr3, r3, r1\n-\tmls\tr2, r1, r3, r7\n-\tcmp\tr2, #0\n-\tbeq.n\t1129c <__gridxc_fft_gpfa_MOD_setgpfa_check+0x54>\n-\tadd\tr1, lr\n-\tadd.w\tlr, lr, #1\n-\tcmp.w\tlr, #4\n-\tstr.w\tr0, [ip], #4\n-\tbne.n\t1128e <__gridxc_fft_gpfa_MOD_setgpfa_check+0x46>\n+\tmov\tr1, r6\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr5, r1\n+\tcmp\tr1, #0\n+\tbne.w\t121c0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x258>\n+\tmov\tr0, r7\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, r6\n+\tadds\tr5, #1\n+\tmov\tr7, r0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.n\t11fca <__gridxc_fft_gpfa_MOD_setgpfa_check+0x62>\n+\tadd\tr6, r8\n+\tadd.w\tr8, r8, #1\n+\tcmp.w\tr8, #4\n+\tstr.w\tr5, [r4], #4\n+\tbne.n\t11fba <__gridxc_fft_gpfa_MOD_setgpfa_check+0x52>\n+\tmov\tr4, fp\n \tcmp\tr7, #1\n-\tbne.n\t113b4 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x16c>\n+\tmov\tfp, r8\n+\tldr.w\tr8, [sp, #16]\n+\tbne.n\t120f0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x188>\n \tldrd\tr2, r1, [r4]\n \tmovs\tr0, #3\n-\tldr\tr7, [r4, #8]\n-\tadd.w\tsl, sp, #48\t@ 0x30\n+\tldr\tr5, [r4, #8]\n+\tadd.w\tr8, sp, #48\t@ 0x30\n \tcmp\tr2, #31\n-\tvldr\td9, [pc, #472]\t@ 114a8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x260>\n-\tit\tls\n+\tvldr\td9, [pc, #468]\t@ 121e0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x278>\n+\titet\tls\n \tmovls\tr3, #1\n-\tit\thi\n \tmovhi\tr3, #0\n-\tmov\tfp, sl\n-\tit\tls\n \tlslls\tr3, r2\n \tstr\tr3, [r4, #0]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tmov\tr1, r7\n+\tmov\tr1, r5\n \tstr\tr0, [r4, #4]\n \tmovs\tr0, #5\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tldr.w\tip, [sp, #12]\n-\tstr.w\tr9, [sp, #36]\t@ 0x24\n-\tadd.w\tr1, r4, #12\n+\tldr\tr2, [sp, #12]\n+\tadd.w\tr3, r4, #12\n+\tstr\tr3, [sp, #16]\n \tmovs\tr3, #1\n-\tmov\tr9, r5\n \tstr\tr0, [r4, #8]\n-\tldr.w\tr5, [ip], #4\n-\tcmp\tr5, #1\n-\tbne.n\t11338 <__gridxc_fft_gpfa_MOD_setgpfa_check+0xf0>\n-\tcmp\tip, r1\n-\tbne.n\t11302 <__gridxc_fft_gpfa_MOD_setgpfa_check+0xba>\n-\tldr.w\tr9, [sp, #36]\t@ 0x24\n-\tsubs\tr2, r3, #1\n-\tldr\tr3, [pc, #420]\t@ (114bc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x274>)\n-\tstr.w\tr2, [r9]\n-\tldr\tr2, [pc, #424]\t@ (114c4 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x27c>)\n+\tldr.w\tr7, [r2], #4\n+\tcmp\tr7, #1\n+\tbne.n\t12066 <__gridxc_fft_gpfa_MOD_setgpfa_check+0xfe>\n+\tldr\tr1, [sp, #16]\n+\tcmp\tr2, r1\n+\tbne.n\t12032 <__gridxc_fft_gpfa_MOD_setgpfa_check+0xca>\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tsubs\tr3, #1\n+\tstr\tr3, [r2, #0]\n+\tldr\tr2, [pc, #428]\t@ (121f4 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x28c>)\n+\tldr\tr3, [pc, #412]\t@ (121e8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x280>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #428]\t@ 0x1ac\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t114a0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x258>\n+\tbne.w\t121d6 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x26e>\n \tadd\tsp, #436\t@ 0x1b4\n \tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [sp, #16]\n-\tvmov\ts15, r5\n-\tcmp\tr5, #0\n-\tvcvt.f64.s32\td16, s15\n-\tsdiv\tr8, r2, r5\n-\tvdiv.f64\td8, d9, d16\n-\tsdiv\tr2, r8, r5\n-\tmls\tr8, r5, r2, r8\n-\tble.n\t1130a <__gridxc_fft_gpfa_MOD_setgpfa_check+0xc2>\n-\tldr\tr2, [sp, #32]\n-\tadd.w\tsl, r3, r5, lsl #1\n-\tmov\tr6, r3\n+\tvmov\ts15, r7\n+\tmov\tr1, r7\n+\tldr\tr0, [sp, #24]\n+\tvcvt.f64.s32\td7, s15\n+\tstr\tr2, [sp, #20]\n+\tstr\tr3, [sp, #12]\n+\tvdiv.f64\td8, d9, d7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, r7\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tldr\tr3, [sp, #12]\n+\tldr\tr2, [sp, #20]\n+\tmov\tsl, r1\n+\tcmp\tr7, #0\n+\tble.n\t1203a <__gridxc_fft_gpfa_MOD_setgpfa_check+0xd2>\n+\tldr\tr1, [sp, #32]\n+\tadd.w\tfp, r3, r7, lsl #1\n+\tmov\tr5, r3\n+\tstr\tr3, [sp, #20]\n \tmovs\tr4, #0\n-\tstrd\tr3, ip, [sp, #20]\n-\tadd.w\tr7, r2, r3, lsl #3\n-\tstr\tr1, [sp, #28]\n-\tadd\tr2, sp, #40\t@ 0x28\n-\tstr\tr2, [sp, #12]\n-\tcmp\tr9, r6\n-\tble.n\t11396 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x14e>\n+\tstr\tr2, [sp, #28]\n+\tadd.w\tr6, r1, r3, lsl #3\n+\tmov\tr3, r8\n+\tmov\tr8, sl\n+\tmov\tsl, r3\n+\tadd\tr1, sp, #40\t@ 0x28\n+\tstr\tr1, [sp, #12]\n+\tcmp\tr9, r5\n+\tble.n\t120d2 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x16a>\n \tvmov\ts15, r4\n \tldr\tr1, [sp, #12]\n-\tmov\tr0, fp\n+\tmov\tr0, sl\n \tvcvt.f64.s32\td0, s15\n \tvmul.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvldr\td16, [fp]\n-\tvstr\td16, [r7]\n-\tvldr\td16, [fp, #-8]\n-\tvstr\td16, [r7, #-8]\n+\tvldr\td7, [sl]\n+\tvstr\td7, [r6]\n+\tvldr\td7, [sl, #-8]\n+\tvstr\td7, [r6, #-8]\n \tadd\tr4, r8\n-\tadds\tr6, #2\n-\tcmp\tr5, r4\n-\tadd.w\tr7, r7, #16\n+\tadds\tr5, #2\n+\tcmp\tr7, r4\n+\tadd.w\tr6, r6, #16\n \tit\tlt\n-\tsublt\tr4, r4, r5\n-\tcmp\tr6, sl\n-\tbne.n\t1136e <__gridxc_fft_gpfa_MOD_setgpfa_check+0x126>\n-\tldrd\tr3, ip, [sp, #20]\n-\tldr\tr1, [sp, #28]\n-\tadd.w\tr3, r3, r5, lsl #1\n-\tb.n\t1130a <__gridxc_fft_gpfa_MOD_setgpfa_check+0xc2>\n-\tldr\tr3, [pc, #272]\t@ (114c8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x280>)\n-\tadd\tr7, sp, #80\t@ 0x50\n-\tvldr\td16, [pc, #244]\t@ 114b0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x268>\n-\tmov\tr0, r7\n+\tsublt\tr4, r4, r7\n+\tcmp\tr5, fp\n+\tbne.n\t120aa <__gridxc_fft_gpfa_MOD_setgpfa_check+0x142>\n+\tldr\tr3, [sp, #20]\n+\tmov\tr8, sl\n+\tldr\tr2, [sp, #28]\n+\tadd.w\tr3, r3, r7, lsl #1\n+\tb.n\t1203a <__gridxc_fft_gpfa_MOD_setgpfa_check+0xd2>\n+\tldr\tr3, [pc, #260]\t@ (121f8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x290>)\n+\tadd\tr5, sp, #80\t@ 0x50\n+\tldr\tr6, [pc, #260]\t@ (121fc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x294>)\n+\tmov\tr0, r5\n \tadd\tr3, pc\n-\tldr.w\tsl, [pc, #264]\t@ 114cc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x284>\n \tstr\tr3, [sp, #88]\t@ 0x58\n-\tmov.w\tr8, #20\n-\tldr\tr3, [pc, #260]\t@ (114d0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x288>)\n-\tadd\tsl, pc\n-\tstr.w\tlr, [sp, #136]\t@ 0x88\n-\tstr.w\tlr, [sp, #20]\n+\tldr\tr3, [pc, #256]\t@ (12200 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x298>)\n+\tadd\tr6, pc\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tmovs\tr7, #20\n \tadd\tr3, pc\n-\tvstr\td16, [sp, #80]\t@ 0x50\n-\tstr.w\tsl, [sp, #148]\t@ 0x94\n+\tstr.w\tfp, [sp, #136]\t@ 0x88\n+\tstr\tr6, [sp, #148]\t@ 0x94\n \tstr\tr3, [sp, #132]\t@ 0x84\n \tmovs\tr3, #0\n-\tstr.w\tr8, [sp, #152]\t@ 0x98\n+\tstr\tr7, [sp, #152]\t@ 0x98\n \tstr\tr3, [sp, #128]\t@ 0x80\n \tmovw\tr3, #5228\t@ 0x146c\n \tstr\tr3, [sp, #92]\t@ 0x5c\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #80]\t@ 0x50\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr1, fp\n-\tldr\tr2, [sp, #20]\n-\tmov\tr0, r7\n+\tmov\tr2, fp\n+\tmov\tr1, r8\n+\tmov\tr0, r5\n \tadd.w\tfp, sp, #60\t@ 0x3c\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tmov\tr0, r7\n-\tadd\tr7, sp, #64\t@ 0x40\n+\tmov\tr0, r5\n+\tadd\tr5, sp, #64\t@ 0x40\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, sl\n-\tmov\tr2, r8\n+\tmov\tr3, r6\n \tmov\tr1, fp\n-\tmov\tr0, r7\n+\tmov\tr2, r7\n+\tmov\tr0, r5\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr7, [sp, #64]\t@ 0x40\n-\tadd.w\tsl, r7, #6\n-\tmov\tr0, sl\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tadd.w\tr8, r5, #6\n+\tmov\tr0, r8\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #168]\t@ (114d4 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x28c>)\n+\tldr\tr3, [pc, #164]\t@ (12204 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x29c>)\n \tldr.w\tfp, [sp, #60]\t@ 0x3c\n \tmov\tr1, r0\n-\tmov\tr8, r0\n+\tmov\tr6, r0\n \tadd\tr3, pc\n \tmovs\tr2, #6\n-\tmov\tr0, sl\n-\tstrd\tr7, fp, [sp]\n+\tmov\tr0, r8\n+\tstrd\tr5, fp, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tcmp\tr7, #0\n-\tble.n\t1144a <__gridxc_fft_gpfa_MOD_setgpfa_check+0x202>\n+\tcmp\tr5, #0\n+\tble.n\t1217e <__gridxc_fft_gpfa_MOD_setgpfa_check+0x216>\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tadds\tr7, #32\n-\tcmp\tr7, #1\n-\tmov\tr0, r7\n+\tadds\tr5, #32\n+\tcmp\tr5, #1\n+\tmov\tr0, r5\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #124]\t@ (114d8 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x290>)\n+\tldr\tr3, [pc, #120]\t@ (12208 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x2a0>)\n \tmov\tfp, r0\n-\tmov\tr2, sl\n+\tmov\tr2, r8\n \tmov\tr1, r0\n \tadd\tr3, pc\n-\tmov\tr0, r7\n+\tmov\tr0, r5\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #26\n \tstr\tr3, [sp, #0]\n-\tmov\tr3, r8\n+\tmov\tr3, r6\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr0, r8\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #100]\t@ (114dc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x294>)\n+\tldr\tr3, [pc, #96]\t@ (1220c <__gridxc_fft_gpfa_MOD_setgpfa_check+0x2a4>)\n \tmov\tr0, fp\n-\tmov\tr1, r7\n-\tldr\tr3, [r6, r3]\n+\tmov\tr1, r5\n+\tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t112c0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x78>\n-\tadd\tr1, lr\n-\tadd.w\tlr, lr, #1\n-\tmovs\tr0, #0\n-\tcmp.w\tlr, #4\n-\tstr.w\tr0, [ip], #4\n-\tbne.w\t1128e <__gridxc_fft_gpfa_MOD_setgpfa_check+0x46>\n-\tb.n\t112bc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x74>\n+\tb.n\t11ffc <__gridxc_fft_gpfa_MOD_setgpfa_check+0x94>\n+\tadd\tr6, r8\n+\tadd.w\tr8, r8, #1\n+\tmovs\tr5, #0\n+\tcmp.w\tr8, #4\n+\tstr.w\tr5, [r4], #4\n+\tbne.w\t11fba <__gridxc_fft_gpfa_MOD_setgpfa_check+0x52>\n+\tb.n\t11ff0 <__gridxc_fft_gpfa_MOD_setgpfa_check+0x88>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \tnop.w\n \t.word\t0x54442d18\n \t.word\t0x401921fb\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x0000024c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000242\n+\t.word\t0x00000256\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001a4\n+\t.word\t0x0000024e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x000001a6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000106\n- R_ARM_REL32\t.LC0\n \t.word\t0x000000fc\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000000fa\n R_ARM_REL32\t.bss\n \t.word\t0x000000f6\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000009e\n+\t.word\t0x0000009a\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000074\n+\t.word\t0x00000070\n R_ARM_REL32\t.LC3\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \n-000114e0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>:\n+00012210 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>:\n __gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0():\n-\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n+\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n-\tldr\tr4, [pc, #372]\t@ (11668 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x188>)\n+\tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n+\tldr\tr4, [pc, #336]\t@ (12374 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x164>)\n \tmov\tr5, r0\n-\tldr\tr2, [pc, #372]\t@ (1166c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x18c>)\n-\tsub\tsp, #16\n+\tldr\tr2, [pc, #336]\t@ (12378 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x168>)\n+\tsub\tsp, #20\n \tadd\tr4, pc\n-\tldr\tr3, [pc, #372]\t@ (11670 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x190>)\n+\tldr\tr3, [pc, #336]\t@ (1237c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x16c>)\n \tadd\tr2, pc\n-\tldr\tr0, [r4, #24]\n+\tldr\tr0, [r4, #20]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #12]\n \tmov.w\tr3, #0\n \tcmp\tr0, #0\n-\tbeq.n\t115d0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0xf0>\n-\tldrd\tr3, r2, [r4, #52]\t@ 0x34\n+\tbeq.n\t122fe <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0xee>\n+\tldrd\tr3, r2, [r4, #48]\t@ 0x30\n \tsubs\tr2, r2, r3\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n-\tldr\tr4, [pc, #344]\t@ (11674 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x194>)\n+\tldr\tr4, [pc, #308]\t@ (12380 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x170>)\n \tadd\tr7, sp, #4\n \tadd\tr6, sp, #8\n \tmov\tr3, r5\n \tadd\tr4, pc\n \tstr\tr2, [sp, #8]\n \tmov\tr1, r6\n \tmov\tr2, r7\n-\tbl\t11248 <__gridxc_fft_gpfa_MOD_setgpfa_check>\n+\tbl\t11f68 <__gridxc_fft_gpfa_MOD_setgpfa_check>\n \tldr.w\tr8, [sp, #4]\n-\tldrd\tr3, r2, [r4, #52]\t@ 0x34\n+\tldrd\tr3, r2, [r4, #48]\t@ 0x30\n \tsubs\tr2, r2, r3\n \tadds\tr2, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tcmp\tr2, r8\n-\tbge.n\t115b6 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0xd6>\n-\tldr\tr0, [r4, #24]\n+\tbge.n\t122e4 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0xd4>\n+\tldr\tr0, [r4, #20]\n \tcmp\tr0, #0\n-\tbeq.n\t11626 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x146>\n+\tbeq.n\t1234a <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x13a>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmovs\tr3, #8\n \tmov.w\tr9, #0\n-\tstr\tr3, [r4, #32]\n-\tcmp.w\tr8, #536870912\t@ 0x20000000\n+\tmov.w\tfp, #8\n+\tstr.w\tr9, [r4, #36]\t@ 0x24\n \tmovw\tr3, #769\t@ 0x301\n-\tstr.w\tr9, [r4, #24]\n-\tvstr\td16, [r4, #36]\t@ 0x24\n-\tstrh\tr3, [r4, #40]\t@ 0x28\n-\tbcs.n\t11636 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x156>\n+\tcmp.w\tr8, #536870912\t@ 0x20000000\n+\tstr.w\tr9, [r4, #20]\n+\tstr.w\tr9, [r4, #32]\n+\tstr.w\tfp, [r4, #28]\n+\tstrh\tr3, [r4, #36]\t@ 0x24\n+\tbcs.n\t1235a <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x14a>\n \tmov.w\tsl, r8, lsl #3\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r4, #24]\n+\tstr\tr0, [r4, #20]\n \tcmp\tr0, #0\n-\tbeq.n\t11618 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x138>\n+\tbeq.n\t1233c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x12c>\n \tmov\tr3, r5\n-\tvldr\td16, [pc, #208]\t@ 11650 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x170>\n-\tadd.w\tr5, r4, #44\t@ 0x2c\n \tmov\tr2, r7\n \tmov\tr1, r6\n-\tstr.w\tr8, [r4, #56]\t@ 0x38\n-\tstr.w\tr8, [sp, #8]\n-\tvst1.32\t{d16}, [r5]\n \tmovs\tr5, #1\n-\tstr\tr5, [r4, #52]\t@ 0x34\n+\tstr.w\tfp, [r4, #40]\t@ 0x28\n+\tstrd\tr5, r5, [r4, #44]\t@ 0x2c\n \tmov.w\tr5, #4294967295\t@ 0xffffffff\n-\tstr\tr5, [r4, #28]\n-\tbl\t11248 <__gridxc_fft_gpfa_MOD_setgpfa_check>\n-\tldrd\tr1, r3, [r4, #52]\t@ 0x34\n+\tstr.w\tr8, [r4, #52]\t@ 0x34\n+\tstr.w\tr8, [sp, #8]\n+\tstr\tr5, [r4, #24]\n+\tbl\t11f68 <__gridxc_fft_gpfa_MOD_setgpfa_check>\n+\tldrd\tr1, r3, [r4, #48]\t@ 0x30\n \tldr\tr2, [sp, #4]\n \tsubs\tr3, r3, r1\n \tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r2\n-\tblt.n\t11608 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x128>\n-\tldr\tr2, [pc, #192]\t@ (11678 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x198>)\n-\tldr\tr3, [pc, #180]\t@ (11670 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x190>)\n+\tblt.n\t1232c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x11c>\n+\tldr\tr2, [pc, #156]\t@ (12384 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x174>)\n+\tldr\tr3, [pc, #148]\t@ (1237c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x16c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #12]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t11614 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x134>\n-\tadd\tsp, #16\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbne.n\t12338 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x128>\n+\tadd\tsp, #20\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tstr\tr0, [r4, #36]\t@ 0x24\n+\tmovs\tr6, #8\n+\tstrd\tr6, r0, [r4, #28]\n \tmov.w\tr0, #800\t@ 0x320\n-\tmovs\tr2, #8\n \tmovw\tr3, #769\t@ 0x301\n-\tstr\tr2, [r4, #32]\n-\tvstr\td16, [r4, #36]\t@ 0x24\n-\tstrh\tr3, [r4, #40]\t@ 0x28\n+\tstrh\tr3, [r4, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [r4, #24]\n-\tcbz\tr0, 1163e <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x15e>\n-\tvldr\td16, [pc, #104]\t@ 11658 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x178>\n-\tvldr\td17, [pc, #108]\t@ 11660 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x180>\n-\tadd.w\tr3, r4, #44\t@ 0x2c\n-\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tstr\tr0, [r4, #20]\n+\tcbz\tr0, 12362 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x152>\n+\tmovs\tr3, #1\n \tmovs\tr2, #100\t@ 0x64\n-\tstr\tr1, [r4, #28]\n-\tvst1.32\t{d16-d17}, [r3]\n-\tb.n\t1151a <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x3a>\n-\tldr\tr0, [pc, #112]\t@ (1167c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x19c>)\n+\tstr\tr3, [r4, #44]\t@ 0x2c\n+\tstrd\tr3, r2, [r4, #48]\t@ 0x30\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr\tr6, [r4, #40]\t@ 0x28\n+\tstr\tr3, [r4, #24]\n+\tb.n\t1224a <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x3a>\n+\tldr\tr0, [pc, #88]\t@ (12388 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x178>)\n \tmov\tr2, r9\n \tmovs\tr1, #12\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_stop_string>\n R_ARM_THM_CALL\t_gfortran_stop_string\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr1, [pc, #100]\t@ (11680 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1a0>)\n+\tldr\tr1, [pc, #76]\t@ (1238c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x17c>)\n \tmov\tr2, sl\n-\tldr\tr0, [pc, #100]\t@ (11684 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1a4>)\n+\tldr\tr0, [pc, #76]\t@ (12390 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x180>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #96]\t@ (11688 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1a8>)\n-\tldr\tr1, [pc, #96]\t@ (1168c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1ac>)\n-\tldr\tr0, [pc, #100]\t@ (11690 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1b0>)\n+\tldr\tr2, [pc, #72]\t@ (12394 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x184>)\n+\tldr\tr1, [pc, #72]\t@ (12398 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x188>)\n+\tldr\tr0, [pc, #76]\t@ (1239c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x18c>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr0, [pc, #92]\t@ (11694 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1b4>)\n+\tldr\tr0, [pc, #68]\t@ (123a0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x190>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tldr\tr1, [pc, #88]\t@ (11698 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1b8>)\n+\tldr\tr1, [pc, #64]\t@ (123a4 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x194>)\n \tmov.w\tr2, #800\t@ 0x320\n-\tldr\tr0, [pc, #84]\t@ (1169c <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x1bc>)\n+\tldr\tr0, [pc, #60]\t@ (123a8 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0+0x198>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n \tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000064\n-\t.word\t0x0000016c\n+\t.word\t0x00000148\n R_ARM_REL32\t.bss\n-\t.word\t0x0000016c\n+\t.word\t0x00000148\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000014e\n+\t.word\t0x0000012a\n R_ARM_REL32\t.bss\n-\t.word\t0x000000ba\n+\t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000006a\n+\t.word\t0x00000052\n R_ARM_REL32\t.LC11\n-\t.word\t0x0000005e\n+\t.word\t0x00000046\n R_ARM_REL32\t.LC4\n-\t.word\t0x00000060\n+\t.word\t0x00000048\n R_ARM_REL32\t.LC10\n-\t.word\t0x00000058\n+\t.word\t0x00000040\n R_ARM_REL32\t.LC6\n-\t.word\t0x0000005a\n+\t.word\t0x00000042\n R_ARM_REL32\t.LC7\n-\t.word\t0x0000005c\n+\t.word\t0x00000044\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000058\n+\t.word\t0x00000040\n R_ARM_REL32\t.LC9\n-\t.word\t0x0000004e\n+\t.word\t0x00000036\n R_ARM_REL32\t.LC4\n-\t.word\t0x00000050\n+\t.word\t0x00000038\n R_ARM_REL32\t.LC5\n \n-000116a0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp>:\n+000123ac <__gridxc_fft_gpfa_MOD_fft_gpfa_dp>:\n __gridxc_fft_gpfa_MOD_fft_gpfa_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3936]\t@ 0xf60\n \tmov\tfp, r2\n-\tldr\tr2, [pc, #252]\t@ (117b0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x110>)\n+\tldr\tr2, [pc, #252]\t@ (124bc <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x110>)\n \tmov\tr7, r3\n-\tldr\tr3, [pc, #252]\t@ (117b4 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x114>)\n+\tldr\tr3, [pc, #252]\t@ (124c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x114>)\n \tadd\tr2, pc\n \tsub\tsp, #124\t@ 0x7c\n \tldr\tr6, [r0, #24]\n \tmov\tip, r1\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #160]\t@ 0xa0\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #116]\t@ 0x74\n \tmov.w\tr3, #0\n \tldr\tr3, [sp, #164]\t@ 0xa4\n \tldr\tr1, [sp, #168]\t@ 0xa8\n \tstr\tr3, [sp, #24]\n \tcmp\tr6, #0\n-\tbeq.n\t117a0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x100>\n+\tbeq.n\t124ac <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x100>\n \tnegs\tr3, r6\n \tstr\tr3, [sp, #20]\n \tldrd\tr3, r4, [r0, #28]\n \tldr.w\tr5, [ip, #24]\n \tsubs\tr4, r4, r3\n \tldr\tr3, [r0, #0]\n \tadds\tr4, #1\n \trsb\tsl, r5, #0\n \tstr\tr3, [sp, #16]\n-\tcbnz\tr5, 116f8 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x58>\n+\tcbnz\tr5, 12404 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x58>\n \tmov.w\tsl, #4294967295\t@ 0xffffffff\n \tmovs\tr5, #1\n-\tldr\tr3, [pc, #188]\t@ (117b8 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x118>)\n+\tldr\tr3, [pc, #188]\t@ (124c4 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x118>)\n \tldr.w\tr9, [r8]\n \tadd\tr3, pc\n \tldr\tr0, [r3, #0]\n \tldrd\tr3, r2, [ip, #28]\n \tcmp\tr9, r0\n \tsub.w\tr3, r2, r3\n \tldr.w\tr2, [ip]\n \tadd.w\tr3, r3, #1\n-\tbeq.n\t11728 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x88>\n+\tbeq.n\t12434 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x88>\n \tmov\tr0, r8\n \tstrd\tr3, r1, [sp, #32]\n \tstr\tr2, [sp, #28]\n-\tbl\t114e0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n+\tbl\t12210 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n \tldrd\tr3, r1, [sp, #32]\n \tldr\tr2, [sp, #28]\n \tstr\tr4, [sp, #76]\t@ 0x4c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr4, [pc, #140]\t@ (117bc <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x11c>)\n \tadd\tr0, sp, #44\t@ 0x2c\n+\tldr\tr4, [pc, #140]\t@ (124c8 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x11c>)\n \tstr\tr1, [sp, #12]\n+\tstr\tr5, [sp, #104]\t@ 0x68\n \tadd\tr4, pc\n \tldr\tr1, [sp, #24]\n+\tadd\tr5, sp, #92\t@ 0x5c\n \tstrd\tr8, r1, [sp, #4]\n \tstr\tr7, [sp, #0]\n \tldr\tr1, [sp, #16]\n \tstr\tr1, [sp, #44]\t@ 0x2c\n \tldr\tr1, [sp, #20]\n \tstr\tr1, [sp, #48]\t@ 0x30\n \tadd\tr1, sp, #80\t@ 0x50\n \tstr\tr3, [sp, #112]\t@ 0x70\n \tmov\tr3, fp\n \tstrd\tr2, sl, [sp, #80]\t@ 0x50\n-\tldr\tr2, [r4, #24]\n+\tldr\tr2, [r4, #20]\n \tmovs\tr4, #8\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #52]\t@ 0x34\n-\tstr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #88]\t@ 0x58\n+\tmovs\tr4, #0\n+\tstr\tr4, [r5, #4]\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tstr\tr4, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #92]\t@ 0x5c\n \tmovs\tr4, #1\n-\tvstr\td16, [sp, #92]\t@ 0x5c\n+\tstr\tr6, [sp, #68]\t@ 0x44\n \tstr\tr4, [sp, #72]\t@ 0x48\n \tstr\tr4, [sp, #108]\t@ 0x6c\n \tmovw\tr4, #769\t@ 0x301\n-\tstr\tr6, [sp, #68]\t@ 0x44\n-\tstr\tr5, [sp, #104]\t@ 0x68\n \tstrh.w\tr4, [sp, #60]\t@ 0x3c\n \tstrh.w\tr4, [sp, #96]\t@ 0x60\n-\tbl\tdd28 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n-\tldr\tr3, [pc, #64]\t@ (117c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x120>)\n-\tldr\tr2, [pc, #64]\t@ (117c4 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x124>)\n+\tbl\te7b8 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n+\tldr\tr3, [pc, #64]\t@ (124cc <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x120>)\n+\tldr\tr2, [pc, #64]\t@ (124d0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x124>)\n \tadd\tr3, pc\n \tadd\tr2, pc\n \tstr.w\tr9, [r3]\n-\tldr\tr3, [pc, #40]\t@ (117b4 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x114>)\n+\tldr\tr3, [pc, #40]\t@ (124c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x114>)\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #116]\t@ 0x74\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t117aa <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x10a>\n+\tbne.n\t124b6 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x10a>\n \tadd\tsp, #124\t@ 0x7c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tstr\tr3, [sp, #20]\n-\tb.n\t116dc <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x3c>\n+\tb.n\t123e8 <__gridxc_fft_gpfa_MOD_fft_gpfa_dp+0x3c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \t.word\t0x000000f4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x000000b6\n R_ARM_REL32\t.data\n-\t.word\t0x00000084\n+\t.word\t0x00000086\n R_ARM_REL32\t.bss\n \t.word\t0x0000003a\n R_ARM_REL32\t.data\n \t.word\t0x0000003c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000117c8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp>:\n+000124d4 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp>:\n __gridxc_fft_gpfa_MOD_fft_gpfa_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3936]\t@ 0xf60\n \tmov\tfp, r2\n-\tldr\tr2, [pc, #252]\t@ (118d8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x110>)\n+\tldr\tr2, [pc, #252]\t@ (125e4 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x110>)\n \tmov\tr7, r3\n-\tldr\tr3, [pc, #252]\t@ (118dc <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x114>)\n+\tldr\tr3, [pc, #252]\t@ (125e8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x114>)\n \tadd\tr2, pc\n \tsub\tsp, #124\t@ 0x7c\n \tldr\tr6, [r0, #24]\n \tmov\tip, r1\n \tldr\tr3, [r2, r3]\n \tldr.w\tr8, [sp, #160]\t@ 0xa0\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #116]\t@ 0x74\n \tmov.w\tr3, #0\n \tldr\tr3, [sp, #164]\t@ 0xa4\n \tldr\tr1, [sp, #168]\t@ 0xa8\n \tstr\tr3, [sp, #24]\n \tcmp\tr6, #0\n-\tbeq.n\t118c8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x100>\n+\tbeq.n\t125d4 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x100>\n \tnegs\tr3, r6\n \tstr\tr3, [sp, #20]\n \tldrd\tr3, r4, [r0, #28]\n \tldr.w\tr5, [ip, #24]\n \tsubs\tr4, r4, r3\n \tldr\tr3, [r0, #0]\n \tadds\tr4, #1\n \trsb\tsl, r5, #0\n \tstr\tr3, [sp, #16]\n-\tcbnz\tr5, 11820 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x58>\n+\tcbnz\tr5, 1252c <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x58>\n \tmov.w\tsl, #4294967295\t@ 0xffffffff\n \tmovs\tr5, #1\n-\tldr\tr3, [pc, #188]\t@ (118e0 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x118>)\n+\tldr\tr3, [pc, #188]\t@ (125ec <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x118>)\n \tldr.w\tr9, [r8]\n \tadd\tr3, pc\n \tldr\tr0, [r3, #0]\n \tldrd\tr3, r2, [ip, #28]\n \tcmp\tr9, r0\n \tsub.w\tr3, r2, r3\n \tldr.w\tr2, [ip]\n \tadd.w\tr3, r3, #1\n-\tbeq.n\t11850 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x88>\n+\tbeq.n\t1255c <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x88>\n \tmov\tr0, r8\n \tstrd\tr3, r1, [sp, #32]\n \tstr\tr2, [sp, #28]\n-\tbl\t114e0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n+\tbl\t12210 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n \tldrd\tr3, r1, [sp, #32]\n \tldr\tr2, [sp, #28]\n \tstr\tr4, [sp, #76]\t@ 0x4c\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr4, [pc, #140]\t@ (118e4 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x11c>)\n \tadd\tr0, sp, #44\t@ 0x2c\n+\tldr\tr4, [pc, #140]\t@ (125f0 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x11c>)\n \tstr\tr1, [sp, #12]\n+\tstr\tr5, [sp, #104]\t@ 0x68\n \tadd\tr4, pc\n \tldr\tr1, [sp, #24]\n+\tadd\tr5, sp, #92\t@ 0x5c\n \tstrd\tr8, r1, [sp, #4]\n \tstr\tr7, [sp, #0]\n \tldr\tr1, [sp, #16]\n \tstr\tr1, [sp, #44]\t@ 0x2c\n \tldr\tr1, [sp, #20]\n \tstr\tr1, [sp, #48]\t@ 0x30\n \tadd\tr1, sp, #80\t@ 0x50\n \tstr\tr3, [sp, #112]\t@ 0x70\n \tmov\tr3, fp\n \tstrd\tr2, sl, [sp, #80]\t@ 0x50\n-\tldr\tr2, [r4, #24]\n+\tldr\tr2, [r4, #20]\n \tmovs\tr4, #4\n-\tvstr\td16, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #64]\t@ 0x40\n \tstr\tr4, [sp, #52]\t@ 0x34\n-\tstr\tr4, [sp, #100]\t@ 0x64\n \tstr\tr4, [sp, #88]\t@ 0x58\n+\tmovs\tr4, #0\n+\tstr\tr4, [r5, #4]\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tstr\tr4, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #92]\t@ 0x5c\n \tmovs\tr4, #1\n-\tvstr\td16, [sp, #92]\t@ 0x5c\n+\tstr\tr6, [sp, #68]\t@ 0x44\n \tstr\tr4, [sp, #72]\t@ 0x48\n \tstr\tr4, [sp, #108]\t@ 0x6c\n \tmovw\tr4, #769\t@ 0x301\n-\tstr\tr6, [sp, #68]\t@ 0x44\n-\tstr\tr5, [sp, #104]\t@ 0x68\n \tstrh.w\tr4, [sp, #60]\t@ 0x3c\n \tstrh.w\tr4, [sp, #96]\t@ 0x60\n-\tbl\t86ec <__gridxc_gpfa_core_sp_MOD_gpfa_>\n-\tldr\tr3, [pc, #64]\t@ (118e8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x120>)\n-\tldr\tr2, [pc, #64]\t@ (118ec <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x124>)\n+\tbl\t8adc <__gridxc_gpfa_core_sp_MOD_gpfa_>\n+\tldr\tr3, [pc, #64]\t@ (125f4 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x120>)\n+\tldr\tr2, [pc, #64]\t@ (125f8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x124>)\n \tadd\tr3, pc\n \tadd\tr2, pc\n \tstr.w\tr9, [r3]\n-\tldr\tr3, [pc, #40]\t@ (118dc <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x114>)\n+\tldr\tr3, [pc, #40]\t@ (125e8 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x114>)\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #116]\t@ 0x74\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t118d2 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x10a>\n+\tbne.n\t125de <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x10a>\n \tadd\tsp, #124\t@ 0x7c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tstr\tr3, [sp, #20]\n-\tb.n\t11804 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x3c>\n+\tb.n\t12510 <__gridxc_fft_gpfa_MOD_fft_gpfa_sp+0x3c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n \t.word\t0x000000f4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x000000b6\n R_ARM_REL32\t.data\n-\t.word\t0x00000084\n+\t.word\t0x00000086\n R_ARM_REL32\t.bss\n \t.word\t0x0000003a\n R_ARM_REL32\t.data\n \t.word\t0x0000003c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000118f0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp>:\n+000125fc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp>:\n __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3976]\t@ 0xf88\n-\tmov\tr5, r1\n-\tldr\tr1, [pc, #188]\t@ (119c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd0>)\n-\tldr\tr3, [pc, #188]\t@ (119c4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd4>)\n+\tmov\tr4, r1\n+\tldr\tr1, [pc, #172]\t@ (126bc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc0>)\n+\tldr\tr3, [pc, #172]\t@ (126c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc4>)\n \tsub\tsp, #96\t@ 0x60\n \tadd\tr1, pc\n-\tmov\tr4, r0\n-\tldr\tr7, [r5, #0]\n+\tmov\tr5, r0\n+\tldr\tr6, [r4, #0]\n \tmov\tr8, r2\n \tldr\tr3, [r1, r3]\n-\tlsls\tr6, r7, #1\n+\tlsls\tr7, r6, #1\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #92]\t@ 0x5c\n \tmov.w\tr3, #0\n-\tldr\tr3, [pc, #168]\t@ (119c8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd8>)\n+\tldr\tr3, [pc, #152]\t@ (126c4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc8>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n-\tcmp\tr7, r3\n-\tbeq.n\t1192c <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0x3c>\n-\tmov\tr0, r5\n-\tbl\t114e0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n-\tvldr\td16, [pc, #136]\t@ 119b8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc8>\n-\tadd\tr3, sp, #36\t@ 0x24\n-\tmovs\tr2, #8\n-\tmov.w\tr1, #4294967295\t@ 0xffffffff\n-\tstr.w\tr8, [sp, #12]\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr\tr5, [sp, #4]\n-\tadd\tr0, sp, #16\n-\tvst1.32\t{d16}, [r3]\n-\tstr\tr2, [sp, #24]\n-\tstr\tr6, [sp, #48]\t@ 0x30\n-\tadd\tr6, r1\n-\tstr\tr4, [sp, #16]\n-\tadd\tr4, r2\n-\tstr\tr1, [sp, #20]\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr1, sp, #76\t@ 0x4c\n-\tldr\tr2, [pc, #112]\t@ (119cc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xdc>)\n-\tldr\tr3, [pc, #112]\t@ (119d0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xe0>)\n+\tcmp\tr6, r3\n+\tbeq.n\t12638 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0x3c>\n+\tmov\tr0, r4\n+\tbl\t12210 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n+\tldr\tr2, [pc, #140]\t@ (126c8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xcc>)\n+\tadd.w\tr1, r5, #8\n+\tstr\tr5, [sp, #20]\n+\tadd\tr5, sp, #68\t@ 0x44\n+\tldr\tr3, [pc, #136]\t@ (126cc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd0>)\n \tadd\tr2, pc\n-\tvst1.32\t{d16}, [r1]\n+\tstr\tr4, [sp, #4]\n+\tadd\tr0, sp, #20\n+\tstr.w\tr8, [sp, #12]\n \tadd\tr3, pc\n-\tstr\tr4, [sp, #56]\t@ 0x38\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tldr\tr2, [r2, #20]\n \tadds\tr1, r3, #4\n+\tstr\tr4, [sp, #24]\n \tstr\tr1, [sp, #8]\n \tstr\tr1, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tmovs\tr4, #8\n+\tstr\tr4, [sp, #76]\t@ 0x4c\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tstr\tr4, [sp, #28]\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tmovs\tr4, #0\n+\tstr\tr4, [r5, #4]\n+\tstr\tr4, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #52]\t@ 0x34\n+\tsubs\tr7, #1\n+\tstr\tr4, [sp, #32]\n+\tstr\tr4, [sp, #68]\t@ 0x44\n \tmovs\tr4, #1\n-\tvstr\td17, [sp, #28]\n-\tldr\tr2, [r2, #24]\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tstr\tr4, [sp, #84]\t@ 0x54\n+\tstr\tr7, [sp, #88]\t@ 0x58\n+\tstrd\tr4, r4, [sp, #44]\t@ 0x2c\n+\tstrd\tr4, r4, [sp, #80]\t@ 0x50\n \tmovw\tr4, #769\t@ 0x301\n-\tvstr\td17, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tstrh.w\tr4, [sp, #32]\n+\tstrh.w\tr4, [sp, #36]\t@ 0x24\n \tstrh.w\tr4, [sp, #72]\t@ 0x48\n-\tbl\tdd28 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n-\tldr\tr3, [pc, #64]\t@ (119d4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xe4>)\n-\tldr\tr2, [pc, #64]\t@ (119d8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xe8>)\n+\tbl\te7b8 <__gridxc_gpfa_core_dp_MOD_gpfa_>\n+\tldr\tr3, [pc, #52]\t@ (126d0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd4>)\n+\tldr\tr2, [pc, #56]\t@ (126d4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd8>)\n \tadd\tr3, pc\n \tadd\tr2, pc\n-\tstr\tr7, [r3, #0]\n-\tldr\tr3, [pc, #36]\t@ (119c4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xd4>)\n+\tstr\tr6, [r3, #0]\n+\tldr\tr3, [pc, #28]\t@ (126c0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc4>)\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #92]\t@ 0x5c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t119b2 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xc2>\n+\tbne.n\t126b8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp+0xbc>\n \tadd\tsp, #96\t@ 0x60\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x000000b4\n+\t.word\t0x000000a4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000a6\n+\t.word\t0x00000096\n R_ARM_REL32\t.data\n-\t.word\t0x0000006a\n+\t.word\t0x00000080\n R_ARM_REL32\t.bss\n-\t.word\t0x00000068\n+\t.word\t0x0000007a\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000003a\n+\t.word\t0x00000030\n R_ARM_REL32\t.data\n-\t.word\t0x0000003c\n+\t.word\t0x00000032\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000119dc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp>:\n+000126d8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp>:\n __gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3976]\t@ 0xf88\n-\tmov\tr5, r1\n-\tldr\tr1, [pc, #192]\t@ (11ab0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd4>)\n-\tldr\tr3, [pc, #192]\t@ (11ab4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd8>)\n+\tmov\tr4, r1\n+\tldr\tr1, [pc, #172]\t@ (12798 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xc0>)\n+\tldr\tr3, [pc, #172]\t@ (1279c <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xc4>)\n \tsub\tsp, #96\t@ 0x60\n \tadd\tr1, pc\n-\tmov\tr4, r0\n-\tldr\tr7, [r5, #0]\n+\tmov\tr5, r0\n+\tldr\tr6, [r4, #0]\n \tmov\tr8, r2\n \tldr\tr3, [r1, r3]\n-\tlsls\tr6, r7, #1\n+\tlsls\tr7, r6, #1\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #92]\t@ 0x5c\n \tmov.w\tr3, #0\n-\tldr\tr3, [pc, #172]\t@ (11ab8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xdc>)\n+\tldr\tr3, [pc, #152]\t@ (127a0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xc8>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n-\tcmp\tr7, r3\n-\tbeq.n\t11a18 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0x3c>\n-\tmov\tr0, r5\n-\tbl\t114e0 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n-\tvldr\td16, [pc, #140]\t@ 11aa8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xcc>\n-\tadd\tr3, sp, #36\t@ 0x24\n-\tmovs\tr2, #4\n-\tmov.w\tr1, #4294967295\t@ 0xffffffff\n-\tstr.w\tr8, [sp, #12]\n-\tvmov.i32\td17, #0\t@ 0x00000000\n-\tstr\tr5, [sp, #4]\n-\tadd\tr0, sp, #16\n-\tvst1.32\t{d16}, [r3]\n-\tstr\tr2, [sp, #24]\n-\tstr\tr6, [sp, #48]\t@ 0x30\n-\tadd\tr6, r1\n-\tstr\tr4, [sp, #16]\n-\tadd\tr4, r2\n-\tstr\tr1, [sp, #20]\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tadd\tr1, sp, #76\t@ 0x4c\n-\tldr\tr2, [pc, #116]\t@ (11abc <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xe0>)\n-\tldr\tr3, [pc, #116]\t@ (11ac0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xe4>)\n+\tcmp\tr6, r3\n+\tbeq.n\t12714 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0x3c>\n+\tmov\tr0, r4\n+\tbl\t12210 <__gridxc_fft_gpfa_MOD_setgpfa_alloc.constprop.0>\n+\tldr\tr2, [pc, #140]\t@ (127a4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xcc>)\n+\tadds\tr1, r5, #4\n+\tstr\tr5, [sp, #20]\n+\tadd\tr5, sp, #68\t@ 0x44\n+\tldr\tr3, [pc, #136]\t@ (127a8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd0>)\n \tadd\tr2, pc\n-\tvst1.32\t{d16}, [r1]\n+\tstr\tr4, [sp, #4]\n+\tadd\tr0, sp, #20\n+\tstr.w\tr8, [sp, #12]\n \tadd\tr3, pc\n-\tstr\tr4, [sp, #56]\t@ 0x38\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tldr\tr2, [r2, #20]\n \tadds\tr1, r3, #4\n+\tstr\tr4, [sp, #24]\n \tstr\tr1, [sp, #8]\n \tstr\tr1, [sp, #0]\n \tadd\tr1, sp, #56\t@ 0x38\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tmovs\tr4, #4\n+\tstr\tr4, [sp, #76]\t@ 0x4c\n+\tstr\tr4, [sp, #40]\t@ 0x28\n+\tstr\tr4, [sp, #28]\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tmovs\tr4, #0\n+\tstr\tr4, [r5, #4]\n+\tstr\tr4, [sp, #36]\t@ 0x24\n+\tstr\tr7, [sp, #52]\t@ 0x34\n+\tsubs\tr7, #1\n+\tstr\tr4, [sp, #32]\n+\tstr\tr4, [sp, #68]\t@ 0x44\n \tmovs\tr4, #1\n-\tvstr\td17, [sp, #28]\n-\tldr\tr2, [r2, #24]\n-\tstr\tr4, [sp, #44]\t@ 0x2c\n-\tstr\tr4, [sp, #84]\t@ 0x54\n+\tstr\tr7, [sp, #88]\t@ 0x58\n+\tstrd\tr4, r4, [sp, #44]\t@ 0x2c\n+\tstrd\tr4, r4, [sp, #80]\t@ 0x50\n \tmovw\tr4, #769\t@ 0x301\n-\tvstr\td17, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tstrh.w\tr4, [sp, #32]\n+\tstrh.w\tr4, [sp, #36]\t@ 0x24\n \tstrh.w\tr4, [sp, #72]\t@ 0x48\n-\tbl\t86ec <__gridxc_gpfa_core_sp_MOD_gpfa_>\n-\tldr\tr3, [pc, #68]\t@ (11ac4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xe8>)\n-\tldr\tr2, [pc, #68]\t@ (11ac8 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xec>)\n+\tbl\t8adc <__gridxc_gpfa_core_sp_MOD_gpfa_>\n+\tldr\tr3, [pc, #56]\t@ (127ac <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd4>)\n+\tldr\tr2, [pc, #56]\t@ (127b0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd8>)\n \tadd\tr3, pc\n \tadd\tr2, pc\n-\tstr\tr7, [r3, #0]\n-\tldr\tr3, [pc, #40]\t@ (11ab4 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xd8>)\n+\tstr\tr6, [r3, #0]\n+\tldr\tr3, [pc, #28]\t@ (1279c <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xc4>)\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #92]\t@ 0x5c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t11a9e <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xc2>\n+\tbne.n\t12792 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_sp+0xba>\n \tadd\tsp, #96\t@ 0x60\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x000000b8\n+\t.word\t0x000000a4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000aa\n+\t.word\t0x00000096\n R_ARM_REL32\t.data\n-\t.word\t0x0000006e\n+\t.word\t0x00000082\n R_ARM_REL32\t.bss\n-\t.word\t0x0000006c\n+\t.word\t0x0000007c\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000003e\n+\t.word\t0x00000032\n R_ARM_REL32\t.data\n-\t.word\t0x00000040\n+\t.word\t0x00000034\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00011acc <__gridxc_fft_gpfa_MOD_nfft>:\n+000127b4 <__gridxc_fft_gpfa_MOD_nfft>:\n __gridxc_fft_gpfa_MOD_nfft():\n-\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n+\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3688]\t@ 0xe68\n-\tldr\tr1, [pc, #368]\t@ (11c50 <__gridxc_fft_gpfa_MOD_nfft+0x184>)\n-\tsub\tsp, #380\t@ 0x17c\n-\tldr\tr2, [pc, #368]\t@ (11c54 <__gridxc_fft_gpfa_MOD_nfft+0x188>)\n-\tadd\tr5, sp, #12\n+\tstr.w\tr0, [ip, #3672]\t@ 0xe58\n+\tldr\tr2, [pc, #404]\t@ (1295c <__gridxc_fft_gpfa_MOD_nfft+0x1a8>)\n+\tsub\tsp, #388\t@ 0x184\n+\tldr\tr1, [pc, #404]\t@ (12960 <__gridxc_fft_gpfa_MOD_nfft+0x1ac>)\n+\tmov\tr7, r0\n+\tadd\tr2, pc\n+\tadd\tr4, sp, #20\n+\tstr\tr2, [sp, #8]\n+\tmov\tr0, r2\n+\tldr\tr2, [pc, #396]\t@ (12964 <__gridxc_fft_gpfa_MOD_nfft+0x1b0>)\n \tadd\tr1, pc\n-\tldr\tr4, [pc, #368]\t@ (11c58 <__gridxc_fft_gpfa_MOD_nfft+0x18c>)\n+\tstr\tr4, [sp, #12]\n \tmovw\tr3, #65533\t@ 0xfffd\n \tmovt\tr3, #32767\t@ 0x7fff\n-\tadd\tr4, pc\n+\tldr\tr5, [r7, #0]\n \tldr\tr2, [r1, r2]\n-\tldr\tr1, [r0, #0]\n+\tcmp\tr5, r3\n \tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #372]\t@ 0x174\n+\tstr\tr2, [sp, #380]\t@ 0x17c\n \tmov.w\tr2, #0\n-\tstr\tr1, [r5, #0]\n-\tcmp\tr1, r3\n-\tbgt.n\t11b5e <__gridxc_fft_gpfa_MOD_nfft+0x92>\n-\tldr\tr7, [pc, #340]\t@ (11c5c <__gridxc_fft_gpfa_MOD_nfft+0x190>)\n-\tmovw\tr8, #65534\t@ 0xfffe\n-\tmovt\tr8, #32767\t@ 0x7fff\n-\tmov\tr6, r0\n-\tadd\tr7, pc\n-\tadd.w\tlr, r7, #20\n-\tadd.w\tip, r7, #8\n-\tmov\tr2, r1\n-\tldr.w\tr0, [ip], #4\n+\tstr\tr5, [sp, #20]\n+\tbgt.n\t12862 <__gridxc_fft_gpfa_MOD_nfft+0xae>\n+\tldr.w\tr8, [pc, #368]\t@ 12968 <__gridxc_fft_gpfa_MOD_nfft+0x1b4>\n+\tmovw\tr9, #65534\t@ 0xfffe\n+\tmovt\tr9, #32767\t@ 0x7fff\n+\tadd\tr8, pc\n+\tadd.w\tr6, r8, #20\n+\tadd.w\tr4, r8, #8\n+\tmov\tsl, r5\n+\tldr.w\tfp, [r4], #4\n+\tcmp.w\tfp, #0\n+\tblt.w\t1292c <__gridxc_fft_gpfa_MOD_nfft+0x178>\n+\tcmp.w\tsl, #0\n+\tblt.w\t12926 <__gridxc_fft_gpfa_MOD_nfft+0x172>\n+\tmov\tr1, fp\n+\tmov\tr0, sl\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr0, fp, r0, sl\n+\tcbnz\tr0, 12850 <__gridxc_fft_gpfa_MOD_nfft+0x9c>\n+\tmov\tr0, sl\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp.w\tfp, #0\n+\tmov\tsl, r0\n+\tblt.n\t12914 <__gridxc_fft_gpfa_MOD_nfft+0x160>\n \tcmp\tr0, #0\n-\tblt.n\t11b3a <__gridxc_fft_gpfa_MOD_nfft+0x6e>\n-\tcmp\tr2, #0\n-\tblt.n\t11c18 <__gridxc_fft_gpfa_MOD_nfft+0x14c>\n-\tsdiv\tr3, r2, r0\n-\tmls\tr3, r0, r3, r2\n-\tcbnz\tr3, 11b4e <__gridxc_fft_gpfa_MOD_nfft+0x82>\n-\tsdiv\tr2, r2, r0\n+\tblt.n\t12926 <__gridxc_fft_gpfa_MOD_nfft+0x172>\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmls\tr0, fp, r0, sl\n \tcmp\tr0, #0\n-\tbge.n\t11b24 <__gridxc_fft_gpfa_MOD_nfft+0x58>\n-\tsubs\tr3, r2, #1\n-\tcmp\tr2, #0\n-\tble.n\t11b28 <__gridxc_fft_gpfa_MOD_nfft+0x5c>\n-\tsdiv\tr3, r3, r0\n-\tsubs\tr3, #1\n-\tmls\tr3, r0, r3, r2\n-\tcmp\tr3, #0\n-\tbeq.n\t11b32 <__gridxc_fft_gpfa_MOD_nfft+0x66>\n-\tcmp\tlr, ip\n-\tbne.n\t11b1c <__gridxc_fft_gpfa_MOD_nfft+0x50>\n-\tcmp\tr2, #1\n-\tbeq.n\t11c24 <__gridxc_fft_gpfa_MOD_nfft+0x158>\n-\tadds\tr1, #1\n-\tstr\tr1, [r6, #0]\n-\tcmp\tr1, r8\n-\tbne.n\t11b16 <__gridxc_fft_gpfa_MOD_nfft+0x4a>\n-\tldr\tr3, [pc, #256]\t@ (11c60 <__gridxc_fft_gpfa_MOD_nfft+0x194>)\n-\tadd\tr6, sp, #24\n-\tvldr\td16, [pc, #228]\t@ 11c48 <__gridxc_fft_gpfa_MOD_nfft+0x17c>\n-\tmov.w\tr8, #20\n-\tadd\tr3, pc\n-\tldr\tr7, [pc, #244]\t@ (11c64 <__gridxc_fft_gpfa_MOD_nfft+0x198>)\n-\tstr\tr3, [sp, #32]\n-\tmov\tr0, r6\n-\tldr\tr3, [pc, #244]\t@ (11c68 <__gridxc_fft_gpfa_MOD_nfft+0x19c>)\n-\tmov.w\tr9, #4\n-\tvstr\td16, [sp, #24]\n-\tadd\tr7, pc\n+\tbeq.n\t1282e <__gridxc_fft_gpfa_MOD_nfft+0x7a>\n+\tcmp\tr6, r4\n+\tbne.n\t1280c <__gridxc_fft_gpfa_MOD_nfft+0x58>\n+\tcmp.w\tsl, #1\n+\tbeq.n\t1293c <__gridxc_fft_gpfa_MOD_nfft+0x188>\n+\tadds\tr5, #1\n+\tstr\tr5, [r7, #0]\n+\tcmp\tr5, r9\n+\tbne.n\t12806 <__gridxc_fft_gpfa_MOD_nfft+0x52>\n+\tldr\tr3, [pc, #264]\t@ (1296c <__gridxc_fft_gpfa_MOD_nfft+0x1b8>)\n+\tadd\tr4, sp, #32\n \tmovw\tr2, #5037\t@ 0x13ad\n+\tldr\tr5, [pc, #260]\t@ (12970 <__gridxc_fft_gpfa_MOD_nfft+0x1bc>)\n \tadd\tr3, pc\n-\tstr\tr2, [sp, #36]\t@ 0x24\n-\tstr\tr7, [sp, #92]\t@ 0x5c\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstrd\tr3, r2, [sp, #40]\t@ 0x28\n+\tldr\tr3, [pc, #256]\t@ (12974 <__gridxc_fft_gpfa_MOD_nfft+0x1c0>)\n+\tmovs\tr7, #4\n+\tmov\tr0, r4\n+\tadd\tr5, pc\n+\tmovs\tr6, #20\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tadd\tr3, pc\n+\tstr\tr5, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tmovs\tr3, #0\n-\tstr.w\tr8, [sp, #96]\t@ 0x60\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tstr.w\tr9, [sp, #80]\t@ 0x50\n+\tstr\tr7, [sp, #88]\t@ 0x58\n+\tstr\tr6, [sp, #104]\t@ 0x68\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #32]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr1, r5\n-\tmov\tr2, r9\n-\tmov\tr0, r6\n-\tadd.w\tr5, sp, r8\n+\tmov\tr2, r7\n+\tldr\tr1, [sp, #12]\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tmov\tr0, r6\n-\tadd\tr6, sp, #16\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, r7\n-\tmov\tr2, r8\n-\tmov\tr1, r6\n-\tmov\tr0, r5\n+\tadd\tr4, sp, #28\n+\tmov\tr3, r5\n+\tadd\tr5, sp, #24\n+\tmov\tr2, r6\n+\tmov\tr1, r5\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr.w\tr8, [r5]\n-\tadd.w\tr7, r8, #39\t@ 0x27\n-\tcmp\tr7, #1\n-\tmov\tr0, r7\n+\tldr\tr7, [sp, #28]\n+\tadd.w\tr6, r7, #39\t@ 0x27\n+\tcmp\tr6, #1\n+\tmov\tr0, r6\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #152]\t@ (11c6c <__gridxc_fft_gpfa_MOD_nfft+0x1a0>)\n-\tldr\tr6, [sp, #16]\n+\tldr\tr3, [pc, #168]\t@ (12978 <__gridxc_fft_gpfa_MOD_nfft+0x1c4>)\n+\tldr\tr5, [sp, #24]\n \tmov\tr1, r0\n-\tmov\tr5, r0\n+\tmov\tr4, r0\n \tadd\tr3, pc\n \tmovs\tr2, #39\t@ 0x27\n-\tmov\tr0, r7\n-\tstrd\tr8, r6, [sp]\n+\tmov\tr0, r6\n+\tstrd\tr7, r5, [sp]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tcmp.w\tr8, #0\n-\tbgt.n\t11c1c <__gridxc_fft_gpfa_MOD_nfft+0x150>\n-\tldr\tr3, [pc, #128]\t@ (11c70 <__gridxc_fft_gpfa_MOD_nfft+0x1a4>)\n-\tmov\tr1, r7\n-\tmov\tr0, r5\n-\tldr\tr3, [r4, r3]\n+\tcmp\tr7, #0\n+\tbgt.n\t12934 <__gridxc_fft_gpfa_MOD_nfft+0x180>\n+\tldr\tr3, [pc, #148]\t@ (1297c <__gridxc_fft_gpfa_MOD_nfft+0x1c8>)\n+\tmov\tr1, r6\n+\tldr\tr2, [sp, #8]\n+\tmov\tr0, r4\n+\tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #120]\t@ (11c74 <__gridxc_fft_gpfa_MOD_nfft+0x1a8>)\n-\tldr\tr3, [pc, #88]\t@ (11c54 <__gridxc_fft_gpfa_MOD_nfft+0x188>)\n+\tldr\tr2, [pc, #136]\t@ (12980 <__gridxc_fft_gpfa_MOD_nfft+0x1cc>)\n+\tldr\tr3, [pc, #108]\t@ (12964 <__gridxc_fft_gpfa_MOD_nfft+0x1b0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #372]\t@ 0x174\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t11c3e <__gridxc_fft_gpfa_MOD_nfft+0x172>\n-\tmov\tr0, r5\n-\tadd\tsp, #380\t@ 0x17c\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n+\tbne.n\t12956 <__gridxc_fft_gpfa_MOD_nfft+0x1a2>\n+\tmov\tr0, r4\n+\tadd\tsp, #388\t@ 0x184\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n-\tadds\tr3, r2, #1\n-\tb.n\t11b40 <__gridxc_fft_gpfa_MOD_nfft+0x74>\n-\tmov\tr0, r6\n+\tcmp\tr0, #0\n+\tble.n\t12842 <__gridxc_fft_gpfa_MOD_nfft+0x8e>\n+\tadd.w\tr0, sl, #4294967295\t@ 0xffffffff\n+\tmov\tr1, fp\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr0, #1\n+\tb.n\t12828 <__gridxc_fft_gpfa_MOD_nfft+0x74>\n+\tadd.w\tr0, sl, #1\n+\tb.n\t1291c <__gridxc_fft_gpfa_MOD_nfft+0x168>\n+\tcmp.w\tsl, #0\n+\tbgt.n\t12918 <__gridxc_fft_gpfa_MOD_nfft+0x164>\n+\tb.n\t12820 <__gridxc_fft_gpfa_MOD_nfft+0x6c>\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t11bec <__gridxc_fft_gpfa_MOD_nfft+0x120>\n-\tldr\tr2, [pc, #80]\t@ (11c78 <__gridxc_fft_gpfa_MOD_nfft+0x1ac>)\n-\tldr\tr3, [pc, #44]\t@ (11c54 <__gridxc_fft_gpfa_MOD_nfft+0x188>)\n+\tb.n\t128e6 <__gridxc_fft_gpfa_MOD_nfft+0x132>\n+\tldr\tr2, [pc, #68]\t@ (12984 <__gridxc_fft_gpfa_MOD_nfft+0x1d0>)\n+\tldr\tr3, [pc, #36]\t@ (12964 <__gridxc_fft_gpfa_MOD_nfft+0x1b0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #372]\t@ 0x174\n+\tldr\tr3, [sp, #380]\t@ 0x17c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t11c3e <__gridxc_fft_gpfa_MOD_nfft+0x172>\n-\tadd\tsp, #380\t@ 0x17c\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n+\tbne.n\t12956 <__gridxc_fft_gpfa_MOD_nfft+0x1a2>\n+\tadd\tsp, #388\t@ 0x184\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\tnop.w\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x00000168\n+\t.word\t0x0000018c\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000186\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000164\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000148\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000f2\n+\t.word\t0x000000fc\n R_ARM_REL32\t.LC0\n-\t.word\t0x000000e4\n+\t.word\t0x000000f4\n R_ARM_REL32\t.bss\n-\t.word\t0x000000e2\n+\t.word\t0x000000f0\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000090\n+\t.word\t0x000000a0\n R_ARM_REL32\t.LC14\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000074\n+\t.word\t0x00000084\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000004c\n+\t.word\t0x00000040\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -20,53 +20,56 @@\n 0x00000110 616c616c 69617300 2e4c4334 002e4c43 alalias..LC4..LC\n 0x00000120 35002e4c 4336002e 4c433700 2e4c4338 5..LC6..LC7..LC8\n 0x00000130 002e4c43 39002e4c 43313000 2e4c4331 ..LC9..LC10..LC1\n 0x00000140 31005f5f 67726964 78635f66 66745f67 1.__gridxc_fft_g\n 0x00000150 7066615f 4d4f445f 73657467 7066615f pfa_MOD_setgpfa_\n 0x00000160 616c6c6f 632e636f 6e737470 726f702e alloc.constprop.\n 0x00000170 30002e4c 43313400 69707269 6d652e30 0..LC14.iprime.0\n- 0x00000180 005f6766 6f727472 616e5f70 6f775f69 ._gfortran_pow_i\n- 0x00000190 345f6934 005f5f67 72696478 635f6770 4_i4.__gridxc_gp\n- 0x000001a0 66615f63 6f72655f 73705f4d 4f445f67 fa_core_sp_MOD_g\n- 0x000001b0 7066615f 005f474c 4f42414c 5f4f4646 pfa_._GLOBAL_OFF\n- 0x000001c0 5345545f 5441424c 455f005f 5f737461 SET_TABLE_.__sta\n- 0x000001d0 636b5f63 686b5f67 75617264 005f6766 ck_chk_guard._gf\n- 0x000001e0 6f727472 616e5f73 745f7772 69746500 ortran_st_write.\n- 0x000001f0 5f67666f 72747261 6e5f7472 616e7366 _gfortran_transf\n- 0x00000200 65725f69 6e746567 65725f77 72697465 er_integer_write\n- 0x00000210 005f6766 6f727472 616e5f73 745f7772 ._gfortran_st_wr\n- 0x00000220 6974655f 646f6e65 005f6766 6f727472 ite_done._gfortr\n- 0x00000230 616e5f73 7472696e 675f7472 696d006d an_string_trim.m\n- 0x00000240 616c6c6f 63005f67 666f7274 72616e5f alloc._gfortran_\n- 0x00000250 636f6e63 61745f73 7472696e 67006672 concat_string.fr\n- 0x00000260 6565005f 5f677269 6478635f 7379735f ee.__gridxc_sys_\n- 0x00000270 4d4f445f 64696500 5f5f7374 61636b5f MOD_die.__stack_\n- 0x00000280 63686b5f 6661696c 005f5f67 72696478 chk_fail.__gridx\n- 0x00000290 635f6770 66615f63 6f72655f 64705f4d c_gpfa_core_dp_M\n- 0x000002a0 4f445f67 7066615f 005f5f67 72696478 OD_gpfa_.__gridx\n- 0x000002b0 635f6666 745f6770 66615f4d 4f445f73 c_fft_gpfa_MOD_s\n- 0x000002c0 65746770 66610073 696e636f 73005f5f etgpfa.sincos.__\n- 0x000002d0 67726964 78635f66 66745f67 7066615f gridxc_fft_gpfa_\n- 0x000002e0 4d4f445f 73657467 7066615f 63686563 MOD_setgpfa_chec\n- 0x000002f0 6b005f67 666f7274 72616e5f 73746f70 k._gfortran_stop\n- 0x00000300 5f737472 696e6700 5f67666f 72747261 _string._gfortra\n- 0x00000310 6e5f6f73 5f657272 6f725f61 74005f67 n_os_error_at._g\n- 0x00000320 666f7274 72616e5f 72756e74 696d655f fortran_runtime_\n- 0x00000330 6572726f 725f6174 005f6766 6f727472 error_at._gfortr\n- 0x00000340 616e5f72 756e7469 6d655f65 72726f72 an_runtime_error\n- 0x00000350 005f5f67 72696478 635f6666 745f6770 .__gridxc_fft_gp\n- 0x00000360 66615f4d 4f445f66 66745f67 7066615f fa_MOD_fft_gpfa_\n- 0x00000370 6470005f 5f677269 6478635f 6666745f dp.__gridxc_fft_\n- 0x00000380 67706661 5f4d4f44 5f666674 5f677066 gpfa_MOD_fft_gpf\n- 0x00000390 615f7370 005f5f67 72696478 635f6666 a_sp.__gridxc_ff\n- 0x000003a0 745f6770 66615f4d 4f445f66 66745f67 t_gpfa_MOD_fft_g\n- 0x000003b0 7066615f 657a5f64 70005f5f 67726964 pfa_ez_dp.__grid\n- 0x000003c0 78635f66 66745f67 7066615f 4d4f445f xc_fft_gpfa_MOD_\n- 0x000003d0 6666745f 67706661 5f657a5f 7370005f fft_gpfa_ez_sp._\n- 0x000003e0 5f677269 6478635f 6666745f 67706661 _gridxc_fft_gpfa\n- 0x000003f0 5f4d4f44 5f6e6666 74005f5f 67726964 _MOD_nfft.__grid\n- 0x00000400 78635f66 66745f67 7066615f 4d4f445f xc_fft_gpfa_MOD_\n- 0x00000410 74726967 73005f5f 67726964 78635f66 trigs.__gridxc_f\n- 0x00000420 66745f67 7066615f 4d4f445f 6e6f6c64 ft_gpfa_MOD_nold\n- 0x00000430 005f5f67 72696478 635f6666 745f6770 .__gridxc_fft_gp\n- 0x00000440 66615f4d 4f445f6d 736700 fa_MOD_msg.\n+ 0x00000180 005f5f61 65616269 5f696469 76005f5f .__aeabi_idiv.__\n+ 0x00000190 61656162 695f7569 64697600 5f67666f aeabi_uidiv._gfo\n+ 0x000001a0 72747261 6e5f706f 775f6934 5f693400 rtran_pow_i4_i4.\n+ 0x000001b0 5f5f6165 6162695f 69646976 6d6f6400 __aeabi_idivmod.\n+ 0x000001c0 5f5f6772 69647863 5f677066 615f636f __gridxc_gpfa_co\n+ 0x000001d0 72655f73 705f4d4f 445f6770 66615f00 re_sp_MOD_gpfa_.\n+ 0x000001e0 5f474c4f 42414c5f 4f464653 45545f54 _GLOBAL_OFFSET_T\n+ 0x000001f0 41424c45 5f005f5f 73746163 6b5f6368 ABLE_.__stack_ch\n+ 0x00000200 6b5f6775 61726400 5f67666f 72747261 k_guard._gfortra\n+ 0x00000210 6e5f7374 5f777269 7465005f 67666f72 n_st_write._gfor\n+ 0x00000220 7472616e 5f747261 6e736665 725f696e tran_transfer_in\n+ 0x00000230 74656765 725f7772 69746500 5f67666f teger_write._gfo\n+ 0x00000240 72747261 6e5f7374 5f777269 74655f64 rtran_st_write_d\n+ 0x00000250 6f6e6500 5f67666f 72747261 6e5f7374 one._gfortran_st\n+ 0x00000260 72696e67 5f747269 6d006d61 6c6c6f63 ring_trim.malloc\n+ 0x00000270 005f6766 6f727472 616e5f63 6f6e6361 ._gfortran_conca\n+ 0x00000280 745f7374 72696e67 00667265 65005f5f t_string.free.__\n+ 0x00000290 67726964 78635f73 79735f4d 4f445f64 gridxc_sys_MOD_d\n+ 0x000002a0 6965005f 5f737461 636b5f63 686b5f66 ie.__stack_chk_f\n+ 0x000002b0 61696c00 5f5f6772 69647863 5f677066 ail.__gridxc_gpf\n+ 0x000002c0 615f636f 72655f64 705f4d4f 445f6770 a_core_dp_MOD_gp\n+ 0x000002d0 66615f00 5f5f6772 69647863 5f666674 fa_.__gridxc_fft\n+ 0x000002e0 5f677066 615f4d4f 445f7365 74677066 _gpfa_MOD_setgpf\n+ 0x000002f0 61007369 6e636f73 005f5f67 72696478 a.sincos.__gridx\n+ 0x00000300 635f6666 745f6770 66615f4d 4f445f73 c_fft_gpfa_MOD_s\n+ 0x00000310 65746770 66615f63 6865636b 005f6766 etgpfa_check._gf\n+ 0x00000320 6f727472 616e5f73 746f705f 73747269 ortran_stop_stri\n+ 0x00000330 6e67005f 67666f72 7472616e 5f6f735f ng._gfortran_os_\n+ 0x00000340 6572726f 725f6174 005f6766 6f727472 error_at._gfortr\n+ 0x00000350 616e5f72 756e7469 6d655f65 72726f72 an_runtime_error\n+ 0x00000360 5f617400 5f67666f 72747261 6e5f7275 _at._gfortran_ru\n+ 0x00000370 6e74696d 655f6572 726f7200 5f5f6772 ntime_error.__gr\n+ 0x00000380 69647863 5f666674 5f677066 615f4d4f idxc_fft_gpfa_MO\n+ 0x00000390 445f6666 745f6770 66615f64 70005f5f D_fft_gpfa_dp.__\n+ 0x000003a0 67726964 78635f66 66745f67 7066615f gridxc_fft_gpfa_\n+ 0x000003b0 4d4f445f 6666745f 67706661 5f737000 MOD_fft_gpfa_sp.\n+ 0x000003c0 5f5f6772 69647863 5f666674 5f677066 __gridxc_fft_gpf\n+ 0x000003d0 615f4d4f 445f6666 745f6770 66615f65 a_MOD_fft_gpfa_e\n+ 0x000003e0 7a5f6470 005f5f67 72696478 635f6666 z_dp.__gridxc_ff\n+ 0x000003f0 745f6770 66615f4d 4f445f66 66745f67 t_gpfa_MOD_fft_g\n+ 0x00000400 7066615f 657a5f73 70005f5f 67726964 pfa_ez_sp.__grid\n+ 0x00000410 78635f66 66745f67 7066615f 4d4f445f xc_fft_gpfa_MOD_\n+ 0x00000420 6e666674 005f5f67 72696478 635f6666 nfft.__gridxc_ff\n+ 0x00000430 745f6770 66615f4d 4f445f74 72696773 t_gpfa_MOD_trigs\n+ 0x00000440 005f5f67 72696478 635f6666 745f6770 .__gridxc_fft_gp\n+ 0x00000450 66615f4d 4f445f6e 6f6c6400 5f5f6772 fa_MOD_nold.__gr\n+ 0x00000460 69647863 5f666674 5f677066 615f4d4f idxc_fft_gpfa_MO\n+ 0x00000470 445f6d73 6700 D_msg.\n \n"}]}, {"source1": "interpolation.F90.o", "source2": "interpolation.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 11964 (bytes into file)\n+ Start of section headers: 12160 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 16\n Section header string table index: 15\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,25 +1,25 @@\n-There are 16 section headers, starting at offset 0x2ebc:\n+There are 16 section headers, starting at offset 0x2f80:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 001dcc 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 002a20 0003c8 08 I 13 1 4\n- [ 3] .data PROGBITS 00000000 001e04 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 001e04 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 001e04 000206 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 002010 0000b0 00 A 0 0 8\n- [ 7] .data.rel PROGBITS 00000000 0020c0 00001c 00 WA 0 0 4\n- [ 8] .rel.data.rel REL 00000000 002de8 000018 08 I 13 7 4\n- [ 9] .data.rel.ro.local PROGBITS 00000000 0020dc 000050 00 WA 0 0 4\n- [10] .rel.data.rel.ro.local REL 00000000 002e00 000030 08 I 13 9 4\n- [11] .note.GNU-stack PROGBITS 00000000 00212c 000000 00 0 0 1\n- [12] .ARM.attributes ARM_ATTRIBUTES 00000000 00212c 000033 00 0 0 1\n- [13] .symtab SYMTAB 00000000 002160 000490 10 14 46 4\n- [14] .strtab STRTAB 00000000 0025f0 000430 00 0 0 1\n- [15] .shstrtab STRTAB 00000000 002e30 00008c 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 001e24 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 002ab4 0003f8 08 I 13 1 4\n+ [ 3] .data PROGBITS 00000000 001e5c 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 001e5c 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 001e5c 000206 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 002068 0000b0 00 A 0 0 8\n+ [ 7] .data.rel PROGBITS 00000000 002118 00001c 00 WA 0 0 4\n+ [ 8] .rel.data.rel REL 00000000 002eac 000018 08 I 13 7 4\n+ [ 9] .data.rel.ro.local PROGBITS 00000000 002134 000050 00 WA 0 0 4\n+ [10] .rel.data.rel.ro.local REL 00000000 002ec4 000030 08 I 13 9 4\n+ [11] .note.GNU-stack PROGBITS 00000000 002184 000000 00 0 0 1\n+ [12] .ARM.attributes ARM_ATTRIBUTES 00000000 002184 00002d 00 0 0 1\n+ [13] .symtab SYMTAB 00000000 0021b4 0004b0 10 14 46 4\n+ [14] .strtab STRTAB 00000000 002664 00044d 00 0 0 1\n+ [15] .shstrtab STRTAB 00000000 002ef4 00008c 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,76 +1,78 @@\n \n-Symbol table '.symtab' contains 73 entries:\n+Symbol table '.symtab' contains 75 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 2: 0000030c 0 NOTYPE LOCAL DEFAULT 1 $d\n- 3: 00000318 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 2: 00000330 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 3: 0000033c 0 NOTYPE LOCAL DEFAULT 1 $t\n 4: 00000000 0 SECTION LOCAL DEFAULT 5 .rodata.str1.4\n 5: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 6: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 7: 00000004 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 8: 0000002c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n- 9: 0000040c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 00000430 0 NOTYPE LOCAL DEFAULT 1 $d\n 10: 00000080 0 NOTYPE LOCAL DEFAULT 5 .LC3\n- 11: 00000418 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 00000904 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 11: 0000043c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 00000930 0 NOTYPE LOCAL DEFAULT 1 $d\n 13: 000000ac 0 NOTYPE LOCAL DEFAULT 5 .LC4\n- 14: 0000091c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 15: 00000a68 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 14: 00000948 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 15: 00000a90 0 NOTYPE LOCAL DEFAULT 1 $d\n 16: 000000d4 0 NOTYPE LOCAL DEFAULT 5 .LC5\n 17: 000000d8 0 NOTYPE LOCAL DEFAULT 5 .LC6\n 18: 0000010c 0 NOTYPE LOCAL DEFAULT 5 .LC7\n- 19: 00000a84 0 NOTYPE LOCAL DEFAULT 1 $t\n- 20: 00000d68 0 NOTYPE LOCAL DEFAULT 1 $d\n- 21: 00000d9c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 000010f8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 23: 00001114 0 NOTYPE LOCAL DEFAULT 1 $t\n- 24: 000013e0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00000aac 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 20: 00000da8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 00000ddc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 22: 00001128 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 23: 00001144 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 24: 000013f8 0 NOTYPE LOCAL DEFAULT 1 $d\n 25: 00000144 0 NOTYPE LOCAL DEFAULT 5 .LC8\n 26: 00000148 0 NOTYPE LOCAL DEFAULT 5 .LC9\n 27: 0000014c 0 NOTYPE LOCAL DEFAULT 5 .LC10\n 28: 00000190 0 NOTYPE LOCAL DEFAULT 5 .LC11\n 29: 000001ac 0 NOTYPE LOCAL DEFAULT 5 .LC12\n- 30: 000013fc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 31: 000015f0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 32: 00001604 0 NOTYPE LOCAL DEFAULT 1 $t\n- 33: 00001b08 0 NOTYPE LOCAL DEFAULT 1 $d\n- 34: 000013fd 1864 FUNC LOCAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_master.localalias\n- 35: 00001b44 0 NOTYPE LOCAL DEFAULT 1 $t\n- 36: 00001c78 0 NOTYPE LOCAL DEFAULT 1 $d\n- 37: 00001b45 360 FUNC LOCAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_x.localalias\n- 38: 00001cac 0 NOTYPE LOCAL DEFAULT 1 $t\n- 39: 00001dc0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 30: 00001414 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 31: 00001610 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 32: 00001624 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 33: 00001b60 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 34: 00001415 1928 FUNC LOCAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_master.localalias\n+ 35: 00001b9c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 36: 00001cd0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 37: 00001b9d 360 FUNC LOCAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_x.localalias\n+ 38: 00001d04 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 39: 00001e18 0 NOTYPE LOCAL DEFAULT 1 $d\n 40: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 41: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n 42: 00000000 0 NOTYPE LOCAL DEFAULT 7 $d\n 43: 00000000 0 SECTION LOCAL DEFAULT 9 .data.rel.ro.local\n 44: 00000000 0 NOTYPE LOCAL DEFAULT 9 $d\n 45: 00000000 80 OBJECT LOCAL DEFAULT 9 jumptable.108.0\n- 46: 00000001 792 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n- 47: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 48: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 49: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 50: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 51: 00000319 166 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n- 52: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 53: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 54: 000003c1 88 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_clean_spline\n- 55: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n- 56: 00000419 1284 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_polint\n- 57: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 58: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 59: 0000091d 360 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_dx\n- 60: 00000a85 792 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_x\n- 61: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_select_string\n- 62: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n- 63: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n- 64: 00000d9d 888 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_n\n- 65: 00001115 744 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline\n- 66: 000013fd 1864 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_master\n- 67: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n- 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n- 69: 00001b45 360 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_x\n- 70: 00001cad 288 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_dx\n- 71: 00000000 28 OBJECT GLOBAL DEFAULT 7 __gridxc_interpolation_MOD___vtab_gridxc_interpolation_Spline_t\n- 72: 00000008 168 OBJECT GLOBAL DEFAULT 6 __gridxc_interpolation_MOD___def_init_gridxc_interpolation_Spline_t\n+ 46: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idivmod\n+ 47: 00000000 0 NOTYPE GLOBAL DEFAULT UND __aeabi_idiv\n+ 48: 00000001 828 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n+ 49: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 50: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 51: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 52: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 53: 0000033d 168 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n+ 54: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 55: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 56: 000003e5 88 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_clean_spline\n+ 57: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n+ 58: 0000043d 1292 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_polint\n+ 59: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 60: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 61: 00000949 356 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_dx\n+ 62: 00000aad 816 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_x\n+ 63: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_select_string\n+ 64: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n+ 65: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n+ 66: 00000ddd 872 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline_n\n+ 67: 00001145 720 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_evaluate_spline\n+ 68: 00001415 1928 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_master\n+ 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n+ 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n+ 71: 00001b9d 360 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_x\n+ 72: 00001d05 288 FUNC GLOBAL DEFAULT 1 __gridxc_interpolation_MOD_generate_spline_dx\n+ 73: 00000000 28 OBJECT GLOBAL DEFAULT 7 __gridxc_interpolation_MOD___vtab_gridxc_interpolation_Spline_t\n+ 74: 00000008 168 OBJECT GLOBAL DEFAULT 6 __gridxc_interpolation_MOD___def_init_gridxc_interpolation_Spline_t\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,139 +1,145 @@\n \n-Relocation section '.rel.text' at offset 0x2a20 contains 121 entries:\n+Relocation section '.rel.text' at offset 0x2ab4 contains 127 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000027e 00002f0a R_ARM_THM_CALL 00000000 free\n-0000028a 00002f0a R_ARM_THM_CALL 00000000 free\n-00000298 00002f0a R_ARM_THM_CALL 00000000 free\n-00000306 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0000030c 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000310 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000314 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000330 0000340a R_ARM_THM_CALL 00000000 memcpy\n-0000034e 0000350a R_ARM_THM_CALL 00000000 malloc\n-00000358 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00000372 0000350a R_ARM_THM_CALL 00000000 malloc\n-0000037c 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00000398 0000350a R_ARM_THM_CALL 00000000 malloc\n-000003d4 00002f0a R_ARM_THM_CALL 00000000 free\n-000003e0 00002f0a R_ARM_THM_CALL 00000000 free\n-000003ec 00002f0a R_ARM_THM_CALL 00000000 free\n-00000406 0000370a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-0000040c 00000603 R_ARM_REL32 00000000 .LC0\n-00000410 00000703 R_ARM_REL32 00000004 .LC1\n-00000414 00000803 R_ARM_REL32 0000002c .LC2\n-00000668 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00000672 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00000680 0000390a R_ARM_THM_CALL 00000000 memset\n-0000068a 0000390a R_ARM_THM_CALL 00000000 memset\n-00000900 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000904 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000908 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000090c 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000910 00000a03 R_ARM_REL32 00000080 .LC3\n-00000914 00003a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000918 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000a78 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000a7c 00003a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000a80 00000d03 R_ARM_REL32 000000ac .LC4\n-00000b5a 00003d0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n-00000c62 00003e0a R_ARM_THM_CALL 00000000 log\n-00000c9c 00003f0a R_ARM_THM_CALL 00000000 exp\n-00000cba 00003f0a R_ARM_THM_CALL 00000000 exp\n-00000d62 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000d78 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d7c 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000d80 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d84 00001003 R_ARM_REL32 000000d4 .LC5\n-00000d88 00003a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000d8c 00001103 R_ARM_REL32 000000d8 .LC6\n-00000d90 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n-00000d94 00001203 R_ARM_REL32 0000010c .LC7\n-00000d98 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000f70 00003d0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n-00000f9a 00003e0a R_ARM_THM_CALL 00000000 log\n-00000fda 00003f0a R_ARM_THM_CALL 00000000 exp\n-00000ff6 00003f0a R_ARM_THM_CALL 00000000 exp\n-00001100 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001104 00001103 R_ARM_REL32 000000d8 .LC6\n-00001108 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n-0000110c 00003a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001110 00001203 R_ARM_REL32 0000010c .LC7\n-00001180 00003d0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n-00001294 00003e0a R_ARM_THM_CALL 00000000 log\n-000012d0 00003f0a R_ARM_THM_CALL 00000000 exp\n-000012ec 00003f0a R_ARM_THM_CALL 00000000 exp\n-000013e8 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000013ec 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n-000013f0 00003a1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000013f4 00001203 R_ARM_REL32 0000010c .LC7\n-000013f8 00001103 R_ARM_REL32 000000d8 .LC6\n-000014f8 00002f0a R_ARM_THM_CALL 00000000 free\n-00001500 00002f0a R_ARM_THM_CALL 00000000 free\n-0000150a 00002f0a R_ARM_THM_CALL 00000000 free\n-000015dc 00003e0a R_ARM_THM_CALL 00000000 log\n-000015f8 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000015fc 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001600 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000018fa 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00001928 0000350a R_ARM_THM_CALL 00000000 malloc\n-00001958 0000350a R_ARM_THM_CALL 00000000 malloc\n-0000198a 0000350a R_ARM_THM_CALL 00000000 malloc\n-00001a10 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00001a1a 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00001a24 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00001acc 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001ada 0000430a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001ae8 0000430a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001af6 0000430a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001afe 0000440a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00001b18 00001003 R_ARM_REL32 000000d4 .LC5\n-00001b1c 00001903 R_ARM_REL32 00000144 .LC8\n-00001b20 00001903 R_ARM_REL32 00000144 .LC8\n-00001b24 00001a03 R_ARM_REL32 00000148 .LC9\n-00001b28 00001c03 R_ARM_REL32 00000190 .LC11\n-00001b2c 00001d03 R_ARM_REL32 000001ac .LC12\n-00001b30 00001c03 R_ARM_REL32 00000190 .LC11\n-00001b34 00001d03 R_ARM_REL32 000001ac .LC12\n-00001b38 00001c03 R_ARM_REL32 00000190 .LC11\n-00001b3c 00001d03 R_ARM_REL32 000001ac .LC12\n-00001b40 00001b03 R_ARM_REL32 0000014c .LC10\n-00001bc6 0000390a R_ARM_THM_CALL 00000000 memset\n-00001bd2 00002f0a R_ARM_THM_CALL 00000000 free\n-00001bde 00002f0a R_ARM_THM_CALL 00000000 free\n-00001c30 00002f0a R_ARM_THM_CALL 00000000 free\n-00001c38 00002f0a R_ARM_THM_CALL 00000000 free\n-00001c64 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001c74 0000370a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c80 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001c84 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001c88 00002803 R_ARM_REL32 00000000 .rodata\n-00001c8c 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001c90 00002803 R_ARM_REL32 00000000 .rodata\n-00001c94 00002803 R_ARM_REL32 00000000 .rodata\n-00001c98 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001c9c 00002803 R_ARM_REL32 00000000 .rodata\n-00001ca0 00000603 R_ARM_REL32 00000000 .LC0\n-00001ca4 00000703 R_ARM_REL32 00000004 .LC1\n-00001ca8 00000803 R_ARM_REL32 0000002c .LC2\n-00001d78 0000340a R_ARM_THM_CALL 00000000 memcpy\n-00001dbc 0000300a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001dc0 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001dc4 0000321a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001dc8 00003119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003a8 0000341e R_ARM_THM_JUMP24 00000000 memcpy\n-00001c04 00002f1e R_ARM_THM_JUMP24 00000000 free\n+00000212 00002e0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000021a 00002f0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000232 00002e0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000023a 00002f0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000272 00002e0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000027e 00002f0a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000002a0 0000310a R_ARM_THM_CALL 00000000 free\n+000002ac 0000310a R_ARM_THM_CALL 00000000 free\n+000002ba 0000310a R_ARM_THM_CALL 00000000 free\n+0000032c 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000330 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000334 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000338 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000354 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00000374 0000370a R_ARM_THM_CALL 00000000 malloc\n+0000037e 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00000398 0000370a R_ARM_THM_CALL 00000000 malloc\n+000003a2 0000360a R_ARM_THM_CALL 00000000 memcpy\n+000003be 0000370a R_ARM_THM_CALL 00000000 malloc\n+000003f8 0000310a R_ARM_THM_CALL 00000000 free\n+00000404 0000310a R_ARM_THM_CALL 00000000 free\n+00000410 0000310a R_ARM_THM_CALL 00000000 free\n+0000042a 0000390a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00000430 00000603 R_ARM_REL32 00000000 .LC0\n+00000434 00000703 R_ARM_REL32 00000004 .LC1\n+00000438 00000803 R_ARM_REL32 0000002c .LC2\n+0000068c 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00000696 0000360a R_ARM_THM_CALL 00000000 memcpy\n+000006a4 00003b0a R_ARM_THM_CALL 00000000 memset\n+000006ae 00003b0a R_ARM_THM_CALL 00000000 memset\n+0000092a 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000930 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000934 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000938 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000093c 00000a03 R_ARM_REL32 00000080 .LC3\n+00000940 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000944 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000aa0 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000aa4 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000aa8 00000d03 R_ARM_REL32 000000ac .LC4\n+00000b96 00003f0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n+00000c9c 0000400a R_ARM_THM_CALL 00000000 log\n+00000cd8 0000410a R_ARM_THM_CALL 00000000 exp\n+00000cf4 0000410a R_ARM_THM_CALL 00000000 exp\n+00000da0 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000db8 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000dbc 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000dc0 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000dc4 00001003 R_ARM_REL32 000000d4 .LC5\n+00000dc8 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000dcc 00001103 R_ARM_REL32 000000d8 .LC6\n+00000dd0 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n+00000dd4 00001203 R_ARM_REL32 0000010c .LC7\n+00000dd8 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000fb4 00003f0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n+00000fdc 0000400a R_ARM_THM_CALL 00000000 log\n+0000101c 0000410a R_ARM_THM_CALL 00000000 exp\n+00001038 0000410a R_ARM_THM_CALL 00000000 exp\n+00001130 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001134 00001103 R_ARM_REL32 000000d8 .LC6\n+00001138 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n+0000113c 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001140 00001203 R_ARM_REL32 0000010c .LC7\n+000011ac 00003f0a R_ARM_THM_CALL 00000000 _gfortran_select_string\n+000012c0 0000400a R_ARM_THM_CALL 00000000 log\n+000012fc 0000410a R_ARM_THM_CALL 00000000 exp\n+00001318 0000410a R_ARM_THM_CALL 00000000 exp\n+00001400 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001404 00002b03 R_ARM_REL32 00000000 .data.rel.ro.local\n+00001408 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+0000140c 00001203 R_ARM_REL32 0000010c .LC7\n+00001410 00001103 R_ARM_REL32 000000d8 .LC6\n+00001514 0000310a R_ARM_THM_CALL 00000000 free\n+0000151c 0000310a R_ARM_THM_CALL 00000000 free\n+00001526 0000310a R_ARM_THM_CALL 00000000 free\n+000015f8 0000400a R_ARM_THM_CALL 00000000 log\n+00001618 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000161c 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001620 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001922 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00001956 0000370a R_ARM_THM_CALL 00000000 malloc\n+00001988 0000370a R_ARM_THM_CALL 00000000 malloc\n+000019b8 0000370a R_ARM_THM_CALL 00000000 malloc\n+00001a5a 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00001a64 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00001a70 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00001b26 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001b34 0000450a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001b42 0000450a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001b50 0000450a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001b58 0000460a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00001b70 00001003 R_ARM_REL32 000000d4 .LC5\n+00001b74 00001903 R_ARM_REL32 00000144 .LC8\n+00001b78 00001903 R_ARM_REL32 00000144 .LC8\n+00001b7c 00001a03 R_ARM_REL32 00000148 .LC9\n+00001b80 00001c03 R_ARM_REL32 00000190 .LC11\n+00001b84 00001d03 R_ARM_REL32 000001ac .LC12\n+00001b88 00001c03 R_ARM_REL32 00000190 .LC11\n+00001b8c 00001d03 R_ARM_REL32 000001ac .LC12\n+00001b90 00001c03 R_ARM_REL32 00000190 .LC11\n+00001b94 00001d03 R_ARM_REL32 000001ac .LC12\n+00001b98 00001b03 R_ARM_REL32 0000014c .LC10\n+00001c1e 00003b0a R_ARM_THM_CALL 00000000 memset\n+00001c2a 0000310a R_ARM_THM_CALL 00000000 free\n+00001c36 0000310a R_ARM_THM_CALL 00000000 free\n+00001c88 0000310a R_ARM_THM_CALL 00000000 free\n+00001c90 0000310a R_ARM_THM_CALL 00000000 free\n+00001cbc 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001ccc 0000390a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001cd8 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001cdc 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001ce0 00002803 R_ARM_REL32 00000000 .rodata\n+00001ce4 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001ce8 00002803 R_ARM_REL32 00000000 .rodata\n+00001cec 00002803 R_ARM_REL32 00000000 .rodata\n+00001cf0 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001cf4 00002803 R_ARM_REL32 00000000 .rodata\n+00001cf8 00000603 R_ARM_REL32 00000000 .LC0\n+00001cfc 00000703 R_ARM_REL32 00000004 .LC1\n+00001d00 00000803 R_ARM_REL32 0000002c .LC2\n+00001dd0 0000360a R_ARM_THM_CALL 00000000 memcpy\n+00001e14 0000320a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001e18 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001e1c 0000331a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001e20 00003419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000003ce 0000361e R_ARM_THM_JUMP24 00000000 memcpy\n+00001c5c 0000311e R_ARM_THM_JUMP24 00000000 free\n \n-Relocation section '.rel.data.rel' at offset 0x2de8 contains 3 entries:\n+Relocation section '.rel.data.rel' at offset 0x2eac contains 3 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000000c 00004802 R_ARM_ABS32 00000008 __gridxc_interpolation_MOD___def_init_gridxc_interpolation_Spline_t\n-00000010 00003302 R_ARM_ABS32 00000319 __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n-00000014 00002e02 R_ARM_ABS32 00000001 __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n+0000000c 00004a02 R_ARM_ABS32 00000008 __gridxc_interpolation_MOD___def_init_gridxc_interpolation_Spline_t\n+00000010 00003502 R_ARM_ABS32 0000033d __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n+00000014 00003002 R_ARM_ABS32 00000001 __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n \n-Relocation section '.rel.data.rel.ro.local' at offset 0x2e00 contains 6 entries:\n+Relocation section '.rel.data.rel.ro.local' at offset 0x2ec4 contains 6 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000014 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n 0000001c 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n 00000028 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n 00000030 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n 0000003c 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n 00000044 00000402 R_ARM_ABS32 00000000 .rodata.str1.4\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,26 +1,27 @@\n-\tJ%!\tHxD\n-cK3!dHxD[\n+^K3!_HxD[\n F[F\"F)F0F\n Attempt to DEALLOCATE unallocated '%s'\n At line 655 of file /build/reproducible-path/libgridxc-2.0.1/src/interpolation.F90\n polint: ERROR: two mesh points are equal\n evaluate_spline ERROR: x out of range\n evaluate_spline/find_interval ERROR: x out of range\n evaluate_spline/find_interval ERROR: unknown mesh type\n Integer overflow when calculating the amount of memory to allocate\n Error allocating %lu bytes\n In file '/build/reproducible-path/libgridxc-2.0.1/src/interpolation.F90', around line 301\n __gridxc_interpolation_MOD_generate_spline_master.localalias\n __gridxc_interpolation_MOD_generate_spline_x.localalias\n jumptable.108.0\n+__aeabi_idivmod\n+__aeabi_idiv\n __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t\n __stack_chk_fail\n-_GLOBAL_OFFSET_TABLE_\n __stack_chk_guard\n+_GLOBAL_OFFSET_TABLE_\n __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t\n __gridxc_interpolation_MOD_clean_spline\n _gfortran_runtime_error_at\n __gridxc_interpolation_MOD_polint\n __gridxc_sys_MOD_die\n __gridxc_interpolation_MOD_evaluate_spline_dx\n __gridxc_interpolation_MOD_evaluate_spline_x\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -4,311 +4,333 @@\n Disassembly of section .text:\n \n 00000000 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t>:\n __gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n-\tldr\tr2, [pc, #760]\t@ (30c <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x30c>)\n-\tsub\tsp, #28\n-\tldr\tr3, [pc, #760]\t@ (310 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x310>)\n-\tadd\tr2, pc\n+\tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n+\tsub\tsp, #44\t@ 0x2c\n \tadd\tr7, sp, #0\n-\tmov\tsl, r1\n-\tmov\tr5, r0\n-\tldr\tr3, [r2, r3]\n-\tldrsb.w\tr2, [r0, #16]\n-\tmov\tr0, sp\n+\tldr\tr3, [pc, #792]\t@ (330 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x330>)\n+\tldrsb.w\tr6, [r0, #16]\n+\tmov\tr2, sp\n+\tmov\tfp, r0\n+\tstr\tr1, [r7, #8]\n+\tldr\tr1, [pc, #784]\t@ (334 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x334>)\n+\tadd\tr1, pc\n+\tldr\tr3, [r1, r3]\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [r7, #20]\n+\tstr\tr3, [r7, #36]\t@ 0x24\n \tmov.w\tr3, #0\n-\tadds\tr3, r2, #1\n+\tadds\tr3, r6, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n-\tcmp\tr0, r1\n+\tcmp\tr2, r1\n \tbeq.n\t5a <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x5a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr0, sp\n-\tcmp\tr0, r1\n+\tmov\tr2, sp\n+\tcmp\tr2, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n \tbne.n\t4c <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x4c>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t2b4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2b4>\n-\tbic.w\tr3, r2, r2, asr #31\n-\tmov\tr0, sp\n-\tstr.w\tsp, [r7, #12]\n+\tbne.w\t2dc <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2dc>\n+\tbic.w\tr3, r6, r6, asr #31\n+\tmov\tr2, sp\n+\tmov\tlr, sp\n \tlsls\tr3, r3, #2\n \tadds\tr3, #7\n \tbic.w\tr1, r3, #7\n \tbfc\tr3, #0, #12\n \tsub.w\tr3, sp, r3\n-\tcmp\tr0, r3\n-\tbeq.n\t94 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x94>\n+\tcmp\tr2, r3\n+\tbeq.n\t92 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x92>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr0, sp\n-\tcmp\tr0, r3\n+\tmov\tr2, sp\n+\tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t86 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x86>\n+\tbne.n\t84 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x84>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t2fc <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2fc>\n-\tmov\tr3, sp\n-\tmovs\tr1, #1\n-\tmov\tfp, sp\n-\tcmp\tr2, #0\n-\tmov.w\tr6, r3, lsr #2\n-\tldr\tr3, [r7, #12]\n-\tstr\tr1, [r3, #0]\n-\tble.w\t1ba <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1ba>\n-\tsubs\tr3, r2, #1\n-\tcmp\tr3, #3\n-\tsxtb.w\tip, r3\n-\tbls.n\t138 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x138>\n-\tadd.w\tr1, r5, #24\n-\tadd.w\tr0, r5, #72\t@ 0x48\n-\tvld3.32\t{d16,d18,d20}, [r1]\n-\tadd.w\tr1, r5, #48\t@ 0x30\n-\tvld3.32\t{d17,d19,d21}, [r1]\n-\tlsrs\tr1, r3, #2\n-\tcmp\tr1, #1\n-\tvst1.32\t{d16-d17}, [fp]\n-\tbeq.n\t132 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x132>\n-\tcmp\tr1, #2\n-\tvld3.32\t{d16,d18,d20}, [r0]\n-\tadd.w\tr0, r5, #96\t@ 0x60\n-\tvld3.32\t{d17,d19,d21}, [r0]\n-\tadd.w\tr0, fp, #16\n-\tvst1.32\t{d16-d17}, [r0]\n-\tadd.w\tr0, r5, #120\t@ 0x78\n-\tbeq.n\t132 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x132>\n-\tvld3.32\t{d16,d18,d20}, [r0]\n-\tadd.w\tr0, r5, #144\t@ 0x90\n-\tadd.w\tr4, fp, #48\t@ 0x30\n-\tcmp\tr1, #3\n-\tvld3.32\t{d17,d19,d21}, [r0]\n-\tadd.w\tr0, fp, #32\n-\tvst1.32\t{d16-d17}, [r0]\n-\tadd.w\tr0, r5, #168\t@ 0xa8\n-\tbeq.n\t132 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x132>\n-\tadd.w\tr1, fp, r1, lsl #4\n-\tmov\tlr, r0\n-\tadds\tr0, #48\t@ 0x30\n-\tvld3.32\t{d16,d18,d20}, [lr]!\n-\tvld3.32\t{d17,d19,d21}, [lr]\n-\tvst1.32\t{d16-d17}, [r4]!\n-\tcmp\tr4, r1\n-\tbne.n\t11e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x11e>\n-\tbic.w\tr3, r3, #3\n-\tadds\tr1, r3, #1\n-\tsubs\tr3, r1, #1\n-\tmovs\tr0, #12\n-\tmov.w\tr8, r1, lsl #2\n-\tadd.w\tlr, r1, #1\n-\tadd.w\tr4, fp, r8\n-\tcmp\tr2, lr\n-\tmla\tr3, r0, r3, r5\n-\tldr\tr3, [r3, #24]\n-\tstr.w\tr3, [r4, #-4]\n-\tblt.n\t17e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x17e>\n-\tmla\tr3, r0, r1, r5\n-\tldr\tr3, [r3, #24]\n-\tstr.w\tr3, [r8, r6, lsl #2]\n-\tadds\tr6, r1, #2\n-\tcmp\tr6, r2\n-\tbgt.n\t17e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x17e>\n-\tmla\tlr, r0, lr, r5\n-\tadds\tr1, #3\n-\tcmp\tr2, r1\n-\tldr.w\tr3, [lr, #24]\n-\tstr\tr3, [r4, #4]\n-\tblt.n\t17e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x17e>\n-\tmla\tr6, r0, r6, r5\n-\tldr\tr3, [r6, #24]\n-\tstr\tr3, [r4, #8]\n-\tldr\tr6, [r7, #12]\n-\tmov\tr0, r5\n+\tbne.w\t322 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x322>\n+\tmovs\tr3, #1\n+\tmov\tip, sp\n+\tcmp\tr6, #0\n+\tstr.w\tr3, [lr]\n+\tble.w\t1c4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1c4>\n+\tadd.w\tr8, r6, #4294967295\t@ 0xffffffff\n+\tldr.w\tr3, [fp, #24]\n+\tcmp\tr6, #1\n+\tstr.w\tr3, [ip]\n+\tsxtb.w\tr8, r8\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #36]\t@ 0x24\n+\tcmp\tr6, #2\n+\tstr.w\tr3, [ip, #4]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #48]\t@ 0x30\n+\tcmp\tr6, #3\n+\tstr.w\tr3, [ip, #8]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #60]\t@ 0x3c\n+\tcmp\tr6, #4\n+\tstr.w\tr3, [ip, #12]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #72]\t@ 0x48\n+\tcmp\tr6, #5\n+\tstr.w\tr3, [ip, #16]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #84]\t@ 0x54\n+\tcmp\tr6, #6\n+\tstr.w\tr3, [ip, #20]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #96]\t@ 0x60\n+\tcmp\tr6, #7\n+\tstr.w\tr3, [ip, #24]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #108]\t@ 0x6c\n+\tcmp\tr6, #8\n+\tstr.w\tr3, [ip, #28]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #120]\t@ 0x78\n+\tcmp\tr6, #9\n+\tstr.w\tr3, [ip, #32]\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #132]\t@ 0x84\n+\tcmp\tr6, #10\n+\tstr.w\tr3, [ip, #36]\t@ 0x24\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #144]\t@ 0x90\n+\tcmp\tr6, #11\n+\tstr.w\tr3, [ip, #40]\t@ 0x28\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #156]\t@ 0x9c\n+\tcmp\tr6, #12\n+\tstr.w\tr3, [ip, #44]\t@ 0x2c\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #168]\t@ 0xa8\n+\tcmp\tr6, #13\n+\tstr.w\tr3, [ip, #48]\t@ 0x30\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #180]\t@ 0xb4\n+\tcmp\tr6, #14\n+\tstr.w\tr3, [ip, #52]\t@ 0x34\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #192]\t@ 0xc0\n+\tcmp\tr6, #15\n+\tstr.w\tr3, [ip, #56]\t@ 0x38\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tldr.w\tr3, [fp, #204]\t@ 0xcc\n+\tcmp\tr6, #16\n+\tstr.w\tr3, [ip, #60]\t@ 0x3c\n+\tbeq.n\t18e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x18e>\n+\tmov\tr0, fp\n+\tadd.w\tr4, ip, #60\t@ 0x3c\n+\tmovs\tr1, #17\n+\tldr.w\tr3, [r0, #216]\t@ 0xd8\n+\tadds\tr1, #1\n+\tadds\tr0, #12\n+\tcmp\tr6, r1\n+\tstr.w\tr3, [r4, #4]!\n+\tbge.n\t17e <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x17e>\n+\tmov\tr0, fp\n+\tmov\tr5, lr\n \tmovs\tr1, #0\n \tmovs\tr4, #1\n \tldr\tr3, [r0, #32]\n-\tsxtb.w\tlr, r1\n-\tmov.w\tr8, #4294967295\t@ 0xffffffff\n-\tcmp\tlr, ip\n+\tsxtb\tr2, r1\n+\tcmp\tr2, r8\n \tit\teq\n-\tcmpeq\tr3, r8\n-\tbeq.w\t2bc <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2bc>\n-\tldr.w\tlr, [r0, #28]\n+\tcmpeq.w\tr3, #4294967295\t@ 0xffffffff\n+\tbeq.w\t2e4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2e4>\n+\tldr\tr2, [r0, #28]\n \tadds\tr1, #1\n \tadds\tr0, #12\n-\tcmp\tr2, r1\n-\tsub.w\tr3, r3, lr\n+\tcmp\tr1, r6\n+\tsub.w\tr3, r3, r2\n \tadd.w\tr3, r3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tmul.w\tr4, r3, r4\n-\tstr.w\tr4, [r6, #4]!\n-\tbne.n\t186 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x186>\n-\tldr\tr3, [r7, #12]\n-\tldr.w\tr6, [r3, r2, lsl #2]\n-\tcmp\tr6, #0\n-\tble.w\t2d8 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2d8>\n-\tstr.w\tsl, [r7, #8]\n-\tmovs\tr4, #0\n-\tmov\tr8, r5\n+\tstr.w\tr4, [r5, #4]!\n+\tbne.n\t196 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x196>\n+\tldr.w\tr1, [lr, r6, lsl #2]\n+\tcmp\tr1, #0\n+\tble.w\t2fe <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2fe>\n \tmov\tsl, r6\n-\tcmp\tr2, #0\n-\tble.n\t2b0 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2b0>\n-\tcmp\tr2, #2\n-\tble.w\t2f6 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2f6>\n-\tldr\tr0, [r7, #12]\n-\tsubs\tr3, r2, #3\n-\tmovs\tr5, #1\n-\tbic.w\tr3, r3, #1\n+\tmov.w\tr8, #0\n+\tcmp.w\tsl, #0\n+\tstr\tr1, [r7, #12]\n+\tstrd\tip, lr, [r7, #24]\n+\tble.n\t2d8 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2d8>\n+\tcmp.w\tsl, #2\n+\tble.w\t31c <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x31c>\n+\tldr\tr3, [r7, #24]\n+\tsub.w\tr4, sl, #3\n+\tmovs\tr6, #1\n+\tbic.w\tr4, r4, #1\n+\tsubs\tr3, #4\n+\tstr\tr3, [r7, #20]\n+\tldr\tr3, [r7, #28]\n+\tmovs\tr5, #0\n+\tadds\tr4, #3\n+\tmov\tr9, r6\n+\tadds\tr3, #4\n \tstr.w\tsl, [r7, #4]\n-\tmovs\tr1, #0\n-\tadds\tr3, #3\n-\tmov\tr6, r5\n-\tsub.w\tr9, fp, #4\n-\tadd.w\tlr, r0, #4\n-\tmov\tsl, r2\n-\tldr\tr2, [r7, #12]\n-\tldr.w\tip, [fp, r6, lsl #2]\n-\tldr.w\tr0, [r2, r6, lsl #2]\n-\tsdiv\tr2, r4, r0\n-\tmls\tr2, r0, r2, r4\n-\tsdiv\tr2, r2, r5\n-\tldr.w\tr5, [r9, r6, lsl #2]\n-\tmla\tr2, r5, r2, r1\n-\tldr.w\tr5, [lr, r6, lsl #2]\n-\tadds\tr6, #2\n-\tcmp\tr3, r6\n-\tsdiv\tr1, r4, r5\n-\tmls\tr1, r5, r1, r4\n-\tsdiv\tr1, r1, r0\n-\tmla\tr1, ip, r1, r2\n-\tbne.n\t1f8 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1f8>\n-\tmov\tr2, sl\n+\tstr\tr3, [r7, #16]\n+\tldr\tr3, [r7, #28]\n+\tmov\tr0, r8\n+\tldr.w\tsl, [r3, r9, lsl #2]\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr0, r1\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #20]\n+\tldr.w\tr1, [r3, r9, lsl #2]\n+\tldr\tr3, [r7, #16]\n+\tldr.w\tr6, [r3, r9, lsl #2]\n+\tmla\tr5, r1, r0, r5\n+\tmov\tr0, r8\n+\tmov\tr1, r6\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr0, r1\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [r7, #24]\n+\tldr.w\tr3, [r3, r9, lsl #2]\n+\tadd.w\tr9, r9, #2\n+\tcmp\tr9, r4\n+\tmla\tr5, r3, r0, r5\n+\tbne.n\t208 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x208>\n \tldr.w\tsl, [r7, #4]\n-\tadd.w\tr6, r3, #1073741824\t@ 0x40000000\n-\tldr\tr0, [r7, #12]\n-\tsubs\tr6, #1\n-\tmov\tlr, r2\n-\tlsls\tr6, r6, #2\n-\tsub.w\tip, r6, #4\n-\tadd\tr6, r0\n-\tadd\tip, fp\n-\tldr.w\tr5, [r6, #4]!\n-\tadds\tr3, #1\n-\tldr.w\tr2, [ip, #4]!\n-\tcmp\tr3, lr\n-\tsdiv\tr0, r4, r5\n-\tmls\tr0, r5, r0, r4\n-\tldr.w\tr5, [r6, #-4]\n-\tsdiv\tr0, r0, r5\n-\tmla\tr1, r2, r0, r1\n-\tble.n\t24a <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x24a>\n+\tadd.w\tr9, r4, #1073741824\t@ 0x40000000\n+\tldr\tr3, [r7, #28]\n+\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n+\tmov.w\tr9, r9, lsl #2\n+\tsub.w\tr6, r9, #4\n+\tadd\tr9, r3\n+\tldr\tr3, [r7, #24]\n+\tadd\tr6, r3\n+\tldr.w\tr1, [r9, #4]!\n+\tmov\tr0, r8\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr0, r1\n+\tadds\tr4, #1\n+\tldr.w\tr1, [r9, #-4]\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr.w\tr3, [r6, #4]!\n+\tcmp\tsl, r4\n+\tmla\tr5, r3, r0, r5\n+\tbge.n\t26c <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x26c>\n \tldr\tr3, [r7, #8]\n-\tmul.w\tr1, r3, r1\n-\tldr.w\tr3, [r8]\n-\tadds\tr5, r3, r1\n-\tbeq.n\t2a2 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2a2>\n-\tldr\tr0, [r5, #60]\t@ 0x3c\n-\tcbz\tr0, 286 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x286>\n+\tmul.w\tr5, r3, r5\n+\tldr.w\tr4, [fp]\n+\tadds\tr4, r4, r5\n+\tbeq.n\t2c4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2c4>\n+\tldr\tr0, [r4, #60]\t@ 0x3c\n+\tcbz\tr0, 2a8 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2a8>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr3, #0\n-\tstr\tr3, [r5, #60]\t@ 0x3c\n-\tldr\tr0, [r5, #96]\t@ 0x60\n-\tcbz\tr0, 292 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x292>\n+\tstr\tr3, [r4, #60]\t@ 0x3c\n+\tldr\tr0, [r4, #96]\t@ 0x60\n+\tcbz\tr0, 2b4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2b4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr3, #0\n-\tstr\tr3, [r5, #96]\t@ 0x60\n-\tldr.w\tr0, [r5, #132]\t@ 0x84\n-\tcbz\tr0, 2a2 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2a2>\n+\tstr\tr3, [r4, #96]\t@ 0x60\n+\tldr.w\tr0, [r4, #132]\t@ 0x84\n+\tcbz\tr0, 2c4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2c4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r5, #132]\t@ 0x84\n-\tadds\tr4, #1\n-\tcmp\tsl, r4\n-\tbeq.n\t2d8 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2d8>\n-\tldrsb.w\tr2, [r8, #16]\n-\tcmp\tr2, #0\n-\tbgt.n\t1d4 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1d4>\n-\tmovs\tr1, #0\n-\tb.n\t272 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x272>\n+\tstr.w\tr3, [r4, #132]\t@ 0x84\n+\tldr\tr3, [r7, #12]\n+\tadd.w\tr8, r8, #1\n+\tcmp\tr3, r8\n+\tbeq.n\t2fe <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x2fe>\n+\tldrsb.w\tsl, [fp, #16]\n+\tcmp.w\tsl, #0\n+\tbgt.n\t1e0 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1e0>\n+\tmovs\tr5, #0\n+\tb.n\t294 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x294>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tb.n\t68 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x68>\n \tadds\tr1, #1\n \tnegs\tr4, r4\n \tadds\tr0, #12\n-\tcmp\tr2, r1\n-\tstr.w\tr4, [r6, #4]!\n-\tbne.w\t186 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x186>\n-\tldr\tr3, [r7, #12]\n-\tldr.w\tr6, [r3, r2, lsl #2]\n-\tcmp\tr6, #0\n-\tbgt.w\t1c6 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1c6>\n-\tldr\tr2, [pc, #56]\t@ (314 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x314>)\n-\tldr\tr3, [pc, #52]\t@ (310 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x310>)\n+\tcmp\tr1, r6\n+\tstr.w\tr4, [r5, #4]!\n+\tbne.w\t196 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x196>\n+\tldr.w\tr1, [lr, r6, lsl #2]\n+\tcmp\tr1, #0\n+\tbgt.w\t1ce <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x1ce>\n+\tldr\tr2, [pc, #56]\t@ (338 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x338>)\n+\tldr\tr3, [pc, #44]\t@ (330 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x330>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [r7, #20]\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t306 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x306>\n+\tbne.n\t32c <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x32c>\n \tmovs\tr0, #0\n-\tadds\tr7, #28\n+\tadds\tr7, #44\t@ 0x2c\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tmovs\tr1, #0\n-\tmovs\tr3, #1\n-\tb.n\t236 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x236>\n+\tmovs\tr5, #0\n+\tmovs\tr4, #1\n+\tb.n\t254 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0x254>\n \tsubs\tr1, #4\n \tadd.w\tr3, sp, r1\n \tstr\tr0, [r3, #0]\n-\tb.n\ta2 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0xa2>\n+\tb.n\ta0 <__gridxc_interpolation_MOD___final_gridxc_interpolation_Spline_t+0xa0>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x000002f2\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000034\n+\t.word\t0x0000030e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000032\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00000318 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t>:\n+0000033c <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t>:\n __gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t():\n \tpush\t{r3, r4, r5, r6, r7, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4072]\t@ 0xfe8\n \tmov\tr5, r1\n \tmov\tr4, r0\n \tmov\tr1, r0\n \tmovs\tr2, #168\t@ 0xa8\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tcmp\tr5, r4\n-\tbeq.n\t3b0 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x98>\n+\tbeq.n\t3d6 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x9a>\n \tldr\tr7, [r4, #60]\t@ 0x3c\n-\tcbz\tr7, 3b2 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x9a>\n+\tcmp\tr7, #0\n+\tbeq.n\t3d8 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x9c>\n \tldrd\tr3, r6, [r4, #88]\t@ 0x58\n \tsubs\tr6, r6, r3\n \tadds\tr6, #1\n \tlsls\tr6, r6, #3\n \tcmp\tr6, #1\n \tmov\tr0, r6\n \tit\tcc\n@@ -317,15 +339,15 @@\n R_ARM_THM_CALL\tmalloc\n \tmov\tr1, r7\n \tmov\tr2, r6\n \tstr\tr0, [r5, #60]\t@ 0x3c\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr7, [r4, #96]\t@ 0x60\n-\tcbz\tr7, 3ba <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0xa2>\n+\tcbz\tr7, 3e0 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0xa4>\n \tldrd\tr3, r6, [r4, #124]\t@ 0x7c\n \tsubs\tr6, r6, r3\n \tadds\tr6, #1\n \tlsls\tr6, r6, #3\n \tcmp\tr6, #1\n \tmov\tr0, r6\n \tit\tcc\n@@ -334,15 +356,15 @@\n R_ARM_THM_CALL\tmalloc\n \tmov\tr2, r6\n \tmov\tr1, r7\n \tstr\tr0, [r5, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr.w\tr6, [r4, #132]\t@ 0x84\n-\tcbz\tr6, 3ac <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x94>\n+\tcbz\tr6, 3d2 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x96>\n \tldrd\tr4, r2, [r4, #160]\t@ 0xa0\n \tsubs\tr4, r2, r4\n \tadds\tr4, #1\n \tlsls\tr4, r4, #3\n \tcmp\tr4, #1\n \tmov\tr0, r4\n \tit\tcc\n@@ -356,261 +378,260 @@\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemcpy\n \tstr.w\tr6, [r5, #132]\t@ 0x84\n \tpop\t{r3, r4, r5, r6, r7, pc}\n \tstr\tr7, [r5, #60]\t@ 0x3c\n \tldr\tr7, [r4, #96]\t@ 0x60\n \tcmp\tr7, #0\n-\tbne.n\t360 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x48>\n+\tbne.n\t386 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x4a>\n \tstr\tr7, [r5, #96]\t@ 0x60\n-\tb.n\t380 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x68>\n-\tnop\n+\tb.n\t3a6 <__gridxc_interpolation_MOD___copy_gridxc_interpolation_Spline_t+0x6a>\n \n-000003c0 <__gridxc_interpolation_MOD_clean_spline>:\n+000003e4 <__gridxc_interpolation_MOD_clean_spline>:\n __gridxc_interpolation_MOD_clean_spline():\n \tpush\t{r3, r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4080]\t@ 0xff0\n \tmov\tr4, r0\n \tldr\tr0, [r0, #60]\t@ 0x3c\n-\tcbz\tr0, 3f4 <__gridxc_interpolation_MOD_clean_spline+0x34>\n+\tcbz\tr0, 418 <__gridxc_interpolation_MOD_clean_spline+0x34>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r4, #96]\t@ 0x60\n \tmovs\tr5, #0\n \tstr\tr5, [r4, #60]\t@ 0x3c\n-\tcbz\tr0, 3fa <__gridxc_interpolation_MOD_clean_spline+0x3a>\n+\tcbz\tr0, 41e <__gridxc_interpolation_MOD_clean_spline+0x3a>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r4, #132]\t@ 0x84\n \tstr\tr5, [r4, #96]\t@ 0x60\n-\tcbz\tr0, 3fa <__gridxc_interpolation_MOD_clean_spline+0x3a>\n+\tcbz\tr0, 41e <__gridxc_interpolation_MOD_clean_spline+0x3a>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr.w\tr5, [r4, #132]\t@ 0x84\n \tmovs\tr3, #0\n \tstr\tr3, [r4, #56]\t@ 0x38\n \tpop\t{r3, r4, r5, pc}\n-\tldr\tr2, [pc, #16]\t@ (40c <__gridxc_interpolation_MOD_clean_spline+0x4c>)\n-\tldr\tr1, [pc, #16]\t@ (410 <__gridxc_interpolation_MOD_clean_spline+0x50>)\n-\tldr\tr0, [pc, #20]\t@ (414 <__gridxc_interpolation_MOD_clean_spline+0x54>)\n+\tldr\tr2, [pc, #16]\t@ (430 <__gridxc_interpolation_MOD_clean_spline+0x4c>)\n+\tldr\tr1, [pc, #16]\t@ (434 <__gridxc_interpolation_MOD_clean_spline+0x50>)\n+\tldr\tr0, [pc, #20]\t@ (438 <__gridxc_interpolation_MOD_clean_spline+0x54>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n \tnop\n \t.word\t0x00000008\n R_ARM_REL32\t.LC0\n \t.word\t0x0000000a\n R_ARM_REL32\t.LC1\n \t.word\t0x0000000c\n R_ARM_REL32\t.LC2\n \n-00000418 <__gridxc_interpolation_MOD_polint>:\n+0000043c <__gridxc_interpolation_MOD_polint>:\n __gridxc_interpolation_MOD_polint():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3976]\t@ 0xf88\n \tsub\tsp, #84\t@ 0x54\n \tadd\tr7, sp, #0\n \tldr\tr5, [r2, #0]\n-\tldr.w\tr2, [pc, #1236]\t@ 904 <__gridxc_interpolation_MOD_polint+0x4ec>\n+\tldr.w\tr2, [pc, #1244]\t@ 930 <__gridxc_interpolation_MOD_polint+0x4f4>\n \tmov\tr9, r1\n \tstr\tr3, [r7, #20]\n \tadd\tr2, pc\n \tldr\tr4, [r7, #120]\t@ 0x78\n-\tldr.w\tr3, [pc, #1228]\t@ 908 <__gridxc_interpolation_MOD_polint+0x4f0>\n+\tldr.w\tr3, [pc, #1236]\t@ 934 <__gridxc_interpolation_MOD_polint+0x4f8>\n \tstr\tr4, [r7, #48]\t@ 0x30\n \tldr\tr4, [r7, #124]\t@ 0x7c\n \tstr\tr0, [r7, #24]\n \tmov\tr0, sp\n \tstr\tr4, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #76]\t@ 0x4c\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1208]\t@ 90c <__gridxc_interpolation_MOD_polint+0x4f4>\n+\tldr.w\tr3, [pc, #1216]\t@ 938 <__gridxc_interpolation_MOD_polint+0x4fc>\n \tadd\tr3, pc\n \tstr\tr3, [r7, #4]\n \tbic.w\tr3, r5, r5, asr #31\n \tlsls\tr3, r3, #3\n \tmov\tr1, r3\n \tadds\tr3, #7\n \tbic.w\tr2, r1, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr0, r2\n-\tbeq.n\t482 <__gridxc_interpolation_MOD_polint+0x6a>\n+\tbeq.n\t4a6 <__gridxc_interpolation_MOD_polint+0x6a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t474 <__gridxc_interpolation_MOD_polint+0x5c>\n+\tbne.n\t498 <__gridxc_interpolation_MOD_polint+0x5c>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t5ca <__gridxc_interpolation_MOD_polint+0x1b2>\n+\tbne.w\t5ee <__gridxc_interpolation_MOD_polint+0x1b2>\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr2, r2, #15\n \tbic.w\tr1, r3, #7\n \tsub.w\tr2, sp, r2\n \tstr.w\tsp, [r7, #40]\t@ 0x28\n \tcmp\tr0, r2\n-\tbeq.n\t4b8 <__gridxc_interpolation_MOD_polint+0xa0>\n+\tbeq.n\t4dc <__gridxc_interpolation_MOD_polint+0xa0>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4aa <__gridxc_interpolation_MOD_polint+0x92>\n+\tbne.n\t4ce <__gridxc_interpolation_MOD_polint+0x92>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t5d4 <__gridxc_interpolation_MOD_polint+0x1bc>\n+\tbne.w\t5f8 <__gridxc_interpolation_MOD_polint+0x1bc>\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tbic.w\tr2, r3, #7\n \tsub.w\tr1, sp, r1\n \tstr.w\tsp, [r7, #36]\t@ 0x24\n \tcmp\tr0, r1\n-\tbeq.n\t4ee <__gridxc_interpolation_MOD_polint+0xd6>\n+\tbeq.n\t512 <__gridxc_interpolation_MOD_polint+0xd6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4e0 <__gridxc_interpolation_MOD_polint+0xc8>\n+\tbne.n\t504 <__gridxc_interpolation_MOD_polint+0xc8>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 4fe <__gridxc_interpolation_MOD_polint+0xe6>\n+\tcbz\tr2, 522 <__gridxc_interpolation_MOD_polint+0xe6>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tbic.w\tr2, r3, #7\n \tsub.w\tr1, sp, r1\n \tstr.w\tsp, [r7, #32]\n \tcmp\tr0, r1\n-\tbeq.n\t526 <__gridxc_interpolation_MOD_polint+0x10e>\n+\tbeq.n\t54a <__gridxc_interpolation_MOD_polint+0x10e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t518 <__gridxc_interpolation_MOD_polint+0x100>\n+\tbne.n\t53c <__gridxc_interpolation_MOD_polint+0x100>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 536 <__gridxc_interpolation_MOD_polint+0x11e>\n+\tcbz\tr2, 55a <__gridxc_interpolation_MOD_polint+0x11e>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tbic.w\tr2, r3, #7\n \tsub.w\tr1, sp, r1\n \tstr.w\tsp, [r7, #28]\n \tcmp\tr0, r1\n-\tbeq.n\t55e <__gridxc_interpolation_MOD_polint+0x146>\n+\tbeq.n\t582 <__gridxc_interpolation_MOD_polint+0x146>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t550 <__gridxc_interpolation_MOD_polint+0x138>\n+\tbne.n\t574 <__gridxc_interpolation_MOD_polint+0x138>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 56e <__gridxc_interpolation_MOD_polint+0x156>\n+\tcbz\tr2, 592 <__gridxc_interpolation_MOD_polint+0x156>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tbic.w\tr2, r3, #7\n \tsub.w\tr1, sp, r1\n \tstr.w\tsp, [r7, #60]\t@ 0x3c\n \tcmp\tr0, r1\n-\tbeq.n\t596 <__gridxc_interpolation_MOD_polint+0x17e>\n+\tbeq.n\t5ba <__gridxc_interpolation_MOD_polint+0x17e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t588 <__gridxc_interpolation_MOD_polint+0x170>\n+\tbne.n\t5ac <__gridxc_interpolation_MOD_polint+0x170>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 5a6 <__gridxc_interpolation_MOD_polint+0x18e>\n+\tcbz\tr2, 5ca <__gridxc_interpolation_MOD_polint+0x18e>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r3, #7\n \tbic.w\tr1, r1, #15\n \tstr.w\tsp, [r7, #56]\t@ 0x38\n \tsub.w\tr1, sp, r1\n \tmov\tr0, sp\n \tcmp\tr0, r1\n-\tbeq.n\t5de <__gridxc_interpolation_MOD_polint+0x1c6>\n+\tbeq.n\t602 <__gridxc_interpolation_MOD_polint+0x1c6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t5ba <__gridxc_interpolation_MOD_polint+0x1a2>\n+\tb.n\t5de <__gridxc_interpolation_MOD_polint+0x1a2>\n \tsubs\tr1, #4\n \tadd.w\tr2, sp, r1\n \tstr\tr0, [r2, #0]\n-\tb.n\t490 <__gridxc_interpolation_MOD_polint+0x78>\n+\tb.n\t4b4 <__gridxc_interpolation_MOD_polint+0x78>\n \tsubs\tr1, #4\n \tadd.w\tr2, sp, r1\n \tstr\tr0, [r2, #0]\n-\tb.n\t4c6 <__gridxc_interpolation_MOD_polint+0xae>\n+\tb.n\t4ea <__gridxc_interpolation_MOD_polint+0xae>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 5ee <__gridxc_interpolation_MOD_polint+0x1d6>\n+\tcbz\tr2, 612 <__gridxc_interpolation_MOD_polint+0x1d6>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r3, #7\n \tbic.w\tr1, r1, #15\n \tstr.w\tsp, [r7, #52]\t@ 0x34\n \tsub.w\tr1, sp, r1\n \tmov\tr0, sp\n \tcmp\tr0, r1\n-\tbeq.n\t612 <__gridxc_interpolation_MOD_polint+0x1fa>\n+\tbeq.n\t636 <__gridxc_interpolation_MOD_polint+0x1fa>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t602 <__gridxc_interpolation_MOD_polint+0x1ea>\n+\tb.n\t626 <__gridxc_interpolation_MOD_polint+0x1ea>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 622 <__gridxc_interpolation_MOD_polint+0x20a>\n+\tcbz\tr2, 646 <__gridxc_interpolation_MOD_polint+0x20a>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tmov\tr8, sp\n \tbic.w\tr2, r2, #15\n \tbic.w\tr3, r3, #7\n \tsub.w\tr2, sp, r2\n \tmov\tr1, sp\n \tcmp\tr1, r2\n-\tbeq.n\t644 <__gridxc_interpolation_MOD_polint+0x22c>\n+\tbeq.n\t668 <__gridxc_interpolation_MOD_polint+0x22c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tb.n\t634 <__gridxc_interpolation_MOD_polint+0x21c>\n+\tb.n\t658 <__gridxc_interpolation_MOD_polint+0x21c>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 654 <__gridxc_interpolation_MOD_polint+0x23c>\n+\tcbz\tr3, 678 <__gridxc_interpolation_MOD_polint+0x23c>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tmov\tr6, sp\n \tcmp\tr5, #0\n-\tble.w\t8e0 <__gridxc_interpolation_MOD_polint+0x4c8>\n+\tble.w\t90a <__gridxc_interpolation_MOD_polint+0x4ce>\n \tldr.w\tfp, [r7, #40]\t@ 0x28\n \tlsls\tr4, r5, #3\n \tmov\tr1, r9\n \tmov\tr2, r4\n \tmov\tr0, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n@@ -639,16 +660,16 @@\n \tldr\tr1, [r7, #48]\t@ 0x30\n \tldrd\tr2, r3, [r3]\n \tstrd\tr2, r3, [r1]\n \tldr\tr1, [r7, #44]\t@ 0x2c\n \tmov.w\tr2, #0\n \tmov.w\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tbeq.w\t878 <__gridxc_interpolation_MOD_polint+0x460>\n-\tldr\tr3, [pc, #596]\t@ (910 <__gridxc_interpolation_MOD_polint+0x4f8>)\n+\tbeq.w\t8a2 <__gridxc_interpolation_MOD_polint+0x466>\n+\tldr\tr3, [pc, #604]\t@ (93c <__gridxc_interpolation_MOD_polint+0x500>)\n \tsubs\tr4, r5, #1\n \tadd\tr3, pc\n \tstr\tr3, [r7, #0]\n \tmovs\tr3, #1\n \tstr\tr3, [r7, #68]\t@ 0x44\n \tmov\tr3, fp\n \tadds\tr3, #8\n@@ -661,1903 +682,1896 @@\n \tldr\tr2, [r7, #68]\t@ 0x44\n \tmov\tr0, r8\n \tmov\tsl, r3\n \tadd.w\tr9, r3, r2, lsl #3\n \tmov\tr2, r3\n \tmov\tr1, r9\n \tmovs\tr3, #0\n-\tvldmia\tr2!, {d16}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr1!, {d6}\n \tcmp\tr3, r4\n-\tvsub.f64\td16, d16, d17\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t6e4 <__gridxc_interpolation_MOD_polint+0x2cc>\n+\tvsub.f64\td7, d7, d6\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t708 <__gridxc_interpolation_MOD_polint+0x2cc>\n \tmov\tr2, r8\n \tmovs\tr3, #1\n-\tb.n\t708 <__gridxc_interpolation_MOD_polint+0x2f0>\n+\tb.n\t72c <__gridxc_interpolation_MOD_polint+0x2f0>\n \tadds\tr3, #1\n \tcmp\tr3, r4\n-\tbgt.w\t894 <__gridxc_interpolation_MOD_polint+0x47c>\n-\tvldmia\tr2!, {d16}\n-\tvcmp.f64\td16, #0.0\n+\tbgt.w\t8be <__gridxc_interpolation_MOD_polint+0x482>\n+\tvldmia\tr2!, {d7}\n+\tvcmp.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t700 <__gridxc_interpolation_MOD_polint+0x2e8>\n-\tldr\tr3, [pc, #508]\t@ (914 <__gridxc_interpolation_MOD_polint+0x4fc>)\n+\tbne.n\t724 <__gridxc_interpolation_MOD_polint+0x2e8>\n+\tldr\tr3, [pc, #516]\t@ (940 <__gridxc_interpolation_MOD_polint+0x504>)\n \tmovs\tr1, #40\t@ 0x28\n \tldr\tr2, [r7, #4]\n \tldr\tr0, [r7, #0]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [r7, #20]\n-\tvldr\td17, [r3]\n+\tvldr\td6, [r3]\n \tldr\tr2, [r7, #56]\t@ 0x38\n \tmovs\tr3, #0\n \tmov\tlr, r2\n-\tvldmia\tsl!, {d16}\n+\tvldmia\tsl!, {d7}\n \tadds\tr3, #1\n \tcmp\tr3, r4\n-\tvsub.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t730 <__gridxc_interpolation_MOD_polint+0x318>\n-\tldr\tr2, [r7, #52]\t@ 0x34\n+\tvsub.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t754 <__gridxc_interpolation_MOD_polint+0x318>\n+\tldr\tr1, [r7, #52]\t@ 0x34\n \tmovs\tr3, #0\n-\tmov\tip, r2\n-\tvldmia\tr9!, {d16}\n+\tmov\tr2, r1\n+\tvldmia\tr9!, {d7}\n \tadds\tr3, #1\n \tcmp\tr3, r4\n-\tvsub.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t748 <__gridxc_interpolation_MOD_polint+0x330>\n-\tldr\tr0, [r7, #36]\t@ 0x24\n+\tvsub.f64\td7, d7, d6\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t76c <__gridxc_interpolation_MOD_polint+0x330>\n+\tldr.w\tip, [r7, #36]\t@ 0x24\n \tmov\tr1, r6\n \tldr.w\tfp, [r7, #12]\n \tmov\tsl, r6\n-\tmov\tr2, r0\n+\tmov\tr0, ip\n \tmov\tr9, r8\n \tmovs\tr3, #0\n-\tvldmia\tr0!, {d17}\n+\tvldmia\tip!, {d6}\n \tadds\tr3, #1\n-\tvldmia\tfp!, {d16}\n+\tvldmia\tfp!, {d7}\n \tcmp\tr3, r4\n-\tvldmia\tr9!, {d18}\n-\tvsub.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d18\n-\tvstmia\tsl!, {d17}\n-\tbne.n\t76a <__gridxc_interpolation_MOD_polint+0x352>\n+\tvldmia\tr9!, {d5}\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d7, d5\n+\tvstmia\tsl!, {d6}\n+\tbne.n\t790 <__gridxc_interpolation_MOD_polint+0x354>\n \tldr.w\tsl, [r7, #40]\t@ 0x28\n \tmov\tr9, r6\n-\tldr\tr0, [r7, #56]\t@ 0x38\n+\tldr.w\tip, [r7, #56]\t@ 0x38\n \tmovs\tr3, #0\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tip!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tr9!, {d17}\n+\tvldmia\tr9!, {d6}\n \tcmp\tr3, r4\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tsl!, {d16}\n-\tbne.n\t792 <__gridxc_interpolation_MOD_polint+0x37a>\n-\tldr\tr0, [r7, #52]\t@ 0x34\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tsl!, {d7}\n+\tbne.n\t7ba <__gridxc_interpolation_MOD_polint+0x37e>\n+\tldr.w\tip, [r7, #52]\t@ 0x34\n \tmov\tr9, r6\n \tmovs\tr3, #0\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tip!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tr9!, {d17}\n+\tvldmia\tr9!, {d6}\n \tcmp\tr3, r4\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t7ae <__gridxc_interpolation_MOD_polint+0x396>\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t7d8 <__gridxc_interpolation_MOD_polint+0x39c>\n \tldr.w\tr9, [r7, #28]\n \tmovs\tr3, #0\n \tldr.w\tsl, [r7, #60]\t@ 0x3c\n \tldr.w\tfp, [r7, #8]\n-\tmov\tr0, r9\n-\tmov\tr2, sl\n-\tvldmia\tr9!, {d17}\n+\tmov\tip, r9\n+\tmov\tr0, sl\n+\tvldmia\tr9!, {d6}\n \tadds\tr3, #1\n-\tvldmia\tfp!, {d16}\n+\tvldmia\tfp!, {d7}\n \tcmp\tr3, r4\n-\tvldmia\tr5!, {d18}\n-\tvsub.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d18\n-\tvstmia\tsl!, {d17}\n-\tbne.n\t7d6 <__gridxc_interpolation_MOD_polint+0x3be>\n+\tvldmia\tr5!, {d5}\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d7, d5\n+\tvstmia\tsl!, {d6}\n+\tbne.n\t800 <__gridxc_interpolation_MOD_polint+0x3c4>\n \tldr.w\tsl, [r7, #32]\n \tmov\tr9, r6\n \tldr\tr5, [r7, #60]\t@ 0x3c\n \tmovs\tr3, #0\n-\tvldmia\tlr!, {d18}\n+\tvldmia\tlr!, {d5}\n \tadds\tr3, #1\n-\tvldmia\tr5!, {d17}\n+\tvldmia\tr5!, {d6}\n \tcmp\tr3, r4\n-\tvldmia\tr9!, {d16}\n-\tvfnms.f64\td16, d18, d17\n-\tvstmia\tsl!, {d16}\n-\tbne.n\t7fe <__gridxc_interpolation_MOD_polint+0x3e6>\n+\tvldmia\tr9!, {d7}\n+\tvnmls.f64\td7, d5, d6\n+\tvstmia\tsl!, {d7}\n+\tbne.n\t828 <__gridxc_interpolation_MOD_polint+0x3ec>\n \tmovs\tr3, #0\n-\tvldmia\tip!, {d18}\n+\tvldmia\tr2!, {d5}\n \tadds\tr3, #1\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr0!, {d6}\n \tcmp\tr3, r4\n-\tvldmia\tr1!, {d16}\n-\tvfnms.f64\td16, d18, d17\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t81a <__gridxc_interpolation_MOD_polint+0x402>\n+\tvldmia\tr1!, {d7}\n+\tvnmls.f64\td7, d5, d6\n+\tvstmia\tip!, {d7}\n+\tbne.n\t844 <__gridxc_interpolation_MOD_polint+0x408>\n \tldr\tr1, [r7, #48]\t@ 0x30\n \tldr\tr0, [r7, #44]\t@ 0x2c\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tvldr\td16, [r1]\n-\tvldr\td17, [r0]\n+\tvldr\td7, [r1]\n+\tvldr\td6, [r0]\n \tcmp.w\tr4, r3, lsl #1\n-\tble.n\t89c <__gridxc_interpolation_MOD_polint+0x484>\n+\tble.n\t8c6 <__gridxc_interpolation_MOD_polint+0x48a>\n \tldr\tr2, [r7, #68]\t@ 0x44\n \tlsls\tr3, r3, #3\n \tsubs\tr4, #1\n \tadd.w\tr2, r2, #1\n \tstr\tr2, [r7, #68]\t@ 0x44\n \tldr\tr2, [r7, #40]\t@ 0x28\n \tadd\tr2, r3\n-\tvldr\td19, [r2]\n+\tvldr\td4, [r2]\n \tldr\tr2, [r7, #32]\n \tadd\tr3, r2\n-\tvadd.f64\td16, d16, d19\n-\tvldr\td18, [r3]\n-\tvstr\td16, [r1]\n-\tvadd.f64\td17, d18, d17\n-\tvstr\td17, [r0]\n-\tbne.w\t6d0 <__gridxc_interpolation_MOD_polint+0x2b8>\n-\tldr\tr2, [pc, #156]\t@ (918 <__gridxc_interpolation_MOD_polint+0x500>)\n-\tldr\tr3, [pc, #140]\t@ (908 <__gridxc_interpolation_MOD_polint+0x4f0>)\n+\tvadd.f64\td7, d7, d4\n+\tvldr\td5, [r3]\n+\tvstr\td7, [r1]\n+\tvadd.f64\td6, d5, d6\n+\tvstr\td6, [r0]\n+\tbne.w\t6f4 <__gridxc_interpolation_MOD_polint+0x2b8>\n+\tldr\tr2, [pc, #160]\t@ (944 <__gridxc_interpolation_MOD_polint+0x508>)\n+\tldr\tr3, [pc, #140]\t@ (934 <__gridxc_interpolation_MOD_polint+0x4f8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #76]\t@ 0x4c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t900 <__gridxc_interpolation_MOD_polint+0x4e8>\n+\tbne.n\t92a <__gridxc_interpolation_MOD_polint+0x4ee>\n \tadds\tr7, #84\t@ 0x54\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr3, [r7, #20]\n-\tvldr\td17, [r3]\n-\tb.n\t72a <__gridxc_interpolation_MOD_polint+0x312>\n+\tvldr\td6, [r3]\n+\tb.n\t74e <__gridxc_interpolation_MOD_polint+0x312>\n \tldr\tr3, [r7, #16]\n \tsubs\tr4, #1\n \tldr\tr2, [r7, #68]\t@ 0x44\n \tsub.w\tr3, r3, #2\n \tadd.w\tr2, r2, #1\n \tstr\tr2, [r7, #68]\t@ 0x44\n \tldr\tr2, [r7, #36]\t@ 0x24\n \tmov.w\tr3, r3, lsl #3\n \tadd\tr2, r3\n-\tvldr\td19, [r2]\n+\tvldr\td4, [r2]\n \tldr\tr2, [r7, #28]\n \tadd\tr3, r2\n-\tvadd.f64\td16, d16, d19\n-\tvldr\td18, [r3]\n+\tvadd.f64\td7, d7, d4\n+\tvldr\td5, [r3]\n \tldr\tr3, [r7, #48]\t@ 0x30\n-\tvadd.f64\td17, d18, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td6, d5, d6\n+\tvstr\td7, [r3]\n \tldr\tr3, [r7, #44]\t@ 0x2c\n-\tvstr\td17, [r3]\n-\tbeq.n\t878 <__gridxc_interpolation_MOD_polint+0x460>\n+\tvstr\td6, [r3]\n+\tbeq.n\t8a2 <__gridxc_interpolation_MOD_polint+0x466>\n \tldr\tr3, [r7, #64]\t@ 0x40\n \tstr\tr3, [r7, #16]\n \tsubs\tr3, #1\n \tstr\tr3, [r7, #64]\t@ 0x40\n-\tb.n\t6d0 <__gridxc_interpolation_MOD_polint+0x2b8>\n+\tb.n\t6f4 <__gridxc_interpolation_MOD_polint+0x2b8>\n \tadd.w\tr5, r5, r5, lsr #31\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tmovs\tr1, #0\n \tmovs\tr0, #0\n \tasrs\tr3, r5, #1\n+\tstrd\tr0, r1, [r2]\n \tadd.w\tr9, r9, r3, lsl #3\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tstrd\tr0, r1, [r3]\n \tldr\tr1, [r7, #48]\t@ 0x30\n \tldrd\tr2, r3, [r9, #-8]\n \tstrd\tr2, r3, [r1]\n-\tb.n\t878 <__gridxc_interpolation_MOD_polint+0x460>\n+\tb.n\t8a2 <__gridxc_interpolation_MOD_polint+0x466>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x000004ca\n+\tnop\n+\t.word\t0x000004d2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000004b2\n+\t.word\t0x000004ba\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000250\n+\t.word\t0x00000258\n R_ARM_REL32\t.LC3\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000098\n+\t.word\t0x0000009a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000091c <__gridxc_interpolation_MOD_evaluate_spline_dx>:\n+00000948 <__gridxc_interpolation_MOD_evaluate_spline_dx>:\n __gridxc_interpolation_MOD_evaluate_spline_dx():\n \tpush\t{r3, r4, r5, r6, r7, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n+\tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n-\tvldr\td16, [pc, #312]\t@ a68 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x14c>\n-\tmov\tr7, r1\n+\tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n+\tvldr\td7, [pc, #308]\t@ a90 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x148>\n+\tmov\tr4, r1\n \tvldr\td9, [r0]\n-\tmov\tr5, r2\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tldr\tr4, [r3, #0]\n-\tvmul.f64\td16, d9, d16\n-\tldr\tr3, [pc, #308]\t@ (a78 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x15c>)\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tsubs\tr4, #1\n+\tmov\tr6, r2\n+\tldr\tr0, [sp, #80]\t@ 0x50\n+\tldr\tr7, [r3, #0]\n+\tvmul.f64\td7, d9, d7\n+\tldr\tr3, [pc, #304]\t@ (aa0 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x158>)\n+\tldr\tr5, [sp, #88]\t@ 0x58\n+\tsubs\tr7, #1\n \tvldr\td8, [r0]\n \tadd\tr3, pc\n-\tvneg.f64\td17, d16\n-\tvcmpe.f64\td8, d17\n+\tvneg.f64\td6, d7\n+\tvcmpe.f64\td8, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\ta54 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x138>\n-\tvmov\ts15, r4\n-\tvcvt.f64.s32\td17, s15\n-\tvfma.f64\td16, d17, d9\n-\tvcmpe.f64\td8, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\ta54 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x138>\n-\tvdiv.f64\td16, d8, d9\n-\tvldr\td19, [pc, #248]\t@ a70 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x154>\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td17, d16\n-\tvmov\tr3, s15\n+\tbmi.n\ta80 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x138>\n+\tvmov\ts13, r7\n+\tvcvt.f64.s32\td6, s13\n+\tvmla.f64\td7, d6, d9\n+\tvcmpe.f64\td8, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbgt.n\ta80 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x138>\n+\tvdiv.f64\td7, d8, d9\n+\tvldr\td11, [pc, #244]\t@ a98 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x150>\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr3, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tls\n \taddls\tr3, #1\n \tcmp\tr3, #1\n \tit\tlt\n \tmovlt\tr3, #1\n-\tcmp\tr3, r4\n+\tcmp\tr3, r7\n \tit\tge\n-\tmovge\tr3, r4\n+\tmovge\tr3, r7\n \tvmov\ts15, r3\n \tsubs\tr2, r3, #1\n-\tvcvt.f64.s32\td23, s15\n-\tvmov\ts15, r2\n+\tvmov\ts14, r2\n+\tvcvt.f64.s32\td4, s15\n \tlsls\tr3, r3, #3\n-\tvcvt.f64.s32\td17, s15\n-\tadds\tr2, r5, r3\n-\tadds\tr1, r7, r3\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tvmul.f64\td23, d23, d9\n-\tvldr\td24, [r2]\n-\tvmul.f64\td17, d17, d9\n-\tvldr\td27, [r1]\n-\tvldr\td22, [r2, #-8]\n-\tvsub.f64\td26, d23, d8\n-\tvldr\td25, [r1, #-8]\n-\tvsub.f64\td18, d23, d17\n-\tvsub.f64\td8, d8, d17\n-\tvdiv.f64\td16, d8, d18\n-\tvdiv.f64\td21, d26, d18\n-\tvmul.f64\td18, d18, d18\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td28, d16, d16\n-\tvmul.f64\td19, d24, d16\n-\tvmul.f64\td26, d21, d21\n-\tvmul.f64\td16, d27, d16\n-\tvfma.f64\td16, d25, d21\n-\tvmul.f64\td29, d22, d21\n-\tvsub.f64\td30, d28, d20\n-\tvsub.f64\td21, d26, d20\n-\tvmul.f64\td19, d19, d30\n-\tvfma.f64\td19, d29, d21\n-\tvfma.f64\td16, d18, d19\n-\tvstr\td16, [r3]\n-\tcbz\tr6, a4e <__gridxc_interpolation_MOD_evaluate_spline_dx+0x132>\n-\tvmov.f64\td29, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td21, #240\t@ 0xbf800000 -1.0\n-\tvsub.f64\td19, d25, d27\n-\tvsub.f64\td17, d17, d23\n-\tvfms.f64\td20, d28, d29\n-\tvfma.f64\td21, d26, d29\n-\tvmul.f64\td16, d20, d24\n-\tvfma.f64\td16, d22, d21\n-\tvfma.f64\td19, d18, d16\n-\tvdiv.f64\td16, d19, d17\n-\tvstr\td16, [r6]\n-\tvpop\t{d8-d9}\n+\tvcvt.f64.s32\td7, s14\n+\tadds\tr2, r6, r3\n+\tadds\tr1, r4, r3\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tvmul.f64\td4, d4, d9\n+\tvldr\td0, [r2]\n+\tvmul.f64\td7, d7, d9\n+\tvldr\td10, [r1]\n+\tvldr\td1, [r2, #-8]\n+\tvldr\td3, [r1, #-8]\n+\tvsub.f64\td5, d4, d8\n+\tvsub.f64\td9, d4, d7\n+\tvsub.f64\td8, d8, d7\n+\tvdiv.f64\td14, d8, d9\n+\tvdiv.f64\td13, d5, d9\n+\tvmul.f64\td9, d9, d9\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td11, d9, d11\n+\tvmul.f64\td9, d14, d14\n+\tvmul.f64\td12, d0, d14\n+\tvmul.f64\td8, d13, d13\n+\tvmul.f64\td14, d10, d14\n+\tvmla.f64\td14, d3, d13\n+\tvmul.f64\td13, d1, d13\n+\tvsub.f64\td6, d9, d5\n+\tvsub.f64\td2, d8, d5\n+\tvmul.f64\td6, d12, d6\n+\tvmla.f64\td6, d13, d2\n+\tvmla.f64\td14, d6, d11\n+\tvstr\td14, [r3]\n+\tcbz\tr5, a7a <__gridxc_interpolation_MOD_evaluate_spline_dx+0x132>\n+\tvsub.f64\td7, d7, d4\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tvmov.f64\td6, d5\n+\tvsub.f64\td3, d3, d10\n+\tvmls.f64\td6, d9, d4\n+\tvnmls.f64\td5, d8, d4\n+\tvmul.f64\td6, d6, d0\n+\tvmla.f64\td6, d5, d1\n+\tvmla.f64\td3, d6, d11\n+\tvdiv.f64\td6, d3, d7\n+\tvstr\td6, [r5]\n+\tvpop\t{d8-d14}\n \tpop\t{r3, r4, r5, r6, r7, pc}\n-\tldr\tr2, [pc, #36]\t@ (a7c <__gridxc_interpolation_MOD_evaluate_spline_dx+0x160>)\n+\tldr\tr2, [pc, #32]\t@ (aa4 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x15c>)\n \tmovs\tr1, #37\t@ 0x25\n-\tldr\tr0, [pc, #36]\t@ (a80 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x164>)\n+\tldr\tr0, [pc, #32]\t@ (aa8 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x160>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t972 <__gridxc_interpolation_MOD_evaluate_spline_dx+0x56>\n-\tnop.w\n+\tb.n\t99e <__gridxc_interpolation_MOD_evaluate_spline_dx+0x56>\n \t.word\t0xa0b5ed8d\n \t.word\t0x3eb0c6f7\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x00000128\n+\t.word\t0x00000124\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000022\n+\t.word\t0x0000001e\n R_ARM_REL32\t.LC4\n \n-00000a84 <__gridxc_interpolation_MOD_evaluate_spline_x>:\n+00000aac <__gridxc_interpolation_MOD_evaluate_spline_x>:\n __gridxc_interpolation_MOD_evaluate_spline_x():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d12}\n+\tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3848]\t@ 0xf08\n+\tstr.w\tr0, [ip, #3832]\t@ 0xef8\n \tldr\tr4, [r3, #0]\n-\tmov\tsl, r0\n-\tvldr\td18, [pc, #712]\t@ d68 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2e4>\n+\tmov\tr9, r0\n+\tvldr\td4, [pc, #736]\t@ da8 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2fc>\n \tsub\tsp, #176\t@ 0xb0\n \tsubs\tr3, r4, #1\n \tvmov\ts15, r3\n-\tvldr\td11, [sl]\n-\tmov\tr7, r2\n-\tadd.w\tr3, sl, r3, lsl #3\n-\tvcvt.f64.s32\td19, s15\n-\tldr\tr0, [sp, #248]\t@ 0xf8\n-\tmov\tr6, r1\n-\tldr\tr2, [pc, #700]\t@ (d78 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2f4>)\n+\tvldr\td12, [r9]\n+\tmov\tr6, r2\n+\tadd.w\tr3, r9, r3, lsl #3\n+\tvcvt.f64.s32\td6, s15\n+\tldr\tr0, [sp, #264]\t@ 0x108\n+\tmov\tr5, r1\n+\tldr\tr2, [pc, #724]\t@ (db8 <__gridxc_interpolation_MOD_evaluate_spline_x+0x30c>)\n \tbic.w\tr4, r4, r4, asr #31\n-\tvldr\td16, [r3]\n-\tldr\tr3, [pc, #692]\t@ (d7c <__gridxc_interpolation_MOD_evaluate_spline_x+0x2f8>)\n+\tvldr\td7, [r3]\n+\tldr\tr3, [pc, #716]\t@ (dbc <__gridxc_interpolation_MOD_evaluate_spline_x+0x310>)\n \tadd\tr2, pc\n \tvldr\td10, [r0]\n-\tvsub.f64\td20, d16, d11\n-\tvmaxnm.f64\td17, d11, d16\n-\tvminnm.f64\td16, d11, d16\n-\tvstr\td11, [sp, #24]\n+\tvsub.f64\td5, d7, d12\n+\tvcmpe.f64\td12, d7\n+\tvstr\td12, [sp, #24]\n \tldr\tr3, [r2, r3]\n-\tmovs\tr2, #1\n-\tldr\tr5, [pc, #668]\t@ (d80 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2fc>)\n-\tvdiv.f64\td12, d20, d19\n+\tldr.w\tsl, [pc, #700]\t@ dc0 <__gridxc_interpolation_MOD_evaluate_spline_x+0x314>\n+\tvdiv.f64\td11, d5, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #172]\t@ 0xac\n \tmov.w\tr3, #0\n-\tldr\tr3, [pc, #660]\t@ (d84 <__gridxc_interpolation_MOD_evaluate_spline_x+0x300>)\n-\tadd\tr5, pc\n-\tldrd\tr9, r8, [sp, #252]\t@ 0xfc\n+\tldr\tr3, [pc, #684]\t@ (dc4 <__gridxc_interpolation_MOD_evaluate_spline_x+0x318>)\n+\tadd\tsl, pc\n \tadd\tr3, pc\n+\tldrd\tr8, r7, [sp, #268]\t@ 0x10c\n+\tite\tlt\n+\tvmovlt.f64\td6, d7\n+\tvmovge.f64\td6, d12\n+\tit\tls\n+\tvmovls.f64\td7, d12\n \tldr\tr3, [r3, #0]\n \tstrh.w\tr3, [sp]\n \tlsrs\tr3, r3, #16\n \tstrb.w\tr3, [sp, #2]\n \tmovs\tr3, #0\n \tstr\tr3, [sp, #60]\t@ 0x3c\n \tstr\tr3, [sp, #96]\t@ 0x60\n \tstr\tr3, [sp, #132]\t@ 0x84\n-\tvabs.f64\td19, d12\n-\tvstr\td12, [sp, #32]\n-\tvfma.f64\td17, d19, d18\n-\tvfms.f64\td16, d19, d18\n-\tvcmpe.f64\td17, d10\n-\tvstr\td16, [sp, #8]\n-\tvstr\td17, [sp, #16]\n+\tvabs.f64\td5, d11\n+\tvstr\td11, [sp, #32]\n+\tvmul.f64\td5, d5, d4\n+\tvadd.f64\td6, d6, d5\n+\tvsub.f64\td7, d7, d5\n+\tvcmpe.f64\td6, d10\n+\tvstr\td7, [sp, #8]\n+\tvstr\td6, [sp, #16]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvcmpe.f64\td16, d10\n-\tit\tpl\n-\tmovpl\tr2, r3\n+\tvcmpe.f64\td7, d10\n+\tit\tmi\n+\tmovmi\tr3, #1\n \tvmrs\tAPSR_nzcv, fpscr\n-\torr.w\tr3, r2, #1\n-\tit\tle\n-\tmovle\tr3, r2\n-\tcbz\tr3, b50 <__gridxc_interpolation_MOD_evaluate_spline_x+0xcc>\n-\tldr\tr3, [pc, #580]\t@ (d88 <__gridxc_interpolation_MOD_evaluate_spline_x+0x304>)\n+\tit\tgt\n+\torrgt.w\tr3, r3, #1\n+\tcbz\tr3, b8c <__gridxc_interpolation_MOD_evaluate_spline_x+0xe0>\n+\tldr\tr3, [pc, #584]\t@ (dc8 <__gridxc_interpolation_MOD_evaluate_spline_x+0x31c>)\n \tmovs\tr1, #51\t@ 0x33\n-\tldr\tr0, [pc, #580]\t@ (d8c <__gridxc_interpolation_MOD_evaluate_spline_x+0x308>)\n+\tldr\tr0, [pc, #584]\t@ (dcc <__gridxc_interpolation_MOD_evaluate_spline_x+0x320>)\n \tadd\tr0, pc\n-\tldr\tr3, [r5, r3]\n+\tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr0, [pc, #572]\t@ (d90 <__gridxc_interpolation_MOD_evaluate_spline_x+0x30c>)\n+\tldr\tr0, [pc, #576]\t@ (dd0 <__gridxc_interpolation_MOD_evaluate_spline_x+0x324>)\n \tmovs\tr3, #3\n \tmov\tr2, sp\n \tmovs\tr1, #4\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_select_string>\n R_ARM_THM_CALL\t_gfortran_select_string\n \tcmp\tr0, #2\n-\tbeq.w\td0e <__gridxc_interpolation_MOD_evaluate_spline_x+0x28a>\n+\tbeq.w\td4c <__gridxc_interpolation_MOD_evaluate_spline_x+0x2a0>\n \tcmp\tr0, #3\n-\tbeq.n\tc44 <__gridxc_interpolation_MOD_evaluate_spline_x+0x1c0>\n+\tbeq.n\tc7e <__gridxc_interpolation_MOD_evaluate_spline_x+0x1d2>\n \tcmp\tr0, #1\n-\tbeq.w\tccc <__gridxc_interpolation_MOD_evaluate_spline_x+0x248>\n-\tldr\tr3, [pc, #536]\t@ (d88 <__gridxc_interpolation_MOD_evaluate_spline_x+0x304>)\n-\tmvn.w\tr4, #7\n-\tldr\tr0, [pc, #540]\t@ (d94 <__gridxc_interpolation_MOD_evaluate_spline_x+0x310>)\n+\tbeq.w\td0a <__gridxc_interpolation_MOD_evaluate_spline_x+0x25e>\n+\tldr\tr3, [pc, #540]\t@ (dc8 <__gridxc_interpolation_MOD_evaluate_spline_x+0x31c>)\n \tmovs\tr1, #54\t@ 0x36\n+\tldr\tr0, [pc, #548]\t@ (dd4 <__gridxc_interpolation_MOD_evaluate_spline_x+0x328>)\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n \tadd\tr0, pc\n-\tldr\tr3, [r5, r3]\n-\tmov.w\tr5, #4294967295\t@ 0xffffffff\n+\tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvsub.f64\td17, d9, d8\n-\tvsub.f64\td19, d10, d8\n+\tmvn.w\tr3, #7\n+\tvsub.f64\td6, d9, d8\n+\tvsub.f64\td7, d10, d8\n \tvsub.f64\td10, d9, d10\n-\tadds\tr3, r7, r4\n-\tlsls\tr0, r5, #3\n-\tadd\tr4, r6\n-\tvldr\td18, [pc, #472]\t@ d70 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2ec>\n-\tadd\tr7, r0\n-\tvdiv.f64\td16, d19, d17\n-\tvmul.f64\td22, d17, d17\n-\tvdiv.f64\td21, d10, d17\n+\tadds\tr2, r6, r3\n+\tlsls\tr0, r4, #3\n+\tadd\tr3, r5\n+\tvldr\td11, [pc, #472]\t@ db0 <__gridxc_interpolation_MOD_evaluate_spline_x+0x304>\n \tadd\tr6, r0\n-\tvldr\td19, [r3]\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvldr\td26, [r4]\n-\tvmul.f64\td22, d22, d18\n-\tvldr\td23, [r7]\n-\tvldr\td18, [r6]\n-\tvmul.f64\td25, d16, d16\n-\tvmul.f64\td17, d19, d16\n-\tvmul.f64\td24, d21, d21\n-\tvmul.f64\td16, d26, d16\n-\tvfma.f64\td16, d18, d21\n-\tvmul.f64\td27, d23, d21\n-\tvsub.f64\td28, d25, d20\n-\tvsub.f64\td21, d24, d20\n-\tvmul.f64\td17, d17, d28\n-\tvfma.f64\td17, d27, d21\n-\tvfma.f64\td16, d22, d17\n-\tvstr\td16, [r9]\n-\tcmp.w\tr8, #0\n-\tbeq.n\tc24 <__gridxc_interpolation_MOD_evaluate_spline_x+0x1a0>\n-\tvmov.f64\td17, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td16, #240\t@ 0xbf800000 -1.0\n-\tvsub.f64\td18, d18, d26\n+\tvdiv.f64\td14, d7, d6\n+\tvmul.f64\td3, d6, d6\n+\tvdiv.f64\td13, d10, d6\n+\tadd\tr5, r0\n+\tvldr\td10, [r3]\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td2, [r6]\n+\tvmul.f64\td11, d3, d11\n+\tvldr\td3, [r2]\n+\tvldr\td5, [r5]\n+\tvmul.f64\td1, d14, d14\n+\tvmul.f64\td12, d3, d14\n+\tvmul.f64\td0, d13, d13\n+\tvmul.f64\td14, d10, d14\n+\tvmla.f64\td14, d5, d13\n+\tvmul.f64\td13, d2, d13\n+\tvsub.f64\td7, d1, d6\n+\tvsub.f64\td4, d0, d6\n+\tvmul.f64\td7, d12, d7\n+\tvmla.f64\td7, d13, d4\n+\tvmla.f64\td14, d7, d11\n+\tvstr\td14, [r8]\n+\tcbz\tr7, c5e <__gridxc_interpolation_MOD_evaluate_spline_x+0x1b2>\n+\tvmov.f64\td7, d6\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tvsub.f64\td5, d5, d10\n \tvsub.f64\td8, d8, d9\n-\tvfms.f64\td20, d25, d17\n-\tvfma.f64\td16, d24, d17\n-\tvmul.f64\td19, d19, d20\n-\tvfma.f64\td19, d23, d16\n-\tvfma.f64\td18, d19, d22\n-\tvdiv.f64\td16, d18, d8\n-\tvstr\td16, [r8]\n-\tldr\tr2, [pc, #368]\t@ (d98 <__gridxc_interpolation_MOD_evaluate_spline_x+0x314>)\n-\tldr\tr3, [pc, #340]\t@ (d7c <__gridxc_interpolation_MOD_evaluate_spline_x+0x2f8>)\n+\tvmls.f64\td6, d1, d4\n+\tvnmls.f64\td7, d0, d4\n+\tvmul.f64\td7, d7, d2\n+\tvmla.f64\td7, d6, d3\n+\tvmla.f64\td5, d7, d11\n+\tvdiv.f64\td7, d5, d8\n+\tvstr\td7, [r7]\n+\tldr\tr2, [pc, #376]\t@ (dd8 <__gridxc_interpolation_MOD_evaluate_spline_x+0x32c>)\n+\tldr\tr3, [pc, #344]\t@ (dbc <__gridxc_interpolation_MOD_evaluate_spline_x+0x310>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #172]\t@ 0xac\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\td62 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2de>\n+\tbne.w\tda0 <__gridxc_interpolation_MOD_evaluate_spline_x+0x2f4>\n \tadd\tsp, #176\t@ 0xb0\n-\tvpop\t{d8-d12}\n+\tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tvsub.f64\td16, d10, d11\n-\tvldr\td12, [sp, #48]\t@ 0x30\n+\tvsub.f64\td7, d10, d12\n+\tvldr\td11, [sp, #48]\t@ 0x30\n \tvldr\td8, [sp, #40]\t@ 0x28\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n \tsubs\tr4, #1\n \tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td0, d16, d12\n-\tvadd.f64\td0, d0, d17\n+\tvdiv.f64\td0, d7, d11\n+\tvadd.f64\td0, d0, d6\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d0, d8\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr3, s15\n+\tvdiv.f64\td7, d0, d8\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr3, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n \taddge\tr3, #1\n \tcmp\tr3, #1\n \tit\tlt\n \tmovlt\tr3, #1\n-\tcmp\tr4, r3\n+\tcmp\tr3, r4\n \tit\tge\n-\tmovge\tr4, r3\n-\tsubs\tr5, r4, #1\n-\tvmov\ts15, r5\n+\tmovge\tr3, r4\n+\tsubs\tr4, r3, #1\n+\tvmov\ts15, r4\n+\tmov\tsl, r3\n \tvcvt.f64.s32\td0, s15\n \tvmul.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov\ts15, r4\n-\tvsub.f64\td16, d0, d9\n-\tlsls\tr4, r4, #3\n-\tvcvt.f64.s32\td17, s15\n-\tvmul.f64\td0, d17, d8\n-\tvmov.f64\td8, d11\n-\tvfma.f64\td8, d12, d16\n+\tvmov\ts15, sl\n+\tvcvt.f64.s32\td6, s15\n+\tvsub.f64\td7, d0, d9\n+\tvmul.f64\td0, d6, d8\n+\tvmov.f64\td8, d12\n+\tvmla.f64\td8, d7, d11\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvsub.f64\td0, d0, d9\n-\tvmov.f64\td9, d11\n-\tvfma.f64\td9, d12, d0\n-\tb.n\tb84 <__gridxc_interpolation_MOD_evaluate_spline_x+0x100>\n-\tvmov.f64\td8, d11\n-\tsubs\tr3, r4, r0\n-\tcmp\tr3, #1\n-\tble.n\td00 <__gridxc_interpolation_MOD_evaluate_spline_x+0x27c>\n+\tvmov.f64\td9, d12\n+\tmov.w\tr3, sl, lsl #3\n+\tvmla.f64\td9, d0, d11\n+\tb.n\tbc2 <__gridxc_interpolation_MOD_evaluate_spline_x+0x116>\n+\tvmov.f64\td8, d12\n+\tb.n\td34 <__gridxc_interpolation_MOD_evaluate_spline_x+0x288>\n \tadds\tr3, r0, r4\n \tadd.w\tr3, r3, r3, lsr #31\n \tasrs\tr3, r3, #1\n-\tadd.w\tr2, sl, r3, lsl #3\n-\tvldr\td16, [r2, #-8]\n-\tvcmpe.f64\td10, d16\n+\tadd.w\tr2, r9, r3, lsl #3\n+\tvldr\td7, [r2, #-8]\n+\tvcmpe.f64\td10, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tit\tmi\n+\tit\tpl\n+\tvmovpl.f64\td8, d7\n+\tite\tpl\n+\tmovpl\tr0, r3\n \tmovmi\tr4, r3\n-\tbmi.n\tcd0 <__gridxc_interpolation_MOD_evaluate_spline_x+0x24c>\n-\tmov\tr0, r3\n-\tvmov.f64\td8, d16\n \tsubs\tr3, r4, r0\n \tcmp\tr3, #1\n-\tbgt.n\tcd6 <__gridxc_interpolation_MOD_evaluate_spline_x+0x252>\n-\tsubs\tr4, #1\n-\tsubs\tr5, r0, #1\n-\tlsls\tr4, r4, #3\n-\tadd\tsl, r4\n-\tvldr\td9, [sl]\n-\tb.n\tb84 <__gridxc_interpolation_MOD_evaluate_spline_x+0x100>\n-\tvsub.f64\td17, d10, d11\n+\tbgt.n\td10 <__gridxc_interpolation_MOD_evaluate_spline_x+0x264>\n+\tadd.w\tsl, r4, #4294967295\t@ 0xffffffff\n+\tsubs\tr4, r0, #1\n+\tmov.w\tr3, sl, lsl #3\n+\tadd\tr9, r3\n+\tvldr\td9, [r9]\n+\tb.n\tbc2 <__gridxc_interpolation_MOD_evaluate_spline_x+0x116>\n+\tvsub.f64\td6, d10, d12\n \tsubs\tr4, #1\n-\tvmov.f64\td9, d11\n-\tvmov.f64\td8, d11\n-\tvdiv.f64\td16, d17, d12\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr3, s15\n+\tvmov.f64\td9, d12\n+\tvmov.f64\td8, d12\n+\tvdiv.f64\td7, d6, d11\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr3, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n \taddge\tr3, #1\n \tcmp\tr3, #1\n \tit\tlt\n \tmovlt\tr3, #1\n-\tcmp\tr4, r3\n+\tcmp\tr3, r4\n \tit\tge\n-\tmovge\tr4, r3\n+\tmovge\tr3, r4\n+\tvmov\ts15, r3\n+\tsubs\tr4, r3, #1\n+\tvcvt.f64.s32\td7, s15\n+\tlsls\tr3, r3, #3\n+\tvmla.f64\td9, d7, d11\n \tvmov\ts15, r4\n-\tsubs\tr5, r4, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r5\n-\tlsls\tr4, r4, #3\n-\tvfma.f64\td9, d12, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvfma.f64\td8, d12, d16\n-\tb.n\tb84 <__gridxc_interpolation_MOD_evaluate_spline_x+0x100>\n+\tvcvt.f64.s32\td7, s15\n+\tvmla.f64\td8, d7, d11\n+\tb.n\tbc2 <__gridxc_interpolation_MOD_evaluate_spline_x+0x116>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\tnop.w\n \t.word\t0xa0b5ed8d\n \t.word\t0x3eb0c6f7\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x000002ae\n+\t.word\t0x000002c6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000028c\n+\t.word\t0x000002a4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000028a\n+\t.word\t0x000002a6\n R_ARM_REL32\t.LC5\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000240\n+\t.word\t0x00000246\n R_ARM_REL32\t.LC6\n-\t.word\t0x00000234\n+\t.word\t0x00000238\n R_ARM_REL32\t.data.rel.ro.local\n-\t.word\t0x00000218\n+\t.word\t0x0000021c\n R_ARM_REL32\t.LC7\n-\t.word\t0x0000016c\n+\t.word\t0x00000172\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00000d9c <__gridxc_interpolation_MOD_evaluate_spline_n>:\n+00000ddc <__gridxc_interpolation_MOD_evaluate_spline_n>:\n __gridxc_interpolation_MOD_evaluate_spline_n():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d13}\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3968]\t@ 0xf80\n-\tldr.w\tr9, [r1, #24]\n-\tmov\tr7, r3\n+\tstr.w\tr0, [ip, #3952]\t@ 0xf70\n+\tldr.w\tsl, [r1, #24]\n \tmov\tfp, r0\n-\tmovs\tr3, #1\n \tldrd\tr0, r6, [r1, #28]\n-\tcmp.w\tr9, #0\n+\tcmp.w\tsl, #0\n+\tldr.w\tr9, [r2, #24]\n \tit\teq\n-\tmoveq\tr9, r3\n-\tldr\tr3, [r2, #24]\n-\tldr.w\tip, [pc, #820]\t@ 1100 <__gridxc_interpolation_MOD_evaluate_spline_n+0x364>\n+\tmoveq.w\tsl, #1\n+\tldr.w\tip, [pc, #804]\t@ 1130 <__gridxc_interpolation_MOD_evaluate_spline_n+0x354>\n \tsubs\tr0, r6, r0\n-\tcmp\tr3, #0\n+\tcmp.w\tr9, #0\n \tldr\tr6, [r1, #0]\n \tadd\tip, pc\n \tldr\tr2, [r2, #0]\n \tsub\tsp, #44\t@ 0x2c\n \tit\teq\n-\tmoveq\tr3, #1\n-\tadd.w\tsl, r0, #1\n-\tmov\tr1, r7\n-\tcbz\tr7, df6 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5a>\n-\tldr\tr7, [r7, #0]\n-\tcbz\tr7, df6 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5a>\n-\tldr\tr4, [r1, #24]\n+\tmoveq.w\tr9, #1\n+\tadds\tr1, r0, #1\n+\tmov\tr7, r3\n+\tcbz\tr3, e38 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5c>\n+\tldr\tr7, [r3, #0]\n+\tcbz\tr7, e38 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5c>\n+\tldr\tr4, [r3, #24]\n \trsb\tlr, r4, #0\n-\tcbnz\tr4, df6 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5a>\n+\tcbnz\tr4, e38 <__gridxc_interpolation_MOD_evaluate_spline_n+0x5c>\n \tmov.w\tlr, #4294967295\t@ 0xffffffff\n \tmovs\tr4, #1\n-\tbic.w\tr1, sl, sl, asr #31\n+\tbic.w\tr3, r1, r1, asr #31\n \tcmp\tr0, #0\n-\tstr\tr1, [sp, #4]\n-\tblt.w\t10ec <__gridxc_interpolation_MOD_evaluate_spline_n+0x350>\n-\tmov.w\tr1, r9, lsl #3\n-\tlsls\tr3, r3, #3\n-\tstr\tr1, [sp, #12]\n-\tmov\tr8, r2\n-\tstr\tr3, [sp, #16]\n-\tlsls\tr3, r4, #3\n+\tstr\tr3, [sp, #4]\n+\tblt.w\t10ee <__gridxc_interpolation_MOD_evaluate_spline_n+0x312>\n+\tmov.w\tr3, sl, lsl #3\n \tstr\tr3, [sp, #8]\n-\tadd\tlr, r4\n+\tmov.w\tr3, r9, lsl #3\n+\tstr\tr3, [sp, #12]\n+\tlsls\tr3, r4, #3\n+\tstr\tr3, [sp, #16]\n \tldrd\tr1, r3, [fp, #88]\t@ 0x58\n-\tadd.w\tr7, r7, lr, lsl #3\n+\tmov\tr8, r2\n+\tadd\tlr, r4\n \tldr.w\tsl, [fp, #60]\t@ 0x3c\n-\tmov.w\tr9, #1\n \tsubs\tr3, r3, r1\n-\tvldr\td11, [fp, #8]\n+\tvldr\td15, [fp, #8]\n \tadds\tr2, r3, #1\n \tldr.w\tr3, [fp, #84]\t@ 0x54\n-\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n-\tstr.w\tip, [sp, #24]\n+\tadd.w\tr7, r7, lr, lsl #3\n+\tmov.w\tr9, #1\n \tcmp\tr3, #0\n \tbic.w\tr2, r2, r2, asr #31\n \tit\teq\n \tmoveq\tr3, #1\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [pc, #700]\t@ (1104 <__gridxc_interpolation_MOD_evaluate_spline_n+0x368>)\n-\tstr\tr2, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [pc, #688]\t@ (1134 <__gridxc_interpolation_MOD_evaluate_spline_n+0x358>)\n+\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n+\tstr\tr2, [sp, #32]\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #32]\n-\tldr\tr3, [pc, #696]\t@ (1108 <__gridxc_interpolation_MOD_evaluate_spline_n+0x36c>)\n+\tstr\tr3, [sp, #28]\n+\tldr\tr3, [pc, #680]\t@ (1138 <__gridxc_interpolation_MOD_evaluate_spline_n+0x35c>)\n+\tstr.w\tip, [sp, #24]\n \tadd\tr3, pc\n \tstr\tr3, [sp, #20]\n-\tb.n\tf3e <__gridxc_interpolation_MOD_evaluate_spline_n+0x1a2>\n+\tb.n\tf82 <__gridxc_interpolation_MOD_evaluate_spline_n+0x1a6>\n \tcmp\tr0, #1\n-\tbeq.w\t1004 <__gridxc_interpolation_MOD_evaluate_spline_n+0x268>\n-\tldr\tr3, [pc, #688]\t@ (110c <__gridxc_interpolation_MOD_evaluate_spline_n+0x370>)\n+\tbeq.w\t1046 <__gridxc_interpolation_MOD_evaluate_spline_n+0x26a>\n+\tldr\tr3, [pc, #668]\t@ (113c <__gridxc_interpolation_MOD_evaluate_spline_n+0x360>)\n \tmovs\tr1, #54\t@ 0x36\n \tldr\tr2, [sp, #24]\n-\tldr\tr0, [pc, #684]\t@ (1110 <__gridxc_interpolation_MOD_evaluate_spline_n+0x374>)\n+\tldr\tr0, [pc, #664]\t@ (1140 <__gridxc_interpolation_MOD_evaluate_spline_n+0x364>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvldr\td18, [r6]\n-\tvsub.f64\td17, d9, d8\n+\tvldr\td4, [r6]\n+\tvsub.f64\td6, d9, d8\n \tldrd\tr1, r0, [fp, #132]\t@ 0x84\n-\tvsub.f64\td20, d18, d8\n-\tvsub.f64\td18, d9, d18\n+\tvsub.f64\td5, d4, d8\n+\tvsub.f64\td4, d9, d4\n \tadd.w\tip, r0, r5\n \tadd\tr0, r4\n \tldr.w\tr3, [fp, #100]\t@ 0x64\n-\tvmul.f64\td21, d17, d17\n+\tvmul.f64\td2, d6, d6\n \tadd.w\tip, r1, ip, lsl #3\n \tadd.w\tr1, r1, r0, lsl #3\n-\tvdiv.f64\td16, d20, d17\n+\tvdiv.f64\td7, d5, d6\n \tadd\tr4, r3\n-\tvdiv.f64\td20, d18, d17\n+\tvdiv.f64\td5, d4, d6\n \tadd\tr3, r5\n-\tvldr\td22, [r1]\n+\tvldr\td11, [r1]\n \tldr.w\tr1, [fp, #96]\t@ 0x60\n-\tvldr\td19, [pc, #588]\t@ 10f8 <__gridxc_interpolation_MOD_evaluate_spline_n+0x35c>\n+\tvldr\td12, [ip]\n+\tvldr\td13, [pc, #564]\t@ 1128 <__gridxc_interpolation_MOD_evaluate_spline_n+0x34c>\n \tadd.w\tr3, r1, r3, lsl #3\n \tadd.w\tr1, r1, r4, lsl #3\n-\tvmul.f64\td21, d21, d19\n-\tvldr\td19, [ip]\n-\tvldr\td25, [r3]\n-\tvldr\td18, [r1]\n-\tvmul.f64\td24, d16, d16\n-\tvmul.f64\td27, d19, d16\n-\tvmul.f64\td23, d20, d20\n-\tvmul.f64\td16, d25, d16\n-\tvfma.f64\td16, d18, d20\n-\tvmul.f64\td26, d22, d20\n-\tvsub.f64\td17, d24, d10\n-\tvsub.f64\td20, d23, d10\n-\tvmul.f64\td17, d17, d27\n-\tvfma.f64\td17, d20, d26\n-\tvfma.f64\td16, d17, d21\n-\tvstr\td16, [r8]\n-\tcbz\tr7, f26 <__gridxc_interpolation_MOD_evaluate_spline_n+0x18a>\n-\tvmov.f64\td20, #8\t@ 0x40400000 3.0\n-\tvsub.f64\td18, d18, d25\n-\tvmov.f64\td25, d10\n-\tvmov.f64\td17, #240\t@ 0xbf800000 -1.0\n-\tvfms.f64\td25, d24, d20\n-\tvfma.f64\td17, d23, d20\n-\tvsub.f64\td16, d8, d9\n-\tvmul.f64\td19, d19, d25\n-\tvfma.f64\td19, d22, d17\n-\tvfma.f64\td18, d19, d21\n-\tvdiv.f64\td17, d18, d16\n-\tvstr\td17, [r7]\n-\tldr\tr3, [sp, #12]\n+\tvmul.f64\td13, d2, d13\n+\tvldr\td6, [r3]\n+\tvldr\td2, [r1]\n+\tvmul.f64\td4, d7, d7\n+\tvmul.f64\td1, d12, d7\n+\tvmul.f64\td3, d5, d5\n+\tvmul.f64\td14, d11, d5\n+\tvsub.f64\td0, d4, d10\n+\tvmul.f64\td1, d0, d1\n+\tvmul.f64\td0, d6, d7\n+\tvsub.f64\td7, d3, d10\n+\tvmla.f64\td0, d2, d5\n+\tvmla.f64\td1, d7, d14\n+\tvmla.f64\td0, d1, d13\n+\tvstr\td0, [r8]\n+\tcbz\tr7, f6a <__gridxc_interpolation_MOD_evaluate_spline_n+0x18e>\n+\tvmov.f64\td5, d10\n+\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n+\tvsub.f64\td6, d2, d6\n+\tvsub.f64\td2, d8, d9\n+\tvnmls.f64\td5, d3, d7\n+\tvmov.f64\td3, d10\n+\tvmls.f64\td3, d4, d7\n+\tvmul.f64\td5, d5, d11\n+\tvmla.f64\td5, d3, d12\n+\tvmla.f64\td6, d5, d13\n+\tvdiv.f64\td7, d6, d2\n+\tvstr\td7, [r7]\n+\tldr\tr3, [sp, #8]\n \tadd.w\tr9, r9, #1\n \tadd\tr6, r3\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #12]\n \tadd\tr8, r3\n-\tldr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #16]\n \tadd\tr7, r3\n \tldr\tr3, [sp, #4]\n \tcmp\tr3, r9\n-\tblt.w\t10ec <__gridxc_interpolation_MOD_evaluate_spline_n+0x350>\n-\tvldr\td13, [r6]\n-\tvcmpe.f64\td13, d11\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\tf5a <__gridxc_interpolation_MOD_evaluate_spline_n+0x1be>\n-\tvldr\td16, [fp, #16]\n-\tvcmpe.f64\td13, d16\n+\tblt.w\t10ee <__gridxc_interpolation_MOD_evaluate_spline_n+0x312>\n+\tvldr\td12, [r6]\n+\tvcmpe.f64\td12, d15\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.n\tf9e <__gridxc_interpolation_MOD_evaluate_spline_n+0x1c2>\n+\tvldr\td7, [fp, #16]\n+\tvcmpe.f64\td12, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\tf68 <__gridxc_interpolation_MOD_evaluate_spline_n+0x1cc>\n-\tldr\tr3, [pc, #432]\t@ (110c <__gridxc_interpolation_MOD_evaluate_spline_n+0x370>)\n+\tble.n\tfac <__gridxc_interpolation_MOD_evaluate_spline_n+0x1d0>\n+\tldr\tr3, [pc, #412]\t@ (113c <__gridxc_interpolation_MOD_evaluate_spline_n+0x360>)\n \tmovs\tr1, #51\t@ 0x33\n \tldr\tr2, [sp, #24]\n-\tldr\tr0, [sp, #32]\n+\tldr\tr0, [sp, #28]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr0, [sp, #20]\n \tmovs\tr3, #3\n \tmov\tr2, fp\n \tmovs\tr1, #4\n \tbl\t0 <_gfortran_select_string>\n R_ARM_THM_CALL\t_gfortran_select_string\n \tmov\tr4, r0\n \tcmp\tr0, #2\n-\tbeq.w\t1092 <__gridxc_interpolation_MOD_evaluate_spline_n+0x2f6>\n+\tbeq.n\t1094 <__gridxc_interpolation_MOD_evaluate_spline_n+0x2b8>\n \tcmp\tr0, #3\n-\tbne.w\te54 <__gridxc_interpolation_MOD_evaluate_spline_n+0xb8>\n+\tbne.w\te98 <__gridxc_interpolation_MOD_evaluate_spline_n+0xbc>\n \tvldr\td9, [fp, #24]\n-\tvldr\td12, [fp, #48]\t@ 0x30\n+\tvldr\td11, [fp, #48]\t@ 0x30\n \tvldr\td8, [fp, #40]\t@ 0x28\n-\tvsub.f64\td13, d13, d9\n-\tvdiv.f64\td0, d13, d12\n+\tvsub.f64\td12, d12, d9\n+\tvdiv.f64\td0, d12, d11\n \tvadd.f64\td0, d0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tvdiv.f64\td16, d0, d8\n-\tsubs\tr4, r2, #1\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr3, s15\n+\tldr\tr3, [sp, #32]\n+\tvdiv.f64\td7, d0, d8\n+\tsubs\tr3, #1\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr4, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n-\taddge\tr3, #1\n-\tcmp\tr3, #1\n+\taddge\tr4, #1\n+\tcmp\tr4, #1\n \tit\tlt\n-\tmovlt\tr3, #1\n+\tmovlt\tr4, #1\n \tcmp\tr4, r3\n \tit\tge\n \tmovge\tr4, r3\n \tsubs\tr3, r4, #1\n \tvmov\ts0, r3\n \tadds\tr5, r4, #1\n \tvcvt.f64.s32\td0, s0\n \tvmul.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvmov\ts15, r4\n-\tvsub.f64\td16, d0, d10\n-\tvcvt.f64.s32\td17, s15\n-\tvmul.f64\td0, d17, d8\n+\tvcvt.f64.s32\td6, s15\n+\tvsub.f64\td7, d0, d10\n+\tvmul.f64\td0, d6, d8\n \tvmov.f64\td8, d9\n-\tvfma.f64\td8, d12, d16\n+\tvmla.f64\td8, d7, d11\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvsub.f64\td0, d0, d10\n-\tvfma.f64\td9, d12, d0\n-\tb.n\te6a <__gridxc_interpolation_MOD_evaluate_spline_n+0xce>\n-\tldr\tr3, [sp, #28]\n-\tldr\tr5, [sp, #36]\t@ 0x24\n+\tvmla.f64\td9, d0, d11\n+\tb.n\teae <__gridxc_interpolation_MOD_evaluate_spline_n+0xd2>\n+\tldrd\tr5, r3, [sp, #32]\n \tcmp\tr3, #1\n-\tbne.n\t105a <__gridxc_interpolation_MOD_evaluate_spline_n+0x2be>\n-\tsubs\tr2, r5, r4\n-\tadds\tr3, r5, r4\n-\tcmp\tr2, #1\n-\tble.n\t103a <__gridxc_interpolation_MOD_evaluate_spline_n+0x29e>\n+\tbeq.n\t106c <__gridxc_interpolation_MOD_evaluate_spline_n+0x290>\n+\tb.n\t10f8 <__gridxc_interpolation_MOD_evaluate_spline_n+0x31c>\n \tadd.w\tr3, r3, r3, lsr #31\n \tasrs\tr3, r3, #1\n \tadd.w\tr2, sl, r3, lsl #3\n-\tvldr\td16, [r2, #-8]\n-\tvcmpe.f64\td13, d16\n+\tvldr\td7, [r2, #-8]\n+\tvcmpe.f64\td12, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tit\tpl\n+\tite\tpl\n \tmovpl\tr4, r3\n-\tbpl.n\t100c <__gridxc_interpolation_MOD_evaluate_spline_n+0x270>\n-\tmov\tr5, r3\n+\tmovmi\tr5, r3\n \tsubs\tr2, r5, r4\n \tadds\tr3, r5, r4\n \tcmp\tr2, #1\n-\tbgt.n\t1014 <__gridxc_interpolation_MOD_evaluate_spline_n+0x278>\n-\tldr\tr2, [sp, #28]\n+\tbgt.n\t1050 <__gridxc_interpolation_MOD_evaluate_spline_n+0x274>\n+\tldr\tr2, [sp, #36]\t@ 0x24\n \tsubs\tr3, r4, #1\n \tmul.w\tr3, r2, r3\n \tadd.w\tr3, sl, r3, lsl #3\n \tvldr\td8, [r3]\n \tsubs\tr3, r5, #1\n \tmul.w\tr3, r2, r3\n \tadd.w\tr3, sl, r3, lsl #3\n \tvldr\td9, [r3]\n-\tb.n\te6a <__gridxc_interpolation_MOD_evaluate_spline_n+0xce>\n-\tsubs\tr2, r5, r4\n-\tadds\tr3, r4, r5\n-\tcmp\tr2, #1\n-\tble.n\t103a <__gridxc_interpolation_MOD_evaluate_spline_n+0x29e>\n-\tadd.w\tr3, r3, r3, lsr #31\n-\tldr\tr1, [sp, #28]\n-\tasrs\tr3, r3, #1\n-\tsubs\tr2, r3, #1\n-\tmul.w\tr2, r1, r2\n-\tadd.w\tr2, sl, r2, lsl #3\n-\tvldr\td16, [r2]\n-\tvcmpe.f64\td13, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tit\tpl\n-\tmovpl\tr4, r3\n-\tbpl.n\t105a <__gridxc_interpolation_MOD_evaluate_spline_n+0x2be>\n-\tmov\tr5, r3\n-\tsubs\tr2, r5, r4\n-\tadds\tr3, r4, r5\n-\tcmp\tr2, #1\n-\tbgt.n\t1062 <__gridxc_interpolation_MOD_evaluate_spline_n+0x2c6>\n-\tb.n\t103a <__gridxc_interpolation_MOD_evaluate_spline_n+0x29e>\n+\tb.n\teae <__gridxc_interpolation_MOD_evaluate_spline_n+0xd2>\n \tvldr\td8, [fp, #24]\n-\tvldr\td17, [fp, #32]\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tvsub.f64\td13, d13, d8\n+\tvldr\td7, [fp, #32]\n+\tldr\tr3, [sp, #32]\n+\tvsub.f64\td12, d12, d8\n \tvmov.f64\td9, d8\n-\tsubs\tr4, r2, #1\n-\tvdiv.f64\td16, d13, d17\n-\tvrintz.f64\td18, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d18\n-\tvmov\tr3, s15\n+\tsubs\tr3, #1\n+\tvdiv.f64\td6, d12, d7\n+\tvcvt.s32.f64\ts11, d6\n+\tvmov\tr4, s11\n+\tvcvt.f64.s32\td5, s11\n+\tvcmpe.f64\td6, d5\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n-\taddge\tr3, #1\n-\tcmp\tr3, #1\n+\taddge\tr4, #1\n+\tcmp\tr4, #1\n \tit\tlt\n-\tmovlt\tr3, #1\n+\tmovlt\tr4, #1\n \tcmp\tr4, r3\n \tit\tge\n \tmovge\tr4, r3\n-\tvmov\ts15, r4\n+\tvmov\ts13, r4\n \tsubs\tr3, r4, #1\n \tadds\tr5, r4, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r3\n-\tvfma.f64\td9, d17, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvfma.f64\td8, d17, d16\n-\tb.n\te6a <__gridxc_interpolation_MOD_evaluate_spline_n+0xce>\n+\tvcvt.f64.s32\td6, s13\n+\tvmla.f64\td9, d6, d7\n+\tvmov\ts12, r3\n+\tvcvt.f64.s32\td6, s12\n+\tvmla.f64\td8, d6, d7\n+\tb.n\teae <__gridxc_interpolation_MOD_evaluate_spline_n+0xd2>\n \tadd\tsp, #44\t@ 0x2c\n-\tvpop\t{d8-d13}\n+\tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tnop\n+\tmov\tr1, r3\n+\tb.n\t111e <__gridxc_interpolation_MOD_evaluate_spline_n+0x342>\n+\tadd.w\tr3, r3, r3, lsr #31\n+\tasrs\tr3, r3, #1\n+\tsubs\tr2, r3, #1\n+\tmul.w\tr2, r1, r2\n+\tadd.w\tr2, sl, r2, lsl #3\n+\tvldr\td7, [r2]\n+\tvcmpe.f64\td12, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tpl\n+\tmovpl\tr4, r3\n+\tmovmi\tr5, r3\n+\tsubs\tr2, r5, r4\n+\tadds\tr3, r4, r5\n+\tcmp\tr2, #1\n+\tbgt.n\t10fc <__gridxc_interpolation_MOD_evaluate_spline_n+0x320>\n+\tb.n\t1074 <__gridxc_interpolation_MOD_evaluate_spline_n+0x298>\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x0000032a\n+\t.word\t0x00000318\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002b8\n+\t.word\t0x000002a8\n R_ARM_REL32\t.LC6\n-\t.word\t0x000002b6\n+\t.word\t0x000002a2\n R_ARM_REL32\t.data.rel.ro.local\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000002a8\n+\t.word\t0x00000294\n R_ARM_REL32\t.LC7\n \n-00001114 <__gridxc_interpolation_MOD_evaluate_spline>:\n+00001144 <__gridxc_interpolation_MOD_evaluate_spline>:\n __gridxc_interpolation_MOD_evaluate_spline():\n \tstmdb\tsp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d12}\n+\tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n+\tstr.w\tr0, [ip, #4000]\t@ 0xfa0\n \tvldr\td10, [r1]\n \tmov\tr7, r3\n-\tvldr\td16, [r0, #8]\n-\tmovs\tr3, #1\n-\tldr.w\tr9, [r0, #84]\t@ 0x54\n+\tvldr\td7, [r0, #8]\n \tmov\tr6, r0\n-\tldr.w\tfp, [pc, #684]\t@ 13e8 <__gridxc_interpolation_MOD_evaluate_spline+0x2d4>\n+\tldr.w\tr9, [r0, #84]\t@ 0x54\n \tmov\tr8, r2\n-\tvcmpe.f64\td10, d16\n+\tldrd\tr3, r4, [r0, #88]\t@ 0x58\n+\tvcmpe.f64\td10, d7\n \tcmp.w\tr9, #0\n+\tldr.w\tfp, [pc, #648]\t@ 1400 <__gridxc_interpolation_MOD_evaluate_spline+0x2bc>\n \tit\teq\n-\tmoveq\tr9, r3\n+\tmoveq.w\tr9, #1\n+\tsubs\tr4, r4, r3\n+\tadds\tr4, #1\n \tadd\tfp, pc\n-\tldrd\tr3, r4, [r0, #88]\t@ 0x58\n \tvmrs\tAPSR_nzcv, fpscr\n \tldr.w\tsl, [r0, #60]\t@ 0x3c\n-\tsub.w\tr4, r4, r3\n-\tadd.w\tr4, r4, #1\n \tbic.w\tr4, r4, r4, asr #31\n-\tbmi.n\t1260 <__gridxc_interpolation_MOD_evaluate_spline+0x14c>\n-\tvldr\td16, [r0, #16]\n-\tvcmpe.f64\td10, d16\n+\tbmi.n\t128c <__gridxc_interpolation_MOD_evaluate_spline+0x148>\n+\tvldr\td7, [r0, #16]\n+\tvcmpe.f64\td10, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t1260 <__gridxc_interpolation_MOD_evaluate_spline+0x14c>\n-\tldr\tr0, [pc, #628]\t@ (13ec <__gridxc_interpolation_MOD_evaluate_spline+0x2d8>)\n+\tbgt.n\t128c <__gridxc_interpolation_MOD_evaluate_spline+0x148>\n+\tldr\tr0, [pc, #608]\t@ (1404 <__gridxc_interpolation_MOD_evaluate_spline+0x2c0>)\n \tmovs\tr3, #3\n \tmov\tr2, r6\n \tmovs\tr1, #4\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_select_string>\n R_ARM_THM_CALL\t_gfortran_select_string\n \tmov\tr5, r0\n \tcmp\tr0, #2\n-\tbeq.w\t1382 <__gridxc_interpolation_MOD_evaluate_spline+0x26e>\n+\tbeq.w\t139c <__gridxc_interpolation_MOD_evaluate_spline+0x258>\n \tcmp\tr0, #3\n-\tbeq.n\t1272 <__gridxc_interpolation_MOD_evaluate_spline+0x15e>\n+\tbeq.n\t129e <__gridxc_interpolation_MOD_evaluate_spline+0x15a>\n \tcmp\tr0, #1\n-\tbeq.w\t12fa <__gridxc_interpolation_MOD_evaluate_spline+0x1e6>\n-\tldr\tr3, [pc, #600]\t@ (13f0 <__gridxc_interpolation_MOD_evaluate_spline+0x2dc>)\n+\tbeq.w\t1326 <__gridxc_interpolation_MOD_evaluate_spline+0x1e2>\n+\tldr\tr3, [pc, #580]\t@ (1408 <__gridxc_interpolation_MOD_evaluate_spline+0x2c4>)\n \tmovs\tr1, #54\t@ 0x36\n-\tldr\tr0, [pc, #600]\t@ (13f4 <__gridxc_interpolation_MOD_evaluate_spline+0x2e0>)\n+\tldr\tr0, [pc, #580]\t@ (140c <__gridxc_interpolation_MOD_evaluate_spline+0x2c8>)\n \tadd\tr0, pc\n \tldr.w\tr3, [fp, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvsub.f64\td17, d9, d8\n-\tvsub.f64\td19, d10, d8\n-\tvsub.f64\td10, d9, d10\n-\tvldr\td18, [pc, #556]\t@ 13e0 <__gridxc_interpolation_MOD_evaluate_spline+0x2cc>\n+\tvsub.f64\td6, d8, d9\n+\tvsub.f64\td7, d10, d9\n+\tvsub.f64\td10, d8, d10\n+\tvldr\td11, [pc, #536]\t@ 13f8 <__gridxc_interpolation_MOD_evaluate_spline+0x2b4>\n \tldrd\tr3, r2, [r6, #96]\t@ 0x60\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td16, d19, d17\n-\tvmul.f64\td22, d17, d17\n-\tvdiv.f64\td21, d10, d17\n+\tvdiv.f64\td14, d7, d6\n+\tvmul.f64\td3, d6, d6\n+\tvdiv.f64\td13, d10, d6\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n \tldrd\tr1, r0, [r6, #132]\t@ 0x84\n-\tvmul.f64\td22, d22, d18\n+\tvmul.f64\td11, d3, d11\n \tadds\tr6, r0, r4\n \tadd\tr4, r2\n \tadd\tr0, r5\n \tadd\tr2, r5\n \tadd.w\tr4, r3, r4, lsl #3\n \tadd.w\tr5, r1, r6, lsl #3\n \tadd.w\tr3, r3, r2, lsl #3\n \tadd.w\tr1, r1, r0, lsl #3\n-\tvldr\td19, [r5]\n-\tvldr\td26, [r4]\n-\tvldr\td23, [r1]\n-\tvldr\td18, [r3]\n-\tvmul.f64\td25, d16, d16\n-\tvmul.f64\td28, d19, d16\n-\tvmul.f64\td24, d21, d21\n-\tvmul.f64\td16, d26, d16\n-\tvfma.f64\td16, d18, d21\n-\tvmul.f64\td27, d23, d21\n-\tvsub.f64\td17, d25, d20\n-\tvsub.f64\td21, d24, d20\n-\tvmul.f64\td17, d17, d28\n-\tvfma.f64\td17, d21, d27\n-\tvfma.f64\td16, d22, d17\n-\tvstr\td16, [r8]\n-\tcbz\tr7, 1258 <__gridxc_interpolation_MOD_evaluate_spline+0x144>\n-\tvmov.f64\td17, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td16, #240\t@ 0xbf800000 -1.0\n-\tvsub.f64\td18, d18, d26\n-\tvsub.f64\td8, d8, d9\n-\tvfms.f64\td20, d25, d17\n-\tvfma.f64\td16, d24, d17\n-\tvmul.f64\td19, d19, d20\n-\tvfma.f64\td19, d23, d16\n-\tvfma.f64\td18, d22, d19\n-\tvdiv.f64\td16, d18, d8\n-\tvstr\td16, [r7]\n-\tvpop\t{d8-d12}\n+\tvldr\td3, [r5]\n+\tvldr\td10, [r4]\n+\tvldr\td2, [r1]\n+\tvldr\td5, [r3]\n+\tvmul.f64\td1, d14, d14\n+\tvmul.f64\td12, d3, d14\n+\tvmul.f64\td0, d13, d13\n+\tvmul.f64\td14, d10, d14\n+\tvmla.f64\td14, d5, d13\n+\tvmul.f64\td13, d2, d13\n+\tvsub.f64\td7, d1, d6\n+\tvsub.f64\td4, d0, d6\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d4, d13\n+\tvmla.f64\td14, d7, d11\n+\tvstr\td14, [r8]\n+\tcbz\tr7, 1284 <__gridxc_interpolation_MOD_evaluate_spline+0x140>\n+\tvmov.f64\td7, d6\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tvsub.f64\td5, d5, d10\n+\tvsub.f64\td8, d9, d8\n+\tvmls.f64\td6, d1, d4\n+\tvnmls.f64\td7, d0, d4\n+\tvmul.f64\td7, d7, d2\n+\tvmla.f64\td7, d6, d3\n+\tvmla.f64\td5, d7, d11\n+\tvdiv.f64\td7, d5, d8\n+\tvstr\td7, [r7]\n+\tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #396]\t@ (13f0 <__gridxc_interpolation_MOD_evaluate_spline+0x2dc>)\n+\tldr\tr3, [pc, #376]\t@ (1408 <__gridxc_interpolation_MOD_evaluate_spline+0x2c4>)\n \tmovs\tr1, #51\t@ 0x33\n-\tldr\tr0, [pc, #400]\t@ (13f8 <__gridxc_interpolation_MOD_evaluate_spline+0x2e4>)\n+\tldr\tr0, [pc, #380]\t@ (1410 <__gridxc_interpolation_MOD_evaluate_spline+0x2cc>)\n \tadd\tr0, pc\n \tldr.w\tr3, [fp, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t1176 <__gridxc_interpolation_MOD_evaluate_spline+0x62>\n-\tvldr\td9, [r6, #24]\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tb.n\t11a2 <__gridxc_interpolation_MOD_evaluate_spline+0x5e>\n+\tvldr\td8, [r6, #24]\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tvldr\td11, [r6, #48]\t@ 0x30\n-\tsubs\tr5, r4, #1\n-\tvldr\td8, [r6, #40]\t@ 0x28\n+\tsubs\tr4, #1\n+\tvldr\td9, [r6, #40]\t@ 0x28\n \tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvsub.f64\td17, d10, d9\n-\tvdiv.f64\td0, d17, d11\n-\tvadd.f64\td0, d0, d16\n+\tvsub.f64\td6, d10, d8\n+\tvdiv.f64\td0, d6, d11\n+\tvadd.f64\td0, d0, d7\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d0, d8\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr3, s15\n+\tvdiv.f64\td7, d0, d9\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr5, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n-\taddge\tr3, #1\n-\tcmp\tr3, #1\n+\taddge\tr5, #1\n+\tcmp\tr5, #1\n \tit\tlt\n-\tmovlt\tr3, #1\n-\tcmp\tr5, r3\n+\tmovlt\tr5, #1\n+\tcmp\tr5, r4\n \tit\tge\n-\tmovge\tr5, r3\n+\tmovge\tr5, r4\n \tsubs\tr3, r5, #1\n \tvmov\ts0, r3\n \tadds\tr4, r5, #1\n \tvcvt.f64.s32\td0, s0\n-\tvmul.f64\td0, d0, d8\n+\tvmul.f64\td0, d0, d9\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvmov\ts15, r5\n-\tvsub.f64\td16, d0, d12\n-\tvcvt.f64.s32\td17, s15\n-\tvmul.f64\td0, d17, d8\n-\tvmov.f64\td8, d9\n-\tvfma.f64\td8, d11, d16\n+\tvcvt.f64.s32\td6, s15\n+\tvsub.f64\td7, d0, d12\n+\tvmul.f64\td0, d6, d9\n+\tvmov.f64\td9, d8\n+\tvmla.f64\td9, d7, d11\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvsub.f64\td0, d0, d12\n-\tvfma.f64\td9, d11, d0\n-\tb.n\t11a6 <__gridxc_interpolation_MOD_evaluate_spline+0x92>\n+\tvmla.f64\td8, d0, d11\n+\tb.n\t11d2 <__gridxc_interpolation_MOD_evaluate_spline+0x8e>\n \tcmp.w\tr9, #1\n-\tbne.n\t134c <__gridxc_interpolation_MOD_evaluate_spline+0x238>\n-\tsubs\tr3, r4, r5\n-\tadds\tr1, r4, r5\n-\tcmp\tr3, #1\n-\tble.n\t132e <__gridxc_interpolation_MOD_evaluate_spline+0x21a>\n+\tbeq.n\t134a <__gridxc_interpolation_MOD_evaluate_spline+0x206>\n+\tb.n\t1392 <__gridxc_interpolation_MOD_evaluate_spline+0x24e>\n \tadd.w\tr1, r1, r1, lsr #31\n \tasrs\tr1, r1, #1\n \tadd.w\tr3, sl, r1, lsl #3\n-\tvldr\td16, [r3, #-8]\n-\tvcmpe.f64\td10, d16\n+\tvldr\td7, [r3, #-8]\n+\tvcmpe.f64\td10, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tit\tpl\n+\tite\tpl\n \tmovpl\tr5, r1\n-\tbpl.n\t1300 <__gridxc_interpolation_MOD_evaluate_spline+0x1ec>\n-\tmov\tr4, r1\n+\tmovmi\tr4, r1\n \tsubs\tr3, r4, r5\n \tadds\tr1, r4, r5\n \tcmp\tr3, #1\n-\tbgt.n\t1308 <__gridxc_interpolation_MOD_evaluate_spline+0x1f4>\n+\tbgt.n\t132e <__gridxc_interpolation_MOD_evaluate_spline+0x1ea>\n \tsubs\tr3, r5, #1\n \tmul.w\tr3, r9, r3\n \tadd.w\tr3, sl, r3, lsl #3\n-\tvldr\td8, [r3]\n+\tvldr\td9, [r3]\n \tsubs\tr3, r4, #1\n \tmul.w\tr3, r9, r3\n \tadd.w\tsl, sl, r3, lsl #3\n-\tvldr\td9, [sl]\n-\tb.n\t11a6 <__gridxc_interpolation_MOD_evaluate_spline+0x92>\n-\tsubs\tr2, r4, r5\n-\tadds\tr3, r5, r4\n-\tcmp\tr2, #1\n-\tble.n\t132e <__gridxc_interpolation_MOD_evaluate_spline+0x21a>\n+\tvldr\td8, [sl]\n+\tb.n\t11d2 <__gridxc_interpolation_MOD_evaluate_spline+0x8e>\n \tadd.w\tr3, r3, r3, lsr #31\n \tasrs\tr3, r3, #1\n \tsubs\tr2, r3, #1\n \tmul.w\tr2, r9, r2\n \tadd.w\tr2, sl, r2, lsl #3\n-\tvldr\td16, [r2]\n-\tvcmpe.f64\td10, d16\n+\tvldr\td7, [r2]\n+\tvcmpe.f64\td10, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tit\tpl\n+\tite\tpl\n \tmovpl\tr5, r3\n-\tbpl.n\t134c <__gridxc_interpolation_MOD_evaluate_spline+0x238>\n-\tmov\tr4, r3\n+\tmovmi\tr4, r3\n \tsubs\tr2, r4, r5\n \tadds\tr3, r5, r4\n \tcmp\tr2, #1\n-\tbgt.n\t1354 <__gridxc_interpolation_MOD_evaluate_spline+0x240>\n-\tb.n\t132e <__gridxc_interpolation_MOD_evaluate_spline+0x21a>\n-\tvldr\td8, [r6, #24]\n-\tsubs\tr5, r4, #1\n-\tvldr\td17, [r6, #32]\n-\tvsub.f64\td18, d10, d8\n-\tvmov.f64\td9, d8\n-\tvdiv.f64\td16, d18, d17\n-\tvrintz.f64\td18, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d18\n-\tvmov\tr3, s15\n+\tbgt.n\t1370 <__gridxc_interpolation_MOD_evaluate_spline+0x22c>\n+\tb.n\t1352 <__gridxc_interpolation_MOD_evaluate_spline+0x20e>\n+\tvldr\td9, [r6, #24]\n+\tsubs\tr4, #1\n+\tvldr\td7, [r6, #32]\n+\tvsub.f64\td5, d10, d9\n+\tvmov.f64\td8, d9\n+\tvdiv.f64\td6, d5, d7\n+\tvcvt.s32.f64\ts11, d6\n+\tvmov\tr5, s11\n+\tvcvt.f64.s32\td5, s11\n+\tvcmpe.f64\td6, d5\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tge\n-\taddge\tr3, #1\n-\tcmp\tr3, #1\n+\taddge\tr5, #1\n+\tcmp\tr5, #1\n \tit\tlt\n-\tmovlt\tr3, #1\n-\tcmp\tr5, r3\n+\tmovlt\tr5, #1\n+\tcmp\tr5, r4\n \tit\tge\n-\tmovge\tr5, r3\n-\tvmov\ts15, r5\n+\tmovge\tr5, r4\n+\tvmov\ts13, r5\n \tsubs\tr3, r5, #1\n \tadds\tr4, r5, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r3\n-\tvfma.f64\td9, d17, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvfma.f64\td8, d17, d16\n-\tb.n\t11a6 <__gridxc_interpolation_MOD_evaluate_spline+0x92>\n-\tnop\n+\tvcvt.f64.s32\td6, s13\n+\tvmla.f64\td8, d6, d7\n+\tvmov\ts12, r3\n+\tvcvt.f64.s32\td6, s12\n+\tvmla.f64\td9, d6, d7\n+\tb.n\t11d2 <__gridxc_interpolation_MOD_evaluate_spline+0x8e>\n \tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x00000298\n+\t.word\t0x00000278\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000026a\n+\t.word\t0x00000256\n R_ARM_REL32\t.data.rel.ro.local\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000254\n+\t.word\t0x00000240\n R_ARM_REL32\t.LC7\n-\t.word\t0x0000018e\n+\t.word\t0x0000017a\n R_ARM_REL32\t.LC6\n \n-000013fc <__gridxc_interpolation_MOD_generate_spline_master>:\n+00001414 <__gridxc_interpolation_MOD_generate_spline_master>:\n __gridxc_interpolation_MOD_generate_spline_master.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d13}\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3960]\t@ 0xf78\n-\tsub\tsp, #52\t@ 0x34\n+\tstr.w\tr0, [ip, #3912]\t@ 0xf48\n+\tsub\tsp, #84\t@ 0x54\n \tadd\tr7, sp, #0\n \tmov\tsl, r2\n-\tldr\tr2, [pc, #480]\t@ (15f8 <__gridxc_interpolation_MOD_generate_spline_master+0x1fc>)\n+\tldr\tr2, [pc, #488]\t@ (1618 <__gridxc_interpolation_MOD_generate_spline_master+0x204>)\n \tmov\tr6, r1\n \tldr\tr5, [r3, #0]\n-\tldr\tr3, [pc, #476]\t@ (15fc <__gridxc_interpolation_MOD_generate_spline_master+0x200>)\n+\tldr.w\tr4, [r7, #184]\t@ 0xb8\n \tadd\tr2, pc\n-\tldrd\tr9, r4, [r7, #136]\t@ 0x88\n-\tstr\tr4, [r7, #20]\n+\tldr\tr3, [pc, #480]\t@ (161c <__gridxc_interpolation_MOD_generate_spline_master+0x208>)\n+\tstr\tr4, [r7, #60]\t@ 0x3c\n+\tldr.w\tr4, [r7, #188]\t@ 0xbc\n+\tstr\tr4, [r7, #52]\t@ 0x34\n \tmov\tr4, r0\n \tmov\tr0, sp\n+\tldr.w\tr8, [r7, #200]\t@ 0xc8\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr2, [r7, #148]\t@ 0x94\n+\tldr.w\tr2, [r7, #196]\t@ 0xc4\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [r7, #144]\t@ 0x90\n-\tstr\tr3, [r7, #16]\n+\tldr.w\tr3, [r7, #192]\t@ 0xc0\n+\tstr\tr3, [r7, #48]\t@ 0x30\n \tbic.w\tr3, r5, r5, asr #31\n-\tstr\tr2, [r7, #12]\n+\tstr\tr2, [r7, #44]\t@ 0x2c\n \tlsls\tr3, r3, #3\n-\tstr\tr3, [r7, #24]\n+\tstr\tr3, [r7, #56]\t@ 0x38\n \tmov\tr1, r3\n \tmov\tr2, r3\n \tbic.w\tr3, r3, #4080\t@ 0xff0\n-\tldr.w\tr8, [r7, #152]\t@ 0x98\n-\tbic.w\tr3, r3, #15\n \tadds\tr1, #7\n+\tbic.w\tr3, r3, #15\n+\tstr.w\tsp, [r7, #36]\t@ 0x24\n \tsub.w\tr3, sp, r3\n-\tstr.w\tsp, [r7, #4]\n \tcmp\tr0, r3\n-\tbeq.n\t1474 <__gridxc_interpolation_MOD_generate_spline_master+0x78>\n+\tbeq.n\t1492 <__gridxc_interpolation_MOD_generate_spline_master+0x7e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1466 <__gridxc_interpolation_MOD_generate_spline_master+0x6a>\n+\tbne.n\t1484 <__gridxc_interpolation_MOD_generate_spline_master+0x70>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t1596 <__gridxc_interpolation_MOD_generate_spline_master+0x19a>\n+\tbne.w\t15b2 <__gridxc_interpolation_MOD_generate_spline_master+0x19e>\n \tbic.w\tr3, r1, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr3, r3, #15\n \tbic.w\tr2, r1, #7\n \tsub.w\tr3, sp, r3\n-\tstr.w\tsp, [r7, #32]\n+\tstr.w\tsp, [r7, #68]\t@ 0x44\n \tcmp\tr0, r3\n-\tbeq.n\t14aa <__gridxc_interpolation_MOD_generate_spline_master+0xae>\n+\tbeq.n\t14c8 <__gridxc_interpolation_MOD_generate_spline_master+0xb4>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t149c <__gridxc_interpolation_MOD_generate_spline_master+0xa0>\n+\tbne.n\t14ba <__gridxc_interpolation_MOD_generate_spline_master+0xa6>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.n\t15a0 <__gridxc_interpolation_MOD_generate_spline_master+0x1a4>\n+\tbne.n\t15bc <__gridxc_interpolation_MOD_generate_spline_master+0x1a8>\n \tbic.w\tr3, r1, #4080\t@ 0xff0\n \tmov\tr2, sp\n \tbic.w\tr3, r3, #15\n \tbic.w\tr1, r1, #7\n \tsub.w\tr3, sp, r3\n-\tstr.w\tsp, [r7, #28]\n+\tmov\tr9, sp\n \tcmp\tr2, r3\n-\tbeq.n\t14de <__gridxc_interpolation_MOD_generate_spline_master+0xe2>\n+\tbeq.n\t14fa <__gridxc_interpolation_MOD_generate_spline_master+0xe6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t14d0 <__gridxc_interpolation_MOD_generate_spline_master+0xd4>\n+\tbne.n\t14ec <__gridxc_interpolation_MOD_generate_spline_master+0xd8>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 14f0 <__gridxc_interpolation_MOD_generate_spline_master+0xf4>\n+\tcbz\tr1, 150c <__gridxc_interpolation_MOD_generate_spline_master+0xf8>\n \tsubs\tr1, #4\n \tadd.w\tr3, sp, r1\n \tstr\tr0, [r3, #0]\n \tldr\tr0, [r4, #60]\t@ 0x3c\n-\tstr.w\tsp, [r7, #36]\t@ 0x24\n-\tcbz\tr0, 14fc <__gridxc_interpolation_MOD_generate_spline_master+0x100>\n+\tstr.w\tsp, [r7, #64]\t@ 0x40\n+\tcbz\tr0, 1518 <__gridxc_interpolation_MOD_generate_spline_master+0x104>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r4, #96]\t@ 0x60\n-\tcbz\tr0, 1504 <__gridxc_interpolation_MOD_generate_spline_master+0x108>\n+\tcbz\tr0, 1520 <__gridxc_interpolation_MOD_generate_spline_master+0x10c>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r4, #132]\t@ 0x84\n-\tcbz\tr0, 150e <__gridxc_interpolation_MOD_generate_spline_master+0x112>\n+\tcbz\tr0, 152a <__gridxc_interpolation_MOD_generate_spline_master+0x116>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr2, #0\n \tcmp\tr5, #1\n \tstr\tr2, [r4, #60]\t@ 0x3c\n \tstr\tr2, [r4, #96]\t@ 0x60\n \tstr.w\tr2, [r4, #132]\t@ 0x84\n-\tble.n\t15aa <__gridxc_interpolation_MOD_generate_spline_master+0x1ae>\n+\tble.n\t15c6 <__gridxc_interpolation_MOD_generate_spline_master+0x1b2>\n \tcmp\tr5, #2\n-\tbeq.w\t1a2e <__gridxc_interpolation_MOD_generate_spline_master+0x632>\n-\tvldr\td11, [r6, #8]\n+\tbeq.w\t1a7a <__gridxc_interpolation_MOD_generate_spline_master+0x666>\n+\tvldr\td8, [r6, #8]\n \tadd.w\tr3, r6, #16\n-\tvldr\td10, [r6]\n+\tvldr\td9, [r6]\n \tsub.w\tfp, r5, #2\n \tmov\tr1, r3\n-\tvmov.f64\td17, d11\n-\tvsub.f64\td18, d11, d10\n-\tb.n\t1544 <__gridxc_interpolation_MOD_generate_spline_master+0x148>\n+\tvmov.f64\td6, d8\n+\tvsub.f64\td5, d8, d9\n+\tb.n\t1560 <__gridxc_interpolation_MOD_generate_spline_master+0x14c>\n \tadds\tr2, #1\n \tcmp\tr2, fp\n-\tbeq.n\t15ba <__gridxc_interpolation_MOD_generate_spline_master+0x1be>\n-\tvmov.f64\td19, d17\n-\tvldmia\tr1!, {d17}\n-\tvmov.f64\td16, d18\n-\tvsub.f64\td18, d17, d19\n-\tvmul.f64\td16, d18, d16\n-\tvcmpe.f64\td16, #0.0\n+\tbeq.n\t15d6 <__gridxc_interpolation_MOD_generate_spline_master+0x1c2>\n+\tvmov.f64\td4, d6\n+\tvldmia\tr1!, {d6}\n+\tvmov.f64\td7, d5\n+\tvsub.f64\td5, d6, d4\n+\tvmul.f64\td7, d5, d7\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t153e <__gridxc_interpolation_MOD_generate_spline_master+0x142>\n+\tbhi.n\t155a <__gridxc_interpolation_MOD_generate_spline_master+0x146>\n \tcmp.w\tr8, #0\n-\tbeq.n\t1570 <__gridxc_interpolation_MOD_generate_spline_master+0x174>\n+\tbeq.n\t158c <__gridxc_interpolation_MOD_generate_spline_master+0x178>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr.w\tr3, [r8]\n-\tldr.w\tsp, [r7, #4]\n-\tldr\tr2, [pc, #136]\t@ (1600 <__gridxc_interpolation_MOD_generate_spline_master+0x204>)\n-\tldr\tr3, [pc, #132]\t@ (15fc <__gridxc_interpolation_MOD_generate_spline_master+0x200>)\n+\tldr.w\tsp, [r7, #36]\t@ 0x24\n+\tldr\tr2, [pc, #140]\t@ (1620 <__gridxc_interpolation_MOD_generate_spline_master+0x20c>)\n+\tldr\tr3, [pc, #136]\t@ (161c <__gridxc_interpolation_MOD_generate_spline_master+0x208>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #76]\t@ 0x4c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1acc <__gridxc_interpolation_MOD_generate_spline_master+0x6d0>\n-\tadds\tr7, #52\t@ 0x34\n+\tbne.w\t1b26 <__gridxc_interpolation_MOD_generate_spline_master+0x712>\n+\tadds\tr7, #84\t@ 0x54\n \tmov\tsp, r7\n-\tvpop\t{d8-d13}\n+\tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tb.n\t1482 <__gridxc_interpolation_MOD_generate_spline_master+0x86>\n+\tb.n\t14a0 <__gridxc_interpolation_MOD_generate_spline_master+0x8c>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tb.n\t14b6 <__gridxc_interpolation_MOD_generate_spline_master+0xba>\n+\tb.n\t14d4 <__gridxc_interpolation_MOD_generate_spline_master+0xc0>\n \tcmp.w\tr8, #0\n-\tbeq.n\t1570 <__gridxc_interpolation_MOD_generate_spline_master+0x174>\n+\tbeq.n\t158c <__gridxc_interpolation_MOD_generate_spline_master+0x178>\n \tmvn.w\tr3, #1\n \tstr.w\tr3, [r8]\n-\tb.n\t1570 <__gridxc_interpolation_MOD_generate_spline_master+0x174>\n+\tb.n\t158c <__gridxc_interpolation_MOD_generate_spline_master+0x178>\n \tcmp.w\tr8, #0\n-\tbeq.n\t15c6 <__gridxc_interpolation_MOD_generate_spline_master+0x1ca>\n+\tbeq.n\t15e2 <__gridxc_interpolation_MOD_generate_spline_master+0x1ce>\n \tmovs\tr2, #0\n \tstr.w\tr2, [r8]\n-\tvldr\td16, [r6, #16]\n-\tvsub.f64\td13, d11, d10\n-\tstr\tr3, [r7, #8]\n-\tvsub.f64\td16, d16, d11\n-\tvdiv.f64\td12, d16, d13\n-\tvmov.f64\td0, d12\n+\tvldr\td7, [r6, #16]\n+\tvsub.f64\td11, d8, d9\n+\tstr\tr3, [r7, #40]\t@ 0x28\n+\tvsub.f64\td7, d7, d8\n+\tvdiv.f64\td10, d7, d11\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tldr\tr3, [r7, #8]\n-\tvmov.f64\td8, d0\n-\tvldr\td19, [pc, #8]\t@ 15f0 <__gridxc_interpolation_MOD_generate_spline_master+0x1f4>\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tvldr\td5, [pc, #16]\t@ 1610 <__gridxc_interpolation_MOD_generate_spline_master+0x1fc>\n \tmovs\tr2, #3\n-\tb.n\t1610 <__gridxc_interpolation_MOD_generate_spline_master+0x214>\n+\tvstr\td0, [r7, #8]\n+\tb.n\t1630 <__gridxc_interpolation_MOD_generate_spline_master+0x21c>\n \tnop\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x000001d6\n+\t.word\t0x000001dc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000084\n+\t.word\t0x00000088\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \tadds\tr2, #1\n-\tvmov.f64\td10, d17\n+\tvmov.f64\td9, d6\n \tcmp\tr2, r5\n-\tbgt.w\t1a8a <__gridxc_interpolation_MOD_generate_spline_master+0x68e>\n-\tvmov.f64\td17, d11\n-\tvldmia\tr3!, {d11}\n-\tvsub.f64\td10, d17, d10\n-\tvsub.f64\td18, d11, d17\n-\tvdiv.f64\td16, d18, d10\n-\tvsub.f64\td16, d16, d12\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d19\n+\tbgt.w\t1adc <__gridxc_interpolation_MOD_generate_spline_master+0x6c8>\n+\tvmov.f64\td6, d8\n+\tvldmia\tr3!, {d8}\n+\tvsub.f64\td9, d6, d9\n+\tvsub.f64\td4, d8, d6\n+\tvdiv.f64\td7, d4, d9\n+\tvsub.f64\td7, d7, d10\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t1604 <__gridxc_interpolation_MOD_generate_spline_master+0x208>\n-\tldr.w\tr3, [pc, #1248]\t@ 1b18 <__gridxc_interpolation_MOD_generate_spline_master+0x71c>\n+\tblt.n\t1624 <__gridxc_interpolation_MOD_generate_spline_master+0x210>\n+\tldr.w\tr3, [pc, #1304]\t@ 1b70 <__gridxc_interpolation_MOD_generate_spline_master+0x75c>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n-\tstrh\tr3, [r7, #40]\t@ 0x28\n+\tstrh.w\tr3, [r7, #72]\t@ 0x48\n \tlsrs\tr3, r3, #16\n-\tstrb.w\tr3, [r7, #42]\t@ 0x2a\n-\tcmp.w\tr9, #0\n-\tbeq.w\t1a52 <__gridxc_interpolation_MOD_generate_spline_master+0x656>\n-\tvldr\td19, [r6]\n-\tvmov.f64\td22, #8\t@ 0x40400000 3.0\n-\tvldr\td16, [sl, #8]\n-\tvmov.f64\td21, #224\t@ 0xbf000000 -0.5\n-\tvldr\td17, [r6, #8]\n-\tvldr\td18, [sl]\n-\tvldr\td20, [r9]\n-\tvsub.f64\td17, d17, d19\n-\tvsub.f64\td18, d16, d18\n-\tvdiv.f64\td19, d22, d17\n-\tvdiv.f64\td16, d18, d17\n-\tvsub.f64\td16, d16, d20\n-\tvmul.f64\td16, d16, d19\n-\tldr\tr3, [r7, #32]\n+\tstrb.w\tr3, [r7, #74]\t@ 0x4a\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tcmp\tr3, #0\n+\tbeq.w\t1aa0 <__gridxc_interpolation_MOD_generate_spline_master+0x68c>\n+\tvldr\td7, [r6, #8]\n+\tvmov.f64\td2, #8\t@ 0x40400000 3.0\n+\tvldr\td4, [sl]\n+\tvmov.f64\td10, #224\t@ 0xbf000000 -0.5\n+\tvldr\td5, [r6]\n+\tvldr\td6, [sl, #8]\n+\tvldr\td3, [r3]\n+\tvsub.f64\td5, d7, d5\n+\tvsub.f64\td6, d6, d4\n+\tvdiv.f64\td4, d2, d5\n+\tvdiv.f64\td7, d6, d5\n+\tvsub.f64\td7, d7, d3\n+\tvmul.f64\td7, d7, d4\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tsubs\tr1, r5, #1\n-\tldr\tr2, [r7, #28]\n-\tstr\tr1, [r7, #8]\n-\tvstr\td16, [r3]\n-\tldr\tr3, [r7, #20]\n-\tvstr\td21, [r2]\n+\tvstr\td10, [r9]\n+\tstr\tr1, [r7, #40]\t@ 0x28\n+\tvstr\td7, [r3]\n+\tldr\tr3, [r7, #52]\t@ 0x34\n \tcmp\tr3, #0\n-\tbeq.w\t1a5c <__gridxc_interpolation_MOD_generate_spline_master+0x660>\n-\tmov.w\tr8, r5, lsl #3\n-\tvldr\td16, [r3]\n-\tadd.w\tr3, r6, r8\n-\tvmov.f64\td19, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td22, [r3, #-16]\n-\tvmov.f64\td17, d20\n-\tvldr\td18, [r3, #-8]\n-\tadd.w\tr3, sl, r8\n-\tvsub.f64\td18, d18, d22\n-\tvldr\td23, [r3, #-16]\n-\tvdiv.f64\td22, d19, d18\n-\tvldr\td19, [r3, #-8]\n-\tlsls\tr3, r1, #3\n-\tstr\tr3, [r7, #20]\n-\tadds\tr3, r2, r3\n-\tvsub.f64\td19, d19, d23\n-\tvstr\td20, [r3]\n-\tvdiv.f64\td23, d19, d18\n-\tvsub.f64\td16, d16, d23\n-\tvmul.f64\td16, d16, d22\n-\tldr\tr3, [r7, #32]\n+\tbeq.w\t1aaa <__gridxc_interpolation_MOD_generate_spline_master+0x696>\n+\tvldr\td7, [r3]\n+\tlsls\tr3, r5, #3\n+\tadds\tr2, r6, r3\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tadd\tr3, sl\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvmov.f64\td2, #8\t@ 0x40400000 3.0\n+\tvldr\td3, [r2, #-16]\n+\tvmov.f64\td6, d4\n+\tvldr\td5, [r2, #-8]\n+\tlsls\tr2, r1, #3\n+\tstr\tr2, [r7, #52]\t@ 0x34\n+\tadd\tr2, r9\n+\tvsub.f64\td5, d5, d3\n+\tvstr\td4, [r2]\n+\tvldr\td4, [r3, #-8]\n+\tvdiv.f64\td3, d2, d5\n+\tvldr\td2, [r3, #-16]\n+\tvsub.f64\td4, d4, d2\n+\tvdiv.f64\td2, d4, d5\n+\tvsub.f64\td7, d7, d2\n+\tvmul.f64\td7, d7, d3\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr5, #2\n-\tadd.w\tr9, r3, r8\n-\tvstr\td16, [r9, #-8]\n-\tbeq.w\t1ac4 <__gridxc_interpolation_MOD_generate_spline_master+0x6c8>\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tadd.w\tr8, r3, r2\n+\tvstr\td7, [r8, #-8]\n+\tbeq.w\t18c0 <__gridxc_interpolation_MOD_generate_spline_master+0x4ac>\n \tcmp\tr5, #4\n-\tble.w\t1ac8 <__gridxc_interpolation_MOD_generate_spline_master+0x6cc>\n-\tvldr\td18, [sl]\n+\tble.w\t1b22 <__gridxc_interpolation_MOD_generate_spline_master+0x70e>\n+\tvldr\td12, [sl]\n \tsubs\tr1, r5, #5\n-\tvldr\td23, [sl, #8]\n-\tmov\tr0, r3\n-\tvldr\td16, [r6]\n+\tvldr\td3, [sl, #8]\n \tbic.w\tr1, r1, #1\n-\tvldr\td17, [r6, #8]\n-\tmov\tip, r0\n-\tvsub.f64\td18, d23, d18\n-\tldr.w\tlr, [r7, #28]\n-\tvldr\td26, [r3]\n+\tvldr\td7, [r6]\n+\tmov\tip, r3\n+\tvldr\td6, [r6, #8]\n \tadds\tr1, #4\n-\tvsub.f64\td22, d17, d16\n+\tvsub.f64\td12, d3, d12\n+\tvldr\td11, [r3]\n \tmov\tr2, r6\n \tmov\tr3, sl\n-\tmovs\tr0, #2\n-\tvmov.f64\td31, #0\t@ 0x40000000 2.0\n-\tvmov.f64\td30, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td29, #24\t@ 0x40c00000 6.0\n-\tvldr\td19, [r3, #16]\n-\tvmov.f64\td25, d16\n-\tvldr\td16, [r2, #16]\n-\tvmov.f64\td24, d17\n-\tvdiv.f64\td20, d18, d22\n-\tadd.w\tlr, lr, #16\n-\tvsub.f64\td27, d19, d23\n-\tvldr\td23, [r3, #24]\n-\tvsub.f64\td7, d16, d17\n-\tvsub.f64\td25, d16, d25\n-\tvldr\td17, [r2, #24]\n-\tadd.w\tip, ip, #16\n-\tvsub.f64\td18, d23, d19\n-\tadds\tr0, #2\n-\tadds\tr3, #16\n+\tvsub.f64\td9, d6, d7\n+\tmov\tr0, r9\n+\tmov.w\tlr, #2\n+\tvmov.f64\td13, #0\t@ 0x40000000 2.0\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td15, #24\t@ 0x40c00000 6.0\n \tadds\tr2, #16\n-\tvdiv.f64\td6, d27, d7\n-\tvsub.f64\td24, d17, d24\n-\tvdiv.f64\td28, d22, d25\n-\tvsub.f64\td22, d17, d16\n-\tcmp\tr0, r1\n-\tvdiv.f64\td27, d7, d24\n-\tvmov.f64\td7, d31\n-\tvdiv.f64\td19, d18, d22\n-\tvsub.f64\td20, d6, d20\n-\tvfma.f64\td7, d28, d21\n-\tvsub.f64\td5, d28, d30\n-\tvmul.f64\td20, d20, d29\n-\tvsub.f64\td19, d19, d6\n-\tvsub.f64\td6, d27, d30\n-\tvdiv.f64\td21, d20, d25\n-\tvdiv.f64\td20, d5, d7\n-\tvmul.f64\td25, d19, d29\n-\tvdiv.f64\td19, d25, d24\n-\tvmov.f64\td24, d31\n-\tvfms.f64\td21, d28, d26\n-\tvfma.f64\td24, d20, d27\n-\tvstr\td20, [lr, #-8]\n-\tvdiv.f64\td20, d21, d7\n-\tvdiv.f64\td21, d6, d24\n-\tvfms.f64\td19, d20, d27\n-\tvstr\td20, [ip, #-8]\n-\tvstr\td21, [lr]\n-\tvdiv.f64\td26, d19, d24\n-\tvstr\td26, [ip]\n-\tbne.n\t173c <__gridxc_interpolation_MOD_generate_spline_master+0x340>\n+\tadds\tr3, #16\n+\tvdiv.f64\td4, d12, d9\n+\tvmov.f64\td8, d7\n+\tvmov.f64\td2, d6\n+\tadds\tr0, #16\n+\tvldr\td7, [r2]\n+\tadd.w\tip, ip, #16\n+\tvldr\td12, [r3]\n+\tadd.w\tlr, lr, #2\n+\tcmp\tlr, r1\n+\tvsub.f64\td1, d7, d6\n+\tvsub.f64\td8, d7, d8\n+\tvsub.f64\td0, d12, d3\n+\tvldr\td6, [r2, #8]\n+\tvldr\td3, [r3, #8]\n+\tvdiv.f64\td5, d9, d8\n+\tvsub.f64\td2, d6, d2\n+\tvdiv.f64\td0, d0, d1\n+\tvmov.f64\td9, d13\n+\tvsub.f64\td12, d3, d12\n+\tvstr\td2, [r7, #16]\n+\tvdiv.f64\td2, d1, d2\n+\tvmla.f64\td9, d5, d10\n+\tvsub.f64\td4, d0, d4\n+\tvstr\td0, [r7, #24]\n+\tvmul.f64\td4, d4, d15\n+\tvdiv.f64\td1, d4, d8\n+\tvmov.f64\td4, d13\n+\tvmls.f64\td1, d5, d11\n+\tvsub.f64\td5, d5, d14\n+\tvdiv.f64\td8, d5, d9\n+\tvsub.f64\td5, d2, d14\n+\tvdiv.f64\td0, d1, d9\n+\tvsub.f64\td9, d6, d7\n+\tvldr\td1, [r7, #24]\n+\tvmla.f64\td4, d8, d2\n+\tvstr\td8, [r0, #-8]\n+\tvstr\td0, [ip, #-8]\n+\tvdiv.f64\td10, d5, d4\n+\tvdiv.f64\td5, d12, d9\n+\tvstr\td10, [r0]\n+\tvsub.f64\td5, d5, d1\n+\tvldr\td1, [r7, #16]\n+\tvmul.f64\td5, d5, d15\n+\tvdiv.f64\td1, d5, d1\n+\tvmls.f64\td1, d0, d2\n+\tvdiv.f64\td11, d1, d4\n+\tvstr\td11, [ip]\n+\tbne.n\t1758 <__gridxc_interpolation_MOD_generate_spline_master+0x344>\n \tlsls\tr3, r1, #3\n-\tvmov.f64\td25, #0\t@ 0x40000000 2.0\n+\tvmov.f64\td0, #0\t@ 0x40000000 2.0\n \tsub.w\tr0, r3, #16\n \tadd.w\tlr, r3, sl\n \tadds\tr2, r6, r3\n-\tldr\tr3, [r7, #28]\n-\tvmov.f64\td24, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td23, #24\t@ 0x40c00000 6.0\n-\tadd.w\tip, r3, r0\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tadd.w\tip, r9, r0\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n \tadd\tr0, r3\n \tmov\tr3, lr\n-\tvldr\td27, [r2, #-16]\n+\tvmov.f64\td2, #24\t@ 0x40c00000 6.0\n+\tvldr\td5, [r2, #-16]\n \tadd.w\tip, ip, #8\n-\tvldr\td18, [r2, #-8]\n+\tvldr\td3, [r2, #-8]\n \tadds\tr0, #8\n-\tvldr\td26, [r3, #-8]\n+\tvldr\td11, [r3, #-8]\n \tadds\tr1, #1\n-\tvldr\td17, [r3, #-16]\n+\tvldr\td6, [r3, #-16]\n \tmov\tlr, r3\n-\tvldmia\tr2!, {d16}\n-\tvsub.f64\td21, d18, d27\n-\tvldr\td22, [ip, #-8]\n+\tvldmia\tr2!, {d7}\n+\tvsub.f64\td9, d3, d5\n+\tvldr\td4, [ip, #-8]\n \tadds\tr3, #8\n-\tvsub.f64\td20, d26, d17\n-\tvldr\td19, [r0, #-8]\n-\tvsub.f64\td18, d16, d18\n-\tvsub.f64\td16, d16, d27\n+\tvsub.f64\td6, d11, d6\n \tcmp\tr5, r1\n-\tvdiv.f64\td27, d20, d21\n-\tvdiv.f64\td20, d21, d16\n-\tvldr\td21, [r3, #-8]\n-\tvsub.f64\td21, d21, d26\n-\tvdiv.f64\td17, d21, d18\n-\tvmov.f64\td21, d25\n-\tvfma.f64\td21, d20, d22\n-\tvsub.f64\td18, d20, d24\n-\tvsub.f64\td17, d17, d27\n-\tvdiv.f64\td22, d18, d21\n-\tvmul.f64\td17, d17, d23\n-\tvdiv.f64\td18, d17, d16\n-\tvstr\td22, [ip]\n-\tvfms.f64\td18, d20, d19\n-\tvdiv.f64\td17, d18, d21\n-\tvstr\td17, [r0]\n-\tbgt.n\t180e <__gridxc_interpolation_MOD_generate_spline_master+0x412>\n-\tldr\tr2, [r7, #20]\n-\tldr\tr3, [r7, #28]\n-\tvldr\td16, [r9, #-8]\n-\tadd\tr3, r2\n-\tvldr\td17, [r3]\n-\tmov\tr3, r2\n-\tldr\tr1, [r7, #28]\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldr\td20, [r9, #-16]\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tadd.w\tfp, r1, fp, lsl #3\n-\tvfms.f64\td16, d20, d17\n+\tvsub.f64\td3, d7, d3\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td5, [r0, #-8]\n+\tvdiv.f64\td10, d6, d9\n+\tvdiv.f64\td8, d9, d7\n+\tvldr\td9, [r3, #-8]\n+\tvsub.f64\td9, d9, d11\n+\tvdiv.f64\td6, d9, d3\n+\tvmov.f64\td3, d0\n+\tvmla.f64\td3, d8, d4\n+\tvsub.f64\td4, d8, d1\n+\tvsub.f64\td6, d6, d10\n+\tvdiv.f64\td9, d4, d3\n+\tvmul.f64\td6, d6, d2\n+\tvdiv.f64\td4, d6, d7\n+\tvstr\td9, [ip]\n+\tvmls.f64\td4, d8, d5\n+\tvdiv.f64\td6, d4, d3\n+\tvstr\td6, [r0]\n+\tbgt.n\t1838 <__gridxc_interpolation_MOD_generate_spline_master+0x424>\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tvldr\td7, [r8, #-8]\n+\tadd\tr3, r9\n+\tvldr\td6, [r3]\n+\tadd.w\tfp, r9, fp, lsl #3\n+\tvldr\td3, [r8, #-16]\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tldr\tr2, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tvldr\td4, [fp]\n+\tvmls.f64\td7, d6, d3\n \tadds\tr3, r2, r3\n-\tvldr\td19, [fp]\n-\tvfma.f64\td18, d19, d17\n-\tvdiv.f64\td17, d16, d18\n-\tvstr\td17, [r3]\n-\tadd.w\tr3, r2, r8\n-\tsub.w\tr2, r8, #8\n-\tadds\tr0, r1, r2\n-\tldr\tr1, [r7, #32]\n-\tvldr\td16, [r3, #-8]\n-\tldr\tr3, [r7, #36]\t@ 0x24\n+\tldr\tr1, [r7, #60]\t@ 0x3c\n+\tvmla.f64\td5, d6, d4\n+\tvdiv.f64\td6, d7, d5\n+\tvstr\td6, [r3]\n+\tadds\tr3, r2, r1\n+\tsub.w\tr2, r1, #8\n+\tldr\tr1, [r7, #68]\t@ 0x44\n+\tadd.w\tr0, r9, r2\n+\tvldr\td7, [r3, #-8]\n \tadd\tr1, r2\n+\tldr\tr3, [r7, #64]\t@ 0x40\n \tadd\tr2, r3\n-\tldr\tr3, [r7, #8]\n-\tvldmdb\tr0!, {d18}\n+\tldr\tr3, [r7, #40]\t@ 0x28\n+\tvldmdb\tr0!, {d5}\n \tsubs\tr3, #1\n-\tvldmdb\tr1!, {d17}\n-\tvfma.f64\td17, d18, d16\n-\tvmov.f64\td16, d17\n-\tvstmdb\tr2!, {d17}\n-\tbne.n\t18d8 <__gridxc_interpolation_MOD_generate_spline_master+0x4dc>\n-\tldr\tr3, [r7, #16]\n-\tcbz\tr3, 18fe <__gridxc_interpolation_MOD_generate_spline_master+0x502>\n-\tldr\tr1, [r7, #36]\t@ 0x24\n+\tvldmdb\tr1!, {d6}\n+\tvmla.f64\td6, d7, d5\n+\tvmov.f64\td7, d6\n+\tvstmdb\tr2!, {d6}\n+\tbne.n\t1900 <__gridxc_interpolation_MOD_generate_spline_master+0x4ec>\n+\tldr\tr3, [r7, #48]\t@ 0x30\n+\tcbz\tr3, 1926 <__gridxc_interpolation_MOD_generate_spline_master+0x512>\n+\tldrd\tr2, r1, [r7, #60]\t@ 0x3c\n \tmov\tr0, r3\n-\tmov\tr2, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr3, [r7, #12]\n-\tcbz\tr3, 190a <__gridxc_interpolation_MOD_generate_spline_master+0x50e>\n+\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tcbz\tr3, 1932 <__gridxc_interpolation_MOD_generate_spline_master+0x51e>\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t1570 <__gridxc_interpolation_MOD_generate_spline_master+0x174>\n-\tvmov.i32\td11, #0\t@ 0x00000000\n-\tmovs\tr1, #8\n-\tmovw\tr9, #769\t@ 0x301\n+\tbeq.w\t158c <__gridxc_interpolation_MOD_generate_spline_master+0x178>\n+\tadd.w\tr2, r4, #68\t@ 0x44\n+\tmovs\tr3, #0\n+\tmov.w\tr9, #8\n+\tmovw\tfp, #769\t@ 0x301\n \tcmp.w\tr5, #536870912\t@ 0x20000000\n-\tstr\tr1, [r4, #68]\t@ 0x44\n-\tvstr\td11, [r4, #72]\t@ 0x48\n-\tstrh.w\tr9, [r4, #76]\t@ 0x4c\n-\tbge.w\t1afa <__gridxc_interpolation_MOD_generate_spline_master+0x6fe>\n-\tldr\tr0, [r7, #24]\n+\tstrd\tr3, r3, [r2, #4]\n+\tstr.w\tr9, [r4, #68]\t@ 0x44\n+\tstrh.w\tfp, [r4, #76]\t@ 0x4c\n+\tbge.w\t1b54 <__gridxc_interpolation_MOD_generate_spline_master+0x740>\n+\tldr\tr0, [r7, #56]\t@ 0x38\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tmovs\tr1, #8\n-\tmov\tfp, r0\n+\tmovs\tr3, #0\n+\tstr\tr0, [r7, #68]\t@ 0x44\n \tstr\tr0, [r4, #60]\t@ 0x3c\n \tcmp\tr0, #0\n-\tbeq.w\t1aec <__gridxc_interpolation_MOD_generate_spline_master+0x6f0>\n-\tvldr\td10, [pc, #460]\t@ 1b08 <__gridxc_interpolation_MOD_generate_spline_master+0x70c>\n-\tmovs\tr2, #1\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr1, [r4, #104]\t@ 0x68\n-\tstr\tr2, [r4, #88]\t@ 0x58\n-\tstr\tr3, [r4, #64]\t@ 0x40\n-\tvstr\td11, [r4, #108]\t@ 0x6c\n-\tldr\tr0, [r7, #24]\n+\tbeq.w\t1b46 <__gridxc_interpolation_MOD_generate_spline_master+0x732>\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstrd\tr3, r3, [r4, #108]\t@ 0x6c\n+\tstr\tr2, [r4, #64]\t@ 0x40\n+\tmov.w\tr8, #1\n+\tldr\tr0, [r7, #56]\t@ 0x38\n \tstr\tr5, [r4, #92]\t@ 0x5c\n-\tstrh.w\tr9, [r4, #112]\t@ 0x70\n-\tvstr\td10, [r4, #80]\t@ 0x50\n+\tstr.w\tr9, [r4, #80]\t@ 0x50\n+\tstrd\tr8, r8, [r4, #84]\t@ 0x54\n+\tstr.w\tr9, [r4, #104]\t@ 0x68\n+\tstrh.w\tfp, [r4, #112]\t@ 0x70\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmovs\tr2, #1\n-\tmovs\tr1, #8\n-\tstr\tr0, [r7, #32]\n+\tmovs\tr3, #0\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstr\tr0, [r7, #48]\t@ 0x30\n \tstr\tr0, [r4, #96]\t@ 0x60\n \tcmp\tr0, #0\n-\tbeq.w\t1ade <__gridxc_interpolation_MOD_generate_spline_master+0x6e2>\n-\tadd.w\tr0, r4, #116\t@ 0x74\n-\tstrd\tr2, r5, [r4, #124]\t@ 0x7c\n-\tstr\tr3, [r4, #100]\t@ 0x64\n-\tvst1.32\t{d10}, [r0]\n-\tvstr\td11, [r4, #144]\t@ 0x90\n-\tldr\tr0, [r7, #24]\n-\tstrh.w\tr9, [r4, #148]\t@ 0x94\n-\tstr.w\tr1, [r4, #140]\t@ 0x8c\n+\tbeq.w\t1b38 <__gridxc_interpolation_MOD_generate_spline_master+0x724>\n+\tstrd\tr3, r3, [r4, #144]\t@ 0x90\n+\tstr\tr2, [r4, #100]\t@ 0x64\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tstrd\tr8, r5, [r4, #124]\t@ 0x7c\n+\tstr.w\tr8, [r4, #120]\t@ 0x78\n+\tstr.w\tr9, [r4, #116]\t@ 0x74\n+\tstrh.w\tfp, [r4, #148]\t@ 0x94\n+\tstr.w\tr9, [r4, #140]\t@ 0x8c\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmov\tr9, r0\n-\tmovs\tr2, #1\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tmov\tr3, r0\n \tstr.w\tr0, [r4, #132]\t@ 0x84\n \tcmp\tr0, #0\n-\tbeq.w\t1ad0 <__gridxc_interpolation_MOD_generate_spline_master+0x6d4>\n-\tstr.w\tr3, [r4, #136]\t@ 0x88\n-\tldr\tr3, [r7, #20]\n-\tvldr\td18, [r6]\n-\tadd\tr3, r6\n-\tvldr\ts15, [r7, #8]\n-\tvldr\td20, [pc, #348]\t@ 1b10 <__gridxc_interpolation_MOD_generate_spline_master+0x714>\n-\tvstr\td18, [r4, #24]\n-\tvldr\td16, [r3]\n-\tvcvt.f64.s32\td17, s15\n-\tldrh\tr3, [r7, #40]\t@ 0x28\n-\tstrh\tr3, [r4, #0]\n-\tvsub.f64\td22, d16, d18\n-\tvminnm.f64\td19, d16, d18\n-\tvmaxnm.f64\td16, d16, d18\n-\tldrb.w\tr3, [r7, #42]\t@ 0x2a\n-\tstrb\tr3, [r4, #2]\n-\tldrb\tr3, [r4, #0]\n-\tvdiv.f64\td21, d22, d17\n-\tstr.w\tr2, [r4, #160]\t@ 0xa0\n-\tcmp\tr3, #108\t@ 0x6c\n+\tbeq.w\t1b2a <__gridxc_interpolation_MOD_generate_spline_master+0x716>\n+\tstr.w\tr2, [r4, #136]\t@ 0x88\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tvldr\ts15, [r7, #40]\t@ 0x28\n+\tadd\tr2, r6\n+\tvldr\td5, [r6]\n+\tvldr\td3, [r7, #8]\n+\tvcvt.f64.s32\td6, s15\n+\tvldr\td2, [pc, #376]\t@ 1b60 <__gridxc_interpolation_MOD_generate_spline_master+0x74c>\n+\tvldr\td7, [r2]\n+\tvstr\td3, [r4, #40]\t@ 0x28\n+\tldrh.w\tr2, [r7, #72]\t@ 0x48\n+\tvsub.f64\td4, d7, d5\n+\tvcmpe.f64\td7, d5\n+\tstrh\tr2, [r4, #0]\n+\tldrb.w\tr2, [r7, #74]\t@ 0x4a\n+\tstrb\tr2, [r4, #2]\n+\tvdiv.f64\td3, d4, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tldrb\tr2, [r4, #0]\n+\tstr.w\tr9, [r4, #152]\t@ 0x98\n+\tstrd\tr8, r8, [r4, #156]\t@ 0x9c\n \tstr.w\tr5, [r4, #164]\t@ 0xa4\n-\tvstr\td10, [r4, #152]\t@ 0x98\n-\tvstr\td8, [r4, #40]\t@ 0x28\n-\tvabs.f64\td18, d21\n-\tvstr\td21, [r4, #32]\n-\tvfms.f64\td19, d18, d20\n-\tvfma.f64\td16, d18, d20\n-\tvstr\td19, [r4, #8]\n-\tvstr\td16, [r4, #16]\n-\tbeq.n\t1a78 <__gridxc_interpolation_MOD_generate_spline_master+0x67c>\n-\tmov\tr1, r6\n-\tmov\tr2, r8\n-\tmov\tr0, fp\n+\tite\thi\n+\tvmovhi.f64\td4, d5\n+\tvmovls.f64\td4, d7\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvstr\td5, [r4, #24]\n+\tcmp\tr2, #108\t@ 0x6c\n+\tvabs.f64\td6, d3\n+\tvstr\td3, [r4, #32]\n+\tvmul.f64\td6, d6, d2\n+\tvsub.f64\td4, d4, d6\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td4, [r4, #8]\n+\tvstr\td7, [r4, #16]\n+\tbeq.n\t1ac6 <__gridxc_interpolation_MOD_generate_spline_master+0x6b2>\n \tstr\tr5, [r4, #56]\t@ 0x38\n+\tmov\tr1, r6\n+\tldr\tr4, [r7, #60]\t@ 0x3c\n+\tldr\tr0, [r7, #68]\t@ 0x44\n+\tmov\tr2, r4\n+\tstr\tr3, [r7, #56]\t@ 0x38\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tr2, r8\n+\tmov\tr2, r4\n \tmov\tr1, sl\n-\tldr\tr0, [r7, #32]\n+\tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr1, [r7, #36]\t@ 0x24\n-\tmov\tr2, r8\n-\tmov\tr0, r9\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tldr\tr1, [r7, #64]\t@ 0x40\n+\tmov\tr2, r4\n+\tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr.w\tsp, [r7, #4]\n-\tb.n\t1574 <__gridxc_interpolation_MOD_generate_spline_master+0x178>\n+\tldr.w\tsp, [r7, #36]\t@ 0x24\n+\tb.n\t1590 <__gridxc_interpolation_MOD_generate_spline_master+0x17c>\n \tcmp.w\tr8, #0\n-\tbeq.n\t1a38 <__gridxc_interpolation_MOD_generate_spline_master+0x63c>\n+\tbeq.n\t1a84 <__gridxc_interpolation_MOD_generate_spline_master+0x670>\n \tstr.w\tr2, [r8]\n-\tldr\tr3, [pc, #224]\t@ (1b1c <__gridxc_interpolation_MOD_generate_spline_master+0x720>)\n+\tldr\tr3, [pc, #236]\t@ (1b74 <__gridxc_interpolation_MOD_generate_spline_master+0x760>)\n \tmov.w\tfp, #0\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n-\tstrh\tr3, [r7, #40]\t@ 0x28\n+\tstrh.w\tr3, [r7, #72]\t@ 0x48\n \tlsrs\tr3, r3, #16\n-\tstrb.w\tr3, [r7, #42]\t@ 0x2a\n-\tcmp.w\tr9, #0\n-\tbne.w\t164e <__gridxc_interpolation_MOD_generate_spline_master+0x252>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvmov.f64\td21, d16\n-\tb.n\t1682 <__gridxc_interpolation_MOD_generate_spline_master+0x286>\n-\tvmov.i64\td18, #0x0000000000000000\n+\tstrb.w\tr3, [r7, #74]\t@ 0x4a\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tcmp\tr3, #0\n+\tbne.w\t1670 <__gridxc_interpolation_MOD_generate_spline_master+0x25c>\n+\tvldr\td7, [pc, #196]\t@ 1b68 <__gridxc_interpolation_MOD_generate_spline_master+0x754>\n+\tvmov.f64\td10, d7\n+\tb.n\t16a4 <__gridxc_interpolation_MOD_generate_spline_master+0x290>\n \tlsls\tr3, r1, #3\n-\tstr\tr3, [r7, #20]\n-\tadds\tr3, r2, r3\n-\tmov.w\tr8, r5, lsl #3\n-\tvmov.f64\td17, d18\n-\tvmov.f64\td16, d18\n-\tvstr\td18, [r3]\n-\tb.n\t16e8 <__gridxc_interpolation_MOD_generate_spline_master+0x2ec>\n-\tldrb\tr3, [r4, #1]\n-\tcmp\tr3, #111\t@ 0x6f\n-\tbne.n\t1a08 <__gridxc_interpolation_MOD_generate_spline_master+0x60c>\n-\tldrb\tr3, [r4, #2]\n-\tcmp\tr3, #103\t@ 0x67\n-\tbne.n\t1a08 <__gridxc_interpolation_MOD_generate_spline_master+0x60c>\n-\tvstr\td9, [r4, #48]\t@ 0x30\n-\tb.n\t1a08 <__gridxc_interpolation_MOD_generate_spline_master+0x60c>\n-\tvabs.f64\td16, d8\n-\tvcmpe.f64\td16, d19\n+\tvldr\td5, [pc, #184]\t@ 1b68 <__gridxc_interpolation_MOD_generate_spline_master+0x754>\n+\tstr\tr3, [r7, #52]\t@ 0x34\n+\tadd\tr3, r9\n+\tvmov.f64\td6, d5\n+\tvmov.f64\td7, d5\n+\tvstr\td5, [r3]\n+\tlsls\tr3, r5, #3\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tb.n\t1704 <__gridxc_interpolation_MOD_generate_spline_master+0x2f0>\n+\tldrb\tr2, [r4, #1]\n+\tcmp\tr2, #111\t@ 0x6f\n+\tbne.n\t1a4e <__gridxc_interpolation_MOD_generate_spline_master+0x63a>\n+\tldrb\tr2, [r4, #2]\n+\tcmp\tr2, #103\t@ 0x67\n+\tbne.n\t1a4e <__gridxc_interpolation_MOD_generate_spline_master+0x63a>\n+\tvldr\td7, [r7]\n+\tvstr\td7, [r4, #48]\t@ 0x30\n+\tb.n\t1a4e <__gridxc_interpolation_MOD_generate_spline_master+0x63a>\n+\tvldr\td7, [r7, #8]\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t1aa8 <__gridxc_interpolation_MOD_generate_spline_master+0x6ac>\n-\tldr\tr3, [pc, #132]\t@ (1b20 <__gridxc_interpolation_MOD_generate_spline_master+0x724>)\n+\tbpl.n\t1b00 <__gridxc_interpolation_MOD_generate_spline_master+0x6ec>\n+\tldr\tr3, [pc, #136]\t@ (1b78 <__gridxc_interpolation_MOD_generate_spline_master+0x764>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n-\tstrh\tr3, [r7, #40]\t@ 0x28\n+\tstrh.w\tr3, [r7, #72]\t@ 0x48\n \tlsrs\tr3, r3, #16\n-\tstrb.w\tr3, [r7, #42]\t@ 0x2a\n-\tb.n\t1646 <__gridxc_interpolation_MOD_generate_spline_master+0x24a>\n-\tldr\tr3, [pc, #120]\t@ (1b24 <__gridxc_interpolation_MOD_generate_spline_master+0x728>)\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tstrb.w\tr3, [r7, #74]\t@ 0x4a\n+\tb.n\t1668 <__gridxc_interpolation_MOD_generate_spline_master+0x254>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tldr\tr3, [pc, #116]\t@ (1b7c <__gridxc_interpolation_MOD_generate_spline_master+0x768>)\n+\tvsub.f64\td7, d10, d7\n \tadd\tr3, pc\n-\tvsub.f64\td12, d12, d16\n+\tvdiv.f64\td7, d11, d7\n+\tvstr\td7, [r7]\n \tldr\tr3, [r3, #0]\n-\tvdiv.f64\td9, d13, d12\n-\tstrh\tr3, [r7, #40]\t@ 0x28\n+\tstrh.w\tr3, [r7, #72]\t@ 0x48\n \tlsrs\tr3, r3, #16\n-\tstrb.w\tr3, [r7, #42]\t@ 0x2a\n-\tb.n\t1646 <__gridxc_interpolation_MOD_generate_spline_master+0x24a>\n-\tldr\tr3, [r7, #20]\n-\tb.n\t189a <__gridxc_interpolation_MOD_generate_spline_master+0x49e>\n+\tstrb.w\tr3, [r7, #74]\t@ 0x4a\n+\tb.n\t1668 <__gridxc_interpolation_MOD_generate_spline_master+0x254>\n \tmovs\tr1, #2\n-\tb.n\t17ea <__gridxc_interpolation_MOD_generate_spline_master+0x3ee>\n+\tb.n\t1816 <__gridxc_interpolation_MOD_generate_spline_master+0x402>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr1, [pc, #84]\t@ (1b28 <__gridxc_interpolation_MOD_generate_spline_master+0x72c>)\n-\tldr\tr0, [pc, #88]\t@ (1b2c <__gridxc_interpolation_MOD_generate_spline_master+0x730>)\n-\tldr\tr2, [r7, #24]\n+\tldr\tr1, [pc, #84]\t@ (1b80 <__gridxc_interpolation_MOD_generate_spline_master+0x76c>)\n+\tldr\tr0, [pc, #84]\t@ (1b84 <__gridxc_interpolation_MOD_generate_spline_master+0x770>)\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #80]\t@ (1b30 <__gridxc_interpolation_MOD_generate_spline_master+0x734>)\n-\tldr\tr0, [pc, #80]\t@ (1b34 <__gridxc_interpolation_MOD_generate_spline_master+0x738>)\n-\tldr\tr2, [r7, #24]\n+\tldr\tr1, [pc, #76]\t@ (1b88 <__gridxc_interpolation_MOD_generate_spline_master+0x774>)\n+\tldr\tr0, [pc, #80]\t@ (1b8c <__gridxc_interpolation_MOD_generate_spline_master+0x778>)\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #72]\t@ (1b38 <__gridxc_interpolation_MOD_generate_spline_master+0x73c>)\n-\tldr\tr0, [pc, #76]\t@ (1b3c <__gridxc_interpolation_MOD_generate_spline_master+0x740>)\n-\tldr\tr2, [r7, #24]\n+\tldr\tr1, [pc, #72]\t@ (1b90 <__gridxc_interpolation_MOD_generate_spline_master+0x77c>)\n+\tldr\tr0, [pc, #72]\t@ (1b94 <__gridxc_interpolation_MOD_generate_spline_master+0x780>)\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #68]\t@ (1b40 <__gridxc_interpolation_MOD_generate_spline_master+0x744>)\n+\tldr\tr0, [pc, #64]\t@ (1b98 <__gridxc_interpolation_MOD_generate_spline_master+0x784>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tnop\n \tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n \t.word\t0xa0b5ed8d\n \t.word\t0x3eb0c6f7\n-\t.word\t0x000004da\n+\t...\n+\t.word\t0x00000512\n R_ARM_REL32\t.LC5\n-\t.word\t0x000000da\n+\t.word\t0x000000e6\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000082\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000072\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC9\n-\t.word\t0x0000004e\n+\t.word\t0x0000004c\n R_ARM_REL32\t.LC11\n-\t.word\t0x00000050\n+\t.word\t0x0000004e\n R_ARM_REL32\t.LC12\n-\t.word\t0x00000048\n+\t.word\t0x00000046\n R_ARM_REL32\t.LC11\n-\t.word\t0x0000004a\n+\t.word\t0x00000048\n R_ARM_REL32\t.LC12\n-\t.word\t0x00000042\n+\t.word\t0x00000040\n R_ARM_REL32\t.LC11\n-\t.word\t0x00000044\n+\t.word\t0x00000042\n R_ARM_REL32\t.LC12\n-\t.word\t0x00000040\n+\t.word\t0x0000003e\n R_ARM_REL32\t.LC10\n \n-00001b44 <__gridxc_interpolation_MOD_generate_spline_x>:\n+00001b9c <__gridxc_interpolation_MOD_generate_spline_x>:\n __gridxc_interpolation_MOD_generate_spline_x.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3864]\t@ 0xf18\n \tmov\tr5, r3\n-\tvldr\td16, [pc, #288]\t@ 1c78 <__gridxc_interpolation_MOD_generate_spline_x+0x134>\n+\tvldr\td7, [pc, #288]\t@ 1cd0 <__gridxc_interpolation_MOD_generate_spline_x+0x134>\n \tsub\tsp, #208\t@ 0xd0\n-\tldr\tr4, [pc, #288]\t@ (1c80 <__gridxc_interpolation_MOD_generate_spline_x+0x13c>)\n+\tldr\tr4, [pc, #288]\t@ (1cd8 <__gridxc_interpolation_MOD_generate_spline_x+0x13c>)\n \tmov\tr3, r2\n-\tldr\tr2, [pc, #288]\t@ (1c84 <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n-\tvldr\td18, [r5]\n+\tldr\tr2, [pc, #288]\t@ (1cdc <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n+\tvldr\td5, [r5]\n \tadd\tr4, pc\n \tldr\tr6, [sp, #232]\t@ 0xe8\n \tldr\tr7, [sp, #236]\t@ 0xec\n-\tvcmpe.f64\td18, d16\n+\tvcmpe.f64\td5, d7\n \tldr\tr2, [r4, r2]\n \tldr.w\tr8, [r3]\n \tmovs\tr4, #0\n-\tvldr\td17, [r6]\n+\tvldr\td6, [r6]\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #204]\t@ 0xcc\n \tmov.w\tr2, #0\n \tmov\tr2, r1\n \tstr\tr4, [sp, #92]\t@ 0x5c\n \tvmrs\tAPSR_nzcv, fpscr\n \tstr\tr4, [sp, #128]\t@ 0x80\n-\tvcmpe.f64\td17, d16\n+\tvcmpe.f64\td6, d7\n \tstr\tr4, [sp, #164]\t@ 0xa4\n-\tble.n\t1c08 <__gridxc_interpolation_MOD_generate_spline_x+0xc4>\n+\tble.n\t1c60 <__gridxc_interpolation_MOD_generate_spline_x+0xc4>\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t1c56 <__gridxc_interpolation_MOD_generate_spline_x+0x112>\n+\tbgt.n\t1cae <__gridxc_interpolation_MOD_generate_spline_x+0x112>\n \tmov\tr1, r0\n-\tldr\tr0, [pc, #232]\t@ (1c88 <__gridxc_interpolation_MOD_generate_spline_x+0x144>)\n+\tldr\tr0, [pc, #232]\t@ (1ce0 <__gridxc_interpolation_MOD_generate_spline_x+0x144>)\n \tstrd\tr4, r6, [sp]\n \tadd\tr0, pc\n \tstr\tr7, [sp, #8]\n \tstr\tr0, [sp, #12]\n \tadd\tr0, sp, #28\n \tstr\tr0, [sp, #16]\n \tadd\tr0, sp, #32\n-\tbl\t13fc <__gridxc_interpolation_MOD_generate_spline_master>\n+\tbl\t1414 <__gridxc_interpolation_MOD_generate_spline_master>\n \tldr\tr3, [sp, #28]\n-\tcbz\tr3, 1bca <__gridxc_interpolation_MOD_generate_spline_x+0x86>\n+\tcbz\tr3, 1c22 <__gridxc_interpolation_MOD_generate_spline_x+0x86>\n \tcmp.w\tr8, #0\n-\tble.n\t1bca <__gridxc_interpolation_MOD_generate_spline_x+0x86>\n+\tble.n\t1c22 <__gridxc_interpolation_MOD_generate_spline_x+0x86>\n \tmov.w\tr2, r8, lsl #3\n \tmovs\tr1, #0\n \tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tldr\tr0, [sp, #92]\t@ 0x5c\n \tldr\tr4, [sp, #128]\t@ 0x80\n-\tcbz\tr0, 1c2a <__gridxc_interpolation_MOD_generate_spline_x+0xe6>\n+\tcbz\tr0, 1c82 <__gridxc_interpolation_MOD_generate_spline_x+0xe6>\n \tmovs\tr5, #0\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tstr\tr5, [sp, #92]\t@ 0x5c\n \tcmp\tr4, #0\n-\tbeq.n\t1c68 <__gridxc_interpolation_MOD_generate_spline_x+0x124>\n+\tbeq.n\t1cc0 <__gridxc_interpolation_MOD_generate_spline_x+0x124>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [sp, #164]\t@ 0xa4\n \tstr\tr5, [sp, #128]\t@ 0x80\n \tcmp\tr0, #0\n-\tbeq.n\t1c68 <__gridxc_interpolation_MOD_generate_spline_x+0x124>\n-\tldr\tr2, [pc, #160]\t@ (1c8c <__gridxc_interpolation_MOD_generate_spline_x+0x148>)\n-\tldr\tr3, [pc, #148]\t@ (1c84 <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n+\tbeq.n\t1cc0 <__gridxc_interpolation_MOD_generate_spline_x+0x124>\n+\tldr\tr2, [pc, #160]\t@ (1ce4 <__gridxc_interpolation_MOD_generate_spline_x+0x148>)\n+\tldr\tr3, [pc, #148]\t@ (1cdc <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #204]\t@ 0xcc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1c64 <__gridxc_interpolation_MOD_generate_spline_x+0x120>\n+\tbne.n\t1cbc <__gridxc_interpolation_MOD_generate_spline_x+0x120>\n \tadd\tsp, #208\t@ 0xd0\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t1c1c <__gridxc_interpolation_MOD_generate_spline_x+0xd8>\n+\tbgt.n\t1c74 <__gridxc_interpolation_MOD_generate_spline_x+0xd8>\n \tmov\tr1, r0\n-\tldr\tr0, [pc, #124]\t@ (1c90 <__gridxc_interpolation_MOD_generate_spline_x+0x14c>)\n+\tldr\tr0, [pc, #124]\t@ (1ce8 <__gridxc_interpolation_MOD_generate_spline_x+0x14c>)\n \tstrd\tr5, r6, [sp]\n \tadd\tr0, pc\n \tstr\tr7, [sp, #8]\n-\tb.n\t1ba8 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n+\tb.n\t1c00 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n \tmov\tr1, r0\n-\tldr\tr0, [pc, #116]\t@ (1c94 <__gridxc_interpolation_MOD_generate_spline_x+0x150>)\n+\tldr\tr0, [pc, #116]\t@ (1cec <__gridxc_interpolation_MOD_generate_spline_x+0x150>)\n \tstrd\tr5, r4, [sp]\n \tadd\tr0, pc\n \tstr\tr7, [sp, #8]\n-\tb.n\t1ba8 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n+\tb.n\t1c00 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n \tldr\tr5, [sp, #164]\t@ 0xa4\n-\tcbz\tr4, 1c34 <__gridxc_interpolation_MOD_generate_spline_x+0xf0>\n+\tcbz\tr4, 1c8c <__gridxc_interpolation_MOD_generate_spline_x+0xf0>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcbz\tr5, 1c3c <__gridxc_interpolation_MOD_generate_spline_x+0xf8>\n+\tcbz\tr5, 1c94 <__gridxc_interpolation_MOD_generate_spline_x+0xf8>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #88]\t@ (1c98 <__gridxc_interpolation_MOD_generate_spline_x+0x154>)\n-\tldr\tr3, [pc, #68]\t@ (1c84 <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n+\tldr\tr2, [pc, #88]\t@ (1cf0 <__gridxc_interpolation_MOD_generate_spline_x+0x154>)\n+\tldr\tr3, [pc, #68]\t@ (1cdc <__gridxc_interpolation_MOD_generate_spline_x+0x140>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #204]\t@ 0xcc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1c64 <__gridxc_interpolation_MOD_generate_spline_x+0x120>\n+\tbne.n\t1cbc <__gridxc_interpolation_MOD_generate_spline_x+0x120>\n \tadd\tsp, #208\t@ 0xd0\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n \tmov\tr1, r0\n-\tldr\tr0, [pc, #64]\t@ (1c9c <__gridxc_interpolation_MOD_generate_spline_x+0x158>)\n+\tldr\tr0, [pc, #64]\t@ (1cf4 <__gridxc_interpolation_MOD_generate_spline_x+0x158>)\n \tstrd\tr4, r7, [sp, #4]\n \tadd\tr0, pc\n \tstr\tr4, [sp, #0]\n-\tb.n\t1ba8 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n+\tb.n\t1c00 <__gridxc_interpolation_MOD_generate_spline_x+0x64>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr2, [pc, #52]\t@ (1ca0 <__gridxc_interpolation_MOD_generate_spline_x+0x15c>)\n-\tldr\tr1, [pc, #56]\t@ (1ca4 <__gridxc_interpolation_MOD_generate_spline_x+0x160>)\n-\tldr\tr0, [pc, #56]\t@ (1ca8 <__gridxc_interpolation_MOD_generate_spline_x+0x164>)\n+\tldr\tr2, [pc, #52]\t@ (1cf8 <__gridxc_interpolation_MOD_generate_spline_x+0x15c>)\n+\tldr\tr1, [pc, #56]\t@ (1cfc <__gridxc_interpolation_MOD_generate_spline_x+0x160>)\n+\tldr\tr0, [pc, #56]\t@ (1d00 <__gridxc_interpolation_MOD_generate_spline_x+0x164>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n \t.word\t0x9ce410a0\n \t.word\t0x4628fdb9\n@@ -2580,24 +2594,24 @@\n \t.word\t0x0000002e\n R_ARM_REL32\t.LC0\n \t.word\t0x00000030\n R_ARM_REL32\t.LC1\n \t.word\t0x00000032\n R_ARM_REL32\t.LC2\n \n-00001cac <__gridxc_interpolation_MOD_generate_spline_dx>:\n+00001d04 <__gridxc_interpolation_MOD_generate_spline_dx>:\n __gridxc_interpolation_MOD_generate_spline_dx():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr4, r2\n-\tldr\tr2, [pc, #256]\t@ (1dc0 <__gridxc_interpolation_MOD_generate_spline_dx+0x114>)\n+\tldr\tr2, [pc, #256]\t@ (1e18 <__gridxc_interpolation_MOD_generate_spline_dx+0x114>)\n \tmov\tfp, r3\n-\tldr\tr3, [pc, #256]\t@ (1dc4 <__gridxc_interpolation_MOD_generate_spline_dx+0x118>)\n+\tldr\tr3, [pc, #256]\t@ (1e1c <__gridxc_interpolation_MOD_generate_spline_dx+0x118>)\n \tadd\tr2, pc\n \tsub\tsp, #20\n \tldr.w\tlr, [r4]\n \tadd\tr7, sp, #8\n \tmov\tr5, r1\n \tldr\tr3, [r2, r3]\n \tmov\tr1, sp\n@@ -2607,90 +2621,90 @@\n \tbic.w\tr3, lr, lr, asr #31\n \tldrd\tr8, r9, [r7, #48]\t@ 0x30\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t1d04 <__gridxc_interpolation_MOD_generate_spline_dx+0x58>\n+\tbeq.n\t1d5c <__gridxc_interpolation_MOD_generate_spline_dx+0x58>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1cf6 <__gridxc_interpolation_MOD_generate_spline_dx+0x4a>\n+\tbne.n\t1d4e <__gridxc_interpolation_MOD_generate_spline_dx+0x4a>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.n\t1daa <__gridxc_interpolation_MOD_generate_spline_dx+0xfe>\n+\tbne.n\t1e02 <__gridxc_interpolation_MOD_generate_spline_dx+0xfe>\n \tadd\tr6, sp, #8\n \tmov\tsl, sp\n \tcmp.w\tlr, #0\n-\tble.n\t1d7c <__gridxc_interpolation_MOD_generate_spline_dx+0xd0>\n+\tble.n\t1dd4 <__gridxc_interpolation_MOD_generate_spline_dx+0xd0>\n \tmov.w\tr1, lr, lsl #3\n \tmov\tip, sp\n \tbic.w\tr3, r1, #4080\t@ 0xff0\n \tmov\tr2, r1\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tcmp\tip, r3\n-\tbeq.n\t1d40 <__gridxc_interpolation_MOD_generate_spline_dx+0x94>\n+\tbeq.n\t1d98 <__gridxc_interpolation_MOD_generate_spline_dx+0x94>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tip, sp\n \tcmp\tip, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1d32 <__gridxc_interpolation_MOD_generate_spline_dx+0x86>\n+\tbne.n\t1d8a <__gridxc_interpolation_MOD_generate_spline_dx+0x86>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 1d52 <__gridxc_interpolation_MOD_generate_spline_dx+0xa6>\n+\tcbz\tr1, 1daa <__gridxc_interpolation_MOD_generate_spline_dx+0xa6>\n \tsubs\tr1, #4\n \tadd.w\tr3, sp, r1\n \tstr\tr0, [r3, #0]\n \tadd\tr1, sp, #8\n-\tvldr\td17, [r0]\n+\tvldr\td6, [r0]\n \tmov\tip, r1\n \tmovs\tr0, #0\n \tvmov\ts15, r0\n \tmov\tr3, r0\n \tadds\tr3, #2\n \tadds\tr0, #1\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s15\n \tcmp\tlr, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tip!, {d16}\n-\tbge.n\t1d5c <__gridxc_interpolation_MOD_generate_spline_dx+0xb0>\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tip!, {d7}\n+\tbge.n\t1db4 <__gridxc_interpolation_MOD_generate_spline_dx+0xb0>\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmov\tsp, sl\n \tmov\tr3, fp\n \tmov\tr2, r4\n \tmov\tr1, r5\n \tmov\tr0, r6\n \tstrd\tr8, r9, [sp]\n-\tbl\t1b44 <__gridxc_interpolation_MOD_generate_spline_x>\n-\tldr\tr2, [pc, #56]\t@ (1dc8 <__gridxc_interpolation_MOD_generate_spline_dx+0x11c>)\n-\tldr\tr3, [pc, #48]\t@ (1dc4 <__gridxc_interpolation_MOD_generate_spline_dx+0x118>)\n+\tbl\t1b9c <__gridxc_interpolation_MOD_generate_spline_x>\n+\tldr\tr2, [pc, #56]\t@ (1e20 <__gridxc_interpolation_MOD_generate_spline_dx+0x11c>)\n+\tldr\tr3, [pc, #48]\t@ (1e1c <__gridxc_interpolation_MOD_generate_spline_dx+0x118>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #4]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1dbc <__gridxc_interpolation_MOD_generate_spline_dx+0x110>\n+\tbne.n\t1e14 <__gridxc_interpolation_MOD_generate_spline_dx+0x110>\n \tadds\tr7, #12\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr6, sp, #8\n \tmov\tsl, sp\n \tcmp.w\tlr, #0\n-\tble.n\t1d7c <__gridxc_interpolation_MOD_generate_spline_dx+0xd0>\n-\tb.n\t1d1a <__gridxc_interpolation_MOD_generate_spline_dx+0x6e>\n+\tble.n\t1dd4 <__gridxc_interpolation_MOD_generate_spline_dx+0xd0>\n+\tb.n\t1d72 <__gridxc_interpolation_MOD_generate_spline_dx+0x6e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0x000000f8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000032\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -9,62 +9,64 @@\n 0x00000060 6e5f4d4f 445f6765 6e657261 74655f73 n_MOD_generate_s\n 0x00000070 706c696e 655f6d61 73746572 2e6c6f63 pline_master.loc\n 0x00000080 616c616c 69617300 5f5f6772 69647863 alalias.__gridxc\n 0x00000090 5f696e74 6572706f 6c617469 6f6e5f4d _interpolation_M\n 0x000000a0 4f445f67 656e6572 6174655f 73706c69 OD_generate_spli\n 0x000000b0 6e655f78 2e6c6f63 616c616c 69617300 ne_x.localalias.\n 0x000000c0 6a756d70 7461626c 652e3130 382e3000 jumptable.108.0.\n- 0x000000d0 5f5f6772 69647863 5f696e74 6572706f __gridxc_interpo\n- 0x000000e0 6c617469 6f6e5f4d 4f445f5f 5f66696e lation_MOD___fin\n- 0x000000f0 616c5f67 72696478 635f696e 74657270 al_gridxc_interp\n- 0x00000100 6f6c6174 696f6e5f 53706c69 6e655f74 olation_Spline_t\n- 0x00000110 00667265 65005f5f 73746163 6b5f6368 .free.__stack_ch\n- 0x00000120 6b5f6661 696c005f 474c4f42 414c5f4f k_fail._GLOBAL_O\n- 0x00000130 46465345 545f5441 424c455f 005f5f73 FFSET_TABLE_.__s\n- 0x00000140 7461636b 5f63686b 5f677561 7264005f tack_chk_guard._\n- 0x00000150 5f677269 6478635f 696e7465 72706f6c _gridxc_interpol\n- 0x00000160 6174696f 6e5f4d4f 445f5f5f 636f7079 ation_MOD___copy\n- 0x00000170 5f677269 6478635f 696e7465 72706f6c _gridxc_interpol\n- 0x00000180 6174696f 6e5f5370 6c696e65 5f74006d ation_Spline_t.m\n- 0x00000190 656d6370 79006d61 6c6c6f63 005f5f67 emcpy.malloc.__g\n- 0x000001a0 72696478 635f696e 74657270 6f6c6174 ridxc_interpolat\n- 0x000001b0 696f6e5f 4d4f445f 636c6561 6e5f7370 ion_MOD_clean_sp\n- 0x000001c0 6c696e65 005f6766 6f727472 616e5f72 line._gfortran_r\n- 0x000001d0 756e7469 6d655f65 72726f72 5f617400 untime_error_at.\n- 0x000001e0 5f5f6772 69647863 5f696e74 6572706f __gridxc_interpo\n- 0x000001f0 6c617469 6f6e5f4d 4f445f70 6f6c696e lation_MOD_polin\n- 0x00000200 74006d65 6d736574 005f5f67 72696478 t.memset.__gridx\n- 0x00000210 635f7379 735f4d4f 445f6469 65005f5f c_sys_MOD_die.__\n- 0x00000220 67726964 78635f69 6e746572 706f6c61 gridxc_interpola\n- 0x00000230 74696f6e 5f4d4f44 5f657661 6c756174 tion_MOD_evaluat\n- 0x00000240 655f7370 6c696e65 5f647800 5f5f6772 e_spline_dx.__gr\n- 0x00000250 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n- 0x00000260 6f6e5f4d 4f445f65 76616c75 6174655f on_MOD_evaluate_\n- 0x00000270 73706c69 6e655f78 005f6766 6f727472 spline_x._gfortr\n- 0x00000280 616e5f73 656c6563 745f7374 72696e67 an_select_string\n- 0x00000290 006c6f67 00657870 005f5f67 72696478 .log.exp.__gridx\n- 0x000002a0 635f696e 74657270 6f6c6174 696f6e5f c_interpolation_\n- 0x000002b0 4d4f445f 6576616c 75617465 5f73706c MOD_evaluate_spl\n- 0x000002c0 696e655f 6e005f5f 67726964 78635f69 ine_n.__gridxc_i\n- 0x000002d0 6e746572 706f6c61 74696f6e 5f4d4f44 nterpolation_MOD\n- 0x000002e0 5f657661 6c756174 655f7370 6c696e65 _evaluate_spline\n- 0x000002f0 005f5f67 72696478 635f696e 74657270 .__gridxc_interp\n- 0x00000300 6f6c6174 696f6e5f 4d4f445f 67656e65 olation_MOD_gene\n- 0x00000310 72617465 5f73706c 696e655f 6d617374 rate_spline_mast\n- 0x00000320 6572005f 67666f72 7472616e 5f6f735f er._gfortran_os_\n- 0x00000330 6572726f 725f6174 005f6766 6f727472 error_at._gfortr\n- 0x00000340 616e5f72 756e7469 6d655f65 72726f72 an_runtime_error\n- 0x00000350 005f5f67 72696478 635f696e 74657270 .__gridxc_interp\n- 0x00000360 6f6c6174 696f6e5f 4d4f445f 67656e65 olation_MOD_gene\n- 0x00000370 72617465 5f73706c 696e655f 78005f5f rate_spline_x.__\n- 0x00000380 67726964 78635f69 6e746572 706f6c61 gridxc_interpola\n- 0x00000390 74696f6e 5f4d4f44 5f67656e 65726174 tion_MOD_generat\n- 0x000003a0 655f7370 6c696e65 5f647800 5f5f6772 e_spline_dx.__gr\n- 0x000003b0 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n- 0x000003c0 6f6e5f4d 4f445f5f 5f767461 625f6772 on_MOD___vtab_gr\n- 0x000003d0 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n- 0x000003e0 6f6e5f53 706c696e 655f7400 5f5f6772 on_Spline_t.__gr\n- 0x000003f0 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n- 0x00000400 6f6e5f4d 4f445f5f 5f646566 5f696e69 on_MOD___def_ini\n- 0x00000410 745f6772 69647863 5f696e74 6572706f t_gridxc_interpo\n- 0x00000420 6c617469 6f6e5f53 706c696e 655f7400 lation_Spline_t.\n+ 0x000000d0 5f5f6165 6162695f 69646976 6d6f6400 __aeabi_idivmod.\n+ 0x000000e0 5f5f6165 6162695f 69646976 005f5f67 __aeabi_idiv.__g\n+ 0x000000f0 72696478 635f696e 74657270 6f6c6174 ridxc_interpolat\n+ 0x00000100 696f6e5f 4d4f445f 5f5f6669 6e616c5f ion_MOD___final_\n+ 0x00000110 67726964 78635f69 6e746572 706f6c61 gridxc_interpola\n+ 0x00000120 74696f6e 5f53706c 696e655f 74006672 tion_Spline_t.fr\n+ 0x00000130 6565005f 5f737461 636b5f63 686b5f66 ee.__stack_chk_f\n+ 0x00000140 61696c00 5f5f7374 61636b5f 63686b5f ail.__stack_chk_\n+ 0x00000150 67756172 64005f47 4c4f4241 4c5f4f46 guard._GLOBAL_OF\n+ 0x00000160 46534554 5f544142 4c455f00 5f5f6772 FSET_TABLE_.__gr\n+ 0x00000170 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n+ 0x00000180 6f6e5f4d 4f445f5f 5f636f70 795f6772 on_MOD___copy_gr\n+ 0x00000190 69647863 5f696e74 6572706f 6c617469 idxc_interpolati\n+ 0x000001a0 6f6e5f53 706c696e 655f7400 6d656d63 on_Spline_t.memc\n+ 0x000001b0 7079006d 616c6c6f 63005f5f 67726964 py.malloc.__grid\n+ 0x000001c0 78635f69 6e746572 706f6c61 74696f6e xc_interpolation\n+ 0x000001d0 5f4d4f44 5f636c65 616e5f73 706c696e _MOD_clean_splin\n+ 0x000001e0 65005f67 666f7274 72616e5f 72756e74 e._gfortran_runt\n+ 0x000001f0 696d655f 6572726f 725f6174 005f5f67 ime_error_at.__g\n+ 0x00000200 72696478 635f696e 74657270 6f6c6174 ridxc_interpolat\n+ 0x00000210 696f6e5f 4d4f445f 706f6c69 6e74006d ion_MOD_polint.m\n+ 0x00000220 656d7365 74005f5f 67726964 78635f73 emset.__gridxc_s\n+ 0x00000230 79735f4d 4f445f64 6965005f 5f677269 ys_MOD_die.__gri\n+ 0x00000240 6478635f 696e7465 72706f6c 6174696f dxc_interpolatio\n+ 0x00000250 6e5f4d4f 445f6576 616c7561 74655f73 n_MOD_evaluate_s\n+ 0x00000260 706c696e 655f6478 005f5f67 72696478 pline_dx.__gridx\n+ 0x00000270 635f696e 74657270 6f6c6174 696f6e5f c_interpolation_\n+ 0x00000280 4d4f445f 6576616c 75617465 5f73706c MOD_evaluate_spl\n+ 0x00000290 696e655f 78005f67 666f7274 72616e5f ine_x._gfortran_\n+ 0x000002a0 73656c65 63745f73 7472696e 67006c6f select_string.lo\n+ 0x000002b0 67006578 70005f5f 67726964 78635f69 g.exp.__gridxc_i\n+ 0x000002c0 6e746572 706f6c61 74696f6e 5f4d4f44 nterpolation_MOD\n+ 0x000002d0 5f657661 6c756174 655f7370 6c696e65 _evaluate_spline\n+ 0x000002e0 5f6e005f 5f677269 6478635f 696e7465 _n.__gridxc_inte\n+ 0x000002f0 72706f6c 6174696f 6e5f4d4f 445f6576 rpolation_MOD_ev\n+ 0x00000300 616c7561 74655f73 706c696e 65005f5f aluate_spline.__\n+ 0x00000310 67726964 78635f69 6e746572 706f6c61 gridxc_interpola\n+ 0x00000320 74696f6e 5f4d4f44 5f67656e 65726174 tion_MOD_generat\n+ 0x00000330 655f7370 6c696e65 5f6d6173 74657200 e_spline_master.\n+ 0x00000340 5f67666f 72747261 6e5f6f73 5f657272 _gfortran_os_err\n+ 0x00000350 6f725f61 74005f67 666f7274 72616e5f or_at._gfortran_\n+ 0x00000360 72756e74 696d655f 6572726f 72005f5f runtime_error.__\n+ 0x00000370 67726964 78635f69 6e746572 706f6c61 gridxc_interpola\n+ 0x00000380 74696f6e 5f4d4f44 5f67656e 65726174 tion_MOD_generat\n+ 0x00000390 655f7370 6c696e65 5f78005f 5f677269 e_spline_x.__gri\n+ 0x000003a0 6478635f 696e7465 72706f6c 6174696f dxc_interpolatio\n+ 0x000003b0 6e5f4d4f 445f6765 6e657261 74655f73 n_MOD_generate_s\n+ 0x000003c0 706c696e 655f6478 005f5f67 72696478 pline_dx.__gridx\n+ 0x000003d0 635f696e 74657270 6f6c6174 696f6e5f c_interpolation_\n+ 0x000003e0 4d4f445f 5f5f7674 61625f67 72696478 MOD___vtab_gridx\n+ 0x000003f0 635f696e 74657270 6f6c6174 696f6e5f c_interpolation_\n+ 0x00000400 53706c69 6e655f74 005f5f67 72696478 Spline_t.__gridx\n+ 0x00000410 635f696e 74657270 6f6c6174 696f6e5f c_interpolation_\n+ 0x00000420 4d4f445f 5f5f6465 665f696e 69745f67 MOD___def_init_g\n+ 0x00000430 72696478 635f696e 74657270 6f6c6174 ridxc_interpolat\n+ 0x00000440 696f6e5f 53706c69 6e655f74 00 ion_Spline_t.\n \n"}]}, {"source1": "ldaxc.F90.o", "source2": "ldaxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 8192 (bytes into file)\n+ Start of section headers: 8596 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x2000:\n+There are 12 section headers, starting at offset 0x2194:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 001758 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 001dd0 0001c8 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 001790 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 001790 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 001790 000077 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 001808 000004 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 00180c 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 00180c 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 001840 000340 10 10 30 4\n- [10] .strtab STRTAB 00000000 001b80 000250 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 001f98 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0018f0 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 001f64 0001c8 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 001928 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 001928 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 001928 000077 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 0019a0 000004 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 0019a4 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0019a4 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 0019d4 000340 10 10 30 4\n+ [10] .strtab STRTAB 00000000 001d14 000250 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 00212c 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,48 +1,48 @@\n \n Symbol table '.symtab' contains 52 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 2: 00000230 0 NOTYPE LOCAL DEFAULT 1 $d\n- 3: 00000380 0 NOTYPE LOCAL DEFAULT 1 $t\n- 4: 000007b0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 5: 00000001 1992 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_pzxc.localalias\n- 6: 000007c8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 7: 00000ba8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 8: 000007c9 1248 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_pw92c.localalias\n- 9: 00000ca8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 00000e70 0 NOTYPE LOCAL DEFAULT 1 $d\n- 11: 00000ea8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 00001060 0 NOTYPE LOCAL DEFAULT 1 $d\n- 13: 00000ea9 496 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_exchng.localalias\n+ 2: 00000240 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 3: 00000390 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 4: 00000878 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 00000001 2208 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_pzxc.localalias\n+ 6: 000008a0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 7: 00000c58 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 8: 00000d78 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 9: 000008a1 1368 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_pw92c.localalias\n+ 10: 00000fd0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 11: 00001010 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 000011d8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 13: 00001011 520 FUNC LOCAL DEFAULT 1 __gridxc_lda_MOD_exchng.localalias\n 14: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 15: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 16: 00000020 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 17: 00000040 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 18: 00000044 0 NOTYPE LOCAL DEFAULT 5 .LC4\n 19: 00000048 0 NOTYPE LOCAL DEFAULT 5 .LC5\n 20: 0000004c 0 NOTYPE LOCAL DEFAULT 5 .LC6\n 21: 00000050 0 NOTYPE LOCAL DEFAULT 5 .LC7\n 22: 00000058 0 NOTYPE LOCAL DEFAULT 5 .LC8\n 23: 00000060 0 NOTYPE LOCAL DEFAULT 5 .LC9\n- 24: 00001098 0 NOTYPE LOCAL DEFAULT 1 $t\n- 25: 00001640 0 NOTYPE LOCAL DEFAULT 1 $d\n- 26: 00001680 0 NOTYPE LOCAL DEFAULT 1 $t\n- 27: 00001750 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 24: 00001218 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 25: 000015e8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 26: 00001620 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 27: 000018d8 0 NOTYPE LOCAL DEFAULT 1 $d\n 28: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 29: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 30: 00000001 1992 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pzxc\n+ 30: 00000001 2208 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pzxc\n 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n- 33: 000007c9 1248 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pw92c\n+ 33: 000008a1 1368 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pw92c\n 34: 00000000 0 NOTYPE GLOBAL DEFAULT UND pow\n- 35: 00000ca9 512 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pw92xc\n- 36: 00000ea9 496 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_exchng\n- 37: 00001099 1728 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_ldaxc\n+ 35: 00000df9 536 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_pw92xc\n+ 36: 00001011 520 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_exchng\n+ 37: 00001219 1752 FUNC GLOBAL DEFAULT 1 __gridxc_lda_MOD_ldaxc\n 38: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n 39: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n 40: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n 41: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_lda_exc_vxc_fxc\n 42: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n 43: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n 44: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,60 +1,60 @@\n \n-Relocation section '.rel.text' at offset 0x1dd0 contains 57 entries:\n+Relocation section '.rel.text' at offset 0x1f64 contains 57 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000004e 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-0000038c 0000200a R_ARM_THM_CALL 00000000 log\n-000006a8 0000200a R_ARM_THM_CALL 00000000 log\n-00000756 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000762 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-0000081c 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000854 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000868 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000908 0000220a R_ARM_THM_CALL 00000000 pow\n-00000968 0000200a R_ARM_THM_CALL 00000000 log\n-000009fc 0000200a R_ARM_THM_CALL 00000000 log\n-00000a8c 0000200a R_ARM_THM_CALL 00000000 log\n-00000b54 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000d00 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000d40 0000200a R_ARM_THM_CALL 00000000 log\n-00000dd2 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000dde 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000ef4 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000f32 0000200a R_ARM_THM_CALL 00000000 log\n-00000fb8 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00000fc4 00001f0a R_ARM_THM_CALL 00000000 cbrt\n-00001198 0000260a R_ARM_THM_CALL 00000000 memset\n-000011a2 0000260a R_ARM_THM_CALL 00000000 memset\n-000011ce 0000270a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-000011f0 0000280a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-00001210 0000290a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_lda_exc_vxc_fxc\n-000012b0 00002a0a R_ARM_THM_CALL 00000000 memcpy\n-0000131c 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000132e 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001340 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000149e 00002a0a R_ARM_THM_CALL 00000000 memcpy\n-000014aa 00002a0a R_ARM_THM_CALL 00000000 memcpy\n-00001574 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000158a 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000159c 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001648 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000164c 00002d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001650 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001654 00002e1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001658 00001003 R_ARM_REL32 00000020 .LC1\n-0000165c 00001c03 R_ARM_REL32 00000000 .rodata\n-00001660 00001103 R_ARM_REL32 00000040 .LC3\n-00001664 00001203 R_ARM_REL32 00000044 .LC4\n-00001668 00001303 R_ARM_REL32 00000048 .LC5\n-0000166c 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001670 00000f03 R_ARM_REL32 00000000 .LC0\n-00001674 00001403 R_ARM_REL32 0000004c .LC6\n-00001678 00001503 R_ARM_REL32 00000050 .LC7\n-0000167c 00001603 R_ARM_REL32 00000058 .LC8\n-000016fc 00002f0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000170e 0000300a R_ARM_THM_CALL 00000000 malloc\n-00001728 0000310a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00001732 0000320a R_ARM_THM_CALL 00000000 free\n-00001746 0000320a R_ARM_THM_CALL 00000000 free\n-0000174c 0000330a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001750 00001703 R_ARM_REL32 00000060 .LC9\n-00001754 00002e1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000052 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000398 0000200a R_ARM_THM_CALL 00000000 log\n+00000764 0000200a R_ARM_THM_CALL 00000000 log\n+00000816 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000822 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+000008fe 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000936 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+0000094a 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+000009e6 0000220a R_ARM_THM_CALL 00000000 pow\n+00000a2e 0000200a R_ARM_THM_CALL 00000000 log\n+00000ada 0000200a R_ARM_THM_CALL 00000000 log\n+00000b2e 0000200a R_ARM_THM_CALL 00000000 log\n+00000d9a 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000e50 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000e90 0000200a R_ARM_THM_CALL 00000000 log\n+00000f3a 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00000f46 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+0000105c 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+0000109a 0000200a R_ARM_THM_CALL 00000000 log\n+00001138 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00001144 00001f0a R_ARM_THM_CALL 00000000 cbrt\n+00001326 0000260a R_ARM_THM_CALL 00000000 memset\n+00001330 0000260a R_ARM_THM_CALL 00000000 memset\n+0000135c 0000270a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+0000137a 0000280a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+00001398 0000290a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_lda_exc_vxc_fxc\n+00001438 00002a0a R_ARM_THM_CALL 00000000 memcpy\n+000014a4 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000014b6 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000014c8 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000015f8 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000015fc 00002d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001600 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001604 00002e1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001608 00001003 R_ARM_REL32 00000020 .LC1\n+0000160c 00001c03 R_ARM_REL32 00000000 .rodata\n+00001610 00001103 R_ARM_REL32 00000040 .LC3\n+00001614 00001203 R_ARM_REL32 00000044 .LC4\n+00001618 00001303 R_ARM_REL32 00000048 .LC5\n+0000161c 00002c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001666 00002a0a R_ARM_THM_CALL 00000000 memcpy\n+00001672 00002a0a R_ARM_THM_CALL 00000000 memcpy\n+0000173c 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001752 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001764 00002b0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001882 00002f0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00001894 0000300a R_ARM_THM_CALL 00000000 malloc\n+000018ae 0000310a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000018b8 0000320a R_ARM_THM_CALL 00000000 free\n+000018cc 0000320a R_ARM_THM_CALL 00000000 free\n+000018d2 0000330a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000018d8 00002e1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000018dc 00000f03 R_ARM_REL32 00000000 .LC0\n+000018e0 00001403 R_ARM_REL32 0000004c .LC6\n+000018e4 00001503 R_ARM_REL32 00000050 .LC7\n+000018e8 00001603 R_ARM_REL32 00000058 .LC8\n+000018ec 00001703 R_ARM_REL32 00000060 .LC9\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -5,868 +5,951 @@\n \n 00000000 <__gridxc_lda_MOD_pzxc>:\n __gridxc_lda_MOD_pzxc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3952]\t@ 0xf70\n-\tsub\tsp, #48\t@ 0x30\n+\tstr.w\tr0, [ip, #3912]\t@ 0xf48\n+\tsub\tsp, #88\t@ 0x58\n \tldr\tr4, [r1, #0]\n \tmov\tr9, r0\n \tmov\tsl, r3\n-\tvldr\td12, [r2]\n+\tvldr\td9, [r2]\n \tcmp\tr4, #2\n-\tldr\tr6, [sp, #148]\t@ 0x94\n-\tldrd\tr5, r8, [sp, #152]\t@ 0x98\n-\tldr\tr7, [sp, #160]\t@ 0xa0\n-\tbeq.w\t61e <__gridxc_lda_MOD_pzxc+0x61e>\n-\tvmov.i64\td15, #0x0000000000000000\n-\tvcmpe.f64\td12, d15\n+\tldr\tr6, [sp, #188]\t@ 0xbc\n+\tldrd\tr5, r8, [sp, #192]\t@ 0xc0\n+\tldr\tr7, [sp, #200]\t@ 0xc8\n+\tbeq.w\t6be <__gridxc_lda_MOD_pzxc+0x6be>\n+\tvldr\td14, [pc, #824]\t@ 368 <__gridxc_lda_MOD_pzxc+0x368>\n+\tvcmpe.f64\td9, d14\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\t6f2 <__gridxc_lda_MOD_pzxc+0x6f2>\n-\tvmov.f64\td10, d15\n-\tvmov.f64\td9, d15\n-\tvmov.f64\td0, d12\n-\tvldr\td14, [pc, #484]\t@ 230 <__gridxc_lda_MOD_pzxc+0x230>\n+\tbls.w\t7a6 <__gridxc_lda_MOD_pzxc+0x7a6>\n+\tvstr\td14, [sp, #24]\n+\tvstr\td14, [sp, #16]\n+\tvstr\td14, [sp]\n+\tvmov.f64\td0, d9\n+\tvldr\td12, [pc, #496]\t@ 240 <__gridxc_lda_MOD_pzxc+0x240>\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td8, [pc, #480]\t@ 238 <__gridxc_lda_MOD_pzxc+0x238>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td8, [pc, #492]\t@ 248 <__gridxc_lda_MOD_pzxc+0x248>\n \tvmov.f64\td13, #104\t@ 0x3f400000 0.750\n-\tvdiv.f64\td18, d16, d0\n-\tvmul.f64\td14, d0, d14\n+\tvdiv.f64\td10, d7, d0\n+\tvmul.f64\td12, d0, d12\n \tldr.w\tr3, [r9]\n \tcmp\tr3, #1\n-\tvmul.f64\td13, d14, d13\n-\tvmul.f64\td8, d18, d8\n-\tbeq.w\t672 <__gridxc_lda_MOD_pzxc+0x672>\n-\tvldr\td16, [pc, #724]\t@ 350 <__gridxc_lda_MOD_pzxc+0x350>\n-\tvldr\td19, [pc, #448]\t@ 240 <__gridxc_lda_MOD_pzxc+0x240>\n-\tvdiv.f64\td23, d16, d12\n-\tvmul.f64\td16, d14, d16\n-\tvcmpe.f64\td18, d19\n-\tvdiv.f64\td21, d16, d12\n+\tvmul.f64\td13, d12, d13\n+\tvmul.f64\td8, d10, d8\n+\tbeq.w\t73a <__gridxc_lda_MOD_pzxc+0x73a>\n+\tvldr\td7, [pc, #736]\t@ 360 <__gridxc_lda_MOD_pzxc+0x360>\n+\tvldr\td6, [pc, #460]\t@ 250 <__gridxc_lda_MOD_pzxc+0x250>\n+\tvdiv.f64\td11, d7, d9\n+\tvmul.f64\td7, d12, d7\n+\tvcmpe.f64\td10, d6\n+\tvdiv.f64\td7, d7, d9\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvneg.f64\td20, d23\n-\tble.w\t380 <__gridxc_lda_MOD_pzxc+0x380>\n-\tvsqrt.f64\td19, d8\n-\tvmov.f64\td22, #112\t@ 0x3f800000 1.0\n-\tvldr\td16, [pc, #416]\t@ 248 <__gridxc_lda_MOD_pzxc+0x248>\n+\tvneg.f64\td11, d11\n+\tvstr\td7, [sp, #8]\n+\tble.w\t390 <__gridxc_lda_MOD_pzxc+0x390>\n+\tvsqrt.f64\td5, d8\n+\tvldr\td7, [pc, #428]\t@ 258 <__gridxc_lda_MOD_pzxc+0x258>\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvldr\td3, [pc, #428]\t@ 260 <__gridxc_lda_MOD_pzxc+0x260>\n+\tvldr\td6, [pc, #432]\t@ 268 <__gridxc_lda_MOD_pzxc+0x268>\n \tcmp\tr4, #2\n-\tvmov.f64\td18, d22\n-\tvldr\td26, [pc, #416]\t@ 250 <__gridxc_lda_MOD_pzxc+0x250>\n-\tvldr\td28, [pc, #420]\t@ 258 <__gridxc_lda_MOD_pzxc+0x258>\n-\tvmov.f64\td31, d22\n-\tvfma.f64\td18, d8, d16\n-\tvldr\td30, [pc, #416]\t@ 260 <__gridxc_lda_MOD_pzxc+0x260>\n-\tvldr\td24, [pc, #420]\t@ 268 <__gridxc_lda_MOD_pzxc+0x268>\n-\tvmov.f64\td6, d22\n-\tvfma.f64\td31, d8, d28\n-\tvldr\td25, [pc, #416]\t@ 270 <__gridxc_lda_MOD_pzxc+0x270>\n-\tvldr\td29, [pc, #420]\t@ 278 <__gridxc_lda_MOD_pzxc+0x278>\n-\tvfma.f64\td6, d8, d24\n-\tvldr\td27, [pc, #420]\t@ 280 <__gridxc_lda_MOD_pzxc+0x280>\n-\tvldr\td7, [pc, #424]\t@ 288 <__gridxc_lda_MOD_pzxc+0x288>\n-\tvfma.f64\td18, d19, d26\n-\tvmul.f64\td30, d19, d30\n-\tvfma.f64\td30, d8, d24\n-\tvfma.f64\td6, d19, d25\n-\tvmul.f64\td29, d19, d29\n-\tvfma.f64\td29, d8, d16\n-\tvmov.f64\td16, d22\n-\tvfma.f64\td16, d8, d27\n-\tvdiv.f64\td24, d22, d18\n-\tvldr\td18, [pc, #392]\t@ 290 <__gridxc_lda_MOD_pzxc+0x290>\n-\tvfma.f64\td16, d19, d7\n-\tvadd.f64\td26, d6, d6\n-\tvfma.f64\td31, d19, d18\n-\tvmul.f64\td29, d29, d20\n-\tvldr\td18, [pc, #380]\t@ 298 <__gridxc_lda_MOD_pzxc+0x298>\n-\tvdiv.f64\td25, d22, d31\n-\tvldr\td22, [pc, #380]\t@ 2a0 <__gridxc_lda_MOD_pzxc+0x2a0>\n-\tvmul.f64\td22, d19, d22\n-\tvfma.f64\td22, d8, d28\n-\tvmul.f64\td22, d22, d20\n-\tvadd.f64\td20, d16, d16\n-\tvmul.f64\td26, d26, d24\n-\tvmul.f64\td6, d6, d24\n-\tvmul.f64\td7, d26, d29\n-\tvfma.f64\td7, d30, d23\n-\tvmul.f64\td26, d25, d25\n-\tvmul.f64\td20, d20, d25\n-\tvmul.f64\td16, d16, d25\n-\tvmul.f64\td26, d26, d18\n-\tvmul.f64\td20, d20, d22\n-\tvnmul.f64\td18, d18, d25\n-\tvmul.f64\td25, d26, d22\n-\tvldr\td22, [pc, #324]\t@ 2a8 <__gridxc_lda_MOD_pzxc+0x2a8>\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td19, d19, d22\n-\tvfma.f64\td19, d8, d27\n-\tvfma.f64\td20, d19, d23\n-\tvmul.f64\td23, d24, d24\n-\tvmul.f64\td19, d26, d20\n-\tvldr\td20, [pc, #304]\t@ 2b0 <__gridxc_lda_MOD_pzxc+0x2b0>\n-\tvmul.f64\td23, d23, d20\n-\tvnmul.f64\td20, d20, d24\n-\tvmul.f64\td28, d23, d7\n-\tvmul.f64\td6, d6, d20\n-\tvmul.f64\td23, d23, d29\n-\tbeq.w\t46a <__gridxc_lda_MOD_pzxc+0x46a>\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvmul.f64\td2, d8, d7\n+\tvldr\td7, [pc, #432]\t@ 270 <__gridxc_lda_MOD_pzxc+0x270>\n+\tvmul.f64\td1, d8, d7\n+\tvadd.f64\td7, d2, d4\n+\tvmov.f64\td15, d2\n+\tvmov.f64\td14, d1\n+\tvmla.f64\td7, d5, d3\n+\tvldr\td3, [pc, #416]\t@ 278 <__gridxc_lda_MOD_pzxc+0x278>\n+\tvdiv.f64\td0, d4, d7\n+\tvadd.f64\td7, d1, d4\n+\tvmla.f64\td7, d5, d6\n+\tvldr\td6, [pc, #408]\t@ 280 <__gridxc_lda_MOD_pzxc+0x280>\n+\tvldr\td1, [pc, #412]\t@ 288 <__gridxc_lda_MOD_pzxc+0x288>\n+\tvmul.f64\td6, d8, d6\n+\tvadd.f64\td2, d6, d4\n+\tvdiv.f64\td10, d4, d7\n+\tvldr\td7, [pc, #404]\t@ 290 <__gridxc_lda_MOD_pzxc+0x290>\n+\tvmla.f64\td2, d5, d1\n+\tvmul.f64\td7, d8, d7\n+\tvmov.f64\td8, d15\n+\tvadd.f64\td1, d7, d4\n+\tvldr\td4, [pc, #392]\t@ 298 <__gridxc_lda_MOD_pzxc+0x298>\n+\tvmla.f64\td1, d5, d3\n+\tvldr\td3, [pc, #392]\t@ 2a0 <__gridxc_lda_MOD_pzxc+0x2a0>\n+\tvmla.f64\td6, d5, d4\n+\tvmov.f64\td4, d14\n+\tvmla.f64\td8, d5, d3\n+\tvldr\td3, [pc, #384]\t@ 2a8 <__gridxc_lda_MOD_pzxc+0x2a8>\n+\tvmla.f64\td4, d5, d3\n+\tvmul.f64\td6, d6, d11\n+\tvmul.f64\td8, d8, d11\n+\tvmul.f64\td14, d4, d11\n+\tvldr\td4, [pc, #372]\t@ 2b0 <__gridxc_lda_MOD_pzxc+0x2b0>\n+\tvmla.f64\td7, d5, d4\n+\tvadd.f64\td5, d2, d2\n+\tvldr\td4, [pc, #368]\t@ 2b8 <__gridxc_lda_MOD_pzxc+0x2b8>\n+\tvmul.f64\td2, d2, d0\n+\tvmul.f64\td5, d5, d0\n+\tvmul.f64\td15, d1, d10\n+\tvnmls.f64\td6, d5, d8\n+\tvmul.f64\td11, d7, d11\n+\tvmul.f64\td5, d0, d0\n+\tvldr\td7, [pc, #348]\t@ 2c0 <__gridxc_lda_MOD_pzxc+0x2c0>\n+\tvmul.f64\td5, d5, d7\n+\tvnmul.f64\td7, d7, d0\n+\tvmov.f64\td3, d6\n+\tvadd.f64\td6, d1, d1\n+\tvmul.f64\td1, d5, d8\n+\tvmul.f64\td6, d6, d10\n+\tvmul.f64\td3, d3, d5\n+\tvmul.f64\td5, d2, d7\n+\tvnmls.f64\td11, d6, d14\n+\tvmul.f64\td6, d10, d10\n+\tvmul.f64\td6, d6, d4\n+\tvnmul.f64\td4, d4, d10\n+\tvmul.f64\td2, d11, d6\n+\tvmul.f64\td10, d6, d14\n+\tvmul.f64\td6, d15, d4\n+\tbeq.w\t47e <__gridxc_lda_MOD_pzxc+0x47e>\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tvstr\td5, [r5]\n \tcmp\tr4, #0\n-\tvstr\td14, [r6]\n-\tvmul.f64\td13, d13, d16\n-\tvmul.f64\td20, d20, d16\n-\tvstr\td6, [r5]\n-\tvstr\td21, [r8]\n-\tvstr\td28, [r7]\n+\tvmul.f64\td13, d13, d6\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td5, [sp, #8]\n+\tvstr\td12, [r6]\n+\tvstr\td3, [r7]\n+\tvstr\td5, [r8]\n \tvstr\td13, [sl]\n-\tvstr\td20, [r3]\n-\tble.n\t220 <__gridxc_lda_MOD_pzxc+0x220>\n+\tvstr\td7, [r3]\n+\tble.n\t230 <__gridxc_lda_MOD_pzxc+0x230>\n \tmov\tlr, r5\n \tadd.w\tip, r4, #1\n \tlsls\tr0, r4, #3\n \tmov\tr5, r7\n \tmovs\tr4, #1\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td17, [r6]\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td6, [r6]\n \tmov\tr2, r5\n-\tvldr\td16, [lr]\n+\tvldr\td7, [lr]\n \tmov\tr3, r8\n \tmovs\tr1, #1\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvstmia\tr6!, {d17}\n-\tvstmia\tlr!, {d16}\n-\tvldr\td17, [r3]\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d5\n+\tvstmia\tr6!, {d6}\n+\tvstmia\tlr!, {d7}\n+\tvldr\td6, [r3]\n \tadds\tr1, #1\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tcmp\tr1, ip\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td17, [r3]\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td6, [r3]\n \tadd\tr3, r0\n-\tvstr\td16, [r2]\n+\tvstr\td7, [r2]\n \tadd\tr2, r0\n-\tbne.n\t1f2 <__gridxc_lda_MOD_pzxc+0x1f2>\n+\tbne.n\t202 <__gridxc_lda_MOD_pzxc+0x202>\n \tadds\tr4, #1\n \tadd.w\tr8, r8, #8\n \tadds\tr5, #8\n \tcmp\tr4, ip\n-\tbne.n\t1d4 <__gridxc_lda_MOD_pzxc+0x1d4>\n-\tadd\tsp, #48\t@ 0x30\n+\tbne.n\t1e4 <__gridxc_lda_MOD_pzxc+0x1e4>\n+\tadd\tsp, #88\t@ 0x58\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n \tnop\n \tnop.w\n \t.word\t0xfdf6d26d\n \t.word\t0xbfff8307\n \t.word\t0x45cf0e15\n \t.word\t0x3fe3d9e9\n \t.word\t0x133ea76a\n \t.word\t0x3ff9cab8\n \t.word\t0xf41f212d\n \t.word\t0x3fd5566c\n \t.word\t0xab9f559b\n \t.word\t0x3ff0d8ad\n+\t.word\t0x1b089a02\n+\t.word\t0x3ff65e9e\n \t.word\t0xc63f1412\n \t.word\t0x3fd0b5dc\n-\t.word\t0x4839e3e0\n-\t.word\t0x3fe3a775\n+\t.word\t0xca34b3ad\n+\t.word\t0x3ffa190d\n \t.word\t0xf0298191\n \t.word\t0x3fdc733b\n \t.word\t0x4839e3e0\n \t.word\t0x3ff3a775\n-\t.word\t0xab9f559b\n-\t.word\t0x3fe0d8ad\n \t.word\t0x08541ac3\n \t.word\t0x3fd647d1\n-\t.word\t0xca34b3ad\n-\t.word\t0x3ffa190d\n-\t.word\t0x1b089a02\n-\t.word\t0x3ff65e9e\n-\t.word\t0x4f0d844d\n-\t.word\t0x3fc594af\n+\t.word\t0x4839e3e0\n+\t.word\t0x3fe3a775\n+\t.word\t0xab9f559b\n+\t.word\t0x3fe0d8ad\n \t.word\t0x1b089a02\n \t.word\t0x3fe65e9e\n \t.word\t0xca34b3ad\n \t.word\t0x3fea190d\n+\t.word\t0x4f0d844d\n+\t.word\t0x3fc594af\n \t.word\t0xeb1c432d\n \t.word\t0x3fd236e2\n+\t.word\t0x09f788f2\n+\t.word\t0xbf784d8d\n \t.word\t0xab9f559b\n \t.word\t0x3fafd8ad\n-\t.word\t0xe399df81\n-\t.word\t0xbf8cf1ef\n-\t.word\t0xc3ece2a5\n-\t.word\t0x3f65d867\n-\t.word\t0x5e9e1b08\n-\t.word\t0xbf80cb29\n \t.word\t0x8db8bac7\n \t.word\t0x3f56f006\n+\t.word\t0xc3ece2a5\n+\t.word\t0x3f65d867\n \t.word\t0xd2f1a9fc\n \t.word\t0x3f70624d\n+\t.word\t0x5e9e1b08\n+\t.word\t0xbf80cb29\n+\t.word\t0xab9f559b\n+\t.word\t0x3f9fd8ad\n+\t.word\t0x30553261\n+\t.word\t0xbf93a92a\n+\t.word\t0xe399df81\n+\t.word\t0xbf8cf1ef\n \t.word\t0x124ba3b4\n \t.word\t0x3f4e955e\n+\t.word\t0xa5119ce0\n+\t.word\t0x3f97c1bd\n+\t.word\t0xcc40fd68\n+\t.word\t0x3f7c2038\n+\t.word\t0x06d3a06d\n+\t.word\t0xbfb06d3a\n+\t.word\t0x710cb296\n+\t.word\t0xbfab8bac\n+\t.word\t0x30553261\n+\t.word\t0x3f83a92a\n \t.word\t0x59050d3f\n \t.word\t0xbfbde23c\n \t.word\t0xea4a8c15\n \t.word\t0x3f913404\n-\t.word\t0x710cb296\n-\t.word\t0xbfab8bac\n \t.word\t0xbc6a7efa\n \t.word\t0xbfb89374\n-\t.word\t0x06d3a06d\n-\t.word\t0xbfb06d3a\n \t.word\t0xf98d728b\n \t.word\t0x3ff428a2\n-\t.word\t0x30553261\n-\t.word\t0x3f83a92a\n-\t.word\t0xcc40fd68\n-\t.word\t0x3f7c2038\n-\t.word\t0xa5119ce0\n-\t.word\t0x3f97c1bd\n-\t.word\t0xab9f559b\n-\t.word\t0x3f9fd8ad\n-\t.word\t0x09f788f2\n-\t.word\t0xbf784d8d\n-\t.word\t0x30553261\n-\t.word\t0xbf93a92a\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n+\t...\n \t.word\t0xdf98f597\n \t.word\t0x4009da35\n+\t.word\t0xea65f90f\n+\t.word\t0x3fe13c23\n \t.word\t0xc12a7cba\n \t.word\t0x3f073b49\n \t.word\t0x488a0ed6\n \t.word\t0x3f971c09\n-\t.word\t0xea65f90f\n-\t.word\t0x3fe13c23\n-\t.word\t0xdf98f597\n-\t.word\t0xc009da35\n \tvmov.f64\td0, d8\n-\tvstr\td20, [sp, #16]\n-\tvstr\td21, [sp, #8]\n+\tvldr\td15, [pc, #-208]\t@ 2c8 <__gridxc_lda_MOD_pzxc+0x2c8>\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td29, [pc, #-220]\t@ 2b8 <__gridxc_lda_MOD_pzxc+0x2b8>\n+\tvldr\td7, [pc, #-208]\t@ 2d0 <__gridxc_lda_MOD_pzxc+0x2d0>\n+\tvldr\td1, [pc, #-156]\t@ 308 <__gridxc_lda_MOD_pzxc+0x308>\n \tcmp\tr4, #2\n-\tvldr\td27, [pc, #-216]\t@ 2c0 <__gridxc_lda_MOD_pzxc+0x2c0>\n-\tvldr\td26, [pc, #-84]\t@ 348 <__gridxc_lda_MOD_pzxc+0x348>\n-\tvmov.f64\td28, d29\n-\tvldr\td16, [pc, #-108]\t@ 338 <__gridxc_lda_MOD_pzxc+0x338>\n-\tvfma.f64\td28, d8, d27\n-\tvmov.f64\td27, d29\n-\tvfma.f64\td27, d8, d26\n-\tvldr\td25, [pc, #-116]\t@ 340 <__gridxc_lda_MOD_pzxc+0x340>\n-\tvldr\td24, [pc, #-232]\t@ 2d0 <__gridxc_lda_MOD_pzxc+0x2d0>\n-\tvmov.f64\td26, d16\n-\tvldr\td23, [pc, #-248]\t@ 2c8 <__gridxc_lda_MOD_pzxc+0x2c8>\n-\tvmov.f64\td31, d29\n-\tvfma.f64\td26, d8, d25\n-\tvmov.f64\td25, d16\n-\tvfma.f64\td25, d8, d24\n-\tvmul.f64\td24, d8, d0\n-\tvldr\td18, [pc, #-240]\t@ 2e8 <__gridxc_lda_MOD_pzxc+0x2e8>\n-\tvfma.f64\td29, d8, d23\n-\tvldr\td22, [pc, #-256]\t@ 2e0 <__gridxc_lda_MOD_pzxc+0x2e0>\n-\tvldr\td19, [pc, #-268]\t@ 2d8 <__gridxc_lda_MOD_pzxc+0x2d8>\n-\tvfma.f64\td28, d24, d23\n-\tvmov.f64\td23, d27\n-\tvmov.f64\td27, d16\n-\tvfma.f64\td16, d8, d18\n-\tvfma.f64\td23, d24, d22\n-\tvfma.f64\td26, d24, d18\n-\tvfma.f64\td25, d24, d19\n-\tvldr\td18, [pc, #-220]\t@ 328 <__gridxc_lda_MOD_pzxc+0x328>\n-\tvldr\td20, [sp, #16]\n-\tvfma.f64\td31, d8, d22\n-\tvfma.f64\td27, d8, d19\n-\tvldr\td30, [pc, #-228]\t@ 330 <__gridxc_lda_MOD_pzxc+0x330>\n-\tvldr\td22, [pc, #-248]\t@ 320 <__gridxc_lda_MOD_pzxc+0x320>\n-\tvldr\td6, [pc, #-300]\t@ 2f0 <__gridxc_lda_MOD_pzxc+0x2f0>\n-\tvmul.f64\td28, d28, d20\n-\tvldr\td21, [sp, #8]\n-\tvmov.f64\td24, d16\n-\tvldr\td16, [pc, #-284]\t@ 310 <__gridxc_lda_MOD_pzxc+0x310>\n-\tvfms.f64\td16, d8, d18\n-\tvldr\td18, [pc, #-316]\t@ 2f8 <__gridxc_lda_MOD_pzxc+0x2f8>\n-\tvmul.f64\td23, d23, d20\n-\tvmul.f64\td19, d26, d20\n-\tvmul.f64\td25, d25, d20\n-\tvldr\td20, [pc, #-316]\t@ 308 <__gridxc_lda_MOD_pzxc+0x308>\n-\tvfms.f64\td6, d8, d18\n-\tvldr\td18, [pc, #-332]\t@ 300 <__gridxc_lda_MOD_pzxc+0x300>\n-\tvfms.f64\td20, d8, d30\n-\tvfms.f64\td18, d8, d22\n-\tvfma.f64\td16, d24, d0\n-\tvfma.f64\td6, d29, d0\n-\tvfma.f64\td20, d31, d0\n-\tvfma.f64\td18, d27, d0\n-\tbne.w\t19a <__gridxc_lda_MOD_pzxc+0x19a>\n-\tvmov.f64\td26, #112\t@ 0x3f800000 1.0\n-\tvldr\td22, [pc, #-344]\t@ 318 <__gridxc_lda_MOD_pzxc+0x318>\n-\tvmov.f64\td29, d14\n-\tvldr\td17, [sp]\n-\tvdiv.f64\td27, d26, d12\n-\tvldr\td7, [sp, #24]\n-\tvfnms.f64\td29, d14, d22\n-\tvsub.f64\td16, d16, d6\n-\tvsub.f64\td24, d18, d20\n-\tvmov.f64\td8, d20\n-\tvsub.f64\td19, d19, d28\n-\tvadd.f64\td30, d17, d17\n-\tvmov.f64\td17, d13\n-\tvmov.f64\td0, d13\n-\tvfma.f64\td6, d16, d9\n-\tvsub.f64\td16, d16, d18\n-\tvsub.f64\td18, d20, d18\n-\tvfnms.f64\td17, d13, d22\n-\tvfma.f64\td28, d19, d9\n-\tvsub.f64\td19, d25, d23\n-\tvsub.f64\td23, d23, d25\n-\tvmov.f64\td25, d14\n-\tvadd.f64\td16, d16, d20\n-\tvfms.f64\td25, d14, d22\n-\tvmov.f64\td20, d29\n-\tvfma.f64\td14, d29, d9\n-\tvfms.f64\td20, d13, d22\n-\tvfma.f64\td8, d24, d9\n-\tvadd.f64\td11, d11, d11\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tvmov.f64\td3, d6\n-\tvmul.f64\td16, d16, d10\n-\tvfma.f64\td0, d17, d9\n-\tvmov.f64\td5, d14\n-\tvadd.f64\td20, d20, d13\n-\tvfms.f64\td13, d13, d22\n-\tvldr\td22, [pc, #-428]\t@ 350 <__gridxc_lda_MOD_pzxc+0x350>\n-\tvmul.f64\td22, d9, d22\n-\tvmul.f64\td20, d20, d10\n-\tvmul.f64\td22, d22, d27\n-\tvfma.f64\td21, d29, d22\n-\tvsub.f64\td22, d26, d15\n-\tvadd.f64\td26, d15, d26\n-\tvmul.f64\td31, d26, d10\n-\tvmul.f64\td26, d26, d7\n-\tvmul.f64\td7, d22, d7\n-\tvmul.f64\td22, d22, d10\n-\tvfma.f64\td6, d31, d18\n-\tvfma.f64\td14, d31, d13\n-\tvfma.f64\td5, d17, d22\n-\tvfma.f64\td3, d24, d22\n-\tvmul.f64\td17, d17, d7\n-\tvmul.f64\td7, d24, d7\n-\tvmov.f64\td24, #80\t@ 0x3e800000 0.250\n-\tvmul.f64\td13, d13, d26\n-\tvmul.f64\td26, d18, d26\n-\tvmul.f64\td18, d27, d27\n-\tvmul.f64\td24, d27, d24\n-\tvmul.f64\td27, d11, d18\n-\tvmul.f64\td18, d30, d18\n-\tvstr\td5, [r6]\n-\tvmul.f64\td5, d22, d24\n-\tvmul.f64\td24, d31, d24\n-\tvstr\td3, [r5]\n-\tvmov.f64\td3, d21\n-\tvstr\td6, [r5, #8]\n-\tvfma.f64\td3, d20, d27\n-\tvfms.f64\td21, d18, d20\n-\tvmul.f64\td6, d27, d17\n-\tvmul.f64\td4, d27, d13\n-\tvmul.f64\td1, d27, d26\n-\tvmov.f64\td20, d28\n-\tvnmul.f64\td17, d18, d17\n-\tvnmul.f64\td13, d13, d18\n-\tvmul.f64\td30, d27, d7\n-\tvnmul.f64\td2, d18, d7\n-\tvnmul.f64\td26, d26, d18\n-\tvfma.f64\td20, d27, d16\n-\tvfms.f64\td28, d18, d16\n-\tvfma.f64\td1, d31, d23\n-\tvfma.f64\td26, d31, d23\n-\tvfma.f64\td6, d29, d5\n-\tvfma.f64\td17, d29, d5\n-\tvfma.f64\td4, d25, d24\n-\tvfma.f64\td13, d25, d24\n-\tvfma.f64\td30, d22, d19\n-\tvfma.f64\td2, d22, d19\n-\tvstr\td14, [r6, #8]\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tvadd.f64\td6, d3, d6\n-\tvadd.f64\td17, d21, d17\n-\tvmul.f64\td0, d0, d23\n-\tvadd.f64\td30, d20, d30\n-\tvadd.f64\td3, d3, d4\n-\tvadd.f64\td16, d28, d2\n-\tvadd.f64\td21, d21, d13\n-\tvadd.f64\td20, d20, d1\n-\tvadd.f64\td28, d28, d26\n-\tvmul.f64\td8, d8, d23\n-\tvstr\td0, [sl]\n-\tvstr\td6, [r8]\n-\tvstr\td17, [r8, #16]\n-\tvstr\td3, [r8, #8]\n-\tvstr\td21, [r8, #24]\n-\tvstr\td30, [r7]\n-\tvstr\td16, [r7, #16]\n-\tvstr\td20, [r7, #8]\n-\tvstr\td28, [r7, #24]\n-\tvstr\td8, [r3]\n-\tb.n\t1c4 <__gridxc_lda_MOD_pzxc+0x1c4>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvldr\td11, [r2, #8]\n-\tvmaxnm.f64\td17, d12, d16\n-\tvmaxnm.f64\td11, d11, d16\n-\tvadd.f64\td12, d17, d11\n-\tvstr\td17, [sp]\n-\tvcmpe.f64\td12, d16\n+\tvldr\td2, [pc, #-168]\t@ 300 <__gridxc_lda_MOD_pzxc+0x300>\n+\tvmov.f64\td3, d7\n+\tvldr\td4, [pc, #-192]\t@ 2f0 <__gridxc_lda_MOD_pzxc+0x2f0>\n+\tvmla.f64\td3, d8, d1\n+\tvmov.f64\td1, d7\n+\tvmla.f64\td1, d8, d2\n+\tvldr\td2, [pc, #-200]\t@ 2f8 <__gridxc_lda_MOD_pzxc+0x2f8>\n+\tvldr\td6, [pc, #-220]\t@ 2e8 <__gridxc_lda_MOD_pzxc+0x2e8>\n+\tvldr\td5, [pc, #-232]\t@ 2e0 <__gridxc_lda_MOD_pzxc+0x2e0>\n+\tvmov.f64\td14, d2\n+\tvldr\td10, [pc, #-248]\t@ 2d8 <__gridxc_lda_MOD_pzxc+0x2d8>\n+\tvmla.f64\td14, d8, d15\n+\tvmov.f64\td15, d2\n+\tvmla.f64\td15, d8, d4\n+\tvmul.f64\td4, d8, d0\n+\tvmla.f64\td3, d4, d5\n+\tvmla.f64\td1, d4, d6\n+\tvstr\td14, [sp, #56]\t@ 0x38\n+\tvmov.f64\td14, d7\n+\tvmla.f64\td7, d8, d6\n+\tvmla.f64\td14, d8, d5\n+\tvmov.f64\td5, d15\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmla.f64\td5, d4, d10\n+\tvmov.f64\td15, d2\n+\tvmla.f64\td15, d8, d10\n+\tvmul.f64\td3, d3, d11\n+\tvmul.f64\td1, d1, d11\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvldr\td7, [pc, #-268]\t@ 310 <__gridxc_lda_MOD_pzxc+0x310>\n+\tvmul.f64\td10, d5, d11\n+\tvldr\td5, [pc, #-268]\t@ 318 <__gridxc_lda_MOD_pzxc+0x318>\n+\tvmla.f64\td6, d4, d7\n+\tvmla.f64\td2, d8, d7\n+\tvldr\td7, [pc, #-224]\t@ 350 <__gridxc_lda_MOD_pzxc+0x350>\n+\tvmls.f64\td7, d8, d5\n+\tvldr\td5, [sp, #48]\t@ 0x30\n+\tvldr\td4, [pc, #-244]\t@ 348 <__gridxc_lda_MOD_pzxc+0x348>\n+\tvmla.f64\td7, d5, d0\n+\tvldr\td5, [pc, #-260]\t@ 340 <__gridxc_lda_MOD_pzxc+0x340>\n+\tvmls.f64\td5, d8, d4\n+\tvldr\td4, [pc, #-284]\t@ 330 <__gridxc_lda_MOD_pzxc+0x330>\n+\tvstr\td2, [sp, #56]\t@ 0x38\n+\tvmul.f64\td2, d6, d11\n+\tvldr\td6, [pc, #-288]\t@ 338 <__gridxc_lda_MOD_pzxc+0x338>\n+\tvldr\td11, [pc, #-316]\t@ 320 <__gridxc_lda_MOD_pzxc+0x320>\n+\tvmla.f64\td5, d14, d0\n+\tvmls.f64\td4, d8, d6\n+\tvldr\td6, [pc, #-320]\t@ 328 <__gridxc_lda_MOD_pzxc+0x328>\n+\tvmls.f64\td6, d8, d11\n+\tvldr\td8, [sp, #56]\t@ 0x38\n+\tvmla.f64\td4, d15, d0\n+\tvmla.f64\td6, d8, d0\n+\tbne.w\t1a6 <__gridxc_lda_MOD_pzxc+0x1a6>\n+\tvldr\td8, [sp, #32]\n+\tvsub.f64\td6, d6, d5\n+\tvsub.f64\td2, d2, d3\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n+\tvldr\td0, [sp, #40]\t@ 0x28\n+\tvadd.f64\td15, d8, d8\n+\tvldr\td8, [sp]\n+\tvadd.f64\td0, d0, d0\n+\tvmla.f64\td5, d6, d8\n+\tvsub.f64\td6, d6, d4\n+\tvmla.f64\td3, d2, d8\n+\tvmov.f64\td2, d8\n+\tvldr\td8, [sp, #16]\n+\tvadd.f64\td6, d6, d7\n+\tvmul.f64\td6, d6, d8\n+\tvldr\td8, [pc, #-356]\t@ 358 <__gridxc_lda_MOD_pzxc+0x358>\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tvldr\td3, [pc, #-356]\t@ 360 <__gridxc_lda_MOD_pzxc+0x360>\n+\tvstr\td5, [sp, #32]\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvdiv.f64\td6, d11, d9\n+\tvmul.f64\td3, d2, d3\n+\tvldr\td5, [sp, #24]\n+\tvsub.f64\td9, d11, d5\n+\tvadd.f64\td11, d5, d11\n+\tvmul.f64\td14, d3, d6\n+\tvmul.f64\td3, d12, d8\n+\tvmul.f64\td8, d13, d8\n+\tvstr\td14, [sp, #56]\t@ 0x38\n+\tvmov.f64\td14, #80\t@ 0x3e800000 0.250\n+\tvsub.f64\td2, d3, d12\n+\tvmul.f64\td14, d6, d14\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td14, [sp, #64]\t@ 0x40\n+\tvmul.f64\td5, d0, d6\n+\tvldr\td14, [sp, #56]\t@ 0x38\n+\tvmul.f64\td6, d15, d6\n+\tvldr\td0, [sp, #8]\n+\tvldr\td15, [sp, #80]\t@ 0x50\n+\tvmla.f64\td0, d14, d2\n+\tvsub.f64\td14, d12, d3\n+\tvldr\td3, [sp]\n+\tvmla.f64\td12, d2, d3\n+\tvsub.f64\td3, d2, d8\n+\tvstr\td14, [sp, #72]\t@ 0x48\n+\tvmov.f64\td14, d13\n+\tvadd.f64\td3, d3, d13\n+\tvstr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td0, [sp, #16]\n+\tvmul.f64\td3, d3, d0\n+\tvstr\td12, [sp, #8]\n+\tvmul.f64\td12, d9, d15\n+\tvstr\td3, [sp, #16]\n+\tvmul.f64\td3, d9, d0\n+\tvmul.f64\td0, d11, d0\n+\tvmul.f64\td11, d11, d15\n+\tvsub.f64\td9, d8, d13\n+\tvmov.f64\td15, d7\n+\tvstr\td11, [sp, #24]\n+\tvsub.f64\td11, d13, d8\n+\tvldr\td13, [sp]\n+\tvsub.f64\td8, d4, d7\n+\tvsub.f64\td4, d7, d4\n+\tvsub.f64\td7, d10, d1\n+\tvsub.f64\td1, d1, d10\n+\tvmla.f64\td14, d9, d13\n+\tvmla.f64\td15, d8, d13\n+\tvmul.f64\td10, d7, d3\n+\tvldr\td7, [sp, #8]\n+\tvmla.f64\td7, d9, d3\n+\tvstr\td14, [sp, #80]\t@ 0x50\n+\tvldr\td14, [sp, #64]\t@ 0x40\n+\tvstr\td7, [r6]\n+\tvmul.f64\td13, d3, d14\n+\tvmul.f64\td14, d0, d14\n+\tvldr\td7, [sp, #8]\n+\tvmla.f64\td7, d0, d11\n+\tvmul.f64\td13, d13, d2\n+\tvldr\td2, [sp, #72]\t@ 0x48\n+\tvmul.f64\td14, d2, d14\n+\tvmul.f64\td2, d1, d0\n+\tvmul.f64\td1, d9, d12\n+\tvldr\td9, [sp, #32]\n+\tvmul.f64\td12, d8, d12\n+\tvstr\td7, [r6, #8]\n+\tvstr\td2, [sp]\n+\tvmov.f64\td2, d9\n+\tvmla.f64\td2, d8, d3\n+\tvmla.f64\td9, d0, d4\n+\tvstr\td2, [r5]\n+\tvstr\td9, [r5, #8]\n+\tvldr\td9, [sp, #24]\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvldr\td0, [sp, #16]\n+\tvmul.f64\td4, d4, d9\n+\tvmul.f64\td11, d11, d9\n+\tvmov.f64\td9, d7\n+\tvldr\td8, [sp, #40]\t@ 0x28\n+\tvmla.f64\td9, d0, d5\n+\tvmov.f64\td2, d7\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvmls.f64\td2, d6, d0\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tvmov.f64\td0, d7\n+\tvmls.f64\td7, d6, d8\n+\tvmla.f64\td0, d5, d8\n+\tvmov.f64\td3, d9\n+\tvmov.f64\td9, d13\n+\tvmls.f64\td13, d6, d1\n+\tvmla.f64\td9, d5, d1\n+\tvmov.f64\td1, d14\n+\tvmla.f64\td1, d5, d11\n+\tvmls.f64\td14, d6, d11\n+\tvmov.f64\td8, d7\n+\tvmov.f64\td7, d10\n+\tvmla.f64\td7, d5, d12\n+\tvmls.f64\td10, d6, d12\n+\tvadd.f64\td9, d9, d3\n+\tvadd.f64\td13, d13, d2\n+\tvadd.f64\td1, d1, d3\n+\tvldr\td3, [sp]\n+\tvadd.f64\td14, d14, d2\n+\tvadd.f64\td7, d7, d0\n+\tvmov.f64\td2, d3\n+\tvstr\td9, [r8]\n+\tvmla.f64\td2, d5, d4\n+\tvmov.f64\td5, d3\n+\tvmls.f64\td5, d6, d4\n+\tvstr\td14, [r8, #24]\n+\tvldr\td14, [sp, #80]\t@ 0x50\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvadd.f64\td3, d10, d8\n+\tvstr\td7, [r7]\n+\tvstr\td13, [r8, #16]\n+\tvmul.f64\td7, d14, d4\n+\tvmul.f64\td4, d15, d4\n+\tvstr\td1, [r8, #8]\n+\tvstr\td3, [r7, #16]\n+\tvadd.f64\td2, d2, d0\n+\tvadd.f64\td5, d5, d8\n+\tvstr\td7, [sl]\n+\tvstr\td4, [r3]\n+\tvstr\td2, [r7, #8]\n+\tvstr\td5, [r7, #24]\n+\tb.n\t1d4 <__gridxc_lda_MOD_pzxc+0x1d4>\n+\tvcmpe.f64\td9, #0.0\n+\tvldr\td7, [pc, #-860]\t@ 368 <__gridxc_lda_MOD_pzxc+0x368>\n+\tvldr\td6, [r2, #8]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t72e <__gridxc_lda_MOD_pzxc+0x72e>\n-\tvsub.f64\td16, d17, d11\n-\tvmov.f64\td18, #240\t@ 0xbf800000 -1.0\n-\tvdiv.f64\td15, d16, d12\n-\tvcmpe.f64\td15, d18\n+\tvcmpe.f64\td6, d7\n+\tite\tlt\n+\tvmovlt.f64\td5, d7\n+\tvmovge.f64\td5, d9\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t71c <__gridxc_lda_MOD_pzxc+0x71c>\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvcmpe.f64\td15, d9\n+\tvstr\td5, [sp, #32]\n+\tit\tlt\n+\tvmovlt.f64\td6, d7\n+\tvadd.f64\td9, d5, d6\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvcmpe.f64\td9, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t74a <__gridxc_lda_MOD_pzxc+0x74a>\n-\tvldr\td16, [pc, #-760]\t@ 370 <__gridxc_lda_MOD_pzxc+0x370>\n-\tvldr\td10, [pc, #-788]\t@ 358 <__gridxc_lda_MOD_pzxc+0x358>\n-\tvstr\td16, [sp, #24]\n-\tb.n\t46 <__gridxc_lda_MOD_pzxc+0x46>\n-\tvldr\td20, [pc, #-788]\t@ 360 <__gridxc_lda_MOD_pzxc+0x360>\n-\tvldr\td19, [pc, #-784]\t@ 368 <__gridxc_lda_MOD_pzxc+0x368>\n-\tvcmpe.f64\td0, d20\n-\tvmul.f64\td19, d0, d19\n+\tbls.n\t7ee <__gridxc_lda_MOD_pzxc+0x7ee>\n+\tvsub.f64\td7, d5, d6\n+\tvmov.f64\td6, #240\t@ 0xbf800000 -1.0\n+\tvdiv.f64\td7, d7, d9\n+\tvcmpe.f64\td7, d6\n+\tvstr\td7, [sp, #24]\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\t7d4 <__gridxc_lda_MOD_pzxc+0x7d4>\n+\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n+\tvcmpe.f64\td7, d10\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td21, d19, d19\n-\tbmi.n\t70e <__gridxc_lda_MOD_pzxc+0x70e>\n-\tvadd.f64\td20, d21, d16\n-\tvstr\td18, [sp, #40]\t@ 0x28\n-\tvstr\td21, [sp, #32]\n-\tvstr\td19, [sp, #8]\n-\tvsqrt.f64\td16, d20\n-\tvadd.f64\td0, d19, d16\n-\tvstr\td16, [sp, #16]\n+\tblt.n\t80a <__gridxc_lda_MOD_pzxc+0x80a>\n+\tvldr\td7, [pc, #-952]\t@ 370 <__gridxc_lda_MOD_pzxc+0x370>\n+\tvstr\td10, [sp]\n+\tvstr\td7, [sp, #16]\n+\tvldr\td7, [pc, #-956]\t@ 378 <__gridxc_lda_MOD_pzxc+0x378>\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tb.n\t4a <__gridxc_lda_MOD_pzxc+0x4a>\n+\tvldr\td6, [pc, #-956]\t@ 380 <__gridxc_lda_MOD_pzxc+0x380>\n+\tvldr\td15, [pc, #-952]\t@ 388 <__gridxc_lda_MOD_pzxc+0x388>\n+\tvcmpe.f64\td0, d6\n+\tvmul.f64\td15, d0, d15\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td11, d15, d15\n+\tbmi.n\t7c2 <__gridxc_lda_MOD_pzxc+0x7c2>\n+\tvadd.f64\td7, d11, d7\n+\tvsqrt.f64\td6, d7\n+\tvadd.f64\td0, d15, d6\n+\tvstr\td6, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td18, [sp, #40]\t@ 0x28\n-\tvldr\td21, [sp, #32]\n-\tvldr\td16, [sp, #16]\n-\tvldr\td19, [sp, #8]\n-\tvmul.f64\td16, d16, d19\n-\tvmov.f64\td22, #120\t@ 0x3fc00000 1.5\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td24, d0, d22\n-\tvsub.f64\td0, d16, d0\n-\tvdiv.f64\td20, d24, d16\n-\tvdiv.f64\td16, d0, d21\n-\tvsub.f64\td20, d20, d23\n-\tvnmul.f64\td16, d16, d16\n-\tvmul.f64\td14, d14, d20\n-\tvfma.f64\td19, d16, d22\n-\tvmul.f64\td13, d13, d19\n-\tb.n\t78 <__gridxc_lda_MOD_pzxc+0x78>\n-\tvstr\td15, [r3]\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tvstr\td15, [r6]\n-\tvstr\td15, [r5]\n-\tvstr\td15, [r3]\n-\tadd\tsp, #48\t@ 0x30\n+\tvmov.f64\td7, d0\n+\tvldr\td6, [sp, #8]\n+\tvmul.f64\td6, d6, d15\n+\tvmov.f64\td3, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td1, d7, d3\n+\tvsub.f64\td7, d6, d7\n+\tvdiv.f64\td4, d1, d6\n+\tvdiv.f64\td6, d7, d11\n+\tvsub.f64\td4, d4, d2\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td12, d12, d4\n+\tvmls.f64\td5, d6, d3\n+\tvmul.f64\td13, d13, d5\n+\tb.n\t7c <__gridxc_lda_MOD_pzxc+0x7c>\n+\tvstr\td14, [r3]\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tvstr\td14, [r6]\n+\tvstr\td14, [r5]\n+\tvstr\td14, [r3]\n+\tadd\tsp, #88\t@ 0x58\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td0, d19\n-\tvfma.f64\td16, d21, d20\n-\tb.n\t6bc <__gridxc_lda_MOD_pzxc+0x6bc>\n-\tvldr\td16, [pc, #-944]\t@ 370 <__gridxc_lda_MOD_pzxc+0x370>\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvldr\td10, [pc, #-944]\t@ 378 <__gridxc_lda_MOD_pzxc+0x378>\n-\tvstr\td16, [sp, #24]\n-\tb.n\t46 <__gridxc_lda_MOD_pzxc+0x46>\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tvstr\td16, [r6]\n-\tvstr\td16, [r6, #8]\n-\tvstr\td16, [r5]\n-\tvstr\td16, [r3]\n-\tvstr\td16, [r5, #8]\n-\tb.n\t220 <__gridxc_lda_MOD_pzxc+0x220>\n-\tvadd.f64\td13, d15, d9\n-\tvsub.f64\td8, d9, d15\n-\tvmov.f64\td0, d13\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvmla.f64\td7, d11, d5\n+\tvmov.f64\td6, d7\n+\tvmov.f64\td7, d15\n+\tb.n\t770 <__gridxc_lda_MOD_pzxc+0x770>\n+\tvldr\td7, [pc, #160]\t@ 878 <__gridxc_lda_MOD_pzxc+0x878>\n+\tvstr\td7, [sp, #16]\n+\tvldr\td7, [pc, #160]\t@ 880 <__gridxc_lda_MOD_pzxc+0x880>\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp]\n+\tb.n\t4a <__gridxc_lda_MOD_pzxc+0x4a>\n+\tvstr\td7, [r3]\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n+\tvstr\td7, [r6]\n+\tvstr\td7, [r6, #8]\n+\tvstr\td7, [r5]\n+\tvstr\td7, [r3]\n+\tvstr\td7, [r5, #8]\n+\tb.n\t230 <__gridxc_lda_MOD_pzxc+0x230>\n+\tvadd.f64\td12, d7, d10\n+\tvsub.f64\td8, d10, d7\n+\tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td10, d0\n+\tvmov.f64\td11, d0\n \tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td24, d0, d0\n-\tvmov.f64\td22, #0\t@ 0x40000000 2.0\n-\tvldr\td21, [pc, #64]\t@ 7b0 <__gridxc_lda_MOD_pzxc+0x7b0>\n-\tvmul.f64\td16, d10, d10\n-\tvldr\td19, [pc, #64]\t@ 7b8 <__gridxc_lda_MOD_pzxc+0x7b8>\n-\tvldr\td23, [pc, #68]\t@ 7c0 <__gridxc_lda_MOD_pzxc+0x7c0>\n-\tvdiv.f64\td18, d9, d24\n-\tvdiv.f64\td20, d9, d16\n-\tvmul.f64\td16, d8, d0\n-\tvfma.f64\td16, d10, d13\n-\tvsub.f64\td10, d10, d0\n-\tvmul.f64\td10, d10, d23\n-\tvsub.f64\td16, d16, d22\n-\tvmul.f64\td9, d16, d21\n-\tvadd.f64\td18, d18, d20\n-\tvmul.f64\td16, d18, d19\n-\tvstr\td16, [sp, #24]\n-\tb.n\t46 <__gridxc_lda_MOD_pzxc+0x46>\n-\tnop.w\n-\t.word\t0xcf657063\n-\t.word\t0x3ffec750\n+\tvmul.f64\td5, d8, d0\n+\tvmul.f64\td4, d0, d0\n+\tvmla.f64\td5, d11, d12\n+\tvsub.f64\td6, d11, d0\n+\tvmul.f64\td11, d11, d11\n+\tvdiv.f64\td3, d10, d4\n+\tvdiv.f64\td4, d10, d11\n+\tvadd.f64\td3, d3, d4\n+\tvldr\td4, [pc, #64]\t@ 888 <__gridxc_lda_MOD_pzxc+0x888>\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvmov.f64\td7, #0\t@ 0x40000000 2.0\n+\tvsub.f64\td5, d5, d7\n+\tvldr\td7, [pc, #52]\t@ 890 <__gridxc_lda_MOD_pzxc+0x890>\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [sp]\n+\tvldr\td7, [pc, #48]\t@ 898 <__gridxc_lda_MOD_pzxc+0x898>\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #16]\n+\tb.w\t4a <__gridxc_lda_MOD_pzxc+0x4a>\n+\tnop\n+\t.word\t0xdf98f597\n+\t.word\t0xc009da35\n+\t.word\t0xea65f90f\n+\t.word\t0x3fe13c23\n \t.word\t0x0daf8058\n \t.word\t0x3feb5bd6\n+\t.word\t0xcf657063\n+\t.word\t0x3ffec750\n \t.word\t0x8a43a042\n \t.word\t0x400484e0\n \n-000007c8 <__gridxc_lda_MOD_pw92c>:\n+000008a0 <__gridxc_lda_MOD_pw92c>:\n __gridxc_lda_MOD_pw92c.localalias():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3888]\t@ 0xf30\n+\tstr.w\tr0, [ip, #3856]\t@ 0xf10\n \tldr\tr6, [r0, #0]\n-\tsub\tsp, #128\t@ 0x80\n+\tsub\tsp, #160\t@ 0xa0\n \tmov\tr5, r2\n \tmov\tr4, r3\n-\tvldr\td10, [r1]\n+\tvldr\td9, [r1]\n \tcmp\tr6, #1\n-\tbeq.w\tb40 <__gridxc_lda_MOD_pw92c+0x378>\n-\tvldr\td16, [r1, #8]\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvldr\td18, [pc, #944]\t@ ba8 <__gridxc_lda_MOD_pw92c+0x3e0>\n-\tvldr\td0, [pc, #948]\t@ bb0 <__gridxc_lda_MOD_pw92c+0x3e8>\n-\tvadd.f64\td20, d16, d10\n-\tvsub.f64\td10, d10, d16\n-\tvldr\td12, [pc, #944]\t@ bb8 <__gridxc_lda_MOD_pw92c+0x3f0>\n-\tvmaxnm.f64\td20, d20, d18\n-\tvdiv.f64\td11, d17, d20\n-\tvstr\td20, [sp, #16]\n-\tvmul.f64\td0, d11, d0\n-\tvmul.f64\td10, d10, d11\n+\tbeq.w\td78 <__gridxc_lda_MOD_pw92c+0x4d8>\n+\tvldr\td6, [r1, #8]\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #904]\t@ c58 <__gridxc_lda_MOD_pw92c+0x3b8>\n+\tvldr\td0, [pc, #908]\t@ c60 <__gridxc_lda_MOD_pw92c+0x3c0>\n+\tvadd.f64\td4, d6, d9\n+\tvsub.f64\td9, d9, d6\n+\tvldr\td11, [pc, #904]\t@ c68 <__gridxc_lda_MOD_pw92c+0x3c8>\n+\tvcmpe.f64\td4, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tge\n+\tvmovge.f64\td7, d4\n+\tvdiv.f64\td12, d5, d7\n+\tvstr\td7, [sp, #32]\n+\tvmul.f64\td0, d12, d0\n+\tvmul.f64\td9, d9, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [pc, #924]\t@ bc0 <__gridxc_lda_MOD_pw92c+0x3f8>\n-\tvmov.f64\td8, d0\n-\tvmul.f64\td16, d11, d16\n-\tvsub.f64\td14, d12, d10\n-\tvadd.f64\td9, d10, d12\n-\tvmul.f64\td13, d10, d10\n-\tvmul.f64\td16, d16, d8\n+\tvldr\td7, [pc, #876]\t@ c70 <__gridxc_lda_MOD_pw92c+0x3d0>\n+\tvmov.f64\td10, d0\n+\tvmul.f64\td7, d12, d7\n+\tvsub.f64\td14, d11, d9\n+\tvadd.f64\td8, d9, d11\n+\tvmul.f64\td13, d9, d9\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td6, d14, d12\n \tvmov.f64\td0, d14\n-\tvstr\td16, [sp]\n-\tvmul.f64\td16, d14, d11\n-\tvstr\td16, [sp, #104]\t@ 0x68\n-\tvnmul.f64\td16, d11, d9\n-\tvstr\td16, [sp, #120]\t@ 0x78\n+\tvstr\td7, [sp, #24]\n+\tvnmul.f64\td7, d12, d8\n+\tvstr\td6, [sp, #128]\t@ 0x80\n+\tvstr\td7, [sp, #152]\t@ 0x98\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td22, d13, d13\n-\tvmov.f64\td11, d0\n-\tvmov.f64\td0, d9\n-\tvstr\td22, [sp, #8]\n+\tvmul.f64\td2, d13, d13\n+\tvmov.f64\td12, d0\n+\tvmov.f64\td0, d8\n+\tvstr\td2, [sp]\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td22, [sp, #8]\n-\tvmov.f64\td23, #0\t@ 0x40000000 2.0\n-\tvmov.f64\td17, #16\t@ 0x40800000 4.0\n-\tvldr\td19, [pc, #844]\t@ bc8 <__gridxc_lda_MOD_pw92c+0x400>\n-\tvsub.f64\td16, d0, d11\n-\tvldr\td24, [pc, #844]\t@ bd0 <__gridxc_lda_MOD_pw92c+0x408>\n-\tvsub.f64\td18, d12, d22\n-\tvsub.f64\td21, d22, d12\n-\tvmul.f64\td12, d9, d0\n-\tvmul.f64\td17, d10, d17\n-\tvfma.f64\td12, d14, d11\n-\tvldr\td20, [sp, #16]\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td17, d17, d13\n-\tvsub.f64\td12, d12, d23\n-\tvmul.f64\td6, d12, d19\n-\tvmul.f64\td29, d17, d6\n-\tvmov.f64\td17, d29\n-\tvfma.f64\td29, d22, d16\n-\tvfnms.f64\td17, d18, d16\n-\tvstr\td17, [sp, #112]\t@ 0x70\n-\tvsqrt.f64\td15, d8\n-\tvldr\td16, [pc, #784]\t@ bd8 <__gridxc_lda_MOD_pw92c+0x410>\n-\tvldr\td12, [pc, #788]\t@ be0 <__gridxc_lda_MOD_pw92c+0x418>\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td8, d8, d0\n+\tvmov.f64\td6, #16\t@ 0x40800000 4.0\n+\tvmla.f64\td8, d14, d12\n+\tvmov.f64\td7, #0\t@ 0x40000000 2.0\n+\tvmul.f64\td9, d9, d6\n+\tvldr\td6, [pc, #788]\t@ c78 <__gridxc_lda_MOD_pw92c+0x3d8>\n+\tvldr\td2, [sp]\n+\tvsub.f64\td0, d0, d12\n+\tvmul.f64\td9, d9, d13\n+\tvsub.f64\td7, d8, d7\n+\tvmul.f64\td7, d7, d6\n+\tvsub.f64\td6, d2, d11\n+\tvmul.f64\td9, d9, d7\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvldr\td7, [pc, #760]\t@ c80 <__gridxc_lda_MOD_pw92c+0x3e0>\n+\tvstr\td6, [sp, #80]\t@ 0x50\n+\tvmul.f64\td0, d0, d7\n+\tvmov.f64\td6, d9\n+\tvsub.f64\td7, d11, d2\n+\tvmla.f64\td9, d2, d0\n+\tvnmls.f64\td6, d7, d0\n+\tvstr\td9, [sp, #144]\t@ 0x90\n+\tvstr\td6, [sp, #136]\t@ 0x88\n+\tvsqrt.f64\td12, d10\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvldr\td15, [pc, #724]\t@ c88 <__gridxc_lda_MOD_pw92c+0x3e8>\n \tvmov.f64\td1, #0\t@ 0x40000000 2.0\n-\tvmov.f64\td0, d8\n-\tvmul.f64\td14, d8, d16\n-\tvstr\td29, [sp, #96]\t@ 0x60\n-\tvstr\td6, [sp, #88]\t@ 0x58\n-\tvmov.f64\td9, #120\t@ 0x3fc00000 1.5\n-\tvstr\td21, [sp, #80]\t@ 0x50\n-\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvstr\td20, [sp, #64]\t@ 0x40\n-\tvstr\td16, [sp, #8]\n-\tvfma.f64\td14, d15, d12\n-\tvmul.f64\td11, d15, d8\n-\tvdiv.f64\td10, d19, d15\n+\tvldr\td9, [pc, #724]\t@ c90 <__gridxc_lda_MOD_pw92c+0x3f0>\n+\tvmov.f64\td0, d10\n+\tvstr\td2, [sp, #120]\t@ 0x78\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvldr\td13, [pc, #716]\t@ c98 <__gridxc_lda_MOD_pw92c+0x3f8>\n+\tvdiv.f64\td4, d7, d12\n+\tvmov.f64\td7, #120\t@ 0x3fc00000 1.5\n+\tvmul.f64\td14, d12, d10\n+\tvmul.f64\td3, d12, d7\n+\tvstr\td3, [sp]\n+\tvstr\td4, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tpow\n-\tvldr\td25, [pc, #728]\t@ be8 <__gridxc_lda_MOD_pw92c+0x420>\n-\tvmul.f64\td9, d15, d9\n-\tvldr\td24, [pc, #728]\t@ bf0 <__gridxc_lda_MOD_pw92c+0x428>\n-\tvldr\td19, [pc, #732]\t@ bf8 <__gridxc_lda_MOD_pw92c+0x430>\n-\tvfma.f64\td14, d0, d25\n-\tvldr\td16, [sp, #8]\n-\tvfma.f64\td16, d8, d24\n-\tvldr\td23, [pc, #724]\t@ c00 <__gridxc_lda_MOD_pw92c+0x438>\n-\tvldr\td17, [pc, #728]\t@ c08 <__gridxc_lda_MOD_pw92c+0x440>\n-\tvstr\td0, [sp, #24]\n-\tvfma.f64\td16, d9, d19\n-\tvstr\td17, [sp, #16]\n-\tvmov.f64\td24, d14\n-\tvfma.f64\td24, d11, d19\n-\tvdiv.f64\td25, d23, d24\n-\tvfma.f64\td16, d10, d12\n-\tvmov.f64\td12, d13\n-\tvfma.f64\td12, d8, d17\n-\tvnmul.f64\td16, d16, d25\n-\tvadd.f64\td23, d25, d13\n-\tvdiv.f64\td14, d16, d24\n-\tvmov.f64\td0, d23\n-\tvstr\td23, [sp, #8]\n+\tvmul.f64\td5, d12, d15\n+\tvldr\td4, [pc, #688]\t@ ca0 <__gridxc_lda_MOD_pw92c+0x400>\n+\tvmla.f64\td5, d10, d9\n+\tvldr\td7, [pc, #688]\t@ ca8 <__gridxc_lda_MOD_pw92c+0x408>\n+\tvldr\td6, [pc, #692]\t@ cb0 <__gridxc_lda_MOD_pw92c+0x410>\n+\tvstr\td0, [sp, #16]\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvmla.f64\td5, d0, d4\n+\tvmla.f64\td5, d14, d7\n+\tvmov.f64\td7, d8\n+\tvmla.f64\td7, d10, d13\n+\tvdiv.f64\td11, d6, d5\n+\tvstr\td5, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvadd.f64\td4, d11, d8\n+\tvmov.f64\td0, d4\n+\tvstr\td4, [sp, #40]\t@ 0x28\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td23, [sp, #8]\n-\tvldr\td17, [sp, #16]\n-\tvldr\td16, [pc, #664]\t@ c10 <__gridxc_lda_MOD_pw92c+0x448>\n-\tvldr\td25, [pc, #668]\t@ c18 <__gridxc_lda_MOD_pw92c+0x450>\n-\tvldr\td18, [sp, #24]\n-\tvldr\td27, [pc, #668]\t@ c20 <__gridxc_lda_MOD_pw92c+0x458>\n-\tvldr\td26, [pc, #672]\t@ c28 <__gridxc_lda_MOD_pw92c+0x460>\n-\tvstr\td18, [sp, #40]\t@ 0x28\n-\tvmul.f64\td14, d12, d14\n-\tvdiv.f64\td24, d14, d23\n-\tvldr\td23, [pc, #664]\t@ c30 <__gridxc_lda_MOD_pw92c+0x468>\n-\tvmul.f64\td14, d0, d23\n-\tvstr\td23, [sp, #48]\t@ 0x30\n-\tvfma.f64\td24, d0, d17\n-\tvmul.f64\td17, d8, d16\n-\tvfma.f64\td17, d15, d25\n-\tvfma.f64\td17, d18, d27\n-\tvldr\td27, [pc, #644]\t@ c38 <__gridxc_lda_MOD_pw92c+0x470>\n-\tvstr\td24, [sp, #56]\t@ 0x38\n-\tvfma.f64\td17, d11, d26\n-\tvdiv.f64\td0, d27, d17\n-\tvldr\td27, [pc, #636]\t@ c40 <__gridxc_lda_MOD_pw92c+0x478>\n-\tvfma.f64\td16, d8, d27\n-\tvfma.f64\td16, d9, d26\n-\tvmov.f64\td26, d13\n-\tvfma.f64\td16, d10, d25\n-\tvnmul.f64\td16, d16, d0\n-\tvadd.f64\td25, d0, d13\n-\tvdiv.f64\td27, d16, d17\n-\tvldr\td16, [pc, #612]\t@ c48 <__gridxc_lda_MOD_pw92c+0x480>\n-\tvmov.f64\td0, d25\n-\tvstr\td25, [sp, #8]\n-\tvfma.f64\td26, d8, d16\n-\tvstr\td16, [sp, #24]\n-\tvstr\td26, [sp, #16]\n-\tvstr\td27, [sp, #32]\n+\tvldr\td6, [pc, #644]\t@ cb8 <__gridxc_lda_MOD_pw92c+0x418>\n+\tvldr\td7, [sp, #64]\t@ 0x40\n+\tvldr\td3, [sp]\n+\tvmla.f64\td9, d10, d6\n+\tvldr\td4, [sp, #8]\n+\tvldr\td5, [sp, #56]\t@ 0x38\n+\tvldr\td1, [pc, #628]\t@ cc0 <__gridxc_lda_MOD_pw92c+0x420>\n+\tvldr\td2, [sp, #16]\n+\tvmla.f64\td9, d3, d7\n+\tvldr\td3, [sp, #48]\t@ 0x30\n+\tvmla.f64\td9, d4, d15\n+\tvldr\td4, [sp, #40]\t@ 0x28\n+\tvldr\td15, [pc, #612]\t@ cc8 <__gridxc_lda_MOD_pw92c+0x428>\n+\tvnmul.f64\td11, d11, d9\n+\tvdiv.f64\td7, d11, d5\n+\tvldr\td5, [pc, #608]\t@ cd0 <__gridxc_lda_MOD_pw92c+0x430>\n+\tvldr\td11, [pc, #612]\t@ cd8 <__gridxc_lda_MOD_pw92c+0x438>\n+\tvmul.f64\td7, d7, d3\n+\tvdiv.f64\td6, d7, d4\n+\tvmul.f64\td7, d12, d15\n+\tvmla.f64\td7, d10, d1\n+\tvldr\td4, [pc, #600]\t@ ce0 <__gridxc_lda_MOD_pw92c+0x440>\n+\tvldr\td1, [pc, #604]\t@ ce8 <__gridxc_lda_MOD_pw92c+0x448>\n+\tvmla.f64\td7, d2, d4\n+\tvldr\td4, [pc, #604]\t@ cf0 <__gridxc_lda_MOD_pw92c+0x450>\n+\tvmla.f64\td7, d14, d1\n+\tvdiv.f64\td9, d5, d7\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tvmla.f64\td6, d0, d13\n+\tvmul.f64\td0, d0, d4\n+\tvmul.f64\td3, d0, d3\n+\tvmul.f64\td4, d6, d4\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d10, d11\n+\tvstr\td3, [sp, #104]\t@ 0x68\n+\tvstr\td4, [sp, #112]\t@ 0x70\n+\tvadd.f64\td13, d9, d8\n+\tvstr\td9, [sp, #64]\t@ 0x40\n+\tvldr\td9, [pc, #556]\t@ cf8 <__gridxc_lda_MOD_pw92c+0x458>\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvmov.f64\td0, d13\n+\tvstr\td13, [sp, #56]\t@ 0x38\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td26, [sp, #16]\n-\tvldr\td27, [sp, #32]\n-\tvldr\td25, [sp, #8]\n-\tvldr\td16, [sp, #24]\n-\tvmul.f64\td27, d26, d27\n-\tvldr\td30, [pc, #568]\t@ c50 <__gridxc_lda_MOD_pw92c+0x488>\n-\tvldr\td18, [sp, #40]\t@ 0x28\n-\tvldr\td28, [pc, #568]\t@ c58 <__gridxc_lda_MOD_pw92c+0x490>\n-\tvldr\td31, [pc, #572]\t@ c60 <__gridxc_lda_MOD_pw92c+0x498>\n-\tvdiv.f64\td7, d27, d25\n-\tvldr\td27, [pc, #572]\t@ c68 <__gridxc_lda_MOD_pw92c+0x4a0>\n-\tvmov.f64\td25, d0\n-\tvfma.f64\td7, d0, d16\n-\tvldr\td16, [pc, #568]\t@ c70 <__gridxc_lda_MOD_pw92c+0x4a8>\n-\tvmul.f64\td17, d8, d16\n-\tvfma.f64\td17, d15, d27\n-\tvldr\td15, [pc, #564]\t@ c78 <__gridxc_lda_MOD_pw92c+0x4b0>\n-\tvmul.f64\td25, d25, d15\n-\tvfma.f64\td17, d18, d30\n-\tvldr\td30, [pc, #560]\t@ c80 <__gridxc_lda_MOD_pw92c+0x4b8>\n-\tvstr\td7, [sp, #8]\n-\tvfma.f64\td16, d8, d30\n-\tvfma.f64\td17, d11, d28\n-\tvmov.f64\td11, d13\n-\tvfma.f64\td16, d9, d28\n-\tvldr\td9, [pc, #544]\t@ c88 <__gridxc_lda_MOD_pw92c+0x4c0>\n-\tvfma.f64\td11, d8, d9\n-\tvfma.f64\td16, d10, d27\n-\tvmul.f64\td10, d25, d26\n-\tvdiv.f64\td18, d31, d17\n-\tvfms.f64\td10, d12, d14\n-\tvnmul.f64\td16, d16, d18\n-\tvadd.f64\td13, d18, d13\n-\tvdiv.f64\td8, d16, d17\n-\tvmov.f64\td0, d13\n+\tvldr\td1, [pc, #544]\t@ d00 <__gridxc_lda_MOD_pw92c+0x460>\n+\tvmul.f64\td7, d10, d9\n+\tvldr\td5, [pc, #544]\t@ d08 <__gridxc_lda_MOD_pw92c+0x468>\n+\tvldr\td2, [sp, #16]\n+\tvmov.f64\td11, d0\n+\tvmla.f64\td7, d12, d1\n+\tvldr\td13, [pc, #536]\t@ d10 <__gridxc_lda_MOD_pw92c+0x470>\n+\tvstr\td1, [sp, #96]\t@ 0x60\n+\tvldr\td6, [pc, #536]\t@ d18 <__gridxc_lda_MOD_pw92c+0x478>\n+\tvldr\td12, [pc, #540]\t@ d20 <__gridxc_lda_MOD_pw92c+0x480>\n+\tvmla.f64\td7, d2, d5\n+\tvmov.f64\td1, d7\n+\tvmla.f64\td1, d14, d13\n+\tvmov.f64\td14, d8\n+\tvmla.f64\td14, d10, d12\n+\tvdiv.f64\td2, d6, d1\n+\tvstr\td1, [sp, #40]\t@ 0x28\n+\tvadd.f64\td8, d2, d8\n+\tvstr\td2, [sp, #16]\n+\tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td16, [pc, #508]\t@ c90 <__gridxc_lda_MOD_pw92c+0x4c8>\n-\tvldr\td21, [sp, #80]\t@ 0x50\n+\tvldr\td5, [pc, #500]\t@ d28 <__gridxc_lda_MOD_pw92c+0x488>\n+\tvldr\td6, [pc, #392]\t@ cc0 <__gridxc_lda_MOD_pw92c+0x420>\n+\tvmov.f64\td7, d0\n+\tvldr\td3, [sp]\n \tcmp\tr6, #1\n-\tvldr\td7, [sp, #8]\n-\tvldr\td23, [sp, #48]\t@ 0x30\n-\tvmul.f64\td26, d21, d16\n-\tvmul.f64\td16, d0, d16\n-\tvldr\td24, [sp, #56]\t@ 0x38\n-\tvmul.f64\td15, d7, d15\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tvldr\td6, [sp, #88]\t@ 0x58\n-\tvmul.f64\td16, d16, d11\n-\tvfms.f64\td15, d24, d23\n-\tvmul.f64\td17, d10, d22\n-\tvldr\td20, [sp, #64]\t@ 0x40\n-\tvldr\td29, [sp, #96]\t@ 0x60\n-\tvfma.f64\td17, d16, d21\n-\tvmul.f64\td15, d15, d22\n-\tvmul.f64\td17, d17, d6\n-\tvfma.f64\td17, d12, d14\n-\tvmul.f64\td8, d11, d8\n-\tvstr\td17, [r5]\n-\tvdiv.f64\td25, d8, d13\n-\tvfma.f64\td25, d0, d9\n-\tvfma.f64\td15, d25, d26\n-\tvmul.f64\td15, d15, d6\n-\tvfma.f64\td15, d24, d23\n-\tbeq.n\tb8a <__gridxc_lda_MOD_pw92c+0x3c2>\n-\tvldr\td18, [sp, #112]\t@ 0x70\n-\tvldr\td19, [sp, #120]\t@ 0x78\n-\tvnmul.f64\td16, d18, d16\n-\tvldr\td18, [sp, #104]\t@ 0x68\n-\tvfma.f64\td16, d10, d29\n-\tvmul.f64\td18, d16, d18\n-\tvmul.f64\td16, d16, d19\n-\tvldr\td19, [sp]\n-\tvfma.f64\td18, d19, d15\n-\tvfma.f64\td16, d19, d15\n-\tvmov.f64\td19, d17\n-\tvfma.f64\td19, d18, d20\n-\tvfma.f64\td17, d16, d20\n-\tvstr\td19, [r4]\n-\tvstr\td17, [r4, #8]\n-\tadd\tsp, #128\t@ 0x80\n-\tvpop\t{d8-d15}\n-\tpop\t{r4, r5, r6, pc}\n-\tvldr\td20, [pc, #100]\t@ ba8 <__gridxc_lda_MOD_pw92c+0x3e0>\n-\tvldr\td0, [pc, #104]\t@ bb0 <__gridxc_lda_MOD_pw92c+0x3e8>\n-\tvmaxnm.f64\td20, d10, d20\n-\tvdiv.f64\td0, d0, d20\n-\tvstr\td20, [sp]\n-\tbl\t0 \n- R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [pc, #100]\t@ bc0 <__gridxc_lda_MOD_pw92c+0x3f8>\n-\tvldr\td20, [sp]\n-\tvmov.i64\td29, #0x0000000000000000\n-\tvmov.f64\td8, d0\n-\tvldr\td6, [pc, #300]\t@ c98 <__gridxc_lda_MOD_pw92c+0x4d0>\n-\tvmul.f64\td16, d0, d16\n-\tvldr\td21, [pc, #300]\t@ ca0 <__gridxc_lda_MOD_pw92c+0x4d8>\n-\tvmov.f64\td22, d29\n-\tvstr\td29, [sp, #112]\t@ 0x70\n-\tvstr\td29, [sp, #104]\t@ 0x68\n-\tvdiv.f64\td16, d16, d20\n-\tvstr\td16, [sp]\n-\tb.n\t8c0 <__gridxc_lda_MOD_pw92c+0xf8>\n-\tvldr\td16, [sp]\n-\tvmul.f64\td20, d16, d20\n-\tvfma.f64\td17, d15, d20\n-\tvmov.f64\td19, d17\n-\tvstr\td19, [r4]\n-\tadd\tsp, #128\t@ 0x80\n+\tvmla.f64\td6, d10, d5\n+\tvldr\td0, [pc, #412]\t@ ce8 <__gridxc_lda_MOD_pw92c+0x448>\n+\tvldr\td4, [sp, #8]\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvmla.f64\td6, d3, d0\n+\tvldr\td0, [sp, #64]\t@ 0x40\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvmla.f64\td6, d4, d15\n+\tvnmul.f64\td6, d0, d6\n+\tvdiv.f64\td5, d6, d5\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmul.f64\td5, d5, d2\n+\tvdiv.f64\td6, d5, d6\n+\tvldr\td5, [pc, #344]\t@ cd8 <__gridxc_lda_MOD_pw92c+0x438>\n+\tvmla.f64\td6, d11, d5\n+\tvldr\td5, [pc, #424]\t@ d30 <__gridxc_lda_MOD_pw92c+0x490>\n+\tvmla.f64\td9, d10, d5\n+\tvldr\td5, [sp, #16]\n+\tvmla.f64\td9, d3, d13\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvmla.f64\td9, d4, d1\n+\tvldr\td1, [sp, #40]\t@ 0x28\n+\tvldr\td4, [sp, #112]\t@ 0x70\n+\tvmov.f64\td0, d4\n+\tvnmul.f64\td9, d5, d9\n+\tvdiv.f64\td1, d9, d1\n+\tvmul.f64\td1, d1, d14\n+\tvdiv.f64\td5, d1, d8\n+\tvldr\td1, [pc, #380]\t@ d38 <__gridxc_lda_MOD_pw92c+0x498>\n+\tvldr\td8, [sp, #80]\t@ 0x50\n+\tvnmls.f64\td0, d6, d1\n+\tvmul.f64\td11, d11, d1\n+\tvmov.f64\td6, d3\n+\tvldr\td1, [pc, #368]\t@ d40 <__gridxc_lda_MOD_pw92c+0x4a0>\n+\tvnmls.f64\td6, d11, d2\n+\tvldr\td2, [sp, #120]\t@ 0x78\n+\tvmla.f64\td5, d7, d12\n+\tvmul.f64\td7, d7, d1\n+\tvmul.f64\td1, d8, d1\n+\tvmul.f64\td7, d7, d14\n+\tvmul.f64\td5, d5, d1\n+\tvldr\td1, [sp, #88]\t@ 0x58\n+\tvmla.f64\td5, d0, d2\n+\tvmul.f64\td2, d6, d2\n+\tvmla.f64\td2, d7, d8\n+\tvmla.f64\td4, d5, d1\n+\tvmla.f64\td3, d2, d1\n+\tvstr\td3, [r5]\n+\tbeq.w\tdd8 <__gridxc_lda_MOD_pw92c+0x538>\n+\tvldr\td5, [sp, #136]\t@ 0x88\n+\tvmul.f64\td7, d7, d5\n+\tvldr\td5, [sp, #24]\n+\tvmul.f64\td5, d5, d4\n+\tvldr\td4, [sp, #144]\t@ 0x90\n+\tvnmls.f64\td7, d6, d4\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvmov.f64\td6, d5\n+\tvmla.f64\td6, d7, d4\n+\tvldr\td4, [sp, #152]\t@ 0x98\n+\tvmla.f64\td5, d7, d4\n+\tvldr\td4, [sp, #32]\n+\tvmov.f64\td7, d3\n+\tvmla.f64\td7, d6, d4\n+\tvmla.f64\td3, d5, d4\n+\tvstr\td7, [r4]\n+\tvstr\td3, [r4, #8]\n+\tadd\tsp, #160\t@ 0xa0\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tnop\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0xa4aeacc4\n \t.word\t0x3fce8ec8\n \t.word\t0x00001198\n \t.word\t0x3ff00000\n \t.word\t0x55555555\n \t.word\t0xbfd55555\n \t.word\t0xcf657063\n \t.word\t0x3ffec750\n \t.word\t0x8a43a042\n \t.word\t0x400484e0\n-\t.word\t0xa0f9096c\n-\t.word\t0x400cb367\n \t.word\t0x2e48e8a7\n \t.word\t0x401e61ff\n+\t.word\t0xa0f9096c\n+\t.word\t0x400cb367\n+\t.word\t0x8793dd98\n+\t.word\t0x3fcb5a85\n \t.word\t0x36b8f9b1\n \t.word\t0x3fdf8c54\n-\t.word\t0x36b8f9b1\n-\t.word\t0x3fef8c54\n \t.word\t0x3404ea4b\n \t.word\t0x3ffa3611\n \t.word\t0x7053a807\n \t.word\t0x403014f2\n-\t.word\t0x8793dd98\n-\t.word\t0x3fcb5a85\n+\t.word\t0x36b8f9b1\n+\t.word\t0x3fef8c54\n \t.word\t0xde69ad43\n \t.word\t0x4018ca71\n \t.word\t0x75f6fd22\n \t.word\t0x402c3ce0\n+\t.word\t0x569f93f8\n+\t.word\t0x40401514\n+\t.word\t0x2bfdb4cc\n+\t.word\t0x3fca4d2b\n \t.word\t0x840e171a\n \t.word\t0x3fe40164\n \t.word\t0x43fe5c92\n \t.word\t0x400aedfa\n \t.word\t0xb0ccbc06\n \t.word\t0xbfafd651\n-\t.word\t0x569f93f8\n-\t.word\t0x40401514\n-\t.word\t0x840e171a\n-\t.word\t0x3ff40164\n-\t.word\t0x2bfdb4cc\n-\t.word\t0x3fca4d2b\n+\t.word\t0xda5119ce\n+\t.word\t0x400cfc1b\n+\t.word\t0xb4395810\n+\t.word\t0x4024b6c8\n \t.word\t0xbd66277c\n \t.word\t0x3fdfca18\n \t.word\t0x04ff4342\n \t.word\t0x3fec2b17\n \t.word\t0x8c3dca5e\n \t.word\t0x403d9bcb\n-\t.word\t0xb4395810\n-\t.word\t0x4024b6c8\n-\t.word\t0xda5119ce\n-\t.word\t0x400cfc1b\n-\t.word\t0x94ee392e\n-\t.word\t0xbf9fd60e\n-\t.word\t0xbd66277c\n-\t.word\t0x3fefca18\n \t.word\t0x47ae147b\n \t.word\t0x3fbc7ae1\n+\t.word\t0x840e171a\n+\t.word\t0x3ff40164\n+\t.word\t0xbd66277c\n+\t.word\t0x3fefca18\n+\t.word\t0x94ee392e\n+\t.word\t0xbf9fd60e\n \t.word\t0x384e3bd7\n \t.word\t0xbf9439d0\n+\t.word\t0x812dea11\n+\t.word\t0x3d719799\n+\t.word\t0xa4aeacc4\n+\t.word\t0x3fce8ec8\n+\t.word\t0x55555555\n+\t.word\t0xbfd55555\n \t.word\t0xd48733aa\n \t.word\t0x3d968fca\n \t.word\t0x00001198\n \t.word\t0xbff00000\n+\t...\n+\tvldr\td10, [pc, #-52]\t@ d48 <__gridxc_lda_MOD_pw92c+0x4a8>\n+\tvldr\td0, [pc, #-48]\t@ d50 <__gridxc_lda_MOD_pw92c+0x4b0>\n+\tvcmpe.f64\td9, d10\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td8, d10\n+\tvmovge.f64\td8, d9\n+\tvdiv.f64\td0, d0, d8\n+\tvstr\td8, [sp, #32]\n+\tbl\t0 \n+ R_ARM_THM_CALL\tcbrt\n+\tvldr\td7, [pc, #-72]\t@ d58 <__gridxc_lda_MOD_pw92c+0x4b8>\n+\tvldr\td5, [pc, #-68]\t@ d60 <__gridxc_lda_MOD_pw92c+0x4c0>\n+\tvmov.f64\td10, d0\n+\tvldr\td6, [pc, #-60]\t@ d70 <__gridxc_lda_MOD_pw92c+0x4d0>\n+\tvmul.f64\td7, d0, d7\n+\tvstr\td5, [sp, #88]\t@ 0x58\n+\tvldr\td5, [pc, #-80]\t@ d68 <__gridxc_lda_MOD_pw92c+0x4c8>\n+\tvmov.f64\td2, d6\n+\tvstr\td6, [sp, #144]\t@ 0x90\n+\tvdiv.f64\td7, d7, d8\n+\tvstr\td6, [sp, #136]\t@ 0x88\n+\tvstr\td5, [sp, #80]\t@ 0x50\n+\tvstr\td6, [sp, #128]\t@ 0x80\n+\tvstr\td7, [sp, #24]\n+\tb.n\t9aa <__gridxc_lda_MOD_pw92c+0x10a>\n+\tvldr\td7, [sp, #24]\n+\tvldr\td6, [sp, #32]\n+\tvmul.f64\td10, d7, d6\n+\tvmov.f64\td7, d3\n+\tvmla.f64\td7, d10, d4\n+\tvstr\td7, [r4]\n+\tadd\tsp, #160\t@ 0xa0\n+\tvpop\t{d8-d15}\n+\tpop\t{r4, r5, r6, pc}\n \n-00000ca8 <__gridxc_lda_MOD_pw92xc>:\n+00000df8 <__gridxc_lda_MOD_pw92xc>:\n __gridxc_lda_MOD_pw92xc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3976]\t@ 0xf88\n \tsub\tsp, #20\n@@ -875,299 +958,311 @@\n \tmov\tr4, r2\n \tmov\tr9, r0\n \tmov\tr8, r3\n \tldr.w\tsl, [sp, #120]\t@ 0x78\n \tcmp\tr6, #2\n \tldrd\tfp, r7, [sp, #124]\t@ 0x7c\n \tvldr\td9, [r2]\n-\tbeq.n\td9c <__gridxc_lda_MOD_pw92xc+0xf4>\n-\tvmov.i64\td8, #0x0000000000000000\n+\tbeq.n\teec <__gridxc_lda_MOD_pw92xc+0xf4>\n+\tvldr\td8, [pc, #420]\t@ fd0 <__gridxc_lda_MOD_pw92xc+0x1d8>\n \tvcmpe.f64\td9, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\te52 <__gridxc_lda_MOD_pw92xc+0x1aa>\n+\tbls.w\tfb2 <__gridxc_lda_MOD_pw92xc+0x1ba>\n \tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td11, d8\n-\tvmov.f64\td10, d12\n-\tvldr\td0, [pc, #376]\t@ e70 <__gridxc_lda_MOD_pw92xc+0x1c8>\n+\tvmov.f64\td10, d8\n+\tvmov.f64\td11, d12\n+\tvldr\td0, [pc, #400]\t@ fd8 <__gridxc_lda_MOD_pw92xc+0x1e0>\n \tvdiv.f64\td0, d0, d9\n \tvmov.f64\td9, #104\t@ 0x3f400000 0.750\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [pc, #368]\t@ e78 <__gridxc_lda_MOD_pw92xc+0x1d0>\n+\tvldr\td7, [pc, #392]\t@ fe0 <__gridxc_lda_MOD_pw92xc+0x1e8>\n \tldr.w\tr3, [r9]\n-\tvdiv.f64\td15, d16, d0\n+\tvdiv.f64\td13, d7, d0\n \tcmp\tr3, #1\n-\tvneg.f64\td16, d15\n-\tvnmul.f64\td9, d15, d9\n-\tbne.n\td7c <__gridxc_lda_MOD_pw92xc+0xd4>\n-\tvldr\td16, [pc, #352]\t@ e80 <__gridxc_lda_MOD_pw92xc+0x1d8>\n-\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td13, d16, d0\n-\tvmul.f64\td19, d13, d13\n-\tvadd.f64\td17, d19, d14\n-\tvstr\td19, [sp, #8]\n-\tvsqrt.f64\td16, d17\n-\tvadd.f64\td0, d13, d16\n-\tvstr\td16, [sp]\n+\tvneg.f64\td2, d13\n+\tvnmul.f64\td9, d13, d9\n+\tbne.n\tecc <__gridxc_lda_MOD_pw92xc+0xd4>\n+\tvldr\td6, [pc, #376]\t@ fe8 <__gridxc_lda_MOD_pw92xc+0x1f0>\n+\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td7, d6, d0\n+\tvmul.f64\td14, d7, d7\n+\tvstr\td7, [sp]\n+\tvadd.f64\td5, d14, d15\n+\tvsqrt.f64\td6, d5\n+\tvadd.f64\td0, d7, d6\n+\tvstr\td6, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td16, [sp]\n-\tvldr\td19, [sp, #8]\n-\tvmov.f64\td18, #120\t@ 0x3fc00000 1.5\n-\tvmul.f64\td13, d13, d16\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvsub.f64\td20, d13, d0\n-\tvmul.f64\td0, d0, d18\n-\tvdiv.f64\td17, d20, d19\n-\tvdiv.f64\td19, d0, d13\n-\tvnmul.f64\td17, d17, d17\n-\tvsub.f64\td16, d16, d19\n-\tvfma.f64\td14, d17, d18\n-\tvmul.f64\td16, d16, d15\n-\tvmul.f64\td9, d9, d14\n+\tvldr\td6, [sp, #8]\n+\tvldr\td7, [sp]\n+\tvmov.f64\td3, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td6, d0, d3\n+\tvsub.f64\td4, d7, d0\n+\tvdiv.f64\td5, d4, d14\n+\tvdiv.f64\td4, d6, d7\n+\tvmul.f64\td5, d5, d5\n+\tvsub.f64\td2, d2, d4\n+\tvmls.f64\td15, d5, d3\n+\tvmul.f64\td2, d2, d13\n+\tvmul.f64\td9, d9, d15\n \tcmp\tr6, #2\n-\tbeq.n\te08 <__gridxc_lda_MOD_pw92xc+0x160>\n-\tvstr\td16, [fp]\n+\tbeq.n\tf70 <__gridxc_lda_MOD_pw92xc+0x178>\n+\tvstr\td2, [fp]\n \tvstr\td9, [r8]\n \tmov\tr3, r7\n \tmov\tr2, sl\n \tmov\tr1, r4\n \tmov\tr0, r5\n \tadd\tsp, #20\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n-\tb.n\t7c8 <__gridxc_lda_MOD_pw92c>\n-\tvmov.i64\td18, #0x0000000000000000\n-\tvldr\td16, [r2, #8]\n-\tvmaxnm.f64\td17, d9, d18\n-\tvmaxnm.f64\td16, d16, d18\n-\tvadd.f64\td9, d17, d16\n-\tvcmpe.f64\td9, d18\n+\tb.n\t8a0 <__gridxc_lda_MOD_pw92c>\n+\tvcmpe.f64\td9, #0.0\n+\tvldr\td5, [pc, #220]\t@ fd0 <__gridxc_lda_MOD_pw92xc+0x1d8>\n+\tvldr\td7, [r2, #8]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\te5c <__gridxc_lda_MOD_pw92xc+0x1b4>\n-\tvsub.f64\td17, d17, d16\n-\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td16, d17, d9\n-\tvadd.f64\td12, d16, d10\n-\tvsub.f64\td10, d10, d16\n+\tvcmpe.f64\td7, d5\n+\tite\tlt\n+\tvmovlt.f64\td6, d5\n+\tvmovge.f64\td6, d9\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvadd.f64\td9, d6, d7\n+\tvcmpe.f64\td9, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\tfbc <__gridxc_lda_MOD_pw92xc+0x1c4>\n+\tvsub.f64\td6, d6, d7\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td7, d6, d9\n+\tvadd.f64\td12, d7, d11\n+\tvsub.f64\td11, d11, d7\n \tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td13, d0\n-\tvmov.f64\td0, d10\n+\tvmov.f64\td8, d0\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td11, d10, d0\n-\tvmov.f64\td17, #0\t@ 0x40000000 2.0\n-\tvldr\td16, [pc, #156]\t@ e88 <__gridxc_lda_MOD_pw92xc+0x1e0>\n-\tvfma.f64\td11, d12, d13\n-\tvsub.f64\td8, d13, d0\n-\tvldr\td18, [pc, #152]\t@ e90 <__gridxc_lda_MOD_pw92xc+0x1e8>\n-\tvmul.f64\td8, d8, d18\n-\tvsub.f64\td11, d11, d17\n-\tvmul.f64\td11, d11, d16\n-\tb.n\tcf4 <__gridxc_lda_MOD_pw92xc+0x4c>\n-\tvldr\td19, [pc, #140]\t@ e98 <__gridxc_lda_MOD_pw92xc+0x1f0>\n-\tvmov.f64\td18, d9\n-\tvldr\td21, [pc, #140]\t@ ea0 <__gridxc_lda_MOD_pw92xc+0x1f8>\n-\tvmov.f64\td20, d9\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td10, d8, d10\n-\tvfnms.f64\td18, d9, d19\n-\tvfms.f64\td20, d9, d19\n-\tvfma.f64\td17, d11, d21\n+\tvmov.f64\td6, #0\t@ 0x40000000 2.0\n+\tvldr\td7, [pc, #160]\t@ ff0 <__gridxc_lda_MOD_pw92xc+0x1f8>\n+\tvmul.f64\td10, d12, d8\n+\tvsub.f64\td8, d8, d0\n+\tvmla.f64\td10, d11, d0\n+\tvldr\td5, [pc, #152]\t@ ff8 <__gridxc_lda_MOD_pw92xc+0x200>\n+\tvmul.f64\td8, d8, d5\n+\tvsub.f64\td10, d10, d6\n+\tvmul.f64\td10, d10, d7\n+\tb.n\te44 <__gridxc_lda_MOD_pw92xc+0x4c>\n+\tvldr\td6, [pc, #140]\t@ 1000 <__gridxc_lda_MOD_pw92xc+0x208>\n+\tvmul.f64\td11, d8, d11\n+\tvldr\td7, [pc, #140]\t@ 1008 <__gridxc_lda_MOD_pw92xc+0x210>\n \tvmul.f64\td8, d8, d12\n-\tvmul.f64\td10, d10, d18\n-\tvmul.f64\td8, d8, d20\n-\tvfma.f64\td10, d16, d17\n-\tvfma.f64\td8, d16, d17\n-\tvfma.f64\td9, d11, d18\n-\tvstr\td10, [fp]\n+\tvmul.f64\td6, d10, d6\n+\tvmul.f64\td7, d9, d7\n+\tvmla.f64\td2, d6, d2\n+\tvsub.f64\td5, d9, d7\n+\tvsub.f64\td7, d7, d9\n+\tvmla.f64\td9, d10, d7\n+\tvmov.f64\td6, d2\n+\tvmla.f64\td2, d11, d7\n+\tvmla.f64\td6, d8, d5\n \tvstr\td9, [r8]\n-\tvstr\td8, [fp, #8]\n-\tb.n\td88 <__gridxc_lda_MOD_pw92xc+0xe0>\n+\tvstr\td2, [fp]\n+\tvstr\td6, [fp, #8]\n+\tb.n\ted8 <__gridxc_lda_MOD_pw92xc+0xe0>\n \tvstr\td8, [r3]\n \tvstr\td8, [fp]\n-\tb.n\td88 <__gridxc_lda_MOD_pw92xc+0xe0>\n-\tvstr\td18, [r3]\n-\tvstr\td18, [fp]\n-\tvstr\td18, [fp, #8]\n-\tb.n\td88 <__gridxc_lda_MOD_pw92xc+0xe0>\n+\tb.n\ted8 <__gridxc_lda_MOD_pw92xc+0xe0>\n+\tvstr\td5, [r3]\n+\tvstr\td5, [fp]\n+\tvstr\td5, [fp, #8]\n+\tb.n\ted8 <__gridxc_lda_MOD_pw92xc+0xe0>\n \tnop\n \tnop.w\n+\t...\n \t.word\t0xa4aeacc4\n \t.word\t0x3fce8ec8\n \t.word\t0x03cd5e97\n \t.word\t0x3fe38c63\n \t.word\t0x0a9843e0\n \t.word\t0x3f8cae89\n \t.word\t0xcf657063\n \t.word\t0x3ffec750\n \t.word\t0x8a43a042\n \t.word\t0x400484e0\n-\t.word\t0xf98d728b\n-\t.word\t0x3ff428a2\n \t.word\t0xe635ca2c\n \t.word\t0x3fd0a28b\n+\t.word\t0xf98d728b\n+\t.word\t0x3ff428a2\n \n-00000ea8 <__gridxc_lda_MOD_exchng>:\n+00001010 <__gridxc_lda_MOD_exchng>:\n __gridxc_lda_MOD_exchng.localalias():\n \tpush\t{r4, r5, r6, r7, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #20\n \tldr\tr6, [r1, #0]\n \tmov\tr5, r0\n \tmov\tr4, r3\n \tvldr\td9, [r2]\n \tcmp\tr6, #2\n \tldr\tr7, [sp, #104]\t@ 0x68\n-\tbeq.n\tf82 <__gridxc_lda_MOD_exchng+0xda>\n-\tvmov.i64\td8, #0x0000000000000000\n+\tbeq.n\t10ea <__gridxc_lda_MOD_exchng+0xda>\n+\tvldr\td8, [pc, #416]\t@ 11d8 <__gridxc_lda_MOD_exchng+0x1c8>\n \tvcmpe.f64\td9, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\t103e <__gridxc_lda_MOD_exchng+0x196>\n+\tbls.w\t11b6 <__gridxc_lda_MOD_exchng+0x1a6>\n \tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td11, d8\n-\tvmov.f64\td10, d12\n-\tvldr\td0, [pc, #372]\t@ 1060 <__gridxc_lda_MOD_exchng+0x1b8>\n+\tvmov.f64\td10, d8\n+\tvmov.f64\td11, d12\n+\tvldr\td0, [pc, #396]\t@ 11e0 <__gridxc_lda_MOD_exchng+0x1d0>\n \tvdiv.f64\td0, d0, d9\n \tvmov.f64\td9, #104\t@ 0x3f400000 0.750\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [pc, #364]\t@ 1068 <__gridxc_lda_MOD_exchng+0x1c0>\n+\tvldr\td7, [pc, #388]\t@ 11e8 <__gridxc_lda_MOD_exchng+0x1d8>\n \tldr\tr3, [r5, #0]\n-\tvdiv.f64\td15, d16, d0\n+\tvdiv.f64\td13, d7, d0\n \tcmp\tr3, #1\n-\tvneg.f64\td16, d15\n-\tvnmul.f64\td9, d15, d9\n-\tbne.n\tf6e <__gridxc_lda_MOD_exchng+0xc6>\n-\tvldr\td16, [pc, #352]\t@ 1070 <__gridxc_lda_MOD_exchng+0x1c8>\n-\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td13, d16, d0\n-\tvmul.f64\td19, d13, d13\n-\tvadd.f64\td17, d19, d14\n-\tvstr\td19, [sp, #8]\n-\tvsqrt.f64\td16, d17\n-\tvadd.f64\td0, d13, d16\n-\tvstr\td16, [sp]\n+\tvneg.f64\td2, d13\n+\tvnmul.f64\td9, d13, d9\n+\tbne.n\t10d6 <__gridxc_lda_MOD_exchng+0xc6>\n+\tvldr\td6, [pc, #376]\t@ 11f0 <__gridxc_lda_MOD_exchng+0x1e0>\n+\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td7, d6, d0\n+\tvmul.f64\td14, d7, d7\n+\tvstr\td7, [sp]\n+\tvadd.f64\td5, d14, d15\n+\tvsqrt.f64\td6, d5\n+\tvadd.f64\td0, d7, d6\n+\tvstr\td6, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td16, [sp]\n-\tvldr\td19, [sp, #8]\n-\tvmov.f64\td18, #120\t@ 0x3fc00000 1.5\n-\tvmul.f64\td13, d13, d16\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvsub.f64\td20, d13, d0\n-\tvmul.f64\td0, d0, d18\n-\tvdiv.f64\td17, d20, d19\n-\tvdiv.f64\td19, d0, d13\n-\tvnmul.f64\td17, d17, d17\n-\tvsub.f64\td16, d16, d19\n-\tvfma.f64\td14, d17, d18\n-\tvmul.f64\td16, d16, d15\n-\tvmul.f64\td9, d9, d14\n+\tvldr\td6, [sp, #8]\n+\tvldr\td7, [sp]\n+\tvmov.f64\td3, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td6, d0, d3\n+\tvsub.f64\td4, d7, d0\n+\tvdiv.f64\td5, d4, d14\n+\tvdiv.f64\td4, d6, d7\n+\tvmul.f64\td5, d5, d5\n+\tvsub.f64\td2, d2, d4\n+\tvmls.f64\td15, d5, d3\n+\tvmul.f64\td2, d2, d13\n+\tvmul.f64\td9, d9, d15\n \tcmp\tr6, #2\n-\tbeq.n\tfee <__gridxc_lda_MOD_exchng+0x146>\n-\tvstr\td16, [r7]\n+\tbeq.n\t116e <__gridxc_lda_MOD_exchng+0x15e>\n+\tvstr\td2, [r7]\n \tvstr\td9, [r4]\n \tadd\tsp, #20\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, r7, pc}\n-\tvmov.i64\td18, #0x0000000000000000\n-\tvldr\td16, [r2, #8]\n-\tvmaxnm.f64\td17, d9, d18\n-\tvmaxnm.f64\td16, d16, d18\n-\tvadd.f64\td9, d17, d16\n-\tvcmpe.f64\td9, d18\n+\tvcmpe.f64\td9, #0.0\n+\tvldr\td5, [pc, #232]\t@ 11d8 <__gridxc_lda_MOD_exchng+0x1c8>\n+\tvldr\td7, [r2, #8]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t104e <__gridxc_lda_MOD_exchng+0x1a6>\n-\tvsub.f64\td17, d17, d16\n-\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td16, d17, d9\n-\tvadd.f64\td12, d16, d10\n-\tvsub.f64\td10, d10, d16\n+\tvcmpe.f64\td7, d5\n+\tite\tlt\n+\tvmovlt.f64\td6, d5\n+\tvmovge.f64\td6, d9\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvadd.f64\td9, d6, d7\n+\tvcmpe.f64\td9, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\t11c6 <__gridxc_lda_MOD_exchng+0x1b6>\n+\tvsub.f64\td6, d6, d7\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td7, d6, d9\n+\tvadd.f64\td12, d7, d11\n+\tvsub.f64\td11, d11, d7\n \tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td13, d0\n-\tvmov.f64\td0, d10\n+\tvmov.f64\td8, d0\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td11, d10, d0\n-\tvmov.f64\td17, #0\t@ 0x40000000 2.0\n-\tvldr\td16, [pc, #164]\t@ 1078 <__gridxc_lda_MOD_exchng+0x1d0>\n-\tvfma.f64\td11, d13, d12\n-\tvsub.f64\td8, d13, d0\n-\tvldr\td18, [pc, #160]\t@ 1080 <__gridxc_lda_MOD_exchng+0x1d8>\n-\tvmul.f64\td8, d8, d18\n-\tvsub.f64\td11, d11, d17\n-\tvmul.f64\td11, d11, d16\n-\tb.n\tee8 <__gridxc_lda_MOD_exchng+0x40>\n-\tvldr\td19, [pc, #152]\t@ 1088 <__gridxc_lda_MOD_exchng+0x1e0>\n-\tvmov.f64\td18, d9\n-\tvldr\td21, [pc, #152]\t@ 1090 <__gridxc_lda_MOD_exchng+0x1e8>\n-\tvmov.f64\td20, d9\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td10, d8, d10\n-\tvfnms.f64\td18, d9, d19\n-\tvfms.f64\td20, d9, d19\n-\tvfma.f64\td17, d11, d21\n+\tvmov.f64\td6, #0\t@ 0x40000000 2.0\n+\tvldr\td7, [pc, #168]\t@ 11f8 <__gridxc_lda_MOD_exchng+0x1e8>\n+\tvmul.f64\td10, d8, d12\n+\tvsub.f64\td8, d8, d0\n+\tvmla.f64\td10, d11, d0\n+\tvldr\td5, [pc, #160]\t@ 1200 <__gridxc_lda_MOD_exchng+0x1f0>\n+\tvmul.f64\td8, d8, d5\n+\tvsub.f64\td10, d10, d6\n+\tvmul.f64\td10, d10, d7\n+\tb.n\t1050 <__gridxc_lda_MOD_exchng+0x40>\n+\tvldr\td6, [pc, #152]\t@ 1208 <__gridxc_lda_MOD_exchng+0x1f8>\n+\tvmul.f64\td11, d8, d11\n+\tvldr\td7, [pc, #152]\t@ 1210 <__gridxc_lda_MOD_exchng+0x200>\n \tvmul.f64\td8, d8, d12\n-\tvmul.f64\td10, d10, d18\n-\tvmul.f64\td8, d8, d20\n-\tvfma.f64\td10, d16, d17\n-\tvfma.f64\td8, d16, d17\n-\tvfma.f64\td9, d18, d11\n-\tvstr\td10, [r7]\n-\tvstr\td8, [r7, #8]\n+\tvmul.f64\td6, d10, d6\n+\tvmul.f64\td7, d9, d7\n+\tvmla.f64\td2, d6, d2\n+\tvsub.f64\td5, d9, d7\n+\tvsub.f64\td7, d7, d9\n+\tvmla.f64\td9, d7, d10\n+\tvmov.f64\td6, d2\n+\tvmla.f64\td2, d11, d7\n+\tvmla.f64\td6, d8, d5\n \tvstr\td9, [r4]\n+\tvstr\td2, [r7]\n+\tvstr\td6, [r7, #8]\n \tadd\tsp, #20\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, r7, pc}\n \tvstr\td8, [r3]\n \tvstr\td8, [r7]\n \tadd\tsp, #20\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, r7, pc}\n-\tvstr\td18, [r3]\n-\tvstr\td18, [r7]\n-\tvstr\td18, [r7, #8]\n-\tb.n\tf7a <__gridxc_lda_MOD_exchng+0xd2>\n+\tvstr\td5, [r3]\n+\tvstr\td5, [r7]\n+\tvstr\td5, [r7, #8]\n+\tb.n\t10e2 <__gridxc_lda_MOD_exchng+0xd2>\n \tnop.w\n+\t...\n \t.word\t0xa4aeacc4\n \t.word\t0x3fce8ec8\n \t.word\t0x03cd5e97\n \t.word\t0x3fe38c63\n \t.word\t0x0a9843e0\n \t.word\t0x3f8cae89\n \t.word\t0xcf657063\n \t.word\t0x3ffec750\n \t.word\t0x8a43a042\n \t.word\t0x400484e0\n-\t.word\t0xf98d728b\n-\t.word\t0x3ff428a2\n \t.word\t0xe635ca2c\n \t.word\t0x3fd0a28b\n+\t.word\t0xf98d728b\n+\t.word\t0x3ff428a2\n \n-00001098 <__gridxc_lda_MOD_ldaxc>:\n+00001218 <__gridxc_lda_MOD_ldaxc>:\n __gridxc_lda_MOD_ldaxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3864]\t@ 0xf18\n \tsub\tsp, #188\t@ 0xbc\n \tadd\tr7, sp, #24\n \tldr.w\tr9, [r2]\n-\tldr.w\tr2, [pc, #1424]\t@ 1648 <__gridxc_lda_MOD_ldaxc+0x5b0>\n+\tldr\tr2, [pc, #960]\t@ (15f8 <__gridxc_lda_MOD_ldaxc+0x3e0>)\n \tmov\tsl, r3\n-\tldr.w\tr3, [pc, #1424]\t@ 164c <__gridxc_lda_MOD_ldaxc+0x5b4>\n+\tldr\tr3, [pc, #960]\t@ (15fc <__gridxc_lda_MOD_ldaxc+0x3e4>)\n \tldr.w\tr4, [r7, #208]\t@ 0xd0\n \tadd\tr2, pc\n \tstr\tr4, [r7, #40]\t@ 0x28\n \tldr.w\tr4, [r7, #212]\t@ 0xd4\n \tstr\tr4, [r7, #36]\t@ 0x24\n \tstr\tr0, [r7, #32]\n \tbic.w\tr0, r9, r9, asr #31\n@@ -1186,50 +1281,56 @@\n \tstr\tr3, [r7, #24]\n \tldr.w\tr3, [r7, #224]\t@ 0xe0\n \tstr\tr3, [r7, #52]\t@ 0x34\n \tldr.w\tr3, [r7, #228]\t@ 0xe4\n \tstr\tr0, [r7, #12]\n \tstr\tr3, [r7, #48]\t@ 0x30\n \tbic.w\tr3, r2, #4080\t@ 0xff0\n-\tldr.w\tr0, [pc, #1348]\t@ 1650 <__gridxc_lda_MOD_ldaxc+0x5b8>\n+\tldr\tr0, [pc, #888]\t@ (1600 <__gridxc_lda_MOD_ldaxc+0x3e8>)\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tstr\tr4, [r7, #20]\n \tadd\tr0, pc\n \tldr.w\tr4, [r7, #240]\t@ 0xf0\n \tstr\tr0, [r7, #8]\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr\tr4, [r7, #44]\t@ 0x2c\n-\tbeq.n\t1136 <__gridxc_lda_MOD_ldaxc+0x9e>\n+\tbeq.n\t12b0 <__gridxc_lda_MOD_ldaxc+0x98>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1128 <__gridxc_lda_MOD_ldaxc+0x90>\n+\tbne.n\t12a2 <__gridxc_lda_MOD_ldaxc+0x8a>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t14c2 <__gridxc_lda_MOD_ldaxc+0x42a>\n+\tbne.w\t168a <__gridxc_lda_MOD_ldaxc+0x472>\n \tadd\tr3, sp, #24\n \tcmp.w\tr9, #4\n \tstr\tr3, [r7, #0]\n-\tbeq.w\t12c0 <__gridxc_lda_MOD_ldaxc+0x228>\n+\tbeq.w\t1448 <__gridxc_lda_MOD_ldaxc+0x230>\n \tcmp.w\tr9, #0\n \tstr.w\tr9, [r7, #60]\t@ 0x3c\n-\tble.n\t11b0 <__gridxc_lda_MOD_ldaxc+0x118>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvldr\td16, [sl]\n+\tble.n\t133e <__gridxc_lda_MOD_ldaxc+0x126>\n+\tvldr\td7, [sl]\n+\tvldr\td6, [pc, #780]\t@ 15e8 <__gridxc_lda_MOD_ldaxc+0x3d0>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tcmp.w\tr9, #1\n-\tvmaxnm.f64\td16, d16, d17\n-\tvstr\td16, [r7, #80]\t@ 0x50\n-\tbeq.n\t117c <__gridxc_lda_MOD_ldaxc+0xe4>\n-\tvldr\td16, [sl, #8]\n-\tvmaxnm.f64\td16, d16, d17\n-\tvstr\td16, [r7, #88]\t@ 0x58\n+\tvstr\td7, [r7, #80]\t@ 0x50\n+\tbeq.n\t130a <__gridxc_lda_MOD_ldaxc+0xf2>\n+\tvldr\td7, [sl, #8]\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvstr\td7, [r7, #88]\t@ 0x58\n \tcmp.w\tr9, #0\n \tmov.w\tr6, r9, lsl #3\n \tldrd\tr5, fp, [r7, #48]\t@ 0x30\n \tit\tle\n \tmovle\tr6, #8\n \tmovs\tr4, #1\n \tstr\tr1, [r7, #4]\n@@ -1243,158 +1344,158 @@\n \tmov\tr2, r6\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadd\tfp, r8\n \tadd\tr5, r8\n \tcmp\tr9, r4\n-\tbge.n\t1190 <__gridxc_lda_MOD_ldaxc+0xf8>\n+\tbge.n\t131e <__gridxc_lda_MOD_ldaxc+0x106>\n \tldr\tr1, [r7, #4]\n \tcmp\tr1, #0\n-\tbeq.w\t130e <__gridxc_lda_MOD_ldaxc+0x276>\n+\tbeq.w\t1496 <__gridxc_lda_MOD_ldaxc+0x27e>\n \tldr\tr3, [r1, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t130e <__gridxc_lda_MOD_ldaxc+0x276>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr2, [r7, #20]\n+\tbeq.w\t1496 <__gridxc_lda_MOD_ldaxc+0x27e>\n+\tldr\tr3, [r7, #20]\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tcmp\tr2, #0\n \tit\tne\n \tcmpne\tr3, #0\n-\tbeq.w\t14b0 <__gridxc_lda_MOD_ldaxc+0x418>\n+\tbeq.w\t1678 <__gridxc_lda_MOD_ldaxc+0x460>\n \tldr\tr0, [r7, #44]\t@ 0x2c\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n \tcmp\tr0, #1\n-\tbeq.n\t11ea <__gridxc_lda_MOD_ldaxc+0x152>\n-\tldr.w\tr3, [pc, #1148]\t@ 1654 <__gridxc_lda_MOD_ldaxc+0x5bc>\n+\tbeq.n\t1374 <__gridxc_lda_MOD_ldaxc+0x15c>\n+\tldr\tr3, [pc, #668]\t@ (1604 <__gridxc_lda_MOD_ldaxc+0x3ec>)\n \tmovs\tr1, #31\n \tldr\tr2, [r7, #8]\n-\tldr.w\tr0, [pc, #1144]\t@ 1658 <__gridxc_lda_MOD_ldaxc+0x5c0>\n+\tldr\tr0, [pc, #668]\t@ (1608 <__gridxc_lda_MOD_ldaxc+0x3f0>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [r7, #12]\n \tldr\tr0, [r7, #44]\t@ 0x2c\n \tmvns\tr5, r3\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n \tldr\tr3, [r7, #0]\n \tmov\tr4, r0\n-\tldr.w\tr1, [pc, #1120]\t@ 165c <__gridxc_lda_MOD_ldaxc+0x5c4>\n+\tldr\tr1, [pc, #648]\t@ (160c <__gridxc_lda_MOD_ldaxc+0x3f4>)\n \tadd.w\tr2, r7, #80\t@ 0x50\n \tstr\tr3, [sp, #0]\n \tadd.w\tr3, r7, #128\t@ 0x80\n \tldr\tr0, [r7, #20]\n \tadd\tr1, pc\n \tstr\tr3, [sp, #4]\n \tadd.w\tr3, r7, #72\t@ 0x48\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_lda_exc_vxc_fxc>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_lda_exc_vxc_fxc\n \tcmp\tr4, #1\n-\tbeq.w\t15d0 <__gridxc_lda_MOD_ldaxc+0x538>\n-\tvldr\td16, [r7, #72]\t@ 0x48\n-\tvldr\td17, [r7, #128]\t@ 0x80\n+\tbeq.w\t1798 <__gridxc_lda_MOD_ldaxc+0x580>\n+\tvldr\td7, [r7, #72]\t@ 0x48\n+\tvldr\td6, [r7, #128]\t@ 0x80\n \tcmp\tr4, #0\n-\tbeq.w\t14d8 <__gridxc_lda_MOD_ldaxc+0x440>\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n+\tbeq.w\t16a0 <__gridxc_lda_MOD_ldaxc+0x488>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tcmp.w\tr9, #0\n-\tvmul.f64\td16, d16, d18\n-\tvmul.f64\td17, d17, d18\n-\tvstr\td16, [r3]\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td7, [r3]\n \tldr\tr3, [r7, #36]\t@ 0x24\n-\tvstr\td16, [r3]\n-\tble.w\t16cc <__gridxc_lda_MOD_ldaxc+0x634>\n+\tvstr\td7, [r3]\n+\tble.w\t1852 <__gridxc_lda_MOD_ldaxc+0x63a>\n \tldr\tr3, [r7, #0]\n \tcmp.w\tr9, #1\n-\tvldr\td16, [r3]\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td16, [r7, #112]\t@ 0x70\n-\tbeq.w\t16e0 <__gridxc_lda_MOD_ldaxc+0x648>\n-\tvldr\td20, [r3, #8]\n-\tvldr\td21, [r7, #144]\t@ 0x90\n+\tvldr\td7, [r3]\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td7, [r7, #112]\t@ 0x70\n+\tbeq.w\t1866 <__gridxc_lda_MOD_ldaxc+0x64e>\n+\tvldr\td2, [r3, #8]\n+\tvldr\td3, [r7, #144]\t@ 0x90\n \tldr\tr3, [r7, #12]\n-\tvldr\td19, [r7, #136]\t@ 0x88\n-\tvmul.f64\td20, d20, d18\n+\tvldr\td4, [r7, #136]\t@ 0x88\n+\tvmul.f64\td2, d2, d5\n \tldr\tr2, [r7, #52]\t@ 0x34\n \trsb\tr3, r3, #3\n-\tvmul.f64\td21, d21, d18\n-\tvstr\td16, [r7, #96]\t@ 0x60\n-\tvmul.f64\td18, d19, d18\n+\tvmul.f64\td3, d3, d5\n+\tvstr\td7, [r7, #96]\t@ 0x60\n+\tvmul.f64\td5, d4, d5\n \tmov\tr5, r2\n \tadd.w\tr3, r2, r3, lsl #3\n-\tvstr\td20, [r7, #120]\t@ 0x78\n-\tvstr\td17, [r2]\n-\tvstr\td20, [r7, #104]\t@ 0x68\n-\tvstr\td21, [r3, #16]\n-\tvstr\td18, [r3, #8]\n-\tvstr\td18, [r2, #8]\n+\tvstr\td2, [r7, #120]\t@ 0x78\n+\tvstr\td6, [r2]\n+\tvstr\td2, [r7, #104]\t@ 0x68\n+\tvstr\td3, [r3, #16]\n+\tvstr\td5, [r3, #8]\n+\tvstr\td5, [r2, #8]\n \tldr\tr3, [r7, #48]\t@ 0x30\n \tmov.w\tr6, r9, lsl #3\n \tmovs\tr4, #0\n \tmov\tr1, r5\n \tmov\tr0, r3\n \tmov\tr2, r6\n \tadds\tr4, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmov\tr3, r0\n \tadd\tr3, r8\n \tadd\tr5, r8\n-\tcmp\tr4, r9\n-\tbne.n\t12a8 <__gridxc_lda_MOD_ldaxc+0x210>\n-\tb.n\t1496 <__gridxc_lda_MOD_ldaxc+0x3fe>\n-\tvldr\td17, [sl, #24]\n-\tvmov.f64\td21, #16\t@ 0x40800000 4.0\n-\tvldr\td19, [sl, #16]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td16, [sl]\n+\tcmp\tr9, r4\n+\tbne.n\t1430 <__gridxc_lda_MOD_ldaxc+0x218>\n+\tb.n\t165e <__gridxc_lda_MOD_ldaxc+0x446>\n+\tvldr\td5, [sl, #24]\n+\tvmov.f64\td2, #16\t@ 0x40800000 4.0\n+\tvldr\td1, [sl, #16]\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvldr\td7, [sl]\n \tmovs\tr3, #2\n-\tvmul.f64\td17, d17, d17\n-\tvldr\td20, [sl, #8]\n-\tvfma.f64\td17, d19, d19\n+\tvmul.f64\td5, d5, d5\n+\tvldr\td3, [sl, #8]\n+\tvmla.f64\td5, d1, d1\n \tstr\tr3, [r7, #60]\t@ 0x3c\n-\tvsub.f64\td19, d16, d20\n-\tvadd.f64\td16, d16, d20\n-\tvmul.f64\td17, d17, d21\n-\tvfma.f64\td17, d19, d19\n-\tvsqrt.f64\td8, d17\n-\tvadd.f64\td17, d16, d8\n-\tvsub.f64\td16, d16, d8\n-\tvmul.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td17, [r7, #80]\t@ 0x50\n-\tb.n\t1178 <__gridxc_lda_MOD_ldaxc+0xe0>\n-\tldr\tr3, [pc, #848]\t@ (1660 <__gridxc_lda_MOD_ldaxc+0x5c8>)\n+\tvsub.f64\td6, d7, d3\n+\tvadd.f64\td7, d7, d3\n+\tvmul.f64\td6, d6, d6\n+\tvmla.f64\td6, d5, d2\n+\tvsqrt.f64\td8, d6\n+\tvadd.f64\td6, d7, d8\n+\tvsub.f64\td7, d7, d8\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td6, [r7, #80]\t@ 0x50\n+\tb.n\t1306 <__gridxc_lda_MOD_ldaxc+0xee>\n+\tldr\tr3, [pc, #376]\t@ (1610 <__gridxc_lda_MOD_ldaxc+0x3f8>)\n \tmovs\tr2, #2\n \tldr\tr4, [r7, #32]\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tadd\tr3, pc\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 134a <__gridxc_lda_MOD_ldaxc+0x2b2>\n-\tldr\tr3, [pc, #832]\t@ (1664 <__gridxc_lda_MOD_ldaxc+0x5cc>)\n+\tcbz\tr0, 14d2 <__gridxc_lda_MOD_ldaxc+0x2ba>\n+\tldr\tr3, [pc, #360]\t@ (1614 <__gridxc_lda_MOD_ldaxc+0x3fc>)\n \tmovs\tr2, #2\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tmov\tr1, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 134a <__gridxc_lda_MOD_ldaxc+0x2b2>\n-\tldr\tr3, [pc, #816]\t@ (1668 <__gridxc_lda_MOD_ldaxc+0x5d0>)\n+\tcbz\tr0, 14d2 <__gridxc_lda_MOD_ldaxc+0x2ba>\n+\tldr\tr3, [pc, #344]\t@ (1618 <__gridxc_lda_MOD_ldaxc+0x400>)\n \tmovs\tr2, #2\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tmov\tr1, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t1568 <__gridxc_lda_MOD_ldaxc+0x4d0>\n+\tbne.w\t1730 <__gridxc_lda_MOD_ldaxc+0x518>\n \tldr\tr3, [r7, #48]\t@ 0x30\n \tadd.w\tr2, r7, #96\t@ 0x60\n \tstr\tr3, [sp, #16]\n \tadd.w\tr1, r7, #60\t@ 0x3c\n \tldr\tr3, [r7, #52]\t@ 0x34\n \tstr\tr3, [sp, #12]\n \tldr\tr3, [r7, #36]\t@ 0x24\n@@ -1403,76 +1504,101 @@\n \tldr\tr0, [r7, #16]\n \tstr\tr2, [sp, #8]\n \tadd.w\tr2, r7, #112\t@ 0x70\n \tstr\tr2, [sp, #4]\n \tadd.w\tr2, r7, #80\t@ 0x50\n \tbl\t0 <__gridxc_lda_MOD_pzxc>\n \tcmp.w\tr9, #4\n-\tbne.w\t148c <__gridxc_lda_MOD_ldaxc+0x3f4>\n-\tvldr\td17, [pc, #708]\t@ 1640 <__gridxc_lda_MOD_ldaxc+0x5a8>\n-\tvmov.f64\td25, #112\t@ 0x3f800000 1.0\n-\tvldr\td20, [r7, #104]\t@ 0x68\n-\tvldr\td16, [r7, #96]\t@ 0x60\n-\tvadd.f64\td8, d8, d17\n-\tvldr\td23, [r7, #120]\t@ 0x78\n-\tvldr\td19, [r7, #112]\t@ 0x70\n-\tvsub.f64\td24, d16, d20\n-\tvadd.f64\td16, d16, d20\n-\tvldr\td21, [sl, #8]\n-\tvdiv.f64\td20, d25, d8\n-\tvldr\td18, [sl]\n-\tvsub.f64\td17, d19, d23\n-\tvadd.f64\td19, d19, d23\n-\tvldr\td22, [sl, #16]\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tvsub.f64\td18, d18, d21\n-\tvldr\td21, [sl, #24]\n+\tbne.w\t1652 <__gridxc_lda_MOD_ldaxc+0x43a>\n+\tvldr\td5, [pc, #236]\t@ 15f0 <__gridxc_lda_MOD_ldaxc+0x3d8>\n+\tvmov.f64\td0, #112\t@ 0x3f800000 1.0\n+\tvldr\td2, [r7, #120]\t@ 0x78\n+\tvldr\td7, [r7, #112]\t@ 0x70\n+\tvadd.f64\td8, d8, d5\n+\tvldr\td4, [sl]\n+\tvldr\td6, [sl, #8]\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvsub.f64\td3, d7, d2\n+\tvadd.f64\td7, d7, d2\n+\tvldr\td1, [sl, #16]\n+\tvdiv.f64\td2, d0, d8\n+\tvsub.f64\td6, d4, d6\n \tldr\tr3, [r7, #28]\n-\tvmul.f64\td26, d17, d22\n-\tvmov.f64\td25, d19\n-\tvmul.f64\td22, d22, d24\n-\tldr\tr2, [r7, #24]\n-\tvmul.f64\td27, d17, d18\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td17, d17, d21\n-\tvmul.f64\td21, d21, d24\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td25, d27, d20\n-\tvfms.f64\td19, d27, d20\n-\tvfma.f64\td24, d18, d20\n-\tvfms.f64\td16, d18, d20\n-\tvmul.f64\td26, d26, d20\n-\tvmul.f64\td17, d17, d20\n-\tvmul.f64\td22, d22, d20\n-\tvmul.f64\td20, d21, d20\n-\tvstr\td26, [r3, #16]\n-\tvstr\td17, [r3, #24]\n-\tvmul.f64\td25, d25, d23\n-\tvmul.f64\td19, d19, d23\n-\tvmul.f64\td24, d24, d23\n-\tvmul.f64\td16, d16, d23\n-\tvstr\td22, [r2, #16]\n-\tvstr\td20, [r2, #24]\n-\tvstr\td25, [r3]\n-\tvstr\td19, [r3, #8]\n-\tvstr\td24, [r2]\n-\tvstr\td16, [r2, #8]\n-\tldr\tr2, [pc, #564]\t@ (166c <__gridxc_lda_MOD_ldaxc+0x5d4>)\n-\tldr\tr3, [pc, #528]\t@ (164c <__gridxc_lda_MOD_ldaxc+0x5b4>)\n+\tvmul.f64\td8, d3, d1\n+\tvmul.f64\td4, d3, d6\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td8, d8, d2\n+\tvadd.f64\td0, d7, d4\n+\tvsub.f64\td7, d7, d4\n+\tvstr\td8, [r3, #16]\n+\tvldr\td4, [sl, #24]\n+\tvldr\td8, [r7, #104]\t@ 0x68\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td0, d0, d5\n+\tvmul.f64\td3, d3, d4\n+\tvstr\td7, [r3, #8]\n+\tvldr\td7, [r7, #96]\t@ 0x60\n+\tvmul.f64\td3, d3, d2\n+\tvstr\td0, [r3]\n+\tvsub.f64\td0, d7, d8\n+\tvadd.f64\td7, d7, d8\n+\tvstr\td3, [r3, #24]\n+\tldr\tr3, [r7, #24]\n+\tvmul.f64\td6, d6, d0\n+\tvmul.f64\td3, d1, d0\n+\tvmul.f64\td4, d4, d0\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td3, d3, d2\n+\tvmul.f64\td4, d4, d2\n+\tvadd.f64\td2, d7, d6\n+\tvsub.f64\td7, d7, d6\n+\tvstr\td3, [r3, #16]\n+\tvstr\td4, [r3, #24]\n+\tvmul.f64\td2, d2, d5\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td2, [r3]\n+\tvstr\td7, [r3, #8]\n+\tldr\tr2, [pc, #92]\t@ (161c <__gridxc_lda_MOD_ldaxc+0x404>)\n+\tldr\tr3, [pc, #56]\t@ (15fc <__gridxc_lda_MOD_ldaxc+0x3e4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [r7, #156]\t@ 0x9c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t174c <__gridxc_lda_MOD_ldaxc+0x6b4>\n+\tbne.w\t18d2 <__gridxc_lda_MOD_ldaxc+0x6ba>\n \tadds\tr7, #164\t@ 0xa4\n \tmov\tsp, r7\n \tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x812dea11\n+\t.word\t0x3d719799\n+\t.word\t0x000003b6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x0000036a\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x00000296\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000278\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000016c\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x0000015c\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x0000014e\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x00000056\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \tldr\tr1, [r7, #40]\t@ 0x28\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n \tldr\tr3, [r7, #12]\n \tldr\tr2, [r7, #48]\t@ 0x30\n \tldrd\tsl, fp, [r7, #128]\t@ 0x80\n@@ -1480,54 +1606,55 @@\n \tldrd\tr0, r1, [r7, #136]\t@ 0x88\n \tadd.w\tr3, r2, r3, lsl #3\n \tldrd\tr4, r5, [r7, #144]\t@ 0x90\n \tstrd\tsl, fp, [r2]\n \tstrd\tr4, r5, [r3, #16]\n \tstrd\tr0, r1, [r3, #8]\n \tstrd\tr0, r1, [r2, #8]\n-\tmov.w\tr6, r9, lsl #3\n \tcmp.w\tr9, #0\n-\tble.n\t1436 <__gridxc_lda_MOD_ldaxc+0x39e>\n+\tit\tgt\n+\tmovgt.w\tr6, r9, lsl #3\n+\tble.n\t15be <__gridxc_lda_MOD_ldaxc+0x3a6>\n \tmov\tr2, r6\n \tadd.w\tr1, r7, #112\t@ 0x70\n \tldr\tr0, [r7, #28]\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr0, [r7, #24]\n \tmov\tr2, r6\n \tadd.w\tr1, r7, #96\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\t1436 <__gridxc_lda_MOD_ldaxc+0x39e>\n-\tldr\tr3, [pc, #416]\t@ (1654 <__gridxc_lda_MOD_ldaxc+0x5bc>)\n+\tb.n\t15be <__gridxc_lda_MOD_ldaxc+0x3a6>\n+\tldr\tr3, [pc, #604]\t@ (18d8 <__gridxc_lda_MOD_ldaxc+0x6c0>)\n \tmovs\tr1, #31\n \tldr\tr2, [r7, #8]\n-\tldr\tr0, [pc, #440]\t@ (1670 <__gridxc_lda_MOD_ldaxc+0x5d8>)\n+\tldr\tr0, [pc, #604]\t@ (18dc <__gridxc_lda_MOD_ldaxc+0x6c4>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t11cc <__gridxc_lda_MOD_ldaxc+0x134>\n+\tb.n\t135a <__gridxc_lda_MOD_ldaxc+0x142>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #24\n \tcmp.w\tr9, #4\n \tstr\tr3, [r7, #0]\n-\tbne.w\t1150 <__gridxc_lda_MOD_ldaxc+0xb8>\n-\tb.n\t12c0 <__gridxc_lda_MOD_ldaxc+0x228>\n+\tbne.w\t12ca <__gridxc_lda_MOD_ldaxc+0xb2>\n+\tb.n\t1448 <__gridxc_lda_MOD_ldaxc+0x230>\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tcmp.w\tr9, #0\n-\tvstr\td16, [r3]\n-\tble.w\t16c0 <__gridxc_lda_MOD_ldaxc+0x628>\n+\tvstr\td7, [r3]\n+\tble.w\t1846 <__gridxc_lda_MOD_ldaxc+0x62e>\n \tldr\tr3, [r7, #0]\n \tcmp.w\tr9, #1\n \tldrd\tr2, r3, [r3]\n \tstrd\tr2, r3, [r7, #112]\t@ 0x70\n-\tbeq.w\t16a2 <__gridxc_lda_MOD_ldaxc+0x60a>\n+\tbeq.w\t1828 <__gridxc_lda_MOD_ldaxc+0x610>\n \tldr\tr3, [r7, #12]\n \tcmp.w\tr9, #2\n \tldr\tr0, [r7, #48]\t@ 0x30\n \trsb\tr1, r3, #3\n \tldr\tr3, [r7, #0]\n \tldr\tr4, [r7, #36]\t@ 0x24\n \tadd.w\tr1, r0, r1, lsl #3\n@@ -1538,79 +1665,79 @@\n \tstrd\tr2, r3, [r0]\n \tstrd\tr2, r3, [r0, #8]\n \tstrd\tr2, r3, [r4]\n \tstrd\tr2, r3, [r7, #96]\t@ 0x60\n \tstrd\tr2, r3, [r7, #104]\t@ 0x68\n \tstrd\tr2, r3, [r1, #8]\n \tstrd\tr2, r3, [r1, #16]\n-\tbeq.n\t1542 <__gridxc_lda_MOD_ldaxc+0x4aa>\n+\tbeq.n\t170a <__gridxc_lda_MOD_ldaxc+0x4f2>\n \tstrd\tr2, r3, [r0, #32]\n \tstrd\tr2, r3, [r0, #40]\t@ 0x28\n \tldr\tr3, [r7, #12]\n \tldr\tr2, [r7, #52]\t@ 0x34\n \tldrd\tr0, r1, [r7, #144]\t@ 0x90\n \tadd.w\tr3, r5, r3, lsl #1\n \tadd.w\tr3, r2, r3, lsl #3\n-\tvstr\td17, [r2]\n+\tvstr\td6, [r2]\n \tstrd\tr0, r1, [r3, #16]\n \tldrd\tr0, r1, [r7, #136]\t@ 0x88\n \tstrd\tr0, r1, [r3, #8]\n \tstrd\tr0, r1, [r2, #8]\n-\tb.n\t148c <__gridxc_lda_MOD_ldaxc+0x3f4>\n-\tldr\tr3, [pc, #264]\t@ (1674 <__gridxc_lda_MOD_ldaxc+0x5dc>)\n+\tb.n\t1652 <__gridxc_lda_MOD_ldaxc+0x43a>\n+\tldr\tr3, [pc, #428]\t@ (18e0 <__gridxc_lda_MOD_ldaxc+0x6c8>)\n \tmovs\tr2, #2\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tmov\tr1, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t134a <__gridxc_lda_MOD_ldaxc+0x2b2>\n-\tldr\tr3, [pc, #248]\t@ (1678 <__gridxc_lda_MOD_ldaxc+0x5e0>)\n+\tbeq.w\t14d2 <__gridxc_lda_MOD_ldaxc+0x2ba>\n+\tldr\tr3, [pc, #412]\t@ (18e4 <__gridxc_lda_MOD_ldaxc+0x6cc>)\n \tmovs\tr2, #4\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tmov\tr1, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 15a6 <__gridxc_lda_MOD_ldaxc+0x50e>\n-\tldr\tr3, [pc, #232]\t@ (167c <__gridxc_lda_MOD_ldaxc+0x5e4>)\n+\tcbz\tr0, 176e <__gridxc_lda_MOD_ldaxc+0x556>\n+\tldr\tr3, [pc, #396]\t@ (18e8 <__gridxc_lda_MOD_ldaxc+0x6d0>)\n \tmovs\tr2, #4\n \tldr.w\tr0, [r7, #244]\t@ 0xf4\n \tmov\tr1, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t16ee <__gridxc_lda_MOD_ldaxc+0x656>\n+\tbne.w\t1874 <__gridxc_lda_MOD_ldaxc+0x65c>\n \tadd.w\tr5, r7, #80\t@ 0x50\n \tadd.w\tr4, r7, #60\t@ 0x3c\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tadd.w\tr2, r7, #112\t@ 0x70\n \tldr\tr0, [r7, #16]\n \tmov\tr1, r4\n \tstr\tr2, [sp, #0]\n \tmov\tr2, r5\n-\tbl\tea8 <__gridxc_lda_MOD_exchng>\n+\tbl\t1010 <__gridxc_lda_MOD_exchng>\n \tldr\tr2, [r7, #36]\t@ 0x24\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd.w\tr3, r7, #96\t@ 0x60\n-\tbl\t7c8 <__gridxc_lda_MOD_pw92c>\n-\tb.n\t1372 <__gridxc_lda_MOD_ldaxc+0x2da>\n+\tbl\t8a0 <__gridxc_lda_MOD_pw92c>\n+\tb.n\t14fa <__gridxc_lda_MOD_ldaxc+0x2e2>\n \tldr\tr1, [r7, #36]\t@ 0x24\n \tcmp.w\tr9, #0\n \tldrd\tr2, r3, [r7, #72]\t@ 0x48\n \tstrd\tr2, r3, [r1]\n-\tble.w\t145a <__gridxc_lda_MOD_ldaxc+0x3c2>\n+\tble.w\t1620 <__gridxc_lda_MOD_ldaxc+0x408>\n \tldr\tr0, [r7, #0]\n \tcmp.w\tr9, #1\n \tldrd\tr2, r3, [r0]\n \tstrd\tr2, r3, [r7, #96]\t@ 0x60\n-\tbeq.n\t1680 <__gridxc_lda_MOD_ldaxc+0x5e8>\n+\tbeq.n\t1806 <__gridxc_lda_MOD_ldaxc+0x5ee>\n \tldr\tr3, [r7, #12]\n \tcmp.w\tr9, #2\n \tldr\tr4, [r7, #52]\t@ 0x34\n \trsb\tr1, r3, #3\n \tldrd\tr2, r3, [r0, #8]\n \tadd.w\tr1, r4, r1, lsl #3\n \tldr\tr0, [r7, #40]\t@ 0x28\n@@ -1620,88 +1747,57 @@\n \tstrd\tr2, r3, [r4]\n \tstrd\tr2, r3, [r4, #8]\n \tstrd\tr2, r3, [r0]\n \tstrd\tr2, r3, [r7, #112]\t@ 0x70\n \tstrd\tr2, r3, [r7, #120]\t@ 0x78\n \tstrd\tr2, r3, [r1, #8]\n \tstrd\tr2, r3, [r1, #16]\n-\tbeq.w\t1464 <__gridxc_lda_MOD_ldaxc+0x3cc>\n+\tbeq.w\t162a <__gridxc_lda_MOD_ldaxc+0x412>\n \tstrd\tr2, r3, [r4, #32]\n \tstrd\tr2, r3, [r4, #40]\t@ 0x28\n-\tb.n\t1464 <__gridxc_lda_MOD_ldaxc+0x3cc>\n-\tnop\n-\t.word\t0x812dea11\n-\t.word\t0x3d719799\n-\t.word\t0x00000582\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000534\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000470\n- R_ARM_REL32\t.LC1\n-\t.word\t0x00000450\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000344\n- R_ARM_REL32\t.LC3\n-\t.word\t0x00000334\n- R_ARM_REL32\t.LC4\n-\t.word\t0x00000326\n- R_ARM_REL32\t.LC5\n-\t.word\t0x0000022e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001b2\n- R_ARM_REL32\t.LC0\n-\t.word\t0x000000fe\n- R_ARM_REL32\t.LC6\n-\t.word\t0x000000ec\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000000de\n- R_ARM_REL32\t.LC8\n+\tb.n\t162a <__gridxc_lda_MOD_ldaxc+0x412>\n \tldr\tr1, [r7, #40]\t@ 0x28\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r7, #112]\t@ 0x70\n \tmovs\tr6, #8\n \tstrd\tr2, r3, [r1]\n \tldr\tr1, [r7, #52]\t@ 0x34\n \tstrd\tr2, r3, [r1]\n \tldr\tr1, [r7, #48]\t@ 0x30\n \tldrd\tr2, r3, [r7, #128]\t@ 0x80\n \tstrd\tr2, r3, [r1]\n-\tb.n\t1496 <__gridxc_lda_MOD_ldaxc+0x3fe>\n+\tb.n\t165e <__gridxc_lda_MOD_ldaxc+0x446>\n \tldr\tr3, [r7, #52]\t@ 0x34\n \tmovs\tr2, #0\n \tldr\tr1, [r7, #36]\t@ 0x24\n \tmovs\tr6, #8\n-\tvstr\td17, [r3]\n+\tvstr\td6, [r3]\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n \tldr\tr1, [r7, #48]\t@ 0x30\n \tstrd\tr2, r3, [r7, #96]\t@ 0x60\n \tstrd\tr2, r3, [r1]\n-\tb.n\t1496 <__gridxc_lda_MOD_ldaxc+0x3fe>\n+\tb.n\t165e <__gridxc_lda_MOD_ldaxc+0x446>\n \tldr\tr1, [r7, #36]\t@ 0x24\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\t1542 <__gridxc_lda_MOD_ldaxc+0x4aa>\n-\tvldr\td16, [r7, #136]\t@ 0x88\n+\tb.n\t170a <__gridxc_lda_MOD_ldaxc+0x4f2>\n+\tvldr\td7, [r7, #136]\t@ 0x88\n \tldr\tr3, [r7, #52]\t@ 0x34\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td16, [r3]\n-\tvstr\td16, [r3, #8]\n-\tb.n\t1436 <__gridxc_lda_MOD_ldaxc+0x39e>\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td7, [r3]\n+\tvstr\td7, [r3, #8]\n+\tb.n\t15be <__gridxc_lda_MOD_ldaxc+0x3a6>\n \tldr\tr3, [r7, #52]\t@ 0x34\n-\tvstr\td16, [r7, #96]\t@ 0x60\n+\tvstr\td7, [r7, #96]\t@ 0x60\n \tmov\tr5, r3\n-\tvstr\td17, [r3]\n-\tb.n\t12a0 <__gridxc_lda_MOD_ldaxc+0x208>\n+\tvstr\td6, [r3]\n+\tb.n\t1428 <__gridxc_lda_MOD_ldaxc+0x210>\n \tmov\tr3, r4\n \tldr.w\tr2, [r7, #244]\t@ 0xf4\n \tadd.w\tr1, r7, #64\t@ 0x40\n \tadd.w\tr0, r7, #68\t@ 0x44\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n \tldr\tr6, [r7, #68]\t@ 0x44\n@@ -1709,39 +1805,48 @@\n \tcmp\tr5, #1\n \tmov\tr0, r5\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr6, [sp, #0]\n-\tldr\tr3, [pc, #56]\t@ (1750 <__gridxc_lda_MOD_ldaxc+0x6b8>)\n+\tldr\tr3, [pc, #80]\t@ (18ec <__gridxc_lda_MOD_ldaxc+0x6d4>)\n \tmov\tr1, r0\n \tldr.w\tr8, [r7, #64]\t@ 0x40\n \tmov\tr4, r0\n \tadd\tr3, pc\n \tmovs\tr2, #22\n \tmov\tr0, r5\n \tstr.w\tr8, [sp, #4]\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tcmp\tr6, #0\n-\tble.n\t1736 <__gridxc_lda_MOD_ldaxc+0x69e>\n+\tble.n\t18bc <__gridxc_lda_MOD_ldaxc+0x6a4>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #28]\t@ (1754 <__gridxc_lda_MOD_ldaxc+0x6bc>)\n+\tldr\tr3, [pc, #24]\t@ (18d8 <__gridxc_lda_MOD_ldaxc+0x6c0>)\n \tmov\tr0, r4\n \tldr\tr2, [r7, #8]\n \tmov\tr1, r5\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t1372 <__gridxc_lda_MOD_ldaxc+0x2da>\n+\tb.n\t14fa <__gridxc_lda_MOD_ldaxc+0x2e2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x0000002e\n- R_ARM_REL32\t.LC9\n+\tnop\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x00000256\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000001a2\n+ R_ARM_REL32\t.LC6\n+\t.word\t0x00000190\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x00000182\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x00000044\n+ R_ARM_REL32\t.LC9\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "m_io.F90.o", "source2": "m_io.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 4336 (bytes into file)\n+ Start of section headers: 4324 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x10f0:\n+There are 11 section headers, starting at offset 0x10e4:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 0004ec 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 000e30 000260 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 000520 000170 00 WA 0 0 8\n- [ 4] .bss NOBITS 00000000 000690 000058 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 000690 0000ef 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 00077f 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 00077f 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 0007b4 0003b0 10 9 31 4\n- [ 9] .strtab STRTAB 00000000 000b64 0002cc 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 001090 00005f 00 0 0 1\n+ [ 2] .rel.text REL 00000000 000e24 000260 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 000520 00016c 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 00068c 000058 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 00068c 0000ef 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 00077b 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 00077b 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 0007a8 0003b0 10 9 31 4\n+ [ 9] .strtab STRTAB 00000000 000b58 0002cc 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 001084 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -51,12 +51,12 @@\n 47: 000004cd 16 FUNC GLOBAL DEFAULT 1 __gridxc_io_MOD_io_setout\n 48: 000004dd 16 FUNC GLOBAL DEFAULT 1 __gridxc_io_MOD_io_seterr\n 49: 00000050 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_used\n 50: 00000000 4 OBJECT GLOBAL HIDDEN 3 __gridxc_io_MOD_stdout\n 51: 00000054 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_stderr\n 52: 00000008 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_opened\n 53: 0000000c 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_named\n- 54: 00000008 360 OBJECT GLOBAL HIDDEN 3 __gridxc_io_MOD_lun_is_free\n+ 54: 00000004 360 OBJECT GLOBAL HIDDEN 3 __gridxc_io_MOD_lun_is_free\n 55: 00000004 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_iostat\n 56: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_i\n 57: 00000044 11 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_form\n 58: 00000010 50 OBJECT GLOBAL HIDDEN 4 __gridxc_io_MOD_filename\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Relocation section '.rel.text' at offset 0xe30 contains 76 entries:\n+Relocation section '.rel.text' at offset 0xe24 contains 76 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000054 0000200a R_ARM_THM_CALL 00000000 _gfortran_st_write\n 00000060 0000210a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n 00000066 0000220a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n 000000a4 0000200a R_ARM_THM_CALL 00000000 _gfortran_st_write\n 000000ae 0000230a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n 000000b8 0000210a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -297,15 +297,15 @@\n R_ARM_THM_CALL\t_gfortran_st_close\n \tcmp\tr4, #89\t@ 0x59\n \tbhi.n\t2a4 <__gridxc_io_MOD_io_close+0x4c>\n \tldr\tr3, [pc, #48]\t@ (2cc <__gridxc_io_MOD_io_close+0x74>)\n \tmovs\tr2, #1\n \tadd\tr3, pc\n \tadd.w\tr3, r3, r4, lsl #2\n-\tstr\tr2, [r3, #8]\n+\tstr\tr2, [r3, #4]\n \tldr\tr2, [pc, #40]\t@ (2d0 <__gridxc_io_MOD_io_close+0x78>)\n \tldr\tr3, [pc, #32]\t@ (2c8 <__gridxc_io_MOD_io_close+0x70>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #36]\t@ 0x24\n \teors\tr2, r3\n@@ -377,15 +377,15 @@\n \tsubs\tr4, #10\n \tcmp\tr4, #89\t@ 0x59\n \tbhi.n\t350 <__gridxc_io_MOD_io_reserve+0x7c>\n \tldr\tr3, [pc, #72]\t@ (390 <__gridxc_io_MOD_io_reserve+0xbc>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tadd.w\tr3, r3, r4, lsl #2\n-\tstr\tr2, [r3, #8]\n+\tstr\tr2, [r3, #4]\n \tldr\tr2, [pc, #64]\t@ (394 <__gridxc_io_MOD_io_reserve+0xc0>)\n \tldr\tr3, [pc, #44]\t@ (380 <__gridxc_io_MOD_io_reserve+0xac>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #276]\t@ 0x114\n \teors\tr2, r3\n@@ -445,15 +445,15 @@\n \tmov.w\tr2, #0\n \tb.n\t3dc <__gridxc_io_MOD_io_assign+0x44>\n \tadds\tr3, #1\n \tstr\tr3, [r4, #0]\n \tcmp\tr3, #99\t@ 0x63\n \tbgt.n\t458 <__gridxc_io_MOD_io_assign+0xc0>\n \tadd.w\tr2, r8, r3, lsl #2\n-\tldr.w\tr2, [r2, #-32]\n+\tldr.w\tr2, [r2, #-36]\n \tcmp\tr2, #0\n \tbeq.n\t3d4 <__gridxc_io_MOD_io_assign+0x3c>\n \tadd\tr0, sp, #4\n \tldr\tr1, [pc, #172]\t@ (498 <__gridxc_io_MOD_io_assign+0x100>)\n \tadd.w\tr2, r5, #80\t@ 0x50\n \tmov.w\tip, #114\t@ 0x72\n \tadd\tr1, pc\n@@ -467,15 +467,15 @@\n \tbl\t0 <_gfortran_st_inquire>\n R_ARM_THM_CALL\t_gfortran_st_inquire\n \tldr\tr2, [r5, #4]\n \tldr\tr3, [r4, #0]\n \tcbnz\tr2, 440 <__gridxc_io_MOD_io_assign+0xa8>\n \tldr\tr1, [r5, #80]\t@ 0x50\n \tadd.w\tr0, r8, r3, lsl #2\n-\tstr.w\tr2, [r0, #-32]\n+\tstr.w\tr2, [r0, #-36]\n \tcmp\tr1, #0\n \tbne.n\t3d4 <__gridxc_io_MOD_io_assign+0x3c>\n \tldr\tr2, [pc, #116]\t@ (49c <__gridxc_io_MOD_io_assign+0x104>)\n \tldr\tr3, [pc, #92]\t@ (488 <__gridxc_io_MOD_io_assign+0xf0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n@@ -488,15 +488,15 @@\n \tmovs\tr2, #1\n \tstr\tr2, [r5, #80]\t@ 0x50\n \tsub.w\tr2, r3, #10\n \tadds\tr3, #1\n \tcmp\tr3, #99\t@ 0x63\n \tstr\tr3, [r4, #0]\n \tadd.w\tr2, r8, r2, lsl #2\n-\tstr.w\tr9, [r2, #8]\n+\tstr.w\tr9, [r2, #4]\n \tble.n\t3dc <__gridxc_io_MOD_io_assign+0x44>\n \tldr\tr2, [pc, #68]\t@ (4a0 <__gridxc_io_MOD_io_assign+0x108>)\n \tldr\tr3, [pc, #44]\t@ (488 <__gridxc_io_MOD_io_assign+0xf0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #276]\t@ 0x114\n"}, {"source1": "readelf --wide --decompress --hex-dump=.data {}", "source2": "readelf --wide --decompress --hex-dump=.data {}", "unified_diff": "@@ -1,10 +1,10 @@\n \n Hex dump of section '.data':\n- 0x00000000 06000000 00000000 01000000 01000000 ................\n+ 0x00000000 06000000 01000000 01000000 01000000 ................\n 0x00000010 01000000 01000000 01000000 01000000 ................\n 0x00000020 01000000 01000000 01000000 01000000 ................\n 0x00000030 01000000 01000000 01000000 01000000 ................\n 0x00000040 01000000 01000000 01000000 01000000 ................\n 0x00000050 01000000 01000000 01000000 01000000 ................\n 0x00000060 01000000 01000000 01000000 01000000 ................\n 0x00000070 01000000 01000000 01000000 01000000 ................\n@@ -18,9 +18,9 @@\n 0x000000f0 01000000 01000000 01000000 01000000 ................\n 0x00000100 01000000 01000000 01000000 01000000 ................\n 0x00000110 01000000 01000000 01000000 01000000 ................\n 0x00000120 01000000 01000000 01000000 01000000 ................\n 0x00000130 01000000 01000000 01000000 01000000 ................\n 0x00000140 01000000 01000000 01000000 01000000 ................\n 0x00000150 01000000 01000000 01000000 01000000 ................\n- 0x00000160 01000000 01000000 01000000 01000000 ................\n+ 0x00000160 01000000 01000000 01000000 ............\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "m_walltime.F90.o", "source2": "m_walltime.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 1184 (bytes into file)\n+ Start of section headers: 1180 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 10\n Section header string table index: 9\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,19 +1,19 @@\n-There are 10 section headers, starting at offset 0x4a0:\n+There are 10 section headers, starting at offset 0x49c:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 000128 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 0003d8 000078 08 I 7 1 4\n+ [ 2] .rel.text REL 00000000 0003d4 000078 08 I 7 1 4\n [ 3] .data PROGBITS 00000000 00015c 000004 00 WA 0 0 4\n [ 4] .bss NOBITS 00000000 000160 000020 00 WA 0 0 8\n [ 5] .note.GNU-stack PROGBITS 00000000 000160 000000 00 0 0 1\n- [ 6] .ARM.attributes ARM_ATTRIBUTES 00000000 000160 000033 00 0 0 1\n- [ 7] .symtab SYMTAB 00000000 000194 000120 10 8 7 4\n- [ 8] .strtab STRTAB 00000000 0002b4 000123 00 0 0 1\n- [ 9] .shstrtab STRTAB 00000000 000450 000050 00 0 0 1\n+ [ 6] .ARM.attributes ARM_ATTRIBUTES 00000000 000160 00002d 00 0 0 1\n+ [ 7] .symtab SYMTAB 00000000 000190 000120 10 8 7 4\n+ [ 8] .strtab STRTAB 00000000 0002b0 000123 00 0 0 1\n+ [ 9] .shstrtab STRTAB 00000000 00044c 000050 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Relocation section '.rel.text' at offset 0x3d8 contains 15 entries:\n+Relocation section '.rel.text' at offset 0x3d4 contains 15 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000036 0000090a R_ARM_THM_CALL 00000000 _gfortran_system_clock_8\n 00000050 0000070a R_ARM_THM_CALL 00000000 __aeabi_l2d\n 000000a2 0000070a R_ARM_THM_CALL 00000000 __aeabi_l2d\n 000000bc 0000090a R_ARM_THM_CALL 00000000 _gfortran_system_clock_8\n 000000cc 0000090a R_ARM_THM_CALL 00000000 _gfortran_system_clock_8\n 000000dc 0000070a R_ARM_THM_CALL 00000000 __aeabi_l2d\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -34,24 +34,24 @@\n \tcmp\tr5, r0\n \tsbcs.w\tr3, r7, r1\n \tblt.n\t92 <__gridxc_walltime_MOD_wall_time+0x92>\n \tsubs\tr0, r5, r0\n \tsbc.w\tr1, r7, r1\n \tbl\t0 <__aeabi_l2d>\n R_ARM_THM_CALL\t__aeabi_l2d\n-\tvldr\td17, [r6, #8]\n-\tvmov\td18, r0, r1\n-\tvdiv.f64\td16, d18, d17\n+\tvldr\td6, [r6, #8]\n+\tvmov\td5, r0, r1\n+\tvdiv.f64\td7, d5, d6\n \tldr\tr3, [pc, #184]\t@ (11c <__gridxc_walltime_MOD_wall_time+0x11c>)\n \tadd\tr3, pc\n-\tvldr\td17, [r3, #24]\n+\tvldr\td6, [r3, #24]\n \tstrd\tr5, r7, [r3, #16]\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r4]\n-\tvstr\td16, [r3, #24]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r4]\n+\tvstr\td7, [r3, #24]\n \tldr\tr2, [pc, #164]\t@ (120 <__gridxc_walltime_MOD_wall_time+0x120>)\n \tldr\tr3, [pc, #152]\t@ (114 <__gridxc_walltime_MOD_wall_time+0x114>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #28]\n \teors\tr2, r3\n@@ -63,17 +63,17 @@\n \tsubs\tr0, r3, r0\n \tldr\tr3, [r6, #4]\n \tsbc.w\tr1, r3, r1\n \tadds\tr0, r0, r5\n \tadc.w\tr1, r7, r1\n \tbl\t0 <__aeabi_l2d>\n R_ARM_THM_CALL\t__aeabi_l2d\n-\tvldr\td17, [r6, #8]\n-\tvmov\td18, r0, r1\n-\tvdiv.f64\td16, d18, d17\n+\tvldr\td6, [r6, #8]\n+\tvmov\td5, r0, r1\n+\tvdiv.f64\td7, d5, d6\n \tb.n\t60 <__gridxc_walltime_MOD_wall_time+0x60>\n \tmovs\tr2, #0\n \tldr\tr6, [pc, #108]\t@ (124 <__gridxc_walltime_MOD_wall_time+0x124>)\n \tmov\tr0, r2\n \tmov\tr1, sp\n \tbl\t0 <_gfortran_system_clock_8>\n R_ARM_THM_CALL\t_gfortran_system_clock_8\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "mesh1d.F90.o", "source2": "mesh1d.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 23108 (bytes into file)\n+ Start of section headers: 23200 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x5a44:\n+There are 12 section headers, starting at offset 0x5aa0:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 00387c 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 004f04 000ad8 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 0038b8 000028 00 WA 0 0 8\n- [ 4] .bss NOBITS 00000000 0038e0 000194 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 0038e0 000684 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 003f68 000010 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 003f78 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 003f78 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 003fac 0008c0 10 10 91 4\n- [10] .strtab STRTAB 00000000 00486c 000696 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 0059dc 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 003894 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 004f50 000ae8 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0038d0 000028 00 WA 0 0 8\n+ [ 4] .bss NOBITS 00000000 0038f8 000184 00 WA 0 0 8\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0038f8 000684 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 003f80 000010 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 003f90 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 003f90 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 003fc0 0008f0 10 10 93 4\n+ [10] .strtab STRTAB 00000000 0048b0 00069d 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 005a38 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Symbol table '.symtab' contains 140 entries:\n+Symbol table '.symtab' contains 143 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 5: 00000028 0 NOTYPE LOCAL DEFAULT 5 .LC1\n@@ -48,96 +48,99 @@\n 44: 000003a4 0 NOTYPE LOCAL DEFAULT 5 .LC32\n 45: 000003c0 0 NOTYPE LOCAL DEFAULT 5 .LC33\n 46: 00000414 0 NOTYPE LOCAL DEFAULT 5 .LC34\n 47: 00000460 0 NOTYPE LOCAL DEFAULT 5 .LC35\n 48: 0000047c 0 NOTYPE LOCAL DEFAULT 5 .LC36\n 49: 000004a0 0 NOTYPE LOCAL DEFAULT 5 .LC37\n 50: 00000808 0 NOTYPE LOCAL DEFAULT 1 $t\n- 51: 00000d40 0 NOTYPE LOCAL DEFAULT 1 $d\n- 52: 00000da8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 53: 000012f0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 54: 0000131c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 55: 00001a50 0 NOTYPE LOCAL DEFAULT 1 $d\n- 56: 00001ac0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 57: 00001d98 0 NOTYPE LOCAL DEFAULT 1 $d\n- 58: 00000809 5868 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_set_mesh.localalias\n- 59: 000004c4 0 NOTYPE LOCAL DEFAULT 5 .LC40\n- 60: 000004ec 0 NOTYPE LOCAL DEFAULT 5 .LC41\n- 61: 00001ef4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 62: 000021a8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 63: 00000528 0 NOTYPE LOCAL DEFAULT 5 .LC42\n- 64: 000021f0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 65: 000021f1 2052 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_derivative.localalias\n- 66: 00002670 0 NOTYPE LOCAL DEFAULT 1 $d\n- 67: 000026ac 0 NOTYPE LOCAL DEFAULT 1 $t\n- 68: 000029d0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 69: 00000560 0 NOTYPE LOCAL DEFAULT 5 .LC43\n- 70: 000029f4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 71: 00002c3a 0 NOTYPE LOCAL DEFAULT 1 $d\n- 72: 00002c3e 0 NOTYPE LOCAL DEFAULT 1 $t\n- 73: 00002dc8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 74: 000029f5 1060 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_integral.localalias\n- 75: 00000594 0 NOTYPE LOCAL DEFAULT 5 .LC44\n- 76: 000005c4 0 NOTYPE LOCAL DEFAULT 5 .LC45\n- 77: 00000600 0 NOTYPE LOCAL DEFAULT 5 .LC46\n- 78: 00000638 0 NOTYPE LOCAL DEFAULT 5 .LC47\n- 79: 00000644 0 NOTYPE LOCAL DEFAULT 5 .LC48\n- 80: 00002e18 0 NOTYPE LOCAL DEFAULT 1 $t\n- 81: 00003478 0 NOTYPE LOCAL DEFAULT 1 $d\n- 82: 000034b4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 83: 00003778 0 NOTYPE LOCAL DEFAULT 1 $d\n- 84: 00000668 0 NOTYPE LOCAL DEFAULT 5 .LC49\n- 85: 000037a0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 86: 00003870 0 NOTYPE LOCAL DEFAULT 1 $d\n- 87: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 88: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 89: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 90: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 91: 00000001 904 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_locate\n- 92: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n- 93: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_polint\n- 94: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n- 95: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 96: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 97: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 98: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 99: 00000389 868 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_get_mesh\n- 100: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 101: 000006ed 284 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_set_interpolation\n- 102: 00000809 5868 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_set_mesh\n- 103: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 104: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 105: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n- 106: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 107: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n- 108: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n- 109: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n- 110: 00001ef5 764 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_interpolation_local\n- 111: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_dx\n- 112: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_evaluate_spline_dx\n- 113: 000021f1 2052 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_derivative\n- 114: 000029f5 1060 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_integral\n- 115: 00002e19 2440 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_numerov\n- 116: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n- 117: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n- 118: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_real_write\n- 119: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n- 120: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n- 121: 000037a1 220 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_get_n\n- 122: 00000020 8 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_ypn\n- 123: 00000018 8 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_yp1\n- 124: 000000d0 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp4\n- 125: 000000ac 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp3\n- 126: 00000088 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp2\n- 127: 00000064 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp1\n- 128: 00000004 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xi\n- 129: 000000f8 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_sqrxp\n- 130: 00000170 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s2\n- 131: 00000148 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s1\n- 132: 00000120 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s0\n- 133: 00000000 11 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_mesh_type\n- 134: 00000040 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_ivec\n- 135: 0000000c 10 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_interpolation_method\n- 136: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_defined_mesh\n- 137: 00000028 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_d\n- 138: 00000030 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_b\n- 139: 00000038 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_aa\n+ 51: 00000d88 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 52: 00000de8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 53: 00001330 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 54: 00001354 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 55: 00001588 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 56: 000015a0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 57: 00001ac0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 58: 00001b28 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 59: 00001dc0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 60: 00000809 5908 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_set_mesh.localalias\n+ 61: 000004c4 0 NOTYPE LOCAL DEFAULT 5 .LC40\n+ 62: 000004ec 0 NOTYPE LOCAL DEFAULT 5 .LC41\n+ 63: 00001f1c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 64: 000021e8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 65: 00000528 0 NOTYPE LOCAL DEFAULT 5 .LC42\n+ 66: 00002230 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 67: 00002231 1996 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_derivative.localalias\n+ 68: 000026e8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 69: 00002724 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 70: 000029e8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 71: 00000560 0 NOTYPE LOCAL DEFAULT 5 .LC43\n+ 72: 000029fc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 73: 00002c42 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 74: 00002c46 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 75: 00002de0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 76: 000029fd 1084 FUNC LOCAL DEFAULT 1 __gridxc_mesh1d_MOD_integral.localalias\n+ 77: 00000594 0 NOTYPE LOCAL DEFAULT 5 .LC44\n+ 78: 000005c4 0 NOTYPE LOCAL DEFAULT 5 .LC45\n+ 79: 00000600 0 NOTYPE LOCAL DEFAULT 5 .LC46\n+ 80: 00000638 0 NOTYPE LOCAL DEFAULT 5 .LC47\n+ 81: 00000644 0 NOTYPE LOCAL DEFAULT 5 .LC48\n+ 82: 00002e38 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 83: 00003468 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 84: 000034a4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 85: 000037a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 86: 00000668 0 NOTYPE LOCAL DEFAULT 5 .LC49\n+ 87: 000037c0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 88: 00003888 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 89: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 90: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 91: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 92: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 93: 00000001 904 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_locate\n+ 94: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n+ 95: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_polint\n+ 96: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n+ 97: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 98: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 99: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 100: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 101: 00000389 868 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_get_mesh\n+ 102: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 103: 000006ed 284 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_set_interpolation\n+ 104: 00000809 5908 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_set_mesh\n+ 105: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 106: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 107: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n+ 108: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 109: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n+ 110: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n+ 111: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n+ 112: 00001f1d 788 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_interpolation_local\n+ 113: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_dx\n+ 114: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_evaluate_spline_dx\n+ 115: 00002231 1996 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_derivative\n+ 116: 000029fd 1084 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_integral\n+ 117: 00002e39 2440 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_numerov\n+ 118: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 119: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n+ 120: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_real_write\n+ 121: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 122: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n+ 123: 000037c1 212 FUNC GLOBAL DEFAULT 1 __gridxc_mesh1d_MOD_get_n\n+ 124: 00000000 0 NOTYPE GLOBAL DEFAULT UND lround\n+ 125: 00000020 8 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_ypn\n+ 126: 00000018 8 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_yp1\n+ 127: 000000d0 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp4\n+ 128: 000000ac 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp3\n+ 129: 00000088 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp2\n+ 130: 00000064 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xp1\n+ 131: 00000004 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_xi\n+ 132: 000000f4 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_sqrxp\n+ 133: 00000160 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s2\n+ 134: 0000013c 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s1\n+ 135: 00000118 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_s0\n+ 136: 00000000 11 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_mesh_type\n+ 137: 00000040 36 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_ivec\n+ 138: 0000000c 10 OBJECT GLOBAL HIDDEN 3 __gridxc_mesh1d_MOD_interpolation_method\n+ 139: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_defined_mesh\n+ 140: 00000028 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_d\n+ 141: 00000030 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_b\n+ 142: 00000038 8 OBJECT GLOBAL HIDDEN 4 __gridxc_mesh1d_MOD_aa\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,350 +1,352 @@\n \n-Relocation section '.rel.text' at offset 0x4f04 contains 347 entries:\n+Relocation section '.rel.text' at offset 0x4f50 contains 349 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000054 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000082 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000001b6 00005d0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_polint\n-00000278 00005e0a R_ARM_THM_CALL 00000000 log\n-00000320 00005f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000054 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000082 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000001d4 00005f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_polint\n+0000029a 0000600a R_ARM_THM_CALL 00000000 log\n+00000322 0000610a R_ARM_THM_CALL 00000000 __stack_chk_fail\n 00000330 00000203 R_ARM_REL32 00000000 .bss\n-00000334 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000338 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000033c 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000340 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000334 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000338 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000033c 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000340 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n 00000344 00000403 R_ARM_REL32 00000000 .LC0\n 00000348 00000103 R_ARM_REL32 00000000 .data\n 0000034c 00000503 R_ARM_REL32 00000028 .LC1\n 00000350 00000203 R_ARM_REL32 00000000 .bss\n 00000354 00000803 R_ARM_REL32 00000064 .LC4\n 00000358 00000103 R_ARM_REL32 00000000 .data\n 0000035c 00000203 R_ARM_REL32 00000000 .bss\n 00000360 00000703 R_ARM_REL32 0000003c .LC3\n 00000364 00000203 R_ARM_REL32 00000000 .bss\n 00000368 00000203 R_ARM_REL32 00000000 .bss\n 0000036c 00000203 R_ARM_REL32 00000000 .bss\n-00000370 00000903 R_ARM_REL32 00000070 .LC5\n-00000374 00000703 R_ARM_REL32 0000003c .LC3\n-00000378 00000203 R_ARM_REL32 00000000 .bss\n-0000037c 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000370 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000374 00000903 R_ARM_REL32 00000070 .LC5\n+00000378 00000703 R_ARM_REL32 0000003c .LC3\n+0000037c 00000203 R_ARM_REL32 00000000 .bss\n 00000380 00000203 R_ARM_REL32 00000000 .bss\n 00000384 00000a03 R_ARM_REL32 00000098 .LC6\n-000004a8 0000640a R_ARM_THM_CALL 00000000 memcpy\n-000004d8 0000640a R_ARM_THM_CALL 00000000 memcpy\n-0000053e 0000640a R_ARM_THM_CALL 00000000 memcpy\n-0000056a 0000640a R_ARM_THM_CALL 00000000 memcpy\n-000006c0 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000004a8 0000660a R_ARM_THM_CALL 00000000 memcpy\n+000004d8 0000660a R_ARM_THM_CALL 00000000 memcpy\n+0000053e 0000660a R_ARM_THM_CALL 00000000 memcpy\n+0000056a 0000660a R_ARM_THM_CALL 00000000 memcpy\n+000006c0 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 000006c4 00000203 R_ARM_REL32 00000000 .bss\n-000006c8 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000006c8 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n 000006cc 00000e03 R_ARM_REL32 000000c8 .LC7\n 000006d0 00000203 R_ARM_REL32 00000000 .bss\n 000006d4 00000203 R_ARM_REL32 00000000 .bss\n 000006d8 00000203 R_ARM_REL32 00000000 .bss\n 000006dc 00000203 R_ARM_REL32 00000000 .bss\n 000006e0 00000203 R_ARM_REL32 00000000 .bss\n 000006e4 00000203 R_ARM_REL32 00000000 .bss\n 000006e8 00000203 R_ARM_REL32 00000000 .bss\n-00000714 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000726 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000736 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000746 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000714 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000726 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000736 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000746 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 000007d4 00001203 R_ARM_REL32 000000ec .LC8\n-000007d8 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000007d8 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 000007dc 00001303 R_ARM_REL32 000000f4 .LC9\n 000007e0 00001403 R_ARM_REL32 000000fc .LC10\n 000007e4 00001503 R_ARM_REL32 00000108 .LC11\n 000007e8 00000103 R_ARM_REL32 00000000 .data\n 000007ec 00001403 R_ARM_REL32 000000fc .LC10\n 000007f0 00000103 R_ARM_REL32 00000000 .data\n 000007f4 00000103 R_ARM_REL32 00000000 .data\n 000007f8 00001203 R_ARM_REL32 000000ec .LC8\n 000007fc 00000103 R_ARM_REL32 00000000 .data\n-00000800 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000800 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n 00000804 00001603 R_ARM_REL32 00000114 .LC12\n-00000906 0000670a R_ARM_THM_CALL 00000000 free\n-00000918 0000670a R_ARM_THM_CALL 00000000 free\n-0000092a 0000670a R_ARM_THM_CALL 00000000 free\n-0000093c 0000670a R_ARM_THM_CALL 00000000 free\n-0000094e 0000670a R_ARM_THM_CALL 00000000 free\n-0000095e 0000670a R_ARM_THM_CALL 00000000 free\n-0000096c 0000670a R_ARM_THM_CALL 00000000 free\n-0000097c 0000670a R_ARM_THM_CALL 00000000 free\n-0000098e 0000670a R_ARM_THM_CALL 00000000 free\n-000009a0 0000670a R_ARM_THM_CALL 00000000 free\n-000009f6 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000a46 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000a7e 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000ab4 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000aee 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000b42 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000b76 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000bac 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000be4 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000c20 0000680a R_ARM_THM_CALL 00000000 malloc\n-00000ca2 00005e0a R_ARM_THM_CALL 00000000 log\n-00000cea 0000690a R_ARM_THM_CALL 00000000 exp\n-00000d0c 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000d58 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d5c 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000d60 00001903 R_ARM_REL32 00000140 .LC13\n-00000d64 00001a03 R_ARM_REL32 00000180 .LC14\n-00000d68 00001b03 R_ARM_REL32 000001bc .LC15\n-00000d6c 00003103 R_ARM_REL32 000004a0 .LC37\n-00000d70 00000203 R_ARM_REL32 00000000 .bss\n-00000d74 00000203 R_ARM_REL32 00000000 .bss\n-00000d78 00000203 R_ARM_REL32 00000000 .bss\n-00000d7c 00000203 R_ARM_REL32 00000000 .bss\n-00000d80 00000203 R_ARM_REL32 00000000 .bss\n-00000d84 00000203 R_ARM_REL32 00000000 .bss\n-00000d88 00000203 R_ARM_REL32 00000000 .bss\n-00000d8c 00000203 R_ARM_REL32 00000000 .bss\n-00000d90 00000203 R_ARM_REL32 00000000 .bss\n-00000d94 00000603 R_ARM_REL32 00000030 .LC2\n-00000d98 00000103 R_ARM_REL32 00000000 .data\n-00000d9c 00000103 R_ARM_REL32 00000000 .data\n-00000da0 00000503 R_ARM_REL32 00000028 .LC1\n-00000da4 00000203 R_ARM_REL32 00000000 .bss\n-00000dfe 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000f08 0000640a R_ARM_THM_CALL 00000000 memcpy\n-00001308 00000103 R_ARM_REL32 00000000 .data\n-0000130c 00000803 R_ARM_REL32 00000064 .LC4\n-00001310 00000103 R_ARM_REL32 00000000 .data\n-00001314 00000803 R_ARM_REL32 00000064 .LC4\n-00001318 00000203 R_ARM_REL32 00000000 .bss\n-0000155a 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001638 00006a0a R_ARM_THM_CALL 00000000 memset\n-0000164a 00006a0a R_ARM_THM_CALL 00000000 memset\n-00001658 00006a0a R_ARM_THM_CALL 00000000 memset\n-00001694 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001756 0000690a R_ARM_THM_CALL 00000000 exp\n-00001840 00005e0a R_ARM_THM_CALL 00000000 log\n-0000189e 0000690a R_ARM_THM_CALL 00000000 exp\n-000019b2 0000690a R_ARM_THM_CALL 00000000 exp\n-00001a60 00000203 R_ARM_REL32 00000000 .bss\n-00001a64 00000203 R_ARM_REL32 00000000 .bss\n-00001a68 00000203 R_ARM_REL32 00000000 .bss\n-00001a6c 00000203 R_ARM_REL32 00000000 .bss\n-00001a70 00000503 R_ARM_REL32 00000028 .LC1\n-00001a74 00000103 R_ARM_REL32 00000000 .data\n-00001a78 00000203 R_ARM_REL32 00000000 .bss\n-00001a7c 00000203 R_ARM_REL32 00000000 .bss\n-00001a80 00000803 R_ARM_REL32 00000064 .LC4\n-00001a84 00000103 R_ARM_REL32 00000000 .data\n-00001a88 00000203 R_ARM_REL32 00000000 .bss\n-00001a8c 00000603 R_ARM_REL32 00000030 .LC2\n-00001a90 00000103 R_ARM_REL32 00000000 .data\n-00001a94 00000103 R_ARM_REL32 00000000 .data\n-00001a98 00000503 R_ARM_REL32 00000028 .LC1\n-00001a9c 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001aa0 00003003 R_ARM_REL32 0000047c .LC36\n-00001aa4 00000203 R_ARM_REL32 00000000 .bss\n-00001aa8 00000203 R_ARM_REL32 00000000 .bss\n-00001aac 00000203 R_ARM_REL32 00000000 .bss\n-00001ab0 00000203 R_ARM_REL32 00000000 .bss\n-00001ab4 00000103 R_ARM_REL32 00000000 .data\n-00001ab8 00000803 R_ARM_REL32 00000064 .LC4\n-00001abc 00002f03 R_ARM_REL32 00000460 .LC35\n-00001b3a 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001bcc 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001bdc 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001bec 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001bfa 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001c0a 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c18 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001c28 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c36 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001c46 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c54 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001c64 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c72 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001c82 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001c90 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001ca0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001cb0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001cc0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001cd0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001ce0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001cf0 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d00 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d10 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d20 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d28 00006d0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00001d38 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d46 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001d56 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d64 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001d74 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d82 00006b0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001d92 00006c0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00001d98 00000203 R_ARM_REL32 00000000 .bss\n-00001d9c 00000503 R_ARM_REL32 00000028 .LC1\n-00001da0 00000203 R_ARM_REL32 00000000 .bss\n-00001da4 00000103 R_ARM_REL32 00000000 .data\n-00001da8 00000203 R_ARM_REL32 00000000 .bss\n-00001dac 00000803 R_ARM_REL32 00000064 .LC4\n-00001db0 00002c03 R_ARM_REL32 000003a4 .LC32\n-00001db4 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001db8 00001c03 R_ARM_REL32 000001ec .LC16\n-00001dbc 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001dc0 00001e03 R_ARM_REL32 0000021c .LC18\n-00001dc4 00001f03 R_ARM_REL32 00000268 .LC19\n-00001dc8 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001dcc 00001e03 R_ARM_REL32 0000021c .LC18\n-00001dd0 00002c03 R_ARM_REL32 000003a4 .LC32\n-00001dd4 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001dd8 00002703 R_ARM_REL32 000002d4 .LC27\n-00001ddc 00002a03 R_ARM_REL32 00000320 .LC30\n-00001de0 00002e03 R_ARM_REL32 00000414 .LC34\n-00001de4 00002c03 R_ARM_REL32 000003a4 .LC32\n-00001de8 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001dec 00002803 R_ARM_REL32 000002d8 .LC28\n-00001df0 00002a03 R_ARM_REL32 00000320 .LC30\n-00001df4 00002e03 R_ARM_REL32 00000414 .LC34\n+0000090c 0000690a R_ARM_THM_CALL 00000000 free\n+0000091e 0000690a R_ARM_THM_CALL 00000000 free\n+00000930 0000690a R_ARM_THM_CALL 00000000 free\n+00000942 0000690a R_ARM_THM_CALL 00000000 free\n+00000954 0000690a R_ARM_THM_CALL 00000000 free\n+00000964 0000690a R_ARM_THM_CALL 00000000 free\n+00000972 0000690a R_ARM_THM_CALL 00000000 free\n+00000982 0000690a R_ARM_THM_CALL 00000000 free\n+00000994 0000690a R_ARM_THM_CALL 00000000 free\n+000009a6 0000690a R_ARM_THM_CALL 00000000 free\n+00000a06 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000a4a 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000a90 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000ad4 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000b14 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000b66 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000ba0 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000be0 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000c26 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000c66 00006a0a R_ARM_THM_CALL 00000000 malloc\n+00000cee 0000600a R_ARM_THM_CALL 00000000 log\n+00000d32 00006b0a R_ARM_THM_CALL 00000000 exp\n+00000d54 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000d98 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000d9c 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000da0 00001903 R_ARM_REL32 00000140 .LC13\n+00000da4 00001a03 R_ARM_REL32 00000180 .LC14\n+00000da8 00001b03 R_ARM_REL32 000001bc .LC15\n+00000dac 00003103 R_ARM_REL32 000004a0 .LC37\n+00000db0 00000203 R_ARM_REL32 00000000 .bss\n+00000db4 00000203 R_ARM_REL32 00000000 .bss\n+00000db8 00000203 R_ARM_REL32 00000000 .bss\n+00000dbc 00000203 R_ARM_REL32 00000000 .bss\n+00000dc0 00000203 R_ARM_REL32 00000000 .bss\n+00000dc4 00000203 R_ARM_REL32 00000000 .bss\n+00000dc8 00000203 R_ARM_REL32 00000000 .bss\n+00000dcc 00000203 R_ARM_REL32 00000000 .bss\n+00000dd0 00000203 R_ARM_REL32 00000000 .bss\n+00000dd4 00000603 R_ARM_REL32 00000030 .LC2\n+00000dd8 00000103 R_ARM_REL32 00000000 .data\n+00000ddc 00000103 R_ARM_REL32 00000000 .data\n+00000de0 00000503 R_ARM_REL32 00000028 .LC1\n+00000de4 00000203 R_ARM_REL32 00000000 .bss\n+00000e3e 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000f60 0000660a R_ARM_THM_CALL 00000000 memcpy\n+00001340 00000103 R_ARM_REL32 00000000 .data\n+00001344 00000803 R_ARM_REL32 00000064 .LC4\n+00001348 00000103 R_ARM_REL32 00000000 .data\n+0000134c 00000803 R_ARM_REL32 00000064 .LC4\n+00001350 00000203 R_ARM_REL32 00000000 .bss\n+00001590 00000203 R_ARM_REL32 00000000 .bss\n+00001594 00000203 R_ARM_REL32 00000000 .bss\n+00001598 00000203 R_ARM_REL32 00000000 .bss\n+0000159c 00000203 R_ARM_REL32 00000000 .bss\n+000015c0 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000016a2 00006c0a R_ARM_THM_CALL 00000000 memset\n+000016b4 00006c0a R_ARM_THM_CALL 00000000 memset\n+000016c2 00006c0a R_ARM_THM_CALL 00000000 memset\n+000016fe 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000017bc 00006b0a R_ARM_THM_CALL 00000000 exp\n+000018a6 0000600a R_ARM_THM_CALL 00000000 log\n+00001900 00006b0a R_ARM_THM_CALL 00000000 exp\n+00001a1a 00006b0a R_ARM_THM_CALL 00000000 exp\n+00001ad8 00000503 R_ARM_REL32 00000028 .LC1\n+00001adc 00000103 R_ARM_REL32 00000000 .data\n+00001ae0 00000203 R_ARM_REL32 00000000 .bss\n+00001ae4 00000203 R_ARM_REL32 00000000 .bss\n+00001ae8 00000803 R_ARM_REL32 00000064 .LC4\n+00001aec 00000103 R_ARM_REL32 00000000 .data\n+00001af0 00000203 R_ARM_REL32 00000000 .bss\n+00001af4 00000603 R_ARM_REL32 00000030 .LC2\n+00001af8 00000103 R_ARM_REL32 00000000 .data\n+00001afc 00000103 R_ARM_REL32 00000000 .data\n+00001b00 00000503 R_ARM_REL32 00000028 .LC1\n+00001b04 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001b08 00003003 R_ARM_REL32 0000047c .LC36\n+00001b0c 00000203 R_ARM_REL32 00000000 .bss\n+00001b10 00000203 R_ARM_REL32 00000000 .bss\n+00001b14 00000203 R_ARM_REL32 00000000 .bss\n+00001b18 00000203 R_ARM_REL32 00000000 .bss\n+00001b1c 00000103 R_ARM_REL32 00000000 .data\n+00001b20 00000803 R_ARM_REL32 00000064 .LC4\n+00001b24 00002f03 R_ARM_REL32 00000460 .LC35\n+00001ba0 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001bf4 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001c04 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c14 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c22 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001c32 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c40 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001c50 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c5e 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001c6e 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c7c 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001c8c 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001c9a 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001caa 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001cb8 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001cc8 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001cd8 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001ce8 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001cf8 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d08 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d18 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d28 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d38 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d48 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d50 00006f0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00001d60 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d6e 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001d7e 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001d8c 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001d9c 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001daa 00006d0a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001dba 00006e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001dc0 00000203 R_ARM_REL32 00000000 .bss\n+00001dc4 00000503 R_ARM_REL32 00000028 .LC1\n+00001dc8 00000203 R_ARM_REL32 00000000 .bss\n+00001dcc 00000103 R_ARM_REL32 00000000 .data\n+00001dd0 00000203 R_ARM_REL32 00000000 .bss\n+00001dd4 00000803 R_ARM_REL32 00000064 .LC4\n+00001dd8 00002c03 R_ARM_REL32 000003a4 .LC32\n+00001ddc 00002d03 R_ARM_REL32 000003c0 .LC33\n+00001de0 00001c03 R_ARM_REL32 000001ec .LC16\n+00001de4 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001de8 00001e03 R_ARM_REL32 0000021c .LC18\n+00001dec 00001f03 R_ARM_REL32 00000268 .LC19\n+00001df0 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001df4 00001e03 R_ARM_REL32 0000021c .LC18\n 00001df8 00002c03 R_ARM_REL32 000003a4 .LC32\n 00001dfc 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001e00 00002203 R_ARM_REL32 00000278 .LC22\n+00001e00 00002703 R_ARM_REL32 000002d4 .LC27\n 00001e04 00002a03 R_ARM_REL32 00000320 .LC30\n-00001e08 00002b03 R_ARM_REL32 00000358 .LC31\n+00001e08 00002e03 R_ARM_REL32 00000414 .LC34\n 00001e0c 00002c03 R_ARM_REL32 000003a4 .LC32\n 00001e10 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001e14 00002303 R_ARM_REL32 0000027c .LC23\n+00001e14 00002803 R_ARM_REL32 000002d8 .LC28\n 00001e18 00002a03 R_ARM_REL32 00000320 .LC30\n 00001e1c 00002e03 R_ARM_REL32 00000414 .LC34\n 00001e20 00002c03 R_ARM_REL32 000003a4 .LC32\n 00001e24 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001e28 00002503 R_ARM_REL32 000002cc .LC25\n+00001e28 00002203 R_ARM_REL32 00000278 .LC22\n 00001e2c 00002a03 R_ARM_REL32 00000320 .LC30\n-00001e30 00002e03 R_ARM_REL32 00000414 .LC34\n+00001e30 00002b03 R_ARM_REL32 00000358 .LC31\n 00001e34 00002c03 R_ARM_REL32 000003a4 .LC32\n 00001e38 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001e3c 00002603 R_ARM_REL32 000002d0 .LC26\n+00001e3c 00002303 R_ARM_REL32 0000027c .LC23\n 00001e40 00002a03 R_ARM_REL32 00000320 .LC30\n 00001e44 00002e03 R_ARM_REL32 00000414 .LC34\n-00001e48 00002003 R_ARM_REL32 00000270 .LC20\n-00001e4c 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e50 00001e03 R_ARM_REL32 0000021c .LC18\n-00001e54 00002103 R_ARM_REL32 00000274 .LC21\n-00001e58 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e5c 00001e03 R_ARM_REL32 0000021c .LC18\n-00001e60 00002203 R_ARM_REL32 00000278 .LC22\n-00001e64 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e68 00001e03 R_ARM_REL32 0000021c .LC18\n-00001e6c 00002303 R_ARM_REL32 0000027c .LC23\n-00001e70 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e74 00002403 R_ARM_REL32 00000280 .LC24\n-00001e78 00002503 R_ARM_REL32 000002cc .LC25\n-00001e7c 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e80 00002403 R_ARM_REL32 00000280 .LC24\n-00001e84 00002603 R_ARM_REL32 000002d0 .LC26\n-00001e88 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e8c 00002403 R_ARM_REL32 00000280 .LC24\n-00001e90 00002703 R_ARM_REL32 000002d4 .LC27\n-00001e94 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001e98 00002403 R_ARM_REL32 00000280 .LC24\n-00001e9c 00002803 R_ARM_REL32 000002d8 .LC28\n-00001ea0 00001d03 R_ARM_REL32 000001f4 .LC17\n-00001ea4 00002403 R_ARM_REL32 00000280 .LC24\n-00001ea8 00002903 R_ARM_REL32 000002dc .LC29\n-00001eac 00001c03 R_ARM_REL32 000001ec .LC16\n-00001eb0 00002a03 R_ARM_REL32 00000320 .LC30\n-00001eb4 00002b03 R_ARM_REL32 00000358 .LC31\n-00001eb8 00002c03 R_ARM_REL32 000003a4 .LC32\n-00001ebc 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001ec0 00001f03 R_ARM_REL32 00000268 .LC19\n-00001ec4 00002a03 R_ARM_REL32 00000320 .LC30\n-00001ec8 00002b03 R_ARM_REL32 00000358 .LC31\n-00001ecc 00002c03 R_ARM_REL32 000003a4 .LC32\n-00001ed0 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001ed4 00002003 R_ARM_REL32 00000270 .LC20\n+00001e48 00002c03 R_ARM_REL32 000003a4 .LC32\n+00001e4c 00002d03 R_ARM_REL32 000003c0 .LC33\n+00001e50 00002503 R_ARM_REL32 000002cc .LC25\n+00001e54 00002a03 R_ARM_REL32 00000320 .LC30\n+00001e58 00002e03 R_ARM_REL32 00000414 .LC34\n+00001e5c 00002c03 R_ARM_REL32 000003a4 .LC32\n+00001e60 00002d03 R_ARM_REL32 000003c0 .LC33\n+00001e64 00002603 R_ARM_REL32 000002d0 .LC26\n+00001e68 00002a03 R_ARM_REL32 00000320 .LC30\n+00001e6c 00002e03 R_ARM_REL32 00000414 .LC34\n+00001e70 00002003 R_ARM_REL32 00000270 .LC20\n+00001e74 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001e78 00001e03 R_ARM_REL32 0000021c .LC18\n+00001e7c 00002103 R_ARM_REL32 00000274 .LC21\n+00001e80 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001e84 00001e03 R_ARM_REL32 0000021c .LC18\n+00001e88 00002203 R_ARM_REL32 00000278 .LC22\n+00001e8c 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001e90 00001e03 R_ARM_REL32 0000021c .LC18\n+00001e94 00002303 R_ARM_REL32 0000027c .LC23\n+00001e98 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001e9c 00002403 R_ARM_REL32 00000280 .LC24\n+00001ea0 00002503 R_ARM_REL32 000002cc .LC25\n+00001ea4 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001ea8 00002403 R_ARM_REL32 00000280 .LC24\n+00001eac 00002603 R_ARM_REL32 000002d0 .LC26\n+00001eb0 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001eb4 00002403 R_ARM_REL32 00000280 .LC24\n+00001eb8 00002703 R_ARM_REL32 000002d4 .LC27\n+00001ebc 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001ec0 00002403 R_ARM_REL32 00000280 .LC24\n+00001ec4 00002803 R_ARM_REL32 000002d8 .LC28\n+00001ec8 00001d03 R_ARM_REL32 000001f4 .LC17\n+00001ecc 00002403 R_ARM_REL32 00000280 .LC24\n+00001ed0 00002903 R_ARM_REL32 000002dc .LC29\n+00001ed4 00001c03 R_ARM_REL32 000001ec .LC16\n 00001ed8 00002a03 R_ARM_REL32 00000320 .LC30\n 00001edc 00002b03 R_ARM_REL32 00000358 .LC31\n 00001ee0 00002c03 R_ARM_REL32 000003a4 .LC32\n 00001ee4 00002d03 R_ARM_REL32 000003c0 .LC33\n-00001ee8 00002103 R_ARM_REL32 00000274 .LC21\n+00001ee8 00001f03 R_ARM_REL32 00000268 .LC19\n 00001eec 00002a03 R_ARM_REL32 00000320 .LC30\n 00001ef0 00002b03 R_ARM_REL32 00000358 .LC31\n-00001fa6 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00001fba 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000202a 00005d0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_polint\n-000020de 00006f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-00002158 0000700a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_evaluate_spline_dx\n-000021a2 00005f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000021c0 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000021c4 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000021c8 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000021cc 00000103 R_ARM_REL32 00000000 .data\n-000021d0 00001203 R_ARM_REL32 000000ec .LC8\n-000021d4 00001403 R_ARM_REL32 000000fc .LC10\n-000021d8 00000203 R_ARM_REL32 00000000 .bss\n-000021dc 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000021e0 00003c03 R_ARM_REL32 000004ec .LC41\n-000021e4 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000021e8 00005703 R_ARM_REL32 00000000 .rodata\n-000021ec 00003b03 R_ARM_REL32 000004c4 .LC40\n-00002444 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002458 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002690 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002694 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002698 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000269c 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000026a0 00000103 R_ARM_REL32 00000000 .data\n-000026a4 00001203 R_ARM_REL32 000000ec .LC8\n-000026a8 00001403 R_ARM_REL32 000000fc .LC10\n-00002718 00006f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-000029ca 00005f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000029e8 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000029ec 00003f03 R_ARM_REL32 00000528 .LC42\n-000029f0 00005703 R_ARM_REL32 00000000 .rodata\n-00002ac4 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002b18 00006f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-00002c00 00005c0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002c68 00006f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-00002d34 00005f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002de0 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002de4 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002de8 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002dec 00000103 R_ARM_REL32 00000000 .data\n-00002df0 00001203 R_ARM_REL32 000000ec .LC8\n-00002df4 00000203 R_ARM_REL32 00000000 .bss\n-00002df8 00000103 R_ARM_REL32 00000000 .data\n-00002dfc 00005703 R_ARM_REL32 00000000 .rodata\n-00002e00 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002e04 00001403 R_ARM_REL32 000000fc .LC10\n-00002e08 00000203 R_ARM_REL32 00000000 .bss\n-00002e0c 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002e10 00004503 R_ARM_REL32 00000560 .LC43\n-00002e14 00005703 R_ARM_REL32 00000000 .rodata\n-00003000 00006a0a R_ARM_THM_CALL 00000000 memset\n-00003020 0000640a R_ARM_THM_CALL 00000000 memcpy\n-00003450 00006a0a R_ARM_THM_CALL 00000000 memset\n-0000346a 0000640a R_ARM_THM_CALL 00000000 memcpy\n-00003490 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003494 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003498 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001ef4 00002c03 R_ARM_REL32 000003a4 .LC32\n+00001ef8 00002d03 R_ARM_REL32 000003c0 .LC33\n+00001efc 00002003 R_ARM_REL32 00000270 .LC20\n+00001f00 00002a03 R_ARM_REL32 00000320 .LC30\n+00001f04 00002b03 R_ARM_REL32 00000358 .LC31\n+00001f08 00002c03 R_ARM_REL32 000003a4 .LC32\n+00001f0c 00002d03 R_ARM_REL32 000003c0 .LC33\n+00001f10 00002103 R_ARM_REL32 00000274 .LC21\n+00001f14 00002a03 R_ARM_REL32 00000320 .LC30\n+00001f18 00002b03 R_ARM_REL32 00000358 .LC31\n+00001fd0 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00001fe4 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000207c 00005f0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_polint\n+00002106 0000710a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+00002194 0000720a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_evaluate_spline_dx\n+000021e0 0000610a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002200 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002204 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002208 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000220c 00000103 R_ARM_REL32 00000000 .data\n+00002210 00001203 R_ARM_REL32 000000ec .LC8\n+00002214 00001403 R_ARM_REL32 000000fc .LC10\n+00002218 00000203 R_ARM_REL32 00000000 .bss\n+0000221c 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002220 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002224 00003e03 R_ARM_REL32 000004ec .LC41\n+00002228 00005903 R_ARM_REL32 00000000 .rodata\n+0000222c 00003d03 R_ARM_REL32 000004c4 .LC40\n+0000247e 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002492 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002700 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002704 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002708 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000270c 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002710 00000103 R_ARM_REL32 00000000 .data\n+00002714 00001203 R_ARM_REL32 000000ec .LC8\n+00002718 00001403 R_ARM_REL32 000000fc .LC10\n+0000271c 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002720 00004103 R_ARM_REL32 00000528 .LC42\n+0000273c 0000710a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+000029de 0000610a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000029f8 00005903 R_ARM_REL32 00000000 .rodata\n+00002acc 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002b20 0000710a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+00002c08 00005e0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002c70 0000710a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+00002d44 0000610a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002e00 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e04 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e08 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002e0c 00000103 R_ARM_REL32 00000000 .data\n+00002e10 00001203 R_ARM_REL32 000000ec .LC8\n+00002e14 00000203 R_ARM_REL32 00000000 .bss\n+00002e18 00000103 R_ARM_REL32 00000000 .data\n+00002e1c 00005903 R_ARM_REL32 00000000 .rodata\n+00002e20 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002e24 00001403 R_ARM_REL32 000000fc .LC10\n+00002e28 00000203 R_ARM_REL32 00000000 .bss\n+00002e2c 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002e30 00004703 R_ARM_REL32 00000560 .LC43\n+00002e34 00005903 R_ARM_REL32 00000000 .rodata\n+00003020 00006c0a R_ARM_THM_CALL 00000000 memset\n+00003040 0000660a R_ARM_THM_CALL 00000000 memcpy\n+00003480 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003484 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003488 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000348c 00000203 R_ARM_REL32 00000000 .bss\n+00003490 00000203 R_ARM_REL32 00000000 .bss\n+00003494 00000203 R_ARM_REL32 00000000 .bss\n+00003498 00000203 R_ARM_REL32 00000000 .bss\n 0000349c 00000203 R_ARM_REL32 00000000 .bss\n 000034a0 00000203 R_ARM_REL32 00000000 .bss\n-000034a4 00000203 R_ARM_REL32 00000000 .bss\n-000034a8 00000203 R_ARM_REL32 00000000 .bss\n-000034ac 00000203 R_ARM_REL32 00000000 .bss\n-000034b0 00000203 R_ARM_REL32 00000000 .bss\n-000036de 0000740a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000036ea 0000750a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000036f4 0000760a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n-000036fa 0000770a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0000370e 0000780a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000372c 0000670a R_ARM_THM_CALL 00000000 free\n-00003746 0000640a R_ARM_THM_CALL 00000000 memcpy\n-00003772 00005f0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00003780 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003784 00004c03 R_ARM_REL32 000005c4 .LC45\n-00003788 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000378c 0000611a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003790 00004b03 R_ARM_REL32 00000594 .LC44\n-00003794 00004d03 R_ARM_REL32 00000600 .LC46\n-00003798 00004e03 R_ARM_REL32 00000638 .LC47\n-0000379c 00004f03 R_ARM_REL32 00000644 .LC48\n-00003846 00005e0a R_ARM_THM_CALL 00000000 log\n-00003856 00005e0a R_ARM_THM_CALL 00000000 log\n-00003870 00006019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003874 0000621a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003878 00005403 R_ARM_REL32 00000668 .LC49\n-0000050c 0000641e R_ARM_THM_JUMP24 00000000 memcpy\n+000034b4 00006c0a R_ARM_THM_CALL 00000000 memset\n+000034ce 0000660a R_ARM_THM_CALL 00000000 memcpy\n+00003706 0000760a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00003712 0000770a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+0000371c 0000780a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n+00003722 0000790a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00003736 00007a0a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00003754 0000690a R_ARM_THM_CALL 00000000 free\n+0000376e 0000660a R_ARM_THM_CALL 00000000 memcpy\n+0000379a 0000610a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000037a0 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000037a4 00004e03 R_ARM_REL32 000005c4 .LC45\n+000037a8 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000037ac 0000631a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000037b0 00004d03 R_ARM_REL32 00000594 .LC44\n+000037b4 00004f03 R_ARM_REL32 00000600 .LC46\n+000037b8 00005003 R_ARM_REL32 00000638 .LC47\n+000037bc 00005103 R_ARM_REL32 00000644 .LC48\n+00003864 0000600a R_ARM_THM_CALL 00000000 log\n+00003874 0000600a R_ARM_THM_CALL 00000000 log\n+0000387c 00007c0a R_ARM_THM_CALL 00000000 lround\n+00003888 00006219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000388c 0000641a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003890 00005603 R_ARM_REL32 00000668 .LC49\n+0000050c 0000661e R_ARM_THM_JUMP24 00000000 memcpy\n+00003822 00007c1e R_ARM_THM_JUMP24 00000000 lround\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,34 +1,44 @@\n-4%}DzD+FB\n-(M(J}DzD\n+,%}DzD+FB\n+'M'J}DzD\n+{I\"F{HyDxD\n yJzIzHzDyDxD\n xJyIyHzDyDxD\n+wI\"FwHyDxD\n vJvIwHzDyDxD\n+uI\"FuHyDxD\n sJtItHzDyDxD\n+rI\"FrHyDxD\n qJqIrHzDyDxD\n+pI\"FpHyDxD\n nJoIoHzDyDxD\n+mI\"FmHyDxD\n lJlImHzDyDxD\n+kI\"FkHyDxD\n iJjIjHzDyDxD\n hJiIiHzDyDxD\n gJhIhHzDyDxD\n fJgIgHzDyDxD\n eJfIfHzDyDxD\n dJeIeHzDyDxD\n cJdIdHzDyDxD\n bJcIcHzDyDxD\n aJbIbHzDyDxD\n _J`I`HzDyDxD\n+^I\"F^HyDxD\n ]J]I^HzDyDxD\n+\\I\"F\\HyDxD\n ZJ[I[HzDyDxD\n+YI\"FYHyDxD\n XJXIYHzDyDxD\n 0;azD+h{a\n-PK8!PHxDZ\n-vcH#sK3!zhrH\n-@F{D;f9K\n-.I\"\"@FyD\n+OK8!OHxDZ\n+zgJ#yK3!zhxH\n+u{D;f8K<$O\n+,I\"\"@FyD\n unknown \n spline \n mesh1D locate: ERROR: mesh not defined\n logarithmic\n mesh1D locate: ERROR: x0 out of range\n numerical\n mesh1D locate: ERROR: unknown mesh type\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -5,30 +5,30 @@\n \n 00000000 <__gridxc_mesh1d_MOD_locate>:\n __gridxc_mesh1d_MOD_locate.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d12}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3952]\t@ 0xf70\n+\tstr.w\tr0, [ip, #3960]\t@ 0xf78\n \tldr\tr3, [pc, #792]\t@ (330 <__gridxc_mesh1d_MOD_locate+0x330>)\n-\tsub\tsp, #68\t@ 0x44\n+\tsub\tsp, #60\t@ 0x3c\n \tldr\tr2, [pc, #792]\t@ (334 <__gridxc_mesh1d_MOD_locate+0x334>)\n \tmov\tr8, r0\n \tldr\tr1, [pc, #792]\t@ (338 <__gridxc_mesh1d_MOD_locate+0x338>)\n \tadd\tr3, pc\n \tadd\tr2, pc\n-\tstr\tr2, [sp, #20]\n+\tstr\tr2, [sp, #12]\n \tmov\tr4, r2\n \tldr\tr2, [pc, #788]\t@ (33c <__gridxc_mesh1d_MOD_locate+0x33c>)\n \tadd\tr1, pc\n \tldr\tr3, [r3, #0]\n \tldr\tr2, [r1, r2]\n \tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #52]\t@ 0x34\n \tmov.w\tr2, #0\n \tcbnz\tr3, 46 <__gridxc_mesh1d_MOD_locate+0x46>\n \tldr\tr3, [pc, #772]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n \tmovs\tr1, #38\t@ 0x26\n \tldr\tr0, [pc, #772]\t@ (344 <__gridxc_mesh1d_MOD_locate+0x344>)\n \tadd\tr0, pc\n \tldr\tr3, [r4, r3]\n@@ -40,160 +40,172 @@\n \tmovs\tr0, #11\n \tadd\tr4, pc\n \tadd\tr3, pc\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t2ae <__gridxc_mesh1d_MOD_locate+0x2ae>\n+\tbeq.w\t2b0 <__gridxc_mesh1d_MOD_locate+0x2b0>\n \tldr\tr6, [pc, #752]\t@ (350 <__gridxc_mesh1d_MOD_locate+0x350>)\n \tmovw\tr3, #28524\t@ 0x6f6c\n \tmovt\tr3, #24935\t@ 0x6167\n \tldr\tr2, [r4, #0]\n \tadd\tr6, pc\n \tcmp\tr2, r3\n \tldr\tr5, [r6, #36]\t@ 0x24\n \tldr\tr7, [r6, #32]\n-\tbeq.w\t1fe <__gridxc_mesh1d_MOD_locate+0x1fe>\n+\tbeq.w\t220 <__gridxc_mesh1d_MOD_locate+0x220>\n \tldr\tr3, [pc, #732]\t@ (354 <__gridxc_mesh1d_MOD_locate+0x354>)\n \tmovs\tr2, #9\n \tldr\tr1, [pc, #732]\t@ (358 <__gridxc_mesh1d_MOD_locate+0x358>)\n \tmovs\tr0, #11\n \tadd\tr3, pc\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t1ec <__gridxc_mesh1d_MOD_locate+0x1ec>\n+\tbne.w\t20e <__gridxc_mesh1d_MOD_locate+0x20e>\n \tldr\tr3, [pc, #716]\t@ (35c <__gridxc_mesh1d_MOD_locate+0x35c>)\n \tsubs\tr0, r5, r7\n \tadds\tr5, r0, #1\n-\tvmov.f64\td11, #240\t@ 0xbf800000 -1.0\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n \tadd\tr3, pc\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td10, #240\t@ 0xbf800000 -1.0\n \tbic.w\tr5, r5, r5, asr #31\n \tldrd\tr1, r2, [r3, #4]\n \tadds\tr3, r2, #1\n \tadd\tr2, r5\n \tadd.w\tr3, r1, r3, lsl #3\n \tadd.w\tr2, r1, r2, lsl #3\n-\tvldr\td17, [r3]\n-\tvldr\td16, [r2]\n-\tvcmpe.f64\td17, d16\n+\tvldr\td6, [r3]\n+\tvldr\td7, [r2]\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvselge.f64\td11, d11, d12\n+\tit\tmi\n+\tvmovmi.f64\td10, d11\n \tcmp\tr0, #0\n-\tble.w\t314 <__gridxc_mesh1d_MOD_locate+0x314>\n-\tvldr\td17, [r8]\n+\tble.w\t316 <__gridxc_mesh1d_MOD_locate+0x316>\n+\tvldr\td6, [r8]\n \tmovs\tr4, #1\n-\tvldmia\tr3!, {d16}\n+\tvldmia\tr3!, {d7}\n \tmov\tr2, r4\n \tadds\tr4, #1\n-\tvsub.f64\td16, d17, d16\n-\tvmul.f64\td16, d16, d11\n-\tvcmpe.f64\td16, #0.0\n+\tvsub.f64\td7, d6, d7\n+\tvmul.f64\td7, d7, d10\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t102 <__gridxc_mesh1d_MOD_locate+0x102>\n-\tvldr\td16, [r3]\n-\tvsub.f64\td16, d16, d17\n-\tvmul.f64\td16, d16, d11\n-\tvcmpe.f64\td16, #0.0\n+\tblt.n\t104 <__gridxc_mesh1d_MOD_locate+0x104>\n+\tvldr\td7, [r3]\n+\tvsub.f64\td7, d7, d6\n+\tvmul.f64\td7, d7, d10\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbge.w\t2e2 <__gridxc_mesh1d_MOD_locate+0x2e2>\n+\tbge.w\t2e4 <__gridxc_mesh1d_MOD_locate+0x2e4>\n \tcmp\tr5, r4\n-\tbgt.n\td0 <__gridxc_mesh1d_MOD_locate+0xd0>\n+\tbgt.n\td2 <__gridxc_mesh1d_MOD_locate+0xd2>\n \tadds\tr3, r2, #2\n \tvmov\ts15, r4\n-\tvmov\ts20, r3\n+\tvmov\ts24, r3\n \tsubs\tr6, r2, #1\n \tcmp\tr6, #1\n-\tvcvt.f64.s32\td12, s15\n-\tvcvt.f64.s32\td10, s20\n+\tvcvt.f64.s32\td11, s15\n+\tvcvt.f64.s32\td12, s24\n \tit\tlt\n \tmovlt\tr6, #1\n \tadds\tr7, r2, #4\n-\tldr\tr3, [pc, #540]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n+\tldr\tr3, [pc, #536]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n \tmovs\tr1, #37\t@ 0x25\n-\tldr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #12]\n \tldr\tr0, [pc, #564]\t@ (360 <__gridxc_mesh1d_MOD_locate+0x360>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #560]\t@ (364 <__gridxc_mesh1d_MOD_locate+0x364>)\n+\tldr\tr3, [pc, #556]\t@ (364 <__gridxc_mesh1d_MOD_locate+0x364>)\n \tadd\tr3, pc\n \tldr\tr1, [r3, #4]\n \tcmp\tr4, #3\n-\tble.w\t2d8 <__gridxc_mesh1d_MOD_locate+0x2d8>\n+\tble.w\t2da <__gridxc_mesh1d_MOD_locate+0x2da>\n \tcmp\tr7, r5\n \tit\tge\n \tmovge\tr7, r5\n \tcmp\tr7, r5\n-\tbne.n\t150 <__gridxc_mesh1d_MOD_locate+0x150>\n+\tbne.n\t152 <__gridxc_mesh1d_MOD_locate+0x152>\n \tsubs\tr6, r7, #5\n \tcmp\tr6, #1\n \tit\tlt\n \tmovlt\tr6, #1\n \tldr\tr4, [pc, #532]\t@ (368 <__gridxc_mesh1d_MOD_locate+0x368>)\n \tsubs\tr7, r7, r6\n-\tldr.w\tr9, [pc, #532]\t@ 36c <__gridxc_mesh1d_MOD_locate+0x36c>\n-\tadd\tr3, sp, #32\n+\tadd\tr3, sp, #40\t@ 0x28\n \tvldr\td9, [pc, #460]\t@ 328 <__gridxc_mesh1d_MOD_locate+0x328>\n \tadds\tr7, #1\n-\tstr\tr3, [sp, #12]\n \tadd\tr4, pc\n-\tadd\tr3, sp, #48\t@ 0x30\n-\tadd\tr9, pc\n \tmov.w\tr5, #1000\t@ 0x3e8\n-\tadd.w\tfp, sp, #40\t@ 0x28\n-\tadd.w\tsl, sp, #28\n-\tstr\tr3, [sp, #16]\n-\tb.n\t186 <__gridxc_mesh1d_MOD_locate+0x186>\n-\tvmov.f64\td10, d8\n+\tadd.w\tfp, sp, #32\n+\tadd.w\tsl, sp, #20\n+\tadd.w\tr9, sp, #24\n+\tstr\tr3, [sp, #8]\n+\tb.n\t1a4 <__gridxc_mesh1d_MOD_locate+0x1a4>\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td6, [r8]\n+\tvsub.f64\td7, d7, d6\n+\tvmul.f64\td7, d7, d10\n+\tvcmpe.f64\td7, #0.0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tle\n+\tvmovle.f64\td11, d8\n+\tit\tgt\n+\tvmovgt.f64\td12, d8\n \tsubs\tr5, #1\n-\tbeq.w\t302 <__gridxc_mesh1d_MOD_locate+0x302>\n-\tldr.w\tr1, [r9, #4]\n-\tldr\tr3, [sp, #12]\n-\tvadd.f64\td8, d12, d10\n-\tstr\tr3, [sp, #4]\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tldr\tr3, [sp, #16]\n+\tbeq.w\t304 <__gridxc_mesh1d_MOD_locate+0x304>\n+\tldr\tr3, [pc, #460]\t@ (36c <__gridxc_mesh1d_MOD_locate+0x36c>)\n+\tadd\tr3, pc\n+\tldr\tr1, [r3, #4]\n+\tldr\tr3, [sp, #8]\n+\tvadd.f64\td8, d11, d12\n+\tldr\tr0, [r4, #92]\t@ 0x5c\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tstr.w\tr9, [sp, #4]\n \tmov\tr2, sl\n \tstr\tr3, [sp, #0]\n-\tvmul.f64\td8, d8, d16\n-\tstr\tr7, [sp, #28]\n+\tsubs\tr0, r6, r0\n+\tvmul.f64\td8, d8, d7\n+\tstr\tr7, [sp, #20]\n \tldr\tr3, [r4, #32]\n-\tldr\tr0, [r4, #92]\t@ 0x5c\n \tsubs\tr3, r6, r3\n-\tsubs\tr0, r6, r0\n-\tvstr\td8, [sp, #40]\t@ 0x28\n+\tvstr\td8, [sp, #32]\n \tadd.w\tr1, r1, r3, lsl #3\n \tldr\tr3, [r4, #64]\t@ 0x40\n \tadd.w\tr0, r3, r0, lsl #3\n \tmov\tr3, fp\n \tbl\t0 <__gridxc_interpolation_MOD_polint>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_polint\n-\tvsub.f64\td16, d10, d12\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d9\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t28c <__gridxc_mesh1d_MOD_locate+0x28c>\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvldr\td17, [r8]\n-\tvsub.f64\td16, d16, d17\n-\tvmul.f64\td16, d16, d11\n-\tvcmpe.f64\td16, #0.0\n+\tvsub.f64\td7, d12, d11\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d9\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t178 <__gridxc_mesh1d_MOD_locate+0x178>\n-\tvmov.f64\td12, d8\n-\tb.n\t17c <__gridxc_mesh1d_MOD_locate+0x17c>\n-\tldr\tr3, [pc, #336]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n+\tbpl.n\t174 <__gridxc_mesh1d_MOD_locate+0x174>\n+\tldr\tr2, [pc, #388]\t@ (370 <__gridxc_mesh1d_MOD_locate+0x370>)\n+\tldr\tr3, [pc, #332]\t@ (33c <__gridxc_mesh1d_MOD_locate+0x33c>)\n+\tadd\tr2, pc\n+\tldr\tr3, [r2, r3]\n+\tldr\tr2, [r3, #0]\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\teors\tr2, r3\n+\tmov.w\tr3, #0\n+\tbne.w\t322 <__gridxc_mesh1d_MOD_locate+0x322>\n+\tvmov.f64\td0, d8\n+\tadd\tsp, #60\t@ 0x3c\n+\tvpop\t{d8-d12}\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tldr\tr3, [pc, #304]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n \tmovs\tr1, #39\t@ 0x27\n-\tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #380]\t@ (370 <__gridxc_mesh1d_MOD_locate+0x370>)\n+\tldr\tr2, [sp, #12]\n+\tldr\tr0, [pc, #348]\t@ (374 <__gridxc_mesh1d_MOD_locate+0x374>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tb.n\t8c <__gridxc_mesh1d_MOD_locate+0x8c>\n \tldr\tr2, [r4, #4]\n \tmovw\tr3, #26994\t@ 0x6972\n@@ -205,103 +217,91 @@\n \tmovw\tr3, #26989\t@ 0x696d\n \tcmp\tr2, r3\n \tbne.w\t76 <__gridxc_mesh1d_MOD_locate+0x76>\n \tldrb\tr3, [r4, #2]\n \tcmp\tr3, #99\t@ 0x63\n \tbne.w\t76 <__gridxc_mesh1d_MOD_locate+0x76>\n \tldrd\tr3, r2, [r6, #4]\n-\tvldr\td17, [r6, #48]\t@ 0x30\n+\tvldr\td6, [r6, #48]\t@ 0x30\n \tvldr\td8, [r8]\n \tadd.w\tr3, r3, r2, lsl #3\n-\tvldr\td16, [r3, #8]\n-\tvsub.f64\td18, d16, d17\n-\tvcmpe.f64\td8, d18\n+\tvldr\td7, [r3, #8]\n+\tvsub.f64\td5, d7, d6\n+\tvcmpe.f64\td8, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t268 <__gridxc_mesh1d_MOD_locate+0x268>\n-\tldr\tr3, [pc, #244]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n+\tbhi.n\t28a <__gridxc_mesh1d_MOD_locate+0x28a>\n+\tldr\tr3, [pc, #212]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n \tmovs\tr1, #37\t@ 0x25\n-\tldr\tr2, [sp, #20]\n-\tldr\tr0, [pc, #292]\t@ (374 <__gridxc_mesh1d_MOD_locate+0x374>)\n+\tldr\tr2, [sp, #12]\n+\tldr\tr0, [pc, #260]\t@ (378 <__gridxc_mesh1d_MOD_locate+0x378>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvldr\td17, [r6, #48]\t@ 0x30\n+\tvldr\td6, [r6, #48]\t@ 0x30\n \tldrd\tr3, r2, [r6, #4]\n \tadd.w\tr3, r3, r2, lsl #3\n-\tvldr\td16, [r3, #8]\n-\tvsub.f64\td16, d8, d16\n+\tvldr\td7, [r3, #8]\n+\tvsub.f64\td7, d8, d7\n \tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td0, d16, d17\n+\tvdiv.f64\td0, d7, d6\n \tvadd.f64\td0, d0, d9\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tldr\tr3, [pc, #248]\t@ (378 <__gridxc_mesh1d_MOD_locate+0x378>)\n+\tldr\tr3, [pc, #220]\t@ (37c <__gridxc_mesh1d_MOD_locate+0x37c>)\n \tadd\tr3, pc\n-\tvldr\td16, [r3, #56]\t@ 0x38\n-\tvdiv.f64\td8, d0, d16\n+\tvldr\td7, [r3, #56]\t@ 0x38\n+\tvdiv.f64\td8, d0, d7\n \tvadd.f64\td8, d8, d9\n-\tldr\tr2, [pc, #236]\t@ (37c <__gridxc_mesh1d_MOD_locate+0x37c>)\n-\tldr\tr3, [pc, #172]\t@ (33c <__gridxc_mesh1d_MOD_locate+0x33c>)\n-\tadd\tr2, pc\n-\tldr\tr3, [r2, r3]\n-\tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\teors\tr2, r3\n-\tmov.w\tr3, #0\n-\tbne.n\t320 <__gridxc_mesh1d_MOD_locate+0x320>\n-\tvmov.f64\td0, d8\n-\tadd\tsp, #68\t@ 0x44\n-\tvpop\t{d8-d12}\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #208]\t@ (380 <__gridxc_mesh1d_MOD_locate+0x380>)\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvldr\td16, [r8]\n+\tb.n\t1ea <__gridxc_mesh1d_MOD_locate+0x1ea>\n+\tldr\tr3, [pc, #204]\t@ (380 <__gridxc_mesh1d_MOD_locate+0x380>)\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [r8]\n \tadd\tr3, pc\n \tldrd\tr2, r1, [r3, #4]\n-\tvldr\td18, [r3, #40]\t@ 0x28\n+\tvldr\td5, [r3, #40]\t@ 0x28\n \tadd.w\tr3, r2, r1, lsl #3\n-\tvldr\td19, [r3, #8]\n-\tvsub.f64\td16, d16, d19\n-\tvdiv.f64\td8, d16, d18\n-\tvadd.f64\td8, d8, d17\n-\tb.n\t28c <__gridxc_mesh1d_MOD_locate+0x28c>\n+\tvldr\td4, [r3, #8]\n+\tvsub.f64\td7, d7, d4\n+\tvdiv.f64\td8, d7, d5\n+\tvadd.f64\td8, d8, d6\n+\tb.n\t1ea <__gridxc_mesh1d_MOD_locate+0x1ea>\n \tcmp\tr5, #6\n \tmov\tr7, r5\n \tit\tge\n \tmovge\tr7, #6\n-\tb.n\t144 <__gridxc_mesh1d_MOD_locate+0x144>\n+\tb.n\t146 <__gridxc_mesh1d_MOD_locate+0x146>\n \tvmov\ts15, r4\n \tsubs\tr6, r2, #2\n \tcmp\tr6, #1\n \tadd.w\tr7, r2, #3\n-\tvcvt.f64.s32\td10, s15\n+\tvcvt.f64.s32\td12, s15\n \tvmov\ts15, r2\n \tit\tlt\n \tmovlt\tr6, #1\n \tmov\tr4, r2\n-\tvcvt.f64.s32\td12, s15\n-\tb.n\t138 <__gridxc_mesh1d_MOD_locate+0x138>\n-\tldr\tr3, [pc, #60]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n+\tvcvt.f64.s32\td11, s15\n+\tb.n\t13a <__gridxc_mesh1d_MOD_locate+0x13a>\n+\tldr\tr3, [pc, #56]\t@ (340 <__gridxc_mesh1d_MOD_locate+0x340>)\n \tmovs\tr1, #45\t@ 0x2d\n-\tldr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #12]\n \tldr\tr0, [pc, #120]\t@ (384 <__gridxc_mesh1d_MOD_locate+0x384>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t28c <__gridxc_mesh1d_MOD_locate+0x28c>\n+\tb.n\t1ea <__gridxc_mesh1d_MOD_locate+0x1ea>\n \tmovs\tr6, #1\n \tmovs\tr7, #4\n \tmov\tr4, r6\n-\tvmov.f64\td10, #0\t@ 0x40000000 2.0\n-\tb.n\t122 <__gridxc_mesh1d_MOD_locate+0x122>\n+\tvmov.f64\td12, #0\t@ 0x40000000 2.0\n+\tb.n\t124 <__gridxc_mesh1d_MOD_locate+0x124>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n+\tnop\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x0000030e\n R_ARM_REL32\t.bss\n \t.word\t0x00000310\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x0000030c\n@@ -319,33 +319,33 @@\n R_ARM_REL32\t.bss\n \t.word\t0x000002d2\n R_ARM_REL32\t.LC4\n \t.word\t0x000002d4\n R_ARM_REL32\t.data\n \t.word\t0x000002c2\n R_ARM_REL32\t.bss\n-\t.word\t0x00000230\n+\t.word\t0x0000022e\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000022c\n+\t.word\t0x0000022a\n R_ARM_REL32\t.bss\n-\t.word\t0x00000202\n+\t.word\t0x00000206\n R_ARM_REL32\t.bss\n-\t.word\t0x00000202\n+\t.word\t0x000001c8\n R_ARM_REL32\t.bss\n-\t.word\t0x00000176\n+\t.word\t0x0000017e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000158\n R_ARM_REL32\t.LC5\n-\t.word\t0x0000011e\n+\t.word\t0x00000100\n R_ARM_REL32\t.LC3\n-\t.word\t0x000000f6\n+\t.word\t0x000000d8\n R_ARM_REL32\t.bss\n-\t.word\t0x000000e8\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000000c4\n+\t.word\t0x000000c2\n R_ARM_REL32\t.bss\n-\t.word\t0x00000074\n+\t.word\t0x00000072\n R_ARM_REL32\t.LC6\n \n 00000388 <__gridxc_mesh1d_MOD_get_mesh>:\n __gridxc_mesh1d_MOD_get_mesh.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n@@ -553,15 +553,15 @@\n \tldr\tr3, [sp, #24]\n \tadd\tr3, r0\n \tmovs\tr0, #0\n \tadd.w\tr3, fp, r3, lsl #3\n \tldrd\tr4, r5, [r1], #8\n \tadds\tr0, #1\n \tstrd\tr4, r5, [r3]\n-\tcmp\tr0, r2\n+\tcmp\tr2, r0\n \tadd\tr3, r6\n \tbne.n\t5a0 <__gridxc_mesh1d_MOD_get_mesh+0x218>\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov\tr7, r2\n \tb.n\t3ca <__gridxc_mesh1d_MOD_get_mesh+0x42>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n@@ -591,18 +591,18 @@\n \tldr\tr2, [sp, #32]\n \tadds\tr3, #1\n \tadd\tr2, r9\n \tadd.w\tr3, r1, r3, lsl #3\n \tmov.w\tr9, r9, lsl #3\n \tmovs\tr1, #0\n \tadd.w\tr2, r7, r2, lsl #3\n-\tvldmia\tr3!, {d16}\n+\tvldmia\tr3!, {d7}\n \tadds\tr1, #1\n \tcmp\tr1, r6\n-\tvstr\td16, [r2]\n+\tvstr\td7, [r2]\n \tadd\tr2, r9\n \tbne.n\t60a <__gridxc_mesh1d_MOD_get_mesh+0x282>\n \tb.n\t542 <__gridxc_mesh1d_MOD_get_mesh+0x1ba>\n \tcmp.w\tr8, #0\n \tbeq.w\t484 <__gridxc_mesh1d_MOD_get_mesh+0xfc>\n \tldrd\tr1, r3, [r0, #100]\t@ 0x64\n \tcmp\tr6, #0\n@@ -808,1955 +808,1986 @@\n \t.word\t0x0000003a\n R_ARM_REL32\t.LC12\n \n 00000808 <__gridxc_mesh1d_MOD_set_mesh>:\n __gridxc_mesh1d_MOD_set_mesh.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3856]\t@ 0xf10\n-\tsub\tsp, #172\t@ 0xac\n+\tstr.w\tr0, [ip, #3816]\t@ 0xee8\n+\tsub\tsp, #180\t@ 0xb4\n+\tldr.w\tr9, [pc, #1400]\t@ d98 <__gridxc_mesh1d_MOD_set_mesh+0x590>\n \tmov\tr4, r0\n-\tldr.w\tr0, [pc, #1332]\t@ d58 <__gridxc_mesh1d_MOD_set_mesh+0x550>\n-\tmov\tr9, r1\n-\tadd\tr0, pc\n-\tstr\tr2, [sp, #28]\n+\tmov\tsl, r1\n+\tadd\tr9, pc\n+\tstr\tr2, [sp, #24]\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tstr\tr0, [sp, #16]\n \tcbz\tr1, 858 <__gridxc_mesh1d_MOD_set_mesh+0x50>\n-\tldrd\tr5, r1, [sp, #240]\t@ 0xf0\n-\tmov\tr6, r3\n-\torr.w\tr3, r1, r5\n+\tldrd\tr0, r1, [sp, #280]\t@ 0x118\n+\tmov\tr5, r3\n+\torr.w\tr3, r1, r0\n \tldr\tr1, [r4, #0]\n-\torrs\tr3, r6\n+\torrs\tr3, r5\n \tstr\tr1, [sp, #48]\t@ 0x30\n \torrs\tr3, r2\n-\tbeq.w\t17a0 <__gridxc_mesh1d_MOD_set_mesh+0xf98>\n-\tldr.w\tr3, [pc, #1300]\t@ d5c <__gridxc_mesh1d_MOD_set_mesh+0x554>\n+\tbeq.w\t1806 <__gridxc_mesh1d_MOD_set_mesh+0xffe>\n+\tldr.w\tr3, [pc, #1364]\t@ d9c <__gridxc_mesh1d_MOD_set_mesh+0x594>\n \tmovs\tr1, #63\t@ 0x3f\n-\tldr\tr3, [r0, r3]\n-\tldr.w\tr0, [pc, #1296]\t@ d60 <__gridxc_mesh1d_MOD_set_mesh+0x558>\n-\tldr\tr3, [r3, #0]\n+\tldr.w\tr0, [pc, #1364]\t@ da0 <__gridxc_mesh1d_MOD_set_mesh+0x598>\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n+\tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldrd\tr3, r2, [sp, #240]\t@ 0xf0\n+\tldrd\tr3, r2, [sp, #280]\t@ 0x118\n \tcmp\tr3, #0\n \tit\tne\n \tcmpne\tr2, #0\n \tbeq.n\t878 <__gridxc_mesh1d_MOD_set_mesh+0x70>\n-\tldr.w\tr3, [pc, #1268]\t@ d5c <__gridxc_mesh1d_MOD_set_mesh+0x554>\n+\tldr.w\tr3, [pc, #1332]\t@ d9c <__gridxc_mesh1d_MOD_set_mesh+0x594>\n \tmovs\tr1, #58\t@ 0x3a\n-\tldr\tr2, [sp, #16]\n-\tldr.w\tr0, [pc, #1268]\t@ d64 <__gridxc_mesh1d_MOD_set_mesh+0x55c>\n-\tldr\tr3, [r2, r3]\n+\tldr.w\tr0, [pc, #1336]\t@ da4 <__gridxc_mesh1d_MOD_set_mesh+0x59c>\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr4, [r4, #0]\n-\tcmp\tr4, #2\n-\tbgt.w\t1516 <__gridxc_mesh1d_MOD_set_mesh+0xd0e>\n-\tldr.w\tr3, [pc, #1240]\t@ d5c <__gridxc_mesh1d_MOD_set_mesh+0x554>\n+\tldr\tr3, [r4, #0]\n+\tstr\tr3, [sp, #0]\n+\tcmp\tr3, #2\n+\tbgt.w\t1564 <__gridxc_mesh1d_MOD_set_mesh+0xd5c>\n+\tldr.w\tr3, [pc, #1304]\t@ d9c <__gridxc_mesh1d_MOD_set_mesh+0x594>\n \tmovs\tr1, #47\t@ 0x2f\n-\tldr\tr2, [sp, #16]\n-\tldr.w\tr0, [pc, #1244]\t@ d68 <__gridxc_mesh1d_MOD_set_mesh+0x560>\n-\tldr\tr3, [r2, r3]\n+\tldr.w\tr0, [pc, #1308]\t@ da8 <__gridxc_mesh1d_MOD_set_mesh+0x5a0>\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp.w\tr9, #0\n-\tbeq.n\t8ec <__gridxc_mesh1d_MOD_set_mesh+0xe4>\n-\tadd.w\tr3, r9, r4, lsl #3\n-\tvldr\td17, [r9]\n-\tcmp\tr4, #2\n-\tvldr\td18, [r3, #-8]\n-\tvsub.f64\td18, d18, d17\n-\tbne.w\t1b08 <__gridxc_mesh1d_MOD_set_mesh+0x1300>\n-\tadd.w\tr2, r9, #8\n+\tcmp.w\tsl, #0\n+\tbeq.n\t8f2 <__gridxc_mesh1d_MOD_set_mesh+0xea>\n+\tldr\tr2, [sp, #0]\n+\tvldr\td6, [sl]\n+\tcmp\tr2, #2\n+\tadd.w\tr3, sl, r2, lsl #3\n+\tvldr\td5, [r3, #-8]\n+\tvsub.f64\td5, d5, d6\n+\tbne.w\t1b70 <__gridxc_mesh1d_MOD_set_mesh+0x1368>\n+\tldr\tr1, [sp, #0]\n+\tadd.w\tr2, sl, #8\n \tmovs\tr3, #2\n-\tb.n\t8be <__gridxc_mesh1d_MOD_set_mesh+0xb6>\n+\tb.n\t8c4 <__gridxc_mesh1d_MOD_set_mesh+0xbc>\n \tadds\tr3, #1\n-\tcmp\tr4, r3\n-\tblt.n\t8ec <__gridxc_mesh1d_MOD_set_mesh+0xe4>\n-\tvmov.f64\td16, d17\n-\tvldmia\tr2!, {d17}\n-\tvsub.f64\td16, d17, d16\n-\tvmul.f64\td16, d16, d18\n-\tvcmpe.f64\td16, #0.0\n+\tcmp\tr1, r3\n+\tblt.n\t8f2 <__gridxc_mesh1d_MOD_set_mesh+0xea>\n+\tvmov.f64\td7, d6\n+\tvldmia\tr2!, {d6}\n+\tvsub.f64\td7, d6, d7\n+\tvmul.f64\td7, d7, d5\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.n\t8b8 <__gridxc_mesh1d_MOD_set_mesh+0xb0>\n-\tldr.w\tr3, [pc, #1152]\t@ d5c <__gridxc_mesh1d_MOD_set_mesh+0x554>\n+\tbhi.n\t8be <__gridxc_mesh1d_MOD_set_mesh+0xb6>\n+\tldr.w\tr3, [pc, #1212]\t@ d9c <__gridxc_mesh1d_MOD_set_mesh+0x594>\n \tmovs\tr1, #35\t@ 0x23\n-\tldr\tr2, [sp, #16]\n-\tldr.w\tr0, [pc, #1160]\t@ d6c <__gridxc_mesh1d_MOD_set_mesh+0x564>\n-\tldr\tr3, [r2, r3]\n+\tldr.w\tr0, [pc, #1220]\t@ dac <__gridxc_mesh1d_MOD_set_mesh+0x5a4>\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr.w\tr3, [pc, #1152]\t@ d70 <__gridxc_mesh1d_MOD_set_mesh+0x568>\n+\tldr.w\tr3, [pc, #1212]\t@ db0 <__gridxc_mesh1d_MOD_set_mesh+0x5a8>\n \tadd\tr3, pc\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #0\n-\tbeq.n\t9ae <__gridxc_mesh1d_MOD_set_mesh+0x1a6>\n-\tldr.w\tr6, [pc, #1144]\t@ d74 <__gridxc_mesh1d_MOD_set_mesh+0x56c>\n+\tbeq.n\t9b6 <__gridxc_mesh1d_MOD_set_mesh+0x1ae>\n+\tldr.w\tr6, [pc, #1204]\t@ db4 <__gridxc_mesh1d_MOD_set_mesh+0x5ac>\n \tadd\tr6, pc\n \tldr\tr0, [r6, #64]\t@ 0x40\n \tcmp\tr0, #0\n-\tbeq.w\t1bd0 <__gridxc_mesh1d_MOD_set_mesh+0x13c8>\n+\tbeq.w\t1bf8 <__gridxc_mesh1d_MOD_set_mesh+0x13f0>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r6, #248]\t@ 0xf8\n+\tldr.w\tr0, [r6, #244]\t@ 0xf4\n \tmovs\tr5, #0\n \tstr\tr5, [r6, #64]\t@ 0x40\n \tcmp\tr0, #0\n-\tbeq.w\t1be0 <__gridxc_mesh1d_MOD_set_mesh+0x13d8>\n+\tbeq.w\t1c08 <__gridxc_mesh1d_MOD_set_mesh+0x1400>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r6, #288]\t@ 0x120\n-\tstr.w\tr5, [r6, #248]\t@ 0xf8\n+\tldr.w\tr0, [r6, #280]\t@ 0x118\n+\tstr.w\tr5, [r6, #244]\t@ 0xf4\n \tcmp\tr0, #0\n-\tbeq.w\t1ca4 <__gridxc_mesh1d_MOD_set_mesh+0x149c>\n+\tbeq.w\t1ccc <__gridxc_mesh1d_MOD_set_mesh+0x14c4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r6, #328]\t@ 0x148\n-\tstr.w\tr5, [r6, #288]\t@ 0x120\n+\tldr.w\tr0, [r6, #316]\t@ 0x13c\n+\tstr.w\tr5, [r6, #280]\t@ 0x118\n \tcmp\tr0, #0\n-\tbeq.w\t1cb4 <__gridxc_mesh1d_MOD_set_mesh+0x14ac>\n+\tbeq.w\t1cdc <__gridxc_mesh1d_MOD_set_mesh+0x14d4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr0, [r6, #368]\t@ 0x170\n-\tstr.w\tr5, [r6, #328]\t@ 0x148\n+\tldr.w\tr0, [r6, #352]\t@ 0x160\n+\tstr.w\tr5, [r6, #316]\t@ 0x13c\n \tcmp\tr0, #0\n-\tbeq.w\t1cc4 <__gridxc_mesh1d_MOD_set_mesh+0x14bc>\n+\tbeq.w\t1cec <__gridxc_mesh1d_MOD_set_mesh+0x14e4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r6, #4]\n-\tstr.w\tr5, [r6, #368]\t@ 0x170\n+\tstr.w\tr5, [r6, #352]\t@ 0x160\n \tcmp\tr0, #0\n-\tbeq.w\t1cd4 <__gridxc_mesh1d_MOD_set_mesh+0x14cc>\n+\tbeq.w\t1cfc <__gridxc_mesh1d_MOD_set_mesh+0x14f4>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r6, #100]\t@ 0x64\n \tstr\tr5, [r6, #4]\n \tcmp\tr0, #0\n-\tbeq.w\t1ce4 <__gridxc_mesh1d_MOD_set_mesh+0x14dc>\n+\tbeq.w\t1d0c <__gridxc_mesh1d_MOD_set_mesh+0x1504>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r6, #136]\t@ 0x88\n \tstr\tr5, [r6, #100]\t@ 0x64\n \tcmp\tr0, #0\n-\tbeq.w\t1cf4 <__gridxc_mesh1d_MOD_set_mesh+0x14ec>\n+\tbeq.w\t1d1c <__gridxc_mesh1d_MOD_set_mesh+0x1514>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r6, #172]\t@ 0xac\n \tstr.w\tr5, [r6, #136]\t@ 0x88\n \tcmp\tr0, #0\n-\tbeq.w\t1d04 <__gridxc_mesh1d_MOD_set_mesh+0x14fc>\n+\tbeq.w\t1d2c <__gridxc_mesh1d_MOD_set_mesh+0x1524>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r6, #208]\t@ 0xd0\n \tstr.w\tr5, [r6, #172]\t@ 0xac\n \tcmp\tr0, #0\n-\tbeq.w\t1d14 <__gridxc_mesh1d_MOD_set_mesh+0x150c>\n+\tbeq.w\t1d3c <__gridxc_mesh1d_MOD_set_mesh+0x1534>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #976]\t@ (d78 <__gridxc_mesh1d_MOD_set_mesh+0x570>)\n+\tldr.w\tr3, [pc, #1036]\t@ db8 <__gridxc_mesh1d_MOD_set_mesh+0x5b0>\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstr.w\tr2, [r3, #208]\t@ 0xd0\n-\tldr\tr3, [pc, #972]\t@ (d7c <__gridxc_mesh1d_MOD_set_mesh+0x574>)\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmovs\tr2, #8\n-\tcmp.w\tr4, #536870912\t@ 0x20000000\n+\tldr.w\tr3, [pc, #1028]\t@ dbc <__gridxc_mesh1d_MOD_set_mesh+0x5b4>\n+\tmovs\tr2, #0\n \tadd\tr3, pc\n+\tstrd\tr2, r2, [r3, #76]\t@ 0x4c\n+\tmovs\tr2, #8\n \tstr\tr2, [r3, #72]\t@ 0x48\n \tmovw\tr2, #769\t@ 0x301\n-\tvstr\td16, [r3, #76]\t@ 0x4c\n \tstrh.w\tr2, [r3, #80]\t@ 0x50\n-\tbic.w\tr3, r4, r4, asr #31\n-\tbge.w\t1d24 <__gridxc_mesh1d_MOD_set_mesh+0x151c>\n-\tldr\tr2, [pc, #940]\t@ (d80 <__gridxc_mesh1d_MOD_set_mesh+0x578>)\n-\tcmp\tr4, #0\n-\tadd\tr2, pc\n-\tldr\tr2, [r2, #64]\t@ 0x40\n-\tble.w\t1532 <__gridxc_mesh1d_MOD_set_mesh+0xd2a>\n-\tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #20]\n-\tcmp\tr2, #0\n-\tbne.w\t1d2c <__gridxc_mesh1d_MOD_set_mesh+0x1524>\n-\tldr\tr5, [sp, #20]\n-\tldr\tr6, [pc, #920]\t@ (d84 <__gridxc_mesh1d_MOD_set_mesh+0x57c>)\n-\tcmp\tr5, #1\n-\tadd\tr6, pc\n+\tldr\tr3, [sp, #0]\n+\tcmp.w\tr3, #536870912\t@ 0x20000000\n+\tbic.w\tr2, r3, r3, asr #31\n+\tbge.w\t1d4c <__gridxc_mesh1d_MOD_set_mesh+0x1544>\n+\tldr\tr3, [pc, #992]\t@ (dc0 <__gridxc_mesh1d_MOD_set_mesh+0x5b8>)\n+\tadd\tr3, pc\n+\tldr.w\tr8, [r3, #64]\t@ 0x40\n+\tldr\tr3, [sp, #0]\n+\tcmp\tr3, #0\n+\tit\tgt\n+\tlslgt\tr4, r2, #3\n+\tble.w\t1580 <__gridxc_mesh1d_MOD_set_mesh+0xd78>\n+\tcmp.w\tr8, #0\n+\tbne.w\t1d54 <__gridxc_mesh1d_MOD_set_mesh+0x154c>\n+\tldr\tr5, [pc, #968]\t@ (dc4 <__gridxc_mesh1d_MOD_set_mesh+0x5bc>)\n+\tcmp\tr4, #1\n+\tmov\tr7, r4\n \tit\tcc\n-\tmovcc\tr5, #1\n-\tmov\tr0, r5\n+\tmovcc\tr7, #1\n+\tadd\tr5, pc\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #24]\n-\tstr\tr0, [r6, #64]\t@ 0x40\n+\tstr\tr0, [sp, #20]\n+\tstr\tr0, [r5, #64]\t@ 0x40\n \tcmp\tr0, #0\n-\tbeq.w\t1d3c <__gridxc_mesh1d_MOD_set_mesh+0x1534>\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tldr.w\tr2, [r6, #248]\t@ 0xf8\n-\tvldr\td8, [pc, #816]\t@ d40 <__gridxc_mesh1d_MOD_set_mesh+0x538>\n-\tadd.w\tr1, r6, #84\t@ 0x54\n+\tbeq.w\t1d64 <__gridxc_mesh1d_MOD_set_mesh+0x155c>\n+\tldr.w\tr0, [r5, #244]\t@ 0xf4\n+\tmovs\tr6, #8\n+\tldr\tr3, [sp, #0]\n \tmov.w\tfp, #1\n-\tmov.w\tsl, #4294967295\t@ 0xffffffff\n-\tmov.w\tr8, #8\n-\tmovw\tr7, #769\t@ 0x301\n-\tvstr\td9, [r6, #260]\t@ 0x104\n-\tstr\tr4, [r6, #96]\t@ 0x60\n-\tstr.w\tfp, [r6, #92]\t@ 0x5c\n-\tstr.w\tsl, [r6, #68]\t@ 0x44\n-\tstr.w\tr8, [r6, #256]\t@ 0x100\n-\tstrh.w\tr7, [r6, #264]\t@ 0x108\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1d4a <__gridxc_mesh1d_MOD_set_mesh+0x1542>\n-\tmov\tr0, r5\n+\tstr.w\tr8, [r5, #260]\t@ 0x104\n+\tstr\tr3, [r5, #96]\t@ 0x60\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr8, [r5, #256]\t@ 0x100\n+\tstr\tr3, [r5, #68]\t@ 0x44\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrd\tfp, fp, [r5, #88]\t@ 0x58\n+\tstr\tr6, [r5, #84]\t@ 0x54\n+\tstr.w\tr6, [r5, #252]\t@ 0xfc\n+\tstrh.w\tr3, [r5, #260]\t@ 0x104\n+\tcmp\tr0, #0\n+\tbne.w\t1d72 <__gridxc_mesh1d_MOD_set_mesh+0x156a>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [sp, #32]\n-\tstr.w\tr0, [r6, #248]\t@ 0xf8\n+\tstr.w\tr0, [r5, #244]\t@ 0xf4\n \tcmp\tr0, #0\n-\tbeq.w\t1d5a <__gridxc_mesh1d_MOD_set_mesh+0x1552>\n-\tldr.w\tr2, [r6, #288]\t@ 0x120\n-\tadd.w\tr1, r6, #268\t@ 0x10c\n-\tvstr\td9, [r6, #300]\t@ 0x12c\n-\tstrd\tfp, r4, [r6, #276]\t@ 0x114\n-\tstr.w\tsl, [r6, #252]\t@ 0xfc\n-\tstr.w\tr8, [r6, #296]\t@ 0x128\n-\tstrh.w\tr7, [r6, #304]\t@ 0x130\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1d68 <__gridxc_mesh1d_MOD_set_mesh+0x1560>\n-\tmov\tr0, r5\n+\tbeq.w\t1d82 <__gridxc_mesh1d_MOD_set_mesh+0x157a>\n+\tldr.w\tr0, [r5, #280]\t@ 0x118\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr8, [r5, #296]\t@ 0x128\n+\tstr.w\tr3, [r5, #276]\t@ 0x114\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [r5, #272]\t@ 0x110\n+\tstr.w\tr3, [r5, #248]\t@ 0xf8\n+\tmovw\tr3, #769\t@ 0x301\n+\tstr.w\tfp, [r5, #268]\t@ 0x10c\n+\tstr.w\tr6, [r5, #264]\t@ 0x108\n+\tstrd\tr6, r8, [r5, #288]\t@ 0x120\n+\tstrh.w\tr3, [r5, #296]\t@ 0x128\n+\tcmp\tr0, #0\n+\tbne.w\t1d90 <__gridxc_mesh1d_MOD_set_mesh+0x1588>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r6, #288]\t@ 0x120\n+\tstr.w\tr0, [r5, #280]\t@ 0x118\n \tcmp\tr0, #0\n-\tbeq.w\t1d78 <__gridxc_mesh1d_MOD_set_mesh+0x1570>\n-\tldr.w\tr2, [r6, #328]\t@ 0x148\n-\tadd.w\tr1, r6, #308\t@ 0x134\n-\tvstr\td9, [r6, #340]\t@ 0x154\n-\tstrd\tfp, r4, [r6, #316]\t@ 0x13c\n-\tstr.w\tsl, [r6, #292]\t@ 0x124\n-\tstr.w\tr8, [r6, #336]\t@ 0x150\n-\tstrh.w\tr7, [r6, #344]\t@ 0x158\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1d86 <__gridxc_mesh1d_MOD_set_mesh+0x157e>\n-\tmov\tr0, r5\n+\tbeq.w\t1da0 <__gridxc_mesh1d_MOD_set_mesh+0x1598>\n+\tldr.w\tr0, [r5, #316]\t@ 0x13c\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr8, [r5, #332]\t@ 0x14c\n+\tstr.w\tr3, [r5, #312]\t@ 0x138\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [r5, #308]\t@ 0x134\n+\tstr.w\tr3, [r5, #284]\t@ 0x11c\n+\tmovw\tr3, #769\t@ 0x301\n+\tstr.w\tfp, [r5, #304]\t@ 0x130\n+\tstr.w\tr6, [r5, #300]\t@ 0x12c\n+\tstrd\tr6, r8, [r5, #324]\t@ 0x144\n+\tstrh.w\tr3, [r5, #332]\t@ 0x14c\n+\tcmp\tr0, #0\n+\tbne.w\t1dae <__gridxc_mesh1d_MOD_set_mesh+0x15a6>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r6, #328]\t@ 0x148\n+\tstr.w\tr0, [r5, #316]\t@ 0x13c\n \tcmp\tr0, #0\n-\tbeq.w\t1c2c <__gridxc_mesh1d_MOD_set_mesh+0x1424>\n-\tldr.w\tr2, [r6, #368]\t@ 0x170\n-\tadd.w\tr1, r6, #348\t@ 0x15c\n-\tvstr\td9, [r6, #380]\t@ 0x17c\n-\tstr.w\tfp, [r6, #356]\t@ 0x164\n-\tstr.w\tsl, [r6, #332]\t@ 0x14c\n-\tstr.w\tr8, [r6, #376]\t@ 0x178\n-\tstrh.w\tr7, [r6, #384]\t@ 0x180\n-\tstr.w\tr4, [r6, #360]\t@ 0x168\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1c3a <__gridxc_mesh1d_MOD_set_mesh+0x1432>\n-\tmov\tr0, r5\n+\tbeq.w\t1c54 <__gridxc_mesh1d_MOD_set_mesh+0x144c>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr8, r8, [r5, #364]\t@ 0x16c\n+\tstr.w\tr3, [r5, #320]\t@ 0x140\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh.w\tr3, [r5, #368]\t@ 0x170\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr3, [r5, #348]\t@ 0x15c\n+\tldr.w\tr3, [r5, #352]\t@ 0x160\n+\tstrd\tfp, fp, [r5, #340]\t@ 0x154\n+\tstr.w\tr6, [r5, #336]\t@ 0x150\n+\tstr.w\tr6, [r5, #360]\t@ 0x168\n+\tcmp\tr3, #0\n+\tbne.w\t1c62 <__gridxc_mesh1d_MOD_set_mesh+0x145a>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [sp, #36]\t@ 0x24\n-\tstr.w\tr0, [r6, #368]\t@ 0x170\n+\tstr.w\tr0, [r5, #352]\t@ 0x160\n \tcmp\tr0, #0\n-\tbeq.w\t1c4a <__gridxc_mesh1d_MOD_set_mesh+0x1442>\n-\tldr\tr6, [pc, #648]\t@ (d88 <__gridxc_mesh1d_MOD_set_mesh+0x580>)\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tvldr\td8, [pc, #568]\t@ d40 <__gridxc_mesh1d_MOD_set_mesh+0x538>\n+\tbeq.w\t1c72 <__gridxc_mesh1d_MOD_set_mesh+0x146a>\n+\tldr\tr5, [pc, #672]\t@ (dc8 <__gridxc_mesh1d_MOD_set_mesh+0x5c0>)\n+\tmovs\tr6, #8\n+\tldr\tr3, [sp, #0]\n+\tmovs\tr0, #0\n+\tadd\tr5, pc\n \tmov.w\tfp, #1\n-\tadd\tr6, pc\n-\tmov.w\tsl, #4294967295\t@ 0xffffffff\n-\tadd.w\tr1, r6, #388\t@ 0x184\n-\tmov.w\tr8, #8\n-\tmovw\tr7, #769\t@ 0x301\n-\tldr\tr2, [r6, #4]\n-\tvstr\td9, [r6, #16]\n-\tstr.w\tr4, [r6, #400]\t@ 0x190\n-\tstr.w\tfp, [r6, #396]\t@ 0x18c\n-\tstr.w\tsl, [r6, #372]\t@ 0x174\n-\tstr.w\tr8, [r6, #12]\n-\tstrh\tr7, [r6, #20]\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1c58 <__gridxc_mesh1d_MOD_set_mesh+0x1450>\n-\tmov\tr0, r5\n+\tadd.w\tip, r5, #16\n+\tmovw\tr8, #769\t@ 0x301\n+\tldr\tr1, [r5, #4]\n+\tstr.w\tr0, [ip, #4]\n+\tstr.w\tr3, [r5, #384]\t@ 0x180\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tfp, fp, [r5, #376]\t@ 0x178\n+\tstr.w\tr6, [r5, #372]\t@ 0x174\n+\tstr\tr6, [r5, #12]\n+\tstr\tr0, [r5, #16]\n+\tstr.w\tr3, [r5, #356]\t@ 0x164\n+\tstrh.w\tr8, [r5, #20]\n+\tcmp\tr1, #0\n+\tbne.w\t1c80 <__gridxc_mesh1d_MOD_set_mesh+0x1478>\n+\tmov\tr0, r7\n+\tstr\tr1, [sp, #4]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n+\tldr\tr1, [sp, #4]\n \tstr\tr0, [sp, #44]\t@ 0x2c\n-\tstr\tr0, [r6, #4]\n+\tstr\tr0, [r5, #4]\n \tcmp\tr0, #0\n-\tbeq.w\t1c68 <__gridxc_mesh1d_MOD_set_mesh+0x1460>\n-\tldr\tr2, [r6, #100]\t@ 0x64\n-\tadd.w\tr1, r6, #24\n-\tvstr\td9, [r6, #112]\t@ 0x70\n-\tstrd\tfp, r4, [r6, #32]\n-\tstr.w\tsl, [r6, #8]\n-\tstr.w\tr8, [r6, #108]\t@ 0x6c\n-\tstrh.w\tr7, [r6, #116]\t@ 0x74\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1c76 <__gridxc_mesh1d_MOD_set_mesh+0x146e>\n-\tmov\tr0, r5\n+\tbeq.w\t1c90 <__gridxc_mesh1d_MOD_set_mesh+0x1488>\n+\tstrd\tr1, r1, [r5, #112]\t@ 0x70\n+\tldr\tr1, [r5, #100]\t@ 0x64\n+\tldr\tr3, [sp, #0]\n+\tstr\tr3, [r5, #36]\t@ 0x24\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [r5, #32]\n+\tstr.w\tfp, [r5, #28]\n+\tstr\tr3, [r5, #8]\n+\tstr\tr6, [r5, #24]\n+\tstr\tr6, [r5, #108]\t@ 0x6c\n+\tstrh.w\tr8, [r5, #116]\t@ 0x74\n+\tcmp\tr1, #0\n+\tbne.w\t1c9e <__gridxc_mesh1d_MOD_set_mesh+0x1496>\n+\tmov\tr0, r7\n+\tstr\tr1, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n+\tldr\tr1, [sp, #8]\n \tstr\tr0, [sp, #4]\n-\tstr\tr0, [r6, #100]\t@ 0x64\n+\tstr\tr0, [r5, #100]\t@ 0x64\n \tcmp\tr0, #0\n-\tbeq.w\t1c86 <__gridxc_mesh1d_MOD_set_mesh+0x147e>\n-\tldr.w\tr2, [r6, #136]\t@ 0x88\n-\tadd.w\tr1, r6, #120\t@ 0x78\n-\tvstr\td9, [r6, #148]\t@ 0x94\n-\tstrd\tfp, r4, [r6, #128]\t@ 0x80\n-\tstr.w\tsl, [r6, #104]\t@ 0x68\n-\tstr.w\tr8, [r6, #144]\t@ 0x90\n-\tstrh.w\tr7, [r6, #152]\t@ 0x98\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1c94 <__gridxc_mesh1d_MOD_set_mesh+0x148c>\n-\tmov\tr0, r5\n+\tbeq.w\t1cae <__gridxc_mesh1d_MOD_set_mesh+0x14a6>\n+\tstrd\tr1, r1, [r5, #148]\t@ 0x94\n+\tldr.w\tr1, [r5, #136]\t@ 0x88\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr3, [r5, #132]\t@ 0x84\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [r5, #128]\t@ 0x80\n+\tstr.w\tfp, [r5, #124]\t@ 0x7c\n+\tstr\tr3, [r5, #104]\t@ 0x68\n+\tstr\tr6, [r5, #120]\t@ 0x78\n+\tstr.w\tr6, [r5, #144]\t@ 0x90\n+\tstrh.w\tr8, [r5, #152]\t@ 0x98\n+\tcmp\tr1, #0\n+\tbne.w\t1cbc <__gridxc_mesh1d_MOD_set_mesh+0x14b4>\n+\tmov\tr0, r7\n+\tstr\tr1, [sp, #8]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #8]\n-\tstr.w\tr0, [r6, #136]\t@ 0x88\n+\tldr\tr1, [sp, #8]\n+\tstr\tr0, [sp, #12]\n+\tstr.w\tr0, [r5, #136]\t@ 0x88\n \tcmp\tr0, #0\n-\tbeq.w\t1bf0 <__gridxc_mesh1d_MOD_set_mesh+0x13e8>\n-\tldr.w\tr2, [r6, #172]\t@ 0xac\n-\tadd.w\tr1, r6, #156\t@ 0x9c\n-\tvstr\td9, [r6, #184]\t@ 0xb8\n-\tstrd\tfp, r4, [r6, #164]\t@ 0xa4\n-\tstr.w\tsl, [r6, #140]\t@ 0x8c\n-\tstr.w\tr8, [r6, #180]\t@ 0xb4\n-\tstrh.w\tr7, [r6, #188]\t@ 0xbc\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1bfe <__gridxc_mesh1d_MOD_set_mesh+0x13f6>\n-\tmov\tr0, r5\n+\tbeq.w\t1c18 <__gridxc_mesh1d_MOD_set_mesh+0x1410>\n+\tstrd\tr1, r1, [r5, #184]\t@ 0xb8\n+\tldr.w\tr1, [r5, #172]\t@ 0xac\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr3, [r5, #168]\t@ 0xa8\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [r5, #164]\t@ 0xa4\n+\tstr.w\tfp, [r5, #160]\t@ 0xa0\n+\tstr.w\tr3, [r5, #140]\t@ 0x8c\n+\tstr.w\tr6, [r5, #156]\t@ 0x9c\n+\tstr.w\tr6, [r5, #180]\t@ 0xb4\n+\tstrh.w\tr8, [r5, #188]\t@ 0xbc\n+\tcmp\tr1, #0\n+\tbne.w\t1c26 <__gridxc_mesh1d_MOD_set_mesh+0x141e>\n+\tmov\tr0, r7\n+\tstr\tr1, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #12]\n-\tstr.w\tr0, [r6, #172]\t@ 0xac\n+\tldr\tr1, [sp, #16]\n+\tstr\tr0, [sp, #8]\n+\tstr.w\tr0, [r5, #172]\t@ 0xac\n \tcmp\tr0, #0\n-\tbeq.w\t1c0e <__gridxc_mesh1d_MOD_set_mesh+0x1406>\n-\tldr.w\tr2, [r6, #208]\t@ 0xd0\n-\tadd.w\tr1, r6, #192\t@ 0xc0\n-\tvstr\td9, [r6, #220]\t@ 0xdc\n-\tstr.w\tfp, [r6, #200]\t@ 0xc8\n-\tstr.w\tsl, [r6, #176]\t@ 0xb0\n-\tstr.w\tr8, [r6, #216]\t@ 0xd8\n-\tstrh.w\tr7, [r6, #224]\t@ 0xe0\n-\tstr.w\tr4, [r6, #204]\t@ 0xcc\n-\tvst1.32\t{d8}, [r1]\n-\tcmp\tr2, #0\n-\tbne.w\t1c1c <__gridxc_mesh1d_MOD_set_mesh+0x1414>\n-\tmov\tr0, r5\n+\tbeq.w\t1c36 <__gridxc_mesh1d_MOD_set_mesh+0x142e>\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr3, [r5, #176]\t@ 0xb0\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr3, [r5, #204]\t@ 0xcc\n+\tldr.w\tr3, [r5, #208]\t@ 0xd0\n+\tstrd\tr1, r1, [r5, #220]\t@ 0xdc\n+\tstrd\tfp, fp, [r5, #196]\t@ 0xc4\n+\tstrh.w\tr8, [r5, #224]\t@ 0xe0\n+\tstr.w\tr6, [r5, #192]\t@ 0xc0\n+\tstr.w\tr6, [r5, #216]\t@ 0xd8\n+\tcmp\tr3, #0\n+\tbne.w\t1c44 <__gridxc_mesh1d_MOD_set_mesh+0x143c>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tmov\tr5, r0\n-\tstr.w\tr0, [r6, #208]\t@ 0xd0\n+\tmov\tfp, r0\n+\tstr.w\tr0, [r5, #208]\t@ 0xd0\n \tcmp\tr0, #0\n-\tbeq.w\t1bc2 <__gridxc_mesh1d_MOD_set_mesh+0x13ba>\n-\tldr\tr2, [pc, #344]\t@ (d8c <__gridxc_mesh1d_MOD_set_mesh+0x584>)\n+\tbeq.w\t1bea <__gridxc_mesh1d_MOD_set_mesh+0x13e2>\n+\tldr\tr0, [sp, #0]\n \tmov.w\tr1, #4294967295\t@ 0xffffffff\n-\tvldr\td16, [pc, #264]\t@ d40 <__gridxc_mesh1d_MOD_set_mesh+0x538>\n-\tcmp\tr4, #0\n+\tldr\tr2, [pc, #332]\t@ (dcc <__gridxc_mesh1d_MOD_set_mesh+0x5c4>)\n+\tmovs\tr3, #1\n+\tcmp\tr0, #0\n \tadd\tr2, pc\n-\tldr\tr6, [sp, #24]\n-\tadd.w\tr3, r2, #228\t@ 0xe4\n-\tstr.w\tr4, [r2, #240]\t@ 0xf0\n-\tvst1.32\t{d16}, [r3]\n-\tmov.w\tr3, #1\n+\tit\tgt\n+\tldrgt\tr6, [sp, #20]\n \tstr.w\tr1, [r2, #212]\t@ 0xd4\n-\tstr.w\tr3, [r2, #236]\t@ 0xec\n-\tble.n\tc6e <__gridxc_mesh1d_MOD_set_mesh+0x466>\n+\tmov.w\tr1, #8\n+\tstr.w\tr0, [r2, #240]\t@ 0xf0\n+\tstr.w\tr1, [r2, #228]\t@ 0xe4\n+\tit\tgt\n+\tmovgt\tr1, r0\n+\tstrd\tr3, r3, [r2, #232]\t@ 0xe8\n+\tble.n\tcb6 <__gridxc_mesh1d_MOD_set_mesh+0x4ae>\n \tvmov\ts15, r3\n-\tcmp\tr3, r4\n+\tcmp\tr1, r3\n \tadd.w\tr3, r3, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvstmia\tr6!, {d16}\n-\tbne.n\tc5a <__gridxc_mesh1d_MOD_set_mesh+0x452>\n-\tcmp.w\tr9, #0\n-\tbeq.w\t16fc <__gridxc_mesh1d_MOD_set_mesh+0xef4>\n-\tadd.w\tr3, r9, r4, lsl #3\n-\tvldr\td8, [r9]\n-\tvldr\td0, [r9, #8]\n-\tsubs\tr6, r4, #1\n-\tsub.w\tfp, r4, #2\n-\tstr\tr6, [sp, #56]\t@ 0x38\n-\tvldr\td9, [r3, #-8]\n-\tvldr\td16, [r3, #-16]\n-\tvsub.f64\td0, d0, d8\n-\tvsub.f64\td16, d9, d16\n-\tvsub.f64\td9, d9, d8\n-\tvdiv.f64\td0, d16, d0\n+\tvcvt.f64.s32\td7, s15\n+\tvstmia\tr6!, {d7}\n+\tbne.n\tca2 <__gridxc_mesh1d_MOD_set_mesh+0x49a>\n+\tcmp.w\tsl, #0\n+\tbeq.w\t1760 <__gridxc_mesh1d_MOD_set_mesh+0xf58>\n+\tldr\tr2, [sp, #0]\n+\tvldr\td14, [sl]\n+\tvldr\td0, [sl, #8]\n+\tsubs\tr4, r2, #1\n+\tadd.w\tr3, sl, r2, lsl #3\n+\tsubs\tr7, r2, #2\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tvsub.f64\td0, d0, d14\n+\tldr\tr5, [pc, #248]\t@ (dd0 <__gridxc_mesh1d_MOD_set_mesh+0x5c8>)\n+\tvldr\td8, [r3, #-8]\n+\tvldr\td7, [r3, #-16]\n+\tadd\tr5, pc\n+\tvsub.f64\td7, d8, d7\n+\tvsub.f64\td8, d8, d14\n+\tvdiv.f64\td0, d7, d0\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmov\ts15, fp\n-\tvldr\td16, [pc, #156]\t@ d48 <__gridxc_mesh1d_MOD_set_mesh+0x540>\n-\tvcvt.f64.s32\td17, s15\n-\tvmov\ts15, r6\n-\tldr\tr6, [pc, #216]\t@ (d90 <__gridxc_mesh1d_MOD_set_mesh+0x588>)\n-\tvcvt.f64.s32\td18, s15\n-\tadd\tr6, pc\n-\tvdiv.f64\td10, d0, d17\n-\tvcmpe.f64\td10, d16\n-\tvstr\td10, [r6, #56]\t@ 0x38\n+\tvmov\ts15, r7\n+\tvmov\ts11, r4\n+\tvcvt.f64.s32\td6, s15\n+\tvldr\td7, [pc, #136]\t@ d88 <__gridxc_mesh1d_MOD_set_mesh+0x580>\n+\tvcvt.f64.s32\td5, s11\n+\tvdiv.f64\td9, d0, d6\n+\tvcmpe.f64\td9, d7\n+\tvstr\td9, [r5, #56]\t@ 0x38\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t1778 <__gridxc_mesh1d_MOD_set_mesh+0xf70>\n-\tldr\tr2, [pc, #192]\t@ (d94 <__gridxc_mesh1d_MOD_set_mesh+0x58c>)\n-\tvmul.f64\td0, d10, d18\n-\tldr\tr3, [pc, #188]\t@ (d98 <__gridxc_mesh1d_MOD_set_mesh+0x590>)\n+\tbmi.w\t17de <__gridxc_mesh1d_MOD_set_mesh+0xfd6>\n+\tldr\tr2, [pc, #184]\t@ (dd4 <__gridxc_mesh1d_MOD_set_mesh+0x5cc>)\n+\tvmul.f64\td0, d9, d5\n+\tldr\tr3, [pc, #180]\t@ (dd8 <__gridxc_mesh1d_MOD_set_mesh+0x5d0>)\n \tadd\tr2, pc\n \tadd\tr3, pc\n \tldmia\tr2, {r0, r1, r2}\n \tstmia\tr3!, {r0, r1}\n \tstrh.w\tr2, [r3], #2\n \tlsrs\tr2, r2, #16\n \tstrb\tr2, [r3, #0]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvsub.f64\td0, d0, d16\n-\tvdiv.f64\td16, d9, d0\n-\tvstr\td16, [r6, #48]\t@ 0x30\n-\tldr\tr6, [pc, #156]\t@ (d9c <__gridxc_mesh1d_MOD_set_mesh+0x594>)\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvsub.f64\td0, d0, d7\n+\tvdiv.f64\td7, d8, d0\n+\tvstr\td7, [r5, #48]\t@ 0x30\n+\tldr\tr5, [pc, #148]\t@ (ddc <__gridxc_mesh1d_MOD_set_mesh+0x5d4>)\n \tmovs\tr2, #7\n-\tldr\tr3, [pc, #156]\t@ (da0 <__gridxc_mesh1d_MOD_set_mesh+0x598>)\n+\tldr\tr3, [pc, #148]\t@ (de0 <__gridxc_mesh1d_MOD_set_mesh+0x5d8>)\n \tmovs\tr0, #11\n-\tadd\tr6, pc\n+\tadd\tr5, pc\n \tadd\tr3, pc\n-\tmov\tr1, r6\n+\tmov\tr1, r5\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t1678 <__gridxc_mesh1d_MOD_set_mesh+0xe70>\n-\tcmp\tr4, #1\n-\tble.n\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tldr\tr3, [pc, #136]\t@ (da4 <__gridxc_mesh1d_MOD_set_mesh+0x59c>)\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td18, d8\n-\tvldr\td21, [pc, #40]\t@ d50 <__gridxc_mesh1d_MOD_set_mesh+0x548>\n-\tadd\tr3, pc\n-\tadd.w\tr2, r9, #8\n-\tvmov.f64\td20, #240\t@ 0xbf800000 -1.0\n-\tvldr\td16, [r3, #40]\t@ 0x28\n+\tbne.w\t16e2 <__gridxc_mesh1d_MOD_set_mesh+0xeda>\n+\tldr\tr1, [sp, #0]\n+\tcmp\tr1, #1\n+\tble.n\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tldr\tr3, [pc, #124]\t@ (de4 <__gridxc_mesh1d_MOD_set_mesh+0x5dc>)\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td5, d14\n+\tvldr\td2, [pc, #32]\t@ d90 <__gridxc_mesh1d_MOD_set_mesh+0x588>\n+\tadd\tr3, pc\n+\tadd.w\tr2, sl, #8\n+\tvldr\td7, [r3, #40]\t@ 0x28\n \tmovs\tr3, #2\n-\tvdiv.f64\td19, d17, d16\n-\tb.n\tdae <__gridxc_mesh1d_MOD_set_mesh+0x5a6>\n-\tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n+\tvdiv.f64\td3, d4, d7\n+\tb.n\tdee <__gridxc_mesh1d_MOD_set_mesh+0x5e6>\n+\tnop.w\n \t.word\t0xa0b5ed8d\n \t.word\t0x3eb0c6f7\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000052e\n+\t.word\t0x0000056e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000508\n+\t.word\t0x0000054e\n R_ARM_REL32\t.LC13\n-\t.word\t0x000004ee\n+\t.word\t0x00000532\n R_ARM_REL32\t.LC14\n-\t.word\t0x000004d6\n+\t.word\t0x00000518\n R_ARM_REL32\t.LC15\n-\t.word\t0x00000482\n+\t.word\t0x000004c0\n R_ARM_REL32\t.LC37\n-\t.word\t0x0000047c\n+\t.word\t0x000004b6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000474\n+\t.word\t0x000004ae\n R_ARM_REL32\t.bss\n-\t.word\t0x000003cc\n+\t.word\t0x00000404\n R_ARM_REL32\t.bss\n-\t.word\t0x000003be\n+\t.word\t0x000003fc\n R_ARM_REL32\t.bss\n-\t.word\t0x000003a6\n+\t.word\t0x000003de\n R_ARM_REL32\t.bss\n-\t.word\t0x00000392\n+\t.word\t0x000003be\n R_ARM_REL32\t.bss\n-\t.word\t0x00000278\n+\t.word\t0x00000298\n R_ARM_REL32\t.bss\n-\t.word\t0x0000014c\n+\t.word\t0x00000146\n R_ARM_REL32\t.bss\n-\t.word\t0x000000d0\n+\t.word\t0x000000ec\n R_ARM_REL32\t.bss\n-\t.word\t0x000000b6\n+\t.word\t0x000000ae\n R_ARM_REL32\t.LC2\n-\t.word\t0x000000b8\n+\t.word\t0x000000b0\n R_ARM_REL32\t.data\n-\t.word\t0x00000092\n+\t.word\t0x0000008a\n R_ARM_REL32\t.data\n-\t.word\t0x00000094\n+\t.word\t0x0000008c\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000078\n+\t.word\t0x0000006e\n R_ARM_REL32\t.bss\n \tadds\tr3, #1\n-\tcmp\tr4, r3\n-\tblt.n\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tvmov.f64\td17, d18\n-\tvldmia\tr2!, {d18}\n-\tvmov.f64\td16, d20\n-\tvsub.f64\td17, d18, d17\n-\tvfma.f64\td16, d19, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d21\n+\tcmp\tr1, r3\n+\tblt.n\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tvmov.f64\td6, d5\n+\tvldmia\tr2!, {d5}\n+\tvmov.f64\td7, d4\n+\tvsub.f64\td6, d5, d6\n+\tvnmls.f64\td7, d6, d3\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d2\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\tda8 <__gridxc_mesh1d_MOD_set_mesh+0x5a0>\n-\tldr.w\tr5, [pc, #1332]\t@ 1308 <__gridxc_mesh1d_MOD_set_mesh+0xb00>\n-\tldr.w\tr2, [pc, #1332]\t@ 130c <__gridxc_mesh1d_MOD_set_mesh+0xb04>\n+\tble.n\tde8 <__gridxc_mesh1d_MOD_set_mesh+0x5e0>\n+\tldr.w\tr5, [pc, #1324]\t@ 1340 <__gridxc_mesh1d_MOD_set_mesh+0xb38>\n+\tldr.w\tr2, [pc, #1324]\t@ 1344 <__gridxc_mesh1d_MOD_set_mesh+0xb3c>\n \tadd\tr5, pc\n \tadd\tr2, pc\n \tmov\tr3, r5\n \tmovw\tr6, #8224\t@ 0x2020\n \tldmia\tr2, {r0, r1, r2}\n \tstmia\tr3!, {r0, r1}\n \tstrb\tr2, [r3, #0]\n \tstrh.w\tr6, [r5, #9]\n-\tldr.w\tr5, [pc, #1312]\t@ 1310 <__gridxc_mesh1d_MOD_set_mesh+0xb08>\n+\tldr.w\tr5, [pc, #1304]\t@ 1348 <__gridxc_mesh1d_MOD_set_mesh+0xb40>\n \tmovs\tr2, #9\n-\tldr.w\tr3, [pc, #1312]\t@ 1314 <__gridxc_mesh1d_MOD_set_mesh+0xb0c>\n+\tldr.w\tr3, [pc, #1304]\t@ 134c <__gridxc_mesh1d_MOD_set_mesh+0xb44>\n \tmovs\tr0, #11\n \tadd\tr5, pc\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t153a <__gridxc_mesh1d_MOD_set_mesh+0xd32>\n-\tldr.w\tr3, [pc, #1292]\t@ 1318 <__gridxc_mesh1d_MOD_set_mesh+0xb10>\n-\tsubs\tr2, r4, #1\n-\tsub.w\tfp, r4, #2\n-\tadd\tr3, pc\n-\tldr.w\tr1, [r3, #176]\t@ 0xb0\n-\tstr\tr1, [sp, #20]\n-\tldr\tr1, [r3, #32]\n+\tbne.w\t15a0 <__gridxc_mesh1d_MOD_set_mesh+0xd98>\n+\tldr\tr6, [sp, #0]\n+\tsubs\tr3, r6, #1\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr.w\tr3, [pc, #1280]\t@ 1350 <__gridxc_mesh1d_MOD_set_mesh+0xb48>\n+\tsubs\tr7, r6, #2\n+\tadd\tr3, pc\n+\tldr.w\tr0, [r3, #176]\t@ 0xb0\n \tldr.w\tr8, [r3, #164]\t@ 0xa4\n-\tadd.w\tip, r1, #4294967295\t@ 0xffffffff\n-\tldr.w\tr1, [r3, #200]\t@ 0xc8\n-\tldr.w\tsl, [r3, #128]\t@ 0x80\n-\tsub.w\tr5, r1, r8\n-\tldr.w\tr1, [r3, #396]\t@ 0x18c\n-\tstr\tr5, [sp, #64]\t@ 0x40\n-\tsub.w\tr5, r1, r8\n-\tldr.w\tr1, [r3, #276]\t@ 0x114\n-\tstr\tr5, [sp, #68]\t@ 0x44\n-\tsub.w\tr5, r1, sl\n-\tldr\tr1, [r3, #4]\n+\tstr\tr0, [sp, #16]\n+\tldr.w\tr0, [r3, #200]\t@ 0xc8\n+\tldr.w\tr1, [r3, #128]\t@ 0x80\n+\tsub.w\tr5, r0, r8\n+\tldr.w\tr0, [r3, #380]\t@ 0x17c\n+\tstr\tr5, [sp, #72]\t@ 0x48\n+\tsub.w\tr5, r0, r8\n+\tldr.w\tr0, [r3, #272]\t@ 0x110\n \tstr\tr5, [sp, #76]\t@ 0x4c\n-\tstr\tr1, [sp, #44]\t@ 0x2c\n+\tsubs\tr5, r0, r1\n+\tstr\tr5, [sp, #84]\t@ 0x54\n \tldr\tr5, [r3, #100]\t@ 0x64\n-\tldr\tr1, [r3, #8]\n \tstr\tr5, [sp, #4]\n-\tstr\tr1, [sp, #88]\t@ 0x58\n \tldr.w\tr5, [r3, #136]\t@ 0x88\n-\tldr.w\tr1, [r3, #168]\t@ 0xa8\n-\tldr\tr6, [r3, #104]\t@ 0x68\n-\tldr.w\tr7, [r3, #140]\t@ 0x8c\n-\tldr.w\tr0, [r3, #212]\t@ 0xd4\n-\tstr\tr5, [sp, #8]\n-\tstr\tr1, [sp, #28]\n-\tldr.w\tr5, [r3, #172]\t@ 0xac\n-\tldr.w\tr1, [r3, #368]\t@ 0x170\n-\tstr\tr0, [sp, #84]\t@ 0x54\n+\tldr.w\tr0, [r3, #168]\t@ 0xa8\n \tstr\tr5, [sp, #12]\n-\tstr\tr6, [sp, #16]\n-\tldr.w\tr5, [r3, #208]\t@ 0xd0\n-\tstr\tr7, [sp, #24]\n-\tstr\tr1, [sp, #36]\t@ 0x24\n-\tldr.w\tr1, [r3, #372]\t@ 0x174\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tldr.w\tr1, [r3, #132]\t@ 0x84\n-\tstr\tr1, [sp, #52]\t@ 0x34\n-\tldr.w\tr1, [r3, #248]\t@ 0xf8\n-\tldr.w\tr3, [r3, #252]\t@ 0xfc\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tadds\tr3, r6, #3\n+\tldr.w\tr5, [r3, #172]\t@ 0xac\n+\tldr.w\tr4, [r3, #140]\t@ 0x8c\n+\tldr.w\tr2, [r3, #212]\t@ 0xd4\n+\tstr\tr5, [sp, #8]\n+\tstr\tr0, [sp, #28]\n+\tldr\tr5, [r3, #4]\n+\tldr.w\tr0, [r3, #352]\t@ 0x160\n+\tldr.w\tr9, [r3, #104]\t@ 0x68\n+\tldr.w\tfp, [r3, #208]\t@ 0xd0\n+\tstr\tr4, [sp, #20]\n+\tadd.w\tip, r9, #1\n+\tstr\tr2, [sp, #24]\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tldr\tr2, [r3, #32]\n+\tstr\tr5, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [r3, #8]\n+\tadd.w\tlr, r2, #4294967295\t@ 0xffffffff\n+\tstr\tr0, [sp, #36]\t@ 0x24\n+\tldr.w\tr0, [r3, #356]\t@ 0x164\n+\tstr\tr0, [sp, #68]\t@ 0x44\n+\tldr.w\tr0, [r3, #132]\t@ 0x84\n+\tstr\tr0, [sp, #60]\t@ 0x3c\n+\tldr.w\tr0, [r3, #244]\t@ 0xf4\n+\tldr\tr2, [sp, #24]\n+\tldr.w\tr3, [r3, #248]\t@ 0xf8\n+\tstr\tr0, [sp, #32]\n+\tldr\tr0, [sp, #16]\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tadd.w\tr3, r9, #3\n \tstr\tr3, [sp, #96]\t@ 0x60\n-\tadds\tr3, r7, #3\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr3, [sp, #20]\n-\tstr\tr1, [sp, #32]\n-\tadds\tr1, r3, #3\n-\tstr\tr1, [sp, #104]\t@ 0x68\n-\tmov\tr1, r0\n-\tadds\tr0, #3\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n-\tadds\tr0, r6, #1\n-\tstr\tr0, [sp, #92]\t@ 0x5c\n-\tadds\tr0, r6, #2\n-\tstr\tr0, [sp, #112]\t@ 0x70\n-\tadds\tr0, r7, #1\n-\tstr\tr0, [sp, #116]\t@ 0x74\n-\tadds\tr0, r7, #2\n-\tstr\tr0, [sp, #120]\t@ 0x78\n-\tadds\tr0, r3, #1\n-\tstr\tr0, [sp, #124]\t@ 0x7c\n-\tadds\tr0, r3, #2\n-\tstr\tr0, [sp, #128]\t@ 0x80\n-\tadds\tr0, r1, #1\n-\tstr\tr0, [sp, #132]\t@ 0x84\n-\tadds\tr0, r1, #2\n-\tstr\tr0, [sp, #136]\t@ 0x88\n-\tadds\tr0, r4, r6\n-\tstr\tr0, [sp, #56]\t@ 0x38\n-\tadds\tr0, r2, r6\n-\tstr\tr0, [sp, #140]\t@ 0x8c\n-\tadds\tr0, r4, r7\n-\tstr\tr0, [sp, #144]\t@ 0x90\n-\tadds\tr0, r2, r7\n-\tstr\tr0, [sp, #148]\t@ 0x94\n-\tadds\tr0, r4, r3\n-\tadds\tr3, r2, r3\n-\tstr\tr0, [sp, #152]\t@ 0x98\n+\tmov\tr3, r4\n+\tadds\tr1, r3, #1\n+\tstr\tr1, [sp, #112]\t@ 0x70\n+\tadds\tr1, r3, #2\n+\tstr\tr1, [sp, #116]\t@ 0x74\n+\tadds\tr1, r0, #1\n+\tstr\tr1, [sp, #120]\t@ 0x78\n+\tadds\tr1, r0, #2\n+\tstr\tr1, [sp, #124]\t@ 0x7c\n+\tmov\tr1, r2\n+\tadds\tr4, #3\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #128]\t@ 0x80\n+\tmov\tr1, r2\n+\tstr\tr4, [sp, #100]\t@ 0x64\n+\tadds\tr1, #2\n+\tstr\tr1, [sp, #132]\t@ 0x84\n+\tldr\tr1, [sp, #88]\t@ 0x58\n+\tadds\tr4, r0, #3\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tmov\tr4, r2\n+\tadd.w\tr2, r6, r9\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tadd.w\tr2, r1, r9\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tadds\tr2, r6, r3\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n+\tadds\tr2, r1, r3\n+\tldr\tr3, [sp, #24]\n+\tstr\tr2, [sp, #144]\t@ 0x90\n+\tadds\tr2, r6, r0\n+\tstr\tr2, [sp, #148]\t@ 0x94\n+\tadds\tr2, r1, r0\n+\tstr\tr2, [sp, #152]\t@ 0x98\n+\tadds\tr2, r1, r3\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tadds\tr4, #3\n+\tadds\tr3, r6, r3\n+\tstr.w\tip, [sp, #92]\t@ 0x5c\n \tstr\tr3, [sp, #156]\t@ 0x9c\n-\tadds\tr3, r2, r1\n-\tstr\tr3, [sp, #164]\t@ 0xa4\n-\tadds\tr3, r4, r1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tsub.w\tr3, sl, r8\n-\tstr\tr3, [sp, #80]\t@ 0x50\n+\tadd.w\tip, r9, #2\n+\tsub.w\tr3, r1, r8\n+\tstr.w\tip, [sp, #108]\t@ 0x6c\n+\tstr\tr2, [sp, #168]\t@ 0xa8\n+\tstr\tr3, [sp, #88]\t@ 0x58\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tble.n\tf0c <__gridxc_mesh1d_MOD_set_mesh+0x704>\n+\tble.n\tf64 <__gridxc_mesh1d_MOD_set_mesh+0x75c>\n+\tadd.w\tr0, lr, #1\n \tlsls\tr2, r3, #3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd.w\tr0, ip, #1\n-\tmov\tr1, r9\n-\tadd\tr0, r3\n \tldr\tr3, [sp, #44]\t@ 0x2c\n+\tadd\tr0, r5\n+\tmov\tr1, sl\n \tadd.w\tr0, r3, r0, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tcmp.w\tfp, #2\n-\tble.w\t11c0 <__gridxc_mesh1d_MOD_set_mesh+0x9b8>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tadd.w\tlr, fp, #4294967295\t@ 0xffffffff\n+\tcmp\tr7, #2\n+\tble.w\t1216 <__gridxc_mesh1d_MOD_set_mesh+0xa0e>\n \tldr\tr6, [sp, #44]\t@ 0x2c\n-\tcmp.w\tfp, #5\n-\tmov.w\tr2, r3, lsl #3\n-\tadd.w\tr1, r2, #16\n-\tadd.w\tr0, r2, #24\n-\tadd.w\tr3, r2, #32\n-\tadd\tr1, r6\n+\tlsls\tr3, r5, #3\n+\tadd.w\tr0, r3, #16\n+\tadd.w\tr1, r3, #24\n+\tadd.w\tr2, r3, #32\n+\tadd.w\tip, r7, #4294967295\t@ 0xffffffff\n \tadd\tr0, r6\n-\tadd\tr3, r6\n-\tble.w\t1b02 <__gridxc_mesh1d_MOD_set_mesh+0x12fa>\n-\tvldr\td18, [r1]\n+\tadd\tr1, r6\n \tadd\tr2, r6\n-\tldr\tr1, [sp, #16]\n-\tvmov.f64\td21, #32\t@ 0x41000000 8.0\n-\tvldr\td17, [r3]\n-\tvmov.f64\td23, #48\t@ 0x41800000 16.0\n-\tldr\tr3, [sp, #4]\n-\tvmov.f64\td30, #62\t@ 0x41f00000 30.0\n-\tvldr\td16, [r0]\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tvldr\td22, [pc, #912]\t@ 12f0 <__gridxc_mesh1d_MOD_set_mesh+0xae8>\n-\tvmov.f64\td29, #96\t@ 0x3f000000 0.5\n-\tadd.w\tr7, r3, r1, lsl #3\n-\tldr\tr3, [sp, #8]\n-\tldr\tr1, [sp, #24]\n-\tvneg.f64\td31, d16\n-\tvmov.f64\td19, #16\t@ 0x40800000 4.0\n-\tvmov.f64\td28, #24\t@ 0x40c00000 6.0\n-\tadd.w\tr6, r3, r1, lsl #3\n-\tldr\tr3, [sp, #12]\n+\tcmp\tr7, #5\n+\tble.w\t1b6a <__gridxc_mesh1d_MOD_set_mesh+0x1362>\n+\tvldr\td3, [r2]\n+\tadd\tr3, r6\n+\tldr\tr2, [sp, #4]\n+\tvmov.f64\td15, #32\t@ 0x41000000 8.0\n+\tvldr\td11, [r0]\n+\tvmov.f64\td10, #48\t@ 0x41800000 16.0\n+\tvldr\td7, [r1]\n+\tvmov.f64\td13, #16\t@ 0x40800000 4.0\n \tldr\tr1, [sp, #20]\n-\tadd.w\tr0, r3, r1, lsl #3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadd.w\tr1, r5, r3, lsl #3\n-\tmovs\tr3, #3\n-\tvmov.f64\td27, d18\n-\tvldr\td26, [r2, #8]\n-\tvldr\td18, [r2, #40]\t@ 0x28\n-\tvmul.f64\td25, d17, d23\n-\tvldr\td24, [r2, #16]\n-\tvmov.f64\td6, d16\n-\tvmov.f64\td3, d26\n-\tvldr\td7, [r2, #24]\n-\tvadd.f64\td5, d26, d18\n-\tvmov.f64\td2, d18\n-\tvfms.f64\td5, d27, d19\n-\tvfma.f64\td2, d27, d20\n-\tvmov.f64\td0, d25\n-\tvfma.f64\td3, d17, d21\n-\tvfma.f64\td0, d27, d23\n-\tvmov.f64\td1, d24\n-\tvfma.f64\td1, d17, d30\n-\tvmov.f64\td4, d17\n-\tvfma.f64\td5, d16, d28\n-\tvldr\td16, [r2, #48]\t@ 0x30\n-\tvfms.f64\td3, d27, d21\n-\tvneg.f64\td9, d17\n-\tadd.w\tip, r3, #4\n-\tadds\tr2, #24\n-\tvfnms.f64\td1, d6, d23\n+\tadd.w\tr0, r2, r9, lsl #3\n+\tldr\tr2, [sp, #12]\n+\tldr\tr6, [sp, #16]\n+\tvldr\td12, [pc, #892]\t@ 1330 <__gridxc_mesh1d_MOD_set_mesh+0xb28>\n+\tadd.w\tr1, r2, r1, lsl #3\n+\tldr\tr2, [sp, #8]\n+\tstr\tr7, [sp, #172]\t@ 0xac\n+\tadd.w\tr6, r2, r6, lsl #3\n+\tldr\tr2, [sp, #24]\n+\tadd.w\tlr, fp, r2, lsl #3\n+\tmovs\tr2, #3\n+\tvmul.f64\td8, d3, d10\n+\tvmov.f64\td6, d11\n+\tvldr\td5, [r3, #8]\n+\tvmov.f64\td2, #62\t@ 0x41f00000 30.0\n+\tvmul.f64\td9, d11, d15\n+\tvldr\td11, [r3, #40]\t@ 0x28\n \tadds\tr1, #24\n-\tvfms.f64\td5, d17, d19\n-\tvsub.f64\td2, d2, d26\n-\tvfms.f64\td2, d17, d20\n-\tadds\tr7, #24\n-\tvsub.f64\td26, d0, d26\n-\tadds\tr6, #24\n-\tvfma.f64\td26, d31, d30\n+\tvldr\td0, [r3, #16]\n+\tvmov.f64\td4, d8\n+\tvmov.f64\td1, #24\t@ 0x40c00000 6.0\n+\tvmla.f64\td4, d6, d10\n \tadds\tr0, #24\n-\tadds\tr3, #3\n-\tcmp\tip, lr\n-\tvsub.f64\td0, d3, d18\n-\tvmov.f64\td3, d16\n-\tvfma.f64\td3, d6, d21\n-\tvsub.f64\td10, d1, d16\n-\tvstr\td5, [r1]\n-\tvadd.f64\td5, d16, d24\n-\tvfma.f64\td5, d17, d28\n-\tvldr\td17, [r2, #32]\n-\tvmul.f64\td2, d2, d29\n-\tvfma.f64\td10, d18, d23\n-\tvmul.f64\td0, d0, d22\n-\tvadd.f64\td27, d17, d7\n-\tvmov.f64\td1, d17\n-\tvfma.f64\td1, d4, d20\n-\tvstr\td2, [r0]\n-\tvmov.f64\td2, d16\n-\tvfma.f64\td2, d6, d20\n-\tvsub.f64\td6, d26, d18\n-\tvsub.f64\td25, d25, d27\n-\tvsub.f64\td3, d24, d3\n-\tvmov.f64\td26, d5\n-\tvfma.f64\td25, d16, d23\n-\tvmov.f64\td5, d17\n-\tvfma.f64\td26, d31, d19\n-\tvfma.f64\td5, d4, d21\n-\tvmov.f64\td31, d27\n-\tvfma.f64\td31, d9, d19\n-\tvfma.f64\td3, d18, d21\n-\tvsub.f64\td1, d1, d7\n-\tvfms.f64\td25, d18, d30\n-\tvfms.f64\td1, d16, d20\n-\tvfms.f64\td26, d18, d19\n-\tvsub.f64\td2, d2, d24\n-\tvmul.f64\td10, d10, d22\n-\tvfma.f64\td31, d18, d28\n-\tvfms.f64\td2, d18, d20\n-\tvmul.f64\td6, d6, d22\n-\tvstr\td0, [r7]\n-\tvsub.f64\td5, d7, d5\n-\tvstr\td10, [r6, #8]\n-\tvfma.f64\td5, d16, d21\n-\tvfms.f64\td31, d16, d19\n-\tvmul.f64\td24, d3, d22\n-\tvmul.f64\td25, d25, d22\n-\tvstr\td6, [r6]\n-\tvstr\td26, [r1, #8]\n-\tvmul.f64\td27, d2, d29\n-\tvstr\td24, [r7, #8]\n-\tvstr\td25, [r6, #16]\n-\tvmov.f64\td4, d31\n-\tvmul.f64\td7, d5, d22\n-\tvmul.f64\td5, d1, d29\n-\tvstr\td27, [r0, #8]\n-\tvneg.f64\td31, d16\n+\tadd.w\tlr, lr, #24\n+\tadds\tr6, #24\n+\tmov\tr7, r2\n+\tadds\tr3, #24\n+\tadds\tr7, #4\n+\tadds\tr2, #3\n+\tcmp\tr7, ip\n+\tvsub.f64\td4, d4, d5\n+\tvmls.f64\td4, d7, d2\n+\tvsub.f64\td4, d4, d11\n+\tvmul.f64\td4, d4, d12\n+\tvstr\td4, [r1]\n+\tvadd.f64\td4, d5, d11\n+\tvmls.f64\td4, d6, d13\n+\tvadd.f64\td6, d6, d6\n+\tvadd.f64\td6, d6, d11\n+\tvmla.f64\td4, d7, d1\n+\tvsub.f64\td6, d6, d5\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvmov.f64\td6, d0\n+\tvmla.f64\td6, d3, d2\n+\tvstr\td4, [sp, #160]\t@ 0xa0\n+\tvmov.f64\td2, d7\n+\tvmul.f64\td4, d7, d15\n+\tvnmls.f64\td6, d7, d10\n+\tvldr\td7, [r3, #24]\n+\tvadd.f64\td4, d7, d4\n+\tvsub.f64\td4, d0, d4\n+\tvsub.f64\td6, d6, d7\n+\tvmla.f64\td4, d11, d15\n+\tvmla.f64\td6, d11, d10\n+\tvmul.f64\td4, d4, d12\n+\tvmul.f64\td6, d6, d12\n+\tvstr\td4, [r0, #8]\n+\tvstr\td6, [r1, #8]\n+\tvadd.f64\td6, d7, d0\n+\tvmla.f64\td6, d3, d1\n+\tvmul.f64\td1, d3, d13\n+\tvmls.f64\td6, d2, d13\n+\tvadd.f64\td2, d2, d2\n+\tvadd.f64\td2, d2, d7\n+\tvmls.f64\td6, d11, d13\n+\tvsub.f64\td0, d2, d0\n+\tvmul.f64\td2, d3, d15\n+\tvadd.f64\td5, d5, d2\n+\tvstr\td6, [lr, #8]\n+\tvldr\td6, [r3]\n+\tvsub.f64\td5, d5, d9\n+\tvldr\td9, [sp, #48]\t@ 0x30\n+\tvsub.f64\td5, d5, d11\n+\tvmul.f64\td5, d5, d12\n+\tvstr\td5, [r0]\n+\tvadd.f64\td5, d3, d3\n+\tvldr\td3, [sp, #160]\t@ 0xa0\n+\tvsub.f64\td3, d3, d1\n+\tvsub.f64\td4, d9, d5\n+\tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n+\tvstr\td3, [lr]\n+\tvmul.f64\td4, d4, d9\n+\tvldr\td3, [r3, #32]\n+\tvadd.f64\td2, d2, d3\n+\tvadd.f64\td5, d5, d3\n+\tvstr\td4, [r6]\n+\tvsub.f64\td2, d6, d2\n+\tvsub.f64\td5, d5, d6\n+\tvmla.f64\td2, d7, d15\n+\tvadd.f64\td6, d3, d6\n+\tvsub.f64\td4, d8, d6\n+\tvsub.f64\td1, d6, d1\n+\tvmov.f64\td6, #24\t@ 0x40c00000 6.0\n+\tvmla.f64\td4, d7, d10\n+\tvmla.f64\td1, d11, d6\n+\tvadd.f64\td6, d11, d11\n+\tvmul.f64\td2, d2, d12\n+\tvsub.f64\td0, d0, d6\n+\tvmls.f64\td1, d7, d13\n+\tvstr\td2, [r0, #16]\n+\tvmov.f64\td2, #62\t@ 0x41f00000 30.0\n+\tvadd.f64\td6, d7, d7\n+\tvmls.f64\td4, d11, d2\n+\tvmul.f64\td0, d0, d9\n+\tvsub.f64\td5, d5, d6\n+\tvstr\td1, [lr, #16]\n+\tvstr\td0, [r6, #8]\n+\tvmul.f64\td5, d5, d9\n+\tvmul.f64\td4, d4, d12\n+\tvstr\td5, [r6, #16]\n \tvstr\td4, [r1, #16]\n-\tvstr\td7, [r7, #16]\n-\tvstr\td5, [r0, #16]\n-\tblt.w\tf8c <__gridxc_mesh1d_MOD_set_mesh+0x784>\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tvmov.f64\td22, #32\t@ 0x41000000 8.0\n+\tblt.w\tfc8 <__gridxc_mesh1d_MOD_set_mesh+0x7c0>\n+\tldr\tr7, [sp, #172]\t@ 0xac\n \tldr\tr1, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td21, #48\t@ 0x41800000 16.0\n-\tadd\tr2, r3\n-\tvldr\td23, [pc, #488]\t@ 12f0 <__gridxc_mesh1d_MOD_set_mesh+0xae8>\n-\tvmov.f64\td26, #62\t@ 0x41f00000 30.0\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tadd.w\tr2, r1, r2, lsl #3\n-\tldr\tr1, [sp, #16]\n-\tvmov.f64\td25, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td24, #24\t@ 0x40c00000 6.0\n-\tadds\tr7, r1, r3\n+\tadds\tr3, r2, r5\n+\tadd.w\tr6, r9, r2\n+\tvldr\td10, [pc, #472]\t@ 1330 <__gridxc_mesh1d_MOD_set_mesh+0xb28>\n+\tvmov.f64\td9, #32\t@ 0x41000000 8.0\n+\tvmov.f64\td8, #48\t@ 0x41800000 16.0\n+\tadd.w\tr3, r1, r3, lsl #3\n \tldr\tr1, [sp, #4]\n-\tvmov.f64\td19, #16\t@ 0x40800000 4.0\n-\tadd.w\tr7, r1, r7, lsl #3\n-\tldr\tr1, [sp, #24]\n-\tadds\tr6, r1, r3\n-\tldr\tr1, [sp, #8]\n+\tvmov.f64\td11, #62\t@ 0x41f00000 30.0\n+\tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n+\tvmov.f64\td13, #24\t@ 0x40c00000 6.0\n+\tvmov.f64\td0, #16\t@ 0x40800000 4.0\n \tadd.w\tr6, r1, r6, lsl #3\n \tldr\tr1, [sp, #20]\n-\tadds\tr0, r1, r3\n+\tadds\tr5, r1, r2\n \tldr\tr1, [sp, #12]\n+\tadd.w\tr5, r1, r5, lsl #3\n+\tldr\tr1, [sp, #16]\n+\tadds\tr0, r1, r2\n+\tldr\tr1, [sp, #8]\n \tadd.w\tr0, r1, r0, lsl #3\n-\tldr\tr1, [sp, #84]\t@ 0x54\n-\tadd\tr1, r3\n-\tadd.w\tr1, r5, r1, lsl #3\n-\tvldr\td7, [r2, #-16]\n-\tadds\tr3, #1\n-\tvldr\td31, [r2, #-8]\n-\tcmp\tfp, r3\n-\tvldr\td28, [r2, #16]\n-\tvmov.f64\td16, d7\n-\tvldr\td30, [r2, #8]\n-\tvfnms.f64\td16, d31, d21\n-\tvmov.f64\td18, d7\n-\tvmov.f64\td17, d28\n-\tvfnms.f64\td18, d31, d20\n-\tvfnms.f64\td17, d30, d22\n-\tvldmia\tr2!, {d29}\n-\tvadd.f64\td27, d28, d7\n-\tvfma.f64\td16, d30, d21\n-\tvfma.f64\td27, d29, d24\n-\tvadd.f64\td18, d28, d18\n-\tvfms.f64\td27, d31, d19\n-\tvadd.f64\td17, d17, d7\n-\tvfms.f64\td18, d30, d20\n-\tvfms.f64\td17, d31, d22\n-\tvsub.f64\td16, d16, d28\n-\tvfms.f64\td16, d29, d26\n-\tvfms.f64\td27, d30, d19\n-\tvmul.f64\td18, d18, d25\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvstmia\tr1!, {d27}\n-\tvstmia\tr0!, {d18}\n-\tvstmia\tr7!, {d17}\n-\tvstmia\tr6!, {d16}\n-\tbge.n\t1146 <__gridxc_mesh1d_MOD_set_mesh+0x93e>\n-\tldr\tr6, [sp, #12]\n-\tvmov.f64\td19, #0\t@ 0x40000000 2.0\n+\tldr\tr1, [sp, #24]\n+\tadd\tr1, r2\n+\tadd.w\tr1, fp, r1, lsl #3\n+\tvldr\td6, [r3, #-16]\n+\tadds\tr2, #1\n+\tvldr\td7, [r3, #16]\n+\tcmp\tr7, r2\n+\tvldr\td4, [r3, #-8]\n+\tvmov.f64\td15, d6\n+\tvldr\td5, [r3, #8]\n+\tvmov.f64\td1, d7\n+\tvldmia\tr3!, {d2}\n+\tvadd.f64\td3, d4, d4\n+\tvnmls.f64\td15, d4, d8\n+\tvnmls.f64\td1, d5, d9\n+\tvsub.f64\td3, d3, d6\n+\tvmla.f64\td15, d5, d8\n+\tvadd.f64\td1, d1, d6\n+\tvadd.f64\td6, d7, d6\n+\tvmla.f64\td6, d2, d13\n+\tvmls.f64\td1, d4, d9\n+\tvsub.f64\td15, d15, d7\n+\tvadd.f64\td7, d3, d7\n+\tvmls.f64\td15, d2, d11\n+\tvadd.f64\td3, d5, d5\n+\tvmls.f64\td6, d4, d0\n+\tvsub.f64\td7, d7, d3\n+\tvmls.f64\td6, d5, d0\n+\tvmul.f64\td1, d1, d10\n+\tvmul.f64\td15, d15, d10\n+\tvmul.f64\td7, d7, d12\n+\tvstmia\tr6!, {d1}\n+\tvstmia\tr5!, {d15}\n+\tvstmia\tr0!, {d7}\n+\tvstmia\tr1!, {d6}\n+\tbge.n\t1198 <__gridxc_mesh1d_MOD_set_mesh+0x990>\n+\tldr\tr2, [sp, #8]\n+\tadd.w\tr6, fp, r4, lsl #3\n \tldr\tr3, [sp, #104]\t@ 0x68\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n-\tldr\tr0, [sp, #8]\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tadd.w\tr1, r6, r3, lsl #3\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr7, [sp, #4]\n-\tadd.w\tr2, r0, r2, lsl #3\n-\tldr\tr0, [sp, #124]\t@ 0x7c\n-\tadd.w\tip, r5, r3, lsl #3\n-\tvldr\td20, [r1]\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tldr\tr1, [sp, #12]\n+\tldr\tr4, [sp, #4]\n+\tadd.w\tlr, r2, r3, lsl #3\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr0, [sp, #120]\t@ 0x78\n+\tvldr\td1, [r6]\n+\tadd.w\tip, r1, r3, lsl #3\n \tldr\tr3, [sp, #96]\t@ 0x60\n-\tvldr\td16, [r2]\n-\tadd.w\tr0, r6, r0, lsl #3\n-\tvldr\td17, [ip]\n-\tvmov.f64\td22, d20\n-\tadd.w\tr3, r7, r3, lsl #3\n-\tvldr\td24, [pc, #248]\t@ 12f8 <__gridxc_mesh1d_MOD_set_mesh+0xaf0>\n-\tvmov.f64\td25, d16\n-\tvfms.f64\td22, d17, d19\n-\tvfma.f64\td25, d17, d19\n-\tvldr\td18, [r3]\n-\tvfma.f64\td18, d20, d19\n-\tvfms.f64\td25, d20, d19\n-\tvfms.f64\td18, d16, d19\n-\tvfnms.f64\td16, d20, d21\n-\tvstr\td22, [r0]\n-\tvmov.f64\td22, d20\n-\tldr\tr0, [sp, #8]\n-\tvfnms.f64\td22, d17, d21\n-\tvldr\td23, [r1]\n-\tvfms.f64\td18, d17, d24\n-\tldr\tr1, [sp, #116]\t@ 0x74\n-\tvsub.f64\td23, d23, d17\n-\tadd.w\tr1, r0, r1, lsl #3\n-\tvstr\td25, [r1]\n-\tmov\tr1, r6\n-\tvldr\td26, [r2]\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tvadd.f64\td22, d22, d26\n-\tadd.w\tr2, r7, r2, lsl #3\n-\tvstr\td18, [r2]\n-\tvldr\td25, [r3]\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tvadd.f64\td16, d16, d25\n-\tadd.w\tr3, r6, r3, lsl #3\n+\tadd.w\tr0, r2, r0, lsl #3\n+\tstr\tr0, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #116]\t@ 0x74\n+\tadd.w\tr5, r4, r3, lsl #3\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvldr\td6, [lr]\n+\tadd.w\tr0, r1, r0, lsl #3\n+\tvldr\td7, [ip]\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tvadd.f64\td0, d6, d6\n+\tstr\tr0, [sp, #92]\t@ 0x5c\n+\tvadd.f64\td8, d7, d7\n+\tldr\tr0, [sp, #128]\t@ 0x80\n+\tadd.w\tr3, r4, r3, lsl #3\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tvldr\td5, [r5]\n+\tvldr\td2, [pc, #196]\t@ 1338 <__gridxc_mesh1d_MOD_set_mesh+0xb30>\n+\tadd.w\tr3, r2, r3, lsl #3\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tadd.w\tr3, fp, r0, lsl #3\n+\tldr\tr0, [sp, #24]\n+\tvadd.f64\td5, d0, d5\n+\tadd\tr0, r7\n+\tvstr\td1, [r3]\n+\tmov\tr3, r4\n+\tldr\tr4, [sp, #108]\t@ 0x6c\n+\tadd.w\tr0, fp, r0, lsl #3\n+\tvsub.f64\td5, d5, d8\n+\tvmls.f64\td5, d1, d2\n+\tadd.w\tr4, r3, r4, lsl #3\n+\tstr\tr4, [sp, #24]\n+\tldr\tr4, [sp, #132]\t@ 0x84\n+\tadd.w\tr4, fp, r4, lsl #3\n+\tstr\tr4, [sp, #104]\t@ 0x68\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tadd.w\tr4, r3, r4, lsl #3\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tldr\tr4, [sp, #140]\t@ 0x8c\n+\tadd.w\tr4, r1, r4, lsl #3\n+\tstr\tr4, [sp, #112]\t@ 0x70\n+\tldr\tr4, [sp, #148]\t@ 0x94\n+\tadd.w\tr4, r2, r4, lsl #3\n+\tstr\tr4, [sp, #116]\t@ 0x74\n+\tldr\tr4, [sp, #156]\t@ 0x9c\n+\tvldr\td3, [r6]\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tadd.w\tr4, fp, r4, lsl #3\n+\tstr\tr4, [sp, #124]\t@ 0x7c\n+\tldr\tr4, [sp, #168]\t@ 0xa8\n+\tvstr\td5, [r6]\n+\tadd.w\tfp, fp, r4, lsl #3\n+\tldr\tr4, [sp, #136]\t@ 0x88\n+\tvldr\td8, [r5]\n+\tldr\tr5, [sp, #48]\t@ 0x30\n+\tadd.w\tr3, r3, r4, lsl #3\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr6, [sp, #100]\t@ 0x64\n+\tadd.w\tr4, r1, r3, lsl #3\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tadd.w\tr2, r2, r3, lsl #3\n+\tstr\tr2, [sp, #120]\t@ 0x78\n+\tldr\tr2, [sp, #20]\n+\tadds\tr3, r7, r2\n+\tadd.w\tr3, r1, r3, lsl #3\n+\tldr\tr1, [sp, #16]\n+\tadds\tr2, r7, r1\n+\tadd.w\tr1, r7, r9\n+\tldr\tr7, [sp, #8]\n \tadd.w\tr2, r7, r2, lsl #3\n-\tvstr\td23, [r3]\n-\tvldr\td23, [pc, #140]\t@ 1300 <__gridxc_mesh1d_MOD_set_mesh+0xaf8>\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tvfms.f64\td16, d17, d23\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvstr\td22, [r3]\n-\tldr\tr3, [sp, #132]\t@ 0x84\n-\tvstr\td16, [r2]\n-\tadd.w\tr3, r5, r3, lsl #3\n-\tldr\tr2, [sp, #136]\t@ 0x88\n-\tvstr\td17, [r3]\n-\tadd.w\tr2, r5, r2, lsl #3\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr6, [sp, #56]\t@ 0x38\n-\tadd\tr3, fp\n-\tldr\tr2, [sp, #148]\t@ 0x94\n-\tadd.w\tr3, r5, r3, lsl #3\n-\tadd.w\tr6, r7, r6, lsl #3\n-\tstr\tr6, [sp, #48]\t@ 0x30\n-\tldr\tr6, [sp, #144]\t@ 0x90\n-\tadd.w\tr6, r0, r6, lsl #3\n-\tstr\tr6, [sp, #56]\t@ 0x38\n-\tldr\tr6, [sp, #152]\t@ 0x98\n-\tadd.w\tr6, r1, r6, lsl #3\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tldr\tr6, [sp, #160]\t@ 0xa0\n-\tadd.w\tlr, r5, r6, lsl #3\n-\tldr\tr6, [sp, #164]\t@ 0xa4\n-\tstr.w\tlr, [sp, #92]\t@ 0x5c\n-\tadd.w\tr5, r5, r6, lsl #3\n-\tldr\tr6, [sp, #140]\t@ 0x8c\n-\tadd.w\tlr, r7, r6, lsl #3\n-\tmov\tr7, r0\n-\tadd.w\tr0, r0, r2, lsl #3\n-\tmov\tr2, r1\n-\tldr\tr1, [sp, #156]\t@ 0x9c\n-\tstr\tr0, [sp, #84]\t@ 0x54\n-\tldr\tr0, [sp, #16]\n-\tadd.w\tr6, r2, r1, lsl #3\n-\tldr\tr1, [sp, #20]\n-\tadd\tr0, fp\n-\tadd\tr1, fp\n-\tb.n\t131c <__gridxc_mesh1d_MOD_set_mesh+0xb14>\n-\tnop\n-\tnop.w\n+\tldr\tr7, [sp, #4]\n+\tadd.w\tr1, r7, r1, lsl #3\n+\tldr\tr7, [sp, #104]\t@ 0x68\n+\tvstr\td3, [r7]\n+\tvadd.f64\td3, d1, d1\n+\tvadd.f64\td5, d7, d3\n+\tvsub.f64\td3, d6, d3\n+\tvnmls.f64\td7, d6, d4\n+\tvnmls.f64\td6, d1, d4\n+\tb.n\t1354 <__gridxc_mesh1d_MOD_set_mesh+0xb4c>\n \t.word\t0x55555555\n \t.word\t0x3fb55555\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n-\t.word\t0x55555555\n-\t.word\t0x3fc55555\n-\t.word\t0x0000052c\n+\t.word\t0x00000524\n R_ARM_REL32\t.data\n-\t.word\t0x0000052e\n+\t.word\t0x00000526\n R_ARM_REL32\t.LC4\n-\t.word\t0x00000514\n+\t.word\t0x0000050c\n R_ARM_REL32\t.data\n-\t.word\t0x00000516\n+\t.word\t0x0000050e\n R_ARM_REL32\t.LC4\n-\t.word\t0x00000502\n+\t.word\t0x000004f8\n R_ARM_REL32\t.bss\n-\tadd.w\tr1, r2, r1, lsl #3\n-\tldr\tr2, [sp, #24]\n-\tadd\tr2, fp\n-\tvldr\td17, [r1]\n-\tadd.w\tr2, r7, r2, lsl #3\n-\tldr\tr7, [sp, #4]\n-\tvadd.f64\td20, d17, d17\n-\tvldr\td16, [r2]\n-\tadd.w\tr0, r7, r0, lsl #3\n-\tldr\tr7, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td22, d20\n-\tvldr\td18, [r0]\n-\tvfma.f64\td22, d16, d19\n-\tvadd.f64\td22, d22, d18\n-\tvldr\td18, [ip]\n-\tvstr\td18, [r7]\n-\tvldr\td18, [r3]\n-\tldr\tr7, [sp, #92]\t@ 0x5c\n-\tvfma.f64\td22, d18, d24\n-\tvmov.f64\td24, d17\n-\tvfma.f64\td20, d18, d19\n-\tvfma.f64\td24, d18, d19\n-\tvstr\td18, [r7]\n-\tldr\tr7, [sp, #48]\t@ 0x30\n-\tvstr\td22, [r7]\n-\tvldr\td22, [r0]\n-\tvadd.f64\td20, d16, d20\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tvadd.f64\td16, d16, d22\n-\tvfma.f64\td16, d17, d21\n-\tvstr\td24, [r0]\n-\tvldr\td19, [r1]\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tvfma.f64\td16, d18, d23\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tvadd.f64\td19, d19, d18\n-\tvstr\td20, [r1]\n-\tvldr\td20, [r2]\n-\tldrd\tr2, r3, [r3]\n-\tstrd\tr2, r3, [r5]\n-\tvadd.f64\td17, d17, d20\n-\tvstr\td19, [r6]\n-\tvfma.f64\td17, d18, d21\n-\tvstr\td16, [lr]\n-\tvstr\td17, [r0]\n-\tcmp.w\tr9, #0\n-\tbeq.w\t1664 <__gridxc_mesh1d_MOD_set_mesh+0xe5c>\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tcbz\tr3, 13e2 <__gridxc_mesh1d_MOD_set_mesh+0xbda>\n-\tldr.w\tr1, [pc, #1684]\t@ 1a60 <__gridxc_mesh1d_MOD_set_mesh+0x1258>\n-\tldrd\tr6, r7, [r3]\n-\tadd\tr1, pc\n-\tldr\tr3, [r1, #8]\n-\tadds\tr2, r4, r3\n-\tldr\tr3, [r1, #4]\n-\tadd.w\tr3, r3, r2, lsl #3\n-\tstrd\tr6, r7, [r3]\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tcmp\tsl, r3\n-\tbgt.n\t1484 <__gridxc_mesh1d_MOD_set_mesh+0xc7c>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tvsub.f64\td5, d5, d0\n+\tvstr\td5, [r5]\n+\tldr\tr5, [sp, #96]\t@ 0x60\n+\tvadd.f64\td7, d7, d8\n+\tvstr\td3, [r5]\n+\tvldr\td5, [lr]\n+\tvldr\td3, [ip]\n+\tldr\tr5, [sp, #92]\t@ 0x5c\n+\tvsub.f64\td5, d5, d1\n+\tvadd.f64\td6, d6, d3\n+\tvstr\td5, [r6]\n+\tvldr\td5, [pc, #520]\t@ 1588 <__gridxc_mesh1d_MOD_set_mesh+0xd80>\n+\tldr\tr6, [sp, #24]\n+\tvstr\td6, [r5]\n+\tvmls.f64\td7, d1, d5\n+\tvldr\td0, [r3]\n+\tvadd.f64\td6, d0, d0\n+\tvstr\td7, [r6]\n+\tvldr\td7, [r2]\n+\tvldr\td3, [r0]\n+\tvldr\td8, [r1]\n+\tvadd.f64\td1, d7, d7\n+\tldr\tr5, [sp, #124]\t@ 0x7c\n+\tvadd.f64\td6, d6, d1\n+\tvstr\td3, [r5]\n+\tldrd\tr6, r7, [r0]\n+\tstrd\tr6, r7, [fp]\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tvadd.f64\td6, d6, d8\n+\tvmla.f64\td6, d3, d2\n+\tvstr\td6, [r0]\n+\tvldr\td6, [r1]\n+\tldr\tr0, [sp, #108]\t@ 0x6c\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tvadd.f64\td6, d0, d6\n+\tvmla.f64\td6, d7, d4\n+\tvmla.f64\td6, d3, d5\n+\tvstr\td6, [r0]\n+\tvadd.f64\td6, d3, d3\n+\tvadd.f64\td1, d1, d6\n+\tvadd.f64\td6, d7, d6\n+\tvadd.f64\td1, d1, d0\n+\tvstr\td6, [r1]\n+\tvldr\td6, [r2]\n+\tldr\tr2, [sp, #112]\t@ 0x70\n+\tvadd.f64\td6, d6, d3\n+\tvstr\td1, [r2]\n+\tvldr\td5, [r3]\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tvadd.f64\td7, d7, d5\n+\tvmla.f64\td7, d3, d4\n+\tvstr\td6, [r2]\n+\tvstr\td7, [r4]\n+\tcmp.w\tsl, #0\n+\tbeq.w\t16ce <__gridxc_mesh1d_MOD_set_mesh+0xec6>\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tcbz\tr2, 143a <__gridxc_mesh1d_MOD_set_mesh+0xc32>\n+\tldr\tr3, [pc, #364]\t@ (1590 <__gridxc_mesh1d_MOD_set_mesh+0xd88>)\n+\tldrd\tr0, r1, [r2]\n+\tadd\tr3, pc\n+\tldr\tr4, [sp, #0]\n+\tldr\tr2, [r3, #8]\n+\tldr\tr3, [r3, #4]\n+\tadd\tr4, r2\n+\tadd.w\tr3, r3, r4, lsl #3\n+\tstrd\tr0, r1, [r3]\n+\tldrd\tr2, r3, [sp, #56]\t@ 0x38\n+\tcmp\tr2, r3\n+\tbgt.n\t14d6 <__gridxc_mesh1d_MOD_set_mesh+0xcce>\n+\tldr\tr1, [sp, #84]\t@ 0x54\n \tadds\tr3, #1\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tsub.w\tr3, r3, sl\n-\tadd\tr1, sl\n+\tldr\tr0, [sp, #80]\t@ 0x50\n+\tadd.w\tr4, r9, r2\n \tadd\tr1, r2\n-\tldr\tr2, [sp, #32]\n-\tadd.w\tr1, r2, r1, lsl #3\n-\tldr\tr2, [sp, #16]\n-\tadd.w\tr4, r2, sl\n+\tsubs\tr3, r3, r2\n \tldr\tr2, [sp, #4]\n+\tadd\tr1, r0\n+\tldr\tr0, [sp, #32]\n \tadd.w\tr4, r2, r4, lsl #3\n \tmovs\tr2, #0\n+\tadd.w\tr1, r0, r1, lsl #3\n \tmov\tr0, r4\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tadds\tr2, #1\n \tcmp\tr3, r2\n-\tvabs.f64\td16, d16\n-\tvsqrt.f64\td17, d16\n-\tvstmia\tr1!, {d17}\n-\tbne.n\t140c <__gridxc_mesh1d_MOD_set_mesh+0xc04>\n-\tldr.w\tr6, [pc, #1600]\t@ 1a64 <__gridxc_mesh1d_MOD_set_mesh+0x125c>\n+\tvabs.f64\td7, d7\n+\tvsqrt.f64\td6, d7\n+\tvstmia\tr1!, {d6}\n+\tbne.n\t1462 <__gridxc_mesh1d_MOD_set_mesh+0xc5a>\n+\tldr\tr6, [pc, #280]\t@ (1594 <__gridxc_mesh1d_MOD_set_mesh+0xd8c>)\n \tmov\tr5, r4\n \tmovs\tr0, #0\n \tadd\tr6, pc\n-\tldr.w\tr1, [r6, #292]\t@ 0x124\n-\tldr.w\tr2, [r6, #316]\t@ 0x13c\n+\tldr.w\tr1, [r6, #284]\t@ 0x11c\n+\tldr.w\tr2, [r6, #308]\t@ 0x134\n \tadd\tr2, r1\n-\tldr.w\tr1, [r6, #288]\t@ 0x120\n+\tldr.w\tr1, [r6, #280]\t@ 0x118\n \tadd.w\tr1, r1, r2, lsl #3\n-\tvldmia\tr5!, {d16}\n+\tvldmia\tr5!, {d7}\n \tadds\tr0, #1\n \tcmp\tr0, r3\n-\tvabs.f64\td16, d16\n-\tvsqrt.f64\td17, d16\n-\tvmul.f64\td16, d17, d16\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t143e <__gridxc_mesh1d_MOD_set_mesh+0xc36>\n-\tldr.w\tr5, [pc, #1548]\t@ 1a68 <__gridxc_mesh1d_MOD_set_mesh+0x1260>\n+\tvabs.f64\td7, d7\n+\tvsqrt.f64\td6, d7\n+\tvmul.f64\td7, d6, d7\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t1492 <__gridxc_mesh1d_MOD_set_mesh+0xc8a>\n+\tldr\tr5, [pc, #232]\t@ (1598 <__gridxc_mesh1d_MOD_set_mesh+0xd90>)\n \tmovs\tr0, #0\n \tadd\tr5, pc\n-\tldr.w\tr1, [r5, #332]\t@ 0x14c\n-\tldr.w\tr2, [r5, #356]\t@ 0x164\n+\tldr.w\tr1, [r5, #320]\t@ 0x140\n+\tldr.w\tr2, [r5, #344]\t@ 0x158\n \tadd\tr2, r1\n-\tldr.w\tr1, [r5, #328]\t@ 0x148\n+\tldr.w\tr1, [r5, #316]\t@ 0x13c\n \tadd.w\tr2, r1, r2, lsl #3\n-\tvldmia\tr4!, {d16}\n+\tvldmia\tr4!, {d7}\n \tadds\tr0, #1\n \tcmp\tr3, r0\n-\tvmul.f64\td16, d16, d16\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t1472 <__gridxc_mesh1d_MOD_set_mesh+0xc6a>\n+\tvmul.f64\td7, d7, d7\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t14c4 <__gridxc_mesh1d_MOD_set_mesh+0xcbc>\n \tldr\tr3, [sp, #28]\n \tcmp\tr8, r3\n-\tbgt.n\t1502 <__gridxc_mesh1d_MOD_set_mesh+0xcfa>\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tbgt.n\t1552 <__gridxc_mesh1d_MOD_set_mesh+0xd4a>\n+\tldr\tr1, [sp, #88]\t@ 0x58\n \tmov\tr5, r3\n-\tldr\tr3, [sp, #16]\n+\tldr\tr3, [sp, #4]\n \tadds\tr5, #1\n \tadd\tr1, r8\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tadd\tr1, r3\n-\tldr\tr3, [sp, #4]\n+\tldr\tr0, [sp, #72]\t@ 0x48\n+\tadd\tr1, r9\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n \tadd\tr0, r8\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr4, [sp, #24]\n-\tsub.w\tr5, r5, r8\n+\tldr\tr4, [sp, #20]\n \tadd.w\tr1, r3, r1, lsl #3\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #16]\n \tadd\tr2, r8\n \tadd\tr4, r8\n \tadd\tr0, r3\n-\tldr\tr3, [sp, #12]\n-\tvmov.f64\td20, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td19, #80\t@ 0x3e800000 0.250\n+\tldr\tr3, [sp, #8]\n+\tsub.w\tr5, r5, r8\n+\tvmov.f64\td3, #8\t@ 0x40400000 3.0\n+\tvmov.f64\td4, #80\t@ 0x3e800000 0.250\n \tadd.w\tr0, r3, r0, lsl #3\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tadd\tr2, r3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadd.w\tr2, r3, r2, lsl #3\n-\tldr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #12]\n \tadd.w\tr4, r3, r4, lsl #3\n \tmovs\tr3, #0\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr1!, {d6}\n \tadds\tr3, #1\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tcmp\tr3, r5\n-\tvldmia\tr4!, {d18}\n-\tvmul.f64\td16, d16, d17\n-\tvmul.f64\td17, d17, d17\n-\tvmul.f64\td18, d18, d18\n-\tvadd.f64\td16, d16, d16\n-\tvfnms.f64\td16, d18, d20\n-\tvmul.f64\td16, d16, d19\n-\tvdiv.f64\td18, d16, d17\n-\tvstmia\tr2!, {d18}\n-\tbne.n\t14d0 <__gridxc_mesh1d_MOD_set_mesh+0xcc8>\n-\tldr.w\tr3, [pc, #1384]\t@ 1a6c <__gridxc_mesh1d_MOD_set_mesh+0x1264>\n+\tvldmia\tr4!, {d5}\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td6, d6, d6\n+\tvmul.f64\td5, d5, d5\n+\tvadd.f64\td7, d7, d7\n+\tvnmls.f64\td7, d5, d3\n+\tvmul.f64\td7, d7, d4\n+\tvdiv.f64\td5, d7, d6\n+\tvstmia\tr2!, {d5}\n+\tbne.n\t1520 <__gridxc_mesh1d_MOD_set_mesh+0xd18>\n+\tldr\tr3, [pc, #72]\t@ (159c <__gridxc_mesh1d_MOD_set_mesh+0xd94>)\n \tmovs\tr2, #1\n \tadd\tr3, pc\n \tstr\tr2, [r3, #0]\n-\tadd\tsp, #172\t@ 0xac\n-\tvpop\t{d8-d11}\n+\tadd\tsp, #180\t@ 0xb4\n+\tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tcmp.w\tr9, #0\n-\tbeq.w\t8ec <__gridxc_mesh1d_MOD_set_mesh+0xe4>\n-\tadd.w\tr3, r9, r4, lsl #3\n-\tvldr\td17, [r9]\n-\tvldr\td18, [r3, #-8]\n-\tvsub.f64\td18, d18, d17\n-\tb.w\t8b0 <__gridxc_mesh1d_MOD_set_mesh+0xa8>\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #20]\n-\tb.w\t9e2 <__gridxc_mesh1d_MOD_set_mesh+0x1da>\n+\tcmp.w\tsl, #0\n+\tbeq.w\t8f2 <__gridxc_mesh1d_MOD_set_mesh+0xea>\n+\tadd.w\tr3, sl, r3, lsl #3\n+\tvldr\td6, [sl]\n+\tvldr\td5, [r3, #-8]\n+\tvsub.f64\td5, d5, d6\n+\tb.w\t8b4 <__gridxc_mesh1d_MOD_set_mesh+0xac>\n+\tmovs\tr4, #0\n+\tb.w\t9f0 <__gridxc_mesh1d_MOD_set_mesh+0x1e8>\n+\tnop\n+\t.word\t0x55555555\n+\t.word\t0x3fc55555\n+\t.word\t0x00000164\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000112\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000e4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000042\n+ R_ARM_REL32\t.bss\n \tldr\tr2, [r5, #0]\n \tmovw\tr3, #28524\t@ 0x6f6c\n \tmovt\tr3, #24935\t@ 0x6167\n \tcmp\tr2, r3\n-\tbeq.w\t184a <__gridxc_mesh1d_MOD_set_mesh+0x1042>\n-\tldr.w\tr3, [pc, #1316]\t@ 1a70 <__gridxc_mesh1d_MOD_set_mesh+0x1268>\n+\tbeq.w\t18b0 <__gridxc_mesh1d_MOD_set_mesh+0x10a8>\n+\tldr.w\tr3, [pc, #1316]\t@ 1ad8 <__gridxc_mesh1d_MOD_set_mesh+0x12d0>\n \tmovs\tr2, #7\n-\tldr.w\tr1, [pc, #1312]\t@ 1a74 <__gridxc_mesh1d_MOD_set_mesh+0x126c>\n+\tldr.w\tr1, [pc, #1316]\t@ 1adc <__gridxc_mesh1d_MOD_set_mesh+0x12d4>\n \tmovs\tr0, #11\n \tadd\tr3, pc\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\t17ae <__gridxc_mesh1d_MOD_set_mesh+0xfa6>\n-\tldr.w\tr2, [pc, #1296]\t@ 1a78 <__gridxc_mesh1d_MOD_set_mesh+0x1270>\n-\tcmp\tr4, #0\n+\tbne.w\t1814 <__gridxc_mesh1d_MOD_set_mesh+0x100c>\n+\tldr.w\tr2, [pc, #1300]\t@ 1ae0 <__gridxc_mesh1d_MOD_set_mesh+0x12d8>\n \tadd\tr2, pc\n \tldr.w\tr8, [r2, #164]\t@ 0xa4\n \tldr.w\tr3, [r2, #200]\t@ 0xc8\n-\tldr.w\tsl, [r2, #128]\t@ 0x80\n+\tldr.w\tr1, [r2, #128]\t@ 0x80\n \tsub.w\tr3, r3, r8\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr.w\tr3, [r2, #396]\t@ 0x18c\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr.w\tr3, [r2, #380]\t@ 0x17c\n+\tldr.w\tr9, [r2, #104]\t@ 0x68\n \tsub.w\tr3, r3, r8\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr3, [r2, #276]\t@ 0x114\n-\tsub.w\tr3, r3, sl\n \tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr.w\tr3, [r2, #272]\t@ 0x110\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tsubs\tr3, r3, r1\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tldr\tr3, [r2, #100]\t@ 0x64\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [r2, #104]\t@ 0x68\n-\tstr\tr3, [sp, #16]\n \tldr.w\tr3, [r2, #136]\t@ 0x88\n-\tstr\tr3, [sp, #8]\n+\tstr\tr3, [sp, #12]\n \tldr.w\tr3, [r2, #140]\t@ 0x8c\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #20]\n \tldr.w\tr3, [r2, #172]\t@ 0xac\n-\tstr\tr3, [sp, #12]\n+\tstr\tr3, [sp, #8]\n \tldr.w\tr3, [r2, #176]\t@ 0xb0\n-\tstr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #16]\n \tldr.w\tr3, [r2, #168]\t@ 0xa8\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r2, #368]\t@ 0x170\n+\tldr.w\tr3, [r2, #352]\t@ 0x160\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr.w\tr3, [r2, #372]\t@ 0x174\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tr3, [r2, #356]\t@ 0x164\n+\tstr\tr3, [sp, #68]\t@ 0x44\n \tldr.w\tr3, [r2, #132]\t@ 0x84\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr3, [r2, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tr3, [r2, #244]\t@ 0xf4\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r2, #252]\t@ 0xfc\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tsub.w\tr3, sl, r8\n+\tldr.w\tr3, [r2, #248]\t@ 0xf8\n \tstr\tr3, [sp, #80]\t@ 0x50\n-\tble.w\t13be <__gridxc_mesh1d_MOD_set_mesh+0xbb6>\n+\tsub.w\tr3, r1, r8\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #0]\n+\tcmp\tr4, #0\n+\tble.w\t1416 <__gridxc_mesh1d_MOD_set_mesh+0xc0e>\n \tldr\tr1, [r2, #8]\n \tmov\tr3, r0\n \tldrd\tr6, r5, [r2, #208]\t@ 0xd0\n \tadds\tr0, r1, #1\n \tldr\tr1, [r2, #4]\n-\tvldr\td16, [r2, #40]\t@ 0x28\n+\tvldr\td7, [r2, #40]\t@ 0x28\n+\tmov\tr2, r4\n \tadd.w\tr1, r1, r0, lsl #3\n-\tvmov\ts15, r3\n-\tvmov.f64\td17, d8\n+\tvmov\ts13, r3\n \tmov\tr0, r3\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td18, s15\n-\tcmp\tr4, r3\n-\tvfma.f64\td17, d16, d18\n-\tvstmia\tr1!, {d17}\n-\tbne.n\t15f4 <__gridxc_mesh1d_MOD_set_mesh+0xdec>\n-\tldr\tr2, [sp, #16]\n-\tadds\tr0, #2\n-\tadds\tr1, r2, #1\n+\tvcvt.f64.s32\td5, s13\n+\tvmov.f64\td6, d14\n+\tcmp\tr2, r3\n+\tvmla.f64\td6, d5, d7\n+\tvstmia\tr1!, {d6}\n+\tbne.n\t165e <__gridxc_mesh1d_MOD_set_mesh+0xe56>\n \tldr\tr2, [sp, #4]\n+\tadd.w\tr1, r9, #1\n+\tadds\tr0, #2\n \tadd.w\tr1, r2, r1, lsl #3\n \tmovs\tr2, #1\n \tadds\tr2, #1\n-\tvstmia\tr1!, {d16}\n+\tvstmia\tr1!, {d7}\n \tcmp\tr0, r2\n-\tbne.n\t161e <__gridxc_mesh1d_MOD_set_mesh+0xe16>\n+\tbne.n\t1688 <__gridxc_mesh1d_MOD_set_mesh+0xe80>\n \tlsls\tr7, r3, #3\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #20]\n \tmov\tr2, r7\n \tmovs\tr1, #0\n \tadds\tr0, r3, #1\n-\tldr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #12]\n \tadd.w\tr0, r3, r0, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #16]\n \tmov\tr2, r7\n \tmovs\tr1, #0\n \tadds\tr0, r3, #1\n-\tldr\tr3, [sp, #12]\n+\tldr\tr3, [sp, #8]\n \tadd.w\tr0, r3, r0, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadds\tr0, r5, #1\n \tmov\tr2, r7\n \tmovs\tr1, #0\n \tadd.w\tr0, r6, r0, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tcmp.w\tr9, #0\n-\tbne.w\t13c6 <__gridxc_mesh1d_MOD_set_mesh+0xbbe>\n-\tldr.w\tr2, [pc, #1044]\t@ 1a7c <__gridxc_mesh1d_MOD_set_mesh+0x1274>\n+\tcmp.w\tsl, #0\n+\tbne.w\t141e <__gridxc_mesh1d_MOD_set_mesh+0xc16>\n+\tldr.w\tr2, [pc, #1044]\t@ 1ae4 <__gridxc_mesh1d_MOD_set_mesh+0x12dc>\n \tadd\tr2, pc\n \tldrd\tr3, r2, [r2, #4]\n \tadd.w\tr3, r3, r2, lsl #3\n-\tvstr\td8, [r3, #8]\n-\tb.n\t13c6 <__gridxc_mesh1d_MOD_set_mesh+0xbbe>\n-\tldr\tr2, [r6, #0]\n+\tvstr\td14, [r3, #8]\n+\tb.n\t141e <__gridxc_mesh1d_MOD_set_mesh+0xc16>\n+\tldr\tr2, [r5, #0]\n \tmovw\tr3, #28524\t@ 0x6f6c\n \tmovt\tr3, #24935\t@ 0x6167\n \tcmp\tr2, r3\n-\tbeq.w\t1982 <__gridxc_mesh1d_MOD_set_mesh+0x117a>\n-\tldr\tr3, [pc, #1012]\t@ (1a80 <__gridxc_mesh1d_MOD_set_mesh+0x1278>)\n+\tbeq.w\t19ea <__gridxc_mesh1d_MOD_set_mesh+0x11e2>\n+\tldr\tr3, [pc, #1012]\t@ (1ae8 <__gridxc_mesh1d_MOD_set_mesh+0x12e0>)\n \tmovs\tr2, #9\n-\tldr\tr1, [pc, #1012]\t@ (1a84 <__gridxc_mesh1d_MOD_set_mesh+0x127c>)\n+\tldr\tr1, [pc, #1012]\t@ (1aec <__gridxc_mesh1d_MOD_set_mesh+0x12e4>)\n \tmovs\tr0, #11\n \tadd\tr3, pc\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n+\tmov\tr3, r0\n \tstr\tr0, [sp, #92]\t@ 0x5c\n \tcmp\tr0, #0\n-\tbne.w\t17ae <__gridxc_mesh1d_MOD_set_mesh+0xfa6>\n-\tmov.w\tsl, #1\n-\tldr\tr6, [sp, #56]\t@ 0x38\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmovs\tr1, #2\n-\tmov\tip, r0\n-\tmov\tr8, sl\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tstr\tr1, [sp, #108]\t@ 0x6c\n-\tstrd\tr0, r0, [sp, #76]\t@ 0x4c\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tstrd\tr0, r0, [sp, #64]\t@ 0x40\n-\tstr\tr4, [sp, #28]\n-\tstr.w\tfp, [sp, #164]\t@ 0xa4\n-\tstrd\tfp, r6, [sp, #156]\t@ 0x9c\n-\tstrd\tfp, r6, [sp, #148]\t@ 0x94\n-\tstrd\tfp, r6, [sp, #140]\t@ 0x8c\n-\tstr\tr0, [sp, #132]\t@ 0x84\n-\tstr\tr0, [sp, #124]\t@ 0x7c\n-\tstr\tr0, [sp, #116]\t@ 0x74\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tstr.w\tsl, [sp, #136]\t@ 0x88\n-\tstr.w\tsl, [sp, #128]\t@ 0x80\n-\tstr.w\tsl, [sp, #120]\t@ 0x78\n-\tstr.w\tsl, [sp, #112]\t@ 0x70\n-\tstrd\tr1, r1, [sp, #100]\t@ 0x64\n-\tstr\tr1, [sp, #96]\t@ 0x60\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tstrd\tr3, r3, [sp, #20]\n-\tstr\tr3, [sp, #16]\n-\tb.w\tef0 <__gridxc_mesh1d_MOD_set_mesh+0x6e8>\n-\tldr\tr3, [sp, #28]\n+\tbne.w\t1814 <__gridxc_mesh1d_MOD_set_mesh+0x100c>\n+\tldr\tr2, [sp, #0]\n+\tmovs\tr4, #2\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tmovs\tr5, #1\n+\tstr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr5, [sp, #56]\t@ 0x38\n+\tstrd\tr0, r0, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tstrd\tr0, r0, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tmov\tlr, r3\n+\tmov\tr8, r5\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tmov\tr9, r1\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tmov\tr3, r5\n+\tstr\tr2, [sp, #28]\n+\tmov\tr5, r1\n+\tstr\tr7, [sp, #168]\t@ 0xa8\n+\tstrd\tr7, r0, [sp, #152]\t@ 0x98\n+\tstrd\tr7, r0, [sp, #144]\t@ 0x90\n+\tstrd\tr7, r0, [sp, #136]\t@ 0x88\n+\tstr\tr1, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tstrd\tr4, r3, [sp, #104]\t@ 0x68\n+\tstrd\tr4, r4, [sp, #96]\t@ 0x60\n+\tstr\tr1, [sp, #24]\n+\tstrd\tr1, r1, [sp, #16]\n+\tb.w\tf4a <__gridxc_mesh1d_MOD_set_mesh+0x742>\n+\tldr\tr3, [sp, #24]\n \tcmp\tr3, #0\n-\tbeq.w\t1a32 <__gridxc_mesh1d_MOD_set_mesh+0x122a>\n-\tvldr\td8, [r3]\n+\tbeq.w\t1a9e <__gridxc_mesh1d_MOD_set_mesh+0x1296>\n+\tvldr\td14, [r3]\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, #0\n-\tbeq.w\t1a1e <__gridxc_mesh1d_MOD_set_mesh+0x1216>\n-\tsubs\tr3, r4, #1\n-\tvmov\ts18, r3\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n-\tvcvt.f64.s32\td9, s18\n+\tbeq.w\t1a8a <__gridxc_mesh1d_MOD_set_mesh+0x1282>\n+\tldr\tr3, [sp, #0]\n+\tsubs\tr3, #1\n+\tvmov\ts16, r3\n+\tldr\tr3, [sp, #280]\t@ 0x118\n+\tvcvt.f64.s32\td8, s16\n \tcmp\tr3, #0\n-\tbeq.w\t1834 <__gridxc_mesh1d_MOD_set_mesh+0x102c>\n-\tvldr\td16, [r3]\n-\tvldr\td17, [pc, #808]\t@ 1a50 <__gridxc_mesh1d_MOD_set_mesh+0x1248>\n-\tldr\tr5, [pc, #860]\t@ (1a88 <__gridxc_mesh1d_MOD_set_mesh+0x1280>)\n-\tvcmpe.f64\td16, d17\n+\tbeq.w\t189a <__gridxc_mesh1d_MOD_set_mesh+0x1092>\n+\tvldr\td7, [r3]\n+\tvldr\td6, [pc, #816]\t@ 1ac0 <__gridxc_mesh1d_MOD_set_mesh+0x12b8>\n+\tldr\tr5, [pc, #860]\t@ (1af0 <__gridxc_mesh1d_MOD_set_mesh+0x12e8>)\n+\tvcmpe.f64\td7, d6\n \tadd\tr5, pc\n-\tvstr\td16, [r5, #56]\t@ 0x38\n+\tvstr\td7, [r5, #56]\t@ 0x38\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t1acc <__gridxc_mesh1d_MOD_set_mesh+0x12c4>\n-\tldr\tr2, [pc, #844]\t@ (1a8c <__gridxc_mesh1d_MOD_set_mesh+0x1284>)\n-\tvmul.f64\td0, d16, d9\n-\tldr\tr3, [pc, #840]\t@ (1a90 <__gridxc_mesh1d_MOD_set_mesh+0x1288>)\n+\tbmi.w\t1b34 <__gridxc_mesh1d_MOD_set_mesh+0x132c>\n+\tldr\tr2, [pc, #844]\t@ (1af4 <__gridxc_mesh1d_MOD_set_mesh+0x12ec>)\n+\tvmul.f64\td0, d7, d8\n+\tldr\tr3, [pc, #844]\t@ (1af8 <__gridxc_mesh1d_MOD_set_mesh+0x12f0>)\n \tadd\tr2, pc\n \tadd\tr3, pc\n \tldmia\tr2, {r0, r1, r2}\n \tstmia\tr3!, {r0, r1}\n \tstrh.w\tr2, [r3], #2\n \tlsrs\tr2, r2, #16\n \tstrb\tr2, [r3, #0]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvsub.f64\td0, d0, d18\n-\tvldr\td16, [r3]\n-\tvsub.f64\td16, d16, d8\n-\tvdiv.f64\td18, d16, d0\n-\tvstr\td18, [r5, #48]\t@ 0x30\n-\tb.w\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tvdiv.f64\td16, d9, d18\n-\tldr\tr3, [pc, #788]\t@ (1a94 <__gridxc_mesh1d_MOD_set_mesh+0x128c>)\n-\tldr\tr2, [pc, #792]\t@ (1a98 <__gridxc_mesh1d_MOD_set_mesh+0x1290>)\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvsub.f64\td0, d0, d5\n+\tvldr\td7, [r3]\n+\tvsub.f64\td7, d7, d14\n+\tvdiv.f64\td5, d7, d0\n+\tvstr\td5, [r5, #48]\t@ 0x30\n+\tb.w\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tvdiv.f64\td7, d8, d5\n+\tldr\tr3, [pc, #792]\t@ (1afc <__gridxc_mesh1d_MOD_set_mesh+0x12f4>)\n+\tldr\tr2, [pc, #792]\t@ (1b00 <__gridxc_mesh1d_MOD_set_mesh+0x12f8>)\n \tmov.w\tr1, #538976288\t@ 0x20202020\n \tadd\tr3, pc\n \tadd\tr2, pc\n \tstr.w\tr1, [r3, #7]\n-\tvstr\td16, [r6, #40]\t@ 0x28\n+\tvstr\td7, [r5, #40]\t@ 0x28\n \tldmia.w\tr2, {r0, r1}\n \tstrh\tr1, [r3, #4]\n \tstr\tr0, [r3, #0]\n \tlsrs\tr1, r1, #16\n \tstrb\tr1, [r3, #6]\n-\tb.w\tcfe <__gridxc_mesh1d_MOD_set_mesh+0x4f6>\n+\tb.w\td46 <__gridxc_mesh1d_MOD_set_mesh+0x53e>\n \tmov\tr3, r1\n \tcmp\tr1, #2\n-\tbgt.w\t1a38 <__gridxc_mesh1d_MOD_set_mesh+0x1230>\n-\tmov\tr4, r3\n-\tb.w\t880 <__gridxc_mesh1d_MOD_set_mesh+0x78>\n-\tldr\tr3, [pc, #748]\t@ (1a9c <__gridxc_mesh1d_MOD_set_mesh+0x1294>)\n+\tbgt.w\t1aa4 <__gridxc_mesh1d_MOD_set_mesh+0x129c>\n+\tstr\tr3, [sp, #0]\n+\tb.w\t882 <__gridxc_mesh1d_MOD_set_mesh+0x7a>\n+\tldr\tr3, [pc, #748]\t@ (1b04 <__gridxc_mesh1d_MOD_set_mesh+0x12fc>)\n \tmovs\tr1, #34\t@ 0x22\n-\tldr\tr2, [sp, #16]\n-\tldr\tr0, [pc, #744]\t@ (1aa0 <__gridxc_mesh1d_MOD_set_mesh+0x1298>)\n-\tldr\tr3, [r2, r3]\n+\tldr\tr0, [pc, #748]\t@ (1b08 <__gridxc_mesh1d_MOD_set_mesh+0x1300>)\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #740]\t@ (1aa4 <__gridxc_mesh1d_MOD_set_mesh+0x129c>)\n+\tldr\tr3, [pc, #740]\t@ (1b0c <__gridxc_mesh1d_MOD_set_mesh+0x1304>)\n \tadd\tr3, pc\n \tldr\tr2, [r3, #100]\t@ 0x64\n-\tldr.w\tsl, [r3, #128]\t@ 0x80\n+\tldr.w\tr1, [r3, #128]\t@ 0x80\n \tstr\tr2, [sp, #4]\n-\tldr.w\tr2, [r3, #276]\t@ 0x114\n+\tldr.w\tr2, [r3, #272]\t@ 0x110\n \tldr.w\tr8, [r3, #164]\t@ 0xa4\n-\tsub.w\tr2, r2, sl\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tsubs\tr2, r2, r1\n+\tstr\tr2, [sp, #84]\t@ 0x54\n \tldr.w\tr2, [r3, #200]\t@ 0xc8\n+\tldr.w\tr9, [r3, #104]\t@ 0x68\n \tsub.w\tr2, r2, r8\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldr.w\tr2, [r3, #396]\t@ 0x18c\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr.w\tr2, [r3, #380]\t@ 0x17c\n+\tstr\tr1, [sp, #56]\t@ 0x38\n \tsub.w\tr2, r2, r8\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr2, [r3, #104]\t@ 0x68\n-\tstr\tr2, [sp, #16]\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n \tldr.w\tr2, [r3, #132]\t@ 0x84\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tldr.w\tr2, [r3, #248]\t@ 0xf8\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tldr.w\tr2, [r3, #244]\t@ 0xf4\n \tstr\tr2, [sp, #32]\n-\tldr.w\tr2, [r3, #252]\t@ 0xfc\n-\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr.w\tr2, [r3, #248]\t@ 0xf8\n+\tstr\tr2, [sp, #80]\t@ 0x50\n \tldr.w\tr2, [r3, #136]\t@ 0x88\n-\tstr\tr2, [sp, #8]\n+\tstr\tr2, [sp, #12]\n \tldr.w\tr2, [r3, #140]\t@ 0x8c\n-\tstr\tr2, [sp, #24]\n+\tstr\tr2, [sp, #20]\n \tldr.w\tr2, [r3, #168]\t@ 0xa8\n \tstr\tr2, [sp, #28]\n \tldr.w\tr2, [r3, #172]\t@ 0xac\n-\tstr\tr2, [sp, #12]\n+\tstr\tr2, [sp, #8]\n \tldr.w\tr2, [r3, #176]\t@ 0xb0\n-\tstr\tr2, [sp, #20]\n-\tldr.w\tr2, [r3, #368]\t@ 0x170\n-\tldr.w\tr3, [r3, #372]\t@ 0x174\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tsub.w\tr3, sl, r8\n+\tstr\tr2, [sp, #16]\n+\tldr.w\tr2, [r3, #352]\t@ 0x160\n+\tldr.w\tr3, [r3, #356]\t@ 0x164\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tsub.w\tr3, r1, r8\n \tstr\tr2, [sp, #36]\t@ 0x24\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tb.n\t13be <__gridxc_mesh1d_MOD_set_mesh+0xbb6>\n-\tldr\tr3, [sp, #244]\t@ 0xf4\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tb.n\t1416 <__gridxc_mesh1d_MOD_set_mesh+0xc0e>\n+\tldr\tr3, [sp, #284]\t@ 0x11c\n \tcmp\tr3, #0\n-\tbeq.w\t1ac0 <__gridxc_mesh1d_MOD_set_mesh+0x12b8>\n+\tbeq.w\t1b28 <__gridxc_mesh1d_MOD_set_mesh+0x1320>\n \tvldr\td0, [r3]\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d0, d9\n-\tb.n\t1726 <__gridxc_mesh1d_MOD_set_mesh+0xf1e>\n+\tvdiv.f64\td7, d0, d8\n+\tb.n\t178c <__gridxc_mesh1d_MOD_set_mesh+0xf84>\n \tldr\tr2, [r5, #4]\n \tmovw\tr3, #26994\t@ 0x6972\n \tmovt\tr3, #26740\t@ 0x6874\n \tadds\tr5, #4\n \tcmp\tr2, r3\n-\tbne.w\t154a <__gridxc_mesh1d_MOD_set_mesh+0xd42>\n+\tbne.w\t15b0 <__gridxc_mesh1d_MOD_set_mesh+0xda8>\n \tldrh.w\tr2, [r5, #4]!\n \tmovw\tr3, #26989\t@ 0x696d\n \tcmp\tr2, r3\n-\tbne.w\t154a <__gridxc_mesh1d_MOD_set_mesh+0xd42>\n+\tbne.w\t15b0 <__gridxc_mesh1d_MOD_set_mesh+0xda8>\n \tldrb\tr3, [r5, #2]\n \tcmp\tr3, #99\t@ 0x63\n-\tbne.w\t154a <__gridxc_mesh1d_MOD_set_mesh+0xd42>\n-\tldr\tr5, [pc, #564]\t@ (1aa8 <__gridxc_mesh1d_MOD_set_mesh+0x12a0>)\n+\tbne.w\t15b0 <__gridxc_mesh1d_MOD_set_mesh+0xda8>\n+\tldr\tr5, [pc, #564]\t@ (1b10 <__gridxc_mesh1d_MOD_set_mesh+0x1308>)\n \tadd\tr5, pc\n \tldr\tr3, [r5, #100]\t@ 0x64\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [r5, #104]\t@ 0x68\n-\tstr\tr3, [sp, #16]\n-\tvldr\td10, [r5, #56]\t@ 0x38\n+\tvldr\td9, [r5, #56]\t@ 0x38\n \tldr.w\tr3, [r5, #136]\t@ 0x88\n-\tstr\tr3, [sp, #8]\n+\tstr\tr3, [sp, #12]\n \tldr.w\tr3, [r5, #140]\t@ 0x8c\n-\tvmov.f64\td0, d10\n-\tstr\tr3, [sp, #24]\n+\tvmov.f64\td0, d9\n+\tstr\tr3, [sp, #20]\n \tldr.w\tr3, [r5, #172]\t@ 0xac\n-\tstr\tr3, [sp, #12]\n+\tstr\tr3, [sp, #8]\n \tldr.w\tr3, [r5, #176]\t@ 0xb0\n-\tstr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tldr.w\tr8, [r5, #164]\t@ 0xa4\n-\tvmov.f64\td11, d0\n+\tvmov.f64\td10, d0\n \tldr.w\tr3, [r5, #200]\t@ 0xc8\n-\tldr.w\tsl, [r5, #128]\t@ 0x80\n+\tldr.w\tr2, [r5, #128]\t@ 0x80\n \tsub.w\tr3, r3, r8\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tldr.w\tr3, [r5, #396]\t@ 0x18c\n-\tvldr\td9, [r5, #48]\t@ 0x30\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr.w\tr3, [r5, #380]\t@ 0x17c\n+\tldr.w\tr9, [r5, #104]\t@ 0x68\n \tsub.w\tr3, r3, r8\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr3, [r5, #276]\t@ 0x114\n-\tsub.w\tr3, r3, sl\n \tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr.w\tr3, [r5, #272]\t@ 0x110\n+\tvldr\td8, [r5, #48]\t@ 0x30\n+\tsubs\tr3, r3, r2\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tldr.w\tr3, [r5, #168]\t@ 0xa8\n \tstr\tr3, [sp, #28]\n-\tldr.w\tr3, [r5, #368]\t@ 0x170\n+\tldr.w\tr3, [r5, #352]\t@ 0x160\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tldr.w\tr3, [r5, #372]\t@ 0x174\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tr3, [r5, #356]\t@ 0x164\n+\tstr\tr3, [sp, #68]\t@ 0x44\n \tldr.w\tr3, [r5, #132]\t@ 0x84\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr3, [r5, #248]\t@ 0xf8\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tr3, [r5, #244]\t@ 0xf4\n \tstr\tr3, [sp, #32]\n-\tldr.w\tr3, [r5, #252]\t@ 0xfc\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tsub.w\tr3, sl, r8\n+\tldr.w\tr3, [r5, #248]\t@ 0xf8\n \tstr\tr3, [sp, #80]\t@ 0x50\n+\tsub.w\tr3, r2, r8\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #0]\n \tcmp\tr4, #0\n-\tble.w\t13be <__gridxc_mesh1d_MOD_set_mesh+0xbb6>\n-\tldr\tr3, [sp, #16]\n-\tvmul.f64\td21, d10, d10\n-\tldr\tr0, [pc, #420]\t@ (1aac <__gridxc_mesh1d_MOD_set_mesh+0x12a4>)\n-\tvsub.f64\td24, d8, d9\n-\tadds\tr6, r3, #1\n+\tble.w\t1416 <__gridxc_mesh1d_MOD_set_mesh+0xc0e>\n \tldr\tr3, [sp, #4]\n-\tadd\tr0, pc\n+\tadd.w\tr6, r9, #1\n+\tldr\tr0, [pc, #420]\t@ (1b14 <__gridxc_mesh1d_MOD_set_mesh+0x130c>)\n+\tvmul.f64\td3, d9, d9\n+\tvsub.f64\td0, d14, d8\n \tadds\tr7, r4, #1\n-\tvmul.f64\td23, d21, d10\n-\tvmul.f64\td22, d21, d21\n \tadd.w\tr6, r3, r6, lsl #3\n-\tldr\tr3, [sp, #24]\n-\tldr\tr1, [r0, #4]\n+\tldr\tr3, [sp, #20]\n+\tadd\tr0, pc\n \tadds\tr5, r3, #1\n-\tldr\tr3, [sp, #8]\n-\tldr\tr2, [r0, #8]\n+\tldr\tr3, [sp, #12]\n+\tvmul.f64\td1, d3, d9\n+\tvmul.f64\td2, d3, d3\n+\tldr\tr1, [r0, #4]\n \tadd.w\tr5, r3, r5, lsl #3\n \tldr.w\tr3, [r0, #212]\t@ 0xd4\n+\tldr\tr2, [r0, #8]\n \tldr.w\tr0, [r0, #208]\t@ 0xd0\n-\tadds\tr2, #1\n \tadds\tr3, #1\n-\tadd.w\tr2, r1, r2, lsl #3\n+\tadds\tr2, #1\n \tadd.w\tr0, r0, r3, lsl #3\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #16]\n+\tadd.w\tr2, r1, r2, lsl #3\n \tadds\tr1, r3, #1\n-\tldr\tr3, [sp, #12]\n+\tldr\tr3, [sp, #8]\n \tadd.w\tr1, r3, r1, lsl #3\n \tmovs\tr3, #1\n-\tvadd.f64\td20, d9, d24\n-\tvmul.f64\td19, d9, d10\n-\tvmul.f64\td18, d21, d9\n-\tvmul.f64\td17, d9, d23\n-\tvmul.f64\td16, d22, d9\n+\tvmul.f64\td7, d8, d9\n+\tvadd.f64\td4, d8, d0\n+\tvmul.f64\td5, d3, d8\n+\tvmul.f64\td6, d8, d1\n \tadds\tr3, #1\n-\tvmul.f64\td9, d9, d11\n \tcmp\tr7, r3\n-\tvstmia\tr2!, {d20}\n-\tvstmia\tr6!, {d19}\n-\tvstmia\tr5!, {d18}\n-\tvstmia\tr1!, {d17}\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t194e <__gridxc_mesh1d_MOD_set_mesh+0x1146>\n-\tb.n\t13be <__gridxc_mesh1d_MOD_set_mesh+0xbb6>\n-\tldr\tr2, [r6, #4]\n+\tvstmia\tr6!, {d7}\n+\tvmul.f64\td7, d2, d8\n+\tvstmia\tr2!, {d4}\n+\tvmul.f64\td8, d8, d10\n+\tvstmia\tr5!, {d5}\n+\tvstmia\tr1!, {d6}\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t19b6 <__gridxc_mesh1d_MOD_set_mesh+0x11ae>\n+\tb.n\t1416 <__gridxc_mesh1d_MOD_set_mesh+0xc0e>\n+\tldr\tr2, [r5, #4]\n \tmovw\tr3, #26994\t@ 0x6972\n \tmovt\tr3, #26740\t@ 0x6874\n-\tadds\tr1, r6, #4\n+\tadds\tr1, r5, #4\n \tcmp\tr2, r3\n-\tbne.w\t1688 <__gridxc_mesh1d_MOD_set_mesh+0xe80>\n+\tbne.w\t16f2 <__gridxc_mesh1d_MOD_set_mesh+0xeea>\n \tldrh.w\tr2, [r1, #4]!\n \tmovw\tr3, #26989\t@ 0x696d\n \tcmp\tr2, r3\n-\tbne.w\t1688 <__gridxc_mesh1d_MOD_set_mesh+0xe80>\n+\tbne.w\t16f2 <__gridxc_mesh1d_MOD_set_mesh+0xeea>\n \tldrb\tr3, [r1, #2]\n \tcmp\tr3, #99\t@ 0x63\n-\tbne.w\t1688 <__gridxc_mesh1d_MOD_set_mesh+0xe80>\n-\tvmov.f64\td0, d10\n+\tbne.w\t16f2 <__gridxc_mesh1d_MOD_set_mesh+0xeea>\n+\tvmov.f64\td0, d9\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #72]\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tldr\tr3, [pc, #248]\t@ (1ab0 <__gridxc_mesh1d_MOD_set_mesh+0x12a8>)\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td11, d0\n-\tcmp\tr4, #1\n-\tadd\tr3, pc\n-\tvsub.f64\td19, d0, d21\n-\tvldr\td9, [r3, #48]\t@ 0x30\n-\tvmul.f64\td19, d19, d9\n-\tble.w\t1b30 <__gridxc_mesh1d_MOD_set_mesh+0x1328>\n-\tvmov.f64\td18, d8\n-\tvldr\td20, [pc, #124]\t@ 1a58 <__gridxc_mesh1d_MOD_set_mesh+0x1250>\n-\tadd.w\tr2, r9, #8\n+\tldr\tr3, [pc, #248]\t@ (1b18 <__gridxc_mesh1d_MOD_set_mesh+0x1310>)\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td10, d0\n+\tadd\tr3, pc\n+\tvsub.f64\td5, d0, d4\n+\tvldr\td8, [r3, #48]\t@ 0x30\n+\tldr\tr3, [sp, #0]\n+\tvmul.f64\td5, d5, d8\n+\tcmp\tr3, #1\n+\tble.w\t1b96 <__gridxc_mesh1d_MOD_set_mesh+0x138e>\n+\tmov\tr1, r3\n+\tvmov.f64\td3, d14\n+\tvldr\td2, [pc, #128]\t@ 1ac8 <__gridxc_mesh1d_MOD_set_mesh+0x12c0>\n+\tadd.w\tr2, sl, #8\n \tmovs\tr3, #2\n-\tb.n\t19f0 <__gridxc_mesh1d_MOD_set_mesh+0x11e8>\n+\tb.n\t1a5c <__gridxc_mesh1d_MOD_set_mesh+0x1254>\n \tadds\tr3, #1\n-\tvmul.f64\td19, d19, d11\n-\tcmp\tr4, r3\n-\tblt.w\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tvmov.f64\td17, d18\n-\tvldmia\tr2!, {d18}\n-\tvsub.f64\td17, d18, d17\n-\tvdiv.f64\td16, d17, d19\n-\tvsub.f64\td16, d16, d21\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d20\n+\tvmul.f64\td5, d5, d10\n+\tcmp\tr1, r3\n+\tblt.w\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tvmov.f64\td6, d3\n+\tvldmia\tr2!, {d3}\n+\tvsub.f64\td6, d3, d6\n+\tvdiv.f64\td7, d6, d5\n+\tvsub.f64\td7, d7, d4\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d2\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t19e4 <__gridxc_mesh1d_MOD_set_mesh+0x11dc>\n-\tldr\tr5, [pc, #160]\t@ (1ab4 <__gridxc_mesh1d_MOD_set_mesh+0x12ac>)\n-\tldr\tr2, [pc, #160]\t@ (1ab8 <__gridxc_mesh1d_MOD_set_mesh+0x12b0>)\n+\tble.n\t1a50 <__gridxc_mesh1d_MOD_set_mesh+0x1248>\n+\tldr\tr5, [pc, #156]\t@ (1b1c <__gridxc_mesh1d_MOD_set_mesh+0x1314>)\n+\tldr\tr2, [pc, #156]\t@ (1b20 <__gridxc_mesh1d_MOD_set_mesh+0x1318>)\n \tadd\tr5, pc\n \tadd\tr2, pc\n-\tb.w\tddc <__gridxc_mesh1d_MOD_set_mesh+0x5d4>\n-\tldr\tr3, [pc, #124]\t@ (1a9c <__gridxc_mesh1d_MOD_set_mesh+0x1294>)\n+\tb.w\te1c <__gridxc_mesh1d_MOD_set_mesh+0x614>\n+\tldr\tr3, [pc, #120]\t@ (1b04 <__gridxc_mesh1d_MOD_set_mesh+0x12fc>)\n \tmovs\tr1, #24\n-\tldr\tr2, [sp, #16]\n-\tldr\tr0, [pc, #148]\t@ (1abc <__gridxc_mesh1d_MOD_set_mesh+0x12b4>)\n-\tldr\tr3, [r2, r3]\n+\tldr\tr0, [pc, #148]\t@ (1b24 <__gridxc_mesh1d_MOD_set_mesh+0x131c>)\n \tadd\tr0, pc\n+\tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.w\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tvmov.i64\td8, #0x0000000000000000\n-\tb.n\t1708 <__gridxc_mesh1d_MOD_set_mesh+0xf00>\n-\tadd.w\tr3, r9, r1, lsl #3\n-\tvldr\td17, [r9]\n-\tmov\tr4, r1\n-\tvldr\td18, [r3, #-8]\n-\tvsub.f64\td18, d18, d17\n-\tb.w\t8b0 <__gridxc_mesh1d_MOD_set_mesh+0xa8>\n+\tb.w\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tvldr\td14, [pc, #48]\t@ 1ad0 <__gridxc_mesh1d_MOD_set_mesh+0x12c8>\n+\tb.n\t176c <__gridxc_mesh1d_MOD_set_mesh+0xf64>\n+\tadd.w\tr3, sl, r1, lsl #3\n+\tvldr\td6, [sl]\n+\tstr\tr1, [sp, #0]\n+\tvldr\td5, [r3, #-8]\n+\tvsub.f64\td5, d5, d6\n+\tb.w\t8b4 <__gridxc_mesh1d_MOD_set_mesh+0xac>\n \tnop\n+\tnop.w\n \t.word\t0xa0b5ed8d\n \t.word\t0x3eb0c6f7\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000068a\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000636\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000606\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000560\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000516\n- R_ARM_REL32\t.LC1\n+\t...\n \t.word\t0x00000518\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x0000051a\n R_ARM_REL32\t.data\n-\t.word\t0x0000050a\n+\t.word\t0x0000050e\n R_ARM_REL32\t.bss\n-\t.word\t0x00000410\n+\t.word\t0x0000040e\n R_ARM_REL32\t.bss\n-\t.word\t0x000003ec\n+\t.word\t0x000003ea\n R_ARM_REL32\t.LC4\n-\t.word\t0x000003ee\n+\t.word\t0x000003ec\n R_ARM_REL32\t.data\n-\t.word\t0x00000354\n+\t.word\t0x00000356\n R_ARM_REL32\t.bss\n-\t.word\t0x00000342\n- R_ARM_REL32\t.LC2\n \t.word\t0x00000344\n- R_ARM_REL32\t.data\n-\t.word\t0x0000030c\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x00000346\n R_ARM_REL32\t.data\n \t.word\t0x0000030e\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000310\n R_ARM_REL32\t.LC1\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000002e4\n+\t.word\t0x000002ea\n R_ARM_REL32\t.LC36\n-\t.word\t0x000002e0\n+\t.word\t0x000002e2\n R_ARM_REL32\t.bss\n-\t.word\t0x00000230\n+\t.word\t0x00000232\n R_ARM_REL32\t.bss\n-\t.word\t0x00000198\n+\t.word\t0x00000190\n R_ARM_REL32\t.bss\n-\t.word\t0x000000ea\n+\t.word\t0x000000ec\n R_ARM_REL32\t.bss\n-\t.word\t0x0000009a\n+\t.word\t0x00000096\n R_ARM_REL32\t.data\n-\t.word\t0x0000009c\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC4\n \t.word\t0x00000090\n R_ARM_REL32\t.LC35\n-\tldr\tr3, [pc, #724]\t@ (1d98 <__gridxc_mesh1d_MOD_set_mesh+0x1590>)\n+\tldr\tr3, [pc, #660]\t@ (1dc0 <__gridxc_mesh1d_MOD_set_mesh+0x15b8>)\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tadd\tr3, pc\n \tstrd\tr0, r1, [r3, #56]\t@ 0x38\n \tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr2, [pc, #716]\t@ (1d9c <__gridxc_mesh1d_MOD_set_mesh+0x1594>)\n-\tldr\tr1, [pc, #716]\t@ (1da0 <__gridxc_mesh1d_MOD_set_mesh+0x1598>)\n+\tldr\tr2, [pc, #652]\t@ (1dc4 <__gridxc_mesh1d_MOD_set_mesh+0x15bc>)\n+\tldr\tr1, [pc, #652]\t@ (1dc8 <__gridxc_mesh1d_MOD_set_mesh+0x15c0>)\n \tadd\tr2, pc\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadd\tr1, pc\n-\tldr\tr3, [pc, #712]\t@ (1da4 <__gridxc_mesh1d_MOD_set_mesh+0x159c>)\n-\tvsub.f64\td16, d16, d8\n+\tldr\tr3, [pc, #648]\t@ (1dcc <__gridxc_mesh1d_MOD_set_mesh+0x15c4>)\n+\tvsub.f64\td7, d7, d14\n \tadd\tr3, pc\n-\tvdiv.f64\td17, d16, d9\n-\tvstr\td17, [r1, #40]\t@ 0x28\n+\tvdiv.f64\td6, d7, d8\n+\tvstr\td6, [r1, #40]\t@ 0x28\n \tldmia.w\tr2, {r0, r1}\n \tstrh\tr1, [r3, #4]\n \tmov.w\tr2, #538976288\t@ 0x20202020\n \tstr\tr0, [r3, #0]\n \tstr.w\tr2, [r3, #7]\n \tlsrs\tr1, r1, #16\n \tstrb\tr1, [r3, #6]\n-\tb.w\tdec <__gridxc_mesh1d_MOD_set_mesh+0x5e4>\n-\tmovs\tr3, #3\n-\tb.w\t10f6 <__gridxc_mesh1d_MOD_set_mesh+0x8ee>\n-\tldr\tr3, [pc, #668]\t@ (1da8 <__gridxc_mesh1d_MOD_set_mesh+0x15a0>)\n+\tb.w\te2c <__gridxc_mesh1d_MOD_set_mesh+0x624>\n+\tmovs\tr2, #3\n+\tb.w\t114e <__gridxc_mesh1d_MOD_set_mesh+0x946>\n+\tldr\tr3, [pc, #604]\t@ (1dd0 <__gridxc_mesh1d_MOD_set_mesh+0x15c8>)\n \tadd\tr3, pc\n \tldr\tr2, [r3, #0]\n \tcmp\tr2, #0\n-\tbne.w\t8f8 <__gridxc_mesh1d_MOD_set_mesh+0xf0>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tbne.w\t8fe <__gridxc_mesh1d_MOD_set_mesh+0xf6>\n+\tstrd\tr2, r2, [r3, #76]\t@ 0x4c\n \tmovs\tr2, #8\n \tstr\tr2, [r3, #72]\t@ 0x48\n \tmovw\tr2, #769\t@ 0x301\n-\tvstr\td16, [r3, #76]\t@ 0x4c\n \tstrh.w\tr2, [r3, #80]\t@ 0x50\n-\tbic.w\tr3, r4, r4, asr #31\n-\tb.w\t9d2 <__gridxc_mesh1d_MOD_set_mesh+0x1ca>\n-\tldr\tr3, [pc, #632]\t@ (1dac <__gridxc_mesh1d_MOD_set_mesh+0x15a4>)\n-\tmov\tr1, r6\n+\tldr\tr3, [sp, #0]\n+\tbic.w\tr2, r3, r3, asr #31\n+\tb.w\t9dc <__gridxc_mesh1d_MOD_set_mesh+0x1d4>\n+\tldr\tr3, [pc, #572]\t@ (1dd4 <__gridxc_mesh1d_MOD_set_mesh+0x15cc>)\n+\tmov\tr1, r5\n \tmovs\tr2, #9\n \tmovs\tr0, #11\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tmov\tr3, r0\n \tstr\tr0, [sp, #92]\t@ 0x5c\n-\tcbz\tr0, 1b66 <__gridxc_mesh1d_MOD_set_mesh+0x135e>\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tmov.w\tsl, #1\n+\tcbz\tr0, 1bcc <__gridxc_mesh1d_MOD_set_mesh+0x13c4>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmov\tr8, sl\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tstrd\tr2, r2, [sp, #76]\t@ 0x4c\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr4, [sp, #28]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tstrd\tr3, r3, [sp, #20]\n-\tstr\tr3, [sp, #16]\n-\tb.n\t18fa <__gridxc_mesh1d_MOD_set_mesh+0x10f2>\n-\tmov\tr1, r3\n-\tmov.w\tsl, #1\n-\tldr\tr6, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #0]\n+\tmovs\tr1, #1\n+\tmov\tr8, r1\n+\tmov\tr9, r3\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tstrd\tr2, r2, [sp, #84]\t@ 0x54\n+\tstr\tr0, [sp, #60]\t@ 0x3c\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr0, [sp, #28]\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tstrd\tr3, r3, [sp, #16]\n+\tb.n\t1960 <__gridxc_mesh1d_MOD_set_mesh+0x1158>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmovs\tr2, #2\n-\tmov\tip, r1\n-\tmov\tr8, sl\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tstr\tr2, [sp, #108]\t@ 0x6c\n-\tstrd\tr1, r1, [sp, #76]\t@ 0x4c\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr4, [sp, #28]\n-\tstr.w\tfp, [sp, #164]\t@ 0xa4\n-\tstrd\tfp, r6, [sp, #156]\t@ 0x9c\n-\tstrd\tfp, r6, [sp, #148]\t@ 0x94\n-\tstrd\tfp, r6, [sp, #140]\t@ 0x8c\n-\tstr\tr1, [sp, #132]\t@ 0x84\n-\tstr\tr1, [sp, #124]\t@ 0x7c\n-\tstr\tr1, [sp, #116]\t@ 0x74\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tstr.w\tsl, [sp, #136]\t@ 0x88\n-\tstr.w\tsl, [sp, #128]\t@ 0x80\n-\tstr.w\tsl, [sp, #120]\t@ 0x78\n-\tstr.w\tsl, [sp, #112]\t@ 0x70\n-\tstrd\tr2, r2, [sp, #100]\t@ 0x64\n-\tstr\tr2, [sp, #96]\t@ 0x60\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tstrd\tr3, r3, [sp, #20]\n-\tstr\tr3, [sp, #16]\n-\tb.w\tef0 <__gridxc_mesh1d_MOD_set_mesh+0x6e8>\n-\tldr\tr1, [pc, #492]\t@ (1db0 <__gridxc_mesh1d_MOD_set_mesh+0x15a8>)\n-\tldr\tr0, [pc, #492]\t@ (1db4 <__gridxc_mesh1d_MOD_set_mesh+0x15ac>)\n-\tldr\tr2, [sp, #20]\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tmov\tr1, r3\n+\tmovs\tr3, #1\n+\tldr\tr2, [sp, #0]\n+\tmov\tr5, r3\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tmovs\tr4, #2\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tstrd\tr3, r3, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tb.n\t1724 <__gridxc_mesh1d_MOD_set_mesh+0xf1c>\n+\tldr\tr1, [pc, #492]\t@ (1dd8 <__gridxc_mesh1d_MOD_set_mesh+0x15d0>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #492]\t@ (1ddc <__gridxc_mesh1d_MOD_set_mesh+0x15d4>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #484]\t@ (1db8 <__gridxc_mesh1d_MOD_set_mesh+0x15b0>)\n-\tldr\tr1, [pc, #488]\t@ (1dbc <__gridxc_mesh1d_MOD_set_mesh+0x15b4>)\n-\tldr\tr0, [pc, #488]\t@ (1dc0 <__gridxc_mesh1d_MOD_set_mesh+0x15b8>)\n+\tldr\tr2, [pc, #484]\t@ (1de0 <__gridxc_mesh1d_MOD_set_mesh+0x15d8>)\n+\tldr\tr1, [pc, #488]\t@ (1de4 <__gridxc_mesh1d_MOD_set_mesh+0x15dc>)\n+\tldr\tr0, [pc, #488]\t@ (1de8 <__gridxc_mesh1d_MOD_set_mesh+0x15e0>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #480]\t@ (1dc4 <__gridxc_mesh1d_MOD_set_mesh+0x15bc>)\n-\tldr\tr1, [pc, #484]\t@ (1dc8 <__gridxc_mesh1d_MOD_set_mesh+0x15c0>)\n-\tldr\tr0, [pc, #484]\t@ (1dcc <__gridxc_mesh1d_MOD_set_mesh+0x15c4>)\n+\tldr\tr2, [pc, #480]\t@ (1dec <__gridxc_mesh1d_MOD_set_mesh+0x15e4>)\n+\tldr\tr1, [pc, #484]\t@ (1df0 <__gridxc_mesh1d_MOD_set_mesh+0x15e8>)\n+\tldr\tr0, [pc, #484]\t@ (1df4 <__gridxc_mesh1d_MOD_set_mesh+0x15ec>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #476]\t@ (1dd0 <__gridxc_mesh1d_MOD_set_mesh+0x15c8>)\n-\tldr\tr0, [pc, #480]\t@ (1dd4 <__gridxc_mesh1d_MOD_set_mesh+0x15cc>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #476]\t@ (1df8 <__gridxc_mesh1d_MOD_set_mesh+0x15f0>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #476]\t@ (1dfc <__gridxc_mesh1d_MOD_set_mesh+0x15f4>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #472]\t@ (1dd8 <__gridxc_mesh1d_MOD_set_mesh+0x15d0>)\n-\tldr\tr1, [pc, #472]\t@ (1ddc <__gridxc_mesh1d_MOD_set_mesh+0x15d4>)\n-\tldr\tr0, [pc, #476]\t@ (1de0 <__gridxc_mesh1d_MOD_set_mesh+0x15d8>)\n+\tldr\tr2, [pc, #472]\t@ (1e00 <__gridxc_mesh1d_MOD_set_mesh+0x15f8>)\n+\tldr\tr1, [pc, #472]\t@ (1e04 <__gridxc_mesh1d_MOD_set_mesh+0x15fc>)\n+\tldr\tr0, [pc, #476]\t@ (1e08 <__gridxc_mesh1d_MOD_set_mesh+0x1600>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #468]\t@ (1de4 <__gridxc_mesh1d_MOD_set_mesh+0x15dc>)\n-\tldr\tr0, [pc, #468]\t@ (1de8 <__gridxc_mesh1d_MOD_set_mesh+0x15e0>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #468]\t@ (1e0c <__gridxc_mesh1d_MOD_set_mesh+0x1604>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #468]\t@ (1e10 <__gridxc_mesh1d_MOD_set_mesh+0x1608>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #460]\t@ (1dec <__gridxc_mesh1d_MOD_set_mesh+0x15e4>)\n-\tldr\tr1, [pc, #464]\t@ (1df0 <__gridxc_mesh1d_MOD_set_mesh+0x15e8>)\n-\tldr\tr0, [pc, #464]\t@ (1df4 <__gridxc_mesh1d_MOD_set_mesh+0x15ec>)\n+\tldr\tr2, [pc, #460]\t@ (1e14 <__gridxc_mesh1d_MOD_set_mesh+0x160c>)\n+\tldr\tr1, [pc, #464]\t@ (1e18 <__gridxc_mesh1d_MOD_set_mesh+0x1610>)\n+\tldr\tr0, [pc, #464]\t@ (1e1c <__gridxc_mesh1d_MOD_set_mesh+0x1614>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #456]\t@ (1df8 <__gridxc_mesh1d_MOD_set_mesh+0x15f0>)\n-\tldr\tr0, [pc, #460]\t@ (1dfc <__gridxc_mesh1d_MOD_set_mesh+0x15f4>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #456]\t@ (1e20 <__gridxc_mesh1d_MOD_set_mesh+0x1618>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #456]\t@ (1e24 <__gridxc_mesh1d_MOD_set_mesh+0x161c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #452]\t@ (1e00 <__gridxc_mesh1d_MOD_set_mesh+0x15f8>)\n-\tldr\tr1, [pc, #452]\t@ (1e04 <__gridxc_mesh1d_MOD_set_mesh+0x15fc>)\n-\tldr\tr0, [pc, #456]\t@ (1e08 <__gridxc_mesh1d_MOD_set_mesh+0x1600>)\n+\tldr\tr2, [pc, #452]\t@ (1e28 <__gridxc_mesh1d_MOD_set_mesh+0x1620>)\n+\tldr\tr1, [pc, #452]\t@ (1e2c <__gridxc_mesh1d_MOD_set_mesh+0x1624>)\n+\tldr\tr0, [pc, #456]\t@ (1e30 <__gridxc_mesh1d_MOD_set_mesh+0x1628>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #448]\t@ (1e0c <__gridxc_mesh1d_MOD_set_mesh+0x1604>)\n-\tldr\tr0, [pc, #448]\t@ (1e10 <__gridxc_mesh1d_MOD_set_mesh+0x1608>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #448]\t@ (1e34 <__gridxc_mesh1d_MOD_set_mesh+0x162c>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #448]\t@ (1e38 <__gridxc_mesh1d_MOD_set_mesh+0x1630>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #440]\t@ (1e14 <__gridxc_mesh1d_MOD_set_mesh+0x160c>)\n-\tldr\tr1, [pc, #444]\t@ (1e18 <__gridxc_mesh1d_MOD_set_mesh+0x1610>)\n-\tldr\tr0, [pc, #444]\t@ (1e1c <__gridxc_mesh1d_MOD_set_mesh+0x1614>)\n+\tldr\tr2, [pc, #440]\t@ (1e3c <__gridxc_mesh1d_MOD_set_mesh+0x1634>)\n+\tldr\tr1, [pc, #444]\t@ (1e40 <__gridxc_mesh1d_MOD_set_mesh+0x1638>)\n+\tldr\tr0, [pc, #444]\t@ (1e44 <__gridxc_mesh1d_MOD_set_mesh+0x163c>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #436]\t@ (1e20 <__gridxc_mesh1d_MOD_set_mesh+0x1618>)\n-\tldr\tr0, [pc, #440]\t@ (1e24 <__gridxc_mesh1d_MOD_set_mesh+0x161c>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #436]\t@ (1e48 <__gridxc_mesh1d_MOD_set_mesh+0x1640>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #436]\t@ (1e4c <__gridxc_mesh1d_MOD_set_mesh+0x1644>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #432]\t@ (1e28 <__gridxc_mesh1d_MOD_set_mesh+0x1620>)\n-\tldr\tr1, [pc, #432]\t@ (1e2c <__gridxc_mesh1d_MOD_set_mesh+0x1624>)\n-\tldr\tr0, [pc, #436]\t@ (1e30 <__gridxc_mesh1d_MOD_set_mesh+0x1628>)\n+\tldr\tr2, [pc, #432]\t@ (1e50 <__gridxc_mesh1d_MOD_set_mesh+0x1648>)\n+\tldr\tr1, [pc, #432]\t@ (1e54 <__gridxc_mesh1d_MOD_set_mesh+0x164c>)\n+\tldr\tr0, [pc, #436]\t@ (1e58 <__gridxc_mesh1d_MOD_set_mesh+0x1650>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #428]\t@ (1e34 <__gridxc_mesh1d_MOD_set_mesh+0x162c>)\n-\tldr\tr0, [pc, #428]\t@ (1e38 <__gridxc_mesh1d_MOD_set_mesh+0x1630>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #428]\t@ (1e5c <__gridxc_mesh1d_MOD_set_mesh+0x1654>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #428]\t@ (1e60 <__gridxc_mesh1d_MOD_set_mesh+0x1658>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #420]\t@ (1e3c <__gridxc_mesh1d_MOD_set_mesh+0x1634>)\n-\tldr\tr1, [pc, #424]\t@ (1e40 <__gridxc_mesh1d_MOD_set_mesh+0x1638>)\n-\tldr\tr0, [pc, #424]\t@ (1e44 <__gridxc_mesh1d_MOD_set_mesh+0x163c>)\n+\tldr\tr2, [pc, #420]\t@ (1e64 <__gridxc_mesh1d_MOD_set_mesh+0x165c>)\n+\tldr\tr1, [pc, #424]\t@ (1e68 <__gridxc_mesh1d_MOD_set_mesh+0x1660>)\n+\tldr\tr0, [pc, #424]\t@ (1e6c <__gridxc_mesh1d_MOD_set_mesh+0x1664>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #416]\t@ (1e48 <__gridxc_mesh1d_MOD_set_mesh+0x1640>)\n-\tldr\tr1, [pc, #420]\t@ (1e4c <__gridxc_mesh1d_MOD_set_mesh+0x1644>)\n-\tldr\tr0, [pc, #420]\t@ (1e50 <__gridxc_mesh1d_MOD_set_mesh+0x1648>)\n+\tldr\tr2, [pc, #416]\t@ (1e70 <__gridxc_mesh1d_MOD_set_mesh+0x1668>)\n+\tldr\tr1, [pc, #420]\t@ (1e74 <__gridxc_mesh1d_MOD_set_mesh+0x166c>)\n+\tldr\tr0, [pc, #420]\t@ (1e78 <__gridxc_mesh1d_MOD_set_mesh+0x1670>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #412]\t@ (1e54 <__gridxc_mesh1d_MOD_set_mesh+0x164c>)\n-\tldr\tr1, [pc, #416]\t@ (1e58 <__gridxc_mesh1d_MOD_set_mesh+0x1650>)\n-\tldr\tr0, [pc, #416]\t@ (1e5c <__gridxc_mesh1d_MOD_set_mesh+0x1654>)\n+\tldr\tr2, [pc, #412]\t@ (1e7c <__gridxc_mesh1d_MOD_set_mesh+0x1674>)\n+\tldr\tr1, [pc, #416]\t@ (1e80 <__gridxc_mesh1d_MOD_set_mesh+0x1678>)\n+\tldr\tr0, [pc, #416]\t@ (1e84 <__gridxc_mesh1d_MOD_set_mesh+0x167c>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #408]\t@ (1e60 <__gridxc_mesh1d_MOD_set_mesh+0x1658>)\n-\tldr\tr1, [pc, #412]\t@ (1e64 <__gridxc_mesh1d_MOD_set_mesh+0x165c>)\n-\tldr\tr0, [pc, #412]\t@ (1e68 <__gridxc_mesh1d_MOD_set_mesh+0x1660>)\n+\tldr\tr2, [pc, #408]\t@ (1e88 <__gridxc_mesh1d_MOD_set_mesh+0x1680>)\n+\tldr\tr1, [pc, #412]\t@ (1e8c <__gridxc_mesh1d_MOD_set_mesh+0x1684>)\n+\tldr\tr0, [pc, #412]\t@ (1e90 <__gridxc_mesh1d_MOD_set_mesh+0x1688>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #404]\t@ (1e6c <__gridxc_mesh1d_MOD_set_mesh+0x1664>)\n-\tldr\tr1, [pc, #408]\t@ (1e70 <__gridxc_mesh1d_MOD_set_mesh+0x1668>)\n-\tldr\tr0, [pc, #408]\t@ (1e74 <__gridxc_mesh1d_MOD_set_mesh+0x166c>)\n+\tldr\tr2, [pc, #404]\t@ (1e94 <__gridxc_mesh1d_MOD_set_mesh+0x168c>)\n+\tldr\tr1, [pc, #408]\t@ (1e98 <__gridxc_mesh1d_MOD_set_mesh+0x1690>)\n+\tldr\tr0, [pc, #408]\t@ (1e9c <__gridxc_mesh1d_MOD_set_mesh+0x1694>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #400]\t@ (1e78 <__gridxc_mesh1d_MOD_set_mesh+0x1670>)\n-\tldr\tr1, [pc, #404]\t@ (1e7c <__gridxc_mesh1d_MOD_set_mesh+0x1674>)\n-\tldr\tr0, [pc, #404]\t@ (1e80 <__gridxc_mesh1d_MOD_set_mesh+0x1678>)\n+\tldr\tr2, [pc, #400]\t@ (1ea0 <__gridxc_mesh1d_MOD_set_mesh+0x1698>)\n+\tldr\tr1, [pc, #404]\t@ (1ea4 <__gridxc_mesh1d_MOD_set_mesh+0x169c>)\n+\tldr\tr0, [pc, #404]\t@ (1ea8 <__gridxc_mesh1d_MOD_set_mesh+0x16a0>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #396]\t@ (1e84 <__gridxc_mesh1d_MOD_set_mesh+0x167c>)\n-\tldr\tr1, [pc, #400]\t@ (1e88 <__gridxc_mesh1d_MOD_set_mesh+0x1680>)\n-\tldr\tr0, [pc, #400]\t@ (1e8c <__gridxc_mesh1d_MOD_set_mesh+0x1684>)\n+\tldr\tr2, [pc, #396]\t@ (1eac <__gridxc_mesh1d_MOD_set_mesh+0x16a4>)\n+\tldr\tr1, [pc, #400]\t@ (1eb0 <__gridxc_mesh1d_MOD_set_mesh+0x16a8>)\n+\tldr\tr0, [pc, #400]\t@ (1eb4 <__gridxc_mesh1d_MOD_set_mesh+0x16ac>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #392]\t@ (1e90 <__gridxc_mesh1d_MOD_set_mesh+0x1688>)\n-\tldr\tr1, [pc, #396]\t@ (1e94 <__gridxc_mesh1d_MOD_set_mesh+0x168c>)\n-\tldr\tr0, [pc, #396]\t@ (1e98 <__gridxc_mesh1d_MOD_set_mesh+0x1690>)\n+\tldr\tr2, [pc, #392]\t@ (1eb8 <__gridxc_mesh1d_MOD_set_mesh+0x16b0>)\n+\tldr\tr1, [pc, #396]\t@ (1ebc <__gridxc_mesh1d_MOD_set_mesh+0x16b4>)\n+\tldr\tr0, [pc, #396]\t@ (1ec0 <__gridxc_mesh1d_MOD_set_mesh+0x16b8>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr2, [pc, #388]\t@ (1e9c <__gridxc_mesh1d_MOD_set_mesh+0x1694>)\n-\tldr\tr1, [pc, #392]\t@ (1ea0 <__gridxc_mesh1d_MOD_set_mesh+0x1698>)\n-\tldr\tr0, [pc, #392]\t@ (1ea4 <__gridxc_mesh1d_MOD_set_mesh+0x169c>)\n+\tldr\tr2, [pc, #388]\t@ (1ec4 <__gridxc_mesh1d_MOD_set_mesh+0x16bc>)\n+\tldr\tr1, [pc, #392]\t@ (1ec8 <__gridxc_mesh1d_MOD_set_mesh+0x16c0>)\n+\tldr\tr0, [pc, #392]\t@ (1ecc <__gridxc_mesh1d_MOD_set_mesh+0x16c4>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr0, [pc, #384]\t@ (1ea8 <__gridxc_mesh1d_MOD_set_mesh+0x16a0>)\n+\tldr\tr0, [pc, #384]\t@ (1ed0 <__gridxc_mesh1d_MOD_set_mesh+0x16c8>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tldr\tr2, [pc, #380]\t@ (1eac <__gridxc_mesh1d_MOD_set_mesh+0x16a4>)\n-\tldr\tr1, [pc, #384]\t@ (1eb0 <__gridxc_mesh1d_MOD_set_mesh+0x16a8>)\n-\tldr\tr0, [pc, #384]\t@ (1eb4 <__gridxc_mesh1d_MOD_set_mesh+0x16ac>)\n+\tldr\tr2, [pc, #380]\t@ (1ed4 <__gridxc_mesh1d_MOD_set_mesh+0x16cc>)\n+\tldr\tr1, [pc, #384]\t@ (1ed8 <__gridxc_mesh1d_MOD_set_mesh+0x16d0>)\n+\tldr\tr0, [pc, #384]\t@ (1edc <__gridxc_mesh1d_MOD_set_mesh+0x16d4>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #376]\t@ (1eb8 <__gridxc_mesh1d_MOD_set_mesh+0x16b0>)\n-\tldr\tr0, [pc, #380]\t@ (1ebc <__gridxc_mesh1d_MOD_set_mesh+0x16b4>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #376]\t@ (1ee0 <__gridxc_mesh1d_MOD_set_mesh+0x16d8>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #376]\t@ (1ee4 <__gridxc_mesh1d_MOD_set_mesh+0x16dc>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #372]\t@ (1ec0 <__gridxc_mesh1d_MOD_set_mesh+0x16b8>)\n-\tldr\tr1, [pc, #372]\t@ (1ec4 <__gridxc_mesh1d_MOD_set_mesh+0x16bc>)\n-\tldr\tr0, [pc, #376]\t@ (1ec8 <__gridxc_mesh1d_MOD_set_mesh+0x16c0>)\n+\tldr\tr2, [pc, #372]\t@ (1ee8 <__gridxc_mesh1d_MOD_set_mesh+0x16e0>)\n+\tldr\tr1, [pc, #372]\t@ (1eec <__gridxc_mesh1d_MOD_set_mesh+0x16e4>)\n+\tldr\tr0, [pc, #376]\t@ (1ef0 <__gridxc_mesh1d_MOD_set_mesh+0x16e8>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #368]\t@ (1ecc <__gridxc_mesh1d_MOD_set_mesh+0x16c4>)\n-\tldr\tr0, [pc, #368]\t@ (1ed0 <__gridxc_mesh1d_MOD_set_mesh+0x16c8>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #368]\t@ (1ef4 <__gridxc_mesh1d_MOD_set_mesh+0x16ec>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #368]\t@ (1ef8 <__gridxc_mesh1d_MOD_set_mesh+0x16f0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #360]\t@ (1ed4 <__gridxc_mesh1d_MOD_set_mesh+0x16cc>)\n-\tldr\tr1, [pc, #364]\t@ (1ed8 <__gridxc_mesh1d_MOD_set_mesh+0x16d0>)\n-\tldr\tr0, [pc, #364]\t@ (1edc <__gridxc_mesh1d_MOD_set_mesh+0x16d4>)\n+\tldr\tr2, [pc, #360]\t@ (1efc <__gridxc_mesh1d_MOD_set_mesh+0x16f4>)\n+\tldr\tr1, [pc, #364]\t@ (1f00 <__gridxc_mesh1d_MOD_set_mesh+0x16f8>)\n+\tldr\tr0, [pc, #364]\t@ (1f04 <__gridxc_mesh1d_MOD_set_mesh+0x16fc>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #356]\t@ (1ee0 <__gridxc_mesh1d_MOD_set_mesh+0x16d8>)\n-\tldr\tr0, [pc, #360]\t@ (1ee4 <__gridxc_mesh1d_MOD_set_mesh+0x16dc>)\n-\tldr\tr2, [sp, #20]\n+\tldr\tr1, [pc, #356]\t@ (1f08 <__gridxc_mesh1d_MOD_set_mesh+0x1700>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #356]\t@ (1f0c <__gridxc_mesh1d_MOD_set_mesh+0x1704>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr2, [pc, #352]\t@ (1ee8 <__gridxc_mesh1d_MOD_set_mesh+0x16e0>)\n-\tldr\tr1, [pc, #352]\t@ (1eec <__gridxc_mesh1d_MOD_set_mesh+0x16e4>)\n-\tldr\tr0, [pc, #356]\t@ (1ef0 <__gridxc_mesh1d_MOD_set_mesh+0x16e8>)\n+\tldr\tr2, [pc, #352]\t@ (1f10 <__gridxc_mesh1d_MOD_set_mesh+0x1708>)\n+\tldr\tr1, [pc, #352]\t@ (1f14 <__gridxc_mesh1d_MOD_set_mesh+0x170c>)\n+\tldr\tr0, [pc, #356]\t@ (1f18 <__gridxc_mesh1d_MOD_set_mesh+0x1710>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n \tnop\n-\t.word\t0x000002ce\n+\t.word\t0x0000028e\n R_ARM_REL32\t.bss\n-\t.word\t0x000002c6\n+\t.word\t0x00000286\n R_ARM_REL32\t.LC1\n-\t.word\t0x000002c4\n+\t.word\t0x00000284\n R_ARM_REL32\t.bss\n-\t.word\t0x000002c0\n+\t.word\t0x00000280\n R_ARM_REL32\t.data\n-\t.word\t0x0000029a\n+\t.word\t0x0000025a\n R_ARM_REL32\t.bss\n-\t.word\t0x00000270\n+\t.word\t0x00000232\n R_ARM_REL32\t.LC4\n \t.word\t0x000001e4\n R_ARM_REL32\t.LC32\n \t.word\t0x000001e6\n R_ARM_REL32\t.LC33\n \t.word\t0x000001de\n R_ARM_REL32\t.LC16\n@@ -2913,239 +2944,242 @@\n \t.word\t0x00000158\n R_ARM_REL32\t.LC21\n \t.word\t0x0000015a\n R_ARM_REL32\t.LC30\n \t.word\t0x0000015c\n R_ARM_REL32\t.LC31\n \n-00001ef4 <__gridxc_mesh1d_MOD_interpolation_local>:\n+00001f1c <__gridxc_mesh1d_MOD_interpolation_local>:\n __gridxc_mesh1d_MOD_interpolation_local():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d10}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3952]\t@ 0xf70\n \tsub\tsp, #84\t@ 0x54\n \tadd\tr7, sp, #16\n \tmov\tr5, r1\n \tmov\tr8, r3\n \tmov\tr4, r2\n-\tldr\tr2, [pc, #684]\t@ (21c0 <__gridxc_mesh1d_MOD_interpolation_local+0x2cc>)\n+\tldr\tr2, [pc, #708]\t@ (2200 <__gridxc_mesh1d_MOD_interpolation_local+0x2e4>)\n \tmov\tr6, sp\n \tldr.w\tr3, [r7, #128]\t@ 0x80\n \tstr\tr3, [r7, #16]\n \tadd\tr2, pc\n \tldr\tr3, [r5, #0]\n \tstr\tr3, [r7, #20]\n-\tldr\tr3, [pc, #672]\t@ (21c4 <__gridxc_mesh1d_MOD_interpolation_local+0x2d0>)\n+\tldr\tr3, [pc, #696]\t@ (2204 <__gridxc_mesh1d_MOD_interpolation_local+0x2e8>)\n \tldr.w\tr9, [r8]\n-\tldr.w\tsl, [pc, #668]\t@ 21c8 <__gridxc_mesh1d_MOD_interpolation_local+0x2d4>\n+\tldr.w\tsl, [pc, #692]\t@ 2208 <__gridxc_mesh1d_MOD_interpolation_local+0x2ec>\n \tldr.w\tr1, [r7, #132]\t@ 0x84\n \tldr\tr3, [r2, r3]\n \tadd\tsl, pc\n \tldr.w\tr2, [r7, #136]\t@ 0x88\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #60]\t@ 0x3c\n \tmov.w\tr3, #0\n \tbic.w\tr3, r9, r9, asr #31\n \tlsls\tr3, r3, #3\n \tbic.w\tr5, r3, #4080\t@ 0xff0\n \tbic.w\tr5, r5, #15\n \tsub.w\tr5, sp, r5\n \tcmp\tr6, r5\n-\tbeq.n\t1f64 <__gridxc_mesh1d_MOD_interpolation_local+0x70>\n+\tbeq.n\t1f8c <__gridxc_mesh1d_MOD_interpolation_local+0x70>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr6, sp\n \tcmp\tr6, r5\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1f56 <__gridxc_mesh1d_MOD_interpolation_local+0x62>\n+\tbne.n\t1f7e <__gridxc_mesh1d_MOD_interpolation_local+0x62>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t219a <__gridxc_mesh1d_MOD_interpolation_local+0x2a6>\n+\tbne.w\t21d8 <__gridxc_mesh1d_MOD_interpolation_local+0x2bc>\n \tldr\tr6, [r0, #24]\n \tadd\tr3, sp, #16\n \tldr\tr5, [r0, #0]\n \tcmp\tr6, #0\n \tstr\tr3, [r7, #0]\n \tit\teq\n \tmoveq\tr6, #1\n \tcmp\tr1, #0\n-\tbeq.n\t206c <__gridxc_mesh1d_MOD_interpolation_local+0x178>\n+\tbeq.w\t20b2 <__gridxc_mesh1d_MOD_interpolation_local+0x196>\n \tmovs\tr3, #0\n \tmov\tr0, r8\n \tmov\tr2, r3\n \tstrd\tr3, r3, [sp]\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tldr.w\tfp, [pc, #568]\t@ 21cc <__gridxc_mesh1d_MOD_interpolation_local+0x2d8>\n+\tldr.w\tfp, [pc, #588]\t@ 220c <__gridxc_mesh1d_MOD_interpolation_local+0x2f0>\n \tmovs\tr2, #6\n-\tldr\tr3, [pc, #564]\t@ (21d0 <__gridxc_mesh1d_MOD_interpolation_local+0x2dc>)\n+\tldr\tr3, [pc, #588]\t@ (2210 <__gridxc_mesh1d_MOD_interpolation_local+0x2f4>)\n \tmovs\tr0, #10\n \tadd\tfp, pc\n \tadd.w\tfp, fp, #12\n \tadd\tr3, pc\n \tmov\tr1, fp\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t20ca <__gridxc_mesh1d_MOD_interpolation_local+0x1d6>\n-\tldr\tr3, [pc, #544]\t@ (21d4 <__gridxc_mesh1d_MOD_interpolation_local+0x2e0>)\n+\tbeq.w\t20f2 <__gridxc_mesh1d_MOD_interpolation_local+0x1d6>\n+\tldr\tr3, [pc, #568]\t@ (2214 <__gridxc_mesh1d_MOD_interpolation_local+0x2f8>)\n \tmov\tr1, fp\n \tmovs\tr2, #8\n \tmovs\tr0, #10\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.n\t209a <__gridxc_mesh1d_MOD_interpolation_local+0x1a6>\n+\tbne.n\t20e0 <__gridxc_mesh1d_MOD_interpolation_local+0x1c4>\n \tldr\tr3, [r7, #20]\n \tcmp\tr3, #0\n-\tble.n\t20aa <__gridxc_mesh1d_MOD_interpolation_local+0x1b6>\n+\tble.n\t2090 <__gridxc_mesh1d_MOD_interpolation_local+0x174>\n+\tldr.w\tr8, [pc, #548]\t@ 2218 <__gridxc_mesh1d_MOD_interpolation_local+0x2fc>\n \tadd.w\tr3, r7, #48\t@ 0x30\n-\tldr.w\tr8, [pc, #520]\t@ 21d8 <__gridxc_mesh1d_MOD_interpolation_local+0x2e4>\n \tstr\tr3, [r7, #4]\n \tadd.w\tr3, r7, #24\n \tstr\tr3, [r7, #12]\n \tadd.w\tr3, r7, #40\t@ 0x28\n \tstr\tr3, [r7, #8]\n \tmov\tr3, r9\n-\tcmp\tr3, #6\n \tmov.w\tsl, r6, lsl #3\n-\tit\tge\n-\tmovge\tr3, #6\n+\tcmp\tr3, #6\n \tadd\tr8, pc\n-\tmovs\tr6, #1\n+\tmov.w\tr6, #1\n \tadd.w\tfp, r7, #32\n+\tit\tge\n+\tmovge\tr3, #6\n \tstr\tr3, [r7, #0]\n-\tb.n\t203e <__gridxc_mesh1d_MOD_interpolation_local+0x14a>\n-\tsubs\tr1, #2\n+\tmov\tr0, r4\n+\tbl\t0 <__gridxc_mesh1d_MOD_locate>\n+\tvcvt.s32.f64\ts15, d0\n+\tvstr\td0, [r7, #32]\n+\tvmov\tr1, s15\n+\tcmp\tr1, #3\n+\tit\tle\n+\tldrle\tr3, [r7, #0]\n+\tble.n\t2042 <__gridxc_mesh1d_MOD_interpolation_local+0x126>\n+\tadds\tr3, r1, #3\n+\tcmp\tr3, r9\n+\tit\tge\n+\tmovge\tr3, r9\n+\tldr\tr2, [r7, #4]\n+\tcmp\tr3, r9\n+\tstr\tr2, [sp, #4]\n+\tite\tne\n+\tsubne\tr1, #2\n+\tsubeq\tr1, r3, #5\n+\tldr\tr2, [r7, #8]\n+\tstr\tr2, [sp, #0]\n \tcmp\tr1, #1\n \tit\tlt\n \tmovlt\tr1, #1\n-\tldr\tr2, [r7, #4]\n+\tldr\tr2, [r7, #12]\n+\tldr.w\tr0, [r8, #92]\t@ 0x5c\n \tsubs\tr3, r3, r1\n-\tstr\tr2, [sp, #4]\n \tadds\tr3, #1\n-\tldr\tr2, [r7, #8]\n-\tadds\tr6, #1\n-\tstr\tr2, [sp, #0]\n-\tadds\tr4, #8\n \tstr\tr3, [r7, #24]\n-\tldr.w\tr0, [r8, #92]\t@ 0x5c\n \tldr\tr3, [r7, #16]\n \tsubs\tr0, r1, r0\n \tsubs\tr1, #1\n-\tldr\tr2, [r7, #12]\n+\tadds\tr6, #1\n+\tadds\tr4, #8\n \tadd.w\tr1, r3, r1, lsl #3\n \tldr.w\tr3, [r8, #64]\t@ 0x40\n \tadd.w\tr0, r3, r0, lsl #3\n \tmov\tr3, fp\n \tbl\t0 <__gridxc_interpolation_MOD_polint>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_polint\n \tldrd\tr2, r3, [r7, #40]\t@ 0x28\n \tstrd\tr2, r3, [r5]\n \tldr\tr3, [r7, #20]\n \tadd\tr5, sl\n \tcmp\tr3, r6\n-\tblt.n\t20aa <__gridxc_mesh1d_MOD_interpolation_local+0x1b6>\n-\tmov\tr0, r4\n-\tbl\t0 <__gridxc_mesh1d_MOD_locate>\n-\tvcvt.s32.f64\ts15, d0\n-\tldr\tr3, [r7, #0]\n-\tvstr\td0, [r7, #32]\n-\tvmov\tr1, s15\n-\tcmp\tr1, #3\n-\tble.n\t205e <__gridxc_mesh1d_MOD_interpolation_local+0x16a>\n-\tadds\tr3, r1, #3\n-\tcmp\tr3, r9\n-\tit\tge\n-\tmovge\tr3, r9\n-\tcmp\tr3, r9\n-\tbne.n\t1ff6 <__gridxc_mesh1d_MOD_interpolation_local+0x102>\n-\tsubs\tr1, r3, #5\n-\tcmp\tr1, #1\n-\tit\tlt\n-\tmovlt\tr1, #1\n-\tb.n\t1ffe <__gridxc_mesh1d_MOD_interpolation_local+0x10a>\n+\tbge.n\t2020 <__gridxc_mesh1d_MOD_interpolation_local+0x104>\n+\tldr\tr2, [pc, #392]\t@ (221c <__gridxc_mesh1d_MOD_interpolation_local+0x300>)\n+\tldr\tr3, [pc, #368]\t@ (2204 <__gridxc_mesh1d_MOD_interpolation_local+0x2e8>)\n+\tadd\tr2, pc\n+\tldr\tr3, [r2, r3]\n+\tldr\tr2, [r3, #0]\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\teors\tr2, r3\n+\tmov.w\tr3, #0\n+\tbne.w\t21e0 <__gridxc_mesh1d_MOD_interpolation_local+0x2c4>\n+\tadds\tr7, #68\t@ 0x44\n+\tmov\tsp, r7\n+\tvpop\t{d8-d10}\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tcmp\tr2, #0\n-\tbeq.n\t1f92 <__gridxc_mesh1d_MOD_interpolation_local+0x9e>\n+\tbeq.n\t1fbc <__gridxc_mesh1d_MOD_interpolation_local+0xa0>\n \tadd.w\tr3, r9, #4294967295\t@ 0xffffffff\n-\tvmov\ts15, r3\n-\tvldr\td17, [r2]\n+\tvmov\ts14, r3\n+\tvldr\td6, [r2]\n \tadd.w\tr3, r7, #48\t@ 0x30\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s14\n \tstrd\tr1, r1, [sp]\n \tmov\tr2, r1\n \tmov\tr0, r8\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r7, #48]\t@ 0x30\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r7, #48]\t@ 0x30\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tb.n\t1f92 <__gridxc_mesh1d_MOD_interpolation_local+0x9e>\n-\tldr\tr3, [pc, #320]\t@ (21dc <__gridxc_mesh1d_MOD_interpolation_local+0x2e8>)\n+\tb.n\t1fbc <__gridxc_mesh1d_MOD_interpolation_local+0xa0>\n+\tldr\tr3, [pc, #316]\t@ (2220 <__gridxc_mesh1d_MOD_interpolation_local+0x304>)\n \tmovs\tr1, #56\t@ 0x38\n-\tldr\tr0, [pc, #320]\t@ (21e0 <__gridxc_mesh1d_MOD_interpolation_local+0x2ec>)\n+\tldr\tr0, [pc, #316]\t@ (2224 <__gridxc_mesh1d_MOD_interpolation_local+0x308>)\n \tadd\tr0, pc\n \tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #312]\t@ (21e4 <__gridxc_mesh1d_MOD_interpolation_local+0x2f0>)\n-\tldr\tr3, [pc, #276]\t@ (21c4 <__gridxc_mesh1d_MOD_interpolation_local+0x2d0>)\n-\tadd\tr2, pc\n-\tldr\tr3, [r2, r3]\n-\tldr\tr2, [r3, #0]\n-\tldr\tr3, [r7, #60]\t@ 0x3c\n-\teors\tr2, r3\n-\tmov.w\tr3, #0\n-\tbne.n\t21a2 <__gridxc_mesh1d_MOD_interpolation_local+0x2ae>\n-\tadds\tr7, #68\t@ 0x44\n-\tmov\tsp, r7\n-\tvpop\t{d8-d10}\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tb.n\t2090 <__gridxc_mesh1d_MOD_interpolation_local+0x174>\n \tldr\tr3, [r7, #0]\n \tmov\tr2, r8\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [pc, #276]\t@ (21e8 <__gridxc_mesh1d_MOD_interpolation_local+0x2f4>)\n+\tldr\tr3, [pc, #300]\t@ (2228 <__gridxc_mesh1d_MOD_interpolation_local+0x30c>)\n \tadd\tr3, pc\n \tstr\tr3, [sp, #0]\n \tadd.w\tfp, r3, #8\n \tldr\tr1, [r7, #16]\n \tmov\tr0, fp\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n \tldr\tr3, [r7, #20]\n \tcmp\tr3, #0\n-\tble.n\t20aa <__gridxc_mesh1d_MOD_interpolation_local+0x1b6>\n+\tble.n\t2090 <__gridxc_mesh1d_MOD_interpolation_local+0x174>\n \tvmov\ts15, r9\n-\tvldr\td10, [pc, #184]\t@ 21a8 <__gridxc_mesh1d_MOD_interpolation_local+0x2b4>\n-\tvldr\td16, [pc, #188]\t@ 21b0 <__gridxc_mesh1d_MOD_interpolation_local+0x2bc>\n+\tvldr\td10, [pc, #208]\t@ 21e8 <__gridxc_mesh1d_MOD_interpolation_local+0x2cc>\n \tadd.w\tr3, r7, #48\t@ 0x30\n-\tvcvt.f64.s32\td9, s15\n \tmov.w\tr9, r6, lsl #3\n+\tvcvt.f64.s32\td9, s15\n+\tvldr\td7, [pc, #200]\t@ 21f0 <__gridxc_mesh1d_MOD_interpolation_local+0x2d4>\n \tstr\tr3, [r7, #4]\n \tmovs\tr6, #1\n \tadd.w\tr3, r7, #24\n \tstr\tr3, [r7, #12]\n \tadd.w\tr3, r7, #40\t@ 0x28\n \tstr\tr3, [r7, #8]\n \tvmul.f64\td10, d9, d10\n-\tvadd.f64\td9, d9, d16\n-\tb.n\t216c <__gridxc_mesh1d_MOD_interpolation_local+0x278>\n+\tvadd.f64\td9, d9, d7\n+\tb.n\t21aa <__gridxc_mesh1d_MOD_interpolation_local+0x28e>\n \tvcmpe.f64\td0, d9\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t2188 <__gridxc_mesh1d_MOD_interpolation_local+0x294>\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvmaxnm.f64\td8, d0, d16\n-\tvminnm.f64\td8, d8, d10\n+\tbgt.n\t21c6 <__gridxc_mesh1d_MOD_interpolation_local+0x2aa>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvcmpe.f64\td0, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td8, d7\n+\tvcmpe.f64\td8, d10\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td8, d10\n \tvstr\td8, [r7, #32]\n \tldr\tr3, [r7, #12]\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tstr\tr3, [sp, #8]\n \tmov\tr0, fp\n \tldr\tr3, [r7, #8]\n-\tvsub.f64\td8, d8, d16\n+\tvsub.f64\td8, d8, d7\n \tstr\tr3, [sp, #4]\n \tadds\tr6, #1\n \tldr\tr3, [r7, #4]\n \tadds\tr4, #8\n \tstr\tr3, [sp, #0]\n \tmov\tr3, r8\n \tldr\tr2, [r7, #0]\n@@ -3154,1838 +3188,1832 @@\n \tbl\t0 <__gridxc_interpolation_MOD_evaluate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_evaluate_spline_dx\n \tldrd\tr2, r3, [r7, #40]\t@ 0x28\n \tstrd\tr2, r3, [r5]\n \tldr\tr3, [r7, #20]\n \tadd\tr5, r9\n \tcmp\tr3, r6\n-\tblt.n\t20aa <__gridxc_mesh1d_MOD_interpolation_local+0x1b6>\n+\tblt.w\t2090 <__gridxc_mesh1d_MOD_interpolation_local+0x174>\n \tmov\tr0, r4\n \tbl\t0 <__gridxc_mesh1d_MOD_locate>\n-\tvldr\td16, [pc, #68]\t@ 21b8 <__gridxc_mesh1d_MOD_interpolation_local+0x2c4>\n+\tvldr\td7, [pc, #68]\t@ 21f8 <__gridxc_mesh1d_MOD_interpolation_local+0x2dc>\n \tvmov.f64\td8, d0\n \tvstr\td0, [r7, #32]\n-\tvcmpe.f64\td0, d16\n+\tvcmpe.f64\td0, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t211a <__gridxc_mesh1d_MOD_interpolation_local+0x226>\n-\tldr\tr3, [pc, #80]\t@ (21dc <__gridxc_mesh1d_MOD_interpolation_local+0x2e8>)\n+\tbpl.n\t2142 <__gridxc_mesh1d_MOD_interpolation_local+0x226>\n+\tldr\tr3, [pc, #88]\t@ (2220 <__gridxc_mesh1d_MOD_interpolation_local+0x304>)\n \tmovs\tr1, #39\t@ 0x27\n-\tldr\tr0, [pc, #92]\t@ (21ec <__gridxc_mesh1d_MOD_interpolation_local+0x2f8>)\n+\tldr\tr0, [pc, #96]\t@ (222c <__gridxc_mesh1d_MOD_interpolation_local+0x310>)\n \tadd\tr0, pc\n \tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t2134 <__gridxc_mesh1d_MOD_interpolation_local+0x240>\n+\tb.n\t2170 <__gridxc_mesh1d_MOD_interpolation_local+0x254>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t1f72 <__gridxc_mesh1d_MOD_interpolation_local+0x7e>\n+\tb.n\t1f9a <__gridxc_mesh1d_MOD_interpolation_local+0x7e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\tnop.w\n \t.word\t0xfffffffe\n \t.word\t0x3fefffff\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n-\t.word\t0x000002a0\n+\t.word\t0x000002b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000292\n+\t.word\t0x000002aa\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000022c\n+\t.word\t0x00000242\n R_ARM_REL32\t.data\n-\t.word\t0x0000022a\n+\t.word\t0x00000240\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000218\n+\t.word\t0x0000022e\n R_ARM_REL32\t.LC10\n-\t.word\t0x000001ea\n+\t.word\t0x00000204\n R_ARM_REL32\t.bss\n+\t.word\t0x00000184\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000013c\n+\t.word\t0x0000013a\n R_ARM_REL32\t.LC41\n-\t.word\t0x00000132\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000112\n+\t.word\t0x0000012a\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000005a\n+\t.word\t0x0000005c\n R_ARM_REL32\t.LC40\n \n-000021f0 <__gridxc_mesh1d_MOD_derivative>:\n+00002230 <__gridxc_mesh1d_MOD_derivative>:\n __gridxc_mesh1d_MOD_derivative.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3936]\t@ 0xf60\n+\tstr.w\tr0, [ip, #3872]\t@ 0xf20\n \tmov\tr6, r1\n \tsub\tsp, #124\t@ 0x7c\n \tmov\tr5, r2\n-\tldr.w\tr2, [pc, #1160]\t@ 2690 <__gridxc_mesh1d_MOD_derivative+0x4a0>\n+\tldr.w\tr2, [pc, #1204]\t@ 2700 <__gridxc_mesh1d_MOD_derivative+0x4d0>\n \tmov\tr1, r3\n \tldr\tr4, [r6, #0]\n \tadd\tr7, sp, #16\n-\tldr.w\tr3, [pc, #1152]\t@ 2694 <__gridxc_mesh1d_MOD_derivative+0x4a4>\n+\tldr.w\tr3, [pc, #1196]\t@ 2704 <__gridxc_mesh1d_MOD_derivative+0x4d4>\n \tadd\tr2, pc\n-\tldr.w\tfp, [pc, #1152]\t@ 2698 <__gridxc_mesh1d_MOD_derivative+0x4a8>\n+\tldr.w\tsl, [pc, #1196]\t@ 2708 <__gridxc_mesh1d_MOD_derivative+0x4d8>\n \tmov\tr9, sp\n \tbic.w\tip, r4, r4, asr #31\n-\tadd\tfp, pc\n+\tadd\tsl, pc\n \tldr\tr3, [r2, r3]\n \tmov.w\tip, ip, lsl #3\n \tmov\tr2, ip\n \tadd.w\tip, ip, #7\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #100]\t@ 0x64\n \tmov.w\tr3, #0\n \tbic.w\tr3, r2, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n-\tldrd\tlr, r8, [r7, #144]\t@ 0x90\n+\tldrd\tlr, r8, [r7, #208]\t@ 0xd0\n \tcmp\tr9, r3\n-\tbeq.n\t2258 <__gridxc_mesh1d_MOD_derivative+0x68>\n+\tbeq.n\t229c <__gridxc_mesh1d_MOD_derivative+0x6c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr9, sp\n \tcmp\tr9, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t224a <__gridxc_mesh1d_MOD_derivative+0x5a>\n+\tbne.n\t228e <__gridxc_mesh1d_MOD_derivative+0x5e>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t23ea <__gridxc_mesh1d_MOD_derivative+0x1fa>\n+\tbne.w\t2426 <__gridxc_mesh1d_MOD_derivative+0x1f6>\n \tbic.w\tr3, ip, #4080\t@ 0xff0\n-\tmov\tr9, sp\n+\tmov\tfp, sp\n \tbic.w\tr3, r3, #15\n-\tadd.w\tsl, sp, #16\n+\tadd.w\tr9, sp, #16\n \tsub.w\tr3, sp, r3\n \tbic.w\tr2, ip, #7\n-\tcmp\tr9, r3\n-\tbeq.n\t228e <__gridxc_mesh1d_MOD_derivative+0x9e>\n+\tcmp\tfp, r3\n+\tbeq.n\t22d2 <__gridxc_mesh1d_MOD_derivative+0xa2>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n-\tmov\tr9, sp\n-\tcmp\tr9, r3\n+\tmov\tfp, sp\n+\tcmp\tfp, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2280 <__gridxc_mesh1d_MOD_derivative+0x90>\n+\tbne.n\t22c4 <__gridxc_mesh1d_MOD_derivative+0x94>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t23f4 <__gridxc_mesh1d_MOD_derivative+0x204>\n+\tbne.w\t2430 <__gridxc_mesh1d_MOD_derivative+0x200>\n \tbic.w\tr3, ip, #4080\t@ 0xff0\n \tadd\tr2, sp, #16\n \tbic.w\tr3, r3, #15\n \tstr\tr2, [r7, #8]\n \tsub.w\tr3, sp, r3\n \tmov\tr2, sp\n \tbic.w\tip, ip, #7\n \tcmp\tr2, r3\n-\tbeq.n\t22c4 <__gridxc_mesh1d_MOD_derivative+0xd4>\n+\tbeq.n\t2308 <__gridxc_mesh1d_MOD_derivative+0xd8>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t22b6 <__gridxc_mesh1d_MOD_derivative+0xc6>\n+\tbne.n\t22fa <__gridxc_mesh1d_MOD_derivative+0xca>\n \tubfx\tr3, ip, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 22d4 <__gridxc_mesh1d_MOD_derivative+0xe4>\n+\tcbz\tr3, 2318 <__gridxc_mesh1d_MOD_derivative+0xe8>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tldr.w\tr9, [r0, #24]\n+\tldr.w\tfp, [r0, #24]\n \tldr\tr3, [r0, #0]\n-\tcmp.w\tr9, #0\n+\tcmp.w\tfp, #0\n \tstr\tr3, [r7, #12]\n-\tmov.w\tr3, #1\n \tit\teq\n-\tmoveq\tr9, r3\n+\tmoveq.w\tfp, #1\n \tadd\tr3, sp, #16\n \tstr\tr3, [r7, #0]\n \tcmp\tr1, #0\n-\tbeq.w\t23fe <__gridxc_mesh1d_MOD_derivative+0x20e>\n+\tbeq.w\t243a <__gridxc_mesh1d_MOD_derivative+0x20a>\n \tmovs\tr3, #0\n \tmov\tr0, r6\n \tmov\tr2, r3\n \tstrd\tr3, r3, [sp]\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n \tcmp.w\tr8, #0\n-\tbeq.w\t2430 <__gridxc_mesh1d_MOD_derivative+0x240>\n+\tbeq.w\t246a <__gridxc_mesh1d_MOD_derivative+0x23a>\n \tldr.w\tr8, [r8]\n \tcmp.w\tr8, #1\n-\tble.w\t242e <__gridxc_mesh1d_MOD_derivative+0x23e>\n+\tble.w\t2468 <__gridxc_mesh1d_MOD_derivative+0x238>\n \tldr\tr3, [r7, #12]\n-\tsubs\tr2, r4, #1\n-\tvldr\td17, [pc, #852]\t@ 2670 <__gridxc_mesh1d_MOD_derivative+0x480>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r7, #44\t@ 0x2c\n-\tmovw\tr1, #769\t@ 0x301\n-\tstr.w\tr9, [r7, #88]\t@ 0x58\n-\tstr\tr4, [r7, #96]\t@ 0x60\n-\tvst1.32\t{d17}, [r3]\n-\trsb\tr3, r9, #0\n-\tstr\tr3, [r7, #68]\t@ 0x44\n+\tsubs\tr1, r4, #1\n+\tstr\tr3, [r7, #28]\n+\trsb\tr3, fp, #0\n+\tstr\tr3, [r7, #32]\n \tmovs\tr3, #0\n-\tcmp\tr2, r3\n-\tstrd\tr3, r2, [r7, #52]\t@ 0x34\n+\tcmp\tr1, r3\n+\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstrd\tr3, r3, [r7, #40]\t@ 0x28\n+\tmov.w\tr2, #8\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n+\tmov\tr9, sp\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n \tit\tge\n \tlslge\tr3, r4, #3\n-\tvstr\td16, [r7, #76]\t@ 0x4c\n+\tstr\tr2, [r7, #48]\t@ 0x30\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\tstr\tr2, [r7, #84]\t@ 0x54\n+\tmovs\tr2, #1\n+\tstr\tr2, [r7, #56]\t@ 0x38\n+\tstr\tr2, [r7, #88]\t@ 0x58\n+\tmovw\tr2, #769\t@ 0x301\n+\tstrh\tr2, [r7, #44]\t@ 0x2c\n+\tstrh.w\tr2, [r7, #80]\t@ 0x50\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n-\tstrh.w\tr1, [r7, #80]\t@ 0x50\n \tbic.w\tr2, r2, #15\n-\tvstr\td16, [r7, #36]\t@ 0x24\n+\tstr\tr1, [r7, #96]\t@ 0x60\n \tsub.w\tr2, sp, r2\n-\tstrh\tr1, [r7, #40]\t@ 0x28\n-\tmovs\tr1, #8\n-\tstr\tr1, [r7, #84]\t@ 0x54\n-\tstr\tr1, [r7, #72]\t@ 0x48\n-\tmov\tr9, sp\n-\tstr\tr1, [r7, #32]\n-\tmovs\tr1, #1\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n \tmov\tr1, sp\n \tcmp\tr1, r2\n-\tbeq.n\t2382 <__gridxc_mesh1d_MOD_derivative+0x192>\n+\tstr.w\tfp, [r7, #52]\t@ 0x34\n+\tstr\tr4, [r7, #60]\t@ 0x3c\n+\tbeq.n\t23ba <__gridxc_mesh1d_MOD_derivative+0x18a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2374 <__gridxc_mesh1d_MOD_derivative+0x184>\n+\tbne.n\t23ac <__gridxc_mesh1d_MOD_derivative+0x17c>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 2392 <__gridxc_mesh1d_MOD_derivative+0x1a2>\n+\tcbz\tr3, 23ca <__gridxc_mesh1d_MOD_derivative+0x19a>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tmovs\tr4, #0\n \tadd.w\tsl, sp, #16\n \tmov\tr2, r5\n \tmov\tr3, r4\n \tmov\tr1, r6\n-\tadd.w\tr0, r7, #24\n-\tstrd\tsl, r4, [r7, #24]\n+\tadd.w\tr0, r7, #64\t@ 0x40\n+\tstrd\tsl, r4, [r7, #64]\t@ 0x40\n \tstrd\tr4, r4, [sp]\n-\tbl\t21f0 <__gridxc_mesh1d_MOD_derivative>\n+\tbl\t2230 <__gridxc_mesh1d_MOD_derivative>\n \tadd.w\tr2, r8, #4294967295\t@ 0xffffffff\n \tadd.w\tr3, r7, #16\n \tstr\tr2, [r7, #16]\n \tmov\tr1, r6\n \tstr\tr3, [sp, #4]\n \tstr\tr4, [sp, #0]\n \tmov\tr2, sl\n \tmov\tr3, r4\n-\tadd.w\tr0, r7, #64\t@ 0x40\n-\tbl\t21f0 <__gridxc_mesh1d_MOD_derivative>\n+\tadd.w\tr0, r7, #28\n+\tbl\t2230 <__gridxc_mesh1d_MOD_derivative>\n \tmov\tsp, r9\n-\tldr\tr2, [pc, #716]\t@ (269c <__gridxc_mesh1d_MOD_derivative+0x4ac>)\n-\tldr\tr3, [pc, #708]\t@ (2694 <__gridxc_mesh1d_MOD_derivative+0x4a4>)\n+\tldr\tr2, [pc, #772]\t@ (270c <__gridxc_mesh1d_MOD_derivative+0x4dc>)\n+\tldr\tr3, [pc, #764]\t@ (2704 <__gridxc_mesh1d_MOD_derivative+0x4d4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #100]\t@ 0x64\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t29ca <__gridxc_mesh1d_MOD_derivative+0x7da>\n+\tbne.w\t29de <__gridxc_mesh1d_MOD_derivative+0x7ae>\n \tadds\tr7, #108\t@ 0x6c\n \tmov\tsp, r7\n+\tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tb.n\t2266 <__gridxc_mesh1d_MOD_derivative+0x76>\n+\tb.n\t22aa <__gridxc_mesh1d_MOD_derivative+0x7a>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tb.n\t229c <__gridxc_mesh1d_MOD_derivative+0xac>\n+\tb.n\t22e0 <__gridxc_mesh1d_MOD_derivative+0xb0>\n \tcmp.w\tlr, #0\n-\tbeq.w\t2300 <__gridxc_mesh1d_MOD_derivative+0x110>\n+\tbeq.n\t2342 <__gridxc_mesh1d_MOD_derivative+0x112>\n \tsubs\tr3, r4, #1\n-\tvmov\ts15, r3\n-\tvldr\td17, [lr]\n+\tvmov\ts14, r3\n+\tvldr\td6, [lr]\n \tadd.w\tr3, r7, #16\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s14\n \tmov\tr2, r1\n \tmov\tr0, r6\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r7, #16]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r7, #16]\n \tstrd\tr1, r1, [sp]\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tb.n\t2300 <__gridxc_mesh1d_MOD_derivative+0x110>\n-\tbne.n\t23cc <__gridxc_mesh1d_MOD_derivative+0x1dc>\n-\tldr.w\tr8, [pc, #620]\t@ 26a0 <__gridxc_mesh1d_MOD_derivative+0x4b0>\n+\tb.n\t2342 <__gridxc_mesh1d_MOD_derivative+0x112>\n+\tbne.n\t2404 <__gridxc_mesh1d_MOD_derivative+0x1d4>\n+\tldr.w\tr8, [pc, #676]\t@ 2710 <__gridxc_mesh1d_MOD_derivative+0x4e0>\n \tmovs\tr2, #6\n-\tldr\tr3, [pc, #620]\t@ (26a4 <__gridxc_mesh1d_MOD_derivative+0x4b4>)\n+\tldr\tr3, [pc, #672]\t@ (2714 <__gridxc_mesh1d_MOD_derivative+0x4e4>)\n \tmovs\tr0, #10\n \tadd\tr8, pc\n \tadd.w\tr1, r8, #12\n \tadd\tr3, pc\n \tstr\tr1, [r7, #4]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tldr\tr1, [r7, #4]\n \tcmp\tr0, #0\n-\tbeq.w\t2700 <__gridxc_mesh1d_MOD_derivative+0x510>\n-\tldr\tr3, [pc, #596]\t@ (26a8 <__gridxc_mesh1d_MOD_derivative+0x4b8>)\n+\tbeq.w\t2724 <__gridxc_mesh1d_MOD_derivative+0x4f4>\n+\tldr\tr3, [pc, #652]\t@ (2718 <__gridxc_mesh1d_MOD_derivative+0x4e8>)\n \tmovs\tr2, #8\n \tmovs\tr0, #10\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tmov\tr2, r0\n \tcmp\tr0, #0\n-\tbne.w\t26ac <__gridxc_mesh1d_MOD_derivative+0x4bc>\n+\tbne.w\t269c <__gridxc_mesh1d_MOD_derivative+0x46c>\n \tsub.w\tip, r4, #2\n \tcmp.w\tip, #2\n-\tble.w\t28ba <__gridxc_mesh1d_MOD_derivative+0x6ca>\n-\tvldr\td22, [r5, #24]\n+\tble.w\t28de <__gridxc_mesh1d_MOD_derivative+0x6ae>\n+\tvldr\td4, [r5, #24]\n \tsub.w\tlr, r4, #3\n \tcmp\tr4, #7\n-\tble.w\t2976 <__gridxc_mesh1d_MOD_derivative+0x786>\n-\tvmov.f64\td20, d22\n+\tble.w\t2996 <__gridxc_mesh1d_MOD_derivative+0x766>\n+\tvmov.f64\td0, d4\n \tldr\tr1, [r7, #0]\n-\tvldr\td23, [r5, #8]\n+\tvldr\td3, [r5, #8]\n \tmov\tr3, r5\n-\tvldr\td21, [r5, #16]\n+\tvldr\td5, [r5, #16]\n \tmovs\tr2, #3\n-\tvldr\td24, [pc, #484]\t@ 2678 <__gridxc_mesh1d_MOD_derivative+0x488>\n-\tvmov.f64\td19, #32\t@ 0x41000000 8.0\n-\tvldr\td17, [r3]\n-\tvmov.f64\td18, d20\n-\tvfma.f64\td17, d20, d19\n-\tvldr\td20, [r3, #48]\t@ 0x30\n-\tvmov.f64\td25, d21\n-\tvldr\td16, [r3, #8]\n-\tvldr\td21, [r3, #40]\t@ 0x28\n-\tvmov.f64\td26, d23\n-\tvmov.f64\td27, d20\n-\tvldr\td23, [r3, #32]\n-\tvfma.f64\td27, d18, d19\n-\tvldr\td18, [r3, #16]\n-\tvsub.f64\td16, d16, d21\n+\tvldr\td2, [pc, #540]\t@ 26e8 <__gridxc_mesh1d_MOD_derivative+0x4b8>\n+\tvmov.f64\td6, #32\t@ 0x41000000 8.0\n+\tvmul.f64\td1, d0, d6\n+\tvldr\td7, [r3]\n+\tvmul.f64\td8, d3, d6\n+\tvldr\td3, [r3, #32]\n+\tvmul.f64\td0, d5, d6\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tadds\tr3, #24\n \tmov\tr0, r2\n-\tvfma.f64\td16, d23, d19\n+\tvadd.f64\td7, d1, d7\n \tadds\tr0, #4\n-\tadds\tr3, #24\n-\tadds\tr1, #24\n-\tvsub.f64\td17, d17, d23\n \tadds\tr2, #3\n-\tvfms.f64\td17, d26, d19\n+\tadds\tr1, #24\n \tcmp\tlr, r0\n-\tvfms.f64\td16, d25, d19\n-\tvsub.f64\td18, d18, d27\n-\tvfma.f64\td18, d21, d19\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td18, d18, d24\n-\tvstr\td17, [r1, #-8]\n-\tvstr\td16, [r1]\n-\tvstr\td18, [r1, #8]\n-\tbgt.n\t2498 <__gridxc_mesh1d_MOD_derivative+0x2a8>\n-\tlsls\tr3, r2, #3\n-\tldr\tr1, [r7, #0]\n-\tsub.w\tr0, r3, #8\n-\tvldr\td21, [pc, #356]\t@ 2678 <__gridxc_mesh1d_MOD_derivative+0x488>\n-\tadd\tr3, r5\n-\tadd\tr0, r1\n-\tvmov.f64\td17, #32\t@ 0x41000000 8.0\n-\tmov\tr1, r3\n-\tvldr\td18, [r3, #-16]\n+\tvsub.f64\td7, d7, d3\n+\tvsub.f64\td7, d7, d8\n+\tvmul.f64\td7, d7, d2\n+\tvstr\td7, [r1, #-8]\n+\tvldr\td7, [r3, #-16]\n+\tvsub.f64\td7, d7, d5\n+\tvmla.f64\td7, d3, d6\n+\tvsub.f64\td7, d7, d0\n+\tvldr\td0, [r3, #24]\n+\tvadd.f64\td1, d1, d0\n+\tvmul.f64\td7, d7, d2\n+\tvstr\td7, [r1]\n+\tvldr\td7, [r3, #-8]\n+\tvsub.f64\td7, d7, d1\n+\tvmla.f64\td7, d5, d6\n+\tvmul.f64\td7, d7, d2\n+\tvstr\td7, [r1, #8]\n+\tbgt.n\t24d2 <__gridxc_mesh1d_MOD_derivative+0x2a2>\n+\tlsls\tr1, r2, #3\n+\tldr\tr3, [r7, #0]\n+\tsub.w\tr0, r1, #8\n+\tvldr\td7, [pc, #412]\t@ 26e8 <__gridxc_mesh1d_MOD_derivative+0x4b8>\n+\tadd\tr1, r5\n+\tadd\tr0, r3\n+\tvmov.f64\td5, #32\t@ 0x41000000 8.0\n+\tmov\tr3, r1\n \tadds\tr2, #1\n-\tadds\tr3, #8\n+\tadds\tr1, #8\n \tcmp\tip, r2\n-\tvldr\td20, [r1]\n-\tvldr\td16, [r1, #-24]\t@ 0xffffffe8\n-\tvldr\td19, [r3]\n-\tvfma.f64\td16, d20, d17\n-\tvsub.f64\td16, d16, d19\n-\tvfms.f64\td16, d18, d17\n-\tvmul.f64\td16, d16, d21\n-\tvstmia\tr0!, {d16}\n-\tbge.n\t251e <__gridxc_mesh1d_MOD_derivative+0x32e>\n-\tvldr\td29, [r5, #8]\n-\tvmov.f64\td20, #48\t@ 0x41800000 16.0\n-\tvldr\td23, [pc, #296]\t@ 2680 <__gridxc_mesh1d_MOD_derivative+0x490>\n-\tvmov.f64\td26, #57\t@ 0x41c80000 25.0\n-\tvmul.f64\td18, d22, d20\n-\tvldr\td31, [r5]\n-\tvldr\td28, [r5, #32]\n-\tvmov.f64\td19, #50\t@ 0x41900000 18.0\n-\tvfma.f64\td18, d29, d23\n-\tvldr\td30, [r5, #16]\n-\tvldr\td17, [pc, #272]\t@ 2688 <__gridxc_mesh1d_MOD_derivative+0x498>\n-\tvmov.f64\td24, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td27, d28\n-\tvmov.f64\td16, #36\t@ 0x41200000 10.0\n-\tvfma.f64\td27, d30, d19\n-\tvmov.f64\td25, #24\t@ 0x40c00000 6.0\n-\tvfms.f64\td18, d31, d26\n+\tvldr\td1, [r3]\n+\tvldr\td6, [r3, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [r1]\n+\tvmla.f64\td6, d1, d5\n+\tvldr\td3, [r3, #-16]\n+\tvsub.f64\td6, d6, d2\n+\tvmls.f64\td6, d3, d5\n+\tvmul.f64\td6, d6, d7\n+\tvstmia\tr0!, {d6}\n+\tbge.n\t2554 <__gridxc_mesh1d_MOD_derivative+0x324>\n+\tvldr\td0, [r5, #8]\n+\tvmov.f64\td13, #48\t@ 0x41800000 16.0\n+\tvldr\td12, [pc, #356]\t@ 26f0 <__gridxc_mesh1d_MOD_derivative+0x4c0>\n+\tvmov.f64\td2, #57\t@ 0x41c80000 25.0\n+\tvmul.f64\td3, d4, d13\n+\tvldr\td8, [r5]\n+\tvldr\td10, [r5, #16]\n+\tvmov.f64\td1, #8\t@ 0x40400000 3.0\n+\tvmla.f64\td3, d0, d12\n+\tvldr\td5, [pc, #336]\t@ 26f8 <__gridxc_mesh1d_MOD_derivative+0x4c8>\n+\tvldr\td9, [r5, #32]\n \tlsls\tr3, r4, #3\n \tadd\tr5, r3\n+\tvmov.f64\td15, #50\t@ 0x41900000 18.0\n \tldr\tr2, [r7, #0]\n-\tvfms.f64\td27, d31, d24\n+\tvmls.f64\td3, d8, d2\n+\tvldr\td14, [r5, #-24]\t@ 0xffffffe8\n \tadd\tr3, r2\n-\tvfms.f64\td18, d30, d17\n-\tvldr\td30, [r5, #-8]\n-\tvfms.f64\td27, d29, d16\n-\tvldr\td29, [r5, #-16]\n-\tvfms.f64\td18, d28, d24\n-\tvldr\td28, [r5, #-40]\t@ 0xffffffd8\n-\tvmul.f64\td16, d29, d16\n-\tvfms.f64\td27, d22, d25\n-\tvfma.f64\td16, d30, d24\n-\tvmul.f64\td18, d18, d21\n-\tvmul.f64\td22, d27, d21\n-\tvldr\td27, [r5, #-32]\t@ 0xffffffe0\n-\tvstr\td18, [r2]\n-\tvldr\td18, [r5, #-24]\t@ 0xffffffe8\n-\tvfma.f64\td16, d27, d25\n-\tvmul.f64\td17, d18, d17\n-\tvfma.f64\td17, d30, d26\n-\tvfma.f64\td17, d28, d24\n-\tvsub.f64\td16, d16, d28\n-\tvfms.f64\td16, d18, d19\n-\tvfms.f64\td17, d29, d23\n-\tvfms.f64\td17, d27, d20\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td17, d17, d21\n-\tvstr\td17, [r3, #-8]\n-\tvstr\td22, [r2, #8]\n-\tvstr\td16, [r3, #-16]\n+\tvldr\td6, [r5, #-8]\n+\tvldr\td11, [r5, #-16]\n+\tvmls.f64\td3, d10, d5\n+\tvmul.f64\td5, d14, d5\n+\tvmla.f64\td5, d6, d2\n+\tvmov.f64\td2, d9\n+\tvmla.f64\td2, d10, d15\n+\tvmov.f64\td6, #36\t@ 0x41200000 10.0\n+\tvmls.f64\td3, d9, d1\n+\tvmls.f64\td2, d8, d1\n+\tvmls.f64\td2, d0, d6\n+\tvldr\td0, [r5, #-8]\n+\tvmul.f64\td6, d11, d6\n+\tvmul.f64\td3, d3, d7\n+\tvmla.f64\td6, d0, d1\n+\tvldr\td0, [r5, #-32]\t@ 0xffffffe0\n+\tvstr\td3, [r2]\n+\tvldr\td3, [r5, #-40]\t@ 0xffffffd8\n+\tvmla.f64\td5, d3, d1\n+\tvmls.f64\td5, d11, d12\n+\tvmls.f64\td5, d0, d13\n+\tvmul.f64\td5, d5, d7\n+\tvstr\td5, [r3, #-8]\n+\tvmov.f64\td5, #24\t@ 0x40c00000 6.0\n+\tvmla.f64\td6, d0, d5\n+\tvmls.f64\td2, d4, d5\n+\tvsub.f64\td6, d6, d3\n+\tvmul.f64\td2, d2, d7\n+\tvmls.f64\td6, d14, d15\n+\tvstr\td2, [r2, #8]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [r3, #-16]\n \tldr\tr3, [r7, #8]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r7, #84\t@ 0x54\n-\tvldr\td17, [pc, #88]\t@ 2670 <__gridxc_mesh1d_MOD_derivative+0x480>\n \tmovs\tr2, #0\n-\tstr\tr4, [r7, #96]\t@ 0x60\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tmov\tr0, r6\n-\tvstr\td16, [r7, #72]\t@ 0x48\n-\tadd.w\tr1, r7, #16\n-\tvstr\td16, [r7, #76]\t@ 0x4c\n-\tvst1.32\t{d17}, [r3]\n \tmovs\tr3, #1\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstr\tr4, [r7, #96]\t@ 0x60\n+\tstrd\tr3, r3, [r7, #88]\t@ 0x58\n+\tadd.w\tr1, r7, #16\n+\tmovs\tr3, #8\n+\tstrd\tr2, r2, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #84]\t@ 0x54\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr\tr2, [r7, #80]\t@ 0x50\n \tstr\tr3, [r7, #68]\t@ 0x44\n \tadd.w\tr3, r7, #64\t@ 0x40\n \tstrd\tr2, r2, [sp, #4]\n \tstr\tr2, [sp, #0]\n \tbl\t388 <__gridxc_mesh1d_MOD_get_mesh>\n-\tcmp.w\tr9, #1\n-\tbne.w\t2894 <__gridxc_mesh1d_MOD_derivative+0x6a4>\n+\tcmp.w\tfp, #1\n+\tbne.w\t28b8 <__gridxc_mesh1d_MOD_derivative+0x688>\n \tldr\tr3, [r7, #0]\n \tldrd\tr1, r2, [r7, #8]\n \tadd.w\tr4, r3, r4, lsl #3\n-\tvldmia\tr3!, {d18}\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr3!, {d5}\n+\tvldmia\tr1!, {d6}\n \tcmp\tr3, r4\n-\tvdiv.f64\td16, d18, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t2658 <__gridxc_mesh1d_MOD_derivative+0x468>\n-\tb.n\t23cc <__gridxc_mesh1d_MOD_derivative+0x1dc>\n-\tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x55555555\n-\t.word\t0x3fb55555\n-\t.word\t0x00000000\n-\t.word\t0x40480000\n-\t.word\t0x00000000\n-\t.word\t0x40420000\n-\t.word\t0x00000478\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000474\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002c8\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000262\n- R_ARM_REL32\t.data\n-\t.word\t0x00000260\n- R_ARM_REL32\t.LC8\n-\t.word\t0x0000024e\n- R_ARM_REL32\t.LC10\n-\tldr\tr3, [pc, #824]\t@ (29e8 <__gridxc_mesh1d_MOD_derivative+0x7f8>)\n+\tvdiv.f64\td7, d5, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t2686 <__gridxc_mesh1d_MOD_derivative+0x456>\n+\tb.n\t2404 <__gridxc_mesh1d_MOD_derivative+0x1d4>\n+\tldr\tr3, [pc, #124]\t@ (271c <__gridxc_mesh1d_MOD_derivative+0x4ec>)\n \tmovs\tr1, #53\t@ 0x35\n-\tldr\tr0, [pc, #824]\t@ (29ec <__gridxc_mesh1d_MOD_derivative+0x7fc>)\n+\tldr\tr0, [pc, #124]\t@ (2720 <__gridxc_mesh1d_MOD_derivative+0x4f0>)\n \tadd\tr0, pc\n-\tldr.w\tr3, [fp, r3]\n+\tldr.w\tr3, [sl, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [r7, #8]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [r7, #64]\t@ 0x40\n-\tadd.w\tr3, r7, #84\t@ 0x54\n-\tvldr\td17, [pc, #772]\t@ 29d0 <__gridxc_mesh1d_MOD_derivative+0x7e0>\n \tmovs\tr2, #0\n-\tstr\tr4, [r7, #96]\t@ 0x60\n+\tstr\tr3, [r7, #64]\t@ 0x40\n \tmov\tr0, r6\n-\tvstr\td16, [r7, #72]\t@ 0x48\n-\tadd.w\tr1, r7, #16\n-\tvstr\td16, [r7, #76]\t@ 0x4c\n-\tvst1.32\t{d17}, [r3]\n+\tstr\tr4, [r7, #96]\t@ 0x60\n \tmovs\tr3, #1\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tstrd\tr2, r2, [r7, #72]\t@ 0x48\n+\tadd.w\tr1, r7, #16\n+\tstrd\tr3, r3, [r7, #88]\t@ 0x58\n+\tmovs\tr3, #8\n+\tstr\tr2, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #84]\t@ 0x54\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr\tr3, [r7, #68]\t@ 0x44\n \tadd.w\tr3, r7, #64\t@ 0x40\n \tstrd\tr2, r2, [sp, #4]\n \tstr\tr2, [sp, #0]\n \tbl\t388 <__gridxc_mesh1d_MOD_get_mesh>\n \tcmp\tr4, #0\n-\tbgt.n\t2646 <__gridxc_mesh1d_MOD_derivative+0x456>\n-\tb.n\t23cc <__gridxc_mesh1d_MOD_derivative+0x1dc>\n-\tldr\tr0, [pc, #748]\t@ (29f0 <__gridxc_mesh1d_MOD_derivative+0x800>)\n+\tbgt.n\t2674 <__gridxc_mesh1d_MOD_derivative+0x444>\n+\tb.n\t2404 <__gridxc_mesh1d_MOD_derivative+0x1d4>\n+\tnop.w\n+\t.word\t0x55555555\n+\t.word\t0x3fb55555\n+\t.word\t0x00000000\n+\t.word\t0x40480000\n+\t.word\t0x00000000\n+\t.word\t0x40420000\n+\t.word\t0x000004a4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000004a0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000300\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000298\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000296\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x00000284\n+ R_ARM_REL32\t.LC10\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x0000007a\n+ R_ARM_REL32\t.LC42\n+\tldr\tr0, [pc, #720]\t@ (29f8 <__gridxc_mesh1d_MOD_derivative+0x7c8>)\n \tadd.w\tr3, r8, #32\n \tmov\tr2, r6\n \tstr\tr3, [sp, #0]\n \tadd\tr0, pc\n \tadd.w\tr3, r8, #24\n \tadds\tr0, #8\n \tmov\tr1, r5\n-\tstr.w\tsl, [sp, #4]\n+\tstr.w\tr9, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n-\tvldr\td22, [sl, #8]\n-\tvldr\td23, [sl]\n-\tvmov.f64\td19, #0\t@ 0x40000000 2.0\n-\tvldr\td20, [r5, #8]\n+\tvldr\td7, [r9]\n+\tvldr\td2, [r9, #8]\n \tlsls\tr3, r4, #3\n-\tvmov.f64\td17, d22\n-\tvldr\td21, [r5]\n-\tvfma.f64\td17, d23, d19\n-\tvldr\td18, [pc, #668]\t@ 29d8 <__gridxc_mesh1d_MOD_derivative+0x7e8>\n-\tadd.w\tr2, sl, r3\n-\tldr\tr0, [r7, #0]\n-\tvsub.f64\td16, d20, d21\n+\tvldr\td6, [r5, #8]\n+\tadd.w\tr2, r9, r3\n+\tvadd.f64\td4, d7, d7\n+\tvldr\td3, [r5]\n+\tvldr\td1, [pc, #652]\t@ 29e8 <__gridxc_mesh1d_MOD_derivative+0x7b8>\n \tadd\tr3, r5\n+\tldr\tr0, [r7, #0]\n \tcmp\tr4, #2\n-\tvldr\td25, [r2, #-8]\n-\tvldr\td24, [r3, #-16]\n-\tvfms.f64\td16, d17, d18\n-\tvldr\td17, [r2, #-16]\n-\tvfma.f64\td17, d25, d19\n-\tvstr\td16, [r0]\n-\tvldr\td16, [r3, #-8]\n+\tvsub.f64\td5, d6, d3\n+\tvldr\td0, [r2, #-16]\n+\tvadd.f64\td4, d4, d2\n+\tvmls.f64\td5, d4, d1\n+\tvldr\td4, [r3, #-8]\n+\tvstr\td5, [r0]\n+\tvldr\td5, [r2, #-8]\n+\tvadd.f64\td5, d5, d5\n+\tvadd.f64\td5, d5, d0\n+\tvldr\td0, [r3, #-16]\n \tadd.w\tr3, r0, r4, lsl #3\n-\tvsub.f64\td16, d16, d24\n-\tvfma.f64\td16, d17, d18\n-\tvstr\td16, [r3, #-8]\n-\tble.n\t26bc <__gridxc_mesh1d_MOD_derivative+0x4cc>\n+\tvsub.f64\td4, d4, d0\n+\tvmla.f64\td4, d5, d1\n+\tvstr\td4, [r3, #-8]\n+\tble.n\t26ac <__gridxc_mesh1d_MOD_derivative+0x47c>\n \tsub.w\tlr, r4, #4\n \tcmp\tr4, #8\n-\tble.w\t297a <__gridxc_mesh1d_MOD_derivative+0x78a>\n-\tvldr\td25, [pc, #600]\t@ 29e0 <__gridxc_mesh1d_MOD_derivative+0x7f0>\n+\tble.w\t299a <__gridxc_mesh1d_MOD_derivative+0x76a>\n+\tvldr\td0, [pc, #580]\t@ 29f0 <__gridxc_mesh1d_MOD_derivative+0x7c0>\n \tmov\tr1, r5\n-\tmov\tr3, sl\n+\tmov\tr3, r9\n \tmovs\tr2, #3\n-\tvmov.f64\td24, #96\t@ 0x3f000000 0.5\n-\tvldr\td19, [r3, #16]\n+\tvmov.f64\td1, #96\t@ 0x3f000000 0.5\n+\tvldr\td9, [r3, #16]\n \tadds\tr0, #48\t@ 0x30\n-\tvldr\td31, [r1, #16]\n+\tvldr\td5, [r1, #16]\n \tadd.w\tip, r2, #7\n-\tvldr\td18, [r3, #24]\n+\tvldr\td8, [r3, #24]\n \tadds\tr1, #48\t@ 0x30\n-\tvsub.f64\td27, d23, d19\n-\tvldr\td17, [r3, #32]\n-\tvldr\td16, [r3, #40]\t@ 0x28\n-\tvsub.f64\td6, d31, d21\n-\tvldr\td23, [r3, #48]\t@ 0x30\n-\tvsub.f64\td26, d22, d18\n-\tvldr\td30, [r1, #-24]\t@ 0xffffffe8\n-\tvsub.f64\td19, d19, d17\n-\tvldr\td29, [r1, #-16]\n-\tvsub.f64\td18, d18, d16\n-\tvldr\td28, [r1, #-8]\n-\tvsub.f64\td17, d17, d23\n-\tvldr\td21, [r1]\n-\tvsub.f64\td7, d30, d20\n-\tvldr\td22, [r3, #56]\t@ 0x38\n-\tvsub.f64\td31, d29, d31\n-\tvsub.f64\td30, d28, d30\n-\tvldr\td20, [r1, #8]\n-\tvsub.f64\td29, d21, d29\n-\tvmul.f64\td27, d27, d25\n-\tvsub.f64\td16, d16, d22\n-\tvmul.f64\td26, d26, d25\n-\tvsub.f64\td28, d20, d28\n-\tvmul.f64\td19, d19, d25\n-\tvmul.f64\td18, d18, d25\n-\tvmul.f64\td17, d17, d25\n-\tvfma.f64\td27, d6, d24\n-\tvfma.f64\td26, d7, d24\n-\tvfma.f64\td19, d31, d24\n-\tvfma.f64\td18, d30, d24\n-\tvfma.f64\td17, d29, d24\n-\tvmul.f64\td16, d16, d25\n-\tvfma.f64\td16, d28, d24\n+\tvsub.f64\td7, d7, d9\n+\tvldr\td4, [r3, #32]\n+\tvsub.f64\td3, d5, d3\n \tadds\tr3, #48\t@ 0x30\n+\tvsub.f64\td2, d2, d8\n \tadds\tr2, #6\n \tcmp\tlr, ip\n-\tvstr\td27, [r0, #-40]\t@ 0xffffffd8\n-\tvstr\td26, [r0, #-32]\t@ 0xffffffe0\n-\tvstr\td19, [r0, #-24]\t@ 0xffffffe8\n-\tvstr\td18, [r0, #-16]\n-\tvstr\td17, [r0, #-8]\n-\tvstr\td16, [r0]\n-\tbgt.n\t2792 <__gridxc_mesh1d_MOD_derivative+0x5a2>\n+\tvmul.f64\td7, d7, d0\n+\tvmla.f64\td7, d3, d1\n+\tvldr\td3, [r1, #-24]\t@ 0xffffffe8\n+\tvsub.f64\td6, d3, d6\n+\tvmul.f64\td6, d6, d1\n+\tvmla.f64\td6, d2, d0\n+\tvldr\td2, [r1, #-16]\n+\tvstr\td7, [r0, #-40]\t@ 0xffffffd8\n+\tvsub.f64\td7, d9, d4\n+\tvldr\td9, [r1, #-8]\n+\tvsub.f64\td5, d2, d5\n+\tvmul.f64\td7, d7, d0\n+\tvsub.f64\td3, d9, d3\n+\tvmla.f64\td7, d5, d1\n+\tvldr\td5, [r3, #-8]\n+\tvstr\td6, [r0, #-32]\t@ 0xffffffe0\n+\tvldr\td6, [r1, #8]\n+\tvsub.f64\td8, d8, d5\n+\tvsub.f64\td9, d6, d9\n+\tvmul.f64\td8, d8, d0\n+\tvstr\td7, [r0, #-24]\t@ 0xffffffe8\n+\tvmla.f64\td8, d3, d1\n+\tvldr\td7, [r3]\n+\tvldr\td3, [r1]\n+\tvsub.f64\td4, d4, d7\n+\tvsub.f64\td2, d3, d2\n+\tvmul.f64\td4, d4, d0\n+\tvstr\td8, [r0, #-16]\n+\tvmla.f64\td4, d2, d1\n+\tvldr\td2, [r3, #8]\n+\tvsub.f64\td5, d5, d2\n+\tvmul.f64\td5, d5, d0\n+\tvmla.f64\td5, d9, d1\n+\tvstr\td4, [r0, #-8]\n+\tvstr\td5, [r0]\n+\tbgt.n\t27b6 <__gridxc_mesh1d_MOD_derivative+0x586>\n \tadd.w\tr3, r2, #536870912\t@ 0x20000000\n \tldr\tr1, [r7, #0]\n \tsubs\tr3, #3\n-\tvldr\td20, [pc, #396]\t@ 29e0 <__gridxc_mesh1d_MOD_derivative+0x7f0>\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [pc, #376]\t@ 29f0 <__gridxc_mesh1d_MOD_derivative+0x7c0>\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n \tlsls\tr3, r3, #3\n \tadd\tr5, r3\n-\tadd\tsl, r3\n+\tadd\tr9, r3\n \tadds\tr3, #8\n \tadd\tr1, r3\n-\tvldmia\tsl!, {d16}\n+\tvldmia\tr9!, {d7}\n \tmov\tr3, r5\n \tadds\tr2, #1\n \tadds\tr5, #8\n \tcmp\tr4, r2\n-\tvldr\td17, [sl, #8]\n-\tvldr\td18, [r3]\n-\tvsub.f64\td16, d16, d17\n-\tvldr\td17, [r5, #8]\n-\tvsub.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d20\n-\tvfma.f64\td16, d17, d19\n-\tvstmia\tr1!, {d16}\n-\tbge.n\t2864 <__gridxc_mesh1d_MOD_derivative+0x674>\n-\tb.n\t2608 <__gridxc_mesh1d_MOD_derivative+0x418>\n+\tvldr\td6, [r9, #8]\n+\tvldr\td5, [r3]\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [r5, #8]\n+\tvsub.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d3\n+\tvmla.f64\td7, d6, d4\n+\tvstmia\tr1!, {d7}\n+\tbge.n\t2888 <__gridxc_mesh1d_MOD_derivative+0x658>\n+\tb.n\t2642 <__gridxc_mesh1d_MOD_derivative+0x412>\n \tldr\tr0, [r7, #0]\n-\tmov.w\tr9, r9, lsl #3\n+\tmov.w\tfp, fp, lsl #3\n \tldr\tr1, [r7, #8]\n \tmovs\tr3, #0\n \tldr\tr2, [r7, #12]\n-\tvldmia\tr0!, {d18}\n+\tvldmia\tr0!, {d5}\n \tadds\tr3, #1\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr1!, {d6}\n \tcmp\tr4, r3\n-\tvdiv.f64\td16, d18, d17\n-\tvstr\td16, [r2]\n-\tadd\tr2, r9\n-\tbne.n\t28a0 <__gridxc_mesh1d_MOD_derivative+0x6b0>\n-\tb.n\t23cc <__gridxc_mesh1d_MOD_derivative+0x1dc>\n+\tvdiv.f64\td7, d5, d6\n+\tvstr\td7, [r2]\n+\tadd\tr2, fp\n+\tbne.n\t28c4 <__gridxc_mesh1d_MOD_derivative+0x694>\n+\tb.n\t2404 <__gridxc_mesh1d_MOD_derivative+0x1d4>\n \tcmp\tr4, #1\n-\tble.n\t297e <__gridxc_mesh1d_MOD_derivative+0x78e>\n-\tvldr\td16, [r5, #8]\n+\tble.n\t299e <__gridxc_mesh1d_MOD_derivative+0x76e>\n+\tvldr\td3, [r5, #8]\n \tcmp\tr4, #2\n-\tvldr\td19, [r5]\n-\tbeq.n\t2922 <__gridxc_mesh1d_MOD_derivative+0x732>\n-\tvldr\td20, [r5, #16]\n+\tvldr\td5, [r5]\n+\tbeq.n\t2942 <__gridxc_mesh1d_MOD_derivative+0x712>\n+\tvldr\td4, [r5, #16]\n \tcmp\tr4, #3\n-\tbeq.n\t2932 <__gridxc_mesh1d_MOD_derivative+0x742>\n-\tvldr\td17, [r5, #24]\n-\tvmov.f64\td24, #38\t@ 0x41300000 11.0\n-\tvmov.f64\td23, #34\t@ 0x41100000 9.0\n-\tvmov.f64\td22, #50\t@ 0x41900000 18.0\n-\tvmov.f64\td25, #0\t@ 0x40000000 2.0\n-\tvldr\td21, [pc, #240]\t@ 29d8 <__gridxc_mesh1d_MOD_derivative+0x7e8>\n-\tvadd.f64\td18, d17, d17\n-\tvmul.f64\td17, d17, d24\n-\tvfma.f64\td17, d16, d23\n-\tvfma.f64\td18, d16, d22\n+\tbeq.n\t2952 <__gridxc_mesh1d_MOD_derivative+0x722>\n+\tvldr\td7, [r5, #24]\n+\tvmov.f64\td0, #38\t@ 0x41300000 11.0\n+\tvmov.f64\td2, #34\t@ 0x41100000 9.0\n+\tvmov.f64\td1, #50\t@ 0x41900000 18.0\n+\tvadd.f64\td8, d5, d5\n \tldr\tr3, [r7, #0]\n-\tvfms.f64\td18, d19, d24\n-\tvmov.f64\td16, d17\n-\tvfms.f64\td18, d20, d23\n-\tvfms.f64\td16, d19, d25\n-\tvfms.f64\td16, d20, d22\n-\tvmul.f64\td17, d18, d21\n-\tvstr\td17, [r3]\n-\tvmul.f64\td16, d16, d21\n-\tvstr\td16, [r3, #24]\n-\tb.n\t2608 <__gridxc_mesh1d_MOD_derivative+0x418>\n-\tvsub.f64\td16, d16, d19\n+\tvadd.f64\td6, d7, d7\n+\tvmul.f64\td7, d7, d0\n+\tvmla.f64\td7, d3, d2\n+\tvmla.f64\td6, d3, d1\n+\tvldr\td3, [pc, #200]\t@ 29e8 <__gridxc_mesh1d_MOD_derivative+0x7b8>\n+\tvmls.f64\td6, d5, d0\n+\tvsub.f64\td7, d7, d8\n+\tvmls.f64\td6, d4, d2\n+\tvmls.f64\td7, d4, d1\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #24]\n+\tb.n\t2642 <__gridxc_mesh1d_MOD_derivative+0x412>\n+\tvsub.f64\td5, d3, d5\n \tldr\tr3, [r7, #0]\n-\tvstr\td16, [r3]\n-\tvstr\td16, [r3, #8]\n-\tb.n\t2608 <__gridxc_mesh1d_MOD_derivative+0x418>\n-\tvmov.f64\td23, #16\t@ 0x40800000 4.0\n-\tvmov.f64\td24, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td18, d20\n-\tvmov.f64\td17, d19\n-\tvfnms.f64\td18, d16, d23\n-\tvfma.f64\td17, d20, d24\n-\tvsub.f64\td22, d20, d19\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n+\tvstr\td5, [r3]\n+\tvstr\td5, [r3, #8]\n+\tb.n\t2642 <__gridxc_mesh1d_MOD_derivative+0x412>\n+\tvmov.f64\td7, #16\t@ 0x40800000 4.0\n+\tvmov.f64\td0, #8\t@ 0x40400000 3.0\n+\tvsub.f64\td1, d4, d5\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td3, d3, d7\n+\tvmov.f64\td7, d5\n+\tvmla.f64\td7, d4, d0\n \tldr\tr3, [r7, #0]\n-\tvfms.f64\td18, d19, d24\n-\tvfms.f64\td17, d16, d23\n-\tvmul.f64\td22, d22, d21\n-\tvstr\td22, [r3, #8]\n-\tvmul.f64\td18, d18, d21\n-\tvmul.f64\td17, d17, d21\n-\tvstr\td18, [r3]\n-\tvstr\td17, [r3, #16]\n-\tb.n\t2608 <__gridxc_mesh1d_MOD_derivative+0x418>\n+\tvmul.f64\td1, d1, d2\n+\tvsub.f64\td6, d3, d4\n+\tvmls.f64\td6, d5, d0\n+\tvstr\td1, [r3, #8]\n+\tvsub.f64\td7, d7, d3\n+\tvmul.f64\td6, d6, d2\n+\tvmul.f64\td7, d7, d2\n+\tvstr\td6, [r3]\n+\tvstr\td7, [r3, #16]\n+\tb.n\t2642 <__gridxc_mesh1d_MOD_derivative+0x412>\n \tmovs\tr2, #3\n-\tb.n\t250a <__gridxc_mesh1d_MOD_derivative+0x31a>\n+\tb.n\t2540 <__gridxc_mesh1d_MOD_derivative+0x310>\n \tmovs\tr2, #3\n-\tb.n\t284a <__gridxc_mesh1d_MOD_derivative+0x65a>\n-\tbeq.n\t29be <__gridxc_mesh1d_MOD_derivative+0x7ce>\n+\tb.n\t286e <__gridxc_mesh1d_MOD_derivative+0x63e>\n+\tbeq.n\t29d2 <__gridxc_mesh1d_MOD_derivative+0x7a2>\n \tldr\tr3, [r7, #8]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tmovs\tr1, #8\n \tstr\tr3, [r7, #64]\t@ 0x40\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tvldr\td17, [pc, #64]\t@ 29d0 <__gridxc_mesh1d_MOD_derivative+0x7e0>\n-\tmovs\tr1, #1\n-\tstr\tr3, [r7, #68]\t@ 0x44\n-\tadd.w\tr3, r7, #84\t@ 0x54\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n \tmov\tr0, r6\n-\tvstr\td16, [r7, #72]\t@ 0x48\n+\tmovs\tr3, #1\n+\tstr\tr2, [r7, #72]\t@ 0x48\n+\tstrd\tr1, r3, [r7, #84]\t@ 0x54\n+\tmov.w\tr1, #4294967295\t@ 0xffffffff\n+\tstr\tr3, [r7, #92]\t@ 0x5c\n+\tadd.w\tr3, r7, #64\t@ 0x40\n+\tstr\tr1, [r7, #68]\t@ 0x44\n \tadd.w\tr1, r7, #16\n \tstr\tr4, [r7, #96]\t@ 0x60\n-\tvstr\td16, [r7, #76]\t@ 0x4c\n-\tvst1.32\t{d17}, [r3]\n-\tadd.w\tr3, r7, #64\t@ 0x40\n+\tstrd\tr2, r2, [r7, #76]\t@ 0x4c\n \tstrd\tr2, r2, [sp, #4]\n \tstr\tr2, [sp, #0]\n \tbl\t388 <__gridxc_mesh1d_MOD_get_mesh>\n-\tb.n\t23cc <__gridxc_mesh1d_MOD_derivative+0x1dc>\n+\tb.n\t2404 <__gridxc_mesh1d_MOD_derivative+0x1d4>\n \tldr\tr1, [r7, #0]\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\t2608 <__gridxc_mesh1d_MOD_derivative+0x418>\n+\tb.n\t2642 <__gridxc_mesh1d_MOD_derivative+0x412>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n+\tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x55555555\n \t.word\t0x3fb55555\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000336\n- R_ARM_REL32\t.LC42\n-\t.word\t0x000002e2\n+\t.word\t0x000002c6\n R_ARM_REL32\t.rodata\n \n-000029f4 <__gridxc_mesh1d_MOD_integral>:\n+000029fc <__gridxc_mesh1d_MOD_integral>:\n __gridxc_mesh1d_MOD_integral.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n+\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n+\tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n \tsub\tsp, #36\t@ 0x24\n \tadd\tr7, sp, #8\n \tmov\tr4, r1\n \tmov\tr1, r2\n-\tldr\tr2, [pc, #972]\t@ (2de0 <__gridxc_mesh1d_MOD_integral+0x3ec>)\n+\tldr\tr2, [pc, #996]\t@ (2e00 <__gridxc_mesh1d_MOD_integral+0x404>)\n \tldr\tr5, [r0, #0]\n \tmov\tr6, r0\n-\tldr\tr0, [pc, #972]\t@ (2de4 <__gridxc_mesh1d_MOD_integral+0x3f0>)\n+\tldr\tr0, [pc, #996]\t@ (2e04 <__gridxc_mesh1d_MOD_integral+0x408>)\n \tadd\tr2, pc\n \tstr\tr2, [r7, #4]\n \tmov\tlr, sp\n-\tldr\tr2, [pc, #968]\t@ (2de8 <__gridxc_mesh1d_MOD_integral+0x3f4>)\n+\tldr\tr2, [pc, #992]\t@ (2e08 <__gridxc_mesh1d_MOD_integral+0x40c>)\n \tadd\tr0, pc\n \tldr\tr2, [r0, r2]\n \tbic.w\tr0, r5, r5, asr #31\n \tlsls\tr0, r0, #3\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [r7, #20]\n \tmov.w\tr2, #0\n \tmov\tip, r0\n \tadds\tr0, #7\n \tbic.w\tr2, ip, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tlr, r2\n-\tbeq.n\t2a54 <__gridxc_mesh1d_MOD_integral+0x60>\n+\tbeq.n\t2a5c <__gridxc_mesh1d_MOD_integral+0x60>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tlr, sp\n \tcmp\tlr, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2a46 <__gridxc_mesh1d_MOD_integral+0x52>\n+\tbne.n\t2a4e <__gridxc_mesh1d_MOD_integral+0x52>\n \tubfx\tr2, ip, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t2bbc <__gridxc_mesh1d_MOD_integral+0x1c8>\n+\tbne.w\t2bc4 <__gridxc_mesh1d_MOD_integral+0x1c8>\n \tbic.w\tr2, r0, #4080\t@ 0xff0\n \tmov\tip, sp\n \tbic.w\tr2, r2, #15\n \tbic.w\tr0, r0, #7\n \tsub.w\tr2, sp, r2\n \tadd.w\tr9, sp, #8\n \tcmp\tip, r2\n-\tbeq.n\t2a8a <__gridxc_mesh1d_MOD_integral+0x96>\n+\tbeq.n\t2a92 <__gridxc_mesh1d_MOD_integral+0x96>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tip, sp\n \tcmp\tip, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2a7c <__gridxc_mesh1d_MOD_integral+0x88>\n+\tbne.n\t2a84 <__gridxc_mesh1d_MOD_integral+0x88>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n \tcmp\tr0, #0\n-\tbne.w\t2c76 <__gridxc_mesh1d_MOD_integral+0x282>\n+\tbne.w\t2c7e <__gridxc_mesh1d_MOD_integral+0x282>\n \tadd.w\tr8, sp, #8\n \tcmp\tr1, #0\n-\tbeq.w\t2bc8 <__gridxc_mesh1d_MOD_integral+0x1d4>\n+\tbeq.w\t2bd0 <__gridxc_mesh1d_MOD_integral+0x1d4>\n \tmovs\tr3, #0\n \tmov\tr0, r6\n \tmov\tr2, r3\n \tstrd\tr3, r3, [sp]\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tldr.w\tfp, [pc, #824]\t@ 2dec <__gridxc_mesh1d_MOD_integral+0x3f8>\n+\tldr.w\tfp, [pc, #848]\t@ 2e0c <__gridxc_mesh1d_MOD_integral+0x410>\n \tmovs\tr2, #6\n-\tldr\tr3, [pc, #824]\t@ (2df0 <__gridxc_mesh1d_MOD_integral+0x3fc>)\n+\tldr\tr3, [pc, #848]\t@ (2e10 <__gridxc_mesh1d_MOD_integral+0x414>)\n \tmovs\tr0, #10\n \tadd\tfp, pc\n \tadd.w\tsl, fp, #12\n \tadd\tr3, pc\n \tmov\tr1, sl\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tmov\tr3, r0\n \tcmp\tr0, #0\n-\tbne.w\t2bf6 <__gridxc_mesh1d_MOD_integral+0x202>\n-\tldr\tr1, [pc, #800]\t@ (2df4 <__gridxc_mesh1d_MOD_integral+0x400>)\n+\tbne.w\t2bfe <__gridxc_mesh1d_MOD_integral+0x202>\n+\tldr\tr1, [pc, #824]\t@ (2e14 <__gridxc_mesh1d_MOD_integral+0x418>)\n \tcmp\tr5, #0\n \tadd\tr1, pc\n \tldrd\tr2, r1, [r1, #100]\t@ 0x64\n-\tble.w\t2c50 <__gridxc_mesh1d_MOD_integral+0x25c>\n+\tble.w\t2c58 <__gridxc_mesh1d_MOD_integral+0x25c>\n \tadds\tr1, #1\n \tadd.w\tr2, r2, r1, lsl #3\n \tmov\tr1, r8\n-\tvldmia\tr4!, {d16}\n+\tvldmia\tr4!, {d7}\n \tmov\tsl, r3\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tadds\tr3, #1\n \tcmp\tr5, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t2ae6 <__gridxc_mesh1d_MOD_integral+0xf2>\n-\tldr\tr3, [pc, #760]\t@ (2df8 <__gridxc_mesh1d_MOD_integral+0x404>)\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t2aee <__gridxc_mesh1d_MOD_integral+0xf2>\n+\tldr\tr3, [pc, #784]\t@ (2e18 <__gridxc_mesh1d_MOD_integral+0x41c>)\n \tmov\tr2, r6\n-\tldr\tr0, [pc, #760]\t@ (2dfc <__gridxc_mesh1d_MOD_integral+0x408>)\n+\tldr\tr0, [pc, #784]\t@ (2e1c <__gridxc_mesh1d_MOD_integral+0x420>)\n \tadd\tr3, pc\n \tstr.w\tr9, [sp, #4]\n \tadd\tr0, pc\n \tadd.w\tr1, r3, #32\n \tadds\tr0, #8\n \tstr\tr1, [sp, #0]\n \tadds\tr3, #24\n \tmov\tr1, r8\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n \tcmp\tr5, #2\n-\tble.w\t2c6c <__gridxc_mesh1d_MOD_integral+0x278>\n-\tvmov.i64\td17, #0x0000000000000000\n+\tble.w\t2c74 <__gridxc_mesh1d_MOD_integral+0x278>\n \tadd.w\tr1, r8, #8\n \tadd.w\tr3, sl, #4294967295\t@ 0xffffffff\n \tmovs\tr2, #0\n-\tvldmia\tr1!, {d16}\n+\tvldr\td6, [pc, #680]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n+\tvldmia\tr1!, {d7}\n \tadds\tr2, #1\n \tcmp\tr3, r2\n-\tvadd.f64\td17, d17, d16\n-\tbne.n\t2b30 <__gridxc_mesh1d_MOD_integral+0x13c>\n-\tvmov.i64\td16, #0x0000000000000000\n+\tvadd.f64\td6, d6, d7\n+\tbne.n\t2b38 <__gridxc_mesh1d_MOD_integral+0x13c>\n \tadd.w\tr1, r9, #8\n \tmovs\tr2, #0\n-\tvldmia\tr1!, {d18}\n+\tvldr\td7, [pc, #656]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n+\tvldmia\tr1!, {d5}\n \tadds\tr2, #1\n \tcmp\tr3, r2\n-\tvadd.f64\td16, d16, d18\n-\tbne.n\t2b48 <__gridxc_mesh1d_MOD_integral+0x154>\n-\tvldr\td18, [pc, #624]\t@ 2dc8 <__gridxc_mesh1d_MOD_integral+0x3d4>\n-\tvmul.f64\td16, d16, d18\n+\tvadd.f64\td7, d7, d5\n+\tbne.n\t2b50 <__gridxc_mesh1d_MOD_integral+0x154>\n+\tvldr\td5, [pc, #648]\t@ 2de8 <__gridxc_mesh1d_MOD_integral+0x3ec>\n+\tvmul.f64\td7, d7, d5\n \tsubs\tr5, #1\n-\tvldr\td19, [r9]\n-\tvldr\td18, [r8]\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n+\tvldr\td8, [r9]\n+\tvldr\td5, [r8]\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n \tlsls\tr5, r5, #3\n-\tvldr\td8, [pc, #608]\t@ 2dd0 <__gridxc_mesh1d_MOD_integral+0x3dc>\n+\tvldr\td3, [pc, #632]\t@ 2df0 <__gridxc_mesh1d_MOD_integral+0x3f4>\n \tadd\tr9, r5\n \tadd\tr8, r5\n-\tvldr\td22, [r9]\n-\tvldr\td21, [r8]\n-\tvadd.f64\td19, d19, d22\n-\tvadd.f64\td18, d18, d21\n-\tvnmul.f64\td8, d8, d19\n-\tvfma.f64\td8, d18, d20\n-\tvadd.f64\td8, d8, d17\n-\tvsub.f64\td8, d8, d16\n-\tldr\tr2, [pc, #616]\t@ (2e00 <__gridxc_mesh1d_MOD_integral+0x40c>)\n-\tldr\tr3, [pc, #588]\t@ (2de8 <__gridxc_mesh1d_MOD_integral+0x3f4>)\n+\tvldr\td1, [r9]\n+\tvldr\td2, [r8]\n+\tvadd.f64\td8, d8, d1\n+\tvadd.f64\td5, d5, d2\n+\tvmul.f64\td8, d8, d3\n+\tvnmls.f64\td8, d5, d4\n+\tvadd.f64\td8, d8, d6\n+\tvsub.f64\td8, d8, d7\n+\tldr\tr2, [pc, #640]\t@ (2e20 <__gridxc_mesh1d_MOD_integral+0x424>)\n+\tldr\tr3, [pc, #612]\t@ (2e08 <__gridxc_mesh1d_MOD_integral+0x40c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #20]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2d34 <__gridxc_mesh1d_MOD_integral+0x340>\n+\tbne.w\t2d44 <__gridxc_mesh1d_MOD_integral+0x348>\n \tvmov.f64\td0, d8\n \tadds\tr7, #28\n \tmov\tsp, r7\n-\tvpop\t{d8}\n+\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsub.w\tip, r2, #4\n \tadd.w\tr2, sp, ip\n \tstr\tr0, [r2, #0]\n-\tb.n\t2a62 <__gridxc_mesh1d_MOD_integral+0x6e>\n+\tb.n\t2a6a <__gridxc_mesh1d_MOD_integral+0x6e>\n \tcmp\tr3, #0\n-\tbeq.w\t2ab0 <__gridxc_mesh1d_MOD_integral+0xbc>\n-\tvldr\td17, [r3]\n+\tbeq.w\t2ab8 <__gridxc_mesh1d_MOD_integral+0xbc>\n+\tvldr\td6, [r3]\n \tsubs\tr3, r5, #1\n-\tvmov\ts15, r3\n+\tvmov\ts14, r3\n \tstrd\tr1, r1, [sp]\n \tadd.w\tr3, r7, #8\n \tmov\tr2, r1\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s14\n \tmov\tr0, r6\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r7, #8]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r7, #8]\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tb.n\t2ab0 <__gridxc_mesh1d_MOD_integral+0xbc>\n-\tldr\tr3, [pc, #524]\t@ (2e04 <__gridxc_mesh1d_MOD_integral+0x410>)\n+\tb.n\t2ab8 <__gridxc_mesh1d_MOD_integral+0xbc>\n+\tldr\tr3, [pc, #548]\t@ (2e24 <__gridxc_mesh1d_MOD_integral+0x428>)\n \tmovs\tr2, #8\n \tmov\tr1, sl\n \tmovs\tr0, #10\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 2c3e <__gridxc_mesh1d_MOD_integral+0x24a>\n-\tvmov.i64\td8, #0x0000000000000000\n+\tcbnz\tr0, 2c46 <__gridxc_mesh1d_MOD_integral+0x24a>\n+\tvldr\td8, [pc, #464]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n \tcmp\tr5, #1\n-\tble.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tldr\tr2, [pc, #504]\t@ (2e08 <__gridxc_mesh1d_MOD_integral+0x414>)\n+\tble.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tldr\tr2, [pc, #528]\t@ (2e28 <__gridxc_mesh1d_MOD_integral+0x42c>)\n \tsubs\tr3, r5, #2\n-\tvldr\td17, [r4]\n+\tvldr\td6, [r4]\n \tadd\tr2, pc\n-\tvldr\td20, [r4, #8]\n+\tvldr\td2, [r4, #8]\n \tldrd\tr0, r6, [r2, #100]\t@ 0x64\n \tadd.w\tr2, r0, r6, lsl #3\n-\tvldr\td16, [r2, #8]\n-\tvldr\td19, [r2, #16]\n-\tvmul.f64\td17, d17, d16\n+\tvldr\td7, [r2, #8]\n+\tvldr\td5, [r2, #16]\n+\tvmul.f64\td6, d6, d7\n \tcmp\tr3, #3\n-\tbhi.w\t2d38 <__gridxc_mesh1d_MOD_integral+0x344>\n+\tbhi.w\t2d48 <__gridxc_mesh1d_MOD_integral+0x34c>\n \ttbb\t[pc, r3]\n-\t.short\t0x6376\n-\t.short\t0x2348\n-\tldr\tr3, [pc, #460]\t@ (2e0c <__gridxc_mesh1d_MOD_integral+0x418>)\n+\t.short\t0x677a\n+\t.short\t0x234a\n+\tldr\tr3, [pc, #484]\t@ (2e2c <__gridxc_mesh1d_MOD_integral+0x430>)\n \tmovs\tr1, #51\t@ 0x33\n \tldr\tr2, [r7, #4]\n-\tldr\tr0, [pc, #456]\t@ (2e10 <__gridxc_mesh1d_MOD_integral+0x41c>)\n+\tldr\tr0, [pc, #480]\t@ (2e30 <__gridxc_mesh1d_MOD_integral+0x434>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tldr\tr0, [pc, #448]\t@ (2e14 <__gridxc_mesh1d_MOD_integral+0x420>)\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tldr\tr0, [pc, #472]\t@ (2e34 <__gridxc_mesh1d_MOD_integral+0x438>)\n \tadd.w\tr3, fp, #32\n \tmov\tr2, r6\n \tstr\tr3, [sp, #0]\n \tadd\tr0, pc\n \tadd.w\tr3, fp, #24\n \tadds\tr0, #8\n \tmov\tr1, r8\n \tstr.w\tr9, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvmov.f64\td17, d16\n-\tb.n\t2b5e <__gridxc_mesh1d_MOD_integral+0x16a>\n+\tvldr\td7, [pc, #360]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n+\tvmov.f64\td6, d7\n+\tb.n\t2b66 <__gridxc_mesh1d_MOD_integral+0x16a>\n \tsubs\tr0, #4\n \tadd.w\tr2, sp, r0\n \tstr\tr0, [r2, #0]\n-\tb.n\t2a98 <__gridxc_mesh1d_MOD_integral+0xa4>\n-\tvldr\td16, [r4, #24]\n-\tvmov.f64\td22, #60\t@ 0x41e00000 28.0\n-\tvldr\td8, [r2, #32]\n-\tvmov.f64\td21, #34\t@ 0x41100000 9.0\n-\tvldr\td23, [r4, #32]\n-\tvldr\td24, [r2, #40]\t@ 0x28\n-\tvmul.f64\td8, d16, d8\n-\tvldr\td18, [r2, #24]\n-\tvfma.f64\td8, d20, d19\n-\tvmov.f64\td16, #54\t@ 0x41b00000 22.0\n-\tvfma.f64\td17, d23, d24\n-\tvldr\td20, [r4, #16]\n-\tvmul.f64\td18, d18, d16\n-\tvldr\td19, [pc, #280]\t@ 2dd0 <__gridxc_mesh1d_MOD_integral+0x3dc>\n-\tvmul.f64\td8, d8, d22\n-\tvfma.f64\td8, d17, d21\n-\tvfma.f64\td8, d20, d18\n-\tvmul.f64\td8, d8, d19\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tvldr\td18, [r2, #24]\n-\tvmov.f64\td16, #34\t@ 0x41100000 9.0\n-\tvldr\td8, [r4, #16]\n-\tvmov.f64\td21, #8\t@ 0x40400000 3.0\n-\tvldr\td23, [r4, #24]\n-\tvldr\td22, [r2, #32]\n-\tvmul.f64\td8, d8, d18\n-\tvmov.f64\td18, #64\t@ 0x3e000000 0.125\n-\tvfma.f64\td8, d20, d19\n-\tvfma.f64\td17, d23, d22\n-\tvmul.f64\td8, d8, d16\n-\tvfma.f64\td8, d17, d21\n-\tvmul.f64\td8, d8, d18\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tvmov.f64\td16, #16\t@ 0x40800000 4.0\n-\tvldr\td22, [r4, #16]\n-\tvldr\td21, [r2, #24]\n-\tvmul.f64\td16, d19, d16\n-\tvldr\td18, [pc, #196]\t@ 2dd8 <__gridxc_mesh1d_MOD_integral+0x3e4>\n-\tvfma.f64\td17, d16, d20\n-\tvmov.f64\td8, d17\n-\tvfma.f64\td8, d22, d21\n-\tvmul.f64\td8, d8, d18\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tvfma.f64\td17, d20, d19\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td8, d17, d16\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tb.n\t2aa0 <__gridxc_mesh1d_MOD_integral+0xa4>\n+\tvldr\td3, [r4, #32]\n+\tvmul.f64\td5, d2, d5\n+\tvldr\td1, [r2, #40]\t@ 0x28\n+\tvldr\td4, [r4, #24]\n+\tvldr\td0, [r2, #32]\n+\tvmla.f64\td6, d3, d1\n+\tvldr\td7, [r2, #24]\n+\tvmov.f64\td1, #34\t@ 0x41100000 9.0\n+\tvldr\td2, [r4, #16]\n+\tvmla.f64\td5, d4, d0\n+\tvmov.f64\td4, #54\t@ 0x41b00000 22.0\n+\tvldr\td3, [pc, #312]\t@ 2df0 <__gridxc_mesh1d_MOD_integral+0x3f4>\n+\tvmul.f64\td7, d7, d4\n+\tvmov.f64\td8, d6\n+\tvmov.f64\td6, #60\t@ 0x41e00000 28.0\n+\tvmul.f64\td8, d8, d1\n+\tvmla.f64\td8, d5, d6\n+\tvmla.f64\td8, d7, d2\n+\tvmul.f64\td8, d8, d3\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tvldr\td9, [r4, #24]\n+\tvmul.f64\td7, d2, d5\n+\tvldr\td0, [r2, #32]\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tvldr\td1, [r4, #16]\n+\tvmov.f64\td5, #34\t@ 0x41100000 9.0\n+\tvldr\td3, [r2, #24]\n+\tvmla.f64\td6, d9, d0\n+\tvmla.f64\td7, d1, d3\n+\tvmov.f64\td8, d6\n+\tvmov.f64\td6, #64\t@ 0x3e000000 0.125\n+\tvmul.f64\td8, d8, d4\n+\tvmla.f64\td8, d7, d5\n+\tvmul.f64\td8, d8, d6\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tvmov.f64\td4, #16\t@ 0x40800000 4.0\n+\tvldr\td1, [r4, #16]\n+\tvldr\td3, [r2, #24]\n+\tvmul.f64\td5, d5, d4\n+\tvldr\td7, [pc, #212]\t@ 2df8 <__gridxc_mesh1d_MOD_integral+0x3fc>\n+\tvmla.f64\td6, d5, d2\n+\tvmov.f64\td8, d6\n+\tvmla.f64\td8, d1, d3\n+\tvmul.f64\td8, d8, d7\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tvmla.f64\td6, d2, d5\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td8, d6, d7\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tvmov.i64\td8, #0x0000000000000000\n \tcmp\tr5, #6\n-\tbeq.n\t2d62 <__gridxc_mesh1d_MOD_integral+0x36e>\n+\tbeq.n\t2dd6 <__gridxc_mesh1d_MOD_integral+0x3da>\n \tadds\tr3, r6, #4\n \tadd.w\tip, r4, #24\n+\tvldr\td8, [pc, #140]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n \tsub.w\tlr, r5, #6\n-\tmovs\tr1, #0\n \tadd.w\tr3, r0, r3, lsl #3\n-\tvldmia\tip!, {d18}\n+\tmovs\tr1, #0\n+\tvldmia\tip!, {d4}\n \tadds\tr1, #1\n-\tvldmia\tr3!, {d16}\n+\tvldmia\tr3!, {d7}\n \tcmp\tlr, r1\n-\tvfma.f64\td8, d18, d16\n-\tbne.n\t2d50 <__gridxc_mesh1d_MOD_integral+0x35c>\n-\tvldr\td28, [r2, #24]\n+\tvmla.f64\td8, d4, d7\n+\tbne.n\t2d60 <__gridxc_mesh1d_MOD_integral+0x364>\n+\tvldr\td0, [r2, #24]\n \tadds\tr2, r5, r6\n-\tvldr\td29, [r4, #16]\n+\tvldr\td3, [r4, #16]\n \tadd.w\tr5, r4, r5, lsl #3\n \tadd.w\tr4, r0, r2, lsl #3\n-\tvmov.f64\td25, #55\t@ 0x41b80000 23.0\n-\tvmov.f64\td24, #60\t@ 0x41e00000 28.0\n-\tvldr\td22, [pc, #80]\t@ 2dd0 <__gridxc_mesh1d_MOD_integral+0x3dc>\n-\tvldr\td30, [r5, #-24]\t@ 0xffffffe8\n-\tvmov.f64\td23, #34\t@ 0x41100000 9.0\n-\tvldr\td18, [r4, #-16]\n-\tvldr\td16, [r5, #-16]\n-\tvldr\td21, [r4, #-8]\n-\tvmul.f64\td18, d18, d30\n-\tvldr\td27, [r5, #-8]\n-\tvfma.f64\td18, d29, d28\n-\tvldr\td26, [r4]\n-\tvmul.f64\td21, d21, d16\n-\tvmov.f64\td16, d17\n-\tvfma.f64\td21, d20, d19\n-\tvfma.f64\td16, d27, d26\n-\tvmul.f64\td17, d18, d25\n-\tvfma.f64\td17, d21, d24\n-\tvfma.f64\td17, d16, d23\n-\tvfma.f64\td8, d17, d22\n-\tb.n\t2b96 <__gridxc_mesh1d_MOD_integral+0x1a2>\n-\tnop\n+\tvmul.f64\td7, d2, d5\n+\tvmul.f64\td3, d3, d0\n+\tvldr\td4, [r5, #-16]\n+\tvldr\td1, [r4, #-8]\n+\tvldr\td5, [r5, #-24]\t@ 0xffffffe8\n+\tvldr\td2, [r4, #-16]\n+\tvmla.f64\td7, d1, d4\n+\tvmov.f64\td4, d3\n+\tvldr\td1, [r4]\n+\tvmov.f64\td3, #34\t@ 0x41100000 9.0\n+\tvmla.f64\td4, d2, d5\n+\tvldr\td5, [r5, #-8]\n+\tvmov.f64\td2, #55\t@ 0x41b80000 23.0\n+\tvmla.f64\td6, d1, d5\n+\tvmov.f64\td1, #60\t@ 0x41e00000 28.0\n+\tvldr\td5, [pc, #44]\t@ 2df0 <__gridxc_mesh1d_MOD_integral+0x3f4>\n+\tvmul.f64\td7, d7, d1\n+\tvmla.f64\td7, d4, d2\n+\tvmla.f64\td7, d6, d3\n+\tvmla.f64\td8, d7, d5\n+\tb.n\t2b9e <__gridxc_mesh1d_MOD_integral+0x1a2>\n+\tvldr\td8, [pc, #8]\t@ 2de0 <__gridxc_mesh1d_MOD_integral+0x3e4>\n+\tb.n\t2d72 <__gridxc_mesh1d_MOD_integral+0x376>\n+\tnop.w\n+\t...\n \t.word\t0x55555555\n \t.word\t0x3fb55555\n \t.word\t0x55555555\n \t.word\t0x3fa55555\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x000003c4\n+\t.word\t0x000003dc\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003c0\n+\t.word\t0x000003d8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000032e\n+\t.word\t0x00000346\n R_ARM_REL32\t.data\n-\t.word\t0x0000032c\n+\t.word\t0x00000344\n R_ARM_REL32\t.LC8\n-\t.word\t0x0000031c\n+\t.word\t0x00000334\n R_ARM_REL32\t.bss\n-\t.word\t0x000002f0\n+\t.word\t0x00000308\n R_ARM_REL32\t.data\n-\t.word\t0x000002ee\n+\t.word\t0x00000306\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000262\n+\t.word\t0x0000027a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000202\n+\t.word\t0x0000021a\n R_ARM_REL32\t.LC10\n-\t.word\t0x000001ee\n+\t.word\t0x00000206\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000001c4\n+\t.word\t0x000001dc\n R_ARM_REL32\t.LC43\n-\t.word\t0x000001b6\n+\t.word\t0x000001ce\n R_ARM_REL32\t.rodata\n \n-00002e18 <__gridxc_mesh1d_MOD_numerov>:\n+00002e38 <__gridxc_mesh1d_MOD_numerov>:\n __gridxc_mesh1d_MOD_numerov():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n+\tvpush\t{d8-d13}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3536]\t@ 0xdd0\n+\tstr.w\tr0, [ip, #3504]\t@ 0xdb0\n \tsub\tsp, #508\t@ 0x1fc\n \tadd\tr7, sp, #8\n \tstrd\tr2, r3, [r7, #60]\t@ 0x3c\n-\tldr.w\tr2, [pc, #1624]\t@ 3490 <__gridxc_mesh1d_MOD_numerov+0x678>\n-\tldr.w\tr4, [r7, #552]\t@ 0x228\n-\tldr.w\tr3, [pc, #1620]\t@ 3494 <__gridxc_mesh1d_MOD_numerov+0x67c>\n+\tldr.w\tr2, [pc, #1576]\t@ 3480 <__gridxc_mesh1d_MOD_numerov+0x648>\n+\tldr.w\tr4, [r7, #584]\t@ 0x248\n+\tldr.w\tr3, [pc, #1572]\t@ 3484 <__gridxc_mesh1d_MOD_numerov+0x64c>\n \tadd\tr2, pc\n \tstr\tr4, [r7, #68]\t@ 0x44\n-\tldr.w\tr4, [r7, #556]\t@ 0x22c\n+\tldr.w\tr4, [r7, #588]\t@ 0x24c\n \tstr\tr4, [r7, #56]\t@ 0x38\n \tstr\tr0, [r7, #48]\t@ 0x30\n \tldr\tr3, [r2, r3]\n-\tldrd\tr2, ip, [r7, #560]\t@ 0x230\n+\tldrd\tr2, ip, [r7, #592]\t@ 0x250\n \tldr\tr3, [r3, #0]\n \tstr.w\tr3, [r7, #492]\t@ 0x1ec\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1592]\t@ 3498 <__gridxc_mesh1d_MOD_numerov+0x680>\n+\tldr.w\tr3, [pc, #1544]\t@ 3488 <__gridxc_mesh1d_MOD_numerov+0x650>\n \tstr.w\tsp, [r7, #16]\n \tadd\tr3, pc\n \tstr\tr3, [r7, #12]\n-\tldr.w\tr3, [r7, #568]\t@ 0x238\n+\tldr.w\tr3, [r7, #600]\t@ 0x258\n \tstr\tr3, [r7, #44]\t@ 0x2c\n \tstr\tr1, [r7, #52]\t@ 0x34\n \tcmp\tr1, #0\n-\tbeq.w\t3582 <__gridxc_mesh1d_MOD_numerov+0x76a>\n-\tldr\tr3, [r0, #0]\n-\tstr\tr3, [r7, #28]\n-\tmov\tr4, r3\n+\tbeq.w\t35a6 <__gridxc_mesh1d_MOD_numerov+0x76e>\n+\tldr.w\tsl, [r0]\n+\tmov\tr4, sl\n \tldr\tr5, [r7, #56]\t@ 0x38\n \tbic.w\tr3, r4, r4, asr #31\n \tldr\tr1, [r7, #68]\t@ 0x44\n-\tcmp\tr5, #0\n-\tmov\tr5, r4\n-\tit\teq\n-\tmoveq\tr5, #0\n \tlsls\tr3, r3, #3\n-\tcmp\tr1, #0\n-\tmov\tr1, r4\n-\tit\teq\n-\tmoveq\tr1, #0\n-\tmov\tr9, r5\n+\tcmp\tr5, #0\n+\tite\tne\n+\tmovne\tr9, r4\n+\tmoveq.w\tr9, #0\n \tldr\tr5, [r7, #60]\t@ 0x3c\n-\tmov\tsl, r1\n+\tcmp\tr1, #0\n+\tite\tne\n+\tmovne\tfp, r4\n+\tmoveq.w\tfp, #0\n \tmov\tr1, r3\n \tadds\tr3, #7\n \tcmp\tr5, #0\n-\tmov\tr5, r4\n-\tit\teq\n+\tite\tne\n+\tmovne\tr5, r4\n \tmoveq\tr5, #0\n \tbic.w\tr0, r1, #4080\t@ 0xff0\n \tstr\tr5, [r7, #8]\n \tbic.w\tr0, r0, #15\n \tldr\tr5, [r7, #64]\t@ 0x40\n \tsub.w\tr0, sp, r0\n \tcmp\tr5, #0\n-\tmov\tr6, r4\n-\tit\teq\n+\tite\tne\n+\tmovne\tr6, r4\n \tmoveq\tr6, #0\n \tmov\tr5, sp\n \tcmp\tr5, r0\n-\tbeq.n\t2ed4 <__gridxc_mesh1d_MOD_numerov+0xbc>\n+\tbeq.n\t2ef4 <__gridxc_mesh1d_MOD_numerov+0xbc>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr5, sp\n \tcmp\tr5, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2ec6 <__gridxc_mesh1d_MOD_numerov+0xae>\n+\tbne.n\t2ee6 <__gridxc_mesh1d_MOD_numerov+0xae>\n \tubfx\tr1, r1, #0, #12\n \tsub.w\tsp, sp, r1\n \tcmp\tr1, #0\n-\tbne.w\t3586 <__gridxc_mesh1d_MOD_numerov+0x76e>\n+\tbne.w\t35aa <__gridxc_mesh1d_MOD_numerov+0x772>\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr5, sp\n \tbic.w\tr1, r1, #15\n \tadd.w\tr8, sp, #8\n \tsub.w\tr1, sp, r1\n \tbic.w\tr0, r3, #7\n \tcmp\tr5, r1\n-\tbeq.n\t2f0a <__gridxc_mesh1d_MOD_numerov+0xf2>\n+\tbeq.n\t2f2a <__gridxc_mesh1d_MOD_numerov+0xf2>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr5, sp\n \tcmp\tr5, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2efc <__gridxc_mesh1d_MOD_numerov+0xe4>\n+\tbne.n\t2f1c <__gridxc_mesh1d_MOD_numerov+0xe4>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n \tcmp\tr0, #0\n-\tbne.w\t358e <__gridxc_mesh1d_MOD_numerov+0x776>\n+\tbne.w\t35b2 <__gridxc_mesh1d_MOD_numerov+0x77a>\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr5, sp\n \tbic.w\tr1, r1, #15\n-\tadd.w\tfp, sp, #8\n+\tadd\tr0, sp, #8\n \tsub.w\tr1, sp, r1\n-\tbic.w\tr0, r3, #7\n+\tstr\tr0, [r7, #40]\t@ 0x28\n \tcmp\tr5, r1\n-\tbeq.n\t2f40 <__gridxc_mesh1d_MOD_numerov+0x128>\n+\tbic.w\tr0, r3, #7\n+\tbeq.n\t2f60 <__gridxc_mesh1d_MOD_numerov+0x128>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr5, sp\n \tcmp\tr5, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2f32 <__gridxc_mesh1d_MOD_numerov+0x11a>\n+\tbne.n\t2f52 <__gridxc_mesh1d_MOD_numerov+0x11a>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n-\tcbz\tr0, 2f52 <__gridxc_mesh1d_MOD_numerov+0x13a>\n+\tcbz\tr0, 2f72 <__gridxc_mesh1d_MOD_numerov+0x13a>\n \tsubs\tr0, #4\n \tadd.w\tr1, sp, r0\n \tstr\tr0, [r1, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr5, sp\n \tbic.w\tr1, r1, #15\n \tadd\tr0, sp, #8\n \tsub.w\tr1, sp, r1\n-\tstr\tr0, [r7, #40]\t@ 0x28\n+\tstr\tr0, [r7, #36]\t@ 0x24\n \tcmp\tr5, r1\n \tbic.w\tr0, r3, #7\n-\tbeq.n\t2f7a <__gridxc_mesh1d_MOD_numerov+0x162>\n+\tbeq.n\t2f9a <__gridxc_mesh1d_MOD_numerov+0x162>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr5, sp\n \tcmp\tr5, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2f6c <__gridxc_mesh1d_MOD_numerov+0x154>\n+\tbne.n\t2f8c <__gridxc_mesh1d_MOD_numerov+0x154>\n \tubfx\tr1, r0, #0, #12\n \tsub.w\tsp, sp, r1\n-\tcbz\tr1, 2f8a <__gridxc_mesh1d_MOD_numerov+0x172>\n+\tcbz\tr1, 2faa <__gridxc_mesh1d_MOD_numerov+0x172>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n \tbic.w\tr1, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n \tbic.w\tr3, r3, #7\n \tsub.w\tr1, sp, r1\n \tadd\tr5, sp, #8\n \tcmp\tr0, r1\n-\tbeq.n\t2fb0 <__gridxc_mesh1d_MOD_numerov+0x198>\n+\tbeq.n\t2fd0 <__gridxc_mesh1d_MOD_numerov+0x198>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2fa2 <__gridxc_mesh1d_MOD_numerov+0x18a>\n+\tbne.n\t2fc2 <__gridxc_mesh1d_MOD_numerov+0x18a>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 2fc0 <__gridxc_mesh1d_MOD_numerov+0x1a8>\n+\tcbz\tr3, 2fe0 <__gridxc_mesh1d_MOD_numerov+0x1a8>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #8\n-\tstr\tr3, [r7, #36]\t@ 0x24\n+\tstr\tr3, [r7, #32]\n \tcmp\tr2, #0\n-\tbeq.w\t3598 <__gridxc_mesh1d_MOD_numerov+0x780>\n+\tbeq.w\t35bc <__gridxc_mesh1d_MOD_numerov+0x784>\n \tmovs\tr3, #0\n \tstrd\tr3, r3, [sp]\n \tmov\tr1, r2\n \tmov\tr2, r3\n \tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n \tldr\tr3, [r7, #52]\t@ 0x34\n \tcmp\tr3, #0\n-\tbeq.w\t3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n+\tbeq.w\t357c <__gridxc_mesh1d_MOD_numerov+0x744>\n \tvldr\td8, [r3]\n \tvldr\td9, [r3, #8]\n \tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tbeq.w\t364a <__gridxc_mesh1d_MOD_numerov+0x832>\n+\tbeq.w\t366e <__gridxc_mesh1d_MOD_numerov+0x836>\n \tcmp\tr4, #0\n-\tble.n\t3028 <__gridxc_mesh1d_MOD_numerov+0x210>\n+\tble.n\t3048 <__gridxc_mesh1d_MOD_numerov+0x210>\n \tlsls\tr3, r4, #3\n \tmovs\tr1, #0\n \tmov\tr2, r3\n-\tmov\tr0, fp\n-\tstr\tr3, [r7, #32]\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tstr\tr3, [r7, #28]\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr.w\tip, [pc, #1172]\t@ 349c <__gridxc_mesh1d_MOD_numerov+0x684>\n-\tldr\tr2, [r7, #32]\n+\tldr.w\tip, [pc, #1124]\t@ 348c <__gridxc_mesh1d_MOD_numerov+0x654>\n+\tldr\tr2, [r7, #28]\n \tadd\tip, pc\n-\tldr\tr0, [r7, #40]\t@ 0x28\n-\tldr.w\tr3, [ip, #396]\t@ 0x18c\n-\tldr.w\tr1, [ip, #372]\t@ 0x174\n+\tldr\tr0, [r7, #36]\t@ 0x24\n+\tldr.w\tr3, [ip, #380]\t@ 0x17c\n+\tldr.w\tr1, [ip, #356]\t@ 0x164\n \tadd\tr1, r3\n-\tldr.w\tr3, [ip, #368]\t@ 0x170\n+\tldr.w\tr3, [ip, #352]\t@ 0x160\n \tadd.w\tr1, r3, r1, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [r7, #68]\t@ 0x44\n-\tcbz\tr3, 305e <__gridxc_mesh1d_MOD_numerov+0x246>\n-\tldr.w\tr3, [pc, #1140]\t@ 34a0 <__gridxc_mesh1d_MOD_numerov+0x688>\n-\tcmp.w\tsl, #0\n+\tcbz\tr3, 307e <__gridxc_mesh1d_MOD_numerov+0x246>\n+\tldr.w\tr3, [pc, #1092]\t@ 3490 <__gridxc_mesh1d_MOD_numerov+0x658>\n+\tcmp.w\tfp, #0\n \tadd\tr3, pc\n-\tldrd\tr2, r1, [r3, #288]\t@ 0x120\n-\tldr.w\tr3, [r3, #316]\t@ 0x13c\n-\tble.n\t305e <__gridxc_mesh1d_MOD_numerov+0x246>\n+\tldrd\tr2, r1, [r3, #280]\t@ 0x118\n+\tldr.w\tr3, [r3, #308]\t@ 0x134\n+\tble.n\t307e <__gridxc_mesh1d_MOD_numerov+0x246>\n \tadd\tr3, r1\n \tldr\tr0, [r7, #68]\t@ 0x44\n-\tmov\tr1, fp\n+\tldr\tr1, [r7, #40]\t@ 0x28\n \tadd.w\tr2, r2, r3, lsl #3\n \tmovs\tr3, #0\n-\tvldmia\tr2!, {d16}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tr0!, {d17}\n-\tcmp\tsl, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr1!, {d16}\n-\tbne.n\t3048 <__gridxc_mesh1d_MOD_numerov+0x230>\n+\tvldmia\tr0!, {d6}\n+\tcmp\tfp, r3\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr1!, {d7}\n+\tbne.n\t3068 <__gridxc_mesh1d_MOD_numerov+0x230>\n \tldr\tr3, [r7, #56]\t@ 0x38\n-\tcbz\tr3, 309c <__gridxc_mesh1d_MOD_numerov+0x284>\n-\tldr.w\tr3, [pc, #1088]\t@ 34a4 <__gridxc_mesh1d_MOD_numerov+0x68c>\n+\tcbz\tr3, 30bc <__gridxc_mesh1d_MOD_numerov+0x284>\n+\tldr.w\tr3, [pc, #1040]\t@ 3494 <__gridxc_mesh1d_MOD_numerov+0x65c>\n \tcmp.w\tr9, #0\n \tadd\tr3, pc\n-\tldrd\tr1, r2, [r3, #328]\t@ 0x148\n-\tldr.w\tr3, [r3, #356]\t@ 0x164\n-\tble.n\t309c <__gridxc_mesh1d_MOD_numerov+0x284>\n+\tldrd\tr1, r2, [r3, #316]\t@ 0x13c\n+\tldr.w\tr3, [r3, #344]\t@ 0x158\n+\tble.n\t30bc <__gridxc_mesh1d_MOD_numerov+0x284>\n \tadd\tr3, r2\n \tldr\tr0, [r7, #56]\t@ 0x38\n-\tldr\tr2, [r7, #40]\t@ 0x28\n+\tldr\tr2, [r7, #36]\t@ 0x24\n \tadd.w\tr1, r1, r3, lsl #3\n \tmovs\tr3, #0\n-\tvldmia\tr1!, {d18}\n+\tvldmia\tr1!, {d5}\n \tadds\tr3, #1\n-\tvldmia\tr0!, {d17}\n+\tvldmia\tr0!, {d6}\n \tcmp\tr9, r3\n-\tvldr\td16, [r2]\n-\tvfma.f64\td16, d18, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t3082 <__gridxc_mesh1d_MOD_numerov+0x26a>\n-\tldr.w\tr3, [pc, #1032]\t@ 34a8 <__gridxc_mesh1d_MOD_numerov+0x690>\n+\tvldr\td7, [r2]\n+\tvmla.f64\td7, d5, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t30a2 <__gridxc_mesh1d_MOD_numerov+0x26a>\n+\tldr\tr3, [pc, #984]\t@ (3498 <__gridxc_mesh1d_MOD_numerov+0x660>)\n \tcmp\tr4, #2\n \tadd\tr3, pc\n-\tldr.w\tr2, [r3, #248]\t@ 0xf8\n-\tldr.w\tr1, [r3, #252]\t@ 0xfc\n-\tstr\tr2, [r7, #32]\n+\tldr.w\tr2, [r3, #244]\t@ 0xf4\n+\tldr.w\tr1, [r3, #248]\t@ 0xf8\n+\tstr\tr2, [r7, #28]\n \tstr\tr1, [r7, #24]\n \tadd.w\tr2, r2, r1, lsl #3\n-\tvldr\td18, [r2, #8]\n-\tvldr\td17, [r2, #16]\n-\tvdiv.f64\td16, d8, d18\n-\tvdiv.f64\td20, d9, d17\n-\tvstr\td16, [r5]\n-\tvstr\td20, [r5, #8]\n-\tble.w\t3754 <__gridxc_mesh1d_MOD_numerov+0x93c>\n+\tvldr\td7, [r2, #8]\n+\tvldr\td5, [r2, #16]\n+\tvdiv.f64\td6, d8, d7\n+\tvdiv.f64\td7, d9, d5\n+\tvstr\td6, [r5]\n+\tvstr\td7, [r5, #8]\n+\tble.w\t377c <__gridxc_mesh1d_MOD_numerov+0x944>\n \tcmp\tr4, #4\n-\tble.w\t376a <__gridxc_mesh1d_MOD_numerov+0x952>\n-\tldr\tr2, [r7, #40]\t@ 0x28\n-\tsubs\tr0, r4, #5\n-\tbic.w\tr0, r0, #1\n-\tvldr\td22, [fp]\n-\tvldr\td21, [fp, #8]\n-\tadds\tr0, #4\n-\tvldr\td19, [pc, #908]\t@ 3478 <__gridxc_mesh1d_MOD_numerov+0x660>\n-\tmov\tr1, fp\n-\tvldr\td24, [r2]\n+\tble.w\t3792 <__gridxc_mesh1d_MOD_numerov+0x95a>\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tsubs\tr1, r4, #5\n+\tldr\tr0, [r7, #40]\t@ 0x28\n+\tbic.w\tr1, r1, #1\n+\tvldr\td5, [pc, #872]\t@ 3468 <__gridxc_mesh1d_MOD_numerov+0x630>\n+\tadds\tr1, #4\n \tmov\tr3, r5\n-\tvldr\td23, [r2, #8]\n \tmov.w\tip, #2\n-\tvldr\td29, [pc, #896]\t@ 3480 <__gridxc_mesh1d_MOD_numerov+0x668>\n-\tvmov.f64\td28, #36\t@ 0x41200000 10.0\n-\tvmov.f64\td27, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td26, #0\t@ 0x40000000 2.0\n-\tvmov.f64\td25, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td3, d22\n-\tvldr\td22, [r1, #16]\n-\tvmov.f64\td18, d27\n-\tvmov.f64\td6, d26\n-\tvfma.f64\td18, d24, d19\n-\tvfma.f64\td6, d23, d29\n-\tvmov.f64\td4, d22\n-\tvldr\td24, [r2, #16]\n-\tvfma.f64\td4, d21, d28\n-\tvmov.f64\td7, d25\n-\tvmov.f64\td5, d21\n-\tvldr\td21, [r1, #24]\n-\tvfms.f64\td7, d24, d19\n+\tvldr\td0, [r2]\n+\tvmov.f64\td9, #36\t@ 0x41200000 10.0\n+\tvldr\td1, [r2, #8]\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvldr\td2, [r0]\n+\tvmov.f64\td11, #0\t@ 0x40000000 2.0\n+\tvldr\td3, [r0, #8]\n+\tvldr\td8, [pc, #840]\t@ 3470 <__gridxc_mesh1d_MOD_numerov+0x638>\n+\tvmov.f64\td10, d2\n+\tvmov.f64\td2, d4\n+\tadds\tr0, #16\n+\tvmov.f64\td13, d4\n+\tadds\tr2, #16\n \tadds\tr3, #16\n-\tvmov.f64\td17, d27\n-\tvmov.f64\td31, d26\n-\tvfma.f64\td17, d23, d19\n-\tvfma.f64\td31, d24, d29\n-\tvadd.f64\td5, d21, d5\n-\tvldr\td23, [r2, #24]\n-\tvmul.f64\td18, d18, d16\n-\tvfma.f64\td5, d22, d28\n-\tvmov.f64\td30, d25\n \tadd.w\tip, ip, #2\n-\tvfms.f64\td30, d23, d19\n-\tadds\tr1, #16\n-\tvadd.f64\td4, d4, d3\n-\tadds\tr2, #16\n-\tcmp\tr0, ip\n-\tvmul.f64\td17, d17, d20\n-\tvfma.f64\td18, d4, d19\n-\tvfma.f64\td17, d5, d19\n-\tvfma.f64\td18, d6, d20\n-\tvdiv.f64\td16, d18, d7\n-\tvfma.f64\td17, d16, d31\n-\tvstr\td16, [r3]\n-\tvdiv.f64\td20, d17, d30\n-\tvstr\td20, [r3, #8]\n-\tbne.n\t3110 <__gridxc_mesh1d_MOD_numerov+0x2f8>\n+\tvnmls.f64\td2, d0, d5\n+\tcmp\tr1, ip\n+\tvnmls.f64\td13, d1, d5\n+\tvmul.f64\td0, d2, d6\n+\tvldr\td2, [r0]\n+\tvmul.f64\td13, d13, d7\n+\tvmov.f64\td6, d2\n+\tvmla.f64\td6, d3, d9\n+\tvadd.f64\td6, d6, d10\n+\tvmov.f64\td10, d3\n+\tvldr\td3, [r0, #8]\n+\tvmla.f64\td0, d6, d5\n+\tvmov.f64\td6, d11\n+\tvmla.f64\td6, d1, d8\n+\tvadd.f64\td10, d3, d10\n+\tvmla.f64\td10, d2, d9\n+\tvldr\td1, [r2, #8]\n+\tvmla.f64\td0, d6, d7\n+\tvmov.f64\td7, d4\n+\tvmla.f64\td13, d10, d5\n+\tvmov.f64\td10, d4\n+\tvmls.f64\td10, d1, d5\n+\tvmov.f64\td12, d0\n+\tvldr\td0, [r2]\n+\tvmls.f64\td7, d0, d5\n+\tvdiv.f64\td6, d12, d7\n+\tvmov.f64\td7, d11\n+\tvmla.f64\td7, d0, d8\n+\tvmla.f64\td13, d7, d6\n+\tvstr\td6, [r3]\n+\tvdiv.f64\td7, d13, d10\n+\tvstr\td7, [r3, #8]\n+\tbne.n\t312a <__gridxc_mesh1d_MOD_numerov+0x2f2>\n \tldr\tr3, [r7, #40]\t@ 0x28\n-\tlsls\tr1, r0, #3\n-\tadd.w\tip, fp, r1\n-\tvldr\td18, [pc, #716]\t@ 3478 <__gridxc_mesh1d_MOD_numerov+0x660>\n-\tadds\tr2, r3, r1\n-\tvldr\td27, [pc, #716]\t@ 3480 <__gridxc_mesh1d_MOD_numerov+0x668>\n-\tadd\tr1, r5\n-\tvmov.f64\td26, #36\t@ 0x41200000 10.0\n-\tvmov.f64\td25, #240\t@ 0xbf800000 -1.0\n-\tvmov.f64\td24, #0\t@ 0x40000000 2.0\n-\tvmov.f64\td23, #112\t@ 0x3f800000 1.0\n-\tvldr\td20, [r2, #-16]\n-\tvmov.f64\td16, d25\n-\tvldr\td17, [r1, #-16]\n+\tlsls\tr2, r1, #3\n+\tvldr\td5, [pc, #672]\t@ 3468 <__gridxc_mesh1d_MOD_numerov+0x630>\n+\tvmov.f64\td9, #36\t@ 0x41200000 10.0\n+\tadd.w\tip, r3, r2\n+\tldr\tr3, [r7, #36]\t@ 0x24\n+\tvldr\td10, [pc, #668]\t@ 3470 <__gridxc_mesh1d_MOD_numerov+0x638>\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tadds\tr0, r3, r2\n+\tadd\tr2, r5\n+\tvmov.f64\td8, #0\t@ 0x40000000 2.0\n \tmov\tr3, ip\n-\tvldr\td21, [r2, #-8]\n-\tadds\tr0, #1\n-\tvfma.f64\td16, d20, d18\n-\tvmov.f64\td20, d24\n-\tvldr\td22, [r3, #-16]\n+\tvldr\td6, [ip]\n+\tvldr\td1, [r0, #-16]\n+\tadds\tr1, #1\n+\tvldr\td3, [r2, #-16]\n \tadd.w\tip, ip, #8\n-\tvfma.f64\td20, d21, d27\n-\tvldr\td21, [r3, #-8]\n-\tvldr\td19, [r1, #-8]\n-\tadds\tr2, #8\n-\tcmp\tr4, r0\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [ip, #-8]\n-\tvadd.f64\td17, d17, d22\n-\tvfma.f64\td17, d21, d26\n-\tvfma.f64\td16, d17, d18\n-\tvldr\td17, [r2, #-8]\n-\tvfma.f64\td16, d20, d19\n-\tvmov.f64\td19, d23\n-\tvfms.f64\td19, d17, d18\n-\tvdiv.f64\td17, d16, d19\n-\tvstmia\tr1!, {d17}\n-\tbgt.n\t31c6 <__gridxc_mesh1d_MOD_numerov+0x3ae>\n-\tldr\tr3, [pc, #640]\t@ (34ac <__gridxc_mesh1d_MOD_numerov+0x694>)\n+\tvldr\td2, [r3, #-16]\n+\tcmp\tr4, r1\n+\tvldr\td7, [r3, #-8]\n+\tmov\tr3, r0\n+\tvldr\td11, [r2, #-8]\n+\tadd.w\tr0, r0, #8\n+\tvadd.f64\td6, d6, d2\n+\tvmla.f64\td6, d7, d9\n+\tvmov.f64\td7, d4\n+\tvldr\td2, [r3, #-8]\n+\tvldr\td0, [r3]\n+\tvnmls.f64\td7, d1, d5\n+\tvmov.f64\td1, d8\n+\tvmla.f64\td1, d2, d10\n+\tvmov.f64\td2, d4\n+\tvmls.f64\td2, d0, d5\n+\tvmul.f64\td7, d7, d3\n+\tvmla.f64\td7, d6, d5\n+\tvmla.f64\td7, d1, d11\n+\tvdiv.f64\td6, d7, d2\n+\tvstmia\tr2!, {d6}\n+\tbgt.n\t31e2 <__gridxc_mesh1d_MOD_numerov+0x3aa>\n+\tldr\tr3, [pc, #592]\t@ (349c <__gridxc_mesh1d_MOD_numerov+0x664>)\n \tadd\tr3, pc\n-\tldr.w\tr3, [r3, #276]\t@ 0x114\n+\tldr.w\tr3, [r3, #272]\t@ 0x110\n \tstr\tr3, [r7, #20]\n \tldr\tr2, [r7, #24]\n \tmov\tr0, r5\n \tldr.w\tip, [r7, #52]\t@ 0x34\n \tadds\tr1, r3, r2\n-\tldr\tr3, [r7, #32]\n+\tldr\tr3, [r7, #28]\n \tstr\tr5, [r7, #4]\n \tadd.w\tr1, r3, r1, lsl #3\n \tmovs\tr3, #0\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tmov\tr2, r3\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr1!, {d6}\n \tadds\tr3, #1\n \tcmp\tr4, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tip!, {d16}\n-\tbne.n\t3246 <__gridxc_mesh1d_MOD_numerov+0x42e>\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tip!, {d7}\n+\tbne.n\t3266 <__gridxc_mesh1d_MOD_numerov+0x42e>\n \tldr\tr3, [r7, #60]\t@ 0x3c\n \tcmp\tr3, #0\n-\tbeq.w\t343e <__gridxc_mesh1d_MOD_numerov+0x626>\n-\tldr.w\tlr, [r7, #40]\t@ 0x28\n-\tmov\tr9, fp\n+\tbeq.w\t34a4 <__gridxc_mesh1d_MOD_numerov+0x66c>\n \tmov\tip, r8\n-\tmov\tfp, r8\n \tmov\tr0, r5\n \tmovs\tr1, #0\n-\tvldmia\tlr!, {d18}\n+\tldrd\tlr, r9, [r7, #36]\t@ 0x24\n+\tstr.w\tr8, [r7, #40]\t@ 0x28\n+\tvldmia\tlr!, {d5}\n \tcmp\tr2, r1\n-\tvldmia\tr0!, {d17}\n+\tvldmia\tr0!, {d6}\n \tadd.w\tr1, r1, #1\n-\tvldmia\tr9!, {d16}\n-\tvfma.f64\td16, d18, d17\n-\tvstmia\tip!, {d16}\n-\tbne.n\t3274 <__gridxc_mesh1d_MOD_numerov+0x45c>\n+\tvldmia\tr9!, {d7}\n+\tvmla.f64\td7, d5, d6\n+\tvstmia\tip!, {d7}\n+\tbne.n\t3294 <__gridxc_mesh1d_MOD_numerov+0x45c>\n \tcmp\tr4, #2\n-\tble.n\t3370 <__gridxc_mesh1d_MOD_numerov+0x558>\n+\tble.n\t3394 <__gridxc_mesh1d_MOD_numerov+0x55c>\n \tsubs\tr0, r4, #1\n \tcmp\tr4, #5\n-\tble.w\t376e <__gridxc_mesh1d_MOD_numerov+0x956>\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tble.w\t3796 <__gridxc_mesh1d_MOD_numerov+0x95e>\n+\tldr\tr2, [r7, #32]\n \tmovs\tr3, #3\n-\tldr\tr1, [r7, #4]\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td25, [r8]\n-\tvldr\td24, [r8, #8]\n-\tvldr\td23, [r5]\n-\tvldr\td22, [r5, #8]\n-\tvldr\td21, [pc, #464]\t@ 3488 <__gridxc_mesh1d_MOD_numerov+0x670>\n-\tvldr\td16, [fp, #16]\n-\tadds\tr2, #24\n-\tvldr\td19, [r1, #16]\n-\tadd.w\tip, r3, #4\n+\tldr\tr1, [r7, #40]\t@ 0x28\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n+\tldr.w\tip, [r7, #4]\n+\tvldr\td6, [r8]\n+\tvldr\td3, [r8, #8]\n+\tvldr\td0, [r5]\n+\tvldr\td7, [r5, #8]\n+\tvldr\td1, [pc, #412]\t@ 3478 <__gridxc_mesh1d_MOD_numerov+0x640>\n+\tvldr\td4, [r1, #16]\n \tadds\tr1, #24\n-\tadd.w\tfp, fp, #24\n-\tvsub.f64\td18, d16, d25\n-\tvldr\td25, [fp]\n-\tvsub.f64\td27, d19, d23\n-\tvldr\td23, [r1]\n+\tvldr\td5, [ip, #16]\n+\tadd.w\tip, ip, #24\n+\tadds\tr2, #24\n+\tadd.w\tlr, r3, #4\n+\tvsub.f64\td6, d4, d6\n \tadds\tr3, #3\n-\tcmp\tip, r0\n-\tvsub.f64\td17, d25, d24\n-\tvldr\td24, [fp, #8]\n-\tvsub.f64\td26, d23, d22\n-\tvldr\td22, [r1, #8]\n-\tvmul.f64\td18, d18, d21\n-\tvsub.f64\td16, d24, d16\n-\tvfma.f64\td18, d27, d20\n-\tvsub.f64\td19, d22, d19\n-\tvmul.f64\td17, d17, d21\n-\tvfma.f64\td17, d26, d20\n-\tvmul.f64\td16, d16, d21\n-\tvfma.f64\td16, d19, d20\n-\tvstr\td18, [r2, #-16]\n-\tvstr\td17, [r2, #-8]\n-\tvstr\td16, [r2]\n-\tblt.n\t32ba <__gridxc_mesh1d_MOD_numerov+0x4a2>\n+\tvsub.f64\td0, d5, d0\n+\tcmp\tlr, r0\n+\tvmul.f64\td6, d6, d1\n+\tvmla.f64\td6, d0, d2\n+\tvldr\td0, [ip]\n+\tvsub.f64\td7, d0, d7\n+\tvmul.f64\td8, d7, d2\n+\tvldr\td7, [ip, #8]\n+\tvstr\td6, [r2, #-16]\n+\tvldr\td6, [r1]\n+\tvsub.f64\td5, d7, d5\n+\tvsub.f64\td3, d6, d3\n+\tvmul.f64\td5, d5, d2\n+\tvmla.f64\td8, d3, d1\n+\tvldr\td3, [r1, #8]\n+\tvsub.f64\td4, d3, d4\n+\tvmla.f64\td5, d4, d1\n+\tvstr\td8, [r2, #-8]\n+\tvstr\td5, [r2]\n+\tblt.n\t32de <__gridxc_mesh1d_MOD_numerov+0x4a6>\n \tadd.w\tr1, r3, #536870912\t@ 0x20000000\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr2, [r7, #32]\n \tsubs\tr1, #3\n-\tvldr\td20, [pc, #348]\t@ 3488 <__gridxc_mesh1d_MOD_numerov+0x670>\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [pc, #296]\t@ 3478 <__gridxc_mesh1d_MOD_numerov+0x640>\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n \tlsls\tr1, r1, #3\n \tadd.w\tip, r1, #8\n \tadds\tr0, r5, r1\n \tadd\tip, r2\n \tadd\tr1, r8\n-\tmov\tr2, r1\n-\tvldr\td16, [r1, #16]\n+\tmov\tr2, r0\n+\tvldr\td7, [r0, #16]\n \tadds\tr3, #1\n-\tadds\tr1, #8\n+\tadds\tr0, #8\n \tcmp\tr3, r4\n-\tvldr\td17, [r2]\n-\tmov\tr2, r0\n-\tadd.w\tr0, r0, #8\n-\tvsub.f64\td16, d16, d17\n-\tvldr\td18, [r2]\n-\tvldr\td17, [r0, #8]\n-\tvsub.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d20\n-\tvfma.f64\td16, d17, d19\n-\tvstmia\tip!, {d16}\n-\tble.n\t333c <__gridxc_mesh1d_MOD_numerov+0x524>\n-\tvldr\td16, [r8, #8]\n-\tvmov.f64\td21, #32\t@ 0x41000000 8.0\n-\tvldr\td18, [r8]\n-\tvmov.f64\td20, #20\t@ 0x40a00000 5.0\n+\tvldr\td6, [r2]\n+\tmov\tr2, r1\n+\tadd.w\tr1, r1, #8\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td5, [r2]\n+\tvldr\td6, [r1, #8]\n+\tvsub.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d4\n+\tvmla.f64\td7, d6, d3\n+\tvstmia\tip!, {d7}\n+\tble.n\t3360 <__gridxc_mesh1d_MOD_numerov+0x528>\n+\tvldr\td7, [r8, #8]\n+\tvmov.f64\td2, #32\t@ 0x41000000 8.0\n+\tvldr\td6, [r8]\n+\tvmov.f64\td3, #20\t@ 0x40a00000 5.0\n \tlsls\tr3, r4, #3\n-\tvldr\td17, [r8, #16]\n-\tvmul.f64\td16, d16, d21\n+\tvldr\td4, [r8, #16]\n+\tvmul.f64\td7, d7, d2\n \tadd\tr8, r3\n-\tvfma.f64\td16, d18, d20\n-\tldr\tr2, [r7, #36]\t@ 0x24\n-\tvldr\td19, [pc, #228]\t@ 3478 <__gridxc_mesh1d_MOD_numerov+0x660>\n+\tvmla.f64\td7, d6, d3\n+\tldr\tr2, [r7, #32]\n+\tvldr\td5, [pc, #176]\t@ 3468 <__gridxc_mesh1d_MOD_numerov+0x630>\n \tcmp\tr4, #0\n-\tvldr\td23, [r8, #-8]\n+\tvldr\td0, [r8, #-8]\n \tadd\tr3, r2\n-\tvldr\td22, [r8, #-24]\t@ 0xffffffe8\n-\tvldr\td18, [r3, #-16]\n-\tvsub.f64\td17, d17, d16\n-\tvldr\td16, [r8, #-16]\n-\tvmul.f64\td16, d16, d21\n-\tvfma.f64\td16, d23, d20\n-\tvsub.f64\td16, d16, d22\n-\tvfma.f64\td18, d16, d19\n-\tvstr\td18, [r3, #-8]\n-\tvldr\td16, [r2, #8]\n-\tvfma.f64\td16, d17, d19\n-\tldr\tr3, [pc, #228]\t@ (34b0 <__gridxc_mesh1d_MOD_numerov+0x698>)\n+\tvldr\td1, [r8, #-24]\t@ 0xffffffe8\n+\tvldr\td6, [r3, #-16]\n+\tvsub.f64\td4, d4, d7\n+\tvldr\td7, [r8, #-16]\n+\tvmul.f64\td7, d7, d2\n+\tvmla.f64\td7, d0, d3\n+\tvsub.f64\td7, d7, d1\n+\tvmla.f64\td6, d7, d5\n+\tvstr\td6, [r3, #-8]\n+\tvldr\td6, [r2, #8]\n+\tvmla.f64\td6, d4, d5\n+\tldr\tr3, [pc, #176]\t@ (34a0 <__gridxc_mesh1d_MOD_numerov+0x668>)\n \tadd\tr3, pc\n \tldrd\tr0, lr, [r3, #136]\t@ 0x88\n \tldrd\tr8, ip, [r3, #100]\t@ 0x64\n-\tvstr\td16, [r2]\n+\tvstr\td6, [r2]\n \tldr.w\tr2, [r3, #164]\t@ 0xa4\n \tldr.w\tr3, [r3, #128]\t@ 0x80\n-\tble.n\t343e <__gridxc_mesh1d_MOD_numerov+0x626>\n+\tble.n\t34a4 <__gridxc_mesh1d_MOD_numerov+0x66c>\n \tadd.w\tr9, r3, ip\n \tadd\tr2, lr\n \tldrd\tr3, r1, [r7, #20]\n \tadd.w\tr2, r0, r2, lsl #3\n-\tldr.w\tlr, [r7, #36]\t@ 0x24\n-\tvmov.f64\td21, #96\t@ 0x3f000000 0.5\n+\tldr.w\tlr, [r7, #32]\n+\tvmov.f64\td2, #96\t@ 0x3f000000 0.5\n \tadd\tr3, r1\n-\tldr\tr1, [r7, #32]\n+\tldr\tr1, [r7, #28]\n \tmov\tip, r3\n \tldr\tr0, [r7, #60]\t@ 0x3c\n \tadd.w\tr3, r8, r9, lsl #3\n \tadd.w\tip, r1, ip, lsl #3\n \tmovs\tr1, #0\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tadds\tr1, #1\n-\tvldmia\tr5!, {d16}\n+\tvldmia\tr5!, {d7}\n \tcmp\tr4, r1\n-\tvldmia\tr3!, {d20}\n-\tvldmia\tlr!, {d19}\n-\tvmul.f64\td16, d16, d17\n-\tvldmia\tip!, {d18}\n-\tvmul.f64\td16, d16, d21\n-\tvdiv.f64\td17, d16, d20\n-\tvadd.f64\td19, d17, d19\n-\tvdiv.f64\td17, d19, d18\n-\tvstmia\tr0!, {d17}\n-\tbne.n\t340c <__gridxc_mesh1d_MOD_numerov+0x5f4>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tcmp\tr3, #0\n-\tbeq.n\t34d6 <__gridxc_mesh1d_MOD_numerov+0x6be>\n-\tcmp\tr6, #0\n-\tble.w\t3732 <__gridxc_mesh1d_MOD_numerov+0x91a>\n-\tmov\tr0, r3\n-\tlsls\tr2, r6, #3\n-\tmovs\tr1, #0\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tcmp\tr3, #0\n-\tbeq.w\t3680 <__gridxc_mesh1d_MOD_numerov+0x868>\n-\tcmp.w\tsl, #0\n-\tble.n\t346e <__gridxc_mesh1d_MOD_numerov+0x656>\n-\tldr\tr0, [r7, #64]\t@ 0x40\n-\tmov\tr1, r3\n-\tmov.w\tr2, sl, lsl #3\n-\tbl\t0 \n- R_ARM_THM_CALL\tmemcpy\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tcmp\tr3, #0\n-\tbeq.w\t374a <__gridxc_mesh1d_MOD_numerov+0x932>\n-\tb.n\t34b4 <__gridxc_mesh1d_MOD_numerov+0x69c>\n+\tvldmia\tr3!, {d3}\n+\tvldmia\tlr!, {d4}\n+\tvmul.f64\td7, d7, d6\n+\tvldmia\tip!, {d5}\n+\tvmul.f64\td7, d7, d2\n+\tvdiv.f64\td6, d7, d3\n+\tvadd.f64\td4, d6, d4\n+\tvdiv.f64\td6, d4, d5\n+\tvstmia\tr0!, {d6}\n+\tbne.n\t3430 <__gridxc_mesh1d_MOD_numerov+0x5f8>\n+\tb.n\t34a4 <__gridxc_mesh1d_MOD_numerov+0x66c>\n+\tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fb55555\n \t.word\t0xaaaaaaab\n \t.word\t0x3feaaaaa\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x0000064c\n+\t.word\t0x0000061c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000630\n+\t.word\t0x00000600\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000048e\n+\t.word\t0x0000045e\n R_ARM_REL32\t.bss\n-\t.word\t0x0000046c\n+\t.word\t0x0000043c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000436\n+\t.word\t0x00000406\n R_ARM_REL32\t.bss\n-\t.word\t0x00000402\n+\t.word\t0x000003d4\n R_ARM_REL32\t.bss\n-\t.word\t0x0000027e\n+\t.word\t0x0000024e\n R_ARM_REL32\t.bss\n-\t.word\t0x000000e0\n+\t.word\t0x000000ac\n R_ARM_REL32\t.bss\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tcbz\tr3, 34fc <__gridxc_mesh1d_MOD_numerov+0x6c4>\n+\tcmp\tr6, #0\n+\tble.w\t375a <__gridxc_mesh1d_MOD_numerov+0x922>\n+\tmov\tr0, r3\n+\tlsls\tr2, r6, #3\n+\tmovs\tr1, #0\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tldr\tr3, [r7, #68]\t@ 0x44\n+\tcmp\tr3, #0\n+\tbeq.w\t36a4 <__gridxc_mesh1d_MOD_numerov+0x86c>\n+\tcmp.w\tfp, #0\n+\tble.n\t34d2 <__gridxc_mesh1d_MOD_numerov+0x69a>\n+\tldr\tr0, [r7, #64]\t@ 0x40\n+\tmov\tr1, r3\n+\tmov.w\tr2, fp, lsl #3\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemcpy\n+\tldr\tr3, [r7, #56]\t@ 0x38\n+\tcmp\tr3, #0\n+\tbeq.w\t3772 <__gridxc_mesh1d_MOD_numerov+0x93a>\n \tldr\tr0, [r7, #56]\t@ 0x38\n \tmovs\tr3, #1\n \tldr\tr2, [r7, #64]\t@ 0x40\n \tldr\tr1, [r7, #52]\t@ 0x34\n-\tvldmia\tr0!, {d18}\n+\tvldmia\tr0!, {d5}\n \tadds\tr3, #1\n-\tvldmia\tr1!, {d17}\n+\tvldmia\tr1!, {d6}\n \tcmp\tr6, r3\n-\tvldr\td16, [r2]\n-\tvfma.f64\td16, d18, d17\n-\tvstmia\tr2!, {d16}\n-\tbge.n\t34bc <__gridxc_mesh1d_MOD_numerov+0x6a4>\n+\tvldr\td7, [r2]\n+\tvmla.f64\td7, d5, d6\n+\tvstmia\tr2!, {d7}\n+\tbge.n\t34e2 <__gridxc_mesh1d_MOD_numerov+0x6aa>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n \tcmp\tr3, #0\n-\tbeq.n\t3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n+\tbeq.n\t357c <__gridxc_mesh1d_MOD_numerov+0x744>\n \tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tbeq.w\t3690 <__gridxc_mesh1d_MOD_numerov+0x878>\n-\tldr\tr3, [pc, #664]\t@ (3780 <__gridxc_mesh1d_MOD_numerov+0x968>)\n+\tbeq.w\t36b4 <__gridxc_mesh1d_MOD_numerov+0x87c>\n+\tldr\tr3, [pc, #660]\t@ (37a0 <__gridxc_mesh1d_MOD_numerov+0x968>)\n \tmovs\tr1, #56\t@ 0x38\n \tldr\tr2, [r7, #12]\n-\tldr\tr0, [pc, #664]\t@ (3784 <__gridxc_mesh1d_MOD_numerov+0x96c>)\n+\tldr\tr0, [pc, #656]\t@ (37a4 <__gridxc_mesh1d_MOD_numerov+0x96c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [r7, #28]\n \tmov\tr4, sp\n-\tsubs.w\tip, r3, #1\n-\tbpl.n\t35c8 <__gridxc_mesh1d_MOD_numerov+0x7b0>\n+\tsubs.w\tip, sl, #1\n+\tbpl.n\t35ec <__gridxc_mesh1d_MOD_numerov+0x7b4>\n \tmovs\tr3, #0\n \tldr\tr0, [r7, #48]\t@ 0x30\n \tmov\tr2, r3\n \tadd.w\tr1, r7, #88\t@ 0x58\n-\tbl\t29f4 <__gridxc_mesh1d_MOD_integral>\n+\tbl\t29fc <__gridxc_mesh1d_MOD_integral>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n-\tvldr\td17, [r3]\n-\tvdiv.f64\td16, d17, d0\n-\tvsqrt.f64\td17, d16\n+\tvldr\td6, [r3]\n+\tvdiv.f64\td7, d6, d0\n+\tvsqrt.f64\td6, d7\n \tldr\tr3, [r7, #60]\t@ 0x3c\n-\tcbz\tr3, 353a <__gridxc_mesh1d_MOD_numerov+0x722>\n+\tcbz\tr3, 355e <__gridxc_mesh1d_MOD_numerov+0x726>\n \tldr\tr1, [r7, #8]\n \tcmp\tr1, #0\n-\tble.n\t353a <__gridxc_mesh1d_MOD_numerov+0x722>\n+\tble.n\t355e <__gridxc_mesh1d_MOD_numerov+0x726>\n \tmov\tr2, r3\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadds\tr3, #1\n-\tcmp\tr1, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t3528 <__gridxc_mesh1d_MOD_numerov+0x710>\n+\tcmp\tr3, r1\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t354c <__gridxc_mesh1d_MOD_numerov+0x714>\n \tldr\tr3, [r7, #64]\t@ 0x40\n-\tcbz\tr3, 3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n+\tcbz\tr3, 357c <__gridxc_mesh1d_MOD_numerov+0x744>\n \tcmp\tr6, #0\n-\tble.n\t3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n+\tble.n\t357c <__gridxc_mesh1d_MOD_numerov+0x744>\n \tmov\tr2, r3\n \tmovs\tr3, #0\n-\tvldr\td16, [r2]\n+\tvldr\td7, [r2]\n \tadds\tr3, #1\n \tcmp\tr3, r6\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tbne.n\t3546 <__gridxc_mesh1d_MOD_numerov+0x72e>\n-\tldr\tr2, [pc, #556]\t@ (3788 <__gridxc_mesh1d_MOD_numerov+0x970>)\n-\tldr\tr3, [pc, #560]\t@ (378c <__gridxc_mesh1d_MOD_numerov+0x974>)\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n+\tbne.n\t356a <__gridxc_mesh1d_MOD_numerov+0x732>\n+\tldr\tr2, [pc, #552]\t@ (37a8 <__gridxc_mesh1d_MOD_numerov+0x970>)\n+\tldr\tr3, [pc, #556]\t@ (37ac <__gridxc_mesh1d_MOD_numerov+0x974>)\n \tadd\tr2, pc\n \tldr.w\tsp, [r7, #16]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [r7, #492]\t@ 0x1ec\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t3772 <__gridxc_mesh1d_MOD_numerov+0x95a>\n+\tbne.w\t379a <__gridxc_mesh1d_MOD_numerov+0x962>\n \tadd.w\tr7, r7, #500\t@ 0x1f4\n \tmov\tsp, r7\n-\tvpop\t{d8-d9}\n+\tvpop\t{d8-d13}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr4, [r0, #0]\n-\tb.n\t2e7c <__gridxc_mesh1d_MOD_numerov+0x64>\n+\tb.n\t2e9c <__gridxc_mesh1d_MOD_numerov+0x64>\n \tsubs\tr1, #4\n \tadd\tr1, sp\n \tstr\tr0, [r1, #0]\n-\tb.n\t2ee2 <__gridxc_mesh1d_MOD_numerov+0xca>\n+\tb.n\t2f02 <__gridxc_mesh1d_MOD_numerov+0xca>\n \tsubs\tr0, #4\n \tadd.w\tr1, sp, r0\n \tstr\tr0, [r1, #0]\n-\tb.n\t2f18 <__gridxc_mesh1d_MOD_numerov+0x100>\n+\tb.n\t2f38 <__gridxc_mesh1d_MOD_numerov+0x100>\n \tcmp.w\tip, #0\n-\tbeq.w\t2fda <__gridxc_mesh1d_MOD_numerov+0x1c2>\n+\tbeq.w\t2ffa <__gridxc_mesh1d_MOD_numerov+0x1c2>\n \tsubs\tr3, r4, #1\n-\tvmov\ts15, r3\n-\tvldr\td17, [ip]\n+\tvmov\ts14, r3\n+\tvldr\td6, [ip]\n \tadd.w\tr3, r7, #80\t@ 0x50\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s14\n \tmov\tr1, r2\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tstrd\tr2, r2, [sp]\n \tldr\tr0, [r7, #48]\t@ 0x30\n \tbl\t808 <__gridxc_mesh1d_MOD_set_mesh>\n-\tb.n\t2fda <__gridxc_mesh1d_MOD_numerov+0x1c2>\n-\tlsls\tr2, r3, #3\n+\tb.n\t2ffa <__gridxc_mesh1d_MOD_numerov+0x1c2>\n+\tmov.w\tr2, sl, lsl #3\n \tmov\tr1, sp\n \tbic.w\tr3, r2, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tcmp\tr1, r3\n-\tbeq.n\t35ea <__gridxc_mesh1d_MOD_numerov+0x7d2>\n+\tbeq.n\t3610 <__gridxc_mesh1d_MOD_numerov+0x7d8>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t35dc <__gridxc_mesh1d_MOD_numerov+0x7c4>\n+\tbne.n\t3602 <__gridxc_mesh1d_MOD_numerov+0x7ca>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 35fc <__gridxc_mesh1d_MOD_numerov+0x7e4>\n+\tcbz\tr2, 3622 <__gridxc_mesh1d_MOD_numerov+0x7ea>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n \tldr\tr5, [r7, #52]\t@ 0x34\n \tadd\tr1, sp, #8\n \tmov\tr0, r1\n \tmovs\tr3, #0\n \tmov\tr2, r5\n-\tvldmia\tr2!, {d16}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n \tcmp\tip, r3\n-\tvmul.f64\td16, d16, d16\n-\tvstmia\tr0!, {d16}\n-\tbge.n\t3606 <__gridxc_mesh1d_MOD_numerov+0x7ee>\n+\tvmul.f64\td7, d7, d7\n+\tvstmia\tr0!, {d7}\n+\tbge.n\t362c <__gridxc_mesh1d_MOD_numerov+0x7f4>\n \tmovs\tr3, #0\n \tldr\tr0, [r7, #48]\t@ 0x30\n \tmov\tr2, r3\n-\tbl\t29f4 <__gridxc_mesh1d_MOD_integral>\n+\tbl\t29fc <__gridxc_mesh1d_MOD_integral>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n-\tldr\tr2, [r7, #28]\n \tmov\tsp, r4\n-\tvldr\td17, [r3]\n+\tvldr\td6, [r3]\n \tmovs\tr3, #0\n-\tvdiv.f64\td16, d17, d0\n-\tvsqrt.f64\td17, d16\n-\tvldr\td16, [r5]\n+\tvdiv.f64\td7, d6, d0\n+\tvsqrt.f64\td6, d7\n+\tvldr\td7, [r5]\n \tadds\tr3, #1\n-\tcmp\tr2, r3\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr5!, {d16}\n-\tbne.n\t3636 <__gridxc_mesh1d_MOD_numerov+0x81e>\n-\tb.n\t351a <__gridxc_mesh1d_MOD_numerov+0x702>\n+\tcmp\tsl, r3\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr5!, {d7}\n+\tbne.n\t365a <__gridxc_mesh1d_MOD_numerov+0x822>\n+\tb.n\t353e <__gridxc_mesh1d_MOD_numerov+0x706>\n \tvcmp.f64\td8, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t3678 <__gridxc_mesh1d_MOD_numerov+0x860>\n+\tbne.n\t369c <__gridxc_mesh1d_MOD_numerov+0x864>\n \tvcmp.f64\td9, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t3678 <__gridxc_mesh1d_MOD_numerov+0x860>\n-\tldr\tr3, [pc, #288]\t@ (3780 <__gridxc_mesh1d_MOD_numerov+0x968>)\n+\tbne.n\t369c <__gridxc_mesh1d_MOD_numerov+0x864>\n+\tldr\tr3, [pc, #284]\t@ (37a0 <__gridxc_mesh1d_MOD_numerov+0x968>)\n \tmovs\tr1, #44\t@ 0x2c\n \tldr\tr2, [r7, #12]\n-\tldr\tr0, [pc, #296]\t@ (3790 <__gridxc_mesh1d_MOD_numerov+0x978>)\n+\tldr\tr0, [pc, #292]\t@ (37b0 <__gridxc_mesh1d_MOD_numerov+0x978>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [r7, #52]\t@ 0x34\n \tvldr\td8, [r3]\n \tvldr\td9, [r3, #8]\n \tcmp\tr4, #0\n-\tbgt.w\t2ff6 <__gridxc_mesh1d_MOD_numerov+0x1de>\n-\tb.n\t305e <__gridxc_mesh1d_MOD_numerov+0x246>\n+\tbgt.w\t3016 <__gridxc_mesh1d_MOD_numerov+0x1de>\n+\tb.n\t307e <__gridxc_mesh1d_MOD_numerov+0x246>\n \tldr\tr3, [r7, #56]\t@ 0x38\n \tcmp\tr3, #0\n-\tbne.w\t34b4 <__gridxc_mesh1d_MOD_numerov+0x69c>\n+\tbne.w\t34da <__gridxc_mesh1d_MOD_numerov+0x6a2>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n \tcmp\tr3, #0\n-\tbeq.w\t3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n+\tbeq.w\t357c <__gridxc_mesh1d_MOD_numerov+0x744>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n-\tvldr\td16, [r3]\n-\tvcmpe.f64\td16, #0.0\n+\tvldr\td7, [r3]\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbhi.w\t34f4 <__gridxc_mesh1d_MOD_numerov+0x6dc>\n-\tldr\tr3, [pc, #240]\t@ (3794 <__gridxc_mesh1d_MOD_numerov+0x97c>)\n+\tbhi.w\t351a <__gridxc_mesh1d_MOD_numerov+0x6e2>\n+\tldr\tr3, [pc, #236]\t@ (37b4 <__gridxc_mesh1d_MOD_numerov+0x97c>)\n \tadd.w\tr8, r7, #88\t@ 0x58\n-\tvldr\td16, [pc, #204]\t@ 3778 <__gridxc_mesh1d_MOD_numerov+0x960>\n \tmov\tr0, r8\n+\tadd.w\tr5, r7, #432\t@ 0x1b0\n \tadd\tr3, pc\n \tstr\tr3, [r7, #96]\t@ 0x60\n-\tldr\tr3, [pc, #228]\t@ (3798 <__gridxc_mesh1d_MOD_numerov+0x980>)\n-\tadd.w\tr5, r7, #432\t@ 0x1b0\n-\tvstr\td16, [r7, #88]\t@ 0x58\n+\tldr\tr3, [pc, #224]\t@ (37b8 <__gridxc_mesh1d_MOD_numerov+0x980>)\n \tmovs\tr4, #60\t@ 0x3c\n-\tadd\tr3, pc\n+\tmov.w\tr2, #20480\t@ 0x5000\n \tstr.w\tr5, [r7, #156]\t@ 0x9c\n+\tadd\tr3, pc\n+\tstr.w\tr4, [r7, #160]\t@ 0xa0\n \tstr.w\tr3, [r7, #140]\t@ 0x8c\n \tmovs\tr3, #0\n-\tstr.w\tr4, [r7, #160]\t@ 0xa0\n \tstr.w\tr3, [r7, #136]\t@ 0x88\n \tmovs\tr3, #9\n \tstr.w\tr3, [r7, #144]\t@ 0x90\n \tmovw\tr3, #1050\t@ 0x41a\n \tstr\tr3, [r7, #100]\t@ 0x64\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [r7, #88]\t@ 0x58\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #184]\t@ (379c <__gridxc_mesh1d_MOD_numerov+0x984>)\n+\tldr\tr1, [pc, #176]\t@ (37bc <__gridxc_mesh1d_MOD_numerov+0x984>)\n \tmovs\tr2, #34\t@ 0x22\n \tmov\tr0, r8\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tldr\tr1, [r7, #44]\t@ 0x2c\n \tmovs\tr2, #8\n@@ -4999,140 +5027,137 @@\n \tmov\tr2, r4\n \tadd.w\tr5, r7, #80\t@ 0x50\n \tadd.w\tr4, r7, #76\t@ 0x4c\n \tmov\tr0, r5\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_string_trim>\n R_ARM_THM_CALL\t_gfortran_string_trim\n-\tldr\tr3, [pc, #108]\t@ (3780 <__gridxc_mesh1d_MOD_numerov+0x968>)\n+\tldr\tr3, [pc, #100]\t@ (37a0 <__gridxc_mesh1d_MOD_numerov+0x968>)\n \tldr\tr2, [r7, #12]\n \tldrd\tr4, r5, [r7, #76]\t@ 0x4c\n \tldr\tr3, [r2, r3]\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tcmp\tr5, #0\n-\tble.w\t34f4 <__gridxc_mesh1d_MOD_numerov+0x6dc>\n+\tble.w\t351a <__gridxc_mesh1d_MOD_numerov+0x6e2>\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t34f4 <__gridxc_mesh1d_MOD_numerov+0x6dc>\n+\tb.n\t351a <__gridxc_mesh1d_MOD_numerov+0x6e2>\n \tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tbeq.n\t3688 <__gridxc_mesh1d_MOD_numerov+0x870>\n-\tcmp.w\tsl, #0\n-\tble.n\t374a <__gridxc_mesh1d_MOD_numerov+0x932>\n+\tbeq.n\t36ac <__gridxc_mesh1d_MOD_numerov+0x874>\n+\tcmp.w\tfp, #0\n+\tble.n\t3772 <__gridxc_mesh1d_MOD_numerov+0x93a>\n \tldr\tr0, [r7, #64]\t@ 0x40\n \tmov\tr1, r3\n-\tmov.w\tr2, sl, lsl #3\n+\tmov.w\tr2, fp, lsl #3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr\tr3, [r7, #44]\t@ 0x2c\n \tcmp\tr3, #0\n-\tbne.w\t34e4 <__gridxc_mesh1d_MOD_numerov+0x6cc>\n-\tb.n\t3558 <__gridxc_mesh1d_MOD_numerov+0x740>\n-\tldr.w\tr3, [r3, #276]\t@ 0x114\n+\tbne.w\t350a <__gridxc_mesh1d_MOD_numerov+0x6d2>\n+\tb.n\t357c <__gridxc_mesh1d_MOD_numerov+0x744>\n+\tldr.w\tr3, [r3, #272]\t@ 0x110\n \tcmp\tr4, #0\n \tstr\tr3, [r7, #20]\n-\tbgt.w\t3232 <__gridxc_mesh1d_MOD_numerov+0x41a>\n+\tbgt.w\t3252 <__gridxc_mesh1d_MOD_numerov+0x41a>\n \tldr\tr3, [r7, #60]\t@ 0x3c\n \tcmp\tr3, #0\n-\tbne.w\t3370 <__gridxc_mesh1d_MOD_numerov+0x558>\n-\tb.n\t343e <__gridxc_mesh1d_MOD_numerov+0x626>\n-\tmovs\tr0, #2\n-\tb.n\t31a2 <__gridxc_mesh1d_MOD_numerov+0x38a>\n+\tbne.w\t3394 <__gridxc_mesh1d_MOD_numerov+0x55c>\n+\tb.n\t34a4 <__gridxc_mesh1d_MOD_numerov+0x66c>\n+\tmovs\tr1, #2\n+\tb.n\t31c0 <__gridxc_mesh1d_MOD_numerov+0x388>\n \tmovs\tr3, #3\n-\tb.n\t3320 <__gridxc_mesh1d_MOD_numerov+0x508>\n+\tb.n\t3344 <__gridxc_mesh1d_MOD_numerov+0x50c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000292\n+\t.word\t0x0000028c\n R_ARM_REL32\t.LC45\n-\t.word\t0x00000228\n+\t.word\t0x00000224\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000124\n+\t.word\t0x00000120\n R_ARM_REL32\t.LC44\n-\t.word\t0x000000e2\n+\t.word\t0x000000de\n R_ARM_REL32\t.LC46\n-\t.word\t0x000000d6\n+\t.word\t0x000000d2\n R_ARM_REL32\t.LC47\n-\t.word\t0x000000b0\n+\t.word\t0x000000a8\n R_ARM_REL32\t.LC48\n \n-000037a0 <__gridxc_mesh1d_MOD_get_n>:\n+000037c0 <__gridxc_mesh1d_MOD_get_n>:\n __gridxc_mesh1d_MOD_get_n():\n \tpush\t{r3, r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d12}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tvldr\td9, [r3]\n \tmov\tr4, r0\n-\tvldr\td10, [r2]\n+\tvldr\td12, [r2]\n \tmov\tr5, r1\n-\tldr.w\tip, [pc, #176]\t@ 3870 <__gridxc_mesh1d_MOD_get_n+0xd0>\n-\tvmul.f64\td16, d9, d10\n+\tldr.w\tip, [pc, #168]\t@ 3888 <__gridxc_mesh1d_MOD_get_n+0xc8>\n+\tvmul.f64\td7, d9, d12\n \tadd\tip, pc\n-\tvcmpe.f64\td16, #0.0\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t3808 <__gridxc_mesh1d_MOD_get_n+0x68>\n-\tvldr\td16, [r0]\n+\tbls.n\t3826 <__gridxc_mesh1d_MOD_get_n+0x66>\n+\tvldr\td7, [r0]\n \tvldr\td8, [r1]\n-\tvsub.f64\td8, d8, d16\n-\tvmul.f64\td16, d9, d8\n-\tvcmpe.f64\td16, #0.0\n+\tvsub.f64\td8, d8, d7\n+\tvmul.f64\td7, d9, d8\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t3808 <__gridxc_mesh1d_MOD_get_n+0x68>\n-\tvcmp.f64\td9, d10\n+\tbls.n\t3826 <__gridxc_mesh1d_MOD_get_n+0x66>\n+\tvcmp.f64\td9, d12\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t382e <__gridxc_mesh1d_MOD_get_n+0x8e>\n-\tvdiv.f64\td16, d8, d9\n+\tbne.n\t384c <__gridxc_mesh1d_MOD_get_n+0x8c>\n+\tvdiv.f64\td0, d8, d9\n \tvpop\t{d8-d12}\n-\tvcvta.s32.f64\ts15, d16\n-\tvmov\tr0, s15\n-\tpop\t{r3, r4, r5, pc}\n-\tldr\tr3, [pc, #104]\t@ (3874 <__gridxc_mesh1d_MOD_get_n+0xd4>)\n+\tldmia.w\tsp!, {r3, r4, r5, lr}\n+\tb.w\t0 \n+ R_ARM_THM_JUMP24\tlround\n+\tldr\tr3, [pc, #100]\t@ (388c <__gridxc_mesh1d_MOD_get_n+0xcc>)\n \tmovs\tr1, #27\n-\tldr\tr0, [pc, #104]\t@ (3878 <__gridxc_mesh1d_MOD_get_n+0xd8>)\n+\tldr\tr0, [pc, #100]\t@ (3890 <__gridxc_mesh1d_MOD_get_n+0xd0>)\n \tadd\tr0, pc\n \tldr.w\tr3, [ip, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvcmp.f64\td9, d10\n+\tvcmp.f64\td9, d12\n \tvldr\td8, [r5]\n-\tvldr\td16, [r4]\n+\tvldr\td7, [r4]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvsub.f64\td8, d8, d16\n-\tbeq.n\t37f6 <__gridxc_mesh1d_MOD_get_n+0x56>\n-\tvmul.f64\td16, d10, d8\n-\tvsub.f64\td9, d9, d10\n-\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td12, d16, d9\n-\tvdiv.f64\td0, d10, d12\n-\tvadd.f64\td0, d0, d11\n+\tvsub.f64\td8, d8, d7\n+\tbeq.n\t3816 <__gridxc_mesh1d_MOD_get_n+0x56>\n+\tvmul.f64\td7, d12, d8\n+\tvsub.f64\td9, d9, d12\n+\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td11, d7, d9\n+\tvdiv.f64\td0, d12, d11\n+\tvadd.f64\td0, d0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d8, d12\n+\tvdiv.f64\td7, d8, d11\n \tvmov.f64\td8, d0\n-\tvadd.f64\td0, d16, d11\n+\tvadd.f64\td0, d7, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d0, d8\n-\tvpop\t{d8-d12}\n-\tvcvta.s32.f64\ts15, d16\n-\tvmov\tr0, s15\n+\tvdiv.f64\td0, d0, d8\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n \tadds\tr0, #1\n+\tvpop\t{d8-d12}\n \tpop\t{r3, r4, r5, pc}\n-\tnop\n-\t.word\t0x000000a6\n+\t.word\t0x0000009e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000066\n+\t.word\t0x00000060\n R_ARM_REL32\t.LC49\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -72,38 +72,38 @@\n 0x00000450 6e736665 725f6368 61726163 7465725f nsfer_character_\n 0x00000460 77726974 65005f67 666f7274 72616e5f write._gfortran_\n 0x00000470 7472616e 73666572 5f726561 6c5f7772 transfer_real_wr\n 0x00000480 69746500 5f67666f 72747261 6e5f7374 ite._gfortran_st\n 0x00000490 5f777269 74655f64 6f6e6500 5f67666f _write_done._gfo\n 0x000004a0 72747261 6e5f7374 72696e67 5f747269 rtran_string_tri\n 0x000004b0 6d005f5f 67726964 78635f6d 65736831 m.__gridxc_mesh1\n- 0x000004c0 645f4d4f 445f6765 745f6e00 5f5f6772 d_MOD_get_n.__gr\n- 0x000004d0 69647863 5f6d6573 6831645f 4d4f445f idxc_mesh1d_MOD_\n- 0x000004e0 79706e00 5f5f6772 69647863 5f6d6573 ypn.__gridxc_mes\n- 0x000004f0 6831645f 4d4f445f 79703100 5f5f6772 h1d_MOD_yp1.__gr\n- 0x00000500 69647863 5f6d6573 6831645f 4d4f445f idxc_mesh1d_MOD_\n- 0x00000510 78703400 5f5f6772 69647863 5f6d6573 xp4.__gridxc_mes\n- 0x00000520 6831645f 4d4f445f 78703300 5f5f6772 h1d_MOD_xp3.__gr\n- 0x00000530 69647863 5f6d6573 6831645f 4d4f445f idxc_mesh1d_MOD_\n- 0x00000540 78703200 5f5f6772 69647863 5f6d6573 xp2.__gridxc_mes\n- 0x00000550 6831645f 4d4f445f 78703100 5f5f6772 h1d_MOD_xp1.__gr\n- 0x00000560 69647863 5f6d6573 6831645f 4d4f445f idxc_mesh1d_MOD_\n- 0x00000570 7869005f 5f677269 6478635f 6d657368 xi.__gridxc_mesh\n- 0x00000580 31645f4d 4f445f73 71727870 005f5f67 1d_MOD_sqrxp.__g\n- 0x00000590 72696478 635f6d65 73683164 5f4d4f44 ridxc_mesh1d_MOD\n- 0x000005a0 5f733200 5f5f6772 69647863 5f6d6573 _s2.__gridxc_mes\n- 0x000005b0 6831645f 4d4f445f 7331005f 5f677269 h1d_MOD_s1.__gri\n- 0x000005c0 6478635f 6d657368 31645f4d 4f445f73 dxc_mesh1d_MOD_s\n- 0x000005d0 30005f5f 67726964 78635f6d 65736831 0.__gridxc_mesh1\n- 0x000005e0 645f4d4f 445f6d65 73685f74 79706500 d_MOD_mesh_type.\n- 0x000005f0 5f5f6772 69647863 5f6d6573 6831645f __gridxc_mesh1d_\n- 0x00000600 4d4f445f 69766563 005f5f67 72696478 MOD_ivec.__gridx\n- 0x00000610 635f6d65 73683164 5f4d4f44 5f696e74 c_mesh1d_MOD_int\n- 0x00000620 6572706f 6c617469 6f6e5f6d 6574686f erpolation_metho\n- 0x00000630 64005f5f 67726964 78635f6d 65736831 d.__gridxc_mesh1\n- 0x00000640 645f4d4f 445f6465 66696e65 645f6d65 d_MOD_defined_me\n- 0x00000650 7368005f 5f677269 6478635f 6d657368 sh.__gridxc_mesh\n- 0x00000660 31645f4d 4f445f64 005f5f67 72696478 1d_MOD_d.__gridx\n- 0x00000670 635f6d65 73683164 5f4d4f44 5f62005f c_mesh1d_MOD_b._\n- 0x00000680 5f677269 6478635f 6d657368 31645f4d _gridxc_mesh1d_M\n- 0x00000690 4f445f61 6100 OD_aa.\n+ 0x000004c0 645f4d4f 445f6765 745f6e00 6c726f75 d_MOD_get_n.lrou\n+ 0x000004d0 6e64005f 5f677269 6478635f 6d657368 nd.__gridxc_mesh\n+ 0x000004e0 31645f4d 4f445f79 706e005f 5f677269 1d_MOD_ypn.__gri\n+ 0x000004f0 6478635f 6d657368 31645f4d 4f445f79 dxc_mesh1d_MOD_y\n+ 0x00000500 7031005f 5f677269 6478635f 6d657368 p1.__gridxc_mesh\n+ 0x00000510 31645f4d 4f445f78 7034005f 5f677269 1d_MOD_xp4.__gri\n+ 0x00000520 6478635f 6d657368 31645f4d 4f445f78 dxc_mesh1d_MOD_x\n+ 0x00000530 7033005f 5f677269 6478635f 6d657368 p3.__gridxc_mesh\n+ 0x00000540 31645f4d 4f445f78 7032005f 5f677269 1d_MOD_xp2.__gri\n+ 0x00000550 6478635f 6d657368 31645f4d 4f445f78 dxc_mesh1d_MOD_x\n+ 0x00000560 7031005f 5f677269 6478635f 6d657368 p1.__gridxc_mesh\n+ 0x00000570 31645f4d 4f445f78 69005f5f 67726964 1d_MOD_xi.__grid\n+ 0x00000580 78635f6d 65736831 645f4d4f 445f7371 xc_mesh1d_MOD_sq\n+ 0x00000590 72787000 5f5f6772 69647863 5f6d6573 rxp.__gridxc_mes\n+ 0x000005a0 6831645f 4d4f445f 7332005f 5f677269 h1d_MOD_s2.__gri\n+ 0x000005b0 6478635f 6d657368 31645f4d 4f445f73 dxc_mesh1d_MOD_s\n+ 0x000005c0 31005f5f 67726964 78635f6d 65736831 1.__gridxc_mesh1\n+ 0x000005d0 645f4d4f 445f7330 005f5f67 72696478 d_MOD_s0.__gridx\n+ 0x000005e0 635f6d65 73683164 5f4d4f44 5f6d6573 c_mesh1d_MOD_mes\n+ 0x000005f0 685f7479 7065005f 5f677269 6478635f h_type.__gridxc_\n+ 0x00000600 6d657368 31645f4d 4f445f69 76656300 mesh1d_MOD_ivec.\n+ 0x00000610 5f5f6772 69647863 5f6d6573 6831645f __gridxc_mesh1d_\n+ 0x00000620 4d4f445f 696e7465 72706f6c 6174696f MOD_interpolatio\n+ 0x00000630 6e5f6d65 74686f64 005f5f67 72696478 n_method.__gridx\n+ 0x00000640 635f6d65 73683164 5f4d4f44 5f646566 c_mesh1d_MOD_def\n+ 0x00000650 696e6564 5f6d6573 68005f5f 67726964 ined_mesh.__grid\n+ 0x00000660 78635f6d 65736831 645f4d4f 445f6400 xc_mesh1d_MOD_d.\n+ 0x00000670 5f5f6772 69647863 5f6d6573 6831645f __gridxc_mesh1d_\n+ 0x00000680 4d4f445f 62005f5f 67726964 78635f6d MOD_b.__gridxc_m\n+ 0x00000690 65736831 645f4d4f 445f6161 00 esh1d_MOD_aa.\n \n"}]}, {"source1": "mesh3d.F90.o", "source2": "mesh3d.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 67052 (bytes into file)\n+ Start of section headers: 66628 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 14\n Section header string table index: 13\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,23 +1,23 @@\n-There are 14 section headers, starting at offset 0x105ec:\n+There are 14 section headers, starting at offset 0x10444:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 0057fc 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 00fbd4 000980 08 I 11 1 4\n- [ 3] .data PROGBITS 00000000 005838 008070 00 WA 0 0 8\n- [ 4] .bss NOBITS 00000000 00d8a8 000050 00 WA 0 0 4\n- [ 5] .rodata.str1.4 PROGBITS 00000000 00d8a8 000d4d 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 00e5f8 00027c 00 A 0 0 4\n- [ 7] .data.rel PROGBITS 00000000 00e874 000038 00 WA 0 0 4\n- [ 8] .rel.data.rel REL 00000000 010554 000020 08 I 11 7 4\n- [ 9] .note.GNU-stack PROGBITS 00000000 00e8ac 000000 00 0 0 1\n- [10] .ARM.attributes ARM_ATTRIBUTES 00000000 00e8ac 000033 00 0 0 1\n- [11] .symtab SYMTAB 00000000 00e8e0 000a60 10 12 126 4\n- [12] .strtab STRTAB 00000000 00f340 000894 00 0 0 1\n- [13] .shstrtab STRTAB 00000000 010574 000075 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 00547c 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 00f8ac 000b00 08 I 11 1 4\n+ [ 3] .data PROGBITS 00000000 0054b8 008070 00 WA 0 0 8\n+ [ 4] .bss NOBITS 00000000 00d528 000050 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 00d528 000d4d 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 00e278 00027c 00 A 0 0 4\n+ [ 7] .data.rel PROGBITS 00000000 00e4f4 000038 00 WA 0 0 4\n+ [ 8] .rel.data.rel REL 00000000 0103ac 000020 08 I 11 7 4\n+ [ 9] .note.GNU-stack PROGBITS 00000000 00e52c 000000 00 0 0 1\n+ [10] .ARM.attributes ARM_ATTRIBUTES 00000000 00e52c 00002d 00 0 0 1\n+ [11] .symtab SYMTAB 00000000 00e55c 000a90 10 12 126 4\n+ [12] .strtab STRTAB 00000000 00efec 0008bf 00 0 0 1\n+ [13] .shstrtab STRTAB 00000000 0103cc 000075 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,169 +1,172 @@\n \n-Symbol table '.symtab' contains 166 entries:\n+Symbol table '.symtab' contains 169 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 5: 00000044 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 6: 00000060 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 7: 000000b4 0 NOTYPE LOCAL DEFAULT 5 .LC3\n- 8: 00000041 528 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_initdistr.part.0\n- 9: 00000208 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 8: 00000041 456 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_initdistr.part.0\n+ 9: 000001dc 0 NOTYPE LOCAL DEFAULT 1 $d\n 10: 000000ec 0 NOTYPE LOCAL DEFAULT 5 .LC4\n- 11: 00000250 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 00000251 908 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0\n- 13: 000005b8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 14: 000005dc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 15: 000005dd 856 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0\n- 16: 00000910 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 11: 00000208 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 00000209 924 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0\n+ 13: 00000580 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 14: 000005a4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 15: 000005a5 864 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0\n+ 16: 000008e0 0 NOTYPE LOCAL DEFAULT 1 $d\n 17: 00000128 0 NOTYPE LOCAL DEFAULT 5 .LC5\n 18: 00000168 0 NOTYPE LOCAL DEFAULT 5 .LC6\n- 19: 00000934 0 NOTYPE LOCAL DEFAULT 1 $t\n- 20: 00000935 1444 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0\n- 21: 00000eb8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 22: 00000ed8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 23: 00000ed9 382 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0\n+ 19: 00000904 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 20: 00000905 1056 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0\n+ 21: 00000cd8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 22: 00000cf0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 23: 00000d25 200 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0\n 24: 0000019c 0 NOTYPE LOCAL DEFAULT 5 .LC7\n 25: 000001d8 0 NOTYPE LOCAL DEFAULT 5 .LC8\n 26: 00000214 0 NOTYPE LOCAL DEFAULT 5 .LC9\n 27: 00000258 0 NOTYPE LOCAL DEFAULT 5 .LC10\n 28: 00000294 0 NOTYPE LOCAL DEFAULT 5 .LC11\n 29: 000002e8 0 NOTYPE LOCAL DEFAULT 5 .LC12\n 30: 00000318 0 NOTYPE LOCAL DEFAULT 5 .LC13\n 31: 00000360 0 NOTYPE LOCAL DEFAULT 5 .LC14\n 32: 00000390 0 NOTYPE LOCAL DEFAULT 5 .LC15\n 33: 000003dc 0 NOTYPE LOCAL DEFAULT 5 .LC16\n 34: 00000418 0 NOTYPE LOCAL DEFAULT 5 .LC17\n 35: 00000420 0 NOTYPE LOCAL DEFAULT 5 .LC18\n 36: 00000448 0 NOTYPE LOCAL DEFAULT 5 .LC19\n- 37: 00001059 5232 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_reducedata.isra.0\n- 38: 000017ec 0 NOTYPE LOCAL DEFAULT 1 $d\n- 39: 00001814 0 NOTYPE LOCAL DEFAULT 1 $t\n- 40: 000022c8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 41: 000022f4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 42: 000024b0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 43: 00000498 0 NOTYPE LOCAL DEFAULT 5 .LC20\n- 44: 000004c0 0 NOTYPE LOCAL DEFAULT 5 .LC21\n- 45: 000024c8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 46: 000024c9 324 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0\n- 47: 000025f0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 48: 0000260c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 49: 00002828 0 NOTYPE LOCAL DEFAULT 1 $d\n- 50: 0000260d 560 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_samemeshdistr.localalias\n- 51: 0000283c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 52: 000028b4 0 NOTYPE LOCAL DEFAULT 1 $d\n- 53: 000004f0 0 NOTYPE LOCAL DEFAULT 5 .LC22\n- 54: 00000528 0 NOTYPE LOCAL DEFAULT 5 .LC23\n- 55: 00000530 0 NOTYPE LOCAL DEFAULT 5 .LC24\n- 56: 000028bc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 57: 00002af0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 58: 000028bd 616 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_freemeshtask.localalias\n- 59: 00000580 0 NOTYPE LOCAL DEFAULT 5 .LC25\n- 60: 000005ac 0 NOTYPE LOCAL DEFAULT 5 .LC26\n- 61: 000005b4 0 NOTYPE LOCAL DEFAULT 5 .LC27\n- 62: 00002b24 0 NOTYPE LOCAL DEFAULT 1 $t\n- 63: 00002cb8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 64: 00002b25 468 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_freemeshdistr.localalias\n- 65: 00000604 0 NOTYPE LOCAL DEFAULT 5 .LC28\n- 66: 00000630 0 NOTYPE LOCAL DEFAULT 5 .LC29\n- 67: 00002cf8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 68: 00002cf9 700 FUNC LOCAL DEFAULT 1 __gridxc_mesh3d_MOD_reducedistr\n- 69: 00002f88 0 NOTYPE LOCAL DEFAULT 1 $d\n- 70: 0000066c 0 NOTYPE LOCAL DEFAULT 5 .LC30\n- 71: 00000694 0 NOTYPE LOCAL DEFAULT 5 .LC31\n- 72: 000006c8 0 NOTYPE LOCAL DEFAULT 5 .LC32\n- 73: 000006fc 0 NOTYPE LOCAL DEFAULT 5 .LC33\n- 74: 0000072c 0 NOTYPE LOCAL DEFAULT 5 .LC34\n- 75: 00000760 0 NOTYPE LOCAL DEFAULT 5 .LC35\n- 76: 000007b4 0 NOTYPE LOCAL DEFAULT 5 .LC36\n- 77: 000007f8 0 NOTYPE LOCAL DEFAULT 5 .LC37\n- 78: 00000838 0 NOTYPE LOCAL DEFAULT 5 .LC38\n- 79: 0000088c 0 NOTYPE LOCAL DEFAULT 5 .LC39\n- 80: 000008cc 0 NOTYPE LOCAL DEFAULT 5 .LC40\n- 81: 0000090c 0 NOTYPE LOCAL DEFAULT 5 .LC42\n- 82: 00000930 0 NOTYPE LOCAL DEFAULT 5 .LC44\n- 83: 00000964 0 NOTYPE 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__gridxc_mesh3d_MOD_storedmeshdistr\n-000028b4 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000028b8 0000921a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n-000029f4 00008d0a R_ARM_THM_CALL 00000000 free\n-00002a06 00008d0a R_ARM_THM_CALL 00000000 free\n-00002a14 00008d0a R_ARM_THM_CALL 00000000 free\n-00002a20 00008d0a R_ARM_THM_CALL 00000000 free\n-00002aea 00008e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00002af0 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002af4 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002af8 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002afc 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002b00 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002b04 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002b08 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002b0c 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002b10 00003503 R_ARM_REL32 000004f0 .LC22\n-00002b14 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002b18 00003603 R_ARM_REL32 00000528 .LC23\n-00002b1c 00002303 R_ARM_REL32 00000420 .LC18\n-00002b20 00003703 R_ARM_REL32 00000530 .LC24\n-00002c8e 00008d0a R_ARM_THM_CALL 00000000 free\n-00002cb0 00008e0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00002cb4 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002cb8 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002cbc 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002cc0 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002cc4 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002cc8 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002ccc 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002cd0 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002cd4 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002cd8 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002cdc 00003b03 R_ARM_REL32 00000580 .LC25\n-00002ce0 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00002ce4 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002ce8 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002cec 00003c03 R_ARM_REL32 000005ac .LC26\n-00002cf0 00002303 R_ARM_REL32 00000420 .LC18\n-00002cf4 00003d03 R_ARM_REL32 000005b4 .LC27\n-00002f88 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002f8c 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002f90 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002f94 00004103 R_ARM_REL32 00000604 .LC28\n-00002f98 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002f9c 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002fa0 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002fa4 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002fa8 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002fac 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00002fb0 00004203 R_ARM_REL32 00000630 .LC29\n-00003180 0000970a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000031aa 0000980a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-000031b0 00008d0a R_ARM_THM_CALL 00000000 free\n-00003248 0000970a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000033ac 0000820a R_ARM_THM_CALL 00000000 malloc\n-00003638 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000363c 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003640 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003644 0000881a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n-00003648 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000364c 00004603 R_ARM_REL32 0000066c .LC30\n-00003650 00004703 R_ARM_REL32 00000694 .LC31\n-00003654 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00003658 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-0000365c 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003660 0000921a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n-00003664 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00003668 00004803 R_ARM_REL32 000006c8 .LC32\n-0000366c 00004a03 R_ARM_REL32 0000072c .LC34\n-00003670 00004903 R_ARM_REL32 000006fc .LC33\n-00003674 00007803 R_ARM_REL32 00000000 .rodata\n-00003702 0000820a R_ARM_THM_CALL 00000000 malloc\n-000037d4 0000990a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-000038c2 00009a0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n-000039ea 00008d0a R_ARM_THM_CALL 00000000 free\n-00003a40 00008d0a R_ARM_THM_CALL 00000000 free\n-00003bc8 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003bcc 00005603 R_ARM_REL32 00000a24 .LC48\n-00003bd0 00005003 R_ARM_REL32 000008cc .LC40\n-00003bd4 00000103 R_ARM_REL32 00000000 .bss\n-00003bd8 00005103 R_ARM_REL32 0000090c .LC42\n-00003bdc 00000103 R_ARM_REL32 00000000 .bss\n-00003be0 00005103 R_ARM_REL32 0000090c .LC42\n-00003be4 00004c03 R_ARM_REL32 000007b4 .LC36\n-00003be8 00004f03 R_ARM_REL32 0000088c .LC39\n-00003bec 00004d03 R_ARM_REL32 000007f8 .LC37\n-00003ca2 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00003cb4 0000840a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00003cba 0000820a R_ARM_THM_CALL 00000000 malloc\n-00003cf4 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00003d46 0000820a R_ARM_THM_CALL 00000000 malloc\n-00003f60 00008d0a R_ARM_THM_CALL 00000000 free\n-00003f76 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-0000400e 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000040c8 00000503 R_ARM_REL32 00000044 .LC1\n-000040cc 00004e03 R_ARM_REL32 00000838 .LC38\n-000040d0 00000403 R_ARM_REL32 00000000 .LC0\n-000040d4 00000503 R_ARM_REL32 00000044 .LC1\n-000040d8 00004b03 R_ARM_REL32 00000760 .LC35\n-000040dc 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-000040e0 00000503 R_ARM_REL32 00000044 .LC1\n-000040e4 00005503 R_ARM_REL32 000009d0 .LC47\n-000040e8 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000040ec 00005403 R_ARM_REL32 000009a4 .LC46\n-000040f0 00005203 R_ARM_REL32 00000930 .LC44\n-000040f4 00005303 R_ARM_REL32 00000964 .LC45\n-000041ce 0000820a R_ARM_THM_CALL 00000000 malloc\n-00004726 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004734 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-0000473c 0000840a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00004740 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004744 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004748 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000474c 0000881a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n-00004750 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004754 00007803 R_ARM_REL32 00000000 .rodata\n-00004758 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-0000475c 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004760 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004764 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004768 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-0000476c 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004770 00000503 R_ARM_REL32 00000044 .LC1\n-00004774 00005e03 R_ARM_REL32 00000a50 .LC49\n-00004778 00000403 R_ARM_REL32 00000000 .LC0\n-000049a4 0000820a R_ARM_THM_CALL 00000000 malloc\n-00004a08 0000820a R_ARM_THM_CALL 00000000 malloc\n-00004a72 0000820a R_ARM_THM_CALL 00000000 malloc\n-00004ae4 0000820a R_ARM_THM_CALL 00000000 malloc\n-00004d10 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004d14 0000881a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n-00004d18 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004d1c 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00004d20 00006203 R_ARM_REL32 00000ad4 .LC51\n-00004d24 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004d28 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d2c 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d30 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d34 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d38 00000103 R_ARM_REL32 00000000 .bss\n-00004d3c 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d40 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d44 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d48 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d4c 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d50 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004d54 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d58 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004d5c 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004e80 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00004e88 0000840a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00004e96 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00004ea4 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00004eb2 0000830a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00004eb8 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00004ebc 00006103 R_ARM_REL32 00000aa4 .LC50\n-00004ec0 00006803 R_ARM_REL32 00000c90 .LC57\n-00004ec4 00009403 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n-00004ec8 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00004ecc 00006703 R_ARM_REL32 00000c54 .LC56\n-00004ed0 00006703 R_ARM_REL32 00000c54 .LC56\n-00004ed4 00000503 R_ARM_REL32 00000044 .LC1\n-00004ed8 00006403 R_ARM_REL32 00000b58 .LC53\n-00004edc 00000403 R_ARM_REL32 00000000 .LC0\n-00004ee0 00000503 R_ARM_REL32 00000044 .LC1\n-00004ee4 00006303 R_ARM_REL32 00000b04 .LC52\n-00004ee8 00000503 R_ARM_REL32 00000044 .LC1\n-00004eec 00006503 R_ARM_REL32 00000bac .LC54\n-00004ef0 00000503 R_ARM_REL32 00000044 .LC1\n-00004ef4 00006603 R_ARM_REL32 00000c00 .LC55\n-00005018 0000810a R_ARM_THM_CALL 00000000 memset\n-00005186 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-0000518c 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005190 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005194 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005198 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000519c 0000921a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n-0000532a 0000990a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n-00005602 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00005608 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000560c 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005610 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005614 0000871a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00005618 00007103 R_ARM_REL32 00000cc4 .LC58\n-0000561c 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00005620 00007303 R_ARM_REL32 00000d20 .LC62\n-00005624 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00005628 0000921a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n-0000562c 00007803 R_ARM_REL32 00000000 .rodata\n-00005630 00007203 R_ARM_REL32 00000d00 .LC61\n-00005634 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005638 00007103 R_ARM_REL32 00000cc4 .LC58\n-0000563c 00007303 R_ARM_REL32 00000d20 .LC62\n-00005640 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-00005644 00008503 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n-000057e2 00008b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000057e8 00008c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000057ec 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000057f0 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000057f4 00008619 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000057f8 0000921a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n-00002212 00008d1e R_ARM_THM_JUMP24 00000000 free\n-000045b2 00008d1e R_ARM_THM_JUMP24 00000000 free\n+000000e2 0000830a R_ARM_THM_CALL 00000000 memset\n+000000ee 0000830a R_ARM_THM_CALL 00000000 memset\n+00000126 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000013a 0000840a R_ARM_THM_CALL 00000000 malloc\n+000001d0 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000001d8 0000860a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+000001dc 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000001e0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000001e4 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000001e8 00000703 R_ARM_REL32 000000b4 .LC3\n+000001ec 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000001f0 00000103 R_ARM_REL32 00000000 .bss\n+000001f4 00008a1a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+000001f8 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000001fc 00000503 R_ARM_REL32 00000044 .LC1\n+00000200 00000603 R_ARM_REL32 00000060 .LC2\n+00000204 00000403 R_ARM_REL32 00000000 .LC0\n+000003e4 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00000424 00008c0a R_ARM_THM_CALL 00000000 log\n+00000430 00008c0a R_ARM_THM_CALL 00000000 log\n+0000043c 00008c0a R_ARM_THM_CALL 00000000 log\n+000004e4 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+000004f0 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+000004fc 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000051a 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00000526 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00000532 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000057a 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000588 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000058c 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000590 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000594 00000a03 R_ARM_REL32 000000ec .LC4\n+00000598 00000a03 R_ARM_REL32 000000ec .LC4\n+0000059c 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000005a0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000077c 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000079a 00008c0a R_ARM_THM_CALL 00000000 log\n+000007a6 00008c0a R_ARM_THM_CALL 00000000 log\n+00000846 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00000852 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000085e 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+0000087c 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00000888 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+00000894 00008d0a R_ARM_THM_CALL 00000000 _gfortran_pow_i4_i4\n+000008dc 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000008e8 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000008ec 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000008f0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000008f4 00000a03 R_ARM_REL32 000000ec .LC4\n+000008f8 00000a03 R_ARM_REL32 000000ec .LC4\n+000008fc 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000900 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000966 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00000a88 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00000ae8 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00000aee 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00000c6e 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00000ce0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000ce4 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000ce8 00001203 R_ARM_REL32 00000168 .LC6\n+00000cec 00001103 R_ARM_REL32 00000128 .LC5\n+00000d48 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000010a6 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000010c2 0000840a R_ARM_THM_CALL 00000000 malloc\n+0000126a 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000128a 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000012b8 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000012cc 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000014fc 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000151a 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00001548 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000156a 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+0000157c 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001580 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001584 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001588 00001803 R_ARM_REL32 0000019c .LC7\n+0000158c 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001590 00001903 R_ARM_REL32 000001d8 .LC8\n+00001594 00001a03 R_ARM_REL32 00000214 .LC9\n+00001598 00001b03 R_ARM_REL32 00000258 .LC10\n+0000159c 00001d03 R_ARM_REL32 000002e8 .LC12\n+000015a0 00001d03 R_ARM_REL32 000002e8 .LC12\n+000019d0 0000830a R_ARM_THM_CALL 00000000 memset\n+00001b66 0000830a R_ARM_THM_CALL 00000000 memset\n+00001e40 00001e03 R_ARM_REL32 00000318 .LC13\n+00001e44 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001e48 00001f03 R_ARM_REL32 00000360 .LC14\n+00001e4c 00002103 R_ARM_REL32 000003dc .LC16\n+00002076 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000020e8 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000020ec 00002003 R_ARM_REL32 00000390 .LC15\n+000020f0 00008a1a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+000020f4 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000020f8 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000020fc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002100 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002104 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000227c 0000860a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+0000228a 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000022b6 0000910a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+000022bc 00000403 R_ARM_REL32 00000000 .LC0\n+000022c0 00000503 R_ARM_REL32 00000044 .LC1\n+000022c4 00001c03 R_ARM_REL32 00000294 .LC11\n+000022c8 00002203 R_ARM_REL32 00000418 .LC17\n+000022cc 00002303 R_ARM_REL32 00000420 .LC18\n+000022d0 00002403 R_ARM_REL32 00000448 .LC19\n+000023fc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002400 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002404 00002e03 R_ARM_REL32 000004c0 .LC21\n+00002408 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+0000240c 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002410 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002414 00002d03 R_ARM_REL32 00000498 .LC20\n+00002634 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002638 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+0000263c 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002640 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002644 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000026c0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000026c4 0000951a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n+00002800 0000900a R_ARM_THM_CALL 00000000 free\n+00002812 0000900a R_ARM_THM_CALL 00000000 free\n+00002820 0000900a R_ARM_THM_CALL 00000000 free\n+0000282c 0000900a R_ARM_THM_CALL 00000000 free\n+000028f2 0000910a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+000028f8 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000028fc 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002900 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002904 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002908 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+0000290c 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002910 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002914 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002918 00003703 R_ARM_REL32 000004f0 .LC22\n+0000291c 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002920 00003803 R_ARM_REL32 00000528 .LC23\n+00002924 00002303 R_ARM_REL32 00000420 .LC18\n+00002928 00003903 R_ARM_REL32 00000530 .LC24\n+00002a96 0000900a R_ARM_THM_CALL 00000000 free\n+00002ab8 0000910a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00002abc 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002ac0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002ac4 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002ac8 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002acc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002ad0 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002ad4 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002ad8 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002adc 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002ae0 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002ae4 00003d03 R_ARM_REL32 00000580 .LC25\n+00002ae8 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00002aec 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002af0 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002af4 00003e03 R_ARM_REL32 000005ac .LC26\n+00002af8 00002303 R_ARM_REL32 00000420 .LC18\n+00002afc 00003f03 R_ARM_REL32 000005b4 .LC27\n+00002d90 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002d94 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002d98 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002d9c 00004303 R_ARM_REL32 00000604 .LC28\n+00002da0 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002da4 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002da8 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002dac 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002db0 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002db4 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00002db8 00004403 R_ARM_REL32 00000630 .LC29\n+00002ed6 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00002ee8 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00002ef8 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00002f86 00009a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00002fb0 00009b0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00002fb6 0000900a R_ARM_THM_CALL 00000000 free\n+00003050 00009a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00003074 00009b0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+0000307a 0000900a R_ARM_THM_CALL 00000000 free\n+00003110 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000313c 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003146 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000031cc 0000840a R_ARM_THM_CALL 00000000 malloc\n+00003274 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003286 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+0000328e 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+000032da 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000032e8 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000032f6 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003304 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003312 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003322 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003332 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003342 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000033fe 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003418 0000840a R_ARM_THM_CALL 00000000 malloc\n+000034e0 00009c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+000035c6 00009d0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d4\n+000036fa 0000900a R_ARM_THM_CALL 00000000 free\n+0000375c 0000900a R_ARM_THM_CALL 00000000 free\n+0000379a 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000037ac 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+000038d8 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000038dc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000038e0 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000038e4 00008a1a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+000038e8 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000038ec 00004803 R_ARM_REL32 0000066c .LC30\n+000038f0 00004903 R_ARM_REL32 00000694 .LC31\n+000038f4 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000038f8 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000038fc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003900 0000951a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n+00003904 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00003908 00004a03 R_ARM_REL32 000006c8 .LC32\n+0000390c 00004c03 R_ARM_REL32 0000072c .LC34\n+00003910 00004b03 R_ARM_REL32 000006fc .LC33\n+00003914 00000103 R_ARM_REL32 00000000 .bss\n+00003918 00000103 R_ARM_REL32 00000000 .bss\n+0000391c 00007803 R_ARM_REL32 00000000 .rodata\n+00003920 00005303 R_ARM_REL32 0000090c .LC42\n+00003924 00005803 R_ARM_REL32 00000a24 .LC48\n+00003928 00005203 R_ARM_REL32 000008cc .LC40\n+0000392c 00005303 R_ARM_REL32 0000090c .LC42\n+00003930 00004e03 R_ARM_REL32 000007b4 .LC36\n+00003934 00004f03 R_ARM_REL32 000007f8 .LC37\n+00003938 00005103 R_ARM_REL32 0000088c .LC39\n+00003a02 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003a0a 0000860a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00003a10 0000840a R_ARM_THM_CALL 00000000 malloc\n+00003a48 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003a52 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003ab2 0000840a R_ARM_THM_CALL 00000000 malloc\n+00003ae4 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003aea 00008b0a R_ARM_THM_CALL 00000000 __aeabi_idivmod\n+00003cc4 0000900a R_ARM_THM_CALL 00000000 free\n+00003cda 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00003d08 00000503 R_ARM_REL32 00000044 .LC1\n+00003d0c 00005003 R_ARM_REL32 00000838 .LC38\n+00003d10 00000403 R_ARM_REL32 00000000 .LC0\n+00003d14 00000503 R_ARM_REL32 00000044 .LC1\n+00003d18 00004d03 R_ARM_REL32 00000760 .LC35\n+00003d1c 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003d20 00005603 R_ARM_REL32 000009a4 .LC46\n+00003d24 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00003d28 00000503 R_ARM_REL32 00000044 .LC1\n+00003d2c 00005703 R_ARM_REL32 000009d0 .LC47\n+00003d30 00005403 R_ARM_REL32 00000930 .LC44\n+00003d5e 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003d92 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003dca 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00003dec 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003df0 00005503 R_ARM_REL32 00000964 .LC45\n+00003eca 0000840a R_ARM_THM_CALL 00000000 malloc\n+0000441a 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004428 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00004430 0000860a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00004434 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004438 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000443c 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004440 00008a1a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+00004444 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004448 00007803 R_ARM_REL32 00000000 .rodata\n+0000444c 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004450 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004454 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004458 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+0000445c 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004460 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004464 00000503 R_ARM_REL32 00000044 .LC1\n+00004468 00006003 R_ARM_REL32 00000a50 .LC49\n+0000446c 00000403 R_ARM_REL32 00000000 .LC0\n+0000463e 0000830a R_ARM_THM_CALL 00000000 memset\n+00004678 0000840a R_ARM_THM_CALL 00000000 malloc\n+000046ce 0000840a R_ARM_THM_CALL 00000000 malloc\n+0000471c 0000820a R_ARM_THM_CALL 00000000 __aeabi_idiv\n+00004738 0000840a R_ARM_THM_CALL 00000000 malloc\n+000047a0 0000840a R_ARM_THM_CALL 00000000 malloc\n+00004ac6 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00004ace 0000860a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00004adc 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00004aea 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00004af8 0000850a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00004afc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004b00 00008a1a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_totnodes\n+00004b04 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004b08 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00004b0c 00006303 R_ARM_REL32 00000aa4 .LC50\n+00004b10 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004b14 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b18 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b1c 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b20 00000103 R_ARM_REL32 00000000 .bss\n+00004b24 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b28 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b2c 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b30 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b34 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b38 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b3c 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004b40 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b44 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b48 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004b4c 00006403 R_ARM_REL32 00000ad4 .LC51\n+00004b50 00009703 R_ARM_REL32 00000000 __gridxc_mesh3d_MOD_storedmeshtask\n+00004b54 00006a03 R_ARM_REL32 00000c90 .LC57\n+00004b58 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00004b5c 00006903 R_ARM_REL32 00000c54 .LC56\n+00004b60 00006903 R_ARM_REL32 00000c54 .LC56\n+00004b64 00000503 R_ARM_REL32 00000044 .LC1\n+00004b68 00006603 R_ARM_REL32 00000b58 .LC53\n+00004b6c 00000403 R_ARM_REL32 00000000 .LC0\n+00004b70 00000503 R_ARM_REL32 00000044 .LC1\n+00004b74 00006503 R_ARM_REL32 00000b04 .LC52\n+00004b78 00000503 R_ARM_REL32 00000044 .LC1\n+00004b7c 00006703 R_ARM_REL32 00000bac .LC54\n+00004b80 00000503 R_ARM_REL32 00000044 .LC1\n+00004b84 00006803 R_ARM_REL32 00000c00 .LC55\n+00004caa 0000830a R_ARM_THM_CALL 00000000 memset\n+00004e14 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004e20 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e24 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e28 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004e2c 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e30 0000951a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n+00004fbc 00009c0a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d4\n+0000528c 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005290 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005294 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00005298 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000529c 0000891a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000052a0 00007103 R_ARM_REL32 00000cc4 .LC58\n+000052a4 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000052a8 00007303 R_ARM_REL32 00000d20 .LC62\n+000052ac 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000052b0 0000951a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n+000052b4 00007803 R_ARM_REL32 00000000 .rodata\n+000052b8 00007203 R_ARM_REL32 00000d00 .LC61\n+000052bc 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000052c0 00007103 R_ARM_REL32 00000cc4 .LC58\n+000052c4 00007303 R_ARM_REL32 00000d20 .LC62\n+000052c8 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+000052cc 00008703 R_ARM_REL32 00006400 __gridxc_mesh3d_MOD_storedmeshdistr\n+00005464 00008e0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00005468 00008f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000546c 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005470 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005474 00008819 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005478 0000951a R_ARM_GOT_BREL 00000000 __gridxc_config_MOD_gridxc_mynode\n+0000202a 0000901e R_ARM_THM_JUMP24 00000000 free\n+0000285a 0000831e R_ARM_THM_JUMP24 00000000 memset\n+000042ae 0000901e R_ARM_THM_JUMP24 00000000 free\n \n-Relocation section '.rel.data.rel' at offset 0x10554 contains 4 entries:\n+Relocation section '.rel.data.rel' at offset 0x103ac contains 4 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000000c 0000a402 R_ARM_ABS32 00000010 __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Tasktype\n+0000000c 0000a702 R_ARM_ABS32 00000010 __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Tasktype\n 00000010 00007e02 R_ARM_ABS32 00000001 __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Tasktype\n-00000028 0000a502 R_ARM_ABS32 00000110 __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Distrtype\n+00000028 0000a802 R_ARM_ABS32 00000110 __gridxc_mesh3d_MOD___def_init_gridxc_mesh3d_Distrtype\n 0000002c 00008002 R_ARM_ABS32 00000021 __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Distrtype\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,12 +1,13 @@\n-jK4!jHxD\n+WK4!WHxD\n DK.!DHxD\n-\\IRF\\HyDxD\n-0F{DuY-hI\n-#D]c6K{D\n+I #\"FyD@F\n+(F{DuY-hI\n+%I\"F%HyDxD\n+$I\"F$HyDxD\n Integer overflow when calculating the amount of memory to allocate\n Error allocating %lu bytes\n In file '/build/reproducible-path/libgridxc-2.0.1/src/mesh3d.F90', around line 1740\n mesh3D initDistr ERROR: parameter maxDistr too small\n mesh3D optimizeNodeDistr ERROR: parameter maxFac too small\n mesh3D divideBox1D ERROR: boxSize not a multiple of blockSize\n mesh3D divideBox1D ERROR: size(workload)/=boxSize\n@@ -72,20 +73,23 @@\n __gridxc_mesh3d_MOD_reducedistr\n __gridxc_mesh3d_MOD_setmeshdistr.localalias\n __gridxc_mesh3d_MOD_associatemeshtask.localalias\n __gridxc_mesh3d_MOD_copymeshdata.localalias\n mysrcdata.0\n __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Tasktype\n __gridxc_mesh3d_MOD___copy_gridxc_mesh3d_Distrtype\n+__aeabi_uidiv\n+__aeabi_idiv\n _gfortran_os_error_at\n _gfortran_runtime_error\n __gridxc_mesh3d_MOD_storedmeshdistr\n _GLOBAL_OFFSET_TABLE_\n __gridxc_sys_MOD_die\n __gridxc_config_MOD_gridxc_totnodes\n+__aeabi_idivmod\n _gfortran_pow_i4_i4\n __stack_chk_fail\n __stack_chk_guard\n _gfortran_runtime_error_at\n __gridxc_mesh3d_MOD_samemeshdistr\n __gridxc_mesh3d_MOD_nodemeshbox\n __gridxc_mesh3d_MOD_mymeshbox\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -31,641 +31,627 @@\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tpop\t{r3, pc}\n \tnop\n \n 00000040 <__gridxc_mesh3d_MOD_initdistr.part.0>:\n __gridxc_mesh3d_MOD_initdistr.part.0():\n-\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n+\tstmdb\tsp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n-\tldr.w\tlr, [pc, #468]\t@ 228 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1e8>\n-\tsub\tsp, #16\n-\tmov\tr8, r0\n-\tmov\tr5, r1\n+\tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n+\tldr.w\tlr, [pc, #392]\t@ 1dc <__gridxc_mesh3d_MOD_initdistr.part.0+0x19c>\n+\tmov\tr9, r0\n+\tmov\tr8, r1\n+\tmov\tr5, r2\n \tadd\tlr, pc\n-\tmov\tr7, r2\n-\tmov\tr9, r3\n+\tmov\tr6, r3\n \tadd.w\tlr, lr, #80\t@ 0x50\n \tmovs\tr4, #0\n-\tldr\tr6, [pc, #452]\t@ (22c <__gridxc_mesh3d_MOD_initdistr.part.0+0x1ec>)\n-\tadd\tr6, pc\n+\tldr\tr7, [pc, #376]\t@ (1e0 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1a0>)\n+\tadd\tr7, pc\n \tsub.w\tip, lr, #80\t@ 0x50\n-\tb.n\t74 <__gridxc_mesh3d_MOD_initdistr.part.0+0x34>\n+\tb.n\t72 <__gridxc_mesh3d_MOD_initdistr.part.0+0x32>\n \tcmp\tlr, ip\n-\tbeq.n\t94 <__gridxc_mesh3d_MOD_initdistr.part.0+0x54>\n+\tbeq.n\t92 <__gridxc_mesh3d_MOD_initdistr.part.0+0x52>\n \tldr.w\tr3, [ip, #4]!\n \tcmp\tr3, #0\n-\tblt.n\t70 <__gridxc_mesh3d_MOD_initdistr.part.0+0x30>\n+\tblt.n\t6e <__gridxc_mesh3d_MOD_initdistr.part.0+0x2e>\n \tadds\tr4, #1\n \tadd.w\tlr, lr, #364\t@ 0x16c\n \tcmp\tr4, #20\n-\tbne.n\t6a <__gridxc_mesh3d_MOD_initdistr.part.0+0x2a>\n-\tldr\tr3, [pc, #424]\t@ (230 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1f0>)\n+\tbne.n\t68 <__gridxc_mesh3d_MOD_initdistr.part.0+0x28>\n+\tldr\tr3, [pc, #348]\t@ (1e4 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1a4>)\n \tmovs\tr1, #52\t@ 0x34\n-\tldr\tr0, [pc, #424]\t@ (234 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1f4>)\n+\tldr\tr0, [pc, #348]\t@ (1e8 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1a8>)\n \tadd\tr0, pc\n-\tldr\tr3, [r6, r3]\n+\tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr.w\tr3, [r9]\n-\tmov.w\tr9, #1\n-\tstr\tr3, [sp, #0]\n-\tldr\tr3, [r7, #0]\n-\tstr\tr3, [sp, #4]\n-\tldr\tr7, [pc, #404]\t@ (238 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1f8>)\n \tldr\tr3, [r5, #0]\n-\tstr\tr3, [sp, #8]\n-\tadd\tr7, pc\n-\tldr\tr2, [pc, #400]\t@ (23c <__gridxc_mesh3d_MOD_initdistr.part.0+0x1fc>)\n-\tldr\tr3, [r5, #4]\n-\tstr\tr3, [sp, #12]\n-\tmov.w\tr3, #364\t@ 0x16c\n-\tvld1.64\t{d16-d17}, [sp :64]\n+\tmov.w\tr5, #364\t@ 0x16c\n+\tldr.w\tsl, [pc, #336]\t@ 1ec <__gridxc_mesh3d_MOD_initdistr.part.0+0x1ac>\n+\tldr\tr2, [pc, #336]\t@ (1f0 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1b0>)\n+\tmul.w\tr5, r4, r5\n+\tadd\tsl, pc\n+\tldr\tr1, [r6, #0]\n \tadd\tr2, pc\n-\tmul.w\tr4, r3, r4\n-\tldr\tr1, [r5, #8]\n-\tadds\tr3, r7, r4\n-\tadds\tr5, r7, r4\n-\tadds\tr3, #84\t@ 0x54\n-\tadd.w\tr0, r4, #104\t@ 0x68\n-\tstr.w\tr9, [r7, r4]\n-\tadd\tr0, r7\n-\tvst1.32\t{d16-d17}, [r3]\n-\tldr\tr3, [r2, #0]\n-\tstr\tr1, [r5, #100]\t@ 0x64\n+\tadd.w\tr6, sl, r5\n+\tadd.w\tr0, r5, #104\t@ 0x68\n+\tadd\tr0, sl\n+\tstrd\tr1, r3, [r6, #84]\t@ 0x54\n \tmovs\tr1, #255\t@ 0xff\n-\tadd.w\tsl, r3, r9\n-\tstr.w\tsl, [r2]\n-\tstr.w\tsl, [r8]\n+\tldr.w\tr3, [r8]\n+\tstr\tr3, [r6, #92]\t@ 0x5c\n+\tldr\tr3, [r2, #0]\n+\tadd.w\tfp, r3, #1\n+\tldr.w\tr3, [r8, #4]\n+\tstr.w\tfp, [r2]\n \tmovs\tr2, #200\t@ 0xc8\n+\tstr\tr3, [r6, #96]\t@ 0x60\n+\tstr.w\tfp, [r9]\n+\tldr.w\tr3, [r8, #8]\n+\tmov.w\tr8, #1\n+\tstr\tr3, [r6, #100]\t@ 0x64\n+\tstr.w\tr8, [sl, r5]\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tadds\tr0, r4, #4\n+\tadds\tr0, r5, #4\n \tmovs\tr2, #80\t@ 0x50\n \tmovs\tr1, #255\t@ 0xff\n-\tadd\tr0, r7\n-\tadd.w\tr4, r4, #320\t@ 0x140\n+\tadd\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr3, [pc, #316]\t@ (240 <__gridxc_mesh3d_MOD_initdistr.part.0+0x200>)\n-\tmovs\tr2, #4\n-\tstr.w\tsl, [r5, #4]\n-\tstr.w\tr2, [r5, #312]\t@ 0x138\n-\tmovw\tr2, #259\t@ 0x103\n-\tvstr\td16, [r5, #316]\t@ 0x13c\n-\tstrh\tr2, [r7, r4]\n-\tadd\tr4, r7\n-\tldr\tr3, [r6, r3]\n-\tldr\tr6, [r3, #0]\n-\tcmp\tr6, #0\n-\tbic.w\tr1, r6, r6, asr #31\n-\tble.n\t1b2 <__gridxc_mesh3d_MOD_initdistr.part.0+0x172>\n-\tmvn.w\tr2, #2147483648\t@ 0x80000000\n+\tadd.w\tr5, r5, #320\t@ 0x140\n+\tldr\tr3, [pc, #252]\t@ (1f4 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1b4>)\n+\tmovs\tr2, #0\n+\tstrd\tr2, r2, [r6, #316]\t@ 0x13c\n+\tmovs\tr1, #4\n+\tstr.w\tfp, [r6, #4]\n+\tstr.w\tr1, [r6, #312]\t@ 0x138\n+\tmovw\tr1, #259\t@ 0x103\n+\tstrh.w\tr1, [sl, r5]\n+\tldr\tr3, [r7, r3]\n+\tldr\tr5, [r3, #0]\n+\tcmp\tr5, r2\n+\tbic.w\tr1, r5, r5, asr #31\n+\tble.n\t1c0 <__gridxc_mesh3d_MOD_initdistr.part.0+0x180>\n \tmovs\tr3, #6\n-\tudiv\tr2, r2, r1\n-\tmul.w\tr3, r1, r3\n-\tcmp\tr2, #5\n-\tble.n\t1fc <__gridxc_mesh3d_MOD_initdistr.part.0+0x1bc>\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n-\tbge.n\t1fc <__gridxc_mesh3d_MOD_initdistr.part.0+0x1bc>\n-\tlsls\tr7, r3, #2\n-\tmov\tr0, r7\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr6, r3, r1\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, #5\n+\tble.n\t1d4 <__gridxc_mesh3d_MOD_initdistr.part.0+0x194>\n+\tcmp.w\tr6, #1073741824\t@ 0x40000000\n+\titt\tlt\n+\tlsllt\tr6, r6, #2\n+\tmovlt\tr0, r6\n+\tbge.n\t1d4 <__gridxc_mesh3d_MOD_initdistr.part.0+0x194>\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r5, #304]\t@ 0x130\n-\tcmp\tr0, #0\n-\tbeq.n\t1ee <__gridxc_mesh3d_MOD_initdistr.part.0+0x1ae>\n-\tvldr\td18, [pc, #184]\t@ 208 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1c8>\n-\tvldr\td19, [pc, #188]\t@ 210 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1d0>\n-\tadd.w\tr7, r4, #20\n-\tvldr\td16, [pc, #188]\t@ 218 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1d8>\n-\tvldr\td17, [pc, #192]\t@ 220 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1e0>\n-\tmvn.w\tr3, #2\n-\tadds\tr4, #4\n-\tstr.w\tr3, [r5, #308]\t@ 0x134\n+\tldr\tr3, [pc, #184]\t@ (1f8 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1b8>)\n+\tmov.w\tr2, #364\t@ 0x16c\n+\tadd\tr3, pc\n+\tmla\tr3, r2, r4, r3\n+\tstr.w\tr0, [r3, #304]\t@ 0x130\n+\tcbz\tr0, 1c6 <__gridxc_mesh3d_MOD_initdistr.part.0+0x186>\n+\tmovs\tr1, #1\n+\tmovs\tr2, #2\n+\tstr.w\tr1, [r3, #328]\t@ 0x148\n+\tmovs\tr4, #6\n+\tstrd\tr1, r2, [r3, #332]\t@ 0x14c\n+\tstr.w\tr2, [r3, #340]\t@ 0x154\n+\tmovs\tr2, #0\n+\tstr.w\tr1, [r3, #344]\t@ 0x158\n+\tmovs\tr1, #3\n+\tstr.w\tr1, [r3, #348]\t@ 0x15c\n+\tsubs\tr1, r5, #1\n+\tstr.w\tr4, [r3, #352]\t@ 0x160\n+\tcmp\tr1, r2\n+\tmvn.w\tr4, #2\n+\tstr.w\tr2, [r3, #356]\t@ 0x164\n+\tstr.w\tr4, [r3, #308]\t@ 0x134\n+\tmov.w\tr4, #4\n+\tstr.w\tr1, [r3, #360]\t@ 0x168\n+\tstr.w\tr4, [r3, #324]\t@ 0x144\n+\tblt.n\t1bc <__gridxc_mesh3d_MOD_initdistr.part.0+0x17c>\n \tmovs\tr1, #24\n \tmov\tr3, r0\n-\tmovs\tr2, #0\n-\tstr.w\tr2, [r5, #356]\t@ 0x164\n-\tmla\tr1, r1, r6, r0\n-\tsubs\tr6, #1\n-\tstr.w\tr6, [r5, #360]\t@ 0x168\n-\tvst1.32\t{d18-d19}, [r4]\n-\tvst1.32\t{d16-d17}, [r7]\n+\tmla\tr1, r1, r5, r0\n+\tstr\tr2, [r3, #0]\n \tadds\tr3, #24\n-\tstr.w\tr2, [r3, #-24]\n \tstr.w\tr2, [r3, #-16]\n \tstr.w\tr2, [r3, #-8]\n-\tcmp\tr1, r3\n-\tbne.n\t186 <__gridxc_mesh3d_MOD_initdistr.part.0+0x146>\n+\tcmp\tr3, r1\n+\tbne.n\t198 <__gridxc_mesh3d_MOD_initdistr.part.0+0x158>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr\tr3, [r0, #4]\n \tadds\tr0, #24\n \tstr.w\tr3, [r0, #-12]\n \tstr.w\tr3, [r0, #-4]\n-\tcmp\tr0, r1\n-\tbne.n\t19c <__gridxc_mesh3d_MOD_initdistr.part.0+0x15c>\n-\tadd\tsp, #16\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tmov\tr0, r9\n-\tbl\t0 \n- R_ARM_THM_CALL\tmalloc\n-\tstr.w\tr0, [r5, #304]\t@ 0x130\n-\tcbz\tr0, 1ec <__gridxc_mesh3d_MOD_initdistr.part.0+0x1ac>\n-\tvldr\td18, [pc, #72]\t@ 208 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1c8>\n-\tvldr\td19, [pc, #76]\t@ 210 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1d0>\n-\tadds\tr3, r4, #4\n-\tvldr\td16, [pc, #76]\t@ 218 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1d8>\n-\tvldr\td17, [pc, #80]\t@ 220 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1e0>\n-\tadds\tr4, #20\n-\tmovs\tr2, #0\n-\tsubs\tr6, #1\n-\tstrd\tr2, r6, [r5, #356]\t@ 0x164\n-\tmvn.w\tr2, #2\n-\tstr.w\tr2, [r5, #308]\t@ 0x134\n-\tvst1.32\t{d18-d19}, [r3]\n-\tvst1.32\t{d16-d17}, [r4]\n-\tb.n\t1ac <__gridxc_mesh3d_MOD_initdistr.part.0+0x16c>\n-\tmov\tr7, r0\n-\tldr\tr1, [pc, #84]\t@ (244 <__gridxc_mesh3d_MOD_initdistr.part.0+0x204>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #84]\t@ (248 <__gridxc_mesh3d_MOD_initdistr.part.0+0x208>)\n+\tcmp\tr1, r0\n+\tbne.n\t1ac <__gridxc_mesh3d_MOD_initdistr.part.0+0x16c>\n+\tldmia.w\tsp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tmov\tr0, r8\n+\tmov\tr6, r2\n+\tb.n\t13a <__gridxc_mesh3d_MOD_initdistr.part.0+0xfa>\n+\tldr\tr1, [pc, #52]\t@ (1fc <__gridxc_mesh3d_MOD_initdistr.part.0+0x1bc>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #52]\t@ (200 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1c0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #76]\t@ (24c <__gridxc_mesh3d_MOD_initdistr.part.0+0x20c>)\n+\tldr\tr0, [pc, #44]\t@ (204 <__gridxc_mesh3d_MOD_initdistr.part.0+0x1c4>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tnop.w\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n-\t.word\t0x00000006\n-\t.word\t0x000001ca\n+\t.word\t0x0000017e\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000001c0\n+\t.word\t0x00000176\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000001a4\n+\t.word\t0x0000015a\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000018c\n+\t.word\t0x00000146\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x00000180\n+\t.word\t0x00000146\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n-\t.word\t0x0000004c\n+\t.word\t0x000000b0\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x0000002c\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000004e\n+\t.word\t0x0000002e\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000004a\n+\t.word\t0x0000002a\n R_ARM_REL32\t.LC0\n \n-00000250 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>:\n+00000208 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>:\n __gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tstr.w\tr0, [ip, #-72]\n \tsubw\tsp, sp, #4068\t@ 0xfe4\n-\tldr\tr3, [pc, #848]\t@ (5c0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x370>)\n-\tmovs\tr6, #0\n-\tmov\tr4, r1\n+\tldr\tr3, [pc, #864]\t@ (588 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x380>)\n+\tmov\tr4, r0\n+\tmovs\tr0, #0\n+\tmov\tfp, r1\n \tmov\tlr, r1\n-\tmovw\tr8, #52429\t@ 0xcccd\n-\tmovt\tr8, #52428\t@ 0xcccc\n \tstr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [pc, #836]\t@ (5c4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x374>)\n \tmovw\tr1, #43691\t@ 0xaaab\n \tmovt\tr1, #43690\t@ 0xaaaa\n-\tstr\tr6, [sp, #4]\n+\tldr\tr2, [pc, #848]\t@ (58c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x384>)\n+\tmovw\tsl, #52429\t@ 0xcccd\n+\tmovt\tsl, #52428\t@ 0xcccc\n \tadd\tr2, pc\n \tmovw\tip, #39321\t@ 0x9999\n \tmovt\tip, #6553\t@ 0x1999\n \tmovw\tr5, #26215\t@ 0x6667\n \tmovt\tr5, #26214\t@ 0x6666\n-\tmovw\tr7, #21846\t@ 0x5556\n-\tmovt\tr7, #21845\t@ 0x5555\n+\tmovw\tr8, #21846\t@ 0x5556\n+\tmovt\tr8, #21845\t@ 0x5555\n \tldr\tr3, [r2, r3]\n+\tmov\tr6, r0\n \tmovw\tr2, #43690\t@ 0xaaaa\n \tmovt\tr2, #10922\t@ 0x2aaa\n-\tldr.w\tr9, [pc, #792]\t@ 5c8 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x378>\n+\tldr.w\tr9, [pc, #804]\t@ 590 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x388>\n \tldr\tr3, [r3, #0]\n \tstr.w\tr3, [sp, #4060]\t@ 0xfdc\n \tmov.w\tr3, #0\n-\tstr\tr6, [sp, #36]\t@ 0x24\n+\tstr\tr0, [sp, #40]\t@ 0x28\n \tadd\tr9, pc\n \tands.w\tr3, lr, #1\n-\tbne.n\t2da <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x8a>\n+\tbne.n\t294 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x8c>\n \tadd.w\tlr, lr, lr, lsr #31\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tmov.w\tlr, lr, asr #1\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tands.w\tr3, lr, #1\n-\tbeq.n\t2c6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x76>\n-\tmla\tsl, r1, lr, r2\n-\tcmp.w\tsl, #1431655765\t@ 0x55555555\n-\tbcs.n\t2f0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xa0>\n-\tsmull\tsl, r3, r7, lr\n+\tbeq.n\t280 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x78>\n+\tmla\tr7, r1, lr, r2\n+\tcmp.w\tr7, #1431655765\t@ 0x55555555\n+\tbcs.n\t2aa <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xa2>\n+\tsmull\tr7, r3, r8, lr\n \tadds\tr6, #1\n \tsub.w\tlr, r3, lr, asr #31\n-\tb.n\t2c0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x70>\n-\tmla\tsl, r8, lr, ip\n-\tcmp.w\tsl, #858993459\t@ 0x33333333\n-\tbcs.n\t30e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xbe>\n-\tldr\tr3, [sp, #4]\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #4]\n-\tsmull\tsl, r3, r5, lr\n+\tb.n\t27a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x72>\n+\tmla\tr7, sl, lr, ip\n+\tcmp.w\tr7, #858993459\t@ 0x33333333\n+\tbcs.n\t2c4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xbc>\n+\tsmull\tr7, r3, r5, lr\n \tmov.w\tlr, lr, asr #31\n+\tadds\tr0, #1\n \trsb\tlr, lr, r3, asr #1\n-\tb.n\t2c0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x70>\n+\tb.n\t27a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x72>\n \tstr\tr3, [sp, #0]\n-\tsubs.w\tr3, lr, #1\n+\tsubs.w\tsl, lr, #1\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tit\tne\n-\tmovne\tr3, #1\n-\tmov\tsl, r3\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tmovne.w\tsl, #1\n \tcmp\tr3, #0\n-\tblt.w\t49e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x24e>\n+\tblt.w\t46c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x264>\n \tmovs\tr3, #0\n \tcmp\tr6, #0\n-\tblt.w\t5a2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x352>\n-\tldr\tr2, [pc, #672]\t@ (5cc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x37c>)\n+\tblt.w\t56e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x366>\n+\tldr\tr2, [pc, #688]\t@ (594 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x38c>)\n+\tmov\tr1, r3\n \tmovs\tr5, #0\n-\tstr.w\tlr, [sp, #16]\n-\tmov\tr7, r4\n+\tstr.w\tlr, [sp, #12]\n \tadd\tr2, pc\n \tstr\tr2, [sp, #32]\n-\tldr\tr2, [pc, #660]\t@ (5d0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x380>)\n-\tmov\tlr, r3\n-\tstr\tr0, [sp, #52]\t@ 0x34\n+\tldr\tr2, [pc, #680]\t@ (598 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x390>)\n+\tmov\tr3, r0\n+\tstr\tr6, [sp, #36]\t@ 0x24\n+\tmov\tlr, r1\n \tadd\tr2, pc\n-\tstr\tr2, [sp, #24]\n+\tmov\tr6, fp\n+\tstr\tr2, [sp, #20]\n+\tmov\tr2, r5\n+\tstr\tr4, [sp, #52]\t@ 0x34\n \tcmp.w\tlr, #31\n-\tble.w\t4ca <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x27a>\n+\tble.w\t49a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x292>\n \tmovs\tr4, #0\n-\tldr\tr3, [sp, #4]\n \tcmp\tr3, #0\n-\tblt.w\t4c0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x270>\n-\tadd.w\tr3, sl, #1\n+\tblt.w\t48e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x286>\n+\tmov\tfp, r9\n \tadd.w\tr8, sp, #60\t@ 0x3c\n-\tstr\tr3, [sp, #8]\n-\tmovs\tr3, #0\n-\tstr\tr6, [sp, #20]\n+\tmovs\tr5, #0\n+\tmov\tr9, r2\n+\tadd.w\tr1, sl, #1\n+\tstr\tr3, [sp, #16]\n+\tstr\tr1, [sp, #8]\n \tstr.w\tlr, [sp, #28]\n-\tstr\tr7, [sp, #40]\t@ 0x28\n-\tmov.w\tfp, #0\n-\tmov\tr2, r5\n-\tmov\tr5, fp\n-\tmov\tfp, r2\n-\tstr\tr4, [sp, #12]\n-\tmov\tr4, fp\n-\tmovs\tr7, #0\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tmovs\tr3, #0\n+\tmov\tr2, fp\n+\tmov\tfp, r3\n+\tmov\tr3, r2\n+\tstr\tr4, [sp, #24]\n+\tmov\tr4, r9\n+\tstr.w\tr9, [sp, #4]\n \tadds\tr6, r4, #1\n+\tmovs\tr7, #0\n+\tmov\tr9, r3\n \tcmp.w\tr6, #1000\t@ 0x3e8\n-\tble.n\t390 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x140>\n-\tldr\tr2, [pc, #592]\t@ (5d4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x384>)\n+\tble.n\t352 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x14a>\n+\tldr\tr2, [pc, #596]\t@ (59c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x394>)\n \tmovs\tr1, #58\t@ 0x3a\n-\tldr\tr0, [sp, #24]\n+\tldr\tr0, [sp, #20]\n \tldr.w\tr2, [r9, r2]\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n-\tmovs\tr3, #0\n \tcmp\tsl, r7\n-\tstr.w\tr3, [r8, r4, lsl #2]\n-\tble.n\t3ac <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x15c>\n+\tstr.w\tr5, [r8, r4, lsl #2]\n+\tble.n\t36e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x166>\n \tmov\tr4, r6\n \tldr\tr7, [sp, #0]\n \tadds\tr6, r4, #1\n \tcmp.w\tr6, #1000\t@ 0x3e8\n-\tbgt.n\t380 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x130>\n+\tbgt.n\t344 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x13c>\n \tcmp\tsl, r7\n-\tstr.w\tr3, [r8, r4, lsl #2]\n-\tbgt.n\t398 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x148>\n+\tstr.w\tr5, [r8, r4, lsl #2]\n+\tbgt.n\t35a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x152>\n \tldr\tr2, [sp, #8]\n-\tadds\tr5, #1\n-\tadd\tfp, r2\n-\tldr\tr2, [sp, #4]\n-\tcmp\tr2, r5\n-\tbge.n\t374 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x124>\n-\tldr\tr4, [sp, #12]\n-\tmov\tr5, fp\n-\tldr\tr2, [sp, #20]\n+\tmov\tr3, r9\n+\tldr.w\tr9, [sp, #4]\n+\tadd.w\tfp, fp, #1\n+\tadd\tr9, r2\n+\tldr\tr2, [sp, #16]\n+\tcmp\tr2, fp\n+\tbge.n\t332 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x12a>\n+\tldr\tr4, [sp, #24]\n+\tmov\tfp, r3\n+\tldr\tr3, [sp, #36]\t@ 0x24\n \tadds\tr4, #1\n-\tcmp\tr2, r4\n-\tbge.n\t368 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x118>\n+\tcmp\tr3, r4\n+\tbge.n\t328 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x120>\n \tldr.w\tlr, [sp, #28]\n-\tmov\tr6, r2\n-\tldr\tr7, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tmov\tr3, r2\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tmov\tr2, r9\n+\tmov\tr9, fp\n+\tldr\tr1, [sp, #40]\t@ 0x28\n \tadd.w\tlr, lr, #1\n-\tcmp\tr3, lr\n-\tbge.n\t342 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xf2>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tcmp\tr5, #0\n-\tble.n\t49e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x24e>\n-\tvldr\ts15, [r0]\n-\tadd\tr1, sp, #56\t@ 0x38\n-\tadd.w\tr5, r1, r5, lsl #2\n-\tvldr\td9, [pc, #464]\t@ 5b8 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x368>\n-\tmov\tfp, r1\n-\tmov\tr8, r5\n-\tvcvt.f64.s32\td11, s15\n-\tmov\tsl, r0\n-\tmov\tr9, r7\n-\tvmov.f64\td10, #8\t@ 0x40400000 3.0\n-\tstr\tr1, [sp, #0]\n-\tldr.w\tr5, [fp, #4]!\n-\tvmov\ts15, r5\n-\tldr\tr6, [sp, #0]\n-\tvcvt.f64.s32\td16, s15\n-\tvdiv.f64\td15, d11, d16\n-\tldr.w\tr4, [r6, #4]!\n-\tmul.w\tr3, r4, r5\n-\tsdiv\tr7, r9, r3\n-\tmls\tr3, r3, r7, r9\n-\tcbnz\tr3, 496 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x246>\n-\tvldr\ts15, [sl, #4]\n-\tvcvt.f64.s32\td18, s15\n-\tvldr\ts15, [sl, #8]\n-\tvcvt.f64.s32\td17, s15\n-\tvmov\ts15, r4\n-\tvcvt.f64.s32\td16, s15\n+\tcmp\tr1, lr\n+\tbge.n\t300 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xf8>\n+\tldr\tr4, [sp, #52]\t@ 0x34\n+\tmov\tfp, r6\n+\tcmp\tr2, #0\n+\tble.n\t46c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x264>\n+\tvldr\ts15, [r4]\n+\tadd\tr3, sp, #56\t@ 0x38\n+\tvldr\td10, [pc, #460]\t@ 580 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x378>\n+\tadd.w\tr5, r3, r2, lsl #2\n+\tmov\tr8, r3\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tvcvt.f64.s32\td12, s15\n+\tstr\tr3, [sp, #0]\n+\tldr.w\tr7, [r8, #4]!\n \tvmov\ts15, r7\n-\tvdiv.f64\td8, d18, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvdiv.f64\td14, d17, d16\n-\tvadd.f64\td16, d15, d8\n-\tvadd.f64\td16, d16, d14\n-\tvdiv.f64\td13, d10, d16\n-\tvmul.f64\td0, d15, d13\n+\tldr.w\tsl, [sp]\n+\tvcvt.f64.s32\td7, s15\n+\tvdiv.f64\td9, d12, d7\n+\tldr.w\tr6, [sl, #4]!\n+\tmov\tr0, fp\n+\tmul.w\tr1, r6, r7\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr9, r0\n+\tcbnz\tr1, 464 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x25c>\n+\tvldr\ts15, [r4, #4]\n+\tvcvt.f64.s32\td5, s15\n+\tvldr\ts15, [r4, #8]\n+\tvcvt.f64.s32\td6, s15\n+\tvmov\ts15, r6\n+\tvcvt.f64.s32\td7, s15\n+\tvdiv.f64\td8, d5, d7\n+\tvmov\ts15, r0\n+\tvcvt.f64.s32\td7, s15\n+\tvdiv.f64\td15, d6, d7\n+\tvadd.f64\td7, d9, d8\n+\tvadd.f64\td7, d7, d15\n+\tvdiv.f64\td14, d11, d7\n+\tvmul.f64\td0, d9, d14\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmov.f64\td12, d0\n-\tvmul.f64\td0, d8, d13\n+\tvmov.f64\td13, d0\n+\tvmul.f64\td0, d8, d14\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvmov.f64\td8, d0\n-\tvmul.f64\td0, d14, d13\n+\tvmul.f64\td0, d15, d14\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvmul.f64\td8, d8, d8\n-\tvfma.f64\td8, d12, d12\n-\tvfma.f64\td8, d0, d0\n-\tvcmpe.f64\td9, d8\n+\tvmla.f64\td8, d13, d13\n+\tvmla.f64\td8, d0, d0\n+\tvcmpe.f64\td10, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t496 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x246>\n+\tble.n\t464 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x25c>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td9, d8\n-\tstrd\tr5, r4, [r3]\n-\tstr\tr7, [r3, #8]\n-\tcmp\tr6, r8\n-\tbne.n\t40e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x1be>\n-\tcmp\tfp, r8\n-\tbne.n\t3fc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x1ac>\n-\tldr\tr2, [pc, #312]\t@ (5d8 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x388>)\n-\tldr\tr3, [pc, #284]\t@ (5c0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x370>)\n+\tvmov.f64\td10, d8\n+\tstrd\tr7, r6, [r3]\n+\tstr.w\tr9, [r3, #8]\n+\tcmp\tsl, r5\n+\tbne.n\t3da <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x1d2>\n+\tcmp\tr8, r5\n+\tbne.n\t3c6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x1be>\n+\tldr\tr2, [pc, #304]\t@ (5a0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x398>)\n+\tldr\tr3, [pc, #280]\t@ (588 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x380>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [sp, #4060]\t@ 0xfdc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t5ae <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x35e>\n+\tbne.n\t57a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x372>\n \taddw\tsp, sp, #4068\t@ 0xfe4\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tldr\tr1, [sp, #36]\t@ 0x24\n \tadds\tr4, #1\n-\tcmp\tr6, r4\n-\tbge.w\t34c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xfc>\n-\tb.n\t3cc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x17c>\n-\tldr\tr3, [sp, #4]\n+\tcmp\tr1, r4\n+\tbge.w\t30a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x102>\n+\tb.n\t39a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x192>\n \tmovs\tr1, #0\n \tcmp\tr3, #0\n-\tblt.n\t59a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x34a>\n-\tadd.w\tr3, sl, #1\n-\tmov\tr2, r5\n-\tstr\tr3, [sp, #8]\n-\tmov\tr5, lr\n+\tblt.n\t564 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x35c>\n+\tstr\tr3, [sp, #24]\n+\tmov\tr7, lr\n \tmov\tr3, r1\n \tadd.w\tr8, sp, #60\t@ 0x3c\n-\tstr\tr6, [sp, #40]\t@ 0x28\n-\tstr\tr7, [sp, #48]\t@ 0x30\n+\tadd.w\tr0, sl, #1\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tstr\tr0, [sp, #8]\n \tstr.w\tr8, [sp, #28]\n-\tmovs\tr7, #0\n-\tstr\tr3, [sp, #12]\n-\tmov\tfp, r7\n+\tmovs\tr6, #0\n+\tstr\tr3, [sp, #4]\n+\tmov\tfp, r6\n \tmov\tr3, r2\n \tldr\tr2, [sp, #28]\n \tmovs\tr4, #0\n-\tadds\tr6, r3, #1\n-\tstr\tr3, [sp, #20]\n-\tadd.w\tr7, r2, r3, lsl #2\n-\tadds\tr3, r6, r4\n+\tadds\tr5, r3, #1\n+\tstr\tr3, [sp, #16]\n+\tadd.w\tr6, r2, r3, lsl #2\n+\tadds\tr3, r5, r4\n \tcmp.w\tr3, #1000\t@ 0x3e8\n-\tble.n\t54a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2fa>\n-\tldr\tr3, [pc, #204]\t@ (5d4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x384>)\n+\tble.n\t516 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x30e>\n+\tldr\tr3, [pc, #200]\t@ (59c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x394>)\n \tmovs\tr1, #58\t@ 0x3a\n \tldr\tr0, [sp, #32]\n \tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr1, [sp, #12]\n+\tldr\tr1, [sp, #4]\n \tmovs\tr0, #3\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tlsl.w\tr8, r0, r5\n+\tlsl.w\tr8, r0, r7\n \tmov\tr1, fp\n \tmovs\tr0, #5\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tmov\tr1, r4\n \tmul.w\tr8, r0, r8\n-\tldr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #12]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tcmp\tr4, sl\n \tmul.w\tr0, r8, r0\n-\tstr\tr0, [r7, #0]\n-\tbge.n\t574 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x324>\n+\tstr\tr0, [r6, #0]\n+\tbge.n\t540 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x338>\n \tldr\tr4, [sp, #0]\n-\tadds\tr7, #4\n-\tadds\tr3, r6, r4\n+\tadds\tr6, #4\n+\tadds\tr3, r5, r4\n \tcmp.w\tr3, #1000\t@ 0x3e8\n-\tbgt.n\t506 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2b6>\n-\tldr\tr1, [sp, #12]\n+\tbgt.n\t4d2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2ca>\n+\tldr\tr1, [sp, #4]\n \tmovs\tr0, #3\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n-\tlsl.w\tr8, r0, r5\n+\tlsl.w\tr8, r0, r7\n \tmov\tr1, fp\n \tmovs\tr0, #5\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tmov\tr1, r4\n \tmul.w\tr8, r0, r8\n-\tldr\tr0, [sp, #16]\n+\tldr\tr0, [sp, #12]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tcmp\tr4, sl\n \tmul.w\tr3, r0, r8\n-\tstr\tr3, [r7, #0]\n-\tblt.n\t53e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2ee>\n+\tstr\tr3, [r6, #0]\n+\tblt.n\t50a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x302>\n \tldr\tr2, [sp, #8]\n \tadd.w\tfp, fp, #1\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #16]\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #4]\n+\tldr\tr2, [sp, #24]\n \tcmp\tr2, fp\n-\tbge.n\t4f2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2a2>\n+\tbge.n\t4be <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2b6>\n \tmov\tr2, r3\n-\tldr\tr3, [sp, #12]\n-\tldr\tr1, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #4]\n+\tldr\tr1, [sp, #36]\t@ 0x24\n \tadds\tr3, #1\n \tcmp\tr1, r3\n-\tbge.n\t4ea <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x29a>\n-\tmov\tlr, r5\n-\tldr\tr7, [sp, #48]\t@ 0x30\n-\tmov\tr6, r1\n-\tmov\tr5, r2\n-\tb.n\t3cc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x17c>\n+\tbge.n\t4b6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x2ae>\n+\tldr\tr3, [sp, #24]\n+\tmov\tlr, r7\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tb.n\t39a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x192>\n+\tldr\tr0, [sp, #36]\t@ 0x24\n \tadds\tr1, #1\n-\tcmp\tr6, r1\n-\tbge.n\t4ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x27e>\n-\tb.n\t3cc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x17c>\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tcmp\tr0, r1\n+\tbge.n\t49c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x294>\n+\tb.n\t39a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x192>\n+\tldr\tr2, [sp, #40]\t@ 0x28\n \tadds\tr3, #1\n \tcmp\tr2, r3\n-\tbge.w\t324 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xd4>\n-\tb.n\t49e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x24e>\n+\tbge.w\t2da <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0xd2>\n+\tb.n\t46c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0+0x264>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n-\tnop.w\n \t.word\t0xffffffff\n \t.word\t0x7fefffff\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000336\n+\t.word\t0x00000346\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000306\n+\t.word\t0x00000314\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000294\n+\t.word\t0x000002a6\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000028e\n+\t.word\t0x0000029e\n R_ARM_REL32\t.LC4\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000132\n+\t.word\t0x0000012c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000005dc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>:\n+000005a4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>:\n __gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tstr.w\tr0, [ip, #-64]\n \tsubw\tsp, sp, #4068\t@ 0xfe4\n-\tldr\tr3, [pc, #796]\t@ (918 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x33c>)\n+\tmov\tr8, r2\n+\tldr\tr2, [pc, #804]\t@ (8e8 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x344>)\n \tmov\tr4, r1\n+\tldr\tr3, [pc, #804]\t@ (8ec <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x348>)\n \tmov\tlr, r1\n-\tmovw\tsl, #52429\t@ 0xcccd\n-\tmovt\tsl, #52428\t@ 0xcccc\n-\tstrd\tr0, r2, [sp, #48]\t@ 0x30\n+\tadd\tr2, pc\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tmovs\tr0, #0\n-\tldr\tr2, [pc, #780]\t@ (91c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x340>)\n \tmovw\tr1, #43691\t@ 0xaaab\n \tmovt\tr1, #43690\t@ 0xaaaa\n+\tmovw\tfp, #52429\t@ 0xcccd\n+\tmovt\tfp, #52428\t@ 0xcccc\n+\tldr\tr3, [r2, r3]\n \tmovw\tip, #39321\t@ 0x9999\n \tmovt\tip, #6553\t@ 0x1999\n-\tadd\tr2, pc\n \tmovw\tr6, #26215\t@ 0x6667\n \tmovt\tr6, #26214\t@ 0x6666\n-\tmovw\tr8, #21846\t@ 0x5556\n-\tmovt\tr8, #21845\t@ 0x5555\n-\tldr\tr3, [r2, r3]\n+\tmovw\tsl, #21846\t@ 0x5556\n+\tmovt\tsl, #21845\t@ 0x5555\n \tmov\tr5, r0\n \tmovw\tr2, #43690\t@ 0xaaaa\n \tmovt\tr2, #10922\t@ 0x2aaa\n-\tldr.w\tr9, [pc, #736]\t@ 920 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x344>\n+\tldr.w\tr9, [pc, #744]\t@ 8f0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x34c>\n \tldr\tr3, [r3, #0]\n \tstr.w\tr3, [sp, #4060]\t@ 0xfdc\n \tmov.w\tr3, #0\n \tstr\tr0, [sp, #40]\t@ 0x28\n \tadd\tr9, pc\n \tands.w\tr3, lr, #1\n-\tbne.n\t668 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x8c>\n+\tbne.n\t630 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x8c>\n \tadd.w\tlr, lr, lr, lsr #31\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tmov.w\tlr, lr, asr #1\n \tadds\tr3, #1\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tands.w\tr3, lr, #1\n-\tbeq.n\t654 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x78>\n+\tbeq.n\t61c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x78>\n \tmla\tr7, r1, lr, r2\n \tcmp.w\tr7, #1431655765\t@ 0x55555555\n-\tbcs.n\t67e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xa2>\n-\tsmull\tr7, r3, r8, lr\n+\tbcs.n\t646 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xa2>\n+\tsmull\tr7, r3, sl, lr\n \tadds\tr5, #1\n \tsub.w\tlr, r3, lr, asr #31\n-\tb.n\t64e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x72>\n-\tmla\tr7, sl, lr, ip\n+\tb.n\t616 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x72>\n+\tmla\tr7, fp, lr, ip\n \tcmp.w\tr7, #858993459\t@ 0x33333333\n-\tbcs.n\t698 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xbc>\n+\tbcs.n\t660 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xbc>\n \tsmull\tr7, r3, r6, lr\n \tmov.w\tlr, lr, asr #31\n \tadds\tr0, #1\n \trsb\tlr, lr, r3, asr #1\n-\tb.n\t64e <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x72>\n+\tb.n\t616 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x72>\n \tstr\tr3, [sp, #0]\n-\tsubs.w\tr3, lr, #1\n-\tit\tne\n-\tmovne\tr3, #1\n-\tmov\tsl, r3\n+\tsubs.w\tsl, lr, #1\n \tldr\tr3, [sp, #40]\t@ 0x28\n+\tit\tne\n+\tmovne.w\tsl, #1\n \tcmp\tr3, #0\n-\tblt.w\t7fa <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x21e>\n+\tblt.w\t7ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x22a>\n \tmovs\tr3, #0\n \tcmp\tr5, #0\n-\tblt.w\t8fc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x320>\n-\tldr\tr2, [pc, #620]\t@ (924 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x348>)\n+\tblt.w\t8d0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x32c>\n+\tldr\tr2, [pc, #628]\t@ (8f4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x350>)\n \tmov\tr1, r3\n \tmovs\tr6, #0\n \tstr.w\tlr, [sp, #12]\n \tadd\tr2, pc\n \tstr\tr2, [sp, #32]\n-\tldr\tr2, [pc, #612]\t@ (928 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x34c>)\n+\tldr\tr2, [pc, #620]\t@ (8f8 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x354>)\n \tmov\tr3, r0\n \tstr\tr5, [sp, #36]\t@ 0x24\n \tmov\tlr, r1\n \tadd\tr2, pc\n-\tmov\tr5, r4\n+\tmov\tr5, r8\n \tstr\tr2, [sp, #20]\n \tmov\tr2, r6\n+\tstr\tr4, [sp, #52]\t@ 0x34\n \tcmp.w\tlr, #31\n-\tble.w\t828 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x24c>\n+\tble.w\t7fc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x258>\n \tmovs\tr4, #0\n \tcmp\tr3, #0\n-\tblt.w\t81c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x240>\n+\tblt.w\t7f0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x24c>\n \tmov\tfp, r9\n \tadd.w\tr8, sp, #60\t@ 0x3c\n \tmovs\tr6, #0\n \tmov\tr9, r2\n \tadd.w\tr1, sl, #1\n \tstr\tr3, [sp, #16]\n \tstr\tr1, [sp, #8]\n@@ -678,114 +664,120 @@\n \tstr\tr4, [sp, #24]\n \tmov\tr4, r9\n \tstr.w\tr9, [sp, #4]\n \tadds\tr5, r4, #1\n \tmovs\tr7, #0\n \tmov\tr9, r3\n \tcmp.w\tr5, #1000\t@ 0x3e8\n-\tble.n\t724 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x148>\n-\tldr\tr2, [pc, #532]\t@ (92c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x350>)\n+\tble.n\t6ee <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x14a>\n+\tldr\tr2, [pc, #536]\t@ (8fc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x358>)\n \tmovs\tr1, #58\t@ 0x3a\n \tldr\tr0, [sp, #20]\n \tldr.w\tr2, [r9, r2]\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n \tcmp\tsl, r7\n \tstr.w\tr6, [r8, r4, lsl #2]\n-\tble.n\t740 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x164>\n+\tble.n\t70a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x166>\n \tmov\tr4, r5\n \tldr\tr7, [sp, #0]\n \tadds\tr5, r4, #1\n \tcmp.w\tr5, #1000\t@ 0x3e8\n-\tbgt.n\t716 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x13a>\n+\tbgt.n\t6e0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x13c>\n \tcmp\tsl, r7\n \tstr.w\tr6, [r8, r4, lsl #2]\n-\tbgt.n\t72c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x150>\n+\tbgt.n\t6f6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x152>\n \tldr\tr2, [sp, #8]\n \tmov\tr3, r9\n \tldr.w\tr9, [sp, #4]\n \tadd.w\tfp, fp, #1\n \tadd\tr9, r2\n \tldr\tr2, [sp, #16]\n \tcmp\tr2, fp\n-\tbge.n\t704 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x128>\n+\tbge.n\t6ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x12a>\n \tldr\tr4, [sp, #24]\n \tmov\tfp, r3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadds\tr4, #1\n \tcmp\tr3, r4\n-\tbge.n\t6fa <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x11e>\n+\tbge.n\t6c4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x120>\n \tldr.w\tlr, [sp, #28]\n \tmov\tr3, r2\n \tldr\tr5, [sp, #44]\t@ 0x2c\n \tmov\tr2, r9\n \tmov\tr9, fp\n \tldr\tr1, [sp, #40]\t@ 0x28\n \tadd.w\tlr, lr, #1\n \tcmp\tr1, lr\n-\tbge.n\t6d2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xf6>\n-\tmov\tr4, r5\n+\tbge.n\t69c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xf8>\n+\tldr\tr4, [sp, #52]\t@ 0x34\n+\tmov\tr8, r5\n \tcmp\tr2, #0\n-\tble.n\t7fa <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x21e>\n+\tble.n\t7ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x22a>\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tadd\tr5, sp, #56\t@ 0x38\n-\tldr.w\tr9, [sp, #52]\t@ 0x34\n+\tvldr\td10, [pc, #400]\t@ 8e0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x33c>\n \tadd.w\tr6, r5, r2, lsl #2\n-\tvldr\td10, [pc, #388]\t@ 910 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x334>\n \tvmov.f64\td11, #96\t@ 0x3f000000 0.5\n \tvldr\ts18, [r3]\n \tvldr\ts16, [r3, #4]\n \tvcvt.f64.s32\td9, s18\n \tvcvt.f64.s32\td8, s16\n \tldr.w\tr7, [r5, #4]!\n+\tmov\tr0, r4\n \tvmov\ts15, r7\n-\tvcvt.f64.s32\td16, s15\n-\tsdiv\tr8, r4, r7\n-\tvdiv.f64\td0, d9, d16\n-\tvmov\ts15, r8\n-\tvcvt.f64.s32\td16, s15\n-\tvdiv.f64\td14, d8, d16\n-\tvadd.f64\td13, d0, d14\n+\tmov\tr1, r7\n+\tvcvt.f64.s32\td7, s15\n+\tvdiv.f64\td12, d9, d7\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tvmov\ts15, r0\n+\tstr\tr0, [sp, #0]\n+\tvcvt.f64.s32\td7, s15\n+\tvdiv.f64\td14, d8, d7\n+\tvadd.f64\td13, d12, d14\n \tvmul.f64\td13, d13, d11\n-\tvdiv.f64\td0, d0, d13\n+\tvdiv.f64\td0, d12, d13\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvmov.f64\td12, d0\n \tvdiv.f64\td0, d14, d13\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td16, d0, d0\n-\tvfma.f64\td16, d12, d12\n-\tvcmpe.f64\td16, d10\n+\tvmul.f64\td7, d0, d0\n+\tvmla.f64\td7, d12, d12\n+\tvcmpe.f64\td7, d10\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t7f6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x21a>\n-\tvmov.f64\td10, d16\n-\tstrd\tr7, r8, [r9]\n+\tbpl.n\t7ca <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x226>\n+\tvmov.f64\td10, d7\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr7, [r8]\n+\tstr.w\tr3, [r8, #4]\n \tcmp\tr5, r6\n-\tbne.n\t7a0 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x1c4>\n-\tldr\tr2, [pc, #308]\t@ (930 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x354>)\n-\tldr\tr3, [pc, #280]\t@ (918 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x33c>)\n+\tbne.n\t768 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x1c4>\n+\tldr\tr2, [pc, #304]\t@ (900 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x35c>)\n+\tldr\tr3, [pc, #280]\t@ (8ec <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x348>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [sp, #4060]\t@ 0xfdc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t908 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x32c>\n+\tbne.n\t8dc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x338>\n \taddw\tsp, sp, #4068\t@ 0xfe4\n \tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr1, [sp, #36]\t@ 0x24\n \tadds\tr4, #1\n \tcmp\tr1, r4\n-\tbge.w\t6dc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x100>\n-\tb.n\t76c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x190>\n+\tbge.w\t6a6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x102>\n+\tb.n\t736 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x192>\n \tmovs\tr1, #0\n \tcmp\tr3, #0\n-\tblt.n\t8f2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x316>\n+\tblt.n\t8c6 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x322>\n \tstr\tr3, [sp, #24]\n \tmov\tr7, lr\n \tmov\tr3, r1\n \tadd.w\tr8, sp, #60\t@ 0x3c\n \tadd.w\tr0, sl, #1\n \tstr\tr5, [sp, #44]\t@ 0x2c\n \tstr\tr0, [sp, #8]\n@@ -797,16 +789,16 @@\n \tldr\tr2, [sp, #28]\n \tmovs\tr4, #0\n \tadds\tr5, r3, #1\n \tstr\tr3, [sp, #16]\n \tadd.w\tr6, r2, r3, lsl #2\n \tadds\tr3, r5, r4\n \tcmp.w\tr3, #1000\t@ 0x3e8\n-\tble.n\t8a4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2c8>\n-\tldr\tr3, [pc, #200]\t@ (92c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x350>)\n+\tble.n\t878 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2d4>\n+\tldr\tr3, [pc, #196]\t@ (8fc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x358>)\n \tmovs\tr1, #58\t@ 0x3a\n \tldr\tr0, [sp, #32]\n \tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr1, [sp, #4]\n \tmovs\tr0, #3\n@@ -821,20 +813,20 @@\n \tmul.w\tr8, r0, r8\n \tldr\tr0, [sp, #12]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tcmp\tr4, sl\n \tmul.w\tr0, r8, r0\n \tstr\tr0, [r6, #0]\n-\tbge.n\t8ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2f2>\n+\tbge.n\t8a2 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2fe>\n \tldr\tr4, [sp, #0]\n \tadds\tr6, #4\n \tadds\tr3, r5, r4\n \tcmp.w\tr3, #1000\t@ 0x3e8\n-\tbgt.n\t860 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x284>\n+\tbgt.n\t834 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x290>\n \tldr\tr1, [sp, #4]\n \tmovs\tr0, #3\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tlsl.w\tr8, r0, r7\n \tmov\tr1, fp\n \tmovs\tr0, #5\n@@ -844,714 +836,520 @@\n \tmul.w\tr8, r0, r8\n \tldr\tr0, [sp, #12]\n \tbl\t0 <_gfortran_pow_i4_i4>\n R_ARM_THM_CALL\t_gfortran_pow_i4_i4\n \tcmp\tr4, sl\n \tmul.w\tr3, r0, r8\n \tstr\tr3, [r6, #0]\n-\tblt.n\t898 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2bc>\n+\tblt.n\t86c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x2c8>\n \tldr\tr2, [sp, #8]\n \tadd.w\tfp, fp, #1\n \tldr\tr3, [sp, #16]\n \tadd\tr3, r2\n \tldr\tr2, [sp, #24]\n \tcmp\tr2, fp\n-\tbge.n\t84c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x270>\n+\tbge.n\t820 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x27c>\n \tmov\tr2, r3\n \tldr\tr3, [sp, #4]\n \tldr\tr1, [sp, #36]\t@ 0x24\n \tadds\tr3, #1\n \tcmp\tr1, r3\n-\tbge.n\t844 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x268>\n+\tbge.n\t818 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x274>\n \tldr\tr3, [sp, #24]\n \tmov\tlr, r7\n \tldr\tr5, [sp, #44]\t@ 0x2c\n-\tb.n\t76c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x190>\n+\tb.n\t736 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x192>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tadds\tr1, #1\n \tcmp\tr0, r1\n-\tbge.n\t82a <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x24e>\n-\tb.n\t76c <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x190>\n+\tbge.n\t7fe <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x25a>\n+\tb.n\t736 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x192>\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tadds\tr3, #1\n \tcmp\tr2, r3\n-\tbge.w\t6ae <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xd2>\n-\tb.n\t7fa <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x21e>\n+\tbge.w\t676 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0xd2>\n+\tb.n\t7ce <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0+0x22a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n \t.word\t0xffffffff\n \t.word\t0x7fefffff\n+\t.word\t0x0000031a\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002fa\n+\t.word\t0x000002d8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002d0\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000262\n+\t.word\t0x0000026a\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000025a\n+\t.word\t0x00000262\n R_ARM_REL32\t.LC4\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000012e\n+\t.word\t0x0000012a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00000934 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>:\n+00000904 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>:\n __gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n+\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4024]\t@ 0xfb8\n-\tsub\tsp, #36\t@ 0x24\n-\tldr\tr2, [r2, #0]\n-\tmov\tr8, r1\n-\tldr\tr4, [sp, #72]\t@ 0x48\n-\tstr\tr2, [sp, #8]\n-\tldr.w\tr2, [pc, #1400]\t@ ec8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x594>\n-\tmov\tr5, r4\n-\tadd\tr2, pc\n-\tcbz\tr4, 972 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e>\n-\tldr\tr5, [r4, #0]\n-\tcbz\tr5, 972 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e>\n-\tldr.w\tsl, [r4, #24]\n-\tmovs\tr1, #1\n-\tcmp.w\tsl, #0\n+\tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n+\tsub\tsp, #20\n+\tldr.w\tr8, [pc, #964]\t@ ce0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3dc>\n+\tldr.w\tfp, [r2]\n+\tadd\tr8, pc\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tstr\tr1, [sp, #0]\n+\tmov\tr9, r5\n+\tcbz\tr5, 946 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x42>\n+\tldr.w\tr9, [r5]\n+\tcmp.w\tr9, #0\n+\tbeq.n\t946 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x42>\n+\tldr\tr4, [r5, #24]\n+\tldrd\tr2, r1, [r5, #28]\n+\tcmp\tr4, #0\n \tit\teq\n-\tmoveq\tsl, r1\n-\tldrd\tr1, r6, [r4, #28]\n-\tsub.w\tfp, r6, r1\n-\tvld1.32\t{d7}, [r0]\n-\tadd\tr1, sp, #12\n-\tcmp.w\tr8, #1\n-\tvmov\tr7, s14\n-\tvst1.32\t{d7[1]}, [r1]\n-\tbeq.w\tba4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x270>\n-\tldr\tr1, [sp, #12]\n-\tmovs\tr4, #1\n-\tsubs\tr6, r1, r7\n-\tadd.w\tr9, r6, #1\n-\tcbz\tr3, 9a4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x70>\n-\tldr\tr4, [r3, #0]\n-\tsdiv\tr3, r9, r4\n-\tmls\tr3, r4, r3, r9\n-\tcmp\tr3, #0\n-\tbne.w\taea <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1b6>\n-\tcmp\tr5, #0\n-\tbeq.w\tb02 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1ce>\n-\tadd.w\tr3, fp, #1\n+\tmoveq\tr4, #1\n+\tsub.w\tsl, r1, r2\n+\tldrd\tr7, r2, [r0]\n+\tstr\tr2, [sp, #8]\n+\tldr\tr2, [sp, #0]\n+\tcmp\tr2, #1\n+\tbeq.w\tb8e <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x28a>\n+\tldr\tr2, [sp, #8]\n+\tmovs\tr5, #1\n+\tsubs\tr6, r2, r7\n+\tadds\tr2, r6, #1\n+\tcbz\tr3, 972 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x6e>\n+\tldr\tr5, [r3, #0]\n+\tmov\tr0, r2\n+\tstr\tr2, [sp, #4]\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tldr\tr2, [sp, #4]\n+\tcmp\tr1, #0\n+\tbne.w\taca <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1c6>\n+\tcmp.w\tr9, #0\n+\tbeq.w\tae4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1e0>\n+\tadd.w\tr3, sl, #1\n \tbic.w\tr3, r3, r3, asr #31\n-\tcmp\tr9, r3\n-\tbeq.n\t9c8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x94>\n-\tldr.w\tr3, [pc, #1300]\t@ ecc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x598>\n+\tcmp\tr2, r3\n+\tbeq.n\t996 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x92>\n+\tldr\tr3, [pc, #860]\t@ (ce4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e0>)\n \tmovs\tr1, #49\t@ 0x31\n-\tldr.w\tr0, [pc, #1296]\t@ ed0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x59c>\n+\tldr\tr0, [pc, #860]\t@ (ce8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e4>)\n \tadd\tr0, pc\n-\tldr\tr3, [r2, r3]\n+\tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvmov.i64\td16, #0x0000000000000000\n-\tcmp.w\tfp, #0\n-\tblt.n\t9f0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xbc>\n-\tcmp.w\tsl, #1\n-\tbne.w\tbb0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x27c>\n-\tadd.w\tip, r5, #8\n-\tmov\tr3, r5\n-\tadd.w\tfp, ip, fp, lsl #3\n-\tvldmia\tr3!, {d17}\n-\tvadd.f64\td16, d16, d17\n-\tcmp\tr3, fp\n-\tbne.n\t9e4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xb0>\n-\tvmov\ts15, r8\n-\tldr\tr3, [sp, #8]\n-\tcmp.w\tr8, #1\n-\tvcvt.f64.s32\td17, s15\n-\tstr\tr7, [r3, #0]\n-\tvdiv.f64\td20, d16, d17\n-\tble.n\tad4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1a0>\n+\tvldr\td7, [pc, #832]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tcmp.w\tsl, #0\n+\tblt.n\t9bc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xb8>\n+\tcmp\tr4, #1\n+\tbne.w\tba2 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x29e>\n+\tadd.w\tr0, r9, #8\n+\tmov\tr3, r9\n+\tadd.w\tsl, r0, sl, lsl #3\n+\tvldmia\tr3!, {d6}\n+\tvadd.f64\td7, d7, d6\n+\tcmp\tr3, sl\n+\tbne.n\t9b0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xac>\n+\tvldr\ts13, [sp]\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr7, [fp]\n+\tvcvt.f64.s32\td6, s13\n+\tcmp\tr3, #1\n+\tvdiv.f64\td8, d7, d6\n+\tble.n\tab0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1ac>\n \tcmp\tr6, #0\n-\tblt.n\tad4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1a0>\n-\tmov\tlr, r3\n-\tadd.w\tip, r5, #8\n-\tcmp.w\tsl, #1\n-\tbne.w\tbcc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x298>\n-\tvmov\ts15, sl\n-\tmovs\tr1, #0\n-\tmov\tr9, r5\n-\tmov\tr2, ip\n-\tvcvt.f64.s32\td19, s15\n-\tmov\tr0, r1\n-\tvmul.f64\td19, d19, d20\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmov\tr3, r5\n-\tvldmia\tr3!, {d17}\n-\tvadd.f64\td16, d16, d17\n-\tcmp\tr3, r2\n-\tbne.n\ta32 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xfe>\n-\tvcmpe.f64\td19, d16\n-\tvldr\td17, [r2, #-8]\n+\tblt.n\tab0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1ac>\n+\tcmp\tr4, #1\n+\tbne.w\tbbc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2b8>\n+\tmov\tsl, fp\n+\tstr.w\tfp, [sp, #12]\n+\tmov\tfp, r4\n+\tadd.w\tr0, r9, #8\n+\tstr\tr0, [sp, #4]\n+\tvmov\ts15, fp\n+\tmov.w\tlr, #0\n+\tldr\tr0, [sp, #4]\n+\tmov\tr4, r9\n+\tvcvt.f64.s32\td4, s15\n+\tmov\tr3, lr\n+\tvmul.f64\td4, d4, d8\n+\tvldr\td7, [pc, #724]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tmov\tr2, r9\n+\tvldmia\tr2!, {d6}\n+\tvadd.f64\td7, d7, d6\n+\tcmp\tr0, r2\n+\tbne.n\ta06 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x102>\n+\tvcmpe.f64\td4, d7\n+\tvldr\td6, [r0, #-8]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.w\tb7e <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x24a>\n-\tcmp\tr0, #0\n-\tbeq.w\tb96 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x262>\n-\tsubs\tr3, r0, #1\n-\tcmp\tr1, r3\n-\tblt.w\tb96 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x262>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmov\tr3, r5\n-\tsub.w\tr1, r2, #8\n-\tvldmia\tr3!, {d17}\n-\tvadd.f64\td16, d16, d17\n-\tcmp\tr3, r1\n-\tbne.n\ta66 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x132>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvldmia\tr9!, {d18}\n-\tvadd.f64\td17, d17, d18\n-\tcmp\tr9, r2\n-\tbne.n\ta76 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x142>\n-\tadds\tr3, r7, r0\n-\tcmp\tr6, r0\n-\tbeq.n\taa8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x174>\n-\tvsub.f64\td17, d17, d19\n-\tvsub.f64\td16, d16, d19\n-\tvabs.f64\td17, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td17, d16\n+\tbpl.w\tb68 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x264>\n+\tcmp\tr3, #0\n+\tbeq.w\tb80 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x27c>\n+\tsubs\tr1, r3, #1\n+\tcmp\tr1, lr\n+\tbgt.w\tb80 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x27c>\n+\tvldr\td7, [pc, #676]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tmov\tr1, r9\n+\tsub.w\tlr, r0, #8\n+\tvldmia\tr1!, {d6}\n+\tvadd.f64\td7, d7, d6\n+\tcmp\tr1, lr\n+\tbne.n\ta3a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x136>\n+\tvldr\td6, [pc, #656]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tvldmia\tr4!, {d5}\n+\tvadd.f64\td6, d6, d5\n+\tcmp\tr0, r4\n+\tbne.n\ta4a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x146>\n+\tadds\tr4, r7, r3\n+\tcmp\tr6, r3\n+\tbeq.n\ta7c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x178>\n+\tvsub.f64\td6, d6, d4\n+\tvsub.f64\td7, d7, d4\n+\tvabs.f64\td6, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\taa8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x174>\n-\tstr.w\tr3, [lr, #4]\n-\tadds\tr3, #1\n-\tsdiv\tr1, r3, r4\n-\tldr.w\tr2, [lr]\n-\tadd\tr2, r4\n-\tmls\tr1, r4, r1, r3\n-\tsubs\tr3, r3, r1\n-\tcmp\tr2, r3\n+\titt\tle\n+\tstrle.w\tr4, [sl, #4]\n+\taddle\tr4, #1\n+\tldr.w\tr0, [sl]\n+\tmov\tr1, r5\n+\tadd.w\tr8, r5, r0\n+\tmov\tr0, r4\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tsubs\tr4, r4, r1\n+\tcmp\tr4, r8\n \tit\tlt\n-\tmovlt\tr2, r3\n-\tstr.w\tr2, [lr, #24]\n-\tsubs\tr2, #1\n-\tstr.w\tr2, [lr, #4]\n-\tadd.w\tsl, sl, #1\n-\tadd.w\tlr, lr, #24\n-\tcmp\tr8, sl\n-\tbne.n\ta18 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xe4>\n+\tmovlt\tr4, r8\n+\tstr.w\tr4, [sl, #24]\n+\tsubs\tr4, #1\n+\tstr.w\tr4, [sl, #4]\n+\tldr\tr3, [sp, #0]\n+\tadd.w\tfp, fp, #1\n+\tadd.w\tsl, sl, #24\n+\tcmp\tr3, fp\n+\tbne.n\t9ea <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xe6>\n+\tldr.w\tfp, [sp, #12]\n+\tldr\tr2, [sp, #0]\n \tmovs\tr3, #6\n-\tldrd\tr2, r1, [sp, #8]\n-\tmul.w\tr3, r3, r8\n-\tsubs\tr3, #5\n-\tstr.w\tr1, [r2, r3, lsl #2]\n-\tadd\tsp, #36\t@ 0x24\n+\tmul.w\tr2, r3, r2\n+\tsubs\tr3, r2, #5\n+\tldr\tr2, [sp, #8]\n+\tstr.w\tr2, [fp, r3, lsl #2]\n+\tadd\tsp, #20\n+\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #992]\t@ (ecc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x598>)\n+\tldr\tr3, [pc, #536]\t@ (ce4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e0>)\n \tmovs\tr1, #61\t@ 0x3d\n-\tldr\tr0, [pc, #996]\t@ (ed4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x5a0>)\n+\tldr\tr0, [pc, #540]\t@ (cec <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3e8>)\n \tadd\tr0, pc\n-\tldr\tr3, [r2, r3]\n-\tstr\tr2, [sp, #4]\n+\tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr2, [sp, #4]\n-\tcmp\tr5, #0\n-\tbne.w\t9aa <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x76>\n-\tsdiv\tr3, r9, r4\n-\tldr\tr2, [sp, #8]\n-\tstr\tr7, [r2, #0]\n-\tsdiv\tr1, r3, r8\n-\tmls\tr3, r8, r1, r3\n-\tmul.w\tr1, r4, r1\n-\tcmp\tr3, #0\n-\tadd\tr4, r1\n-\tble.w\tce4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3b0>\n+\tcmp.w\tr9, #0\n+\tbne.w\t97a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x76>\n \tmov\tr0, r2\n-\tadds\tr3, #1\n-\tadds\tr2, r4, r7\n-\tcmp\tr3, #2\n-\tadd.w\tr2, r2, #4294967295\t@ 0xffffffff\n-\tmov\tr5, r3\n-\tstr\tr2, [r0, #4]\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr1, [sp, #0]\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmul.w\tr0, r5, r0\n+\tsubs\tr3, r1, #0\n+\tstr.w\tr7, [fp]\n+\tadd\tr5, r0\n+\tadd.w\tr2, r3, #1\n+\tble.w\tcf0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3ec>\n+\tadds\tr3, r5, r7\n+\tcmp\tr2, #2\n+\tadd.w\tr3, r3, #4294967295\t@ 0xffffffff\n+\tmov\tr4, r2\n+\tadd.w\tr1, fp, #24\n \tit\tne\n-\tmovne\tr3, #2\n-\tadd.w\tr0, r0, #24\n-\tbeq.w\tcda <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3a6>\n-\tldr.w\tr2, [r0, #-20]\n-\tadds\tr3, #1\n-\tadds\tr0, #24\n-\tcmp\tr3, r5\n-\tadd.w\tr2, r2, #1\n-\tstr.w\tr2, [r0, #-24]\n-\tadd\tr2, r4\n-\tadd.w\tr2, r2, #4294967295\t@ 0xffffffff\n-\tstr.w\tr2, [r0, #-20]\n-\tbne.n\tb3a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x206>\n-\tcmp\tr8, r3\n-\tblt.n\tae4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1b0>\n-\tldr\tr0, [sp, #8]\n-\tmovs\tr2, #24\n-\tmla\tr2, r2, r3, r0\n-\tldr.w\tr0, [r2, #-44]\n-\tadds\tr3, #1\n-\tadds\tr4, r0, #1\n-\tadds\tr2, #24\n-\tadd\tr0, r1\n-\tstr.w\tr4, [r2, #-48]\n-\tcmp\tr8, r3\n-\tstr.w\tr0, [r2, #-44]\n-\tbge.n\tb68 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x234>\n-\tb.n\tae4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1b0>\n-\tvcmp.f64\td17, #0.0\n-\tadds\tr2, #8\n+\tmovne\tr2, #2\n+\tstr.w\tr3, [fp, #4]\n+\tbeq.w\tcca <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3c6>\n+\tldr.w\tr3, [r1, #-20]\n+\tadds\tr2, #1\n+\tadds\tr1, #24\n+\tcmp\tr2, r4\n+\tadd.w\tr3, r3, #1\n+\tstr.w\tr3, [r1, #-24]\n+\tadd\tr3, r5\n+\tadd.w\tr3, r3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr3, [r1, #-20]\n+\tbne.n\tb20 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x21c>\n+\tldr\tr3, [sp, #0]\n+\tcmp\tr3, r2\n+\tblt.n\tac0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1bc>\n+\tmovs\tr3, #24\n+\tldr\tr4, [sp, #0]\n+\tmla\tr3, r3, r2, fp\n+\tldr.w\tr1, [r3, #-44]\n+\tadds\tr1, #1\n+\tadds\tr2, #1\n+\tstr.w\tr1, [r3, #-24]\n+\tadd\tr1, r0\n+\tsubs\tr1, #1\n+\tadds\tr3, #24\n+\tstr.w\tr1, [r3, #-44]\n+\tcmp\tr4, r2\n+\tbge.n\tb50 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x24c>\n+\tb.n\tac0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1bc>\n+\tvcmp.f64\td6, #0.0\n+\tadds\tr0, #8\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tgt\n-\tmovgt\tr1, r0\n-\tadds\tr0, #1\n-\tcmp\tr6, r0\n-\tbge.w\ta2c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xf8>\n-\tb.n\tac8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x194>\n-\tadd\tr1, r0\n-\tadd.w\tr1, r1, r1, lsr #31\n-\tadd.w\tr3, r7, r1, asr #1\n+\tmovgt\tlr, r3\n \tadds\tr3, #1\n-\tb.n\taa8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x174>\n+\tcmp\tr6, r3\n+\tbge.w\ta00 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xfc>\n+\tb.n\ta9e <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x19a>\n+\tadd\tlr, r3\n+\tadd.w\tlr, lr, lr, lsr #31\n+\tadd.w\tr4, r7, lr, asr #1\n+\tadds\tr4, #1\n+\tb.n\ta7c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x178>\n \tldr\tr3, [sp, #8]\n-\tvst1.32\t{d7}, [r3]\n-\tadd\tsp, #36\t@ 0x24\n+\tstr.w\tr7, [fp]\n+\tstr.w\tr3, [fp, #4]\n+\tadd\tsp, #20\n+\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tmov.w\tr0, sl, lsl #3\n-\tmov\tr1, r5\n+\tlsls\tr0, r4, #3\n+\tmov\tr1, r9\n \tmovs\tr2, #0\n-\tvldr\td17, [r1]\n-\tcmp\tr2, fp\n+\tvldr\td6, [r1]\n+\tcmp\tr2, sl\n \tadd\tr1, r0\n \tadd.w\tr2, r2, #1\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\tbb8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x284>\n-\tb.n\t9f0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xbc>\n-\tmov.w\tr0, sl, lsl #3\n-\tldr.w\tsl, [sp, #8]\n-\tmov\tr9, r8\n-\tmov.w\tfp, #1\n-\tmov\tr8, r4\n-\tvmov\ts15, fp\n-\tmov.w\tip, #0\n-\tmov\tr2, r5\n-\tmov\tlr, r5\n-\tvcvt.f64.s32\td19, s15\n-\tmovs\tr1, #1\n-\tmov\tr4, ip\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\tba8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2a4>\n+\tb.n\t9bc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0xb8>\n+\tmovs\tr3, #1\n+\tlsls\tr4, r4, #3\n+\tmov\tsl, fp\n+\tmov\tr8, r3\n \tstr.w\tfp, [sp, #4]\n-\tvmul.f64\td19, d19, d20\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmov\tfp, r5\n+\tvmov\ts15, r8\n+\tmovs\tr1, #0\n+\tmov\tr2, r9\n+\tmov\tlr, r9\n+\tvcvt.f64.s32\td4, s15\n+\tmovs\tr0, #1\n+\tmov\tip, r1\n+\tvmul.f64\td4, d4, d8\n+\tvldr\td7, [pc, #248]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tmov\tfp, r9\n \tmovs\tr3, #0\n-\tvldr\td17, [fp]\n+\tvldr\td6, [fp]\n \tadds\tr3, #1\n-\tadd\tfp, r0\n-\tcmp\tr3, r1\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\tc00 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2cc>\n-\tvcmpe.f64\td16, d19\n-\tvldr\td17, [lr]\n+\tadd\tfp, r4\n+\tcmp\tr3, r0\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\tbe6 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2e2>\n+\tvcmpe.f64\td7, d4\n+\tvldr\td6, [lr]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\tcb0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x37c>\n-\tldr.w\tfp, [sp, #4]\n-\tcmp\tr4, #0\n-\tbeq.n\tccc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x398>\n-\tsubs\tr3, r4, #1\n-\tcmp\tip, r3\n-\tblt.n\tccc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x398>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tmov\tip, r5\n-\tmovs\tr3, #0\n-\tvldr\td16, [ip]\n-\tadds\tr3, #1\n-\tadd\tip, r0\n-\tcmp\tr3, r4\n-\tvadd.f64\td17, d17, d16\n-\tbne.n\tc34 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x300>\n-\tvmov.i64\td16, #0x0000000000000000\n+\tble.n\tca0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x39c>\n+\tcmp.w\tip, #0\n+\tbeq.n\tcba <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3b6>\n+\tadd.w\tr3, ip, #4294967295\t@ 0xffffffff\n+\tcmp\tr1, r3\n+\tblt.n\tcba <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3b6>\n+\tvldr\td6, [pc, #196]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tmov\tr1, r9\n \tmovs\tr3, #0\n-\tvldr\td18, [r2]\n+\tvldr\td7, [r1]\n \tadds\tr3, #1\n-\tadd\tr2, r0\n-\tcmp\tr3, r1\n-\tvadd.f64\td16, d16, d18\n-\tbne.n\tc4a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x316>\n-\tadds\tr3, r7, r4\n-\tcmp\tr6, r4\n-\tbeq.n\tc80 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x34c>\n-\tvsub.f64\td17, d17, d19\n-\tvsub.f64\td16, d16, d19\n-\tvabs.f64\td17, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td17, d16\n+\tadd\tr1, r4\n+\tcmp\tip, r3\n+\tvadd.f64\td6, d6, d7\n+\tbne.n\tc1a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x316>\n+\tvldr\td7, [pc, #172]\t@ cd8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x3d4>\n+\tmovs\tr1, #0\n+\tvldr\td5, [r2]\n+\tadds\tr1, #1\n+\tadd\tr2, r4\n+\tcmp\tr0, r1\n+\tvadd.f64\td7, d7, d5\n+\tbne.n\tc30 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x32c>\n+\tadd.w\tfp, r7, r3\n+\tcmp\tr6, ip\n+\tbeq.n\tc6a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x366>\n+\tvsub.f64\td6, d6, d4\n+\tvsub.f64\td7, d7, d4\n+\tvabs.f64\td6, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\tc80 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x34c>\n-\tstr.w\tr3, [sl, #4]\n-\tadds\tr3, #1\n-\tsdiv\tr2, r3, r8\n-\tmls\tr2, r8, r2, r3\n-\tsubs\tr2, r3, r2\n-\tldr.w\tr3, [sl]\n-\tadd\tr3, r8\n+\titt\tpl\n+\tstrpl.w\tfp, [sl, #4]\n+\taddpl.w\tfp, fp, #1\n+\tmov\tr1, r5\n+\tmov\tr0, fp\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tldr.w\tr2, [sl]\n+\tsub.w\tr3, fp, r1\n+\tadd\tr2, r5\n \tcmp\tr3, r2\n \tit\tlt\n \tmovlt\tr3, r2\n \tstr.w\tr3, [sl, #24]\n \tsubs\tr3, #1\n \tstr.w\tr3, [sl, #4]\n-\tadd.w\tfp, fp, #1\n+\tldr\tr3, [sp, #0]\n+\tadd.w\tr8, r8, #1\n \tadd.w\tsl, sl, #24\n-\tcmp\tfp, r9\n-\tbne.n\tbdc <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2a8>\n-\tmov\tr8, r9\n-\tb.n\tad4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1a0>\n-\tvcmp.f64\td17, #0.0\n-\tadds\tr1, #1\n-\tadd\tlr, r0\n+\tcmp\tr8, r3\n+\tbne.n\tbc8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2c4>\n+\tldr.w\tfp, [sp, #4]\n+\tb.n\tab0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1ac>\n+\tvcmp.f64\td6, #0.0\n+\tadds\tr0, #1\n+\tadd\tlr, r4\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tgt\n-\tmovgt\tip, r4\n-\tadds\tr4, #1\n-\tcmp\tr6, r4\n-\tbge.n\tbf8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2c4>\n-\tldr.w\tfp, [sp, #4]\n-\tb.n\tca0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x36c>\n-\tadd\tip, r4\n-\tadd.w\tip, ip, ip, lsr #31\n-\tadd.w\tr3, r7, ip, asr #1\n-\tadds\tr3, #1\n-\tb.n\tc80 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x34c>\n-\tcmp.w\tr8, #1\n-\tbgt.w\tb5c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x228>\n-\tb.n\tae4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1b0>\n-\tadds\tr0, r3, #1\n-\tcmp\tr8, r0\n-\tblt.w\tae4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1b0>\n-\tmov\tr4, r8\n-\tcmp\tr4, #1\n-\tit\tge\n-\tmovge\tr4, #1\n-\tsubs\tr2, r4, r3\n-\tcmp\tr3, r4\n-\tadd.w\tr5, r2, #4294967295\t@ 0xffffffff\n-\tit\tlt\n-\tmovlt\tr6, #0\n-\tit\tge\n-\tmovge\tr6, #1\n-\tcmp\tr3, r4\n-\tit\tge\n-\tmovge\tr2, #1\n-\tcmp\tr5, #9\n-\tit\thi\n-\tmovhi\tr5, #0\n-\tit\tls\n-\tmovls\tr5, #1\n-\torrs\tr5, r6\n-\tbne.n\tdac <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x478>\n-\tmovs\tr5, #24\n-\tvdup.32\tq8, r3\n-\tldr\tr6, [sp, #8]\n-\tlsrs\tr7, r2, #2\n-\tvldr\td18, [pc, #404]\t@ eb8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x584>\n-\tvldr\td19, [pc, #408]\t@ ec0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x58c>\n-\tmul.w\tr3, r5, r3\n-\tmovs\tr5, #96\t@ 0x60\n-\tvdup.32\tq12, r1\n-\tvmov.i32\tq11, #4\t@ 0x00000004\n-\tadd\tr6, r3\n-\tadd\tr6, r5\n-\tadds\tr3, #100\t@ 0x64\n-\tvmov.i8\tq10, #255\t@ 0xff\n-\tvadd.i32\tq8, q8, q9\n-\tmla\tr7, r5, r7, r6\n-\tldr\tr5, [sp, #8]\n-\tadd\tr3, r5\n-\tldr.w\tr5, [r6, #-96]\n-\tadds\tr6, #96\t@ 0x60\n-\tstr\tr5, [sp, #16]\n-\tadds\tr3, #96\t@ 0x60\n-\tvorr\tq9, q8, q8\n-\tcmp\tr6, r7\n-\tvadd.i32\tq8, q8, q11\n-\tldr.w\tr5, [r6, #-168]\n-\tstr\tr5, [sp, #20]\n-\tldr.w\tr5, [r6, #-144]\n-\tstr\tr5, [sp, #24]\n-\tldr.w\tr5, [r6, #-120]\n-\tstr\tr5, [sp, #28]\n-\tsub.w\tr5, r3, #168\t@ 0xa8\n-\tvldr\td6, [sp, #16]\n-\tvldr\td7, [sp, #24]\n-\tvadd.i32\tq3, q3, q12\n-\tvadd.i32\tq3, q3, q10\n-\tvstr\ts12, [r3, #-192]\t@ 0xffffff40\n-\tvst1.32\t{d6[1]}, [r5]\n-\tsub.w\tr5, r3, #144\t@ 0x90\n-\tvst1.32\t{d7[0]}, [r5]\n-\tsub.w\tr5, r3, #120\t@ 0x78\n-\tvst1.32\t{d7[1]}, [r5]\n-\tbne.n\td4e <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x41a>\n-\tbic.w\tr3, r2, #3\n-\tadd\tr0, r3\n-\tlsls\tr3, r2, #30\n-\tbeq.n\tea6 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x572>\n-\tmovs\tr2, #6\n-\tldr\tr7, [sp, #8]\n-\tadds\tr3, r0, #1\n-\tcmp\tr3, r4\n-\tmul.w\tip, r0, r2\n-\tsub.w\tr5, ip, #6\n-\tsub.w\tr2, ip, #5\n-\tmov.w\tr6, r5, lsl #2\n-\tldr.w\tr5, [r7, r5, lsl #2]\n-\tadd\tr5, r1\n-\tadd.w\tr5, r5, #4294967295\t@ 0xffffffff\n-\tstr.w\tr5, [r7, r2, lsl #2]\n-\tbgt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tadd\tr6, r7\n-\tmov\tr2, r7\n-\tadd.w\tr7, ip, #1\n-\tadds\tr3, r0, #2\n-\tcmp\tr3, r4\n-\tldr\tr5, [r6, #24]\n-\tadd\tr5, r1\n-\tadd.w\tr5, r5, #4294967295\t@ 0xffffffff\n-\tstr.w\tr5, [r2, r7, lsl #2]\n-\tbgt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr\tr3, [r6, #48]\t@ 0x30\n-\tadd.w\tr5, ip, #7\n-\tmov\tr7, r2\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadds\tr3, r0, #3\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr\tr3, [r6, #72]\t@ 0x48\n-\tadd.w\tr5, ip, #13\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadds\tr3, r0, #4\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr\tr3, [r6, #96]\t@ 0x60\n-\tadd.w\tr5, ip, #19\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadds\tr3, r0, #5\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr\tr3, [r6, #120]\t@ 0x78\n-\tadd.w\tr5, ip, #25\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadds\tr3, r0, #6\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr.w\tr3, [r6, #144]\t@ 0x90\n-\tadd.w\tr5, ip, #31\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadds\tr3, r0, #7\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr.w\tr3, [r6, #168]\t@ 0xa8\n-\tadd.w\tr5, ip, #37\t@ 0x25\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadd.w\tr3, r0, #8\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr.w\tr3, [r6, #192]\t@ 0xc0\n-\tadd.w\tr5, ip, #43\t@ 0x2b\n-\tadd\tr3, r1\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r5, lsl #2]\n-\tadd.w\tr3, r0, #9\n-\tcmp\tr4, r3\n-\tblt.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n-\tldr.w\tr4, [r6, #216]\t@ 0xd8\n-\tadd.w\tr2, ip, #49\t@ 0x31\n-\tadd.w\tr3, r0, #10\n-\tadds\tr0, r1, r4\n-\tsubs\tr0, #1\n-\tstr.w\tr0, [r7, r2, lsl #2]\n-\tcmp\tr3, r8\n-\tble.w\tb5c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x228>\n-\tadd\tsp, #36\t@ 0x24\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvmov.i32\tq8, #1\t@ 0x00000001\n-\tvadd.i32\tq9, q9, q8\n-\tvmov.32\tr3, d19[1]\n-\tb.n\te9a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x566>\n+\tmovgt\tr1, ip\n+\tadd.w\tip, ip, #1\n+\tcmp\tr6, ip\n+\tbge.n\tbde <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x2da>\n+\tb.n\tc8c <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x388>\n+\tadd\tr1, ip\n+\tadd.w\tr1, r1, r1, lsr #31\n+\tadd.w\tr3, r7, r1, asr #1\n+\tadd.w\tfp, r3, #1\n+\tb.n\tc6a <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x366>\n+\tldr\tr3, [sp, #0]\n+\tcmp\tr3, #1\n+\tbgt.w\tb44 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x240>\n+\tb.n\tac0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1bc>\n \tnop.w\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n-\t.word\t0x00000570\n+\t...\n+\t.word\t0x000003ba\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000050c\n+\t.word\t0x00000358\n R_ARM_REL32\t.LC6\n-\t.word\t0x000003e0\n+\t.word\t0x00000218\n R_ARM_REL32\t.LC5\n+\tldr\tr1, [sp, #0]\n+\tcmp\tr2, r1\n+\tbgt.w\tac0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1bc>\n+\tmov\tr4, r1\n+\tmovs\tr1, #24\n+\tcmp\tr4, #1\n+\tit\tge\n+\tmovge\tr4, #1\n+\tmla\tr3, r1, r3, fp\n+\tldr\tr1, [r3, #0]\n+\tadds\tr2, #1\n+\tadds\tr3, #24\n+\tcmp\tr2, r4\n+\tadd\tr1, r0\n+\tadd.w\tr1, r1, #4294967295\t@ 0xffffffff\n+\tstr.w\tr1, [r3, #-20]\n+\tble.n\td06 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x402>\n+\tldr\tr3, [sp, #0]\n+\tcmp\tr2, r3\n+\tble.w\tb44 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x240>\n+\tb.n\tac0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0+0x1bc>\n \n-00000ed8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>:\n+00000d24 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>:\n __gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0():\n-\tvld1.32\t{d7}, [r0]\n+\tpush\t{r3, r4, r5, r6, r7, lr}\n+\tmov.w\tip, #4096\t@ 0x1000\n+\tsub.w\tip, sp, ip\n+\tstr.w\tr0, [ip, #4072]\t@ 0xfe8\n+\tldrd\tr6, r3, [r0]\n \tcmp\tr1, #1\n-\tvmov.32\tr3, d7[1]\n-\tbeq.n\tf5e <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x86>\n-\tvmov\tr0, s14\n-\tpush\t{r4, r5, r6, r7, lr}\n-\tvstr\ts14, [r2]\n-\tsubs\tr3, r3, r0\n-\tadds\tr3, #1\n-\tsdiv\tip, r3, r1\n-\tmls\tr3, r1, ip, r3\n-\tadd.w\tr5, ip, #1\n-\tcmp\tr3, #0\n-\tble.n\tf64 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x8c>\n-\tmov\tlr, r2\n-\tsubs\tr4, r2, #4\n-\tadds\tr3, #1\n-\tsub.w\tr7, r2, #12\n-\tmov\tr6, r3\n+\tmov\tr4, r2\n+\tit\teq\n+\tstrdeq\tr6, r3, [r2]\n+\tbeq.n\tdb8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x94>\n+\tsubs\tr3, r3, r6\n+\tmov\tr5, r1\n+\tadds\tr0, r3, #1\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tsubs\tr3, r1, #0\n+\tstr\tr6, [r4, #0]\n+\tadd.w\tr3, r3, #1\n+\tadd.w\tr6, r0, #1\n+\tble.n\tdba <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x96>\n+\tmov\tip, r4\n+\tsub.w\tlr, r4, #4\n \tcmp\tr3, #2\n-\tldr.w\tr0, [lr], #-8\n-\tadd\tr0, r5\n-\tadd.w\tr0, r0, #4294967295\t@ 0xffffffff\n-\tstr\tr0, [r4, #8]\n-\tmov.w\tr0, #2\n-\tbeq.w\t104e <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x176>\n-\tldr.w\tr3, [r7, r0, lsl #3]\n+\tmov\tr7, r3\n+\tit\tne\n+\tmovne\tr1, #2\n+\tldr.w\tr2, [ip], #-8\n+\tadd\tr2, r6\n+\tadd.w\tr2, r2, #4294967295\t@ 0xffffffff\n+\tstr.w\tr2, [lr, #8]\n+\tit\tne\n+\tsubne.w\tr2, r4, #12\n+\tbeq.n\tde6 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0xc2>\n+\tldr.w\tr3, [r2, r1, lsl #3]\n \tadds\tr3, #1\n-\tstr.w\tr3, [lr, r0, lsl #3]\n-\tadd\tr3, r5\n+\tstr.w\tr3, [ip, r1, lsl #3]\n+\tadd\tr3, r6\n \tsubs\tr3, #1\n-\tstr.w\tr3, [r4, r0, lsl #3]\n-\tadds\tr0, #1\n-\tcmp\tr6, r0\n-\tbne.n\tf24 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x4c>\n-\tmov\tr3, r6\n-\tcmp\tr6, r1\n-\tbgt.n\tf5c <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x84>\n-\tadd.w\tr2, r2, r3, lsl #3\n-\tldr.w\tr2, [r2, #-12]\n-\tadds\tr0, r2, #1\n-\tadd\tr2, ip\n-\tstr.w\tr0, [lr, r3, lsl #3]\n-\tstr.w\tr2, [r4, r3, lsl #3]\n+\tstr.w\tr3, [lr, r1, lsl #3]\n+\tadds\tr1, #1\n+\tcmp\tr7, r1\n+\tbne.n\td7e <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x5a>\n+\tmov\tr3, r7\n+\tcmp\tr7, r5\n+\tbgt.n\tdb8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x94>\n+\tadd.w\tr4, r4, r3, lsl #3\n+\tldr.w\tr2, [r4, #-12]\n+\tadds\tr2, #1\n+\tstr.w\tr2, [ip, r3, lsl #3]\n+\tadd\tr2, r0\n+\tsubs\tr2, #1\n+\tstr.w\tr2, [lr, r3, lsl #3]\n \tadds\tr3, #1\n-\tcmp\tr3, r1\n-\tble.n\tf4a <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x72>\n-\tpop\t{r4, r5, r6, r7, pc}\n-\tvst1.32\t{d7}, [r2]\n-\tbx\tlr\n-\tadds\tr4, r3, #1\n-\tcmp\tr4, r1\n-\tbgt.n\tf5c <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x84>\n-\tcmp\tr1, #1\n-\tmov\tr5, r1\n+\tcmp\tr3, r5\n+\tble.n\tda4 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x80>\n+\tpop\t{r3, r4, r5, r6, r7, pc}\n+\tcmp\tr3, r5\n+\tbgt.n\tdb8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x94>\n+\tcmp\tr5, #1\n+\tmov\tr1, r5\n+\tsub.w\tip, r4, #8\n \tit\tge\n-\tmovge\tr5, #1\n-\tsubs\tr0, r5, r3\n-\tcmp\tr5, r3\n-\tadd.w\tr6, r0, #4294967295\t@ 0xffffffff\n-\tit\tgt\n-\tmovgt\tr7, #0\n-\tit\tle\n-\tmovle\tr7, #1\n-\tcmp\tr5, r3\n-\tit\tle\n-\tmovle\tr0, #1\n-\tcmp\tr6, #3\n-\tit\thi\n-\tmovhi\tr6, #0\n-\tit\tls\n-\tmovls\tr6, #1\n-\torrs\tr6, r7\n-\tbne.n\tfe6 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x10e>\n-\tsubs\tr0, #1\n-\tlsls\tr3, r3, #3\n-\tadds\tr6, r2, r3\n-\tvdup.32\tq11, ip\n-\tmov.w\tlr, r0, lsr #2\n-\tadds\tr3, #36\t@ 0x24\n-\tvmov.i8\tq10, #255\t@ 0xff\n-\tadd\tr3, r2\n-\tadd.w\tlr, r6, lr, lsl #5\n-\tvld2.32\t{d16-d19}, [r6]!\n-\tsub.w\tr7, r3, #24\n-\tvadd.i32\tq8, q11, q8\n-\tcmp\tlr, r6\n-\tvadd.i32\tq3, q8, q10\n-\tvstr\ts12, [r3, #-32]\t@ 0xffffffe0\n-\tvst1.32\t{d6[1]}, [r7]\n-\tsub.w\tr7, r3, #16\n-\tvst1.32\t{d7[0]}, [r7]\n-\tsub.w\tr7, r3, #8\n-\tadd.w\tr3, r3, #32\n-\tvst1.32\t{d7[1]}, [r7]\n-\tbne.n\tfb0 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0xd8>\n-\tbic.w\tr0, r0, #3\n-\tadd\tr4, r0\n-\tlsls\tr0, r4, #1\n-\tadds\tr3, r4, #1\n-\tsubs\tr6, r0, #2\n-\tsubs\tr7, r0, #1\n-\tcmp\tr5, r3\n-\tmov.w\tlr, r6, lsl #2\n-\tldr.w\tr6, [r2, r6, lsl #2]\n-\tadd\tr6, ip\n-\tadd.w\tr6, r6, #4294967295\t@ 0xffffffff\n-\tstr.w\tr6, [r2, r7, lsl #2]\n-\tblt.n\t1042 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x16a>\n-\tadd\tlr, r2\n-\tadds\tr7, r0, #1\n-\tadds\tr3, r4, #2\n-\tcmp\tr5, r3\n-\tldr.w\tr6, [lr, #8]\n-\tadd\tr6, ip\n-\tadd.w\tr6, r6, #4294967295\t@ 0xffffffff\n-\tstr.w\tr6, [r2, r7, lsl #2]\n-\tblt.n\t1042 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x16a>\n-\tldr.w\tr3, [lr, #16]\n-\tadds\tr6, r0, #3\n-\tadd\tr3, ip\n-\tsubs\tr3, #1\n-\tstr.w\tr3, [r2, r6, lsl #2]\n-\tadds\tr3, r4, #3\n-\tcmp\tr5, r3\n-\tblt.n\t1042 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x16a>\n-\tldr.w\tr5, [lr, #24]\n-\tadds\tr0, #5\n-\tadds\tr3, r4, #4\n-\tadd.w\tr4, ip, r5\n-\tsubs\tr4, #1\n-\tstr.w\tr4, [r2, r0, lsl #2]\n-\tcmp\tr3, r1\n-\tbgt.n\tf5c <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x84>\n-\tsub.w\tlr, r2, #8\n-\tsubs\tr4, r2, #4\n-\tb.n\tf42 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x6a>\n-\tcmp\tr1, #1\n-\tbgt.w\tf42 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x6a>\n-\tpop\t{r4, r5, r6, r7, pc}\n-\tnop\n+\tmovge\tr1, #1\n+\tsub.w\tlr, r4, #4\n+\tldr.w\tr2, [ip, r3, lsl #3]\n+\tadd\tr2, r0\n+\tsubs\tr2, #1\n+\tstr.w\tr2, [lr, r3, lsl #3]\n+\tadds\tr3, #1\n+\tcmp\tr1, r3\n+\tbge.n\tdce <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0xaa>\n+\tcmp\tr3, r5\n+\tble.n\td9c <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x78>\n+\tpop\t{r3, r4, r5, r6, r7, pc}\n+\tcmp\tr5, #1\n+\tbgt.n\td9c <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0+0x78>\n+\tpop\t{r3, r4, r5, r6, r7, pc}\n \n-00001058 <__gridxc_mesh3d_MOD_reducedata.isra.0>:\n+00000dec <__gridxc_mesh3d_MOD_reducedata.isra.0>:\n __gridxc_mesh3d_MOD_reducedata.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d10}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n@@ -1562,2066 +1360,2135 @@\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip, #1688]\t@ 0x698\n \tsub.w\tsp, sp, #18688\t@ 0x4900\n \tmov\tr8, r0\n \tsub\tsp, #44\t@ 0x2c\n \tmov\tr0, r2\n-\tldr.w\tr2, [pc, #1876]\t@ 17ec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x794>\n+\tldr.w\tr2, [pc, #1872]\t@ 157c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x790>\n+\tmov\tr7, r3\n+\tldr.w\tr3, [pc, #1868]\t@ 1580 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x794>\n \tadd.w\tr4, sp, #18688\t@ 0x4900\n-\tadds\tr4, #104\t@ 0x68\n-\tstr\tr3, [sp, #88]\t@ 0x58\n \tadd\tr2, pc\n-\tldr.w\tr3, [pc, #1864]\t@ 17f0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x798>\n-\tstr\tr1, [sp, #32]\n+\tstr\tr1, [sp, #36]\t@ 0x24\n \tadd.w\tr1, sp, #18688\t@ 0x4900\n+\tadds\tr4, #104\t@ 0x68\n \tadds\tr1, #36\t@ 0x24\n-\tldr\tr4, [r4, #0]\n \tldr\tr3, [r2, r3]\n+\tldr\tr4, [r4, #0]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r1, #0]\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1844]\t@ 17f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x79c>\n+\tldr.w\tr3, [pc, #1840]\t@ 1584 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x798>\n \tadd\tr3, pc\n \tstr\tr3, [sp, #24]\n \tadd.w\tr3, sp, #18688\t@ 0x4900\n \tadds\tr3, #108\t@ 0x6c\n \tldr\tr3, [r3, #0]\n \tcmp\tr4, #0\n-\tbeq.w\t11f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x19c>\n+\tbeq.w\tf8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1a0>\n \tldr\tr5, [r4, #0]\n-\tstr\tr5, [sp, #56]\t@ 0x38\n+\tstr\tr5, [sp, #60]\t@ 0x3c\n \tcmp\tr5, #0\n-\tbeq.w\t2020 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfc8>\n+\tbeq.w\t1e2a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x103e>\n \tldr\tr2, [r4, #24]\n \tcmp\tr2, #0\n \tit\teq\n \tmoveq\tr2, #1\n-\tstr\tr2, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #104]\t@ 0x68\n \tldrd\tr1, r2, [r4, #64]\t@ 0x40\n \tsubs\tr2, r2, r1\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n \tldrd\tr2, r1, [r4, #28]\n \tsubs\tr2, r1, r2\n \tstr\tr2, [sp, #44]\t@ 0x2c\n \tldrd\tr2, r1, [r4, #40]\t@ 0x28\n-\tsubs\tr2, r1, r2\n-\tstr\tr2, [sp, #48]\t@ 0x30\n+\tsub.w\tsl, r1, r2\n \tldrd\tr2, r1, [r4, #52]\t@ 0x34\n-\tsubs\tr6, r1, r2\n+\tsub.w\tfp, r1, r2\n \tldr\tr2, [r4, #60]\t@ 0x3c\n \tldr\tr1, [r4, #36]\t@ 0x24\n-\tstr\tr1, [sp, #152]\t@ 0x98\n+\tstr\tr1, [sp, #160]\t@ 0xa0\n \tldr\tr1, [r4, #48]\t@ 0x30\n \tmov\tr4, r5\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr2, [sp, #80]\t@ 0x50\n \tnegs\tr2, r2\n \tstr\tr1, [sp, #20]\n-\tstr\tr2, [sp, #148]\t@ 0x94\n+\tstr\tr2, [sp, #156]\t@ 0x9c\n \tcmp\tr3, #0\n-\tbeq.n\t11fa <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1a2>\n+\tbeq.n\tf92 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1a6>\n \tldr\tr2, [r3, #0]\n \tstr\tr2, [sp, #28]\n-\tcbz\tr2, 114a <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf2>\n+\tcbz\tr2, ee0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf4>\n \tldr\tr2, [r3, #24]\n-\tstr\tr2, [sp, #64]\t@ 0x40\n+\tstr\tr2, [sp, #68]\t@ 0x44\n \tcmp\tr2, #0\n-\tbeq.w\t2012 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfba>\n+\tbeq.w\t1e1c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1030>\n \tnegs\tr2, r2\n-\tstr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #88]\t@ 0x58\n \tldr\tr2, [sp, #28]\n \torrs\tr4, r2\n \tldrd\tr1, r2, [r3, #28]\n \tsubs\tr2, r2, r1\n-\tadd.w\tsl, r2, #1\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #64]\t@ 0x40\n \tldrd\tr2, r1, [r3, #40]\t@ 0x28\n \tldr\tr3, [r3, #36]\t@ 0x24\n-\tsub.w\tfp, r1, r2\n-\tstr\tr3, [sp, #80]\t@ 0x50\n+\tsubs\tr2, r1, r2\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #56]\t@ 0x38\n \tldr\tr3, [r0, #24]\n-\tldrd\tr7, r5, [r0, #28]\n+\tldrd\tr6, r5, [r0, #28]\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr3, #1\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tldr\tr3, [r0, #0]\n \tstr\tr3, [sp, #52]\t@ 0x34\n \tldr\tr3, [r0, #36]\t@ 0x24\n \tstr\tr3, [sp, #16]\n \tldr\tr3, [r0, #48]\t@ 0x30\n \tstr\tr3, [sp, #12]\n \tldr\tr3, [r0, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #144]\t@ 0x90\n+\tstr\tr3, [sp, #152]\t@ 0x98\n \tldr\tr3, [r0, #68]\t@ 0x44\n \tstr\tr3, [sp, #8]\n \tldr\tr3, [r0, #64]\t@ 0x40\n \tldrd\tr1, ip, [r0, #40]\t@ 0x28\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #32]\n \tldrd\tlr, r2, [r0, #52]\t@ 0x34\n \tcmp\tr4, #0\n-\tbeq.w\t2216 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11be>\n-\tldr.w\tr0, [pc, #1656]\t@ 17f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>\n-\tsubs\tr3, r5, r7\n-\tstr\tr3, [sp, #132]\t@ 0x84\n+\tbeq.w\t202e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n+\tldr.w\tr0, [pc, #1648]\t@ 1588 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x79c>\n+\tsubs\tr3, r5, r6\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n \tsub.w\tr3, ip, r1\n-\tldr\tr1, [sp, #32]\n+\tldr\tr1, [sp, #36]\t@ 0x24\n \tadd\tr0, pc\n-\tstr\tr3, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #144]\t@ 0x90\n \tsub.w\tr3, r2, lr\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #148]\t@ 0x94\n \tadd.w\tr3, sp, #15680\t@ 0x3d40\n \tadds\tr3, #44\t@ 0x2c\n-\tstr\tr6, [sp, #4]\n+\tstr.w\tsl, [sp, #4]\n \tmov\tr2, r3\n \tmov\tr4, r1\n \tmov\tr5, r3\n \tadd.w\tr9, r1, #24\n-\tmovs\tr7, #0\n-\tmov\tr6, r0\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tmovs\tr6, #0\n+\tmov\tsl, r0\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tstr\tr3, [r2, #32]\n-\tldr\tr3, [sp, #136]\t@ 0x88\n+\tldr\tr3, [sp, #144]\t@ 0x90\n \tstr\tr3, [r2, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tldr\tr3, [sp, #148]\t@ 0x94\n \tstr\tr3, [r2, #56]\t@ 0x38\n \tldrd\tr3, r1, [r4]\n-\tstr\tr7, [r2, #28]\n-\tstr\tr7, [r2, #40]\t@ 0x28\n-\tstr\tr7, [r2, #52]\t@ 0x34\n+\tstr\tr6, [r2, #28]\n+\tstr\tr6, [r2, #40]\t@ 0x28\n+\tstr\tr6, [r2, #52]\t@ 0x34\n \tsubs\tr1, r1, r3\n \tldrd\tr0, r3, [r5, #28]\n \tsubs\tr3, r3, r0\n \tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr1, r3\n-\tblt.n\t11fe <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1a6>\n-\tldr.w\tr3, [pc, #1572]\t@ 17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>\n+\tblt.n\tf96 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1aa>\n+\tldr.w\tr3, [pc, #1564]\t@ 158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>\n \tmovs\tr1, #57\t@ 0x39\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tmov\tr0, r6\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tmov\tr0, sl\n \tldr\tr2, [sp, #24]\n \tadds\tr4, #8\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp\tr4, r9\n-\tbeq.n\t1206 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1ae>\n-\tldr\tr2, [sp, #72]\t@ 0x48\n+\tcmp\tr9, r4\n+\tbeq.n\tf9e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1b2>\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tadds\tr5, #12\n-\tb.n\t11ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x156>\n-\tstr\tr4, [sp, #56]\t@ 0x38\n+\tb.n\tf46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x15a>\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n \tcmp\tr3, #0\n-\tbne.n\t111c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc4>\n+\tbne.n\teb2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc6>\n \tstr\tr3, [sp, #28]\n-\tb.n\t114a <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf2>\n+\tb.n\tee0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf4>\n \tadds\tr4, #8\n \tadds\tr5, #12\n \tcmp\tr9, r4\n-\tbne.n\t11ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x156>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr6, [sp, #4]\n+\tbne.n\tf46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x15a>\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tsl, [sp, #4]\n \tcmp\tr3, #0\n-\tbeq.n\t129c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x244>\n-\tldr.w\tr0, [pc, #1520]\t@ 1800 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a8>\n-\tmovs\tr7, #0\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tbeq.n\t1032 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x246>\n+\tldr.w\tr0, [pc, #1508]\t@ 1590 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>\n+\tmov\tr4, r7\n+\tldr\tr2, [sp, #100]\t@ 0x64\n+\tadd.w\tr9, r7, #24\n \tadd\tr0, pc\n-\tstr.w\tfp, [sp, #4]\n-\tmov\tr4, r3\n-\tmov\tfp, sl\n+\tstr.w\tr8, [sp, #4]\n \tmov\tr5, r2\n-\tadd.w\tr9, r3, #24\n-\tmov\tsl, r0\n+\tmov\tr8, r7\n+\tmovs\tr6, #0\n+\tmov\tr7, r0\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tstr\tr3, [r2, #32]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr3, [r2, #44]\t@ 0x2c\n \tldrd\tr3, r1, [r4]\n-\tstr\tr7, [r2, #28]\n-\tstr\tr7, [r2, #40]\t@ 0x28\n-\tstrd\tr7, r6, [r2, #52]\t@ 0x34\n+\tstr\tr6, [r2, #28]\n+\tstrd\tr6, sl, [r2, #40]\t@ 0x28\n+\tstrd\tr6, fp, [r2, #52]\t@ 0x34\n \tsubs\tr1, r1, r3\n \tldrd\tr0, r3, [r5, #28]\n \tsubs\tr3, r3, r0\n \tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr1, r3\n-\tblt.w\t2026 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfce>\n-\tldr.w\tr3, [pc, #1448]\t@ 17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>\n+\tblt.w\t1206 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x41a>\n+\tldr.w\tr3, [pc, #1440]\t@ 158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>\n \tmovs\tr1, #57\t@ 0x39\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tmov\tr0, sl\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tmov\tr0, r7\n \tldr\tr2, [sp, #24]\n \tadds\tr4, #8\n \tadds\tr5, #12\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr4, r9\n-\tbne.n\t122a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1d2>\n-\tmov\tsl, fp\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tldrd\tfp, r3, [sp, #4]\n+\tbne.n\tfc2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1d6>\n+\tmov\tr7, r8\n+\tldr\tr2, [sp, #32]\n+\tldrd\tr8, r3, [sp, #4]\n \tsubs\tr3, r3, r2\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n \tadds\tr3, #1\n \tbic.w\tr2, r2, r2, asr #31\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r2\n-\tbeq.n\t129c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x244>\n-\tldr.w\tr3, [pc, #1392]\t@ 17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>\n+\tbeq.n\t1032 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x246>\n+\tldr.w\tr3, [pc, #1388]\t@ 158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>\n \tmovs\tr1, #65\t@ 0x41\n \tldr\tr2, [sp, #24]\n-\tldr.w\tr0, [pc, #1392]\t@ 1804 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7ac>\n+\tldr.w\tr0, [pc, #1388]\t@ 1594 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a8>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr3, [sp, #28]\n \tcmp\tr3, #0\n-\tbeq.w\t2450 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13f8>\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tldrd\tr2, r3, [r0]\n+\tbeq.w\t225a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x146e>\n+\tldrd\tr2, r3, [r7]\n \tsubs\tr1, r3, r2\n-\tldrd\tr2, r3, [r0, #8]\n+\tldrd\tr2, r3, [r7, #8]\n \tadds\tr1, #1\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n \tcmp\tr1, r3\n \tit\tlt\n \tmovlt\tr1, r3\n-\tldrd\tr2, r3, [r0, #16]\n+\tldrd\tr2, r3, [r7, #16]\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n \tcmp\tr1, r3\n \tit\tlt\n \tmovlt\tr1, r3\n-\tadd.w\tr3, fp, #1\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadds\tr3, #1\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r1\n-\tbge.n\t12ea <__gridxc_mesh3d_MOD_reducedata.isra.0+0x292>\n-\tldr.w\tr3, [pc, #1316]\t@ 17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>\n+\tbge.n\t107e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x292>\n+\tldr.w\tr3, [pc, #1312]\t@ 158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>\n \tmovs\tr1, #56\t@ 0x38\n \tldr\tr2, [sp, #24]\n-\tldr.w\tr0, [pc, #1320]\t@ 1808 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b0>\n+\tldr.w\tr0, [pc, #1316]\t@ 1598 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7ac>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldrd\tr7, r9, [r8, #4]\n+\tldrd\tr6, r9, [r8, #4]\n \tldr.w\tr3, [r8]\n \tstr\tr3, [sp, #4]\n-\tcmp\tr3, r7\n+\tcmp\tr3, r6\n \tit\tlt\n-\tmovlt\tr3, r7\n+\tmovlt\tr3, r6\n \tcmp\tr3, r9\n \tit\tlt\n \tmovlt\tr3, r9\n \tmov\tr5, r3\n \tcmp\tr3, #0\n \tbic.w\tr4, r3, r3, asr #31\n-\tble.w\t2466 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x140e>\n-\tmvn.w\tr3, #2147483648\t@ 0x80000000\n-\tudiv\tr3, r3, r4\n+\tble.w\t2270 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1484>\n+\tmov\tr1, r4\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n \tadd.w\tr4, r4, r4, lsl #1\n-\tcmp\tr3, #2\n-\tble.w\t246e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1416>\n+\tcmp\tr0, #2\n+\tble.w\t2278 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x148c>\n \tcmp.w\tr4, #536870912\t@ 0x20000000\n-\tit\tlt\n+\titt\tlt\n \tlsllt\tr4, r4, #3\n-\tit\tlt\n \tmovlt\tr0, r4\n-\tbge.w\t246e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1416>\n+\tbge.w\t2278 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x148c>\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [sp, #8]\n \tcmp\tr0, #0\n-\tbeq.w\t2476 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x141e>\n+\tbeq.w\t2280 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1494>\n \tsubs\tr3, r5, #1\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n-\tvmov\ts15, r7\n-\tldr\tr3, [sp, #32]\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n+\tstr\tr3, [sp, #168]\t@ 0xa8\n+\tvmov\ts15, r6\n+\tvldr\ts11, [sp, #4]\n+\tldr\tr2, [sp, #36]\t@ 0x24\n \tadd\tr5, sp, #808\t@ 0x328\n-\tvcvt.f64.s32\td17, s15\n+\tvcvt.f64.s32\td6, s15\n \tvmov\ts15, r9\n-\tsub.w\tr2, r5, #88\t@ 0x58\n-\tstr.w\tsl, [sp, #72]\t@ 0x48\n-\tvcvt.f64.s32\td16, s15\n-\tvldr\ts15, [sp, #4]\n-\tmov\tr9, r2\n-\tmovs\tr7, #12\n-\tvdiv.f64\td9, d18, d17\n-\tmov\tsl, r8\n-\tvcvt.f64.s32\td19, s15\n-\tstr\tr2, [sp, #128]\t@ 0x80\n-\tvdiv.f64\td10, d18, d16\n-\tstr.w\tfp, [sp, #44]\t@ 0x2c\n-\tvdiv.f64\td8, d18, d19\n-\tvld1.32\t{d18-d19}, [r3]!\n-\tvld1.32\t{d16}, [r3]\n-\taddw\tr3, sp, #2344\t@ 0x928\n+\tvcvt.f64.s32\td4, s11\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvcvt.f64.s32\td7, s15\n+\tldr.w\tr3, [pc, #1192]\t@ 159c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b0>\n+\tsub.w\tr1, r5, #88\t@ 0x58\n+\tsub.w\tip, r5, #80\t@ 0x50\n+\tvdiv.f64\td10, d5, d6\n+\tadd\tr3, pc\n+\tvdiv.f64\td8, d5, d4\n \tstr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [r2, #8]\n+\tmov\tr9, r1\n+\tvdiv.f64\td9, d5, d7\n+\tstr.w\tr3, [r5, #-80]\n+\tldr\tr3, [r2, #12]\n+\tmov\tfp, ip\n+\tstr.w\tr3, [r5, #-76]\n+\tldr\tr3, [r2, #16]\n+\tstr.w\tr3, [r5, #-72]\n+\tldr\tr3, [r2, #20]\n+\tstr.w\tr3, [r5, #-68]\n+\tldr\tr3, [r2, #0]\n+\tstr.w\tr3, [r5, #-88]\n+\tldr\tr3, [r2, #4]\n+\tstr.w\tr3, [r5, #-84]\n+\tmovs\tr3, #12\n+\tstr\tr1, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #32]\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tvst1.64\t{d18-d19}, [r2 :64]\n-\tvstr\td16, [r2, #16]\n-\tsub.w\tr3, r5, #76\t@ 0x4c\n-\tmov.w\tfp, #6\n-\tb.n\t1414 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3bc>\n-\tvldr\ts15, [r3]\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d9\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t13c6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x36e>\n-\tsubs\tr4, #1\n-\tldr.w\tr2, [sl, #4]\n-\tldr.w\tr1, [r3, #-4]\n-\tmul.w\tr4, r2, r4\n-\tcmp\tr4, r1\n-\tbgt.n\t1450 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3f8>\n-\tvldr\ts15, [r3, #8]\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d10\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tsub.w\tr3, r5, #84\t@ 0x54\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tsub.w\tr0, r5, #76\t@ 0x4c\n+\tmovs\tr3, #6\n+\tb.n\t11c6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3da>\n+\tvldr\ts15, [r0]\n+\tldr.w\tr1, [r8, #4]\n+\tldr.w\tr2, [r0, #-4]\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d10\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr4, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t13fa <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3a2>\n-\tsubs\tr4, #1\n-\tldr.w\tr1, [sl, #8]\n-\tldr\tr0, [r3, #4]\n+\tit\tmi\n+\taddmi.w\tr4, r4, #4294967295\t@ 0xffffffff\n \tmul.w\tr4, r1, r4\n-\tcmp\tr4, r0\n-\tbgt.w\t2034 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfdc>\n-\tadd.w\tfp, fp, #6\n-\tadds\tr3, #24\n-\tcmp\tfp, r7\n-\tbeq.n\t14de <__gridxc_mesh3d_MOD_reducedata.isra.0+0x486>\n-\tvldr\ts15, [r3, #-8]\n-\tmov\tr8, r3\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d8\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n+\tcmp\tr4, r2\n+\tbgt.w\t1e30 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1044>\n+\tvldr\ts15, [r0, #8]\n+\tldr.w\tr2, [r8, #8]\n+\tldr\tr6, [r0, #4]\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d9\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr4, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t143a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3e2>\n-\tsubs\tr4, #1\n+\tit\tmi\n+\taddmi.w\tr4, r4, #4294967295\t@ 0xffffffff\n+\tmul.w\tr4, r2, r4\n+\tcmp\tr4, r6\n+\tbgt.w\t1426 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x63a>\n+\tldr\tr4, [sp, #32]\n+\tadds\tr3, #6\n+\tadds\tr0, #24\n+\tcmp\tr4, r3\n+\tbeq.n\t1212 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x426>\n+\tvldr\ts15, [r0, #-8]\n+\tmov\tr6, r0\n \tldr\tr2, [sp, #4]\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d8\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr4, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tmi\n+\taddmi.w\tr4, r4, #4294967295\t@ 0xffffffff\n \tmul.w\tr4, r2, r4\n-\tldr.w\tr2, [r3, #-12]\n+\tldr.w\tr2, [r0, #-12]\n \tcmp\tr4, r2\n-\tble.n\t13a2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x34a>\n-\tsub.w\tr8, r3, #8\n-\tmovs\tr6, #2\n-\tb.n\t1452 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3fa>\n-\tmovs\tr6, #4\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tr3, #125\t@ 0x7d\n-\tble.n\t1472 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x41a>\n-\tldr\tr3, [pc, #924]\t@ (17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>)\n-\tmovs\tr1, #46\t@ 0x2e\n-\tldr\tr2, [sp, #24]\n-\tldr\tr0, [pc, #936]\t@ (180c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b4>)\n-\tldr\tr3, [r2, r3]\n-\tadd\tr0, pc\n-\tldr\tr3, [r3, #0]\n-\tblx\tr3\n-\tldr.w\tr3, [sl]\n-\tstr\tr3, [sp, #4]\n-\tadds\tr1, r7, r6\n-\tadd.w\tr3, sp, #18688\t@ 0x4900\n-\tadds\tr3, #40\t@ 0x28\n-\tsub.w\tfp, fp, #6\n-\tadd.w\tr1, r3, r1, lsl #2\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tsub.w\tr1, r1, #17920\t@ 0x4600\n-\tadds\tr7, #6\n-\tadd.w\tr9, r9, #24\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9]\n-\tsub.w\tr3, r5, #84\t@ 0x54\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9, #4]\n-\tsub.w\tr3, r5, #80\t@ 0x50\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9, #8]\n-\tsub.w\tr3, r5, #76\t@ 0x4c\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9, #12]\n-\tsub.w\tr3, r5, #72\t@ 0x48\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9, #16]\n-\tsub.w\tr3, r5, #68\t@ 0x44\n-\tldr.w\tr3, [r3, fp, lsl #2]\n-\tstr.w\tr3, [r9, #20]\n-\tstr.w\tr4, [r1, #-120]\n-\tsubs\tr4, #1\n-\tstr.w\tr4, [r8]\n-\tb.n\t1398 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x340>\n-\tvmov\ts15, r2\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tble.n\t114e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x362>\n+\tsub.w\tr6, r0, #8\n+\tmov.w\tsl, #2\n+\tb.n\t142e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x642>\n+\tadds\tr4, #8\n+\tadds\tr5, #12\n+\tcmp\tr4, r9\n+\tbne.w\tfc2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1d6>\n+\tb.n\t1004 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x218>\n+\tmov\tsl, r2\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n \tmovs\tr3, #24\n-\tmov\tr8, sl\n-\tadd.w\tr0, sp, #12736\t@ 0x31c0\n-\tsub.w\tip, r8, #4\n-\tadds\tr0, #8\n-\tldr.w\tfp, [sp, #44]\t@ 0x2c\n+\tvmov\ts16, r1\n+\tldr\tr1, [sp, #136]\t@ 0x88\n+\tadd.w\tr4, sp, #12736\t@ 0x31c0\n+\tadds\tr4, #8\n+\tmvn.w\tr5, #6\n \tmul.w\tr2, r3, r2\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tsub.w\tr4, r0, #12\n-\tmov\tlr, ip\n-\tadds\tr3, #8\n-\tmvn.w\tr7, #6\n-\tadds\tr5, r3, r2\n-\tmov\tr6, r2\n-\tldr.w\tsl, [sp, #72]\t@ 0x48\n-\tstr\tr0, [sp, #72]\t@ 0x48\n-\tstr.w\tr8, [sp, #36]\t@ 0x24\n-\tsub.w\tr9, r5, r6\n-\tmov\tr8, ip\n-\tldr.w\tr3, [lr, #4]!\n-\tmov\tip, r4\n-\tb.n\t1558 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x500>\n-\tcmp\tr0, #0\n-\tblt.n\t158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x534>\n-\tsdiv\tr2, r0, r3\n-\tcmp\tr3, #0\n-\tmls\tr2, r3, r2, r0\n-\tstr.w\tr2, [r4, #-8]\n-\tldr.w\tr2, [r9, #-4]\n-\tblt.n\t157e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x526>\n-\tcmp\tr2, #0\n-\tblt.n\t1590 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x538>\n-\tsdiv\tr0, r2, r3\n-\tmls\tr0, r3, r0, r2\n-\tadd.w\tr9, r9, #24\n-\tstr.w\tr0, [r4, #-4]\n-\tcmp\tr5, r9\n-\tadd.w\tr4, r4, #24\n-\tbeq.n\t1594 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x53c>\n-\tldr.w\tr0, [r9, #-8]\n-\tcmp\tr3, #0\n-\tbge.n\t1524 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4cc>\n+\tadd.w\tr9, r1, #8\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tmov\tr1, r8\n+\tadd\tr9, r2\n+\tsub.w\tr2, r4, #12\n+\tsub.w\tr3, r8, #4\n+\tstr\tr7, [sp, #32]\n+\tmov\tr8, r2\n+\tmov\tr7, r5\n+\tmov\tr2, r1\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tstr\tr4, [sp, #44]\t@ 0x2c\n+\tldr.w\tr6, [r3, #4]!\n+\tvmov\ts17, sl\n+\tldr\tr1, [sp, #48]\t@ 0x30\n+\tmov\tr5, r8\n+\tmov\tsl, r6\n+\tmov\tfp, r2\n+\tsub.w\tr4, r9, r1\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tb.n\t12a2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4b6>\n+\tcmp\tr6, #0\n+\tblt.n\t12d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4e8>\n+\tmov\tr1, sl\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tmls\tr3, sl, r2, r6\n+\tcmp.w\tsl, #0\n+\tldr.w\tr6, [r4, #-4]\n+\tstr.w\tr3, [r5, #-8]\n+\tblt.n\t12c0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4d4>\n+\tcmp\tr6, #0\n+\tblt.n\t12d8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4ec>\n+\tmov\tr1, sl\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tmls\tr3, sl, r2, r6\n+\tadds\tr4, #24\n+\tstr.w\tr3, [r5, #-4]\n+\tcmp\tr9, r4\n+\tadd.w\tr5, r5, #24\n+\tbeq.n\t12dc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4f0>\n+\tldr.w\tr6, [r4, #-8]\n+\tcmp.w\tsl, #0\n+\tbge.n\t1262 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x476>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.n\t1266 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x47a>\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n \tsubs\tr2, r0, #1\n-\tcmp\tr0, #0\n-\tble.n\t1528 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4d0>\n-\tsdiv\tr2, r2, r3\n-\tcmp\tr3, #0\n-\tadd.w\tr2, r2, #4294967295\t@ 0xffffffff\n-\tmls\tr2, r3, r2, r0\n-\tstr.w\tr2, [r4, #-8]\n-\tldr.w\tr2, [r9, #-4]\n-\tbge.n\t153c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4e4>\n-\tsubs\tr0, r2, #1\n-\tcmp\tr2, #0\n-\tble.n\t1540 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4e8>\n-\tsdiv\tr0, r0, r3\n-\tsubs\tr0, #1\n-\tb.n\t1544 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4ec>\n-\tadds\tr2, r0, #1\n-\tb.n\t1566 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x50e>\n-\tadds\tr0, r2, #1\n-\tb.n\t1584 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x52c>\n-\tmov\tr4, ip\n+\tb.n\t1270 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x484>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.n\t1286 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x49a>\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr2, r0, #1\n+\tb.n\t1290 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4a4>\n+\tadds\tr0, r6, #1\n+\tb.n\t12b6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4ca>\n+\tadds\tr0, r6, #1\n+\tb.n\t12ca <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4de>\n \tadds\tr7, #2\n-\tmov\tip, r8\n-\tadds\tr4, #8\n-\tldr.w\tr8, [sp, #36]\t@ 0x24\n-\tadds\tr5, #8\n-\tadds\tr2, r7, #1\n-\tbne.n\t1512 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x4ba>\n-\tvcvt.f64.s32\td17, s15\n-\tvmov\ts15, r1\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvcvt.f64.s32\td16, s15\n-\tvldr\ts15, [sp, #4]\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tvmov\tsl, s17\n+\tmov\tr2, fp\n+\tadd.w\tr8, r8, #8\n+\tadd.w\tr9, r9, #8\n+\tadds\tr0, r7, #1\n+\tbne.n\t124a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x45e>\n+\tvldr\ts11, [sp, #4]\n+\tvcvt.f64.s32\td6, s16\n+\tvcvt.f64.s32\td7, s17\n \taddw\tr5, sp, #3752\t@ 0xea8\n-\tmovs\tr7, #12\n-\tvdiv.f64\td8, d18, d17\n-\tsub.w\tr1, r5, #32\n-\tvcvt.f64.s32\td19, s15\n-\tvmov\tr0, s15\n-\tvdiv.f64\td9, d18, d16\n-\tmov\tr9, r1\n-\tmov\tr2, r1\n-\tstr\tr1, [sp, #44]\t@ 0x2c\n-\tstrd\tfp, r6, [sp, #92]\t@ 0x5c\n-\tvdiv.f64\td10, d18, d19\n-\tstrd\tsl, ip, [sp, #100]\t@ 0x64\n-\tvld1.32\t{d18-d19}, [r3]!\n-\tvld1.32\t{d16}, [r3]\n+\tldr\tr7, [sp, #32]\n+\tsub.w\tr9, r5, #32\n+\tvcvt.f64.s32\td4, s11\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tldr\tr3, [pc, #652]\t@ (15a0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b4>)\n+\tmov\tr8, fp\n+\tvdiv.f64\td10, d5, d6\n+\tldr\tr4, [sp, #44]\t@ 0x2c\n+\tvdiv.f64\td9, d5, d7\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #96]\t@ 0x60\n+\tmov\tr2, r9\n+\tvdiv.f64\td8, d5, d4\n+\tldr\tr3, [r7, #8]\n+\tstr.w\tr3, [r9, #8]\n+\tldr\tr3, [r7, #12]\n+\tstr.w\tr3, [r9, #12]\n+\tldr\tr3, [r7, #16]\n+\tstr.w\tr3, [r9, #16]\n+\tldr\tr3, [r7, #20]\n+\tstr.w\tr3, [r9, #20]\n+\tldr\tr3, [r7, #0]\n+\tstr.w\tr3, [r5, #-32]\n+\tldr\tr3, [r7, #4]\n+\tstr.w\tr3, [r9, #4]\n+\tmovs\tr3, #12\n+\tstr.w\tr9, [sp, #92]\t@ 0x5c\n+\tstr\tr3, [sp, #32]\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tvst1.64\t{d18-d19}, [r1 :64]\n-\tvstr\td16, [r1, #16]\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tsub.w\tr3, r5, #28\n+\tstrd\tr3, r4, [sp, #108]\t@ 0x6c\n \tsub.w\tr3, r5, #20\n-\tmov.w\tsl, #6\n-\tb.n\t1678 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x620>\n+\tmov.w\tfp, #6\n+\tb.n\t13e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x5f8>\n \tvldr\ts15, [r3]\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d8\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t162a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x5d2>\n-\tsubs\tr4, #1\n \tldr.w\tr1, [r8, #4]\n-\tmul.w\tr4, r1, r4\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d10\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr6, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tmi\n+\taddmi.w\tr6, r6, #4294967295\t@ 0xffffffff\n+\tmul.w\tr6, r1, r6\n \tldr.w\tr1, [r3, #-4]\n-\tcmp\tr4, r1\n-\tbgt.n\t16b2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x65a>\n+\tcmp\tr6, r1\n+\tbgt.w\t1e16 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x102a>\n \tvldr\ts15, [r3, #8]\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d9\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t165e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x606>\n-\tsubs\tr4, #1\n \tldr.w\tr1, [r8, #8]\n-\tmul.w\tr4, r1, r4\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d9\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr6, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tmi\n+\taddmi.w\tr6, r6, #4294967295\t@ 0xffffffff\n+\tmul.w\tr6, r1, r6\n \tldr\tr1, [r3, #4]\n-\tcmp\tr4, r1\n-\tbgt.w\t2008 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfb0>\n-\tadd.w\tsl, sl, #6\n+\tcmp\tr6, r1\n+\tbgt.w\t1d8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfa0>\n+\tldr\tr1, [sp, #32]\n+\tadd.w\tfp, fp, #6\n \tadds\tr3, #24\n-\tcmp\tr7, sl\n-\tbeq.n\t1740 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x6e8>\n+\tcmp\tr1, fp\n+\tbeq.n\t14bc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x6d0>\n \tvldr\ts15, [r3, #-8]\n-\tmov\tfp, r3\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d10\n-\tvrintz.f64\td17, d16\n-\tvcvt.s32.f64\ts15, d16\n-\tvcmpe.f64\td16, d17\n-\tvmov\tr4, s15\n+\tmov\tr4, r3\n+\tldr\tr1, [sp, #4]\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d8\n+\tvcvt.s32.f64\ts13, d7\n+\tvmov\tr6, s13\n+\tvcvt.f64.s32\td6, s13\n+\tvcmpe.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t169e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x646>\n-\tsubs\tr4, #1\n-\tmul.w\tr4, r0, r4\n+\tit\tmi\n+\taddmi.w\tr6, r6, #4294967295\t@ 0xffffffff\n+\tmul.w\tr6, r1, r6\n \tldr.w\tr1, [r3, #-12]\n-\tcmp\tr4, r1\n-\tble.n\t1606 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x5ae>\n-\tsub.w\tfp, r3, #8\n-\tmovs\tr6, #2\n-\tb.n\t16b4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x65c>\n-\tmovs\tr6, #4\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tadds\tr3, #1\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tr3, #125\t@ 0x7d\n-\tble.n\t16d6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x67e>\n-\tldr\tr3, [pc, #316]\t@ (17fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a4>)\n+\tcmp\tr6, r1\n+\tble.n\t136a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x57e>\n+\tsub.w\tr4, r3, #8\n+\tmov.w\tsl, #2\n+\tb.w\t1d94 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfa8>\n+\tadd.w\tr6, r0, #8\n+\tmov.w\tsl, #6\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tadds\tr2, #1\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tcmp\tr2, #125\t@ 0x7d\n+\tble.n\t1450 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x664>\n+\tldr\tr2, [pc, #336]\t@ (158c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7a0>)\n \tmovs\tr1, #46\t@ 0x2e\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #24]\n-\tldr\tr0, [pc, #328]\t@ (1810 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b8>)\n-\tldr\tr3, [r2, r3]\n-\tadd\tr0, pc\n-\tldr\tr3, [r3, #0]\n-\tblx\tr3\n-\tldr.w\tr0, [r8]\n-\tldr\tr2, [sp, #4]\n-\tsub.w\tsl, sl, #6\n-\tadds\tr3, r7, r6\n-\tadd.w\tr1, sp, #18688\t@ 0x4900\n-\tadds\tr7, #6\n-\tadds\tr1, #40\t@ 0x28\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #24]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr2, [r3, r2]\n+\tldr\tr2, [r2, #0]\n+\tblx\tr2\n+\tldr.w\tr3, [r8]\n+\tstr\tr3, [sp, #4]\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr2, [sp, #32]\n+\tsubs\tr1, r3, #6\n \tadd.w\tr9, r9, #24\n-\tadd.w\tr3, r1, r3, lsl #2\n-\tldr.w\tr1, [r2, sl, lsl #2]\n-\tstr.w\tr1, [r9]\n-\tsub.w\tr1, r5, #28\n-\tsub.w\tr3, r3, #14976\t@ 0x3a80\n-\tldr.w\tr1, [r1, sl, lsl #2]\n-\tstr.w\tr1, [r9, #4]\n-\tsub.w\tr1, r5, #24\n-\tldr.w\tr1, [r1, sl, lsl #2]\n-\tstr.w\tr1, [r9, #8]\n-\tsub.w\tr1, r5, #20\n-\tldr.w\tr1, [r1, sl, lsl #2]\n-\tstr.w\tr1, [r9, #12]\n-\tsub.w\tr1, r5, #16\n-\tldr.w\tr1, [r1, sl, lsl #2]\n-\tstr.w\tr1, [r9, #16]\n-\tsub.w\tr1, r5, #12\n-\tldr.w\tr1, [r1, sl, lsl #2]\n+\tsub.w\tlr, r5, #76\t@ 0x4c\n+\tadd.w\tr3, r2, sl\n+\tadds\tr2, #6\n+\tstr\tr2, [sp, #32]\n+\tsub.w\tip, r5, #72\t@ 0x48\n+\tldr\tr2, [sp, #136]\t@ 0x88\n+\tadd.w\tr0, sp, #18688\t@ 0x4900\n+\tadds\tr0, #40\t@ 0x28\n+\tadd.w\tsl, r4, #4294967295\t@ 0xffffffff\n+\tadd.w\tr3, r0, r3, lsl #2\n+\tsub.w\tr0, r5, #68\t@ 0x44\n+\tldr.w\tr2, [r2, r1, lsl #2]\n+\tsub.w\tr3, r3, #17920\t@ 0x4600\n+\tstr.w\tr2, [r9]\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tldr.w\tr2, [r2, r1, lsl #2]\n+\tstr.w\tr2, [r9, #4]\n+\tldr.w\tr2, [fp, r1, lsl #2]\n+\tstr.w\tr2, [r9, #8]\n+\tldr.w\tr2, [lr, r1, lsl #2]\n+\tstr.w\tr2, [r9, #12]\n+\tldr.w\tr2, [ip, r1, lsl #2]\n+\tstr.w\tr2, [r9, #16]\n+\tldr.w\tr1, [r0, r1, lsl #2]\n \tstr.w\tr1, [r9, #20]\n-\tstr.w\tr4, [r3, #-64]\n-\tsubs\tr4, #1\n-\tstr.w\tr4, [fp]\n-\tb.n\t15fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x5a4>\n-\tldr\tr0, [sp, #36]\t@ 0x24\n+\tstr.w\tr4, [r3, #-120]\n+\tstr.w\tsl, [r6]\n+\tb.n\t1146 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x35a>\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n \tmovs\tr3, #24\n-\tmov\tr1, r2\n-\tadd.w\tr4, sp, #15680\t@ 0x3d40\n-\tldr.w\tfp, [sp, #92]\t@ 0x5c\n-\tadds\tr4, #52\t@ 0x34\n-\tldrd\tsl, ip, [sp, #100]\t@ 0x64\n-\tmul.w\tlr, r3, r0\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tadd.w\tr3, r1, #8\n-\tadd.w\tr5, r3, lr\n-\tmvn.w\tr7, #6\n-\tldr.w\tr3, [ip, #4]!\n-\tsub.w\tr6, r5, lr\n-\tmov\tr8, r4\n-\tb.n\t17a4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x74c>\n-\tcmp\tr0, #0\n-\tblt.n\t17de <__gridxc_mesh3d_MOD_reducedata.isra.0+0x786>\n-\tsdiv\tr9, r0, r3\n-\tcmp\tr3, #0\n-\tmls\tr0, r3, r9, r0\n-\tstr.w\tr0, [r8, #-8]\n-\tldr.w\tr0, [r6, #-4]\n-\tblt.n\t17cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x774>\n-\tcmp\tr0, #0\n-\tblt.n\t17e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x78c>\n-\tsdiv\tr9, r0, r3\n-\tmls\tr0, r3, r9, r0\n-\tadds\tr6, #24\n-\tstr.w\tr0, [r8, #-4]\n-\tcmp\tr5, r6\n-\tadd.w\tr8, r8, #24\n-\tbeq.n\t1814 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7bc>\n-\tldr.w\tr0, [r6, #-8]\n-\tcmp\tr3, #0\n-\tbge.n\t1772 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x71a>\n-\tadd.w\tr9, r0, #4294967295\t@ 0xffffffff\n-\tcmp\tr0, #0\n-\tble.n\t1776 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x71e>\n-\tsdiv\tr9, r9, r3\n-\tcmp\tr3, #0\n-\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n-\tmls\tr0, r3, r9, r0\n-\tstr.w\tr0, [r8, #-8]\n-\tldr.w\tr0, [r6, #-4]\n-\tbge.n\t178a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x732>\n-\tadd.w\tr9, r0, #4294967295\t@ 0xffffffff\n-\tcmp\tr0, #0\n-\tble.n\t178e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x736>\n-\tsdiv\tr9, r9, r3\n-\tadd.w\tr9, r9, #4294967295\t@ 0xffffffff\n-\tb.n\t1792 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x73a>\n-\tadd.w\tr9, r0, #1\n-\tb.n\t17b4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x75c>\n-\tadd.w\tr9, r0, #1\n-\tb.n\t17d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x77c>\n+\tadd.w\tr8, r9, #8\n+\tldr\tr4, [sp, #112]\t@ 0x70\n+\tstr\tr7, [sp, #4]\n+\tmvn.w\tfp, #6\n+\tstr.w\tr9, [sp, #32]\n+\tmul.w\tr2, r3, r2\n+\tstr\tr4, [sp, #44]\t@ 0x2c\n+\tmov\tr3, r2\n+\tadd\tr8, r2\n+\tadd.w\tr2, sp, #15680\t@ 0x3d40\n+\tmov\tr9, r3\n+\tadds\tr2, #52\t@ 0x34\n+\tmov\tr7, r2\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tsub.w\tsl, r8, r9\n+\tmov\tr4, r7\n+\tldr.w\tr5, [r3, #4]!\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tb.n\t1534 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x748>\n+\tcmp\tr6, #0\n+\tblt.n\t1572 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x786>\n+\tmov\tr0, r6\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tcmp\tr5, #0\n+\tmls\tr3, r5, r2, r6\n+\tldr.w\tr6, [sl, #-4]\n+\tstr.w\tr3, [r4, #-8]\n+\tblt.n\t155e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x772>\n+\tcmp\tr6, #0\n+\tblt.n\t1576 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x78a>\n+\tmov\tr1, r5\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr2, r0\n+\tmls\tr3, r5, r2, r6\n+\tadd.w\tsl, sl, #24\n+\tstr.w\tr3, [r4, #-4]\n+\tcmp\tr8, sl\n+\tadd.w\tr4, r4, #24\n+\tbeq.n\t15a4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7b8>\n+\tldr.w\tr6, [sl, #-8]\n+\tcmp\tr5, #0\n+\tbge.n\t14f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x708>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.n\t14f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x70c>\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr2, r0, #1\n+\tcmp\tr5, #0\n+\tmls\tr3, r5, r2, r6\n+\tldr.w\tr6, [sl, #-4]\n+\tstr.w\tr3, [r4, #-8]\n+\tbge.n\t1512 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x726>\n+\tcmp\tr6, #0\n+\tit\tgt\n+\taddgt.w\tr0, r6, #4294967295\t@ 0xffffffff\n+\tble.n\t1516 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x72a>\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tsubs\tr2, r0, #1\n+\tb.n\t1520 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x734>\n+\tadds\tr0, r6, #1\n+\tb.n\t1546 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x75a>\n+\tadds\tr0, r6, #1\n+\tb.n\t1568 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x77c>\n \tnop\n-\t.word\t0x00000746\n+\t.word\t0x00000740\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000730\n+\t.word\t0x0000072c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000668\n+\t.word\t0x00000662\n R_ARM_REL32\t.LC7\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000005e4\n+\t.word\t0x000005d8\n R_ARM_REL32\t.LC8\n-\t.word\t0x0000056a\n+\t.word\t0x00000564\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000520\n+\t.word\t0x0000051c\n R_ARM_REL32\t.LC10\n-\t.word\t0x000003a2\n+\t.word\t0x00000496\n R_ARM_REL32\t.LC12\n-\t.word\t0x00000142\n+\t.word\t0x0000027e\n R_ARM_REL32\t.LC12\n-\tadds\tr7, #2\n-\tadds\tr4, #8\n-\tadds\tr5, #8\n-\tadds\tr3, r7, #1\n-\tbne.n\t1766 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x70e>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr9, r1, lr\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tsub.w\tr3, r3, #2128\t@ 0x850\n-\tldr\tr7, [sp, #60]\t@ 0x3c\n-\tsub.w\tr8, r1, #20\n+\tadd.w\tfp, fp, #2\n+\tadds\tr7, #8\n+\tadd.w\tr8, r8, #8\n+\tcmp.w\tfp, #4294967295\t@ 0xffffffff\n+\tbne.n\t14e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x6f8>\n+\tmov\tr3, r9\n+\tldr.w\tr9, [sp, #32]\n \tldr\tr4, [sp, #44]\t@ 0x2c\n-\tadd\tr2, r8\n-\tstr\tr2, [sp, #156]\t@ 0x9c\n \tmovs\tr2, #0\n-\tstr\tr2, [r3, #0]\n-\tstr\tr2, [sp, #36]\t@ 0x24\n+\tadd\tr9, r3\n+\tstr\tr2, [sp, #216]\t@ 0xd8\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tsub.w\tr8, r4, #20\n+\tstr\tr2, [sp, #32]\n+\tldr\tr6, [sp, #100]\t@ 0x64\n+\tadd\tr3, r8\n+\tldr.w\tr2, [pc, #2160]\t@ 1e40 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1054>\n+\tldr.w\tsl, [sp, #92]\t@ 0x5c\n+\tldr\tr7, [sp, #4]\n+\tadd\tr2, pc\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n \tadd\tr3, sp, #296\t@ 0x128\n-\tldr.w\tr2, [pc, #2696]\t@ 22c8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1270>\n-\tstr\tr3, [sp, #180]\t@ 0xb4\n+\tstr\tr2, [sp, #196]\t@ 0xc4\n+\tstr\tr3, [sp, #188]\t@ 0xbc\n \tadd\tr3, sp, #220\t@ 0xdc\n-\tadd\tr2, pc\n-\tstr\tr3, [sp, #184]\t@ 0xb8\n-\tstr\tr2, [sp, #188]\t@ 0xbc\n-\tldr\tr3, [r7, #20]\n-\tmov\tr5, r8\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n-\tldr\tr3, [r7, #16]\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [r7, #12]\n-\tldr\tr6, [sp, #128]\t@ 0x80\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr3, [r7, #8]\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [r7, #4]\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tstrd\tfp, sl, [sp, #192]\t@ 0xc0\n-\tmov\tsl, r4\n-\tldr\tr3, [r7, #0]\n-\tstr.w\tr9, [sp, #200]\t@ 0xc8\n-\tmov\tr9, r6\n+\tstr\tr7, [sp, #200]\t@ 0xc8\n+\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tldr\tr3, [r6, #20]\n+\tmov\tfp, r8\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tldr\tr3, [r6, #16]\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr3, [r6, #12]\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tldr\tr3, [r6, #8]\n \tstr\tr3, [sp, #124]\t@ 0x7c\n-\tstrd\tr7, r8, [sp, #204]\t@ 0xcc\n-\tldr\tr3, [r5, #12]\n-\tldr\tr2, [r5, #0]\n-\tldr\tr4, [r5, #20]\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #136]\t@ 0x88\n+\tldr\tr3, [r6, #4]\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [r6, #0]\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tstrd\tr9, r6, [sp, #204]\t@ 0xcc\n+\tstr.w\tr8, [sp, #212]\t@ 0xd4\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tldr.w\tr4, [fp]\n+\tldr.w\tr2, [fp, #8]\n+\tcmp\tr3, r4\n+\tldr.w\tr1, [fp, #4]\n+\tit\tlt\n+\tmovlt\tr3, r4\n+\tstr\tr2, [sp, #184]\t@ 0xb8\n+\tmov\tr8, r3\n \tldr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [r5, #8]\n-\tstr\tr4, [sp, #48]\t@ 0x30\n+\tldr.w\tr0, [fp, #12]\n \tcmp\tr3, r2\n-\tldr\tr4, [sp, #104]\t@ 0x68\n+\tstr\tr1, [sp, #172]\t@ 0xac\n \tit\tlt\n \tmovlt\tr3, r2\n-\tldr\tr0, [r5, #16]\n-\tldr\tr6, [sp, #96]\t@ 0x60\n-\tcmp\tr4, r1\n-\tit\tlt\n-\tmovlt\tr4, r1\n-\tldr\tr7, [r5, #4]\n-\tcmp\tr6, r0\n-\tstr\tr1, [sp, #168]\t@ 0xa8\n-\tit\tlt\n-\tmovlt\tr6, r0\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tmov\tfp, r6\n-\tldr\tr6, [sp, #108]\t@ 0x6c\n-\tstr\tr7, [sp, #164]\t@ 0xa4\n-\tcmp\tr6, r7\n-\tstr\tr0, [sp, #172]\t@ 0xac\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tldrd\tr6, r7, [fp, #16]\n+\tcmp\tr2, r1\n \tit\tge\n-\tmovge\tr6, r7\n-\tldr\tr7, [sp, #100]\t@ 0x64\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tcmp\tr7, r1\n+\tmovge\tr2, r1\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tmov\tr9, r2\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tstr\tr0, [sp, #176]\t@ 0xb0\n+\tcmp\tr2, r0\n \tstr\tr3, [sp, #72]\t@ 0x48\n \tit\tge\n-\tmovge\tr7, r1\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tstr\tr4, [sp, #120]\t@ 0x78\n-\tcmp\tr0, r1\n-\tstr\tr6, [sp, #4]\n-\tit\tge\n-\tmovge\tr0, r1\n-\tcmp\tr7, r4\n-\tit\tge\n-\tcmpge\tr6, r3\n-\tmov\tr1, r6\n+\tmovge\tr2, r0\n+\tldr\tr0, [sp, #112]\t@ 0x70\n+\tcmp\tr1, r6\n+\tstr\tr7, [sp, #180]\t@ 0xb4\n \tit\tlt\n-\tmovlt\tr1, #1\n+\tmovlt\tr1, r6\n+\tcmp\tr0, r7\n \tit\tge\n-\tmovge\tr1, #0\n-\tcmp\tr0, fp\n+\tmovge\tr0, r7\n+\tcmp\tr9, r8\n \tit\tge\n+\tcmpge\tr2, r3\n+\tite\tlt\n+\tmovlt\tr3, #1\n \tmovge\tr3, #0\n+\tcmp\tr0, r1\n \tit\tlt\n-\tmovlt\tr3, #1\n-\tmov\tr8, r0\n-\torrs\tr3, r1\n-\tbne.w\t1a92 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xa3a>\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\torrlt.w\tr3, r3, #1\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #92]\t@ 0x5c\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tcmp\tr3, #0\n+\tbne.w\t183c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xa50>\n+\tldr\tr3, [sp, #32]\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #116]\t@ 0x74\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tcmp\tr3, #125\t@ 0x7d\n-\tble.n\t190a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x8b2>\n-\tldr.w\tr3, [pc, #2516]\t@ 22cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1274>\n+\tble.n\t1698 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x8ac>\n+\tldr.w\tr3, [pc, #1976]\t@ 1e44 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1058>\n \tmovs\tr1, #70\t@ 0x46\n-\tstr\tr2, [sp, #176]\t@ 0xb0\n \tldr\tr2, [sp, #24]\n-\tldr\tr0, [sp, #188]\t@ 0xbc\n+\tldr\tr0, [sp, #196]\t@ 0xc4\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [sp, #176]\t@ 0xb0\n-\tldr\tr1, [sp, #116]\t@ 0x74\n-\tmovs\tr0, #6\n-\tldr\tr3, [sp, #32]\n-\tadd.w\tr4, sp, #9664\t@ 0x25c0\n-\tadds\tr4, #60\t@ 0x3c\n-\tstr\tr4, [sp, #212]\t@ 0xd4\n-\tmul.w\tr0, r1, r0\n-\tldr.w\tr1, [r9]\n-\tvld1.32\t{d16-d17}, [r3]\n-\tsub.w\tlr, r0, #6\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tvorr\tq9, q8, q8\n-\tadd\tr1, r3\n-\tsubs\tr2, r1, r2\n-\tldr\tr3, [sp, #4]\n-\tstr.w\tr2, [r4, lr, lsl #2]\n-\tsubs\tr1, r0, #5\n-\tldr.w\tr2, [r9, #4]\n-\tmov\tr0, r1\n-\tstr\tr0, [sp, #176]\t@ 0xb0\n-\tlsls\tr1, r1, #2\n-\tadd\tr2, r3\n-\tldr\tr3, [sp, #164]\t@ 0xa4\n-\tvtrn.32\tq9, q8\n-\tadd.w\tip, r1, #12\n-\tsubs\tr2, r2, r3\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tstr.w\tr2, [r4, r0, lsl #2]\n-\tldr.w\tr2, [r9, #8]\n-\tldr\tr4, [sp, #168]\t@ 0xa8\n-\tadd\tr2, r3\n-\tldr\tr0, [sp, #172]\t@ 0xac\n-\tsubs\tr2, r2, r4\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tmov\tr6, r2\n-\tldr.w\tr2, [r9, #12]\n-\tvorr\tq8, q9, q9\n-\tadds\tr3, r1, #4\n-\tadd\tr2, r7\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tsubs\tr4, r2, r4\n-\tldr.w\tr2, [r9, #16]\n-\tstr\tr4, [sp, #164]\t@ 0xa4\n-\tadd\tr2, fp\n-\tldr\tr4, [sp, #48]\t@ 0x30\n-\tsubs\tr0, r2, r0\n-\tldr.w\tr2, [r9, #20]\n-\tadd\tr2, r8\n-\tsubs\tr2, r2, r4\n-\tmov\tr4, r6\n-\tldr\tr6, [sp, #212]\t@ 0xd4\n-\tstr\tr4, [r6, r3]\n-\tadd.w\tr4, r1, #8\n-\tmov\tr3, r4\n-\tstr\tr4, [sp, #48]\t@ 0x30\n-\tldr\tr4, [sp, #164]\t@ 0xa4\n-\tadds\tr1, #16\n-\tstr\tr1, [sp, #164]\t@ 0xa4\n-\tstr\tr4, [r6, r3]\n-\tmov\tr4, r6\n-\tldr\tr3, [sp, #32]\n-\tadd\tr4, ip\n-\tstr.w\tr0, [r6, ip]\n-\tstr\tr2, [r6, r1]\n-\tmov.w\tr1, lr, lsl #2\n-\tldr\tr2, [r3, #16]\n-\tvld1.32\t{d18}, [r4]\n-\tldr\tr0, [sp, #4]\n-\tvdup.32\td19, r2\n-\tadds\tr2, r6, r1\n-\tldr\tr6, [sp, #120]\t@ 0x78\n-\tvld1.32\t{d20-d21}, [r2]\n-\tsubs\tr3, r7, r6\n-\tvsub.i32\td18, d18, d19\n-\tadds\tr3, #1\n-\tvsub.i32\tq8, q10, q8\n-\tvst1.32\t{d16-d17}, [r2]\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tvst1.32\t{d18}, [r4]\n-\tsubs\tr2, r0, r2\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tmovs\tr1, #6\n+\tadd.w\tr2, sp, #9664\t@ 0x25c0\n+\tadds\tr2, #60\t@ 0x3c\n+\tmul.w\tr1, r3, r1\n+\tldr\tr3, [r5, #0]\n+\tadd\tr3, r8\n+\tsubs\tr0, r1, #5\n+\tsubs\tr3, r3, r4\n+\tsubs\tr4, r1, #6\n+\tstr\tr4, [sp, #96]\t@ 0x60\n+\tstr.w\tr3, [r2, r4, lsl #2]\n+\tlsls\tr3, r0, #2\n+\tadd.w\tip, r3, #8\n+\tadd.w\tr7, r3, #12\n+\tadd.w\tlr, r3, #16\n+\tadds\tr1, r3, #4\n+\tldr\tr3, [r5, #4]\n+\tstr\tr1, [sp, #4]\n+\tldr\tr1, [sp, #172]\t@ 0xac\n+\tadd\tr3, r9\n+\tldr\tr4, [sp, #72]\t@ 0x48\n+\tsubs\tr3, r3, r1\n+\tstr.w\tr3, [r2, r0, lsl #2]\n+\tldr\tr3, [r5, #8]\n+\tldr\tr1, [sp, #184]\t@ 0xb8\n+\tadd\tr3, r4\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tsubs\tr3, r3, r1\n+\tldr\tr1, [sp, #4]\n+\tstr\tr3, [r2, r1]\n+\tldr\tr1, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [r5, #12]\n+\tadd\tr3, r1\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tsubs\tr3, r3, r4\n+\tstr.w\tr3, [r2, ip]\n+\tldr\tr3, [r5, #16]\n \tldr\tr4, [sp, #180]\t@ 0xb4\n-\tldr\tr0, [sp, #36]\t@ 0x24\n-\tmla\tr3, r2, r3, r3\n-\tsub.w\tr2, r8, fp\n-\tmla\tr3, r2, r3, r3\n-\tsub.w\tr2, r4, #80\t@ 0x50\n-\tldr\tr4, [sp, #184]\t@ 0xb8\n-\tldr.w\tr2, [r2, r0, lsl #2]\n-\tadd\tr3, r2\n-\tstr.w\tr3, [r4, r0, lsl #2]\n-\tldr\tr3, [sp, #116]\t@ 0x74\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tadd\tr3, r1\n+\tsubs\tr3, r3, r6\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tstr\tr3, [r2, r7]\n+\tldr\tr3, [r5, #20]\n+\tadd\tr3, r6\n+\tsubs\tr3, r3, r4\n+\tstr.w\tr3, [r2, lr]\n+\tldr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr6, [r3, #0]\n+\tldr\tr4, [r3, #8]\n+\tstr\tr6, [sp, #172]\t@ 0xac\n+\tmov\tr6, r3\n+\tldr\tr3, [sp, #96]\t@ 0x60\n+\tstr\tr4, [sp, #176]\t@ 0xb0\n+\tldr\tr4, [sp, #172]\t@ 0xac\n+\tldr.w\tr3, [r2, r3, lsl #2]\n+\tsubs\tr3, r3, r4\n+\tldr\tr4, [sp, #96]\t@ 0x60\n+\tstr.w\tr3, [r2, r4, lsl #2]\n+\tldr\tr3, [r6, #16]\n+\tldr\tr6, [sp, #4]\n+\tstr\tr3, [sp, #180]\t@ 0xb4\n+\tldr\tr4, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tsubs\tr4, r3, r4\n+\tldr\tr3, [r2, r6]\n+\tldr\tr6, [sp, #176]\t@ 0xb0\n+\tadds\tr4, #1\n+\tsubs\tr3, r3, r6\n+\tldr\tr6, [sp, #4]\n+\tstr\tr3, [r2, r6]\n+\tsub.w\tr3, r9, r8\n+\tldr\tr6, [sp, #180]\t@ 0xb4\n+\tmla\tr4, r3, r4, r4\n+\tldr\tr3, [r2, r7]\n+\tsubs\tr3, r3, r6\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tstr\tr3, [r2, r7]\n+\tsubs\tr3, r6, r1\n+\tldr\tr6, [sp, #172]\t@ 0xac\n+\tldr\tr1, [sp, #188]\t@ 0xbc\n+\tmla\tr4, r3, r4, r4\n+\tldr.w\tr3, [r2, r0, lsl #2]\n+\tsubs\tr3, r3, r6\n+\tstr.w\tr3, [r2, r0, lsl #2]\n+\tsub.w\tr3, r1, #80\t@ 0x50\n+\tldr\tr1, [sp, #32]\n+\tldr.w\tr3, [r3, r1, lsl #2]\n+\tadd\tr4, r3\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tstr.w\tr4, [r3, r1, lsl #2]\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr4, [sp, #176]\t@ 0xb0\n+\tstr\tr3, [sp, #32]\n+\tldr.w\tr3, [r2, ip]\n+\tldr\tr1, [sp, #132]\t@ 0x84\n+\tsubs\tr3, r3, r4\n+\tldr.w\tr4, [sl]\n+\tstr.w\tr3, [r2, ip]\n \tadd.w\tr3, sp, #6720\t@ 0x1a40\n+\tadd\tr4, r8\n \tadds\tr3, #4\n-\tldr\tr0, [sp, #72]\t@ 0x48\n-\tldr.w\tr2, [sl]\n-\tadd\tr1, r3\n+\tsubs\tr4, r4, r1\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tstr.w\tr4, [r3, r1, lsl #2]\n+\tldr.w\tr4, [sl, #4]\n+\tldr\tr6, [sp, #180]\t@ 0xb4\n+\tadd.w\tr8, r9, r4\n+\tldr\tr4, [sp, #128]\t@ 0x80\n+\tldr\tr1, [sp, #44]\t@ 0x2c\n+\tsub.w\tr8, r8, r4\n+\tldr.w\tr4, [r2, lr]\n+\tstr.w\tr8, [r3, r0, lsl #2]\n+\tsubs\tr4, r4, r6\n+\tstr.w\tr4, [r2, lr]\n+\tldr\tr4, [sp, #72]\t@ 0x48\n+\tldr.w\tr2, [sl, #8]\n+\tldr\tr6, [sp, #4]\n+\tadd\tr2, r4\n \tldr\tr4, [sp, #124]\t@ 0x7c\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #4]\n \tsubs\tr2, r2, r4\n-\tstr.w\tr2, [r3, lr, lsl #2]\n-\tldr.w\tr2, [sl, #4]\n-\tldr\tr4, [sp, #108]\t@ 0x6c\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #176]\t@ 0xb0\n+\tstr\tr2, [r3, r6]\n+\tldr.w\tr2, [sl, #12]\n+\tldr\tr4, [sp, #120]\t@ 0x78\n+\tadd\tr2, r1\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n \tsubs\tr2, r2, r4\n-\tldr\tr4, [sp, #104]\t@ 0x68\n-\tstr.w\tr2, [r3, r0, lsl #2]\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tldr.w\tr2, [sl, #8]\n+\tstr.w\tr2, [r3, ip]\n+\tldr.w\tr2, [sl, #16]\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tadd\tr2, r1\n+\tldr\tr1, [sp, #116]\t@ 0x74\n+\tsubs\tr2, r2, r1\n+\tstr\tr2, [r3, r7]\n+\tldr.w\tr2, [sl, #20]\n+\tldr\tr1, [sp, #112]\t@ 0x70\n \tadd\tr2, r6\n+\tldr\tr6, [sp, #96]\t@ 0x60\n+\tsubs\tr2, r2, r1\n+\tldr\tr1, [sp, #200]\t@ 0xc8\n+\tstr.w\tr2, [r3, lr]\n+\tldr\tr4, [r1, #0]\n+\tldr.w\tr2, [r3, r6, lsl #2]\n+\tldr.w\tr8, [r1, #8]\n \tsubs\tr2, r2, r4\n-\tstr\tr2, [r3, r0]\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tldr.w\tr2, [sl, #12]\n-\tldr\tr4, [sp, #100]\t@ 0x64\n-\tadd\tr2, r7\n+\tstr.w\tr2, [r3, r6, lsl #2]\n+\tldr\tr6, [sp, #4]\n+\tldr\tr1, [r1, #16]\n+\tldr\tr2, [r3, r6]\n+\tsub.w\tr2, r2, r8\n+\tstr\tr2, [r3, r6]\n+\tldr\tr2, [r3, r7]\n+\tsubs\tr2, r2, r1\n+\tstr\tr2, [r3, r7]\n+\tldr.w\tr2, [r3, r0, lsl #2]\n \tsubs\tr2, r2, r4\n-\tstr\tr2, [r3, r0]\n-\tldr.w\tr2, [sl, #16]\n-\tldr\tr0, [sp, #96]\t@ 0x60\n-\tadd\tr2, fp\n-\tsubs\tr2, r2, r0\n+\tstr.w\tr2, [r3, r0, lsl #2]\n+\tldr.w\tr2, [r3, ip]\n+\tsub.w\tr2, r2, r8\n \tstr.w\tr2, [r3, ip]\n-\tldr.w\tr2, [sl, #20]\n-\tadd\tip, r3\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tadd\tr2, r8\n-\tsubs\tr2, r2, r0\n-\tldr\tr0, [sp, #164]\t@ 0xa4\n-\tstr\tr2, [r3, r0]\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tvld1.32\t{d20-d21}, [r1]\n-\tvld1.32\t{d18}, [ip]\n-\tvld1.32\t{d16-d17}, [r3]\n-\tldr\tr3, [r3, #16]\n-\tvorr\tq11, q8, q8\n-\tvtrn.32\tq11, q8\n-\tvsub.i32\tq8, q10, q11\n-\tvst1.32\t{d16-d17}, [r1]\n-\tvdup.32\td16, r3\n-\tvsub.i32\td16, d18, d16\n-\tvst1.32\t{d16}, [ip]\n-\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tldr.w\tr2, [r3, lr]\n+\tsubs\tr2, r2, r1\n+\tstr.w\tr2, [r3, lr]\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tadd.w\tfp, fp, #24\n \tadds\tr5, #24\n-\tadd.w\tr9, r9, #24\n-\tcmp\tr3, r5\n-\tbne.w\t1878 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x820>\n-\tldrd\tr7, r8, [sp, #204]\t@ 0xcc\n-\tmov\tr4, sl\n-\tldr.w\tr9, [sp, #200]\t@ 0xc8\n-\tadds\tr4, #24\n-\tldr.w\tfp, [sp, #192]\t@ 0xc0\n-\tadds\tr7, #24\n-\tldr.w\tsl, [sp, #196]\t@ 0xc4\n-\tcmp\tr9, r4\n-\tbne.w\t184c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7f4>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr3, fp\n+\tbne.w\t160c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x820>\n+\tldrd\tr9, r6, [sp, #204]\t@ 0xcc\n+\tadd.w\tsl, sl, #24\n+\tldr.w\tr8, [sp, #212]\t@ 0xd4\n+\tadds\tr6, #24\n+\tcmp\tr9, sl\n+\tbne.w\t15e8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x7fc>\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tcmp\tr3, #0\n-\tbeq.w\t2434 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13dc>\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tbeq.w\t223e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1452>\n+\tldr\tr3, [sp, #32]\n \tcmp\tr3, #0\n-\tble.w\t21c0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1168>\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tble.w\t1fd8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11ec>\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr3, #0\n-\tble.w\t2484 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x142c>\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr2, [sp, #40]\t@ 0x28\n+\tble.w\t228e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14a2>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #104]\t@ 0x68\n \tcmp\tr2, #1\n \tit\teq\n \tcmpeq\tr3, #1\n-\tbne.w\t22f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x129c>\n-\tldr\tr2, [sp, #36]\t@ 0x24\n+\tbne.w\t2108 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x131c>\n+\tldr\tr2, [sp, #32]\n \tadd.w\tr0, sp, #6720\t@ 0x1a40\n \tadds\tr0, #4\n \tmovs\tr3, #24\n-\tstr.w\tfp, [sp, #96]\t@ 0x60\n \tldr.w\tfp, [sp, #16]\n+\tstr\tr0, [sp, #72]\t@ 0x48\n \tmla\tlr, r3, r2, r0\n-\tldr\tr2, [sp, #152]\t@ 0x98\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n \tadd.w\tr3, sp, #9664\t@ 0x25c0\n-\tstr\tr0, [sp, #72]\t@ 0x48\n \tmov\tr4, lr\n \tmov\tlr, r2\n \tmov.w\tr9, r2, lsl #3\n \tadds\tr3, #60\t@ 0x3c\n-\tstr.w\tsl, [sp, #100]\t@ 0x64\n \tstr\tr3, [sp, #104]\t@ 0x68\n \tldrd\tr8, r5, [r0, #16]\n \tldrd\tr1, r6, [r0, #8]\n \tcmp\tr5, r8\n-\tblt.n\t1bf4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb9c>\n+\tblt.n\t198e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xba2>\n \tcmp\tr6, r1\n-\tblt.n\t1bf4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb9c>\n+\tblt.n\t198e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xba2>\n \tldrd\tr7, ip, [r0]\n \tcmp\tip, r7\n-\tblt.n\t1bf4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb9c>\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tblt.n\t198e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xba2>\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tadds\tr5, #1\n \tadds\tr6, #1\n \tstrd\tr4, r3, [sp, #108]\t@ 0x6c\n \tsubs\tr6, r6, r1\n \tadd.w\tip, r2, ip, lsl #3\n \tadd.w\tr7, r2, r7, lsl #3\n \tadd.w\tr2, ip, #8\n \tstr\tr2, [sp, #48]\t@ 0x30\n \tsub.w\tr2, r5, r8\n \tstr\tr2, [sp, #44]\t@ 0x2c\n \tldr\tr2, [sp, #20]\n-\tldr\tr5, [sp, #148]\t@ 0x94\n+\tldr\tr5, [sp, #156]\t@ 0x9c\n \tmul.w\tr2, r2, r8\n \tmla\tr2, r1, lr, r2\n \tldr\tr1, [sp, #12]\n-\tstr\tr2, [sp, #92]\t@ 0x5c\n+\tstr\tr2, [sp, #96]\t@ 0x60\n \tldr\tr2, [r3, #16]\n \tmul.w\tr2, r1, r2\n \tldr\tr1, [r3, #8]\n \tmla\tr2, r1, fp, r2\n \tldr\tr1, [sp, #52]\t@ 0x34\n-\tstr\tr2, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #92]\t@ 0x5c\n \tldr\tr2, [r3, #0]\n \tadd.w\tip, r1, r2, lsl #3\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #80]\t@ 0x50\n \tmovs\tr2, #0\n \tadd\tr1, r5\n \tmov\tr5, r2\n-\tldr\tr4, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #92]\t@ 0x5c\n \tmov.w\tsl, #0\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #96]\t@ 0x60\n \tadd.w\tr8, r4, r2\n \tstrd\tr0, r2, [sp, #116]\t@ 0x74\n \tadd\tr3, r1\n \tmov\tr2, r8\n \tstrd\tr1, r5, [sp, #124]\t@ 0x7c\n \tldr\tr1, [sp, #48]\t@ 0x30\n \tmov\tr8, r2\n \tmov\tr5, r3\n \tmovs\tr4, #0\n \tstr\tr2, [sp, #4]\n \tadd.w\tr0, r1, r3, lsl #3\n \tadd.w\tr2, r7, r5, lsl #3\n \tadd.w\tr1, ip, r8, lsl #3\n-\tvldr\td17, [r2]\n-\tvldmia\tr1!, {d16}\n-\tvadd.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n+\tvldr\td6, [r2]\n+\tvldmia\tr1!, {d7}\n+\tvadd.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n \tcmp\tr0, r2\n-\tbne.n\t1ba4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb4c>\n+\tbne.n\t193e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb52>\n \tadds\tr4, #1\n \tadd\tr5, lr\n \tadd\tr8, fp\n \tadd\tr0, r9\n \tcmp\tr6, r4\n-\tbne.n\t1b9c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb44>\n+\tbne.n\t1936 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb4a>\n \tldr\tr1, [sp, #20]\n \tadd.w\tsl, sl, #1\n \tldr\tr2, [sp, #4]\n \tadd\tr3, r1\n \tldr\tr1, [sp, #12]\n \tadd\tr2, r1\n \tldr\tr1, [sp, #44]\t@ 0x2c\n \tcmp\tr1, sl\n-\tbne.n\t1b8e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb36>\n+\tbne.n\t1928 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb3c>\n \tldrd\tr1, r5, [sp, #124]\t@ 0x7c\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tldrd\tr0, r2, [sp, #116]\t@ 0x74\n \tadd\tr1, r3\n-\tldr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #152]\t@ 0x98\n \tadds\tr5, #1\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr3, r5\n-\tbne.n\t1b76 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb1e>\n+\tbne.n\t1910 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xb24>\n \tldrd\tr4, r3, [sp, #108]\t@ 0x6c\n \tadds\tr0, #24\n \tadds\tr3, #24\n \tcmp\tr4, r0\n-\tbne.n\t1b10 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xab8>\n-\tldrd\tfp, sl, [sp, #96]\t@ 0x60\n+\tbne.n\t18aa <__gridxc_mesh3d_MOD_reducedata.isra.0+0xabe>\n \tldr\tr3, [sp, #104]\t@ 0x68\n \tldr\tr2, [sp, #28]\n \tcmp\tr2, #0\n-\tbeq.w\t229a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n-\tcmp.w\tfp, #0\n-\tblt.n\t1c5c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc04>\n-\tcmp.w\tsl, #0\n-\tble.n\t1c5c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc04>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tbeq.w\t20ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12c2>\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tcmp\tr2, #0\n+\tblt.n\t19f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc08>\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tcmp\tr2, #0\n+\tble.n\t19f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc08>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tcmp\tr3, #1\n-\tbne.w\t226a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1212>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tmov.w\tr6, sl, lsl #3\n-\tldr\tr2, [sp, #28]\n+\tbne.w\t207a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128e>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n \tmovs\tr4, #0\n+\tldr\tr2, [sp, #28]\n+\tlsls\tr6, r3, #3\n+\tldr\tr3, [sp, #88]\t@ 0x58\n \tadds\tr3, #1\n \tadd.w\tr3, r2, r3, lsl #3\n-\tldr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tlsls\tr5, r2, #3\n-\tmov\tr0, r3\n \tmov\tr2, r6\n+\tmov\tr0, r3\n \tmovs\tr1, #0\n \tadds\tr4, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n+\tldr\tr2, [sp, #56]\t@ 0x38\n \tmov\tr3, r0\n \tadd\tr3, r5\n-\tcmp\tfp, r4\n-\tbge.n\t1c32 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbda>\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tcmp\tr2, r4\n+\tbge.n\t19c8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbdc>\n+\tldr\tr3, [sp, #32]\n \tcmp\tr3, #0\n-\tble.w\t21d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x117c>\n+\tble.w\t1fec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1200>\n \tadd.w\tr3, sp, #9664\t@ 0x25c0\n \tadd.w\tr2, sp, #6720\t@ 0x1a40\n \tadds\tr3, #60\t@ 0x3c\n \tadds\tr2, #4\n \tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #68]\t@ 0x44\n \tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #88]\t@ 0x58\n \tldr.w\tr8, [sp, #12]\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #32]\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n \tldr\tr1, [r2, #16]\n-\tstr\tr1, [sp, #84]\t@ 0x54\n+\tstr\tr1, [sp, #88]\t@ 0x58\n \tadds\tr3, #1\n \tldr\tr1, [r2, #8]\n \tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tldr.w\tr2, [pc, #1620]\t@ 22d0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1278>\n-\tstr\tr1, [sp, #92]\t@ 0x5c\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr2, [pc, #1076]\t@ 1e48 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x105c>\n+\tstr\tr1, [sp, #80]\t@ 0x50\n \tadd\tr2, pc\n-\tstr\tr2, [sp, #144]\t@ 0x90\n+\tstr\tr2, [sp, #132]\t@ 0x84\n \tmovs\tr2, #24\n \tmul.w\tr2, r2, r3\n \tbic.w\tr3, r3, r3, asr #31\n \tstr\tr3, [sp, #120]\t@ 0x78\n \tldr\tr3, [sp, #16]\n-\tstr\tr2, [sp, #148]\t@ 0x94\n+\tstr\tr2, [sp, #136]\t@ 0x88\n \tmov.w\tsl, r3, lsl #3\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tlsls\tr6, r3, #3\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tldr\tr3, [sp, #8]\n \tstr\tr6, [sp, #12]\n \tadds\tr3, #8\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tldr\tr2, [sp, #96]\t@ 0x60\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n-\tldr\tr4, [r2, #8]\n-\tstr\tr4, [sp, #68]\t@ 0x44\n-\tmov\tr5, r4\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n+\tldr\tr0, [sp, #100]\t@ 0x64\n+\tldr\tr1, [sp, #64]\t@ 0x40\n \tldr\tr6, [r2, #16]\n-\tadd\tr5, r4\n+\tldr\tr4, [r2, #8]\n+\tstr\tr6, [sp, #44]\t@ 0x2c\n+\tldr\tr6, [sp, #80]\t@ 0x50\n+\tstr\tr4, [sp, #60]\t@ 0x3c\n+\tadds\tr5, r4, r6\n+\tldr\tr4, [r2, #12]\n \tldr.w\tfp, [r2, #4]\n-\tldr\tr4, [sp, #84]\t@ 0x54\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tstr\tr4, [sp, #56]\t@ 0x38\n+\tldr\tr4, [sp, #88]\t@ 0x58\n \tldr\tr3, [r2, #0]\n \tadds\tr4, r6, r4\n-\tstr\tr6, [sp, #48]\t@ 0x30\n-\tstr\tr4, [r1, #16]\n-\tadds\tr7, r3, r0\n-\tldr\tr6, [r2, #12]\n-\tstr\tr4, [sp, #88]\t@ 0x58\n-\tadd.w\tr4, fp, r0\n-\tstr\tr4, [r1, #4]\n-\tstr\tr4, [sp, #4]\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n-\tstr\tr5, [r1, #8]\n-\tcmp\tr5, r4\n+\tadd.w\tr6, fp, r1\n+\tstr\tr6, [sp, #4]\n+\tadds\tr7, r3, r1\n+\tstr\tr6, [r0, #4]\n+\tldr\tr6, [sp, #80]\t@ 0x50\n+\tstr\tr5, [sp, #48]\t@ 0x30\n+\tcmp\tr7, r1\n \tit\tge\n-\tcmpge\tr7, r0\n-\tstr\tr7, [r1, #0]\n-\tstr\tr5, [sp, #44]\t@ 0x2c\n-\tadd.w\tr5, r6, r4\n-\tstr\tr5, [r1, #12]\n+\tcmpge\tr5, r6\n+\tstr\tr5, [r0, #8]\n+\tldr\tr5, [sp, #56]\t@ 0x38\n \tit\tlt\n-\tmovlt\tr0, #1\n-\tldrd\tr1, r4, [sp, #84]\t@ 0x54\n-\tit\tge\n-\tmovge\tr0, #0\n+\tmovlt\tr1, #1\n \tldr\tr2, [r2, #20]\n-\tcmp\tr4, r1\n-\tstr\tr2, [sp, #20]\n \tit\tge\n \tmovge\tr1, #0\n+\tadd\tr5, r6\n+\tstr\tr4, [sp, #76]\t@ 0x4c\n+\tmov\tr6, r4\n+\tstr\tr4, [r0, #16]\n+\tldr\tr4, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #20]\n+\tldr\tr2, [sp, #36]\t@ 0x24\n+\tcmp\tr6, r4\n \tit\tlt\n-\tmovlt\tr1, #1\n-\tldr\tr2, [sp, #32]\n-\torrs\tr1, r0\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tstr\tr6, [sp, #56]\t@ 0x38\n+\torrlt.w\tr1, r1, #1\n \tldr\tr6, [sp, #20]\n-\tldr\tr2, [r2, #4]\n+\tstr\tr7, [r0, #0]\n \tadd.w\tr9, r6, r4\n+\tldr\tr2, [r2, #4]\n+\tldr\tr6, [sp, #4]\n+\tstr\tr5, [r0, #12]\n+\tcmp\tr2, r6\n \tstr.w\tr9, [r0, #20]\n-\tldr\tr4, [sp, #4]\n-\tcmp\tr2, r4\n-\tblt.w\t203e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfe6>\n-\tldr\tr4, [sp, #32]\n-\tldr\tr0, [r4, #12]\n+\tblt.w\t1e50 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1064>\n+\tldr\tr6, [sp, #36]\t@ 0x24\n+\tldr\tr0, [r6, #12]\n \tcmp\tr0, r5\n-\tblt.w\t203e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfe6>\n-\tldr\tr0, [r4, #20]\n+\tblt.w\t1e50 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1064>\n+\tldr\tr0, [r6, #20]\n \tcmp\tr0, r9\n-\tit\tge\n-\tmovge\tr0, #0\n \tit\tlt\n-\tmovlt\tr0, #1\n-\torrs\tr1, r0\n-\tbne.w\t203e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfe6>\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n+\torrlt.w\tr1, r1, #1\n+\tcmp\tr1, #0\n+\tbne.w\t1e50 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1064>\n+\tldr\tr1, [sp, #64]\t@ 0x40\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [sp, #132]\t@ 0x84\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n \tcmp\tr1, r2\n-\tbne.w\t2064 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x100c>\n-\tldr\tr0, [sp, #32]\n+\tbne.w\t1e76 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x108a>\n+\tldr\tr0, [sp, #36]\t@ 0x24\n \tldrd\tr1, r2, [r0, #8]\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [sp, #136]\t@ 0x88\n+\tldr\tr1, [sp, #144]\t@ 0x90\n \tcmp\tr1, r2\n-\tbne.w\t2064 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x100c>\n+\tbne.w\t1e76 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x108a>\n \tldrd\tr1, r2, [r0, #16]\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [sp, #140]\t@ 0x8c\n+\tldr\tr1, [sp, #148]\t@ 0x94\n \tcmp\tr1, r2\n-\tbne.w\t2064 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x100c>\n-\tldr\tr0, [sp, #68]\t@ 0x44\n+\tbne.w\t1e76 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x108a>\n+\tldrd\tr1, r0, [sp, #56]\t@ 0x38\n \tsub.w\tr2, fp, r3\n-\tldr\tr1, [sp, #56]\t@ 0x38\n \tadds\tr2, #1\n \tsubs\tr1, r1, r0\n-\tldr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tadds\tr1, #1\n \tcmp\tr2, r1\n \tit\tlt\n \tmovlt\tr2, r1\n \tldr\tr1, [sp, #20]\n \tsubs\tr1, r1, r0\n \tadds\tr1, #1\n \tcmp\tr2, r1\n \tit\tlt\n \tmovlt\tr2, r1\n \tldr\tr1, [sp, #120]\t@ 0x78\n \tcmp\tr2, r1\n-\tble.n\t1da8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd50>\n-\tldr.w\tr2, [pc, #1336]\t@ 22cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1274>\n+\tble.n\t1b32 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd46>\n+\tldr\tr2, [pc, #804]\t@ (1e44 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1058>)\n \tmovs\tr1, #56\t@ 0x38\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tldr\tr3, [sp, #24]\n-\tldr.w\tr0, [pc, #1336]\t@ 22d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x127c>\n+\tldr\tr0, [pc, #804]\t@ (1e4c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1060>)\n \tldr\tr2, [r3, r2]\n \tadd\tr0, pc\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr2, [sp, #32]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #36]\t@ 0x24\n \tldr\tr0, [sp, #4]\n \tldr\tr1, [r2, #0]\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n+\tstr\tr1, [sp, #64]\t@ 0x40\n \tsubs\tr4, r0, r1\n \tsubs\tr7, r7, r1\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tldr\tr1, [r2, #8]\n-\tstr\tr1, [sp, #92]\t@ 0x5c\n+\tstr\tr1, [sp, #80]\t@ 0x50\n \tldr\tr2, [r2, #16]\n \tsubs\tr0, r0, r1\n \tsubs\tr5, r5, r1\n-\tldr\tr1, [sp, #88]\t@ 0x58\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n \tsub.w\tr9, r9, r2\n-\tstr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #88]\t@ 0x58\n \tsubs\tr1, r1, r2\n-\tldr\tr2, [sp, #160]\t@ 0xa0\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr2, [sp, #168]\t@ 0xa8\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tcmp\tr2, #0\n \tstr\tr1, [sp, #4]\n-\tblt.n\t1de2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd8a>\n-\tldr\tr2, [sp, #148]\t@ 0x94\n+\tblt.n\t1b6c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd80>\n+\tldr\tr2, [sp, #136]\t@ 0x88\n \tmovs\tr1, #0\n \tldr\tr0, [sp, #8]\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tfp, r3\n-\tblt.n\t1e72 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe1a>\n+\tblt.n\t1bfc <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe10>\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tmov\tr0, r4\n \tldr\tr1, [sp, #4]\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tstr\tr7, [sp, #104]\t@ 0x68\n-\tmul.w\tr2, r7, r2\n+\tstr\tr7, [sp, #92]\t@ 0x5c\n \tstr\tr3, [sp, #112]\t@ 0x70\n-\tmla\tr1, r8, r1, r2\n-\tldr\tr2, [sp, #52]\t@ 0x34\n-\tldr.w\tip, [sp, #68]\t@ 0x44\n+\tmul.w\tr2, r7, r2\n+\tldr.w\tip, [sp, #60]\t@ 0x3c\n+\tmla\tr1, r1, r8, r2\n \tldr\tr3, [sp, #12]\n-\tstr.w\tfp, [sp, #108]\t@ 0x6c\n+\tldrd\tr6, r2, [sp, #48]\t@ 0x30\n+\tstr.w\tfp, [sp, #104]\t@ 0x68\n \tmov\tfp, r6\n \tmla\tlr, sl, r6, r2\n \tldr\tr2, [sp, #8]\n-\tstr\tr2, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n \tmov\tr2, r7\n \tldr\tr7, [sp, #56]\t@ 0x38\n \tldr\tr4, [sp, #20]\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr6, [sp, #48]\t@ 0x30\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tvldr\td7, [pc, #660]\t@ 1e38 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x104c>\n \tcmp\tr4, r6\n-\tblt.n\t1e4e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdf6>\n+\tblt.n\t1bd8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdec>\n \tldr\tr4, [sp, #4]\n \tmov\tr6, r1\n \tstr\tr0, [sp, #12]\n \tstr\tr2, [sp, #116]\t@ 0x74\n \tcmp\tr7, ip\n-\tblt.n\t1e42 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdea>\n+\tblt.n\t1bcc <__gridxc_mesh3d_MOD_reducedata.isra.0+0xde0>\n \tadd.w\tr0, lr, r6, lsl #3\n \tmov\tr2, fp\n-\tvldr\td17, [r0]\n+\tvldr\td6, [r0]\n \tadds\tr2, #1\n \tadd\tr0, sl\n \tcmp\tr5, r2\n-\tvadd.f64\td16, d16, d17\n-\tbge.n\t1e32 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdda>\n+\tvadd.f64\td7, d7, d6\n+\tbge.n\t1bbc <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdd0>\n \tadds\tr4, #1\n \tadd\tr6, r8\n \tcmp\tr9, r4\n-\tbge.n\t1e28 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdd0>\n+\tbge.n\t1bb2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdc6>\n \tldr\tr0, [sp, #12]\n \tldr\tr2, [sp, #116]\t@ 0x74\n-\tldr\tr4, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #76]\t@ 0x4c\n \tadds\tr2, #1\n \tcmp\tr0, r2\n \tmov\tr6, r4\n \tadd.w\tr4, r4, #24\n-\tstr\tr4, [sp, #88]\t@ 0x58\n+\tstr\tr4, [sp, #76]\t@ 0x4c\n \tldr\tr4, [sp, #40]\t@ 0x28\n-\tvstr\td16, [r6]\n+\tvstr\td7, [r6]\n \tadd\tr1, r4\n-\tbge.n\t1e14 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdbc>\n+\tbge.n\t1b9e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xdb2>\n \tstr\tr3, [sp, #12]\n \tmov\tr4, r0\n-\tldr\tr7, [sp, #104]\t@ 0x68\n-\tldr.w\tfp, [sp, #108]\t@ 0x6c\n+\tldr\tr7, [sp, #92]\t@ 0x5c\n+\tldr.w\tfp, [sp, #104]\t@ 0x68\n \tldr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #68]\t@ 0x44\n+\tldrd\tr2, r1, [sp, #56]\t@ 0x38\n \tcmp\tr2, r1\n-\tblt.w\t219c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1144>\n+\tblt.w\t1faa <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11be>\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tcmp\tr2, #1\n-\tbne.w\t207a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1022>\n-\tldr\tr2, [sp, #16]\n+\tbne.w\t1e8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10a0>\n+\tldr\tr2, [sp, #4]\n \tmov.w\tip, r7, lsl #3\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tldr\tr6, [sp, #8]\n-\tstr\tr6, [sp, #104]\t@ 0x68\n-\tstrd\tr0, r3, [sp, #108]\t@ 0x6c\n-\tmul.w\tr1, r0, r2\n-\tldr\tr2, [sp, #4]\n-\tstr.w\tsl, [sp, #116]\t@ 0x74\n-\tmul.w\tr2, r8, r2\n+\tstr\tr6, [sp, #76]\t@ 0x4c\n+\tmul.w\tr1, r2, r8\n+\tldr\tr2, [sp, #16]\n+\tstr\tr0, [sp, #104]\t@ 0x68\n+\tstr.w\tsl, [sp, #112]\t@ 0x70\n+\tmul.w\tr2, r0, r2\n+\tmov\tr0, r1\n \tadds\tr6, r1, r2\n-\tstr\tr6, [sp, #88]\t@ 0x58\n+\tstr\tr6, [sp, #92]\t@ 0x5c\n \tldr\tr6, [sp, #52]\t@ 0x34\n \tadd.w\tlr, r6, ip\n-\tmov\tr6, ip\n-\tldr\tr0, [sp, #20]\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tcmp\tr0, r3\n-\tblt.n\t1eec <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe94>\n-\tldr.w\tsl, [sp, #88]\t@ 0x58\n-\tldr.w\tip, [sp, #4]\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tstr\tr5, [sp, #152]\t@ 0x98\n+\tldr\tr1, [sp, #20]\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tvldr\td7, [pc, #508]\t@ 1e38 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x104c>\n+\tcmp\tr1, r6\n+\tblt.n\t1c6c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe80>\n+\tldr.w\tsl, [sp, #92]\t@ 0x5c\n+\tldr\tr6, [sp, #4]\n+\tstr\tr5, [sp, #116]\t@ 0x74\n \tcmp\tfp, r3\n-\tblt.n\t1ede <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe86>\n+\tblt.n\t1c62 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe76>\n \tadd.w\tr5, lr, sl, lsl #3\n-\tmov\tr0, r7\n-\tvldmia\tr5!, {d17}\n-\tadds\tr0, #1\n-\tcmp\tr4, r0\n-\tvadd.f64\td16, d16, d17\n-\tbge.n\t1ed0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe78>\n-\tadd.w\tip, ip, #1\n+\tmov\tr1, r7\n+\tvldmia\tr5!, {d6}\n+\tadds\tr1, #1\n+\tcmp\tr4, r1\n+\tvadd.f64\td7, d7, d6\n+\tbge.n\t1c54 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe68>\n+\tadds\tr6, #1\n \tadd\tsl, r8\n-\tcmp\tr9, ip\n-\tbge.n\t1ec6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe6e>\n-\tldr\tr5, [sp, #152]\t@ 0x98\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tldr\tr3, [sp, #16]\n-\tadds\tr0, #1\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n-\tldr\tr0, [sp, #104]\t@ 0x68\n-\tvstr\td16, [r0, #8]\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd\tr0, r3\n-\tstr\tr0, [sp, #88]\t@ 0x58\n-\tldr\tr0, [sp, #104]\t@ 0x68\n-\tadd.w\tr3, r0, #24\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tcmp\tr5, r0\n-\tbge.n\t1eae <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe56>\n+\tcmp\tr9, r6\n+\tbge.n\t1c4a <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe5e>\n+\tldr\tr5, [sp, #116]\t@ 0x74\n+\tldr\tr6, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tadds\tr1, #1\n+\tstr\tr1, [sp, #104]\t@ 0x68\n+\tvstr\td7, [r6, #8]\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n+\tldr\tr6, [sp, #16]\n+\tadd\tr1, r6\n+\tldr\tr6, [sp, #76]\t@ 0x4c\n+\tstr\tr1, [sp, #92]\t@ 0x5c\n+\tadd.w\tr1, r6, #24\n+\tstr\tr1, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #104]\t@ 0x68\n+\tcmp\tr5, r1\n+\tbge.n\t1c36 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xe4a>\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tmov\tr1, r0\n \tldr\tr0, [sp, #20]\n-\tmov\tip, r6\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tldrd\tr3, sl, [sp, #112]\t@ 0x70\n+\tldr.w\tsl, [sp, #112]\t@ 0x70\n \tcmp\tr0, r6\n-\tblt.n\t1f8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf34>\n+\tblt.n\t1d10 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf24>\n \tadd\tr1, r2\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tmov\tr0, sl\n \tldr.w\tsl, [sp, #16]\n \tadd.w\tlr, r2, ip\n \tldr\tr2, [sp, #8]\n \tmov\tr6, r8\n \tstr\tr4, [sp, #20]\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr4, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldrd\tr3, r4, [sp, #56]\t@ 0x38\n+\tvldr\td7, [pc, #384]\t@ 1e38 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x104c>\n \tcmp\tr3, r4\n-\tblt.n\t1f76 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf1e>\n-\tldr.w\tip, [sp, #44]\t@ 0x2c\n+\tblt.n\t1cfa <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf0e>\n+\tldr.w\tip, [sp, #48]\t@ 0x30\n \tmov\tr8, r1\n \tldr\tr4, [sp, #20]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tstr\tr2, [sp, #104]\t@ 0x68\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr6, [sp, #76]\t@ 0x4c\n+\tstr.w\tr9, [sp, #92]\t@ 0x5c\n \tcmp\tfp, r3\n-\tblt.n\t1f64 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf0c>\n-\tadd.w\tr6, lr, r8, lsl #3\n-\tmov\tr2, r7\n-\tvldmia\tr6!, {d17}\n-\tadds\tr2, #1\n-\tcmp\tr4, r2\n-\tvadd.f64\td16, d16, d17\n-\tbge.n\t1f56 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xefe>\n+\tblt.n\t1ce6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xefa>\n+\tadd.w\tr9, lr, r8, lsl #3\n+\tmov\tr6, r7\n+\tvldmia\tr9!, {d6}\n+\tadds\tr6, #1\n+\tcmp\tr4, r6\n+\tvadd.f64\td7, d7, d6\n+\tbge.n\t1cd8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xeec>\n \tadd.w\tip, ip, #1\n \tadd\tr8, sl\n \tcmp\tr5, ip\n-\tbge.n\t1f4c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xef4>\n-\tldr\tr6, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #104]\t@ 0x68\n+\tbge.n\t1cce <__gridxc_mesh3d_MOD_reducedata.isra.0+0xee2>\n+\tldr\tr6, [sp, #76]\t@ 0x4c\n+\tldr.w\tr9, [sp, #92]\t@ 0x5c\n \tstr\tr4, [sp, #20]\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #4]\n \tadd\tr1, r6\n-\tvstr\td16, [r2, #16]\n+\tvstr\td7, [r2, #16]\n \tadds\tr2, #24\n \tadds\tr3, #1\n \tstr\tr3, [sp, #4]\n \tcmp\tr9, r3\n-\tbge.n\t1f32 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xeda>\n+\tbge.n\t1cb2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xec6>\n \tmov\tr8, r6\n \tmov\tsl, r0\n \tldr\tr3, [sp, #72]\t@ 0x48\n \tmovs\tr1, #24\n-\tldr\tr2, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #108]\t@ 0x6c\n \tmovs\tr4, #0\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tldrd\tr7, r9, [sp, #124]\t@ 0x7c\n+\tldr\tr5, [sp, #100]\t@ 0x64\n+\tldrd\tr9, r7, [sp, #124]\t@ 0x7c\n \tmla\tfp, r1, r2, r3\n-\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #84]\t@ 0x54\n \tldr\tr6, [sp, #12]\n \tlsls\tr0, r3, #3\n \tldrd\tr1, r2, [r5]\n \tldr.w\tr3, [fp, r4, lsl #3]\n \tsubs.w\tlr, r2, r1\n-\tbmi.n\t1fe0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf88>\n-\tldr\tr2, [sp, #80]\t@ 0x50\n+\tbmi.n\t1d64 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf78>\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tmov\tip, r7\n \tmovs\tr1, #0\n \tmla\tr3, r3, r2, r9\n \tldr\tr2, [sp, #28]\n \tadd.w\tr3, r2, r3, lsl #3\n-\tvldr\td16, [r3]\n-\tcmp\tlr, r1\n-\tvldr\td17, [ip, #-8]\n+\tvldr\td7, [r3]\n+\tcmp\tr1, lr\n+\tvldr\td6, [ip, #-8]\n \tadd.w\tr1, r1, #1\n \tadd.w\tip, ip, #24\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r0\n-\tbne.n\t1fc2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf6a>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tbne.n\t1d46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf5a>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tadds\tr4, #1\n \tadds\tr5, #8\n \tadds\tr7, #8\n \tadd\tr9, r3\n \tcmp\tr4, #3\n-\tbne.n\t1fa4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf4c>\n+\tbne.n\t1d28 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf3c>\n \tldr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr1, [sp, #36]\t@ 0x24\n+\tldr\tr1, [sp, #32]\n \tadds\tr3, #24\n \tstr\tr3, [sp, #96]\t@ 0x60\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n \tstr\tr6, [sp, #12]\n \tadds\tr2, r3, #2\n \tadds\tr3, #1\n-\tcmp\tr2, r1\n-\tbgt.w\t21d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x117c>\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tb.n\t1ca8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc50>\n-\tadd.w\tfp, r3, #8\n-\tmovs\tr6, #6\n-\tb.w\t16b4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x65c>\n+\tcmp\tr1, r2\n+\tblt.w\t1fec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1200>\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tb.n\t1a40 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc54>\n+\tadd.w\tr4, r3, #8\n+\tmov.w\tsl, #6\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tcmp\tr3, #125\t@ 0x7d\n+\tble.n\t1db6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfca>\n+\tldr\tr3, [pc, #164]\t@ (1e44 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1058>)\n+\tmovs\tr1, #46\t@ 0x2e\n+\tstr\tr2, [sp, #116]\t@ 0x74\n+\tldr\tr2, [sp, #24]\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldr\tr3, [r2, r3]\n+\tldr\tr3, [r3, #0]\n+\tblx\tr3\n+\tldr\tr2, [sp, #116]\t@ 0x74\n+\tldr.w\tr3, [r8]\n+\tstr\tr3, [sp, #4]\n+\tsub.w\tfp, fp, #6\n+\tldr\tr3, [sp, #32]\n+\tsub.w\tlr, r5, #24\n+\tsub.w\tip, r5, #20\n+\tadd.w\tr1, r3, sl\n+\tadds\tr3, #6\n+\tstr\tr3, [sp, #32]\n+\tadd.w\tr0, sp, #18688\t@ 0x4900\n+\tldr.w\tr3, [r9, fp, lsl #2]\n+\tadds\tr0, #40\t@ 0x28\n+\tstr\tr3, [r2, #24]\n+\tadd.w\tr1, r0, r1, lsl #2\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tsub.w\tr0, r5, #16\n+\tsub.w\tr1, r1, #14976\t@ 0x3a80\n+\tadds\tr2, #24\n+\tldr.w\tr3, [r3, fp, lsl #2]\n+\tstr\tr3, [r2, #4]\n+\tldr.w\tr3, [lr, fp, lsl #2]\n+\tstr\tr3, [r2, #8]\n+\tldr.w\tr3, [ip, fp, lsl #2]\n+\tstr\tr3, [r2, #12]\n+\tldr.w\tr3, [r0, fp, lsl #2]\n+\tstr\tr3, [r2, #16]\n+\tsub.w\tr3, r5, #12\n+\tldr.w\tr3, [r3, fp, lsl #2]\n+\tstr\tr3, [r2, #20]\n+\tstr.w\tr6, [r1, #-64]\n+\tsubs\tr6, #1\n+\tstr\tr6, [r4, #0]\n+\tb.w\t1360 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x574>\n+\tmov.w\tsl, #4\n+\tb.n\t1d94 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xfa8>\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tstr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr2, [sp, #88]\t@ 0x58\n \tmovs\tr2, #1\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tb.w\t1130 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd8>\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tb.w\tec6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xda>\n \tmov\tr4, r5\n-\tb.w\t1118 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc0>\n-\tadds\tr4, #8\n-\tadds\tr5, #12\n-\tcmp\tr4, r9\n-\tbne.w\t122a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1d2>\n-\tb.w\t126e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x216>\n-\tadd.w\tr8, r3, #8\n-\tmovs\tr6, #6\n-\tb.w\t1452 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x3fa>\n-\tldr\tr2, [pc, #652]\t@ (22cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1274>)\n+\tb.w\teae <__gridxc_mesh3d_MOD_reducedata.isra.0+0xc2>\n+\tmov.w\tsl, #4\n+\tb.w\t142e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x642>\n+\t...\n+\t.word\t0x00000864\n+ R_ARM_REL32\t.LC13\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x0000042c\n+ R_ARM_REL32\t.LC14\n+\t.word\t0x0000031e\n+ R_ARM_REL32\t.LC16\n+\tldr\tr2, [pc, #660]\t@ (20e8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12fc>)\n \tmovs\tr1, #46\t@ 0x2e\n-\tstr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #80]\t@ 0x50\n \tldr\tr3, [sp, #24]\n-\tldr\tr0, [sp, #144]\t@ 0x90\n+\tldr\tr0, [sp, #132]\t@ 0x84\n \tldr\tr2, [r3, r2]\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n-\tldr\tr3, [sp, #32]\n+\tldr\tr3, [sp, #36]\t@ 0x24\n \tldrd\tr3, r2, [r3]\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tsubs\tr2, r2, r1\n-\tldr\tr1, [sp, #132]\t@ 0x84\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n \tcmp\tr1, r2\n-\tbeq.w\t1d4a <__gridxc_mesh3d_MOD_reducedata.isra.0+0xcf2>\n-\tldr\tr2, [pc, #612]\t@ (22cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1274>)\n+\tbeq.w\t1ad8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xcec>\n+\tldr\tr2, [pc, #624]\t@ (20e8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12fc>)\n \tmovs\tr1, #72\t@ 0x48\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #64]\t@ 0x40\n \tldr\tr3, [sp, #24]\n-\tldr\tr0, [pc, #616]\t@ (22d8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1280>)\n+\tldr\tr0, [pc, #620]\t@ (20ec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1300>)\n \tldr\tr2, [r3, r2]\n \tadd\tr0, pc\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tb.n\t1d68 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd10>\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tldr\tr2, [sp, #4]\n-\tldr\tr1, [sp, #16]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tb.n\t1af6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xd0a>\n+\tldr\tr6, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #16]\n+\tldr\tr1, [sp, #4]\n \tldr\tr0, [sp, #12]\n \tldr.w\tip, [sp, #8]\n-\tmul.w\tr2, r8, r2\n-\tstr\tr6, [sp, #88]\t@ 0x58\n-\tmul.w\tr1, r6, r1\n+\tmul.w\tr2, r6, r2\n+\tstr\tr6, [sp, #76]\t@ 0x4c\n+\tmul.w\tr1, r8, r1\n \tldr\tr6, [sp, #12]\n \tmul.w\tlr, r7, r0\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tstr\tr3, [sp, #104]\t@ 0x68\n \tadds\tr0, r2, r1\n-\tstr\tr0, [sp, #104]\t@ 0x68\n+\tstr\tr0, [sp, #92]\t@ 0x5c\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tstr.w\tsl, [sp, #152]\t@ 0x98\n \tadd\tr0, lr\n \tstr\tr0, [sp, #116]\t@ 0x74\n \tmov\tr0, ip\n-\tmov\tip, r1\n-\tmov\tr1, lr\n+\tmov\tip, lr\n \tstr\tr2, [sp, #112]\t@ 0x70\n \tldr\tr3, [sp, #20]\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr2, [sp, #48]\t@ 0x30\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tvldr\td7, [pc, #540]\t@ 20e0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12f4>\n \tcmp\tr3, r2\n-\tblt.n\t20f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10a0>\n-\tldr.w\tsl, [sp, #104]\t@ 0x68\n+\tblt.n\t1f08 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x111c>\n+\tldr.w\tsl, [sp, #92]\t@ 0x5c\n \tldr.w\tlr, [sp, #4]\n-\tldrd\tr3, r2, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #112]\t@ 0x70\n \tstr\tr5, [sp, #12]\n \tstr\tr0, [sp, #156]\t@ 0x9c\n \tcmp\tfp, r3\n-\tblt.n\t20e6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x108e>\n+\tblt.n\t1ef6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x110a>\n \tldr\tr0, [sp, #116]\t@ 0x74\n \tadd.w\tr5, r0, sl, lsl #3\n \tmov\tr0, r7\n-\tvldr\td17, [r5]\n+\tvldr\td6, [r5]\n \tadds\tr0, #1\n \tadd\tr5, r6\n \tcmp\tr4, r0\n-\tvadd.f64\td16, d16, d17\n-\tbge.n\t20d6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x107e>\n+\tvadd.f64\td7, d7, d6\n+\tbge.n\t1ee6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10fa>\n \tadd.w\tlr, lr, #1\n \tadd\tsl, r8\n \tcmp\tr9, lr\n-\tbge.n\t20ca <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1072>\n+\tbge.n\t1eda <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10ee>\n \tldr\tr5, [sp, #12]\n \tldr\tr0, [sp, #156]\t@ 0x9c\n-\tstrd\tr3, r2, [sp, #108]\t@ 0x6c\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tadds\tr0, #24\n \tldr\tr2, [sp, #16]\n \tadds\tr3, #1\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tvstr\td16, [r0, #-16]\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tvstr\td7, [r0, #-16]\n \tadd\tr3, r2\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr5, r3\n-\tbge.n\t20ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1056>\n+\tbge.n\t1ebe <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10d2>\n \tldr\tr0, [sp, #20]\n-\tmov\tlr, r1\n+\tmov\tlr, ip\n \tstr\tr6, [sp, #12]\n-\tmov\tr1, ip\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tldr\tr6, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #104]\t@ 0x68\n \tldr.w\tsl, [sp, #152]\t@ 0x98\n \tcmp\tr0, r6\n \tldr\tr2, [sp, #112]\t@ 0x70\n-\tblt.w\t1f8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf34>\n+\tblt.w\t1d10 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf24>\n \tadd\tr1, r2\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tldr\tr6, [sp, #12]\n \tmov\tr0, sl\n \tadd\tr2, lr\n \tldr.w\tlr, [sp, #8]\n \tstr\tr2, [sp, #20]\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldrd\tr2, r3, [sp, #56]\t@ 0x38\n+\tvldr\td7, [pc, #400]\t@ 20e0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12f4>\n \tcmp\tr2, r3\n-\tblt.n\t2182 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x112a>\n-\tldr.w\tip, [sp, #44]\t@ 0x2c\n+\tblt.n\t1f90 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11a4>\n+\tldr.w\tip, [sp, #48]\t@ 0x30\n \tmov\tsl, r1\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n \tstr.w\tr8, [sp, #12]\n \tcmp\tfp, r3\n-\tblt.n\t2170 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1118>\n+\tblt.n\t1f7e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1192>\n \tldr\tr2, [sp, #20]\n \tadd.w\tr8, r2, sl, lsl #3\n \tmov\tr2, r7\n-\tvldr\td17, [r8]\n+\tvldr\td6, [r8]\n \tadds\tr2, #1\n \tadd\tr8, r6\n \tcmp\tr4, r2\n-\tvadd.f64\td16, d16, d17\n-\tbge.n\t2160 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1108>\n+\tvadd.f64\td7, d7, d6\n+\tbge.n\t1f6e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1182>\n \tldr\tr2, [sp, #16]\n \tadd.w\tip, ip, #1\n \tcmp\tr5, ip\n \tadd\tsl, r2\n-\tbge.n\t2154 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10fc>\n+\tbge.n\t1f62 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1176>\n \tldr.w\tr8, [sp, #12]\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr2, [sp, #4]\n \tadd\tr1, r8\n-\tvstr\td16, [lr, #16]\n+\tvstr\td7, [lr, #16]\n \tadd.w\tlr, lr, #24\n \tadds\tr2, #1\n \tstr\tr2, [sp, #4]\n \tcmp\tr9, r2\n-\tbge.n\t213c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10e4>\n+\tbge.n\t1f4a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x115e>\n \tmov\tsl, r0\n \tstr\tr6, [sp, #12]\n-\tb.n\t1f8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf34>\n+\tb.n\t1d10 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf24>\n \tldr\tr2, [sp, #20]\n-\tldr\tr1, [sp, #48]\t@ 0x30\n+\tldr\tr1, [sp, #44]\t@ 0x2c\n \tcmp\tr2, r1\n-\tblt.w\t1f8c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf34>\n+\tblt.w\t1d10 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xf24>\n \tldr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #16]\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tcmp\tr2, #1\n \tldr\tr2, [sp, #4]\n-\tmul.w\tr1, r0, r1\n-\tmul.w\tr2, r8, r2\n-\tbne.n\t2262 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x120a>\n-\tmov.w\tip, r7, lsl #3\n-\tb.n\t1f1c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xec4>\n+\tit\teq\n+\tmoveq.w\tip, r7, lsl #3\n+\tmul.w\tr1, r2, r8\n+\tldr\tr2, [sp, #16]\n+\tmul.w\tr2, r0, r2\n+\tbeq.w\t1c9c <__gridxc_mesh3d_MOD_reducedata.isra.0+0xeb0>\n+\tldr\tr0, [sp, #12]\n+\tmul.w\tlr, r7, r0\n+\tb.n\t1f38 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x114c>\n \tldr\tr3, [sp, #28]\n \tcmp\tr3, #0\n-\tbeq.n\t229a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n-\tcmp.w\tfp, #0\n-\tblt.n\t21d4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x117c>\n-\tcmp.w\tsl, #0\n-\tbgt.w\t1c16 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbbe>\n-\tldr\tr3, [pc, #260]\t@ (22dc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1284>)\n+\tbeq.n\t20ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12c2>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr3, #0\n+\tblt.n\t1fec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1200>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp\tr3, #0\n+\tbgt.w\t19ac <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbc0>\n+\tldr\tr3, [pc, #256]\t@ (20f0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1304>)\n \tldr\tr2, [sp, #24]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #1\n-\tbeq.n\t223e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11e6>\n+\tbeq.n\t2056 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x126a>\n \tldr\tr3, [sp, #8]\n \tcmp\tr3, #0\n-\tbeq.w\t24a0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1448>\n-\tldr\tr2, [pc, #244]\t@ (22e0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1288>)\n+\tbeq.w\t22aa <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14be>\n+\tldr\tr2, [pc, #240]\t@ (20f4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1308>)\n \tadd.w\tr1, sp, #18688\t@ 0x4900\n-\tldr\tr3, [pc, #244]\t@ (22e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128c>)\n+\tldr\tr3, [pc, #240]\t@ (20f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x130c>)\n \tadds\tr1, #36\t@ 0x24\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t225e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1206>\n+\tbne.n\t2076 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128a>\n \tldr\tr0, [sp, #8]\n \tadd.w\tsp, sp, #18688\t@ 0x4900\n \tadd\tsp, #44\t@ 0x2c\n \tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n-\tldr\tr2, [pc, #208]\t@ (22e8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1290>)\n+\tldr\tr2, [pc, #204]\t@ (20fc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1310>)\n \tadd.w\tr1, sp, #18688\t@ 0x4900\n-\tldr\tr3, [pc, #196]\t@ (22e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128c>)\n+\tldr\tr3, [pc, #192]\t@ (20f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x130c>)\n \tadds\tr1, #36\t@ 0x24\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t225e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1206>\n+\tbne.n\t2076 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128a>\n \tadd.w\tsp, sp, #18688\t@ 0x4900\n \tadd\tsp, #44\t@ 0x2c\n \tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldr\tr3, [sp, #8]\n \tcmp\tr3, #0\n-\tbeq.n\t2216 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11be>\n-\tldr\tr2, [pc, #164]\t@ (22ec <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1294>)\n+\tbeq.n\t202e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n+\tldr\tr2, [pc, #160]\t@ (2100 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1314>)\n \tadd.w\tr1, sp, #18688\t@ 0x4900\n-\tldr\tr3, [pc, #152]\t@ (22e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128c>)\n+\tldr\tr3, [pc, #148]\t@ (20f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x130c>)\n \tadds\tr1, #36\t@ 0x24\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbeq.n\t2202 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11aa>\n+\tbeq.n\t201a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x122e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr0, [sp, #12]\n-\tmul.w\tlr, r7, r0\n-\tb.n\t212a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x10d2>\n \tlsls\tr4, r3, #3\n \tldr\tr3, [sp, #28]\n-\tldr\tr2, [sp, #84]\t@ 0x54\n+\tldr\tr2, [sp, #88]\t@ 0x58\n \tmov.w\tr8, #0\n \tadds\tr5, r3, r4\n \tmov.w\tr9, #0\n \tmovs\tr3, #0\n \tadd.w\tr0, r5, r2, lsl #3\n \tmovs\tr1, #0\n+\tldr\tr6, [sp, #64]\t@ 0x40\n \tadds\tr1, #1\n \tstrd\tr8, r9, [r0]\n-\tcmp\tsl, r1\n \tadd\tr0, r4\n-\tbne.n\t2282 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x122a>\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tcmp\tr6, r1\n+\tbne.n\t2092 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12a6>\n+\tldr\tr1, [sp, #84]\t@ 0x54\n \tadds\tr3, #1\n-\tcmp\tfp, r3\n \tadd\tr2, r1\n-\tbge.n\t227c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1224>\n-\tb.n\t1c46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbee>\n-\tldr\tr3, [pc, #64]\t@ (22dc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1284>)\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tcmp\tr1, r3\n+\tbge.n\t208c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12a0>\n+\tb.n\t19de <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbf2>\n+\tldr\tr3, [pc, #64]\t@ (20f0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1304>)\n \tldr\tr2, [sp, #24]\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tcmp\tr3, #1\n-\tbeq.n\t223e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11e6>\n+\tbeq.n\t2056 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x126a>\n \tldr\tr3, [sp, #8]\n \tcmp\tr3, #0\n-\tbeq.n\t2216 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11be>\n-\tldr\tr2, [pc, #64]\t@ (22f0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1298>)\n+\tbeq.n\t202e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n+\tldr\tr2, [pc, #64]\t@ (2104 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1318>)\n \tadd.w\tr1, sp, #18688\t@ 0x4900\n-\tldr\tr3, [pc, #48]\t@ (22e4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128c>)\n+\tldr\tr3, [pc, #48]\t@ (20f8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x130c>)\n \tadds\tr1, #36\t@ 0x24\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbeq.n\t2202 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x11aa>\n-\tb.n\t225e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1206>\n-\t.word\t0x00000a7e\n- R_ARM_REL32\t.LC13\n-\t.word\t0x00000000\n+\tbeq.n\t201a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x122e>\n+\tb.n\t2076 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x128a>\n+\tnop.w\n+\t...\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000064c\n- R_ARM_REL32\t.LC14\n-\t.word\t0x00000530\n- R_ARM_REL32\t.LC16\n-\t.word\t0x00000264\n+\t.word\t0x00000266\n R_ARM_REL32\t.LC15\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n-\t.word\t0x000000ea\n+\t.word\t0x000000e6\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000c4\n+\t.word\t0x000000c0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000009a\n+\t.word\t0x00000096\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000036\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tadd.w\tr1, sp, #6720\t@ 0x1a40\n-\tadds\tr1, #4\n+\tldr\tr1, [sp, #32]\n+\tadd.w\tr2, sp, #6720\t@ 0x1a40\n+\tadds\tr2, #4\n \tmovs\tr3, #24\n-\tstr.w\tfp, [sp, #108]\t@ 0x6c\n+\tmov\tfp, r2\n+\tstr\tr2, [sp, #72]\t@ 0x48\n \tldr.w\tlr, [sp, #16]\n-\tmla\tr3, r3, r2, r1\n+\tmla\tr3, r3, r1, r2\n \tldr\tr2, [sp, #40]\t@ 0x28\n-\tldr.w\tfp, [sp, #152]\t@ 0x98\n \tstr\tr3, [sp, #96]\t@ 0x60\n \tadd.w\tr3, sp, #9664\t@ 0x25c0\n-\tmov.w\tr8, r2, lsl #3\n-\tldr\tr2, [sp, #112]\t@ 0x70\n \tadds\tr3, #60\t@ 0x3c\n-\tstr\tr1, [sp, #72]\t@ 0x48\n-\tstr\tr3, [sp, #4]\n+\tmov\tr1, fp\n+\tmov.w\tr8, r2, lsl #3\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tldr.w\tfp, [sp, #160]\t@ 0xa0\n+\tmov\tr4, r3\n+\tstr\tr3, [sp, #116]\t@ 0x74\n \tmov.w\tr9, r2, lsl #3\n-\tstrd\tsl, r3, [sp, #116]\t@ 0x74\n \tldrd\tr5, r6, [r1, #16]\n \tldrd\tr2, ip, [r1, #8]\n \tcmp\tr5, r6\n-\tbgt.n\t241a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13c2>\n+\tbgt.n\t222e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1442>\n \tcmp\tr2, ip\n-\tbgt.n\t241a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13c2>\n+\tbgt.n\t222e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1442>\n \tldrd\tr3, r0, [r1]\n \tcmp\tr3, r0\n-\tbgt.n\t241a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13c2>\n+\tbgt.n\t222e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1442>\n \tadds\tr6, #1\n \tadd.w\tip, ip, #1\n-\tsubs\tr4, r6, r5\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n-\tldr\tr4, [sp, #20]\n+\tsubs\tr6, r6, r5\n+\tstr\tr6, [sp, #92]\t@ 0x5c\n+\tldr\tr6, [sp, #20]\n \tsub.w\tip, ip, r2\n \tmul.w\tr2, fp, r2\n \tadds\tr0, #1\n \tsubs\tr0, r0, r3\n-\tstr\tr1, [sp, #124]\t@ 0x7c\n-\tmla\tr2, r4, r5, r2\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tstr\tr2, [sp, #104]\t@ 0x68\n-\tldr\tr2, [sp, #112]\t@ 0x70\n+\tstrd\tr4, r1, [sp, #120]\t@ 0x78\n+\tmla\tr2, r6, r5, r2\n+\tldr\tr5, [sp, #12]\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tldr\tr2, [sp, #104]\t@ 0x68\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd.w\tr7, r2, r3, lsl #3\n-\tldr\tr2, [sp, #4]\n-\tldr\tr3, [r2, #0]\n-\tmul.w\tr3, r4, r3\n-\tldr\tr4, [sp, #52]\t@ 0x34\n-\tadd.w\tsl, r4, r3, lsl #3\n-\tldr\tr3, [r2, #8]\n-\tldr\tr4, [sp, #12]\n-\tldr\tr2, [r2, #16]\n+\tldr\tr3, [r4, #0]\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tmul.w\tr3, r2, r3\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadd.w\tsl, r2, r3, lsl #3\n+\tldr\tr3, [r4, #8]\n+\tldr\tr2, [r4, #16]\n \tmul.w\tr3, r3, lr\n-\tmla\tr3, r2, r4, r3\n-\tldr\tr4, [sp, #148]\t@ 0x94\n-\tstr\tr3, [sp, #100]\t@ 0x64\n+\tmla\tr3, r2, r5, r3\n+\tldr\tr5, [sp, #156]\t@ 0x9c\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n \tmovs\tr2, #0\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tmov\tr6, r2\n-\tadds\tr5, r3, r4\n \tmov\tr4, r2\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tldr\tr3, [sp, #104]\t@ 0x68\n+\tadds\tr5, r3, r5\n+\tldr\tr2, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #112]\t@ 0x70\n \tadds\tr1, r2, r4\n \tmovs\tr2, #0\n \tadd\tr3, r5\n-\tstr\tr4, [sp, #128]\t@ 0x80\n+\tstrd\tr4, r5, [sp, #128]\t@ 0x80\n \tmov\tr4, r2\n \tmov\tr2, r1\n \tmov\tr1, r3\n \tmov\tr3, r4\n-\tstrd\tr5, r6, [sp, #152]\t@ 0x98\n+\tstr\tr6, [sp, #136]\t@ 0x88\n \tmov\tr6, r2\n \tmov\tr5, r1\n \tmovs\tr4, #0\n-\tstrd\tr2, r1, [sp, #44]\t@ 0x2c\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #4]\n+\tstrd\tr1, r3, [sp, #44]\t@ 0x2c\n \tadd.w\tr3, r7, r5, lsl #3\n \tadd.w\tr1, sl, r6, lsl #3\n \tmovs\tr2, #0\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tvldr\td17, [r1]\n+\tvldr\td6, [r1]\n \tcmp\tr0, r2\n \tadd\tr1, r8\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r9\n-\tbne.n\t23c8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1370>\n+\tbne.n\t21da <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13ee>\n \tadds\tr4, #1\n \tadd\tr5, fp\n \tadd\tr6, lr\n \tcmp\tip, r4\n-\tbne.n\t23be <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1366>\n-\tldrd\tr2, r1, [sp, #44]\t@ 0x2c\n+\tbne.n\t21d0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13e4>\n+\tldrd\tr1, r3, [sp, #44]\t@ 0x2c\n \tldr\tr4, [sp, #20]\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #4]\n+\tadds\tr3, #1\n \tadd\tr1, r4\n \tldr\tr4, [sp, #12]\n-\tadds\tr3, #1\n \tadd\tr2, r4\n \tldr\tr4, [sp, #92]\t@ 0x5c\n \tcmp\tr4, r3\n-\tbne.n\t23b2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x135a>\n-\tldrd\tr5, r6, [sp, #152]\t@ 0x98\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tldr\tr4, [sp, #128]\t@ 0x80\n-\tadds\tr6, #1\n+\tbne.n\t21c4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13d8>\n+\tldrd\tr4, r5, [sp, #128]\t@ 0x80\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr6, [sp, #136]\t@ 0x88\n \tadd\tr5, r3\n-\tldr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tadds\tr6, #1\n \tadd\tr4, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tcmp\tr3, r6\n-\tbne.n\t239a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1342>\n-\tldr\tr1, [sp, #124]\t@ 0x7c\n-\tldr\tr3, [sp, #4]\n+\tbne.n\t21ac <__gridxc_mesh3d_MOD_reducedata.isra.0+0x13c0>\n+\tldrd\tr4, r1, [sp, #120]\t@ 0x78\n \tadds\tr1, #24\n-\tadds\tr3, #24\n-\tstr\tr3, [sp, #4]\n \tldr\tr3, [sp, #96]\t@ 0x60\n+\tadds\tr4, #24\n \tcmp\tr3, r1\n-\tbne.n\t232a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12d2>\n-\tldr.w\tfp, [sp, #108]\t@ 0x6c\n-\tldrd\tsl, r3, [sp, #116]\t@ 0x74\n-\tb.w\t1c02 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbaa>\n+\tbne.n\t213c <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1350>\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tb.w\t1998 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbac>\n \tldr\tr3, [sp, #28]\n \tcmp\tr3, #0\n-\tbeq.w\t229a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n-\tcmp.w\tfp, #0\n-\tblt.w\t1c46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbee>\n-\tcmp.w\tsl, #0\n-\tbgt.w\t1c16 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbbe>\n-\tb.w\t1c46 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbee>\n+\tbeq.w\t20ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12c2>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr3, #0\n+\tblt.w\t19de <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbf2>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp\tr3, #0\n+\tbgt.w\t19ac <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbc0>\n+\tb.w\t19de <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbf2>\n \tldr.w\tr3, [r8]\n \tstr\tr3, [sp, #4]\n \tldr\tr3, [sp, #28]\n \tldr.w\tr9, [r8, #8]\n-\tldr.w\tr7, [r8, #4]\n+\tldr.w\tr6, [r8, #4]\n \tstr\tr3, [sp, #8]\n-\tb.w\t133e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x2e6>\n+\tb.w\t10d2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x2e6>\n \tmovs\tr0, #1\n \tmovs\tr4, #0\n-\tb.w\t132e <__gridxc_mesh3d_MOD_reducedata.isra.0+0x2d6>\n-\tldr\tr0, [pc, #64]\t@ (24b0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1458>)\n+\tb.w\t10c2 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x2d6>\n+\tldr\tr0, [pc, #64]\t@ (22bc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14d0>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tldr\tr1, [pc, #60]\t@ (24b4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x145c>)\n+\tldr\tr1, [pc, #60]\t@ (22c0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14d4>)\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #60]\t@ (24b8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1460>)\n+\tldr\tr0, [pc, #60]\t@ (22c4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14d8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n \tldr\tr3, [sp, #28]\n \tcmp\tr3, #0\n-\tbeq.w\t229a <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1242>\n-\tcmp.w\tfp, #0\n-\tblt.w\t1c4e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbf6>\n-\tcmp.w\tsl, #0\n-\tbgt.w\t1c16 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbbe>\n-\tb.w\t1c4e <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbf6>\n-\tldr\tr2, [pc, #24]\t@ (24bc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1464>)\n-\tldr\tr1, [pc, #28]\t@ (24c0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x1468>)\n-\tldr\tr0, [pc, #28]\t@ (24c4 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x146c>)\n+\tbeq.w\t20ae <__gridxc_mesh3d_MOD_reducedata.isra.0+0x12c2>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr3, #0\n+\tblt.w\t19e6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbfa>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp\tr3, #0\n+\tbgt.w\t19ac <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbc0>\n+\tb.w\t19e6 <__gridxc_mesh3d_MOD_reducedata.isra.0+0xbfa>\n+\tldr\tr2, [pc, #28]\t@ (22c8 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14dc>)\n+\tldr\tr1, [pc, #28]\t@ (22cc <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14e0>)\n+\tldr\tr0, [pc, #32]\t@ (22d0 <__gridxc_mesh3d_MOD_reducedata.isra.0+0x14e4>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\t.word\t0x0000003c\n+\tnop\n+\t.word\t0x0000003e\n R_ARM_REL32\t.LC0\n-\t.word\t0x00000034\n- R_ARM_REL32\t.LC1\n \t.word\t0x00000036\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000038\n R_ARM_REL32\t.LC11\n-\t.word\t0x00000012\n- R_ARM_REL32\t.LC17\n \t.word\t0x00000014\n- R_ARM_REL32\t.LC18\n+ R_ARM_REL32\t.LC17\n \t.word\t0x00000016\n+ R_ARM_REL32\t.LC18\n+\t.word\t0x00000018\n R_ARM_REL32\t.LC19\n \n-000024c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>:\n+000022d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>:\n __gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4064]\t@ 0xfe0\n-\tldr\tr7, [pc, #276]\t@ (25f0 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x128>)\n+\tldr\tr7, [pc, #276]\t@ (23fc <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x128>)\n \tsubs.w\tlr, r1, #0\n \tadd\tr7, pc\n-\tbgt.n\t24f4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x2c>\n-\tldr\tr3, [pc, #272]\t@ (25f4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x12c>)\n+\tbgt.n\t2300 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x2c>\n+\tldr\tr3, [pc, #272]\t@ (2400 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x12c>)\n \tmovs\tr1, #46\t@ 0x2e\n-\tldr\tr0, [pc, #272]\t@ (25f8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x130>)\n+\tldr\tr0, [pc, #272]\t@ (2404 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x130>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n \tldr\tr3, [r3, #0]\n \tbx\tr3\n-\tldr.w\tip, [pc, #260]\t@ 25fc <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x134>\n+\tldr.w\tip, [pc, #260]\t@ 2408 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x134>\n \tmov\tr6, r2\n \tmov\tr5, r3\n \tmovs\tr2, #1\n \tadd\tip, pc\n \tadd.w\tip, ip, #80\t@ 0x50\n \tsub.w\tr1, ip, #80\t@ 0x50\n-\tb.n\t250e <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x46>\n+\tb.n\t231a <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x46>\n \tcmp\tip, r1\n-\tbeq.n\t251c <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x54>\n+\tbeq.n\t2328 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x54>\n \tldr.w\tr3, [r1, #4]!\n \tcmp\tlr, r3\n-\tbne.n\t250a <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x42>\n+\tbne.n\t2316 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x42>\n \tldr.w\tr3, [ip, #-80]\n-\tcbnz\tr3, 2528 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x60>\n+\tcbnz\tr3, 2334 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x60>\n \tadds\tr2, #1\n \tadd.w\tip, ip, #364\t@ 0x16c\n \tcmp\tr2, #21\n-\tbne.n\t2504 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x3c>\n-\tb.n\t24e2 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x1a>\n-\tldr\tr3, [pc, #212]\t@ (2600 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x138>)\n+\tbne.n\t2310 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x3c>\n+\tb.n\t22ee <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x1a>\n+\tldr\tr3, [pc, #212]\t@ (240c <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x138>)\n \tsubs\tr4, r2, #1\n \tmov.w\tr2, #364\t@ 0x16c\n \tldr\tr1, [r0, #0]\n \tadd\tr3, pc\n \tmla\tr3, r2, r4, r3\n \tldr\tr2, [r3, #92]\t@ 0x5c\n \tcmp\tr1, r2\n-\tbne.n\t25e0 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n+\tbne.n\t23ec <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n \tldr\tr1, [r0, #4]\n \tldr\tr2, [r3, #96]\t@ 0x60\n \tcmp\tr1, r2\n-\tbne.n\t25e0 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n+\tbne.n\t23ec <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n \tldr\tr2, [r0, #8]\n \tldr\tr3, [r3, #100]\t@ 0x64\n \tcmp\tr2, r3\n-\tbne.n\t25e0 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n-\tldr\tr3, [pc, #180]\t@ (2604 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x13c>)\n+\tbne.n\t23ec <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x118>\n+\tldr\tr3, [pc, #180]\t@ (2410 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x13c>)\n \tmov.w\tr2, #364\t@ 0x16c\n \tldr\tr6, [r6, #0]\n \tadd\tr3, pc\n \tmla\tr3, r2, r4, r3\n \tldrd\tr1, r2, [r3, #340]\t@ 0x154\n \tldr.w\tr7, [r3, #328]\t@ 0x148\n \tldr.w\tr4, [r3, #308]\t@ 0x134\n@@ -3658,22 +3525,22 @@\n \tldr\tr1, [r0, r1]\n \tstr\tr1, [r5, #12]\n \tldr\tr1, [r0, r3]\n \tldr\tr3, [r0, r2]\n \tstr\tr4, [r5, #8]\n \tstrd\tr1, r3, [r5, #16]\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tldr\tr3, [pc, #16]\t@ (25f4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x12c>)\n+\tldr\tr3, [pc, #16]\t@ (2400 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x12c>)\n \tmovs\tr1, #37\t@ 0x25\n-\tldr\tr0, [pc, #32]\t@ (2608 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x140>)\n+\tldr\tr0, [pc, #32]\t@ (2414 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x140>)\n \tadd\tr0, pc\n \tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t254e <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x86>\n+\tb.n\t235a <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0+0x86>\n \t.word\t0x0000010e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x0000010c\n R_ARM_REL32\t.LC21\n \t.word\t0x000000fa\n@@ -3681,85 +3548,85 @@\n \t.word\t0x000000ca\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x000000aa\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x0000001e\n R_ARM_REL32\t.LC20\n \n-0000260c <__gridxc_mesh3d_MOD_samemeshdistr>:\n+00002418 <__gridxc_mesh3d_MOD_samemeshdistr>:\n __gridxc_mesh3d_MOD_samemeshdistr.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tldr\tr4, [r0, #0]\n \tldr\tr5, [r1, #0]\n \tsub\tsp, #100\t@ 0x64\n \tcmp\tr4, r5\n-\tbeq.n\t2690 <__gridxc_mesh3d_MOD_samemeshdistr+0x84>\n+\tbeq.n\t249c <__gridxc_mesh3d_MOD_samemeshdistr+0x84>\n \tcmp\tr4, #0\n-\tbeq.n\t268c <__gridxc_mesh3d_MOD_samemeshdistr+0x80>\n-\tble.n\t264e <__gridxc_mesh3d_MOD_samemeshdistr+0x42>\n-\tldr\tr1, [pc, #516]\t@ (2828 <__gridxc_mesh3d_MOD_samemeshdistr+0x21c>)\n+\tbeq.n\t2498 <__gridxc_mesh3d_MOD_samemeshdistr+0x80>\n+\tble.n\t245a <__gridxc_mesh3d_MOD_samemeshdistr+0x42>\n+\tldr\tr1, [pc, #516]\t@ (2634 <__gridxc_mesh3d_MOD_samemeshdistr+0x21c>)\n \tmovs\tr0, #1\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t2632 <__gridxc_mesh3d_MOD_samemeshdistr+0x26>\n+\tb.n\t243e <__gridxc_mesh3d_MOD_samemeshdistr+0x26>\n \tcmp\tr1, r3\n-\tbeq.n\t2644 <__gridxc_mesh3d_MOD_samemeshdistr+0x38>\n+\tbeq.n\t2450 <__gridxc_mesh3d_MOD_samemeshdistr+0x38>\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr4, r2\n-\tbne.n\t262e <__gridxc_mesh3d_MOD_samemeshdistr+0x22>\n+\tbne.n\t243a <__gridxc_mesh3d_MOD_samemeshdistr+0x22>\n \tldr.w\tr3, [r1, #-80]\n \tcmp\tr3, #0\n-\tbne.w\t27de <__gridxc_mesh3d_MOD_samemeshdistr+0x1d2>\n+\tbne.w\t25ea <__gridxc_mesh3d_MOD_samemeshdistr+0x1d2>\n \tadds\tr0, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr0, #21\n-\tbne.n\t2628 <__gridxc_mesh3d_MOD_samemeshdistr+0x1c>\n-\tcbz\tr5, 2682 <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n+\tbne.n\t2434 <__gridxc_mesh3d_MOD_samemeshdistr+0x1c>\n+\tcbz\tr5, 248e <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n \tmov.w\tr4, #4294967295\t@ 0xffffffff\n \tcmp\tr5, #0\n-\tble.n\t2682 <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n-\tldr\tr1, [pc, #464]\t@ (282c <__gridxc_mesh3d_MOD_samemeshdistr+0x220>)\n+\tble.n\t248e <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n+\tldr\tr1, [pc, #464]\t@ (2638 <__gridxc_mesh3d_MOD_samemeshdistr+0x220>)\n \tmovs\tr6, #1\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t266a <__gridxc_mesh3d_MOD_samemeshdistr+0x5e>\n+\tb.n\t2476 <__gridxc_mesh3d_MOD_samemeshdistr+0x5e>\n \tcmp\tr1, r3\n-\tbeq.n\t2678 <__gridxc_mesh3d_MOD_samemeshdistr+0x6c>\n+\tbeq.n\t2484 <__gridxc_mesh3d_MOD_samemeshdistr+0x6c>\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr5, r2\n-\tbne.n\t2666 <__gridxc_mesh3d_MOD_samemeshdistr+0x5a>\n+\tbne.n\t2472 <__gridxc_mesh3d_MOD_samemeshdistr+0x5a>\n \tldr.w\tr0, [r1, #-80]\n-\tcbnz\tr0, 269a <__gridxc_mesh3d_MOD_samemeshdistr+0x8e>\n+\tcbnz\tr0, 24a6 <__gridxc_mesh3d_MOD_samemeshdistr+0x8e>\n \tadds\tr6, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr6, #21\n-\tbne.n\t2660 <__gridxc_mesh3d_MOD_samemeshdistr+0x54>\n+\tbne.n\t246c <__gridxc_mesh3d_MOD_samemeshdistr+0x54>\n \tmovs\tr1, #0\n \tmov\tr0, r1\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tcmp\tr5, #0\n-\tbne.n\t2654 <__gridxc_mesh3d_MOD_samemeshdistr+0x48>\n+\tbne.n\t2460 <__gridxc_mesh3d_MOD_samemeshdistr+0x48>\n \tmovs\tr1, #1\n \tmov\tr0, r1\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \torr.w\tr3, r4, r6\n \tlsrs\tr1, r3, #31\n-\tbne.n\t2682 <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n+\tbne.n\t248e <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n \tcmp\tr4, r6\n-\tbeq.w\t2822 <__gridxc_mesh3d_MOD_samemeshdistr+0x216>\n+\tbeq.w\t262e <__gridxc_mesh3d_MOD_samemeshdistr+0x216>\n \tcmp\tr4, #0\n-\tbeq.n\t2692 <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n+\tbeq.n\t249e <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n \tsubs\tr2, r4, #1\n \tmov.w\tr3, #364\t@ 0x16c\n \tsubs\tr6, #1\n-\tldr\tr5, [pc, #376]\t@ (2830 <__gridxc_mesh3d_MOD_samemeshdistr+0x224>)\n+\tldr\tr5, [pc, #376]\t@ (263c <__gridxc_mesh3d_MOD_samemeshdistr+0x224>)\n \tmul.w\tr2, r3, r2\n \tadd\tr5, pc\n \tmul.w\tr3, r6, r3\n \tadds\tr6, r5, r2\n \tadd\tr5, r3\n \tldrd\tr7, r4, [r6, #356]\t@ 0x164\n \tstr\tr4, [sp, #40]\t@ 0x28\n@@ -3780,15 +3647,15 @@\n \tldr\tr4, [sp, #40]\t@ 0x28\n \tldr.w\tip, [r6, #308]\t@ 0x134\n \tldrd\tsl, fp, [r6, #332]\t@ 0x14c\n \tcmp\tr7, r4\n \tldr.w\tr8, [r5, #308]\t@ 0x134\n \tldr.w\tlr, [r5, #332]\t@ 0x14c\n \tldr.w\tr9, [r5, #356]\t@ 0x164\n-\tbgt.w\t2822 <__gridxc_mesh3d_MOD_samemeshdistr+0x216>\n+\tbgt.w\t262e <__gridxc_mesh3d_MOD_samemeshdistr+0x216>\n \tldr.w\tr5, [r5, #352]\t@ 0x160\n \tstr\tr5, [sp, #68]\t@ 0x44\n \tldr.w\tr6, [r6, #352]\t@ 0x160\n \tldr\tr4, [sp, #4]\n \tmla\tr5, r9, r5, r8\n \tstr\tr6, [sp, #64]\t@ 0x40\n \tstr\tr5, [sp, #32]\n@@ -3796,31 +3663,31 @@\n \tmla\tip, r7, r6, ip\n \tmul.w\tr6, sl, r4\n \tstr\tr0, [sp, #72]\t@ 0x48\n \tstr\tr6, [sp, #24]\n \tmov\tr0, r7\n \tstr.w\tsl, [sp, #36]\t@ 0x24\n \tmul.w\tr5, r5, lr\n-\tldr.w\tlr, [pc, #244]\t@ 2834 <__gridxc_mesh3d_MOD_samemeshdistr+0x228>\n+\tldr.w\tlr, [pc, #244]\t@ 2640 <__gridxc_mesh3d_MOD_samemeshdistr+0x228>\n \tstr\tr5, [sp, #28]\n-\tldr\tr5, [pc, #244]\t@ (2838 <__gridxc_mesh3d_MOD_samemeshdistr+0x22c>)\n+\tldr\tr5, [pc, #244]\t@ (2644 <__gridxc_mesh3d_MOD_samemeshdistr+0x22c>)\n \tadd\tlr, pc\n \tadd.w\tr8, lr, r2\n \tadd\tr5, pc\n \tadds\tr6, r5, r2\n \tstr\tr6, [sp, #56]\t@ 0x38\n \tmov\tr6, r1\n \tldr\tr1, [sp, #44]\t@ 0x2c\n \tadd\tr5, r3\n \tmov\tr2, r3\n \tmov\tr3, lr\n \tstr\tr5, [sp, #60]\t@ 0x3c\n \tldr\tr5, [sp, #16]\n \tcmp\tr1, r5\n-\tbgt.n\t2808 <__gridxc_mesh3d_MOD_samemeshdistr+0x1fc>\n+\tbgt.n\t2614 <__gridxc_mesh3d_MOD_samemeshdistr+0x1fc>\n \tldr\tr5, [sp, #56]\t@ 0x38\n \tmov\tsl, r1\n \tldr\tr7, [sp, #60]\t@ 0x3c\n \tadd.w\tr9, r3, r2\n \tldr\tr4, [sp, #52]\t@ 0x34\n \tldr.w\tr5, [r5, #340]\t@ 0x154\n \tldr.w\tr7, [r7, #340]\t@ 0x154\n@@ -3830,15 +3697,15 @@\n \tldr\tr5, [sp, #32]\n \tstrd\tr1, ip, [sp, #76]\t@ 0x4c\n \tstrd\tr0, r2, [sp, #84]\t@ 0x54\n \tstr\tr3, [sp, #92]\t@ 0x5c\n \tmla\tr5, r4, r7, r5\n \tldr\tr4, [sp, #36]\t@ 0x24\n \tcmp\tr4, fp\n-\tbgt.n\t27ea <__gridxc_mesh3d_MOD_samemeshdistr+0x1de>\n+\tbgt.n\t25f6 <__gridxc_mesh3d_MOD_samemeshdistr+0x1de>\n \tldr\tr3, [sp, #24]\n \tldr.w\tr7, [r8, #324]\t@ 0x144\n \tldr\tr2, [sp, #12]\n \tadd\tr3, lr\n \tldr.w\tr1, [r9, #324]\t@ 0x144\n \tldr\tr0, [sp, #20]\n \tstr\tr4, [sp, #36]\t@ 0x24\n@@ -3847,76 +3714,76 @@\n \tmul.w\tr7, r2, r7\n \tldr\tr2, [sp, #28]\n \tadd\tr2, r5\n \tmla\tr2, r1, r2, r0\n \tldr\tr0, [sp, #8]\n \tmul.w\tip, r0, r1\n \tmov\tr1, r4\n-\tb.n\t27c8 <__gridxc_mesh3d_MOD_samemeshdistr+0x1bc>\n+\tb.n\t25d4 <__gridxc_mesh3d_MOD_samemeshdistr+0x1bc>\n \tadd\tr2, ip\n \tcmp\tfp, r1\n-\tblt.n\t27e8 <__gridxc_mesh3d_MOD_samemeshdistr+0x1dc>\n+\tblt.n\t25f4 <__gridxc_mesh3d_MOD_samemeshdistr+0x1dc>\n \tldr\tr4, [r3, #0]\n \tadds\tr1, #1\n \tldr\tr0, [r2, #0]\n \tadd\tr3, r7\n \tcmp\tr4, r0\n-\tbeq.n\t27c2 <__gridxc_mesh3d_MOD_samemeshdistr+0x1b6>\n+\tbeq.n\t25ce <__gridxc_mesh3d_MOD_samemeshdistr+0x1b6>\n \tmov\tr1, r6\n \tmov\tr0, r1\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov\tr4, r0\n \tcmp\tr5, #0\n-\tbne.w\t2654 <__gridxc_mesh3d_MOD_samemeshdistr+0x48>\n-\tb.n\t2682 <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n+\tbne.w\t2460 <__gridxc_mesh3d_MOD_samemeshdistr+0x48>\n+\tb.n\t248e <__gridxc_mesh3d_MOD_samemeshdistr+0x76>\n \tldr\tr4, [sp, #36]\t@ 0x24\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tadd.w\tsl, sl, #1\n \tadd\tlr, r3\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tadd\tr5, r3\n \tldr\tr3, [sp, #16]\n \tcmp\tr3, sl\n-\tbge.n\t2790 <__gridxc_mesh3d_MOD_samemeshdistr+0x184>\n+\tbge.n\t259c <__gridxc_mesh3d_MOD_samemeshdistr+0x184>\n \tldrd\tr1, ip, [sp, #76]\t@ 0x4c\n \tstr\tr4, [sp, #36]\t@ 0x24\n \tldrd\tr0, r2, [sp, #84]\t@ 0x54\n \tldr\tr3, [sp, #92]\t@ 0x5c\n \tldr\tr4, [sp, #64]\t@ 0x40\n \tadds\tr0, #1\n \tldr\tr5, [sp, #68]\t@ 0x44\n \tadd\tip, r4\n \tldr\tr4, [sp, #32]\n \tadd\tr4, r5\n \tstr\tr4, [sp, #32]\n \tldr\tr4, [sp, #40]\t@ 0x28\n \tcmp\tr4, r0\n-\tbge.n\t275c <__gridxc_mesh3d_MOD_samemeshdistr+0x150>\n+\tbge.n\t2568 <__gridxc_mesh3d_MOD_samemeshdistr+0x150>\n \tldr\tr0, [sp, #72]\t@ 0x48\n \tmov\tr1, r0\n-\tb.n\t2692 <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n+\tb.n\t249e <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n \tmov\tr1, r0\n-\tb.n\t2692 <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n+\tb.n\t249e <__gridxc_mesh3d_MOD_samemeshdistr+0x86>\n \tnop\n \t.word\t0x00000200\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x000001cc\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000172\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x000000ec\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x000000ea\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \n-0000283c <__gridxc_mesh3d_MOD_nodemeshbox>:\n+00002648 <__gridxc_mesh3d_MOD_nodemeshbox>:\n __gridxc_mesh3d_MOD_nodemeshbox():\n \tldr\tr1, [r1, #0]\n-\tcbnz\tr1, 2870 <__gridxc_mesh3d_MOD_nodemeshbox+0x34>\n+\tcbnz\tr1, 267c <__gridxc_mesh3d_MOD_nodemeshbox+0x34>\n \tpush\t{lr}\n \tmov\tlr, r0\n \tmov\tip, r3\n \tldrd\tr0, r2, [r0]\n \tldr.w\tr3, [lr, #8]\n \tsubs\tr0, #1\n \tsubs\tr2, #1\n@@ -3924,299 +3791,302 @@\n \tstr.w\tr1, [ip]\n \tstr.w\tr1, [ip, #8]\n \tstr.w\tr1, [ip, #16]\n \tstr.w\tr0, [ip, #4]\n \tstr.w\tr2, [ip, #12]\n \tstr.w\tr3, [ip, #20]\n \tldr.w\tpc, [sp], #4\n-\tb.n\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tb.n\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n \tnop\n \n-00002874 <__gridxc_mesh3d_MOD_mymeshbox>:\n+00002680 <__gridxc_mesh3d_MOD_mymeshbox>:\n __gridxc_mesh3d_MOD_mymeshbox():\n \tldr\tr1, [r1, #0]\n \tmov\tr3, r2\n \tpush\t{r4, lr}\n-\tldr.w\tlr, [pc, #56]\t@ 28b4 <__gridxc_mesh3d_MOD_mymeshbox+0x40>\n+\tldr.w\tlr, [pc, #56]\t@ 26c0 <__gridxc_mesh3d_MOD_mymeshbox+0x40>\n \tsub\tsp, #8\n \tadd\tlr, pc\n-\tcbnz\tr1, 28a4 <__gridxc_mesh3d_MOD_mymeshbox+0x30>\n+\tcbnz\tr1, 26b0 <__gridxc_mesh3d_MOD_mymeshbox+0x30>\n \tmov\tip, r0\n \tstr\tr1, [r3, #0]\n \tldrd\tr4, r0, [r0]\n \tstr\tr1, [r3, #8]\n \tldr.w\tr2, [ip, #8]\n \tsubs\tr4, #1\n \tsubs\tr0, #1\n \tsubs\tr2, #1\n \tstr\tr1, [r3, #16]\n \tstr\tr4, [r3, #4]\n \tstr\tr0, [r3, #12]\n \tstr\tr2, [r3, #20]\n \tadd\tsp, #8\n \tpop\t{r4, pc}\n-\tldr\tr2, [pc, #16]\t@ (28b8 <__gridxc_mesh3d_MOD_mymeshbox+0x44>)\n+\tldr\tr2, [pc, #16]\t@ (26c4 <__gridxc_mesh3d_MOD_mymeshbox+0x44>)\n \tldr.w\tr2, [lr, r2]\n \tstr\tr2, [sp, #4]\n \tadd\tsp, #8\n \tldmia.w\tsp!, {r4, lr}\n-\tb.n\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tb.n\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n \t.word\t0x00000030\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n \n-000028bc <__gridxc_mesh3d_MOD_freemeshtask>:\n+000026c8 <__gridxc_mesh3d_MOD_freemeshtask>:\n __gridxc_mesh3d_MOD_freemeshtask.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4072]\t@ 0xfe8\n-\tldr\tr5, [pc, #544]\t@ (2af0 <__gridxc_mesh3d_MOD_freemeshtask+0x234>)\n+\tldr\tr5, [pc, #540]\t@ (28f8 <__gridxc_mesh3d_MOD_freemeshtask+0x230>)\n \tldr\tr2, [r0, #0]\n \tadd\tr5, pc\n \tcmp\tr2, #0\n-\tble.w\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n-\tldr\tr3, [pc, #536]\t@ (2af4 <__gridxc_mesh3d_MOD_freemeshtask+0x238>)\n+\tble.w\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n+\tldr\tr3, [pc, #532]\t@ (28fc <__gridxc_mesh3d_MOD_freemeshtask+0x234>)\n \tmovs\tr4, #1\n \tadd\tr3, pc\n-\tb.n\t2922 <__gridxc_mesh3d_MOD_freemeshtask+0x66>\n+\tb.n\t272e <__gridxc_mesh3d_MOD_freemeshtask+0x66>\n \tldr\tr1, [r3, #16]\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #20]\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #24]\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #28]\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #32]\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #36]\t@ 0x24\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #40]\t@ 0x28\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #44]\t@ 0x2c\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tldr\tr1, [r3, #48]\t@ 0x30\n \tcmp\tr2, r1\n-\tbeq.n\t2928 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n+\tbeq.n\t2734 <__gridxc_mesh3d_MOD_freemeshtask+0x6c>\n \tadds\tr4, #1\n \tadd.w\tr3, r3, #256\t@ 0x100\n \tcmp\tr4, #101\t@ 0x65\n-\tbeq.w\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbeq.w\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr1, [r3, #12]\n \tcmp\tr2, r1\n-\tbne.n\t28e0 <__gridxc_mesh3d_MOD_freemeshtask+0x24>\n-\tldr\tr3, [pc, #460]\t@ (2af8 <__gridxc_mesh3d_MOD_freemeshtask+0x23c>)\n+\tbne.n\t26ec <__gridxc_mesh3d_MOD_freemeshtask+0x24>\n+\tldr\tr3, [pc, #456]\t@ (2900 <__gridxc_mesh3d_MOD_freemeshtask+0x238>)\n \tsubs\tr1, r4, #1\n \tadd\tr3, pc\n \tlsls\tr6, r1, #8\n \tadd\tr3, r6\n \tldr\tr0, [r3, #12]\n \tcmp\tr2, r0\n-\tbeq.w\t2aa8 <__gridxc_mesh3d_MOD_freemeshtask+0x1ec>\n+\tbeq.w\t28b0 <__gridxc_mesh3d_MOD_freemeshtask+0x1e8>\n \tldr\tr0, [r3, #16]\n \tcmp\tr2, r0\n-\tbeq.w\t2aca <__gridxc_mesh3d_MOD_freemeshtask+0x20e>\n+\tbeq.w\t28d2 <__gridxc_mesh3d_MOD_freemeshtask+0x20a>\n \tldr\tr0, [r3, #20]\n \tcmp\tr2, r0\n-\tbeq.w\t2ac6 <__gridxc_mesh3d_MOD_freemeshtask+0x20a>\n+\tbeq.w\t28ce <__gridxc_mesh3d_MOD_freemeshtask+0x206>\n \tldr\tr0, [r3, #24]\n \tcmp\tr2, r0\n-\tbeq.w\t2ace <__gridxc_mesh3d_MOD_freemeshtask+0x212>\n+\tbeq.w\t28d6 <__gridxc_mesh3d_MOD_freemeshtask+0x20e>\n \tldr\tr0, [r3, #28]\n \tcmp\tr2, r0\n-\tbeq.w\t2abe <__gridxc_mesh3d_MOD_freemeshtask+0x202>\n+\tbeq.w\t28c6 <__gridxc_mesh3d_MOD_freemeshtask+0x1fe>\n \tldr\tr0, [r3, #32]\n \tcmp\tr2, r0\n-\tbeq.w\t2ac2 <__gridxc_mesh3d_MOD_freemeshtask+0x206>\n+\tbeq.w\t28ca <__gridxc_mesh3d_MOD_freemeshtask+0x202>\n \tldr\tr0, [r3, #36]\t@ 0x24\n \tcmp\tr2, r0\n-\tbeq.w\t2ad6 <__gridxc_mesh3d_MOD_freemeshtask+0x21a>\n+\tbeq.w\t28de <__gridxc_mesh3d_MOD_freemeshtask+0x216>\n \tldr\tr0, [r3, #40]\t@ 0x28\n \tcmp\tr2, r0\n-\tbeq.w\t2ada <__gridxc_mesh3d_MOD_freemeshtask+0x21e>\n+\tbeq.w\t28e2 <__gridxc_mesh3d_MOD_freemeshtask+0x21a>\n \tldr\tr0, [r3, #44]\t@ 0x2c\n \tcmp\tr2, r0\n-\tbeq.w\t2ad2 <__gridxc_mesh3d_MOD_freemeshtask+0x216>\n+\tbeq.w\t28da <__gridxc_mesh3d_MOD_freemeshtask+0x212>\n \tldr\tr3, [r3, #48]\t@ 0x30\n \tcmp\tr3, r2\n \tit\teq\n \tmoveq\tr3, #9\n-\tbeq.w\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n-\tldr\tr3, [pc, #372]\t@ (2afc <__gridxc_mesh3d_MOD_freemeshtask+0x240>)\n+\tbeq.w\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n+\tldr\tr3, [pc, #368]\t@ (2904 <__gridxc_mesh3d_MOD_freemeshtask+0x23c>)\n \tadd\tr3, pc\n \tadd\tr3, r6\n \tldr\tr2, [r3, #12]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #16]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #20]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #24]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #28]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #32]\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #36]\t@ 0x24\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr2, [r3, #44]\t@ 0x2c\n \tcmp\tr2, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n \tldr\tr3, [r3, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tbge.n\t2a56 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n-\tldr\tr2, [pc, #308]\t@ (2b00 <__gridxc_mesh3d_MOD_freemeshtask+0x244>)\n+\tbge.n\t285e <__gridxc_mesh3d_MOD_freemeshtask+0x196>\n+\tldr\tr2, [pc, #304]\t@ (2908 <__gridxc_mesh3d_MOD_freemeshtask+0x240>)\n \tadd.w\tr3, r6, #48\t@ 0x30\n \tadd\tr2, pc\n \tadd\tr3, r2\n \tadds\tr7, r3, #4\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbgt.n\t2a5a <__gridxc_mesh3d_MOD_freemeshtask+0x19e>\n+\tbgt.n\t2862 <__gridxc_mesh3d_MOD_freemeshtask+0x19a>\n \tldr.w\tr3, [r7, #4]!\n \tmov.w\tr8, #2\n \tcmp\tr3, #0\n-\tbgt.n\t2a5e <__gridxc_mesh3d_MOD_freemeshtask+0x1a2>\n-\tldr\tr7, [pc, #284]\t@ (2b04 <__gridxc_mesh3d_MOD_freemeshtask+0x248>)\n+\tbgt.n\t2866 <__gridxc_mesh3d_MOD_freemeshtask+0x19e>\n+\tldr\tr7, [pc, #280]\t@ (290c <__gridxc_mesh3d_MOD_freemeshtask+0x244>)\n \tadd\tr7, pc\n \tadds\tr4, r7, r6\n \tldr.w\tr0, [r4, #220]\t@ 0xdc\n \tcmp\tr0, #0\n-\tbeq.n\t2ade <__gridxc_mesh3d_MOD_freemeshtask+0x222>\n+\tbeq.n\t28e6 <__gridxc_mesh3d_MOD_freemeshtask+0x21e>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr0, [r4, #184]\t@ 0xb8\n \tmovs\tr5, #0\n \tstr.w\tr5, [r4, #220]\t@ 0xdc\n \tcmp\tr0, #0\n-\tbeq.n\t2ade <__gridxc_mesh3d_MOD_freemeshtask+0x222>\n+\tbeq.n\t28e6 <__gridxc_mesh3d_MOD_freemeshtask+0x21e>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r4, #124]\t@ 0x7c\n \tstr.w\tr5, [r4, #184]\t@ 0xb8\n \tcmp\tr0, #0\n-\tbeq.n\t2ade <__gridxc_mesh3d_MOD_freemeshtask+0x222>\n+\tbeq.n\t28e6 <__gridxc_mesh3d_MOD_freemeshtask+0x21e>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr0, [r4, #64]\t@ 0x40\n \tstr\tr5, [r4, #124]\t@ 0x7c\n \tcmp\tr0, #0\n-\tbeq.n\t2ade <__gridxc_mesh3d_MOD_freemeshtask+0x222>\n+\tbeq.n\t28e6 <__gridxc_mesh3d_MOD_freemeshtask+0x21e>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tvmov.i32\td19, #0\t@ 0x00000000\n-\tvmov.i8\tq8, #255\t@ 0xff\n-\tadds\tr2, r7, r6\n-\tvmov.i8\td18, #255\t@ 0xff\n-\tadd.w\tr3, r6, #12\n-\tadd\tr3, r7\n-\tadds\tr2, #52\t@ 0x34\n+\tadds\tr1, r7, #4\n+\tmovs\tr2, #0\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [r4]\n+\tadd.w\tr2, r6, #48\t@ 0x30\n \tstr\tr5, [r4, #64]\t@ 0x40\n+\tadd.w\tr0, r6, #12\n \tstr\tr5, [r4, #8]\n-\tvstr\td19, [r4]\n-\tvst1.32\t{d18}, [r2]\n-\tvst1.8\t{d16-d17}, [r3]\n-\tvstr\td16, [r3, #16]\n-\tvstr\td16, [r3, #24]\n-\tvstr\td16, [r3, #32]\n+\tadds\tr4, r2, r1\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tadd\tr0, r7\n+\tstr\tr3, [r1, r2]\n+\tmovs\tr2, #40\t@ 0x28\n+\tstr\tr3, [r4, #4]\n+\tmovs\tr1, #255\t@ 0xff\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, lr}\n+\tb.w\t0 \n+ R_ARM_THM_JUMP24\tmemset\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, pc}\n \tmov.w\tr8, #1\n \tsubs\tr3, #1\n \tmov.w\tr2, #364\t@ 0x16c\n \tmovs\tr0, #0\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tmul.w\tr1, r2, r3\n-\tldr\tr2, [pc, #152]\t@ (2b08 <__gridxc_mesh3d_MOD_freemeshtask+0x24c>)\n+\tldr\tr2, [pc, #152]\t@ (2910 <__gridxc_mesh3d_MOD_freemeshtask+0x248>)\n \tadd.w\tr3, r1, #100\t@ 0x64\n \tadd\tr2, pc\n \tadd\tr3, r2\n \tadd.w\tr2, r2, #300\t@ 0x12c\n \tadd\tr1, r2\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr4, r2\n-\tbne.n\t2a8c <__gridxc_mesh3d_MOD_freemeshtask+0x1d0>\n-\tmovs\tr0, #1\n-\tstr.w\tip, [r3]\n+\titt\teq\n+\tstreq.w\tip, [r3]\n+\tmoveq\tr0, #1\n \tcmp\tr3, r1\n-\tbne.n\t2a7e <__gridxc_mesh3d_MOD_freemeshtask+0x1c2>\n-\tcbnz\tr0, 2aa0 <__gridxc_mesh3d_MOD_freemeshtask+0x1e4>\n-\tldr\tr3, [pc, #120]\t@ (2b0c <__gridxc_mesh3d_MOD_freemeshtask+0x250>)\n+\tbne.n\t2886 <__gridxc_mesh3d_MOD_freemeshtask+0x1be>\n+\tcbnz\tr0, 28a8 <__gridxc_mesh3d_MOD_freemeshtask+0x1e0>\n+\tldr\tr3, [pc, #120]\t@ (2914 <__gridxc_mesh3d_MOD_freemeshtask+0x24c>)\n \tmovs\tr1, #52\t@ 0x34\n-\tldr\tr0, [pc, #120]\t@ (2b10 <__gridxc_mesh3d_MOD_freemeshtask+0x254>)\n+\tldr\tr0, [pc, #120]\t@ (2918 <__gridxc_mesh3d_MOD_freemeshtask+0x250>)\n \tadd\tr0, pc\n \tldr\tr3, [r5, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tcmp.w\tr8, #2\n-\tbne.n\t29da <__gridxc_mesh3d_MOD_freemeshtask+0x11e>\n-\tb.n\t29e6 <__gridxc_mesh3d_MOD_freemeshtask+0x12a>\n+\tbne.n\t27e6 <__gridxc_mesh3d_MOD_freemeshtask+0x11e>\n+\tb.n\t27f2 <__gridxc_mesh3d_MOD_freemeshtask+0x12a>\n \tmovs\tr3, #0\n-\tldr\tr2, [pc, #104]\t@ (2b14 <__gridxc_mesh3d_MOD_freemeshtask+0x258>)\n+\tldr\tr2, [pc, #104]\t@ (291c <__gridxc_mesh3d_MOD_freemeshtask+0x254>)\n \tadd.w\tr3, r3, r1, lsl #6\n \tmov.w\tr1, #4294967295\t@ 0xffffffff\n \tadd\tr2, pc\n \tadd.w\tr3, r2, r3, lsl #2\n \tstr\tr1, [r3, #12]\n-\tb.n\t2986 <__gridxc_mesh3d_MOD_freemeshtask+0xca>\n+\tb.n\t2792 <__gridxc_mesh3d_MOD_freemeshtask+0xca>\n \tmovs\tr3, #4\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #5\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #2\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #1\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #3\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #8\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #6\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n \tmovs\tr3, #7\n-\tb.n\t2aaa <__gridxc_mesh3d_MOD_freemeshtask+0x1ee>\n-\tldr\tr2, [pc, #56]\t@ (2b18 <__gridxc_mesh3d_MOD_freemeshtask+0x25c>)\n-\tldr\tr1, [pc, #56]\t@ (2b1c <__gridxc_mesh3d_MOD_freemeshtask+0x260>)\n-\tldr\tr0, [pc, #60]\t@ (2b20 <__gridxc_mesh3d_MOD_freemeshtask+0x264>)\n+\tb.n\t28b2 <__gridxc_mesh3d_MOD_freemeshtask+0x1ea>\n+\tldr\tr2, [pc, #56]\t@ (2920 <__gridxc_mesh3d_MOD_freemeshtask+0x258>)\n+\tldr\tr1, [pc, #56]\t@ (2924 <__gridxc_mesh3d_MOD_freemeshtask+0x25c>)\n+\tldr\tr0, [pc, #60]\t@ (2928 <__gridxc_mesh3d_MOD_freemeshtask+0x260>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n \tnop\n-\t.word\t0x0000021c\n+\t.word\t0x00000218\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000214\n+\t.word\t0x00000210\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000001c8\n+\t.word\t0x000001c4\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x00000170\n+\t.word\t0x0000016c\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x0000012e\n+\t.word\t0x0000012a\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x00000118\n+\t.word\t0x00000114\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n \t.word\t0x00000090\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000074\n R_ARM_REL32\t.LC22\n@@ -4225,180 +4095,180 @@\n \t.word\t0x00000030\n R_ARM_REL32\t.LC23\n \t.word\t0x00000032\n R_ARM_REL32\t.LC18\n \t.word\t0x00000034\n R_ARM_REL32\t.LC24\n \n-00002b24 <__gridxc_mesh3d_MOD_freemeshdistr>:\n+0000292c <__gridxc_mesh3d_MOD_freemeshdistr>:\n __gridxc_mesh3d_MOD_freemeshdistr.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n-\tldr\tr2, [pc, #384]\t@ (2cb8 <__gridxc_mesh3d_MOD_freemeshdistr+0x194>)\n+\tldr\tr2, [pc, #384]\t@ (2ac0 <__gridxc_mesh3d_MOD_freemeshdistr+0x194>)\n \tsub\tsp, #8\n-\tldr\tr3, [pc, #384]\t@ (2cbc <__gridxc_mesh3d_MOD_freemeshdistr+0x198>)\n+\tldr\tr3, [pc, #384]\t@ (2ac4 <__gridxc_mesh3d_MOD_freemeshdistr+0x198>)\n \tadd\tr2, pc\n-\tldr\tr5, [pc, #384]\t@ (2cc0 <__gridxc_mesh3d_MOD_freemeshdistr+0x19c>)\n+\tldr\tr5, [pc, #384]\t@ (2ac8 <__gridxc_mesh3d_MOD_freemeshdistr+0x19c>)\n \tldr\tr0, [r0, #0]\n \tadd\tr5, pc\n \tldr\tr3, [r2, r3]\n \tcmp\tr0, #0\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #4]\n \tmov.w\tr3, #0\n-\tbgt.n\t2b6c <__gridxc_mesh3d_MOD_freemeshdistr+0x48>\n-\tldr\tr2, [pc, #368]\t@ (2cc4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1a0>)\n-\tldr\tr3, [pc, #360]\t@ (2cbc <__gridxc_mesh3d_MOD_freemeshdistr+0x198>)\n+\tbgt.n\t2974 <__gridxc_mesh3d_MOD_freemeshdistr+0x48>\n+\tldr\tr2, [pc, #368]\t@ (2acc <__gridxc_mesh3d_MOD_freemeshdistr+0x1a0>)\n+\tldr\tr3, [pc, #360]\t@ (2ac4 <__gridxc_mesh3d_MOD_freemeshdistr+0x198>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #4]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2cb4 <__gridxc_mesh3d_MOD_freemeshdistr+0x190>\n+\tbne.w\t2abc <__gridxc_mesh3d_MOD_freemeshdistr+0x190>\n \tadd\tsp, #8\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tldr\tr7, [pc, #344]\t@ (2cc8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1a4>)\n+\tldr\tr7, [pc, #344]\t@ (2ad0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1a4>)\n \tmovs\tr6, #1\n \tadd\tr7, pc\n \tadd.w\tip, r7, #80\t@ 0x50\n \tmov\tr1, ip\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t2b82 <__gridxc_mesh3d_MOD_freemeshdistr+0x5e>\n+\tb.n\t298a <__gridxc_mesh3d_MOD_freemeshdistr+0x5e>\n \tcmp\tr3, r1\n-\tbeq.n\t2b90 <__gridxc_mesh3d_MOD_freemeshdistr+0x6c>\n+\tbeq.n\t2998 <__gridxc_mesh3d_MOD_freemeshdistr+0x6c>\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr0, r2\n-\tbne.n\t2b7e <__gridxc_mesh3d_MOD_freemeshdistr+0x5a>\n+\tbne.n\t2986 <__gridxc_mesh3d_MOD_freemeshdistr+0x5a>\n \tldr.w\tr3, [r1, #-80]\n-\tcbnz\tr3, 2b9c <__gridxc_mesh3d_MOD_freemeshdistr+0x78>\n+\tcbnz\tr3, 29a4 <__gridxc_mesh3d_MOD_freemeshdistr+0x78>\n \tadds\tr6, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr6, #21\n-\tbne.n\t2b78 <__gridxc_mesh3d_MOD_freemeshdistr+0x54>\n-\tb.n\t2b50 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n+\tbne.n\t2980 <__gridxc_mesh3d_MOD_freemeshdistr+0x54>\n+\tb.n\t2958 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n \tsubs\tr6, #1\n \tmov.w\tlr, #364\t@ 0x16c\n-\tldr\tr3, [pc, #296]\t@ (2ccc <__gridxc_mesh3d_MOD_freemeshdistr+0x1a8>)\n+\tldr\tr3, [pc, #296]\t@ (2ad4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1a8>)\n \tmovs\tr2, #0\n \tmul.w\tlr, lr, r6\n \tadd\tr3, pc\n \tadd\tr3, lr\n \tmov\tr1, r3\n-\tb.n\t2bb8 <__gridxc_mesh3d_MOD_freemeshdistr+0x94>\n+\tb.n\t29c0 <__gridxc_mesh3d_MOD_freemeshdistr+0x94>\n \tadds\tr2, #1\n \tcmp\tr2, #20\n-\tbeq.n\t2bd4 <__gridxc_mesh3d_MOD_freemeshdistr+0xb0>\n+\tbeq.n\t29dc <__gridxc_mesh3d_MOD_freemeshdistr+0xb0>\n \tldr.w\tr4, [r1, #4]!\n \tcmp\tr4, r0\n-\tbne.n\t2bb2 <__gridxc_mesh3d_MOD_freemeshdistr+0x8e>\n+\tbne.n\t29ba <__gridxc_mesh3d_MOD_freemeshdistr+0x8e>\n \tmovs\tr1, #91\t@ 0x5b\n \tmla\tr2, r1, r6, r2\n-\tldr\tr1, [pc, #264]\t@ (2cd0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1ac>)\n+\tldr\tr1, [pc, #264]\t@ (2ad8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1ac>)\n \tadd\tr1, pc\n \tadd.w\tr2, r1, r2, lsl #2\n \tmov.w\tr1, #4294967295\t@ 0xffffffff\n \tstr\tr1, [r2, #4]\n \tadd\tip, lr\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr2, #0\n-\tbge.n\t2b50 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n+\tbge.n\t2958 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n \tcmp\tr3, ip\n-\tbne.n\t2bd6 <__gridxc_mesh3d_MOD_freemeshdistr+0xb2>\n+\tbne.n\t29de <__gridxc_mesh3d_MOD_freemeshdistr+0xb2>\n \tadd.w\tr7, r7, #300\t@ 0x12c\n-\tldr\tr3, [pc, #236]\t@ (2cd4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1b0>)\n-\tldr.w\tr9, [pc, #236]\t@ 2cd8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1b4>\n+\tldr\tr3, [pc, #236]\t@ (2adc <__gridxc_mesh3d_MOD_freemeshdistr+0x1b0>)\n+\tldr.w\tr9, [pc, #236]\t@ 2ae0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1b4>\n \tadd.w\tsl, r7, lr\n-\tldr.w\tr8, [pc, #232]\t@ 2cdc <__gridxc_mesh3d_MOD_freemeshdistr+0x1b8>\n+\tldr.w\tr8, [pc, #232]\t@ 2ae4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1b8>\n \tadd.w\tr4, lr, #100\t@ 0x64\n-\tldr\tr7, [pc, #228]\t@ (2ce0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1bc>)\n+\tldr\tr7, [pc, #228]\t@ (2ae8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1bc>)\n \tadd\tr3, pc\n \tadd\tr4, r3\n \tadd\tr9, pc\n \tadd\tr7, pc\n \tadd\tr8, pc\n-\tb.n\t2c0a <__gridxc_mesh3d_MOD_freemeshdistr+0xe6>\n+\tb.n\t2a12 <__gridxc_mesh3d_MOD_freemeshdistr+0xe6>\n \tcmp\tsl, r4\n-\tbeq.n\t2c7a <__gridxc_mesh3d_MOD_freemeshdistr+0x156>\n+\tbeq.n\t2a82 <__gridxc_mesh3d_MOD_freemeshdistr+0x156>\n \tldr.w\tr3, [r4, #4]!\n \tcmp\tr3, #0\n-\tble.n\t2c06 <__gridxc_mesh3d_MOD_freemeshdistr+0xe2>\n+\tble.n\t2a0e <__gridxc_mesh3d_MOD_freemeshdistr+0xe2>\n \tsubs\tr3, #1\n \tlsls\tr3, r3, #8\n \tadds\tr2, r7, r3\n \tldr\tr1, [r2, #12]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #16]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #20]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #24]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #28]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #32]\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #36]\t@ 0x24\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr1, [r2, #40]\t@ 0x28\n \tstr\tr1, [sp, #0]\n \tcmp\tr1, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tldr\tr2, [r2, #44]\t@ 0x2c\n \tstr\tr2, [sp, #0]\n \tcmp\tr2, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n \tadd\tr3, r9\n \tldr\tr3, [r3, #48]\t@ 0x30\n \tstr\tr3, [sp, #0]\n \tcmp\tr3, #0\n-\tbgt.n\t2c9c <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n-\tldr\tr3, [pc, #120]\t@ (2ce4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1c0>)\n+\tbgt.n\t2aa4 <__gridxc_mesh3d_MOD_freemeshdistr+0x178>\n+\tldr\tr3, [pc, #120]\t@ (2aec <__gridxc_mesh3d_MOD_freemeshdistr+0x1c0>)\n \tmovs\tr1, #43\t@ 0x2b\n \tmov\tr0, r8\n \tldr\tr3, [r5, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tcmp\tsl, r4\n-\tbne.n\t2c0a <__gridxc_mesh3d_MOD_freemeshdistr+0xe6>\n+\tbne.n\t2a12 <__gridxc_mesh3d_MOD_freemeshdistr+0xe6>\n \tmov.w\tr4, #364\t@ 0x16c\n-\tldr\tr5, [pc, #104]\t@ (2ce8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1c4>)\n+\tldr\tr5, [pc, #104]\t@ (2af0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1c4>)\n \tadd\tr5, pc\n \tmul.w\tr4, r6, r4\n \tadds\tr6, r5, r4\n \tldr.w\tr0, [r6, #304]\t@ 0x130\n-\tcbz\tr0, 2ca4 <__gridxc_mesh3d_MOD_freemeshdistr+0x180>\n+\tcbz\tr0, 2aac <__gridxc_mesh3d_MOD_freemeshdistr+0x180>\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmovs\tr3, #0\n \tstr.w\tr3, [r6, #304]\t@ 0x130\n \tstr\tr3, [r5, r4]\n-\tb.n\t2b50 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n+\tb.n\t2958 <__gridxc_mesh3d_MOD_freemeshdistr+0x2c>\n \tmov\tr0, sp\n-\tbl\t28bc <__gridxc_mesh3d_MOD_freemeshtask>\n-\tb.n\t2c06 <__gridxc_mesh3d_MOD_freemeshdistr+0xe2>\n-\tldr\tr2, [pc, #68]\t@ (2cec <__gridxc_mesh3d_MOD_freemeshdistr+0x1c8>)\n-\tldr\tr1, [pc, #72]\t@ (2cf0 <__gridxc_mesh3d_MOD_freemeshdistr+0x1cc>)\n-\tldr\tr0, [pc, #72]\t@ (2cf4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1d0>)\n+\tbl\t26c8 <__gridxc_mesh3d_MOD_freemeshtask>\n+\tb.n\t2a0e <__gridxc_mesh3d_MOD_freemeshdistr+0xe2>\n+\tldr\tr2, [pc, #68]\t@ (2af4 <__gridxc_mesh3d_MOD_freemeshdistr+0x1c8>)\n+\tldr\tr1, [pc, #72]\t@ (2af8 <__gridxc_mesh3d_MOD_freemeshdistr+0x1cc>)\n+\tldr\tr0, [pc, #72]\t@ (2afc <__gridxc_mesh3d_MOD_freemeshdistr+0x1d0>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n@@ -4431,97 +4301,97 @@\n \t.word\t0x0000003e\n R_ARM_REL32\t.LC26\n \t.word\t0x00000040\n R_ARM_REL32\t.LC18\n \t.word\t0x00000042\n R_ARM_REL32\t.LC27\n \n-00002cf8 <__gridxc_mesh3d_MOD_reducedistr>:\n+00002b00 <__gridxc_mesh3d_MOD_reducedistr>:\n __gridxc_mesh3d_MOD_reducedistr():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3960]\t@ 0xf78\n-\tldr\tr5, [pc, #636]\t@ (2f88 <__gridxc_mesh3d_MOD_reducedistr+0x290>)\n+\tldr\tr5, [pc, #636]\t@ (2d90 <__gridxc_mesh3d_MOD_reducedistr+0x290>)\n \tmov\tr4, r0\n \tldr\tr0, [r0, #0]\n \tsub\tsp, #100\t@ 0x64\n \tadd\tr5, pc\n \tcmp\tr0, #0\n-\tbeq.w\t2f62 <__gridxc_mesh3d_MOD_reducedistr+0x26a>\n-\tble.n\t2d48 <__gridxc_mesh3d_MOD_reducedistr+0x50>\n-\tldr\tr1, [pc, #624]\t@ (2f8c <__gridxc_mesh3d_MOD_reducedistr+0x294>)\n+\tbeq.w\t2d6a <__gridxc_mesh3d_MOD_reducedistr+0x26a>\n+\tble.n\t2b50 <__gridxc_mesh3d_MOD_reducedistr+0x50>\n+\tldr\tr1, [pc, #624]\t@ (2d94 <__gridxc_mesh3d_MOD_reducedistr+0x294>)\n \tmovs\tr6, #1\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t2d2c <__gridxc_mesh3d_MOD_reducedistr+0x34>\n+\tb.n\t2b34 <__gridxc_mesh3d_MOD_reducedistr+0x34>\n \tcmp\tr1, r3\n-\tbeq.n\t2d3e <__gridxc_mesh3d_MOD_reducedistr+0x46>\n+\tbeq.n\t2b46 <__gridxc_mesh3d_MOD_reducedistr+0x46>\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr0, r2\n-\tbne.n\t2d28 <__gridxc_mesh3d_MOD_reducedistr+0x30>\n+\tbne.n\t2b30 <__gridxc_mesh3d_MOD_reducedistr+0x30>\n \tldr.w\tr3, [r1, #-80]\n \tcmp\tr3, #0\n-\tbne.w\t2f68 <__gridxc_mesh3d_MOD_reducedistr+0x270>\n+\tbne.w\t2d70 <__gridxc_mesh3d_MOD_reducedistr+0x270>\n \tadds\tr6, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr6, #21\n-\tbne.n\t2d22 <__gridxc_mesh3d_MOD_reducedistr+0x2a>\n-\tldr\tr3, [pc, #580]\t@ (2f90 <__gridxc_mesh3d_MOD_reducedistr+0x298>)\n+\tbne.n\t2b2a <__gridxc_mesh3d_MOD_reducedistr+0x2a>\n+\tldr\tr3, [pc, #580]\t@ (2d98 <__gridxc_mesh3d_MOD_reducedistr+0x298>)\n \tmovs\tr1, #41\t@ 0x29\n-\tldr\tr0, [pc, #580]\t@ (2f94 <__gridxc_mesh3d_MOD_reducedistr+0x29c>)\n+\tldr\tr0, [pc, #580]\t@ (2d9c <__gridxc_mesh3d_MOD_reducedistr+0x29c>)\n \tadd\tr0, pc\n \tldr\tr3, [r5, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmvn.w\tr3, #1\n \tstr\tr3, [sp, #0]\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmov\tr6, r3\n-\tldr\tr2, [pc, #564]\t@ (2f98 <__gridxc_mesh3d_MOD_reducedistr+0x2a0>)\n+\tldr\tr2, [pc, #564]\t@ (2da0 <__gridxc_mesh3d_MOD_reducedistr+0x2a0>)\n \tmov.w\tr1, #364\t@ 0x16c\n \tldr\tr0, [sp, #0]\n \tmov.w\tlr, #1\n \tadd\tr2, pc\n-\tldr\tr3, [pc, #552]\t@ (2f9c <__gridxc_mesh3d_MOD_reducedistr+0x2a4>)\n+\tldr\tr3, [pc, #552]\t@ (2da4 <__gridxc_mesh3d_MOD_reducedistr+0x2a4>)\n \tmov\tip, lr\n \tadd\tr3, pc\n \tmla\tr7, r1, r0, r2\n \tmov\tr2, r6\n-\tb.n\t2d8e <__gridxc_mesh3d_MOD_reducedistr+0x96>\n+\tb.n\t2b96 <__gridxc_mesh3d_MOD_reducedistr+0x96>\n \tadd.w\tip, ip, #1\n \tadd.w\tr3, r3, #364\t@ 0x16c\n \tcmp.w\tip, #21\n-\tbeq.w\t2f62 <__gridxc_mesh3d_MOD_reducedistr+0x26a>\n+\tbeq.w\t2d6a <__gridxc_mesh3d_MOD_reducedistr+0x26a>\n \tcmp\tr2, ip\n-\tbeq.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbeq.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tbeq.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbeq.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr0, [r3, #84]\t@ 0x54\n \tldr\tr1, [r7, #84]\t@ 0x54\n \tcmp\tr0, r1\n-\tbne.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbne.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr0, [r3, #88]\t@ 0x58\n \tldr\tr1, [r7, #88]\t@ 0x58\n \tcmp\tr0, r1\n-\tbne.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbne.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr0, [r3, #92]\t@ 0x5c\n \tldr\tr1, [r7, #92]\t@ 0x5c\n \tcmp\tr0, r1\n-\tbne.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbne.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr0, [r3, #96]\t@ 0x60\n \tldr\tr1, [r7, #96]\t@ 0x60\n \tcmp\tr0, r1\n-\tbne.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbne.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr\tr0, [r3, #100]\t@ 0x64\n \tldr\tr1, [r7, #100]\t@ 0x64\n \tcmp\tr0, r1\n-\tbne.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tbne.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tldr.w\tr0, [r3, #304]\t@ 0x130\n \tstr\tr0, [sp, #12]\n \tldr.w\tr0, [r3, #344]\t@ 0x158\n \tstr\tr0, [sp, #36]\t@ 0x24\n \tldr.w\tr0, [r3, #348]\t@ 0x15c\n \tstr\tr0, [sp, #16]\n \tldr.w\tr0, [r7, #304]\t@ 0x130\n@@ -4536,40 +4406,40 @@\n \tstr\tr0, [sp, #4]\n \tldr.w\tr0, [r7, #328]\t@ 0x148\n \tldr.w\tr9, [r3, #308]\t@ 0x134\n \tldrd\tsl, r8, [r3, #332]\t@ 0x14c\n \tstr\tr0, [sp, #8]\n \tldr.w\tlr, [r7, #308]\t@ 0x134\n \tldr.w\tfp, [r7, #356]\t@ 0x164\n-\tbgt.w\t2f6e <__gridxc_mesh3d_MOD_reducedistr+0x276>\n+\tbgt.w\t2d76 <__gridxc_mesh3d_MOD_reducedistr+0x276>\n \tldr.w\tr0, [r3, #352]\t@ 0x160\n \tstr\tr0, [sp, #48]\t@ 0x30\n \tstr\tr2, [sp, #56]\t@ 0x38\n \tmov\tr2, r4\n \tstr\tr1, [sp, #28]\n \tmla\tr9, r0, r1, r9\n \tldr.w\tr0, [r7, #352]\t@ 0x160\n \tstr\tr0, [sp, #52]\t@ 0x34\n \tstr\tr7, [sp, #32]\n \tmla\tfp, r0, fp, lr\n \tldr\tr7, [sp, #36]\t@ 0x24\n \tldr\tr1, [sp, #16]\n \tcmp\tr7, r1\n-\tbgt.n\t2f12 <__gridxc_mesh3d_MOD_reducedistr+0x21a>\n+\tbgt.n\t2d1a <__gridxc_mesh3d_MOD_reducedistr+0x21a>\n \tldr\tr1, [sp, #0]\n \tmov.w\tr4, #364\t@ 0x16c\n-\tldr.w\tlr, [pc, #360]\t@ 2fa0 <__gridxc_mesh3d_MOD_reducedistr+0x2a8>\n+\tldr.w\tlr, [pc, #360]\t@ 2da8 <__gridxc_mesh3d_MOD_reducedistr+0x2a8>\n \tstr.w\tfp, [sp, #92]\t@ 0x5c\n \tadd\tlr, pc\n \tstr\tr6, [sp, #88]\t@ 0x58\n \tmul.w\tr4, r1, r4\n \tstr.w\tip, [sp, #76]\t@ 0x4c\n \tadd\tlr, r4\n \tldr.w\tr1, [lr, #340]\t@ 0x154\n-\tldr.w\tlr, [pc, #340]\t@ 2fa4 <__gridxc_mesh3d_MOD_reducedistr+0x2ac>\n+\tldr.w\tlr, [pc, #340]\t@ 2dac <__gridxc_mesh3d_MOD_reducedistr+0x2ac>\n \tmov\tr0, r1\n \tstr\tr1, [sp, #84]\t@ 0x54\n \tadd\tlr, pc\n \tldr.w\tr1, [r3, #340]\t@ 0x154\n \tadd\tr4, lr\n \tstr\tr4, [sp, #72]\t@ 0x48\n \tldr\tr4, [sp, #4]\n@@ -4585,15 +4455,15 @@\n \tldr\tr0, [sp, #8]\n \tmov\tfp, r9\n \tmov\tr9, r3\n \tmul.w\tr1, r0, r1\n \tstrd\tr1, r4, [sp, #64]\t@ 0x40\n \tldr\tr1, [sp, #32]\n \tcmp\tsl, r8\n-\tbgt.n\t2eea <__gridxc_mesh3d_MOD_reducedistr+0x1f2>\n+\tbgt.n\t2cf2 <__gridxc_mesh3d_MOD_reducedistr+0x1f2>\n \tldr\tr6, [sp, #24]\n \tldr\tr0, [sp, #60]\t@ 0x3c\n \tldr.w\tr4, [r9, #324]\t@ 0x144\n \tadd\tr0, r6\n \tldr\tr6, [sp, #12]\n \tldr\tr3, [sp, #72]\t@ 0x48\n \tstr.w\tsl, [sp, #32]\n@@ -4605,93 +4475,93 @@\n \tldr\tr6, [sp, #20]\n \tadd\tr4, r7\n \tmla\tr4, r3, r4, r6\n \tldr\tr6, [sp, #8]\n \tmul.w\tlr, r6, r3\n \tmov\tr6, sl\n \tmov\tsl, r7\n-\tb.n\t2eca <__gridxc_mesh3d_MOD_reducedistr+0x1d2>\n+\tb.n\t2cd2 <__gridxc_mesh3d_MOD_reducedistr+0x1d2>\n \tadd\tr4, lr\n \tcmp\tr8, r6\n-\tblt.n\t2ee4 <__gridxc_mesh3d_MOD_reducedistr+0x1ec>\n+\tblt.n\t2cec <__gridxc_mesh3d_MOD_reducedistr+0x1ec>\n \tldr\tr7, [r0, #0]\n \tadds\tr6, #1\n \tldr\tr3, [r4, #0]\n \tadd\tr0, ip\n \tcmp\tr7, r3\n-\tbeq.n\t2ec4 <__gridxc_mesh3d_MOD_reducedistr+0x1cc>\n+\tbeq.n\t2ccc <__gridxc_mesh3d_MOD_reducedistr+0x1cc>\n \tmov\tr4, r2\n \tldr.w\tip, [sp, #76]\t@ 0x4c\n \tldr\tr2, [sp, #56]\t@ 0x38\n \tmov\tr3, r9\n \tmov\tr7, r1\n-\tb.n\t2d7e <__gridxc_mesh3d_MOD_reducedistr+0x86>\n+\tb.n\t2b86 <__gridxc_mesh3d_MOD_reducedistr+0x86>\n \tmov\tr7, sl\n \tldr.w\tsl, [sp, #32]\n \tldr\tr0, [sp, #24]\n \tldr\tr4, [sp, #80]\t@ 0x50\n \tldr\tr3, [sp, #68]\t@ 0x44\n \tadd\tr0, r4\n \tstr\tr0, [sp, #24]\n \tldr\tr0, [sp, #84]\t@ 0x54\n \tadds\tr3, #1\n \tstr\tr3, [sp, #68]\t@ 0x44\n \tadd\tr7, r0\n \tldr\tr0, [sp, #16]\n \tcmp\tr0, r3\n-\tbge.n\t2e8a <__gridxc_mesh3d_MOD_reducedistr+0x192>\n+\tbge.n\t2c92 <__gridxc_mesh3d_MOD_reducedistr+0x192>\n \tmov\tr3, r9\n \tldr\tr6, [sp, #88]\t@ 0x58\n \tmov\tr9, fp\n \tldr.w\tip, [sp, #76]\t@ 0x4c\n \tldr.w\tfp, [sp, #92]\t@ 0x5c\n \tstr\tr1, [sp, #32]\n \tldr\tr1, [sp, #48]\t@ 0x30\n \tldr\tr4, [sp, #28]\n \tadd\tr9, r1\n \tldr\tr1, [sp, #52]\t@ 0x34\n \tadds\tr4, #1\n \tstr\tr4, [sp, #28]\n \tadd\tfp, r1\n \tcmp\tr6, r4\n-\tbge.n\t2e26 <__gridxc_mesh3d_MOD_reducedistr+0x12e>\n+\tbge.n\t2c2e <__gridxc_mesh3d_MOD_reducedistr+0x12e>\n \tmov\tlr, ip\n \tmov\tr4, r2\n \tmov\tr0, r4\n \tadd.w\tr6, lr, #4294967295\t@ 0xffffffff\n-\tbl\t2b24 <__gridxc_mesh3d_MOD_freemeshdistr>\n-\tldr\tr2, [pc, #116]\t@ (2fa8 <__gridxc_mesh3d_MOD_reducedistr+0x2b0>)\n+\tbl\t292c <__gridxc_mesh3d_MOD_freemeshdistr>\n+\tldr\tr2, [pc, #116]\t@ (2db0 <__gridxc_mesh3d_MOD_reducedistr+0x2b0>)\n \tmov.w\tr3, #364\t@ 0x16c\n \tadd\tr2, pc\n \tmla\tr2, r3, r6, r2\n \tmovs\tr3, #0\n-\tb.n\t2f48 <__gridxc_mesh3d_MOD_reducedistr+0x250>\n+\tb.n\t2d50 <__gridxc_mesh3d_MOD_reducedistr+0x250>\n \tadds\tr3, #1\n \tcmp\tr3, #20\n-\tbeq.n\t2f72 <__gridxc_mesh3d_MOD_reducedistr+0x27a>\n+\tbeq.n\t2d7a <__gridxc_mesh3d_MOD_reducedistr+0x27a>\n \tldr.w\tr1, [r2, #4]!\n \tcmp\tr1, #0\n-\tbge.n\t2f42 <__gridxc_mesh3d_MOD_reducedistr+0x24a>\n+\tbge.n\t2d4a <__gridxc_mesh3d_MOD_reducedistr+0x24a>\n \tmovs\tr0, #91\t@ 0x5b\n-\tldr\tr2, [pc, #88]\t@ (2fac <__gridxc_mesh3d_MOD_reducedistr+0x2b4>)\n+\tldr\tr2, [pc, #88]\t@ (2db4 <__gridxc_mesh3d_MOD_reducedistr+0x2b4>)\n \tldr\tr1, [r4, #0]\n \tadd\tr2, pc\n \tmla\tr3, r0, r6, r3\n \tadd.w\tr3, r2, r3, lsl #2\n \tstr\tr1, [r3, #4]\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr3, r6, #1\n \tstr\tr3, [sp, #0]\n-\tb.n\t2d62 <__gridxc_mesh3d_MOD_reducedistr+0x6a>\n+\tb.n\t2b6a <__gridxc_mesh3d_MOD_reducedistr+0x6a>\n \tmov\tlr, ip\n-\tb.n\t2f28 <__gridxc_mesh3d_MOD_reducedistr+0x230>\n-\tldr\tr3, [pc, #28]\t@ (2f90 <__gridxc_mesh3d_MOD_reducedistr+0x298>)\n+\tb.n\t2d30 <__gridxc_mesh3d_MOD_reducedistr+0x230>\n+\tldr\tr3, [pc, #28]\t@ (2d98 <__gridxc_mesh3d_MOD_reducedistr+0x298>)\n \tmovs\tr1, #56\t@ 0x38\n-\tldr\tr0, [pc, #56]\t@ (2fb0 <__gridxc_mesh3d_MOD_reducedistr+0x2b8>)\n+\tldr\tr0, [pc, #56]\t@ (2db8 <__gridxc_mesh3d_MOD_reducedistr+0x2b8>)\n \tadd\tr0, pc\n \tldr\tr3, [r5, r3]\n \tldr\tr3, [r3, #0]\n \tadd\tsp, #100\t@ 0x64\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tnop\n@@ -4714,1425 +4584,1458 @@\n \t.word\t0x0000006c\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000052\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000034\n R_ARM_REL32\t.LC29\n \n-00002fb4 <__gridxc_mesh3d_MOD_setmeshdistr>:\n+00002dbc <__gridxc_mesh3d_MOD_setmeshdistr>:\n __gridxc_mesh3d_MOD_setmeshdistr.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d10}\n-\tvpush\t{d12-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #2704]\t@ 0xa90\n-\tsubw\tsp, sp, #1300\t@ 0x514\n-\tmov\tr9, r2\n-\tldr.w\tr2, [pc, #1636]\t@ 3638 <__gridxc_mesh3d_MOD_setmeshdistr+0x684>\n-\tmov\tr4, r3\n-\tldr.w\tr3, [pc, #1632]\t@ 363c <__gridxc_mesh3d_MOD_setmeshdistr+0x688>\n+\tstr.w\tr0, [ip, #2824]\t@ 0xb08\n+\tsubw\tsp, sp, #1236\t@ 0x4d4\n+\tmov\tr4, r0\n+\tmov\tr5, r3\n+\tldr.w\tr3, [pc, #2816]\t@ 38d8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb1c>\n+\tstr\tr4, [sp, #196]\t@ 0xc4\n+\tmov\tr4, r2\n+\tldr.w\tr2, [pc, #2812]\t@ 38dc <__gridxc_mesh3d_MOD_setmeshdistr+0xb20>\n+\tstr\tr1, [sp, #84]\t@ 0x54\n \tadd\tr2, pc\n-\tstr\tr1, [sp, #72]\t@ 0x48\n-\tstr\tr0, [sp, #192]\t@ 0xc0\n-\tldr.w\tr1, [sp, #1416]\t@ 0x588\n+\tldr.w\tr1, [sp, #1296]\t@ 0x510\n+\tldr.w\tr0, [sp, #1272]\t@ 0x4f8\n+\tldr.w\tr7, [sp, #1284]\t@ 0x504\n+\tmov\tfp, r1\n \tldr\tr3, [r2, r3]\n-\tldr.w\tr7, [sp, #1392]\t@ 0x570\n-\tmov\tsl, r1\n+\tldr.w\tr6, [sp, #1288]\t@ 0x508\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [sp, #1292]\t@ 0x50c\n+\tstr.w\tr3, [sp, #1228]\t@ 0x4cc\n \tmov.w\tr3, #0\n-\tldr.w\tr3, [pc, #1604]\t@ 3640 <__gridxc_mesh3d_MOD_setmeshdistr+0x68c>\n-\tldr.w\tr8, [sp, #1404]\t@ 0x57c\n+\tldr.w\tr3, [pc, #2780]\t@ 38e0 <__gridxc_mesh3d_MOD_setmeshdistr+0xb24>\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tldr.w\tr3, [sp, #1396]\t@ 0x574\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr.w\tr3, [sp, #1276]\t@ 0x4fc\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tldr.w\tr3, [sp, #1280]\t@ 0x500\n \tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr3, [sp, #1400]\t@ 0x578\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr.w\tr3, [sp, #1412]\t@ 0x584\n-\tldr.w\tr5, [sp, #1408]\t@ 0x580\n-\tstr\tr3, [sp, #196]\t@ 0xc4\n-\tcbz\tr1, 3050 <__gridxc_mesh3d_MOD_setmeshdistr+0x9c>\n-\tldr.w\tsl, [r1]\n-\tcmp.w\tsl, #0\n-\tbeq.n\t3050 <__gridxc_mesh3d_MOD_setmeshdistr+0x9c>\n+\tldr.w\tr3, [sp, #1292]\t@ 0x50c\n+\tstr\tr3, [sp, #200]\t@ 0xc8\n+\tcbz\tr1, 2e52 <__gridxc_mesh3d_MOD_setmeshdistr+0x96>\n+\tldr.w\tfp, [r1]\n+\tcmp.w\tfp, #0\n+\tbeq.n\t2e52 <__gridxc_mesh3d_MOD_setmeshdistr+0x96>\n \tldr\tr3, [r1, #24]\n-\tldr.w\tfp, [r1, #36]\t@ 0x24\n+\tldr.w\tr8, [r1, #36]\t@ 0x24\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr3, #1\n \tstr\tr3, [sp, #116]\t@ 0x74\n \tldrd\tr3, r2, [r1, #28]\n \tsubs\tr3, r2, r3\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #100]\t@ 0x64\n \tldrd\tr3, r2, [r1, #40]\t@ 0x28\n \tsubs\tr3, r2, r3\n-\tstr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n \tldrd\tr3, r2, [r1, #52]\t@ 0x34\n \tsubs\tr3, r2, r3\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tstr\tr3, [sp, #104]\t@ 0x68\n \tldr\tr3, [r1, #48]\t@ 0x30\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tldr.w\tr3, [pc, #1520]\t@ 3644 <__gridxc_mesh3d_MOD_setmeshdistr+0x690>\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr6, [r1, r3]\n-\tldr\tr3, [r6, #0]\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr.w\tr3, [pc, #2704]\t@ 38e4 <__gridxc_mesh3d_MOD_setmeshdistr+0xb28>\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr.w\tr9, [r1, r3]\n+\tldr.w\tr3, [r9]\n \tcmp\tr3, #1\n-\tbeq.w\t32aa <__gridxc_mesh3d_MOD_setmeshdistr+0x2f6>\n-\tcmp\tr7, #0\n-\tbeq.w\t32a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x2f2>\n-\tldr\tr2, [r7, #0]\n+\tbeq.w\t30d4 <__gridxc_mesh3d_MOD_setmeshdistr+0x318>\n+\tcmp\tr0, #0\n+\tbeq.w\t30d0 <__gridxc_mesh3d_MOD_setmeshdistr+0x314>\n+\tldr\tr2, [r0, #0]\n \tcmp\tr3, r2\n \tit\tge\n \tcmpge\tr2, #0\n-\tbgt.w\t334a <__gridxc_mesh3d_MOD_setmeshdistr+0x396>\n-\tldr.w\tr3, [pc, #1492]\t@ 3648 <__gridxc_mesh3d_MOD_setmeshdistr+0x694>\n-\tldr.w\tr0, [pc, #1492]\t@ 364c <__gridxc_mesh3d_MOD_setmeshdistr+0x698>\n+\tit\tgt\n+\tstrgt\tr2, [sp, #280]\t@ 0x118\n+\tbgt.n\t2e8c <__gridxc_mesh3d_MOD_setmeshdistr+0xd0>\n+\tldr.w\tr3, [pc, #2668]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n+\tldr.w\tr0, [pc, #2668]\t@ 38ec <__gridxc_mesh3d_MOD_setmeshdistr+0xb30>\n \tadd\tr0, pc\n \tldr\tr3, [r1, r3]\n \tmovs\tr1, #39\t@ 0x27\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tcmp\tr4, #0\n-\tbeq.w\t32a2 <__gridxc_mesh3d_MOD_setmeshdistr+0x2ee>\n-\tldr\tr3, [r4, #0]\n-\tldr\tr2, [sp, #336]\t@ 0x150\n+\tcmp\tr5, #0\n+\tbeq.w\t30b2 <__gridxc_mesh3d_MOD_setmeshdistr+0x2f6>\n+\tldr\tr3, [r5, #0]\n+\tldr\tr2, [sp, #280]\t@ 0x118\n \tcmp\tr3, #0\n-\tblt.n\t309c <__gridxc_mesh3d_MOD_setmeshdistr+0xe8>\n-\tldr\tr1, [r6, #0]\n+\tblt.n\t2ea8 <__gridxc_mesh3d_MOD_setmeshdistr+0xec>\n+\tldr.w\tr1, [r9]\n \tadd\tr2, r3\n \tcmp\tr2, r1\n-\tble.w\t334e <__gridxc_mesh3d_MOD_setmeshdistr+0x39a>\n-\tldr.w\tr3, [pc, #1448]\t@ 3648 <__gridxc_mesh3d_MOD_setmeshdistr+0x694>\n+\tit\tle\n+\tstrle\tr3, [sp, #288]\t@ 0x120\n+\tble.n\t2ebc <__gridxc_mesh3d_MOD_setmeshdistr+0x100>\n+\tldr.w\tr3, [pc, #2620]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #49\t@ 0x31\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr.w\tr0, [pc, #1448]\t@ 3650 <__gridxc_mesh3d_MOD_setmeshdistr+0x69c>\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [pc, #2620]\t@ 38f0 <__gridxc_mesh3d_MOD_setmeshdistr+0xb34>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tldr\tr3, [r1, #0]\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tcmp\tr5, #0\n-\tbeq.w\t3292 <__gridxc_mesh3d_MOD_setmeshdistr+0x2de>\n-\tldr\tr2, [r5, #0]\n-\tadd\tr0, sp, #332\t@ 0x14c\n-\tstr\tr0, [sp, #148]\t@ 0x94\n-\tmov\tr0, r3\n-\tstr\tr2, [sp, #112]\t@ 0x70\n-\tstr\tr2, [sp, #332]\t@ 0x14c\n-\tsdiv\tr3, r3, r2\n-\tmls\tr3, r2, r3, r0\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tcmp\tr3, #0\n-\tbne.w\t3280 <__gridxc_mesh3d_MOD_setmeshdistr+0x2cc>\n-\tldr\tr3, [r1, #4]\n-\tmov\tr0, r1\n-\tmov\tr1, r2\n-\tsdiv\tr2, r3, r2\n-\tmls\tr3, r1, r2, r3\n-\tcmp\tr3, #0\n-\tbne.w\t3280 <__gridxc_mesh3d_MOD_setmeshdistr+0x2cc>\n-\tldr\tr2, [r0, #8]\n-\tmov\tr0, r1\n-\tsdiv\tr1, r2, r1\n-\tmls\tr2, r0, r1, r2\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n-\tcmp\tr2, #0\n-\tbne.w\t327e <__gridxc_mesh3d_MOD_setmeshdistr+0x2ca>\n-\tldr\tr1, [sp, #192]\t@ 0xc0\n-\tadd\tr2, sp, #348\t@ 0x15c\n+\tldr\tr5, [sp, #84]\t@ 0x54\n+\tldr\tr0, [r5, #0]\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tcmp\tr6, #0\n+\tbeq.w\t30c0 <__gridxc_mesh3d_MOD_setmeshdistr+0x304>\n \tldr\tr3, [r6, #0]\n-\tadd\tr7, sp, #340\t@ 0x154\n-\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tadd\tr2, sp, #276\t@ 0x114\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tmov\tr1, r3\n+\tmov\tsl, r3\n+\tstr\tr2, [sp, #156]\t@ 0x9c\n+\tstr\tr3, [sp, #276]\t@ 0x114\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tstr\tr1, [sp, #124]\t@ 0x7c\n+\tcmp\tr1, #0\n+\tbne.w\t309c <__gridxc_mesh3d_MOD_setmeshdistr+0x2e0>\n+\tldr\tr0, [r5, #4]\n+\tmov\tr1, sl\n+\tmov\tr6, r5\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr5, r1\n+\tcmp\tr1, #0\n+\tbne.w\t309c <__gridxc_mesh3d_MOD_setmeshdistr+0x2e0>\n+\tldr\tr0, [r6, #8]\n+\tmov\tr1, sl\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tstr\tr1, [sp, #124]\t@ 0x7c\n+\tcmp\tr1, #0\n+\tbne.w\t309a <__gridxc_mesh3d_MOD_setmeshdistr+0x2de>\n+\tldr\tr1, [sp, #196]\t@ 0xc4\n+\tadd\tr2, sp, #292\t@ 0x124\n+\tldr.w\tr3, [r9]\n+\tstr\tr2, [sp, #208]\t@ 0xd0\n \tldr\tr1, [r1, #0]\n \tcmp\tr3, #1\n-\tstr\tr1, [sp, #204]\t@ 0xcc\n-\tstr\tr1, [sp, #348]\t@ 0x15c\n-\tbeq.w\t3352 <__gridxc_mesh3d_MOD_setmeshdistr+0x39e>\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tadd\tr3, sp, #336\t@ 0x150\n-\tadd\tr2, sp, #344\t@ 0x158\n-\tmov\tr0, r7\n+\tstr\tr1, [sp, #212]\t@ 0xd4\n+\tadd\tr3, sp, #284\t@ 0x11c\n+\tstr\tr1, [sp, #292]\t@ 0x124\n+\tbeq.w\t3174 <__gridxc_mesh3d_MOD_setmeshdistr+0x3b8>\n+\tmov\tr5, r3\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tadd\tr3, sp, #280\t@ 0x118\n+\tadd\tr2, sp, #288\t@ 0x120\n+\tmov\tr0, r5\n \tbl\t40 <__gridxc_mesh3d_MOD_initdistr.part.0>\n-\tldr\tr4, [r7, #0]\n-\tcmp\tr4, #0\n-\tbeq.w\t3356 <__gridxc_mesh3d_MOD_setmeshdistr+0x3a2>\n-\tble.n\t315c <__gridxc_mesh3d_MOD_setmeshdistr+0x1a8>\n-\tldr.w\tr1, [pc, #1316]\t@ 3654 <__gridxc_mesh3d_MOD_setmeshdistr+0x6a0>\n+\tldr\tr6, [r5, #0]\n+\tcmp\tr6, #0\n+\tbeq.w\t317c <__gridxc_mesh3d_MOD_setmeshdistr+0x3c0>\n+\tble.n\t2f66 <__gridxc_mesh3d_MOD_setmeshdistr+0x1aa>\n+\tldr.w\tr1, [pc, #2492]\t@ 38f4 <__gridxc_mesh3d_MOD_setmeshdistr+0xb38>\n \tmovs\tr0, #0\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t3140 <__gridxc_mesh3d_MOD_setmeshdistr+0x18c>\n+\tb.n\t2f4a <__gridxc_mesh3d_MOD_setmeshdistr+0x18e>\n \tcmp\tr1, r3\n-\tbeq.n\t3152 <__gridxc_mesh3d_MOD_setmeshdistr+0x19e>\n+\tbeq.n\t2f5c <__gridxc_mesh3d_MOD_setmeshdistr+0x1a0>\n \tldr.w\tr2, [r3, #4]!\n-\tcmp\tr2, r4\n-\tbne.n\t313c <__gridxc_mesh3d_MOD_setmeshdistr+0x188>\n+\tcmp\tr2, r6\n+\tbne.n\t2f46 <__gridxc_mesh3d_MOD_setmeshdistr+0x18a>\n \tldr.w\tr3, [r1, #-80]\n \tcmp\tr3, #0\n-\tbne.w\t3360 <__gridxc_mesh3d_MOD_setmeshdistr+0x3ac>\n+\tbne.w\t3184 <__gridxc_mesh3d_MOD_setmeshdistr+0x3c8>\n \tadds\tr0, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr0, #20\n-\tbne.n\t3136 <__gridxc_mesh3d_MOD_setmeshdistr+0x182>\n-\tmvn.w\tr3, #1\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tcmp.w\tr9, #0\n-\tbeq.n\t31f8 <__gridxc_mesh3d_MOD_setmeshdistr+0x244>\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tmov.w\tr8, #364\t@ 0x16c\n-\tldr.w\tr5, [pc, #1256]\t@ 3658 <__gridxc_mesh3d_MOD_setmeshdistr+0x6a4>\n-\tadd\tr5, pc\n-\tmul.w\tr8, r8, r3\n-\tadd.w\tr6, r8, #304\t@ 0x130\n-\tadd\tr6, r5\n-\tmov\tr0, r6\n+\tbne.n\t2f40 <__gridxc_mesh3d_MOD_setmeshdistr+0x184>\n+\tmvn.w\tsl, #1\n+\tcmp\tr4, #0\n+\tbeq.n\t2ff8 <__gridxc_mesh3d_MOD_setmeshdistr+0x23c>\n+\tmov.w\tr9, #364\t@ 0x16c\n+\tldr.w\tr7, [pc, #2436]\t@ 38f8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb3c>\n+\tadd\tr7, pc\n+\tmul.w\tr9, r9, sl\n+\tadd.w\tr8, r9, #304\t@ 0x130\n+\tadd\tr8, r7\n+\tadd\tr7, r9\n+\tmov\tr0, r8\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tmov\tr2, r9\n-\tadd.w\tr3, r5, r8\n+\tldr\tr3, [r4, #4]\n+\tstr\tr3, [r0, #4]\n \tmov\tr5, r0\n-\tvld1.32\t{d18-d19}, [r2]!\n-\tvld1.32\t{d16}, [r2]\n-\tmov\tr2, r0\n-\tvst1.32\t{d18-d19}, [r2]!\n-\tvst1.32\t{d16}, [r2]\n-\tldr.w\tr3, [r3, #304]\t@ 0x130\n+\tldr\tr3, [r4, #8]\n+\tstr\tr3, [r0, #8]\n+\tldr\tr3, [r4, #12]\n+\tstr\tr3, [r0, #12]\n+\tldr\tr3, [r4, #16]\n+\tstr\tr3, [r0, #16]\n+\tldr\tr3, [r4, #20]\n+\tstr\tr3, [r0, #20]\n+\tldr\tr3, [r4, #0]\n+\tstr\tr3, [r0, #0]\n+\tldr.w\tr3, [r7, #304]\t@ 0x130\n \tcmp\tr3, r0\n-\tbeq.n\t31b4 <__gridxc_mesh3d_MOD_setmeshdistr+0x200>\n-\tmov\tr0, r6\n+\tbeq.n\t2fba <__gridxc_mesh3d_MOD_setmeshdistr+0x1fe>\n+\tmov\tr0, r8\n \tmov\tr1, r5\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #200]\t@ 0xc8\n-\tmov\tr1, r7\n-\tbl\t260c <__gridxc_mesh3d_MOD_samemeshdistr>\n+\tldr\tr4, [sp, #160]\t@ 0xa0\n+\tldr\tr0, [sp, #208]\t@ 0xd0\n+\tmov\tr1, r4\n+\tbl\t2418 <__gridxc_mesh3d_MOD_samemeshdistr>\n \tcmp\tr0, #0\n-\tbeq.n\t3270 <__gridxc_mesh3d_MOD_setmeshdistr+0x2bc>\n-\tmov\tr0, r7\n-\tbl\t2b24 <__gridxc_mesh3d_MOD_freemeshdistr>\n-\tldr\tr4, [sp, #204]\t@ 0xcc\n-\tldr\tr3, [sp, #192]\t@ 0xc0\n-\tldr.w\tr2, [pc, #1168]\t@ 365c <__gridxc_mesh3d_MOD_setmeshdistr+0x6a8>\n-\tstr\tr4, [r3, #0]\n+\tbeq.n\t308c <__gridxc_mesh3d_MOD_setmeshdistr+0x2d0>\n+\tmov\tr0, r4\n+\tbl\t292c <__gridxc_mesh3d_MOD_freemeshdistr>\n+\tldr\tr6, [sp, #212]\t@ 0xd4\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tldr.w\tr2, [pc, #2344]\t@ 38fc <__gridxc_mesh3d_MOD_setmeshdistr+0xb40>\n+\tstr\tr6, [r3, #0]\n \tadd\tr2, pc\n-\tldr.w\tr3, [pc, #1128]\t@ 363c <__gridxc_mesh3d_MOD_setmeshdistr+0x688>\n+\tldr.w\tr3, [pc, #2300]\t@ 38d8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb1c>\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [sp, #1292]\t@ 0x50c\n+\tldr.w\tr3, [sp, #1228]\t@ 0x4cc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t400e <__gridxc_mesh3d_MOD_setmeshdistr+0x105a>\n-\taddw\tsp, sp, #1300\t@ 0x514\n-\tvpop\t{d12-d15}\n-\tvpop\t{d8-d10}\n+\tbne.w\t3d92 <__gridxc_mesh3d_MOD_setmeshdistr+0xfd6>\n+\taddw\tsp, sp, #1236\t@ 0x4d4\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tcmp.w\tsl, #0\n-\tbeq.w\t3364 <__gridxc_mesh3d_MOD_setmeshdistr+0x3b0>\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tcmp.w\tfp, #0\n+\tbeq.w\t3188 <__gridxc_mesh3d_MOD_setmeshdistr+0x3cc>\n+\tldr\tr3, [sp, #200]\t@ 0xc8\n \tcmp\tr3, #0\n-\tbeq.w\t3338 <__gridxc_mesh3d_MOD_setmeshdistr+0x384>\n-\tldr.w\tr3, [pc, #1108]\t@ 3660 <__gridxc_mesh3d_MOD_setmeshdistr+0x6ac>\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr1, [sp, #344]\t@ 0x158\n+\tbeq.w\t315e <__gridxc_mesh3d_MOD_setmeshdistr+0x3a2>\n+\tldr.w\tr3, [pc, #2292]\t@ 3900 <__gridxc_mesh3d_MOD_setmeshdistr+0xb44>\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr1, [sp, #288]\t@ 0x120\n \tldr\tr2, [r2, r3]\n-\tstr\tr2, [sp, #144]\t@ 0x90\n-\tstr\tr1, [sp, #156]\t@ 0x9c\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tstr\tr1, [sp, #172]\t@ 0xac\n \tldr\tr3, [r2, #0]\n \tcmp\tr3, r1\n-\tbge.n\t32ae <__gridxc_mesh3d_MOD_setmeshdistr+0x2fa>\n-\tvmov.i64\tq6, #0xffffffff00000000\n-\tvmov.i64\td8, #0xffffffff00000000\n-\tvstr\td12, [sp, #376]\t@ 0x178\n-\tvstr\td13, [sp, #384]\t@ 0x180\n-\tvstr\td8, [sp, #392]\t@ 0x188\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tmov.w\tr8, #364\t@ 0x16c\n-\tldr.w\tr5, [pc, #1068]\t@ 3664 <__gridxc_mesh3d_MOD_setmeshdistr+0x6b0>\n-\tadd\tr5, pc\n-\tmul.w\tr8, r8, r3\n-\tadd.w\tr6, r8, #304\t@ 0x130\n-\tadd\tr6, r5\n-\tmov\tr0, r6\n+\tbge.n\t30d8 <__gridxc_mesh3d_MOD_setmeshdistr+0x31c>\n+\tmovs\tr4, #0\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tmov\tr5, r4\n+\tmov\tr7, r4\n+\tstr\tr4, [sp, #320]\t@ 0x140\n+\tstr\tr4, [sp, #328]\t@ 0x148\n+\tstr\tr4, [sp, #336]\t@ 0x150\n+\tstr\tr3, [sp, #324]\t@ 0x144\n+\tstr\tr3, [sp, #332]\t@ 0x14c\n+\tstr\tr3, [sp, #340]\t@ 0x154\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n+\tmov.w\tr3, #364\t@ 0x16c\n+\tldr.w\tr8, [pc, #2244]\t@ 3904 <__gridxc_mesh3d_MOD_setmeshdistr+0xb48>\n+\tadd\tr8, pc\n+\tmul.w\tsl, r3, sl\n+\tadd.w\tr9, sl, #304\t@ 0x130\n+\tadd\tr9, r8\n+\tadd\tr8, sl\n+\tmov\tr0, r9\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, r5, r8\n-\tmov\tr2, r0\n-\tmov\tr5, r0\n-\tvst1.32\t{d12-d13}, [r2]!\n-\tvst1.32\t{d8}, [r2]\n-\tldr.w\tr3, [r3, #304]\t@ 0x130\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tstrd\tr3, r5, [r0, #4]\n+\tmov\tsl, r0\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tstrd\tr3, r4, [r0, #12]\n+\tldr\tr3, [sp, #132]\t@ 0x84\n+\tstr\tr7, [r0, #0]\n+\tstr\tr3, [r0, #20]\n+\tldr.w\tr3, [r8, #304]\t@ 0x130\n \tcmp\tr3, r0\n-\tbne.n\t31a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x1f2>\n-\tldr\tr0, [sp, #200]\t@ 0xc8\n-\tmov\tr1, r7\n-\tbl\t260c <__gridxc_mesh3d_MOD_samemeshdistr>\n+\tbeq.n\t2fba <__gridxc_mesh3d_MOD_setmeshdistr+0x1fe>\n+\tmov\tr1, sl\n+\tmov\tr0, r9\n+\tbl\t0 <_gfortran_internal_unpack>\n+ R_ARM_THM_CALL\t_gfortran_internal_unpack\n+\tmov\tr0, sl\n+\tbl\t0 \n+ R_ARM_THM_CALL\tfree\n+\tldr\tr4, [sp, #160]\t@ 0xa0\n+\tldr\tr0, [sp, #208]\t@ 0xd0\n+\tmov\tr1, r4\n+\tbl\t2418 <__gridxc_mesh3d_MOD_samemeshdistr>\n \tcmp\tr0, #0\n-\tbne.n\t31c0 <__gridxc_mesh3d_MOD_setmeshdistr+0x20c>\n-\tldr\tr0, [sp, #200]\t@ 0xc8\n-\tbl\t2b24 <__gridxc_mesh3d_MOD_freemeshdistr>\n-\tmov\tr0, r7\n-\tbl\t2cf8 <__gridxc_mesh3d_MOD_reducedistr>\n-\tb.n\t31c8 <__gridxc_mesh3d_MOD_setmeshdistr+0x214>\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tldr\tr3, [pc, #964]\t@ (3648 <__gridxc_mesh3d_MOD_setmeshdistr+0x694>)\n+\tbne.n\t2fc8 <__gridxc_mesh3d_MOD_setmeshdistr+0x20c>\n+\tldr\tr0, [sp, #208]\t@ 0xd0\n+\tbl\t292c <__gridxc_mesh3d_MOD_freemeshdistr>\n+\tldr\tr0, [sp, #160]\t@ 0xa0\n+\tbl\t2b00 <__gridxc_mesh3d_MOD_reducedistr>\n+\tb.n\t2fd0 <__gridxc_mesh3d_MOD_setmeshdistr+0x214>\n+\tstr\tr5, [sp, #124]\t@ 0x7c\n+\tldr.w\tr3, [pc, #2120]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #50\t@ 0x32\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #992]\t@ (3668 <__gridxc_mesh3d_MOD_setmeshdistr+0x6b4>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [pc, #2144]\t@ 3908 <__gridxc_mesh3d_MOD_setmeshdistr+0xb4c>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t3100 <__gridxc_mesh3d_MOD_setmeshdistr+0x14c>\n-\tadd\tr3, sp, #332\t@ 0x14c\n-\tstr\tr5, [sp, #124]\t@ 0x7c\n+\tb.n\t2f04 <__gridxc_mesh3d_MOD_setmeshdistr+0x148>\n+\tstr\tr5, [sp, #288]\t@ 0x120\n+\tldr\tr5, [sp, #84]\t@ 0x54\n+\tldr\tr0, [r5, #0]\n+\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tcmp\tr6, #0\n+\tbne.w\t2ec8 <__gridxc_mesh3d_MOD_setmeshdistr+0x10c>\n+\tadd\tr3, sp, #276\t@ 0x114\n+\tstr\tr6, [sp, #124]\t@ 0x7c\n \tmov\tr2, r3\n-\tstr\tr3, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n \tmovs\tr3, #1\n-\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #72]\t@ 0x48\n \tstr\tr3, [r2, #0]\n-\tb.n\t3100 <__gridxc_mesh3d_MOD_setmeshdistr+0x14c>\n-\tstr\tr4, [sp, #344]\t@ 0x158\n-\tb.n\t30b0 <__gridxc_mesh3d_MOD_setmeshdistr+0xfc>\n-\tstr\tr3, [sp, #336]\t@ 0x150\n-\tb.n\t3084 <__gridxc_mesh3d_MOD_setmeshdistr+0xd0>\n-\tmovs\tr4, #0\n-\tb.n\t31c8 <__gridxc_mesh3d_MOD_setmeshdistr+0x214>\n-\tldr\tr2, [sp, #336]\t@ 0x150\n-\tstr\tr2, [sp, #96]\t@ 0x60\n+\tb.n\t2f04 <__gridxc_mesh3d_MOD_setmeshdistr+0x148>\n+\tstr\tr3, [sp, #280]\t@ 0x118\n+\tb.n\t2e8c <__gridxc_mesh3d_MOD_setmeshdistr+0xd0>\n+\tmovs\tr6, #0\n+\tb.n\t2fd0 <__gridxc_mesh3d_MOD_setmeshdistr+0x214>\n+\tldr\tr2, [sp, #280]\t@ 0x118\n+\tstr\tr2, [sp, #108]\t@ 0x6c\n \tadds\tr2, r1, r2\n \tcmp\tr3, r2\n-\tbge.n\t321c <__gridxc_mesh3d_MOD_setmeshdistr+0x268>\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tbge.n\t301c <__gridxc_mesh3d_MOD_setmeshdistr+0x260>\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n \tcmp\tr3, #1\n-\tble.n\t339e <__gridxc_mesh3d_MOD_setmeshdistr+0x3ea>\n-\tldr\tr0, [pc, #940]\t@ (366c <__gridxc_mesh3d_MOD_setmeshdistr+0x6b8>)\n-\tmovs\tr2, #0\n+\tble.n\t31c0 <__gridxc_mesh3d_MOD_setmeshdistr+0x404>\n+\tldr.w\tr2, [pc, #2080]\t@ 390c <__gridxc_mesh3d_MOD_setmeshdistr+0xb50>\n+\tmov\tr9, r3\n+\tmovs\tr7, #0\n+\tadd\tr3, sp, #428\t@ 0x1ac\n+\tadd\tr2, pc\n+\tstr\tr3, [sp, #56]\t@ 0x38\n \tmovs\tr5, #2\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tadd\tr0, pc\n-\tadd\tr2, sp, #488\t@ 0x1e8\n-\tadd.w\tr8, sp, #892\t@ 0x37c\n-\tstr\tr2, [sp, #52]\t@ 0x34\n-\tmov\tr2, r7\n-\tmov\tr7, r4\n-\tb.n\t32e0 <__gridxc_mesh3d_MOD_setmeshdistr+0x32c>\n-\tldr\tr1, [sp, #96]\t@ 0x60\n+\tadd\tr3, sp, #828\t@ 0x33c\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #68]\t@ 0x44\n+\tstr\tr6, [sp, #52]\t@ 0x34\n+\tb.n\t310c <__gridxc_mesh3d_MOD_setmeshdistr+0x350>\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n \tadds\tr5, #1\n-\tcmp\tr1, r5\n-\tblt.w\t4012 <__gridxc_mesh3d_MOD_setmeshdistr+0x105e>\n-\tsdiv\tr4, r3, r5\n-\tmls\tr6, r5, r4, r3\n-\tcmp\tr6, #0\n-\tbne.n\t32d6 <__gridxc_mesh3d_MOD_setmeshdistr+0x322>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr9, r3, #1\n-\tcmp.w\tr9, #100\t@ 0x64\n-\tble.n\t330c <__gridxc_mesh3d_MOD_setmeshdistr+0x358>\n-\tldr\tr3, [pc, #844]\t@ (3648 <__gridxc_mesh3d_MOD_setmeshdistr+0x694>)\n+\tcmp\tr3, r5\n+\tblt.w\t3d96 <__gridxc_mesh3d_MOD_setmeshdistr+0xfda>\n+\tmov\tr1, r5\n+\tmov\tr0, r9\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr4, r1\n+\tcmp\tr1, #0\n+\tbne.n\t3102 <__gridxc_mesh3d_MOD_setmeshdistr+0x346>\n+\tadds\tr6, r7, #1\n+\tcmp\tr6, #100\t@ 0x64\n+\tble.n\t3130 <__gridxc_mesh3d_MOD_setmeshdistr+0x374>\n+\tldr.w\tr3, [pc, #1988]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #50\t@ 0x32\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n \tldr\tr3, [r2, r3]\n-\tstr\tr0, [sp, #64]\t@ 0x40\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldrd\tr0, r2, [sp, #64]\t@ 0x40\n-\tldrd\tr3, r1, [sp, #48]\t@ 0x30\n-\tstr.w\tr5, [r1, r3, lsl #2]\n-\tlsls\tr1, r3, #2\n-\tmov\tr3, r4\n-\tadds\tr6, #1\n-\tsdiv\tr4, r4, r5\n-\tmls\tip, r5, r4, r3\n-\tcmp.w\tip, #0\n-\tbeq.n\t3316 <__gridxc_mesh3d_MOD_setmeshdistr+0x362>\n-\tcmp\tr3, #1\n-\tstr.w\tr6, [r8, r1]\n-\tbeq.w\t40b0 <__gridxc_mesh3d_MOD_setmeshdistr+0x10fc>\n-\tstr.w\tr9, [sp, #48]\t@ 0x30\n-\tb.n\t32d6 <__gridxc_mesh3d_MOD_setmeshdistr+0x322>\n-\tldr\tr3, [pc, #780]\t@ (3648 <__gridxc_mesh3d_MOD_setmeshdistr+0x694>)\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tstr.w\tr5, [r3, r7, lsl #2]\n+\tlsls\tr7, r7, #2\n+\tmov\tr0, r9\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, r5\n+\tadds\tr4, #1\n+\tmov\tr9, r0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.n\t3138 <__gridxc_mesh3d_MOD_setmeshdistr+0x37c>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tcmp.w\tr9, #1\n+\tstr\tr4, [r3, r7]\n+\tbeq.w\t3de2 <__gridxc_mesh3d_MOD_setmeshdistr+0x1026>\n+\tmov\tr7, r6\n+\tb.n\t3102 <__gridxc_mesh3d_MOD_setmeshdistr+0x346>\n+\tldr.w\tr3, [pc, #1928]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #44\t@ 0x2c\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #816]\t@ (3670 <__gridxc_mesh3d_MOD_setmeshdistr+0x6bc>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [pc, #1960]\t@ 3910 <__gridxc_mesh3d_MOD_setmeshdistr+0xb54>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t3208 <__gridxc_mesh3d_MOD_setmeshdistr+0x254>\n-\tstr\tr2, [sp, #336]\t@ 0x150\n-\tb.n\t3084 <__gridxc_mesh3d_MOD_setmeshdistr+0xd0>\n-\tstr\tr3, [sp, #344]\t@ 0x158\n-\tb.n\t30b0 <__gridxc_mesh3d_MOD_setmeshdistr+0xfc>\n+\tb.n\t3008 <__gridxc_mesh3d_MOD_setmeshdistr+0x24c>\n+\tmov\tr2, r3\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n \tmovs\tr3, #0\n-\tstr\tr3, [r7, #0]\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmovs\tr4, #0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tb.n\t3162 <__gridxc_mesh3d_MOD_setmeshdistr+0x1ae>\n-\tstr\tr0, [sp, #100]\t@ 0x64\n-\tb.n\t3162 <__gridxc_mesh3d_MOD_setmeshdistr+0x1ae>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tadd.w\tfp, sp, #336\t@ 0x150\n+\tstr\tr3, [r2, #0]\n+\tmovs\tr6, #0\n+\tmov.w\tsl, #4294967295\t@ 0xffffffff\n+\tb.n\t2f6a <__gridxc_mesh3d_MOD_setmeshdistr+0x1ae>\n+\tmov\tsl, r0\n+\tb.n\t2f6a <__gridxc_mesh3d_MOD_setmeshdistr+0x1ae>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd.w\tfp, sp, #280\t@ 0x118\n \tldr.w\tr9, [fp]\n \tcmp\tr3, #0\n-\tbeq.w\t3fb4 <__gridxc_mesh3d_MOD_setmeshdistr+0x1000>\n-\tldr\tr5, [r3, #0]\n-\tadd\tr6, sp, #440\t@ 0x1b8\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tstr\tr5, [r6, #0]\n+\tbeq.w\t3d34 <__gridxc_mesh3d_MOD_setmeshdistr+0xf78>\n+\tldr\tr4, [r3, #0]\n+\tadd\tr5, sp, #380\t@ 0x17c\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tstr\tr4, [r5, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t3f94 <__gridxc_mesh3d_MOD_setmeshdistr+0xfe0>\n+\tbeq.w\t3ce2 <__gridxc_mesh3d_MOD_setmeshdistr+0xf26>\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [r6, #4]\n-\tmul.w\tr2, r3, r5\n-\tcmp.w\tr8, #0\n-\tbeq.w\t3cf8 <__gridxc_mesh3d_MOD_setmeshdistr+0xd44>\n-\tldr.w\tr8, [r8]\n-\tstr.w\tr8, [r6, #8]\n-\tb.w\t3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xd4c>\n-\tmovs\tr3, #0\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tmovs\tr5, #0\n-\tcmp\tr5, #1\n-\tmov\tr0, r5\n+\tstr\tr3, [r5, #4]\n+\tmul.w\tr1, r3, r4\n+\tcmp\tr7, #0\n+\tbeq.w\t3a4c <__gridxc_mesh3d_MOD_setmeshdistr+0xc90>\n+\tldr.w\tr8, [r7]\n+\tstr.w\tr8, [r5, #8]\n+\tb.w\t3a5e <__gridxc_mesh3d_MOD_setmeshdistr+0xca2>\n+\tmovs\tr7, #0\n+\tmovs\tr4, #0\n+\tcmp\tr4, #1\n+\tmov\tr0, r4\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #80]\t@ 0x50\n+\tstr\tr0, [sp, #96]\t@ 0x60\n \tcmp\tr0, #0\n-\tbeq.w\t3cea <__gridxc_mesh3d_MOD_setmeshdistr+0xd36>\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tadd\tr2, sp, #376\t@ 0x178\n-\tldr\tr5, [sp, #152]\t@ 0x98\n-\tstr\tr2, [sp, #108]\t@ 0x6c\n-\tldr\tr1, [r3, #4]\n-\tsubs\tr5, #1\n-\tldr\tr0, [r3, #8]\n-\tmovs\tr3, #0\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tstr\tr1, [sp, #172]\t@ 0xac\n-\tsubs\tr1, #1\n-\tcmp\tr2, r3\n-\tstr\tr1, [sp, #176]\t@ 0xb0\n-\tstr\tr1, [sp, #388]\t@ 0x184\n-\tadd.w\tr1, r0, #4294967295\t@ 0xffffffff\n-\tstr\tr0, [sp, #180]\t@ 0xb4\n-\tstr\tr3, [sp, #376]\t@ 0x178\n-\tstr\tr3, [sp, #384]\t@ 0x180\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tstr\tr5, [sp, #168]\t@ 0xa8\n-\tstr\tr5, [sp, #380]\t@ 0x17c\n-\tstr\tr1, [sp, #184]\t@ 0xb8\n-\tstr\tr1, [sp, #396]\t@ 0x18c\n-\tble.w\t3ccc <__gridxc_mesh3d_MOD_setmeshdistr+0xd18>\n-\tvldr\td14, [pc, #528]\t@ 3600 <__gridxc_mesh3d_MOD_setmeshdistr+0x64c>\n-\tvldr\td15, [pc, #532]\t@ 3608 <__gridxc_mesh3d_MOD_setmeshdistr+0x654>\n-\tstr\tr7, [sp, #248]\t@ 0xf8\n-\tvldr\td12, [pc, #536]\t@ 3610 <__gridxc_mesh3d_MOD_setmeshdistr+0x65c>\n-\tvldr\td13, [pc, #540]\t@ 3618 <__gridxc_mesh3d_MOD_setmeshdistr+0x664>\n-\tadd\tr6, sp, #892\t@ 0x37c\n-\tvldr\td9, [pc, #540]\t@ 3620 <__gridxc_mesh3d_MOD_setmeshdistr+0x66c>\n-\tmov\tr8, r2\n-\tvldr\td8, [pc, #544]\t@ 3628 <__gridxc_mesh3d_MOD_setmeshdistr+0x674>\n-\tmov\tr7, fp\n-\tadd.w\tr8, r8, #4294967295\t@ 0xffffffff\n-\tldr.w\tr3, [r6, r8, lsl #2]\n-\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tbeq.w\t3a3e <__gridxc_mesh3d_MOD_setmeshdistr+0xc82>\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tmovs\tr4, #0\n+\tldr\tr0, [sp, #168]\t@ 0xa8\n+\tadd\tr3, sp, #320\t@ 0x140\n+\tcmp\tr7, r4\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [r2, #4]\n+\tadd.w\tr0, r0, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [r2, #8]\n+\tstr\tr1, [sp, #188]\t@ 0xbc\n+\tadd.w\tr1, r1, #4294967295\t@ 0xffffffff\n+\tstr\tr2, [sp, #192]\t@ 0xc0\n+\tadd.w\tr2, r2, #4294967295\t@ 0xffffffff\n+\tstr\tr4, [sp, #320]\t@ 0x140\n+\tstr\tr4, [sp, #328]\t@ 0x148\n+\tstr\tr4, [sp, #336]\t@ 0x150\n+\tstr\tr0, [sp, #140]\t@ 0x8c\n+\tstr\tr0, [sp, #324]\t@ 0x144\n+\tstr\tr1, [sp, #128]\t@ 0x80\n+\tstr\tr1, [sp, #332]\t@ 0x14c\n+\tstr\tr2, [sp, #132]\t@ 0x84\n+\tstr\tr2, [sp, #340]\t@ 0x154\n+\tble.w\t3a38 <__gridxc_mesh3d_MOD_setmeshdistr+0xc7c>\n+\tldr.w\tr2, [pc, #1796]\t@ 3914 <__gridxc_mesh3d_MOD_setmeshdistr+0xb58>\n+\tadd.w\tr9, sp, #828\t@ 0x33c\n+\tldr.w\tr3, [pc, #1792]\t@ 3918 <__gridxc_mesh3d_MOD_setmeshdistr+0xb5c>\n+\tadd\tr2, pc\n+\tstrd\tr6, sl, [sp, #256]\t@ 0x100\n+\tadd\tr3, pc\n+\tmov\tsl, fp\n+\tmov\tfp, r8\n+\tadds\tr3, #4\n+\tstr\tr2, [sp, #244]\t@ 0xf4\n+\tstr\tr3, [sp, #252]\t@ 0xfc\n+\tadds\tr3, r2, #4\n+\tstr\tr3, [sp, #248]\t@ 0xf8\n+\tsubs\tr7, #1\n+\tldr.w\tr3, [r9, r7, lsl #2]\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n \tcmp\tr3, #0\n-\tble.w\t3a28 <__gridxc_mesh3d_MOD_setmeshdistr+0xa74>\n-\tadd\tr3, sp, #488\t@ 0x1e8\n-\tmovs\tr2, #48\t@ 0x30\n-\tmov\tfp, sl\n-\tvldr\td10, [pc, #524]\t@ 3630 <__gridxc_mesh3d_MOD_setmeshdistr+0x67c>\n-\tmov\tsl, r7\n-\tstrd\tr8, r4, [sp, #252]\t@ 0xfc\n-\tldr.w\tr1, [r3, r8, lsl #2]\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tstr\tr1, [sp, #104]\t@ 0x68\n-\tadds\tr0, r3, r2\n-\tldr\tr3, [pc, #572]\t@ (3674 <__gridxc_mesh3d_MOD_setmeshdistr+0x6c0>)\n-\tstr\tr0, [sp, #240]\t@ 0xf0\n+\tble.w\t373c <__gridxc_mesh3d_MOD_setmeshdistr+0x980>\n+\tadd\tr3, sp, #428\t@ 0x1ac\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tstrd\tr7, r9, [sp, #264]\t@ 0x108\n+\tldr.w\tr2, [r3, r7, lsl #2]\n+\tmovs\tr3, #24\n+\tadd\tr1, r3\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tstr\tr1, [sp, #204]\t@ 0xcc\n+\tmla\tr3, r3, r2, r1\n+\tstr\tr3, [sp, #180]\t@ 0xb4\n+\tldr.w\tr3, [pc, #1728]\t@ 391c <__gridxc_mesh3d_MOD_setmeshdistr+0xb60>\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #244]\t@ 0xf4\n-\tsubs\tr3, r1, #1\n-\tstr\tr3, [sp, #188]\t@ 0xbc\n-\tand.w\tr3, r1, #1\n \tstr\tr3, [sp, #236]\t@ 0xec\n-\tlsrs\tr3, r1, #1\n-\tstr\tr6, [sp, #260]\t@ 0x104\n-\tmla\tr3, r2, r3, r0\n-\tstr\tr3, [sp, #208]\t@ 0xd0\n-\torr.w\tr3, r1, #1\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n+\tldr.w\tr3, [pc, #1724]\t@ 3920 <__gridxc_mesh3d_MOD_setmeshdistr+0xb64>\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #240]\t@ 0xf0\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #120]\t@ 0x78\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tldr\tr2, [sp, #156]\t@ 0x9c\n-\tldr\tr1, [sp, #96]\t@ 0x60\n-\tldr\tr3, [r3, #0]\n-\tldr\tr0, [sp, #104]\t@ 0x68\n-\tsubs\tr3, r3, r2\n-\tmov\tr2, r1\n-\tcmp\tr0, #0\n-\tsdiv\tr4, r1, r0\n-\tsdiv\tr1, r3, r1\n-\tstr\tr4, [sp, #96]\t@ 0x60\n-\tmls\tr3, r2, r1, r3\n-\tsdiv\tr3, r3, r4\n-\tstr\tr3, [sp, #132]\t@ 0x84\n-\tble.w\t39ee <__gridxc_mesh3d_MOD_setmeshdistr+0xa3a>\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tldrd\tr4, r9, [r3]\n+\tldr\tr5, [sp, #112]\t@ 0x70\n+\tldr\tr0, [sp, #108]\t@ 0x6c\n+\tmov\tr1, r5\n+\tmov\tr4, r0\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #164]\t@ 0xa4\n+\tmov\tr1, r4\n+\tstr\tr0, [sp, #108]\t@ 0x6c\n+\tmov\tr4, r0\n+\tldr\tr0, [r3, #0]\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tsubs\tr0, r0, r3\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tmov\tr0, r1\n+\tmov\tr1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr5, #0\n+\tstr\tr0, [sp, #148]\t@ 0x94\n+\tble.w\t36fe <__gridxc_mesh3d_MOD_setmeshdistr+0x942>\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr2, [sp, #180]\t@ 0xb4\n \tldrd\tr5, r8, [r3, #8]\n-\tldrd\tr6, r7, [r3, #16]\n-\tldr\tr3, [sp, #188]\t@ 0xbc\n-\tcmp\tr3, #1\n-\tbls.w\t3bba <__gridxc_mesh3d_MOD_setmeshdistr+0xc06>\n-\tstrd\tr5, r8, [sp, #312]\t@ 0x138\n-\tstrd\tr6, r7, [sp, #320]\t@ 0x140\n-\tstrd\tr6, r7, [sp, #296]\t@ 0x128\n-\tstrd\tr4, r9, [sp, #304]\t@ 0x130\n-\tstrd\tr4, r9, [sp, #280]\t@ 0x118\n-\tstrd\tr5, r8, [sp, #288]\t@ 0x120\n-\tvldr\td20, [sp, #312]\t@ 0x138\n-\tvldr\td21, [sp, #320]\t@ 0x140\n-\tvldr\td18, [sp, #296]\t@ 0x128\n-\tvldr\td19, [sp, #304]\t@ 0x130\n-\tvldr\td16, [sp, #280]\t@ 0x118\n-\tvldr\td17, [sp, #288]\t@ 0x120\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n-\tldr\tr2, [sp, #208]\t@ 0xd0\n-\tvstr\td16, [r3, #-48]\t@ 0xffffffd0\n-\tvstr\td17, [r3, #-40]\t@ 0xffffffd8\n-\tadds\tr3, #48\t@ 0x30\n-\tvstr\td18, [r3, #-80]\t@ 0xffffffb0\n-\tvstr\td19, [r3, #-72]\t@ 0xffffffb8\n-\tvstr\td20, [r3, #-64]\t@ 0xffffffc0\n-\tvstr\td21, [r3, #-56]\t@ 0xffffffc8\n+\tldrd\tr6, r9, [r3, #16]\n+\tmov\tr1, r8\n+\tldrd\tr7, r4, [r3]\n+\tmov\tr0, r9\n+\tldr\tr3, [sp, #204]\t@ 0xcc\n+\tstrd\tr7, r4, [r3, #-24]\n+\tstrd\tr5, r1, [r3, #-16]\n+\tstrd\tr6, r0, [r3, #-8]\n+\tadds\tr3, #24\n \tcmp\tr2, r3\n-\tbne.n\t34ce <__gridxc_mesh3d_MOD_setmeshdistr+0x51a>\n-\tldr\tr1, [sp, #236]\t@ 0xec\n-\tcbz\tr1, 3534 <__gridxc_mesh3d_MOD_setmeshdistr+0x580>\n-\tldr\tr3, [sp, #228]\t@ 0xe4\n-\tmovs\tr2, #6\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tcmp\tr1, #1\n-\tmul.w\tr3, r2, r3\n-\tsub.w\tr2, r3, #6\n-\tstr.w\tr4, [r0, r2, lsl #2]\n-\tadd.w\tr2, r0, r3, lsl #2\n-\tstrd\tr9, r5, [r2, #-20]\n-\tstrd\tr8, r6, [r2, #-12]\n-\tstr.w\tr7, [r2, #-4]\n-\tbeq.n\t352c <__gridxc_mesh3d_MOD_setmeshdistr+0x578>\n-\tstr.w\tr4, [r0, r3, lsl #2]\n-\tadds\tr3, #6\n-\tadd.w\tr3, r0, r3, lsl #2\n-\tstrd\tr9, r5, [r3, #-20]\n-\tstrd\tr8, r6, [r3, #-12]\n-\tstr.w\tr7, [r3, #-4]\n-\tldr\tr3, [sp, #104]\t@ 0x68\n+\tbne.n\t32b0 <__gridxc_mesh3d_MOD_setmeshdistr+0x4f4>\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tmov\tr8, r1\n+\tmov\tr9, r0\n \tcmp\tr3, #1\n-\tbeq.w\t39ee <__gridxc_mesh3d_MOD_setmeshdistr+0xa3a>\n+\tbeq.w\t36fe <__gridxc_mesh3d_MOD_setmeshdistr+0x942>\n \tldr\tr3, [sp, #124]\t@ 0x7c\n \tcmp\tr3, #0\n-\tbne.w\t3ac2 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0e>\n-\tldr\tr1, [sp, #172]\t@ 0xac\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tsdiv\tr3, r1, r2\n-\tmls\tr3, r2, r3, r1\n-\tcmp\tr3, #0\n-\tbne.w\t3ac2 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0e>\n-\tldr\tr1, [sp, #180]\t@ 0xb4\n-\tsdiv\tr3, r1, r2\n-\tmls\tr3, r2, r3, r1\n-\tcmp\tr3, #0\n-\tbne.w\t3ac2 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0e>\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tsdiv\tr3, r4, r2\n-\tmls\tr3, r2, r3, r4\n-\tcmp\tr3, #0\n-\tbne.w\t3ae2 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2e>\n-\tsdiv\tr3, r5, r2\n-\tmls\tr3, r2, r3, r5\n-\tcmp\tr3, #0\n-\tbne.w\t3ae2 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2e>\n-\tmov\tr3, r2\n-\tsdiv\tr2, r6, r2\n-\tmls\tr2, r3, r2, r6\n-\tsubs\tr2, #0\n-\tit\tne\n-\tmovne\tr2, #1\n-\tldr\tr0, [sp, #112]\t@ 0x70\n-\tadd.w\tr3, r9, #1\n-\tsdiv\tr1, r3, r0\n-\tmls\tr3, r0, r1, r3\n-\tcmp\tr3, #0\n-\tbne.w\t3b30 <__gridxc_mesh3d_MOD_setmeshdistr+0xb7c>\n-\tadd.w\tr3, r8, #1\n-\tsdiv\tr1, r3, r0\n-\tmls\tr3, r0, r1, r3\n-\tcmp\tr3, #0\n-\tbne.w\t3b30 <__gridxc_mesh3d_MOD_setmeshdistr+0xb7c>\n-\tadds\tr3, r7, #1\n-\tsdiv\tr1, r3, r0\n-\tmls\tr3, r0, r1, r3\n-\tsubs\tr3, #0\n+\tbne.w\t3786 <__gridxc_mesh3d_MOD_setmeshdistr+0x9ca>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #188]\t@ 0xbc\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t3786 <__gridxc_mesh3d_MOD_setmeshdistr+0x9ca>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #192]\t@ 0xc0\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t3786 <__gridxc_mesh3d_MOD_setmeshdistr+0x9ca>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t37a4 <__gridxc_mesh3d_MOD_setmeshdistr+0x9e8>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmov\tr0, r5\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t37a4 <__gridxc_mesh3d_MOD_setmeshdistr+0x9e8>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmov\tr0, r6\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tadds\tr0, r4, #1\n+\tsubs\tr3, r1, #0\n+\tldr\tr1, [sp, #72]\t@ 0x48\n \tit\tne\n \tmovne\tr3, #1\n-\torrs\tr3, r2\n-\tbne.w\t3b30 <__gridxc_mesh3d_MOD_setmeshdistr+0xb7c>\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t37b6 <__gridxc_mesh3d_MOD_setmeshdistr+0x9fa>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tadd.w\tr0, r8, #1\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbne.w\t37b6 <__gridxc_mesh3d_MOD_setmeshdistr+0x9fa>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tadd.w\tr0, r9, #1\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr1, #0\n+\tit\tne\n+\torrne.w\tr3, r3, #1\n+\tcmp\tr3, #0\n+\tbne.w\t37b6 <__gridxc_mesh3d_MOD_setmeshdistr+0x9fa>\n+\tldr\tr3, [sp, #104]\t@ 0x68\n \tcmp\tr3, #0\n-\tblt.n\t36a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x6f2>\n+\tblt.n\t33ba <__gridxc_mesh3d_MOD_setmeshdistr+0x5fe>\n \tldr\tr3, [sp, #116]\t@ 0x74\n \tmovs\tr2, #0\n-\tldr\tr0, [sp, #88]\t@ 0x58\n \tmov\tip, r2\n-\tmov\tr1, r4\n \tcmp\tr3, #1\n-\tbne.w\t3b52 <__gridxc_mesh3d_MOD_setmeshdistr+0xb9e>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\titt\teq\n+\tmoveq\tr1, r7\n+\tldreq\tr0, [sp, #100]\t@ 0x64\n+\tbne.w\t3882 <__gridxc_mesh3d_MOD_setmeshdistr+0xac6>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tcmp\tr3, #0\n-\tblt.w\t3a56 <__gridxc_mesh3d_MOD_setmeshdistr+0xaa2>\n-\tmov\tlr, r2\n-\tmovs\tr4, #0\n+\tblt.w\t3772 <__gridxc_mesh3d_MOD_setmeshdistr+0x9b6>\n+\tmov\tr7, r2\n+\tmov.w\tlr, #0\n \tcmp\tr0, #0\n-\tblt.w\t3c5e <__gridxc_mesh3d_MOD_setmeshdistr+0xcaa>\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tadd.w\tr2, fp, lr, lsl #3\n+\tblt.w\t39ce <__gridxc_mesh3d_MOD_setmeshdistr+0xc12>\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tadd.w\tr2, sl, r7, lsl #3\n \tmovs\tr3, #0\n-\tb.n\t3680 <__gridxc_mesh3d_MOD_setmeshdistr+0x6cc>\n-\tnop\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000003\n-\t.word\t0x00000000\n-\t.word\t0x00000006\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000003\n-\t.word\t0x00000658\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000063c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t...\n- R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000005ce\n- R_ARM_REL32\t.LC30\n-\t.word\t0x000005a2\n- R_ARM_REL32\t.LC31\n-\t.word\t0x0000051e\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000004e2\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x00000488\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n-\t.word\t0x00000426\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000003da\n- R_ARM_REL32\t.LC32\n-\t.word\t0x000003a2\n- R_ARM_REL32\t.LC34\n-\t.word\t0x0000032a\n- R_ARM_REL32\t.LC33\n-\t.word\t0x00000236\n- R_ARM_REL32\t.rodata\n+\tb.n\t3394 <__gridxc_mesh3d_MOD_setmeshdistr+0x5d8>\n \tadds\tr3, #1\n \tcmp\tr0, r3\n-\tblt.w\t3a48 <__gridxc_mesh3d_MOD_setmeshdistr+0xa94>\n-\tvldmia\tr2!, {d16}\n-\tvcmpe.f64\td16, #0.0\n+\tblt.w\t3762 <__gridxc_mesh3d_MOD_setmeshdistr+0x9a6>\n+\tvldmia\tr2!, {d7}\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t3678 <__gridxc_mesh3d_MOD_setmeshdistr+0x6c4>\n-\tmov\tr4, r1\n-\tstr\tr0, [sp, #88]\t@ 0x58\n-\tldr.w\tr3, [pc, #1332]\t@ 3bc8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc14>\n+\tbpl.n\t338c <__gridxc_mesh3d_MOD_setmeshdistr+0x5d0>\n+\tmov\tr7, r1\n+\tstr\tr0, [sp, #100]\t@ 0x64\n+\tldr.w\tr3, [pc, #1344]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #43\t@ 0x2b\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr.w\tr0, [pc, #1328]\t@ 3bcc <__gridxc_mesh3d_MOD_setmeshdistr+0xc18>\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [pc, #1396]\t@ 3924 <__gridxc_mesh3d_MOD_setmeshdistr+0xb68>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tsub.w\tr4, r9, r4\n-\tsub.w\tr5, r8, r5\n+\tsubs\tr4, r4, r7\n+\tsub.w\tr8, r8, r5\n \tadds\tr2, r4, #1\n-\tadds\tr0, r5, #1\n+\tadd.w\tr0, r8, #1\n \tcmp\tr2, r0\n-\tsub.w\tr6, r7, r6\n-\tadd.w\tr3, r6, #1\n-\tstr\tr2, [sp, #216]\t@ 0xd8\n-\tstrd\tr2, r0, [sp, #364]\t@ 0x16c\n+\tsub.w\tr9, r9, r6\n+\tadd.w\tr3, r9, #1\n+\tstr\tr2, [sp, #220]\t@ 0xdc\n+\tstrd\tr2, r0, [sp, #308]\t@ 0x134\n \tit\tlt\n \tmovlt\tr2, r0\n \tcmp\tr3, r2\n-\tstr\tr3, [sp, #224]\t@ 0xe0\n-\tstr\tr3, [sp, #372]\t@ 0x174\n+\tstr\tr3, [sp, #228]\t@ 0xe4\n+\tstr\tr3, [sp, #316]\t@ 0x13c\n \tit\tlt\n \tmovlt\tr3, r2\n-\tadd\tr1, sp, #364\t@ 0x16c\n+\tadd\tr1, sp, #308\t@ 0x134\n \tcmp\tr3, #0\n \tbic.w\tr4, r3, r3, asr #31\n-\tstr\tr0, [sp, #220]\t@ 0xdc\n+\tstr\tr0, [sp, #224]\t@ 0xe0\n \tstr\tr1, [sp, #232]\t@ 0xe8\n-\tstr\tr2, [sp, #212]\t@ 0xd4\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tble.w\t3cb8 <__gridxc_mesh3d_MOD_setmeshdistr+0xd04>\n-\tmvn.w\tr2, #2147483648\t@ 0x80000000\n-\tadd.w\tr3, r4, r4, lsl #1\n-\tudiv\tr2, r2, r4\n-\tcmp\tr2, #2\n-\tble.w\t3cae <__gridxc_mesh3d_MOD_setmeshdistr+0xcfa>\n-\tcmp.w\tr3, #536870912\t@ 0x20000000\n-\tbge.w\t3cae <__gridxc_mesh3d_MOD_setmeshdistr+0xcfa>\n-\tlsls\tr5, r3, #3\n+\tstr\tr2, [sp, #216]\t@ 0xd8\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tble.w\t3a0e <__gridxc_mesh3d_MOD_setmeshdistr+0xc52>\n+\tmov\tr1, r4\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tadd.w\tr5, r4, r4, lsl #1\n+\tcmp\tr0, #2\n+\tble.w\t3a06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc4a>\n+\tcmp.w\tr5, #536870912\t@ 0x20000000\n+\tbge.w\t3a06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc4a>\n+\tlsls\tr5, r5, #3\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #68]\t@ 0x44\n+\tstr\tr0, [sp, #80]\t@ 0x50\n \tcmp\tr0, #0\n-\tbeq.w\t3c94 <__gridxc_mesh3d_MOD_setmeshdistr+0xce0>\n-\tldr\tr5, [sp, #128]\t@ 0x80\n+\tbeq.w\t39f8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc3c>\n+\tldr\tr5, [sp, #136]\t@ 0x88\n \tmovs\tr2, #0\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tsubs\tr3, r5, #1\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tadds\tr2, #1\n \tstrd\tr0, r1, [r3]\n \tstrd\tr0, r1, [r3, #8]\n \tcmp\tr5, r2\n \tstrd\tr0, r1, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t371c <__gridxc_mesh3d_MOD_setmeshdistr+0x768>\n-\tldr\tr3, [sp, #196]\t@ 0xc4\n+\tbne.n\t3432 <__gridxc_mesh3d_MOD_setmeshdistr+0x676>\n+\tldr\tr3, [sp, #200]\t@ 0xc8\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tbne.w\t3ae6 <__gridxc_mesh3d_MOD_setmeshdistr+0xb32>\n-\tadd\tr3, sp, #400\t@ 0x190\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tldr\tr3, [sp, #152]\t@ 0x98\n-\tldr\tr5, [sp, #168]\t@ 0xa8\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #184]\t@ 0xb8\n-\tldr\tr7, [sp, #176]\t@ 0xb0\n+\tbne.w\t3828 <__gridxc_mesh3d_MOD_setmeshdistr+0xa6c>\n+\tadd\tr3, sp, #344\t@ 0x158\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tldr\tr5, [sp, #140]\t@ 0x8c\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr2, [sp, #132]\t@ 0x84\n+\tldr\tr7, [sp, #128]\t@ 0x80\n \tcmp\tr3, r5\n-\tldr\tr6, [sp, #180]\t@ 0xb4\n-\tldr.w\tr9, [sp, #172]\t@ 0xac\n-\tstr\tr1, [sp, #400]\t@ 0x190\n-\tstr\tr1, [sp, #408]\t@ 0x198\n-\tstr\tr1, [sp, #416]\t@ 0x1a0\n-\tstr\tr5, [sp, #404]\t@ 0x194\n-\tstr\tr7, [sp, #412]\t@ 0x19c\n-\tstr\tr2, [sp, #420]\t@ 0x1a4\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tbne.w\t3b1e <__gridxc_mesh3d_MOD_setmeshdistr+0xb6a>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tcmp\tr3, r7\n-\tbne.w\t3b1e <__gridxc_mesh3d_MOD_setmeshdistr+0xb6a>\n+\tldr\tr6, [sp, #192]\t@ 0xc0\n+\tldr.w\tr9, [sp, #188]\t@ 0xbc\n+\tstr\tr1, [sp, #344]\t@ 0x158\n+\tstr\tr1, [sp, #352]\t@ 0x160\n+\tstr\tr1, [sp, #360]\t@ 0x168\n+\tstr\tr5, [sp, #348]\t@ 0x15c\n+\tstr\tr7, [sp, #356]\t@ 0x164\n+\tstr\tr2, [sp, #364]\t@ 0x16c\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tbne.w\t3860 <__gridxc_mesh3d_MOD_setmeshdistr+0xaa4>\n \tldr\tr3, [sp, #92]\t@ 0x5c\n-\tldr\tr2, [sp, #64]\t@ 0x40\n+\tcmp\tr3, r7\n+\tbne.w\t3860 <__gridxc_mesh3d_MOD_setmeshdistr+0xaa4>\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #68]\t@ 0x44\n \tcmp\tr3, r2\n-\tbne.w\t3b1e <__gridxc_mesh3d_MOD_setmeshdistr+0xb6a>\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tbne.w\t3860 <__gridxc_mesh3d_MOD_setmeshdistr+0xaa4>\n+\tldr\tr3, [sp, #136]\t@ 0x88\n \tcmp\tr4, r3\n-\tbge.n\t3792 <__gridxc_mesh3d_MOD_setmeshdistr+0x7de>\n-\tldr.w\tr3, [pc, #1096]\t@ 3bc8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc14>\n+\tbge.n\t34a8 <__gridxc_mesh3d_MOD_setmeshdistr+0x6ec>\n+\tldr.w\tr3, [pc, #1104]\t@ 38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>\n \tmovs\tr1, #61\t@ 0x3d\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr.w\tr0, [pc, #1096]\t@ 3bd0 <__gridxc_mesh3d_MOD_setmeshdistr+0xc1c>\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [pc, #1160]\t@ 3928 <__gridxc_mesh3d_MOD_setmeshdistr+0xb6c>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tadd\tr2, sp, #352\t@ 0x160\n-\tldr\tr1, [sp, #244]\t@ 0xf4\n-\tldr.w\tr4, [pc, #1084]\t@ 3bd4 <__gridxc_mesh3d_MOD_setmeshdistr+0xc20>\n-\tadd\tr3, sp, #356\t@ 0x164\n-\tstr\tr1, [sp, #4]\n+\tadd\tr2, sp, #296\t@ 0x128\n+\tldr\tr1, [sp, #236]\t@ 0xec\n+\tldr\tr3, [sp, #240]\t@ 0xf0\n \tmov.w\tr8, #0\n+\tldr\tr0, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #20]\n+\tadd\tr3, sp, #300\t@ 0x12c\n+\tstr\tr1, [sp, #4]\n+\tstr\tr0, [sp, #304]\t@ 0x130\n \tstr\tr5, [r2, #0]\n-\tadd\tr4, pc\n+\tldr\tr0, [sp, #248]\t@ 0xf8\n \tstr\tr3, [sp, #0]\n-\tadd\tr3, sp, #360\t@ 0x168\n+\tadd\tr3, sp, #304\t@ 0x130\n+\tstr.w\tr8, [sp, #40]\t@ 0x28\n \tstr\tr3, [sp, #8]\n-\tldr.w\tr3, [pc, #1064]\t@ 3bd8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc24>\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tadd\tr3, pc\n-\tstr\tr0, [sp, #360]\t@ 0x168\n-\tstr\tr3, [sp, #20]\n-\tadds\tr0, r4, #4\n \tadds\tr3, r1, #4\n-\tstr.w\tr8, [sp, #40]\t@ 0x28\n+\tstrd\tr8, r8, [sp, #28]\n \tstrd\tr3, r3, [sp, #12]\n \tmovs\tr3, #32\n-\tstrd\tr8, r8, [sp, #28]\n+\tstr.w\tr8, [sp, #24]\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tmov\tr3, r1\n-\tstr.w\tr8, [sp, #24]\n-\tstr\tr7, [sp, #356]\t@ 0x164\n+\tstr\tr7, [sp, #300]\t@ 0x12c\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tcmp\tr6, r8\n-\tble.n\t3868 <__gridxc_mesh3d_MOD_setmeshdistr+0x8b4>\n+\tble.n\t3576 <__gridxc_mesh3d_MOD_setmeshdistr+0x7ba>\n \tcmp.w\tr9, #0\n-\tble.n\t3868 <__gridxc_mesh3d_MOD_setmeshdistr+0x8b4>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tble.n\t3576 <__gridxc_mesh3d_MOD_setmeshdistr+0x7ba>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tcmp\tr3, #0\n-\tble.n\t3868 <__gridxc_mesh3d_MOD_setmeshdistr+0x8b4>\n-\tldr\tr2, [r4, #64]\t@ 0x40\n-\tldr\tr3, [r4, #8]\n-\tldr\tr1, [r4, #4]\n+\tble.n\t3576 <__gridxc_mesh3d_MOD_setmeshdistr+0x7ba>\n+\tldr\tr0, [sp, #244]\t@ 0xf4\n+\tldr\tr2, [r0, #64]\t@ 0x40\n+\tldr\tr3, [r0, #8]\n+\tldr\tr1, [r0, #4]\n+\tldr\tr4, [r0, #24]\n \tadd\tr3, r2\n-\tldr.w\tip, [r4, #28]\n-\tldr\tr6, [r4, #52]\t@ 0x34\n-\tldr\tr2, [r4, #40]\t@ 0x28\n-\tldr\tr4, [r4, #24]\n+\tldr.w\tip, [r0, #28]\n+\tldr\tr6, [r0, #52]\t@ 0x34\n+\tldr\tr2, [r0, #40]\t@ 0x28\n \tldr\tr0, [sp, #116]\t@ 0x74\n-\tcmp\tr0, #1\n \tmla\tr1, r4, r3, r1\n-\tbne.w\t3bf0 <__gridxc_mesh3d_MOD_setmeshdistr+0xc3c>\n+\tcmp\tr0, #1\n+\tbne.w\t3960 <__gridxc_mesh3d_MOD_setmeshdistr+0xba4>\n \tmul.w\tr3, r4, r6\n \tmov\tr0, r8\n \tmul.w\tr8, r4, r2\n \tmov\tr9, r0\n \tmul.w\tr4, r4, ip\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #88]\t@ 0x58\n \tmov\tip, r0\n \tmov\tr6, r1\n \tmov.w\tlr, #0\n-\tstrd\tr0, r1, [sp, #48]\t@ 0x30\n-\tadd.w\tr0, fp, ip, lsl #3\n+\tstrd\tr0, r1, [sp, #52]\t@ 0x34\n+\tadd.w\tr0, sl, ip, lsl #3\n \tmov\tr1, r6\n \tmovs\tr2, #0\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tcmp\tr5, r2\n \tadd.w\tr2, r2, #1\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd\tr1, r4\n-\tbgt.n\t382c <__gridxc_mesh3d_MOD_setmeshdistr+0x878>\n+\tbgt.n\t353a <__gridxc_mesh3d_MOD_setmeshdistr+0x77e>\n \tadd\tr6, r8\n-\tadd\tip, sl\n+\tadd\tip, fp\n \tadd.w\tr3, lr, #1\n \tcmp\tlr, r7\n-\tbge.n\t384e <__gridxc_mesh3d_MOD_setmeshdistr+0x89a>\n+\tbge.n\t355c <__gridxc_mesh3d_MOD_setmeshdistr+0x7a0>\n \tmov\tlr, r3\n-\tb.n\t3824 <__gridxc_mesh3d_MOD_setmeshdistr+0x870>\n-\tldrd\tr0, r1, [sp, #48]\t@ 0x30\n+\tb.n\t3532 <__gridxc_mesh3d_MOD_setmeshdistr+0x776>\n+\tldrd\tr0, r1, [sp, #52]\t@ 0x34\n \tadd.w\tr2, r9, #1\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #88]\t@ 0x58\n \tadd\tr1, r3\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tadd\tr0, r3\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tcmp\tr9, r3\n-\tbge.n\t3868 <__gridxc_mesh3d_MOD_setmeshdistr+0x8b4>\n+\tbge.n\t3576 <__gridxc_mesh3d_MOD_setmeshdistr+0x7ba>\n \tmov\tr9, r2\n-\tb.n\t3818 <__gridxc_mesh3d_MOD_setmeshdistr+0x864>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr6, [pc, #876]\t@ (3bdc <__gridxc_mesh3d_MOD_setmeshdistr+0xc28>)\n-\tadd\tr4, sp, #440\t@ 0x1b8\n-\tadd.w\tr8, sp, #460\t@ 0x1cc\n-\tadd.w\tr9, sp, #476\t@ 0x1dc\n-\tadd\tr6, pc\n-\tadds\tr3, r6, #4\n-\tldr\tr6, [sp, #136]\t@ 0x88\n-\tvstr\td16, [sp, #452]\t@ 0x1c4\n-\tmovs\tr5, #0\n-\tstr\tr4, [sp, #4]\n-\tmovw\tip, #770\t@ 0x302\n-\tstr\tr5, [sp, #0]\n+\tb.n\t3526 <__gridxc_mesh3d_MOD_setmeshdistr+0x76a>\n+\tadd\tr5, sp, #380\t@ 0x17c\n+\tldr.w\tr8, [sp, #252]\t@ 0xfc\n+\tstr\tr5, [sp, #4]\n+\tmovs\tr4, #0\n+\tldr\tr6, [sp, #80]\t@ 0x50\n \tmovs\tr7, #8\n-\tstrh.w\tip, [r4, #16]\n-\tmov\tr2, r3\n-\tstr\tr7, [r4, #8]\n-\tmov.w\tr7, #4294967295\t@ 0xffffffff\n-\tvst1.32\t{d14-d15}, [r8]\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tstr\tr6, [r4, #44]\t@ 0x2c\n-\tvst1.32\t{d9}, [r9]\n-\tstr\tr7, [r4, #4]\n-\tldr\tr7, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #140]\t@ 0x8c\n-\tldr\tr0, [sp, #72]\t@ 0x48\n-\tstr\tr7, [r4, #0]\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tbl\t1058 <__gridxc_mesh3d_MOD_reducedata.isra.0>\n-\tldr\tr1, [pc, #808]\t@ (3be0 <__gridxc_mesh3d_MOD_setmeshdistr+0xc2c>)\n+\tstr\tr4, [sp, #0]\n+\tmov\tr2, r8\n+\tstr\tr7, [r5, #20]\n+\tstrd\tr4, r4, [sp, #392]\t@ 0x188\n+\tstr\tr7, [r5, #8]\n+\tldr\tr7, [sp, #152]\t@ 0x98\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #144]\t@ 0x90\n+\tldr\tr0, [sp, #84]\t@ 0x54\n+\tstr\tr6, [r5, #0]\n+\tmovs\tr6, #1\n+\tstr\tr4, [r5, #40]\t@ 0x28\n+\tstrd\tr6, r6, [r5, #24]\n+\tmovs\tr6, #3\n+\tstr\tr7, [r5, #44]\t@ 0x2c\n+\tstrd\tr6, r6, [r5, #32]\n+\tmov.w\tr6, #4294967295\t@ 0xffffffff\n+\tstr\tr6, [r5, #4]\n+\tmovw\tr6, #770\t@ 0x302\n+\tstrh\tr6, [r5, #16]\n+\tbl\tdec <__gridxc_mesh3d_MOD_reducedata.isra.0>\n+\tldr\tr1, [pc, #880]\t@ (392c <__gridxc_mesh3d_MOD_setmeshdistr+0xb70>)\n \tmovs\tr3, #32\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tmov\tr2, r5\n+\tmov\tr2, r4\n \tadd\tr1, pc\n-\tstr\tr5, [sp, #0]\n+\tmov\tr0, r8\n+\tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_dealloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_dealloc_d4\n-\tcmp\tr6, r5\n-\tblt.w\t3a6a <__gridxc_mesh3d_MOD_setmeshdistr+0xab6>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tvldr\td16, [r3]\n-\tcmp\tr1, r5\n-\tvldr\td19, [r3, #8]\n-\tadd.w\tr5, r5, #1\n-\tvldr\td18, [r3, #16]\n+\tcmp\tr7, r4\n+\tblt.w\t37c8 <__gridxc_mesh3d_MOD_setmeshdistr+0xa0c>\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr1, [sp, #152]\t@ 0x98\n+\tvldr\td6, [pc, #752]\t@ 38c8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0c>\n+\tvldr\td7, [r3]\n+\tcmp\tr4, r1\n+\tvldr\td4, [r3, #8]\n+\tadd.w\tr4, r4, #1\n+\tvldr\td5, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tvadd.f64\td16, d16, d19\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td17, d17, d16\n-\tbne.n\t38d4 <__gridxc_mesh3d_MOD_setmeshdistr+0x920>\n-\tvldr\td16, [pc, #708]\t@ 3bc0 <__gridxc_mesh3d_MOD_setmeshdistr+0xc0c>\n-\tvmul.f64\td16, d17, d16\n-\tvcmp.f64\td16, #0.0\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td6, d6, d7\n+\tbne.n\t35d8 <__gridxc_mesh3d_MOD_setmeshdistr+0x81c>\n+\tvldr\td7, [pc, #720]\t@ 38d0 <__gridxc_mesh3d_MOD_setmeshdistr+0xb14>\n+\tvmul.f64\td7, d6, d7\n+\tvcmp.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t3a6a <__gridxc_mesh3d_MOD_setmeshdistr+0xab6>\n-\tvmov.f64\td16, #8\t@ 0x40400000 3.0\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvmov.i64\td20, #0x0000000000000000\n-\tldr.w\tip, [sp, #108]\t@ 0x6c\n-\tvdiv.f64\td21, d16, d17\n-\tadd.w\tr5, r3, #24\n+\tbeq.w\t37c8 <__gridxc_mesh3d_MOD_setmeshdistr+0xa0c>\n+\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n+\tvldr\td3, [pc, #688]\t@ 38c8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0c>\n+\tldrd\tip, r3, [sp, #76]\t@ 0x4c\n \tmovs\tr7, #0\n-\tmovs\tr0, #3\n-\tldr.w\tr6, [ip, #-4]!\n-\tmov\tlr, r0\n-\tsubs\tr0, #1\n-\tcmp\tr6, #0\n-\tble.w\t3c7e <__gridxc_mesh3d_MOD_setmeshdistr+0xcca>\n-\tvmov.i64\td19, #0x0000000000000000\n-\tmov\tr2, r5\n+\tvdiv.f64\td2, d7, d6\n+\tmovs\tr4, #3\n+\tadd.w\tr0, r3, #24\n+\tldr.w\tr1, [ip, #-4]!\n+\tmov\tr6, r4\n+\tsubs\tr4, #1\n+\tcmp\tr1, #0\n+\tble.w\t39f0 <__gridxc_mesh3d_MOD_setmeshdistr+0xc34>\n+\tvldr\td4, [pc, #656]\t@ 38c8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb0c>\n+\tmov\tr2, r0\n \tmovs\tr3, #0\n-\tvmov.f64\td17, d19\n+\tvmov.f64\td6, d4\n \tvmov\ts15, r3\n-\tvldr\td18, [r2, #-8]\n-\tmul.w\tr1, r3, r3\n+\tvldr\td5, [r2, #-8]\n+\tmul.w\tlr, r3, r3\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmov\ts15, r1\n+\tvcvt.f64.s32\td7, s15\n \tadds\tr2, #24\n-\tcmp\tr6, r3\n-\tvfma.f64\td17, d18, d16\n-\tvcvt.f64.s32\td16, s15\n-\tvfma.f64\td19, d18, d16\n-\tbne.n\t3940 <__gridxc_mesh3d_MOD_setmeshdistr+0x98c>\n-\tvmul.f64\td17, d21, d17\n-\tvnmul.f64\td17, d17, d17\n-\tvfma.f64\td17, d21, d19\n-\tvcmpe.f64\td20, d17\n-\tsubs\tr5, #8\n+\tcmp\tr1, r3\n+\tvmla.f64\td6, d7, d5\n+\tvmov\ts14, lr\n+\tvcvt.f64.s32\td7, s14\n+\tvmla.f64\td4, d7, d5\n+\tbne.n\t3642 <__gridxc_mesh3d_MOD_setmeshdistr+0x886>\n+\tvmul.f64\td6, d2, d6\n+\tvmul.f64\td6, d6, d6\n+\tvnmls.f64\td6, d2, d4\n+\tvcmpe.f64\td3, d6\n+\tsubs\tr0, #8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvselge.f64\td20, d20, d17\n \tit\tmi\n-\tmovmi\tr7, lr\n-\tcmp\tr0, #0\n-\tbne.n\t3926 <__gridxc_mesh3d_MOD_setmeshdistr+0x972>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tsubs\tr5, r7, #1\n-\tldr\tr3, [sp, #232]\t@ 0xe8\n-\tmov\tr2, r4\n-\tldr\tr7, [sp, #140]\t@ 0x8c\n-\tvst1.32\t{d12-d13}, [r8]\n+\tvmovmi.f64\td3, d6\n+\tit\tmi\n+\tmovmi\tr7, r6\n+\tcmp\tr4, #0\n+\tbne.n\t3628 <__gridxc_mesh3d_MOD_setmeshdistr+0x86c>\n+\tldr\tr6, [sp, #144]\t@ 0x90\n+\tsubs\tr7, #1\n+\tstr\tr6, [sp, #0]\n+\tmov.w\tr8, #2\n+\tmovs\tr6, #4\n+\tstr\tr6, [r5, #20]\n+\tstrd\tr4, r4, [sp, #388]\t@ 0x184\n+\tmovs\tr6, #6\n+\tstr\tr4, [sp, #396]\t@ 0x18c\n+\tmov.w\tip, r7, lsl #3\n+\tstrd\tr8, r6, [r5, #32]\n+\tmov\tr2, r5\n+\tldr\tr6, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n+\tadd\tr6, ip\n+\tstr\tr6, [r5, #0]\n \tldr\tr6, [sp, #80]\t@ 0x50\n-\tstr\tr7, [sp, #0]\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tldr.w\tr3, [r3, r5, lsl #2]\n-\tlsls\tr5, r5, #3\n-\tvstr\td16, [sp, #448]\t@ 0x1c0\n-\tadd\tr6, r5\n-\tvstr\td16, [sp, #452]\t@ 0x1c4\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tstr\tr1, [r4, #44]\t@ 0x2c\n-\tvst1.32\t{d8}, [r9]\n-\tadd\tr0, r5\n-\tstr\tr6, [r4, #0]\n-\tldr\tr6, [sp, #68]\t@ 0x44\n-\tvstr\td16, [sp, #408]\t@ 0x198\n-\tadd\tr5, r6\n-\tvstr\td16, [sp, #412]\t@ 0x19c\n+\tadd\tr0, ip\n+\tldr\tr3, [sp, #232]\t@ 0xe8\n+\tadd\tip, r6\n \tmvn.w\tr6, #6\n-\tstr\tr6, [r4, #4]\n-\tmovs\tr4, #1\n-\tstr\tr4, [r7, #28]\n-\tadd\tr4, sp, #420\t@ 0x1a4\n-\tstr\tr3, [r7, #32]\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tvst1.32\t{d10}, [r4]\n+\tstr\tr6, [r5, #4]\n+\tldr\tr6, [sp, #144]\t@ 0x90\n+\tldr.w\tlr, [r3, r7, lsl #2]\n+\tmovs\tr7, #1\n+\tldr\tr1, [sp, #112]\t@ 0x70\n+\tstrd\tr7, r7, [r5, #24]\n+\tstr\tr7, [r5, #40]\t@ 0x28\n+\tstr\tr1, [r5, #44]\t@ 0x2c\n+\tmovs\tr5, #8\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tstr\tr5, [r6, #20]\n+\tstrd\tr4, r4, [sp, #352]\t@ 0x160\n+\tstr\tr4, [sp, #360]\t@ 0x168\n+\tmovs\tr4, #3\n+\tstrd\tr7, lr, [r6, #28]\n+\tstr\tr4, [r6, #24]\n \tmvn.w\tr4, #2\n-\tstr\tr5, [r7, #0]\n-\tstr\tr4, [r7, #4]\n-\tbl\t934 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>\n-\tldr\tr0, [sp, #68]\t@ 0x44\n+\tstr.w\tip, [r6]\n+\tstr\tr4, [r6, #4]\n+\tbl\t904 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>\n+\tldr\tr0, [sp, #80]\t@ 0x50\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [sp, #132]\t@ 0x84\n-\tmovs\tr3, #6\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tldr\tr1, [sp, #120]\t@ 0x78\n-\tmul.w\tr2, r3, r2\n-\tldr\tr3, [sp, #160]\t@ 0xa0\n-\tadds\tr1, #1\n-\tstr\tr1, [sp, #120]\t@ 0x78\n-\tcmp\tr3, r1\n-\tadd.w\tr2, r0, r2, lsl #2\n-\tvld1.64\t{d18-d19}, [r2 :64]\n-\tvldr\td16, [r2, #16]\n-\tvstr\td18, [sp, #376]\t@ 0x178\n-\tvstr\td19, [sp, #384]\t@ 0x180\n-\tvstr\td16, [sp, #392]\t@ 0x188\n-\tbge.w\t345c <__gridxc_mesh3d_MOD_setmeshdistr+0x4a8>\n-\tldrd\tr8, r4, [sp, #252]\t@ 0xfc\n-\tmov\tr7, sl\n-\tldr\tr6, [sp, #260]\t@ 0x104\n-\tmov\tsl, fp\n-\tcmp.w\tr8, #0\n-\tbne.w\t340c <__gridxc_mesh3d_MOD_setmeshdistr+0x458>\n-\tldr\tr7, [sp, #248]\t@ 0xf8\n-\tvldr\td12, [sp, #376]\t@ 0x178\n-\tvldr\td13, [sp, #384]\t@ 0x180\n-\tvldr\td8, [sp, #392]\t@ 0x188\n-\tldr\tr0, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #148]\t@ 0x94\n+\tmovs\tr2, #6\n+\tldr\tr1, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #120]\t@ 0x78\n+\tmul.w\tr3, r2, r3\n+\tadds\tr0, #1\n+\tstr\tr0, [sp, #120]\t@ 0x78\n+\tmov\tr2, r3\n+\tadd.w\tr3, r1, r3, lsl #2\n+\tldr.w\tr2, [r1, r2, lsl #2]\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tstr\tr2, [r1, #0]\n+\tldr\tr2, [r3, #4]\n+\tstr\tr2, [r1, #4]\n+\tldr\tr2, [r3, #8]\n+\tstr\tr2, [r1, #8]\n+\tldr\tr2, [r3, #12]\n+\tstr\tr2, [r1, #12]\n+\tldr\tr2, [r3, #16]\n+\tldr\tr3, [r3, #20]\n+\tstr\tr3, [r1, #20]\n+\tldr\tr3, [sp, #176]\t@ 0xb0\n+\tstr\tr2, [r1, #16]\n+\tcmp\tr3, r0\n+\tbge.w\t326c <__gridxc_mesh3d_MOD_setmeshdistr+0x4b0>\n+\tldrd\tr7, r9, [sp, #264]\t@ 0x108\n+\tcmp\tr7, #0\n+\tbne.w\t3230 <__gridxc_mesh3d_MOD_setmeshdistr+0x474>\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldrd\tr6, sl, [sp, #256]\t@ 0x100\n+\tldrd\tr7, r2, [r3]\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n+\tldrd\tr5, r2, [r3, #8]\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tldrd\tr4, r3, [r3, #16]\n+\tstr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.w\t3230 <__gridxc_mesh3d_MOD_setmeshdistr+0x27c>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadds\tr4, #1\n-\tadd\tlr, sl\n-\tcmp\tr3, r4\n-\tbge.w\t35f2 <__gridxc_mesh3d_MOD_setmeshdistr+0x63e>\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tb.n\t3038 <__gridxc_mesh3d_MOD_setmeshdistr+0x27c>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tadd.w\tlr, lr, #1\n+\tadd\tr7, fp\n+\tcmp\tr3, lr\n+\tbge.w\t3384 <__gridxc_mesh3d_MOD_setmeshdistr+0x5c8>\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tadd.w\tip, ip, #1\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #104]\t@ 0x68\n \tcmp\tr3, ip\n-\tbge.w\t35de <__gridxc_mesh3d_MOD_setmeshdistr+0x62a>\n-\tmov\tr4, r1\n-\tb.n\t36a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x6f2>\n-\tldr\tr3, [sp, #212]\t@ 0xd4\n-\tldr\tr2, [sp, #224]\t@ 0xe0\n-\tcmp\tr3, r2\n-\tble.w\t3caa <__gridxc_mesh3d_MOD_setmeshdistr+0xcf6>\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tldr\tr2, [sp, #220]\t@ 0xdc\n-\tcmp\tr3, r2\n-\tbeq.w\t3ca6 <__gridxc_mesh3d_MOD_setmeshdistr+0xcf2>\n-\tldr\tr2, [sp, #216]\t@ 0xd8\n-\tmov.w\tr5, #4294967295\t@ 0xffffffff\n-\tcmp\tr3, r2\n-\tit\teq\n-\tmoveq\tr5, #0\n-\tlsls\tr5, r5, #3\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr0, [sp, #108]\t@ 0x6c\n-\tldr\tr6, [sp, #80]\t@ 0x50\n-\tmovs\tr3, #0\n-\tldr\tr1, [sp, #104]\t@ 0x68\n-\tadd\tr0, r5\n-\tvst1.32\t{d12-d13}, [r8]\n-\tadd\tr5, r6\n-\tmov\tr2, r4\n-\tvstr\td16, [sp, #448]\t@ 0x1c0\n-\tvstr\td16, [sp, #452]\t@ 0x1c4\n-\tstr\tr1, [r4, #44]\t@ 0x2c\n-\tvst1.32\t{d8}, [r9]\n-\tstr\tr3, [sp, #0]\n-\tstr\tr5, [r4, #0]\n-\tmvn.w\tr5, #6\n-\tldr\tr3, [sp, #148]\t@ 0x94\n-\tstr\tr5, [r4, #4]\n-\tbl\t934 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>\n-\tb.n\t39e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xa34>\n-\tldr\tr3, [pc, #260]\t@ (3bc8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc14>)\n+\tbge.w\t336e <__gridxc_mesh3d_MOD_setmeshdistr+0x5b2>\n+\tmov\tr7, r1\n+\tb.n\t33ba <__gridxc_mesh3d_MOD_setmeshdistr+0x5fe>\n+\tldr\tr3, [pc, #352]\t@ (38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>)\n \tmovs\tr1, #64\t@ 0x40\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #280]\t@ (3be4 <__gridxc_mesh3d_MOD_setmeshdistr+0xc30>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #416]\t@ (3930 <__gridxc_mesh3d_MOD_setmeshdistr+0xb74>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [sp, #112]\t@ 0x70\n-\tsdiv\tr3, r4, r2\n-\tmls\tr3, r2, r3, r4\n-\tcmp\tr3, #0\n-\tbeq.w\t356e <__gridxc_mesh3d_MOD_setmeshdistr+0x5ba>\n-\tmovs\tr2, #1\n-\tb.n\t358c <__gridxc_mesh3d_MOD_setmeshdistr+0x5d8>\n-\tadd\tr2, sp, #400\t@ 0x190\n-\tldr\tr0, [sp, #72]\t@ 0x48\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmov\tr0, r7\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.w\t3300 <__gridxc_mesh3d_MOD_setmeshdistr+0x544>\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tadds\tr0, r4, #1\n+\tmovs\tr3, #1\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tcmp\tr1, #0\n+\tbeq.w\t332c <__gridxc_mesh3d_MOD_setmeshdistr+0x570>\n+\tldr\tr3, [pc, #304]\t@ (38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>)\n+\tmovs\tr1, #62\t@ 0x3e\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #372]\t@ (3934 <__gridxc_mesh3d_MOD_setmeshdistr+0xb78>)\n+\tldr\tr3, [r2, r3]\n+\tadd\tr0, pc\n+\tldr\tr3, [r3, #0]\n+\tblx\tr3\n+\tb.n\t3356 <__gridxc_mesh3d_MOD_setmeshdistr+0x59a>\n+\tldr\tr3, [sp, #216]\t@ 0xd8\n+\tldr\tr2, [sp, #228]\t@ 0xe4\n+\tcmp\tr3, r2\n+\tble.w\t3a26 <__gridxc_mesh3d_MOD_setmeshdistr+0xc6a>\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tldr\tr2, [sp, #224]\t@ 0xe0\n+\tcmp\tr3, r2\n+\tbeq.w\t3a22 <__gridxc_mesh3d_MOD_setmeshdistr+0xc66>\n+\tldr\tr2, [sp, #220]\t@ 0xdc\n+\tsubs\tr4, r3, r2\n+\tit\tne\n+\tmovne.w\tr4, #4294967295\t@ 0xffffffff\n+\tlsls\tr4, r4, #3\n+\tldr\tr6, [sp, #96]\t@ 0x60\n+\tmovs\tr7, #0\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n+\tmov.w\tip, #1\n+\tldr\tr1, [sp, #112]\t@ 0x70\n+\tmov\tr2, r5\n+\tstr\tr7, [sp, #0]\n+\tadd\tr0, r4\n+\tldr\tr3, [sp, #156]\t@ 0x9c\n+\tadd\tr4, r6\n+\tmovs\tr6, #4\n+\tstr\tr6, [r5, #20]\n+\tstrd\tr7, r7, [sp, #388]\t@ 0x184\n+\tmovs\tr6, #2\n+\tstr\tr7, [sp, #396]\t@ 0x18c\n+\tstr\tr4, [r5, #0]\n+\tmovs\tr4, #6\n+\tstrd\tip, ip, [r5, #24]\n+\tstrd\tr6, r4, [r5, #32]\n+\tmvn.w\tr4, #6\n+\tstr.w\tip, [r5, #40]\t@ 0x28\n+\tstr\tr1, [r5, #44]\t@ 0x2c\n+\tstr\tr4, [r5, #4]\n+\tbl\t904 <__gridxc_mesh3d_MOD_dividebox1d.constprop.1.isra.0>\n+\tb.n\t36f8 <__gridxc_mesh3d_MOD_setmeshdistr+0x93c>\n+\tadd\tr2, sp, #344\t@ 0x158\n+\tldr\tr0, [sp, #84]\t@ 0x54\n \tmov\tr5, r2\n \tmov\tr3, r2\n-\tstr\tr2, [sp, #140]\t@ 0x8c\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tbl\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tstr\tr2, [sp, #144]\t@ 0x90\n+\tldr\tr2, [sp, #164]\t@ 0xa4\n+\tbl\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n \tmov\tr2, r5\n \tldrd\tr3, r5, [r5]\n \tsubs\tr5, r5, r3\n \tldrd\tr3, r7, [r2, #8]\n \tsubs\tr7, r7, r3\n \tldrd\tr3, r2, [r2, #16]\n \tadd.w\tr9, r7, #1\n \tsubs\tr3, r2, r3\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #68]\t@ 0x44\n \tadds\tr6, r3, #1\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #100]\t@ 0x64\n \tadds\tr2, r5, #1\n-\tstr\tr2, [sp, #48]\t@ 0x30\n+\tstr\tr2, [sp, #52]\t@ 0x34\n \tcmp\tr3, r5\n-\tbeq.w\t3766 <__gridxc_mesh3d_MOD_setmeshdistr+0x7b2>\n-\tldr\tr3, [pc, #168]\t@ (3bc8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc14>)\n-\tmovs\tr1, #62\t@ 0x3e\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #192]\t@ (3be8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc34>)\n-\tldr\tr3, [r2, r3]\n-\tadd\tr0, pc\n-\tldr\tr3, [r3, #0]\n-\tblx\tr3\n-\tb.n\t3778 <__gridxc_mesh3d_MOD_setmeshdistr+0x7c4>\n-\tldr\tr3, [pc, #148]\t@ (3bc8 <__gridxc_mesh3d_MOD_setmeshdistr+0xc14>)\n+\tbeq.w\t347c <__gridxc_mesh3d_MOD_setmeshdistr+0x6c0>\n+\tldr\tr3, [pc, #132]\t@ (38e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xb2c>)\n \tmovs\tr1, #62\t@ 0x3e\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #180]\t@ (3bec <__gridxc_mesh3d_MOD_setmeshdistr+0xc38>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #208]\t@ (3938 <__gridxc_mesh3d_MOD_setmeshdistr+0xb7c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t35c8 <__gridxc_mesh3d_MOD_setmeshdistr+0x614>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tb.n\t348e <__gridxc_mesh3d_MOD_setmeshdistr+0x6d2>\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tadd.w\tip, ip, #1\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #104]\t@ 0x68\n \tcmp\tr3, ip\n-\tblt.w\t36a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x6f2>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tblt.w\t33ba <__gridxc_mesh3d_MOD_setmeshdistr+0x5fe>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tcmp\tr3, #0\n-\tblt.n\t3b42 <__gridxc_mesh3d_MOD_setmeshdistr+0xb8e>\n-\tmov\tr3, r5\n-\tldr\tr5, [sp, #88]\t@ 0x58\n-\tmov\tr1, r4\n+\tblt.n\t3872 <__gridxc_mesh3d_MOD_setmeshdistr+0xab6>\n+\tmov\tr3, r4\n+\tldr\tr4, [sp, #100]\t@ 0x64\n+\tmov\tr1, r7\n \tmov\tlr, r2\n \tmovs\tr0, #0\n-\tcmp\tr5, #0\n-\tblt.w\t3c84 <__gridxc_mesh3d_MOD_setmeshdistr+0xcd0>\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tstrd\tr2, ip, [sp, #48]\t@ 0x30\n-\tlsls\tr4, r4, #3\n-\tadd.w\tip, fp, lr, lsl #3\n+\tcmp\tr4, #0\n+\tblt.w\t3a2a <__gridxc_mesh3d_MOD_setmeshdistr+0xc6e>\n+\tldr\tr7, [sp, #116]\t@ 0x74\n+\tstrd\tr2, ip, [sp, #52]\t@ 0x34\n+\tlsls\tr7, r7, #3\n+\tadd.w\tip, sl, lr, lsl #3\n \tmovs\tr2, #0\n-\tb.n\t3b80 <__gridxc_mesh3d_MOD_setmeshdistr+0xbcc>\n+\tb.n\t38b0 <__gridxc_mesh3d_MOD_setmeshdistr+0xaf4>\n \tadds\tr2, #1\n-\tadd\tip, r4\n-\tcmp\tr5, r2\n-\tblt.n\t3b96 <__gridxc_mesh3d_MOD_setmeshdistr+0xbe2>\n-\tvldr\td16, [ip]\n-\tvcmpe.f64\td16, #0.0\n+\tadd\tip, r7\n+\tcmp\tr4, r2\n+\tblt.n\t393c <__gridxc_mesh3d_MOD_setmeshdistr+0xb80>\n+\tvldr\td7, [ip]\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t3b78 <__gridxc_mesh3d_MOD_setmeshdistr+0xbc4>\n-\tstr\tr5, [sp, #88]\t@ 0x58\n-\tmov\tr4, r1\n-\tmov\tr5, r3\n-\tb.n\t3692 <__gridxc_mesh3d_MOD_setmeshdistr+0x6de>\n-\tldr\tr2, [sp, #84]\t@ 0x54\n-\tadds\tr0, #1\n-\tadd\tlr, sl\n-\tcmp\tr2, r0\n-\tbge.n\t3b70 <__gridxc_mesh3d_MOD_setmeshdistr+0xbbc>\n-\tldrd\tr2, ip, [sp, #48]\t@ 0x30\n-\tadd.w\tip, ip, #1\n-\tldr\tr0, [sp, #56]\t@ 0x38\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n-\tcmp\tr0, ip\n-\tbge.n\t3b5e <__gridxc_mesh3d_MOD_setmeshdistr+0xbaa>\n-\tstr\tr5, [sp, #88]\t@ 0x58\n-\tmov\tr4, r1\n-\tmov\tr5, r3\n-\tb.n\t36a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x6f2>\n-\tmov\tr1, r0\n-\tmovs\tr3, #1\n-\tb.n\t34f2 <__gridxc_mesh3d_MOD_setmeshdistr+0x53e>\n+\tbpl.n\t38a8 <__gridxc_mesh3d_MOD_setmeshdistr+0xaec>\n+\tstr\tr4, [sp, #100]\t@ 0x64\n+\tmov\tr7, r1\n+\tmov\tr4, r3\n+\tb.n\t33a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x5ea>\n+\tnop\n+\t...\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n \t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000af6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000ad6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t...\n+ R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000528\n- R_ARM_REL32\t.LC48\n-\t.word\t0x00000440\n- R_ARM_REL32\t.LC40\n-\t.word\t0x0000042c\n+\t.word\t0x00000a66\n+ R_ARM_REL32\t.LC30\n+\t.word\t0x00000a36\n+ R_ARM_REL32\t.LC31\n+\t.word\t0x000009b4\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x0000097e\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x00000920\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n+\t.word\t0x000008c0\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x0000085a\n+ R_ARM_REL32\t.LC32\n+\t.word\t0x00000816\n+ R_ARM_REL32\t.LC34\n+\t.word\t0x000007a0\n+ R_ARM_REL32\t.LC33\n+\t.word\t0x000006f6\n R_ARM_REL32\t.bss\n-\t.word\t0x00000422\n- R_ARM_REL32\t.LC42\n-\t.word\t0x00000360\n+\t.word\t0x000006f4\n R_ARM_REL32\t.bss\n-\t.word\t0x0000031e\n+\t.word\t0x000006bc\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000006b8\n R_ARM_REL32\t.LC42\n-\t.word\t0x00000114\n+\t.word\t0x0000056c\n+ R_ARM_REL32\t.LC48\n+\t.word\t0x00000482\n+ R_ARM_REL32\t.LC40\n+\t.word\t0x00000368\n+ R_ARM_REL32\t.LC42\n+\t.word\t0x0000019c\n R_ARM_REL32\t.LC36\n-\t.word\t0x000000bc\n- R_ARM_REL32\t.LC39\n-\t.word\t0x000000ae\n+\t.word\t0x00000170\n R_ARM_REL32\t.LC37\n+\t.word\t0x000000ca\n+ R_ARM_REL32\t.LC39\n+\tldr\tr2, [sp, #92]\t@ 0x5c\n+\tadds\tr0, #1\n+\tadd\tlr, fp\n+\tcmp\tr0, r2\n+\tble.n\t38a0 <__gridxc_mesh3d_MOD_setmeshdistr+0xae4>\n+\tldrd\tr2, ip, [sp, #52]\t@ 0x34\n+\tadd.w\tip, ip, #1\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n+\tadd\tr2, r0\n+\tldr\tr0, [sp, #104]\t@ 0x68\n+\tcmp\tr0, ip\n+\tbge.n\t388e <__gridxc_mesh3d_MOD_setmeshdistr+0xad2>\n+\tstr\tr4, [sp, #100]\t@ 0x64\n+\tmov\tr7, r1\n+\tmov\tr4, r3\n+\tb.n\t33ba <__gridxc_mesh3d_MOD_setmeshdistr+0x5fe>\n \tmul.w\tr9, r4, r2\n \tldr\tr2, [sp, #116]\t@ 0x74\n \tmul.w\tr0, r4, r6\n \tmov\tr3, r8\n \tmul.w\tr4, r4, ip\n-\tstr\tr0, [sp, #164]\t@ 0xa4\n+\tstr\tr0, [sp, #184]\t@ 0xb8\n \tlsls\tr6, r2, #3\n \tmov\tr0, r8\n \tmov\tlr, r3\n \tmov\tip, r1\n \tmov.w\tr8, #0\n-\tstrd\tr3, r1, [sp, #48]\t@ 0x30\n-\tstr\tr0, [sp, #76]\t@ 0x4c\n-\tadd.w\tr0, fp, lr, lsl #3\n+\tstrd\tr3, r1, [sp, #52]\t@ 0x34\n+\tstr\tr0, [sp, #88]\t@ 0x58\n+\tadd.w\tr0, sl, lr, lsl #3\n \tmov\tr1, ip\n \tmovs\tr2, #0\n-\tvldr\td16, [r0]\n-\tcmp\tr2, r5\n+\tvldr\td7, [r0]\n+\tcmp\tr5, r2\n \tadd\tr0, r6\n \tadd.w\tr2, r2, #1\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd\tr1, r4\n-\tblt.n\t3c1c <__gridxc_mesh3d_MOD_setmeshdistr+0xc68>\n+\tbgt.n\t398c <__gridxc_mesh3d_MOD_setmeshdistr+0xbd0>\n \tadd\tip, r9\n-\tadd\tlr, sl\n+\tadd\tlr, fp\n \tadd.w\tr3, r8, #1\n \tcmp\tr8, r7\n-\tbge.n\t3c40 <__gridxc_mesh3d_MOD_setmeshdistr+0xc8c>\n+\tbge.n\t39b0 <__gridxc_mesh3d_MOD_setmeshdistr+0xbf4>\n \tmov\tr8, r3\n-\tb.n\t3c14 <__gridxc_mesh3d_MOD_setmeshdistr+0xc60>\n-\tldrd\tr3, r1, [sp, #48]\t@ 0x30\n-\tldr\tr2, [sp, #164]\t@ 0xa4\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n+\tb.n\t3984 <__gridxc_mesh3d_MOD_setmeshdistr+0xbc8>\n+\tldrd\tr3, r1, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #184]\t@ 0xb8\n+\tldr\tr0, [sp, #88]\t@ 0x58\n \tadd\tr1, r2\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd.w\tip, r0, #1\n \tadd\tr3, r2\n-\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #68]\t@ 0x44\n \tcmp\tr0, r2\n-\tbge.w\t3868 <__gridxc_mesh3d_MOD_setmeshdistr+0x8b4>\n+\tbge.w\t3576 <__gridxc_mesh3d_MOD_setmeshdistr+0x7ba>\n \tmov\tr0, ip\n-\tb.n\t3c06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc52>\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tadds\tr4, #1\n-\tadd\tlr, sl\n-\tcmp\tr3, r4\n-\tbge.w\t35ea <__gridxc_mesh3d_MOD_setmeshdistr+0x636>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n+\tb.n\t3976 <__gridxc_mesh3d_MOD_setmeshdistr+0xbba>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tadd.w\tlr, lr, #1\n+\tadd\tr7, fp\n+\tcmp\tr3, lr\n+\tbge.w\t337c <__gridxc_mesh3d_MOD_setmeshdistr+0x5c0>\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n \tadd.w\tip, ip, #1\n \tadd\tr2, r3\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #104]\t@ 0x68\n \tcmp\tr3, ip\n-\tbge.w\t35e6 <__gridxc_mesh3d_MOD_setmeshdistr+0x632>\n-\tmov\tr4, r1\n-\tb.n\t36a6 <__gridxc_mesh3d_MOD_setmeshdistr+0x6f2>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tb.n\t3974 <__gridxc_mesh3d_MOD_setmeshdistr+0x9c0>\n-\tldr\tr4, [sp, #84]\t@ 0x54\n-\tadds\tr0, #1\n-\tadd\tlr, sl\n-\tcmp\tr4, r0\n-\tbge.w\t3b62 <__gridxc_mesh3d_MOD_setmeshdistr+0xbae>\n-\tb.n\t3ba4 <__gridxc_mesh3d_MOD_setmeshdistr+0xbf0>\n-\tldr\tr5, [sp, #68]\t@ 0x44\n-\tldr.w\tr1, [pc, #1072]\t@ 40c8 <__gridxc_mesh3d_MOD_setmeshdistr+0x1114>\n+\tbge.w\t3376 <__gridxc_mesh3d_MOD_setmeshdistr+0x5ba>\n+\tmov\tr7, r1\n+\tb.n\t33ba <__gridxc_mesh3d_MOD_setmeshdistr+0x5fe>\n+\tvldr\td6, [pc, #780]\t@ 3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xf44>\n+\tb.n\t3676 <__gridxc_mesh3d_MOD_setmeshdistr+0x8ba>\n+\tldr\tr5, [sp, #80]\t@ 0x50\n+\tldr\tr1, [pc, #780]\t@ (3d08 <__gridxc_mesh3d_MOD_setmeshdistr+0xf4c>)\n \tmov\tr2, r5\n-\tldr.w\tr0, [pc, #1072]\t@ 40cc <__gridxc_mesh3d_MOD_setmeshdistr+0x1118>\n+\tldr\tr0, [pc, #780]\t@ (3d0c <__gridxc_mesh3d_MOD_setmeshdistr+0xf50>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tmovs\tr5, #8\n-\tb.n\t3a8c <__gridxc_mesh3d_MOD_setmeshdistr+0xad8>\n-\tmovs\tr5, #16\n-\tb.n\t3a8c <__gridxc_mesh3d_MOD_setmeshdistr+0xad8>\n-\tldr.w\tr0, [pc, #1056]\t@ 40d0 <__gridxc_mesh3d_MOD_setmeshdistr+0x111c>\n+\tldr\tr0, [pc, #776]\t@ (3d10 <__gridxc_mesh3d_MOD_setmeshdistr+0xf54>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n \tmovs\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #68]\t@ 0x44\n+\tstr\tr0, [sp, #80]\t@ 0x50\n \tcmp\tr0, #0\n-\tbeq.n\t3c92 <__gridxc_mesh3d_MOD_setmeshdistr+0xcde>\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tbeq.n\t39f6 <__gridxc_mesh3d_MOD_setmeshdistr+0xc3a>\n+\tldr\tr3, [sp, #136]\t@ 0x88\n \tsubs\tr3, #1\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tb.n\t3732 <__gridxc_mesh3d_MOD_setmeshdistr+0x77e>\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tadd\tr2, sp, #184\t@ 0xb8\n-\tldr\tr1, [sp, #176]\t@ 0xb0\n-\tvld1.32\t{d8[1]}, [r2]\n-\tstrd\tr3, r5, [sp, #264]\t@ 0x108\n-\tstr\tr3, [sp, #272]\t@ 0x110\n-\tstr\tr1, [sp, #276]\t@ 0x114\n-\tvldr\td12, [sp, #264]\t@ 0x108\n-\tvldr\td13, [sp, #272]\t@ 0x110\n-\tb.n\t3a3e <__gridxc_mesh3d_MOD_setmeshdistr+0xa8a>\n-\tldr\tr1, [pc, #1000]\t@ (40d4 <__gridxc_mesh3d_MOD_setmeshdistr+0x1120>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #1000]\t@ (40d8 <__gridxc_mesh3d_MOD_setmeshdistr+0x1124>)\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tb.n\t3448 <__gridxc_mesh3d_MOD_setmeshdistr+0x68c>\n+\tmovs\tr4, #8\n+\tb.n\t37e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xa2c>\n+\tmovs\tr4, #16\n+\tb.n\t37e8 <__gridxc_mesh3d_MOD_setmeshdistr+0xa2c>\n+\tldr\tr7, [sp, #92]\t@ 0x5c\n+\tadds\tr0, #1\n+\tadd\tlr, fp\n+\tcmp\tr7, r0\n+\tbge.w\t3892 <__gridxc_mesh3d_MOD_setmeshdistr+0xad6>\n+\tb.n\t394a <__gridxc_mesh3d_MOD_setmeshdistr+0xb8e>\n+\tmov\tr5, r4\n+\tmov\tr7, r4\n+\tb.n\t375a <__gridxc_mesh3d_MOD_setmeshdistr+0x99e>\n+\tldr\tr1, [pc, #724]\t@ (3d14 <__gridxc_mesh3d_MOD_setmeshdistr+0xf58>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #724]\t@ (3d18 <__gridxc_mesh3d_MOD_setmeshdistr+0xf5c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tsdiv\tr8, r9, r2\n-\tstr.w\tr8, [r6, #8]\n-\tmul.w\tr2, r2, r8\n-\tcmp\tr9, r2\n-\tblt.w\t3f7e <__gridxc_mesh3d_MOD_setmeshdistr+0xfca>\n-\tstr.w\tr2, [fp]\n-\tcmp\tr3, r5\n+\tmov\tr0, r9\n+\tstrd\tr1, r3, [sp, #52]\t@ 0x34\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr8, r0\n+\tldrd\tr1, r3, [sp, #52]\t@ 0x34\n+\tstr\tr0, [r5, #8]\n+\tmul.w\tr1, r1, r8\n+\tcmp\tr9, r1\n+\tit\tge\n+\tstrge.w\tr1, [fp]\n+\tbge.n\t3a80 <__gridxc_mesh3d_MOD_setmeshdistr+0xcc4>\n+\tldr\tr2, [pc, #684]\t@ (3d1c <__gridxc_mesh3d_MOD_setmeshdistr+0xf60>)\n+\tmovs\tr1, #42\t@ 0x2a\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #680]\t@ (3d20 <__gridxc_mesh3d_MOD_setmeshdistr+0xf64>)\n+\tldr\tr2, [r3, r2]\n+\tadd\tr0, pc\n+\tldr\tr2, [r2, #0]\n+\tblx\tr2\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr3, r4\n \tmov\tr2, r3\n \tit\tlt\n-\tmovlt\tr2, r5\n+\tmovlt\tr2, r4\n \tcmp\tr2, r8\n \tit\tlt\n \tmovlt\tr2, r8\n-\torr.w\tsl, r2, r2, asr #31\n-\tadds.w\tsl, sl, #1\n-\tbeq.w\t3f7a <__gridxc_mesh3d_MOD_setmeshdistr+0xfc6>\n+\torr.w\tr7, r2, r2, asr #31\n+\tadds\tr7, #1\n+\tbeq.w\t3cde <__gridxc_mesh3d_MOD_setmeshdistr+0xf22>\n \tmovs\tr1, #6\n \tlsrs\tr2, r2, #31\n-\tmul.w\tsl, r1, sl\n-\tcmp.w\tsl, #1073741824\t@ 0x40000000\n-\tbge.n\t3cae <__gridxc_mesh3d_MOD_setmeshdistr+0xcfa>\n-\tmov.w\tsl, sl, lsl #2\n-\tmov\tr0, sl\n-\tcbz\tr2, 3d44 <__gridxc_mesh3d_MOD_setmeshdistr+0xd90>\n+\tmul.w\tr7, r1, r7\n+\tcmp.w\tr7, #1073741824\t@ 0x40000000\n+\tbge.n\t3a06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc4a>\n+\tlsls\tr7, r7, #2\n+\tmov\tr0, r7\n+\tcbz\tr2, 3ab0 <__gridxc_mesh3d_MOD_setmeshdistr+0xcf4>\n \tmovs\tr0, #1\n-\tmov.w\tsl, #0\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tmovs\tr7, #0\n+\tstr\tr3, [sp, #52]\t@ 0x34\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tmov\tr9, r0\n \tcmp\tr0, #0\n-\tbeq.w\t3f6c <__gridxc_mesh3d_MOD_setmeshdistr+0xfb8>\n-\tldr\tr2, [sp, #72]\t@ 0x48\n+\tbeq.w\t3cd0 <__gridxc_mesh3d_MOD_setmeshdistr+0xf14>\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tadd.w\tfp, r0, #8\n-\tldr.w\tlr, [sp, #112]\t@ 0x70\n-\tmov.w\tsl, #1\n+\tmov\tr7, r3\n \tsubs\tr2, #4\n+\tstrd\tr5, r2, [sp, #56]\t@ 0x38\n+\tmovs\tr2, #1\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr.w\tr0, [r3, #4]!\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr.w\tr5, [r3], #4\n \tstr\tr3, [sp, #56]\t@ 0x38\n-\tstrd\tr6, r2, [sp, #48]\t@ 0x30\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tmov\tr1, r5\n+\tbl\t0 <__aeabi_idivmod>\n+ R_ARM_THM_CALL\t__aeabi_idivmod\n+\tldr\tr2, [sp, #72]\t@ 0x48\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tcmp\tr5, #0\n \tstr.w\tr3, [fp, #-4]\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr1, [r3, #4]!\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tsdiv\tr1, r1, lr\n-\tldr.w\tr0, [r3], #4\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tcmp\tr0, #0\n-\tsdiv\tr2, r1, r0\n-\tmls\tr1, r0, r2, r1\n-\tmla\tr3, r2, lr, lr\n-\tble.n\t3df2 <__gridxc_mesh3d_MOD_setmeshdistr+0xe3e>\n-\tcmp\tr1, #0\n-\tble.w\t3f68 <__gridxc_mesh3d_MOD_setmeshdistr+0xfb4>\n-\tcmp\tr1, r0\n+\tmov\tr3, r1\n+\tmla\tr1, r0, r2, r2\n+\tble.n\t3b5c <__gridxc_mesh3d_MOD_setmeshdistr+0xda0>\n+\tcmp\tr3, #0\n+\tble.w\t3ccc <__gridxc_mesh3d_MOD_setmeshdistr+0xf10>\n+\tcmp\tr3, r5\n \tmov\tip, fp\n-\tmov.w\tr6, #4294967295\t@ 0xffffffff\n-\tmov.w\tr2, #0\n \tit\tge\n-\tmovge\tr1, r0\n-\tstr\tr1, [sp, #60]\t@ 0x3c\n-\tadds\tr1, r6, #1\n-\tstr.w\tr1, [ip, #16]\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n+\tmovge\tr3, r5\n+\tmov.w\tr0, #4294967295\t@ 0xffffffff\n+\tmovs\tr2, #0\n \tadds\tr2, #1\n-\tadd\tr6, r3\n+\tadd.w\tlr, r0, #1\n \tadd.w\tip, ip, #24\n-\tstr.w\tr6, [ip, #-4]\n-\tcmp\tr2, r1\n-\tblt.n\t3dae <__gridxc_mesh3d_MOD_setmeshdistr+0xdfa>\n-\tcmp\tr0, r2\n-\tble.n\t3df2 <__gridxc_mesh3d_MOD_setmeshdistr+0xe3e>\n-\tadd.w\tr1, r2, r2, lsl #1\n-\tsub.w\tr6, r3, lr\n-\tadd\tr1, sl\n-\tadd.w\tr1, r9, r1, lsl #3\n-\tldr.w\tr3, [r1, #-4]\n-\tadds\tr1, #24\n+\tadd\tr0, r1\n+\tstr.w\tlr, [ip, #-8]\n+\tcmp\tr2, r3\n+\tstr.w\tr0, [ip, #-4]\n+\tblt.n\t3b16 <__gridxc_mesh3d_MOD_setmeshdistr+0xd5a>\n+\tcmp\tr5, r2\n+\tble.n\t3b5c <__gridxc_mesh3d_MOD_setmeshdistr+0xda0>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #52]\t@ 0x34\n+\tsubs\tr1, r1, r3\n+\tadd.w\tr3, r2, r2, lsl #1\n+\tadd\tr3, r0\n+\tadd.w\tr3, r9, r3, lsl #3\n+\tldr.w\tr0, [r3, #-4]\n+\tadds\tr3, #24\n \tadds\tr2, #1\n-\tadd.w\tip, r3, #1\n-\tcmp\tr0, r2\n-\tadd\tr3, r6\n-\tstr.w\tip, [r1, #-8]\n-\tstr.w\tr3, [r1, #-4]\n-\tbgt.n\t3dd8 <__gridxc_mesh3d_MOD_setmeshdistr+0xe24>\n-\tadd.w\tsl, sl, #1\n+\tadd.w\tip, r0, #1\n+\tcmp\tr5, r2\n+\tadd\tr0, r1\n+\tstr.w\tip, [r3, #-8]\n+\tstr.w\tr0, [r3, #-4]\n+\tbgt.n\t3b42 <__gridxc_mesh3d_MOD_setmeshdistr+0xd86>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tadd.w\tfp, fp, #8\n-\tcmp.w\tsl, #4\n-\tbne.n\t3d6a <__gridxc_mesh3d_MOD_setmeshdistr+0xdb6>\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tcmp\tr5, #0\n-\tble.w\t3f5e <__gridxc_mesh3d_MOD_setmeshdistr+0xfaa>\n-\tcmp\tr3, #0\n-\tble.w\t3f5e <__gridxc_mesh3d_MOD_setmeshdistr+0xfaa>\n-\tldr\tr2, [pc, #716]\t@ (40dc <__gridxc_mesh3d_MOD_setmeshdistr+0x1128>)\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tcmp\tr3, #4\n+\tbne.n\t3ad2 <__gridxc_mesh3d_MOD_setmeshdistr+0xd16>\n+\tcmp\tr4, #0\n+\tble.w\t3cc2 <__gridxc_mesh3d_MOD_setmeshdistr+0xf06>\n+\tcmp\tr7, #0\n+\tble.w\t3cc2 <__gridxc_mesh3d_MOD_setmeshdistr+0xf06>\n+\tldr\tr2, [pc, #428]\t@ (3d24 <__gridxc_mesh3d_MOD_setmeshdistr+0xf68>)\n \tmov.w\tr1, #364\t@ 0x16c\n-\tldr\tr0, [sp, #100]\t@ 0x64\n-\tmovs\tr6, #0\n+\tldr.w\tfp, [sp, #288]\t@ 0x120\n+\tmovs\tr5, #0\n \tadd\tr2, pc\n-\tldr.w\tfp, [sp, #344]\t@ 0x158\n-\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr6, [sp, #76]\t@ 0x4c\n \tmov\tr3, r8\n-\tstr\tr4, [sp, #72]\t@ 0x48\n+\tmov\tr6, r4\n \tmov\tr4, r9\n-\tmla\tsl, r1, r0, r2\n+\tstr\tr7, [sp, #68]\t@ 0x44\n+\tmla\tsl, r1, sl, r2\n \tmov\tr1, r9\n \tmov\tr2, r1\n \tmov\tr0, r4\n \tmov\tr1, r3\n \tmov.w\tr9, #0\n \tmov\tr3, r2\n-\tstr\tr5, [sp, #76]\t@ 0x4c\n-\tstr\tr4, [sp, #68]\t@ 0x44\n \tstr\tr6, [sp, #80]\t@ 0x50\n-\tstr\tr7, [sp, #84]\t@ 0x54\n+\tstr\tr4, [sp, #72]\t@ 0x48\n+\tstr\tr5, [sp, #84]\t@ 0x54\n \tcmp\tr1, #0\n-\tble.n\t3f34 <__gridxc_mesh3d_MOD_setmeshdistr+0xf80>\n+\tble.n\t3c9a <__gridxc_mesh3d_MOD_setmeshdistr+0xede>\n \tldrd\tr7, ip, [r0, #32]\n-\tstrd\tr9, r1, [sp, #52]\t@ 0x34\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstrd\tr9, r1, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #72]\t@ 0x48\n \tadd.w\tlr, r1, fp\n \tldrd\tr6, r5, [r3, #24]\n \tmov\tr9, r0\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr5, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr5, [sp, #52]\t@ 0x34\n \tldr.w\tr1, [sl, #308]\t@ 0x134\n \tldr.w\tr3, [sl, #340]\t@ 0x154\n \tldr.w\tr4, [sl, #328]\t@ 0x148\n \tadd\tr3, r1\n \tldr.w\tr1, [sl, #352]\t@ 0x160\n \tmla\tr3, r1, fp, r3\n \tldr.w\tr1, [sl, #332]\t@ 0x14c\n@@ -6144,15 +6047,15 @@\n \tmul.w\tr1, r3, r1\n \tldr.w\tr3, [sl, #304]\t@ 0x130\n \tstr\tr6, [r3, r1]\n \tldrd\tr0, r1, [r2, #40]\t@ 0x28\n \tadds\tr2, #24\n \tldr.w\tr5, [sl, #324]\t@ 0x144\n \tmul.w\tr4, r5, r4\n-\tldr\tr5, [sp, #48]\t@ 0x30\n+\tldr\tr5, [sp, #52]\t@ 0x34\n \tstr\tr5, [r3, r4]\n \tldr.w\tr4, [sl, #340]\t@ 0x154\n \tldr.w\tr3, [sl, #308]\t@ 0x134\n \tldr.w\tr8, [sl, #328]\t@ 0x148\n \tadd.w\tr3, r3, r4, lsl #1\n \tldr.w\tr4, [sl, #352]\t@ 0x160\n \tmla\tr4, r4, fp, r3\n@@ -6185,254 +6088,212 @@\n \tldr.w\tr4, [sl, #324]\t@ 0x144\n \tmul.w\tr3, r4, r3\n \tldr.w\tr4, [sl, #304]\t@ 0x130\n \tstr\tr0, [r4, r3]\n \tldr.w\tr3, [sl, #324]\t@ 0x144\n \tmul.w\tr8, r3, r8\n \tstr.w\tr1, [r4, r8]\n-\tbne.n\t3e5c <__gridxc_mesh3d_MOD_setmeshdistr+0xea8>\n+\tbne.n\t3bc2 <__gridxc_mesh3d_MOD_setmeshdistr+0xe06>\n \tmov\tr0, r9\n-\tldr.w\tr9, [sp, #52]\t@ 0x34\n-\tldrd\tr1, r3, [sp, #56]\t@ 0x38\n+\tldr.w\tr9, [sp, #56]\t@ 0x38\n+\tldrd\tr1, r3, [sp, #60]\t@ 0x3c\n \tadd.w\tr9, r9, #1\n-\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr2, [sp, #68]\t@ 0x44\n \tadds\tr0, #24\n \tcmp\tr9, r2\n-\tbne.w\t3e40 <__gridxc_mesh3d_MOD_setmeshdistr+0xe8c>\n-\tldr\tr6, [sp, #80]\t@ 0x50\n+\tbne.w\t3ba6 <__gridxc_mesh3d_MOD_setmeshdistr+0xdea>\n+\tldr\tr5, [sp, #84]\t@ 0x54\n \tmov\tr2, r3\n-\tldr\tr5, [sp, #76]\t@ 0x4c\n+\tldr\tr6, [sp, #80]\t@ 0x50\n \tmov\tr3, r1\n-\tadds\tr6, #1\n+\tadds\tr5, #1\n \tmov\tr1, r2\n-\tldr\tr4, [sp, #68]\t@ 0x44\n+\tldr\tr4, [sp, #72]\t@ 0x48\n \tadds\tr1, #24\n-\tldr\tr7, [sp, #84]\t@ 0x54\n-\tcmp\tr6, r5\n-\tbne.w\t3e2c <__gridxc_mesh3d_MOD_setmeshdistr+0xe78>\n+\tcmp\tr5, r6\n+\tbne.w\t3b94 <__gridxc_mesh3d_MOD_setmeshdistr+0xdd8>\n+\tldr\tr6, [sp, #76]\t@ 0x4c\n \tmov\tr9, r4\n-\tldr\tr4, [sp, #72]\t@ 0x48\n \tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.w\t31b4 <__gridxc_mesh3d_MOD_setmeshdistr+0x200>\n+\tb.w\t2fba <__gridxc_mesh3d_MOD_setmeshdistr+0x1fe>\n \tmovs\tr2, #0\n-\tb.n\t3dca <__gridxc_mesh3d_MOD_setmeshdistr+0xe16>\n-\tldr\tr1, [pc, #368]\t@ (40e0 <__gridxc_mesh3d_MOD_setmeshdistr+0x112c>)\n-\tmov\tr2, sl\n-\tldr\tr0, [pc, #368]\t@ (40e4 <__gridxc_mesh3d_MOD_setmeshdistr+0x1130>)\n+\tb.n\t3b32 <__gridxc_mesh3d_MOD_setmeshdistr+0xd76>\n+\tldr\tr1, [pc, #84]\t@ (3d28 <__gridxc_mesh3d_MOD_setmeshdistr+0xf6c>)\n+\tmov\tr2, r7\n+\tldr\tr0, [pc, #84]\t@ (3d2c <__gridxc_mesh3d_MOD_setmeshdistr+0xf70>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n \tmovs\tr0, #1\n-\tb.n\t3d44 <__gridxc_mesh3d_MOD_setmeshdistr+0xd90>\n-\tldr\tr2, [pc, #360]\t@ (40e8 <__gridxc_mesh3d_MOD_setmeshdistr+0x1134>)\n-\tmovs\tr1, #42\t@ 0x2a\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #356]\t@ (40ec <__gridxc_mesh3d_MOD_setmeshdistr+0x1138>)\n-\tldr\tr2, [r3, r2]\n-\tadd\tr0, pc\n-\tldr\tr2, [r2, #0]\n-\tblx\tr2\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tb.n\t3d0e <__gridxc_mesh3d_MOD_setmeshdistr+0xd5a>\n-\tcmp.w\tr8, #0\n-\tbeq.n\t3fdc <__gridxc_mesh3d_MOD_setmeshdistr+0x1028>\n-\tldr\tr3, [pc, #332]\t@ (40e8 <__gridxc_mesh3d_MOD_setmeshdistr+0x1134>)\n+\tb.n\t3ab0 <__gridxc_mesh3d_MOD_setmeshdistr+0xcf4>\n+\tcmp\tr7, #0\n+\tbeq.n\t3d5a <__gridxc_mesh3d_MOD_setmeshdistr+0xf9e>\n+\tldr\tr3, [pc, #52]\t@ (3d1c <__gridxc_mesh3d_MOD_setmeshdistr+0xf60>)\n \tmovs\tr1, #51\t@ 0x33\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [pc, #332]\t@ (40f0 <__gridxc_mesh3d_MOD_setmeshdistr+0x113c>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #64]\t@ (3d30 <__gridxc_mesh3d_MOD_setmeshdistr+0xf74>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldrd\tr3, r8, [r6, #4]\n-\tmul.w\tr2, r5, r3\n-\tb.n\t3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xd4c>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\torrs.w\tr3, r3, r8\n-\tbeq.n\t3ff4 <__gridxc_mesh3d_MOD_setmeshdistr+0x1040>\n-\tldr\tr3, [pc, #296]\t@ (40e8 <__gridxc_mesh3d_MOD_setmeshdistr+0x1134>)\n-\tadd\tr6, sp, #440\t@ 0x1b8\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tldrd\tr3, r8, [r5, #4]\n+\tmul.w\tr1, r4, r3\n+\tb.n\t3a5e <__gridxc_mesh3d_MOD_setmeshdistr+0xca2>\n+\t...\n+\t.word\t0x00000306\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000308\n+ R_ARM_REL32\t.LC38\n+\t.word\t0x00000304\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000002cc\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x000002ce\n+ R_ARM_REL32\t.LC35\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x000002a4\n+ R_ARM_REL32\t.LC46\n+\t.word\t0x0000019e\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x0000004e\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000050\n+ R_ARM_REL32\t.LC47\n+\t.word\t0x0000003c\n+ R_ARM_REL32\t.LC44\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\torrs\tr3, r7\n+\tbeq.n\t3d78 <__gridxc_mesh3d_MOD_setmeshdistr+0xfbc>\n+\tldr\tr3, [pc, #176]\t@ (3dec <__gridxc_mesh3d_MOD_setmeshdistr+0x1030>)\n+\tadd\tr5, sp, #380\t@ 0x17c\n+\tldr\tr2, [sp, #64]\t@ 0x40\n \tmovs\tr1, #62\t@ 0x3e\n-\tldr\tr0, [pc, #300]\t@ (40f4 <__gridxc_mesh3d_MOD_setmeshdistr+0x1140>)\n+\tldr\tr0, [pc, #172]\t@ (3df0 <__gridxc_mesh3d_MOD_setmeshdistr+0x1034>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr.w\tr8, [r6, #8]\n-\tldrd\tr5, r3, [r6]\n-\tmul.w\tr2, r5, r3\n-\tb.n\t3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xd4c>\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tadd\tr2, sp, #444\t@ 0x1bc\n-\tsdiv\tr1, r9, r5\n+\tldr.w\tr8, [r5, #8]\n+\tldrd\tr4, r3, [r5]\n+\tmul.w\tr1, r4, r3\n+\tb.n\t3a5e <__gridxc_mesh3d_MOD_setmeshdistr+0xca2>\n+\tmov\tr1, r4\n+\tmov\tr0, r9\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tmov\tr1, r0\n+\tadd\tr2, sp, #384\t@ 0x180\n \tadds\tr0, r3, #4\n-\tbl\t5dc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>\n-\tldrd\tr3, r8, [r6, #4]\n-\tmul.w\tr2, r3, r5\n-\tb.n\t3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xd4c>\n-\tadd\tr6, sp, #440\t@ 0x1b8\n-\tldr\tr0, [sp, #72]\t@ 0x48\n-\tmov\tr2, r6\n+\tbl\t5a4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>\n+\tldrd\tr3, r8, [r5, #4]\n+\tmul.w\tr1, r3, r4\n+\tb.n\t3a5e <__gridxc_mesh3d_MOD_setmeshdistr+0xca2>\n+\tadd\tr5, sp, #380\t@ 0x17c\n \tmov\tr1, r9\n-\tbl\t250 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n-\tldrd\tr5, r3, [r6]\n-\tldr.w\tr8, [r6, #8]\n-\tmul.w\tr2, r5, r3\n-\tb.n\t3d00 <__gridxc_mesh3d_MOD_setmeshdistr+0xd4c>\n+\tldr\tr0, [sp, #84]\t@ 0x54\n+\tmov\tr2, r5\n+\tbl\t208 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n+\tldrd\tr4, r3, [r5]\n+\tldr.w\tr8, [r5, #8]\n+\tmul.w\tr1, r4, r3\n+\tb.n\t3a5e <__gridxc_mesh3d_MOD_setmeshdistr+0xca2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tmov\tr4, r7\n-\tmov\tr7, r2\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tcmp\tr2, #0\n-\tble.w\t33a2 <__gridxc_mesh3d_MOD_setmeshdistr+0x3ee>\n-\tsubs\tr3, r2, #1\n-\tcmp\tr3, #2\n-\tbls.n\t40ba <__gridxc_mesh3d_MOD_setmeshdistr+0x1106>\n-\tlsrs\tr3, r2, #2\n-\tadd\tr0, sp, #488\t@ 0x1e8\n-\tvmov.i32\tq8, #-2147483648\t@ 0x80000000\n-\tmov\tr2, r0\n-\tadd.w\tr3, r0, r3, lsl #4\n-\tvld1.64\t{d18-d19}, [r2 :64]!\n-\tvmax.s32\tq8, q8, q9\n-\tcmp\tr3, r2\n-\tbne.n\t4032 <__gridxc_mesh3d_MOD_setmeshdistr+0x107e>\n-\tvmax.s32\td7, d16, d17\n-\tldr\tr2, [sp, #48]\t@ 0x30\n-\tlsls\tr1, r2, #30\n-\tvpmax.s32\td7, d7, d7\n-\tvmov\tr3, s14\n-\tbeq.n\t4084 <__gridxc_mesh3d_MOD_setmeshdistr+0x10d0>\n-\tbic.w\tr1, r2, #3\n-\tmov\tr6, r2\n-\tadds\tr1, #1\n-\tsubs\tr2, r1, #1\n-\tadds\tr5, r1, #1\n-\tldr.w\tr2, [r0, r2, lsl #2]\n-\tcmp\tr3, r2\n-\tit\tlt\n-\tmovlt\tr3, r2\n-\tcmp\tr6, r5\n-\tblt.n\t4084 <__gridxc_mesh3d_MOD_setmeshdistr+0x10d0>\n-\tldr.w\tr2, [r0, r1, lsl #2]\n-\tadds\tr1, #2\n-\tcmp\tr3, r2\n-\tit\tlt\n-\tmovlt\tr3, r2\n-\tcmp\tr6, r1\n-\tblt.n\t4084 <__gridxc_mesh3d_MOD_setmeshdistr+0x10d0>\n-\tldr.w\tr2, [r0, r5, lsl #2]\n-\tcmp\tr3, r2\n+\tldr\tr6, [sp, #52]\t@ 0x34\n+\tcmp\tr7, #0\n+\tble.w\t31c2 <__gridxc_mesh3d_MOD_setmeshdistr+0x406>\n+\tadd\tr2, sp, #424\t@ 0x1a8\n+\tmov.w\tr3, #2147483648\t@ 0x80000000\n+\tadd.w\tr1, r2, r7, lsl #2\n+\tldr.w\tr0, [r2, #4]!\n+\tcmp\tr3, r0\n \tit\tlt\n-\tmovlt\tr3, r2\n-\tbic.w\tr5, r3, r3, asr #31\n+\tmovlt\tr3, r0\n+\tcmp\tr1, r2\n+\tbne.n\t3da8 <__gridxc_mesh3d_MOD_setmeshdistr+0xfec>\n+\tbic.w\tr1, r3, r3, asr #31\n \tcmp\tr3, #0\n-\tble.w\t33a2 <__gridxc_mesh3d_MOD_setmeshdistr+0x3ee>\n-\tmvn.w\tr3, #2147483648\t@ 0x80000000\n-\tmovs\tr2, #6\n-\tudiv\tr3, r3, r5\n-\tmul.w\tr5, r2, r5\n-\tcmp\tr3, #5\n-\tble.w\t3cae <__gridxc_mesh3d_MOD_setmeshdistr+0xcfa>\n-\tcmp.w\tr5, #1073741824\t@ 0x40000000\n-\tbge.w\t3cae <__gridxc_mesh3d_MOD_setmeshdistr+0xcfa>\n-\tlsls\tr5, r5, #2\n-\tb.w\t33a4 <__gridxc_mesh3d_MOD_setmeshdistr+0x3f0>\n-\tmov\tr4, r7\n-\tstr.w\tr9, [sp, #48]\t@ 0x30\n+\tble.w\t31c2 <__gridxc_mesh3d_MOD_setmeshdistr+0x406>\n+\tmovs\tr4, #6\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr4, r1, r4\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, #5\n+\tble.w\t3a06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc4a>\n+\tcmp.w\tr4, #1073741824\t@ 0x40000000\n+\tbge.w\t3a06 <__gridxc_mesh3d_MOD_setmeshdistr+0xc4a>\n+\tlsls\tr4, r4, #2\n+\tb.w\t31c4 <__gridxc_mesh3d_MOD_setmeshdistr+0x408>\n+\tmov\tr2, r6\n+\tldr\tr6, [sp, #52]\t@ 0x34\n \tmov\tr7, r2\n-\tb.n\t4016 <__gridxc_mesh3d_MOD_setmeshdistr+0x1062>\n-\tmovs\tr1, #1\n-\tmov.w\tr3, #2147483648\t@ 0x80000000\n-\tadd\tr0, sp, #488\t@ 0x1e8\n-\tmov\tr6, r2\n-\tb.n\t4058 <__gridxc_mesh3d_MOD_setmeshdistr+0x10a4>\n+\tb.n\t3d98 <__gridxc_mesh3d_MOD_setmeshdistr+0xfdc>\n \tnop\n-\t.word\t0x00000426\n- R_ARM_REL32\t.LC1\n-\t.word\t0x00000428\n- R_ARM_REL32\t.LC38\n-\t.word\t0x0000041a\n- R_ARM_REL32\t.LC0\n-\t.word\t0x000003e0\n- R_ARM_REL32\t.LC1\n-\t.word\t0x000003e2\n- R_ARM_REL32\t.LC35\n-\t.word\t0x000002c0\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x0000016a\n- R_ARM_REL32\t.LC1\n-\t.word\t0x0000016c\n- R_ARM_REL32\t.LC47\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000015e\n- R_ARM_REL32\t.LC46\n-\t.word\t0x00000148\n- R_ARM_REL32\t.LC44\n-\t.word\t0x00000128\n+\t.word\t0x000000a6\n R_ARM_REL32\t.LC45\n \n-000040f8 <__gridxc_mesh3d_MOD_fftmeshdistr>:\n+00003df4 <__gridxc_mesh3d_MOD_fftmeshdistr>:\n __gridxc_mesh3d_MOD_fftmeshdistr():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3760]\t@ 0xeb0\n-\tldr.w\tr6, [pc, #1588]\t@ 4740 <__gridxc_mesh3d_MOD_fftmeshdistr+0x648>\n+\tldr.w\tr6, [pc, #1580]\t@ 4434 <__gridxc_mesh3d_MOD_fftmeshdistr+0x640>\n \tsub\tsp, #300\t@ 0x12c\n-\tldr.w\tr5, [pc, #1588]\t@ 4744 <__gridxc_mesh3d_MOD_fftmeshdistr+0x64c>\n+\tldr.w\tr5, [pc, #1580]\t@ 4438 <__gridxc_mesh3d_MOD_fftmeshdistr+0x644>\n \tadd\tr6, pc\n-\tldr.w\tr3, [pc, #1584]\t@ 4748 <__gridxc_mesh3d_MOD_fftmeshdistr+0x650>\n-\tldr.w\tr4, [pc, #1584]\t@ 474c <__gridxc_mesh3d_MOD_fftmeshdistr+0x654>\n+\tldr.w\tr3, [pc, #1576]\t@ 443c <__gridxc_mesh3d_MOD_fftmeshdistr+0x648>\n+\tldr.w\tr4, [pc, #1576]\t@ 4440 <__gridxc_mesh3d_MOD_fftmeshdistr+0x64c>\n \tadd\tr3, pc\n \tldr\tr5, [r6, r5]\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [sp, #292]\t@ 0x124\n \tmov.w\tr5, #0\n \tstr\tr0, [sp, #92]\t@ 0x5c\n \tstr\tr1, [sp, #84]\t@ 0x54\n \tmov\tr5, r2\n \tldr\tr1, [r3, r4]\n \tstr\tr1, [sp, #180]\t@ 0xb4\n \tldr\tr1, [r1, #0]\n \tcmp\tr1, #1\n-\tbeq.w\t45ce <__gridxc_mesh3d_MOD_fftmeshdistr+0x4d6>\n+\tbeq.w\t42ca <__gridxc_mesh3d_MOD_fftmeshdistr+0x4d6>\n \tldr\tr3, [sp, #84]\t@ 0x54\n \tldr\tr6, [r3, #0]\n \tcmp\tr6, #0\n-\tbgt.w\t4600 <__gridxc_mesh3d_MOD_fftmeshdistr+0x508>\n+\tbgt.w\t42f4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x500>\n \tldr\tr4, [sp, #92]\t@ 0x5c\n \tadd\tr3, sp, #220\t@ 0xdc\n \tmov\tr2, r3\n \tmov\tr6, r3\n \tmov\tr0, r4\n \tstr\tr3, [sp, #108]\t@ 0x6c\n-\tbl\t250 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n+\tbl\t208 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n \tmovs\tr3, #0\n \tadd\tr2, sp, #228\t@ 0xe4\n \tldr\tr0, [sp, #84]\t@ 0x54\n \tstr\tr2, [sp, #12]\n \tmov\tr1, r4\n \tadd\tr2, sp, #224\t@ 0xe0\n \tstr\tr6, [sp, #4]\n \tstr\tr2, [sp, #8]\n \tmov\tr2, r3\n \tstrd\tr3, r3, [sp, #20]\n \tstr\tr3, [sp, #16]\n \tstr\tr3, [sp, #0]\n-\tbl\t2fb4 <__gridxc_mesh3d_MOD_setmeshdistr>\n+\tbl\t2dbc <__gridxc_mesh3d_MOD_setmeshdistr>\n \tcmp\tr5, #0\n-\tbeq.w\t45e4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ec>\n+\tbeq.w\t42d8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4e4>\n \tldrd\tr0, r1, [sp, #220]\t@ 0xdc\n \tmovs\tr2, #1\n \tldr\tr3, [sp, #228]\t@ 0xe4\n \tstr\tr2, [sp, #252]\t@ 0xfc\n \tcmp\tr3, r1\n \tmov\tr2, r3\n \tit\tlt\n@@ -6441,62 +6302,62 @@\n \tcmp\tr2, r0\n \tmul.w\tr3, r1, r3\n \tit\tlt\n \tmovlt\tr2, r0\n \tstr\tr3, [sp, #244]\t@ 0xf4\n \tcmp\tr2, #0\n \tbic.w\tr7, r2, r2, asr #31\n-\tble.w\t471a <__gridxc_mesh3d_MOD_fftmeshdistr+0x622>\n+\tble.w\t440e <__gridxc_mesh3d_MOD_fftmeshdistr+0x61a>\n \tlsls\tr4, r7, #1\n \tmovw\tr3, #43690\t@ 0xaaaa\n \tmovt\tr3, #10922\t@ 0x2aaa\n \tcmp\tr4, r3\n-\tbgt.w\t4738 <__gridxc_mesh3d_MOD_fftmeshdistr+0x640>\n+\tbgt.w\t442c <__gridxc_mesh3d_MOD_fftmeshdistr+0x638>\n \tmovs\tr3, #6\n \tmul.w\tr9, r3, r7\n \tcmp.w\tr9, #1073741824\t@ 0x40000000\n-\tbge.w\t4738 <__gridxc_mesh3d_MOD_fftmeshdistr+0x640>\n+\tbge.w\t442c <__gridxc_mesh3d_MOD_fftmeshdistr+0x638>\n \tmvns\tr6, r4\n \tmov.w\tr8, r9, lsl #2\n \tmov\tr0, r8\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tstr\tr0, [sp, #88]\t@ 0x58\n \tcmp\tr0, #0\n-\tbeq.w\t472a <__gridxc_mesh3d_MOD_fftmeshdistr+0x632>\n+\tbeq.w\t441e <__gridxc_mesh3d_MOD_fftmeshdistr+0x62a>\n \tadd.w\tr3, r9, r6\n \tlsls\tr4, r4, #2\n \tadd.w\tr6, r6, r7, lsl #2\n \tmovw\tlr, #21846\t@ 0x5556\n \tmovt\tlr, #21845\t@ 0x5555\n \tadd.w\tr3, r0, r3, lsl #2\n \tstr\tr3, [sp, #172]\t@ 0xac\n \tmov\tr3, r0\n \tadd\tr3, r4\n \tstr\tr3, [sp, #116]\t@ 0x74\n \tadd\tr3, r4\n \tstr\tr3, [sp, #124]\t@ 0x7c\n-\tldr.w\tr3, [pc, #1360]\t@ 4750 <__gridxc_mesh3d_MOD_fftmeshdistr+0x658>\n+\tldr.w\tr3, [pc, #1352]\t@ 4444 <__gridxc_mesh3d_MOD_fftmeshdistr+0x650>\n \tmov\tr7, lr\n \tadd.w\tr2, r0, r6, lsl #2\n \tstr\tr5, [sp, #132]\t@ 0x84\n \tadd\tr3, pc\n \tstr\tr2, [sp, #76]\t@ 0x4c\n \tstr\tr3, [sp, #188]\t@ 0xbc\n \tadd\tr3, sp, #244\t@ 0xf4\n \tstr\tr3, [sp, #104]\t@ 0x68\n \tmovs\tr3, #0\n \tstr\tr3, [sp, #168]\t@ 0xa8\n \tldr\tr3, [sp, #168]\t@ 0xa8\n \tldr\tr0, [sp, #132]\t@ 0x84\n \trsb\tsl, r3, #1\n-\tbl\t2b24 <__gridxc_mesh3d_MOD_freemeshdistr>\n+\tbl\t292c <__gridxc_mesh3d_MOD_freemeshdistr>\n \tmovw\tr3, #43691\t@ 0xaaab\n \tmovt\tr3, #43690\t@ 0xaaaa\n \tumull\tr2, r3, r3, sl\n \tldr\tr2, [sp, #180]\t@ 0xb4\n \tbic.w\tr1, r3, #1\n \tadd.w\tr3, r1, r3, lsr #1\n \tldr\tr2, [r2, #0]\n@@ -6507,50 +6368,50 @@\n \teor.w\tr4, r9, r3\n \tumull\tr1, r4, r7, r4\n \teor.w\tr4, r4, r3\n \tadd.w\tr4, r4, r4, lsl #1\n \tsub.w\tr4, r9, r4\n \tadd.w\tr3, r4, #1\n \tstr\tr3, [sp, #48]\t@ 0x30\n-\tbeq.w\t45c2 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ca>\n+\tbeq.w\t42be <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ca>\n \tldr\tr6, [sp, #132]\t@ 0x84\n-\tldr.w\tr2, [pc, #1256]\t@ 4754 <__gridxc_mesh3d_MOD_fftmeshdistr+0x65c>\n+\tldr.w\tr2, [pc, #1248]\t@ 4448 <__gridxc_mesh3d_MOD_fftmeshdistr+0x654>\n \tmov\tr0, r6\n \tldr\tr3, [sp, #180]\t@ 0xb4\n \tldr\tr1, [sp, #92]\t@ 0x5c\n \tadd\tr2, pc\n \tbl\t40 <__gridxc_mesh3d_MOD_initdistr.part.0>\n \tldr\tr0, [r6, #0]\n \tcmp\tr0, #0\n-\tbeq.w\t45c8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4d0>\n-\tble.n\t42ae <__gridxc_mesh3d_MOD_fftmeshdistr+0x1b6>\n-\tldr.w\tr2, [pc, #1236]\t@ 4758 <__gridxc_mesh3d_MOD_fftmeshdistr+0x660>\n+\tbeq.w\t42c4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4d0>\n+\tble.n\t3faa <__gridxc_mesh3d_MOD_fftmeshdistr+0x1b6>\n+\tldr.w\tr2, [pc, #1228]\t@ 444c <__gridxc_mesh3d_MOD_fftmeshdistr+0x658>\n \tmovs\tr6, #0\n \tadd\tr2, pc\n \tadds\tr2, #80\t@ 0x50\n \tsub.w\tr3, r2, #80\t@ 0x50\n-\tb.n\t4296 <__gridxc_mesh3d_MOD_fftmeshdistr+0x19e>\n+\tb.n\t3f92 <__gridxc_mesh3d_MOD_fftmeshdistr+0x19e>\n \tcmp\tr2, r3\n-\tbeq.n\t42a4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ac>\n+\tbeq.n\t3fa0 <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ac>\n \tldr.w\tr1, [r3, #4]!\n \tcmp\tr0, r1\n-\tbne.n\t4292 <__gridxc_mesh3d_MOD_fftmeshdistr+0x19a>\n+\tbne.n\t3f8e <__gridxc_mesh3d_MOD_fftmeshdistr+0x19a>\n \tldr.w\tr3, [r2, #-80]\n-\tcbnz\tr3, 42b2 <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ba>\n+\tcbnz\tr3, 3fae <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ba>\n \tadds\tr6, #1\n \tadd.w\tr2, r2, #364\t@ 0x16c\n \tcmp\tr6, #20\n-\tbne.n\t428c <__gridxc_mesh3d_MOD_fftmeshdistr+0x194>\n+\tbne.n\t3f88 <__gridxc_mesh3d_MOD_fftmeshdistr+0x194>\n \tmvn.w\tr6, #1\n \tmov.w\tr8, r4, lsl #2\n \tadd.w\tr3, r8, #296\t@ 0x128\n \tadd\tr3, sp\n \tldr.w\tip, [r3, #-76]\n \tcmp.w\tip, #0\n-\tble.w\t4572 <__gridxc_mesh3d_MOD_fftmeshdistr+0x47a>\n+\tble.w\t426e <__gridxc_mesh3d_MOD_fftmeshdistr+0x47a>\n \tadd\tr3, sp, #296\t@ 0x128\n \tadd\tr0, sp, #268\t@ 0x10c\n \tadd.w\tlr, r3, r5, lsl #2\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tmov.w\tr1, r9, lsl #1\n \tlsls\tr2, r3, #1\n \tadd.w\tr3, r0, r5, lsl #3\n@@ -6560,15 +6421,15 @@\n \tsubs\tr5, r1, #1\n \tldr.w\tr3, [lr, #-76]\n \tsubs\tr4, r2, #1\n \tsubs\tr1, #2\n \tsubs\tr2, #2\n \tcmp\tr3, #0\n \tstr\tr3, [sp, #136]\t@ 0x88\n-\tble.w\t4572 <__gridxc_mesh3d_MOD_fftmeshdistr+0x47a>\n+\tble.w\t426e <__gridxc_mesh3d_MOD_fftmeshdistr+0x47a>\n \tlsls\tr3, r1, #2\n \tstr\tr3, [sp, #148]\t@ 0x94\n \tlsls\tr3, r4, #2\n \tstr\tr3, [sp, #152]\t@ 0x98\n \tlsls\tr3, r2, #2\n \tstr\tr3, [sp, #156]\t@ 0x9c\n \tldr\tr3, [sp, #188]\t@ 0xbc\n@@ -6609,15 +6470,15 @@\n \tstr\tr0, [sp, #176]\t@ 0xb0\n \tstr.w\tr8, [sp, #212]\t@ 0xd4\n \tldr\tr3, [sp, #84]\t@ 0x54\n \tmov\tr6, r5\n \tstr\tr5, [sp, #216]\t@ 0xd8\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tbne.w\t45b6 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4be>\n+\tbne.w\t42b2 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4be>\n \tldr\tr3, [r7, #0]\n \tstr\tr1, [sp, #268]\t@ 0x10c\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #272]\t@ 0x110\n \tldr\tr3, [r7, #4]\n \tstr\tr1, [sp, #276]\t@ 0x114\n \tsubs\tr3, #1\n@@ -6650,34 +6511,34 @@\n \tldr\tr3, [sp, #128]\t@ 0x80\n \tldr\tr4, [r7, r3]\n \tldr\tr1, [r2, r3]\n \tmovs\tr3, #1\n \tldrd\tr2, r0, [sp, #160]\t@ 0xa0\n \tstr\tr4, [sp, #256]\t@ 0x100\n \tstr\tr3, [sp, #232]\t@ 0xe8\n-\tbl\t5dc <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>\n+\tbl\t5a4 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.0.isra.0>\n \tldr\tr2, [sp, #88]\t@ 0x58\n \tsubs\tr3, r4, #1\n \tldr\tr1, [sp, #236]\t@ 0xec\n \tmovs\tr4, #0\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tstr\tr3, [r2, #4]\n \tmov\tr9, r1\n \tstr\tr4, [r2, #0]\n \tldrd\tr0, r2, [sp, #112]\t@ 0x70\n-\tbl\ted8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>\n+\tbl\td24 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>\n \tldr.w\tr8, [sp, #240]\t@ 0xf0\n \tldrd\tr0, r2, [sp, #120]\t@ 0x78\n \tmov\tr1, r8\n-\tbl\ted8 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>\n+\tbl\td24 <__gridxc_mesh3d_MOD_dividebox1d.constprop.0.isra.0>\n \tcmp\tr8, r4\n-\tble.w\t4544 <__gridxc_mesh3d_MOD_fftmeshdistr+0x44c>\n+\tble.w\t4240 <__gridxc_mesh3d_MOD_fftmeshdistr+0x44c>\n \tmov\tr2, r9\n \tcmp\tr2, #0\n-\tble.w\t4544 <__gridxc_mesh3d_MOD_fftmeshdistr+0x44c>\n+\tble.w\t4240 <__gridxc_mesh3d_MOD_fftmeshdistr+0x44c>\n \tldr\tr3, [sp, #104]\t@ 0x68\n \tmov\tip, r2\n \tstrd\tr5, r7, [sp, #96]\t@ 0x60\n \tldr.w\tlr, [r3]\n \tadd.w\tr3, r9, #4294967295\t@ 0xffffffff\n \tmul.w\tr9, lr, r3\n \tldr\tr3, [sp, #172]\t@ 0xac\n@@ -6755,243 +6616,242 @@\n \tmul.w\tr4, r3, r4\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tstr\tr3, [r6, r4]\n \tldr.w\tr3, [fp, #324]\t@ 0x144\n \tmul.w\tr5, r3, r5\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [r6, r5]\n-\tbne.n\t4438 <__gridxc_mesh3d_MOD_fftmeshdistr+0x340>\n+\tbne.n\t4134 <__gridxc_mesh3d_MOD_fftmeshdistr+0x340>\n \tldrd\tr6, r4, [sp, #56]\t@ 0x38\n \tldr\tr1, [sp, #72]\t@ 0x48\n \tadd.w\tr2, lr, r6\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tadds\tr6, r2, r1\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tadds\tr4, #1\n \tadds\tr3, #8\n \tcmp\tr2, r4\n-\tbne.w\t4424 <__gridxc_mesh3d_MOD_fftmeshdistr+0x32c>\n+\tbne.w\t4120 <__gridxc_mesh3d_MOD_fftmeshdistr+0x32c>\n \tldrd\tr5, r7, [sp, #96]\t@ 0x60\n \tldr\tr2, [sp, #140]\t@ 0x8c\n \tldr\tr3, [sp, #80]\t@ 0x50\n \tadd\tr5, r2\n \tldr\tr2, [sp, #136]\t@ 0x88\n \tadds\tr3, #1\n \tstr\tr3, [sp, #80]\t@ 0x50\n \tcmp\tr3, r2\n-\tbne.w\t4364 <__gridxc_mesh3d_MOD_fftmeshdistr+0x26c>\n+\tbne.w\t4060 <__gridxc_mesh3d_MOD_fftmeshdistr+0x26c>\n \tldrd\tr2, r7, [sp, #196]\t@ 0xc4\n \tldr.w\tr9, [sp, #52]\t@ 0x34\n \tadds\tr2, #1\n \tldr\tr0, [sp, #176]\t@ 0xb0\n \tldrd\tr6, r5, [sp, #204]\t@ 0xcc\n \tcmp\tr7, r2\n \tldr.w\tr8, [sp, #212]\t@ 0xd4\n-\tbne.w\t432a <__gridxc_mesh3d_MOD_fftmeshdistr+0x232>\n+\tbne.w\t4026 <__gridxc_mesh3d_MOD_fftmeshdistr+0x232>\n \tldr\tr7, [sp, #192]\t@ 0xc0\n \tldr\tr4, [sp, #132]\t@ 0x84\n \tmov\tr0, r4\n-\tbl\t2cf8 <__gridxc_mesh3d_MOD_reducedistr>\n+\tbl\t2b00 <__gridxc_mesh3d_MOD_reducedistr>\n \tldr\tr3, [sp, #168]\t@ 0xa8\n \tmov\tr2, r4\n \tadds\tr2, #4\n \tstr\tr2, [sp, #132]\t@ 0x84\n \tldr\tr2, [sp, #104]\t@ 0x68\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #168]\t@ 0xa8\n \tadds\tr3, #3\n \tadd.w\tr2, r2, #4\n \tstr\tr2, [sp, #104]\t@ 0x68\n-\tbne.w\t4216 <__gridxc_mesh3d_MOD_fftmeshdistr+0x11e>\n-\tldr\tr2, [pc, #452]\t@ (475c <__gridxc_mesh3d_MOD_fftmeshdistr+0x664>)\n-\tldr\tr3, [pc, #428]\t@ (4744 <__gridxc_mesh3d_MOD_fftmeshdistr+0x64c>)\n+\tbne.w\t3f12 <__gridxc_mesh3d_MOD_fftmeshdistr+0x11e>\n+\tldr\tr2, [pc, #444]\t@ (4450 <__gridxc_mesh3d_MOD_fftmeshdistr+0x65c>)\n+\tldr\tr3, [pc, #420]\t@ (4438 <__gridxc_mesh3d_MOD_fftmeshdistr+0x644>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #292]\t@ 0x124\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4726 <__gridxc_mesh3d_MOD_fftmeshdistr+0x62e>\n+\tbne.w\t441a <__gridxc_mesh3d_MOD_fftmeshdistr+0x626>\n \tldr\tr0, [sp, #88]\t@ 0x58\n \tadd\tsp, #300\t@ 0x12c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n \tldr\tr3, [sp, #176]\t@ 0xb0\n \tmov\tr0, r7\n \tldr\tr2, [sp, #184]\t@ 0xb8\n-\tbl\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n-\tb.n\t438a <__gridxc_mesh3d_MOD_fftmeshdistr+0x292>\n+\tbl\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tb.n\t4086 <__gridxc_mesh3d_MOD_fftmeshdistr+0x292>\n \tldr\tr2, [sp, #132]\t@ 0x84\n \tmovs\tr3, #0\n \tstr\tr3, [r2, #0]\n \tmov.w\tr6, #4294967295\t@ 0xffffffff\n-\tb.n\t42b2 <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ba>\n+\tb.n\t3fae <__gridxc_mesh3d_MOD_fftmeshdistr+0x1ba>\n \tldr\tr2, [sp, #84]\t@ 0x54\n \tmovs\tr3, #0\n \tstr\tr3, [r2, #0]\n-\tcbz\tr5, 45e4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ec>\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tadds\tr3, r5, #4\n-\tvst1.8\t{d16}, [r5]\n-\tvst1.8\t{d16}, [r3]\n-\tldr\tr2, [pc, #376]\t@ (4760 <__gridxc_mesh3d_MOD_fftmeshdistr+0x668>)\n-\tldr\tr3, [pc, #348]\t@ (4744 <__gridxc_mesh3d_MOD_fftmeshdistr+0x64c>)\n+\tcbz\tr5, 42d8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4e4>\n+\tstr\tr3, [r5, #0]\n+\tstr\tr3, [r5, #4]\n+\tstr\tr3, [r5, #8]\n+\tldr\tr2, [pc, #376]\t@ (4454 <__gridxc_mesh3d_MOD_fftmeshdistr+0x660>)\n+\tldr\tr3, [pc, #348]\t@ (4438 <__gridxc_mesh3d_MOD_fftmeshdistr+0x644>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #292]\t@ 0x124\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4726 <__gridxc_mesh3d_MOD_fftmeshdistr+0x62e>\n+\tbne.w\t441a <__gridxc_mesh3d_MOD_fftmeshdistr+0x626>\n \tadd\tsp, #300\t@ 0x12c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [pc, #352]\t@ (4764 <__gridxc_mesh3d_MOD_fftmeshdistr+0x66c>)\n+\tldr\tr2, [pc, #352]\t@ (4458 <__gridxc_mesh3d_MOD_fftmeshdistr+0x664>)\n \tmovs\tr3, #1\n \tadd\tr2, pc\n \tadds\tr2, #80\t@ 0x50\n \tmov\tr4, r2\n \tsub.w\tr0, r4, #80\t@ 0x50\n-\tb.n\t4614 <__gridxc_mesh3d_MOD_fftmeshdistr+0x51c>\n+\tb.n\t4308 <__gridxc_mesh3d_MOD_fftmeshdistr+0x514>\n \tcmp\tr4, r0\n-\tbeq.n\t4622 <__gridxc_mesh3d_MOD_fftmeshdistr+0x52a>\n+\tbeq.n\t4316 <__gridxc_mesh3d_MOD_fftmeshdistr+0x522>\n \tldr.w\tr7, [r0, #4]!\n \tcmp\tr6, r7\n-\tbne.n\t4610 <__gridxc_mesh3d_MOD_fftmeshdistr+0x518>\n+\tbne.n\t4304 <__gridxc_mesh3d_MOD_fftmeshdistr+0x510>\n \tldr.w\tr0, [r4, #-80]\n-\tcbnz\tr0, 462e <__gridxc_mesh3d_MOD_fftmeshdistr+0x536>\n+\tcbnz\tr0, 4322 <__gridxc_mesh3d_MOD_fftmeshdistr+0x52e>\n \tadds\tr3, #1\n \tadd.w\tr4, r4, #364\t@ 0x16c\n \tcmp\tr3, #21\n-\tbne.n\t460a <__gridxc_mesh3d_MOD_fftmeshdistr+0x512>\n-\tb.n\t4144 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n+\tbne.n\t42fe <__gridxc_mesh3d_MOD_fftmeshdistr+0x50a>\n+\tb.n\t3e40 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n \tsubs\tr3, #1\n \tmov.w\tr0, #364\t@ 0x16c\n-\tldr\tr6, [pc, #304]\t@ (4768 <__gridxc_mesh3d_MOD_fftmeshdistr+0x670>)\n+\tldr\tr6, [pc, #304]\t@ (445c <__gridxc_mesh3d_MOD_fftmeshdistr+0x668>)\n \tmul.w\tr0, r3, r0\n \tadd\tr6, pc\n \tldr\tr3, [sp, #92]\t@ 0x5c\n \tadds\tr4, r6, r0\n \tldr.w\tr9, [r3]\n \tldr\tr3, [r4, #92]\t@ 0x5c\n \tcmp\tr3, r9\n-\tbne.w\t4144 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n+\tbne.w\t3e40 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n \tldr\tr3, [sp, #92]\t@ 0x5c\n \tldr\tr7, [r3, #4]\n \tldr\tr3, [r4, #96]\t@ 0x60\n \tcmp\tr3, r7\n-\tbne.w\t4144 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n+\tbne.w\t3e40 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n \tldr\tr3, [r4, #100]\t@ 0x64\n \tldr\tr4, [sp, #92]\t@ 0x5c\n \tldr.w\tip, [r4, #8]\n \tcmp\tr3, ip\n-\tbne.w\t4144 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n+\tbne.w\t3e40 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n \tldr\tr4, [r6, r0]\n \tcmp\tr4, #0\n-\tbeq.w\t4144 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n+\tbeq.w\t3e40 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4c>\n \tcmp\tr5, #0\n-\tbeq.n\t45e4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ec>\n+\tbeq.n\t42d8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4e4>\n \tsubs\tr6, r5, #4\n \tadd.w\tsl, r5, #8\n \tldr.w\tr8, [r6, #4]!\n \tcmp.w\tr8, #0\n-\tble.n\t46a8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5b0>\n+\tble.n\t439c <__gridxc_mesh3d_MOD_fftmeshdistr+0x5a8>\n \tmov\tlr, r2\n \tmovs\tr3, #1\n \tsub.w\tr0, lr, #80\t@ 0x50\n-\tb.n\t4690 <__gridxc_mesh3d_MOD_fftmeshdistr+0x598>\n+\tb.n\t4384 <__gridxc_mesh3d_MOD_fftmeshdistr+0x590>\n \tcmp\tlr, r0\n-\tbeq.n\t469e <__gridxc_mesh3d_MOD_fftmeshdistr+0x5a6>\n+\tbeq.n\t4392 <__gridxc_mesh3d_MOD_fftmeshdistr+0x59e>\n \tldr.w\tfp, [r0, #4]!\n \tcmp\tr8, fp\n-\tbne.n\t468c <__gridxc_mesh3d_MOD_fftmeshdistr+0x594>\n+\tbne.n\t4380 <__gridxc_mesh3d_MOD_fftmeshdistr+0x58c>\n \tldr.w\tr0, [lr, #-80]\n-\tcbnz\tr0, 46e2 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5ea>\n+\tcbnz\tr0, 43d6 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5e2>\n \tadds\tr3, #1\n \tadd.w\tlr, lr, #364\t@ 0x16c\n \tcmp\tr3, #21\n-\tbne.n\t4686 <__gridxc_mesh3d_MOD_fftmeshdistr+0x58e>\n+\tbne.n\t437a <__gridxc_mesh3d_MOD_fftmeshdistr+0x586>\n \tmovs\tr4, #0\n \tcmp\tsl, r6\n-\tbne.n\t4678 <__gridxc_mesh3d_MOD_fftmeshdistr+0x580>\n+\tbne.n\t436c <__gridxc_mesh3d_MOD_fftmeshdistr+0x578>\n \tcmp\tr4, #0\n-\tbne.n\t45e4 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4ec>\n+\tbne.n\t42d8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x4e4>\n \tldr\tr6, [sp, #92]\t@ 0x5c\n \tadd\tr3, sp, #220\t@ 0xdc\n \tmov\tr2, r3\n \tmov\tr7, r3\n \tmov\tr0, r6\n \tstr\tr3, [sp, #108]\t@ 0x6c\n-\tbl\t250 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n+\tbl\t208 <__gridxc_mesh3d_MOD_optimizenodedistr.constprop.1.isra.0>\n \tadd\tr3, sp, #228\t@ 0xe4\n \tldr\tr0, [sp, #84]\t@ 0x54\n \tmov\tr2, r4\n \tstr\tr3, [sp, #12]\n \tmov\tr1, r6\n \tadd\tr3, sp, #224\t@ 0xe0\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr3, [sp, #8]\n \tmov\tr3, r4\n \tstr\tr4, [sp, #16]\n \tstrd\tr4, r7, [sp]\n-\tbl\t2fb4 <__gridxc_mesh3d_MOD_setmeshdistr>\n-\tb.n\t4178 <__gridxc_mesh3d_MOD_fftmeshdistr+0x80>\n+\tbl\t2dbc <__gridxc_mesh3d_MOD_setmeshdistr>\n+\tb.n\t3e74 <__gridxc_mesh3d_MOD_fftmeshdistr+0x80>\n \tmov.w\tr0, #364\t@ 0x16c\n \tsubs\tr3, #1\n-\tldr.w\tr8, [pc, #128]\t@ 476c <__gridxc_mesh3d_MOD_fftmeshdistr+0x674>\n+\tldr.w\tr8, [pc, #128]\t@ 4460 <__gridxc_mesh3d_MOD_fftmeshdistr+0x66c>\n \tmul.w\tr3, r0, r3\n \tadd\tr8, pc\n \tadd.w\tlr, r8, r3\n \tldr.w\tr0, [lr, #92]\t@ 0x5c\n \tcmp\tr0, r9\n-\tbne.n\t46a8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5b0>\n+\tbne.n\t439c <__gridxc_mesh3d_MOD_fftmeshdistr+0x5a8>\n \tldr.w\tr0, [lr, #96]\t@ 0x60\n \tcmp\tr0, r7\n-\tbne.n\t46a8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5b0>\n+\tbne.n\t439c <__gridxc_mesh3d_MOD_fftmeshdistr+0x5a8>\n \tldr.w\tr0, [lr, #100]\t@ 0x64\n \tcmp\tr0, ip\n-\tbne.n\t46a8 <__gridxc_mesh3d_MOD_fftmeshdistr+0x5b0>\n+\tbne.n\t439c <__gridxc_mesh3d_MOD_fftmeshdistr+0x5a8>\n \tldr.w\tr3, [r8, r3]\n \tcmp\tr3, #0\n \tit\teq\n \tmoveq\tr4, #0\n-\tb.n\t46aa <__gridxc_mesh3d_MOD_fftmeshdistr+0x5b2>\n+\tb.n\t439e <__gridxc_mesh3d_MOD_fftmeshdistr+0x5aa>\n \tmovs\tr4, #0\n \tmov.w\tr6, #4294967295\t@ 0xffffffff\n \tmov\tr9, r4\n \tmov\tr8, r4\n-\tb.n\t41c6 <__gridxc_mesh3d_MOD_fftmeshdistr+0xce>\n+\tb.n\t3ec2 <__gridxc_mesh3d_MOD_fftmeshdistr+0xce>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr1, [pc, #68]\t@ (4770 <__gridxc_mesh3d_MOD_fftmeshdistr+0x678>)\n+\tldr\tr1, [pc, #68]\t@ (4464 <__gridxc_mesh3d_MOD_fftmeshdistr+0x670>)\n \tmov\tr2, r8\n-\tldr\tr0, [pc, #68]\t@ (4774 <__gridxc_mesh3d_MOD_fftmeshdistr+0x67c>)\n+\tldr\tr0, [pc, #68]\t@ (4468 <__gridxc_mesh3d_MOD_fftmeshdistr+0x674>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #60]\t@ (4778 <__gridxc_mesh3d_MOD_fftmeshdistr+0x680>)\n+\tldr\tr0, [pc, #60]\t@ (446c <__gridxc_mesh3d_MOD_fftmeshdistr+0x678>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\t.word\t0x0000062a\n+\t.word\t0x00000622\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000628\n+\t.word\t0x00000620\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n-\t.word\t0x00000544\n+\t.word\t0x0000053c\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000004de\n+\t.word\t0x000004d6\n R_ARM_REL32\t.rodata\n-\t.word\t0x000004cc\n+\t.word\t0x000004c4\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000001c0\n+\t.word\t0x000001b8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000174\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x0000015c\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x0000012a\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n@@ -7000,755 +6860,732 @@\n \t.word\t0x0000003c\n R_ARM_REL32\t.LC1\n \t.word\t0x0000003e\n R_ARM_REL32\t.LC49\n \t.word\t0x0000003a\n R_ARM_REL32\t.LC0\n \n-0000477c <__gridxc_mesh3d_MOD_associatemeshtask>:\n+00004470 <__gridxc_mesh3d_MOD_associatemeshtask>:\n __gridxc_mesh3d_MOD_associatemeshtask.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3984]\t@ 0xf90\n-\tldr.w\tr4, [pc, #1404]\t@ 4d10 <__gridxc_mesh3d_MOD_associatemeshtask+0x594>\n+\tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n+\tldr.w\tr4, [pc, #1656]\t@ 4afc <__gridxc_mesh3d_MOD_associatemeshtask+0x68c>\n \tsub\tsp, #44\t@ 0x2c\n-\tldr.w\tr3, [pc, #1404]\t@ 4d14 <__gridxc_mesh3d_MOD_associatemeshtask+0x598>\n+\tldr.w\tr3, [pc, #1656]\t@ 4b00 <__gridxc_mesh3d_MOD_associatemeshtask+0x690>\n \tadd\tr4, pc\n-\tstr\tr4, [sp, #8]\n-\tstrd\tr0, r2, [sp]\n-\tldr.w\tr9, [r4, r3]\n-\tldr.w\tr3, [r9]\n+\tstr\tr4, [sp, #12]\n+\tstrd\tr0, r2, [sp, #4]\n+\tldr\tr7, [r4, r3]\n+\tldr\tr3, [r7, #0]\n \tcmp\tr3, #1\n-\tble.w\t4ccc <__gridxc_mesh3d_MOD_associatemeshtask+0x550>\n+\tble.w\t498c <__gridxc_mesh3d_MOD_associatemeshtask+0x51c>\n \tldr\tr5, [r1, #0]\n \tcmp\tr5, #0\n-\tbne.w\t4cd6 <__gridxc_mesh3d_MOD_associatemeshtask+0x55a>\n-\tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #4]\n-\tcbz\tr3, 482c <__gridxc_mesh3d_MOD_associatemeshtask+0xb0>\n-\tldr\tr6, [r3, #0]\n-\tmovw\tr3, #65172\t@ 0xfe94\n-\tmovt\tr3, #65535\t@ 0xffff\n-\tcmp\tr6, #0\n-\tbeq.n\t4822 <__gridxc_mesh3d_MOD_associatemeshtask+0xa6>\n-\tble.n\t4802 <__gridxc_mesh3d_MOD_associatemeshtask+0x86>\n-\tldr.w\tr1, [pc, #1348]\t@ 4d18 <__gridxc_mesh3d_MOD_associatemeshtask+0x59c>\n+\titt\teq\n+\tmoveq.w\tr3, #4294967295\t@ 0xffffffff\n+\tstreq\tr3, [sp, #20]\n+\tbeq.n\t44fa <__gridxc_mesh3d_MOD_associatemeshtask+0x8a>\n+\tble.n\t44dc <__gridxc_mesh3d_MOD_associatemeshtask+0x6c>\n+\tldr.w\tr1, [pc, #1620]\t@ 4b04 <__gridxc_mesh3d_MOD_associatemeshtask+0x694>\n \tmovs\tr0, #1\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t47e6 <__gridxc_mesh3d_MOD_associatemeshtask+0x6a>\n-\tcmp\tr1, r3\n-\tbeq.n\t47f8 <__gridxc_mesh3d_MOD_associatemeshtask+0x7c>\n+\tb.n\t44c0 <__gridxc_mesh3d_MOD_associatemeshtask+0x50>\n+\tcmp\tr3, r1\n+\tbeq.n\t44d2 <__gridxc_mesh3d_MOD_associatemeshtask+0x62>\n \tldr.w\tr2, [r3, #4]!\n-\tcmp\tr6, r2\n-\tbne.n\t47e2 <__gridxc_mesh3d_MOD_associatemeshtask+0x66>\n+\tcmp\tr5, r2\n+\tbne.n\t44bc <__gridxc_mesh3d_MOD_associatemeshtask+0x4c>\n \tldr.w\tr3, [r1, #-80]\n \tcmp\tr3, #0\n-\tbne.w\t4e4c <__gridxc_mesh3d_MOD_associatemeshtask+0x6d0>\n+\tbne.w\t4a62 <__gridxc_mesh3d_MOD_associatemeshtask+0x5f2>\n \tadds\tr0, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr0, #21\n-\tbne.n\t47dc <__gridxc_mesh3d_MOD_associatemeshtask+0x60>\n-\tldr.w\tr3, [pc, #1304]\t@ 4d1c <__gridxc_mesh3d_MOD_associatemeshtask+0x5a0>\n+\tbne.n\t44b6 <__gridxc_mesh3d_MOD_associatemeshtask+0x46>\n+\tldr.w\tr3, [pc, #1576]\t@ 4b08 <__gridxc_mesh3d_MOD_associatemeshtask+0x698>\n \tmovs\tr1, #45\t@ 0x2d\n-\tldr\tr2, [sp, #8]\n-\tmov.w\tr6, #4294967295\t@ 0xffffffff\n-\tldr.w\tr0, [pc, #1296]\t@ 4d20 <__gridxc_mesh3d_MOD_associatemeshtask+0x5a4>\n+\tldr\tr2, [sp, #12]\n+\tmov.w\tr5, #4294967295\t@ 0xffffffff\n+\tldr.w\tr0, [pc, #1568]\t@ 4b0c <__gridxc_mesh3d_MOD_associatemeshtask+0x69c>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tmovw\tr3, #64808\t@ 0xfd28\n-\tmovt\tr3, #65535\t@ 0xffff\n-\tldr.w\tr2, [pc, #1280]\t@ 4d24 <__gridxc_mesh3d_MOD_associatemeshtask+0x5a8>\n+\tmvn.w\tr3, #1\n+\tstr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #8]\n+\tcbz\tr3, 451a <__gridxc_mesh3d_MOD_associatemeshtask+0xaa>\n+\tldr\tr6, [r3, #0]\n+\tcmp\tr6, #0\n+\titt\teq\n+\tmovweq\tr3, #65172\t@ 0xfe94\n+\tmovteq\tr3, #65535\t@ 0xffff\n+\tbne.w\t4992 <__gridxc_mesh3d_MOD_associatemeshtask+0x522>\n+\tldr.w\tr2, [pc, #1532]\t@ 4b10 <__gridxc_mesh3d_MOD_associatemeshtask+0x6a0>\n \tadd\tr2, pc\n \tadd\tr3, r2\n \tstr\tr3, [sp, #32]\n-\tldr\tr3, [sp, #0]\n+\tldr\tr3, [sp, #4]\n \tldr\tr2, [r3, #0]\n \tcmp\tr2, #0\n-\tble.n\t48a6 <__gridxc_mesh3d_MOD_associatemeshtask+0x12a>\n-\tldr.w\tr3, [pc, #1264]\t@ 4d28 <__gridxc_mesh3d_MOD_associatemeshtask+0x5ac>\n+\tble.n\t4594 <__gridxc_mesh3d_MOD_associatemeshtask+0x124>\n+\tldr.w\tr3, [pc, #1520]\t@ 4b14 <__gridxc_mesh3d_MOD_associatemeshtask+0x6a4>\n \tmovs\tr1, #1\n \tadd\tr3, pc\n-\tb.n\t487e <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n+\tb.n\t456c <__gridxc_mesh3d_MOD_associatemeshtask+0xfc>\n \tldr\tr0, [r3, #16]\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #20]\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #24]\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #28]\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #32]\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #36]\t@ 0x24\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #40]\t@ 0x28\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #44]\t@ 0x2c\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tldr\tr0, [r3, #48]\t@ 0x30\n \tcmp\tr2, r0\n-\tbeq.n\t4884 <__gridxc_mesh3d_MOD_associatemeshtask+0x108>\n+\tbeq.n\t4572 <__gridxc_mesh3d_MOD_associatemeshtask+0x102>\n \tadds\tr1, #1\n \tadd.w\tr3, r3, #256\t@ 0x100\n \tcmp\tr1, #101\t@ 0x65\n-\tbeq.n\t48a6 <__gridxc_mesh3d_MOD_associatemeshtask+0x12a>\n+\tbeq.n\t4594 <__gridxc_mesh3d_MOD_associatemeshtask+0x124>\n \tldr\tr0, [r3, #12]\n \tcmp\tr2, r0\n-\tbne.n\t483e <__gridxc_mesh3d_MOD_associatemeshtask+0xc2>\n+\tbne.n\t452c <__gridxc_mesh3d_MOD_associatemeshtask+0xbc>\n \tsubs\tr3, r1, #1\n-\tldr.w\tr2, [pc, #1188]\t@ 4d2c <__gridxc_mesh3d_MOD_associatemeshtask+0x5b0>\n+\tldr.w\tr2, [pc, #1440]\t@ 4b18 <__gridxc_mesh3d_MOD_associatemeshtask+0x6a8>\n \tlsls\tr3, r3, #8\n \tadd\tr2, pc\n \tadd\tr2, r3\n \tldr\tr1, [r2, #52]\t@ 0x34\n \tcmp\tr5, r1\n-\tbeq.w\t4dbc <__gridxc_mesh3d_MOD_associatemeshtask+0x640>\n+\tbeq.w\t49de <__gridxc_mesh3d_MOD_associatemeshtask+0x56e>\n \tldr\tr2, [r2, #56]\t@ 0x38\n \tcmp\tr5, r2\n-\tbeq.w\t4dbc <__gridxc_mesh3d_MOD_associatemeshtask+0x640>\n-\tldr\tr0, [sp, #0]\n-\tbl\t28bc <__gridxc_mesh3d_MOD_freemeshtask>\n-\tldr.w\tr8, [r9]\n-\tcmp.w\tr8, #1\n-\tbeq.w\t4e06 <__gridxc_mesh3d_MOD_associatemeshtask+0x68a>\n-\tldr.w\tr4, [pc, #1148]\t@ 4d30 <__gridxc_mesh3d_MOD_associatemeshtask+0x5b4>\n-\tmovs\tr7, #0\n-\tadd\tr4, pc\n-\tmov\tr3, r4\n+\tbeq.w\t49de <__gridxc_mesh3d_MOD_associatemeshtask+0x56e>\n+\tldr\tr0, [sp, #4]\n+\tbl\t26c8 <__gridxc_mesh3d_MOD_freemeshtask>\n+\tldr.w\tfp, [r7]\n+\tcmp.w\tfp, #1\n+\tbeq.w\t4a22 <__gridxc_mesh3d_MOD_associatemeshtask+0x5b2>\n+\tldr.w\tr3, [pc, #1400]\t@ 4b1c <__gridxc_mesh3d_MOD_associatemeshtask+0x6ac>\n+\tmov.w\tr8, #0\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #24]\n \tldr\tr2, [r3, #12]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #16]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #20]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #24]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #28]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #32]\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #36]\t@ 0x24\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #44]\t@ 0x2c\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n \tldr\tr2, [r3, #48]\t@ 0x30\n \tcmp\tr2, #0\n-\tbge.w\t4d9a <__gridxc_mesh3d_MOD_associatemeshtask+0x61e>\n-\tldr.w\tr2, [pc, #1060]\t@ 4d34 <__gridxc_mesh3d_MOD_associatemeshtask+0x5b8>\n-\tmov.w\tfp, r7, lsl #8\n-\tldr.w\tip, [pc, #1056]\t@ 4d38 <__gridxc_mesh3d_MOD_associatemeshtask+0x5bc>\n-\tvmov.i32\td20, #0\t@ 0x00000000\n-\tadd\tr2, pc\n-\tvmov.i32\td18, #0\t@ 0x00000000\n-\tadd.w\tr0, r2, fp\n-\tadd\tip, pc\n-\tvmov.i8\tq8, #255\t@ 0xff\n-\tadd.w\tr1, fp, #12\n-\tvmov.i8\td19, #255\t@ 0xff\n-\tmov\tr3, r0\n-\tvstr\td20, [r0]\n-\tadd\tr1, r2\n-\tldr.w\tr7, [ip, #76]\t@ 0x4c\n-\tadd.w\tr9, r0, #52\t@ 0x34\n-\tadd.w\tlr, fp, #200\t@ 0xc8\n-\tldr\tr0, [sp, #0]\n+\tbge.w\t49fc <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n+\tldr.w\tr3, [pc, #1312]\t@ 4b20 <__gridxc_mesh3d_MOD_associatemeshtask+0x6b0>\n+\tmov.w\tr4, r8, lsl #8\n+\tldr.w\tsl, [pc, #1308]\t@ 4b24 <__gridxc_mesh3d_MOD_associatemeshtask+0x6b4>\n+\tadd.w\tr0, r4, #12\n+\tadd\tr3, pc\n+\tmovs\tr2, #40\t@ 0x28\n+\tadd\tsl, pc\n+\tmovs\tr1, #255\t@ 0xff\n+\tadd.w\tr8, sl, r4\n+\tadd\tr0, sl\n+\tldr\tr7, [r3, #76]\t@ 0x4c\n+\tmov.w\tr9, #0\n+\tstr\tr4, [sp, #0]\n \tadds\tr7, #1\n-\tstr.w\tr7, [ip, #76]\t@ 0x4c\n-\tmov.w\tip, #0\n-\tstr.w\tip, [r3, #8]\n-\tstr\tr7, [r0, #0]\n-\tcmp\tr8, ip\n-\tvst1.32\t{d19}, [r9]\n-\tstr.w\tip, [r3, #60]\t@ 0x3c\n-\tvst1.8\t{d16-d17}, [r1]\n-\tvstr\td16, [r1, #16]\n-\tvstr\td16, [r1, #24]\n-\tvstr\td16, [r1, #32]\n-\tmov.w\tr1, #4\n-\tstr\tr7, [r3, #12]\n-\tstr.w\tr1, [r3, #192]\t@ 0xc0\n-\tvstr\td18, [r3, #196]\t@ 0xc4\n-\tmovw\tr3, #257\t@ 0x101\n-\tstrh.w\tr3, [r2, lr]\n-\tble.w\t4dd6 <__gridxc_mesh3d_MOD_associatemeshtask+0x65a>\n-\tmov.w\tr3, r8, lsl #1\n+\tstr\tr7, [r3, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #4]\n+\tstr.w\tr9, [sl, r4]\n+\tstrd\tr9, r9, [r8, #4]\n+\tstr\tr7, [r3, #0]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr.w\tr9, [r8, #60]\t@ 0x3c\n+\tstrd\tr3, r3, [r8, #52]\t@ 0x34\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tadd.w\tr3, r4, #200\t@ 0xc8\n+\tmovs\tr2, #4\n+\tstrd\tr9, r9, [r8, #196]\t@ 0xc4\n+\tcmp\tfp, r9\n+\tstr.w\tr2, [r8, #192]\t@ 0xc0\n+\tmovw\tr2, #257\t@ 0x101\n+\tstr.w\tr7, [r8, #12]\n+\tstrh.w\tr2, [sl, r3]\n+\tble.w\t4a32 <__gridxc_mesh3d_MOD_associatemeshtask+0x5c2>\n+\tmov.w\tr3, fp, lsl #1\n \tsubs\tr3, #1\n \tcmp.w\tr3, #1073741824\t@ 0x40000000\n-\tbge.w\t4e84 <__gridxc_mesh3d_MOD_associatemeshtask+0x708>\n+\tbge.w\t4aca <__gridxc_mesh3d_MOD_associatemeshtask+0x65a>\n \tlsls\tr3, r3, #2\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tmov\tsl, r3\n-\tmov\tr0, sl\n+\tmov\tr9, r3\n+\tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [pc, #912]\t@ (4d3c <__gridxc_mesh3d_MOD_associatemeshtask+0x5c0>)\n-\tadd\tr1, pc\n-\tadd.w\tr9, r1, fp\n-\tstr.w\tr0, [r9, #184]\t@ 0xb8\n+\tldr.w\tr2, [pc, #1192]\t@ 4b28 <__gridxc_mesh3d_MOD_associatemeshtask+0x6b8>\n+\tldr\tr3, [sp, #0]\n+\tadd\tr2, pc\n+\tadd.w\tr8, r2, r3\n+\tstr.w\tr0, [r8, #184]\t@ 0xb8\n \tcmp\tr0, #0\n-\tbeq.w\t4e8c <__gridxc_mesh3d_MOD_associatemeshtask+0x710>\n-\tadd.w\tip, r1, #4\n-\tadd.w\tr3, r8, #4294967295\t@ 0xffffffff\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tadd.w\tr2, fp, #200\t@ 0xc8\n-\tadd\tr2, ip\n-\tstr\tr1, [sp, #28]\n-\tstr\tr3, [sp, #12]\n-\tmov\tr1, r3\n-\tvldr\td9, [pc, #788]\t@ 4ce8 <__gridxc_mesh3d_MOD_associatemeshtask+0x56c>\n-\tadd.w\tr3, fp, #232\t@ 0xe8\n-\tlsls\tr1, r1, #1\n-\tmov\tr0, sl\n-\tstr.w\tr1, [r9, #216]\t@ 0xd8\n-\tmov.w\tsl, #0\n-\tmovw\tlr, #257\t@ 0x101\n-\tstr.w\tsl, [r9, #212]\t@ 0xd4\n-\tstr.w\tsl, [r9, #188]\t@ 0xbc\n-\tvst1.32\t{d9}, [r2]\n-\tmovs\tr2, #4\n-\tvstr\td8, [r9, #232]\t@ 0xe8\n-\tstr.w\tr2, [r9, #228]\t@ 0xe4\n-\tstrh.w\tlr, [ip, r3]\n-\tstr\tr1, [sp, #20]\n-\tstr\tr3, [sp, #24]\n+\tbeq.w\t4ad2 <__gridxc_mesh3d_MOD_associatemeshtask+0x662>\n+\tadds\tr1, r2, r3\n+\tstr\tr2, [sp, #28]\n+\tadd.w\tr2, fp, #4294967295\t@ 0xffffffff\n+\tmovs\tr3, #4\n+\tmov\tr0, r9\n+\tstr.w\tr3, [r8, #204]\t@ 0xcc\n+\tmov.w\tr9, #0\n+\tlsls\tr4, r2, #1\n+\tstr.w\tr3, [r8, #228]\t@ 0xe4\n+\tmovw\tip, #257\t@ 0x101\n+\tstr.w\tr9, [r8, #212]\t@ 0xd4\n+\tmov.w\tsl, #1\n+\tstrd\tr9, r9, [r8, #232]\t@ 0xe8\n+\tstr.w\tr9, [r8, #188]\t@ 0xbc\n+\tstr.w\tr4, [r8, #216]\t@ 0xd8\n+\tstr.w\tsl, [r8, #208]\t@ 0xd0\n+\tstrh.w\tip, [r1, #236]\t@ 0xec\n+\tstr\tr2, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [sp, #24]\n-\tmovs\tr2, #4\n-\tldr\tr1, [sp, #28]\n-\tstr.w\tr0, [r9, #220]\t@ 0xdc\n+\tldr\tr2, [sp, #28]\n+\tmovs\tr3, #4\n+\tstr.w\tr0, [r8, #220]\t@ 0xdc\n \tcmp\tr0, #0\n-\tbeq.w\t4e76 <__gridxc_mesh3d_MOD_associatemeshtask+0x6fa>\n-\tadd\tr3, r1\n-\tldr\tr0, [sp, #20]\n-\tstr.w\tr0, [r9, #252]\t@ 0xfc\n-\tcmp.w\tr8, #0\n-\tstr.w\tsl, [r9, #248]\t@ 0xf8\n-\tstr.w\tsl, [r9, #224]\t@ 0xe0\n-\tvstr\td9, [r3, #8]\n-\tadd.w\tr3, fp, #80\t@ 0x50\n-\tstr.w\tr2, [r9, #72]\t@ 0x48\n-\tmovw\tr2, #259\t@ 0x103\n-\tvstr\td8, [r9, #76]\t@ 0x4c\n-\tstrh\tr2, [r1, r3]\n-\tbic.w\tr3, r8, r8, asr #31\n-\tble.w\t4e6c <__gridxc_mesh3d_MOD_associatemeshtask+0x6f0>\n-\tmvn.w\tr2, #2147483648\t@ 0x80000000\n-\tmovs\tr1, #6\n-\tudiv\tr2, r2, r3\n-\tmul.w\tr3, r1, r3\n-\tcmp\tr2, #5\n-\tble.w\t4e84 <__gridxc_mesh3d_MOD_associatemeshtask+0x708>\n-\tcmp.w\tr3, #1073741824\t@ 0x40000000\n-\tbge.w\t4e84 <__gridxc_mesh3d_MOD_associatemeshtask+0x708>\n-\tlsls\tr3, r3, #2\n-\tstr\tr3, [sp, #28]\n+\tbeq.w\t4abc <__gridxc_mesh3d_MOD_associatemeshtask+0x64c>\n+\tstr.w\tr3, [r8, #240]\t@ 0xf0\n+\tmovw\tr1, #259\t@ 0x103\n+\tstr.w\tr3, [r8, #72]\t@ 0x48\n+\tcmp.w\tfp, #0\n+\tldr\tr3, [sp, #0]\n+\tstr.w\tr4, [r8, #252]\t@ 0xfc\n+\tadd.w\tr3, r3, #80\t@ 0x50\n+\tstrd\tr9, r9, [r8, #76]\t@ 0x4c\n+\tstrd\tsl, r9, [r8, #244]\t@ 0xf4\n+\tstr.w\tr9, [r8, #224]\t@ 0xe0\n+\tstrh\tr1, [r2, r3]\n+\tbic.w\tr1, fp, fp, asr #31\n+\tble.w\t4ab8 <__gridxc_mesh3d_MOD_associatemeshtask+0x648>\n+\tmov.w\tr8, #6\n+\tmvn.w\tr0, #2147483648\t@ 0x80000000\n+\tmul.w\tr8, r8, r1\n+\tbl\t0 <__aeabi_idiv>\n+ R_ARM_THM_CALL\t__aeabi_idiv\n+\tcmp\tr0, #5\n+\tble.w\t4aca <__gridxc_mesh3d_MOD_associatemeshtask+0x65a>\n+\tcmp.w\tr8, #1073741824\t@ 0x40000000\n+\tbge.w\t4aca <__gridxc_mesh3d_MOD_associatemeshtask+0x65a>\n+\tmov.w\tr3, r8, lsl #2\n+\tmov\tr4, r3\n \tmov\tsl, r3\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [pc, #712]\t@ (4d40 <__gridxc_mesh3d_MOD_associatemeshtask+0x5c4>)\n-\tstr\tr0, [sp, #24]\n-\tadd\tr1, pc\n-\tadd.w\tr9, r1, fp\n-\tstr.w\tr0, [r9, #64]\t@ 0x40\n+\tldr.w\tip, [pc, #1004]\t@ 4b2c <__gridxc_mesh3d_MOD_associatemeshtask+0x6bc>\n+\tldr\tr3, [sp, #0]\n+\tadd\tip, pc\n+\tadd.w\tr8, ip, r3\n+\tstr.w\tr0, [r8, #64]\t@ 0x40\n \tcmp\tr0, #0\n-\tbeq.w\t4e9a <__gridxc_mesh3d_MOD_associatemeshtask+0x71e>\n-\tadd.w\tr2, fp, #80\t@ 0x50\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tadd\tr2, r1\n-\tadd.w\tip, r1, #4\n-\tvldr\td10, [pc, #596]\t@ 4cf0 <__gridxc_mesh3d_MOD_associatemeshtask+0x574>\n-\tvldr\td11, [pc, #600]\t@ 4cf8 <__gridxc_mesh3d_MOD_associatemeshtask+0x57c>\n-\tadd.w\tlr, r2, #4\n-\tvldr\td8, [pc, #600]\t@ 4d00 <__gridxc_mesh3d_MOD_associatemeshtask+0x584>\n-\tvldr\td9, [pc, #604]\t@ 4d08 <__gridxc_mesh3d_MOD_associatemeshtask+0x58c>\n-\tmov\tr0, sl\n-\tadds\tr2, #20\n-\tadd.w\tsl, fp, #136\t@ 0x88\n-\tldr\tr3, [sp, #12]\n-\tstr.w\tr3, [r9, #120]\t@ 0x78\n+\tbeq.w\t4ae0 <__gridxc_mesh3d_MOD_associatemeshtask+0x670>\n+\tadd\tip, r3\n+\tldr\tr3, [sp, #16]\n+\tmovs\tr2, #2\n+\tstr.w\tr3, [r8, #120]\t@ 0x78\n+\tstrd\tr2, r2, [r8, #96]\t@ 0x60\n \tmovs\tr3, #0\n-\tstr.w\tr3, [r9, #116]\t@ 0x74\n+\tmov.w\tr9, #1\n+\tstrd\tr3, r3, [r8, #136]\t@ 0x88\n+\tstr.w\tr3, [r8, #116]\t@ 0x74\n+\tmov.w\tlr, #3\n+\tmovs\tr3, #6\n+\tstr\tr0, [sp, #28]\n+\tstrd\tlr, r3, [r8, #108]\t@ 0x6c\n+\tmov\tr0, sl\n \tmvn.w\tr3, #2\n-\tstr.w\tr3, [r9, #68]\t@ 0x44\n-\tvst1.32\t{d10-d11}, [lr]\n-\tvst1.32\t{d8-d9}, [r2]\n-\tmovs\tr2, #4\n-\tvstr\td16, [r9, #136]\t@ 0x88\n-\tstr.w\tr2, [r9, #132]\t@ 0x84\n-\tmovw\tr2, #259\t@ 0x103\n-\tstrh.w\tr2, [ip, sl]\n-\tstr\tr1, [sp, #20]\n+\tmov.w\tsl, #4\n+\tstr.w\tr3, [r8, #68]\t@ 0x44\n+\tmovw\tlr, #259\t@ 0x103\n+\tstrd\tr9, r9, [r8, #88]\t@ 0x58\n+\tstr.w\tr9, [r8, #104]\t@ 0x68\n+\tstr.w\tsl, [r8, #84]\t@ 0x54\n+\tstr.w\tsl, [r8, #132]\t@ 0x84\n+\tstrh.w\tlr, [ip, #140]\t@ 0x8c\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr1, [sp, #20]\n+\tldr\tr1, [sp, #28]\n+\tmovs\tr2, #2\n \tmovs\tr3, #0\n-\tstr.w\tr0, [r9, #124]\t@ 0x7c\n+\tstr.w\tr0, [r8, #124]\t@ 0x7c\n \tcmp\tr0, #0\n-\tbeq.w\t4ea8 <__gridxc_mesh3d_MOD_associatemeshtask+0x72c>\n-\tadd\tsl, r1\n-\tmvn.w\tr2, #2\n-\tstr.w\tr2, [r9, #128]\t@ 0x80\n-\tldr\tr2, [sp, #12]\n-\tstr.w\tr3, [r9, #176]\t@ 0xb0\n-\tstr.w\tr2, [r9, #180]\t@ 0xb4\n+\tbeq.w\t4aee <__gridxc_mesh3d_MOD_associatemeshtask+0x67e>\n+\tstrd\tr9, r2, [r8, #152]\t@ 0x98\n+\tmovs\tr4, #6\n+\tstr.w\tr2, [r8, #160]\t@ 0xa0\n+\tmov.w\tip, #3\n+\tldr\tr2, [sp, #16]\n+\tstrd\tip, r4, [r8, #168]\t@ 0xa8\n+\tmvn.w\tr4, #2\n \tcmp\tr2, #0\n-\tvstr\td10, [sl, #8]\n-\tvstr\td11, [sl, #16]\n-\tvstr\td8, [sl, #24]\n-\tvstr\td9, [sl, #32]\n-\tblt.n\t4c02 <__gridxc_mesh3d_MOD_associatemeshtask+0x486>\n-\tldr\tr2, [sp, #24]\n+\tstr.w\tr4, [r8, #128]\t@ 0x80\n+\tstr.w\tsl, [r8, #144]\t@ 0x90\n+\tstr.w\tr9, [r8, #148]\t@ 0x94\n+\tstr.w\tr9, [r8, #164]\t@ 0xa4\n+\tstr.w\tr3, [r8, #176]\t@ 0xb0\n+\tstr.w\tr2, [r8, #180]\t@ 0xb4\n+\tblt.n\t48c4 <__gridxc_mesh3d_MOD_associatemeshtask+0x454>\n \tmovs\tr7, #24\n-\tmov\tr1, r2\n-\tmla\tr7, r7, r8, r2\n+\tmov\tr2, r1\n+\tmla\tr7, r7, fp, r1\n \tstr\tr3, [r1, #0]\n \tadds\tr1, #24\n \tstr.w\tr3, [r1, #-16]\n \tstr.w\tr3, [r1, #-8]\n \tcmp\tr7, r1\n-\tbne.n\t4b28 <__gridxc_mesh3d_MOD_associatemeshtask+0x3ac>\n+\tbne.n\t47f0 <__gridxc_mesh3d_MOD_associatemeshtask+0x380>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr\tr3, [r2, #4]\n \tadds\tr2, #24\n \tstr.w\tr3, [r2, #-12]\n \tstr.w\tr3, [r2, #-4]\n \tcmp\tr7, r2\n-\tbne.n\t4b3c <__gridxc_mesh3d_MOD_associatemeshtask+0x3c0>\n-\tldr\tr2, [pc, #500]\t@ (4d44 <__gridxc_mesh3d_MOD_associatemeshtask+0x5c8>)\n+\tbne.n\t4804 <__gridxc_mesh3d_MOD_associatemeshtask+0x394>\n+\tldr\tr2, [pc, #792]\t@ (4b30 <__gridxc_mesh3d_MOD_associatemeshtask+0x6c0>)\n \tmovs\tr7, #0\n+\tldr\tr3, [sp, #0]\n \tmov\tip, r7\n \tadd\tr2, pc\n-\tadd\tr2, fp\n+\tadd\tr2, r3\n \tldr.w\tr3, [r2, #172]\t@ 0xac\n \tldr.w\tr1, [r2, #144]\t@ 0x90\n \tmul.w\tr3, r7, r3\n \tadds\tr7, #1\n-\tcmp\tr8, r7\n-\tadd.w\tlr, r3, #2\n+\tcmp\tfp, r7\n \tmul.w\tr1, r3, r1\n-\tadd.w\tr3, r3, #4\n \tstr.w\tip, [r0, r1]\n-\tldr.w\tr1, [r2, #144]\t@ 0x90\n-\tmul.w\tr1, r1, lr\n+\tadd.w\tr1, r3, #2\n+\tadd.w\tr3, r3, #4\n+\tldr.w\tr4, [r2, #144]\t@ 0x90\n+\tmul.w\tr1, r4, r1\n \tstr.w\tip, [r0, r1]\n \tldr.w\tr1, [r2, #144]\t@ 0x90\n \tmul.w\tr3, r1, r3\n \tstr.w\tip, [r0, r3]\n-\tbne.n\t4b56 <__gridxc_mesh3d_MOD_associatemeshtask+0x3da>\n+\tbne.n\t4820 <__gridxc_mesh3d_MOD_associatemeshtask+0x3b0>\n \tldr.w\tr1, [r2, #148]\t@ 0x94\n \tldr.w\tr3, [r2, #128]\t@ 0x80\n \tldrd\tr7, sl, [r2, #176]\t@ 0xb0\n-\tadd.w\tr9, r3, r1, lsl #1\n+\tadd.w\tfp, r3, r1, lsl #1\n \tldr.w\tlr, [r2, #124]\t@ 0x7c\n \tldrd\tr3, r1, [r2, #164]\t@ 0xa4\n \tcmp\tr7, sl\n \tldr.w\tip, [r2, #160]\t@ 0xa0\n-\tbgt.n\t4bfe <__gridxc_mesh3d_MOD_associatemeshtask+0x482>\n+\tbgt.n\t48c0 <__gridxc_mesh3d_MOD_associatemeshtask+0x450>\n \tcmp\tr3, r1\n-\tbgt.n\t4bfe <__gridxc_mesh3d_MOD_associatemeshtask+0x482>\n+\tbgt.n\t48c0 <__gridxc_mesh3d_MOD_associatemeshtask+0x450>\n \tadds\tr1, #1\n-\tmov\tr8, r7\n+\tmul.w\tr9, ip, r3\n \tsubs\tr0, r1, r3\n-\tldr\tr1, [pc, #396]\t@ (4d48 <__gridxc_mesh3d_MOD_associatemeshtask+0x5cc>)\n-\tmul.w\tr3, ip, r3\n-\tstr\tr6, [sp, #12]\n+\tldr\tr1, [pc, #684]\t@ (4b34 <__gridxc_mesh3d_MOD_associatemeshtask+0x6c4>)\n+\tldr\tr3, [sp, #0]\n+\tmov\tr8, r7\n \tadd\tr1, pc\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n-\tadd\tr1, fp\n-\tmov\tr6, r3\n+\tadd\tr1, r3\n \tldr.w\tr2, [r1, #172]\t@ 0xac\n-\tmov.w\tfp, #0\n-\tmla\tr2, r2, r8, r9\n-\tadd\tr2, r6\n+\tmovs\tr4, #0\n+\tmla\tr2, r2, r8, fp\n+\tadd\tr2, r9\n \tldr.w\tr3, [r1, #144]\t@ 0x90\n-\tadd.w\tfp, fp, #1\n-\tcmp\tr0, fp\n+\tadds\tr4, #1\n+\tcmp\tr0, r4\n \tmul.w\tr3, r2, r3\n \tadd\tr2, ip\n \tstr.w\tr7, [lr, r3]\n-\tbne.n\t4bda <__gridxc_mesh3d_MOD_associatemeshtask+0x45e>\n+\tbne.n\t48a0 <__gridxc_mesh3d_MOD_associatemeshtask+0x430>\n \tadd.w\tr3, r8, #1\n \tcmp\tsl, r8\n-\tbeq.n\t4bfc <__gridxc_mesh3d_MOD_associatemeshtask+0x480>\n+\tbeq.n\t48c0 <__gridxc_mesh3d_MOD_associatemeshtask+0x450>\n \tmov\tr8, r3\n-\tb.n\t4bcc <__gridxc_mesh3d_MOD_associatemeshtask+0x450>\n-\tldr\tr6, [sp, #12]\n-\tldr\tr3, [sp, #0]\n+\tb.n\t4894 <__gridxc_mesh3d_MOD_associatemeshtask+0x424>\n+\tldr\tr3, [sp, #4]\n \tldr\tr7, [r3, #0]\n \tcmp\tr7, #0\n-\tble.w\t4e0c <__gridxc_mesh3d_MOD_associatemeshtask+0x690>\n+\tble.w\t4a28 <__gridxc_mesh3d_MOD_associatemeshtask+0x5b8>\n+\tldr\tr3, [sp, #24]\n \tmov.w\tr8, #1\n-\tb.n\t4c54 <__gridxc_mesh3d_MOD_associatemeshtask+0x4d8>\n-\tldr\tr3, [r4, #16]\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #20]\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #24]\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #28]\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #32]\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #36]\t@ 0x24\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #40]\t@ 0x28\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #44]\t@ 0x2c\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n-\tldr\tr3, [r4, #48]\t@ 0x30\n-\tcmp\tr3, r7\n-\tbeq.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n+\tb.n\t4918 <__gridxc_mesh3d_MOD_associatemeshtask+0x4a8>\n+\tldr\tr1, [r3, #16]\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #20]\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #24]\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #28]\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #32]\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #36]\t@ 0x24\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #40]\t@ 0x28\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #44]\t@ 0x2c\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tldr\tr1, [r3, #48]\t@ 0x30\n+\tcmp\tr1, r7\n+\tbeq.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n \tadd.w\tr8, r8, #1\n-\tadd.w\tr4, r4, #256\t@ 0x100\n+\tadd.w\tr3, r3, #256\t@ 0x100\n \tcmp.w\tr8, #101\t@ 0x65\n-\tbeq.w\t4e0c <__gridxc_mesh3d_MOD_associatemeshtask+0x690>\n-\tldr\tr3, [r4, #12]\n+\tbeq.w\t4a28 <__gridxc_mesh3d_MOD_associatemeshtask+0x5b8>\n+\tldr\tr1, [r3, #12]\n \tadd.w\tr2, r8, #4294967295\t@ 0xffffffff\n-\tcmp\tr3, r7\n-\tbne.n\t4c0e <__gridxc_mesh3d_MOD_associatemeshtask+0x492>\n-\tldr\tr3, [sp, #16]\n+\tcmp\tr1, r7\n+\tbne.n\t48d2 <__gridxc_mesh3d_MOD_associatemeshtask+0x462>\n+\tldr\tr3, [sp, #20]\n \tlsls\tr4, r2, #8\n \tmov.w\tr2, #364\t@ 0x16c\n \tmul.w\tr2, r3, r2\n-\tldr\tr3, [pc, #224]\t@ (4d4c <__gridxc_mesh3d_MOD_associatemeshtask+0x5d0>)\n+\tldr\tr3, [pc, #520]\t@ (4b38 <__gridxc_mesh3d_MOD_associatemeshtask+0x6c8>)\n \tadd\tr3, pc\n \tadd.w\tr0, r2, #100\t@ 0x64\n \tadd\tr3, r4\n \tstr\tr5, [r3, #52]\t@ 0x34\n-\tldr\tr3, [pc, #216]\t@ (4d50 <__gridxc_mesh3d_MOD_associatemeshtask+0x5d4>)\n+\tldr\tr3, [pc, #512]\t@ (4b3c <__gridxc_mesh3d_MOD_associatemeshtask+0x6cc>)\n \tadd\tr3, pc\n \tadd\tr0, r3\n \tadd.w\tr3, r3, #300\t@ 0x12c\n-\tadd\tr2, r3\n+\tadds\tr1, r3, r2\n \tmov\tr3, r0\n-\tb.n\t4c8c <__gridxc_mesh3d_MOD_associatemeshtask+0x510>\n-\tcmp\tr3, r2\n-\tbeq.w\t4de0 <__gridxc_mesh3d_MOD_associatemeshtask+0x664>\n-\tldr.w\tr1, [r3, #4]!\n-\tcmp\tr1, r8\n-\tbne.n\t4c86 <__gridxc_mesh3d_MOD_associatemeshtask+0x50a>\n-\tldr\tr3, [sp, #4]\n+\tb.n\t494e <__gridxc_mesh3d_MOD_associatemeshtask+0x4de>\n+\tcmp\tr1, r3\n+\tbeq.n\t4a3c <__gridxc_mesh3d_MOD_associatemeshtask+0x5cc>\n+\tldr.w\tr2, [r3, #4]!\n+\tcmp\tr2, r8\n+\tbne.n\t494a <__gridxc_mesh3d_MOD_associatemeshtask+0x4da>\n+\tldr\tr3, [sp, #8]\n \tcmp\tr3, #0\n \tit\tne\n \tcmpne\tr6, r5\n-\tbeq.n\t4cc2 <__gridxc_mesh3d_MOD_associatemeshtask+0x546>\n-\tldr\tr3, [pc, #180]\t@ (4d54 <__gridxc_mesh3d_MOD_associatemeshtask+0x5d8>)\n+\tbeq.n\t4982 <__gridxc_mesh3d_MOD_associatemeshtask+0x512>\n+\tldr\tr3, [pc, #476]\t@ (4b40 <__gridxc_mesh3d_MOD_associatemeshtask+0x6d0>)\n \tadd\tr3, pc\n \tadd\tr3, r4\n \tstr\tr6, [r3, #56]\t@ 0x38\n \tldr\tr3, [sp, #32]\n \tadd.w\tr1, r3, #100\t@ 0x64\n \tadd.w\tr0, r3, #300\t@ 0x12c\n \tmov\tr3, r1\n-\tb.n\t4cba <__gridxc_mesh3d_MOD_associatemeshtask+0x53e>\n+\tb.n\t497a <__gridxc_mesh3d_MOD_associatemeshtask+0x50a>\n \tcmp\tr0, r3\n-\tbeq.w\t4e1e <__gridxc_mesh3d_MOD_associatemeshtask+0x6a2>\n+\tbeq.n\t4a6a <__gridxc_mesh3d_MOD_associatemeshtask+0x5fa>\n \tldr.w\tr2, [r3, #4]!\n \tcmp\tr2, r8\n-\tbne.n\t4cb4 <__gridxc_mesh3d_MOD_associatemeshtask+0x538>\n-\tldr\tr3, [pc, #148]\t@ (4d58 <__gridxc_mesh3d_MOD_associatemeshtask+0x5dc>)\n+\tbne.n\t4976 <__gridxc_mesh3d_MOD_associatemeshtask+0x506>\n+\tldr\tr3, [pc, #448]\t@ (4b44 <__gridxc_mesh3d_MOD_associatemeshtask+0x6d4>)\n \tmovs\tr2, #1\n \tadd\tr3, pc\n \tadd\tr3, r4\n \tstr\tr2, [r3, #8]\n \tadd\tsp, #44\t@ 0x2c\n-\tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tble.n\t4d7e <__gridxc_mesh3d_MOD_associatemeshtask+0x602>\n-\tldr\tr1, [pc, #128]\t@ (4d5c <__gridxc_mesh3d_MOD_associatemeshtask+0x5e0>)\n+\tble.n\t49c0 <__gridxc_mesh3d_MOD_associatemeshtask+0x550>\n+\tldr\tr1, [pc, #432]\t@ (4b48 <__gridxc_mesh3d_MOD_associatemeshtask+0x6d8>)\n \tmovs\tr0, #1\n \tadd\tr1, pc\n \tadds\tr1, #80\t@ 0x50\n \tsub.w\tr3, r1, #80\t@ 0x50\n-\tb.n\t4d64 <__gridxc_mesh3d_MOD_associatemeshtask+0x5e8>\n-\tnop\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000002\n-\t.word\t0x00000001\n-\t.word\t0x00000003\n-\t.word\t0x00000006\n-\t.word\t0x00000572\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n-\t.word\t0x0000053c\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000508\n- R_ARM_REL32\t.LC51\n-\t.word\t0x000004fa\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000004ea\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x0000049c\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x00000474\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x00000414\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x0000040e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000038e\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000002c2\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000001ee\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x00000182\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000000dc\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000000d4\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x000000b0\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x0000008e\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x0000007c\n- R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\tcmp\tr3, r1\n-\tbeq.n\t4d74 <__gridxc_mesh3d_MOD_associatemeshtask+0x5f8>\n+\tb.n\t49a6 <__gridxc_mesh3d_MOD_associatemeshtask+0x536>\n+\tcmp\tr1, r3\n+\tbeq.n\t49b6 <__gridxc_mesh3d_MOD_associatemeshtask+0x546>\n \tldr.w\tr2, [r3, #4]!\n-\tcmp\tr5, r2\n-\tbne.n\t4d60 <__gridxc_mesh3d_MOD_associatemeshtask+0x5e4>\n+\tcmp\tr6, r2\n+\tbne.n\t49a2 <__gridxc_mesh3d_MOD_associatemeshtask+0x532>\n \tldr.w\tr3, [r1, #-80]\n \tcmp\tr3, #0\n-\tbne.n\t4e16 <__gridxc_mesh3d_MOD_associatemeshtask+0x69a>\n+\tbne.n\t4a98 <__gridxc_mesh3d_MOD_associatemeshtask+0x628>\n \tadds\tr0, #1\n \tadd.w\tr1, r1, #364\t@ 0x16c\n \tcmp\tr0, #21\n-\tbne.n\t4ce0 <__gridxc_mesh3d_MOD_associatemeshtask+0x564>\n-\tldr\tr3, [pc, #312]\t@ (4eb8 <__gridxc_mesh3d_MOD_associatemeshtask+0x73c>)\n+\tbne.n\t499c <__gridxc_mesh3d_MOD_associatemeshtask+0x52c>\n+\tldr\tr3, [pc, #324]\t@ (4b08 <__gridxc_mesh3d_MOD_associatemeshtask+0x698>)\n \tmovs\tr1, #45\t@ 0x2d\n-\tldr\tr2, [sp, #8]\n-\tmov.w\tr5, #4294967295\t@ 0xffffffff\n-\tldr\tr0, [pc, #304]\t@ (4ebc <__gridxc_mesh3d_MOD_associatemeshtask+0x740>)\n+\tldr\tr2, [sp, #12]\n+\tmov.w\tr6, #4294967295\t@ 0xffffffff\n+\tldr\tr0, [pc, #384]\t@ (4b4c <__gridxc_mesh3d_MOD_associatemeshtask+0x6dc>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tmvn.w\tr3, #1\n-\tstr\tr3, [sp, #16]\n-\tb.n\t47be <__gridxc_mesh3d_MOD_associatemeshtask+0x42>\n-\tadds\tr7, #1\n-\tadd.w\tr3, r3, #256\t@ 0x100\n-\tcmp\tr7, #100\t@ 0x64\n-\tbne.w\t48bc <__gridxc_mesh3d_MOD_associatemeshtask+0x140>\n-\tldr\tr3, [pc, #272]\t@ (4eb8 <__gridxc_mesh3d_MOD_associatemeshtask+0x73c>)\n-\tmovs\tr1, #51\t@ 0x33\n+\tmovw\tr3, #64808\t@ 0xfd28\n+\tmovt\tr3, #65535\t@ 0xffff\n+\tb.n\t4510 <__gridxc_mesh3d_MOD_associatemeshtask+0xa0>\n \tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #272]\t@ (4ec0 <__gridxc_mesh3d_MOD_associatemeshtask+0x744>)\n-\tldr\tr3, [r2, r3]\n-\tadd\tr0, pc\n-\tldr\tr3, [r3, #0]\n-\tblx\tr3\n-\tldr.w\tr8, [r9]\n-\tb.n\t490c <__gridxc_mesh3d_MOD_associatemeshtask+0x190>\n-\tldr\tr2, [sp, #4]\n \tcmp\tr2, #0\n-\tbeq.n\t4ccc <__gridxc_mesh3d_MOD_associatemeshtask+0x550>\n+\tbeq.n\t498c <__gridxc_mesh3d_MOD_associatemeshtask+0x51c>\n \tcmp\tr6, r1\n-\tbeq.n\t4ccc <__gridxc_mesh3d_MOD_associatemeshtask+0x550>\n-\tldr\tr2, [pc, #252]\t@ (4ec4 <__gridxc_mesh3d_MOD_associatemeshtask+0x748>)\n+\tbeq.n\t498c <__gridxc_mesh3d_MOD_associatemeshtask+0x51c>\n+\tldr\tr2, [pc, #356]\t@ (4b50 <__gridxc_mesh3d_MOD_associatemeshtask+0x6e0>)\n \tadd\tr2, pc\n \tadd\tr3, r2\n \tldr\tr3, [r3, #56]\t@ 0x38\n \tcmp\tr6, r3\n-\tbne.w\t48a0 <__gridxc_mesh3d_MOD_associatemeshtask+0x124>\n-\tb.n\t4ccc <__gridxc_mesh3d_MOD_associatemeshtask+0x550>\n-\tmov.w\tsl, #1\n-\tstr.w\tip, [sp, #36]\t@ 0x24\n-\tb.n\t49a2 <__gridxc_mesh3d_MOD_associatemeshtask+0x226>\n+\tbeq.n\t498c <__gridxc_mesh3d_MOD_associatemeshtask+0x51c>\n+\tldr\tr0, [sp, #4]\n+\tbl\t26c8 <__gridxc_mesh3d_MOD_freemeshtask>\n+\tb.n\t4594 <__gridxc_mesh3d_MOD_associatemeshtask+0x124>\n+\tadd.w\tr8, r8, #1\n+\tadd.w\tr3, r3, #256\t@ 0x100\n+\tcmp.w\tr8, #100\t@ 0x64\n+\tbne.w\t45ac <__gridxc_mesh3d_MOD_associatemeshtask+0x13c>\n+\tldr\tr3, [pc, #248]\t@ (4b08 <__gridxc_mesh3d_MOD_associatemeshtask+0x698>)\n+\tmovs\tr1, #51\t@ 0x33\n+\tldr\tr2, [sp, #12]\n+\tldr\tr0, [pc, #320]\t@ (4b54 <__gridxc_mesh3d_MOD_associatemeshtask+0x6e4>)\n+\tldr\tr3, [r2, r3]\n+\tadd\tr0, pc\n+\tldr\tr3, [r3, #0]\n+\tblx\tr3\n+\tldr.w\tfp, [r7]\n+\tb.n\t45fc <__gridxc_mesh3d_MOD_associatemeshtask+0x18c>\n+\tldr\tr2, [sp, #4]\n+\tmovs\tr3, #0\n+\tstr\tr3, [r2, #0]\n+\tmvn.w\tr2, #1\n+\tmov.w\tr8, #4294967295\t@ 0xffffffff\n+\tb.n\t4922 <__gridxc_mesh3d_MOD_associatemeshtask+0x4b2>\n+\tstr.w\tr9, [sp, #36]\t@ 0x24\n+\tmov.w\tr9, #1\n+\tb.n\t4676 <__gridxc_mesh3d_MOD_associatemeshtask+0x206>\n \tmovs\tr3, #0\n-\tb.n\t4dea <__gridxc_mesh3d_MOD_associatemeshtask+0x66e>\n+\tb.n\t4a46 <__gridxc_mesh3d_MOD_associatemeshtask+0x5d6>\n \tadds\tr3, #1\n \tcmp\tr3, #50\t@ 0x32\n-\tbeq.n\t4e3a <__gridxc_mesh3d_MOD_associatemeshtask+0x6be>\n+\tbeq.n\t4a86 <__gridxc_mesh3d_MOD_associatemeshtask+0x616>\n \tldr.w\tr2, [r0, #4]!\n \tcmp\tr2, #0\n-\tbge.n\t4de4 <__gridxc_mesh3d_MOD_associatemeshtask+0x668>\n-\tldr\tr1, [sp, #16]\n+\tbge.n\t4a40 <__gridxc_mesh3d_MOD_associatemeshtask+0x5d0>\n+\tldr\tr1, [sp, #20]\n \tmovs\tr2, #91\t@ 0x5b\n \tmla\tr3, r2, r1, r3\n-\tldr\tr2, [pc, #204]\t@ (4ec8 <__gridxc_mesh3d_MOD_associatemeshtask+0x74c>)\n+\tldr\tr2, [pc, #256]\t@ (4b58 <__gridxc_mesh3d_MOD_associatemeshtask+0x6e8>)\n \tadds\tr3, #26\n \tadd\tr2, pc\n \tstr.w\tr8, [r2, r3, lsl #2]\n-\tb.n\t4c94 <__gridxc_mesh3d_MOD_associatemeshtask+0x518>\n-\tldr\tr2, [sp, #0]\n-\tmovs\tr3, #0\n-\tstr\tr3, [r2, #0]\n-\tmvn.w\tr2, #1\n-\tmov.w\tr8, #4294967295\t@ 0xffffffff\n-\tb.n\t4c5e <__gridxc_mesh3d_MOD_associatemeshtask+0x4e2>\n+\tb.n\t4956 <__gridxc_mesh3d_MOD_associatemeshtask+0x4e6>\n \tsubs\tr3, r0, #1\n \tmov\tr5, r0\n-\tstr\tr3, [sp, #16]\n-\tb.n\t47be <__gridxc_mesh3d_MOD_associatemeshtask+0x42>\n+\tstr\tr3, [sp, #20]\n+\tb.n\t44fa <__gridxc_mesh3d_MOD_associatemeshtask+0x8a>\n \tmovs\tr3, #0\n-\tb.n\t4e28 <__gridxc_mesh3d_MOD_associatemeshtask+0x6ac>\n+\tb.n\t4a74 <__gridxc_mesh3d_MOD_associatemeshtask+0x604>\n \tadds\tr3, #1\n \tcmp\tr3, #50\t@ 0x32\n-\tbeq.n\t4e5a <__gridxc_mesh3d_MOD_associatemeshtask+0x6de>\n+\tbeq.n\t4aa6 <__gridxc_mesh3d_MOD_associatemeshtask+0x636>\n \tldr.w\tr2, [r1, #4]!\n \tcmp\tr2, #0\n-\tbge.n\t4e22 <__gridxc_mesh3d_MOD_associatemeshtask+0x6a6>\n+\tbge.n\t4a6e <__gridxc_mesh3d_MOD_associatemeshtask+0x5fe>\n \tldr\tr2, [sp, #32]\n \tadds\tr3, #26\n \tstr.w\tr8, [r2, r3, lsl #2]\n-\tb.n\t4cc2 <__gridxc_mesh3d_MOD_associatemeshtask+0x546>\n-\tldr\tr3, [pc, #124]\t@ (4eb8 <__gridxc_mesh3d_MOD_associatemeshtask+0x73c>)\n+\tb.n\t4982 <__gridxc_mesh3d_MOD_associatemeshtask+0x512>\n+\tldr\tr3, [pc, #128]\t@ (4b08 <__gridxc_mesh3d_MOD_associatemeshtask+0x698>)\n \tmovs\tr1, #58\t@ 0x3a\n-\tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #136]\t@ (4ecc <__gridxc_mesh3d_MOD_associatemeshtask+0x750>)\n+\tldr\tr2, [sp, #12]\n+\tldr\tr0, [pc, #204]\t@ (4b5c <__gridxc_mesh3d_MOD_associatemeshtask+0x6ec>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t4c94 <__gridxc_mesh3d_MOD_associatemeshtask+0x518>\n+\tb.n\t4956 <__gridxc_mesh3d_MOD_associatemeshtask+0x4e6>\n \tsubs\tr3, r0, #1\n \tmov.w\tr2, #364\t@ 0x16c\n \tmov\tr6, r0\n \tmul.w\tr3, r2, r3\n-\tb.n\t4822 <__gridxc_mesh3d_MOD_associatemeshtask+0xa6>\n-\tldr\tr3, [pc, #92]\t@ (4eb8 <__gridxc_mesh3d_MOD_associatemeshtask+0x73c>)\n+\tb.n\t4510 <__gridxc_mesh3d_MOD_associatemeshtask+0xa0>\n+\tldr\tr3, [pc, #96]\t@ (4b08 <__gridxc_mesh3d_MOD_associatemeshtask+0x698>)\n \tmovs\tr1, #58\t@ 0x3a\n-\tldr\tr2, [sp, #8]\n-\tldr\tr0, [pc, #108]\t@ (4ed0 <__gridxc_mesh3d_MOD_associatemeshtask+0x754>)\n+\tldr\tr2, [sp, #12]\n+\tldr\tr0, [pc, #176]\t@ (4b60 <__gridxc_mesh3d_MOD_associatemeshtask+0x6f0>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t4cc2 <__gridxc_mesh3d_MOD_associatemeshtask+0x546>\n-\tstr.w\tsl, [sp, #28]\n-\tmov.w\tsl, #1\n-\tb.n\t4a70 <__gridxc_mesh3d_MOD_associatemeshtask+0x2f4>\n-\tldr\tr1, [pc, #92]\t@ (4ed4 <__gridxc_mesh3d_MOD_associatemeshtask+0x758>)\n-\tldr\tr0, [pc, #92]\t@ (4ed8 <__gridxc_mesh3d_MOD_associatemeshtask+0x75c>)\n+\tb.n\t4982 <__gridxc_mesh3d_MOD_associatemeshtask+0x512>\n+\tmov\tr4, r9\n+\tb.n\t4736 <__gridxc_mesh3d_MOD_associatemeshtask+0x2c6>\n+\tldr\tr1, [pc, #164]\t@ (4b64 <__gridxc_mesh3d_MOD_associatemeshtask+0x6f4>)\n+\tldr\tr0, [pc, #168]\t@ (4b68 <__gridxc_mesh3d_MOD_associatemeshtask+0x6f8>)\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #84]\t@ (4edc <__gridxc_mesh3d_MOD_associatemeshtask+0x760>)\n+\tldr\tr0, [pc, #160]\t@ (4b6c <__gridxc_mesh3d_MOD_associatemeshtask+0x6fc>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tldr\tr1, [pc, #80]\t@ (4ee0 <__gridxc_mesh3d_MOD_associatemeshtask+0x764>)\n-\tldr\tr0, [pc, #84]\t@ (4ee4 <__gridxc_mesh3d_MOD_associatemeshtask+0x768>)\n+\tldr\tr1, [pc, #156]\t@ (4b70 <__gridxc_mesh3d_MOD_associatemeshtask+0x700>)\n+\tldr\tr0, [pc, #156]\t@ (4b74 <__gridxc_mesh3d_MOD_associatemeshtask+0x704>)\n \tldr\tr2, [sp, #36]\t@ 0x24\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #76]\t@ (4ee8 <__gridxc_mesh3d_MOD_associatemeshtask+0x76c>)\n-\tldr\tr0, [pc, #76]\t@ (4eec <__gridxc_mesh3d_MOD_associatemeshtask+0x770>)\n-\tldr\tr2, [sp, #28]\n+\tldr\tr1, [pc, #148]\t@ (4b78 <__gridxc_mesh3d_MOD_associatemeshtask+0x708>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #148]\t@ (4b7c <__gridxc_mesh3d_MOD_associatemeshtask+0x70c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #68]\t@ (4ef0 <__gridxc_mesh3d_MOD_associatemeshtask+0x774>)\n-\tldr\tr0, [pc, #72]\t@ (4ef4 <__gridxc_mesh3d_MOD_associatemeshtask+0x778>)\n-\tldr\tr2, [sp, #28]\n+\tldr\tr1, [pc, #144]\t@ (4b80 <__gridxc_mesh3d_MOD_associatemeshtask+0x710>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #144]\t@ (4b84 <__gridxc_mesh3d_MOD_associatemeshtask+0x714>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tnop\n+\t.word\t0x0000066e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_config_MOD_gridxc_totnodes\n+\t.word\t0x0000064e\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000012c\n+\t.word\t0x0000061a\n R_ARM_REL32\t.LC50\n-\t.word\t0x0000010c\n- R_ARM_REL32\t.LC57\n-\t.word\t0x000000f8\n+\t.word\t0x000005f8\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x000005e8\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x0000059a\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x00000570\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x00000510\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000510\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000004a2\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000003e6\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x00000310\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000002a4\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x00000204\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000001fc\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x000001da\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000001ba\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n+\t.word\t0x000001ac\n+ R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n+\t.word\t0x0000017a\n+ R_ARM_REL32\t.LC51\n+\t.word\t0x00000162\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshtask\n-\t.word\t0x000000c6\n+\t.word\t0x0000013a\n+ R_ARM_REL32\t.LC57\n+\t.word\t0x000000fa\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x00000084\n+\t.word\t0x000000c8\n R_ARM_REL32\t.LC56\n-\t.word\t0x00000068\n+\t.word\t0x000000ac\n R_ARM_REL32\t.LC56\n-\t.word\t0x00000054\n+\t.word\t0x0000009e\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000056\n+\t.word\t0x000000a0\n R_ARM_REL32\t.LC53\n-\t.word\t0x00000052\n+\t.word\t0x0000009c\n R_ARM_REL32\t.LC0\n-\t.word\t0x0000004a\n+\t.word\t0x00000094\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000004c\n+\t.word\t0x00000096\n R_ARM_REL32\t.LC52\n-\t.word\t0x00000044\n+\t.word\t0x0000008e\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000046\n+\t.word\t0x00000090\n R_ARM_REL32\t.LC54\n-\t.word\t0x0000003e\n+\t.word\t0x00000088\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000040\n+\t.word\t0x0000008a\n R_ARM_REL32\t.LC55\n \n-00004ef8 <__gridxc_mesh3d_MOD_copymeshdata>:\n+00004b88 <__gridxc_mesh3d_MOD_copymeshdata>:\n __gridxc_mesh3d_MOD_copymeshdata.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3784]\t@ 0xec8\n \tsub\tsp, #276\t@ 0x114\n \tldr\tr5, [r2, #24]\n-\tldr.w\tr8, [pc, #636]\t@ 518c <__gridxc_mesh3d_MOD_copymeshdata+0x294>\n+\tldr.w\tr8, [pc, #640]\t@ 4e20 <__gridxc_mesh3d_MOD_copymeshdata+0x298>\n \tmov\tfp, r1\n \tstr\tr0, [sp, #28]\n \tadd\tr8, pc\n-\tldr\tr0, [pc, #632]\t@ (5190 <__gridxc_mesh3d_MOD_copymeshdata+0x298>)\n+\tldr\tr0, [pc, #636]\t@ (4e24 <__gridxc_mesh3d_MOD_copymeshdata+0x29c>)\n \tstr\tr3, [sp, #84]\t@ 0x54\n-\tldr\tr3, [pc, #632]\t@ (5194 <__gridxc_mesh3d_MOD_copymeshdata+0x29c>)\n+\tldr\tr3, [pc, #636]\t@ (4e28 <__gridxc_mesh3d_MOD_copymeshdata+0x2a0>)\n \tadd\tr0, pc\n \tldr\tr7, [sp, #316]\t@ 0x13c\n \tldr\tr3, [r0, r3]\n \tldrd\tr4, r0, [r2, #64]\t@ 0x40\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #268]\t@ 0x10c\n \tmov.w\tr3, #0\n@@ -7756,20 +7593,21 @@\n \tsubs\tr0, r0, r4\n \tadds\tr0, #1\n \tstr\tr0, [sp, #80]\t@ 0x50\n \tldr\tr0, [r3, #24]\n \tcmp\tr0, #0\n \tit\teq\n \tmoveq\tr0, #1\n+\tcmp\tr5, #0\n \tstr\tr0, [sp, #20]\n+\tite\tne\n+\tmovne\tr0, r5\n+\tmoveq\tr0, #1\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tldrd\tr0, r4, [r3, #64]\t@ 0x40\n-\tcmp\tr5, #0\n-\tit\teq\n-\tmoveq\tr5, #1\n-\tstr\tr5, [sp, #48]\t@ 0x30\n \tsubs\tr0, r4, r0\n \tstr\tr0, [sp, #16]\n \tldrd\tr0, r5, [r3, #28]\n \tsubs\tr5, r5, r0\n \tldrd\tr0, r6, [r3, #40]\t@ 0x28\n \tsubs\tr6, r6, r0\n \tldrd\tr0, r4, [r3, #52]\t@ 0x34\n@@ -7796,21 +7634,21 @@\n \tldr\tr0, [sp, #16]\n \tldr\tr3, [r2, #48]\t@ 0x30\n \tstr\tr3, [sp, #68]\t@ 0x44\n \tldr\tr3, [r2, #60]\t@ 0x3c\n \tstr\tr3, [sp, #76]\t@ 0x4c\n \tadds\tr3, r0, #1\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tcbz\tr7, 4faa <__gridxc_mesh3d_MOD_copymeshdata+0xb2>\n+\tcbz\tr7, 4c3c <__gridxc_mesh3d_MOD_copymeshdata+0xb4>\n \tmov\tr0, r7\n \tmovs\tr2, #0\n-\tbl\t477c <__gridxc_mesh3d_MOD_associatemeshtask>\n+\tbl\t4470 <__gridxc_mesh3d_MOD_associatemeshtask>\n \tldr.w\tr1, [fp]\n \tcmp\tr1, #0\n-\tbne.w\t5100 <__gridxc_mesh3d_MOD_copymeshdata+0x208>\n+\tbne.w\t4d8e <__gridxc_mesh3d_MOD_copymeshdata+0x206>\n \tldr\tr2, [sp, #28]\n \tstr\tr1, [sp, #100]\t@ 0x64\n \tstr\tr1, [sp, #108]\t@ 0x6c\n \tldr\tr3, [r2, #0]\n \tstr\tr1, [sp, #116]\t@ 0x74\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #104]\t@ 0x68\n@@ -7820,21 +7658,21 @@\n \tldr\tr3, [r2, #8]\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #120]\t@ 0x78\n \tadd\tr3, sp, #100\t@ 0x64\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, #0\n-\tble.n\t5054 <__gridxc_mesh3d_MOD_copymeshdata+0x15c>\n+\tble.n\t4ce6 <__gridxc_mesh3d_MOD_copymeshdata+0x15e>\n \torr.w\tr3, r5, r6\n \torrs.w\tr3, r3, sl\n-\tbmi.n\t5054 <__gridxc_mesh3d_MOD_copymeshdata+0x15c>\n+\tbmi.n\t4ce6 <__gridxc_mesh3d_MOD_copymeshdata+0x15e>\n \tldr\tr3, [sp, #20]\n \tcmp\tr3, #1\n-\tbne.w\t5116 <__gridxc_mesh3d_MOD_copymeshdata+0x21e>\n+\tbne.w\t4da4 <__gridxc_mesh3d_MOD_copymeshdata+0x21c>\n \tadds\tr7, r5, #1\n \tmovs\tr3, #0\n \tmov.w\tr8, r4, lsl #3\n \tmov\tip, sl\n \tlsls\tr7, r7, #3\n \tmov\tfp, r3\n \tstr\tr4, [sp, #32]\n@@ -7852,38 +7690,37 @@\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr3, r0\n \tcmp\tr6, r5\n \tadd\tr3, r8\n \tadd.w\tr5, r5, #1\n-\tbne.n\t5012 <__gridxc_mesh3d_MOD_copymeshdata+0x11a>\n+\tbne.n\t4ca4 <__gridxc_mesh3d_MOD_copymeshdata+0x11c>\n \tldr\tr3, [sp, #12]\n \tcmp\tsl, fp\n \tadd\tr4, r3\n \tadd.w\tr3, fp, #1\n-\tbeq.n\t5038 <__gridxc_mesh3d_MOD_copymeshdata+0x140>\n+\tbeq.n\t4cca <__gridxc_mesh3d_MOD_copymeshdata+0x142>\n \tmov\tfp, r3\n-\tb.n\t500c <__gridxc_mesh3d_MOD_copymeshdata+0x114>\n+\tb.n\t4c9e <__gridxc_mesh3d_MOD_copymeshdata+0x116>\n \tldrd\tfp, r3, [sp, #88]\t@ 0x58\n \tmov\tip, sl\n \tldr\tr2, [sp, #24]\n \tldr\tr5, [sp, #36]\t@ 0x24\n \tadd.w\tr1, fp, #1\n \tadd\tr3, r2\n \tldr\tr2, [sp, #16]\n \tcmp\tfp, r2\n-\tbeq.n\t5052 <__gridxc_mesh3d_MOD_copymeshdata+0x15a>\n+\tbeq.n\t4ce4 <__gridxc_mesh3d_MOD_copymeshdata+0x15c>\n \tmov\tfp, r1\n-\tb.n\t4ffa <__gridxc_mesh3d_MOD_copymeshdata+0x102>\n+\tb.n\t4c8c <__gridxc_mesh3d_MOD_copymeshdata+0x104>\n \tldr\tr4, [sp, #32]\n \tldr\tr3, [sp, #56]\t@ 0x38\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #156]\t@ 0x9c\n \tmovs\tr2, #0\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tstr\tr3, [sp, #148]\t@ 0x94\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tstr\tr3, [sp, #168]\t@ 0xa8\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tstr\tr3, [sp, #160]\t@ 0xa0\n \tldr\tr3, [sp, #72]\t@ 0x48\n@@ -7892,150 +7729,152 @@\n \tstr\tr3, [sp, #172]\t@ 0xac\n \tldr\tr3, [sp, #80]\t@ 0x50\n \tstr\tr3, [sp, #192]\t@ 0xc0\n \tldr\tr3, [sp, #52]\t@ 0x34\n \tstr\tr3, [sp, #124]\t@ 0x7c\n \tldr\tr3, [sp, #20]\n \tstr\tr3, [sp, #220]\t@ 0xdc\n-\tldr\tr3, [sp, #12]\n-\tstr\tr3, [sp, #244]\t@ 0xf4\n \tldr\tr3, [sp, #76]\t@ 0x4c\n \tldr\tr1, [sp, #44]\t@ 0x2c\n \tldr\tr0, [sp, #28]\n+\tstr\tr5, [sp, #228]\t@ 0xe4\n \tstr\tr4, [sp, #232]\t@ 0xe8\n \tmovs\tr4, #8\n \tstr\tr3, [sp, #184]\t@ 0xb8\n \tnegs\tr3, r3\n-\tvstr\td16, [sp, #136]\t@ 0x88\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n \tstr\tr3, [sp, #128]\t@ 0x80\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n+\tstr\tr2, [sp, #212]\t@ 0xd4\n \tldr\tr3, [sp, #84]\t@ 0x54\n-\tstr\tr5, [sp, #228]\t@ 0xe4\n+\tstr\tr2, [sp, #136]\t@ 0x88\n+\tstr\tr2, [sp, #152]\t@ 0x98\n \tstr\tr6, [sp, #240]\t@ 0xf0\n \tstr.w\tsl, [sp, #252]\t@ 0xfc\n-\tstr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr2, [sp, #164]\t@ 0xa4\n+\tstr\tr2, [sp, #176]\t@ 0xb0\n+\tstr\tr2, [sp, #208]\t@ 0xd0\n+\tstr\tr2, [sp, #224]\t@ 0xe0\n+\tstr\tr2, [sp, #236]\t@ 0xec\n+\tstr\tr2, [sp, #248]\t@ 0xf8\n+\tstr\tr2, [sp, #4]\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tstr\tr2, [sp, #264]\t@ 0x108\n+\tldr\tr2, [sp, #24]\n+\tldr\tr5, [sp, #12]\n \tstr\tr4, [sp, #144]\t@ 0x90\n \tstr\tr4, [sp, #132]\t@ 0x84\n \tstr\tr4, [sp, #216]\t@ 0xd8\n \tstr\tr4, [sp, #204]\t@ 0xcc\n \tmov.w\tr4, #772\t@ 0x304\n+\tstr\tr2, [sp, #256]\t@ 0x100\n \tstrh.w\tr4, [sp, #140]\t@ 0x8c\n \tstrh.w\tr4, [sp, #212]\t@ 0xd4\n \tmovs\tr4, #1\n \tstr\tr4, [sp, #188]\t@ 0xbc\n \tstr\tr4, [sp, #260]\t@ 0x104\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tstr\tr4, [sp, #264]\t@ 0x108\n-\tldr\tr4, [sp, #24]\n-\tstr\tr2, [sp, #164]\t@ 0xa4\n-\tstr\tr2, [sp, #176]\t@ 0xb0\n-\tstr\tr2, [sp, #224]\t@ 0xe0\n-\tstr\tr2, [sp, #236]\t@ 0xec\n-\tstr\tr2, [sp, #248]\t@ 0xf8\n-\tstr\tr2, [sp, #4]\n-\tnegs\tr2, r4\n-\tstr\tr4, [sp, #256]\t@ 0x100\n-\tadd\tr4, sp, #196\t@ 0xc4\n-\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tnegs\tr4, r2\n+\tadd\tr2, sp, #196\t@ 0xc4\n+\tstr\tr2, [sp, #0]\n \tadd\tr2, sp, #124\t@ 0x7c\n-\tstr\tr4, [sp, #0]\n+\tstr\tr5, [sp, #244]\t@ 0xf4\n \tstr.w\tr9, [sp, #196]\t@ 0xc4\n-\tbl\t1058 <__gridxc_mesh3d_MOD_reducedata.isra.0>\n-\tldr\tr2, [pc, #176]\t@ (5198 <__gridxc_mesh3d_MOD_copymeshdata+0x2a0>)\n-\tldr\tr3, [pc, #168]\t@ (5194 <__gridxc_mesh3d_MOD_copymeshdata+0x29c>)\n+\tstr\tr4, [sp, #200]\t@ 0xc8\n+\tbl\tdec <__gridxc_mesh3d_MOD_reducedata.isra.0>\n+\tldr\tr2, [pc, #180]\t@ (4e2c <__gridxc_mesh3d_MOD_copymeshdata+0x2a4>)\n+\tldr\tr3, [pc, #176]\t@ (4e28 <__gridxc_mesh3d_MOD_copymeshdata+0x2a0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #268]\t@ 0x10c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t5186 <__gridxc_mesh3d_MOD_copymeshdata+0x28e>\n+\tbne.n\t4e14 <__gridxc_mesh3d_MOD_copymeshdata+0x28c>\n \tadd\tsp, #276\t@ 0x114\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #152]\t@ (519c <__gridxc_mesh3d_MOD_copymeshdata+0x2a4>)\n+\tldr\tr3, [pc, #160]\t@ (4e30 <__gridxc_mesh3d_MOD_copymeshdata+0x2a8>)\n \tldr\tr0, [sp, #28]\n \tldr.w\tr3, [r8, r3]\n \tstr\tr3, [sp, #32]\n \tmov\tr2, r3\n \tadd\tr3, sp, #100\t@ 0x64\n \tstr\tr3, [sp, #44]\t@ 0x2c\n-\tbl\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n-\tb.n\t4fd2 <__gridxc_mesh3d_MOD_copymeshdata+0xda>\n+\tbl\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tb.n\t4c64 <__gridxc_mesh3d_MOD_copymeshdata+0xdc>\n \tmov\tr2, r3\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmovs\tr3, #0\n \tldr.w\tfp, [sp, #12]\n+\tmovs\tr3, #0\n+\tvldr\td7, [pc, #104]\t@ 4e18 <__gridxc_mesh3d_MOD_copymeshdata+0x290>\n \tlsls\tr0, r2, #3\n \tmov\tr1, sl\n \tmov\tr2, r3\n \tmov\tip, r3\n \tmov.w\tsl, #0\n \tmov\tr7, r2\n \tmov\tlr, ip\n \tmov.w\tr8, #0\n \tstrd\tfp, r1, [sp, #32]\n \tadd.w\tfp, r9, lr, lsl #3\n \tmovs\tr1, #0\n \tcmp\tr1, r5\n-\tvstr\td16, [fp]\n+\tvstr\td7, [fp]\n \tadd.w\tr1, r1, #1\n \tadd\tfp, r0\n-\tbne.n\t5140 <__gridxc_mesh3d_MOD_copymeshdata+0x248>\n+\tbne.n\t4dce <__gridxc_mesh3d_MOD_copymeshdata+0x246>\n \tadd\tlr, r4\n \tadd.w\tr2, r8, #1\n \tcmp\tr8, r6\n-\tbeq.n\t515c <__gridxc_mesh3d_MOD_copymeshdata+0x264>\n+\tbeq.n\t4dea <__gridxc_mesh3d_MOD_copymeshdata+0x262>\n \tmov\tr8, r2\n-\tb.n\t513a <__gridxc_mesh3d_MOD_copymeshdata+0x242>\n+\tb.n\t4dc8 <__gridxc_mesh3d_MOD_copymeshdata+0x240>\n \tldrd\tfp, r1, [sp, #32]\n \tadd.w\tr2, sl, #1\n \tadd\tip, fp\n \tcmp\tsl, r1\n-\tbeq.n\t516e <__gridxc_mesh3d_MOD_copymeshdata+0x276>\n+\tbeq.n\t4dfc <__gridxc_mesh3d_MOD_copymeshdata+0x274>\n \tmov\tsl, r2\n-\tb.n\t5130 <__gridxc_mesh3d_MOD_copymeshdata+0x238>\n+\tb.n\t4dbe <__gridxc_mesh3d_MOD_copymeshdata+0x236>\n \tmov\tr2, r7\n \tldr\tr7, [sp, #24]\n \tadd.w\tip, r2, #1\n \tadd\tr3, r7\n \tldr\tr7, [sp, #16]\n \tcmp\tr2, r7\n-\tbeq.n\t5182 <__gridxc_mesh3d_MOD_copymeshdata+0x28a>\n+\tbeq.n\t4e10 <__gridxc_mesh3d_MOD_copymeshdata+0x288>\n \tmov\tr2, ip\n-\tb.n\t5128 <__gridxc_mesh3d_MOD_copymeshdata+0x230>\n+\tb.n\t4db6 <__gridxc_mesh3d_MOD_copymeshdata+0x22e>\n \tmov\tsl, r1\n-\tb.n\t5054 <__gridxc_mesh3d_MOD_copymeshdata+0x15c>\n+\tb.n\t4ce6 <__gridxc_mesh3d_MOD_copymeshdata+0x15e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x00000274\n+\t...\n+\t.word\t0x00000278\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000270\n+\t.word\t0x00000274\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000aa\n+\t.word\t0x000000b0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n \n-000051a0 <__gridxc_mesh3d_MOD_redistributemeshdata>:\n+00004e34 <__gridxc_mesh3d_MOD_redistributemeshdata>:\n __gridxc_mesh3d_MOD_redistributemeshdata():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3824]\t@ 0xef0\n \tsub\tsp, #236\t@ 0xec\n-\tldr.w\tr4, [pc, #1108]\t@ 5608 <__gridxc_mesh3d_MOD_redistributemeshdata+0x468>\n+\tldr.w\tr4, [pc, #1096]\t@ 5290 <__gridxc_mesh3d_MOD_redistributemeshdata+0x45c>\n \tmov\tr7, r0\n \tmov\tr6, r2\n \tadd\tr4, pc\n \tmov\tr8, r3\n \tstr\tr0, [sp, #96]\t@ 0x60\n-\tldr.w\tr0, [pc, #1096]\t@ 560c <__gridxc_mesh3d_MOD_redistributemeshdata+0x46c>\n+\tldr.w\tr0, [pc, #1084]\t@ 5294 <__gridxc_mesh3d_MOD_redistributemeshdata+0x460>\n \tldrd\tr2, r3, [r1, #64]\t@ 0x40\n \tldr\tr5, [r1, #24]\n \tldr\tr0, [r4, r0]\n \tsubs\tr3, r3, r2\n \tadds\tr3, #1\n \tcmp\tr5, #0\n \tldr\tr0, [r0, #0]\n@@ -8056,85 +7895,85 @@\n \tldrd\tr3, r2, [r1, #52]\t@ 0x34\n \tstr\tr4, [sp, #100]\t@ 0x64\n \tldr.w\tr9, [r1]\n \tsubs\tr3, r2, r3\n \tldr\tr2, [r1, #60]\t@ 0x3c\n \tstr\tr3, [sp, #88]\t@ 0x58\n \tldr\tr3, [r7, #0]\n-\tldr.w\tr7, [pc, #1028]\t@ 5610 <__gridxc_mesh3d_MOD_redistributemeshdata+0x470>\n+\tldr\tr7, [pc, #1016]\t@ (5298 <__gridxc_mesh3d_MOD_redistributemeshdata+0x464>)\n \tldr\tr1, [r1, #48]\t@ 0x30\n \tcmp\tr3, #0\n \tadd\tr7, pc\n \tstr\tr2, [sp, #76]\t@ 0x4c\n \tstr\tr1, [sp, #60]\t@ 0x3c\n \trsb\tr2, r2, #0\n \tstr\tr2, [sp, #92]\t@ 0x5c\n-\tbne.n\t5240 <__gridxc_mesh3d_MOD_redistributemeshdata+0xa0>\n+\tbne.n\t4ed2 <__gridxc_mesh3d_MOD_redistributemeshdata+0x9e>\n \tldr\tr3, [r6, #0]\n \tcmp\tr3, #0\n-\tbeq.w\t54f6 <__gridxc_mesh3d_MOD_redistributemeshdata+0x356>\n-\tldr\tr3, [pc, #1004]\t@ (5614 <__gridxc_mesh3d_MOD_redistributemeshdata+0x474>)\n+\tbeq.w\t5186 <__gridxc_mesh3d_MOD_redistributemeshdata+0x352>\n+\tldr\tr3, [pc, #992]\t@ (529c <__gridxc_mesh3d_MOD_redistributemeshdata+0x468>)\n \tmovs\tr1, #56\t@ 0x38\n-\tldr\tr0, [pc, #1004]\t@ (5618 <__gridxc_mesh3d_MOD_redistributemeshdata+0x478>)\n+\tldr\tr0, [pc, #992]\t@ (52a0 <__gridxc_mesh3d_MOD_redistributemeshdata+0x46c>)\n \tadd\tr0, pc\n \tldr\tr4, [r7, r3]\n \tldr\tr3, [r4, #0]\n \tblx\tr3\n \tldr.w\tsl, [r6]\n \tcmp.w\tsl, #0\n-\tbgt.n\t5250 <__gridxc_mesh3d_MOD_redistributemeshdata+0xb0>\n-\tb.n\t5282 <__gridxc_mesh3d_MOD_redistributemeshdata+0xe2>\n-\tble.w\t5416 <__gridxc_mesh3d_MOD_redistributemeshdata+0x276>\n+\tbgt.n\t4ee2 <__gridxc_mesh3d_MOD_redistributemeshdata+0xae>\n+\tb.n\t4f14 <__gridxc_mesh3d_MOD_redistributemeshdata+0xe0>\n+\tble.w\t50a8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x274>\n \tldr.w\tsl, [r6]\n \tcmp.w\tsl, #0\n-\tble.w\t5416 <__gridxc_mesh3d_MOD_redistributemeshdata+0x276>\n-\tldr\tr2, [pc, #968]\t@ (561c <__gridxc_mesh3d_MOD_redistributemeshdata+0x47c>)\n+\tble.w\t50a8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x274>\n+\tldr\tr2, [pc, #960]\t@ (52a4 <__gridxc_mesh3d_MOD_redistributemeshdata+0x470>)\n \tmovs\tr1, #1\n \tadd\tr2, pc\n \tadds\tr2, #80\t@ 0x50\n \tsub.w\tr3, r2, #80\t@ 0x50\n-\tb.n\t5262 <__gridxc_mesh3d_MOD_redistributemeshdata+0xc2>\n+\tb.n\t4ef4 <__gridxc_mesh3d_MOD_redistributemeshdata+0xc0>\n \tcmp\tr3, r2\n-\tbeq.n\t5274 <__gridxc_mesh3d_MOD_redistributemeshdata+0xd4>\n+\tbeq.n\t4f06 <__gridxc_mesh3d_MOD_redistributemeshdata+0xd2>\n \tldr.w\tr0, [r3, #4]!\n \tcmp\tsl, r0\n-\tbne.n\t525e <__gridxc_mesh3d_MOD_redistributemeshdata+0xbe>\n+\tbne.n\t4ef0 <__gridxc_mesh3d_MOD_redistributemeshdata+0xbc>\n \tldr.w\tr3, [r2, #-80]\n \tcmp\tr3, #0\n-\tbne.w\t54d6 <__gridxc_mesh3d_MOD_redistributemeshdata+0x336>\n+\tbne.w\t5164 <__gridxc_mesh3d_MOD_redistributemeshdata+0x330>\n \tadds\tr1, #1\n \tadd.w\tr2, r2, #364\t@ 0x16c\n \tcmp\tr1, #21\n-\tbne.n\t5258 <__gridxc_mesh3d_MOD_redistributemeshdata+0xb8>\n-\tldr\tr3, [pc, #916]\t@ (5614 <__gridxc_mesh3d_MOD_redistributemeshdata+0x474>)\n+\tbne.n\t4eea <__gridxc_mesh3d_MOD_redistributemeshdata+0xb6>\n+\tldr\tr3, [pc, #904]\t@ (529c <__gridxc_mesh3d_MOD_redistributemeshdata+0x468>)\n \tldr\tr4, [r7, r3]\n-\tldr\tr0, [pc, #924]\t@ (5620 <__gridxc_mesh3d_MOD_redistributemeshdata+0x480>)\n+\tldr\tr0, [pc, #912]\t@ (52a8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x474>)\n \tmovs\tr1, #44\t@ 0x2c\n \tldr\tr3, [r4, #0]\n \tadd\tr0, pc\n \tblx\tr3\n-\tldr\tr3, [pc, #916]\t@ (5624 <__gridxc_mesh3d_MOD_redistributemeshdata+0x484>)\n+\tldr\tr3, [pc, #908]\t@ (52ac <__gridxc_mesh3d_MOD_redistributemeshdata+0x478>)\n \tadd\tr3, pc\n \tsub.w\tr2, r3, #636\t@ 0x27c\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #120]\t@ 0x78\n \tsub.w\tr2, r3, #632\t@ 0x278\n \tsub.w\tr3, r3, #628\t@ 0x274\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #124]\t@ 0x7c\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #128]\t@ 0x80\n+\tldr\tr3, [pc, #884]\t@ (52b0 <__gridxc_mesh3d_MOD_redistributemeshdata+0x47c>)\n \tmov\tr1, sl\n-\tldr\tr3, [pc, #892]\t@ (5628 <__gridxc_mesh3d_MOD_redistributemeshdata+0x488>)\n \tadd\tr0, sp, #120\t@ 0x78\n \tldr\tr3, [r7, r3]\n \tstr\tr3, [sp, #56]\t@ 0x38\n \tmov\tr2, r3\n \tadd\tr3, sp, #132\t@ 0x84\n-\tbl\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tbl\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n \tldrd\tr3, r4, [sp, #132]\t@ 0x84\n \tsubs\tr4, r4, r3\n \tldrd\tr3, r2, [sp, #140]\t@ 0x8c\n \tsub.w\tfp, r2, r3\n \tldrd\tr3, r2, [sp, #148]\t@ 0x94\n \tadd.w\tsl, fp, #1\n \tsubs\tr3, r2, r3\n@@ -8142,17 +7981,17 @@\n \tstr\tr3, [sp, #64]\t@ 0x40\n \tadds\tr3, #1\n \tstr\tr2, [sp, #68]\t@ 0x44\n \tstr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tmov\tr0, r8\n \tstr\tr3, [sp, #116]\t@ 0x74\n-\tldr\tr3, [pc, #840]\t@ (562c <__gridxc_mesh3d_MOD_redistributemeshdata+0x48c>)\n+\tldr\tr3, [pc, #828]\t@ (52b4 <__gridxc_mesh3d_MOD_redistributemeshdata+0x480>)\n \tldr\tr7, [sp, #52]\t@ 0x34\n-\tldr\tr2, [pc, #840]\t@ (5630 <__gridxc_mesh3d_MOD_redistributemeshdata+0x490>)\n+\tldr\tr2, [pc, #828]\t@ (52b8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x484>)\n \tadd\tr3, pc\n \tmov\tr1, r3\n \tstr\tr3, [sp, #4]\n \tadd\tr2, pc\n \tstr\tr2, [sp, #20]\n \tmovs\tr2, #0\n \tstr\tr2, [sp, #40]\t@ 0x28\n@@ -8176,30 +8015,30 @@\n \tstrd\tr4, fp, [sp, #108]\t@ 0x6c\n \tstr.w\tip, [sp, #80]\t@ 0x50\n \tstr.w\tip, [sp, #104]\t@ 0x68\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d4>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d4\n \tldr\tr0, [sp, #96]\t@ 0x60\n \tmov\tr1, r6\n-\tbl\t260c <__gridxc_mesh3d_MOD_samemeshdistr>\n+\tbl\t2418 <__gridxc_mesh3d_MOD_samemeshdistr>\n \tcmp\tr0, #0\n-\tbeq.w\t547c <__gridxc_mesh3d_MOD_redistributemeshdata+0x2dc>\n+\tbeq.w\t510e <__gridxc_mesh3d_MOD_redistributemeshdata+0x2da>\n \tldr\tr7, [sp, #52]\t@ 0x34\n \tcmp\tr7, #0\n-\tble.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tble.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tldr\tr3, [sp, #56]\t@ 0x38\n \tcmp\tr3, #0\n-\tble.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tble.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tcmp.w\tsl, #0\n-\tble.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tble.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tldr\tr3, [sp, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tble.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tble.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tcmp\tr5, #1\n-\tbne.w\t5558 <__gridxc_mesh3d_MOD_redistributemeshdata+0x3b8>\n+\tbne.w\t51e2 <__gridxc_mesh3d_MOD_redistributemeshdata+0x3ae>\n \tldrd\tr7, r3, [r8, #20]\n \tmovs\tr1, #0\n \tldrd\tsl, r6, [r8]\n \tmul.w\tip, r3, r7\n \tldr.w\tr3, [r8, #60]\t@ 0x3c\n \tstr\tr3, [sp, #84]\t@ 0x54\n \tmov\tlr, r6\n@@ -8214,77 +8053,77 @@\n \tstr.w\tlr, [sp, #96]\t@ 0x60\n \tmla\tr3, r1, r3, lr\n \tstr\tr3, [sp, #68]\t@ 0x44\n \tmovs\tr3, #0\n \tldrd\tr2, r1, [sp, #68]\t@ 0x44\n \tmov\tr6, r0\n \tmovs\tr5, #0\n-\tstrd\tr0, r3, [sp, #52]\t@ 0x34\n+\tstrd\tr3, r0, [sp, #52]\t@ 0x34\n \tmla\tlr, r1, r3, r2\n \tmla\tr2, r5, r8, lr\n \tadd.w\tr0, r9, r6, lsl #3\n \tmovs\tr1, #0\n \tmla\tr2, r7, r2, sl\n-\tvldmia\tr0!, {d16}\n+\tvldmia\tr0!, {d7}\n \tcmp\tr1, r4\n \tadd.w\tr1, r1, #1\n-\tvstr\td16, [r2]\n+\tvstr\td7, [r2]\n \tadd\tr2, ip\n-\tblt.n\t53b0 <__gridxc_mesh3d_MOD_redistributemeshdata+0x210>\n+\tblt.n\t5042 <__gridxc_mesh3d_MOD_redistributemeshdata+0x20e>\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tfp, r5\n \tadd\tr6, r3\n \tadd.w\tr3, r5, #1\n-\tble.n\t53d2 <__gridxc_mesh3d_MOD_redistributemeshdata+0x232>\n+\tble.n\t5064 <__gridxc_mesh3d_MOD_redistributemeshdata+0x230>\n \tmov\tr5, r3\n-\tb.n\t53a2 <__gridxc_mesh3d_MOD_redistributemeshdata+0x202>\n-\tldrd\tr0, r3, [sp, #52]\t@ 0x34\n+\tb.n\t5034 <__gridxc_mesh3d_MOD_redistributemeshdata+0x200>\n+\tldrd\tr3, r0, [sp, #52]\t@ 0x34\n \tldr\tr2, [sp, #60]\t@ 0x3c\n \tadds\tr1, r3, #1\n \tadd\tr0, r2\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tcmp\tr3, r2\n-\tbge.n\t53e6 <__gridxc_mesh3d_MOD_redistributemeshdata+0x246>\n+\tbge.n\t5078 <__gridxc_mesh3d_MOD_redistributemeshdata+0x244>\n \tmov\tr3, r1\n-\tb.n\t5392 <__gridxc_mesh3d_MOD_redistributemeshdata+0x1f2>\n+\tb.n\t5024 <__gridxc_mesh3d_MOD_redistributemeshdata+0x1f0>\n \tldrd\tr1, r6, [sp, #88]\t@ 0x58\n \tldr\tr3, [sp, #76]\t@ 0x4c\n \tadds\tr1, #1\n \tldr.w\tlr, [sp, #96]\t@ 0x60\n \tadd\tr6, r3\n \tldr\tr3, [sp, #80]\t@ 0x50\n \tcmp\tr3, r1\n-\tbge.n\t537e <__gridxc_mesh3d_MOD_redistributemeshdata+0x1de>\n-\tldr\tr2, [pc, #568]\t@ (5634 <__gridxc_mesh3d_MOD_redistributemeshdata+0x494>)\n-\tldr\tr3, [pc, #524]\t@ (560c <__gridxc_mesh3d_MOD_redistributemeshdata+0x46c>)\n+\tbge.n\t5010 <__gridxc_mesh3d_MOD_redistributemeshdata+0x1dc>\n+\tldr\tr2, [pc, #556]\t@ (52bc <__gridxc_mesh3d_MOD_redistributemeshdata+0x488>)\n+\tldr\tr3, [pc, #516]\t@ (5294 <__gridxc_mesh3d_MOD_redistributemeshdata+0x460>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #228]\t@ 0xe4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t5602 <__gridxc_mesh3d_MOD_redistributemeshdata+0x462>\n+\tbne.w\t528c <__gridxc_mesh3d_MOD_redistributemeshdata+0x458>\n \tadd\tsp, #236\t@ 0xec\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #508]\t@ (5614 <__gridxc_mesh3d_MOD_redistributemeshdata+0x474>)\n+\tldr\tr3, [pc, #496]\t@ (529c <__gridxc_mesh3d_MOD_redistributemeshdata+0x468>)\n \tmovs\tr1, #56\t@ 0x38\n-\tldr\tr0, [pc, #540]\t@ (5638 <__gridxc_mesh3d_MOD_redistributemeshdata+0x498>)\n+\tldr\tr0, [pc, #528]\t@ (52c0 <__gridxc_mesh3d_MOD_redistributemeshdata+0x48c>)\n \tadd\tr0, pc\n \tldr\tr4, [r7, r3]\n \tldr\tr3, [r4, #0]\n \tblx\tr3\n \tldr.w\tsl, [r6]\n \tcmp.w\tsl, #0\n-\tbne.w\t5238 <__gridxc_mesh3d_MOD_redistributemeshdata+0x98>\n-\tldr\tr0, [pc, #520]\t@ (563c <__gridxc_mesh3d_MOD_redistributemeshdata+0x49c>)\n+\tbne.w\t4eca <__gridxc_mesh3d_MOD_redistributemeshdata+0x96>\n+\tldr\tr0, [pc, #512]\t@ (52c4 <__gridxc_mesh3d_MOD_redistributemeshdata+0x490>)\n \tmovs\tr1, #44\t@ 0x2c\n \tldr\tr3, [r4, #0]\n \tadd\tr0, pc\n \tblx\tr3\n-\tldr\tr3, [pc, #516]\t@ (5640 <__gridxc_mesh3d_MOD_redistributemeshdata+0x4a0>)\n+\tldr\tr3, [pc, #504]\t@ (52c8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x494>)\n \tstr.w\tsl, [sp, #132]\t@ 0x84\n \tadd\tr3, pc\n \tstr.w\tsl, [sp, #140]\t@ 0x8c\n \tsub.w\tr2, r3, #272\t@ 0x110\n \tstr.w\tsl, [sp, #148]\t@ 0x94\n \tldr\tr1, [r2, #0]\n \tsub.w\tr2, r3, #268\t@ 0x10c\n@@ -8298,93 +8137,95 @@\n \tstr\tr3, [sp, #56]\t@ 0x38\n \tstrd\tsl, r3, [sp, #124]\t@ 0x7c\n \tsubs\tr3, #1\n \tstr\tr4, [sp, #136]\t@ 0x88\n \tstr.w\tfp, [sp, #144]\t@ 0x90\n \tstr\tr3, [sp, #64]\t@ 0x40\n \tstr\tr3, [sp, #152]\t@ 0x98\n-\tb.n\t52dc <__gridxc_mesh3d_MOD_redistributemeshdata+0x13c>\n+\tb.n\t4f6e <__gridxc_mesh3d_MOD_redistributemeshdata+0x13a>\n \tldr\tr3, [sp, #100]\t@ 0x64\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstrd\tr8, r3, [sp]\n \tmovs\tr2, #1\n+\tstrd\tr8, r3, [sp]\n \tldr\tr3, [sp, #72]\t@ 0x48\n-\tmovs\tr4, #8\n \tstr\tr3, [sp, #188]\t@ 0xbc\n \tldr\tr3, [sp, #84]\t@ 0x54\n \tstr\tr3, [sp, #200]\t@ 0xc8\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tstr\tr3, [sp, #192]\t@ 0xc0\n \tldr\tr3, [sp, #88]\t@ 0x58\n \tstr\tr3, [sp, #212]\t@ 0xd4\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tstr\tr3, [sp, #204]\t@ 0xcc\n \tldr\tr3, [sp, #52]\t@ 0x34\n \tstr\tr3, [sp, #224]\t@ 0xe0\n-\tstr\tr0, [sp, #184]\t@ 0xb8\n \tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr4, [sp, #92]\t@ 0x5c\n+\tstrd\tr0, r0, [sp, #168]\t@ 0xa8\n+\tstr\tr0, [sp, #184]\t@ 0xb8\n \tstr\tr0, [sp, #196]\t@ 0xc4\n \tstr\tr0, [sp, #208]\t@ 0xd0\n-\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tadd\tr0, sp, #120\t@ 0x78\n \tstr\tr3, [sp, #216]\t@ 0xd8\n \tadd\tr3, sp, #132\t@ 0x84\n \tstr\tr2, [sp, #220]\t@ 0xdc\n \tadd\tr2, sp, #156\t@ 0x9c\n-\tstr\tr0, [sp, #160]\t@ 0xa0\n-\tadd\tr0, sp, #120\t@ 0x78\n \tldr\tr1, [sp, #96]\t@ 0x60\n+\tstr\tr4, [sp, #160]\t@ 0xa0\n+\tmovs\tr4, #8\n+\tstr\tr5, [sp, #180]\t@ 0xb4\n \tstr\tr4, [sp, #176]\t@ 0xb0\n \tstr\tr4, [sp, #164]\t@ 0xa4\n \tmov.w\tr4, #772\t@ 0x304\n-\tvstr\td16, [sp, #168]\t@ 0xa8\n-\tstr\tr5, [sp, #180]\t@ 0xb4\n \tstr.w\tr9, [sp, #156]\t@ 0x9c\n \tstrh.w\tr4, [sp, #172]\t@ 0xac\n-\tbl\t4ef8 <__gridxc_mesh3d_MOD_copymeshdata>\n-\tb.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n-\tsubs\tr3, r1, #1\n+\tbl\t4b88 <__gridxc_mesh3d_MOD_copymeshdata>\n+\tb.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tmov.w\tr2, #364\t@ 0x16c\n+\tsubs\tr3, r1, #1\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [pc, #352]\t@ (5644 <__gridxc_mesh3d_MOD_redistributemeshdata+0x4a4>)\n+\tldr\tr2, [pc, #348]\t@ (52cc <__gridxc_mesh3d_MOD_redistributemeshdata+0x498>)\n+\tadds\tr3, #88\t@ 0x58\n \tadd\tr2, pc\n-\tadds\tr1, r2, r3\n-\tadd.w\tr3, r1, #92\t@ 0x5c\n-\tvld1.32\t{d16}, [r3]\n-\tldr\tr3, [r1, #100]\t@ 0x64\n-\tvstr\td16, [sp, #120]\t@ 0x78\n-\tb.n\t52a6 <__gridxc_mesh3d_MOD_redistributemeshdata+0x106>\n+\tadd\tr3, r2\n+\tadds\tr2, r3, #4\n+\tldr\tr3, [r3, #4]\n+\tstr\tr3, [sp, #120]\t@ 0x78\n+\tldr\tr3, [r2, #4]\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [r2, #8]\n+\tstr\tr3, [sp, #128]\t@ 0x80\n+\tb.n\t4f3a <__gridxc_mesh3d_MOD_redistributemeshdata+0x106>\n+\tmovs\tr2, #8\n+\tstr.w\tr2, [r8, #20]\n+\tstr.w\tr2, [r8, #8]\n \tldr\tr2, [sp, #72]\t@ 0x48\n-\tvmov.i32\td16, #0\t@ 0x00000000\n \tstr.w\tr2, [r8, #32]\n \tldr\tr2, [sp, #84]\t@ 0x54\n \tstr.w\tr2, [r8, #44]\t@ 0x2c\n \tldr\tr2, [sp, #88]\t@ 0x58\n \tstr.w\tr2, [r8, #56]\t@ 0x38\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tstr.w\tr2, [r8, #48]\t@ 0x30\n \tldr\tr2, [sp, #52]\t@ 0x34\n \tstr.w\tr2, [r8, #68]\t@ 0x44\n-\tstr.w\tr3, [r8, #28]\n \tldr\tr2, [sp, #76]\t@ 0x4c\n+\tstrd\tr3, r3, [r8, #12]\n+\tstr.w\tr3, [r8, #28]\n \tstr.w\tr3, [r8, #40]\t@ 0x28\n \tstr.w\tr3, [r8, #52]\t@ 0x34\n-\tmov.w\tr3, #772\t@ 0x304\n-\tvstr\td16, [r8, #12]\n-\tstrh.w\tr3, [r8, #16]\n+\tmovs\tr3, #1\n+\tstrd\tr2, r3, [r8, #60]\t@ 0x3c\n \tldr\tr3, [sp, #92]\t@ 0x5c\n-\tstr.w\tr2, [r8, #60]\t@ 0x3c\n-\tmovs\tr2, #1\n \tstr.w\tr3, [r8, #4]\n-\tmovs\tr3, #8\n+\tmov.w\tr3, #772\t@ 0x304\n \tstr.w\tr5, [r8, #24]\n \tstr.w\tr0, [r8, #36]\t@ 0x24\n-\tstr.w\tr1, [r8, #48]\t@ 0x30\n \tstr.w\tr9, [r8]\n-\tstr.w\tr2, [r8, #64]\t@ 0x40\n-\tstr.w\tr3, [r8, #20]\n-\tstr.w\tr3, [r8, #8]\n-\tb.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tstrh.w\tr3, [r8, #16]\n+\tb.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tlsls\tr6, r5, #3\n \tldr.w\tr3, [r8]\n \tldrd\tsl, r5, [r8, #20]\n \tstr\tr3, [sp, #52]\t@ 0x34\n \tldr.w\tr3, [r8, #48]\t@ 0x30\n \tmov.w\tlr, #0\n \tldr.w\tr1, [r8, #4]\n@@ -8408,113 +8249,111 @@\n \tstr\tr0, [sp, #68]\t@ 0x44\n \tmla\tlr, r3, r1, r2\n \tmla\tr2, r8, r7, lr\n \tldr\tr3, [sp, #52]\t@ 0x34\n \tadd.w\tr0, r9, ip, lsl #3\n \tmovs\tr1, #0\n \tmla\tr2, sl, r2, r3\n-\tvldr\td16, [r0]\n+\tvldr\td7, [r0]\n \tcmp\tr1, r4\n \tadd\tr0, r6\n \tadd.w\tr1, r1, #1\n-\tvstr\td16, [r2]\n+\tvstr\td7, [r2]\n \tadd\tr2, r5\n-\tblt.n\t55b4 <__gridxc_mesh3d_MOD_redistributemeshdata+0x414>\n+\tblt.n\t523e <__gridxc_mesh3d_MOD_redistributemeshdata+0x40a>\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr7, fp\n \tadd\tip, r3\n \tadd.w\tr3, r7, #1\n-\tbge.n\t55d8 <__gridxc_mesh3d_MOD_redistributemeshdata+0x438>\n+\tbge.n\t5262 <__gridxc_mesh3d_MOD_redistributemeshdata+0x42e>\n \tmov\tr7, r3\n-\tb.n\t55a4 <__gridxc_mesh3d_MOD_redistributemeshdata+0x404>\n+\tb.n\t522e <__gridxc_mesh3d_MOD_redistributemeshdata+0x3fa>\n \tldr\tr2, [sp, #60]\t@ 0x3c\n \tldr\tr0, [sp, #68]\t@ 0x44\n \tldr\tr3, [sp, #56]\t@ 0x38\n \tadd\tr0, r2\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tadds\tr1, r3, #1\n \tcmp\tr3, r2\n-\tbge.n\t55ec <__gridxc_mesh3d_MOD_redistributemeshdata+0x44c>\n+\tbge.n\t5276 <__gridxc_mesh3d_MOD_redistributemeshdata+0x442>\n \tmov\tr3, r1\n-\tb.n\t5594 <__gridxc_mesh3d_MOD_redistributemeshdata+0x3f4>\n+\tb.n\t521e <__gridxc_mesh3d_MOD_redistributemeshdata+0x3ea>\n \tldrd\tr2, lr, [sp, #96]\t@ 0x60\n \tldr\tr3, [sp, #76]\t@ 0x4c\n \tadds\tr2, #1\n \tadd\tlr, r3\n \tldr\tr3, [sp, #80]\t@ 0x50\n \tldrd\tr1, ip, [sp, #88]\t@ 0x58\n \tcmp\tr3, r2\n-\tbge.n\t5582 <__gridxc_mesh3d_MOD_redistributemeshdata+0x3e2>\n-\tb.n\t53fa <__gridxc_mesh3d_MOD_redistributemeshdata+0x25a>\n+\tbge.n\t520c <__gridxc_mesh3d_MOD_redistributemeshdata+0x3d8>\n+\tb.n\t508c <__gridxc_mesh3d_MOD_redistributemeshdata+0x258>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\t.word\t0x0000044a\n+\t.word\t0x0000043e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003fc\n+\t.word\t0x000003f2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000003e8\n+\t.word\t0x000003de\n R_ARM_REL32\t.LC58\n-\t.word\t0x000003c4\n+\t.word\t0x000003ba\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x00000394\n+\t.word\t0x0000038a\n R_ARM_REL32\t.LC62\n-\t.word\t0x00000392\n+\t.word\t0x00000388\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n-\t.word\t0x00000340\n+\t.word\t0x00000336\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000033e\n+\t.word\t0x00000334\n R_ARM_REL32\t.LC61\n-\t.word\t0x00000232\n+\t.word\t0x00000228\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000218\n+\t.word\t0x0000020e\n R_ARM_REL32\t.LC58\n-\t.word\t0x00000202\n+\t.word\t0x000001f8\n R_ARM_REL32\t.LC62\n-\t.word\t0x000001fc\n+\t.word\t0x000001f2\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n-\t.word\t0x0000015e\n+\t.word\t0x00000156\n R_ARM_REL32\t__gridxc_mesh3d_MOD_storedmeshdistr\n \n-00005648 <__gridxc_mesh3d_MOD_addmeshdata>:\n+000052d0 <__gridxc_mesh3d_MOD_addmeshdata>:\n __gridxc_mesh3d_MOD_addmeshdata():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3808]\t@ 0xee0\n \tsub\tsp, #252\t@ 0xfc\n \tmov\tr7, r3\n-\tldr\tr3, [pc, #392]\t@ (57e8 <__gridxc_mesh3d_MOD_addmeshdata+0x1a0>)\n+\tldr\tr3, [pc, #384]\t@ (5468 <__gridxc_mesh3d_MOD_addmeshdata+0x198>)\n \tmov\tr5, r0\n \tldr\tr6, [r2, #24]\n \tstr\tr1, [sp, #64]\t@ 0x40\n-\tldr\tr1, [pc, #388]\t@ (57ec <__gridxc_mesh3d_MOD_addmeshdata+0x1a4>)\n+\tldr\tr1, [pc, #380]\t@ (546c <__gridxc_mesh3d_MOD_addmeshdata+0x19c>)\n \tcmp\tr6, #0\n \tldr\tr4, [sp, #288]\t@ 0x120\n \tit\teq\n \tmoveq\tr6, #1\n \tadd\tr1, pc\n \tldr\tr0, [sp, #292]\t@ 0x124\n-\tldr.w\tsl, [pc, #380]\t@ 57f0 <__gridxc_mesh3d_MOD_addmeshdata+0x1a8>\n+\tldr.w\tsl, [pc, #372]\t@ 5470 <__gridxc_mesh3d_MOD_addmeshdata+0x1a0>\n \tldr.w\tr8, [r4, #24]\n \tldr\tr3, [r1, r3]\n \tadd\tsl, pc\n \tcmp.w\tr8, #0\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #244]\t@ 0xf4\n \tmov.w\tr3, #0\n-\tmov.w\tr3, #1\n \tit\teq\n-\tmoveq\tr8, r3\n+\tmoveq.w\tr8, #1\n \tldrd\tr1, r3, [r2, #64]\t@ 0x40\n \tsubs\tr3, r3, r1\n \tadds\tr3, #1\n \tstr\tr3, [sp, #36]\t@ 0x24\n \tldrd\tr1, r3, [r4, #64]\t@ 0x40\n \tsubs\tr3, r3, r1\n \tadd.w\tfp, r3, #1\n@@ -8546,42 +8385,41 @@\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tldr\tr3, [r4, #36]\t@ 0x24\n \tstr\tr3, [sp, #48]\t@ 0x30\n \tldr\tr3, [r4, #48]\t@ 0x30\n \tldr.w\tr9, [r2, #60]\t@ 0x3c\n \tldr\tr4, [r4, #60]\t@ 0x3c\n \tstr\tr3, [sp, #56]\t@ 0x38\n-\tcbz\tr0, 56fe <__gridxc_mesh3d_MOD_addmeshdata+0xb6>\n+\tcbz\tr0, 5384 <__gridxc_mesh3d_MOD_addmeshdata+0xb4>\n \tmovs\tr2, #0\n \tmov\tr1, r7\n-\tbl\t477c <__gridxc_mesh3d_MOD_associatemeshtask>\n+\tbl\t4470 <__gridxc_mesh3d_MOD_associatemeshtask>\n \tldr\tr1, [r7, #0]\n \tcmp\tr1, #0\n-\tbne.n\t57cc <__gridxc_mesh3d_MOD_addmeshdata+0x184>\n+\tbne.n\t544e <__gridxc_mesh3d_MOD_addmeshdata+0x17e>\n \tldr\tr3, [r5, #0]\n \tadd\tr7, sp, #76\t@ 0x4c\n \tstr\tr1, [sp, #76]\t@ 0x4c\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #80]\t@ 0x50\n \tldr\tr3, [r5, #4]\n \tstr\tr1, [sp, #84]\t@ 0x54\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #88]\t@ 0x58\n \tldr\tr3, [r5, #8]\n \tstr\tr1, [sp, #92]\t@ 0x5c\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #96]\t@ 0x60\n \tldr\tr3, [sp, #16]\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tstr\tr3, [sp, #132]\t@ 0x84\n \tmovs\tr2, #0\n-\tldr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #132]\t@ 0x84\n \tmov\tr0, r5\n-\tstr\tr3, [sp, #144]\t@ 0x90\n+\tldr\tr3, [sp, #24]\n \tmovs\tr5, #8\n+\tstr\tr3, [sp, #144]\t@ 0x90\n \tldr\tr3, [sp, #20]\n \tstr\tr3, [sp, #136]\t@ 0x88\n \tldr\tr3, [sp, #32]\n \tstr\tr3, [sp, #156]\t@ 0x9c\n \tldr\tr3, [sp, #28]\n \tstr\tr3, [sp, #148]\t@ 0x94\n \tldr\tr3, [sp, #36]\t@ 0x24\n@@ -8591,78 +8429,79 @@\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tstr\tr3, [sp, #204]\t@ 0xcc\n \tldr\tr3, [sp, #52]\t@ 0x34\n \tstr\tr3, [sp, #216]\t@ 0xd8\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tstr\tr3, [sp, #208]\t@ 0xd0\n \tldr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr3, [sp, #228]\t@ 0xe4\n-\tldr\tr3, [sp, #56]\t@ 0x38\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tstr\tr3, [sp, #220]\t@ 0xdc\n+\tstr\tr6, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #228]\t@ 0xe4\n \trsb\tr3, r9, #0\n-\tstr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #116]\t@ 0x74\n \tstr\tr3, [sp, #104]\t@ 0x68\n \tmov\tr3, r7\n-\tvstr\td16, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #184]\t@ 0xb8\n-\tstr\tr6, [sp, #124]\t@ 0x7c\n+\tstr\tr2, [sp, #188]\t@ 0xbc\n+\tstr\tr2, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #140]\t@ 0x8c\n \tstr.w\tr8, [sp, #196]\t@ 0xc4\n \tstr.w\tr9, [sp, #160]\t@ 0xa0\n-\tstr\tr2, [sp, #140]\t@ 0x8c\n \tstr\tr2, [sp, #152]\t@ 0x98\n+\tstr\tr2, [sp, #184]\t@ 0xb8\n \tstr\tr2, [sp, #200]\t@ 0xc8\n \tstr\tr2, [sp, #212]\t@ 0xd4\n \tstr\tr2, [sp, #224]\t@ 0xe0\n \tstr\tr2, [sp, #4]\n \tldr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr6, [sp, #56]\t@ 0x38\n \tstr\tr2, [sp, #172]\t@ 0xac\n-\tnegs\tr2, r4\n-\tstr\tr4, [sp, #232]\t@ 0xe8\n-\tadd\tr4, sp, #172\t@ 0xac\n-\tstr\tr2, [sp, #176]\t@ 0xb0\n+\tadd\tr2, sp, #172\t@ 0xac\n+\tstr\tr2, [sp, #0]\n \tadd\tr2, sp, #100\t@ 0x64\n-\tstr\tr4, [sp, #0]\n \tstr\tr5, [sp, #120]\t@ 0x78\n \tstr\tr5, [sp, #108]\t@ 0x6c\n \tstr\tr5, [sp, #192]\t@ 0xc0\n \tstr\tr5, [sp, #180]\t@ 0xb4\n \tmov.w\tr5, #772\t@ 0x304\n+\tstr\tr4, [sp, #232]\t@ 0xe8\n+\tnegs\tr4, r4\n \tstrh.w\tr5, [sp, #116]\t@ 0x74\n \tstrh.w\tr5, [sp, #188]\t@ 0xbc\n \tmovs\tr5, #1\n+\tstr\tr6, [sp, #220]\t@ 0xdc\n \tstr\tr5, [sp, #164]\t@ 0xa4\n \tstrd\tr5, fp, [sp, #236]\t@ 0xec\n-\tbl\t1058 <__gridxc_mesh3d_MOD_reducedata.isra.0>\n-\tldr\tr2, [pc, #64]\t@ (57f4 <__gridxc_mesh3d_MOD_addmeshdata+0x1ac>)\n-\tldr\tr3, [pc, #48]\t@ (57e8 <__gridxc_mesh3d_MOD_addmeshdata+0x1a0>)\n+\tstr\tr4, [sp, #176]\t@ 0xb0\n+\tbl\tdec <__gridxc_mesh3d_MOD_reducedata.isra.0>\n+\tldr\tr2, [pc, #60]\t@ (5474 <__gridxc_mesh3d_MOD_addmeshdata+0x1a4>)\n+\tldr\tr3, [pc, #48]\t@ (5468 <__gridxc_mesh3d_MOD_addmeshdata+0x198>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #244]\t@ 0xf4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t57e2 <__gridxc_mesh3d_MOD_addmeshdata+0x19a>\n+\tbne.n\t5464 <__gridxc_mesh3d_MOD_addmeshdata+0x194>\n \tadd\tsp, #252\t@ 0xfc\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #40]\t@ (57f8 <__gridxc_mesh3d_MOD_addmeshdata+0x1b0>)\n+\tldr\tr3, [pc, #40]\t@ (5478 <__gridxc_mesh3d_MOD_addmeshdata+0x1a8>)\n \tadd\tr7, sp, #76\t@ 0x4c\n \tmov\tr0, r5\n \tldr.w\tr3, [sl, r3]\n \tstr\tr3, [sp, #68]\t@ 0x44\n \tmov\tr2, r3\n \tmov\tr3, r7\n-\tbl\t24c8 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n-\tb.n\t571e <__gridxc_mesh3d_MOD_addmeshdata+0xd6>\n+\tbl\t22d4 <__gridxc_mesh3d_MOD_nodemeshbox.part.0.isra.0>\n+\tb.n\t53a4 <__gridxc_mesh3d_MOD_addmeshdata+0xd4>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000017a\n+\t.word\t0x00000172\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000170\n+\t.word\t0x00000168\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000003a\n+\t.word\t0x00000038\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_config_MOD_gridxc_mynode\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -65,77 +65,79 @@\n 0x000003e0 79737263 64617461 2e30005f 5f677269 ysrcdata.0.__gri\n 0x000003f0 6478635f 6d657368 33645f4d 4f445f5f dxc_mesh3d_MOD__\n 0x00000400 5f636f70 795f6772 69647863 5f6d6573 _copy_gridxc_mes\n 0x00000410 6833645f 5461736b 74797065 006d656d h3d_Tasktype.mem\n 0x00000420 63707900 5f5f6772 69647863 5f6d6573 cpy.__gridxc_mes\n 0x00000430 6833645f 4d4f445f 5f5f636f 70795f67 h3d_MOD___copy_g\n 0x00000440 72696478 635f6d65 73683364 5f446973 ridxc_mesh3d_Dis\n- 0x00000450 74727479 7065006d 656d7365 74006d61 trtype.memset.ma\n- 0x00000460 6c6c6f63 005f6766 6f727472 616e5f6f lloc._gfortran_o\n- 0x00000470 735f6572 726f725f 6174005f 67666f72 s_error_at._gfor\n- 0x00000480 7472616e 5f72756e 74696d65 5f657272 tran_runtime_err\n- 0x00000490 6f72005f 5f677269 6478635f 6d657368 or.__gridxc_mesh\n- 0x000004a0 33645f4d 4f445f73 746f7265 646d6573 3d_MOD_storedmes\n- 0x000004b0 68646973 7472005f 474c4f42 414c5f4f hdistr._GLOBAL_O\n- 0x000004c0 46465345 545f5441 424c455f 005f5f67 FFSET_TABLE_.__g\n- 0x000004d0 72696478 635f7379 735f4d4f 445f6469 ridxc_sys_MOD_di\n- 0x000004e0 65005f5f 67726964 78635f63 6f6e6669 e.__gridxc_confi\n- 0x000004f0 675f4d4f 445f6772 69647863 5f746f74 g_MOD_gridxc_tot\n- 0x00000500 6e6f6465 73006c6f 67005f67 666f7274 nodes.log._gfort\n- 0x00000510 72616e5f 706f775f 69345f69 34005f5f ran_pow_i4_i4.__\n- 0x00000520 73746163 6b5f6368 6b5f6661 696c005f stack_chk_fail._\n- 0x00000530 5f737461 636b5f63 686b5f67 75617264 _stack_chk_guard\n- 0x00000540 00667265 65005f67 666f7274 72616e5f .free._gfortran_\n- 0x00000550 72756e74 696d655f 6572726f 725f6174 runtime_error_at\n- 0x00000560 005f5f67 72696478 635f6d65 73683364 .__gridxc_mesh3d\n- 0x00000570 5f4d4f44 5f73616d 656d6573 68646973 _MOD_samemeshdis\n- 0x00000580 7472005f 5f677269 6478635f 6d657368 tr.__gridxc_mesh\n- 0x00000590 33645f4d 4f445f6e 6f64656d 65736862 3d_MOD_nodemeshb\n- 0x000005a0 6f78005f 5f677269 6478635f 6d657368 ox.__gridxc_mesh\n- 0x000005b0 33645f4d 4f445f6d 796d6573 68626f78 3d_MOD_mymeshbox\n- 0x000005c0 005f5f67 72696478 635f636f 6e666967 .__gridxc_config\n- 0x000005d0 5f4d4f44 5f677269 6478635f 6d796e6f _MOD_gridxc_myno\n- 0x000005e0 6465005f 5f677269 6478635f 6d657368 de.__gridxc_mesh\n- 0x000005f0 33645f4d 4f445f66 7265656d 65736874 3d_MOD_freemesht\n- 0x00000600 61736b00 5f5f6772 69647863 5f6d6573 ask.__gridxc_mes\n- 0x00000610 6833645f 4d4f445f 73746f72 65646d65 h3d_MOD_storedme\n- 0x00000620 73687461 736b005f 5f677269 6478635f shtask.__gridxc_\n- 0x00000630 6d657368 33645f4d 4f445f66 7265656d mesh3d_MOD_freem\n- 0x00000640 65736864 69737472 005f5f67 72696478 eshdistr.__gridx\n- 0x00000650 635f6d65 73683364 5f4d4f44 5f736574 c_mesh3d_MOD_set\n- 0x00000660 6d657368 64697374 72005f67 666f7274 meshdistr._gfort\n- 0x00000670 72616e5f 696e7465 726e616c 5f706163 ran_internal_pac\n- 0x00000680 6b005f67 666f7274 72616e5f 696e7465 k._gfortran_inte\n- 0x00000690 726e616c 5f756e70 61636b00 5f5f6772 rnal_unpack.__gr\n- 0x000006a0 69647863 5f616c6c 6f635f4d 4f445f72 idxc_alloc_MOD_r\n- 0x000006b0 65616c6c 6f635f64 34005f5f 67726964 ealloc_d4.__grid\n- 0x000006c0 78635f61 6c6c6f63 5f4d4f44 5f646561 xc_alloc_MOD_dea\n- 0x000006d0 6c6c6f63 5f643400 5f5f6772 69647863 lloc_d4.__gridxc\n- 0x000006e0 5f6d6573 6833645f 4d4f445f 6666746d _mesh3d_MOD_fftm\n- 0x000006f0 65736864 69737472 005f5f67 72696478 eshdistr.__gridx\n- 0x00000700 635f6d65 73683364 5f4d4f44 5f617373 c_mesh3d_MOD_ass\n- 0x00000710 6f636961 74656d65 73687461 736b005f ociatemeshtask._\n- 0x00000720 5f677269 6478635f 6d657368 33645f4d _gridxc_mesh3d_M\n- 0x00000730 4f445f63 6f70796d 65736864 61746100 OD_copymeshdata.\n- 0x00000740 5f5f6772 69647863 5f6d6573 6833645f __gridxc_mesh3d_\n- 0x00000750 4d4f445f 72656469 73747269 62757465 MOD_redistribute\n- 0x00000760 6d657368 64617461 005f5f67 72696478 meshdata.__gridx\n- 0x00000770 635f6d65 73683364 5f4d4f44 5f616464 c_mesh3d_MOD_add\n- 0x00000780 6d657368 64617461 005f5f67 72696478 meshdata.__gridx\n- 0x00000790 635f6d65 73683364 5f4d4f44 5f6e7461 c_mesh3d_MOD_nta\n- 0x000007a0 736b6964 005f5f67 72696478 635f6d65 skid.__gridxc_me\n- 0x000007b0 73683364 5f4d4f44 5f6e6469 73747269 sh3d_MOD_ndistri\n- 0x000007c0 64005f5f 67726964 78635f6d 65736833 d.__gridxc_mesh3\n- 0x000007d0 645f4d4f 445f5f5f 76746162 5f677269 d_MOD___vtab_gri\n- 0x000007e0 6478635f 6d657368 33645f54 61736b74 dxc_mesh3d_Taskt\n- 0x000007f0 79706500 5f5f6772 69647863 5f6d6573 ype.__gridxc_mes\n- 0x00000800 6833645f 4d4f445f 5f5f7674 61625f67 h3d_MOD___vtab_g\n- 0x00000810 72696478 635f6d65 73683364 5f446973 ridxc_mesh3d_Dis\n- 0x00000820 74727479 7065005f 5f677269 6478635f trtype.__gridxc_\n- 0x00000830 6d657368 33645f4d 4f445f5f 5f646566 mesh3d_MOD___def\n- 0x00000840 5f696e69 745f6772 69647863 5f6d6573 _init_gridxc_mes\n- 0x00000850 6833645f 5461736b 74797065 005f5f67 h3d_Tasktype.__g\n- 0x00000860 72696478 635f6d65 73683364 5f4d4f44 ridxc_mesh3d_MOD\n- 0x00000870 5f5f5f64 65665f69 6e69745f 67726964 ___def_init_grid\n- 0x00000880 78635f6d 65736833 645f4469 73747274 xc_mesh3d_Distrt\n- 0x00000890 79706500 ype.\n+ 0x00000450 74727479 7065005f 5f616561 62695f75 trtype.__aeabi_u\n+ 0x00000460 69646976 005f5f61 65616269 5f696469 idiv.__aeabi_idi\n+ 0x00000470 76006d65 6d736574 006d616c 6c6f6300 v.memset.malloc.\n+ 0x00000480 5f67666f 72747261 6e5f6f73 5f657272 _gfortran_os_err\n+ 0x00000490 6f725f61 74005f67 666f7274 72616e5f or_at._gfortran_\n+ 0x000004a0 72756e74 696d655f 6572726f 72005f5f runtime_error.__\n+ 0x000004b0 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n+ 0x000004c0 445f7374 6f726564 6d657368 64697374 D_storedmeshdist\n+ 0x000004d0 72005f47 4c4f4241 4c5f4f46 46534554 r._GLOBAL_OFFSET\n+ 0x000004e0 5f544142 4c455f00 5f5f6772 69647863 _TABLE_.__gridxc\n+ 0x000004f0 5f737973 5f4d4f44 5f646965 005f5f67 _sys_MOD_die.__g\n+ 0x00000500 72696478 635f636f 6e666967 5f4d4f44 ridxc_config_MOD\n+ 0x00000510 5f677269 6478635f 746f746e 6f646573 _gridxc_totnodes\n+ 0x00000520 005f5f61 65616269 5f696469 766d6f64 .__aeabi_idivmod\n+ 0x00000530 006c6f67 005f6766 6f727472 616e5f70 .log._gfortran_p\n+ 0x00000540 6f775f69 345f6934 005f5f73 7461636b ow_i4_i4.__stack\n+ 0x00000550 5f63686b 5f666169 6c005f5f 73746163 _chk_fail.__stac\n+ 0x00000560 6b5f6368 6b5f6775 61726400 66726565 k_chk_guard.free\n+ 0x00000570 005f6766 6f727472 616e5f72 756e7469 ._gfortran_runti\n+ 0x00000580 6d655f65 72726f72 5f617400 5f5f6772 me_error_at.__gr\n+ 0x00000590 69647863 5f6d6573 6833645f 4d4f445f idxc_mesh3d_MOD_\n+ 0x000005a0 73616d65 6d657368 64697374 72005f5f samemeshdistr.__\n+ 0x000005b0 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n+ 0x000005c0 445f6e6f 64656d65 7368626f 78005f5f D_nodemeshbox.__\n+ 0x000005d0 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n+ 0x000005e0 445f6d79 6d657368 626f7800 5f5f6772 D_mymeshbox.__gr\n+ 0x000005f0 69647863 5f636f6e 6669675f 4d4f445f idxc_config_MOD_\n+ 0x00000600 67726964 78635f6d 796e6f64 65005f5f gridxc_mynode.__\n+ 0x00000610 67726964 78635f6d 65736833 645f4d4f gridxc_mesh3d_MO\n+ 0x00000620 445f6672 65656d65 73687461 736b005f D_freemeshtask._\n+ 0x00000630 5f677269 6478635f 6d657368 33645f4d _gridxc_mesh3d_M\n+ 0x00000640 4f445f73 746f7265 646d6573 68746173 OD_storedmeshtas\n+ 0x00000650 6b005f5f 67726964 78635f6d 65736833 k.__gridxc_mesh3\n+ 0x00000660 645f4d4f 445f6672 65656d65 73686469 d_MOD_freemeshdi\n+ 0x00000670 73747200 5f5f6772 69647863 5f6d6573 str.__gridxc_mes\n+ 0x00000680 6833645f 4d4f445f 7365746d 65736864 h3d_MOD_setmeshd\n+ 0x00000690 69737472 005f6766 6f727472 616e5f69 istr._gfortran_i\n+ 0x000006a0 6e746572 6e616c5f 7061636b 005f6766 nternal_pack._gf\n+ 0x000006b0 6f727472 616e5f69 6e746572 6e616c5f ortran_internal_\n+ 0x000006c0 756e7061 636b005f 5f677269 6478635f unpack.__gridxc_\n+ 0x000006d0 616c6c6f 635f4d4f 445f7265 616c6c6f alloc_MOD_reallo\n+ 0x000006e0 635f6434 005f5f67 72696478 635f616c c_d4.__gridxc_al\n+ 0x000006f0 6c6f635f 4d4f445f 6465616c 6c6f635f loc_MOD_dealloc_\n+ 0x00000700 6434005f 5f677269 6478635f 6d657368 d4.__gridxc_mesh\n+ 0x00000710 33645f4d 4f445f66 66746d65 73686469 3d_MOD_fftmeshdi\n+ 0x00000720 73747200 5f5f6772 69647863 5f6d6573 str.__gridxc_mes\n+ 0x00000730 6833645f 4d4f445f 6173736f 63696174 h3d_MOD_associat\n+ 0x00000740 656d6573 68746173 6b005f5f 67726964 emeshtask.__grid\n+ 0x00000750 78635f6d 65736833 645f4d4f 445f636f xc_mesh3d_MOD_co\n+ 0x00000760 70796d65 73686461 7461005f 5f677269 pymeshdata.__gri\n+ 0x00000770 6478635f 6d657368 33645f4d 4f445f72 dxc_mesh3d_MOD_r\n+ 0x00000780 65646973 74726962 7574656d 65736864 edistributemeshd\n+ 0x00000790 61746100 5f5f6772 69647863 5f6d6573 ata.__gridxc_mes\n+ 0x000007a0 6833645f 4d4f445f 6164646d 65736864 h3d_MOD_addmeshd\n+ 0x000007b0 61746100 5f5f6772 69647863 5f6d6573 ata.__gridxc_mes\n+ 0x000007c0 6833645f 4d4f445f 6e746173 6b696400 h3d_MOD_ntaskid.\n+ 0x000007d0 5f5f6772 69647863 5f6d6573 6833645f __gridxc_mesh3d_\n+ 0x000007e0 4d4f445f 6e646973 74726964 005f5f67 MOD_ndistrid.__g\n+ 0x000007f0 72696478 635f6d65 73683364 5f4d4f44 ridxc_mesh3d_MOD\n+ 0x00000800 5f5f5f76 7461625f 67726964 78635f6d ___vtab_gridxc_m\n+ 0x00000810 65736833 645f5461 736b7479 7065005f esh3d_Tasktype._\n+ 0x00000820 5f677269 6478635f 6d657368 33645f4d _gridxc_mesh3d_M\n+ 0x00000830 4f445f5f 5f767461 625f6772 69647863 OD___vtab_gridxc\n+ 0x00000840 5f6d6573 6833645f 44697374 72747970 _mesh3d_Distrtyp\n+ 0x00000850 65005f5f 67726964 78635f6d 65736833 e.__gridxc_mesh3\n+ 0x00000860 645f4d4f 445f5f5f 6465665f 696e6974 d_MOD___def_init\n+ 0x00000870 5f677269 6478635f 6d657368 33645f54 _gridxc_mesh3d_T\n+ 0x00000880 61736b74 79706500 5f5f6772 69647863 asktype.__gridxc\n+ 0x00000890 5f6d6573 6833645f 4d4f445f 5f5f6465 _mesh3d_MOD___de\n+ 0x000008a0 665f696e 69745f67 72696478 635f6d65 f_init_gridxc_me\n+ 0x000008b0 73683364 5f446973 74727479 706500 sh3d_Distrtype.\n \n"}]}, {"source1": "minvec.F90.o", "source2": "minvec.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 2668 (bytes into file)\n+ Start of section headers: 2864 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0xa6c:\n+There are 12 section headers, starting at offset 0xb30:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 00063c 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 000944 0000c0 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 000674 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 000674 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 000674 00005b 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0006d0 00000c 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 0006dc 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0006dc 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 000710 000140 10 10 10 4\n- [10] .strtab STRTAB 00000000 000850 0000f1 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 000a04 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0006a8 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 0009c0 000108 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0006e0 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 0006e0 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0006e0 00005b 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 00073c 00000c 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 000748 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000748 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 000778 000150 10 10 10 4\n+ [10] .strtab STRTAB 00000000 0008c8 0000f8 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 000ac8 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,23 +1,24 @@\n \n-Symbol table '.symtab' contains 20 entries:\n+Symbol table '.symtab' contains 21 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 3: 00000030 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 5: 00000368 0 NOTYPE LOCAL DEFAULT 1 $d\n- 6: 00000388 0 NOTYPE LOCAL DEFAULT 1 $t\n- 7: 00000628 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 00000328 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 6: 00000348 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 7: 00000694 0 NOTYPE LOCAL DEFAULT 1 $d\n 8: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 9: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 10: 00000001 1596 FUNC GLOBAL DEFAULT 1 __gridxc_minvec_MOD_minvec\n+ 10: 00000001 1704 FUNC GLOBAL DEFAULT 1 __gridxc_minvec_MOD_minvec\n 11: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_volcel\n 12: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sorting_MOD_ordix\n 13: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sorting_MOD_order\n 14: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n 15: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 16: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 17: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n 18: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_cellsubs_MOD_reclat\n- 19: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 19: 00000000 0 NOTYPE GLOBAL DEFAULT UND lround\n+ 20: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,27 +1,36 @@\n \n-Relocation section '.rel.text' at offset 0x944 contains 24 entries:\n+Relocation section '.rel.text' at offset 0x9c0 contains 33 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000032 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n-00000112 00000c0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_ordix\n-00000120 00000d0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_order\n-0000012e 00000d0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_order\n-0000020c 00000e0a R_ARM_THM_CALL 00000000 memcpy\n-0000021e 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n+00000034 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n+00000126 00000c0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_ordix\n+00000134 00000d0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_order\n+00000140 00000d0a R_ARM_THM_CALL 00000000 __gridxc_sorting_MOD_order\n+00000228 00000e0a R_ARM_THM_CALL 00000000 memcpy\n+0000023a 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n 00000282 00000e0a R_ARM_THM_CALL 00000000 memcpy\n 00000294 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n-000002e0 00000e0a R_ARM_THM_CALL 00000000 memcpy\n-000002f2 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n-00000370 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000374 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000378 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000037c 0000111a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000380 00000203 R_ARM_REL32 00000000 .LC0\n-00000384 00000803 R_ARM_REL32 00000000 .rodata\n-0000038e 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n-000003ca 0000120a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n-00000624 0000130a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000628 00000803 R_ARM_REL32 00000000 .rodata\n-0000062c 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000630 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000634 0000111a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000638 00000303 R_ARM_REL32 00000030 .LC3\n+000002d0 00000e0a R_ARM_THM_CALL 00000000 memcpy\n+000002e2 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n+00000330 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000334 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000338 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000033c 0000111a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000340 00000203 R_ARM_REL32 00000000 .LC0\n+00000344 00000803 R_ARM_REL32 00000000 .rodata\n+0000034c 00000b0a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_volcel\n+00000388 0000120a R_ARM_THM_CALL 00000000 __gridxc_cellsubs_MOD_reclat\n+000003dc 0000130a R_ARM_THM_CALL 00000000 lround\n+00000400 0000130a R_ARM_THM_CALL 00000000 lround\n+0000042c 0000130a R_ARM_THM_CALL 00000000 lround\n+00000460 0000130a R_ARM_THM_CALL 00000000 lround\n+00000488 0000130a R_ARM_THM_CALL 00000000 lround\n+000004b0 0000130a R_ARM_THM_CALL 00000000 lround\n+000004dc 0000130a R_ARM_THM_CALL 00000000 lround\n+00000504 0000130a R_ARM_THM_CALL 00000000 lround\n+0000052c 0000130a R_ARM_THM_CALL 00000000 lround\n+00000690 0000140a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000694 00000803 R_ARM_REL32 00000000 .rodata\n+00000698 00000f19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000069c 0000101a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000006a0 0000111a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000006a4 00000303 R_ARM_REL32 00000030 .LC3\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,9 +1,10 @@\n-KF)F F:F\n-KF:F9FPF\n+CF\"FPF)F\n+CF)F\"FPF\n+CF\"F!FHF\n MINVEC: BASIS VECTORS ARE LINEARLY DEPENDENT\n MINVEC: ERROR: Iteration has not converged\n __gridxc_minvec_MOD_minvec\n __gridxc_cellsubs_MOD_volcel\n __gridxc_sorting_MOD_ordix\n __gridxc_sorting_MOD_order\n _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -5,487 +5,522 @@\n \n 00000000 <__gridxc_minvec_MOD_minvec>:\n __gridxc_minvec_MOD_minvec():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3656]\t@ 0xe48\n-\tmov\tr4, r2\n-\tldr\tr2, [pc, #856]\t@ (370 <__gridxc_minvec_MOD_minvec+0x370>)\n-\tldr\tr3, [pc, #856]\t@ (374 <__gridxc_minvec_MOD_minvec+0x374>)\n-\tsub\tsp, #340\t@ 0x154\n-\tadd\tr2, pc\n+\tstr.w\tr0, [ip, #3624]\t@ 0xe28\n+\tldr\tr3, [pc, #792]\t@ (330 <__gridxc_minvec_MOD_minvec+0x330>)\n+\tsub\tsp, #372\t@ 0x174\n+\tmov\tr6, r2\n+\tldr\tr2, [pc, #792]\t@ (334 <__gridxc_minvec_MOD_minvec+0x334>)\n+\tadd\tr3, pc\n \tmov\tr5, r0\n-\tmov\tr6, r1\n-\tldr.w\tfp, [pc, #852]\t@ 378 <__gridxc_minvec_MOD_minvec+0x378>\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tmov\tr4, r3\n+\tldr\tr3, [pc, #784]\t@ (338 <__gridxc_minvec_MOD_minvec+0x338>)\n+\tadd\tr2, pc\n+\tmov\tfp, r1\n \tldr\tr3, [r2, r3]\n-\tadd\tfp, pc\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #332]\t@ 0x14c\n+\tstr\tr3, [sp, #364]\t@ 0x16c\n \tmov.w\tr3, #0\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n-\tvabs.f64\td17, d0\n-\tvldr\td16, [pc, #812]\t@ 368 <__gridxc_minvec_MOD_minvec+0x368>\n-\tvstr\td0, [sp, #88]\t@ 0x58\n-\tvcmpe.f64\td17, d16\n-\tvstr\td17, [sp, #24]\n+\tvabs.f64\td12, d0\n+\tvldr\td7, [pc, #744]\t@ 328 <__gridxc_minvec_MOD_minvec+0x328>\n+\tvstr\td0, [sp, #152]\t@ 0x98\n+\tvcmpe.f64\td12, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t60 <__gridxc_minvec_MOD_minvec+0x60>\n-\tldr\tr3, [pc, #808]\t@ (37c <__gridxc_minvec_MOD_minvec+0x37c>)\n+\tbpl.n\t5c <__gridxc_minvec_MOD_minvec+0x5c>\n+\tldr\tr3, [pc, #748]\t@ (33c <__gridxc_minvec_MOD_minvec+0x33c>)\n \tmovs\tr1, #44\t@ 0x2c\n-\tldr\tr0, [pc, #808]\t@ (380 <__gridxc_minvec_MOD_minvec+0x380>)\n+\tldr\tr0, [pc, #748]\t@ (340 <__gridxc_minvec_MOD_minvec+0x340>)\n \tadd\tr0, pc\n-\tldr.w\tr3, [fp, r3]\n+\tldr\tr3, [r4, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvldr\td19, [r5, #56]\t@ 0x38\n-\tadd.w\tr9, sp, #148\t@ 0x94\n-\tvldr\td15, [r5, #8]\n-\tadd.w\tsl, sp, #184\t@ 0xb8\n-\tvldr\td11, [r5, #32]\n-\tadd.w\tr8, sp, #256\t@ 0x100\n-\tvldr\td20, [r5, #48]\t@ 0x30\n-\tvmul.f64\td16, d19, d19\n-\tvldr\td14, [r5]\n-\tvmul.f64\td18, d15, d15\n-\tvldr\td12, [r5, #24]\n-\tvmul.f64\td17, d11, d11\n-\tvfma.f64\td16, d20, d20\n-\tvldr\td21, [r5, #16]\n-\tvfma.f64\td18, d14, d14\n-\tvldr\td22, [r5, #64]\t@ 0x40\n-\tvfma.f64\td17, d12, d12\n-\tvldr\td13, [r5, #40]\t@ 0x28\n-\tldr\tr7, [pc, #728]\t@ (384 <__gridxc_minvec_MOD_minvec+0x384>)\n+\tvldr\td7, [r5]\n+\tadd.w\tr8, sp, #180\t@ 0xb4\n+\tvldr\td3, [r5, #8]\n+\tadd.w\tsl, sp, #192\t@ 0xc0\n+\tvldr\td2, [r5, #16]\n+\tadd.w\tr9, sp, #216\t@ 0xd8\n+\tvmov.f64\td6, d7\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [r5, #32]\n+\tvmla.f64\td7, d3, d3\n+\tvldr\td4, [r5, #56]\t@ 0x38\n+\tvstr\td3, [sp, #96]\t@ 0x60\n+\tadd\tr7, sp, #288\t@ 0x120\n+\tvstr\td6, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td6, d5, d5\n+\tvstr\td5, [sp, #120]\t@ 0x78\n \tmovs\tr3, #100\t@ 0x64\n-\tvfma.f64\td16, d22, d22\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tvfma.f64\td18, d21, d21\n-\tadd\tr7, pc\n-\tvfma.f64\td17, d13, d13\n-\tadd\tr3, sp, #160\t@ 0xa0\n-\tstr\tr5, [sp, #100]\t@ 0x64\n+\tvmla.f64\td7, d2, d2\n+\tvstr\td5, [sp, #248]\t@ 0xf8\n+\tvldr\td5, [r5, #40]\t@ 0x28\n+\tvstr\td3, [sp, #224]\t@ 0xe0\n+\tvldr\td3, [r5, #48]\t@ 0x30\n+\tldr\tr4, [pc, #652]\t@ (344 <__gridxc_minvec_MOD_minvec+0x344>)\n+\tvldr\td15, [pc, #624]\t@ 328 <__gridxc_minvec_MOD_minvec+0x328>\n+\tadd\tr4, pc\n \tstr\tr3, [sp, #80]\t@ 0x50\n-\tstrd\tr4, fp, [sp, #136]\t@ 0x88\n-\tvstr\td19, [sp, #64]\t@ 0x40\n-\tvstr\td20, [sp, #56]\t@ 0x38\n-\tvstr\td21, [sp, #48]\t@ 0x30\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvstr\td14, [sp, #184]\t@ 0xb8\n-\tvstr\td15, [sp, #192]\t@ 0xc0\n-\tvstr\td21, [sp, #200]\t@ 0xc8\n-\tvstr\td12, [sp, #208]\t@ 0xd0\n-\tvstr\td11, [sp, #216]\t@ 0xd8\n-\tvstr\td13, [sp, #224]\t@ 0xe0\n-\tvstr\td20, [sp, #232]\t@ 0xe8\n-\tvstr\td19, [sp, #240]\t@ 0xf0\n-\tvstr\td22, [sp, #248]\t@ 0xf8\n-\tvstr\td18, [sp, #160]\t@ 0xa0\n-\tvstr\td17, [sp, #168]\t@ 0xa8\n-\tvstr\td16, [sp, #176]\t@ 0xb0\n-\tldr\tr4, [sp, #80]\t@ 0x50\n-\tadds\tr1, r7, #4\n-\tmov\tr3, r9\n-\tmov\tr5, r1\n-\tmov\tr0, r4\n-\tmov\tr2, r7\n+\tvstr\td4, [sp, #48]\t@ 0x30\n+\tadds\tr3, r4, #4\n+\tvstr\td7, [sp, #192]\t@ 0xc0\n+\tvldr\td7, [r5, #24]\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvstr\td2, [sp, #40]\t@ 0x28\n+\tvmla.f64\td6, d7, d7\n+\tvstr\td7, [sp, #104]\t@ 0x68\n+\tvstr\td7, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td7, d4, d4\n+\tvmla.f64\td7, d3, d3\n+\tvstr\td2, [sp, #232]\t@ 0xe8\n+\tvstr\td4, [sp, #272]\t@ 0x110\n+\tvmla.f64\td6, d5, d5\n+\tvstr\td3, [sp, #136]\t@ 0x88\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvstr\td5, [sp, #128]\t@ 0x80\n+\tvstr\td5, [sp, #256]\t@ 0x100\n+\tvstr\td6, [sp, #200]\t@ 0xc8\n+\tvldr\td6, [r5, #64]\t@ 0x40\n+\tvmla.f64\td7, d6, d6\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvstr\td6, [sp, #280]\t@ 0x118\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n+\tstr\tr5, [sp, #168]\t@ 0xa8\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tmov\tr3, r8\n+\tmov\tr2, r4\n+\tmov\tr0, sl\n+\tmov\tr1, r5\n \tbl\t0 <__gridxc_sorting_MOD_ordix>\n R_ARM_THM_CALL\t__gridxc_sorting_MOD_ordix\n-\tmov\tr3, r9\n+\tmov\tr3, r8\n \tmov\tr1, r5\n-\tmov\tr0, r4\n-\tmov\tr2, r7\n+\tmov\tr2, r4\n+\tmov\tr0, sl\n \tmovs\tr5, #0\n \tbl\t0 <__gridxc_sorting_MOD_order>\n R_ARM_THM_CALL\t__gridxc_sorting_MOD_order\n-\tmov\tr3, r9\n-\tmov\tr2, r7\n-\tmov\tr1, r7\n-\tmov\tr0, sl\n-\tmov\tfp, r9\n+\tmov\tr3, r8\n+\tmov\tr2, r4\n+\tmov\tr1, r4\n+\tmov\tr0, r9\n \tbl\t0 <__gridxc_sorting_MOD_order>\n R_ARM_THM_CALL\t__gridxc_sorting_MOD_order\n-\tvldr\td16, [sp, #184]\t@ 0xb8\n-\tmov\tr9, r5\n-\tvmov\ts15, r9\n-\teor.w\tr4, r9, #1\n-\tmov.w\tr5, #4294967295\t@ 0xffffffff\n-\tvstr\td16, [sp, #16]\n-\tvcvt.f64.s32\td23, s15\n-\tvldr\td16, [sp, #192]\t@ 0xc0\n-\tstr\tr7, [sp, #96]\t@ 0x60\n-\tvstr\td16, [sp]\n-\tvldr\td16, [sp, #200]\t@ 0xc8\n-\tvstr\td16, [sp, #8]\n-\tcmp\tr5, #1\n-\tand.w\tr3, r4, #1\n-\tit\teq\n+\tvldr\td7, [sp, #216]\t@ 0xd8\n+\tstr.w\tr8, [sp, #144]\t@ 0x90\n+\tmov\tr8, r5\n+\tstr\tr4, [sp, #88]\t@ 0x58\n+\tvstr\td7, [sp, #32]\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tstr.w\tsl, [sp, #148]\t@ 0x94\n+\tvstr\td7, [sp, #16]\n+\tvldr\td7, [sp, #232]\t@ 0xe8\n+\tvstr\td7, [sp, #24]\n+\tvmov\ts15, r8\n+\tvldr\td6, [sp, #32]\n+\teor.w\tsl, r8, #1\n+\tmov.w\tr4, #4294967295\t@ 0xffffffff\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td6, [sp]\n+\tvldr\td6, [sp, #16]\n+\tvmul.f64\td11, d6, d7\n+\tvldr\td6, [sp, #24]\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td7, [sp, #8]\n+\tcmp\tr4, #1\n+\tite\teq\n \tmoveq\tr3, #0\n+\tandne.w\tr3, sl, #1\n \tcmp\tr3, #0\n-\tbne.w\t360 <__gridxc_minvec_MOD_minvec+0x360>\n-\tvmov\ts15, r5\n-\tmov.w\tr7, #4294967295\t@ 0xffffffff\n-\tvcvt.f64.s32\td22, s15\n-\tvldr\td9, [sp, #216]\t@ 0xd8\n-\torrs.w\tr3, r5, r7\n-\tvldr\td16, [sp]\n+\tbne.w\t322 <__gridxc_minvec_MOD_minvec+0x322>\n+\tvmov\ts15, r4\n+\tmov.w\tr5, #4294967295\t@ 0xffffffff\n+\tvcvt.f64.s32\td8, s15\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\torrs.w\tr3, r4, r5\n+\tvldr\td9, [sp]\n+\tvmov.f64\td13, d11\n \tit\teq\n-\tmoveq\tr7, #1\n-\tvldr\td10, [sp, #208]\t@ 0xd0\n-\tvmov\ts15, r7\n-\tvmul.f64\td9, d22, d9\n-\tvldr\td20, [sp, #240]\t@ 0xf0\n-\tvfma.f64\td9, d16, d23\n-\tvldr\td16, [sp, #16]\n-\tvcvt.f64.s32\td21, s15\n-\tvmul.f64\td10, d22, d10\n-\tvldr\td8, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td10, d16, d23\n-\tvldr\td19, [sp, #232]\t@ 0xe8\n-\tvldr\td16, [sp, #8]\n-\tvfma.f64\td9, d20, d21\n-\tvmul.f64\td8, d22, d8\n-\tvldr\td18, [sp, #248]\t@ 0xf8\n-\tvfma.f64\td8, d16, d23\n-\tvfma.f64\td10, d21, d19\n-\tvldr\td16, [sp, #176]\t@ 0xb0\n-\tvfma.f64\td8, d18, d21\n-\tvldr\td18, [pc, #400]\t@ 368 <__gridxc_minvec_MOD_minvec+0x368>\n-\tvmul.f64\td17, d9, d9\n-\tvfma.f64\td17, d10, d10\n-\tvfma.f64\td17, d8, d8\n-\tvadd.f64\td18, d17, d18\n-\tvstr\td17, [sp, #40]\t@ 0x28\n-\tvcmpe.f64\td16, d18\n-\tvstr\td18, [sp, #32]\n+\tmoveq\tr5, #1\n+\tvldr\td6, [sp, #264]\t@ 0x108\n+\tvmla.f64\td9, d8, d7\n+\tvldr\td7, [sp, #248]\t@ 0xf8\n+\tvldr\td14, [sp, #8]\n+\tvmla.f64\td13, d8, d7\n+\tvmov\ts15, r5\n+\tvcvt.f64.s32\td7, s15\n+\tvmla.f64\td9, d7, d6\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tvmla.f64\td13, d7, d6\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvmla.f64\td14, d8, d6\n+\tvldr\td6, [sp, #280]\t@ 0x118\n+\tvmul.f64\td10, d9, d9\n+\tvmla.f64\td14, d7, d6\n+\tvldr\td7, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td10, d13, d13\n+\tvmla.f64\td10, d14, d14\n+\tvadd.f64\td5, d10, d15\n+\tvcmpe.f64\td7, d5\n+\tvstr\td5, [sp, #72]\t@ 0x48\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.w\t326 <__gridxc_minvec_MOD_minvec+0x326>\n+\tbls.n\t306 <__gridxc_minvec_MOD_minvec+0x306>\n \tmovs\tr2, #72\t@ 0x48\n-\tmov\tr1, sl\n-\tmov\tr0, r8\n-\tvstr\td23, [sp, #128]\t@ 0x80\n-\tvstr\td22, [sp, #104]\t@ 0x68\n+\tmov\tr1, r9\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tr0, r8\n-\tvstr\td10, [sp, #304]\t@ 0x130\n-\tvstr\td9, [sp, #312]\t@ 0x138\n-\tvstr\td8, [sp, #320]\t@ 0x140\n+\tmov\tr0, r7\n+\tvstr\td9, [sp, #336]\t@ 0x150\n+\tvstr\td13, [sp, #344]\t@ 0x158\n+\tvstr\td14, [sp, #352]\t@ 0x160\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n-\tvldr\td17, [sp, #88]\t@ 0x58\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [sp, #24]\n-\tvldr\td18, [pc, #312]\t@ 368 <__gridxc_minvec_MOD_minvec+0x368>\n-\tvdiv.f64\td17, d16, d17\n-\tvabs.f64\td16, d0\n-\tvsub.f64\td16, d16, d19\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #120]\t@ 0x78\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d18\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvabs.f64\td7, d0\n+\tvdiv.f64\td6, d4, d6\n+\tvsub.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #160]\t@ 0xa0\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d15\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t608 <__gridxc_minvec_MOD_minvec+0x608>\n-\tvldr\td18, [sp, #32]\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvldr\td22, [sp, #104]\t@ 0x68\n-\tvldr\td23, [sp, #128]\t@ 0x80\n-\tvcmpe.f64\td16, d18\n-\tvstr\td18, [sp, #112]\t@ 0x70\n+\tbmi.w\t670 <__gridxc_minvec_MOD_minvec+0x670>\n+\tvldr\td7, [sp, #200]\t@ 0xc8\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t326 <__gridxc_minvec_MOD_minvec+0x326>\n+\tbls.n\t306 <__gridxc_minvec_MOD_minvec+0x306>\n \tmovs\tr2, #72\t@ 0x48\n-\tmov\tr1, sl\n-\tmov\tr0, r8\n-\tvstr\td23, [sp, #104]\t@ 0x68\n-\tvstr\td22, [sp, #32]\n+\tmov\tr1, r9\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tr0, r8\n-\tvstr\td10, [sp, #280]\t@ 0x118\n-\tvstr\td9, [sp, #288]\t@ 0x120\n-\tvstr\td8, [sp, #296]\t@ 0x128\n+\tmov\tr0, r7\n+\tvstr\td9, [sp, #312]\t@ 0x138\n+\tvstr\td13, [sp, #320]\t@ 0x140\n+\tvstr\td14, [sp, #328]\t@ 0x148\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n-\tvabs.f64\td16, d0\n-\tvldr\td19, [sp, #24]\n-\tvldr\td17, [sp, #120]\t@ 0x78\n-\tvldr\td18, [pc, #192]\t@ 368 <__gridxc_minvec_MOD_minvec+0x368>\n-\tvsub.f64\td16, d16, d19\n-\tvmul.f64\td16, d16, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d18\n+\tvabs.f64\td7, d0\n+\tvldr\td6, [sp, #160]\t@ 0xa0\n+\tvsub.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d15\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t5b4 <__gridxc_minvec_MOD_minvec+0x5b4>\n-\tvldr\td16, [sp, #160]\t@ 0xa0\n-\tvldr\td18, [sp, #112]\t@ 0x70\n-\tvldr\td22, [sp, #32]\n-\tvldr\td23, [sp, #104]\t@ 0x68\n-\tvcmpe.f64\td16, d18\n+\tbmi.w\t622 <__gridxc_minvec_MOD_minvec+0x622>\n+\tvldr\td7, [sp, #192]\t@ 0xc0\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t326 <__gridxc_minvec_MOD_minvec+0x326>\n+\tbls.n\t306 <__gridxc_minvec_MOD_minvec+0x306>\n \tmovs\tr2, #72\t@ 0x48\n-\tmov\tr1, sl\n-\tmov\tr0, r8\n+\tmov\tr1, r9\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tr0, r8\n-\tvstr\td10, [sp, #256]\t@ 0x100\n-\tvstr\td9, [sp, #264]\t@ 0x108\n-\tvstr\td8, [sp, #272]\t@ 0x110\n+\tmov\tr0, r7\n+\tvstr\td9, [sp, #288]\t@ 0x120\n+\tvstr\td13, [sp, #296]\t@ 0x128\n+\tvstr\td14, [sp, #304]\t@ 0x130\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n-\tvabs.f64\td16, d0\n-\tvldr\td19, [sp, #24]\n-\tvldr\td17, [sp, #120]\t@ 0x78\n-\tvldr\td18, [pc, #100]\t@ 368 <__gridxc_minvec_MOD_minvec+0x368>\n-\tvldr\td22, [sp, #32]\n-\tvsub.f64\td16, d16, d19\n-\tvldr\td23, [sp, #104]\t@ 0x68\n-\tvmul.f64\td16, d16, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d18\n+\tvabs.f64\td7, d0\n+\tvldr\td6, [sp, #160]\t@ 0xa0\n+\tvsub.f64\td7, d7, d12\n+\tvmul.f64\td7, d7, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d15\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t616 <__gridxc_minvec_MOD_minvec+0x616>\n-\tadds\tr7, #1\n-\tcmp\tr7, #2\n-\tbne.w\t17a <__gridxc_minvec_MOD_minvec+0x17a>\n+\tbmi.w\t680 <__gridxc_minvec_MOD_minvec+0x680>\n \tadds\tr5, #1\n \tcmp\tr5, #2\n-\tbne.w\t15e <__gridxc_minvec_MOD_minvec+0x15e>\n-\tcmp.w\tr9, #0\n-\tbne.n\t388 <__gridxc_minvec_MOD_minvec+0x388>\n-\tmov.w\tr9, #1\n-\tmov.w\tr5, #4294967295\t@ 0xffffffff\n-\tvmov\ts15, r9\n-\teor.w\tr4, r9, #1\n-\tcmp\tr5, #1\n-\tand.w\tr3, r4, #1\n-\tvcvt.f64.s32\td23, s15\n-\tit\teq\n-\tmoveq\tr3, #0\n-\tcmp\tr3, #0\n-\tbeq.w\t16e <__gridxc_minvec_MOD_minvec+0x16e>\n-\tadds\tr5, #1\n-\tb.n\t15e <__gridxc_minvec_MOD_minvec+0x15e>\n-\tnop.w\n+\tbne.w\t1b4 <__gridxc_minvec_MOD_minvec+0x1b4>\n+\tadds\tr4, #1\n+\tcmp\tr4, #2\n+\tbne.w\t198 <__gridxc_minvec_MOD_minvec+0x198>\n+\tcmp.w\tr8, #0\n+\tbne.n\t348 <__gridxc_minvec_MOD_minvec+0x348>\n+\tmov.w\tr8, #1\n+\tb.n\t168 <__gridxc_minvec_MOD_minvec+0x168>\n+\tadds\tr4, #1\n+\tb.n\t198 <__gridxc_minvec_MOD_minvec+0x198>\n+\tnop\n \t.word\t0xe2308c3a\n \t.word\t0x3e45798e\n-\t.word\t0x00000350\n+\t.word\t0x00000310\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000034c\n+\t.word\t0x0000030a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n+\t...\n+ R_ARM_GOT32\t__stack_chk_guard\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000326\n+\t.word\t0x000002e8\n R_ARM_REL32\t.LC0\n-\t.word\t0x000002ca\n+\t.word\t0x00000286\n R_ARM_REL32\t.rodata\n-\tldr\tr5, [sp, #100]\t@ 0x64\n-\tldr\tr4, [sp, #136]\t@ 0x88\n-\tmov\tr0, sl\n+\tldr\tr5, [sp, #168]\t@ 0xa8\n+\tmov\tr0, r9\n \tbl\t0 <__gridxc_cellsubs_MOD_volcel>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_volcel\n \tvcmpe.f64\td0, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t3c0 <__gridxc_minvec_MOD_minvec+0x3c0>\n-\tvldr\td18, [sp, #232]\t@ 0xe8\n-\tvldr\td17, [sp, #240]\t@ 0xf0\n-\tvldr\td16, [sp, #248]\t@ 0xf8\n-\tvneg.f64\td18, d18\n-\tvneg.f64\td17, d17\n-\tvneg.f64\td16, d16\n-\tvstr\td18, [sp, #232]\t@ 0xe8\n-\tvstr\td17, [sp, #240]\t@ 0xf0\n-\tvstr\td16, [sp, #248]\t@ 0xf8\n-\tldr\tr2, [pc, #612]\t@ (628 <__gridxc_minvec_MOD_minvec+0x628>)\n-\tmov\tr1, r8\n+\tbpl.n\t37e <__gridxc_minvec_MOD_minvec+0x37e>\n+\tvldr\td7, [sp, #264]\t@ 0x108\n+\tvneg.f64\td7, d7\n+\tvstr\td7, [sp, #264]\t@ 0x108\n+\tvldr\td7, [sp, #272]\t@ 0x110\n+\tvneg.f64\td7, d7\n+\tvstr\td7, [sp, #272]\t@ 0x110\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvneg.f64\td7, d7\n+\tvstr\td7, [sp, #280]\t@ 0x118\n+\tldr\tr2, [pc, #788]\t@ (694 <__gridxc_minvec_MOD_minvec+0x694>)\n+\tmov\tr1, r7\n \tmov\tr0, r5\n \tadd\tr2, pc\n \tadds\tr2, #8\n \tbl\t0 <__gridxc_cellsubs_MOD_reclat>\n R_ARM_THM_CALL\t__gridxc_cellsubs_MOD_reclat\n-\tvldr\td20, [sp, #288]\t@ 0x120\n-\tvldr\td18, [sp, #192]\t@ 0xc0\n-\tvldr\td29, [sp, #280]\t@ 0x118\n-\tvldr\td24, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td22, d18, d20\n-\tvldr\td28, [sp, #296]\t@ 0x128\n-\tvldr\td17, [sp, #216]\t@ 0xd8\n-\tvfma.f64\td22, d24, d29\n-\tvldr\td19, [sp, #264]\t@ 0x108\n-\tvldr\td5, [sp, #200]\t@ 0xc8\n-\tvldr\td27, [sp, #256]\t@ 0x100\n-\tvmul.f64\td30, d17, d20\n-\tvldr\td31, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td21, d18, d19\n-\tvfma.f64\td22, d5, d28\n-\tvldr\td25, [sp, #272]\t@ 0x110\n-\tvfma.f64\td21, d24, d27\n-\tvldr\td4, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td30, d31, d29\n-\tvldr\td26, [sp, #240]\t@ 0xf0\n-\tvldr\td23, [sp, #232]\t@ 0xe8\n-\tvldr\td16, [sp, #312]\t@ 0x138\n-\tvfma.f64\td21, d5, d25\n-\tvmul.f64\td20, d26, d20\n-\tvfma.f64\td30, d4, d28\n-\tvfma.f64\td20, d23, d29\n-\tvmul.f64\td18, d18, d16\n-\tldr\tr2, [pc, #496]\t@ (62c <__gridxc_minvec_MOD_minvec+0x62c>)\n-\tvcvta.s32.f64\ts15, d22\n-\tldr\tr3, [pc, #492]\t@ (630 <__gridxc_minvec_MOD_minvec+0x630>)\n+\tvldr\td13, [sp, #288]\t@ 0x120\n+\tvldr\td10, [sp, #216]\t@ 0xd8\n+\tvldr\td8, [sp, #224]\t@ 0xe0\n+\tvldr\td12, [sp, #296]\t@ 0x128\n+\tvmul.f64\td0, d10, d13\n+\tvldr\td9, [sp, #232]\t@ 0xe8\n+\tvldr\td7, [sp, #304]\t@ 0x130\n+\tvmla.f64\td0, d8, d12\n+\tvldr\td6, [sp, #328]\t@ 0x148\n+\tvldr\td4, [sp, #344]\t@ 0x158\n+\tvldr\td3, [sp, #352]\t@ 0x160\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvmla.f64\td0, d9, d7\n+\tvldr\td7, [sp, #336]\t@ 0x150\n+\tvldr\td14, [sp, #312]\t@ 0x138\n+\tvldr\td11, [sp, #320]\t@ 0x140\n+\tvstr\td7, [sp, #8]\n+\tvstr\td6, [sp]\n+\tvstr\td4, [sp, #16]\n+\tvstr\td3, [sp, #24]\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvmov\ts13, r0\n+\tvmul.f64\td0, d10, d14\n+\tvmla.f64\td0, d8, d11\n+\tvstr\td11, [sp, #32]\n+\tvcvt.f64.s32\td15, s13\n+\tvldr\td6, [sp]\n+\tvmla.f64\td0, d9, d6\n+\tvstr\td15, [r6]\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td4, [sp, #16]\n+\tvldr\td5, [sp, #8]\n+\tvmov\ts13, r0\n+\tvldr\td3, [sp, #24]\n+\tvmul.f64\td0, d8, d4\n+\tvcvt.f64.s32\td4, s13\n+\tvmla.f64\td0, d10, d5\n+\tvstr\td4, [r6, #8]\n+\tvmla.f64\td0, d9, d3\n+\tvstr\td4, [sp, #88]\t@ 0x58\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td11, [sp, #240]\t@ 0xf0\n+\tvldr\td9, [sp, #248]\t@ 0xf8\n+\tvmov\ts13, r0\n+\tvldr\td10, [sp, #256]\t@ 0x100\n+\tvmul.f64\td0, d11, d13\n+\tvcvt.f64.s32\td3, s13\n+\tvmla.f64\td0, d9, d12\n+\tvldr\td7, [sp, #64]\t@ 0x40\n+\tvstr\td3, [r6, #16]\n+\tvmla.f64\td0, d10, d7\n+\tvstr\td3, [sp, #80]\t@ 0x50\n+\tvstr\td7, [sp, #72]\t@ 0x48\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td7, [sp, #32]\n+\tvmov\ts16, r0\n+\tvldr\td6, [sp]\n+\tvcvt.f64.s32\td8, s16\n+\tvstr\td14, [sp, #64]\t@ 0x40\n+\tvmul.f64\td0, d9, d7\n+\tvmla.f64\td0, d11, d14\n+\tvstr\td8, [r6, #24]\n+\tvmla.f64\td0, d10, d6\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td4, [sp, #16]\n+\tvldr\td5, [sp, #8]\n+\tvmov\ts28, r0\n+\tvldr\td3, [sp, #24]\n+\tvmul.f64\td0, d9, d4\n+\tvcvt.f64.s32\td14, s28\n+\tvmla.f64\td0, d11, d5\n+\tvstr\td14, [r6, #32]\n+\tvmla.f64\td0, d10, d3\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvmov\ts20, r0\n+\tvcvt.f64.s32\td10, s20\n+\tvstr\td10, [r6, #40]\t@ 0x28\n+\tvldr\td9, [sp, #272]\t@ 0x110\n+\tvldr\td11, [sp, #280]\t@ 0x118\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvmul.f64\td0, d12, d9\n+\tvldr\td12, [sp, #264]\t@ 0x108\n+\tvmla.f64\td0, d13, d12\n+\tvmla.f64\td0, d7, d11\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td6, [sp, #32]\n+\tvldr\td7, [sp, #64]\t@ 0x40\n+\tvmov\ts26, r0\n+\tvmul.f64\td0, d9, d6\n+\tvcvt.f64.s32\td13, s26\n+\tvmla.f64\td0, d12, d7\n+\tvldr\td6, [sp]\n+\tvstr\td13, [r6, #48]\t@ 0x30\n+\tvmla.f64\td0, d11, d6\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td4, [sp, #16]\n+\tvldr\td5, [sp, #8]\n+\tvmov\ts15, r0\n+\tvldr\td3, [sp, #24]\n+\tvmul.f64\td0, d9, d4\n+\tvcvt.f64.s32\td9, s15\n+\tvmla.f64\td0, d12, d5\n+\tvstr\td9, [r6, #56]\t@ 0x38\n+\tvmla.f64\td0, d11, d3\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlround\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvldr\td2, [sp, #104]\t@ 0x68\n+\tvmov\ts12, r0\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvldr\td0, [sp, #136]\t@ 0x88\n+\tvcvt.f64.s32\td6, s12\n+\tvmul.f64\td7, d4, d2\n+\tvldr\td3, [sp, #80]\t@ 0x50\n+\tvmla.f64\td7, d15, d1\n+\tvldr\td11, [sp, #120]\t@ 0x78\n+\tvldr\td12, [sp, #96]\t@ 0x60\n+\tvstr\td6, [r6, #64]\t@ 0x40\n+\tvmul.f64\td5, d4, d11\n+\tldr\tr2, [pc, #304]\t@ (698 <__gridxc_minvec_MOD_minvec+0x698>)\n+\tvmla.f64\td7, d0, d3\n+\tvmla.f64\td5, d15, d12\n+\tldr\tr3, [pc, #300]\t@ (69c <__gridxc_minvec_MOD_minvec+0x69c>)\n \tadd\tr2, pc\n-\tvcvta.s32.f64\ts14, d21\n-\tvcvt.f64.s32\td21, s15\n-\tvcvta.s32.f64\ts15, d30\n-\tvldr\td30, [sp, #248]\t@ 0xf8\n-\tvfma.f64\td20, d30, d28\n-\tvmul.f64\td28, d17, d19\n-\tvmul.f64\td19, d19, d26\n-\tvcvt.f64.s32\td22, s14\n-\tvfma.f64\td19, d27, d23\n-\tvcvt.f64.s32\td29, s15\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td16, d26, d16\n-\tvldr\td26, [sp, #304]\t@ 0x130\n-\tvfma.f64\td28, d31, d27\n-\tvldr\td27, [sp, #48]\t@ 0x30\n-\tvfma.f64\td19, d25, d30\n-\tvstr\td22, [r4]\n-\tvfma.f64\td18, d24, d26\n-\tvfma.f64\td16, d23, d26\n-\tvcvta.s32.f64\ts14, d20\n-\tvmul.f64\td24, d21, d12\n-\tvmul.f64\td23, d21, d11\n-\tvfma.f64\td17, d31, d26\n-\tvmul.f64\td26, d21, d13\n-\tvfma.f64\td24, d22, d14\n-\tvfma.f64\td26, d27, d22\n-\tvfma.f64\td23, d22, d15\n-\tvmul.f64\td22, d29, d12\n-\tvfma.f64\td28, d4, d25\n-\tvcvt.f64.s32\td20, s14\n-\tvstr\td21, [r4, #8]\n-\tvcvta.s32.f64\ts13, d19\n-\tvmul.f64\td21, d29, d11\n-\tvstr\td29, [r4, #32]\n-\tvmul.f64\td29, d29, d13\n-\tvmul.f64\td12, d12, d20\n-\tvmul.f64\td11, d11, d20\n-\tvmul.f64\td13, d13, d20\n-\tvstr\td20, [r4, #56]\t@ 0x38\n-\tvcvt.f64.s32\td19, s13\n-\tvmov.f64\td20, d22\n-\tvcvta.s32.f64\ts15, d28\n-\tvmov.f64\td22, d12\n-\tvfma.f64\td13, d27, d19\n-\tvfma.f64\td22, d14, d19\n-\tvfma.f64\td11, d15, d19\n-\tvstr\td19, [r4, #48]\t@ 0x30\n-\tvldr\td19, [sp, #320]\t@ 0x140\n-\tvcvt.f64.s32\td25, s15\n-\tvfma.f64\td18, d5, d19\n-\tvfma.f64\td17, d4, d19\n-\tvfma.f64\td16, d30, d19\n-\tvfma.f64\td29, d27, d25\n-\tvfma.f64\td20, d25, d14\n-\tvfma.f64\td21, d25, d15\n-\tvldr\td19, [sp, #56]\t@ 0x38\n-\tvldr\td27, [sp, #72]\t@ 0x48\n-\tvstr\td25, [r4, #24]\n-\tvldr\td25, [sp, #64]\t@ 0x40\n-\tvcvta.s32.f64\ts13, d18\n-\tvcvta.s32.f64\ts14, d17\n-\tvcvta.s32.f64\ts15, d16\n-\tvcvt.f64.s32\td18, s13\n-\tvcvt.f64.s32\td17, s14\n-\tvcvt.f64.s32\td16, s15\n-\tvfma.f64\td24, d19, d18\n-\tvfma.f64\td23, d25, d18\n-\tvfma.f64\td26, d27, d18\n-\tvfma.f64\td20, d19, d17\n-\tvfma.f64\td21, d25, d17\n-\tvfma.f64\td29, d27, d17\n-\tvfma.f64\td22, d19, d16\n-\tvfma.f64\td11, d25, d16\n-\tvfma.f64\td13, d27, d16\n-\tvstr\td18, [r4, #16]\n-\tvstr\td17, [r4, #40]\t@ 0x28\n-\tvstr\td16, [r4, #64]\t@ 0x40\n-\tvstr\td24, [r6]\n-\tvstr\td23, [r6, #8]\n-\tvstr\td26, [r6, #16]\n-\tvstr\td20, [r6, #24]\n-\tvstr\td21, [r6, #32]\n-\tvstr\td29, [r6, #40]\t@ 0x28\n-\tvstr\td22, [r6, #48]\t@ 0x30\n-\tvstr\td11, [r6, #56]\t@ 0x38\n-\tvstr\td13, [r6, #64]\t@ 0x40\n+\tvstr\td7, [fp]\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvmul.f64\td7, d7, d15\n+\tvldr\td15, [sp, #128]\t@ 0x80\n+\tvmla.f64\td7, d4, d15\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvmla.f64\td5, d4, d3\n+\tvldr\td4, [sp, #56]\t@ 0x38\n+\tvmla.f64\td7, d4, d3\n+\tvldr\td4, [sp, #40]\t@ 0x28\n+\tvstr\td5, [fp, #8]\n+\tvmul.f64\td5, d2, d9\n+\tvmla.f64\td5, d1, d13\n+\tvstr\td7, [fp, #16]\n+\tvmul.f64\td7, d8, d1\n+\tvmla.f64\td7, d14, d2\n+\tvmla.f64\td5, d0, d6\n+\tvmla.f64\td7, d0, d10\n+\tvstr\td5, [fp, #48]\t@ 0x30\n+\tvmul.f64\td5, d11, d9\n+\tvmul.f64\td9, d15, d9\n+\tvmla.f64\td5, d12, d13\n+\tvmla.f64\td9, d4, d13\n+\tvstr\td7, [fp, #24]\n+\tvmul.f64\td7, d8, d12\n+\tvmul.f64\td8, d4, d8\n+\tvmla.f64\td7, d14, d11\n+\tvmla.f64\td8, d14, d15\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvldr\td3, [sp, #56]\t@ 0x38\n+\tvmla.f64\td7, d4, d10\n+\tvmla.f64\td5, d4, d6\n+\tvmla.f64\td8, d3, d10\n+\tvmla.f64\td9, d3, d6\n+\tvstr\td7, [fp, #32]\n+\tvstr\td8, [fp, #40]\t@ 0x28\n+\tvstr\td5, [fp, #56]\t@ 0x38\n+\tvstr\td9, [fp, #64]\t@ 0x40\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #332]\t@ 0x14c\n+\tldr\tr3, [sp, #364]\t@ 0x16c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t624 <__gridxc_minvec_MOD_minvec+0x624>\n-\tadd\tsp, #340\t@ 0x154\n+\tbne.n\t690 <__gridxc_minvec_MOD_minvec+0x690>\n+\tadd\tsp, #372\t@ 0x174\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr7, [sp, #96]\t@ 0x60\n-\tmov\tr9, fp\n+\tldr\tr4, [sp, #88]\t@ 0x58\n \tmovs\tr1, #5\n+\tldrd\tr8, sl, [sp, #144]\t@ 0x90\n \tmovs\tr0, #4\n \tmovs\tr3, #3\n \tmovs\tr2, #1\n-\tadd\tr4, sp, #336\t@ 0x150\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, r4, r3, lsl #3\n-\tvstr\td10, [r3, #-152]\t@ 0xffffff68\n-\tadd.w\tr3, r4, r0, lsl #3\n+\tadd\tr5, sp, #368\t@ 0x170\n+\tadd.w\tr3, r5, r3, lsl #3\n \tvstr\td9, [r3, #-152]\t@ 0xffffff68\n-\tadd.w\tr3, r4, r1, lsl #3\n-\tvstr\td8, [r3, #-152]\t@ 0xffffff68\n-\tadd.w\tr3, r4, r2, lsl #3\n-\tvstr\td16, [r3, #-176]\t@ 0xffffff50\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tadd.w\tr3, r5, r0, lsl #3\n+\tvstr\td13, [r3, #-152]\t@ 0xffffff68\n+\tadd.w\tr3, r5, r1, lsl #3\n+\tvstr\td14, [r3, #-152]\t@ 0xffffff68\n+\tadd.w\tr3, r5, r2, lsl #3\n+\tvstr\td10, [r3, #-176]\t@ 0xffffff50\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tsubs\tr3, #1\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tbne.w\t106 <__gridxc_minvec_MOD_minvec+0x106>\n-\tldrd\tr4, fp, [sp, #136]\t@ 0x88\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tbne.w\t11c <__gridxc_minvec_MOD_minvec+0x11c>\n+\tldr\tr2, [pc, #64]\t@ (6a0 <__gridxc_minvec_MOD_minvec+0x6a0>)\n \tmovs\tr1, #42\t@ 0x2a\n-\tldr\tr2, [pc, #60]\t@ (634 <__gridxc_minvec_MOD_minvec+0x634>)\n-\tldr\tr0, [pc, #60]\t@ (638 <__gridxc_minvec_MOD_minvec+0x638>)\n-\tldr\tr5, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #172]\t@ 0xac\n+\tldr\tr0, [pc, #64]\t@ (6a4 <__gridxc_minvec_MOD_minvec+0x6a4>)\n+\tldr\tr5, [sp, #168]\t@ 0xa8\n+\tldr\tr2, [r3, r2]\n \tadd\tr0, pc\n-\tldr.w\tr2, [fp, r2]\n \tldr\tr2, [r2, #0]\n \tblx\tr2\n-\tb.n\t38c <__gridxc_minvec_MOD_minvec+0x38c>\n-\tldr\tr7, [sp, #96]\t@ 0x60\n-\tmov\tr9, fp\n+\tb.n\t34a <__gridxc_minvec_MOD_minvec+0x34a>\n+\tldr\tr4, [sp, #88]\t@ 0x58\n \tmovs\tr1, #8\n+\tldrd\tr8, sl, [sp, #144]\t@ 0x90\n \tmovs\tr0, #7\n \tmovs\tr3, #6\n \tmovs\tr2, #2\n-\tb.n\t5c0 <__gridxc_minvec_MOD_minvec+0x5c0>\n+\tb.n\t630 <__gridxc_minvec_MOD_minvec+0x630>\n \tmovs\tr3, #0\n-\tldr\tr7, [sp, #96]\t@ 0x60\n-\tmov\tr9, fp\n+\tldr\tr4, [sp, #88]\t@ 0x58\n+\tldrd\tr8, sl, [sp, #144]\t@ 0x90\n \tmovs\tr1, #2\n \tmovs\tr0, #1\n \tmov\tr2, r3\n-\tb.n\t5c0 <__gridxc_minvec_MOD_minvec+0x5c0>\n+\tb.n\t630 <__gridxc_minvec_MOD_minvec+0x630>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x0000025e\n+\t.word\t0x0000030c\n R_ARM_REL32\t.rodata\n-\t.word\t0x000001e6\n+\t.word\t0x00000124\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t...\n R_ARM_GOT32\t__stack_chk_guard\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000038\n R_ARM_REL32\t.LC3\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -10,10 +10,10 @@\n 0x00000070 74696e67 5f4d4f44 5f6f7264 6572006d ting_MOD_order.m\n 0x00000080 656d6370 79005f47 4c4f4241 4c5f4f46 emcpy._GLOBAL_OF\n 0x00000090 46534554 5f544142 4c455f00 5f5f7374 FSET_TABLE_.__st\n 0x000000a0 61636b5f 63686b5f 67756172 64005f5f ack_chk_guard.__\n 0x000000b0 67726964 78635f73 79735f4d 4f445f64 gridxc_sys_MOD_d\n 0x000000c0 6965005f 5f677269 6478635f 63656c6c ie.__gridxc_cell\n 0x000000d0 73756273 5f4d4f44 5f726563 6c617400 subs_MOD_reclat.\n- 0x000000e0 5f5f7374 61636b5f 63686b5f 6661696c __stack_chk_fail\n- 0x000000f0 00 .\n+ 0x000000e0 6c726f75 6e64005f 5f737461 636b5f63 lround.__stack_c\n+ 0x000000f0 686b5f66 61696c00 hk_fail.\n \n"}]}, {"source1": "moreParallelSubs.F90.o", "source2": "moreParallelSubs.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 7544 (bytes into file)\n+ Start of section headers: 7540 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x1d78:\n+There are 12 section headers, starting at offset 0x1d74:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 000ecc 00 AX 0 0 4\n- [ 2] .rel.text REL 00000000 001858 0004b8 08 I 9 1 4\n+ [ 2] .rel.text REL 00000000 001854 0004b8 08 I 9 1 4\n [ 3] .data PROGBITS 00000000 000f00 000000 00 WA 0 0 1\n [ 4] .bss NOBITS 00000000 000f00 00006c 00 WA 0 0 4\n [ 5] .rodata.str1.4 PROGBITS 00000000 000f00 0001d3 01 AMS 0 0 4\n [ 6] .rodata PROGBITS 00000000 0010d4 00000c 00 A 0 0 4\n [ 7] .note.GNU-stack PROGBITS 00000000 0010e0 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0010e0 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 001114 0003e0 10 10 32 4\n- [10] .strtab STRTAB 00000000 0014f4 000361 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 001d10 000067 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0010e0 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 001110 0003e0 10 10 32 4\n+ [10] .strtab STRTAB 00000000 0014f0 000361 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 001d0c 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Relocation section '.rel.text' at offset 0x1858 contains 151 entries:\n+Relocation section '.rel.text' at offset 0x1854 contains 151 entries:\n Offset Info Type Sym. Value Symbol's Name\n 000000b8 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 000000d4 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 000000ec 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 0000015c 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_s1\n 00000186 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n 000001a4 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n@@ -21,56 +21,56 @@\n 00000504 0000270a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_assign\n 0000051c 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 00000534 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n 0000059a 0000280a R_ARM_THM_CALL 00000000 _gfortran_st_open\n 000005f6 00002f0a R_ARM_THM_CALL 00000000 _gfortran_st_write\n 00000600 0000300a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n 00000606 0000310a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000690 00002b0a R_ARM_THM_CALL 00000000 memmove\n-000006aa 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000006b8 0000320a R_ARM_THM_CALL 00000000 malloc\n-000006d0 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000006d6 0000320a R_ARM_THM_CALL 00000000 malloc\n-000006f4 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000006fa 0000340a R_ARM_THM_CALL 00000000 free\n-0000070e 0000350a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000728 0000320a R_ARM_THM_CALL 00000000 malloc\n-00000742 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000754 0000340a R_ARM_THM_CALL 00000000 free\n-0000076e 0000340a R_ARM_THM_CALL 00000000 free\n-0000077c 0000360a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_close\n-0000079c 0000370a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_s1\n-000007b0 0000380a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_i1\n-000007c4 0000380a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_i1\n-000007d8 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000007f8 0000290a R_ARM_THM_CALL 00000000 memcpy\n-00000842 00002a0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-000008f0 00002b0a R_ARM_THM_CALL 00000000 memmove\n-00000902 0000390a R_ARM_THM_CALL 00000000 memset\n-0000094c 00002c0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-00000958 00002d0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character\n-0000095e 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-00000972 0000360a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_close\n-0000099c 00002b0a R_ARM_THM_CALL 00000000 memmove\n-000009ae 0000390a R_ARM_THM_CALL 00000000 memset\n-000009d8 0000290a R_ARM_THM_CALL 00000000 memcpy\n-000009e8 0000290a R_ARM_THM_CALL 00000000 memcpy\n-00000a04 0000390a R_ARM_THM_CALL 00000000 memset\n-00000a5c 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n-00000a78 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n-00000ad6 00002b0a R_ARM_THM_CALL 00000000 memmove\n-00000b44 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_s1\n-00000b82 0000290a R_ARM_THM_CALL 00000000 memcpy\n-00000b9e 0000390a R_ARM_THM_CALL 00000000 memset\n-00000bae 0000290a R_ARM_THM_CALL 00000000 memcpy\n-00000bca 0000390a R_ARM_THM_CALL 00000000 memset\n-00000be0 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000bf6 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000c4a 0000280a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00000c64 0000340a R_ARM_THM_CALL 00000000 free\n+00000692 00002b0a R_ARM_THM_CALL 00000000 memmove\n+000006ac 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000006ba 0000320a R_ARM_THM_CALL 00000000 malloc\n+000006d2 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000006d8 0000320a R_ARM_THM_CALL 00000000 malloc\n+000006f6 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000006fc 0000340a R_ARM_THM_CALL 00000000 free\n+00000710 0000350a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+0000072a 0000320a R_ARM_THM_CALL 00000000 malloc\n+00000744 0000330a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000756 0000340a R_ARM_THM_CALL 00000000 free\n+00000770 0000340a R_ARM_THM_CALL 00000000 free\n+0000077e 0000360a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_close\n+0000079e 0000370a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_s1\n+000007b2 0000380a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_i1\n+000007c6 0000380a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_i1\n+000007da 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000007fa 0000290a R_ARM_THM_CALL 00000000 memcpy\n+00000844 00002a0a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+000008f2 00002b0a R_ARM_THM_CALL 00000000 memmove\n+00000904 0000390a R_ARM_THM_CALL 00000000 memset\n+0000094e 00002c0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+0000095a 00002d0a R_ARM_THM_CALL 00000000 _gfortran_transfer_character\n+00000960 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+00000974 0000360a R_ARM_THM_CALL 00000000 __gridxc_io_MOD_io_close\n+0000099e 00002b0a R_ARM_THM_CALL 00000000 memmove\n+000009b0 0000390a R_ARM_THM_CALL 00000000 memset\n+000009da 0000290a R_ARM_THM_CALL 00000000 memcpy\n+000009ea 0000290a R_ARM_THM_CALL 00000000 memcpy\n+00000a06 0000390a R_ARM_THM_CALL 00000000 memset\n+00000a5e 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n+00000a7a 0000260a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_i1\n+00000ad8 00002b0a R_ARM_THM_CALL 00000000 memmove\n+00000b46 0000250a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_s1\n+00000b84 0000290a R_ARM_THM_CALL 00000000 memcpy\n+00000ba0 0000390a R_ARM_THM_CALL 00000000 memset\n+00000bb0 0000290a R_ARM_THM_CALL 00000000 memcpy\n+00000bcc 0000390a R_ARM_THM_CALL 00000000 memset\n+00000be2 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000bf8 0000240a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000c4c 0000280a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+00000c66 0000340a R_ARM_THM_CALL 00000000 free\n 00000c70 00003a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000c74 00003b1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000c78 00003a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000c7c 00003a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000c80 00000403 R_ARM_REL32 00000000 .LC0\n 00000c84 00000503 R_ARM_REL32 00000008 .LC1\n 00000c88 00003c1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -223,17 +223,17 @@\n \tstr\tr5, [r1, r2]\n \tadd.w\tr2, sp, #10688\t@ 0x29c0\n \tldr\tr2, [r2, #0]\n \tcmp\tr2, r3\n \tadd.w\tr2, sp, #10624\t@ 0x2980\n \tadd.w\tr2, r2, #60\t@ 0x3c\n \tldr\tr2, [r2, #0]\n-\tble.w\t7e6 <__gridxc_moreparallelsubs_MOD_copyfile+0x7d2>\n+\tble.w\t7e8 <__gridxc_moreparallelsubs_MOD_copyfile+0x7d4>\n \tcmp\tr2, r3\n-\tble.w\tb72 <__gridxc_moreparallelsubs_MOD_copyfile+0xb5e>\n+\tble.w\tb74 <__gridxc_moreparallelsubs_MOD_copyfile+0xb60>\n \tadd.w\tfp, sp, #636\t@ 0x27c\n \tldr\tr1, [sp, #28]\n \tmov\tr2, r7\n \tsubw\tr0, r6, #1812\t@ 0x714\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr.w\tr3, [pc, #2648]\t@ cb0 <__gridxc_moreparallelsubs_MOD_copyfile+0xc9c>\n@@ -289,15 +289,15 @@\n \tldr\tr7, [r3, #96]\t@ 0x60\n \tldr\tr2, [r3, #76]\t@ 0x4c\n \tmla\tr2, r7, r4, r2\n \tldr\tr7, [r3, #92]\t@ 0x5c\n \tmul.w\tr7, r2, r7\n \tldr.w\tr2, [ip, r7]\n \tcmp\tr2, r8\n-\tble.w\t980 <__gridxc_moreparallelsubs_MOD_copyfile+0x96c>\n+\tble.w\t982 <__gridxc_moreparallelsubs_MOD_copyfile+0x96e>\n \tstr.w\tlr, [ip, r7]\n \tsubw\tr7, r6, #2356\t@ 0x934\n \tldr\tr1, [r3, #60]\t@ 0x3c\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tmla\tr5, r5, r1, r2\n \tmla\tr2, r1, r4, r2\n \tldr\tr1, [r3, #56]\t@ 0x38\n@@ -310,54 +310,53 @@\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tmla\tr2, r1, r4, r2\n \tldr\tr1, [r3, #56]\t@ 0x38\n \tmul.w\tr2, r1, r2\n \tldr\tr0, [r0, r2]\n \tldr\tr2, [r7, #0]\n \tcmp\tr2, r0\n-\tbge.w\t9b4 <__gridxc_moreparallelsubs_MOD_copyfile+0x9a0>\n+\tbge.w\t9b6 <__gridxc_moreparallelsubs_MOD_copyfile+0x9a2>\n \tcmp.w\tr2, #1000\t@ 0x3e8\n \tblt.n\t362 <__gridxc_moreparallelsubs_MOD_copyfile+0x34e>\n \tldr.w\tr3, [pc, #2360]\t@ c88 <__gridxc_moreparallelsubs_MOD_copyfile+0xc74>\n \tmovs\tr1, #46\t@ 0x2e\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr.w\tr0, [pc, #2408]\t@ cc0 <__gridxc_moreparallelsubs_MOD_copyfile+0xcac>\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr2, [r7, #0]\n \tvmov\ts15, r2\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td6, #120\t@ 0x3fc00000 1.5\n \tsubw\tr2, r6, #2356\t@ 0x934\n \tldr.w\tr1, [pc, #2388]\t@ cc4 <__gridxc_moreparallelsubs_MOD_copyfile+0xcb0>\n-\tvcvt.f64.s32\td16, s15\n-\tmov.w\tr0, #1000\t@ 0x3e8\n-\tldr.w\tr5, [pc, #2380]\t@ cc8 <__gridxc_moreparallelsubs_MOD_copyfile+0xcb4>\n+\tvcvt.f64.s32\td7, s15\n+\tldr.w\tr5, [pc, #2384]\t@ cc8 <__gridxc_moreparallelsubs_MOD_copyfile+0xcb4>\n \tadd\tr1, pc\n \tmovs\tr7, #0\n-\tstr\tr7, [sp, #20]\n \tadd\tr5, pc\n+\tstr\tr7, [sp, #20]\n \tstr\tr7, [sp, #8]\n-\tvmul.f64\td16, d16, d17\n+\tmov\tr0, r5\n+\tvmul.f64\td7, d7, d6\n \tstr\tr7, [sp, #0]\n-\tvcvt.s32.f64\ts15, d16\n+\tvcvt.s32.f64\ts15, d7\n \tvmov\tr3, s15\n-\tcmp\tr3, r0\n+\tcmp.w\tr3, #1000\t@ 0x3e8\n \tit\tge\n-\tmovge\tr3, r0\n+\tmovge.w\tr3, #1000\t@ 0x3e8\n \tstr\tr3, [r2, #0]\n \tmovs\tr3, #15\n \tstr\tr3, [sp, #16]\n \tadd.w\tr3, r1, #8\n \tstr\tr3, [sp, #4]\n \tmovw\tr3, #10000\t@ 0x2710\n \tstr\tr3, [sp, #12]\n-\tldr.w\tr3, [pc, #2332]\t@ ccc <__gridxc_moreparallelsubs_MOD_copyfile+0xcb8>\n-\tmov\tr0, r5\n+\tldr.w\tr3, [pc, #2328]\t@ ccc <__gridxc_moreparallelsubs_MOD_copyfile+0xcb8>\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tadd\tr3, pc\n \tbl\t0 <__gridxc_alloc_MOD_realloc_s1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_s1\n \tldr\tr3, [r5, #96]\t@ 0x60\n \tldr\tr0, [r5, #76]\t@ 0x4c\n \tmov\tr1, r7\n@@ -383,27 +382,27 @@\n \tldr\tr2, [r7, #24]\n \tldr\tr3, [r7, #4]\n \tmla\tr3, r2, r0, r3\n \tldr\tr2, [r7, #20]\n \tmla\tr1, r2, r3, r1\n \tldr\tr3, [r7, #0]\n \tadd\tr3, r1\n-\tbgt.w\t994 <__gridxc_moreparallelsubs_MOD_copyfile+0x980>\n+\tbgt.w\t996 <__gridxc_moreparallelsubs_MOD_copyfile+0x982>\n \tadds\tr2, r5, #1\n \tmov\tr0, r3\n \tmov\tr1, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tadds\tr7, r4, #1\n \tmovw\tr3, #34465\t@ 0x86a1\n \tmovt\tr3, #1\n \tcmp\tr7, r3\n \tbeq.w\te30 <__gridxc_moreparallelsubs_MOD_copyfile+0xe1c>\n \tcmp\tr7, #2\n-\tbeq.w\t9cc <__gridxc_moreparallelsubs_MOD_copyfile+0x9b8>\n+\tbeq.w\t9ce <__gridxc_moreparallelsubs_MOD_copyfile+0x9ba>\n \tsubw\tr3, r6, #2360\t@ 0x938\n \tsub.w\tr5, r6, #2160\t@ 0x870\n \tadd.w\tr8, sp, #288\t@ 0x120\n \tmov\tr0, r8\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r5, #4]\n \tldr.w\tr3, [pc, #2196]\t@ cd4 <__gridxc_moreparallelsubs_MOD_copyfile+0xcc0>\n@@ -427,39 +426,39 @@\n R_ARM_THM_CALL\t_gfortran_transfer_character\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n \tldr\tr3, [r5, #0]\n \tand.w\tr3, r3, #3\n \tcmp\tr3, #2\n-\tbeq.w\t96c <__gridxc_moreparallelsubs_MOD_copyfile+0x958>\n+\tbeq.w\t96e <__gridxc_moreparallelsubs_MOD_copyfile+0x95a>\n \tmov\tr4, r7\n \tsub.w\tr3, r6, #2352\t@ 0x930\n \tldr\tr2, [r3, #0]\n \tcmp\tr4, r2\n \tble.w\t296 <__gridxc_moreparallelsubs_MOD_copyfile+0x282>\n \tvmov\ts15, r2\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td6, #120\t@ 0x3fc00000 1.5\n \tmovs\tr2, #17\n \tstr\tr2, [sp, #12]\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s15\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tldr\tr1, [sp, #56]\t@ 0x38\n \tmovs\tr5, #0\n \tadd.w\tr7, r2, #8\n \tldr.w\tr9, [sp, #60]\t@ 0x3c\n \tldr.w\tr8, [sp, #44]\t@ 0x2c\n-\tvmul.f64\td16, d16, d17\n+\tvmul.f64\td7, d7, d6\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tstr\tr5, [sp, #16]\n \tstr\tr5, [sp, #8]\n \tstr\tr5, [sp, #0]\n-\tvcvt.s32.f64\ts15, d16\n+\tvcvt.s32.f64\ts14, d7\n \tstr\tr7, [sp, #4]\n-\tvmov\tr2, s15\n+\tvmov\tr2, s14\n \tcmp\tr2, r1\n \tit\tge\n \tmovge\tr2, r1\n \tmov\tr1, r8\n \tstr\tr2, [r3, #0]\n \tmov\tr2, r9\n \tldr\tr3, [sp, #36]\t@ 0x24\n@@ -505,15 +504,15 @@\n \tmovs\tr2, #6\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tldr\tr0, [r0, #0]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbne.w\tbd0 <__gridxc_moreparallelsubs_MOD_copyfile+0xbbc>\n+\tbne.w\tbd2 <__gridxc_moreparallelsubs_MOD_copyfile+0xbbe>\n \tadd\tr3, sp, #104\t@ 0x68\n \tadd\tr1, sp, #88\t@ 0x58\n \tldr.w\tr2, [pc, #1956]\t@ ce8 <__gridxc_moreparallelsubs_MOD_copyfile+0xcd4>\n \tmovs\tr5, #0\n \tadd\tr2, pc\n \tstr\tr2, [r3, #8]\n \tldr\tr2, [r1, #0]\n@@ -593,15 +592,15 @@\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadds\tr4, #1\n \tcmp\tr4, r3\n-\tbeq.w\t77a <__gridxc_moreparallelsubs_MOD_copyfile+0x766>\n+\tbeq.w\t77c <__gridxc_moreparallelsubs_MOD_copyfile+0x768>\n \tldr.w\tr3, [pc, #1780]\t@ d0c <__gridxc_moreparallelsubs_MOD_copyfile+0xcf8>\n \tadd\tr3, pc\n \tldr.w\tlr, [r3, #36]\t@ 0x24\n \tldr\tr3, [r5, #40]\t@ 0x28\n \tsubs\tr0, r4, #1\n \tldr.w\tip, [r5, #60]\t@ 0x3c\n \tldr\tr6, [r5, #56]\t@ 0x38\n@@ -610,44 +609,45 @@\n \tmla\tr3, r0, ip, r3\n \tldrd\tr9, sl, [r5, #92]\t@ 0x5c\n \tmul.w\tr1, r6, r1\n \tmul.w\tr3, r6, r3\n \tldr.w\tr1, [lr, r1]\n \tldr.w\tr3, [lr, r3]\n \tcmp\tr1, r3\n-\tit\tne\n-\tmovne\tr3, #0\n-\tit\tne\n+\titte\tne\n \tmovne\tr0, #1\n-\tbne.n\t662 <__gridxc_moreparallelsubs_MOD_copyfile+0x64e>\n-\tmla\tr0, sl, r0, r2\n-\tmul.w\tr0, r9, r0\n-\tldr.w\tr3, [r8, r0]\n-\tadds\tr0, r3, #1\n+\tmovne\tr3, #0\n+\tmlaeq\tr0, sl, r0, r2\n \tmla\tr2, sl, r4, r2\n+\tit\teq\n+\tmuleq.w\tr0, r9, r0\n \tmul.w\tr2, r9, r2\n+\tit\teq\n+\tldreq.w\tr3, [r8, r0]\n \tldr.w\tr2, [r8, r2]\n+\tit\teq\n+\taddeq\tr0, r3, #1\n \tsubs\tr2, r2, r0\n \tadds\tr2, #1\n \tcmp\tr2, #0\n \tbic.w\tr6, r2, r2, asr #31\n-\tble.n\t694 <__gridxc_moreparallelsubs_MOD_copyfile+0x680>\n+\tble.n\t696 <__gridxc_moreparallelsubs_MOD_copyfile+0x682>\n \tldr\tr0, [r7, #24]\n \tldr\tr2, [r7, #4]\n \tmla\tr2, r0, r1, r2\n \tldr\tr1, [r7, #20]\n \tmov\tr0, fp\n \tmla\tr3, r1, r2, r3\n \tldr\tr1, [r7, #0]\n \tmov\tr2, r6\n \tadd\tr1, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tcmp\tr4, #1\n-\tbeq.w\t7ca <__gridxc_moreparallelsubs_MOD_copyfile+0x7b6>\n+\tbeq.w\t7cc <__gridxc_moreparallelsubs_MOD_copyfile+0x7b8>\n \tcmp\tr4, #2\n \tbne.n\t5ce <__gridxc_moreparallelsubs_MOD_copyfile+0x5ba>\n \tadd.w\tr2, sp, #10688\t@ 0x29c0\n \tldr\tr3, [sp, #32]\n \tmov\tr1, fp\n \tmov\tr0, r6\n \tldr\tr2, [r2, #0]\n@@ -668,15 +668,15 @@\n \tstrd\tr6, fp, [sp]\n \tadds\tr6, #35\t@ 0x23\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr.w\tr3, [pc, #1592]\t@ d14 <__gridxc_moreparallelsubs_MOD_copyfile+0xd00>\n+\tldr.w\tr3, [pc, #1588]\t@ d14 <__gridxc_moreparallelsubs_MOD_copyfile+0xd00>\n \tmov\tr2, sl\n \tmov\tr1, r0\n \tmov\tr9, r0\n \tadd\tr3, pc\n \tmov\tr0, r6\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #1\n@@ -717,15 +717,15 @@\n \tmov\tr3, r9\n \tmov\tr1, r8\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr1, [r3, #0]\n \tcmp\tr1, #0\n-\tbgt.w\tc60 <__gridxc_moreparallelsubs_MOD_copyfile+0xc4c>\n+\tbgt.w\tc62 <__gridxc_moreparallelsubs_MOD_copyfile+0xc4e>\n \tmov\tr0, r9\n \tstr\tr1, [sp, #44]\t@ 0x2c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr3, [pc, #1324]\t@ c88 <__gridxc_moreparallelsubs_MOD_copyfile+0xc74>\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tmov\tr0, r8\n@@ -742,15 +742,15 @@\n \tcmp\tr4, r3\n \tbne.w\t614 <__gridxc_moreparallelsubs_MOD_copyfile+0x600>\n \tldr\tr0, [sp, #84]\t@ 0x54\n \tbl\t0 <__gridxc_io_MOD_io_close>\n R_ARM_THM_CALL\t__gridxc_io_MOD_io_close\n \tldr.w\tr5, [pc, #1428]\t@ d18 <__gridxc_moreparallelsubs_MOD_copyfile+0xd04>\n \tmovs\tr4, #0\n-\tldr.w\tr1, [pc, #1428]\t@ d1c <__gridxc_moreparallelsubs_MOD_copyfile+0xd08>\n+\tldr.w\tr1, [pc, #1424]\t@ d1c <__gridxc_moreparallelsubs_MOD_copyfile+0xd08>\n \tmov\tr2, r4\n \tadd\tr5, pc\n \tmovs\tr3, #15\n \tmov\tr0, r5\n \tstrd\tr3, r4, [sp]\n \tadd\tr1, pc\n \tmovw\tr3, #10000\t@ 0x2710\n@@ -782,48 +782,48 @@\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n \tbne.w\td70 <__gridxc_moreparallelsubs_MOD_copyfile+0xd5c>\n \tmovs\tr4, #2\n \tb.n\t614 <__gridxc_moreparallelsubs_MOD_copyfile+0x600>\n \tcmp\tr2, r3\n-\tble.w\tba6 <__gridxc_moreparallelsubs_MOD_copyfile+0xb92>\n+\tble.w\tba8 <__gridxc_moreparallelsubs_MOD_copyfile+0xb94>\n \tadd.w\tfp, sp, #636\t@ 0x27c\n \tldr\tr1, [sp, #28]\n \tmov\tr2, r7\n \tsubw\tr0, r6, #1812\t@ 0x714\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tldr.w\tr3, [pc, #1320]\t@ d28 <__gridxc_moreparallelsubs_MOD_copyfile+0xd14>\n \tmovs\tr4, #1\n-\tldr.w\tr2, [pc, #1320]\t@ d2c <__gridxc_moreparallelsubs_MOD_copyfile+0xd18>\n+\tldr.w\tr2, [pc, #1316]\t@ d2c <__gridxc_moreparallelsubs_MOD_copyfile+0xd18>\n \tmovw\tsl, #34464\t@ 0x86a0\n \tmovt\tsl, #1\n \tadd\tr3, pc\n \tadd\tr2, pc\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tadds\tr3, #4\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tadd.w\tr3, r2, #36\t@ 0x24\n \tstr\tr3, [sp, #52]\t@ 0x34\n \tsub.w\tr3, r6, #2352\t@ 0x930\n-\tldr.w\tr1, [pc, #1292]\t@ d30 <__gridxc_moreparallelsubs_MOD_copyfile+0xd1c>\n+\tldr.w\tr1, [pc, #1288]\t@ d30 <__gridxc_moreparallelsubs_MOD_copyfile+0xd1c>\n \tstr\tr2, [sp, #48]\t@ 0x30\n \tadd\tr1, pc\n \tstr.w\tr9, [sp, #80]\t@ 0x50\n \tldr\tr2, [r3, #0]\n \tstr\tr1, [sp, #36]\t@ 0x24\n \tcmp\tr2, r4\n \tstr.w\tsl, [sp, #56]\t@ 0x38\n-\tblt.w\ta16 <__gridxc_moreparallelsubs_MOD_copyfile+0xa02>\n+\tblt.w\ta18 <__gridxc_moreparallelsubs_MOD_copyfile+0xa04>\n \tmov\tr1, fp\n \tmovw\tr0, #10000\t@ 0x2710\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n-\tldr.w\tr3, [pc, #1260]\t@ d34 <__gridxc_moreparallelsubs_MOD_copyfile+0xd20>\n+\tldr.w\tr3, [pc, #1256]\t@ d34 <__gridxc_moreparallelsubs_MOD_copyfile+0xd20>\n \tsubs\tr5, r4, #1\n \tbic.w\tlr, r0, r0, asr #31\n \tadd\tr3, pc\n \tmovw\tr8, #10000\t@ 0x2710\n \tldrd\tr7, r9, [r3, #92]\t@ 0x5c\n \tldr\tr2, [r3, #76]\t@ 0x4c\n \tldr.w\tip, [r3, #72]\t@ 0x48\n@@ -846,36 +846,36 @@\n \tldr\tr7, [r3, #96]\t@ 0x60\n \tldr\tr1, [r3, #76]\t@ 0x4c\n \tmla\tr1, r7, r4, r1\n \tldr\tr7, [r3, #92]\t@ 0x5c\n \tmul.w\tr1, r7, r1\n \tldr.w\tr7, [ip, r1]\n \tcmp\tr7, r8\n-\tbgt.w\ta7e <__gridxc_moreparallelsubs_MOD_copyfile+0xa6a>\n+\tbgt.w\ta80 <__gridxc_moreparallelsubs_MOD_copyfile+0xa6c>\n \tldr\tr5, [r3, #60]\t@ 0x3c\n \tldr\tr1, [r3, #40]\t@ 0x28\n \tldr\tr3, [r3, #56]\t@ 0x38\n \tmla\tr1, r5, r4, r1\n \tadds\tr5, r2, #1\n \tmul.w\tr1, r3, r1\n \tldr\tr0, [r0, r1]\n \tsubs\tr5, r7, r5\n-\tbmi.n\t906 <__gridxc_moreparallelsubs_MOD_copyfile+0x8f2>\n-\tldr.w\tr7, [pc, #1136]\t@ d38 <__gridxc_moreparallelsubs_MOD_copyfile+0xd24>\n+\tbmi.n\t908 <__gridxc_moreparallelsubs_MOD_copyfile+0x8f4>\n+\tldr.w\tr7, [pc, #1132]\t@ d38 <__gridxc_moreparallelsubs_MOD_copyfile+0xd24>\n \tmovw\tip, #9999\t@ 0x270f\n \tcmp\tr5, ip\n \tadd\tr7, pc\n \tldr\tr1, [r7, #24]\n \tldr\tr3, [r7, #4]\n \tmla\tr3, r1, r0, r3\n \tldr\tr1, [r7, #20]\n \tmla\tr2, r1, r3, r2\n \tldr\tr3, [r7, #0]\n \tadd\tr3, r2\n-\tble.w\tad0 <__gridxc_moreparallelsubs_MOD_copyfile+0xabc>\n+\tble.w\tad2 <__gridxc_moreparallelsubs_MOD_copyfile+0xabe>\n \tmov\tr1, fp\n \tmovw\tr2, #10000\t@ 0x2710\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tsub.w\tr2, r5, #9984\t@ 0x2700\n \tadd.w\tr0, r0, #9984\t@ 0x2700\n@@ -886,15 +886,15 @@\n R_ARM_THM_CALL\tmemset\n \tadds\tr7, r4, #1\n \tmovw\tr3, #34465\t@ 0x86a1\n \tmovt\tr3, #1\n \tcmp\tr7, r3\n \tbeq.w\te30 <__gridxc_moreparallelsubs_MOD_copyfile+0xe1c>\n \tcmp\tr7, #2\n-\tbeq.n\t9de <__gridxc_moreparallelsubs_MOD_copyfile+0x9ca>\n+\tbeq.n\t9e0 <__gridxc_moreparallelsubs_MOD_copyfile+0x9cc>\n \tsubw\tr3, r6, #2360\t@ 0x938\n \tsub.w\tr5, r6, #2160\t@ 0x870\n \tadd.w\tr8, sp, #288\t@ 0x120\n \tmov\tr0, r8\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r5, #4]\n \tldr.w\tr3, [pc, #1036]\t@ d3c <__gridxc_moreparallelsubs_MOD_copyfile+0xd28>\n@@ -918,21 +918,21 @@\n R_ARM_THM_CALL\t_gfortran_transfer_character\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n \tldr\tr3, [r5, #0]\n \tand.w\tr3, r3, #3\n \tcmp\tr3, #2\n-\tbne.n\ta08 <__gridxc_moreparallelsubs_MOD_copyfile+0x9f4>\n+\tbne.n\ta0a <__gridxc_moreparallelsubs_MOD_copyfile+0x9f6>\n \tldr.w\tr9, [sp, #80]\t@ 0x50\n \tldr\tr0, [sp, #84]\t@ 0x54\n \tbl\t0 <__gridxc_io_MOD_io_close>\n R_ARM_THM_CALL\t__gridxc_io_MOD_io_close\n \tcmp.w\tr9, #0\n-\tbne.w\t780 <__gridxc_moreparallelsubs_MOD_copyfile+0x76c>\n+\tbne.w\t782 <__gridxc_moreparallelsubs_MOD_copyfile+0x76e>\n \tb.n\t502 <__gridxc_moreparallelsubs_MOD_copyfile+0x4ee>\n \tldr\tr7, [r3, #60]\t@ 0x3c\n \tldr\tr5, [r3, #40]\t@ 0x28\n \tldr\tr3, [r3, #56]\t@ 0x38\n \tmla\tr5, r7, r4, r5\n \tmul.w\tr5, r3, r5\n \tldr\tr0, [r0, r5]\n@@ -983,58 +983,58 @@\n \tadd.w\tr0, fp, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tsub.w\tr3, r6, #2352\t@ 0x930\n \tmov\tr4, r7\n \tldr\tr2, [r3, #0]\n \tcmp\tr2, r4\n-\tbge.w\t83c <__gridxc_moreparallelsubs_MOD_copyfile+0x828>\n+\tbge.w\t83e <__gridxc_moreparallelsubs_MOD_copyfile+0x82a>\n \tvmov\ts15, r2\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td6, #120\t@ 0x3fc00000 1.5\n \tmovs\tr2, #17\n \tstr\tr2, [sp, #12]\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s15\n \tldr\tr2, [sp, #40]\t@ 0x28\n \tldr\tr1, [sp, #56]\t@ 0x38\n \tmovs\tr5, #0\n \tadd.w\tr7, r2, #8\n \tldr.w\tr9, [sp, #60]\t@ 0x3c\n \tldr.w\tr8, [sp, #44]\t@ 0x2c\n-\tvmul.f64\td16, d16, d17\n+\tvmul.f64\td7, d7, d6\n \tldr\tr0, [sp, #52]\t@ 0x34\n \tstr\tr5, [sp, #16]\n \tstr\tr5, [sp, #8]\n \tstr\tr5, [sp, #0]\n-\tvcvt.s32.f64\ts15, d16\n+\tvcvt.s32.f64\ts14, d7\n \tstr\tr7, [sp, #4]\n-\tvmov\tr2, s15\n+\tvmov\tr2, s14\n \tcmp\tr2, r1\n \tit\tge\n \tmovge\tr2, r1\n \tmov\tr1, r8\n \tstr\tr2, [r3, #0]\n \tmov\tr2, r9\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tbl\t0 <__gridxc_alloc_MOD_realloc_i1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_i1\n \tldr\tr0, [sp, #48]\t@ 0x30\n \tmovs\tr3, #16\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [pc, #732]\t@ (d44 <__gridxc_moreparallelsubs_MOD_copyfile+0xd30>)\n+\tldr\tr3, [pc, #728]\t@ (d44 <__gridxc_moreparallelsubs_MOD_copyfile+0xd30>)\n \tmov\tr2, r9\n \tmov\tr1, r8\n \tadds\tr0, #72\t@ 0x48\n \tadd\tr3, pc\n \tstr\tr7, [sp, #4]\n \tstr\tr5, [sp, #16]\n \tstr\tr5, [sp, #8]\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_i1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_i1\n-\tb.n\t83c <__gridxc_moreparallelsubs_MOD_copyfile+0x828>\n+\tb.n\t83e <__gridxc_moreparallelsubs_MOD_copyfile+0x82a>\n \tstr.w\tlr, [ip, r1]\n \tsubw\tr7, r6, #2356\t@ 0x934\n \tldr\tr1, [r3, #60]\t@ 0x3c\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tmla\tr5, r1, r5, r2\n \tmla\tr2, r4, r1, r2\n \tldr\tr1, [r3, #56]\t@ 0x38\n@@ -1047,69 +1047,68 @@\n \tldr\tr2, [r3, #40]\t@ 0x28\n \tmla\tr2, r1, r4, r2\n \tldr\tr1, [r3, #56]\t@ 0x38\n \tmul.w\tr2, r1, r2\n \tldr\tr0, [r0, r2]\n \tldr\tr2, [r7, #0]\n \tcmp\tr0, r2\n-\tbgt.n\tadc <__gridxc_moreparallelsubs_MOD_copyfile+0xac8>\n+\tbgt.n\tade <__gridxc_moreparallelsubs_MOD_copyfile+0xaca>\n \tldr\tr1, [r3, #96]\t@ 0x60\n \tmovs\tr5, #1\n \tldr\tr2, [r3, #76]\t@ 0x4c\n \tldr\tr3, [r3, #92]\t@ 0x5c\n \tmla\tr2, r1, r4, r2\n \tmul.w\tr2, r3, r2\n \tldr.w\tr7, [ip, r2]\n \tmovs\tr2, #0\n-\tb.n\t8c2 <__gridxc_moreparallelsubs_MOD_copyfile+0x8ae>\n+\tb.n\t8c4 <__gridxc_moreparallelsubs_MOD_copyfile+0x8b0>\n \tadds\tr2, r5, #1\n \tmov\tr0, r3\n \tmov\tr1, fp\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n-\tb.n\t906 <__gridxc_moreparallelsubs_MOD_copyfile+0x8f2>\n+\tb.n\t908 <__gridxc_moreparallelsubs_MOD_copyfile+0x8f4>\n \tcmp.w\tr2, #1000\t@ 0x3e8\n-\tblt.n\taf4 <__gridxc_moreparallelsubs_MOD_copyfile+0xae0>\n-\tldr\tr3, [pc, #420]\t@ (c88 <__gridxc_moreparallelsubs_MOD_copyfile+0xc74>)\n+\tblt.n\taf6 <__gridxc_moreparallelsubs_MOD_copyfile+0xae2>\n+\tldr\tr3, [pc, #416]\t@ (c88 <__gridxc_moreparallelsubs_MOD_copyfile+0xc74>)\n \tmovs\tr1, #46\t@ 0x2e\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tldr\tr0, [pc, #604]\t@ (d48 <__gridxc_moreparallelsubs_MOD_copyfile+0xd34>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tldr\tr2, [r7, #0]\n \tvmov\ts15, r2\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n+\tvmov.f64\td6, #120\t@ 0x3fc00000 1.5\n \tsubw\tr2, r6, #2356\t@ 0x934\n \tldr\tr1, [pc, #584]\t@ (d4c <__gridxc_moreparallelsubs_MOD_copyfile+0xd38>)\n-\tvcvt.f64.s32\td16, s15\n-\tmov.w\tr0, #1000\t@ 0x3e8\n+\tvcvt.f64.s32\td7, s15\n \tldr\tr5, [pc, #580]\t@ (d50 <__gridxc_moreparallelsubs_MOD_copyfile+0xd3c>)\n \tadd\tr1, pc\n \tmovs\tr7, #0\n-\tstr\tr7, [sp, #20]\n \tadd\tr5, pc\n+\tstr\tr7, [sp, #20]\n \tstr\tr7, [sp, #8]\n-\tvmul.f64\td16, d16, d17\n+\tmov\tr0, r5\n+\tvmul.f64\td7, d7, d6\n \tstr\tr7, [sp, #0]\n-\tvcvt.s32.f64\ts15, d16\n+\tvcvt.s32.f64\ts15, d7\n \tvmov\tr3, s15\n-\tcmp\tr3, r0\n+\tcmp.w\tr3, #1000\t@ 0x3e8\n \tit\tge\n-\tmovge\tr3, r0\n+\tmovge.w\tr3, #1000\t@ 0x3e8\n \tstr\tr3, [r2, #0]\n \tmovs\tr3, #15\n \tstr\tr3, [sp, #16]\n \tadd.w\tr3, r1, #8\n \tstr\tr3, [sp, #4]\n \tmovw\tr3, #10000\t@ 0x2710\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [pc, #532]\t@ (d54 <__gridxc_moreparallelsubs_MOD_copyfile+0xd40>)\n-\tmov\tr0, r5\n+\tldr\tr3, [pc, #528]\t@ (d54 <__gridxc_moreparallelsubs_MOD_copyfile+0xd40>)\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tadd\tr3, pc\n \tbl\t0 <__gridxc_alloc_MOD_realloc_s1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_s1\n \tldr\tr3, [r5, #96]\t@ 0x60\n \tldr\tr0, [r5, #76]\t@ 0x4c\n \tmov\tr2, r7\n@@ -1122,15 +1121,15 @@\n \tldr\tr3, [r5, #56]\t@ 0x38\n \tmul.w\tr3, r1, r3\n \tldr\tr1, [r5, #72]\t@ 0x48\n \tldr\tr7, [r1, r0]\n \tldr\tr1, [r5, #36]\t@ 0x24\n \tmovs\tr5, #1\n \tldr\tr0, [r1, r3]\n-\tb.n\t8c2 <__gridxc_moreparallelsubs_MOD_copyfile+0x8ae>\n+\tb.n\t8c4 <__gridxc_moreparallelsubs_MOD_copyfile+0x8b0>\n \tadd.w\tr3, sp, #10624\t@ 0x2980\n \tadd.w\tfp, sp, #636\t@ 0x27c\n \tldr\tr1, [sp, #28]\n \tmov\tr0, fp\n \tadds\tr3, #60\t@ 0x3c\n \tldr\tr2, [r3, #0]\n \tbl\t0 \n@@ -1159,27 +1158,27 @@\n \tsubs\tr2, r7, r3\n \tadd.w\tr3, sp, #10624\t@ 0x2980\n \tadds\tr3, #60\t@ 0x3c\n \tldr\tr3, [r3, #0]\n \tadd.w\tr0, fp, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tb.n\t7fc <__gridxc_moreparallelsubs_MOD_copyfile+0x7e8>\n+\tb.n\t7fe <__gridxc_moreparallelsubs_MOD_copyfile+0x7ea>\n \tadd.w\tr0, sp, #10688\t@ 0x29c0\n \tldr\tr3, [pc, #384]\t@ (d58 <__gridxc_moreparallelsubs_MOD_copyfile+0xd44>)\n \tadds\tr0, #4\n \tmovs\tr2, #9\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tldr\tr0, [r0, #0]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, c00 <__gridxc_moreparallelsubs_MOD_copyfile+0xbec>\n+\tcbz\tr0, c02 <__gridxc_moreparallelsubs_MOD_copyfile+0xbee>\n \tadd.w\tr0, sp, #10688\t@ 0x29c0\n-\tldr\tr3, [pc, #368]\t@ (d5c <__gridxc_moreparallelsubs_MOD_copyfile+0xd48>)\n+\tldr\tr3, [pc, #364]\t@ (d5c <__gridxc_moreparallelsubs_MOD_copyfile+0xd48>)\n \tadds\tr0, #4\n \tmovs\tr2, #9\n \tadd\tr3, pc\n \tmov\tr1, r5\n \tldr\tr0, [r0, #0]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n@@ -1198,15 +1197,15 @@\n \tadd.w\tr2, sp, #10688\t@ 0x29c0\n \tstr.w\tr5, [r3, #164]\t@ 0xa4\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [r3, #40]\t@ 0x28\n \tldr\tr2, [pc, #320]\t@ (d64 <__gridxc_moreparallelsubs_MOD_copyfile+0xd50>)\n \tadd\tr2, pc\n \tstr\tr2, [r3, #48]\t@ 0x30\n-\tldr\tr2, [pc, #320]\t@ (d68 <__gridxc_moreparallelsubs_MOD_copyfile+0xd54>)\n+\tldr\tr2, [pc, #316]\t@ (d68 <__gridxc_moreparallelsubs_MOD_copyfile+0xd54>)\n \tadd\tr2, pc\n \tstr\tr2, [r3, #64]\t@ 0x40\n \tldr\tr2, [sp, #72]\t@ 0x48\n \tsub.w\tr0, r2, #40\t@ 0x28\n \tmov.w\tr2, #384\t@ 0x180\n \tstr\tr2, [r3, #12]\n \tmovs\tr2, #7\n@@ -1214,29 +1213,28 @@\n \tmovs\tr2, #9\n \tstr\tr2, [r3, #68]\t@ 0x44\n \tmov.w\tr2, #2816\t@ 0xb00\n \tmovt\tr2, #256\t@ 0x100\n \tstr\tr2, [r3, #0]\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tldr\tr2, [pc, #284]\t@ (d6c <__gridxc_moreparallelsubs_MOD_copyfile+0xd58>)\n+\tldr\tr2, [pc, #280]\t@ (d6c <__gridxc_moreparallelsubs_MOD_copyfile+0xd58>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, #40]\t@ 0x28\n \tldr\tr1, [r2, #56]\t@ 0x38\n \tldr\tr6, [r2, #36]\t@ 0x24\n \tmul.w\tr3, r1, r3\n \tstr\tr5, [r6, r3]\n \tb.n\t5b0 <__gridxc_moreparallelsubs_MOD_copyfile+0x59c>\n \tldr.w\tr0, [sl]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr1, [r3, #0]\n-\tb.n\t750 <__gridxc_moreparallelsubs_MOD_copyfile+0x73c>\n-\tnop\n+\tb.n\t752 <__gridxc_moreparallelsubs_MOD_copyfile+0x73e>\n \t.word\t0x00000c2a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x00000c20\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000bea\n@@ -1271,17 +1269,17 @@\n R_ARM_REL32\t.bss\n \t.word\t0x00000a32\n R_ARM_REL32\t.LC12\n \t.word\t0x00000a0e\n R_ARM_REL32\t.bss\n \t.word\t0x00000962\n R_ARM_REL32\t.LC14\n-\t.word\t0x00000942\n+\t.word\t0x00000946\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000940\n+\t.word\t0x00000946\n R_ARM_REL32\t.bss\n \t.word\t0x00000912\n R_ARM_REL32\t.LC3\n \t.word\t0x000008da\n R_ARM_REL32\t.bss\n \t.word\t0x00000890\n R_ARM_REL32\t.LC8\n@@ -1309,61 +1307,61 @@\n R_ARM_REL32\t.bss\n \t.word\t0x00000738\n R_ARM_REL32\t.LC8\n \t.word\t0x00000722\n R_ARM_REL32\t.LC11\n \t.word\t0x000006f0\n R_ARM_REL32\t.bss\n-\t.word\t0x00000648\n+\t.word\t0x00000646\n R_ARM_REL32\t.LC21\n-\t.word\t0x0000062c\n+\t.word\t0x0000062a\n R_ARM_REL32\t.LC20\n-\t.word\t0x00000588\n+\t.word\t0x00000586\n R_ARM_REL32\t.bss\n-\t.word\t0x00000582\n+\t.word\t0x00000580\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000572\n+\t.word\t0x00000570\n R_ARM_REL32\t.LC5\n-\t.word\t0x00000564\n+\t.word\t0x00000562\n R_ARM_REL32\t.LC7\n-\t.word\t0x00000516\n+\t.word\t0x00000514\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000518\n+\t.word\t0x00000516\n R_ARM_REL32\t.bss\n-\t.word\t0x00000504\n+\t.word\t0x00000502\n R_ARM_REL32\t.LC12\n-\t.word\t0x000004e0\n+\t.word\t0x000004de\n R_ARM_REL32\t.bss\n-\t.word\t0x00000464\n+\t.word\t0x00000462\n R_ARM_REL32\t.bss\n-\t.word\t0x00000408\n+\t.word\t0x00000406\n R_ARM_REL32\t.LC8\n-\t.word\t0x00000404\n+\t.word\t0x00000402\n R_ARM_REL32\t.LC11\n-\t.word\t0x000002d2\n+\t.word\t0x000002d0\n R_ARM_REL32\t.LC7\n-\t.word\t0x00000258\n+\t.word\t0x00000256\n R_ARM_REL32\t.LC14\n-\t.word\t0x0000023c\n+\t.word\t0x0000023e\n R_ARM_REL32\t.rodata\n-\t.word\t0x0000023a\n+\t.word\t0x0000023e\n R_ARM_REL32\t.bss\n-\t.word\t0x0000020e\n+\t.word\t0x0000020c\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000017a\n+\t.word\t0x00000178\n R_ARM_REL32\t.LC16\n-\t.word\t0x00000168\n+\t.word\t0x00000166\n R_ARM_REL32\t.LC17\n-\t.word\t0x00000154\n+\t.word\t0x00000152\n R_ARM_REL32\t.LC8\n-\t.word\t0x0000013e\n- R_ARM_REL32\t.LC9\n \t.word\t0x0000013c\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x0000013a\n R_ARM_REL32\t.LC10\n-\t.word\t0x00000118\n+\t.word\t0x00000116\n R_ARM_REL32\t.bss\n \tadd.w\tr9, r6, #34\t@ 0x22\n \tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tldr\tr3, [pc, #312]\t@ (eb4 <__gridxc_moreparallelsubs_MOD_copyfile+0xea0>)\n \tmov\tr8, r0\n@@ -1441,27 +1439,27 @@\n \tldr\tr3, [r2, r3]\n \tadd\tr1, r6\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t7e2 <__gridxc_moreparallelsubs_MOD_copyfile+0x7ce>\n+\tb.n\t7e4 <__gridxc_moreparallelsubs_MOD_copyfile+0x7d0>\n \tldr\tr3, [pc, #136]\t@ (ebc <__gridxc_moreparallelsubs_MOD_copyfile+0xea8>)\n \tmovs\tr1, #45\t@ 0x2d\n \tldr\tr2, [sp, #64]\t@ 0x40\n \tmovw\tr4, #34464\t@ 0x86a0\n \tmovt\tr4, #1\n \tldr\tr0, [pc, #128]\t@ (ec0 <__gridxc_moreparallelsubs_MOD_copyfile+0xeac>)\n \tldr.w\tr9, [sp, #80]\t@ 0x50\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t970 <__gridxc_moreparallelsubs_MOD_copyfile+0x95c>\n+\tb.n\t972 <__gridxc_moreparallelsubs_MOD_copyfile+0x95e>\n \tadd.w\tr3, sp, #10688\t@ 0x29c0\n \tadds\tr3, #4\n \tldr\tr3, [r3, #0]\n \tadd.w\tr6, r3, #38\t@ 0x26\n \tcmp\tr6, #1\n \tmov\tr0, r6\n \tit\tcc\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "precision.F90.o", "source2": "precision.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 164 (bytes into file)\n+ Start of section headers: 160 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 7\n Section header string table index: 6\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,16 +1,16 @@\n-There are 7 section headers, starting at offset 0xa4:\n+There are 7 section headers, starting at offset 0xa0:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n [ 1] .text PROGBITS 00000000 000034 000000 00 AX 0 0 1\n [ 2] .data PROGBITS 00000000 000034 000000 00 WA 0 0 1\n [ 3] .bss NOBITS 00000000 000034 000000 00 WA 0 0 1\n [ 4] .note.GNU-stack PROGBITS 00000000 000034 000000 00 0 0 1\n- [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 000034 000033 00 0 0 1\n- [ 6] .shstrtab STRTAB 00000000 000067 00003c 00 0 0 1\n+ [ 5] .ARM.attributes ARM_ATTRIBUTES 00000000 000034 00002d 00 0 0 1\n+ [ 6] .shstrtab STRTAB 00000000 000061 00003c 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "radfft.F90.o", "source2": "radfft.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 4476 (bytes into file)\n+ Start of section headers: 4404 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x117c:\n+There are 12 section headers, starting at offset 0x1134:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000a00 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 000f84 000190 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 000a38 000008 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 000a40 000090 00 WA 0 0 4\n- [ 5] .rodata.str1.4 PROGBITS 00000000 000a40 000013 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 000a54 00000c 00 A 0 0 4\n- [ 7] .note.GNU-stack PROGBITS 00000000 000a60 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000a60 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 000a94 0002b0 10 10 20 4\n- [10] .strtab STRTAB 00000000 000d44 000240 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 001114 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0009bc 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 000f3c 000190 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0009f4 000008 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 0009fc 000090 00 WA 0 0 4\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0009fc 000013 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 000a10 00000c 00 A 0 0 4\n+ [ 7] .note.GNU-stack PROGBITS 00000000 000a1c 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 000a1c 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 000a4c 0002b0 10 10 20 4\n+ [10] .strtab STRTAB 00000000 000cfc 000240 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 0010cc 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -9,28 +9,28 @@\n 5: 00000008 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 6: 0000000c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 7: 00000010 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 8: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 9: 00000060 0 NOTYPE LOCAL DEFAULT 1 $d\n 10: 00000078 0 NOTYPE LOCAL DEFAULT 1 $t\n 11: 00000378 0 NOTYPE LOCAL DEFAULT 1 $d\n- 12: 000003a4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 13: 000006d8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 14: 00000700 0 NOTYPE LOCAL DEFAULT 1 $t\n- 15: 000009c0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 12: 000003ac 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 13: 00000538 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 14: 0000054c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 15: 00000960 0 NOTYPE LOCAL DEFAULT 1 $d\n 16: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 17: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n 18: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n 19: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n 20: 00000001 120 FUNC GLOBAL DEFAULT 1 __gridxc_radfft_MOD_reset_radfft\n 21: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d3\n 22: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d2\n 23: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_dealloc_d1\n 24: 00000000 0 NOTYPE GLOBAL DEFAULT UND __powidf2\n- 25: 00000079 2440 FUNC GLOBAL DEFAULT 1 __gridxc_radfft_MOD_radfft\n+ 25: 00000079 2372 FUNC GLOBAL DEFAULT 1 __gridxc_radfft_MOD_radfft\n 26: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 27: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n 29: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n 31: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n 32: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,53 +1,53 @@\n \n-Relocation section '.rel.text' at offset 0xf84 contains 50 entries:\n+Relocation section '.rel.text' at offset 0xf3c contains 50 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000026 0000150a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d3\n 00000038 0000160a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d2\n 0000004a 0000170a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_dealloc_d1\n 00000060 00000403 R_ARM_REL32 00000000 .LC0\n 00000064 00000203 R_ARM_REL32 00000000 .bss\n 00000068 00000503 R_ARM_REL32 00000008 .LC1\n 0000006c 00000603 R_ARM_REL32 0000000c .LC2\n 00000070 00000703 R_ARM_REL32 00000010 .LC3\n 00000074 00000103 R_ARM_REL32 00000000 .data\n-00000388 00001a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000038c 00001b1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000390 00000103 R_ARM_REL32 00000000 .data\n-00000394 00000203 R_ARM_REL32 00000000 .bss\n+00000390 00001a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000394 00001b1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000398 00000103 R_ARM_REL32 00000000 .data\n 0000039c 00000203 R_ARM_REL32 00000000 .bss\n-000003a0 00000203 R_ARM_REL32 00000000 .bss\n-00000512 0000180a R_ARM_THM_CALL 00000000 __powidf2\n-00000594 00001c0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000005a2 00001d0a R_ARM_THM_CALL 00000000 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n-000005b4 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-000005ba 00001f0a R_ARM_THM_CALL 00000000 free\n-000006e0 00000203 R_ARM_REL32 00000000 .bss\n-000006e4 00001003 R_ARM_REL32 00000000 .rodata\n-000006e8 00000203 R_ARM_REL32 00000000 .bss\n-000006ec 00000203 R_ARM_REL32 00000000 .bss\n-000006f0 00000203 R_ARM_REL32 00000000 .bss\n-000006f4 00000203 R_ARM_REL32 00000000 .bss\n-000006f8 00001a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000006fc 00001b1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000752 0000180a R_ARM_THM_CALL 00000000 __powidf2\n-00000800 0000200a R_ARM_THM_CALL 00000000 exp\n-0000089c 0000210a R_ARM_THM_CALL 00000000 __gridxc_bessph_MOD_bessph\n-0000094a 0000220a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n-0000096e 0000230a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n-000009ac 0000240a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-000009bc 0000250a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000009c8 00000203 R_ARM_REL32 00000000 .bss\n-000009cc 00000203 R_ARM_REL32 00000000 .bss\n-000009d0 00000203 R_ARM_REL32 00000000 .bss\n-000009d4 00001003 R_ARM_REL32 00000000 .rodata\n-000009d8 00000203 R_ARM_REL32 00000000 .bss\n-000009dc 00000403 R_ARM_REL32 00000000 .LC0\n-000009e0 00000603 R_ARM_REL32 0000000c .LC2\n-000009e4 00000703 R_ARM_REL32 00000010 .LC3\n-000009e8 00000103 R_ARM_REL32 00000000 .data\n-000009ec 00000403 R_ARM_REL32 00000000 .LC0\n-000009f0 00001003 R_ARM_REL32 00000000 .rodata\n-000009f4 00000203 R_ARM_REL32 00000000 .bss\n-000009f8 00000503 R_ARM_REL32 00000008 .LC1\n-000009fc 00000103 R_ARM_REL32 00000000 .data\n+000003a0 00000103 R_ARM_REL32 00000000 .data\n+000003a4 00000203 R_ARM_REL32 00000000 .bss\n+000003a8 00000203 R_ARM_REL32 00000000 .bss\n+000004ec 0000180a R_ARM_THM_CALL 00000000 __powidf2\n+00000540 00000203 R_ARM_REL32 00000000 .bss\n+00000544 00001003 R_ARM_REL32 00000000 .rodata\n+00000548 00000203 R_ARM_REL32 00000000 .bss\n+00000598 0000180a R_ARM_THM_CALL 00000000 __powidf2\n+0000060a 00001c0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000618 00001d0a R_ARM_THM_CALL 00000000 __gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n+00000626 00001e0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+0000062c 00001f0a R_ARM_THM_CALL 00000000 free\n+00000772 0000200a R_ARM_THM_CALL 00000000 exp\n+0000080a 0000210a R_ARM_THM_CALL 00000000 __gridxc_bessph_MOD_bessph\n+000008e6 0000220a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d2\n+0000090a 0000230a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d1\n+00000948 0000240a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00000958 0000250a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000970 00000203 R_ARM_REL32 00000000 .bss\n+00000974 00000203 R_ARM_REL32 00000000 .bss\n+00000978 00000203 R_ARM_REL32 00000000 .bss\n+0000097c 00001a19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000980 00001b1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000984 00000203 R_ARM_REL32 00000000 .bss\n+00000988 00000203 R_ARM_REL32 00000000 .bss\n+0000098c 00000203 R_ARM_REL32 00000000 .bss\n+00000990 00001003 R_ARM_REL32 00000000 .rodata\n+00000994 00000203 R_ARM_REL32 00000000 .bss\n+00000998 00000403 R_ARM_REL32 00000000 .LC0\n+0000099c 00000603 R_ARM_REL32 0000000c .LC2\n+000009a0 00000703 R_ARM_REL32 00000010 .LC3\n+000009a4 00000103 R_ARM_REL32 00000000 .data\n+000009a8 00000403 R_ARM_REL32 00000000 .LC0\n+000009ac 00001003 R_ARM_REL32 00000000 .rodata\n+000009b0 00000203 R_ARM_REL32 00000000 .bss\n+000009b4 00000503 R_ARM_REL32 00000008 .LC1\n+000009b8 00000103 R_ARM_REL32 00000000 .data\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -62,876 +62,856 @@\n 00000078 <__gridxc_radfft_MOD_radfft>:\n __gridxc_radfft_MOD_radfft():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3800]\t@ 0xed8\n-\tldr\tr6, [pc, #760]\t@ (388 <__gridxc_radfft_MOD_radfft+0x310>)\n+\tldr\tr5, [pc, #768]\t@ (390 <__gridxc_radfft_MOD_radfft+0x318>)\n \tsub\tsp, #196\t@ 0xc4\n-\tldr\tr5, [pc, #760]\t@ (38c <__gridxc_radfft_MOD_radfft+0x314>)\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tadd\tr6, pc\n+\tldr\tr4, [pc, #768]\t@ (394 <__gridxc_radfft_MOD_radfft+0x31c>)\n+\tadd\tr5, pc\n \tldr\tr1, [r1, #0]\n-\tmovs\tr4, #8\n-\tldr\tr5, [r6, r5]\n-\tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #188]\t@ 0xbc\n-\tmov.w\tr5, #0\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr3, [pc, #740]\t@ (390 <__gridxc_radfft_MOD_radfft+0x318>)\n+\tldr\tr4, [r5, r4]\n \tmov\tr5, r2\n-\tstr\tr4, [sp, #160]\t@ 0xa0\n-\tmovs\tr2, #0\n+\tldr\tr4, [r4, #0]\n+\tstr\tr4, [sp, #188]\t@ 0xbc\n+\tmov.w\tr4, #0\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [pc, #752]\t@ (398 <__gridxc_radfft_MOD_radfft+0x320>)\n+\tstr\tr1, [sp, #48]\t@ 0x30\n \tadd\tr3, pc\n \tldr\tr4, [sp, #296]\t@ 0x128\n-\tstr\tr1, [sp, #44]\t@ 0x2c\n-\tmovw\tr1, #769\t@ 0x301\n-\tvstr\td16, [sp, #164]\t@ 0xa4\n-\tldr\tr3, [r3, #0]\n-\tstr\tr4, [sp, #132]\t@ 0x84\n-\tadds\tr6, r3, #1\n \tstr\tr0, [sp, #124]\t@ 0x7c\n-\tstr\tr2, [sp, #172]\t@ 0xac\n+\tstr\tr4, [sp, #140]\t@ 0x8c\n+\tldr\tr2, [r3, #0]\n+\tadd\tr3, sp, #164\t@ 0xa4\n+\tmov\tr1, r3\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tadds\tr0, r2, #1\n+\tmov.w\tr3, #0\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tstr\tr3, [r1, #4]\n+\tmov.w\tr1, #8\n+\tstr\tr1, [sp, #160]\t@ 0xa0\n+\tmovw\tr1, #769\t@ 0x301\n \tstrh.w\tr1, [sp, #168]\t@ 0xa8\n-\tbne.n\td4 <__gridxc_radfft_MOD_radfft+0x5c>\n-\tldr\tr1, [pc, #708]\t@ (394 <__gridxc_radfft_MOD_radfft+0x31c>)\n+\tbne.n\tda <__gridxc_radfft_MOD_radfft+0x62>\n+\tldr\tr1, [pc, #708]\t@ (39c <__gridxc_radfft_MOD_radfft+0x324>)\n \tadd\tr1, pc\n-\tstr\tr2, [r1, #0]\n-\tldr\tr2, [sp, #124]\t@ 0x7c\n-\tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #60]\t@ 0x3c\n-\tcmp\tr3, r2\n-\tblt.w\t97c <__gridxc_radfft_MOD_radfft+0x904>\n-\tldr\tr3, [pc, #692]\t@ (398 <__gridxc_radfft_MOD_radfft+0x320>)\n+\tstr\tr3, [r1, #0]\n+\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [r3, #0]\n+\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tr2, r3\n+\tblt.w\t918 <__gridxc_radfft_MOD_radfft+0x8a0>\n+\tldr\tr3, [pc, #696]\t@ (3a0 <__gridxc_radfft_MOD_radfft+0x328>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #4]\n-\tadds\tr0, r3, #1\n-\tbne.n\tf4 <__gridxc_radfft_MOD_radfft+0x7c>\n-\tldr\tr2, [pc, #688]\t@ (39c <__gridxc_radfft_MOD_radfft+0x324>)\n+\tadds\tr2, r3, #1\n+\tbne.n\tfa <__gridxc_radfft_MOD_radfft+0x82>\n+\tldr\tr2, [pc, #688]\t@ (3a4 <__gridxc_radfft_MOD_radfft+0x32c>)\n \tmovs\tr1, #0\n \tadd\tr2, pc\n \tstr\tr1, [r2, #60]\t@ 0x3c\n \tstr\tr1, [r2, #108]\t@ 0x6c\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tldr\tr2, [sp, #48]\t@ 0x30\n \tcmp\tr3, r2\n-\tblt.w\t906 <__gridxc_radfft_MOD_radfft+0x88e>\n-\tvldr\ts15, [sp, #44]\t@ 0x2c\n+\tblt.w\t8a2 <__gridxc_radfft_MOD_radfft+0x82a>\n+\tvldr\ts13, [sp, #48]\t@ 0x30\n \tmov.w\tr8, #0\n-\tvldr\td16, [r5]\n+\tvldr\td7, [r5]\n \tmov.w\tr9, #0\n \tmovt\tr9, #49136\t@ 0xbff0\n-\tldr\tr3, [pc, #652]\t@ (3a0 <__gridxc_radfft_MOD_radfft+0x328>)\n-\tvcvt.f64.s32\td17, s15\n-\tvldr\td18, [pc, #608]\t@ 378 <__gridxc_radfft_MOD_radfft+0x300>\n-\tadd\tr3, pc\n-\tvldr\td9, [pc, #608]\t@ 380 <__gridxc_radfft_MOD_radfft+0x308>\n-\tvdiv.f64\td10, d18, d16\n-\tvmov.f64\td19, d17\n+\tldr\tr3, [pc, #656]\t@ (3a8 <__gridxc_radfft_MOD_radfft+0x330>)\n+\tvcvt.f64.s32\td14, s13\n+\tvldr\td6, [pc, #600]\t@ 378 <__gridxc_radfft_MOD_radfft+0x300>\n+\tadd\tr3, pc\n+\tvldr\td5, [pc, #604]\t@ 380 <__gridxc_radfft_MOD_radfft+0x308>\n+\tvldr\td9, [pc, #608]\t@ 388 <__gridxc_radfft_MOD_radfft+0x310>\n+\tvdiv.f64\td8, d7, d14\n \tldr\tr0, [r3, #24]\n \tldrd\tr4, r1, [r3]\n-\tstr\tr0, [sp, #88]\t@ 0x58\n+\tstr\tr0, [sp, #92]\t@ 0x5c\n+\tvdiv.f64\td10, d5, d7\n \tldr\tr7, [r3, #20]\n-\tvdiv.f64\td8, d16, d19\n \tadds\tr2, r1, r0\n+\tstr\tr4, [sp, #100]\t@ 0x64\n \tadd\tr0, r2\n-\tvstr\td17, [sp, #136]\t@ 0x88\n-\tvmov.i64\td17, #0x0000000000000000\n-\tstr\tr4, [sp, #96]\t@ 0x60\n \tmla\tr5, r7, r2, r4\n \tmla\tr0, r7, r0, r4\n-\tvstr\td17, [r5]\n+\tvstr\td6, [r5]\n \tstrd\tr8, r9, [r0]\n \tldr\tr0, [sp, #60]\t@ 0x3c\n \tcmp\tr0, #0\n \tvmul.f64\td9, d8, d9\n-\tble.w\t8f0 <__gridxc_radfft_MOD_radfft+0x878>\n+\tble.w\t898 <__gridxc_radfft_MOD_radfft+0x820>\n \tldr.w\tfp, [r3, #48]\t@ 0x30\n \tldr\tr3, [r3, #36]\t@ 0x24\n-\tldr\tr4, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #92]\t@ 0x5c\n \tadd.w\tr6, r1, fp\n-\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tadds\tr3, r6, r3\n \tadd.w\tip, r3, r4\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #100]\t@ 0x64\n \tadds\tr0, r4, r6\n \tadds\tr5, r4, r0\n \tmla\tr0, r0, r7, r3\n \tmla\tr5, r7, r5, r3\n-\tvstr\td17, [r0]\n+\tvstr\td6, [r0]\n \tadd.w\tr0, r4, ip\n \tmov\tr4, r3\n \tmla\tr3, ip, r7, r3\n \tstrd\tr8, r9, [r5]\n \tmla\tr0, r7, r0, r4\n \tstrd\tr8, r9, [r3]\n \tldr\tr3, [sp, #60]\t@ 0x3c\n-\tvstr\td17, [r0]\n+\tvstr\td6, [r0]\n \tcmp\tr3, #1\n-\tbeq.w\t3a4 <__gridxc_radfft_MOD_radfft+0x32c>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tbeq.w\t3ac <__gridxc_radfft_MOD_radfft+0x334>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tadd.w\tr0, fp, r6\n-\tstr\tr1, [sp, #40]\t@ 0x28\n+\tstr\tr1, [sp, #44]\t@ 0x2c\n \tmov\tr5, r6\n-\tstr\tr6, [sp, #56]\t@ 0x38\n+\tstr\tr6, [sp, #64]\t@ 0x40\n \tmul.w\tsl, fp, r7\n \tlsls\tr1, r3, #1\n-\tstr\tr1, [sp, #116]\t@ 0x74\n+\tstr\tr1, [sp, #128]\t@ 0x80\n \tadds\tr4, r1, r6\n \tadd\tr1, r0\n-\tldr\tr6, [sp, #112]\t@ 0x70\n+\tldr\tr6, [sp, #120]\t@ 0x78\n \tadds\tr3, r0, r3\n-\tstr\tr4, [sp, #52]\t@ 0x34\n+\tstr\tr4, [sp, #56]\t@ 0x38\n \tmov\tlr, r0\n \tmul.w\tr1, r7, r1\n \tmov\tip, sl\n-\tstr\tr1, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #84]\t@ 0x54\n \tlsls\tr1, r6, #1\n \tsubs\tr2, r2, r1\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #96]\t@ 0x60\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #100]\t@ 0x64\n \tmul.w\tr3, r7, r3\n-\tstr\tr1, [sp, #120]\t@ 0x78\n+\tstr\tr1, [sp, #132]\t@ 0x84\n \tmul.w\tr6, r7, r6\n-\tvmov.f64\td18, #8\t@ 0x40400000 3.0\n-\tstr\tr0, [sp, #100]\t@ 0x64\n-\tstr\tr5, [sp, #104]\t@ 0x68\n+\tvmov.f64\td5, #8\t@ 0x40400000 3.0\n+\tstr\tr0, [sp, #108]\t@ 0x6c\n+\tstr\tr5, [sp, #112]\t@ 0x70\n \tmla\tr1, r4, r7, r2\n \tadd\tr2, r3\n \tmov\tr4, r3\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr1, [sp, #80]\t@ 0x50\n \tmovs\tr2, #3\n-\tstr\tr2, [sp, #92]\t@ 0x5c\n+\tstr\tr2, [sp, #96]\t@ 0x60\n \tmovs\tr2, #2\n-\tb.n\t2ec <__gridxc_radfft_MOD_radfft+0x274>\n-\tvstr\td17, [r8]\n-\tvldr\td16, [r0]\n-\tvmul.f64\td16, d18, d16\n+\tb.n\t2e8 <__gridxc_radfft_MOD_radfft+0x270>\n+\tvstr\td6, [r8]\n+\tvldr\td7, [r0]\n+\tvmul.f64\td7, d5, d7\n \tadds\tr1, #1\n \tadd\tr3, r6\n \tadd\tr0, r6\n \tcmp\tr1, r2\n-\tvstr\td16, [r8]\n-\tbne.w\t32a <__gridxc_radfft_MOD_radfft+0x2b2>\n-\tldrd\tr3, r4, [sp, #104]\t@ 0x68\n+\tvstr\td7, [r8]\n+\tbne.w\t326 <__gridxc_radfft_MOD_radfft+0x2ae>\n+\tldrd\tr3, r4, [sp, #112]\t@ 0x70\n \tmov\tr8, r2\n-\tldr\tr0, [sp, #116]\t@ 0x74\n+\tldr\tr0, [sp, #128]\t@ 0x80\n \tadd\tr3, r0\n \tmov\tr9, r3\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tmul.w\tr1, r2, r3\n \tldr\tr3, [sp, #120]\t@ 0x78\n+\tmul.w\tr1, r2, r3\n+\tldr\tr3, [sp, #132]\t@ 0x84\n \tadd.w\tr5, lr, r1\n \tadd\tr9, r1\n \tsubs\tr1, r1, r3\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n \tadd\tr1, r3\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tldr\tr3, [sp, #100]\t@ 0x64\n \tmla\tr9, r7, r9, r3\n-\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tadd\tr3, r5\n \tadd\tr5, r0\n \tmul.w\tr3, r7, r3\n \tmul.w\tr5, r7, r5\n \tsub.w\tsl, r5, r3\n-\tldr\tr5, [sp, #88]\t@ 0x58\n+\tldr\tr5, [sp, #92]\t@ 0x5c\n \tadd.w\tlr, r5, r1\n \tadd\tr1, r0\n-\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #100]\t@ 0x64\n \tmov\tr5, sl\n \tmul.w\tlr, r7, lr\n \tmul.w\tr1, r7, r1\n \tsub.w\tlr, lr, r3\n \tsubs\tr1, r1, r3\n \tadd\tr3, r0\n \tadd.w\tr0, lr, r3\n-\tvstr\td17, [r3]\n+\tvstr\td6, [r3]\n \tcmp\tr2, r8\n-\tvldr\td16, [r0]\n+\tvldr\td7, [r0]\n \tadd.w\tr0, r5, r3\n-\tvneg.f64\td16, d16\n-\tvstr\td16, [r3]\n-\tvstr\td17, [r0]\n-\tbgt.w\t79a <__gridxc_radfft_MOD_radfft+0x722>\n+\tvneg.f64\td7, d7\n+\tvstr\td7, [r3]\n+\tvstr\td6, [r0]\n+\tbgt.w\t858 <__gridxc_radfft_MOD_radfft+0x7e0>\n \tadd\tr1, r3\n-\tvldr\td16, [r1]\n-\tvneg.f64\td16, d16\n-\tvstr\td16, [r0]\n-\tldr\tr1, [sp, #40]\t@ 0x28\n+\tvldr\td7, [r1]\n+\tvneg.f64\td7, d7\n+\tvstr\td7, [r0]\n+\tldr\tr1, [sp, #44]\t@ 0x2c\n \tadds\tr2, #1\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [sp, #96]\t@ 0x60\n \tadd\tr4, ip\n \tadd\tr1, fp\n-\tstr\tr1, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #52]\t@ 0x34\n+\tstr\tr1, [sp, #44]\t@ 0x2c\n+\tldr\tr1, [sp, #56]\t@ 0x38\n \tadds\tr3, #2\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr1, fp\n-\tstr\tr1, [sp, #52]\t@ 0x34\n-\tldr\tr1, [sp, #64]\t@ 0x40\n+\tstr\tr3, [sp, #96]\t@ 0x60\n \tadd\tr1, fp\n-\tstr\tr1, [sp, #64]\t@ 0x40\n+\tstr\tr1, [sp, #56]\t@ 0x38\n \tldr\tr1, [sp, #68]\t@ 0x44\n-\tadd\tr1, ip\n+\tadd\tr1, fp\n \tstr\tr1, [sp, #68]\t@ 0x44\n \tldr\tr1, [sp, #76]\t@ 0x4c\n \tadd\tr1, ip\n \tstr\tr1, [sp, #76]\t@ 0x4c\n \tldr\tr1, [sp, #80]\t@ 0x50\n \tadd\tr1, ip\n \tstr\tr1, [sp, #80]\t@ 0x50\n-\tldr\tr1, [sp, #56]\t@ 0x38\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tadd\tr1, ip\n+\tstr\tr1, [sp, #84]\t@ 0x54\n+\tldr\tr1, [sp, #64]\t@ 0x40\n \tadd\tr1, fp\n-\tstr\tr1, [sp, #56]\t@ 0x38\n+\tstr\tr1, [sp, #64]\t@ 0x40\n \tldr\tr1, [sp, #60]\t@ 0x3c\n \tcmp\tr1, r2\n-\tblt.w\t8fc <__gridxc_radfft_MOD_radfft+0x884>\n+\tblt.n\t3ac <__gridxc_radfft_MOD_radfft+0x334>\n \tvmov\ts15, r3\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tvcvt.f64.s32\td18, s15\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tvcvt.f64.s32\td5, s15\n \tadd.w\tlr, r3, fp\n-\tstrd\tlr, r3, [sp, #100]\t@ 0x64\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n-\tadds\tr5, r1, r3\n+\tstrd\tlr, r3, [sp, #108]\t@ 0x6c\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tstr\tr4, [sp, #108]\t@ 0x6c\n+\tstr\tr4, [sp, #116]\t@ 0x74\n+\tadds\tr5, r1, r3\n+\tldr\tr1, [sp, #68]\t@ 0x44\n \tadd.w\tr8, r1, r3\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [sp, #56]\t@ 0x38\n \tmul.w\tr5, r7, r5\n \tsub.w\tr9, r1, r3\n \tsub.w\tr8, r8, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tsubs\tr5, r5, r4\n-\tstr\tr3, [sp, #128]\t@ 0x80\n-\tmovs\tr1, #0\n-\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldrd\tr3, r0, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tldr\tr3, [sp, #84]\t@ 0x54\n \tmul.w\tr8, r7, r8\n \tmul.w\tr9, r7, r9\n-\tstr.w\tr8, [sp, #84]\t@ 0x54\n+\tsubs\tr5, r5, r4\n \tsub.w\tsl, r3, r4\n-\tldr\tr3, [sp, #128]\t@ 0x80\n-\tstr.w\tr9, [sp, #48]\t@ 0x30\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tmovs\tr1, #0\n+\tstr.w\tr9, [sp, #52]\t@ 0x34\n+\tstr.w\tr8, [sp, #88]\t@ 0x58\n \tadd.w\tr8, r5, r3\n-\tvstr\td17, [r3]\n+\tvstr\td6, [r3]\n \tcmp\tr1, #1\n-\tvldr\td16, [r8]\n+\tvldr\td7, [r8]\n \tadd.w\tr8, sl, r3\n-\tvmul.f64\td16, d18, d16\n-\tvstr\td16, [r3]\n-\tble.w\t1fe <__gridxc_radfft_MOD_radfft+0x186>\n-\tldr\tr4, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [r3]\n+\tble.w\t1fc <__gridxc_radfft_MOD_radfft+0x184>\n+\tldr\tr4, [sp, #52]\t@ 0x34\n \tcmp\tr1, r2\n \tadd.w\tr9, r4, r0\n-\tvldr\td19, [r9]\n-\tvsub.f64\td16, d16, d19\n-\tvstr\td16, [r3]\n-\tvstr\td17, [r8]\n-\tblt.w\t7c6 <__gridxc_radfft_MOD_radfft+0x74e>\n-\tvmov.f64\td16, d17\n-\tldr\tr4, [sp, #84]\t@ 0x54\n+\tvldr\td4, [r9]\n+\tvsub.f64\td7, d7, d4\n+\tvstr\td7, [r3]\n+\tvstr\td6, [r8]\n+\tblt.w\t88a <__gridxc_radfft_MOD_radfft+0x812>\n+\tvmov.f64\td7, d6\n+\tldr\tr4, [sp, #88]\t@ 0x58\n \tadd.w\tr9, r4, r0\n-\tvldr\td19, [r9]\n-\tvsub.f64\td16, d16, d19\n-\tb.n\t20a <__gridxc_radfft_MOD_radfft+0x192>\n+\tvldr\td4, [r9]\n+\tvsub.f64\td7, d7, d4\n+\tb.n\t208 <__gridxc_radfft_MOD_radfft+0x190>\n+\tnop.w\n+\t...\n \t.word\t0x54442d18\n \t.word\t0x400921fb\n \t.word\t0x33d43651\n \t.word\t0x3fd98845\n-\t.word\t0x000002ee\n+\t.word\t0x000002fa\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002dc\n+\t.word\t0x000002ec\n R_ARM_REL32\t.data\n-\t.word\t0x000002c0\n+\t.word\t0x000002c2\n R_ARM_REL32\t.bss\n-\t.word\t0x000002b2\n+\t.word\t0x000002b4\n R_ARM_REL32\t.data\n-\t.word\t0x000002aa\n+\t.word\t0x000002ac\n R_ARM_REL32\t.bss\n-\t.word\t0x00000282\n+\t.word\t0x00000284\n R_ARM_REL32\t.bss\n-\tvmov\tr3, s15\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tblt.n\t3dc <__gridxc_radfft_MOD_radfft+0x364>\n-\tldr\tr3, [pc, #816]\t@ (6e0 <__gridxc_radfft_MOD_radfft+0x668>)\n+\tblt.n\t3e2 <__gridxc_radfft_MOD_radfft+0x36a>\n+\tldr\tr3, [pc, #396]\t@ (540 <__gridxc_radfft_MOD_radfft+0x4c8>)\n \tmovs\tr2, #0\n \tmovs\tr6, #0\n \tmovs\tr7, #0\n \tadd\tr3, pc\n \tldrd\tr0, r1, [r3, #128]\t@ 0x80\n \tldrd\tr3, r5, [r3, #108]\t@ 0x6c\n \tmul.w\tr1, r0, r1\n \tmla\tr3, r5, r0, r3\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tadds\tr2, #1\n \tstrd\tr6, r7, [r3]\n \tcmp\tr0, r2\n \tadd\tr3, r1\n-\tbge.n\t3c8 <__gridxc_radfft_MOD_radfft+0x350>\n+\tbge.n\t3ce <__gridxc_radfft_MOD_radfft+0x356>\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tcmp\tr3, #0\n-\tblt.w\t7d4 <__gridxc_radfft_MOD_radfft+0x75c>\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tvmov.i64\td13, #0x0000000000000000\n-\tldr\tr3, [pc, #768]\t@ (6e4 <__gridxc_radfft_MOD_radfft+0x66c>)\n-\tadd.w\tr9, sp, #152\t@ 0x98\n-\tldr.w\tfp, [pc, #764]\t@ 6e8 <__gridxc_radfft_MOD_radfft+0x670>\n-\tldr.w\tr8, [pc, #764]\t@ 6ec <__gridxc_radfft_MOD_radfft+0x674>\n+\tblt.w\t746 <__gridxc_radfft_MOD_radfft+0x6ce>\n+\tldr\tr3, [pc, #352]\t@ (544 <__gridxc_radfft_MOD_radfft+0x4cc>)\n+\tvldr\td13, [pc, #336]\t@ 538 <__gridxc_radfft_MOD_radfft+0x4c0>\n \tadd\tr3, pc\n \tadds\tr3, #8\n-\tadd\tfp, pc\n \tstr\tr3, [sp, #112]\t@ 0x70\n-\tlsls\tr3, r1, #1\n-\tlsls\tr2, r1, #2\n-\tcmp\tr3, r1\n-\tmov\tsl, r3\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmov.w\tsl, r3, lsl #1\n+\tlsls\tr2, r3, #2\n+\tcmp\tr3, sl\n \tstr\tr2, [sp, #108]\t@ 0x6c\n-\tvldr\td14, [pc, #724]\t@ 6d8 <__gridxc_radfft_MOD_radfft+0x660>\n-\tmov\tr2, r3\n-\tadd\tr8, pc\n-\tmov\tr3, fp\n \tit\tge\n-\tmovge\tr2, r1\n-\tstr.w\tr9, [sp, #80]\t@ 0x50\n-\tstr\tr2, [sp, #64]\t@ 0x40\n-\tmovs\tr2, #0\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tadd\tr2, sp, #144\t@ 0x90\n-\tstr\tr2, [sp, #104]\t@ 0x68\n-\tadd\tr2, sp, #164\t@ 0xa4\n-\tstr\tr2, [sp, #116]\t@ 0x74\n-\tadd\tr2, sp, #172\t@ 0xac\n-\tstr\tr2, [sp, #120]\t@ 0x78\n-\tldrd\tr0, lr, [r8, #60]\t@ 0x3c\n+\tmovge\tr3, sl\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tmovs\tr3, #0\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr3, sp, #144\t@ 0x90\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tadd\tr3, sp, #152\t@ 0x98\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr0, [pc, #312]\t@ (548 <__gridxc_radfft_MOD_radfft+0x4d0>)\n \tcmp.w\tsl, #1\n-\tldr.w\tfp, [r8, #84]\t@ 0x54\n-\tldr.w\tip, [r8, #80]\t@ 0x50\n-\tadd.w\tr1, lr, fp\n-\tstr\tr0, [sp, #48]\t@ 0x30\n-\tadd.w\tr2, fp, r1\n-\tmla\tr1, ip, r1, r0\n-\tmla\tr2, ip, r2, r0\n+\tadd\tr0, pc\n+\tldrd\tr5, lr, [r0, #60]\t@ 0x3c\n+\tldr\tr2, [r0, #84]\t@ 0x54\n+\tldr.w\tip, [r0, #80]\t@ 0x50\n+\tadd.w\tr1, lr, r2\n+\tadd.w\tr3, r2, r1\n+\tmla\tr1, ip, r1, r5\n+\tmla\tr3, ip, r3, r5\n \tstr\tr1, [sp, #68]\t@ 0x44\n \tvstr\td13, [r1]\n-\tvstr\td13, [r2]\n-\tmov.w\tr2, fp, lsl #1\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tble.w\t562 <__gridxc_radfft_MOD_radfft+0x4ea>\n-\tldr.w\tr1, [r8, #48]\t@ 0x30\n-\tldr.w\tr2, [r8, #4]\n-\tldr\tr5, [sp, #60]\t@ 0x3c\n-\tldr.w\tr0, [r8, #24]\n-\tldr.w\tr7, [r8]\n-\tldr.w\tr4, [r8, #20]\n-\tmla\tr6, r1, r5, r2\n-\tldr.w\tr1, [r8, #36]\t@ 0x24\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tmla\tr6, r1, r2, r6\n-\tldr\tr1, [sp, #56]\t@ 0x38\n-\trsb\tr2, r5, #1\n-\tadd\tr6, r0\n-\tadd\tr2, r1\n-\tadd\tr0, r6\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tmla\tr6, r4, r6, r7\n-\tldr.w\tr2, [r8, #96]\t@ 0x60\n-\tmla\tr7, r4, r0, r7\n-\tcmp\tr1, #1\n-\tbgt.w\t700 <__gridxc_radfft_MOD_radfft+0x688>\n-\tmul.w\tr1, r2, ip\n-\tmovs\tr4, #1\n-\tstr\tr1, [sp, #52]\t@ 0x34\n-\tmla\tlr, r4, r2, lr\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr1, [sp, #72]\t@ 0x48\n+\tvstr\td13, [r3]\n+\tmov.w\tr3, r2, lsl #1\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tble.w\t5de <__gridxc_radfft_MOD_radfft+0x566>\n+\tldr\tr1, [r0, #48]\t@ 0x30\n+\tldr\tr3, [r0, #4]\n+\tldr\tr7, [sp, #60]\t@ 0x3c\n+\tldr\tr4, [r0, #20]\n+\trsb\tr8, r7, #1\n+\tmla\tr6, r1, r7, r3\n+\tldr\tr1, [r0, #36]\t@ 0x24\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tmla\tr6, r1, r3, r6\n+\tldr\tr1, [r0, #24]\n+\tldr\tr3, [r0, #0]\n+\tadd\tr6, r1\n+\tldr\tr0, [r0, #96]\t@ 0x60\n+\tadd\tr1, r6\n+\tstr\tr0, [sp, #52]\t@ 0x34\n+\tmla\tr6, r4, r6, r3\n+\tmla\tr9, r4, r1, r3\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr3, r8\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tcmp\tr3, #1\n+\titt\tle\n+\tmovle\tr4, #1\n+\tmulle.w\tr8, r0, ip\n+\tbgt.n\t54c <__gridxc_radfft_MOD_radfft+0x4d4>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tvmov.f64\td12, #240\t@ 0xbf800000 -1.0\n-\tadd\tr2, lr\n-\tadd\tfp, lr\n-\tldr\tr5, [sp, #48]\t@ 0x30\n+\tldr\tr7, [sp, #80]\t@ 0x50\n \tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n-\tstr.w\tr8, [sp, #76]\t@ 0x4c\n-\tmul.w\tfp, ip, fp\n-\tmul.w\tr9, ip, r2\n+\tmla\tlr, r4, r3, lr\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tadd\tr2, lr\n+\tadd\tr7, lr\n+\tmul.w\tr2, ip, r2\n+\tmul.w\tr7, ip, r7\n+\tadd\tr5, r2\n+\tsubs\tr7, r7, r2\n \tsub.w\tr2, sl, r4\n-\tadd\tr5, fp\n-\tsub.w\tr9, r9, fp\n-\tadd.w\tfp, r1, r2, lsl #3\n-\tldr\tr2, [sp, #60]\t@ 0x3c\n-\tmov\tr8, fp\n+\tadd.w\tfp, r3, r2, lsl #3\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tmov\tr2, fp\n \tmov\tfp, r6\n-\tmov\tr6, r7\n-\tand.w\tr2, r2, #1\n-\tldr\tr7, [sp, #52]\t@ 0x34\n-\tstr\tr2, [sp, #48]\t@ 0x30\n+\tand.w\tr3, r3, #1\n \tstr\tr3, [sp, #52]\t@ 0x34\n-\tb.n\t544 <__gridxc_radfft_MOD_radfft+0x4cc>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tvldr\td15, [r8]\n+\tmov\tr3, r8\n+\tmov\tr6, r2\n+\tmov\tr8, r9\n+\tmov\tr9, r3\n+\tb.n\t51a <__gridxc_radfft_MOD_radfft+0x4a2>\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tvldr\td7, [r6]\n \tcmp\tr3, #0\n \tsub.w\tr3, sl, r4\n \tvmov\ts0, r3\n-\tvseleq.f64\td17, d11, d12\n+\tite\teq\n+\tvmoveq.f64\td15, d11\n+\tvmovne.f64\td15, d12\n \tvcvt.f64.s32\td0, s0\n-\tvmul.f64\td15, d17, d15\n+\tvmul.f64\td15, d15, d7\n \tvnmul.f64\td0, d8, d0\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tadds\tr4, #1\n \tbl\t0 <__powidf2>\n R_ARM_THM_CALL\t__powidf2\n \tvmul.f64\td0, d0, d15\n-\tvldr\td16, [fp]\n-\tadd.w\tr0, r9, r5\n-\tsub.w\tr8, r8, #8\n+\tvldr\td7, [fp]\n+\tadds\tr0, r7, r5\n+\tsubs\tr6, #8\n \tcmp\tsl, r4\n \tvmul.f64\td0, d0, d9\n-\tvmul.f64\td16, d16, d0\n-\tvstr\td16, [r5]\n-\tadd\tr5, r7\n-\tvldr\td16, [r6]\n-\tvmul.f64\td16, d16, d0\n-\tvstr\td16, [r0]\n-\tble.n\t55c <__gridxc_radfft_MOD_radfft+0x4e4>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [r5]\n+\tadd\tr5, r9\n+\tvldr\td7, [r8]\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [r0]\n+\tble.n\t5de <__gridxc_radfft_MOD_radfft+0x566>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr4, r3\n-\tbne.n\t4ee <__gridxc_radfft_MOD_radfft+0x476>\n+\tbne.n\t4c2 <__gridxc_radfft_MOD_radfft+0x44a>\n \tvmov\ts15, r4\n \tvmov.f64\td15, d13\n \tvcvt.f64.s32\td0, s15\n \tvmul.f64\td0, d0, d8\n-\tb.n\t50e <__gridxc_radfft_MOD_radfft+0x496>\n-\tldr.w\tr8, [sp, #76]\t@ 0x4c\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tb.n\t4e8 <__gridxc_radfft_MOD_radfft+0x470>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x00000182\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000158\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000132\n+ R_ARM_REL32\t.bss\n+\tadd.w\tfp, lr, r0\n+\tlsls\tr3, r2, #1\n+\tadd.w\tr7, r2, fp\n+\tadd\tfp, r3\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tmul.w\tr8, r0, ip\n+\tstrd\tr5, r2, [sp, #84]\t@ 0x54\n+\tmovs\tr4, #1\n+\tmul.w\tr7, ip, r7\n+\tstrd\tip, sl, [sp, #92]\t@ 0x5c\n+\tmul.w\tfp, ip, fp\n+\tsub.w\tr3, fp, r7\n+\tadd.w\tfp, r1, #8\n+\tadd\tr7, r5\n+\tmov\tsl, fp\n+\tmov\tr5, r6\n+\tmov\tfp, lr\n+\tmov\tr6, r9\n+\tmov\tr9, r3\n+\tvmov\ts15, r4\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tvldmia\tsl!, {d11}\n+\tadds\tr4, #1\n+\tvcvt.f64.s32\td0, s15\n+\tvmul.f64\td0, d0, d8\n+\tbl\t0 <__powidf2>\n+ R_ARM_THM_CALL\t__powidf2\n+\tvmul.f64\td0, d9, d0\n+\tvldr\td7, [r5]\n+\tadd.w\tr0, r9, r7\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tvmul.f64\td0, d0, d11\n+\tcmp\tr4, r3\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [r7]\n+\tadd\tr7, r8\n+\tvldr\td7, [r6]\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [r0]\n+\tblt.n\t584 <__gridxc_radfft_MOD_radfft+0x50c>\n+\tldr.w\tsl, [sp, #96]\t@ 0x60\n+\tmov\tr9, r6\n+\tldrd\tr2, ip, [sp, #88]\t@ 0x58\n+\tmov\tr6, r5\n+\tmov\tlr, fp\n+\tldr\tr5, [sp, #84]\t@ 0x54\n+\tcmp\tsl, r4\n+\tbgt.w\t482 <__gridxc_radfft_MOD_radfft+0x40a>\n+\tldr\tr2, [sp, #104]\t@ 0x68\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tmovs\tr2, #8\n \tstr\tr3, [sp, #152]\t@ 0x98\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n \tldr\tr3, [sp, #108]\t@ 0x6c\n \tstr\tr3, [sp, #184]\t@ 0xb8\n-\tldr\tr3, [sp, #120]\t@ 0x78\n-\tldr\tr0, [sp, #80]\t@ 0x50\n-\tstr\tr2, [sp, #160]\t@ 0xa0\n-\tmovs\tr2, #1\n-\tstr\tr2, [sp, #180]\t@ 0xb4\n-\tmov.w\tr2, #4294967295\t@ 0xffffffff\n-\tvst1.32\t{d14}, [r3]\n-\tldr\tr3, [sp, #116]\t@ 0x74\n-\tstr\tr2, [sp, #156]\t@ 0x9c\n-\tmovw\tr2, #769\t@ 0x301\n-\tvstr\td16, [r3]\n-\tstrh.w\tr2, [sp, #168]\t@ 0xa8\n+\tmovs\tr3, #8\n+\tstr\tr3, [sp, #172]\t@ 0xac\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n+\tmovs\tr3, #0\n+\tstrd\tr3, r3, [r2]\n+\tmovs\tr3, #1\n+\tstrd\tr3, r3, [sp, #176]\t@ 0xb0\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tmovw\tr3, #769\t@ 0x301\n+\tstrh.w\tr3, [sp, #168]\t@ 0xa8\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tldr\tr2, [sp, #112]\t@ 0x70\n \tmov\tr4, r0\n-\tldr\tr1, [sp, #104]\t@ 0x68\n+\tldr\tr1, [sp, #100]\t@ 0x64\n \tstr.w\tsl, [sp, #144]\t@ 0x90\n \tbl\t0 <__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp>\n R_ARM_THM_CALL\t__gridxc_fft_gpfa_MOD_fft_gpfa_ez_dp\n-\tldr\tr2, [sp, #152]\t@ 0x98\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tcmp\tr2, r4\n-\tbeq.n\t5c0 <__gridxc_radfft_MOD_radfft+0x548>\n-\tldr\tr0, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tcmp\tr3, r4\n+\tbeq.n\t630 <__gridxc_radfft_MOD_radfft+0x5b8>\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n \tmov\tr1, r4\n-\tstr\tr3, [sp, #40]\t@ 0x28\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tcmp\tr2, #0\n-\tble.n\t622 <__gridxc_radfft_MOD_radfft+0x5aa>\n-\tldr\tr0, [r3, #96]\t@ 0x60\n-\tldr\tr5, [r3, #64]\t@ 0x40\n-\tldr\tr2, [r3, #84]\t@ 0x54\n-\tldr.w\tr4, [r3, #132]\t@ 0x84\n-\tadd\tr5, r0\n-\tldr\tr7, [r3, #112]\t@ 0x70\n-\tadd\tr5, r2\n-\tldr\tr1, [r3, #108]\t@ 0x6c\n-\tldr.w\tr2, [r3, #128]\t@ 0x80\n-\tadd\tr7, r4\n-\tldr\tr6, [r3, #80]\t@ 0x50\n-\tmul.w\tr4, r2, r4\n-\tmla\tr2, r2, r7, r1\n-\tldr\tr1, [r3, #60]\t@ 0x3c\n-\tmul.w\tr0, r6, r0\n-\tmla\tr1, r6, r5, r1\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n-\tadds\tr6, r5, #1\n-\tmovs\tr5, #1\n-\tvmov\ts15, r5\n-\tvldr\td18, [r1]\n-\tvldr\td17, [r2]\n-\tadds\tr5, #1\n-\tvcvt.f64.s32\td16, s15\n-\tadd\tr1, r0\n-\tcmp\tr5, r6\n-\tvadd.f64\td17, d17, d18\n-\tvmul.f64\td16, d16, d10\n-\tvdiv.f64\td18, d17, d16\n-\tvstr\td18, [r2]\n-\tadd\tr2, r4\n-\tbne.n\t5f8 <__gridxc_radfft_MOD_radfft+0x580>\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tcmp\tr3, #0\n+\tble.n\t698 <__gridxc_radfft_MOD_radfft+0x620>\n+\tldr\tr7, [pc, #824]\t@ (970 <__gridxc_radfft_MOD_radfft+0x8f8>)\n+\tadds\tr5, r3, #1\n+\tmovs\tr2, #1\n+\tadd\tr7, pc\n+\tldr\tr1, [r7, #96]\t@ 0x60\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldr.w\tr0, [r7, #132]\t@ 0x84\n+\tldr\tr4, [r7, #112]\t@ 0x70\n+\tadd\tr3, r1\n+\tldr\tr6, [r7, #84]\t@ 0x54\n+\tadd.w\tip, r0, r4\n+\tldr\tr4, [r7, #108]\t@ 0x6c\n+\tadd\tr6, r3\n+\tldr.w\tr3, [r7, #128]\t@ 0x80\n+\tldr.w\tlr, [r7, #80]\t@ 0x50\n+\tmul.w\tr0, r3, r0\n+\tmla\tr3, r3, ip, r4\n+\tldr\tr4, [r7, #60]\t@ 0x3c\n+\tmul.w\tr1, lr, r1\n+\tmla\tr4, lr, r6, r4\n+\tvmov\ts15, r2\n+\tvldr\td5, [r4]\n+\tvldr\td6, [r3]\n \tadds\tr2, #1\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tcmp\tr1, r2\n-\tbge.w\t426 <__gridxc_radfft_MOD_radfft+0x3ae>\n-\tldr\tr3, [pc, #188]\t@ (6f0 <__gridxc_radfft_MOD_radfft+0x678>)\n-\tvmov.i64\td17, #0x0000000000000000\n+\tvcvt.f64.s32\td7, s15\n+\tadd\tr4, r1\n+\tcmp\tr2, r5\n+\tvadd.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d10\n+\tvdiv.f64\td5, d6, d7\n+\tvstr\td5, [r3]\n+\tadd\tr3, r0\n+\tbne.n\t66e <__gridxc_radfft_MOD_radfft+0x5f6>\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadds\tr3, #1\n+\tstr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tr2, r3\n+\tbge.w\t40c <__gridxc_radfft_MOD_radfft+0x394>\n+\tldr\tr3, [pc, #716]\t@ (974 <__gridxc_radfft_MOD_radfft+0x8fc>)\n+\tvldr\td6, [pc, #692]\t@ 960 <__gridxc_radfft_MOD_radfft+0x8e8>\n \tadd\tr3, pc\n \tldr\tr1, [r3, #112]\t@ 0x70\n \tldr.w\tr5, [r3, #128]\t@ 0x80\n \tldr\tr2, [r3, #108]\t@ 0x6c\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \tmul.w\tr6, r5, r1\n \tadds\tr7, r2, r6\n-\tvstr\td17, [r7]\n+\tvstr\td6, [r7]\n \tcmp\tr3, #0\n-\tbne.w\t7ec <__gridxc_radfft_MOD_radfft+0x774>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tbne.n\t75e <__gridxc_radfft_MOD_radfft+0x6e6>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tble.w\t8d8 <__gridxc_radfft_MOD_radfft+0x860>\n+\tble.w\t846 <__gridxc_radfft_MOD_radfft+0x7ce>\n \tldr\tr1, [sp, #72]\t@ 0x48\n \tadds\tr3, #1\n \tmov\tr0, r3\n \tmovs\tr3, #1\n \tadds\tr1, #8\n \tvmov\ts15, r3\n-\tvldmia\tr1!, {d18}\n+\tvldmia\tr1!, {d5}\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td16, s15\n+\tvcvt.f64.s32\td7, s15\n \tcmp\tr3, r0\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td16, d16, d16\n-\tvfma.f64\td17, d16, d18\n-\tbne.n\t664 <__gridxc_radfft_MOD_radfft+0x5ec>\n+\tvmul.f64\td7, d7, d8\n+\tvmul.f64\td7, d7, d7\n+\tvmla.f64\td6, d7, d5\n+\tbne.n\t6d8 <__gridxc_radfft_MOD_radfft+0x660>\n \tvadd.f64\td9, d9, d9\n-\tvmul.f64\td17, d9, d17\n-\tvstr\td17, [r7]\n-\tldr\tr4, [pc, #100]\t@ (6f4 <__gridxc_radfft_MOD_radfft+0x67c>)\n+\tvmul.f64\td6, d9, d6\n+\tvstr\td6, [r7]\n+\tldr\tr4, [pc, #628]\t@ (978 <__gridxc_radfft_MOD_radfft+0x900>)\n \tadd\tr2, r6\n-\tldr\tr1, [sp, #132]\t@ 0x84\n+\tldr\tr1, [sp, #140]\t@ 0x8c\n \tmovs\tr3, #0\n \tadd\tr4, pc\n \tldr.w\tr4, [r4, #132]\t@ 0x84\n \tmul.w\tr5, r4, r5\n \tmov\tr6, r5\n \tldrd\tr4, r5, [r2]\n \tadds\tr3, #1\n \tadd\tr2, r6\n \tcmp\tr3, r0\n \tstrd\tr4, r5, [r1], #8\n-\tbne.n\t6a2 <__gridxc_radfft_MOD_radfft+0x62a>\n-\tldr\tr2, [pc, #68]\t@ (6f8 <__gridxc_radfft_MOD_radfft+0x680>)\n-\tldr\tr3, [pc, #68]\t@ (6fc <__gridxc_radfft_MOD_radfft+0x684>)\n+\tbne.n\t716 <__gridxc_radfft_MOD_radfft+0x69e>\n+\tldr\tr2, [pc, #596]\t@ (97c <__gridxc_radfft_MOD_radfft+0x904>)\n+\tldr\tr3, [pc, #596]\t@ (980 <__gridxc_radfft_MOD_radfft+0x908>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #188]\t@ 0xbc\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t9bc <__gridxc_radfft_MOD_radfft+0x944>\n+\tbne.w\t958 <__gridxc_radfft_MOD_radfft+0x8e0>\n \tadd\tsp, #196\t@ 0xc4\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tnop\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000328\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002f0\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000002f0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002e0\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000b6\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000003e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\tmul.w\tr1, r2, ip\n-\tadd.w\tr5, lr, r2\n-\tstr\tr1, [sp, #52]\t@ 0x34\n-\tadd.w\tr9, fp, r5\n-\tldr\tr1, [sp, #76]\t@ 0x4c\n-\tmovs\tr4, #1\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tadd\tr5, r1\n-\tmul.w\tr9, ip, r9\n-\tstrd\tr2, r8, [sp, #92]\t@ 0x5c\n-\tstrd\tlr, ip, [sp, #84]\t@ 0x54\n-\tmul.w\tr5, ip, r5\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tsub.w\tr1, r5, r9\n-\tadd\tr9, r0\n-\tldr\tr0, [sp, #72]\t@ 0x48\n-\tmov\tr8, r9\n-\tadd.w\tr5, r0, #8\n-\tmov\tr9, r5\n-\tmov\tr5, r6\n-\tmov\tr6, r7\n-\tmov\tr7, r1\n-\tvmov\ts15, r4\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tvldmia\tr9!, {d11}\n-\tadds\tr4, #1\n-\tvcvt.f64.s32\td0, s15\n-\tvmul.f64\td0, d0, d8\n-\tbl\t0 <__powidf2>\n- R_ARM_THM_CALL\t__powidf2\n-\tvmul.f64\td0, d9, d0\n-\tvldr\td16, [r5]\n-\tadd.w\tr0, r7, r8\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tvmul.f64\td0, d0, d11\n-\tvmul.f64\td16, d16, d0\n-\tvstr\td16, [r8]\n-\tadd\tr8, r3\n-\tvldr\td16, [r6]\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvmul.f64\td16, d16, d0\n-\tcmp\tr4, r3\n-\tvstr\td16, [r0]\n-\tblt.n\t73e <__gridxc_radfft_MOD_radfft+0x6c6>\n-\tmov\tr7, r6\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tldrd\tlr, ip, [sp, #84]\t@ 0x54\n-\tmov\tr6, r5\n-\tldrd\tr8, r3, [sp, #96]\t@ 0x60\n-\tcmp\tsl, r4\n-\tbgt.w\t4aa <__gridxc_radfft_MOD_radfft+0x432>\n-\tb.n\t562 <__gridxc_radfft_MOD_radfft+0x4ea>\n-\tvldr\td16, [r9]\n-\tadd.w\tsl, r1, r3\n-\tadd.w\tr8, r8, #1\n-\tadd\tr9, r6\n-\tadd\tr3, r6\n-\tcmp\tr2, r8\n-\tvmul.f64\td16, d18, d16\n-\tvstr\td16, [r0]\n-\tvldr\td19, [sl]\n-\tvsub.f64\td16, d16, d19\n-\tvstr\td16, [r0]\n-\tbge.w\t26e <__gridxc_radfft_MOD_radfft+0x1f6>\n-\tb.n\t29e <__gridxc_radfft_MOD_radfft+0x226>\n-\tvldr\td16, [r0]\n-\tvmul.f64\td16, d18, d16\n-\tvstr\td16, [r8]\n-\tb.n\t368 <__gridxc_radfft_MOD_radfft+0x2f0>\n-\tldr\tr3, [pc, #496]\t@ (9c8 <__gridxc_radfft_MOD_radfft+0x950>)\n+\tldr\tr3, [pc, #572]\t@ (984 <__gridxc_radfft_MOD_radfft+0x90c>)\n \tmovs\tr6, #0\n \tmovs\tr7, #0\n \tadd\tr3, pc\n \tldrd\tr2, r1, [r3, #108]\t@ 0x6c\n \tldr.w\tr5, [r3, #128]\t@ 0x80\n \tmla\tr3, r1, r5, r2\n \tstrd\tr6, r7, [r3]\n \tvldr\ts15, [sp, #60]\t@ 0x3c\n-\tvldr\td0, [pc, #460]\t@ 9c0 <__gridxc_radfft_MOD_radfft+0x948>\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tvcvt.f64.s32\td16, s15\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tvdiv.f64\td0, d0, d16\n+\tvldr\td0, [pc, #516]\t@ 968 <__gridxc_radfft_MOD_radfft+0x8f0>\n+\tstr\tr1, [sp, #52]\t@ 0x34\n+\tvcvt.f64.s32\td7, s15\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tvdiv.f64\td0, d0, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tvmul.f64\td0, d16, d0\n+\tvmul.f64\td0, d14, d0\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n+\tldr\tr1, [sp, #52]\t@ 0x34\n \tvcvt.s32.f64\ts15, d0\n \tvmov\tr4, s15\n \tcmp\tr4, #0\n-\tble.n\t8d8 <__gridxc_radfft_MOD_radfft+0x860>\n-\tldr\tr3, [pc, #428]\t@ (9cc <__gridxc_radfft_MOD_radfft+0x954>)\n+\tble.n\t846 <__gridxc_radfft_MOD_radfft+0x7ce>\n+\tldr\tr3, [pc, #508]\t@ (988 <__gridxc_radfft_MOD_radfft+0x910>)\n \tmov.w\tfp, #1\n-\tldr\tr7, [pc, #428]\t@ (9d0 <__gridxc_radfft_MOD_radfft+0x958>)\n+\tldr\tr7, [pc, #504]\t@ (98c <__gridxc_radfft_MOD_radfft+0x914>)\n \tvadd.f64\td9, d9, d9\n \tadd\tr3, pc\n-\tvmov.i64\td12, #0x0000000000000000\n-\tldr.w\tr9, [sp, #44]\t@ 0x2c\n-\tadd\tr7, pc\n+\tldr.w\tr9, [sp, #48]\t@ 0x30\n \tldr.w\tsl, [sp, #124]\t@ 0x7c\n+\tadd\tr7, pc\n+\tvldr\td12, [pc, #444]\t@ 960 <__gridxc_radfft_MOD_radfft+0x8e8>\n \tadd.w\tr8, sp, #144\t@ 0x90\n \tldr.w\tip, [r3, #132]\t@ 0x84\n \tmov\tr4, fp\n-\tvstr\ts15, [sp, #40]\t@ 0x28\n+\tvstr\ts15, [sp, #44]\t@ 0x2c\n \tmul.w\tr0, ip, r4\n \tvmov\ts15, r4\n \tcmp.w\tr9, #0\n \tadd.w\tr3, r0, r1\n \tvcvt.f64.s32\td11, s15\n \tmla\tr3, r5, r3, r2\n \tvmul.f64\td11, d11, d10\n \tvstr\td12, [r3]\n-\tble.n\t8ea <__gridxc_radfft_MOD_radfft+0x872>\n+\tble.n\t884 <__gridxc_radfft_MOD_radfft+0x80c>\n \tldr\tr3, [sp, #72]\t@ 0x48\n \tmovs\tr6, #1\n \tadd.w\tfp, r3, #8\n \tvmov\ts15, r6\n \tadd\tr0, r1\n \tmov\tr1, r8\n \tvldmia\tfp!, {d15}\n \tvcvt.f64.s32\td13, s15\n \tadds\tr6, #1\n \tmla\tr2, r5, r0, r2\n \tmov\tr0, sl\n \tvmul.f64\td13, d13, d8\n-\tvmul.f64\td16, d11, d13\n+\tvmul.f64\td7, d11, d13\n \tvmul.f64\td13, d13, d13\n-\tvstr\td16, [sp, #144]\t@ 0x90\n+\tvstr\td7, [sp, #144]\t@ 0x90\n \tvldr\td14, [r2]\n \tbl\t0 <__gridxc_bessph_MOD_bessph>\n R_ARM_THM_CALL\t__gridxc_bessph_MOD_bessph\n \tldr.w\tip, [r7, #132]\t@ 0x84\n \tvmul.f64\td13, d13, d0\n \tldrd\tr2, r1, [r7, #108]\t@ 0x6c\n \tcmp\tr9, r6\n \tldr.w\tr5, [r7, #128]\t@ 0x80\n \tmul.w\tr0, ip, r4\n-\tvfma.f64\td14, d15, d13\n+\tvmla.f64\td14, d13, d15\n \tadd.w\tr3, r0, r1\n \tmla\tr3, r5, r3, r2\n \tvstr\td14, [r3]\n-\tbge.n\t870 <__gridxc_radfft_MOD_radfft+0x7f8>\n-\tvmul.f64\td16, d9, d14\n-\tvstr\td16, [r3]\n+\tbge.n\t7de <__gridxc_radfft_MOD_radfft+0x766>\n+\tvmul.f64\td14, d9, d14\n+\tvstr\td14, [r3]\n \tadds\tr4, #1\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tcmp\tr3, r4\n-\tbge.n\t846 <__gridxc_radfft_MOD_radfft+0x7ce>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n+\tcmp\tr3, r4\n+\tbge.n\t7b4 <__gridxc_radfft_MOD_radfft+0x73c>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tblt.w\t6b2 <__gridxc_radfft_MOD_radfft+0x63a>\n+\tblt.w\t726 <__gridxc_radfft_MOD_radfft+0x6ae>\n \tadds\tr3, #1\n \tmul.w\tr6, r1, r5\n \tmov\tr0, r3\n-\tb.n\t68e <__gridxc_radfft_MOD_radfft+0x616>\n-\tvmov.f64\td16, d12\n-\tb.n\t8cc <__gridxc_radfft_MOD_radfft+0x854>\n-\tvmov\tr3, s15\n-\tcmp\tr3, #0\n-\tbge.w\t3ac <__gridxc_radfft_MOD_radfft+0x334>\n-\tb.n\t3d4 <__gridxc_radfft_MOD_radfft+0x35c>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tb.n\t702 <__gridxc_radfft_MOD_radfft+0x68a>\n+\tvldr\td7, [r9]\n+\tadd.w\tsl, r1, r3\n+\tadd.w\tr8, r8, #1\n+\tadd\tr9, r6\n+\tadd\tr3, r6\n+\tcmp\tr2, r8\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [r0]\n+\tvldr\td4, [sl]\n+\tvsub.f64\td7, d7, d4\n+\tvstr\td7, [r0]\n+\tbge.w\t26c <__gridxc_radfft_MOD_radfft+0x1f4>\n+\tb.n\t29c <__gridxc_radfft_MOD_radfft+0x224>\n+\tvmov.f64\td14, d12\n+\tb.n\t83a <__gridxc_radfft_MOD_radfft+0x7c2>\n+\tvldr\td7, [r0]\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [r8]\n+\tb.n\t364 <__gridxc_radfft_MOD_radfft+0x2ec>\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tbge.w\t3ac <__gridxc_radfft_MOD_radfft+0x334>\n-\tb.n\t3dc <__gridxc_radfft_MOD_radfft+0x364>\n-\tldr\tr3, [pc, #204]\t@ (9d4 <__gridxc_radfft_MOD_radfft+0x95c>)\n+\tbge.w\t3b2 <__gridxc_radfft_MOD_radfft+0x33a>\n+\tb.n\t3da <__gridxc_radfft_MOD_radfft+0x362>\n+\tldr\tr3, [pc, #236]\t@ (990 <__gridxc_radfft_MOD_radfft+0x918>)\n \tmov\tr4, r2\n-\tldr\tr7, [pc, #204]\t@ (9d8 <__gridxc_radfft_MOD_radfft+0x960>)\n+\tldr\tr7, [pc, #236]\t@ (994 <__gridxc_radfft_MOD_radfft+0x91c>)\n \tmovs\tr6, #0\n-\tldr.w\tfp, [pc, #204]\t@ 9dc <__gridxc_radfft_MOD_radfft+0x964>\n+\tldr.w\tfp, [pc, #236]\t@ 998 <__gridxc_radfft_MOD_radfft+0x920>\n \tadd\tr3, pc\n-\tldr\tr2, [pc, #200]\t@ (9e0 <__gridxc_radfft_MOD_radfft+0x968>)\n+\tldr\tr2, [pc, #232]\t@ (99c <__gridxc_radfft_MOD_radfft+0x924>)\n \tadd\tr7, pc\n \tadd.w\tr1, r3, #8\n \tadd\tfp, pc\n \tadd\tr2, pc\n \tmov.w\tr9, #6\n \tadd.w\tr0, r7, #60\t@ 0x3c\n \tstr\tr2, [sp, #4]\n \tstr.w\tfp, [sp, #8]\n \tmovs\tr2, #2\n \tstrd\tr6, r6, [sp, #12]\n \tmov\tsl, r3\n \tstrd\tr2, r9, [sp, #20]\n \tadd\tr2, sp, #144\t@ 0x90\n-\tstr\tr2, [sp, #104]\t@ 0x68\n+\tstr\tr2, [sp, #100]\t@ 0x64\n \tmov.w\tr8, r4, lsl #1\n \tstr\tr2, [sp, #0]\n \tadds\tr2, r3, #4\n \tstr.w\tr8, [sp, #144]\t@ 0x90\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d2>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d2\n \tmovs\tr3, #2\n \tstr\tr3, [sp, #12]\n-\tldr\tr3, [pc, #144]\t@ (9e4 <__gridxc_radfft_MOD_radfft+0x96c>)\n+\tldr\tr3, [pc, #176]\t@ (9a0 <__gridxc_radfft_MOD_radfft+0x928>)\n \tmov\tr1, sl\n-\tldr\tr2, [sp, #104]\t@ 0x68\n+\tldr\tr2, [sp, #100]\t@ 0x64\n \tadd.w\tr0, r7, #108\t@ 0x6c\n \tadd\tr3, pc\n \tstr.w\tr9, [sp, #16]\n \tstr.w\tfp, [sp]\n \tstrd\tr6, r6, [sp, #4]\n \tstr.w\tr8, [sp, #144]\t@ 0x90\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d1>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d1\n-\tldr\tr3, [pc, #116]\t@ (9e8 <__gridxc_radfft_MOD_radfft+0x970>)\n+\tldr\tr3, [pc, #148]\t@ (9a4 <__gridxc_radfft_MOD_radfft+0x92c>)\n \tadd\tr3, pc\n \tstr\tr4, [r3, #4]\n-\tb.w\tfc <__gridxc_radfft_MOD_radfft+0x84>\n+\tb.w\t102 <__gridxc_radfft_MOD_radfft+0x8a>\n \tldr\tr3, [sp, #124]\t@ 0x7c\n-\tmovs\tr4, #6\n-\tldr\tr2, [pc, #104]\t@ (9ec <__gridxc_radfft_MOD_radfft+0x974>)\n+\tmovs\tr1, #6\n+\tldr\tr2, [pc, #136]\t@ (9a8 <__gridxc_radfft_MOD_radfft+0x930>)\n \tstr\tr3, [sp, #8]\n \tstr\tr3, [sp, #0]\n \tadd\tr2, pc\n-\tldr\tr3, [pc, #100]\t@ (9f0 <__gridxc_radfft_MOD_radfft+0x978>)\n+\tldr\tr3, [pc, #132]\t@ (9ac <__gridxc_radfft_MOD_radfft+0x934>)\n \tstr\tr2, [sp, #16]\n-\tldr\tr0, [pc, #100]\t@ (9f4 <__gridxc_radfft_MOD_radfft+0x97c>)\n+\tldr\tr0, [pc, #132]\t@ (9b0 <__gridxc_radfft_MOD_radfft+0x938>)\n \tadd\tr3, pc\n-\tldr\tr2, [pc, #100]\t@ (9f8 <__gridxc_radfft_MOD_radfft+0x980>)\n-\tadd.w\tr1, r3, #8\n+\tldr\tr2, [pc, #132]\t@ (9b4 <__gridxc_radfft_MOD_radfft+0x93c>)\n \tstr\tr3, [sp, #4]\n \tadd\tr0, pc\n \tadd\tr2, pc\n \tstr\tr2, [sp, #12]\n \tmovs\tr2, #0\n \tstrd\tr2, r2, [sp, #20]\n \tmovs\tr2, #1\n-\tstrd\tr2, r4, [sp, #28]\n+\tstrd\tr2, r1, [sp, #28]\n \tadds\tr2, r3, #4\n+\tadd.w\tr1, r3, #8\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr3, [pc, #72]\t@ (9fc <__gridxc_radfft_MOD_radfft+0x984>)\n+\tldr\tr3, [pc, #104]\t@ (9b8 <__gridxc_radfft_MOD_radfft+0x940>)\n \tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd\tr3, pc\n \tstr\tr2, [r3, #0]\n-\tb.w\te0 <__gridxc_radfft_MOD_radfft+0x68>\n+\tb.w\te6 <__gridxc_radfft_MOD_radfft+0x6e>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop.w\n+\t...\n \t.word\t0xbbb55516\n \t.word\t0xc0326bb1\n-\t.word\t0x000001ea\n+\t.word\t0x00000330\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002c4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000026a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000024e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000234\n R_ARM_REL32\t.bss\n-\t.word\t0x000001a0\n+\t.word\t0x000001ee\n R_ARM_REL32\t.bss\n-\t.word\t0x0000019a\n+\t.word\t0x000001e8\n R_ARM_REL32\t.bss\n-\t.word\t0x000000be\n+\t.word\t0x000000de\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000be\n+\t.word\t0x000000de\n R_ARM_REL32\t.bss\n-\t.word\t0x000000bc\n+\t.word\t0x000000dc\n R_ARM_REL32\t.LC0\n-\t.word\t0x000000be\n+\t.word\t0x000000de\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000084\n+\t.word\t0x000000a4\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000070\n+\t.word\t0x00000090\n R_ARM_REL32\t.data\n-\t.word\t0x00000062\n+\t.word\t0x00000082\n R_ARM_REL32\t.LC0\n-\t.word\t0x0000005e\n+\t.word\t0x0000007e\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000058\n+\t.word\t0x0000007c\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n+\t.word\t0x0000007e\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000044\n+\t.word\t0x00000064\n R_ARM_REL32\t.data\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "sorting.F90.o", "source2": "sorting.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 2996 (bytes into file)\n+ Start of section headers: 2844 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0xbb4:\n+There are 11 section headers, starting at offset 0xb1c:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000790 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 000aac 0000b0 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 0007c8 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 0007c8 000000 00 WA 0 0 1\n- [ 5] .rodata PROGBITS 00000000 0007c8 000004 00 A 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 0007cc 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0007cc 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 000800 000170 10 9 15 4\n- [ 9] .strtab STRTAB 00000000 000970 00013a 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 000b5c 000058 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0006fc 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 000a14 0000b0 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 000734 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 000734 000000 00 WA 0 0 1\n+ [ 5] .rodata PROGBITS 00000000 000734 000004 00 A 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 000738 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 000738 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 000768 000170 10 9 15 4\n+ [ 9] .strtab STRTAB 00000000 0008d8 00013a 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 000ac4 000058 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -6,21 +6,21 @@\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 3: 00000258 0 NOTYPE LOCAL DEFAULT 1 $d\n 4: 00000161 260 FUNC LOCAL DEFAULT 1 __gridxc_sorting_MOD_iorder.localalias\n 5: 00000264 0 NOTYPE LOCAL DEFAULT 1 $t\n 6: 00000358 0 NOTYPE LOCAL DEFAULT 1 $d\n 7: 00000265 256 FUNC LOCAL DEFAULT 1 __gridxc_sorting_MOD_order.localalias\n 8: 00000364 0 NOTYPE LOCAL DEFAULT 1 $t\n- 9: 00000538 0 NOTYPE LOCAL DEFAULT 1 $d\n- 10: 00000365 520 FUNC LOCAL DEFAULT 1 __gridxc_sorting_MOD_ordix.localalias\n- 11: 0000056c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 00000770 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 00000510 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 10: 00000365 464 FUNC LOCAL DEFAULT 1 __gridxc_sorting_MOD_ordix.localalias\n+ 11: 00000534 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 000006ec 0 NOTYPE LOCAL DEFAULT 1 $d\n 13: 00000000 0 SECTION LOCAL DEFAULT 5 .rodata\n 14: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 15: 00000161 260 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_iorder\n 16: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n 17: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n 18: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 19: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 20: 00000265 256 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_order\n- 21: 00000365 520 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_ordix\n- 22: 0000056d 548 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_ordvec\n+ 21: 00000365 464 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_ordix\n+ 22: 00000535 456 FUNC GLOBAL DEFAULT 1 __gridxc_sorting_MOD_ordvec\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,25 +1,25 @@\n \n-Relocation section '.rel.text' at offset 0xaac contains 22 entries:\n+Relocation section '.rel.text' at offset 0xa14 contains 22 entries:\n Offset Info Type Sym. Value Symbol's Name\n 00000212 0000100a R_ARM_THM_CALL 00000000 memcpy\n 0000022c 0000100a R_ARM_THM_CALL 00000000 memcpy\n 00000254 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n 00000258 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 0000025c 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000260 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000310 0000100a R_ARM_THM_CALL 00000000 memcpy\n 0000032a 0000100a R_ARM_THM_CALL 00000000 memcpy\n 00000352 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n 00000358 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 0000035c 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n 00000360 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000043e 0000100a R_ARM_THM_CALL 00000000 memcpy\n-00000530 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000560 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000564 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000568 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000768 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000780 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000784 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000788 00000d03 R_ARM_REL32 00000000 .rodata\n-0000078c 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000003f4 0000100a R_ARM_THM_CALL 00000000 memcpy\n+0000050a 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000528 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000052c 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000530 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000006e8 0000110a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000006ec 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000006f0 0000131a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000006f4 00000d03 R_ARM_REL32 00000000 .rodata\n+000006f8 00001219 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -12,28 +12,28 @@\n \tbgt.n\t64 \n \tldr.w\tr1, [ip, #20]\n \tadd.w\tlr, r0, #4294967295\t@ 0xffffffff\n \tldrd\tr5, r8, [ip, #12]\n \tldr.w\tr7, [r1, lr, lsl #2]\n \tldr.w\tr6, [ip, #8]\n \tcmp.w\tr8, #1\n-\tvldr\td17, [ip]\n+\tvldr\td6, [ip]\n \tmla\tr2, r7, r8, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td19, [r2, #8]\n+\tvldr\td4, [r2, #8]\n \tbne.n\t8a \n \tmov.w\tr8, r3, lsl #2\n \tadd.w\tip, r3, #4294967295\t@ 0xffffffff\n \tadd.w\tr2, r1, r8\n \tldr.w\tr2, [r2, #-4]\n \tadd\tr2, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td16, [r2, #8]\n-\tvsub.f64\td18, d16, d17\n-\tvcmpe.f64\td18, d19\n+\tvldr\td7, [r2, #8]\n+\tvsub.f64\td5, d7, d6\n+\tvcmpe.f64\td5, d4\n \tvmrs\tAPSR_nzcv, fpscr\n \tbgt.n\tdc \n \tcmp\tr4, r3\n \tbgt.n\t11c \n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tcmp\tr4, r3\n \tbgt.n\t13e \n@@ -50,40 +50,40 @@\n \tadd.w\tlr, r2, #4294967295\t@ 0xffffffff\n \tmov.w\tr9, r3, lsl #2\n \tadd.w\tip, r3, #4294967295\t@ 0xffffffff\n \tadd.w\tr2, r1, r9\n \tldr.w\tr2, [r2, #-4]\n \tmla\tr2, r2, r8, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td16, [r2, #8]\n-\tvsub.f64\td18, d16, d17\n-\tvcmpe.f64\td18, d19\n+\tvldr\td7, [r2, #8]\n+\tvsub.f64\td5, d7, d6\n+\tvcmpe.f64\td5, d4\n \tvmrs\tAPSR_nzcv, fpscr\n \tbgt.n\t68 \n \tcmp\tr4, r3\n \tble.n\t64 \n \tldr.w\tr2, [r1, r9]\n \tmla\tr2, r2, r8, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td16, [r2, #8]\n-\tvsub.f64\td16, d16, d17\n-\tvcmpe.f64\td19, d16\n+\tvldr\td7, [r2, #8]\n+\tvsub.f64\td7, d7, d6\n+\tvcmpe.f64\td4, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\t64 \n \tadds\tr2, r3, #1\n \tmov\tip, r3\n \tb.n\t6e \n \tcmp\tr4, r3\n \tble.n\tfc \n \tldr.w\tr2, [r1, r8]\n \tadd\tr2, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td18, [r2, #8]\n-\tvsub.f64\td18, d18, d17\n-\tvcmpe.f64\td18, d16\n+\tvldr\td5, [r2, #8]\n+\tvsub.f64\td5, d5, d6\n+\tvcmpe.f64\td5, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbgt.n\t138 \n \tmov\tr2, r3\n \tcmp\tr2, r0\n \tbeq.n\t64 \n \tldr.w\tr0, [r1, ip, lsl #2]\n \tlsls\tr3, r2, #1\n@@ -93,28 +93,28 @@\n \tbgt.n\t64 \n \tmov\tr0, r2\n \tadd.w\tlr, r2, #4294967295\t@ 0xffffffff\n \tb.n\t38 \n \tldr.w\tr2, [r1, r8]\n \tadd\tr2, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td16, [r2, #8]\n-\tvsub.f64\td16, d16, d17\n-\tvcmpe.f64\td19, d16\n+\tvldr\td7, [r2, #8]\n+\tvsub.f64\td7, d7, d6\n+\tvcmpe.f64\td4, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\t64 \n \tadds\tr2, r3, #1\n \tmov\tip, r3\n \tb.n\tfe \n \tldr.w\tr2, [r1, r9]\n \tmla\tr2, r2, r8, r5\n \tadd.w\tr2, r6, r2, lsl #3\n-\tvldr\td18, [r2, #8]\n-\tvsub.f64\td18, d18, d17\n-\tvcmpe.f64\td16, d18\n+\tvldr\td5, [r2, #8]\n+\tvsub.f64\td5, d5, d6\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\t6c \n \tb.n\td6 \n \tnop\n \n 00000160 <__gridxc_sorting_MOD_iorder>:\n __gridxc_sorting_MOD_iorder.localalias():\n@@ -332,210 +332,191 @@\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4024]\t@ 0xfb8\n \tsub\tsp, #44\t@ 0x2c\n \tadd\tr7, sp, #0\n \tldr.w\tr8, [r2]\n-\tldr\tr2, [pc, #480]\t@ (560 <__gridxc_sorting_MOD_ordix+0x1fc>)\n+\tldr\tr2, [pc, #424]\t@ (528 <__gridxc_sorting_MOD_ordix+0x1c4>)\n \tldr\tr1, [r1, #0]\n \tsubs.w\tr4, r8, #1\n \tstr\tr0, [r7, #8]\n-\tldr\tr0, [pc, #476]\t@ (564 <__gridxc_sorting_MOD_ordix+0x200>)\n+\tldr\tr0, [pc, #420]\t@ (52c <__gridxc_sorting_MOD_ordix+0x1c8>)\n \tstr\tr3, [r7, #20]\n \tadd\tr0, pc\n \tldr\tr2, [r0, r2]\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [r7, #36]\t@ 0x24\n \tmov.w\tr2, #0\n \tbic.w\tr2, r1, r1, asr #31\n \tstr\tr2, [r7, #16]\n \tmvn.w\tr2, r2\n \tstr\tr2, [r7, #12]\n-\tbmi.w\t4d4 <__gridxc_sorting_MOD_ordix+0x170>\n+\tbmi.n\t4a0 <__gridxc_sorting_MOD_ordix+0x13c>\n \tmov.w\tr6, r8, lsl #2\n \tmov\tr0, sp\n \tadds\tr2, r6, #7\n-\tmov\tr5, sp\n+\tmov\tr9, sp\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #7\n \tbic.w\tr1, r1, #15\n \tsub.w\tr1, sp, r1\n \tcmp\tr0, r1\n-\tbeq.n\t3d2 <__gridxc_sorting_MOD_ordix+0x6e>\n+\tbeq.n\t3d0 <__gridxc_sorting_MOD_ordix+0x6c>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t3c4 <__gridxc_sorting_MOD_ordix+0x60>\n+\tbne.n\t3c2 <__gridxc_sorting_MOD_ordix+0x5e>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 3e2 <__gridxc_sorting_MOD_ordix+0x7e>\n+\tcbz\tr2, 3e0 <__gridxc_sorting_MOD_ordix+0x7c>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tmov\tr1, sp\n-\tcmp.w\tr8, #3\n-\tble.w\t52a <__gridxc_sorting_MOD_ordix+0x1c6>\n-\tmov.w\tr0, r8, lsr #2\n-\tmov\tr2, r1\n-\tvldr\td16, [pc, #324]\t@ 538 <__gridxc_sorting_MOD_ordix+0x1d4>\n-\tvldr\td17, [pc, #328]\t@ 540 <__gridxc_sorting_MOD_ordix+0x1dc>\n-\tadd.w\tr0, r1, r0, lsl #4\n-\tvmov.i32\tq10, #4\t@ 0x00000004\n-\tvorr\tq9, q8, q8\n-\tvadd.i32\tq8, q8, q10\n-\tvst1.32\t{d18-d19}, [r2]!\n-\tcmp\tr2, r0\n-\tbne.n\t402 <__gridxc_sorting_MOD_ordix+0x9e>\n-\tbic.w\tr2, r8, #3\n-\tadds\tr0, r2, #1\n+\tmovs\tr2, #1\n+\tsubs\tr5, r1, #4\n+\tstr.w\tr2, [r5, #4]!\n+\tadds\tr2, #1\n \tcmp\tr8, r2\n-\tbeq.n\t43a <__gridxc_sorting_MOD_ordix+0xd6>\n-\tadd.w\tip, r0, #1\n-\tstr.w\tr0, [r1, r2, lsl #2]\n-\tcmp\tip, r8\n-\tmov.w\tr2, r2, lsl #2\n-\tbgt.n\t43a <__gridxc_sorting_MOD_ordix+0xd6>\n-\tadd\tr2, r1\n-\tadds\tr0, #2\n-\tcmp\tr8, r0\n-\tstr.w\tip, [r2, #4]\n-\tblt.n\t43a <__gridxc_sorting_MOD_ordix+0xd6>\n-\tstr\tr0, [r2, #8]\n-\tmov\tr2, r6\n+\tbge.n\t3e6 <__gridxc_sorting_MOD_ordix+0x82>\n \tmov\tr0, r3\n+\tmov\tr2, r6\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tsp, r5\n-\tldrd\tr1, r2, [r7, #12]\n-\tldr\tr0, [r7, #8]\n-\tcmp\tr2, #1\n-\tbne.n\t4f0 <__gridxc_sorting_MOD_ordix+0x18c>\n-\tadds\tr3, r1, #2\n-\tadd.w\tip, r8, r1\n-\tadd.w\tr1, r0, #16\n-\tvldr\td16, [pc, #236]\t@ 548 <__gridxc_sorting_MOD_ordix+0x1e4>\n-\tadd.w\tr2, r0, r3, lsl #3\n-\tadd.w\tr5, r1, ip, lsl #3\n-\tvldmia\tr2!, {d17}\n-\tvmaxnm.f64\td16, d16, d17\n+\tmov\tsp, r9\n+\tldrd\tr2, r1, [r7, #12]\n+\tldr\tr3, [r7, #8]\n+\tcmp\tr1, #1\n+\tbne.n\t4bc <__gridxc_sorting_MOD_ordix+0x158>\n+\tadd.w\tr1, r8, r2\n+\tadd.w\tip, r2, #2\n+\tadd.w\tr0, r3, #16\n+\tvldr\td7, [pc, #252]\t@ 510 <__gridxc_sorting_MOD_ordix+0x1ac>\n+\tadd.w\tr2, r3, ip, lsl #3\n+\tadd.w\tr5, r0, r1, lsl #3\n+\tvldmia\tr2!, {d6}\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tcmp\tr2, r5\n-\tbne.n\t464 <__gridxc_sorting_MOD_ordix+0x100>\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tadd.w\tr2, r1, ip, lsl #3\n-\tvldr\td17, [pc, #212]\t@ 550 <__gridxc_sorting_MOD_ordix+0x1ec>\n-\tvldmia\tr3!, {d18}\n-\tvminnm.f64\td17, d17, d18\n-\tcmp\tr3, r2\n-\tbne.n\t47c <__gridxc_sorting_MOD_ordix+0x118>\n-\tvsub.f64\td16, d16, d17\n-\tvldr\td17, [pc, #200]\t@ 558 <__gridxc_sorting_MOD_ordix+0x1f4>\n+\tbne.n\t41c <__gridxc_sorting_MOD_ordix+0xb8>\n+\tadd.w\tr3, r3, ip, lsl #3\n+\tadd.w\tr2, r0, r1, lsl #3\n+\tvldr\td6, [pc, #220]\t@ 518 <__gridxc_sorting_MOD_ordix+0x1b4>\n+\tvldmia\tr3!, {d5}\n+\tvcmpe.f64\td6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td6, d5\n+\tcmp\tr2, r3\n+\tbne.n\t43e <__gridxc_sorting_MOD_ordix+0xda>\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [pc, #196]\t@ 520 <__gridxc_sorting_MOD_ordix+0x1bc>\n \tmov.w\tr5, r8, asr #1\n \tcmp.w\tr8, #1\n \tstr.w\tr8, [r7, #24]\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r7]\n-\tbeq.n\t4d4 <__gridxc_sorting_MOD_ordix+0x170>\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r7]\n+\tbeq.n\t4a0 <__gridxc_sorting_MOD_ordix+0x13c>\n \tmov\tr9, r7\n \tmov\tr0, r5\n \tmov\tip, r9\n \tbl\t0 \n \tsubs\tr5, #1\n-\tbne.n\t4a8 <__gridxc_sorting_MOD_ordix+0x144>\n+\tbne.n\t474 <__gridxc_sorting_MOD_ordix+0x110>\n \tldr\tr5, [r7, #20]\n \tstr\tr4, [r7, #24]\n \tadd\tr6, r5\n \tldr\tr3, [r5, #0]\n \tmov\tip, r9\n \tldr.w\tr2, [r6, #-4]!\n \tmovs\tr0, #1\n \tstr\tr2, [r5, #0]\n \tsubs\tr4, #1\n \tstr\tr3, [r6, #0]\n \tbl\t0 \n \tstr\tr4, [r7, #24]\n \tcmp\tr4, #0\n-\tbne.n\t4ba <__gridxc_sorting_MOD_ordix+0x156>\n-\tldr\tr2, [pc, #144]\t@ (568 <__gridxc_sorting_MOD_ordix+0x204>)\n-\tldr\tr3, [pc, #136]\t@ (560 <__gridxc_sorting_MOD_ordix+0x1fc>)\n+\tbne.n\t486 <__gridxc_sorting_MOD_ordix+0x122>\n+\tldr\tr2, [pc, #140]\t@ (530 <__gridxc_sorting_MOD_ordix+0x1cc>)\n+\tldr\tr3, [pc, #132]\t@ (528 <__gridxc_sorting_MOD_ordix+0x1c4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #36]\t@ 0x24\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t530 <__gridxc_sorting_MOD_ordix+0x1cc>\n+\tbne.n\t50a <__gridxc_sorting_MOD_ordix+0x1a6>\n \tadds\tr7, #44\t@ 0x2c\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n-\tadd\tr1, r2\n-\tvldr\td16, [pc, #84]\t@ 548 <__gridxc_sorting_MOD_ordix+0x1e4>\n-\tlsls\tr2, r2, #3\n+\tadd\tr2, r1\n+\tvldr\td7, [pc, #80]\t@ 510 <__gridxc_sorting_MOD_ordix+0x1ac>\n+\tlsls\tr1, r1, #3\n \tmovs\tr5, #0\n-\tadd.w\tr3, r0, r1, lsl #3\n-\tvldr\td17, [r3, #8]\n+\tadd.w\tr0, r3, r2, lsl #3\n+\tvldr\td6, [r0, #8]\n \tadds\tr5, #1\n-\tadd\tr3, r2\n+\tadd\tr0, r1\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n \tcmp\tr8, r5\n-\tvmaxnm.f64\td16, d16, d17\n-\tbne.n\t4fe <__gridxc_sorting_MOD_ordix+0x19a>\n-\tadd.w\tr3, r0, r1, lsl #3\n-\tvldr\td17, [pc, #60]\t@ 550 <__gridxc_sorting_MOD_ordix+0x1ec>\n-\tmovs\tr1, #0\n-\tvldr\td18, [r3, #8]\n-\tadds\tr1, #1\n-\tadd\tr3, r2\n-\tcmp\tr8, r1\n-\tvminnm.f64\td17, d17, d18\n-\tbne.n\t518 <__gridxc_sorting_MOD_ordix+0x1b4>\n-\tb.n\t488 <__gridxc_sorting_MOD_ordix+0x124>\n-\tmovs\tr0, #1\n+\tbne.n\t4ca <__gridxc_sorting_MOD_ordix+0x166>\n+\tadd.w\tr3, r3, r2, lsl #3\n+\tvldr\td6, [pc, #44]\t@ 518 <__gridxc_sorting_MOD_ordix+0x1b4>\n \tmovs\tr2, #0\n-\tb.n\t41c <__gridxc_sorting_MOD_ordix+0xb8>\n+\tvldr\td5, [r3, #8]\n+\tadds\tr2, #1\n+\tadd\tr3, r1\n+\tvcmpe.f64\td6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td6, d5\n+\tcmp\tr8, r2\n+\tbne.n\t4ee <__gridxc_sorting_MOD_ordix+0x18a>\n+\tb.n\t454 <__gridxc_sorting_MOD_ordix+0xf0>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n+\tnop\n \t.word\t0xffffffff\n \t.word\t0xffefffff\n \t.word\t0xffffffff\n \t.word\t0x7fefffff\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000001d6\n+\t.word\t0x0000019e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000008c\n+\t.word\t0x00000088\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-0000056c <__gridxc_sorting_MOD_ordvec>:\n+00000534 <__gridxc_sorting_MOD_ordvec>:\n __gridxc_sorting_MOD_ordvec():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3992]\t@ 0xf98\n \tsub\tsp, #68\t@ 0x44\n \tadd\tr7, sp, #0\n \tldr\tr5, [r2, #0]\n-\tldr\tr2, [pc, #508]\t@ (780 <__gridxc_sorting_MOD_ordvec+0x214>)\n-\tmov\tr4, r1\n+\tldr\tr2, [pc, #416]\t@ (6ec <__gridxc_sorting_MOD_ordvec+0x1b8>)\n \tstr\tr3, [r7, #28]\n \tadd\tr2, pc\n-\tldr\tr3, [pc, #504]\t@ (784 <__gridxc_sorting_MOD_ordvec+0x218>)\n-\tstr\tr1, [r7, #24]\n-\tstr\tr0, [r7, #44]\t@ 0x2c\n-\tstr\tr5, [r7, #52]\t@ 0x34\n-\tldr\tr4, [r4, #0]\n+\tldr\tr3, [pc, #412]\t@ (6f0 <__gridxc_sorting_MOD_ordvec+0x1bc>)\n+\tldr\tr4, [r7, #104]\t@ 0x68\n+\tstr\tr4, [r7, #12]\n+\tstrd\tr0, r5, [r7, #44]\t@ 0x2c\n+\tldr\tr4, [r1, #0]\n \tldr\tr3, [r2, r3]\n-\tldr\tr1, [r7, #104]\t@ 0x68\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #60]\t@ 0x3c\n \tmov.w\tr3, #0\n \tbic.w\tr3, r5, r5, asr #31\n \tbic.w\tfp, r4, r4, asr #31\n \tlsls\tr3, r3, #2\n \tmvn.w\tr0, fp\n@@ -543,139 +524,116 @@\n \tstr\tr0, [r7, #40]\t@ 0x28\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr2, r2, #15\n \tbic.w\tr3, r3, #7\n \tsub.w\tr2, sp, r2\n \tcmp\tr0, r2\n-\tbeq.n\t5d6 <__gridxc_sorting_MOD_ordvec+0x6a>\n+\tbeq.n\t59c <__gridxc_sorting_MOD_ordvec+0x68>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t5c8 <__gridxc_sorting_MOD_ordvec+0x5c>\n+\tbne.n\t58e <__gridxc_sorting_MOD_ordvec+0x5a>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t75c <__gridxc_sorting_MOD_ordvec+0x1f0>\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tbne.w\t6e0 <__gridxc_sorting_MOD_ordvec+0x1ac>\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tstr.w\tsp, [r7, #32]\n \tcmp\tr3, #0\n-\tble.n\t644 <__gridxc_sorting_MOD_ordvec+0xd8>\n-\tmov\tr2, r3\n-\tsubs\tr3, #1\n-\tcmp\tr3, #2\n-\tbls.w\t764 <__gridxc_sorting_MOD_ordvec+0x1f8>\n-\tvldr\td16, [pc, #372]\t@ 770 <__gridxc_sorting_MOD_ordvec+0x204>\n-\tvldr\td17, [pc, #376]\t@ 778 <__gridxc_sorting_MOD_ordvec+0x20c>\n-\tlsrs\tr0, r2, #2\n-\tvmov.i32\tq10, #4\t@ 0x00000004\n-\tmov\tr2, r1\n-\tmovs\tr3, #0\n-\tvorr\tq9, q8, q8\n-\tadds\tr3, #1\n-\tvadd.i32\tq8, q8, q10\n-\tcmp\tr0, r3\n-\tvst1.32\t{d18-d19}, [r2]!\n-\tbne.n\t60a <__gridxc_sorting_MOD_ordvec+0x9e>\n-\tldr\tr2, [r7, #52]\t@ 0x34\n-\tbic.w\tr3, r2, #3\n-\tadds\tr3, #1\n-\tlsls\tr2, r2, #30\n-\tbeq.n\t644 <__gridxc_sorting_MOD_ordvec+0xd8>\n-\tadd.w\tr2, r1, r3, lsl #2\n-\tldr\tr5, [r7, #52]\t@ 0x34\n+\tble.n\t5c8 <__gridxc_sorting_MOD_ordvec+0x94>\n+\tldr\tr3, [r7, #12]\n+\tsubs\tr2, r3, #4\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tadds\tr0, r3, #1\n-\tcmp\tr5, r0\n-\tstr.w\tr3, [r2, #-4]\n-\tblt.n\t644 <__gridxc_sorting_MOD_ordvec+0xd8>\n-\tstr.w\tr0, [r1, r3, lsl #2]\n-\tadds\tr3, #2\n-\tcmp\tr5, r3\n-\tblt.n\t644 <__gridxc_sorting_MOD_ordvec+0xd8>\n-\tstr\tr3, [r2, #4]\n+\tmovs\tr3, #1\n+\tstr.w\tr3, [r2, #4]!\n+\tadds\tr3, #1\n+\tcmp\tr3, r0\n+\tbne.n\t5be <__gridxc_sorting_MOD_ordvec+0x8a>\n \tcmp\tr4, #0\n-\tble.n\t6e2 <__gridxc_sorting_MOD_ordvec+0x176>\n-\tldr\tr3, [pc, #316]\t@ (788 <__gridxc_sorting_MOD_ordvec+0x21c>)\n-\tstr\tr1, [r7, #8]\n+\tble.n\t666 <__gridxc_sorting_MOD_ordvec+0x132>\n+\tldr\tr3, [pc, #292]\t@ (6f4 <__gridxc_sorting_MOD_ordvec+0x1c0>)\n+\tstr\tr1, [r7, #24]\n \tmov\tr1, r4\n \tadd\tr3, pc\n-\tstr\tr3, [r7, #12]\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tstr\tr3, [r7, #8]\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tsubs\tr3, #1\n \tstr\tr3, [r7, #36]\t@ 0x24\n \tldr\tr3, [r7, #28]\n \tadd.w\tr8, r3, r4, lsl #3\n \tadd.w\tr9, r1, #1\n \tmovs\tr6, #0\n \tadd.w\tsl, r8, #8\n-\tstr\tr4, [r7, #48]\t@ 0x30\n+\tstr\tr4, [r7, #52]\t@ 0x34\n \tstr\tr1, [r7, #16]\n \tstr.w\tr8, [r7, #4]\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tadds\tr2, r6, #1\n \tcmp\tr3, r2\n-\tble.n\t758 <__gridxc_sorting_MOD_ordvec+0x1ec>\n+\tble.n\t6dc <__gridxc_sorting_MOD_ordvec+0x1a8>\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tadd.w\tip, r6, #2\n \tmul.w\tr8, fp, r2\n-\tldr\tr4, [r7, #48]\t@ 0x30\n+\tldr\tr4, [r7, #52]\t@ 0x34\n \tmov\tr5, r2\n \tadd.w\tlr, r8, r3\n \tmla\tip, fp, ip, r3\n \tcmp\tr4, r9\n-\tblt.n\t6fe <__gridxc_sorting_MOD_ordvec+0x192>\n+\tblt.n\t682 <__gridxc_sorting_MOD_ordvec+0x14e>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n \tadd.w\tr0, sl, ip, lsl #3\n \tadd.w\tr1, sl, lr, lsl #3\n-\tvldr\td18, [r3]\n+\tvldr\td5, [r3]\n \tmov\tr3, r9\n-\tb.n\t6aa <__gridxc_sorting_MOD_ordvec+0x13e>\n+\tb.n\t62e <__gridxc_sorting_MOD_ordvec+0xfa>\n \tadds\tr3, #1\n \tcmp\tr4, r3\n-\tblt.n\t6fe <__gridxc_sorting_MOD_ordvec+0x192>\n-\tvldmia\tr0!, {d16}\n-\tvldmia\tr1!, {d17}\n-\tvsub.f64\td16, d16, d17\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d18\n+\tblt.n\t682 <__gridxc_sorting_MOD_ordvec+0x14e>\n+\tvldmia\tr0!, {d7}\n+\tvldmia\tr1!, {d6}\n+\tvsub.f64\td7, d7, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t6a4 <__gridxc_sorting_MOD_ordvec+0x138>\n+\tble.n\t628 <__gridxc_sorting_MOD_ordvec+0xf4>\n \tcmp\tr2, r5\n-\tstr\tr4, [r7, #48]\t@ 0x30\n-\tblt.n\t70c <__gridxc_sorting_MOD_ordvec+0x1a0>\n+\tstr\tr4, [r7, #52]\t@ 0x34\n+\tblt.n\t690 <__gridxc_sorting_MOD_ordvec+0x15c>\n \tmov\tr6, r5\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tcmp\tr6, r3\n-\tblt.n\t670 <__gridxc_sorting_MOD_ordvec+0x104>\n+\tblt.n\t5f4 <__gridxc_sorting_MOD_ordvec+0xc0>\n \tldr\tr1, [r7, #16]\n \tldr.w\tr8, [r7, #4]\n-\tldr\tr4, [r7, #48]\t@ 0x30\n+\tldr\tr4, [r7, #52]\t@ 0x34\n \tsubs\tr1, #1\n \tsub.w\tr8, r8, #8\n-\tbne.n\t65e <__gridxc_sorting_MOD_ordvec+0xf2>\n-\tldr\tr2, [pc, #168]\t@ (78c <__gridxc_sorting_MOD_ordvec+0x220>)\n-\tldr\tr3, [pc, #156]\t@ (784 <__gridxc_sorting_MOD_ordvec+0x218>)\n+\tbne.n\t5e2 <__gridxc_sorting_MOD_ordvec+0xae>\n+\tldr\tr2, [pc, #144]\t@ (6f8 <__gridxc_sorting_MOD_ordvec+0x1c4>)\n+\tldr\tr3, [pc, #132]\t@ (6f0 <__gridxc_sorting_MOD_ordvec+0x1bc>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #60]\t@ 0x3c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t768 <__gridxc_sorting_MOD_ordvec+0x1fc>\n+\tbne.n\t6e8 <__gridxc_sorting_MOD_ordvec+0x1b4>\n \tadds\tr7, #68\t@ 0x44\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tadds\tr5, #1\n \tadd\tip, fp\n \tadd\tlr, fp\n \tcmp\tr3, r5\n-\tbne.n\t68e <__gridxc_sorting_MOD_ordvec+0x122>\n-\tstr\tr4, [r7, #48]\t@ 0x30\n+\tbne.n\t612 <__gridxc_sorting_MOD_ordvec+0xde>\n+\tstr\tr4, [r7, #52]\t@ 0x34\n \tldr\tr3, [r7, #40]\t@ 0x28\n \tsubs\tr4, r5, r6\n \tldr\tr1, [r7, #16]\n \tadd\tr3, r8\n \tadd.w\tr8, r7, #56\t@ 0x38\n \tadds\tr0, r3, r1\n \tldr\tr1, [r7, #28]\n@@ -691,38 +649,31 @@\n \tadds\tr0, r2, #1\n \tldr\tr2, [r7, #28]\n \tldr\tr1, [r7, #24]\n \tstr\tr4, [r7, #56]\t@ 0x38\n \tadd.w\tr0, r2, r0, lsl #3\n \tmov\tr2, r8\n \tbl\t264 <__gridxc_sorting_MOD_order>\n-\tldr\tr1, [r7, #8]\n+\tldr\tr1, [r7, #12]\n \tldr\tr3, [r7, #32]\n \tmov\tr2, r8\n \tstr\tr4, [r7, #56]\t@ 0x38\n \tadd.w\tr0, r1, r6, lsl #2\n-\tldr\tr1, [r7, #12]\n+\tldr\tr1, [r7, #8]\n \tbl\t160 <__gridxc_sorting_MOD_iorder>\n-\tb.n\t6ca <__gridxc_sorting_MOD_ordvec+0x15e>\n+\tb.n\t64e <__gridxc_sorting_MOD_ordvec+0x11a>\n \tmov\tr6, r3\n-\tb.n\t6cc <__gridxc_sorting_MOD_ordvec+0x160>\n+\tb.n\t650 <__gridxc_sorting_MOD_ordvec+0x11c>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t5e4 <__gridxc_sorting_MOD_ordvec+0x78>\n-\tmovs\tr3, #1\n-\tb.n\t628 <__gridxc_sorting_MOD_ordvec+0xbc>\n+\tb.n\t5aa <__gridxc_sorting_MOD_ordvec+0x76>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n-\t.word\t0x000001f4\n+\t.word\t0x0000019a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000136\n+\t.word\t0x0000011e\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000a2\n+\t.word\t0x0000008a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "sys.F90.o", "source2": "sys.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 2348 (bytes into file)\n+ Start of section headers: 2324 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 14\n Section header string table index: 13\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,23 +1,23 @@\n-There are 14 section headers, starting at offset 0x92c:\n+There are 14 section headers, starting at offset 0x914:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 0001c0 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 000784 000118 08 I 11 1 4\n- [ 3] .data PROGBITS 00000000 0001f8 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 0001f8 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 0001f8 0000a2 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 00029c 000004 00 A 0 0 4\n- [ 7] .data.rel PROGBITS 00000000 0002a0 00000c 00 WA 0 0 4\n- [ 8] .rel.data.rel REL 00000000 00089c 000018 08 I 11 7 4\n- [ 9] .note.GNU-stack PROGBITS 00000000 0002ac 000000 00 0 0 1\n- [10] .ARM.attributes ARM_ATTRIBUTES 00000000 0002ac 000033 00 0 0 1\n- [11] .symtab SYMTAB 00000000 0002e0 000270 10 12 18 4\n- [12] .strtab STRTAB 00000000 000550 000232 00 0 0 1\n- [13] .shstrtab STRTAB 00000000 0008b4 000075 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000034 0001b0 00 AX 0 0 4\n+ [ 2] .rel.text REL 00000000 00076c 000118 08 I 11 1 4\n+ [ 3] .data PROGBITS 00000000 0001e4 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 0001e4 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0001e4 0000a2 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 000288 000004 00 A 0 0 4\n+ [ 7] .data.rel PROGBITS 00000000 00028c 00000c 00 WA 0 0 4\n+ [ 8] .rel.data.rel REL 00000000 000884 000018 08 I 11 7 4\n+ [ 9] .note.GNU-stack PROGBITS 00000000 000298 000000 00 0 0 1\n+ [10] .ARM.attributes ARM_ATTRIBUTES 00000000 000298 00002d 00 0 0 1\n+ [11] .symtab SYMTAB 00000000 0002c8 000270 10 12 18 4\n+ [12] .strtab STRTAB 00000000 000538 000232 00 0 0 1\n+ [13] .shstrtab STRTAB 00000000 00089c 000075 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -6,37 +6,37 @@\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 4: 00000038 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 5: 00000040 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 6: 00000064 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 7: 00000068 0 NOTYPE LOCAL DEFAULT 5 .LC4\n 8: 00000148 0 NOTYPE LOCAL DEFAULT 1 $d\n- 9: 0000017c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 0000018c 0 NOTYPE LOCAL DEFAULT 1 $d\n- 11: 00000194 0 NOTYPE LOCAL DEFAULT 1 $t\n- 12: 000001a0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 13: 000001a8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 14: 000001b8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 9: 0000016c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 10: 0000017c 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 11: 00000184 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 12: 00000190 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 13: 00000198 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 14: 000001a8 0 NOTYPE LOCAL DEFAULT 1 $d\n 15: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n 16: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n 17: 00000000 0 NOTYPE LOCAL DEFAULT 7 $d\n 18: 00000001 2 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_dummy_timer_start\n- 19: 00000005 376 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_simple_die_routine\n+ 19: 00000005 360 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_simple_die_routine\n 20: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n 21: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_len_trim\n 22: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n 23: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n 24: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n 25: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n 26: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n 27: 00000000 0 NOTYPE GLOBAL DEFAULT UND exit\n 28: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n 29: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 30: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 31: 0000017d 2 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_dummy_timer_stop\n- 32: 00000181 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_timer_stop_routine\n+ 31: 0000016d 2 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_dummy_timer_stop\n+ 32: 00000171 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_timer_stop_routine\n 33: 00000000 4 OBJECT GLOBAL DEFAULT 7 __gridxc_sys_MOD_gridxc_timer_stop\n- 34: 00000195 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_timer_start_routine\n+ 34: 00000185 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_timer_start_routine\n 35: 00000004 4 OBJECT GLOBAL DEFAULT 7 __gridxc_sys_MOD_gridxc_timer_start\n- 36: 000001a9 4 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_exit\n- 37: 000001ad 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_die_routine\n+ 36: 00000199 4 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_exit\n+ 37: 0000019d 20 FUNC GLOBAL DEFAULT 1 __gridxc_sys_MOD_set_die_routine\n 38: 00000008 4 OBJECT GLOBAL DEFAULT 7 __gridxc_sys_MOD_die\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,44 +1,44 @@\n \n-Relocation section '.rel.text' at offset 0x784 contains 35 entries:\n+Relocation section '.rel.text' at offset 0x76c contains 35 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000005a 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000062 0000150a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-00000070 0000160a R_ARM_THM_CALL 00000000 malloc\n-00000086 0000170a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000090 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000096 0000190a R_ARM_THM_CALL 00000000 free\n-0000009c 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-000000b0 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000000b8 0000150a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-000000c6 0000160a R_ARM_THM_CALL 00000000 malloc\n-000000d8 0000170a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000000e2 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000000e8 0000190a R_ARM_THM_CALL 00000000 free\n-000000ee 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000108 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000114 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000011a 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000144 00001c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000158 00000303 R_ARM_REL32 00000000 .LC0\n-0000015c 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000160 00000403 R_ARM_REL32 00000038 .LC1\n-00000164 00001e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000168 00000503 R_ARM_REL32 00000040 .LC2\n-0000016c 00000603 R_ARM_REL32 00000064 .LC3\n-00000170 00000703 R_ARM_REL32 00000068 .LC4\n-00000174 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000178 00000f03 R_ARM_REL32 00000000 .rodata\n-0000018c 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000190 0000211a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n-000001a0 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000001a4 0000231a R_ARM_GOT_BREL 00000004 __gridxc_sys_MOD_gridxc_timer_start\n-000001b8 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000001bc 0000261a R_ARM_GOT_BREL 00000008 __gridxc_sys_MOD_die\n-00000140 00001b1e R_ARM_THM_JUMP24 00000000 exit\n-000001a8 00001b1e R_ARM_THM_JUMP24 00000000 exit\n+00000054 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000005c 0000150a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+0000006a 0000160a R_ARM_THM_CALL 00000000 malloc\n+00000080 0000170a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000008a 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000090 0000190a R_ARM_THM_CALL 00000000 free\n+00000096 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000000b2 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000000ba 0000150a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+000000c8 0000160a R_ARM_THM_CALL 00000000 malloc\n+000000da 0000170a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000000e4 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+000000ea 0000190a R_ARM_THM_CALL 00000000 free\n+000000f0 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000010a 0000140a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000116 0000180a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+0000011c 00001a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000142 00001c0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000148 00000303 R_ARM_REL32 00000000 .LC0\n+0000014c 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000150 00000403 R_ARM_REL32 00000038 .LC1\n+00000154 00001e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000158 00000503 R_ARM_REL32 00000040 .LC2\n+0000015c 00000603 R_ARM_REL32 00000064 .LC3\n+00000160 00000703 R_ARM_REL32 00000068 .LC4\n+00000164 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000168 00000f03 R_ARM_REL32 00000000 .rodata\n+0000017c 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000180 0000211a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_gridxc_timer_stop\n+00000190 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000194 0000231a R_ARM_GOT_BREL 00000004 __gridxc_sys_MOD_gridxc_timer_start\n+000001a8 00001d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000001ac 0000261a R_ARM_GOT_BREL 00000008 __gridxc_sys_MOD_die\n+0000013e 00001b1e R_ARM_THM_JUMP24 00000000 exit\n+00000198 00001b1e R_ARM_THM_JUMP24 00000000 exit\n \n-Relocation section '.rel.data.rel' at offset 0x89c contains 3 entries:\n+Relocation section '.rel.data.rel' at offset 0x884 contains 3 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000000 00001f02 R_ARM_ABS32 0000017d __gridxc_sys_MOD_dummy_timer_stop\n+00000000 00001f02 R_ARM_ABS32 0000016d __gridxc_sys_MOD_dummy_timer_stop\n 00000004 00001202 R_ARM_ABS32 00000001 __gridxc_sys_MOD_dummy_timer_start\n 00000008 00001302 R_ARM_ABS32 00000005 __gridxc_sys_MOD_simple_die_routine\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -8,53 +8,52 @@\n \tbx\tlr\n \tnop\n \n 00000004 <__gridxc_sys_MOD_simple_die_routine>:\n __gridxc_sys_MOD_simple_die_routine():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3680]\t@ 0xe60\n+\tstr.w\tr0, [ip, #3688]\t@ 0xe68\n \tsub\tsp, #372\t@ 0x174\n-\tvldr\td16, [pc, #300]\t@ 148 <__gridxc_sys_MOD_simple_die_routine+0x144>\n+\tldr\tr6, [pc, #304]\t@ (148 <__gridxc_sys_MOD_simple_die_routine+0x144>)\n \tadd\tr4, sp, #16\n-\tldr\tr6, [pc, #308]\t@ (158 <__gridxc_sys_MOD_simple_die_routine+0x154>)\n-\tldr\tr2, [pc, #312]\t@ (15c <__gridxc_sys_MOD_simple_die_routine+0x158>)\n-\tmovs\tr3, #60\t@ 0x3c\n-\tvstr\td16, [sp, #16]\n+\tldr\tr2, [pc, #304]\t@ (14c <__gridxc_sys_MOD_simple_die_routine+0x148>)\n \tadd\tr6, pc\n-\tldr.w\tfp, [pc, #304]\t@ 160 <__gridxc_sys_MOD_simple_die_routine+0x15c>\n+\tmovs\tr3, #60\t@ 0x3c\n+\tldr.w\tfp, [pc, #300]\t@ 150 <__gridxc_sys_MOD_simple_die_routine+0x14c>\n \tadd\tr2, pc\n \tstrd\tr6, r3, [r4, #8]\n \tmov\tr5, r0\n-\tldr\tr3, [pc, #296]\t@ (164 <__gridxc_sys_MOD_simple_die_routine+0x160>)\n+\tldr\tr3, [pc, #292]\t@ (154 <__gridxc_sys_MOD_simple_die_routine+0x150>)\n \tadd\tfp, pc\n \tstr.w\tfp, [r4, #52]\t@ 0x34\n \tmov\tr8, r1\n-\tmov\tr0, r4\n \tmov.w\tsl, #5\n-\tvldr\td8, [pc, #260]\t@ 150 <__gridxc_sys_MOD_simple_die_routine+0x14c>\n+\tmov\tr0, r4\n \tldr\tr3, [r2, r3]\n+\tmov.w\tr2, #4096\t@ 0x1000\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #364]\t@ 0x16c\n \tmov.w\tr3, #0\n \tstr.w\tsl, [r4, #56]\t@ 0x38\n+\tmovs\tr3, #0\n+\tstrd\tr2, r3, [sp, #16]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n \tmov\tr1, r5\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tr7, r0, r0, asr #31\n \tadd.w\tr9, r7, #35\t@ 0x23\n \tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #240]\t@ (168 <__gridxc_sys_MOD_simple_die_routine+0x164>)\n+\tldr\tr3, [pc, #232]\t@ (158 <__gridxc_sys_MOD_simple_die_routine+0x154>)\n \tmov\tr1, r0\n \tmovs\tr2, #35\t@ 0x23\n \tadd\tr3, pc\n \tstr\tr7, [sp, #0]\n \tstr\tr5, [sp, #4]\n \tmov\tr7, r0\n \tmov\tr0, r9\n@@ -69,19 +68,21 @@\n \tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tmovs\tr2, #61\t@ 0x3d\n-\tmov\tr0, r4\n \tstrd\tfp, sl, [r4, #52]\t@ 0x34\n-\tstr\tr6, [r4, #8]\n-\tvstr\td8, [sp, #16]\n+\tmov\tr0, r4\n \tstr\tr2, [r4, #12]\n+\tmov.w\tsl, #4096\t@ 0x1000\n+\tstr\tr6, [r4, #8]\n+\tmov.w\tfp, #6\n+\tstrd\tsl, fp, [sp, #16]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n \tmov\tr1, r5\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_string_len_trim>\n R_ARM_THM_CALL\t_gfortran_string_len_trim\n \tbic.w\tr7, r0, r0, asr #31\n@@ -93,126 +94,123 @@\n \tmov\tr1, r0\n \tmovs\tr2, #35\t@ 0x23\n \tstrd\tr7, r5, [sp]\n \tmov\tr5, r0\n \tmov\tr0, r8\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n-\tmov\tr2, r8\n \tmov\tr1, r5\n+\tmov\tr2, r8\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tldr\tr3, [pc, #120]\t@ (16c <__gridxc_sys_MOD_simple_die_routine+0x168>)\n-\tvstr\td8, [sp, #16]\n-\tmovs\tr1, #62\t@ 0x3e\n-\tadd\tr3, pc\n-\tmovs\tr2, #3\n+\tldr\tr3, [pc, #100]\t@ (15c <__gridxc_sys_MOD_simple_die_routine+0x158>)\n+\tmovs\tr2, #62\t@ 0x3e\n \tmov\tr0, r4\n-\tstrd\tr3, r2, [r4, #52]\t@ 0x34\n-\tstr\tr1, [r4, #12]\n+\tstr\tr2, [r4, #12]\n+\tadd\tr3, pc\n+\tstr\tr3, [r4, #52]\t@ 0x34\n+\tmovs\tr3, #3\n+\tstrd\tsl, fp, [sp, #16]\n+\tstr\tr3, [r4, #56]\t@ 0x38\n \tstr\tr6, [r4, #8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #96]\t@ (170 <__gridxc_sys_MOD_simple_die_routine+0x16c>)\n+\tldr\tr1, [pc, #80]\t@ (160 <__gridxc_sys_MOD_simple_die_routine+0x15c>)\n \tmovs\tr2, #57\t@ 0x39\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tldr\tr2, [pc, #84]\t@ (174 <__gridxc_sys_MOD_simple_die_routine+0x170>)\n-\tldr\tr3, [pc, #64]\t@ (164 <__gridxc_sys_MOD_simple_die_routine+0x160>)\n+\tldr\tr2, [pc, #64]\t@ (164 <__gridxc_sys_MOD_simple_die_routine+0x160>)\n+\tldr\tr3, [pc, #48]\t@ (154 <__gridxc_sys_MOD_simple_die_routine+0x150>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #364]\t@ 0x16c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t144 <__gridxc_sys_MOD_simple_die_routine+0x140>\n-\tldr\tr0, [pc, #68]\t@ (178 <__gridxc_sys_MOD_simple_die_routine+0x174>)\n+\tbne.n\t142 <__gridxc_sys_MOD_simple_die_routine+0x13e>\n+\tldr\tr0, [pc, #48]\t@ (168 <__gridxc_sys_MOD_simple_die_routine+0x164>)\n \tadd\tr0, pc\n \tadd\tsp, #372\t@ 0x174\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\texit\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x00001000\n-\t.word\t0x00000000\n-\t.word\t0x00001000\n-\t.word\t0x00000006\n-\t.word\t0x0000012a\n- R_ARM_REL32\t.LC0\n+\tnop\n \t.word\t0x00000128\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x00000124\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000122\n+\t.word\t0x0000011e\n R_ARM_REL32\t.LC1\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000000ea\n+\t.word\t0x000000e0\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000006e\n+\t.word\t0x0000005c\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000005a\n+\t.word\t0x00000048\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000004e\n+\t.word\t0x0000003c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000040\n+\t.word\t0x0000002e\n R_ARM_REL32\t.rodata\n \n-0000017c <__gridxc_sys_MOD_dummy_timer_stop>:\n+0000016c <__gridxc_sys_MOD_dummy_timer_stop>:\n __gridxc_sys_MOD_dummy_timer_stop():\n \tbx\tlr\n \tnop\n \n-00000180 <__gridxc_sys_MOD_set_timer_stop_routine>:\n+00000170 <__gridxc_sys_MOD_set_timer_stop_routine>:\n __gridxc_sys_MOD_set_timer_stop_routine():\n-\tldr\tr3, [pc, #8]\t@ (18c <__gridxc_sys_MOD_set_timer_stop_routine+0xc>)\n-\tldr\tr2, [pc, #12]\t@ (190 <__gridxc_sys_MOD_set_timer_stop_routine+0x10>)\n+\tldr\tr3, [pc, #8]\t@ (17c <__gridxc_sys_MOD_set_timer_stop_routine+0xc>)\n+\tldr\tr2, [pc, #12]\t@ (180 <__gridxc_sys_MOD_set_timer_stop_routine+0x10>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, r2]\n \tstr\tr0, [r3, #0]\n \tbx\tlr\n \t.word\t0x00000004\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_stop\n \n-00000194 <__gridxc_sys_MOD_set_timer_start_routine>:\n+00000184 <__gridxc_sys_MOD_set_timer_start_routine>:\n __gridxc_sys_MOD_set_timer_start_routine():\n-\tldr\tr3, [pc, #8]\t@ (1a0 <__gridxc_sys_MOD_set_timer_start_routine+0xc>)\n-\tldr\tr2, [pc, #12]\t@ (1a4 <__gridxc_sys_MOD_set_timer_start_routine+0x10>)\n+\tldr\tr3, [pc, #8]\t@ (190 <__gridxc_sys_MOD_set_timer_start_routine+0xc>)\n+\tldr\tr2, [pc, #12]\t@ (194 <__gridxc_sys_MOD_set_timer_start_routine+0x10>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, r2]\n \tstr\tr0, [r3, #0]\n \tbx\tlr\n \t.word\t0x00000004\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_gridxc_timer_start\n \n-000001a8 <__gridxc_sys_MOD_exit>:\n+00000198 <__gridxc_sys_MOD_exit>:\n __gridxc_sys_MOD_exit():\n \tb.w\t0 \n R_ARM_THM_JUMP24\texit\n \n-000001ac <__gridxc_sys_MOD_set_die_routine>:\n+0000019c <__gridxc_sys_MOD_set_die_routine>:\n __gridxc_sys_MOD_set_die_routine():\n-\tldr\tr3, [pc, #8]\t@ (1b8 <__gridxc_sys_MOD_set_die_routine+0xc>)\n-\tldr\tr2, [pc, #12]\t@ (1bc <__gridxc_sys_MOD_set_die_routine+0x10>)\n+\tldr\tr3, [pc, #8]\t@ (1a8 <__gridxc_sys_MOD_set_die_routine+0xc>)\n+\tldr\tr2, [pc, #12]\t@ (1ac <__gridxc_sys_MOD_set_die_routine+0x10>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, r2]\n \tstr\tr0, [r3, #0]\n \tbx\tlr\n \t.word\t0x00000004\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "vdwxc.F90.o", "source2": "vdwxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 34360 (bytes into file)\n+ Start of section headers: 34308 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x8638:\n+There are 12 section headers, starting at offset 0x8604:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 00551c 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 007770 000e60 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 005558 00001d 00 WA 0 0 8\n- [ 4] .bss NOBITS 00000000 005578 011f48 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 005578 000435 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0059b0 000864 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 006214 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 006214 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 006248 000bf0 10 10 122 4\n- [10] .strtab STRTAB 00000000 006e38 000936 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 0085d0 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 0054b8 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 007744 000e58 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0054f0 00001d 00 WA 0 0 8\n+ [ 4] .bss NOBITS 00000000 005510 011f38 00 WA 0 0 8\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 005510 000435 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 005948 000864 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 0061ac 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0061ac 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 0061dc 000c30 10 10 126 4\n+ [10] .strtab STRTAB 00000000 006e0c 000936 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 00859c 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,194 +1,198 @@\n \n-Symbol table '.symtab' contains 191 entries:\n+Symbol table '.symtab' contains 195 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 5: 00000044 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 6: 00000060 0 NOTYPE LOCAL DEFAULT 5 .LC3\n 7: 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00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 112: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 113: 00000030 2048 OBJECT LOCAL DEFAULT 6 wt.7\n+ 114: 00000830 8 OBJECT LOCAL DEFAULT 6 A.330.6\n+ 115: 00000838 8 OBJECT LOCAL DEFAULT 6 A.332.5\n+ 116: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 117: 00000000 4 OBJECT LOCAL DEFAULT 3 first_call.4\n+ 118: 00000004 4 OBJECT LOCAL DEFAULT 3 first_call.13\n+ 119: 00000008 4 OBJECT LOCAL DEFAULT 3 first_call.10\n+ 120: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 121: 000000a0 8 OBJECT LOCAL DEFAULT 4 b.2\n+ 122: 000000a8 8 OBJECT LOCAL DEFAULT 4 a.3\n+ 123: 000001a0 8 OBJECT LOCAL DEFAULT 4 b.8\n+ 124: 000001a8 8 OBJECT LOCAL DEFAULT 4 a.9\n+ 125: 000002d0 4 OBJECT LOCAL DEFAULT 4 initialized.1\n+ 126: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_get_n\n+ 127: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 128: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_mesh\n+ 129: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_get_mesh\n+ 130: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n+ 131: 00000000 0 NOTYPE GLOBAL DEFAULT UND sincos\n+ 132: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 133: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 134: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_integral\n+ 135: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 136: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_os_error_at\n+ 137: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error\n+ 138: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 139: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_runtime_error_at\n+ 140: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n+ 141: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 142: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_x\n+ 143: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_inquire\n+ 144: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 145: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_reshape_r8\n+ 146: 00005738 51200 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_phi_table\n+ 147: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_open\n+ 148: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 149: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n+ 150: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 151: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_array_write\n+ 152: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_close\n+ 153: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n+ 154: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n+ 155: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n+ 156: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_array\n+ 157: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n+ 158: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_ldaxc\n+ 159: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 160: 0000272d 2220 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_theta\n+ 161: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n+ 162: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n+ 163: 00002fd9 3824 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_set_kcut\n+ 164: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n+ 165: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n+ 166: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_radfft_MOD_radfft\n+ 167: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n+ 168: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_dx\n+ 169: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n+ 170: 00003ec9 292 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_set_author\n+ 171: 00003fed 1480 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_phi\n+ 172: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n+ 173: 000045b5 1652 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_localxc\n+ 174: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_gga_MOD_ggaxc\n+ 175: 00004c29 588 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_get_qmesh\n+ 176: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n+ 177: 00004e75 1604 FUNC GLOBAL DEFAULT 1 __gridxc_vdwxc_MOD_vdw_decusp\n+ 178: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n+ 179: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_evaluate_spline_dx\n+ 180: 00000010 8 OBJECT GLOBAL HIDDEN 3 __gridxc_vdwxc_MOD_zab\n+ 181: 00000018 5 OBJECT GLOBAL HIDDEN 3 __gridxc_vdwxc_MOD_vdw_author\n+ 182: 000001c0 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_qmesh_set\n+ 183: 000000b0 240 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_qmesh\n+ 184: 000001c4 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_phir\n+ 185: 00000200 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_phik\n+ 186: 000001b0 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_phi_table_set\n+ 187: 000002c8 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_nk\n+ 188: 000002cc 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_kcut_set\n+ 189: 000001b8 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_kcut\n+ 190: 000002b8 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_dr\n+ 191: 00000000 160 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_dmesh\n+ 192: 000002c0 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_dk\n+ 193: 0000023c 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_d2phidr2\n+ 194: 00000278 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vdwxc_MOD_d2phidk2\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,463 +1,462 @@\n \n-Relocation section '.rel.text' at offset 0x7770 contains 460 entries:\n+Relocation section '.rel.text' at offset 0x7744 contains 459 entries:\n Offset Info Type Sym. Value Symbol's Name\n-0000007a 00007a0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_n\n-000000b2 00007b0a R_ARM_THM_CALL 00000000 malloc\n-000000d6 00007b0a R_ARM_THM_CALL 00000000 malloc\n-000000e4 00007b0a R_ARM_THM_CALL 00000000 malloc\n-000000f2 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000100 00007b0a R_ARM_THM_CALL 00000000 malloc\n-0000010e 00007b0a R_ARM_THM_CALL 00000000 malloc\n-0000011c 00007b0a R_ARM_THM_CALL 00000000 malloc\n-0000012a 00007b0a R_ARM_THM_CALL 00000000 malloc\n-0000015c 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-0000016e 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-00000262 00007e0a R_ARM_THM_CALL 00000000 exp\n-0000028e 00007f0a R_ARM_THM_CALL 00000000 sincos\n-000002ce 00007e0a R_ARM_THM_CALL 00000000 exp\n-000002ec 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000328 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000032c 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000330 00006b03 R_ARM_REL32 00000000 .rodata\n-000004ba 0000820a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n-000004ca 0000820a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n-000004ec 0000820a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n-00000502 0000830a R_ARM_THM_CALL 00000000 free\n-00000508 0000830a R_ARM_THM_CALL 00000000 free\n-0000050e 0000830a R_ARM_THM_CALL 00000000 free\n-00000514 0000830a R_ARM_THM_CALL 00000000 free\n-0000051a 0000830a R_ARM_THM_CALL 00000000 free\n-00000520 0000830a R_ARM_THM_CALL 00000000 free\n-00000526 0000830a R_ARM_THM_CALL 00000000 free\n-0000052c 0000830a R_ARM_THM_CALL 00000000 free\n-0000059e 00007e0a R_ARM_THM_CALL 00000000 exp\n-000005e4 00007f0a R_ARM_THM_CALL 00000000 sincos\n-00000668 00007f0a R_ARM_THM_CALL 00000000 sincos\n-000006ac 00007e0a R_ARM_THM_CALL 00000000 exp\n-000006d8 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000712 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00000720 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-0000072e 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-0000073c 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-0000074a 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00000752 0000850a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00000756 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000766 0000870a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-00000774 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00000782 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00000790 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-000007a8 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000007ac 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000007b0 00000503 R_ARM_REL32 00000044 .LC2\n-000007b4 00000603 R_ARM_REL32 00000060 .LC3\n-000007b8 00000503 R_ARM_REL32 00000044 .LC2\n-000007bc 00000603 R_ARM_REL32 00000060 .LC3\n-000007c0 00000503 R_ARM_REL32 00000044 .LC2\n-000007c4 00000603 R_ARM_REL32 00000060 .LC3\n-000007c8 00000503 R_ARM_REL32 00000044 .LC2\n-000007cc 00000603 R_ARM_REL32 00000060 .LC3\n-000007d0 00000503 R_ARM_REL32 00000044 .LC2\n-000007d4 00000603 R_ARM_REL32 00000060 .LC3\n-000007d8 00000403 R_ARM_REL32 00000000 .LC1\n-000007dc 00000703 R_ARM_REL32 000000b4 .LC4\n-000007e0 00000803 R_ARM_REL32 000000bc .LC5\n-000007e4 00000903 R_ARM_REL32 000000e4 .LC6\n-000007e8 00000503 R_ARM_REL32 00000044 .LC2\n-000007ec 00000603 R_ARM_REL32 00000060 .LC3\n-000007f0 00000503 R_ARM_REL32 00000044 .LC2\n-000007f4 00000603 R_ARM_REL32 00000060 .LC3\n-000007f8 00000503 R_ARM_REL32 00000044 .LC2\n-000007fc 00000603 R_ARM_REL32 00000060 .LC3\n-0000083e 0000880a R_ARM_THM_CALL 00000000 log\n-00000880 0000880a R_ARM_THM_CALL 00000000 log\n-00000898 00007e0a R_ARM_THM_CALL 00000000 exp\n-000008c8 00000103 R_ARM_REL32 00000000 .data\n-000008cc 00000203 R_ARM_REL32 00000000 .bss\n-00000922 0000890a R_ARM_THM_CALL 00000000 memset\n-00000942 00008a0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n-00000998 0000880a R_ARM_THM_CALL 00000000 log\n-00000a9e 0000880a R_ARM_THM_CALL 00000000 log\n-00000ab6 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000ad6 0000890a R_ARM_THM_CALL 00000000 memset\n-00000b08 00000103 R_ARM_REL32 00000000 .data\n-00000b0c 00000203 R_ARM_REL32 00000000 .bss\n-00000b10 00006b03 R_ARM_REL32 00000000 .rodata\n-00000b14 00000203 R_ARM_REL32 00000000 .bss\n-00000b18 00000203 R_ARM_REL32 00000000 .bss\n-00000b1c 00000103 R_ARM_REL32 00000000 .data\n-00000b20 00000203 R_ARM_REL32 00000000 .bss\n-00000b24 00000103 R_ARM_REL32 00000000 .data\n-00000b28 00000203 R_ARM_REL32 00000000 .bss\n-00000b2c 00000203 R_ARM_REL32 00000000 .bss\n-00000b30 00000203 R_ARM_REL32 00000000 .bss\n-00000bb2 00007a0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_n\n-00000be8 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c0e 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c1c 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c2a 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c38 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c46 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c54 00007b0a R_ARM_THM_CALL 00000000 malloc\n-00000c86 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-00000c98 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-00000d12 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000d46 00007f0a R_ARM_THM_CALL 00000000 sincos\n-00000d90 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d94 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000d98 00006b03 R_ARM_REL32 00000000 .rodata\n-00000dda 00007f0a R_ARM_THM_CALL 00000000 sincos\n-00000e1c 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000e28 00007e0a R_ARM_THM_CALL 00000000 exp\n-00000fb2 0000820a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n-00000fce 0000820a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n-00000fe4 0000830a R_ARM_THM_CALL 00000000 free\n-00000fea 0000830a R_ARM_THM_CALL 00000000 free\n-00000ff0 0000830a R_ARM_THM_CALL 00000000 free\n-00000ff6 0000830a R_ARM_THM_CALL 00000000 free\n-00000ffc 0000830a R_ARM_THM_CALL 00000000 free\n-00001002 0000830a R_ARM_THM_CALL 00000000 free\n-00001008 0000830a R_ARM_THM_CALL 00000000 free\n-00001080 00007f0a R_ARM_THM_CALL 00000000 sincos\n-000010b0 00007e0a R_ARM_THM_CALL 00000000 exp\n-000010fa 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001108 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001120 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001124 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001128 00000503 R_ARM_REL32 00000044 .LC2\n-0000112c 00001703 R_ARM_REL32 00000130 .LC9\n-0000113a 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001148 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001156 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001164 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001172 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001180 0000840a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n-00001188 0000850a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n-00001198 0000870a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n-0000119c 00000503 R_ARM_REL32 00000044 .LC2\n-000011a0 00001703 R_ARM_REL32 00000130 .LC9\n-000011a4 00000503 R_ARM_REL32 00000044 .LC2\n-000011a8 00001703 R_ARM_REL32 00000130 .LC9\n-000011ac 00000503 R_ARM_REL32 00000044 .LC2\n-000011b0 00001703 R_ARM_REL32 00000130 .LC9\n-000011b4 00000503 R_ARM_REL32 00000044 .LC2\n-000011b8 00001703 R_ARM_REL32 00000130 .LC9\n-000011bc 00000503 R_ARM_REL32 00000044 .LC2\n-000011c0 00001703 R_ARM_REL32 00000130 .LC9\n-000011c4 00000503 R_ARM_REL32 00000044 .LC2\n-000011c8 00001703 R_ARM_REL32 00000130 .LC9\n-000011cc 00000403 R_ARM_REL32 00000000 .LC1\n-000011d0 00000703 R_ARM_REL32 000000b4 .LC4\n-000011d4 00000803 R_ARM_REL32 000000bc .LC5\n-000011d8 00001803 R_ARM_REL32 00000184 .LC10\n-0000135c 00008b0a R_ARM_THM_CALL 00000000 _gfortran_st_inquire\n-000013a2 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-000013f6 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-000016a8 00002303 R_ARM_REL32 000001d0 .LC11\n-000016ac 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000016b0 00002403 R_ARM_REL32 00000208 .LC12\n-000016b4 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000016b8 00006b03 R_ARM_REL32 00000000 .rodata\n-000016bc 00000203 R_ARM_REL32 00000000 .bss\n-00001700 0000890a R_ARM_THM_CALL 00000000 memset\n-00001720 0000890a R_ARM_THM_CALL 00000000 memset\n-00001740 0000890a R_ARM_THM_CALL 00000000 memset\n-00001764 0000890a R_ARM_THM_CALL 00000000 memset\n-0000178c 0000890a R_ARM_THM_CALL 00000000 memset\n-00001796 0000890a R_ARM_THM_CALL 00000000 memset\n-00001940 00008c0a R_ARM_THM_CALL 00000000 memcpy\n-00001b14 00008d0a R_ARM_THM_CALL 00000000 _gfortran_reshape_r8\n-00001b68 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-00001b6c 00006b03 R_ARM_REL32 00000000 .rodata\n-00001b70 00006b03 R_ARM_REL32 00000000 .rodata\n-00001e6c 00008f0a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00001e84 0000900a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001e92 0000910a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00001e98 0000920a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001eb0 0000900a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001ef2 0000930a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001ef8 0000920a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001f0e 0000900a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001f68 0000930a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001f6e 0000920a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001f82 0000940a R_ARM_THM_CALL 00000000 _gfortran_st_close\n-00002018 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-0000201c 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-00002020 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-00002024 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-00002028 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-0000202c 00002303 R_ARM_REL32 000001d0 .LC11\n-00002030 00002403 R_ARM_REL32 00000208 .LC12\n-00002034 00002503 R_ARM_REL32 0000021c .LC13\n-00002038 00006b03 R_ARM_REL32 00000000 .rodata\n-0000203c 00000203 R_ARM_REL32 00000000 .bss\n-00002040 00000203 R_ARM_REL32 00000000 .bss\n-00002044 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002048 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002082 00008f0a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00002096 0000950a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-000020a0 0000960a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n-000020a6 0000970a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-000020e2 0000950a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-00002130 0000980a R_ARM_THM_CALL 00000000 _gfortran_transfer_array\n-00002136 0000970a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-00002156 0000950a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-000021b6 0000980a R_ARM_THM_CALL 00000000 _gfortran_transfer_array\n-000021bc 0000970a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-000021e8 0000940a R_ARM_THM_CALL 00000000 _gfortran_st_close\n-00002200 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002260 00002503 R_ARM_REL32 0000021c .LC13\n-00002264 00000203 R_ARM_REL32 00000000 .bss\n-00002268 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-0000226c 00002303 R_ARM_REL32 000001d0 .LC11\n-000022c0 0000990a R_ARM_THM_CALL 00000000 cbrt\n-00002302 00009a0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n-0000248a 00007e0a R_ARM_THM_CALL 00000000 exp\n-00002500 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002560 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002564 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00002568 00006b03 R_ARM_REL32 00000000 .rodata\n-0000256c 00002f03 R_ARM_REL32 00000228 .LC19\n-00002570 00000103 R_ARM_REL32 00000000 .data\n-00002574 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002662 00007e0a R_ARM_THM_CALL 00000000 exp\n-00002760 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00002764 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002768 00003303 R_ARM_REL32 00000230 .LC20\n-0000285a 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00002952 0000890a R_ARM_THM_CALL 00000000 memset\n-000029c2 0000890a R_ARM_THM_CALL 00000000 memset\n-00002b80 00009e0a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n-00002bd2 00008c0a R_ARM_THM_CALL 00000000 memcpy\n-00002d9a 00008c0a R_ARM_THM_CALL 00000000 memcpy\n-00003000 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00003004 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003008 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000300c 00000103 R_ARM_REL32 00000000 .data\n-00003010 00003703 R_ARM_REL32 00000258 .LC21\n-00003014 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000307e 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000030f8 0000a00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00003120 0000a00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00003146 0000a00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-0000316c 0000a00a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00003360 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003364 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003368 00000103 R_ARM_REL32 00000000 .data\n-0000336c 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003370 00003703 R_ARM_REL32 00000258 .LC21\n-00003374 00000203 R_ARM_REL32 00000000 .bss\n-00003378 00006b03 R_ARM_REL32 00000000 .rodata\n-0000337c 00000203 R_ARM_REL32 00000000 .bss\n-00003380 00003a03 R_ARM_REL32 0000025c .LC24\n-00003384 00003b03 R_ARM_REL32 00000270 .LC25\n-00003388 00003c03 R_ARM_REL32 00000284 .LC26\n-0000338c 00003d03 R_ARM_REL32 0000029c .LC27\n-00003390 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00003394 00003e03 R_ARM_REL32 000002b4 .LC28\n-00003398 00000203 R_ARM_REL32 00000000 .bss\n-0000339c 00000203 R_ARM_REL32 00000000 .bss\n-000033a0 00000203 R_ARM_REL32 00000000 .bss\n-0000345a 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000034ca 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000034e4 0000a20a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-000034ee 0000830a R_ARM_THM_CALL 00000000 free\n-000034fe 0000a30a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00003504 0000830a R_ARM_THM_CALL 00000000 free\n-000035d0 00000203 R_ARM_REL32 00000000 .bss\n-000035d4 00006b03 R_ARM_REL32 00000000 .rodata\n-000035d8 00000203 R_ARM_REL32 00000000 .bss\n-000035dc 00000203 R_ARM_REL32 00000000 .bss\n-000035e0 00000203 R_ARM_REL32 00000000 .bss\n-000036a4 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00003714 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-0000372c 0000a20a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-00003736 0000830a R_ARM_THM_CALL 00000000 free\n-00003746 0000a30a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-0000374c 0000830a R_ARM_THM_CALL 00000000 free\n-00003826 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00003892 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000038ae 0000a40a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-000038b8 0000830a R_ARM_THM_CALL 00000000 free\n-000038c8 0000a30a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-000038ce 0000830a R_ARM_THM_CALL 00000000 free\n-00003948 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000039c0 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000039d6 0000a40a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-000039e0 0000830a R_ARM_THM_CALL 00000000 free\n-000039f0 0000a30a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-000039f6 0000830a R_ARM_THM_CALL 00000000 free\n-00003b10 00000203 R_ARM_REL32 00000000 .bss\n-00003b14 00006b03 R_ARM_REL32 00000000 .rodata\n-00003b18 00000203 R_ARM_REL32 00000000 .bss\n-00003b1c 00000203 R_ARM_REL32 00000000 .bss\n-00003b20 00006b03 R_ARM_REL32 00000000 .rodata\n-00003b24 00000203 R_ARM_REL32 00000000 .bss\n-00003b28 00000203 R_ARM_REL32 00000000 .bss\n-00003b2c 00000203 R_ARM_REL32 00000000 .bss\n-00003b30 00000203 R_ARM_REL32 00000000 .bss\n-00003e50 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-00003eaa 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-00003eb8 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00003ed0 00000203 R_ARM_REL32 00000000 .bss\n-00003ed4 00000203 R_ARM_REL32 00000000 .bss\n-00003ed8 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003edc 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003ee0 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003ee4 00000203 R_ARM_REL32 00000000 .bss\n-00003ee8 00008e03 R_ARM_REL32 00005748 __gridxc_vdwxc_MOD_phi_table\n-00003eec 00006b03 R_ARM_REL32 00000000 .rodata\n-00003f10 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003f20 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003f44 00008c0a R_ARM_THM_CALL 00000000 memcpy\n-00003f62 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003f92 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003fa4 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003fb6 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00003fe0 00004703 R_ARM_REL32 000002d0 .LC31\n-00003fe4 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003fe8 00004803 R_ARM_REL32 000002d8 .LC32\n-00003fec 00000103 R_ARM_REL32 00000000 .data\n-00003ff0 00000103 R_ARM_REL32 00000000 .data\n-00003ff4 00004903 R_ARM_REL32 000002e0 .LC33\n-00003ff8 00000103 R_ARM_REL32 00000000 .data\n-00003ffc 00000103 R_ARM_REL32 00000000 .data\n-00004000 00004a03 R_ARM_REL32 000002e4 .LC34\n-00004004 00004b03 R_ARM_REL32 000002e8 .LC35\n-00004008 00003703 R_ARM_REL32 00000258 .LC21\n-0000400c 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00004010 00004c03 R_ARM_REL32 000002ec .LC36\n-000040aa 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000411e 0000890a R_ARM_THM_CALL 00000000 memset\n-000043f0 0000a80a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n-00004400 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004404 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004408 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000440c 00000103 R_ARM_REL32 00000000 .data\n-00004410 00003703 R_ARM_REL32 00000258 .LC21\n-00004414 00000203 R_ARM_REL32 00000000 .bss\n-00004418 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-0000441c 00005003 R_ARM_REL32 00000340 .LC38\n-00004420 00000203 R_ARM_REL32 00000000 .bss\n-00004424 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004428 00004f03 R_ARM_REL32 00000314 .LC37\n-000045ba 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004720 0000890a R_ARM_THM_CALL 00000000 memset\n-0000472a 0000890a R_ARM_THM_CALL 00000000 memset\n-000047b0 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000047c6 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000480c 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004820 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004834 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004848 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-0000485c 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004870 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004884 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004898 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000048ac 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-000048c0 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004952 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004980 00009a0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n-000049d6 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004a42 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004a68 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004aaa 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004ade 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004b20 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004b82 0000aa0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n-00004ba8 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004bac 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004bb0 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004bb4 00000103 R_ARM_REL32 00000000 .data\n-00004bb8 00000103 R_ARM_REL32 00000000 .data\n-00004bbc 00000103 R_ARM_REL32 00000000 .data\n-00004bc0 00005403 R_ARM_REL32 0000036c .LC40\n-00004bc4 00005503 R_ARM_REL32 00000370 .LC41\n-00004bc8 00000103 R_ARM_REL32 00000000 .data\n-00004bcc 00000103 R_ARM_REL32 00000000 .data\n-00004bd0 00005703 R_ARM_REL32 00000384 .LC44\n-00004bd4 00005803 R_ARM_REL32 00000388 .LC45\n-00004bd8 00004903 R_ARM_REL32 000002e0 .LC33\n-00004bdc 00005a03 R_ARM_REL32 00000394 .LC47\n-00004be0 00004a03 R_ARM_REL32 000002e4 .LC34\n-00004be4 00005c03 R_ARM_REL32 000003a0 .LC49\n-00004be8 00004b03 R_ARM_REL32 000002e8 .LC35\n-00004bec 00005d03 R_ARM_REL32 000003a4 .LC50\n-00004bf0 00003703 R_ARM_REL32 00000258 .LC21\n-00004bf4 00005e03 R_ARM_REL32 000003a8 .LC51\n-00004bf8 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00004bfc 00006003 R_ARM_REL32 000003b0 .LC53\n-00004c00 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004c04 00005603 R_ARM_REL32 00000374 .LC42\n-00004c08 00002f03 R_ARM_REL32 00000228 .LC19\n-00004c0c 00005903 R_ARM_REL32 0000038c .LC46\n-00004c10 00002f03 R_ARM_REL32 00000228 .LC19\n-00004c14 00005b03 R_ARM_REL32 00000398 .LC48\n-00004c18 00002f03 R_ARM_REL32 00000228 .LC19\n-00004c1c 00005903 R_ARM_REL32 0000038c .LC46\n-00004c20 00005f03 R_ARM_REL32 000003ac .LC52\n-00004c24 00004b03 R_ARM_REL32 000002e8 .LC35\n-00004c28 00002f03 R_ARM_REL32 00000228 .LC19\n-00004c2c 00004a03 R_ARM_REL32 000002e4 .LC34\n-00004c30 00002f03 R_ARM_REL32 00000228 .LC19\n-00004c88 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004cf2 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004d44 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-00004d94 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-00004ddc 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n-00004df4 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n-00004e2c 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004e40 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004e44 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004e48 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000000a6 00007e0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_n\n+000000d6 00007f0a R_ARM_THM_CALL 00000000 malloc\n+000000f6 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000104 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000112 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000120 00007f0a R_ARM_THM_CALL 00000000 malloc\n+0000012e 00007f0a R_ARM_THM_CALL 00000000 malloc\n+0000013c 00007f0a R_ARM_THM_CALL 00000000 malloc\n+0000014a 00007f0a R_ARM_THM_CALL 00000000 malloc\n+0000017c 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+0000018e 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+00000282 0000820a R_ARM_THM_CALL 00000000 exp\n+000002ae 0000830a R_ARM_THM_CALL 00000000 sincos\n+000002ee 0000820a R_ARM_THM_CALL 00000000 exp\n+0000030c 0000820a R_ARM_THM_CALL 00000000 exp\n+00000340 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000344 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000348 00006f03 R_ARM_REL32 00000000 .rodata\n+00000512 0000860a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n+00000522 0000860a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n+00000544 0000860a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n+0000055a 0000870a R_ARM_THM_CALL 00000000 free\n+00000560 0000870a R_ARM_THM_CALL 00000000 free\n+00000566 0000870a R_ARM_THM_CALL 00000000 free\n+0000056c 0000870a R_ARM_THM_CALL 00000000 free\n+00000572 0000870a R_ARM_THM_CALL 00000000 free\n+00000578 0000870a R_ARM_THM_CALL 00000000 free\n+0000057e 0000870a R_ARM_THM_CALL 00000000 free\n+00000584 0000870a R_ARM_THM_CALL 00000000 free\n+000005f6 0000820a R_ARM_THM_CALL 00000000 exp\n+0000063c 0000830a R_ARM_THM_CALL 00000000 sincos\n+000006b0 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000006b4 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000006e6 0000830a R_ARM_THM_CALL 00000000 sincos\n+0000072a 0000820a R_ARM_THM_CALL 00000000 exp\n+00000756 0000820a R_ARM_THM_CALL 00000000 exp\n+00000794 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007a2 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007b0 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007be 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007cc 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007da 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000007e2 0000890a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+000007e6 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000007f6 00008b0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00000804 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00000812 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00000818 00000503 R_ARM_REL32 00000044 .LC2\n+0000081c 00000603 R_ARM_REL32 00000060 .LC3\n+00000820 00000503 R_ARM_REL32 00000044 .LC2\n+00000824 00000603 R_ARM_REL32 00000060 .LC3\n+00000828 00000503 R_ARM_REL32 00000044 .LC2\n+0000082c 00000603 R_ARM_REL32 00000060 .LC3\n+00000830 00000503 R_ARM_REL32 00000044 .LC2\n+00000834 00000603 R_ARM_REL32 00000060 .LC3\n+00000838 00000503 R_ARM_REL32 00000044 .LC2\n+0000083c 00000603 R_ARM_REL32 00000060 .LC3\n+00000840 00000503 R_ARM_REL32 00000044 .LC2\n+00000844 00000603 R_ARM_REL32 00000060 .LC3\n+00000848 00000403 R_ARM_REL32 00000000 .LC1\n+0000084c 00000703 R_ARM_REL32 000000b4 .LC4\n+00000850 00000803 R_ARM_REL32 000000bc .LC5\n+00000854 00000903 R_ARM_REL32 000000e4 .LC6\n+00000858 00000503 R_ARM_REL32 00000044 .LC2\n+0000085c 00000603 R_ARM_REL32 00000060 .LC3\n+00000860 00000503 R_ARM_REL32 00000044 .LC2\n+00000864 00000603 R_ARM_REL32 00000060 .LC3\n+000008a6 00008c0a R_ARM_THM_CALL 00000000 log\n+000008e8 00008c0a R_ARM_THM_CALL 00000000 log\n+0000090a 0000820a R_ARM_THM_CALL 00000000 exp\n+00000938 00000103 R_ARM_REL32 00000000 .data\n+0000093c 00000203 R_ARM_REL32 00000000 .bss\n+00000992 00008d0a R_ARM_THM_CALL 00000000 memset\n+000009b2 00008e0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n+00000a14 00008c0a R_ARM_THM_CALL 00000000 log\n+00000b12 00008c0a R_ARM_THM_CALL 00000000 log\n+00000b34 0000820a R_ARM_THM_CALL 00000000 exp\n+00000b54 00008d0a R_ARM_THM_CALL 00000000 memset\n+00000b88 00000103 R_ARM_REL32 00000000 .data\n+00000b8c 00000203 R_ARM_REL32 00000000 .bss\n+00000b90 00006f03 R_ARM_REL32 00000000 .rodata\n+00000b94 00000203 R_ARM_REL32 00000000 .bss\n+00000b98 00000203 R_ARM_REL32 00000000 .bss\n+00000b9c 00000103 R_ARM_REL32 00000000 .data\n+00000ba0 00000203 R_ARM_REL32 00000000 .bss\n+00000ba4 00000103 R_ARM_REL32 00000000 .data\n+00000ba8 00000203 R_ARM_REL32 00000000 .bss\n+00000bac 00000203 R_ARM_REL32 00000000 .bss\n+00000bb0 00000203 R_ARM_REL32 00000000 .bss\n+00000c52 00007e0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_n\n+00000c80 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000ca2 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000cb0 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000cbe 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000ccc 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000cda 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000ce8 00007f0a R_ARM_THM_CALL 00000000 malloc\n+00000d1a 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00000d2c 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+00000da4 0000820a R_ARM_THM_CALL 00000000 exp\n+00000dd8 0000830a R_ARM_THM_CALL 00000000 sincos\n+00000e18 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000e1c 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000e20 00006f03 R_ARM_REL32 00000000 .rodata\n+00000e66 0000830a R_ARM_THM_CALL 00000000 sincos\n+00000eac 0000820a R_ARM_THM_CALL 00000000 exp\n+00000eb8 0000820a R_ARM_THM_CALL 00000000 exp\n+0000105c 0000860a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n+00001078 0000860a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_integral\n+0000108e 0000870a R_ARM_THM_CALL 00000000 free\n+00001094 0000870a R_ARM_THM_CALL 00000000 free\n+0000109a 0000870a R_ARM_THM_CALL 00000000 free\n+000010a0 0000870a R_ARM_THM_CALL 00000000 free\n+000010a6 0000870a R_ARM_THM_CALL 00000000 free\n+000010ac 0000870a R_ARM_THM_CALL 00000000 free\n+000010b2 0000870a R_ARM_THM_CALL 00000000 free\n+00001124 0000830a R_ARM_THM_CALL 00000000 sincos\n+00001158 0000820a R_ARM_THM_CALL 00000000 exp\n+000011b0 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000011b4 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000011c8 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000011d6 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000011e4 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+000011f2 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001200 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+0000120e 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+0000121c 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+0000122a 0000880a R_ARM_THM_CALL 00000000 _gfortran_os_error_at\n+00001232 0000890a R_ARM_THM_CALL 00000000 _gfortran_runtime_error\n+00001242 00008b0a R_ARM_THM_CALL 00000000 _gfortran_runtime_error_at\n+00001248 00000503 R_ARM_REL32 00000044 .LC2\n+0000124c 00001903 R_ARM_REL32 00000130 .LC9\n+00001250 00000503 R_ARM_REL32 00000044 .LC2\n+00001254 00001903 R_ARM_REL32 00000130 .LC9\n+00001258 00000503 R_ARM_REL32 00000044 .LC2\n+0000125c 00001903 R_ARM_REL32 00000130 .LC9\n+00001260 00000503 R_ARM_REL32 00000044 .LC2\n+00001264 00001903 R_ARM_REL32 00000130 .LC9\n+00001268 00000503 R_ARM_REL32 00000044 .LC2\n+0000126c 00001903 R_ARM_REL32 00000130 .LC9\n+00001270 00000503 R_ARM_REL32 00000044 .LC2\n+00001274 00001903 R_ARM_REL32 00000130 .LC9\n+00001278 00000503 R_ARM_REL32 00000044 .LC2\n+0000127c 00001903 R_ARM_REL32 00000130 .LC9\n+00001280 00000403 R_ARM_REL32 00000000 .LC1\n+00001284 00000703 R_ARM_REL32 000000b4 .LC4\n+00001288 00000803 R_ARM_REL32 000000bc .LC5\n+0000128c 00001a03 R_ARM_REL32 00000184 .LC10\n+0000140a 00008f0a R_ARM_THM_CALL 00000000 _gfortran_st_inquire\n+0000144e 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00001496 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+00001730 00002503 R_ARM_REL32 000001d0 .LC11\n+00001734 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001738 00002603 R_ARM_REL32 00000208 .LC12\n+0000173c 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001740 00006f03 R_ARM_REL32 00000000 .rodata\n+00001744 00000203 R_ARM_REL32 00000000 .bss\n+00001784 00008d0a R_ARM_THM_CALL 00000000 memset\n+000017a4 00008d0a R_ARM_THM_CALL 00000000 memset\n+000017c6 00008d0a R_ARM_THM_CALL 00000000 memset\n+000017ea 00008d0a R_ARM_THM_CALL 00000000 memset\n+00001812 00008d0a R_ARM_THM_CALL 00000000 memset\n+0000181c 00008d0a R_ARM_THM_CALL 00000000 memset\n+000019ba 0000900a R_ARM_THM_CALL 00000000 memcpy\n+00001bd6 0000910a R_ARM_THM_CALL 00000000 _gfortran_reshape_r8\n+00001cd8 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+00001cdc 00006f03 R_ARM_REL32 00000000 .rodata\n+00001ce0 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+00001ce4 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+00001ce8 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+00001f02 0000930a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+00001f22 0000940a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00001f30 0000950a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00001f36 0000960a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00001f52 0000940a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00001f8e 0000970a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+00001f94 0000960a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00001fb0 0000940a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00002002 0000970a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+00002008 0000960a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00002020 0000980a R_ARM_THM_CALL 00000000 _gfortran_st_close\n+00002092 0000930a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+000020a4 0000990a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+000020ae 00009a0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n+000020b4 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+000020e4 0000990a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+00002132 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_array\n+00002138 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+00002158 0000990a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+000021ac 00009c0a R_ARM_THM_CALL 00000000 _gfortran_transfer_array\n+000021b2 00009b0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+000021de 0000980a R_ARM_THM_CALL 00000000 _gfortran_st_close\n+000021e4 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000021e8 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+000021ec 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+000021f0 00002503 R_ARM_REL32 000001d0 .LC11\n+000021f4 00002603 R_ARM_REL32 00000208 .LC12\n+000021f8 00002703 R_ARM_REL32 0000021c .LC13\n+000021fc 00006f03 R_ARM_REL32 00000000 .rodata\n+00002200 00000203 R_ARM_REL32 00000000 .bss\n+00002204 00000203 R_ARM_REL32 00000000 .bss\n+00002208 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000220c 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002210 00002703 R_ARM_REL32 0000021c .LC13\n+00002214 00000203 R_ARM_REL32 00000000 .bss\n+00002218 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+0000221c 00002503 R_ARM_REL32 000001d0 .LC11\n+0000226c 00009d0a R_ARM_THM_CALL 00000000 cbrt\n+000022ae 00009e0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n+000023f6 0000820a R_ARM_THM_CALL 00000000 exp\n+000024c6 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002528 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000252c 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002530 00006f03 R_ARM_REL32 00000000 .rodata\n+00002534 00002f03 R_ARM_REL32 00000228 .LC19\n+00002538 00000103 R_ARM_REL32 00000000 .data\n+0000253c 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002618 0000820a R_ARM_THM_CALL 00000000 exp\n+00002720 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002724 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002728 00003303 R_ARM_REL32 00000230 .LC20\n+00002816 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00002904 00008d0a R_ARM_THM_CALL 00000000 memset\n+00002972 00008d0a R_ARM_THM_CALL 00000000 memset\n+00002b28 0000a20a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n+00002b7e 0000900a R_ARM_THM_CALL 00000000 memcpy\n+00002c80 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002c84 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00002c88 00000103 R_ARM_REL32 00000000 .data\n+00002c8c 00003703 R_ARM_REL32 00000258 .LC21\n+00002c90 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002d74 0000900a R_ARM_THM_CALL 00000000 memcpy\n+00002fc6 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+0000303e 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000030be 0000a40a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+000030e6 0000a40a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+0000310c 0000a40a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00003132 0000a40a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00003320 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003324 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003328 00000103 R_ARM_REL32 00000000 .data\n+0000332c 00003703 R_ARM_REL32 00000258 .LC21\n+00003330 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003334 00000203 R_ARM_REL32 00000000 .bss\n+00003338 00006f03 R_ARM_REL32 00000000 .rodata\n+0000333c 00000203 R_ARM_REL32 00000000 .bss\n+00003340 00003c03 R_ARM_REL32 0000025c .LC24\n+00003344 00003d03 R_ARM_REL32 00000270 .LC25\n+00003348 00003e03 R_ARM_REL32 00000284 .LC26\n+0000334c 00003f03 R_ARM_REL32 0000029c .LC27\n+00003350 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003354 00004003 R_ARM_REL32 000002b4 .LC28\n+00003358 00000203 R_ARM_REL32 00000000 .bss\n+0000335c 00000203 R_ARM_REL32 00000000 .bss\n+00003360 00000203 R_ARM_REL32 00000000 .bss\n+00003364 00000203 R_ARM_REL32 00000000 .bss\n+00003426 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+0000349c 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000034b6 0000a60a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+000034c0 0000870a R_ARM_THM_CALL 00000000 free\n+000034d2 0000a70a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+000034d8 0000870a R_ARM_THM_CALL 00000000 free\n+000035a0 00000203 R_ARM_REL32 00000000 .bss\n+000035a4 00006f03 R_ARM_REL32 00000000 .rodata\n+000035a8 00000203 R_ARM_REL32 00000000 .bss\n+000035ac 00000203 R_ARM_REL32 00000000 .bss\n+000035b0 00000203 R_ARM_REL32 00000000 .bss\n+00003676 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000036ec 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00003704 0000a60a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+0000370e 0000870a R_ARM_THM_CALL 00000000 free\n+00003720 0000a70a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00003726 0000870a R_ARM_THM_CALL 00000000 free\n+000037ee 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00003868 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00003884 0000a80a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+0000388e 0000870a R_ARM_THM_CALL 00000000 free\n+000038a0 0000a70a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+000038a6 0000870a R_ARM_THM_CALL 00000000 free\n+00003940 00000203 R_ARM_REL32 00000000 .bss\n+00003944 00006f03 R_ARM_REL32 00000000 .rodata\n+00003948 00000203 R_ARM_REL32 00000000 .bss\n+0000394c 00000203 R_ARM_REL32 00000000 .bss\n+00003950 00006f03 R_ARM_REL32 00000000 .rodata\n+00003954 00000203 R_ARM_REL32 00000000 .bss\n+00003958 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000039da 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000039f0 0000a80a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+000039fa 0000870a R_ARM_THM_CALL 00000000 free\n+00003a0c 0000a70a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00003a12 0000870a R_ARM_THM_CALL 00000000 free\n+00003e42 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00003e8e 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+00003e9a 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00003ea0 00000203 R_ARM_REL32 00000000 .bss\n+00003ea4 00000203 R_ARM_REL32 00000000 .bss\n+00003ea8 00000203 R_ARM_REL32 00000000 .bss\n+00003eac 00000203 R_ARM_REL32 00000000 .bss\n+00003eb0 00000203 R_ARM_REL32 00000000 .bss\n+00003eb4 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003eb8 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003ebc 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003ec0 00009203 R_ARM_REL32 00005738 __gridxc_vdwxc_MOD_phi_table\n+00003ec4 00006f03 R_ARM_REL32 00000000 .rodata\n+00003ee8 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003ef8 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003f1c 0000900a R_ARM_THM_CALL 00000000 memcpy\n+00003f3a 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003f6a 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003f7c 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003f8e 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00003fb8 00004903 R_ARM_REL32 000002d0 .LC31\n+00003fbc 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003fc0 00004a03 R_ARM_REL32 000002d8 .LC32\n+00003fc4 00000103 R_ARM_REL32 00000000 .data\n+00003fc8 00000103 R_ARM_REL32 00000000 .data\n+00003fcc 00004b03 R_ARM_REL32 000002e0 .LC33\n+00003fd0 00000103 R_ARM_REL32 00000000 .data\n+00003fd4 00000103 R_ARM_REL32 00000000 .data\n+00003fd8 00004c03 R_ARM_REL32 000002e4 .LC34\n+00003fdc 00004d03 R_ARM_REL32 000002e8 .LC35\n+00003fe0 00003703 R_ARM_REL32 00000258 .LC21\n+00003fe4 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00003fe8 00004e03 R_ARM_REL32 000002ec .LC36\n+00004086 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000040fe 00008d0a R_ARM_THM_CALL 00000000 memset\n+000043d0 0000ac0a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n+000043e0 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000043e4 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000043e8 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000043ec 00000103 R_ARM_REL32 00000000 .data\n+000043f0 00003703 R_ARM_REL32 00000258 .LC21\n+000043f4 00000203 R_ARM_REL32 00000000 .bss\n+000043f8 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000043fc 00005203 R_ARM_REL32 00000340 .LC38\n+00004400 00000203 R_ARM_REL32 00000000 .bss\n+00004404 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004408 00005103 R_ARM_REL32 00000314 .LC37\n+000045b0 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004712 00008d0a R_ARM_THM_CALL 00000000 memset\n+0000471c 00008d0a R_ARM_THM_CALL 00000000 memset\n+0000479c 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000047b0 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000047f6 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000480a 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000481e 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004832 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004846 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000485a 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000486e 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004882 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004896 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000048aa 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+0000493c 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+0000496a 00009e0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_ldaxc\n+000049c0 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+000049f8 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000049fc 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004a00 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004a04 00000103 R_ARM_REL32 00000000 .data\n+00004a08 00000103 R_ARM_REL32 00000000 .data\n+00004a0c 00000103 R_ARM_REL32 00000000 .data\n+00004a10 00005603 R_ARM_REL32 0000036c .LC40\n+00004a14 00005703 R_ARM_REL32 00000370 .LC41\n+00004a18 00000103 R_ARM_REL32 00000000 .data\n+00004a1c 00000103 R_ARM_REL32 00000000 .data\n+00004a20 00005903 R_ARM_REL32 00000384 .LC44\n+00004a24 00005a03 R_ARM_REL32 00000388 .LC45\n+00004a28 00004b03 R_ARM_REL32 000002e0 .LC33\n+00004a2c 00005c03 R_ARM_REL32 00000394 .LC47\n+00004a30 00004c03 R_ARM_REL32 000002e4 .LC34\n+00004a34 00005e03 R_ARM_REL32 000003a0 .LC49\n+00004a38 00004d03 R_ARM_REL32 000002e8 .LC35\n+00004a3c 00005f03 R_ARM_REL32 000003a4 .LC50\n+00004a40 00003703 R_ARM_REL32 00000258 .LC21\n+00004a44 00006003 R_ARM_REL32 000003a8 .LC51\n+00004a48 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00004a4c 00006203 R_ARM_REL32 000003b0 .LC53\n+00004a50 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004a54 00005803 R_ARM_REL32 00000374 .LC42\n+00004a58 00002f03 R_ARM_REL32 00000228 .LC19\n+00004a5c 00005b03 R_ARM_REL32 0000038c .LC46\n+00004a60 00002f03 R_ARM_REL32 00000228 .LC19\n+00004aa0 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00004ac6 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004b08 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00004b3c 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00004b7e 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00004be0 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_gga_MOD_ggaxc\n+00004c08 00005d03 R_ARM_REL32 00000398 .LC48\n+00004c0c 00002f03 R_ARM_REL32 00000228 .LC19\n+00004c10 00005b03 R_ARM_REL32 0000038c .LC46\n+00004c14 00006103 R_ARM_REL32 000003ac .LC52\n+00004c18 00004d03 R_ARM_REL32 000002e8 .LC35\n+00004c1c 00002f03 R_ARM_REL32 00000228 .LC19\n+00004c20 00004c03 R_ARM_REL32 000002e4 .LC34\n+00004c24 00002f03 R_ARM_REL32 00000228 .LC19\n+00004c7c 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004ce8 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004d3e 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00004d90 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+00004dd8 0000b00a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n+00004df0 0000b00a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n+00004e28 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004e2c 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e30 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004e34 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e38 00000103 R_ARM_REL32 00000000 .data\n+00004e3c 00003703 R_ARM_REL32 00000258 .LC21\n+00004e40 00000203 R_ARM_REL32 00000000 .bss\n+00004e44 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e48 00000203 R_ARM_REL32 00000000 .bss\n 00004e4c 00000103 R_ARM_REL32 00000000 .data\n 00004e50 00003703 R_ARM_REL32 00000258 .LC21\n 00004e54 00000203 R_ARM_REL32 00000000 .bss\n-00004e58 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004e5c 00000203 R_ARM_REL32 00000000 .bss\n-00004e60 00000103 R_ARM_REL32 00000000 .data\n-00004e64 00003703 R_ARM_REL32 00000258 .LC21\n-00004e68 00000203 R_ARM_REL32 00000000 .bss\n-00004e6c 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004e70 00006b03 R_ARM_REL32 00000000 .rodata\n-00004e74 00000203 R_ARM_REL32 00000000 .bss\n-00004e78 00000203 R_ARM_REL32 00000000 .bss\n-00004e7c 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004e80 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00004e84 00006203 R_ARM_REL32 000003d4 .LC54\n-00004efc 00009d0a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00004fb6 0000890a R_ARM_THM_CALL 00000000 memset\n-000050ac 0000ae0a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n-0000512a 0000890a R_ARM_THM_CALL 00000000 memset\n-000051bc 0000890a R_ARM_THM_CALL 00000000 memset\n-00005318 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-0000538e 0000a10a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000053aa 0000af0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_evaluate_spline_dx\n-000053b6 0000830a R_ARM_THM_CALL 00000000 free\n-000053c0 0000830a R_ARM_THM_CALL 00000000 free\n-00005428 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000542c 0000811a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00005430 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005434 00000103 R_ARM_REL32 00000000 .data\n-00005438 00003703 R_ARM_REL32 00000258 .LC21\n-0000543c 00000203 R_ARM_REL32 00000000 .bss\n-00005440 00000203 R_ARM_REL32 00000000 .bss\n-00005444 00008019 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00005448 00000203 R_ARM_REL32 00000000 .bss\n-0000544c 00000203 R_ARM_REL32 00000000 .bss\n-00005450 00006b03 R_ARM_REL32 00000000 .rodata\n-00005454 00000203 R_ARM_REL32 00000000 .bss\n-00005458 00000203 R_ARM_REL32 00000000 .bss\n-0000545c 00000203 R_ARM_REL32 00000000 .bss\n-00005460 00000203 R_ARM_REL32 00000000 .bss\n-00005464 00000203 R_ARM_REL32 00000000 .bss\n-00005468 00000203 R_ARM_REL32 00000000 .bss\n-0000546c 00006b03 R_ARM_REL32 00000000 .rodata\n-00005488 00007c0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-000054c4 00007d0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-0000550e 0000860a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00005514 00009b1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00005518 00006503 R_ARM_REL32 0000040c .LC55\n-00000aea 0000891e R_ARM_THM_JUMP24 00000000 memset\n-00003c52 0000a51e R_ARM_THM_JUMP24 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n-00003f54 0000891e R_ARM_THM_JUMP24 00000000 memset\n-00004ce0 00008c1e R_ARM_THM_JUMP24 00000000 memcpy\n+00004e58 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e5c 00006f03 R_ARM_REL32 00000000 .rodata\n+00004e60 00000203 R_ARM_REL32 00000000 .bss\n+00004e64 00000203 R_ARM_REL32 00000000 .bss\n+00004e68 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004e6c 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00004e70 00006603 R_ARM_REL32 000003d4 .LC54\n+00004edc 0000a10a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00004f92 00008d0a R_ARM_THM_CALL 00000000 memset\n+0000508a 0000b20a R_ARM_THM_CALL 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n+0000510e 00008d0a R_ARM_THM_CALL 00000000 memset\n+00005198 00008d0a R_ARM_THM_CALL 00000000 memset\n+00005250 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005254 0000851a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00005258 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000525c 00000103 R_ARM_REL32 00000000 .data\n+00005260 00003703 R_ARM_REL32 00000258 .LC21\n+00005264 00000203 R_ARM_REL32 00000000 .bss\n+00005268 00000203 R_ARM_REL32 00000000 .bss\n+0000526c 00008419 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00005270 00000203 R_ARM_REL32 00000000 .bss\n+00005274 00000203 R_ARM_REL32 00000000 .bss\n+00005278 00000203 R_ARM_REL32 00000000 .bss\n+0000527c 00000203 R_ARM_REL32 00000000 .bss\n+00005280 00006f03 R_ARM_REL32 00000000 .rodata\n+00005284 00000203 R_ARM_REL32 00000000 .bss\n+00005288 00000203 R_ARM_REL32 00000000 .bss\n+0000528c 00000203 R_ARM_REL32 00000000 .bss\n+0000533a 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000053a2 0000a50a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000053ba 0000b30a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_evaluate_spline_dx\n+000053c6 0000870a R_ARM_THM_CALL 00000000 free\n+000053d0 0000870a R_ARM_THM_CALL 00000000 free\n+00005424 0000800a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00005466 0000810a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+000054a2 00008a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000054a8 00000203 R_ARM_REL32 00000000 .bss\n+000054ac 00006f03 R_ARM_REL32 00000000 .rodata\n+000054b0 00009f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000054b4 00006903 R_ARM_REL32 0000040c .LC55\n+00000b68 00008d1e R_ARM_THM_JUMP24 00000000 memset\n+00003c42 0000a91e R_ARM_THM_JUMP24 00000000 __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n+00003f2c 00008d1e R_ARM_THM_JUMP24 00000000 memset\n+00004cd6 0000901e R_ARM_THM_JUMP24 00000000 memcpy\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,23 +1,20 @@\n-&+xDuY!F\n-)I*F)HyDxD\n-(I*F(HyDxD\n-&I*F&HyDxD\n-%I*F%HyDxD\n-#I*F#HyDxD\n- J I!HzDyDxD\n-,L}D|D+h\n- +,YxD1F\n-bvK{D+dO\n-jK$!jHxD\n+#I\"F#HyDxD\n+!I\"F!HyDxD\n+ I\"F HyDxD\n+.L}D|D+h\n+EJ)Foa F\n+hK$!hHxD\n+D<7-h=`O\n HBF9F[FxD\n -K\"F)F{D\n K(h{D*y\n-)K+!,HxD\n-##`XJNKzD\n+(K+!+HxD\n+dK !:hdH\n+##`VJKKzD\n Integer overflow when calculating the amount of memory to allocate\n Error allocating %lu bytes\n In file '/build/reproducible-path/libgridxc-2.0.1/src/vdwxc.F90', around line 492\n Attempt to DEALLOCATE unallocated '%s'\n At line 560 of file /build/reproducible-path/libgridxc-2.0.1/src/vdwxc.F90\n In file '/build/reproducible-path/libgridxc-2.0.1/src/vdwxc.F90', around line 850\n At line 906 of file /build/reproducible-path/libgridxc-2.0.1/src/vdwxc.F90\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -5,815 +5,845 @@\n \n 00000000 <__gridxc_vdwxc_MOD_dphi.isra.0>:\n __gridxc_vdwxc_MOD_dphi.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3784]\t@ 0xec8\n-\tvabs.f64\td11, d0\n-\tvabs.f64\td21, d1\n-\tvldr\td16, [pc, #736]\t@ 300 <__gridxc_vdwxc_MOD_dphi.isra.0+0x300>\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td17, #62\t@ 0x41f00000 30.0\n-\tvldr\td19, [pc, #732]\t@ 308 <__gridxc_vdwxc_MOD_dphi.isra.0+0x308>\n-\tldr\tr6, [pc, #760]\t@ (328 <__gridxc_vdwxc_MOD_dphi.isra.0+0x328>)\n-\tvmov.f64\td20, #36\t@ 0x41200000 10.0\n-\tvmaxnm.f64\td11, d11, d21\n-\tldr\tr5, [pc, #756]\t@ (32c <__gridxc_vdwxc_MOD_dphi.isra.0+0x32c>)\n-\tsub\tsp, #212\t@ 0xd4\n-\tadd\tr6, pc\n-\tldr\tr0, [pc, #752]\t@ (330 <__gridxc_vdwxc_MOD_dphi.isra.0+0x330>)\n-\tadd\tr4, sp, #136\t@ 0x88\n-\tadd\tr3, sp, #152\t@ 0x98\n-\tadd\tr2, sp, #144\t@ 0x90\n-\tvmul.f64\td16, d11, d16\n-\tvmul.f64\td17, d11, d17\n-\tvstr\td18, [sp, #152]\t@ 0x98\n+\tstr.w\tr0, [ip, #3760]\t@ 0xeb0\n+\tvabs.f64\td9, d0\n+\tvabs.f64\td2, d1\n+\tvmov.f64\td6, #62\t@ 0x41f00000 30.0\n+\tvmov.f64\td3, #36\t@ 0x41200000 10.0\n+\tvldr\td7, [pc, #760]\t@ 320 <__gridxc_vdwxc_MOD_dphi.isra.0+0x320>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td4, [pc, #760]\t@ 328 <__gridxc_vdwxc_MOD_dphi.isra.0+0x328>\n+\tsub\tsp, #236\t@ 0xec\n+\tvcmpe.f64\td9, d2\n+\tldr\tr5, [pc, #776]\t@ (340 <__gridxc_vdwxc_MOD_dphi.isra.0+0x340>)\n+\tldr\tr4, [pc, #776]\t@ (344 <__gridxc_vdwxc_MOD_dphi.isra.0+0x344>)\n+\tadd\tr7, sp, #160\t@ 0xa0\n+\tadd\tr5, pc\n+\tldr\tr0, [pc, #776]\t@ (348 <__gridxc_vdwxc_MOD_dphi.isra.0+0x348>)\n+\tvstr\td5, [sp, #176]\t@ 0xb0\n+\tadd\tr3, sp, #176\t@ 0xb0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tadd\tr2, sp, #168\t@ 0xa8\n+\tldr\tr4, [r5, r4]\n \tadd\tr0, pc\n-\tldr\tr5, [r6, r5]\n-\tmov\tr1, r4\n-\tvmov.f64\td10, d0\n+\tmov\tr1, r7\n+\tvmov.f64\td11, d0\n+\tldr\tr4, [r4, #0]\n+\tstr\tr4, [sp, #228]\t@ 0xe4\n+\tmov.w\tr4, #0\n \tvmov.f64\td8, d1\n-\tvminnm.f64\td16, d16, d18\n-\tvmaxnm.f64\td17, d17, d20\n-\tldr\tr5, [r5, #0]\n-\tstr\tr5, [sp, #204]\t@ 0xcc\n-\tmov.w\tr5, #0\n-\tvmaxnm.f64\td16, d16, d19\n-\tvstr\td17, [sp, #136]\t@ 0x88\n-\tvstr\td16, [sp, #144]\t@ 0x90\n+\tmov.w\tr4, #0\n+\tit\tlt\n+\tvmovlt.f64\td9, d2\n+\tvmul.f64\td6, d9, d6\n+\tvmul.f64\td7, d9, d7\n+\tvcmpe.f64\td6, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td7, d5\n+\tit\tlt\n+\tvmovlt.f64\td6, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td6, [sp, #160]\t@ 0xa0\n+\tit\thi\n+\tvmovhi.f64\td7, d5\n+\tvcmpe.f64\td7, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d4\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n \tbl\t0 <__gridxc_mesh1d_MOD_get_n>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_n\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmovs\tr3, #8\n-\tcmp.w\tr0, #536870912\t@ 0x20000000\n-\tstr\tr3, [sp, #176]\t@ 0xb0\n-\tstr\tr0, [sp, #128]\t@ 0x80\n+\tmovs\tr2, #8\n+\tstrd\tr4, r4, [sp, #204]\t@ 0xcc\n \tmovw\tr3, #769\t@ 0x301\n-\tvstr\td16, [sp, #180]\t@ 0xb4\n-\tstrh.w\tr3, [sp, #184]\t@ 0xb8\n-\tbge.w\t74e <__gridxc_vdwxc_MOD_dphi.isra.0+0x74e>\n-\tcmp\tr0, #0\n+\tcmp.w\tr0, #536870912\t@ 0x20000000\n+\tstr\tr0, [sp, #152]\t@ 0x98\n+\tstr\tr2, [sp, #200]\t@ 0xc8\n+\tstrh.w\tr3, [sp, #208]\t@ 0xd0\n+\tbge.w\t7de <__gridxc_vdwxc_MOD_dphi.isra.0+0x7de>\n+\tcmp\tr0, r4\n \tmov\tr6, r0\n-\tit\tgt\n-\tlslgt\tr5, r0, #3\n-\tit\tgt\n-\tmovgt\tr8, r5\n-\tbgt.n\tb0 <__gridxc_vdwxc_MOD_dphi.isra.0+0xb0>\n+\titt\tgt\n+\tlslgt\tr4, r0, #3\n+\tmovgt\tr8, r4\n+\tbgt.n\td4 <__gridxc_vdwxc_MOD_dphi.isra.0+0xd4>\n \tmov.w\tr8, #1\n-\tmovs\tr5, #0\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #168]\t@ 0xa8\n+\tstr\tr0, [sp, #192]\t@ 0xc0\n \tcmp\tr0, #0\n-\tbeq.w\t740 <__gridxc_vdwxc_MOD_dphi.isra.0+0x740>\n-\tvldr\td16, [pc, #592]\t@ 310 <__gridxc_vdwxc_MOD_dphi.isra.0+0x310>\n-\tadd\tr3, sp, #188\t@ 0xbc\n+\tbeq.w\t7d0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7d0>\n \tmov\tr0, r8\n-\tmovs\tr7, #1\n-\tstrd\tr7, r6, [sp, #196]\t@ 0xc4\n-\tvst1.32\t{d16}, [r3]\n+\tmovs\tr5, #1\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [sp, #172]\t@ 0xac\n+\tstrd\tr5, r6, [sp, #220]\t@ 0xdc\n+\tstr\tr3, [sp, #196]\t@ 0xc4\n+\tmovs\tr3, #8\n+\tstr\tr5, [sp, #216]\t@ 0xd8\n+\tstr\tr3, [sp, #212]\t@ 0xd4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #36]\t@ 0x24\n+\tstr\tr0, [sp, #88]\t@ 0x58\n \tcmp\tr0, #0\n-\tbeq.w\t732 <__gridxc_vdwxc_MOD_dphi.isra.0+0x732>\n+\tbeq.w\t7c2 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7c2>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #64]\t@ 0x40\n+\tstr\tr0, [sp, #112]\t@ 0x70\n \tcmp\tr0, #0\n-\tbeq.w\t724 <__gridxc_vdwxc_MOD_dphi.isra.0+0x724>\n+\tbeq.w\t7b4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7b4>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #96]\t@ 0x60\n+\tstr\tr0, [sp, #120]\t@ 0x78\n \tcmp\tr0, #0\n-\tbeq.w\t716 <__gridxc_vdwxc_MOD_dphi.isra.0+0x716>\n+\tbeq.w\t7a6 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7a6>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #20]\n+\tstr\tr0, [sp, #72]\t@ 0x48\n \tcmp\tr0, #0\n-\tbeq.w\t708 <__gridxc_vdwxc_MOD_dphi.isra.0+0x708>\n+\tbeq.w\t798 <__gridxc_vdwxc_MOD_dphi.isra.0+0x798>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #24]\n+\tstr\tr0, [sp, #76]\t@ 0x4c\n \tcmp\tr0, #0\n-\tbeq.w\t778 <__gridxc_vdwxc_MOD_dphi.isra.0+0x778>\n+\tbeq.w\t808 <__gridxc_vdwxc_MOD_dphi.isra.0+0x808>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #40]\t@ 0x28\n+\tstr\tr0, [sp, #92]\t@ 0x5c\n \tcmp\tr0, #0\n-\tbeq.w\t76a <__gridxc_vdwxc_MOD_dphi.isra.0+0x76a>\n+\tbeq.w\t7fa <__gridxc_vdwxc_MOD_dphi.isra.0+0x7fa>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n+\tstr\tr0, [sp, #96]\t@ 0x60\n \tcmp\tr0, #0\n-\tbeq.w\t786 <__gridxc_vdwxc_MOD_dphi.isra.0+0x786>\n-\tvldr\td18, [sp, #152]\t@ 0x98\n-\tadd\tr0, sp, #128\t@ 0x80\n-\tvldr\td17, [sp, #144]\t@ 0x90\n-\tmov\tr3, r4\n+\tbeq.w\t78a <__gridxc_vdwxc_MOD_dphi.isra.0+0x78a>\n+\tvldr\td5, [sp, #176]\t@ 0xb0\n \tmovs\tr4, #0\n-\tadd\tr2, sp, #160\t@ 0xa0\n-\tmov\tr5, r0\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tadd\tr0, sp, #152\t@ 0x98\n+\tmov\tr3, r7\n+\tadd\tr2, sp, #184\t@ 0xb8\n+\tmov\tr7, r0\n \tmov\tr1, r4\n-\tvdiv.f64\td16, d18, d17\n-\tstr\tr2, [sp, #100]\t@ 0x64\n+\tvdiv.f64\td7, d5, d6\n+\tstr\tr2, [sp, #124]\t@ 0x7c\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r4\n \tstr\tr4, [sp, #0]\n-\tstr\tr0, [sp, #48]\t@ 0x30\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n+\tstr\tr0, [sp, #100]\t@ 0x64\n+\tvstr\td7, [sp, #184]\t@ 0xb8\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n \tmov\tr3, r4\n-\tadd\tr2, sp, #168\t@ 0xa8\n-\tadd\tr1, sp, #132\t@ 0x84\n-\tmov\tr0, r5\n+\tadd\tr2, sp, #192\t@ 0xc0\n+\tadd\tr1, sp, #156\t@ 0x9c\n+\tmov\tr0, r7\n \tstrd\tr4, r4, [sp, #4]\n \tstr\tr4, [sp, #0]\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n \tsubs\tr3, r6, #1\n \tcmp\tr3, r4\n-\tstr\tr6, [sp, #160]\t@ 0xa0\n-\tble.w\t6e6 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6e6>\n-\tldrd\tr2, r1, [sp, #168]\t@ 0xa8\n-\tvmov.f64\td17, #4\t@ 0x40200000 2.5\n-\tstr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr6, [sp, #184]\t@ 0xb8\n+\tble.w\t764 <__gridxc_vdwxc_MOD_dphi.isra.0+0x764>\n+\tldrd\tr2, r1, [sp, #192]\t@ 0xc0\n+\tvmov.f64\td6, #4\t@ 0x40200000 2.5\n+\tstr\tr2, [sp, #116]\t@ 0x74\n \tmov\tr0, r6\n \tmov\tr4, r2\n \tadds\tr2, r6, r1\n-\tvmul.f64\td17, d11, d17\n+\tvmul.f64\td6, d9, d6\n \tadd.w\tr2, r4, r2, lsl #3\n-\tvldmdb\tr2!, {d16}\n-\tvcmp.f64\td17, d16\n+\tvldmdb\tr2!, {d7}\n+\tvcmp.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tit\tmi\n \tmovmi\tr0, r3\n \tsubs\tr3, #1\n-\tbne.n\t194 <__gridxc_vdwxc_MOD_dphi.isra.0+0x194>\n+\tbne.n\t1b4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x1b4>\n \tmovs\tr3, #1\n-\tstr\tr0, [sp, #32]\n-\tstr\tr0, [sp, #160]\t@ 0xa0\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tvcmpe.f64\td11, #0.0\n-\tvmul.f64\td14, d11, d11\n-\tvmul.f64\td13, d10, d10\n-\tvdiv.f64\td17, d9, d10\n+\tstr\tr0, [sp, #84]\t@ 0x54\n+\tstr\tr0, [sp, #184]\t@ 0xb8\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tvmul.f64\td14, d9, d9\n+\tvmul.f64\td13, d11, d11\n \tvmul.f64\td12, d8, d8\n-\tvldr\td16, [pc, #332]\t@ 318 <__gridxc_vdwxc_MOD_dphi.isra.0+0x318>\n+\tvldr\td7, [pc, #336]\t@ 330 <__gridxc_vdwxc_MOD_dphi.isra.0+0x330>\n+\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n+\tvcmpe.f64\td9, #0.0\n+\tvmul.f64\td14, d14, d7\n+\tvmul.f64\td13, d13, d7\n+\tvmul.f64\td7, d12, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td14, d14, d16\n-\tvmul.f64\td13, d13, d16\n-\tvmul.f64\td16, d12, d16\n-\tvstr\td16, [sp, #56]\t@ 0x38\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvdiv.f64\td17, d9, d8\n-\tvstr\td17, [sp, #88]\t@ 0x58\n-\tbls.w\t554 <__gridxc_vdwxc_MOD_dphi.isra.0+0x554>\n-\tvdiv.f64\td16, d9, d11\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tvstr\td7, [sp, #32]\n+\tvdiv.f64\td7, d10, d11\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvdiv.f64\td7, d10, d8\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tbls.w\t5ac <__gridxc_vdwxc_MOD_dphi.isra.0+0x5ac>\n+\tvdiv.f64\td7, d10, d9\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \tadds\tr1, #1\n-\tldr.w\tfp, [sp, #36]\t@ 0x24\n-\tldr.w\tsl, [sp, #20]\n+\tldr.w\tfp, [sp, #88]\t@ 0x58\n+\tldr.w\tsl, [sp, #72]\t@ 0x48\n \tmovs\tr5, #0\n \tadd.w\tr4, r3, r1, lsl #3\n-\tldr.w\tr9, [sp, #44]\t@ 0x2c\n-\tadd\tr3, sp, #112\t@ 0x70\n-\tldr.w\tr8, [sp, #24]\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tadd\tr3, sp, #104\t@ 0x68\n-\tldr\tr7, [sp, #40]\t@ 0x28\n-\tvldr\td11, [pc, #264]\t@ 320 <__gridxc_vdwxc_MOD_dphi.isra.0+0x320>\n-\tstr\tr3, [sp, #28]\n-\tvstr\td16, [sp, #80]\t@ 0x50\n-\tb.n\t282 <__gridxc_vdwxc_MOD_dphi.isra.0+0x282>\n-\tvcmp.f64\td10, #0.0\n-\tvmul.f64\td15, d12, d12\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td15, d15, d16\n-\tbne.n\t2dc <__gridxc_vdwxc_MOD_dphi.isra.0+0x2dc>\n-\tvmov.f64\td18, d15\n+\tldr.w\tr9, [sp, #96]\t@ 0x60\n+\tadd\tr3, sp, #136\t@ 0x88\n+\tldr.w\tr8, [sp, #76]\t@ 0x4c\n+\tstr\tr3, [sp, #24]\n+\tadd\tr3, sp, #128\t@ 0x80\n+\tldr\tr7, [sp, #92]\t@ 0x5c\n+\tvldr\td9, [pc, #256]\t@ 338 <__gridxc_vdwxc_MOD_dphi.isra.0+0x338>\n+\tstr\tr3, [sp, #16]\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tb.n\t2a2 <__gridxc_vdwxc_MOD_dphi.isra.0+0x2a2>\n+\tvcmp.f64\td11, #0.0\n+\tvmul.f64\td12, d15, d15\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td12, d12, d7\n+\tbne.n\t2fc <__gridxc_vdwxc_MOD_dphi.isra.0+0x2fc>\n+\tvmov.f64\td5, d12\n \tvcmp.f64\td8, #0.0\n-\tvstr\td18, [r7]\n+\tvstr\td5, [r7]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t2be <__gridxc_vdwxc_MOD_dphi.isra.0+0x2be>\n-\tvmov.f64\td18, d15\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvstr\td18, [r9]\n-\tvmul.f64\td16, d12, d16\n-\tvmul.f64\td16, d16, d16\n-\tvnmul.f64\td0, d11, d16\n+\tbne.n\t2de <__gridxc_vdwxc_MOD_dphi.isra.0+0x2de>\n+\tvmov.f64\td5, d12\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvstr\td5, [r9]\n+\tvmul.f64\td7, d15, d7\n+\tvmul.f64\td7, d7, d7\n+\tvnmul.f64\td0, d9, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n-\tvdiv.f64\td16, d15, d0\n-\tvstr\td16, [r8]\n+\tvsub.f64\td0, d10, d0\n+\tvdiv.f64\td7, d12, d0\n+\tvstr\td7, [r8]\n \tadds\tr5, #1\n \tadd.w\tr9, r9, #8\n \tadd.w\tr8, r8, #8\n \tadds\tr7, #8\n \tcmp\tr6, r5\n-\tbeq.n\t334 <__gridxc_vdwxc_MOD_dphi.isra.0+0x334>\n-\tvldmia\tr4!, {d12}\n-\tldr\tr1, [sp, #28]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tvmov.f64\td0, d12\n+\tbeq.n\t34c <__gridxc_vdwxc_MOD_dphi.isra.0+0x34c>\n+\tvldmia\tr4!, {d15}\n+\tldr\tr1, [sp, #16]\n+\tldr\tr0, [sp, #24]\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvcmp.f64\td12, #0.0\n-\tldrd\tr0, r1, [sp, #104]\t@ 0x68\n-\tldrd\tr2, r3, [sp, #112]\t@ 0x70\n+\tvcmp.f64\td15, #0.0\n+\tldrd\tr0, r1, [sp, #128]\t@ 0x80\n+\tldrd\tr2, r3, [sp, #136]\t@ 0x88\n \tvmrs\tAPSR_nzcv, fpscr\n \tstrd\tr0, r1, [fp], #8\n \tstrd\tr2, r3, [sl], #8\n-\tbne.n\t222 <__gridxc_vdwxc_MOD_dphi.isra.0+0x222>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n+\tbne.n\t242 <__gridxc_vdwxc_MOD_dphi.isra.0+0x242>\n+\tvldr\td7, [sp, #32]\n \tvstr\td14, [r8]\n \tvstr\td13, [r7]\n-\tvstr\td16, [r9]\n-\tb.n\t272 <__gridxc_vdwxc_MOD_dphi.isra.0+0x272>\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvmul.f64\td0, d12, d16\n+\tvstr\td7, [r9]\n+\tb.n\t292 <__gridxc_vdwxc_MOD_dphi.isra.0+0x292>\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvmul.f64\td0, d15, d7\n \tvmul.f64\td0, d0, d0\n-\tvnmul.f64\td0, d11, d0\n+\tvnmul.f64\td0, d9, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n-\tvdiv.f64\td18, d15, d0\n-\tb.n\t24e <__gridxc_vdwxc_MOD_dphi.isra.0+0x24e>\n-\tvldr\td16, [sp, #72]\t@ 0x48\n-\tvmul.f64\td0, d12, d16\n+\tvsub.f64\td0, d10, d0\n+\tvdiv.f64\td5, d12, d0\n+\tb.n\t26e <__gridxc_vdwxc_MOD_dphi.isra.0+0x26e>\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvmul.f64\td0, d15, d7\n \tvmul.f64\td0, d0, d0\n-\tvnmul.f64\td0, d11, d0\n+\tvnmul.f64\td0, d9, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n-\tvdiv.f64\td18, d15, d0\n-\tb.n\t23c <__gridxc_vdwxc_MOD_dphi.isra.0+0x23c>\n+\tvsub.f64\td0, d10, d0\n+\tvdiv.f64\td5, d12, d0\n+\tb.n\t25c <__gridxc_vdwxc_MOD_dphi.isra.0+0x25c>\n \tnop\n \tnop.w\n \t.word\t0x9999999a\n \t.word\t0x3fb99999\n \t.word\t0x47ae147b\n \t.word\t0x3f847ae1\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n \t.word\t0x7b830193\n \t.word\t0x3fd6eb16\n \t.word\t0x4ae74487\n \t.word\t0x3ff65718\n-\t.word\t0x000002ea\n+\t.word\t0x00000300\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002dc\n+\t.word\t0x000002f6\n R_ARM_REL32\t.rodata\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvmov.i64\td15, #0x0000000000000000\n+\tldr\tr3, [sp, #112]\t@ 0x70\n \tmovs\tr5, #2\n-\tstr\tr5, [sp, #124]\t@ 0x7c\n-\tvstr\td15, [r3]\n-\tldr\tr3, [sp, #32]\n+\tvldr\td7, [pc, #836]\t@ 698 <__gridxc_vdwxc_MOD_dphi.isra.0+0x698>\n+\tstr\tr5, [sp, #148]\t@ 0x94\n+\tvstr\td7, [r3]\n+\tldr\tr3, [sp, #84]\t@ 0x54\n \tcmp\tr3, #1\n-\tble.w\t4e4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x4e4>\n-\tldr\tr3, [sp, #172]\t@ 0xac\n+\tble.w\t53c <__gridxc_vdwxc_MOD_dphi.isra.0+0x53c>\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n \tmovs\tr4, #8\n-\tldr\tr2, [sp, #68]\t@ 0x44\n-\tvmov.f64\td8, #8\t@ 0x40400000 3.0\n+\tldr\tr2, [sp, #116]\t@ 0x74\n \tadds\tr3, #2\n-\tstr\tr6, [sp, #28]\n-\tldr\tr6, [sp, #96]\t@ 0x60\n+\tstr\tr6, [sp, #80]\t@ 0x50\n+\tldr\tr6, [sp, #120]\t@ 0x78\n \tadd.w\tr7, r2, r3, lsl #3\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tstr\tr7, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr7, [sp, #108]\t@ 0x6c\n \tadd.w\tr8, r3, #8\n-\tadd\tr3, sp, #124\t@ 0x7c\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr\tr3, [sp, #28]\n-\tvldmia\tr7!, {d4}\n+\tadd\tr3, sp, #148\t@ 0x94\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tvldr\td7, [pc, #792]\t@ 698 <__gridxc_vdwxc_MOD_dphi.isra.0+0x698>\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tvldmia\tr7!, {d15}\n \tcmp\tr3, #1\n-\tvstr\td15, [r6]\n-\tbeq.w\t4b2 <__gridxc_vdwxc_MOD_dphi.isra.0+0x4b2>\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tvmul.f64\td2, d4, d4\n-\tldr\tr1, [sp, #40]\t@ 0x28\n-\tvmov.f64\td22, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [r6]\n+\tbeq.w\t50a <__gridxc_vdwxc_MOD_dphi.isra.0+0x50a>\n+\tvmul.f64\td7, d15, d15\n+\tvmov.f64\td6, #8\t@ 0x40400000 3.0\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n \tadds\tr3, r2, r4\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tadd.w\tsl, r2, #8\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tvsub.f64\td5, d6, d7\n+\tvstr\td7, [sp, #24]\n+\tvsub.f64\td7, d7, d6\n \tadd.w\tip, r0, #8\n-\tvsub.f64\td9, d8, d2\n-\tvldr\td12, [r3]\n-\tadds\tr3, r1, r4\n-\tvsub.f64\td10, d2, d8\n+\tadd.w\tsl, r2, #8\n+\tldr\tr2, [sp, #108]\t@ 0x6c\n \tadd.w\tlr, r1, #8\n+\tvstr\td5, [sp, #32]\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tvldr\td7, [r3]\n+\tadds\tr3, r1, r4\n \tadd.w\tr1, r6, #8\n-\tvmov.f64\td1, #96\t@ 0x3f000000 0.5\n-\tvldr\td28, [r3]\n+\tvldr\td11, [r3]\n \tadds\tr3, r0, r4\n-\tvmul.f64\td11, d4, d12\n-\tvmul.f64\td12, d12, d8\n-\tvmov.f64\td0, #80\t@ 0x3e800000 0.250\n-\tvldr\td27, [r3]\n-\tldr\tr3, [sp, #20]\n+\tvmul.f64\td5, d15, d7\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td12, [r3]\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvadd.f64\td7, d11, d12\n \tadd\tr3, r4\n-\tvadd.f64\td13, d28, d27\n-\tvldr\td14, [r3]\n-\tldr\tr3, [sp, #24]\n+\tvstr\td5, [sp, #16]\n+\tvstr\td7, [sp, #48]\t@ 0x30\n+\tvldr\td7, [r3]\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tadd\tr3, r4\n-\tvldr\td29, [r3]\n-\tldr\tr3, [sp, #20]\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td13, [r3]\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tadd.w\tr9, r3, #8\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tadd.w\tr0, r3, #8\n-\tldr\tr3, [sp, #28]\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tadd.w\tfp, r3, #1\n \tmovs\tr3, #2\n-\tvldmia\tr0!, {d19}\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tlr!, {d24}\n+\tvldmia\tsl!, {d4}\n \tcmp\tr3, fp\n-\tvldmia\tip!, {d21}\n-\tvadd.f64\td23, d29, d19\n-\tvmul.f64\td19, d29, d19\n-\tvadd.f64\td26, d24, d27\n-\tvldmia\tr2!, {d18}\n-\tvadd.f64\td25, d24, d21\n-\tvadd.f64\td24, d28, d24\n-\tvldmia\tsl!, {d16}\n-\tvadd.f64\td6, d28, d21\n-\tvmul.f64\td7, d23, d23\n-\tvmul.f64\td17, d18, d18\n-\tvdiv.f64\td30, d0, d19\n-\tvldmia\tr9!, {d3}\n-\tvdiv.f64\td19, d22, d24\n-\tvmul.f64\td5, d18, d16\n-\tvmul.f64\td18, d4, d18\n-\tvmul.f64\td16, d16, d12\n-\tvdiv.f64\td24, d22, d7\n-\tvadd.f64\td20, d17, d10\n-\tvmul.f64\td31, d11, d3\n-\tvsub.f64\td7, d8, d17\n-\tvadd.f64\td21, d27, d21\n-\tvmul.f64\td26, d6, d26\n-\tvnmul.f64\td16, d18, d16\n-\tvmul.f64\td25, d25, d13\n-\tvmul.f64\td20, d20, d3\n-\tvmul.f64\td17, d2, d17\n-\tvfma.f64\td20, d5, d9\n-\tvfma.f64\td16, d7, d31\n-\tvdiv.f64\td3, d22, d21\n-\tvmul.f64\td21, d18, d18\n-\tvdiv.f64\td31, d22, d26\n-\tvdiv.f64\td26, d22, d25\n-\tvmul.f64\td21, d21, d18\n-\tvfma.f64\td16, d20, d14\n-\tvadd.f64\td16, d16, d16\n-\tvdiv.f64\td18, d16, d21\n-\tvadd.f64\td24, d30, d24\n-\tvdiv.f64\td16, d24, d23\n-\tvadd.f64\td19, d19, d3\n-\tvadd.f64\td26, d31, d26\n-\tvmul.f64\td19, d19, d1\n-\tvfnms.f64\td16, d26, d19\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td17, d17, d18\n-\tvstmia\tr1!, {d17}\n-\tbne.n\t3ec <__gridxc_vdwxc_MOD_dphi.isra.0+0x3ec>\n+\tvldr\td3, [sp, #64]\t@ 0x40\n+\tvmul.f64\td8, d7, d7\n+\tvmul.f64\td0, d15, d7\n+\tvmul.f64\td7, d7, d4\n+\tvldmia\tr0!, {d2}\n+\tvmul.f64\td4, d4, d3\n+\tvmov.f64\td3, #80\t@ 0x3e800000 0.250\n+\tvldmia\tlr!, {d5}\n+\tvldmia\tip!, {d6}\n+\tvmul.f64\td9, d4, d0\n+\tvadd.f64\td4, d13, d2\n+\tvmul.f64\td2, d13, d2\n+\tvmul.f64\td1, d4, d4\n+\tvdiv.f64\td3, d3, d2\n+\tvdiv.f64\td2, d14, d1\n+\tvadd.f64\td3, d3, d2\n+\tvdiv.f64\td1, d3, d4\n+\tvldr\td4, [sp, #56]\t@ 0x38\n+\tvldr\td3, [sp, #32]\n+\tvadd.f64\td10, d8, d4\n+\tvldmia\tr9!, {d4}\n+\tvmul.f64\td10, d10, d4\n+\tvmla.f64\td10, d7, d3\n+\tvldr\td7, [sp, #16]\n+\tvadd.f64\td3, d11, d6\n+\tvmul.f64\td4, d7, d4\n+\tvadd.f64\td7, d5, d12\n+\tvmul.f64\td7, d3, d7\n+\tvadd.f64\td3, d5, d6\n+\tvadd.f64\td5, d11, d5\n+\tvadd.f64\td6, d12, d6\n+\tvdiv.f64\td2, d14, d7\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvmul.f64\td3, d3, d7\n+\tvdiv.f64\td7, d14, d5\n+\tvdiv.f64\td5, d14, d6\n+\tvdiv.f64\td6, d14, d3\n+\tvadd.f64\td7, d7, d5\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvadd.f64\td6, d2, d6\n+\tvmul.f64\td7, d7, d5\n+\tvnmls.f64\td1, d6, d7\n+\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n+\tvsub.f64\td7, d7, d8\n+\tvnmls.f64\td9, d7, d4\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvmla.f64\td9, d10, d7\n+\tvldr\td7, [sp, #24]\n+\tvmul.f64\td8, d7, d8\n+\tvmul.f64\td7, d0, d0\n+\tvmul.f64\td7, d7, d0\n+\tvmul.f64\td8, d1, d8\n+\tvadd.f64\td9, d9, d9\n+\tvdiv.f64\td6, d9, d7\n+\tvmul.f64\td8, d8, d6\n+\tvstmia\tr1!, {d8}\n+\tbne.n\t41c <__gridxc_vdwxc_MOD_dphi.isra.0+0x41c>\n \tmovs\tr3, #0\n-\tldr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr0, [sp, #100]\t@ 0x64\n \tmov\tr2, r3\n \tmov\tr1, r6\n \tbl\t0 <__gridxc_mesh1d_MOD_integral>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_integral\n-\tvmov.f64\td9, d0\n+\tvmov.f64\td8, d0\n \tmovs\tr3, #0\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tldr\tr0, [sp, #104]\t@ 0x68\n \tmov\tr2, r3\n \tmov\tr1, r6\n \tbl\t0 <__gridxc_mesh1d_MOD_integral>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_integral\n-\tldr\tr3, [sp, #32]\n-\tvsub.f64\td9, d9, d0\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tvsub.f64\td8, d8, d0\n \tadds\tr5, #1\n \tadds\tr4, #8\n \tcmp\tr5, r3\n-\tstr\tr5, [sp, #124]\t@ 0x7c\n-\tvstmia\tr8!, {d9}\n-\tble.w\t36a <__gridxc_vdwxc_MOD_dphi.isra.0+0x36a>\n+\tstr\tr5, [sp, #148]\t@ 0x94\n+\tvstmia\tr8!, {d8}\n+\tble.w\t37e <__gridxc_vdwxc_MOD_dphi.isra.0+0x37e>\n \tmovs\tr3, #0\n-\tldr\tr0, [sp, #100]\t@ 0x64\n+\tldr\tr0, [sp, #124]\t@ 0x7c\n \tmov\tr2, r3\n-\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr\tr1, [sp, #112]\t@ 0x70\n \tbl\t0 <__gridxc_mesh1d_MOD_integral>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_integral\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvldr\td8, [pc, #676]\t@ 798 <__gridxc_vdwxc_MOD_dphi.isra.0+0x798>\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tvldr\td8, [pc, #340]\t@ 6a0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6a0>\n \tvmul.f64\td8, d0, d8\n \tcmp\tr3, #0\n-\tbeq.w\t75a <__gridxc_vdwxc_MOD_dphi.isra.0+0x75a>\n+\tbeq.w\t7ea <__gridxc_vdwxc_MOD_dphi.isra.0+0x7ea>\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #36]\t@ 0x24\n+\tldr\tr0, [sp, #88]\t@ 0x58\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #64]\t@ 0x40\n+\tldr\tr0, [sp, #112]\t@ 0x70\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #96]\t@ 0x60\n+\tldr\tr0, [sp, #120]\t@ 0x78\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #20]\n+\tldr\tr0, [sp, #72]\t@ 0x48\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #24]\n+\tldr\tr0, [sp, #76]\t@ 0x4c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #628]\t@ (7a8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7a8>)\n-\tldr\tr3, [pc, #632]\t@ (7ac <__gridxc_vdwxc_MOD_dphi.isra.0+0x7ac>)\n+\tldr\tr2, [pc, #292]\t@ (6b0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6b0>)\n+\tldr\tr3, [pc, #296]\t@ (6b4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6b4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #204]\t@ 0xcc\n+\tldr\tr3, [sp, #228]\t@ 0xe4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t756 <__gridxc_vdwxc_MOD_dphi.isra.0+0x756>\n+\tbne.w\t7e6 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7e6>\n \tvmov.f64\td0, d8\n-\tadd\tsp, #212\t@ 0xd4\n+\tadd\tsp, #236\t@ 0xec\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvcmp.f64\td10, #0.0\n+\tvcmp.f64\td11, #0.0\n \tadds\tr1, #1\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t614 <__gridxc_vdwxc_MOD_dphi.isra.0+0x614>\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tbeq.n\t66c <__gridxc_vdwxc_MOD_dphi.isra.0+0x66c>\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \tmovs\tr5, #0\n-\tldr.w\tsl, [sp, #36]\t@ 0x24\n+\tldr.w\tsl, [sp, #88]\t@ 0x58\n \tvmov.f64\td12, #96\t@ 0x3f000000 0.5\n-\tldrd\tfp, r9, [sp, #20]\n+\tldrd\tfp, r9, [sp, #72]\t@ 0x48\n \tadd.w\tr4, r3, r1, lsl #3\n-\tldrd\tr8, r7, [sp, #40]\t@ 0x28\n-\tadd\tr3, sp, #112\t@ 0x70\n-\tvldr\td10, [pc, #548]\t@ 7a0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7a0>\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tadd\tr3, sp, #104\t@ 0x68\n-\tstr\tr3, [sp, #28]\n-\tb.n\t5d8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x5d8>\n-\tvldr\td16, [sp, #72]\t@ 0x48\n+\tldrd\tr8, r7, [sp, #92]\t@ 0x5c\n+\tadd\tr3, sp, #136\t@ 0x88\n+\tvldr\td9, [pc, #212]\t@ 6a8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6a8>\n+\tstr\tr3, [sp, #24]\n+\tadd\tr3, sp, #128\t@ 0x80\n+\tstr\tr3, [sp, #16]\n+\tb.n\t630 <__gridxc_vdwxc_MOD_dphi.isra.0+0x630>\n+\tvldr\td7, [sp, #40]\t@ 0x28\n \tvmul.f64\td11, d15, d15\n-\tvmul.f64\td0, d16, d15\n+\tvmul.f64\td0, d7, d15\n \tvmul.f64\td11, d11, d12\n \tvmul.f64\td0, d0, d0\n-\tvnmul.f64\td0, d10, d0\n+\tvnmul.f64\td0, d9, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n+\tvsub.f64\td0, d10, d0\n \tvcmp.f64\td8, #0.0\n-\tvdiv.f64\td18, d11, d0\n+\tvdiv.f64\td4, d11, d0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvstr\td18, [r8]\n-\tbne.w\t6c8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6c8>\n-\tvmov.f64\td17, d11\n-\tvstr\td17, [r7]\n+\tvstr\td4, [r8]\n+\tbne.w\t746 <__gridxc_vdwxc_MOD_dphi.isra.0+0x746>\n+\tvmov.f64\td7, d11\n+\tvstr\td7, [r7]\n \tvstr\td11, [r9]\n \tadds\tr5, #1\n \tadd.w\tr9, r9, #8\n \tadd.w\tr8, r8, #8\n \tadds\tr7, #8\n \tcmp\tr6, r5\n-\tbeq.w\t334 <__gridxc_vdwxc_MOD_dphi.isra.0+0x334>\n+\tbeq.w\t34c <__gridxc_vdwxc_MOD_dphi.isra.0+0x34c>\n \tvldmia\tr4!, {d15}\n-\tldr\tr1, [sp, #28]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tldr\tr1, [sp, #16]\n+\tldr\tr0, [sp, #24]\n \tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n \tvcmp.f64\td15, #0.0\n-\tldrd\tr0, r1, [sp, #104]\t@ 0x68\n-\tldrd\tr2, r3, [sp, #112]\t@ 0x70\n+\tldrd\tr0, r1, [sp, #128]\t@ 0x80\n+\tldrd\tr2, r3, [sp, #136]\t@ 0x88\n \tvmrs\tAPSR_nzcv, fpscr\n \tstrd\tr0, r1, [sl], #8\n \tstrd\tr2, r3, [fp], #8\n-\tbne.n\t586 <__gridxc_vdwxc_MOD_dphi.isra.0+0x586>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n+\tbne.n\t5de <__gridxc_vdwxc_MOD_dphi.isra.0+0x5de>\n+\tvldr\td7, [sp, #32]\n \tvstr\td14, [r9]\n \tvstr\td13, [r8]\n-\tvstr\td16, [r7]\n-\tb.n\t5c6 <__gridxc_vdwxc_MOD_dphi.isra.0+0x5c6>\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tvstr\td7, [r7]\n+\tb.n\t61e <__gridxc_vdwxc_MOD_dphi.isra.0+0x61e>\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \tmovs\tr5, #0\n-\tldr.w\tr9, [sp, #36]\t@ 0x24\n-\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n-\tldrd\tr8, fp, [sp, #20]\n+\tldr.w\tr9, [sp, #88]\t@ 0x58\n+\tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n+\tldrd\tr8, fp, [sp, #72]\t@ 0x48\n \tadd.w\tr4, r3, r1, lsl #3\n-\tldrd\tsl, r7, [sp, #40]\t@ 0x28\n-\tadd\tr3, sp, #112\t@ 0x70\n-\tvldr\td12, [pc, #368]\t@ 7a0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7a0>\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tadd\tr3, sp, #104\t@ 0x68\n-\tstr\tr3, [sp, #28]\n-\tb.n\t65c <__gridxc_vdwxc_MOD_dphi.isra.0+0x65c>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n+\tldrd\tsl, r7, [sp, #92]\t@ 0x5c\n+\tadd\tr3, sp, #136\t@ 0x88\n+\tvldr\td12, [pc, #32]\t@ 6a8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6a8>\n+\tstr\tr3, [sp, #24]\n+\tadd\tr3, sp, #128\t@ 0x80\n+\tstr\tr3, [sp, #16]\n+\tb.n\t6da <__gridxc_vdwxc_MOD_dphi.isra.0+0x6da>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x6222c720\n+\t.word\t0x3fd9f02f\n+\t.word\t0x4ae74487\n+\t.word\t0x3ff65718\n+\t.word\t0x00000120\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\tvldr\td7, [sp, #32]\n \tvstr\td14, [fp]\n \tvstr\td13, [sl]\n-\tvstr\td16, [r7]\n+\tvstr\td7, [r7]\n \tadds\tr5, #1\n \tadd.w\tfp, fp, #8\n \tadd.w\tsl, sl, #8\n \tadds\tr7, #8\n \tcmp\tr5, r6\n-\tbeq.w\t334 <__gridxc_vdwxc_MOD_dphi.isra.0+0x334>\n-\tvldmia\tr4!, {d15}\n-\tldr\tr1, [sp, #28]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tvmov.f64\td0, d15\n+\tbeq.w\t34c <__gridxc_vdwxc_MOD_dphi.isra.0+0x34c>\n+\tvldmia\tr4!, {d11}\n+\tldr\tr1, [sp, #16]\n+\tldr\tr0, [sp, #24]\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvcmp.f64\td15, #0.0\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tldrd\tr0, r1, [sp, #112]\t@ 0x70\n+\tvcmp.f64\td11, #0.0\n+\tvldr\td6, [sp, #128]\t@ 0x80\n+\tldrd\tr0, r1, [sp, #136]\t@ 0x88\n \tstrd\tr0, r1, [r8], #8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvstmia\tr9!, {d16}\n-\tbeq.n\t63a <__gridxc_vdwxc_MOD_dphi.isra.0+0x63a>\n+\tvstmia\tr9!, {d6}\n+\tbeq.n\t6b8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6b8>\n \tvcmp.f64\td8, #0.0\n-\tvmul.f64\td11, d15, d15\n+\tvmul.f64\td15, d11, d11\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td11, d11, d10\n-\tvstr\td11, [sl]\n-\tbeq.n\t6c2 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6c2>\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvmul.f64\td15, d15, d16\n-\tvmul.f64\td15, d15, d15\n-\tvnmul.f64\td0, d12, d15\n+\tvmul.f64\td15, d15, d9\n+\tvstr\td15, [sl]\n+\tbeq.n\t740 <__gridxc_vdwxc_MOD_dphi.isra.0+0x740>\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d11, d7\n+\tvmul.f64\td7, d7, d7\n+\tvnmul.f64\td0, d12, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n-\tvdiv.f64\td17, d11, d0\n-\tvstr\td17, [r7]\n-\tvstr\td11, [fp]\n-\tb.n\t64a <__gridxc_vdwxc_MOD_dphi.isra.0+0x64a>\n-\tvmov.f64\td17, d11\n-\tb.n\t6b8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6b8>\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvmul.f64\td15, d16, d15\n-\tvmul.f64\td15, d15, d15\n-\tvnmul.f64\td0, d10, d15\n+\tvsub.f64\td0, d10, d0\n+\tvdiv.f64\td7, d15, d0\n+\tvstr\td7, [r7]\n+\tvstr\td15, [fp]\n+\tb.n\t6c8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x6c8>\n+\tvmov.f64\td7, d15\n+\tb.n\t736 <__gridxc_vdwxc_MOD_dphi.isra.0+0x736>\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d7, d15\n+\tvmul.f64\td7, d7, d7\n+\tvnmul.f64\td0, d9, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td0, d9, d0\n-\tvdiv.f64\td17, d11, d0\n-\tb.n\t5be <__gridxc_vdwxc_MOD_dphi.isra.0+0x5be>\n-\tldr\tr3, [sp, #168]\t@ 0xa8\n+\tvsub.f64\td0, d10, d0\n+\tvdiv.f64\td7, d11, d0\n+\tb.n\t616 <__gridxc_vdwxc_MOD_dphi.isra.0+0x616>\n \tcmp\tr6, #1\n-\tstr\tr7, [sp, #124]\t@ 0x7c\n-\tstr\tr3, [sp, #68]\t@ 0x44\n-\tbeq.n\t700 <__gridxc_vdwxc_MOD_dphi.isra.0+0x700>\n-\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tit\teq\n+\tmoveq\tr3, #1\n+\tstr\tr5, [sp, #148]\t@ 0x94\n+\titt\teq\n+\tldreq\tr1, [sp, #196]\t@ 0xc4\n+\tstreq\tr3, [sp, #84]\t@ 0x54\n+\tbeq.w\t1d0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x1d0>\n+\tldr\tr1, [sp, #112]\t@ 0x70\n \tmovs\tr3, #2\n \tmovs\tr2, #0\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #148]\t@ 0x94\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\t4e4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x4e4>\n-\tmovs\tr3, #1\n-\tldr\tr1, [sp, #172]\t@ 0xac\n-\tstr\tr3, [sp, #32]\n-\tb.n\t1b0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x1b0>\n-\tldr\tr1, [pc, #164]\t@ (7b0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7b0>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #164]\t@ (7b4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7b4>)\n+\tb.n\t53c <__gridxc_vdwxc_MOD_dphi.isra.0+0x53c>\n+\tldr\tr1, [pc, #140]\t@ (818 <__gridxc_vdwxc_MOD_dphi.isra.0+0x818>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #140]\t@ (81c <__gridxc_vdwxc_MOD_dphi.isra.0+0x81c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #160]\t@ (7b8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7b8>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #160]\t@ (7bc <__gridxc_vdwxc_MOD_dphi.isra.0+0x7bc>)\n+\tldr\tr1, [pc, #132]\t@ (820 <__gridxc_vdwxc_MOD_dphi.isra.0+0x820>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #132]\t@ (824 <__gridxc_vdwxc_MOD_dphi.isra.0+0x824>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #152]\t@ (7c0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7c0>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #152]\t@ (7c4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7c4>)\n+\tldr\tr1, [pc, #128]\t@ (828 <__gridxc_vdwxc_MOD_dphi.isra.0+0x828>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #128]\t@ (82c <__gridxc_vdwxc_MOD_dphi.isra.0+0x82c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #148]\t@ (7c8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7c8>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #148]\t@ (7cc <__gridxc_vdwxc_MOD_dphi.isra.0+0x7cc>)\n+\tldr\tr1, [pc, #120]\t@ (830 <__gridxc_vdwxc_MOD_dphi.isra.0+0x830>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #120]\t@ (834 <__gridxc_vdwxc_MOD_dphi.isra.0+0x834>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #140]\t@ (7d0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7d0>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #140]\t@ (7d4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7d4>)\n+\tldr\tr1, [pc, #116]\t@ (838 <__gridxc_vdwxc_MOD_dphi.isra.0+0x838>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #116]\t@ (83c <__gridxc_vdwxc_MOD_dphi.isra.0+0x83c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #136]\t@ (7d8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7d8>)\n+\tldr\tr1, [pc, #108]\t@ (840 <__gridxc_vdwxc_MOD_dphi.isra.0+0x840>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #108]\t@ (844 <__gridxc_vdwxc_MOD_dphi.isra.0+0x844>)\n+\tadd\tr1, pc\n+\tadd\tr0, pc\n+\tbl\t0 <_gfortran_os_error_at>\n+ R_ARM_THM_CALL\t_gfortran_os_error_at\n+\tldr\tr0, [pc, #104]\t@ (848 <__gridxc_vdwxc_MOD_dphi.isra.0+0x848>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr2, [pc, #128]\t@ (7dc <__gridxc_vdwxc_MOD_dphi.isra.0+0x7dc>)\n-\tldr\tr1, [pc, #128]\t@ (7e0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7e0>)\n-\tldr\tr0, [pc, #132]\t@ (7e4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7e4>)\n+\tldr\tr2, [pc, #96]\t@ (84c <__gridxc_vdwxc_MOD_dphi.isra.0+0x84c>)\n+\tldr\tr1, [pc, #96]\t@ (850 <__gridxc_vdwxc_MOD_dphi.isra.0+0x850>)\n+\tldr\tr0, [pc, #100]\t@ (854 <__gridxc_vdwxc_MOD_dphi.isra.0+0x854>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\tldr\tr1, [pc, #124]\t@ (7e8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7e8>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #124]\t@ (7ec <__gridxc_vdwxc_MOD_dphi.isra.0+0x7ec>)\n-\tadd\tr1, pc\n-\tadd\tr0, pc\n-\tbl\t0 <_gfortran_os_error_at>\n- R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #116]\t@ (7f0 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7f0>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #116]\t@ (7f4 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7f4>)\n+\tldr\tr1, [pc, #92]\t@ (858 <__gridxc_vdwxc_MOD_dphi.isra.0+0x858>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #92]\t@ (85c <__gridxc_vdwxc_MOD_dphi.isra.0+0x85c>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #112]\t@ (7f8 <__gridxc_vdwxc_MOD_dphi.isra.0+0x7f8>)\n-\tmov\tr2, r5\n-\tldr\tr0, [pc, #112]\t@ (7fc <__gridxc_vdwxc_MOD_dphi.isra.0+0x7fc>)\n+\tldr\tr1, [pc, #84]\t@ (860 <__gridxc_vdwxc_MOD_dphi.isra.0+0x860>)\n+\tmov\tr2, r4\n+\tldr\tr0, [pc, #84]\t@ (864 <__gridxc_vdwxc_MOD_dphi.isra.0+0x864>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tnop.w\n-\t.word\t0x6222c720\n-\t.word\t0x3fd9f02f\n-\t.word\t0x4ae74487\n-\t.word\t0x3ff65718\n-\t.word\t0x00000270\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000009e\n+\tnop\n+\t.word\t0x00000084\n R_ARM_REL32\t.LC2\n-\t.word\t0x000000a0\n+\t.word\t0x00000086\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000098\n+\t.word\t0x0000007e\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000009a\n+\t.word\t0x00000080\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000092\n+\t.word\t0x00000078\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000094\n+\t.word\t0x0000007a\n R_ARM_REL32\t.LC3\n-\t.word\t0x0000008c\n+\t.word\t0x00000072\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000008e\n+\t.word\t0x00000074\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000086\n+\t.word\t0x0000006c\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000088\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000084\n+\t.word\t0x00000066\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x00000068\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x00000064\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000078\n+\t.word\t0x00000058\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000007a\n+\t.word\t0x0000005a\n R_ARM_REL32\t.LC5\n-\t.word\t0x0000007c\n+\t.word\t0x0000005c\n R_ARM_REL32\t.LC6\n-\t.word\t0x00000074\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000076\n- R_ARM_REL32\t.LC3\n-\t.word\t0x0000006e\n+\t.word\t0x00000054\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000070\n+\t.word\t0x00000056\n R_ARM_REL32\t.LC3\n-\t.word\t0x00000068\n+\t.word\t0x0000004e\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000006a\n+\t.word\t0x00000050\n R_ARM_REL32\t.LC3\n \n-00000800 <__gridxc_vdwxc_MOD_iofd.isra.0>:\n+00000868 <__gridxc_vdwxc_MOD_iofd.isra.0>:\n __gridxc_vdwxc_MOD_iofd.isra.0():\n \tpush\t{r3, r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n-\tldr\tr5, [pc, #180]\t@ (8c8 <__gridxc_vdwxc_MOD_iofd.isra.0+0xc8>)\n+\tldr\tr5, [pc, #188]\t@ (938 <__gridxc_vdwxc_MOD_iofd.isra.0+0xd0>)\n \tvmov.f64\td8, d0\n-\tldr\tr4, [pc, #176]\t@ (8cc <__gridxc_vdwxc_MOD_iofd.isra.0+0xcc>)\n+\tldr\tr4, [pc, #184]\t@ (93c <__gridxc_vdwxc_MOD_iofd.isra.0+0xd4>)\n \tadd\tr5, pc\n \tadd\tr4, pc\n \tldr\tr3, [r5, #0]\n \tvldr\td10, [r4]\n-\tcbnz\tr3, 864 <__gridxc_vdwxc_MOD_iofd.isra.0+0x64>\n-\tvldr\td16, [r4, #160]\t@ 0xa0\n+\tcbnz\tr3, 8cc <__gridxc_vdwxc_MOD_iofd.isra.0+0x64>\n+\tvldr\td7, [r4, #160]\t@ 0xa0\n \tvldr\td9, [r4, #168]\t@ 0xa8\n \tvsub.f64\td8, d8, d10\n \tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td0, d8, d16\n+\tvdiv.f64\td0, d8, d7\n \tvadd.f64\td0, d0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvdiv.f64\td16, d0, d9\n-\tvadd.f64\td16, d16, d10\n+\tvdiv.f64\td7, d0, d9\n+\tvadd.f64\td7, d7, d10\n \tvpop\t{d8-d11}\n-\tvcvt.s32.f64\ts15, d16\n+\tvcvt.s32.f64\ts15, d7\n \tvmov\tr0, s15\n \tcmp\tr0, #1\n \tit\tlt\n \tmovlt\tr0, #1\n \tcmp\tr0, #19\n \tit\tge\n \tmovge\tr0, #19\n \tpop\t{r3, r4, r5, pc}\n-\tvldr\td16, [r4, #144]\t@ 0x90\n+\tvldr\td7, [r4, #144]\t@ 0x90\n \tvldr\td11, [r4, #8]\n \tvldr\td0, [r4, #152]\t@ 0x98\n-\tvldr\td9, [pc, #68]\t@ 8b8 <__gridxc_vdwxc_MOD_iofd.isra.0+0xb8>\n+\tvldr\td9, [pc, #76]\t@ 928 <__gridxc_vdwxc_MOD_iofd.isra.0+0xc0>\n \tvsub.f64\td11, d11, d10\n-\tvsub.f64\td0, d0, d16\n+\tvsub.f64\td0, d0, d7\n \tvdiv.f64\td0, d0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n \tvmul.f64\td9, d0, d9\n-\tvldr\td16, [pc, #52]\t@ 8c0 <__gridxc_vdwxc_MOD_iofd.isra.0+0xc0>\n-\tvmaxnm.f64\td9, d9, d16\n+\tvldr\td7, [pc, #60]\t@ 930 <__gridxc_vdwxc_MOD_iofd.isra.0+0xc8>\n+\tvcmpe.f64\td9, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td9, d7\n \tvmov.f64\td0, d9\n \tvstr\td9, [r4, #168]\t@ 0xa8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tmovs\tr3, #0\n \tstr\tr3, [r5, #0]\n-\tvsub.f64\td0, d0, d16\n-\tvdiv.f64\td16, d11, d0\n-\tvstr\td16, [r4, #160]\t@ 0xa0\n-\tb.n\t82e <__gridxc_vdwxc_MOD_iofd.isra.0+0x2e>\n-\tnop\n+\tvsub.f64\td0, d0, d7\n+\tvdiv.f64\td7, d11, d0\n+\tvstr\td7, [r4, #160]\t@ 0xa0\n+\tb.n\t896 <__gridxc_vdwxc_MOD_iofd.isra.0+0x2e>\n \tnop.w\n \t.word\t0x1c71c71c\n \t.word\t0x3fac71c7\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x000000aa\n+\t.word\t0x000000b2\n R_ARM_REL32\t.data\n-\t.word\t0x000000ac\n+\t.word\t0x000000b4\n R_ARM_REL32\t.bss\n \n-000008d0 <__gridxc_vdwxc_MOD_pofq>:\n+00000940 <__gridxc_vdwxc_MOD_pofq>:\n __gridxc_vdwxc_MOD_pofq():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n+\tvpush\t{d8-d14}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4008]\t@ 0xfa8\n-\tldr\tr3, [pc, #544]\t@ (b08 <__gridxc_vdwxc_MOD_pofq+0x238>)\n+\tstr.w\tr0, [ip, #3984]\t@ 0xf90\n+\tldr\tr3, [pc, #560]\t@ (b88 <__gridxc_vdwxc_MOD_pofq+0x248>)\n \tsub\tsp, #20\n \tmov\tfp, r0\n \tadd\tr3, pc\n \tstrd\tr1, r2, [sp, #8]\n \tldr\tr3, [r3, #4]\n-\tcbz\tr3, 954 <__gridxc_vdwxc_MOD_pofq+0x84>\n-\tldr\tr4, [pc, #532]\t@ (b0c <__gridxc_vdwxc_MOD_pofq+0x23c>)\n+\tcbz\tr3, 9c4 <__gridxc_vdwxc_MOD_pofq+0x84>\n+\tldr\tr4, [pc, #548]\t@ (b8c <__gridxc_vdwxc_MOD_pofq+0x24c>)\n \tmov.w\tr2, #7200\t@ 0x1c20\n-\tldr.w\tr9, [pc, #532]\t@ b10 <__gridxc_vdwxc_MOD_pofq+0x240>\n+\tldr.w\tr9, [pc, #548]\t@ b90 <__gridxc_vdwxc_MOD_pofq+0x250>\n \tmovs\tr1, #0\n-\tldr.w\tsl, [pc, #528]\t@ b14 <__gridxc_vdwxc_MOD_pofq+0x244>\n+\tldr.w\tsl, [pc, #544]\t@ b94 <__gridxc_vdwxc_MOD_pofq+0x254>\n \tadd\tr4, pc\n-\tldr\tr6, [pc, #528]\t@ (b18 <__gridxc_vdwxc_MOD_pofq+0x248>)\n+\tldr\tr6, [pc, #544]\t@ (b98 <__gridxc_vdwxc_MOD_pofq+0x258>)\n \tadd\tr9, pc\n \tadd\tsl, pc\n \tadd.w\tr8, r4, #7424\t@ 0x1d00\n \tadd\tr6, pc\n \tadd.w\tsl, sl, #176\t@ 0xb0\n \tadd.w\tr8, r8, #16\n \tmov\tr5, r4\n@@ -831,1565 +861,1575 @@\n \tadd.w\tr2, r9, #16\n \tmov\tr0, sl\n \tadds\tr5, #240\t@ 0xf0\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_x>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_x\n \tadds\tr6, #240\t@ 0xf0\n \tcmp\tr8, r4\n-\tbne.n\t926 <__gridxc_vdwxc_MOD_pofq+0x56>\n-\tldr\tr3, [pc, #460]\t@ (b1c <__gridxc_vdwxc_MOD_pofq+0x24c>)\n+\tbne.n\t996 <__gridxc_vdwxc_MOD_pofq+0x56>\n+\tldr\tr3, [pc, #476]\t@ (b9c <__gridxc_vdwxc_MOD_pofq+0x25c>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstr\tr2, [r3, #4]\n-\tldr\tr4, [pc, #456]\t@ (b20 <__gridxc_vdwxc_MOD_pofq+0x250>)\n-\tvldr\td9, [fp]\n+\tldr\tr4, [pc, #472]\t@ (ba0 <__gridxc_vdwxc_MOD_pofq+0x260>)\n+\tvldr\td8, [fp]\n \tadd\tr4, pc\n \tvldr\td0, [r4, #408]\t@ 0x198\n-\tvcmpe.f64\td9, d0\n+\tvcmpe.f64\td8, d0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.w\tad0 <__gridxc_vdwxc_MOD_pofq+0x200>\n-\tldr\tr5, [pc, #436]\t@ (b24 <__gridxc_vdwxc_MOD_pofq+0x254>)\n-\tvldr\td8, [r4, #176]\t@ 0xb0\n+\tbgt.w\tb4e <__gridxc_vdwxc_MOD_pofq+0x20e>\n+\tldr\tr5, [pc, #452]\t@ (ba4 <__gridxc_vdwxc_MOD_pofq+0x264>)\n+\tvldr\td10, [r4, #176]\t@ 0xb0\n \tadd\tr5, pc\n \tldr\tr3, [r5, #8]\n \tcmp\tr3, #0\n-\tbne.w\ta86 <__gridxc_vdwxc_MOD_pofq+0x1b6>\n-\tvldr\td17, [r4, #416]\t@ 0x1a0\n-\tvldr\td10, [r4, #424]\t@ 0x1a8\n-\tvsub.f64\td16, d9, d8\n-\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n-\tldr\tr5, [pc, #408]\t@ (b28 <__gridxc_vdwxc_MOD_pofq+0x258>)\n+\tbne.w\tafa <__gridxc_vdwxc_MOD_pofq+0x1ba>\n+\tvldr\td7, [r4, #416]\t@ 0x1a0\n+\tvldr\td9, [r4, #424]\t@ 0x1a8\n+\tvsub.f64\td10, d8, d10\n+\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n+\tldr\tr5, [pc, #424]\t@ (ba8 <__gridxc_vdwxc_MOD_pofq+0x268>)\n+\tvmov.f64\td11, d12\n+\tvldr\td14, [pc, #364]\t@ b70 <__gridxc_vdwxc_MOD_pofq+0x230>\n \tadd\tr5, pc\n-\tvdiv.f64\td0, d16, d17\n-\tvadd.f64\td0, d0, d8\n+\tvdiv.f64\td0, d10, d7\n+\tvmov.f64\td10, d12\n+\tvadd.f64\td0, d0, d12\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td18, [pc, #336]\t@ af0 <__gridxc_vdwxc_MOD_pofq+0x220>\n-\tvdiv.f64\td16, d0, d10\n-\tvmov.f64\td17, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td26, #240\t@ 0xbf800000 -1.0\n-\tldr\tr3, [pc, #380]\t@ (b2c <__gridxc_vdwxc_MOD_pofq+0x25c>)\n-\tldr.w\tip, [pc, #384]\t@ b30 <__gridxc_vdwxc_MOD_pofq+0x260>\n+\tvmov.f64\td5, #8\t@ 0x40400000 3.0\n+\tvdiv.f64\td7, d0, d9\n+\tldr\tr3, [pc, #392]\t@ (bac <__gridxc_vdwxc_MOD_pofq+0x26c>)\n+\tldr.w\tip, [pc, #396]\t@ bb0 <__gridxc_vdwxc_MOD_pofq+0x270>\n \tadd\tr3, pc\n-\tldr\tr1, [sp, #8]\n \tadd.w\tr0, r3, #7200\t@ 0x1c20\n \tadd\tip, pc\n-\tldr\tr2, [sp, #12]\n-\tvadd.f64\td16, d16, d8\n-\tvcvt.s32.f64\ts15, d16\n+\tldrd\tr1, r2, [sp, #8]\n+\tvadd.f64\td7, d7, d12\n+\tvcvt.s32.f64\ts15, d7\n \tvmov\tr4, s15\n \tcmp\tr4, #1\n \tit\tlt\n \tmovlt\tr4, #1\n \tcmp\tr4, #29\n \tit\tge\n \tmovge\tr4, #29\n \tlsls\tr6, r4, #3\n \tadd.w\tr4, r5, r4, lsl #3\n \tadd\tr3, r6\n \tadd\tip, r6\n \tadd\tr0, r6\n-\tvldr\td21, [r4, #168]\t@ 0xa8\n-\tvldr\td20, [r4, #176]\t@ 0xb0\n-\tvsub.f64\td23, d9, d21\n-\tvsub.f64\td21, d20, d21\n-\tvsub.f64\td20, d20, d9\n-\tvdiv.f64\td27, d8, d21\n-\tvmul.f64\td28, d21, d21\n-\tvmul.f64\td21, d21, d18\n-\tvmul.f64\td28, d28, d18\n-\tvmul.f64\td20, d20, d27\n-\tvmul.f64\td23, d23, d27\n-\tvmul.f64\td16, d20, d20\n-\tvmul.f64\td18, d23, d23\n-\tvsub.f64\td25, d16, d8\n-\tvsub.f64\td24, d18, d8\n-\tvfma.f64\td26, d18, d17\n-\tvfms.f64\td8, d16, d17\n-\tvmul.f64\td25, d25, d20\n-\tvmul.f64\td24, d24, d23\n+\tvldr\td7, [r4, #168]\t@ 0xa8\n+\tvldr\td1, [r4, #176]\t@ 0xb0\n+\tvsub.f64\td0, d8, d7\n+\tvsub.f64\td7, d1, d7\n+\tvsub.f64\td1, d1, d8\n+\tvdiv.f64\td9, d12, d7\n+\tvmul.f64\td13, d7, d14\n+\tvmul.f64\td1, d1, d9\n+\tvmul.f64\td0, d0, d9\n+\tvmul.f64\td4, d1, d1\n+\tvmul.f64\td6, d0, d0\n+\tvsub.f64\td8, d4, d12\n+\tvmls.f64\td10, d4, d5\n+\tvnmls.f64\td11, d6, d5\n+\tvsub.f64\td12, d6, d12\n+\tvmul.f64\td5, d7, d7\n+\tvmul.f64\td8, d8, d1\n+\tvmul.f64\td12, d12, d0\n+\tvmul.f64\td14, d5, d14\n \tmov\tr4, ip\n-\tvldr\td18, [ip, #-8]\n-\tvldr\td29, [r3, #-8]\n+\tvldr\td3, [ip, #-8]\n+\tvldr\td4, [r3, #-8]\n \tadd.w\tip, ip, #240\t@ 0xf0\n-\tvldr\td17, [r4]\n+\tvldr\td2, [r4]\n \tmov\tr4, r3\n-\tvmul.f64\td16, d18, d8\n+\tvmul.f64\td5, d3, d10\n \tadds\tr3, #240\t@ 0xf0\n \tcmp\tr0, r3\n-\tvfma.f64\td16, d17, d26\n-\tvmul.f64\td17, d24, d17\n-\tvfma.f64\td17, d25, d18\n-\tvldr\td19, [r4]\n-\tvmul.f64\td18, d19, d23\n-\tvsub.f64\td19, d19, d29\n-\tvfma.f64\td18, d29, d20\n-\tvmul.f64\td16, d16, d21\n-\tvfma.f64\td18, d17, d28\n-\tvfma.f64\td16, d19, d27\n-\tvstmia\tr1!, {d18}\n-\tvstmia\tr2!, {d16}\n-\tbne.n\ta2e <__gridxc_vdwxc_MOD_pofq+0x15e>\n+\tvmul.f64\td6, d12, d2\n+\tvldr\td7, [r4]\n+\tvmla.f64\td6, d8, d3\n+\tvmla.f64\td5, d2, d11\n+\tvmul.f64\td3, d7, d0\n+\tvsub.f64\td7, d7, d4\n+\tvmla.f64\td3, d4, d1\n+\tvmul.f64\td7, d7, d9\n+\tvmla.f64\td7, d5, d13\n+\tvmla.f64\td3, d6, d14\n+\tvstmia\tr2!, {d7}\n+\tvstmia\tr1!, {d3}\n+\tbne.n\taa2 <__gridxc_vdwxc_MOD_pofq+0x162>\n \tadd\tsp, #20\n-\tvpop\t{d8-d11}\n+\tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td16, [r4, #400]\t@ 0x190\n+\tvldr\td7, [r4, #400]\t@ 0x190\n \tvldr\td11, [r4, #184]\t@ 0xb8\n-\tvldr\td10, [pc, #104]\t@ af8 <__gridxc_vdwxc_MOD_pofq+0x228>\n-\tvsub.f64\td0, d0, d16\n-\tvsub.f64\td11, d11, d8\n+\tvldr\td9, [pc, #116]\t@ b78 <__gridxc_vdwxc_MOD_pofq+0x238>\n+\tvsub.f64\td0, d0, d7\n+\tvsub.f64\td11, d11, d10\n \tvdiv.f64\td0, d0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td10, d0, d10\n-\tvldr\td16, [pc, #88]\t@ b00 <__gridxc_vdwxc_MOD_pofq+0x230>\n-\tvmaxnm.f64\td10, d10, d16\n-\tvmov.f64\td0, d10\n-\tvstr\td10, [r4, #424]\t@ 0x1a8\n+\tvmul.f64\td9, d0, d9\n+\tvldr\td7, [pc, #100]\t@ b80 <__gridxc_vdwxc_MOD_pofq+0x240>\n+\tvcmpe.f64\td9, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td9, d7\n+\tvmov.f64\td0, d9\n+\tvstr\td9, [r4, #424]\t@ 0x1a8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tmovs\tr3, #0\n \tstr\tr3, [r5, #8]\n-\tvsub.f64\td0, d0, d16\n-\tvdiv.f64\td17, d11, d0\n-\tvstr\td17, [r4, #416]\t@ 0x1a0\n-\tb.n\t984 <__gridxc_vdwxc_MOD_pofq+0xb4>\n+\tvsub.f64\td0, d0, d7\n+\tvdiv.f64\td7, d11, d0\n+\tvstr\td7, [r4, #416]\t@ 0x1a0\n+\tb.n\t9f4 <__gridxc_vdwxc_MOD_pofq+0xb4>\n \tldr\tr0, [sp, #8]\n \tmovs\tr2, #240\t@ 0xf0\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tldr\tr0, [sp, #12]\n \tmovs\tr2, #240\t@ 0xf0\n \tmovs\tr1, #0\n \tadd\tsp, #20\n-\tvpop\t{d8-d11}\n+\tvpop\t{d8-d14}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemset\n-\tnop\n+\tnop.w\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x92492492\n \t.word\t0x3fa24924\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000021a\n+\t.word\t0x0000022a\n R_ARM_REL32\t.data\n \t.word\t0x00003d2c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000204\n+\t.word\t0x00000214\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000206\n+\t.word\t0x00000216\n R_ARM_REL32\t.bss\n \t.word\t0x0000210c\n R_ARM_REL32\t.bss\n-\t.word\t0x000001c8\n+\t.word\t0x000001d8\n R_ARM_REL32\t.data\n-\t.word\t0x000001c2\n+\t.word\t0x000001d2\n R_ARM_REL32\t.bss\n-\t.word\t0x000001ae\n+\t.word\t0x000001be\n R_ARM_REL32\t.data\n-\t.word\t0x00000196\n+\t.word\t0x0000019e\n R_ARM_REL32\t.bss\n-\t.word\t0x00003c9e\n+\t.word\t0x00003c9a\n R_ARM_REL32\t.bss\n-\t.word\t0x0000207a\n+\t.word\t0x00002078\n R_ARM_REL32\t.bss\n \n-00000b34 <__gridxc_vdwxc_MOD_phi_val.isra.0>:\n+00000bb4 <__gridxc_vdwxc_MOD_phi_val.isra.0>:\n __gridxc_vdwxc_MOD_phi_val.isra.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3808]\t@ 0xee0\n+\tstr.w\tr0, [ip, #3792]\t@ 0xed0\n \tvmul.f64\td9, d0, d0\n \tvmul.f64\td10, d1, d1\n-\tvldr\td16, [pc, #532]\t@ d68 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x234>\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td21, #62\t@ 0x41f00000 30.0\n-\tvldr\td19, [pc, #528]\t@ d70 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x23c>\n-\tldr\tr5, [pc, #556]\t@ (d90 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x25c>)\n-\tvmov.f64\td20, #36\t@ 0x41200000 10.0\n-\tvadd.f64\td22, d9, d10\n-\tldr\tr4, [pc, #552]\t@ (d94 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x260>)\n-\tsub\tsp, #188\t@ 0xbc\n+\tvmov.f64\td11, d1\n+\tvmov.f64\td6, #62\t@ 0x41f00000 30.0\n+\tvmov.f64\td3, #36\t@ 0x41200000 10.0\n+\tvldr\td2, [pc, #536]\t@ df8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x244>\n+\tvmov.f64\td4, #96\t@ 0x3f000000 0.5\n+\tvldr\td5, [pc, #536]\t@ e00 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x24c>\n+\tvadd.f64\td1, d9, d10\n+\tldr\tr5, [pc, #552]\t@ (e18 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x264>)\n+\tldr\tr4, [pc, #556]\t@ (e1c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x268>)\n+\tsub\tsp, #204\t@ 0xcc\n \tadd\tr5, pc\n-\tldr\tr0, [pc, #548]\t@ (d98 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x264>)\n-\tadd\tr6, sp, #112\t@ 0x70\n-\tadd\tr3, sp, #128\t@ 0x80\n-\tadd\tr2, sp, #120\t@ 0x78\n-\tvsqrt.f64\td17, d22\n-\tvstr\td18, [sp, #128]\t@ 0x80\n+\tldr\tr0, [pc, #552]\t@ (e20 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x26c>)\n+\tadd\tr7, sp, #128\t@ 0x80\n+\tadd\tr3, sp, #144\t@ 0x90\n+\tvsqrt.f64\td7, d1\n+\tvstr\td4, [sp, #144]\t@ 0x90\n \tldr\tr4, [r5, r4]\n+\tadd\tr2, sp, #136\t@ 0x88\n \tadd\tr0, pc\n-\tmov\tr1, r6\n-\tvmov.f64\td8, d0\n+\tmov\tr1, r7\n \tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #180]\t@ 0xb4\n+\tstr\tr4, [sp, #196]\t@ 0xc4\n \tmov.w\tr4, #0\n-\tvmov.f64\td11, d1\n-\tvmul.f64\td16, d17, d16\n-\tvmul.f64\td17, d17, d21\n-\tvminnm.f64\td16, d16, d18\n-\tvmaxnm.f64\td17, d17, d20\n-\tvmaxnm.f64\td16, d16, d19\n-\tvstr\td17, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #120]\t@ 0x78\n+\tvmov.f64\td8, d0\n+\tmovs\tr6, #0\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td7, d7, d2\n+\tvcmpe.f64\td6, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td7, d4\n+\tit\tlt\n+\tvmovlt.f64\td6, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td6, [sp, #128]\t@ 0x80\n+\tit\thi\n+\tvmovhi.f64\td7, d4\n+\tvcmpe.f64\td7, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d5\n+\tvstr\td7, [sp, #136]\t@ 0x88\n \tbl\t0 <__gridxc_mesh1d_MOD_get_n>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_n\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tmovs\tr3, #8\n-\tcmp.w\tr0, #536870912\t@ 0x20000000\n-\tstr\tr3, [sp, #152]\t@ 0x98\n-\tstr\tr0, [sp, #20]\n+\tmovs\tr2, #8\n+\tstrd\tr6, r6, [sp, #172]\t@ 0xac\n \tmovw\tr3, #769\t@ 0x301\n-\tstr\tr0, [sp, #108]\t@ 0x6c\n-\tvstr\td16, [sp, #156]\t@ 0x9c\n-\tstrh.w\tr3, [sp, #160]\t@ 0xa0\n-\tbge.w\t1184 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x650>\n-\tcmp\tr0, #0\n-\tit\tgt\n-\tlslgt\tr7, r0, #3\n-\tit\tgt\n-\tmovgt\tr5, r7\n-\tbgt.n\tbe6 <__gridxc_vdwxc_MOD_phi_val.isra.0+0xb2>\n+\tcmp.w\tr0, #536870912\t@ 0x20000000\n+\tstr\tr0, [sp, #40]\t@ 0x28\n+\tstr\tr0, [sp, #124]\t@ 0x7c\n+\tstr\tr2, [sp, #168]\t@ 0xa8\n+\tstrh.w\tr3, [sp, #176]\t@ 0xb0\n+\tbge.w\t122e <__gridxc_vdwxc_MOD_phi_val.isra.0+0x67a>\n+\tcmp\tr0, r6\n+\titt\tgt\n+\tlslgt\tr6, r0, #3\n+\tmovgt\tr5, r6\n+\tbgt.n\tc7e <__gridxc_vdwxc_MOD_phi_val.isra.0+0xca>\n \tmovs\tr5, #1\n-\tmovs\tr7, #0\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #144]\t@ 0x90\n+\tstr\tr0, [sp, #160]\t@ 0xa0\n \tcmp\tr0, #0\n-\tbeq.w\t1176 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x642>\n-\tvldr\td16, [pc, #384]\t@ d78 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x244>\n-\tadd\tr3, sp, #164\t@ 0xa4\n+\tbeq.w\t1220 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x66c>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr0, r5\n \tmovs\tr4, #1\n-\tstr\tr4, [sp, #172]\t@ 0xac\n-\tvst1.32\t{d16}, [r3]\n-\tldr\tr3, [sp, #20]\n-\tstr\tr3, [sp, #176]\t@ 0xb0\n+\tstrd\tr4, r3, [sp, #188]\t@ 0xbc\n+\tstr\tr4, [sp, #184]\t@ 0xb8\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [sp, #148]\t@ 0x94\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tmovs\tr3, #8\n+\tstr\tr3, [sp, #180]\t@ 0xb4\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #24]\n+\tstr\tr0, [sp, #44]\t@ 0x2c\n \tcmp\tr0, #0\n-\tbeq.w\t1168 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x634>\n+\tbeq.w\t1212 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x65e>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #80]\t@ 0x50\n+\tstr\tr0, [sp, #96]\t@ 0x60\n \tcmp\tr0, #0\n-\tbeq.w\t115a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x626>\n+\tbeq.w\t1204 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x650>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #84]\t@ 0x54\n+\tstr\tr0, [sp, #100]\t@ 0x64\n \tcmp\tr0, #0\n-\tbeq.w\t114c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x618>\n+\tbeq.w\t11f6 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x642>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #28]\n+\tstr\tr0, [sp, #48]\t@ 0x30\n \tcmp\tr0, #0\n-\tbeq.w\t113e <__gridxc_vdwxc_MOD_phi_val.isra.0+0x60a>\n+\tbeq.w\t11e8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x634>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #32]\n+\tstr\tr0, [sp, #52]\t@ 0x34\n \tcmp\tr0, #0\n-\tbeq.w\t1130 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5fc>\n+\tbeq.w\t11da <__gridxc_vdwxc_MOD_phi_val.isra.0+0x626>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tstr\tr0, [sp, #36]\t@ 0x24\n+\tstr\tr0, [sp, #56]\t@ 0x38\n \tcmp\tr0, #0\n-\tbeq.w\t10fe <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5ca>\n-\tvldr\td18, [sp, #128]\t@ 0x80\n-\tadd\tr2, sp, #108\t@ 0x6c\n-\tvldr\td17, [sp, #120]\t@ 0x78\n-\tmov\tr3, r6\n-\tmov\tr7, r2\n+\tbeq.w\t11cc <__gridxc_vdwxc_MOD_phi_val.isra.0+0x618>\n+\tvldr\td5, [sp, #144]\t@ 0x90\n+\tadd\tr2, sp, #124\t@ 0x7c\n+\tvldr\td6, [sp, #136]\t@ 0x88\n \tmovs\tr6, #0\n-\tadd\tr5, sp, #136\t@ 0x88\n+\tmov\tr3, r7\n+\tmov\tr7, r2\n+\tadd\tr5, sp, #152\t@ 0x98\n \tmov\tr1, r6\n-\tvdiv.f64\td16, d18, d17\n+\tvdiv.f64\td7, d5, d6\n \tmov\tr0, r7\n-\tstr\tr2, [sp, #40]\t@ 0x28\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n \tmov\tr2, r6\n \tstr\tr6, [sp, #0]\n \tstr\tr5, [sp, #4]\n-\tvstr\td16, [sp, #136]\t@ 0x88\n+\tvstr\td7, [sp, #152]\t@ 0x98\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n \tmov\tr3, r6\n \tmov\tr1, r5\n-\tadd\tr2, sp, #144\t@ 0x90\n+\tadd\tr2, sp, #160\t@ 0xa0\n \tmov\tr0, r7\n \tstrd\tr6, r6, [sp, #4]\n \tstr\tr6, [sp, #0]\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r6\n-\tble.w\t10ea <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5b6>\n+\tble.w\t11b8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x604>\n \tvcmp.f64\td11, #0.0\n-\tvldr\td16, [pc, #212]\t@ d80 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x24c>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tldr\tr2, [sp, #144]\t@ 0x90\n-\tldr\tr1, [sp, #148]\t@ 0x94\n-\tvdiv.f64\td12, d17, d8\n-\tvmul.f64\td9, d9, d16\n+\tvldr\td7, [pc, #200]\t@ e08 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x254>\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tldr\tr2, [sp, #160]\t@ 0xa0\n+\tldr\tr1, [sp, #164]\t@ 0xa4\n+\tvdiv.f64\td12, d6, d8\n+\tvmul.f64\td9, d9, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td10, d10, d16\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tstr\tr1, [sp, #72]\t@ 0x48\n-\tbne.n\td9c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x268>\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tvmul.f64\td10, d10, d7\n+\tstr\tr2, [sp, #92]\t@ 0x5c\n+\tstr\tr1, [sp, #24]\n+\tbne.n\te24 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x270>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tadds\tr5, r1, #1\n \tmov\tr6, r4\n-\tadd.w\tfp, sp, #96\t@ 0x60\n-\tldrd\tsl, r9, [sp, #24]\n+\tadd\tr7, sp, #112\t@ 0x70\n+\tldrd\tfp, sl, [sp, #44]\t@ 0x2c\n \tadd.w\tr5, r3, r5, lsl #3\n-\tldr\tr3, [sp, #20]\n-\tldrd\tr8, r7, [sp, #32]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldrd\tr9, r8, [sp, #52]\t@ 0x34\n \tadds\tr4, r3, #1\n-\tadd\tr3, sp, #88\t@ 0x58\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tb.n\td3a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x206>\n+\tadd\tr3, sp, #104\t@ 0x68\n+\tstr\tr3, [sp, #16]\n+\tb.n\tdcc <__gridxc_vdwxc_MOD_phi_val.isra.0+0x218>\n \tvcmp.f64\td8, #0.0\n-\tvmul.f64\td14, d13, d13\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td13, d11, d11\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvmul.f64\td14, d14, d16\n-\tbeq.w\t1048 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x514>\n-\tvmul.f64\td13, d12, d13\n-\tvldr\td16, [pc, #128]\t@ d88 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x254>\n-\tvmul.f64\td13, d13, d13\n-\tvnmul.f64\td0, d16, d13\n+\tvmul.f64\td13, d13, d7\n+\tbeq.w\t10f2 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x53e>\n+\tvmul.f64\td11, d12, d11\n+\tvldr\td7, [pc, #116]\t@ e10 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x25c>\n+\tvmul.f64\td11, d11, d11\n+\tvnmul.f64\td0, d7, d11\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvsub.f64\td0, d16, d0\n-\tvdiv.f64\td16, d14, d0\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvsub.f64\td0, d7, d0\n+\tvdiv.f64\td7, d13, d0\n \tadds\tr6, #1\n-\tvstmia\tsl!, {d15}\n+\tvstmia\tfp!, {d15}\n \tcmp\tr4, r6\n-\tvstmia\tr9!, {d11}\n-\tvstmia\tr8!, {d16}\n-\tvstmia\tr7!, {d14}\n-\tbeq.w\te5c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x328>\n-\tvldmia\tr5!, {d13}\n-\tmov\tr0, fp\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td0, d13\n+\tvstmia\tsl!, {d14}\n+\tvstmia\tr9!, {d7}\n+\tvstmia\tr8!, {d13}\n+\tbeq.w\teec <__gridxc_vdwxc_MOD_phi_val.isra.0+0x338>\n+\tvldmia\tr5!, {d11}\n+\tmov\tr0, r7\n+\tldr\tr1, [sp, #16]\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvcmp.f64\td13, #0.0\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td11, [sp, #96]\t@ 0x60\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\tcea <__gridxc_vdwxc_MOD_phi_val.isra.0+0x1b6>\n-\tvmov.f64\td16, d9\n-\tvmov.f64\td14, d10\n-\tb.n\td22 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x1ee>\n-\tnop\n+\tvcmp.f64\td11, #0.0\n+\tvldr\td15, [sp, #104]\t@ 0x68\n+\tvldr\td14, [sp, #112]\t@ 0x70\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbne.n\td7c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x1c8>\n+\tvmov.f64\td7, d9\n+\tvmov.f64\td13, d10\n+\tb.n\tdb4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x200>\n \t.word\t0x9999999a\n \t.word\t0x3fb99999\n \t.word\t0x47ae147b\n \t.word\t0x3f847ae1\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n \t.word\t0x7b830193\n \t.word\t0x3fd6eb16\n \t.word\t0x4ae74487\n \t.word\t0x3ff65718\n-\t.word\t0x0000021e\n+\t.word\t0x00000222\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000212\n+\t.word\t0x00000216\n R_ARM_REL32\t.rodata\n-\tvdiv.f64\td13, d17, d11\n+\tvdiv.f64\td13, d6, d11\n \tvcmp.f64\td8, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t104e <__gridxc_vdwxc_MOD_phi_val.isra.0+0x51a>\n+\tbeq.w\t10f8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x544>\n+\tldrd\tr9, r8, [sp, #52]\t@ 0x34\n+\tadd\tr7, sp, #112\t@ 0x70\n \tadds\tr5, r1, #1\n-\tvmov.f64\td11, d17\n-\tldrd\tr8, r9, [sp, #24]\n+\tadds\tr4, r3, #1\n+\tvmov.f64\td11, d6\n+\tadd\tr3, sp, #104\t@ 0x68\n+\tldrd\tfp, sl, [sp, #44]\t@ 0x2c\n+\tstr\tr3, [sp, #16]\n+\tmov\tr3, r7\n+\tvldr\td8, [pc, #840]\t@ 1198 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5e4>\n+\tmov\tr7, r9\n \tadd.w\tr5, r2, r5, lsl #3\n-\tldrd\tsl, r7, [sp, #32]\n \tmovs\tr6, #1\n-\tvldr\td8, [pc, #844]\t@ 1110 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5dc>\n-\tadd.w\tfp, sp, #96\t@ 0x60\n-\tadds\tr4, r3, #1\n-\tadd\tr3, sp, #88\t@ 0x58\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tvldmia\tr5!, {d15}\n-\tmov\tr0, fp\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td0, d15\n+\tmov\tr9, r3\n+\tvldmia\tr5!, {d14}\n+\tmov\tr0, r9\n+\tldr\tr1, [sp, #16]\n+\tvmov.f64\td0, d14\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvcmp.f64\td15, #0.0\n-\tldrd\tr2, r3, [sp, #88]\t@ 0x58\n-\tvldr\td14, [sp, #96]\t@ 0x60\n+\tvcmp.f64\td14, #0.0\n+\tldrd\tr0, r1, [sp, #104]\t@ 0x68\n+\tldrd\tr2, r3, [sp, #112]\t@ 0x70\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t102e <__gridxc_vdwxc_MOD_phi_val.isra.0+0x4fa>\n-\tvmul.f64\td0, d12, d15\n-\tvmul.f64\td17, d15, d15\n-\tvmul.f64\td15, d13, d15\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tstrd\tr2, r3, [sp, #64]\t@ 0x40\n+\tbeq.w\t10d8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x524>\n+\tvmul.f64\td0, d12, d14\n+\tvmul.f64\td7, d14, d14\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td14, d13, d14\n+\tstrd\tr2, r3, [sp, #72]\t@ 0x48\n \tadds\tr6, #1\n+\tstrd\tr0, r1, [sp, #64]\t@ 0x40\n \tvmul.f64\td0, d0, d0\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td15, d15, d15\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td14, d14, d14\n \tvnmul.f64\td0, d8, d0\n-\tvstr\td17, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #32]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvstr\td0, [sp, #48]\t@ 0x30\n-\tvnmul.f64\td0, d8, d15\n+\tvmov.f64\td15, d0\n+\tvnmul.f64\td0, d8, d14\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td16, [sp, #48]\t@ 0x30\n \tvsub.f64\td0, d11, d0\n-\tvldr\td17, [sp, #56]\t@ 0x38\n-\tldrd\tr2, r3, [sp, #64]\t@ 0x40\n-\tvsub.f64\td16, d11, d16\n+\tvldr\td7, [sp, #32]\n \tcmp\tr6, r4\n-\tstrd\tr2, r3, [r8], #8\n-\tvstmia\tr9!, {d14}\n-\tvdiv.f64\td19, d17, d16\n-\tvdiv.f64\td16, d17, d0\n-\tvstmia\tsl!, {d19}\n-\tvstmia\tr7!, {d16}\n-\tbne.n\tdce <__gridxc_vdwxc_MOD_phi_val.isra.0+0x29a>\n-\tvmov.i64\td11, #0x0000000000000000\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr2, [sp, #20]\n-\tcmp\tr2, #1\n-\tvstr\td11, [r3]\n-\tbeq.w\tfc6 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x492>\n-\tadd.w\tr8, r3, #8\n+\tvsub.f64\td15, d11, d15\n+\tldrd\tr0, r1, [sp, #64]\t@ 0x40\n+\tstrd\tr0, r1, [fp], #8\n+\tvdiv.f64\td5, d7, d0\n+\tvdiv.f64\td4, d7, d15\n+\tldrd\tr2, r3, [sp, #72]\t@ 0x48\n+\tstrd\tr2, r3, [sl], #8\n+\tvstmia\tr8!, {d5}\n+\tvstmia\tr7!, {d4}\n+\tbne.n\te5a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x2a6>\n+\tldr\tr2, [sp, #96]\t@ 0x60\n+\tvldr\td7, [pc, #688]\t@ 11a0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5ec>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tvstr\td7, [r2]\n+\tcmp\tr3, #1\n+\tbeq.w\t1070 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x4bc>\n \tldr\tr3, [sp, #24]\n \tmovs\tr5, #8\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tadd\tr3, r5\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [sp, #28]\n-\tadd.w\tfp, r2, #2\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #92]\t@ 0x5c\n \tmovs\tr6, #2\n+\tadds\tr3, #2\n+\tadd.w\tr8, r2, #8\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tadd.w\tsl, r1, r3, lsl #3\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tmov\tr7, sl\n+\tstr.w\tsl, [sp, #88]\t@ 0x58\n+\tadd.w\tfp, r3, r5\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tadd\tr3, r5\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #32]\n-\tvmov.f64\td8, #8\t@ 0x40400000 3.0\n-\tadd.w\tfp, r2, fp, lsl #3\n-\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tadd\tr3, r5\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tmov\tr7, fp\n-\tstr.w\tfp, [sp, #64]\t@ 0x40\n-\tadd.w\tr9, r3, r5\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tmov\tsl, r3\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tadd\tr3, r5\n+\tstr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr9, r3\n \tadds\tr2, r3, r5\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr3, [sp, #24]\n-\tmov\tr0, r9\n-\tvldmia\tr7!, {d6}\n-\tvmov.f64\td22, #112\t@ 0x3f800000 1.0\n+\tstr\tr2, [sp, #64]\t@ 0x40\n+\tvldmia\tr7!, {d10}\n+\tmov\tsl, fp\n+\tvldr\td7, [pc, #604]\t@ 11a0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5ec>\n+\tvmov.f64\td2, #112\t@ 0x3f800000 1.0\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tvmul.f64\td14, d10, d10\n+\tldr.w\tlr, [sp, #72]\t@ 0x48\n \tadd\tr3, r5\n-\tldr.w\tip, [sp, #56]\t@ 0x38\n-\tldrd\tfp, lr, [sp, #44]\t@ 0x2c\n-\tvmul.f64\td3, d6, d6\n-\tvldr\td1, [r3]\n-\tldr\tr3, [sp, #32]\n-\tldr\tr1, [sp, #72]\t@ 0x48\n+\tvstr\td7, [r9]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tldrd\tip, r0, [sp, #80]\t@ 0x50\n+\tvsub.f64\td12, d11, d14\n+\tvsub.f64\td13, d14, d11\n+\tvmul.f64\td14, d14, d7\n+\tvldr\td7, [r3]\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #88]\t@ 0x58\n \tadd\tr3, r5\n-\tvsub.f64\td4, d8, d3\n-\tvsub.f64\td5, d3, d8\n-\tvmul.f64\td2, d6, d1\n-\tvmul.f64\td3, d3, d10\n-\tvmul.f64\td1, d1, d8\n-\tvldr\td28, [r3]\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tldr\tr2, [sp, #64]\t@ 0x40\n+\tvmul.f64\td15, d10, d7\n+\tvmul.f64\td7, d7, d11\n+\tvldr\td9, [r3]\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #16]\n \tadd\tr3, r5\n-\tvstr\td11, [sl]\n-\tvldr\td27, [r3]\n-\tldr\tr3, [sp, #28]\n+\tvldr\td8, [r3]\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tvadd.f64\td7, d9, d8\n \tadd\tr3, r5\n-\tvadd.f64\td0, d28, d27\n-\tvldr\td9, [r3]\n+\tvstr\td7, [sp, #32]\n+\tvldr\td7, [r3]\n \tmovs\tr3, #2\n-\tvldmia\tr2!, {d17}\n+\tvstr\td7, [sp, #24]\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #1\n-\tvldmia\tfp!, {d16}\n+\tvldmia\tsl!, {d5}\n \tcmp\tr3, r4\n-\tvldmia\tlr!, {d26}\n-\tvmul.f64\td18, d17, d17\n-\tvldmia\tip!, {d21}\n-\tvmul.f64\td29, d17, d16\n-\tvmul.f64\td17, d6, d17\n-\tvmul.f64\td16, d1, d16\n-\tvmul.f64\td31, d2, d26\n-\tvldmia\tr0!, {d20}\n-\tvadd.f64\td25, d21, d27\n-\tvadd.f64\td19, d5, d18\n-\tvsub.f64\td30, d8, d18\n-\tvmul.f64\td23, d17, d17\n-\tvmul.f64\td18, d18, d3\n-\tvnmul.f64\td16, d17, d16\n-\tvadd.f64\td24, d21, d20\n-\tvadd.f64\td7, d28, d20\n-\tvadd.f64\td21, d28, d21\n-\tvmul.f64\td19, d19, d26\n-\tvadd.f64\td20, d27, d20\n-\tvfma.f64\td19, d29, d4\n-\tvfma.f64\td16, d31, d30\n-\tvmul.f64\td24, d24, d0\n-\tvmul.f64\td23, d23, d17\n-\tvdiv.f64\td26, d22, d21\n-\tvmul.f64\td25, d7, d25\n-\tvdiv.f64\td21, d22, d20\n-\tvdiv.f64\td20, d22, d24\n-\tvdiv.f64\td17, d22, d25\n-\tvfma.f64\td16, d19, d9\n-\tvadd.f64\td16, d16, d16\n-\tvdiv.f64\td19, d16, d23\n-\tvadd.f64\td26, d26, d21\n-\tvadd.f64\td17, d17, d20\n-\tvmul.f64\td26, d26, d18\n-\tvmul.f64\td17, d17, d26\n-\tvmul.f64\td17, d17, d19\n-\tvstmia\tr1!, {d17}\n-\tbne.n\tf08 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x3d4>\n+\tvldr\td3, [sp, #16]\n+\tvmul.f64\td4, d7, d7\n+\tvmul.f64\td6, d10, d7\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td5, d3, d5\n+\tvadd.f64\td3, d13, d4\n+\tvmul.f64\td0, d7, d12\n+\tvsub.f64\td7, d11, d4\n+\tvmul.f64\td1, d5, d6\n+\tvldmia\tlr!, {d5}\n+\tvmla.f64\td0, d3, d5\n+\tvmul.f64\td5, d15, d5\n+\tvnmls.f64\td1, d5, d7\n+\tvldr\td7, [sp, #24]\n+\tvldmia\tip!, {d5}\n+\tvmla.f64\td1, d0, d7\n+\tvmul.f64\td0, d4, d14\n+\tvmul.f64\td4, d6, d6\n+\tvldmia\tr0!, {d7}\n+\tvadd.f64\td3, d5, d8\n+\tvmul.f64\td4, d4, d6\n+\tvadd.f64\td1, d1, d1\n+\tvdiv.f64\td6, d1, d4\n+\tvadd.f64\td4, d9, d7\n+\tvmul.f64\td4, d4, d3\n+\tvadd.f64\td3, d8, d7\n+\tvdiv.f64\td1, d2, d4\n+\tvadd.f64\td4, d5, d7\n+\tvadd.f64\td5, d9, d5\n+\tvldr\td7, [sp, #32]\n+\tvmul.f64\td4, d4, d7\n+\tvdiv.f64\td7, d2, d5\n+\tvdiv.f64\td5, d2, d3\n+\tvadd.f64\td7, d7, d5\n+\tvdiv.f64\td5, d2, d4\n+\tvmul.f64\td7, d7, d0\n+\tvadd.f64\td1, d1, d5\n+\tvmul.f64\td1, d1, d7\n+\tvmul.f64\td6, d6, d1\n+\tvstmia\tr1!, {d6}\n+\tbne.n\tfa6 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x3f2>\n \tmovs\tr3, #0\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n \tmov\tr2, r3\n-\tmov\tr1, sl\n+\tmov\tr1, r9\n \tbl\t0 <__gridxc_mesh1d_MOD_integral>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_integral\n-\tldr\tr3, [sp, #20]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tadds\tr6, #1\n \tadds\tr5, #8\n \tcmp\tr3, r6\n \tvstmia\tr8!, {d0}\n-\tbge.w\teb0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x37c>\n+\tbge.w\tf3a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x386>\n \tmovs\tr3, #0\n-\tldr\tr0, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n \tmov\tr2, r3\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tldr\tr1, [sp, #96]\t@ 0x60\n \tbl\t0 <__gridxc_mesh1d_MOD_integral>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_integral\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tvldr\td8, [pc, #320]\t@ 1118 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5e4>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tvldr\td8, [pc, #296]\t@ 11a8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5f4>\n \tvmul.f64\td8, d0, d8\n \tcmp\tr3, #0\n-\tbeq.w\t118c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x658>\n+\tbeq.w\t1236 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x682>\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #24]\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #80]\t@ 0x50\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #84]\t@ 0x54\n+\tldr\tr0, [sp, #100]\t@ 0x64\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #28]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #32]\n+\tldr\tr0, [sp, #52]\t@ 0x34\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr0, [sp, #36]\t@ 0x24\n+\tldr\tr0, [sp, #56]\t@ 0x38\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #272]\t@ (1120 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5ec>)\n-\tldr\tr3, [pc, #276]\t@ (1124 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5f0>)\n+\tldr\tr2, [pc, #248]\t@ (11b0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5fc>)\n+\tldr\tr3, [pc, #248]\t@ (11b4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x600>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #180]\t@ 0xb4\n+\tldr\tr3, [sp, #196]\t@ 0xc4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t10fa <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5c6>\n+\tbne.n\t11c8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x614>\n \tvmov.f64\td0, d8\n-\tadd\tsp, #188\t@ 0xbc\n+\tadd\tsp, #204\t@ 0xcc\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tadds\tr6, #1\n-\tstrd\tr2, r3, [r8], #8\n-\tcmp\tr4, r6\n-\tvstmia\tr9!, {d14}\n-\tvstmia\tsl!, {d9}\n-\tvstmia\tr7!, {d10}\n-\tbne.w\tdce <__gridxc_vdwxc_MOD_phi_val.isra.0+0x29a>\n-\tb.n\te5c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x328>\n-\tvmov.f64\td16, d14\n-\tb.n\td22 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x1ee>\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tstrd\tr0, r1, [fp], #8\n+\tcmp\tr6, r4\n+\tstrd\tr2, r3, [sl], #8\n+\tvstmia\tr7!, {d9}\n+\tvstmia\tr8!, {d10}\n+\tbne.w\te5a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x2a6>\n+\tb.n\teec <__gridxc_vdwxc_MOD_phi_val.isra.0+0x338>\n+\tvmov.f64\td7, d13\n+\tb.n\tdb4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x200>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n \tadds\tr5, r1, #1\n-\tldrd\tsl, r9, [sp, #24]\n+\tldrd\tfp, sl, [sp, #44]\t@ 0x2c\n \tmovs\tr6, #1\n \tadd.w\tr5, r3, r5, lsl #3\n-\tldr\tr3, [sp, #20]\n-\tldrd\tr8, r7, [sp, #32]\n-\tadd.w\tfp, sp, #96\t@ 0x60\n-\tvldr\td11, [pc, #168]\t@ 1110 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5dc>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldrd\tr9, r8, [sp, #52]\t@ 0x34\n+\tadd\tr7, sp, #112\t@ 0x70\n \tadds\tr4, r3, #1\n \tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tadd\tr3, sp, #88\t@ 0x58\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tvldmia\tr5!, {d14}\n-\tmov\tr0, fp\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n-\tvmov.f64\td0, d14\n+\tadd\tr3, sp, #104\t@ 0x68\n+\tstr\tr3, [sp, #16]\n+\tvldmia\tr5!, {d8}\n+\tmov\tr0, r7\n+\tldr\tr1, [sp, #16]\n+\tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\tsincos\n-\tvcmp.f64\td14, #0.0\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td8, [sp, #96]\t@ 0x60\n+\tvcmp.f64\td8, #0.0\n+\tvldr\td15, [sp, #104]\t@ 0x68\n+\tvldr\td14, [sp, #112]\t@ 0x70\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t10d2 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x59e>\n-\tvmul.f64\td0, d13, d14\n-\tvmul.f64\td14, d14, d14\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n+\tbeq.n\t117a <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5c6>\n+\tvmul.f64\td11, d8, d8\n+\tvmul.f64\td8, d13, d8\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n \tadds\tr6, #1\n-\tvmul.f64\td0, d0, d0\n-\tvmul.f64\td14, d14, d16\n-\tvnmul.f64\td0, d11, d0\n+\tvmul.f64\td8, d8, d8\n+\tvmul.f64\td11, d11, d7\n+\tvldr\td7, [pc, #68]\t@ 1198 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5e4>\n+\tvnmul.f64\td0, d7, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvsub.f64\td0, d12, d0\n-\tcmp\tr6, r4\n-\tvstmia\tsl!, {d15}\n-\tvstmia\tr9!, {d8}\n-\tvstmia\tr8!, {d14}\n-\tvdiv.f64\td17, d14, d0\n-\tvstmia\tr7!, {d17}\n-\tbne.n\t1074 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x540>\n-\tb.n\te5c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x328>\n+\tcmp\tr4, r6\n+\tvstmia\tfp!, {d15}\n+\tvstmia\tsl!, {d14}\n+\tvstmia\tr9!, {d11}\n+\tvdiv.f64\td6, d11, d0\n+\tvstmia\tr8!, {d6}\n+\tbne.n\t1118 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x564>\n+\tb.n\teec <__gridxc_vdwxc_MOD_phi_val.isra.0+0x338>\n \tadds\tr6, #1\n-\tvstmia\tsl!, {d15}\n+\tvstmia\tfp!, {d15}\n \tcmp\tr4, r6\n-\tvstmia\tr9!, {d8}\n-\tvstmia\tr8!, {d9}\n-\tvstmia\tr7!, {d10}\n-\tbne.n\t1074 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x540>\n-\tb.n\te5c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x328>\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tvstmia\tsl!, {d14}\n+\tvstmia\tr9!, {d9}\n+\tvstmia\tr8!, {d10}\n+\tbne.n\t1118 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x564>\n+\tb.n\teec <__gridxc_vdwxc_MOD_phi_val.isra.0+0x338>\n+\tnop\n+\tnop.w\n+\t.word\t0x4ae74487\n+\t.word\t0x3ff65718\n+\t...\n+\t.word\t0x6222c720\n+\t.word\t0x3fc9f02f\n+\t.word\t0x000000f2\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\tldr\tr1, [sp, #96]\t@ 0x60\n \tmovs\tr2, #0\n-\tldr\tr3, [sp, #144]\t@ 0x90\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #160]\t@ 0xa0\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n \tmovs\tr3, #0\n \tstrd\tr2, r3, [r1]\n-\tb.n\tfc6 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x492>\n+\tb.n\t1070 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x4bc>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tldr\tr1, [pc, #40]\t@ (1128 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5f4>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #40]\t@ (112c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x5f8>)\n+\tldr\tr1, [pc, #120]\t@ (1248 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x694>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #120]\t@ (124c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x698>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tnop.w\n-\t.word\t0x4ae74487\n-\t.word\t0x3ff65718\n-\t.word\t0x6222c720\n-\t.word\t0x3fc9f02f\n-\t.word\t0x0000010c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000020\n- R_ARM_REL32\t.LC2\n-\t.word\t0x00000022\n- R_ARM_REL32\t.LC9\n-\tldr\tr1, [pc, #104]\t@ (119c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x668>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #104]\t@ (11a0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x66c>)\n+\tldr\tr1, [pc, #116]\t@ (1250 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x69c>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #116]\t@ (1254 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6a0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #100]\t@ (11a4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x670>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #100]\t@ (11a8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x674>)\n+\tldr\tr1, [pc, #108]\t@ (1258 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6a4>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #108]\t@ (125c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6a8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #92]\t@ (11ac <__gridxc_vdwxc_MOD_phi_val.isra.0+0x678>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #92]\t@ (11b0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x67c>)\n+\tldr\tr1, [pc, #104]\t@ (1260 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6ac>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #104]\t@ (1264 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6b0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #88]\t@ (11b4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x680>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #88]\t@ (11b8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x684>)\n+\tldr\tr1, [pc, #96]\t@ (1268 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6b4>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #96]\t@ (126c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6b8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #80]\t@ (11bc <__gridxc_vdwxc_MOD_phi_val.isra.0+0x688>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #80]\t@ (11c0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x68c>)\n+\tldr\tr1, [pc, #92]\t@ (1270 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6bc>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #92]\t@ (1274 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6c0>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr1, [pc, #76]\t@ (11c4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x690>)\n-\tmov\tr2, r7\n-\tldr\tr0, [pc, #76]\t@ (11c8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x694>)\n+\tldr\tr1, [pc, #84]\t@ (1278 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6c4>)\n+\tmov\tr2, r6\n+\tldr\tr0, [pc, #84]\t@ (127c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6c8>)\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_os_error_at>\n R_ARM_THM_CALL\t_gfortran_os_error_at\n-\tldr\tr0, [pc, #68]\t@ (11cc <__gridxc_vdwxc_MOD_phi_val.isra.0+0x698>)\n+\tldr\tr0, [pc, #80]\t@ (1280 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6cc>)\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error>\n R_ARM_THM_CALL\t_gfortran_runtime_error\n-\tldr\tr2, [pc, #64]\t@ (11d0 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x69c>)\n-\tldr\tr1, [pc, #68]\t@ (11d4 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6a0>)\n-\tldr\tr0, [pc, #68]\t@ (11d8 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6a4>)\n+\tldr\tr2, [pc, #76]\t@ (1284 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6d0>)\n+\tldr\tr1, [pc, #76]\t@ (1288 <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6d4>)\n+\tldr\tr0, [pc, #80]\t@ (128c <__gridxc_vdwxc_MOD_phi_val.isra.0+0x6d8>)\n \tadd\tr2, pc\n \tadd\tr1, pc\n \tadd\tr0, pc\n \tbl\t0 <_gfortran_runtime_error_at>\n R_ARM_THM_CALL\t_gfortran_runtime_error_at\n-\t.word\t0x00000062\n+\tnop\n+\t.word\t0x00000072\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000064\n+\t.word\t0x00000074\n R_ARM_REL32\t.LC9\n-\t.word\t0x0000005c\n+\t.word\t0x0000006c\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000005e\n+\t.word\t0x0000006e\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000056\n+\t.word\t0x00000066\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000058\n+\t.word\t0x00000068\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000050\n+\t.word\t0x00000060\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000052\n+\t.word\t0x00000062\n R_ARM_REL32\t.LC9\n-\t.word\t0x0000004a\n+\t.word\t0x0000005a\n R_ARM_REL32\t.LC2\n-\t.word\t0x0000004c\n+\t.word\t0x0000005c\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000044\n+\t.word\t0x00000054\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000046\n+\t.word\t0x00000056\n R_ARM_REL32\t.LC9\n-\t.word\t0x00000042\n+\t.word\t0x0000004e\n+ R_ARM_REL32\t.LC2\n+\t.word\t0x00000050\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x0000004c\n R_ARM_REL32\t.LC1\n-\t.word\t0x0000003a\n+\t.word\t0x00000044\n R_ARM_REL32\t.LC4\n-\t.word\t0x0000003c\n+\t.word\t0x00000046\n R_ARM_REL32\t.LC5\n-\t.word\t0x0000003e\n+\t.word\t0x00000048\n R_ARM_REL32\t.LC10\n \n-000011dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>:\n+00001290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>:\n __gridxc_vdwxc_MOD_phi_soft.isra.0():\n \tpush\t{r3, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n \tvmul.f64\td8, d1, d1\n-\tvfma.f64\td8, d0, d0\n+\tvmla.f64\td8, d0, d0\n \tvcmp.f64\td8, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t1218 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0x3c>\n-\tvldr\td18, [pc, #172]\t@ 12b0 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xd4>\n-\tvcmpe.f64\td8, d18\n+\tbeq.n\t12cc <__gridxc_vdwxc_MOD_phi_soft.isra.0+0x3c>\n+\tvldr\td5, [pc, #168]\t@ 1360 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xd0>\n+\tvcmpe.f64\td8, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t1222 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0x46>\n+\tble.n\t12d6 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0x46>\n \tvpop\t{d8-d11}\n \tldmia.w\tsp!, {r3, lr}\n-\tb.n\tb34 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n+\tb.n\tbb4 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n \tvpop\t{d8-d11}\n-\tvldr\td0, [pc, #152]\t@ 12b8 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xdc>\n+\tvldr\td0, [pc, #148]\t@ 1368 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xd8>\n \tpop\t{r3, pc}\n-\tvsqrt.f64\td18, d8\n-\tvmov.f64\td16, d1\n-\tvldr\td1, [pc, #148]\t@ 12c0 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xe4>\n-\tvdiv.f64\td11, d16, d18\n-\tvdiv.f64\td10, d0, d18\n+\tvsqrt.f64\td5, d8\n+\tvmov.f64\td7, d1\n+\tvldr\td1, [pc, #144]\t@ 1370 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xe0>\n+\tvdiv.f64\td11, d7, d5\n+\tvdiv.f64\td10, d0, d5\n \tvmul.f64\td0, d10, d1\n \tvmul.f64\td1, d11, d1\n-\tbl\tb34 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n+\tbl\tbb4 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n \tvmov.f64\td9, d0\n-\tvldr\td0, [pc, #128]\t@ 12c8 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xec>\n+\tvldr\td0, [pc, #124]\t@ 1378 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xe8>\n \tvmul.f64\td1, d11, d0\n \tvmul.f64\td0, d10, d0\n-\tbl\tb34 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n-\tvldr\td16, [pc, #96]\t@ 12b8 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xdc>\n-\tvadd.f64\td22, d9, d0\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvldr\td17, [pc, #108]\t@ 12d0 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xf4>\n-\tvsub.f64\td23, d9, d0\n-\tvmov.f64\td18, d16\n-\tvsub.f64\td0, d0, d9\n-\tvldr\td21, [pc, #100]\t@ 12d8 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xfc>\n-\tvmov.f64\td24, #16\t@ 0x40800000 4.0\n-\tvfms.f64\td18, d22, d20\n-\tvfma.f64\td17, d22, d20\n-\tvmul.f64\td19, d8, d20\n-\tvadd.f64\td18, d18, d18\n-\tvmul.f64\td17, d17, d24\n-\tvfma.f64\td18, d23, d21\n-\tvfma.f64\td17, d0, d21\n-\tvmul.f64\td18, d19, d18\n-\tvfma.f64\td18, d17, d20\n-\tvfma.f64\td16, d8, d18\n+\tbl\tbb4 <__gridxc_vdwxc_MOD_phi_val.isra.0>\n+\tvadd.f64\td7, d9, d0\n+\tvsub.f64\td9, d9, d0\n+\tvldr\td3, [pc, #108]\t@ 1380 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xf0>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td6, [pc, #76]\t@ 1368 <__gridxc_vdwxc_MOD_phi_soft.isra.0+0xd8>\n+\tvmov.f64\td2, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td4, d8, d5\n+\tvmul.f64\td9, d9, d3\n+\tvsub.f64\td1, d7, d6\n+\tvsub.f64\td7, d6, d7\n+\tvmov.f64\td3, d9\n+\tvadd.f64\td7, d7, d7\n+\tvnmls.f64\td3, d1, d2\n+\tvadd.f64\td7, d7, d9\n+\tvmul.f64\td5, d3, d5\n+\tvmla.f64\td5, d7, d4\n+\tvmla.f64\td6, d5, d8\n \tvpop\t{d8-d11}\n-\tvmov.f64\td0, d16\n+\tvmov.f64\td0, d6\n \tpop\t{r3, pc}\n \tnop.w\n \t.word\t0x00000001\n \t.word\t0x3ff00000\n \t.word\t0x9999999a\n \t.word\t0x3fd99999\n \t.word\t0xc28f5c29\n \t.word\t0x3ff028f5\n \t.word\t0x7ae147ae\n \t.word\t0x3fefae14\n-\t.word\t0x9999999a\n-\t.word\t0xbfd99999\n \t.word\t0x00000000\n \t.word\t0x40490000\n \n-000012e0 <__gridxc_vdwxc_MOD_set_phi_table>:\n+00001388 <__gridxc_vdwxc_MOD_set_phi_table>:\n __gridxc_vdwxc_MOD_set_phi_table():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n-\tstr.w\tr0, [ip, #2432]\t@ 0x980\n+\tstr.w\tr0, [ip, #2408]\t@ 0x968\n \tsub.w\tsp, sp, #13824\t@ 0x3600\n-\tldr.w\tsl, [pc, #916]\t@ 16a8 <__gridxc_vdwxc_MOD_set_phi_table+0x3c8>\n-\tsub\tsp, #28\n-\tldr\tr2, [pc, #916]\t@ (16ac <__gridxc_vdwxc_MOD_set_phi_table+0x3cc>)\n-\tadd\tr4, sp, #128\t@ 0x80\n-\tadd.w\tr3, sp, #1560\t@ 0x618\n-\tldr\tr6, [pc, #912]\t@ (16b0 <__gridxc_vdwxc_MOD_set_phi_table+0x3d0>)\n-\tadd\tsl, pc\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldr.w\tsl, [pc, #884]\t@ 1730 <__gridxc_vdwxc_MOD_set_phi_table+0x3a8>\n+\tsub\tsp, #52\t@ 0x34\n+\tldr\tr2, [pc, #884]\t@ (1734 <__gridxc_vdwxc_MOD_set_phi_table+0x3ac>)\n+\tadd\tr4, sp, #160\t@ 0xa0\n \tmovw\tr3, #1116\t@ 0x45c\n-\tstrd\tsl, r3, [r4, #8]\n+\tldr\tr5, [pc, #880]\t@ (1738 <__gridxc_vdwxc_MOD_set_phi_table+0x3b0>)\n+\tadd\tsl, pc\n \tadd\tr2, pc\n-\tldr\tr3, [pc, #900]\t@ (16b4 <__gridxc_vdwxc_MOD_set_phi_table+0x3d4>)\n-\tadd\tr6, pc\n-\tmovs\tr5, #16\n-\tstrd\tr6, r5, [r4, #56]\t@ 0x38\n-\tvldr\td16, [pc, #836]\t@ 1680 <__gridxc_vdwxc_MOD_set_phi_table+0x3a0>\n+\tadd.w\tr6, sp, #1584\t@ 0x630\n+\tstrd\tsl, r3, [r4, #8]\n+\tmovs\tr3, #16\n+\tstr\tr3, [r4, #60]\t@ 0x3c\n+\tadd\tr5, pc\n+\tldr\tr3, [pc, #864]\t@ (173c <__gridxc_vdwxc_MOD_set_phi_table+0x3b4>)\n \tadd.w\tr1, sp, #13824\t@ 0x3600\n-\tadds\tr1, #20\n-\tadd\tr7, sp, #152\t@ 0x98\n-\tldr\tr3, [r2, r3]\n+\tstr\tr6, [sp, #92]\t@ 0x5c\n+\tadds\tr1, #44\t@ 0x2c\n+\tstr\tr5, [r4, #56]\t@ 0x38\n+\tadd.w\tr8, sp, #176\t@ 0xb0\n \tmov\tr0, r4\n+\tmov.w\tfp, #0\n+\tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r1, #0]\n \tmov.w\tr3, #0\n-\tsub.w\tr3, r7, #32\n-\tvstr\td16, [r4]\n+\tsub.w\tr3, r8, #24\n \tstr\tr3, [r4, #28]\n-\tstr\tr4, [sp, #68]\t@ 0x44\n+\tmov.w\tr3, #16512\t@ 0x4080\n+\tstrd\tr3, fp, [r4]\n+\tstr\tr4, [sp, #96]\t@ 0x60\n \tbl\t0 <_gfortran_st_inquire>\n R_ARM_THM_CALL\t_gfortran_st_inquire\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tsub.w\tr3, r3, #1440\t@ 0x5a0\n-\tldr\tr3, [r3, #0]\n-\tcmp\tr3, #0\n-\tbne.w\t204c <__gridxc_vdwxc_MOD_set_phi_table+0xd6c>\n-\tadd.w\tr5, sp, #10624\t@ 0x2980\n-\tadd.w\tfp, sp, #7424\t@ 0x1d00\n-\tadd.w\tr4, sp, #7424\t@ 0x1d00\n-\tadds\tr5, #16\n-\tadd\tr7, sp, #124\t@ 0x7c\n-\tadd.w\tfp, fp, #24\n-\tadds\tr4, #16\n-\tldr\tr3, [pc, #816]\t@ (16b8 <__gridxc_vdwxc_MOD_set_phi_table+0x3d8>)\n-\tmovs\tr6, #0\n-\tmov\tr2, r6\n-\tstr\tr6, [sp, #0]\n+\tadd\tr2, sp, #152\t@ 0x98\n+\tldr\tr2, [r2, #0]\n+\tcmp\tr2, #0\n+\tbne.w\t2058 <__gridxc_vdwxc_MOD_set_phi_table+0xcd0>\n+\tadd.w\tr4, sp, #10624\t@ 0x2980\n+\tadd.w\tr8, sp, #156\t@ 0x9c\n+\tadds\tr4, #40\t@ 0x28\n+\tadd.w\tr3, sp, #7456\t@ 0x1d20\n+\tadds\tr3, #16\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n+\tadd.w\tr3, sp, #7456\t@ 0x1d20\n+\tadds\tr3, #8\n+\tstr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr3, [pc, #780]\t@ (1740 <__gridxc_vdwxc_MOD_set_phi_table+0x3b8>)\n+\tmovs\tr5, #0\n+\tmov\tr2, r5\n+\tstr\tr5, [sp, #0]\n \tadd\tr3, pc\n-\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n-\tadd.w\tr8, r3, #32\n+\tmovs\tr7, #8\n+\tadd.w\tr6, r3, #32\n \tadd.w\tr1, r3, #40\t@ 0x28\n-\tmov\tr0, r8\n+\tmov\tr0, r6\n \tadds\tr3, #24\n \tstr\tr1, [sp, #4]\n-\tmov\tr1, r6\n+\tmov\tr1, r5\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tvmov.i32\td18, #0\t@ 0x00000000\n-\tadd.w\tr2, sp, #10624\t@ 0x2980\n-\tstrd\tr6, r6, [sp, #4]\n-\tadds\tr2, #28\n-\tstr\tr6, [sp, #0]\n-\tvldr\td16, [pc, #720]\t@ 1688 <__gridxc_vdwxc_MOD_set_phi_table+0x3a8>\n-\tvldr\td17, [pc, #724]\t@ 1690 <__gridxc_vdwxc_MOD_set_phi_table+0x3b0>\n-\tmov\tr3, r6\n-\tvstr\td18, [r2]\n-\tmovs\tr6, #8\n-\tstr\tr6, [r5, #8]\n-\tmovw\tr6, #769\t@ 0x301\n-\tstrh\tr6, [r5, #16]\n+\tmov\tr0, r6\n \tadd.w\tr6, sp, #10624\t@ 0x2980\n-\tmov\tr1, r7\n-\tadds\tr6, #36\t@ 0x24\n-\tldr\tr7, [pc, #740]\t@ (16bc <__gridxc_vdwxc_MOD_set_phi_table+0x3dc>)\n-\tmov\tr0, r8\n-\tmov\tr2, r5\n-\tmov\tr8, r5\n-\tadd\tr7, pc\n-\tstr\tr7, [sp, #56]\t@ 0x38\n-\tvst1.32\t{d16-d17}, [r6]\n-\tmov.w\tr7, #4294967295\t@ 0xffffffff\n-\tmov\tr6, r5\n-\tstr\tr7, [r5, #4]\n-\tldr\tr7, [sp, #56]\t@ 0x38\n-\tstr\tr7, [r5, #0]\n-\tmov\tr9, r7\n-\tmovs\tr7, #1\n+\tldr\tr3, [pc, #744]\t@ (1744 <__gridxc_vdwxc_MOD_set_phi_table+0x3bc>)\n+\tadds\tr6, #52\t@ 0x34\n+\tstrd\tr5, r5, [sp, #4]\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tstr\tr5, [sp, #0]\n+\tmov\tr3, r5\n+\tstr\tr7, [r4, #20]\n+\tmov\tr1, r8\n+\tstrd\tr5, r5, [r6]\n+\tmov\tr2, r4\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tmovs\tr6, #1\n+\tstr\tr7, [r4, #8]\n+\tmov\tr7, r4\n+\tstr\tr5, [r4, #0]\n+\tmovs\tr5, #20\n+\tstrd\tr6, r6, [r4, #24]\n+\tvmov.f64\td9, #112\t@ 0x3f800000 1.0\n+\tstr\tr5, [r4, #32]\n+\tmov.w\tr5, #4294967295\t@ 0xffffffff\n+\tstr\tr5, [r4, #4]\n+\tmovw\tr5, #769\t@ 0x301\n+\tstrh\tr5, [r4, #16]\n+\tmov\tr5, r4\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tstr\tr4, [sp, #40]\t@ 0x28\n-\tstr.w\tfp, [sp, #16]\n+\tldr.w\tr9, [sp, #64]\t@ 0x40\n \tvldmia\tr9!, {d8}\n \tvmov.f64\td1, d8\n \tvmov.f64\td0, d8\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n-\tcmp\tr7, #1\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tcmp\tr6, #1\n+\tvstr\td0, [r5]\n \tvmov.f64\td11, d0\n-\tvstr\td0, [r6]\n-\tbeq.w\t1fba <__gridxc_vdwxc_MOD_set_phi_table+0xcda>\n+\tittt\teq\n+\taddeq\tr5, #168\t@ 0xa8\n+\taddeq\tr7, #160\t@ 0xa0\n+\tmoveq\tr6, #2\n+\tbeq.n\t149e <__gridxc_vdwxc_MOD_set_phi_table+0x116>\n \tvmul.f64\td10, d8, d8\n-\tldr\tr4, [sp, #56]\t@ 0x38\n-\tadd.w\tfp, r5, r7, lsl #3\n-\tmov\tsl, r8\n-\tvldmia\tr4!, {d1}\n-\tvmov.f64\td16, d10\n+\tldr.w\tfp, [sp, #64]\t@ 0x40\n+\tadd.w\tsl, r4, r6, lsl #3\n+\tmov\tr8, r7\n+\tvldmia\tfp!, {d1}\n+\tvmov.f64\td7, d10\n \tvmov.f64\td0, d8\n-\tvfma.f64\td16, d1, d1\n-\tvcmpe.f64\td16, d9\n+\tvmla.f64\td7, d1, d1\n+\tvcmpe.f64\td7, d9\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t1646 <__gridxc_vdwxc_MOD_set_phi_table+0x366>\n+\tbmi.w\t16ec <__gridxc_vdwxc_MOD_set_phi_table+0x364>\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n \tvadd.f64\td0, d0, d11\n-\tadd.w\tfp, fp, #160\t@ 0xa0\n-\tvstr\td0, [fp, #-168]\t@ 0xffffff58\n-\tvstmia\tsl!, {d0}\n-\tcmp\tr6, sl\n-\tbne.n\t142a <__gridxc_vdwxc_MOD_set_phi_table+0x14a>\n-\tadds\tr7, #1\n-\tadds\tr6, #168\t@ 0xa8\n-\tadd.w\tr8, r8, #160\t@ 0xa0\n-\tcmp\tr7, #21\n-\tbne.n\t1400 <__gridxc_vdwxc_MOD_set_phi_table+0x120>\n-\tadd.w\tr7, sp, #4224\t@ 0x1080\n-\tldr.w\tfp, [sp, #16]\n-\tadds\tr7, #24\n-\tadd.w\tr8, sp, #1048\t@ 0x418\n-\tsub.w\tr3, r7, #8\n+\tadd.w\tsl, sl, #160\t@ 0xa0\n+\tvstr\td0, [sl, #-168]\t@ 0xffffff58\n+\tvstmia\tr8!, {d0}\n+\tcmp\tr5, r8\n+\tbne.n\t14d0 <__gridxc_vdwxc_MOD_set_phi_table+0x148>\n+\tadds\tr6, #1\n+\tadds\tr5, #168\t@ 0xa8\n+\tadds\tr7, #160\t@ 0xa0\n+\tcmp\tr6, #21\n+\tbne.n\t149e <__gridxc_vdwxc_MOD_set_phi_table+0x116>\n+\tadd.w\tr6, sp, #4256\t@ 0x10a0\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadds\tr6, #16\n+\tadd.w\tr7, sp, #1072\t@ 0x430\n+\tsub.w\tr3, r6, #8\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n+\tstrd\tr2, r3, [sp, #84]\t@ 0x54\n \tmovs\tr2, #1\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tmov\tr1, fp\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tmov\tr0, r8\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tadd.w\tr6, sp, #1040\t@ 0x410\n-\tldr\tr4, [sp, #40]\t@ 0x28\n-\tstr\tr3, [sp, #84]\t@ 0x54\n+\tstr\tr3, [sp, #72]\t@ 0x48\n+\tmov\tr0, r7\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tr5, sp, #1064\t@ 0x428\n+\tstr\tr3, [sp, #100]\t@ 0x64\n \tmovs\tr3, #2\n-\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #16]\n \tmov\tr3, r2\n-\tstrd\tr6, r4, [sp, #72]\t@ 0x48\n-\tstrd\tr4, fp, [sp, #88]\t@ 0x58\n-\tstrd\tr7, r6, [sp, #96]\t@ 0x60\n-\tstrd\tr8, r5, [sp, #104]\t@ 0x68\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tstr\tr5, [sp, #80]\t@ 0x50\n+\tstrd\tr6, r5, [sp, #104]\t@ 0x68\n+\tstrd\tr7, r4, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #68]\t@ 0x44\n \tmovs\tr5, #1\n-\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr\tr3, [sp, #100]\t@ 0x64\n \tmov\tr6, r5\n-\tvldr\td16, [pc, #488]\t@ 1698 <__gridxc_vdwxc_MOD_set_phi_table+0x3b8>\n-\tstrd\tr0, r1, [sp, #112]\t@ 0x70\n-\tvldmia\tr3!, {d8}\n-\tvmul.f64\td9, d8, d16\n-\tvldr\td16, [pc, #480]\t@ 16a0 <__gridxc_vdwxc_MOD_set_phi_table+0x3c0>\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tvmaxnm.f64\td9, d9, d16\n-\tvsub.f64\td12, d8, d9\n-\tvadd.f64\td11, d8, d9\n+\tvldr\td7, [pc, #468]\t@ 1720 <__gridxc_vdwxc_MOD_set_phi_table+0x398>\n+\tstrd\tr0, r1, [sp, #120]\t@ 0x78\n+\tvldmia\tr3!, {d15}\n+\tvmul.f64\td9, d15, d7\n+\tvldr\td7, [pc, #460]\t@ 1728 <__gridxc_vdwxc_MOD_set_phi_table+0x3a0>\n+\tstr\tr3, [sp, #100]\t@ 0x64\n+\tvcmpe.f64\td9, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td9, d7\n+\tvsub.f64\td12, d15, d9\n+\tvadd.f64\td11, d15, d9\n \tvmov.f64\td1, d12\n \tvmov.f64\td0, d12\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n-\tvmov.f64\td15, d0\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tvmov.f64\td14, d0\n \tvmov.f64\td1, d11\n \tvmov.f64\td0, d11\n-\tvstr\td15, [sp, #24]\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n-\tvadd.f64\td16, d9, d9\n-\tvmov.f64\td17, #80\t@ 0x3e800000 0.250\n-\tldrd\tr3, r2, [sp, #60]\t@ 0x3c\n-\tvmul.f64\td18, d8, d8\n-\tvdiv.f64\td10, d17, d9\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td16, d16, d16\n-\tldr\tr0, [sp, #112]\t@ 0x70\n+\tvstr\td14, [sp, #32]\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tvadd.f64\td7, d9, d9\n+\tvmov.f64\td6, #80\t@ 0x3e800000 0.250\n+\tldrd\tr3, r2, [sp, #68]\t@ 0x44\n+\tvmul.f64\td5, d15, d15\n+\tvdiv.f64\td10, d6, d9\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td7, d7, d7\n+\tldr\tr0, [sp, #120]\t@ 0x78\n \tadd.w\tr4, r2, r3, lsl #3\n-\tldr\tr1, [sp, #116]\t@ 0x74\n+\tldr\tr1, [sp, #124]\t@ 0x7c\n \tmov\tr3, r4\n-\tldr.w\tr8, [sp, #80]\t@ 0x50\n-\tldrd\tsl, r9, [sp, #72]\t@ 0x48\n+\tldr.w\tr8, [sp, #88]\t@ 0x58\n+\tldrd\tsl, r9, [sp, #80]\t@ 0x50\n \tmov\tfp, r0\n-\tvdiv.f64\td16, d17, d16\n-\tldr\tr7, [sp, #56]\t@ 0x38\n+\tvdiv.f64\td7, d6, d7\n+\tldr\tr7, [sp, #64]\t@ 0x40\n \tmov\tr4, r1\n \tmov\tr5, r3\n-\tvstr\td18, [sp, #32]\n-\tvstr\td0, [sp, #48]\t@ 0x30\n-\tvstr\td16, [sp, #16]\n-\tb.n\t15e6 <__gridxc_vdwxc_MOD_set_phi_table+0x306>\n+\tvstr\td5, [sp, #40]\t@ 0x28\n+\tvstr\td0, [sp, #56]\t@ 0x38\n+\tvstr\td7, [sp, #24]\n+\tb.n\t168c <__gridxc_vdwxc_MOD_set_phi_table+0x304>\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n-\tvmov.f64\td15, d0\n-\tvldr\td16, [sp, #24]\n+\tvmov.f64\td14, d0\n+\tvldr\td7, [sp, #32]\n \tvmov.f64\td1, d13\n \tvmov.f64\td0, d11\n-\tvadd.f64\td15, d15, d16\n+\tvadd.f64\td14, d14, d7\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n-\tvmov.f64\td13, d0\n-\tvldr\td14, [sp, #48]\t@ 0x30\n+\tvmov.f64\td15, d0\n+\tvldr\td13, [sp, #56]\t@ 0x38\n \tvmov.f64\td1, d8\n \tvmov.f64\td0, d11\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tvmov.f64\td1, d8\n-\tvadd.f64\td13, d13, d14\n+\tvadd.f64\td15, d15, d13\n \tcmp\tr3, r6\n-\tvadd.f64\td14, d0, d14\n+\tvadd.f64\td13, d0, d13\n \tvmov.f64\td0, d12\n-\tbeq.n\t166c <__gridxc_vdwxc_MOD_set_phi_table+0x38c>\n+\tbeq.n\t1710 <__gridxc_vdwxc_MOD_set_phi_table+0x388>\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n-\tvldr\td16, [sp, #24]\n-\tvadd.f64\td0, d0, d16\n-\tvadd.f64\td16, d13, d14\n-\tvsub.f64\td17, d14, d13\n-\tvldr\td19, [sp, #16]\n+\tvldr\td7, [sp, #32]\n+\tvadd.f64\td0, d0, d7\n+\tvadd.f64\td5, d15, d13\n+\tvsub.f64\td7, d13, d15\n+\tvldr\td4, [sp, #24]\n \tadds\tr5, #160\t@ 0xa0\n-\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr3, [sp, #16]\n \tadds\tr6, #1\n \tadds\tr4, #160\t@ 0xa0\n \tadd.w\tfp, fp, #160\t@ 0xa0\n-\tvsub.f64\td16, d16, d0\n-\tvsub.f64\td18, d17, d15\n-\tvsub.f64\td17, d17, d0\n+\tvsub.f64\td5, d5, d0\n+\tvsub.f64\td6, d7, d14\n+\tvsub.f64\td7, d7, d0\n \tcmp\tr6, r3\n-\tvsub.f64\td16, d16, d15\n-\tvadd.f64\td18, d18, d0\n-\tvadd.f64\td17, d17, d15\n-\tvmul.f64\td16, d16, d10\n-\tvmul.f64\td18, d18, d10\n-\tvmul.f64\td17, d17, d19\n-\tvstr\td16, [r5, #-168]\t@ 0xffffff58\n-\tvstmia\tr8!, {d18}\n-\tvldr\td16, [r5, #-168]\t@ 0xffffff58\n-\tvstr\td18, [r4, #-168]\t@ 0xffffff58\n-\tvstr\td17, [fp, #-168]\t@ 0xffffff58\n-\tvstmia\tr9!, {d16}\n-\tvstmia\tsl!, {d17}\n-\tbeq.n\t16c0 <__gridxc_vdwxc_MOD_set_phi_table+0x3e0>\n+\tvsub.f64\td5, d5, d14\n+\tvadd.f64\td6, d6, d0\n+\tvadd.f64\td7, d7, d14\n+\tvmul.f64\td5, d5, d10\n+\tvmul.f64\td6, d6, d10\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td5, [r5, #-168]\t@ 0xffffff58\n+\tvstr\td7, [fp, #-168]\t@ 0xffffff58\n+\tvstmia\tr8!, {d6}\n+\tvstmia\tsl!, {d7}\n+\tvldr\td7, [r5, #-168]\t@ 0xffffff58\n+\tvstr\td6, [r4, #-168]\t@ 0xffffff58\n+\tvstmia\tr9!, {d7}\n+\tbeq.n\t1748 <__gridxc_vdwxc_MOD_set_phi_table+0x3c0>\n \tvldmia\tr7!, {d8}\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td17, [sp, #32]\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [sp, #40]\t@ 0x28\n \tvmov.f64\td0, d12\n-\tvfma.f64\td17, d8, d8\n+\tvmla.f64\td6, d8, d8\n \tvsub.f64\td13, d8, d9\n \tvadd.f64\td8, d8, d9\n \tvmov.f64\td1, d13\n-\tvcmpe.f64\td17, d16\n+\tvcmpe.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t1538 <__gridxc_vdwxc_MOD_set_phi_table+0x258>\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tbpl.n\t15de <__gridxc_vdwxc_MOD_set_phi_table+0x256>\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n \tvmov.f64\td1, d13\n-\tvmov.f64\td15, d0\n+\tvmov.f64\td14, d0\n \tvmov.f64\td0, d11\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n \tvmov.f64\td1, d8\n-\tvmov.f64\td13, d0\n+\tvmov.f64\td15, d0\n \tvmov.f64\td0, d11\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n \tvmov.f64\td1, d8\n-\tvmov.f64\td14, d0\n+\tvmov.f64\td13, d0\n \tvmov.f64\td0, d12\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n-\tb.n\t158a <__gridxc_vdwxc_MOD_set_phi_table+0x2aa>\n-\tbl\t11dc <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n-\tadd.w\tfp, fp, #160\t@ 0xa0\n-\tvstr\td0, [fp, #-168]\t@ 0xffffff58\n-\tvstmia\tsl!, {d0}\n-\tcmp\tsl, r6\n-\tbne.w\t142a <__gridxc_vdwxc_MOD_set_phi_table+0x14a>\n-\tadds\tr7, #1\n-\tadds\tr6, #168\t@ 0xa8\n-\tadd.w\tr8, r8, #160\t@ 0xa0\n-\tcmp\tr7, #21\n-\tbne.w\t1400 <__gridxc_vdwxc_MOD_set_phi_table+0x120>\n-\tb.n\t146a <__gridxc_vdwxc_MOD_set_phi_table+0x18a>\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tb.n\t1630 <__gridxc_vdwxc_MOD_set_phi_table+0x2a8>\n+\tbl\t1290 <__gridxc_vdwxc_MOD_phi_soft.isra.0>\n+\tadd.w\tsl, sl, #160\t@ 0xa0\n+\tvstr\td0, [sl, #-168]\t@ 0xffffff58\n+\tvstmia\tr8!, {d0}\n+\tcmp\tr8, r5\n+\tbne.w\t14d0 <__gridxc_vdwxc_MOD_set_phi_table+0x148>\n+\tadds\tr6, #1\n+\tadds\tr5, #168\t@ 0xa8\n+\tadds\tr7, #160\t@ 0xa0\n+\tcmp\tr6, #21\n+\tbne.w\t149e <__gridxc_vdwxc_MOD_set_phi_table+0x116>\n+\tb.n\t150e <__gridxc_vdwxc_MOD_set_phi_table+0x186>\n \tbl\t0 <__gridxc_vdwxc_MOD_dphi.isra.0>\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvadd.f64\td0, d0, d16\n-\tb.n\t158a <__gridxc_vdwxc_MOD_set_phi_table+0x2aa>\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvadd.f64\td0, d0, d7\n+\tb.n\t1630 <__gridxc_vdwxc_MOD_set_phi_table+0x2a8>\n \tnop\n-\tnop.w\n-\t.word\t0x00004080\n-\t.word\t0x00000000\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000014\n \t.word\t0x47ae147b\n \t.word\t0x3f847ae1\n \t.word\t0xd2f1a9fc\n \t.word\t0x3f50624d\n-\t.word\t0x00000384\n+\t.word\t0x00000364\n R_ARM_REL32\t.LC11\n-\t.word\t0x0000037c\n+\t.word\t0x00000366\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000037c\n+\t.word\t0x0000035c\n R_ARM_REL32\t.LC12\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000328\n+\t.word\t0x00000302\n R_ARM_REL32\t.rodata\n-\t.word\t0x000002da\n+\t.word\t0x000002e0\n R_ARM_REL32\t.bss\n \tadds\tr2, r6, #1\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tldrd\tr0, r1, [sp, #112]\t@ 0x70\n+\tstr\tr2, [sp, #16]\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tldrd\tr0, r1, [sp, #120]\t@ 0x78\n \tadds\tr2, #160\t@ 0xa0\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tstr\tr2, [sp, #88]\t@ 0x58\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tadds\tr1, #8\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tldr\tr3, [sp, #68]\t@ 0x44\n \tadds\tr0, #8\n \tadds\tr2, #160\t@ 0xa0\n-\tstr\tr2, [sp, #76]\t@ 0x4c\n-\tldr\tr2, [sp, #72]\t@ 0x48\n+\tstr\tr2, [sp, #84]\t@ 0x54\n+\tldr\tr2, [sp, #80]\t@ 0x50\n \tadds\tr3, #1\n \tcmp\tr3, #21\n \tadd.w\tr2, r2, #160\t@ 0xa0\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tbne.w\t14a6 <__gridxc_vdwxc_MOD_set_phi_table+0x1c6>\n-\tldrd\tr8, r5, [sp, #104]\t@ 0x68\n-\tadd.w\tr0, sp, #13632\t@ 0x3540\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tbne.w\t1542 <__gridxc_vdwxc_MOD_set_phi_table+0x1ba>\n+\tldrd\tr7, r4, [sp, #112]\t@ 0x70\n+\tadd.w\tr0, sp, #13696\t@ 0x3580\n \tmovs\tr2, #160\t@ 0xa0\n \tmovs\tr1, #0\n-\tadds\tr0, #48\t@ 0x30\n-\tldrd\tr4, fp, [sp, #88]\t@ 0x58\n-\tldrd\tr7, r6, [sp, #96]\t@ 0x60\n+\tadds\tr0, #8\n+\tldrd\tr6, r5, [sp, #104]\t@ 0x68\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tadd.w\tr2, r5, #3200\t@ 0xc80\n-\tmov\tr3, r5\n+\tadd.w\tr2, r4, #3200\t@ 0xc80\n+\tmov\tr3, r4\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tstrd\tr0, r1, [r3, #152]\t@ 0x98\n \tadds\tr3, #160\t@ 0xa0\n \tcmp\tr2, r3\n-\tbne.n\t170e <__gridxc_vdwxc_MOD_set_phi_table+0x42e>\n-\taddw\tr0, r7, #3032\t@ 0xbd8\n+\tbne.n\t1792 <__gridxc_vdwxc_MOD_set_phi_table+0x40a>\n+\taddw\tr0, r6, #3032\t@ 0xbd8\n \tmovs\tr1, #0\n \tmovs\tr2, #160\t@ 0xa0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n-\tadd.w\tr7, r3, #3200\t@ 0xc80\n+\tadd.w\tr6, r3, #3200\t@ 0xc80\n \tstrd\tr0, r1, [r3, #152]\t@ 0x98\n \tadds\tr3, #160\t@ 0xa0\n-\tcmp\tr7, r3\n-\tbne.n\t172e <__gridxc_vdwxc_MOD_set_phi_table+0x44e>\n+\tcmp\tr6, r3\n+\tbne.n\t17b2 <__gridxc_vdwxc_MOD_set_phi_table+0x42a>\n+\tldr\tr3, [sp, #76]\t@ 0x4c\n \tmovs\tr2, #160\t@ 0xa0\n \tmovs\tr1, #0\n-\taddw\tr0, fp, #3032\t@ 0xbd8\n+\taddw\tr0, r3, #3032\t@ 0xbd8\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tadd.w\tr2, r4, #3200\t@ 0xc80\n-\tmov\tr3, r4\n+\tldr\tr3, [sp, #52]\t@ 0x34\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n+\tadd.w\tr2, r3, #3200\t@ 0xc80\n \tstrd\tr0, r1, [r3, #152]\t@ 0x98\n \tadds\tr3, #160\t@ 0xa0\n \tcmp\tr2, r3\n-\tbne.n\t174e <__gridxc_vdwxc_MOD_set_phi_table+0x46e>\n-\taddw\tr0, r8, #3032\t@ 0xbd8\n+\tbne.n\t17d4 <__gridxc_vdwxc_MOD_set_phi_table+0x44c>\n+\taddw\tr0, r7, #3032\t@ 0xbd8\n \tmovs\tr1, #0\n \tmovs\tr2, #160\t@ 0xa0\n-\tadd.w\tr8, r6, #3200\t@ 0xc80\n+\tadd.w\tr7, r5, #3200\t@ 0xc80\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tmov\tr3, r6\n+\tmov\tr3, r5\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tstrd\tr0, r1, [r3, #152]\t@ 0x98\n \tadds\tr3, #160\t@ 0xa0\n-\tcmp\tr8, r3\n-\tbne.n\t176e <__gridxc_vdwxc_MOD_set_phi_table+0x48e>\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tcmp\tr7, r3\n+\tbne.n\t17f4 <__gridxc_vdwxc_MOD_set_phi_table+0x46c>\n+\tldr\tr3, [sp, #72]\t@ 0x48\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tstrd\tr0, r1, [r3], #160\t@ 0xa0\n-\tcmp\tr7, r3\n-\tbne.n\t177e <__gridxc_vdwxc_MOD_set_phi_table+0x49e>\n+\tcmp\tr6, r3\n+\tbne.n\t1804 <__gridxc_vdwxc_MOD_set_phi_table+0x47c>\n \tmovs\tr2, #160\t@ 0xa0\n \tmovs\tr1, #0\n-\tmov\tr0, r4\n+\tldr\tr0, [sp, #52]\t@ 0x34\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmovs\tr1, #0\n \tmovs\tr2, #160\t@ 0xa0\n-\tmov\tr0, r6\n+\tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tmov\tr3, r6\n+\tmov\tr3, r5\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tstrd\tr0, r1, [r3], #160\t@ 0xa0\n-\tcmp\tr8, r3\n-\tbne.n\t17a0 <__gridxc_vdwxc_MOD_set_phi_table+0x4c0>\n-\tadd.w\tr0, r4, #160\t@ 0xa0\n-\tldr\tr4, [pc, #952]\t@ (1b68 <__gridxc_vdwxc_MOD_set_phi_table+0x888>)\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tadd.w\tr3, r5, #160\t@ 0xa0\n-\tldr\tr2, [pc, #948]\t@ (1b6c <__gridxc_vdwxc_MOD_set_phi_table+0x88c>)\n-\tadd\tr4, pc\n-\tldr\tr5, [sp, #56]\t@ 0x38\n+\tcmp\tr7, r3\n+\tbne.n\t1826 <__gridxc_vdwxc_MOD_set_phi_table+0x49e>\n+\tadd.w\tip, r5, #160\t@ 0xa0\n+\tldr\tr1, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #52]\t@ 0x34\n+\tadd.w\tr3, r4, #160\t@ 0xa0\n+\tldr.w\tr5, [pc, #1180]\t@ 1cd8 <__gridxc_vdwxc_MOD_set_phi_table+0x950>\n \tadds\tr1, #160\t@ 0xa0\n-\tadd.w\tip, r6, #160\t@ 0xa0\n+\tldr.w\tr2, [pc, #1176]\t@ 1cdc <__gridxc_vdwxc_MOD_set_phi_table+0x954>\n+\tadds\tr0, #160\t@ 0xa0\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tadd\tr5, pc\n \tadd\tr2, pc\n-\tmov\tr7, r0\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n-\tmov\tr0, r4\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tvldr\td12, [pc, #868]\t@ 1b30 <__gridxc_vdwxc_MOD_set_phi_table+0x850>\n-\tvldr\td13, [pc, #872]\t@ 1b38 <__gridxc_vdwxc_MOD_set_phi_table+0x858>\n-\tadd.w\tr6, r5, #152\t@ 0x98\n-\tvldr\td14, [pc, #872]\t@ 1b40 <__gridxc_vdwxc_MOD_set_phi_table+0x860>\n-\tvldr\td15, [pc, #876]\t@ 1b48 <__gridxc_vdwxc_MOD_set_phi_table+0x868>\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tvldr\td10, [pc, #876]\t@ 1b50 <__gridxc_vdwxc_MOD_set_phi_table+0x870>\n-\tvldr\td11, [pc, #880]\t@ 1b58 <__gridxc_vdwxc_MOD_set_phi_table+0x878>\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tvldr\td9, [pc, #884]\t@ 1b60 <__gridxc_vdwxc_MOD_set_phi_table+0x880>\n-\tadd\tr5, sp, #696\t@ 0x2b8\n \tmov.w\tsl, #0\n-\tstr\tr5, [sp, #24]\n-\tadd.w\tr8, r2, #2096\t@ 0x830\n-\tadd\tr5, sp, #568\t@ 0x238\n-\tmov\tr6, ip\n-\tstr\tr5, [sp, #60]\t@ 0x3c\n-\tadd\tr5, sp, #440\t@ 0x1b8\n-\tstr\tr5, [sp, #80]\t@ 0x50\n-\tadd\tr5, sp, #400\t@ 0x190\n-\tstr\tr5, [sp, #76]\t@ 0x4c\n-\tadd\tr5, sp, #520\t@ 0x208\n-\tstr\tr5, [sp, #88]\t@ 0x58\n-\tadd\tr5, sp, #480\t@ 0x1e0\n-\tstr\tr5, [sp, #84]\t@ 0x54\n-\tmov\tr5, r1\n-\tmov\tr1, r3\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tadd.w\tr3, r1, sl\n-\tadd.w\tr9, r6, sl\n-\tstr\tr3, [sp, #32]\n-\tadd.w\tr3, r5, sl\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tadd.w\tfp, r7, sl\n-\tstrd\tsl, r0, [sp, #96]\t@ 0x60\n-\tmov\tsl, r9\n-\tmov\tr9, r3\n+\tldr.w\tfp, [sp, #92]\t@ 0x5c\n+\tadd.w\tr6, r4, #152\t@ 0x98\n+\tmov\tr7, r0\n+\tstr\tr6, [sp, #88]\t@ 0x58\n+\tmov\tr0, r5\n+\tstr\tr5, [sp, #124]\t@ 0x7c\n+\tadd.w\tr6, r2, #2096\t@ 0x830\n+\tmov\tr5, ip\n+\tmov\tr9, r1\n+\tmov\tip, sl\n+\tstr\tr4, [sp, #80]\t@ 0x50\n+\tadd\tr4, sp, #720\t@ 0x2d0\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr4, [sp, #56]\t@ 0x38\n+\tadd\tr4, sp, #592\t@ 0x250\n+\tstr\tr4, [sp, #84]\t@ 0x54\n+\tadd\tr4, sp, #472\t@ 0x1d8\n+\tstr\tr4, [sp, #112]\t@ 0x70\n+\tadd\tr4, sp, #436\t@ 0x1b4\n+\tstr\tr4, [sp, #108]\t@ 0x6c\n+\tadd\tr4, sp, #544\t@ 0x220\n+\tstr\tr4, [sp, #120]\t@ 0x78\n+\tadd\tr4, sp, #508\t@ 0x1fc\n+\tstr\tr4, [sp, #116]\t@ 0x74\n+\tadd.w\tr1, r7, ip\n+\tstr\tr1, [sp, #76]\t@ 0x4c\n+\tldr\tr1, [sp, #64]\t@ 0x40\n+\tadd.w\tr2, r9, ip\n+\tstr\tr1, [sp, #52]\t@ 0x34\n+\tsub.w\tr1, fp, #864\t@ 0x360\n+\tstr\tr1, [sp, #100]\t@ 0x64\n+\tadd.w\tr8, r3, ip\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tadd.w\tsl, r5, ip\n+\tstr\tr7, [sp, #144]\t@ 0x90\n+\tsub.w\tr4, fp, #992\t@ 0x3e0\n+\tmov\tr7, r2\n+\tadd.w\tr1, r1, #2096\t@ 0x830\n \tstr\tr0, [sp, #40]\t@ 0x28\n-\tstr\tr2, [sp, #16]\n-\tstrd\tr1, r7, [sp, #104]\t@ 0x68\n-\tstrd\tr6, r5, [sp, #112]\t@ 0x70\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr9, r9, #8\n-\tldr\tr2, [sp, #16]\n-\tadd.w\tfp, fp, #8\n-\tvldr\td18, [sl, #-160]\t@ 0xffffff60\n-\tsub.w\tr1, r4, #992\t@ 0x3e0\n-\tvldr\td20, [sl, #-152]\t@ 0xffffff68\n-\tsub.w\tr0, r4, #864\t@ 0x360\n-\tvldr\td17, [r3]\n-\tvldr\td16, [r3, #8]\n-\tmov\tr3, r2\n-\tvldr\td27, [r9, #-168]\t@ 0xffffff58\n+\tstr\tr1, [sp, #104]\t@ 0x68\n+\tstrd\tip, r0, [sp, #128]\t@ 0x80\n+\tstr\tr6, [sp, #72]\t@ 0x48\n+\tstrd\tr3, r9, [sp, #136]\t@ 0x88\n+\tstr\tr5, [sp, #148]\t@ 0x94\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tadds\tr7, #8\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tadd.w\tr8, r8, #8\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tvldr\td5, [sl, #-160]\t@ 0xffffff60\n \tadds\tr2, #8\n-\tvldr\td26, [r9, #-160]\t@ 0xffffff60\n-\tvsub.f64\td16, d16, d17\n-\tvldr\td21, [r3]\n-\tvldr\td17, [r2]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td7, [r3]\n+\tmov\tr3, r1\n+\tvldr\td2, [r2, #-168]\t@ 0xffffff58\n+\tadds\tr1, #8\n+\tvldr\td6, [sl, #-152]\t@ 0xffffff68\n+\tvsub.f64\td7, d3, d7\n+\tvldr\td3, [r2, #-160]\t@ 0xffffff60\n+\tvldr\td4, [r7, #-168]\t@ 0xffffff58\n+\tvldr\td1, [r7, #-160]\t@ 0xffffff60\n+\tldr\tr0, [sp, #100]\t@ 0x64\n+\tvmul.f64\td2, d2, d7\n+\tvmul.f64\td3, d3, d7\n+\tvmul.f64\td5, d7, d5\n+\tvmul.f64\td6, d7, d6\n+\tvstr\td2, [r4, #64]\t@ 0x40\n+\tvstr\td3, [r4, #72]\t@ 0x48\n+\tvldr\td2, [r3]\n \tmov\tr3, sl\n-\tvldr\td25, [fp, #-168]\t@ 0xffffff58\n+\tvldr\td3, [r1]\n \tadd.w\tsl, sl, #8\n-\tvldr\td24, [fp, #-160]\t@ 0xffffff60\n-\tvsub.f64\td17, d17, d21\n-\tvmul.f64\td18, d16, d18\n-\tvmul.f64\td20, d16, d20\n-\tvldr\td22, [r9, #-8]\n-\tldr.w\tip, [sp, #32]\n-\tvmul.f64\td24, d24, d16\n-\tvmul.f64\td25, d25, d16\n-\tstr\tr2, [sp, #16]\n-\tvmul.f64\td19, d18, d17\n-\tvldr\td23, [r9]\n-\tvmul.f64\td18, d20, d17\n-\tvldr\td20, [fp, #-8]\n-\tvmul.f64\td27, d27, d17\n-\tvmul.f64\td22, d22, d17\n-\tvmul.f64\td23, d23, d17\n-\tvmul.f64\td26, d26, d17\n-\tvldr\td21, [fp]\n-\tvmul.f64\td20, d20, d16\n-\tvldr\td28, [ip, #-160]\t@ 0xffffff60\n-\tmov\tr5, ip\n-\tldrd\tr6, r7, [ip]\n-\tvmul.f64\td21, d21, d16\n-\tvstr\td28, [r1]\n+\tstr\tr1, [sp, #52]\t@ 0x34\n+\tmov\tr1, r4\n+\tvsub.f64\td3, d3, d2\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td1, d1, d3\n+\tvstr\td5, [r4, #96]\t@ 0x60\n+\tvldr\td5, [r7, #-8]\n+\tvstr\td6, [r4, #104]\t@ 0x68\n+\tvstr\td4, [r4, #32]\n+\tvldr\td6, [r7]\n+\tvmul.f64\td5, d5, d3\n+\tvstr\td1, [r4, #40]\t@ 0x28\n+\tvmul.f64\td6, d6, d3\n+\tvstr\td5, [r4, #56]\t@ 0x38\n+\tvldr\td5, [r2, #-8]\n+\tvstr\td6, [r4, #48]\t@ 0x30\n+\tvldr\td6, [r2]\n+\tvmul.f64\td5, d5, d7\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n \tmovs\tr2, #128\t@ 0x80\n-\tvstr\td27, [r1, #32]\n-\tvstr\td23, [r1, #48]\t@ 0x30\n-\tvstr\td22, [r1, #56]\t@ 0x38\n-\tvstr\td24, [r1, #72]\t@ 0x48\n-\tvstr\td21, [r1, #80]\t@ 0x50\n-\tvstr\td20, [r1, #88]\t@ 0x58\n-\tvstr\td19, [r1, #96]\t@ 0x60\n-\tvstr\td18, [r1, #104]\t@ 0x68\n-\tstrd\tr6, r7, [r1, #24]\n-\tvstr\td26, [r1, #40]\t@ 0x28\n-\tvstr\td25, [r1, #64]\t@ 0x40\n-\tldrd\tr6, r7, [ip, #-152]\t@ 0x98\n-\tstrd\tr6, r7, [r1, #8]\n-\tvldr\td19, [r3]\n-\tvldr\td18, [sl]\n-\tldrd\tr6, r7, [r5, #8]!\n-\tstrd\tr6, r7, [r1, #16]\n-\tvmul.f64\td18, d16, d18\n-\tvmul.f64\td16, d16, d19\n-\tstr\tr5, [sp, #32]\n-\tvmul.f64\td18, d18, d17\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td18, [r1, #112]\t@ 0x70\n-\tvstr\td16, [r1, #120]\t@ 0x78\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td5, [r4, #88]\t@ 0x58\n+\tvstr\td6, [r4, #80]\t@ 0x50\n+\tvldr\td6, [r8, #-8]\n+\tvstr\td6, [r4, #24]\n+\tvldr\td6, [r8, #-168]\t@ 0xffffff58\n+\tvldr\td5, [r3]\n+\tvstr\td6, [r4]\n+\tvldr\td6, [r8, #-160]\t@ 0xffffff60\n+\tvstr\td6, [r4, #8]\n+\tvldr\td6, [r8]\n+\tvstr\td6, [r4, #16]\n+\tvldr\td6, [sl]\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td6, [r4, #112]\t@ 0x70\n+\tvstr\td7, [r4, #120]\t@ 0x78\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tvmov.i64\td17, #0x0000000000000000\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr2, [sp, #24]\n+\tvldr\td6, [pc, #784]\t@ 1cd0 <__gridxc_vdwxc_MOD_set_phi_table+0x948>\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tvmov.f64\td3, d6\n+\tvmov.f64\td15, d6\n+\tvmov.f64\td14, d6\n+\tvmov.f64\td13, d6\n+\tvmov.f64\td12, d6\n+\tvmov.f64\td11, d6\n+\tvmov.f64\td10, d6\n+\tvmov.f64\td9, d6\n+\tvmov.f64\td8, d6\n+\tvmov.f64\td0, d6\n+\tvmov.f64\td1, d6\n+\tvmov.f64\td4, d6\n+\tvmov.f64\td2, d6\n+\tldr\tr6, [sp, #72]\t@ 0x48\n \tadds\tr3, #48\t@ 0x30\n-\tvmov.f64\td18, d17\n-\tvmov.f64\td19, d17\n-\tvmov.f64\td20, d17\n-\tvmov.f64\td21, d17\n-\tvmov.f64\td22, d17\n-\tvmov.f64\td23, d17\n-\tvmov.f64\td24, d17\n-\tvmov.f64\td27, d17\n-\tvmov.f64\td28, d17\n-\tvmov.f64\td29, d17\n-\tvmov.f64\td30, d17\n-\tvmov.f64\td31, d17\n-\tvmov.f64\td7, d17\n-\tvmov.f64\td6, d17\n-\tvmov.f64\td5, d17\n-\tvldmia\tr2!, {d16}\n+\tvstr\td6, [sp, #16]\n+\tvstr\td6, [sp, #24]\n+\tvstr\td6, [sp, #32]\n+\tvldmia\tr2!, {d7}\n \tadds\tr3, #128\t@ 0x80\n-\tvldr\td25, [r3, #-120]\t@ 0xffffff88\n-\tvldr\td26, [r3, #-128]\t@ 0xffffff80\n-\tvldr\td2, [r3, #-112]\t@ 0xffffff90\n-\tvfma.f64\td6, d16, d25\n-\tvldr\td25, [r3, #-80]\t@ 0xffffffb0\n-\tvldr\td1, [r3, #-104]\t@ 0xffffff98\n-\tvfma.f64\td5, d26, d16\n-\tvldr\td0, [r3, #-96]\t@ 0xffffffa0\n-\tvfma.f64\td7, d16, d2\n-\tvldr\td8, [r3, #-88]\t@ 0xffffffa8\n-\tvfma.f64\td28, d16, d25\n-\tvldr\td25, [r3, #-72]\t@ 0xffffffb8\n-\tvfma.f64\td31, d16, d1\n-\tvldr\td3, [r3, #-64]\t@ 0xffffffc0\n-\tvfma.f64\td30, d16, d0\n-\tvldr\td4, [r3, #-56]\t@ 0xffffffc8\n-\tvfma.f64\td29, d16, d8\n-\tvldr\td2, [r3, #-48]\t@ 0xffffffd0\n-\tvfma.f64\td27, d16, d25\n-\tvldr\td1, [r3, #-40]\t@ 0xffffffd8\n-\tvfma.f64\td24, d16, d3\n-\tvldr\td0, [r3, #-32]\t@ 0xffffffe0\n-\tvfma.f64\td23, d16, d4\n-\tvldr\td8, [r3, #-24]\t@ 0xffffffe8\n-\tvfma.f64\td22, d16, d2\n-\tvldr\td26, [r3, #-16]\n-\tvfma.f64\td21, d16, d1\n-\tvldr\td25, [r3, #-8]\n-\tvfma.f64\td20, d16, d0\n-\tvfma.f64\td19, d16, d8\n-\tcmp\tr8, r3\n-\tvfma.f64\td18, d16, d26\n-\tvfma.f64\td17, d16, d25\n-\tbne.n\t198a <__gridxc_vdwxc_MOD_set_phi_table+0x6aa>\n-\tsub.w\tr3, r4, #992\t@ 0x3e0\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tsub.w\tr6, r4, #1120\t@ 0x460\n-\tsubw\tr7, r4, #1100\t@ 0x44c\n-\tvstr\td5, [r3]\n-\tsub.w\tr5, r4, #1080\t@ 0x438\n-\tvstr\td6, [r3, #8]\n-\tsubw\tlr, r4, #1068\t@ 0x42c\n-\tvstr\td29, [r3, #40]\t@ 0x28\n-\tmov.w\tip, #4\n-\tvstr\td7, [r3, #16]\n-\tmovs\tr0, #8\n-\tvstr\td31, [r3, #24]\n-\tvstr\td30, [r3, #32]\n-\tvstr\td28, [r3, #48]\t@ 0x30\n-\tvstr\td27, [r3, #56]\t@ 0x38\n-\tvstr\td24, [r3, #64]\t@ 0x40\n-\tvstr\td23, [r3, #72]\t@ 0x48\n-\tvstr\td22, [r3, #80]\t@ 0x50\n-\tvstr\td21, [r3, #88]\t@ 0x58\n-\tvstr\td20, [r3, #96]\t@ 0x60\n-\tvstr\td19, [r3, #104]\t@ 0x68\n-\tvstr\td18, [r3, #112]\t@ 0x70\n-\tvstr\td17, [r3, #120]\t@ 0x78\n-\tsub.w\tr3, r4, #1040\t@ 0x410\n-\tstr.w\tip, [r6, #8]\n-\tstr\tr2, [r3, #0]\n-\tsub.w\tr2, r4, #1160\t@ 0x488\n-\tstr.w\tip, [r3, #44]\t@ 0x2c\n-\tstr\tr0, [r3, #8]\n-\tstr\tr1, [r2, #0]\n-\tsubw\tr1, r4, #1028\t@ 0x404\n-\tstr\tr0, [r2, #8]\n-\tmvn.w\tr0, #4\n-\tstr\tr0, [r3, #4]\n-\tmovw\tr0, #770\t@ 0x302\n-\tvstr\td16, [r1]\n-\tsub.w\tr1, r4, #1020\t@ 0x3fc\n-\tvst1.32\t{d12-d13}, [r1]\n-\tsub.w\tr1, r4, #1004\t@ 0x3ec\n-\tvst1.32\t{d9}, [r1]\n-\tsubw\tr1, r4, #1148\t@ 0x47c\n-\tvstr\td16, [r1]\n-\tsubw\tr1, r4, #1140\t@ 0x474\n-\tvst1.32\t{d14-d15}, [r1]\n-\tsubw\tr1, r4, #1108\t@ 0x454\n-\tvstr\td16, [r1]\n-\tmov.w\tr1, #4294967295\t@ 0xffffffff\n-\tstr\tr1, [r2, #4]\n-\tstrh\tr0, [r3, #16]\n-\tsubw\tr0, r4, #1060\t@ 0x424\n-\tvst1.32\t{d10-d11}, [r7]\n-\tmovw\tr3, #769\t@ 0x301\n-\tldr\tr7, [pc, #144]\t@ (1b70 <__gridxc_vdwxc_MOD_set_phi_table+0x890>)\n-\tstrh\tr3, [r2, #16]\n-\tmovw\tr3, #257\t@ 0x101\n-\tvstr\td16, [lr]\n-\tadd\tr7, pc\n-\tstrh\tr3, [r6, #16]\n-\tstrh\tr3, [r5, #16]\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tstr.w\tip, [r5, #8]\n-\tadd.w\tip, r7, #2096\t@ 0x830\n-\tvst1.32\t{d10-d11}, [r0]\n-\taddw\tr7, r7, #2104\t@ 0x838\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tstr\tr3, [sp, #0]\n+\tvldr\td6, [r3, #-128]\t@ 0xffffff80\n+\tcmp\tr6, r3\n+\tvldr\td5, [sp, #32]\n+\tvmla.f64\td2, d7, d6\n+\tvldr\td6, [r3, #-120]\t@ 0xffffff88\n+\tvmla.f64\td4, d7, d6\n+\tvldr\td6, [r3, #-112]\t@ 0xffffff90\n+\tvmla.f64\td5, d7, d6\n+\tvldr\td6, [r3, #-104]\t@ 0xffffff98\n+\tvmla.f64\td1, d7, d6\n+\tvldr\td6, [r3, #-96]\t@ 0xffffffa0\n+\tvmla.f64\td0, d7, d6\n+\tvldr\td6, [r3, #-88]\t@ 0xffffffa8\n+\tvstr\td5, [sp, #32]\n+\tvmla.f64\td8, d7, d6\n+\tvldr\td6, [r3, #-80]\t@ 0xffffffb0\n+\tvldr\td5, [r3, #-24]\t@ 0xffffffe8\n+\tvmla.f64\td9, d7, d6\n+\tvldr\td6, [r3, #-72]\t@ 0xffffffb8\n+\tvmla.f64\td10, d7, d6\n+\tvldr\td6, [r3, #-64]\t@ 0xffffffc0\n+\tvmla.f64\td11, d7, d6\n+\tvldr\td6, [r3, #-56]\t@ 0xffffffc8\n+\tvmla.f64\td12, d7, d6\n+\tvldr\td6, [r3, #-48]\t@ 0xffffffd0\n+\tvmla.f64\td13, d7, d6\n+\tvldr\td6, [r3, #-40]\t@ 0xffffffd8\n+\tvmla.f64\td14, d7, d6\n+\tvldr\td6, [r3, #-32]\t@ 0xffffffe0\n+\tvmla.f64\td15, d7, d6\n+\tvldr\td6, [sp, #16]\n+\tvmla.f64\td6, d7, d5\n+\tvldr\td5, [sp, #24]\n+\tvstr\td6, [sp, #16]\n+\tvldr\td6, [r3, #-16]\n+\tvmla.f64\td3, d7, d6\n+\tvldr\td6, [r3, #-8]\n+\tvmla.f64\td5, d7, d6\n+\tvstr\td5, [sp, #24]\n+\tbne.n\t1a0a <__gridxc_vdwxc_MOD_set_phi_table+0x682>\n+\tvmov.f64\td6, d5\n+\tsub.w\tr2, fp, #1040\t@ 0x410\n+\tvldr\td5, [sp, #32]\n+\tsubw\tr0, fp, #1028\t@ 0x404\n+\tvldr\td7, [sp, #16]\n+\tsub.w\tr1, fp, #1136\t@ 0x470\n+\tsubw\tr5, fp, #1148\t@ 0x47c\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tmov.w\tlr, #8\n+\tstr\tr3, [r2, #0]\n+\tsubw\tip, fp, #1100\t@ 0x44c\n \tmovs\tr3, #0\n-\tstr\tr1, [r6, #4]\n-\tstr\tr1, [r5, #4]\n-\tstr.w\tip, [r6]\n-\tldrd\tr1, r2, [sp, #76]\t@ 0x4c\n-\tstr\tr7, [r5, #0]\n+\tmvn.w\tr9, #4\n+\tstrd\tr3, r3, [r0]\n+\tstrd\tr3, r3, [r1]\n+\tmovs\tr0, #4\n+\tmovs\tr1, #1\n+\tstr\tr0, [r2, #32]\n+\tstrd\tr1, r1, [r2, #24]\n+\tstr\tr1, [r2, #40]\t@ 0x28\n+\tstr\tr0, [r2, #44]\t@ 0x2c\n+\tstr\tr0, [r2, #36]\t@ 0x24\n+\tstr.w\tlr, [r2, #20]\n+\tstr\tr6, [sp, #72]\t@ 0x48\n+\tvstr\td2, [r4]\n+\tvstr\td4, [r4, #8]\n+\tvstr\td5, [r4, #16]\n+\tvstr\td1, [r4, #24]\n+\tvstr\td0, [r4, #32]\n+\tvstr\td7, [r4, #104]\t@ 0x68\n+\tvstr\td3, [r4, #112]\t@ 0x70\n+\tvstr\td6, [r4, #120]\t@ 0x78\n+\tvstr\td8, [r4, #40]\t@ 0x28\n+\tvstr\td9, [r4, #48]\t@ 0x30\n+\tvstr\td10, [r4, #56]\t@ 0x38\n+\tvstr\td11, [r4, #64]\t@ 0x40\n+\tvstr\td12, [r4, #72]\t@ 0x48\n+\tvstr\td13, [r4, #80]\t@ 0x50\n+\tvstr\td14, [r4, #88]\t@ 0x58\n+\tvstr\td15, [r4, #96]\t@ 0x60\n+\tstr.w\tlr, [r2, #8]\n+\tstr.w\tr9, [r2, #4]\n+\tmovw\tr9, #770\t@ 0x302\n+\tstrh.w\tr9, [r2, #16]\n+\tmov.w\tr9, #4294967295\t@ 0xffffffff\n+\tldr\tr2, [sp, #116]\t@ 0x74\n+\tstr.w\tlr, [r5, #20]\n+\tstr.w\tlr, [r5, #8]\n+\tsub.w\tlr, fp, #1112\t@ 0x458\n+\tstr\tr2, [sp, #0]\n+\tsub.w\tr2, fp, #1064\t@ 0x428\n+\tstrd\tr3, r3, [ip]\n+\tsubw\tip, fp, #1076\t@ 0x434\n+\tstr.w\tr0, [lr, #20]\n+\tstrd\tr3, r3, [r2]\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tstr\tr2, [r5, #0]\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tstr.w\tr0, [lr, #8]\n+\tstrd\tr1, r1, [lr, #24]\n+\tstr.w\tr2, [lr]\n+\tstr.w\tr0, [ip, #20]\n+\tstr.w\tr0, [ip, #8]\n+\tstrd\tr1, r1, [ip, #24]\n+\tstr.w\tr9, [lr, #4]\n+\tstr.w\tr9, [ip, #4]\n+\tldr\tr0, [sp, #120]\t@ 0x78\n+\tstrd\tr1, r1, [r5, #24]\n+\tstr.w\tr9, [r5, #4]\n+\tmov.w\tr9, #2\n+\tldrd\tr1, r2, [sp, #108]\t@ 0x6c\n+\tstr.w\tr9, [lr, #32]\n+\tstr.w\tr9, [ip, #32]\n+\tmovw\tr9, #257\t@ 0x101\n+\tstrh.w\tr9, [lr, #16]\n+\tmov.w\tlr, #16\n+\tldr\tr6, [sp, #68]\t@ 0x44\n+\tstrh.w\tr9, [ip, #16]\n+\tstr.w\tlr, [r5, #32]\n+\taddw\tlr, r6, #2104\t@ 0x838\n+\tstr.w\tlr, [ip]\n+\tmovw\tip, #769\t@ 0x301\n+\tstrh.w\tip, [r5, #16]\n \tbl\t0 <_gfortran_reshape_r8>\n R_ARM_THM_CALL\t_gfortran_reshape_r8\n-\tldr\tr2, [sp, #40]\t@ 0x28\n-\tadd.w\tr3, r2, #128\t@ 0x80\n-\tldr\tr2, [sp, #16]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr2, [sp, #52]\t@ 0x34\n+\tadds\tr3, #128\t@ 0x80\n \tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #88]\t@ 0x58\n \tcmp\tr3, r2\n-\tbne.w\t183e <__gridxc_vdwxc_MOD_set_phi_table+0x55e>\n-\tb.n\t1b74 <__gridxc_vdwxc_MOD_set_phi_table+0x894>\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000004\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000010\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000002\n-\t.word\t0x00000004\n-\t.word\t0x00000001\n-\t.word\t0x000003ae\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x000003a8\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000084\n- R_ARM_REL32\t.rodata\n-\tldrd\tsl, r0, [sp, #96]\t@ 0x60\n-\tmov\tr2, r3\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldrd\tr1, r7, [sp, #104]\t@ 0x68\n-\tadds\tr3, #8\n-\tldrd\tr6, r5, [sp, #112]\t@ 0x70\n+\tbne.w\t18c0 <__gridxc_vdwxc_MOD_set_phi_table+0x538>\n+\tldrd\tip, r0, [sp, #128]\t@ 0x80\n+\tmov\tr1, r3\n+\tldr\tr2, [sp, #80]\t@ 0x50\n+\tldr\tr6, [sp, #72]\t@ 0x48\n \tadd.w\tr0, r0, #2560\t@ 0xa00\n-\tadd.w\tsl, sl, #160\t@ 0xa0\n-\tcmp\tr2, r3\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tbne.w\t1816 <__gridxc_vdwxc_MOD_set_phi_table+0x536>\n-\tldr\tr4, [sp, #92]\t@ 0x5c\n+\tadds\tr2, #8\n+\tadd.w\tip, ip, #160\t@ 0xa0\n+\tldrd\tr3, r9, [sp, #136]\t@ 0x88\n+\tcmp\tr1, r2\n+\tldrd\tr7, r5, [sp, #144]\t@ 0x90\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tbne.w\t1886 <__gridxc_vdwxc_MOD_set_phi_table+0x4fe>\n+\tldr\tr5, [sp, #124]\t@ 0x7c\n \tmovs\tr0, #0\n-\tldr.w\tr3, [pc, #1148]\t@ 2018 <__gridxc_vdwxc_MOD_set_phi_table+0xd38>\n+\tldr\tr3, [pc, #204]\t@ (1ce0 <__gridxc_vdwxc_MOD_set_phi_table+0x958>)\n \tmovs\tr1, #0\n-\tadd.w\tr2, r4, #53504\t@ 0xd100\n+\tadd.w\tr2, r5, #53504\t@ 0xd100\n \tadd\tr3, pc\n \tadds\tr2, #128\t@ 0x80\n \tadd.w\tr3, r3, #2432\t@ 0x980\n \tstrd\tr0, r1, [r3]\n \tstrd\tr0, r1, [r3, #8]\n \tstrd\tr0, r1, [r3, #16]\n \tstrd\tr0, r1, [r3, #24]\n@@ -2403,17 +2443,17 @@\n \tstrd\tr0, r1, [r3, #88]\t@ 0x58\n \tstrd\tr0, r1, [r3, #96]\t@ 0x60\n \tstrd\tr0, r1, [r3, #104]\t@ 0x68\n \tstrd\tr0, r1, [r3, #112]\t@ 0x70\n \tstrd\tr0, r1, [r3, #120]\t@ 0x78\n \tadd.w\tr3, r3, #2560\t@ 0xa00\n \tcmp\tr2, r3\n-\tbne.n\t1bac <__gridxc_vdwxc_MOD_set_phi_table+0x8cc>\n-\tldr.w\tr2, [pc, #1060]\t@ 201c <__gridxc_vdwxc_MOD_set_phi_table+0xd3c>\n-\tadd.w\tr5, r4, #51200\t@ 0xc800\n+\tbne.n\t1c22 <__gridxc_vdwxc_MOD_set_phi_table+0x89a>\n+\tldr\tr2, [pc, #120]\t@ (1ce4 <__gridxc_vdwxc_MOD_set_phi_table+0x95c>)\n+\tadd.w\tr4, r5, #51200\t@ 0xc800\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tadd\tr2, pc\n \tadd.w\tr2, r2, #48640\t@ 0xbe00\n \tmov\tr3, r2\n \tstrd\tr0, r1, [r3]\n \tadds\tr3, #128\t@ 0x80\n@@ -2428,3113 +2468,3104 @@\n \tstrd\tr0, r1, [r3, #-56]\t@ 0x38\n \tstrd\tr0, r1, [r3, #-48]\t@ 0x30\n \tstrd\tr0, r1, [r3, #-40]\t@ 0x28\n \tstrd\tr0, r1, [r3, #-32]\n \tstrd\tr0, r1, [r3, #-24]\n \tstrd\tr0, r1, [r3, #-16]\n \tstrd\tr0, r1, [r3, #-8]\n-\tcmp\tr5, r3\n-\tbne.n\t1c08 <__gridxc_vdwxc_MOD_set_phi_table+0x928>\n-\tldr\tr3, [pc, #976]\t@ (2020 <__gridxc_vdwxc_MOD_set_phi_table+0xd40>)\n-\tadd.w\tr1, r4, #50944\t@ 0xc700\n+\tcmp\tr4, r3\n+\tbne.n\t1c7c <__gridxc_vdwxc_MOD_set_phi_table+0x8f4>\n+\tldr\tr3, [pc, #36]\t@ (1ce8 <__gridxc_vdwxc_MOD_set_phi_table+0x960>)\n+\tadd.w\tr1, r5, #50944\t@ 0xc700\n \tadd\tr3, pc\n \tadd.w\tr3, r3, #2304\t@ 0x900\n-\tvldr\td23, [r3, #8]\n-\tvldr\td22, [r3, #40]\t@ 0x28\n-\tvldr\td21, [r3, #72]\t@ 0x48\n-\tvldr\td20, [r3, #104]\t@ 0x68\n-\tvldr\td19, [r3]\n-\tvldr\td18, [r3, #32]\n-\tvldr\td17, [r3, #64]\t@ 0x40\n-\tvldr\td16, [r3, #96]\t@ 0x60\n-\tvadd.f64\td19, d19, d23\n-\tvadd.f64\td18, d18, d22\n-\tvldr\td23, [r3, #16]\n-\tvadd.f64\td17, d17, d21\n-\tvldr\td22, [r3, #48]\t@ 0x30\n-\tvadd.f64\td16, d16, d20\n-\tvldr\td21, [r3, #80]\t@ 0x50\n-\tvldr\td20, [r3, #112]\t@ 0x70\n-\tvadd.f64\td19, d19, d23\n-\tvadd.f64\td18, d18, d22\n-\tvldr\td23, [r3, #24]\n-\tvadd.f64\td17, d17, d21\n-\tvldr\td22, [r3, #56]\t@ 0x38\n-\tvadd.f64\td16, d16, d20\n-\tvldr\td21, [r3, #88]\t@ 0x58\n-\tvldr\td20, [r3, #120]\t@ 0x78\n-\tvadd.f64\td19, d19, d23\n-\tvadd.f64\td18, d18, d22\n-\tvadd.f64\td17, d17, d21\n-\tvadd.f64\td16, d16, d20\n-\tvstr\td19, [r3, #128]\t@ 0x80\n-\tvstr\td18, [r3, #160]\t@ 0xa0\n-\tvstr\td17, [r3, #192]\t@ 0xc0\n-\tvstr\td16, [r3, #224]\t@ 0xe0\n+\tb.n\t1cec <__gridxc_vdwxc_MOD_set_phi_table+0x964>\n+\t...\n+\t.word\t0x0000048c\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\t.word\t0x0000048e\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000000c2\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\t.word\t0x0000006c\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\t.word\t0x0000001c\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #40]\t@ 0x28\n+\tvldr\td0, [r3, #64]\t@ 0x40\n+\tvldr\td1, [r3, #96]\t@ 0x60\n+\tvldr\td5, [r3]\n+\tvldr\td6, [r3, #32]\n+\tvldr\td2, [r3, #72]\t@ 0x48\n+\tvldr\td7, [r3, #104]\t@ 0x68\n+\tvadd.f64\td5, d5, d3\n+\tvadd.f64\td6, d6, d4\n+\tvldr\td3, [r3, #80]\t@ 0x50\n+\tvadd.f64\td2, d0, d2\n+\tvldr\td4, [r3, #112]\t@ 0x70\n+\tvadd.f64\td7, d1, d7\n+\tvldr\td0, [r3, #16]\n+\tvldr\td1, [r3, #48]\t@ 0x30\n+\tvadd.f64\td5, d5, d0\n+\tvadd.f64\td3, d2, d3\n+\tvadd.f64\td6, d6, d1\n+\tvadd.f64\td7, d7, d4\n+\tvldr\td0, [r3, #24]\n+\tvldr\td1, [r3, #56]\t@ 0x38\n+\tvldr\td2, [r3, #88]\t@ 0x58\n+\tvldr\td4, [r3, #120]\t@ 0x78\n+\tvadd.f64\td5, d5, d0\n+\tvadd.f64\td6, d6, d1\n+\tvadd.f64\td3, d3, d2\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td5, [r3, #128]\t@ 0x80\n+\tvstr\td6, [r3, #160]\t@ 0xa0\n+\tvstr\td3, [r3, #192]\t@ 0xc0\n+\tvstr\td7, [r3, #224]\t@ 0xe0\n \tadd.w\tr3, r3, #2560\t@ 0xa00\n-\tcmp\tr3, r1\n-\tbne.n\t1c5a <__gridxc_vdwxc_MOD_set_phi_table+0x97a>\n-\tldr\tr3, [pc, #832]\t@ (2024 <__gridxc_vdwxc_MOD_set_phi_table+0xd44>)\n-\tadd.w\tr4, r4, #48384\t@ 0xbd00\n-\tadds\tr4, #128\t@ 0x80\n+\tcmp\tr1, r3\n+\tbne.n\t1cec <__gridxc_vdwxc_MOD_set_phi_table+0x964>\n+\tldr.w\tr3, [pc, #1136]\t@ 21e8 <__gridxc_vdwxc_MOD_set_phi_table+0xe60>\n+\tadd.w\tr5, r5, #48384\t@ 0xbd00\n+\tadds\tr5, #128\t@ 0x80\n \tadd\tr3, pc\n \tadd.w\tr3, r3, #46080\t@ 0xb400\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadds\tr2, #128\t@ 0x80\n-\tvldr\td19, [r3, #32]\n+\tvldr\td4, [r3, #32]\n \tadds\tr3, #128\t@ 0x80\n-\tvldr\td18, [r3, #-64]\t@ 0xffffffc0\n-\tvldr\td17, [r3, #-32]\t@ 0xffffffe0\n-\tcmp\tr3, r4\n-\tvadd.f64\td16, d16, d19\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r2, #-128]\t@ 0xffffff80\n-\tvldr\td19, [r3, #-88]\t@ 0xffffffa8\n-\tvldr\td16, [r3, #-120]\t@ 0xffffff88\n-\tvldr\td18, [r3, #-56]\t@ 0xffffffc8\n-\tvldr\td17, [r3, #-24]\t@ 0xffffffe8\n-\tvadd.f64\td16, d16, d19\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r2, #-120]\t@ 0xffffff88\n-\tvldr\td19, [r3, #-80]\t@ 0xffffffb0\n-\tvldr\td16, [r3, #-112]\t@ 0xffffff90\n-\tvldr\td18, [r3, #-48]\t@ 0xffffffd0\n-\tvldr\td17, [r3, #-16]\n-\tvadd.f64\td16, d16, d19\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r2, #-112]\t@ 0xffffff90\n-\tvldr\td16, [r3, #-104]\t@ 0xffffff98\n-\tvldr\td19, [r3, #-72]\t@ 0xffffffb8\n-\tvldr\td18, [r3, #-40]\t@ 0xffffffd8\n-\tvldr\td17, [r3, #-8]\n-\tvadd.f64\td16, d16, d19\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r2, #-104]\t@ 0xffffff98\n-\tbne.n\t1cf0 <__gridxc_vdwxc_MOD_set_phi_table+0xa10>\n-\tldr\tr4, [pc, #684]\t@ (2028 <__gridxc_vdwxc_MOD_set_phi_table+0xd48>)\n-\tmov.w\tsl, #0\n-\tldr\tr6, [sp, #44]\t@ 0x2c\n-\tvmov.i32\td9, #0\t@ 0x00000000\n-\tadd\tr4, pc\n-\tvldr\td16, [pc, #576]\t@ 1fc8 <__gridxc_vdwxc_MOD_set_phi_table+0xce8>\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tsub.w\tr5, r6, #1432\t@ 0x598\n-\tldr.w\tr8, [pc, #664]\t@ 202c <__gridxc_vdwxc_MOD_set_phi_table+0xd4c>\n-\tsub.w\tr7, r6, #864\t@ 0x360\n-\tvldr\td8, [pc, #564]\t@ 1fd0 <__gridxc_vdwxc_MOD_set_phi_table+0xcf0>\n-\tmov.w\tfp, #8\n-\tvldr\td18, [r3, #8]\n-\tadd\tr8, pc\n-\tvldr\td17, [r3, #16]\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvstr\td16, [r5]\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tvldr\td16, [r3]\n-\tstr.w\tr8, [r5, #8]\n-\tstr.w\tsl, [r5, #164]\t@ 0xa4\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #24]\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #32]\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #40]\t@ 0x28\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #48]\t@ 0x30\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #56]\t@ 0x38\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #64]\t@ 0x40\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #72]\t@ 0x48\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #80]\t@ 0x50\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #88]\t@ 0x58\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #96]\t@ 0x60\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvldr\td18, [r3, #104]\t@ 0x68\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #112]\t@ 0x70\n-\tadd.w\tr3, r4, #48384\t@ 0xbd00\n-\tvadd.f64\td16, d16, d18\n-\tvadd.f64\td16, d16, d17\n-\tvldr\td17, [r3, #120]\t@ 0x78\n-\tadd.w\tr3, r4, #50944\t@ 0xc700\n-\tvadd.f64\td16, d16, d17\n-\tvstr\td16, [r3, #128]\t@ 0x80\n-\tldr\tr3, [pc, #476]\t@ (2030 <__gridxc_vdwxc_MOD_set_phi_table+0xd50>)\n+\tvldr\td5, [r3, #-64]\t@ 0xffffffc0\n+\tvldr\td6, [r3, #-32]\t@ 0xffffffe0\n+\tcmp\tr3, r5\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r2, #-128]\t@ 0xffffff80\n+\tvldr\td4, [r3, #-88]\t@ 0xffffffa8\n+\tvldr\td7, [r3, #-120]\t@ 0xffffff88\n+\tvldr\td5, [r3, #-56]\t@ 0xffffffc8\n+\tvldr\td6, [r3, #-24]\t@ 0xffffffe8\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r2, #-120]\t@ 0xffffff88\n+\tvldr\td4, [r3, #-80]\t@ 0xffffffb0\n+\tvldr\td7, [r3, #-112]\t@ 0xffffff90\n+\tvldr\td5, [r3, #-48]\t@ 0xffffffd0\n+\tvldr\td6, [r3, #-16]\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r2, #-112]\t@ 0xffffff90\n+\tvldr\td7, [r3, #-104]\t@ 0xffffff98\n+\tvldr\td4, [r3, #-72]\t@ 0xffffffb8\n+\tvldr\td5, [r3, #-40]\t@ 0xffffffd8\n+\tvldr\td6, [r3, #-8]\n+\tvadd.f64\td7, d7, d4\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r2, #-104]\t@ 0xffffff98\n+\tbne.n\t1d84 <__gridxc_vdwxc_MOD_set_phi_table+0x9fc>\n+\tldr\tr7, [pc, #988]\t@ (21ec <__gridxc_vdwxc_MOD_set_phi_table+0xe64>)\n+\tmov.w\tfp, #0\n+\tldr\tr4, [sp, #92]\t@ 0x5c\n+\tmov.w\tr2, #2304\t@ 0x900\n+\tmovt\tr2, #256\t@ 0x100\n+\tadd\tr7, pc\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tsub.w\tr6, r4, #1424\t@ 0x590\n+\tldr.w\tsl, [pc, #968]\t@ 21f0 <__gridxc_vdwxc_MOD_set_phi_table+0xe68>\n+\tsub.w\tr8, r4, #864\t@ 0x360\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tsub.w\tr5, r4, #992\t@ 0x3e0\n+\tvldr\td5, [r3, #8]\n+\tadd\tsl, pc\n+\tvldr\td6, [r3, #16]\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tstr\tr2, [r6, #0]\n+\tsub.w\tr4, r4, #980\t@ 0x3d4\n+\tstr.w\tsl, [r6, #8]\n+\tvldr\td7, [r3]\n+\tstr.w\tfp, [r6, #164]\t@ 0xa4\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #24]\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #32]\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #48]\t@ 0x30\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #56]\t@ 0x38\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #64]\t@ 0x40\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #72]\t@ 0x48\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #80]\t@ 0x50\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #88]\t@ 0x58\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #96]\t@ 0x60\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvldr\td5, [r3, #104]\t@ 0x68\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #112]\t@ 0x70\n+\tadd.w\tr3, r7, #48384\t@ 0xbd00\n+\tvadd.f64\td7, d7, d5\n+\tvadd.f64\td7, d7, d6\n+\tvldr\td6, [r3, #120]\t@ 0x78\n+\tadd.w\tr3, r7, #50944\t@ 0xc700\n+\tvadd.f64\td7, d7, d6\n+\tvstr\td7, [r3, #128]\t@ 0x80\n+\tldr\tr3, [pc, #780]\t@ (21f4 <__gridxc_vdwxc_MOD_set_phi_table+0xe6c>)\n \tadd\tr3, pc\n-\tstr\tr3, [r5, #44]\t@ 0x2c\n-\tldr\tr3, [pc, #472]\t@ (2034 <__gridxc_vdwxc_MOD_set_phi_table+0xd54>)\n+\tstr\tr3, [r6, #44]\t@ 0x2c\n+\tldr\tr3, [pc, #780]\t@ (21f8 <__gridxc_vdwxc_MOD_set_phi_table+0xe70>)\n \tadd\tr3, pc\n-\tstr\tr3, [r5, #64]\t@ 0x40\n+\tstr\tr3, [r6, #64]\t@ 0x40\n \tmov.w\tr3, #1296\t@ 0x510\n-\tstr\tr3, [r5, #12]\n+\tstr\tr3, [r6, #12]\n \tmovs\tr3, #16\n-\tstr\tr3, [r5, #40]\t@ 0x28\n+\tstr\tr3, [r6, #40]\t@ 0x28\n \tmovs\tr3, #11\n-\tstr\tr3, [r5, #68]\t@ 0x44\n+\tstr\tr3, [r6, #68]\t@ 0x44\n+\tmovs\tr3, #1\n+\tstr\tr3, [r6, #4]\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tldr.w\tr9, [sp, #24]\n-\tvstr\td8, [r6, #-864]\t@ 0xfffffca0\n-\tmovw\tr3, #1297\t@ 0x511\n+\tldr.w\tr9, [sp, #56]\t@ 0x38\n+\tmovs\tr3, #1\n+\tmovw\tr2, #1297\t@ 0x511\n+\tstr.w\tr3, [r8, #4]\n \tmov\tr0, r9\n-\tstr\tr3, [r7, #12]\n-\tstr.w\tr8, [r7, #8]\n+\tstr.w\tr2, [r8, #12]\n+\tstr.w\tsl, [r8, #8]\n+\tstr.w\tfp, [r8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #428]\t@ (2038 <__gridxc_vdwxc_MOD_set_phi_table+0xd58>)\n+\tldr\tr1, [pc, #724]\t@ (21fc <__gridxc_vdwxc_MOD_set_phi_table+0xe74>)\n \tmovs\tr2, #4\n \tmov\tr0, r9\n \tadd\tr1, pc\n \tadds\tr1, #32\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n \tmov\tr0, r9\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n+\tmovs\tr3, #1\n \tmov\tr0, r9\n-\tstr.w\tr8, [r7, #8]\n-\tmovw\tr3, #1298\t@ 0x512\n-\tvstr\td8, [r6, #-864]\t@ 0xfffffca0\n-\tstr\tr3, [r7, #12]\n-\tstr.w\tr9, [sp, #24]\n+\tmovw\tr2, #1298\t@ 0x512\n+\tstr.w\tr3, [r8, #4]\n+\tstr.w\tr2, [r8, #12]\n+\tstr.w\tsl, [r8, #8]\n+\tstr.w\tfp, [r8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tvldr\td16, [pc, #288]\t@ 1fd8 <__gridxc_vdwxc_MOD_set_phi_table+0xcf8>\n-\tvldr\td17, [pc, #292]\t@ 1fe0 <__gridxc_vdwxc_MOD_set_phi_table+0xd00>\n-\tmov\tr3, r6\n-\tvstr\td9, [r6, #-980]\t@ 0xfffffc2c\n-\tsub.w\tr9, r3, #972\t@ 0x3cc\n-\tsub.w\tr6, r6, #992\t@ 0x3e0\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [pc, #364]\t@ (203c <__gridxc_vdwxc_MOD_set_phi_table+0xd5c>)\n-\tmov\tr2, fp\n-\tvst1.32\t{d16-d17}, [r9]\n+\tldr\tr1, [pc, #680]\t@ (2200 <__gridxc_vdwxc_MOD_set_phi_table+0xe78>)\n+\tmovs\tr2, #8\n+\tmovs\tr3, #1\n+\tmov\tr0, r9\n+\tstr\tr3, [r5, #28]\n+\tadd\tr1, pc\n+\tstrd\tfp, fp, [r4]\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n-\tldr\tr0, [sp, #24]\n-\tadd\tr3, pc\n-\tstr.w\tip, [r6, #4]\n+\tstr\tr2, [r5, #20]\n+\tstr\tr2, [r5, #8]\n+\tstr\tr3, [r5, #24]\n+\tmov\tr3, fp\n+\tstr\tr1, [r5, #0]\n+\tstr.w\tr9, [sp, #56]\t@ 0x38\n+\tmov.w\tr9, #20\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tstr.w\tr9, [r5, #32]\n+\tstr.w\tip, [r5, #4]\n \tmovw\tip, #769\t@ 0x301\n-\tstr\tr3, [r6, #0]\n-\tmov\tr3, sl\n-\tstrh.w\tip, [r6, #16]\n-\tstr.w\tfp, [r6, #8]\n+\tstrh.w\tip, [r5, #16]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tldr\tr0, [sp, #24]\n+\tldr\tr0, [sp, #56]\t@ 0x38\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tstr.w\tr8, [r7, #8]\n-\tldr\tr0, [sp, #24]\n-\tvstr\td8, [r3, #-864]\t@ 0xfffffca0\n-\tmovw\tr3, #1299\t@ 0x513\n-\tstr\tr3, [r7, #12]\n+\tmovs\tr3, #1\n+\tmovw\tr1, #1299\t@ 0x513\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tstr.w\tr3, [r8, #4]\n+\tstr.w\tr1, [r8, #12]\n+\tstr.w\tsl, [r8, #8]\n+\tstr.w\tfp, [r8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tstr\tr4, [r6, #0]\n-\tvldr\td16, [pc, #208]\t@ 1fe8 <__gridxc_vdwxc_MOD_set_phi_table+0xd08>\n-\tvldr\td17, [pc, #212]\t@ 1ff0 <__gridxc_vdwxc_MOD_set_phi_table+0xd10>\n-\tmov\tr3, sl\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tmov\tr2, fp\n-\tvldr\td18, [pc, #212]\t@ 1ff8 <__gridxc_vdwxc_MOD_set_phi_table+0xd18>\n-\tvldr\td19, [pc, #216]\t@ 2000 <__gridxc_vdwxc_MOD_set_phi_table+0xd20>\n-\tsub.w\tr0, r4, #956\t@ 0x3bc\n-\tvst1.32\t{d16-d17}, [r9]\n-\tldr\tr7, [sp, #24]\n-\tvldr\td16, [pc, #208]\t@ 2008 <__gridxc_vdwxc_MOD_set_phi_table+0xd28>\n-\tvldr\td17, [pc, #212]\t@ 2010 <__gridxc_vdwxc_MOD_set_phi_table+0xd30>\n-\tvstr\td9, [r4, #-980]\t@ 0xfffffc2c\n-\tstr.w\tfp, [r6, #8]\n-\tvst1.32\t{d18-d19}, [r0]\n-\tsub.w\tr0, r4, #940\t@ 0x3ac\n-\tldr\tr1, [sp, #60]\t@ 0x3c\n+\tmovs\tr3, #16\n+\tstr\tr7, [r5, #0]\n+\tmovs\tr2, #8\n+\tstr\tr3, [r5, #48]\t@ 0x30\n+\tmovs\tr3, #1\n+\tstrd\tfp, fp, [r4]\n+\tmovs\tr4, #3\n+\tstrd\tr3, r9, [r5, #52]\t@ 0x34\n+\tstrd\tr3, r9, [r5, #64]\t@ 0x40\n+\tldr.w\tr9, [sp, #56]\t@ 0x38\n+\tldr\tr1, [sp, #84]\t@ 0x54\n+\tmov\tr0, r9\n+\tstr\tr2, [r5, #20]\n+\tstr\tr2, [r5, #8]\n+\tstr\tr3, [r5, #24]\n+\tmov\tr3, fp\n+\tstr\tr4, [r5, #32]\n+\tstr\tr4, [r5, #44]\t@ 0x2c\n \tmov.w\tr4, #772\t@ 0x304\n-\tvst1.32\t{d16-d17}, [r0]\n-\tmov\tr0, r7\n-\tstrh\tr4, [r6, #16]\n-\tmovs\tr4, #20\n-\tstr\tr4, [r6, #68]\t@ 0x44\n+\tstr.w\tfp, [r5, #28]\n+\tstrh\tr4, [r5, #16]\n+\tmovs\tr4, #4\n+\tstr.w\tfp, [r5, #40]\t@ 0x28\n+\tstr\tr4, [r5, #36]\t@ 0x24\n+\tmov.w\tr4, #320\t@ 0x140\n+\tstr\tr4, [r5, #60]\t@ 0x3c\n \tmovw\tr4, #65200\t@ 0xfeb0\n \tmovt\tr4, #65535\t@ 0xffff\n-\tstr\tr4, [r6, #4]\n+\tstr\tr4, [r5, #4]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tmov\tr0, r7\n+\tmov\tr0, r9\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n+\tmovs\tr3, #1\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tstr\tr3, [r6, #4]\n \tmovw\tr3, #1300\t@ 0x514\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tstr.w\tr8, [r5, #8]\n-\tstr\tr3, [r5, #12]\n-\tvstr\td8, [r5]\n+\tstr.w\tsl, [r6, #8]\n+\tstr.w\tfp, [r6]\n+\tstr\tr3, [r6, #12]\n \tbl\t0 <_gfortran_st_close>\n R_ARM_THM_CALL\t_gfortran_st_close\n-\tldr\tr3, [pc, #184]\t@ (2040 <__gridxc_vdwxc_MOD_set_phi_table+0xd60>)\n+\tldr\tr3, [pc, #476]\t@ (2204 <__gridxc_vdwxc_MOD_set_phi_table+0xe7c>)\n \tmovs\tr2, #1\n \tadd.w\tr1, sp, #13824\t@ 0x3600\n \tadd\tr3, pc\n-\tadds\tr1, #20\n+\tadds\tr1, #44\t@ 0x2c\n \tstr.w\tr2, [r3, #432]\t@ 0x1b0\n-\tldr\tr2, [pc, #172]\t@ (2044 <__gridxc_vdwxc_MOD_set_phi_table+0xd64>)\n-\tldr\tr3, [pc, #172]\t@ (2048 <__gridxc_vdwxc_MOD_set_phi_table+0xd68>)\n+\tldr\tr2, [pc, #464]\t@ (2208 <__gridxc_vdwxc_MOD_set_phi_table+0xe80>)\n+\tldr\tr3, [pc, #468]\t@ (220c <__gridxc_vdwxc_MOD_set_phi_table+0xe84>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2200 <__gridxc_vdwxc_MOD_set_phi_table+0xf20>\n+\tbne.w\t21e4 <__gridxc_vdwxc_MOD_set_phi_table+0xe5c>\n \tadd.w\tsp, sp, #13824\t@ 0x3600\n-\tadd\tsp, #28\n+\tadd\tsp, #52\t@ 0x34\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadds\tr6, #168\t@ 0xa8\n-\tadd.w\tr8, r8, #160\t@ 0xa0\n-\tmovs\tr7, #2\n-\tb.w\t1400 <__gridxc_vdwxc_MOD_set_phi_table+0x120>\n-\tnop\n-\t.word\t0x01000900\n-\t.word\t0x00000001\n-\t.word\t0x00000000\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000014\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000000\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n-\t.word\t0x00000000\n-\t.word\t0x00000003\n-\t.word\t0x00000010\n-\t.word\t0x00000001\n-\t.word\t0x00000014\n-\t.word\t0x00000140\n-\t.word\t0x00000001\n-\t.word\t0x00000470\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x00000418\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x000003c8\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x00000336\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x000002a0\n- R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x00000282\n- R_ARM_REL32\t.LC11\n-\t.word\t0x000001d8\n- R_ARM_REL32\t.LC12\n-\t.word\t0x000001d6\n- R_ARM_REL32\t.LC13\n-\t.word\t0x000001a6\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000015c\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000ae\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000a6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\tvldr\td16, [pc, #440]\t@ 2208 <__gridxc_vdwxc_MOD_set_phi_table+0xf28>\n-\tmov.w\tr9, #0\n-\tstrd\tr5, r6, [r4, #40]\t@ 0x28\n-\tadd.w\tr5, sp, #10624\t@ 0x2980\n-\tadds\tr5, #16\n-\tldr\tr3, [pc, #512]\t@ (2260 <__gridxc_vdwxc_MOD_set_phi_table+0xf80>)\n-\tvldr\td8, [pc, #428]\t@ 2210 <__gridxc_vdwxc_MOD_set_phi_table+0xf30>\n-\tsubs\tr7, #28\n-\tvstr\td16, [r4]\n-\tadd\tr3, pc\n-\tldr\tr0, [sp, #68]\t@ 0x44\n-\tstr\tr3, [r4, #64]\t@ 0x40\n-\tmovs\tr3, #11\n+\tldr\tr2, [pc, #436]\t@ (2210 <__gridxc_vdwxc_MOD_set_phi_table+0xe88>)\n+\tmovs\tr3, #16\n+\tmovs\tr6, #1\n+\tstr\tr3, [r4, #40]\t@ 0x28\n+\tadd\tr2, pc\n+\tstr\tr5, [r4, #44]\t@ 0x2c\n+\tstr\tr2, [r4, #64]\t@ 0x40\n+\tmovs\tr2, #11\n \tstr.w\tsl, [r4, #8]\n-\tstr\tr3, [r4, #68]\t@ 0x44\n-\tmovw\tr3, #1118\t@ 0x45e\n-\tstr.w\tr9, [r4, #164]\t@ 0xa4\n-\tstr\tr3, [r4, #12]\n+\tmovs\tr7, #8\n+\tstr\tr2, [r4, #68]\t@ 0x44\n+\tmovw\tr2, #1118\t@ 0x45e\n+\tstr.w\tfp, [r4, #164]\t@ 0xa4\n+\tsub.w\tr8, r8, #20\n+\tstr\tr2, [r4, #12]\n+\tmov.w\tr2, #2304\t@ 0x900\n+\tmovt\tr2, #256\t@ 0x100\n+\tstr\tr6, [r4, #4]\n+\tstr\tr2, [r4, #0]\n+\tadd.w\tr4, sp, #10624\t@ 0x2980\n+\tadds\tr4, #40\t@ 0x28\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tmovw\tr3, #1119\t@ 0x45f\n-\tmov\tr0, r5\n-\tstr\tr3, [r5, #12]\n-\tstr.w\tsl, [r5, #8]\n-\tvstr\td8, [r5]\n+\tmovw\tr2, #1119\t@ 0x45f\n+\tmov\tr0, r4\n+\tstr\tr2, [r4, #12]\n+\tstrd\tr6, sl, [r4, #4]\n+\tstr\tr7, [r4, #0]\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n \tmovs\tr2, #4\n-\tmov\tr1, r7\n-\tmov\tr0, r5\n+\tmov\tr1, r8\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer>\n R_ARM_THM_CALL\t_gfortran_transfer_integer\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr\tr3, [r5, #0]\n-\tand.w\tr3, r3, #3\n-\tcmp\tr3, #2\n-\tbeq.w\t21ee <__gridxc_vdwxc_MOD_set_phi_table+0xf0e>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tsubw\tr3, r3, #1436\t@ 0x59c\n-\tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tcmp\tr3, #20\n-\tbne.w\t21cc <__gridxc_vdwxc_MOD_set_phi_table+0xeec>\n-\tmovw\tr3, #1121\t@ 0x461\n-\tmov\tr0, r5\n-\tstr\tr3, [r5, #12]\n-\tadd.w\tr8, sp, #9728\t@ 0x2600\n-\tstr.w\tsl, [r5, #8]\n-\tadd.w\tr8, r8, #24\n-\tvstr\td8, [r5]\n-\tvmov.i32\td9, #0\t@ 0x00000000\n+\tldr\tr2, [r4, #0]\n+\tand.w\tr2, r2, #3\n+\tcmp\tr2, #2\n+\tbeq.w\t1422 <__gridxc_vdwxc_MOD_set_phi_table+0x9a>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tsubw\tr2, r3, #1428\t@ 0x594\n+\tldr.w\tr9, [r2]\n+\tcmp.w\tr9, #20\n+\tbne.n\t21c2 <__gridxc_vdwxc_MOD_set_phi_table+0xe3a>\n+\tmovw\tr2, #1121\t@ 0x461\n+\tmov\tr0, r4\n+\tstr\tr2, [r4, #12]\n+\tstr.w\tsl, [r4, #8]\n+\tstrd\tr7, r6, [r4]\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n-\tsubw\tr6, r8, #2312\t@ 0x908\n-\tvldr\td16, [pc, #300]\t@ 2218 <__gridxc_vdwxc_MOD_set_phi_table+0xf38>\n-\tvldr\td17, [pc, #304]\t@ 2220 <__gridxc_vdwxc_MOD_set_phi_table+0xf40>\n-\tsubw\tr2, r8, #2300\t@ 0x8fc\n-\tsubw\tr1, r8, #2292\t@ 0x8f4\n-\tldr\tr3, [pc, #360]\t@ (2264 <__gridxc_vdwxc_MOD_set_phi_table+0xf84>)\n-\tmov\tr0, r5\n+\tadd.w\tr3, sp, #9728\t@ 0x2600\n+\tadds\tr3, #48\t@ 0x30\n+\tadd.w\tr2, sp, #7456\t@ 0x1d20\n+\tsubw\tr5, r3, #2312\t@ 0x908\n+\tsubw\tr3, r3, #2300\t@ 0x8fc\n+\tadds\tr2, #16\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tldr\tr2, [pc, #276]\t@ (2214 <__gridxc_vdwxc_MOD_set_phi_table+0xe8c>)\n+\tmov\tr1, r5\n+\tstr\tr7, [r5, #20]\n+\tmov\tr0, r4\n+\tstr.w\tfp, [r3, #4]\n+\tadd\tr2, pc\n+\tstr.w\tfp, [r3]\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n-\tvstr\td9, [r2]\n-\tadd\tr3, pc\n-\tvst1.32\t{d16-d17}, [r1]\n-\tadd.w\tfp, sp, #7424\t@ 0x1d00\n-\tadd.w\tfp, fp, #24\n-\tstr\tr2, [sp, #16]\n-\tmovs\tr2, #8\n-\tstr\tr1, [sp, #24]\n-\tmov\tr1, r6\n-\tstr\tr2, [r6, #8]\n-\tmov\tr4, r6\n-\tstr\tr3, [r6, #0]\n-\tmov\tr3, r9\n-\tstr.w\tip, [r6, #4]\n+\tstr\tr3, [sp, #16]\n+\tmov\tr3, fp\n+\tstr\tr2, [r5, #0]\n+\tmov\tr2, r7\n+\tstr.w\tip, [r5, #4]\n \tmovw\tip, #769\t@ 0x301\n-\tstrh.w\tip, [r6, #16]\n+\tstr\tr7, [r5, #8]\n+\tstrh.w\tip, [r5, #16]\n+\tstrd\tr6, r9, [r5, #28]\n+\tstr\tr6, [r5, #24]\n+\tstr\tr5, [sp, #52]\t@ 0x34\n \tbl\t0 <_gfortran_transfer_array>\n R_ARM_THM_CALL\t_gfortran_transfer_array\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr\tr3, [r5, #0]\n-\tand.w\tr3, r3, #3\n-\tcmp\tr3, #2\n-\tbeq.w\t1384 <__gridxc_vdwxc_MOD_set_phi_table+0xa4>\n-\tmovw\tr3, #1122\t@ 0x462\n-\tmov\tr0, r5\n-\tstr\tr3, [r5, #12]\n-\tstr.w\tsl, [r5, #8]\n-\tvstr\td8, [r5]\n+\tldr\tr2, [r4, #0]\n+\tand.w\tr2, r2, #3\n+\tcmp\tr2, #2\n+\tbeq.w\t1432 <__gridxc_vdwxc_MOD_set_phi_table+0xaa>\n+\tmovw\tr2, #1122\t@ 0x462\n+\tmov\tr0, r4\n+\tstrd\tr7, r6, [r4]\n+\tstr\tr2, [r4, #12]\n+\tstr.w\tsl, [r4, #8]\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n-\tldr\tr2, [sp, #16]\n-\tldr\tr1, [sp, #24]\n-\tmov\tr0, r5\n-\tvldr\td16, [pc, #196]\t@ 2228 <__gridxc_vdwxc_MOD_set_phi_table+0xf48>\n-\tvldr\td17, [pc, #200]\t@ 2230 <__gridxc_vdwxc_MOD_set_phi_table+0xf50>\n-\tmov.w\tip, #772\t@ 0x304\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tvldr\td18, [pc, #200]\t@ 2238 <__gridxc_vdwxc_MOD_set_phi_table+0xf58>\n-\tvldr\td19, [pc, #204]\t@ 2240 <__gridxc_vdwxc_MOD_set_phi_table+0xf60>\n-\tvstr\td9, [r2]\n-\tstr\tr3, [r6, #68]\t@ 0x44\n-\tmovs\tr2, #8\n-\tvst1.32\t{d16-d17}, [r1]\n-\tsubw\tr1, r8, #2276\t@ 0x8e4\n-\tsubw\tr8, r8, #2260\t@ 0x8d4\n-\tvldr\td16, [pc, #188]\t@ 2248 <__gridxc_vdwxc_MOD_set_phi_table+0xf68>\n-\tvldr\td17, [pc, #192]\t@ 2250 <__gridxc_vdwxc_MOD_set_phi_table+0xf70>\n-\tstr\tr2, [r6, #8]\n-\tvst1.32\t{d18-d19}, [r1]\n-\tmov\tr3, r9\n-\tldr\tr1, [pc, #204]\t@ (2268 <__gridxc_vdwxc_MOD_set_phi_table+0xf88>)\n-\tvst1.32\t{d16-d17}, [r8]\n+\tldr\tr3, [sp, #16]\n+\tldr\tr1, [pc, #184]\t@ (2218 <__gridxc_vdwxc_MOD_set_phi_table+0xe90>)\n+\tmovs\tr0, #16\n+\tmov\tr2, r7\n+\tstr\tr0, [r5, #48]\t@ 0x30\n \tadd\tr1, pc\n-\tstrh.w\tip, [r6, #16]\n-\tmovw\tip, #65200\t@ 0xfeb0\n-\tmovt\tip, #65535\t@ 0xffff\n-\tstr\tr1, [r6, #0]\n-\tstr.w\tip, [r6, #4]\n-\tmov\tr1, r6\n+\tstrd\tfp, fp, [r3]\n+\tmov\tr0, r4\n+\tmov\tr3, fp\n+\tstrd\tr6, fp, [r5, #24]\n+\tstr\tr6, [r5, #52]\t@ 0x34\n+\tstr\tr6, [r5, #64]\t@ 0x40\n+\tmovs\tr6, #3\n+\tstr\tr1, [r5, #0]\n+\tstr\tr6, [r5, #32]\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tstr\tr6, [r5, #44]\t@ 0x2c\n+\tmov.w\tr6, #772\t@ 0x304\n+\tstr\tr7, [r5, #20]\n+\tstrh\tr6, [r5, #16]\n+\tmovs\tr6, #4\n+\tstr\tr7, [r5, #8]\n+\tstr\tr6, [r5, #36]\t@ 0x24\n+\tmov.w\tr6, #320\t@ 0x140\n+\tstr.w\tfp, [r5, #40]\t@ 0x28\n+\tstr\tr6, [r5, #60]\t@ 0x3c\n+\tmovw\tr6, #65200\t@ 0xfeb0\n+\tmovt\tr6, #65535\t@ 0xffff\n+\tstr.w\tr9, [r5, #56]\t@ 0x38\n+\tstr.w\tr9, [r5, #68]\t@ 0x44\n+\tstr\tr6, [r5, #4]\n \tbl\t0 <_gfortran_transfer_array>\n R_ARM_THM_CALL\t_gfortran_transfer_array\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr\tr3, [r5, #0]\n+\tldr\tr3, [r4, #0]\n \tand.w\tr3, r3, #3\n \tcmp\tr3, #2\n-\tbeq.w\t1384 <__gridxc_vdwxc_MOD_set_phi_table+0xa4>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tmovw\tr1, #1124\t@ 0x464\n-\tvldr\td16, [pc, #132]\t@ 2258 <__gridxc_vdwxc_MOD_set_phi_table+0xf78>\n-\tsub.w\tr3, r3, #1432\t@ 0x598\n-\tldr\tr2, [pc, #144]\t@ (226c <__gridxc_vdwxc_MOD_set_phi_table+0xf8c>)\n-\tldr\tr0, [sp, #68]\t@ 0x44\n+\tbeq.w\t1432 <__gridxc_vdwxc_MOD_set_phi_table+0xaa>\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tmovs\tr5, #0\n+\tldr\tr2, [pc, #84]\t@ (221c <__gridxc_vdwxc_MOD_set_phi_table+0xe94>)\n+\tmovs\tr1, #1\n+\tsub.w\tr3, r3, #1424\t@ 0x590\n+\tmovw\tr4, #1124\t@ 0x464\n \tadd\tr2, pc\n-\tvstr\td16, [r3]\n-\tstrd\tr2, r1, [r3, #8]\n+\tldr\tr0, [sp, #96]\t@ 0x60\n+\tstr\tr5, [r3, #0]\n+\tstrd\tr2, r4, [r3, #8]\n+\tstr\tr1, [r3, #4]\n \tbl\t0 <_gfortran_st_close>\n R_ARM_THM_CALL\t_gfortran_st_close\n-\tb.n\t1f86 <__gridxc_vdwxc_MOD_set_phi_table+0xca6>\n-\tadd.w\tfp, sp, #7424\t@ 0x1d00\n-\tadd.w\tr4, sp, #7424\t@ 0x1d00\n-\tadd.w\tfp, fp, #24\n-\tadds\tr4, #16\n-\tb.w\t1384 <__gridxc_vdwxc_MOD_set_phi_table+0xa4>\n+\tb.n\t2024 <__gridxc_vdwxc_MOD_set_phi_table+0xc9c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x01000900\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000014\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000000\n-\t.word\t0x00000003\n-\t.word\t0x00000004\n-\t.word\t0x00000000\n-\t.word\t0x00000003\n-\t.word\t0x00000010\n-\t.word\t0x00000001\n-\t.word\t0x00000014\n-\t.word\t0x00000140\n-\t.word\t0x00000001\n+\t.word\t0x00000466\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\t.word\t0x000003cc\n+ R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n+\t.word\t0x000003b4\n+ R_ARM_REL32\t.LC11\n+\t.word\t0x0000030a\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x00000308\n+ R_ARM_REL32\t.LC13\n+\t.word\t0x000002cc\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000029c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001d4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001cc\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n-\t.word\t0x00000001\n-\t.word\t0x000001f2\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000001ac\n R_ARM_REL32\t.LC13\n-\t.word\t0x0000015a\n+\t.word\t0x00000106\n R_ARM_REL32\t.bss\n-\t.word\t0x000000c4\n+\t.word\t0x000000ae\n R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x0000008a\n+\t.word\t0x00000046\n R_ARM_REL32\t.LC11\n \n-00002270 <__gridxc_vdwxc_MOD_qofrho.isra.0>:\n+00002220 <__gridxc_vdwxc_MOD_qofrho.isra.0>:\n __gridxc_vdwxc_MOD_qofrho.isra.0():\n \tpush\t{r4, r5, r6, r7, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d14}\n+\tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3912]\t@ 0xf48\n-\tvldr\td16, [pc, #644]\t@ 2508 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x298>\n-\tsub\tsp, #108\t@ 0x6c\n-\tldr\tr5, [pc, #724]\t@ (2560 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f0>)\n-\tmov\tr7, r1\n-\tldr\tr4, [pc, #724]\t@ (2564 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f4>)\n-\tmov\tr6, r2\n-\tvcmpe.f64\td0, d16\n+\tstr.w\tr0, [ip, #3888]\t@ 0xf30\n+\tvldr\td7, [pc, #668]\t@ 24d0 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2b0>\n+\tsub\tsp, #124\t@ 0x7c\n+\tldr\tr5, [pc, #748]\t@ (2528 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x308>)\n+\tmov\tr6, r1\n+\tldr\tr4, [pc, #748]\t@ (252c <__gridxc_vdwxc_MOD_qofrho.isra.0+0x30c>)\n+\tmov\tr7, r2\n+\tvcmpe.f64\td0, d7\n \tadd\tr5, pc\n \tldr\tr4, [r5, r4]\n \tvmrs\tAPSR_nzcv, fpscr\n \tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #100]\t@ 0x64\n+\tstr\tr4, [sp, #116]\t@ 0x74\n \tmov.w\tr4, #0\n \tmov\tr4, r3\n-\tbls.w\t24de <__gridxc_vdwxc_MOD_qofrho.isra.0+0x26e>\n+\tbls.w\t24a2 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x282>\n \tvmov.f64\td9, d0\n-\tvldr\td0, [pc, #608]\t@ 2510 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2a0>\n+\tvldr\td0, [pc, #632]\t@ 24d8 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2b8>\n \tmov\tr5, r0\n-\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td11, d8\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n \tvmul.f64\td0, d9, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tldr\tr1, [pc, #672]\t@ (2568 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f8>)\n-\tldr\tr0, [pc, #676]\t@ (256c <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2fc>)\n+\tldr\tr1, [pc, #700]\t@ (2530 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x310>)\n+\tldr\tr0, [pc, #704]\t@ (2534 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x314>)\n \tmovs\tr3, #0\n \tadd\tr1, pc\n \tstrd\tr3, r3, [sp, #28]\n \tadd.w\tr2, r1, #2112\t@ 0x840\n \tadd\tr0, pc\n \taddw\tr1, r1, #2116\t@ 0x844\n \tstr\tr3, [sp, #24]\n \tmovs\tr3, #4\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #56\t@ 0x38\n+\tadd\tr3, sp, #72\t@ 0x48\n \tstr\tr3, [sp, #20]\n-\tadd\tr3, sp, #64\t@ 0x40\n-\tstr\tr3, [sp, #16]\n \tadd\tr3, sp, #80\t@ 0x50\n+\tstr\tr3, [sp, #16]\n+\tadd\tr3, sp, #96\t@ 0x60\n \tstr\tr3, [sp, #12]\n-\tadd\tr3, sp, #88\t@ 0x58\n+\tadd\tr3, sp, #104\t@ 0x68\n \tstr\tr3, [sp, #8]\n-\tadd\tr3, sp, #40\t@ 0x28\n+\tadd\tr3, sp, #56\t@ 0x38\n \tstr\tr3, [sp, #4]\n-\tadd\tr3, sp, #48\t@ 0x30\n+\tadd\tr3, sp, #64\t@ 0x40\n \tstr\tr3, [sp, #0]\n-\tadd\tr3, sp, #72\t@ 0x48\n+\tadd\tr3, sp, #88\t@ 0x58\n \tvmov.f64\td10, d0\n-\tvstr\td9, [sp, #72]\t@ 0x48\n+\tvstr\td9, [sp, #88]\t@ 0x58\n \tbl\t0 <__gridxc_lda_MOD_ldaxc>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_ldaxc\n-\tvldr\td13, [r5, #8]\n-\tvadd.f64\td30, d9, d9\n-\tvldr\td12, [r5]\n-\tvmov.f64\td26, #64\t@ 0x3e000000 0.125\n-\tvldr\td25, [r5, #16]\n-\tvmov.f64\td0, d8\n-\tvmul.f64\td16, d13, d13\n-\tldr\tr3, [pc, #588]\t@ (2570 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x300>)\n-\tvfma.f64\td16, d12, d12\n-\tvmul.f64\td30, d30, d10\n-\tadd\tr3, pc\n-\tvldr\td20, [sp, #48]\t@ 0x30\n-\tvldr\td31, [sp, #88]\t@ 0x58\n-\tvldr\td3, [sp, #40]\t@ 0x28\n-\tvfma.f64\td16, d25, d25\n-\tvmul.f64\td29, d30, d30\n-\tvldr\td24, [r3, #16]\n-\tvldr\td21, [pc, #464]\t@ 2518 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2a8>\n-\tvdiv.f64\td17, d3, d20\n-\tvldr\td22, [pc, #464]\t@ 2520 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2b0>\n-\tvmul.f64\td2, d30, d29\n-\tvsub.f64\td30, d31, d20\n-\tvldr\td7, [pc, #460]\t@ 2528 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2b8>\n-\tvmul.f64\td6, d10, d22\n-\tvldr\td28, [pc, #460]\t@ 2530 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2c0>\n-\tvldr\td23, [pc, #464]\t@ 2538 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2c8>\n-\tvmul.f64\td16, d24, d16\n-\tvmul.f64\td24, d24, d21\n-\tvdiv.f64\td1, d30, d9\n-\tvldr\td27, [pc, #456]\t@ 2540 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2d0>\n-\tvdiv.f64\td31, d6, d9\n-\tvldr\td5, [pc, #456]\t@ 2548 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2d8>\n-\tvldr\td4, [pc, #460]\t@ 2550 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2e0>\n-\tvdiv.f64\td6, d24, d29\n-\tvmul.f64\td30, d16, d21\n-\tvdiv.f64\td24, d30, d29\n-\tvmov.f64\td29, #80\t@ 0x3e800000 0.250\n-\tvadd.f64\td17, d17, d8\n-\tvsub.f64\td17, d17, d24\n-\tvmul.f64\td17, d17, d10\n-\tvfma.f64\td28, d17, d7\n-\tvmul.f64\td24, d17, d23\n-\tvdiv.f64\td14, d17, d10\n-\tvadd.f64\td17, d24, d8\n-\tvfma.f64\td27, d24, d28\n-\tvmov.f64\td28, d8\n-\tvfma.f64\td28, d24, d17\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvfma.f64\td21, d24, d27\n-\tvmov.f64\td27, d8\n-\tvfma.f64\td27, d24, d28\n-\tvmov.f64\td28, d10\n-\tvfma.f64\td28, d31, d9\n-\tvmul.f64\td9, d20, d9\n-\tvmul.f64\td20, d20, d20\n-\tvfma.f64\td26, d24, d21\n-\tvmov.f64\td21, d8\n-\tvfma.f64\td21, d24, d27\n-\tvmov.f64\td27, d8\n-\tvmul.f64\td14, d14, d31\n-\tvfma.f64\td5, d24, d26\n-\tvmov.f64\td26, d8\n-\tvfma.f64\td26, d24, d21\n-\tvdiv.f64\td21, d3, d20\n-\tvmov.f64\td20, d8\n-\tvfma.f64\td4, d24, d5\n-\tvfma.f64\td27, d24, d26\n-\tvmov.f64\td26, d8\n-\tvfma.f64\td23, d24, d4\n-\tvfma.f64\td20, d24, d27\n-\tvfma.f64\td29, d24, d23\n-\tvmov.f64\td23, d8\n-\tvfma.f64\td23, d24, d20\n-\tvmov.f64\td20, d8\n-\tvfma.f64\td22, d24, d29\n-\tvfma.f64\td26, d24, d23\n-\tvmov.f64\td23, #128\t@ 0xc0000000 -2.0\n-\tvmul.f64\td23, d10, d23\n-\tvmul.f64\td6, d6, d23\n-\tvfma.f64\td17, d24, d22\n-\tvldr\td22, [pc, #276]\t@ 2558 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2e8>\n-\tvfma.f64\td20, d24, d26\n-\tvmul.f64\td22, d16, d22\n-\tvmul.f64\td12, d6, d12\n-\tvmul.f64\td13, d6, d13\n-\tvfma.f64\td0, d24, d17\n-\tvldr\td17, [sp, #80]\t@ 0x50\n-\tvfma.f64\td11, d24, d20\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tvsub.f64\td17, d17, d3\n-\tvdiv.f64\td16, d17, d9\n-\tvmul.f64\td9, d6, d25\n-\tvdiv.f64\td17, d22, d2\n-\tvnmul.f64\td0, d0, d24\n-\tvfms.f64\td16, d1, d21\n-\tvmul.f64\td17, d17, d28\n-\tvfma.f64\td16, d17, d20\n-\tvfma.f64\td14, d10, d16\n+\tvadd.f64\td7, d9, d9\n+\tvldr\td11, [r5]\n+\tvldr\td12, [r5, #8]\n+\tvldr\td13, [r5, #16]\n+\tvmul.f64\td5, d11, d11\n+\tldr\tr3, [pc, #624]\t@ (2538 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x318>)\n+\tvmul.f64\td7, d7, d10\n+\tvmla.f64\td5, d12, d12\n+\tadd\tr3, pc\n+\tvldr\td6, [sp, #64]\t@ 0x40\n+\tvldr\td2, [sp, #56]\t@ 0x38\n+\tvldr\td0, [pc, #516]\t@ 24e0 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2c0>\n+\tvmul.f64\td4, d7, d7\n+\tvmla.f64\td5, d13, d13\n+\tvldr\td1, [pc, #512]\t@ 24e8 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2c8>\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td7, [r3, #16]\n+\tvmul.f64\td15, d5, d7\n+\tvldr\td5, [pc, #500]\t@ 24f0 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2d0>\n+\tvmul.f64\td7, d7, d5\n+\tvdiv.f64\td3, d7, d4\n+\tvdiv.f64\td7, d2, d6\n+\tvmul.f64\td2, d15, d5\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tvdiv.f64\td3, d2, d4\n+\tvadd.f64\td7, d7, d14\n+\tvldr\td4, [pc, #476]\t@ 24f8 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2d8>\n+\tvmov.f64\td2, #64\t@ 0x3e000000 0.125\n+\tvsub.f64\td7, d7, d3\n+\tvldr\td3, [pc, #472]\t@ 2500 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2e0>\n+\tvmul.f64\td7, d7, d10\n+\tvmla.f64\td0, d7, d4\n+\tvldr\td4, [pc, #468]\t@ 2508 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2e8>\n+\tvmul.f64\td8, d7, d4\n+\tvmla.f64\td1, d8, d0\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvmla.f64\td5, d8, d1\n+\tvdiv.f64\td1, d7, d10\n+\tvldr\td7, [pc, #452]\t@ 2510 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f0>\n+\tvmla.f64\td2, d8, d5\n+\tvldr\td5, [sp, #56]\t@ 0x38\n+\tvmla.f64\td3, d8, d2\n+\tvmul.f64\td2, d10, d7\n+\tvdiv.f64\td7, d2, d9\n+\tvmov.f64\td2, d10\n+\tvmla.f64\td2, d7, d9\n+\tvmul.f64\td1, d1, d7\n+\tvldr\td7, [pc, #424]\t@ 2518 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f8>\n+\tvmla.f64\td7, d8, d3\n+\tvadd.f64\td2, d2, d2\n+\tvmla.f64\td4, d8, d7\n+\tvldr\td7, [sp, #96]\t@ 0x60\n+\tvsub.f64\td7, d7, d5\n+\tvldr\td5, [sp, #104]\t@ 0x68\n+\tvsub.f64\td5, d5, d6\n+\tvdiv.f64\td3, d5, d9\n+\tvmul.f64\td9, d6, d9\n+\tvmul.f64\td6, d6, d6\n+\tvdiv.f64\td5, d7, d9\n+\tvdiv.f64\td7, d0, d6\n+\tvldr\td6, [pc, #380]\t@ 2520 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x300>\n+\tvmov.f64\td0, d14\n+\tvmul.f64\td6, d15, d6\n+\tvmls.f64\td5, d3, d7\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td3, [sp, #48]\t@ 0x30\n+\tvdiv.f64\td7, d6, d7\n+\tvldr\td6, [pc, #336]\t@ 2510 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f0>\n+\tvmla.f64\td5, d2, d7\n+\tvmov.f64\td7, #80\t@ 0x3e800000 0.250\n+\tvmla.f64\td7, d8, d4\n+\tvmla.f64\td1, d5, d10\n+\tvmla.f64\td6, d8, d7\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmov.f64\td9, d1\n+\tvmla.f64\td7, d8, d6\n+\tvmla.f64\td0, d8, d7\n+\tvmov.f64\td7, #128\t@ 0xc0000000 -2.0\n+\tvmul.f64\td10, d10, d7\n+\tvmul.f64\td10, d3, d10\n+\tvnmul.f64\td0, d0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmul.f64\td11, d11, d0\n-\tvsub.f64\td8, d8, d0\n-\tvmov.f64\td16, #20\t@ 0x40a00000 5.0\n-\tvmul.f64\td12, d11, d12\n-\tvmul.f64\td8, d8, d16\n-\tvmul.f64\td13, d11, d13\n-\tvmul.f64\td9, d9, d11\n-\tvmul.f64\td14, d14, d11\n-\tvstr\td8, [r7]\n-\tvstr\td12, [r4]\n-\tvstr\td13, [r4, #8]\n-\tvstr\td14, [r6]\n-\tvstr\td9, [r4, #16]\n-\tldr\tr2, [pc, #176]\t@ (2574 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x304>)\n-\tldr\tr3, [pc, #156]\t@ (2564 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2f4>)\n+\tvmov.f64\td4, d8\n+\tvmla.f64\td4, d8, d8\n+\tvmov.f64\td3, d8\n+\tvsub.f64\td7, d14, d0\n+\tvmul.f64\td6, d10, d11\n+\tvmul.f64\td5, d10, d12\n+\tvmul.f64\td10, d10, d13\n+\tvmla.f64\td3, d4, d8\n+\tvmov.f64\td4, d8\n+\tvmla.f64\td4, d3, d8\n+\tvmov.f64\td3, d8\n+\tvmla.f64\td3, d4, d8\n+\tvmov.f64\td4, d8\n+\tvmla.f64\td4, d3, d8\n+\tvmov.f64\td3, d8\n+\tvmla.f64\td3, d4, d8\n+\tvmov.f64\td4, d8\n+\tvmla.f64\td4, d3, d8\n+\tvmov.f64\td3, d8\n+\tvmla.f64\td3, d4, d8\n+\tvmov.f64\td4, d8\n+\tvmla.f64\td4, d3, d8\n+\tvmla.f64\td8, d4, d8\n+\tvmla.f64\td0, d8, d0\n+\tvmul.f64\td6, d6, d0\n+\tvmul.f64\td9, d9, d0\n+\tvmul.f64\td5, d5, d0\n+\tvmul.f64\td10, d10, d0\n+\tvstr\td6, [r4]\n+\tvmov.f64\td6, #20\t@ 0x40a00000 5.0\n+\tvstr\td9, [r7]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td5, [r4, #8]\n+\tvstr\td10, [r4, #16]\n+\tvstr\td7, [r6]\n+\tldr\tr2, [pc, #180]\t@ (253c <__gridxc_vdwxc_MOD_qofrho.isra.0+0x31c>)\n+\tldr\tr3, [pc, #160]\t@ (252c <__gridxc_vdwxc_MOD_qofrho.isra.0+0x30c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t2500 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x290>\n-\tadd\tsp, #108\t@ 0x6c\n-\tvpop\t{d8-d14}\n+\tbne.n\t24c6 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x2a6>\n+\tadd\tsp, #124\t@ 0x7c\n+\tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, r7, pc}\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tmovt\tr3, #16404\t@ 0x4014\n+\tmovs\tr0, #0\n \tstrd\tr2, r3, [r1]\n-\tmovs\tr2, #0\n \tmovs\tr3, #0\n-\tstrd\tr2, r3, [r6]\n-\tvst1.8\t{d16-d17}, [r4 :64]\n-\tvstr\td16, [r4, #16]\n-\tb.n\t24c2 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x252>\n+\tmovs\tr1, #0\n+\tstrd\tr3, r3, [r4]\n+\tstrd\tr3, r3, [r4, #8]\n+\tstrd\tr3, r3, [r4, #16]\n+\tstrd\tr0, r1, [r7]\n+\tb.n\t2486 <__gridxc_vdwxc_MOD_qofrho.isra.0+0x266>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n+\tnop\n \tnop.w\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x1c71c71c\n-\t.word\t0x3fbc71c7\n-\t.word\t0x55555555\n-\t.word\t0x3fd55555\n-\t.word\t0x11111111\n-\t.word\t0x3f911111\n \t.word\t0x745d1746\n \t.word\t0x3fb745d1\n \t.word\t0x9999999a\n-\t.word\t0x3fc99999\n-\t.word\t0x9999999a\n \t.word\t0x3fb99999\n+\t.word\t0x1c71c71c\n+\t.word\t0x3fbc71c7\n+\t.word\t0x11111111\n+\t.word\t0x3f911111\n \t.word\t0x92492492\n \t.word\t0x3fc24924\n+\t.word\t0x9999999a\n+\t.word\t0x3fc99999\n+\t.word\t0x55555555\n+\t.word\t0x3fd55555\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x1c71c71c\n \t.word\t0x3fcc71c7\n-\t.word\t0x000002c8\n+\t.word\t0x000002e0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000029a\n+\t.word\t0x000002b6\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000294\n+\t.word\t0x000002b0\n R_ARM_REL32\t.LC19\n-\t.word\t0x00000240\n+\t.word\t0x00000264\n R_ARM_REL32\t.data\n-\t.word\t0x000000aa\n+\t.word\t0x000000ae\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00002578 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>:\n+00002540 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>:\n __gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0():\n \tpush\t{r3, r4, r5, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n-\tvmov.f64\td16, #20\t@ 0x40a00000 5.0\n-\tmov\tr4, r1\n-\tmovs\tr1, #1\n-\tldr\tr2, [pc, #460]\t@ (2760 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1e8>)\n-\tvcmpe.f64\td0, d16\n-\tvmov.f64\td13, d0\n-\tadd\tr2, pc\n+\tvmov.f64\td7, #20\t@ 0x40a00000 5.0\n+\tldr\tr2, [pc, #456]\t@ (2720 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1e0>)\n+\tvmov.f64\td12, d0\n \tmov\tr5, r0\n+\tvcmpe.f64\td0, d7\n+\tadd\tr2, pc\n+\tmov\tr4, r1\n \tvmrs\tAPSR_nzcv, fpscr\n \tvcmpe.f64\td0, #0.0\n-\tit\tle\n-\tmovle\tr1, #0\n+\tite\tgt\n+\tmovgt\tr3, #1\n+\tmovle\tr3, #0\n \tvmrs\tAPSR_nzcv, fpscr\n-\torr.w\tr3, r1, #1\n-\tit\tpl\n-\tmovpl\tr3, r1\n-\tcbz\tr3, 25c8 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x50>\n-\tldr\tr3, [pc, #424]\t@ (2764 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1ec>)\n+\tit\tmi\n+\torrmi.w\tr3, r3, #1\n+\tcbz\tr3, 258e <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x4e>\n+\tldr\tr3, [pc, #416]\t@ (2724 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1e4>)\n \tmovs\tr1, #36\t@ 0x24\n-\tldr\tr0, [pc, #424]\t@ (2768 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1f0>)\n+\tldr\tr0, [pc, #416]\t@ (2728 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1e8>)\n \tadd\tr0, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvmov.f64\td8, #30\t@ 0x40f00000 7.5\n-\tvmov.i64\td9, #0x0000000000000000\n-\tvldr\td0, [pc, #308]\t@ 2708 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x190>\n-\tvmov.f64\td11, d8\n-\tvldr\td12, [pc, #308]\t@ 2710 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x198>\n-\tvldr\td10, [pc, #312]\t@ 2718 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1a0>\n-\tvldr\td14, [pc, #316]\t@ 2720 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1a8>\n-\tvldr\td15, [pc, #320]\t@ 2728 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1b0>\n-\tb.n\t2666 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0xee>\n-\tvmov.f64\td8, d18\n-\tvadd.f64\td11, d8, d9\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvldr\td16, [pc, #312]\t@ 2730 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1b8>\n-\tvmov.f64\td24, #64\t@ 0x3e000000 0.125\n-\tvldr\td26, [pc, #312]\t@ 2738 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1c0>\n-\tvmov.f64\td0, #112\t@ 0x3f800000 1.0\n-\tvldr\td27, [pc, #312]\t@ 2740 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1c8>\n-\tvmov.f64\td22, #80\t@ 0x3e800000 0.250\n-\tvmul.f64\td18, d11, d17\n-\tvldr\td20, [pc, #308]\t@ 2748 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1d0>\n-\tvldr\td19, [pc, #312]\t@ 2750 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1d8>\n-\tvfma.f64\td26, d18, d16\n-\tvmul.f64\td16, d18, d12\n-\tvmul.f64\td25, d18, d20\n-\tvfma.f64\td27, d16, d26\n-\tvmov.f64\td26, d14\n-\tvfma.f64\td26, d16, d27\n-\tvmov.f64\td27, d15\n-\tvfma.f64\td24, d16, d26\n-\tvldr\td26, [pc, #284]\t@ 2758 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1e0>\n-\tvfma.f64\td27, d16, d24\n-\tvmov.f64\td24, d0\n-\tvfma.f64\td26, d16, d27\n-\tvfma.f64\td24, d18, d26\n-\tvfma.f64\td22, d24, d25\n-\tvfma.f64\td19, d16, d22\n-\tvfma.f64\td17, d16, d19\n-\tvfma.f64\td0, d16, d17\n-\tvnmul.f64\td0, d0, d16\n+\tvmov.f64\td9, #30\t@ 0x40f00000 7.5\n+\tvldr\td4, [pc, #300]\t@ 26c0 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x180>\n+\tvldr\td11, [pc, #304]\t@ 26c8 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x188>\n+\tvmov.f64\td8, d9\n+\tvldr\td13, [pc, #304]\t@ 26d0 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x190>\n+\tvldr\td14, [pc, #308]\t@ 26d8 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x198>\n+\tvldr\td15, [pc, #312]\t@ 26e0 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1a0>\n+\tb.n\t2620 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0xe0>\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvldr\td3, [pc, #308]\t@ 26e8 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1a8>\n+\tvldr\td2, [pc, #312]\t@ 26f0 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1b0>\n+\tit\tle\n+\tvmovle.f64\td9, d8\n+\tit\tgt\n+\tvmovgt.f64\td11, d8\n+\tvadd.f64\td8, d9, d11\n+\tvmul.f64\td6, d8, d5\n+\tvmla.f64\td3, d6, d15\n+\tvmul.f64\td7, d6, d13\n+\tvmla.f64\td2, d3, d7\n+\tvldr\td3, [pc, #284]\t@ 26f8 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1b8>\n+\tvmla.f64\td3, d2, d7\n+\tvmla.f64\td4, d3, d7\n+\tvldr\td3, [pc, #280]\t@ 2700 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1c0>\n+\tvmla.f64\td3, d4, d7\n+\tvldr\td4, [pc, #280]\t@ 2708 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1c8>\n+\tvmla.f64\td4, d3, d7\n+\tvmov.f64\td3, d0\n+\tvmla.f64\td3, d4, d6\n+\tvldr\td4, [pc, #272]\t@ 2710 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1d0>\n+\tvmul.f64\td6, d6, d4\n+\tvmla.f64\td1, d3, d6\n+\tvmla.f64\td10, d1, d7\n+\tvmla.f64\td5, d10, d7\n+\tvmla.f64\td0, d5, d7\n+\tvnmul.f64\td0, d7, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td22, #20\t@ 0x40a00000 5.0\n-\tvmul.f64\td18, d11, d18\n-\tvmov.f64\td23, d16\n-\tvsub.f64\td19, d16, d0\n-\tvmul.f64\td17, d18, d12\n-\tvmul.f64\td19, d19, d22\n-\tvadd.f64\td24, d17, d16\n-\tvsub.f64\td22, d13, d19\n-\tvfma.f64\td23, d24, d17\n-\tvmov.f64\td24, d16\n-\tvabs.f64\td22, d22\n-\tvcmpe.f64\td22, d10\n-\tvfma.f64\td24, d17, d23\n-\tvmov.f64\td23, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvfma.f64\td23, d17, d24\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td24, d17, d23\n-\tvmov.f64\td23, d16\n-\tvfma.f64\td23, d17, d24\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td24, d17, d23\n-\tvmov.f64\td23, d16\n-\tvfma.f64\td23, d17, d24\n-\tvmov.f64\td24, d16\n-\tvfma.f64\td24, d17, d23\n-\tvmov.f64\td23, d16\n-\tvfma.f64\td23, d17, d24\n-\tvfma.f64\td16, d17, d23\n-\tvmul.f64\td16, d16, d0\n-\tvstr\td16, [r4]\n-\tbmi.n\t26fe <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x186>\n-\tvcmpe.f64\td13, d19\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t25ea <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x72>\n-\tvmov.f64\td9, d18\n-\tb.n\t25ee <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x76>\n+\tvmov.f64\td4, d0\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvmov.f64\td0, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td7, #20\t@ 0x40a00000 5.0\n+\tvldr\td10, [pc, #232]\t@ 2718 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x1d8>\n+\tvsub.f64\td6, d0, d4\n+\tvmul.f64\td8, d8, d5\n+\tvmov.f64\td1, #80\t@ 0x3e800000 0.250\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td7, d8, d13\n+\tvmov.f64\td3, d7\n+\tvmov.f64\td2, d7\n+\tvmla.f64\td3, d7, d7\n+\tvmla.f64\td2, d3, d7\n+\tvmov.f64\td3, d7\n+\tvmla.f64\td3, d2, d7\n+\tvmov.f64\td2, d7\n+\tvmla.f64\td2, d3, d7\n+\tvmov.f64\td3, d7\n+\tvmla.f64\td3, d2, d7\n+\tvmov.f64\td2, d7\n+\tvmla.f64\td2, d3, d7\n+\tvmov.f64\td3, d7\n+\tvmla.f64\td3, d2, d7\n+\tvmov.f64\td2, d7\n+\tvmla.f64\td2, d3, d7\n+\tvmov.f64\td3, d7\n+\tvmla.f64\td3, d2, d7\n+\tvmla.f64\td7, d3, d7\n+\tvmla.f64\td4, d7, d4\n+\tvsub.f64\td7, d12, d6\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d14\n+\tvstr\td4, [r4]\n+\tvmov.f64\td4, #64\t@ 0x3e000000 0.125\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td12, d6\n+\tbpl.w\t25ac <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0+0x6c>\n+\tvstr\td8, [r5]\n \tvpop\t{d8-d15}\n-\tvstr\td18, [r5]\n \tpop\t{r3, r4, r5, pc}\n+\tnop\n \t.word\t0x31c9b876\n \t.word\t0x3fd0194c\n+\t...\n \t.word\t0x9999999a\n \t.word\t0x3fc99999\n \t.word\t0x9ee75616\n \t.word\t0x3cd203af\n-\t.word\t0x1c71c71c\n-\t.word\t0x3fbc71c7\n-\t.word\t0x92492492\n-\t.word\t0x3fc24924\n \t.word\t0x11111111\n \t.word\t0x3f911111\n \t.word\t0x745d1746\n \t.word\t0x3fb745d1\n \t.word\t0x9999999a\n \t.word\t0x3fb99999\n+\t.word\t0x1c71c71c\n+\t.word\t0x3fbc71c7\n+\t.word\t0x92492492\n+\t.word\t0x3fc24924\n+\t.word\t0x55555555\n+\t.word\t0x3fc55555\n \t.word\t0x47ae147c\n \t.word\t0x3fa47ae1\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x55555555\n-\t.word\t0x3fc55555\n-\t.word\t0x000001c0\n+\t.word\t0x000001ba\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000001a4\n+\t.word\t0x0000019e\n R_ARM_REL32\t.LC20\n \n-0000276c <__gridxc_vdwxc_MOD_vdw_theta>:\n+0000272c <__gridxc_vdwxc_MOD_vdw_theta>:\n __gridxc_vdwxc_MOD_vdw_theta():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3384]\t@ 0xd38\n \tsub.w\tsp, sp, #668\t@ 0x29c\n+\tmov\tr8, r1\n+\tldr.w\tr1, [pc, #1336]\t@ 2c80 <__gridxc_vdwxc_MOD_vdw_theta+0x554>\n \tadd\tr7, sp, #8\n \tmov\tsl, r2\n-\tldr.w\tr2, [pc, #2168]\t@ 3004 <__gridxc_vdwxc_MOD_vdw_theta+0x898>\n+\tldr.w\tr2, [pc, #1332]\t@ 2c84 <__gridxc_vdwxc_MOD_vdw_theta+0x558>\n+\tadd\tr1, pc\n \tldr.w\tfp, [r3, #24]\n-\tstr\tr1, [r7, #36]\t@ 0x24\n-\tldr.w\tr1, [pc, #2164]\t@ 3008 <__gridxc_vdwxc_MOD_vdw_theta+0x89c>\n-\tcmp.w\tfp, #0\n \tstr\tr0, [r7, #8]\n-\tadd\tr1, pc\n \tldr.w\tr4, [r7, #704]\t@ 0x2c0\n-\tldr.w\tip, [r7, #708]\t@ 0x2c4\n+\tcmp.w\tfp, #0\n \tldr\tr2, [r1, r2]\n+\tit\teq\n+\tmoveq.w\tfp, #1\n \tldr\tr1, [r0, #0]\n \tldr\tr2, [r2, #0]\n \tstr.w\tr2, [r7, #652]\t@ 0x28c\n \tmov.w\tr2, #0\n-\tmov.w\tr2, #1\n-\tit\teq\n-\tmoveq\tfp, r2\n \tldr\tr2, [r4, #24]\n \tstr\tr1, [r7, #48]\t@ 0x30\n \tldr\tr1, [r3, #0]\n \tstr\tr1, [r7, #44]\t@ 0x2c\n \tldr\tr1, [r3, #32]\n \tldr\tr3, [r3, #28]\n+\tldr.w\tip, [r7, #708]\t@ 0x2c4\n \tstr\tr2, [r7, #92]\t@ 0x5c\n \tstr\tr1, [r7, #16]\n \tstr\tr3, [r7, #12]\n \tcmp\tr2, #0\n-\tbeq.w\t29e2 <__gridxc_vdwxc_MOD_vdw_theta+0x276>\n+\tbeq.w\t2992 <__gridxc_vdwxc_MOD_vdw_theta+0x266>\n \tnegs\tr3, r2\n-\tstr\tr3, [r7, #56]\t@ 0x38\n+\tstr\tr3, [r7, #52]\t@ 0x34\n \tldrd\tr3, r2, [r4, #28]\n-\tldr.w\tr8, [ip, #24]\n+\tldr.w\tr1, [ip, #24]\n \tsub.w\tr9, r2, r3\n+\tstr\tr1, [r7, #88]\t@ 0x58\n \tldrd\tr3, r2, [r4, #40]\t@ 0x28\n \tsubs\tr3, r2, r3\n \tldr\tr2, [r4, #0]\n-\tstr\tr2, [r7, #68]\t@ 0x44\n+\tstr\tr2, [r7, #64]\t@ 0x40\n \tldr\tr2, [r4, #36]\t@ 0x24\n-\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr3, [r7, #56]\t@ 0x38\n \tadds\tr3, #1\n-\tstr\tr2, [r7, #88]\t@ 0x58\n+\tstr\tr2, [r7, #84]\t@ 0x54\n \tadd.w\tr2, r9, #1\n \tstr\tr3, [r7, #28]\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tcmp.w\tr8, #0\n-\tbeq.w\t29ee <__gridxc_vdwxc_MOD_vdw_theta+0x282>\n-\trsb\tr3, r8, #0\n+\tstr\tr2, [r7, #68]\t@ 0x44\n+\tcmp\tr1, #0\n+\tbeq.w\t299e <__gridxc_vdwxc_MOD_vdw_theta+0x272>\n+\tnegs\tr3, r1\n \tstr\tr3, [r7, #40]\t@ 0x28\n \tldrd\tr3, r5, [ip, #28]\n \tmovs\tr0, #5\n-\tldr.w\tr1, [pc, #2040]\t@ 300c <__gridxc_vdwxc_MOD_vdw_theta+0x8a0>\n+\tldr.w\tr1, [pc, #1208]\t@ 2c88 <__gridxc_vdwxc_MOD_vdw_theta+0x55c>\n \tsubs\tr5, r5, r3\n \tldr.w\tr4, [ip, #36]\t@ 0x24\n \tldrd\tr3, r6, [ip, #40]\t@ 0x28\n \tadd\tr1, pc\n \tadds\tr1, #24\n \tsubs\tr6, r6, r3\n \tstr\tr6, [r7, #96]\t@ 0x60\n \tldrd\tr3, r2, [ip, #52]\t@ 0x34\n \tldr.w\tr6, [ip]\n-\tstr\tr6, [r7, #64]\t@ 0x40\n+\tstr\tr6, [r7, #60]\t@ 0x3c\n \tsubs\tr3, r2, r3\n \tldr.w\tr6, [ip, #48]\t@ 0x30\n \tmovs\tr2, #2\n \tstr\tr6, [r7, #100]\t@ 0x64\n \tadds\tr6, r5, #1\n-\tstr\tr6, [r7, #84]\t@ 0x54\n+\tstr\tr6, [r7, #80]\t@ 0x50\n \tldr\tr6, [r7, #96]\t@ 0x60\n-\tstr\tr3, [r7, #80]\t@ 0x50\n+\tstr\tr3, [r7, #76]\t@ 0x4c\n \tadds\tr6, #1\n-\tstr\tr6, [r7, #76]\t@ 0x4c\n-\tldr\tr6, [r7, #80]\t@ 0x50\n-\tldr.w\tr3, [pc, #1988]\t@ 3010 <__gridxc_vdwxc_MOD_vdw_theta+0x8a4>\n+\tstr\tr6, [r7, #72]\t@ 0x48\n+\tldr\tr6, [r7, #76]\t@ 0x4c\n+\tldr.w\tr3, [pc, #1156]\t@ 2c8c <__gridxc_vdwxc_MOD_vdw_theta+0x560>\n \tadds\tr6, #1\n \tstr\tr6, [r7, #24]\n \tldr\tr6, [r7, #40]\t@ 0x28\n \tadd\tr3, pc\n \tsubs\tr6, r6, r4\n \tstr\tr6, [r7, #32]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t2b06 <__gridxc_vdwxc_MOD_vdw_theta+0x39a>\n+\tbeq.w\t2aae <__gridxc_vdwxc_MOD_vdw_theta+0x382>\n \tldr\tr3, [r7, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tble.w\t29fa <__gridxc_vdwxc_MOD_vdw_theta+0x28e>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tvldr\td8, [r3]\n-\tldr\tr3, [r7, #48]\t@ 0x30\n+\tble.w\t29aa <__gridxc_vdwxc_MOD_vdw_theta+0x27e>\n+\tvldr\td8, [r8]\n \tcmp\tr3, #1\n-\tbeq.w\t2bea <__gridxc_vdwxc_MOD_vdw_theta+0x47e>\n-\tldr\tr3, [r7, #36]\t@ 0x24\n-\tvldr\td18, [sl, #24]\n-\tvldr\td21, [sl]\n-\tvldr\td17, [sl, #8]\n-\tvldr\td22, [r3, #8]\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tvldr\td20, [sl, #32]\n-\tvadd.f64\td18, d18, d21\n-\tvldr\td16, [sl, #16]\n-\tmov\tr0, r3\n-\tvldr\td19, [sl, #40]\t@ 0x28\n-\tvadd.f64\td8, d8, d22\n-\tvadd.f64\td17, d17, d20\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tvstr\td18, [r7, #144]\t@ 0x90\n-\tvadd.f64\td16, d16, d19\n-\tvstr\td17, [r7, #152]\t@ 0x98\n-\tvstr\td16, [r7, #160]\t@ 0xa0\n+\tbeq.w\t2b92 <__gridxc_vdwxc_MOD_vdw_theta+0x466>\n+\tvldr\td1, [r8, #8]\n+\tadd.w\tr8, r7, #144\t@ 0x90\n+\tvldr\td5, [sl, #24]\n+\tvldr\td2, [sl]\n+\tvldr\td6, [sl, #8]\n+\tvadd.f64\td8, d8, d1\n+\tvldr\td3, [sl, #32]\n+\tvldr\td7, [sl, #16]\n+\tvadd.f64\td5, d5, d2\n+\tvldr\td4, [sl, #40]\t@ 0x28\n+\tvadd.f64\td6, d6, d3\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td5, [r8]\n+\tvstr\td6, [r8, #8]\n+\tvstr\td7, [r8, #16]\n \tadd.w\tr2, r7, #112\t@ 0x70\n \tadd.w\tr3, r7, #120\t@ 0x78\n \tmov\tr6, r2\n \tvmov.f64\td0, d8\n \tmov\tr1, r6\n+\tmov\tr0, r8\n \tstr\tr2, [r7, #16]\n \tadd.w\tr2, r7, #104\t@ 0x68\n \tstr\tr3, [r7, #20]\n-\tbl\t2270 <__gridxc_vdwxc_MOD_qofrho.isra.0>\n+\tbl\t2220 <__gridxc_vdwxc_MOD_qofrho.isra.0>\n \tadd.w\tr3, r7, #408\t@ 0x198\n \tadd.w\tr2, r7, #168\t@ 0xa8\n \tmov\tr1, r3\n \tmov\tr0, r6\n \tstr\tr2, [r7, #12]\n \tstr\tr3, [r7, #36]\t@ 0x24\n-\tbl\t8d0 <__gridxc_vdwxc_MOD_pofq>\n+\tbl\t940 <__gridxc_vdwxc_MOD_pofq>\n \tldr\tr2, [r7, #12]\n \tcmp.w\tfp, #1\n-\tbne.w\t2c56 <__gridxc_vdwxc_MOD_vdw_theta+0x4ea>\n+\tbne.w\t2bfa <__gridxc_vdwxc_MOD_vdw_theta+0x4ce>\n \tldr\tr0, [r7, #44]\t@ 0x2c\n \tadd.w\tr1, r7, #648\t@ 0x288\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tldr\tr6, [r7, #96]\t@ 0x60\n-\tvldmia\tr3!, {d16}\n-\tvmul.f64\td16, d16, d8\n+\tvldmia\tr3!, {d7}\n+\tvmul.f64\td7, d7, d8\n \tcmp\tr3, r1\n-\tvstmia\tr0!, {d16}\n-\tbne.n\t2900 <__gridxc_vdwxc_MOD_vdw_theta+0x194>\n+\tvstmia\tr0!, {d7}\n+\tbne.n\t28b4 <__gridxc_vdwxc_MOD_vdw_theta+0x188>\n \tldr\tr3, [r7, #28]\n \tstr\tr6, [r7, #96]\t@ 0x60\n \tcmp\tr3, #0\n-\tble.n\t296c <__gridxc_vdwxc_MOD_vdw_theta+0x200>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tble.n\t291c <__gridxc_vdwxc_MOD_vdw_theta+0x1f0>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tble.n\t296c <__gridxc_vdwxc_MOD_vdw_theta+0x200>\n+\tble.n\t291c <__gridxc_vdwxc_MOD_vdw_theta+0x1f0>\n \tldr\tr3, [r7, #92]\t@ 0x5c\n \tcmp\tr3, #1\n-\tbne.w\t2c16 <__gridxc_vdwxc_MOD_vdw_theta+0x4aa>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tbne.w\t2bba <__gridxc_vdwxc_MOD_vdw_theta+0x48e>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tmov.w\tfp, #0\n-\tldr\tr0, [r7, #68]\t@ 0x44\n-\tmov\tr6, r1\n-\tstr\tr5, [r7, #72]\t@ 0x48\n+\tldr\tr0, [r7, #64]\t@ 0x40\n+\tmov\tr6, r2\n+\tstr\tr4, [r7, #44]\t@ 0x2c\n \tmov.w\tsl, r3, lsl #3\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tldr\tr5, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr4, [r7, #56]\t@ 0x38\n \tadds\tr3, #1\n-\tstr.w\tr8, [r7, #60]\t@ 0x3c\n-\tmov\tr8, r2\n+\tstr\tr5, [r7, #68]\t@ 0x44\n+\tmov\tr5, r1\n \tadd.w\tr3, r0, r3, lsl #3\n-\tldr\tr0, [r7, #88]\t@ 0x58\n+\tldr\tr0, [r7, #84]\t@ 0x54\n \tmov.w\tr9, r0, lsl #3\n \tmov\tr0, r3\n \tmov\tr2, sl\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr3, r0\n-\tcmp\tfp, r5\n+\tcmp\tfp, r4\n \tadd\tr3, r9\n \tadd.w\tfp, fp, #1\n-\tbne.n\t294c <__gridxc_vdwxc_MOD_vdw_theta+0x1e0>\n-\tmov\tr2, r8\n-\tldr\tr5, [r7, #72]\t@ 0x48\n-\tldr.w\tr8, [r7, #60]\t@ 0x3c\n-\tmov\tr1, r6\n+\tbne.n\t28fe <__gridxc_vdwxc_MOD_vdw_theta+0x1d2>\n+\tmov\tr1, r5\n+\tldr\tr4, [r7, #44]\t@ 0x2c\n+\tldr\tr5, [r7, #68]\t@ 0x44\n+\tmov\tr2, r6\n \tldr\tr3, [r7, #24]\n \tcmp\tr3, #0\n-\tble.n\t2a1e <__gridxc_vdwxc_MOD_vdw_theta+0x2b2>\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tble.n\t29ca <__gridxc_vdwxc_MOD_vdw_theta+0x29e>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr3, #0\n-\tble.n\t2a1e <__gridxc_vdwxc_MOD_vdw_theta+0x2b2>\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tble.n\t29ca <__gridxc_vdwxc_MOD_vdw_theta+0x29e>\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tcmp\tr3, #0\n-\tble.n\t2a1e <__gridxc_vdwxc_MOD_vdw_theta+0x2b2>\n-\tcmp.w\tr8, #1\n-\tbne.w\t2eae <__gridxc_vdwxc_MOD_vdw_theta+0x742>\n-\tmov.w\tr9, r3, lsl #3\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tble.n\t29ca <__gridxc_vdwxc_MOD_vdw_theta+0x29e>\n+\tldr\tr3, [r7, #88]\t@ 0x58\n+\tcmp\tr3, #1\n+\tbne.w\t2e8e <__gridxc_vdwxc_MOD_vdw_theta+0x762>\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tmov.w\tfp, r4, lsl #3\n \tldr\tr0, [r7, #32]\n-\tadd.w\tsl, r3, fp\n \tldr\tr6, [r7, #96]\t@ 0x60\n+\tmov.w\tr9, r3, lsl #3\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr\tr4, [r7, #96]\t@ 0x60\n+\tadd.w\tsl, r3, fp\n+\tstr\tr2, [r7, #68]\t@ 0x44\n \tadd.w\tr3, sl, #8\n-\tstr.w\tr8, [r7, #96]\t@ 0x60\n \tmov.w\tsl, #0\n+\tmov\tr5, sl\n+\tldr.w\tsl, [r7, #76]\t@ 0x4c\n+\tstrd\tr8, r1, [r7, #72]\t@ 0x48\n \tmov\tr8, r0\n-\tstr\tr4, [r7, #76]\t@ 0x4c\n-\tmov\tr4, sl\n-\tstr\tr3, [r7, #84]\t@ 0x54\n-\tldr.w\tsl, [r7, #80]\t@ 0x50\n-\tstr\tr2, [r7, #72]\t@ 0x48\n-\tstr\tr1, [r7, #80]\t@ 0x50\n-\tldr\tr3, [r7, #84]\t@ 0x54\n-\tmovs\tr5, #0\n+\tstr\tr3, [r7, #80]\t@ 0x50\n+\tldr\tr3, [r7, #80]\t@ 0x50\n+\tmovs\tr4, #0\n \tadd.w\tr3, r3, r8, lsl #3\n \tmov\tr0, r3\n \tmov\tr2, r9\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr3, r0\n-\tcmp\tr5, r6\n+\tcmp\tr4, r6\n \tadd\tr3, fp\n-\tadd.w\tr5, r5, #1\n-\tbne.n\t29bc <__gridxc_vdwxc_MOD_vdw_theta+0x250>\n+\tadd.w\tr4, r4, #1\n+\tbne.n\t296c <__gridxc_vdwxc_MOD_vdw_theta+0x240>\n \tldr\tr3, [r7, #100]\t@ 0x64\n-\tcmp\tr4, sl\n+\tcmp\tr5, sl\n \tadd\tr8, r3\n-\tadd.w\tr3, r4, #1\n-\tbeq.n\t2a14 <__gridxc_vdwxc_MOD_vdw_theta+0x2a8>\n-\tmov\tr4, r3\n-\tb.n\t29b4 <__gridxc_vdwxc_MOD_vdw_theta+0x248>\n+\tadd.w\tr3, r5, #1\n+\tbeq.n\t29c2 <__gridxc_vdwxc_MOD_vdw_theta+0x296>\n+\tmov\tr5, r3\n+\tb.n\t2964 <__gridxc_vdwxc_MOD_vdw_theta+0x238>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [r7, #56]\t@ 0x38\n+\tstr\tr3, [r7, #52]\t@ 0x34\n \tmovs\tr3, #1\n \tstr\tr3, [r7, #92]\t@ 0x5c\n-\tb.n\t27d8 <__gridxc_vdwxc_MOD_vdw_theta+0x6c>\n+\tb.n\t2796 <__gridxc_vdwxc_MOD_vdw_theta+0x6a>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tmov.w\tr8, #1\n \tstr\tr3, [r7, #40]\t@ 0x28\n-\tb.n\t280c <__gridxc_vdwxc_MOD_vdw_theta+0xa0>\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n-\tadd.w\tr3, r7, #144\t@ 0x90\n-\tvmov.i64\td8, #0x0000000000000000\n-\tmov\tr0, r3\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tvstr\td16, [r7, #160]\t@ 0xa0\n-\tvst1.8\t{d16-d17}, [r3 :64]\n-\tb.n\t28bc <__gridxc_vdwxc_MOD_vdw_theta+0x150>\n-\tldr.w\tr8, [r7, #96]\t@ 0x60\n-\tldrd\tr4, r1, [r7, #76]\t@ 0x4c\n-\tldr\tr2, [r7, #72]\t@ 0x48\n+\tmovs\tr3, #1\n+\tstr\tr3, [r7, #88]\t@ 0x58\n+\tb.n\t27c8 <__gridxc_vdwxc_MOD_vdw_theta+0x9c>\n+\tadd.w\tr8, r7, #144\t@ 0x90\n+\tmovs\tr3, #0\n+\tvldr\td8, [pc, #708]\t@ 2c78 <__gridxc_vdwxc_MOD_vdw_theta+0x54c>\n+\tstrd\tr3, r3, [r8]\n+\tstrd\tr3, r3, [r8, #8]\n+\tstrd\tr3, r3, [r8, #16]\n+\tb.n\t286e <__gridxc_vdwxc_MOD_vdw_theta+0x142>\n+\tldr\tr4, [r7, #96]\t@ 0x60\n+\tldrd\tr8, r1, [r7, #72]\t@ 0x48\n+\tldr\tr2, [r7, #68]\t@ 0x44\n \tldr\tr3, [r7, #48]\t@ 0x30\n \tcmp\tr3, #0\n-\tble.n\t2adc <__gridxc_vdwxc_MOD_vdw_theta+0x370>\n+\tble.n\t2a88 <__gridxc_vdwxc_MOD_vdw_theta+0x35c>\n \tldr\tr3, [r7, #16]\n \tldr\tr0, [r7, #100]\t@ 0x64\n-\tvldr\td18, [r3, #-8]\n+\tvldr\td5, [r3, #-8]\n \tldr\tr3, [r7, #32]\n \tsubs\tr3, r3, r0\n \tldr\tr0, [r7, #48]\t@ 0x30\n-\tvmul.f64\td18, d8, d18\n-\tadd\tr3, r8\n+\tvmul.f64\td5, d8, d5\n \tcmp\tr0, #2\n \tit\tge\n \tmovge\tr0, #2\n \tmov\tfp, r0\n \tldr\tr0, [r7, #92]\t@ 0x5c\n \tcmp\tr0, #1\n-\tbne.w\t2e10 <__gridxc_vdwxc_MOD_vdw_theta+0x6a4>\n-\tldr\tr0, [r7, #100]\t@ 0x64\n+\tldr\tr0, [r7, #88]\t@ 0x58\n+\tadd\tr3, r0\n+\tbne.w\t2de8 <__gridxc_vdwxc_MOD_vdw_theta+0x6bc>\n+\tldr\tr5, [r7, #100]\t@ 0x64\n \tlsls\tr4, r4, #3\n-\tstr.w\tfp, [r7, #84]\t@ 0x54\n+\tldr.w\tsl, [r7, #52]\t@ 0x34\n+\tadd.w\tr9, r3, r5\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n+\tstr.w\tfp, [r7, #88]\t@ 0x58\n \tadd.w\tr5, r2, #240\t@ 0xf0\n-\tadd.w\tr9, r3, r0\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tldr.w\tsl, [r7, #56]\t@ 0x38\n \tadd\tr3, r4\n-\tldr.w\tfp, [r7, #52]\t@ 0x34\n+\tmov\tfp, r0\n \tmov\tlr, r3\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldr\tr3, [r7, #64]\t@ 0x40\n \tadds\tr3, #8\n \tstr\tr3, [r7, #96]\t@ 0x60\n \tldr\tr0, [r7, #96]\t@ 0x60\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tadd.w\tr6, r0, sl, lsl #3\n \tmov\tr0, r2\n-\tvldmia\tr0!, {d17}\n-\tvldmia\tr3!, {d16}\n-\tvfma.f64\td16, d18, d17\n+\tvldmia\tr0!, {d6}\n+\tvldmia\tr3!, {d7}\n+\tvmla.f64\td7, d5, d6\n \tcmp\tr3, r1\n-\tvstmia\tr6!, {d16}\n-\tbne.n\t2a76 <__gridxc_vdwxc_MOD_vdw_theta+0x30a>\n+\tvstmia\tr6!, {d7}\n+\tbne.n\t2a22 <__gridxc_vdwxc_MOD_vdw_theta+0x2f6>\n \tldr.w\tip, [r7, #20]\n \tmov\tr6, r9\n-\tvldmia\tip!, {d17}\n+\tvldmia\tip!, {d6}\n \tadd.w\tr0, lr, r6, lsl #3\n \tmov\tr3, r2\n-\tvmul.f64\td17, d17, d8\n-\tvldmia\tr3!, {d16}\n-\tvmul.f64\td16, d16, d17\n+\tvmul.f64\td6, d6, d8\n+\tvldmia\tr3!, {d7}\n+\tvmul.f64\td7, d7, d6\n \tcmp\tr3, r5\n-\tvstr\td16, [r0]\n+\tvstr\td7, [r0]\n \tadd\tr0, r4\n-\tbne.n\t2a9e <__gridxc_vdwxc_MOD_vdw_theta+0x332>\n-\tadd\tr6, r8\n-\tcmp\tip, fp\n-\tbne.n\t2a90 <__gridxc_vdwxc_MOD_vdw_theta+0x324>\n+\tbne.n\t2a4a <__gridxc_vdwxc_MOD_vdw_theta+0x31e>\n+\tadd\tr6, fp\n+\tcmp\tip, r8\n+\tbne.n\t2a3c <__gridxc_vdwxc_MOD_vdw_theta+0x310>\n \tldr\tr3, [r7, #92]\t@ 0x5c\n-\tldr\tr0, [r7, #84]\t@ 0x54\n+\tmovs\tr0, #2\n+\tstr\tr0, [r7, #92]\t@ 0x5c\n \tsub.w\tr3, r3, #1\n+\tldr\tr0, [r7, #88]\t@ 0x58\n \tclz\tr3, r3\n \tlsrs\tr3, r3, #5\n \tcmp\tr3, #0\n \tldr\tr3, [r7, #100]\t@ 0x64\n \tadd\tr9, r3\n-\tldr\tr3, [r7, #88]\t@ 0x58\n+\tldr\tr3, [r7, #84]\t@ 0x54\n \tadd\tsl, r3\n-\tmov.w\tr3, #2\n-\tstr\tr3, [r7, #92]\t@ 0x5c\n-\tit\teq\n+\tite\tne\n+\tmovne\tr3, #2\n \tmoveq\tr3, #3\n \tcmp\tr0, r3\n-\tbge.n\t2a6c <__gridxc_vdwxc_MOD_vdw_theta+0x300>\n-\tldr.w\tr2, [pc, #1332]\t@ 3014 <__gridxc_vdwxc_MOD_vdw_theta+0x8a8>\n-\tldr.w\tr3, [pc, #1312]\t@ 3004 <__gridxc_vdwxc_MOD_vdw_theta+0x898>\n+\tbge.n\t2a18 <__gridxc_vdwxc_MOD_vdw_theta+0x2ec>\n+\tldr\tr2, [pc, #516]\t@ (2c90 <__gridxc_vdwxc_MOD_vdw_theta+0x564>)\n+\tldr\tr3, [pc, #504]\t@ (2c84 <__gridxc_vdwxc_MOD_vdw_theta+0x558>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr.w\tr3, [r7, #652]\t@ 0x28c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t3000 <__gridxc_vdwxc_MOD_vdw_theta+0x894>\n+\tbne.w\t2fc6 <__gridxc_vdwxc_MOD_vdw_theta+0x89a>\n \tadd.w\tr7, r7, #660\t@ 0x294\n \tmov\tsp, r7\n \tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tldrd\tr2, r3, [r7, #12]\n \tcmp.w\tfp, #1\n \tstr.w\tsp, [r7, #12]\n \tsub.w\tr3, r3, r2\n \tadd.w\tr2, r3, #1\n+\tit\teq\n+\tldreq\tr3, [r7, #44]\t@ 0x2c\n \tstr\tr2, [r7, #16]\n-\tbne.w\t2dc8 <__gridxc_vdwxc_MOD_vdw_theta+0x65c>\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tbne.w\t2da2 <__gridxc_vdwxc_MOD_vdw_theta+0x676>\n \tldr\tr1, [r7, #92]\t@ 0x5c\n-\tldr\tr2, [r7, #72]\t@ 0x48\n-\tldr\tr0, [r7, #88]\t@ 0x58\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tldr\tr0, [r7, #84]\t@ 0x54\n \tmul.w\tr2, r2, r1\n \tcmp\tr2, r0\n \tit\teq\n \tcmpeq\tr1, #1\n-\tit\teq\n+\tite\teq\n \tmoveq\tr2, #1\n-\tit\tne\n \tmovne\tr2, #0\n \tstr\tr2, [r7, #48]\t@ 0x30\n-\tbne.w\t2cc4 <__gridxc_vdwxc_MOD_vdw_theta+0x558>\n-\tldr\tr1, [r7, #68]\t@ 0x44\n-\tldr\tr2, [r7, #76]\t@ 0x4c\n-\tmov\tr6, r8\n-\tldr\tr0, [r7, #100]\t@ 0x64\n-\tmul.w\tr2, r2, r4\n-\tcmp\tr2, r0\n \tit\teq\n-\tcmpeq\tr6, #1\n-\tldr\tr0, [r7, #84]\t@ 0x54\n+\tldreq\tr1, [r7, #64]\t@ 0x40\n+\tbne.w\t2c94 <__gridxc_vdwxc_MOD_vdw_theta+0x568>\n+\tldr\tr2, [r7, #72]\t@ 0x48\n+\tldr\tr6, [r7, #100]\t@ 0x64\n+\tldr\tr0, [r7, #88]\t@ 0x58\n+\tmul.w\tr2, r2, r4\n+\tcmp\tr2, r6\n \tit\teq\n+\tcmpeq\tr0, #1\n+\tldr\tr6, [r7, #80]\t@ 0x50\n+\tite\teq\n \tmoveq\tr2, #1\n-\tit\tne\n \tmovne\tr2, #0\n-\tand.w\tr2, r2, #1\n-\tmul.w\tr0, r0, r8\n+\tmul.w\tr0, r6, r0\n \tcmp\tr0, r4\n-\tit\tne\n-\tmovne\tr2, #0\n-\tmov\tr9, r2\n-\tldr\tr2, [r7, #64]\t@ 0x40\n+\tite\tne\n+\tmovne.w\tr9, #0\n+\tandeq.w\tr9, r2, #1\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n \tcmp.w\tr9, #0\n-\tbeq.w\t2c7e <__gridxc_vdwxc_MOD_vdw_theta+0x512>\n+\tbeq.w\t2c22 <__gridxc_vdwxc_MOD_vdw_theta+0x4f6>\n \tstrd\tr1, r2, [sp]\n \tmov\tr2, sl\n-\tldr\tr1, [r7, #36]\t@ 0x24\n+\tmov\tr1, r8\n \tldr\tr0, [r7, #8]\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta>\n R_ARM_THM_CALL\t__gridxc_vv_vdwxc_MOD_vv_vdw_theta\n \tcmp.w\tfp, #1\n-\tbne.w\t2d0a <__gridxc_vdwxc_MOD_vdw_theta+0x59e>\n+\tbne.w\t2ce2 <__gridxc_vdwxc_MOD_vdw_theta+0x5b6>\n \tldr\tr3, [r7, #48]\t@ 0x30\n-\tcbz\tr3, 2b9e <__gridxc_vdwxc_MOD_vdw_theta+0x432>\n+\tcbz\tr3, 2b46 <__gridxc_vdwxc_MOD_vdw_theta+0x41a>\n \tcmp.w\tr9, #0\n-\tbeq.w\t2d2e <__gridxc_vdwxc_MOD_vdw_theta+0x5c2>\n+\tbeq.w\t2d0a <__gridxc_vdwxc_MOD_vdw_theta+0x5de>\n \tldr.w\tsp, [r7, #12]\n-\tb.n\t2adc <__gridxc_vdwxc_MOD_vdw_theta+0x370>\n+\tb.n\t2a88 <__gridxc_vdwxc_MOD_vdw_theta+0x35c>\n \tldr\tr3, [r7, #28]\n \tcmp\tr3, #0\n-\tble.n\t2b90 <__gridxc_vdwxc_MOD_vdw_theta+0x424>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tble.n\t2b38 <__gridxc_vdwxc_MOD_vdw_theta+0x40c>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tcmp\tr3, #0\n-\tble.n\t2b90 <__gridxc_vdwxc_MOD_vdw_theta+0x424>\n+\tble.n\t2b38 <__gridxc_vdwxc_MOD_vdw_theta+0x40c>\n \tldr\tr3, [r7, #92]\t@ 0x5c\n \tcmp\tr3, #1\n-\tbne.w\t2fb0 <__gridxc_vdwxc_MOD_vdw_theta+0x844>\n-\tldr\tr3, [r7, #56]\t@ 0x38\n-\tldr\tr2, [r7, #68]\t@ 0x44\n+\tbne.w\t2f78 <__gridxc_vdwxc_MOD_vdw_theta+0x84c>\n+\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr2, [r7, #64]\t@ 0x40\n \tadds\tr3, #1\n \tldr.w\tfp, [r7, #20]\n \tldr\tr6, [r7, #48]\t@ 0x30\n \tadd.w\tr3, r2, r3, lsl #3\n-\tldr\tr2, [r7, #88]\t@ 0x58\n+\tldr\tr2, [r7, #84]\t@ 0x54\n \tmov.w\tsl, r2, lsl #3\n-\tldr\tr2, [r7, #72]\t@ 0x48\n-\tlsls\tr2, r2, #3\n+\tldr\tr2, [r7, #68]\t@ 0x44\n+\tmov.w\tr8, r2, lsl #3\n+\tmov\tr2, r8\n \tmov\tr1, fp\n \tmov\tr0, r3\n-\tstr\tr2, [r7, #96]\t@ 0x60\n+\tadd\tfp, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr2, [r7, #96]\t@ 0x60\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tmov\tr3, r0\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tcmp\tr6, r2\n \tadd\tr3, sl\n-\tadd\tfp, r2\n-\tcmp\tr6, r0\n \tadd.w\tr6, r6, #1\n-\tbne.n\t2bcc <__gridxc_vdwxc_MOD_vdw_theta+0x460>\n-\tb.n\t2b90 <__gridxc_vdwxc_MOD_vdw_theta+0x424>\n-\tadd.w\tr3, r7, #144\t@ 0x90\n+\tbne.n\t2b76 <__gridxc_vdwxc_MOD_vdw_theta+0x44a>\n+\tb.n\t2b38 <__gridxc_vdwxc_MOD_vdw_theta+0x40c>\n+\tadd.w\tr8, r7, #144\t@ 0x90\n \tldr.w\tr0, [sl]\n-\tmov\tip, r3\n+\tmov\tip, r8\n \tldr.w\tr1, [sl, #4]\n-\tstr\tr3, [r7, #52]\t@ 0x34\n \tldr.w\tr2, [sl, #8]\n \tldr.w\tr3, [sl, #12]\n \tstmia.w\tip!, {r0, r1, r2, r3}\n \tldr.w\tr0, [sl, #16]\n \tldr.w\tr1, [sl, #20]\n \tstmia.w\tip!, {r0, r1}\n-\tldr\tr0, [r7, #52]\t@ 0x34\n-\tb.n\t28bc <__gridxc_vdwxc_MOD_vdw_theta+0x150>\n+\tb.n\t286e <__gridxc_vdwxc_MOD_vdw_theta+0x142>\n \tmov.w\tip, r3, lsl #3\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tldr.w\tsl, [r7, #56]\t@ 0x38\n-\tvmov.i64\td16, #0x0000000000000000\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldr.w\tsl, [r7, #52]\t@ 0x34\n+\tmov.w\tlr, #0\n \tldr\tr6, [r7, #96]\t@ 0x60\n \tadd.w\tfp, r3, ip\n-\tmov.w\tlr, #0\n-\tstr\tr5, [r7, #72]\t@ 0x48\n+\tvldr\td7, [pc, #168]\t@ 2c78 <__gridxc_vdwxc_MOD_vdw_theta+0x54c>\n+\tstr\tr5, [r7, #68]\t@ 0x44\n \tadd.w\tr5, fp, sl, lsl #3\n \tmovs\tr0, #0\n \tcmp\tr0, r9\n-\tvstr\td16, [r5]\n+\tvstr\td7, [r5]\n \tadd.w\tr0, r0, #1\n \tadd\tr5, ip\n-\tbne.n\t2c36 <__gridxc_vdwxc_MOD_vdw_theta+0x4ca>\n-\tldr\tr3, [r7, #88]\t@ 0x58\n-\tldr\tr0, [r7, #60]\t@ 0x3c\n+\tbne.n\t2bda <__gridxc_vdwxc_MOD_vdw_theta+0x4ae>\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr0, [r7, #56]\t@ 0x38\n \tadd\tsl, r3\n \tadd.w\tr3, lr, #1\n \tcmp\tlr, r0\n-\tbeq.n\t2c78 <__gridxc_vdwxc_MOD_vdw_theta+0x50c>\n+\tbeq.n\t2c1c <__gridxc_vdwxc_MOD_vdw_theta+0x4f0>\n \tmov\tlr, r3\n-\tb.n\t2c30 <__gridxc_vdwxc_MOD_vdw_theta+0x4c4>\n+\tb.n\t2bd4 <__gridxc_vdwxc_MOD_vdw_theta+0x4a8>\n \tldr\tr3, [r7, #44]\t@ 0x2c\n \tmov.w\tfp, fp, lsl #3\n \tldr\tr0, [r7, #36]\t@ 0x24\n \tadd.w\tr1, r7, #648\t@ 0x288\n \tldr\tr6, [r7, #96]\t@ 0x60\n-\tvldmia\tr0!, {d16}\n-\tvmul.f64\td16, d16, d8\n+\tvldmia\tr0!, {d7}\n+\tvmul.f64\td7, d7, d8\n \tcmp\tr0, r1\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tadd\tr3, fp\n-\tbne.n\t2c64 <__gridxc_vdwxc_MOD_vdw_theta+0x4f8>\n-\tb.n\t2910 <__gridxc_vdwxc_MOD_vdw_theta+0x1a4>\n-\tldr\tr5, [r7, #72]\t@ 0x48\n+\tbne.n\t2c08 <__gridxc_vdwxc_MOD_vdw_theta+0x4dc>\n+\tb.n\t28c4 <__gridxc_vdwxc_MOD_vdw_theta+0x198>\n+\tldr\tr5, [r7, #68]\t@ 0x44\n \tstr\tr6, [r7, #96]\t@ 0x60\n-\tb.n\t296c <__gridxc_vdwxc_MOD_vdw_theta+0x200>\n+\tb.n\t291c <__gridxc_vdwxc_MOD_vdw_theta+0x1f0>\n \tldr\tr6, [r7, #96]\t@ 0x60\n-\tldr\tr2, [r7, #80]\t@ 0x50\n+\tldr\tr2, [r7, #76]\t@ 0x4c\n \torrs\tr6, r5\n \torrs\tr6, r2\n-\tit\tmi\n+\tmov\tr6, sp\n+\titeee\tmi\n \tmovmi\tr2, r9\n-\tbpl.w\t2f22 <__gridxc_vdwxc_MOD_vdw_theta+0x7b6>\n+\tldrpl\tr2, [r7, #80]\t@ 0x50\n+\tldrpl\tr0, [r7, #72]\t@ 0x48\n+\tmulpl\tr2, r0\n+\tittt\tpl\n+\tldrpl\tr0, [r7, #24]\n+\tmulpl\tr2, r0\n+\tlslpl\tr2, r2, #3\n \tbic.w\tr0, r2, #4080\t@ 0xff0\n-\tmov\tr6, sp\n \tbic.w\tr0, r0, #15\n \tsub.w\tr0, sp, r0\n \tcmp\tr6, r0\n-\tbeq.n\t2cae <__gridxc_vdwxc_MOD_vdw_theta+0x542>\n+\tbeq.n\t2c5c <__gridxc_vdwxc_MOD_vdw_theta+0x530>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr6, sp\n \tcmp\tr6, r0\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2ca0 <__gridxc_vdwxc_MOD_vdw_theta+0x534>\n+\tbne.n\t2c4e <__gridxc_vdwxc_MOD_vdw_theta+0x522>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 2cbe <__gridxc_vdwxc_MOD_vdw_theta+0x552>\n+\tcbz\tr2, 2c6c <__gridxc_vdwxc_MOD_vdw_theta+0x540>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tadd\tr2, sp, #8\n-\tstr\tr2, [r7, #52]\t@ 0x34\n-\tb.n\t2b76 <__gridxc_vdwxc_MOD_vdw_theta+0x40a>\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tstr\tr2, [r7, #36]\t@ 0x24\n+\tb.n\t2b1e <__gridxc_vdwxc_MOD_vdw_theta+0x3f2>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x0000052a\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000004a8\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000478\n+ R_ARM_REL32\t.LC21\n+\t.word\t0x00000200\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\tldr\tr2, [r7, #56]\t@ 0x38\n+\tmov\tr0, sp\n+\tldr\tr6, [r7, #96]\t@ 0x60\n \torrs.w\tr9, r9, r2\n-\tbpl.w\t2f16 <__gridxc_vdwxc_MOD_vdw_theta+0x7aa>\n-\tldr\tr2, [r7, #48]\t@ 0x30\n+\tittet\tpl\n+\tldrpl\tr2, [r7, #68]\t@ 0x44\n+\tldrpl\tr1, [r7, #28]\n+\tldrmi\tr2, [r7, #48]\t@ 0x30\n+\tmulpl\tr2, r1\n+\tit\tpl\n+\tlslpl\tr2, r2, #3\n \tbic.w\tr1, r2, #4080\t@ 0xff0\n-\tmov\tr0, sp\n \tbic.w\tr1, r1, #15\n-\tldr\tr6, [r7, #96]\t@ 0x60\n \tsub.w\tr1, sp, r1\n \tcmp\tr0, r1\n-\tbeq.n\t2cf2 <__gridxc_vdwxc_MOD_vdw_theta+0x586>\n+\tbeq.n\t2cca <__gridxc_vdwxc_MOD_vdw_theta+0x59e>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r1\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2ce4 <__gridxc_vdwxc_MOD_vdw_theta+0x578>\n+\tbne.n\t2cbc <__gridxc_vdwxc_MOD_vdw_theta+0x590>\n \tstr\tr6, [r7, #96]\t@ 0x60\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 2d04 <__gridxc_vdwxc_MOD_vdw_theta+0x598>\n+\tcbz\tr2, 2cdc <__gridxc_vdwxc_MOD_vdw_theta+0x5b0>\n \tsubs\tr2, #4\n \tadd\tr2, sp\n \tstr\tr0, [r2, #0]\n \tadd\tr1, sp, #8\n \tstr\tr1, [r7, #20]\n-\tb.n\t2b42 <__gridxc_vdwxc_MOD_vdw_theta+0x3d6>\n+\tb.n\t2aec <__gridxc_vdwxc_MOD_vdw_theta+0x3c0>\n \tldr\tr2, [r7, #16]\n \tcmp\tr2, #0\n-\tble.w\t2b8c <__gridxc_vdwxc_MOD_vdw_theta+0x420>\n+\tble.w\t2b34 <__gridxc_vdwxc_MOD_vdw_theta+0x408>\n \tldr\tr3, [r7, #4]\n \tmov.w\tr0, fp, lsl #3\n \tldr\tr1, [r7, #44]\t@ 0x2c\n+\tmov\tr6, r9\n \tadd.w\tr2, r3, r2, lsl #3\n-\tldrd\tsl, fp, [r3], #8\n-\tstrd\tsl, fp, [r1]\n+\tldrd\tr8, r9, [r3], #8\n+\tstrd\tr8, r9, [r1]\n \tadd\tr1, r0\n \tcmp\tr3, r2\n-\tbne.n\t2d1e <__gridxc_vdwxc_MOD_vdw_theta+0x5b2>\n-\tb.n\t2b8c <__gridxc_vdwxc_MOD_vdw_theta+0x420>\n+\tbne.n\t2cf8 <__gridxc_vdwxc_MOD_vdw_theta+0x5cc>\n+\tmov\tr9, r6\n+\tb.n\t2b34 <__gridxc_vdwxc_MOD_vdw_theta+0x408>\n \tldr\tr3, [r7, #24]\n \tcmp\tr3, #0\n-\tble.w\t2b98 <__gridxc_vdwxc_MOD_vdw_theta+0x42c>\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tble.w\t2b40 <__gridxc_vdwxc_MOD_vdw_theta+0x414>\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr3, #0\n-\tble.w\t2b98 <__gridxc_vdwxc_MOD_vdw_theta+0x42c>\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tble.w\t2b40 <__gridxc_vdwxc_MOD_vdw_theta+0x414>\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tcmp\tr3, #0\n-\tble.w\t2b98 <__gridxc_vdwxc_MOD_vdw_theta+0x42c>\n-\tcmp.w\tr8, #1\n-\tbne.w\t2f34 <__gridxc_vdwxc_MOD_vdw_theta+0x7c8>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tble.w\t2b40 <__gridxc_vdwxc_MOD_vdw_theta+0x414>\n+\tldr\tr3, [r7, #88]\t@ 0x58\n+\tcmp\tr3, #1\n+\tbne.w\t2efa <__gridxc_vdwxc_MOD_vdw_theta+0x7ce>\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tlsls\tr4, r4, #3\n-\tldr\tr5, [r7, #76]\t@ 0x4c\n+\tldr\tr5, [r7, #72]\t@ 0x48\n+\tmov\tr0, r9\n \tadd\tr3, r4\n-\tldr.w\tsl, [r7, #52]\t@ 0x34\n+\tldr.w\tsl, [r7, #36]\t@ 0x24\n \tadd.w\tr2, r3, #8\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tldr.w\tfp, [r7, #32]\n-\tmov.w\tr8, r3, lsl #3\n-\tmov\tr0, fp\n-\tmul.w\tr1, r5, r3\n-\tmov\tfp, sl\n-\tmov\tsl, r9\n \tmov\tr9, r4\n \tmov\tr4, r5\n+\tmov.w\tr8, r3, lsl #3\n+\tmul.w\tr1, r5, r3\n \tlsls\tr1, r1, #3\n+\tmov\tr6, sl\n \tmovs\tr5, #0\n-\tstr\tr1, [r7, #92]\t@ 0x5c\n-\tmov\tr1, r5\n-\tmov\tr6, r8\n \tstr.w\tsl, [r7, #96]\t@ 0x60\n-\tadd.w\tr3, r2, r0, lsl #3\n-\tmov\tsl, r0\n-\tmov\tr5, fp\n-\tmov\tr8, r1\n-\tstr\tr2, [r7, #88]\t@ 0x58\n+\tmov\tsl, r1\n+\tmov\tr1, r8\n+\tadd.w\tr3, r2, fp, lsl #3\n+\tmov\tr8, r5\n+\tmov\tr5, r6\n+\tmov\tr6, r1\n+\tstrd\tr2, r0, [r7, #88]\t@ 0x58\n \tmov\tr1, r5\n \tmov\tr0, r3\n \tmov\tr2, r6\n \tadd.w\tr8, r8, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmov\tr3, r0\n \tadd\tr3, r9\n \tadd\tr5, r6\n-\tcmp\tr4, r8\n-\tbne.n\t2d90 <__gridxc_vdwxc_MOD_vdw_theta+0x624>\n-\tmov\tr0, sl\n+\tcmp\tr8, r4\n+\tbne.n\t2d6a <__gridxc_vdwxc_MOD_vdw_theta+0x63e>\n+\tldrd\tr2, r0, [r7, #88]\t@ 0x58\n+\tmov\tr1, sl\n \tldr\tr3, [r7, #100]\t@ 0x64\n-\tldrd\tr1, sl, [r7, #92]\t@ 0x5c\n-\tadd\tr0, r3\n-\tldr\tr5, [r7, #80]\t@ 0x50\n \tmov\tr8, r6\n-\tldr\tr2, [r7, #88]\t@ 0x58\n-\tadd\tfp, r1\n-\tadd.w\tr3, sl, #1\n-\tcmp\tsl, r5\n-\tbeq.w\t2b98 <__gridxc_vdwxc_MOD_vdw_theta+0x42c>\n-\tmov\tsl, r3\n-\tb.n\t2d78 <__gridxc_vdwxc_MOD_vdw_theta+0x60c>\n+\tldr.w\tsl, [r7, #96]\t@ 0x60\n+\tldr\tr5, [r7, #76]\t@ 0x4c\n+\tadd\tfp, r3\n+\tadd\tsl, r1\n+\tadds\tr3, r0, #1\n+\tcmp\tr5, r0\n+\tbeq.w\t2b40 <__gridxc_vdwxc_MOD_vdw_theta+0x414>\n+\tmov\tr0, r3\n+\tb.n\t2d50 <__gridxc_vdwxc_MOD_vdw_theta+0x624>\n \tcmp\tr3, #0\n \tmov\tr1, sp\n-\tit\tge\n+\tite\tge\n \tmovge\tr3, r2\n-\tit\tlt\n \tmovlt\tr3, r0\n \tldr\tr6, [r7, #96]\t@ 0x60\n \tit\tge\n \tlslge\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr1, r2\n-\tbeq.n\t2df8 <__gridxc_vdwxc_MOD_vdw_theta+0x68c>\n+\tbeq.n\t2dd0 <__gridxc_vdwxc_MOD_vdw_theta+0x6a4>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t2dea <__gridxc_vdwxc_MOD_vdw_theta+0x67e>\n+\tbne.n\t2dc2 <__gridxc_vdwxc_MOD_vdw_theta+0x696>\n \tstr\tr6, [r7, #96]\t@ 0x60\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 2e0a <__gridxc_vdwxc_MOD_vdw_theta+0x69e>\n+\tcbz\tr3, 2de2 <__gridxc_vdwxc_MOD_vdw_theta+0x6b6>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #8\n \tstr\tr3, [r7, #4]\n-\tb.n\t2b22 <__gridxc_vdwxc_MOD_vdw_theta+0x3b6>\n-\tldr\tr5, [r7, #100]\t@ 0x64\n-\tlsls\tr0, r0, #3\n+\tb.n\t2acc <__gridxc_vdwxc_MOD_vdw_theta+0x3a0>\n+\tldr\tr0, [r7, #92]\t@ 0x5c\n \tlsls\tr4, r4, #3\n-\tldr.w\tr9, [r7, #56]\t@ 0x38\n+\tldr\tr5, [r7, #100]\t@ 0x64\n+\tmov\tr6, fp\n+\tldr.w\tr9, [r7, #52]\t@ 0x34\n \tadd.w\tlr, r3, r5\n-\tldr\tr3, [r7, #68]\t@ 0x44\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tlsls\tr0, r0, #3\n \tadd.w\tr5, r2, #240\t@ 0xf0\n-\tmov\tr6, fp\n \tadd\tr3, r0\n \tstr\tr3, [r7, #92]\t@ 0x5c\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tadd\tr3, r4\n \tmov\tsl, r3\n \tmovs\tr3, #1\n \tstr\tr3, [r7, #96]\t@ 0x60\n \tldr\tr3, [r7, #92]\t@ 0x5c\n \tmov\tfp, r2\n \tldr.w\tip, [r7, #36]\t@ 0x24\n \tadd.w\tr3, r3, r9, lsl #3\n-\tvldmia\tfp!, {d17}\n-\tvldmia\tip!, {d16}\n-\tvfma.f64\td16, d18, d17\n+\tvldmia\tfp!, {d6}\n+\tvldmia\tip!, {d7}\n+\tvmla.f64\td7, d5, d6\n \tcmp\tip, r1\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tadd\tr3, r0\n-\tbne.n\t2e40 <__gridxc_vdwxc_MOD_vdw_theta+0x6d4>\n+\tbne.n\t2e1a <__gridxc_vdwxc_MOD_vdw_theta+0x6ee>\n \tldr.w\tfp, [r7, #20]\n \tmov\tip, lr\n-\tstr\tr6, [r7, #84]\t@ 0x54\n-\tvldmia\tfp!, {d17}\n+\tstr\tr6, [r7, #80]\t@ 0x50\n+\tvldmia\tfp!, {d6}\n \tadd.w\tr6, sl, ip, lsl #3\n \tmov\tr3, r2\n-\tvmul.f64\td17, d17, d8\n-\tvldmia\tr3!, {d16}\n-\tvmul.f64\td16, d16, d17\n+\tvmul.f64\td6, d6, d8\n+\tvldmia\tr3!, {d7}\n+\tvmul.f64\td7, d7, d6\n \tcmp\tr3, r5\n-\tvstr\td16, [r6]\n+\tvstr\td7, [r6]\n \tadd\tr6, r4\n-\tbne.n\t2e6c <__gridxc_vdwxc_MOD_vdw_theta+0x700>\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tadd\tip, r8\n-\tcmp\tfp, r3\n-\tbne.n\t2e5e <__gridxc_vdwxc_MOD_vdw_theta+0x6f2>\n+\tbne.n\t2e46 <__gridxc_vdwxc_MOD_vdw_theta+0x71a>\n+\tldr\tr3, [r7, #88]\t@ 0x58\n+\tcmp\tfp, r8\n+\tadd\tip, r3\n+\tbne.n\t2e38 <__gridxc_vdwxc_MOD_vdw_theta+0x70c>\n \tldr\tr3, [r7, #96]\t@ 0x60\n-\tldr\tr6, [r7, #84]\t@ 0x54\n+\tldr\tr6, [r7, #80]\t@ 0x50\n \tsub.w\tr3, r3, #1\n \tclz\tr3, r3\n \tlsrs\tr3, r3, #5\n \tcmp\tr3, #0\n \tldr\tr3, [r7, #100]\t@ 0x64\n+\tite\tne\n+\tmovne.w\tip, #2\n+\tmoveq.w\tip, #3\n \tadd\tlr, r3\n-\tldr\tr3, [r7, #88]\t@ 0x58\n+\tldr\tr3, [r7, #84]\t@ 0x54\n+\tcmp\tr6, ip\n \tadd\tr9, r3\n \tmov.w\tr3, #2\n \tstr\tr3, [r7, #96]\t@ 0x60\n-\tit\teq\n-\tmoveq\tr3, #3\n-\tcmp\tr6, r3\n-\tbge.n\t2e34 <__gridxc_vdwxc_MOD_vdw_theta+0x6c8>\n-\tb.n\t2adc <__gridxc_vdwxc_MOD_vdw_theta+0x370>\n-\tldr\tr3, [r7, #64]\t@ 0x40\n-\tmov.w\tr0, r8, lsl #3\n+\tbge.n\t2e0e <__gridxc_vdwxc_MOD_vdw_theta+0x6e2>\n+\tb.n\t2a88 <__gridxc_vdwxc_MOD_vdw_theta+0x35c>\n+\tlsls\tr0, r3, #3\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tldr.w\tfp, [r7, #40]\t@ 0x28\n-\tvmov.i64\td16, #0x0000000000000000\n+\tmov.w\tsl, #0\n \tldr\tr6, [r7, #96]\t@ 0x60\n \tadd.w\tr9, r3, r0\n-\tmov.w\tsl, #0\n-\tmov\tr3, r1\n-\tstr.w\tr8, [r7, #84]\t@ 0x54\n+\tvldr\td7, [pc, #300]\t@ 2fd0 <__gridxc_vdwxc_MOD_vdw_theta+0x8a4>\n+\tmov\tip, r1\n+\tmov\tr3, r8\n \tmov\tlr, fp\n \tmov.w\tr8, #0\n \tstr.w\tsl, [r7, #96]\t@ 0x60\n-\tadd.w\tsl, r9, lr, lsl #3\n-\tmov.w\tip, #0\n-\tcmp\tip, r5\n-\tvstr\td16, [sl]\n-\tadd.w\tip, ip, #1\n-\tadd\tsl, r0\n-\tbne.n\t2ede <__gridxc_vdwxc_MOD_vdw_theta+0x772>\n+\tstr.w\tfp, [r7, #80]\t@ 0x50\n+\tadd.w\tfp, r9, lr, lsl #3\n+\tmov.w\tsl, #0\n+\tcmp\tsl, r5\n+\tvstr\td7, [fp]\n+\tadd.w\tsl, sl, #1\n+\tadd\tfp, r0\n+\tbne.n\t2ebe <__gridxc_vdwxc_MOD_vdw_theta+0x792>\n \tadd\tlr, r4\n \tadd.w\tr1, r8, #1\n \tcmp\tr8, r6\n-\tbeq.n\t2efa <__gridxc_vdwxc_MOD_vdw_theta+0x78e>\n+\tbeq.n\t2eda <__gridxc_vdwxc_MOD_vdw_theta+0x7ae>\n \tmov\tr8, r1\n-\tb.n\t2ed6 <__gridxc_vdwxc_MOD_vdw_theta+0x76a>\n-\tldrd\tsl, r1, [r7, #96]\t@ 0x60\n+\tb.n\t2eb6 <__gridxc_vdwxc_MOD_vdw_theta+0x78a>\n+\tldr\tr1, [r7, #100]\t@ 0x64\n+\tldr.w\tfp, [r7, #80]\t@ 0x50\n+\tldr.w\tsl, [r7, #96]\t@ 0x60\n \tadd\tfp, r1\n-\tldr\tr1, [r7, #80]\t@ 0x50\n-\tadd.w\tip, sl, #1\n+\tldr\tr1, [r7, #76]\t@ 0x4c\n+\tadd.w\tlr, sl, #1\n \tcmp\tsl, r1\n-\tbeq.n\t2f0e <__gridxc_vdwxc_MOD_vdw_theta+0x7a2>\n-\tmov\tsl, ip\n-\tb.n\t2ecc <__gridxc_vdwxc_MOD_vdw_theta+0x760>\n-\tldr.w\tr8, [r7, #84]\t@ 0x54\n-\tmov\tr1, r3\n-\tb.n\t2a1e <__gridxc_vdwxc_MOD_vdw_theta+0x2b2>\n-\tldr\tr2, [r7, #72]\t@ 0x48\n-\tldr\tr1, [r7, #28]\n-\tmul.w\tr2, r1, r2\n-\tlsls\tr2, r2, #3\n-\tb.n\t2cd0 <__gridxc_vdwxc_MOD_vdw_theta+0x564>\n-\tldr\tr0, [r7, #76]\t@ 0x4c\n-\tldr\tr2, [r7, #84]\t@ 0x54\n-\tmul.w\tr2, r0, r2\n-\tldr\tr0, [r7, #24]\n-\tmul.w\tr2, r0, r2\n-\tlsls\tr2, r2, #3\n-\tb.n\t2c8e <__gridxc_vdwxc_MOD_vdw_theta+0x522>\n-\tldr\tr3, [r7, #52]\t@ 0x34\n-\tmov.w\tr8, r8, lsl #3\n+\tbeq.n\t2ef4 <__gridxc_vdwxc_MOD_vdw_theta+0x7c8>\n+\tmov\tsl, lr\n+\tb.n\t2ea8 <__gridxc_vdwxc_MOD_vdw_theta+0x77c>\n+\tmov\tr1, ip\n+\tmov\tr8, r3\n+\tb.n\t29ca <__gridxc_vdwxc_MOD_vdw_theta+0x29e>\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tmov\tr2, r9\n-\tldr\tr1, [r7, #76]\t@ 0x4c\n-\tldr.w\tip, [r7, #40]\t@ 0x28\n+\tldr\tr1, [r7, #72]\t@ 0x48\n \tmov\tlr, r2\n+\tldr.w\tip, [r7, #40]\t@ 0x28\n \tadd.w\tr5, r3, r5, lsl #3\n-\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldr\tr3, [r7, #88]\t@ 0x58\n \tadd.w\tfp, r5, #8\n+\tmov.w\tr8, r3, lsl #3\n+\tldr\tr3, [r7, #60]\t@ 0x3c\n \tadd\tr3, r8\n \tmov\tr9, r3\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tmov.w\tsl, r3, lsl #3\n \tmul.w\tr1, r1, r3\n \tstr\tr1, [r7, #96]\t@ 0x60\n \tmov\tr1, fp\n \tadd.w\tr0, r1, r2, lsl #3\n \tmov\tfp, ip\n \tmov\tr6, r2\n \tmovs\tr5, #0\n \tstr.w\tlr, [r7, #92]\t@ 0x5c\n-\tldr\tr3, [r7, #52]\t@ 0x34\n+\tldr\tr3, [r7, #36]\t@ 0x24\n \tadd.w\tlr, r3, r6, lsl #3\n \tadd.w\tr3, r9, fp, lsl #3\n-\tvldmia\tlr!, {d16}\n-\tvstr\td16, [r3]\n+\tvldmia\tlr!, {d7}\n+\tvstr\td7, [r3]\n \tcmp\tr0, lr\n \tadd\tr3, r8\n-\tbne.n\t2f78 <__gridxc_vdwxc_MOD_vdw_theta+0x80c>\n-\tldr\tr3, [r7, #84]\t@ 0x54\n+\tbne.n\t2f40 <__gridxc_vdwxc_MOD_vdw_theta+0x814>\n+\tldr\tr3, [r7, #80]\t@ 0x50\n \tadds\tr5, #1\n \tadd\tfp, r4\n \tadd\tr0, sl\n \tadd\tr6, r3\n-\tldr\tr3, [r7, #76]\t@ 0x4c\n+\tldr\tr3, [r7, #72]\t@ 0x48\n \tcmp\tr5, r3\n-\tbne.n\t2f6e <__gridxc_vdwxc_MOD_vdw_theta+0x802>\n+\tbne.n\t2f36 <__gridxc_vdwxc_MOD_vdw_theta+0x80a>\n \tldrd\tlr, r3, [r7, #92]\t@ 0x5c\n-\tldr\tr0, [r7, #80]\t@ 0x50\n+\tldr\tr0, [r7, #76]\t@ 0x4c\n \tadd\tr2, r3\n \tldr\tr3, [r7, #100]\t@ 0x64\n \tcmp\tlr, r0\n \tadd\tip, r3\n \tadd.w\tr3, lr, #1\n-\tbeq.w\t2b98 <__gridxc_vdwxc_MOD_vdw_theta+0x42c>\n+\tbeq.w\t2b40 <__gridxc_vdwxc_MOD_vdw_theta+0x414>\n \tmov\tlr, r3\n-\tb.n\t2f60 <__gridxc_vdwxc_MOD_vdw_theta+0x7f4>\n+\tb.n\t2f28 <__gridxc_vdwxc_MOD_vdw_theta+0x7fc>\n \tmov.w\tlr, r3, lsl #3\n-\tldr\tr3, [r7, #68]\t@ 0x44\n-\tldr\tr0, [r7, #48]\t@ 0x30\n+\tldr\tr3, [r7, #64]\t@ 0x40\n+\tldrd\tr0, ip, [r7, #48]\t@ 0x30\n \tadd\tr3, lr\n-\tldr.w\tip, [r7, #56]\t@ 0x38\n \tmov\tfp, r3\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tmov\tr6, r0\n \tmov.w\tsl, r3, lsl #3\n \tldr\tr3, [r7, #20]\n \tadd.w\tr1, r3, sl\n \tldr\tr3, [r7, #20]\n \tadd.w\tr2, r3, r0, lsl #3\n \tadd.w\tr3, fp, ip, lsl #3\n-\tvldmia\tr2!, {d16}\n-\tvstr\td16, [r3]\n+\tvldmia\tr2!, {d7}\n+\tvstr\td7, [r3]\n \tcmp\tr2, r1\n \tadd\tr3, lr\n-\tbne.n\t2fd8 <__gridxc_vdwxc_MOD_vdw_theta+0x86c>\n-\tldr\tr3, [r7, #72]\t@ 0x48\n+\tbne.n\t2f9e <__gridxc_vdwxc_MOD_vdw_theta+0x872>\n+\tldr\tr3, [r7, #68]\t@ 0x44\n \tadd\tr1, sl\n-\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr2, [r7, #56]\t@ 0x38\n \tadd\tr0, r3\n-\tldr\tr3, [r7, #88]\t@ 0x58\n+\tldr\tr3, [r7, #84]\t@ 0x54\n \tcmp\tr6, r2\n \tadd\tip, r3\n \tadd.w\tr3, r6, #1\n-\tbeq.w\t2b90 <__gridxc_vdwxc_MOD_vdw_theta+0x424>\n+\tbeq.w\t2b38 <__gridxc_vdwxc_MOD_vdw_theta+0x40c>\n \tmov\tr6, r3\n-\tb.n\t2fce <__gridxc_vdwxc_MOD_vdw_theta+0x862>\n+\tb.n\t2f94 <__gridxc_vdwxc_MOD_vdw_theta+0x868>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000868\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000007e8\n- R_ARM_REL32\t.data\n-\t.word\t0x000007b8\n- R_ARM_REL32\t.LC21\n-\t.word\t0x0000052c\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\tnop\n+\tnop.w\n+\t...\n \n-00003018 <__gridxc_vdwxc_MOD_vdw_set_kcut>:\n+00002fd8 <__gridxc_vdwxc_MOD_vdw_set_kcut>:\n __gridxc_vdwxc_MOD_vdw_set_kcut():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip, #3672]\t@ 0xe58\n-\tldr\tr5, [pc, #784]\t@ (3360 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x348>)\n+\tldr\tr6, [pc, #784]\t@ (3320 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x348>)\n \tsub.w\tsp, sp, #16640\t@ 0x4100\n-\tldr\tr6, [pc, #784]\t@ (3364 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x34c>)\n+\tldr\tr5, [pc, #784]\t@ (3324 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x34c>)\n \tsub\tsp, #68\t@ 0x44\n-\tadd\tr5, pc\n-\tldr\tr1, [pc, #780]\t@ (3368 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x350>)\n-\tmov\tr9, r5\n-\tldr\tr5, [pc, #780]\t@ (336c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x354>)\n \tadd\tr6, pc\n-\tldr\tr3, [pc, #780]\t@ (3370 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x358>)\n+\tldr\tr1, [pc, #780]\t@ (3328 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x350>)\n+\tldr\tr3, [pc, #784]\t@ (332c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x354>)\n \tadd.w\tr7, sp, #16640\t@ 0x4100\n+\tldr.w\tr9, [pc, #780]\t@ 3330 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x358>\n \tadd\tr1, pc\n-\tmov\tr4, r0\n-\tadds\tr7, #60\t@ 0x3c\n \tldr\tr5, [r6, r5]\n+\tmov\tr4, r0\n \tadd\tr3, pc\n \tmovs\tr2, #2\n \tadds\tr1, #24\n \tmovs\tr0, #5\n+\tadd\tr9, pc\n+\tadds\tr7, #60\t@ 0x3c\n \tldr\tr5, [r5, #0]\n \tstr\tr5, [r7, #0]\n \tmov.w\tr5, #0\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t3c2c <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc14>\n-\tldr\tr5, [pc, #744]\t@ (3374 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x35c>)\n-\tvldr\td12, [r4]\n+\tbeq.w\t3c1c <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc44>\n+\tldr\tr5, [pc, #744]\t@ (3334 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x35c>)\n+\tvldr\td7, [r4]\n \tadd\tr5, pc\n-\tvldr\td16, [r5, #440]\t@ 0x1b8\n-\tvcmp.f64\td12, d16\n+\tvmov.f64\td6, d7\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [r5, #440]\t@ 0x1b8\n+\tvcmp.f64\td6, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.w\t3c02 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xbea>\n+\tbeq.w\t3bf2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc1a>\n \tldr.w\tr4, [r5, #448]\t@ 0x1c0\n \tcmp\tr4, #0\n-\tbeq.w\t3e36 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xe1e>\n+\tbeq.w\t3e28 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xe50>\n \tadd\tr3, sp, #320\t@ 0x140\n-\tstr\tr3, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tadd\tr3, sp, #304\t@ 0x130\n-\tstr\tr3, [sp, #96]\t@ 0x60\n-\tadd\tr3, sp, #216\t@ 0xd8\n-\tstr\tr3, [sp, #116]\t@ 0x74\n-\tldr\tr5, [pc, #704]\t@ (3378 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x360>)\n+\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tadd\tr3, sp, #224\t@ 0xe0\n+\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr5, [pc, #696]\t@ (3338 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x360>)\n \tmovs\tr4, #0\n-\tldr\tr0, [pc, #704]\t@ (337c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x364>)\n+\tldr\tr6, [pc, #696]\t@ (333c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x364>)\n \tmov.w\tsl, #17\n \tadd\tr5, pc\n-\tldr\tr3, [pc, #700]\t@ (3380 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x368>)\n+\tldr\tr3, [pc, #692]\t@ (3340 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x368>)\n \tadd.w\tfp, r5, #2112\t@ 0x840\n+\tadd\tr6, pc\n \tadd.w\tr8, r5, #2128\t@ 0x850\n \taddw\tr7, r5, #2116\t@ 0x844\n-\tadd\tr0, pc\n-\tadds\tr5, #16\n-\tmov\tr6, r0\n \tadd\tr3, pc\n+\tadds\tr5, #16\n \tmov\tr2, r8\n \tmov\tr1, r7\n-\tadd.w\tr0, r0, #456\t@ 0x1c8\n+\tadd.w\tr0, r6, #452\t@ 0x1c4\n \tstr\tr3, [sp, #12]\n-\tmov\tr3, fp\n \tstr.w\tsl, [sp, #28]\n+\tmov\tr3, fp\n \tstr.w\tfp, [sp, #4]\n \tstr\tr5, [sp, #8]\n \tstr\tr5, [sp, #0]\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr3, [pc, #644]\t@ (3384 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x36c>)\n+\tldr\tr3, [pc, #640]\t@ (3344 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x36c>)\n \tmov\tr2, r8\n \tmov\tr1, r7\n \tadd\tr3, pc\n-\tadd.w\tr0, r6, #520\t@ 0x208\n+\tadd.w\tr0, r6, #512\t@ 0x200\n \tstrd\tsl, r4, [sp, #28]\n \tmov.w\tsl, #21\n \tstr\tr3, [sp, #12]\n \tmov\tr3, fp\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstrd\tfp, r5, [sp, #4]\n \tstr\tr5, [sp, #0]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr3, [pc, #608]\t@ (3388 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x370>)\n+\tldr\tr3, [pc, #604]\t@ (3348 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x370>)\n \tmov\tr2, r8\n \tmov\tr1, r7\n \tadd\tr3, pc\n-\tadd.w\tr0, r6, #584\t@ 0x248\n+\tadd.w\tr0, r6, #572\t@ 0x23c\n \tstr\tr3, [sp, #12]\n \tmov\tr3, fp\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstrd\tfp, r5, [sp, #4]\n \tstr\tr5, [sp, #0]\n \tstr.w\tsl, [sp, #28]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr0, [pc, #576]\t@ (338c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x374>)\n+\tldr\tr0, [pc, #568]\t@ (334c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x374>)\n \tmov\tr2, r8\n \tmov\tr1, r7\n \tmov\tr3, fp\n \tadd\tr0, pc\n \tstr.w\tsl, [sp, #28]\n \tstr\tr0, [sp, #12]\n-\tadd.w\tr0, r6, #648\t@ 0x288\n+\tadd.w\tr0, r6, #632\t@ 0x278\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstr\tr5, [sp, #8]\n \tstrd\tr5, fp, [sp]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tvldr\td16, [pc, #452]\t@ 3338 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x320>\n-\tldr\tr3, [sp, #100]\t@ 0x64\n+\tvldr\td7, [pc, #440]\t@ 32f0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x318>\n+\tvldr\td6, [sp, #96]\t@ 0x60\n \tmovs\tr0, #0\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \tmovs\tr1, #0\n \tmovt\tr1, #16297\t@ 0x3fa9\n-\tvmul.f64\td16, d12, d16\n-\tsub.w\tr2, r3, #112\t@ 0x70\n-\tstrd\tr0, r1, [r6, #712]\t@ 0x2c8\n-\tadd\tr1, pc, #452\t@ (adr r1, 3350 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x338>)\n+\tstrd\tr0, r1, [r6, #696]\t@ 0x2b8\n+\tvmul.f64\td7, d6, d7\n+\tadd\tr1, pc, #444\t@ (adr r1, 3310 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x338>)\n \tldrd\tr0, r1, [r1]\n-\tstrd\tr0, r1, [r6, #720]\t@ 0x2d0\n-\tvcvt.s32.f64\ts15, d16\n-\tstr\tr2, [sp, #144]\t@ 0x90\n-\tadd\tr1, pc, #444\t@ (adr r1, 3358 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x340>)\n+\tstrd\tr0, r1, [r6, #704]\t@ 0x2c0\n+\tadd\tr1, pc, #444\t@ (adr r1, 3318 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x340>)\n \tldrd\tr0, r1, [r1]\n-\tstrd\tr0, r1, [r2, #-8]\n+\tvcvt.s32.f64\ts15, d7\n+\tstrd\tr0, r1, [r2, #-112]\t@ 0x70\n \tvmov\tr3, s15\n \tadds\tr3, #1\n-\tstr.w\tr3, [r6, #728]\t@ 0x2d8\n+\tstr.w\tr3, [r6, #712]\t@ 0x2c8\n \tcmp.w\tr3, #2048\t@ 0x800\n-\tble.n\t31c4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x1ac>\n-\tldr\tr3, [pc, #472]\t@ (3390 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x378>)\n+\tble.n\t3188 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x1b0>\n+\tldr\tr3, [pc, #468]\t@ (3350 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x378>)\n \tmovs\tr1, #26\n-\tldr\tr0, [pc, #472]\t@ (3394 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x37c>)\n+\tldr\tr0, [pc, #468]\t@ (3354 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x37c>)\n \tadd\tr0, pc\n \tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tldr.w\tfp, [pc, #460]\t@ 3398 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x380>\n-\tvmov.i64\td13, #0x0000000000000000\n+\tvldr\td6, [sp, #96]\t@ 0x60\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n \tmovs\tr3, #1\n-\tvdiv.f64\td10, d16, d12\n-\tadd\tfp, pc\n-\tmov\tr9, fp\n \tstr\tr3, [sp, #68]\t@ 0x44\n-\tadd\tr3, sp, #192\t@ 0xc0\n-\tstr\tr3, [sp, #112]\t@ 0x70\n-\tadd\tr3, sp, #224\t@ 0xe0\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tadd\tr3, sp, #264\t@ 0x108\n-\tstr\tr3, [sp, #84]\t@ 0x54\n \tadd\tr3, sp, #200\t@ 0xc8\n-\tstr\tr3, [sp, #140]\t@ 0x8c\n-\tadd\tr3, sp, #176\t@ 0xb0\n+\tstr\tr3, [sp, #144]\t@ 0x90\n+\tvdiv.f64\td14, d7, d6\n+\tldr\tr3, [pc, #440]\t@ (3358 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x380>)\n+\tvldr\td15, [pc, #344]\t@ 32f8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x320>\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr3, [pc, #436]\t@ (335c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x384>)\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #80]\t@ 0x50\n+\tadd\tr3, sp, #216\t@ 0xd8\n+\tstr\tr3, [sp, #152]\t@ 0x98\n+\tadd\tr3, sp, #232\t@ 0xe8\n \tstr\tr3, [sp, #92]\t@ 0x5c\n-\tadd\tr3, sp, #160\t@ 0xa0\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n+\tadd\tr3, sp, #268\t@ 0x10c\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tadd\tr3, sp, #208\t@ 0xd0\n+\tstr\tr3, [sp, #148]\t@ 0x94\n+\tadd\tr3, sp, #192\t@ 0xc0\n+\tstr\tr3, [sp, #104]\t@ 0x68\n+\tadd\tr3, sp, #176\t@ 0xb0\n+\tstr\tr3, [sp, #120]\t@ 0x78\n \tadd\tr3, sp, #184\t@ 0xb8\n-\tstr\tr3, [sp, #136]\t@ 0x88\n-\tadd\tr3, sp, #156\t@ 0x9c\n-\tstr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #140]\t@ 0x8c\n \tadd\tr3, sp, #168\t@ 0xa8\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tadd\tr3, sp, #164\t@ 0xa4\n \tstr\tr3, [sp, #132]\t@ 0x84\n-\tadd.w\tr3, fp, #476\t@ 0x1dc\n-\tstr\tr3, [sp, #80]\t@ 0x50\n \tmovs\tr2, #1\n+\tldr\tr3, [sp, #116]\t@ 0x74\n \tstr\tr2, [sp, #64]\t@ 0x40\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tvmov.i32\td11, #0\t@ 0x00000000\n-\tldr\tr6, [sp, #100]\t@ 0x64\n-\tadd.w\tr3, r9, #176\t@ 0xb0\n-\tmov\tfp, r9\n-\tstr\tr3, [sp, #104]\t@ 0x68\n+\tadds\tr3, #176\t@ 0xb0\n+\tstr\tr3, [sp, #112]\t@ 0x70\n \tadd.w\tr3, r3, r2, lsl #3\n-\tstr\tr3, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #128]\t@ 0x80\n \tadds\tr3, r2, #1\n-\tstr\tr3, [sp, #148]\t@ 0x94\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tldr\tr5, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #156]\t@ 0x9c\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tmovs\tr5, #0\n \tldr\tr4, [sp, #144]\t@ 0x90\n-\tmov\tr1, r5\n+\tldr\tr0, [sp, #152]\t@ 0x98\n+\tmov\tr1, r4\n+\tldr\tr7, [pc, #364]\t@ (3360 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x388>)\n \tvldmia\tr3!, {d0}\n+\tadd\tr7, pc\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tbl\t2540 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>\n+\tldr\tr2, [sp, #128]\t@ 0x80\n+\tmov\tr1, r4\n+\tldr\tr4, [sp, #124]\t@ 0x7c\n \tmov\tr0, r4\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tbl\t2578 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n-\tmov\tr1, r5\n-\tldr\tr0, [sp, #116]\t@ 0x74\n-\tmovs\tr5, #0\n-\tvldr\td0, [r3, #-8]\n-\tbl\t2578 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tldr.w\tr8, [sp, #96]\t@ 0x60\n-\tvldr\td9, [r4]\n-\tstr.w\tr8, [sp, #120]\t@ 0x78\n-\tvldr\td8, [r3, #-8]\n-\tldr\tr3, [pc, #320]\t@ (339c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x384>)\n-\tadd\tr3, pc\n-\tadd.w\tr2, r3, #476\t@ 0x1dc\n-\tldr.w\tr1, [r3, #504]\t@ 0x1f8\n-\tldr.w\tr0, [r3, #492]\t@ 0x1ec\n-\tvld1.32\t{d16}, [r2]\n-\tldr.w\tr2, [r3, #456]\t@ 0x1c8\n-\tldr.w\tr3, [r3, #460]\t@ 0x1cc\n-\tstr\tr3, [sp, #52]\t@ 0x34\n+\tvldr\td0, [r2, #-8]\n+\tbl\t2540 <__gridxc_vdwxc_MOD_saturate_inverse.constprop.0.isra.0>\n+\tldr\tr3, [sp, #116]\t@ 0x74\n+\tldr.w\tr8, [sp, #108]\t@ 0x6c\n+\tvldr\td9, [r4, #-8]\n+\tldr.w\tr0, [r3, #452]\t@ 0x1c4\n+\tldr.w\tr2, [r3, #500]\t@ 0x1f4\n+\tldr.w\tr1, [r3, #488]\t@ 0x1e8\n+\tldr.w\tfp, [r3, #456]\t@ 0x1c8\n+\tstr\tr0, [sp, #48]\t@ 0x30\n+\tldr.w\tr0, [r3, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r3, #472]\t@ 0x1d8\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvmov.32\tr2, d16[1]\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n-\tstr\tr0, [sp, #72]\t@ 0x48\n-\tmul.w\tsl, r1, r3\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tvldr\td8, [r4]\n+\tstr\tr1, [sp, #72]\t@ 0x48\n+\tmul.w\tsl, r2, r3\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tmov\tr1, sl\n-\tmul.w\tr9, r0, r3\n+\tstr\tr0, [sp, #52]\t@ 0x34\n+\tmov\tr2, sl\n+\tmul.w\tr9, r1, r3\n \tmov\tsl, r9\n-\tmov\tr9, r6\n-\tldr\tr3, [sp, #52]\t@ 0x34\n+\tmov\tr9, r8\n \tvmov\ts15, r5\n-\tvldr\td17, [fp, #712]\t@ 0x2c8\n-\tadds\tr4, r1, r3\n-\tvcvt.f64.s32\td16, s15\n+\tldr\tr1, [sp, #52]\t@ 0x34\n+\tadd.w\tr4, r2, fp\n+\tvldr\td6, [r7, #696]\t@ 0x2b8\n+\tvcvt.f64.s32\td7, s15\n \tadd\tr4, sl\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tldr\tr6, [sp, #48]\t@ 0x30\n-\tldr.w\tr3, [fp, #432]\t@ 0x1b0\n-\tvmul.f64\td16, d16, d17\n-\tmla\tr7, r5, r2, r4\n-\tvmul.f64\td14, d16, d9\n-\tvmul.f64\td15, d16, d8\n-\tmla\tr7, r0, r7, r6\n-\tvstmia\tr8!, {d16}\n+\tldr.w\tr3, [r7, #432]\t@ 0x1b0\n+\tmla\tr6, r1, r5, r4\n+\tvmul.f64\td7, d7, d6\n+\tldrd\tr0, r1, [sp, #44]\t@ 0x2c\n+\tvmul.f64\td11, d7, d9\n+\tvmul.f64\td10, d7, d8\n+\tmla\tr6, r0, r6, r1\n+\tvstmia\tr8!, {d7}\n \tcmp\tr3, #0\n-\tbeq.w\t3c56 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc3e>\n-\tvmov.f64\td16, #62\t@ 0x41f00000 30.0\n-\tmovs\tr0, #1\n-\tvcmpe.f64\td14, d16\n+\tbeq.w\t3c46 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc6e>\n+\tvmov.f64\td7, #62\t@ 0x41f00000 30.0\n+\tvcmpe.f64\td11, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvcmpe.f64\td15, d16\n-\tit\tlt\n-\tmovlt\tr0, #0\n+\tvcmpe.f64\td10, d7\n+\tite\tge\n+\tmovge\tr3, #1\n+\tmovlt\tr3, #0\n \tvmrs\tAPSR_nzcv, fpscr\n-\torr.w\tr3, r0, #1\n-\tit\tlt\n-\tmovlt\tr3, r0\n+\tit\tge\n+\torrge.w\tr3, r3, #1\n \tcmp\tr3, #0\n-\tbeq.w\t3c94 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xc7c>\n+\tbeq.w\t3c82 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xcaa>\n \tadds\tr5, #1\n \tmovw\tr3, #2049\t@ 0x801\n-\tvstr\td13, [r7]\n+\tvstr\td15, [r6]\n \tcmp\tr5, r3\n-\tbne.n\t3298 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x280>\n-\tldr\tr3, [pc, #152]\t@ (33a0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x388>)\n+\tbne.n\t3250 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x278>\n+\tldrd\tr2, r3, [sp, #44]\t@ 0x2c\n \tmov\tr6, r9\n-\tldr\tr1, [sp, #48]\t@ 0x30\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n+\tldr\tr0, [sp, #52]\t@ 0x34\n+\tvmov.f64\td2, #112\t@ 0x3f800000 1.0\n+\tvldr\td4, [pc, #52]\t@ 3300 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x328>\n+\tmla\tr4, r2, r4, r3\n+\tldr\tr3, [pc, #144]\t@ (3364 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x38c>)\n+\tvldr\td3, [pc, #48]\t@ 3308 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x330>\n \tadd\tr3, pc\n-\tldr\tr7, [sp, #120]\t@ 0x78\n-\tvldr\td19, [pc, #40]\t@ 3340 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x328>\n-\tvldr\td20, [pc, #44]\t@ 3348 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x330>\n-\tldr.w\tr0, [r3, #484]\t@ 0x1e4\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tmla\tr4, r4, r3, r1\n-\tldr\tr1, [sp, #96]\t@ 0x60\n-\tmul.w\tr3, r2, r3\n-\tadd.w\tr1, r1, #16384\t@ 0x4000\n-\tadds\tr1, #8\n-\tb.n\t33b2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x39a>\n+\tmul.w\tr2, r0, r2\n+\tldr.w\tr1, [r3, #480]\t@ 0x1e0\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tadd.w\tr3, r3, #16384\t@ 0x4000\n+\tadds\tr3, #8\n+\tb.n\t3376 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x39e>\n \tnop.w\n \t.word\t0xab8b494c\n \t.word\t0x403fd4bb\n+\t...\n \t.word\t0x47ae147b\n \t.word\t0x3f847ae1\n \t.word\t0x00000000\n \t.word\t0x40590000\n \t.word\t0x9217271a\n \t.word\t0x3fa015bf\n \t.word\t0x9217271a\n \t.word\t0x405015bf\n \t.word\t0x00000306\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000302\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002fe\n- R_ARM_REL32\t.data\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000300\n+ R_ARM_REL32\t.data\n \t.word\t0x000002fe\n R_ARM_REL32\t.LC21\n+\t.word\t0x000002fa\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x000002e2\n R_ARM_REL32\t.bss\n-\t.word\t0x000002b4\n+\t.word\t0x000002ac\n R_ARM_REL32\t.rodata\n \t.word\t0x000002a8\n R_ARM_REL32\t.bss\n-\t.word\t0x000002a6\n+\t.word\t0x000002a2\n R_ARM_REL32\t.LC24\n-\t.word\t0x0000027e\n+\t.word\t0x00000278\n R_ARM_REL32\t.LC25\n-\t.word\t0x0000025a\n+\t.word\t0x00000254\n R_ARM_REL32\t.LC26\n-\t.word\t0x00000236\n+\t.word\t0x00000230\n R_ARM_REL32\t.LC27\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000001d6\n+\t.word\t0x000001d2\n R_ARM_REL32\t.LC28\n-\t.word\t0x000001be\n+\t.word\t0x000001b2\n R_ARM_REL32\t.bss\n-\t.word\t0x0000013c\n+\t.word\t0x000001b0\n R_ARM_REL32\t.bss\n-\t.word\t0x0000008c\n+\t.word\t0x00000166\n R_ARM_REL32\t.bss\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvstr\td17, [r4]\n-\tcmp\tr1, r7\n-\tadd\tr4, r3\n-\tbeq.n\t33f8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x3e0>\n-\tvldmia\tr7!, {d18}\n-\tvldr\td17, [r4]\n-\tvmul.f64\td16, d18, d19\n-\tvcmpe.f64\td16, #0.0\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t33a8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x390>\n-\tvcmpe.f64\td18, d20\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\t33a4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x38c>\n-\tvmul.f64\td16, d16, d16\n-\tvmov.f64\td18, d21\n-\tcmp\tr1, r7\n-\tvmul.f64\td16, d16, d16\n-\tvfms.f64\td18, d16, d16\n-\tvmul.f64\td16, d18, d18\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td17, d17, d16\n-\tvstr\td17, [r4]\n-\tadd\tr4, r3\n-\tbne.n\t33b2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x39a>\n-\tldr\tr4, [pc, #468]\t@ (35d0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5b8>)\n-\tmovs\tr3, #8\n-\tldr\tr5, [sp, #68]\t@ 0x44\n-\tnegs\tr7, r2\n+\t.word\t0x00000088\n+ R_ARM_REL32\t.bss\n+\tvldr\td6, [pc, #548]\t@ 3590 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5b8>\n+\tvstr\td6, [r4]\n+\tcmp\tr3, r6\n+\tadd\tr4, r2\n+\tbeq.n\t33bc <__gridxc_vdwxc_MOD_vdw_set_kcut+0x3e4>\n+\tvldmia\tr6!, {d5}\n+\tvldr\td6, [r4]\n+\tvmul.f64\td7, d5, d4\n+\tvcmpe.f64\td7, #0.0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\t336c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x394>\n+\tvcmpe.f64\td5, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbge.n\t3368 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x390>\n+\tvmul.f64\td7, d7, d7\n+\tvmov.f64\td5, d2\n+\tcmp\tr3, r6\n+\tvmul.f64\td7, d7, d7\n+\tvmls.f64\td5, d7, d7\n+\tvmul.f64\td7, d5, d5\n+\tvmul.f64\td7, d7, d7\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td6, [r4]\n+\tadd\tr4, r2\n+\tbne.n\t3376 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x39e>\n+\tldr\tr7, [sp, #84]\t@ 0x54\n+\trsb\tr1, r1, #1\n+\tldr\tr4, [pc, #476]\t@ (35a0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5c8>)\n+\tmovw\tr8, #769\t@ 0x301\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n \tadd\tr4, pc\n-\tstr.w\tr3, [r6, #-88]\n+\tstr.w\tr3, [r7, #-68]\n+\tmovs\tr3, #0\n+\tstrd\tr3, r3, [r7, #-76]\t@ 0x4c\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r7, #-80]\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r6, #-68]\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tsub.w\tr2, r6, #76\t@ 0x4c\n-\tldr.w\tr3, [r4, #508]\t@ 0x1fc\n-\trsb\tip, r0, #1\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tmovw\tr8, #769\t@ 0x301\n-\tsubs\tr3, r5, r3\n+\tstr.w\tr3, [r7, #-60]\n+\tldr\tr3, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr.w\tr3, [r7, #-64]\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r7, #-84]\n+\tldr.w\tr3, [r4, #504]\t@ 0x1f8\n \tldr\tr5, [sp, #76]\t@ 0x4c\n-\tvstr\td11, [r6, #-84]\t@ 0xffffffac\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tstrh.w\tr8, [r6, #-80]\n+\tsubs\tr3, r2, r3\n+\tldr\tr6, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tstrh.w\tr8, [r7, #-72]\n \tmul.w\tr5, r3, r5\n-\tldr.w\tr3, [r4, #496]\t@ 0x1f0\n-\tsubs\tr3, r1, r3\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tmla\tr5, r1, r3, r5\n+\tldr.w\tr3, [r4, #492]\t@ 0x1ec\n+\tmov\tr2, r5\n+\tldr\tr5, [sp, #64]\t@ 0x40\n+\tsubs\tr3, r5, r3\n+\tmla\tr2, r6, r3, r2\n \tldr\tr3, [sp, #48]\t@ 0x30\n-\tadd.w\tr5, r3, r5, lsl #3\n-\tldr.w\tr3, [r4, #488]\t@ 0x1e8\n-\tadd.w\tr1, ip, r3\n-\tstr.w\tr1, [r6, #-64]\n-\tvst1.32\t{d16}, [r2]\n-\tstrd\tr5, r7, [r6, #-96]\t@ 0x60\n+\tadd.w\tr5, r3, r2, lsl #3\n+\tldr.w\tr3, [r4, #484]\t@ 0x1e4\n+\tstr.w\tr5, [r7, #-88]\n+\tadd\tr1, r3\n+\tstr.w\tr1, [r7, #-56]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tmovs\tr3, #8\n-\tstr.w\tr3, [r6, #-48]\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r6, #-28]\n-\tadd.w\tr3, r4, #540\t@ 0x21c\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tmov\tr7, r0\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #-40]\n+\tldr.w\tr3, [r4, #564]\t@ 0x234\n+\tmov\tr6, r0\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r4, #572]\t@ 0x23c\n-\tldr.w\tr0, [r4, #520]\t@ 0x208\n \tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r4, #560]\t@ 0x230\n-\tvstr\td11, [r6, #-44]\t@ 0xffffffd4\n+\tldr.w\tr2, [r4, #552]\t@ 0x228\n+\tldr.w\tr0, [r4, #512]\t@ 0x200\n \tsubs\tr2, r1, r2\n-\tldr.w\tr1, [r4, #568]\t@ 0x238\n-\tstrh.w\tr8, [r6, #-40]\n+\tldr.w\tr1, [r4, #560]\t@ 0x230\n+\tstr\tr7, [sp, #84]\t@ 0x54\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r4, #556]\t@ 0x22c\n+\tldr.w\tr1, [r4, #548]\t@ 0x224\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r4, #548]\t@ 0x224\n-\tvmov.32\tr1, d16[1]\n+\tldr.w\tr2, [r4, #540]\t@ 0x21c\n+\tldr.w\tr1, [r4, #544]\t@ 0x220\n \trsb\tr2, r2, #1\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tldr.w\tr0, [r4, #552]\t@ 0x228\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r6, #-24]\n-\tsub.w\tr2, r6, #36\t@ 0x24\n-\tnegs\tr1, r1\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tvst1.32\t{d16}, [r2]\n-\tstrd\tr3, r1, [r6, #-56]\t@ 0x38\n+\tadd.w\tr0, r0, r3, lsl #3\n+\tldr.w\tr3, [r4, #536]\t@ 0x218\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r4, #532]\t@ 0x214\n+\tstr.w\tr1, [r7, #-32]\n+\tmovs\tr1, #0\n+\tstr.w\tr2, [r7, #-20]\n+\tmovs\tr2, #8\n+\tstr.w\tr1, [r7, #-36]\n+\tstr.w\tr0, [r7, #-52]\n+\tstr.w\tr2, [r7, #-44]\n+\tmovs\tr2, #1\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tstrd\tr3, r2, [r7, #-28]\n+\tnegs\tr3, r3\n+\tstrh.w\tr8, [r7, #-36]\n+\tstr.w\tr3, [r7, #-48]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n \tmov\tr4, r0\n-\tldr\tr0, [pc, #256]\t@ (35d4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5bc>)\n-\tmov\tr3, r7\n+\tldr\tr0, [pc, #252]\t@ (35a4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5cc>)\n+\tmov\tr3, r6\n \tadd\tr0, pc\n \taddw\tr2, r0, #2136\t@ 0x858\n \tadd.w\tr1, r0, #2128\t@ 0x850\n \taddw\tr0, r0, #2116\t@ 0x844\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tr5, r7\n-\tbeq.n\t34f2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x4da>\n-\tmov\tr0, r7\n+\tcmp\tr5, r6\n+\tbeq.n\t34c4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x4ec>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r6, #-56]\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr.w\tr3, [r3, #-52]\n \tcmp\tr3, r4\n-\tbeq.n\t3508 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x4f0>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n+\tbeq.n\t34dc <__gridxc_vdwxc_MOD_vdw_set_kcut+0x504>\n+\tldr\tr0, [sp, #88]\t@ 0x58\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #204]\t@ (35d8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5c0>)\n+\tldr\tr3, [pc, #200]\t@ (35a8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5d0>)\n \tadd\tr3, pc\n-\tadd.w\tr2, r3, #540\t@ 0x21c\n-\tldr.w\tr1, [r3, #568]\t@ 0x238\n-\tldr.w\tr0, [r3, #524]\t@ 0x20c\n-\tvld1.32\t{d7}, [r2]\n-\tldrd\tr5, r8, [r3, #548]\t@ 0x224\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tldr.w\tr2, [r3, #556]\t@ 0x22c\n-\tvmov.32\tr7, d7[1]\n-\tldr.w\tlr, [r3, #520]\t@ 0x208\n-\tvmov\tip, s14\n+\tldr.w\tr2, [r3, #548]\t@ 0x224\n+\tldr.w\tfp, [r3, #560]\t@ 0x230\n+\tldr.w\tr9, [r3, #516]\t@ 0x204\n+\tldrd\tr4, r7, [r3, #540]\t@ 0x21c\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tldr.w\tr6, [r3, #512]\t@ 0x200\n+\tldrd\tr5, r0, [r3, #532]\t@ 0x214\n+\tcmp\tr4, r7\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tcmp\tr5, r8\n-\tstr\tr2, [sp, #40]\t@ 0x28\n-\tstr\tr0, [sp, #52]\t@ 0x34\n \tmul.w\tsl, r3, r2\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tmul.w\tr9, r3, r1\n-\tadd.w\tr3, sl, r0\n-\tadd.w\tr4, r3, r9\n-\tbgt.w\t3e2e <__gridxc_vdwxc_MOD_vdw_set_kcut+0xe16>\n-\tmla\tr3, r7, r5, r4\n-\tadd.w\tr0, r8, #1\n-\tmul.w\tr2, r7, ip\n-\tvldr\td17, [pc, #104]\t@ 35c8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5b0>\n-\tsubs\tr0, r0, r5\n-\tmovs\tr1, #0\n-\tmla\tr3, ip, r3, lr\n-\tvldr\td16, [r3]\n-\tadds\tr1, #1\n-\tcmp\tr0, r1\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n-\tadd\tr3, r2\n-\tbne.n\t3568 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x550>\n-\tldr\tr3, [pc, #92]\t@ (35dc <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5c4>)\n+\tadd.w\tr2, sl, r9\n+\tmul.w\tr8, r3, fp\n+\tadd\tr2, r8\n+\tbgt.w\t3e20 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xe48>\n+\tmla\tr3, r0, r4, r2\n+\tadd.w\tlr, r7, #1\n+\tmul.w\tr1, r5, r0\n+\tvldr\td6, [pc, #120]\t@ 3598 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5c0>\n+\tsub.w\tlr, lr, r4\n+\tmov.w\tip, #0\n+\tmla\tr3, r5, r3, r6\n+\tvldr\td7, [r3]\n+\tadd.w\tip, ip, #1\n+\tcmp\tlr, ip\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tadd\tr3, r1\n+\tbne.n\t352e <__gridxc_vdwxc_MOD_vdw_set_kcut+0x556>\n+\tldr\tr3, [pc, #100]\t@ (35ac <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5d4>)\n \tadd\tr3, pc\n-\tldr.w\tr0, [r3, #728]\t@ 0x2d8\n-\tcmp.w\tr0, #2048\t@ 0x800\n-\tbgt.n\t35a8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x590>\n-\tmla\tr3, r7, r0, r4\n-\tmov\tr1, r0\n-\tmovw\tr4, #2049\t@ 0x801\n-\tmla\tr3, ip, r3, lr\n-\tadds\tr1, #1\n-\tvstr\td13, [r3]\n-\tcmp\tr1, r4\n-\tadd\tr3, r2\n-\tbne.n\t3598 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x580>\n-\tcmp\tr0, #0\n-\tble.n\t3648 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x630>\n-\tldr\tr3, [sp, #52]\t@ 0x34\n-\tmovs\tr1, #1\n-\tldr\tr4, [pc, #48]\t@ (35e0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5c8>)\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tadd\tr9, r3\n-\tadd.w\tr3, r9, sl\n-\tadd\tr4, pc\n-\tadd\tr3, r7\n-\tmla\tr3, ip, r3, lr\n-\tb.n\t35f4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5dc>\n-\tnop\n+\tldr.w\tip, [r3, #712]\t@ 0x2c8\n+\tcmp.w\tip, #2048\t@ 0x800\n+\tbgt.n\t3572 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x59a>\n+\tmla\tr3, ip, r0, r2\n+\tmov\tr2, ip\n+\tmovw\tlr, #2049\t@ 0x801\n+\tmla\tr3, r5, r3, r6\n+\tadds\tr2, #1\n+\tvstr\td15, [r3]\n+\tcmp\tr2, lr\n+\tadd\tr3, r1\n+\tbne.n\t3560 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x588>\n+\tcmp.w\tip, #0\n+\tble.n\t3618 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x640>\n+\tadd\tr8, r9\n+\tldr.w\tlr, [pc, #56]\t@ 35b0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5d8>\n+\tadd.w\tr3, r8, sl\n+\tmovs\tr2, #1\n+\tadd\tr3, r0\n+\tadd\tlr, pc\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tmla\tr3, r5, r3, r6\n+\tb.n\t35c4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5ec>\n \tnop.w\n+\t...\n \t.word\t0xdff344ac\n \t.word\t0x402f7fcc\n-\t.word\t0x000001cc\n+\t.word\t0x000001d2\n R_ARM_REL32\t.bss\n-\t.word\t0x000000fa\n+\t.word\t0x000000f8\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000ca\n+\t.word\t0x000000c6\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n+\t.word\t0x00000062\n R_ARM_REL32\t.bss\n-\t.word\t0x00000024\n+\t.word\t0x0000002c\n R_ARM_REL32\t.bss\n-\tvmov.i64\td18, #0x0000000000000000\n-\tadds\tr1, #1\n-\tvstr\td18, [r3]\n-\tcmp\tr0, r1\n-\tadd\tr3, r2\n-\tblt.n\t3648 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x630>\n-\tvldr\td16, [r4, #720]\t@ 0x2d0\n-\tvmov\ts13, r1\n-\tvldr\td18, [r3]\n-\tvcvt.f64.s32\td17, s13\n-\tvmul.f64\td16, d10, d16\n-\tvmul.f64\td16, d16, d17\n-\tvcmpe.f64\td16, #0.0\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t35e8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5d0>\n-\tvcmpe.f64\td16, d19\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\t35e4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5cc>\n-\tvmul.f64\td16, d16, d16\n-\tvmov.f64\td17, d19\n-\tadds\tr1, #1\n-\tcmp\tr0, r1\n-\tvmul.f64\td16, d16, d16\n-\tvfms.f64\td17, d16, d16\n-\tvmul.f64\td16, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3]\n-\tadd\tr3, r2\n-\tbge.n\t35f4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5dc>\n-\trsb\tr3, r5, #1\n-\tldr.w\tr5, [pc, #1216]\t@ 3b10 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xaf8>\n-\tadd\tr3, r8\n-\tstr.w\tr3, [r6, #-64]\n-\tadd\tr5, pc\n+\tvldr\td5, [pc, #888]\t@ 3930 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x958>\n+\tadds\tr2, #1\n+\tvstr\td5, [r3]\n+\tcmp\tip, r2\n+\tadd\tr3, r1\n+\tblt.n\t3618 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x640>\n+\tvldr\td7, [lr, #704]\t@ 0x2c0\n+\tvmov\ts13, r2\n+\tvldr\td5, [r3]\n+\tvcvt.f64.s32\td6, s13\n+\tvmul.f64\td7, d14, d7\n+\tvmul.f64\td7, d7, d6\n+\tvcmpe.f64\td7, #0.0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbls.n\t35b8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5e0>\n+\tvcmpe.f64\td7, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbge.n\t35b4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5dc>\n+\tvmul.f64\td7, d7, d7\n+\tvmov.f64\td6, d4\n+\tadds\tr2, #1\n+\tcmp\tip, r2\n+\tvmul.f64\td7, d7, d7\n+\tvmls.f64\td6, d7, d7\n+\tvmul.f64\td7, d6, d6\n+\tvmul.f64\td7, d7, d7\n+\tvmul.f64\td5, d5, d7\n+\tvstr\td5, [r3]\n+\tadd\tr3, r1\n+\tbge.n\t35c4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x5ec>\n+\trsb\tr3, r4, #1\n+\tldr\tr4, [pc, #800]\t@ (3940 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x968>)\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tadd\tr3, r7\n+\tadd\tr4, pc\n+\tmovs\tr1, #0\n+\tmov\tr7, r2\n+\tmovw\tr8, #769\t@ 0x301\n+\tstr.w\tr1, [r2, #-72]\n+\tstr.w\tr5, [r2, #-68]\n+\tstr.w\tr1, [r2, #-76]\n+\tstr.w\tr3, [r2, #-56]\n \tmovs\tr3, #8\n-\tstr.w\tr3, [r6, #-88]\n+\tstrh.w\tr8, [r2, #-72]\n+\tstr.w\tr3, [r2, #-80]\n \tmovs\tr3, #1\n-\tstr.w\tr3, [r6, #-68]\n-\tsub.w\tr3, r6, #76\t@ 0x4c\n+\tstrd\tr0, r3, [r2, #-64]\t@ 0x40\n+\tnegs\tr0, r0\n+\tldr.w\tr3, [r4, #564]\t@ 0x234\n+\tstr.w\tr0, [r2, #-84]\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tmovw\tr8, #769\t@ 0x301\n-\tvstr\td11, [r6, #-84]\t@ 0xffffffac\n-\tnegs\tr7, r7\n-\tstrh.w\tr8, [r6, #-80]\n-\tvst1.32\t{d7}, [r3]\n-\tldr.w\tr3, [r5, #572]\t@ 0x23c\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tsubs\tr4, r2, r3\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tldr\tr0, [sp, #40]\t@ 0x28\n-\tstr.w\tr7, [r6, #-92]\n-\tmul.w\tr4, r3, r4\n-\tldr.w\tr3, [r5, #560]\t@ 0x230\n+\tsubs\tr5, r2, r3\n+\tldr.w\tr3, [r4, #552]\t@ 0x228\n+\tldr\tr2, [sp, #44]\t@ 0x2c\n \tsubs\tr3, r1, r3\n-\tmla\tr4, r0, r3, r4\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tadd.w\tr4, lr, r4, lsl #3\n-\tstr.w\tr4, [r6, #-96]\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tmul.w\tr5, fp, r5\n+\tmla\tr5, r2, r3, r5\n+\tadd.w\tr5, r6, r5, lsl #3\n+\tstr.w\tr5, [r7, #-88]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tmovs\tr3, #8\n-\tstr.w\tr3, [r6, #-48]\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r6, #-28]\n-\tadd.w\tr3, r5, #476\t@ 0x1dc\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tmov\tr7, r0\n+\tmovs\tr3, #0\n+\tstr.w\tr3, [r7, #-40]\n+\tldr.w\tr3, [r4, #504]\t@ 0x1f8\n+\tmov\tr6, r0\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r5, #508]\t@ 0x1fc\n-\tldr.w\tr0, [r5, #456]\t@ 0x1c8\n \tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r5, #496]\t@ 0x1f0\n-\tvstr\td11, [r6, #-44]\t@ 0xffffffd4\n+\tldr.w\tr2, [r4, #492]\t@ 0x1ec\n+\tldr.w\tr0, [r4, #452]\t@ 0x1c4\n \tsubs\tr2, r1, r2\n-\tldr.w\tr1, [r5, #504]\t@ 0x1f8\n-\tstrh.w\tr8, [r6, #-40]\n+\tldr.w\tr1, [r4, #500]\t@ 0x1f4\n+\tstr\tr7, [sp, #84]\t@ 0x54\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r5, #492]\t@ 0x1ec\n+\tldr.w\tr1, [r4, #488]\t@ 0x1e8\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr2, [r5, #484]\t@ 0x1e4\n-\tvmov.32\tr1, d16[1]\n+\tldr.w\tr2, [r4, #480]\t@ 0x1e0\n+\tldr.w\tr1, [r4, #484]\t@ 0x1e4\n \trsb\tr2, r2, #1\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tldr.w\tr0, [r5, #488]\t@ 0x1e8\n-\tadd\tr2, r0\n-\tstr.w\tr2, [r6, #-24]\n-\tsub.w\tr2, r6, #36\t@ 0x24\n-\tnegs\tr1, r1\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tvst1.32\t{d16}, [r2]\n-\tstrd\tr3, r1, [r6, #-56]\t@ 0x38\n+\tadd.w\tr0, r0, r3, lsl #3\n+\tldr.w\tr3, [r4, #476]\t@ 0x1dc\n+\tadd\tr2, r1\n+\tldr.w\tr1, [r4, #472]\t@ 0x1d8\n+\tstr.w\tr1, [r7, #-32]\n+\tmovs\tr1, #0\n+\tstr.w\tr2, [r7, #-20]\n+\tmovs\tr2, #8\n+\tstr.w\tr1, [r7, #-36]\n+\tstr.w\tr0, [r7, #-52]\n+\tstr.w\tr2, [r7, #-44]\n+\tmovs\tr2, #1\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tstrd\tr3, r2, [r7, #-28]\n+\tnegs\tr3, r3\n+\tstrh.w\tr8, [r7, #-36]\n+\tstr.w\tr3, [r7, #-48]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n-\tmov\tr5, r0\n-\tldr\tr0, [pc, #1012]\t@ (3b14 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xafc>)\n-\tldr\tr2, [sp, #140]\t@ 0x8c\n-\tmov\tr3, r7\n+\tmov\tr4, r0\n+\tldr\tr0, [pc, #588]\t@ (3944 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x96c>)\n+\tldr\tr2, [sp, #148]\t@ 0x94\n+\tmov\tr3, r6\n \tadd\tr0, pc\n \tadd.w\tr1, r0, #2128\t@ 0x850\n \taddw\tr0, r0, #2116\t@ 0x844\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tr4, r7\n-\tbeq.n\t373a <__gridxc_vdwxc_MOD_vdw_set_kcut+0x722>\n-\tmov\tr0, r7\n+\tcmp\tr5, r6\n+\tbeq.n\t3712 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x73a>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r6, #-56]\n-\tcmp\tr3, r5\n-\tbeq.n\t3750 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x738>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tmov\tr1, r5\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr.w\tr3, [r3, #-52]\n+\tcmp\tr3, r4\n+\tbeq.n\t372a <__gridxc_vdwxc_MOD_vdw_set_kcut+0x752>\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tmov\tr1, r4\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #964]\t@ (3b18 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb00>)\n+\tldr\tr2, [pc, #540]\t@ (3948 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x970>)\n \tldr\tr1, [sp, #64]\t@ 0x40\n \tadd\tr2, pc\n-\tadd.w\tr3, r2, #476\t@ 0x1dc\n-\tldr.w\tr9, [r2, #492]\t@ 0x1ec\n-\tvld1.32\t{d7}, [r3]\n-\tldr.w\tr3, [r2, #460]\t@ 0x1cc\n-\tldr.w\tr5, [r2, #504]\t@ 0x1f8\n-\tldrd\tr4, lr, [r2, #484]\t@ 0x1e4\n-\tvmov.32\tip, d7[1]\n-\tmla\tr3, r1, r9, r3\n+\tldr.w\tr8, [r2, #488]\t@ 0x1e8\n+\tldr.w\tr3, [r2, #456]\t@ 0x1c8\n+\tldr.w\tr6, [r2, #500]\t@ 0x1f4\n+\tldrd\tr4, ip, [r2, #480]\t@ 0x1e0\n+\tmla\tr3, r1, r8, r3\n \tldr\tr1, [sp, #68]\t@ 0x44\n-\tldr.w\tr7, [r2, #456]\t@ 0x1c8\n-\tcmp\tr4, lr\n-\tmla\tr3, r1, r5, r3\n-\tvmov\tr1, s14\n-\tbgt.n\t37b4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x79c>\n-\tmla\tr3, ip, r4, r3\n-\tadd.w\tr0, lr, #1\n-\tvldr\td17, [pc, #884]\t@ 3b08 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xaf0>\n-\tsubs\tr0, r0, r4\n+\tldr.w\tr7, [r2, #452]\t@ 0x1c4\n+\tcmp\tr4, ip\n+\tldrd\tlr, r5, [r2, #472]\t@ 0x1d8\n+\tmla\tr3, r1, r6, r3\n+\tbgt.n\t3782 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x7aa>\n+\tmla\tr3, r5, r4, r3\n+\tadd.w\tr1, ip, #1\n+\tmul.w\tr0, lr, r5\n+\tvldr\td6, [pc, #468]\t@ 3938 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x960>\n+\tsubs\tr1, r1, r4\n \tmovs\tr2, #0\n-\tmla\tr3, r1, r3, r7\n-\tmul.w\tr1, ip, r1\n-\tvldr\td16, [r3]\n+\tmla\tr3, lr, r3, r7\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tcmp\tr0, r2\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n-\tadd\tr3, r1\n-\tbne.n\t37a0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x788>\n-\tldr\tr1, [sp, #112]\t@ 0x70\n-\tmovs\tr2, #8\n-\tstr.w\tr2, [r6, #-88]\n-\tmovs\tr2, #1\n-\tstr.w\tr2, [r6, #-68]\n+\tcmp\tr1, r2\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tadd\tr3, r0\n+\tbne.n\t376e <__gridxc_vdwxc_MOD_vdw_set_kcut+0x796>\n+\tldr\tr2, [sp, #84]\t@ 0x54\n \trsb\tr3, r4, #1\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tadd\tr3, lr\n-\tldr.w\tr8, [pc, #848]\t@ 3b1c <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb04>\n-\tmovw\tsl, #769\t@ 0x301\n-\tvstr\td13, [r1, #-8]\n-\tadd\tr8, pc\n-\tldr\tr1, [sp, #108]\t@ 0x6c\n-\tvstr\td13, [r2]\n-\tvstr\td13, [r2, #-8]\n-\tsub.w\tr2, r6, #76\t@ 0x4c\n-\tldr\tr4, [sp, #68]\t@ 0x44\n-\tstr.w\tr3, [r6, #-64]\n-\trsb\tr3, ip, #0\n-\tvstr\td11, [r6, #-84]\t@ 0xffffffac\n-\tstrh.w\tsl, [r6, #-80]\n-\tvst1.32\t{d7}, [r2]\n-\tstr.w\tr3, [r6, #-92]\n-\tldr.w\tr3, [r8, #508]\t@ 0x1fc\n-\tldr.w\tr2, [r8, #496]\t@ 0x1f0\n-\tvstr\td13, [r1]\n-\tsubs\tr3, r4, r3\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tsubs\tr2, r1, r2\n-\tmul.w\tr3, r5, r3\n-\tmovs\tr5, #8\n-\tmla\tr3, r9, r2, r3\n-\tadd.w\tr7, r7, r3, lsl #3\n-\tstr.w\tr7, [r6, #-96]\n+\tldr\tr4, [pc, #448]\t@ (394c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x974>)\n+\tadd\tr3, ip\n+\tmovs\tr1, #0\n+\tmovw\tr9, #769\t@ 0x301\n+\tstrd\tr1, r1, [r2, #-76]\t@ 0x4c\n+\tadd\tr4, pc\n+\tldr\tr1, [sp, #120]\t@ 0x78\n+\tstr.w\tr3, [r2, #-56]\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r2, #-80]\n+\tmovs\tr3, #1\n+\tstrd\tr5, r3, [r2, #-64]\t@ 0x40\n+\tnegs\tr5, r5\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tvstr\td15, [r1, #-8]\n+\tvstr\td15, [r1]\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tvstr\td15, [r3, #-8]\n+\tvstr\td15, [r3]\n+\tldr.w\tr3, [r4, #504]\t@ 0x1f8\n+\tstr.w\tr5, [r2, #-84]\n+\tsubs\tr5, r1, r3\n+\tldr.w\tr3, [r4, #492]\t@ 0x1ec\n+\tstr.w\tlr, [r2, #-68]\n+\tstrh.w\tr9, [r2, #-72]\n+\tmul.w\tr5, r6, r5\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tsubs\tr3, r6, r3\n+\tmov\tr6, r2\n+\tmla\tr5, r8, r3, r5\n+\tadd.w\tr5, r7, r5, lsl #3\n+\tstr.w\tr5, [r2, #-88]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, r8, #604\t@ 0x25c\n+\tldr\tr1, [sp, #68]\t@ 0x44\n+\tldr.w\tr3, [r4, #624]\t@ 0x270\n+\tmovs\tr7, #0\n+\tldr.w\tr2, [r4, #612]\t@ 0x264\n+\tsubs\tr3, r1, r3\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\tldr.w\tr2, [r8, #624]\t@ 0x270\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r8, #636]\t@ 0x27c\n+\tstr\tr6, [sp, #84]\t@ 0x54\n \tsubs\tr2, r1, r2\n-\tldr.w\tr1, [r8, #632]\t@ 0x278\n-\tsubs\tr3, r4, r3\n-\tstr.w\tr5, [r6, #-48]\n-\tmovs\tr5, #1\n-\tstr.w\tr5, [r6, #-28]\n-\tmov\tr5, r0\n-\tvmov.32\tr0, d16[1]\n+\tldr.w\tr1, [r4, #620]\t@ 0x26c\n+\tstr.w\tr7, [r6, #-40]\n+\tmov\tr7, r0\n+\tldr.w\tr6, [r4, #600]\t@ 0x258\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r8, #620]\t@ 0x26c\n-\tsub.w\tr4, r6, #36\t@ 0x24\n-\tvstr\td11, [r6, #-44]\t@ 0xffffffd4\n-\tstrh.w\tsl, [r6, #-40]\n+\tldr.w\tr1, [r4, #608]\t@ 0x260\n+\trsb\tr6, r6, #1\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr1, [r8, #584]\t@ 0x248\n-\tldr.w\tr2, [r8, #612]\t@ 0x264\n-\tnegs\tr0, r0\n-\tadd.w\tr3, r1, r3, lsl #3\n-\tldr.w\tr1, [r8, #616]\t@ 0x268\n-\trsb\tr2, r2, #1\n-\tadd\tr2, r1\n-\tstr.w\tr2, [r6, #-24]\n-\tvst1.32\t{d16}, [r4]\n-\tstrd\tr3, r0, [r6, #-56]\t@ 0x38\n-\tldr\tr0, [sp, #84]\t@ 0x54\n+\tldr.w\tr2, [r4, #572]\t@ 0x23c\n+\tldr.w\tr1, [r4, #604]\t@ 0x25c\n+\tadd.w\tip, r2, r3, lsl #3\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tldr.w\tr3, [r4, #596]\t@ 0x254\n+\tadd\tr6, r1\n+\tsub.w\tr0, r2, #40\t@ 0x28\n+\tldr.w\tr1, [r4, #592]\t@ 0x250\n+\tstr.w\tr1, [r2, #-32]\n+\tmovs\tr1, #0\n+\tstr\tr1, [r0, #4]\n+\tmovs\tr1, #8\n+\tstr.w\tr6, [r2, #-20]\n+\tstr.w\tip, [r2, #-52]\n+\tstr.w\tr1, [r2, #-44]\n+\tmovs\tr1, #1\n+\tstrh.w\tr9, [r2, #-36]\n+\tstrd\tr3, r1, [r2, #-28]\n+\tnegs\tr3, r3\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tstr.w\tr3, [r2, #-48]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [pc, #648]\t@ (3b20 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb08>)\n-\tldr\tr1, [sp, #136]\t@ 0x88\n-\tmov\tr4, r0\n+\tldr\tr2, [pc, #224]\t@ (3950 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x978>)\n+\tldr\tr3, [sp, #104]\t@ 0x68\n+\tmov\tr6, r0\n \tadd\tr2, pc\n-\tstr\tr1, [sp, #0]\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tadd.w\tr0, r8, #712\t@ 0x2c8\n+\tstr\tr3, [sp, #0]\n+\tadd.w\tr0, r4, #696\t@ 0x2b8\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n \tadd.w\tr2, r2, #2144\t@ 0x860\n-\tmov\tr1, r5\n-\tstr\tr4, [sp, #4]\n+\tmov\tr1, r7\n+\tstr\tr6, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n-\tcmp\tr7, r5\n-\tbeq.n\t38bc <__gridxc_vdwxc_MOD_vdw_set_kcut+0x8a4>\n-\tmov\tr0, r5\n+\tcmp\tr5, r7\n+\tbeq.n\t3892 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x8ba>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r6, #-56]\n-\tcmp\tr3, r4\n-\tbeq.n\t38d2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x8ba>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n-\tmov\tr1, r4\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr.w\tr3, [r3, #-52]\n+\tcmp\tr3, r6\n+\tbeq.n\t38aa <__gridxc_vdwxc_MOD_vdw_set_kcut+0x8d2>\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tmov\tr1, r6\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tmov\tr0, r4\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr8, [pc, #592]\t@ 3b24 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb0c>\n-\tmovs\tr3, #8\n-\tstr.w\tr3, [r6, #-88]\n-\tmovs\tr3, #1\n-\tadd\tr8, pc\n-\tstr.w\tr3, [r6, #-68]\n-\tadd.w\tr3, r8, #540\t@ 0x21c\n-\tldr\tr5, [sp, #64]\t@ 0x40\n-\tsub.w\tr4, r6, #76\t@ 0x4c\n-\tvstr\td11, [r6, #-84]\t@ 0xffffffac\n-\tldr.w\tr1, [r8, #572]\t@ 0x23c\n-\tmovw\tr9, #769\t@ 0x301\n-\tvld1.32\t{d16}, [r3]\n+\tldr\tr7, [pc, #168]\t@ (3954 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x97c>)\n+\tmovs\tr3, #0\n+\tldr\tr5, [sp, #84]\t@ 0x54\n+\tmov.w\tip, #0\n+\tadd\tr7, pc\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tsub.w\tr1, r5, #76\t@ 0x4c\n+\tmovw\tr8, #769\t@ 0x301\n+\tstr.w\tr3, [r5, #-76]\n+\tldr.w\tr4, [r7, #564]\t@ 0x234\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr2, [r8, #568]\t@ 0x238\n-\tsubs\tr1, r3, r1\n-\tldr.w\tr3, [r8, #560]\t@ 0x230\n-\tldr.w\tr7, [r8, #520]\t@ 0x208\n-\tsubs\tr3, r5, r3\n-\tstrh.w\tr9, [r6, #-80]\n-\tmul.w\tr1, r2, r1\n-\tldr.w\tr2, [r8, #556]\t@ 0x22c\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tmla\tr1, r2, r3, r1\n-\tvmov.32\tr2, d16[1]\n-\tldr.w\tr3, [r8, #548]\t@ 0x224\n-\tadd.w\tr7, r7, r1, lsl #3\n-\tldr.w\tr1, [r8, #552]\t@ 0x228\n+\tldr.w\tr2, [r7, #560]\t@ 0x230\n+\tsubs\tr4, r3, r4\n+\tldr.w\tr3, [r7, #552]\t@ 0x228\n+\tldr.w\tr5, [r7, #548]\t@ 0x224\n+\tsubs\tr3, r6, r3\n+\tldr.w\tr6, [r7, #512]\t@ 0x200\n+\tmul.w\tr2, r4, r2\n+\tldr.w\tr4, [r7, #536]\t@ 0x218\n+\tldr\tr0, [sp, #92]\t@ 0x5c\n+\tmla\tr2, r5, r3, r2\n+\tldr.w\tr3, [r7, #540]\t@ 0x21c\n+\tldr\tr5, [sp, #84]\t@ 0x54\n \trsb\tr3, r3, #1\n-\tadd\tr3, r1\n-\tnegs\tr2, r2\n-\tstr.w\tr3, [r6, #-64]\n-\tvst1.32\t{d16}, [r4]\n-\tmovs\tr4, #8\n-\tstrd\tr7, r2, [r6, #-96]\t@ 0x60\n+\tadd.w\tr6, r6, r2, lsl #3\n+\tldr.w\tr2, [r7, #544]\t@ 0x220\n+\tadd\tr3, r2\n+\tldr.w\tr2, [r7, #532]\t@ 0x214\n+\tstr.w\tr2, [r5, #-68]\n+\tstr.w\tip, [r1, #4]\n+\tmovs\tr1, #8\n+\tstr.w\tr3, [r5, #-56]\n+\tstr.w\tr1, [r5, #-80]\n+\tmovs\tr1, #1\n+\tstrh.w\tr8, [r5, #-72]\n+\tstrd\tr4, r1, [r5, #-64]\t@ 0x40\n+\tnegs\tr4, r4\n+\tstrd\tr6, r4, [r5, #-88]\t@ 0x58\n+\tmov\tr4, r5\n+\tb.n\t3958 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x980>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x71d77959\n+\t.word\t0x3fb0411e\n+\t.word\t0x0000031a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000246\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000216\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001b2\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000da\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000009c\n+ R_ARM_REL32\t.bss\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, r8, #668\t@ 0x29c\n+\tldr.w\tr3, [r7, #684]\t@ 0x2ac\n \tldr\tr2, [sp, #68]\t@ 0x44\n+\tmovs\tr1, #0\n+\tstr.w\tr1, [r5, #-40]\n \tmov\tr5, r0\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tsub.w\tr0, r6, #36\t@ 0x24\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r8, #700]\t@ 0x2bc\n-\tstr.w\tr4, [r6, #-48]\n-\tmovs\tr4, #1\n+\tsubs\tr1, r2, r3\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr.w\tr3, [r7, #672]\t@ 0x2a0\n+\tldr.w\tip, [r7, #656]\t@ 0x290\n \tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r8, #688]\t@ 0x2b0\n-\tstr.w\tr4, [r6, #-28]\n-\tsubs\tr2, r1, r2\n-\tldr.w\tr1, [r8, #696]\t@ 0x2b8\n-\tvstr\td11, [r6, #-44]\t@ 0xffffffd4\n-\tstrh.w\tr9, [r6, #-40]\n-\tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r8, #684]\t@ 0x2ac\n-\tmla\tr1, r1, r2, r3\n-\tvmov.32\tr3, d16[1]\n-\tldr.w\tr2, [r8, #648]\t@ 0x288\n+\tldr.w\tr2, [r7, #680]\t@ 0x2a8\n+\tldr\tr0, [sp, #88]\t@ 0x58\n+\tmul.w\tr1, r2, r1\n+\tldr.w\tr2, [r7, #668]\t@ 0x29c\n+\tmla\tr1, r2, r3, r1\n+\tldr.w\tr2, [r7, #632]\t@ 0x278\n+\tldr.w\tr3, [r7, #660]\t@ 0x294\n \tadd.w\tr2, r2, r1, lsl #3\n-\tldr.w\tr1, [r8, #728]\t@ 0x2d8\n-\tnegs\tr4, r3\n-\tldr.w\tr3, [r8, #676]\t@ 0x2a4\n-\tadds\tr1, #1\n-\tstr.w\tr1, [r6, #-164]\n-\tldr.w\tr1, [r8, #680]\t@ 0x2a8\n+\tldr.w\tr1, [r7, #712]\t@ 0x2c8\n \trsb\tr3, r3, #1\n+\tstr.w\tr2, [r4, #-52]\n+\tadds\tr1, #1\n+\tstr.w\tr1, [r4, #-156]\n+\tldr.w\tr1, [r7, #664]\t@ 0x298\n+\tmovs\tr2, #8\n+\tstr.w\tr2, [r4, #-44]\n+\tmovs\tr2, #1\n \tadd\tr3, r1\n-\tstr.w\tr3, [r6, #-24]\n-\tvst1.32\t{d16}, [r0]\n-\tstrd\tr2, r4, [r6, #-56]\t@ 0x38\n-\tldr\tr0, [sp, #84]\t@ 0x54\n+\tstr.w\tr3, [r4, #-20]\n+\tmov\tr3, r4\n+\tldr.w\tr1, [r7, #652]\t@ 0x28c\n+\tstrd\tip, r2, [r4, #-28]\n+\tstr.w\tr1, [r4, #-32]\n+\tmovs\tr1, #0\n+\tstr.w\tr1, [r4, #-36]\n+\tstrh.w\tr8, [r4, #-36]\n+\trsb\tr4, ip, #0\n+\tstr.w\tr4, [r3, #-48]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr3, [sp, #132]\t@ 0x84\n+\tldr\tr3, [sp, #120]\t@ 0x78\n \tmov\tr4, r0\n \tstr\tr3, [sp, #0]\n-\tldr\tr2, [sp, #128]\t@ 0x80\n-\tadd.w\tr0, r8, #720\t@ 0x2d0\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n+\tadd.w\tr0, r7, #704\t@ 0x2c0\n \tmov\tr1, r5\n+\tldrd\tr2, r3, [sp, #132]\t@ 0x84\n \tstr\tr4, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n-\tcmp\tr7, r5\n-\tbeq.n\t39e4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x9cc>\n+\tcmp\tr6, r5\n+\tbeq.n\t39fe <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa26>\n \tmov\tr0, r5\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r6, #-56]\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tldr.w\tr3, [r3, #-52]\n \tcmp\tr3, r4\n-\tbeq.n\t39fa <__gridxc_vdwxc_MOD_vdw_set_kcut+0x9e2>\n-\tldr\tr0, [sp, #84]\t@ 0x54\n+\tbeq.n\t3a16 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa3e>\n+\tldr\tr0, [sp, #88]\t@ 0x58\n \tmov\tr1, r4\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr5, [pc, #300]\t@ (3b28 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb10>)\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tadd\tr5, pc\n+\tldr.w\tr5, [pc, #1160]\t@ 3ea0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec8>\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr7, [r5, #460]\t@ 0x1cc\n-\tldr.w\tip, [r5, #492]\t@ 0x1ec\n-\tldr.w\tlr, [r5, #504]\t@ 0x1f8\n-\tldrd\tr2, r1, [r5, #484]\t@ 0x1e4\n-\tmla\tr4, r4, ip, r7\n-\tldr.w\tr8, [r5, #456]\t@ 0x1c8\n-\tmla\tr7, r3, ip, r7\n-\tldr.w\tr0, [r5, #480]\t@ 0x1e0\n-\tmla\tr4, r3, lr, r4\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr5, pc\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tldr.w\tr7, [r5, #488]\t@ 0x1e8\n+\tldr.w\tr6, [r5, #456]\t@ 0x1c8\n+\tldr.w\tip, [r5, #500]\t@ 0x1f4\n+\tldrd\tr2, r1, [r5, #480]\t@ 0x1e0\n+\tmla\tr4, r4, r7, r6\n+\tldr.w\tlr, [r5, #452]\t@ 0x1c4\n+\tmla\tr6, r3, r7, r6\n+\tldr\tr7, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [r5, #476]\t@ 0x1dc\n+\tmla\tr4, r3, ip, r4\n \tcmp\tr2, r1\n-\tmla\tr7, r3, lr, r7\n-\tbgt.n\t3a66 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa4e>\n+\tmla\tr6, r7, ip, r6\n+\tbgt.n\t3a84 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xaac>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #476]\t@ 0x1dc\n+\tldr.w\tr5, [r5, #472]\t@ 0x1d8\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr4, r2\n-\tadd\tr2, r7\n+\tadd\tr2, r6\n \tmul.w\tr0, r5, r0\n \tmul.w\tr4, r5, r4\n \tmul.w\tr2, r5, r2\n-\tadd.w\tr3, r8, r4\n+\tadd.w\tr3, lr, r4\n \tsubs\tr5, r2, r4\n \tmovs\tr2, #0\n \tadds\tr4, r5, r3\n \tadds\tr2, #1\n-\tldrd\tr8, r9, [r3]\n+\tldrd\tr6, r7, [r3]\n \tcmp\tr1, r2\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r4]\n-\tbne.n\t3a54 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa3c>\n-\tldr\tr5, [pc, #196]\t@ (3b2c <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb14>)\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tadd\tr5, pc\n+\tstrd\tr6, r7, [r4]\n+\tbne.n\t3a72 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa9a>\n+\tldr.w\tr5, [pc, #1052]\t@ 3ea4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xecc>\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr7, [r5, #524]\t@ 0x20c\n-\tldr.w\tip, [r5, #556]\t@ 0x22c\n-\tldr.w\tlr, [r5, #568]\t@ 0x238\n-\tldrd\tr2, r1, [r5, #548]\t@ 0x224\n-\tmla\tr4, r4, ip, r7\n-\tldr.w\tr8, [r5, #520]\t@ 0x208\n-\tmla\tr7, r3, ip, r7\n-\tldr.w\tr0, [r5, #544]\t@ 0x220\n-\tmla\tr4, r3, lr, r4\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr5, pc\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tldr.w\tr7, [r5, #548]\t@ 0x224\n+\tldr.w\tr6, [r5, #516]\t@ 0x204\n+\tldr.w\tip, [r5, #560]\t@ 0x230\n+\tldrd\tr2, r1, [r5, #540]\t@ 0x21c\n+\tmla\tr4, r4, r7, r6\n+\tldr.w\tlr, [r5, #512]\t@ 0x200\n+\tmla\tr6, r3, r7, r6\n+\tldr\tr7, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [r5, #536]\t@ 0x218\n+\tmla\tr4, r3, ip, r4\n \tcmp\tr2, r1\n-\tmla\tr7, r3, lr, r7\n-\tbgt.n\t3ad2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xaba>\n+\tmla\tr6, r7, ip, r6\n+\tbgt.n\t3af2 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb1a>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #540]\t@ 0x21c\n+\tldr.w\tr5, [r5, #532]\t@ 0x214\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr4, r2\n-\tadd\tr2, r7\n+\tadd\tr2, r6\n \tmul.w\tr0, r5, r0\n \tmul.w\tr4, r5, r4\n \tmul.w\tr2, r5, r2\n-\tadd.w\tr3, r8, r4\n+\tadd.w\tr3, lr, r4\n \tsubs\tr5, r2, r4\n \tmovs\tr2, #0\n-\tadds\tr4, r5, r3\n+\tadds\tr4, r3, r5\n \tadds\tr2, #1\n-\tldrd\tr8, r9, [r3]\n-\tcmp\tr1, r2\n+\tldrd\tr6, r7, [r3]\n+\tcmp\tr2, r1\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r4]\n-\tbne.n\t3ac0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xaa8>\n-\tldr\tr5, [pc, #92]\t@ (3b30 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb18>)\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tadd\tr5, pc\n+\tstrd\tr6, r7, [r4]\n+\tbne.n\t3ae0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb08>\n+\tldr\tr5, [pc, #948]\t@ (3ea8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xed0>)\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr7, [r5, #588]\t@ 0x24c\n+\tadd\tr5, pc\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tldr.w\tr7, [r5, #608]\t@ 0x260\n+\tldr.w\tr6, [r5, #576]\t@ 0x240\n \tldr.w\tip, [r5, #620]\t@ 0x26c\n-\tldr.w\tlr, [r5, #632]\t@ 0x278\n-\tldrd\tr2, r1, [r5, #612]\t@ 0x264\n-\tmla\tr4, r4, ip, r7\n-\tldr.w\tr8, [r5, #584]\t@ 0x248\n-\tmla\tr7, r3, ip, r7\n-\tldr.w\tr0, [r5, #608]\t@ 0x260\n-\tmla\tr4, r3, lr, r4\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tldrd\tr2, r1, [r5, #600]\t@ 0x258\n+\tmla\tr4, r4, r7, r6\n+\tldr.w\tlr, [r5, #572]\t@ 0x23c\n+\tmla\tr6, r3, r7, r6\n+\tldr\tr7, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [r5, #596]\t@ 0x254\n+\tmla\tr4, r3, ip, r4\n \tcmp\tr2, r1\n-\tb.n\t3b34 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb1c>\n-\tnop.w\n-\t.word\t0x71d77959\n-\t.word\t0x3fb0411e\n-\t.word\t0x000004b6\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003ee\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000003c0\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000342\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000280\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000242\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000126\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000be\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000056\n- R_ARM_REL32\t.bss\n-\tmla\tr7, r3, lr, r7\n-\tbgt.n\t3b70 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb58>\n+\tmla\tr6, r7, ip, r6\n+\tbgt.n\t3b5e <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb86>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #604]\t@ 0x25c\n+\tldr.w\tr5, [r5, #592]\t@ 0x250\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr4, r2\n-\tadd\tr2, r7\n+\tadd\tr2, r6\n \tmul.w\tr0, r5, r0\n \tmul.w\tr4, r5, r4\n \tmul.w\tr2, r5, r2\n-\tadd.w\tr3, r8, r4\n+\tadd.w\tr3, lr, r4\n \tsubs\tr5, r2, r4\n \tmovs\tr2, #0\n-\tadds\tr4, r3, r5\n+\tadds\tr4, r5, r3\n \tadds\tr2, #1\n-\tldrd\tr8, r9, [r3]\n+\tldrd\tr6, r7, [r3]\n \tcmp\tr2, r1\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r4]\n-\tbne.n\t3b5e <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb46>\n-\tldr\tr5, [pc, #860]\t@ (3ed0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xeb8>)\n-\tldr\tr4, [sp, #64]\t@ 0x40\n-\tadd\tr5, pc\n+\tstrd\tr6, r7, [r4]\n+\tbne.n\t3b4c <__gridxc_vdwxc_MOD_vdw_set_kcut+0xb74>\n+\tldr\tr5, [pc, #844]\t@ (3eac <__gridxc_vdwxc_MOD_vdw_set_kcut+0xed4>)\n \tldr\tr3, [sp, #68]\t@ 0x44\n-\tldr.w\tr7, [r5, #652]\t@ 0x28c\n-\tldr.w\tip, [r5, #684]\t@ 0x2ac\n-\tldr.w\tlr, [r5, #696]\t@ 0x2b8\n-\tldrd\tr2, r1, [r5, #676]\t@ 0x2a4\n-\tmla\tr4, r4, ip, r7\n-\tldr.w\tr8, [r5, #648]\t@ 0x288\n-\tmla\tr7, r3, ip, r7\n-\tldr.w\tr0, [r5, #672]\t@ 0x2a0\n-\tmla\tr4, r3, lr, r4\n-\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd\tr5, pc\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tldr.w\tr7, [r5, #668]\t@ 0x29c\n+\tldr.w\tr6, [r5, #636]\t@ 0x27c\n+\tldr.w\tip, [r5, #680]\t@ 0x2a8\n+\tldrd\tr2, r1, [r5, #660]\t@ 0x294\n+\tmla\tr4, r4, r7, r6\n+\tldr.w\tlr, [r5, #632]\t@ 0x278\n+\tmla\tr6, r3, r7, r6\n+\tldr\tr7, [sp, #64]\t@ 0x40\n+\tldr.w\tr0, [r5, #656]\t@ 0x290\n+\tmla\tr4, r3, ip, r4\n \tcmp\tr2, r1\n-\tmla\tr7, r3, lr, r7\n-\tbgt.n\t3bdc <__gridxc_vdwxc_MOD_vdw_set_kcut+0xbc4>\n+\tmla\tr6, r7, ip, r6\n+\tbgt.n\t3bca <__gridxc_vdwxc_MOD_vdw_set_kcut+0xbf2>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #668]\t@ 0x29c\n+\tldr.w\tr5, [r5, #652]\t@ 0x28c\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr4, r2\n-\tadd\tr2, r7\n+\tadd\tr2, r6\n \tmul.w\tr0, r5, r0\n \tmul.w\tr4, r5, r4\n \tmul.w\tr2, r5, r2\n-\tadd.w\tr3, r8, r4\n+\tadd.w\tr3, lr, r4\n \tsubs\tr5, r2, r4\n \tmovs\tr2, #0\n \tadds\tr4, r5, r3\n \tadds\tr2, #1\n-\tldrd\tr8, r9, [r3]\n-\tcmp\tr1, r2\n+\tldrd\tr6, r7, [r3]\n+\tcmp\tr2, r1\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r4]\n-\tbne.n\t3bca <__gridxc_vdwxc_MOD_vdw_set_kcut+0xbb2>\n+\tstrd\tr6, r7, [r4]\n+\tbne.n\t3bb8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xbe0>\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #148]\t@ 0x94\n+\tldr\tr2, [sp, #156]\t@ 0x9c\n \tadds\tr3, #1\n \tstr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, r2\n-\tbne.w\t3224 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x20c>\n-\tmov\tr9, fp\n+\tbne.w\t31e6 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x20e>\n \tcmp\tr3, #31\n \tstr\tr3, [sp, #68]\t@ 0x44\n-\tbne.w\t3206 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x1ee>\n-\tldr\tr3, [pc, #732]\t@ (3ed4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xebc>)\n+\tbne.w\t31d0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x1f8>\n+\tldr\tr3, [pc, #716]\t@ (3eb0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xed8>)\n \tmovs\tr2, #1\n+\tvldr\td7, [sp, #96]\t@ 0x60\n \tadd\tr3, pc\n-\tstr.w\tr2, [r3, #732]\t@ 0x2dc\n-\tvstr\td12, [r3, #440]\t@ 0x1b8\n-\tldr\tr2, [pc, #724]\t@ (3ed8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec0>)\n+\tstr.w\tr2, [r3, #716]\t@ 0x2cc\n+\tvstr\td7, [r3, #440]\t@ 0x1b8\n+\tldr\tr2, [pc, #704]\t@ (3eb4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xedc>)\n \tadd.w\tr1, sp, #16640\t@ 0x4100\n-\tldr\tr3, [pc, #720]\t@ (3edc <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec4>)\n+\tldr\tr3, [pc, #700]\t@ (3eb8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xee0>)\n \tadds\tr1, #60\t@ 0x3c\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t3eb8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xea0>\n+\tbne.w\t3e9a <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec2>\n \tadd.w\tsp, sp, #16640\t@ 0x4100\n \tadd\tsp, #68\t@ 0x44\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr2, [pc, #688]\t@ (3ee0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec8>)\n-\tldr\tr3, [pc, #684]\t@ (3edc <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec4>)\n+\tldr\tr2, [pc, #668]\t@ (3ebc <__gridxc_vdwxc_MOD_vdw_set_kcut+0xee4>)\n+\tldr\tr3, [pc, #664]\t@ (3eb8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xee0>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t3eb8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xea0>\n+\tbne.w\t3e9a <__gridxc_vdwxc_MOD_vdw_set_kcut+0xec2>\n \tmov\tr0, r4\n \tadd.w\tsp, sp, #16640\t@ 0x4100\n \tadd\tsp, #68\t@ 0x44\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut>\n R_ARM_THM_JUMP24\t__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n-\tbl\t12e0 <__gridxc_vdwxc_MOD_set_phi_table>\n-\tldr\tr3, [sp, #80]\t@ 0x50\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tldr.w\tr0, [fp, #492]\t@ 0x1ec\n-\tldr.w\tr4, [fp, #460]\t@ 0x1cc\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [fp, #504]\t@ 0x1f8\n+\tbl\t1388 <__gridxc_vdwxc_MOD_set_phi_table>\n+\tldr.w\tr2, [r7, #472]\t@ 0x1d8\n+\tstr\tr2, [sp, #44]\t@ 0x2c\n+\tldr.w\tr2, [r7, #452]\t@ 0x1c4\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tldr.w\tr2, [r7, #476]\t@ 0x1dc\n+\tldr.w\tr3, [r7, #500]\t@ 0x1f4\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tldr.w\tr1, [r7, #488]\t@ 0x1e8\n \tstr\tr3, [sp, #76]\t@ 0x4c\n-\tldr.w\tr2, [fp, #456]\t@ 0x1c8\n-\tstr\tr4, [sp, #52]\t@ 0x34\n-\tmul.w\tr1, r3, r1\n+\tldr.w\tfp, [r7, #456]\t@ 0x1c8\n+\tmul.w\tr2, r3, r2\n \tldr\tr3, [sp, #64]\t@ 0x40\n-\tstr\tr2, [sp, #48]\t@ 0x30\n-\tvmov.32\tr2, d16[1]\n-\tadds\tr4, r1, r4\n-\tstr\tr0, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tmul.w\tsl, r0, r3\n+\tstr\tr1, [sp, #72]\t@ 0x48\n+\tadd.w\tr4, r2, fp\n+\tmul.w\tsl, r1, r3\n \tadd\tr4, sl\n-\tb.w\t32d0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x2b8>\n-\tvmov.f64\td0, d14\n-\tstrd\tr1, r2, [sp, #56]\t@ 0x38\n-\tbl\t800 <__gridxc_vdwxc_MOD_iofd.isra.0>\n-\tvmov.f64\td0, d15\n-\tmov\tr6, r0\n-\tbl\t800 <__gridxc_vdwxc_MOD_iofd.isra.0>\n-\tldr.w\tip, [pc, #568]\t@ 3ee4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xecc>\n-\tmovs\tr3, #20\n-\tmvn.w\tr2, #322\t@ 0x142\n-\tmvn.w\tr1, #334\t@ 0x14e\n-\tadd\tip, pc\n+\tb.w\t328a <__gridxc_vdwxc_MOD_vdw_set_kcut+0x2b2>\n+\tvmov.f64\td0, d11\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tbl\t868 <__gridxc_vdwxc_MOD_iofd.isra.0>\n+\tvmov.f64\td0, d10\n+\tstr\tr0, [sp, #56]\t@ 0x38\n+\tbl\t868 <__gridxc_vdwxc_MOD_iofd.isra.0>\n+\tldr\tr2, [sp, #80]\t@ 0x50\n \tadds\tr5, #1\n-\tadd.w\tlr, ip, r0, lsl #3\n-\tmla\tr3, r3, r0, r6\n-\tadd.w\tr0, ip, r6, lsl #3\n-\tvldr\td17, [lr, #-8]\n-\tlsls\tr6, r3, #4\n-\tvldr\td16, [lr]\n-\tadd.w\tip, r6, r2\n-\tmvn.w\tlr, #332\t@ 0x14c\n-\tsub.w\tr3, r6, #334\t@ 0x14e\n-\tvsub.f64\td15, d15, d17\n-\tmvn.w\tr2, #320\t@ 0x140\n-\tvsub.f64\td16, d16, d17\n-\tvldr\td17, [r0, #-8]\n-\tvsub.f64\td14, d14, d17\n-\tvdiv.f64\td19, d15, d16\n-\tvldr\td16, [r0]\n-\tldr\tr0, [pc, #492]\t@ (3ee8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xed0>)\n-\tvsub.f64\td16, d16, d17\n-\tadd\tr0, pc\n-\tadd.w\tip, r0, ip, lsl #3\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvdiv.f64\td22, d14, d16\n-\tvldr\td16, [ip]\n-\tadd.w\tip, r6, r1\n-\tvldr\td24, [r3]\n-\tsub.w\tr3, r6, #326\t@ 0x146\n-\tmvn.w\tr1, #328\t@ 0x148\n-\tadd.w\tip, r0, ip, lsl #3\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvldr\td25, [ip]\n-\tsub.w\tip, r6, #330\t@ 0x14a\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvldr\td18, [ip]\n-\tmvn.w\tip, #330\t@ 0x14a\n-\tadd\tip, r6\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvmul.f64\td20, d19, d19\n-\tvmul.f64\td23, d19, d20\n-\tvmul.f64\td17, d22, d22\n-\tvfma.f64\td25, d23, d16\n-\tvldr\td16, [ip]\n-\tadd.w\tip, r6, lr\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvmul.f64\td21, d22, d17\n-\tvmul.f64\td18, d17, d18\n-\tvfma.f64\td18, d22, d16\n-\tvldr\td27, [ip]\n-\tsub.w\tip, r6, #322\t@ 0x142\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvldr\td26, [ip]\n-\tsub.w\tip, r6, #336\t@ 0x150\n-\tadd.w\tip, r0, ip, lsl #3\n-\tvfma.f64\td24, d23, d26\n-\tvldr\td16, [ip]\n-\tmvn.w\tip, #324\t@ 0x144\n-\tvfma.f64\td16, d21, d27\n-\tvfma.f64\td16, d22, d25\n-\tvfma.f64\td16, d24, d17\n-\tvldr\td24, [r3]\n-\tmvn.w\tr3, #326\t@ 0x146\n-\tadds\tr3, r6, r3\n-\tvmul.f64\td17, d17, d24\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvldr\td24, [r3]\n-\tadds\tr3, r6, r2\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvfma.f64\td17, d22, d24\n-\tvldr\td24, [r3]\n-\tsub.w\tr3, r6, #324\t@ 0x144\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvldr\td22, [r3]\n-\tsub.w\tr3, r6, #332\t@ 0x14c\n-\tvfma.f64\td22, d21, d24\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvfma.f64\td16, d22, d23\n-\tvldr\td22, [r3]\n-\tadds\tr3, r6, r1\n-\tldrd\tr1, r2, [sp, #56]\t@ 0x38\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvadd.f64\td18, d18, d22\n-\tvldr\td22, [r3]\n-\tsub.w\tr3, r6, #328\t@ 0x148\n-\tadd\tr6, ip\n-\tadd.w\tr3, r0, r3, lsl #3\n-\tvfma.f64\td18, d21, d22\n-\tadd.w\tr0, r0, r6, lsl #3\n-\tvfma.f64\td16, d19, d18\n-\tvldr\td19, [r3]\n-\tvldr\td18, [r0]\n-\tmovw\tr3, #2049\t@ 0x801\n-\tcmp\tr5, r3\n-\tvadd.f64\td17, d17, d19\n-\tvfma.f64\td17, d21, d18\n-\tvfma.f64\td16, d17, d20\n-\tvstr\td16, [r7]\n-\tbne.w\t3298 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x280>\n-\tb.w\t3306 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x2ee>\n-\tmul.w\tr2, r7, ip\n-\tb.w\t357c <__gridxc_vdwxc_MOD_vdw_set_kcut+0x564>\n-\tldr\tr3, [pc, #180]\t@ (3eec <__gridxc_vdwxc_MOD_vdw_set_kcut+0xed4>)\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tmovw\tlr, #2049\t@ 0x801\n+\tcmp\tr5, lr\n+\tadd.w\tr1, r2, r3, lsl #3\n+\tvldr\td7, [r1, #-8]\n+\tadd.w\tr1, r2, r0, lsl #3\n+\tvldr\td5, [r1, #-8]\n+\tvsub.f64\td11, d11, d7\n+\tvldr\td6, [r1]\n+\tadd.w\tr1, r2, r3, lsl #3\n+\tmvn.w\tr2, #322\t@ 0x142\n+\tvsub.f64\td10, d10, d5\n+\tvsub.f64\td6, d6, d5\n+\tvdiv.f64\td5, d10, d6\n+\tvldr\td6, [r1]\n+\tmov.w\tr1, #20\n+\tvsub.f64\td6, d6, d7\n+\tmla\tr0, r1, r0, r3\n+\tldr\tr3, [pc, #480]\t@ (3ec0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xee8>)\n+\tadd\tr3, pc\n+\tvdiv.f64\td7, d11, d6\n+\tmov.w\tr1, r0, lsl #4\n+\tadd.w\tip, r1, r2\n+\tmvn.w\tr2, #330\t@ 0x14a\n+\tsub.w\tr0, r1, #334\t@ 0x14e\n+\tadd.w\tip, r3, ip, lsl #3\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvldr\td1, [ip]\n+\tmvn.w\tip, #334\t@ 0x14e\n+\tadd\tip, r1\n+\tvldr\td11, [r0]\n+\tsub.w\tr0, r1, #326\t@ 0x146\n+\tadd.w\tip, r3, ip, lsl #3\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvldr\td12, [ip]\n+\tsub.w\tip, r1, #330\t@ 0x14a\n+\tadd.w\tip, r3, ip, lsl #3\n+\tvldr\td13, [ip]\n+\tadd.w\tip, r1, r2\n+\tmvn.w\tr2, #326\t@ 0x146\n+\tadd.w\tip, r3, ip, lsl #3\n+\tvmul.f64\td2, d5, d5\n+\tvmul.f64\td3, d5, d2\n+\tvmul.f64\td4, d7, d7\n+\tvmla.f64\td12, d3, d1\n+\tvldr\td1, [ip]\n+\tmvn.w\tip, #332\t@ 0x14c\n+\tadd\tip, r1\n+\tvmul.f64\td13, d4, d13\n+\tvmul.f64\td6, d7, d4\n+\tadd.w\tip, r3, ip, lsl #3\n+\tvmla.f64\td13, d7, d1\n+\tvldr\td10, [ip]\n+\tsub.w\tip, r1, #322\t@ 0x142\n+\tadd.w\tip, r3, ip, lsl #3\n+\tvldr\td1, [ip]\n+\tsub.w\tip, r1, #336\t@ 0x150\n+\tadd.w\tip, r3, ip, lsl #3\n+\tvmla.f64\td11, d3, d1\n+\tvldr\td1, [r0]\n+\tadd.w\tr0, r1, r2\n+\tmvn.w\tr2, #324\t@ 0x144\n+\tvldr\td0, [ip]\n+\tmvn.w\tip, #328\t@ 0x148\n+\tvmla.f64\td0, d6, d10\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvmla.f64\td0, d12, d7\n+\tvmla.f64\td0, d11, d4\n+\tvmul.f64\td4, d4, d1\n+\tvldr\td1, [r0]\n+\tmvn.w\tr0, #320\t@ 0x140\n+\tadd\tr0, r1\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvmla.f64\td4, d7, d1\n+\tvldr\td1, [r0]\n+\tsub.w\tr0, r1, #324\t@ 0x144\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvldr\td7, [r0]\n+\tsub.w\tr0, r1, #332\t@ 0x14c\n+\tvmla.f64\td7, d6, d1\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvmla.f64\td0, d7, d3\n+\tvldr\td7, [r0]\n+\tadd.w\tr0, r1, ip\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvadd.f64\td7, d13, d7\n+\tvldr\td3, [r0]\n+\tsub.w\tr0, r1, #328\t@ 0x148\n+\tadd\tr1, r2\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n+\tadd.w\tr0, r3, r0, lsl #3\n+\tvmla.f64\td7, d6, d3\n+\tadd.w\tr3, r3, r1, lsl #3\n+\tvmla.f64\td0, d7, d5\n+\tvldr\td5, [r0]\n+\tvldr\td7, [r3]\n+\tvadd.f64\td4, d4, d5\n+\tvmla.f64\td4, d6, d7\n+\tvmla.f64\td0, d4, d2\n+\tvstr\td0, [r6]\n+\tbne.w\t3250 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x278>\n+\tb.w\t32be <__gridxc_vdwxc_MOD_vdw_set_kcut+0x2e6>\n+\tmul.w\tr1, r5, r0\n+\tb.w\t3544 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x56c>\n+\tldr\tr3, [pc, #152]\t@ (3ec4 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xeec>)\n \tmov\tr1, r4\n \tstr\tr4, [sp, #0]\n \tadd\tr3, pc\n \tadd.w\tr6, r3, #16\n \tadd.w\tr2, r3, #40\t@ 0x28\n \tmov\tr0, r6\n \taddw\tr3, r3, #2120\t@ 0x848\n \tstr\tr2, [sp, #4]\n \tmov\tr2, r4\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n \tadd\tr3, sp, #320\t@ 0x140\n-\tvmov.i32\td18, #0\t@ 0x00000000\n-\tmov\tr0, r6\n-\tmov\tr6, r3\n+\tmov\tr7, r3\n \tstrd\tr4, r4, [sp, #4]\n-\tmov\tr2, r6\n \tstr\tr4, [sp, #0]\n-\tvldr\td16, [pc, #88]\t@ 3ec0 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xea8>\n-\tvldr\td17, [pc, #92]\t@ 3ec8 <__gridxc_vdwxc_MOD_vdw_set_kcut+0xeb0>\n-\tvstr\td18, [r3, #-4]\n-\tmovs\tr1, #8\n-\tstr.w\tr1, [r6, #-8]\n-\tsub.w\tr1, r6, #104\t@ 0x68\n-\tstr\tr1, [sp, #116]\t@ 0x74\n-\tmov\tr7, r1\n-\tmovw\tr1, #769\t@ 0x301\n-\tstrh.w\tr1, [r2], #4\n-\tmov\tr1, r7\n-\tstr\tr3, [sp, #100]\t@ 0x64\n+\tmov\tr0, r6\n+\tstrd\tr4, r4, [r3, #-4]\n+\tsub.w\tr2, r7, #16\n+\tsub.w\tr1, r7, #96\t@ 0x60\n+\tmovs\tr6, #30\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tmov\tr3, r4\n-\tsub.w\tr4, r6, #16\n-\tvst1.32\t{d16-d17}, [r2]\n-\tmov\tr2, r4\n-\tstr\tr4, [sp, #96]\t@ 0x60\n-\tadd.w\tr4, r5, #176\t@ 0xb0\n-\tstr.w\tr4, [r6, #-16]\n-\tmov.w\tr4, #4294967295\t@ 0xffffffff\n-\tstr.w\tr4, [r6, #-12]\n+\tstr\tr6, [r7, #16]\n+\tmovs\tr4, #8\n+\tadd.w\tr6, r5, #176\t@ 0xb0\n+\tstr\tr4, [r7, #4]\n+\tstr.w\tr4, [r7, #-8]\n+\tmovs\tr4, #1\n+\tstr.w\tr6, [r7, #-16]\n+\tmov.w\tr6, #4294967295\t@ 0xffffffff\n+\tstrd\tr4, r4, [r7, #8]\n+\tstr.w\tr6, [r7, #-12]\n+\tmovw\tr6, #769\t@ 0x301\n+\tstrh\tr6, [r7, #0]\n+\tstr\tr2, [sp, #108]\t@ 0x6c\n+\tstr\tr1, [sp, #124]\t@ 0x7c\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r5, #448]\t@ 0x1c0\n-\tb.w\t30b6 <__gridxc_vdwxc_MOD_vdw_set_kcut+0x9e>\n+\tstr.w\tr4, [r5, #448]\t@ 0x1c0\n+\tb.w\t307e <__gridxc_vdwxc_MOD_vdw_set_kcut+0xa6>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000001e\n-\t.word\t0x00000358\n+\tnop\n+\t.word\t0x00000480\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000416\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000003ae\n R_ARM_REL32\t.bss\n-\t.word\t0x000002d8\n+\t.word\t0x00000346\n R_ARM_REL32\t.bss\n-\t.word\t0x000002c8\n+\t.word\t0x000002c4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000002b4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002ac\n+\t.word\t0x00000298\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000228\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001e4\n+\t.word\t0x000001dc\n R_ARM_REL32\t__gridxc_vdwxc_MOD_phi_table\n-\t.word\t0x000000ac\n+\t.word\t0x00000092\n R_ARM_REL32\t.rodata\n \n-00003ef0 <__gridxc_vdwxc_MOD_vdw_set_author>:\n+00003ec8 <__gridxc_vdwxc_MOD_vdw_set_author>:\n __gridxc_vdwxc_MOD_vdw_set_author():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4080]\t@ 0xff0\n-\tldr\tr3, [pc, #224]\t@ (3fe0 <__gridxc_vdwxc_MOD_vdw_set_author+0xf0>)\n+\tldr\tr3, [pc, #224]\t@ (3fb8 <__gridxc_vdwxc_MOD_vdw_set_author+0xf0>)\n \tmov\tr4, r1\n-\tldr\tr6, [pc, #224]\t@ (3fe4 <__gridxc_vdwxc_MOD_vdw_set_author+0xf4>)\n+\tldr\tr6, [pc, #224]\t@ (3fbc <__gridxc_vdwxc_MOD_vdw_set_author+0xf4>)\n \tmov\tr5, r0\n \tmov\tr1, r0\n \tadd\tr3, pc\n \tmovs\tr2, #5\n \tmov\tr0, r4\n \tadd\tr6, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbz\tr0, 3f68 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n-\tldr\tr3, [pc, #208]\t@ (3fe8 <__gridxc_vdwxc_MOD_vdw_set_author+0xf8>)\n+\tcbz\tr0, 3f40 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n+\tldr\tr3, [pc, #208]\t@ (3fc0 <__gridxc_vdwxc_MOD_vdw_set_author+0xf8>)\n \tmovs\tr2, #5\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 3f58 <__gridxc_vdwxc_MOD_vdw_set_author+0x68>\n-\tldr\tr3, [pc, #196]\t@ (3fec <__gridxc_vdwxc_MOD_vdw_set_author+0xfc>)\n+\tcbnz\tr0, 3f30 <__gridxc_vdwxc_MOD_vdw_set_author+0x68>\n+\tldr\tr3, [pc, #196]\t@ (3fc4 <__gridxc_vdwxc_MOD_vdw_set_author+0xfc>)\n \tcmp\tr4, #4\n-\tadd\tr1, pc, #164\t@ (adr r1, 3fd0 <__gridxc_vdwxc_MOD_vdw_set_author+0xe0>)\n+\tadd\tr1, pc, #164\t@ (adr r1, 3fa8 <__gridxc_vdwxc_MOD_vdw_set_author+0xe0>)\n \tldrd\tr0, r1, [r1]\n \tadd\tr3, pc\n \tstrd\tr0, r1, [r3, #16]\n-\tbgt.n\t3f7a <__gridxc_vdwxc_MOD_vdw_set_author+0x8a>\n-\tldr\tr3, [pc, #180]\t@ (3ff0 <__gridxc_vdwxc_MOD_vdw_set_author+0x100>)\n+\tbgt.n\t3f52 <__gridxc_vdwxc_MOD_vdw_set_author+0x8a>\n+\tldr\tr3, [pc, #180]\t@ (3fc8 <__gridxc_vdwxc_MOD_vdw_set_author+0x100>)\n \tmov\tr2, r4\n \tmov\tr1, r5\n \tadd\tr3, pc\n \tadds\tr3, #24\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \trsb\tr2, r4, #5\n \tadd\tr0, r4\n \tmovs\tr1, #32\n \tldmia.w\tsp!, {r4, r5, r6, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemset\n-\tldr\tr3, [pc, #152]\t@ (3ff4 <__gridxc_vdwxc_MOD_vdw_set_author+0x104>)\n+\tldr\tr3, [pc, #152]\t@ (3fcc <__gridxc_vdwxc_MOD_vdw_set_author+0x104>)\n \tmovs\tr2, #3\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcbnz\tr0, 3f88 <__gridxc_vdwxc_MOD_vdw_set_author+0x98>\n-\tldr\tr3, [pc, #140]\t@ (3ff8 <__gridxc_vdwxc_MOD_vdw_set_author+0x108>)\n-\tadd\tr1, pc, #108\t@ (adr r1, 3fd8 <__gridxc_vdwxc_MOD_vdw_set_author+0xe8>)\n+\tcbnz\tr0, 3f60 <__gridxc_vdwxc_MOD_vdw_set_author+0x98>\n+\tldr\tr3, [pc, #140]\t@ (3fd0 <__gridxc_vdwxc_MOD_vdw_set_author+0x108>)\n+\tadd\tr1, pc, #108\t@ (adr r1, 3fb0 <__gridxc_vdwxc_MOD_vdw_set_author+0xe8>)\n \tldrd\tr0, r1, [r1]\n \tadd\tr3, pc\n \tstrd\tr0, r1, [r3, #16]\n \tcmp\tr4, #4\n-\tble.n\t3f38 <__gridxc_vdwxc_MOD_vdw_set_author+0x48>\n-\tldr\tr3, [pc, #128]\t@ (3ffc <__gridxc_vdwxc_MOD_vdw_set_author+0x10c>)\n+\tble.n\t3f10 <__gridxc_vdwxc_MOD_vdw_set_author+0x48>\n+\tldr\tr3, [pc, #128]\t@ (3fd4 <__gridxc_vdwxc_MOD_vdw_set_author+0x10c>)\n \tldr\tr0, [r5, #0]\n \tadd\tr3, pc\n \tldrb\tr2, [r5, #4]\n \tstr\tr0, [r3, #24]\n \tstrb\tr2, [r3, #28]\n \tpop\t{r4, r5, r6, pc}\n-\tldr\tr3, [pc, #116]\t@ (4000 <__gridxc_vdwxc_MOD_vdw_set_author+0x110>)\n+\tldr\tr3, [pc, #116]\t@ (3fd8 <__gridxc_vdwxc_MOD_vdw_set_author+0x110>)\n \tmovs\tr2, #3\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t3f68 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n-\tldr\tr3, [pc, #104]\t@ (4004 <__gridxc_vdwxc_MOD_vdw_set_author+0x114>)\n+\tbeq.n\t3f40 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n+\tldr\tr3, [pc, #104]\t@ (3fdc <__gridxc_vdwxc_MOD_vdw_set_author+0x114>)\n \tmovs\tr2, #2\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t3f68 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n-\tldr\tr3, [pc, #88]\t@ (4008 <__gridxc_vdwxc_MOD_vdw_set_author+0x118>)\n+\tbeq.n\t3f40 <__gridxc_vdwxc_MOD_vdw_set_author+0x78>\n+\tldr\tr3, [pc, #88]\t@ (3fe0 <__gridxc_vdwxc_MOD_vdw_set_author+0x118>)\n \tmovs\tr2, #2\n \tmov\tr1, r5\n \tmov\tr0, r4\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t3f76 <__gridxc_vdwxc_MOD_vdw_set_author+0x86>\n-\tldr\tr3, [pc, #76]\t@ (400c <__gridxc_vdwxc_MOD_vdw_set_author+0x11c>)\n+\tbeq.n\t3f4e <__gridxc_vdwxc_MOD_vdw_set_author+0x86>\n+\tldr\tr3, [pc, #76]\t@ (3fe4 <__gridxc_vdwxc_MOD_vdw_set_author+0x11c>)\n \tmovs\tr1, #39\t@ 0x27\n-\tldr\tr0, [pc, #76]\t@ (4010 <__gridxc_vdwxc_MOD_vdw_set_author+0x120>)\n+\tldr\tr0, [pc, #76]\t@ (3fe8 <__gridxc_vdwxc_MOD_vdw_set_author+0x120>)\n \tadd\tr0, pc\n \tldr\tr3, [r6, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t3f76 <__gridxc_vdwxc_MOD_vdw_set_author+0x86>\n+\tb.n\t3f4e <__gridxc_vdwxc_MOD_vdw_set_author+0x86>\n \tnop\n \t.word\t0xe978d4fe\n \t.word\t0xbffe3126\n \t.word\t0xc3611340\n \t.word\t0xbfeb2bd3\n \t.word\t0x000000d4\n R_ARM_REL32\t.LC31\n@@ -5559,240 +5590,242 @@\n \t.word\t0x00000050\n R_ARM_REL32\t.LC21\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n \t.word\t0x00000048\n R_ARM_REL32\t.LC36\n \n-00004014 <__gridxc_vdwxc_MOD_vdw_phi>:\n+00003fec <__gridxc_vdwxc_MOD_vdw_phi>:\n __gridxc_vdwxc_MOD_vdw_phi():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n+\tvpush\t{d8-d10}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3856]\t@ 0xf10\n-\tmov\tip, r2\n-\tldr\tr2, [pc, #984]\t@ (4400 <__gridxc_vdwxc_MOD_vdw_phi+0x3ec>)\n-\tldr\tr3, [pc, #984]\t@ (4404 <__gridxc_vdwxc_MOD_vdw_phi+0x3f0>)\n+\tstr.w\tr0, [ip, #3832]\t@ 0xef8\n \tsub\tsp, #204\t@ 0xcc\n+\tmov\tip, r2\n+\tldr\tr2, [pc, #984]\t@ (43e0 <__gridxc_vdwxc_MOD_vdw_phi+0x3f4>)\n+\tldr\tr3, [pc, #988]\t@ (43e4 <__gridxc_vdwxc_MOD_vdw_phi+0x3f8>)\n \tadd\tr2, pc\n-\tldr\tr6, [pc, #984]\t@ (4408 <__gridxc_vdwxc_MOD_vdw_phi+0x3f4>)\n-\tmov\tfp, r0\n-\tadd\tr6, pc\n+\tstr\tr0, [sp, #0]\n+\tldr\tr7, [pc, #984]\t@ (43e8 <__gridxc_vdwxc_MOD_vdw_phi+0x3fc>)\n \tldr\tr3, [r2, r3]\n+\tadd\tr7, pc\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #196]\t@ 0xc4\n \tmov.w\tr3, #0\n \tldr\tr3, [r1, #24]\n \tstr\tr3, [sp, #64]\t@ 0x40\n \trsb\tr9, r3, #0\n-\tcbnz\tr3, 4050 <__gridxc_vdwxc_MOD_vdw_phi+0x3c>\n+\tcbnz\tr3, 402c <__gridxc_vdwxc_MOD_vdw_phi+0x40>\n \tmov.w\tr9, #4294967295\t@ 0xffffffff\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #64]\t@ 0x40\n \tldrd\tr3, r4, [r1, #28]\n \tldr.w\tr2, [ip, #24]\n \tsubs\tr4, r4, r3\n \tldr.w\tr8, [r1]\n \tldrd\tr3, r5, [r1, #40]\t@ 0x28\n \tadd.w\tsl, r4, #1\n \tstr\tr2, [sp, #68]\t@ 0x44\n \tsubs\tr5, r5, r3\n \tldr\tr3, [r1, #36]\t@ 0x24\n+\tadd.w\tfp, r5, #1\n \tstr\tr3, [sp, #44]\t@ 0x2c\n-\tadds\tr3, r5, #1\n-\tstr\tr3, [sp, #16]\n \tcmp\tr2, #0\n-\tbeq.n\t4146 <__gridxc_vdwxc_MOD_vdw_phi+0x132>\n+\tbeq.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x13e>\n \tnegs\tr3, r2\n-\tstr\tr3, [sp, #0]\n-\tldr.w\tr7, [ip]\n+\tstr\tr3, [sp, #20]\n+\tldr.w\tr6, [ip]\n \tmovs\tr2, #2\n-\tldr\tr1, [pc, #904]\t@ (440c <__gridxc_vdwxc_MOD_vdw_phi+0x3f8>)\n+\tstr\tr6, [sp, #32]\n \tmovs\tr0, #5\n-\tstr\tr7, [sp, #32]\n-\tldr.w\tr7, [ip, #32]\n+\tldr.w\tr6, [ip, #32]\n+\tldr\tr1, [pc, #900]\t@ (43ec <__gridxc_vdwxc_MOD_vdw_phi+0x400>)\n+\tstr\tr6, [sp, #4]\n+\tldr\tr3, [pc, #900]\t@ (43f0 <__gridxc_vdwxc_MOD_vdw_phi+0x404>)\n \tadd\tr1, pc\n-\tldr\tr3, [pc, #896]\t@ (4410 <__gridxc_vdwxc_MOD_vdw_phi+0x3fc>)\n+\tldr.w\tr6, [ip, #28]\n \tadds\tr1, #24\n-\tstr\tr7, [sp, #4]\n-\tldr.w\tr7, [ip, #28]\n+\tstr\tr6, [sp, #8]\n \tadd\tr3, pc\n-\tstr\tr7, [sp, #8]\n-\tldr.w\tr7, [ip, #36]\t@ 0x24\n-\tstr\tr7, [sp, #48]\t@ 0x30\n-\tldr.w\tr7, [ip, #44]\t@ 0x2c\n-\tstr\tr7, [sp, #12]\n-\tldr.w\tr7, [ip, #40]\t@ 0x28\n+\tldr.w\tr6, [ip, #36]\t@ 0x24\n+\tstr\tr6, [sp, #48]\t@ 0x30\n+\tldr.w\tr6, [ip, #44]\t@ 0x2c\n+\tstr\tr6, [sp, #12]\n+\tldr.w\tr6, [ip, #40]\t@ 0x28\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n+\tmov\tr3, r0\n \tcmp\tr0, #0\n-\tbeq.w\t4380 <__gridxc_vdwxc_MOD_vdw_phi+0x36c>\n-\tldr\tr3, [pc, #860]\t@ (4414 <__gridxc_vdwxc_MOD_vdw_phi+0x400>)\n+\tbeq.w\t4364 <__gridxc_vdwxc_MOD_vdw_phi+0x378>\n+\tldr\tr3, [pc, #864]\t@ (43f4 <__gridxc_vdwxc_MOD_vdw_phi+0x408>)\n \tadd\tr3, pc\n-\tldr.w\tr3, [r3, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r3, #716]\t@ 0x2cc\n \tcmp\tr3, #0\n-\tbeq.w\t4370 <__gridxc_vdwxc_MOD_vdw_phi+0x35c>\n-\tcmp\tr4, #28\n+\tbeq.w\t4354 <__gridxc_vdwxc_MOD_vdw_phi+0x368>\n+\tcmp\tr5, #28\n \tit\tgt\n-\tcmpgt\tr5, #28\n-\tbgt.n\t40d8 <__gridxc_vdwxc_MOD_vdw_phi+0xc4>\n-\tldr\tr3, [pc, #844]\t@ (4418 <__gridxc_vdwxc_MOD_vdw_phi+0x404>)\n+\tcmpgt\tr4, #28\n+\tbgt.n\t40b6 <__gridxc_vdwxc_MOD_vdw_phi+0xca>\n+\tldr\tr3, [pc, #844]\t@ (43f8 <__gridxc_vdwxc_MOD_vdw_phi+0x40c>)\n \tmovs\tr1, #35\t@ 0x23\n-\tldr\tr0, [pc, #844]\t@ (441c <__gridxc_vdwxc_MOD_vdw_phi+0x408>)\n+\tldr\tr0, [pc, #844]\t@ (43fc <__gridxc_vdwxc_MOD_vdw_phi+0x410>)\n \tadd\tr0, pc\n-\tldr\tr3, [r6, r3]\n+\tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #836]\t@ (4420 <__gridxc_vdwxc_MOD_vdw_phi+0x40c>)\n-\tvldr\td21, [fp]\n+\tldr\tr2, [pc, #840]\t@ (4400 <__gridxc_vdwxc_MOD_vdw_phi+0x414>)\n+\tldr\tr3, [sp, #0]\n \tadd\tr2, pc\n-\tvldr\td16, [r2, #440]\t@ 0x1b8\n-\tvcmpe.f64\td21, d16\n+\tvldr\td3, [r3]\n+\tvldr\td7, [r2, #440]\t@ 0x1b8\n+\tvcmpe.f64\td3, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t4152 <__gridxc_vdwxc_MOD_vdw_phi+0x13e>\n-\tadds\tr3, r5, #1\n-\tcmp\tr3, #0\n-\tble.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n+\tblt.n\t4136 <__gridxc_vdwxc_MOD_vdw_phi+0x14a>\n+\tcmp.w\tfp, #0\n+\tble.n\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n \tcmp.w\tsl, #0\n-\tble.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n+\tble.n\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, #1\n-\tbne.w\t4584 <__gridxc_vdwxc_MOD_vdw_phi+0x570>\n+\tbne.w\t457a <__gridxc_vdwxc_MOD_vdw_phi+0x58e>\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tadd.w\tr4, r9, #1\n \tmov.w\tr7, sl, lsl #3\n \tadd.w\tr4, r8, r4, lsl #3\n \tmov.w\tr8, #0\n \tlsls\tr6, r3, #3\n \tmov\tr0, r4\n \tmov\tr2, r7\n \tmovs\tr1, #0\n \tadd\tr4, r6\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tcmp\tr8, r5\n \tadd.w\tr8, r8, #1\n-\tbne.n\t4116 <__gridxc_vdwxc_MOD_vdw_phi+0x102>\n-\tldr\tr2, [pc, #760]\t@ (4424 <__gridxc_vdwxc_MOD_vdw_phi+0x410>)\n-\tldr\tr3, [pc, #724]\t@ (4404 <__gridxc_vdwxc_MOD_vdw_phi+0x3f0>)\n+\tbne.n\t40f6 <__gridxc_vdwxc_MOD_vdw_phi+0x10a>\n+\tldr\tr2, [pc, #760]\t@ (4404 <__gridxc_vdwxc_MOD_vdw_phi+0x418>)\n+\tldr\tr3, [pc, #724]\t@ (43e4 <__gridxc_vdwxc_MOD_vdw_phi+0x3f8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #196]\t@ 0xc4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t45ba <__gridxc_vdwxc_MOD_vdw_phi+0x5a6>\n+\tbne.w\t45b0 <__gridxc_vdwxc_MOD_vdw_phi+0x5c4>\n \tadd\tsp, #204\t@ 0xcc\n+\tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n-\tstr\tr3, [sp, #0]\n+\tstr\tr3, [sp, #20]\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #68]\t@ 0x44\n-\tb.n\t407a <__gridxc_vdwxc_MOD_vdw_phi+0x66>\n-\tvldr\td16, [r2, #720]\t@ 0x2d0\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [pc, #668]\t@ 43f8 <__gridxc_vdwxc_MOD_vdw_phi+0x3e4>\n-\tvmov.f64\td22, #240\t@ 0xbf800000 -1.0\n-\tldr.w\tr0, [r2, #648]\t@ 0x288\n-\tvmov.f64\td28, #8\t@ 0x40400000 3.0\n-\tvdiv.f64\td26, d18, d16\n-\tvmul.f64\td17, d16, d16\n-\tvmul.f64\td20, d16, d19\n-\tstr\tr0, [sp, #56]\t@ 0x38\n-\tldr.w\tr4, [r2, #544]\t@ 0x220\n-\tvmov.f64\td27, d22\n-\tldr.w\tr1, [r2, #672]\t@ 0x2a0\n-\tvmul.f64\td17, d17, d19\n-\tldr.w\tr7, [r2, #524]\t@ 0x20c\n-\tldr.w\tip, [r2, #568]\t@ 0x238\n-\tldr.w\tr6, [r2, #652]\t@ 0x28c\n-\tldr.w\tlr, [r2, #696]\t@ 0x2b8\n-\tadd\tr7, ip\n-\tldr.w\tfp, [r2, #556]\t@ 0x22c\n-\tldr.w\tsl, [r2, #684]\t@ 0x2ac\n-\tadd\tr6, lr\n-\tldr.w\tr3, [r2, #520]\t@ 0x208\n-\tadd\tr7, fp\n-\tadd\tr6, sl\n+\tb.n\t4056 <__gridxc_vdwxc_MOD_vdw_phi+0x6a>\n+\tvldr\td7, [r2, #704]\t@ 0x2c0\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tldr.w\tr1, [r2, #632]\t@ 0x278\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tvmov.f64\td9, d5\n+\tvdiv.f64\td10, d5, d7\n+\tldr.w\tr1, [r2, #636]\t@ 0x27c\n+\tstr\tr1, [sp, #0]\n+\tvldr\td1, [pc, #640]\t@ 43d8 <__gridxc_vdwxc_MOD_vdw_phi+0x3ec>\n+\tldr.w\tr7, [r2, #656]\t@ 0x290\n+\tldr.w\tr4, [r2, #536]\t@ 0x218\n+\tldr.w\tr3, [r2, #512]\t@ 0x200\n+\tldr.w\tr6, [r2, #516]\t@ 0x204\n+\tldr.w\tip, [r2, #560]\t@ 0x230\n+\tldr.w\tfp, [r2, #548]\t@ 0x224\n+\tldr.w\tlr, [r2, #680]\t@ 0x2a8\n+\tldr.w\tsl, [r2, #668]\t@ 0x29c\n \tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr3, [r2, #540]\t@ 0x21c\n-\tldr.w\tr2, [r2, #668]\t@ 0x29c\n-\tvmul.f64\td19, d21, d26\n-\tvcvt.s32.f64\ts15, d19\n-\tvmov\tr5, s15\n-\tadds\tr0, r5, #1\n-\tvmov\ts15, r0\n-\tmul.w\tr0, r5, r4\n-\tvcvt.f64.s32\td19, s15\n-\tmul.w\tr5, r1, r5\n+\tldr.w\tr3, [r2, #532]\t@ 0x214\n+\tldr.w\tr2, [r2, #652]\t@ 0x28c\n+\tvmul.f64\td6, d3, d10\n+\tvcvt.s32.f64\ts13, d6\n+\tvmov\tr1, s13\n+\tadds\tr0, r1, #1\n+\tvmov\ts12, r0\n+\tmul.w\tr5, r1, r7\n+\tvcvt.f64.s32\td6, s12\n+\tmul.w\tr0, r1, r4\n+\tadds\tr1, r7, r5\n+\tstr\tr1, [sp, #4]\n+\tldrd\tr7, r1, [sp, #64]\t@ 0x40\n \tadd\tr4, r0\n-\tstr\tr4, [sp, #4]\n-\tadd\tr1, r5\n-\tstr\tr1, [sp, #8]\n-\tldrd\tr1, r4, [sp, #64]\t@ 0x40\n-\tvfnms.f64\td21, d16, d19\n-\tadd\tr0, r7\n-\tadd\tr5, r6\n-\tcmp\tr4, #1\n+\tvnmls.f64\td3, d6, d7\n+\tvmul.f64\td6, d7, d7\n+\tvmul.f64\td7, d7, d1\n+\tcmp\tr7, #1\n \tit\teq\n \tcmpeq\tr1, #1\n-\tldr\tr4, [sp, #4]\n-\tldr\tr1, [sp, #8]\n-\tadd\tr4, r7\n-\tadd\tr1, r6\n-\tvmul.f64\td21, d21, d26\n-\tvsub.f64\td24, d18, d21\n-\tvmul.f64\td16, d21, d21\n-\tvsub.f64\td23, d21, d18\n-\tvmul.f64\td25, d21, d17\n-\tvmul.f64\td19, d24, d24\n-\tvfma.f64\td27, d16, d28\n-\tvsub.f64\td16, d16, d18\n-\tvfma.f64\td22, d19, d28\n-\tvfma.f64\td23, d24, d19\n-\tvmul.f64\td25, d25, d16\n-\tvmul.f64\td27, d27, d20\n-\tvmul.f64\td22, d22, d20\n-\tvmul.f64\td23, d23, d17\n-\tbne.w\t442c <__gridxc_vdwxc_MOD_vdw_phi+0x418>\n-\tmul.w\tr6, r3, ip\n-\tvneg.f64\td27, d27\n-\tmul.w\tr4, r3, r4\n-\tstr\tr6, [sp, #68]\t@ 0x44\n-\tmul.w\tr0, r3, r0\n-\tstr\tr4, [sp, #16]\n+\tvmul.f64\td6, d6, d1\n+\tvmul.f64\td3, d3, d10\n+\tvsub.f64\td0, d5, d3\n+\tvsub.f64\td1, d3, d5\n+\tvmul.f64\td2, d3, d3\n+\tvmul.f64\td8, d0, d0\n+\tvmla.f64\td1, d0, d8\n+\tvnmls.f64\td9, d8, d4\n+\tvmov.f64\td8, d5\n+\tvnmls.f64\td8, d2, d4\n+\tvsub.f64\td2, d2, d5\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td6, d3, d6\n+\tvmul.f64\td9, d9, d7\n+\tvmul.f64\td2, d6, d2\n+\tvmul.f64\td8, d8, d7\n+\tbne.w\t440c <__gridxc_vdwxc_MOD_vdw_phi+0x420>\n+\tldr\tr1, [sp, #0]\n+\tadd.w\tr7, r6, ip\n+\tadd\tr7, fp\n \tmul.w\tfp, r3, fp\n+\tadds\tr6, r4, r7\n+\tadd\tr1, lr\n+\tadds\tr4, r0, r7\n+\tldr\tr0, [sp, #4]\n+\tadd\tr1, sl\n+\tmul.w\tsl, r2, sl\n+\tadd\tr0, r1\n+\tadd\tr1, r5\n+\tmul.w\tr4, r3, r4\n \tstr.w\tr9, [sp, #4]\n-\tmul.w\tr3, r2, r1\n-\tldr\tr1, [sp, #0]\n+\tmul.w\tr5, r3, ip\n+\tstr\tr4, [sp, #12]\n+\tmul.w\tr4, r2, r1\n+\tldr\tr1, [sp, #20]\n+\tstr\tr5, [sp, #68]\t@ 0x44\n+\tmul.w\tr5, r2, lr\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tmul.w\tr5, r3, r6\n+\tstr\tr1, [sp, #0]\n+\tmul.w\tr3, r2, r0\n+\tadds\tr2, r1, #1\n+\tldr\tr1, [sp, #32]\n \tstr\tr3, [sp, #8]\n \tadd.w\tr3, r9, #1\n-\tmul.w\tr4, r2, r5\n-\tstr\tr0, [sp, #12]\n-\tmul.w\tr6, r2, lr\n-\tmul.w\tsl, r2, sl\n-\tlsls\tr2, r3, #3\n-\tadds\tr3, r1, #1\n-\tldr\tr1, [sp, #32]\n+\tstr\tr5, [sp, #16]\n \tmov\tr7, r4\n-\tadd.w\tr0, r8, r2\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tadd.w\tr3, r1, r3, lsl #3\n-\tstr\tr3, [sp, #20]\n-\tadd.w\tr3, r1, #8\n+\tadd.w\tr2, r1, r2, lsl #3\n+\tstr\tr2, [sp, #20]\n+\tadd.w\tr2, r1, #8\n \tldr\tr1, [sp, #44]\t@ 0x2c\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tadds\tr3, r1, #1\n-\tstr\tr0, [sp, #24]\n-\tmov.w\tr9, r1, lsl #3\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n \tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n-\tadd.w\tr3, r8, #8\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tadds\tr5, r2, r3\n+\tadds\tr2, r1, #1\n+\tadd.w\tr0, r8, r3\n+\tmov.w\tr9, r1, lsl #3\n+\tstr\tr0, [sp, #24]\n+\tlsls\tr2, r2, #3\n+\tstr\tr2, [sp, #60]\t@ 0x3c\n+\tadd.w\tr2, r8, #8\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tadds\tr5, r3, r2\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tmov.w\tr8, r3, lsl #3\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #28]\n \tldr\tr1, [sp, #56]\t@ 0x38\n \tldr\tr3, [sp, #12]\n \tldr\tr0, [sp, #4]\n@@ -5809,38 +5842,38 @@\n \tsub.w\tlr, r2, r3\n \tldr\tr3, [sp, #8]\n \tstr\tr7, [sp, #40]\t@ 0x28\n \tadd.w\tr6, r1, r0, lsl #3\n \tsub.w\tip, r3, r7\n \tldrd\tr0, r1, [sp, #20]\n \tldrd\tr3, r2, [sp, #32]\n-\tadd.w\tr7, ip, r3\n-\tvldr\td18, [r3]\n-\tadd\tr3, sl\n-\tvldr\td20, [r2]\n-\tvldr\td19, [r7]\n \tadd.w\tr7, lr, r2\n-\tvmul.f64\td16, d25, d18\n+\tvldr\td4, [r2]\n \tadd\tr2, fp\n-\tvfma.f64\td16, d21, d20\n-\tvmul.f64\td17, d22, d19\n-\tvfma.f64\td17, d27, d18\n-\tvldr\td18, [r7]\n-\tvfma.f64\td16, d24, d18\n-\tvsub.f64\td18, d18, d20\n-\tvfma.f64\td16, d23, d19\n-\tvfma.f64\td17, d26, d18\n-\tvstmia\tr4!, {d16}\n+\tvldr\td5, [r3]\n+\tvmul.f64\td7, d3, d4\n+\tvmla.f64\td7, d2, d5\n+\tvmul.f64\td6, d8, d5\n+\tvldr\td5, [r7]\n+\tadd.w\tr7, ip, r3\n+\tadd\tr3, sl\n+\tvmla.f64\td7, d0, d5\n+\tvsub.f64\td5, d5, d4\n+\tvldr\td4, [r7]\n+\tvnmls.f64\td6, d9, d4\n+\tvmla.f64\td7, d1, d4\n+\tvmla.f64\td6, d5, d10\n+\tvstmia\tr4!, {d7}\n \tcmp\tr5, r4\n-\tvstmia\tr6!, {d17}\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd\tr1, r9\n-\tvstr\td17, [r0]\n+\tvstmia\tr6!, {d6}\n+\tvstr\td6, [r0]\n \tadd\tr0, r8\n-\tbne.n\t42d6 <__gridxc_vdwxc_MOD_vdw_phi+0x2c2>\n+\tbne.n\t42ba <__gridxc_vdwxc_MOD_vdw_phi+0x2ce>\n \tldr\tr2, [sp, #24]\n \tldr\tr1, [sp, #68]\t@ 0x44\n \tadds\tr2, #8\n \tstr\tr2, [sp, #24]\n \tldr\tr2, [sp, #20]\n \tldr\tr7, [sp, #40]\t@ 0x28\n \tadds\tr2, #8\n@@ -5866,123 +5899,133 @@\n \tldr\tr1, [sp, #48]\t@ 0x30\n \tstr\tr2, [sp, #4]\n \tldr\tr2, [sp, #0]\n \tadd\tr2, r1\n \tstr\tr2, [sp, #0]\n \tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd\tr5, r2\n-\tbne.n\t42a2 <__gridxc_vdwxc_MOD_vdw_phi+0x28e>\n-\tb.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n-\tldr\tr3, [pc, #164]\t@ (4418 <__gridxc_vdwxc_MOD_vdw_phi+0x404>)\n+\tbne.n\t4286 <__gridxc_vdwxc_MOD_vdw_phi+0x29a>\n+\tb.n\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n+\tldr\tr3, [pc, #160]\t@ (43f8 <__gridxc_vdwxc_MOD_vdw_phi+0x40c>)\n \tmovs\tr1, #43\t@ 0x2b\n-\tldr\tr0, [pc, #176]\t@ (4428 <__gridxc_vdwxc_MOD_vdw_phi+0x414>)\n+\tldr\tr0, [pc, #172]\t@ (4408 <__gridxc_vdwxc_MOD_vdw_phi+0x41c>)\n \tadd\tr0, pc\n-\tldr\tr3, [r6, r3]\n+\tldr\tr3, [r7, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t40c2 <__gridxc_vdwxc_MOD_vdw_phi+0xae>\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tvmov.i32\td16, #0\t@ 0x00000000\n-\tldrd\tr3, r2, [sp, #4]\n-\tstr\tr1, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [sp, #16]\n-\tmov\tr0, fp\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tsubs\tr2, r3, r2\n-\tstr\tr1, [sp, #144]\t@ 0x90\n+\tb.n\t40a0 <__gridxc_vdwxc_MOD_vdw_phi+0xb4>\n+\tldrd\tr2, r1, [sp, #4]\n+\tstr\tr3, [sp, #116]\t@ 0x74\n+\tldr\tr5, [sp, #44]\t@ 0x2c\n+\tldr\tr0, [sp, #64]\t@ 0x40\n+\tsubs\tr1, r2, r1\n+\tldr\tr2, [sp, #12]\n+\tsub.w\tr4, r9, r5\n+\tstr\tr0, [sp, #124]\t@ 0x7c\n+\tadds\tr1, #1\n+\tldr\tr0, [sp, #68]\t@ 0x44\n+\tsubs\tr2, r2, r6\n+\tstr\tr5, [sp, #136]\t@ 0x88\n \tadds\tr2, #1\n-\tldr\tr1, [sp, #68]\t@ 0x44\n-\tstr\tr1, [sp, #172]\t@ 0xac\n-\tldr\tr1, [sp, #32]\n \tldr\tr5, [sp, #48]\t@ 0x30\n-\tldr\tr3, [sp, #12]\n-\tstr\tr1, [sp, #148]\t@ 0x94\n-\tsub.w\tr1, r9, r4\n-\tstr\tr1, [sp, #104]\t@ 0x68\n-\tsubs\tr3, r3, r7\n-\tldr\tr1, [sp, #0]\n-\tadds\tr3, #1\n-\tstr\tr4, [sp, #136]\t@ 0x88\n-\tstr\tr2, [sp, #180]\t@ 0xb4\n+\tstr\tr1, [sp, #180]\t@ 0xb4\n+\tldr\tr1, [sp, #20]\n+\tstr\tr0, [sp, #172]\t@ 0xac\n+\tldr\tr0, [sp, #32]\n+\tstr\tr0, [sp, #148]\t@ 0x94\n+\tstr\tr4, [sp, #104]\t@ 0x68\n \tsubs\tr4, r1, r5\n-\tadd\tr2, sp, #148\t@ 0x94\n+\tstr\tr2, [sp, #192]\t@ 0xc0\n \tadd\tr1, sp, #100\t@ 0x64\n-\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tldr\tr0, [sp, #0]\n+\tadd\tr2, sp, #148\t@ 0x94\n+\tstr\tr3, [sp, #164]\t@ 0xa4\n+\tstr\tr3, [sp, #112]\t@ 0x70\n+\tstr\tr3, [sp, #160]\t@ 0xa0\n \tmovs\tr3, #8\n \tstr\tr4, [sp, #152]\t@ 0x98\n \tmovw\tr4, #770\t@ 0x302\n \tstr\tr3, [sp, #120]\t@ 0x78\n \tstr\tr3, [sp, #108]\t@ 0x6c\n \tstr\tr3, [sp, #168]\t@ 0xa8\n \tstr\tr3, [sp, #156]\t@ 0x9c\n \tmovs\tr3, #1\n-\tvstr\td16, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n \tstr.w\tsl, [sp, #132]\t@ 0x84\n+\tstr.w\tfp, [sp, #144]\t@ 0x90\n \tstr.w\tr8, [sp, #100]\t@ 0x64\n \tstr\tr5, [sp, #184]\t@ 0xb8\n \tstrh.w\tr4, [sp, #116]\t@ 0x74\n \tstrh.w\tr4, [sp, #164]\t@ 0xa4\n \tstr\tr3, [sp, #128]\t@ 0x80\n \tstr\tr3, [sp, #140]\t@ 0x8c\n \tstr\tr3, [sp, #176]\t@ 0xb0\n \tstr\tr3, [sp, #188]\t@ 0xbc\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi>\n R_ARM_THM_CALL\t__gridxc_vv_vdwxc_MOD_vv_vdw_phi\n-\tb.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n+\tb.n\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n \tnop\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x000003d0\n+\t.word\t0x000003d4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003d2\n+\t.word\t0x000003d4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x0000037e\n R_ARM_REL32\t.data\n-\t.word\t0x00000376\n+\t.word\t0x00000378\n R_ARM_REL32\t.LC21\n-\t.word\t0x0000035a\n+\t.word\t0x0000035c\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000348\n+\t.word\t0x0000034a\n R_ARM_REL32\t.LC38\n-\t.word\t0x0000033e\n+\t.word\t0x00000342\n R_ARM_REL32\t.bss\n \t.word\t0x000002f2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000000ae\n+\t.word\t0x000000aa\n R_ARM_REL32\t.LC37\n-\tmul.w\tr7, r3, ip\n+\tadd.w\tr1, r6, ip\n+\tldr\tr7, [sp, #0]\n+\tadd\tr1, fp\n+\tmul.w\tfp, r3, fp\n+\tadd\tr4, r1\n+\tadd\tr0, r1\n+\tadd\tr7, lr\n+\tldr\tr1, [sp, #4]\n+\tadd\tr7, sl\n \tstr.w\tr9, [sp, #12]\n+\tadd\tr1, r7\n \tmul.w\tr0, r3, r0\n-\tstr\tr7, [sp, #72]\t@ 0x48\n \tmul.w\tr4, r3, r4\n-\tldr\tr6, [sp, #0]\n-\tmul.w\tfp, r3, fp\n-\tstr\tr0, [sp, #20]\n+\tadd\tr5, r7\n+\tmul.w\tr7, r3, ip\n+\tldr\tr6, [sp, #20]\n \tmul.w\tr3, r2, lr\n-\tmov.w\tip, #2\n+\tstr\tr7, [sp, #72]\t@ 0x48\n \tstr\tr3, [sp, #76]\t@ 0x4c\n \tmul.w\tr3, r2, r1\n \tstr\tr3, [sp, #24]\n \tmul.w\tr3, r2, sl\n \tstr\tr3, [sp, #8]\n \tmul.w\tr7, r2, r5\n \tldr\tr3, [sp, #64]\t@ 0x40\n+\tmov.w\tip, #2\n \tldr\tr2, [sp, #68]\t@ 0x44\n-\tstr\tr6, [sp, #28]\n+\tstr\tr0, [sp, #20]\n \tmov.w\tr9, r3, lsl #3\n-\tstr\tr4, [sp, #16]\n+\tstr\tr6, [sp, #28]\n \tadd.w\tr1, r9, r8\n \tstr\tr1, [sp, #80]\t@ 0x50\n \tldr\tr1, [sp, #12]\n \tmov.w\tsl, r2, lsl #3\n+\tstr\tr4, [sp, #16]\n \tadd.w\tr1, r8, r1, lsl #3\n \tstr\tr1, [sp, #88]\t@ 0x58\n \tldr\tr1, [sp, #32]\n \tstrd\tr3, r2, [sp, #32]\n \tadd.w\tr0, sl, r1\n \tstr\tr0, [sp, #84]\t@ 0x54\n \tadd.w\tr1, r1, r6, lsl #3\n@@ -6016,44 +6059,44 @@\n \tldr\tr1, [sp, #92]\t@ 0x5c\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tsub.w\tlr, r3, r7\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tstr\tr7, [sp, #40]\t@ 0x28\n \tadd.w\tr0, r1, r0, lsl #3\n \tmovs\tr1, #1\n-\tadd.w\tr7, lr, r3\n-\tvldr\td18, [r3]\n-\tvldr\td20, [r2]\n+\tvldr\td7, [r3]\n+\tadd.w\tr7, r8, r2\n+\tvldr\td4, [r2]\n \tadds\tr1, #1\n+\tadd\tr2, fp\n \tcmp\tr1, ip\n-\tvldr\td19, [r7]\n-\tvmul.f64\td16, d18, d25\n+\tvmul.f64\td6, d7, d2\n+\tvldr\td5, [r7]\n+\tvmla.f64\td6, d4, d3\n+\tadd.w\tr7, lr, r3\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td6, d5, d0\n+\tvsub.f64\td5, d5, d4\n+\tvldr\td4, [r7]\n \tldr\tr7, [sp, #8]\n-\tvfma.f64\td16, d20, d21\n+\tvnmls.f64\td7, d4, d9\n+\tvmla.f64\td6, d4, d1\n \tadd\tr3, r7\n-\tadd.w\tr7, r8, r2\n-\tvmul.f64\td17, d19, d22\n-\tadd\tr2, fp\n-\tvfms.f64\td17, d18, d27\n-\tvldr\td18, [r7]\n \tldr\tr7, [sp, #4]\n-\tvfma.f64\td16, d18, d24\n-\tvsub.f64\td18, d18, d20\n-\tvfma.f64\td16, d19, d23\n-\tvfma.f64\td17, d18, d26\n-\tvstr\td16, [r6]\n+\tvmla.f64\td7, d5, d10\n+\tvstr\td6, [r6]\n \tadd\tr6, r9\n-\tvstr\td16, [r4]\n+\tvstr\td6, [r4]\n \tadd\tr4, r7\n \tldr\tr7, [sp, #0]\n-\tvstr\td17, [r5]\n+\tvstr\td7, [r5]\n \tadd\tr5, sl\n-\tvstr\td17, [r0]\n+\tvstr\td7, [r0]\n \tadd\tr0, r7\n-\tbne.n\t44de <__gridxc_vdwxc_MOD_vdw_phi+0x4ca>\n+\tbne.n\t44d4 <__gridxc_vdwxc_MOD_vdw_phi+0x4e8>\n \tldr\tr2, [sp, #72]\t@ 0x48\n \tadd.w\tip, ip, #1\n \tldr\tr3, [sp, #16]\n \tcmp.w\tip, #32\n \tldr\tr7, [sp, #40]\t@ 0x28\n \tadd\tr3, r2\n \tstr\tr3, [sp, #16]\n@@ -6077,160 +6120,159 @@\n \tldr\tr3, [sp, #32]\n \tadd\tr3, r2\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tstr\tr3, [sp, #32]\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr3, r2\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tbne.n\t449c <__gridxc_vdwxc_MOD_vdw_phi+0x488>\n-\tb.n\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n+\tbne.n\t4492 <__gridxc_vdwxc_MOD_vdw_phi+0x4a6>\n+\tb.n\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n \tlsls\tr0, r3, #3\n \tmov\tip, r9\n \tldr.w\tr9, [sp, #44]\t@ 0x2c\n \tadd\tr8, r0\n \tmov.w\tlr, #0\n \tmovs\tr6, #0\n \tmovs\tr7, #0\n \tadd.w\tr1, r8, ip, lsl #3\n \tmovs\tr2, #0\n \tcmp\tr4, r2\n \tstrd\tr6, r7, [r1]\n \tadd.w\tr2, r2, #1\n \tadd\tr1, r0\n-\tbne.n\t459c <__gridxc_vdwxc_MOD_vdw_phi+0x588>\n+\tbne.n\t4592 <__gridxc_vdwxc_MOD_vdw_phi+0x5a6>\n \tadd\tip, r9\n \tadd.w\tr3, lr, #1\n \tcmp\tr5, lr\n-\tbeq.w\t412a <__gridxc_vdwxc_MOD_vdw_phi+0x116>\n+\tbeq.w\t410a <__gridxc_vdwxc_MOD_vdw_phi+0x11e>\n \tmov\tlr, r3\n-\tb.n\t4596 <__gridxc_vdwxc_MOD_vdw_phi+0x582>\n+\tb.n\t458c <__gridxc_vdwxc_MOD_vdw_phi+0x5a0>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \n-000045c0 <__gridxc_vdwxc_MOD_vdw_localxc>:\n+000045b4 <__gridxc_vdwxc_MOD_vdw_localxc>:\n __gridxc_vdwxc_MOD_vdw_localxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3944]\t@ 0xf68\n \tsub\tsp, #108\t@ 0x6c\n \tadd\tr7, sp, #48\t@ 0x30\n \tmov\tr6, r2\n-\tldr.w\tr2, [pc, #1484]\t@ 4ba8 <__gridxc_vdwxc_MOD_vdw_localxc+0x5e8>\n+\tldr.w\tr2, [pc, #1064]\t@ 49f8 <__gridxc_vdwxc_MOD_vdw_localxc+0x444>\n \tmov\tr4, r1\n \tstr\tr3, [r7, #32]\n \tadd\tr2, pc\n \tldr\tr1, [r7, #104]\t@ 0x68\n-\tldr.w\tr3, [pc, #1476]\t@ 4bac <__gridxc_vdwxc_MOD_vdw_localxc+0x5ec>\n+\tldr.w\tr3, [pc, #1056]\t@ 49fc <__gridxc_vdwxc_MOD_vdw_localxc+0x448>\n \tstr\tr1, [r7, #28]\n \tldr\tr1, [r7, #108]\t@ 0x6c\n \tstrd\tr0, r1, [r7, #20]\n \tmov\tr0, sp\n \tldr.w\tsl, [r4]\n \tldr\tr3, [r2, r3]\n \tldrd\tr8, r5, [r7, #112]\t@ 0x70\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #52]\t@ 0x34\n \tmov.w\tr3, #0\n \tbic.w\tr1, sl, sl, asr #31\n \tldrd\tr9, r3, [r7, #120]\t@ 0x78\n \tstr\tr3, [r7, #16]\n-\tldr.w\tr3, [pc, #1436]\t@ 4bb0 <__gridxc_vdwxc_MOD_vdw_localxc+0x5f0>\n+\tldr\tr3, [pc, #1016]\t@ (4a00 <__gridxc_vdwxc_MOD_vdw_localxc+0x44c>)\n \tlsls\tr2, r1, #3\n \tadd\tr3, pc\n \tstr\tr3, [r7, #0]\n \tbic.w\tr3, r2, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tcmp\tr0, r3\n-\tbeq.n\t4638 <__gridxc_vdwxc_MOD_vdw_localxc+0x78>\n+\tbeq.n\t462a <__gridxc_vdwxc_MOD_vdw_localxc+0x76>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t462a <__gridxc_vdwxc_MOD_vdw_localxc+0x6a>\n+\tbne.n\t461c <__gridxc_vdwxc_MOD_vdw_localxc+0x68>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\t48fc <__gridxc_vdwxc_MOD_vdw_localxc+0x33c>\n+\tbne.w\t48e6 <__gridxc_vdwxc_MOD_vdw_localxc+0x332>\n \tadd.w\tr3, sl, sl, lsl #1\n \tadd\tr2, sp, #48\t@ 0x30\n \tstr\tr2, [r7, #36]\t@ 0x24\n \tmov\tr0, sp\n \tbic.w\tr3, r3, r3, asr #31\n \tlsls\tr3, r3, #3\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr0, r2\n-\tbeq.n\t4674 <__gridxc_vdwxc_MOD_vdw_localxc+0xb4>\n+\tbeq.n\t4666 <__gridxc_vdwxc_MOD_vdw_localxc+0xb2>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t4666 <__gridxc_vdwxc_MOD_vdw_localxc+0xa6>\n+\tbne.n\t4658 <__gridxc_vdwxc_MOD_vdw_localxc+0xa4>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t4906 <__gridxc_vdwxc_MOD_vdw_localxc+0x346>\n+\tbne.w\t48f0 <__gridxc_vdwxc_MOD_vdw_localxc+0x33c>\n \tmul.w\tr1, r1, sl\n \tadd\tr3, sp, #48\t@ 0x30\n \tstr\tr3, [r7, #12]\n \tmov\tr0, sp\n \tbic.w\tr1, r1, r1, asr #31\n \tlsls\tr1, r1, #3\n \tmov\tr3, r1\n \tadds\tr1, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr0, r2\n-\tbeq.n\t46b4 <__gridxc_vdwxc_MOD_vdw_localxc+0xf4>\n+\tbeq.n\t46a6 <__gridxc_vdwxc_MOD_vdw_localxc+0xf2>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t46a6 <__gridxc_vdwxc_MOD_vdw_localxc+0xe6>\n+\tbne.n\t4698 <__gridxc_vdwxc_MOD_vdw_localxc+0xe4>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 46c4 <__gridxc_vdwxc_MOD_vdw_localxc+0x104>\n+\tcbz\tr3, 46b6 <__gridxc_vdwxc_MOD_vdw_localxc+0x102>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tbic.w\tr3, r1, #4080\t@ 0xff0\n \tadd\tr2, sp, #48\t@ 0x30\n \tbic.w\tr3, r3, #15\n \tstr\tr2, [r7, #8]\n \tsub.w\tr3, sp, r3\n \tmov\tr2, sp\n \tbic.w\tr1, r1, #7\n \tcmp\tr2, r3\n-\tbeq.n\t46ec <__gridxc_vdwxc_MOD_vdw_localxc+0x12c>\n+\tbeq.n\t46de <__gridxc_vdwxc_MOD_vdw_localxc+0x12a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t46de <__gridxc_vdwxc_MOD_vdw_localxc+0x11e>\n+\tbne.n\t46d0 <__gridxc_vdwxc_MOD_vdw_localxc+0x11c>\n \tubfx\tr3, r1, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 46fc <__gridxc_vdwxc_MOD_vdw_localxc+0x13c>\n+\tcbz\tr3, 46ee <__gridxc_vdwxc_MOD_vdw_localxc+0x13a>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tvmov.i64\td8, #0x0000000000000000\n \tadd\tr3, sp, #48\t@ 0x30\n \tstr\tr3, [r7, #4]\n-\tcmp.w\tsl, #0\n \tldr\tr3, [r7, #28]\n+\tcmp.w\tsl, #0\n+\tvldr\td8, [pc, #756]\t@ 49f0 <__gridxc_vdwxc_MOD_vdw_localxc+0x43c>\n \tvstr\td8, [r3]\n \tldr\tr3, [r7, #24]\n \tvstr\td8, [r3]\n-\tble.n\t4766 <__gridxc_vdwxc_MOD_vdw_localxc+0x1a6>\n+\tble.n\t4758 <__gridxc_vdwxc_MOD_vdw_localxc+0x1a4>\n \tmov.w\tfp, sl, lsl #3\n \tmovs\tr1, #0\n \tmov\tr2, fp\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr2, fp\n@@ -6242,201 +6284,201 @@\n \tmov\tr3, r9\n \tadds\tr2, #1\n \tvstr\td8, [r3]\n \tvstr\td8, [r3, #8]\n \tcmp\tr2, sl\n \tvstr\td8, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t4732 <__gridxc_vdwxc_MOD_vdw_localxc+0x172>\n+\tbne.n\t4724 <__gridxc_vdwxc_MOD_vdw_localxc+0x170>\n \tldr\tr3, [r7, #16]\n \tmovs\tr2, #0\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tadds\tr2, #1\n \tstrd\tr0, r1, [r3]\n \tstrd\tr0, r1, [r3, #8]\n \tcmp\tsl, r2\n \tstrd\tr0, r1, [r3, #16]\n \tadd.w\tr3, r3, #24\n-\tbne.n\t4750 <__gridxc_vdwxc_MOD_vdw_localxc+0x190>\n-\tldr.w\tr3, [pc, #1100]\t@ 4bb4 <__gridxc_vdwxc_MOD_vdw_localxc+0x5f4>\n+\tbne.n\t4742 <__gridxc_vdwxc_MOD_vdw_localxc+0x18e>\n+\tldr\tr3, [pc, #680]\t@ (4a04 <__gridxc_vdwxc_MOD_vdw_localxc+0x450>)\n \tmovw\tr2, #21060\t@ 0x5244\n \tmovt\tr2, #19539\t@ 0x4c53\n \tadd\tr3, pc\n \tadd.w\tr1, r3, #24\n \tldr\tr3, [r3, #24]\n \tcmp\tr3, r2\n-\tbeq.w\t490e <__gridxc_vdwxc_MOD_vdw_localxc+0x34e>\n-\tldr.w\tr3, [pc, #1076]\t@ 4bb8 <__gridxc_vdwxc_MOD_vdw_localxc+0x5f8>\n+\tbeq.w\t48f8 <__gridxc_vdwxc_MOD_vdw_localxc+0x344>\n+\tldr\tr3, [pc, #660]\t@ (4a08 <__gridxc_vdwxc_MOD_vdw_localxc+0x454>)\n \tmovw\tr2, #29284\t@ 0x7264\n \tmovt\tr2, #27763\t@ 0x6c73\n \tadd\tr3, pc\n \tadd.w\tr1, r3, #24\n \tldr\tr3, [r3, #24]\n \tcmp\tr3, r2\n-\tbeq.w\t4986 <__gridxc_vdwxc_MOD_vdw_localxc+0x3c6>\n-\tldr.w\tfp, [pc, #1056]\t@ 4bbc <__gridxc_vdwxc_MOD_vdw_localxc+0x5fc>\n+\tbeq.w\t4970 <__gridxc_vdwxc_MOD_vdw_localxc+0x3bc>\n+\tldr.w\tfp, [pc, #640]\t@ 4a0c <__gridxc_vdwxc_MOD_vdw_localxc+0x458>\n \tmovs\tr2, #3\n-\tldr.w\tr3, [pc, #1052]\t@ 4bc0 <__gridxc_vdwxc_MOD_vdw_localxc+0x600>\n+\tldr\tr3, [pc, #640]\t@ (4a10 <__gridxc_vdwxc_MOD_vdw_localxc+0x45c>)\n \tmovs\tr0, #5\n \tadd\tfp, pc\n \tadd.w\tsl, fp, #24\n \tadd\tr3, pc\n \tmov\tr1, sl\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4916 <__gridxc_vdwxc_MOD_vdw_localxc+0x356>\n-\tldr.w\tr3, [pc, #1032]\t@ 4bc4 <__gridxc_vdwxc_MOD_vdw_localxc+0x604>\n+\tbeq.w\t4900 <__gridxc_vdwxc_MOD_vdw_localxc+0x34c>\n+\tldr\tr3, [pc, #620]\t@ (4a14 <__gridxc_vdwxc_MOD_vdw_localxc+0x460>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4916 <__gridxc_vdwxc_MOD_vdw_localxc+0x356>\n+\tbeq.w\t4900 <__gridxc_vdwxc_MOD_vdw_localxc+0x34c>\n \tldr.w\tr2, [fp, #24]\n \tmovw\tr3, #19788\t@ 0x4d4c\n \tmovt\tr3, #19531\t@ 0x4c4b\n \tcmp\tr2, r3\n-\tbeq.w\t4990 <__gridxc_vdwxc_MOD_vdw_localxc+0x3d0>\n-\tldr\tr3, [pc, #996]\t@ (4bc8 <__gridxc_vdwxc_MOD_vdw_localxc+0x608>)\n+\tbeq.w\t497a <__gridxc_vdwxc_MOD_vdw_localxc+0x3c6>\n+\tldr\tr3, [pc, #584]\t@ (4a18 <__gridxc_vdwxc_MOD_vdw_localxc+0x464>)\n \tmovw\tr2, #28012\t@ 0x6d6c\n \tmovt\tr2, #27755\t@ 0x6c6b\n \tadd\tr3, pc\n \tadd.w\tr1, r3, #24\n \tldr\tr3, [r3, #24]\n \tcmp\tr3, r2\n-\tbeq.w\t49fc <__gridxc_vdwxc_MOD_vdw_localxc+0x43c>\n-\tldr\tr3, [pc, #976]\t@ (4bcc <__gridxc_vdwxc_MOD_vdw_localxc+0x60c>)\n+\tbeq.w\t49e6 <__gridxc_vdwxc_MOD_vdw_localxc+0x432>\n+\tldr\tr3, [pc, #564]\t@ (4a1c <__gridxc_vdwxc_MOD_vdw_localxc+0x468>)\n \tmovs\tr2, #3\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tadd.w\tsl, r3, #24\n-\tldr\tr3, [pc, #968]\t@ (4bd0 <__gridxc_vdwxc_MOD_vdw_localxc+0x610>)\n+\tldr\tr3, [pc, #556]\t@ (4a20 <__gridxc_vdwxc_MOD_vdw_localxc+0x46c>)\n \tmov\tr1, sl\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t499a <__gridxc_vdwxc_MOD_vdw_localxc+0x3da>\n-\tldr\tr3, [pc, #956]\t@ (4bd4 <__gridxc_vdwxc_MOD_vdw_localxc+0x614>)\n+\tbeq.w\t4984 <__gridxc_vdwxc_MOD_vdw_localxc+0x3d0>\n+\tldr\tr3, [pc, #544]\t@ (4a24 <__gridxc_vdwxc_MOD_vdw_localxc+0x470>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t499a <__gridxc_vdwxc_MOD_vdw_localxc+0x3da>\n-\tldr\tr3, [pc, #940]\t@ (4bd8 <__gridxc_vdwxc_MOD_vdw_localxc+0x618>)\n+\tbeq.w\t4984 <__gridxc_vdwxc_MOD_vdw_localxc+0x3d0>\n+\tldr\tr3, [pc, #528]\t@ (4a28 <__gridxc_vdwxc_MOD_vdw_localxc+0x474>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4a06 <__gridxc_vdwxc_MOD_vdw_localxc+0x446>\n-\tldr\tr3, [pc, #924]\t@ (4bdc <__gridxc_vdwxc_MOD_vdw_localxc+0x61c>)\n+\tbeq.w\t4a64 <__gridxc_vdwxc_MOD_vdw_localxc+0x4b0>\n+\tldr\tr3, [pc, #512]\t@ (4a2c <__gridxc_vdwxc_MOD_vdw_localxc+0x478>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4a06 <__gridxc_vdwxc_MOD_vdw_localxc+0x446>\n-\tldr\tr3, [pc, #908]\t@ (4be0 <__gridxc_vdwxc_MOD_vdw_localxc+0x620>)\n+\tbeq.w\t4a64 <__gridxc_vdwxc_MOD_vdw_localxc+0x4b0>\n+\tldr\tr3, [pc, #496]\t@ (4a30 <__gridxc_vdwxc_MOD_vdw_localxc+0x47c>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4b46 <__gridxc_vdwxc_MOD_vdw_localxc+0x586>\n-\tldr\tr3, [pc, #892]\t@ (4be4 <__gridxc_vdwxc_MOD_vdw_localxc+0x624>)\n+\tbeq.w\t4ba4 <__gridxc_vdwxc_MOD_vdw_localxc+0x5f0>\n+\tldr\tr3, [pc, #480]\t@ (4a34 <__gridxc_vdwxc_MOD_vdw_localxc+0x480>)\n \tmovs\tr2, #3\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4b46 <__gridxc_vdwxc_MOD_vdw_localxc+0x586>\n-\tldr\tr3, [pc, #876]\t@ (4be8 <__gridxc_vdwxc_MOD_vdw_localxc+0x628>)\n+\tbeq.w\t4ba4 <__gridxc_vdwxc_MOD_vdw_localxc+0x5f0>\n+\tldr\tr3, [pc, #464]\t@ (4a38 <__gridxc_vdwxc_MOD_vdw_localxc+0x484>)\n \tmovs\tr2, #2\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4ae4 <__gridxc_vdwxc_MOD_vdw_localxc+0x524>\n-\tldr\tr3, [pc, #860]\t@ (4bec <__gridxc_vdwxc_MOD_vdw_localxc+0x62c>)\n+\tbeq.w\t4b42 <__gridxc_vdwxc_MOD_vdw_localxc+0x58e>\n+\tldr\tr3, [pc, #448]\t@ (4a3c <__gridxc_vdwxc_MOD_vdw_localxc+0x488>)\n \tmovs\tr2, #2\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4ae4 <__gridxc_vdwxc_MOD_vdw_localxc+0x524>\n-\tldr\tr3, [pc, #844]\t@ (4bf0 <__gridxc_vdwxc_MOD_vdw_localxc+0x630>)\n+\tbeq.w\t4b42 <__gridxc_vdwxc_MOD_vdw_localxc+0x58e>\n+\tldr\tr3, [pc, #432]\t@ (4a40 <__gridxc_vdwxc_MOD_vdw_localxc+0x48c>)\n \tmovs\tr2, #2\n \tmov\tr1, sl\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4a6c <__gridxc_vdwxc_MOD_vdw_localxc+0x4ac>\n-\tldr\tr3, [pc, #828]\t@ (4bf4 <__gridxc_vdwxc_MOD_vdw_localxc+0x634>)\n+\tbeq.w\t4aca <__gridxc_vdwxc_MOD_vdw_localxc+0x516>\n+\tldr\tr3, [pc, #416]\t@ (4a44 <__gridxc_vdwxc_MOD_vdw_localxc+0x490>)\n \tmov\tr1, sl\n \tmovs\tr2, #2\n \tmovs\tr0, #5\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4a6c <__gridxc_vdwxc_MOD_vdw_localxc+0x4ac>\n-\tldr\tr3, [pc, #812]\t@ (4bf8 <__gridxc_vdwxc_MOD_vdw_localxc+0x638>)\n+\tbeq.w\t4aca <__gridxc_vdwxc_MOD_vdw_localxc+0x516>\n+\tldr\tr3, [pc, #400]\t@ (4a48 <__gridxc_vdwxc_MOD_vdw_localxc+0x494>)\n \tmovs\tr1, #32\n \tldr\tr2, [r7, #0]\n-\tldr\tr0, [pc, #808]\t@ (4bfc <__gridxc_vdwxc_MOD_vdw_localxc+0x63c>)\n+\tldr\tr0, [pc, #400]\t@ (4a4c <__gridxc_vdwxc_MOD_vdw_localxc+0x498>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #804]\t@ (4c00 <__gridxc_vdwxc_MOD_vdw_localxc+0x640>)\n-\tldr\tr3, [pc, #716]\t@ (4bac <__gridxc_vdwxc_MOD_vdw_localxc+0x5ec>)\n+\tldr\tr2, [pc, #392]\t@ (4a50 <__gridxc_vdwxc_MOD_vdw_localxc+0x49c>)\n+\tldr\tr3, [pc, #308]\t@ (49fc <__gridxc_vdwxc_MOD_vdw_localxc+0x448>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #52]\t@ 0x34\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4a68 <__gridxc_vdwxc_MOD_vdw_localxc+0x4a8>\n+\tbne.w\t4ac6 <__gridxc_vdwxc_MOD_vdw_localxc+0x512>\n \tadds\tr7, #60\t@ 0x3c\n \tmov\tsp, r7\n \tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n-\tb.n\t4646 <__gridxc_vdwxc_MOD_vdw_localxc+0x86>\n+\tb.n\t4638 <__gridxc_vdwxc_MOD_vdw_localxc+0x84>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t4682 <__gridxc_vdwxc_MOD_vdw_localxc+0xc2>\n+\tb.n\t4674 <__gridxc_vdwxc_MOD_vdw_localxc+0xc0>\n \tldrb\tr3, [r1, #4]\n \tcmp\tr3, #76\t@ 0x4c\n-\tbne.w\t4780 <__gridxc_vdwxc_MOD_vdw_localxc+0x1c0>\n+\tbne.w\t4770 <__gridxc_vdwxc_MOD_vdw_localxc+0x1bc>\n \tldr\tr3, [r7, #12]\n \tmov\tr2, r4\n \tstrd\tr9, r3, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6448,46 +6490,46 @@\n \tstr\tr3, [sp, #16]\n \tmovs\tr3, #6\n \tstr.w\tr8, [sp, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #692]\t@ (4c04 <__gridxc_vdwxc_MOD_vdw_localxc+0x644>)\n+\tldr\tr0, [pc, #284]\t@ (4a54 <__gridxc_vdwxc_MOD_vdw_localxc+0x4a0>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr2, [r7, #8]\n \tstr\tr2, [sp, #20]\n \tmov\tr1, sl\n \tldr\tr2, [r7, #4]\n \tstrd\tr5, r2, [sp, #12]\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #672]\t@ (4c08 <__gridxc_vdwxc_MOD_vdw_localxc+0x648>)\n+\tldr\tr0, [pc, #264]\t@ (4a58 <__gridxc_vdwxc_MOD_vdw_localxc+0x4a4>)\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tstr\tr3, [sp, #8]\n \tadd\tr0, pc\n \tmov\tr3, r6\n \tstrd\tr8, r8, [sp, #28]\n \tstr.w\tr8, [sp, #24]\n \tldr\tr4, [r7, #24]\n \tstrd\tr9, r4, [sp]\n \tmovs\tr4, #4\n \tstr\tr4, [sp, #36]\t@ 0x24\n \tbl\t0 <__gridxc_lda_MOD_ldaxc>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_ldaxc\n-\tb.n\t48da <__gridxc_vdwxc_MOD_vdw_localxc+0x31a>\n+\tb.n\t48c4 <__gridxc_vdwxc_MOD_vdw_localxc+0x310>\n \tldrb\tr3, [r1, #4]\n \tcmp\tr3, #108\t@ 0x6c\n-\tbne.w\t479a <__gridxc_vdwxc_MOD_vdw_localxc+0x1da>\n-\tb.n\t4916 <__gridxc_vdwxc_MOD_vdw_localxc+0x356>\n+\tbne.w\t4788 <__gridxc_vdwxc_MOD_vdw_localxc+0x1d4>\n+\tb.n\t4900 <__gridxc_vdwxc_MOD_vdw_localxc+0x34c>\n \tldrb.w\tr3, [sl, #4]\n \tcmp\tr3, #76\t@ 0x4c\n-\tbne.w\t47e2 <__gridxc_vdwxc_MOD_vdw_localxc+0x222>\n+\tbne.w\t47cc <__gridxc_vdwxc_MOD_vdw_localxc+0x218>\n \tldr\tr3, [r7, #12]\n \tmov\tr2, r4\n \tstrd\tr9, r3, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6499,37 +6541,92 @@\n \tstr\tr3, [sp, #16]\n \tmovs\tr3, #5\n \tstr.w\tr8, [sp, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #568]\t@ (4c0c <__gridxc_vdwxc_MOD_vdw_localxc+0x64c>)\n+\tldr\tr0, [pc, #160]\t@ (4a5c <__gridxc_vdwxc_MOD_vdw_localxc+0x4a8>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr2, [r7, #8]\n \tstr\tr2, [sp, #20]\n \tmov\tr1, sl\n \tldr\tr2, [r7, #4]\n \tstrd\tr5, r2, [sp, #12]\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #548]\t@ (4c10 <__gridxc_vdwxc_MOD_vdw_localxc+0x650>)\n+\tldr\tr0, [pc, #140]\t@ (4a60 <__gridxc_vdwxc_MOD_vdw_localxc+0x4ac>)\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tstr\tr3, [sp, #8]\n \tadd\tr0, pc\n \tmov\tr3, r6\n \tstrd\tr8, r8, [sp, #28]\n \tstr.w\tr8, [sp, #24]\n-\tb.n\t4976 <__gridxc_vdwxc_MOD_vdw_localxc+0x3b6>\n+\tb.n\t4960 <__gridxc_vdwxc_MOD_vdw_localxc+0x3ac>\n \tldrb\tr3, [r1, #4]\n \tcmp\tr3, #108\t@ 0x6c\n-\tbne.w\t47fa <__gridxc_vdwxc_MOD_vdw_localxc+0x23a>\n-\tb.n\t499a <__gridxc_vdwxc_MOD_vdw_localxc+0x3da>\n+\tbne.w\t47e4 <__gridxc_vdwxc_MOD_vdw_localxc+0x230>\n+\tb.n\t4984 <__gridxc_vdwxc_MOD_vdw_localxc+0x3d0>\n+\t...\n+\t.word\t0x0000041e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000003f4\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000029e\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000028a\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000276\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000274\n+ R_ARM_REL32\t.LC40\n+\t.word\t0x00000262\n+ R_ARM_REL32\t.LC41\n+\t.word\t0x0000023e\n+ R_ARM_REL32\t.data\n+\t.word\t0x0000022e\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000228\n+ R_ARM_REL32\t.LC44\n+\t.word\t0x00000218\n+ R_ARM_REL32\t.LC45\n+\t.word\t0x00000208\n+ R_ARM_REL32\t.LC33\n+\t.word\t0x000001f8\n+ R_ARM_REL32\t.LC47\n+\t.word\t0x000001e8\n+ R_ARM_REL32\t.LC34\n+\t.word\t0x000001d8\n+ R_ARM_REL32\t.LC49\n+\t.word\t0x000001c8\n+ R_ARM_REL32\t.LC35\n+\t.word\t0x000001b8\n+ R_ARM_REL32\t.LC50\n+\t.word\t0x000001a8\n+ R_ARM_REL32\t.LC21\n+\t.word\t0x00000198\n+ R_ARM_REL32\t.LC51\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__gridxc_sys_MOD_die\n+\t.word\t0x0000018a\n+ R_ARM_REL32\t.LC53\n+\t.word\t0x00000184\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000116\n+ R_ARM_REL32\t.LC42\n+\t.word\t0x00000100\n+ R_ARM_REL32\t.LC19\n+\t.word\t0x0000009a\n+ R_ARM_REL32\t.LC46\n+\t.word\t0x00000084\n+ R_ARM_REL32\t.LC19\n \tldr\tr3, [r7, #12]\n \tmov\tr2, r4\n \tstrd\tr9, r3, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6541,33 +6638,33 @@\n \tstr\tr3, [sp, #16]\n \tmovs\tr3, #6\n \tstr.w\tr8, [sp, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #468]\t@ (4c14 <__gridxc_vdwxc_MOD_vdw_localxc+0x654>)\n+\tldr\tr0, [pc, #364]\t@ (4c08 <__gridxc_vdwxc_MOD_vdw_localxc+0x654>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr2, [r7, #8]\n \tstr\tr2, [sp, #20]\n \tmov\tr1, sl\n \tldr\tr2, [r7, #4]\n \tstrd\tr5, r2, [sp, #12]\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #448]\t@ (4c18 <__gridxc_vdwxc_MOD_vdw_localxc+0x658>)\n+\tldr\tr0, [pc, #344]\t@ (4c0c <__gridxc_vdwxc_MOD_vdw_localxc+0x658>)\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tstr\tr3, [sp, #8]\n \tadd\tr0, pc\n \tmov\tr3, r6\n \tstrd\tr8, r8, [sp, #28]\n \tstr.w\tr8, [sp, #24]\n-\tb.n\t4976 <__gridxc_vdwxc_MOD_vdw_localxc+0x3b6>\n+\tb.n\t4960 <__gridxc_vdwxc_MOD_vdw_localxc+0x3ac>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tstr.w\tr9, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6582,25 +6679,25 @@\n \tstrd\tr8, r8, [sp, #32]\n \tstr\tr1, [sp, #0]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr8, [sp, #28]\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #372]\t@ (4c1c <__gridxc_vdwxc_MOD_vdw_localxc+0x65c>)\n+\tldr\tr0, [pc, #268]\t@ (4c10 <__gridxc_vdwxc_MOD_vdw_localxc+0x65c>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr0, [r7, #16]\n \tstr\tr0, [sp, #24]\n \tmov\tr1, sl\n \tldr\tr3, [r7, #12]\n \tstrd\tr5, r3, [sp, #16]\n-\tldr\tr0, [pc, #356]\t@ (4c20 <__gridxc_vdwxc_MOD_vdw_localxc+0x660>)\n+\tldr\tr0, [pc, #248]\t@ (4c14 <__gridxc_vdwxc_MOD_vdw_localxc+0x660>)\n \tldr\tr2, [r7, #36]\t@ 0x24\n \tstr\tr2, [sp, #12]\n \tmov\tr2, r4\n \tldr\tr3, [r7, #24]\n \tadd\tr0, pc\n \tstrd\tr8, r8, [sp, #32]\n \tstr\tr3, [sp, #8]\n@@ -6609,15 +6706,15 @@\n \tstr.w\tr9, [sp, #4]\n \tldr\tr4, [r7, #32]\n \tstr\tr4, [sp, #0]\n \tmovs\tr4, #3\n \tstr\tr4, [sp, #40]\t@ 0x28\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n-\tb.n\t48da <__gridxc_vdwxc_MOD_vdw_localxc+0x31a>\n+\tb.n\t48c4 <__gridxc_vdwxc_MOD_vdw_localxc+0x310>\n \tldr\tr3, [r7, #12]\n \tmov\tr2, r4\n \tstrd\tr9, r3, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6629,33 +6726,33 @@\n \tstr\tr3, [sp, #16]\n \tmovs\tr3, #2\n \tstr.w\tr8, [sp, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #264]\t@ (4c24 <__gridxc_vdwxc_MOD_vdw_localxc+0x664>)\n+\tldr\tr0, [pc, #156]\t@ (4c18 <__gridxc_vdwxc_MOD_vdw_localxc+0x664>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr2, [r7, #8]\n \tstr\tr2, [sp, #20]\n \tmov\tr1, sl\n \tldr\tr2, [r7, #4]\n \tstrd\tr5, r2, [sp, #12]\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #244]\t@ (4c28 <__gridxc_vdwxc_MOD_vdw_localxc+0x668>)\n+\tldr\tr0, [pc, #136]\t@ (4c1c <__gridxc_vdwxc_MOD_vdw_localxc+0x668>)\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tstr\tr3, [sp, #8]\n \tadd\tr0, pc\n \tmov\tr3, r6\n \tstrd\tr8, r8, [sp, #28]\n \tstr.w\tr8, [sp, #24]\n-\tb.n\t4976 <__gridxc_vdwxc_MOD_vdw_localxc+0x3b6>\n+\tb.n\t4960 <__gridxc_vdwxc_MOD_vdw_localxc+0x3ac>\n \tldr\tr3, [r7, #12]\n \tmov\tr2, r4\n \tstrd\tr9, r3, [sp, #20]\n \tadd.w\tr9, r7, #40\t@ 0x28\n \tstr.w\tr8, [sp, #12]\n \tmov.w\tr8, #0\n \tldr\tr3, [r7, #28]\n@@ -6667,950 +6764,880 @@\n \tstr\tr3, [sp, #16]\n \tmovs\tr3, #3\n \tstr.w\tr8, [sp, #28]\n \tstr\tr3, [sp, #40]\t@ 0x28\n \tmov\tr3, r6\n \tstr.w\tr9, [sp, #8]\n \tldr.w\tsl, [r7, #20]\n-\tldr\tr0, [pc, #172]\t@ (4c2c <__gridxc_vdwxc_MOD_vdw_localxc+0x66c>)\n+\tldr\tr0, [pc, #68]\t@ (4c20 <__gridxc_vdwxc_MOD_vdw_localxc+0x66c>)\n \tmov\tr1, sl\n \tadd\tr0, pc\n \tbl\t0 <__gridxc_gga_MOD_ggaxc>\n R_ARM_THM_CALL\t__gridxc_gga_MOD_ggaxc\n \tldr\tr2, [r7, #8]\n \tstr\tr2, [sp, #20]\n \tmov\tr1, sl\n \tldr\tr2, [r7, #4]\n \tstrd\tr5, r2, [sp, #12]\n \tmov\tr2, r4\n-\tldr\tr0, [pc, #152]\t@ (4c30 <__gridxc_vdwxc_MOD_vdw_localxc+0x670>)\n+\tldr\tr0, [pc, #48]\t@ (4c24 <__gridxc_vdwxc_MOD_vdw_localxc+0x670>)\n \tldr\tr3, [r7, #36]\t@ 0x24\n \tstr\tr3, [sp, #8]\n \tadd\tr0, pc\n \tmov\tr3, r6\n \tstrd\tr8, r8, [sp, #28]\n \tstr.w\tr8, [sp, #24]\n-\tb.n\t4976 <__gridxc_vdwxc_MOD_vdw_localxc+0x3b6>\n-\t.word\t0x000005c2\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000596\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000043e\n- R_ARM_REL32\t.data\n-\t.word\t0x00000428\n- R_ARM_REL32\t.data\n-\t.word\t0x00000412\n- R_ARM_REL32\t.data\n-\t.word\t0x00000410\n- R_ARM_REL32\t.LC40\n-\t.word\t0x000003fc\n- R_ARM_REL32\t.LC41\n-\t.word\t0x000003d8\n- R_ARM_REL32\t.data\n-\t.word\t0x000003c8\n- R_ARM_REL32\t.data\n-\t.word\t0x000003c2\n- R_ARM_REL32\t.LC44\n-\t.word\t0x000003b2\n- R_ARM_REL32\t.LC45\n-\t.word\t0x000003a2\n- R_ARM_REL32\t.LC33\n-\t.word\t0x00000392\n- R_ARM_REL32\t.LC47\n-\t.word\t0x00000382\n- R_ARM_REL32\t.LC34\n-\t.word\t0x00000372\n- R_ARM_REL32\t.LC49\n-\t.word\t0x00000362\n- R_ARM_REL32\t.LC35\n-\t.word\t0x00000352\n- R_ARM_REL32\t.LC50\n-\t.word\t0x00000342\n- R_ARM_REL32\t.LC21\n-\t.word\t0x00000332\n- R_ARM_REL32\t.LC51\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000324\n- R_ARM_REL32\t.LC53\n-\t.word\t0x0000031e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002b0\n- R_ARM_REL32\t.LC42\n-\t.word\t0x0000029a\n- R_ARM_REL32\t.LC19\n-\t.word\t0x00000234\n- R_ARM_REL32\t.LC46\n-\t.word\t0x0000021e\n- R_ARM_REL32\t.LC19\n-\t.word\t0x000001d0\n+\tb.n\t4960 <__gridxc_vdwxc_MOD_vdw_localxc+0x3ac>\n+\tnop\n+\t.word\t0x00000166\n R_ARM_REL32\t.LC48\n-\t.word\t0x000001ba\n+\t.word\t0x00000150\n R_ARM_REL32\t.LC19\n-\t.word\t0x00000170\n+\t.word\t0x00000106\n R_ARM_REL32\t.LC46\n-\t.word\t0x00000158\n+\t.word\t0x000000ee\n R_ARM_REL32\t.LC52\n-\t.word\t0x00000102\n+\t.word\t0x00000098\n R_ARM_REL32\t.LC35\n-\t.word\t0x000000ec\n+\t.word\t0x00000082\n R_ARM_REL32\t.LC19\n-\t.word\t0x000000a8\n+\t.word\t0x0000003e\n R_ARM_REL32\t.LC34\n-\t.word\t0x00000092\n+\t.word\t0x00000028\n R_ARM_REL32\t.LC19\n \n-00004c34 <__gridxc_vdwxc_MOD_vdw_get_qmesh>:\n+00004c28 <__gridxc_vdwxc_MOD_vdw_get_qmesh>:\n __gridxc_vdwxc_MOD_vdw_get_qmesh():\n-\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n+\tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4000]\t@ 0xfa0\n-\tldr\tr2, [pc, #504]\t@ (4e40 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x20c>)\n-\tsub\tsp, #64\t@ 0x40\n-\tldr\tr3, [pc, #504]\t@ (4e44 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x210>)\n+\tstr.w\tr0, [ip, #3992]\t@ 0xf98\n+\tldr\tr2, [pc, #496]\t@ (4e2c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x204>)\n+\tsub\tsp, #68\t@ 0x44\n+\tldr\tr3, [pc, #496]\t@ (4e30 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x208>)\n \tmov\tr4, r0\n \tadd\tr2, pc\n-\tldr.w\tr9, [pc, #504]\t@ 4e48 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x214>\n+\tldr.w\tr9, [pc, #496]\t@ 4e34 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x20c>\n \tadd\tr9, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #60]\t@ 0x3c\n \tmov.w\tr3, #0\n \tcmp\tr1, #0\n-\tbeq.n\t4ce4 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xb0>\n+\tbeq.n\t4cda <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xb2>\n \tldr\tr7, [r1, #0]\n \tmov\tip, r1\n \tcmp\tr7, #0\n-\tbeq.n\t4ce4 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xb0>\n+\tbeq.n\t4cda <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xb2>\n \tldr\tr6, [r1, #24]\n \tnegs\tr5, r6\n-\tcbnz\tr6, 4c76 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x42>\n+\tcbnz\tr6, 4c6a <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x42>\n \tmov.w\tr5, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n-\tldr\tr1, [pc, #468]\t@ (4e4c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x218>)\n+\tldr\tr1, [pc, #460]\t@ (4e38 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x210>)\n \tmovs\tr2, #2\n-\tldr\tr3, [pc, #468]\t@ (4e50 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x21c>)\n+\tldr\tr3, [pc, #460]\t@ (4e3c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x214>)\n \tmovs\tr0, #5\n \tadd\tr1, pc\n \tadds\tr1, #24\n \tadd\tr3, pc\n \tldrd\tsl, r8, [ip, #28]\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t4dec <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1b8>\n-\tldr\tr3, [pc, #448]\t@ (4e54 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x220>)\n+\tbeq.w\t4de8 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1c0>\n+\tldr\tr3, [pc, #440]\t@ (4e40 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x218>)\n \tsub.w\tr8, r8, sl\n \tadd.w\tr8, r8, #1\n \tadd\tr3, pc\n \tldr.w\tr3, [r3, #448]\t@ 0x1c0\n \tcmp\tr3, #0\n-\tbeq.n\t4d24 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xf0>\n+\tbeq.n\t4d1a <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xf2>\n \tmov\tr2, r8\n \tmovs\tr3, #30\n \tcmp\tr2, #30\n \tstr\tr3, [r4, #0]\n \tit\tlt\n \tmovlt\tr2, #30\n \tcmp\tr6, #1\n-\tbne.n\t4db2 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x17e>\n-\tldr\tr4, [pc, #416]\t@ (4e58 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x224>)\n+\tbne.w\t4dae <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x186>\n+\tldr\tr4, [pc, #404]\t@ (4e44 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x21c>)\n \tadds\tr0, r5, #1\n-\tldr\tr3, [pc, #392]\t@ (4e44 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x210>)\n+\tldr\tr3, [pc, #380]\t@ (4e30 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x208>)\n \tlsls\tr2, r2, #3\n \tadd\tr4, pc\n-\tldr\tr1, [pc, #408]\t@ (4e5c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x228>)\n+\tldr\tr1, [pc, #400]\t@ (4e48 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x220>)\n \tadd.w\tr0, r7, r0, lsl #3\n \tadd\tr1, pc\n \tldr\tr3, [r4, r3]\n \tadds\tr1, #176\t@ 0xb0\n \tldr\tr4, [r3, #0]\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \teors\tr4, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4e2c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1f8>\n-\tadd\tsp, #64\t@ 0x40\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n+\tbne.w\t4e28 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x200>\n+\tadd\tsp, #68\t@ 0x44\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemcpy\n-\tldr\tr1, [pc, #376]\t@ (4e60 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x22c>)\n+\tldr\tr1, [pc, #368]\t@ (4e4c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x224>)\n \tmovs\tr2, #2\n-\tldr\tr3, [pc, #376]\t@ (4e64 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x230>)\n+\tldr\tr3, [pc, #368]\t@ (4e50 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x228>)\n \tmovs\tr0, #5\n \tadd\tr1, pc\n \tadd\tr3, pc\n \tadds\tr1, #24\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\t4dd4 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1a0>\n-\tldr\tr3, [pc, #364]\t@ (4e68 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x234>)\n+\tbeq.n\t4dd0 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1a8>\n+\tldr\tr3, [pc, #352]\t@ (4e54 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x22c>)\n \tadd\tr3, pc\n \tldr.w\tr7, [r3, #448]\t@ 0x1c0\n-\tcbz\tr7, 4d24 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xf0>\n+\tcbz\tr7, 4d1a <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xf2>\n \tmovs\tr3, #30\n \tstr\tr3, [r4, #0]\n-\tldr\tr2, [pc, #352]\t@ (4e6c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x238>)\n-\tldr\tr3, [pc, #312]\t@ (4e44 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x210>)\n+\tldr\tr2, [pc, #344]\t@ (4e58 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x230>)\n+\tldr\tr3, [pc, #300]\t@ (4e30 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x208>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4e2c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1f8>\n-\tadd\tsp, #64\t@ 0x40\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, pc}\n-\tldr\tr3, [pc, #328]\t@ (4e70 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x23c>)\n+\tbne.w\t4e28 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x200>\n+\tadd\tsp, #68\t@ 0x44\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tldr\tr3, [pc, #320]\t@ (4e5c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x234>)\n \tmov.w\tr9, #0\n \tmov\tr2, r9\n \tstr.w\tr9, [sp]\n \tadd\tr3, pc\n+\tmov.w\tfp, #30\n \tadd.w\tsl, r3, #16\n \tadd.w\tr1, r3, #40\t@ 0x28\n \tmov\tr0, sl\n \taddw\tr3, r3, #2120\t@ 0x848\n \tstr\tr1, [sp, #4]\n \tmov\tr1, r9\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n+\tstr.w\tr9, [sp, #40]\t@ 0x28\n \tmov\tr3, r9\n \tstrd\tr9, r9, [sp, #4]\n-\tvmov.i32\td18, #0\t@ 0x00000000\n \tstr.w\tr9, [sp]\n-\tadd\tr2, sp, #44\t@ 0x2c\n-\tvldr\td16, [pc, #212]\t@ 4e30 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1fc>\n-\tvldr\td17, [pc, #216]\t@ 4e38 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x204>\n \tmov\tr0, sl\n-\tldr.w\tr9, [pc, #272]\t@ 4e74 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x240>\n+\tstr.w\tr9, [sp, #36]\t@ 0x24\n+\tadd\tr2, sp, #24\n+\tldr.w\tr9, [pc, #260]\t@ 4e60 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x238>\n \tadd\tr1, sp, #20\n \tmov.w\tip, #8\n-\tvstr\td18, [sp, #36]\t@ 0x24\n+\tmov.w\tsl, #1\n \tadd\tr9, pc\n-\tvst1.32\t{d16-d17}, [r2]\n-\tadd\tr2, sp, #24\n+\tstr.w\tip, [sp, #44]\t@ 0x2c\n \tstr.w\tip, [sp, #32]\n \tadd.w\tip, r9, #176\t@ 0xb0\n+\tstrd\tsl, sl, [sp, #48]\t@ 0x30\n \tstr.w\tip, [sp, #24]\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n+\tstr.w\tfp, [sp, #56]\t@ 0x38\n \tstr.w\tip, [sp, #28]\n \tmovw\tip, #769\t@ 0x301\n \tstrh.w\tip, [sp, #40]\t@ 0x28\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r9, #448]\t@ 0x1c0\n-\tmovs\tr3, #30\n-\tstr\tr3, [r4, #0]\n+\tstr.w\tsl, [r9, #448]\t@ 0x1c0\n+\tstr.w\tfp, [r4]\n \tcmp\tr7, #0\n-\tbeq.n\t4d08 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd4>\n+\tbeq.n\t4cfe <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd6>\n \tmov\tr2, r8\n \tcmp\tr2, #30\n \tit\tlt\n \tmovlt\tr2, #30\n \tcmp\tr6, #1\n-\tbeq.n\t4cb6 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x82>\n-\tldr\tr3, [pc, #196]\t@ (4e78 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x244>)\n+\tbeq.w\t4cac <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x84>\n+\tldr\tr3, [pc, #180]\t@ (4e64 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x23c>)\n \tadd\tr5, r6\n \tlsls\tr6, r6, #3\n \tadd\tr3, pc\n \tadd.w\tr0, r7, r5, lsl #3\n \tadds\tr3, #176\t@ 0xb0\n \tadd.w\tr2, r3, r2, lsl #3\n \tldrd\tr4, r5, [r3], #8\n \tstrd\tr4, r5, [r0]\n \tadd\tr0, r6\n-\tcmp\tr2, r3\n-\tbne.n\t4dc4 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x190>\n-\tb.n\t4d08 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd4>\n+\tcmp\tr3, r2\n+\tbne.n\t4dc0 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x198>\n+\tb.n\t4cfe <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd6>\n \tmov\tr3, r0\n \tmov\tr2, r0\n \tadd\tr1, sp, #20\n \tadd\tr0, sp, #16\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh>\n R_ARM_THM_CALL\t__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n \tldrd\tr3, r2, [sp, #16]\n \tmul.w\tr3, r2, r3\n \tstr\tr3, [r4, #0]\n-\tb.n\t4d08 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd4>\n+\tb.n\t4cfe <__gridxc_vdwxc_MOD_vdw_get_qmesh+0xd6>\n \tmov\tr3, r0\n \tmov\tr2, r0\n \tadd\tr1, sp, #20\n \tadd\tr0, sp, #16\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh>\n R_ARM_THM_CALL\t__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n \tldrd\tr3, r2, [sp, #16]\n \tmul.w\tr3, r2, r3\n-\tldr\tr2, [pc, #120]\t@ (4e7c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x248>)\n+\tldr\tr2, [pc, #104]\t@ (4e68 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x240>)\n \tstr\tr3, [r4, #0]\n-\tldr\tr3, [pc, #60]\t@ (4e44 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x210>)\n+\tldr\tr3, [pc, #44]\t@ (4e30 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x208>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #60]\t@ 0x3c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t4e2c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x1f8>\n-\tldr\tr3, [pc, #104]\t@ (4e80 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x24c>)\n+\tbne.n\t4e28 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x200>\n+\tldr\tr3, [pc, #88]\t@ (4e6c <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x244>)\n \tmovs\tr1, #55\t@ 0x37\n-\tldr\tr0, [pc, #104]\t@ (4e84 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x250>)\n+\tldr\tr0, [pc, #88]\t@ (4e70 <__gridxc_vdwxc_MOD_vdw_get_qmesh+0x248>)\n \tadd\tr0, pc\n \tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n-\tadd\tsp, #64\t@ 0x40\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, lr}\n+\tadd\tsp, #68\t@ 0x44\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tbx\tr3\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000001e\n-\t.word\t0x000001f0\n+\t.word\t0x000001e8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000001f2\n+\t.word\t0x000001ea\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001ca\n+\t.word\t0x000001c2\n R_ARM_REL32\t.data\n-\t.word\t0x000001ca\n+\t.word\t0x000001c2\n R_ARM_REL32\t.LC21\n-\t.word\t0x000001b4\n+\t.word\t0x000001ac\n R_ARM_REL32\t.bss\n-\t.word\t0x00000196\n+\t.word\t0x0000018c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000192\n+\t.word\t0x00000188\n R_ARM_REL32\t.bss\n-\t.word\t0x00000170\n+\t.word\t0x00000166\n R_ARM_REL32\t.data\n-\t.word\t0x00000172\n- R_ARM_REL32\t.LC21\n \t.word\t0x00000168\n+ R_ARM_REL32\t.LC21\n+\t.word\t0x0000015e\n R_ARM_REL32\t.bss\n-\t.word\t0x0000015c\n+\t.word\t0x00000152\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000013c\n+\t.word\t0x00000132\n R_ARM_REL32\t.rodata\n-\t.word\t0x00000100\n+\t.word\t0x000000f6\n R_ARM_REL32\t.bss\n-\t.word\t0x000000bc\n+\t.word\t0x000000ac\n R_ARM_REL32\t.bss\n-\t.word\t0x00000072\n+\t.word\t0x00000062\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000064\n+\t.word\t0x00000054\n R_ARM_REL32\t.LC54\n \n-00004e88 <__gridxc_vdwxc_MOD_vdw_decusp>:\n+00004e74 <__gridxc_vdwxc_MOD_vdw_decusp>:\n __gridxc_vdwxc_MOD_vdw_decusp():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d11}\n+\tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n-\tstr.w\tr0, [ip]\n-\tstr.w\tr0, [ip, #-24]\n+\tstr.w\tr0, [ip, #8]\n \tsub.w\tsp, sp, #8128\t@ 0x1fc0\n-\tmov\tr8, r2\n-\tsub\tsp, #20\n-\tldr.w\tr2, [pc, #1396]\t@ 5428 <__gridxc_vdwxc_MOD_vdw_decusp+0x5a0>\n-\tadd.w\tr4, sp, #8192\t@ 0x2000\n-\tadd.w\tr6, sp, #8192\t@ 0x2000\n+\tmov\tr6, r2\n+\tsub\tsp, #4\n+\tldr\tr2, [pc, #948]\t@ (5250 <__gridxc_vdwxc_MOD_vdw_decusp+0x3dc>)\n+\tadd.w\tr4, sp, #8160\t@ 0x1fe0\n+\tmov\tr7, r1\n \tadds\tr4, #24\n+\tldr\tr1, [r0, #0]\n+\tstr\tr3, [sp, #80]\t@ 0x50\n \tadd\tr2, pc\n-\tstr\tr3, [sp, #88]\t@ 0x58\n-\tadds\tr6, #28\n-\tldr.w\tr3, [pc, #1380]\t@ 542c <__gridxc_vdwxc_MOD_vdw_decusp+0x5a4>\n+\tldr\tr3, [pc, #936]\t@ (5254 <__gridxc_vdwxc_MOD_vdw_decusp+0x3e0>)\n+\tmovs\tr0, #5\n \tldr\tr4, [r4, #0]\n-\tstr\tr4, [sp, #92]\t@ 0x5c\n-\tmov\tr4, r1\n-\tadd.w\tr1, sp, #8128\t@ 0x1fc0\n-\tldr.w\tr7, [pc, #1372]\t@ 5430 <__gridxc_vdwxc_MOD_vdw_decusp+0x5a8>\n+\tstr\tr4, [sp, #84]\t@ 0x54\n+\tadd.w\tr4, sp, #8160\t@ 0x1fe0\n+\tstr\tr1, [sp, #60]\t@ 0x3c\n+\tadd.w\tr1, sp, #8096\t@ 0x1fa0\n+\tadds\tr1, #28\n+\tldr\tr5, [pc, #920]\t@ (5258 <__gridxc_vdwxc_MOD_vdw_decusp+0x3e4>)\n \tldr\tr3, [r2, r3]\n-\tadds\tr1, #12\n-\tldr\tr5, [r0, #0]\n \tmovs\tr2, #2\n+\tadd\tr5, pc\n+\tadds\tr4, #28\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r1, #0]\n \tmov.w\tr3, #0\n-\tldr.w\tr1, [pc, #1356]\t@ 5434 <__gridxc_vdwxc_MOD_vdw_decusp+0x5ac>\n-\tldr.w\tr3, [pc, #1356]\t@ 5438 <__gridxc_vdwxc_MOD_vdw_decusp+0x5b0>\n-\tmovs\tr0, #5\n+\tldr\tr1, [pc, #908]\t@ (525c <__gridxc_vdwxc_MOD_vdw_decusp+0x3e8>)\n+\tldr\tr3, [pc, #908]\t@ (5260 <__gridxc_vdwxc_MOD_vdw_decusp+0x3ec>)\n \tadd\tr1, pc\n-\tldr\tr6, [r6, #0]\n+\tldr.w\tr8, [r4]\n \tadds\tr1, #24\n \tadd\tr3, pc\n-\tadd\tr7, pc\n-\tstr\tr6, [sp, #96]\t@ 0x60\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t50aa <__gridxc_vdwxc_MOD_vdw_decusp+0x222>\n-\tldr.w\tr3, [pc, #1332]\t@ 543c <__gridxc_vdwxc_MOD_vdw_decusp+0x5b4>\n+\tbeq.w\t5088 <__gridxc_vdwxc_MOD_vdw_decusp+0x214>\n+\tldr\tr3, [pc, #892]\t@ (5264 <__gridxc_vdwxc_MOD_vdw_decusp+0x3f0>)\n \tadd\tr3, pc\n-\tldr.w\tr2, [r3, #736]\t@ 0x2e0\n+\tldr.w\tr2, [r3, #720]\t@ 0x2d0\n \tcmp\tr2, #0\n-\tbeq.w\t5100 <__gridxc_vdwxc_MOD_vdw_decusp+0x278>\n-\tadd.w\tlr, sp, #176\t@ 0xb0\n-\tadd.w\tr9, sp, #4048\t@ 0xfd0\n-\tadd\tr3, sp, #160\t@ 0xa0\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr3, sp, #720\t@ 0x2d0\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tadd\tr3, sp, #696\t@ 0x2b8\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tadd\tr3, sp, #464\t@ 0x1d0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tadd\tr3, sp, #456\t@ 0x1c8\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\tcmp\tr5, #0\n-\tble.w\t50e8 <__gridxc_vdwxc_MOD_vdw_decusp+0x260>\n-\tvldr\td9, [r4]\n-\tcmp\tr5, #1\n-\tbeq.w\t54e8 <__gridxc_vdwxc_MOD_vdw_decusp+0x660>\n-\tvldr\td22, [r4, #8]\n-\tsub.w\tr3, r9, #3856\t@ 0xf10\n-\tvldr\td18, [r8]\n-\tadd\tr6, sp, #192\t@ 0xc0\n-\tvldr\td21, [r8, #24]\n-\tvadd.f64\td9, d9, d22\n-\tvldr\td17, [r8, #8]\n-\tvldr\td20, [r8, #32]\n-\tvldr\td16, [r8, #40]\t@ 0x28\n-\tvadd.f64\td18, d18, d21\n-\tvldr\td19, [r8, #16]\n-\tvadd.f64\td17, d17, d20\n+\tbeq.w\t50e4 <__gridxc_vdwxc_MOD_vdw_decusp+0x270>\n+\tadd\tr4, sp, #160\t@ 0xa0\n+\tadd.w\tfp, sp, #4032\t@ 0xfc0\n+\tadd\tr3, sp, #144\t@ 0x90\n+\tstr\tr3, [sp, #28]\n+\tadd\tr3, sp, #704\t@ 0x2c0\n+\tstr\tr3, [sp, #92]\t@ 0x5c\n+\tadd\tr3, sp, #680\t@ 0x2a8\n+\tstr\tr3, [sp, #32]\n+\tadd\tr3, sp, #448\t@ 0x1c0\n+\tstr\tr3, [sp, #88]\t@ 0x58\n+\tadd\tr3, sp, #440\t@ 0x1b8\n+\tstr\tr3, [sp, #36]\t@ 0x24\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tr3, #0\n+\tble.w\t50ca <__gridxc_vdwxc_MOD_vdw_decusp+0x256>\n+\tvldr\td9, [r7]\n+\tcmp\tr3, #1\n+\tbeq.w\t5488 <__gridxc_vdwxc_MOD_vdw_decusp+0x614>\n+\tvldr\td1, [r7, #8]\n+\tsub.w\tr3, fp, #3856\t@ 0xf10\n+\tvldr\td5, [r6]\n+\tadd\tr7, sp, #176\t@ 0xb0\n+\tvldr\td2, [r6, #24]\n+\tvadd.f64\td9, d9, d1\n+\tvldr\td6, [r6, #8]\n+\tvldr\td3, [r6, #32]\n+\tvldr\td7, [r6, #40]\t@ 0x28\n+\tvadd.f64\td5, d5, d2\n+\tvldr\td4, [r6, #16]\n+\tvadd.f64\td6, d6, d3\n \tvmul.f64\td8, d9, d9\n-\tvadd.f64\td16, d16, d19\n-\tvstr\td18, [r3]\n-\tvstr\td17, [r3, #8]\n-\tvstr\td16, [r3, #16]\n-\tldr\tr4, [sp, #44]\t@ 0x2c\n-\tsub.w\tsl, lr, #8\n-\tadd.w\tfp, sp, #144\t@ 0x90\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td5, [r3]\n+\tvstr\td6, [r3, #8]\n+\tvstr\td7, [r3, #16]\n+\tsub.w\tsl, r4, #8\n+\tldr\tr4, [sp, #28]\n+\tadd.w\tr9, sp, #128\t@ 0x80\n \tmov\tr3, sl\n \tvmov.f64\td0, d9\n-\tmov\tr0, r6\n+\tmov\tr0, r7\n \tmov\tr1, r4\n-\tmov\tr2, fp\n-\tbl\t2270 <__gridxc_vdwxc_MOD_qofrho.isra.0>\n-\tldr\tr7, [sp, #52]\t@ 0x34\n-\tadd.w\tr8, sp, #216\t@ 0xd8\n+\tmov\tr2, r9\n+\tbl\t2220 <__gridxc_vdwxc_MOD_qofrho.isra.0>\n+\tldr\tr6, [sp, #36]\t@ 0x24\n+\tadd\tr7, sp, #200\t@ 0xc8\n \tmov\tr0, r4\n-\tmov\tr1, r7\n-\tmov\tr2, r8\n-\tbl\t8d0 <__gridxc_vdwxc_MOD_pofq>\n+\tmov\tr1, r6\n+\tmov\tr2, r7\n+\tbl\t940 <__gridxc_vdwxc_MOD_pofq>\n \tmovs\tr2, #240\t@ 0xf0\n \tmovs\tr1, #0\n-\tsubw\tr0, r9, #3352\t@ 0xd18\n+\tsubw\tr0, fp, #3352\t@ 0xd18\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [sp, #100]\t@ 0x64\n-\tldr\tr4, [sp, #104]\t@ 0x68\n-\tmov\tlr, r7\n-\tldr.w\tr6, [pc, #1148]\t@ 5440 <__gridxc_vdwxc_MOD_vdw_decusp+0x5b8>\n+\tldr\tr3, [sp, #88]\t@ 0x58\n+\tldr\tr4, [sp, #92]\t@ 0x5c\n+\tmov\tlr, r6\n+\tldr\tr5, [pc, #712]\t@ (5268 <__gridxc_vdwxc_MOD_vdw_decusp+0x3f4>)\n \tadds\tr3, #232\t@ 0xe8\n-\tldr\tr0, [sp, #48]\t@ 0x30\n+\tldr\tr0, [sp, #32]\n \tadds\tr4, #216\t@ 0xd8\n \tmov\tr1, r3\n-\tadd\tr6, pc\n+\tadd\tr5, pc\n \tmov\tr2, r0\n-\tvldmia\tr0!, {d16}\n-\tmov\tr7, lr\n-\tmov\tip, r6\n+\tvldmia\tr0!, {d7}\n+\tmov\tr6, lr\n+\tmov\tip, r5\n \tmov\tr3, lr\n-\tvldmia\tr3!, {d18}\n-\tvldmia\tip!, {d17}\n+\tvldmia\tr3!, {d5}\n+\tvldmia\tip!, {d6}\n \tcmp\tr1, r3\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t4fda <__gridxc_vdwxc_MOD_vdw_decusp+0x152>\n-\tadds\tr6, #240\t@ 0xf0\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t4fb4 <__gridxc_vdwxc_MOD_vdw_decusp+0x140>\n+\tadds\tr5, #240\t@ 0xf0\n \tcmp\tr4, r0\n-\tvstr\td16, [r0, #-8]\n-\tbne.n\t4fd0 <__gridxc_vdwxc_MOD_vdw_decusp+0x148>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tvldmia\tr3!, {d18}\n-\tvldmia\tr7!, {d17}\n+\tvstr\td7, [r0, #-8]\n+\tbne.n\t4faa <__gridxc_vdwxc_MOD_vdw_decusp+0x136>\n+\tldr\tr3, [sp, #32]\n+\tvldr\td7, [pc, #612]\t@ 5238 <__gridxc_vdwxc_MOD_vdw_decusp+0x3c4>\n+\tvldmia\tr3!, {d5}\n+\tvldmia\tr6!, {d6}\n \tcmp\tr4, r3\n-\tvfma.f64\td16, d18, d17\n-\tbne.n\t4ffa <__gridxc_vdwxc_MOD_vdw_decusp+0x172>\n-\tvmov.i64\td19, #0x0000000000000000\n-\tvldmia\tr2!, {d18}\n-\tvldmia\tr8!, {d17}\n+\tvmla.f64\td7, d5, d6\n+\tbne.n\t4fd4 <__gridxc_vdwxc_MOD_vdw_decusp+0x160>\n+\tvldr\td5, [pc, #592]\t@ 5238 <__gridxc_vdwxc_MOD_vdw_decusp+0x3c4>\n+\tvldmia\tr2!, {d4}\n+\tvldmia\tr7!, {d6}\n \tcmp\tr4, r2\n-\tvfma.f64\td19, d18, d17\n-\tbne.n\t500e <__gridxc_vdwxc_MOD_vdw_decusp+0x186>\n+\tvmla.f64\td5, d4, d6\n+\tbne.n\t4fe8 <__gridxc_vdwxc_MOD_vdw_decusp+0x174>\n+\tvmul.f64\td7, d7, d9\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tvadd.f64\td8, d8, d8\n-\tvmul.f64\td16, d16, d9\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tvldr\td18, [fp]\n-\tmovs\tr2, #0\n-\tcmp\tr5, #0\n-\tvmul.f64\td19, d8, d19\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #92]\t@ 0x5c\n-\tvmul.f64\td18, d19, d18\n-\tvfma.f64\td18, d16, d20\n-\tble.n\t5080 <__gridxc_vdwxc_MOD_vdw_decusp+0x1f8>\n-\tmov\tr6, r2\n+\tvldr\td4, [r9]\n+\tvstr\td7, [r3]\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tvmul.f64\td8, d8, d5\n+\tvadd.f64\td5, d7, d7\n+\tcmp\tr3, #0\n+\tit\tgt\n+\tmovgt\tr2, #0\n+\tvmla.f64\td5, d8, d4\n+\tit\tgt\n+\tldrgt\tr3, [sp, #84]\t@ 0x54\n+\tble.n\t505e <__gridxc_vdwxc_MOD_vdw_decusp+0x1ea>\n+\tldr\tr1, [sp, #60]\t@ 0x3c\n+\tmov\tr5, r2\n \tadds\tr2, #1\n-\tcmp\tr2, r5\n-\tvstmia\tr3!, {d18}\n-\tbne.n\t5048 <__gridxc_vdwxc_MOD_vdw_decusp+0x1c0>\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tmov\tr5, sl\n+\tvstmia\tr3!, {d5}\n+\tcmp\tr1, r2\n+\tbne.n\t5024 <__gridxc_vdwxc_MOD_vdw_decusp+0x1b0>\n+\tmov\tr6, sl\n+\tadd.w\tr2, r8, #8\n \tmvn.w\tr3, #2\n-\tadds\tr2, #8\n-\tvldmia\tr5!, {d17}\n+\tvldmia\tr6!, {d6}\n \tmov\tr0, r2\n \tmovs\tr1, #0\n-\tvmul.f64\td17, d19, d17\n-\tcmp\tr6, r1\n-\tvstr\td17, [r0, #-8]\n+\tvmul.f64\td6, d8, d6\n+\tcmp\tr5, r1\n+\tvstr\td6, [r0, #-8]\n \tadd.w\tr1, r1, #1\n \tadd.w\tr0, r0, #24\n-\tbne.n\t506a <__gridxc_vdwxc_MOD_vdw_decusp+0x1e2>\n+\tbne.n\t5048 <__gridxc_vdwxc_MOD_vdw_decusp+0x1d4>\n \tadds\tr2, #8\n \tadds\tr3, #1\n-\tbne.n\t505e <__gridxc_vdwxc_MOD_vdw_decusp+0x1d6>\n-\tldr\tr2, [pc, #960]\t@ (5444 <__gridxc_vdwxc_MOD_vdw_decusp+0x5bc>)\n-\tadd.w\tr1, sp, #8128\t@ 0x1fc0\n-\tldr\tr3, [pc, #932]\t@ (542c <__gridxc_vdwxc_MOD_vdw_decusp+0x5a4>)\n-\tadds\tr1, #12\n+\tbne.n\t503c <__gridxc_vdwxc_MOD_vdw_decusp+0x1c8>\n+\tldr\tr2, [pc, #524]\t@ (526c <__gridxc_vdwxc_MOD_vdw_decusp+0x3f8>)\n+\tadd.w\tr1, sp, #8096\t@ 0x1fa0\n+\tldr\tr3, [pc, #492]\t@ (5254 <__gridxc_vdwxc_MOD_vdw_decusp+0x3e0>)\n+\tadds\tr1, #28\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t550e <__gridxc_vdwxc_MOD_vdw_decusp+0x686>\n+\tbne.w\t54a2 <__gridxc_vdwxc_MOD_vdw_decusp+0x62e>\n \tadd.w\tsp, sp, #8128\t@ 0x1fc0\n-\tadd\tsp, #20\n-\tvpop\t{d8-d11}\n+\tadd\tsp, #4\n+\tvpop\t{d8-d9}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tmov\tr6, r0\n+\tmov\tr4, r0\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_vv_vdw_beta>\n R_ARM_THM_CALL\t__gridxc_vv_vdwxc_MOD_vv_vdw_beta\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tcmp\tr5, #0\n+\tldr\tr3, [sp, #80]\t@ 0x50\n \tvstr\td0, [r3]\n-\tble.n\t5080 <__gridxc_vdwxc_MOD_vdw_decusp+0x1f8>\n-\tldr\tr2, [sp, #92]\t@ 0x5c\n-\tmov\tr3, r6\n+\tldr\tr3, [sp, #60]\t@ 0x3c\n+\tcmp\tr3, #0\n+\tble.n\t505e <__gridxc_vdwxc_MOD_vdw_decusp+0x1ea>\n+\tldr\tr2, [sp, #84]\t@ 0x54\n+\tmov\tr3, r4\n+\tldr\tr1, [sp, #60]\t@ 0x3c\n \tadds\tr3, #1\n \tvstmia\tr2!, {d0}\n-\tcmp\tr3, r5\n-\tbne.n\t50be <__gridxc_vdwxc_MOD_vdw_decusp+0x236>\n-\tldr\tr3, [sp, #96]\t@ 0x60\n+\tcmp\tr3, r1\n+\tbne.n\t509e <__gridxc_vdwxc_MOD_vdw_decusp+0x22a>\n+\tmov\tr3, r8\n+\tmovs\tr2, #0\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n-\tmovs\tr2, #0\n+\tldr\tr4, [sp, #60]\t@ 0x3c\n \tadds\tr2, #1\n \tstrd\tr0, r1, [r3]\n-\tstrd\tr0, r1, [r3, #8]\n-\tcmp\tr2, r5\n-\tstrd\tr0, r1, [r3, #16]\n-\tadd.w\tr3, r3, #24\n-\tbne.n\t50d0 <__gridxc_vdwxc_MOD_vdw_decusp+0x248>\n-\tb.n\t5080 <__gridxc_vdwxc_MOD_vdw_decusp+0x1f8>\n-\tvmov.i32\tq8, #0\t@ 0x00000000\n-\tadd\tr6, sp, #192\t@ 0xc0\n-\tvmov.i64\td8, #0x0000000000000000\n-\tvst1.8\t{d16-d17}, [r6 :64]\n+\tadds\tr3, #24\n+\tstrd\tr0, r1, [r3, #-16]\n+\tcmp\tr2, r4\n+\tstrd\tr0, r1, [r3, #-8]\n+\tbne.n\t50b2 <__gridxc_vdwxc_MOD_vdw_decusp+0x23e>\n+\tb.n\t505e <__gridxc_vdwxc_MOD_vdw_decusp+0x1ea>\n+\tadd\tr7, sp, #176\t@ 0xb0\n+\tvldr\td8, [pc, #360]\t@ 5238 <__gridxc_vdwxc_MOD_vdw_decusp+0x3c4>\n+\tmovs\tr3, #0\n+\tstr\tr3, [sp, #176]\t@ 0xb0\n \tvmov.f64\td9, d8\n-\tvstr\td16, [r6, #16]\n-\tb.n\t4f84 <__gridxc_vdwxc_MOD_vdw_decusp+0xfc>\n+\tstrd\tr3, r3, [r7, #4]\n+\tstrd\tr3, r3, [r7, #12]\n+\tstr\tr3, [r7, #20]\n+\tb.n\t4f62 <__gridxc_vdwxc_MOD_vdw_decusp+0xee>\n \tldr.w\tr3, [r3, #432]\t@ 0x1b0\n \tcmp\tr3, #0\n-\tbeq.w\t54e2 <__gridxc_vdwxc_MOD_vdw_decusp+0x65a>\n-\tldr\tr3, [pc, #828]\t@ (5448 <__gridxc_vdwxc_MOD_vdw_decusp+0x5c0>)\n+\tbeq.w\t5482 <__gridxc_vdwxc_MOD_vdw_decusp+0x60e>\n+\tldr\tr3, [pc, #384]\t@ (5270 <__gridxc_vdwxc_MOD_vdw_decusp+0x3fc>)\n \tadd\tr3, pc\n-\tldr.w\tr3, [r3, #732]\t@ 0x2dc\n+\tldr.w\tr3, [r3, #716]\t@ 0x2cc\n \tcmp\tr3, #0\n-\tbeq.w\t54d2 <__gridxc_vdwxc_MOD_vdw_decusp+0x64a>\n-\tldr\tr0, [pc, #816]\t@ (544c <__gridxc_vdwxc_MOD_vdw_decusp+0x5c4>)\n+\tbeq.w\t5472 <__gridxc_vdwxc_MOD_vdw_decusp+0x5fe>\n+\tldr\tr0, [pc, #372]\t@ (5274 <__gridxc_vdwxc_MOD_vdw_decusp+0x400>)\n \tmov.w\tr2, #7200\t@ 0x1c20\n \tmovs\tr1, #0\n-\tldr.w\tfp, [pc, #812]\t@ 5450 <__gridxc_vdwxc_MOD_vdw_decusp+0x5c8>\n+\tldr.w\tsl, [pc, #368]\t@ 5278 <__gridxc_vdwxc_MOD_vdw_decusp+0x404>\n \tadd\tr0, pc\n-\tadd.w\tr9, sp, #4048\t@ 0xfd0\n+\tadd.w\tfp, sp, #4032\t@ 0xfc0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [pc, #804]\t@ (5454 <__gridxc_vdwxc_MOD_vdw_decusp+0x5cc>)\n-\tadd\tfp, pc\n-\tadd.w\tlr, sp, #176\t@ 0xb0\n+\tldr\tr3, [pc, #360]\t@ (527c <__gridxc_vdwxc_MOD_vdw_decusp+0x408>)\n+\tadd\tsl, pc\n+\tmovs\tr2, #1\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #76]\t@ 0x4c\n-\tvldr\td10, [pc, #716]\t@ 5408 <__gridxc_vdwxc_MOD_vdw_decusp+0x580>\n-\tvldr\td11, [pc, #720]\t@ 5410 <__gridxc_vdwxc_MOD_vdw_decusp+0x588>\n-\tstrd\tr8, lr, [sp, #120]\t@ 0x78\n-\tvldr\td19, [r3, #712]\t@ 0x2c8\n-\tmov.w\tsl, #1\n-\tldr\tr3, [pc, #776]\t@ (5458 <__gridxc_vdwxc_MOD_vdw_decusp+0x5d0>)\n-\tmov\tr8, r9\n-\tstr.w\tfp, [sp, #128]\t@ 0x80\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tr9, sl, #7424\t@ 0x1d00\n+\tadd\tr1, sp, #144\t@ 0x90\n+\tadd.w\tr9, r9, #24\n+\tstr\tr1, [sp, #28]\n+\tvldr\td4, [r3, #696]\t@ 0x2b8\n+\tadd\tr1, sp, #704\t@ 0x2c0\n+\tldr\tr3, [pc, #336]\t@ (5280 <__gridxc_vdwxc_MOD_vdw_decusp+0x40c>)\n+\tadd\tr4, sp, #160\t@ 0xa0\n+\tstr\tr1, [sp, #92]\t@ 0x5c\n+\tadd\tr1, sp, #680\t@ 0x2a8\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #84]\t@ 0x54\n-\tadd.w\tr7, r3, #7424\t@ 0x1d00\n-\tadd\tr3, sp, #160\t@ 0xa0\n-\tadds\tr7, #24\n-\tstr\tr3, [sp, #44]\t@ 0x2c\n-\tmov\tr6, r7\n-\tadd\tr3, sp, #720\t@ 0x2d0\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tadd\tr3, sp, #696\t@ 0x2b8\n-\tstr\tr3, [sp, #48]\t@ 0x30\n-\tadd\tr3, sp, #944\t@ 0x3b0\n-\tstr\tr3, [sp, #108]\t@ 0x6c\n-\tadd\tr3, sp, #936\t@ 0x3a8\n-\tstr\tr3, [sp, #80]\t@ 0x50\n-\tadd\tr3, sp, #464\t@ 0x1d0\n-\tstr\tr3, [sp, #100]\t@ 0x64\n-\tadd\tr3, sp, #456\t@ 0x1c8\n-\tstr\tr3, [sp, #52]\t@ 0x34\n-\taddw\tr3, fp, #2120\t@ 0x848\n-\tmov\tfp, r4\n-\tstrd\tr3, r5, [sp, #112]\t@ 0x70\n-\tvmov\ts15, sl\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tstr\tr1, [sp, #32]\n+\tstrd\tsl, r9, [sp, #72]\t@ 0x48\n+\tadd\tr1, sp, #928\t@ 0x3a0\n+\tvldr\td8, [pc, #252]\t@ 5240 <__gridxc_vdwxc_MOD_vdw_decusp+0x3cc>\n+\tmov\tr9, r2\n+\tstr\tr1, [sp, #96]\t@ 0x60\n+\tadd\tr1, sp, #920\t@ 0x398\n+\tstr\tr1, [sp, #68]\t@ 0x44\n+\tadd\tr1, sp, #448\t@ 0x1c0\n+\tstr\tr1, [sp, #88]\t@ 0x58\n+\tadd\tr1, sp, #440\t@ 0x1b8\n+\tstr\tr1, [sp, #36]\t@ 0x24\n+\taddw\tr1, r3, #2120\t@ 0x848\n+\tstrd\tr1, r7, [sp, #100]\t@ 0x64\n+\tmov\tr7, fp\n+\tmov\tfp, r3\n+\tstrd\tr6, r8, [sp, #108]\t@ 0x6c\n+\tstr\tr4, [sp, #116]\t@ 0x74\n+\tvmov\ts15, r9\n+\tldr\tr3, [sp, #28]\n \tvcvt.f64.s32\td9, s15\n-\tvmul.f64\td9, d9, d19\n+\tvmul.f64\td9, d9, d4\n \tvstr\td9, [r3, #-8]\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #64]\t@ 0x40\n \tldr.w\tr4, [r3, #448]\t@ 0x1c0\n \tcmp\tr4, #0\n-\tbeq.w\t5470 <__gridxc_vdwxc_MOD_vdw_decusp+0x5e8>\n-\tvldr\td16, [pc, #624]\t@ 5418 <__gridxc_vdwxc_MOD_vdw_decusp+0x590>\n-\tvcmpe.f64\td9, d16\n+\tbeq.w\t540c <__gridxc_vdwxc_MOD_vdw_decusp+0x598>\n+\tvcmpe.f64\td9, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t525c <__gridxc_vdwxc_MOD_vdw_decusp+0x3d4>\n-\tldr\tr0, [sp, #80]\t@ 0x50\n+\tblt.w\t5290 <__gridxc_vdwxc_MOD_vdw_decusp+0x41c>\n+\tldr\tr0, [sp, #68]\t@ 0x44\n \tmov.w\tr2, #7200\t@ 0x1c20\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [pc, #664]\t@ (545c <__gridxc_vdwxc_MOD_vdw_decusp+0x5d4>)\n+\tldr\tr3, [pc, #228]\t@ (5284 <__gridxc_vdwxc_MOD_vdw_decusp+0x410>)\n \tvmul.f64\td9, d9, d9\n-\tvldr\td18, [pc, #600]\t@ 5420 <__gridxc_vdwxc_MOD_vdw_decusp+0x598>\n+\tvldr\td5, [pc, #164]\t@ 5248 <__gridxc_vdwxc_MOD_vdw_decusp+0x3d4>\n \tadd\tr3, pc\n-\tldrd\tr4, r0, [sp, #80]\t@ 0x50\n-\tvldr\td19, [r3, #712]\t@ 0x2c8\n+\tldr\tr5, [sp, #76]\t@ 0x4c\n+\tldrd\tr4, r0, [sp, #68]\t@ 0x44\n+\tvldr\td4, [r3, #696]\t@ 0x2b8\n \tadd.w\tr1, r0, #8\n-\tvmul.f64\td18, d19, d18\n-\tvmul.f64\td18, d18, d9\n+\tvmul.f64\td5, d4, d5\n+\tvmul.f64\td5, d5, d9\n \tmov\tr2, r4\n \tmov\tr3, r0\n-\tvldmia\tr2!, {d17}\n-\tvldr\td16, [r3]\n-\tvfms.f64\td16, d17, d18\n-\tvstmia\tr3!, {d16}\n+\tvldmia\tr2!, {d6}\n+\tvldr\td7, [r3]\n+\tvmls.f64\td7, d5, d6\n+\tvstmia\tr3!, {d7}\n \tcmp\tr1, r3\n-\tbne.n\t51e4 <__gridxc_vdwxc_MOD_vdw_decusp+0x35c>\n+\tbne.n\t51c2 <__gridxc_vdwxc_MOD_vdw_decusp+0x34e>\n \tadds\tr1, #248\t@ 0xf8\n \tadds\tr0, #240\t@ 0xf0\n \tadds\tr4, #240\t@ 0xf0\n-\tcmp\tr6, r1\n-\tbne.n\t51e0 <__gridxc_vdwxc_MOD_vdw_decusp+0x358>\n-\tadd.w\tsl, sl, #1\n+\tcmp\tr5, r1\n+\tbne.n\t51be <__gridxc_vdwxc_MOD_vdw_decusp+0x34a>\n+\tadd.w\tr9, r9, #1\n \tmovw\tr3, #2049\t@ 0x801\n-\tcmp\tsl, r3\n-\tbne.n\t5188 <__gridxc_vdwxc_MOD_vdw_decusp+0x300>\n-\tldr\tr0, [pc, #592]\t@ (5460 <__gridxc_vdwxc_MOD_vdw_decusp+0x5d8>)\n-\tmov\tr9, r8\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tmov\tr4, fp\n+\tcmp\tr9, r3\n+\tbne.n\t5166 <__gridxc_vdwxc_MOD_vdw_decusp+0x2f2>\n+\tldr\tr0, [pc, #152]\t@ (5288 <__gridxc_vdwxc_MOD_vdw_decusp+0x414>)\n+\tmov\tfp, r7\n+\tldr.w\tsl, [sp, #72]\t@ 0x48\n+\tmov\tlr, fp\n \tadd\tr0, pc\n-\tldr\tr5, [sp, #116]\t@ 0x74\n-\tldr.w\tlr, [sp, #124]\t@ 0x7c\n-\tadd.w\tr6, r0, #240\t@ 0xf0\n-\tldr.w\tr8, [sp, #120]\t@ 0x78\n-\tadd.w\tr1, r3, #248\t@ 0xf8\n-\tadd.w\tr7, r3, #7200\t@ 0x1c20\n+\tldr\tr7, [sp, #104]\t@ 0x68\n+\tldrd\tr6, r8, [sp, #108]\t@ 0x6c\n+\tadd.w\tr5, r0, #240\t@ 0xf0\n+\tldr\tr4, [sp, #116]\t@ 0x74\n+\tadd.w\tr1, sl, #248\t@ 0xf8\n+\tadd.w\tip, sl, #7200\t@ 0x1c20\n \tadds\tr0, #16\n-\tmov\tip, r9\n \tmov\tr2, r0\n-\tmov\tr3, r6\n+\tmov\tr3, r5\n \tldrd\tsl, fp, [r3], #8\n \tadds\tr2, #240\t@ 0xf0\n \tstrd\tsl, fp, [r2, #-248]\t@ 0xf8\n \tcmp\tr1, r3\n-\tbne.n\t5236 <__gridxc_vdwxc_MOD_vdw_decusp+0x3ae>\n-\tadds\tr6, #240\t@ 0xf0\n+\tbne.n\t5212 <__gridxc_vdwxc_MOD_vdw_decusp+0x39e>\n+\tadds\tr5, #240\t@ 0xf0\n \tadds\tr0, #8\n \tadds\tr1, #248\t@ 0xf8\n-\tcmp\tr7, r6\n-\tbne.n\t5232 <__gridxc_vdwxc_MOD_vdw_decusp+0x3aa>\n-\tldr\tr3, [pc, #532]\t@ (5464 <__gridxc_vdwxc_MOD_vdw_decusp+0x5dc>)\n+\tcmp\tip, r5\n+\tbne.n\t520e <__gridxc_vdwxc_MOD_vdw_decusp+0x39a>\n+\tldr\tr3, [pc, #96]\t@ (528c <__gridxc_vdwxc_MOD_vdw_decusp+0x418>)\n \tmovs\tr2, #1\n-\tmov\tr9, ip\n+\tmov\tfp, lr\n \tadd\tr3, pc\n-\tstr.w\tr2, [r3, #736]\t@ 0x2e0\n-\tb.n\t4f32 <__gridxc_vdwxc_MOD_vdw_decusp+0xaa>\n-\tldr.w\tr9, [pc, #520]\t@ 5468 <__gridxc_vdwxc_MOD_vdw_decusp+0x5e0>\n-\tldr\tr3, [pc, #520]\t@ (546c <__gridxc_vdwxc_MOD_vdw_decusp+0x5e4>)\n-\tldr\tr5, [sp, #108]\t@ 0x6c\n-\tadd\tr9, pc\n-\tldr\tr7, [sp, #80]\t@ 0x50\n+\tstr.w\tr2, [r3, #720]\t@ 0x2d0\n+\tb.n\t4f0e <__gridxc_vdwxc_MOD_vdw_decusp+0x9a>\n+\t...\n+\t.word\t0x40590000\n+\t.word\t0x54442d18\n+\t.word\t0x401921fb\n+\t.word\t0x000003a6\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000392\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000386\n+ R_ARM_REL32\t.data\n+\t.word\t0x00000382\n+ R_ARM_REL32\t.LC21\n+\t.word\t0x00000378\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000596\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000200\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000017c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000440\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000438\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000160\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000146\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000000da\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000366\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000058\n+ R_ARM_REL32\t.bss\n+\tldr.w\tsl, [pc, #532]\t@ 54a8 <__gridxc_vdwxc_MOD_vdw_decusp+0x634>\n+\tldr\tr3, [pc, #532]\t@ (54ac <__gridxc_vdwxc_MOD_vdw_decusp+0x638>)\n+\tldr\tr6, [sp, #68]\t@ 0x44\n+\tadd\tsl, pc\n+\tldr.w\tr8, [sp, #96]\t@ 0x60\n \tadd\tr3, pc\n-\tstrd\tr5, r7, [sp, #68]\t@ 0x44\n-\tmov\tr5, r8\n+\tstr.w\tr9, [sp, #120]\t@ 0x78\n+\tmov\tr9, r7\n \tadd.w\tr3, r3, #2144\t@ 0x860\n-\tstr.w\tsl, [sp, #132]\t@ 0x84\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tstrd\tr8, r6, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #40]\t@ 0x28\n \tmovs\tr3, #2\n-\tstr.w\tfp, [sp, #136]\t@ 0x88\n-\tstr\tr3, [sp, #36]\t@ 0x24\n-\tadd\tr3, sp, #152\t@ 0x98\n-\tstr\tr6, [sp, #140]\t@ 0x8c\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tadd.w\tr3, r9, #476\t@ 0x1dc\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tvmov.i32\td8, #0\t@ 0x00000000\n-\tmovs\tr6, #1\n-\tsubw\tr4, r5, #3592\t@ 0xe08\n+\tstr.w\tfp, [sp, #124]\t@ 0x7c\n+\tstr\tr3, [sp, #20]\n+\tadd\tr3, sp, #136\t@ 0x88\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tadd.w\tr3, sl, #696\t@ 0x2b8\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n+\tldrd\tfp, r7, [sp, #52]\t@ 0x34\n+\tmovs\tr5, #1\n+\tldr\tr3, [sp, #20]\n+\tmov\tr8, r7\n \tsubs\tr3, #1\n \tstr\tr3, [sp, #24]\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tstr\tr3, [sp, #28]\n-\tldr\tr3, [sp, #72]\t@ 0x48\n-\tstr\tr3, [sp, #20]\n-\tsubw\tr3, r5, #3580\t@ 0xdfc\n-\tstr\tr3, [sp, #40]\t@ 0x28\n-\tldr\tr3, [sp, #56]\t@ 0x38\n-\tmov.w\tsl, #1\n-\tldr\tr2, [sp, #24]\n-\tmovw\tfp, #769\t@ 0x301\n-\tldr.w\tr1, [r9, #504]\t@ 0x1f8\n-\tldr.w\tr0, [r9, #456]\t@ 0x1c8\n-\tvld1.32\t{d16}, [r3]\n-\tldr\tr3, [sp, #40]\t@ 0x28\n-\tvstr\td8, [r3]\n-\tldr.w\tr3, [r9, #508]\t@ 0x1fc\n-\tstr.w\tsl, [r4, #28]\n-\tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r9, #496]\t@ 0x1f0\n-\tstrh.w\tfp, [r4, #16]\n-\tsubs\tr2, r6, r2\n-\tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r9, #492]\t@ 0x1ec\n-\tmla\tr3, r1, r2, r3\n-\tvmov.32\tr1, d16[1]\n-\tldr.w\tr2, [r9, #484]\t@ 0x1e4\n-\tadd.w\tr7, r0, r3, lsl #3\n-\tsubw\tr3, r5, #3572\t@ 0xdf4\n-\tldr.w\tr0, [r9, #488]\t@ 0x1e8\n-\trsb\tr2, r2, #1\n-\tnegs\tr1, r1\n-\tstr\tr7, [sp, #32]\n-\tadd\tr2, r0\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tstr\tr2, [r4, #32]\n+\tldr\tr6, [sp, #24]\n+\tsubw\tr1, r9, #3580\t@ 0xdfc\n+\tldr.w\tr3, [sl, #504]\t@ 0x1f8\n+\tmovs\tr7, #0\n+\tldr.w\tr2, [sl, #500]\t@ 0x1f4\n+\tsubs\tr0, r6, r3\n+\tldr.w\tr3, [sl, #492]\t@ 0x1ec\n+\tldr.w\tr4, [sl, #480]\t@ 0x1e0\n+\tsubs\tr3, r5, r3\n+\tmul.w\tr0, r2, r0\n+\tldr.w\tr2, [sl, #488]\t@ 0x1e8\n+\trsb\tr4, r4, #1\n+\tmla\tr0, r2, r3, r0\n+\tldr.w\tr2, [sl, #452]\t@ 0x1c4\n+\tsubw\tr3, r9, #3592\t@ 0xe08\n+\tadd.w\tr2, r2, r0, lsl #3\n+\tldr.w\tr0, [sl, #484]\t@ 0x1e4\n+\tstr\tr2, [sp, #16]\n+\tldr.w\tr2, [sl, #476]\t@ 0x1dc\n+\tadd\tr4, r0\n+\tldr.w\tr0, [sl, #472]\t@ 0x1d8\n+\tstr\tr0, [r3, #20]\n+\tstrd\tr7, r7, [r1]\n+\tmovs\tr1, #1\n+\tstr\tr2, [r3, #24]\n+\tnegs\tr2, r2\n+\tstr\tr2, [r3, #4]\n+\tldr\tr2, [sp, #16]\n+\tstr\tr4, [r3, #32]\n+\tstr\tr2, [r3, #0]\n \tmovs\tr2, #8\n-\tstr\tr2, [r4, #8]\n-\tvst1.32\t{d16}, [r3]\n-\tstr\tr1, [r4, #4]\n-\tstr\tr7, [r4, #0]\n+\tstr\tr1, [r3, #28]\n+\tmovw\tr1, #769\t@ 0x301\n+\tstr\tr2, [r3, #8]\n+\tstrh\tr1, [r3, #16]\n+\tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [sp, #24]\n-\tmov\tr7, r0\n-\tldr.w\tr0, [r9, #636]\t@ 0x27c\n-\tldr.w\tr1, [r9, #632]\t@ 0x278\n-\tadd.w\tr3, r9, #604\t@ 0x25c\n-\tsubs\tr0, r2, r0\n-\tsubw\tip, r5, #3352\t@ 0xd18\n-\tmovs\tr2, #8\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r9, #624]\t@ 0x270\n-\tmul.w\tr0, r1, r0\n-\tldr.w\tr1, [r9, #620]\t@ 0x26c\n-\tsubs\tr3, r6, r3\n-\tvmov.32\tlr, d16[1]\n-\tmla\tr0, r1, r3, r0\n-\tldr.w\tr1, [r9, #584]\t@ 0x248\n-\tldr.w\tr3, [r9, #612]\t@ 0x264\n-\trsb\tlr, lr, #0\n-\tadd.w\tr8, r1, r0, lsl #3\n-\tsubw\tr1, r5, #3340\t@ 0xd0c\n-\tsub.w\tr3, sl, r3\n-\tldr\tr0, [sp, #48]\t@ 0x30\n-\tvstr\td8, [r1]\n-\tsubw\tr1, r5, #3332\t@ 0xd04\n-\tstr.w\tr2, [ip, #8]\n-\tldr.w\tr2, [r9, #616]\t@ 0x268\n-\tstr.w\tsl, [ip, #28]\n+\tldr.w\tr1, [sl, #624]\t@ 0x270\n+\tmov\tr4, r0\n+\tldr.w\tr0, [sl, #620]\t@ 0x26c\n+\tsubs\tr1, r6, r1\n+\tldr.w\tr3, [sl, #612]\t@ 0x264\n+\tldr.w\tr6, [sl, #572]\t@ 0x23c\n+\tsubw\tip, r9, #3340\t@ 0xd0c\n+\tsubs\tr3, r5, r3\n+\tldr.w\tr2, [sl, #604]\t@ 0x25c\n+\tmul.w\tr1, r0, r1\n+\tldr.w\tr0, [sl, #608]\t@ 0x260\n+\tmla\tr1, r0, r3, r1\n+\tldr.w\tr3, [sl, #600]\t@ 0x258\n+\tsubw\tr0, r9, #3352\t@ 0xd18\n+\trsb\tr3, r3, #1\n+\tadd.w\tr6, r6, r1, lsl #3\n+\tldr.w\tr1, [sl, #596]\t@ 0x254\n \tadd\tr3, r2\n-\tstrh.w\tfp, [ip, #16]\n-\tstr.w\tr3, [ip, #32]\n-\tvst1.32\t{d16}, [r1]\n-\tstrd\tr8, lr, [ip]\n+\tldr.w\tr2, [sl, #592]\t@ 0x250\n+\tstr\tr2, [r0, #20]\n+\tmovs\tr2, #8\n+\tstrd\tr7, r7, [ip]\n+\tmovw\tr7, #769\t@ 0x301\n+\tstr\tr2, [r0, #8]\n+\tstrh\tr7, [r0, #16]\n+\tmovs\tr7, #1\n+\tstr\tr1, [r0, #24]\n+\tstrd\tr7, r3, [r0, #28]\n+\tnegs\tr3, r1\n+\tstrd\tr6, r3, [r0]\n+\tldr\tr0, [sp, #32]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tstr\tr2, [sp, #8]\n-\tmov\tsl, r0\n-\tldr\tr2, [sp, #20]\n-\tmov\tr1, r7\n-\tstr\tr2, [sp, #4]\n-\tldr\tr2, [sp, #64]\t@ 0x40\n-\tldr\tr3, [sp, #60]\t@ 0x3c\n-\tstr\tr2, [sp, #0]\n+\tldr\tr3, [sp, #28]\n+\tstrd\tr8, r3, [sp, #4]\n \tmov\tr2, r0\n-\tadd.w\tr0, r9, #712\t@ 0x2c8\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmov\tr7, r0\n+\tstr\tr3, [sp, #0]\n+\tmov\tr1, r4\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr0, [sp, #44]\t@ 0x2c\n \tbl\t0 <__gridxc_interpolation_MOD_evaluate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_evaluate_spline_dx\n-\tldr\tr3, [sp, #32]\n-\tcmp\tr3, r7\n-\tbeq.n\t53ba <__gridxc_vdwxc_MOD_vdw_decusp+0x532>\n-\tmov\tr0, r7\n+\tldr\tr2, [sp, #16]\n+\tcmp\tr2, r4\n+\tbeq.n\t53ca <__gridxc_vdwxc_MOD_vdw_decusp+0x556>\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tcmp\tr8, sl\n-\tbeq.n\t53c4 <__gridxc_vdwxc_MOD_vdw_decusp+0x53c>\n-\tmov\tr0, sl\n+\tcmp\tr6, r7\n+\tbeq.n\t53d4 <__gridxc_vdwxc_MOD_vdw_decusp+0x560>\n+\tmov\tr0, r7\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr1, [sp, #28]\n-\tadds\tr6, #1\n-\tldr\tr0, [sp, #20]\n-\tadds\tr1, #240\t@ 0xf0\n-\tstr\tr1, [sp, #28]\n-\tldrd\tr2, r3, [r0], #8\n-\tstr\tr0, [sp, #20]\n-\tstrd\tr2, r3, [r1, #-248]\t@ 0xf8\n-\tldr\tr3, [sp, #36]\t@ 0x24\n-\tcmp\tr6, r3\n-\tbne.w\t52ac <__gridxc_vdwxc_MOD_vdw_decusp+0x424>\n-\tldr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr3, [sp, #36]\t@ 0x24\n+\tadd.w\tfp, fp, #240\t@ 0xf0\n+\tadds\tr5, #1\n+\tldrd\tr2, r3, [r8], #8\n+\tstrd\tr2, r3, [fp, #-248]\t@ 0xf8\n+\tldr\tr3, [sp, #20]\n+\tcmp\tr5, r3\n+\tbne.w\t52d0 <__gridxc_vdwxc_MOD_vdw_decusp+0x45c>\n+\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr3, [sp, #20]\n \tadds\tr2, #240\t@ 0xf0\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #52]\t@ 0x34\n \tadds\tr3, #1\n \tcmp\tr3, #32\n-\tstr\tr3, [sp, #36]\t@ 0x24\n+\tstr\tr3, [sp, #20]\n \tadd.w\tr2, r2, #8\n-\tstr\tr2, [sp, #68]\t@ 0x44\n-\tbne.w\t528e <__gridxc_vdwxc_MOD_vdw_decusp+0x406>\n-\tldrd\tsl, fp, [sp, #132]\t@ 0x84\n-\tmov\tr8, r5\n-\tldr\tr6, [sp, #140]\t@ 0x8c\n-\tb.n\t51c0 <__gridxc_vdwxc_MOD_vdw_decusp+0x338>\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x0000001e\n-\t.word\t0x00000000\n-\t.word\t0x40590000\n-\t.word\t0x54442d18\n-\t.word\t0x401921fb\n-\t.word\t0x00000566\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000534\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000540\n- R_ARM_REL32\t.data\n-\t.word\t0x0000053e\n- R_ARM_REL32\t.LC21\n-\t.word\t0x0000052e\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000758\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003b6\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000338\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000060c\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000031c\n- R_ARM_REL32\t.rodata\n-\t.word\t0x0000031a\n- R_ARM_REL32\t.bss\n-\t.word\t0x000005e6\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000028e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000052e\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000020c\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000200\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000200\n- R_ARM_REL32\t.rodata\n-\tldr\tr3, [sp, #128]\t@ 0x80\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tbne.w\t52c2 <__gridxc_vdwxc_MOD_vdw_decusp+0x44e>\n+\tmov\tr7, r9\n+\tldrd\tr9, fp, [sp, #120]\t@ 0x78\n+\tb.n\t519c <__gridxc_vdwxc_MOD_vdw_decusp+0x328>\n+\tadd.w\tr5, fp, #16\n \tmov\tr2, r4\n \tmov\tr1, r4\n-\tstr\tr4, [sp, #0]\n-\tadd.w\tr5, r3, #16\n-\tadds\tr3, #40\t@ 0x28\n \tmov\tr0, r5\n+\tadd.w\tr3, fp, #40\t@ 0x28\n+\tstr\tr4, [sp, #0]\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #112]\t@ 0x70\n-\tmovw\tr7, #769\t@ 0x301\n+\tsubw\tr6, r7, #3340\t@ 0xd0c\n+\tldr\tr3, [sp, #100]\t@ 0x64\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tvmov.i32\td16, #0\t@ 0x00000000\n+\tmov\tr0, r5\n+\tsubw\tr5, r7, #3352\t@ 0xd18\n \tstrd\tr4, r4, [sp, #4]\n-\tmov\tr3, r4\n \tstr\tr4, [sp, #0]\n-\tsubw\tr2, r8, #3340\t@ 0xd0c\n-\tsubw\tr4, r8, #3352\t@ 0xd18\n-\tsubw\tlr, r8, #3332\t@ 0xd04\n-\tmov\tr0, r5\n-\tmovs\tr5, #8\n-\tvstr\td16, [r2]\n-\tmov.w\tip, #4294967295\t@ 0xffffffff\n-\tstr\tr5, [r4, #8]\n-\tldr\tr5, [sp, #76]\t@ 0x4c\n-\tstrh\tr7, [r4, #16]\n-\tadds\tr5, #176\t@ 0xb0\n-\tvst1.32\t{d10-d11}, [lr]\n-\tldrd\tr1, r2, [sp, #44]\t@ 0x2c\n-\tstrd\tr5, ip, [r4]\n+\tmov.w\tip, #8\n+\tmov\tr3, r4\n+\tstr.w\tip, [r5, #20]\n+\tstrd\tr4, r4, [r6]\n+\tmovs\tr6, #30\n+\tstr\tr6, [r5, #32]\n+\tmovs\tr4, #1\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tldrd\tr1, r2, [sp, #28]\n+\tadds\tr6, #176\t@ 0xb0\n+\tstr.w\tip, [r5, #8]\n+\tstr\tr6, [r5, #0]\n+\tmov.w\tr6, #4294967295\t@ 0xffffffff\n+\tstrd\tr4, r4, [r5, #24]\n+\tstr\tr6, [r5, #4]\n+\tmovw\tr6, #769\t@ 0x301\n+\tstrh\tr6, [r5, #16]\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tldr\tr5, [sp, #76]\t@ 0x4c\n-\tmovs\tr3, #1\n-\tstr.w\tr3, [r5, #448]\t@ 0x1c0\n-\tb.n\t51a6 <__gridxc_vdwxc_MOD_vdw_decusp+0x31e>\n-\tldr\tr3, [pc, #64]\t@ (5514 <__gridxc_vdwxc_MOD_vdw_decusp+0x68c>)\n+\tldr\tr6, [sp, #64]\t@ 0x40\n+\tstr.w\tr4, [r6, #448]\t@ 0x1c0\n+\tb.n\t5184 <__gridxc_vdwxc_MOD_vdw_decusp+0x310>\n+\tldr\tr3, [pc, #60]\t@ (54b0 <__gridxc_vdwxc_MOD_vdw_decusp+0x63c>)\n \tmovs\tr1, #40\t@ 0x28\n-\tldr\tr0, [pc, #64]\t@ (5518 <__gridxc_vdwxc_MOD_vdw_decusp+0x690>)\n+\tldr\tr0, [pc, #60]\t@ (54b4 <__gridxc_vdwxc_MOD_vdw_decusp+0x640>)\n \tadd\tr0, pc\n-\tldr\tr3, [r7, r3]\n+\tldr\tr3, [r5, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t5118 <__gridxc_vdwxc_MOD_vdw_decusp+0x290>\n-\tbl\t12e0 <__gridxc_vdwxc_MOD_set_phi_table>\n-\tb.n\t510a <__gridxc_vdwxc_MOD_vdw_decusp+0x282>\n-\tadd\tr6, sp, #192\t@ 0xc0\n-\tldr.w\tr0, [r8]\n-\tmov\tr4, r6\n-\tldr.w\tr1, [r8, #4]\n-\tldr.w\tr2, [r8, #8]\n+\tb.n\t50fc <__gridxc_vdwxc_MOD_vdw_decusp+0x288>\n+\tbl\t1388 <__gridxc_vdwxc_MOD_set_phi_table>\n+\tb.n\t50ee <__gridxc_vdwxc_MOD_vdw_decusp+0x27a>\n+\tadd\tr7, sp, #176\t@ 0xb0\n+\tldr\tr0, [r6, #0]\n+\tmov\tr5, r7\n+\tldr\tr1, [r6, #4]\n+\tldr\tr2, [r6, #8]\n \tvmul.f64\td8, d9, d9\n-\tldr.w\tr3, [r8, #12]\n-\tstmia\tr4!, {r0, r1, r2, r3}\n-\tldr.w\tr0, [r8, #16]\n-\tldr.w\tr1, [r8, #20]\n-\tstmia\tr4!, {r0, r1}\n-\tb.n\t4f84 <__gridxc_vdwxc_MOD_vdw_decusp+0xfc>\n+\tldr\tr3, [r6, #12]\n+\tstmia\tr5!, {r0, r1, r2, r3}\n+\tldr\tr0, [r6, #16]\n+\tldr\tr1, [r6, #20]\n+\tstmia\tr5!, {r0, r1}\n+\tb.n\t4f62 <__gridxc_vdwxc_MOD_vdw_decusp+0xee>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop\n+\t.word\t0x0000020c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000020a\n+ R_ARM_REL32\t.rodata\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000003c\n+\t.word\t0x00000038\n R_ARM_REL32\t.LC55\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "vv_vdwxc.F90.o", "source2": "vv_vdwxc.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 15396 (bytes into file)\n+ Start of section headers: 15872 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x3c24:\n+There are 12 section headers, starting at offset 0x3e00:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 0027e0 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 0036ac 000510 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 002818 000008 00 WA 0 0 4\n- [ 4] .bss NOBITS 00000000 002820 000650 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 002820 0001e3 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 002a08 000050 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 002a58 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 002a58 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 002a8c 0006a0 10 10 62 4\n- [10] .strtab STRTAB 00000000 00312c 00057d 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 003bbc 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 002980 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 003888 000510 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0029b8 000008 00 WA 0 0 4\n+ [ 4] .bss NOBITS 00000000 0029c0 000648 00 WA 0 0 8\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0029c0 0001e3 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 002ba8 000050 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 002bf8 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 002bf8 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 002c28 0006e0 10 10 66 4\n+ [10] .strtab STRTAB 00000000 003308 00057d 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 003d98 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,109 +1,113 @@\n \n-Symbol table '.symtab' contains 106 entries:\n+Symbol table '.symtab' contains 110 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 3 .data\n 2: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n- 3: 00000001 308 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_set_kmesh.part.0\n+ 3: 00000001 260 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_set_kmesh.part.0\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 5: 00000100 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 000000f0 0 NOTYPE LOCAL DEFAULT 1 $d\n 6: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 7: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC5\n- 8: 00000134 0 NOTYPE LOCAL DEFAULT 1 $t\n- 9: 00000135 200 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0\n- 10: 000001e0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 8: 00000104 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 9: 00000105 200 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0\n+ 10: 000001b0 0 NOTYPE LOCAL DEFAULT 1 $d\n 11: 00000020 0 NOTYPE LOCAL DEFAULT 5 .LC6\n 12: 0000004c 0 NOTYPE LOCAL DEFAULT 5 .LC10\n 13: 00000068 0 NOTYPE LOCAL DEFAULT 5 .LC12\n 14: 00000084 0 NOTYPE LOCAL DEFAULT 5 .LC13\n 15: 000000a4 0 NOTYPE LOCAL DEFAULT 5 .LC14\n- 16: 000001fc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 17: 000001fd 3180 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_set_phi_table.part.0\n- 18: 000004f8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 19: 00000584 0 NOTYPE LOCAL DEFAULT 1 $t\n- 20: 000007b8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 21: 000007d0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 00000d10 0 NOTYPE LOCAL DEFAULT 1 $d\n- 23: 00000d3c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 24: 00000e58 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 16: 000001cc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 17: 000001cd 3168 FUNC LOCAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_set_phi_table.part.0\n+ 18: 000004e8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00000578 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 20: 00000798 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 000007b8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 22: 00000b48 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 23: 00000b6c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 24: 00000e10 0 NOTYPE LOCAL DEFAULT 1 $d\n 25: 000000c4 0 NOTYPE LOCAL DEFAULT 5 .LC18\n 26: 00000100 0 NOTYPE LOCAL DEFAULT 5 .LC19\n 27: 00000108 0 NOTYPE LOCAL DEFAULT 5 .LC20\n 28: 00000114 0 NOTYPE LOCAL DEFAULT 5 .LC21\n 29: 0000011c 0 NOTYPE LOCAL DEFAULT 5 .LC22\n 30: 00000148 0 NOTYPE LOCAL DEFAULT 5 .LC23\n 31: 00000174 0 NOTYPE LOCAL DEFAULT 5 .LC24\n- 32: 00000e68 0 NOTYPE LOCAL DEFAULT 1 $t\n- 33: 000010c0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 34: 00001104 0 NOTYPE LOCAL DEFAULT 1 $t\n- 35: 000014d8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 36: 0000150c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 37: 00001f80 0 NOTYPE LOCAL DEFAULT 1 $d\n- 38: 0000019c 0 NOTYPE LOCAL DEFAULT 5 .LC25\n- 39: 00001ff0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 40: 00002098 0 NOTYPE LOCAL DEFAULT 1 $d\n- 41: 000001bc 0 NOTYPE LOCAL DEFAULT 5 .LC26\n- 42: 000020cc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 43: 00002440 0 NOTYPE LOCAL DEFAULT 1 $d\n- 44: 00002464 0 NOTYPE LOCAL DEFAULT 1 $t\n- 45: 000027bc 0 NOTYPE LOCAL DEFAULT 1 $d\n- 46: 000027d0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 47: 000027d8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 48: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 49: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 50: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n- 51: 00000000 4 OBJECT LOCAL DEFAULT 3 first_call.9\n- 52: 00000004 4 OBJECT LOCAL DEFAULT 3 first_call.4\n- 53: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 54: 00000190 392 OBJECT LOCAL DEFAULT 4 pkf.8\n- 55: 00000318 392 OBJECT LOCAL DEFAULT 4 d2pkfdkf2.7\n- 56: 000004a0 200 OBJECT LOCAL DEFAULT 4 pkg.6\n- 57: 00000568 200 OBJECT LOCAL DEFAULT 4 d2pkgdkg2.5\n- 58: 00000630 8 OBJECT LOCAL DEFAULT 4 akf.3\n- 59: 00000638 8 OBJECT LOCAL DEFAULT 4 akg.2\n- 60: 00000640 8 OBJECT LOCAL DEFAULT 4 bkf.1\n- 61: 00000648 8 OBJECT LOCAL DEFAULT 4 bkg.0\n- 62: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_mesh\n- 63: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_get_mesh\n- 64: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 65: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 66: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 67: 00000000 0 NOTYPE GLOBAL DEFAULT UND pow\n- 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n- 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n- 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_radfft_MOD_radfft\n- 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n- 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_dx\n- 75: 00000e69 4488 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n- 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n- 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n- 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n- 79: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 81: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_x\n- 82: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_open\n- 83: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n- 84: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_real_write\n- 85: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_array_write\n- 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n- 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_close\n- 88: 00001ff1 220 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n- 89: 000020cd 1382 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n- 90: 00002635 412 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n- 91: 000027d1 16 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n- 92: 00000070 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phir\n- 93: 000000b0 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phik\n- 94: 00000188 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phi_table_set\n- 95: 0000016c 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_nk\n- 96: 00000060 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kmesh_set\n- 97: 00000170 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kmax\n- 98: 00000038 40 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kgmesh\n- 99: 00000000 56 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kfmesh\n- 100: 00000064 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kcut_set\n- 101: 00000180 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kcut\n- 102: 00000068 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_dr\n- 103: 00000178 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_dk\n- 104: 000000f0 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_d2phidr2\n- 105: 00000130 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_d2phidk2\n+ 32: 00000e2c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 33: 00001088 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 34: 000010cc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 35: 00001488 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 36: 000014b4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 37: 00001a38 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 38: 00001a40 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 39: 00002098 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 40: 000020d8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 41: 0000019c 0 NOTYPE LOCAL DEFAULT 5 .LC25\n+ 42: 00002208 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 43: 000001bc 0 NOTYPE LOCAL DEFAULT 5 .LC26\n+ 44: 0000223c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 45: 000025b8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 46: 000025dc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 47: 000027c8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 48: 000027d0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 49: 00002958 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 50: 0000296c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 51: 00002978 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 52: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 53: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 54: 00000000 0 NOTYPE LOCAL DEFAULT 3 $d\n+ 55: 00000000 4 OBJECT LOCAL DEFAULT 3 first_call.9\n+ 56: 00000004 4 OBJECT LOCAL DEFAULT 3 first_call.4\n+ 57: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 58: 00000188 392 OBJECT LOCAL DEFAULT 4 pkf.8\n+ 59: 00000310 392 OBJECT LOCAL DEFAULT 4 d2pkfdkf2.7\n+ 60: 00000498 200 OBJECT LOCAL DEFAULT 4 pkg.6\n+ 61: 00000560 200 OBJECT LOCAL DEFAULT 4 d2pkgdkg2.5\n+ 62: 00000628 8 OBJECT LOCAL DEFAULT 4 akf.3\n+ 63: 00000630 8 OBJECT LOCAL DEFAULT 4 akg.2\n+ 64: 00000638 8 OBJECT LOCAL DEFAULT 4 bkf.1\n+ 65: 00000640 8 OBJECT LOCAL DEFAULT 4 bkg.0\n+ 66: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_set_mesh\n+ 67: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_mesh1d_MOD_get_mesh\n+ 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND pow\n+ 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_alloc_MOD_realloc_d3\n+ 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_pack\n+ 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_radfft_MOD_radfft\n+ 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_internal_unpack\n+ 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_dx\n+ 79: 00000e2d 4910 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_theta\n+ 80: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n+ 81: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n+ 82: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n+ 83: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 84: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 85: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_interpolation_MOD_generate_spline_x\n+ 86: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_open\n+ 87: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 88: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_real_write\n+ 89: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_array_write\n+ 90: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 91: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_close\n+ 92: 0000215d 224 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut\n+ 93: 0000223d 1428 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_phi\n+ 94: 000027d1 412 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh\n+ 95: 0000296d 20 FUNC GLOBAL DEFAULT 1 __gridxc_vv_vdwxc_MOD_vv_vdw_beta\n+ 96: 00000070 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phir\n+ 97: 000000ac 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phik\n+ 98: 00000180 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_phi_table_set\n+ 99: 00000160 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_nk\n+ 100: 00000060 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kmesh_set\n+ 101: 00000168 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kmax\n+ 102: 00000038 40 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kgmesh\n+ 103: 00000000 56 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kfmesh\n+ 104: 00000064 4 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kcut_set\n+ 105: 00000178 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_kcut\n+ 106: 00000068 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_dr\n+ 107: 00000170 8 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_dk\n+ 108: 000000e8 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_d2phidr2\n+ 109: 00000124 60 OBJECT GLOBAL HIDDEN 4 __gridxc_vv_vdwxc_MOD_d2phidk2\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,165 +1,165 @@\n \n-Relocation section '.rel.text' at offset 0x36ac contains 162 entries:\n+Relocation section '.rel.text' at offset 0x3888 contains 162 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000044 00003e0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-0000008a 00003f0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-000000a2 00003e0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n-000000d2 00003f0a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n-000000f8 0000400a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000120 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000124 0000421a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000128 00003003 R_ARM_REL32 00000000 .rodata\n-0000012c 00000203 R_ARM_REL32 00000000 .bss\n-00000130 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000001a2 0000430a R_ARM_THM_CALL 00000000 pow\n-000001f0 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000001f4 0000441a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000001f8 00000703 R_ARM_REL32 00000000 .LC5\n-000002de 0000450a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00000306 0000450a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-0000032c 0000450a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n-00000354 0000450a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00000040 0000420a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+00000082 0000430a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+0000009a 0000420a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_set_mesh\n+000000ca 0000430a R_ARM_THM_CALL 00000000 __gridxc_mesh1d_MOD_get_mesh\n+000000ec 0000440a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000000f0 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000000f4 0000461a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000000f8 00003403 R_ARM_REL32 00000000 .rodata\n+000000fc 00000203 R_ARM_REL32 00000000 .bss\n+00000100 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000016e 0000470a R_ARM_THM_CALL 00000000 pow\n+000001c0 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000001c4 0000481a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000001c8 00000703 R_ARM_REL32 00000000 .LC5\n+000002b4 0000490a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+000002dc 0000490a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+0000030a 0000490a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00000330 0000490a R_ARM_THM_CALL 00000000 __gridxc_alloc_MOD_realloc_d3\n+00000528 00000203 R_ARM_REL32 00000000 .bss\n+0000052c 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000530 0000461a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000534 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 00000538 00000203 R_ARM_REL32 00000000 .bss\n-0000053c 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000540 0000421a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000544 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000548 00000203 R_ARM_REL32 00000000 .bss\n-0000054c 0000441a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000550 00000b03 R_ARM_REL32 00000020 .LC6\n-00000554 00000203 R_ARM_REL32 00000000 .bss\n-00000558 00003003 R_ARM_REL32 00000000 .rodata\n-0000055c 00000203 R_ARM_REL32 00000000 .bss\n-00000560 00000c03 R_ARM_REL32 0000004c .LC10\n-00000564 00000d03 R_ARM_REL32 00000068 .LC12\n-00000568 00000e03 R_ARM_REL32 00000084 .LC13\n-0000056c 00000f03 R_ARM_REL32 000000a4 .LC14\n+0000053c 0000481a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000540 00000b03 R_ARM_REL32 00000020 .LC6\n+00000544 00000203 R_ARM_REL32 00000000 .bss\n+00000548 00003403 R_ARM_REL32 00000000 .rodata\n+0000054c 00000203 R_ARM_REL32 00000000 .bss\n+00000550 00000c03 R_ARM_REL32 0000004c .LC10\n+00000554 00000d03 R_ARM_REL32 00000068 .LC12\n+00000558 00000e03 R_ARM_REL32 00000084 .LC13\n+0000055c 00000f03 R_ARM_REL32 000000a4 .LC14\n+00000560 00000203 R_ARM_REL32 00000000 .bss\n+00000564 00003403 R_ARM_REL32 00000000 .rodata\n+00000568 00000203 R_ARM_REL32 00000000 .bss\n+0000056c 00000203 R_ARM_REL32 00000000 .bss\n 00000570 00000203 R_ARM_REL32 00000000 .bss\n 00000574 00000203 R_ARM_REL32 00000000 .bss\n-00000578 00000203 R_ARM_REL32 00000000 .bss\n-0000057c 00000203 R_ARM_REL32 00000000 .bss\n-00000580 00000203 R_ARM_REL32 00000000 .bss\n-00000640 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000006b4 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-000006cc 0000470a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-000006d6 0000480a R_ARM_THM_CALL 00000000 free\n-000006e6 0000490a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-000006ec 0000480a R_ARM_THM_CALL 00000000 free\n-000007c0 00003003 R_ARM_REL32 00000000 .rodata\n-000007c4 00000203 R_ARM_REL32 00000000 .bss\n-000007c8 00000203 R_ARM_REL32 00000000 .bss\n-000007cc 00000203 R_ARM_REL32 00000000 .bss\n-0000089a 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000908 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000922 0000470a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n-0000092c 0000480a R_ARM_THM_CALL 00000000 free\n-0000093c 0000490a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00000942 0000480a R_ARM_THM_CALL 00000000 free\n-00000a20 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000a90 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000aae 00004a0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-00000ab8 0000480a R_ARM_THM_CALL 00000000 free\n-00000ac8 0000490a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00000ace 0000480a R_ARM_THM_CALL 00000000 free\n-00000b4e 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000bc6 0000460a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n-00000bde 00004a0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n-00000be8 0000480a R_ARM_THM_CALL 00000000 free\n-00000bf8 0000490a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n-00000bfe 0000480a R_ARM_THM_CALL 00000000 free\n-00000d18 00000203 R_ARM_REL32 00000000 .bss\n-00000d1c 00003003 R_ARM_REL32 00000000 .rodata\n-00000d20 00000203 R_ARM_REL32 00000000 .bss\n-00000d24 00000203 R_ARM_REL32 00000000 .bss\n-00000d28 00003003 R_ARM_REL32 00000000 .rodata\n-00000d2c 00000203 R_ARM_REL32 00000000 .bss\n-00000d30 00000203 R_ARM_REL32 00000000 .bss\n-00000d34 00000203 R_ARM_REL32 00000000 .bss\n-00000d38 00000203 R_ARM_REL32 00000000 .bss\n-00000e54 0000400a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000e58 00000203 R_ARM_REL32 00000000 .bss\n-00000e5c 00000203 R_ARM_REL32 00000000 .bss\n-00000e60 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000e64 0000421a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000f10 00004c0a R_ARM_THM_CALL 00000000 cbrt\n-00001008 00004d0a R_ARM_THM_CALL 00000000 log\n-00001030 00004d0a R_ARM_THM_CALL 00000000 log\n-00001060 00004e0a R_ARM_THM_CALL 00000000 exp\n-0000108c 00004e0a R_ARM_THM_CALL 00000000 exp\n-000010e8 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000010ec 0000421a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000010f0 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000010f4 00000103 R_ARM_REL32 00000000 .data\n-000010f8 00000103 R_ARM_REL32 00000000 .data\n-000010fc 00000203 R_ARM_REL32 00000000 .bss\n-00001100 00000203 R_ARM_REL32 00000000 .bss\n-0000111a 00004e0a R_ARM_THM_CALL 00000000 exp\n-00001192 00004e0a R_ARM_THM_CALL 00000000 exp\n-00001250 00004d0a R_ARM_THM_CALL 00000000 log\n-00001268 00004d0a R_ARM_THM_CALL 00000000 log\n-000014e8 0000441a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000014ec 00001d03 R_ARM_REL32 0000011c .LC22\n-000014f0 00000203 R_ARM_REL32 00000000 .bss\n-000014f4 00001e03 R_ARM_REL32 00000148 .LC23\n-000014f8 00000103 R_ARM_REL32 00000000 .data\n-000014fc 00000203 R_ARM_REL32 00000000 .bss\n-00001500 00001f03 R_ARM_REL32 00000174 .LC24\n-00001504 00000203 R_ARM_REL32 00000000 .bss\n-00001508 00000203 R_ARM_REL32 00000000 .bss\n-00001ad8 00004f0a R_ARM_THM_CALL 00000000 memcpy\n-00001c54 0000510a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n-00001cc8 0000510a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n-00001d08 0000520a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00001d60 0000530a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001d6a 0000540a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n-00001d90 0000550a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001db2 0000550a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001db8 0000560a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001de2 0000570a R_ARM_THM_CALL 00000000 _gfortran_st_close\n-00001e14 0000520a R_ARM_THM_CALL 00000000 _gfortran_st_open\n-00001e66 0000530a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00001e70 0000540a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n-00001e96 0000550a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001eb8 0000550a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n-00001ebe 0000560a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00001eee 0000570a R_ARM_THM_CALL 00000000 _gfortran_st_close\n-00001f08 0000500a R_ARM_THM_CALL 00000000 memset\n-00001f1a 0000500a R_ARM_THM_CALL 00000000 memset\n-00001f78 0000400a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001fb8 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001fbc 0000421a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001fc0 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001fc4 00000203 R_ARM_REL32 00000000 .bss\n-00001fc8 00003003 R_ARM_REL32 00000000 .rodata\n-00001fcc 00000203 R_ARM_REL32 00000000 .bss\n-00001fd0 00001903 R_ARM_REL32 000000c4 .LC18\n-00001fd4 00001a03 R_ARM_REL32 00000100 .LC19\n-00001fd8 00001b03 R_ARM_REL32 00000108 .LC20\n-00001fdc 00001c03 R_ARM_REL32 00000114 .LC21\n-00001fe0 00000203 R_ARM_REL32 00000000 .bss\n-00001fe4 00001903 R_ARM_REL32 000000c4 .LC18\n-00001fe8 00001b03 R_ARM_REL32 00000108 .LC20\n-00001fec 00000103 R_ARM_REL32 00000000 .data\n-000020b0 00000203 R_ARM_REL32 00000000 .bss\n-000020b4 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000020b8 00000203 R_ARM_REL32 00000000 .bss\n-000020bc 00000203 R_ARM_REL32 00000000 .bss\n-000020c0 00000203 R_ARM_REL32 00000000 .bss\n-000020c4 0000441a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000020c8 00002603 R_ARM_REL32 0000019c .LC25\n-00002194 0000500a R_ARM_THM_CALL 00000000 memset\n-000021d4 0000500a R_ARM_THM_CALL 00000000 memset\n-00002448 00004119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000244c 00000203 R_ARM_REL32 00000000 .bss\n-00002450 0000441a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00002454 00002903 R_ARM_REL32 000001bc .LC26\n-00002458 00000203 R_ARM_REL32 00000000 .bss\n-0000245c 00000203 R_ARM_REL32 00000000 .bss\n-00002460 00000203 R_ARM_REL32 00000000 .bss\n-000026c0 00004f0a R_ARM_THM_CALL 00000000 memcpy\n-000027bc 00000203 R_ARM_REL32 00000000 .bss\n-000027c0 00000203 R_ARM_REL32 00000000 .bss\n-000027c4 00000203 R_ARM_REL32 00000000 .bss\n-000027c8 00000203 R_ARM_REL32 00000000 .bss\n-000027cc 00000203 R_ARM_REL32 00000000 .bss\n-000026ea 00004f1e R_ARM_THM_JUMP24 00000000 memcpy\n-00001be0 0000501e R_ARM_THM_JUMP24 00000000 memset\n+00000630 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000006a2 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000006b6 00004b0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+000006c0 00004c0a R_ARM_THM_CALL 00000000 free\n+000006d0 00004d0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+000006d6 00004c0a R_ARM_THM_CALL 00000000 free\n+000007a8 00000203 R_ARM_REL32 00000000 .bss\n+000007ac 00000203 R_ARM_REL32 00000000 .bss\n+000007b0 00000203 R_ARM_REL32 00000000 .bss\n+000007b4 00000203 R_ARM_REL32 00000000 .bss\n+0000087c 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000008e6 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+000008fc 00004b0a R_ARM_THM_CALL 00000000 __gridxc_radfft_MOD_radfft\n+00000906 00004c0a R_ARM_THM_CALL 00000000 free\n+00000916 00004d0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+0000091c 00004c0a R_ARM_THM_CALL 00000000 free\n+000009ee 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000a5a 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000a78 00004e0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+00000a82 00004c0a R_ARM_THM_CALL 00000000 free\n+00000a92 00004d0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00000a98 00004c0a R_ARM_THM_CALL 00000000 free\n+00000b10 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000b58 00003403 R_ARM_REL32 00000000 .rodata\n+00000b5c 00000203 R_ARM_REL32 00000000 .bss\n+00000b60 00000203 R_ARM_REL32 00000000 .bss\n+00000b64 00003403 R_ARM_REL32 00000000 .rodata\n+00000b68 00000203 R_ARM_REL32 00000000 .bss\n+00000bae 00004a0a R_ARM_THM_CALL 00000000 _gfortran_internal_pack\n+00000bc8 00004e0a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_dx\n+00000bd2 00004c0a R_ARM_THM_CALL 00000000 free\n+00000be2 00004d0a R_ARM_THM_CALL 00000000 _gfortran_internal_unpack\n+00000be8 00004c0a R_ARM_THM_CALL 00000000 free\n+00000e0c 0000440a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000e10 00000203 R_ARM_REL32 00000000 .bss\n+00000e14 00000203 R_ARM_REL32 00000000 .bss\n+00000e18 00000203 R_ARM_REL32 00000000 .bss\n+00000e1c 00000203 R_ARM_REL32 00000000 .bss\n+00000e20 00000203 R_ARM_REL32 00000000 .bss\n+00000e24 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000e28 0000461a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000ed4 0000500a R_ARM_THM_CALL 00000000 cbrt\n+00000fc8 0000510a R_ARM_THM_CALL 00000000 log\n+00000ff0 0000510a R_ARM_THM_CALL 00000000 log\n+0000103c 0000520a R_ARM_THM_CALL 00000000 exp\n+0000105c 0000520a R_ARM_THM_CALL 00000000 exp\n+000010b0 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000010b4 0000461a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000010b8 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000010bc 00000103 R_ARM_REL32 00000000 .data\n+000010c0 00000103 R_ARM_REL32 00000000 .data\n+000010c4 00000203 R_ARM_REL32 00000000 .bss\n+000010c8 00000203 R_ARM_REL32 00000000 .bss\n+000010e2 0000520a R_ARM_THM_CALL 00000000 exp\n+00001154 0000520a R_ARM_THM_CALL 00000000 exp\n+00001212 0000510a R_ARM_THM_CALL 00000000 log\n+00001230 0000510a R_ARM_THM_CALL 00000000 log\n+00001490 0000481a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001494 00001d03 R_ARM_REL32 0000011c .LC22\n+00001498 00000203 R_ARM_REL32 00000000 .bss\n+0000149c 00001e03 R_ARM_REL32 00000148 .LC23\n+000014a0 00000103 R_ARM_REL32 00000000 .data\n+000014a4 00000203 R_ARM_REL32 00000000 .bss\n+000014a8 00001f03 R_ARM_REL32 00000174 .LC24\n+000014ac 00000203 R_ARM_REL32 00000000 .bss\n+000014b0 00000203 R_ARM_REL32 00000000 .bss\n+00001c6a 0000530a R_ARM_THM_CALL 00000000 memcpy\n+00001dde 0000550a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n+00001e46 0000550a R_ARM_THM_CALL 00000000 __gridxc_interpolation_MOD_generate_spline_x\n+00001e88 0000560a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+00001ece 0000570a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00001ed8 0000580a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n+00001f0a 0000590a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+00001f30 0000590a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+00001f36 00005a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00001f74 00005b0a R_ARM_THM_CALL 00000000 _gfortran_st_close\n+00001f9e 0000560a R_ARM_THM_CALL 00000000 _gfortran_st_open\n+00001fec 0000570a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00001ff6 0000580a R_ARM_THM_CALL 00000000 _gfortran_transfer_real_write\n+00002026 0000590a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+00002054 0000590a R_ARM_THM_CALL 00000000 _gfortran_transfer_array_write\n+0000205a 00005a0a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00002082 00005b0a R_ARM_THM_CALL 00000000 _gfortran_st_close\n+000020a0 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000020a4 0000461a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000020a8 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000020ac 00000203 R_ARM_REL32 00000000 .bss\n+000020b0 00003403 R_ARM_REL32 00000000 .rodata\n+000020b4 00000203 R_ARM_REL32 00000000 .bss\n+000020b8 00001903 R_ARM_REL32 000000c4 .LC18\n+000020bc 00001a03 R_ARM_REL32 00000100 .LC19\n+000020c0 00001b03 R_ARM_REL32 00000108 .LC20\n+000020c4 00001c03 R_ARM_REL32 00000114 .LC21\n+000020c8 00000203 R_ARM_REL32 00000000 .bss\n+000020cc 00001903 R_ARM_REL32 000000c4 .LC18\n+000020d0 00001b03 R_ARM_REL32 00000108 .LC20\n+000020d4 00000103 R_ARM_REL32 00000000 .data\n+000020e2 0000540a R_ARM_THM_CALL 00000000 memset\n+000020f4 0000540a R_ARM_THM_CALL 00000000 memset\n+00002156 0000440a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002220 00000203 R_ARM_REL32 00000000 .bss\n+00002224 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00002228 00000203 R_ARM_REL32 00000000 .bss\n+0000222c 00000203 R_ARM_REL32 00000000 .bss\n+00002230 00000203 R_ARM_REL32 00000000 .bss\n+00002234 0000481a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00002238 00002903 R_ARM_REL32 0000019c .LC25\n+00002308 0000540a R_ARM_THM_CALL 00000000 memset\n+00002348 0000540a R_ARM_THM_CALL 00000000 memset\n+000025c0 00004519 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000025c4 00000203 R_ARM_REL32 00000000 .bss\n+000025c8 0000481a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+000025cc 00002b03 R_ARM_REL32 000001bc .LC26\n+000025d0 00000203 R_ARM_REL32 00000000 .bss\n+000025d4 00000203 R_ARM_REL32 00000000 .bss\n+000025d8 00000203 R_ARM_REL32 00000000 .bss\n+0000285c 0000530a R_ARM_THM_CALL 00000000 memcpy\n+00002958 00000203 R_ARM_REL32 00000000 .bss\n+0000295c 00000203 R_ARM_REL32 00000000 .bss\n+00002960 00000203 R_ARM_REL32 00000000 .bss\n+00002964 00000203 R_ARM_REL32 00000000 .bss\n+00002968 00000203 R_ARM_REL32 00000000 .bss\n+00001d6a 0000541e R_ARM_THM_JUMP24 00000000 memset\n+00002886 0000531e R_ARM_THM_JUMP24 00000000 memcpy\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,11 +1,9 @@\n-xD45YF{DBF\n-\t=F{DGF83CD\n+~D45{D9F\n =@UUUUUU\n-q=UUUUUU\n vv_vdwxc_saturate ERROR: x<0\n vv_vdw_set_phi_table ERROR: kcut not set\n vv_vdwxc/set_phi_table phir\n vv_vdwxc/set_phi_table phik\n vv_vdwxc/set_phi_table d2phidr2\n vv_vdwxc/set_phi_table d2phidk2\n /build/reproducible-path/libgridxc-2.0.1/src/vv_vdwxc.F90\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -3,459 +3,460 @@\n \n Disassembly of section .text:\n \n 00000000 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0>:\n __gridxc_vv_vdwxc_MOD_set_kmesh.part.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3976]\t@ 0xf88\n-\tldr\tr0, [pc, #264]\t@ (120 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x120>)\n+\tstr.w\tr0, [ip, #3984]\t@ 0xf90\n+\tldr\tr0, [pc, #220]\t@ (f0 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xf0>)\n \tsub\tsp, #76\t@ 0x4c\n-\tldr\tr3, [pc, #264]\t@ (124 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x124>)\n+\tldr\tr3, [pc, #220]\t@ (f4 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xf4>)\n \tmovs\tr4, #0\n \tadd\tr0, pc\n-\tldr\tr5, [pc, #264]\t@ (128 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x128>)\n+\tldr\tr5, [pc, #220]\t@ (f8 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xf8>)\n \tstr\tr4, [sp, #0]\n \tmov\tr2, r4\n \tadd\tr5, pc\n \tmov\tr1, r4\n \tldr\tr3, [r0, r3]\n-\tadd.w\tr7, r5, #8\n-\tmov\tr0, r7\n-\tvmov.i32\td8, #0\t@ 0x00000000\n+\tadd.w\tr6, r5, #8\n+\tldr.w\tsl, [pc, #208]\t@ fc <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xfc>\n+\tmov\tr0, r6\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #68]\t@ 0x44\n \tmov.w\tr3, #0\n \tadd.w\tr3, r5, #16\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r5\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tadd.w\tr8, sp, #52\t@ 0x34\n-\tvldr\td16, [pc, #176]\t@ 100 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x100>\n-\tvldr\td17, [pc, #180]\t@ 108 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x108>\n-\tmov\tr0, r7\n-\tldr\tr6, [pc, #212]\t@ (12c <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x12c>)\n-\tadd\tr7, sp, #32\n-\tvstr\td8, [sp, #44]\t@ 0x2c\n-\tmov.w\tfp, #8\n-\tadd\tr6, pc\n+\tmov\tr0, r6\n \tmov\tr3, r4\n-\tmov\tr2, r7\n+\tadd\tr2, sp, #32\n \tadd\tr1, sp, #24\n \tstrd\tr4, r4, [sp, #4]\n-\tmov.w\tsl, #4294967295\t@ 0xffffffff\n \tstr\tr4, [sp, #0]\n-\tmovw\tr9, #769\t@ 0x301\n-\tstr.w\tfp, [sp, #40]\t@ 0x28\n-\tstr\tr6, [sp, #32]\n-\tvst1.32\t{d16-d17}, [r8]\n-\tstr.w\tsl, [sp, #36]\t@ 0x24\n-\tstrh.w\tr9, [sp, #48]\t@ 0x30\n+\tmovs\tr7, #8\n+\tmov.w\tip, #7\n+\tadd\tsl, pc\n+\tmovs\tr6, #1\n+\tstrd\tr4, r7, [sp, #48]\t@ 0x30\n+\tstr.w\tip, [sp, #64]\t@ 0x40\n+\tmov.w\tfp, #4294967295\t@ 0xffffffff\n+\tstrd\tr7, r4, [sp, #40]\t@ 0x28\n+\tmovw\tr8, #769\t@ 0x301\n+\tstr\tr2, [sp, #16]\n+\tstr.w\tsl, [sp, #32]\n+\tstrd\tr6, r6, [sp, #56]\t@ 0x38\n+\tstr.w\tfp, [sp, #36]\t@ 0x24\n+\tstrh.w\tr8, [sp, #48]\t@ 0x30\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n \tadd.w\tr0, r5, #24\n-\tadd.w\tr3, r5, #32\n \tmov\tr2, r4\n \tmov\tr1, r4\n+\tadd.w\tr3, r5, #32\n+\tstr\tr4, [sp, #0]\n \tstr\tr3, [sp, #4]\n \tmov\tr3, r5\n-\tstr\tr4, [sp, #0]\n \tstr\tr0, [sp, #20]\n \tbl\t0 <__gridxc_mesh1d_MOD_set_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_set_mesh\n-\tvldr\td16, [pc, #104]\t@ 110 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x110>\n-\tvldr\td17, [pc, #108]\t@ 118 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x118>\n-\tmov\tr2, r7\n \tmov\tr3, r4\n-\tadd.w\tr1, r6, #56\t@ 0x38\n-\tstrd\tsl, fp, [sp, #36]\t@ 0x24\n-\tldr\tr0, [sp, #20]\n-\tvst1.32\t{d16-d17}, [r8]\n-\tstr\tr1, [sp, #32]\n-\tadd\tr1, sp, #28\n \tstrd\tr4, r4, [sp, #4]\n+\tldrd\tr2, r0, [sp, #16]\n \tstr\tr4, [sp, #0]\n-\tvstr\td8, [sp, #44]\t@ 0x2c\n-\tstrh.w\tr9, [sp, #48]\t@ 0x30\n+\tadd\tr1, sp, #28\n+\tstr\tr4, [sp, #48]\t@ 0x30\n+\tstrd\tr7, r4, [sp, #40]\t@ 0x28\n+\tmovs\tr4, #5\n+\tstr.w\tfp, [sp, #36]\t@ 0x24\n+\tstr\tr4, [sp, #64]\t@ 0x40\n+\tadd.w\tr4, sl, #56\t@ 0x38\n+\tstrh.w\tr8, [sp, #48]\t@ 0x30\n+\tstr\tr7, [sp, #52]\t@ 0x34\n+\tstrd\tr6, r6, [sp, #56]\t@ 0x38\n+\tstr\tr4, [sp, #32]\n \tbl\t0 <__gridxc_mesh1d_MOD_get_mesh>\n R_ARM_THM_CALL\t__gridxc_mesh1d_MOD_get_mesh\n-\tldr\tr2, [pc, #88]\t@ (130 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x130>)\n-\tmovs\tr3, #1\n-\tstr\tr3, [r6, #96]\t@ 0x60\n-\tldr\tr3, [pc, #68]\t@ (124 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x124>)\n+\tldr\tr2, [pc, #48]\t@ (100 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0x100>)\n+\tldr\tr3, [pc, #32]\t@ (f4 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xf4>)\n \tadd\tr2, pc\n+\tstr.w\tr6, [sl, #96]\t@ 0x60\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #68]\t@ 0x44\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\tf8 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xf8>\n+\tbne.n\tec <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0+0xec>\n \tadd\tsp, #76\t@ 0x4c\n-\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000007\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000005\n-\t.word\t0x00000100\n+\t.word\t0x000000d4\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000100\n+\t.word\t0x000000d4\n R_ARM_REL32\t.rodata\n-\t.word\t0x000000c6\n+\t.word\t0x000000a0\n R_ARM_REL32\t.bss\n-\t.word\t0x0000004e\n+\t.word\t0x0000002a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00000134 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>:\n+00000104 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>:\n __gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0():\n-\tvmov.i64\td16, #0x0000000000000000\n-\tldr\tr3, [pc, #180]\t@ (1f0 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xbc>)\n+\tvcmpe.f64\td0, #0.0\n+\tldr\tr3, [pc, #180]\t@ (1c0 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xbc>)\n \tadd\tr3, pc\n-\tvcmpe.f64\td0, d16\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t1b8 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0x84>\n+\tbmi.n\t184 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0x80>\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4064]\t@ 0xfe0\n \tvcmp.f64\td0, #0.0\n \tmov\tr5, r0\n \tmov\tr4, r1\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t1c6 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0x92>\n+\tbeq.n\t192 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0x8e>\n \tvmul.f64\td8, d0, d0\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldr\td17, [pc, #112]\t@ 1e0 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xac>\n-\tvldr\td1, [pc, #116]\t@ 1e8 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xb4>\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [pc, #116]\t@ 1b0 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xac>\n+\tvldr\td1, [pc, #120]\t@ 1b8 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xb4>\n \tvmul.f64\td0, d8, d0\n \tvmul.f64\td8, d8, d8\n-\tvmul.f64\td16, d0, d0\n+\tvmul.f64\td7, d0, d0\n \tvmul.f64\td8, d8, d8\n-\tvmul.f64\td16, d16, d16\n+\tvmul.f64\td7, d7, d7\n \tvmul.f64\td8, d8, d8\n-\tvmul.f64\td16, d16, d0\n-\tvdiv.f64\td9, d18, d16\n-\tvadd.f64\td9, d9, d17\n+\tvmul.f64\td7, d7, d0\n+\tvdiv.f64\td9, d5, d7\n+\tvadd.f64\td9, d9, d6\n \tvmul.f64\td8, d8, d9\n \tvmov.f64\td0, d9\n \tbl\t0 \n R_ARM_THM_CALL\tpow\n \tvstr\td0, [r5]\n-\tvdiv.f64\td16, d0, d8\n+\tvdiv.f64\td7, d0, d8\n \tvpop\t{d8-d9}\n-\tvstr\td16, [r4]\n+\tvstr\td7, [r4]\n \tpop\t{r4, r5, r6, pc}\n-\tldr\tr2, [pc, #56]\t@ (1f4 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xc0>)\n+\tldr\tr2, [pc, #60]\t@ (1c4 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xc0>)\n \tmovs\tr1, #28\n-\tldr\tr0, [pc, #56]\t@ (1f8 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xc4>)\n+\tldr\tr0, [pc, #60]\t@ (1c8 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0+0xc4>)\n \tadd\tr0, pc\n \tldr\tr3, [r3, r2]\n \tldr\tr3, [r3, #0]\n \tbx\tr3\n \tvpop\t{d8-d9}\n+\tmovs\tr0, #0\n+\tmovs\tr1, #0\n \tmovs\tr2, #0\n \tmovs\tr3, #0\n \tmovt\tr3, #16368\t@ 0x3ff0\n-\tvstr\td16, [r0]\n-\tstrd\tr2, r3, [r1]\n+\tstrd\tr0, r1, [r5]\n+\tstrd\tr2, r3, [r4]\n \tpop\t{r4, r5, r6, pc}\n \tnop.w\n \t.word\t0x9ee75616\n \t.word\t0x3dc203af\n \t.word\t0x11111111\n \t.word\t0xbfb11111\n \t.word\t0x000000b2\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000036\n+\t.word\t0x0000003a\n R_ARM_REL32\t.LC5\n \n-000001fc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>:\n+000001cc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>:\n __gridxc_vv_vdwxc_MOD_set_phi_table.part.0():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d10}\n+\tvpush\t{d8-d13}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n \tstr.w\tr0, [ip]\n \tsub.w\tip, ip, #4096\t@ 0x1000\n-\tstr.w\tr0, [ip, #3768]\t@ 0xeb8\n-\tldr\tr3, [pc, #772]\t@ (538 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x33c>)\n+\tstr.w\tr0, [ip, #3752]\t@ 0xea8\n+\tldr\tr3, [pc, #804]\t@ (528 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x35c>)\n \tsub.w\tsp, sp, #16640\t@ 0x4100\n-\tldr\tr1, [pc, #772]\t@ (53c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x340>)\n-\tsub\tsp, #12\n+\tldr\tr1, [pc, #804]\t@ (52c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x360>)\n+\tsub\tsp, #4\n \tadd\tr3, pc\n-\tldr\tr2, [pc, #768]\t@ (540 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x344>)\n+\tldr\tr2, [pc, #800]\t@ (530 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x364>)\n \tadd\tr1, pc\n-\tadd.w\tr0, sp, #16640\t@ 0x4100\n-\tldr\tr4, [pc, #764]\t@ (544 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x348>)\n-\tadds\tr0, #4\n+\tadd.w\tr0, sp, #16512\t@ 0x4080\n+\tldr\tr4, [pc, #796]\t@ (534 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x368>)\n+\tadds\tr0, #124\t@ 0x7c\n \tldr\tr3, [r3, #96]\t@ 0x60\n \tldr\tr2, [r1, r2]\n \tadd\tr4, pc\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [r0, #0]\n \tmov.w\tr2, #0\n \tcmp\tr3, #0\n-\tbeq.w\te4c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc50>\n-\tldr\tr3, [pc, #744]\t@ (548 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x34c>)\n+\tbeq.w\te04 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc38>\n+\tldr\tr3, [pc, #776]\t@ (538 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x36c>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #100]\t@ 0x64\n-\tcbnz\tr3, 272 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x76>\n-\tldr\tr3, [pc, #740]\t@ (54c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x350>)\n+\tcbnz\tr3, 242 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x76>\n+\tldr\tr3, [pc, #772]\t@ (53c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x370>)\n \tmovs\tr1, #40\t@ 0x28\n-\tldr\tr0, [pc, #740]\t@ (550 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x354>)\n+\tldr\tr0, [pc, #772]\t@ (540 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x374>)\n \tadd\tr0, pc\n \tldr\tr3, [r4, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #736]\t@ (554 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x358>)\n-\tadd\tr6, sp, #264\t@ 0x108\n-\tadd.w\tr7, sp, #16640\t@ 0x4100\n-\tsub.w\tr2, r6, #16\n+\tldr\tr3, [pc, #768]\t@ (544 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x378>)\n+\tadd.w\tr8, sp, #16512\t@ 0x4080\n+\tadd.w\tsl, sp, #256\t@ 0x100\n+\tadd.w\tr8, r8, #120\t@ 0x78\n \tadd\tr3, pc\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tvldr\td17, [r3, #104]\t@ 0x68\n+\tsub.w\tr2, sl, #16\n+\tstr\tr2, [sp, #76]\t@ 0x4c\n+\tvldr\td6, [r3, #104]\t@ 0x68\n \tmovs\tr3, #0\n \tvmov\ts15, r3\n \tadds\tr3, #1\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td16, d16, d17\n-\tvstmia\tr2!, {d16}\n-\tcmp\tr7, r2\n-\tbne.n\t288 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x8c>\n-\tldr\tr5, [pc, #696]\t@ (558 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x35c>)\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td7, d7, d6\n+\tvstmia\tr2!, {d7}\n+\tcmp\tr8, r2\n+\tbne.n\t25e <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x92>\n+\tldr\tr5, [pc, #720]\t@ (548 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x37c>)\n \tmovs\tr4, #0\n-\tldr\tr0, [pc, #696]\t@ (55c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x360>)\n+\tldr\tr6, [pc, #720]\t@ (54c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x380>)\n \tmov.w\tr9, #27\n \tadd\tr5, pc\n-\tldr\tr3, [pc, #692]\t@ (560 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x364>)\n-\tadd.w\tsl, r5, #40\t@ 0x28\n-\tadd.w\tfp, r5, #48\t@ 0x30\n-\tadd.w\tr8, r5, #44\t@ 0x2c\n-\tadd\tr0, pc\n+\tldr\tr3, [pc, #716]\t@ (550 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x384>)\n+\tadd.w\tfp, r5, #44\t@ 0x2c\n+\tadd.w\tr2, r5, #40\t@ 0x28\n+\tadd.w\tr7, r5, #48\t@ 0x30\n+\tadd\tr6, pc\n \tadds\tr5, #52\t@ 0x34\n-\tmov\tr1, fp\n \tadd\tr3, pc\n-\tmov\tr2, r8\n+\tmov\tr1, r7\n+\tadd.w\tr0, r6, #112\t@ 0x70\n+\tstr\tr2, [sp, #4]\n \tstr\tr3, [sp, #12]\n-\tmov\tr3, sl\n+\tmov\tr3, r2\n \tstr\tr5, [sp, #8]\n \tstr\tr5, [sp, #0]\n \tstr.w\tr9, [sp, #28]\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n-\tadds\tr0, #112\t@ 0x70\n-\tstr.w\tsl, [sp, #4]\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tmov\tr2, fp\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [pc, #636]\t@ (564 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x368>)\n-\tmov\tr1, fp\n-\tmov\tr2, r8\n-\tadds\tr0, #176\t@ 0xb0\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tldr\tr3, [pc, #664]\t@ (554 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x388>)\n+\tmov\tr1, r7\n+\tstrd\tr5, r2, [sp]\n+\tadd.w\tr0, r6, #172\t@ 0xac\n \tadd\tr3, pc\n \tstrd\tr9, r4, [sp, #28]\n-\tstrd\tsl, r5, [sp, #4]\n-\tmov.w\tr9, #31\n-\tstr\tr5, [sp, #0]\n+\tstr\tr5, [sp, #8]\n+\tmov\tr9, r2\n \tstr\tr3, [sp, #12]\n-\tmov\tr3, sl\n+\tmov\tr3, r2\n \tstrd\tr4, r4, [sp, #20]\n+\tmov\tr2, fp\n \tstr\tr4, [sp, #16]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n-\tldr\tr3, [pc, #600]\t@ (568 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x36c>)\n-\tmov\tr1, fp\n-\tmov\tr2, r8\n-\tadds\tr0, #240\t@ 0xf0\n+\tldr\tr3, [pc, #628]\t@ (558 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x38c>)\n+\tmov\tr2, r9\n+\tstrd\tr5, r9, [sp]\n \tadd\tr3, pc\n-\tstrd\tsl, r5, [sp, #4]\n-\tstr\tr5, [sp, #0]\n+\tmov.w\tr9, #31\n+\tmov\tr1, r7\n+\tadd.w\tr0, r6, #232\t@ 0xe8\n+\tstr\tr5, [sp, #8]\n \tstr\tr3, [sp, #12]\n-\tmov\tr3, sl\n+\tmov\tr3, r2\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tmov\tr2, fp\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstr.w\tr9, [sp, #28]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr\tr0, [sp, #44]\t@ 0x2c\n \tstr\tr5, [sp, #8]\n-\tmov\tr1, fp\n-\tstrd\tr5, sl, [sp]\n-\tmov\tr3, sl\n-\tldr\tr5, [pc, #556]\t@ (56c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x370>)\n-\tmov\tr2, r8\n-\tadd.w\tr0, r0, #304\t@ 0x130\n-\tstr.w\tr9, [sp, #28]\n+\tstr\tr5, [sp, #0]\n+\tmov\tr2, fp\n+\tldr\tr5, [pc, #580]\t@ (55c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x390>)\n+\tmov\tr1, r7\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd.w\tr0, r6, #292\t@ 0x124\n+\tstr\tr3, [sp, #4]\n \tadd\tr5, pc\n+\tstr.w\tr9, [sp, #28]\n \tstr\tr4, [sp, #32]\n \tstrd\tr4, r4, [sp, #20]\n \tstr\tr4, [sp, #16]\n \tstr\tr5, [sp, #12]\n \tbl\t0 <__gridxc_alloc_MOD_realloc_d3>\n R_ARM_THM_CALL\t__gridxc_alloc_MOD_realloc_d3\n-\tldr.w\tfp, [pc, #532]\t@ 570 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x374>\n-\tldr\tr3, [pc, #532]\t@ (574 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x378>)\n+\tldr.w\tfp, [pc, #552]\t@ 560 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x394>\n+\tldr\tr3, [pc, #552]\t@ (564 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x398>)\n \tadd\tfp, pc\n-\tstr.w\tfp, [sp, #64]\t@ 0x40\n+\tstr.w\tfp, [sp, #60]\t@ 0x3c\n \tadd\tr3, pc\n \tstr\tr3, [sp, #100]\t@ 0x64\n-\tadds\tr3, #132\t@ 0x84\n+\tadds\tr3, #56\t@ 0x38\n \tstr\tr3, [sp, #104]\t@ 0x68\n-\tadd.w\tr3, fp, #196\t@ 0xc4\n-\tmov\tfp, r7\n-\tmov\tr7, r6\n+\tadd.w\tr3, fp, #360\t@ 0x168\n+\tmov\tfp, r8\n+\tmov\tr8, sl\n \tstr\tr3, [sp, #108]\t@ 0x6c\n-\tldr\tr3, [pc, #512]\t@ (578 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x37c>)\n-\tmov.w\tr8, r4, lsl #3\n-\tmov.w\tr9, #0\n-\tmov\tr5, r7\n+\tldr\tr3, [pc, #532]\t@ (568 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x39c>)\n+\tlsls\tr6, r4, #3\n+\tmovs\tr2, #0\n+\tmov\tsl, fp\n \tadd\tr3, pc\n-\tmov\tr7, r8\n+\tmov\tr9, r2\n \tadds\tr3, #56\t@ 0x38\n-\tadd\tr3, r8\n-\tmov\tr8, r9\n-\tmov\tr9, fp\n+\tmov\tr7, r6\n+\tadd\tr3, r6\n \tstr\tr3, [sp, #92]\t@ 0x5c\n-\tldr\tr3, [pc, #488]\t@ (57c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x380>)\n+\tldr\tr3, [pc, #516]\t@ (56c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3a0>)\n \tsubs\tr2, r7, r4\n+\tmovs\tr5, #0\n \tadds\tr2, #1\n-\tstrd\tr4, r8, [sp, #116]\t@ 0x74\n \tadd\tr3, pc\n-\tmovs\tr6, #0\n-\tmov\tr4, r5\n-\tadd.w\tfp, r2, r8\n-\tadd.w\tr3, r3, r8, lsl #3\n-\tstr.w\tfp, [sp, #44]\t@ 0x2c\n+\tadd.w\tr6, r2, r9\n+\tadd.w\tr3, r3, r9, lsl #3\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tstrd\tr4, r9, [sp, #116]\t@ 0x74\n+\tmov\tr6, r5\n+\tmov\tr9, sl\n+\tmov\tr5, r8\n \tstr\tr3, [sp, #96]\t@ 0x60\n \tstr\tr7, [sp, #124]\t@ 0x7c\n-\tldr\tr1, [pc, #460]\t@ (580 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x384>)\n+\tldr\tr1, [pc, #484]\t@ (570 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3a4>)\n \tlsls\tr3, r6, #3\n-\tsubs\tr2, r3, r6\n-\tvldr\td9, [pc, #320]\t@ 4f8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x2fc>\n+\tldr\tr2, [pc, #484]\t@ (574 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3a8>)\n \tadd\tr1, pc\n+\tvldr\td8, [pc, #340]\t@ 4e8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x31c>\n+\tadd\tr2, pc\n+\tstr\tr2, [sp, #88]\t@ 0x58\n+\tsubs\tr2, r3, r6\n+\tstr\tr1, [sp, #44]\t@ 0x2c\n \tadds\tr7, r2, #1\n \tadd.w\tr2, r1, #56\t@ 0x38\n-\tvldr\td8, [pc, #316]\t@ 500 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x304>\n \tadds\tr3, r2, r3\n-\tstr\tr1, [sp, #48]\t@ 0x30\n-\tstr\tr2, [sp, #56]\t@ 0x38\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr2, [sp, #52]\t@ 0x34\n+\tstr\tr3, [sp, #84]\t@ 0x54\n \tstr\tr6, [sp, #112]\t@ 0x70\n-\tb.n\t3e2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1e6>\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tb.n\t3bc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1f0>\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n \tadds\tr7, #1\n-\tldr\tr2, [sp, #56]\t@ 0x38\n+\tldr\tr2, [sp, #52]\t@ 0x34\n \tadds\tr3, #8\n-\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr2, r3\n-\tbeq.w\tde8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xbec>\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tbeq.w\tda2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xbd6>\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr3, r7\n-\tblt.n\t3d2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1d6>\n+\tblt.n\t3ac <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1e0>\n \tmov\tr1, r3\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tvldr\td18, [pc, #280]\t@ 508 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x30c>\n-\tvmov.f64\td24, #120\t@ 0x3fc00000 1.5\n-\tvldr\td25, [pc, #280]\t@ 510 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x314>\n-\tvldr\td23, [pc, #284]\t@ 518 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x31c>\n-\tvldr\td17, [r3]\n+\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tvldr\td6, [pc, #296]\t@ 4f0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x324>\n+\tvldr\td3, [pc, #300]\t@ 4f8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x32c>\n+\tvldr\td13, [pc, #304]\t@ 500 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x334>\n+\tvldr\td7, [r3]\n \tldr\tr3, [sp, #96]\t@ 0x60\n-\tvldr\td22, [pc, #284]\t@ 520 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x324>\n-\tvmaxnm.f64\td17, d17, d9\n-\tldr\tr2, [sp, #100]\t@ 0x64\n-\tvldr\td16, [r3]\n-\tldr\tr3, [sp, #88]\t@ 0x58\n-\tvmul.f64\td28, d17, d17\n-\tvmul.f64\td19, d17, d8\n-\tvmaxnm.f64\td16, d16, d9\n+\tvldr\td9, [pc, #300]\t@ 508 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x33c>\n+\tvcmpe.f64\td7, d8\n+\tvldr\td0, [pc, #300]\t@ 510 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x344>\n+\tldr\tr2, [sp, #88]\t@ 0x58\n+\tvldr\td5, [r3]\n+\tldr\tr3, [sp, #84]\t@ 0x54\n+\tvmrs\tAPSR_nzcv, fpscr\n \tldr.w\tlr, [r2, #160]\t@ 0xa0\n+\tvcmpe.f64\td5, d8\n \tldr.w\tip, [r2, #148]\t@ 0x94\n-\tvldr\td21, [r3]\n-\tvmul.f64\td19, d19, d28\n-\tvmul.f64\td26, d28, d25\n-\tvmul.f64\td27, d16, d16\n-\tvmul.f64\td16, d16, d8\n+\tldr.w\tr8, [r2, #132]\t@ 0x84\n+\tvldr\td2, [r3]\n \tldr\tr3, [sp, #92]\t@ 0x5c\n-\tvmul.f64\td21, d21, d21\n-\tldr\tr6, [r2, #112]\t@ 0x70\n-\tvmul.f64\td16, d16, d27\n-\tvmul.f64\td25, d27, d25\n-\tvmul.f64\td27, d19, d18\n-\tvldr\td20, [r3]\n-\tvmul.f64\td21, d21, d21\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tvmul.f64\td17, d16, d18\n-\tvmul.f64\td19, d19, d16\n-\tvsqrt.f64\td18, d27\n-\tvmul.f64\td20, d20, d20\n-\tvmul.f64\td27, d27, d23\n-\tvld1.32\t{d7}, [r3]\n-\tvfma.f64\td27, d21, d22\n+\tit\tlt\n+\tvmovlt.f64\td7, d8\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td2, d2, d2\n+\tldr\tr0, [r2, #112]\t@ 0x70\n+\tldr.w\tr6, [r2, #136]\t@ 0x88\n+\tvldr\td4, [r3]\n+\tvmul.f64\td1, d7, d7\n \tldr\tr3, [r2, #116]\t@ 0x74\n-\tvsqrt.f64\td16, d17\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td20, d20, d20\n-\tvmov\tr0, s14\n-\tvmov.32\tr5, d7[1]\n+\tvmul.f64\td11, d2, d2\n+\tvmul.f64\td4, d4, d4\n+\tmul.w\tr4, r8, r6\n \tmla\tr3, lr, r1, r3\n-\tldr\tr1, [sp, #80]\t@ 0x50\n+\tldr\tr1, [sp, #76]\t@ 0x4c\n \tmla\tr3, ip, r7, r3\n-\tvfma.f64\td17, d20, d22\n-\tvsqrt.f64\td23, d27\n-\tmla\tr3, r0, r3, r6\n-\tmul.w\tr0, r5, r0\n+\tvmul.f64\td12, d4, d4\n+\tvmul.f64\td4, d7, d6\n+\tite\tlt\n+\tvmovlt.f64\td7, d8\n+\tvmovge.f64\td7, d5\n+\tvmov.f64\td5, #120\t@ 0x3fc00000 1.5\n+\tmla\tr3, r8, r3, r0\n+\tvmul.f64\td4, d4, d1\n+\tvmul.f64\td1, d1, d13\n+\tvmul.f64\td10, d7, d7\n+\tvmul.f64\td7, d7, d6\n \tmov\tr2, r3\n-\tvsqrt.f64\td22, d17\n-\tvdiv.f64\td21, d26, d18\n-\tvdiv.f64\td20, d25, d16\n-\tvldmia\tr1!, {d16}\n-\tvmov.f64\td17, d21\n-\tvmov.f64\td18, d20\n-\tvmul.f64\td16, d16, d16\n+\tvmul.f64\td2, d4, d3\n+\tvmul.f64\td7, d7, d10\n+\tvmul.f64\td13, d10, d13\n+\tvsqrt.f64\td10, d2\n+\tvmul.f64\td2, d2, d9\n+\tvmul.f64\td3, d7, d3\n+\tvmul.f64\td7, d4, d7\n+\tvmla.f64\td2, d11, d0\n+\tvsqrt.f64\td4, d3\n+\tvmul.f64\td3, d3, d9\n+\tvmla.f64\td3, d12, d0\n+\tvdiv.f64\td6, d1, d10\n+\tvsqrt.f64\td1, d2\n+\tvsqrt.f64\td2, d3\n+\tvdiv.f64\td3, d13, d4\n+\tvldmia\tr1!, {d4}\n+\tvmov.f64\td0, d6\n+\tvmov.f64\td9, d3\n+\tvmul.f64\td4, d4, d4\n \tcmp\tr9, r1\n-\tvfma.f64\td17, d16, d23\n-\tvfma.f64\td18, d16, d22\n-\tvmul.f64\td16, d17, d18\n-\tvadd.f64\td17, d17, d18\n-\tvmul.f64\td17, d16, d17\n-\tvdiv.f64\td16, d24, d17\n-\tvnmul.f64\td16, d19, d16\n-\tvstr\td16, [r2]\n-\tadd\tr2, r0\n-\tbne.n\t4b2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x2b6>\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [pc, #56]\t@ 528 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x32c>\n-\tvldr\td20, [pc, #60]\t@ 530 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x334>\n-\tb.n\t592 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x396>\n+\tvmla.f64\td0, d4, d1\n+\tvmla.f64\td9, d4, d2\n+\tvmul.f64\td4, d0, d9\n+\tvadd.f64\td0, d0, d9\n+\tvmul.f64\td0, d4, d0\n+\tvdiv.f64\td4, d5, d0\n+\tvnmul.f64\td4, d7, d4\n+\tvstr\td4, [r2]\n+\tadd\tr2, r4\n+\tbne.n\t4a2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x2d6>\n+\tldr\tr2, [sp, #76]\t@ 0x4c\n+\tvmov.f64\td2, #112\t@ 0x3f800000 1.0\n+\tvldr\td4, [pc, #56]\t@ 518 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x34c>\n+\tvldr\td3, [pc, #60]\t@ 520 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x354>\n+\tb.n\t586 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3ba>\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n \t.word\t0x54442d18\n \t.word\t0x402921fb\n \t.word\t0xa0000000\n@@ -464,2347 +465,2471 @@\n \t.word\t0x3fd55555\n \t.word\t0xe0000000\n \t.word\t0x3f830be0\n \t.word\t0x47ae147b\n \t.word\t0x3f847ae1\n \t.word\t0x00000000\n \t.word\t0x40590000\n-\t.word\t0x000002fa\n+\t.word\t0x0000031a\n R_ARM_REL32\t.bss\n-\t.word\t0x000002fa\n+\t.word\t0x0000031a\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000002f4\n+\t.word\t0x00000314\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000002e6\n+\t.word\t0x00000306\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x000002e2\n+\t.word\t0x00000302\n R_ARM_REL32\t.LC6\n-\t.word\t0x000002d2\n+\t.word\t0x000002f0\n R_ARM_REL32\t.bss\n-\t.word\t0x000002ac\n+\t.word\t0x000002c6\n R_ARM_REL32\t.rodata\n-\t.word\t0x000002a0\n+\t.word\t0x000002ba\n R_ARM_REL32\t.bss\n-\t.word\t0x0000029e\n+\t.word\t0x000002ba\n R_ARM_REL32\t.LC10\n-\t.word\t0x00000274\n+\t.word\t0x0000028a\n R_ARM_REL32\t.LC12\n-\t.word\t0x00000250\n+\t.word\t0x0000026c\n R_ARM_REL32\t.LC13\n-\t.word\t0x00000220\n+\t.word\t0x00000238\n R_ARM_REL32\t.LC14\n-\t.word\t0x0000020e\n+\t.word\t0x00000222\n R_ARM_REL32\t.bss\n-\t.word\t0x0000020c\n+\t.word\t0x00000220\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000020a\n R_ARM_REL32\t.bss\n-\t.word\t0x000001f2\n+\t.word\t0x000001fa\n R_ARM_REL32\t.bss\n \t.word\t0x000001de\n R_ARM_REL32\t.bss\n-\t.word\t0x000001c2\n+\t.word\t0x000001dc\n R_ARM_REL32\t.bss\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvstr\td17, [r3]\n+\tvldr\td6, [pc, #540]\t@ 798 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5cc>\n+\tvstr\td6, [r3]\n \tcmp\tr9, r2\n-\tadd\tr3, r0\n-\tbeq.n\t5d8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3dc>\n-\tvldmia\tr2!, {d18}\n-\tvldr\td17, [r3]\n-\tvmul.f64\td16, d18, d19\n-\tvcmpe.f64\td16, #0.0\n+\tadd\tr3, r4\n+\tbeq.n\t5cc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x400>\n+\tvldmia\tr2!, {d5}\n+\tvldr\td6, [r3]\n+\tvmul.f64\td7, d5, d4\n+\tvcmpe.f64\td7, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t588 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x38c>\n-\tvcmpe.f64\td18, d20\n+\tbls.n\t57c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3b0>\n+\tvcmpe.f64\td5, d3\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\t584 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x388>\n-\tvmul.f64\td16, d16, d16\n-\tvmov.f64\td18, d21\n+\tbge.n\t578 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3ac>\n+\tvmul.f64\td7, d7, d7\n+\tvmov.f64\td5, d2\n \tcmp\tr9, r2\n-\tvmul.f64\td16, d16, d16\n-\tvfms.f64\td18, d16, d16\n-\tvmul.f64\td16, d18, d18\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td17, d17, d16\n-\tvstr\td17, [r3]\n-\tadd\tr3, r0\n-\tbne.n\t592 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x396>\n-\tldr\tr1, [sp, #64]\t@ 0x40\n-\tvmov.i32\td10, #0\t@ 0x00000000\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tnegs\tr5, r5\n-\tstr.w\tr5, [r4, #-52]\n+\tvmul.f64\td7, d7, d7\n+\tvmls.f64\td5, d7, d7\n+\tvmul.f64\td7, d5, d5\n+\tvmul.f64\td7, d7, d7\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td6, [r3]\n+\tadd\tr3, r4\n+\tbne.n\t586 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x3ba>\n+\tldr\tr4, [pc, #472]\t@ (7a8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5dc>)\n+\tsub.w\tr1, r5, #52\t@ 0x34\n+\tldr\tr2, [sp, #40]\t@ 0x28\n \tmov.w\tsl, #1\n-\tldr.w\tr3, [r1, #164]\t@ 0xa4\n-\tmovw\tr5, #769\t@ 0x301\n-\tvstr\td10, [r4, #-44]\t@ 0xffffffd4\n-\tmov.w\tfp, #8\n-\tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r1, #152]\t@ 0x98\n-\tsubs\tr2, r7, r2\n-\tmul.w\tr3, lr, r3\n-\tmla\tr3, ip, r2, r3\n-\tsub.w\tr2, r4, #36\t@ 0x24\n-\tadd.w\tr6, r6, r3, lsl #3\n-\tldr.w\tr3, [r1, #140]\t@ 0x8c\n-\tstr.w\tr6, [r4, #-56]\n-\tvst1.32\t{d7}, [r2]\n+\tadd\tr4, pc\n+\tstrd\tr8, r6, [r5, #-32]\n+\tmovw\tfp, #769\t@ 0x301\n+\tnegs\tr6, r6\n+\tstr.w\tsl, [r5, #-24]\n+\tldr.w\tr3, [r4, #164]\t@ 0xa4\n+\tstr.w\tr6, [r5, #-48]\n+\tmovs\tr6, #0\n+\tsub.w\tr8, r2, r3\n+\tldr.w\tr3, [r4, #152]\t@ 0x98\n+\tldr.w\tr2, [r4, #144]\t@ 0x90\n+\tsubs\tr3, r7, r3\n+\tstrd\tr6, r6, [r5, #-40]\t@ 0x28\n+\tmul.w\tr8, lr, r8\n+\tstrh.w\tfp, [r5, #-36]\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tmla\tr8, ip, r3, r8\n+\tldr.w\tr3, [r4, #140]\t@ 0x8c\n \trsb\tr3, r3, #1\n-\tldr.w\tr2, [r1, #144]\t@ 0x90\n-\tstrh.w\tr5, [r4, #-40]\n \tadd\tr3, r2\n-\tstr.w\tr3, [r4, #-24]\n-\tsub.w\tr3, r4, #56\t@ 0x38\n-\tstr.w\tfp, [r4, #-48]\n-\tmov\tr0, r3\n-\tstr.w\tsl, [r4, #-28]\n-\tstr\tr3, [sp, #60]\t@ 0x3c\n+\tadd.w\tr8, r0, r8, lsl #3\n+\tstr.w\tr3, [r5, #-20]\n+\tmov\tr0, r1\n+\tmovs\tr3, #8\n+\tstr.w\tr8, [r5, #-52]\n+\tstr.w\tr3, [r5, #-44]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tmov\tr8, r0\n-\tldr\tr0, [sp, #64]\t@ 0x40\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tvstr\td10, [r4, #-84]\t@ 0xffffffac\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r0, #228]\t@ 0xe4\n-\tldr.w\tr1, [r0, #224]\t@ 0xe0\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r5, #-80]\n+\tldr.w\tr3, [r4, #224]\t@ 0xe0\n+\tldr.w\tr1, [r4, #220]\t@ 0xdc\n \tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r0, #216]\t@ 0xd8\n-\tstrh.w\tr5, [r4, #-80]\n+\tldr.w\tr2, [r4, #212]\t@ 0xd4\n+\tstrd\tr6, r6, [r5, #-76]\t@ 0x4c\n+\tmov\tr6, r0\n \tsubs\tr2, r7, r2\n-\tstr.w\tfp, [r4, #-88]\n+\tstrh.w\tfp, [r5, #-72]\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [r0, #212]\t@ 0xd4\n-\tstr.w\tsl, [r4, #-68]\n+\tldr.w\tr1, [r4, #208]\t@ 0xd0\n+\tstr.w\tsl, [r5, #-60]\n \tmla\tr3, r1, r2, r3\n-\tvmov.32\tr2, d16[1]\n-\tldr.w\tr1, [r0, #176]\t@ 0xb0\n+\tldr.w\tr1, [r4, #172]\t@ 0xac\n+\tldr.w\tr2, [r4, #200]\t@ 0xc8\n \tadd.w\tr1, r1, r3, lsl #3\n-\tsub.w\tr3, r4, #76\t@ 0x4c\n-\tnegs\tr2, r2\n-\tstr.w\tr2, [r4, #-92]\n-\tldr.w\tr2, [r0, #204]\t@ 0xcc\n-\tstr.w\tr1, [r4, #-96]\n-\tvst1.32\t{d16}, [r3]\n+\tldr.w\tr3, [r4, #196]\t@ 0xc4\n+\tstr.w\tr3, [r5, #-64]\n \tsub.w\tr2, sl, r2\n-\tldr.w\tr3, [r0, #208]\t@ 0xd0\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r5, #-84]\n+\tldr.w\tr3, [r4, #204]\t@ 0xcc\n+\tstr.w\tr1, [r5, #-88]\n \tadd\tr3, r2\n-\tstr.w\tr3, [r4, #-64]\n-\tsub.w\tr3, r4, #96\t@ 0x60\n-\tstr\tr3, [sp, #52]\t@ 0x34\n+\tstr.w\tr3, [r5, #-56]\n+\tldr.w\tr3, [r4, #192]\t@ 0xc0\n+\tstr.w\tr3, [r5, #-68]\n+\tsub.w\tr3, r5, #88\t@ 0x58\n \tmov\tr0, r3\n+\tstr\tr3, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n-\tmov\tr5, r0\n-\tldr\tr0, [pc, #256]\t@ (7c0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5c4>)\n-\tmov\tr3, r8\n-\tadd\tr0, pc\n-\tadd.w\tr2, r0, #56\t@ 0x38\n-\tadd.w\tr1, r0, #44\t@ 0x2c\n+\tmov\tr4, r0\n+\tmov\tr3, r6\n+\tldrd\tr0, r2, [sp, #100]\t@ 0x64\n+\tmov\tr1, r0\n \tadds\tr0, #48\t@ 0x30\n+\tadds\tr1, #44\t@ 0x2c\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tr6, r8\n-\tbeq.n\t6da <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x4de>\n-\tmov\tr0, r8\n+\tcmp\tr8, r6\n+\tbeq.n\t6c4 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x4f8>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r4, #-96]\n-\tcmp\tr5, r3\n-\tbeq.n\t6f0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x4f4>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tmov\tr1, r5\n+\tldr.w\tr3, [r5, #-88]\n+\tcmp\tr4, r3\n+\tbeq.n\t6da <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x50e>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr1, r4\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr3, [pc, #208]\t@ (7c4 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5c8>)\n+\tldr\tr3, [pc, #208]\t@ (7ac <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5e0>)\n \tadd\tr3, pc\n-\tadd.w\tr2, r3, #196\t@ 0xc4\n-\tldr.w\tr0, [r3, #180]\t@ 0xb4\n-\tldr.w\tr1, [r3, #224]\t@ 0xe0\n-\tvld1.32\t{d7}, [r2]\n-\tstr\tr0, [sp, #68]\t@ 0x44\n-\tldr.w\tr2, [r3, #212]\t@ 0xd4\n-\tldrd\tr0, lr, [r3, #204]\t@ 0xcc\n-\tstr\tr2, [sp, #72]\t@ 0x48\n-\tldr.w\tr6, [r3, #176]\t@ 0xb0\n-\tvmov.32\tr5, d7[1]\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n+\tldr.w\tr0, [r3, #176]\t@ 0xb0\n+\tldr.w\tr2, [r3, #208]\t@ 0xd0\n+\tldr.w\tr1, [r3, #220]\t@ 0xdc\n+\tstr\tr0, [sp, #64]\t@ 0x40\n+\tldr.w\tip, [r3, #172]\t@ 0xac\n+\tldrd\tr0, lr, [r3, #200]\t@ 0xc8\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tldrd\tr6, r4, [r3, #192]\t@ 0xc0\n \tmul.w\tr2, r2, r7\n-\tstr\tr2, [sp, #84]\t@ 0x54\n-\tvmov\tip, s14\n+\tldr\tr3, [sp, #40]\t@ 0x28\n \tcmp\tr0, lr\n-\tstr\tr1, [sp, #76]\t@ 0x4c\n+\tstr\tr2, [sp, #80]\t@ 0x50\n+\tstr\tr1, [sp, #72]\t@ 0x48\n \tmul.w\tr8, r1, r3\n-\tldr\tr3, [sp, #68]\t@ 0x44\n+\tldr\tr3, [sp, #64]\t@ 0x40\n \tadd\tr2, r3\n \tadd\tr2, r8\n-\tbgt.w\te46 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc4a>\n-\tmla\tr3, r5, r0, r2\n+\tbgt.w\tdfe <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc32>\n+\tmla\tr3, r4, r0, r2\n \tadd.w\tfp, lr, #1\n-\tmul.w\tr1, r5, ip\n-\tvldr\td17, [pc, #116]\t@ 7b8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5bc>\n+\tmul.w\tr1, r6, r4\n+\tvldr\td6, [pc, #124]\t@ 7a0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5d4>\n \tsub.w\tfp, fp, r0\n \tmov.w\tsl, #0\n-\tmla\tr3, ip, r3, r6\n-\tvldr\td16, [r3]\n+\tmla\tr3, r6, r3, ip\n+\tvldr\td7, [r3]\n \tadd.w\tsl, sl, #1\n \tcmp\tfp, sl\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n \tadd\tr3, r1\n-\tbne.n\t752 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x556>\n-\tldr\tr3, [pc, #92]\t@ (7c8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5cc>)\n+\tbne.n\t730 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x564>\n+\tldr\tr3, [pc, #104]\t@ (7b0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5e4>)\n \tadd\tr3, pc\n-\tldr.w\tsl, [r3, #364]\t@ 0x16c\n+\tldr.w\tsl, [r3, #352]\t@ 0x160\n \tcmp.w\tsl, #2048\t@ 0x800\n-\tbgt.n\t79a <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x59e>\n-\tmla\tr3, r5, sl, r2\n-\tvmov.i64\td16, #0x0000000000000000\n+\tbgt.n\t778 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5ac>\n+\tmla\tr3, sl, r4, r2\n+\tvldr\td7, [pc, #60]\t@ 798 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5cc>\n \tmov\tr2, sl\n \tmovw\tfp, #2049\t@ 0x801\n-\tmla\tr3, ip, r3, r6\n+\tmla\tr3, r6, r3, ip\n \tadds\tr2, #1\n-\tvstr\td16, [r3]\n+\tvstr\td7, [r3]\n \tcmp\tr2, fp\n \tadd\tr3, r1\n-\tbne.n\t788 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x58c>\n+\tbne.n\t766 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x59a>\n \tcmp.w\tsl, #0\n-\tble.n\t838 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x63c>\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tldr\tr2, [sp, #84]\t@ 0x54\n+\tble.n\t820 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x654>\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tvmov.f64\td3, #112\t@ 0x3f800000 1.0\n+\tldr\tr2, [sp, #80]\t@ 0x50\n \tadd\tr3, r8\n+\tldr.w\tr8, [pc, #48]\t@ 7b4 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5e8>\n \tadd\tr3, r2\n \tmovs\tr2, #1\n-\tadd\tr3, r5\n-\tmla\tr3, ip, r3, r6\n-\tldr.w\tip, [pc, #28]\t@ 7cc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5d0>\n-\tadd\tip, pc\n-\tb.n\t7e0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5e4>\n-\tnop\n+\tadd\tr3, r4\n+\tadd\tr8, pc\n+\tmla\tr3, r6, r3, ip\n+\tb.n\t7c8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5fc>\n+\tnop.w\n+\t...\n \t.word\t0xdff344ac\n \t.word\t0x402f7fcc\n-\t.word\t0x000000fc\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000000ce\n+\t.word\t0x000001cc\n R_ARM_REL32\t.bss\n-\t.word\t0x0000005a\n+\t.word\t0x000000cc\n R_ARM_REL32\t.bss\n-\t.word\t0x00000016\n+\t.word\t0x00000064\n R_ARM_REL32\t.bss\n-\tvmov.i64\td18, #0x0000000000000000\n+\t.word\t0x00000024\n+ R_ARM_REL32\t.bss\n+\tvldr\td4, [pc, #908]\t@ b48 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x97c>\n \tadds\tr2, #1\n-\tvstr\td18, [r3]\n+\tvstr\td4, [r3]\n \tcmp\tsl, r2\n \tadd\tr3, r1\n-\tblt.n\t838 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x63c>\n-\tvmov\ts13, r2\n-\tvldr\td17, [ip, #376]\t@ 0x178\n-\tvldr\td19, [ip, #384]\t@ 0x180\n-\tvcvt.f64.s32\td16, s13\n-\tvldr\td18, [r3]\n-\tvmul.f64\td16, d16, d17\n-\tvdiv.f64\td17, d16, d19\n-\tvcmpe.f64\td17, #0.0\n+\tblt.n\t820 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x654>\n+\tvmov\ts15, r2\n+\tvldr\td6, [r8, #368]\t@ 0x170\n+\tvldr\td5, [r8, #376]\t@ 0x178\n+\tvcvt.f64.s32\td7, s15\n+\tvldr\td4, [r3]\n+\tvmul.f64\td7, d7, d6\n+\tvdiv.f64\td6, d7, d5\n+\tvcmpe.f64\td6, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbls.n\t7d4 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5d8>\n-\tvcmpe.f64\td17, d20\n+\tbls.n\t7bc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5f0>\n+\tvcmpe.f64\td6, d3\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\t7d0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5d4>\n-\tvmul.f64\td17, d17, d17\n-\tvmov.f64\td16, d20\n+\tbge.n\t7b8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5ec>\n+\tvmul.f64\td6, d6, d6\n+\tvmov.f64\td7, d3\n \tadds\tr2, #1\n \tcmp\tsl, r2\n-\tvmul.f64\td17, d17, d17\n-\tvfms.f64\td16, d17, d17\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td16, d16, d16\n-\tvmul.f64\td18, d18, d16\n-\tvstr\td18, [r3]\n+\tvmul.f64\td6, d6, d6\n+\tvmls.f64\td7, d6, d6\n+\tvmul.f64\td7, d7, d7\n+\tvmul.f64\td7, d7, d7\n+\tvmul.f64\td4, d4, d7\n+\tvstr\td4, [r3]\n \tadd\tr3, r1\n-\tbge.n\t7e0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5e4>\n-\tldr.w\tsl, [pc, #1244]\t@ d18 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb1c>\n-\tvmov.i32\td10, #0\t@ 0x00000000\n+\tbge.n\t7c8 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x5fc>\n+\tldr\tr2, [sp, #60]\t@ 0x3c\n \trsb\tr3, r0, #1\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tadd\tsl, pc\n \tadd\tr3, lr\n-\tstr.w\tr3, [r4, #-24]\n-\tsub.w\tr3, r4, #36\t@ 0x24\n-\tvstr\td10, [r4, #-44]\t@ 0xffffffd4\n-\tnegs\tr5, r5\n-\tstr.w\tr5, [r4, #-52]\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tstr.w\tr3, [r5, #-20]\n \tmov.w\tr8, #8\n-\tvst1.32\t{d7}, [r3]\n-\tmov.w\tfp, #1\n-\tldr.w\tr3, [sl, #228]\t@ 0xe4\n-\tldr\tr1, [sp, #72]\t@ 0x48\n-\tsubs\tr5, r2, r3\n-\tldr\tr3, [sp, #76]\t@ 0x4c\n-\tstr.w\tr8, [r4, #-48]\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tstr.w\tfp, [r4, #-28]\n-\tmul.w\tr5, r3, r5\n-\tldr.w\tr3, [sl, #216]\t@ 0xd8\n+\tldr.w\tr3, [r2, #224]\t@ 0xe0\n+\tmov.w\tsl, #1\n+\tstr.w\tr4, [r5, #-28]\n+\tnegs\tr4, r4\n+\tstr.w\tr4, [r5, #-48]\n+\tsubs\tr4, r1, r3\n+\tldr\tr3, [sp, #72]\t@ 0x48\n+\tmovw\tfp, #769\t@ 0x301\n+\tldr\tr0, [sp, #68]\t@ 0x44\n+\tstr.w\tr6, [r5, #-32]\n+\tmovs\tr6, #0\n+\tstr.w\tr8, [r5, #-44]\n+\tmul.w\tr4, r3, r4\n+\tldr.w\tr3, [r2, #212]\t@ 0xd4\n+\tstrd\tr6, r6, [r5, #-40]\t@ 0x28\n \tsubs\tr3, r7, r3\n-\tmla\tr5, r1, r3, r5\n-\tadd.w\tr5, r6, r5, lsl #3\n-\tmovw\tr6, #769\t@ 0x301\n-\tstr.w\tr5, [r4, #-56]\n-\tstrh.w\tr6, [r4, #-40]\n+\tstr.w\tsl, [r5, #-24]\n+\tstrh.w\tfp, [r5, #-36]\n+\tmla\tr4, r0, r3, r4\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tadd.w\tr4, ip, r4, lsl #3\n+\tstr.w\tr4, [r5, #-52]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, sl, #132\t@ 0x84\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tldr.w\tr1, [sl, #160]\t@ 0xa0\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [sl, #164]\t@ 0xa4\n-\tstr.w\tr8, [r4, #-88]\n+\tstr.w\tr8, [r5, #-80]\n \tmov\tr8, r0\n-\tsubs\tr3, r2, r3\n-\tldr.w\tr2, [sl, #152]\t@ 0x98\n-\tvstr\td10, [r4, #-84]\t@ 0xffffffac\n+\tldr\tr0, [sp, #60]\t@ 0x3c\n+\tldr\tr1, [sp, #40]\t@ 0x28\n+\tstrd\tr6, r6, [r5, #-76]\t@ 0x4c\n+\tldr.w\tr3, [r0, #164]\t@ 0xa4\n+\tldr.w\tr2, [r0, #152]\t@ 0x98\n+\tsubs\tr3, r1, r3\n+\tldr.w\tr1, [r0, #160]\t@ 0xa0\n \tsubs\tr2, r7, r2\n-\tstrh.w\tr6, [r4, #-80]\n+\tstrh.w\tfp, [r5, #-72]\n+\tstr.w\tsl, [r5, #-60]\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [sl, #148]\t@ 0x94\n-\tstr.w\tfp, [r4, #-68]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tldr.w\tr1, [r0, #148]\t@ 0x94\n \tmla\tr3, r1, r2, r3\n-\tvmov.32\tr2, d16[1]\n-\tldr.w\tr1, [sl, #112]\t@ 0x70\n+\tldr\tr1, [r0, #112]\t@ 0x70\n+\tldr.w\tr2, [r0, #140]\t@ 0x8c\n \tadd.w\tr1, r1, r3, lsl #3\n-\tsub.w\tr3, r4, #76\t@ 0x4c\n-\tnegs\tr2, r2\n-\tstr.w\tr2, [r4, #-92]\n-\tldr.w\tr2, [sl, #140]\t@ 0x8c\n-\tstr.w\tr1, [r4, #-96]\n-\tvst1.32\t{d16}, [r3]\n-\tsub.w\tr2, fp, r2\n-\tldr.w\tr3, [sl, #144]\t@ 0x90\n+\tldr.w\tr3, [r0, #136]\t@ 0x88\n+\tstr.w\tr3, [r5, #-64]\n+\tsub.w\tr2, sl, r2\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r5, #-84]\n+\tldr.w\tr3, [r0, #144]\t@ 0x90\n+\tstr.w\tr1, [r5, #-88]\n \tadd\tr3, r2\n-\tstr.w\tr3, [r4, #-64]\n+\tstr.w\tr3, [r5, #-56]\n+\tldr.w\tr3, [r0, #132]\t@ 0x84\n+\tstr.w\tr3, [r5, #-68]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n \tstr\tr0, [sp, #0]\n \tmov\tr6, r0\n-\tldr.w\tr0, [pc, #1032]\t@ d1c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb20>\n-\tadd.w\tr2, sl, #368\t@ 0x170\n+\tldr\tr0, [pc, #616]\t@ (b58 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x98c>)\n+\tldr\tr2, [sp, #108]\t@ 0x6c\n \tmov\tr3, r8\n \tadd\tr0, pc\n \tadd.w\tr1, r0, #44\t@ 0x2c\n \tadds\tr0, #48\t@ 0x30\n \tbl\t0 <__gridxc_radfft_MOD_radfft>\n R_ARM_THM_CALL\t__gridxc_radfft_MOD_radfft\n-\tcmp\tr5, r8\n-\tbeq.n\t930 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x734>\n+\tcmp\tr4, r8\n+\tbeq.n\t90a <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x73e>\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r4, #-96]\n+\tldr.w\tr3, [r5, #-88]\n \tcmp\tr6, r3\n-\tbeq.n\t946 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x74a>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tbeq.n\t920 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x754>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tmov\tr1, r6\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #984]\t@ (d20 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb24>)\n-\tldr\tr1, [sp, #44]\t@ 0x2c\n+\tldr\tr2, [pc, #568]\t@ (b5c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x990>)\n+\tldr\tr1, [sp, #40]\t@ 0x28\n \tadd\tr2, pc\n-\tadd.w\tr3, r2, #132\t@ 0x84\n-\tldr.w\tr6, [r2, #148]\t@ 0x94\n-\tvld1.32\t{d7}, [r3]\n+\tldr.w\tip, [r2, #148]\t@ 0x94\n \tldr\tr3, [r2, #116]\t@ 0x74\n-\tldr.w\tip, [r2, #160]\t@ 0xa0\n-\tldrd\tr5, sl, [r2, #140]\t@ 0x8c\n-\tvmov.32\tr8, d7[1]\n-\tmla\tr3, r6, r7, r3\n-\tldr.w\tlr, [r2, #112]\t@ 0x70\n-\tmla\tr3, ip, r1, r3\n-\tcmp\tr5, sl\n-\tvmov\tr1, s14\n-\tbgt.n\t9a6 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x7aa>\n-\tmla\tr3, r5, r8, r3\n-\tadd.w\tr0, sl, #1\n-\tvldr\td17, [pc, #908]\t@ d10 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb14>\n-\tsubs\tr0, r0, r5\n+\tldr.w\tlr, [r2, #160]\t@ 0xa0\n+\tldrd\tr4, sl, [r2, #140]\t@ 0x8c\n+\tmla\tr3, ip, r7, r3\n+\tldr.w\tr8, [r2, #112]\t@ 0x70\n+\tmla\tr3, lr, r1, r3\n+\tcmp\tr4, sl\n+\tldrd\tfp, r6, [r2, #132]\t@ 0x84\n+\tbgt.n\t974 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x7a8>\n+\tmla\tr3, r6, r4, r3\n+\tadd.w\tr1, sl, #1\n+\tmul.w\tr0, fp, r6\n+\tvldr\td6, [pc, #504]\t@ b50 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x984>\n+\tsubs\tr1, r1, r4\n \tmovs\tr2, #0\n-\tmla\tr3, r1, r3, lr\n-\tmul.w\tr1, r1, r8\n-\tvldr\td16, [r3]\n+\tmla\tr3, fp, r3, r8\n+\tvldr\td7, [r3]\n \tadds\tr2, #1\n-\tcmp\tr0, r2\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td16, [r3]\n-\tadd\tr3, r1\n-\tbne.n\t992 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x796>\n-\trsb\tr3, r5, #1\n-\tldr\tr5, [pc, #888]\t@ (d24 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb28>)\n-\tvmov.i32\td10, #0\t@ 0x00000000\n+\tcmp\tr1, r2\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tadd\tr3, r0\n+\tbne.n\t960 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x794>\n+\trsb\tr3, r4, #1\n+\tldr\tr4, [pc, #484]\t@ (b60 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x994>)\n+\tldr\tr1, [sp, #40]\t@ 0x28\n \tadd\tr3, sl\n-\tadd\tr5, pc\n-\tstr.w\tr3, [r4, #-24]\n-\trsb\tr3, r8, #0\n-\tstr.w\tr3, [r4, #-52]\n-\tsub.w\tr3, r4, #36\t@ 0x24\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvstr\td10, [r4, #-44]\t@ 0xffffffd4\n-\tadd\tr1, sp, #136\t@ 0x88\n-\tldr.w\tr2, [r5, #164]\t@ 0xa4\n+\tadd\tr4, pc\n+\tstr.w\tr3, [r5, #-20]\n+\tsub.w\tr3, r5, #112\t@ 0x70\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\td7, [pc, #444]\t@ b48 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x97c>\n \tmov.w\tsl, #1\n-\tvst1.32\t{d7}, [r3]\n-\tmovw\tr8, #769\t@ 0x301\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tsub.w\tfp, r4, #112\t@ 0x70\n-\tstr\tr1, [sp, #68]\t@ 0x44\n-\tsubs\tr2, r3, r2\n-\tldr.w\tr3, [r5, #152]\t@ 0x98\n-\tldr\tr1, [sp, #52]\t@ 0x34\n+\tldr.w\tr3, [r4, #164]\t@ 0xa4\n+\tsub.w\tr2, r5, #96\t@ 0x60\n+\tstr.w\tfp, [r5, #-32]\n+\tmovw\tfp, #769\t@ 0x301\n+\tsubs\tr3, r1, r3\n+\tstr.w\tr6, [r5, #-28]\n+\tstr.w\tsl, [r5, #-24]\n+\tnegs\tr6, r6\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tmul.w\tr1, lr, r3\n+\tldr.w\tr3, [r4, #152]\t@ 0x98\n+\tstr.w\tr6, [r5, #-48]\n+\tmovs\tr6, #0\n \tsubs\tr3, r7, r3\n-\tstr.w\tsl, [r4, #-28]\n-\tmul.w\tr2, ip, r2\n-\tstrh.w\tr8, [r4, #-40]\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tmla\tr6, r6, r3, r2\n+\tstrd\tr6, r6, [r5, #-40]\t@ 0x28\n+\tstrh.w\tfp, [r5, #-36]\n+\tstr\tr2, [sp, #68]\t@ 0x44\n+\tmla\tr1, ip, r3, r1\n \tmovs\tr3, #8\n-\tstr.w\tr3, [r4, #-48]\n-\tvstr\td16, [r1, #-8]\n-\tadd.w\tr6, lr, r6, lsl #3\n-\tstr.w\tr6, [r4, #-56]\n-\tvstr\td16, [r4, #-112]\t@ 0xffffff90\n-\tvstr\td16, [sp, #136]\t@ 0x88\n-\tvstr\td16, [r4, #-120]\t@ 0xffffff88\n+\tstr.w\tr3, [r5, #-44]\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tadd.w\tr8, r8, r1, lsl #3\n+\tstr.w\tr8, [r5, #-52]\n+\tvstr\td7, [r5, #-104]\t@ 0xffffff98\n+\tvstr\td7, [r5, #-96]\t@ 0xffffffa0\n+\tvstr\td7, [r3, #-8]\n+\tvstr\td7, [r5, #-112]\t@ 0xffffff90\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n+\tldr\tr1, [sp, #40]\t@ 0x28\n \tmovs\tr3, #8\n-\tstr.w\tr3, [r4, #-88]\n-\tadd.w\tr3, r5, #260\t@ 0x104\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tldr.w\tr1, [r5, #280]\t@ 0x118\n-\tstr.w\tsl, [r4, #-68]\n-\tmov\tsl, r0\n-\tvld1.32\t{d16}, [r3]\n-\tsubs\tr1, r7, r1\n-\tldr.w\tr3, [r5, #292]\t@ 0x124\n-\tvstr\td10, [r4, #-84]\t@ 0xffffffac\n-\tsubs\tr3, r2, r3\n-\tldr.w\tr2, [r5, #288]\t@ 0x120\n-\tstrh.w\tr8, [r4, #-80]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tmul.w\tr3, r2, r3\n-\tldr.w\tr2, [r5, #276]\t@ 0x114\n-\tmla\tr3, r2, r1, r3\n-\tvmov.32\tr2, d16[1]\n-\tldr.w\tr1, [r5, #268]\t@ 0x10c\n-\trsb\tr1, r1, #1\n-\tnegs\tr2, r2\n-\tstr.w\tr2, [r4, #-92]\n-\tldr.w\tr2, [r5, #240]\t@ 0xf0\n-\tadd.w\tr2, r2, r3, lsl #3\n-\tsub.w\tr3, r4, #76\t@ 0x4c\n-\tstr.w\tr2, [r4, #-96]\n-\tvst1.32\t{d16}, [r3]\n-\tldr.w\tr3, [r5, #272]\t@ 0x110\n-\tadd\tr3, r1\n-\tstr.w\tr3, [r4, #-64]\n+\tstr.w\tr3, [r5, #-80]\n+\tldr.w\tr3, [r4, #284]\t@ 0x11c\n+\tstrd\tr6, r6, [r5, #-76]\t@ 0x4c\n+\tmov\tr6, r0\n+\tsubs\tr3, r1, r3\n+\tldr.w\tr1, [r4, #280]\t@ 0x118\n+\tldr.w\tr0, [r4, #272]\t@ 0x110\n+\tstr.w\tsl, [r5, #-60]\n+\tsubs\tr0, r7, r0\n+\tstrh.w\tfp, [r5, #-72]\n+\tmul.w\tr3, r1, r3\n+\tldr.w\tr1, [r4, #268]\t@ 0x10c\n+\tmla\tr3, r1, r0, r3\n+\tldr.w\tr1, [r4, #232]\t@ 0xe8\n+\tldr.w\tr0, [r4, #260]\t@ 0x104\n+\tadd.w\tr1, r1, r3, lsl #3\n+\tldr.w\tr3, [r4, #256]\t@ 0x100\n+\tstr.w\tr3, [r5, #-64]\n+\tsub.w\tr0, sl, r0\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r5, #-84]\n+\tldr.w\tr3, [r4, #264]\t@ 0x108\n+\tstr.w\tr1, [r5, #-88]\n+\tadd\tr0, r3\n+\tldr.w\tr3, [r4, #252]\t@ 0xfc\n+\tstr.w\tr0, [r5, #-56]\n+\tstr.w\tr3, [r5, #-68]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tldr\tr2, [pc, #656]\t@ (d28 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb2c>)\n-\tmov\tr8, r0\n-\tsub.w\tr1, r4, #104\t@ 0x68\n+\tldr\tr2, [sp, #68]\t@ 0x44\n+\tstr\tr2, [sp, #0]\n+\tmov\tsl, r0\n+\tldr\tr2, [pc, #252]\t@ (b64 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x998>)\n+\tadd.w\tr0, r4, #104\t@ 0x68\n+\tsub.w\tr3, r5, #104\t@ 0x68\n+\tmov\tr1, r6\n \tadd\tr2, pc\n-\tstr\tr1, [sp, #0]\n-\tmov\tr3, fp\n-\tadd.w\tr0, r5, #104\t@ 0x68\n+\tstr.w\tsl, [sp, #4]\n \tadds\tr2, #64\t@ 0x40\n-\tmov\tr1, sl\n-\tstr.w\tr8, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n-\tcmp\tr6, sl\n-\tbeq.n\tabc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x8c0>\n-\tmov\tr0, sl\n+\tcmp\tr8, r6\n+\tbeq.n\ta86 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x8ba>\n+\tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r4, #-96]\n-\tcmp\tr8, r3\n-\tbeq.n\tad2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x8d6>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tmov\tr1, r8\n+\tldr.w\tr3, [r5, #-88]\n+\tcmp\tsl, r3\n+\tbeq.n\ta9c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x8d0>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr1, sl\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tmov\tr0, r8\n+\tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tsl, [pc, #600]\t@ d2c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb30>\n-\tvmov.i32\td10, #0\t@ 0x00000000\n-\tsub.w\tr3, r4, #36\t@ 0x24\n-\tmov.w\tfp, #8\n+\tldr.w\tsl, [pc, #200]\t@ b68 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x99c>\n+\tmovs\tr4, #0\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tmovw\tfp, #769\t@ 0x301\n \tadd\tsl, pc\n-\tstr.w\tfp, [r4, #-48]\n-\tadd.w\tr2, sl, #196\t@ 0xc4\n-\tmovs\tr6, #1\n-\tvstr\td10, [r4, #-44]\t@ 0xffffffd4\n-\tldr.w\tr5, [sl, #224]\t@ 0xe0\n-\tvld1.32\t{d16}, [r2]\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tldr\tr0, [sp, #60]\t@ 0x3c\n-\tvst1.32\t{d16}, [r3]\n-\tldr.w\tr3, [sl, #228]\t@ 0xe4\n-\tstr.w\tr6, [r4, #-28]\n+\tstrd\tr4, r4, [r5, #-40]\t@ 0x28\n+\tldr\tr0, [sp, #56]\t@ 0x38\n+\tstrh.w\tfp, [r5, #-36]\n+\tldr.w\tr3, [sl, #224]\t@ 0xe0\n+\tldr.w\tr6, [sl, #220]\t@ 0xdc\n \tsubs\tr1, r2, r3\n-\tldr.w\tr2, [sl, #216]\t@ 0xd8\n-\tldr.w\tr3, [sl, #212]\t@ 0xd4\n+\tldr.w\tr2, [sl, #212]\t@ 0xd4\n+\tldr.w\tr3, [sl, #208]\t@ 0xd0\n \tsubs\tr2, r7, r2\n-\tmul.w\tr1, r5, r1\n-\tmovw\tr5, #769\t@ 0x301\n-\tstrh.w\tr5, [r4, #-40]\n+\tmul.w\tr1, r6, r1\n+\tmovs\tr6, #1\n+\tstr.w\tr6, [r5, #-24]\n \tmla\tr1, r3, r2, r1\n-\tvmov.32\tr3, d16[1]\n-\tldr.w\tr2, [sl, #176]\t@ 0xb0\n+\tldr.w\tr2, [sl, #172]\t@ 0xac\n+\tldr.w\tr3, [sl, #200]\t@ 0xc8\n \tadd.w\tr8, r2, r1, lsl #3\n-\tldr.w\tr2, [sl, #208]\t@ 0xd0\n-\tnegs\tr3, r3\n-\tstr.w\tr3, [r4, #-52]\n-\tldr.w\tr3, [sl, #204]\t@ 0xcc\n-\tstr.w\tr8, [r4, #-56]\n+\tldr.w\tr2, [sl, #196]\t@ 0xc4\n+\tstr.w\tr2, [r5, #-28]\n \trsb\tr3, r3, #1\n+\tnegs\tr2, r2\n+\tstr.w\tr2, [r5, #-48]\n+\tldr.w\tr2, [sl, #204]\t@ 0xcc\n+\tstr.w\tr8, [r5, #-52]\n \tadd\tr3, r2\n-\tstr.w\tr3, [r4, #-24]\n+\tstr.w\tr3, [r5, #-20]\n+\tldr.w\tr3, [sl, #192]\t@ 0xc0\n+\tstr.w\tr3, [r5, #-32]\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r5, #-44]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tadd.w\tr3, sl, #324\t@ 0x144\n-\tldr\tr2, [sp, #44]\t@ 0x2c\n-\tldr.w\tr1, [sl, #352]\t@ 0x160\n-\tvld1.32\t{d16}, [r3]\n-\tldr.w\tr3, [sl, #356]\t@ 0x164\n-\tstr.w\tr6, [r4, #-68]\n-\tmov\tr6, r0\n+\tldr\tr2, [sp, #40]\t@ 0x28\n+\tmovs\tr3, #8\n+\tstr.w\tr3, [r5, #-80]\n+\tldr.w\tr3, [sl, #344]\t@ 0x158\n+\tldr.w\tr1, [sl, #340]\t@ 0x154\n \tsubs\tr3, r2, r3\n-\tldr.w\tr2, [sl, #344]\t@ 0x158\n-\tvstr\td10, [r4, #-84]\t@ 0xffffffac\n+\tldr.w\tr2, [sl, #332]\t@ 0x14c\n+\tstrd\tr4, r4, [r5, #-76]\t@ 0x4c\n \tsubs\tr2, r7, r2\n-\tstrh.w\tr5, [r4, #-80]\n+\tstr.w\tr6, [r5, #-60]\n \tmul.w\tr3, r1, r3\n-\tldr.w\tr1, [sl, #340]\t@ 0x154\n-\tstr.w\tfp, [r4, #-88]\n-\tldr\tr0, [sp, #52]\t@ 0x34\n+\tldr.w\tr1, [sl, #328]\t@ 0x148\n+\tmov\tr6, r0\n+\tstrh.w\tfp, [r5, #-72]\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tb.n\tb6c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x9a0>\n+\tnop\n+\t...\n+\t.word\t0x71d77959\n+\t.word\t0x3fb0411e\n+\t.word\t0x00000260\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x00000234\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000001de\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000f0\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x000000bc\n+ R_ARM_REL32\t.bss\n \tmla\tr3, r1, r2, r3\n-\tldr.w\tr1, [sl, #304]\t@ 0x130\n-\tvmov.32\tr2, d16[1]\n+\tldr.w\tr1, [sl, #292]\t@ 0x124\n+\tldr.w\tr2, [sl, #320]\t@ 0x140\n \tadd.w\tr1, r1, r3, lsl #3\n-\tsub.w\tr3, r4, #76\t@ 0x4c\n-\tstr.w\tr1, [r4, #-96]\n-\tnegs\tr2, r2\n-\tstr.w\tr2, [r4, #-92]\n-\tvst1.32\t{d16}, [r3]\n-\tldr.w\tr3, [sl, #364]\t@ 0x16c\n-\tldr.w\tr2, [sl, #332]\t@ 0x14c\n-\tadds\tr3, #1\n-\tstr.w\tr3, [r4, #-132]\n-\tldr.w\tr3, [sl, #336]\t@ 0x150\n+\tldr.w\tr3, [sl, #316]\t@ 0x13c\n+\tstr.w\tr3, [r5, #-64]\n \trsb\tr2, r2, #1\n+\tnegs\tr3, r3\n+\tstr.w\tr3, [r5, #-84]\n+\tldr.w\tr3, [sl, #352]\t@ 0x160\n+\tstr.w\tr1, [r5, #-88]\n+\tadds\tr3, #1\n+\tstr.w\tr3, [r5, #-124]\n+\tldr.w\tr3, [sl, #324]\t@ 0x144\n \tadd\tr3, r2\n-\tstr.w\tr3, [r4, #-64]\n+\tstr.w\tr3, [r5, #-56]\n+\tldr.w\tr3, [sl, #312]\t@ 0x138\n+\tstr.w\tr3, [r5, #-68]\n \tbl\t0 <_gfortran_internal_pack>\n R_ARM_THM_CALL\t_gfortran_internal_pack\n-\tsub.w\tr3, r4, #120\t@ 0x78\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tmov\tr4, r0\n \tstr\tr3, [sp, #0]\n-\tmov\tr5, r0\n-\tldr\tr3, [sp, #68]\t@ 0x44\n-\tadd.w\tr0, sl, #376\t@ 0x178\n+\tadd.w\tr0, sl, #368\t@ 0x170\n+\tsub.w\tr3, r5, #120\t@ 0x78\n+\tsub.w\tr2, r5, #124\t@ 0x7c\n \tmov\tr1, r6\n-\tstr\tr5, [sp, #4]\n-\tsubs\tr2, r3, #4\n+\tstr\tr4, [sp, #4]\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_dx>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_dx\n \tcmp\tr8, r6\n-\tbeq.n\tbec <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x9f0>\n+\tbeq.n\tbd6 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa0a>\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr.w\tr3, [r4, #-96]\n-\tcmp\tr5, r3\n-\tbeq.n\tc02 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa06>\n-\tldr\tr0, [sp, #52]\t@ 0x34\n-\tmov\tr1, r5\n+\tldr.w\tr3, [r5, #-88]\n+\tcmp\tr4, r3\n+\tbeq.n\tbec <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa20>\n+\tldr\tr0, [sp, #48]\t@ 0x30\n+\tmov\tr1, r4\n \tbl\t0 <_gfortran_internal_unpack>\n R_ARM_THM_CALL\t_gfortran_internal_unpack\n-\tmov\tr0, r5\n+\tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr5, [pc, #300]\t@ (d30 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb34>)\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, pc\n-\tldr.w\tip, [r5, #116]\t@ 0x74\n-\tldr.w\tr8, [r5, #148]\t@ 0x94\n-\tldr.w\tlr, [r5, #160]\t@ 0xa0\n-\tldrd\tr2, r1, [r5, #140]\t@ 0x8c\n+\tldr\tr4, [pc, #544]\t@ (e10 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc44>)\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr4, pc\n+\tldr.w\tip, [r4, #116]\t@ 0x74\n+\tldr.w\tr8, [r4, #148]\t@ 0x94\n+\tldr.w\tlr, [r4, #160]\t@ 0xa0\n+\tldrd\tr2, r1, [r4, #140]\t@ 0x8c\n \tmla\tr6, r8, r7, ip\n-\tldr.w\tsl, [r5, #112]\t@ 0x70\n+\tldr.w\tsl, [r4, #112]\t@ 0x70\n \tmla\tip, r8, r3, ip\n-\tldr.w\tr0, [r5, #136]\t@ 0x88\n+\tldr.w\tr0, [r4, #136]\t@ 0x88\n \tmla\tr6, lr, r3, r6\n \tcmp\tr2, r1\n \tmla\tip, lr, r7, ip\n-\tbgt.n\tc6e <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa72>\n+\tbgt.n\tc58 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa8c>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #132]\t@ 0x84\n+\tldr.w\tr4, [r4, #132]\t@ 0x84\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr6, r2\n \tadd\tr2, ip\n-\tmul.w\tr0, r5, r0\n+\tmul.w\tr0, r4, r0\n \tmov\tip, r9\n-\tmul.w\tr6, r5, r6\n-\tmul.w\tr2, r5, r2\n+\tmul.w\tr6, r4, r6\n+\tmul.w\tr2, r4, r2\n \tadd.w\tr3, sl, r6\n \tsubs\tr6, r2, r6\n \tmovs\tr2, #0\n-\tadds\tr5, r6, r3\n+\tadds\tr4, r6, r3\n \tadds\tr2, #1\n \tldrd\tr8, r9, [r3]\n \tcmp\tr1, r2\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r5]\n-\tbne.n\tc5a <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa5e>\n+\tstrd\tr8, r9, [r4]\n+\tbne.n\tc44 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xa78>\n \tmov\tr9, ip\n-\tldr\tr5, [pc, #196]\t@ (d34 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb38>)\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, pc\n-\tldr.w\tip, [r5, #180]\t@ 0xb4\n-\tldr.w\tr8, [r5, #212]\t@ 0xd4\n-\tldr.w\tlr, [r5, #224]\t@ 0xe0\n-\tldrd\tr2, r1, [r5, #204]\t@ 0xcc\n+\tldr\tr4, [pc, #440]\t@ (e14 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc48>)\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr4, pc\n+\tldr.w\tip, [r4, #176]\t@ 0xb0\n+\tldr.w\tr8, [r4, #208]\t@ 0xd0\n+\tldr.w\tlr, [r4, #220]\t@ 0xdc\n+\tldrd\tr2, r1, [r4, #200]\t@ 0xc8\n \tmla\tr6, r8, r7, ip\n-\tldr.w\tsl, [r5, #176]\t@ 0xb0\n+\tldr.w\tsl, [r4, #172]\t@ 0xac\n \tmla\tip, r8, r3, ip\n-\tldr.w\tr0, [r5, #200]\t@ 0xc8\n+\tldr.w\tr0, [r4, #196]\t@ 0xc4\n \tmla\tr6, lr, r3, r6\n \tcmp\tr2, r1\n \tmla\tip, lr, r7, ip\n-\tbgt.n\tcda <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xade>\n+\tbgt.n\tcc4 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xaf8>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #196]\t@ 0xc4\n+\tldr.w\tr4, [r4, #192]\t@ 0xc0\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr6, r2\n \tadd\tr2, ip\n-\tmul.w\tr0, r5, r0\n+\tmul.w\tr0, r4, r0\n \tmov\tip, r9\n-\tmul.w\tr6, r5, r6\n-\tmul.w\tr2, r5, r2\n+\tmul.w\tr6, r4, r6\n+\tmul.w\tr2, r4, r2\n \tadd.w\tr3, sl, r6\n \tsubs\tr6, r2, r6\n \tmovs\tr2, #0\n-\tadds\tr5, r3, r6\n+\tadds\tr4, r3, r6\n \tadds\tr2, #1\n \tldrd\tr8, r9, [r3]\n-\tcmp\tr2, r1\n+\tcmp\tr1, r2\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r5]\n-\tbne.n\tcc6 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xaca>\n+\tstrd\tr8, r9, [r4]\n+\tbne.n\tcb0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xae4>\n \tmov\tr9, ip\n-\tldr\tr5, [pc, #92]\t@ (d38 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb3c>)\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, pc\n-\tldr.w\tip, [r5, #244]\t@ 0xf4\n-\tldr.w\tr8, [r5, #276]\t@ 0x114\n-\tldr.w\tlr, [r5, #288]\t@ 0x120\n-\tldrd\tr2, r1, [r5, #268]\t@ 0x10c\n+\tldr\tr4, [pc, #336]\t@ (e18 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc4c>)\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr4, pc\n+\tldr.w\tip, [r4, #236]\t@ 0xec\n+\tldr.w\tr8, [r4, #268]\t@ 0x10c\n+\tldr.w\tlr, [r4, #280]\t@ 0x118\n+\tldrd\tr2, r1, [r4, #260]\t@ 0x104\n \tmla\tr6, r8, r7, ip\n-\tldr.w\tsl, [r5, #240]\t@ 0xf0\n+\tldr.w\tsl, [r4, #232]\t@ 0xe8\n \tmla\tip, r8, r3, ip\n-\tldr.w\tr0, [r5, #264]\t@ 0x108\n+\tldr.w\tr0, [r4, #256]\t@ 0x100\n \tmla\tr6, lr, r3, r6\n \tcmp\tr2, r1\n \tmla\tip, lr, r7, ip\n-\tbgt.n\td76 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb7a>\n-\tb.n\td3c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb40>\n-\tnop\n-\t.word\t0x71d77959\n-\t.word\t0x3fb0411e\n-\t.word\t0x000004ce\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003fe\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000003d2\n- R_ARM_REL32\t.bss\n-\t.word\t0x0000036e\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000288\n- R_ARM_REL32\t.rodata\n-\t.word\t0x00000246\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000126\n- R_ARM_REL32\t.bss\n-\t.word\t0x000000be\n- R_ARM_REL32\t.bss\n-\t.word\t0x00000056\n- R_ARM_REL32\t.bss\n+\tbgt.n\td30 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb64>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #260]\t@ 0x104\n+\tldr.w\tr4, [r4, #252]\t@ 0xfc\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr6, r2\n \tadd\tr2, ip\n-\tmul.w\tr0, r5, r0\n+\tmul.w\tr0, r4, r0\n \tmov\tip, r9\n-\tmul.w\tr6, r5, r6\n-\tmul.w\tr2, r5, r2\n+\tmul.w\tr6, r4, r6\n+\tmul.w\tr2, r4, r2\n \tadd.w\tr3, sl, r6\n \tsubs\tr6, r2, r6\n \tmovs\tr2, #0\n-\tadds\tr5, r6, r3\n+\tadds\tr4, r6, r3\n \tadds\tr2, #1\n \tldrd\tr8, r9, [r3]\n-\tcmp\tr2, r1\n+\tcmp\tr1, r2\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r5]\n-\tbne.n\td62 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb66>\n+\tstrd\tr8, r9, [r4]\n+\tbne.n\td1c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xb50>\n \tmov\tr9, ip\n-\tldr\tr5, [pc, #224]\t@ (e58 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc5c>)\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tadd\tr5, pc\n-\tldr.w\tip, [r5, #308]\t@ 0x134\n-\tldr.w\tr8, [r5, #340]\t@ 0x154\n-\tldr.w\tlr, [r5, #352]\t@ 0x160\n-\tldrd\tr2, r1, [r5, #332]\t@ 0x14c\n+\tldr\tr4, [pc, #232]\t@ (e1c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc50>)\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadd\tr4, pc\n+\tldr.w\tip, [r4, #296]\t@ 0x128\n+\tldr.w\tr8, [r4, #328]\t@ 0x148\n+\tldr.w\tlr, [r4, #340]\t@ 0x154\n+\tldrd\tr2, r1, [r4, #320]\t@ 0x140\n \tmla\tr6, r8, r7, ip\n-\tldr.w\tsl, [r5, #304]\t@ 0x130\n+\tldr.w\tsl, [r4, #292]\t@ 0x124\n \tmla\tip, r8, r3, ip\n-\tldr.w\tr0, [r5, #328]\t@ 0x148\n+\tldr.w\tr0, [r4, #316]\t@ 0x13c\n \tmla\tr6, lr, r3, r6\n \tcmp\tr2, r1\n \tmla\tip, lr, r7, ip\n-\tbgt.w\t3d2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1d6>\n+\tbgt.w\t3ac <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1e0>\n \tadds\tr1, #1\n-\tldr.w\tr5, [r5, #324]\t@ 0x144\n+\tldr.w\tr4, [r4, #312]\t@ 0x138\n \tsubs\tr1, r1, r2\n \tmul.w\tr2, r0, r2\n \tadd\tr6, r2\n \tadd\tr2, ip\n-\tmul.w\tr0, r5, r0\n+\tmul.w\tr0, r4, r0\n \tmov\tip, r9\n-\tmul.w\tr6, r5, r6\n-\tmul.w\tr2, r5, r2\n+\tmul.w\tr6, r4, r6\n+\tmul.w\tr2, r4, r2\n \tadd.w\tr3, sl, r6\n \tsubs\tr6, r2, r6\n \tmovs\tr2, #0\n-\tadds\tr5, r6, r3\n+\tadds\tr4, r6, r3\n \tadds\tr2, #1\n \tldrd\tr8, r9, [r3]\n-\tcmp\tr1, r2\n+\tcmp\tr2, r1\n \tadd\tr3, r0\n-\tstrd\tr8, r9, [r5]\n-\tbne.n\tdd0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xbd4>\n+\tstrd\tr8, r9, [r4]\n+\tbne.n\td8a <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xbbe>\n \tmov\tr9, ip\n-\tb.w\t3d2 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1d6>\n+\tb.w\t3ac <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1e0>\n \tldr\tr6, [sp, #112]\t@ 0x70\n \tadds\tr6, #1\n \tcmp\tr6, #5\n-\tbne.w\t3b0 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1b4>\n-\tldr.w\tr8, [sp, #120]\t@ 0x78\n-\tmov\tr5, r4\n+\tbne.w\t388 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x1bc>\n+\tmov\tsl, r9\n \tldr\tr7, [sp, #124]\t@ 0x7c\n-\tadd.w\tr8, r8, #1\n-\tldr\tr4, [sp, #116]\t@ 0x74\n-\tcmp.w\tr8, #7\n-\tbne.w\t390 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x194>\n+\tldrd\tr4, r9, [sp, #116]\t@ 0x74\n+\tmov\tr8, r5\n+\tadd.w\tr9, r9, #1\n+\tcmp.w\tr9, #7\n+\tbne.w\t366 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x19a>\n \tadds\tr4, #1\n-\tmov\tfp, r9\n-\tmov\tr7, r5\n+\tmov\tfp, sl\n \tcmp\tr4, #5\n-\tbne.w\t376 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x17a>\n-\tldr\tr3, [pc, #68]\t@ (e5c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc60>)\n+\tbne.w\t352 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x186>\n+\tldr\tr3, [pc, #80]\t@ (e20 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc54>)\n \tmovs\tr2, #1\n-\tadd.w\tr1, sp, #16640\t@ 0x4100\n+\tadd.w\tr1, sp, #16512\t@ 0x4080\n \tadd\tr3, pc\n-\tadds\tr1, #4\n-\tstr.w\tr2, [r3, #392]\t@ 0x188\n-\tldr\tr2, [pc, #56]\t@ (e60 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc64>)\n-\tldr\tr3, [pc, #60]\t@ (e64 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc68>)\n+\tadds\tr1, #124\t@ 0x7c\n+\tstr.w\tr2, [r3, #384]\t@ 0x180\n+\tldr\tr2, [pc, #68]\t@ (e24 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc58>)\n+\tldr\tr3, [pc, #72]\t@ (e28 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc5c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r1, #0]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\te54 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc58>\n+\tbne.n\te0c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0xc40>\n \tadd.w\tsp, sp, #16640\t@ 0x4100\n-\tadd\tsp, #12\n-\tvpop\t{d8-d10}\n+\tadd\tsp, #4\n+\tvpop\t{d8-d13}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tmul.w\tr1, r5, ip\n-\tb.n\t768 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x56c>\n+\tmul.w\tr1, r6, r4\n+\tb.n\t746 <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x57a>\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0>\n-\tb.w\t25c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x60>\n+\tb.w\t22c <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0+0x60>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x000000da\n+\t.word\t0x0000021c\n R_ARM_REL32\t.bss\n-\t.word\t0x0000003c\n+\t.word\t0x000001b4\n R_ARM_REL32\t.bss\n-\t.word\t0x00000034\n+\t.word\t0x0000014c\n+ R_ARM_REL32\t.bss\n+\t.word\t0x000000e4\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000048\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000040\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00000e68 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta>:\n+00000e2c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta>:\n __gridxc_vv_vdwxc_MOD_vv_vdw_theta():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #2304]\t@ 0x900\n-\tldr\tr5, [pc, #616]\t@ (10e8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x280>)\n-\tsubw\tsp, sp, #1692\t@ 0x69c\n-\tldr\tr4, [pc, #616]\t@ (10ec <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x284>)\n+\tstr.w\tr0, [ip, #2224]\t@ 0x8b0\n+\tldr\tr5, [pc, #620]\t@ (10b0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x284>)\n+\tsubw\tsp, sp, #1772\t@ 0x6ec\n+\tldr\tr4, [pc, #620]\t@ (10b4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x288>)\n \tadd\tr5, pc\n \tldr\tr0, [r0, #0]\n \tcmp\tr0, #0\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n-\tstr.w\tr4, [sp, #1684]\t@ 0x694\n+\tstr.w\tr4, [sp, #1764]\t@ 0x6e4\n \tmov.w\tr4, #0\n-\tstr\tr3, [sp, #72]\t@ 0x48\n-\tldr\tr3, [pc, #596]\t@ (10f0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x288>)\n-\tldr.w\tr4, [sp, #1792]\t@ 0x700\n-\tadd\tr3, pc\n-\tstr\tr3, [sp, #56]\t@ 0x38\n-\tldr.w\tr3, [sp, #1796]\t@ 0x704\n-\tstr\tr4, [sp, #76]\t@ 0x4c\n-\tstr\tr0, [sp, #44]\t@ 0x2c\n-\tstr\tr3, [sp, #240]\t@ 0xf0\n-\tble.w\t1bb0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xd48>\n+\tstrd\tr0, r3, [sp, #92]\t@ 0x5c\n+\tldr\tr3, [pc, #600]\t@ (10b8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x28c>)\n+\tldr.w\tr4, [sp, #1872]\t@ 0x750\n+\tadd\tr3, pc\n+\tstr\tr3, [sp, #64]\t@ 0x40\n+\tldr.w\tr3, [sp, #1876]\t@ 0x754\n+\tstr\tr4, [sp, #100]\t@ 0x64\n+\tstr\tr3, [sp, #192]\t@ 0xc0\n+\tble.w\t1d3e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xf12>\n \tmov\tr4, r2\n \tvldr\td8, [r1]\n \tcmp\tr0, #1\n-\tbeq.w\t1b96 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xd2e>\n-\tvldr\td22, [r1, #8]\n-\tadd.w\tr9, sp, #672\t@ 0x2a0\n-\tvldr\td18, [r2, #24]\n-\tvldr\td21, [r2]\n-\tvldr\td17, [r2, #32]\n-\tvadd.f64\td8, d8, d22\n-\tvldr\td20, [r2, #8]\n-\tvldr\td16, [r2, #40]\t@ 0x28\n-\tvadd.f64\td18, d18, d21\n-\tvldr\td19, [r2, #16]\n-\tvadd.f64\td17, d17, d20\n-\tvadd.f64\td16, d16, d19\n-\tvstr\td18, [r9]\n-\tvstr\td17, [r9, #8]\n-\tvstr\td16, [r9, #16]\n-\tvldr\td16, [pc, #452]\t@ 10c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x258>\n-\tvcmpe.f64\td8, d16\n+\tbeq.w\t1d24 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xef8>\n+\tvldr\td1, [r1, #8]\n+\tadd.w\tsl, sp, #752\t@ 0x2f0\n+\tvldr\td5, [r2, #24]\n+\tvldr\td2, [r2]\n+\tvldr\td6, [r2, #32]\n+\tvadd.f64\td8, d8, d1\n+\tvldr\td3, [r2, #8]\n+\tvldr\td7, [r2, #40]\t@ 0x28\n+\tvadd.f64\td5, d5, d2\n+\tvldr\td4, [r2, #16]\n+\tvadd.f64\td6, d6, d3\n+\tvadd.f64\td7, d7, d4\n+\tvstr\td5, [sl]\n+\tvstr\td6, [sl, #8]\n+\tvstr\td7, [sl, #16]\n+\tvldr\td7, [pc, #456]\t@ 1088 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x25c>\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t1efe <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1096>\n-\tvldr\td0, [pc, #444]\t@ 10c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x260>\n+\tbmi.w\t20d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12ac>\n+\tvldr\td0, [pc, #448]\t@ 1090 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x264>\n \tvmul.f64\td0, d8, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [r9, #8]\n-\tvldr\td18, [r9]\n-\tvmov.f64\td23, #112\t@ 0x3f800000 1.0\n-\tvldr\td21, [r9, #16]\n-\tvmov.f64\td12, d0\n-\tvmul.f64\td19, d17, d17\n-\tldr\tr3, [pc, #452]\t@ (10f4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x28c>)\n-\tvfma.f64\td19, d18, d18\n-\tvldr\td22, [pc, #412]\t@ 10d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x268>\n-\tvdiv.f64\td10, d23, d8\n+\tvldr\td6, [sl, #8]\n+\tvldr\td5, [sl]\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n+\tvldr\td3, [sl, #16]\n+\tmovs\tr2, #0\n+\tvmul.f64\td4, d6, d6\n+\tldr\tr3, [pc, #460]\t@ (10bc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x290>)\n+\tvmla.f64\td4, d5, d5\n+\tvldr\td2, [pc, #416]\t@ 1098 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x26c>\n+\tvdiv.f64\td9, d1, d8\n \tadd\tr3, pc\n-\tvmov.i32\tq12, #0\t@ 0x00000000\n-\tvfma.f64\td19, d21, d21\n-\tldr\tr2, [r3, #0]\n-\tadd\tr3, sp, #648\t@ 0x288\n-\tstr\tr3, [sp, #408]\t@ 0x198\n-\tadd\tr3, sp, #624\t@ 0x270\n-\tvst1.8\t{d24-d25}, [r3 :64]\n-\tvstr\td24, [sp, #640]\t@ 0x280\n-\tvdiv.f64\td16, d23, d19\n-\tvsqrt.f64\td9, d19\n-\tvmul.f64\td22, d10, d22\n-\tvmul.f64\td11, d22, d0\n-\tvmul.f64\td18, d16, d18\n-\tvmul.f64\td17, d16, d17\n-\tvmul.f64\td9, d9, d10\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td18, d18, d9\n-\tvmul.f64\td17, d17, d9\n-\tvmul.f64\td16, d16, d9\n-\tvmul.f64\td10, d9, d10\n-\tvstr\td18, [sp, #648]\t@ 0x288\n-\tvstr\td17, [sp, #656]\t@ 0x290\n-\tvstr\td16, [sp, #664]\t@ 0x298\n-\tcmp\tr2, #0\n-\tbne.w\t1be4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xd7c>\n-\tadd.w\tfp, sp, #440\t@ 0x1b8\n-\tadd.w\tr5, sp, #1336\t@ 0x538\n-\tadd.w\tr4, sp, #1056\t@ 0x420\n+\tvmov.f64\td12, d0\n+\tstrd\tr2, r2, [sp, #704]\t@ 0x2c0\n+\tstrd\tr2, r2, [sp, #712]\t@ 0x2c8\n+\tvmla.f64\td4, d3, d3\n+\tldr\tr1, [r3, #0]\n+\tstrd\tr2, r2, [sp, #720]\t@ 0x2d0\n+\tadd\tr3, sp, #728\t@ 0x2d8\n+\tstr\tr3, [sp, #488]\t@ 0x1e8\n+\tvdiv.f64\td7, d1, d4\n+\tvsqrt.f64\td11, d4\n+\tvmul.f64\td2, d9, d2\n+\tvmul.f64\td8, d2, d0\n+\tvmul.f64\td5, d7, d5\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td11, d11, d9\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d11\n+\tvmul.f64\td6, d6, d11\n+\tvmul.f64\td7, d7, d11\n+\tvmul.f64\td9, d11, d9\n+\tvstr\td5, [sp, #728]\t@ 0x2d8\n+\tvstr\td6, [sp, #736]\t@ 0x2e0\n+\tvstr\td7, [sp, #744]\t@ 0x2e8\n+\tcmp\tr1, #0\n+\tbne.w\t1d6e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xf42>\n+\tadd\tr6, sp, #520\t@ 0x208\n+\tadd.w\tr9, sp, #1416\t@ 0x588\n+\tadd.w\tr4, sp, #1136\t@ 0x470\n \tvmov.f64\td0, d12\n-\tadd\tr1, sp, #416\t@ 0x1a0\n-\tadd\tr0, sp, #432\t@ 0x1b0\n-\tbl\t134 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>\n-\tadd\tr3, sp, #424\t@ 0x1a8\n-\tvmov.f64\td0, d9\n+\tadd\tr1, sp, #496\t@ 0x1f0\n+\tadd\tr0, sp, #512\t@ 0x200\n+\tbl\t104 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>\n+\tadd\tr3, sp, #504\t@ 0x1f8\n \tmov\tr1, r3\n-\tmov\tr0, fp\n-\tstr\tr3, [sp, #412]\t@ 0x19c\n-\tbl\t134 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>\n-\tldr\tr3, [pc, #312]\t@ (10f8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x290>)\n-\tvldr\td9, [fp, #-8]\n+\tvmov.f64\td0, d11\n+\tmov\tr0, r6\n+\tstr\tr3, [sp, #492]\t@ 0x1ec\n+\tbl\t104 <__gridxc_vv_vdwxc_MOD_saturate.constprop.0.isra.0>\n+\tldr\tr3, [pc, #316]\t@ (10c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x294>)\n+\tvldr\td7, [r6]\n \tadd\tr3, pc\n-\tvldr\td8, [fp]\n+\tvldr\td15, [r6, #-8]\n+\tvstr\td7, [sp, #8]\n \tldr\tr3, [r3, #4]\n \tcmp\tr3, #0\n-\tbeq.w\t11de <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x376>\n-\tldr\tr6, [pc, #296]\t@ (10fc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x294>)\n-\tmov.w\tr8, #1\n-\tvldr\td12, [pc, #252]\t@ 10d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x270>\n-\tadd\tr6, pc\n-\tldr.w\tsl, [pc, #288]\t@ 1100 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x298>\n-\tadd.w\tr7, r6, #1600\t@ 0x640\n-\tadd\tsl, pc\n-\tvldr\td17, [r6, #48]\t@ 0x30\n-\tvldr\td13, [r6]\n-\tvldr\td18, [r6, #40]\t@ 0x28\n-\tvldr\td16, [r6, #8]\n-\tvstr\td17, [sp, #8]\n-\tvsub.f64\td18, d17, d18\n-\tvsub.f64\td16, d16, d13\n-\tvdiv.f64\td0, d18, d16\n+\tbeq.w\t11a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x374>\n+\tldr\tr5, [pc, #296]\t@ (10c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x298>)\n+\tmovs\tr7, #1\n+\tvldr\td12, [pc, #256]\t@ 10a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x274>\n+\tadd\tr5, pc\n+\tldr.w\tr8, [pc, #292]\t@ 10c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x29c>\n+\tadd.w\tr6, r5, #1600\t@ 0x640\n+\tadd\tr8, pc\n+\tvldr\td13, [r5, #48]\t@ 0x30\n+\tvldr\td10, [r5]\n+\tvldr\td7, [r5, #40]\t@ 0x28\n+\tvldr\td6, [r5, #8]\n+\tvsub.f64\td7, d13, d7\n+\tvsub.f64\td6, d6, d10\n+\tvdiv.f64\td0, d7, d6\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td19, [r6, #56]\t@ 0x38\n-\tvldr\td15, [r6, #88]\t@ 0x58\n-\tvmov.f64\td14, d0\n-\tvldr\td20, [r6, #80]\t@ 0x50\n-\tvldr\td18, [r6, #64]\t@ 0x40\n-\tvstr\td19, [sp, #16]\n-\tvsub.f64\td20, d15, d20\n-\tvsub.f64\td18, d18, d19\n-\tvdiv.f64\td0, d20, d18\n+\tvldr\td4, [r5, #88]\t@ 0x58\n+\tvmov.f64\td11, d0\n+\tvldr\td14, [r5, #56]\t@ 0x38\n+\tvldr\td0, [r5, #80]\t@ 0x50\n+\tvldr\td7, [r5, #64]\t@ 0x40\n+\tvstr\td4, [sp, #24]\n+\tvsub.f64\td0, d4, d0\n+\tvsub.f64\td7, d7, d14\n+\tvdiv.f64\td0, d0, d7\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td16, [pc, #168]\t@ 10e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x278>\n-\tvldr\td20, [pc, #148]\t@ 10d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x268>\n-\tadd.w\tr3, r6, #1584\t@ 0x630\n-\tvmov.f64\td18, #24\t@ 0x40c00000 6.0\n-\tvmul.f64\td16, d14, d16\n-\tvmul.f64\td14, d0, d20\n-\tvmaxnm.f64\td16, d16, d12\n-\tvmaxnm.f64\td14, d14, d12\n-\tvmul.f64\td0, d16, d18\n-\tvstr\td16, [r3]\n-\tvstr\td14, [r7, #-8]\n+\tvldr\td6, [pc, #176]\t@ 10a8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x27c>\n+\tvldr\td7, [pc, #156]\t@ 1098 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x26c>\n+\tadd.w\tr3, r5, #1584\t@ 0x630\n+\tvmul.f64\td6, d11, d6\n+\tvmov.f64\td11, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td7, d0, d7\n+\tvmov.f64\td0, #24\t@ 0x40c00000 6.0\n+\tvcmpe.f64\td6, d12\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td7, d12\n+\tit\tlt\n+\tvmovlt.f64\td6, d12\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d6, d0\n+\tvstr\td6, [r3, #-8]\n+\tit\tlt\n+\tvmovlt.f64\td7, d12\n+\tvstr\td7, [r3]\n+\tvstr\td7, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td18, d0\n-\tvldr\td17, [sp, #8]\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n+\tvsub.f64\td5, d13, d10\n+\tvsub.f64\td0, d0, d11\n+\tvldr\td7, [sp, #16]\n+\tvdiv.f64\td13, d5, d0\n \tvmov.f64\td0, #16\t@ 0x40800000 4.0\n-\tvsub.f64\td17, d17, d13\n-\tvmul.f64\td0, d14, d0\n-\tvsub.f64\td18, d18, d16\n-\tvstr\td16, [sp, #8]\n-\tvdiv.f64\td14, d17, d18\n-\tvstr\td14, [r7]\n+\tvmul.f64\td0, d7, d0\n+\tvstr\td13, [r6, #-8]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td16, [sp, #8]\n-\tadd.w\tr3, r6, #1616\t@ 0x650\n-\tvldr\td19, [sp, #16]\n-\tadd.w\tr7, sl, #1584\t@ 0x630\n-\tstr\tr4, [sp, #8]\n-\tvmov.f64\td17, d16\n-\tvsub.f64\td16, d0, d16\n-\tvsub.f64\td15, d15, d19\n-\tldr\tr4, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td18, d15, d16\n-\tvstr\td18, [r3, #-8]\n-\tmov\tr3, r5\n-\tmov\tr5, r8\n-\tmov\tr8, r3\n-\tb.n\t112a <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x2c2>\n+\tvldr\td4, [sp, #24]\n+\tvsub.f64\td0, d0, d11\n+\tstr\tr4, [sp, #16]\n+\tldr\tr4, [sp, #64]\t@ 0x40\n+\tvsub.f64\td14, d4, d14\n+\tvdiv.f64\td6, d14, d0\n+\tvmov.f64\td0, d11\n+\tvstr\td6, [r6]\n+\tadd.w\tr6, r8, #1584\t@ 0x630\n+\tb.n\t10ee <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x2c2>\n+\tnop\n+\tnop.w\n \t.word\t0xd9d7bdbb\n \t.word\t0x3ddb7cdf\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x9999999a\n \t.word\t0x3fc99999\n-\t.word\t0x00000260\n+\t.word\t0x00000264\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000024e\n+\t.word\t0x00000250\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000001b6\n+\t.word\t0x000001bc\n R_ARM_REL32\t.data\n-\t.word\t0x00000130\n+\t.word\t0x00000136\n R_ARM_REL32\t.data\n-\t.word\t0x0000011c\n+\t.word\t0x00000120\n R_ARM_REL32\t.bss\n-\t.word\t0x00000116\n+\t.word\t0x0000011a\n R_ARM_REL32\t.bss\n-\tvmov\ts15, r5\n-\tvldr\td16, [r7]\n-\tvldr\td13, [sl]\n-\tmov\tr5, fp\n+\tvmov\ts15, r7\n+\tvldr\td10, [r8]\n+\tmov\tr7, fp\n \tvcvt.f64.s32\td0, s15\n-\tvmul.f64\td0, d0, d16\n+\tvldr\td7, [r6, #-8]\n+\tvmul.f64\td0, d0, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tadd.w\tr3, sl, #1600\t@ 0x640\n-\tvmov.f64\td17, d0\n-\tvldr\td14, [r3]\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldmia\tr6!, {d16}\n-\tvsub.f64\td17, d18, d17\n-\tvsub.f64\td16, d16, d13\n-\tvfma.f64\td16, d17, d14\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d12\n+\tadd.w\tr3, r8, #1600\t@ 0x640\n+\tvldr\td13, [r3, #-8]\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldmia\tr5!, {d7}\n+\tvsub.f64\td6, d6, d0\n+\tvsub.f64\td7, d7, d10\n+\tvmla.f64\td7, d6, d13\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d12\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t115a <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x2f2>\n-\tldr\tr3, [pc, #920]\t@ (14e8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x680>)\n+\tble.n\t111e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x2f2>\n+\tldr\tr3, [pc, #892]\t@ (1490 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x664>)\n \tmovs\tr1, #41\t@ 0x29\n-\tldr\tr0, [pc, #920]\t@ (14ec <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x684>)\n+\tldr\tr0, [pc, #892]\t@ (1494 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x668>)\n \tadd\tr0, pc\n \tldr\tr3, [r4, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tadd.w\tfp, r5, #1\n-\tcmp\tr5, #7\n-\tbne.n\t1104 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x29c>\n-\tldr.w\tsl, [pc, #908]\t@ 14f0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x688>\n-\tmov\tr5, r8\n-\tldr\tr4, [sp, #8]\n-\tmovs\tr6, #0\n-\tadd\tsl, pc\n-\tldr.w\tfp, [sp, #56]\t@ 0x38\n-\tvldr\td12, [pc, #868]\t@ 14d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x670>\n-\tadd.w\tr7, sl, #56\t@ 0x38\n-\tadd.w\tr8, sl, #1600\t@ 0x640\n-\tvmov\ts15, r6\n-\tvldr\td0, [r8, #-8]\n-\tvldmia\tr7!, {d13}\n-\tvcvt.f64.s32\td16, s15\n-\tvmul.f64\td0, d16, d0\n+\tadd.w\tfp, r7, #1\n+\tcmp\tr7, #7\n+\tbne.n\t10cc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x2a0>\n+\tldr.w\tr8, [pc, #880]\t@ 1498 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x66c>\n+\tmovs\tr5, #0\n+\tldr\tr4, [sp, #16]\n+\tadd\tr8, pc\n+\tldr.w\tfp, [sp, #64]\t@ 0x40\n+\tvldr\td10, [pc, #848]\t@ 1488 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x65c>\n+\tadd.w\tr6, r8, #56\t@ 0x38\n+\tadd.w\tr7, r8, #1584\t@ 0x630\n+\tvmov\ts15, r5\n+\tvldr\td0, [r7]\n+\tvldmia\tr6!, {d11}\n+\tvcvt.f64.s32\td7, s15\n+\tvmul.f64\td0, d7, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td18, [sl, #56]\t@ 0x38\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tadd.w\tr3, sl, #1616\t@ 0x650\n-\tvsub.f64\td0, d16, d0\n-\tvsub.f64\td16, d13, d18\n-\tvldr\td18, [r3, #-8]\n-\tvfma.f64\td16, d0, d18\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d12\n+\tvldr\td5, [r8, #56]\t@ 0x38\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tadd.w\tr3, r8, #1600\t@ 0x640\n+\tvsub.f64\td0, d7, d0\n+\tvsub.f64\td7, d11, d5\n+\tvldr\td5, [r3]\n+\tvmla.f64\td7, d0, d5\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d10\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t11d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x368>\n-\tldr\tr3, [pc, #804]\t@ (14e8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x680>)\n+\tble.n\t1192 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x366>\n+\tldr\tr3, [pc, #780]\t@ (1490 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x664>)\n \tmovs\tr1, #41\t@ 0x29\n-\tldr\tr0, [pc, #812]\t@ (14f4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x68c>)\n+\tldr\tr0, [pc, #788]\t@ (149c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x670>)\n \tadd\tr0, pc\n \tldr.w\tr3, [fp, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tadds\tr6, #1\n-\tcmp\tr6, #5\n-\tbne.n\t117e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x316>\n-\tldr\tr3, [pc, #800]\t@ (14f8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x690>)\n+\tadds\tr5, #1\n+\tcmp\tr5, #5\n+\tbne.n\t1140 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x314>\n+\tldr\tr3, [pc, #772]\t@ (14a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x674>)\n \tmovs\tr2, #0\n \tadd\tr3, pc\n \tstr\tr2, [r3, #4]\n-\tldr\tr3, [pc, #796]\t@ (14fc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x694>)\n-\tvldr\td17, [pc, #756]\t@ 14d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x670>\n+\tldr\tr3, [pc, #768]\t@ (14a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x678>)\n+\tvldr\td5, [pc, #740]\t@ 1488 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x65c>\n \tadd\tr3, pc\n-\tvldr\td16, [r3]\n-\tvsub.f64\td18, d16, d17\n-\tvcmpe.f64\td9, d18\n+\tvldr\td6, [r3]\n+\tvsub.f64\td7, d6, d5\n+\tvcmpe.f64\td15, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t120c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a4>\n-\tvldr\td18, [r3, #48]\t@ 0x30\n-\tvadd.f64\td18, d18, d17\n-\tvcmpe.f64\td9, d18\n+\tbmi.n\t11ce <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a2>\n+\tvldr\td7, [r3, #48]\t@ 0x30\n+\tvadd.f64\td7, d7, d5\n+\tvcmpe.f64\td15, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t1f4c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x10e4>\n-\tldr\tr3, [pc, #728]\t@ (14e8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x680>)\n+\tble.w\t2126 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12fa>\n+\tldr\tr3, [pc, #704]\t@ (1490 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x664>)\n \tmovs\tr1, #39\t@ 0x27\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tldr\tr0, [pc, #748]\t@ (1500 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x698>)\n+\tldr\tr2, [sp, #64]\t@ 0x40\n+\tldr\tr0, [pc, #720]\t@ (14a8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x67c>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #740]\t@ (1504 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x69c>)\n+\tldr\tr3, [pc, #716]\t@ (14ac <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x680>)\n \tadd\tr3, pc\n-\tvldr\td13, [r3, #56]\t@ 0x38\n-\tvldr\td16, [r3]\n-\tldr.w\tr8, [pc, #732]\t@ 1508 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x6a0>\n-\tvsub.f64\td16, d9, d16\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvsub.f64\td13, d8, d13\n+\tvldr\td11, [r3, #56]\t@ 0x38\n+\tvldr\td6, [r3]\n+\tldr.w\tr8, [pc, #708]\t@ 14b0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x684>\n+\tvsub.f64\td6, d15, d6\n+\tvmov.f64\td10, #112\t@ 0x3f800000 1.0\n+\tadd\tr6, sp, #816\t@ 0x330\n \tadd\tr8, pc\n-\tadd\tr7, sp, #696\t@ 0x2b8\n-\tadd.w\tr6, r8, #1600\t@ 0x640\n-\tadd.w\tfp, r8, #1392\t@ 0x570\n-\tvldr\td17, [r6]\n-\tvdiv.f64\td0, d16, d17\n-\tvadd.f64\td0, d0, d12\n+\tadd.w\tr5, r8, #1600\t@ 0x640\n+\tadd.w\tr7, r8, #1376\t@ 0x560\n+\tadd.w\tfp, r8, #1184\t@ 0x4a0\n+\tvldr\td7, [r5, #-8]\n+\tvdiv.f64\td0, d6, d7\n+\tvadd.f64\td0, d0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tadd.w\tr3, r8, #1616\t@ 0x650\n-\tvmov.f64\td14, d0\n-\tvldr\td16, [r3, #-8]\n-\tvdiv.f64\td0, d13, d16\n-\tvadd.f64\td0, d0, d12\n+\tvldr\td13, [sp, #8]\n+\tvldr\td7, [r5]\n+\tvmov.f64\td12, d0\n+\tadd\tr5, sp, #856\t@ 0x358\n+\tvsub.f64\td11, d13, d11\n+\tvdiv.f64\td0, d11, d7\n+\tvadd.f64\td0, d0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td16, [r6, #-8]\n \tadd.w\tr3, r8, #1584\t@ 0x630\n-\tmov\tlr, r7\n-\tadd\tr2, sp, #736\t@ 0x2e0\n-\tstr\tr7, [sp, #364]\t@ 0x16c\n-\tvdiv.f64\td17, d0, d16\n-\tmov\tr0, r2\n-\tvldr\td18, [r3]\n-\tadd.w\tr3, r8, #1184\t@ 0x4a0\n-\tstr\tr2, [sp, #360]\t@ 0x168\n-\tmovs\tr2, #1\n-\tstr\tr3, [sp, #8]\n-\tadd\tr6, sp, #776\t@ 0x308\n-\tvdiv.f64\td16, d14, d18\n-\tstr\tr6, [sp, #244]\t@ 0xf4\n-\tvmov.f64\td31, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td20, #240\t@ 0xbf800000 -1.0\n-\tvldr\td30, [pc, #576]\t@ 14e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x678>\n-\tmov\tr1, r5\n-\tvcvt.s32.f64\ts15, d17\n-\tvmov\tip, s15\n-\tvcvt.s32.f64\ts15, d16\n-\tadd.w\tip, ip, #1\n+\tmov\tr0, r6\n+\tstr\tr6, [sp, #464]\t@ 0x1d0\n+\tstr\tr7, [sp, #8]\n+\tvldr\td7, [r3, #-8]\n+\tvldr\td5, [r3]\n+\tadd\tr3, sp, #776\t@ 0x308\n+\tmov\tip, r3\n+\tstr\tr3, [sp, #468]\t@ 0x1d4\n+\tvdiv.f64\td6, d12, d7\n+\tstr\tr5, [sp, #196]\t@ 0xc4\n+\tvdiv.f64\td7, d0, d5\n+\tvmov.f64\td0, #8\t@ 0x40400000 3.0\n+\tvcvt.s32.f64\ts13, d6\n+\tvcvt.s32.f64\ts15, d7\n+\tvmov\tr6, s13\n \tvmov\tr7, s15\n-\tcmp\tip, r2\n+\tadds\tr6, #1\n+\tcmp\tr6, #1\n+\tadd.w\tr7, r7, #1\n \tit\tlt\n-\tmovlt\tip, r2\n-\tmovs\tr2, #4\n-\tcmp\tip, r2\n+\tmovlt\tr6, #1\n+\tcmp\tr6, #6\n \tit\tge\n-\tmovge\tip, r2\n-\tadds\tr7, #1\n-\tadd.w\tsl, ip, #4294967295\t@ 0xffffffff\n+\tmovge\tr6, #6\n \tcmp\tr7, #1\n \tit\tlt\n \tmovlt\tr7, #1\n-\tmov.w\tr2, sl, lsl #3\n-\tcmp\tr7, #6\n-\tmov\tr3, r2\n+\tadd.w\tlr, r6, #4294967295\t@ 0xffffffff\n+\tcmp\tr7, #4\n \tit\tge\n-\tmovge\tr7, #6\n-\tadd.w\tsl, r7, #4294967295\t@ 0xffffffff\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvldr\td16, [sl]\n-\tvldr\td18, [sl, #400]\t@ 0x190\n-\tvldr\td22, [sl, #792]\t@ 0x318\n-\tadd.w\tsl, r7, #7\n-\tvsub.f64\td27, d9, d16\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvstr\td18, [sp, #272]\t@ 0x110\n-\tvstr\td22, [sp, #256]\t@ 0x100\n-\tvldr\td21, [sl, #792]\t@ 0x318\n-\tvldr\td22, [sl, #400]\t@ 0x190\n-\tadd.w\tsl, r7, #14\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvstr\td21, [sp, #224]\t@ 0xe0\n-\tvldr\td18, [sl, #400]\t@ 0x190\n-\tvldr\td17, [sl, #792]\t@ 0x318\n-\tadd.w\tsl, r7, #6\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvstr\td17, [sp, #192]\t@ 0xc0\n-\tvldr\td25, [sl, #400]\t@ 0x190\n-\tvldr\td19, [sl, #792]\t@ 0x318\n-\tadd.w\tsl, r7, #21\n-\tadd.w\tr2, r8, sl, lsl #3\n-\tadd.w\tsl, r7, #13\n-\tvsub.f64\td23, d22, d25\n+\tmovge\tr7, #4\n+\tadd.w\tr3, r8, lr, lsl #3\n+\tadd.w\tlr, r7, #4294967295\t@ 0xffffffff\n+\tstr\tr3, [sp, #24]\n+\tmov.w\tr2, lr, lsl #3\n+\tadd.w\tlr, r6, #7\n+\tvldr\td4, [r3]\n+\tmov\tr3, r2\n+\tadd.w\tr2, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #14\n+\tstr\tr2, [sp, #40]\t@ 0x28\n+\tadd.w\tr2, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #6\n+\tstr\tr2, [sp, #48]\t@ 0x30\n+\tadd.w\tr2, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #21\n \tstr\tr2, [sp, #32]\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvstr\td19, [sp, #232]\t@ 0xe8\n-\tvldr\td24, [sl, #400]\t@ 0x190\n-\tvstr\td23, [sp, #216]\t@ 0xd8\n-\tvldr\td23, [sl, #792]\t@ 0x318\n-\tadd.w\tsl, r7, #28\n-\tvsub.f64\td26, d18, d24\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tvstr\td23, [sp, #200]\t@ 0xc8\n-\tvstr\td26, [sp, #184]\t@ 0xb8\n-\tvldr\td26, [r2, #400]\t@ 0x190\n-\tvstr\td26, [sp, #168]\t@ 0xa8\n-\tstr.w\tsl, [sp, #56]\t@ 0x38\n-\tadd.w\tsl, r7, #20\n-\tldr\tr2, [sp, #32]\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #24]\n-\tvldr\td28, [sl, #400]\t@ 0x190\n-\tadd.w\tsl, r7, #35\t@ 0x23\n-\tvldr\td7, [r2, #792]\t@ 0x318\n-\tmov\tr2, r3\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #80]\t@ 0x50\n-\tadd.w\tsl, r7, #27\n-\tvstr\td28, [sp, #176]\t@ 0xb0\n-\tvstr\td7, [sp, #152]\t@ 0x98\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #48]\t@ 0x30\n-\tadd.w\tsl, r7, #42\t@ 0x2a\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #280]\t@ 0x118\n-\tadd.w\tsl, r7, #34\t@ 0x22\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #64]\t@ 0x40\n-\tadd.w\tsl, r7, #41\t@ 0x29\n-\tadd.w\tr7, r8, r7, lsl #3\n-\tstr\tr7, [sp, #16]\n-\tadd.w\tsl, r8, sl, lsl #3\n-\tstr.w\tsl, [sp, #208]\t@ 0xd0\n-\tvldr\td26, [r7]\n-\tadd.w\tr7, r8, r3\n-\tstr\tr7, [sp, #296]\t@ 0x128\n-\tmov.w\tsl, ip, lsl #3\n-\tldr\tr7, [sp, #24]\n-\tadd\tr8, sl\n-\tstr.w\tr8, [sp, #288]\t@ 0x120\n-\tadd\tr3, fp\n-\tstr\tr3, [sp, #312]\t@ 0x138\n-\tvsub.f64\td16, d26, d16\n-\tldr\tr3, [sp, #8]\n-\tvsub.f64\td26, d26, d9\n-\tvldr\td29, [r7, #792]\t@ 0x318\n-\tadd.w\tr7, ip, #4\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #304]\t@ 0x130\n-\tmov.w\tr8, r7, lsl #3\n-\tadd.w\tr7, ip, #9\n-\tadd.w\tr3, fp, r8\n-\tstr\tr3, [sp, #336]\t@ 0x150\n-\tlsls\tr7, r7, #3\n-\tstr\tr7, [sp, #32]\n-\tadd.w\tr7, ip, #14\n-\tldr\tr3, [sp, #8]\n-\tldr\tr2, [sp, #32]\n-\tlsls\tr7, r7, #3\n-\tstr\tr7, [sp, #96]\t@ 0x60\n-\tadd.w\tr7, ip, #19\n+\tadd.w\tr1, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #13\n+\tstr\tr1, [sp, #64]\t@ 0x40\n+\tadd.w\tr1, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #28\n+\tmov\tr2, r1\n+\tadd.w\tr1, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #20\n+\tstr\tr1, [sp, #80]\t@ 0x50\n+\tadd.w\tr1, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #35\t@ 0x23\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tadd.w\tr1, r8, lr, lsl #3\n+\tadd.w\tlr, r6, #27\n+\tstr\tr1, [sp, #112]\t@ 0x70\n+\tadd.w\tlr, r8, lr, lsl #3\n+\tstr.w\tlr, [sp, #72]\t@ 0x48\n+\tadd.w\tlr, r6, #42\t@ 0x2a\n+\tadd.w\tlr, r8, lr, lsl #3\n+\tstr.w\tlr, [sp, #128]\t@ 0x80\n+\tadd.w\tlr, r6, #34\t@ 0x22\n+\tadd.w\tlr, r8, lr, lsl #3\n+\tstr.w\tlr, [sp, #104]\t@ 0x68\n+\tadd.w\tlr, r6, #41\t@ 0x29\n+\tadd.w\tr6, r8, r6, lsl #3\n+\tstr\tr6, [sp, #16]\n+\tadd.w\tlr, r8, lr, lsl #3\n+\tstr.w\tlr, [sp, #120]\t@ 0x78\n+\tmov.w\tlr, r7, lsl #3\n+\tvldr\td14, [r6]\n+\tadd.w\tr6, r8, lr\n+\tstr\tr6, [sp, #136]\t@ 0x88\n+\tadds\tr6, r7, #5\n \tadd\tr8, r3\n-\tadd.w\tr3, fp, r2\n-\tstr\tr3, [sp, #376]\t@ 0x178\n-\tlsls\tr7, r7, #3\n-\tstr\tr7, [sp, #104]\t@ 0x68\n-\tadd.w\tr7, ip, #5\n-\tldr\tr3, [sp, #8]\n-\tvstr\td29, [sp, #160]\t@ 0xa0\n-\tlsls\tr7, r7, #3\n-\tstr\tr7, [sp, #24]\n-\tadd.w\tr7, ip, #10\n-\tadd\tr3, r2\n-\tstr\tr3, [sp, #352]\t@ 0x160\n-\tlsls\tr7, r7, #3\n-\tstr\tr7, [sp, #88]\t@ 0x58\n-\tldr\tr2, [sp, #96]\t@ 0x60\n-\tadd.w\tr7, ip, #15\n-\tadd.w\tip, ip, #20\n-\tadd.w\tr3, fp, r2\n-\tstr\tr3, [sp, #392]\t@ 0x188\n-\tldr\tr3, [sp, #8]\n+\tstr.w\tr8, [sp, #144]\t@ 0x90\n+\tlsls\tr6, r6, #3\n+\tmov\tr1, r6\n+\tadd.w\tr6, r7, #10\n+\tlsls\tr6, r6, #3\n+\tstr\tr6, [sp, #168]\t@ 0xa8\n+\tadds\tr6, r7, #4\n+\tmov.w\tr8, r6, lsl #3\n+\tadd.w\tr6, r7, #15\n+\tlsls\tr6, r6, #3\n+\tstr\tr6, [sp, #176]\t@ 0xb0\n+\tadd.w\tr6, r7, #9\n+\tlsls\tr6, r6, #3\n+\tstr\tr6, [sp, #160]\t@ 0xa0\n+\tadd.w\tr6, r7, #20\n+\tlsls\tr6, r6, #3\n+\tstr\tr6, [sp, #200]\t@ 0xc8\n+\tadd.w\tr6, r7, #14\n+\tadds\tr7, #19\n \tlsls\tr7, r7, #3\n-\tmov.w\tip, ip, lsl #3\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #104]\t@ 0x68\n-\tstr\tr3, [sp, #388]\t@ 0x184\n-\tadd.w\tr3, fp, r2\n-\tstr\tr3, [sp, #404]\t@ 0x194\n-\tldr\tr3, [sp, #8]\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #24]\n-\tstr\tr3, [sp, #400]\t@ 0x190\n-\tadd.w\tr3, fp, sl\n-\tstr\tr3, [sp, #320]\t@ 0x140\n-\tldr\tr3, [sp, #8]\n-\tadd\tsl, r3\n-\tadd.w\tr3, fp, r2\n-\tstr\tr3, [sp, #344]\t@ 0x158\n-\tldr\tr3, [sp, #8]\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #88]\t@ 0x58\n-\tstr\tr3, [sp, #328]\t@ 0x148\n-\tadd.w\tr3, fp, r2\n-\tstr\tr3, [sp, #384]\t@ 0x180\n+\tstr\tr7, [sp, #184]\t@ 0xb8\n+\tldr\tr7, [sp, #8]\n+\tlsls\tr6, r6, #3\n+\tadd\tr7, r3\n+\tstr\tr7, [sp, #152]\t@ 0x98\n+\tadd.w\tr7, fp, r3\n \tldr\tr3, [sp, #8]\n-\tadd\tr3, r2\n-\tldr\tr2, [sp, #16]\n+\tstr\tr7, [sp, #376]\t@ 0x178\n+\tmov\tr7, r3\n+\tadd\tr7, lr\n+\tstr\tr7, [sp, #8]\n+\tmov\tr7, r3\n+\tadd\tlr, fp\n+\tadd\tr7, r8\n+\tstr\tr7, [sp, #360]\t@ 0x168\n+\tmov\tr7, r3\n+\tadd\tr3, r1\n+\tadd\tr1, fp\n+\tstr\tr1, [sp, #384]\t@ 0x180\n+\tldr\tr1, [sp, #160]\t@ 0xa0\n+\tadd\tr8, fp\n \tstr\tr3, [sp, #368]\t@ 0x170\n-\tadd.w\tr3, fp, r7\n-\tstr\tr3, [sp, #396]\t@ 0x18c\n-\tadd\tfp, ip\n-\tldr\tr3, [sp, #8]\n-\tvldr\td6, [r2, #400]\t@ 0x190\n-\tvldr\td5, [r2, #792]\t@ 0x318\n+\tmov\tr3, r7\n+\tadd\tr7, r1\n+\tadd\tr1, fp\n+\tstr\tr1, [sp, #408]\t@ 0x198\n+\tldr\tr1, [sp, #168]\t@ 0xa8\n+\tstr\tr7, [sp, #392]\t@ 0x188\n+\tmov\tr7, r3\n+\tadd\tr7, r1\n+\tadd\tr1, fp\n+\tstr\tr1, [sp, #456]\t@ 0x1c8\n+\tadds\tr1, r3, r6\n+\tstr\tr1, [sp, #440]\t@ 0x1b8\n+\tadd\tr6, fp\n+\tldr\tr1, [sp, #176]\t@ 0xb0\n+\tstr\tr7, [sp, #416]\t@ 0x1a0\n+\tmov\tr7, r3\n+\tadd\tr7, r1\n+\tadd\tr1, fp\n+\tstr\tr7, [sp, #448]\t@ 0x1c0\n+\tmov\tr7, r3\n+\tstr\tr1, [sp, #472]\t@ 0x1d8\n+\tmov\tr1, r3\n+\tldr\tr3, [sp, #184]\t@ 0xb8\n \tadd\tr7, r3\n-\tldr\tr2, [sp, #56]\t@ 0x38\n-\tadd\tip, r3\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tvstr\td6, [sp, #264]\t@ 0x108\n-\tvstr\td5, [sp, #248]\t@ 0xf8\n-\tvldr\td2, [r2, #400]\t@ 0x190\n-\tvldr\td4, [r3, #400]\t@ 0x190\n-\tvldr\td3, [r3, #792]\t@ 0x318\n-\tb.n\t150c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x6a4>\n+\tstr\tr7, [sp, #480]\t@ 0x1e0\n+\tmov\tr7, r1\n+\tldr\tr1, [sp, #200]\t@ 0xc8\n+\tadd\tr7, r1\n+\tstr\tr7, [sp, #484]\t@ 0x1e4\n+\tmov\tr7, r3\n+\tldr\tr3, [sp, #24]\n+\tadd\tr7, fp\n+\tadd\tfp, r1\n+\tvldr\td3, [r3, #392]\t@ 0x188\n+\tvldr\td7, [r3, #784]\t@ 0x310\n+\tldr\tr3, [sp, #16]\n+\tvstr\td3, [sp, #352]\t@ 0x160\n+\tvstr\td7, [sp, #336]\t@ 0x150\n+\tvldr\td2, [r3, #392]\t@ 0x188\n+\tvldr\td6, [r3, #784]\t@ 0x310\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvstr\td6, [sp, #328]\t@ 0x148\n+\tldr\tr3, [sp, #32]\n+\tvldr\td7, [r2, #392]\t@ 0x188\n+\tvldr\td6, [r2, #784]\t@ 0x310\n+\tldr\tr2, [sp, #48]\t@ 0x30\n+\tvldr\td5, [r3, #392]\t@ 0x188\n+\tvldr\td1, [r3, #784]\t@ 0x310\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tldr\tr1, [sp, #56]\t@ 0x38\n+\tvstr\td5, [sp, #320]\t@ 0x140\n+\tvstr\td1, [sp, #304]\t@ 0x130\n+\tvldr\td11, [r3, #392]\t@ 0x188\n+\tvldr\td12, [r3, #784]\t@ 0x310\n+\tvldr\td5, [r2, #392]\t@ 0x188\n+\tldr\tr3, [sp, #64]\t@ 0x40\n+\tvldr\td1, [r2, #784]\t@ 0x310\n+\tldr\tr2, [sp, #72]\t@ 0x48\n+\tvstr\td11, [sp, #312]\t@ 0x138\n+\tvstr\td12, [sp, #296]\t@ 0x128\n+\tvldr\td11, [r1, #392]\t@ 0x188\n+\tvldr\td12, [r1, #784]\t@ 0x310\n+\tvstr\td7, [sp, #288]\t@ 0x120\n+\tvstr\td6, [sp, #272]\t@ 0x110\n+\tvldr\td7, [r3, #392]\t@ 0x188\n+\tvldr\td6, [r3, #784]\t@ 0x310\n+\tvstr\td5, [sp, #280]\t@ 0x118\n+\tvldr\td5, [r2, #392]\t@ 0x188\n+\tvstr\td11, [sp, #256]\t@ 0x100\n+\tvstr\td12, [sp, #240]\t@ 0xf0\n+\tvstr\td7, [sp, #248]\t@ 0xf8\n+\tvstr\td6, [sp, #232]\t@ 0xe8\n+\tvstr\td5, [sp, #224]\t@ 0xe0\n+\tvstr\td1, [sp, #264]\t@ 0x108\n+\tvldr\td1, [r2, #784]\t@ 0x310\n+\tldr\tr3, [sp, #80]\t@ 0x50\n+\tldr\tr2, [sp, #104]\t@ 0x68\n+\tvstr\td1, [sp, #208]\t@ 0xd0\n+\tb.n\t14b4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x688>\n+\tnop\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x55555555\n-\t.word\t0x3fc55555\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000396\n+\t.word\t0x0000037a\n R_ARM_REL32\t.LC22\n-\t.word\t0x00000380\n+\t.word\t0x00000366\n R_ARM_REL32\t.bss\n-\t.word\t0x0000032a\n+\t.word\t0x00000310\n R_ARM_REL32\t.LC23\n-\t.word\t0x0000031a\n+\t.word\t0x00000300\n R_ARM_REL32\t.data\n-\t.word\t0x00000314\n+\t.word\t0x000002fa\n R_ARM_REL32\t.bss\n-\t.word\t0x000002e6\n+\t.word\t0x000002cc\n R_ARM_REL32\t.LC24\n-\t.word\t0x000002e2\n+\t.word\t0x000002c8\n R_ARM_REL32\t.bss\n-\t.word\t0x000002cc\n+\t.word\t0x000002b4\n R_ARM_REL32\t.bss\n-\tvstr\td4, [sp, #144]\t@ 0x90\n-\tvstr\td3, [sp, #128]\t@ 0x80\n-\tvstr\td2, [sp, #136]\t@ 0x88\n-\tvldr\td1, [r2, #792]\t@ 0x318\n-\tldr\tr2, [sp, #80]\t@ 0x50\n-\tldr\tr3, [sp, #64]\t@ 0x40\n-\tvstr\td1, [sp, #120]\t@ 0x78\n-\tvldr\td13, [r2, #400]\t@ 0x190\n-\tvldr\td14, [r2, #792]\t@ 0x318\n-\tldr\tr2, [sp, #280]\t@ 0x118\n-\tvldr\td0, [r3, #400]\t@ 0x190\n-\tvldr\td9, [r3, #792]\t@ 0x318\n-\tldr\tr3, [sp, #208]\t@ 0xd0\n-\tvldr\td15, [r2, #400]\t@ 0x190\n-\tvldr\td19, [r2, #792]\t@ 0x318\n-\tldr\tr2, [sp, #288]\t@ 0x120\n-\tvldr\td17, [r3, #400]\t@ 0x190\n-\tvstr\td13, [sp, #104]\t@ 0x68\n-\tvldr\td13, [r3, #792]\t@ 0x318\n-\tvldr\td28, [r2, #56]\t@ 0x38\n-\tldr\tr2, [sp, #296]\t@ 0x128\n-\tvstr\td0, [sp, #112]\t@ 0x70\n-\tvstr\td9, [sp, #96]\t@ 0x60\n-\tvstr\td14, [sp, #88]\t@ 0x58\n-\tvldr\td29, [r2, #56]\t@ 0x38\n-\tldr\tr2, [sp, #312]\t@ 0x138\n-\tvstr\td17, [sp, #8]\n-\tvstr\td13, [sp, #24]\n-\tvsub.f64\td21, d28, d29\n-\tvstr\td15, [sp, #16]\n-\tvsub.f64\td28, d28, d8\n-\tvldr\td3, [r2, #-8]\n-\tvsub.f64\td29, d8, d29\n-\tldr\tr2, [sp, #336]\t@ 0x150\n-\tvstr\td19, [sp, #32]\n-\tvldr\td1, [r2, #-8]\n-\tldr\tr2, [sp, #376]\t@ 0x178\n-\tvldr\td9, [r2, #-8]\n+\tvldr\td11, [r3, #392]\t@ 0x188\n+\tvldr\td12, [r3, #784]\t@ 0x310\n+\tldr\tr3, [sp, #112]\t@ 0x70\n+\tvldr\td7, [r2, #392]\t@ 0x188\n+\tvldr\td6, [r2, #784]\t@ 0x310\n+\tldr\tr2, [sp, #120]\t@ 0x78\n+\tvldr\td5, [r3, #392]\t@ 0x188\n+\tvldr\td1, [r3, #784]\t@ 0x310\n+\tldr\tr3, [sp, #128]\t@ 0x80\n+\tvstr\td7, [sp, #184]\t@ 0xb8\n+\tvldr\td7, [r2, #784]\t@ 0x310\n+\tvstr\td6, [sp, #168]\t@ 0xa8\n+\tvldr\td6, [r3, #784]\t@ 0x310\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvldr\td7, [r3, #392]\t@ 0x188\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tvstr\td5, [sp, #176]\t@ 0xb0\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvstr\td12, [sp, #200]\t@ 0xc8\n+\tvldr\td5, [r3, #56]\t@ 0x38\n+\tldr\tr3, [sp, #144]\t@ 0x90\n+\tvldr\td12, [r2, #392]\t@ 0x188\n+\tvstr\td11, [sp, #216]\t@ 0xd8\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldr\td6, [r3, #56]\t@ 0x38\n+\tldr\tr3, [sp, #152]\t@ 0x98\n+\tvstr\td12, [sp, #104]\t@ 0x68\n+\tvstr\td1, [sp, #160]\t@ 0xa0\n+\tvldr\td1, [r3]\n+\tldr\tr2, [sp, #8]\n+\tldr\tr3, [sp, #368]\t@ 0x170\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvldr\td12, [r2]\n+\tldr\tr2, [sp, #360]\t@ 0x168\n+\tvldr\td1, [r3]\n+\tvstr\td12, [sp, #64]\t@ 0x40\n+\tldr\tr3, [sp, #376]\t@ 0x178\n+\tvldr\td2, [r2]\n \tldr\tr2, [sp, #392]\t@ 0x188\n-\tvldr\td23, [sl]\n-\tvldr\td5, [r7]\n-\tvldr\td19, [ip]\n-\tvldr\td15, [r2, #-8]\n-\tldr\tr2, [sp, #404]\t@ 0x194\n-\tvstr\td23, [sp, #336]\t@ 0x150\n-\tvldr\td14, [fp, #-8]\n-\tvstr\td5, [sp, #280]\t@ 0x118\n-\tvldr\td4, [r2, #-8]\n-\tldr\tr2, [sp, #320]\t@ 0x140\n-\tvstr\td19, [sp, #56]\t@ 0x38\n-\tvstr\td4, [sp, #64]\t@ 0x40\n-\tvldr\td4, [r2, #-8]\n-\tldr\tr2, [sp, #344]\t@ 0x158\n-\tvldr\td2, [r2, #-8]\n-\tldr\tr2, [sp, #384]\t@ 0x180\n-\tvldr\td0, [r2, #-8]\n-\tldr\tr2, [sp, #396]\t@ 0x18c\n-\tvldr\td13, [r2, #-8]\n-\tldr\tr2, [sp, #328]\t@ 0x148\n+\tvstr\td1, [sp, #424]\t@ 0x1a8\n+\tvstr\td2, [sp, #432]\t@ 0x1b0\n+\tvldr\td12, [r2]\n+\tldr\tr2, [sp, #416]\t@ 0x1a0\n+\tvstr\td12, [sp, #400]\t@ 0x190\n+\tvldr\td2, [r2]\n+\tldr\tr2, [sp, #440]\t@ 0x1b8\n+\tvstr\td2, [sp, #392]\t@ 0x188\n+\tvldr\td1, [r2]\n+\tldr\tr2, [sp, #448]\t@ 0x1c0\n+\tvstr\td1, [sp, #368]\t@ 0x170\n+\tvldr\td11, [r2]\n+\tldr\tr2, [sp, #480]\t@ 0x1e0\n+\tvstr\td11, [sp, #360]\t@ 0x168\n+\tvldr\td11, [r3, #-8]\n+\tvldr\td12, [r2]\n+\tldr\tr2, [sp, #484]\t@ 0x1e4\n+\tvstr\td12, [sp, #144]\t@ 0x90\n+\tvldr\td12, [lr, #-8]\n \tvldr\td7, [r2]\n-\tldr\tr2, [sp, #368]\t@ 0x170\n-\tvstr\td7, [sp, #320]\t@ 0x140\n-\tvldr\td7, [r8]\n-\tvldr\td6, [r2]\n-\tldr\tr2, [sp, #304]\t@ 0x130\n-\tvstr\td7, [sp, #328]\t@ 0x148\n-\tvmov.f64\td7, d20\n-\tvstr\td6, [sp, #296]\t@ 0x128\n-\tvldr\td23, [r2]\n-\tldr\tr2, [sp, #352]\t@ 0x160\n-\tvstr\td23, [sp, #344]\t@ 0x158\n-\tvdiv.f64\td23, d12, d16\n-\tvldr\td6, [r2]\n-\tldr\tr2, [sp, #388]\t@ 0x184\n-\tvstr\td6, [sp, #304]\t@ 0x130\n-\tvmov.f64\td6, d12\n-\tvldr\td5, [r2]\n-\tldr\tr2, [sp, #400]\t@ 0x190\n-\tvstr\td5, [sp, #288]\t@ 0x120\n-\tvldr\td17, [r2]\n \tmov\tr2, r4\n-\tvstr\td17, [sp, #48]\t@ 0x30\n-\tvmul.f64\td17, d27, d23\n-\tvmul.f64\td19, d26, d23\n-\tvdiv.f64\td27, d12, d21\n-\tvmul.f64\td22, d17, d22\n-\tvmul.f64\td18, d17, d18\n-\tvfma.f64\td18, d19, d24\n-\tvmul.f64\td5, d17, d17\n-\tvmov.f64\td8, d22\n-\tvfma.f64\td8, d19, d25\n-\tvfma.f64\td20, d5, d31\n-\tvsub.f64\td5, d5, d12\n-\tvstr\td18, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td18, d19, d19\n-\tvmul.f64\td25, d28, d27\n-\tvmul.f64\td26, d29, d27\n-\tvmov.f64\td29, d12\n-\tvmul.f64\td28, d21, d21\n-\tvfms.f64\td29, d18, d31\n-\tvmul.f64\td21, d21, d30\n-\tvsub.f64\td18, d18, d12\n-\tvmul.f64\td22, d25, d25\n-\tvmul.f64\td24, d26, d26\n-\tvmul.f64\td28, d28, d30\n-\tvmul.f64\td18, d18, d19\n-\tvfms.f64\td6, d22, d31\n-\tvfma.f64\td7, d24, d31\n-\tvsub.f64\td24, d24, d12\n-\tvsub.f64\td22, d22, d12\n-\tvmul.f64\td31, d24, d26\n-\tvmul.f64\td24, d5, d17\n-\tvmul.f64\td22, d22, d25\n-\tvmul.f64\td5, d3, d6\n-\tvfma.f64\td5, d7, d4\n-\tvmul.f64\td4, d31, d4\n-\tvmov.f64\td12, d4\n+\tvstr\td7, [sp, #152]\t@ 0x98\n+\tvldr\td2, [r8, #-8]\n+\tldr\tr1, [sp, #384]\t@ 0x180\n+\tvstr\td2, [sp, #448]\t@ 0x1c0\n+\tvldr\td1, [r1, #-8]\n+\tldr\tr1, [sp, #408]\t@ 0x198\n+\tvstr\td1, [sp, #440]\t@ 0x1b8\n+\tvldr\td7, [r1, #-8]\n+\tldr\tr1, [sp, #456]\t@ 0x1c8\n+\tvstr\td7, [sp, #416]\t@ 0x1a0\n+\tvldr\td7, [r7, #-8]\n+\tvldr\td2, [r1, #-8]\n+\tldr\tr1, [sp, #472]\t@ 0x1d8\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tvsub.f64\td7, d14, d4\n+\tvstr\td2, [sp, #408]\t@ 0x198\n+\tvsub.f64\td14, d14, d15\n+\tvldr\td2, [r6, #-8]\n+\tvsub.f64\td4, d15, d4\n+\tvldr\td1, [r1, #-8]\n+\tmov\tr1, r9\n+\tvstr\td2, [sp, #384]\t@ 0x180\n+\tvsub.f64\td2, d5, d6\n+\tvsub.f64\td5, d5, d13\n+\tvstr\td1, [sp, #376]\t@ 0x178\n+\tvldr\td1, [fp, #-8]\n+\tvsub.f64\td6, d13, d6\n+\tvmov.f64\td13, d7\n+\tvsub.f64\td7, d12, d11\n+\tvdiv.f64\td3, d10, d2\n+\tvstr\td1, [sp, #136]\t@ 0x88\n+\tvstr\td13, [sp, #80]\t@ 0x50\n+\tvmul.f64\td1, d5, d3\n+\tvmul.f64\td6, d6, d3\n+\tvmul.f64\td15, d7, d3\n+\tvstr\td3, [sp, #24]\n+\tvmul.f64\td11, d1, d11\n+\tvstr\td15, [sp, #472]\t@ 0x1d8\n+\tvmov.f64\td3, d11\n+\tvmov.f64\td11, d6\n+\tvmla.f64\td3, d6, d12\n+\tvmul.f64\td12, d1, d1\n+\tvdiv.f64\td6, d10, d13\n+\tvmov.f64\td13, d11\n+\tvmul.f64\td11, d11, d11\n+\tvstr\td13, [sp, #120]\t@ 0x78\n+\tvstr\td3, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td7, d4, d6\n+\tvmul.f64\td4, d2, d2\n+\tvmul.f64\td5, d14, d6\n+\tvldr\td14, [pc, #1012]\t@ 1a38 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xc0c>\n+\tvmul.f64\td4, d4, d14\n+\tvmul.f64\td15, d7, d7\n+\tvmul.f64\td2, d2, d14\n+\tvstr\td4, [sp, #32]\n+\tvmov.f64\td4, d10\n+\tvmov.f64\td3, d15\n+\tvmov.f64\td15, d10\n+\tvmls.f64\td15, d12, d0\n+\tvsub.f64\td12, d12, d10\n+\tvstr\td2, [sp, #56]\t@ 0x38\n+\tvmul.f64\td2, d5, d5\n+\tvnmls.f64\td4, d11, d0\n+\tvsub.f64\td11, d11, d10\n+\tvmul.f64\td14, d11, d13\n+\tvmov.f64\td11, d10\n+\tvnmls.f64\td11, d3, d0\n+\tvstr\td4, [sp, #16]\n+\tvmul.f64\td4, d12, d1\n+\tvstr\td4, [sp, #8]\n+\tvsub.f64\td4, d3, d10\n+\tvmov.f64\td12, d11\n+\tvmov.f64\td11, d10\n+\tvmls.f64\td11, d2, d0\n+\tvsub.f64\td2, d2, d10\n+\tvldr\td10, [sp, #64]\t@ 0x40\n+\tvmul.f64\td13, d4, d7\n+\tvldr\td0, [sp, #8]\n+\tvldr\td4, [sp, #72]\t@ 0x48\n+\tvmul.f64\td10, d14, d10\n+\tvldr\td3, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td2, d2, d5\n+\tvmla.f64\td10, d4, d0\n+\tvldr\td0, [sp, #32]\n+\tvmla.f64\td3, d10, d0\n+\tvmul.f64\td0, d4, d15\n+\tvldr\td10, [sp, #16]\n \tvldr\td4, [sp, #64]\t@ 0x40\n-\tvfma.f64\td12, d3, d22\n-\tvmul.f64\td3, d21, d5\n-\tvmul.f64\td5, d6, d1\n-\tvfma.f64\td5, d7, d2\n-\tvmul.f64\td2, d31, d2\n-\tvfma.f64\td2, d22, d1\n-\tvstr\td3, [sp, #352]\t@ 0x160\n-\tvstr\td12, [sp, #80]\t@ 0x50\n-\tvldr\td12, [sp, #96]\t@ 0x60\n-\tvmul.f64\td1, d21, d5\n-\tvmul.f64\td5, d6, d9\n-\tvfma.f64\td5, d7, d0\n-\tvmul.f64\td0, d31, d0\n-\tvfma.f64\td0, d22, d9\n-\tvstr\td2, [sp, #312]\t@ 0x138\n-\tvmul.f64\td9, d21, d5\n-\tvmul.f64\td5, d6, d15\n-\tvfma.f64\td5, d7, d13\n-\tvmul.f64\td13, d31, d13\n-\tvmul.f64\td31, d31, d14\n-\tvmul.f64\td6, d4, d6\n-\tvfma.f64\td31, d22, d4\n-\tvfma.f64\td6, d14, d7\n-\tvmov.f64\td14, d13\n-\tvldr\td13, [sp, #24]\n-\tvfma.f64\td14, d22, d15\n-\tvldr\td22, [sp, #256]\t@ 0x100\n-\tvmov.f64\td15, d31\n-\tvmul.f64\td31, d21, d5\n-\tvmul.f64\td4, d6, d21\n-\tvmul.f64\td6, d29, d22\n-\tvstr\td31, [sp, #368]\t@ 0x170\n-\tvldr\td31, [sp, #248]\t@ 0xf8\n-\tvstr\td4, [sp, #376]\t@ 0x178\n-\tvmul.f64\td21, d24, d31\n-\tvfma.f64\td6, d20, d31\n-\tvmov.f64\td31, d21\n-\tvldr\td21, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td31, d18, d22\n-\tvldr\td22, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td5, d29, d22\n-\tvfma.f64\td5, d20, d21\n-\tvstr\td31, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td31, d24, d21\n-\tvldr\td21, [sp, #192]\t@ 0xc0\n-\tvfma.f64\td31, d18, d22\n-\tvldr\td22, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td7, d24, d21\n-\tvfma.f64\td7, d18, d22\n-\tvmul.f64\td4, d29, d22\n-\tvldr\td22, [sp, #160]\t@ 0xa0\n-\tvfma.f64\td4, d20, d21\n-\tvldr\td21, [sp, #152]\t@ 0x98\n-\tvmul.f64\td3, d29, d22\n-\tvfma.f64\td3, d20, d21\n-\tvmul.f64\td21, d24, d21\n-\tvfma.f64\td21, d18, d22\n-\tvldr\td22, [sp, #128]\t@ 0x80\n-\tvmul.f64\td2, d29, d22\n-\tvstr\td21, [sp, #152]\t@ 0x98\n-\tvldr\td21, [sp, #120]\t@ 0x78\n-\tvfma.f64\td2, d20, d21\n-\tvmul.f64\td21, d24, d21\n-\tvfma.f64\td21, d18, d22\n-\tvmul.f64\td22, d13, d29\n-\tvstr\td21, [sp, #120]\t@ 0x78\n-\tvmul.f64\td21, d29, d12\n-\tvmov.f64\td29, d21\n-\tvldr\td21, [sp, #88]\t@ 0x58\n-\tvfma.f64\td29, d20, d21\n-\tvstr\td29, [sp, #64]\t@ 0x40\n-\tvldr\td29, [sp, #32]\n-\tvfma.f64\td22, d29, d20\n-\tvmul.f64\td20, d24, d21\n-\tvmul.f64\td21, d16, d16\n-\tvmul.f64\td24, d24, d29\n-\tvfma.f64\td20, d18, d12\n-\tvmul.f64\td16, d16, d30\n-\tvldr\td29, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td21, d21, d30\n-\tvmov.f64\td12, d24\n-\tvfma.f64\td12, d18, d13\n-\tvldr\td18, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td5, d16, d5\n-\tvldr\td24, [sp, #336]\t@ 0x150\n-\tvmul.f64\td30, d16, d6\n-\tvmul.f64\td3, d16, d3\n-\tvfma.f64\td18, d21, d7\n-\tvfma.f64\td8, d21, d31\n-\tvmul.f64\td6, d16, d4\n-\tvmul.f64\td2, d16, d2\n-\tvldr\td7, [sp, #328]\t@ 0x148\n-\tvstr\td20, [sp, #32]\n-\tvstr\td12, [sp, #24]\n-\tvmov.f64\td13, d18\n-\tvldr\td18, [sp, #64]\t@ 0x40\n-\tvmov.f64\td12, d8\n-\tvmov.f64\td8, d5\n-\tvmul.f64\td5, d22, d16\n-\tvldr\td22, [sp, #344]\t@ 0x158\n-\tvmul.f64\td31, d16, d18\n-\tvmul.f64\td16, d26, d24\n-\tvfma.f64\td8, d29, d23\n-\tvldr\td29, [sp, #184]\t@ 0xb8\n-\tvfma.f64\td16, d25, d22\n-\tvsub.f64\td18, d24, d22\n-\tvldr\td22, [sp, #80]\t@ 0x50\n-\tvfma.f64\td6, d29, d23\n-\tvldr\td24, [sp, #320]\t@ 0x140\n-\tvmov.f64\td29, d16\n-\tvmul.f64\td16, d26, d24\n-\tvfma.f64\td29, d22, d28\n-\tvldr\td22, [sp, #352]\t@ 0x160\n-\tvfma.f64\td22, d18, d27\n-\tvfma.f64\td16, d25, d7\n-\tvsub.f64\td18, d24, d7\n-\tvldr\td24, [sp, #296]\t@ 0x128\n-\tvldr\td7, [sp, #304]\t@ 0x130\n-\tvfma.f64\td1, d18, d27\n-\tvsub.f64\td18, d24, d7\n-\tvstr\td29, [r0]\n-\tvstr\td22, [lr]\n-\tvldr\td22, [sp, #312]\t@ 0x138\n-\tvfma.f64\td9, d18, d27\n-\tvldr\td29, [sp, #56]\t@ 0x38\n-\tvfma.f64\td16, d28, d22\n-\tvstr\td1, [lr, #8]\n-\tvmul.f64\td18, d26, d29\n-\tvldr\td1, [sp, #48]\t@ 0x30\n-\tvsub.f64\td22, d29, d1\n-\tvfma.f64\td18, d25, d1\n-\tvldr\td29, [sp, #376]\t@ 0x178\n-\tvstr\td9, [lr, #16]\n-\tvstr\td16, [r0, #8]\n-\tvmul.f64\td16, d26, d24\n-\tvfma.f64\td16, d25, d7\n-\tvldr\td24, [sp, #280]\t@ 0x118\n-\tvldr\td7, [sp, #288]\t@ 0x120\n-\tvfma.f64\td29, d22, d27\n-\tvfma.f64\td18, d15, d28\n-\tvfma.f64\td16, d28, d0\n-\tvsub.f64\td20, d24, d7\n-\tvstr\td29, [lr, #32]\n-\tvmov.f64\td29, d30\n-\tvstr\td18, [r0, #32]\n-\tvmov.f64\td30, d3\n-\tvstr\td16, [r0, #16]\n-\tvmul.f64\td16, d26, d24\n-\tvfma.f64\td16, d25, d7\n-\tvldr\td25, [sp, #368]\t@ 0x170\n-\tvfma.f64\td25, d20, d27\n-\tvmov.f64\td7, d16\n-\tvfma.f64\td7, d28, d14\n-\tvstr\td25, [lr, #24]\n-\tvmov.f64\td28, d2\n-\tvstr\td7, [r0, #24]\n-\tvldr\td20, [sp, #264]\t@ 0x108\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tvldr\td24, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td27, d17, d20\n-\tvldr\td22, [sp, #16]\n-\tvsub.f64\td16, d20, d18\n-\tvfma.f64\td27, d19, d18\n-\tvldr\td18, [sp, #176]\t@ 0xb0\n-\tvldr\td20, [sp, #104]\t@ 0x68\n-\tldr\tr3, [sp, #412]\t@ 0x19c\n-\tvfma.f64\td29, d16, d23\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvfma.f64\td27, d21, d24\n-\tvldr\td24, [sp, #152]\t@ 0x98\n-\tvmul.f64\td26, d17, d16\n-\tvsub.f64\td16, d16, d18\n-\tvfma.f64\td26, d19, d18\n-\tvldr\td18, [sp, #144]\t@ 0x90\n-\tvldr\td9, [r3]\n-\tvfma.f64\td30, d16, d23\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvfma.f64\td26, d21, d24\n-\tvmul.f64\td24, d17, d20\n-\tvmul.f64\td4, d9, d27\n-\tvmul.f64\td7, d9, d13\n-\tvmul.f64\td25, d17, d16\n-\tvsub.f64\td16, d16, d18\n-\tvfma.f64\td25, d19, d18\n-\tvldr\td18, [sp, #120]\t@ 0x78\n-\tvfma.f64\td28, d16, d23\n-\tvldr\td16, [sp, #112]\t@ 0x70\n-\tvfma.f64\td25, d21, d18\n-\tvmul.f64\td18, d17, d22\n-\tvldr\td17, [sp, #8]\n-\tvfma.f64\td24, d19, d16\n-\tvsub.f64\td16, d20, d16\n-\tvldr\td20, [sp, #32]\n-\tvfma.f64\td18, d19, d17\n-\tvsub.f64\td17, d22, d17\n-\tvmov.f64\td19, d5\n-\tvmul.f64\td5, d9, d12\n-\tvfma.f64\td31, d16, d23\n-\tvldr\td16, [sp, #24]\n-\tvfma.f64\td24, d21, d20\n-\tvfma.f64\td19, d17, d23\n-\tvldr\td17, [r3, #-8]\n-\tvfma.f64\td18, d16, d21\n-\tvmul.f64\td2, d9, d25\n-\tmov\tr3, r6\n-\tvmul.f64\td3, d17, d8\n-\tvmul.f64\td29, d17, d29\n-\tvmul.f64\td6, d17, d6\n-\tvmul.f64\td30, d17, d30\n-\tvmul.f64\td28, d17, d28\n-\tvmov.f64\td1, d31\n-\tvmul.f64\td31, d9, d26\n-\tvmul.f64\td0, d9, d24\n-\tvmul.f64\td8, d19, d17\n-\tvmul.f64\td9, d18, d9\n-\tvmul.f64\td1, d17, d1\n-\tvldmia\tr0!, {d16}\n+\tvmla.f64\td0, d10, d4\n+\tvldr\td10, [sp, #56]\t@ 0x38\n+\tvldr\td4, [sp, #472]\t@ 0x1d8\n+\tvstr\td3, [r0]\n+\tvldr\td3, [sp, #424]\t@ 0x1a8\n+\tvmla.f64\td4, d0, d10\n+\tvldr\td0, [sp, #16]\n+\tvldr\td10, [sp, #8]\n+\tvmul.f64\td0, d0, d3\n+\tvstr\td4, [ip]\n+\tvldr\td4, [sp, #432]\t@ 0x1b0\n+\tvmla.f64\td0, d15, d4\n+\tvmul.f64\td10, d10, d4\n+\tvldr\td4, [sp, #400]\t@ 0x190\n+\tvmla.f64\td10, d14, d3\n+\tvldr\td3, [sp, #392]\t@ 0x188\n+\tvstr\td0, [sp, #424]\t@ 0x1a8\n+\tvldr\td0, [sp, #8]\n+\tvmul.f64\td0, d0, d4\n+\tvmla.f64\td0, d14, d3\n+\tvstr\td0, [sp, #392]\t@ 0x188\n+\tvldr\td0, [sp, #16]\n+\tvmul.f64\td0, d0, d3\n+\tvldr\td3, [sp, #360]\t@ 0x168\n+\tvmla.f64\td0, d15, d4\n+\tvldr\td4, [sp, #368]\t@ 0x170\n+\tvstr\td0, [sp, #400]\t@ 0x190\n+\tvldr\td0, [sp, #8]\n+\tvmul.f64\td0, d0, d4\n+\tvmla.f64\td0, d14, d3\n+\tvstr\td0, [sp, #360]\t@ 0x168\n+\tvldr\td0, [sp, #16]\n+\tvmul.f64\td0, d0, d3\n+\tvmov.f64\td3, d0\n+\tvmla.f64\td3, d15, d4\n+\tvldr\td4, [sp, #144]\t@ 0x90\n+\tvmul.f64\td15, d4, d15\n+\tvstr\td3, [sp, #368]\t@ 0x170\n+\tvldr\td3, [sp, #152]\t@ 0x98\n+\tvmul.f64\td14, d14, d3\n+\tvmov.f64\td0, d14\n+\tvldr\td14, [sp, #8]\n+\tvmla.f64\td0, d14, d4\n+\tvldr\td4, [sp, #336]\t@ 0x150\n+\tvstr\td0, [sp, #432]\t@ 0x1b0\n+\tvldr\td0, [sp, #16]\n+\tvmla.f64\td15, d3, d0\n+\tvmul.f64\td0, d2, d4\n+\tvldr\td3, [sp, #328]\t@ 0x148\n+\tvmov.f64\td14, d0\n+\tvmul.f64\td0, d12, d3\n+\tvmla.f64\td14, d13, d3\n+\tvstr\td14, [sp, #8]\n+\tvmov.f64\td14, d0\n+\tvmla.f64\td14, d11, d4\n+\tvldr\td4, [sp, #304]\t@ 0x130\n+\tvldr\td3, [sp, #296]\t@ 0x128\n+\tvmul.f64\td0, d2, d4\n+\tvstr\td14, [sp, #328]\t@ 0x148\n+\tvmov.f64\td14, d0\n+\tvmla.f64\td14, d13, d3\n+\tvmul.f64\td0, d12, d3\n+\tvstr\td14, [sp, #16]\n+\tvmov.f64\td14, d0\n+\tvmla.f64\td14, d11, d4\n+\tvldr\td4, [sp, #272]\t@ 0x110\n+\tvmul.f64\td0, d2, d4\n+\tvstr\td14, [sp, #296]\t@ 0x128\n+\tvmov.f64\td14, d0\n+\tvldr\td0, [sp, #264]\t@ 0x108\n+\tvmla.f64\td14, d13, d0\n+\tvmul.f64\td0, d12, d0\n+\tvstr\td14, [sp, #64]\t@ 0x40\n+\tvmov.f64\td14, d0\n+\tvmla.f64\td14, d11, d4\n+\tvldr\td4, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td0, d2, d4\n+\tvstr\td14, [sp, #264]\t@ 0x108\n+\tvmov.f64\td14, d0\n+\tvldr\td0, [sp, #232]\t@ 0xe8\n+\tvmla.f64\td14, d13, d0\n+\tvmul.f64\td0, d12, d0\n+\tvmla.f64\td0, d11, d4\n+\tvldr\td4, [sp, #208]\t@ 0xd0\n+\tvstr\td14, [sp, #72]\t@ 0x48\n+\tvstr\td0, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td0, d2, d4\n+\tvmov.f64\td14, d0\n+\tvldr\td0, [sp, #200]\t@ 0xc8\n+\tvmla.f64\td14, d13, d0\n+\tvmul.f64\td0, d12, d0\n+\tvmla.f64\td0, d11, d4\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvmul.f64\td4, d13, d4\n+\tvstr\td14, [sp, #144]\t@ 0x90\n+\tvldr\td14, [sp, #168]\t@ 0xa8\n+\tvstr\td0, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td0, d2, d14\n+\tvmov.f64\td3, d0\n+\tvldr\td0, [sp, #160]\t@ 0xa0\n+\tvmla.f64\td3, d13, d0\n+\tvmov.f64\td13, d4\n+\tvmul.f64\td4, d12, d0\n+\tvldr\td0, [sp, #448]\t@ 0x1c0\n+\tvstr\td3, [sp, #152]\t@ 0x98\n+\tvldr\td3, [sp, #112]\t@ 0x70\n+\tvmla.f64\td13, d2, d3\n+\tvldr\td2, [sp, #80]\t@ 0x50\n+\tvstr\td13, [sp, #112]\t@ 0x70\n+\tvmov.f64\td13, d4\n+\tvmla.f64\td13, d11, d14\n+\tvmul.f64\td11, d3, d11\n+\tvldr\td4, [sp, #48]\t@ 0x30\n+\tvldr\td14, [pc, #408]\t@ 1a38 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xc0c>\n+\tvstr\td13, [sp, #160]\t@ 0xa0\n+\tvmov.f64\td13, d11\n+\tvmla.f64\td13, d4, d12\n+\tvmov.f64\td4, d14\n+\tvmul.f64\td12, d2, d2\n+\tvldr\td11, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td14, d2, d14\n+\tvsub.f64\td2, d11, d0\n+\tvmul.f64\td12, d12, d4\n+\tvmul.f64\td4, d1, d0\n+\tvstr\td13, [sp, #168]\t@ 0xa8\n+\tvldr\td13, [sp, #120]\t@ 0x78\n+\tvmla.f64\td4, d13, d11\n+\tvldr\td11, [sp, #32]\n+\tvmla.f64\td4, d10, d11\n+\tvstr\td4, [r0, #8]\n+\tvldr\td4, [sp, #24]\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td10, [sp, #424]\t@ 0x1a8\n+\tvmul.f64\td4, d2, d4\n+\tvldr\td3, [sp, #408]\t@ 0x198\n+\tvmla.f64\td4, d10, d0\n+\tvldr\td10, [sp, #416]\t@ 0x1a0\n+\tvsub.f64\td2, d3, d10\n+\tvstr\td4, [ip, #8]\n+\tvmul.f64\td4, d1, d10\n+\tvmla.f64\td4, d13, d3\n+\tvldr\td3, [sp, #392]\t@ 0x188\n+\tvmov.f64\td10, d11\n+\tvmla.f64\td4, d3, d11\n+\tvldr\td11, [sp, #376]\t@ 0x178\n+\tvldr\td3, [sp, #136]\t@ 0x88\n+\tvstr\td4, [r0, #16]\n+\tvldr\td4, [sp, #24]\n+\tvmul.f64\td4, d2, d4\n+\tvldr\td2, [sp, #400]\t@ 0x190\n+\tvmla.f64\td4, d2, d0\n+\tvldr\td2, [sp, #384]\t@ 0x180\n+\tvstr\td4, [ip, #16]\n+\tvmul.f64\td4, d1, d2\n+\tvmla.f64\td4, d13, d11\n+\tvsub.f64\td2, d11, d2\n+\tvldr\td11, [sp, #360]\t@ 0x168\n+\tvmla.f64\td4, d11, d10\n+\tvldr\td11, [sp, #128]\t@ 0x80\n+\tvstr\td4, [r0, #24]\n+\tvmul.f64\td4, d13, d3\n+\tvmla.f64\td4, d1, d11\n+\tvldr\td1, [sp, #432]\t@ 0x1b0\n+\tvsub.f64\td3, d3, d11\n+\tvmla.f64\td4, d1, d10\n+\tvldr\td1, [sp, #368]\t@ 0x170\n+\tvstr\td4, [r0, #32]\n+\tvldr\td4, [sp, #24]\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td4, d3, d4\n+\tvmla.f64\td2, d1, d0\n+\tvmla.f64\td4, d15, d0\n+\tvldr\td3, [sp, #352]\t@ 0x160\n+\tvldr\td1, [sp, #8]\n+\tvstr\td2, [ip, #24]\n+\tvldr\td2, [sp, #344]\t@ 0x158\n+\tvstr\td4, [ip, #32]\n+\tvmul.f64\td4, d5, d3\n+\tvsub.f64\td3, d2, d3\n+\tvmla.f64\td4, d7, d2\n+\tvldr\td2, [sp, #312]\t@ 0x138\n+\tvmul.f64\td3, d3, d6\n+\tvmov.f64\td0, d3\n+\tvldr\td3, [sp, #320]\t@ 0x140\n+\tvmov.f64\td10, d4\n+\tvmla.f64\td10, d1, d12\n+\tvldr\td1, [sp, #328]\t@ 0x148\n+\tvmul.f64\td4, d5, d3\n+\tvsub.f64\td3, d2, d3\n+\tvmla.f64\td4, d7, d2\n+\tvmla.f64\td0, d1, d14\n+\tvldr\td1, [sp, #16]\n+\tvmul.f64\td3, d3, d6\n+\tvmla.f64\td4, d1, d12\n+\tvldr\td1, [sp, #296]\t@ 0x128\n+\tvmov.f64\td2, d3\n+\tvmla.f64\td2, d1, d14\n+\tvstr\td0, [sp, #24]\n+\tvldr\td3, [sp, #288]\t@ 0x120\n+\tvldr\td15, [sp, #64]\t@ 0x40\n+\tvmov.f64\td0, d4\n+\tvldr\td11, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td4, d5, d3\n+\tldr\tr3, [sp, #492]\t@ 0x1ec\n+\tvmov.f64\td13, d2\n+\tvldr\td2, [sp, #280]\t@ 0x118\n+\tvmla.f64\td4, d7, d2\n+\tvsub.f64\td3, d2, d3\n+\tvmul.f64\td3, d3, d6\n+\tvmov.f64\td1, d4\n+\tvmov.f64\td2, d3\n+\tvmla.f64\td1, d15, d12\n+\tvldr\td15, [sp, #264]\t@ 0x108\n+\tvldr\td3, [sp, #256]\t@ 0x100\n+\tvmla.f64\td2, d15, d14\n+\tb.n\t1a40 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xc14>\n+\tnop.w\n+\t.word\t0x55555555\n+\t.word\t0x3fc55555\n+\tvldr\td15, [sp, #72]\t@ 0x48\n+\tvmul.f64\td4, d5, d3\n+\tvstr\td2, [sp, #16]\n+\tvldr\td2, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td4, d7, d2\n+\tvsub.f64\td3, d2, d3\n+\tvmul.f64\td3, d3, d6\n+\tvmov.f64\td2, d4\n+\tvldr\td4, [sp, #232]\t@ 0xe8\n+\tvmla.f64\td2, d15, d12\n+\tvmov.f64\td15, d3\n+\tvmla.f64\td15, d4, d14\n+\tvldr\td4, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td3, d5, d4\n+\tvsub.f64\td4, d11, d4\n+\tvmla.f64\td3, d7, d11\n+\tvldr\td11, [sp, #144]\t@ 0x90\n+\tvmul.f64\td4, d4, d6\n+\tvmla.f64\td3, d11, d12\n+\tvmov.f64\td11, d4\n+\tvldr\td4, [sp, #200]\t@ 0xc8\n+\tvmla.f64\td11, d4, d14\n+\tvstr\td3, [sp, #8]\n+\tvldr\td3, [sp, #176]\t@ 0xb0\n+\tvstr\td11, [sp, #32]\n+\tvldr\td11, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td4, d5, d11\n+\tvsub.f64\td11, d3, d11\n+\tvmla.f64\td4, d7, d3\n+\tvldr\td3, [sp, #152]\t@ 0x98\n+\tvstr\td11, [sp, #48]\t@ 0x30\n+\tvldr\td11, [sp, #40]\t@ 0x28\n+\tvmla.f64\td4, d3, d12\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvmul.f64\td7, d7, d11\n+\tvmla.f64\td7, d5, d3\n+\tvldr\td5, [sp, #112]\t@ 0x70\n+\tvmov.f64\td11, d7\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvmla.f64\td11, d5, d12\n+\tvldr\td12, [sp, #48]\t@ 0x30\n+\tvsub.f64\td5, d7, d3\n+\tvldr\td3, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td7, d12, d6\n+\tvmla.f64\td7, d3, d14\n+\tvmul.f64\td5, d5, d6\n+\tvldr\td6, [sp, #24]\n+\tvmov.f64\td3, d7\n+\tvldr\td7, [sp, #168]\t@ 0xa8\n+\tvmla.f64\td5, d7, d14\n+\tvldr\td7, [r3, #-8]\n+\tvmul.f64\td12, d6, d7\n+\tvldr\td6, [sp, #16]\n+\tvmul.f64\td13, d13, d7\n+\tvmul.f64\td15, d15, d7\n+\tvmul.f64\td14, d6, d7\n+\tvldr\td6, [sp, #32]\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td6, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d3, d7\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td6, [sp, #72]\t@ 0x48\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvldr\td7, [r3]\n+\tmov\tr3, r5\n+\tvldr\td3, [sp, #8]\n+\tvmul.f64\td6, d7, d10\n+\tvstr\td6, [sp, #16]\n+\tvmul.f64\td6, d7, d0\n+\tvstr\td6, [sp, #24]\n+\tvmul.f64\td6, d7, d1\n+\tvstr\td6, [sp, #32]\n+\tvmul.f64\td6, d7, d2\n+\tvstr\td6, [sp, #48]\t@ 0x30\n+\tvmul.f64\td6, d7, d3\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvmul.f64\td6, d7, d4\n+\tvmul.f64\td7, d11, d7\n+\tvstr\td6, [sp, #8]\n+\tvstr\td7, [sp, #40]\t@ 0x28\n+\tvldmia\tr0!, {d7}\n \tadds\tr1, #56\t@ 0x38\n-\tvldmia\tlr!, {d17}\n \tadds\tr3, #56\t@ 0x38\n+\tvldmia\tip!, {d5}\n \tadds\tr2, #56\t@ 0x38\n-\tvmul.f64\td22, d16, d27\n-\tvmul.f64\td21, d16, d29\n-\tvmul.f64\td20, d4, d17\n-\tvmul.f64\td19, d16, d12\n-\tvmul.f64\td23, d16, d3\n-\tcmp\tr6, r0\n-\tvstr\td22, [r1, #-56]\t@ 0xffffffc8\n-\tvmul.f64\td22, d16, d13\n-\tvstr\td21, [r3, #-56]\t@ 0xffffffc8\n-\tvmul.f64\td21, d5, d17\n-\tvstr\td20, [r2, #-56]\t@ 0xffffffc8\n-\tvmul.f64\td20, d7, d17\n-\tvstr\td19, [r1, #-48]\t@ 0xffffffd0\n-\tvmul.f64\td19, d16, d6\n-\tvstr\td23, [r3, #-48]\t@ 0xffffffd0\n-\tvmul.f64\td23, d16, d30\n-\tvstr\td21, [r2, #-48]\t@ 0xffffffd0\n-\tvmul.f64\td21, d16, d26\n-\tvstr\td22, [r1, #-40]\t@ 0xffffffd8\n-\tvmul.f64\td22, d16, d25\n-\tvstr\td19, [r3, #-40]\t@ 0xffffffd8\n-\tvmul.f64\td19, d31, d17\n-\tvstr\td20, [r2, #-40]\t@ 0xffffffd8\n-\tvmul.f64\td20, d16, d28\n-\tvstr\td21, [r1, #-32]\t@ 0xffffffe0\n-\tvmul.f64\td21, d2, d17\n-\tvstr\td23, [r3, #-32]\t@ 0xffffffe0\n-\tvmul.f64\td23, d16, d1\n-\tvstr\td19, [r2, #-32]\t@ 0xffffffe0\n-\tvmul.f64\td19, d16, d24\n-\tvstr\td22, [r1, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td22, d16, d18\n-\tvstr\td20, [r3, #-24]\t@ 0xffffffe8\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td20, d0, d17\n-\tvmul.f64\td17, d9, d17\n-\tvstr\td21, [r2, #-24]\t@ 0xffffffe8\n-\tvstr\td19, [r1, #-16]\n-\tvstr\td23, [r3, #-16]\n-\tvstr\td20, [r2, #-16]\n-\tvstr\td22, [r1, #-8]\n-\tvstr\td16, [r3, #-8]\n-\tvstr\td17, [r2, #-8]\n-\tbne.n\t1a14 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xbac>\n-\tmov\tr1, r5\n+\tvmul.f64\td6, d7, d10\n+\tcmp\tr5, r0\n+\tvstr\td6, [r1, #-56]\t@ 0xffffffc8\n+\tvmul.f64\td6, d7, d12\n+\tvstr\td6, [r3, #-56]\t@ 0xffffffc8\n+\tvldr\td6, [sp, #16]\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-56]\t@ 0xffffffc8\n+\tvmul.f64\td6, d7, d0\n+\tvstr\td6, [r1, #-48]\t@ 0xffffffd0\n+\tvmul.f64\td6, d7, d13\n+\tvstr\td6, [r3, #-48]\t@ 0xffffffd0\n+\tvldr\td6, [sp, #24]\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-48]\t@ 0xffffffd0\n+\tvmul.f64\td6, d7, d1\n+\tvstr\td6, [r1, #-40]\t@ 0xffffffd8\n+\tvmul.f64\td6, d7, d14\n+\tvstr\td6, [r3, #-40]\t@ 0xffffffd8\n+\tvldr\td6, [sp, #32]\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-40]\t@ 0xffffffd8\n+\tvmul.f64\td6, d7, d2\n+\tvstr\td6, [r1, #-32]\t@ 0xffffffe0\n+\tvmul.f64\td6, d7, d15\n+\tvstr\td6, [r3, #-32]\t@ 0xffffffe0\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-32]\t@ 0xffffffe0\n+\tvmul.f64\td6, d7, d3\n+\tvstr\td6, [r1, #-24]\t@ 0xffffffe8\n+\tvldr\td6, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d7, d6\n+\tvstr\td6, [r3, #-24]\t@ 0xffffffe8\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-24]\t@ 0xffffffe8\n+\tvmul.f64\td6, d7, d4\n+\tvstr\td6, [r1, #-16]\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvmul.f64\td6, d7, d6\n+\tvstr\td6, [r3, #-16]\n+\tvldr\td6, [sp, #8]\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [r2, #-16]\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmul.f64\td5, d6, d5\n+\tvmul.f64\td6, d7, d11\n+\tvstr\td6, [r1, #-8]\n+\tvldr\td6, [sp, #80]\t@ 0x50\n+\tvstr\td5, [r2, #-8]\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3, #-8]\n+\tbne.n\t1b7e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xd52>\n+\tmov\tr1, r9\n \tmov.w\tr2, #280\t@ 0x118\n-\tldr\tr0, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tmovs\tr7, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr3, [sp, #44]\t@ 0x2c\n-\tldr.w\tlr, [sp, #76]\t@ 0x4c\n+\tldr\tr3, [sp, #92]\t@ 0x5c\n+\tldr.w\tlr, [sp, #100]\t@ 0x64\n \tmov.w\tip, #4294967295\t@ 0xffffffff\n \tcmp\tr3, #2\n-\tldr.w\tfp, [sp, #240]\t@ 0xf0\n+\tldr.w\tfp, [sp, #192]\t@ 0xc0\n \tit\tge\n \tmovge\tr3, #2\n-\tldr\tr0, [sp, #408]\t@ 0x198\n+\tldr\tr0, [sp, #488]\t@ 0x1e8\n \tmov\tr8, r3\n-\tadd.w\tr2, r6, #280\t@ 0x118\n+\tadd.w\tr2, r5, #280\t@ 0x118\n \tadd.w\tr1, r4, #280\t@ 0x118\n-\tmov\tsl, lr\n-\tmov\tr5, r4\n-\tmov\tr3, r6\n-\tvldmia\tr5!, {d16}\n-\tvldmia\tr3!, {d17}\n-\tvnmul.f64\td16, d10, d16\n-\tvfma.f64\td16, d17, d11\n+\tmov\tr9, lr\n+\tmov\tr6, r4\n+\tmov\tr3, r5\n+\tvldmia\tr6!, {d7}\n+\tvldmia\tr3!, {d6}\n+\tvmul.f64\td7, d7, d9\n \tcmp\tr3, r2\n-\tvstmia\tsl!, {d16}\n-\tbne.n\t1b02 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xc9a>\n-\tmov\tsl, r0\n-\tadd.w\tr5, ip, ip, lsl #1\n+\tvnmls.f64\td7, d6, d8\n+\tvstmia\tr9!, {d7}\n+\tbne.n\t1c94 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xe68>\n+\tmov\tr9, r0\n+\tadd.w\tr6, ip, ip, lsl #1\n \tstr.w\tr8, [sp, #8]\n-\tvldmia\tsl!, {d17}\n-\tadd.w\tr8, fp, r5, lsl #3\n+\tvldmia\tr9!, {d6}\n+\tadd.w\tr8, fp, r6, lsl #3\n \tmov\tr3, r4\n-\tvldmia\tr3!, {d16}\n+\tvldmia\tr3!, {d7}\n \tadd.w\tr8, r8, #24\n-\tvmul.f64\td16, d16, d17\n-\tcmp\tr3, r1\n-\tvstr\td16, [r8]\n-\tbne.n\t1b2e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xcc6>\n-\tadds\tr5, #1\n+\tvmul.f64\td7, d7, d6\n+\tcmp\tr1, r3\n+\tvstr\td7, [r8]\n+\tbne.n\t1cc0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xe94>\n+\tadds\tr6, #1\n \tcmp\tr9, sl\n-\tbne.n\t1b24 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xcbc>\n+\tbne.n\t1cb6 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xe8a>\n \tsub.w\tr7, r7, #1\n \tldr.w\tr8, [sp, #8]\n \tclz\tr7, r7\n \tadd.w\tlr, lr, #280\t@ 0x118\n \tadd.w\tip, ip, #35\t@ 0x23\n \tlsrs\tr7, r7, #5\n \tcmp\tr7, #0\n \tmov.w\tr7, #2\n-\tmov\tr3, r7\n-\tit\teq\n+\tite\tne\n+\tmovne\tr3, #2\n \tmoveq\tr3, #3\n \tcmp\tr3, r8\n-\tble.n\t1afc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xc94>\n-\tldr.w\tr2, [pc, #1096]\t@ 1fb8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1150>\n-\tldr.w\tr3, [pc, #1096]\t@ 1fbc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1154>\n+\tble.n\t1c8e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xe62>\n+\tldr\tr2, [pc, #924]\t@ (20a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1274>)\n+\tldr\tr3, [pc, #928]\t@ (20a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1278>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [sp, #1684]\t@ 0x694\n+\tldr.w\tr3, [sp, #1764]\t@ 0x6e4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1f78 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1110>\n-\taddw\tsp, sp, #1692\t@ 0x69c\n+\tbne.w\t2156 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x132a>\n+\taddw\tsp, sp, #1772\t@ 0x6ec\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tadd.w\tr9, sp, #672\t@ 0x2a0\n+\tadd.w\tsl, sp, #752\t@ 0x2f0\n \tldr\tr0, [r2, #0]\n-\tmov\tr5, r9\n+\tmov\tr5, sl\n \tldr\tr1, [r2, #4]\n \tldr\tr3, [r4, #12]\n \tldr\tr2, [r2, #8]\n \tstmia\tr5!, {r0, r1, r2, r3}\n \tldr\tr0, [r4, #16]\n \tldr\tr1, [r4, #20]\n \tstmia\tr5!, {r0, r1}\n-\tb.w\tef8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x90>\n-\tldr.w\tr2, [pc, #1036]\t@ 1fc0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1158>\n-\tldr.w\tr3, [pc, #1028]\t@ 1fbc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1154>\n+\tb.w\tebc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x90>\n+\tldr\tr2, [pc, #872]\t@ (20a8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x127c>)\n+\tldr\tr3, [pc, #864]\t@ (20a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1278>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [sp, #1684]\t@ 0x694\n+\tldr.w\tr3, [sp, #1764]\t@ 0x6e4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t1f78 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1110>\n-\tldr\tr0, [sp, #72]\t@ 0x48\n+\tbne.w\t2156 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x132a>\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tmov.w\tr2, #280\t@ 0x118\n \tmovs\tr1, #0\n-\taddw\tsp, sp, #1692\t@ 0x69c\n+\taddw\tsp, sp, #1772\t@ 0x6ec\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemset\n-\tldr\tr7, [pc, #988]\t@ (1fc4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x115c>)\n-\tvmov.i64\td8, #0x0000000000000000\n-\tldr\tr2, [pc, #988]\t@ (1fc8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1160>)\n+\tldr\tr3, [pc, #828]\t@ (20ac <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1280>)\n+\tldr.w\tfp, [pc, #828]\t@ 20b0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1284>\n+\tadd\tr3, pc\n+\tvldr\td10, [pc, #800]\t@ 2098 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x126c>\n+\tadd.w\tr7, r3, #392\t@ 0x188\n+\tadd\tfp, pc\n+\tadd.w\tr3, r3, #784\t@ 0x310\n+\tmov\tr8, r7\n+\tmov\tr4, r3\n+\tmov\tr6, r3\n+\tmov\tr9, r7\n+\tadd.w\tr5, fp, #72\t@ 0x48\n+\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #40]\t@ 0x28\n+\tstr\tr7, [sp, #8]\n+\tstr.w\tsl, [sp, #32]\n+\tmov\tip, r8\n+\tldr\tr7, [pc, #788]\t@ (20b4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1288>)\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tadd.w\tsl, fp, #8\n \tadd\tr7, pc\n-\tstr.w\tr9, [sp, #16]\n-\tadd.w\tr8, r7, #400\t@ 0x190\n-\tadd\tr2, pc\n-\tadd.w\tr7, r7, #792\t@ 0x318\n-\tmov\tsl, r8\n-\tmov\tr5, r7\n-\tmov\tfp, r8\n-\tadd.w\tr6, r2, #72\t@ 0x48\n-\tmov\tr4, r2\n-\tstr\tr7, [sp, #32]\n-\tstr.w\tr8, [sp, #8]\n-\tmov\tip, sl\n-\tldr.w\tr8, [pc, #952]\t@ 1fcc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1164>\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tadd.w\tr9, r4, #8\n-\tadd\tr8, pc\n-\tvstr\td8, [fp]\n-\tvstr\td8, [fp, #8]\n-\tmov\tr1, fp\n-\tvstr\td8, [fp, #16]\n-\tmov\tr3, r6\n-\tvstr\td8, [fp, #24]\n-\tmov\tr2, r9\n-\tvstr\td8, [fp, #32]\n-\tmov\tr0, r8\n-\tvstr\td8, [fp, #40]\t@ 0x28\n-\tadd.w\tfp, fp, #56\t@ 0x38\n-\tvstr\td8, [fp, #-8]\n-\tadd.w\tsl, sl, #64\t@ 0x40\n-\tvstr\td16, [ip]\n-\tstrd\tr6, r5, [sp]\n-\tadds\tr5, #56\t@ 0x38\n+\tvstr\td10, [r9]\n+\tvstr\td10, [r9, #8]\n+\tmov\tr1, r9\n+\tvstr\td10, [r9, #16]\n+\tmov\tr3, r5\n+\tvstr\td10, [r9, #24]\n+\tmov\tr2, sl\n+\tvstr\td10, [r9, #32]\n+\tmov\tr0, r7\n+\tvstr\td10, [r9, #40]\t@ 0x28\n+\tadd.w\tr9, r9, #56\t@ 0x38\n+\tvstr\td10, [r9, #-8]\n+\tadd.w\tr8, r8, #64\t@ 0x40\n+\tvstr\td7, [ip]\n+\tstrd\tr5, r6, [sp]\n+\tadds\tr6, #56\t@ 0x38\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_x>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_x\n-\tcmp\tr7, fp\n-\tbne.n\t1c0e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xda6>\n-\tmov\tr3, r8\n-\tmov\tr4, r9\n-\tldr.w\tr9, [sp, #16]\n-\tadd.w\tr2, r3, #1184\t@ 0x4a0\n+\tcmp\tr9, r4\n+\tbne.n\t1d9a <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xf6e>\n+\tmov\tr3, r7\n+\tmov\tr4, sl\n+\tadd.w\tr2, r3, #1176\t@ 0x498\n+\tadd.w\tfp, r3, #1376\t@ 0x560\n+\tldr.w\tsl, [sp, #32]\n \tsubs\tr4, #8\n-\tadd.w\tr5, r3, #1384\t@ 0x568\n-\tmov\tsl, r2\n+\tmov\tr8, r2\n+\tmov\tr6, fp\n+\tmov\tr9, r2\n \tadds\tr3, #56\t@ 0x38\n-\tstr.w\tr8, [sp, #64]\t@ 0x40\n-\tstr\tr2, [sp, #80]\t@ 0x50\n-\tmov\tr2, r4\n-\tldr.w\tr8, [sp, #8]\n-\tmov\tr4, r6\n+\tstr\tr7, [sp, #16]\n+\tstr\tr2, [sp, #72]\t@ 0x48\n+\tldr\tr7, [sp, #8]\n+\tstr.w\tfp, [sp, #56]\t@ 0x38\n \tstr\tr3, [sp, #8]\n-\tmov\tr3, r9\n-\tmov\tfp, r3\n-\tmov\tr9, r7\n-\tmov\tr6, r2\n-\tmov\tr7, sl\n-\tstr\tr5, [sp, #16]\n-\tstr\tr5, [sp, #48]\t@ 0x30\n-\tvmov.i64\td16, #0x0000000000000000\n-\tmov\tip, sl\n-\tmov\tr3, r4\n-\tmov\tr1, r7\n+\tvldr\td7, [pc, #648]\t@ 2098 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x126c>\n+\tmov\tip, r8\n+\tmov\tr1, r9\n \tldr\tr0, [sp, #8]\n-\tadd.w\tr2, r6, #24\n-\tadds\tr7, #40\t@ 0x28\n-\tadd.w\tsl, sl, #48\t@ 0x30\n-\tvstr\td16, [r7, #-40]\t@ 0xffffffd8\n-\tvstr\td16, [r7, #-32]\t@ 0xffffffe0\n-\tvstr\td16, [r7, #-24]\t@ 0xffffffe8\n-\tvstr\td16, [r7, #-16]\n-\tvstr\td16, [r7, #-8]\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvstr\td16, [ip]\n-\tstrd\tr4, r5, [sp]\n-\tadds\tr5, #40\t@ 0x28\n+\tmov\tr3, r5\n+\tadd.w\tr2, r4, #24\n+\tvstr\td7, [r9]\n+\tadd.w\tr9, r9, #40\t@ 0x28\n+\tvstr\td7, [r9, #-32]\t@ 0xffffffe0\n+\tadd.w\tr8, r8, #48\t@ 0x30\n+\tvstr\td7, [r9, #-24]\t@ 0xffffffe8\n+\tvstr\td7, [r9, #-16]\n+\tvstr\td7, [r9, #-8]\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [ip]\n+\tstrd\tr5, r6, [sp]\n+\tadds\tr6, #40\t@ 0x28\n \tbl\t0 <__gridxc_interpolation_MOD_generate_spline_x>\n R_ARM_THM_CALL\t__gridxc_interpolation_MOD_generate_spline_x\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr7, r3\n-\tbne.n\t1c90 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xe28>\n-\tldr\tr3, [pc, #764]\t@ (1fd0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1168>)\n-\tmov\tr7, r9\n-\tvldr\td16, [pc, #680]\t@ 1f80 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1118>\n-\tmov\tr9, fp\n+\tcmp\tfp, r9\n+\tbne.n\t1e0c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xfe0>\n+\tldr\tr3, [pc, #616]\t@ (20b8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x128c>)\n+\tadd\tr6, sp, #520\t@ 0x208\n+\tmov\tr0, r6\n+\tmov.w\tr2, #16777472\t@ 0x1000100\n \tadd\tr3, pc\n-\tadd.w\tfp, sp, #440\t@ 0x1b8\n-\tstr\tr3, [sp, #24]\n-\tmov\tr0, fp\n-\tstr\tr3, [sp, #448]\t@ 0x1c0\n-\tadd.w\tr5, sp, #1336\t@ 0x538\n-\tldr\tr3, [pc, #740]\t@ (1fd4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x116c>)\n-\tadd.w\tr4, sp, #1056\t@ 0x420\n-\tvstr\td16, [sp, #440]\t@ 0x1b8\n+\tstr\tr3, [sp, #32]\n+\tstr\tr3, [sp, #528]\t@ 0x210\n+\tadd.w\tr9, sp, #1416\t@ 0x588\n+\tldr\tr3, [pc, #600]\t@ (20bc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1290>)\n+\tadd.w\tr4, sp, #1136\t@ 0x470\n+\taddw\tr5, sp, #1148\t@ 0x47c\n+\tmov.w\tr8, #8\n \tadd\tr3, pc\n-\tstr\tr3, [sp, #484]\t@ 0x1e4\n+\tstr\tr3, [sp, #564]\t@ 0x234\n \tmov.w\tr3, #416\t@ 0x1a0\n-\tstr\tr3, [sp, #452]\t@ 0x1c4\n+\tstr\tr3, [sp, #532]\t@ 0x214\n \tmovs\tr3, #7\n-\tstr\tr3, [sp, #480]\t@ 0x1e0\n+\tstr\tr3, [sp, #560]\t@ 0x230\n \tmovs\tr3, #0\n-\tstr\tr3, [sp, #604]\t@ 0x25c\n+\tstr\tr3, [sp, #684]\t@ 0x2ac\n+\tmovs\tr3, #22\n+\tstrd\tr2, r3, [sp, #520]\t@ 0x208\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tldr\tr6, [sp, #64]\t@ 0x40\n-\taddw\tr3, sp, #1068\t@ 0x42c\n-\tmov\tr2, r8\n+\tldr\tr3, [sp, #16]\n \tstr\tr3, [sp, #8]\n-\taddw\tr3, sp, #1076\t@ 0x434\n-\tvldr\td14, [pc, #620]\t@ 1f88 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1120>\n-\tvldr\td15, [pc, #624]\t@ 1f90 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1128>\n-\tmov\tr8, r6\n-\tstr.w\tfp, [sp, #96]\t@ 0x60\n-\tmov\tr6, r2\n-\tvldr\td8, [pc, #620]\t@ 1f98 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1130>\n-\tmov\tfp, r3\n-\tstr\tr3, [sp, #64]\t@ 0x40\n-\tstr.w\tr9, [sp, #88]\t@ 0x58\n-\tldr\tr3, [sp, #24]\n-\tmov\tr0, r5\n-\tstr\tr3, [r5, #8]\n-\tvmov.i32\td13, #0\t@ 0x00000000\n-\tldr\tr3, [pc, #660]\t@ (1fd8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1170>)\n-\tmov.w\tr9, #4294967295\t@ 0xffffffff\n-\tmovw\tsl, #769\t@ 0x301\n+\tldr\tr3, [pc, #556]\t@ (20c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1294>)\n+\tstr.w\tsl, [sp, #104]\t@ 0x68\n+\tmov\tsl, r9\n \tadd\tr3, pc\n-\tstr\tr3, [r5, #52]\t@ 0x34\n+\tstr.w\tfp, [sp, #80]\t@ 0x50\n+\tstr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr7, [sp, #16]\n+\tstr\tr6, [sp, #112]\t@ 0x70\n+\tldr\tr3, [sp, #32]\n+\tmov.w\tip, #4096\t@ 0x1000\n+\tstr.w\tr3, [sl, #8]\n+\tmov\tr0, sl\n+\tldr\tr3, [sp, #48]\t@ 0x30\n+\tmovs\tr6, #1\n+\tstr.w\tr3, [sl, #52]\t@ 0x34\n \tmov.w\tr3, #418\t@ 0x1a2\n-\tstr\tr3, [r5, #12]\n+\tstr.w\tr3, [sl, #12]\n \tmovs\tr3, #9\n-\tstr\tr3, [r5, #56]\t@ 0x38\n-\tadd.w\tr3, sp, #1336\t@ 0x538\n-\tvstr\td8, [r3]\n+\tstr.w\tr3, [sl, #56]\t@ 0x38\n+\tmovs\tr3, #22\n+\tstrd\tip, r3, [sl]\n+\tmovs\tr7, #7\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr1, r8\n+\tldr\tr1, [sp, #8]\n \tmovs\tr2, #8\n-\tmov\tr0, r5\n+\tmov\tr0, sl\n \tbl\t0 <_gfortran_transfer_real_write>\n R_ARM_THM_CALL\t_gfortran_transfer_real_write\n-\tldr\tr3, [sp, #8]\n-\tmovs\tr2, #8\n-\tmov\tr1, r4\n-\tmov\tr0, r5\n-\tadd.w\tr8, r8, #8\n-\tvstr\td13, [r3]\n+\tldr\tr2, [sp, #16]\n \tmovs\tr3, #0\n-\tstr\tr2, [r4, #8]\n-\tstrh.w\tsl, [r4, #16]\n-\tvst1.32\t{d14-d15}, [fp]\n-\tstrd\tr6, r9, [r4]\n-\tadds\tr6, #56\t@ 0x38\n+\tmov\tr1, r4\n+\tmov\tr0, sl\n+\tmov.w\tfp, #4294967295\t@ 0xffffffff\n+\tstr.w\tr8, [r4, #20]\n+\tmovw\tr9, #769\t@ 0x301\n+\tstrd\tr3, r3, [r5]\n+\tstr\tr2, [r4, #0]\n+\tmovs\tr2, #8\n+\tstrd\tr6, r6, [r4, #24]\n+\tstr.w\tr8, [r4, #8]\n+\tstr\tr7, [r4, #32]\n+\tstr.w\tfp, [r4, #4]\n+\tstrh.w\tr9, [r4, #16]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tldr\tr3, [sp, #8]\n+\tmovs\tr3, #0\n+\tstr.w\tr8, [r4, #20]\n \tmovs\tr2, #8\n+\tstrd\tr3, r3, [r5]\n \tmov\tr1, r4\n-\tmov\tr0, r5\n-\tvstr\td13, [r3]\n-\tmovs\tr3, #0\n-\tstr\tr2, [r4, #8]\n-\tstrh.w\tsl, [r4, #16]\n-\tvst1.32\t{d14-d15}, [fp]\n-\tstrd\tr7, r9, [r4]\n-\tadds\tr7, #56\t@ 0x38\n+\tstrd\tr6, r6, [r4, #24]\n+\tmov\tr0, sl\n+\tldr\tr6, [sp, #24]\n+\tstrh.w\tr9, [r4, #16]\n+\tstrd\tfp, r8, [r4, #4]\n+\tstr\tr7, [r4, #32]\n+\tstr\tr6, [r4, #0]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tmov\tr0, r5\n+\tmov\tr0, sl\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tldr\tr3, [sp, #32]\n-\tcmp\tr6, r3\n-\tbne.n\t1d36 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xece>\n-\tldr.w\tfp, [sp, #96]\t@ 0x60\n-\tmov.w\tr3, #420\t@ 0x1a4\n-\tvldr\td16, [pc, #468]\t@ 1fa0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1138>\n-\tldr\tr6, [sp, #24]\n-\tmov\tr0, fp\n-\tstr.w\tr6, [fp, #8]\n-\tstr.w\tr3, [fp, #12]\n-\tvstr\td16, [fp]\n-\tldr.w\tr9, [sp, #88]\t@ 0x58\n+\tldr\tr3, [sp, #8]\n+\tldr\tr2, [sp, #16]\n+\tadds\tr3, #8\n+\tstr\tr3, [sp, #8]\n+\tadd.w\tr3, r6, #56\t@ 0x38\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #40]\t@ 0x28\n+\tadds\tr2, #56\t@ 0x38\n+\tstr\tr2, [sp, #16]\n+\tcmp\tr3, r2\n+\tmov.w\tr3, #0\n+\tbne.n\t1ea4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1078>\n+\tldr\tr6, [sp, #112]\t@ 0x70\n+\tmov.w\tr2, #420\t@ 0x1a4\n+\tldr\tr7, [sp, #32]\n+\tmov\tr9, sl\n+\tmov\tr0, r6\n+\tldr.w\tsl, [sp, #104]\t@ 0x68\n+\tstr\tr2, [r6, #12]\n+\tstr\tr7, [r6, #8]\n+\tstr\tr3, [r6, #0]\n+\tmovs\tr3, #22\n+\tstr\tr3, [r6, #4]\n+\tldr.w\tfp, [sp, #80]\t@ 0x50\n \tbl\t0 <_gfortran_st_close>\n R_ARM_THM_CALL\t_gfortran_st_close\n-\tvldr\td16, [pc, #408]\t@ 1f80 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1118>\n-\tmov\tr0, fp\n-\tstr.w\tr6, [fp, #8]\n-\tldr\tr3, [pc, #488]\t@ (1fdc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1174>)\n-\tldr\tr6, [pc, #492]\t@ (1fe0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1178>)\n-\tadd\tr3, pc\n-\tvstr\td16, [fp]\n-\tstr.w\tr3, [fp, #44]\t@ 0x2c\n-\tadd\tr6, pc\n \tmovs\tr3, #7\n-\tstr.w\tr3, [fp, #40]\t@ 0x28\n+\tstr\tr3, [r6, #40]\t@ 0x28\n \tmovs\tr3, #0\n-\tstr.w\tr3, [fp, #164]\t@ 0xa4\n+\tstr.w\tr3, [r6, #164]\t@ 0xa4\n+\tmovs\tr3, #22\n+\tstr\tr3, [r6, #4]\n+\tldr\tr3, [pc, #316]\t@ (20c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1298>)\n+\tmov\tr0, r6\n+\tstr\tr7, [r6, #8]\n+\tmovs\tr7, #8\n+\tadd\tr3, pc\n+\tstr\tr3, [r6, #44]\t@ 0x2c\n+\tmov.w\tr3, #16777472\t@ 0x1000100\n+\tstr\tr3, [r6, #0]\n \tmovw\tr3, #421\t@ 0x1a5\n-\tstr.w\tr3, [fp, #12]\n+\tstr\tr3, [r6, #12]\n \tbl\t0 <_gfortran_st_open>\n R_ARM_THM_CALL\t_gfortran_st_open\n-\tadds\tr6, #56\t@ 0x38\n-\tldr\tr2, [pc, #456]\t@ (1fe4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x117c>)\n-\tmov\tr8, r6\n-\tldr\tr7, [sp, #80]\t@ 0x50\n-\tvldr\td14, [pc, #388]\t@ 1fa8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1140>\n-\tvldr\td15, [pc, #392]\t@ 1fb0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1148>\n-\tstr.w\tfp, [sp, #80]\t@ 0x50\n-\tldr.w\tfp, [sp, #8]\n+\tldr\tr3, [pc, #292]\t@ (20c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x129c>)\n+\tldr\tr2, [pc, #292]\t@ (20cc <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12a0>)\n+\tadd\tr3, pc\n+\tstr.w\tsl, [sp, #32]\n+\tadds\tr3, #56\t@ 0x38\n+\tldr.w\tsl, [sp, #72]\t@ 0x48\n+\tstr\tr3, [sp, #8]\n \tadd\tr2, pc\n-\tvldr\td8, [pc, #356]\t@ 1f98 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1130>\n-\tstr\tr2, [sp, #24]\n-\tstr.w\tr9, [sp, #32]\n-\tldr\tr3, [sp, #24]\n-\tmov\tr0, r5\n-\tstr\tr3, [r5, #8]\n-\tvmov.i32\td13, #0\t@ 0x00000000\n-\tldr\tr3, [pc, #416]\t@ (1fe8 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1180>)\n-\tmov.w\tr9, #4294967295\t@ 0xffffffff\n-\tmovw\tsl, #769\t@ 0x301\n+\tldr\tr3, [pc, #280]\t@ (20d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12a4>)\n+\tstr\tr2, [sp, #16]\n \tadd\tr3, pc\n-\tstr\tr3, [r5, #52]\t@ 0x34\n+\tstr\tr6, [sp, #40]\t@ 0x28\n+\tstr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #16]\n+\tmov.w\tr1, #4096\t@ 0x1000\n+\tstr.w\tr3, [r9, #8]\n+\tmov\tr0, r9\n+\tldr\tr3, [sp, #24]\n+\tmov.w\tr8, #0\n+\tstr.w\tr3, [r9, #52]\t@ 0x34\n \tmovs\tr3, #9\n-\tstr\tr3, [r5, #56]\t@ 0x38\n+\tstr.w\tr3, [r9, #56]\t@ 0x38\n+\tmovs\tr3, #22\n+\tstrd\tr1, r3, [r9]\n \tmovw\tr3, #423\t@ 0x1a7\n-\tstr\tr3, [r5, #12]\n-\tadd.w\tr3, sp, #1336\t@ 0x538\n-\tvstr\td8, [r3]\n+\tstr.w\tr3, [r9, #12]\n+\tmovs\tr6, #1\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tmov\tr1, r8\n+\tldr\tr1, [sp, #8]\n \tmovs\tr2, #8\n-\tmov\tr0, r5\n+\tmov\tr0, r9\n \tbl\t0 <_gfortran_transfer_real_write>\n R_ARM_THM_CALL\t_gfortran_transfer_real_write\n-\tldr\tr6, [sp, #64]\t@ 0x40\n-\tvstr\td13, [fp]\n+\tmov\tr3, r8\n \tmovs\tr2, #8\n-\tmovs\tr3, #0\n-\tstr\tr2, [r4, #8]\n \tmov\tr1, r4\n-\tmov\tr0, r5\n-\tstrh.w\tsl, [r4, #16]\n-\tadd.w\tr8, r8, #8\n-\tvst1.32\t{d14-d15}, [r6]\n-\tstrd\tr7, r9, [r4]\n-\tadds\tr7, #40\t@ 0x28\n+\tmov\tr0, r9\n+\tstr\tr7, [r4, #20]\n+\tstrd\tr8, r8, [r5]\n+\tstr.w\tsl, [r4]\n+\tadd.w\tsl, sl, #40\t@ 0x28\n+\tstrd\tr6, r6, [r4, #24]\n+\tmovs\tr6, #5\n+\tstr\tr7, [r4, #8]\n+\tstr\tr6, [r4, #32]\n+\tmov.w\tr6, #4294967295\t@ 0xffffffff\n+\tstr\tr6, [r4, #4]\n+\tmovw\tr6, #769\t@ 0x301\n+\tstrh\tr6, [r4, #16]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tvstr\td13, [fp]\n-\tmovs\tr2, #8\n-\tstrh.w\tsl, [r4, #16]\n-\tstr\tr2, [r4, #8]\n-\tmovs\tr3, #0\n-\tvst1.32\t{d14-d15}, [r6]\n+\tmovs\tr2, #5\n+\tmovs\tr3, #1\n \tmov\tr1, r4\n-\tldr\tr6, [sp, #16]\n-\tmov\tr0, r5\n-\tstr.w\tr9, [r4, #4]\n-\tstr\tr6, [r4, #0]\n+\tmov\tr0, r9\n+\tstr\tr7, [r4, #20]\n+\tstrd\tr8, r8, [r5]\n+\tstr\tr2, [r4, #32]\n+\tmov.w\tr2, #4294967295\t@ 0xffffffff\n+\tstrd\tr3, r3, [r4, #24]\n+\tmov\tr3, r8\n+\tstrd\tr2, r7, [r4, #4]\n+\tmovs\tr2, #8\n+\tstr.w\tfp, [r4]\n+\tadd.w\tfp, fp, #40\t@ 0x28\n+\tstrh\tr6, [r4, #16]\n \tbl\t0 <_gfortran_transfer_array_write>\n R_ARM_THM_CALL\t_gfortran_transfer_array_write\n-\tmov\tr0, r5\n+\tmov\tr0, r9\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmov\tr3, r6\n-\tadds\tr3, #40\t@ 0x28\n-\tstr\tr3, [sp, #16]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n-\tcmp\tr7, r3\n-\tbne.n\t1e3c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xfd4>\n-\tldr.w\tfp, [sp, #80]\t@ 0x50\n-\tmovw\tr3, #425\t@ 0x1a9\n-\tvldr\td16, [pc, #200]\t@ 1fa0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1138>\n-\tldr\tr2, [sp, #24]\n-\tmov\tr0, fp\n-\tstr.w\tr2, [fp, #8]\n-\tstr.w\tr3, [fp, #12]\n-\tvstr\td16, [fp]\n-\tldr.w\tr9, [sp, #32]\n+\tldr\tr3, [sp, #8]\n+\tadds\tr3, #8\n+\tstr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #56]\t@ 0x38\n+\tcmp\tsl, r3\n+\tbne.n\t1fc0 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1194>\n+\tldr\tr6, [sp, #40]\t@ 0x28\n+\tmovs\tr3, #22\n+\tldr\tr2, [sp, #16]\n+\tmov\tr0, r6\n+\tldr.w\tsl, [sp, #32]\n+\tstr\tr2, [r6, #8]\n+\tmovw\tr2, #425\t@ 0x1a9\n+\tstrd\tr8, r3, [r6]\n+\tstr\tr2, [r6, #12]\n \tbl\t0 <_gfortran_st_close>\n R_ARM_THM_CALL\t_gfortran_st_close\n-\tldr\tr3, [pc, #248]\t@ (1fec <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x1184>)\n-\tmovs\tr2, #0\n-\tadd\tr3, pc\n-\tstr\tr2, [r3, #0]\n-\tb.w\tfa2 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x13a>\n+\tldr\tr2, [pc, #76]\t@ (20d4 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12a8>)\n+\tadd\tr2, pc\n+\tstr.w\tr8, [r2]\n+\tb.w\tf64 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x138>\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x00000398\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x00000362\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000334\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000032e\n+ R_ARM_REL32\t.rodata\n+\t.word\t0x0000030a\n+ R_ARM_REL32\t.bss\n+\t.word\t0x0000025c\n+ R_ARM_REL32\t.LC18\n+\t.word\t0x00000248\n+ R_ARM_REL32\t.LC19\n+\t.word\t0x00000224\n+ R_ARM_REL32\t.LC20\n+\t.word\t0x00000132\n+ R_ARM_REL32\t.LC21\n+\t.word\t0x0000011e\n+ R_ARM_REL32\t.bss\n+\t.word\t0x00000114\n+ R_ARM_REL32\t.LC18\n+\t.word\t0x00000112\n+ R_ARM_REL32\t.LC20\n+\t.word\t0x00000048\n+ R_ARM_REL32\t.data\n \tmov.w\tr4, #280\t@ 0x118\n \tmovs\tr1, #0\n \tmov\tr2, r4\n-\tldr\tr0, [sp, #72]\t@ 0x48\n+\tldr\tr0, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr5, [sp, #44]\t@ 0x2c\n+\tldr\tr5, [sp, #92]\t@ 0x5c\n \tmovs\tr1, #0\n-\tldr\tr0, [sp, #76]\t@ 0x4c\n+\tldr\tr0, [sp, #100]\t@ 0x64\n \tmul.w\tr2, r4, r5\n \tmov.w\tr4, #840\t@ 0x348\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tldr\tr3, [sp, #240]\t@ 0xf0\n+\tldr\tr3, [sp, #192]\t@ 0xc0\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tadds\tr2, r3, r4\n \tmla\tr4, r5, r4, r4\n \tadd\tr4, r3\n \tsub.w\tr3, r2, #840\t@ 0x348\n \tstrd\tr0, r1, [r3]\n \tadds\tr3, #24\n \tstrd\tr0, r1, [r3, #-16]\n \tstrd\tr0, r1, [r3, #-8]\n-\tcmp\tr2, r3\n-\tbne.n\t1f30 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x10c8>\n+\tcmp\tr3, r2\n+\tbne.n\t210a <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12de>\n \tadd.w\tr2, r2, #840\t@ 0x348\n \tcmp\tr4, r2\n-\tbne.n\t1f2c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x10c4>\n-\tb.n\t1b6e <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xd06>\n-\tvldr\td13, [r3, #56]\t@ 0x38\n-\tvsub.f64\td18, d13, d17\n-\tvcmpe.f64\td8, d18\n+\tbne.n\t2106 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x12da>\n+\tb.n\t1d00 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0xed4>\n+\tvldr\td11, [r3, #56]\t@ 0x38\n+\tvldr\td4, [sp, #8]\n+\tvsub.f64\td7, d11, d5\n+\tvcmpe.f64\td4, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t120c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a4>\n-\tvldr\td18, [r3, #88]\t@ 0x58\n-\tvadd.f64\td17, d18, d17\n-\tvcmpe.f64\td8, d17\n+\tbmi.w\t11ce <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a2>\n+\tvldr\td7, [r3, #88]\t@ 0x58\n+\tvadd.f64\td7, d7, d5\n+\tvcmpe.f64\td4, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t1228 <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3c0>\n-\tb.w\t120c <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a4>\n+\tble.w\t11ea <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3be>\n+\tb.w\t11ce <__gridxc_vv_vdwxc_MOD_vv_vdw_theta+0x3a2>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop.w\n-\t.word\t0x01000100\n-\t.word\t0x00000016\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000007\n-\t.word\t0x00001000\n-\t.word\t0x00000016\n-\t.word\t0x00000000\n-\t.word\t0x00000016\n-\t.word\t0x00000008\n-\t.word\t0x00000001\n-\t.word\t0x00000001\n-\t.word\t0x00000005\n-\t.word\t0x0000043e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000404\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x000003d4\n- R_ARM_REL32\t.bss\n-\t.word\t0x000003ce\n- R_ARM_REL32\t.rodata\n-\t.word\t0x000003ac\n- R_ARM_REL32\t.bss\n-\t.word\t0x000002f0\n- R_ARM_REL32\t.LC18\n-\t.word\t0x000002da\n- R_ARM_REL32\t.LC19\n-\t.word\t0x0000028a\n- R_ARM_REL32\t.LC20\n-\t.word\t0x000001e4\n- R_ARM_REL32\t.LC21\n-\t.word\t0x000001de\n- R_ARM_REL32\t.bss\n-\t.word\t0x000001b0\n- R_ARM_REL32\t.LC18\n-\t.word\t0x00000194\n- R_ARM_REL32\t.LC20\n-\t.word\t0x000000f2\n- R_ARM_REL32\t.data\n+\tnop\n \n-00001ff0 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut>:\n+0000215c <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut>:\n __gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut():\n \tpush\t{r3, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4088]\t@ 0xff8\n-\tldr\tr2, [pc, #176]\t@ (20b0 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xc0>)\n-\tvldr\td16, [r0]\n+\tldr\tr2, [pc, #180]\t@ (2220 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xc4>)\n+\tvldr\td7, [r0]\n \tadd\tr2, pc\n-\tldr.w\tip, [pc, #172]\t@ 20b4 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xc4>\n+\tldr.w\tip, [pc, #176]\t@ 2224 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xc8>\n \tadd\tip, pc\n-\tvldr\td17, [r2, #384]\t@ 0x180\n-\tvcmp.f64\td16, d17\n+\tvldr\td6, [r2, #376]\t@ 0x178\n+\tvcmp.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t2062 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x72>\n-\tvldr\td17, [pc, #124]\t@ 2098 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xa8>\n+\tbeq.n\t21ce <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x72>\n+\tvldr\td6, [pc, #128]\t@ 2208 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xac>\n \tmovs\tr0, #0\n-\tvstr\td16, [r2, #384]\t@ 0x180\n+\tvstr\td7, [r2, #376]\t@ 0x178\n \tmovs\tr1, #0\n \tmovt\tr1, #16297\t@ 0x3fa9\n \tstrd\tr0, r1, [r2, #104]\t@ 0x68\n-\tvmul.f64\td16, d16, d17\n-\tadd\tr1, pc, #108\t@ (adr r1, 20a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xb0>)\n+\tvmul.f64\td7, d7, d6\n+\tadd\tr1, pc, #112\t@ (adr r1, 2210 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xb4>)\n \tldrd\tr0, r1, [r1]\n-\tstrd\tr0, r1, [r2, #376]\t@ 0x178\n-\tadd\tr1, pc, #104\t@ (adr r1, 20a8 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xb8>)\n-\tldrd\tr0, r1, [r1]\n-\tvcvt.s32.f64\ts15, d16\n \tstrd\tr0, r1, [r2, #368]\t@ 0x170\n-\tvmov\tr3, s15\n+\tadd\tr1, pc, #108\t@ (adr r1, 2218 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xbc>)\n+\tldrd\tr0, r1, [r1]\n+\tvcvt.s32.f64\ts14, d7\n+\tstrd\tr0, r1, [r2, #360]\t@ 0x168\n+\tvmov\tr3, s14\n \tadds\tr3, #1\n-\tstr.w\tr3, [r2, #364]\t@ 0x16c\n+\tstr.w\tr3, [r2, #352]\t@ 0x160\n \tcmp.w\tr3, #2048\t@ 0x800\n-\tbgt.n\t207c <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x8c>\n-\tldr\tr3, [pc, #92]\t@ (20b8 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xc8>)\n+\tbgt.n\t21e8 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x8c>\n+\tldr\tr3, [pc, #96]\t@ (2228 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xcc>)\n \tmovs\tr2, #1\n \tadd\tr3, pc\n \tstr\tr2, [r3, #100]\t@ 0x64\n-\tldr\tr3, [pc, #88]\t@ (20bc <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xcc>)\n+\tldr\tr3, [pc, #92]\t@ (222c <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd0>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #96]\t@ 0x60\n-\tcbz\tr3, 2090 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xa0>\n-\tldr\tr3, [pc, #84]\t@ (20c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd0>)\n+\tcbz\tr3, 21fc <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xa0>\n+\tldr\tr3, [pc, #88]\t@ (2230 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd4>)\n \tadd\tr3, pc\n-\tldr.w\tr3, [r3, #392]\t@ 0x188\n-\tcbnz\tr3, 208e <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x9e>\n+\tldr.w\tr3, [r3, #384]\t@ 0x180\n+\tcbnz\tr3, 21fa <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x9e>\n \tldmia.w\tsp!, {r3, lr}\n-\tb.w\t1fc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>\n-\tldr\tr3, [pc, #68]\t@ (20c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd4>)\n+\tb.w\t1cc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>\n+\tldr\tr3, [pc, #72]\t@ (2234 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd8>)\n \tmovs\tr1, #29\n-\tldr\tr0, [pc, #68]\t@ (20c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xd8>)\n+\tldr\tr0, [pc, #72]\t@ (2238 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0xdc>)\n \tadd\tr0, pc\n \tldr.w\tr3, [ip, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t205a <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x6a>\n+\tb.n\t21c6 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x6a>\n \tpop\t{r3, pc}\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0>\n-\tb.n\t206a <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x7a>\n+\tb.n\t21d6 <__gridxc_vv_vdwxc_MOD_vv_vdw_set_kcut+0x7a>\n \tnop\n+\tnop.w\n \t.word\t0xab8b494c\n \t.word\t0x403fd4bb\n \t.word\t0x9217271a\n \t.word\t0x3fa015bf\n \t.word\t0x9217271a\n \t.word\t0x405015bf\n-\t.word\t0x000000a8\n+\t.word\t0x000000ac\n R_ARM_REL32\t.bss\n-\t.word\t0x000000a6\n+\t.word\t0x000000aa\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000056\n+\t.word\t0x0000005a\n R_ARM_REL32\t.bss\n-\t.word\t0x00000054\n+\t.word\t0x00000058\n R_ARM_REL32\t.bss\n-\t.word\t0x00000050\n+\t.word\t0x00000054\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000042\n+\t.word\t0x00000046\n R_ARM_REL32\t.LC25\n \n-000020cc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi>:\n+0000223c <__gridxc_vv_vdwxc_MOD_vv_vdw_phi>:\n __gridxc_vv_vdwxc_MOD_vv_vdw_phi():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n+\tvpush\t{d8-d10}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3960]\t@ 0xf78\n+\tstr.w\tr0, [ip, #3936]\t@ 0xf60\n \tldr\tr3, [r1, #24]\n \tsub\tsp, #100\t@ 0x64\n-\tldr.w\tr9, [pc, #868]\t@ 2448 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x37c>\n+\tldr.w\tr9, [pc, #872]\t@ 25c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x384>\n \tmov\tr7, r0\n \tadd\tr9, pc\n \tstr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, #0\n-\tbeq.w\t242e <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x362>\n+\tbeq.w\t25a6 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x36a>\n \tnegs\tr3, r3\n \tstr\tr3, [sp, #0]\n \tldrd\tr3, r4, [r1, #28]\n \tldr\tr5, [r2, #24]\n \tsubs\tr4, r4, r3\n \tstr\tr5, [sp, #68]\t@ 0x44\n \tldrd\tr3, r0, [r1, #40]\t@ 0x28\n \tsub.w\tr8, r0, r3\n \tldr\tr3, [r1, #0]\n \tstr\tr3, [sp, #32]\n \tldr\tr3, [r1, #36]\t@ 0x24\n \tstr\tr3, [sp, #44]\t@ 0x2c\n \tcmp\tr5, #0\n-\tbeq.w\t2422 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x356>\n+\tbeq.w\t259a <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x35e>\n \tnegs\tr3, r5\n \tstr\tr3, [sp, #20]\n-\tldr\tr3, [pc, #816]\t@ (244c <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x380>)\n+\tldr\tr3, [pc, #820]\t@ (25c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x388>)\n \tldr\tr1, [r2, #0]\n \tadd\tr3, pc\n \tstr\tr1, [sp, #36]\t@ 0x24\n \tldr\tr1, [r2, #36]\t@ 0x24\n \tldrd\tfp, sl, [r2, #28]\n \tstr\tr1, [sp, #48]\t@ 0x30\n-\tldr.w\tr3, [r3, #392]\t@ 0x188\n+\tldr.w\tr3, [r3, #384]\t@ 0x180\n \tldrd\tr6, r5, [r2, #40]\t@ 0x28\n \tcmp\tr3, #0\n-\tbeq.w\t243a <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x36e>\n-\tmov\tr3, r8\n-\tcmp\tr3, #33\t@ 0x21\n+\tbeq.w\t25b2 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x376>\n+\tcmp\tr4, #33\t@ 0x21\n \tit\tgt\n-\tcmpgt\tr4, #33\t@ 0x21\n-\tbgt.n\t21e6 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x11a>\n-\tldr\tr3, [pc, #780]\t@ (2450 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x384>)\n+\tcmpgt.w\tr8, #33\t@ 0x21\n+\tbgt.n\t235e <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x122>\n+\tldr\tr3, [pc, #784]\t@ (25c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x38c>)\n \tmovs\tr1, #38\t@ 0x26\n-\tldr\tr0, [pc, #780]\t@ (2454 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x388>)\n+\tldr\tr0, [pc, #784]\t@ (25cc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x390>)\n \tadd\tr0, pc\n \tldr.w\tr3, [r9, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #772]\t@ (2458 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x38c>)\n-\tvldr\td21, [r7]\n+\tldr\tr3, [pc, #776]\t@ (25d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x394>)\n+\tvldr\td3, [r7]\n \tadd\tr3, pc\n-\tvldr\td16, [r3, #384]\t@ 0x180\n-\tvcmpe.f64\td21, d16\n+\tvldr\td7, [r3, #376]\t@ 0x178\n+\tvcmpe.f64\td3, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tblt.n\t21fc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x130>\n+\tblt.n\t2374 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x138>\n \tcmp.w\tr8, #0\n-\tblt.n\t21a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xd8>\n+\tblt.n\t2318 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xdc>\n \tcmp\tr4, #0\n-\tblt.n\t21a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xd8>\n+\tblt.n\t2318 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xdc>\n \tldr\tr3, [sp, #64]\t@ 0x40\n \tcmp\tr3, #1\n-\tbne.w\t25fa <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x52e>\n+\tbne.w\t278a <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x54e>\n \tldr\tr3, [sp, #0]\n \tadds\tr4, #1\n \tldr\tr2, [sp, #32]\n \tmov.w\tr9, #0\n \tadds\tr3, #1\n \tlsls\tr4, r4, #3\n \tadd.w\tr3, r2, r3, lsl #3\n@@ -2815,22 +2940,22 @@\n \tmovs\tr1, #0\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tmov\tr3, r0\n \tcmp\tr8, r9\n \tadd\tr3, r7\n \tadd.w\tr9, r9, #1\n-\tbne.n\t218e <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xc2>\n+\tbne.n\t2302 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xc6>\n \tsubs\tr5, r5, r6\n-\tbmi.n\t21e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x114>\n+\tbmi.n\t2354 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x118>\n \tsubs.w\tr0, sl, fp\n-\tbmi.n\t21e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x114>\n+\tbmi.n\t2354 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x118>\n \tldr\tr3, [sp, #68]\t@ 0x44\n \tcmp\tr3, #1\n-\tbne.w\t25be <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x4f2>\n+\tbne.w\t274e <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x512>\n \tldr\tr3, [sp, #48]\t@ 0x30\n \tadds\tr0, #1\n \tldr\tr6, [sp, #20]\n \tmov.w\tr8, #0\n \tlsls\tr4, r0, #3\n \tlsls\tr7, r3, #3\n \tldr\tr3, [sp, #36]\t@ 0x24\n@@ -2840,111 +2965,111 @@\n \tmov\tr2, r4\n \tmovs\tr1, #0\n \tadd\tr6, r7\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tcmp\tr8, r5\n \tadd.w\tr8, r8, #1\n-\tbne.n\t21cc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x100>\n+\tbne.n\t2340 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x104>\n \tadd\tsp, #100\t@ 0x64\n+\tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #628]\t@ (245c <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x390>)\n-\tvldr\td21, [r7]\n+\tldr\tr3, [pc, #628]\t@ (25d4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x398>)\n+\tvldr\td3, [r7]\n \tadd\tr3, pc\n-\tvldr\td16, [r3, #384]\t@ 0x180\n-\tvcmpe.f64\td21, d16\n+\tvldr\td7, [r3, #376]\t@ 0x178\n+\tvcmpe.f64\td3, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbge.n\t2170 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xa4>\n-\tldr\tr2, [pc, #608]\t@ (2460 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x394>)\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [pc, #572]\t@ 2440 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x374>\n-\tvmov.f64\td22, #240\t@ 0xbf800000 -1.0\n+\tbge.n\t22e4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xa8>\n+\tldr\tr2, [pc, #608]\t@ (25d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x39c>)\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvldr\td1, [pc, #572]\t@ 25b8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x37c>\n+\tvmov.f64\td4, #8\t@ 0x40400000 3.0\n \tadd\tr2, pc\n-\tvmov.f64\td23, #8\t@ 0x40400000 3.0\n-\tvmov.f64\td27, d22\n-\tvldr\td16, [r2, #376]\t@ 0x178\n-\tldr.w\tr0, [r2, #304]\t@ 0x130\n-\tstr\tr0, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td26, d18, d16\n-\tvmul.f64\td17, d16, d16\n-\tvmul.f64\td20, d16, d19\n-\tldr.w\tr4, [r2, #200]\t@ 0xc8\n-\tldr.w\tr1, [r2, #328]\t@ 0x148\n-\tldr.w\tr7, [r2, #180]\t@ 0xb4\n-\tvmul.f64\td17, d17, d19\n-\tldr.w\tip, [r2, #224]\t@ 0xe0\n-\tldr.w\tr6, [r2, #308]\t@ 0x134\n-\tldr.w\tlr, [r2, #352]\t@ 0x160\n-\tadd\tr7, ip\n-\tldr.w\tfp, [r2, #212]\t@ 0xd4\n-\tldr.w\tsl, [r2, #340]\t@ 0x154\n-\tadd\tr6, lr\n-\tldr.w\tr3, [r2, #176]\t@ 0xb0\n-\tadd\tr7, fp\n-\tadd\tr6, sl\n+\tvmov.f64\td9, d5\n+\tvldr\td7, [r2, #368]\t@ 0x170\n+\tldr.w\tr1, [r2, #292]\t@ 0x124\n+\tstr\tr1, [sp, #56]\t@ 0x38\n+\tvdiv.f64\td10, d5, d7\n+\tldr.w\tr7, [r2, #316]\t@ 0x13c\n+\tldr.w\tr4, [r2, #196]\t@ 0xc4\n+\tldr.w\tr3, [r2, #172]\t@ 0xac\n+\tldr.w\tr6, [r2, #176]\t@ 0xb0\n+\tldr.w\tip, [r2, #220]\t@ 0xdc\n+\tldr.w\tr8, [r2, #208]\t@ 0xd0\n+\tldr.w\tsl, [r2, #296]\t@ 0x128\n+\tldr.w\tlr, [r2, #340]\t@ 0x154\n+\tldr.w\tr9, [r2, #328]\t@ 0x148\n \tstr\tr3, [sp, #52]\t@ 0x34\n-\tldr.w\tr3, [r2, #196]\t@ 0xc4\n-\tldr.w\tr2, [r2, #324]\t@ 0x144\n-\tvmul.f64\td19, d26, d21\n-\tvcvt.s32.f64\ts15, d19\n-\tvmov\tr5, s15\n-\tadds\tr0, r5, #1\n-\tvmov\ts15, r0\n-\tmul.w\tr0, r5, r4\n-\tvcvt.f64.s32\td19, s15\n-\tmul.w\tr5, r1, r5\n-\tadd.w\tr8, r4, r0\n-\tadd\tr0, r7\n-\tadd.w\tr9, r1, r5\n-\tadd\tr5, r6\n-\tldrd\tr1, r4, [sp, #64]\t@ 0x40\n-\tvfnms.f64\td21, d16, d19\n-\tcmp\tr4, #1\n+\tldr.w\tr3, [r2, #192]\t@ 0xc0\n+\tldr.w\tr2, [r2, #312]\t@ 0x138\n+\tvmul.f64\td6, d10, d3\n+\tvcvt.s32.f64\ts13, d6\n+\tvmov\tr1, s13\n+\tadds\tr0, r1, #1\n+\tvmov\ts12, r0\n+\tmul.w\tr5, r1, r7\n+\tvcvt.f64.s32\td6, s12\n+\tmul.w\tr0, r1, r4\n+\tadd.w\tfp, r7, r5\n+\tldrd\tr7, r1, [sp, #64]\t@ 0x40\n+\tadd\tr4, r0\n+\tvnmls.f64\td3, d6, d7\n+\tvmul.f64\td6, d7, d7\n+\tvmul.f64\td7, d7, d1\n+\tcmp\tr7, #1\n \tit\teq\n \tcmpeq\tr1, #1\n-\tadd.w\tr4, r8, r7\n-\tadd.w\tr1, r9, r6\n-\tvmul.f64\td21, d21, d26\n-\tvsub.f64\td25, d18, d21\n-\tvmul.f64\td16, d21, d21\n-\tvsub.f64\td24, d21, d18\n-\tvmul.f64\td28, d21, d17\n-\tvmul.f64\td19, d25, d25\n-\tvfma.f64\td27, d16, d23\n-\tvsub.f64\td16, d16, d18\n-\tvfma.f64\td22, d19, d23\n-\tvfma.f64\td24, d25, d19\n-\tvmul.f64\td28, d16, d28\n-\tvmul.f64\td27, d27, d20\n-\tvmul.f64\td22, d22, d20\n-\tvmul.f64\td24, d24, d17\n-\tbne.w\t2464 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x398>\n-\tmul.w\tr6, r3, ip\n-\tvneg.f64\td27, d27\n+\tvmul.f64\td6, d6, d1\n+\tvmul.f64\td3, d3, d10\n+\tvsub.f64\td0, d5, d3\n+\tvsub.f64\td1, d3, d5\n+\tvmul.f64\td2, d3, d3\n+\tvmul.f64\td8, d0, d0\n+\tvmla.f64\td1, d0, d8\n+\tvnmls.f64\td9, d8, d4\n+\tvmov.f64\td8, d5\n+\tvnmls.f64\td8, d2, d4\n+\tvsub.f64\td2, d2, d5\n+\tvmul.f64\td1, d1, d6\n+\tvmul.f64\td6, d3, d6\n+\tvmul.f64\td9, d9, d7\n+\tvmul.f64\td2, d2, d6\n+\tvmul.f64\td8, d8, d7\n+\tbne.w\t25dc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x3a0>\n+\tadd.w\tr7, r6, ip\n+\tadd.w\tr1, sl, lr\n+\tadd\tr7, r8\n+\tadd\tr1, r9\n+\tadds\tr6, r4, r7\n+\tadds\tr4, r0, r7\n+\tadd.w\tr0, fp, r1\n+\tadd\tr1, r5\n+\tmul.w\tr5, r3, ip\n \tmul.w\tr4, r3, r4\n-\tstr\tr6, [sp, #68]\t@ 0x44\n-\tmul.w\tr0, r3, r0\n-\tstr\tr4, [sp, #16]\n-\tmul.w\tr6, r2, lr\n-\tstr\tr0, [sp, #12]\n-\tmul.w\tr4, r2, r5\n-\tstr\tr6, [sp, #64]\t@ 0x40\n-\tmul.w\tfp, r3, fp\n-\tmul.w\tsl, r2, sl\n-\tmov\tr7, r4\n-\tmul.w\tr3, r2, r1\n-\tldr\tr2, [sp, #0]\n+\tstr\tr5, [sp, #68]\t@ 0x44\n+\tmul.w\tr5, r2, lr\n+\tstr\tr4, [sp, #12]\n+\tmul.w\tfp, r3, r8\n+\tstr\tr5, [sp, #64]\t@ 0x40\n+\tmul.w\tr4, r2, r1\n \tldr\tr1, [sp, #20]\n+\tmul.w\tr5, r3, r6\n+\tmul.w\tsl, r2, r9\n+\tstr\tr5, [sp, #16]\n+\tmul.w\tr3, r2, r0\n+\tldr\tr2, [sp, #0]\n \tstr\tr3, [sp, #8]\n+\tmov\tr7, r4\n \tadds\tr3, r2, #1\n \tstr\tr2, [sp, #4]\n-\tadds\tr2, r1, #1\n \tstr\tr1, [sp, #0]\n-\tlsls\tr3, r3, #3\n+\tadds\tr2, r1, #1\n \tldr\tr1, [sp, #36]\t@ 0x24\n+\tlsls\tr3, r3, #3\n \tadd.w\tr2, r1, r2, lsl #3\n \tstr\tr2, [sp, #20]\n \tadd.w\tr2, r1, #8\n \tldr\tr1, [sp, #44]\t@ 0x2c\n \tstr\tr2, [sp, #76]\t@ 0x4c\n \tadds\tr2, r1, #1\n \tmov.w\tr9, r1, lsl #3\n@@ -2976,38 +3101,38 @@\n \tsub.w\tlr, r2, r3\n \tldr\tr3, [sp, #8]\n \tstr\tr7, [sp, #40]\t@ 0x28\n \tadd.w\tr6, r1, r0, lsl #3\n \tsub.w\tip, r3, r7\n \tldrd\tr0, r1, [sp, #20]\n \tldrd\tr3, r2, [sp, #32]\n-\tadd.w\tr7, ip, r3\n-\tvldr\td18, [r3]\n-\tadd\tr3, sl\n-\tvldr\td20, [r2]\n-\tvldr\td19, [r7]\n \tadd.w\tr7, lr, r2\n-\tvmul.f64\td16, d28, d18\n+\tvldr\td4, [r2]\n \tadd\tr2, fp\n-\tvfma.f64\td16, d21, d20\n-\tvmul.f64\td17, d22, d19\n-\tvfma.f64\td17, d27, d18\n-\tvldr\td18, [r7]\n-\tvfma.f64\td16, d25, d18\n-\tvsub.f64\td18, d18, d20\n-\tvfma.f64\td16, d24, d19\n-\tvfma.f64\td17, d26, d18\n-\tvstmia\tr4!, {d16}\n+\tvldr\td5, [r3]\n+\tvmul.f64\td7, d3, d4\n+\tvmla.f64\td7, d2, d5\n+\tvmul.f64\td6, d8, d5\n+\tvldr\td5, [r7]\n+\tadd.w\tr7, ip, r3\n+\tadd\tr3, sl\n+\tvmla.f64\td7, d0, d5\n+\tvsub.f64\td5, d5, d4\n+\tvldr\td4, [r7]\n+\tvnmls.f64\td6, d9, d4\n+\tvmla.f64\td7, d1, d4\n+\tvmla.f64\td6, d5, d10\n+\tvstmia\tr4!, {d7}\n \tcmp\tr5, r4\n-\tvstmia\tr6!, {d17}\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd\tr1, r9\n-\tvstr\td17, [r0]\n+\tvstmia\tr6!, {d6}\n+\tvstr\td6, [r0]\n \tadd\tr0, r8\n-\tbne.n\t2384 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x2b8>\n+\tbne.n\t24f8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x2bc>\n \tldr\tr2, [sp, #24]\n \tldr\tr1, [sp, #68]\t@ 0x44\n \tadds\tr2, #8\n \tstr\tr2, [sp, #24]\n \tldr\tr2, [sp, #20]\n \tldr\tr7, [sp, #40]\t@ 0x28\n \tadds\tr2, #8\n@@ -3033,83 +3158,92 @@\n \tldr\tr1, [sp, #48]\t@ 0x30\n \tstr\tr2, [sp, #4]\n \tldr\tr2, [sp, #0]\n \tadd\tr2, r1\n \tstr\tr2, [sp, #0]\n \tldr\tr2, [sp, #60]\t@ 0x3c\n \tadd\tr5, r2\n-\tbne.n\t2350 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x284>\n+\tbne.n\t24c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x288>\n \tadd\tsp, #100\t@ 0x64\n+\tvpop\t{d8-d10}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr\tr3, [sp, #20]\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #68]\t@ 0x44\n-\tb.n\t2118 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x4c>\n+\tb.n\t228c <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x50>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tstr\tr3, [sp, #0]\n \tmovs\tr3, #1\n \tstr\tr3, [sp, #64]\t@ 0x40\n-\tb.n\t20f4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x28>\n-\tbl\t1fc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>\n-\tb.n\t2136 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x6a>\n+\tb.n\t2268 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x2c>\n+\tbl\t1cc <__gridxc_vv_vdwxc_MOD_set_phi_table.part.0>\n+\tb.n\t22aa <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x6e>\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n-\t.word\t0x0000035e\n+\t.word\t0x00000362\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000032c\n+\t.word\t0x00000330\n R_ARM_REL32\t.bss\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000030a\n+\t.word\t0x0000030e\n R_ARM_REL32\t.LC26\n-\t.word\t0x000002fe\n+\t.word\t0x00000302\n R_ARM_REL32\t.bss\n \t.word\t0x0000026c\n R_ARM_REL32\t.bss\n \t.word\t0x00000252\n R_ARM_REL32\t.bss\n+\tadd.w\tr1, r6, ip\n+\tadd.w\tr7, sl, lr\n+\tadd\tr1, r8\n+\tadd\tr7, r9\n+\tadd\tr0, r1\n+\tadd\tr4, r1\n+\tadd\tr5, r7\n+\tadd.w\tr1, fp, r7\n \tldr\tr7, [sp, #20]\n \tmul.w\tr0, r3, r0\n \tstr\tr7, [sp, #12]\n+\tstr\tr0, [sp, #20]\n \tmul.w\tr7, r3, ip\n-\tmul.w\tr1, r2, r1\n+\tmul.w\tr0, r3, r8\n \tstr\tr7, [sp, #72]\t@ 0x48\n-\tstr\tr0, [sp, #20]\n+\tmul.w\tr1, r2, r1\n+\tstr\tr0, [sp, #4]\n \tmul.w\tr7, r2, r5\n-\tmul.w\tr0, r2, lr\n \tldr\tr6, [sp, #0]\n-\tmul.w\tr2, r2, sl\n+\tmul.w\tr0, r2, lr\n+\tstr\tr1, [sp, #24]\n+\tmul.w\tr2, r2, r9\n \tstr\tr0, [sp, #76]\t@ 0x4c\n \tstr\tr2, [sp, #0]\n \tmul.w\tr4, r3, r4\n \tldr\tr2, [sp, #64]\t@ 0x40\n-\tmul.w\tfp, r3, fp\n-\tldr\tr0, [sp, #32]\n \tmov.w\tip, #2\n+\tldr\tr0, [sp, #32]\n \tldr\tr3, [sp, #12]\n \tmov.w\tr9, r2, lsl #3\n \tstr\tr4, [sp, #16]\n \tadd.w\tr4, r9, r0\n \tadd.w\tr0, r0, r6, lsl #3\n \tstr\tr0, [sp, #88]\t@ 0x58\n \tldr\tr0, [sp, #36]\t@ 0x24\n-\tstr\tr1, [sp, #24]\n \tldr\tr1, [sp, #68]\t@ 0x44\n+\tstr\tr4, [sp, #80]\t@ 0x50\n \tadd.w\tr3, r0, r3, lsl #3\n \tstr\tr3, [sp, #92]\t@ 0x5c\n \tldr\tr3, [sp, #44]\t@ 0x2c\n \tmov.w\tsl, r1, lsl #3\n-\tstr\tr4, [sp, #80]\t@ 0x50\n-\tstr\tr6, [sp, #28]\n \tadd.w\tr4, sl, r0\n-\tlsls\tr3, r3, #3\n-\tstr\tr3, [sp, #4]\n-\tldr\tr3, [sp, #48]\t@ 0x30\n+\tstr\tr6, [sp, #28]\n \tstr\tr4, [sp, #84]\t@ 0x54\n+\tmov.w\tfp, r3, lsl #3\n+\tldr\tr3, [sp, #48]\t@ 0x30\n \tstrd\tr2, r1, [sp, #32]\n \tlsls\tr3, r3, #3\n \tstr\tr3, [sp, #8]\n \tldr\tr1, [sp, #56]\t@ 0x38\n \tldr\tr0, [sp, #28]\n \tadd\tr1, r7\n \tstr\tr1, [sp, #40]\t@ 0x28\n@@ -3132,44 +3266,44 @@\n \tldr\tr1, [sp, #92]\t@ 0x5c\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tsub.w\tlr, r3, r7\n \tldr\tr3, [sp, #40]\t@ 0x28\n \tstr\tr7, [sp, #40]\t@ 0x28\n \tadd.w\tr0, r1, r0, lsl #3\n \tmovs\tr1, #1\n-\tadd.w\tr7, lr, r3\n-\tvldr\td18, [r3]\n-\tvldr\td20, [r2]\n+\tvldr\td7, [r3]\n+\tadd.w\tr7, r8, r2\n+\tvldr\td4, [r2]\n \tadds\tr1, #1\n \tcmp\tr1, ip\n-\tvldr\td19, [r7]\n-\tvmul.f64\td16, d18, d28\n+\tvldr\td5, [r7]\n+\tvmul.f64\td6, d7, d2\n+\tldr\tr7, [sp, #4]\n+\tvmla.f64\td6, d4, d3\n+\tvmul.f64\td7, d7, d8\n+\tadd\tr2, r7\n+\tadd.w\tr7, lr, r3\n+\tvmla.f64\td6, d5, d0\n+\tvsub.f64\td5, d5, d4\n+\tvldr\td4, [r7]\n \tldr\tr7, [sp, #0]\n-\tvfma.f64\td16, d20, d21\n+\tvnmls.f64\td7, d4, d9\n+\tvmla.f64\td6, d4, d1\n \tadd\tr3, r7\n-\tadd.w\tr7, r8, r2\n-\tvmul.f64\td17, d19, d22\n-\tadd\tr2, fp\n-\tvfms.f64\td17, d18, d27\n-\tvldr\td18, [r7]\n-\tldr\tr7, [sp, #4]\n-\tvfma.f64\td16, d18, d25\n-\tvsub.f64\td18, d18, d20\n-\tvfma.f64\td16, d19, d24\n-\tvfma.f64\td17, d18, d26\n-\tvstr\td16, [r6]\n-\tadd\tr6, r9\n-\tvstr\td16, [r4]\n-\tadd\tr4, r7\n \tldr\tr7, [sp, #8]\n-\tvstr\td17, [r5]\n+\tvmla.f64\td7, d5, d10\n+\tvstr\td6, [r6]\n+\tadd\tr6, r9\n+\tvstr\td6, [r4]\n+\tadd\tr4, fp\n+\tvstr\td7, [r5]\n \tadd\tr5, sl\n-\tvstr\td17, [r0]\n+\tvstr\td7, [r0]\n \tadd\tr0, r7\n-\tbne.n\t2518 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x44c>\n+\tbne.n\t26a8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x46c>\n \tldr\tr2, [sp, #72]\t@ 0x48\n \tadd.w\tip, ip, #1\n \tldr\tr3, [sp, #16]\n \tcmp.w\tip, #37\t@ 0x25\n \tldr\tr7, [sp, #40]\t@ 0x28\n \tadd\tr3, r2\n \tstr\tr3, [sp, #16]\n@@ -3193,16 +3327,16 @@\n \tldr\tr3, [sp, #32]\n \tadd\tr3, r2\n \tldr\tr2, [sp, #68]\t@ 0x44\n \tstr\tr3, [sp, #32]\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tadd\tr3, r2\n \tstr\tr3, [sp, #36]\t@ 0x24\n-\tbne.n\t24d6 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x40a>\n-\tb.n\t21e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x114>\n+\tbne.n\t2666 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x42a>\n+\tb.n\t2354 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x118>\n \tlsls\tr4, r3, #3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tldr.w\tlr, [sp, #20]\n \tmov.w\tip, #0\n \tadd\tr3, r4\n \tldr.w\tr9, [sp, #48]\t@ 0x30\n \tmov\tr8, r3\n@@ -3210,119 +3344,121 @@\n \tmovs\tr7, #0\n \tadd.w\tr1, r8, lr, lsl #3\n \tmovs\tr2, #0\n \tcmp\tr0, r2\n \tstrd\tr6, r7, [r1]\n \tadd.w\tr2, r2, #1\n \tadd\tr1, r4\n-\tbne.n\t25dc <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x510>\n+\tbne.n\t276c <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x530>\n \tadd\tlr, r9\n \tadd.w\tr3, ip, #1\n \tcmp\tr5, ip\n-\tbeq.w\t21e0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x114>\n+\tbeq.w\t2354 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x118>\n \tmov\tip, r3\n-\tb.n\t25d6 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x50a>\n+\tb.n\t2766 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x52a>\n \tlsls\tr0, r3, #3\n \tldr\tr3, [sp, #32]\n \tldr.w\tip, [sp]\n-\tvmov.i64\td16, #0x0000000000000000\n+\tmovs\tr7, #0\n \tadd\tr3, r0\n \tldr.w\tr9, [sp, #44]\t@ 0x2c\n \tmov\tlr, r3\n-\tmovs\tr7, #0\n+\tvldr\td7, [pc, #40]\t@ 27c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x58c>\n \tadd.w\tr1, lr, ip, lsl #3\n \tmovs\tr2, #0\n \tcmp\tr4, r2\n-\tvstr\td16, [r1]\n+\tvstr\td7, [r1]\n \tadd.w\tr2, r2, #1\n \tadd\tr1, r0\n-\tbne.n\t2616 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x54a>\n+\tbne.n\t27a6 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x56a>\n \tadd\tip, r9\n \tadds\tr3, r7, #1\n \tcmp\tr8, r7\n-\tbeq.w\t21a4 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xd8>\n+\tbeq.w\t2318 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0xdc>\n \tmov\tr7, r3\n-\tb.n\t2610 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x544>\n+\tb.n\t27a0 <__gridxc_vv_vdwxc_MOD_vv_vdw_phi+0x564>\n \tnop\n+\tnop.w\n+\t...\n \n-00002634 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh>:\n+000027d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh>:\n __gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n \tmov\tsl, r1\n \tsub\tsp, #12\n \tmov\tr1, r2\n-\tcbz\tr2, 2666 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x32>\n+\tcbz\tr2, 2802 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x32>\n \tldr\tr1, [r2, #0]\n-\tcbz\tr1, 2666 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x32>\n+\tcbz\tr1, 2802 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x32>\n \tldr\tr6, [r2, #24]\n \trsb\tr9, r6, #0\n-\tcbnz\tr6, 265e <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x2a>\n+\tcbnz\tr6, 27fa <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x2a>\n \tmov.w\tr9, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tldrd\tr2, r5, [r2, #28]\n \tsubs\tr5, r5, r2\n \tadds\tr5, #1\n \tmov\tfp, r3\n-\tcbz\tr3, 2692 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x5e>\n+\tcbz\tr3, 282e <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x5e>\n \tldr.w\tfp, [r3]\n \tcmp.w\tfp, #0\n-\tbeq.n\t2692 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x5e>\n+\tbeq.n\t282e <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x5e>\n \tldr.w\tr8, [r3, #24]\n \trsb\tr7, r8, #0\n \tcmp.w\tr8, #0\n-\tbne.n\t268a <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x56>\n+\tbne.n\t2826 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x56>\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tr8, #1\n \tldrd\tr3, r4, [r3, #28]\n \tsubs\tr4, r4, r3\n \tadds\tr4, #1\n-\tldr\tr3, [pc, #296]\t@ (27bc <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x188>)\n+\tldr\tr3, [pc, #296]\t@ (2958 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x188>)\n \tadd\tr3, pc\n \tldr\tr3, [r3, #96]\t@ 0x60\n \tcmp\tr3, #0\n-\tbeq.n\t2742 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x10e>\n+\tbeq.n\t28de <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x10e>\n \tmovs\tr3, #7\n \tstr\tr3, [r0, #0]\n \tmovs\tr3, #5\n \tstr.w\tr3, [sl]\n-\tcbz\tr1, 26c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x90>\n+\tcbz\tr1, 2860 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x90>\n \tcmp\tr5, #7\n \tit\tlt\n \tmovlt\tr5, #7\n \tcmp\tr6, #1\n-\tbne.n\t2750 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x11c>\n+\tbne.n\t28ec <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x11c>\n \tadd.w\tr0, r9, #1\n \tlsls\tr2, r5, #3\n \tadd.w\tr0, r1, r0, lsl #3\n-\tldr\tr1, [pc, #256]\t@ (27c0 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x18c>)\n+\tldr\tr1, [pc, #256]\t@ (295c <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x18c>)\n \tadd\tr1, pc\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tcmp.w\tfp, #0\n-\tbeq.n\t273c <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x108>\n+\tbeq.n\t28d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x108>\n \tcmp\tr4, #5\n \tit\tlt\n \tmovlt\tr4, #5\n \tcmp.w\tr8, #1\n-\tbne.n\t26ee <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0xba>\n-\tldr\tr1, [pc, #236]\t@ (27c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x190>)\n+\tbne.n\t288a <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0xba>\n+\tldr\tr1, [pc, #236]\t@ (2960 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x190>)\n \tadds\tr0, r7, #1\n \tlsls\tr2, r4, #3\n \tadd\tr1, pc\n \tadd.w\tr0, fp, r0, lsl #3\n \tadds\tr1, #56\t@ 0x38\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tmemcpy\n \tadd\tr7, r8\n-\tldr\tr3, [pc, #212]\t@ (27c8 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x194>)\n+\tldr\tr3, [pc, #212]\t@ (2964 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x194>)\n \tadd.w\tr0, fp, r7, lsl #3\n \tadd\tr3, pc\n \tadd\tr7, r8\n \tadd.w\tr1, r8, r7\n \tadd.w\tr2, r8, r1\n \tadd.w\tr7, fp, r7, lsl #3\n \tldrd\tr4, r5, [r3, #56]\t@ 0x38\n@@ -3340,57 +3476,58 @@\n \tldrd\tr2, r3, [r3, #88]\t@ 0x58\n \tstrd\tr2, r3, [r8]\n \tadd\tsp, #12\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tstrd\tr1, r0, [sp]\n \tbl\t0 <__gridxc_vv_vdwxc_MOD_set_kmesh.part.0>\n \tldrd\tr1, r0, [sp]\n-\tb.n\t269c <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x68>\n-\tldr\tr3, [pc, #120]\t@ (27cc <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x198>)\n+\tb.n\t2838 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x68>\n+\tldr\tr3, [pc, #120]\t@ (2968 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x198>)\n \tadd\tr9, r6\n \tadd.w\tip, r6, r9\n \tadd\tr3, pc\n \tadd.w\tr9, r1, r9, lsl #3\n \tadd.w\tr5, r6, ip\n \tadd.w\tip, r1, ip, lsl #3\n \tadds\tr2, r6, r5\n-\tvldr\td16, [r3]\n+\tvldr\td7, [r3]\n \tadd.w\tr5, r1, r5, lsl #3\n \tadd.w\tlr, r1, r2, lsl #3\n \tadds\tr0, r6, r2\n \tadds\tr2, r6, r0\n-\tvstr\td16, [r9]\n+\tvstr\td7, [r9]\n \tadd\tr6, r2\n-\tvldr\td16, [r3, #8]\n+\tvldr\td7, [r3, #8]\n \tadd.w\tr0, r1, r0, lsl #3\n \tadd.w\tr2, r1, r2, lsl #3\n \tadd.w\tr6, r1, r6, lsl #3\n-\tvstr\td16, [ip]\n-\tvldr\td16, [r3, #16]\n-\tvstr\td16, [r5]\n-\tvldr\td16, [r3, #24]\n-\tvstr\td16, [lr]\n-\tvldr\td16, [r3, #32]\n-\tvstr\td16, [r0]\n+\tvstr\td7, [ip]\n+\tvldr\td7, [r3, #16]\n+\tvstr\td7, [r5]\n+\tvldr\td7, [r3, #24]\n+\tvstr\td7, [lr]\n+\tvldr\td7, [r3, #32]\n+\tvstr\td7, [r0]\n \tldrd\tr0, r1, [r3, #40]\t@ 0x28\n \tstrd\tr0, r1, [r2]\n \tldrd\tr2, r3, [r3, #48]\t@ 0x30\n \tstrd\tr2, r3, [r6]\n-\tb.n\t26c4 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x90>\n+\tb.n\t2860 <__gridxc_vv_vdwxc_MOD_vv_vdw_get_kmesh+0x90>\n \t.word\t0x00000124\n R_ARM_REL32\t.bss\n \t.word\t0x000000fe\n R_ARM_REL32\t.bss\n \t.word\t0x000000e4\n R_ARM_REL32\t.bss\n \t.word\t0x000000ce\n R_ARM_REL32\t.bss\n \t.word\t0x00000070\n R_ARM_REL32\t.bss\n \n-000027d0 <__gridxc_vv_vdwxc_MOD_vv_vdw_beta>:\n+0000296c <__gridxc_vv_vdwxc_MOD_vv_vdw_beta>:\n __gridxc_vv_vdwxc_MOD_vv_vdw_beta():\n-\tvldr\td0, [pc, #4]\t@ 27d8 <__gridxc_vv_vdwxc_MOD_vv_vdw_beta+0x8>\n+\tvldr\td0, [pc, #8]\t@ 2978 <__gridxc_vv_vdwxc_MOD_vv_vdw_beta+0xc>\n \tbx\tlr\n \tnop\n+\tnop.w\n \t.word\t0x40000000\n \t.word\t0x3f745b6c\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "xc_hybrids.F90.o", "source2": "xc_hybrids.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 4448 (bytes into file)\n+ Start of section headers: 4788 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x1160:\n+There are 11 section headers, starting at offset 0x12b4:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 000d80 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 001020 0000e8 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 000db8 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 000db8 000000 00 WA 0 0 1\n- [ 5] .rodata PROGBITS 00000000 000db8 000008 00 A 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 000dc0 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 000dc0 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 000df4 000160 10 9 11 4\n- [ 9] .strtab STRTAB 00000000 000f54 0000cc 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 001108 000058 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 000ed8 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 001174 0000e8 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 000f10 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 000f10 000000 00 WA 0 0 1\n+ [ 5] .rodata PROGBITS 00000000 000f10 000008 00 A 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 000f18 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 000f18 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 000f48 000160 10 9 11 4\n+ [ 9] .strtab STRTAB 00000000 0010a8 0000cc 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 00125c 000058 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,25 +1,25 @@\n \n Symbol table '.symtab' contains 22 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 2: 00000448 0 NOTYPE LOCAL DEFAULT 1 $d\n- 3: 000004bc 0 NOTYPE LOCAL DEFAULT 1 $t\n- 4: 000007c8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 5: 000007e0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 6: 00000bf0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 7: 00000c4c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 8: 00000d70 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 2: 00000430 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 3: 000004a4 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 4: 00000860 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 5: 00000880 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 6: 00000cb0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 7: 00000d0c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 8: 00000ec8 0 NOTYPE LOCAL DEFAULT 1 $d\n 9: 00000000 0 SECTION LOCAL DEFAULT 5 .rodata\n 10: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n- 11: 00000001 2016 FUNC GLOBAL DEFAULT 1 __gridxc_hybrids_MOD_pbe0xc\n+ 11: 00000001 2176 FUNC GLOBAL DEFAULT 1 __gridxc_hybrids_MOD_pbe0xc\n 12: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_pw92c\n 13: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n 14: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n 15: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n 16: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_lda_MOD_exchng\n 17: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n 18: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n 19: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 20: 000007e1 1440 FUNC GLOBAL DEFAULT 1 __gridxc_hybrids_MOD_hsexc\n+ 20: 00000881 1624 FUNC GLOBAL DEFAULT 1 __gridxc_hybrids_MOD_hsexc\n 21: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_xwpbe_MOD_xwpbe\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,32 +1,32 @@\n \n-Relocation section '.rel.text' at offset 0x1020 contains 29 entries:\n+Relocation section '.rel.text' at offset 0x1174 contains 29 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000140 00000c0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n-0000014c 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-000001a8 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-000001bc 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-0000020c 00000e0a R_ARM_THM_CALL 00000000 exp\n-00000274 00000f0a R_ARM_THM_CALL 00000000 log\n-000002ea 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-0000035a 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n-000004b0 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000004b4 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000004b8 00000903 R_ARM_REL32 00000000 .rodata\n-000007c2 0000130a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000007d8 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000007dc 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000008b0 00000c0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n-000008bc 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-00000908 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-0000091c 00000d0a R_ARM_THM_CALL 00000000 cbrt\n-00000978 00000e0a R_ARM_THM_CALL 00000000 exp\n-000009d4 00000f0a R_ARM_THM_CALL 00000000 log\n-00000a12 0000150a R_ARM_THM_CALL 00000000 __gridxc_xwpbe_MOD_xwpbe\n-00000a4a 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n-00000a6e 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n-00000c40 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000c44 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000c48 00000903 R_ARM_REL32 00000000 .rodata\n-00000d66 0000130a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000d78 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d7c 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000162 00000c0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+0000016e 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+000001d6 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+000001e6 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+0000023e 00000e0a R_ARM_THM_CALL 00000000 exp\n+000002ae 00000f0a R_ARM_THM_CALL 00000000 log\n+00000336 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+0000038a 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00000498 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000049c 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000004a0 00000903 R_ARM_REL32 00000000 .rodata\n+0000085c 0000130a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000878 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000087c 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000964 00000c0a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_pw92c\n+00000970 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+000009d8 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+000009e8 00000d0a R_ARM_THM_CALL 00000000 cbrt\n+00000a4c 00000e0a R_ARM_THM_CALL 00000000 exp\n+00000aac 00000f0a R_ARM_THM_CALL 00000000 log\n+00000ae6 0000150a R_ARM_THM_CALL 00000000 __gridxc_xwpbe_MOD_xwpbe\n+00000b24 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00000b46 0000100a R_ARM_THM_CALL 00000000 __gridxc_lda_MOD_exchng\n+00000d00 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000d04 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000d08 00000903 R_ARM_REL32 00000000 .rodata\n+00000ec0 0000130a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000ed0 00001119 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000ed4 0000121a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -6,958 +6,1051 @@\n 00000000 <__gridxc_hybrids_MOD_pbe0xc>:\n __gridxc_hybrids_MOD_pbe0xc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3424]\t@ 0xd60\n-\tldr.w\tr5, [pc, #1176]\t@ 4b0 <__gridxc_hybrids_MOD_pbe0xc+0x4b0>\n+\tldr.w\tr5, [pc, #1152]\t@ 498 <__gridxc_hybrids_MOD_pbe0xc+0x498>\n \tsub.w\tsp, sp, #572\t@ 0x23c\n-\tldr.w\tr4, [pc, #1172]\t@ 4b4 <__gridxc_hybrids_MOD_pbe0xc+0x4b4>\n+\tldr.w\tr4, [pc, #1148]\t@ 49c <__gridxc_hybrids_MOD_pbe0xc+0x49c>\n \tadd\tr5, pc\n-\tldr.w\tr8, [r1]\n+\tldr\tr7, [r1, #0]\n \tldr\tr1, [sp, #672]\t@ 0x2a0\n-\tvldr\td16, [r2]\n-\tcmp.w\tr8, #1\n+\tvldr\td7, [r2]\n+\tcmp\tr7, #1\n \tldr\tr4, [r5, r4]\n \tldr\tr4, [r4, #0]\n \tstr\tr4, [sp, #564]\t@ 0x234\n \tmov.w\tr4, #0\n-\tstr\tr1, [sp, #108]\t@ 0x6c\n+\tstr\tr1, [sp, #140]\t@ 0x8c\n \tldr\tr1, [sp, #676]\t@ 0x2a4\n-\tstr\tr1, [sp, #112]\t@ 0x70\n+\tstr\tr1, [sp, #144]\t@ 0x90\n \tldr\tr1, [sp, #680]\t@ 0x2a8\n \tstr\tr1, [sp, #296]\t@ 0x128\n \tldr\tr1, [sp, #684]\t@ 0x2ac\n \tstr\tr1, [sp, #300]\t@ 0x12c\n \tldr\tr1, [sp, #688]\t@ 0x2b0\n \tstr\tr1, [sp, #304]\t@ 0x130\n \tldr\tr1, [sp, #692]\t@ 0x2b4\n-\tstr\tr0, [sp, #88]\t@ 0x58\n+\tstr\tr0, [sp, #72]\t@ 0x48\n \tstr\tr1, [sp, #308]\t@ 0x134\n-\tbeq.w\t768 <__gridxc_hybrids_MOD_pbe0xc+0x768>\n-\tvldr\td21, [r3, #24]\n-\tvldr\td20, [r3, #8]\n-\tvldr\td18, [r3, #32]\n-\tvldr\td23, [r2, #8]\n-\tvldr\td22, [r3]\n-\tvadd.f64\td24, d18, d20\n-\tvldr\td17, [r3, #16]\n-\tvadd.f64\td10, d23, d16\n-\tvldr\td19, [r3, #40]\t@ 0x28\n-\tvadd.f64\td25, d21, d22\n-\tvldr\td26, [pc, #968]\t@ 448 <__gridxc_hybrids_MOD_pbe0xc+0x448>\n-\tvstr\td21, [sp, #536]\t@ 0x218\n-\tvmov.f64\td21, d17\n-\tvstr\td18, [sp, #544]\t@ 0x220\n-\tvadd.f64\td8, d17, d19\n-\tvstr\td24, [sp, #448]\t@ 0x1c0\n-\tvmaxnm.f64\td10, d10, d26\n-\tvmov.f64\td18, d20\n-\tvmov.f64\td24, d25\n-\tvstr\td16, [sp, #344]\t@ 0x158\n-\tvstr\td23, [sp, #352]\t@ 0x160\n-\tvstr\td22, [sp, #512]\t@ 0x200\n-\tvstr\td25, [sp, #440]\t@ 0x1b8\n-\tvstr\td20, [sp, #520]\t@ 0x208\n-\tvstr\td17, [sp, #528]\t@ 0x210\n-\tvldr\td17, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td18, d18, d18\n-\tvldr\td16, [sp, #544]\t@ 0x220\n-\tadd\tr4, sp, #344\t@ 0x158\n-\tvldr\td22, [sp, #536]\t@ 0x218\n+\tbeq.w\t7f8 <__gridxc_hybrids_MOD_pbe0xc+0x7f8>\n+\tvldr\td1, [r2, #8]\n+\tvldr\td6, [pc, #984]\t@ 430 <__gridxc_hybrids_MOD_pbe0xc+0x430>\n+\tvldr\td5, [r3]\n+\tvadd.f64\td15, d1, d7\n+\tvldr\td2, [r3, #24]\n+\tvldr\td3, [r3, #8]\n+\tvldr\td4, [r3, #32]\n+\tvadd.f64\td0, d2, d5\n+\tvstr\td7, [sp, #344]\t@ 0x158\n+\tvcmpe.f64\td15, d6\n+\tvldr\td7, [r3, #16]\n+\tvstr\td5, [sp, #512]\t@ 0x200\n+\tvldr\td5, [r3, #40]\t@ 0x28\n+\tvstr\td1, [sp, #352]\t@ 0x160\n+\tvadd.f64\td1, d4, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td4, [sp, #544]\t@ 0x220\n+\tvadd.f64\td4, d7, d5\n+\tvstr\td7, [sp, #528]\t@ 0x210\n+\tvmov.f64\td7, d3\n+\tvstr\td0, [sp, #440]\t@ 0x1b8\n+\tvstr\td1, [sp, #448]\t@ 0x1c0\n+\tvstr\td2, [sp, #536]\t@ 0x218\n+\tit\tlt\n+\tvmovlt.f64\td15, d6\n+\tvmov.f64\td1, d4\n+\tvstr\td3, [sp, #520]\t@ 0x208\n+\tvstr\td4, [sp, #104]\t@ 0x68\n+\tvldr\td3, [sp, #448]\t@ 0x1c0\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td4, [sp, #512]\t@ 0x200\n+\tadd.w\tfp, sp, #344\t@ 0x158\n+\tvldr\td2, [sp, #440]\t@ 0x1b8\n \tadd\tr3, sp, #408\t@ 0x198\n-\tvmul.f64\td20, d17, d17\n-\tvldr\td23, [sp, #512]\t@ 0x200\n-\tvfma.f64\td20, d24, d24\n-\tvmul.f64\td16, d16, d16\n-\tvfma.f64\td16, d22, d22\n-\tvstr\td19, [sp, #552]\t@ 0x228\n-\tvfma.f64\td18, d23, d23\n-\tvldr\td15, [pc, #860]\t@ 448 <__gridxc_hybrids_MOD_pbe0xc+0x448>\n-\tldr\tr5, [pc, #968]\t@ (4b8 <__gridxc_hybrids_MOD_pbe0xc+0x4b8>)\n+\tvldr\td6, [sp, #544]\t@ 0x220\n \tadd\tr2, sp, #328\t@ 0x148\n-\tmov\tr1, r4\n-\tvstr\td24, [sp, #176]\t@ 0xb0\n-\tvfma.f64\td16, d19, d19\n+\tvmla.f64\td7, d4, d4\n+\tvstr\td3, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td4, d3, d3\n+\tvldr\td3, [sp, #536]\t@ 0x218\n+\tvmla.f64\td4, d2, d2\n+\tvmul.f64\td6, d6, d6\n+\tvstr\td5, [sp, #552]\t@ 0x228\n+\tmov\tr1, fp\n+\tvmla.f64\td6, d3, d3\n+\tvstr\td2, [sp, #200]\t@ 0xc8\n+\tvldr\td2, [pc, #812]\t@ 430 <__gridxc_hybrids_MOD_pbe0xc+0x430>\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td4, d1, d1\n+\tldr\tr5, [pc, #912]\t@ (4a0 <__gridxc_hybrids_MOD_pbe0xc+0x4a0>)\n+\tvstr\td1, [sp, #456]\t@ 0x1c8\n+\tadd.w\tsl, sp, #392\t@ 0x188\n+\tvmla.f64\td6, d5, d5\n \tadd\tr5, pc\n-\tvfma.f64\td18, d21, d21\n \tmov\tr0, r5\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n-\tadd.w\tsl, sp, #392\t@ 0x188\n-\tvmov.f64\td19, d20\n-\tvstr\td8, [sp, #456]\t@ 0x1c8\n-\tvfma.f64\td19, d8, d8\n-\tadd.w\tfp, sp, #376\t@ 0x178\n-\tadd\tr7, sp, #424\t@ 0x1a8\n-\tadd\tr6, sp, #512\t@ 0x200\n+\tvstr\td2, [sp, #24]\n+\tadd.w\tr8, sp, #376\t@ 0x178\n+\tadd\tr6, sp, #424\t@ 0x1a8\n+\tadd\tr4, sp, #464\t@ 0x1d0\n \tadd.w\tr9, sp, #360\t@ 0x168\n-\tvsqrt.f64\td20, d18\n-\tvsqrt.f64\td18, d16\n-\tvsqrt.f64\td16, d19\n-\tvstr\td20, [sp, #392]\t@ 0x188\n-\tvstr\td18, [sp, #400]\t@ 0x190\n-\tvmaxnm.f64\td11, d16, d15\n-\tvstr\td11, [sp, #192]\t@ 0xc0\n+\tvsqrt.f64\td5, d4\n+\tvsqrt.f64\td4, d6\n+\tvldr\td6, [sp, #528]\t@ 0x210\n+\tvmla.f64\td7, d6, d6\n+\tvsqrt.f64\td6, d7\n+\tvcmpe.f64\td5, d2\n+\tvstr\td4, [sp, #400]\t@ 0x190\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td9, d2\n+\tvmovge.f64\td9, d5\n+\tvstr\td6, [sp, #392]\t@ 0x188\n+\tvstr\td9, [sp, #216]\t@ 0xd8\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td16, [pc, #776]\t@ 450 <__gridxc_hybrids_MOD_pbe0xc+0x450>\n-\tvmul.f64\td0, d10, d16\n+\tvldr\td7, [pc, #720]\t@ 438 <__gridxc_hybrids_MOD_pbe0xc+0x438>\n+\tvmul.f64\td0, d15, d7\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [pc, #768]\t@ 458 <__gridxc_hybrids_MOD_pbe0xc+0x458>\n-\tvdiv.f64\td9, d18, d10\n-\tvldr\td22, [sp, #352]\t@ 0x160\n-\tvldr\td16, [sp, #344]\t@ 0x158\n-\tvmul.f64\td19, d0, d19\n-\tvldr\td21, [pc, #756]\t@ 460 <__gridxc_hybrids_MOD_pbe0xc+0x460>\n-\tvldr\td20, [pc, #760]\t@ 468 <__gridxc_hybrids_MOD_pbe0xc+0x468>\n-\tvsub.f64\td16, d16, d22\n-\tvstr\td0, [sp, #200]\t@ 0xc8\n-\tvstr\td18, [sp, #8]\n-\tvsqrt.f64\td12, d19\n-\tvmul.f64\td16, d16, d9\n-\tvmaxnm.f64\td16, d16, d21\n-\tvstr\td12, [sp, #208]\t@ 0xd0\n-\tvminnm.f64\td16, d16, d20\n-\tvadd.f64\td17, d16, d18\n-\tvsub.f64\td16, d18, d16\n-\tvmov.f64\td0, d17\n-\tvmov.f64\td13, d16\n-\tvstr\td17, [sp, #320]\t@ 0x140\n-\tvstr\td16, [sp, #216]\t@ 0xd8\n+\tvldr\td6, [sp, #352]\t@ 0x160\n+\tvldr\td7, [sp, #344]\t@ 0x158\n+\tvstr\td0, [sp, #224]\t@ 0xe0\n+\tvsub.f64\td7, d7, d6\n+\tvdiv.f64\td6, d8, d15\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tvldr\td6, [pc, #688]\t@ 440 <__gridxc_hybrids_MOD_pbe0xc+0x440>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td7, d6\n+\tvldr\td6, [pc, #676]\t@ 448 <__gridxc_hybrids_MOD_pbe0xc+0x448>\n+\tvcmpe.f64\td7, d6\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td7, d6\n+\tvldr\td6, [pc, #668]\t@ 450 <__gridxc_hybrids_MOD_pbe0xc+0x450>\n+\tvmul.f64\td6, d0, d6\n+\tvsub.f64\td10, d8, d7\n+\tvsqrt.f64\td11, d6\n+\tvadd.f64\td6, d7, d8\n+\tvstr\td10, [sp, #240]\t@ 0xf0\n+\tvmov.f64\td0, d6\n+\tvstr\td6, [sp, #320]\t@ 0x140\n+\tvstr\td11, [sp, #232]\t@ 0xe8\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td16, d0\n-\tvmov.f64\td0, d13\n-\tvmov.f64\td14, d16\n-\tvstr\td16, [sp, #224]\t@ 0xe0\n+\tvmov.f64\td12, d0\n+\tvstr\td0, [sp, #248]\t@ 0xf8\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td22, d0, d0\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td20, d10, d12\n-\tvldr\td13, [sp, #328]\t@ 0x148\n-\tvfma.f64\td22, d14, d14\n-\tvmul.f64\td21, d11, d16\n-\tvldr\td19, [pc, #660]\t@ 470 <__gridxc_hybrids_MOD_pbe0xc+0x470>\n-\tvstr\td0, [sp, #248]\t@ 0xf8\n-\tvstr\td13, [sp, #128]\t@ 0x80\n-\tvmul.f64\td19, d13, d19\n-\tvmul.f64\td16, d22, d16\n-\tvstr\td22, [sp, #120]\t@ 0x78\n-\tvmul.f64\td12, d16, d16\n-\tvmul.f64\td20, d20, d16\n-\tvdiv.f64\td11, d21, d20\n-\tvmul.f64\td12, d12, d16\n-\tvdiv.f64\td16, d19, d12\n-\tvneg.f64\td0, d16\n-\tvstr\td16, [sp, #232]\t@ 0xe8\n+\tvldr\td10, [sp, #328]\t@ 0x148\n+\tvmul.f64\td5, d15, d11\n+\tvldr\td6, [pc, #612]\t@ 458 <__gridxc_hybrids_MOD_pbe0xc+0x458>\n+\tvmul.f64\td7, d12, d12\n+\tvstr\td0, [sp, #272]\t@ 0x110\n+\tvmla.f64\td7, d0, d0\n+\tvstr\td10, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td6, d10, d6\n+\tvmov.f64\td3, d7\n+\tvstr\td7, [sp, #152]\t@ 0x98\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td4, d9, d7\n+\tvmul.f64\td7, d3, d7\n+\tvmul.f64\td9, d7, d7\n+\tvmul.f64\td5, d5, d7\n+\tvdiv.f64\td11, d4, d5\n+\tvmul.f64\td9, d9, d7\n+\tvdiv.f64\td7, d6, d9\n+\tvstr\td11, [sp, #112]\t@ 0x70\n+\tvneg.f64\td0, d7\n+\tvstr\td7, [sp, #256]\t@ 0x100\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td18, [sp, #8]\n-\tvldr\td16, [pc, #608]\t@ 478 <__gridxc_hybrids_MOD_pbe0xc+0x478>\n-\tvmul.f64\td17, d11, d11\n-\tvldr\td19, [pc, #608]\t@ 480 <__gridxc_hybrids_MOD_pbe0xc+0x480>\n-\tvsub.f64\td21, d0, d18\n-\tvstr\td0, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td14, d12, d19\n-\tvmul.f64\td20, d17, d17\n-\tvstr\td17, [sp, #168]\t@ 0xa8\n-\tvmov.f64\td19, d18\n-\tvdiv.f64\td12, d16, d21\n-\tvstr\td21, [sp, #136]\t@ 0x88\n-\tvstr\td20, [sp, #160]\t@ 0xa0\n-\tvstr\td14, [sp, #144]\t@ 0x90\n-\tvfma.f64\td17, d20, d12\n-\tvfma.f64\td19, d12, d17\n-\tvmul.f64\td16, d17, d16\n-\tvstr\td17, [sp, #256]\t@ 0x100\n-\tvdiv.f64\td17, d18, d19\n-\tvmul.f64\td16, d16, d17\n-\tvstr\td17, [sp, #288]\t@ 0x120\n-\tvstr\td16, [sp, #264]\t@ 0x108\n-\tvadd.f64\td16, d16, d18\n-\tvmov.f64\td0, d16\n-\tvstr\td16, [sp, #152]\t@ 0x98\n+\tvsub.f64\td4, d0, d8\n+\tvldr\td7, [pc, #536]\t@ 460 <__gridxc_hybrids_MOD_pbe0xc+0x460>\n+\tvmul.f64\td5, d11, d11\n+\tvldr\td6, [pc, #536]\t@ 468 <__gridxc_hybrids_MOD_pbe0xc+0x468>\n+\tvstr\td0, [sp, #264]\t@ 0x108\n+\tvstr\td4, [sp, #168]\t@ 0xa8\n+\tvdiv.f64\td4, d7, d4\n+\tvmul.f64\td9, d9, d6\n+\tvstr\td5, [sp, #192]\t@ 0xc0\n+\tvmov.f64\td6, d5\n+\tvmul.f64\td5, d5, d5\n+\tvstr\td9, [sp, #176]\t@ 0xb0\n+\tvstr\td5, [sp, #120]\t@ 0x78\n+\tvmla.f64\td6, d5, d4\n+\tvstr\td4, [sp, #16]\n+\tvmov.f64\td5, d6\n+\tvmul.f64\td7, d6, d7\n+\tvstr\td6, [sp, #80]\t@ 0x50\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d4, d5\n+\tvdiv.f64\td6, d8, d6\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #96]\t@ 0x60\n+\tvstr\td7, [sp, #280]\t@ 0x118\n+\tvadd.f64\td7, d7, d8\n+\tvmov.f64\td0, d7\n+\tvstr\td7, [sp, #184]\t@ 0xb8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvmul.f64\td16, d14, d0\n-\tvmov.i64\td22, #0x0000000000000000\n+\tvmul.f64\td7, d9, d0\n \tadds\tr3, r5, #4\n-\tstr.w\tr8, [sp, #116]\t@ 0x74\n-\tadd\tr5, sp, #464\t@ 0x1d0\n-\tmov\tr8, sl\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n-\tvstr\td16, [sp, #272]\t@ 0x110\n-\tvadd.f64\td16, d13, d16\n+\tstr\tr7, [sp, #148]\t@ 0x94\n+\tadd\tr5, sp, #512\t@ 0x200\n+\tmov\tr7, sl\n+\tvldr\td2, [sp, #24]\n+\tvstr\td7, [sp, #88]\t@ 0x58\n+\tvadd.f64\td7, d10, d7\n+\tstr\tr3, [sp, #76]\t@ 0x4c\n \tadd\tr3, sp, #336\t@ 0x150\n-\tstr.w\tr9, [sp, #84]\t@ 0x54\n-\tstr\tr3, [sp, #104]\t@ 0x68\n-\tvstr\td16, [sp, #96]\t@ 0x60\n-\tvldr\td16, [sp, #408]\t@ 0x198\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvldr\td16, [sp, #416]\t@ 0x1a0\n-\tvstr\td16, [sp, #312]\t@ 0x138\n-\tvldmia\tr8!, {d17}\n-\tmov\tsl, fp\n-\tvldmia\tr4!, {d16}\n-\tadds\tr6, #24\n-\tvstr\td22, [sp, #72]\t@ 0x48\n+\tstr.w\tr9, [sp, #68]\t@ 0x44\n+\tstr\tr3, [sp, #136]\t@ 0x88\n+\tvstr\td7, [sp, #128]\t@ 0x80\n+\tvldr\td7, [sp, #408]\t@ 0x198\n+\tvstr\td7, [sp, #288]\t@ 0x120\n+\tvldr\td7, [sp, #416]\t@ 0x1a0\n+\tvstr\td7, [sp, #312]\t@ 0x138\n+\tvldr\td7, [pc, #388]\t@ 470 <__gridxc_hybrids_MOD_pbe0xc+0x470>\n+\tvstr\td7, [sp, #8]\n+\tvldmia\tfp!, {d8}\n+\tmov\tsl, r8\n+\tvldmia\tr7!, {d14}\n \tadds\tr5, #24\n-\tvadd.f64\td17, d17, d17\n-\tvadd.f64\td16, d16, d16\n-\tvmaxnm.f64\td17, d17, d15\n-\tvmaxnm.f64\td16, d16, d15\n-\tvstr\td17, [sp, #24]\n-\tvstr\td17, [sp, #16]\n-\tvldr\td17, [pc, #372]\t@ 450 <__gridxc_hybrids_MOD_pbe0xc+0x450>\n-\tvstmia\tfp!, {d16}\n-\tvstr\td16, [sp, #8]\n-\tvmul.f64\td0, d16, d17\n+\tvldr\td7, [pc, #312]\t@ 438 <__gridxc_hybrids_MOD_pbe0xc+0x438>\n+\tadds\tr4, #24\n+\tvadd.f64\td8, d8, d8\n+\tvstr\td2, [sp, #48]\t@ 0x30\n+\tvadd.f64\td14, d14, d14\n+\tvldr\td10, [pc, #360]\t@ 478 <__gridxc_hybrids_MOD_pbe0xc+0x478>\n+\tvcmpe.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvcmpe.f64\td14, d2\n+\tit\tlt\n+\tvmovlt.f64\td8, d2\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d8, d7\n+\tvstmia\tr8!, {d8}\n+\tit\tlt\n+\tvmovlt.f64\td14, d2\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td17, [sp, #16]\n-\tvldr\td16, [sp, #8]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td19, [pc, #396]\t@ 488 <__gridxc_hybrids_MOD_pbe0xc+0x488>\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td18, d17, d18\n-\tvldr\td24, [pc, #392]\t@ 490 <__gridxc_hybrids_MOD_pbe0xc+0x490>\n-\tvmul.f64\td27, d16, d0\n-\tldr\tr3, [sp, #104]\t@ 0x68\n-\tstr\tr7, [sp, #0]\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td3, d8, d0\n+\tvldr\td6, [pc, #316]\t@ 480 <__gridxc_hybrids_MOD_pbe0xc+0x480>\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td13, d0\n+\tldr\tr3, [sp, #136]\t@ 0x88\n+\tvmul.f64\td7, d14, d7\n+\tstr\tr6, [sp, #0]\n+\tldrd\tr0, r1, [sp, #72]\t@ 0x48\n \tmov\tr2, sl\n-\tldrd\tr0, r1, [sp, #88]\t@ 0x58\n-\tvstr\td17, [sp, #64]\t@ 0x40\n-\tvdiv.f64\td14, d18, d27\n-\tvldr\td18, [pc, #372]\t@ 498 <__gridxc_hybrids_MOD_pbe0xc+0x498>\n-\tvstr\td0, [sp, #56]\t@ 0x38\n-\tadds\tr7, #8\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tvstr\td27, [sp, #40]\t@ 0x28\n-\tvstr\td20, [sp, #24]\n-\tvstr\td18, [sp, #16]\n-\tvmul.f64\td26, d14, d14\n-\tvmul.f64\td26, d26, d19\n-\tvadd.f64\td19, d26, d20\n-\tvstr\td26, [sp, #32]\n-\tvdiv.f64\td13, d20, d19\n-\tvfms.f64\td24, d13, d18\n-\tvmul.f64\td13, d13, d13\n-\tvstr\td24, [sp, #8]\n+\tvstr\td3, [sp, #40]\t@ 0x28\n+\tadds\tr6, #8\n+\tvdiv.f64\td12, d7, d3\n+\tvldr\td7, [pc, #288]\t@ 488 <__gridxc_hybrids_MOD_pbe0xc+0x488>\n+\tvstr\td1, [sp, #32]\n+\tvmul.f64\td11, d12, d12\n+\tvmul.f64\td11, d11, d6\n+\tvadd.f64\td6, d11, d1\n+\tvdiv.f64\td9, d1, d6\n+\tvmls.f64\td7, d9, d10\n+\tvmul.f64\td9, d9, d9\n+\tvstr\td7, [sp, #24]\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td23, [pc, #320]\t@ 4a0 <__gridxc_hybrids_MOD_pbe0xc+0x4a0>\n-\tvldr\td0, [sp, #56]\t@ 0x38\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvldr\td20, [sp, #24]\n-\tvmul.f64\td0, d0, d23\n-\tvldr\td17, [sp, #64]\t@ 0x40\n-\tvldr\td27, [sp, #40]\t@ 0x28\n-\tvldr\td26, [sp, #32]\n-\tvdiv.f64\td19, d20, d17\n-\tvldr\td18, [sp, #16]\n-\tvdiv.f64\td17, d20, d16\n-\tvldr\td24, [sp, #8]\n-\tvldr\td25, [r7, #-8]\n-\tvdiv.f64\td21, d0, d27\n-\tldr\tr3, [sp, #84]\t@ 0x54\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tcmp\tr3, r4\n-\tvadd.f64\td21, d21, d17\n-\tvadd.f64\td17, d14, d14\n-\tvmul.f64\td17, d17, d26\n-\tvnmul.f64\td21, d21, d17\n-\tvdiv.f64\td17, d21, d14\n-\tvldr\td21, [sp, #336]\t@ 0x150\n-\tvmul.f64\td21, d16, d21\n-\tvmul.f64\td18, d21, d18\n-\tvfma.f64\td22, d21, d24\n-\tvmul.f64\td18, d18, d13\n-\tvmul.f64\td16, d17, d18\n-\tvfma.f64\td16, d25, d24\n-\tvstmia\tr9!, {d16}\n-\tvldr\td16, [r6, #-24]\t@ 0xffffffe8\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td18, d16, d21\n-\tvldr\td16, [r6, #-16]\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td17, d16, d21\n-\tvldr\td16, [r6, #-8]\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td19, d19, d14\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvldr\td19, [pc, #148]\t@ 4a8 <__gridxc_hybrids_MOD_pbe0xc+0x4a8>\n-\tvmul.f64\td14, d14, d19\n-\tvmul.f64\td18, d18, d14\n-\tvmul.f64\td17, d17, d14\n-\tvmul.f64\td16, d16, d14\n-\tvmul.f64\td18, d18, d13\n-\tvmul.f64\td17, d17, d13\n-\tvmul.f64\td16, d16, d13\n-\tvstr\td18, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tbne.w\t2b0 <__gridxc_hybrids_MOD_pbe0xc+0x2b0>\n-\tb.n\t4bc <__gridxc_hybrids_MOD_pbe0xc+0x4bc>\n-\tnop.w\n+\tvldr\td4, [pc, #256]\t@ 490 <__gridxc_hybrids_MOD_pbe0xc+0x490>\n+\tvldr\td1, [sp, #32]\n+\tvldr\td3, [sp, #40]\t@ 0x28\n+\tvmul.f64\td13, d13, d4\n+\tvldr\td2, [sp, #24]\n+\tvdiv.f64\td5, d1, d14\n+\tvldr\td6, [r6, #-8]\n+\tldr\tr3, [sp, #68]\t@ 0x44\n+\tvdiv.f64\td7, d13, d3\n+\tvmul.f64\td6, d2, d6\n+\tvdiv.f64\td3, d1, d8\n+\tcmp\tr3, fp\n+\tvadd.f64\td3, d7, d3\n+\tvadd.f64\td7, d12, d12\n+\tvmul.f64\td7, d7, d11\n+\tvnmul.f64\td7, d3, d7\n+\tvdiv.f64\td3, d7, d12\n+\tvldr\td7, [sp, #336]\t@ 0x150\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #8]\n+\tvmul.f64\td10, d8, d10\n+\tvmla.f64\td7, d8, d2\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvmul.f64\td10, d10, d9\n+\tvstr\td7, [sp, #8]\n+\tvldr\td7, [r5, #-16]\n+\tvadd.f64\td7, d7, d7\n+\tvmul.f64\td7, d7, d8\n+\tvmul.f64\td7, d7, d5\n+\tvmla.f64\td6, d3, d10\n+\tvldr\td3, [r5, #-8]\n+\tvadd.f64\td3, d3, d3\n+\tvmul.f64\td3, d3, d8\n+\tvstmia\tr9!, {d6}\n+\tvldr\td6, [r5, #-24]\t@ 0xffffffe8\n+\tvmul.f64\td3, d3, d5\n+\tvadd.f64\td6, d6, d6\n+\tvmul.f64\td6, d6, d8\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td5, d5, d12\n+\tvmul.f64\td6, d6, d5\n+\tb.n\t4a4 <__gridxc_hybrids_MOD_pbe0xc+0x4a4>\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0x6dc9c883\n-\t.word\t0x3ff45f30\n \t.word\t0xffffdcd1\n \t.word\t0xbfefffff\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n+\t.word\t0x6dc9c883\n+\t.word\t0x3ff45f30\n \t.word\t0xeafdf295\n \t.word\t0x404014fc\n \t.word\t0xdd62e0ae\n \t.word\t0x40012b4b\n \t.word\t0xf1fb1946\n \t.word\t0x3f9fd63c\n+\t...\n+\t.word\t0x353f7cee\n+\t.word\t0x3fe9ba5e\n \t.word\t0x8c8d59f4\n \t.word\t0x3fd17954\n \t.word\t0x1a9fbe77\n \t.word\t0x3ffcdd2f\n-\t.word\t0x353f7cee\n-\t.word\t0x3fe9ba5e\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x7576bfc1\n-\t.word\t0x3fdc191d\n-\t.word\t0x0000048c\n+\t.word\t0x00000474\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003b8\n+\t.word\t0x00000380\n R_ARM_REL32\t.rodata\n-\tldrd\tr3, r8, [sp, #112]\t@ 0x70\n-\tvldr\td16, [sp, #96]\t@ 0x60\n-\tcmp.w\tr8, #0\n-\tvstr\td16, [r3]\n-\tvmov.f64\td16, #88\t@ 0x3ec00000 0.375\n-\tldr\tr3, [sp, #108]\t@ 0x6c\n-\tvmul.f64\td16, d9, d16\n-\tvmul.f64\td16, d16, d22\n-\tvstr\td16, [r3]\n-\tble.w\t748 <__gridxc_hybrids_MOD_pbe0xc+0x748>\n-\tvldr\td16, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td18, d10, d8\n-\tvldr\td17, [sp, #208]\t@ 0xd0\n-\tcmp.w\tr8, #1\n-\tvldr\td21, [sp, #144]\t@ 0x90\n-\tvldr\td6, [sp, #128]\t@ 0x80\n-\tvmul.f64\td25, d16, d17\n-\tvldr\td16, [sp, #224]\t@ 0xe0\n-\tvldr\td17, [sp, #232]\t@ 0xe8\n-\tvldr\td5, [sp, #256]\t@ 0x100\n-\tvdiv.f64\td22, d20, d16\n-\tvldr\td16, [sp, #248]\t@ 0xf8\n-\tvldr\td31, [sp, #168]\t@ 0xa8\n-\tvldr\td30, [sp, #264]\t@ 0x108\n-\tvdiv.f64\td16, d20, d16\n-\tvldr\td4, [sp, #272]\t@ 0x110\n-\tvldr\td2, [sp, #160]\t@ 0xa0\n-\tvldr\td3, [sp, #288]\t@ 0x120\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td3, d3, d5\n+\tvldr\td5, [pc, #944]\t@ 860 <__gridxc_hybrids_MOD_pbe0xc+0x860>\n+\tvmul.f64\td5, d12, d5\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td7, d7, d5\n+\tvmul.f64\td5, d3, d5\n+\tvmul.f64\td6, d6, d9\n+\tvmul.f64\td7, d7, d9\n+\tvmul.f64\td5, d5, d9\n+\tvstr\td6, [r4, #-24]\t@ 0xffffffe8\n+\tvstr\td7, [r4, #-16]\n+\tvstr\td5, [r4, #-8]\n+\tbne.w\t2f0 <__gridxc_hybrids_MOD_pbe0xc+0x2f0>\n+\tldrd\tr3, r7, [sp, #144]\t@ 0x90\n+\tvldr\td7, [sp, #128]\t@ 0x80\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tcmp\tr7, #0\n+\tvldr\td6, [sp, #8]\n+\tvstr\td7, [r3]\n+\tvmov.f64\td7, #88\t@ 0x3ec00000 0.375\n+\tldr\tr3, [sp, #140]\t@ 0x8c\n+\tvmul.f64\td7, d0, d7\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td7, [r3]\n+\tble.w\t7d8 <__gridxc_hybrids_MOD_pbe0xc+0x7d8>\n+\tvldr\td7, [sp, #224]\t@ 0xe0\n+\tcmp\tr7, #1\n+\tvldr\td6, [sp, #232]\t@ 0xe8\n+\tvldr\td8, [sp, #16]\n+\tvldr\td5, [sp, #104]\t@ 0x68\n+\tvmul.f64\td3, d7, d6\n+\tvldr\td7, [sp, #248]\t@ 0xf8\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tvmul.f64\td5, d15, d5\n+\tvldr\td14, [sp, #152]\t@ 0x98\n+\tvdiv.f64\td7, d1, d7\n+\tvldr\td11, [sp, #280]\t@ 0x118\n+\tvdiv.f64\td6, d1, d6\n+\tvsub.f64\td7, d7, d6\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvmul.f64\td9, d7, d4\n+\tvldr\td7, [sp, #264]\t@ 0x108\n+\tvmul.f64\td7, d7, d8\n+\tvstr\td9, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tvdiv.f64\td7, d7, d6\n+\tvldr\td6, [sp, #240]\t@ 0xf0\n+\tvstr\td7, [sp, #24]\n+\tvmul.f64\td7, d6, d0\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvdiv.f64\td4, d1, d6\n+\tvldr\td6, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td7, d7, d9\n+\tvldr\td9, [sp, #112]\t@ 0x70\n+\tvdiv.f64\td13, d1, d6\n+\tvldr\td6, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td2, d15, d6\n+\tvldr\td6, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td6, d15, d6\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td4, d4, d9\n+\tvldr\td9, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td2, d2, d9\n+\tvmul.f64\td6, d6, d9\n+\tvmul.f64\td5, d5, d9\n+\tvmul.f64\td12, d9, d11\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d4\n+\tvldr\td4, [pc, #676]\t@ 868 <__gridxc_hybrids_MOD_pbe0xc+0x868>\n+\tvmul.f64\td12, d12, d13\n+\tvmul.f64\td4, d3, d4\n+\tvmul.f64\td4, d4, d0\n+\tvdiv.f64\td10, d4, d3\n+\tvmov.f64\td4, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td14, d4, d14\n+\tvadd.f64\td10, d10, d0\n+\tvldr\td0, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td3, d0, d15\n+\tvdiv.f64\td3, d1, d3\n+\tvstr\td3, [sp, #8]\n+\tvldr\td3, [sp, #80]\t@ 0x50\n+\tvdiv.f64\td9, d1, d3\n+\tvmov.f64\td3, #16\t@ 0x40800000 4.0\n+\tvldr\td1, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td3, d8, d3\n+\tvmla.f64\td4, d3, d1\n+\tvldr\td3, [sp, #112]\t@ 0x70\n+\tvmov.f64\td1, d0\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td2, d2, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td3, d4, d3\n+\tvmul.f64\td4, d2, d11\n+\tvmul.f64\td6, d6, d11\n+\tvmul.f64\td5, d5, d11\n+\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n+\tvstr\td3, [sp, #32]\n+\tvmul.f64\td3, d14, d11\n+\tvldr\td2, [sp, #88]\t@ 0x58\n+\tvstr\td4, [sp, #40]\t@ 0x28\n+\tvldr\td4, [sp, #288]\t@ 0x120\n+\tvmul.f64\td11, d2, d11\n+\tvsub.f64\td8, d4, d0\n+\tvmul.f64\td0, d14, d7\n+\tvmul.f64\td7, d3, d7\n+\tvadd.f64\td4, d2, d4\n+\tvldr\td2, [sp, #8]\n+\tvnmls.f64\td7, d8, d2\n+\tvldr\td8, [sp, #24]\n+\tvldr\td2, [sp, #32]\n+\tvmul.f64\td7, d7, d8\n+\tvadd.f64\td8, d10, d0\n+\tvmul.f64\td8, d8, d2\n+\tvldr\td2, [sp, #120]\t@ 0x78\n \tldr\tr1, [sp, #300]\t@ 0x12c\n-\tldr\tr3, [sp, #308]\t@ 0x134\n-\tvsub.f64\td22, d22, d16\n-\tvldr\td16, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td16, d16, d12\n-\tvmul.f64\td22, d22, d23\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [sp, #136]\t@ 0x88\n-\tvdiv.f64\td28, d16, d17\n-\tvldr\td16, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td19, d16, d9\n-\tvldr\td16, [sp, #192]\t@ 0xc0\n-\tvdiv.f64\td23, d20, d16\n-\tvldr\td16, [sp, #152]\t@ 0x98\n-\tvmul.f64\td19, d19, d22\n-\tvdiv.f64\td26, d20, d16\n-\tvldr\td16, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td17, d10, d16\n-\tvldr\td16, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td16, d10, d16\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td18, d18, d23\n-\tvmul.f64\td23, d23, d11\n-\tvmul.f64\td17, d17, d21\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td18, d18, d21\n-\tvmul.f64\td21, d21, d30\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td18, d18, d23\n-\tvldr\td23, [pc, #548]\t@ 7c8 <__gridxc_hybrids_MOD_pbe0xc+0x7c8>\n-\tvmul.f64\td21, d21, d26\n-\tvmul.f64\td23, d25, d23\n-\tvmul.f64\td23, d23, d9\n-\tvdiv.f64\td24, d23, d25\n-\tvldr\td23, [sp, #120]\t@ 0x78\n-\tvmov.f64\td25, #0\t@ 0x40000000 2.0\n-\tvdiv.f64\td27, d25, d23\n-\tvmul.f64\td23, d6, d10\n-\tvdiv.f64\td29, d20, d23\n-\tvdiv.f64\td23, d20, d5\n-\tvmov.f64\td20, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td20, d12, d20\n-\tvfma.f64\td25, d20, d31\n-\tvmul.f64\td25, d25, d11\n-\tvmul.f64\td17, d17, d25\n-\tvmul.f64\td16, d16, d25\n-\tvmul.f64\td18, d18, d25\n-\tvmul.f64\td11, d25, d11\n-\tvmov.f64\td25, #8\t@ 0x40400000 3.0\n-\tvadd.f64\td24, d24, d9\n-\tvmul.f64\td17, d17, d30\n-\tvmul.f64\td16, d16, d30\n-\tvmul.f64\td18, d18, d30\n-\tvldr\td30, [sp, #280]\t@ 0x118\n-\tvsub.f64\td20, d30, d6\n-\tvadd.f64\td31, d4, d30\n-\tvmul.f64\td30, d27, d25\n-\tvmul.f64\td25, d4, d25\n-\tvmul.f64\td20, d20, d29\n-\tvfms.f64\td20, d30, d19\n-\tvmul.f64\td19, d27, d19\n-\tvadd.f64\td7, d24, d19\n-\tvmul.f64\td19, d25, d19\n-\tvmul.f64\td20, d28, d20\n-\tvnmul.f64\td7, d11, d7\n-\tvfma.f64\td7, d2, d20\n-\tvmul.f64\td20, d5, d20\n-\tvfma.f64\td20, d12, d7\n-\tvmul.f64\td7, d23, d7\n-\tvfms.f64\td7, d20, d3\n-\tvmov.f64\td20, #104\t@ 0x3f400000 0.750\n-\tvfma.f64\td19, d21, d7\n-\tvldr\td7, [sp, #480]\t@ 0x1e0\n-\tvmul.f64\td7, d7, d20\n-\tvfma.f64\td31, d10, d19\n-\tvmov.f64\td19, d23\n-\tvfms.f64\td19, d12, d3\n-\tvstr\td31, [r1]\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td19, d18, d19\n-\tvldr\td31, [sp, #472]\t@ 0x1d8\n-\tvldr\td18, [sp, #360]\t@ 0x168\n-\tvmul.f64\td17, d17, d26\n-\tvmul.f64\td16, d16, d26\n-\tvmul.f64\td19, d19, d26\n-\tvldr\td26, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td31, d31, d20\n-\tvmul.f64\td26, d26, d20\n-\tvstr\td17, [r3]\n-\tvstr\td16, [r3, #8]\n-\tvstr\td19, [r3, #16]\n \tldr\tr0, [sp, #296]\t@ 0x128\n+\tldr\tr3, [sp, #308]\t@ 0x134\n+\tvnmls.f64\td8, d2, d7\n+\tvldr\td2, [sp, #80]\t@ 0x50\n \tldr\tr2, [sp, #304]\t@ 0x130\n-\tvstr\td18, [r0]\n-\tvstr\td26, [r2]\n-\tvstr\td31, [r2, #8]\n+\tvmul.f64\td7, d2, d7\n+\tvldr\td2, [sp, #16]\n+\tvmla.f64\td7, d2, d8\n+\tvldr\td2, [sp, #96]\t@ 0x60\n+\tvmul.f64\td7, d7, d2\n+\tvnmls.f64\td7, d9, d8\n+\tvldr\td8, [sp, #16]\n+\tvmul.f64\td7, d7, d12\n+\tvmla.f64\td7, d11, d0\n+\tvldr\td0, [sp, #464]\t@ 0x1d0\n+\tvmla.f64\td4, d7, d15\n+\tvmov.f64\td7, d9\n+\tvmls.f64\td7, d8, d2\n+\tvldr\td8, [sp, #472]\t@ 0x1d8\n+\tvstr\td4, [r1]\n+\tvldr\td4, [sp, #40]\t@ 0x28\n+\tvmul.f64\td6, d6, d7\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td2, d4, d7\n+\tvldr\td7, [sp, #360]\t@ 0x168\n+\tvmov.f64\td4, #104\t@ 0x3f400000 0.750\n+\tvmul.f64\td6, d6, d13\n+\tvmul.f64\td5, d5, d13\n+\tvmul.f64\td7, d7, d4\n+\tvmul.f64\td0, d0, d4\n+\tvmul.f64\td2, d2, d13\n+\tvldr\td13, [sp, #480]\t@ 0x1e0\n+\tvmul.f64\td8, d8, d4\n+\tvstr\td6, [r3, #8]\n+\tvstr\td5, [r3, #16]\n+\tvstr\td7, [r0]\n+\tvmul.f64\td7, d13, d4\n+\tvstr\td2, [r3]\n+\tvstr\td0, [r2]\n+\tvstr\td8, [r2, #8]\n \tvstr\td7, [r2, #16]\n-\tbeq.n\t748 <__gridxc_hybrids_MOD_pbe0xc+0x748>\n-\tvldr\td18, [sp, #320]\t@ 0x140\n-\tvldr\td26, [sp, #312]\t@ 0x138\n-\tvldr\td31, [sp, #368]\t@ 0x170\n-\tvnmul.f64\td9, d9, d18\n-\tvldr\td7, [sp, #488]\t@ 0x1e8\n-\tvsub.f64\td18, d26, d6\n-\tvadd.f64\td26, d26, d4\n-\tvstr\td17, [r3, #24]\n-\tvmul.f64\td31, d31, d20\n-\tvldr\td17, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td7, d7, d20\n-\tvmul.f64\td9, d9, d22\n-\tvldr\td22, [sp, #504]\t@ 0x1f8\n-\tvmul.f64\td18, d18, d29\n-\tvstr\td16, [r3, #32]\n-\tvmul.f64\td17, d17, d20\n-\tvstr\td19, [r3, #40]\t@ 0x28\n-\tvmul.f64\td22, d22, d20\n-\tvstr\td31, [r0, #8]\n-\tvfms.f64\td18, d9, d30\n-\tvfma.f64\td24, d9, d27\n-\tvmul.f64\td9, d9, d25\n-\tvstr\td7, [r2, #24]\n-\tvstr\td17, [r2, #32]\n-\tvstr\td22, [r2, #40]\t@ 0x28\n-\tvmul.f64\td9, d9, d27\n-\tvmul.f64\td18, d18, d28\n-\tvnmul.f64\td11, d11, d24\n-\tvfma.f64\td11, d2, d18\n-\tvmul.f64\td14, d5, d18\n-\tvfma.f64\td14, d12, d11\n-\tvmul.f64\td23, d23, d11\n-\tvfms.f64\td23, d14, d3\n-\tvfma.f64\td9, d23, d21\n-\tvfma.f64\td26, d10, d9\n-\tvstr\td26, [r1, #8]\n-\tldr\tr2, [pc, #140]\t@ (7d8 <__gridxc_hybrids_MOD_pbe0xc+0x7d8>)\n-\tldr\tr3, [pc, #144]\t@ (7dc <__gridxc_hybrids_MOD_pbe0xc+0x7dc>)\n+\tbeq.n\t7d8 <__gridxc_hybrids_MOD_pbe0xc+0x7d8>\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td7, [sp, #320]\t@ 0x140\n+\tvstr\td6, [r3, #32]\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvnmul.f64\td7, d0, d7\n+\tvldr\td13, [sp, #312]\t@ 0x138\n+\tvldr\td0, [sp, #8]\n+\tvldr\td8, [sp, #16]\n+\tvstr\td2, [r3, #24]\n+\tvmul.f64\td7, d7, d6\n+\tvsub.f64\td6, d13, d1\n+\tvldr\td1, [sp, #80]\t@ 0x50\n+\tvstr\td5, [r3, #40]\t@ 0x28\n+\tvldr\td5, [sp, #88]\t@ 0x58\n+\tvmul.f64\td3, d7, d3\n+\tvmla.f64\td10, d7, d14\n+\tvmul.f64\td7, d7, d11\n+\tvadd.f64\td5, d13, d5\n+\tvnmls.f64\td3, d6, d0\n+\tvldr\td6, [sp, #24]\n+\tvldr\td0, [sp, #120]\t@ 0x78\n+\tvmul.f64\td3, d3, d6\n+\tvldr\td6, [sp, #32]\n+\tvmul.f64\td6, d10, d6\n+\tvnmls.f64\td6, d0, d3\n+\tvmul.f64\td2, d8, d6\n+\tvmla.f64\td2, d1, d3\n+\tvldr\td3, [sp, #96]\t@ 0x60\n+\tvmul.f64\td3, d2, d3\n+\tvnmls.f64\td3, d9, d6\n+\tvldr\td6, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td6, d6, d4\n+\tvstr\td6, [r2, #24]\n+\tvmul.f64\td3, d3, d12\n+\tvldr\td6, [sp, #496]\t@ 0x1f0\n+\tvmla.f64\td3, d7, d14\n+\tvldr\td7, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td6, [r2, #32]\n+\tvstr\td7, [r2, #40]\t@ 0x28\n+\tvmla.f64\td5, d3, d15\n+\tvldr\td7, [sp, #368]\t@ 0x170\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td7, [r0, #8]\n+\tvstr\td5, [r1, #8]\n+\tldr\tr2, [pc, #156]\t@ (878 <__gridxc_hybrids_MOD_pbe0xc+0x878>)\n+\tldr\tr3, [pc, #160]\t@ (87c <__gridxc_hybrids_MOD_pbe0xc+0x87c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #564]\t@ 0x234\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t7c2 <__gridxc_hybrids_MOD_pbe0xc+0x7c2>\n+\tbne.n\t85c <__gridxc_hybrids_MOD_pbe0xc+0x85c>\n \tadd.w\tsp, sp, #572\t@ 0x23c\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvldr\td22, [r3]\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n-\tvldr\td21, [r3, #8]\n-\tvldr\td8, [r3, #16]\n-\tvmul.f64\td20, d16, d19\n-\tvmul.f64\td18, d22, d19\n-\tvldr\td10, [pc, #76]\t@ 7d0 <__gridxc_hybrids_MOD_pbe0xc+0x7d0>\n-\tvmul.f64\td17, d21, d19\n-\tvstr\td21, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td19, d8, d19\n-\tvmov.f64\td24, d22\n-\tvmaxnm.f64\td10, d16, d10\n-\tvstr\td22, [sp, #440]\t@ 0x1b8\n-\tvstr\td18, [sp, #512]\t@ 0x200\n-\tvstr\td18, [sp, #536]\t@ 0x218\n-\tvmov.f64\td18, d17\n-\tvmov.f64\td21, d19\n-\tvstr\td20, [sp, #344]\t@ 0x158\n-\tvstr\td20, [sp, #352]\t@ 0x160\n-\tvstr\td17, [sp, #520]\t@ 0x208\n-\tvstr\td17, [sp, #544]\t@ 0x220\n-\tvstr\td19, [sp, #528]\t@ 0x210\n-\tb.n\tba <__gridxc_hybrids_MOD_pbe0xc+0xba>\n+\tvldr\td15, [pc, #116]\t@ 870 <__gridxc_hybrids_MOD_pbe0xc+0x870>\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td3, [r3, #16]\n+\tvldr\td4, [r3]\n+\tvmul.f64\td2, d7, d5\n+\tvcmpe.f64\td7, d15\n+\tvldr\td6, [r3, #8]\n+\tvmov.f64\td1, d3\n+\tvstr\td3, [sp, #104]\t@ 0x68\n+\tvstr\td4, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td4, d4, d5\n+\tvstr\td6, [sp, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d6, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td5, d3, d5\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvstr\td2, [sp, #352]\t@ 0x160\n+\tvstr\td4, [sp, #512]\t@ 0x200\n+\tvstr\td4, [sp, #536]\t@ 0x218\n+\tit\tge\n+\tvmovge.f64\td15, d7\n+\tvstr\td6, [sp, #520]\t@ 0x208\n+\tvmov.f64\td7, d6\n+\tvstr\td6, [sp, #544]\t@ 0x220\n+\tvstr\td5, [sp, #528]\t@ 0x210\n+\tb.n\tc0 <__gridxc_hybrids_MOD_pbe0xc+0xc0>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\t.word\t0x7576bfc1\n+\t.word\t0x3fdc191d\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x00000088\n+\t.word\t0x00000098\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-000007e0 <__gridxc_hybrids_MOD_hsexc>:\n+00000880 <__gridxc_hybrids_MOD_hsexc>:\n __gridxc_hybrids_MOD_hsexc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3592]\t@ 0xe08\n \tmov\tr6, r2\n-\tldr.w\tr2, [pc, #1096]\t@ c40 <__gridxc_hybrids_MOD_hsexc+0x460>\n+\tldr.w\tr2, [pc, #1128]\t@ d00 <__gridxc_hybrids_MOD_hsexc+0x480>\n \tmov\tr4, r3\n-\tldr.w\tr3, [pc, #1092]\t@ c44 <__gridxc_hybrids_MOD_hsexc+0x464>\n+\tldr.w\tr3, [pc, #1124]\t@ d04 <__gridxc_hybrids_MOD_hsexc+0x484>\n \tadd\tr2, pc\n \tsub\tsp, #404\t@ 0x194\n \tldr.w\tfp, [r1]\n \tmov\tr8, r1\n \tmov\tr7, r0\n-\tvldr\td16, [r6]\n+\tvldr\td3, [r6]\n \tldr\tr3, [r2, r3]\n \tcmp.w\tfp, #1\n \tldrd\tr9, sl, [sp, #520]\t@ 0x208\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #396]\t@ 0x18c\n \tmov.w\tr3, #0\n \tldr\tr3, [sp, #504]\t@ 0x1f8\n-\tstr\tr3, [sp, #8]\n+\tstr\tr3, [sp, #88]\t@ 0x58\n \tldr\tr3, [sp, #508]\t@ 0x1fc\n-\tstr\tr3, [sp, #12]\n+\tstr\tr3, [sp, #100]\t@ 0x64\n \tldr\tr3, [sp, #512]\t@ 0x200\n-\tstr\tr3, [sp, #88]\t@ 0x58\n+\tstr\tr3, [sp, #192]\t@ 0xc0\n \tldr\tr3, [sp, #516]\t@ 0x204\n-\tvldr\td21, [r4]\n-\tstr\tr3, [sp, #92]\t@ 0x5c\n-\tbeq.w\td44 <__gridxc_hybrids_MOD_hsexc+0x564>\n-\tvldr\td17, [r6, #8]\n-\tvldr\td18, [pc, #944]\t@ bf0 <__gridxc_hybrids_MOD_hsexc+0x410>\n-\tvldr\td24, [r4, #24]\n-\tvadd.f64\td9, d17, d16\n-\tvldr\td23, [r4, #32]\n-\tvldr\td25, [r4, #8]\n-\tvldr\td20, [r4, #16]\n-\tvadd.f64\td21, d21, d24\n-\tvldr\td26, [r4, #40]\t@ 0x28\n-\tvadd.f64\td25, d23, d25\n-\tvmaxnm.f64\td9, d9, d18\n-\tvstr\td16, [sp, #264]\t@ 0x108\n-\tvadd.f64\td26, d20, d26\n-\tvstr\td17, [sp, #272]\t@ 0x110\n-\tvmul.f64\td16, d25, d25\n-\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n-\tvfma.f64\td16, d21, d21\n-\tldr\tr5, [pc, #968]\t@ (c48 <__gridxc_hybrids_MOD_hsexc+0x468>)\n-\tvdiv.f64\td8, d13, d9\n-\tvldr\td18, [pc, #872]\t@ bf0 <__gridxc_hybrids_MOD_hsexc+0x410>\n-\tadd\tr5, pc\n+\tvldr\td12, [r4]\n+\tstr\tr3, [sp, #196]\t@ 0xc4\n+\tbeq.w\te88 <__gridxc_hybrids_MOD_hsexc+0x608>\n+\tvldr\td1, [r6, #8]\n+\tvldr\td2, [pc, #976]\t@ cb0 <__gridxc_hybrids_MOD_hsexc+0x430>\n+\tvldr\td6, [r4, #32]\n+\tvadd.f64\td10, d1, d3\n+\tvldr\td7, [r4, #8]\n+\tvldr\td5, [r4, #24]\n+\tvldr\td4, [r4, #16]\n+\tvadd.f64\td7, d6, d7\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvcmpe.f64\td10, d2\n+\tvadd.f64\td12, d12, d5\n+\tvldr\td5, [r4, #40]\t@ 0x28\n+\tvstr\td1, [sp, #272]\t@ 0x110\n+\tvstr\td7, [sp, #64]\t@ 0x40\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvadd.f64\td7, d4, d5\n+\tvmov.f64\td5, d7\n+\tvstr\td7, [sp, #56]\t@ 0x38\n+\tit\tlt\n+\tvmovlt.f64\td10, d2\n+\tvldr\td7, [sp, #64]\t@ 0x40\n \tadd\tr3, sp, #312\t@ 0x138\n-\tmov\tr0, r5\n+\tvldr\td14, [pc, #896]\t@ cb0 <__gridxc_hybrids_MOD_hsexc+0x430>\n \tadd\tr2, sp, #240\t@ 0xf0\n-\tvfma.f64\td16, d26, d26\n+\tldr\tr5, [pc, #976]\t@ (d08 <__gridxc_hybrids_MOD_hsexc+0x488>)\n \tadd\tr1, sp, #264\t@ 0x108\n-\tvstr\td25, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td6, d7, d7\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td6, d12, d12\n+\tadd\tr5, pc\n+\tmov\tr0, r5\n \tadds\tr5, #4\n-\tvstr\td21, [sp, #208]\t@ 0xd0\n-\tvstr\td26, [sp, #200]\t@ 0xc8\n-\tvstr\td18, [sp, #48]\t@ 0x30\n-\tvsqrt.f64\td17, d16\n-\tvmaxnm.f64\td10, d17, d18\n+\tvmla.f64\td6, d5, d5\n+\tvsqrt.f64\td5, d6\n+\tvcmpe.f64\td5, d14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tite\tlt\n+\tvmovlt.f64\td9, d14\n+\tvmovge.f64\td9, d5\n \tbl\t0 <__gridxc_lda_MOD_pw92c>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_pw92c\n-\tvldr\td0, [pc, #832]\t@ bf8 <__gridxc_hybrids_MOD_hsexc+0x418>\n-\tvmul.f64\td0, d9, d0\n+\tvldr\td0, [pc, #844]\t@ cb8 <__gridxc_hybrids_MOD_hsexc+0x438>\n+\tvmul.f64\td0, d10, d0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #264]\t@ 0x108\n-\tvldr\td19, [sp, #272]\t@ 0x110\n-\tvldr\td23, [pc, #820]\t@ c00 <__gridxc_hybrids_MOD_hsexc+0x420>\n-\tvldr\td22, [pc, #824]\t@ c08 <__gridxc_hybrids_MOD_hsexc+0x428>\n-\tvsub.f64\td17, d16, d19\n-\tvldr\td20, [pc, #824]\t@ c10 <__gridxc_hybrids_MOD_hsexc+0x430>\n-\tvstr\td0, [sp, #192]\t@ 0xc0\n-\tvstr\td16, [sp, #24]\n-\tvmul.f64\td20, d0, d20\n-\tvstr\td19, [sp, #40]\t@ 0x28\n-\tvmul.f64\td17, d17, d8\n-\tvsqrt.f64\td12, d20\n-\tvmaxnm.f64\td17, d17, d23\n-\tvminnm.f64\td17, d17, d22\n-\tvadd.f64\td1, d17, d13\n-\tvsub.f64\td11, d13, d17\n-\tvmov.f64\td0, d1\n-\tvstr\td1, [sp, #232]\t@ 0xe8\n+\tvldr\td6, [pc, #840]\t@ cc0 <__gridxc_hybrids_MOD_hsexc+0x440>\n+\tvdiv.f64\td7, d8, d10\n+\tvldr\td15, [sp, #272]\t@ 0x110\n+\tvldr\td3, [pc, #836]\t@ cc8 <__gridxc_hybrids_MOD_hsexc+0x448>\n+\tvmul.f64\td6, d0, d6\n+\tvldr\td4, [pc, #836]\t@ cd0 <__gridxc_hybrids_MOD_hsexc+0x450>\n+\tvstr\td0, [sp, #216]\t@ 0xd8\n+\tvsqrt.f64\td11, d6\n+\tvldr\td6, [sp, #264]\t@ 0x108\n+\tvsub.f64\td5, d6, d15\n+\tvstr\td6, [sp, #104]\t@ 0x68\n+\tvadd.f64\td15, d15, d15\n+\tvmul.f64\td5, d5, d7\n+\tvstr\td7, [sp, #16]\n+\tvcmpe.f64\td5, d3\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td5, d3\n+\tvcmpe.f64\td5, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\thi\n+\tvmovhi.f64\td5, d4\n+\tvadd.f64\td6, d5, d8\n+\tvsub.f64\td13, d8, d5\n+\tvmov.f64\td0, d6\n+\tvstr\td6, [sp, #232]\t@ 0xe8\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td17, d0\n-\tvmov.f64\td0, d11\n-\tvstr\td11, [sp, #72]\t@ 0x48\n-\tvmov.f64\td14, d17\n+\tvstr\td0, [sp, #48]\t@ 0x30\n+\tvmov.f64\td0, d13\n+\tvstr\td13, [sp, #152]\t@ 0x98\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td30, d0, d0\n-\tvmov.f64\td28, #96\t@ 0x3f000000 0.5\n-\tvstr\td10, [sp, #56]\t@ 0x38\n-\tvmul.f64\td27, d10, d28\n-\tvldr\td11, [sp, #240]\t@ 0xf0\n-\tvfma.f64\td30, d14, d14\n-\tvldr\td22, [pc, #732]\t@ c18 <__gridxc_hybrids_MOD_hsexc+0x438>\n-\tvstr\td14, [sp, #80]\t@ 0x50\n-\tvstr\td0, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td22, d11, d22\n-\tvmul.f64\td23, d9, d12\n-\tvstr\td12, [sp, #64]\t@ 0x40\n-\tvmul.f64\td28, d30, d28\n-\tvstr\td30, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td10, d28, d28\n-\tvmul.f64\td23, d23, d28\n-\tvdiv.f64\td14, d27, d23\n-\tvmul.f64\td10, d10, d28\n-\tvdiv.f64\td28, d22, d10\n-\tvmul.f64\td15, d14, d14\n-\tvneg.f64\td0, d28\n-\tvstr\td28, [sp, #168]\t@ 0xa8\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvstr\td0, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td3, d10, d11\n+\tvstr\td9, [sp, #136]\t@ 0x88\n+\tvmul.f64\td5, d6, d6\n+\tvldr\td4, [pc, #724]\t@ cd8 <__gridxc_hybrids_MOD_hsexc+0x458>\n+\tvmla.f64\td5, d0, d0\n+\tvldr\td6, [sp, #240]\t@ 0xf0\n+\tvstr\td11, [sp, #144]\t@ 0x90\n+\tvmul.f64\td4, d6, d4\n+\tvstr\td6, [sp, #8]\n+\tvmov.f64\td0, d5\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td2, d9, d5\n+\tvmul.f64\td5, d0, d5\n+\tvstr\td0, [sp, #120]\t@ 0x78\n+\tvmul.f64\td9, d5, d5\n+\tvmul.f64\td3, d3, d5\n+\tvdiv.f64\td11, d2, d3\n+\tvmul.f64\td9, d9, d5\n+\tvdiv.f64\td3, d4, d9\n+\tvmul.f64\td13, d11, d11\n+\tvneg.f64\td0, d3\n+\tvstr\td3, [sp, #160]\t@ 0xa0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvsub.f64\td29, d0, d13\n-\tvldr\td22, [pc, #668]\t@ c20 <__gridxc_hybrids_MOD_hsexc+0x440>\n-\tvmul.f64\td3, d15, d15\n-\tvldr\td17, [pc, #668]\t@ c28 <__gridxc_hybrids_MOD_hsexc+0x448>\n-\tvmov.f64\td12, d15\n-\tvmov.f64\td23, d13\n-\tvstr\td0, [sp, #160]\t@ 0xa0\n-\tvstr\td29, [sp, #152]\t@ 0x98\n-\tvmul.f64\td17, d10, d17\n-\tvstr\td3, [sp, #144]\t@ 0x90\n-\tvdiv.f64\td10, d22, d29\n-\tvstr\td17, [sp, #16]\n-\tvfma.f64\td12, d3, d10\n-\tvfma.f64\td23, d10, d12\n-\tvmul.f64\td22, d12, d22\n-\tvdiv.f64\td4, d13, d23\n-\tvmul.f64\td23, d22, d4\n-\tvstr\td4, [sp, #136]\t@ 0x88\n-\tvadd.f64\td7, d23, d13\n-\tvstr\td23, [sp, #128]\t@ 0x80\n-\tvmov.f64\td0, d7\n-\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvsub.f64\td1, d0, d8\n+\tvldr\td5, [pc, #648]\t@ ce0 <__gridxc_hybrids_MOD_hsexc+0x460>\n+\tvmov.f64\td7, d13\n+\tvstr\td0, [sp, #208]\t@ 0xd0\n+\tvmov.f64\td3, d8\n+\tvldr\td4, [pc, #640]\t@ ce8 <__gridxc_hybrids_MOD_hsexc+0x468>\n+\tvdiv.f64\td0, d5, d1\n+\tvstr\td1, [sp, #128]\t@ 0x80\n+\tvmul.f64\td9, d9, d4\n+\tvmul.f64\td4, d13, d13\n+\tvstr\td4, [sp, #80]\t@ 0x50\n+\tvmla.f64\td7, d4, d0\n+\tvstr\td0, [sp, #24]\n+\tvmla.f64\td3, d0, d7\n+\tvmul.f64\td5, d7, d5\n+\tvstr\td7, [sp, #32]\n+\tvdiv.f64\td4, d8, d3\n+\tvmul.f64\td3, d5, d4\n+\tvstr\td4, [sp, #176]\t@ 0xb0\n+\tvadd.f64\td5, d3, d8\n+\tvstr\td3, [sp, #72]\t@ 0x48\n+\tvmov.f64\td0, d5\n+\tvstr\td5, [sp, #200]\t@ 0xc8\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td17, [sp, #16]\n-\tvldr\td2, [sp, #312]\t@ 0x138\n+\tvmul.f64\td5, d9, d0\n+\tvldr\td6, [sp, #8]\n \tmov\tr2, r4\n-\tvldr\td19, [sp, #320]\t@ 0x140\n+\tvldr\td2, [sp, #312]\t@ 0x138\n \tmov\tr1, r6\n-\tvmul.f64\td0, d17, d0\n \tmov\tr0, r8\n \tadd\tr3, sp, #344\t@ 0x158\n+\tvadd.f64\td4, d6, d5\n \tstr\tr3, [sp, #4]\n+\tvstr\td2, [sp, #184]\t@ 0xb8\n \tadd\tr3, sp, #280\t@ 0x118\n+\tvldr\td2, [sp, #320]\t@ 0x140\n+\tadd\tr4, sp, #248\t@ 0xf8\n \tstr\tr3, [sp, #0]\n \tadd\tr3, sp, #256\t@ 0x100\n-\tvstr\td17, [sp, #112]\t@ 0x70\n-\tvadd.f64\td22, d11, d0\n-\tvstr\td2, [sp, #104]\t@ 0x68\n-\tvstr\td19, [sp, #224]\t@ 0xe0\n-\tadd\tr4, sp, #248\t@ 0xf8\n-\tvstr\td0, [sp, #96]\t@ 0x60\n-\tvstr\td22, [sp, #32]\n+\tvstr\td4, [sp, #112]\t@ 0x70\n+\tvstr\td2, [sp, #224]\t@ 0xe0\n+\tvstr\td5, [sp, #40]\t@ 0x28\n \tbl\t0 <__gridxc_xwpbe_MOD_xwpbe>\n R_ARM_THM_CALL\t__gridxc_xwpbe_MOD_xwpbe\n-\tvldr\td16, [sp, #24]\n+\tvldr\td6, [sp, #104]\t@ 0x68\n \tadd\tr3, sp, #328\t@ 0x148\n-\tvldr\td18, [sp, #48]\t@ 0x30\n+\tvldr\td5, [sp, #16]\n \tadd\tr2, sp, #296\t@ 0x128\n \tmov\tr1, r5\n \tmov\tr0, r7\n-\tvadd.f64\td16, d16, d16\n+\tvadd.f64\td6, d6, d6\n \tstr\tr3, [sp, #0]\n \tmov\tr3, r4\n-\tvstr\td18, [sp, #24]\n-\tvmaxnm.f64\td16, d16, d18\n-\tvstr\td16, [sp, #296]\t@ 0x128\n-\tvldr\td16, [sp, #256]\t@ 0x100\n-\tvmul.f64\td16, d8, d16\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tvstr\td16, [sp, #16]\n+\tvcmpe.f64\td6, d14\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td6, d14\n+\tvstr\td6, [sp, #296]\t@ 0x128\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvmul.f64\td6, d5, d6\n+\tvstr\td6, [sp, #256]\t@ 0x100\n+\tvstr\td6, [sp, #104]\t@ 0x68\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tvldr\td19, [sp, #40]\t@ 0x28\n+\tvcmpe.f64\td15, d14\n \tmov\tr3, r4\n-\tvldr\td18, [sp, #24]\n \tadd\tr2, sp, #336\t@ 0x150\n \tmov\tr1, r5\n \tstr\tr2, [sp, #0]\n-\tvadd.f64\td19, d19, d19\n \tmov\tr0, r7\n \tadd\tr2, sp, #304\t@ 0x130\n-\tvmaxnm.f64\td19, d19, d18\n-\tvstr\td19, [sp, #304]\t@ 0x130\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tlt\n+\tvmovlt.f64\td15, d14\n+\tvstr\td15, [sp, #304]\t@ 0x130\n \tbl\t0 <__gridxc_lda_MOD_exchng>\n R_ARM_THM_CALL\t__gridxc_lda_MOD_exchng\n-\tldr\tr3, [sp, #8]\n+\tldr\tr3, [sp, #88]\t@ 0x58\n \tcmp.w\tfp, #0\n-\tvldr\td16, [sp, #16]\n-\tvldr\td22, [sp, #32]\n-\tvstr\td16, [r3]\n-\tldr\tr3, [sp, #12]\n-\tvstr\td22, [r3]\n-\tble.w\td26 <__gridxc_hybrids_MOD_hsexc+0x546>\n-\tvldr\td17, [sp, #64]\t@ 0x40\n+\tvldr\td6, [sp, #104]\t@ 0x68\n+\tvldr\td4, [sp, #112]\t@ 0x70\n+\tvstr\td6, [r3]\n+\tldr\tr3, [sp, #100]\t@ 0x64\n+\tvstr\td4, [r3]\n+\tble.w\te6a <__gridxc_hybrids_MOD_hsexc+0x5ea>\n+\tvldr\td2, [sp, #144]\t@ 0x90\n \tcmp.w\tfp, #1\n-\tvldr\td24, [sp, #192]\t@ 0xc0\n-\tvldr\td18, [sp, #80]\t@ 0x50\n-\tvldr\td20, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td19, d24, d17\n-\tvldr\td21, [sp, #208]\t@ 0xd0\n-\tvdiv.f64\td24, d13, d18\n-\tvldr\td25, [sp, #216]\t@ 0xd8\n-\tvdiv.f64\td16, d13, d20\n-\tvldr\td26, [sp, #200]\t@ 0xc8\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvmul.f64\td18, d9, d25\n-\tvldr\td27, [sp, #160]\t@ 0xa0\n-\tvldr\td28, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td22, d17, d8\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tvmul.f64\td27, d27, d10\n-\tvldr\td30, [sp, #176]\t@ 0xb0\n-\tvldr\td29, [sp, #152]\t@ 0x98\n-\tvldr\td2, [sp, #104]\t@ 0x68\n-\tvldr\td7, [sp, #120]\t@ 0x78\n-\tvmul.f64\td27, d27, d28\n-\tvldr\td23, [sp, #128]\t@ 0x80\n-\tvldr\td3, [sp, #144]\t@ 0x90\n-\tvldr\td4, [sp, #136]\t@ 0x88\n-\tvldr\td0, [sp, #96]\t@ 0x60\n-\tvdiv.f64\td31, d27, d29\n-\tldr\tr0, [sp, #88]\t@ 0x58\n-\tvdiv.f64\td27, d13, d7\n-\tldr\tr1, [sp, #92]\t@ 0x5c\n-\tvadd.f64\td29, d0, d2\n-\tldrd\tr2, r3, [sp, #280]\t@ 0x118\n-\tstrd\tr2, r3, [r0]\n-\tldrd\tr2, r3, [sp, #344]\t@ 0x158\n-\tstrd\tr2, r3, [r9]\n-\tldrd\tr2, r3, [sp, #352]\t@ 0x160\n-\tstrd\tr2, r3, [r9, #8]\n-\tvsub.f64\td24, d24, d16\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td20, d13, d16\n-\tvmul.f64\td16, d9, d21\n-\tvmul.f64\td21, d9, d26\n-\tvmov.f64\td26, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td21, d21, d20\n-\tvmul.f64\td20, d14, d20\n-\tvmul.f64\td16, d16, d17\n-\tvmul.f64\td18, d18, d17\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td17, d17, d23\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td21, d21, d20\n-\tvldr\td20, [pc, #200]\t@ c30 <__gridxc_hybrids_MOD_hsexc+0x450>\n-\tvmul.f64\td17, d17, d27\n-\tvmul.f64\td20, d19, d20\n-\tvmul.f64\td20, d20, d8\n-\tvdiv.f64\td25, d20, d19\n-\tvmov.f64\td20, #0\t@ 0x40000000 2.0\n-\tvmul.f64\td19, d11, d9\n-\tvdiv.f64\td28, d20, d30\n-\tvdiv.f64\td30, d13, d12\n-\tvdiv.f64\td6, d13, d19\n-\tvldr\td19, [pc, #168]\t@ c38 <__gridxc_hybrids_MOD_hsexc+0x458>\n-\tvmul.f64\td24, d24, d19\n-\tvmov.f64\td19, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td19, d10, d19\n-\tvmul.f64\td22, d22, d24\n-\tvfma.f64\td20, d15, d19\n-\tvmul.f64\td20, d14, d20\n-\tvmul.f64\td14, d14, d20\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td21, d21, d20\n-\tvsub.f64\td20, d2, d11\n-\tvadd.f64\td25, d25, d8\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td7, d28, d26\n-\tvmul.f64\td18, d18, d23\n-\tvmul.f64\td21, d21, d23\n-\tvmul.f64\td26, d0, d26\n-\tvmul.f64\td20, d20, d6\n-\tvfms.f64\td20, d7, d22\n-\tvmul.f64\td22, d28, d22\n-\tvadd.f64\td23, d25, d22\n-\tvmul.f64\td22, d26, d22\n-\tvmul.f64\td20, d20, d31\n-\tb.n\tc4c <__gridxc_hybrids_MOD_hsexc+0x46c>\n+\tvldr\td1, [sp, #216]\t@ 0xd8\n+\tvldr\td14, [sp, #168]\t@ 0xa8\n+\tvldr\td0, [sp, #24]\n+\tvmul.f64\td1, d1, d2\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvdiv.f64\td7, d8, d14\n+\tvldr\td3, [sp, #208]\t@ 0xd0\n+\tvldr\td14, [sp, #160]\t@ 0xa0\n+\tvdiv.f64\td2, d8, d2\n+\tvldr\td15, [sp, #152]\t@ 0x98\n+\tvldr\td5, [sp, #200]\t@ 0xc8\n+\tvsub.f64\td2, d2, d7\n+\tvmul.f64\td7, d3, d0\n+\tvmul.f64\td7, d7, d14\n+\tvldr\td14, [sp, #128]\t@ 0x80\n+\tvdiv.f64\td14, d7, d14\n+\tvmul.f64\td7, d10, d12\n+\tvldr\td12, [sp, #64]\t@ 0x40\n+\tvstr\td14, [sp, #88]\t@ 0x58\n+\tvldr\td14, [sp, #16]\n+\tvmul.f64\td6, d15, d14\n+\tvldr\td15, [sp, #136]\t@ 0x88\n+\tvdiv.f64\td3, d8, d15\n+\tvdiv.f64\td15, d8, d5\n+\tvmul.f64\td5, d10, d12\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvmul.f64\td4, d10, d12\n+\tvldr\td12, [sp, #72]\t@ 0x48\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td3, d11, d3\n+\tvmul.f64\td7, d7, d9\n+\tvmul.f64\td5, d5, d9\n+\tvmul.f64\td4, d4, d9\n+\tvmul.f64\td9, d9, d12\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d3\n+\tvldr\td3, [pc, #228]\t@ cf0 <__gridxc_hybrids_MOD_hsexc+0x470>\n+\tvmul.f64\td9, d9, d15\n+\tvmul.f64\td3, d1, d3\n+\tvstr\td9, [sp, #64]\t@ 0x40\n+\tvldr\td9, [sp, #120]\t@ 0x78\n+\tvmul.f64\td3, d3, d14\n+\tvdiv.f64\td12, d3, d1\n+\tvldr\td1, [sp, #8]\n+\tvmov.f64\td3, #0\t@ 0x40000000 2.0\n+\tvdiv.f64\td9, d3, d9\n+\tvmul.f64\td1, d1, d10\n+\tvadd.f64\td12, d12, d14\n+\tvdiv.f64\td14, d8, d1\n+\tvldr\td1, [sp, #32]\n+\tvstr\td14, [sp, #56]\t@ 0x38\n+\tvdiv.f64\td14, d8, d1\n+\tvldr\td1, [pc, #172]\t@ cf8 <__gridxc_hybrids_MOD_hsexc+0x478>\n+\tvmul.f64\td2, d2, d1\n+\tvmov.f64\td1, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td1, d0, d1\n+\tvldr\td0, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td6, d6, d2\n+\tvmla.f64\td3, d1, d13\n+\tvldr\td1, [sp, #40]\t@ 0x28\n+\tvmov.f64\td13, #8\t@ 0x40400000 3.0\n+\tvmul.f64\td3, d3, d11\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td11, d11, d3\n+\tvldr\td3, [sp, #72]\t@ 0x48\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td5, d5, d3\n+\tvmul.f64\td4, d4, d3\n+\tvldr\td3, [sp, #8]\n+\tvsub.f64\td8, d0, d3\n+\tvadd.f64\td3, d1, d0\n+\tvmul.f64\td0, d9, d6\n+\tvstr\td0, [sp, #48]\t@ 0x30\n+\tvmul.f64\td0, d9, d13\n+\tb.n\td0c <__gridxc_hybrids_MOD_hsexc+0x48c>\n+\tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n+\t.word\t0x6dc9c883\n+\t.word\t0x3ff45f30\n \t.word\t0xffffdcd1\n \t.word\t0xbfefffff\n \t.word\t0xffffdcd1\n \t.word\t0x3fefffff\n-\t.word\t0x6dc9c883\n-\t.word\t0x3ff45f30\n \t.word\t0xeafdf295\n \t.word\t0x404014fc\n \t.word\t0xdd62e0ae\n \t.word\t0x40012b4b\n \t.word\t0xf1fb1946\n \t.word\t0x3f9fd63c\n \t.word\t0x55555555\n \t.word\t0x3fc55555\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n-\t.word\t0x0000043c\n+\t.word\t0x0000045c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x000003bc\n+\t.word\t0x000003c0\n R_ARM_REL32\t.rodata\n-\tvnmul.f64\td23, d14, d23\n-\tvfma.f64\td23, d3, d20\n-\tvmul.f64\td20, d12, d20\n-\tvfma.f64\td20, d10, d23\n-\tvmul.f64\td23, d30, d23\n-\tvfms.f64\td23, d4, d20\n-\tvmov.f64\td20, d30\n-\tvfms.f64\td20, d10, d4\n-\tvfma.f64\td22, d23, d17\n-\tvmul.f64\td16, d16, d20\n-\tvmul.f64\td18, d18, d20\n-\tvmul.f64\td20, d21, d20\n-\tvmul.f64\td16, d16, d27\n-\tvmul.f64\td18, d18, d27\n-\tvmul.f64\td20, d20, d27\n-\tvfma.f64\td29, d9, d22\n-\tvstr\td16, [sl]\n-\tvstr\td18, [sl, #8]\n-\tvstr\td20, [sl, #16]\n-\tvstr\td29, [r1]\n+\tvmul.f64\td13, d1, d13\n+\tvldr\td1, [sp, #32]\n+\tvmul.f64\td6, d0, d6\n+\tvstr\td0, [sp, #72]\t@ 0x48\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvnmls.f64\td6, d8, d0\n+\tvldr\td8, [sp, #88]\t@ 0x58\n+\tvldr\td0, [sp, #80]\t@ 0x50\n+\tvmul.f64\td6, d6, d8\n+\tvldr\td8, [sp, #48]\t@ 0x30\n+\tvadd.f64\td8, d12, d8\n+\tvmul.f64\td8, d8, d11\n+\tvnmls.f64\td8, d0, d6\n+\tvldr\td0, [sp, #24]\n+\tvmul.f64\td6, d1, d6\n+\tvldr\td1, [sp, #176]\t@ 0xb0\n+\tldr\tr0, [sp, #192]\t@ 0xc0\n+\tldrd\tr2, r3, [sp, #280]\t@ 0x118\n+\tldr\tr1, [sp, #196]\t@ 0xc4\n+\tstrd\tr2, r3, [r0]\n+\tldrd\tr2, r3, [sp, #344]\t@ 0x158\n+\tvmla.f64\td6, d0, d8\n+\tstrd\tr2, r3, [r9]\n+\tldrd\tr2, r3, [sp, #352]\t@ 0x160\n+\tstrd\tr2, r3, [r9, #8]\n \tldrd\tr2, r3, [sp, #360]\t@ 0x168\n \tstrd\tr2, r3, [r9, #16]\n-\tbeq.n\td26 <__gridxc_hybrids_MOD_hsexc+0x546>\n-\tvldr\td1, [sp, #232]\t@ 0xe8\n-\tvldr\td19, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td6, d6, d1\n+\tvnmls.f64\td6, d14, d8\n+\tvldr\td8, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d6, d8\n+\tvldr\td8, [sp, #48]\t@ 0x30\n+\tvmla.f64\td6, d13, d8\n+\tvmov.f64\td8, d1\n+\tvmla.f64\td3, d6, d10\n+\tvmov.f64\td6, d14\n+\tvmls.f64\td6, d0, d1\n+\tvstr\td3, [r1]\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td5, d5, d6\n+\tvmul.f64\td6, d4, d6\n+\tvmul.f64\td7, d7, d15\n+\tvmul.f64\td5, d5, d15\n+\tvmul.f64\td6, d6, d15\n+\tvstr\td7, [sl]\n+\tvstr\td5, [sl, #8]\n+\tvstr\td6, [sl, #16]\n+\tbeq.n\te6a <__gridxc_hybrids_MOD_hsexc+0x5ea>\n+\tvldr\td4, [sp, #16]\n+\tvldr\td15, [sp, #232]\t@ 0xe8\n+\tvldr\td3, [sp, #8]\n+\tvstr\td5, [sl, #32]\n+\tvnmul.f64\td4, d4, d15\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvstr\td7, [sl, #24]\n+\tvstr\td6, [sl, #40]\t@ 0x28\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmul.f64\td4, d4, d2\n+\tvldr\td2, [sp, #224]\t@ 0xe0\n \tldrd\tr2, r3, [sp, #288]\t@ 0x120\n-\tvnmul.f64\td8, d8, d1\n-\tvsub.f64\td11, d19, d11\n-\tvadd.f64\td21, d19, d0\n \tstrd\tr2, r3, [r0, #8]\n+\tvsub.f64\td7, d2, d3\n+\tvldr\td3, [sp, #56]\t@ 0x38\n+\tvmul.f64\td1, d4, d5\n+\tvmla.f64\td12, d9, d4\n+\tvldr\td5, [sp, #32]\n+\tvmul.f64\td4, d4, d13\n+\tvadd.f64\td6, d2, d6\n \tldrd\tr2, r3, [sp, #368]\t@ 0x170\n-\tvmul.f64\td8, d8, d24\n-\tvmul.f64\td11, d11, d6\n+\tvnmls.f64\td1, d7, d3\n+\tvldr\td7, [sp, #88]\t@ 0x58\n \tstrd\tr2, r3, [r9, #24]\n \tldrd\tr2, r3, [sp, #376]\t@ 0x178\n+\tvmul.f64\td12, d12, d11\n \tstrd\tr2, r3, [r9, #32]\n-\tvfms.f64\td11, d8, d7\n-\tvfma.f64\td25, d28, d8\n-\tvmul.f64\td8, d8, d26\n-\tvstr\td16, [sl, #24]\n \tldrd\tr2, r3, [sp, #384]\t@ 0x180\n \tstrd\tr2, r3, [r9, #40]\t@ 0x28\n-\tvstr\td18, [sl, #32]\n-\tvmul.f64\td8, d8, d28\n-\tvstr\td20, [sl, #40]\t@ 0x28\n-\tvmul.f64\td31, d11, d31\n-\tvnmul.f64\td19, d14, d25\n-\tvfma.f64\td19, d3, d31\n-\tvmul.f64\td12, d12, d31\n-\tvfma.f64\td12, d19, d10\n-\tvmul.f64\td19, d19, d30\n-\tvfms.f64\td19, d12, d4\n-\tvfma.f64\td8, d19, d17\n-\tvfma.f64\td21, d9, d8\n-\tvstr\td21, [r1, #8]\n-\tldr\tr2, [pc, #80]\t@ (d78 <__gridxc_hybrids_MOD_hsexc+0x598>)\n-\tldr\tr3, [pc, #80]\t@ (d7c <__gridxc_hybrids_MOD_hsexc+0x59c>)\n+\tvmul.f64\td1, d1, d7\n+\tvldr\td7, [sp, #80]\t@ 0x50\n+\tvnmls.f64\td12, d7, d1\n+\tvmul.f64\td7, d12, d0\n+\tvmla.f64\td7, d5, d1\n+\tvmul.f64\td7, d7, d8\n+\tvldr\td8, [sp, #64]\t@ 0x40\n+\tvnmls.f64\td7, d12, d14\n+\tvmul.f64\td7, d7, d8\n+\tvmla.f64\td7, d4, d9\n+\tvmla.f64\td6, d7, d10\n+\tvstr\td6, [r1, #8]\n+\tldr\tr2, [pc, #100]\t@ (ed0 <__gridxc_hybrids_MOD_hsexc+0x650>)\n+\tldr\tr3, [pc, #100]\t@ (ed4 <__gridxc_hybrids_MOD_hsexc+0x654>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #396]\t@ 0x18c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\td66 <__gridxc_hybrids_MOD_hsexc+0x586>\n+\tbne.n\tec0 <__gridxc_hybrids_MOD_hsexc+0x640>\n \tadd\tsp, #404\t@ 0x194\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tvmov.f64\td17, #96\t@ 0x3f000000 0.5\n-\tvldr\td9, [pc, #36]\t@ d70 <__gridxc_hybrids_MOD_hsexc+0x590>\n-\tvldr\td25, [r4, #8]\n-\tvmul.f64\td17, d16, d17\n-\tvldr\td26, [r4, #16]\n-\tvmaxnm.f64\td9, d16, d9\n-\tvstr\td17, [sp, #264]\t@ 0x108\n-\tvstr\td17, [sp, #272]\t@ 0x110\n-\tb.n\t872 <__gridxc_hybrids_MOD_hsexc+0x92>\n+\tvldr\td10, [pc, #60]\t@ ec8 <__gridxc_hybrids_MOD_hsexc+0x648>\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvldr\td6, [r4, #8]\n+\tvmul.f64\td7, d3, d7\n+\tvcmpe.f64\td3, d10\n+\tvstr\td6, [sp, #64]\t@ 0x40\n+\tvldr\td6, [r4, #16]\n+\tvstr\td7, [sp, #264]\t@ 0x108\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td7, [sp, #272]\t@ 0x110\n+\tvmov.f64\td5, d6\n+\tvstr\td6, [sp, #56]\t@ 0x38\n+\tit\tge\n+\tvmovge.f64\td10, d3\n+\tb.n\t928 <__gridxc_hybrids_MOD_hsexc+0xa8>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n \tnop.w\n \t.word\t0x812dea11\n \t.word\t0x3d719799\n-\t.word\t0x0000004a\n+\t.word\t0x0000005e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}]}, {"source1": "xc_xwpbe.F90.o", "source2": "xc_xwpbe.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 39700 (bytes into file)\n+ Start of section headers: 41028 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 11\n Section header string table index: 10\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,20 +1,20 @@\n-There are 11 section headers, starting at offset 0x9b14:\n+There are 11 section headers, starting at offset 0xa044:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 008f08 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 0097e4 0002d0 08 I 8 1 4\n- [ 3] .data PROGBITS 00000000 008f40 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 008f40 000000 00 WA 0 0 1\n- [ 5] .rodata.str1.4 PROGBITS 00000000 008f40 000099 01 AMS 0 0 4\n- [ 6] .note.GNU-stack PROGBITS 00000000 008fd9 000000 00 0 0 1\n- [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 008fd9 000033 00 0 0 1\n- [ 8] .symtab SYMTAB 00000000 00900c 0004f0 10 9 69 4\n- [ 9] .strtab STRTAB 00000000 0094fc 0002e5 00 0 0 1\n- [10] .shstrtab STRTAB 00000000 009ab4 00005f 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 009418 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 009d04 0002e0 08 I 8 1 4\n+ [ 3] .data PROGBITS 00000000 009450 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 009450 000000 00 WA 0 0 1\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 009450 000099 01 AMS 0 0 4\n+ [ 6] .note.GNU-stack PROGBITS 00000000 0094e9 000000 00 0 0 1\n+ [ 7] .ARM.attributes ARM_ATTRIBUTES 00000000 0094e9 00002d 00 0 0 1\n+ [ 8] .symtab SYMTAB 00000000 009518 000500 10 9 69 4\n+ [ 9] .strtab STRTAB 00000000 009a18 0002eb 00 0 0 1\n+ [10] .shstrtab STRTAB 00000000 009fe4 00005f 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,82 +1,83 @@\n \n-Symbol table '.symtab' contains 79 entries:\n+Symbol table '.symtab' contains 80 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n- 1: 00000001 928 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_calerf.constprop.0.isra.0\n+ 1: 00000001 936 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_calerf.constprop.0.isra.0\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n 3: 00000258 0 NOTYPE LOCAL DEFAULT 1 $d\n 4: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 5: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 6: 0000003c 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 7: 00000050 0 NOTYPE LOCAL DEFAULT 5 .LC2\n 8: 0000007c 0 NOTYPE LOCAL DEFAULT 5 .LC3\n- 9: 000003a0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 10: 000003a1 564 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0\n- 11: 00000598 0 NOTYPE LOCAL DEFAULT 1 $d\n- 12: 000005d4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 13: 000005d5 224 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_exer.isra.0\n- 14: 00000698 0 NOTYPE LOCAL DEFAULT 1 $d\n- 15: 000006b4 0 NOTYPE LOCAL DEFAULT 1 $t\n- 16: 000006b5 188 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_d2exeirhondrho.isra.0\n- 17: 00000748 0 NOTYPE LOCAL DEFAULT 1 $d\n- 18: 00000770 0 NOTYPE LOCAL DEFAULT 1 $t\n- 19: 00000771 176 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0\n- 20: 000007f8 0 NOTYPE LOCAL DEFAULT 1 $d\n- 21: 00000820 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 00000821 3392 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0\n- 23: 00000c28 0 NOTYPE LOCAL DEFAULT 1 $d\n- 24: 00000d70 0 NOTYPE LOCAL DEFAULT 1 $t\n- 25: 000014f0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 26: 00001560 0 NOTYPE LOCAL DEFAULT 1 $t\n- 27: 00001561 4144 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0\n- 28: 00001960 0 NOTYPE LOCAL DEFAULT 1 $d\n- 29: 00001a38 0 NOTYPE LOCAL DEFAULT 1 $t\n- 30: 00001e38 0 NOTYPE LOCAL DEFAULT 1 $d\n- 31: 00001f78 0 NOTYPE LOCAL DEFAULT 1 $t\n- 32: 00002550 0 NOTYPE LOCAL DEFAULT 1 $d\n- 33: 00002590 0 NOTYPE LOCAL DEFAULT 1 $t\n- 34: 00002591 4308 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0\n- 35: 00002998 0 NOTYPE LOCAL DEFAULT 1 $d\n- 36: 00002b08 0 NOTYPE LOCAL DEFAULT 1 $t\n- 37: 00003310 0 NOTYPE LOCAL DEFAULT 1 $d\n- 38: 00003410 0 NOTYPE LOCAL DEFAULT 1 $t\n- 39: 00003665 5396 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0\n- 40: 00003a60 0 NOTYPE LOCAL DEFAULT 1 $d\n- 41: 00003b30 0 NOTYPE LOCAL DEFAULT 1 $t\n- 42: 00003f28 0 NOTYPE LOCAL DEFAULT 1 $d\n- 43: 00004088 0 NOTYPE LOCAL DEFAULT 1 $t\n- 44: 00004890 0 NOTYPE LOCAL DEFAULT 1 $d\n- 45: 00004960 0 NOTYPE LOCAL DEFAULT 1 $t\n- 46: 00004b68 0 NOTYPE LOCAL DEFAULT 1 $d\n- 47: 00004b78 0 NOTYPE LOCAL DEFAULT 1 $t\n- 48: 00004b79 7120 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0\n- 49: 00004f80 0 NOTYPE LOCAL DEFAULT 1 $d\n- 50: 000051a8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 51: 00005988 0 NOTYPE LOCAL DEFAULT 1 $d\n- 52: 00005ad8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 53: 00006290 0 NOTYPE LOCAL DEFAULT 1 $d\n- 54: 000063c8 0 NOTYPE LOCAL DEFAULT 1 $t\n- 55: 00006749 8672 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0\n- 56: 00006b50 0 NOTYPE LOCAL DEFAULT 1 $d\n- 57: 00006c18 0 NOTYPE LOCAL DEFAULT 1 $t\n- 58: 00007018 0 NOTYPE LOCAL DEFAULT 1 $d\n- 59: 00007238 0 NOTYPE LOCAL DEFAULT 1 $t\n- 60: 00007a38 0 NOTYPE LOCAL DEFAULT 1 $d\n- 61: 00007b78 0 NOTYPE LOCAL DEFAULT 1 $t\n- 62: 00008370 0 NOTYPE LOCAL DEFAULT 1 $d\n- 63: 00008460 0 NOTYPE LOCAL DEFAULT 1 $t\n- 64: 000088a0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 65: 00008928 0 NOTYPE LOCAL DEFAULT 1 $t\n- 66: 00008c38 0 NOTYPE LOCAL DEFAULT 1 $d\n- 67: 00008c8c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 68: 00008ec0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n- 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n- 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n- 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n- 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n- 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n- 78: 00008929 1504 FUNC GLOBAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe\n+ 9: 000003a8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 10: 000003a9 564 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0\n+ 11: 000005a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 12: 000005dc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 13: 000005dd 224 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_exer.isra.0\n+ 14: 000006a0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 15: 000006bc 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 16: 000006bd 188 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_d2exeirhondrho.isra.0\n+ 17: 00000750 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 18: 00000778 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 19: 00000779 176 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0\n+ 20: 00000800 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 00000828 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 22: 00000829 3456 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0\n+ 23: 00000bd8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 24: 00000d10 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 25: 00001528 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 26: 000015a8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 27: 000015a9 4296 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0\n+ 28: 000019b0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 29: 00001a60 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 30: 00001e58 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 31: 00001f88 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 32: 00002600 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 33: 00002670 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 34: 00002671 4452 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0\n+ 35: 00002a78 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 36: 00002be0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 37: 000033e0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 38: 000034f8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 39: 000037d5 5620 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0\n+ 40: 00003bd8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 41: 00003c98 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 42: 000040a8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 43: 00004210 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 44: 00004a18 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 45: 00004af0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 46: 00004da8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 47: 00004dc8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 48: 00004dc9 7440 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0\n+ 49: 000051d0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 50: 00005388 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 51: 00005b68 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 52: 00005cc0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 53: 000064b8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 54: 00006648 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 55: 00006ad9 9008 FUNC LOCAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0\n+ 56: 00006ee0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 57: 00006fa0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 58: 000073c0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 59: 000075d0 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 60: 00007dd0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 61: 00007ed8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 62: 000086c8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 63: 000087f8 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 64: 00008d78 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 65: 00008e08 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 66: 00009120 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 67: 0000917c 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 68: 000093d0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND trunc\n+ 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND exp\n+ 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n+ 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND log\n+ 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND cbrt\n+ 79: 00008e09 1552 FUNC GLOBAL DEFAULT 1 __gridxc_xwpbe_MOD_xwpbe\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,93 +1,95 @@\n \n-Relocation section '.rel.text' at offset 0x97e4 contains 90 entries:\n+Relocation section '.rel.text' at offset 0x9d04 contains 92 entries:\n Offset Info Type Sym. Value Symbol's Name\n-000000ea 0000450a R_ARM_THM_CALL 00000000 exp\n-00000248 0000450a R_ARM_THM_CALL 00000000 exp\n-000003e6 0000460a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000003f2 0000470a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-000003f8 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-000004ba 0000450a R_ARM_THM_CALL 00000000 exp\n-000004c8 0000490a R_ARM_THM_CALL 00000000 log\n-00000548 0000460a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000554 0000470a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000055a 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000578 0000460a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-00000584 0000470a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000058a 0000480a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000590 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000005b0 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000005b4 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000005b8 00000503 R_ARM_REL32 00000000 .LC0\n-000005bc 00000603 R_ARM_REL32 0000003c .LC1\n-000005c0 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000005c4 00000503 R_ARM_REL32 00000000 .LC0\n-000005c8 00000803 R_ARM_REL32 0000007c .LC3\n+000000ba 0000450a R_ARM_THM_CALL 00000000 trunc\n+000000d6 0000460a R_ARM_THM_CALL 00000000 exp\n+00000204 0000450a R_ARM_THM_CALL 00000000 trunc\n+00000220 0000460a R_ARM_THM_CALL 00000000 exp\n+000003ee 0000470a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+000003fa 0000480a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000400 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000004c2 0000460a R_ARM_THM_CALL 00000000 exp\n+000004d0 00004a0a R_ARM_THM_CALL 00000000 log\n+00000550 0000470a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000055c 0000480a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000562 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000580 0000470a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000058c 0000480a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000592 0000490a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000598 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000005b8 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000005bc 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000005c0 00000503 R_ARM_REL32 00000000 .LC0\n+000005c4 00000603 R_ARM_REL32 0000003c .LC1\n+000005c8 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n 000005cc 00000503 R_ARM_REL32 00000000 .LC0\n-000005d0 00000703 R_ARM_REL32 00000050 .LC2\n-0000066c 0000450a R_ARM_THM_CALL 00000000 exp\n-00000690 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-000006a8 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000006ac 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000006b0 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000732 0000450a R_ARM_THM_CALL 00000000 exp\n-000007e2 0000450a R_ARM_THM_CALL 00000000 exp\n-0000087c 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00000a1a 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00000bd6 0000490a R_ARM_THM_CALL 00000000 log\n-0000137a 0000450a R_ARM_THM_CALL 00000000 exp\n-000013fa 0000450a R_ARM_THM_CALL 00000000 exp\n-00001488 0000450a R_ARM_THM_CALL 00000000 exp\n-000015cc 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00001774 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-0000187c 0000450a R_ARM_THM_CALL 00000000 exp\n-00001a30 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001a34 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00001abc 0000490a R_ARM_THM_CALL 00000000 log\n-00002024 0000450a R_ARM_THM_CALL 00000000 exp\n-00002546 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00002588 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000258c 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000025dc 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00002786 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00002ba8 0000490a R_ARM_THM_CALL 00000000 log\n-00003526 0000450a R_ARM_THM_CALL 00000000 exp\n-000035aa 0000450a R_ARM_THM_CALL 00000000 exp\n-00003608 0000450a R_ARM_THM_CALL 00000000 exp\n-000036bc 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00003878 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-000039b8 0000450a R_ARM_THM_CALL 00000000 exp\n-00003b28 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00003b2c 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00003d14 0000490a R_ARM_THM_CALL 00000000 log\n-0000429c 0000450a R_ARM_THM_CALL 00000000 exp\n-00004a50 0000450a R_ARM_THM_CALL 00000000 exp\n-00004abc 0000450a R_ARM_THM_CALL 00000000 exp\n-00004b1e 0000450a R_ARM_THM_CALL 00000000 exp\n-00004b62 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00004b70 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00004b74 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00004bc0 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00004d64 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00005248 0000490a R_ARM_THM_CALL 00000000 log\n-00006606 0000450a R_ARM_THM_CALL 00000000 exp\n-0000665a 0000450a R_ARM_THM_CALL 00000000 exp\n-000066ec 0000450a R_ARM_THM_CALL 00000000 exp\n-000067a2 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00006956 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00006aaa 0000450a R_ARM_THM_CALL 00000000 exp\n-00006c10 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00006c14 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00006e0c 0000490a R_ARM_THM_CALL 00000000 log\n-000077ac 0000450a R_ARM_THM_CALL 00000000 exp\n-000086f6 0000450a R_ARM_THM_CALL 00000000 exp\n-00008756 0000450a R_ARM_THM_CALL 00000000 exp\n-00008810 0000450a R_ARM_THM_CALL 00000000 exp\n-0000889c 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00008920 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008924 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-000089e2 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00008c80 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008c84 00004c1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00008c88 00004b19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00008cca 00004d0a R_ARM_THM_CALL 00000000 cbrt\n-00008eb6 00004a0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000005d0 00000803 R_ARM_REL32 0000007c .LC3\n+000005d4 00000503 R_ARM_REL32 00000000 .LC0\n+000005d8 00000703 R_ARM_REL32 00000050 .LC2\n+00000674 0000460a R_ARM_THM_CALL 00000000 exp\n+00000698 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000006b0 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000006b4 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000006b8 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000073a 0000460a R_ARM_THM_CALL 00000000 exp\n+000007ea 0000460a R_ARM_THM_CALL 00000000 exp\n+0000087c 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00000a52 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00000d4c 00004a0a R_ARM_THM_CALL 00000000 log\n+0000149a 0000460a R_ARM_THM_CALL 00000000 exp\n+000014cc 0000460a R_ARM_THM_CALL 00000000 exp\n+00001502 0000460a R_ARM_THM_CALL 00000000 exp\n+00001614 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+0000180c 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00001910 0000460a R_ARM_THM_CALL 00000000 exp\n+00001a58 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001a5c 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00001b18 00004a0a R_ARM_THM_CALL 00000000 log\n+000020c4 0000460a R_ARM_THM_CALL 00000000 exp\n+000025fc 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00002668 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000266c 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000026b8 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+000028ae 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00002cf0 00004a0a R_ARM_THM_CALL 00000000 log\n+00003756 0000460a R_ARM_THM_CALL 00000000 exp\n+0000378e 0000460a R_ARM_THM_CALL 00000000 exp\n+000037b4 0000460a R_ARM_THM_CALL 00000000 exp\n+00003834 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00003a20 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00003b78 0000460a R_ARM_THM_CALL 00000000 exp\n+00003c90 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00003c94 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00003ea0 00004a0a R_ARM_THM_CALL 00000000 log\n+00004448 0000460a R_ARM_THM_CALL 00000000 exp\n+00004d42 0000460a R_ARM_THM_CALL 00000000 exp\n+00004d62 0000460a R_ARM_THM_CALL 00000000 exp\n+00004d84 0000460a R_ARM_THM_CALL 00000000 exp\n+00004da0 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00004dc0 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00004dc4 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00004e10 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00004fe4 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00005478 00004a0a R_ARM_THM_CALL 00000000 log\n+00006a6a 0000460a R_ARM_THM_CALL 00000000 exp\n+00006a92 0000460a R_ARM_THM_CALL 00000000 exp\n+00006ab4 0000460a R_ARM_THM_CALL 00000000 exp\n+00006b36 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00006d2e 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00006e92 0000460a R_ARM_THM_CALL 00000000 exp\n+00006f98 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00006f9c 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000071dc 00004a0a R_ARM_THM_CALL 00000000 log\n+00007bfc 0000460a R_ARM_THM_CALL 00000000 exp\n+00008d0c 0000460a R_ARM_THM_CALL 00000000 exp\n+00008d2c 0000460a R_ARM_THM_CALL 00000000 exp\n+00008d4e 0000460a R_ARM_THM_CALL 00000000 exp\n+00008d72 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00008e00 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00008e04 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00008edc 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+00009170 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00009174 00004d1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00009178 00004c19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000091d2 00004e0a R_ARM_THM_CALL 00000000 cbrt\n+000093cc 00004b0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,10 +1,10 @@\n-=@UUUUUU\n H@UUUUUU\n-3@UUUUUU\n+=@UUUUUU\n+R?UUUUUU\n R?UUUUUU\n /build/reproducible-path/libgridxc-2.0.1/src/xc_xwpbe.F90\n Invalid argument\n continued fraction failed in expint_cp2k\n series failed in expint_cp2k\n __gridxc_xwpbe_MOD_calerf.constprop.0.isra.0\n __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -3,208 +3,211 @@\n \n Disassembly of section .text:\n \n 00000000 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_calerf.constprop.0.isra.0():\n \tpush\t{r4, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n+\tvpush\t{d8-d12}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #4072]\t@ 0xfe8\n-\tvabs.f64\td16, d0\n-\tvmov.f64\td17, #94\t@ 0x3ef00000 0.4687500\n-\tvmov.f64\td8, d0\n+\tstr.w\tr0, [ip, #4048]\t@ 0xfd0\n+\tvabs.f64\td8, d0\n+\tvmov.f64\td7, #94\t@ 0x3ef00000 0.4687500\n+\tvmov.f64\td9, d0\n \tmov\tr4, r0\n-\tvcmpe.f64\td16, d17\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbls.w\t12e <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x12e>\n-\tvmov.f64\td17, #16\t@ 0x40800000 4.0\n-\tvcmpe.f64\td16, d17\n+\tvmov.f64\td7, #16\t@ 0x40800000 4.0\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbhi.n\t112 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x112>\n-\tvldr\td19, [pc, #540]\t@ 258 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x258>\n+\tvldr\td4, [pc, #540]\t@ 258 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x258>\n \tvmov.f64\td0, #48\t@ 0x41800000 16.0\n-\tvldr\td17, [pc, #540]\t@ 260 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x260>\n-\tvldr\td18, [pc, #544]\t@ 268 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x268>\n-\tvmul.f64\td0, d16, d0\n-\tvfma.f64\td17, d16, d19\n-\tvldr\td29, [pc, #540]\t@ 270 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x270>\n-\tvldr\td30, [pc, #544]\t@ 278 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x278>\n-\tvadd.f64\td18, d16, d18\n-\tvldr\td27, [pc, #544]\t@ 280 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x280>\n-\tvldr\td28, [pc, #548]\t@ 288 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x288>\n-\tvrintz.f64\td0, d0\n-\tvldr\td25, [pc, #548]\t@ 290 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x290>\n-\tvldr\td26, [pc, #552]\t@ 298 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x298>\n-\tvfma.f64\td30, d16, d18\n-\tvldr\td23, [pc, #552]\t@ 2a0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2a0>\n-\tvldr\td24, [pc, #556]\t@ 2a8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2a8>\n-\tvfma.f64\td29, d16, d17\n-\tvldr\td21, [pc, #556]\t@ 2b0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2b0>\n-\tvldr\td22, [pc, #560]\t@ 2b8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2b8>\n-\tvldr\td19, [pc, #564]\t@ 2c0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2c0>\n-\tvldr\td20, [pc, #568]\t@ 2c8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2c8>\n-\tvldr\td18, [pc, #572]\t@ 2d0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2d0>\n-\tvldr\td17, [pc, #576]\t@ 2d8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2d8>\n-\tvfma.f64\td28, d16, d30\n-\tvldr\td31, [pc, #576]\t@ 2e0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2e0>\n-\tvfma.f64\td27, d16, d29\n-\tvmul.f64\td0, d0, d31\n-\tvsub.f64\td30, d16, d0\n-\tvadd.f64\td29, d16, d0\n-\tvfma.f64\td26, d16, d28\n+\tvldr\td3, [pc, #540]\t@ 260 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x260>\n+\tvldr\td6, [pc, #544]\t@ 268 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x268>\n+\tvmul.f64\td0, d8, d0\n+\tvmla.f64\td3, d8, d4\n+\tvldr\td2, [pc, #540]\t@ 270 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x270>\n+\tvldr\td5, [pc, #544]\t@ 278 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x278>\n+\tvadd.f64\td6, d8, d6\n+\tvldr\td1, [pc, #544]\t@ 280 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x280>\n+\tvldr\td4, [pc, #548]\t@ 288 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x288>\n+\tvldr\td7, [pc, #552]\t@ 290 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x290>\n+\tvldr\td11, [pc, #556]\t@ 298 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x298>\n+\tvmla.f64\td5, d6, d8\n+\tvldr\td6, [pc, #556]\t@ 2a0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2a0>\n+\tvldr\td10, [pc, #560]\t@ 2a8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2a8>\n+\tvmla.f64\td2, d8, d3\n+\tvldr\td3, [pc, #560]\t@ 2b0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2b0>\n+\tvmla.f64\td4, d8, d5\n+\tvldr\td5, [pc, #560]\t@ 2b8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2b8>\n+\tvmla.f64\td1, d8, d2\n+\tvmla.f64\td3, d8, d4\n+\tvldr\td4, [pc, #556]\t@ 2c0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2c0>\n+\tvmla.f64\td6, d8, d1\n+\tvmla.f64\td4, d8, d3\n+\tvmov.f64\td2, d6\n+\tvldr\td6, [pc, #548]\t@ 2c8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2c8>\n+\tvmla.f64\td5, d8, d2\n+\tvmla.f64\td6, d8, d4\n+\tvmla.f64\td7, d8, d5\n+\tvmla.f64\td10, d8, d6\n+\tvmla.f64\td11, d8, d7\n+\tbl\t0 \n+ R_ARM_THM_CALL\ttrunc\n+\tvldr\td7, [pc, #528]\t@ 2d0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2d0>\n+\tvmul.f64\td0, d0, d7\n+\tvsub.f64\td7, d8, d0\n+\tvadd.f64\td6, d8, d0\n \tvmul.f64\td0, d0, d0\n-\tvfma.f64\td25, d16, d27\n-\tvfma.f64\td0, d30, d29\n-\tvfma.f64\td24, d16, d26\n-\tvfma.f64\td23, d16, d25\n-\tvneg.f64\td0, d0\n-\tvfma.f64\td22, d16, d24\n-\tvfma.f64\td21, d16, d23\n-\tvfma.f64\td20, d16, d22\n-\tvfma.f64\td19, d16, d21\n-\tvfma.f64\td17, d16, d20\n-\tvfma.f64\td18, d16, d19\n-\tvdiv.f64\td9, d18, d17\n+\tvnmla.f64\td0, d6, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmul.f64\td0, d9, d0\n+\tvldr\td5, [pc, #508]\t@ 2d8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2d8>\n+\tvldr\td6, [pc, #512]\t@ 2e0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2e0>\n+\tvmla.f64\td5, d8, d11\n+\tvmla.f64\td6, d8, d10\n+\tvdiv.f64\td7, d5, d6\n+\tvmul.f64\td0, d7, d0\n \tvstr\td0, [r4]\n-\tvcmpe.f64\td8, #0.0\n+\tvcmpe.f64\td9, #0.0\n \tvmrs\tAPSR_nzcv, fpscr\n \tbpl.n\t10c <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x10c>\n-\tvmov.f64\td16, #0\t@ 0x40000000 2.0\n-\tvsub.f64\td16, d16, d0\n-\tvstr\td16, [r4]\n-\tvpop\t{d8-d9}\n+\tvmov.f64\td7, #0\t@ 0x40000000 2.0\n+\tvsub.f64\td7, d7, d0\n+\tvstr\td7, [r4]\n+\tvpop\t{d8-d12}\n \tpop\t{r4, pc}\n-\tvldr\td17, [pc, #468]\t@ 2e8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2e8>\n-\tvcmpe.f64\td16, d17\n+\tvldr\td7, [pc, #468]\t@ 2e8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2e8>\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tblt.n\t1ac <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x1ac>\n-\tvmov.i64\td16, #0x0000000000000000\n-\tvmov.f64\td0, d16\n-\tvstr\td16, [r0]\n+\tvldr\td7, [pc, #460]\t@ 2f0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2f0>\n+\tvmov.f64\td0, d7\n+\tvstr\td7, [r0]\n \tb.n\tf6 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0xf6>\n-\tvldr\td17, [pc, #448]\t@ 2f0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2f0>\n-\tvcmpe.f64\td16, d17\n+\tvldr\td7, [pc, #456]\t@ 2f8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2f8>\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n \tbgt.n\t19e <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x19e>\n-\tvmov.i64\td17, #0x0000000000000000\n-\tvmov.f64\td16, d17\n-\tvldr\td18, [pc, #432]\t@ 2f8 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2f8>\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tvldr\td25, [pc, #432]\t@ 300 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x300>\n-\tvldr\td24, [pc, #436]\t@ 308 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x308>\n-\tvadd.f64\td18, d17, d18\n-\tvldr\td23, [pc, #436]\t@ 310 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x310>\n-\tvadd.f64\td25, d16, d25\n-\tvldr\td22, [pc, #436]\t@ 318 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x318>\n-\tvldr\td21, [pc, #440]\t@ 320 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x320>\n-\tvldr\td17, [pc, #444]\t@ 328 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x328>\n-\tvfma.f64\td24, d16, d18\n-\tvldr\td20, [pc, #444]\t@ 330 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x330>\n-\tvfma.f64\td23, d16, d25\n-\tvfma.f64\td22, d16, d24\n-\tvfma.f64\td21, d16, d23\n-\tvfma.f64\td17, d16, d22\n-\tvfma.f64\td20, d16, d21\n-\tvmul.f64\td8, d17, d8\n-\tvdiv.f64\td17, d8, d20\n-\tvpop\t{d8-d9}\n-\tvsub.f64\td17, d19, d17\n-\tvstr\td17, [r4]\n+\tvldr\td6, [pc, #432]\t@ 2f0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2f0>\n+\tvmov.f64\td7, d6\n+\tvldr\td3, [pc, #440]\t@ 300 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x300>\n+\tvldr\td4, [pc, #444]\t@ 308 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x308>\n+\tvldr\td1, [pc, #448]\t@ 310 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x310>\n+\tvadd.f64\td6, d6, d3\n+\tvldr\td5, [pc, #448]\t@ 318 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x318>\n+\tvadd.f64\td4, d7, d4\n+\tvldr\td2, [pc, #448]\t@ 320 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x320>\n+\tvldr\td3, [pc, #452]\t@ 328 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x328>\n+\tvmla.f64\td1, d6, d7\n+\tvldr\td6, [pc, #452]\t@ 330 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x330>\n+\tvmla.f64\td5, d4, d7\n+\tvldr\td4, [pc, #452]\t@ 338 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x338>\n+\tvmla.f64\td2, d7, d1\n+\tvmla.f64\td3, d7, d5\n+\tvmov.f64\td5, #112\t@ 0x3f800000 1.0\n+\tvmla.f64\td6, d7, d2\n+\tvmla.f64\td4, d7, d3\n+\tvmul.f64\td9, d6, d9\n+\tvdiv.f64\td6, d9, d4\n+\tvpop\t{d8-d12}\n+\tvsub.f64\td6, d5, d6\n+\tvstr\td6, [r4]\n \tpop\t{r4, pc}\n-\tvmul.f64\td16, d0, d0\n-\tvldr\td17, [pc, #404]\t@ 338 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x338>\n-\tvmul.f64\td17, d16, d17\n+\tvmul.f64\td7, d0, d0\n+\tvldr\td6, [pc, #412]\t@ 340 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x340>\n+\tvmul.f64\td6, d7, d6\n \tb.n\t144 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x144>\n-\tvmul.f64\td18, d0, d0\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n-\tvldr\td29, [pc, #392]\t@ 340 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x340>\n+\tvmul.f64\td4, d0, d0\n+\tvmov.f64\td2, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [pc, #400]\t@ 348 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x348>\n \tvmov.f64\td0, #48\t@ 0x41800000 16.0\n-\tvldr\td27, [pc, #392]\t@ 348 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x348>\n-\tvldr\td28, [pc, #396]\t@ 350 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x350>\n-\tvmul.f64\td0, d16, d0\n-\tvdiv.f64\td17, d19, d18\n-\tvldr\td25, [pc, #392]\t@ 358 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x358>\n-\tvldr\td26, [pc, #396]\t@ 360 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x360>\n-\tvldr\td23, [pc, #400]\t@ 368 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x368>\n-\tvldr\td24, [pc, #404]\t@ 370 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x370>\n-\tvrintz.f64\td0, d0\n-\tvldr\td21, [pc, #404]\t@ 378 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x378>\n-\tvldr\td22, [pc, #408]\t@ 380 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x380>\n-\tvldr\td20, [pc, #412]\t@ 388 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x388>\n-\tvldr\td19, [pc, #416]\t@ 390 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x390>\n-\tvldr\td18, [pc, #420]\t@ 398 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x398>\n-\tvldr\td30, [pc, #232]\t@ 2e0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2e0>\n-\tvmul.f64\td0, d0, d30\n-\tvsub.f64\td31, d16, d0\n-\tvadd.f64\td30, d16, d0\n+\tvldr\td3, [pc, #400]\t@ 350 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x350>\n+\tvldr\td7, [pc, #404]\t@ 358 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x358>\n+\tvmul.f64\td0, d8, d0\n+\tvdiv.f64\td10, d2, d4\n+\tvldr\td5, [pc, #400]\t@ 360 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x360>\n+\tvldr\td4, [pc, #404]\t@ 368 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x368>\n+\tvldr\td12, [pc, #408]\t@ 370 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x370>\n+\tvldr\td11, [pc, #412]\t@ 378 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x378>\n+\tvmla.f64\td3, d10, d6\n+\tvadd.f64\td7, d10, d7\n+\tvldr\td6, [pc, #408]\t@ 380 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x380>\n+\tvmla.f64\td4, d7, d10\n+\tvldr\td7, [pc, #408]\t@ 388 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x388>\n+\tvmla.f64\td5, d10, d3\n+\tvmla.f64\td6, d10, d4\n+\tvmla.f64\td7, d10, d5\n+\tvmla.f64\td11, d10, d6\n+\tvmla.f64\td12, d10, d7\n+\tbl\t0 \n+ R_ARM_THM_CALL\ttrunc\n+\tvldr\td7, [pc, #196]\t@ 2d0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x2d0>\n+\tvmul.f64\td0, d0, d7\n+\tvsub.f64\td7, d8, d0\n+\tvadd.f64\td6, d8, d0\n \tvmul.f64\td0, d0, d0\n-\tvfma.f64\td0, d31, d30\n-\tvneg.f64\td0, d0\n-\tvfma.f64\td27, d17, d29\n-\tvadd.f64\td28, d17, d28\n-\tvfma.f64\td26, d17, d28\n-\tvfma.f64\td25, d17, d27\n-\tvfma.f64\td24, d17, d26\n-\tvfma.f64\td23, d17, d25\n-\tvfma.f64\td22, d17, d24\n-\tvfma.f64\td21, d17, d23\n-\tvfma.f64\td19, d17, d22\n-\tvfma.f64\td20, d17, d21\n-\tvmul.f64\td17, d17, d20\n-\tvdiv.f64\td20, d17, d19\n-\tvsub.f64\td18, d18, d20\n-\tvdiv.f64\td9, d18, d16\n+\tvnmla.f64\td0, d6, d7\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmul.f64\td0, d9, d0\n+\tvldr\td7, [pc, #360]\t@ 390 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x390>\n+\tvmla.f64\td7, d10, d12\n+\tvldr\td5, [pc, #360]\t@ 398 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x398>\n+\tvmla.f64\td5, d10, d11\n+\tvldr\td6, [pc, #360]\t@ 3a0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0x3a0>\n+\tvmul.f64\td7, d7, d10\n+\tvdiv.f64\td4, d7, d5\n+\tvsub.f64\td6, d6, d4\n+\tvdiv.f64\td7, d6, d8\n+\tvmul.f64\td0, d7, d0\n \tvstr\td0, [r4]\n \tb.n\tf6 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0+0xf6>\n \tnop\n+\tnop.w\n \t.word\t0x3c5f5815\n \t.word\t0x3e571e70\n \t.word\t0x08eb103e\n \t.word\t0x3fe20dd5\n \t.word\t0xf486ded5\n \t.word\t0x402f7d66\n \t.word\t0x35b8bc02\n \t.word\t0x4021c42c\n \t.word\t0xb0ffcde7\n \t.word\t0x405d6c69\n \t.word\t0xd1c420d0\n \t.word\t0x405087a0\n \t.word\t0xe588749e\n \t.word\t0x4080c972\n+\t.word\t0xc15dc8d7\n+\t.word\t0x409ac030\n+\t.word\t0x21236f6b\n+\t.word\t0x40a00628\n \t.word\t0x86aba462\n \t.word\t0x4072aa29\n+\t.word\t0x3fc90dbd\n+\t.word\t0x40aadebc\n \t.word\t0xeca29d27\n \t.word\t0x4099558e\n \t.word\t0x262b9fa3\n \t.word\t0x408b8f9e\n \t.word\t0x356d1202\n \t.word\t0x40a9b599\n-\t.word\t0xc15dc8d7\n-\t.word\t0x409ac030\n \t.word\t0x7cb10e86\n \t.word\t0x40b10a9e\n-\t.word\t0x21236f6b\n-\t.word\t0x40a00628\n-\t.word\t0x3fc90dbd\n-\t.word\t0x40aadebc\n+\t.word\t0x00000000\n+\t.word\t0x3fb00000\n \t.word\t0x7fd2fc8e\n \t.word\t0x4093395b\n \t.word\t0x7fd35f61\n \t.word\t0x4093395b\n-\t.word\t0x00000000\n-\t.word\t0x3fb00000\n \t.word\t0x0c49ba5e\n \t.word\t0x403a8b02\n+\t...\n \t.word\t0xb7e8ad5e\n \t.word\t0x3c9ffe5a\n \t.word\t0x3ed443e9\n \t.word\t0x400949fb\n \t.word\t0x342fb2de\n \t.word\t0x403799ee\n \t.word\t0x4d365da3\n@@ -227,197 +230,197 @@\n \t.word\t0x3fd38a78\n \t.word\t0x508800db\n \t.word\t0x40048c54\n \t.word\t0x0e2425b8\n \t.word\t0x3fd70fe4\n \t.word\t0x6855f0ad\n \t.word\t0x3ffdf79d\n-\t.word\t0x980a842f\n-\t.word\t0x3fc0199d\n-\t.word\t0x3e122c39\n-\t.word\t0x3fe0e499\n \t.word\t0x8cd6c5b5\n \t.word\t0x3f907844\n \t.word\t0x917d7de7\n \t.word\t0x3faefc42\n+\t.word\t0x3e122c39\n+\t.word\t0x3fe0e499\n+\t.word\t0x980a842f\n+\t.word\t0x3fc0199d\n \t.word\t0x0d71e33c\n \t.word\t0x3f4595fd\n \t.word\t0xa014bad1\n \t.word\t0x3f632147\n \t.word\t0x50429b6d\n \t.word\t0x3fe20dd7\n \n-000003a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>:\n+000003a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0():\n \tpush\t{r4, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d10}\n+\tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3712]\t@ 0xe80\n+\tstr.w\tr0, [ip, #3704]\t@ 0xe78\n \tvcmpe.f64\td0, #0.0\n-\tldr\tr2, [pc, #504]\t@ (5b0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x210>)\n-\tldr\tr3, [pc, #504]\t@ (5b4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x214>)\n+\tldr\tr2, [pc, #504]\t@ (5b8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x210>)\n+\tldr\tr3, [pc, #504]\t@ (5bc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x214>)\n \tsub\tsp, #352\t@ 0x160\n \tadd\tr2, pc\n \tvmrs\tAPSR_nzcv, fpscr\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #348]\t@ 0x15c\n \tmov.w\tr3, #0\n-\tbhi.n\t41e <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x7e>\n+\tbhi.n\t426 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x7e>\n \tmov\tr4, sp\n-\tvldr\td16, [pc, #452]\t@ 598 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n-\tldr\tr3, [pc, #480]\t@ (5b8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x218>)\n+\tvldr\td7, [pc, #452]\t@ 5a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n+\tldr\tr3, [pc, #480]\t@ (5c0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x218>)\n \tmovw\tr2, #5421\t@ 0x152d\n \tmov\tr0, r4\n \tadd\tr3, pc\n-\tvstr\td16, [sp]\n+\tvstr\td7, [sp]\n \tstrd\tr3, r2, [r4, #8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #464]\t@ (5bc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x21c>)\n+\tldr\tr1, [pc, #464]\t@ (5c4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x21c>)\n \tmov\tr0, r4\n \tmovs\tr2, #16\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tldr\tr2, [pc, #448]\t@ (5c0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x220>)\n-\tldr\tr3, [pc, #436]\t@ (5b4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x214>)\n+\tldr\tr2, [pc, #448]\t@ (5c8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x220>)\n+\tldr\tr3, [pc, #436]\t@ (5bc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x214>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #348]\t@ 0x15c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t590 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f0>\n+\tbne.w\t598 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f0>\n \tvmov.f64\td0, d9\n \tadd\tsp, #352\t@ 0x160\n-\tvpop\t{d8-d10}\n+\tvpop\t{d8-d11}\n \tpop\t{r4, pc}\n-\tvmov.f64\td21, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td3, #112\t@ 0x3f800000 1.0\n \tvmov.f64\td8, d0\n-\tvcmpe.f64\td0, d21\n+\tvcmpe.f64\td0, d3\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t4c4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x124>\n-\tvadd.f64\td16, d0, d21\n-\tvmov.f64\td17, #8\t@ 0x40400000 3.0\n-\tvldr\td23, [pc, #356]\t@ 5a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x200>\n-\tvadd.f64\td17, d0, d17\n-\tvdiv.f64\td10, d21, d16\n-\tvsub.f64\td16, d17, d10\n-\tvdiv.f64\td18, d21, d16\n-\tvmul.f64\td19, d18, d17\n-\tvsub.f64\td16, d19, d21\n-\tvmul.f64\td10, d10, d19\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d23\n+\tble.n\t4cc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x124>\n+\tvadd.f64\td7, d0, d3\n+\tvmov.f64\td6, #8\t@ 0x40400000 3.0\n+\tvadd.f64\td6, d0, d6\n+\tvldr\td0, [pc, #352]\t@ 5a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x200>\n+\tvdiv.f64\td10, d3, d7\n+\tvsub.f64\td7, d6, d10\n+\tvdiv.f64\td5, d3, d7\n+\tvmul.f64\td4, d5, d6\n+\tvsub.f64\td7, d4, d3\n+\tvmul.f64\td10, d10, d4\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t4b6 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x116>\n-\tvmov.f64\td19, d17\n+\tbmi.n\t4be <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x116>\n+\tvmov.f64\td4, d6\n \tmovs\tr2, #1\n-\tvmov.f64\td24, #0\t@ 0x40000000 2.0\n+\tvmov.f64\td11, #0\t@ 0x40000000 2.0\n \tadds\tr2, #1\n \tcmp\tr2, #101\t@ 0x65\n-\tbeq.n\t560 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1c0>\n+\tbeq.n\t568 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1c0>\n \tmul.w\tr3, r2, r2\n-\tvadd.f64\td17, d17, d24\n+\tvadd.f64\td6, d6, d11\n \tnegs\tr3, r3\n \tvmov\ts15, r3\n-\tvcvt.f64.s32\td16, s15\n-\tvmov.f64\td22, d17\n-\tvdiv.f64\td20, d16, d19\n-\tvfma.f64\td22, d18, d16\n-\tvdiv.f64\td18, d21, d22\n-\tvadd.f64\td19, d17, d20\n-\tvmul.f64\td20, d18, d19\n-\tvsub.f64\td16, d20, d21\n-\tvmul.f64\td10, d10, d20\n-\tvabs.f64\td16, d16\n-\tvcmpe.f64\td16, d23\n+\tvcvt.f64.s32\td7, s15\n+\tvmov.f64\td1, d6\n+\tvdiv.f64\td2, d7, d4\n+\tvmla.f64\td1, d5, d7\n+\tvdiv.f64\td5, d3, d1\n+\tvadd.f64\td4, d6, d2\n+\tvmul.f64\td7, d5, d4\n+\tvmul.f64\td10, d10, d7\n+\tvsub.f64\td7, d7, d3\n+\tvabs.f64\td7, d7\n+\tvcmpe.f64\td7, d0\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t470 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0xd0>\n+\tbpl.n\t478 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0xd0>\n \tvneg.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvmul.f64\td9, d0, d10\n-\tb.n\t3fc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n-\tvldr\td9, [pc, #224]\t@ 5a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x208>\n+\tb.n\t404 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n+\tvldr\td9, [pc, #224]\t@ 5b0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x208>\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td19, [pc, #208]\t@ 5a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x200>\n-\tvabs.f64\td16, d8\n-\tvneg.f64\td17, d8\n+\tvldr\td4, [pc, #208]\t@ 5a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x200>\n+\tvabs.f64\td7, d8\n+\tvneg.f64\td6, d8\n \tvsub.f64\td9, d8, d9\n \tvsub.f64\td9, d9, d0\n-\tvabs.f64\td18, d9\n-\tvmul.f64\td18, d18, d19\n-\tvcmpe.f64\td18, d16\n+\tvabs.f64\td5, d9\n+\tvmul.f64\td5, d5, d4\n+\tvcmpe.f64\td5, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbgt.n\t3fc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n+\tbgt.n\t404 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n \tmovs\tr3, #1\n-\tb.n\t52a <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x18a>\n-\tvmov\ts15, r3\n-\tvmul.f64\td16, d8, d17\n-\tvcvt.f64.s32\td17, s15\n-\tvdiv.f64\td18, d16, d17\n-\tvdiv.f64\td16, d18, d17\n-\tvneg.f64\td17, d18\n-\tvadd.f64\td9, d9, d16\n-\tvabs.f64\td16, d16\n-\tvabs.f64\td18, d9\n-\tvmul.f64\td18, d18, d19\n-\tvcmpe.f64\td16, d18\n+\tb.n\t532 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x18a>\n+\tvmul.f64\td7, d8, d6\n+\tvmov\ts13, r3\n+\tvcvt.f64.s32\td6, s13\n+\tvdiv.f64\td5, d7, d6\n+\tvdiv.f64\td7, d5, d6\n+\tvneg.f64\td6, d5\n+\tvadd.f64\td9, d9, d7\n+\tvabs.f64\td7, d7\n+\tvabs.f64\td5, d9\n+\tvmul.f64\td5, d5, d4\n+\tvcmpe.f64\td7, d5\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t3fc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n+\tbmi.w\t404 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n \tadds\tr3, #1\n \tcmp\tr3, #101\t@ 0x65\n-\tbne.n\t4f6 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x156>\n+\tbne.n\t4fe <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x156>\n \tmov\tr4, sp\n-\tvldr\td16, [pc, #100]\t@ 598 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n-\tldr\tr3, [pc, #140]\t@ (5c4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x224>)\n+\tvldr\td7, [pc, #100]\t@ 5a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n+\tldr\tr3, [pc, #140]\t@ (5cc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x224>)\n \tmov\tr0, r4\n \tmovw\tr2, #5465\t@ 0x1559\n \tadd\tr3, pc\n-\tvstr\td16, [sp]\n+\tvstr\td7, [sp]\n \tstrd\tr3, r2, [r4, #8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #120]\t@ (5c8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x228>)\n+\tldr\tr1, [pc, #120]\t@ (5d0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x228>)\n \tmov\tr0, r4\n \tmovs\tr2, #28\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tb.n\t3fc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n+\tb.n\t404 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n \tmov\tr4, sp\n-\tvldr\td16, [pc, #52]\t@ 598 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n-\tldr\tr3, [pc, #100]\t@ (5cc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x22c>)\n+\tvldr\td7, [pc, #52]\t@ 5a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x1f8>\n+\tldr\tr3, [pc, #100]\t@ (5d4 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x22c>)\n \tmov\tr0, r4\n \tmovw\tr2, #5443\t@ 0x1543\n \tadd\tr3, pc\n-\tvstr\td16, [sp]\n+\tvstr\td7, [sp]\n \tstrd\tr3, r2, [r4, #8]\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #80]\t@ (5d0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x230>)\n+\tldr\tr1, [pc, #80]\t@ (5d8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x230>)\n \tmov\tr0, r4\n \tmovs\tr2, #40\t@ 0x28\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tb.n\t3fc <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n+\tb.n\t404 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0+0x5c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop.w\n \t.word\t0x00000080\n \t.word\t0x00000006\n \t.word\t0xa4f8e0b4\n \t.word\t0x3d30e374\n@@ -438,2424 +441,2482 @@\n \t.word\t0x00000072\n R_ARM_REL32\t.LC3\n \t.word\t0x0000005a\n R_ARM_REL32\t.LC0\n \t.word\t0x0000004a\n R_ARM_REL32\t.LC2\n \n-000005d4 <__gridxc_xwpbe_MOD_exer.isra.0>:\n+000005dc <__gridxc_xwpbe_MOD_exer.isra.0>:\n __gridxc_xwpbe_MOD_exer.isra.0():\n \tpush\t{lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d9}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n-\tvldr\td17, [pc, #176]\t@ 698 <__gridxc_xwpbe_MOD_exer.isra.0+0xc4>\n+\tvldr\td6, [pc, #176]\t@ 6a0 <__gridxc_xwpbe_MOD_exer.isra.0+0xc4>\n \tsub\tsp, #20\n-\tldr\tr2, [pc, #184]\t@ (6a8 <__gridxc_xwpbe_MOD_exer.isra.0+0xd4>)\n-\tldr\tr3, [pc, #188]\t@ (6ac <__gridxc_xwpbe_MOD_exer.isra.0+0xd8>)\n-\tvcmpe.f64\td0, d17\n+\tldr\tr2, [pc, #184]\t@ (6b0 <__gridxc_xwpbe_MOD_exer.isra.0+0xd4>)\n+\tldr\tr3, [pc, #188]\t@ (6b4 <__gridxc_xwpbe_MOD_exer.isra.0+0xd8>)\n+\tvcmpe.f64\td0, d6\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tvmrs\tAPSR_nzcv, fpscr\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [sp, #12]\n \tmov.w\tr3, #0\n-\tbmi.n\t668 <__gridxc_xwpbe_MOD_exer.isra.0+0x94>\n-\tvldr\td18, [pc, #152]\t@ 6a0 <__gridxc_xwpbe_MOD_exer.isra.0+0xcc>\n-\tvmul.f64\td17, d0, d0\n-\tvmov.f64\td24, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td20, #104\t@ 0x3f400000 0.750\n-\tvmov.f64\td22, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td16, d0, d18\n-\tvsqrt.f64\td23, d16\n-\tvmul.f64\td19, d16, d17\n-\tvsqrt.f64\td21, d19\n-\tvmul.f64\td17, d19, d17\n-\tvsqrt.f64\td19, d17\n-\tvdiv.f64\td0, d24, d23\n-\tvdiv.f64\td16, d22, d21\n-\tvdiv.f64\td17, d20, d19\n-\tvadd.f64\td0, d0, d17\n-\tvsub.f64\td0, d0, d16\n-\tvmul.f64\td0, d0, d18\n-\tldr\tr2, [pc, #100]\t@ (6b0 <__gridxc_xwpbe_MOD_exer.isra.0+0xdc>)\n-\tldr\tr3, [pc, #92]\t@ (6ac <__gridxc_xwpbe_MOD_exer.isra.0+0xd8>)\n+\tbmi.n\t670 <__gridxc_xwpbe_MOD_exer.isra.0+0x94>\n+\tvldr\td5, [pc, #152]\t@ 6a8 <__gridxc_xwpbe_MOD_exer.isra.0+0xcc>\n+\tvmul.f64\td6, d0, d0\n+\tvmov.f64\td3, #104\t@ 0x3f400000 0.750\n+\tvmov.f64\td1, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td7, d0, d5\n+\tvsqrt.f64\td8, d7\n+\tvmul.f64\td4, d7, d6\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvsqrt.f64\td2, d4\n+\tvmul.f64\td6, d4, d6\n+\tvsqrt.f64\td4, d6\n+\tvdiv.f64\td0, d7, d8\n+\tvdiv.f64\td7, d1, d2\n+\tvdiv.f64\td6, d3, d4\n+\tvadd.f64\td0, d0, d6\n+\tvsub.f64\td0, d0, d7\n+\tvmul.f64\td0, d0, d5\n+\tldr\tr2, [pc, #100]\t@ (6b8 <__gridxc_xwpbe_MOD_exer.isra.0+0xdc>)\n+\tldr\tr3, [pc, #92]\t@ (6b4 <__gridxc_xwpbe_MOD_exer.isra.0+0xd8>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #12]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t690 <__gridxc_xwpbe_MOD_exer.isra.0+0xbc>\n+\tbne.n\t698 <__gridxc_xwpbe_MOD_exer.isra.0+0xbc>\n \tadd\tsp, #20\n \tvpop\t{d8-d9}\n \tldr.w\tpc, [sp], #4\n \tvsqrt.f64\td9, d0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tmov\tr0, sp\n \tvmov.f64\td8, d0\n \tvmov.f64\td0, d9\n \tbl\t0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0>\n-\tvldr\td16, [sp]\n-\tvldr\td17, [pc, #28]\t@ 6a0 <__gridxc_xwpbe_MOD_exer.isra.0+0xcc>\n-\tvmul.f64\td16, d16, d17\n-\tvmul.f64\td0, d16, d8\n-\tb.n\t64a <__gridxc_xwpbe_MOD_exer.isra.0+0x76>\n+\tvldr\td7, [sp]\n+\tvldr\td6, [pc, #28]\t@ 6a8 <__gridxc_xwpbe_MOD_exer.isra.0+0xcc>\n+\tvmul.f64\td7, d7, d6\n+\tvmul.f64\td0, d7, d8\n+\tb.n\t652 <__gridxc_xwpbe_MOD_exer.isra.0+0x76>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tnop.w\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x54442d18\n \t.word\t0x400921fb\n \t.word\t0x000000b0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x0000005e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-000006b4 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0>:\n+000006bc <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0>:\n __gridxc_xwpbe_MOD_d2exeirhondrho.isra.0():\n \tpush\t{r3, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d13}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n-\tvldr\td16, [pc, #128]\t@ 748 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x94>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n+\tvldr\td7, [pc, #128]\t@ 750 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x94>\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n \tvmov.f64\td8, d0\n-\tvmov.f64\td13, d1\n-\tvdiv.f64\td12, d17, d0\n-\tvmov.f64\td11, d2\n-\tvcmpe.f64\td0, d16\n-\tvmov.f64\td10, d3\n+\tvmov.f64\td9, d1\n+\tvdiv.f64\td12, d6, d0\n+\tvmov.f64\td13, d2\n+\tvcmpe.f64\td0, d7\n+\tvmov.f64\td11, d3\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t732 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x7e>\n-\tvldr\td19, [pc, #96]\t@ 750 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x9c>\n-\tvldr\td16, [pc, #100]\t@ 758 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xa4>\n-\tvldr\td17, [pc, #104]\t@ 760 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xac>\n-\tvadd.f64\td19, d0, d19\n-\tvldr\td18, [pc, #104]\t@ 768 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xb4>\n-\tvadd.f64\td16, d0, d16\n-\tvfma.f64\td17, d0, d19\n-\tvfma.f64\td18, d0, d16\n-\tvmul.f64\td17, d12, d17\n-\tvdiv.f64\td16, d17, d18\n-\tvmul.f64\td2, d13, d11\n+\tbmi.n\t73a <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x7e>\n+\tvldr\td5, [pc, #96]\t@ 758 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x9c>\n+\tvldr\td7, [pc, #100]\t@ 760 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xa4>\n+\tvldr\td6, [pc, #104]\t@ 768 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xac>\n+\tvadd.f64\td5, d0, d5\n+\tvadd.f64\td7, d0, d7\n+\tvmla.f64\td6, d5, d0\n+\tvldr\td5, [pc, #96]\t@ 770 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0xb4>\n+\tvmla.f64\td5, d7, d0\n+\tvmul.f64\td6, d6, d12\n+\tvdiv.f64\td7, d6, d5\n+\tvmul.f64\td2, d9, d13\n \tvmul.f64\td8, d8, d8\n-\tvsub.f64\td16, d16, d12\n+\tvsub.f64\td7, d7, d12\n \tvdiv.f64\td0, d2, d8\n-\tvadd.f64\td2, d2, d10\n+\tvadd.f64\td2, d2, d11\n \tvpop\t{d8-d13}\n-\tvfma.f64\td0, d16, d2\n+\tvmla.f64\td0, d7, d2\n \tpop\t{r3, pc}\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td9, d0\n+\tvmov.f64\td10, d0\n \tvmov.f64\td0, d8\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvmul.f64\td16, d9, d0\n-\tb.n\t714 <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x60>\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td7, d10, d0\n+\tb.n\t71c <__gridxc_xwpbe_MOD_d2exeirhondrho.isra.0+0x60>\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \n-00000770 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0>:\n+00000778 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0>:\n __gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0():\n \tpush\t{r3, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d11}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4056]\t@ 0xfd8\n-\tvldr\td16, [pc, #116]\t@ 7f8 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x88>\n+\tvldr\td7, [pc, #116]\t@ 800 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x88>\n \tvmov.f64\td8, d0\n \tvmov.f64\td9, d1\n \tvmov.f64\td10, d2\n-\tvcmpe.f64\td0, d16\n+\tvcmpe.f64\td0, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.n\t7e2 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x72>\n-\tvldr\td19, [pc, #96]\t@ 800 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x90>\n-\tvldr\td16, [pc, #100]\t@ 808 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x98>\n-\tvldr\td18, [pc, #104]\t@ 810 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0xa0>\n-\tvadd.f64\td19, d0, d19\n-\tvldr\td17, [pc, #104]\t@ 818 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0xa8>\n-\tvadd.f64\td18, d0, d18\n-\tvfma.f64\td16, d0, d19\n-\tvfma.f64\td17, d0, d18\n-\tvdiv.f64\td18, d16, d0\n-\tvdiv.f64\td11, d18, d17\n+\tbmi.n\t7ea <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x72>\n+\tvldr\td4, [pc, #96]\t@ 808 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x90>\n+\tvldr\td7, [pc, #100]\t@ 810 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x98>\n+\tvldr\td5, [pc, #104]\t@ 818 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0xa0>\n+\tvadd.f64\td4, d0, d4\n+\tvldr\td6, [pc, #104]\t@ 820 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0xa8>\n+\tvadd.f64\td5, d0, d5\n+\tvmla.f64\td7, d4, d0\n+\tvmla.f64\td6, d5, d0\n+\tvdiv.f64\td5, d7, d0\n+\tvdiv.f64\td11, d5, d6\n \tvmul.f64\td9, d9, d9\n-\tvmul.f64\td17, d8, d8\n+\tvmul.f64\td6, d8, d8\n \tvadd.f64\td10, d9, d10\n-\tvfms.f64\td9, d10, d8\n-\tvdiv.f64\td0, d9, d17\n-\tvfma.f64\td0, d10, d11\n+\tvmls.f64\td9, d10, d8\n+\tvdiv.f64\td0, d9, d6\n+\tvmla.f64\td0, d10, d11\n \tvpop\t{d8-d11}\n \tpop\t{r3, pc}\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvmov.f64\td11, d0\n \tvmov.f64\td0, d8\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n \tvmul.f64\td11, d11, d0\n-\tb.n\t7c4 <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x54>\n+\tb.n\t7cc <__gridxc_xwpbe_MOD_d2exeindrhondrho.isra.0+0x54>\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \n-00000820 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>:\n+00000828 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3456]\t@ 0xd80\n-\tvmul.f64\td9, d1, d1\n-\tvldr\td17, [pc, #1008]\t@ c28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x408>\n-\tvldr\td10, [pc, #1012]\t@ c30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x410>\n+\tvmul.f64\td10, d1, d1\n+\tvldr\td7, [pc, #920]\t@ bd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3b0>\n+\tvldr\td11, [pc, #924]\t@ be0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3b8>\n+\tvmov.f64\td13, #80\t@ 0x3e800000 0.250\n+\tvmov.f64\td9, d0\n \tsub.w\tsp, sp, #560\t@ 0x230\n-\tvmov.f64\td5, #80\t@ 0x3e800000 0.250\n-\tvmov.f64\td15, d0\n+\tvmov.f64\td12, d1\n \tmov\tr5, r0\n+\tvmul.f64\td7, d10, d7\n+\tvmul.f64\td11, d0, d11\n \tmov\tr6, r1\n-\tvmul.f64\td16, d9, d17\n-\tvmul.f64\td10, d0, d10\n \tmov\tr4, r2\n-\tvstr\td1, [sp]\n-\tvstr\td5, [sp, #16]\n-\tvmul.f64\td12, d9, d9\n+\tvstr\td1, [sp, #88]\t@ 0x58\n \tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n-\tvstr\td16, [sp, #256]\t@ 0x100\n-\tvmul.f64\td16, d16, d5\n-\tvmov.f64\td0, d10\n-\tvmov.f64\td13, d16\n-\tvstr\td16, [sp, #264]\t@ 0x108\n+\tvmul.f64\td4, d7, d13\n+\tvmov.f64\td0, d11\n+\tvstr\td7, [sp, #320]\t@ 0x140\n+\tvstr\td4, [sp, #96]\t@ 0x60\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n+\tvmul.f64\td2, d9, d9\n+\tvmul.f64\td3, d0, d0\n+\tvldr\td4, [pc, #860]\t@ be8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3c0>\n+\tvmul.f64\td7, d11, d0\n+\tvstr\td0, [sp, #328]\t@ 0x148\n \tldr\tr3, [sp, #648]\t@ 0x288\n-\tvmul.f64\td24, d15, d15\n-\tvldr\td19, [pc, #944]\t@ c38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x418>\n-\tvldr\td18, [pc, #948]\t@ c40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x420>\n-\tvmul.f64\td16, d0, d0\n-\tvmul.f64\td20, d10, d0\n-\tvldr\td1, [sp]\n-\tvldr\td17, [r3]\n-\tvmul.f64\td25, d12, d19\n-\tvmul.f64\td21, d24, d24\n-\tvstr\td24, [sp, #144]\t@ 0x90\n-\tvdiv.f64\td22, d8, d24\n-\tvmul.f64\td10, d10, d16\n-\tvmul.f64\td14, d17, d17\n-\tvldr\td27, [pc, #912]\t@ c48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x428>\n-\tvdiv.f64\td28, d8, d20\n-\tvldr\td26, [pc, #912]\t@ c50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x430>\n-\tvdiv.f64\td24, d8, d21\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvmul.f64\td27, d9, d27\n-\tvstr\td21, [sp, #128]\t@ 0x80\n-\tvmul.f64\td19, d14, d14\n-\tvldr\td23, [pc, #896]\t@ c58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x438>\n-\tvdiv.f64\td30, d8, d10\n-\tvstr\td25, [sp, #336]\t@ 0x150\n-\tvdiv.f64\td16, d8, d16\n-\tvstr\td26, [sp, #104]\t@ 0x68\n-\tvmul.f64\td27, d27, d12\n-\tvmul.f64\td23, d12, d23\n-\tvmul.f64\td29, d17, d19\n-\tvmul.f64\td17, d21, d21\n-\tvstr\td19, [sp, #120]\t@ 0x78\n-\tvstr\td0, [sp, #272]\t@ 0x110\n-\tvmov.f64\td0, d15\n-\tvstr\td23, [sp, #304]\t@ 0x130\n-\tvdiv.f64\td11, d18, d17\n-\tvstr\td17, [sp, #392]\t@ 0x188\n-\tvmul.f64\td17, d21, d15\n-\tvmul.f64\td21, d25, d26\n-\tvstr\td29, [sp, #376]\t@ 0x178\n-\tvstr\td27, [sp, #384]\t@ 0x180\n-\tvdiv.f64\td18, d8, d17\n-\tvmul.f64\td17, d14, d19\n-\tvstr\td21, [sp, #344]\t@ 0x158\n-\tvstr\td17, [sp, #400]\t@ 0x190\n-\tvstr\td22, [sp, #296]\t@ 0x128\n-\tvstr\td28, [sp, #320]\t@ 0x140\n-\tvmul.f64\td7, d24, d19\n-\tvstr\td24, [sp, #328]\t@ 0x148\n-\tvstr\td30, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td7, d7, d28\n-\tvstr\td16, [sp, #288]\t@ 0x120\n-\tvstr\td7, [sp, #88]\t@ 0x58\n-\tvmul.f64\td11, d11, d17\n-\tvmul.f64\td17, d12, d1\n-\tvmov.f64\td19, d17\n-\tvstr\td17, [sp, #136]\t@ 0x88\n-\tvldr\td17, [pc, #764]\t@ c60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x440>\n-\tvmul.f64\td10, d18, d29\n-\tvstr\td18, [sp, #368]\t@ 0x170\n-\tvldr\td18, [pc, #960]\t@ d30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x510>\n-\tvmul.f64\td19, d19, d17\n-\tvmov.f64\td17, d8\n-\tvfma.f64\td17, d27, d11\n-\tvmul.f64\td10, d10, d30\n-\tvmul.f64\td18, d19, d18\n-\tvstr\td19, [sp, #352]\t@ 0x160\n-\tvfma.f64\td17, d7, d21\n-\tvmul.f64\td19, d16, d22\n-\tvmul.f64\td21, d23, d26\n-\tvmul.f64\td23, d22, d14\n-\tvstr\td18, [sp, #360]\t@ 0x168\n-\tvfma.f64\td17, d18, d10\n-\tvstr\td19, [sp, #48]\t@ 0x30\n-\tvmul.f64\td19, d19, d14\n-\tvmul.f64\td29, d21, d7\n-\tvstr\td21, [sp, #312]\t@ 0x138\n-\tvstr\td23, [sp, #96]\t@ 0x60\n-\tvfma.f64\td29, d13, d19\n-\tvstr\td19, [sp, #8]\n-\tvmov.f64\td13, d16\n-\tvmov.f64\td18, d17\n-\tvstr\td17, [sp, #64]\t@ 0x40\n-\tvldr\td17, [pc, #796]\t@ ce8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4c8>\n-\tvdiv.f64\td31, d8, d18\n-\tvmul.f64\td17, d23, d17\n-\tvstr\td29, [sp, #32]\n-\tvmov.f64\td18, #2\t@ 0x40100000 2.250\n-\tvldr\td5, [sp, #16]\n-\tvmul.f64\td18, d29, d18\n-\tvmul.f64\td20, d16, d5\n+\tvmul.f64\td15, d2, d2\n+\tvmul.f64\td11, d11, d3\n+\tvdiv.f64\td1, d8, d7\n+\tvldr\td5, [pc, #844]\t@ bf0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3c8>\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvldr\td7, [r3]\n+\tvmul.f64\td6, d15, d15\n+\tvmul.f64\td5, d10, d5\n+\tvdiv.f64\td0, d8, d11\n+\tvstr\td3, [sp, #336]\t@ 0x150\n+\tvdiv.f64\td14, d8, d15\n+\tvdiv.f64\td3, d8, d3\n+\tvstr\td6, [sp, #424]\t@ 0x1a8\n+\tvdiv.f64\td6, d4, d6\n+\tvmul.f64\td4, d15, d9\n+\tvdiv.f64\td11, d8, d4\n+\tvmul.f64\td4, d7, d7\n+\tvstr\td1, [sp, #376]\t@ 0x178\n+\tvstr\td0, [sp, #296]\t@ 0x128\n+\tvstr\td14, [sp, #384]\t@ 0x180\n+\tvstr\td11, [sp, #72]\t@ 0x48\n+\tvmul.f64\td11, d10, d10\n+\tvmul.f64\td5, d5, d11\n+\tvstr\td11, [sp, #8]\n+\tvstr\td5, [sp, #128]\t@ 0x80\n+\tvmul.f64\td5, d4, d4\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td5, [sp, #392]\t@ 0x188\n+\tvstr\td7, [sp, #120]\t@ 0x78\n+\tvmul.f64\td7, d4, d5\n+\tvmul.f64\td6, d6, d7\n+\tvstr\td7, [sp, #432]\t@ 0x1b0\n+\tvldr\td7, [pc, #736]\t@ bf8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3d0>\n+\tvmul.f64\td7, d11, d7\n+\tvstr\td6, [sp, #256]\t@ 0x100\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td7, d14, d5\n+\tvmul.f64\td14, d11, d12\n+\tvmul.f64\td5, d7, d1\n+\tvldr\td7, [pc, #716]\t@ c00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x3d8>\n+\tvmov.f64\td1, d14\n+\tvstr\td14, [sp, #240]\t@ 0xf0\n+\tvldr\td14, [pc, #920]\t@ cd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4b0>\n+\tvmul.f64\td1, d1, d7\n+\tvdiv.f64\td7, d8, d2\n+\tvldr\td2, [sp, #128]\t@ 0x80\n+\tvmov.f64\td11, d1\n+\tvstr\td1, [sp, #408]\t@ 0x198\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvmov.f64\td12, d7\n+\tvstr\td7, [sp, #352]\t@ 0x160\n+\tvmov.f64\td7, d8\n+\tvmla.f64\td7, d2, d6\n+\tvmul.f64\td6, d1, d14\n+\tvldr\td2, [sp, #120]\t@ 0x78\n+\tvmla.f64\td7, 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[sp]\n-\tvadd.f64\td0, d0, d8\n-\tvldr\td19, [sp, #32]\n-\tvmul.f64\td26, d16, d16\n-\tvldr\td16, [sp, #112]\t@ 0x70\n-\tvmul.f64\td1, d9, d18\n-\tvldr\td7, [sp, #192]\t@ 0xc0\n-\tvldr\td28, [pc, #168]\t@ ca8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x488>\n-\tvldr\td17, [sp, #16]\n-\tvdiv.f64\td2, d27, d26\n-\tvldr\td27, [pc, #164]\t@ cb0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x490>\n-\tvmul.f64\td26, d16, d19\n-\tvldr\td16, [sp, #24]\n-\tvldr\td19, [sp, #104]\t@ 0x68\n-\tvmul.f64\td28, d18, d28\n-\tvmul.f64\td27, d1, d27\n-\tb.n\td70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x550>\n+\tvldr\td7, [pc, #248]\t@ c50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x428>\n+\tvmul.f64\td7, d6, d7\n+\tvmov.f64\td6, #96\t@ 0x3f000000 0.5\n+\tvstr\td7, [sp, #208]\t@ 0xd0\n+\tvldr\td7, [pc, #312]\t@ ca0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x478>\n+\tvstr\td5, [sp, #40]\t@ 0x28\n+\tvmov.f64\td5, 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<__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4e8>\n \tnop.w\n \t.word\t0x9470e5c6\n \t.word\t0x3f841059\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0xaefb2aae\n-\t.word\t0x3fc7fe08\n \t.word\t0x63e07ae3\n \t.word\t0x3f52b04b\n \t.word\t0x9d1cdbd9\n \t.word\t0x3f41c6a9\n-\t.word\t0x00000000\n-\t.word\t0x3fb00000\n-\t.word\t0x26d12521\n-\t.word\t0x3fa508e2\n+\t.word\t0xaefb2aae\n+\t.word\t0x3fc7fe08\n \t.word\t0xd2493883\n \t.word\t0x3f53cbb9\n+\t.word\t0x26d12521\n+\t.word\t0x3fa508e2\n \t.word\t0x0f94a0b7\n \t.word\t0xbffa4852\n \t.word\t0x8d84e354\n \t.word\t0x3fe27ddb\n \t.word\t0x1ff9d571\n \t.word\t0x3ff5eb4b\n+\t.word\t0xe03dc2d9\n+\t.word\t0x4019e6cb\n \t.word\t0x181a38ac\n \t.word\t0x3fe0304c\n \t.word\t0xb9f05136\n \t.word\t0x3fdeb2b8\n \t.word\t0x1c71c71c\n \t.word\t0x3fec71c7\n \t.word\t0x77bd9591\n \t.word\t0xbfb3c464\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n-\t.word\t0x9470e5c6\n-\t.word\t0x3f741059\n \t.word\t0x26d12521\n \t.word\t0x3f8508e2\n-\t.word\t0xfe791dd3\n-\t.word\t0xbfe7a245\n-\t.word\t0xdc766309\n-\t.word\t0xbfc7ca11\n-\t.word\t0x2c4fea23\n-\t.word\t0x3fe04201\n+\t.word\t0x9470e5c6\n+\t.word\t0x3f741059\n \t.word\t0x6bab49c6\n \t.word\t0x3f6aa9fe\n+\t.word\t0xdc766309\n+\t.word\t0xbfc7ca11\n \t.word\t0xaefb2aae\n \t.word\t0x3fa7fe08\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fe04201\n \t.word\t0x46db86a4\n \t.word\t0x3f28bea8\n \t.word\t0x97d453e4\n \t.word\t0x3fef7e15\n+\t.word\t0xfe791dd3\n+\t.word\t0xbfe7a245\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n-\t.word\t0x949a5658\n-\t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n+\t.word\t0x949a5658\n+\t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \t.word\t0x5dae292a\n \t.word\t0x408b6574\n \t.word\t0x63e07ae3\n \t.word\t0x3f82b04b\n \t.word\t0x00000000\n \t.word\t0x3fb00000\n \t.word\t0x00000000\n \t.word\t0x3fa00000\n-\t.word\t0x2e9d68cd\n-\t.word\t0x403d9bdb\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n-\t.word\t0x55555555\n-\t.word\t0x3fe55555\n+\t.word\t0x2e9d68cd\n+\t.word\t0x403d9bdb\n \t.word\t0xfc2dd756\n \t.word\t0x4048ac8b\n+\t.word\t0x55555555\n+\t.word\t0x3fe55555\n \t.word\t0xc9be45de\n \t.word\t0x4033bd3c\n-\t.word\t0xe03dc2d9\n-\t.word\t0x4019e6cb\n-\t.word\t0x54a28591\n-\t.word\t0x40136d19\n-\tvldr\td31, [sp, #152]\t@ 0x98\n-\tvldr\td3, [pc, #-192]\t@ cb8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x498>\n-\tvfma.f64\td26, d16, d19\n-\tvldr\td16, [sp, #8]\n-\tvldr\td20, [sp, #144]\t@ 0x90\n-\tvmul.f64\td30, d27, d7\n-\tvldr\td27, [pc, #-204]\t@ cc0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4a0>\n-\tvfma.f64\td30, d16, d28\n-\tvldr\td28, [pc, #-204]\t@ cc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4a8>\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvfma.f64\td26, d17, d27\n-\tvldr\td27, [pc, #-208]\t@ cd0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4b0>\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvldr\td29, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td27, d16, d27\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvfma.f64\td26, d0, d28\n-\tvldr\td28, [pc, #-224]\t@ cd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4b8>\n-\tvldr\td24, [sp, #168]\t@ 0xa8\n-\tvldr\td21, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td28, d1, d28\n-\tvmul.f64\td27, d27, d11\n-\tvmul.f64\td11, d16, d20\n-\tvldr\td19, [sp, #184]\t@ 0xb8\n-\tvldr\td23, [sp, #200]\t@ 0xc8\n-\tvldr\td6, [sp, #216]\t@ 0xd8\n-\tvfma.f64\td27, d7, d28\n-\tvldr\td28, [pc, #-256]\t@ ce0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4c0>\n-\tvmul.f64\td3, d26, d3\n-\tvldr\td25, [sp, #232]\t@ 0xe8\n+\tvldr\td11, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td7, d4, d2\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvstr\td2, [sp, #288]\t@ 0x120\n+\tvmul.f64\td6, d1, d11\n+\tvstr\td4, [sp, #280]\t@ 0x118\n+\tvmul.f64\td5, d12, d3\n+\tvstr\td7, [sp, #544]\t@ 0x220\n+\tvstr\td1, [sp, #272]\t@ 0x110\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvmul.f64\td7, d7, d6\n+\tvstr\td6, [sp, #216]\t@ 0xd8\n+\tvstr\td5, [sp, #536]\t@ 0x218\n+\tvmul.f64\td0, d5, d7\n+\tvstr\td7, [sp, #224]\t@ 0xe0\n+\tbl\t0 \n+ R_ARM_THM_CALL\tlog\n+\tvldr\td7, [sp, #136]\t@ 0x88\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvadd.f64\td0, d0, d8\n+\tvldr\td1, [sp, #88]\t@ 0x58\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [sp, #192]\t@ 0xc0\n+\tvldr\td2, [sp, #24]\n+\tvmul.f64\td4, d10, d1\n+\tvldr\td3, [sp, #16]\n+\tvdiv.f64\td8, d6, d7\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvldr\td7, [sp, #208]\t@ 0xd0\n+\tvstr\td4, [sp, #552]\t@ 0x228\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #32]\n+\tvmla.f64\td7, d6, d5\n+\tvldr\td6, [pc, #-316]\t@ c58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x430>\n+\tvldr\td5, [pc, #-312]\t@ c60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x438>\n+\tvmul.f64\td6, d4, d6\n+\tvmul.f64\td5, d1, d5\n+\tvmul.f64\td6, d6, d2\n+\tvmla.f64\td6, d5, d3\n \tvldr\td5, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td22, d12, d28\n-\tvfma.f64\td27, d10, d22\n-\tvadd.f64\td22, d18, d18\n-\tvldr\td10, [pc, #-276]\t@ ce8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4c8>\n-\tvnmul.f64\td11, d2, d11\n-\tvldr\td18, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td22, d22, d16\n-\tvmul.f64\td10, d14, d10\n-\tvmov.f64\td12, d27\n-\tvmov.f64\td27, #2\t@ 0x40100000 2.250\n-\tvmul.f64\td22, d22, d31\n-\tvmul.f64\td10, d10, d13\n-\tvmul.f64\td27, d30, d27\n-\tvfma.f64\td22, d17, d27\n-\tvldr\td17, [sp, #80]\t@ 0x50\n-\tvmul.f64\td4, d17, d22\n-\tvldr\td17, [sp, #88]\t@ 0x58\n-\tvldr\td22, [r5]\n-\tvfms.f64\td22, d17, d3\n-\tvldr\td17, [sp, #208]\t@ 0xd0\n-\tvstr\td22, [r5]\n-\tvmul.f64\td22, d12, d10\n-\tvfma.f64\td4, d22, d11\n-\tvldr\td22, [pc, #-348]\t@ cf0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4d0>\n-\tvcmpe.f64\td17, d22\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t143c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xc1c>\n-\tvldr\td26, [pc, #-356]\t@ cf8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4d8>\n-\tvldr\td27, [pc, #-344]\t@ d08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4e8>\n-\tvldr\td22, [pc, #-356]\t@ d00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4e0>\n-\tvadd.f64\td26, d17, d26\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvadd.f64\td27, d17, d27\n-\tvfma.f64\td22, d17, d26\n-\tvldr\td26, [pc, #-360]\t@ d10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4f0>\n-\tvfma.f64\td26, d17, d27\n-\tvmul.f64\td22, d16, d22\n-\tvdiv.f64\td0, d22, d26\n-\tvldr\td27, [sp, #40]\t@ 0x28\n-\tvmul.f64\td25, d25, d25\n-\tvldr\td13, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td21, d24, d21\n-\tvldr\td26, [sp, #296]\t@ 0x128\n-\tvadd.f64\td5, d5, d5\n-\tvsub.f64\td27, d0, d27\n-\tvldr\td28, [sp, #312]\t@ 0x138\n-\tvldr\td0, [sp, #344]\t@ 0x158\n-\tvmul.f64\td26, d26, d13\n-\tvldr\td16, [sp, #392]\t@ 0x188\n-\tvstr\td27, [sp, #144]\t@ 0x90\n-\tvldr\td27, [sp, #488]\t@ 0x1e8\n-\tvmul.f64\td22, d16, d15\n-\tvstr\td26, [sp, #136]\t@ 0x88\n-\tvmov.f64\td26, #16\t@ 0x40800000 4.0\n-\tvldr\td16, [sp, #264]\t@ 0x108\n-\tvmul.f64\td15, d24, d15\n-\tvmul.f64\td28, d28, d26\n-\tvmul.f64\td0, d0, d26\n-\tvmul.f64\td27, d27, d26\n-\tvmul.f64\td26, d24, d26\n-\tvadd.f64\td8, d16, d16\n-\tvstr\td0, [sp, #152]\t@ 0x98\n-\tvstr\td27, [sp, #160]\t@ 0xa0\n-\tvdiv.f64\td27, d26, d9\n-\tvldr\td0, [sp, #280]\t@ 0x118\n-\tvldr\td9, [sp, #64]\t@ 0x40\n-\tvldr\td26, [sp, #304]\t@ 0x130\n-\tvdiv.f64\td16, d27, d14\n-\tvmul.f64\td16, d16, d0\n-\tvmul.f64\td16, d16, d9\n-\tvdiv.f64\td27, d16, d29\n-\tvldr\td16, [pc, #-500]\t@ d18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4f8>\n-\tvmul.f64\td16, d24, d16\n-\tvldr\td24, [pc, #-500]\t@ d20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x500>\n-\tvmul.f64\td27, d27, d18\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tvmul.f64\td9, d18, d16\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td16, d0, d16\n-\tvmul.f64\td0, d23, d6\n-\tvdiv.f64\td29, d18, d15\n-\tvldr\td15, [sp, #328]\t@ 0x148\n-\tvdiv.f64\td18, d18, d25\n-\tvstr\td18, [sp, #64]\t@ 0x40\n-\tvdiv.f64\td18, d24, d22\n-\tvldr\td22, [sp, #384]\t@ 0x180\n-\tvmov.f64\td24, #20\t@ 0x40a00000 5.0\n-\tvmul.f64\td22, d18, d22\n-\tvdiv.f64\td18, d24, d21\n-\tvldr\td24, [sp, #360]\t@ 0x168\n-\tvmul.f64\td18, d18, d24\n-\tvldr\td24, [pc, #-564]\t@ d28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x508>\n-\tvdiv.f64\td21, d24, d9\n-\tvldr\td24, [pc, #-564]\t@ d30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x510>\n-\tvmul.f64\td18, d18, d13\n-\tvldr\td13, [sp, #480]\t@ 0x1e0\n-\tvdiv.f64\td9, d24, d16\n-\tvldr\td24, [pc, #-572]\t@ d38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x518>\n-\tvldr\td16, [sp, #336]\t@ 0x150\n-\tvmul.f64\td25, d15, d24\n-\tvldr\td15, [sp, #368]\t@ 0x170\n-\tvmul.f64\td24, d23, d24\n-\tvldr\td23, [sp, #320]\t@ 0x140\n-\tvmul.f64\td25, d25, d19\n-\tvmul.f64\td19, d19, d15\n-\tvmul.f64\td19, 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0x160\n+\tvldr\td12, [sp, #296]\t@ 0x128\n+\tvadd.f64\td6, d6, d6\n+\tvldr\td7, [sp, #424]\t@ 0x1a8\n+\tvldr\td5, [sp, #344]\t@ 0x158\n+\tvmul.f64\td7, d7, d9\n+\tvstr\td6, [sp, #280]\t@ 0x118\n+\tvmul.f64\td6, d8, d12\n+\tvmul.f64\td8, d13, d13\n+\tvldr\td13, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td15, d5, d15\n+\tvmul.f64\td9, d5, d9\n+\tvadd.f64\td13, d13, d13\n+\tvstr\td6, [sp, #264]\t@ 0x108\n+\tvmov.f64\td6, #16\t@ 0x40800000 4.0\n+\tvstr\td13, [sp, #352]\t@ 0x160\n+\tvldr\td13, [sp, #48]\t@ 0x30\n+\tvsub.f64\td0, d0, d13\n \tvldr\td13, [sp, #400]\t@ 0x190\n-\tvmul.f64\td16, d16, d25\n-\tvmul.f64\td26, d26, d25\n-\tvmul.f64\td23, d23, d25\n-\tvldr\td25, [sp, #152]\t@ 0x98\n-\tvmul.f64\td16, d16, d21\n-\tvmul.f64\td26, d26, d21\n-\tvfma.f64\td16, d13, d22\n-\tvfma.f64\td26, d19, d28\n-\tvldr\td28, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td22, d23, d21\n-\tvldr\td21, [pc, #-652]\t@ d48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x528>\n-\tvfma.f64\td16, d19, d25\n-\tvfma.f64\td22, d19, d28\n-\tvldr\td19, [pc, #-656]\t@ d50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x530>\n-\tvldr\td25, [sp, #352]\t@ 0x160\n-\tvmul.f64\td19, d15, d19\n-\tvmul.f64\td19, d19, d25\n-\tvmov.f64\td28, d16\n-\tvfma.f64\td18, d9, d19\n-\tvldr\td9, [sp, #288]\t@ 0x120\n-\tvldr\td19, [sp, #376]\t@ 0x178\n-\tvmul.f64\td25, d9, d29\n-\tvmul.f64\td16, d14, d25\n-\tvfma.f64\td28, d19, d18\n-\tvmul.f64\td19, d14, d29\n-\tvldr\td29, [sp, #256]\t@ 0x100\n-\tvldr\td18, [pc, #-700]\t@ d58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x538>\n-\tvfma.f64\td26, d16, d8\n-\tvfma.f64\td22, d16, d5\n-\tvmul.f64\td23, d29, d21\n-\tvldr\td29, [sp, #472]\t@ 0x1d8\n-\tvldr\td16, [sp, #248]\t@ 0xf8\n-\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n-\tvmul.f64\td21, d29, d21\n-\tvmul.f64\td16, d16, d8\n-\tvmul.f64\td23, d23, d24\n-\tvnmul.f64\td15, d28, d10\n-\tvmul.f64\td21, d21, d24\n-\tvmov.f64\td5, d26\n-\tvfma.f64\td5, d16, d23\n-\tvldr\td23, [sp]\n-\tvfma.f64\td22, d16, d21\n-\tvadd.f64\td21, d19, d19\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvmul.f64\td8, d23, d8\n-\tvmul.f64\td21, d21, d6\n-\tvmul.f64\td23, d20, d16\n-\tvldr\td6, [sp, #432]\t@ 0x1b0\n-\tvadd.f64\td8, d8, d8\n-\tvmul.f64\td16, d14, d16\n-\tvmov.f64\td13, d22\n-\tvmul.f64\td22, d31, d0\n-\tvmul.f64\td24, d23, d18\n-\tvmul.f64\td29, d9, d8\n-\tvldr\td9, [sp, #520]\t@ 0x208\n-\tvnmul.f64\td22, d5, d22\n-\tvfms.f64\td22, d6, d21\n-\tvmul.f64\td24, d24, d31\n-\tvmov.f64\td26, d22\n-\tvldr\td22, [pc, #-824]\t@ d60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x540>\n-\tvfms.f64\td26, d9, d24\n-\tvldr\td24, [sp, #512]\t@ 0x200\n-\tvmul.f64\td10, d14, d24\n-\tvmul.f64\td14, d14, d18\n-\tvmul.f64\td18, d20, d18\n-\tvadd.f64\td20, d20, d20\n-\tvmul.f64\td9, d24, d9\n-\tvldr\td24, [sp, #456]\t@ 0x1c8\n-\tvfma.f64\td21, d23, d14\n-\tvnmul.f64\td23, d28, d2\n-\tvmul.f64\td18, d18, d16\n-\tvmul.f64\td20, d20, d25\n-\tvldr\td25, [sp, #496]\t@ 0x1f0\n-\tvnmul.f64\td28, d28, d9\n+\tvmul.f64\td13, d13, d6\n+\tvstr\td0, [sp, #424]\t@ 0x1a8\n+\tvldr\td0, [sp, #368]\t@ 0x170\n+\tvstr\td13, [sp, #288]\t@ 0x120\n+\tvmul.f64\td0, d0, d6\n+\tvstr\td0, [sp, #272]\t@ 0x110\n+\tvldr\td0, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td0, d0, d6\n+\tvmul.f64\td6, d5, d6\n+\tvstr\td0, [sp, #344]\t@ 0x158\n+\tvmov.f64\td0, d5\n+\tvdiv.f64\td5, d6, d10\n+\tvldr\td10, [sp, #336]\t@ 0x150\n+\tvdiv.f64\td6, d5, d4\n+\tvldr\td5, [sp, #136]\t@ 0x88\n+\tvmul.f64\td6, d6, d10\n+\tvmul.f64\td6, d6, d5\n+\tvdiv.f64\td5, d6, d2\n+\tvldr\td2, [sp, #328]\t@ 0x148\n+\tvmul.f64\td5, d5, d14\n+\tvstr\td5, [sp, #136]\t@ 0x88\n+\tvldr\td5, [pc, #-668]\t@ cc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4a0>\n+\tvmul.f64\td5, d0, d5\n+\tvldr\td0, [pc, #-668]\t@ cd0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4a8>\n+\tvmul.f64\td6, d2, d5\n+\tvmul.f64\td5, d10, d5\n+\tvdiv.f64\td2, d0, d7\n+\tvldr\td7, [pc, #-676]\t@ cd8 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d9\n+\tvldr\td9, [sp, #312]\t@ 0x138\n+\tvstr\td3, [sp, #200]\t@ 0xc8\n+\tvldr\td3, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td7, d7, d3\n+\tvmul.f64\td3, d3, d6\n+\tvnmls.f64\td3, d10, d15\n+\tvldr\td10, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td7, d7, d10\n+\tvmul.f64\td10, d10, d9\n+\tvstr\td10, [sp, #64]\t@ 0x40\n+\tvldr\td10, [sp, #8]\n+\tvmul.f64\td10, d9, d10\n+\tvmul.f64\td9, d8, d0\n+\tvmul.f64\td0, d4, d0\n+\tvmul.f64\td9, d9, d1\n+\tvmla.f64\td6, d0, d8\n+\tvldr\td0, [sp, #544]\t@ 0x220\n+\tvldr\td8, [sp, #536]\t@ 0x218\n+\tvmls.f64\td3, d9, d0\n+\tvmul.f64\td9, d4, d8\n+\tvldr\td4, [sp, #520]\t@ 0x208\n+\tvmul.f64\td13, d8, d0\n+\tvldr\td0, [sp, #480]\t@ 0x1e0\n+\tvldr\td8, [pc, #884]\t@ 1528 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd00>\n+\tvmul.f64\td4, d6, d4\n+\tvmul.f64\td6, d6, d0\n+\tvstr\td9, [sp, #72]\t@ 0x48\n+\tvmls.f64\td3, d2, d13\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvnmla.f64\td4, d12, d14\n+\tvmov.f64\td14, d3\n+\tvldr\td3, [sp, #472]\t@ 0x1d8\n+\tvstr\td4, [sp, #128]\t@ 0x80\n+\tvmul.f64\td2, d3, d2\n+\tvldr\td4, [sp, #120]\t@ 0x78\n+\tvmul.f64\td3, d3, d10\n+\tvmul.f64\td0, d4, d13\n+\tvldr\td4, [pc, #836]\t@ 1530 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd08>\n+\tvmul.f64\td5, d5, d4\n+\tvmov.f64\td4, #2\t@ 0x40100000 2.250\n+\tvmul.f64\td5, d5, d9\n+\tvldr\td9, [sp, #80]\t@ 0x50\n+\tvmul.f64\td9, d5, d9\n+\tvldr\td5, [sp, #152]\t@ 0x98\n+\tvmul.f64\td4, d5, d4\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvmul.f64\td4, d4, d5\n+\tvmul.f64\td5, d1, d8\n+\tvnmls.f64\td2, d5, d15\n+\tvnmls.f64\td9, d4, d15\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvnmls.f64\td6, d2, d12\n+\tvldr\td2, [sp, #72]\t@ 0x48\n+\tvmul.f64\td15, d15, d2\n+\tvldr\td2, [sp, #216]\t@ 0xd8\n+\tvnmls.f64\td7, d15, d2\n+\tvldr\td2, [sp, #224]\t@ 0xe0\n+\tvldr\td15, [sp, #288]\t@ 0x120\n+\tvmls.f64\td7, d0, d5\n+\tvldr\td5, [sp, #200]\t@ 0xc8\n+\tvldr\td0, [sp, #232]\t@ 0xe8\n+\tvmls.f64\td7, d5, d2\n+\tvmul.f64\td8, d0, d8\n+\tvnmls.f64\td3, d8, d1\n+\tvmov.f64\td2, d7\n+\tvldr\td7, [pc, #732]\t@ 1538 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd10>\n+\tvmul.f64\td11, d11, d7\n+\tvldr\td7, [sp, #144]\t@ 0x90\n+\tvmla.f64\td15, d3, d12\n+\tvldr\td3, [sp, #272]\t@ 0x110\n+\tvmul.f64\td11, d11, d7\n+\tvldr\td7, [sp, #440]\t@ 0x1b8\n+\tvmls.f64\td9, d11, d7\n+\tvldr\td7, [sp, #256]\t@ 0x100\n+\tvmls.f64\td9, d3, d7\n+\tvldr\td7, [sp, #424]\t@ 0x1a8\n+\tvldr\td3, [sp, #184]\t@ 0xb8\n+\tvldr\td11, [sp, #192]\t@ 0xc0\n+\tvldr\td8, [sp, #88]\t@ 0x58\n+\tvmul.f64\td5, d1, d3\n+\tvmul.f64\td9, d9, d7\n+\tvldr\td7, [pc, #676]\t@ 1540 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd18>\n+\tvmul.f64\td4, d14, d5\n+\tvstr\td5, [sp, #104]\t@ 0x68\n+\tvmov.f64\td5, d2\n+\tvmul.f64\td7, d3, d7\n+\tvmov.f64\td3, #96\t@ 0x3f000000 0.5\n+\tvmls.f64\td5, d4, d13\n+\tvmul.f64\td3, d11, d3\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvmul.f64\td7, d7, d14\n+\tvldr\td11, [sp, #40]\t@ 0x28\n+\tvnmls.f64\td7, d6, d3\n+\tvldr\td6, [sp, #136]\t@ 0x88\n+\tvmla.f64\td9, d5, d6\n+\tvldr\td5, [pc, #628]\t@ 1548 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd20>\n+\tvmul.f64\td6, d4, d5\n+\tvldr\td4, [sp, #208]\t@ 0xd0\n+\tvmla.f64\td7, d6, d11\n+\tvldr\td6, [sp, #96]\t@ 0x60\n+\tvmov.f64\td2, d9\n+\tvmov.f64\td9, #8\t@ 0x40400000 3.0\n+\tvmul.f64\td6, d14, d6\n+\tvmul.f64\td9, d4, d9\n+\tvldr\td4, [pc, #600]\t@ 1550 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd28>\n+\tvmls.f64\td7, d6, d9\n+\tvldr\td6, [sp, #32]\n+\tvadd.f64\td6, d6, d6\n+\tvmul.f64\td6, d6, d14\n+\tvmul.f64\td14, d11, d4\n+\tvldr\td11, [sp, #296]\t@ 0x128\n+\tvmls.f64\td7, d6, d14\n+\tvldr\td6, [sp, #552]\t@ 0x228\n+\tvstr\td14, [sp, #80]\t@ 0x50\n \tvldr\td14, [sp, #16]\n-\tvfms.f64\td26, d23, d9\n-\tvmul.f64\td18, d18, d6\n-\tvnmul.f64\td6, d21, d25\n-\tvnmul.f64\td24, d21, d24\n-\tvmul.f64\td21, d31, d22\n-\tvmul.f64\td22, d30, d22\n-\tvmov.f64\td25, d6\n-\tvldr\td6, [sp, #448]\t@ 0x1c0\n-\tvnmul.f64\td21, d5, d21\n-\tvfms.f64\td25, d13, d0\n-\tvldr\td13, [sp, #56]\t@ 0x38\n-\tvfms.f64\td21, d6, d23\n-\tvldr\td23, [sp, #72]\t@ 0x48\n-\tvfma.f64\td24, d21, d0\n-\tvldr\td21, [pc, #-936]\t@ d68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x548>\n-\tvmul.f64\td16, d16, d21\n-\tvnmul.f64\td21, d5, d10\n-\tvmul.f64\td16, d16, d13\n-\tvldr\td13, [sp, #120]\t@ 0x78\n-\tvmul.f64\td21, d21, d13\n-\tvfms.f64\td21, d14, d18\n-\tvmul.f64\td14, d14, d2\n-\tvmul.f64\td18, d2, d12\n-\tvnmul.f64\td16, d23, d16\n-\tvfms.f64\td21, d14, d28\n-\tvldr\td28, [sp, #128]\t@ 0x80\n-\tvfms.f64\td21, d28, d20\n-\tvnmul.f64\td20, d18, d6\n-\tvfma.f64\td20, d31, d22\n-\tvldr\td22, [sp, #80]\t@ 0x50\n-\tvldr\td6, [sp, #104]\t@ 0x68\n-\tvmul.f64\td28, d20, d0\n-\tvldr\td20, [sp, #464]\t@ 0x1d0\n-\tvfma.f64\td28, d20, d29\n-\tvmov.f64\td20, #2\t@ 0x40100000 2.250\n-\tvmul.f64\td20, d22, d20\n-\tvmul.f64\td20, d20, d23\n-\tvfms.f64\td16, d5, d20\n-\tvldr\td20, [pc, #896]\t@ 14f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xcd0>\n-\tvmul.f64\td19, d19, d20\n-\tvldr\td20, [sp, #416]\t@ 0x1a0\n-\tvmul.f64\td19, d19, d20\n-\tvldr\td20, [sp, #408]\t@ 0x198\n-\tvfms.f64\td16, d20, d19\n-\tvldr\td19, [sp, #96]\t@ 0x60\n-\tvmul.f64\td20, d31, d19\n-\tvfma.f64\td16, d15, d11\n-\tvmov.f64\td11, #8\t@ 0x40400000 3.0\n-\tvldr\td15, [pc, #864]\t@ 14f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xcd8>\n-\tvnmul.f64\td23, d20, d26\n-\tvfma.f64\td21, d23, d9\n-\tvldr\td23, [sp, #64]\t@ 0x40\n-\tvmov.f64\td22, d16\n-\tvldr\td16, [pc, #852]\t@ 1500 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xce0>\n-\tvmul.f64\td16, d19, d16\n-\tvmov.f64\td19, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td19, d6, d19\n-\tvnmul.f64\td16, d26, d16\n-\tvfma.f64\td16, d24, d19\n-\tvmul.f64\td24, d21, d27\n-\tvldr\td21, [sp, #144]\t@ 0x90\n-\tvfma.f64\td24, d22, d21\n-\tvldr\td22, [pc, #824]\t@ 1508 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xce8>\n-\tvmul.f64\td21, d25, d22\n-\tvldr\td25, [sp, #32]\n-\tvnmul.f64\td15, d15, d25\n-\tvfma.f64\td16, d25, d21\n-\tvldr\td21, [sp, #112]\t@ 0x70\n-\tvmul.f64\td11, d21, d11\n-\tvldr\td21, [sp, #24]\n-\tvadd.f64\td21, d21, d21\n-\tvmul.f64\td21, d21, d26\n-\tvnmul.f64\td26, d23, d26\n-\tvldr\td23, [sp]\n-\tvfma.f64\td16, d11, d26\n-\tvfma.f64\td16, d21, d15\n-\tvldr\td21, [pc, #776]\t@ 1510 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xcf0>\n-\tvmul.f64\td1, d1, d21\n-\tvldr\td21, [pc, #776]\t@ 1518 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xcf8>\n-\tvmul.f64\td21, d23, d21\n-\tvldr\td23, [sp, #8]\n-\tvmul.f64\td1, d1, d7\n-\tvfma.f64\td1, d23, d21\n-\tvldr\td21, [sp, #504]\t@ 0x1f8\n-\tvldr\td23, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td1, d1, d0\n-\tvfma.f64\td1, d21, d29\n-\tvmul.f64\td21, d30, d0\n-\tvmul.f64\td21, d21, d31\n-\tvfma.f64\td21, d23, d29\n-\tvldr\td23, [pc, #736]\t@ 1520 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd00>\n-\tvmul.f64\td22, d1, d22\n-\tvfms.f64\td21, d18, d9\n-\tvldr\td18, [pc, #732]\t@ 1528 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd08>\n-\tvfma.f64\td16, d24, d18\n-\tvldr\td18, [sp, #424]\t@ 0x1a8\n-\tvldr\td24, [pc, #728]\t@ 1530 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd10>\n-\tvmul.f64\td24, d18, d24\n-\tvldr\td18, [sp, #88]\t@ 0x58\n-\tvmul.f64\td23, d18, d23\n-\tvldr\td18, [r6]\n-\tvfms.f64\td18, d3, d24\n-\tvfms.f64\td18, d16, d23\n-\tvadd.f64\td16, d21, d21\n-\tvstr\td18, [r6]\n-\tvldr\td18, [pc, #700]\t@ 1538 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd18>\n-\tvcmpe.f64\td17, d18\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t13ca <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xbaa>\n-\tvldr\td24, [pc, #692]\t@ 1540 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd20>\n-\tvldr\td18, [pc, #696]\t@ 1548 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd28>\n-\tvldr\td25, [pc, #700]\t@ 1550 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd30>\n-\tvadd.f64\td24, d17, d24\n-\tvadd.f64\td25, d17, d25\n-\tvfma.f64\td18, d17, d24\n-\tvldr\td24, [sp, #40]\t@ 0x28\n-\tvmul.f64\td18, d24, d18\n-\tvldr\td24, [pc, #684]\t@ 1558 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd38>\n-\tvfma.f64\td24, d17, d25\n-\tvdiv.f64\td0, d18, d24\n-\tvldr\td17, [sp, #48]\t@ 0x30\n-\tvmul.f64\td12, d12, d9\n-\tvldr\td18, [pc, #576]\t@ 1500 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xce0>\n-\tvmul.f64\td10, d30, d10\n-\tvmul.f64\td9, d21, d9\n-\tvmul.f64\td11, d21, d11\n-\tvmul.f64\td3, d17, d8\n-\tvldr\td17, [sp, #40]\t@ 0x28\n-\tvnmul.f64\td14, d14, d12\n-\tvmul.f64\td18, d21, d18\n-\tvldr\td21, [sp, #120]\t@ 0x78\n-\tvsub.f64\td0, d0, d17\n-\tvldr\td17, [sp, #24]\n-\tvldr\td24, [pc, #572]\t@ 1528 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd08>\n-\tvmul.f64\td16, d17, d16\n-\tvldr\td17, [sp, #128]\t@ 0x80\n-\tvfma.f64\td14, d17, d3\n-\tvldr\td17, [r4]\n-\tvfma.f64\td14, d21, d10\n-\tvldr\td21, [sp, #96]\t@ 0x60\n-\tvnmul.f64\td18, d21, d18\n-\tvfms.f64\td14, d20, d9\n-\tvfma.f64\td18, d28, d19\n-\tvldr\td19, [sp, #32]\n-\tvfma.f64\td18, d19, d22\n-\tvldr\td19, [sp, #64]\t@ 0x40\n-\tvmul.f64\td14, d14, d27\n-\tvfms.f64\td18, d19, d11\n-\tvfma.f64\td14, d4, d0\n-\tvfma.f64\td18, d15, d16\n-\tvfma.f64\td18, d14, d24\n-\tvfms.f64\td17, d18, d23\n-\tvstr\td17, [r4]\n+\tvmov.f64\td4, d7\n+\tvldr\td7, [pc, #560]\t@ 1558 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd30>\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td6, [sp, #24]\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #552]\t@ 1560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd38>\n+\tvmul.f64\td6, d8, d6\n+\tvldr\td8, [sp, #280]\t@ 0x118\n+\tvmla.f64\td7, d6, d14\n+\tvldr\td6, [pc, #544]\t@ 1568 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd40>\n+\tvldr\td14, [pc, #548]\t@ 1570 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd48>\n+\tvmla.f64\td11, d7, d12\n+\tvmul.f64\td7, d0, d12\n+\tvmla.f64\td8, d7, d1\n+\tvldr\td7, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [pc, #532]\t@ 1578 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd50>\n+\tvmul.f64\td11, d11, d5\n+\tvldr\td5, [sp, #248]\t@ 0xf8\n+\tvmls.f64\td8, d10, d13\n+\tvmla.f64\td4, d2, d7\n+\tvldr\td7, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td14, d7, d14\n+\tvldr\td7, [r6]\n+\tvmls.f64\td7, d6, d5\n+\tvldr\td6, [sp]\n+\tvadd.f64\td10, d8, d8\n+\tvmls.f64\td7, d4, d14\n+\tvstr\td7, [r6]\n+\tvldr\td7, [pc, #488]\t@ 1580 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd58>\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.w\t14c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xc98>\n+\tvmov.f64\td4, d6\n+\tvldr\td6, [pc, #476]\t@ 1588 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd60>\n+\tvldr\td7, [pc, #480]\t@ 1590 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd68>\n+\tvldr\td5, [pc, #484]\t@ 1598 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd70>\n+\tvadd.f64\td6, d4, d6\n+\tvadd.f64\td5, d4, d5\n+\tvmla.f64\td7, d6, d4\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #468]\t@ 15a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd78>\n+\tvmla.f64\td6, d5, d4\n+\tvdiv.f64\td0, d7, d6\n+\tvldr\td7, [sp, #56]\t@ 0x38\n+\tvmul.f64\td9, d8, d9\n+\tvldr\td6, [sp, #112]\t@ 0x70\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvldr\td4, [sp, #64]\t@ 0x40\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td5, d7, d5\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvsub.f64\td0, d0, d7\n+\tvldr\td7, [sp, #32]\n+\tvmul.f64\td10, d7, d10\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td0, d0, d7\n+\tvldr\td7, [sp, #8]\n+\tvmul.f64\td7, d7, d13\n+\tvmul.f64\td7, d7, d4\n+\tvldr\td4, [sp, #224]\t@ 0xe0\n+\tvnmls.f64\td7, d6, d4\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvmla.f64\td7, d5, d6\n+\tvmul.f64\td6, d8, d13\n+\tvldr\td5, [sp, #104]\t@ 0x68\n+\tvmls.f64\td7, d6, d5\n+\tvldr\td6, [sp, #136]\t@ 0x88\n+\tvmla.f64\td0, d7, d6\n+\tvldr\td7, [pc, #256]\t@ 1540 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd18>\n+\tvldr\td6, [sp, #96]\t@ 0x60\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tvnmls.f64\td8, d15, d3\n+\tvmla.f64\td8, d7, d11\n+\tvldr\td7, [r4]\n+\tvmls.f64\td8, d9, d6\n+\tvldr\td6, [sp, #80]\t@ 0x50\n+\tvmls.f64\td8, d10, d6\n+\tvldr\td6, [pc, #264]\t@ 1578 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xd50>\n+\tvmla.f64\td8, d0, d6\n+\tvmls.f64\td7, d8, d14\n+\tvstr\td7, [r4]\n \tadd.w\tsp, sp, #560\t@ 0x230\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvmov.f64\td0, d17\n-\tvstr\td5, [sp, #224]\t@ 0xe0\n-\tvstr\td25, [sp, #216]\t@ 0xd8\n-\tvstr\td18, [sp, #208]\t@ 0xd0\n-\tvstr\td6, [sp, #200]\t@ 0xc8\n-\tvstr\td20, [sp, #192]\t@ 0xc0\n-\tvstr\td23, [sp, #184]\t@ 0xb8\n-\tvstr\td31, [sp, #176]\t@ 0xb0\n-\tvstr\td29, [sp, #168]\t@ 0xa8\n-\tvstr\td7, [sp, #160]\t@ 0xa0\n-\tvstr\td19, [sp, #152]\t@ 0x98\n-\tvstr\td21, [sp, #144]\t@ 0x90\n-\tvstr\td24, [sp, #128]\t@ 0x80\n-\tvstr\td17, [sp, #120]\t@ 0x78\n+\tvmov.f64\td11, d6\n+\tvmov.f64\td0, d6\n+\tvstr\td3, [sp, #264]\t@ 0x108\n+\tvstr\td1, [sp, #232]\t@ 0xe8\n+\tvstr\td2, [sp, #224]\t@ 0xe0\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td17, [sp, #120]\t@ 0x78\n \tvmov.f64\td8, d0\n-\tvmov.f64\td0, d17\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td17, [sp, #120]\t@ 0x78\n+\tvmov.f64\td0, d11\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td4, [sp, #216]\t@ 0xd8\n+\tvldr\td2, [sp, #224]\t@ 0xe0\n+\tvldr\td1, [sp, #232]\t@ 0xe8\n \tvmul.f64\td8, d8, d0\n-\tvldr\td24, [sp, #128]\t@ 0x80\n-\tvldr\td21, [sp, #144]\t@ 0x90\n-\tvldr\td19, [sp, #152]\t@ 0x98\n-\tvldr\td7, [sp, #160]\t@ 0xa0\n-\tvldr\td29, [sp, #168]\t@ 0xa8\n-\tvldr\td31, [sp, #176]\t@ 0xb0\n-\tvldr\td23, [sp, #184]\t@ 0xb8\n-\tvldr\td20, [sp, #192]\t@ 0xc0\n-\tvldr\td6, [sp, #200]\t@ 0xc8\n-\tvldr\td18, [sp, #208]\t@ 0xd0\n-\tvldr\td25, [sp, #216]\t@ 0xd8\n-\tvldr\td5, [sp, #224]\t@ 0xe0\n-\tb.w\tb76 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x356>\n-\tvmov.f64\td0, d17\n-\tvstr\td23, [sp, #144]\t@ 0x90\n-\tvstr\td27, [sp, #136]\t@ 0x88\n-\tvstr\td19, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #104]\t@ 0x68\n-\tvstr\td22, [sp, #88]\t@ 0x58\n-\tvstr\td28, [sp, #80]\t@ 0x50\n-\tvstr\td21, [sp, #72]\t@ 0x48\n-\tvstr\td20, [sp, #56]\t@ 0x38\n-\tvstr\td4, [sp, #16]\n-\tvstr\td30, [sp, #8]\n-\tvstr\td17, [sp]\n+\tvldr\td3, [sp, #264]\t@ 0x108\n+\tb.n\td10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x4e8>\n+\tvmov.f64\td0, d6\n+\tvmov.f64\td12, d6\n+\tvstr\td3, [sp, #16]\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td17, [sp]\n-\tvmov.f64\td13, d0\n-\tvmov.f64\td0, d17\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td30, [sp, #8]\n-\tvmul.f64\td0, d13, d0\n-\tvldr\td4, [sp, #16]\n-\tvldr\td20, [sp, #56]\t@ 0x38\n-\tvldr\td21, [sp, #72]\t@ 0x48\n-\tvldr\td28, [sp, #80]\t@ 0x50\n-\tvldr\td22, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvldr\td19, [sp, #112]\t@ 0x70\n-\tvldr\td27, [sp, #136]\t@ 0x88\n-\tvldr\td23, [sp, #144]\t@ 0x90\n-\tb.n\t12b4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xa94>\n-\tvmov.f64\td0, d17\n-\tvstr\td4, [sp, #552]\t@ 0x228\n-\tvstr\td30, [sp, #544]\t@ 0x220\n-\tvstr\td1, [sp, #536]\t@ 0x218\n-\tvstr\td2, [sp, #528]\t@ 0x210\n-\tvstr\td3, [sp, #240]\t@ 0xf0\n-\tvstr\td5, [sp, #232]\t@ 0xe8\n-\tvstr\td25, [sp, #224]\t@ 0xe0\n-\tvstr\td18, [sp, #216]\t@ 0xd8\n-\tvstr\td6, [sp, #208]\t@ 0xd0\n-\tvstr\td20, [sp, #200]\t@ 0xc8\n-\tvstr\td23, [sp, #192]\t@ 0xc0\n-\tvstr\td31, [sp, #184]\t@ 0xb8\n-\tvstr\td29, [sp, #176]\t@ 0xb0\n-\tvstr\td7, [sp, #168]\t@ 0xa8\n-\tvstr\td19, [sp, #160]\t@ 0xa0\n-\tvstr\td21, [sp, #152]\t@ 0x98\n-\tvstr\td24, [sp, #144]\t@ 0x90\n-\tvstr\td17, [sp, #136]\t@ 0x88\n+\tvmov.f64\td7, d0\n+\tvmov.f64\td0, d12\n+\tvmov.f64\td12, d7\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td3, [sp, #16]\n+\tvmul.f64\td0, d12, d0\n+\tb.n\t13d4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0xbac>\n+\tvmov.f64\td12, d6\n+\tvmov.f64\td0, d6\n+\tvstr\td3, [sp, #288]\t@ 0x120\n+\tvstr\td1, [sp, #280]\t@ 0x118\n+\tvstr\td2, [sp, #272]\t@ 0x110\n+\tvstr\td4, [sp, #264]\t@ 0x108\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td17, [sp, #136]\t@ 0x88\n \tvmov.f64\td8, d0\n-\tvmov.f64\td0, d17\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td17, [sp, #136]\t@ 0x88\n+\tvmov.f64\td0, d12\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td4, [sp, #264]\t@ 0x108\n+\tvldr\td2, [sp, #272]\t@ 0x110\n+\tvldr\td1, [sp, #280]\t@ 0x118\n \tvmul.f64\td0, d8, d0\n-\tvldr\td24, [sp, #144]\t@ 0x90\n-\tvldr\td21, [sp, #152]\t@ 0x98\n-\tvldr\td19, [sp, #160]\t@ 0xa0\n-\tvldr\td7, [sp, #168]\t@ 0xa8\n-\tvldr\td29, [sp, #176]\t@ 0xb0\n-\tvldr\td31, [sp, #184]\t@ 0xb8\n-\tvldr\td23, [sp, #192]\t@ 0xc0\n-\tvldr\td20, [sp, #200]\t@ 0xc8\n-\tvldr\td6, [sp, #208]\t@ 0xd0\n-\tvldr\td18, [sp, #216]\t@ 0xd8\n-\tvldr\td25, [sp, #224]\t@ 0xe0\n-\tvldr\td5, [sp, #232]\t@ 0xe8\n-\tvldr\td3, [sp, #240]\t@ 0xf0\n-\tvldr\td2, [sp, #528]\t@ 0x210\n-\tvldr\td1, [sp, #536]\t@ 0x218\n-\tvldr\td30, [sp, #544]\t@ 0x220\n-\tvldr\td4, [sp, #552]\t@ 0x228\n-\tb.n\te84 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x664>\n-\tnop\n-\tnop.w\n+\tvldr\td3, [sp, #288]\t@ 0x120\n+\tb.n\tebc <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0+0x694>\n+\t.word\t0xe03dc2d9\n+\t.word\t0x4019e6cb\n+\t.word\t0x54a28591\n+\t.word\t0x40136d19\n \t.word\t0x97d453e4\n \t.word\t0x3fff7e15\n-\t.word\t0x77bd9591\n-\t.word\t0xbfb3c464\n \t.word\t0xdc766309\n \t.word\t0xbfc7ca11\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n+\t.word\t0x77bd9591\n+\t.word\t0xbfb3c464\n \t.word\t0x0f94a0b7\n \t.word\t0xbfda4852\n \t.word\t0x1ff9d571\n \t.word\t0x3fe5eb4b\n+\t.word\t0xbda12f68\n+\t.word\t0x3ff2f684\n \t.word\t0xfe791dd3\n \t.word\t0xbfe7a245\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n-\t.word\t0xbda12f68\n-\t.word\t0x3ff2f684\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \n-00001560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>:\n+000015a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3384]\t@ 0xd38\n-\tvmul.f64\td9, d1, d1\n-\tvldr\td16, [pc, #1000]\t@ 1960 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x400>\n-\tvldr\td11, [pc, #1004]\t@ 1968 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x408>\n+\tstr.w\tr0, [ip, #3376]\t@ 0xd30\n+\tvmul.f64\td13, d1, d1\n+\tvldr\td7, [pc, #1008]\t@ 19b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x408>\n \tmov\tr4, r2\n-\tldr.w\tr2, [pc, #1196]\t@ 1a30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x4d0>\n-\tvmov.f64\td17, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr3, [pc, #1192]\t@ 1a34 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x4d4>\n-\tvmov.f64\td8, d0\n-\tvmul.f64\td16, d9, d16\n+\tldr.w\tr2, [pc, #1168]\t@ 1a58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x4b0>\n+\tldr.w\tr3, [pc, #1168]\t@ 1a5c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x4b4>\n+\tsub.w\tsp, sp, #640\t@ 0x280\n \tadd\tr2, pc\n-\tvmul.f64\td11, d0, d11\n-\tsub.w\tsp, sp, #632\t@ 0x278\n-\tvmov.f64\td13, d1\n-\tvmov.f64\td14, d2\n+\tvldr\td10, [pc, #996]\t@ 19b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x410>\n+\tvmul.f64\td7, d13, d7\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tvstr\td13, [sp, #248]\t@ 0xf8\n+\tvmov.f64\td9, d0\n \tldr\tr3, [r2, r3]\n-\tmov\tr5, r0\n-\tvmul.f64\td15, d16, d17\n-\tmov\tr6, r1\n-\tvmov.f64\td0, d11\n+\tvmul.f64\td10, d0, d10\n+\tvmov.f64\td14, d1\n+\tvmov.f64\td15, d2\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #628]\t@ 0x274\n+\tstr\tr3, [sp, #636]\t@ 0x27c\n \tmov.w\tr3, #0\n-\tvstr\td16, [sp, #280]\t@ 0x118\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvstr\td17, [sp, #8]\n-\tvstr\td15, [sp, #288]\t@ 0x120\n+\tvstr\td7, [sp, #368]\t@ 0x170\n+\tvmul.f64\td7, d7, d12\n+\tmov\tr5, r0\n+\tvmov.f64\td0, d10\n+\tmov\tr6, r1\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp, #136]\t@ 0x88\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td17, d8, d8\n-\tvldr\td18, [pc, #920]\t@ 1970 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x410>\n-\tvmul.f64\td25, d9, d9\n-\tvldr\td22, [pc, #920]\t@ 1978 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x418>\n-\tvldr\td21, [pc, #924]\t@ 1980 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x420>\n-\tvmul.f64\td19, d0, d0\n-\tvmul.f64\td18, d9, d18\n-\tvmul.f64\td16, d14, d14\n-\tvmul.f64\td23, d17, d17\n-\tvstr\td17, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td28, d25, d22\n-\tvmul.f64\td22, d11, d0\n-\tvdiv.f64\td27, d12, d17\n-\tvmul.f64\td11, d11, d19\n-\tvmul.f64\td30, d18, d25\n-\tvstr\td19, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td18, d23, d23\n-\tvmul.f64\td20, d16, d16\n-\tvdiv.f64\td29, d12, d23\n-\tvstr\td23, [sp, #168]\t@ 0xa8\n-\tvdiv.f64\td17, d12, d19\n-\tvldr\td26, [pc, #864]\t@ 1988 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x428>\n-\tvstr\td25, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td10, d0\n-\tvstr\td18, [sp, #424]\t@ 0x1a8\n+\tvmov.f64\td7, d0\n+\tvmul.f64\td0, d0, d0\n+\tvmul.f64\td2, d9, d9\n+\tvldr\td5, [pc, #920]\t@ 19c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x418>\n+\tvmul.f64\td1, d15, d15\n+\tvstr\td14, [sp, #48]\t@ 0x30\n+\tvstr\td7, [sp, #144]\t@ 0x90\n+\tvmul.f64\td7, d10, d7\n+\tvmul.f64\td10, d10, d0\n+\tvmul.f64\td11, d2, d2\n+\tvstr\td2, [sp, #256]\t@ 0x100\n+\tvdiv.f64\td2, d8, d2\n+\tvstr\td0, [sp, #288]\t@ 0x120\n+\tvdiv.f64\td6, d8, d7\n+\tvldr\td7, [pc, #884]\t@ 19c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x420>\n+\tvmul.f64\td3, d11, d11\n+\tvdiv.f64\td4, d8, d10\n+\tvmov.f64\td10, d1\n+\tvmul.f64\td7, d13, d7\n+\tvstr\td3, [sp, #464]\t@ 0x1d0\n+\tvstr\td10, [sp]\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvstr\td6, [sp, #88]\t@ 0x58\n+\tvdiv.f64\td6, d5, d3\n+\tvmul.f64\td5, d11, d9\n+\tvstr\td4, [sp, #96]\t@ 0x60\n+\tvmov.f64\td4, d15\n+\tvdiv.f64\td15, d8, d11\n+\tvmul.f64\td3, d1, d1\n+\tvmul.f64\td1, d13, d13\n+\tvdiv.f64\td5, d8, d5\n+\tvstr\td4, [sp, #232]\t@ 0xe8\n+\tvstr\td3, [sp, #408]\t@ 0x198\n+\tvstr\td15, [sp, #400]\t@ 0x190\n+\tvstr\td5, [sp, #160]\t@ 0xa0\n+\tvmov.f64\td5, d13\n+\tvmul.f64\td13, d7, d1\n+\tvldr\td7, [pc, #800]\t@ 19d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x428>\n+\tvstr\td13, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td13, d10, d3\n+\tvstr\td13, [sp, #472]\t@ 0x1d8\n+\tvmul.f64\td13, d6, d13\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvstr\td13, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td13, d1, d7\n+\tvmul.f64\td7, d15, d3\n+\tvmul.f64\td3, d3, d4\n+\tvstr\td13, [sp, #152]\t@ 0x98\n+\tvmul.f64\td15, d7, d6\n+\tvmul.f64\td6, d1, d14\n+\tvldr\td7, [pc, #756]\t@ 19d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x430>\n+\tvmov.f64\td4, d3\n+\tvstr\td3, [sp, #448]\t@ 0x1c0\n+\tvmov.f64\td14, d2\n+\tvldr\td2, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td3, d6, d7\n+\tvstr\td6, [sp, #424]\t@ 0x1a8\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tvldr\td13, [pc, #732]\t@ 19e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x438>\n+\tvstr\td15, [sp, #304]\t@ 0x130\n+\tvmov.f64\td10, d3\n+\tvstr\td3, [sp, #432]\t@ 0x1b0\n+\tvdiv.f64\td3, d8, d0\n \tvmov.f64\td0, d8\n-\tvdiv.f64\td18, d21, d18\n-\tvmul.f64\td21, d23, d8\n-\tvdiv.f64\td19, d12, d22\n-\tvmul.f64\td23, d16, d20\n-\tvmul.f64\td26, d25, d26\n-\tvldr\td24, [pc, #832]\t@ 1990 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x430>\n-\tvdiv.f64\td22, d12, d11\n-\tvstr\td20, [sp, #152]\t@ 0x98\n-\tvdiv.f64\td21, d12, d21\n-\tvstr\td13, [sp, #48]\t@ 0x30\n-\tvstr\td23, [sp, #432]\t@ 0x1b0\n-\tvstr\td30, [sp, #416]\t@ 0x1a0\n-\tvstr\td28, [sp, #344]\t@ 0x158\n-\tvstr\td26, [sp, #304]\t@ 0x130\n-\tvstr\td24, [sp, #24]\n-\tvmul.f64\td11, d27, d16\n-\tvstr\td27, [sp, #232]\t@ 0xe8\n-\tvstr\td29, [sp, #320]\t@ 0x140\n-\tvstr\td17, [sp, #64]\t@ 0x40\n-\tvmul.f64\td23, d18, d23\n-\tvmul.f64\td18, d29, d20\n-\tvstr\td19, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td29, d20, d14\n-\tvstr\td22, [sp, #384]\t@ 0x180\n-\tvmul.f64\td19, d18, d19\n-\tvmul.f64\td18, d25, d13\n-\tvstr\td21, [sp, #392]\t@ 0x188\n-\tvmul.f64\td21, d21, d29\n-\tvstr\td23, [sp, #440]\t@ 0x1b8\n-\tvstr\td29, [sp, #400]\t@ 0x190\n-\tvmov.f64\td25, d18\n-\tvstr\td18, [sp, #360]\t@ 0x168\n-\tvldr\td18, [pc, #732]\t@ 1998 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x438>\n-\tvmov.f64\td20, d19\n-\tvstr\td19, [sp, #328]\t@ 0x148\n-\tvmul.f64\td25, d25, d18\n-\tvmov.f64\td18, d12\n-\tvfma.f64\td18, d30, d23\n-\tvmul.f64\td23, d28, d24\n-\tvstr\td25, [sp, #368]\t@ 0x170\n-\tvfma.f64\td18, d19, d23\n-\tvmul.f64\td19, d21, d22\n-\tvldr\td21, [pc, #700]\t@ 19a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x440>\n-\tvstr\td23, [sp, #352]\t@ 0x160\n-\tvmul.f64\td23, d26, d24\n-\tvldr\td26, [pc, #696]\t@ 19a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x448>\n-\tvmul.f64\td21, d25, d21\n-\tvstr\td19, [sp, #408]\t@ 0x198\n-\tvstr\td23, [sp, #312]\t@ 0x138\n-\tvfma.f64\td18, d21, d19\n-\tvstr\td21, [sp, #376]\t@ 0x178\n-\tvmul.f64\td21, d17, d27\n-\tvmov.f64\td19, d17\n-\tvmul.f64\td25, d21, d16\n-\tvstr\td21, [sp]\n-\tvmul.f64\td21, d23, d20\n-\tvmov.f64\td22, d18\n-\tvstr\td18, [sp, #248]\t@ 0xf8\n-\tvfma.f64\td21, d15, d25\n-\tvldr\td17, [sp, #8]\n-\tvmov.f64\td18, #2\t@ 0x40100000 2.250\n-\tvstr\td25, [sp, #296]\t@ 0x128\n-\tvstr\td26, [sp, #56]\t@ 0x38\n-\tvdiv.f64\td13, d12, d22\n-\tvmul.f64\td24, d19, d17\n-\tvstr\td17, [sp, #16]\n-\tvstr\td16, [sp, #144]\t@ 0x90\n-\tvstr\td24, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td20, d21, d18\n-\tvmul.f64\td18, d11, d26\n-\tvstr\td21, [sp, #8]\n-\tvmul.f64\td18, d18, d24\n-\tvstr\td20, [sp, #336]\t@ 0x150\n-\tvstr\td18, [sp, #472]\t@ 0x1d8\n-\tvmul.f64\td22, d9, d13\n-\tvmul.f64\td20, d20, d22\n-\tvstr\td22, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td15, d20, d18\n-\tvstr\td20, [sp, #456]\t@ 0x1c8\n+\tvmla.f64\td0, d6, d2\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvldr\td2, [sp, #96]\t@ 0x60\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td6, [sp, #416]\t@ 0x1a0\n+\tvmov.f64\td7, d0\n+\tvldr\td0, [sp, #160]\t@ 0xa0\n+\tvmla.f64\td7, d15, d6\n+\tvmul.f64\td6, d0, d4\n+\tvmul.f64\td0, d6, d2\n+\tvldr\td6, [pc, #676]\t@ 19e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x440>\n+\tvmul.f64\td2, d10, d6\n+\tvmov.f64\td6, d7\n+\tvldr\td7, [pc, #672]\t@ 19f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x448>\n+\tvstr\td0, [sp, #456]\t@ 0x1c8\n+\tvmla.f64\td6, d2, d0\n+\tvstr\td2, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td2, d1, d7\n+\tvstr\td1, [sp, #216]\t@ 0xd8\n+\tvldr\td10, [sp]\n+\tvmov.f64\td7, #2\t@ 0x40100000 2.250\n+\tvmov.f64\td0, d9\n+\tvmov.f64\td1, d2\n+\tvstr\td2, [sp, #384]\t@ 0x180\n+\tvstr\td3, [sp, #80]\t@ 0x50\n+\tvldr\td2, [pc, #632]\t@ 19f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x450>\n+\tvstr\td6, [sp, #320]\t@ 0x140\n+\tvmul.f64\td1, d1, d13\n+\tvstr\td2, [sp, #56]\t@ 0x38\n+\tvmov.f64\td4, d1\n+\tvstr\td1, [sp, #392]\t@ 0x188\n+\tvdiv.f64\td1, d8, d6\n+\tvmul.f64\td6, d4, d15\n+\tvmul.f64\td15, d3, d12\n+\tvmov.f64\td4, d15\n+\tvstr\td15, [sp, #336]\t@ 0x150\n+\tvmov.f64\td15, d14\n+\tvmul.f64\td14, d3, d14\n+\tvmul.f64\td3, d14, d10\n+\tvstr\td14, [sp, #16]\n+\tvldr\td14, [sp, #136]\t@ 0x88\n+\tvmul.f64\td15, d15, d10\n+\tvmla.f64\td6, d14, d3\n+\tvstr\td3, [sp, #376]\t@ 0x178\n+\tvstr\td15, [sp, #64]\t@ 0x40\n+\tvmul.f64\td14, d6, d7\n+\tvmul.f64\td7, d15, d2\n+\tvstr\td6, [sp, #24]\n+\tvmov.f64\td3, d14\n+\tvstr\td14, [sp, #312]\t@ 0x138\n+\tvmov.f64\td14, d5\n+\tvmul.f64\td5, d5, d1\n+\tvmul.f64\td2, d7, d4\n+\tvstr\td1, [sp, #8]\n+\tvstr\td5, [sp, #328]\t@ 0x148\n+\tvmul.f64\td5, d3, d5\n+\tvstr\td2, [sp, #344]\t@ 0x158\n+\tvmul.f64\td12, d14, d12\n+\tvldr\td14, [pc, #508]\t@ 1a00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x458>\n+\tvmul.f64\td15, d5, d2\n+\tvstr\td5, [sp, #480]\t@ 0x1e0\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #8]\n-\tvldr\td17, [sp, #16]\n-\tvldr\td28, [pc, #556]\t@ 19b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x450>\n-\tvmul.f64\td18, d16, d13\n-\tvldr\td21, [pc, #556]\t@ 19b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x458>\n-\tvmul.f64\td20, d9, d17\n-\tvldr\td17, [sp, #64]\t@ 0x40\n-\tvmul.f64\td28, d8, d28\n-\tvldr\td29, [pc, #548]\t@ 19c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x460>\n-\tvldr\td27, [pc, #552]\t@ 19c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x468>\n-\tvstr\td18, [sp, #72]\t@ 0x48\n-\tvmul.f64\td19, d17, d20\n-\tvstr\td20, [sp, #40]\t@ 0x28\n-\tvldr\td17, [pc, #544]\t@ 19d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x470>\n-\tvmul.f64\td20, d11, d18\n-\tvmul.f64\td23, d28, d0\n-\tvldr\td28, [pc, #540]\t@ 19d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x478>\n-\tvstr\td0, [sp, #480]\t@ 0x1e0\n+\tvldr\td1, [sp, #8]\n+\tvldr\td6, [sp, #24]\n+\tvmov.f64\td10, d0\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvldr\td3, [sp, #80]\t@ 0x50\n+\tvmul.f64\td5, d6, d1\n+\tvldr\td7, [pc, #476]\t@ 1a08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x460>\n+\tvstr\td12, [sp, #72]\t@ 0x48\n+\tvmul.f64\td3, d3, d12\n+\tvstr\td0, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [pc, #464]\t@ 1a10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x468>\n+\tvmul.f64\td12, d2, d5\n+\tvldr\td4, [pc, #464]\t@ 1a18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x470>\n+\tvstr\td5, [sp, #104]\t@ 0x68\n+\tvmov.f64\td0, d3\n+\tvstr\td3, [sp, #496]\t@ 0x1f0\n+\tvstr\td6, [sp, #352]\t@ 0x160\n+\tvmla.f64\td14, d3, d12\n+\tvstr\td12, [sp, #504]\t@ 0x1f8\n+\tvmov.f64\td12, d7\n+\tvldr\td3, [pc, #440]\t@ 1a20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x478>\n+\tvmla.f64\td12, d1, d6\n+\tvldr\td6, [pc, #440]\t@ 1a28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x480>\n+\tvldr\td7, [pc, #444]\t@ 1a30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x488>\n+\tvldr\td5, [pc, #448]\t@ 1a38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x490>\n+\tvmul.f64\td6, d9, d6\n+\tvmul.f64\td1, d6, d10\n+\tvldr\td6, [pc, #444]\t@ 1a40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x498>\n+\tvmul.f64\td2, d2, d12\n+\tvstr\td12, [sp, #512]\t@ 0x200\n+\tvstr\td1, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td1, d14, d14\n+\tvstr\td2, [sp, #520]\t@ 0x208\n+\tvnmls.f64\td7, d1, d3\n+\tvstr\td1, [sp, #264]\t@ 0x108\n+\tvsqrt.f64\td3, d14\n+\tvmov.f64\td10, d3\n+\tvstr\td3, [sp, #360]\t@ 0x168\n+\tvmov.f64\td3, d1\n+\tvdiv.f64\td1, d8, d3\n+\tvmul.f64\td12, d14, d3\n+\tvstr\td1, [sp, #112]\t@ 0x70\n+\tvmul.f64\td1, d1, d6\n+\tvmov.f64\td6, d8\n+\tvmla.f64\td6, d0, d2\n \tvmov.f64\td0, d15\n-\tvmul.f64\td22, d16, d17\n-\tvldr\td17, [pc, #532]\t@ 19e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x480>\n-\tvfma.f64\td17, d19, d20\n-\tvstr\td20, [sp, #496]\t@ 0x1f0\n-\tvmov.f64\td20, d21\n-\tvstr\td23, [sp, #104]\t@ 0x68\n-\tvldr\td21, [pc, #520]\t@ 19e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x488>\n-\tvfma.f64\td20, d13, d22\n-\tvstr\td22, [sp, #256]\t@ 0x100\n-\tvldr\td22, [pc, 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d28\n-\tvdiv.f64\td16, d23, d9\n-\tvldr\td23, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td23, d16, d23\n-\tvmul.f64\td16, d31, d22\n-\tvdiv.f64\td31, d19, d24\n-\tvldr\td24, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td23, d23, d6\n-\tvldr\td6, [sp, #8]\n-\tvmul.f64\td16, d16, d27\n-\tvmul.f64\td27, d30, d14\n-\tvldr\td30, [pc, #-412]\t@ 1f28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9c8>\n-\tvmul.f64\td7, d6, d3\n-\tvdiv.f64\td26, d23, d6\n-\tvldr\td23, [sp, #216]\t@ 0xd8\n-\tvldr\td6, [sp, #136]\t@ 0x88\n-\tvmul.f64\td16, d16, d23\n-\tvmul.f64\td27, d27, d6\n-\tvldr\td6, [sp, #16]\n-\tvmul.f64\td16, d16, d24\n-\tvldr\td24, [sp, #176]\t@ 0xb0\n-\tvfms.f64\td27, d6, d8\n-\tvmul.f64\td28, d6, d3\n-\tvldr\td6, [sp, #376]\t@ 0x178\n-\tvfma.f64\td16, d29, d25\n-\tvldr\td8, [sp, #32]\n-\tvmul.f64\td9, d26, d17\n-\tvmul.f64\td26, d6, d30\n-\tvdiv.f64\td17, d19, d23\n-\tvadd.f64\td19, d18, d18\n-\tvldr\td30, [sp, #608]\t@ 0x260\n-\tvmul.f64\td19, d19, d24\n-\tvmul.f64\td24, d3, d5\n-\tvldr\td3, [sp, #256]\t@ 0x100\n-\tvsub.f64\td25, d30, d8\n-\tvldr\td1, [sp, #344]\t@ 0x158\n-\tvmov.f64\td30, d16\n-\tvldr\td21, [sp, #312]\t@ 0x138\n-\tvnmul.f64\td23, d24, d3\n-\tvldr\td4, [sp, #184]\t@ 0xb8\n-\tvfma.f64\td23, d13, d26\n-\tvmul.f64\td26, d22, d10\n-\tvldr\td20, [sp, #288]\t@ 0x120\n-\tvldr\td8, [sp, #576]\t@ 0x240\n-\tvldr\td2, [sp, #320]\t@ 0x140\n-\tvldr\td16, [sp, #48]\t@ 0x30\n-\tvldr\td18, [sp, #280]\t@ 0x118\n-\tvmul.f64\td23, d23, d18\n-\tvmul.f64\td10, d17, d10\n-\tvmul.f64\td26, d26, d17\n-\tvmul.f64\td17, d21, d12\n-\tvmul.f64\td21, d21, d1\n-\tvmul.f64\td10, d10, d29\n-\tvmul.f64\td26, d26, d29\n-\tvfms.f64\td27, d28, d21\n-\tvldr\td29, [sp, #144]\t@ 0x90\n-\tvldr\td21, [sp, #168]\t@ 0xa8\n-\tvfms.f64\td11, d7, d17\n-\tvldr\td17, [sp, #152]\t@ 0x98\n-\tvmov.f64\td3, d27\n-\tvldr\td27, [sp, #120]\t@ 0x78\n-\tvfms.f64\td3, d29, d19\n-\tvldr\td29, [sp, #336]\t@ 0x150\n-\tvmul.f64\td19, d4, d20\n-\tvfnms.f64\td30, d11, d26\n-\tvldr\td26, [sp, #64]\t@ 0x40\n-\tvfma.f64\td19, d29, d21\n-\tvnmul.f64\td21, d17, d8\n-\tvldr\td11, [sp, #512]\t@ 0x200\n-\tvmov.f64\td17, #12\t@ 0x40600000 3.5\n-\tvmul.f64\td19, d19, d27\n-\tvmov.f64\td27, d23\n-\tvfms.f64\td19, d8, d2\n-\tvmov.f64\td8, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td23, d13, d6\n-\tvmul.f64\td8, d16, d8\n-\tvmul.f64\td16, d23, d18\n-\tvldr\td18, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td26, d26, d8\n-\tvfma.f64\td27, d11, d26\n-\tvldr\td11, [sp, #80]\t@ 0x50\n-\tvmul.f64\td11, d13, d11\n-\tvldr\td13, [sp, #496]\t@ 0x1f0\n-\tvfma.f64\td16, d13, d26\n-\tvldr\td26, [sp, #120]\t@ 0x78\n-\tvmov.f64\td13, d16\n-\tvfms.f64\td13, d24, d1\n-\tvldr\td24, [sp, #56]\t@ 0x38\n-\tvmul.f64\td16, d13, d18\n-\tvfma.f64\td16, d27, d20\n-\tvldr\td20, [sp, #160]\t@ 0xa0\n-\tvfma.f64\td21, d16, d26\n-\tvmul.f64\td16, d29, d17\n-\tvldr\td26, [sp, #88]\t@ 0x58\n-\tvmul.f64\td16, d16, d20\n-\tvldr\td20, [pc, #-740]\t@ 1f30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9d0>\n-\tvmul.f64\td20, d24, d20\n-\tvldr\td24, [sp, #192]\t@ 0xc0\n-\tvfms.f64\td19, d26, d16\n-\tvmov.f64\td18, d21\n-\tvldr\td21, [sp, #264]\t@ 0x108\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td30, d30, d20\n-\tvmul.f64\td20, d22, d20\n-\tvfma.f64\td19, d0, d30\n-\tvmov.f64\td22, d19\n-\tvldr\td19, [pc, #-776]\t@ 1f38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9d8>\n-\tvmul.f64\td19, d21, d19\n-\tvnmul.f64\td21, d11, d29\n-\tvmul.f64\td19, d19, d16\n-\tvfma.f64\td3, d1, d21\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvldr\td21, [pc, #-792]\t@ 1f40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9e0>\n-\tvmul.f64\td21, d16, d21\n-\tvmov.f64\td16, d4\n-\tvldr\td4, [sp, #112]\t@ 0x70\n-\tvmul.f64\td30, d3, d9\n-\tvneg.f64\td3, d24\n-\tvnmul.f64\td21, d29, d21\n-\tvfma.f64\td30, d2, d25\n-\tvfma.f64\td21, d16, d4\n-\tvldr\td16, [sp, #24]\n-\tvmul.f64\td25, d19, d17\n-\tvmul.f64\td17, d13, d17\n-\tvadd.f64\td16, d16, d16\n-\tvmul.f64\td25, d25, d29\n-\tvmul.f64\td16, d16, d29\n-\tvfms.f64\td21, d24, d16\n-\tvmul.f64\td16, d5, d12\n-\tvmul.f64\td24, d29, d31\n-\tvldr\td29, [sp, #88]\t@ 0x58\n-\tvnmul.f64\td16, d7, d16\n-\tvfma.f64\td16, d23, d12\n-\tvmov.f64\td26, d21\n-\tvldr\td21, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td17, d19, d17\n-\tvldr\td19, [sp, #592]\t@ 0x250\n-\tvmul.f64\td16, d10, d16\n-\tvmov.f64\td10, #8\t@ 0x40400000 3.0\n-\tvfms.f64\td18, d29, d21\n-\tvldr\td21, [pc, #-900]\t@ 1f48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9e8>\n-\tvldr\td29, [sp, #584]\t@ 0x248\n-\tvmul.f64\td24, d24, d10\n-\tvldr\td2, [sp, #96]\t@ 0x60\n-\tvmul.f64\td10, d13, d10\n-\tvmul.f64\td21, d19, d21\n-\tvldr\td19, [pc, #-916]\t@ 1f50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9f0>\n-\tvmul.f64\td19, d29, d19\n-\tvmul.f64\td22, d22, d21\n-\tvmov.f64\td23, d18\n-\tvldr\td18, [sp, #216]\t@ 0xd8\n-\tvfma.f64\td22, d19, d25\n-\tvldr\td25, [sp, #128]\t@ 0x80\n-\tvmul.f64\td17, d17, d19\n-\tvmov.f64\td19, d26\n-\tvfms.f64\td19, d25, d24\n-\tvmov.f64\td24, #104\t@ 0x3f400000 0.750\n-\tvneg.f64\td12, d25\n-\tvmul.f64\td24, d18, d24\n-\tvldr\td18, [sp, #536]\t@ 0x218\n-\tvfma.f64\td16, d18, d24\n-\tvldr\td18, [sp, #600]\t@ 0x258\n-\tvmul.f64\td20, d20, d16\n-\tvldr\td16, [pc, #-976]\t@ 1f58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9f8>\n-\tvfma.f64\td19, d30, d16\n-\tvldr\td16, [sp, #480]\t@ 0x1e0\n-\tvfma.f64\td23, d0, d20\n-\tvldr\td20, [pc, #-984]\t@ 1f60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xa00>\n-\tvfma.f64\td17, d23, d21\n-\tvldr\td21, [pc, #-984]\t@ 1f68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xa08>\n-\tvmul.f64\td21, d2, d21\n-\tvfms.f64\td19, d22, d21\n-\tvldr\td22, [pc, #-988]\t@ 1f70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xa10>\n-\tvmul.f64\td22, d16, d22\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvmul.f64\td20, d16, d20\n-\tvldr\td16, [r6]\n-\tvfms.f64\td16, d18, d22\n-\tvfms.f64\td16, d20, d19\n-\tvadd.f64\td19, d13, d13\n-\tvstr\td16, [r6]\n-\tvldr\td16, [pc, #480]\t@ 2550 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xff0>\n-\tvcmpe.f64\td15, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t2484 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xf24>\n-\tvldr\td22, [pc, #472]\t@ 2558 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xff8>\n-\tvldr\td23, [pc, #476]\t@ 2560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1000>\n-\tvldr\td16, [pc, #480]\t@ 2568 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1008>\n-\tvadd.f64\td22, d15, d22\n-\tvldr\td18, [sp, #32]\n-\tvadd.f64\td23, d15, d23\n-\tvfma.f64\td16, d15, d22\n-\tvldr\td22, [pc, #468]\t@ 2570 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1010>\n-\tvfma.f64\td22, d15, d23\n-\tvmul.f64\td16, d18, d16\n-\tvdiv.f64\td0, d16, d22\n-\tvldr\td16, [sp]\n-\tvmul.f64\td22, d5, d1\n-\tvmul.f64\td14, d6, d14\n+\tvldr\td7, [sp, #552]\t@ 0x228\n+\tvldr\td4, [sp, #232]\t@ 0xe8\n+\tvldr\td10, [sp, #296]\t@ 0x128\n+\tvldr\td13, [sp, #256]\t@ 0x100\n+\tvmul.f64\td6, d7, d4\n+\tvldr\td7, [sp, #568]\t@ 0x238\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvldr\td2, [pc, #-400]\t@ 1f58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9b0>\n+\tvmul.f64\td5, d10, d7\n+\tvldr\td7, [sp]\n+\tvldr\td10, [sp, #392]\t@ 0x188\n+\tvdiv.f64\td4, d13, d7\n+\tvmul.f64\td7, d7, d12\n+\tvmov.f64\td12, #16\t@ 0x40800000 4.0\n+\tvmov.f64\td13, #112\t@ 0x3f800000 1.0\n+\tvstr\td7, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td4, d4, d12\n+\tvldr\td12, [sp, #248]\t@ 0xf8\n+\tvdiv.f64\td7, d4, d12\n+\tvldr\td12, [sp, #288]\t@ 0x120\n+\tvldr\td4, [pc, #-444]\t@ 1f60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9b8>\n+\tvmul.f64\td7, d7, d12\n+\tvldr\td12, [sp, #320]\t@ 0x140\n+\tvmul.f64\td7, d7, d12\n+\tvmul.f64\td12, d1, d4\n+\tvldr\td4, [sp, #536]\t@ 0x218\n+\tvmul.f64\td4, d4, d6\n+\tvmul.f64\td12, d12, d10\n+\tvldr\td10, [sp, #104]\t@ 0x68\n+\tvmul.f64\td4, d4, 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0x60\n+\tvldr\td2, [sp, #352]\t@ 0x160\n+\tvldr\td3, [sp, #8]\n+\tvmul.f64\td11, d4, d11\n+\tvstr\td0, [sp, #104]\t@ 0x68\n+\tvmul.f64\td4, d2, d7\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td1, [sp, #408]\t@ 0x198\n+\tvldr\td12, [sp, #144]\t@ 0x90\n+\tvmov.f64\td2, d4\n+\tvnmls.f64\td2, d11, d3\n+\tvldr\td11, [sp, #616]\t@ 0x268\n+\tvsub.f64\td0, d11, d0\n+\tvldr\td11, [sp, #584]\t@ 0x248\n+\tvmul.f64\td4, d11, d12\n+\tvldr\td12, [sp, #64]\t@ 0x40\n+\tvmul.f64\td0, d0, d1\n+\tvstr\td2, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td2, d11, d1\n+\tvldr\td1, [sp, #368]\t@ 0x170\n+\tvldr\td11, [pc, #-692]\t@ 1f68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9c0>\n+\tvmul.f64\td3, d1, d11\n+\tvmul.f64\td1, d1, d12\n+\tvmov.f64\td12, d9\n+\tvldr\td9, [sp, #24]\n+\tvmls.f64\td9, d1, d12\n+\tvldr\td1, [sp, #400]\t@ 0x190\n+\tvmov.f64\td12, d9\n+\tvldr\td9, [sp, #224]\t@ 0xe0\n+\tvmls.f64\td12, d5, d9\n+\tvldr\td5, [sp, #200]\t@ 0xc8\n+\tvldr\td9, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td3, d3, d5\n+\tvmul.f64\td5, d6, d8\n+\tvmul.f64\td8, d10, d8\n+\tvnmls.f64\td3, d1, d11\n+\tvmul.f64\td5, d5, d10\n+\tvmul.f64\td11, d8, d13\n+\tvldr\td10, [sp, #240]\t@ 0xf0\n+\tvldr\td1, [sp, #312]\t@ 0x138\n+\tvldr\td8, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td5, d5, d13\n+\tvldr\td13, [sp, #48]\t@ 0x30\n+\tvstr\td11, [sp, #192]\t@ 0xc0\n+\tvmov.f64\td11, d14\n+\tvldr\td14, [sp, #344]\t@ 0x158\n+\tvnmls.f64\td11, d3, d5\n+\tvmul.f64\td5, d10, d14\n+\tvldr\td10, [sp, #336]\t@ 0x150\n+\tvmla.f64\td5, d1, d10\n+\tvmov.f64\td1, d2\n+\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td3, d13, d10\n+\tvldr\td13, [sp, #304]\t@ 0x130\n+\tvldr\td10, [sp, #112]\t@ 0x70\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tvnmls.f64\td1, d5, d9\n+\tvldr\td5, [sp, #80]\t@ 0x50\n+\tvmul.f64\td2, d5, d3\n+\tvldr\td5, [sp, #520]\t@ 0x208\n+\tvldr\td3, [sp, #96]\t@ 0x60\n+\tvmul.f64\td5, d5, d2\n+\tvmla.f64\td5, d8, d13\n+\tvldr\td8, [sp, #8]\n+\tvmul.f64\td3, d8, d3\n+\tvmul.f64\td14, d8, d10\n+\tvmul.f64\td8, d3, d13\n+\tvstr\td5, [sp, #24]\n+\tvmov.f64\td5, #12\t@ 0x40600000 3.5\n+\tvldr\td10, [sp, #504]\t@ 0x1f8\n+\tvldr\td13, [sp, #344]\t@ 0x158\n+\tvmla.f64\td8, d10, d2\n+\tvldr\td2, [sp, #64]\t@ 0x40\n+\tvldr\td10, [sp, #336]\t@ 0x150\n+\tvmls.f64\td8, d7, d2\n+\tvmul.f64\td7, d8, d13\n+\tvldr\td13, [sp, #24]\n+\tvmla.f64\td7, d13, d10\n+\tvldr\td10, [sp, #240]\t@ 0xf0\n+\tvldr\td13, [sp, #360]\t@ 0x168\n+\tvnmls.f64\td4, d7, d9\n+\tvldr\td7, [sp, #328]\t@ 0x148\n+\tvmov.f64\td9, d1\n+\tvldr\td1, [pc, #-936]\t@ 1f70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9c8>\n+\tvstr\td4, [sp, #80]\t@ 0x50\n+\tvmul.f64\td4, d10, d5\n+\tvldr\td10, [sp, #120]\t@ 0x78\n+\tvmul.f64\td4, d4, d7\n+\tvldr\td7, [pc, #-948]\t@ 1f78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9d0>\n+\tvmls.f64\td9, d4, d10\n+\tvldr\td4, [pc, #-948]\t@ 1f80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x9d8>\n+\tvldr\td10, [sp, #112]\t@ 0x70\n+\tvmul.f64\td4, d13, d4\n+\tvldr\td13, [sp, #264]\t@ 0x108\n+\tvmul.f64\td7, d10, d7\n+\tvldr\td10, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td4, d4, d13\n+\tvldr\td13, [sp, #280]\t@ 0x118\n+\tvmul.f64\td7, d7, d10\n \tvmul.f64\td1, d13, d1\n-\tvmul.f64\td10, d31, d10\n-\tvldr\td18, [pc, #440]\t@ 2578 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1018>\n-\tvmul.f64\td8, d16, d8\n-\tvldr\td16, [sp, #24]\n-\tvnmul.f64\td28, d28, d22\n-\tvldr\td22, [pc, #432]\t@ 2580 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1020>\n-\tvldr\td24, [r4]\n-\tvmul.f64\td19, d16, d19\n-\tvldr\td16, [sp, #32]\n-\tvmul.f64\td22, d13, d22\n-\tldr\tr2, [pc, #420]\t@ (2588 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1028>)\n-\tldr\tr3, [pc, #424]\t@ (258c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x102c>)\n-\tvsub.f64\td0, d0, d16\n-\tvldr\td16, [sp, #144]\t@ 0x90\n+\tvmov.f64\td13, d9\n+\tvldr\td9, [sp, #104]\t@ 0x68\n+\tvmul.f64\td11, d11, d1\n+\tvmul.f64\td6, d6, d1\n+\tvldr\td1, [sp, #312]\t@ 0x138\n+\tvmla.f64\td13, d11, d9\n+\tvldr\td9, [sp, #168]\t@ 0xa8\n+\tvnmls.f64\td7, d1, d9\n+\tvmul.f64\td1, d10, d14\n+\tvmov.f64\td9, d10\n+\tvldr\td10, [sp, #72]\t@ 0x48\n+\tvmls.f64\td12, d1, d2\n+\tvldr\td1, [sp, #32]\n+\tvstr\td13, [sp, #8]\n+\tvldr\td13, [sp, #152]\t@ 0x98\n+\tvadd.f64\td2, d1, d1\n+\tvmov.f64\td1, d9\n+\tvmul.f64\td2, d2, d9\n+\tvmla.f64\td0, d12, d10\n+\tvmov.f64\td12, d7\n+\tvldr\td7, [sp, #136]\t@ 0x88\n+\tvldr\td10, [sp, #120]\t@ 0x78\n+\tvmls.f64\td12, d2, d13\n+\tvldr\td2, [pc, #584]\t@ 2600 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1058>\n+\tvldr\td13, [sp, #8]\n+\tvmul.f64\td11, d7, d2\n+\tvldr\td7, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td11, d11, d7\n+\tvnmls.f64\td11, d3, d2\n+\tvmul.f64\td3, d4, d5\n+\tvmul.f64\td5, d8, d5\n+\tvldr\td2, [sp, #328]\t@ 0x148\n+\tvmul.f64\td3, d3, d9\n+\tvldr\td9, [sp]\n+\tvmul.f64\td2, d2, d5\n+\tvmul.f64\td5, d4, d5\n+\tvldr\td4, [sp, #592]\t@ 0x250\n+\tvmul.f64\td7, d1, d9\n+\tvldr\td1, [sp, #80]\t@ 0x50\n+\tvmov.f64\td9, #8\t@ 0x40400000 3.0\n+\tvmls.f64\td1, d2, d10\n+\tvldr\td2, [pc, #520]\t@ 2608 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1060>\n+\tvmul.f64\td7, d7, d9\n+\tvmul.f64\td9, d8, d9\n+\tvmul.f64\td2, d4, d2\n+\tvmul.f64\td4, d3, d2\n+\tvmul.f64\td5, d5, d2\n+\tvldr\td3, [sp, #600]\t@ 0x258\n+\tvldr\td2, [pc, #500]\t@ 2610 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1068>\n+\tvmul.f64\td2, d3, d2\n+\tvmov.f64\td3, d12\n+\tvldr\td12, [sp, #272]\t@ 0x110\n+\tvmla.f64\td4, d13, d2\n+\tvldr\td13, [sp, #40]\t@ 0x28\n+\tvmls.f64\td3, d7, d13\n+\tvmov.f64\td7, #104\t@ 0x3f400000 0.750\n+\tvldr\td13, [sp, #544]\t@ 0x220\n+\tvmul.f64\td7, d12, d7\n+\tvldr\td12, [sp, #192]\t@ 0xc0\n+\tvldr\td10, [sp, #104]\t@ 0x68\n+\tvmul.f64\td7, d7, d13\n+\tvldr\td13, [pc, #456]\t@ 2618 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1070>\n+\tvmla.f64\td7, d11, d12\n+\tvldr\td12, [pc, #456]\t@ 2620 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1078>\n+\tvadd.f64\td11, d8, d8\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [sp, #128]\t@ 0x80\n+\tvmul.f64\td13, d7, d13\n+\tvldr\td7, [pc, #444]\t@ 2628 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1080>\n+\tvmla.f64\td1, d6, d10\n+\tvldr\td6, [pc, #444]\t@ 2630 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1088>\n+\tvmla.f64\td3, d0, d7\n+\tvldr\td7, [sp, #488]\t@ 0x1e8\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [sp, #184]\t@ 0xb8\n+\tvmls.f64\td3, d4, d13\n+\tvmla.f64\td5, d1, d2\n+\tvmul.f64\td12, d7, d12\n+\tvldr\td7, [r6]\n+\tvstr\td5, [sp, #8]\n+\tvldr\td5, [sp, #608]\t@ 0x260\n+\tvmls.f64\td7, d6, d5\n+\tvmls.f64\td7, d3, d12\n+\tvstr\td7, [r6]\n+\tvldr\td7, [pc, #396]\t@ 2638 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1090>\n+\tvcmpe.f64\td15, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.w\t25ce <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1026>\n+\tvldr\td6, [pc, #388]\t@ 2640 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1098>\n+\tvldr\td7, [pc, #392]\t@ 2648 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10a0>\n+\tvldr\td5, [pc, #396]\t@ 2650 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10a8>\n+\tvadd.f64\td6, d15, d6\n+\tvadd.f64\td5, d15, d5\n+\tvmla.f64\td7, d6, d15\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #380]\t@ 2658 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10b0>\n+\tvmla.f64\td6, d5, d15\n+\tvdiv.f64\td0, d7, d6\n+\tvldr\td7, [sp, #16]\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvmul.f64\td10, d7, d6\n+\tvldr\td6, [sp, #160]\t@ 0xa0\n+\tvldr\td7, [sp, #96]\t@ 0x60\n+\tldr\tr2, [pc, #356]\t@ (2668 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10c0>)\n+\tldr\tr3, [pc, #360]\t@ (266c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10c4>)\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [sp, #32]\n \tadd\tr2, pc\n-\tvfma.f64\td28, d16, d8\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvfma.f64\td28, d16, d14\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvnmul.f64\td16, d16, d22\n-\tvfms.f64\td28, d11, d1\n-\tvfma.f64\td16, d27, d4\n-\tvfma.f64\td16, d3, d19\n-\tvldr\td19, [sp, #152]\t@ 0x98\n-\tvmul.f64\td28, d28, d9\n-\tvfma.f64\td16, d10, d12\n-\tvfma.f64\td28, d19, d0\n-\tvfms.f64\td16, d17, d21\n-\tvfma.f64\td16, d28, d18\n-\tvfms.f64\td24, d16, d20\n-\tvstr\td24, [r4]\n+\tvmul.f64\td11, d6, d11\n+\tvldr\td6, [sp, #56]\t@ 0x38\n+\tvsub.f64\td0, d0, d6\n+\tvldr\td6, [sp]\n+\tvmul.f64\td9, d6, d9\n+\tvldr\td6, [sp, #144]\t@ 0x90\n+\tvmul.f64\td0, d0, d6\n+\tvldr\td6, [sp, #136]\t@ 0x88\n+\tvmul.f64\td6, d6, d5\n+\tvmul.f64\td6, d6, d4\n+\tvldr\td4, [sp, #224]\t@ 0xe0\n+\tvnmls.f64\td6, d10, d4\n+\tvldr\td4, [sp, #216]\t@ 0xd8\n+\tvmla.f64\td6, d7, d4\n+\tvmul.f64\td7, d8, d5\n+\tvmls.f64\td6, d7, d14\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvmla.f64\td0, d6, d7\n+\tvldr\td7, [pc, #264]\t@ 2660 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x10b8>\n+\tvldr\td6, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #24]\n+\tvnmls.f64\td8, d7, d6\n+\tvldr\td7, [sp, #152]\t@ 0x98\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmls.f64\td8, d11, d7\n+\tvldr\td7, [r4]\n+\tvmls.f64\td8, d9, d6\n+\tvldr\td6, [sp, #8]\n+\tvmls.f64\td8, d6, d13\n+\tvldr\td6, [pc, #152]\t@ 2628 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1080>\n+\tvmla.f64\td8, d0, d6\n+\tvmls.f64\td7, d8, d12\n+\tvstr\td7, [r4]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #628]\t@ 0x274\n+\tldr\tr3, [sp, #636]\t@ 0x27c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t2546 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xfe6>\n-\tadd.w\tsp, sp, #632\t@ 0x278\n+\tbne.n\t25fc <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x1054>\n+\tadd.w\tsp, sp, #640\t@ 0x280\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n \tvmov.f64\td0, d15\n-\tvstr\td17, [sp, #168]\t@ 0xa8\n-\tvstr\td20, [sp, #160]\t@ 0xa0\n-\tvstr\td23, [sp, #152]\t@ 0x98\n-\tvstr\td25, [sp, #144]\t@ 0x90\n-\tvstr\td16, [sp, #136]\t@ 0x88\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvldr\td25, [sp, #144]\t@ 0x90\n-\tvldr\td23, [sp, #152]\t@ 0x98\n-\tvmul.f64\td12, d16, d0\n-\tvldr\td20, [sp, #160]\t@ 0xa0\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvldr\td17, [sp, #168]\t@ 0xa8\n-\tb.w\t1a74 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x514>\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvldr\td1, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td8, d7, d0\n+\tb.w\t1ae0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x538>\n \tvmov.f64\td0, d15\n-\tvstr\td3, [sp, #128]\t@ 0x80\n-\tvstr\td4, [sp, #120]\t@ 0x78\n-\tvstr\td20, [sp, #112]\t@ 0x70\n-\tvstr\td21, [sp, #104]\t@ 0x68\n-\tvstr\td1, [sp, #96]\t@ 0x60\n-\tvstr\td27, [sp, #88]\t@ 0x58\n-\tvstr\td28, [sp, #72]\t@ 0x48\n-\tvstr\td31, [sp, #64]\t@ 0x40\n-\tvstr\td5, [sp, #48]\t@ 0x30\n-\tvstr\td6, [sp, #40]\t@ 0x28\n-\tvstr\td17, [sp, #16]\n-\tvstr\td19, [sp, #8]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvldr\td19, [sp, #8]\n-\tvldr\td17, [sp, #16]\n-\tvmul.f64\td0, d16, d0\n-\tvldr\td6, [sp, #40]\t@ 0x28\n-\tvldr\td5, [sp, #48]\t@ 0x30\n-\tvldr\td31, [sp, #64]\t@ 0x40\n-\tvldr\td28, [sp, #72]\t@ 0x48\n-\tvldr\td27, [sp, #88]\t@ 0x58\n-\tvldr\td1, [sp, #96]\t@ 0x60\n-\tvldr\td21, [sp, #104]\t@ 0x68\n-\tvldr\td20, [sp, #112]\t@ 0x70\n-\tvldr\td4, [sp, #120]\t@ 0x78\n-\tvldr\td3, [sp, #128]\t@ 0x80\n-\tb.n\t23a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xe48>\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvmul.f64\td0, d7, d0\n+\tb.n\t24e4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0xf3c>\n \tvmov.f64\td0, d15\n-\tvstr\td18, [sp, #600]\t@ 0x258\n-\tvstr\td1, [sp, #192]\t@ 0xc0\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n-\tvstr\td20, [sp, #176]\t@ 0xb0\n-\tvstr\td23, [sp, #168]\t@ 0xa8\n-\tvstr\td25, [sp, #160]\t@ 0xa0\n-\tvstr\td16, [sp, #152]\t@ 0x98\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tvldr\td25, [sp, #160]\t@ 0xa0\n-\tvldr\td23, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td16, d16, d0\n-\tvldr\td20, [sp, #176]\t@ 0xb0\n-\tvldr\td17, [sp, #184]\t@ 0xb8\n-\tvldr\td1, [sp, #192]\t@ 0xc0\n-\tvldr\td18, [sp, #600]\t@ 0x258\n-\tvstr\td16, [sp, #608]\t@ 0x260\n-\tvldr\td16, [sp, #152]\t@ 0x98\n-\tb.w\t1b60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x600>\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td7, [sp, #280]\t@ 0x118\n+\tvldr\td1, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [sp, #616]\t@ 0x268\n+\tb.w\t1bac <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0+0x604>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\tnop.w\n+\t.word\t0x97d453e4\n+\t.word\t0x3fef7e15\n+\t.word\t0x50429b6d\n+\t.word\t0x3fe20dd7\n+\t.word\t0x11111111\n+\t.word\t0x3ff11111\n+\t.word\t0x0af83437\n+\t.word\t0xbfaa99f1\n+\t.word\t0xfe791dd3\n+\t.word\t0xbfe7a245\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fe04201\n+\t.word\t0xbda12f68\n+\t.word\t0x3ff2f684\n \t.word\t0x00000000\n \t.word\t0x4085e000\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n-\t.word\t0xf67f4dbe\n-\t.word\t0x40142523\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n+\t.word\t0xf67f4dbe\n+\t.word\t0x40142523\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0x2c4fea23\n-\t.word\t0x3fe04201\n \t.word\t0xdc766309\n \t.word\t0xbfc7ca11\n-\t.word\t0x00000198\n+\t.word\t0x00000158\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00002590 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>:\n+00002670 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3352]\t@ 0xd18\n-\tvldr\td10, [pc, #1012]\t@ 2998 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x408>\n-\tvmul.f64\td14, d1, d1\n-\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n+\tstr.w\tr0, [ip, #3360]\t@ 0xd20\n+\tvldr\td10, [pc, #1012]\t@ 2a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x408>\n+\tvmul.f64\td11, d1, d1\n+\tsub.w\tsp, sp, #656\t@ 0x290\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n \tvmov.f64\td9, d0\n-\tsub.w\tsp, sp, #664\t@ 0x298\n-\tvmov.f64\td13, d1\n+\tvmov.f64\td14, d1\n \tvmul.f64\td10, d0, d10\n \tmov\tr5, r0\n-\tvmul.f64\td16, d14, d8\n-\tvmul.f64\td11, d14, d14\n+\tvstr\td1, [sp, #272]\t@ 0x110\n+\tvmul.f64\td1, d11, d12\n \tmov\tr6, r1\n \tmov\tr4, r2\n-\tvstr\td1, [sp, #128]\t@ 0x80\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n \tvmov.f64\td0, d10\n-\tvstr\td16, [sp, #352]\t@ 0x160\n+\tvstr\td1, [sp, #376]\t@ 0x178\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td24, d9, d9\n-\tvldr\td17, [pc, #952]\t@ 29a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x410>\n-\tldr\tr3, [sp, #752]\t@ 0x2f0\n-\tvmul.f64\td25, d10, d0\n-\tvldr\td20, [pc, #952]\t@ 29a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x418>\n-\tvmul.f64\td18, d0, d0\n-\tvmul.f64\td26, d11, d17\n-\tvldr\td22, [pc, #948]\t@ 29b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x420>\n-\tvdiv.f64\td17, d12, d24\n-\tvmul.f64\td21, d24, d24\n-\tvldr\td19, [r3]\n-\tvstr\td24, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td22, d14, d22\n-\tvdiv.f64\td25, d12, d25\n-\tvstr\td0, [sp, #56]\t@ 0x38\n-\tvmul.f64\td15, d19, d19\n-\tvmul.f64\td0, d10, d18\n-\tvdiv.f64\td27, d12, d21\n-\tvstr\td18, [sp, #360]\t@ 0x168\n-\tvmul.f64\td28, d22, d11\n-\tvldr\td10, [pc, #904]\t@ 29b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x428>\n-\tvdiv.f64\td22, d12, d18\n-\tvstr\td26, [sp, #416]\t@ 0x1a0\n-\tvdiv.f64\td18, d12, d0\n-\tvldr\td23, [pc, #896]\t@ 29c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x430>\n-\tvmul.f64\td26, d26, d10\n-\tvstr\td21, [sp, #152]\t@ 0x98\n-\tvldr\td3, [pc, #892]\t@ 29c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x438>\n+\tvmul.f64\td2, d9, d9\n+\tvldr\td4, [pc, #956]\t@ 2a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x410>\n+\tvmov.f64\td1, d0\n+\tldr\tr3, [sp, #744]\t@ 0x2e8\n+\tvldr\td5, [pc, #956]\t@ 2a88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x418>\n+\tvmul.f64\td0, d0, d0\n+\tvmul.f64\td13, d2, d2\n+\tvstr\td2, [sp, #288]\t@ 0x120\n+\tvmul.f64\td7, d10, d1\n+\tvmul.f64\td5, d11, d5\n+\tvstr\td1, [sp, #24]\n+\tvmul.f64\td10, d10, d0\n+\tvstr\td0, [sp, #384]\t@ 0x180\n+\tvmul.f64\td6, d13, d13\n+\tvdiv.f64\td15, d8, d7\n+\tvldr\td7, [r3]\n+\tvdiv.f64\td10, d8, d10\n+\tvstr\td6, [sp, #488]\t@ 0x1e8\n+\tvdiv.f64\td6, d4, d6\n+\tvdiv.f64\td4, d8, d13\n+\tvstr\td15, [sp, #328]\t@ 0x148\n+\tvstr\td10, [sp, #16]\n+\tvstr\td4, [sp, #432]\t@ 0x1b0\n+\tvmul.f64\td4, d13, d9\n+\tvdiv.f64\td3, d8, d4\n+\tvmul.f64\td4, d11, d11\n+\tvmul.f64\td5, d5, d4\n+\tvstr\td5, [sp, #160]\t@ 0xa0\n+\tvstr\td3, [sp, #144]\t@ 0x90\n+\tvmul.f64\td3, d7, d7\n+\tvmul.f64\td1, d3, d3\n+\tvstr\td3, [sp, #392]\t@ 0x188\n+\tvmul.f64\td7, d7, d1\n+\tvmul.f64\td5, d3, d1\n+\tvstr\td1, [sp, #440]\t@ 0x1b8\n+\tvstr\td7, [sp, #152]\t@ 0x98\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td7, [pc, #832]\t@ 2a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x420>\n+\tvstr\td5, [sp, #496]\t@ 0x1f0\n+\tvmov.f64\td5, d4\n+\tvmul.f64\td4, d4, d7\n+\tvstr\td6, [sp, #168]\t@ 0xa8\n+\tvdiv.f64\td7, d8, d13\n+\tvmul.f64\td14, d5, d14\n+\tvstr\td5, [sp, #120]\t@ 0x78\n+\tvstr\td4, [sp, #136]\t@ 0x88\n+\tvdiv.f64\td4, d8, d0\n+\tvldr\td0, [sp, #168]\t@ 0xa8\n+\tvstr\td14, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td7, d7, d1\n+\tvmul.f64\td6, d7, d15\n+\tvmov.f64\td15, d14\n+\tvldr\td7, [pc, #780]\t@ 2a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x428>\n+\tvldr\td14, [pc, #784]\t@ 2aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x430>\n+\tvstr\td4, [sp, #312]\t@ 0x138\n+\tvmul.f64\td15, d15, d7\n+\tvmov.f64\td7, d8\n+\tvmov.f64\td1, d15\n+\tvstr\td15, [sp, #464]\t@ 0x1d0\n+\tvdiv.f64\td15, d8, d2\n+\tvldr\td2, [sp, #160]\t@ 0xa0\n+\tvmla.f64\td7, d2, d0\n+\tvldr\td2, [sp, #136]\t@ 0x88\n+\tvmul.f64\td2, d2, d14\n+\tvmov.f64\td0, d2\n+\tvstr\td2, [sp, #448]\t@ 0x1c0\n+\tvmov.f64\td2, d6\n+\tvmla.f64\td7, d6, d0\n+\tvldr\td0, [sp, #152]\t@ 0x98\n+\tvldr\td6, [sp, #144]\t@ 0x90\n+\tvmul.f64\td6, d6, d0\n+\tvmul.f64\td6, d6, d10\n+\tvmov.f64\td10, d6\n+\tvstr\td6, [sp, #480]\t@ 0x1e0\n+\tvldr\td6, [pc, #708]\t@ 2aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x438>\n+\tvstr\td15, [sp, #320]\t@ 0x140\n+\tvmul.f64\td0, d1, d6\n+\tvldr\td6, [pc, #704]\t@ 2ab0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x440>\n+\tvmla.f64\td7, d0, d10\n+\tvstr\td0, [sp, #472]\t@ 0x1d8\n+\tvmov.f64\td1, d7\n+\tvstr\td7, [sp, #504]\t@ 0x1f8\n+\tvldr\td7, [pc, #692]\t@ 2ab8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x448>\n+\tvdiv.f64\td1, d8, d1\n+\tvmul.f64\td0, d5, d7\n+\tvldr\td7, [pc, #688]\t@ 2ac0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x450>\n+\tvmul.f64\td7, d11, d7\n+\tvstr\td0, [sp, #416]\t@ 0x1a0\n+\tvstr\td2, [sp, #56]\t@ 0x38\n+\tvmov.f64\td10, d7\n+\tvstr\td7, [sp, #400]\t@ 0x190\n+\tvmul.f64\td7, d0, d14\n \tvmov.f64\td0, d9\n-\tvmul.f64\td23, d11, d23\n-\tvstr\td28, [sp, #480]\t@ 0x1e0\n-\tvstr\td26, [sp, #424]\t@ 0x1a8\n-\tvstr\td23, [sp, #392]\t@ 0x188\n-\tvmul.f64\td23, d23, d10\n-\tvstr\td23, [sp, #400]\t@ 0x190\n-\tvmov.f64\td24, d17\n-\tvstr\td17, [sp, #288]\t@ 0x120\n-\tvmul.f64\td17, d15, d15\n-\tvstr\td25, [sp, #296]\t@ 0x128\n-\tvmul.f64\td29, d19, d17\n-\tvmul.f64\td19, d21, d21\n-\tvmul.f64\td30, d15, d17\n-\tvstr\td17, [sp, #144]\t@ 0x90\n-\tvmul.f64\td3, d22, d3\n-\tvstr\td22, [sp, #16]\n-\tvstr\td18, [sp, #8]\n-\tvstr\td19, [sp, #488]\t@ 0x1e8\n-\tvdiv.f64\td19, d20, d19\n-\tvmul.f64\td20, d21, d9\n-\tvstr\td30, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td21, d14, d8\n-\tvstr\td27, [sp, #408]\t@ 0x198\n-\tvstr\td29, [sp, #464]\t@ 0x1d0\n-\tvdiv.f64\td20, d12, d20\n-\tvmul.f64\td1, d21, d22\n-\tvmul.f64\td30, d19, d30\n-\tvmul.f64\td19, d27, d17\n-\tvmul.f64\td17, d19, d25\n-\tvmul.f64\td19, d11, d13\n-\tvstr\td20, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td20, d20, d29\n-\tvstr\td30, [sp, #504]\t@ 0x1f8\n-\tvmov.f64\td25, d19\n-\tvstr\td19, [sp, #432]\t@ 0x1b0\n-\tvldr\td19, [pc, #752]\t@ 29d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x440>\n-\tvmul.f64\td23, d23, d17\n-\tvstr\td17, [sp, #32]\n-\tvmul.f64\td25, d25, d19\n-\tvmov.f64\td19, d12\n-\tvfma.f64\td19, d28, d30\n-\tvstr\td25, [sp, #440]\t@ 0x1b8\n-\tvfma.f64\td19, d17, d26\n-\tvmul.f64\td26, d20, d18\n-\tvldr\td20, [pc, #724]\t@ 29d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x448>\n-\tvmul.f64\td20, d25, d20\n-\tvstr\td26, [sp, #472]\t@ 0x1d8\n-\tvfma.f64\td19, d20, d26\n-\tvstr\td20, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td26, d22, d24\n-\tvmul.f64\td21, d15, d26\n-\tvstr\td26, [sp, #384]\t@ 0x180\n-\tvmov.f64\td20, d19\n-\tvstr\td19, [sp, #512]\t@ 0x200\n-\tvldr\td19, [pc, #692]\t@ 29e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x450>\n-\tvdiv.f64\td20, d12, d20\n-\tvmul.f64\td25, d14, d19\n-\tvmul.f64\td19, d24, d15\n-\tvmul.f64\td22, d25, d8\n-\tvstr\td25, [sp, #368]\t@ 0x170\n-\tvfma.f64\td23, d22, d21\n-\tvstr\td22, [sp, #376]\t@ 0x178\n-\tvstr\td21, [sp, #48]\t@ 0x30\n-\tvstr\td19, [sp, #80]\t@ 0x50\n-\tvstr\td1, [sp]\n-\tvmov.f64\td18, d23\n-\tvldr\td23, [pc, #652]\t@ 29e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x458>\n-\tvstr\td18, [sp, #64]\t@ 0x40\n-\tvmul.f64\td22, d18, d20\n-\tvstr\td20, [sp, #40]\t@ 0x28\n-\tvmul.f64\td20, d19, d22\n-\tvstr\td22, [sp, #520]\t@ 0x208\n-\tvfma.f64\td3, d1, d20\n-\tvstr\td20, [sp, #72]\t@ 0x48\n-\tvmul.f64\td22, d3, d23\n-\tvstr\td3, [sp, #24]\n-\tvstr\td22, [sp, #136]\t@ 0x88\n+\tvmul.f64\td10, d10, d12\n+\tvmov.f64\td5, d7\n+\tvstr\td7, [sp, #424]\t@ 0x1a8\n+\tvldr\td7, [pc, #652]\t@ 2ac8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x458>\n+\tvstr\td10, [sp, #112]\t@ 0x70\n+\tvmul.f64\td10, d15, d3\n+\tvmul.f64\td5, d5, d2\n+\tvmul.f64\td2, d4, d15\n+\tvstr\td10, [sp, #104]\t@ 0x68\n+\tvmul.f64\td15, d3, d2\n+\tvmov.f64\td3, d5\n+\tvldr\td5, [sp, #112]\t@ 0x70\n+\tvstr\td2, [sp, #408]\t@ 0x198\n+\tvmla.f64\td3, d5, d15\n+\tvstr\td15, [sp, #72]\t@ 0x48\n+\tvstr\td1, [sp, #8]\n+\tvmul.f64\td1, d11, d12\n+\tvldr\td15, [sp, #8]\n+\tvmul.f64\td5, d3, d15\n+\tvmul.f64\td1, d1, d4\n+\tvstr\td3, [sp, #128]\t@ 0x80\n+\tvstr\td5, [sp, #512]\t@ 0x200\n+\tvmul.f64\td5, d10, d5\n+\tvstr\td1, [sp, #64]\t@ 0x40\n+\tvmov.f64\td10, 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\t.word\t0xb39c605a\n \t.word\t0xbfada696\n+\t.word\t0xfa48b0f4\n+\t.word\t0xbfb8f051\n \t.word\t0xdc766309\n \t.word\t0xbfc7ca11\n+\t.word\t0xa6db20a2\n+\t.word\t0xbfc0a036\n \t.word\t0x77bd9591\n \t.word\t0xbfb3c464\n+\t.word\t0x0af83437\n+\t.word\t0xbfaa99f1\n \t.word\t0x0b76c3bb\n \t.word\t0x3ef0e32e\n \t.word\t0xc28f5c29\n \t.word\t0xbfbc28f5\n \t.word\t0x5e247885\n \t.word\t0xbf55ce9e\n \t.word\t0x416c84c0\n@@ -2868,1377 +2929,1417 @@\n \t.word\t0x3fe04201\n \t.word\t0xfe791dd3\n \t.word\t0xbfe7a245\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n-\t.word\t0x949a5658\n-\t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n+\t.word\t0x949a5658\n+\t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0x5dae292a\n-\t.word\t0x408b6574\n \t.word\t0x63e07ae3\n \t.word\t0x3f82b04b\n-\t.word\t0x2e9d68cd\n-\t.word\t0x403d9bdb\n+\t.word\t0x5dae292a\n+\t.word\t0x408b6574\n \t.word\t0x00000000\n \t.word\t0x3fb00000\n \t.word\t0x55555555\n \t.word\t0x3ff55555\n+\t.word\t0x2e9d68cd\n+\t.word\t0x403d9bdb\n \t.word\t0xfc2dd756\n \t.word\t0x3ff8ac8b\n-\t.word\t0xe03dc2d9\n-\t.word\t0x4019e6cb\n \t.word\t0x55555555\n \t.word\t0x3fe55555\n-\t.word\t0xc9be45de\n-\t.word\t0x4033bd3c\n-\t.word\t0x0af83437\n-\t.word\t0xbfaa99f1\n-\tvldr\td20, [pc, #-124]\t@ 2a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x500>\n-\tvcmpe.f64\td3, d20\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t34e2 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xf52>\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvldr\td27, [pc, #-136]\t@ 2a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x508>\n-\tvldr\td20, [pc, #-132]\t@ 2aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x510>\n-\tvldr\td28, [pc, #-128]\t@ 2aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x518>\n-\tvadd.f64\td27, d16, d27\n-\tvadd.f64\td28, d16, d28\n-\tvfma.f64\td20, d16, d27\n-\tvldr\td27, [sp, #24]\n-\tvmul.f64\td20, d27, d20\n-\tvldr\td27, [pc, #-144]\t@ 2ab0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x520>\n-\tvfma.f64\td27, d16, d28\n-\tvdiv.f64\td12, d20, d27\n-\tvldr\td27, [pc, #-212]\t@ 2a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4e8>\n-\tvmov.f64\td20, #112\t@ 0x3f800000 1.0\n-\tvstr\td18, [sp, #272]\t@ 0x110\n-\tvstr\td7, [sp, #264]\t@ 0x108\n-\tvadd.f64\td16, d3, d27\n-\tvstr\td4, [sp, #256]\t@ 0x100\n-\tvstr\td26, [sp, #248]\t@ 0xf8\n-\tvstr\td6, [sp, #240]\t@ 0xf0\n-\tvstr\td30, [sp, #232]\t@ 0xe8\n-\tvstr\td16, [sp, #648]\t@ 0x288\n-\tvdiv.f64\td16, d20, d16\n-\tvstr\td25, [sp, #224]\t@ 0xe0\n-\tvstr\td5, [sp, #216]\t@ 0xd8\n-\tvstr\td23, [sp, #208]\t@ 0xd0\n-\tvstr\td2, [sp, #200]\t@ 0xc8\n-\tvstr\td17, [sp, #192]\t@ 0xc0\n-\tvstr\td21, [sp, #184]\t@ 0xb8\n-\tvstr\td19, [sp, #176]\t@ 0xb0\n-\tvstr\td24, [sp, #168]\t@ 0xa8\n-\tvstr\td1, [sp, #160]\t@ 0xa0\n-\tvstr\td22, [sp, #152]\t@ 0x98\n-\tvstr\td3, [sp, #144]\t@ 0x90\n-\tvmul.f64\td0, d3, d16\n-\tvstr\td16, [sp, #656]\t@ 0x290\n+\tvstr\td5, [sp, #608]\t@ 0x260\n+\tvstr\td7, [sp, #240]\t@ 0xf0\n+\tvldr\td7, [pc, #-180]\t@ 2b38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4c8>\n+\tvmul.f64\td7, d5, d7\n+\tvstr\td7, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td7, d4, d8\n+\tvldr\td8, [sp, #88]\t@ 0x58\n+\tvmla.f64\td7, d5, d8\n+\tvmul.f64\td5, d5, d3\n+\tvmla.f64\td6, d5, d2\n+\tvldr\td5, [pc, #-204]\t@ 2b40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4d0>\n+\tvldr\td2, [sp, #16]\n+\tvmul.f64\td5, d0, d5\n+\tvmul.f64\td7, d7, d15\n+\tvmul.f64\td2, d5, d2\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvstr\td2, [sp, #24]\n+\tvmul.f64\td2, d4, d5\n+\tvldr\td5, [pc, #-228]\t@ 2b48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4d8>\n+\tvldr\td4, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td0, d6, d5\n+\tvldr\td6, [pc, #-232]\t@ 2b50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4e0>\n+\tvmul.f64\td8, d2, d4\n+\tvldr\td5, [sp, #32]\n+\tvldr\td4, [sp, #200]\t@ 0xc8\n+\tvstr\td2, [sp, #184]\t@ 0xb8\n+\tvstr\td0, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td0, d7, d6\n+\tvldr\td7, [pc, #-252]\t@ 2b58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4e8>\n+\tvmul.f64\td15, d4, d5\n+\tvldr\td6, [sp]\n+\tvldr\td2, [sp, #288]\t@ 0x120\n+\tvstr\td0, [sp, #248]\t@ 0xf8\n+\tvdiv.f64\td0, d7, d9\n+\tvldr\td7, [pc, #-268]\t@ 2b60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4f0>\n+\tvdiv.f64\td3, d7, d6\n+\tvldr\td7, [pc, #-244]\t@ 2b80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x510>\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td0, [sp, #256]\t@ 0x100\n+\tvstr\td3, [sp, #48]\t@ 0x30\n+\tbmi.w\t374a <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x10da>\n+\tvldr\td4, [sp, #280]\t@ 0x118\n+\tvldr\td6, [pc, #-264]\t@ 2b88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x518>\n+\tvldr\td7, [pc, #-252]\t@ 2b98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x528>\n+\tvldr\td5, [pc, #-264]\t@ 2b90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x520>\n+\tvadd.f64\td6, d4, d6\n+\tvadd.f64\td5, d4, d5\n+\tvmla.f64\td7, d6, d4\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #-272]\t@ 2ba0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x530>\n+\tvmla.f64\td6, d5, d4\n+\tvdiv.f64\td7, d7, d6\n+\tvstr\td7, [sp, #368]\t@ 0x170\n+\tvldr\td6, [sp]\n+\tvadd.f64\td8, d8, d15\n+\tvldr\td7, [pc, #-352]\t@ 2b68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4f8>\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvstr\td1, [sp, #288]\t@ 0x120\n+\tvadd.f64\td7, d6, d7\n+\tvadd.f64\td8, d8, d14\n+\tvmov.f64\td5, d7\n+\tvstr\td7, [sp, #640]\t@ 0x280\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td7, d7, d5\n+\tvmul.f64\td0, d6, d7\n+\tvstr\td7, [sp, #648]\t@ 0x288\n \tbl\t0 \n R_ARM_THM_CALL\tlog\n-\tvldr\td26, [sp, #248]\t@ 0xf8\n-\tvldr\td23, [sp, #208]\t@ 0xd0\n-\tvadd.f64\td0, d0, d12\n-\tvldr\td16, [sp]\n-\tvmov.f64\td28, #80\t@ 0x3e800000 0.250\n-\tvadd.f64\td8, d8, d26\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tvldr\td20, [pc, #-332]\t@ 2a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4f0>\n-\tvldr\td12, [pc, #-328]\t@ 2a88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x4f8>\n-\tvldr\td3, [sp, #144]\t@ 0x90\n-\tvadd.f64\td8, d8, d23\n-\tvldr\td22, [sp, #152]\t@ 0x98\n-\tvfms.f64\td8, d26, d16\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvldr\td1, [sp, #160]\t@ 0xa0\n-\tvldr\td24, [sp, #168]\t@ 0xa8\n-\tvldr\td19, [sp, #176]\t@ 0xb0\n-\tvfma.f64\td8, d16, d17\n-\tvldr\td16, [sp, #88]\t@ 0x58\n-\tvldr\td17, [sp, #96]\t@ 0x60\n-\tvldr\td21, [sp, #184]\t@ 0xb8\n-\tvldr\td2, [sp, #200]\t@ 0xc8\n-\tvfma.f64\td8, d16, d17\n-\tvldr\td16, [sp, #16]\n-\tvldr\td17, [sp, #192]\t@ 0xc0\n-\tvldr\td5, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td28, d16, d28\n-\tvldr\td25, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td8, d0, d20\n-\tvldr\td20, [r5]\n-\tvldr\td30, [sp, #232]\t@ 0xe8\n-\tvldr\td6, [sp, #240]\t@ 0xf0\n-\tvldr\td4, [sp, #256]\t@ 0x100\n-\tvldr\td7, [sp, #264]\t@ 0x108\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tvmul.f64\td12, d8, d12\n-\tvfma.f64\td20, d12, d28\n-\tvstr\td20, [r5]\n-\tvldr\td20, [pc, #-440]\t@ 2a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x500>\n-\tvcmpe.f64\td3, d20\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t35e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x1058>\n-\tvldr\td16, [sp, #136]\t@ 0x88\n-\tvldr\td28, [pc, #-452]\t@ 2a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x508>\n-\tvldr\td29, [pc, #-440]\t@ 2aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x518>\n-\tvldr\td20, [pc, #-452]\t@ 2aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x510>\n-\tvadd.f64\td28, d16, d28\n-\tvldr\td27, [sp, #24]\n-\tvadd.f64\td29, d16, d29\n-\tvfma.f64\td20, d16, d28\n-\tvldr\td28, [pc, #-456]\t@ 2ab0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x520>\n-\tvfma.f64\td28, d16, d29\n-\tvmul.f64\td20, d27, d20\n-\tvdiv.f64\td0, d20, d28\n-\tvldr\td16, [sp, #616]\t@ 0x268\n-\tvadd.f64\td30, d30, d30\n-\tvldr\td20, [sp, #640]\t@ 0x280\n-\tvmul.f64\td21, d24, d21\n-\tvldr\td31, [sp, #64]\t@ 0x40\n-\tvmul.f64\td25, d25, d25\n-\tvmul.f64\td13, d13, d16\n-\tvldr\td16, [sp, #632]\t@ 0x278\n-\tvldr\td27, [sp, #376]\t@ 0x178\n-\tvmul.f64\td8, d15, d31\n-\tvldr\td31, [sp, #384]\t@ 0x180\n-\tvmul.f64\td28, d16, d20\n-\tvldr\td16, [sp, #600]\t@ 0x258\n-\tvldr\td20, [sp, #608]\t@ 0x260\n-\tvadd.f64\td27, d27, d27\n-\tvstr\td30, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td20, d16, d20\n-\tvdiv.f64\td16, d23, d13\n-\tvldr\td23, [sp, #488]\t@ 0x1e8\n-\tvstr\td27, [sp, #144]\t@ 0x90\n-\tvldr\td27, [sp, #288]\t@ 0x120\n-\tvmul.f64\td29, d23, d9\n-\tvmul.f64\td9, d24, d9\n-\tvldr\td23, [sp, #512]\t@ 0x200\n-\tvdiv.f64\td13, d15, d9\n-\tvmul.f64\td23, d23, d23\n-\tvstr\td16, [sp, #176]\t@ 0xb0\n-\tvldr\td16, [sp, #352]\t@ 0x160\n-\tvmul.f64\td30, d16, d31\n-\tvmul.f64\td31, d16, d27\n-\tvldr\td16, [sp, #120]\t@ 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d25\n-\tvmul.f64\td20, d26, d23\n-\tvstr\td23, [sp, #192]\t@ 0xc0\n-\tvldr\td23, [pc, #-704]\t@ 2ac8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x538>\n-\tvstr\td20, [sp, #64]\t@ 0x40\n-\tvmul.f64\td16, d16, d21\n-\tvldr\td21, [pc, #-708]\t@ 2ad0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x540>\n-\tvdiv.f64\td30, d21, d14\n-\tvldr\td21, [pc, #-708]\t@ 2ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x548>\n-\tvdiv.f64\td14, d10, d28\n-\tvmul.f64\td16, d16, d27\n-\tvdiv.f64\td27, d10, d24\n-\tvldr\td24, [sp, #408]\t@ 0x198\n-\tvmul.f64\td20, d24, d23\n-\tvldr\td24, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td23, d19, d23\n-\tvldr\td26, [sp, #296]\t@ 0x128\n-\tvldr\td19, [sp, #416]\t@ 0x1a0\n-\tvldr\td28, [sp, #568]\t@ 0x238\n-\tvldr\td25, [sp, #392]\t@ 0x188\n-\tvmul.f64\td20, d20, d17\n-\tvmul.f64\td19, d19, d21\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td25, d25, d21\n-\tvmul.f64\td21, d28, d21\n-\tvldr\td28, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td19, d19, 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d26\n-\tvfma.f64\td19, d17, d28\n-\tvldr\td28, [sp, #160]\t@ 0xa0\n-\tvldr\td1, [sp]\n-\tvmul.f64\td26, d28, d26\n-\tvldr\td28, [sp, #520]\t@ 0x208\n-\tvfma.f64\td26, d17, d24\n-\tvldr\td24, [sp, #368]\t@ 0x170\n-\tvldr\td17, [pc, #-900]\t@ 2af0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x560>\n-\tvfma.f64\td19, d30, d25\n-\tvldr\td25, [sp, #304]\t@ 0x130\n-\tvfma.f64\td26, d30, d21\n-\tvmul.f64\td21, d24, d17\n-\tvldr\td24, [sp, #560]\t@ 0x230\n-\tvmul.f64\td17, d24, d17\n-\tvmul.f64\td21, d21, d23\n-\tvmov.f64\td24, d20\n-\tvmul.f64\td23, d17, d23\n-\tvldr\td17, [pc, #-932]\t@ 2af8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x568>\n-\tvmul.f64\td15, d15, d17\n-\tvmul.f64\td17, d31, d17\n-\tvfma.f64\td24, d31, d15\n-\tvldr\td31, [sp, #536]\t@ 0x218\n-\tvldr\td15, [sp, #8]\n-\tvmov.f64\td30, d24\n-\tvldr\td24, [sp, #40]\t@ 0x28\n-\tvmul.f64\td17, d17, d24\n-\tvmul.f64\td17, d17, d8\n-\tvldr\td8, [pc, #-964]\t@ 2b00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x570>\n-\tvfma.f64\td17, d28, d20\n-\tvldr\td28, [sp, #584]\t@ 0x248\n-\tvnmul.f64\td28, d30, d28\n-\tvnmul.f64\td30, d30, d31\n-\tvmov.f64\td31, #80\t@ 0x3e800000 0.250\n-\tvmul.f64\td20, d15, d31\n-\tvfma.f64\td19, d20, d21\n-\tvmul.f64\td21, d24, d13\n-\tvfma.f64\td26, d20, d23\n-\tvsub.f64\td20, d10, d1\n-\tvmov.f64\td23, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td20, d20, d8\n-\tvldr\td8, [sp, #656]\t@ 0x290\n-\tvnmul.f64\td21, d19, d21\n-\tvfma.f64\td21, d25, d16\n-\tvfms.f64\td28, d0, d26\n-\tvldr\td26, [sp, #280]\t@ 0x118\n-\tvfma.f64\td30, d0, d21\n-\tvmul.f64\td21, d24, d0\n-\tvmul.f64\td20, d20, d28\n-\tvldr\td24, [pc, #1016]\t@ 3310 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xd80>\n-\tvfnma.f64\td17, d19, d21\n-\tvldr\td21, [sp, #168]\t@ 0xa8\n-\tvldr\td19, [sp, #552]\t@ 0x228\n-\tvmul.f64\td20, d20, d26\n-\tvmul.f64\td24, d27, d24\n-\tvfma.f64\td17, d21, d16\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td31, d19, d16\n-\tvldr\td19, [sp, #128]\t@ 0x80\n-\tvfma.f64\td20, d30, d31\n-\tvmov.f64\td1, d17\n-\tvldr\td17, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td17, d17, d16\n-\tvmul.f64\td16, d19, d16\n-\tvldr\td19, [sp, #72]\t@ 0x48\n-\tvmul.f64\td21, d16, d22\n-\tvmov.f64\td22, d20\n-\tvldr\td20, [sp, #648]\t@ 0x288\n-\tvmul.f64\td19, d19, d21\n-\tvstr\td21, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td21, d26, d7\n-\tvstr\td19, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td19, d20, d20\n-\tvdiv.f64\td16, d10, d19\n-\tvmov.f64\td10, d15\n-\tvldr\td19, [pc, #920]\t@ 3318 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xd88>\n-\tvfms.f64\td8, d3, d16\n-\tvdiv.f64\td16, d20, d3\n-\tvldr\td20, [sp, #312]\t@ 0x138\n-\tvldr\td25, [sp, #120]\t@ 0x78\n-\tvmul.f64\td24, d24, d20\n-\tvldr\td20, [pc, #904]\t@ 3320 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xd90>\n-\tvmul.f64\td27, d25, d19\n-\tvfms.f64\td22, d1, d27\n-\tvfma.f64\td22, d21, d24\n-\tvldr\td24, [sp, #624]\t@ 0x270\n-\tvmul.f64\td8, d8, d16\n-\tvmov.f64\td16, d1\n-\tvfms.f64\td16, d15, d20\n-\tvldr\td20, [sp, #312]\t@ 0x138\n-\tvldr\td15, [sp]\n-\tvmul.f64\td15, d15, d23\n-\tvmul.f64\td23, d20, d23\n-\tvmul.f64\td20, d20, d29\n-\tvstr\td23, [sp, #72]\t@ 0x48\n-\tvmul.f64\td23, d1, d15\n-\tvstr\td20, [sp, #56]\t@ 0x38\n-\tvldr\td20, [pc, #848]\t@ 3328 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xd98>\n-\tvstr\td15, [sp, #144]\t@ 0x90\n-\tvldr\td15, [pc, #848]\t@ 3330 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xda0>\n-\tvmul.f64\td20, d6, d20\n-\tvmul.f64\td15, d10, d15\n-\tvldr\td10, [sp, #152]\t@ 0x98\n-\tvmul.f64\td7, d7, d20\n-\tvfma.f64\td7, d24, d19\n-\tvldr\td19, [pc, #832]\t@ 3338 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xda8>\n-\tvmul.f64\td24, d26, d18\n-\tvmul.f64\td19, d6, d19\n-\tvldr\td6, [sp, #56]\t@ 0x38\n-\tvadd.f64\td24, d24, d24\n-\tvfma.f64\td22, d23, d6\n-\tvldr\td23, [pc, #816]\t@ 3340 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d29, d1\n-\tvldr\td28, [pc, #708]\t@ 3350 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdc0>\n-\tvfms.f64\td16, d30, d18\n-\tvldr\td18, [sp, #32]\n-\tvfma.f64\td26, d5, d25\n-\tvmov.f64\td25, #120\t@ 0x3fc00000 1.5\n-\tvldr\td5, [sp, #432]\t@ 0x1b0\n-\tvmul.f64\td22, d22, d25\n-\tvmul.f64\td23, d23, d25\n-\tvldr\td25, [pc, #684]\t@ 3358 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdc8>\n-\tvmul.f64\td28, d5, d28\n-\tvldr\td5, [sp, #504]\t@ 0x1f8\n-\tvmul.f64\td25, d10, d25\n-\tvmul.f64\td30, d25, d18\n-\tvfma.f64\td30, d5, d28\n-\tvldr\td5, [sp, #80]\t@ 0x50\n-\tvadd.f64\td25, d5, d5\n-\tvldr\td5, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td28, d24, d5\n-\tvmul.f64\td24, d14, d24\n-\tvldr\td14, [sp, #64]\t@ 0x40\n-\tvmul.f64\td25, d25, d1\n-\tvfma.f64\td16, d24, d23\n-\tvfnms.f64\td17, d22, d28\n-\tvldr\td24, [sp, #40]\t@ 0x28\n-\tvfma.f64\td17, d1, d6\n-\tvmov.f64\td5, d16\n-\tvmul.f64\td16, d21, d15\n-\tvfma.f64\td5, d1, d7\n-\tvldr\td7, [sp, #280]\t@ 0x118\n-\tvfma.f64\td26, d14, d16\n-\tvmov.f64\td16, #4\t@ 0x40200000 2.5\n-\tvmov.f64\td28, d17\n-\tvldr\td17, [sp, #128]\t@ 0x80\n-\tvmul.f64\td19, d19, d16\n-\tvmul.f64\td20, d20, d16\n-\tvldr\td16, [pc, #584]\t@ 3360 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdd0>\n-\tvldr\td14, [pc, #588]\t@ 3368 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdd8>\n-\tvmul.f64\td16, d17, d16\n-\tvldr\td17, [sp, #48]\t@ 0x30\n-\tvnmul.f64\td14, d14, d7\n-\tvmul.f64\td16, d16, d17\n-\tvldr\td17, [pc, #576]\t@ 3370 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xde0>\n-\tvfma.f64\td26, d14, d25\n-\tvmul.f64\td18, d11, d17\n-\tvldr\td11, [sp, #472]\t@ 0x1d8\n-\tvfma.f64\td30, d11, d18\n-\tvldr\td18, [pc, #564]\t@ 3378 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xde8>\n-\tvmul.f64\td18, d10, d18\n-\tvmul.f64\td17, d9, d30\n-\tvldr\td30, [sp, #32]\n-\tvldr\td9, [sp, #304]\t@ 0x130\n-\tvfma.f64\td16, d30, d18\n-\tvnmul.f64\td11, d17, d9\n-\tvldr\td9, [sp, #224]\t@ 0xe0\n-\tvldr\td30, [sp, #120]\t@ 0x78\n-\tvmul.f64\td18, d16, d13\n-\tvmul.f64\td16, d0, d16\n-\tvldr\td13, [sp, #544]\t@ 0x220\n-\tvfma.f64\td11, d24, d18\n-\tvfma.f64\td9, d24, d16\n-\tvldr\td16, [sp, #168]\t@ 0xa8\n-\tvldr\td18, [sp, #184]\t@ 0xb8\n-\tvldr\td24, [sp, #152]\t@ 0x98\n-\tvfms.f64\td9, d16, d17\n-\tvldr\td16, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td11, d0, d11\n-\tvfma.f64\td11, d13, d16\n-\tvldr\td16, [sp, #320]\t@ 0x140\n-\tvldr\td13, [sp, #288]\t@ 0x120\n-\tvmul.f64\td4, d4, d9\n-\tvmul.f64\td10, d16, d9\n-\tvldr\td16, [sp, #336]\t@ 0x150\n-\tvmul.f64\td17, d16, d11\n-\tvmul.f64\td16, d11, d18\n-\tvmul.f64\td18, d4, d23\n-\tvmul.f64\td4, d4, d22\n-\tvldr\td22, [pc, #452]\t@ 3380 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdf0>\n-\tvldr\td23, [sp, #192]\t@ 0xc0\n-\tvmul.f64\td22, d13, d22\n-\tvmov.f64\td13, d26\n-\tvldr\td26, [sp, #104]\t@ 0x68\n-\tvfms.f64\td13, d26, d22\n-\tvmul.f64\td22, d30, d23\n-\tvmul.f64\td26, d21, d19\n-\tvmul.f64\td23, d2, d23\n-\tvmul.f64\td21, d21, d20\n-\tvmul.f64\td20, d10, d20\n-\tvmul.f64\td19, d10, d19\n-\tvfma.f64\td28, d22, d26\n-\tvldr\td26, [sp, #296]\t@ 0x128\n-\tvfma.f64\td5, d23, d21\n-\tvldr\td21, [pc, #400]\t@ 3388 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdf8>\n-\tvmov.f64\td25, d13\n-\tvldr\td13, [pc, #400]\t@ 3390 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe00>\n-\tvmul.f64\td21, d26, d21\n-\tvldr\td26, [sp, #88]\t@ 0x58\n-\tvfms.f64\td25, d26, d21\n-\tvldr\td26, [sp, #112]\t@ 0x70\n-\tvldr\td21, [pc, #388]\t@ 3398 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe08>\n-\tvmul.f64\td13, d26, d13\n-\tvmul.f64\td21, d24, d21\n-\tvldr\td24, [sp, #32]\n-\tvfma.f64\td25, d28, d13\n-\tvldr\td28, [sp, #8]\n-\tvmul.f64\td21, d21, d24\n-\tvldr\td24, [pc, #368]\t@ 33a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe10>\n-\tvmov.f64\td26, d25\n-\tvmov.f64\td25, d1\n-\tvfms.f64\td25, d28, d24\n-\tvldr\td28, [sp, #128]\t@ 0x80\n-\tvldr\td24, [pc, #356]\t@ 33a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe18>\n-\tvldr\td1, [sp, #48]\t@ 0x30\n-\tvmul.f64\td24, d28, d24\n-\tvldr\td28, [sp, #328]\t@ 0x148\n-\tvfma.f64\td21, d1, d24\n-\tvldr\td24, [sp, #160]\t@ 0xa0\n-\tvldr\td1, [sp, #592]\t@ 0x250\n-\tvmul.f64\td21, d0, d21\n-\tvldr\td0, [sp, #208]\t@ 0xd0\n-\tvfma.f64\td21, d1, d24\n-\tvmul.f64\td24, d28, d21\n-\tvfma.f64\td17, d2, d24\n-\tvldr\td24, [sp, #200]\t@ 0xc8\n-\tvfnms.f64\td17, d24, d18\n-\tvldr\td24, [sp, #216]\t@ 0xd8\n-\tvfma.f64\td17, d23, d20\n-\tvldr\td23, [sp, #344]\t@ 0x158\n-\tvldr\td20, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td18, d23, d21\n-\tvldr\td23, [sp, #16]\n-\tvfma.f64\td17, d9, d24\n-\tvfma.f64\td16, d30, d18\n-\tvldr\td18, [pc, #276]\t@ 33b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe20>\n-\tvmul.f64\td21, d21, d18\n-\tvldr\td18, [sp, #96]\t@ 0x60\n-\tvfnms.f64\td16, d20, d4\n-\tvldr\td20, [pc, #340]\t@ 3400 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe70>\n-\tvmul.f64\td21, d21, d7\n-\tvfma.f64\td16, d22, d19\n-\tvldr\td19, [pc, #256]\t@ 33b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe28>\n-\tvmov.f64\td22, d8\n-\tvfma.f64\td22, d0, d20\n-\tvldr\td20, [pc, #324]\t@ 3408 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe78>\n-\tvmul.f64\td19, d18, d19\n-\tvmov.f64\td18, d26\n-\tvfma.f64\td16, d9, d6\n-\tvmul.f64\td20, d25, d20\n-\tvfma.f64\td18, d5, d19\n-\tvfma.f64\td18, d20, d22\n-\tvldr\td20, [pc, #224]\t@ 33c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe30>\n-\tvmov.f64\td22, #80\t@ 0x3e800000 0.250\n-\tvmul.f64\td20, d23, d20\n-\tvldr\td23, [sp, #528]\t@ 0x210\n-\tvmul.f64\td20, d20, d18\n-\tvldr\td18, [pc, #212]\t@ 33c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe38>\n-\tvmul.f64\td18, d23, d18\n-\tvfma.f64\td20, d12, d18\n-\tvldr\td18, [r6]\n-\tvfma.f64\td18, d20, d22\n-\tvadd.f64\td20, d9, d9\n-\tb.n\t3410 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe80>\n+\tvmul.f64\td6, d6, d12\n+\tvnmls.f64\td6, d0, d5\n+\tvmov.f64\td3, d6\n+\tvldr\td6, [pc, #560]\t@ 3428 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdb8>\n+\tvmls.f64\td3, d10, d9\n+\tvstr\td3, [sp, #304]\t@ 0x130\n+\tvldr\td3, [sp, #296]\t@ 0x128\n+\tvmul.f64\td9, d10, d3\n+\tvldr\td10, [sp, #224]\t@ 0xe0\n+\tvmla.f64\td9, d2, d13\n+\tvldr\td2, [sp, #56]\t@ 0x38\n+\tvldr\td3, [sp, #352]\t@ 0x160\n+\tvmul.f64\td6, d10, d6\n+\tvmla.f64\td8, d6, d2\n+\tvldr\td2, [sp, #552]\t@ 0x228\n+\tvldr\td6, [pc, #520]\t@ 3430 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdc0>\n+\tvmul.f64\td6, d2, d6\n+\tvmla.f64\td1, d3, d6\n+\tvmul.f64\td3, d1, d13\n+\tvldr\td1, [sp, #16]\n+\tvadd.f64\td5, d5, d3\n+\tvstr\td5, [sp, #352]\t@ 0x160\n+\tvldr\td5, [pc, #500]\t@ 3438 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdc8>\n+\tvmul.f64\td5, d2, d5\n+\tvldr\td2, [pc, #500]\t@ 3440 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdd0>\n+\tvmul.f64\td2, d1, d2\n+\tvstr\td2, [sp, #160]\t@ 0xa0\n+\tvadd.f64\td2, d11, d11\n+\tvmul.f64\td2, d2, d4\n+\tvldr\td4, [sp, #336]\t@ 0x150\n+\tvmla.f64\td2, d7, d5\n+\tvldr\td7, [sp, #344]\t@ 0x158\n+\tvmul.f64\td1, d4, d0\n+\tvldr\td4, [sp, #384]\t@ 0x180\n+\tvmul.f64\td13, d13, d4\n+\tvstr\td2, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td2, d7, d0\n+\tvmul.f64\td7, d12, d4\n+\tvldr\td0, [sp, #112]\t@ 0x70\n+\tvstr\td13, [sp, #200]\t@ 0xc8\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td7, d15, d0\n+\tvldr\td0, [sp, #400]\t@ 0x190\n+\tvldr\td13, [sp, #144]\t@ 0x90\n+\tvldr\td4, [sp, #120]\t@ 0x78\n+\tvmls.f64\td0, d7, d13\n+\tvldr\td7, [pc, #420]\t@ 3448 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdd8>\n+\tvmul.f64\td7, d4, d7\n+\tvldr\td4, [sp, #480]\t@ 0x1e0\n+\tvmla.f64\td8, d7, d4\n+\tvldr\td7, [sp, #264]\t@ 0x108\n+\tvmul.f64\td4, d8, d7\n+\tvmov.f64\td7, #120\t@ 0x3fc00000 1.5\n+\tvmul.f64\td5, d5, d7\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [pc, #392]\t@ 3450 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xde0>\n+\tvmul.f64\td8, d14, d4\n+\tvldr\td14, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td7, d10, d7\n+\tvldr\td10, [sp, #56]\t@ 0x38\n+\tvmul.f64\td7, d7, d10\n+\tvmul.f64\td10, d2, d14\n+\tvldr\td14, [sp, #128]\t@ 0x80\n+\tvmla.f64\td0, d10, d14\n+\tvldr\td14, [sp, #184]\t@ 0xb8\n+\tvmov.f64\td13, d0\n+\tvadd.f64\td0, d14, d14\n+\tvldr\td14, [sp, #200]\t@ 0xc8\n+\tvmul.f64\td10, d1, d14\n+\tvldr\td14, [sp, #72]\t@ 0x48\n+\tvmul.f64\td0, d0, d15\n+\tvnmls.f64\td9, d10, d5\n+\tvldr\td10, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td1, d10, d1\n+\tvldr\td10, [sp, #304]\t@ 0x130\n+\tvmla.f64\td10, d1, d6\n+\tvldr\td1, [pc, #204]\t@ 33e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xd78>\n+\tvmla.f64\td10, d15, d3\n+\tvldr\td3, [sp, #216]\t@ 0xd8\n+\tvmla.f64\td9, d15, d3\n+\tvldr\td3, [pc, #300]\t@ 3458 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xde8>\n+\tvstr\td9, [sp, #120]\t@ 0x78\n+\tvldr\td9, [sp, #272]\t@ 0x110\n+\tvmul.f64\td3, d9, d3\n+\tvldr\td9, [sp, #8]\n+\tvmla.f64\td7, d3, d14\n+\tvldr\td14, [sp, #416]\t@ 0x1a0\n+\tvmul.f64\td3, d7, d1\n+\tvmov.f64\td1, d13\n+\tvnmls.f64\td8, d3, d9\n+\tvldr\td3, [sp, #104]\t@ 0x68\n+\tvmul.f64\td7, d3, d7\n+\tvmla.f64\td14, d8, d3\n+\tvldr\td8, [sp, #392]\t@ 0x188\n+\tvmla.f64\td8, d7, d9\n+\tvldr\td7, [sp, #288]\t@ 0x120\n+\tvldr\td3, [sp, #296]\t@ 0x128\n+\tvmls.f64\td8, d7, d4\n+\tvldr\td7, [sp, #360]\t@ 0x168\n+\tvmul.f64\td4, d7, d14\n+\tvmul.f64\td7, d14, d3\n+\tvldr\td3, [sp, #336]\t@ 0x150\n+\tvstr\td7, [sp, #264]\t@ 0x108\n+\tvmul.f64\td7, d3, d8\n+\tvldr\td3, [sp, #344]\t@ 0x158\n+\tvmul.f64\td9, d3, d8\n+\tvldr\td3, [sp, #32]\n+\tvmul.f64\td6, d7, d6\n+\tvmul.f64\td7, d7, d5\n+\tvldr\td5, [pc, #192]\t@ 3460 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdf0>\n+\tvmul.f64\td3, d3, d5\n+\tvmls.f64\td1, d0, d3\n+\tvstr\td3, [sp, #8]\n+\tvmov.f64\td3, #4\t@ 0x40200000 2.5\n+\tvldr\td0, [pc, #180]\t@ 3468 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xdf8>\n+\tvmul.f64\td5, d11, d3\n+\tvldr\td11, [sp, #312]\t@ 0x138\n+\tvmul.f64\td3, d11, d3\n+\tvldr\td11, [sp, #320]\t@ 0x140\n+\tvmul.f64\td0, d11, d0\n+\tvmov.f64\td11, d1\n+\tvldr\td1, [sp, #248]\t@ 0xf8\n+\tvmls.f64\td11, d0, d1\n+\tvldr\td1, [sp, #96]\t@ 0x60\n+\tvldr\td13, [sp, #376]\t@ 0x178\n+\tb.n\t34f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe88>\n \tnop\n-\tnop.w\n-\t.word\t0xfff7dd55\n-\t.word\t0x3f4a0ae2\n+\t.word\t0xc9be45de\n+\t.word\t0x4033bd3c\n+\t.word\t0xe03dc2d9\n+\t.word\t0x4019e6cb\n+\t.word\t0x0af83437\n+\t.word\t0xbfaa99f1\n \t.word\t0xdc766309\n \t.word\t0xbfc7ca11\n+\t.word\t0xfff7dd55\n+\t.word\t0x3f4a0ae2\n \t.word\t0x44569e2e\n \t.word\t0x3fce9274\n-\t.word\t0xfa48b0f4\n-\t.word\t0xbfb8f051\n-\t.word\t0x8e5474aa\n-\t.word\t0x3f051bf9\n \t.word\t0xa6db20a2\n \t.word\t0xbfc0a036\n-\t.word\t0xb39c605a\n-\t.word\t0xbfada696\n-\t.word\t0x77bd9591\n-\t.word\t0xbfa3c464\n+\t.word\t0xfa48b0f4\n+\t.word\t0xbfb8f051\n \t.word\t0x6bab49c6\n \t.word\t0x3f6aa9fe\n \t.word\t0xaefb2aae\n \t.word\t0x3fa7fe08\n-\t.word\t0x9470e5c6\n-\t.word\t0x3f741059\n+\t.word\t0xb39c605a\n+\t.word\t0xbfada696\n \t.word\t0x77bd9591\n-\t.word\t0xbfb3c464\n+\t.word\t0xbfa3c464\n+\t.word\t0x8e5474aa\n+\t.word\t0x3f051bf9\n \t.word\t0x46db86a4\n \t.word\t0x3f28bea8\n \t.word\t0x26d12521\n \t.word\t0x3f8508e2\n+\t.word\t0x9470e5c6\n+\t.word\t0x3f741059\n+\t.word\t0x77bd9591\n+\t.word\t0xbfb3c464\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n-\t.word\t0xc9be45de\n-\t.word\t0x4023bd3c\n-\t.word\t0x5e247885\n-\t.word\t0x3f55ce9e\n \t.word\t0x0f94a0b7\n \t.word\t0xbfda4852\n-\t.word\t0x44569e2e\n-\t.word\t0x3fde9274\n+\t.word\t0xc9be45de\n+\t.word\t0x4023bd3c\n \t.word\t0x1ff9d571\n \t.word\t0x3fe5eb4b\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n+\t.word\t0x5e247885\n+\t.word\t0x3f55ce9e\n+\t.word\t0x44569e2e\n+\t.word\t0x3fde9274\n \t.word\t0xc28f5c29\n \t.word\t0x3fbc28f5\n-\t.word\t0xfe791dd3\n-\t.word\t0xbfe7a245\n \t.word\t0xbda12f68\n \t.word\t0x3ff2f684\n+\t.word\t0xfe791dd3\n+\t.word\t0xbfe7a245\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0xfe791dd3\n-\t.word\t0xbfc7a245\n \t.word\t0x25676f30\n \t.word\t0x4001b6ec\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n-\tvstr\td18, [r6]\n-\tvldr\td18, [pc, #-72]\t@ 33d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe40>\n-\tvcmpe.f64\td3, d18\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t3582 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xff2>\n-\tvldr\td24, [sp, #136]\t@ 0x88\n-\tvldr\td22, [pc, #-84]\t@ 33d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe48>\n-\tvldr\td18, [pc, #-72]\t@ 33e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe58>\n-\tvldr\td23, [pc, #-84]\t@ 33e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe50>\n-\tvadd.f64\td22, d24, d22\n-\tvadd.f64\td23, d24, d23\n-\tvfma.f64\td18, d24, d22\n-\tvldr\td22, [sp, #24]\n-\tvmul.f64\td18, d22, d18\n-\tvldr\td22, [pc, #-92]\t@ 33f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe60>\n-\tvfma.f64\td22, d24, d23\n-\tvdiv.f64\td0, d18, d22\n-\tvldr\td22, [sp, #72]\t@ 0x48\n-\tvnmul.f64\td18, d27, d9\n-\tvfma.f64\td18, d11, d31\n-\tvldr\td23, [pc, #-108]\t@ 33f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe68>\n-\tvmul.f64\td10, d10, d15\n-\tvldr\td24, [pc, #-108]\t@ 3400 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe70>\n-\tvmul.f64\td2, d9, d22\n-\tvldr\td22, [sp, #24]\n-\tvldr\td25, [pc, #-112]\t@ 3408 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe78>\n-\tvldr\td26, [r4]\n-\tvsub.f64\td0, d0, d22\n-\tvldr\td22, [sp, #80]\t@ 0x50\n-\tvmul.f64\td20, d22, d20\n-\tvldr\td22, [sp, #16]\n-\tvadd.f64\td18, d21, d18\n-\tvfma.f64\td8, d0, d24\n-\tvfms.f64\td18, d29, d2\n-\tvmul.f64\td23, d22, d23\n-\tvldr\td22, [sp]\n-\tvfms.f64\td18, d22, d21\n-\tvldr\td21, [sp, #56]\t@ 0x38\n-\tvldr\td22, [sp, #144]\t@ 0x90\n-\tvmul.f64\td8, d8, d25\n-\tvfma.f64\td18, d14, d20\n-\tvldr\td20, [sp, #64]\t@ 0x40\n-\tvfma.f64\td8, d21, d22\n-\tvfma.f64\td18, d20, d10\n-\tvfma.f64\td18, d17, d19\n-\tvmov.f64\td17, d18\n-\tvfma.f64\td17, d16, d13\n-\tvfma.f64\td17, d9, d8\n-\tvfma.f64\td26, d17, d23\n-\tvstr\td26, [r4]\n-\tadd.w\tsp, sp, #664\t@ 0x298\n+\t.word\t0xfe791dd3\n+\t.word\t0xbfc7a245\n+\tvstr\td12, [sp, #304]\t@ 0x130\n+\tvmul.f64\td0, d12, d13\n+\tvmul.f64\td1, d1, d13\n+\tvmul.f64\td13, d2, d5\n+\tvmul.f64\td2, d2, d3\n+\tvldr\td12, [sp, #120]\t@ 0x78\n+\tvmul.f64\td3, d9, d3\n+\tvmla.f64\td10, d2, d0\n+\tvmul.f64\td2, d9, d5\n+\tvldr\td5, [sp, #224]\t@ 0xe0\n+\tvmla.f64\td12, d13, d1\n+\tvldr\td13, [sp, #328]\t@ 0x148\n+\tvstr\td10, [sp, #248]\t@ 0xf8\n+\tvldr\td10, [pc, #-192]\t@ 3470 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe00>\n+\tvstr\td12, [sp, #120]\t@ 0x78\n+\tvldr\td12, [sp, #272]\t@ 0x110\n+\tvmul.f64\td10, d5, d10\n+\tvldr\td5, [sp, #56]\t@ 0x38\n+\tvmul.f64\td10, d10, d5\n+\tvldr\td5, [pc, #-208]\t@ 3478 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe08>\n+\tvmul.f64\td5, d13, d5\n+\tvldr\td13, [sp, #232]\t@ 0xe8\n+\tvmls.f64\td11, d5, d13\n+\tvldr\td5, [pc, #-216]\t@ 3480 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe10>\n+\tvldr\td13, [sp, #72]\t@ 0x48\n+\tvmul.f64\td5, d12, d5\n+\tvldr\td12, [sp, #104]\t@ 0x68\n+\tvmla.f64\td10, d5, d13\n+\tvldr\td5, [sp, #424]\t@ 0x1a8\n+\tvldr\td13, [sp, #96]\t@ 0x60\n+\tvmla.f64\td5, d10, d12\n+\tvldr\td10, [sp, #80]\t@ 0x50\n+\tvldr\td12, [sp, #304]\t@ 0x130\n+\tvmul.f64\td10, d10, d5\n+\tvmla.f64\td4, d10, d12\n+\tvldr\td10, [sp, #168]\t@ 0xa8\n+\tvldr\td12, [sp, #352]\t@ 0x160\n+\tvnmls.f64\td4, d6, d10\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvldr\td10, [sp, #264]\t@ 0x108\n+\tvmul.f64\td6, d6, d5\n+\tvmla.f64\td4, d3, d0\n+\tvmla.f64\td10, d6, d13\n+\tvldr\td13, [sp, #200]\t@ 0xc8\n+\tvldr\td6, [sp, #120]\t@ 0x78\n+\tvmov.f64\td3, d4\n+\tvldr\td4, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td3, d12, d8\n+\tvmov.f64\td12, d10\n+\tvldr\td10, [pc, #-312]\t@ 3488 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe18>\n+\tvmul.f64\td5, d5, d10\n+\tvnmls.f64\td12, d7, d13\n+\tvldr\td7, [sp, #32]\n+\tvldr\td13, [pc, #-320]\t@ 3490 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe20>\n+\tvmul.f64\td10, d5, d7\n+\tvldr\td7, [sp, #256]\t@ 0x100\n+\tvmla.f64\td12, d2, d1\n+\tvldr\td2, [sp, #216]\t@ 0xd8\n+\tvldr\td1, [sp, #16]\n+\tvmul.f64\td13, d7, d13\n+\tvmov.f64\td7, d11\n+\tvldr\td11, [sp, #240]\t@ 0xf0\n+\tvmla.f64\td12, d8, d2\n+\tvmov.f64\td2, d15\n+\tvldr\td5, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td7, d6, d13\n+\tvldr\td6, [pc, #-364]\t@ 3498 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe28>\n+\tvmls.f64\td2, d1, d6\n+\tvldr\td6, [pc, #-364]\t@ 34a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe30>\n+\tvldr\td1, [sp, #408]\t@ 0x198\n+\tvmul.f64\td6, d11, d6\n+\tvadd.f64\td11, d8, d8\n+\tvmla.f64\td7, d5, d6\n+\tvldr\td5, [pc, #-320]\t@ 34e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe70>\n+\tvmla.f64\td4, d1, d5\n+\tvldr\td5, [pc, #-320]\t@ 34e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe78>\n+\tvmul.f64\td5, d2, d5\n+\tvldr\td2, [sp, #176]\t@ 0xb0\n+\tvmla.f64\td7, d5, d4\n+\tvldr\td5, [pc, #-400]\t@ 34a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe38>\n+\tvldr\td4, [pc, #-396]\t@ 34b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe40>\n+\tvmul.f64\td5, d2, d5\n+\tvldr\td2, [sp, #368]\t@ 0x170\n+\tvmul.f64\td5, d5, d2\n+\tvldr\td2, [sp, #40]\t@ 0x28\n+\tvldr\td0, [sp]\n+\tvmul.f64\td4, d2, d4\n+\tvmla.f64\td5, d7, d4\n+\tvmov.f64\td4, #80\t@ 0x3e800000 0.250\n+\tvldr\td7, [r6]\n+\tvmla.f64\td7, d5, d4\n+\tvstr\td7, [r6]\n+\tvldr\td7, [pc, #-436]\t@ 34b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe48>\n+\tvcmpe.f64\td0, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.w\t377e <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x110e>\n+\tvldr\td2, [sp, #280]\t@ 0x118\n+\tvldr\td5, [pc, #-448]\t@ 34c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe50>\n+\tvldr\td7, [pc, #-436]\t@ 34d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe60>\n+\tvldr\td4, [pc, #-448]\t@ 34c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe58>\n+\tvadd.f64\td5, d2, d5\n+\tvadd.f64\td4, d2, d4\n+\tvmla.f64\td7, d5, d2\n+\tvldr\td5, [sp, #48]\t@ 0x30\n+\tvmul.f64\td7, d7, d5\n+\tvldr\td5, [pc, #-456]\t@ 34d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe68>\n+\tvmla.f64\td5, d4, d2\n+\tvdiv.f64\td0, d7, d5\n+\tvldr\td7, [sp, #184]\t@ 0xb8\n+\tvldr\td5, [sp, #152]\t@ 0x98\n+\tvldr\td4, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td7, [sp, #48]\t@ 0x30\n+\tvldr\td2, [sp, #112]\t@ 0x70\n+\tvldr\td1, [sp, #40]\t@ 0x28\n+\tvsub.f64\td0, d0, d7\n+\tvldr\td7, [sp, #160]\t@ 0xa0\n+\tvmul.f64\td9, d9, d7\n+\tvldr\td7, [sp, #64]\t@ 0x40\n+\tvmul.f64\td5, d7, d5\n+\tvldr\td7, [sp, #136]\t@ 0x88\n+\tvmul.f64\td7, d8, d7\n+\tvnmls.f64\td7, d14, d4\n+\tvldr\td4, [sp, #144]\t@ 0x90\n+\tvmul.f64\td4, d8, d4\n+\tvadd.f64\td7, d7, d10\n+\tvmls.f64\td7, d4, d2\n+\tvldr\td4, [sp, #24]\n+\tvldr\td2, [sp, #192]\t@ 0xc0\n+\tvmls.f64\td7, d4, d10\n+\tvldr\td4, [sp, #8]\n+\tvmls.f64\td7, d11, d4\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvmla.f64\td7, d9, d4\n+\tvldr\td4, [r4]\n+\tvmla.f64\td7, d3, d6\n+\tvldr\td6, [pc, #-572]\t@ 34e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe70>\n+\tvldr\td3, [pc, #-568]\t@ 34e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe78>\n+\tvmla.f64\td2, d0, d6\n+\tvldr\td6, [pc, #-568]\t@ 34f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xe80>\n+\tvmla.f64\td7, d12, d13\n+\tvmul.f64\td6, d1, d6\n+\tvmla.f64\td5, d2, d3\n+\tvmla.f64\td7, d5, d8\n+\tvmla.f64\td4, d7, d6\n+\tvstr\td4, [r4]\n+\tadd.w\tsp, sp, #656\t@ 0x290\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvldr\td0, [sp, #136]\t@ 0x88\n-\tvstr\td18, [sp, #272]\t@ 0x110\n-\tvstr\td7, [sp, #264]\t@ 0x108\n-\tvstr\td4, [sp, #256]\t@ 0x100\n-\tvstr\td26, [sp, #248]\t@ 0xf8\n-\tvstr\td6, [sp, #240]\t@ 0xf0\n-\tvstr\td30, [sp, #232]\t@ 0xe8\n-\tvstr\td25, [sp, #224]\t@ 0xe0\n-\tvstr\td5, [sp, #216]\t@ 0xd8\n-\tvstr\td23, [sp, #208]\t@ 0xd0\n-\tvstr\td2, [sp, #200]\t@ 0xc8\n-\tvstr\td3, [sp, #192]\t@ 0xc0\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n-\tvstr\td21, [sp, #176]\t@ 0xb0\n-\tvstr\td19, [sp, #168]\t@ 0xa8\n-\tvstr\td1, [sp, #152]\t@ 0x98\n-\tvstr\td22, [sp, #144]\t@ 0x90\n+\tvldr\td0, [sp, #280]\t@ 0x118\n+\tvstr\td2, [sp, #640]\t@ 0x280\n+\tvstr\td1, [sp, #296]\t@ 0x128\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td12, d0\n-\tvldr\td0, [sp, #136]\t@ 0x88\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td22, [sp, #144]\t@ 0x90\n-\tvldr\td1, [sp, #152]\t@ 0x98\n-\tvldr\td24, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td12, d12, d0\n-\tvldr\td19, [sp, #168]\t@ 0xa8\n-\tvldr\td21, [sp, #176]\t@ 0xb0\n-\tvldr\td17, [sp, #184]\t@ 0xb8\n-\tvldr\td3, [sp, #192]\t@ 0xc0\n-\tvldr\td2, [sp, #200]\t@ 0xc8\n-\tvldr\td23, [sp, #208]\t@ 0xd0\n-\tvldr\td5, [sp, #216]\t@ 0xd8\n-\tvldr\td25, [sp, #224]\t@ 0xe0\n-\tvldr\td30, [sp, #232]\t@ 0xe8\n-\tvldr\td6, [sp, #240]\t@ 0xf0\n-\tvldr\td26, [sp, #248]\t@ 0xf8\n-\tvldr\td4, [sp, #256]\t@ 0x100\n-\tvldr\td7, [sp, #264]\t@ 0x108\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tb.w\t2b48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x5b8>\n-\tvldr\td12, [sp, #136]\t@ 0x88\n-\tvstr\td31, [sp, #120]\t@ 0x78\n-\tvstr\td19, [sp, #112]\t@ 0x70\n-\tvmov.f64\td0, d12\n-\tvstr\td16, [sp, #104]\t@ 0x68\n-\tvstr\td17, [sp, #96]\t@ 0x60\n-\tvstr\td21, [sp, #88]\t@ 0x58\n-\tvstr\td27, [sp, #48]\t@ 0x30\n-\tvstr\td20, [sp, #40]\t@ 0x28\n-\tvstr\td29, [sp, #32]\n+\tvstr\td0, [sp, #288]\t@ 0x120\n+\tvldr\td0, [sp, #280]\t@ 0x118\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td7, [sp, #288]\t@ 0x120\n+\tvldr\td1, [sp, #296]\t@ 0x128\n+\tvldr\td2, [sp, #640]\t@ 0x280\n+\tvmul.f64\td7, d7, d0\n+\tvstr\td7, [sp, #368]\t@ 0x170\n+\tb.w\t2cbc <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x64c>\n+\tvldr\td15, [sp, #280]\t@ 0x118\n+\tvstr\td6, [sp, #16]\n+\tvstr\td3, [sp]\n+\tvmov.f64\td0, d15\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td18, d0\n-\tvmov.f64\td0, d12\n-\tvstr\td18, [sp, #8]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td18, [sp, #8]\n-\tvldr\td29, [sp, #32]\n-\tvldr\td20, [sp, #40]\t@ 0x28\n-\tvmul.f64\td0, d18, d0\n-\tvldr\td27, [sp, #48]\t@ 0x30\n-\tvldr\td21, [sp, #88]\t@ 0x58\n-\tvldr\td17, [sp, #96]\t@ 0x60\n-\tvldr\td16, [sp, #104]\t@ 0x68\n-\tvldr\td19, [sp, #112]\t@ 0x70\n-\tvldr\td31, [sp, #120]\t@ 0x78\n-\tb.n\t3454 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0xec4>\n-\tvldr\td0, [sp, #136]\t@ 0x88\n-\tvstr\td3, [sp, #192]\t@ 0xc0\n-\tvstr\td17, [sp, #184]\t@ 0xb8\n-\tvstr\td21, [sp, #176]\t@ 0xb0\n-\tvstr\td19, [sp, #168]\t@ 0xa8\n-\tvstr\td24, [sp, #160]\t@ 0xa0\n-\tvstr\td1, [sp, #152]\t@ 0x98\n-\tvstr\td22, [sp, #144]\t@ 0x90\n+\tvmov.f64\td7, d0\n+\tvmov.f64\td0, d15\n+\tvmov.f64\td15, d7\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td3, [sp]\n+\tvldr\td6, [sp, #16]\n+\tvmul.f64\td0, d15, d0\n+\tb.n\t36a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x1038>\n+\tvldr\td0, [sp, #280]\t@ 0x118\n \tbl\t0 \n R_ARM_THM_CALL\texp\n \tvmov.f64\td8, d0\n-\tvldr\td0, [sp, #136]\t@ 0x88\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td22, [sp, #144]\t@ 0x90\n-\tvldr\td1, [sp, #152]\t@ 0x98\n-\tvldr\td24, [sp, #160]\t@ 0xa0\n+\tvldr\td0, [sp, #280]\t@ 0x118\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td1, [sp, #288]\t@ 0x120\n+\tvldr\td2, [sp, #296]\t@ 0x128\n \tvmul.f64\td0, d8, d0\n-\tvldr\td19, [sp, #168]\t@ 0xa8\n-\tvldr\td21, [sp, #176]\t@ 0xb0\n-\tvldr\td17, [sp, #184]\t@ 0xb8\n-\tvldr\td3, [sp, #192]\t@ 0xc0\n-\tvldr\td2, [sp, #200]\t@ 0xc8\n-\tvldr\td23, [sp, #208]\t@ 0xd0\n-\tvldr\td5, [sp, #216]\t@ 0xd8\n-\tvldr\td25, [sp, #224]\t@ 0xe0\n-\tvldr\td30, [sp, #232]\t@ 0xe8\n-\tvldr\td6, [sp, #240]\t@ 0xf0\n-\tvldr\td26, [sp, #248]\t@ 0xf8\n-\tvldr\td4, [sp, #256]\t@ 0x100\n-\tvldr\td7, [sp, #264]\t@ 0x108\n-\tvldr\td18, [sp, #272]\t@ 0x110\n-\tb.w\t2c84 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x6f4>\n+\tb.w\t2d94 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0+0x724>\n \n-00003664 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>:\n+000037d4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3176]\t@ 0xc68\n-\tvldr\td14, [pc, #1000]\t@ 3a60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x3fc>\n-\tvmul.f64\td11, d1, d1\n+\tstr.w\tr0, [ip, #3184]\t@ 0xc70\n+\tvldr\td11, [pc, #1008]\t@ 3bd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x404>\n+\tvmul.f64\td7, d1, d1\n \tmov\tr4, r2\n-\tldr.w\tr2, [pc, #1188]\t@ 3b28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4c4>\n-\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr3, [pc, #1184]\t@ 3b2c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4c8>\n+\tldr.w\tr2, [pc, #1180]\t@ 3c90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4bc>\n+\tvmov.f64\td10, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr3, [pc, #1176]\t@ 3c94 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4c0>\n \tadd\tr2, pc\n-\tvmul.f64\td14, d0, d14\n-\tvmov.f64\td10, d0\n-\tvmul.f64\td16, d11, d8\n-\tsub.w\tsp, sp, #840\t@ 0x348\n-\tvmov.f64\td13, d2\n+\tvmul.f64\td11, d0, d11\n+\tvmul.f64\td8, d7, d10\n+\tvmov.f64\td9, d0\n+\tsub.w\tsp, sp, #832\t@ 0x340\n+\tvmov.f64\td12, d1\n \tldr\tr3, [r2, r3]\n-\tvmov.f64\td9, d1\n-\tvmov.f64\td0, d14\n+\tvmov.f64\td13, d2\n+\tvmov.f64\td0, d11\n \tmov\tr5, r0\n \tldr\tr3, [r3, #0]\n-\tstr\tr3, [sp, #836]\t@ 0x344\n+\tstr\tr3, [sp, #828]\t@ 0x33c\n \tmov.w\tr3, #0\n \tmov\tr6, r1\n-\tvstr\td16, [sp, #368]\t@ 0x170\n+\tvstr\td7, [sp]\n+\tvmov.f64\td14, #112\t@ 0x3f800000 1.0\n+\tvstr\td8, [sp, #384]\t@ 0x180\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td19, d11, d11\n-\tvmul.f64\td21, d10, d10\n-\tvldr\td18, [pc, #924]\t@ 3a68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x404>\n-\tvmov.f64\td12, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td28, d0, d0\n-\tvmul.f64\td22, d14, d0\n-\tvldr\td23, [pc, #916]\t@ 3a70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x40c>\n-\tvmul.f64\td16, d13, d13\n-\tvmul.f64\td20, d21, d21\n-\tvmul.f64\td29, d19, d18\n-\tvdiv.f64\td18, d12, d21\n-\tvldr\td17, [pc, #904]\t@ 3a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x414>\n-\tvdiv.f64\td15, d12, d28\n-\tvmul.f64\td14, d14, d28\n-\tvstr\td28, [sp, #376]\t@ 0x178\n-\tvmov.f64\td27, d13\n-\tvdiv.f64\td28, d12, d22\n-\tvmul.f64\td22, d20, d20\n-\tvdiv.f64\td30, d12, d20\n-\tvmul.f64\td17, d11, d17\n-\tvstr\td21, [sp, #248]\t@ 0xf8\n-\tvmov.f64\td13, d0\n-\tvstr\td20, [sp, #240]\t@ 0xf0\n-\tvmov.f64\td0, d10\n-\tvstr\td22, [sp, #520]\t@ 0x208\n-\tvdiv.f64\td22, d23, d22\n-\tvmul.f64\td23, d20, d10\n-\tvmul.f64\td31, d17, d19\n-\tvldr\td25, [pc, #844]\t@ 3a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x41c>\n-\tvdiv.f64\td17, d12, d14\n-\tvstr\td19, [sp, #232]\t@ 0xe8\n-\tvldr\td26, [pc, #840]\t@ 3a88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x424>\n-\tvdiv.f64\td23, d12, d23\n-\tvmul.f64\td25, d19, d25\n-\tvldr\td24, [pc, #836]\t@ 3a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x42c>\n-\tvstr\td29, [sp, #448]\t@ 0x1c0\n-\tvstr\td31, [sp, #512]\t@ 0x200\n-\tvmul.f64\td24, d11, d24\n-\tvstr\td25, [sp, #416]\t@ 0x1a0\n-\tvstr\td27, [sp, #176]\t@ 0xb0\n-\tvstr\td26, [sp, #16]\n-\tvldr\td1, [pc, #816]\t@ 3a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x434>\n-\tvstr\td24, [sp, #384]\t@ 0x180\n-\tvmul.f64\td24, d24, d8\n-\tvmov.f64\td21, d18\n-\tvstr\td18, [sp, #288]\t@ 0x120\n-\tvmul.f64\td18, d16, d16\n-\tvmul.f64\td1, d15, d1\n-\tvstr\td28, [sp, #296]\t@ 0x128\n-\tvstr\td30, [sp, #432]\t@ 0x1b0\n-\tvmul.f64\td20, d16, d18\n-\tvstr\td18, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td7, d22, d20\n-\tvmul.f64\td22, d30, d18\n-\tvstr\td20, [sp, #528]\t@ 0x210\n-\tvstr\td17, [sp, #32]\n-\tvstr\td23, [sp, #488]\t@ 0x1e8\n-\tvmul.f64\td20, d22, d28\n-\tvmul.f64\td22, d19, d9\n-\tvmul.f64\td28, d18, d27\n-\tvstr\td7, [sp, #536]\t@ 0x218\n-\tvmov.f64\td19, d22\n-\tvstr\td22, [sp, #464]\t@ 0x1d0\n-\tvldr\td22, [pc, #736]\t@ 3aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x43c>\n-\tvmul.f64\td23, d23, d28\n-\tvstr\td28, [sp, #496]\t@ 0x1f0\n-\tvmov.f64\td18, d20\n-\tvstr\td20, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td30, d19, d22\n-\tvmov.f64\td22, d12\n-\tvmul.f64\td19, d29, d26\n-\tvfma.f64\td22, d31, d7\n-\tvmul.f64\td28, d23, d17\n-\tvldr\td23, [pc, #704]\t@ 3aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x444>\n-\tvmul.f64\td17, d21, d16\n-\tvstr\td30, [sp, #472]\t@ 0x1d8\n-\tvfma.f64\td22, d20, d19\n-\tvmul.f64\td23, d30, d23\n-\tvstr\td28, [sp, #504]\t@ 0x1f8\n-\tvstr\td19, [sp, #456]\t@ 0x1c8\n-\tvstr\td23, [sp, #480]\t@ 0x1e0\n-\tvmov.f64\td20, d22\n-\tvmul.f64\td22, d15, d21\n-\tvfma.f64\td20, d23, d28\n-\tvmul.f64\td23, d25, d26\n-\tvmul.f64\td21, d11, d8\n-\tvstr\td22, [sp, #400]\t@ 0x190\n-\tvstr\td23, [sp, #424]\t@ 0x1a8\n-\tvmul.f64\td23, d23, d18\n-\tvmul.f64\td14, d21, d15\n-\tvmul.f64\td21, d16, d22\n-\tvdiv.f64\td18, d12, d20\n-\tvstr\td20, [sp, #544]\t@ 0x220\n-\tvstr\td24, [sp, #392]\t@ 0x188\n-\tvstr\td16, [sp, #216]\t@ 0xd8\n-\tvmov.f64\td16, d23\n-\tvfma.f64\td16, d24, d21\n-\tvldr\td23, [pc, #616]\t@ 3ab0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x44c>\n-\tvstr\td21, [sp, #408]\t@ 0x198\n-\tvstr\td17, [sp, #72]\t@ 0x48\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tvmul.f64\td20, d16, d18\n-\tvstr\td18, [sp, #80]\t@ 0x50\n-\tvmul.f64\td19, d17, d20\n-\tvstr\td20, [sp, #88]\t@ 0x58\n-\tvfma.f64\td1, d14, d19\n-\tvstr\td19, [sp]\n-\tvmul.f64\td21, d1, d23\n-\tvstr\td1, [sp, #208]\t@ 0xd0\n-\tvstr\td21, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td1, d9, d9\n+\tvldr\td5, [pc, #928]\t@ 3be0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x40c>\n+\tvstr\td9, [sp, #8]\n+\tvmov.f64\td7, d0\n+\tvmul.f64\td15, d13, d13\n+\tvmov.f64\td2, d13\n+\tvldr\td13, [sp]\n+\tvmul.f64\td0, d0, d0\n+\tvmul.f64\td4, d1, d1\n+\tvstr\td1, [sp, #456]\t@ 0x1c8\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n+\tvmul.f64\td7, d11, d7\n+\tvstr\td12, [sp, #80]\t@ 0x50\n+\tvmul.f64\td11, d11, d0\n+\tvstr\td0, [sp, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d4, d4\n+\tvstr\td4, [sp, #512]\t@ 0x200\n+\tvdiv.f64\td3, d14, d7\n+\tvldr\td7, [pc, #868]\t@ 3be8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x414>\n+\tvdiv.f64\td9, d14, d4\n+\tvstr\td2, [sp, #328]\t@ 0x148\n+\tvstr\td6, [sp, #592]\t@ 0x250\n+\tvmul.f64\td7, d13, d7\n+\tvdiv.f64\td6, d5, d6\n+\tvldr\td5, [sp, #8]\n+\tvdiv.f64\td11, d14, d11\n+\tvmul.f64\td5, d4, d5\n+\tvmul.f64\td4, d15, d15\n+\tvdiv.f64\td5, d14, d5\n+\tvstr\td4, [sp, #528]\t@ 0x210\n+\tvstr\td3, [sp, #360]\t@ 0x168\n+\tvstr\td9, [sp, #520]\t@ 0x208\n+\tvstr\td5, [sp, #112]\t@ 0x70\n+\tvmul.f64\td5, d13, d13\n+\tvmul.f64\td13, d7, d5\n+\tvldr\td7, [pc, #808]\t@ 3bf0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x41c>\n+\tvstr\td5, [sp, #488]\t@ 0x1e8\n+\tvstr\td13, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td13, d15, d4\n+\tvmul.f64\td6, d6, d13\n+\tvstr\td13, [sp, #600]\t@ 0x258\n+\tvmul.f64\td13, d5, d7\n+\tvmul.f64\td7, d9, d4\n+\tvmul.f64\td4, d4, d2\n+\tvmul.f64\td9, d5, d12\n+\tvldr\td2, [pc, #776]\t@ 3bf8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x424>\n+\tvstr\td6, [sp, #200]\t@ 0xc8\n+\tvdiv.f64\td6, d14, d1\n+\tvstr\td13, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td13, d7, d3\n+\tvldr\td7, [pc, #764]\t@ 3c00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x42c>\n+\tvmov.f64\td12, d4\n+\tvldr\td1, [sp, #192]\t@ 0xc0\n+\tvstr\td4, [sp, #576]\t@ 0x240\n+\tvdiv.f64\td4, d14, d0\n+\tvldr\td0, [sp, #200]\t@ 0xc8\n+\tvstr\td9, [sp, #552]\t@ 0x228\n+\tvmul.f64\td9, d9, d7\n+\tvmov.f64\td7, d14\n+\tvstr\td13, [sp, #536]\t@ 0x218\n+\tvmla.f64\td7, d1, d0\n+\tvldr\td1, [sp, #184]\t@ 0xb8\n+\tvstr\td9, [sp, #560]\t@ 0x230\n+\tvmul.f64\td1, d1, d2\n+\tvmla.f64\td7, d13, d1\n+\tvstr\td1, [sp, #544]\t@ 0x220\n+\tvmov.f64\td1, d7\n+\tvldr\td7, [pc, #704]\t@ 3c08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x434>\n+\tvmov.f64\td3, d6\n+\tvstr\td6, [sp, #352]\t@ 0x160\n+\tvldr\td6, [sp, #112]\t@ 0x70\n+\tvstr\td11, [sp, #40]\t@ 0x28\n+\tvstr\td2, [sp, #32]\n+\tvmul.f64\td6, d6, d12\n+\tvmul.f64\td0, d6, d11\n+\tvldr\td6, [pc, #680]\t@ 3c10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x43c>\n+\tvmul.f64\td11, d3, d15\n+\tvmul.f64\td6, d9, d6\n+\tvstr\td0, [sp, #584]\t@ 0x248\n+\tvstr\td11, [sp, #96]\t@ 0x60\n+\tvmla.f64\td1, d6, d0\n+\tvmul.f64\td0, d5, d7\n+\tvstr\td6, [sp, #568]\t@ 0x238\n+\tvldr\td7, [pc, #656]\t@ 3c18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x444>\n+\tvldr\td6, [sp]\n+\tvmul.f64\td5, d0, d2\n+\tvstr\td0, [sp, #496]\t@ 0x1f0\n+\tvldr\td0, [sp, #8]\n+\tvmul.f64\td9, d6, d7\n+\tvldr\td6, [pc, #640]\t@ 3c20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x44c>\n+\tvldr\td7, [pc, #644]\t@ 3c28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x454>\n+\tvstr\td1, [sp, #608]\t@ 0x260\n+\tvdiv.f64\td1, d14, d1\n+\tvstr\td5, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td5, d5, d13\n+\tvmul.f64\td13, d8, d4\n+\tvmul.f64\td8, d4, d3\n+\tvstr\td9, [sp, #464]\t@ 0x1d0\n+\tvmul.f64\td9, d9, d10\n+\tvmov.f64\td12, d13\n+\tvstr\td8, [sp, #392]\t@ 0x188\n+\tvmul.f64\td8, d15, d8\n+\tvstr\td9, [sp, #472]\t@ 0x1d8\n+\tvstr\td12, [sp, #176]\t@ 0xb0\n+\tvmla.f64\td5, d9, d8\n+\tvstr\td8, [sp, #480]\t@ 0x1e0\n+\tvmov.f64\td13, d5\n+\tvstr\td5, [sp, #400]\t@ 0x190\n+\tvmul.f64\td5, d5, d1\n+\tvstr\td1, [sp, #72]\t@ 0x48\n+\tvmul.f64\td8, d11, d5\n+\tvstr\td5, [sp, #208]\t@ 0xd0\n+\tvmov.f64\td11, d4\n+\tvmul.f64\td12, d12, d8\n+\tvstr\td8, [sp, #616]\t@ 0x268\n+\tvmul.f64\td8, d11, d10\n+\tvldr\td10, [pc, #548]\t@ 3c30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x45c>\n+\tvmov.f64\td5, d12\n+\tvmla.f64\td5, d4, d6\n+\tvmul.f64\td6, d5, d7\n+\tvstr\td5, [sp, #24]\n+\tvstr\td6, [sp, #336]\t@ 0x150\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvmov.f64\td29, #2\t@ 0x40100000 2.250\n-\tvldr\td22, [pc, #560]\t@ 3ab8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x454>\n-\tvmul.f64\td30, d15, d8\n-\tvldr\td18, [sp, #80]\t@ 0x50\n-\tvldr\td23, [pc, #556]\t@ 3ac0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x45c>\n-\tvmul.f64\td7, d16, d29\n-\tvmul.f64\td21, d16, d22\n-\tvldr\td19, [sp]\n-\tvldr\td22, [pc, #548]\t@ 3ac8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x464>\n-\tvmov.f64\td16, d12\n-\tvmov.f64\td3, d23\n-\tvldr\td17, [sp, #72]\t@ 0x48\n-\tvfma.f64\td3, d14, d19\n-\tvstr\td23, [sp, #160]\t@ 0xa0\n-\tvfma.f64\td22, d18, d21\n-\tvldr\td28, [pc, #528]\t@ 3ad0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x46c>\n-\tvldr\td24, [pc, #532]\t@ 3ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x474>\n-\tvmul.f64\td6, d11, d18\n-\tvldr\td27, [pc, #532]\t@ 3ae0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x47c>\n-\tvstr\td21, [sp, #320]\t@ 0x140\n-\tvstr\td30, [sp, #344]\t@ 0x158\n-\tvmul.f64\td29, d17, d27\n-\tvstr\td7, [sp, #336]\t@ 0x150\n-\tvmul.f64\td7, d7, d6\n-\tvstr\td0, [sp, #552]\t@ 0x228\n-\tvmul.f64\td20, d3, d3\n-\tvstr\td6, [sp, #592]\t@ 0x250\n-\tvmov.f64\td26, d22\n-\tvstr\td22, [sp, #560]\t@ 0x230\n-\tvsqrt.f64\td31, d3\n-\tvldr\td22, [pc, #492]\t@ 3ae8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x484>\n-\tvdiv.f64\td21, d12, d3\n-\tvmul.f64\td29, d29, d30\n-\tvfma.f64\td22, d20, d24\n-\tvmul.f64\td25, d3, d20\n-\tvmul.f64\td26, d17, d26\n-\tvldr\td24, [pc, #476]\t@ 3af0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x48c>\n-\tvdiv.f64\td23, d12, d20\n-\tvstr\td3, [sp, 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0x30\n+\tvmul.f64\td0, d4, d6\n+\tvldr\td6, [sp, #248]\t@ 0xf8\n+\tvmul.f64\td8, d8, d6\n+\tvmul.f64\td6, d13, d9\n+\tvstr\td0, [sp, #624]\t@ 0x270\n+\tvmov.f64\td4, d0\n+\tvstr\td8, [sp, #648]\t@ 0x288\n+\tvldr\td2, [sp, #32]\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvstr\td1, [sp, #120]\t@ 0x78\n+\tvmul.f64\td1, d1, d11\n+\tvdiv.f64\td9, d2, d6\n+\tvstr\td6, [sp, #32]\n+\tvmul.f64\td0, d0, d5\n+\tvldr\td5, [pc, #304]\t@ 3c88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4b4>\n+\tvstr\td1, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td6, d7, d5\n+\tvstr\td0, [sp, #64]\t@ 0x40\n+\tvmul.f64\td0, d8, d3\n+\tvmul.f64\td8, d1, d4\n+\tvstr\td6, [sp, #128]\t@ 0x80\n+\tvstr\td8, [sp, #344]\t@ 0x158\n+\tvstr\td9, [sp, #640]\t@ 0x280\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td27, [sp, #128]\t@ 0x80\n-\tvmov.f64\td22, #120\t@ 0x3fc00000 1.5\n-\tvldr\td20, [sp, #88]\t@ 0x58\n-\tadd\tr0, sp, #824\t@ 0x338\n-\tvdiv.f64\td30, d12, d13\n-\tvmul.f64\td31, d9, d22\n-\tvldr\td28, [sp, #24]\n-\tvmul.f64\td20, d20, d27\n-\tvldr\td27, [sp, #176]\t@ 0xb0\n-\tvstr\td0, [sp, #128]\t@ 0x80\n-\tvmul.f64\td28, d31, d28\n-\tvstr\td31, [sp, #616]\t@ 0x268\n-\tvsqrt.f64\td29, d20\n-\tvstr\td20, [sp, #624]\t@ 0x270\n-\tvdiv.f64\td20, d12, d10\n-\tvmul.f64\td28, d28, d30\n-\tvstr\td30, [sp, #136]\t@ 0x88\n-\tvstr\td28, [sp, #640]\t@ 0x280\n-\tvmul.f64\td27, d29, d27\n-\tvstr\td29, [sp, #312]\t@ 0x138\n-\tvstr\td20, [sp, #144]\t@ 0x90\n-\tvmul.f64\td0, d20, d27\n-\tvstr\td27, [sp, #632]\t@ 0x278\n-\tvmul.f64\td0, d0, d28\n-\tbl\t0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0>\n-\tvldr\td22, [pc, #248]\t@ 3b18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x4b4>\n-\tvldr\td23, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td17, d12\n-\tvldr\td19, [sp]\n-\tvfma.f64\td23, d15, d22\n-\tvldr\td22, [sp, #824]\t@ 0x338\n-\tvldr\td27, [sp, #128]\t@ 0x80\n-\tvldr\td25, [sp, #152]\t@ 0x98\n-\tvldr\td24, [sp, #56]\t@ 0x38\n-\tvldr\td26, [pc, #220]\t@ 3b20 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d20\n-\tvldr\td20, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td22, d22, d18\n-\tvstr\td19, [sp, #152]\t@ 0x98\n-\tvfma.f64\td22, d17, d23\n-\tvldr\td18, [sp, #224]\t@ 0xe0\n-\tvldr\td19, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td16, d22, d28\n-\tvstr\td16, [sp, #160]\t@ 0xa0\n-\tvldr\td16, [sp, #216]\t@ 0xd8\n-\tbmi.w\t4a20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x13bc>\n-\tvldr\td17, [sp, #192]\t@ 0xc0\n-\tvldr\td23, [pc, #756]\t@ 3f98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x934>\n-\tvldr\td22, [pc, #760]\t@ 3fa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x93c>\n-\tvldr\td24, [pc, #764]\t@ 3fa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x944>\n-\tvadd.f64\td23, d17, d23\n-\tvadd.f64\td24, d17, d24\n-\tvfma.f64\td22, d17, d23\n-\tvldr\td23, [sp, #24]\n-\tvmul.f64\td22, d23, d22\n-\tvldr\td23, [pc, #748]\t@ 3fb0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x94c>\n-\tvfma.f64\td23, d17, d24\n-\tvdiv.f64\td12, d22, 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d1\n+\tvldr\td6, [pc, #308]\t@ 4180 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x9ac>\n+\tvldr\td1, [sp, #448]\t@ 0x1c0\n+\tvmul.f64\td6, d8, d6\n+\tvldr\td8, [sp, #560]\t@ 0x230\n+\tvmul.f64\td6, d6, d8\n+\tvldr\td8, [sp, #544]\t@ 0x220\n+\tvmul.f64\td6, d6, d1\n+\tvldr\td1, [sp, #40]\t@ 0x28\n+\tvmla.f64\td6, d3, d1\n+\tvmov.f64\td3, #16\t@ 0x40800000 4.0\n+\tvmul.f64\td4, d8, d3\n+\tvldr\td8, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td3, d8, d3\n+\tvldr\td8, [sp, #536]\t@ 0x218\n+\tvmla.f64\td0, d4, d7\n+\tvldr\td4, [sp]\n+\tvmla.f64\td5, d3, d7\n+\tvldr\td7, [sp, #576]\t@ 0x240\n+\tvmov.f64\td3, d1\n+\tvnmla.f64\td0, d7, d6\n+\tvldr\td7, [pc, #340]\t@ 41f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa1c>\n+\tvmul.f64\td10, d10, d7\n+\tb.n\t4210 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa3c>\n \tnop\n \tnop.w\n+\t.word\t0x8240b780\n+\t.word\t0x3f88c7e2\n \t.word\t0xf9bf81bf\n \t.word\t0x40030035\n \t.word\t0x11111111\n \t.word\t0x3ff11111\n+\t.word\t0xb39c605a\n+\t.word\t0xbfada696\n \t.word\t0x77bd9591\n \t.word\t0xbfa3c464\n \t.word\t0xc28f5c29\n \t.word\t0xbfbc28f5\n \t.word\t0x7f3321d2\n \t.word\t0x4002d97c\n-\t.word\t0xb39c605a\n-\t.word\t0xbfada696\n \t.word\t0xa6e3f893\n \t.word\t0xc025b7d4\n \t.word\t0xa6db20a2\n \t.word\t0xbfc0a036\n \t.word\t0xfa48b0f4\n \t.word\t0xbfb8f051\n \t.word\t0x0b76c3bb\n \t.word\t0x3ef0e32e\n-\t.word\t0xdebd9018\n-\t.word\t0x4073c1fd\n-\t.word\t0x5e247885\n-\t.word\t0xbf55ce9e\n+\t.word\t0x0af83437\n+\t.word\t0xbfaa99f1\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n+\t.word\t0x5e247885\n+\t.word\t0xbf55ce9e\n \t.word\t0x87aa83cc\n \t.word\t0x3fdce71e\n+\t.word\t0xdebd9018\n+\t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0xca57a787\n@@ -4247,1085 +4348,1137 @@\n \t.word\t0x3fe27ddb\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n \t.word\t0xfe791dd3\n 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0x2c0\n-\tvldr\td30, [sp, #728]\t@ 0x2d8\n-\tvldr\td4, [sp, #320]\t@ 0x140\n-\tvmul.f64\td24, d31, d27\n-\tvldr\td27, [sp, #720]\t@ 0x2d0\n-\tvldr\td18, [sp, #88]\t@ 0x58\n-\tvnmul.f64\td10, d10, d4\n-\tvldr\td4, [sp, #520]\t@ 0x208\n-\tvmul.f64\td21, d27, d30\n-\tvldr\td27, [sp, #144]\t@ 0x90\n-\tvldr\td30, [sp, #176]\t@ 0xb0\n-\tvdiv.f64\td2, d4, d18\n-\tvldr\td19, [sp, #424]\t@ 0x1a8\n-\tvldr\td28, [sp, #312]\t@ 0x138\n-\tvmul.f64\td25, d27, d30\n-\tvldr\td30, [sp, #40]\t@ 0x28\n-\tvdiv.f64\td29, d4, d21\n-\tvldr\td27, [pc, #-660]\t@ 4068 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa04>\n-\tvldr\td21, [sp, #288]\t@ 0x120\n-\tvmul.f64\td17, d30, d23\n-\tvldr\td30, [sp, #16]\n-\tvldr\td20, [sp, #432]\t@ 0x1b0\n-\tvldr\td7, [sp, #640]\t@ 0x280\n-\tvdiv.f64\td31, d30, d24\n-\tvldr\td30, [sp, #616]\t@ 0x268\n-\tvdiv.f64\td23, d4, d22\n-\tvstr\td0, [sp, #40]\t@ 0x28\n-\tvmul.f64\td18, d30, d25\n-\tvldr\td30, [sp, #24]\n-\tvmul.f64\td18, d18, d27\n-\tvldr\td27, [sp, #632]\t@ 0x278\n-\tvmul.f64\td21, d21, d27\n-\tvldr\td27, [sp, #816]\t@ 0x330\n-\tvmul.f64\td18, d18, d28\n-\tvsub.f64\td27, d27, d30\n-\tvldr\td30, [sp, #392]\t@ 0x188\n-\tvstr\td27, [sp, #280]\t@ 0x118\n-\tvldr\td27, [sp, #400]\t@ 0x190\n-\tvmul.f64\td19, d27, d19\n-\tvfma.f64\td10, d15, d19\n-\tvldr\td19, [sp, #296]\t@ 0x128\n-\tvmul.f64\td10, d10, d30\n-\tvldr\td30, [sp, #568]\t@ 0x238\n-\tvldr\td6, [sp, #112]\t@ 0x70\n-\tvldr\td16, [sp, #376]\t@ 0x178\n-\tvfma.f64\td10, d30, d20\n-\tvmul.f64\td30, d18, d19\n-\tvldr\td19, [pc, #-772]\t@ 4070 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa0c>\n-\tvmul.f64\td18, d27, d12\n-\tvldr\td3, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td27, d31, d8\n-\tvldr\td15, [sp, #608]\t@ 0x260\n-\tvfma.f64\td30, d7, d21\n-\tvmul.f64\td16, d16, d19\n-\tvldr\td22, [sp, #336]\t@ 0x150\n-\tvldr\td5, [sp, #592]\t@ 0x250\n-\tvmul.f64\td12, d15, d12\n-\tvldr\td1, [sp, #760]\t@ 0x2f8\n-\tvmul.f64\td9, d9, d22\n-\tvldr\td26, [sp, #416]\t@ 0x1a0\n-\tvmul.f64\td16, d16, d3\n-\tvfma.f64\td9, d5, d18\n-\tvdiv.f64\td18, d4, d28\n-\tvmul.f64\td1, d6, d1\n-\tvmul.f64\td12, d12, d5\n-\tvldr\td28, [sp, #408]\t@ 0x198\n-\tvmul.f64\td16, d16, d22\n-\tvldr\td22, [sp]\n-\tvstr\td1, [sp, #88]\t@ 0x58\n-\tvmul.f64\td21, d28, d2\n-\tvldr\td1, [sp, #784]\t@ 0x310\n-\tvnmul.f64\td16, d5, d16\n-\tvldr\td5, [sp, #208]\t@ 0xd0\n-\tvfma.f64\td16, d22, d12\n-\tvldr\td22, [sp, #744]\t@ 0x2e8\n-\tvmul.f64\td9, d15, d9\n-\tvldr\td15, [pc, #-880]\t@ 4078 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa14>\n-\tvmov.f64\td12, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td20, d22, d22\n-\tvmul.f64\td21, d21, d12\n-\tvdiv.f64\td19, d4, d20\n-\tvldr\td20, [sp, #752]\t@ 0x2f0\n-\tvldr\td4, [sp, #600]\t@ 0x258\n-\tvfms.f64\td20, d1, d19\n-\tvdiv.f64\td19, d22, d1\n-\tvmul.f64\td22, d20, d19\n-\tvldr\td19, [pc, #-912]\t@ 4080 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa1c>\n-\tvmul.f64\td20, d25, d8\n-\tvmul.f64\td8, d18, d8\n-\tvmul.f64\td19, d5, d19\n-\tvldr\td5, [sp, #344]\t@ 0x158\n-\tvstr\td22, [sp]\n-\tvmul.f64\td18, d20, d18\n-\tvmul.f64\td8, d8, d7\n-\tvmul.f64\td19, d19, d5\n-\tvldr\td5, [sp, #80]\t@ 0x50\n-\tvmul.f64\td18, d18, d7\n+\tvldr\td6, [sp, #728]\t@ 0x2d8\n+\tvldr\td14, [sp, #280]\t@ 0x118\n \tvldr\td7, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td20, d5, d14\n-\tvfms.f64\td16, d4, d19\n-\tvldr\td4, [sp, #712]\t@ 0x2c8\n-\tvfms.f64\td13, d17, d20\n-\tvmul.f64\td19, d4, d15\n-\tvmul.f64\td4, d5, d11\n-\tvldr\td5, [sp, #272]\t@ 0x110\n-\tvmul.f64\td15, d6, d15\n-\tvmov.f64\td20, d16\n-\tvfms.f64\td20, d5, d4\n-\tvldr\td4, [sp, #104]\t@ 0x68\n-\tvfnms.f64\td30, d13, d18\n-\tvldr\td18, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td11, d18, d11\n-\tvmul.f64\td16, d18, d14\n-\tvadd.f64\td18, d4, d4\n-\tvfms.f64\td9, d5, d11\n-\tvldr\td5, [sp, #232]\t@ 0xe8\n-\tvnmul.f64\td17, d17, d16\n-\tvnmul.f64\td16, d15, d28\n-\tvmul.f64\td18, d18, d28\n-\tvldr\td11, [sp, #648]\t@ 0x288\n-\tvfma.f64\td17, d5, d14\n-\tvnmul.f64\td9, d9, d11\n-\tvmul.f64\td5, d8, d17\n-\tvldr\td17, [pc, #1004]\t@ 4890 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x122c>\n-\tvldr\td8, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td17, d7, d17\n-\tvldr\td7, [sp, #72]\t@ 0x48\n-\tvstr\td5, [sp, #208]\t@ 0xd0\n-\tvfma.f64\td16, d26, d7\n-\tvldr\td7, [sp, #248]\t@ 0xf8\n-\tvneg.f64\td4, d7\n-\tvfms.f64\td16, d7, d18\n-\tvldr\td7, [sp, #808]\t@ 0x328\n-\tvmul.f64\td18, d8, d7\n-\tvmul.f64\td22, d6, d7\n-\tvmov.f64\td7, d28\n-\tvmul.f64\td17, d17, d18\n-\tvstr\td18, [sp, #80]\t@ 0x50\n-\tvldr\td18, [sp, #672]\t@ 0x2a0\n-\tvldr\td5, [sp, #384]\t@ 0x180\n-\tvldr\td31, [sp, #216]\t@ 0xd8\n-\tvfma.f64\td16, d18, d17\n-\tvldr\td3, [sp, #368]\t@ 0x170\n-\tvldr\td13, [sp, #32]\n-\tvmul.f64\td17, d31, d5\n-\tvldr\td0, [sp, #264]\t@ 0x108\n-\tvfma.f64\td17, d3, d10\n-\tvmov.f64\td24, d16\n-\tvmul.f64\td16, d3, d26\n-\tvfma.f64\td16, d31, d28\n-\tvldr\td31, [sp, #120]\t@ 0x78\n-\tvmov.f64\td3, d18\n-\tvfms.f64\td24, d18, d21\n-\tvmov.f64\td21, d8\n-\tvfma.f64\td9, d17, d31\n-\tvldr\td17, [pc, #884]\t@ 4898 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1234>\n-\tvfms.f64\td7, d13, d17\n-\tvmov.f64\td17, #12\t@ 0x40600000 3.5\n-\tvmul.f64\td18, d28, d17\n-\tvmul.f64\td16, d16, d31\n-\tvfms.f64\td16, d11, d20\n-\tvldr\td31, [sp, #56]\t@ 0x38\n-\tvldr\td11, [sp, #128]\t@ 0x80\n-\tvstr\td9, [sp, #112]\t@ 0x70\n-\tvmul.f64\td18, d18, d0\n-\tvldr\td9, [pc, #852]\t@ 48a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x123c>\n-\tvmul.f64\td9, d13, d9\n-\tvfms.f64\td16, d31, d18\n-\tvldr\td18, [pc, #848]\t@ 48a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1244>\n-\tvldr\td31, [sp, #64]\t@ 0x40\n-\tvmul.f64\td18, d11, d18\n-\tvmul.f64\td14, d31, d12\n-\tvmul.f64\td12, d5, d12\n-\tvmul.f64\td11, d25, d18\n-\tvmul.f64\td30, d30, d18\n-\tvldr\td25, [sp, #328]\t@ 0x148\n-\tvldr\td18, [pc, #824]\t@ 48b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x124c>\n-\tvstr\td14, [sp, #32]\n-\tvstr\td11, [sp, #128]\t@ 0x80\n-\tvldr\td11, [sp, #40]\t@ 0x28\n-\tvmul.f64\td18, d25, d18\n-\tvldr\td25, [sp, #48]\t@ 0x30\n-\tvfma.f64\td16, d11, d30\n-\tvmul.f64\td30, d3, d2\n-\tvstr\td30, [sp, #16]\n-\tvmov.f64\td31, d16\n-\tvldr\td16, [sp, #304]\t@ 0x130\n-\tvmul.f64\td18, d18, d16\n-\tvldr\td16, [pc, #784]\t@ 48b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1254>\n-\tvmul.f64\td16, d25, d16\n-\tvldr\td25, [sp, #736]\t@ 0x2e0\n-\tvmul.f64\td8, d8, d25\n-\tvfma.f64\td19, d25, d16\n-\tvldr\td25, [sp, #680]\t@ 0x2a8\n-\tvstr\td8, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td20, d25, d7\n-\tvmul.f64\td8, d25, d5\n-\tvmov.f64\td25, d3\n-\tvmul.f64\td3, d21, d23\n-\tvmul.f64\td21, d28, d14\n-\tvldr\td14, [sp, #96]\t@ 0x60\n-\tvneg.f64\td11, d25\n-\tvmul.f64\td19, d6, d19\n-\tvfma.f64\td24, d30, d21\n-\tvmul.f64\td3, d3, d25\n-\tvmul.f64\td21, d20, d9\n-\tvmul.f64\td25, d14, d23\n-\tvmul.f64\td30, d14, d29\n-\tvmul.f64\td29, d6, d29\n-\tvldr\td14, [sp, #360]\t@ 0x168\n-\tvfma.f64\td24, d3, d21\n-\tvmul.f64\td21, d6, d23\n-\tvldr\td6, [sp, #800]\t@ 0x320\n-\tvstr\td25, [sp, #144]\t@ 0x90\n-\tvmul.f64\td25, d6, d7\n-\tvmul.f64\td7, d7, d27\n-\tvfms.f64\td7, d26, d14\n-\tvldr\td14, [sp, #88]\t@ 0x58\n-\tvmul.f64\td6, d6, d5\n-\tvnmul.f64\td23, d14, d26\n-\tvldr\td26, [sp, #288]\t@ 0x120\n-\tvadd.f64\td14, d19, d27\n-\tvmov.f64\td27, d28\n-\tvstr\td23, [sp, #200]\t@ 0xc8\n-\tvldr\td23, [pc, #648]\t@ 48c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x125c>\n-\tvmul.f64\td23, d26, d23\n-\tvldr\td26, [sp, #160]\t@ 0xa0\n-\tvfms.f64\td24, d26, d23\n-\tvldr\td23, [pc, #640]\t@ 48c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1264>\n-\tvmov.f64\td26, #120\t@ 0x3fc00000 1.5\n-\tvfms.f64\td27, d13, d23\n-\tvldr\td23, [pc, #636]\t@ 48d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x126c>\n-\tvmul.f64\td16, d16, d26\n-\tvstr\td24, [sp, #120]\t@ 0x78\n-\tvldr\td24, [sp, #352]\t@ 0x160\n-\tvstr\td27, [sp, #96]\t@ 0x60\n-\tvmul.f64\td27, d18, d17\n-\tvmul.f64\td23, d24, d23\n-\tvmul.f64\td17, d5, d17\n-\tvmul.f64\td27, d27, d28\n-\tvfma.f64\td19, d23, d22\n-\tvmul.f64\td24, d0, d17\n-\tvmul.f64\td18, d18, d17\n-\tvfma.f64\td14, d23, d22\n-\tvadd.f64\td22, d28, d28\n-\tvstr\td19, [sp, #160]\t@ 0xa0\n-\tvmov.f64\td19, #4\t@ 0x40200000 2.5\n-\tvldr\td13, [sp, #56]\t@ 0x38\n-\tvldr\td0, [sp, #112]\t@ 0x70\n-\tvmul.f64\td20, d20, d19\n-\tvmul.f64\td19, d8, d19\n-\tvfms.f64\td0, d13, d24\n-\tvldr\td24, [pc, #560]\t@ 48d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1274>\n-\tvldr\td13, [sp, #360]\t@ 0x168\n+\tvldr\td3, [sp, #504]\t@ 0x1f8\n+\tvmul.f64\td5, d6, d14\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tvldr\td14, [sp, #328]\t@ 0x148\n+\tvmul.f64\td2, d6, d14\n+\tvldr\td14, [sp, #296]\t@ 0x128\n+\tvldr\td6, [sp, #752]\t@ 0x2f0\n+\tvmul.f64\td6, d6, d14\n+\tvldr\td14, [sp, #744]\t@ 0x2e8\n+\tvmov.f64\td1, d2\n+\tvmul.f64\td4, d12, d14\n+\tvldr\td12, [sp, #400]\t@ 0x190\n+\tvldr\td14, [sp, #416]\t@ 0x1a0\n+\tvmul.f64\td2, d12, d7\n+\tvldr\td12, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td7, d14, d3\n+\tvldr\td14, [sp, #8]\n+\tvmul.f64\td3, d12, d14\n+\tvldr\td14, [sp, #64]\t@ 0x40\n+\tvdiv.f64\td12, d14, d4\n+\tvldr\td14, [sp, #184]\t@ 0xb8\n+\tvmov.f64\td4, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td14, d4, d14\n+\tvstr\td14, [sp, #8]\n+\tvdiv.f64\td14, d4, d5\n+\tvstr\td14, [sp, #296]\t@ 0x128\n+\tvdiv.f64\td14, d4, d6\n+\tvstr\td14, [sp, #328]\t@ 0x148\n+\tvldr\td14, [sp, #376]\t@ 0x178\n+\tvldr\td5, [sp, #352]\t@ 0x160\n+\tvstr\td0, [sp, #224]\t@ 0xe0\n+\tvdiv.f64\td6, d4, d14\n+\tvldr\td4, [pc, #-748]\t@ 41f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0xa1c>\n+\tvldr\td0, [sp, #808]\t@ 0x328\n+\tvstr\td1, [sp, #232]\t@ 0xe8\n+\tvstr\td6, [sp, #280]\t@ 0x118\n+\tvldr\td6, [sp, #656]\t@ 0x290\n+\tvmul.f64\td6, d6, d1\n+\tvldr\td1, [sp, #72]\t@ 0x48\n+\tvmul.f64\td6, d6, d4\n+\tvldr\td4, [sp, #672]\t@ 0x2a0\n+\tvmul.f64\td5, d5, d4\n+\tvldr\td4, [sp, #88]\t@ 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d3\n+\tvldr\td3, [pc, #340]\t@ 4a68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1294>\n+\tvmul.f64\td3, d13, d3\n+\tvmul.f64\td0, d14, d3\n+\tvstr\td8, [sp, #256]\t@ 0x100\n+\tvmov.f64\td8, #4\t@ 0x40200000 2.5\n+\tvmul.f64\td5, d5, d8\n+\tvadd.f64\td14, d10, d0\n+\tvadd.f64\td15, d12, d0\n+\tvmov.f64\td0, #120\t@ 0x3fc00000 1.5\n+\tvldr\td12, [sp, #72]\t@ 0x48\n+\tvmul.f64\td10, d9, d1\n+\tvmul.f64\td4, d4, d0\n+\tvmul.f64\td8, d12, d8\n+\tvstr\td14, [sp, #272]\t@ 0x110\n+\tvmov.f64\td14, d6\n+\tvldr\td12, [sp, #56]\t@ 0x38\n+\tvmla.f64\td14, d10, d4\n+\tvmul.f64\td4, d7, d4\n+\tvstr\td8, [sp, #40]\t@ 0x28\n+\tvmul.f64\td1, d1, d12\n+\tvldr\td10, [sp, #384]\t@ 0x180\n+\tvadd.f64\td8, d11, d11\n+\tvldr\td12, [pc, #260]\t@ 4a70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x129c>\n+\tvldr\td6, [sp, #360]\t@ 0x168\n+\tvnmls.f64\td10, d4, d9\n+\tvmul.f64\td9, d7, d0\n+\tvldr\td4, [sp, #200]\t@ 0xc8\n+\tvldr\td7, [pc, #248]\t@ 4a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12a4>\n+\tvstr\td9, [sp, #280]\t@ 0x118\n+\tvldr\td9, [sp, #704]\t@ 0x2c0\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td6, [sp, #304]\t@ 0x130\n+\tvmul.f64\td12, d9, d12\n+\tvldr\td9, [sp, #232]\t@ 0xe8\n+\tvmls.f64\td2, d7, d6\n+\tvldr\td7, [pc, #224]\t@ 4a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12ac>\n+\tvldr\td6, [sp, #80]\t@ 0x50\n+\tvnmla.f64\td4, d12, d9\n+\tvmov.f64\td9, d4\n+\tvldr\td4, [sp, #416]\t@ 0x1a0\n+\tvmla.f64\td6, d4, d7\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvmul.f64\td7, d4, d8\n+\tvmla.f64\td7, d1, d0\n+\tvldr\td0, [sp, #208]\t@ 0xd0\n+\tvmov.f64\td1, d14\n+\tvldr\td14, [sp, #376]\t@ 0x178\n+\tvmul.f64\td4, d0, d5\n+\tvmla.f64\td1, d4, d3\n+\tvldr\td4, [sp, #272]\t@ 0x110\n+\tvmla.f64\td1, d4, d11\n+\tvldr\td11, [sp, #16]\n+\tvldr\td4, [sp, #248]\t@ 0xf8\n+\tvmul.f64\td5, d11, d5\n+\tvldr\td11, [sp, #40]\t@ 0x28\n+\tvmla.f64\td5, d4, d8\n+\tvldr\td8, [sp, #288]\t@ 0x120\n+\tvmul.f64\td4, d0, d11\n+\tvldr\td0, [sp, #120]\t@ 0x78\n+\tvmla.f64\td10, d4, d3\n+\tvldr\td4, [sp]\n+\tvldr\td3, [sp, #152]\t@ 0x98\n+\tvmla.f64\td10, d15, d4\n+\tvmls.f64\td1, d3, d9\n+\tb.n\t4af0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x131c>\n \tnop\n \tnop.w\n+\t.word\t0xdc766309\n+\t.word\t0xbfc7ca11\n \t.word\t0xfff7dd55\n \t.word\t0x3f4a0ae2\n \t.word\t0x44569e2e\n \t.word\t0x3fce9274\n-\t.word\t0x8e5474aa\n-\t.word\t0x3f051bf9\n-\t.word\t0x96f7d0e1\n-\t.word\t0x400570ac\n \t.word\t0x8a55e750\n \t.word\t0xc0333f45\n+\t.word\t0x96f7d0e1\n+\t.word\t0x400570ac\n \t.word\t0xb39c605a\n \t.word\t0xbfada696\n+\t.word\t0x8e5474aa\n+\t.word\t0x3f051bf9\n+\t.word\t0x50429b6d\n+\t.word\t0x3fe20dd7\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n \t.word\t0x44569e2e\n \t.word\t0x3fde9274\n \t.word\t0xfa48b0f4\n \t.word\t0xbfb8f051\n \t.word\t0x11111111\n \t.word\t0x3ff11111\n-\t.word\t0x50429b6d\n-\t.word\t0x3fe20dd7\n \t.word\t0xc9be45de\n \t.word\t0x4023bd3c\n+\t.word\t0x25676f30\n+\t.word\t0x4001b6ec\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fe04201\n \t.word\t0xc28f5c29\n \t.word\t0x3fbc28f5\n \t.word\t0x77bd9591\n \t.word\t0xbfa3c464\n-\t.word\t0x0af83437\n-\t.word\t0xbfaa99f1\n \t.word\t0xa6db20a2\n \t.word\t0xbfc0a036\n+\t.word\t0x0af83437\n+\t.word\t0xbfaa99f1\n+\t.word\t0xbda12f68\n+\t.word\t0x3ff2f684\n \t.word\t0x5e247885\n \t.word\t0x3f55ce9e\n \t.word\t0xfe791dd3\n \t.word\t0xbfe7a245\n-\t.word\t0xbda12f68\n-\t.word\t0x3ff2f684\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n-\t.word\t0x949a5658\n-\t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n+\t.word\t0x949a5658\n+\t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0x25676f30\n-\t.word\t0x4001b6ec\n-\t.word\t0x2c4fea23\n-\t.word\t0x3fe04201\n-\tvldr\td21, [pc, #-36]\t@ 4940 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12dc>\n-\tvadd.f64\td18, d23, d18\n-\tvadd.f64\td21, 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d9\n+\tvldr\td5, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td6, d5, d6\n+\tvldr\td5, [sp, #344]\t@ 0x158\n+\tvmla.f64\td7, d13, d9\n+\tvldr\td13, [sp, #280]\t@ 0x118\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td5, [pc, #-284]\t@ 4ac0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12ec>\n+\tvmul.f64\td5, d1, d5\n+\tvldr\td1, [sp, #40]\t@ 0x28\n+\tvmla.f64\td6, d7, d5\n+\tvldr\td7, [sp]\n+\tvadd.f64\td11, d7, d7\n+\tvldr\td7, [sp, #128]\t@ 0x80\n+\tvmul.f64\td5, d7, d11\n+\tvldr\td7, [sp, #392]\t@ 0x188\n+\tvmla.f64\td5, d13, d0\n+\tvnmls.f64\td7, d5, d3\n+\tvldr\td5, [sp, #248]\t@ 0xf8\n+\tvldr\td3, [sp, #16]\n+\tvmul.f64\td5, d5, d11\n+\tvmla.f64\td5, d3, d1\n+\tvmla.f64\td7, d5, d2\n+\tvldr\td5, [r6]\n+\tvmls.f64\td7, d15, d4\n+\tvmov.f64\td13, d7\n+\tvmov.f64\td7, #80\t@ 0x3e800000 0.250\n+\tvmla.f64\td5, d6, d7\n+\tvldr\td7, [pc, #-360]\t@ 4ac8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12f4>\n+\tvldr\td6, [sp, #24]\n+\tvcmpe.f64\td6, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td5, [r6]\n+\tbmi.w\t4d5a <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1586>\n+\tvldr\td4, [sp, #336]\t@ 0x150\n+\tvldr\td6, [pc, #-380]\t@ 4ad0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x12fc>\n+\tvldr\td7, [pc, #-368]\t@ 4ae0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x130c>\n+\tvldr\td5, [pc, #-380]\t@ 4ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1304>\n+\tvadd.f64\td6, d4, d6\n+\tvadd.f64\td5, d4, d5\n+\tvmla.f64\td7, d6, d4\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #-388]\t@ 4ae8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1314>\n+\tvmla.f64\td6, d5, d4\n+\tvdiv.f64\td0, d7, d6\n+\tvldr\td7, [sp, #240]\t@ 0xf0\n+\tvldr\td6, [sp, #192]\t@ 0xc0\n+\tvldr\td5, [sp, #112]\t@ 0x70\n+\tvmul.f64\td11, d7, d11\n+\tvldr\td7, [sp, #8]\n+\tvldr\td4, [sp, #104]\t@ 0x68\n+\tvldr\td14, [sp]\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [sp, #72]\t@ 0x48\n+\tvldr\td2, [sp, #168]\t@ 0xa8\n+\tvldr\td1, [sp, #48]\t@ 0x30\n+\tvmul.f64\td5, d7, d5\n+\tvldr\td7, [sp, #88]\t@ 0x58\n+\tldr\tr2, [pc, #276]\t@ (4dc0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15ec>)\n+\tldr\tr3, [pc, #280]\t@ (4dc4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15f0>)\n+\tvsub.f64\td0, d0, d7\n+\tvldr\td7, [sp, #136]\t@ 0x88\n \tadd\tr2, pc\n-\tvmul.f64\td17, d21, d17\n-\tvldr\td21, [sp, #32]\n-\tvfma.f64\td15, d4, d20\n-\tvldr\td20, [sp]\n-\tvfma.f64\td20, d0, d23\n-\tvfma.f64\td15, d12, d11\n-\tvfma.f64\td15, d3, d8\n-\tvmul.f64\td20, d20, d18\n-\tvldr\td18, [sp, #16]\n-\tvfma.f64\td20, d18, d21\n-\tvadd.f64\td15, d19, d15\n-\tvfma.f64\td15, d14, d19\n-\tvfma.f64\td15, d22, d13\n-\tvfma.f64\td15, d16, d24\n-\tvfma.f64\td15, d20, d5\n-\tvfma.f64\td25, d15, d17\n-\tvstr\td25, [r4]\n+\tvmul.f64\td4, d7, d4\n+\tvldr\td7, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td3, d14, d7\n+\tvldr\td7, [sp, #64]\t@ 0x40\n+\tvnmls.f64\td3, d7, d2\n+\tvldr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td2, [sp, #80]\t@ 0x50\n+\tvmls.f64\td3, d11, d7\n+\tvldr\td7, [sp, #144]\t@ 0x90\n+\tvmls.f64\td3, d6, d7\n+\tvldr\td7, [sp, #176]\t@ 0xb0\n+\tvldr\td6, [r4]\n+\tvmla.f64\td3, d5, d7\n+\tvldr\td7, [sp, #32]\n+\tvldr\td5, [pc, #184]\t@ 4da8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15d4>\n+\tvadd.f64\td3, d3, d8\n+\tvmls.f64\td3, d7, d8\n+\tvldr\td7, [pc, #180]\t@ 4db0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15dc>\n+\tvmla.f64\td2, d0, d7\n+\tvldr\td7, [pc, #180]\t@ 4db8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15e4>\n+\tvmla.f64\td3, d12, d10\n+\tvmul.f64\td7, d1, d7\n+\tvmla.f64\td3, d13, d9\n+\tvmla.f64\td4, d2, d5\n+\tvmla.f64\td3, d4, d14\n+\tvmla.f64\td6, d3, d7\n+\tvstr\td6, [r4]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #836]\t@ 0x344\n+\tldr\tr3, [sp, #828]\t@ 0x33c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t4b62 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x14fe>\n-\tadd.w\tsp, sp, #840\t@ 0x348\n+\tbne.n\t4da0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x15cc>\n+\tadd.w\tsp, sp, #832\t@ 0x340\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvldr\td0, [sp, #192]\t@ 0xc0\n-\tvstr\td7, [sp, #280]\t@ 0x118\n-\tvstr\td6, [sp, #272]\t@ 0x110\n-\tvstr\td31, [sp, #264]\t@ 0x108\n-\tvstr\td26, [sp, #256]\t@ 0x100\n-\tvstr\td3, [sp, #248]\t@ 0xf8\n-\tvstr\td1, [sp, #240]\t@ 0xf0\n-\tvstr\td18, [sp, #232]\t@ 0xe8\n-\tvstr\td20, [sp, #224]\t@ 0xe0\n-\tvstr\td19, [sp, #216]\t@ 0xd8\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n-\tvstr\td21, [sp, #200]\t@ 0xc8\n+\tvldr\td8, [sp, #336]\t@ 0x150\n+\tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td12, d0\n-\tvldr\td0, [sp, #192]\t@ 0xc0\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td21, [sp, #200]\t@ 0xc8\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvldr\td19, [sp, #216]\t@ 0xd8\n-\tvmul.f64\td12, d12, d0\n-\tvldr\td20, [sp, #224]\t@ 0xe0\n-\tvldr\td18, [sp, #232]\t@ 0xe8\n-\tvldr\td1, [sp, #240]\t@ 0xf0\n-\tvldr\td3, [sp, #248]\t@ 0xf8\n-\tvldr\td26, [sp, #256]\t@ 0x100\n-\tvldr\td31, [sp, #264]\t@ 0x108\n-\tvldr\td6, [sp, #272]\t@ 0x110\n-\tvldr\td7, [sp, #280]\t@ 0x118\n-\tb.w\t3ccc <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x668>\n-\tvldr\td0, [sp, #192]\t@ 0xc0\n-\tvstr\td4, [sp, #128]\t@ 0x80\n-\tvstr\td20, [sp, #120]\t@ 0x78\n-\tvstr\td24, [sp, #112]\t@ 0x70\n-\tvstr\td16, [sp, #96]\t@ 0x60\n-\tvstr\td22, [sp, #88]\t@ 0x58\n-\tvstr\td19, [sp, #80]\t@ 0x50\n-\tvstr\td3, [sp, #64]\t@ 0x40\n-\tvstr\td2, [sp, #56]\t@ 0x38\n-\tvstr\td5, [sp, #48]\t@ 0x30\n+\tvmov.f64\td11, d0\n+\tvmov.f64\td0, d8\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td11, d11, d0\n+\tb.w\t3e7c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x6a8>\n+\tvldr\td14, [sp, #336]\t@ 0x150\n+\tvmov.f64\td0, d14\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td17, d0\n-\tvldr\td0, [sp, #192]\t@ 0xc0\n-\tvstr\td17, [sp, #40]\t@ 0x28\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td17, [sp, #40]\t@ 0x28\n-\tvldr\td5, [sp, #48]\t@ 0x30\n-\tvldr\td2, [sp, #56]\t@ 0x38\n-\tvmul.f64\td0, d17, d0\n-\tvldr\td3, [sp, #64]\t@ 0x40\n-\tvldr\td19, [sp, #80]\t@ 0x50\n-\tvldr\td22, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #96]\t@ 0x60\n-\tvldr\td24, [sp, #112]\t@ 0x70\n-\tvldr\td20, [sp, #120]\t@ 0x78\n-\tvldr\td4, [sp, #128]\t@ 0x80\n-\tb.n\t4984 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x1320>\n-\tvldr\td12, [sp, #192]\t@ 0xc0\n-\tvstr\td1, [sp, #240]\t@ 0xf0\n-\tvstr\td18, [sp, #232]\t@ 0xe8\n-\tvmov.f64\td0, d12\n-\tvstr\td20, [sp, #224]\t@ 0xe0\n-\tvstr\td19, [sp, #216]\t@ 0xd8\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n-\tvstr\td21, [sp, #200]\t@ 0xc8\n+\tvmov.f64\td7, d0\n+\tvmov.f64\td0, d14\n+\tvmov.f64\td15, d7\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td0, d15, d0\n+\tb.n\t4c74 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x14a0>\n+\tvldr\td8, [sp, #336]\t@ 0x150\n+\tvmov.f64\td0, d8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td8, d0\n-\tvmov.f64\td0, d12\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td21, [sp, #200]\t@ 0xc8\n-\tvldr\td19, [sp, #216]\t@ 0xd8\n-\tvldr\td20, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td16, d8, d0\n-\tvldr\td18, [sp, #232]\t@ 0xe8\n-\tvldr\td1, [sp, #240]\t@ 0xf0\n-\tvldr\td3, [sp, #248]\t@ 0xf8\n-\tvldr\td31, [sp, #264]\t@ 0x108\n-\tvstr\td16, [sp, #816]\t@ 0x330\n-\tvldr\td6, [sp, #272]\t@ 0x110\n-\tvldr\td16, [sp, #208]\t@ 0xd0\n-\tvldr\td7, [sp, #280]\t@ 0x118\n-\tb.w\t3de4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x780>\n+\tvmov.f64\td10, d0\n+\tvmov.f64\td0, d8\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td7, d10, d0\n+\tvstr\td7, [sp, #808]\t@ 0x328\n+\tb.w\t3f48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0+0x774>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n+\tnop.w\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fe04201\n+\t.word\t0x25676f30\n+\t.word\t0x4001b6ec\n \t.word\t0xfe791dd3\n \t.word\t0xbfc7a245\n-\t.word\t0x000001ac\n+\t.word\t0x00000108\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00004b78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>:\n+00004dc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #2976]\t@ 0xba0\n-\tvldr\td11, [pc, #1012]\t@ 4f80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x408>\n-\tvmul.f64\td12, d1, d1\n-\tvmov.f64\td8, #80\t@ 0x3e800000 0.250\n-\tsub.w\tsp, sp, #1040\t@ 0x410\n+\tstr.w\tr0, [ip, #2984]\t@ 0xba8\n+\tvldr\td10, [pc, #1012]\t@ 51d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x408>\n+\tvmul.f64\td13, d1, d1\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n \tvmov.f64\td9, d0\n+\tsub.w\tsp, sp, #1032\t@ 0x408\n+\tvmov.f64\td14, d1\n+\tvmul.f64\td10, d0, d10\n \tmov\tr5, r0\n-\tvmul.f64\td11, d0, d11\n+\tvmul.f64\td5, d13, d12\n \tmov\tr6, r1\n-\tvmul.f64\td16, d12, d8\n \tmov\tr4, r2\n-\tvstr\td1, [sp]\n-\tvmov.f64\td15, #112\t@ 0x3f800000 1.0\n-\tvmul.f64\td13, d12, d12\n-\tvmov.f64\td0, d11\n-\tvstr\td16, [sp, #192]\t@ 0xc0\n+\tvstr\td1, [sp, #168]\t@ 0xa8\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td0, d10\n+\tvstr\td5, [sp, #256]\t@ 0x100\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tldr.w\tr3, [sp, #1128]\t@ 0x468\n-\tvmul.f64\td19, d9, d9\n-\tvldr\td20, [pc, #952]\t@ 4f88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x410>\n-\tvmul.f64\td22, d11, d0\n-\tvmul.f64\td24, d0, d0\n-\tvstr\td0, [sp, #32]\n-\tvldr\td21, [pc, #944]\t@ 4f90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x418>\n-\tvldr\td16, [r3]\n-\tvmul.f64\td14, d19, d19\n-\tvdiv.f64\td25, d15, d19\n-\tvstr\td19, [sp, #208]\t@ 0xd0\n-\tvdiv.f64\td22, d15, d22\n-\tvmul.f64\td0, d11, d24\n-\tvmul.f64\td10, d16, d16\n-\tvstr\td24, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td29, d14, d14\n-\tvldr\td23, [pc, #912]\t@ 4f98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x420>\n-\tvdiv.f64\td27, d15, d14\n-\tvldr\td1, [sp]\n-\tvdiv.f64\td11, d15, d24\n-\tvmul.f64\td24, d13, d21\n-\tvmul.f64\td19, d10, d10\n-\tvmul.f64\td23, d12, d23\n-\tvdiv.f64\td21, d15, d0\n-\tvstr\td29, [sp, #552]\t@ 0x228\n-\tvldr\td18, [pc, #884]\t@ 4fa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x428>\n+\tvmul.f64\td1, d9, d9\n+\tvldr\td4, [pc, #956]\t@ 51d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x410>\n+\tvmov.f64\td7, d0\n+\tldr.w\tr3, [sp, #1120]\t@ 0x460\n+\tvldr\td6, [pc, #952]\t@ 51e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x418>\n+\tvmul.f64\td0, d0, d0\n+\tvmul.f64\td3, d1, d1\n+\tvstr\td1, [sp, #272]\t@ 0x110\n+\tvstr\td7, [sp, #80]\t@ 0x50\n+\tvmul.f64\td7, d10, d7\n+\tvmul.f64\td6, d13, d6\n+\tvmul.f64\td10, d10, d0\n+\tvstr\td0, [sp, #264]\t@ 0x108\n+\tvmul.f64\td11, d3, d3\n+\tvstr\td3, [sp, #688]\t@ 0x2b0\n+\tvdiv.f64\td15, d8, d3\n+\tvdiv.f64\td2, d8, d7\n+\tvldr\td7, [r3]\n+\tvdiv.f64\td5, d4, d11\n+\tvmul.f64\td4, d3, d9\n+\tvdiv.f64\td10, d8, d10\n+\tvstr\td11, [sp, #736]\t@ 0x2e0\n+\tvmul.f64\td11, d13, d13\n+\tvdiv.f64\td4, d8, d4\n+\tvmul.f64\td3, d6, d11\n+\tvmul.f64\td14, d11, d14\n+\tvstr\td3, [sp, #328]\t@ 0x148\n+\tvstr\td14, [sp, #536]\t@ 0x218\n+\tvstr\td15, [sp, #696]\t@ 0x2b8\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvstr\td10, [sp, #24]\n+\tvstr\td4, [sp, #312]\t@ 0x138\n+\tvmul.f64\td4, d7, d7\n+\tvmul.f64\td6, d4, d4\n+\tvstr\td4, [sp, #280]\t@ 0x118\n+\tvmul.f64\td3, d7, d6\n+\tvldr\td7, [pc, #832]\t@ 51e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x420>\n+\tvstr\td6, [sp, #704]\t@ 0x2c0\n+\tvstr\td3, [sp, #320]\t@ 0x140\n+\tvmul.f64\td3, d4, d6\n+\tvmul.f64\td5, d5, d3\n+\tvstr\td3, [sp, #744]\t@ 0x2e8\n+\tvmul.f64\td3, d11, d7\n+\tvmul.f64\td7, d15, d6\n+\tvmov.f64\td6, d8\n+\tvstr\td5, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td2, d7, d2\n+\tvldr\td7, [pc, #796]\t@ 51f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x428>\n+\tvstr\td3, [sp, #304]\t@ 0x130\n+\tvdiv.f64\td3, d8, d0\n+\tvldr\td0, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td15, d14, d7\n+\tvldr\td5, [pc, #784]\t@ 51f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x430>\n+\tvdiv.f64\td14, d8, d1\n+\tvldr\td1, [sp, #328]\t@ 0x148\n+\tvmla.f64\td6, d1, d0\n+\tvldr\td0, [sp, #304]\t@ 0x130\n+\tvldr\td1, [sp, #320]\t@ 0x140\n+\tvstr\td15, [sp, #720]\t@ 0x2d0\n+\tvmul.f64\td0, d0, d5\n+\tvstr\td0, [sp, #712]\t@ 0x2c8\n+\tvmov.f64\td7, d6\n+\tvldr\td6, [sp, #312]\t@ 0x138\n+\tvmla.f64\td7, d2, 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<__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x458>\n+\tvstr\td0, [sp, #680]\t@ 0x2a8\n \tvmov.f64\td0, d9\n-\tvstr\td24, [sp, #472]\t@ 0x1d8\n-\tvmul.f64\td28, d16, d19\n-\tvstr\td19, [sp, #496]\t@ 0x1f0\n-\tvdiv.f64\td16, d20, d29\n-\tvmul.f64\td20, d14, d9\n-\tvmul.f64\td29, d10, d19\n-\tvmul.f64\td26, d13, d18\n-\tvmul.f64\td23, d23, d13\n-\tvldr\td18, [pc, #852]\t@ 4fa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x430>\n-\tvstr\td28, [sp, #536]\t@ 0x218\n-\tvdiv.f64\td20, d15, d20\n-\tvstr\td29, [sp, #560]\t@ 0x230\n-\tvmul.f64\td24, d24, d18\n-\tvstr\td23, [sp, #544]\t@ 0x220\n-\tvstr\td26, [sp, #504]\t@ 0x1f8\n-\tvstr\td18, [sp, #80]\t@ 0x50\n-\tvstr\td24, [sp, #480]\t@ 0x1e0\n-\tvstr\td25, [sp, #144]\t@ 0x90\n-\tvstr\td22, [sp, #216]\t@ 0xd8\n-\tvstr\td27, [sp, #488]\t@ 0x1e8\n-\tvstr\td21, [sp, #8]\n-\tvmul.f64\td29, d16, d29\n-\tvmul.f64\td16, d27, d19\n-\tvmul.f64\td19, d16, d22\n-\tvmul.f64\td22, d13, d1\n-\tvldr\td16, [pc, #792]\t@ 4fb0 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#152]\t@ 0x98\n-\tvldr\td16, [pc, #704]\t@ 4fc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x450>\n-\tvdiv.f64\td22, d15, d20\n-\tvmul.f64\td23, d12, d16\n-\tvmul.f64\td20, d24, d19\n-\tvmul.f64\td16, d25, d10\n-\tvstr\td23, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td23, d23, d8\n-\tvfma.f64\td20, d23, d18\n-\tvstr\td23, [sp, #464]\t@ 0x1d0\n-\tvstr\td18, [sp, #56]\t@ 0x38\n-\tvstr\td16, [sp, #48]\t@ 0x30\n-\tvstr\td17, [sp, #40]\t@ 0x28\n-\tvmov.f64\td18, d20\n-\tvldr\td20, [pc, #964]\t@ 5100 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x588>\n-\tvstr\td18, [sp, #104]\t@ 0x68\n-\tvmul.f64\td23, d18, d22\n-\tvstr\td22, [sp, #72]\t@ 0x48\n-\tvmul.f64\td21, d16, d23\n-\tvstr\td23, [sp, #568]\t@ 0x238\n-\tvfma.f64\td1, d17, d21\n-\tvstr\td21, [sp, #120]\t@ 0x78\n-\tvmul.f64\td23, d1, d20\n-\tvstr\td1, [sp, #24]\n-\tvstr\td23, [sp, #16]\n+\tvmul.f64\td10, d5, d2\n+\tvmul.f64\td5, d13, d12\n+\tvstr\td1, [sp, #288]\t@ 0x120\n+\tvstr\td3, [sp, #88]\t@ 0x58\n+\tvmul.f64\td1, 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\t.word\t0x3f841059\n+\t.word\t0x25676f30\n+\t.word\t0x4001b6ec\n+\t.word\t0x77655a1a\n+\t.word\t0x3f920a14\n \t.word\t0x8240b780\n \t.word\t0x3f88c7e2\n \t.word\t0x0f94a0b7\n \t.word\t0xbffa4852\n \t.word\t0x1ff9d571\n \t.word\t0x3ff5eb4b\n \t.word\t0xe03dc2d9\n \t.word\t0x4019e6cb\n-\t.word\t0xdc766309\n-\t.word\t0xbfc7ca11\n \t.word\t0x181a38ac\n \t.word\t0x3fe0304c\n-\t.word\t0xa6db20a2\n-\t.word\t0xbfc0a036\n \t.word\t0xb9f05136\n \t.word\t0x3fdeb2b8\n \t.word\t0xb39c605a\n \t.word\t0xbfada696\n+\t.word\t0xdc766309\n+\t.word\t0xbfc7ca11\n+\t.word\t0x1c71c71c\n+\t.word\t0x3fec71c7\n+\t.word\t0xa6db20a2\n+\t.word\t0xbfc0a036\n \t.word\t0x77bd9591\n \t.word\t0xbfa3c464\n \t.word\t0xfa48b0f4\n \t.word\t0xbfb8f051\n-\t.word\t0x1c71c71c\n-\t.word\t0x3fec71c7\n \t.word\t0x77bd9591\n \t.word\t0xbfb3c464\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n+\t.word\t0x0b76c3bb\n+\t.word\t0x3ef0e32e\n \t.word\t0xc28f5c29\n \t.word\t0xbfbc28f5\n \t.word\t0x5e247885\n \t.word\t0xbf55ce9e\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n \t.word\t0x87aa83cc\n@@ -5338,2105 +5491,2189 @@\n \t.word\t0x40142523\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \t.word\t0x8d84e354\n \t.word\t0x3fe27ddb\n-\t.word\t0x0758138d\n-\t.word\t0x3fecd0f6\n \t.word\t0x5dae292a\n \t.word\t0x408b6574\n+\t.word\t0x0758138d\n+\t.word\t0x3fecd0f6\n \t.word\t0xc277df34\n \t.word\t0x3fd86301\n-\t.word\t0x3c998ed0\n-\t.word\t0x4016107d\n+\t.word\t0xaa145d16\n+\t.word\t0x4003edc9\n \t.word\t0x2c4fea23\n \t.word\t0x3fd04201\n-\t.word\t0x2c4fea23\n-\t.word\t0x3fe04201\n \t.word\t0x3315d702\n \t.word\t0x3fee7bc2\n+\t.word\t0x3c998ed0\n+\t.word\t0x4016107d\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fe04201\n \t.word\t0xc277df34\n \t.word\t0x40086301\n-\t.word\t0xaa145d16\n-\t.word\t0x4003edc9\n-\t.word\t0x2c4fea23\n-\t.word\t0x3ff04201\n \t.word\t0x47c07d65\n \t.word\t0x40286dc6\n+\t.word\t0x2c4fea23\n+\t.word\t0x3ff04201\n \t.word\t0x3bad40f9\n \t.word\t0x3fe8314e\n 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[sp, #808]\t@ 0x328\n-\tvmul.f64\td25, d28, d25\n-\tvstr\td27, [sp, #768]\t@ 0x300\n-\tvldr\td28, [pc, #-852]\t@ 5100 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x588>\n-\tvfma.f64\td8, d27, d25\n-\tvldr\td27, [sp, #88]\t@ 0x58\n-\tvstr\td25, [sp, #776]\t@ 0x308\n-\tvldr\td25, [sp, #272]\t@ 0x110\n-\tvmul.f64\td27, d27, d16\n-\tvnmul.f64\td16, d16, d15\n-\tvfma.f64\td16, d25, d24\n-\tvldr\td24, [pc, #-876]\t@ 5108 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x590>\n-\tvstr\td27, [sp, #304]\t@ 0x130\n-\tvfnms.f64\td23, d0, d24\n-\tvldr\td24, [sp, #168]\t@ 0xa8\n-\tvadd.f64\td18, d18, d23\n-\tvldr\td23, [sp, #128]\t@ 0x80\n-\tvfms.f64\td18, d22, d21\n-\tvldr\td22, [pc, #-896]\t@ 5110 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x598>\n-\tvmul.f64\td25, d17, d22\n-\tvldr\td17, [pc, #-896]\t@ 5118 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5a0>\n-\tvldr\td22, [pc, #-892]\t@ 5120 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5a8>\n-\tvmul.f64\td24, d24, d17\n-\tvmov.f64\td17, #98\t@ 0x3f100000 0.5625000\n-\tvstr\td25, [sp, #872]\t@ 0x368\n-\tvfms.f64\td29, d0, d17\n-\tvsub.f64\td17, d12, d27\n-\tvfma.f64\td17, d19, d20\n-\tvldr\td20, [pc, #-912]\t@ 5128 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5b0>\n-\tvfma.f64\td8, d25, d24\n-\tvstr\td24, [sp, #880]\t@ 0x370\n-\tvldr\td24, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td27, d2, d20\n-\tvldr\td20, [pc, #-924]\t@ 5130 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5b8>\n-\tvfms.f64\td17, d15, d21\n-\tvldr\td21, [pc, #-924]\t@ 5138 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5c0>\n-\tvldr\td15, [pc, #-920]\t@ 5140 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5c8>\n-\tvmul.f64\td23, d23, d20\n-\tvldr\td20, [pc, #-920]\t@ 5148 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x5d0>\n-\tvmul.f64\td21, d4, d21\n-\tvldr\td2, [pc, #-920]\t@ 5150 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#72]\t@ 0x48\n-\tvmul.f64\td12, d16, d20\n-\tvldr\td16, [pc, #912]\t@ 5998 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe20>\n-\tvstr\td18, [sp, #352]\t@ 0x160\n-\tvmul.f64\td20, d8, d16\n-\tvmul.f64\td16, d25, d12\n-\tvstr\td20, [sp, #360]\t@ 0x168\n-\tvmul.f64\td16, d22, d16\n-\tvldr\td22, [sp, #120]\t@ 0x78\n-\tvfma.f64\td16, d22, d18\n-\tvmov.f64\td18, d16\n-\tvstr\td16, [sp, #120]\t@ 0x78\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvmul.f64\td17, d16, d17\n-\tvldr\td16, [r5]\n-\tvfma.f64\td16, d20, d17\n-\tvmul.f64\td20, d15, d21\n-\tvldr\td17, [sp, #104]\t@ 0x68\n-\tvsub.f64\td13, d18, d20\n-\tvstr\td20, [sp, #344]\t@ 0x158\n-\tvneg.f64\td17, d17\n-\tvstr\td16, [r5]\n-\tvmul.f64\td28, d13, d28\n-\tvldr\td16, [pc, #836]\t@ 59a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe28>\n-\tvstr\td17, [sp, #920]\t@ 0x398\n-\tvcmpe.f64\td1, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t66a4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1b2c>\n-\tvldr\td20, [sp, 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0x1d0\n-\tvldr\td23, [sp, #552]\t@ 0x228\n-\tvmul.f64\td17, d16, d17\n-\tvldr\td16, [sp, #848]\t@ 0x350\n-\tvmul.f64\td16, d16, d20\n-\tvldr\td20, [sp, #784]\t@ 0x310\n-\tvstr\td16, [sp, #680]\t@ 0x2a8\n-\tvmul.f64\td16, d26, d20\n-\tvldr\td20, [sp, #832]\t@ 0x340\n-\tvadd.f64\td26, d24, d24\n-\tvldr\td24, [sp, #624]\t@ 0x270\n-\tvmul.f64\td20, d20, d21\n-\tvldr\td21, [sp, #744]\t@ 0x2e8\n-\tvadd.f64\td24, d24, d24\n-\tvmul.f64\td21, d31, d21\n-\tvldr\td31, [sp, #752]\t@ 0x2f0\n-\tvstr\td20, [sp, #688]\t@ 0x2b0\n-\tvldr\td20, [sp, #272]\t@ 0x110\n-\tvfms.f64\td20, d1, d22\n-\tvldr\td22, [sp, #224]\t@ 0xe0\n-\tvstr\td21, [sp, #728]\t@ 0x2d8\n-\tvldr\td21, [sp, #208]\t@ 0xd0\n-\tvdiv.f64\td22, d22, d6\n-\tvstr\td24, [sp, #552]\t@ 0x228\n-\tvldr\td6, [sp, #280]\t@ 0x118\n-\tvmul.f64\td8, d21, d9\n-\tvmul.f64\td14, d21, d14\n-\tvmul.f64\td21, d23, d9\n-\tvldr\td23, [sp, #600]\t@ 0x258\n-\tvldr\td24, [sp, #432]\t@ 0x1b0\n-\tvmul.f64\td6, d7, d6\n-\tvstr\td20, [sp, #272]\t@ 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d18\n-\tvfma.f64\td20, d11, d26\n-\tvmov.f64\td26, d22\n-\tvfma.f64\td26, d24, d11\n-\tvldr\td11, [sp, #40]\t@ 0x28\n-\tvldr\td24, [sp, #72]\t@ 0x48\n-\tvmul.f64\td17, d17, d11\n-\tvldr\td11, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td18, d18, d24\n-\tvmul.f64\td23, d24, d23\n-\tvmov.f64\td31, d20\n-\tvldr\td20, [pc, #196]\t@ 5a00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe88>\n-\tvmul.f64\td22, d11, d20\n-\tvldr\td11, [sp, #616]\t@ 0x268\n-\tvmul.f64\td20, d11, d20\n-\tvmov.f64\td11, d17\n-\tvfma.f64\td11, d19, d10\n-\tvmul.f64\td22, d22, d21\n-\tvldr\td10, [sp, #592]\t@ 0x250\n-\tvmul.f64\td20, d20, d21\n-\tvmov.f64\td21, d11\n-\tvldr\td11, [sp, #888]\t@ 0x378\n-\tvmul.f64\td18, d18, d11\n-\tvldr\td11, [sp, #568]\t@ 0x238\n-\tvfma.f64\td18, d11, d17\n-\tvldr\td17, [sp, #744]\t@ 0x2e8\n-\tvfma.f64\td17, d24, d25\n-\tvldr\td11, [sp, #648]\t@ 0x288\n-\tvmul.f64\td25, d24, d12\n-\tvnmul.f64\td19, d21, d11\n-\tb.n\t5ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf60>\n-\tnop\n-\t.word\t0x46db86a4\n-\t.word\t0x3f28bea8\n+\t.word\t0x9470e5c6\n+\t.word\t0x3f741059\n+\t.word\t0x26d12521\n+\t.word\t0x3f8508e2\n \t.word\t0xaefb2aae\n \t.word\t0x3fa7fe08\n+\t.word\t0x03ebac6c\n+\t.word\t0xbfb0a5f6\n+\t.word\t0xb045412c\n+\t.word\t0x3e8a27bd\n+\t.word\t0x46db86a4\n+\t.word\t0x3f28bea8\n \t.word\t0xfe791dd3\n \t.word\t0xbfe7a245\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0x55555555\n-\t.word\t0x3ff55555\n \t.word\t0x63e07ae3\n \t.word\t0x3f82b04b\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n \t.word\t0xfc2dd756\n \t.word\t0x3ff8ac8b\n+\t.word\t0x55555555\n+\t.word\t0x3ff55555\n \t.word\t0x00000000\n \t.word\t0x3fb00000\n-\t.word\t0xe03dc2d9\n-\t.word\t0x4019e6cb\n-\t.word\t0xc9be45de\n-\t.word\t0x4033bd3c\n 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d5\n+\tvmul.f64\td1, d1, d3\n+\tvmul.f64\td5, d5, d3\n+\tvldr\td3, [pc, #-380]\t@ 5c50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe88>\n+\tvmul.f64\td0, d12, d3\n+\tvmov.f64\td12, d10\n+\tvldr\td10, [sp, #184]\t@ 0xb8\n+\tvmla.f64\td6, d0, d13\n+\tvmul.f64\td13, d13, d3\n+\tvldr\td0, [sp, #128]\t@ 0x80\n+\tvldr\td3, [sp, #1008]\t@ 0x3f0\n+\tvmul.f64\td13, d13, d0\n+\tvmla.f64\td11, d13, d3\n+\tvldr\td3, [pc, #-412]\t@ 5c58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe90>\n+\tvldr\td13, [sp, #808]\t@ 0x328\n+\tvmul.f64\td14, d14, d3\n+\tvmul.f64\td3, d0, d3\n+\tvmul.f64\td4, d6, d13\n+\tvldr\td13, [sp, #760]\t@ 0x2f8\n+\tvnmls.f64\td12, d14, d0\n+\tvmul.f64\td6, d6, d13\n+\tvldr\td14, [sp, #24]\n+\tvldr\td13, [sp, #472]\t@ 0x1d8\n+\tvmla.f64\td13, d12, d10\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tvmul.f64\td10, d0, d10\n+\tvldr\td0, [sp, #104]\t@ 0x68\n+\tvmul.f64\td9, d14, d12\n+\tvldr\td12, [sp, #848]\t@ 0x350\n+\tvnmla.f64\td0, d9, d1\n+\tvldr\td1, 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#376]\t@ 0x178\n+\tvldr\td5, [sp, #424]\t@ 0x1a8\n+\tvldr\td14, [pc, #52]\t@ 64c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1700>\n+\tvmla.f64\td11, d6, d14\n+\tvmul.f64\td6, d10, d5\n+\tvldr\td10, [sp, #512]\t@ 0x200\n+\tvmla.f64\td12, d6, d4\n+\tvmov.f64\td6, d5\n+\tvldr\td5, [sp, #256]\t@ 0x100\n+\tvmul.f64\td6, d6, d5\n+\tb.n\t6648 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1880>\n+\tnop\n+\tnop.w\n+\t.word\t0x416c84c0\n+\t.word\t0x3fa14aca\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n+\t.word\t0x91b4ef6b\n+\t.word\t0x3ffc5bf8\n \t.word\t0xc277df34\n \t.word\t0x40086301\n \t.word\t0x5d0fe07c\n \t.word\t0x3f77acce\n-\t.word\t0xcebb4be1\n-\t.word\t0x3eec3bf8\n-\t.word\t0xc277df34\n-\t.word\t0x3fd86301\n \t.word\t0x2c4fea23\n \t.word\t0x3fd04201\n+\t.word\t0x2c5f92c6\n+\t.word\t0x3fa2c5f9\n+\t.word\t0xc277df34\n+\t.word\t0x3fd86301\n+\t.word\t0xcebb4be1\n+\t.word\t0x3eec3bf8\n \t.word\t0x63e07ae3\n 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#-280]\t@ 5a10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xe98>\n-\tvldr\td23, [sp, #712]\t@ 0x2c8\n-\tvfma.f64\td17, d26, d16\n-\tvldr\td26, [sp, #328]\t@ 0x148\n-\tvmov.f64\td25, d18\n-\tvldr\td18, [pc, #-292]\t@ 5a18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xea0>\n-\tvfma.f64\td25, d16, d26\n-\tvldr\td26, [sp, #168]\t@ 0xa8\n-\tvfma.f64\td31, d17, d12\n-\tvmov.f64\td11, d25\n-\tvldr\td25, [pc, #-304]\t@ 5a20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xea8>\n-\tvmul.f64\td16, d7, d25\n-\tvldr\td7, [sp, #408]\t@ 0x198\n-\tvmul.f64\td18, d7, d18\n-\tvldr\td7, [pc, #-312]\t@ 5a28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xeb0>\n-\tvmul.f64\td16, d16, d19\n-\tvmul.f64\td7, d26, d7\n-\tvldr\td26, [sp, #400]\t@ 0x190\n-\tvmul.f64\td16, d16, d24\n-\tvmul.f64\td20, d26, d20\n-\tvldr\td26, [sp, #696]\t@ 0x2b8\n-\tvmul.f64\td25, d24, d26\n-\tvmul.f64\td17, d26, d18\n-\tvmul.f64\td26, d22, d21\n-\tvfma.f64\td17, d23, d21\n-\tvstr\td26, [sp, #216]\t@ 0xd8\n-\tvldr\td23, [sp, #416]\t@ 0x1a0\n-\tvldr\td26, [sp, #376]\t@ 0x178\n-\tvstr\td25, [sp, #480]\t@ 0x1e0\n-\tvfma.f64\td17, d23, d20\n-\tvmov.f64\td23, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td21, d26, d7\n-\tvstr\td31, [sp, #496]\t@ 0x1f0\n-\tvfma.f64\td16, d21, d25\n-\tvldr\td21, [pc, #-384]\t@ 5a30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xeb8>\n-\tvmov.f64\td25, d11\n-\tvfms.f64\td25, d10, d21\n-\tvldr\td21, [sp, #608]\t@ 0x260\n-\tvmul.f64\td17, d22, d17\n-\tvmul.f64\td21, d21, d23\n-\tvfma.f64\td16, d21, d31\n-\tvstr\td21, [sp, #320]\t@ 0x140\n-\tvldr\td21, [sp, #16]\n-\tvmov.f64\td10, d25\n-\tvldr\td25, [sp, #704]\t@ 0x2c0\n-\tvsqrt.f64\td21, d21\n-\tvmul.f64\td24, d25, d23\n-\tvldr\td25, [sp, #192]\t@ 0xc0\n-\tvstr\td21, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td21, d26, d25\n-\tvmov.f64\td26, #8\t@ 0x40400000 3.0\n-\tvstr\td21, [sp, #48]\t@ 0x30\n-\tvldr\td21, [pc, #-448]\t@ 5a38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xec0>\n-\tvmul.f64\td21, d8, d21\n-\tvldr\td8, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td25, d8, d21\n-\tvldr\td8, [sp, #32]\n-\tvmul.f64\td8, d8, d21\n-\tvldr\td21, [sp, #376]\t@ 0x178\n-\tvstr\td8, [sp, #32]\n-\tvmul.f64\td8, d21, d26\n-\tvstr\td8, [sp, #200]\t@ 0xc8\n-\tvldr\td8, [sp, #24]\n-\tvmul.f64\td21, d8, d26\n-\tvldr\td8, [sp, #48]\t@ 0x30\n-\tvstr\td21, [sp, #8]\n-\tvmul.f64\td21, d11, d8\n-\tvldr\td8, [sp, #8]\n-\tvfma.f64\td16, d21, d8\n-\tvldr\td8, [sp, #216]\t@ 0xd8\n-\tvfms.f64\td16, d11, d8\n-\tvldr\td8, [sp, #448]\t@ 0x1c0\n-\tvmov.f64\td21, d16\n-\tvmul.f64\td16, d19, d8\n-\tvldr\td8, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td19, d19, d8\n-\tvldr\td8, [sp, #336]\t@ 0x150\n-\tvstr\td19, [sp, #472]\t@ 0x1d8\n-\tvmul.f64\td19, d24, d10\n-\tvfms.f64\td19, d8, d16\n-\tvadd.f64\td16, d17, d24\n-\tvfma.f64\td19, d17, d11\n-\tvstr\td16, [sp, #520]\t@ 0x208\n-\tvldr\td16, [sp, #912]\t@ 0x390\n-\tvldr\td17, [sp, #40]\t@ 0x28\n-\tvfms.f64\td19, d31, d16\n-\tvmul.f64\td31, d17, d16\n-\tvldr\td16, [pc, #-580]\t@ 5a40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xec8>\n-\tvstr\td31, [sp, #544]\t@ 0x220\n-\tvmov.f64\td31, d11\n-\tvmov.f64\td24, d19\n-\tvldr\td19, [sp, #464]\t@ 0x1d0\n-\tvfms.f64\td31, d19, d16\n-\tvmul.f64\td16, d31, d23\n-\tvmul.f64\td23, d8, d14\n-\tvmul.f64\td14, d22, d14\n-\tvstr\td16, [sp, #504]\t@ 0x1f8\n-\tvldr\td16, [pc, #-612]\t@ 5a48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xed0>\n-\tvdiv.f64\td17, d16, d25\n-\tvldr\td16, [pc, #-612]\t@ 5a50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xed8>\n-\tvmul.f64\td16, d5, d16\n-\tvmul.f64\td16, d16, d3\n-\tvstr\td17, [sp, #536]\t@ 0x218\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n-\tvldr\td19, [sp, #688]\t@ 0x2b0\n-\tvldr\td25, [sp, #192]\t@ 0xc0\n-\tvmul.f64\td20, d20, d17\n-\tvldr\td8, [sp, #200]\t@ 0xc8\n-\tvdiv.f64\td16, d16, d19\n-\tvstr\td23, [sp, #456]\t@ 0x1c8\n-\tvldr\td19, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td23, d25, d8\n-\tvadd.f64\td19, d19, d19\n-\tvfms.f64\td21, d11, d23\n-\tvldr\td23, [sp, #184]\t@ 0xb8\n-\tvnmul.f64\td19, d11, d19\n-\tvstr\td16, [sp, #168]\t@ 0xa8\n-\tvmov.f64\td16, d21\n-\tvldr\td21, [pc, #-680]\t@ 5a58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xee0>\n-\tvmul.f64\td25, d23, d21\n-\tvldr\td23, [pc, #-680]\t@ 5a60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xee8>\n-\tvfma.f64\td16, d25, d19\n-\tvstr\td25, [sp, #328]\t@ 0x148\n-\tvldr\td25, [sp, #680]\t@ 0x2a8\n-\tvmov.f64\td19, #107\t@ 0x3f580000 0.8437500\n-\tvdiv.f64\td25, d19, d25\n-\tvldr\td19, [sp, #672]\t@ 0x2a0\n-\tvmul.f64\td21, d19, d10\n-\tvmul.f64\td8, d19, d13\n-\tvldr\td19, [sp, #336]\t@ 0x150\n-\tvmul.f64\td19, d19, d15\n-\tvmul.f64\td15, d22, d15\n-\tvstr\td21, [sp, #384]\t@ 0x180\n-\tvldr\td21, [pc, #-724]\t@ 5a68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xef0>\n-\tvldr\td22, [pc, #-720]\t@ 5a70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xef8>\n-\tvstr\td15, [sp, #376]\t@ 0x178\n-\tvldr\td15, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td21, d31, d21\n-\tvstr\td19, [sp, #392]\t@ 0x188\n-\tvmul.f64\td19, d20, d15\n-\tvldr\td15, [sp, #392]\t@ 0x188\n-\tvstr\td25, [sp, #72]\t@ 0x48\n-\tvldr\td25, [sp, #664]\t@ 0x298\n-\tvmul.f64\td10, d25, d10\n-\tvmul.f64\td25, d25, d13\n-\tvfma.f64\td24, d19, d10\n-\tvmul.f64\td19, d0, d21\n-\tvldr\td0, [sp, #144]\t@ 0x90\n-\tvmul.f64\td20, d20, d25\n-\tvmul.f64\td23, d0, d23\n-\tvldr\td0, [sp, #264]\t@ 0x108\n-\tvstr\td20, [sp, #552]\t@ 0x228\n-\tvmov.f64\td20, #4\t@ 0x40200000 2.5\n-\tvmul.f64\td18, d18, d20\n-\tvfms.f64\td16, d0, d23\n-\tvldr\td0, [sp, #384]\t@ 0x180\n-\tvmul.f64\td0, d0, d15\n-\tvldr\td15, [sp, #488]\t@ 0x1e8\n-\tvfma.f64\td24, d0, d18\n-\tvmul.f64\td0, d18, d8\n-\tvldr\td18, [pc, #-816]\t@ 5a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf00>\n-\tvmul.f64\td18, d15, d18\n-\tvstr\td0, [sp, #512]\t@ 0x200\n-\tvldr\td0, [sp, #256]\t@ 0x100\n-\tvfms.f64\td16, d0, d18\n-\tvldr\td0, [sp, #128]\t@ 0x80\n-\tvmov.f64\td18, #27\t@ 0x40d80000 6.750\n-\tvfma.f64\td16, d0, d24\n-\tvldr\td24, [sp, #152]\t@ 0x98\n-\tvldr\td0, [sp, #240]\t@ 0xf0\n-\tvdiv.f64\td15, d18, d24\n-\tvmul.f64\td24, d21, d22\n-\tvldr\td18, [pc, #-856]\t@ 5a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf08>\n-\tvdiv.f64\td0, d24, d0\n-\tvfnms.f64\td0, d4, d21\n-\tvldr\td21, [sp, #432]\t@ 0x1b0\n-\tvdiv.f64\td21, d18, d21\n-\tvldr\td18, [pc, #-868]\t@ 5a88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf10>\n-\tvstr\td21, [sp, #256]\t@ 0x100\n-\tvldr\td21, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td18, d21, d18\n-\tvldr\td21, [sp, #768]\t@ 0x300\n-\tvfms.f64\td16, d21, d18\n-\tvldr\td21, [sp, #872]\t@ 0x368\n-\tvldr\td18, [sp, #536]\t@ 0x218\n-\tvldr\td24, [sp, #32]\n-\tvfms.f64\td16, d21, d18\n-\tvldr\td18, [pc, #-900]\t@ 5a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf18>\n-\tvldr\td21, [sp, #720]\t@ 0x2d0\n-\tvdiv.f64\td18, d18, d24\n-\tvldr\td24, [sp, #152]\t@ 0x98\n-\tvstr\td18, [sp, #264]\t@ 0x108\n-\tvldr\td18, [pc, #-912]\t@ 5a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf20>\n-\tvmul.f64\td18, d3, d18\n-\tvldr\td3, [sp, #368]\t@ 0x170\n-\tvdiv.f64\td21, d18, d21\n-\tvldr\td18, [pc, #-920]\t@ 5aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf28>\n-\tvmul.f64\td18, d5, d18\n-\tvldr\td5, [sp, #728]\t@ 0x2d8\n-\tvdiv.f64\td5, d18, d5\n-\tvldr\td18, [pc, #-928]\t@ 5aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf30>\n-\tvmul.f64\td18, d3, d18\n-\tvldr\td3, [sp, #816]\t@ 0x330\n-\tvfms.f64\td16, d3, d18\n-\tvmul.f64\td18, d24, d20\n-\tvldr\td3, [sp, #488]\t@ 0x1e8\n-\tvldr\td24, [pc, #-944]\t@ 5ab0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf38>\n-\tvmul.f64\td18, d18, d31\n-\tvstr\td21, [sp, #144]\t@ 0x90\n-\tvldr\td21, [sp, #72]\t@ 0x48\n-\tvmul.f64\td18, d18, d21\n-\tvldr\td21, [pc, #-956]\t@ 5ab8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf40>\n-\tvstr\td5, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td21, d3, d21\n-\tvldr\td5, [sp, #208]\t@ 0xd0\n-\tvmul.f64\td3, d31, d5\n-\tvfms.f64\td16, d27, d21\n-\tvldr\td27, [pc, #-972]\t@ 5ac0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf48>\n-\tvldr\td5, [sp, #400]\t@ 0x190\n-\tvldr\td21, [pc, #-972]\t@ 5ac8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf50>\n-\tvfma.f64\td18, d3, d27\n-\tvstr\td3, [sp, #368]\t@ 0x170\n-\tvldr\td27, [pc, #-976]\t@ 5ad0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xf58>\n-\tvldr\td3, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td21, d5, d21\n-\tvldr\td5, [sp, #600]\t@ 0x258\n-\tvmul.f64\td27, d3, d27\n-\tvldr\td3, [sp, #416]\t@ 0x1a0\n-\tvdiv.f64\td24, d24, d5\n-\tvldr\td5, [sp, #736]\t@ 0x2e0\n-\tvfms.f64\td16, d5, d27\n-\tvldr\td5, [sp, #800]\t@ 0x320\n-\tvadd.f64\td27, d21, d21\n-\tvmul.f64\td21, d21, d17\n-\tvmul.f64\td17, d31, d17\n-\tvfms.f64\td16, d2, d23\n-\tvldr\td2, [sp, #168]\t@ 0xa8\n-\tvldr\td23, [pc, #948]\t@ 6290 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1718>\n-\tvmul.f64\td27, d27, d3\n-\tvldr\td3, [sp, #480]\t@ 0x1e0\n-\tvfms.f64\td16, d5, d7\n-\tvldr\td7, [sp, #264]\t@ 0x108\n-\tvfms.f64\td16, d30, d7\n-\tvldr\td7, [sp, #408]\t@ 0x198\n-\tvldr\td30, [sp, #528]\t@ 0x210\n-\tvstr\td16, [sp, #264]\t@ 0x108\n-\tvmov.f64\td16, #12\t@ 0x40600000 3.5\n-\tvnmul.f64\td16, d16, d31\n-\tvfma.f64\td18, d2, d16\n-\tvldr\td16, [pc, #908]\t@ 6298 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1720>\n-\tvstr\td24, [sp, #32]\n-\tvldr\td24, [pc, #908]\t@ 62a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1728>\n-\tvmul.f64\td16, d7, d16\n-\tvldr\td7, [sp, #424]\t@ 0x1a8\n-\tvldr\td2, [sp, #88]\t@ 0x58\n-\tvmul.f64\td7, d7, d24\n-\tvmul.f64\td7, d7, d30\n-\tvmov.f64\td30, d15\n-\tvfma.f64\td30, d2, d23\n-\tvnmul.f64\td23, d23, d19\n-\tvfms.f64\td18, d17, d7\n-\tvmov.f64\td5, d30\n-\tvmul.f64\td30, d21, d25\n-\tvadd.f64\td25, d16, d16\n-\tvmul.f64\td21, d14, d21\n-\tvmul.f64\td18, d18, d22\n-\tvstr\td30, [sp, #416]\t@ 0x1a0\n-\tvldr\td30, [sp, #184]\t@ 0xb8\n-\tvmul.f64\td25, d25, d3\n-\tvfma.f64\td25, d30, d27\n-\tvldr\td30, [pc, #840]\t@ 62a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1730>\n-\tvmul.f64\td30, d19, d30\n-\tvmov.f64\td3, d25\n-\tvmul.f64\td25, d16, d20\n-\tvmul.f64\td16, d11, d3\n-\tvstr\td3, [sp, #400]\t@ 0x190\n-\tvfma.f64\td16, d10, d21\n-\tvldr\td21, [sp, #176]\t@ 0xb0\n-\tvldr\td10, [sp, #472]\t@ 0x1d8\n-\tvldr\td27, [sp, #496]\t@ 0x1f0\n-\tvldr\td2, [sp, #256]\t@ 0x100\n-\tvfms.f64\td16, d21, d10\n-\tvldr\td21, [pc, #800]\t@ 62b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1738>\n-\tvldr\td3, [pc, #804]\t@ 62b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1740>\n-\tvmul.f64\td3, d29, d3\n-\tvldr\td29, [sp, #424]\t@ 0x1a8\n-\tvmov.f64\td10, d16\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvfms.f64\td10, d27, d9\n-\tvldr\td27, [sp, #272]\t@ 0x110\n-\tvmul.f64\td11, d9, d16\n-\tvmov.f64\td9, d5\n-\tvmov.f64\td15, d10\n-\tvldr\td10, [sp, #920]\t@ 0x398\n-\tvfma.f64\td9, d10, d21\n-\tvmul.f64\td21, d31, d27\n-\tvldr\td10, [sp, #864]\t@ 0x360\n-\tvmov.f64\td16, d9\n-\tvldr\td9, [sp, #104]\t@ 0x68\n-\tvfms.f64\td16, d2, d6\n-\tvneg.f64\td2, d2\n-\tvldr\td6, [sp, #280]\t@ 0x118\n-\tvstr\td2, [sp, #256]\t@ 0x100\n-\tvmov.f64\td2, d19\n-\tvfma.f64\td2, d21, d6\n-\tvldr\td21, [pc, #876]\t@ 6358 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e0>\n-\tvldr\td6, [sp, #504]\t@ 0x1f8\n-\tvfma.f64\td18, d0, d21\n-\tvmov.f64\td21, #114\t@ 0x3f900000 1.125\n-\tvmul.f64\td9, d9, d21\n-\tvmov.f64\td27, d2\n-\tvmov.f64\td2, d30\n-\tvfma.f64\td2, d31, d16\n-\tvldr\td30, [pc, #924]\t@ 63a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1830>\n-\tvldr\td16, [sp, #264]\t@ 0x108\n-\tvfma.f64\td16, d27, d30\n-\tvmov.f64\td27, #0\t@ 0x40000000 2.0\n-\tvfma.f64\td16, d3, d18\n-\tvstr\td2, [sp, #408]\t@ 0x198\n-\tvldr\td2, [pc, #868]\t@ 6388 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1810>\n-\tvnmul.f64\td2, d2, d10\n-\tvldr\td10, [sp, #312]\t@ 0x138\n-\tvfnms.f64\td10, d9, d27\n-\tvldr\td27, [sp, #144]\t@ 0x90\n-\tvmov.f64\td18, d10\n-\tvmov.f64\td10, d23\n-\tvfma.f64\td18, d2, d26\n-\tvldr\td23, [sp, #528]\t@ 0x210\n-\tvfma.f64\td10, d31, d18\n-\tvmov.f64\td18, #98\t@ 0x3f100000 0.5625000\n-\tvmul.f64\td18, d29, d18\n-\tvmul.f64\td29, d18, d23\n-\tvmul.f64\td18, d31, d20\n-\tvldr\td23, [sp, #376]\t@ 0x178\n-\tvmul.f64\td18, d18, d27\n-\tvldr\td27, [sp, #368]\t@ 0x170\n-\tvstr\td29, [sp, #88]\t@ 0x58\n-\tvfma.f64\td18, d27, d24\n-\tvldr\td24, [sp, #880]\t@ 0x370\n-\tvmov.f64\td27, d18\n-\tvldr\td18, [sp, #208]\t@ 0xd0\n-\tvfnms.f64\td27, d17, d29\n-\tvldr\td29, [sp, #288]\t@ 0x120\n-\tvmul.f64\td30, d18, d21\n-\tvmov.f64\td26, d27\n-\tvldr\td27, [sp, #160]\t@ 0xa0\n-\tvnmul.f64\td17, d27, d17\n-\tvmul.f64\td27, d19, d21\n-\tvldr\td21, [sp, #32]\n-\tvfma.f64\td17, d6, d30\n-\tvfma.f64\td27, d29, d31\n-\tvldr\td29, [sp, #384]\t@ 0x180\n-\tvmul.f64\td18, d21, d6\n-\tvldr\td21, [pc, #740]\t@ 6390 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1818>\n-\tvldr\td6, [sp, #624]\t@ 0x270\n-\tvmul.f64\td23, d23, d29\n-\tvmul.f64\td19, d19, d21\n-\tvldr\td21, [sp, #408]\t@ 0x198\n-\tvfma.f64\td19, d31, d6\n-\tvldr\td6, [pc, #508]\t@ 62c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1748>\n-\tvldr\td31, [pc, #680]\t@ 6370 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f8>\n-\tvmul.f64\td6, d24, d6\n-\tvldr\td24, [sp, #776]\t@ 0x308\n-\tvnmul.f64\td31, d31, d0\n-\tvfma.f64\td31, d26, d22\n-\tvfma.f64\td16, d6, d21\n-\tvldr\td21, [pc, #648]\t@ 6368 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f0>\n-\tvfma.f64\td18, d0, d21\n-\tvldr\td21, [pc, #480]\t@ 62c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1750>\n-\tvmul.f64\td21, d24, d21\n-\tvmov.f64\td24, d15\n-\tvfma.f64\td24, d23, d25\n-\tvldr\td23, [sp, #224]\t@ 0xe0\n-\tvldr\td15, [pc, #468]\t@ 62d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1758>\n-\tvmul.f64\td25, d25, d8\n-\tvmul.f64\td29, d29, d23\n-\tvldr\td23, [pc, #464]\t@ 62d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1760>\n-\tvfma.f64\td16, d19, d21\n-\tvmul.f64\td29, d29, d20\n-\tvldr\td20, [sp, #128]\t@ 0x80\n-\tvmov.f64\td19, d24\n-\tvldr\td24, [pc, #580]\t@ 6360 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e8>\n-\tvnmul.f64\td23, d23, d20\n-\tvldr\td20, [pc, #444]\t@ 62e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1768>\n-\tvmul.f64\td24, d0, d24\n-\tvfma.f64\td24, d17, d22\n-\tvldr\td17, [pc, #648]\t@ 63b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1840>\n-\tvfma.f64\td16, d18, d23\n-\tvldr\td18, [sp, #824]\t@ 0x338\n-\tvmul.f64\td17, d19, d17\n-\tvldr\td26, [sp, #448]\t@ 0x1c0\n-\tvldr\td19, [sp, #336]\t@ 0x150\n-\tvmul.f64\td15, d18, d15\n-\tvldr\td18, [sp, #896]\t@ 0x380\n-\tvldr\td22, [sp, #176]\t@ 0xb0\n-\tvldr\td0, [sp, #512]\t@ 0x200\n-\tvfma.f64\td16, d10, d15\n-\tvldr\td10, [pc, #396]\t@ 62e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1770>\n-\tvmul.f64\td10, d18, d10\n-\tvldr\td18, [sp, #64]\t@ 0x40\n-\tvmul.f64\td10, d10, d18\n-\tvldr\td18, [sp, #248]\t@ 0xf8\n-\tvmul.f64\td20, d18, d20\n-\tvldr\td18, [pc, #380]\t@ 62f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1778>\n-\tvfma.f64\td17, d24, d18\n-\tvldr\td18, [sp, #96]\t@ 0x60\n-\tvfms.f64\td16, d27, d20\n-\tvldr\td27, [sp, #552]\t@ 0x228\n-\tvldr\td24, [sp, #184]\t@ 0xb8\n-\tvfma.f64\td16, d18, d17\n-\tvldr\td18, [sp]\n-\tvldr\td17, [pc, #356]\t@ 62f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1780>\n-\tvmul.f64\td17, d18, d17\n-\tvldr\td18, [sp, #56]\t@ 0x38\n-\tvfma.f64\td10, d18, d17\n-\tvldr\td18, [sp, #656]\t@ 0x290\n-\tvldr\td17, [sp, #352]\t@ 0x160\n-\tvmul.f64\td10, d10, d12\n-\tvldr\td12, [sp, #544]\t@ 0x220\n-\tvfma.f64\td10, d18, d17\n-\tvldr\td18, [pc, #328]\t@ 6300 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1788>\n-\tvmul.f64\td17, d10, d26\n-\tvldr\td26, [sp, #456]\t@ 0x1c8\n-\tvfma.f64\td12, d19, d17\n-\tvldr\td19, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td17, d10, d19\n-\tvldr\td19, [sp, #376]\t@ 0x178\n-\tvfnms.f64\td12, d26, d27\n-\tvldr\td26, [sp, #392]\t@ 0x188\n-\tvfma.f64\td11, d22, d17\n-\tvldr\td17, [pc, #296]\t@ 6308 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1790>\n-\tvldr\td22, [sp, #416]\t@ 0x1a0\n-\tvfma.f64\td12, d26, d0\n-\tvldr\td26, [sp, #520]\t@ 0x208\n-\tvmul.f64\td10, d10, d17\n-\tvldr\td17, [pc, #396]\t@ 6380 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1808>\n-\tvfnms.f64\td11, d14, d22\n-\tvadd.f64\td14, d13, d13\n-\tvfma.f64\td12, d13, d26\n-\tvfma.f64\td29, d31, d17\n-\tvldr\td17, [sp, #296]\t@ 0x128\n-\tvmul.f64\td10, d10, d24\n-\tvfma.f64\td11, d19, d25\n-\tvldr\td19, [sp, #80]\t@ 0x50\n-\tvldr\td25, [sp, #400]\t@ 0x190\n-\tvfma.f64\td11, d13, d25\n-\tvfma.f64\td16, d17, d29\n-\tvldr\td17, [pc, #236]\t@ 6310 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1798>\n-\tvmul.f64\td17, d19, d17\n-\tvmul.f64\td17, d17, d16\n-\tvldr\td16, [sp, #576]\t@ 0x240\n-\tvmul.f64\td18, d16, d18\n-\tvldr\td16, [sp, #360]\t@ 0x168\n-\tvfma.f64\td17, d16, d18\n-\tvmov.f64\td18, #80\t@ 0x3e800000 0.250\n-\tvldr\td16, [r6]\n-\tvfma.f64\td16, d17, d18\n-\tvstr\td16, [r6]\n-\tvldr\td16, [pc, #200]\t@ 6318 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17a0>\n-\tvcmpe.f64\td1, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t662a <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1ab2>\n-\tvldr\td19, [sp, #16]\n-\tvldr\td17, [pc, #188]\t@ 6320 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17a8>\n-\tvldr\td16, [pc, #192]\t@ 6328 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17b0>\n-\tvldr\td18, [pc, #196]\t@ 6330 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17b8>\n-\tvadd.f64\td17, d19, d17\n-\tvadd.f64\td18, d19, d18\n-\tvfma.f64\td16, d19, d17\n-\tvldr\td17, [sp, #112]\t@ 0x70\n-\tvmul.f64\td16, d17, d16\n-\tvldr\td17, [pc, #180]\t@ 6338 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17c0>\n-\tvfma.f64\td17, d19, d18\n-\tvdiv.f64\td18, d16, d17\n-\tb.n\t63c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1850>\n-\tnop\n-\t.word\t0x3c998ed0\n-\t.word\t0x4016107d\n \t.word\t0xa6db20a2\n \t.word\t0xbfc0a036\n-\t.word\t0xaa145d16\n-\t.word\t0x3ff3edc9\n-\t.word\t0x47c07d65\n-\t.word\t0x40286dc6\n-\t.word\t0xaa145d16\n-\t.word\t0x4013edc9\n \t.word\t0x03ebac6c\n \t.word\t0xbfb0a5f6\n \t.word\t0x925fea34\n \t.word\t0x3f8134f5\n \t.word\t0x6611d37c\n \t.word\t0x3fef1930\n-\t.word\t0xbcf04c7f\n-\t.word\t0x3e9d59da\n \t.word\t0x8d9aab4b\n \t.word\t0xbff20d34\n-\t.word\t0x61f2a45a\n-\t.word\t0x3ff73e68\n \t.word\t0x0f94a0b7\n \t.word\t0xbfda4852\n-\t.word\t0xdb7a9450\n-\t.word\t0xbf5b1c19\n+\t.word\t0xbcf04c7f\n+\t.word\t0x3e9d59da\n \t.word\t0x1ff9d571\n \t.word\t0x3fe5eb4b\n-\t.word\t0xbda12f68\n-\t.word\t0x3ff2f684\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n+\t.word\t0x61f2a45a\n+\t.word\t0x3ff73e68\n+\t.word\t0xdb7a9450\n+\t.word\t0xbf5b1c19\n+\t.word\t0xbda12f68\n+\t.word\t0x3ff2f684\n \t.word\t0xfe791dd3\n \t.word\t0xbfe7a245\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n-\t.word\t0x949a5658\n-\t.word\t0x3ff26e82\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n+\t.word\t0x949a5658\n+\t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n \t.word\t0x91b4ef6b\n \t.word\t0x3ffc5bf8\n \t.word\t0x3c998ed0\n \t.word\t0x4006107d\n \t.word\t0xaa145d16\n \t.word\t0x3ff3edc9\n \t.word\t0x05d583db\n \t.word\t0x40206aa4\n \t.word\t0x091f4276\n \t.word\t0x3ffac8f9\n-\t.word\t0x3bad40f9\n-\t.word\t0x3fe8314e\n \t.word\t0xfd70288b\n \t.word\t0x400da7c1\n+\t.word\t0x3bad40f9\n+\t.word\t0x3fe8314e\n+\t.word\t0x2c4fea23\n+\t.word\t0x3ff04201\n \t.word\t0x26b8069e\n \t.word\t0xbff3e3fe\n+\t.word\t0xaa145d16\n+\t.word\t0x4013edc9\n+\t.word\t0x5e247885\n+\t.word\t0x3f55ce9e\n \t.word\t0x26a72f3e\n \t.word\t0xbfe2341c\n-\t.word\t0x2c4fea23\n-\t.word\t0x3ff04201\n \t.word\t0xaa145d16\n \t.word\t0x4003edc9\n-\t.word\t0xaa145d16\n-\t.word\t0x4013edc9\n-\t.word\t0x47c07d65\n-\t.word\t0x40286dc6\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n+\t.word\t0x47c07d65\n+\t.word\t0x40286dc6\n \t.word\t0xfe791dd3\n \t.word\t0xbfc7a245\n-\t.word\t0x5e247885\n-\t.word\t0x3f55ce9e\n \t.word\t0x3c998ed0\n \t.word\t0x4016107d\n-\tvldr\td16, [sp, #112]\t@ 0x70\n-\tvldr\td17, [sp, #120]\t@ 0x78\n-\tvldr\td19, [sp, #40]\t@ 0x28\n-\tvsub.f64\td18, d18, d16\n-\tvldr\td16, [sp, #344]\t@ 0x158\n-\tvldr\td29, [sp, #272]\t@ 0x110\n-\tvsub.f64\td22, d16, d17\n-\tvldr\td16, [sp, #216]\t@ 0xd8\n-\tvldr\td17, [sp, #320]\t@ 0x140\n-\tvmul.f64\td18, d18, d28\n-\tvnmul.f64\td16, d16, d13\n-\tvfma.f64\td16, d17, d19\n-\tvldr\td17, [sp, #208]\t@ 0xd0\n-\tvmov.f64\td24, d18\n-\tvmul.f64\td19, d13, d17\n-\tvldr\td17, [sp, #8]\n-\tvmul.f64\td27, d17, d13\n-\tvldr\td17, [sp, #200]\t@ 0xc8\n-\tvadd.f64\td16, d10, d16\n-\tvmul.f64\td26, d13, d17\n-\tvldr\td17, [sp, #232]\t@ 0xe8\n-\tvmul.f64\td25, d17, d14\n-\tvldr\td17, [sp, #280]\t@ 0x118\n-\tvmul.f64\td17, d13, d17\n-\tvfma.f64\td24, d29, d17\n-\tvldr\td29, [sp, #48]\t@ 0x30\n-\tvldr\td17, [sp, #312]\t@ 0x138\n-\tvfma.f64\td16, d29, d27\n-\tvldr\td27, [sp, #192]\t@ 0xc0\n-\tvldr\td29, [pc, #-256]\t@ 6340 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17c8>\n-\tvnmul.f64\td17, d13, d17\n-\tvfma.f64\td17, d9, d14\n-\tvfms.f64\td16, d27, d26\n-\tvldr\td26, [sp, #24]\n-\tvldr\td27, [sp, #240]\t@ 0xf0\n-\tvfms.f64\td16, d26, d10\n-\tvldr\td26, [sp, #328]\t@ 0x148\n-\tvfms.f64\td16, d26, d25\n-\tvldr\td25, [sp, #128]\t@ 0x80\n-\tvldr\td26, [sp, #224]\t@ 0xe0\n-\tvfma.f64\td16, d25, d12\n-\tvmov.f64\td25, #4\t@ 0x40200000 2.5\n-\tvmul.f64\td8, d8, d25\n-\tvmul.f64\td25, d13, d25\n-\tvmul.f64\td8, d8, d26\n-\tvldr\td26, [sp, #152]\t@ 0x98\n-\tvmul.f64\td31, d26, d25\n-\tvldr\td26, [sp, #144]\t@ 0x90\n-\tvmul.f64\td25, d26, d25\n-\tvmul.f64\td26, d28, d29\n-\tvdiv.f64\td27, d26, d27\n-\tvldr\td26, [pc, #-336]\t@ 6348 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17d0>\n-\tvmul.f64\td26, d19, d26\n-\tvfnms.f64\td27, d4, d28\n-\tvldr\td28, [sp, #72]\t@ 0x48\n-\tvfma.f64\td26, d28, d31\n-\tvmov.f64\td28, #12\t@ 0x40600000 3.5\n-\tvldr\td31, [sp, #168]\t@ 0xa8\n-\tvmul.f64\td28, d13, d28\n-\tvfms.f64\td26, d31, d28\n-\tvmov.f64\td28, #120\t@ 0x3fc00000 1.5\n-\tvldr\td31, [sp, #160]\t@ 0xa0\n-\tvmul.f64\td28, d13, d28\n-\tvfms.f64\td26, d7, d28\n-\tvnmul.f64\td7, d28, d31\n-\tvmov.f64\td31, #96\t@ 0x3f000000 0.5\n-\tvmul.f64\td31, d13, d31\n-\tvfma.f64\td7, d30, d31\n-\tvldr\td30, [pc, #-396]\t@ 6350 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17d8>\n-\tvfma.f64\td25, d19, d30\n-\tvldr\td19, [sp, #88]\t@ 0x58\n-\tvfnms.f64\td25, d19, d28\n-\tvldr\td28, [pc, #-404]\t@ 6358 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e0>\n-\tvldr\td19, [pc, #-400]\t@ 6360 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e8>\n-\tvmul.f64\td28, d27, d28\n-\tvfma.f64\td28, d26, d29\n-\tvldr\td26, [pc, #-404]\t@ 6368 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f0>\n-\tvmul.f64\td19, d27, d19\n-\tvfma.f64\td19, d7, d29\n-\tvmul.f64\td26, d27, d26\n-\tvfma.f64\td16, d3, d28\n-\tvldr\td28, [sp, #32]\n-\tvfma.f64\td26, d28, d31\n-\tvldr\td28, [sp, #256]\t@ 0x100\n-\tvfma.f64\td16, d23, d26\n-\tvldr\td23, [pc, #-432]\t@ 6370 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f8>\n-\tvldr\td26, [sp, #304]\t@ 0x130\n-\tvnmul.f64\td23, d23, d27\n-\tvmov.f64\td27, #16\t@ 0x40800000 4.0\n-\tvfma.f64\td23, d25, d29\n-\tvldr\td25, [pc, #-444]\t@ 6378 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1800>\n-\tvmul.f64\td27, d13, d27\n-\tvldr\td29, [pc, #-444]\t@ 6380 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1808>\n-\tvfma.f64\td11, d19, d25\n-\tvldr\td25, [pc, #-444]\t@ 6388 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1810>\n-\tvldr\td19, [sp, #136]\t@ 0x88\n-\tvmul.f64\td25, d13, d25\n-\tvfma.f64\td8, d23, d29\n-\tvldr\td23, [sp, #96]\t@ 0x60\n-\tvnmul.f64\td25, d19, d25\n-\tvldr\td19, [pc, #-460]\t@ 6390 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1818>\n-\tvfma.f64\td25, d26, d13\n-\tvldr\td26, [sp, #104]\t@ 0x68\n-\tvfma.f64\td25, d18, d19\n-\tvldr\td19, [pc, #-468]\t@ 6398 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1820>\n-\tvmul.f64\td19, d13, d19\n-\tvnmul.f64\td19, d26, d19\n-\tvldr\td26, [pc, #-472]\t@ 63a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1828>\n-\tvfma.f64\td19, d13, d5\n-\tvfma.f64\td19, d28, d27\n-\tvldr\td28, [pc, #-460]\t@ 63b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1840>\n-\tvldr\td27, [pc, #-480]\t@ 63a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1830>\n-\tvmul.f64\td23, d23, d28\n-\tvldr\td28, [r4]\n-\tvfma.f64\td19, d18, d26\n-\tvldr\td29, [sp, #80]\t@ 0x50\n-\tvldr\td26, [pc, #-492]\t@ 63b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1838>\n-\tvfma.f64\td16, d23, d11\n-\tvldr\td23, [sp, #296]\t@ 0x128\n-\tvmul.f64\td26, d29, d26\n-\tvfma.f64\td16, d23, d8\n-\tvfma.f64\td16, d24, d27\n-\tvfma.f64\td16, d25, d21\n-\tvmov.f64\td21, #8\t@ 0x40400000 3.0\n-\tvmul.f64\td13, d13, d21\n-\tvfma.f64\td16, d6, d19\n-\tvldr\td19, [pc, #-516]\t@ 63c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1848>\n-\tvfma.f64\td17, d2, d13\n-\tvfms.f64\td17, d18, d19\n-\tvmov.f64\td19, #114\t@ 0x3f900000 1.125\n-\tvnmul.f64\td18, d19, d18\n-\tvldr\td19, [sp, #288]\t@ 0x120\n-\tvfma.f64\td18, d19, d22\n-\tvfma.f64\td16, d18, d20\n-\tvfma.f64\td16, d17, d15\n-\tvfma.f64\td28, d16, d26\n-\tvstr\td28, [r4]\n-\tadd.w\tsp, sp, #1040\t@ 0x410\n+\tvldr\td5, [pc, #-252]\t@ 6550 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1788>\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [sp, #24]\n+\tvmul.f64\td4, d4, d2\n+\tvldr\td2, [sp]\n+\tvmul.f64\td2, d2, d5\n+\tvldr\td5, [pc, #-268]\t@ 6558 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1790>\n+\tvmul.f64\td5, d10, d5\n+\tvldr\td10, [sp, #120]\t@ 0x78\n+\tvmls.f64\td7, d3, d2\n+\tvstr\td2, [sp, #296]\t@ 0x128\n+\tvldr\td2, [pc, #-144]\t@ 65e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1820>\n+\tvldr\td3, [pc, #-284]\t@ 6560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1798>\n+\tvmul.f64\td5, d5, d10\n+\tvldr\td10, [sp, #936]\t@ 0x3a8\n+\tvmul.f64\td2, d1, d2\n+\tvnmls.f64\td2, d9, d14\n+\tvmul.f64\td14, d10, d3\n+\tvldr\td10, [sp, #168]\t@ 0xa8\n+\tvldr\td3, [pc, #-304]\t@ 6568 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17a0>\n+\tvldr\td9, [sp, #872]\t@ 0x368\n+\tvstr\td14, [sp, #120]\t@ 0x78\n+\tvmla.f64\td7, d0, d14\n+\tvmul.f64\td3, d10, d3\n+\tvldr\td10, [sp, #112]\t@ 0x70\n+\tvmla.f64\td5, d3, d10\n+\tvldr\td3, [sp, #184]\t@ 0xb8\n+\tvmla.f64\td9, d5, d3\n+\tvldr\td3, [sp, #656]\t@ 0x290\n+\tvldr\td1, [sp, #592]\t@ 0x250\n+\tvldr\td14, [sp, #672]\t@ 0x2a0\n+\tvldr\td0, [sp, #32]\n+\tvmul.f64\td5, d9, d3\n+\tvldr\td3, [sp, #680]\t@ 0x2a8\n+\tvmov.f64\td10, d9\n+\tvldr\td9, [sp, #504]\t@ 0x1f8\n+\tvmla.f64\td3, d5, d1\n+\tvldr\td5, [sp, #696]\t@ 0x2b8\n+\tvnmls.f64\td3, d14, d9\n+\tvldr\td14, [sp, #448]\t@ 0x1c0\n+\tvldr\td9, [sp, #432]\t@ 0x1b0\n+\tvmla.f64\td3, d5, d14\n+\tvldr\td5, [sp, #704]\t@ 0x2c0\n+\tvmov.f64\td14, d3\n+\tvldr\td3, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td14, d5, d8\n+\tvmul.f64\td5, d10, d3\n+\tvldr\td3, [sp, #528]\t@ 0x210\n+\tvmla.f64\td3, d5, d0\n+\tvldr\td0, [sp, #408]\t@ 0x198\n+\tvldr\td5, [sp, #64]\t@ 0x40\n+\tvmov.f64\td1, d14\n+\tvldr\td14, [sp, #520]\t@ 0x208\n+\tvnmls.f64\td3, d14, d9\n+\tvldr\td9, [sp, #400]\t@ 0x190\n+\tvmla.f64\td3, d4, d9\n+\tvldr\td4, [pc, #-444]\t@ 6570 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17a8>\n+\tvmul.f64\td10, d10, d4\n+\tvldr\td4, [pc, #-444]\t@ 6578 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17b0>\n+\tvmla.f64\td3, d8, d0\n+\tvmul.f64\td10, d10, d5\n+\tvldr\td5, [pc, #-448]\t@ 6580 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17b8>\n+\tvmul.f64\td5, d11, d5\n+\tvstr\td3, [sp, #112]\t@ 0x70\n+\tvldr\td3, [sp, #384]\t@ 0x180\n+\tvmul.f64\td3, d3, d4\n+\tvldr\td4, [sp, #416]\t@ 0x1a0\n+\tvmls.f64\td7, d4, d3\n+\tvldr\td4, [pc, #-332]\t@ 6610 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1848>\n+\tvstr\td3, [sp, #32]\n+\tvmla.f64\td5, d12, d4\n+\tvldr\td4, [sp, #160]\t@ 0xa0\n+\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n+\tvmla.f64\td7, d5, d4\n+\tvldr\td5, [pc, #-348]\t@ 6618 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1850>\n+\tvldr\td4, [sp, #136]\t@ 0x88\n+\tvmla.f64\td6, d2, d5\n+\tvldr\td5, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td7, d6, d5\n+\tvldr\td5, [sp, #336]\t@ 0x150\n+\tvldr\td6, [pc, #-516]\t@ 6588 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17c0>\n+\tvmul.f64\td6, d5, d6\n+\tvldr\td5, [sp, #1000]\t@ 0x3e8\n+\tvmul.f64\td6, d6, d5\n+\tvldr\td5, [pc, #-524]\t@ 6590 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17c8>\n+\tvmul.f64\td5, d4, d5\n+\tvmla.f64\td6, d7, d5\n+\tvldr\td7, [r6]\n+\tvmla.f64\td7, d6, d12\n+\tvadd.f64\td12, d8, d8\n+\tvstr\td7, [r6]\n+\tvldr\td7, [pc, #-544]\t@ 6598 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17d0>\n+\tvcmpe.f64\td15, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tbmi.w\t6a86 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1cbe>\n+\tvldr\td4, [sp, #72]\t@ 0x48\n+\tvldr\td6, [pc, #-556]\t@ 65a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17d8>\n+\tvldr\td7, [pc, #-544]\t@ 65b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e8>\n+\tvldr\td5, [pc, #-556]\t@ 65a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17e0>\n+\tvadd.f64\td6, d4, d6\n+\tvadd.f64\td5, d4, d5\n+\tvmla.f64\td7, d6, d4\n+\tvldr\td6, [sp, #176]\t@ 0xb0\n+\tvmul.f64\td7, d7, d6\n+\tvldr\td6, [pc, #-564]\t@ 65b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f0>\n+\tvmla.f64\td6, d5, d4\n+\tvdiv.f64\td4, d7, d6\n+\tvldr\td7, [sp, #176]\t@ 0xb0\n+\tvldr\td6, [sp, #536]\t@ 0x218\n+\tvldr\td5, [sp, #88]\t@ 0x58\n+\tvsub.f64\td4, d4, d7\n+\tvldr\td7, [sp, #544]\t@ 0x220\n+\tvldr\td0, [sp, #552]\t@ 0x228\n+\tvldr\td15, [sp, #392]\t@ 0x188\n+\tvsub.f64\td11, d7, d6\n+\tvldr\td7, [sp, #344]\t@ 0x158\n+\tvldr\td6, [sp, #304]\t@ 0x130\n+\tvmul.f64\td4, d4, d0\n+\tvmul.f64\td7, d8, d7\n+\tvmov.f64\td14, d4\n+\tvnmls.f64\td7, d6, d5\n+\tvldr\td6, [sp, #8]\n+\tvmul.f64\td9, d8, d6\n+\tvldr\td6, [sp, #312]\t@ 0x138\n+\tvmul.f64\td2, d6, d8\n+\tvldr\td6, [sp, #264]\t@ 0x108\n+\tvadd.f64\td7, d7, d10\n+\tvmul.f64\td3, d8, d6\n+\tvldr\td6, [sp, #352]\t@ 0x160\n+\tvmul.f64\td5, d6, d12\n+\tvldr\td6, [sp, #272]\t@ 0x110\n+\tvmul.f64\td6, d8, d6\n+\tvmla.f64\td14, d6, d15\n+\tvldr\td6, [sp, #496]\t@ 0x1f0\n+\tvmul.f64\td15, d6, d8\n+\tvldr\td6, [sp, #104]\t@ 0x68\n+\tvmla.f64\td7, d2, d6\n+\tvldr\td6, [sp, #144]\t@ 0x90\n+\tvnmls.f64\td15, d13, d12\n+\tvldr\td13, [sp, #216]\t@ 0xd8\n+\tvmls.f64\td7, d3, d6\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmls.f64\td7, d6, d10\n+\tvldr\td6, [sp, #320]\t@ 0x140\n+\tvmov.f64\td10, #12\t@ 0x40600000 3.5\n+\tvmul.f64\td10, d8, d10\n+\tvmls.f64\td7, d5, d6\n+\tvldr\td6, [sp]\n+\tvmla.f64\td7, d6, d1\n+\tvldr\td6, [sp, #24]\n+\tvldr\td1, [pc, #-740]\t@ 65c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x17f8>\n+\tvmul.f64\td5, d0, d1\n+\tvmov.f64\td12, d7\n+\tvmov.f64\td7, #4\t@ 0x40200000 2.5\n+\tvmul.f64\td3, d6, d7\n+\tvldr\td6, [sp, #256]\t@ 0x100\n+\tvmul.f64\td7, d8, d7\n+\tvmul.f64\td3, d3, d6\n+\tvldr\td6, [sp, #48]\t@ 0x30\n+\tvmul.f64\td2, d6, d7\n+\tvldr\td6, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td7, d6, d7\n+\tvldr\td6, [sp, #280]\t@ 0x118\n+\tvdiv.f64\td6, d5, d6\n+\tvldr\td5, [sp, #16]\n+\tvnmls.f64\td6, d5, d0\n+\tvldr\td5, [pc, #-796]\t@ 65c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1800>\n+\tvldr\td0, [sp, #128]\t@ 0x80\n+\tvmul.f64\td5, d9, d5\n+\tvmla.f64\td5, d2, d0\n+\tvmov.f64\td2, #120\t@ 0x3fc00000 1.5\n+\tvldr\td0, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td2, d8, d2\n+\tvmls.f64\td5, d10, d13\n+\tvldr\td10, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td0, d0, d2\n+\tvmls.f64\td5, d10, d2\n+\tvldr\td10, [pc, #-832]\t@ 65d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1808>\n+\tvmla.f64\td7, d9, d10\n+\tvldr\td9, [sp, #360]\t@ 0x168\n+\tvldr\td10, [sp, #80]\t@ 0x50\n+\tvnmls.f64\td7, d9, d2\n+\tvmov.f64\td9, #96\t@ 0x3f000000 0.5\n+\tvldr\td2, [sp, #368]\t@ 0x170\n+\tvmul.f64\td9, d8, d9\n+\tvnmls.f64\td0, d2, d9\n+\tvldr\td2, [pc, #-860]\t@ 65d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1810>\n+\tvmul.f64\td2, d6, d2\n+\tvmla.f64\td2, d5, d1\n+\tvmov.f64\td5, d12\n+\tvmla.f64\td5, d2, d10\n+\tvldr\td2, [pc, #-872]\t@ 65e0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1818>\n+\tvmul.f64\td2, d6, d2\n+\tvmla.f64\td2, d0, d1\n+\tvldr\td0, [pc, #-876]\t@ 65e8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1820>\n+\tvmul.f64\td0, d6, d0\n+\tvnmls.f64\td0, d7, d1\n+\tvldr\td7, [pc, #-880]\t@ 65f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1828>\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td1, [sp, #112]\t@ 0x70\n+\tvmla.f64\td6, d7, d9\n+\tvldr\td7, [sp, #296]\t@ 0x128\n+\tvldr\td9, [sp, #160]\t@ 0xa0\n+\tvmls.f64\td5, d6, d7\n+\tvldr\td6, [pc, #-904]\t@ 65f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1830>\n+\tvldr\td7, [pc, #-900]\t@ 6600 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1838>\n+\tvmul.f64\td6, d8, d6\n+\tvmla.f64\td1, d2, d7\n+\tvldr\td7, [sp, #200]\t@ 0xc8\n+\tvldr\td2, [sp, #56]\t@ 0x38\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [sp, #464]\t@ 0x1d0\n+\tvnmls.f64\td6, d7, d8\n+\tvldr\td7, [pc, #-924]\t@ 6608 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1840>\n+\tvmul.f64\td7, d8, d7\n+\tvmul.f64\td7, d7, d2\n+\tvldr\td2, [sp, #328]\t@ 0x148\n+\tvnmls.f64\td7, d8, d2\n+\tvldr\td2, [pc, #-936]\t@ 6610 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1848>\n+\tvmul.f64\td2, d9, d2\n+\tvmla.f64\td5, d1, d2\n+\tvldr\td2, [pc, #-940]\t@ 6618 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1850>\n+\tvmla.f64\td3, d0, d2\n+\tvldr\td2, [sp, #192]\t@ 0xc0\n+\tvmla.f64\td5, d3, d2\n+\tvmov.f64\td3, #16\t@ 0x40800000 4.0\n+\tvldr\td2, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td3, d8, d3\n+\tvmls.f64\td7, d3, d2\n+\tvldr\td3, [pc, #-964]\t@ 6620 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1858>\n+\tvldr\td2, [sp, #136]\t@ 0x88\n+\tvmla.f64\td6, d4, d3\n+\tvldr\td3, [pc, #-968]\t@ 6628 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1860>\n+\tvmla.f64\td5, d14, d3\n+\tvldr\td3, [sp, #376]\t@ 0x178\n+\tvmla.f64\td5, d6, d3\n+\tvldr\td6, [pc, #-976]\t@ 6630 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1868>\n+\tvldr\td3, [pc, #-972]\t@ 6638 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1870>\n+\tvmla.f64\td7, d4, d6\n+\tvldr\td6, [sp, #288]\t@ 0x120\n+\tvmul.f64\td3, d2, d3\n+\tvmla.f64\td5, d7, d6\n+\tvmov.f64\td7, #114\t@ 0x3f900000 1.125\n+\tvldr\td6, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td7, d4, d7\n+\tvnmls.f64\td7, d11, d6\n+\tvldr\td6, [sp, #32]\n+\tvmla.f64\td5, d7, d6\n+\tvmov.f64\td7, #8\t@ 0x40400000 3.0\n+\tvldr\td6, [pc, #-1012]\t@ 6640 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1878>\n+\tvmul.f64\td8, d8, d7\n+\tvldr\td7, [sp, #152]\t@ 0x98\n+\tvmls.f64\td15, d8, d7\n+\tvldr\td7, [r4]\n+\tvmls.f64\td15, d4, d6\n+\tvldr\td6, [sp, #120]\t@ 0x78\n+\tvmla.f64\td5, d15, d6\n+\tvmla.f64\td7, d5, d3\n+\tvstr\td7, [r4]\n+\tadd.w\tsp, sp, #1032\t@ 0x408\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvldr\td0, [sp, #16]\n-\tvstr\td19, [sp, #272]\t@ 0x110\n-\tvstr\td6, [sp, #168]\t@ 0xa8\n-\tvstr\td1, [sp, #160]\t@ 0xa0\n+\tvldr\td14, [sp, #72]\t@ 0x48\n+\tvmov.f64\td0, d14\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td15, d0\n-\tvldr\td0, [sp, #16]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td1, [sp, #160]\t@ 0xa0\n-\tvldr\td6, [sp, #168]\t@ 0xa8\n-\tvldr\td19, [sp, #272]\t@ 0x110\n-\tvmul.f64\td15, d15, d0\n-\tb.w\t521c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x6a4>\n-\tvldr\td0, [sp, #16]\n-\tvstr\td23, [sp, #376]\t@ 0x178\n-\tvstr\td2, [sp, #368]\t@ 0x170\n-\tvstr\td20, [sp, #360]\t@ 0x168\n-\tvstr\td21, [sp, #352]\t@ 0x160\n-\tvstr\td30, [sp, #336]\t@ 0x150\n-\tvstr\td5, [sp, #264]\t@ 0x108\n-\tvstr\td7, [sp, #248]\t@ 0xf8\n-\tvstr\td28, [sp, #184]\t@ 0xb8\n-\tvstr\td3, [sp, #176]\t@ 0xb0\n-\tvstr\td6, [sp, #64]\t@ 0x40\n-\tvstr\td4, [sp, #56]\t@ 0x38\n+\tvmov.f64\td8, d0\n+\tvmov.f64\td0, d14\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td7, d8, d0\n+\tvstr\td7, [sp]\n+\tb.w\t545c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x694>\n+\tvldr\td11, [sp, #72]\t@ 0x48\n+\tvstr\td1, [sp, #64]\t@ 0x40\n+\tvmov.f64\td0, d11\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, d0\n-\tvldr\td0, [sp, #16]\n-\tvstr\td16, [sp]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp]\n-\tvldr\td4, [sp, #56]\t@ 0x38\n-\tvldr\td6, [sp, #64]\t@ 0x40\n-\tvmul.f64\td18, d16, d0\n-\tvldr\td3, [sp, #176]\t@ 0xb0\n-\tvldr\td28, [sp, #184]\t@ 0xb8\n-\tvldr\td7, [sp, #248]\t@ 0xf8\n-\tvldr\td5, [sp, #264]\t@ 0x108\n-\tvldr\td30, [sp, #336]\t@ 0x150\n-\tvldr\td21, [sp, #352]\t@ 0x160\n-\tvldr\td20, [sp, #360]\t@ 0x168\n-\tvldr\td2, [sp, #368]\t@ 0x170\n-\tvldr\td23, [sp, #376]\t@ 0x178\n-\tb.n\t63c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1850>\n-\tadd.w\tr3, sp, #1032\t@ 0x408\n-\tvldr\td0, [sp, #16]\n-\tvstr\td29, [sp, #1016]\t@ 0x3f8\n-\tvstr\td30, [sp, #1008]\t@ 0x3f0\n-\tvstr\td28, [r3]\n-\tadd.w\tr3, sp, #1024\t@ 0x400\n-\tvstr\td3, [sp, #1000]\t@ 0x3e8\n-\tvstr\td26, [sp, #992]\t@ 0x3e0\n-\tvstr\td25, [r3]\n-\tvstr\td2, [sp, #984]\t@ 0x3d8\n-\tvstr\td31, [sp, #976]\t@ 0x3d0\n-\tvstr\td5, [sp, #968]\t@ 0x3c8\n-\tvstr\td27, [sp, #960]\t@ 0x3c0\n-\tvstr\td4, [sp, #952]\t@ 0x3b8\n-\tvstr\td7, [sp, #944]\t@ 0x3b0\n-\tvstr\td19, [sp, #936]\t@ 0x3a8\n-\tvstr\td6, [sp, #928]\t@ 0x3a0\n-\tvstr\td1, [sp, #368]\t@ 0x170\n+\tvmov.f64\td9, d0\n+\tvmov.f64\td0, d11\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvldr\td1, [sp, #64]\t@ 0x40\n+\tvmul.f64\td4, d9, d0\n+\tb.n\t67f4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0x1a2c>\n+\tvldr\td12, [sp, #72]\t@ 0x48\n+\tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td8, d0\n-\tvldr\td0, [sp, #16]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n \tadd.w\tr3, sp, #1024\t@ 0x400\n-\tvldr\td1, [sp, #368]\t@ 0x170\n-\tvldr\td6, [sp, #928]\t@ 0x3a0\n-\tvldr\td25, [r3]\n-\tadd.w\tr3, sp, #1032\t@ 0x408\n-\tvmul.f64\td0, d8, d0\n-\tvldr\td19, [sp, #936]\t@ 0x3a8\n-\tvldr\td7, [sp, #944]\t@ 0x3b0\n-\tvldr\td4, [sp, #952]\t@ 0x3b8\n-\tvldr\td27, [sp, #960]\t@ 0x3c0\n-\tvldr\td5, [sp, #968]\t@ 0x3c8\n-\tvldr\td31, [sp, #976]\t@ 0x3d0\n-\tvldr\td2, [sp, #984]\t@ 0x3d8\n-\tvldr\td26, [sp, #992]\t@ 0x3e0\n-\tvldr\td3, [sp, #1000]\t@ 0x3e8\n-\tvldr\td30, [sp, #1008]\t@ 0x3f0\n-\tvldr\td29, [sp, #1016]\t@ 0x3f8\n-\tvldr\td28, [r3]\n-\tb.w\t569c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xb24>\n+\tvstr\td0, [r3]\n+\tvmov.f64\td0, d12\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tadd.w\tr3, sp, #1024\t@ 0x400\n+\tvldr\td7, [r3]\n+\tvmul.f64\td0, d7, d0\n+\tb.w\t5964 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0+0xb9c>\n \n-00006748 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>:\n+00006ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>:\n __gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0():\n \tpush\t{r4, r5, r6, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #2816]\t@ 0xb00\n-\tvldr\td14, [pc, #1012]\t@ 6b50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x408>\n-\tvmul.f64\td11, d1, d1\n+\tstr.w\tr0, [ip, #2808]\t@ 0xaf8\n+\tvldr\td10, [pc, #1012]\t@ 6ee0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x408>\n+\tvmul.f64\td12, d1, d1\n \tmov\tr4, r2\n-\tldr.w\tr2, [pc, #1192]\t@ 6c10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4c8>\n-\tvmov.f64\td12, #80\t@ 0x3e800000 0.250\n-\tldr.w\tr3, [pc, #1188]\t@ 6c14 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4cc>\n+\tldr.w\tr2, [pc, #1184]\t@ 6f98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4c0>\n+\tvmov.f64\td9, #80\t@ 0x3e800000 0.250\n+\tldr.w\tr3, [pc, #1180]\t@ 6f9c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4c4>\n+\tsub.w\tsp, sp, #1208\t@ 0x4b8\n \tadd\tr2, pc\n-\tvmul.f64\td14, d0, d14\n-\tvmov.f64\td10, d0\n-\tvmul.f64\td16, d11, d12\n-\tsub.w\tsp, sp, #1200\t@ 0x4b0\n-\tvmov.f64\td8, d1\n+\tvmul.f64\td10, d0, d10\n+\tvmov.f64\td13, d1\n+\tvmul.f64\td1, d12, d9\n+\tvmov.f64\td11, d0\n+\tvstr\td12, [sp, #320]\t@ 0x140\n+\tvmov.f64\td14, d2\n \tldr\tr3, [r2, r3]\n-\tvmov.f64\td9, d2\n-\tvmov.f64\td0, d14\n \tmov\tr5, r0\n+\tvmov.f64\td0, d10\n+\tmov\tr6, r1\n \tldr\tr3, [r3, #0]\n-\tstr.w\tr3, [sp, #1196]\t@ 0x4ac\n+\tstr.w\tr3, [sp, #1204]\t@ 0x4b4\n \tmov.w\tr3, #0\n-\tmov\tr6, r1\n-\tvstr\td16, [sp, #208]\t@ 0xd0\n+\tvstr\td1, [sp, #104]\t@ 0x68\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmul.f64\td22, d10, d10\n-\tvmul.f64\td26, d0, d0\n-\tvmul.f64\td13, d11, d11\n-\tvldr\td20, [pc, #932]\t@ 6b58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x410>\n-\tvmov.f64\td16, #112\t@ 0x3f800000 1.0\n-\tvldr\td19, [pc, #932]\t@ 6b60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x418>\n-\tvldr\td18, [pc, #936]\t@ 6b68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x420>\n-\tvmov.f64\td24, d9\n-\tvmul.f64\td25, d22, d22\n-\tvmul.f64\td17, d14, d26\n-\tvmul.f64\td29, d13, d20\n-\tvmov.f64\td27, d26\n-\tvmul.f64\td20, d14, d0\n-\tvstr\td22, [sp, #224]\t@ 0xe0\n-\tvdiv.f64\td28, d16, d22\n-\tvldr\td22, [pc, #908]\t@ 6b70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x428>\n-\tvmul.f64\td7, d25, d25\n-\tvmul.f64\td18, d11, d18\n-\tvdiv.f64\td14, d16, d27\n-\tvmul.f64\td9, d9, d9\n-\tvmul.f64\td27, d11, d22\n-\tvstr\td26, [sp, #216]\t@ 0xd8\n-\tvdiv.f64\td22, d16, d20\n-\tvstr\td25, [sp, #584]\t@ 0x248\n-\tvdiv.f64\td20, d16, d17\n-\tvmul.f64\td31, d18, d13\n-\tvmul.f64\td18, d25, d10\n-\tvmul.f64\td26, d9, d9\n-\tvdiv.f64\td17, d19, d7\n-\tvldr\td21, [pc, #860]\t@ 6b78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x430>\n-\tvdiv.f64\td30, d16, d25\n-\tvldr\td23, [pc, #860]\t@ 6b80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x438>\n-\tvstr\td27, [sp, #552]\t@ 0x228\n-\tvmul.f64\td27, d27, d12\n-\tvdiv.f64\td19, d16, d18\n-\tvmul.f64\td25, d9, d26\n-\tvstr\td26, [sp, #600]\t@ 0x258\n-\tvmul.f64\td23, d13, d23\n-\tvstr\td21, [sp, #72]\t@ 0x48\n-\tvstr\td29, [sp, #608]\t@ 0x260\n-\tvstr\td25, [sp, #672]\t@ 0x2a0\n-\tvstr\td23, [sp, #568]\t@ 0x238\n-\tvmul.f64\td23, d23, d21\n-\tvstr\td31, [sp, #656]\t@ 0x290\n-\tvstr\td7, [sp, #664]\t@ 0x298\n-\tvstr\td24, [sp, #376]\t@ 0x178\n-\tvstr\td23, [sp, #576]\t@ 0x240\n-\tvstr\td27, [sp, #560]\t@ 0x230\n-\tvstr\td0, [sp, #40]\t@ 0x28\n-\tvmov.f64\td0, d10\n-\tvldr\td3, [pc, #792]\t@ 6b88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x440>\n-\tvstr\td28, [sp, #128]\t@ 0x80\n-\tvmul.f64\td3, d14, d3\n-\tvstr\td22, [sp, #136]\t@ 0x88\n-\tvstr\td20, [sp, #16]\n-\tvmul.f64\td25, d17, d25\n-\tvldr\td17, [pc, #776]\t@ 6b90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x448>\n-\tvmul.f64\td15, d30, d26\n-\tvstr\td30, [sp, #592]\t@ 0x250\n-\tvmov.f64\td30, d16\n-\tvmul.f64\td26, d26, d24\n-\tvstr\td19, [sp, #640]\t@ 0x280\n-\tvfma.f64\td30, d31, d25\n-\tvstr\td25, [sp, #408]\t@ 0x198\n-\tvmul.f64\td15, d15, d22\n-\tvmul.f64\td22, d13, d8\n-\tvmul.f64\td25, d29, d21\n-\tvmul.f64\td18, d19, d26\n-\tvstr\td26, [sp, #648]\t@ 0x288\n-\tvmul.f64\td26, d14, d28\n-\tvmul.f64\td21, d11, d12\n-\tvstr\td22, [sp, #392]\t@ 0x188\n-\tvmul.f64\td22, d22, d17\n-\tvmul.f64\td19, d18, d20\n-\tvldr\td18, [pc, #712]\t@ 6b98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x450>\n-\tvstr\td25, [sp, #616]\t@ 0x268\n-\tvmov.f64\td17, d30\n-\tvstr\td26, [sp, #232]\t@ 0xe8\n-\tvfma.f64\td17, d15, d25\n-\tvmul.f64\td25, d22, d18\n-\tvstr\td22, [sp, #624]\t@ 0x270\n-\tvmul.f64\td18, d23, d15\n-\tvmul.f64\td26, d9, d26\n-\tvstr\td19, [sp, #400]\t@ 0x190\n-\tvstr\td25, [sp, #632]\t@ 0x278\n-\tvmov.f64\td22, d17\n-\tvfma.f64\td22, d25, d19\n-\tvmul.f64\td25, d21, d14\n-\tvmov.f64\td21, d18\n-\tvmul.f64\td19, d28, d9\n-\tvfma.f64\td21, d27, d26\n-\tvldr\td18, [pc, #652]\t@ 6ba0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x458>\n-\tvstr\td22, [sp, #120]\t@ 0x78\n-\tvstr\td26, [sp, #384]\t@ 0x180\n-\tvdiv.f64\td26, d16, d22\n-\tvstr\td16, [sp, #64]\t@ 0x40\n-\tvstr\td21, [sp, #56]\t@ 0x38\n-\tvstr\td19, [sp, #48]\t@ 0x30\n-\tvstr\td25, [sp]\n-\tvmul.f64\td16, d21, d26\n-\tvstr\td26, [sp, #24]\n-\tvstr\td16, [sp, #240]\t@ 0xf0\n-\tvmul.f64\td16, d19, d16\n-\tvfma.f64\td3, d25, d16\n-\tvstr\td16, [sp, #8]\n-\tvmul.f64\td22, d3, d18\n-\tvstr\td3, [sp, #168]\t@ 0xa8\n-\tvstr\td22, [sp, #32]\n+\tvmov.f64\td7, d0\n+\tvmov.f64\td8, #112\t@ 0x3f800000 1.0\n+\tvmul.f64\td0, d0, d0\n+\tvmul.f64\td1, d11, d11\n+\tvldr\td5, [pc, #924]\t@ 6ee8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x410>\n+\tvmul.f64\td3, d14, d14\n+\tvmov.f64\td2, d14\n+\tvstr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td7, d10, d7\n+\tvmul.f64\td10, d10, d0\n+\tvstr\td13, [sp, #184]\t@ 0xb8\n+\tvstr\td1, [sp, #336]\t@ 0x150\n+\tvstr\td2, [sp, #576]\t@ 0x240\n+\tvdiv.f64\td6, d8, d7\n+\tvldr\td7, [pc, #892]\t@ 6ef0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x418>\n+\tvdiv.f64\td15, d8, d10\n+\tvstr\td0, [sp, #328]\t@ 0x148\n+\tvstr\td3, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td7, d12, d7\n+\tvstr\td6, [sp, #40]\t@ 0x28\n+\tvmul.f64\td6, d1, d1\n+\tvdiv.f64\td1, d8, d1\n+\tvstr\td15, [sp, #48]\t@ 0x30\n+\tvmul.f64\td10, d6, d6\n+\tvmov.f64\td4, d6\n+\tvstr\td6, [sp, #800]\t@ 0x320\n+\tvdiv.f64\td6, d5, d10\n+\tvstr\td10, [sp, #848]\t@ 0x350\n+\tvdiv.f64\td10, d8, d4\n+\tvmul.f64\td5, d4, d11\n+\tvmul.f64\td4, d3, d3\n+\tvdiv.f64\td14, d8, d5\n+\tvmul.f64\td5, d12, d12\n+\tvstr\td4, [sp, #816]\t@ 0x330\n+\tvmul.f64\td7, d7, d5\n+\tvstr\td5, [sp, #592]\t@ 0x250\n+\tvstr\td7, [sp, #376]\t@ 0x178\n+\tvmul.f64\td7, d3, d4\n+\tvstr\td7, [sp, #856]\t@ 0x358\n+\tvstr\td1, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td6, d6, d7\n+\tvldr\td7, [pc, #792]\t@ 6ef8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x420>\n+\tvstr\td10, [sp, #808]\t@ 0x328\n+\tvstr\td6, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td6, d5, d7\n+\tvmul.f64\td7, d10, d4\n+\tvmul.f64\td10, d5, d13\n+\tvmul.f64\td4, d4, d2\n+\tvstr\td14, [sp, #680]\t@ 0x2a8\n+\tvstr\td6, [sp, #360]\t@ 0x168\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmov.f64\td13, d10\n+\tvmov.f64\td2, d4\n+\tvstr\td4, [sp, #840]\t@ 0x348\n+\tvstr\td10, [sp, #608]\t@ 0x260\n+\tvmul.f64\td6, d7, d6\n+\tvldr\td7, [pc, #740]\t@ 6f00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x428>\n+\tvldr\td10, [pc, #744]\t@ 6f08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x430>\n+\tvmul.f64\td4, d13, d7\n+\tvmov.f64\td13, d1\n+\tvldr\td1, [sp, #208]\t@ 0xd0\n+\tvmov.f64\td7, d8\n+\tvstr\td6, [sp, #600]\t@ 0x258\n+\tvstr\td4, [sp, #368]\t@ 0x170\n+\tvdiv.f64\td4, d8, d0\n+\tvldr\td0, [sp, #376]\t@ 0x178\n+\tvmla.f64\td7, d0, d1\n+\tvldr\td0, [sp, #360]\t@ 0x168\n+\tvmov.f64\td1, d6\n+\tvmul.f64\td0, d0, d10\n+\tvmla.f64\td7, d6, d0\n+\tvmul.f64\td6, d14, d2\n+\tvstr\td0, [sp, #824]\t@ 0x338\n+\tvmul.f64\td14, d6, d15\n+\tvldr\td6, [pc, #684]\t@ 6f10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x438>\n+\tvstr\td14, [sp, #616]\t@ 0x268\n+\tvldr\td0, [sp, #368]\t@ 0x170\n+\tvmul.f64\td6, d0, d6\n+\tvmov.f64\td0, d7\n+\tvldr\td7, [pc, #672]\t@ 6f18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x440>\n+\tvmla.f64\td0, d6, d14\n+\tvmul.f64\td14, d5, d7\n+\tvldr\td7, [pc, #668]\t@ 6f20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x448>\n+\tvstr\td6, [sp, #832]\t@ 0x340\n+\tvmul.f64\td6, d12, d7\n+\tvstr\td14, [sp, #784]\t@ 0x310\n+\tvmul.f64\td14, d14, d10\n+\tvldr\td7, [pc, #656]\t@ 6f28 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d10\n+\tvstr\td6, [sp, #424]\t@ 0x1a8\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td22, [sp, #88]\t@ 0x58\n-\tvmov.f64\td17, #120\t@ 0x3fc00000 1.5\n-\tvldr\td19, [sp, #240]\t@ 0xf0\n-\tadd.w\tr0, sp, #1184\t@ 0x4a0\n-\tvldr\td16, [sp, #80]\t@ 0x50\n-\tvmul.f64\td29, d8, d17\n-\tvldr\td18, [sp, #40]\t@ 0x28\n-\tvmul.f64\td19, d19, d22\n-\tvldr\td23, [sp, #96]\t@ 0x60\n-\tvldr\td24, [sp, #376]\t@ 0x178\n-\tvdiv.f64\td26, d16, d18\n-\tvstr\td0, [sp, #280]\t@ 0x118\n-\tvmul.f64\td23, d29, d23\n-\tvstr\td16, [sp, #88]\t@ 0x58\n-\tvsqrt.f64\td22, d19\n-\tvstr\td19, [sp, #760]\t@ 0x2f8\n-\tvdiv.f64\td19, d16, d10\n-\tvstr\td29, [sp, #752]\t@ 0x2f0\n-\tvstr\td26, [sp, #80]\t@ 0x50\n-\tvmul.f64\td26, d23, d26\n-\tvmul.f64\td24, d22, d24\n-\tvstr\td22, [sp, #432]\t@ 0x1b0\n-\tvstr\td19, [sp, #288]\t@ 0x120\n-\tvstr\td26, [sp, #488]\t@ 0x1e8\n-\tvmul.f64\td0, d19, d24\n-\tvstr\td24, [sp, #768]\t@ 0x300\n-\tvmul.f64\td0, d0, d26\n-\tbl\t0 <__gridxc_xwpbe_MOD_calerf.constprop.0.isra.0>\n-\tvldr\td17, [pc, #232]\t@ 6c08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4c0>\n-\tvldr\td2, [sp, #160]\t@ 0xa0\n-\tadd.w\tr3, sp, #1184\t@ 0x4a0\n-\tvldr\td25, [sp]\n-\tvmul.f64\td24, d14, d17\n-\tvldr\td18, [sp, #8]\n-\tvldr\td17, [r3]\n-\tadd.w\tr3, sp, #1048\t@ 0x418\n-\tvldr\td23, [sp, #152]\t@ 0x98\n-\tvldr\td21, [sp, #272]\t@ 0x110\n-\tvadd.f64\td2, d24, d2\n-\tb.n\t6c18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4d0>\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tadd.w\tr0, sp, #1192\t@ 0x4a8\n+\tvldr\td6, [sp, #24]\n+\tvldr\td3, [sp, #384]\t@ 0x180\n+\tvdiv.f64\td7, d8, d7\n+\tvldr\td5, [sp, #184]\t@ 0xb8\n+\tvldr\td2, [sp, #576]\t@ 0x240\n+\tvmul.f64\td3, d3, d6\n+\tvstr\td0, [sp, #432]\t@ 0x1b0\n+\tvsqrt.f64\td1, d3\n+\tvstr\td3, [sp, #904]\t@ 0x388\n+\tvmov.f64\td4, d7\n+\tvstr\td7, [sp, #168]\t@ 0xa8\n+\tvdiv.f64\td7, d8, d11\n+\tvmul.f64\td2, d1, d2\n+\tvstr\td1, [sp, #672]\t@ 0x2a0\n+\tvstr\td2, [sp, #912]\t@ 0x390\n+\tb.n\t6fa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x4c8>\n \tnop.w\n \t.word\t0x2e9d68cd\n \t.word\t0x403d9bdb\n-\t.word\t0xaefb2aae\n-\t.word\t0x3fc7fe08\n \t.word\t0x63e07ae3\n \t.word\t0x3f52b04b\n \t.word\t0x9d1cdbd9\n \t.word\t0x3f41c6a9\n-\t.word\t0x9470e5c6\n-\t.word\t0x3f841059\n-\t.word\t0x00000000\n-\t.word\t0x3fb00000\n-\t.word\t0x26d12521\n-\t.word\t0x3fa508e2\n-\t.word\t0x77655a1a\n-\t.word\t0x3f920a14\n+\t.word\t0xaefb2aae\n+\t.word\t0x3fc7fe08\n \t.word\t0xd2493883\n \t.word\t0x3f53cbb9\n \t.word\t0x00000000\n+\t.word\t0x3fb00000\n+\t.word\t0x00000000\n \t.word\t0x3fa00000\n+\t.word\t0x26d12521\n+\t.word\t0x3fa508e2\n+\t.word\t0x9470e5c6\n+\t.word\t0x3f841059\n \t.word\t0x25676f30\n \t.word\t0x4001b6ec\n+\t.word\t0x77655a1a\n+\t.word\t0x3f920a14\n \t.word\t0x8d84e354\n \t.word\t0x3fe27ddb\n \t.word\t0xe03dc2d9\n \t.word\t0x4019e6cb\n \t.word\t0xb9f05136\n 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\t.word\t0x3fe27ddb\n-\t.word\t0x0758138d\n-\t.word\t0x3fecd0f6\n \t.word\t0x5dae292a\n \t.word\t0x408b6574\n+\t.word\t0x0758138d\n+\t.word\t0x3fecd0f6\n \t.word\t0xc277df34\n \t.word\t0x3fd86301\n \t.word\t0x3c998ed0\n \t.word\t0x4016107d\n-\t.word\t0xaa145d16\n-\t.word\t0x4003edc9\n \t.word\t0x2c4fea23\n \t.word\t0x3fd04201\n+\t.word\t0xaa145d16\n+\t.word\t0x4003edc9\n \t.word\t0x3315d702\n \t.word\t0x3fee7bc2\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n \t.word\t0xc277df34\n \t.word\t0x40086301\n \t.word\t0x47c07d65\n@@ -7451,32 +7688,30 @@\n \t.word\t0x3f2330b4\n \t.word\t0xaa145d16\n \t.word\t0x3ff3edc9\n \t.word\t0x925fea34\n \t.word\t0x3f8134f5\n \t.word\t0x86a35812\n \t.word\t0x3e570440\n-\t.word\t0x61f2a45a\n-\t.word\t0x3ff73e68\n \t.word\t0x8d9aab4b\n \t.word\t0xbff20d34\n-\t.word\t0x91b4ef6b\n-\t.word\t0x3ffc5bf8\n \t.word\t0xc28f5c29\n \t.word\t0x3fbc28f5\n-\t.word\t0x25676f30\n-\t.word\t0x4001b6ec\n-\t.word\t0x091f4276\n-\t.word\t0x3ffac8f9\n \t.word\t0xfd70288b\n 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d5\n+\tvldr\td5, [pc, #-608]\t@ 7558 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xa80>\n \tadd.w\tr3, sp, #1152\t@ 0x480\n-\tvldr\td16, [sp, #224]\t@ 0xe0\n-\tvmov.f64\td30, #112\t@ 0x3f800000 1.0\n-\tvmov.f64\td20, #20\t@ 0x40a00000 5.0\n-\tvldr\td23, [sp, #608]\t@ 0x260\n-\tvadd.f64\td8, d8, d8\n-\tvstr\td31, [r3]\n-\tadd.w\tr3, sp, #1144\t@ 0x478\n-\tvmul.f64\td31, d16, d10\n-\tvldr\td25, [pc, #-712]\t@ 7208 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xac0>\n-\tvldr\td27, [sp, #576]\t@ 0x240\n+\tvmul.f64\td5, d3, d5\n+\tvldr\td3, [sp, #208]\t@ 0xd0\n+\tvmul.f64\td5, d5, d3\n+\tvldr\td3, [pc, #-620]\t@ 7560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xa88>\n+\tvmul.f64\td3, d4, d3\n+\tvmla.f64\td5, d3, d8\n+\tvldr\td3, [sp, #488]\t@ 0x1e8\n+\tvadd.f64\td4, d3, d1\n+\tvldr\td3, [sp, #176]\t@ 0xb0\n+\tvmla.f64\td7, d4, d3\n+\tvldr\td4, [pc, #-640]\t@ 7568 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xa90>\n+\tvmul.f64\td3, d6, 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<__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1300>\n-\tvfms.f64\td20, d21, d24\n-\tvmov.f64\td27, d4\n-\tvldr\td4, [sp, #696]\t@ 0x2b8\n-\tvldr\td21, [pc, #880]\t@ 7a50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1308>\n-\tvnmul.f64\td27, d27, d4\n-\tvneg.f64\td4, d16\n-\tvmov.f64\td11, d20\n-\tvmul.f64\td20, d28, d21\n-\tvfms.f64\td11, d19, d15\n-\tvstr\td4, [sp, #584]\t@ 0x248\n-\tvmul.f64\td4, d17, d10\n-\tvldr\td15, [pc, #856]\t@ 7a58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1310>\n-\tvnmul.f64\td20, d16, d20\n-\tvldr\td16, [pc, #856]\t@ 7a60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1318>\n-\tvfms.f64\td20, d22, d19\n-\tvmul.f64\td19, d30, d30\n-\tvstr\td4, [sp, #592]\t@ 0x250\n-\tvmov.f64\td3, d11\n-\tvstr\td19, [sp, #632]\t@ 0x278\n-\tvfms.f64\td3, d4, d16\n-\tvldr\td16, [pc, #836]\t@ 7a68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1320>\n-\tvfma.f64\td27, d20, d18\n-\tvldr\td18, [sp, #232]\t@ 0xe8\n-\tvmov.f64\td24, d3\n-\tvldr\td3, [sp, #720]\t@ 0x2d0\n-\tvfma.f64\td3, d2, d16\n-\tvstr\td27, [sp, #416]\t@ 0x1a0\n-\tvstr\td24, [sp, #720]\t@ 0x2d0\n-\tvmul.f64\td15, d24, d15\n-\tvmov.f64\td20, d3\n-\tvldr\td3, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td16, d3, d19\n-\tvdiv.f64\td25, d25, d16\n-\tvmul.f64\td16, d9, d26\n-\tvmul.f64\td16, d16, d18\n-\tvstr\td16, [sp, #640]\t@ 0x280\n-\tvldr\td16, [pc, #780]\t@ 7a70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1328>\n-\tvstr\td25, [sp, #600]\t@ 0x258\n-\tvldr\td21, [sp, #200]\t@ 0xc8\n-\tvldr\td6, [sp, #272]\t@ 0x110\n-\tvstr\td23, [sp, #224]\t@ 0xe0\n-\tvmul.f64\td18, d21, d16\n-\tvldr\td21, [pc, #764]\t@ 7a78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1330>\n-\tvldr\td16, [pc, #768]\t@ 7a80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1338>\n-\tvmul.f64\td6, d6, d29\n-\tvstr\td5, [sp]\n-\tvmul.f64\td2, d2, d21\n-\tvldr\td21, [pc, #760]\t@ 7a88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1340>\n-\tvmul.f64\td16, d31, d16\n-\tvstr\td18, [sp, #48]\t@ 0x30\n-\tvstr\td6, [sp, #616]\t@ 0x268\n-\tvfma.f64\td20, d30, d21\n-\tvstr\td2, [sp, #608]\t@ 0x260\n-\tvstr\td16, [sp, #232]\t@ 0xe8\n-\tvstr\td20, [sp, #624]\t@ 0x270\n+\tvldr\td14, [sp, #240]\t@ 0xf0\n+\tvmov.f64\td10, d0\n+\tvmul.f64\td0, d2, d3\n+\tvstr\td6, [sp, #368]\t@ 0x170\n+\tvmov.f64\td3, d0\n+\tvstr\td5, [sp, #344]\t@ 0x158\n+\tvmov.f64\td0, #2\t@ 0x40100000 2.250\n+\tvldr\td7, [sp, #320]\t@ 0x140\n+\tvmul.f64\td5, d14, d5\n+\tvldr\td2, [sp]\n+\tvldr\td6, [sp, #904]\t@ 0x388\n+\tvmul.f64\td0, d7, d0\n+\tvldr\td7, [sp, #272]\t@ 0x110\n+\tvstr\td10, [sp, #784]\t@ 0x310\n+\tvstr\td3, [sp, #680]\t@ 0x2a8\n+\tvstr\td1, [sp, #856]\t@ 0x358\n+\tvmul.f64\td0, d0, d2\n+\tvldr\td2, [sp, #128]\t@ 0x80\n+\tvmul.f64\td0, d0, d7\n+\tvldr\td7, [sp, #232]\t@ 0xe8\n+\tvnmul.f64\td0, d6, d0\n+\tvadd.f64\td6, d10, d10\n+\tvldr\td10, [sp, #104]\t@ 0x68\n+\tvmul.f64\td7, d10, d7\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [sp, #384]\t@ 0x180\n+\tvmul.f64\td3, d10, d3\n+\tvmul.f64\td14, d7, d14\n+\tvmul.f64\td2, d2, d6\n+\tvldr\td7, [sp, #32]\n+\tvstr\td14, [sp, #128]\t@ 0x80\n+\tvmov.f64\td10, d2\n+\tvldr\td14, [sp, #368]\t@ 0x170\n+\tvmul.f64\td2, d3, d4\n+\tvmul.f64\td4, d11, d4\n+\tvldr\td11, [sp, #872]\t@ 0x368\n+\tvmul.f64\td14, d7, d14\n+\tvmla.f64\td6, d4, d3\n+\tvldr\td4, [sp, #32]\n+\tvldr\td3, [r3]\n+\tvnmls.f64\td10, d14, d1\n+\tvstr\td14, [sp, #320]\t@ 0x140\n+\tvmul.f64\td2, d2, d4\n+\tvldr\td14, [sp, #368]\t@ 0x170\n+\tvmul.f64\td6, d6, d11\n+\tvmov.f64\td7, d10\n+\tvmls.f64\td7, d2, d3\n+\tvldr\td3, [pc, #720]\t@ 7df0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1318>\n+\tvldr\td2, [pc, #900]\t@ 7ea8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13d0>\n+\tvmov.f64\td11, d7\n+\tvmls.f64\td11, d5, d9\n+\tvldr\td9, [sp, #688]\t@ 0x2b0\n+\tvmul.f64\td5, d9, d5\n+\tvmul.f64\td9, d13, d3\n+\tvldr\td13, [pc, #756]\t@ 7e30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1358>\n+\tvmul.f64\td7, d4, d13\n+\tvldr\td4, [sp, #656]\t@ 0x290\n+\tvstr\td9, [sp, #792]\t@ 0x318\n+\tvmul.f64\td10, d4, d4\n+\tvnmls.f64\td5, d7, d14\n+\tvmov.f64\td7, d6\n+\tvmov.f64\td6, d11\n+\tvmov.f64\td14, d2\n+\tvnmls.f64\td7, d5, d1\n+\tvldr\td1, [sp, #864]\t@ 0x360\n+\tvldr\td5, [sp, #880]\t@ 0x370\n+\tvstr\td7, [sp, #336]\t@ 0x150\n+\tvldr\td7, [pc, #648]\t@ 7df8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1320>\n+\tvmls.f64\td6, d9, d7\n+\tvldr\td9, [pc, #600]\t@ 7dd0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x12f8>\n+\tvmov.f64\td13, d6\n+\tvldr\td6, [pc, #640]\t@ 7e00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1328>\n+\tvmla.f64\td5, d1, d6\n+\tvldr\td6, [sp, #264]\t@ 0x108\n+\tvmul.f64\td6, d6, d10\n+\tvdiv.f64\td9, d9, d6\n+\tvmov.f64\td7, d5\n+\tvldr\td5, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td6, d5, d2\n+\tvldr\td5, [sp, #352]\t@ 0x160\n+\tvmul.f64\td6, d6, d5\n+\tvstr\td6, [sp, #824]\t@ 0x338\n+\tvldr\td6, [pc, #604]\t@ 7e08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1330>\n+\tvstr\td9, [sp, #384]\t@ 0x180\n+\tvmul.f64\td9, d13, d6\n+\tvldr\td6, [pc, #600]\t@ 7e10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1338>\n+\tvstr\td9, [sp, #352]\t@ 0x160\n+\tvldr\td9, [sp, #88]\t@ 0x58\n+\tvmul.f64\td5, d9, d6\n+\tvldr\td6, [pc, #592]\t@ 7e18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1340>\n+\tvldr\td9, [pc, #596]\t@ 7e20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1348>\n+\tvstr\td5, [sp, #104]\t@ 0x68\n+\tvldr\td2, [sp, #624]\t@ 0x270\n+\tvmul.f64\td9, d2, d9\n+\tvmul.f64\td2, d1, d6\n+\tvldr\td6, [pc, #584]\t@ 7e28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1350>\n+\tvmla.f64\td7, d4, d6\n+\tvstr\td2, [sp, #800]\t@ 0x320\n+\tvldr\td6, [sp, #424]\t@ 0x1a8\n+\tvldr\td2, [pc, #624]\t@ 7e60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1388>\n+\tvmul.f64\td6, d6, d2\n+\tvstr\td7, [sp, #816]\t@ 0x330\n+\tvstr\td6, [sp, #808]\t@ 0x328\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvldr\td2, [sp, #1008]\t@ 0x3f0\n-\tadd.w\tr3, sp, #1072\t@ 0x430\n-\tvldr\td3, [sp, #1000]\t@ 0x3e8\n-\tvldr\td19, [sp, #936]\t@ 0x3a8\n-\tvldr\td20, [sp, #448]\t@ 0x1c0\n-\tvmul.f64\td3, d3, d2\n-\tvldr\td2, [sp, #928]\t@ 0x3a0\n-\tvldr\td24, [sp, #320]\t@ 0x140\n-\tvldr\td23, [sp, #880]\t@ 0x370\n-\tvmul.f64\td21, d2, d19\n-\tvldr\td2, [sp, #984]\t@ 0x3d8\n-\tvldr\td19, [sp, #992]\t@ 0x3e0\n-\tvstr\td3, [sp, #696]\t@ 0x2b8\n-\tvldr\td3, [r3]\n+\tadd.w\tr3, sp, #1096\t@ 0x448\n+\tvstr\td0, [sp, #624]\t@ 0x270\n+\tvldr\td2, [sp, #496]\t@ 0x1f0\n+\tvldr\td1, [sp, #504]\t@ 0x1f8\n+\tvldr\td0, [r3]\n+\tadd.w\tr3, sp, #1104\t@ 0x450\n+\tvldr\td4, [r3]\n+\tadd.w\tr3, sp, #1032\t@ 0x408\n+\tvmul.f64\td0, d0, d4\n+\tvstr\td0, [sp, #832]\t@ 0x340\n+\tvldr\td0, [r3]\n+\tadd.w\tr3, sp, #1040\t@ 0x410\n+\tvldr\td4, [r3]\n \tadd.w\tr3, sp, #1080\t@ 0x438\n-\tvmul.f64\td27, d2, d19\n-\tvldr\td2, [sp, #288]\t@ 0x120\n-\tvldr\td19, [sp, #376]\t@ 0x178\n-\tvldr\td22, [sp, #648]\t@ 0x288\n-\tvldr\td31, [sp, #456]\t@ 0x1c8\n-\tvmul.f64\td6, d2, d19\n-\tvldr\td19, [sp, #848]\t@ 0x350\n-\tvldr\td2, [sp, #840]\t@ 0x348\n-\tvmul.f64\td2, d2, d19\n-\tvldr\td19, [sp, #808]\t@ 0x328\n-\tvmov.f64\td1, d2\n-\tvldr\td2, [sp, #56]\t@ 0x38\n-\tvmul.f64\td5, d2, d20\n-\tvldr\td2, [sp, #800]\t@ 0x320\n-\tvmul.f64\td20, d2, d19\n-\tvldr\td2, [sp, #904]\t@ 0x388\n-\tvldr\td19, [sp, #824]\t@ 0x338\n-\tvstr\td5, [sp, #456]\t@ 0x1c8\n-\tvfms.f64\td24, d3, d2\n-\tvldr\td2, [r3]\n-\tadd.w\tr3, sp, #1136\t@ 0x470\n-\tvmul.f64\td2, d2, d19\n-\tvldr\td19, [sp, #872]\t@ 0x368\n-\tvldr\td17, [r3]\n-\tadd.w\tr3, sp, #1152\t@ 0x480\n-\tvmul.f64\td19, d19, d23\n-\tvldr\td23, [sp, #224]\t@ 0xe0\n-\tvnmul.f64\td17, d17, d31\n-\tvstr\td24, [sp, #208]\t@ 0xd0\n-\tvfma.f64\td22, d5, d23\n-\tvldr\td5, [pc, #552]\t@ 7a90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1348>\n-\tvstr\td19, [sp, #656]\t@ 0x290\n-\tvldr\td23, [sp, #72]\t@ 0x48\n-\tvldr\td30, [sp, #664]\t@ 0x298\n-\tvldr\td19, [sp, #632]\t@ 0x278\n-\tvdiv.f64\td23, d23, d2\n-\tvldr\td16, [sp, #232]\t@ 0xe8\n-\tvldr\td2, [sp, #216]\t@ 0xd8\n-\tvdiv.f64\td31, d30, d19\n-\tvldr\td26, [sp, #752]\t@ 0x2f0\n-\tvldr\td18, [sp, #136]\t@ 0x88\n-\tvmul.f64\td19, d2, d16\n-\tvldr\td2, [sp, #40]\t@ 0x28\n-\tvldr\td4, [sp, #488]\t@ 0x1e8\n-\tvmul.f64\td25, d18, d10\n-\tvldr\td10, [sp, #944]\t@ 0x3b0\n-\tvmul.f64\td2, d2, d16\n-\tvldr\td16, [sp, #888]\t@ 0x378\n-\tvldr\td29, [sp]\n-\tvmul.f64\td16, d3, d16\n-\tvstr\td2, [sp, #72]\t@ 0x48\n-\tvdiv.f64\td2, d30, d21\n-\tvmul.f64\td21, d26, d6\n-\tvdiv.f64\td26, d30, d16\n-\tvldr\td16, [sp, #528]\t@ 0x210\n-\tvmul.f64\td21, d21, d5\n-\tvdiv.f64\td5, d30, d1\n-\tvmul.f64\td10, d16, d10\n-\tvldr\td1, [sp, #128]\t@ 0x80\n-\tvldr\td16, [sp, #768]\t@ 0x300\n-\tvstr\td10, [sp, #664]\t@ 0x298\n-\tvmul.f64\td16, d1, d16\n-\tvldr\td10, [sp, #96]\t@ 0x60\n-\tvstr\td31, [sp, #56]\t@ 0x38\n-\tvldr\td31, [r3]\n+\tvmul.f64\td4, d0, d4\n+\tvldr\td0, [r3]\n+\tadd.w\tr3, sp, #1088\t@ 0x440\n+\tvldr\td5, [r3]\n \tadd.w\tr3, sp, #1160\t@ 0x488\n-\tvstr\td2, [sp, #376]\t@ 0x178\n-\tvdiv.f64\td2, d30, d20\n-\tvstr\td26, [sp, #40]\t@ 0x28\n-\tvldr\td26, [sp, #240]\t@ 0xf0\n-\tvstr\td5, [sp, #632]\t@ 0x278\n-\tvldr\td5, [sp, #432]\t@ 0x1b0\n-\tvdiv.f64\td20, d30, d5\n-\tvmul.f64\td21, d21, d5\n-\tvmul.f64\td21, d21, d18\n-\tvmov.f64\td18, d21\n-\tvfma.f64\td18, d4, d16\n-\tvmul.f64\td16, d22, d26\n-\tvstr\td16, [sp, #648]\t@ 0x288\n-\tvldr\td16, [sp, #552]\t@ 0x228\n-\tvstr\td18, [sp, #96]\t@ 0x60\n-\tvnmul.f64\td30, d16, d29\n-\tvstr\td20, [sp, #288]\t@ 0x120\n-\tvldr\td20, [sp, #328]\t@ 0x148\n-\tvmul.f64\td20, d10, d20\n-\tvmul.f64\td10, d10, d31\n-\tvstr\td20, [sp, #688]\t@ 0x2b0\n-\tvstr\td10, [sp, #216]\t@ 0xd8\n-\tvldr\td29, [r3]\n+\tvmul.f64\td0, d0, d5\n+\tvldr\td5, [sp, #576]\t@ 0x240\n+\tvstr\td0, [sp, #360]\t@ 0x168\n+\tvldr\td0, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td6, d0, d5\n+\tvldr\td0, [sp, #136]\t@ 0x88\n+\tvstr\td6, [sp, #376]\t@ 0x178\n+\tvldr\td6, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td5, d0, d6\n+\tvldr\td0, [sp, #976]\t@ 0x3d0\n+\tvldr\td6, [sp, #472]\t@ 0x1d8\n+\tvstr\td5, [sp, #424]\t@ 0x1a8\n+\tvmul.f64\td5, d0, d6\n+\tvldr\td0, [sp, #952]\t@ 0x3b8\n+\tvldr\td6, [sp, #456]\t@ 0x1c8\n+\tvmul.f64\td6, d0, d6\n+\tvldr\td0, [sp, #512]\t@ 0x200\n+\tvmls.f64\td2, d15, d0\n+\tvldr\td0, [sp, #1000]\t@ 0x3e8\n+\tvmul.f64\td0, d0, d1\n+\tvldr\td1, [sp, #968]\t@ 0x3c8\n+\tvstr\td0, [sp, #512]\t@ 0x200\n+\tvldr\td0, [sp, #936]\t@ 0x3a8\n+\tvstr\td2, [sp, #240]\t@ 0xf0\n+\tvldr\td2, [sp, #688]\t@ 0x2b0\n+\tvmul.f64\td3, d0, d1\n+\tvmov.f64\td1, #112\t@ 0x3f800000 1.0\n+\tvdiv.f64\td10, d1, d10\n+\tvmul.f64\td7, d2, d12\n+\tvdiv.f64\td5, d1, d5\n+\tvldr\td2, [sp, #400]\t@ 0x190\n+\tvldr\td0, [r3]\n \tadd.w\tr3, sp, #1048\t@ 0x418\n-\tvldr\td21, [sp, #112]\t@ 0x70\n+\tvldr\td12, [pc, #284]\t@ 7df0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1318>\n+\tvmul.f64\td2, d2, d0\n+\tvldr\td0, [sp, #160]\t@ 0xa0\n+\tvdiv.f64\td0, d0, d3\n+\tvldr\td3, [sp, #328]\t@ 0x148\n+\tvstr\td10, [sp, #120]\t@ 0x78\n+\tvmul.f64\td10, d3, d9\n+\tvldr\td3, [sp, #112]\t@ 0x70\n+\tvstr\td5, [sp, #456]\t@ 0x1c8\n+\tvldr\td5, [sp, #344]\t@ 0x158\n+\tvmul.f64\td3, d3, d9\n+\tvldr\td9, [sp, #1008]\t@ 0x3f0\n+\tvstr\td3, [sp, #840]\t@ 0x348\n+\tvmul.f64\td3, d15, d9\n+\tvstr\td0, [sp, #136]\t@ 0x88\n+\tvdiv.f64\td0, d1, d4\n+\tvldr\td9, [sp, #40]\t@ 0x28\n+\tvldr\td4, [sp, #896]\t@ 0x380\n+\tvdiv.f64\td3, d1, d3\n+\tvmul.f64\td9, d9, d12\n+\tvldr\td12, [sp, #376]\t@ 0x178\n+\tvmul.f64\td4, d4, d12\n+\tvldr\td12, [pc, #188]\t@ 7de8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1310>\n+\tvmul.f64\td4, d4, d12\n+\tvldr\td12, [r3]\n+\tadd.w\tr3, sp, #1184\t@ 0x4a0\n+\tvstr\td0, [sp, #400]\t@ 0x190\n+\tvldr\td0, [sp, #760]\t@ 0x2f8\n+\tvstr\td3, [sp]\n+\tvmul.f64\td3, d0, d12\n+\tvldr\td12, [sp, #912]\t@ 0x390\n+\tvldr\td0, [sp, #424]\t@ 0x1a8\n+\tvstr\td3, [sp, #112]\t@ 0x70\n+\tvldr\td3, [sp, #224]\t@ 0xe0\n+\tvmul.f64\td3, d3, d12\n+\tvldr\td12, [sp, #320]\t@ 0x140\n+\tvmls.f64\td12, d5, d0\n+\tvmov.f64\td5, d12\n+\tvdiv.f64\td12, d1, d6\n+\tvldr\td6, [sp, #672]\t@ 0x2a0\n+\tvdiv.f64\td0, d1, d6\n+\tvmul.f64\td4, d4, d6\n+\tvldr\td1, [sp, #992]\t@ 0x3e0\n+\tvmul.f64\td14, d5, d14\n+\tvldr\td6, [sp, #8]\n+\tvmul.f64\td1, d6, d1\n+\tvstr\td1, [sp, #576]\t@ 0x240\n+\tvldr\td1, [sp, #704]\t@ 0x2c0\n+\tvmul.f64\td3, d3, d1\n+\tvstr\td12, [sp, #504]\t@ 0x1f8\n+\tvldr\td12, [sp, #24]\n+\tvstr\td0, [sp, #440]\t@ 0x1b8\n+\tvmul.f64\td0, d6, d12\n+\tvldr\td6, [sp, #40]\t@ 0x28\n+\tvmla.f64\td3, d4, d6\n \tvstr\td0, [sp, #320]\t@ 0x140\n-\tvldr\td0, [r3]\n-\tadd.w\tr3, sp, #1120\t@ 0x460\n-\tvsub.f64\td16, d29, d21\n-\tvldr\td21, [sp, #960]\t@ 0x3c0\n-\tvldr\td29, [sp, #352]\t@ 0x160\n-\tvldr\td20, [pc, #220]\t@ 7a50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1308>\n-\tvldr\td28, [sp, #24]\n-\tvsub.f64\td29, d29, d21\n-\tvldr\td7, [sp, #472]\t@ 0x1d8\n-\tvldr\td10, [sp, #728]\t@ 0x2d8\n-\tvmul.f64\td16, d16, d15\n-\tvmul.f64\td8, d8, d28\n-\tvldr\td18, [sp, #760]\t@ 0x2f8\n-\tvldr\td21, [sp, #704]\t@ 0x2c0\n-\tvstr\td29, [sp, #672]\t@ 0x2a0\n-\tvldr\td29, [r3]\n-\tadd.w\tr3, sp, #1104\t@ 0x450\n-\tvmul.f64\td8, d8, d7\n-\tvldr\td4, [sp, #264]\t@ 0x108\n-\tvmul.f64\td20, d29, d20\n-\tvmul.f64\td29, d29, d14\n-\tvnmul.f64\td0, d0, d4\n-\tvldr\td5, [r3]\n-\tadd.w\tr3, sp, #1024\t@ 0x400\n-\tvfma.f64\td17, d28, d20\n-\tvfma.f64\td8, d10, d29\n-\tvstr\td0, [sp, #448]\t@ 0x1c0\n-\tvmov.f64\td28, #8\t@ 0x40400000 3.0\n-\tvldr\td0, [pc, #200]\t@ 7a98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1350>\n-\tvldr\td20, [pc, #204]\t@ 7aa0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1358>\n-\tvldr\td29, [pc, #112]\t@ 7a48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1300>\n-\tvdiv.f64\td22, d20, d19\n-\tvldr\td20, [pc, #200]\t@ 7aa8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1360>\n-\tvmul.f64\td17, d17, d18\n-\tvmov.f64\td18, d17\n-\tvfma.f64\td18, d21, d13\n-\tvldr\td13, [sp, #744]\t@ 0x2e8\n-\tvldr\td21, [sp, #256]\t@ 0x100\n-\tvmul.f64\td17, d13, d8\n-\tvmul.f64\td14, d13, d14\n-\tvldr\td13, [sp, #32]\n-\tvadd.f64\td21, d21, d21\n-\tvmov.f64\td8, d10\n-\tvsqrt.f64\td13, d13\n-\tvmul.f64\td14, d14, d10\n-\tvstr\td18, [sp]\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td10, [sp, #192]\t@ 0xc0\n-\tvnmul.f64\td21, d11, d21\n-\tvmul.f64\td23, d23, d18\n-\tvmul.f64\td20, d10, d20\n-\tvldr\td10, [sp, #48]\t@ 0x30\n-\tvstr\td23, [sp, #472]\t@ 0x1d8\n-\tb.n\t7b78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1430>\n+\tvstr\td3, [sp, #472]\t@ 0x1d8\n+\tvldr\td6, [sp, #344]\t@ 0x158\n+\tvldr\td4, [sp, #128]\t@ 0x80\n+\tvldr\td1, [sp, #544]\t@ 0x220\n+\tvstr\td14, [sp, #40]\t@ 0x28\n+\tvmul.f64\td4, d6, d4\n+\tb.n\t7ed8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1400>\n \tnop\n \tnop.w\n+\t.word\t0x00000000\n+\t.word\t0x3fb00000\n+\t.word\t0xfc2dd756\n+\t.word\t0x3ff8ac8b\n \t.word\t0xc9be45de\n \t.word\t0x4033bd3c\n-\t.word\t0x97d453e4\n-\t.word\t0x3fef7e15\n-\t.word\t0x91b4ef6b\n-\t.word\t0x3ffc5bf8\n-\t.word\t0xe03dc2d9\n-\t.word\t0x4019e6cb\n-\t.word\t0x25676f30\n-\t.word\t0x4001b6ec\n+\t.word\t0xc9be45de\n+\t.word\t0x4013bd3c\n+\t.word\t0x2e9d68cd\n+\t.word\t0x403d9bdb\n \t.word\t0x9f31cd78\n \t.word\t0x3f880d70\n \t.word\t0xdc766309\n \t.word\t0xc007ca11\n+\t.word\t0x25676f30\n+\t.word\t0x4001b6ec\n \t.word\t0x77bd9591\n \t.word\t0xbfb3c464\n \t.word\t0xb39c605a\n \t.word\t0xbfdda696\n \t.word\t0x86c894c8\n \t.word\t0x40d95960\n \t.word\t0xc277df34\n \t.word\t0x40386301\n-\t.word\t0xc9be45de\n-\t.word\t0x4013bd3c\n+\t.word\t0xe03dc2d9\n+\t.word\t0x4019e6cb\n \t.word\t0xdc766309\n \t.word\t0xbfc7ca11\n \t.word\t0x4c417c95\n \t.word\t0x3ebc6546\n \t.word\t0xfff7dd55\n \t.word\t0x3f4a0ae2\n \t.word\t0x3315d702\n \t.word\t0x3fee7bc2\n \t.word\t0x416c84c0\n \t.word\t0x3fa14aca\n+\t.word\t0x91b4ef6b\n+\t.word\t0x3ffc5bf8\n \t.word\t0x55555555\n \t.word\t0x3fd55555\n \t.word\t0x54a28591\n \t.word\t0x40136d19\n \t.word\t0xc277df34\n \t.word\t0x40086301\n \t.word\t0xcebb4be1\n \t.word\t0x3eec3bf8\n-\t.word\t0x5d0fe07c\n-\t.word\t0x3f77acce\n \t.word\t0xc277df34\n \t.word\t0x3fd86301\n-\t.word\t0xac2b2500\n-\t.word\t0x3f808541\n+\t.word\t0x5d0fe07c\n+\t.word\t0x3f77acce\n \t.word\t0x63e07ae3\n \t.word\t0x3f62b04b\n \t.word\t0x97d453e4\n \t.word\t0x3fff7e15\n-\t.word\t0x0758138d\n-\t.word\t0x3fecd0f6\n+\t.word\t0x97d453e4\n+\t.word\t0x3fef7e15\n+\t.word\t0xac2b2500\n+\t.word\t0x3f808541\n \t.word\t0x2c5f92c6\n \t.word\t0x3fa2c5f9\n+\t.word\t0x2c4fea23\n+\t.word\t0x3fd04201\n \t.word\t0x3c998ed0\n \t.word\t0x4006107d\n \t.word\t0xaa145d16\n \t.word\t0x3ff3edc9\n-\t.word\t0x2c4fea23\n-\t.word\t0x3fd04201\n+\tvldr\td6, [sp, #200]\t@ 0xc8\n+\tvldr\td3, [sp, #32]\n+\tvldr\td12, [sp, #352]\t@ 0x160\n+\tvldr\td0, [sp, #664]\t@ 0x298\n+\tvstr\td4, [sp, #24]\n+\tvldr\td4, [r3]\n+\tadd.w\tr3, sp, #1168\t@ 0x490\n+\tvsub.f64\td6, d4, d6\n+\tvldr\td4, [sp, #536]\t@ 0x218\n+\tvldr\td5, [r3]\n+\tadd.w\tr3, sp, #1136\t@ 0x470\n+\tvsub.f64\td4, d4, d1\n+\tvldr\td1, [sp, #856]\t@ 0x358\n+\tvstr\td4, [sp, #848]\t@ 0x350\n+\tvldr\td4, [sp, #56]\t@ 0x38\n+\tvmul.f64\td14, d4, d5\n+\tvldr\td5, [pc, #-236]\t@ 7e30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1358>\n+\tvstr\td14, [sp, #496]\t@ 0x1f0\n+\tvldr\td14, [r3]\n+\tadd.w\tr3, sp, #1112\t@ 0x458\n+\tvmul.f64\td5, d14, d5\n+\tvnmls.f64\td7, d5, d3\n+\tvldr\td5, [sp, #184]\t@ 0xb8\n+\tvmla.f64\td2, d7, d1\n+\tvmul.f64\td7, d6, d12\n+\tvadd.f64\td6, d5, d5\n+\tvldr\td1, [sp, #232]\t@ 0xe8\n+\tvmul.f64\td6, d6, d3\n+\tvmov.f64\td3, #2\t@ 0x40100000 2.250\n+\tvmul.f64\td5, d14, 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<__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13a8>\n-\tvfnms.f64\td10, d1, d15\n-\tvmul.f64\td21, d7, d21\n-\tvldr\td7, [sp, #664]\t@ 0x298\n-\tvdiv.f64\td7, d21, d7\n-\tvldr\td21, [pc, #-476]\t@ 7af8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13b0>\n-\tvmul.f64\td21, d14, d21\n-\tvldr\td14, [sp, #576]\t@ 0x240\n-\tvstr\td7, [sp, #72]\t@ 0x48\n-\tvldr\td7, [sp, #968]\t@ 0x3c8\n-\tvfms.f64\td19, d7, d21\n-\tvldr\td21, [pc, #-492]\t@ 7b00 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13b8>\n-\tvldr\td7, [r3]\n-\tadd.w\tr3, sp, #1040\t@ 0x410\n-\tvmul.f64\td31, d14, d21\n-\tvldr\td14, [sp, #480]\t@ 0x1e0\n-\tvmul.f64\td31, d31, d14\n-\tvldr\td14, [sp, #736]\t@ 0x2e0\n-\tvfms.f64\td9, d14, d31\n-\tvldr\td31, [sp, #640]\t@ 0x280\n-\tvldr\td14, [sp, #552]\t@ 0x228\n-\tvmul.f64\td21, d7, d31\n-\tvmul.f64\td7, d7, d26\n-\tvfma.f64\td9, d31, d30\n-\tvldr\td31, [sp, #456]\t@ 0x1c8\n-\tvnmul.f64\td7, d31, d7\n-\tvldr\td31, [r3]\n-\tvfms.f64\td17, d14, d21\n-\tvldr\td28, [sp, #288]\t@ 0x120\n-\tvldr\td14, [sp, #592]\t@ 0x250\n-\tadd.w\tr3, sp, #1096\t@ 0x448\n-\tvfma.f64\td7, d31, d26\n-\tvmul.f64\td26, d6, d18\n-\tvldr\td15, [sp, #488]\t@ 0x1e8\n-\tvldr\td31, [sp, #496]\t@ 0x1f0\n-\tvmul.f64\td22, d14, d22\n-\tvldr\td24, [sp, #720]\t@ 0x2d0\n-\tvmov.f64\td14, d19\n-\tvmul.f64\td26, d26, d28\n-\tvldr\td19, [sp, #864]\t@ 0x360\n-\tvnmul.f64\td31, d17, d31\n-\tvldr\td17, [sp, #648]\t@ 0x288\n-\tvfms.f64\td14, d19, d22\n-\tvmul.f64\td22, d28, d18\n-\tvmul.f64\td26, d26, d15\n-\tvmul.f64\td28, d24, d18\n-\tvldr\td18, [sp, #96]\t@ 0x60\n-\tvmov.f64\td19, #4\t@ 0x40200000 2.5\n-\tvmul.f64\td22, d22, d15\n-\tvfnms.f64\td18, d17, d26\n-\tvstr\td28, [sp, #456]\t@ 0x1c8\n-\tvldr\td28, [r3]\n-\tadd.w\tr3, sp, #1112\t@ 0x458\n-\tvldr\td26, [sp, #40]\t@ 0x28\n-\tvmov.f64\td21, d14\n-\tvmov.f64\td14, d6\n-\tvldr\td6, [r3]\n-\tadd.w\tr3, sp, #1064\t@ 0x428\n-\tvldr\td17, [pc, #-672]\t@ 7b08 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13c0>\n-\tvmov.f64\td29, d18\n-\tvmul.f64\td18, d22, d7\n-\tvldr\td22, [pc, #-676]\t@ 7b10 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13c8>\n-\tvldr\td7, [sp, #896]\t@ 0x380\n-\tvmul.f64\td22, d25, d22\n-\tvstr\td18, [sp, #480]\t@ 0x1e0\n-\tvldr\td18, [sp, #176]\t@ 0xb0\n-\tvldr\td25, [sp, #624]\t@ 0x270\n-\tvfms.f64\td21, d28, d22\n-\tvmul.f64\td18, d18, d19\n-\tvldr\td22, [pc, #-700]\t@ 7b18 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13d0>\n-\tvldr\td28, [sp, #128]\t@ 0x80\n-\tvfms.f64\td21, d7, d23\n-\tvldr\td7, [sp, #952]\t@ 0x3b8\n-\tvmul.f64\td18, d18, d24\n-\tvfms.f64\td21, d7, d20\n-\tvldr\td7, [sp, #392]\t@ 0x188\n-\tvmov.f64\td20, d21\n-\tvldr\td21, [sp, #376]\t@ 0x178\n-\tvfms.f64\td20, d7, d27\n-\tvldr\td7, [sp]\n-\tvldr\td27, [sp, #416]\t@ 0x1a0\n-\tvmov.f64\td30, d20\n-\tvmul.f64\td20, d24, d26\n-\tvldr\td26, [sp, #608]\t@ 0x260\n-\tvmul.f64\td22, d20, d22\n-\tvfma.f64\td22, d18, d28\n-\tvldr\td18, [pc, #-760]\t@ 7b20 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13d8>\n-\tvmul.f64\td20, d20, d18\n-\tvmul.f64\td18, d6, d18\n-\tvmul.f64\td15, d18, d21\n-\tvmul.f64\td18, d12, d25\n-\tvfma.f64\td18, d26, d7\n-\tvmul.f64\td21, d27, d26\n-\tvldr\td27, [sp, #616]\t@ 0x268\n-\tvfma.f64\td21, d11, d25\n-\tvldr\td7, [sp, #600]\t@ 0x258\n-\tvmov.f64\td26, #120\t@ 0x3fc00000 1.5\n-\tvldr\td25, [sp, #152]\t@ 0x98\n-\tvstr\td15, [sp, #192]\t@ 0xc0\n-\tvfma.f64\td31, d27, d18\n-\tvldr\td18, [sp, #688]\t@ 0x2b0\n-\tvmul.f64\td21, d21, d27\n-\tvldr\td27, [sp, #496]\t@ 0x1f0\n-\tvdiv.f64\td18, d17, d18\n-\tvmul.f64\td17, d11, d7\n-\tvstr\td18, [sp, #96]\t@ 0x60\n-\tvmov.f64\td18, #12\t@ 0x40600000 3.5\n-\tvmul.f64\td17, d17, d18\n-\tvnmul.f64\td23, d18, d24\n-\tvfms.f64\td21, d25, d17\n-\tvldr\td17, [pc, #-848]\t@ 7b28 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13e0>\n-\tvmul.f64\td17, d5, d17\n-\tvmul.f64\td5, d24, d26\n-\tvfms.f64\td21, d27, d9\n-\tvldr\td9, [sp, #656]\t@ 0x290\n-\tvmov.f64\td27, d22\n-\tvdiv.f64\td9, d17, d9\n-\tvstr\td9, [sp, #24]\n-\tvldr\td9, [sp, #136]\t@ 0x88\n-\tvldr\td25, [sp, #208]\t@ 0xd0\n-\tvfma.f64\td27, d9, d23\n-\tvldr\td9, [pc, #-884]\t@ 7b30 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13e8>\n-\tvmul.f64\td22, d24, d25\n-\tvldr\td25, [sp, #216]\t@ 0xd8\n-\tvldr\td23, [sp, #304]\t@ 0x130\n-\tvmov.f64\td17, d27\n-\tvldr\td27, [sp, #104]\t@ 0x68\n-\tvfms.f64\td17, d5, d15\n-\tvldr\td15, [sp, #464]\t@ 0x1d0\n-\tvfma.f64\td23, d27, d9\n-\tvmov.f64\td27, d16\n-\tvfma.f64\td27, d22, d25\n-\tvldr\td22, [pc, #-920]\t@ 7b38 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13f0>\n-\tvldr\td25, [sp, #320]\t@ 0x140\n-\tvnmul.f64\td9, d9, d16\n-\tvstr\td23, [sp, #104]\t@ 0x68\n-\tvmov.f64\td28, d27\n-\tvldr\td27, [sp, #280]\t@ 0x118\n-\tvmul.f64\td22, d27, d22\n-\tvldr\td27, [r3]\n-\tadd.w\tr3, sp, #1032\t@ 0x408\n-\tvmul.f64\td14, d14, d22\n-\tvmul.f64\td29, d29, d22\n-\tvldr\td22, [sp, #424]\t@ 0x1a8\n-\tvstr\td14, [sp, #312]\t@ 0x138\n-\tvmov.f64\td14, d21\n-\tvldr\td21, [pc, #-968]\t@ 7b40 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x13f8>\n-\tvfma.f64\td14, d25, d29\n-\tvldr\td25, [pc, #-968]\t@ 7b48 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1400>\n-\tvldr\td29, [pc, #-964]\t@ 7b50 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1408>\n-\tvfma.f64\td23, d27, d21\n-\tvldr\td27, [pc, #-964]\t@ 7b58 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1410>\n-\tvmul.f64\td25, d15, d25\n-\tvmov.f64\td15, #16\t@ 0x40800000 4.0\n-\tvldr\td21, [pc, #-968]\t@ 7b60 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1418>\n-\tvmul.f64\td27, d16, d27\n-\tvfms.f64\td23, d8, d15\n-\tvneg.f64\td15, d8\n-\tvmul.f64\td25, d25, d22\n-\tvldr\td22, [sp, #16]\n-\tvstr\td15, [sp, #288]\t@ 0x120\n-\tvldr\td15, [sp, #672]\t@ 0x2a0\n-\tvfma.f64\td27, d24, d15\n-\tvmov.f64\td15, d11\n-\tvfms.f64\td15, d22, d21\n-\tvldr\td22, [pc, #-1004]\t@ 7b68 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1420>\n-\tvmov.f64\td21, d30\n-\tvldr\td30, [sp, #376]\t@ 0x178\n-\tvmul.f64\td22, d10, d22\n-\tvfma.f64\td22, d17, d29\n-\tvldr\td17, [pc, #-1016]\t@ 7b70 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1428>\n-\tvmov.f64\td8, d15\n-\tvldr\td15, [sp, #920]\t@ 0x398\n-\tvmul.f64\td15, d15, d17\n-\tvldr\td17, [pc, #1016]\t@ 8370 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c28>\n-\tvfma.f64\td21, d28, d17\n-\tvmov.f64\td17, #98\t@ 0x3f100000 0.5625000\n-\tvstr\td15, [sp, #280]\t@ 0x118\n-\tvmul.f64\td17, d6, d17\n-\tvfma.f64\td21, d27, d15\n-\tvmul.f64\td15, d17, d30\n-\tvmul.f64\td17, d24, d19\n-\tvldr\td30, [sp, #72]\t@ 0x48\n-\tvfma.f64\td20, d17, d30\n-\tvmul.f64\td17, d25, d18\n-\tvmul.f64\td18, d12, d18\n-\tvldr\td30, [sp, #152]\t@ 0x98\n-\tvstr\td15, [sp, #184]\t@ 0xb8\n-\tvfnms.f64\td20, d5, d15\n-\tvldr\td15, [pc, #964]\t@ 8378 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c30>\n-\tvmul.f64\td17, d17, d11\n-\tvmul.f64\td25, d25, d18\n-\tvmul.f64\td20, d20, d29\n-\tvstr\td20, [sp, #464]\t@ 0x1d0\n-\tvmul.f64\td20, d7, d18\n-\tvfms.f64\td31, d30, d20\n-\tvldr\td30, [sp, #784]\t@ 0x310\n-\tvldr\td20, [sp, #408]\t@ 0x198\n-\tvmul.f64\td15, d30, d15\n-\tvldr\td30, [sp, #776]\t@ 0x308\n-\tvmul.f64\td14, d15, d14\n-\tvstr\td31, [sp, #392]\t@ 0x188\n-\tvldr\td31, [pc, #920]\t@ 8380 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c38>\n-\tvmul.f64\td31, d16, d31\n-\tvfma.f64\td31, d24, d23\n-\tvldr\td23, [pc, #916]\t@ 8388 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c40>\n-\tvmul.f64\td23, d30, d23\n-\tvfma.f64\td14, d23, d17\n-\tvldr\td17, [pc, #912]\t@ 8390 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c48>\n-\tvmul.f64\td30, d25, d23\n-\tvmul.f64\td17, d20, d17\n-\tvldr\td20, [pc, #908]\t@ 8398 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c50>\n-\tvstr\td30, [sp, #488]\t@ 0x1e8\n-\tvmov.f64\td30, #114\t@ 0x3f900000 1.125\n-\tvfma.f64\td21, d22, d17\n-\tvldr\td22, [sp, #336]\t@ 0x150\n-\tvmul.f64\td16, d16, d30\n-\tvstr\td17, [sp, #152]\t@ 0x98\n-\tvldr\td17, [sp, #144]\t@ 0x90\n-\tvfma.f64\td16, d22, d24\n-\tvldr\td22, [sp, #632]\t@ 0x278\n-\tvmul.f64\td20, d17, d20\n-\tvmul.f64\td6, d4, d22\n-\tvstr\td16, [sp, #424]\t@ 0x1a8\n-\tvldr\td25, [sp, #248]\t@ 0xf8\n-\tvldr\td16, [sp, #200]\t@ 0xc8\n-\tvldr\td17, [sp, #440]\t@ 0x1b8\n-\tvmul.f64\td29, d25, d22\n-\tvldr\td22, [sp, #856]\t@ 0x358\n-\tvmul.f64\td28, d25, d2\n-\tvmul.f64\td25, d4, d2\n-\tvmul.f64\td27, d16, d22\n-\tvmul.f64\td23, d22, d20\n-\tvldr\td22, [sp, #832]\t@ 0x340\n-\tvmul.f64\td20, d20, d26\n-\tvfma.f64\td23, d22, d0\n-\tvmul.f64\td22, d16, d2\n-\tvldr\td2, [sp, #40]\t@ 0x28\n-\tvldr\td16, [pc, #808]\t@ 83a0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c58>\n-\tvldr\td0, [sp, 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d29\n-\tvldr\td7, [sp]\n-\tadd.w\tr3, sp, #1144\t@ 0x478\n-\tvfms.f64\td21, d7, d29\n-\tvadd.f64\td29, d23, d26\n-\tvfma.f64\td20, d8, d26\n-\tvldr\td26, [pc, #668]\t@ 83b0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c68>\n-\tvstr\td21, [sp, #416]\t@ 0x1a0\n-\tvstr\td20, [sp, #408]\t@ 0x198\n-\tvldr\td20, [sp, #512]\t@ 0x200\n-\tvldr\td21, [sp, #200]\t@ 0xc8\n-\tvmul.f64\td7, d20, d8\n-\tvmul.f64\td20, d11, d27\n-\tvldr\td8, [sp, #16]\n-\tvfma.f64\td16, d20, d31\n-\tvldr\td20, [sp, #368]\t@ 0x170\n-\tvfnms.f64\td20, d8, d31\n-\tvldr\td8, [sp, #456]\t@ 0x1c8\n-\tvfma.f64\td20, d2, d6\n-\tvfma.f64\td9, d24, d20\n-\tvldr\td24, [pc, #620]\t@ 83b8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c70>\n-\tvmul.f64\td20, d12, d6\n-\tvldr\td6, [sp, #96]\t@ 0x60\n-\tvmul.f64\td24, d10, d24\n-\tvfma.f64\td24, d6, d8\n-\tvldr\td6, [sp, #328]\t@ 0x148\n-\tvmul.f64\td6, d11, d6\n-\tvstr\td9, [sp, #376]\t@ 0x178\n-\tvldr\td9, [pc, #596]\t@ 83c0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c78>\n-\tvmul.f64\td9, d21, d9\n-\tvmul.f64\td21, d30, d8\n-\tvldr\td8, [sp, #24]\n-\tvfms.f64\td21, d5, d8\n-\tvldr\td5, [pc, #584]\t@ 83c8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c80>\n-\tvmul.f64\td21, d21, d26\n-\tvmul.f64\td26, d7, d25\n-\tvmul.f64\td26, d26, d19\n-\tvmov.f64\td8, d26\n-\tvldr\td26, [sp, #448]\t@ 0x1c0\n-\tvfma.f64\td8, d6, d31\n-\tvldr\td31, [sp, #144]\t@ 0x90\n-\tvmul.f64\td6, d7, d28\n-\tvmul.f64\td7, d7, d19\n-\tvmul.f64\td6, d6, d19\n-\tvmul.f64\td19, d12, d19\n-\tvstr\td8, [sp, #200]\t@ 0xc8\n-\tvldr\td8, [pc, #540]\t@ 83d0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c88>\n-\tvmul.f64\td8, d31, d8\n-\tvmul.f64\td16, d16, d8\n-\tvfma.f64\td16, d4, d26\n-\tvstr\td16, [sp, #440]\t@ 0x1b8\n-\tvldr\td16, [pc, #528]\t@ 83d8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1c90>\n-\tvldr\td26, [sp, #464]\t@ 0x1d0\n-\tvldr\td31, [sp, #168]\t@ 0xa8\n-\tvfms.f64\td26, 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83f0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1ca8>\n-\tvfms.f64\td16, d13, d11\n-\tvldr\td11, [sp, #200]\t@ 0xc8\n-\tvmov.f64\td6, d4\n-\tvldr\td4, [sp, #144]\t@ 0x90\n-\tvfma.f64\td6, d12, d29\n-\tvldr\td29, [sp, #504]\t@ 0x1f8\n-\tvmul.f64\td26, d29, d26\n-\tvldr\td29, [pc, #404]\t@ 83f8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cb0>\n-\tvmul.f64\td29, d4, d29\n-\tvldr\td4, [sp, #376]\t@ 0x178\n-\tvfma.f64\td28, d11, d26\n-\tvldr\td11, [sp, #536]\t@ 0x218\n-\tvfma.f64\td29, d7, d22\n-\tvfma.f64\td28, d11, d14\n-\tvldr\td14, [sp, #976]\t@ 0x3d0\n-\tvldr\td11, [pc, #380]\t@ 8400 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cb8>\n-\tvmul.f64\td11, d14, d11\n-\tvfma.f64\td16, d4, d11\n-\tvldr\td4, [sp, #344]\t@ 0x158\n-\tvfma.f64\td16, d4, d29\n-\tvldr\td29, [sp, #160]\t@ 0xa0\n-\tvldr\td4, [sp, #168]\t@ 0xa8\n-\tvneg.f64\td14, d29\n-\tvfms.f64\td16, d29, d31\n-\tvldr\td29, [sp, #312]\t@ 0x138\n-\tvfma.f64\td16, d4, d24\n-\tvldr\td24, [pc, #344]\t@ 8408 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cc0>\n-\tvldr\td4, [sp, #88]\t@ 0x58\n-\tvfma.f64\td21, d10, d24\n-\tvldr\td24, [pc, #340]\t@ 8410 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cc8>\n-\tvmul.f64\td21, d21, d24\n-\tvldr\td24, [pc, #340]\t@ 8418 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cd0>\n-\tvfma.f64\td21, d28, d24\n-\tvldr\td24, [sp, #432]\t@ 0x1b0\n-\tvldr\td28, [sp, #320]\t@ 0x140\n-\tvfma.f64\td16, d4, d21\n-\tvmov.f64\td21, #104\t@ 0x3f400000 0.750\n-\tvldr\td4, [sp, #80]\t@ 0x50\n-\tvmul.f64\td21, d24, d21\n-\tvldr\td24, [sp, #480]\t@ 0x1e0\n-\tvfma.f64\td24, d4, d21\n-\tvldr\td21, [sp, #392]\t@ 0x188\n-\tvmul.f64\td24, d29, d24\n-\tvfma.f64\td21, d28, d24\n-\tvldr\td24, [sp, #488]\t@ 0x1e8\n-\tvfma.f64\td24, d15, d21\n-\tvldr\td21, [sp, #544]\t@ 0x220\n-\tvmov.f64\td15, d6\n-\tvfma.f64\td15, d21, d24\n-\tvldr\td21, [sp, #536]\t@ 0x218\n-\tvnmul.f64\td9, d24, d9\n-\tvnmul.f64\td10, d24, d21\n-\tvldr\td24, [sp, #64]\t@ 0x40\n-\tvldr\td21, [pc, #260]\t@ 8420 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cd8>\n-\tvmul.f64\td21, d24, d21\n-\tvldr\td24, [sp, #680]\t@ 0x2a8\n-\tvldr\td6, [sp, #328]\t@ 0x148\n-\tvldr\td7, [sp]\n-\tvldr\td4, [r3]\n-\tvmul.f64\td21, d21, d16\n-\tvldr\td16, [pc, #240]\t@ 8428 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1ce0>\n-\tvmul.f64\td16, d24, d16\n-\tvldr\td24, [sp, #400]\t@ 0x190\n-\tvfma.f64\td21, d24, d16\n-\tvadd.f64\td24, d12, d12\n-\tvldr\td16, [r6]\n-\tvfma.f64\td0, d27, d24\n-\tvfma.f64\td25, d6, d24\n-\tvmul.f64\td8, d8, d0\n-\tvldr\td0, [sp, #448]\t@ 0x1c0\n-\tvfma.f64\td8, d7, d0\n-\tvfma.f64\td8, d26, d25\n-\tvmov.f64\td25, #80\t@ 0x3e800000 0.250\n-\tb.n\t8460 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1d18>\n-\tnop\n-\tnop.w\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n-\t.word\t0x11111111\n-\t.word\t0x3ff11111\n+\t.word\t0x44569e2e\n+\t.word\t0x3fce9274\n \t.word\t0x47c07d65\n \t.word\t0x40286dc6\n-\t.word\t0x50429b6d\n-\t.word\t0x3fe20dd7\n+\t.word\t0x11111111\n+\t.word\t0x3ff11111\n \t.word\t0x03ebac6c\n \t.word\t0xbfb0a5f6\n \t.word\t0xb39c605a\n \t.word\t0xbfada696\n \t.word\t0x925fea34\n \t.word\t0x3f8134f5\n \t.word\t0x2c4fea23\n \t.word\t0x3ff04201\n-\t.word\t0x91b4ef6b\n-\t.word\t0x3ffc5bf8\n \t.word\t0x3bad40f9\n \t.word\t0x3fe8314e\n \t.word\t0x0af83437\n \t.word\t0xbfaa99f1\n+\t.word\t0xfd70288b\n+\t.word\t0x400da7c1\n \t.word\t0x8d9aab4b\n \t.word\t0xbff20d34\n \t.word\t0x77bd9591\n \t.word\t0xbfa3c464\n-\t.word\t0xfd70288b\n-\t.word\t0x400da7c1\n \t.word\t0xfa48b0f4\n \t.word\t0xbfb8f051\n \t.word\t0x61f2a45a\n \t.word\t0x3ff73e68\n \t.word\t0xa6db20a2\n \t.word\t0xbfc0a036\n-\t.word\t0x26a72f3e\n-\t.word\t0xbfe2341c\n \t.word\t0xbcf04c7f\n \t.word\t0x3e9d59da\n+\t.word\t0x26a72f3e\n+\t.word\t0xbfe2341c\n+\t.word\t0x91b4ef6b\n+\t.word\t0x3ffc5bf8\n \t.word\t0x091f4276\n \t.word\t0x3ffac8f9\n \t.word\t0xdb7a9450\n \t.word\t0xbf5b1c19\n \t.word\t0x5e247885\n \t.word\t0x3f55ce9e\n-\t.word\t0xfe791dd3\n-\t.word\t0xbfe7a245\n \t.word\t0xbda12f68\n \t.word\t0x3ff2f684\n+\t.word\t0xfe791dd3\n+\t.word\t0xbfe7a245\n \t.word\t0xdebd9018\n \t.word\t0x4073c1fd\n \t.word\t0x0aa64c30\n \t.word\t0x40102546\n \t.word\t0xf67f4dbe\n \t.word\t0x40142523\n \t.word\t0x949a5658\n \t.word\t0x3ff26e82\n \t.word\t0xca57a787\n \t.word\t0x4010c432\n-\t.word\t0xaa145d16\n-\t.word\t0x3ff3edc9\n-\tvfma.f64\td16, d21, d25\n-\tvstr\td16, [r6]\n-\tvldr\td16, [pc, #-60]\t@ 8430 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1ce8>\n-\tvcmpe.f64\td3, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tbmi.w\t8722 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1fda>\n-\tvldr\td26, [sp, #32]\n-\tvldr\td25, [pc, #-72]\t@ 8438 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cf0>\n-\tvldr\td16, [pc, #-60]\t@ 8448 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1d00>\n-\tvldr\td21, [pc, #-72]\t@ 8440 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1cf8>\n-\tvadd.f64\td25, d26, d25\n-\tvadd.f64\td21, d26, d21\n-\tvfma.f64\td16, d26, d25\n-\tvldr\td25, [sp, #112]\t@ 0x70\n-\tvmul.f64\td16, d25, d16\n-\tvldr\td25, [pc, #-80]\t@ 8450 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1d08>\n-\tvfma.f64\td25, d26, d21\n-\tvdiv.f64\td21, d16, d25\n-\tvldr\td16, [sp, #112]\t@ 0x70\n-\tvmul.f64\td22, d22, d23\n-\tvldr\td23, [sp, #8]\n-\tvldr\td25, [sp, #232]\t@ 0xe8\n-\tvsub.f64\td21, d21, d16\n-\tvldr\td16, [sp, #384]\t@ 0x180\n-\tvldr\td28, [sp]\n-\tvldr\td29, [pc, #-112]\t@ 8458 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1d10>\n-\tvsub.f64\td27, d16, d23\n-\tvldr\td16, [sp, #40]\t@ 0x28\n-\tvmul.f64\td21, d21, d4\n-\tldr.w\tr2, [pc, #1096]\t@ 8920 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21d8>\n-\tldr.w\tr3, [pc, #1096]\t@ 8924 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21dc>\n-\tvmul.f64\td26, d12, d16\n-\tvldr\td16, [sp, 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d14, d9\n-\tvmul.f64\td19, d20, d19\n-\tvldr\td20, [pc, #716]\t@ 8900 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21b8>\n-\tvfma.f64\td16, d22, d15\n-\tvldr\td22, [pc, #716]\t@ 8908 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21c0>\n-\tvfma.f64\td8, d18, d22\n-\tvldr\td18, [pc, #716]\t@ 8910 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21c8>\n-\tvmov.f64\td22, #16\t@ 0x40800000 4.0\n-\tvmul.f64\td18, d12, d18\n-\tvmul.f64\td22, d12, d22\n-\tvnmul.f64\td18, d25, d18\n-\tvldr\td25, [sp, #120]\t@ 0x78\n-\tvsub.f64\td8, d8, d10\n-\tvnmul.f64\td23, d25, d23\n-\tvldr\td25, [sp, #352]\t@ 0x160\n-\tvfma.f64\td16, d19, d8\n-\tvfma.f64\td23, d25, d12\n-\tvldr\td25, [sp, #104]\t@ 0x68\n-\tvldr\td19, [sp, #64]\t@ 0x40\n-\tvldr\td30, [r4]\n-\tvfma.f64\td18, d25, d12\n-\tvldr\td25, [pc, #664]\t@ 8918 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x21d0>\n-\tvfma.f64\td23, d21, d24\n-\tvldr\td24, [sp, #288]\t@ 0x120\n-\tvfma.f64\td16, d28, d20\n-\tvmul.f64\td25, d19, d25\n-\tvldr\td19, [sp, #280]\t@ 0x118\n-\tvfma.f64\td18, d24, d22\n-\tvfma.f64\td18, d21, d26\n-\tvfma.f64\td16, d23, d19\n-\tvldr\td19, [sp, #248]\t@ 0xf8\n-\tvfma.f64\td16, d18, d19\n-\tvldr\td19, [sp, #336]\t@ 0x150\n-\tvmov.f64\td18, #114\t@ 0x3f900000 1.125\n-\tvnmul.f64\td18, d18, d21\n-\tvfma.f64\td18, d19, d27\n-\tvfma.f64\td16, d18, d13\n-\tvfma.f64\td16, d17, d11\n-\tvfma.f64\td30, d16, d25\n-\tvstr\td30, [r4]\n+\tvmul.f64\td5, d8, d7\n+\tvldr\td7, [sp, #288]\t@ 0x120\n+\tvmov.f64\td14, d3\n+\tvmul.f64\td6, d7, d12\n+\tvldr\td7, [sp, #112]\t@ 0x70\n+\tvmul.f64\td2, d7, d12\n+\tvldr\td7, [sp, #352]\t@ 0x160\n+\tvldr\td12, [sp, #384]\t@ 0x180\n+\tvmul.f64\td7, d8, d7\n+\tvnmls.f64\td7, d4, d0\n+\tvldr\td4, [sp, #408]\t@ 0x198\n+\tvldr\td0, [sp, #104]\t@ 0x68\n+\tvmul.f64\td4, d4, d10\n+\tvmls.f64\td7, d4, d0\n+\tvldr\td4, [sp, #120]\t@ 0x78\n+\tvldr\td0, [sp, #64]\t@ 0x40\n+\tvmul.f64\td4, d4, d12\n+\tvmls.f64\td7, d4, d0\n+\tvldr\td4, [sp, #360]\t@ 0x168\n+\tvldr\td0, [sp, #304]\t@ 0x130\n+\tvmul.f64\td4, d8, d4\n+\tvmla.f64\td7, d4, d0\n+\tvldr\td4, [sp, #320]\t@ 0x140\n+\tvldr\td0, [sp, #240]\t@ 0xf0\n+\tvmul.f64\td4, d8, d4\n+\tvmla.f64\td14, d4, d0\n+\tvldr\td4, [sp, #560]\t@ 0x230\n+\tvldr\td0, [sp, #256]\t@ 0x100\n+\tvmul.f64\td4, d4, d8\n+\tvnmls.f64\td4, d10, d0\n+\tvldr\td0, [sp, #56]\t@ 0x38\n+\tvldr\td10, [sp, #136]\t@ 0x88\n+\tvmls.f64\td4, d0, d12\n+\tvldr\td0, [pc, #560]\t@ 8d78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22a0>\n+\tvmov.f64\td12, d4\n+\tvldr\td4, [pc, #560]\t@ 8d80 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22a8>\n+\tvmul.f64\td4, d5, d4\n+\tvmla.f64\td4, d6, d10\n+\tvldr\td6, [sp, #160]\t@ 0xa0\n+\tvldr\td10, [sp, #376]\t@ 0x178\n+\tvmls.f64\td4, d6, d10\n+\tvmul.f64\td10, d15, d0\n+\tvldr\td6, [sp, #328]\t@ 0x148\n+\tvdiv.f64\td6, d10, d6\n+\tvldr\td10, [sp, #16]\n+\tvnmls.f64\td6, d10, d15\n+\tvldr\td10, [pc, #524]\t@ 8d88 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22b0>\n+\tvmla.f64\td2, d5, d10\n+\tvmov.f64\td5, #120\t@ 0x3fc00000 1.5\n+\tvldr\td10, [sp, #184]\t@ 0xb8\n+\tvmul.f64\td5, d8, d5\n+\tvmls.f64\td4, d10, d5\n+\tvldr\td10, [sp, #232]\t@ 0xe8\n+\tvnmls.f64\td2, d10, d5\n+\tvldr\td10, [sp, #40]\t@ 0x28\n+\tvmul.f64\td5, d10, d5\n+\tvldr\td10, [pc, #492]\t@ 8d90 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22b8>\n+\tvmul.f64\td10, d6, d10\n+\tvmla.f64\td10, d4, d0\n+\tvldr\td4, [sp, #296]\t@ 0x128\n+\tvmla.f64\td7, d10, d4\n+\tvldr\td4, [pc, #480]\t@ 8d98 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22c0>\n+\tvmov.f64\td10, #96\t@ 0x3f000000 0.5\n+\tvmul.f64\td4, d6, d4\n+\tvmul.f64\td10, d8, d10\n+\tvnmls.f64\td4, d2, d0\n+\tvldr\td2, [sp, #48]\t@ 0x30\n+\tvldr\td13, [sp, #128]\t@ 0x80\n+\tvadd.f64\td7, d7, d11\n+\tvnmls.f64\td5, d2, d10\n+\tvldr\td2, [pc, #452]\t@ 8da0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22c8>\n+\tvmul.f64\td2, d6, d2\n+\tvmla.f64\td2, d13, d10\n+\tvldr\td10, [sp, #264]\t@ 0x108\n+\tvmls.f64\td7, d2, d10\n+\tvldr\td2, [pc, #440]\t@ 8da8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22d0>\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [sp, #80]\t@ 0x50\n+\tvmla.f64\td6, d5, d0\n+\tvldr\td5, [pc, #432]\t@ 8db0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22d8>\n+\tvmla.f64\td1, d4, d5\n+\tvldr\td5, [sp, #528]\t@ 0x210\n+\tvldr\td4, [sp, #88]\t@ 0x58\n+\tvmla.f64\td7, d1, d5\n+\tvldr\td5, [sp, #72]\t@ 0x48\n+\tvldr\td1, [sp, #176]\t@ 0xb0\n+\tvmls.f64\td7, d5, d11\n+\tvldr\td5, [sp, #280]\t@ 0x118\n+\tvmla.f64\td7, d5, d4\n+\tvldr\td5, [pc, #400]\t@ 8db8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22e0>\n+\tvldr\td4, [sp, #168]\t@ 0xa8\n+\tvmla.f64\td4, d6, d5\n+\tvldr\td5, [pc, #396]\t@ 8dc0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22e8>\n+\tvldr\td6, [sp, #152]\t@ 0x98\n+\tvmul.f64\td5, d8, d5\n+\tvsub.f64\td4, d4, d6\n+\tvldr\td6, [sp, #216]\t@ 0xd8\n+\tvmul.f64\td5, d5, d6\n+\tvldr\td6, [sp, #536]\t@ 0x218\n+\tvnmls.f64\td5, d6, d8\n+\tvldr\td6, [pc, #372]\t@ 8dc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22f0>\n+\tvmul.f64\td6, d8, d6\n+\tvmul.f64\td6, d6, d2\n+\tvldr\td2, [sp, #24]\n+\tvnmls.f64\td6, d2, d8\n+\tvldr\td2, [pc, #360]\t@ 8dd0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x22f8>\n+\tvmul.f64\td2, d1, d2\n+\tvmla.f64\td7, d4, d2\n+\tvmov.f64\td4, #16\t@ 0x40800000 4.0\n+\tvldr\td2, [sp, #192]\t@ 0xc0\n+\tvmul.f64\td4, d8, d4\n+\tvmls.f64\td6, d4, d2\n+\tvldr\td4, [pc, #340]\t@ 8dd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2300>\n+\tvmla.f64\td5, d3, d4\n+\tvldr\td4, [pc, #340]\t@ 8de0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2308>\n+\tvmla.f64\td7, d14, d4\n+\tvldr\td4, [sp, #272]\t@ 0x110\n+\tvmla.f64\td7, d5, d4\n+\tvldr\td5, [pc, #332]\t@ 8de8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2310>\n+\tvldr\td4, [pc, #336]\t@ 8df0 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2318>\n+\tvmla.f64\td6, d3, d5\n+\tvldr\td5, [sp, #368]\t@ 0x170\n+\tvmla.f64\td7, d6, d5\n+\tvmov.f64\td5, #114\t@ 0x3f900000 1.125\n+\tvldr\td6, [sp, #520]\t@ 0x208\n+\tvmul.f64\td5, d3, d5\n+\tvnmls.f64\td5, d9, d6\n+\tvldr\td6, [pc, #312]\t@ 8df8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2320>\n+\tvmls.f64\td12, d3, d6\n+\tvldr\td3, [sp, #144]\t@ 0x90\n+\tvldr\td6, [r4]\n+\tvmul.f64\td4, d3, d4\n+\tvldr\td3, [sp, #248]\t@ 0xf8\n+\tvmla.f64\td7, d5, d3\n+\tvldr\td5, [sp, #336]\t@ 0x150\n+\tvmla.f64\td7, d12, d5\n+\tvmla.f64\td6, d7, d4\n+\tvstr\td6, [r4]\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [sp, #1196]\t@ 0x4ac\n+\tldr.w\tr3, [sp, #1204]\t@ 0x4b4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t889c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x2154>\n-\tadd.w\tsp, sp, #1200\t@ 0x4b0\n+\tbne.n\t8d72 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x229a>\n+\tadd.w\tsp, sp, #1208\t@ 0x4b8\n \tvpop\t{d8-d15}\n \tpop\t{r4, r5, r6, pc}\n-\tvldr\td0, [sp, #32]\n-\tvstr\td31, [sp, #192]\t@ 0xc0\n-\tvstr\td2, [sp, #184]\t@ 0xb8\n-\tvstr\td21, [sp, #176]\t@ 0xb0\n+\tvldr\td12, [sp, #96]\t@ 0x60\n+\tvmov.f64\td0, d12\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvstr\td0, [sp, #96]\t@ 0x60\n-\tvldr\td0, [sp, #32]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td20, [sp, #96]\t@ 0x60\n-\tvldr\td3, [sp, #168]\t@ 0xa8\n-\tvldr\td21, [sp, #176]\t@ 0xb0\n-\tvmul.f64\td20, d20, d0\n-\tvldr\td2, [sp, #184]\t@ 0xb8\n-\tvldr\td31, [sp, #192]\t@ 0xc0\n-\tb.w\t6dd8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x690>\n-\tvldr\td0, [sp, #32]\n-\tvstr\td2, [sp, #400]\t@ 0x190\n-\tvstr\td17, [sp, #392]\t@ 0x188\n-\tvstr\td5, [sp, #376]\t@ 0x178\n-\tvstr\td23, [sp, #328]\t@ 0x148\n-\tvstr\td20, [sp, #320]\t@ 0x140\n-\tvstr\td18, [sp, #312]\t@ 0x138\n-\tvstr\td24, [sp, #304]\t@ 0x130\n-\tvstr\td19, [sp, #296]\t@ 0x128\n-\tvstr\td30, [sp, #200]\t@ 0xc8\n-\tvstr\td22, [sp, #160]\t@ 0xa0\n-\tvstr\td4, [sp, #144]\t@ 0x90\n-\tvstr\td1, [sp, #80]\t@ 0x50\n+\tvmov.f64\td8, d0\n+\tvmov.f64\td0, d12\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td8, d8, d0\n+\tb.w\t71c4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x6ec>\n+\tvldr\td13, [sp, #96]\t@ 0x60\n+\tvmov.f64\td0, d13\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvmov.f64\td16, d0\n-\tvldr\td0, [sp, #32]\n-\tvstr\td16, [sp, #32]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp, #32]\n-\tvldr\td1, [sp, #80]\t@ 0x50\n-\tvldr\td4, [sp, #144]\t@ 0x90\n-\tvmul.f64\td21, d16, d0\n-\tvldr\td22, [sp, #160]\t@ 0xa0\n-\tvldr\td30, [sp, #200]\t@ 0xc8\n-\tvldr\td19, [sp, #296]\t@ 0x128\n-\tvldr\td24, [sp, #304]\t@ 0x130\n-\tvldr\td18, [sp, #312]\t@ 0x138\n-\tvldr\td20, [sp, #320]\t@ 0x140\n-\tvldr\td23, [sp, #328]\t@ 0x148\n-\tvldr\td5, [sp, #376]\t@ 0x178\n-\tvldr\td17, [sp, #392]\t@ 0x188\n-\tvldr\td2, [sp, #400]\t@ 0x190\n-\tb.n\t84a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1d60>\n-\tadd.w\tr3, sp, #1176\t@ 0x498\n-\tvldr\td0, [sp, #32]\n-\tvstr\td18, [r3]\n-\tadd.w\tr3, sp, #1168\t@ 0x490\n-\tvstr\td31, [r3]\n-\tadd.w\tr3, sp, #1152\t@ 0x480\n-\tvstr\td4, [r3]\n-\tadd.w\tr3, sp, #1144\t@ 0x478\n-\tvstr\td17, [r3]\n-\tadd.w\tr3, sp, #1136\t@ 0x470\n-\tvstr\td7, [r3]\n-\tadd.w\tr3, sp, #1128\t@ 0x468\n-\tvstr\td29, [r3]\n-\tadd.w\tr3, sp, #1120\t@ 0x460\n-\tvstr\td21, [r3]\n-\tadd.w\tr3, sp, #1112\t@ 0x458\n-\tvstr\td6, [r3]\n-\tadd.w\tr3, sp, #1104\t@ 0x450\n-\tvstr\td5, [r3]\n-\tadd.w\tr3, sp, #1096\t@ 0x448\n-\tvstr\td28, [r3]\n-\tadd.w\tr3, sp, #1088\t@ 0x440\n-\tvstr\td1, [r3]\n-\tadd.w\tr3, sp, #1080\t@ 0x438\n-\tvstr\td2, [r3]\n-\tadd.w\tr3, sp, #1072\t@ 0x430\n-\tvstr\td3, [r3]\n+\tvmov.f64\td14, d0\n+\tvmov.f64\td0, d13\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tvmul.f64\td3, d14, d0\n+\tb.n\t8a8c <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0x1fb4>\n+\tvldr\td10, [sp, #96]\t@ 0x60\n+\tvstr\td1, [sp, #624]\t@ 0x270\n+\tvmov.f64\td0, d10\n \tbl\t0 \n R_ARM_THM_CALL\texp\n-\tvstr\td0, [sp, #416]\t@ 0x1a0\n-\tvldr\td0, [sp, #32]\n-\tbl\t3a0 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n-\tvldr\td16, [sp, #416]\t@ 0x1a0\n-\tadd.w\tr3, sp, #1160\t@ 0x488\n-\tvmul.f64\td16, d16, d0\n-\tvstr\td16, [r3]\n-\tadd.w\tr3, sp, #1072\t@ 0x430\n-\tvldr\td3, [r3]\n-\tadd.w\tr3, sp, #1080\t@ 0x438\n-\tvldr\td2, [r3]\n-\tadd.w\tr3, sp, #1088\t@ 0x440\n-\tvldr\td1, [r3]\n-\tadd.w\tr3, sp, #1096\t@ 0x448\n-\tvldr\td28, [r3]\n-\tadd.w\tr3, sp, #1104\t@ 0x450\n-\tvldr\td5, [r3]\n-\tadd.w\tr3, sp, #1112\t@ 0x458\n-\tvldr\td6, [r3]\n-\tadd.w\tr3, sp, #1120\t@ 0x460\n-\tvldr\td21, [r3]\n-\tadd.w\tr3, sp, #1128\t@ 0x468\n-\tvldr\td29, [r3]\n-\tadd.w\tr3, sp, #1136\t@ 0x470\n-\tvldr\td7, [r3]\n-\tadd.w\tr3, sp, #1144\t@ 0x478\n-\tvldr\td17, [r3]\n-\tadd.w\tr3, sp, #1152\t@ 0x480\n-\tvldr\td4, [r3]\n-\tadd.w\tr3, sp, #1168\t@ 0x490\n-\tvldr\td31, [r3]\n-\tadd.w\tr3, sp, #1176\t@ 0x498\n-\tvldr\td18, [r3]\n-\tb.w\t74a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xd60>\n+\tvmov.f64\td13, d0\n+\tvmov.f64\td0, d10\n+\tbl\t3a8 <__gridxc_xwpbe_MOD_expint_cp2k.constprop.0.isra.0>\n+\tadd.w\tr3, sp, #1184\t@ 0x4a0\n+\tvldr\td1, [sp, #624]\t@ 0x270\n+\tvmul.f64\td7, d13, d0\n+\tvstr\td7, [r3]\n+\tb.w\t7914 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0+0xe3c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x3c998ed0\n-\t.word\t0x4016107d\n+\tnop\n \t.word\t0x91b4ef6b\n \t.word\t0x3ffc5bf8\n \t.word\t0x3c998ed0\n \t.word\t0x4006107d\n+\t.word\t0xaa145d16\n+\t.word\t0x3ff3edc9\n \t.word\t0x05d583db\n \t.word\t0x40206aa4\n \t.word\t0xfd70288b\n \t.word\t0x400da7c1\n \t.word\t0x3bad40f9\n \t.word\t0x3fe8314e\n-\t.word\t0x47c07d65\n-\t.word\t0x40286dc6\n \t.word\t0x091f4276\n \t.word\t0x3ffac8f9\n \t.word\t0x26a72f3e\n \t.word\t0xbfe2341c\n-\t.word\t0xaa145d16\n-\t.word\t0x4003edc9\n+\t.word\t0x26b8069e\n+\t.word\t0xbff3e3fe\n \t.word\t0x2c4fea23\n \t.word\t0x3ff04201\n+\t.word\t0xaa145d16\n+\t.word\t0x4013edc9\n \t.word\t0x5e247885\n \t.word\t0x3f55ce9e\n+\t.word\t0xaa145d16\n+\t.word\t0x4003edc9\n \t.word\t0x2c4fea23\n \t.word\t0x3fe04201\n-\t.word\t0x26b8069e\n-\t.word\t0xbff3e3fe\n-\t.word\t0xaa145d16\n-\t.word\t0x4013edc9\n+\t.word\t0x47c07d65\n+\t.word\t0x40286dc6\n \t.word\t0xfe791dd3\n \t.word\t0xbfc7a245\n-\t.word\t0x00000438\n+\t.word\t0x3c998ed0\n+\t.word\t0x4016107d\n+\t.word\t0x0000033c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \n-00008928 <__gridxc_xwpbe_MOD_xwpbe>:\n+00008e08 <__gridxc_xwpbe_MOD_xwpbe>:\n __gridxc_xwpbe_MOD_xwpbe():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tvpush\t{d8-d15}\n \tsub.w\tip, sp, ip\n-\tstr.w\tr0, [ip, #3864]\t@ 0xf18\n-\tmov\tr6, r0\n-\tldr\tr0, [pc, #832]\t@ (8c80 <__gridxc_xwpbe_MOD_xwpbe+0x358>)\n+\tstr.w\tr0, [ip, #3880]\t@ 0xf28\n+\tmov\tr5, r0\n+\tldr\tr0, [pc, #848]\t@ (9170 <__gridxc_xwpbe_MOD_xwpbe+0x368>)\n \tmov\tr4, r2\n-\tldr\tr2, [pc, #832]\t@ (8c84 <__gridxc_xwpbe_MOD_xwpbe+0x35c>)\n+\tldr\tr2, [pc, #848]\t@ (9174 <__gridxc_xwpbe_MOD_xwpbe+0x36c>)\n+\tsub\tsp, #116\t@ 0x74\n+\tvldr\td10, [pc, #760]\t@ 9120 <__gridxc_xwpbe_MOD_xwpbe+0x318>\n \tadd\tr0, pc\n-\tvmov.i64\td15, #0x0000000000000000\n-\tsub\tsp, #132\t@ 0x84\n-\tldr.w\tr9, [r6]\n-\tmov\tfp, r3\n-\tldr\tr2, [r0, r2]\n+\tldr.w\tr9, [r5]\n+\tmov\tsl, r3\n+\tvstr\td10, [sp, #40]\t@ 0x28\n \tcmp.w\tr9, #1\n-\tldr\tr7, [sp, #232]\t@ 0xe8\n+\tvstr\td10, [sp, #72]\t@ 0x48\n+\tvstr\td10, [sp, #48]\t@ 0x30\n+\tvstr\td10, [sp, #80]\t@ 0x50\n+\tvstr\td10, [sp, #64]\t@ 0x40\n+\tvstr\td10, [sp, #56]\t@ 0x38\n+\tldr\tr2, [r0, r2]\n+\tldr\tr7, [sp, #216]\t@ 0xd8\n+\tldr\tr6, [sp, #220]\t@ 0xdc\n \tldr\tr2, [r2, #0]\n-\tstr\tr2, [sp, #124]\t@ 0x7c\n+\tstr\tr2, [sp, #108]\t@ 0x6c\n \tmov.w\tr2, #0\n-\tldr\tr5, [sp, #236]\t@ 0xec\n-\tvstr\td15, [sp, #56]\t@ 0x38\n-\tvstr\td15, [sp, #88]\t@ 0x58\n-\tvstr\td15, [sp, #64]\t@ 0x40\n-\tvstr\td15, [sp, #96]\t@ 0x60\n-\tvstr\td15, [sp, #80]\t@ 0x50\n-\tvstr\td15, [sp, #72]\t@ 0x48\n-\tbeq.w\t8c8c <__gridxc_xwpbe_MOD_xwpbe+0x364>\n+\tbeq.w\t917c <__gridxc_xwpbe_MOD_xwpbe+0x374>\n \tcmp.w\tr9, #0\n-\tble.w\t8b22 <__gridxc_xwpbe_MOD_xwpbe+0x1fa>\n+\tble.w\t9014 <__gridxc_xwpbe_MOD_xwpbe+0x20c>\n+\tmov\tr5, r6\n+\tvmov.f64\td9, d10\n \tmovs\tr6, #1\n-\tvmov.f64\td13, d15\n \tmov\tr8, r7\n-\tvldr\td9, [pc, #676]\t@ 8c38 <__gridxc_xwpbe_MOD_xwpbe+0x310>\n \tmov\tr7, r6\n-\tmov\tsl, fp\n \tmov\tr6, r9\n \tmov\tr9, r1\n-\tvldr\td8, [r4, #8]\n \tvldmia\tr9!, {d14}\n-\tvldr\td17, [r4]\n+\tvldr\td8, [r4, #8]\n+\tvldr\td6, [r4]\n+\tvcmpe.f64\td14, #0.0\n+\tvldr\td7, [r4, #16]\n \tvmul.f64\td8, d8, d8\n-\tvldr\td16, [r4, #16]\n-\tvmaxnm.f64\td14, d14, d13\n-\tvstr\td13, [sp, #88]\t@ 0x58\n-\tvfma.f64\td8, d17, d17\n-\tvstr\td13, [sp, #64]\t@ 0x40\n-\tvcmpe.f64\td14, d9\n-\tvfma.f64\td8, d16, d16\n+\tvstr\td9, [sp, #72]\t@ 0x48\n+\tvmla.f64\td8, d6, d6\n+\tvstr\td9, [sp, #48]\t@ 0x30\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmla.f64\td8, d7, d7\n+\tvldr\td7, [pc, #640]\t@ 9128 <__gridxc_xwpbe_MOD_xwpbe+0x320>\n+\tit\tlt\n+\tvmovlt.f64\td14, d9\n+\tvcmpe.f64\td14, d7\n+\tvsqrt.f64\td13, d8\n \tvmrs\tAPSR_nzcv, fpscr\n-\tvsqrt.f64\td10, d8\n-\tble.n\t8ace <__gridxc_xwpbe_MOD_xwpbe+0x1a6>\n+\tble.w\t8fc0 <__gridxc_xwpbe_MOD_xwpbe+0x1b8>\n+\tvcmpe.f64\td13, #0.0\n \tvadd.f64\td12, d14, d14\n-\tvldr\td16, [pc, #616]\t@ 8c40 <__gridxc_xwpbe_MOD_xwpbe+0x318>\n-\tvmaxnm.f64\td11, d10, d13\n-\tvmul.f64\td0, d12, d16\n+\tvldr\td7, [pc, #616]\t@ 9130 <__gridxc_xwpbe_MOD_xwpbe+0x328>\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmul.f64\td0, d12, d7\n+\tite\tlt\n+\tvmovlt.f64\td11, d9\n+\tvmovge.f64\td11, d13\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td20, #96\t@ 0x3f000000 0.5\n-\tvmov.f64\td19, #112\t@ 0x3f800000 1.0\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvldr\td3, [pc, #588]\t@ 9138 <__gridxc_xwpbe_MOD_xwpbe+0x330>\n+\tvdiv.f64\td5, d7, d14\n+\tvldr\td4, [pc, #588]\t@ 9140 <__gridxc_xwpbe_MOD_xwpbe+0x338>\n+\tvdiv.f64\td15, d6, d0\n \tvadd.f64\td11, d11, d11\n-\tvdiv.f64\td16, d20, d14\n-\tvldr\td21, [pc, #592]\t@ 8c48 <__gridxc_xwpbe_MOD_xwpbe+0x320>\n-\tvdiv.f64\td20, d19, d0\n-\tvldr\td18, [pc, #592]\t@ 8c50 <__gridxc_xwpbe_MOD_xwpbe+0x328>\n-\tvmul.f64\td16, d16, d11\n-\tvmul.f64\td16, d16, d20\n-\tvcmpe.f64\td16, d21\n-\tvmul.f64\td18, d16, d18\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t8b5e <__gridxc_xwpbe_MOD_xwpbe+0x236>\n-\tvmul.f64\td16, d18, d18\n-\tvldr\td21, [pc, #568]\t@ 8c58 <__gridxc_xwpbe_MOD_xwpbe+0x330>\n-\tvldr\td19, [pc, #572]\t@ 8c60 <__gridxc_xwpbe_MOD_xwpbe+0x338>\n-\tvfma.f64\td19, d16, d21\n-\tvmul.f64\td16, d16, d18\n-\tvdiv.f64\td14, d19, d16\n-\tvmul.f64\td18, d18, d14\n-\tvmov.f64\td19, d14\n-\tvldr\td16, [pc, #556]\t@ 8c68 <__gridxc_xwpbe_MOD_xwpbe+0x340>\n-\tvstr\td19, [sp, #112]\t@ 0x70\n-\tvstr\td13, [sp, #104]\t@ 0x68\n-\tvcmpe.f64\td18, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t8b64 <__gridxc_xwpbe_MOD_xwpbe+0x23c>\n-\tadd.w\tfp, sp, #96\t@ 0x60\n-\tadd\tr2, sp, #64\t@ 0x40\n-\tadd\tr1, sp, #88\t@ 0x58\n-\tadd\tr0, sp, #104\t@ 0x68\n-\tadd\tr3, sp, #72\t@ 0x48\n+\tvmul.f64\td5, d5, d11\n+\tvmul.f64\td5, d5, d15\n+\tvcmpe.f64\td5, d3\n+\tvmul.f64\td7, d5, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.w\t9050 <__gridxc_xwpbe_MOD_xwpbe+0x248>\n+\tvmul.f64\td4, d7, d7\n+\tvldr\td5, [pc, #556]\t@ 9148 <__gridxc_xwpbe_MOD_xwpbe+0x340>\n+\tvldr\td6, [pc, #560]\t@ 9150 <__gridxc_xwpbe_MOD_xwpbe+0x348>\n+\tvnmls.f64\td6, d4, d5\n+\tvmul.f64\td4, d4, d7\n+\tvdiv.f64\td14, d6, d4\n+\tvmul.f64\td7, d7, d14\n+\tvmov.f64\td6, d14\n+\tvldr\td5, [pc, #544]\t@ 9158 <__gridxc_xwpbe_MOD_xwpbe+0x350>\n+\tvstr\td6, [sp, #96]\t@ 0x60\n+\tvstr\td9, [sp, #88]\t@ 0x58\n+\tvcmpe.f64\td7, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.w\t9056 <__gridxc_xwpbe_MOD_xwpbe+0x24e>\n+\tadd.w\tfp, sp, #80\t@ 0x50\n+\tadd\tr2, sp, #48\t@ 0x30\n+\tadd\tr1, sp, #72\t@ 0x48\n+\tadd\tr0, sp, #88\t@ 0x58\n+\tadd\tr3, sp, #56\t@ 0x38\n \tvmov.f64\td2, d14\n-\tstr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #16]\n \tvmov.f64\td1, d11\n \tstr\tr3, [sp, #4]\n \tvmov.f64\td0, d12\n-\tadd\tr3, sp, #80\t@ 0x50\n-\tstr\tr3, [sp, #24]\n+\tadd\tr3, sp, #64\t@ 0x40\n+\tstr\tr3, [sp, #20]\n \tstr\tr3, [sp, #0]\n \tmov\tr3, fp\n-\tstrd\tr1, r2, [sp, #32]\n-\tstr\tr0, [sp, #28]\n-\tvstr\td20, [sp, #40]\t@ 0x28\n-\tbl\t1560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>\n-\tvldr\td16, [pc, #488]\t@ 8c70 <__gridxc_xwpbe_MOD_xwpbe+0x348>\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td20, [sp, #40]\t@ 0x28\n-\tvldr\td19, [sp, #104]\t@ 0x68\n-\tldrd\tr0, r1, [sp, #28]\n-\tvcmpe.f64\td20, d16\n-\tvfma.f64\td15, d19, d18\n-\tldr\tr2, [sp, #36]\t@ 0x24\n-\tvstr\td13, [sp, #104]\t@ 0x68\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvstr\td15, [sp, #56]\t@ 0x38\n-\tbpl.w\t8c16 <__gridxc_xwpbe_MOD_xwpbe+0x2ee>\n-\tldr\tr3, [sp, #20]\n+\tstrd\tr1, r2, [sp, #28]\n+\tstr\tr0, [sp, #24]\n+\tbl\t15a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldrd\tr0, r1, [sp, #24]\n+\tvstr\td9, [sp, #88]\t@ 0x58\n+\tvmla.f64\td10, d6, d7\n+\tvldr\td7, [pc, #464]\t@ 9160 <__gridxc_xwpbe_MOD_xwpbe+0x358>\n+\tldr\tr2, [sp, #32]\n+\tvcmpe.f64\td15, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td10, [sp, #40]\t@ 0x28\n+\tbpl.w\t9100 <__gridxc_xwpbe_MOD_xwpbe+0x2f8>\n+\tldr\tr3, [sp, #16]\n \tvmov.f64\td2, d14\n \tstr\tr3, [sp, #4]\n \tvmov.f64\td1, d11\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #20]\n \tvmov.f64\td0, d12\n \tstr\tr3, [sp, #0]\n \tmov\tr3, fp\n-\tbl\t6748 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>\n-\tb.n\t8be4 <__gridxc_xwpbe_MOD_xwpbe+0x2bc>\n-\tvmov.f64\td18, d13\n-\tvldr\td16, [pc, #420]\t@ 8c78 <__gridxc_xwpbe_MOD_xwpbe+0x350>\n-\tvstr\td15, [sl]\n-\tvstmia\tr8!, {d18}\n-\tvcmpe.f64\td8, d16\n+\tbl\t6ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>\n+\tb.n\t90ce <__gridxc_xwpbe_MOD_xwpbe+0x2c6>\n+\tvmov.f64\td6, d9\n+\tvldr\td7, [pc, #416]\t@ 9168 <__gridxc_xwpbe_MOD_xwpbe+0x360>\n+\tvstr\td10, [sl]\n+\tvstmia\tr8!, {d6}\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t8b42 <__gridxc_xwpbe_MOD_xwpbe+0x21a>\n-\tvldr\td21, [sp, #64]\t@ 0x40\n+\tble.n\t9034 <__gridxc_xwpbe_MOD_xwpbe+0x22c>\n+\tvldr\td6, [sp, #48]\t@ 0x30\n \tadds\tr5, #24\n-\tvldr\td19, [r4]\n+\tvldr\td4, [r4]\n \tadds\tr7, #1\n-\tvldr\td18, [r4, #8]\n+\tvldr\td5, [r4, #8]\n \tcmp\tr6, r7\n-\tvdiv.f64\td20, d21, d10\n-\tvldr\td16, [r4, #16]\n+\tvdiv.f64\td3, d6, d13\n+\tvldr\td7, [r4, #16]\n \tadd.w\tr4, r4, #24\n-\tvmul.f64\td19, d19, d20\n-\tvmul.f64\td18, d20, d18\n-\tvmul.f64\td16, d16, d20\n-\tvstr\td19, [r5, #-24]\t@ 0xffffffe8\n-\tvstr\td18, [r5, #-16]\n-\tvstr\td16, [r5, #-8]\n-\tbge.w\t899c <__gridxc_xwpbe_MOD_xwpbe+0x74>\n-\tldr\tr2, [pc, #356]\t@ (8c88 <__gridxc_xwpbe_MOD_xwpbe+0x360>)\n-\tldr\tr3, [pc, #348]\t@ (8c84 <__gridxc_xwpbe_MOD_xwpbe+0x35c>)\n+\tvmul.f64\td4, d4, d3\n+\tvmul.f64\td5, d3, d5\n+\tvmul.f64\td7, d7, d3\n+\tvstr\td4, [r5, #-24]\t@ 0xffffffe8\n+\tvstr\td5, [r5, #-16]\n+\tvstr\td7, [r5, #-8]\n+\tbge.w\t8e78 <__gridxc_xwpbe_MOD_xwpbe+0x70>\n+\tldr\tr2, [pc, #352]\t@ (9178 <__gridxc_xwpbe_MOD_xwpbe+0x370>)\n+\tldr\tr3, [pc, #348]\t@ (9174 <__gridxc_xwpbe_MOD_xwpbe+0x36c>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #124]\t@ 0x7c\n+\tldr\tr3, [sp, #108]\t@ 0x6c\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t8eb6 <__gridxc_xwpbe_MOD_xwpbe+0x58e>\n-\tadd\tsp, #132\t@ 0x84\n+\tbne.w\t93cc <__gridxc_xwpbe_MOD_xwpbe+0x5c4>\n+\tadd\tsp, #116\t@ 0x74\n \tvpop\t{d8-d15}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tadds\tr7, #1\n-\tvstr\td13, [r5]\n-\tvstr\td13, [r5, #16]\n+\tvstr\td9, [r5]\n+\tvstr\td9, [r5, #16]\n \tadds\tr4, #24\n-\tvstr\td13, [r5, #8]\n+\tvstr\td9, [r5, #8]\n \tcmp\tr6, r7\n \tadd.w\tr5, r5, #24\n-\tbge.w\t899c <__gridxc_xwpbe_MOD_xwpbe+0x74>\n-\tb.n\t8b22 <__gridxc_xwpbe_MOD_xwpbe+0x1fa>\n-\tvmov.f64\td14, d19\n-\tb.n\t8a3a <__gridxc_xwpbe_MOD_xwpbe+0x112>\n-\tadd.w\tip, sp, #96\t@ 0x60\n-\tadd\tr2, sp, #64\t@ 0x40\n-\tadd\tr1, sp, #88\t@ 0x58\n-\tadd\tr0, sp, #104\t@ 0x68\n-\tadd\tr3, sp, #72\t@ 0x48\n+\tbge.w\t8e78 <__gridxc_xwpbe_MOD_xwpbe+0x70>\n+\tb.n\t9014 <__gridxc_xwpbe_MOD_xwpbe+0x20c>\n+\tvmov.f64\td14, d6\n+\tb.n\t8f34 <__gridxc_xwpbe_MOD_xwpbe+0x12c>\n+\tadd.w\tip, sp, #80\t@ 0x50\n+\tadd\tr2, sp, #48\t@ 0x30\n+\tadd\tr1, sp, #72\t@ 0x48\n+\tadd\tr0, sp, #88\t@ 0x58\n+\tadd\tr3, sp, #56\t@ 0x38\n \tvmov.f64\td1, d11\n-\tstr\tr3, [sp, #20]\n+\tstr\tr3, [sp, #16]\n \tvmov.f64\td0, d12\n \tstr\tr3, [sp, #4]\n-\tadd.w\tfp, sp, #112\t@ 0x70\n-\tadd\tr3, sp, #80\t@ 0x50\n+\tadd.w\tfp, sp, #96\t@ 0x60\n+\tadd\tr3, sp, #64\t@ 0x40\n \tstr.w\tfp, [sp, #8]\n-\tstr\tr3, [sp, #24]\n+\tstr\tr3, [sp, #20]\n \tstr\tr3, [sp, #0]\n \tmov\tr3, ip\n-\tstrd\tr2, ip, [sp, #36]\t@ 0x24\n-\tstrd\tr0, r1, [sp, #28]\n-\tvstr\td20, [sp, #48]\t@ 0x30\n-\tbl\t820 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>\n-\tvldr\td16, [pc, #208]\t@ 8c70 <__gridxc_xwpbe_MOD_xwpbe+0x348>\n-\tvmov.f64\td18, #96\t@ 0x3f000000 0.5\n-\tvldr\td20, [sp, #48]\t@ 0x30\n-\tvldr\td19, [sp, #104]\t@ 0x68\n-\tldrd\tr0, r1, [sp, #28]\n-\tvcmpe.f64\td20, d16\n-\tvfma.f64\td15, d19, d18\n-\tvstr\td13, [sp, #104]\t@ 0x68\n-\tldrd\tr2, ip, [sp, #36]\t@ 0x24\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvstr\td15, [sp, #56]\t@ 0x38\n-\tbmi.n\t8bfa <__gridxc_xwpbe_MOD_xwpbe+0x2d2>\n-\tldr\tr3, [sp, #20]\n+\tstrd\tr2, ip, [sp, #32]\n+\tstrd\tr0, r1, [sp, #24]\n+\tbl\t828 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>\n+\tvldr\td6, [sp, #88]\t@ 0x58\n+\tvmov.f64\td7, #96\t@ 0x3f000000 0.5\n+\tldrd\tr0, r1, [sp, #24]\n+\tvstr\td9, [sp, #88]\t@ 0x58\n+\tvmla.f64\td10, d6, d7\n+\tvldr\td7, [pc, #192]\t@ 9160 <__gridxc_xwpbe_MOD_xwpbe+0x358>\n+\tldrd\tr2, ip, [sp, #32]\n+\tvcmpe.f64\td15, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvstr\td10, [sp, #40]\t@ 0x28\n+\tbmi.n\t90e4 <__gridxc_xwpbe_MOD_xwpbe+0x2dc>\n+\tldr\tr3, [sp, #16]\n \tvmov.f64\td1, d11\n \tstr\tr3, [sp, #4]\n \tvmov.f64\td0, d12\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #20]\n \tstr\tr3, [sp, #0]\n \tmov\tr3, ip\n \tstr.w\tfp, [sp, #8]\n-\tbl\t2590 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>\n-\tvldr\td19, [sp, #104]\t@ 0x68\n-\tvmov.f64\td16, #96\t@ 0x3f000000 0.5\n-\tvldr\td18, [sp, #88]\t@ 0x58\n-\tvfma.f64\td15, d19, d16\n-\tvstr\td15, [sp, #56]\t@ 0x38\n-\tb.n\t8ad2 <__gridxc_xwpbe_MOD_xwpbe+0x1aa>\n-\tldr\tr3, [sp, #20]\n+\tbl\t2670 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>\n+\tvldr\td7, [sp, #88]\t@ 0x58\n+\tvmov.f64\td5, #96\t@ 0x3f000000 0.5\n+\tvldr\td6, [sp, #72]\t@ 0x48\n+\tvmla.f64\td10, d7, d5\n+\tvstr\td10, [sp, #40]\t@ 0x28\n+\tb.n\t8fc4 <__gridxc_xwpbe_MOD_xwpbe+0x1bc>\n+\tldr\tr3, [sp, #16]\n \tvmov.f64\td1, d11\n \tstr\tr3, [sp, #4]\n \tvmov.f64\td0, d12\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #20]\n \tstr\tr3, [sp, #0]\n \tmov\tr3, ip\n \tstr.w\tfp, [sp, #8]\n-\tbl\t4b78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>\n-\tb.n\t8be4 <__gridxc_xwpbe_MOD_xwpbe+0x2bc>\n-\tldr\tr3, [sp, #20]\n+\tbl\t4dc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>\n+\tb.n\t90ce <__gridxc_xwpbe_MOD_xwpbe+0x2c6>\n+\tldr\tr3, [sp, #16]\n \tvmov.f64\td2, d14\n \tstr\tr3, [sp, #4]\n \tvmov.f64\td1, d11\n-\tldr\tr3, [sp, #24]\n+\tldr\tr3, [sp, #20]\n \tvmov.f64\td0, d12\n \tstr\tr3, [sp, #0]\n \tmov\tr3, fp\n-\tbl\t3664 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>\n-\tb.n\t8be4 <__gridxc_xwpbe_MOD_xwpbe+0x2bc>\n-\tnop\n+\tbl\t37d4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>\n+\tb.n\t90ce <__gridxc_xwpbe_MOD_xwpbe+0x2c6>\n \tnop.w\n-\t.word\t0x00000000\n+\t...\n \t.word\t0x3ca00000\n \t.word\t0xc9be45de\n \t.word\t0x4023bd3c\n \t.word\t0xd89c87ba\n \t.word\t0x4037f0fb\n \t.word\t0xfbb4c375\n \t.word\t0x3fd63003\n \t.word\t0xcf0b6b6e\n \t.word\t0x4021254b\n \t.word\t0x47f0848d\n-\t.word\t0xc032cbd5\n+\t.word\t0x4032cbd5\n \t.word\t0x47ae147b\n \t.word\t0x3fb47ae1\n \t.word\t0x9fedc755\n \t.word\t0x4066f1e3\n \t.word\t0x154ef7ad\n \t.word\t0x16687e92\n-\t.word\t0x00000338\n+\t.word\t0x00000342\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000015e\n+\t.word\t0x0000015c\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\tvldr\td10, [r1]\n-\tvldr\td8, [r4, #8]\n-\tvldr\td18, [r4]\n-\tvmaxnm.f64\td10, d10, d15\n-\tvldr\td19, [pc, #544]\t@ 8ec0 <__gridxc_xwpbe_MOD_xwpbe+0x598>\n-\tvmul.f64\td8, d8, d8\n-\tvldr\td17, [r4, #16]\n-\tvfma.f64\td8, d18, d18\n-\tvcmpe.f64\td10, d19\n-\tvfma.f64\td8, d17, d17\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tvsqrt.f64\td9, d8\n-\tble.n\t8d92 <__gridxc_xwpbe_MOD_xwpbe+0x46a>\n-\tvldr\td0, [pc, #520]\t@ 8ec8 <__gridxc_xwpbe_MOD_xwpbe+0x5a0>\n-\tvmaxnm.f64\td15, d9, d15\n-\tvmul.f64\td0, d10, d0\n+\tvldr\td9, [r1]\n+\tvldr\td7, [r4, #8]\n+\tvldr\td4, [r4]\n+\tvcmpe.f64\td9, d10\n+\tvldr\td3, [pc, #576]\t@ 93d0 <__gridxc_xwpbe_MOD_xwpbe+0x5c8>\n+\tvmul.f64\td7, d7, d7\n+\tvldr\td5, [r4, #16]\n+\tvmla.f64\td7, d4, d4\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tvmla.f64\td7, d5, d5\n+\tit\tlt\n+\tvmovlt.f64\td9, d10\n+\tvcmpe.f64\td9, d3\n+\tvsqrt.f64\td11, d7\n+\tvmov.f64\td8, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.n\t929e <__gridxc_xwpbe_MOD_xwpbe+0x496>\n+\tvcmpe.f64\td11, d10\n+\tvldr\td0, [pc, #532]\t@ 93d8 <__gridxc_xwpbe_MOD_xwpbe+0x5d0>\n+\tvmul.f64\td0, d9, d0\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tit\tge\n+\tvmovge.f64\td10, d11\n \tbl\t0 \n R_ARM_THM_CALL\tcbrt\n-\tvmov.f64\td18, #112\t@ 0x3f800000 1.0\n-\tvdiv.f64\td17, d15, d10\n-\tvldr\td19, [pc, #504]\t@ 8ed0 <__gridxc_xwpbe_MOD_xwpbe+0x5a8>\n-\tvdiv.f64\td11, d18, d0\n-\tvldr\td16, [pc, #504]\t@ 8ed8 <__gridxc_xwpbe_MOD_xwpbe+0x5b0>\n-\tvmul.f64\td17, d17, d11\n-\tvcmpe.f64\td17, d19\n-\tvmul.f64\td16, d17, d16\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.w\t8dfe <__gridxc_xwpbe_MOD_xwpbe+0x4d6>\n-\tvmul.f64\td17, d16, d16\n-\tvldr\td19, [pc, #484]\t@ 8ee0 <__gridxc_xwpbe_MOD_xwpbe+0x5b8>\n-\tvldr\td18, [pc, #488]\t@ 8ee8 <__gridxc_xwpbe_MOD_xwpbe+0x5c0>\n-\tvfma.f64\td18, d17, d19\n-\tvmul.f64\td17, d16, d17\n-\tvdiv.f64\td12, d18, d17\n-\tvmul.f64\td16, d16, d12\n-\tvmov.f64\td18, d12\n-\tvldr\td17, [pc, #472]\t@ 8ef0 <__gridxc_xwpbe_MOD_xwpbe+0x5c8>\n-\tvstr\td18, [sp, #112]\t@ 0x70\n-\tvcmpe.f64\td16, d17\n-\tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t8e28 <__gridxc_xwpbe_MOD_xwpbe+0x500>\n-\tadd.w\tsl, sp, #96\t@ 0x60\n-\tadd\tr2, sp, #64\t@ 0x40\n-\tadd\tr1, sp, #88\t@ 0x58\n-\tadd\tr0, sp, #56\t@ 0x38\n-\tvmov.f64\td2, d12\n-\tvmov.f64\td1, d15\n-\tvmov.f64\td0, d10\n-\tadd.w\tr9, sp, #72\t@ 0x48\n-\tadd.w\tr8, sp, #80\t@ 0x50\n-\tmov\tr3, sl\n-\tstr.w\tr9, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tstrd\tr1, r2, [sp, #24]\n-\tstr\tr0, [sp, #20]\n-\tbl\t1560 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>\n-\tvldr\td16, [pc, #412]\t@ 8ef8 <__gridxc_xwpbe_MOD_xwpbe+0x5d0>\n+\tvmov.f64\td7, #112\t@ 0x3f800000 1.0\n+\tvldr\td6, [pc, #516]\t@ 93e0 <__gridxc_xwpbe_MOD_xwpbe+0x5d8>\n+\tvldr\td5, [pc, #520]\t@ 93e8 <__gridxc_xwpbe_MOD_xwpbe+0x5e0>\n+\tvdiv.f64\td12, d7, d0\n+\tvdiv.f64\td4, d10, d9\n+\tvmul.f64\td4, d4, d12\n+\tvcmpe.f64\td4, d6\n+\tvmul.f64\td5, d4, d5\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.w\t930a <__gridxc_xwpbe_MOD_xwpbe+0x502>\n+\tvmul.f64\td7, d5, d5\n+\tvldr\td4, [pc, #492]\t@ 93f0 <__gridxc_xwpbe_MOD_xwpbe+0x5e8>\n+\tvldr\td6, [pc, #496]\t@ 93f8 <__gridxc_xwpbe_MOD_xwpbe+0x5f0>\n+\tvnmls.f64\td6, d7, d4\n+\tvmul.f64\td7, d5, d7\n+\tvdiv.f64\td13, d6, d7\n+\tvmul.f64\td5, d5, d13\n+\tvmov.f64\td7, d13\n+\tvstr\td7, [sp, #96]\t@ 0x60\n+\tvldr\td7, [pc, #476]\t@ 9400 <__gridxc_xwpbe_MOD_xwpbe+0x5f8>\n+\tvcmpe.f64\td5, d7\n+\tvmrs\tAPSR_nzcv, fpscr\n+\tble.w\t9338 <__gridxc_xwpbe_MOD_xwpbe+0x530>\n+\tadd.w\tfp, sp, #80\t@ 0x50\n+\tadd.w\tr8, sp, #48\t@ 0x30\n+\tadd\tr1, sp, #72\t@ 0x48\n+\tadd\tr0, sp, #40\t@ 0x28\n+\tadd\tr3, sp, #56\t@ 0x38\n+\tvmov.f64\td2, d13\n+\tstr\tr3, [sp, #16]\n+\tvmov.f64\td1, d10\n+\tstr\tr3, [sp, #4]\n+\tvmov.f64\td0, d9\n+\tadd.w\tr9, sp, #64\t@ 0x40\n+\tmov\tr3, fp\n+\tmov\tr2, r8\n+\tstr.w\tr9, [sp]\n+\tstrd\tr0, r1, [sp, #20]\n+\tbl\t15a8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_0.constprop.0.isra.0>\n+\tvldr\td7, [pc, #416]\t@ 9408 <__gridxc_xwpbe_MOD_xwpbe+0x600>\n \tldrd\tr0, r1, [sp, #20]\n-\tvcmpe.f64\td11, d16\n-\tldr\tr2, [sp, #28]\n+\tvcmpe.f64\td12, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t8e04 <__gridxc_xwpbe_MOD_xwpbe+0x4dc>\n-\tvmov.f64\td1, d15\n-\tstrd\tr8, r9, [sp]\n-\tvmov.f64\td2, d12\n-\tvmov.f64\td0, d10\n-\tmov\tr3, sl\n-\tbl\t6748 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>\n-\tldr.w\tr9, [r6]\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tb.n\t8d96 <__gridxc_xwpbe_MOD_xwpbe+0x46e>\n-\tvmov.f64\td16, d15\n-\tvstr\td16, [fp]\n+\tbpl.n\t9310 <__gridxc_xwpbe_MOD_xwpbe+0x508>\n+\tldr\tr3, [sp, #16]\n+\tvmov.f64\td1, d10\n+\tstrd\tr9, r3, [sp]\n+\tvmov.f64\td2, d13\n+\tvmov.f64\td0, d9\n+\tmov\tr3, fp\n+\tmov\tr2, r8\n+\tbl\t6ad8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_1.constprop.0.isra.0>\n+\tldr.w\tr9, [r5]\n+\tvldr\td10, [sp, #72]\t@ 0x48\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tb.n\t92a2 <__gridxc_xwpbe_MOD_xwpbe+0x49a>\n+\tvmov.f64\td7, d10\n+\tvstr\td7, [sl]\n \tadd.w\tr2, r7, r9, lsl #3\n-\tvldr\td16, [pc, #352]\t@ 8f00 <__gridxc_xwpbe_MOD_xwpbe+0x5d8>\n+\tvldr\td7, [pc, #356]\t@ 9410 <__gridxc_xwpbe_MOD_xwpbe+0x608>\n \tadd.w\tr3, r9, r9, lsl #1\n-\tvstr\td15, [r2, #-8]\n-\tvcmpe.f64\td8, d16\n+\tvstr\td10, [r2, #-8]\n+\tvcmpe.f64\td8, d7\n \tvmrs\tAPSR_nzcv, fpscr\n-\tble.n\t8de8 <__gridxc_xwpbe_MOD_xwpbe+0x4c0>\n-\tvldr\td16, [sp, #64]\t@ 0x40\n+\tble.n\t92f4 <__gridxc_xwpbe_MOD_xwpbe+0x4ec>\n+\tvldr\td7, [sp, #48]\t@ 0x30\n \tlsls\tr3, r3, #3\n \tadd\tr4, r3\n-\tadd\tr3, r5\n-\tvdiv.f64\td19, d16, d9\n-\tvldr\td18, [r4, #-24]\t@ 0xffffffe8\n-\tvldr\td17, [r4, #-16]\n-\tvldr\td16, [r4, #-8]\n-\tvmul.f64\td18, d18, d19\n-\tvmul.f64\td17, d17, d19\n-\tvmul.f64\td16, d16, d19\n-\tvstr\td18, [r3, #-24]\t@ 0xffffffe8\n-\tvstr\td17, [r3, #-16]\n-\tvstr\td16, [r3, #-8]\n-\tb.n\t8b22 <__gridxc_xwpbe_MOD_xwpbe+0x1fa>\n-\tadd.w\tr2, r5, r3, lsl #3\n+\tadd\tr3, r6\n+\tvdiv.f64\td4, d7, d11\n+\tvldr\td5, [r4, #-24]\t@ 0xffffffe8\n+\tvldr\td6, [r4, #-16]\n+\tvldr\td7, [r4, #-8]\n+\tvmul.f64\td5, d5, d4\n+\tvmul.f64\td6, d6, d4\n+\tvmul.f64\td7, d7, d4\n+\tvstr\td5, [r3, #-24]\t@ 0xffffffe8\n+\tvstr\td6, [r3, #-16]\n+\tvstr\td7, [r3, #-8]\n+\tb.n\t9014 <__gridxc_xwpbe_MOD_xwpbe+0x20c>\n+\tadd.w\tr2, r6, r3, lsl #3\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tstrd\tr0, r1, [r2, #-24]\n \tstrd\tr0, r1, [r2, #-16]\n \tstrd\tr0, r1, [r2, #-8]\n-\tb.n\t8b22 <__gridxc_xwpbe_MOD_xwpbe+0x1fa>\n-\tvmov.f64\td12, d18\n-\tb.n\t8d16 <__gridxc_xwpbe_MOD_xwpbe+0x3ee>\n-\tvmov.f64\td1, d15\n-\tstrd\tr8, r9, [sp]\n-\tvmov.f64\td2, d12\n-\tvmov.f64\td0, d10\n-\tmov\tr3, sl\n-\tbl\t3664 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>\n-\tldr.w\tr9, [r6]\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tb.n\t8d96 <__gridxc_xwpbe_MOD_xwpbe+0x46e>\n-\tadd\tr3, sp, #96\t@ 0x60\n-\tadd\tr2, sp, #64\t@ 0x40\n-\tadd\tr1, sp, #88\t@ 0x58\n-\tadd\tr0, sp, #56\t@ 0x38\n-\tvmov.f64\td1, d15\n-\tvmov.f64\td0, d10\n-\tadd.w\tsl, sp, #112\t@ 0x70\n-\tadd.w\tr9, sp, #72\t@ 0x48\n-\tadd.w\tr8, sp, #80\t@ 0x50\n-\tstr.w\tsl, [sp, #8]\n-\tstr.w\tr9, [sp, #4]\n-\tstr.w\tr8, [sp]\n-\tstrd\tr2, r3, [sp, #28]\n+\tb.n\t9014 <__gridxc_xwpbe_MOD_xwpbe+0x20c>\n+\tvmov.f64\td13, d7\n+\tb.n\t921e <__gridxc_xwpbe_MOD_xwpbe+0x416>\n+\tldr\tr3, [sp, #16]\n+\tvmov.f64\td1, d10\n+\tstrd\tr9, r3, [sp]\n+\tvmov.f64\td2, d13\n+\tvmov.f64\td0, d9\n+\tmov\tr3, fp\n+\tmov\tr2, r8\n+\tbl\t37d4 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_3.constprop.0.isra.0>\n+\tldr.w\tr9, [r5]\n+\tvldr\td10, [sp, #72]\t@ 0x48\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tb.n\t92a2 <__gridxc_xwpbe_MOD_xwpbe+0x49a>\n+\tadd.w\tr8, sp, #48\t@ 0x30\n+\tadd\tr3, sp, #80\t@ 0x50\n+\tadd\tr1, sp, #72\t@ 0x48\n+\tadd\tr0, sp, #40\t@ 0x28\n+\tadd\tr2, sp, #56\t@ 0x38\n+\tvmov.f64\td1, d10\n+\tstr\tr2, [sp, #16]\n+\tvmov.f64\td0, d9\n+\tstr\tr2, [sp, #4]\n+\tadd.w\tfp, sp, #96\t@ 0x60\n+\tadd.w\tr9, sp, #64\t@ 0x40\n+\tmov\tr2, r8\n+\tstr.w\tfp, [sp, #8]\n+\tstr.w\tr9, [sp]\n+\tstr\tr3, [sp, #28]\n \tstrd\tr0, r1, [sp, #20]\n-\tbl\t820 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>\n-\tvldr\td16, [pc, #152]\t@ 8ef8 <__gridxc_xwpbe_MOD_xwpbe+0x5d0>\n+\tbl\t828 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_01.constprop.0.isra.0>\n+\tvldr\td7, [pc, #152]\t@ 9408 <__gridxc_xwpbe_MOD_xwpbe+0x600>\n \tldrd\tr0, r1, [sp, #20]\n-\tvcmpe.f64\td11, d16\n-\tldrd\tr2, r3, [sp, #28]\n+\tvcmpe.f64\td12, d7\n+\tldr\tr3, [sp, #28]\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbpl.n\t8e94 <__gridxc_xwpbe_MOD_xwpbe+0x56c>\n-\tvmov.f64\td1, d15\n-\tstrd\tr9, sl, [sp, #4]\n-\tvmov.f64\td0, d10\n-\tstr.w\tr8, [sp]\n-\tbl\t4b78 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>\n-\tldr.w\tr9, [r6]\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tb.n\t8d96 <__gridxc_xwpbe_MOD_xwpbe+0x46e>\n-\tvmov.f64\td1, d15\n-\tstrd\tr9, sl, [sp, #4]\n-\tvmov.f64\td0, d10\n-\tstr.w\tr8, [sp]\n-\tbl\t2590 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>\n-\tldr.w\tr9, [r6]\n-\tvldr\td15, [sp, #88]\t@ 0x58\n-\tvldr\td16, [sp, #56]\t@ 0x38\n-\tb.n\t8d96 <__gridxc_xwpbe_MOD_xwpbe+0x46e>\n+\tbpl.n\t93a6 <__gridxc_xwpbe_MOD_xwpbe+0x59e>\n+\tldr\tr2, [sp, #16]\n+\tvmov.f64\td1, d10\n+\tstrd\tr9, r2, [sp]\n+\tvmov.f64\td0, d9\n+\tmov\tr2, r8\n+\tstr.w\tfp, [sp, #8]\n+\tbl\t4dc8 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_2.constprop.0.isra.0>\n+\tldr.w\tr9, [r5]\n+\tvldr\td10, [sp, #72]\t@ 0x48\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tb.n\t92a2 <__gridxc_xwpbe_MOD_xwpbe+0x49a>\n+\tldr\tr2, [sp, #16]\n+\tvmov.f64\td1, d10\n+\tstrd\tr9, r2, [sp]\n+\tvmov.f64\td0, d9\n+\tmov\tr2, r8\n+\tstr.w\tfp, [sp, #8]\n+\tbl\t2670 <__gridxc_xwpbe_MOD_xwpbe_lda_calc_4.constprop.0.isra.0>\n+\tldr.w\tr9, [r5]\n+\tvldr\td10, [sp, #72]\t@ 0x48\n+\tvldr\td7, [sp, #40]\t@ 0x28\n+\tb.n\t92a2 <__gridxc_xwpbe_MOD_xwpbe+0x49a>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\tnop\n-\tnop.w\n \t.word\t0x00000000\n \t.word\t0x3cb00000\n \t.word\t0xc9be45de\n \t.word\t0x4023bd3c\n \t.word\t0xd89c87ba\n \t.word\t0x4037f0fb\n \t.word\t0xfbb4c375\n \t.word\t0x3fd63003\n \t.word\t0xcf0b6b6e\n \t.word\t0x4021254b\n \t.word\t0x47f0848d\n-\t.word\t0xc032cbd5\n+\t.word\t0x4032cbd5\n \t.word\t0x47ae147b\n \t.word\t0x3fb47ae1\n \t.word\t0x9fedc755\n \t.word\t0x4066f1e3\n \t.word\t0x154ef7ad\n \t.word\t0x16687e92\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -31,20 +31,20 @@\n 0x000001c0 2e302e69 7372612e 30005f5f 67726964 .0.isra.0.__grid\n 0x000001d0 78635f78 77706265 5f4d4f44 5f787770 xc_xwpbe_MOD_xwp\n 0x000001e0 62655f6c 64615f63 616c635f 322e636f be_lda_calc_2.co\n 0x000001f0 6e737470 726f702e 302e6973 72612e30 nstprop.0.isra.0\n 0x00000200 005f5f67 72696478 635f7877 7062655f .__gridxc_xwpbe_\n 0x00000210 4d4f445f 78777062 655f6c64 615f6361 MOD_xwpbe_lda_ca\n 0x00000220 6c635f31 2e636f6e 73747072 6f702e30 lc_1.constprop.0\n- 0x00000230 2e697372 612e3000 65787000 5f67666f .isra.0.exp._gfo\n- 0x00000240 72747261 6e5f7374 5f777269 7465005f rtran_st_write._\n- 0x00000250 67666f72 7472616e 5f747261 6e736665 gfortran_transfe\n- 0x00000260 725f6368 61726163 7465725f 77726974 r_character_writ\n- 0x00000270 65005f67 666f7274 72616e5f 73745f77 e._gfortran_st_w\n- 0x00000280 72697465 5f646f6e 65006c6f 67005f5f rite_done.log.__\n- 0x00000290 73746163 6b5f6368 6b5f6661 696c005f stack_chk_fail._\n- 0x000002a0 474c4f42 414c5f4f 46465345 545f5441 GLOBAL_OFFSET_TA\n- 0x000002b0 424c455f 005f5f73 7461636b 5f63686b BLE_.__stack_chk\n- 0x000002c0 5f677561 72640063 62727400 5f5f6772 _guard.cbrt.__gr\n- 0x000002d0 69647863 5f787770 62655f4d 4f445f78 idxc_xwpbe_MOD_x\n- 0x000002e0 77706265 00 wpbe.\n+ 0x00000230 2e697372 612e3000 7472756e 63006578 .isra.0.trunc.ex\n+ 0x00000240 70005f67 666f7274 72616e5f 73745f77 p._gfortran_st_w\n+ 0x00000250 72697465 005f6766 6f727472 616e5f74 rite._gfortran_t\n+ 0x00000260 72616e73 6665725f 63686172 61637465 ransfer_characte\n+ 0x00000270 725f7772 69746500 5f67666f 72747261 r_write._gfortra\n+ 0x00000280 6e5f7374 5f777269 74655f64 6f6e6500 n_st_write_done.\n+ 0x00000290 6c6f6700 5f5f7374 61636b5f 63686b5f log.__stack_chk_\n+ 0x000002a0 6661696c 005f474c 4f42414c 5f4f4646 fail._GLOBAL_OFF\n+ 0x000002b0 5345545f 5441424c 455f005f 5f737461 SET_TABLE_.__sta\n+ 0x000002c0 636b5f63 686b5f67 75617264 00636272 ck_chk_guard.cbr\n+ 0x000002d0 74005f5f 67726964 78635f78 77706265 t.__gridxc_xwpbe\n+ 0x000002e0 5f4d4f44 5f787770 626500 _MOD_xwpbe.\n \n"}]}, {"source1": "xcmod.F90.o", "source2": "xcmod.F90.o", "unified_diff": null, "details": [{"source1": "readelf --wide --file-header {}", "source2": "readelf --wide --file-header {}", "unified_diff": "@@ -6,15 +6,15 @@\n OS/ABI: UNIX - System V\n ABI Version: 0\n Type: REL (Relocatable file)\n Machine: ARM\n Version: 0x1\n Entry point address: 0x0\n Start of program headers: 0 (bytes into file)\n- Start of section headers: 9752 (bytes into file)\n+ Start of section headers: 9700 (bytes into file)\n Flags: 0x5000000, Version5 EABI\n Size of this header: 52 (bytes)\n Size of program headers: 0 (bytes)\n Number of program headers: 0\n Size of section headers: 40 (bytes)\n Number of section headers: 12\n Section header string table index: 11\n"}, {"source1": "readelf --wide --sections {}", "source2": "readelf --wide --sections {}", "unified_diff": "@@ -1,21 +1,21 @@\n-There are 12 section headers, starting at offset 0x2618:\n+There are 12 section headers, starting at offset 0x25e4:\n \n Section Headers:\n [Nr] Name Type Addr Off Size ES Flg Lk Inf Al\n [ 0] NULL 00000000 000000 000000 00 0 0 0\n- [ 1] .text PROGBITS 00000000 000038 001390 00 AX 0 0 8\n- [ 2] .rel.text REL 00000000 002008 0005a8 08 I 9 1 4\n- [ 3] .data PROGBITS 00000000 0013c8 000000 00 WA 0 0 1\n- [ 4] .bss NOBITS 00000000 0013c8 000918 00 WA 0 0 8\n- [ 5] .rodata.str1.4 PROGBITS 00000000 0013c8 0001d6 01 AMS 0 0 4\n- [ 6] .rodata PROGBITS 00000000 0015a0 000018 00 A 0 0 8\n- [ 7] .note.GNU-stack PROGBITS 00000000 0015b8 000000 00 0 0 1\n- [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0015b8 000033 00 0 0 1\n- [ 9] .symtab SYMTAB 00000000 0015ec 000540 10 10 45 4\n- [10] .strtab STRTAB 00000000 001b2c 0004d9 00 0 0 1\n- [11] .shstrtab STRTAB 00000000 0025b0 000067 00 0 0 1\n+ [ 1] .text PROGBITS 00000000 000038 001380 00 AX 0 0 8\n+ [ 2] .rel.text REL 00000000 001fd4 0005a8 08 I 9 1 4\n+ [ 3] .data PROGBITS 00000000 0013b8 000000 00 WA 0 0 1\n+ [ 4] .bss NOBITS 00000000 0013b8 000918 00 WA 0 0 8\n+ [ 5] .rodata.str1.4 PROGBITS 00000000 0013b8 0001d6 01 AMS 0 0 4\n+ [ 6] .rodata PROGBITS 00000000 001590 000018 00 A 0 0 8\n+ [ 7] .note.GNU-stack PROGBITS 00000000 0015a8 000000 00 0 0 1\n+ [ 8] .ARM.attributes ARM_ATTRIBUTES 00000000 0015a8 00002d 00 0 0 1\n+ [ 9] .symtab SYMTAB 00000000 0015d8 000520 10 10 43 4\n+ [10] .strtab STRTAB 00000000 001af8 0004d9 00 0 0 1\n+ [11] .shstrtab STRTAB 00000000 00257c 000067 00 0 0 1\n Key to Flags:\n W (write), A (alloc), X (execute), M (merge), S (strings), I (info),\n L (link order), O (extra OS processing required), G (group), T (TLS),\n C (compressed), x (unknown), o (OS specific), E (exclude),\n D (mbind), y (purecode), p (processor specific)\n"}, {"source1": "readelf --wide --symbols {}", "source2": "readelf --wide --symbols {}", "unified_diff": "@@ -1,9 +1,9 @@\n \n-Symbol table '.symtab' contains 84 entries:\n+Symbol table '.symtab' contains 82 entries:\n Num: Value Size Type Bind Vis Ndx Name\n 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n 1: 00000000 0 SECTION LOCAL DEFAULT 4 .bss\n 2: 00000000 0 NOTYPE LOCAL DEFAULT 5 $d\n 3: 00000000 0 NOTYPE LOCAL DEFAULT 5 .LC0\n 4: 00000004 0 NOTYPE LOCAL DEFAULT 5 .LC1\n 5: 0000003c 0 NOTYPE LOCAL DEFAULT 5 .LC2\n@@ -13,75 +13,73 @@\n 9: 00000088 0 NOTYPE LOCAL DEFAULT 5 .LC6\n 10: 0000009c 0 NOTYPE LOCAL DEFAULT 5 .LC7\n 11: 000000a8 0 NOTYPE LOCAL DEFAULT 5 .LC8\n 12: 000000ac 0 NOTYPE LOCAL DEFAULT 5 .LC9\n 13: 000000c0 0 NOTYPE LOCAL DEFAULT 5 .LC10\n 14: 000000c4 0 NOTYPE LOCAL DEFAULT 5 .LC11\n 15: 000000c8 0 NOTYPE LOCAL DEFAULT 5 .LC12\n- 16: 00000001 1612 FUNC LOCAL DEFAULT 1 __gridxc_xcmod_MOD_process_libxc_spec.constprop.0\n+ 16: 00000001 1624 FUNC LOCAL DEFAULT 1 __gridxc_xcmod_MOD_process_libxc_spec.constprop.0\n 17: 00000000 0 NOTYPE LOCAL DEFAULT 1 $t\n- 18: 00000370 0 NOTYPE LOCAL DEFAULT 1 $d\n- 19: 000003d0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 20: 0000062c 0 NOTYPE LOCAL DEFAULT 1 $d\n- 21: 0000064c 0 NOTYPE LOCAL DEFAULT 1 $t\n- 22: 000009bc 0 NOTYPE LOCAL DEFAULT 1 $d\n- 23: 000000f0 0 NOTYPE LOCAL DEFAULT 5 .LC13\n- 24: 0000011c 0 NOTYPE LOCAL DEFAULT 5 .LC14\n- 25: 00000120 0 NOTYPE LOCAL DEFAULT 5 .LC15\n- 26: 00000124 0 NOTYPE LOCAL DEFAULT 5 .LC16\n- 27: 00000128 0 NOTYPE LOCAL DEFAULT 5 .LC17\n- 28: 000009e0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 29: 00000d34 0 NOTYPE LOCAL DEFAULT 1 $d\n- 30: 000009e1 944 FUNC LOCAL DEFAULT 1 __gridxc_xcmod_MOD_setxc.localalias\n- 31: 00000d90 0 NOTYPE LOCAL DEFAULT 1 $t\n- 32: 00000fa0 0 NOTYPE LOCAL DEFAULT 1 $d\n- 33: 00000160 0 NOTYPE LOCAL DEFAULT 5 .LC19\n- 34: 00000178 0 NOTYPE LOCAL DEFAULT 5 .LC20\n- 35: 00000198 0 NOTYPE LOCAL DEFAULT 5 .LC21\n- 36: 000001b4 0 NOTYPE LOCAL DEFAULT 5 .LC22\n- 37: 000001bc 0 NOTYPE LOCAL DEFAULT 5 .LC23\n- 38: 00000fb0 0 NOTYPE LOCAL DEFAULT 1 $t\n- 39: 00001348 0 NOTYPE LOCAL DEFAULT 1 $d\n- 40: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n- 41: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n- 42: 00000000 8 OBJECT LOCAL DEFAULT 6 A.88.1\n- 43: 00000010 8 OBJECT LOCAL DEFAULT 6 A.90.0\n- 44: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n- 45: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_index\n- 46: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n- 47: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n- 48: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n- 49: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_functional_get_number\n- 50: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n- 51: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n- 52: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n- 53: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_len_trim\n- 54: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n- 55: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_family_from_id\n- 56: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n- 57: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n- 58: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n- 59: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n- 60: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n- 61: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n- 62: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n- 63: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n- 64: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n- 65: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n- 66: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n- 67: 0000064d 916 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_getxc\n- 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND memmove\n- 69: 000009e1 944 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc\n- 70: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_author\n- 71: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcmp\n- 72: 00000d91 544 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc_family_authors\n- 73: 00000fb1 992 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc_libxc_ids\n- 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n- 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n- 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n- 77: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n- 78: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n- 79: 000007d8 160 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcweightx\n- 80: 00000878 160 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcweightc\n- 81: 00000008 1000 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcfunc\n- 82: 000003f0 1000 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcauth\n- 83: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_nxcfunc\n+ 18: 000005f0 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 19: 00000658 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 20: 000009c8 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 21: 000000f0 0 NOTYPE LOCAL DEFAULT 5 .LC13\n+ 22: 0000011c 0 NOTYPE LOCAL DEFAULT 5 .LC14\n+ 23: 00000120 0 NOTYPE LOCAL DEFAULT 5 .LC15\n+ 24: 00000124 0 NOTYPE LOCAL DEFAULT 5 .LC16\n+ 25: 00000128 0 NOTYPE LOCAL DEFAULT 5 .LC17\n+ 26: 000009ec 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 27: 00000d18 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 28: 000009ed 904 FUNC LOCAL DEFAULT 1 __gridxc_xcmod_MOD_setxc.localalias\n+ 29: 00000d74 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 30: 00000f84 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 31: 00000160 0 NOTYPE LOCAL DEFAULT 5 .LC19\n+ 32: 00000178 0 NOTYPE LOCAL DEFAULT 5 .LC20\n+ 33: 00000198 0 NOTYPE LOCAL DEFAULT 5 .LC21\n+ 34: 000001b4 0 NOTYPE LOCAL DEFAULT 5 .LC22\n+ 35: 000001bc 0 NOTYPE LOCAL DEFAULT 5 .LC23\n+ 36: 00000f94 0 NOTYPE LOCAL DEFAULT 1 $t\n+ 37: 00001338 0 NOTYPE LOCAL DEFAULT 1 $d\n+ 38: 00000000 0 SECTION LOCAL DEFAULT 6 .rodata\n+ 39: 00000000 0 NOTYPE LOCAL DEFAULT 6 $d\n+ 40: 00000000 8 OBJECT LOCAL DEFAULT 6 A.88.1\n+ 41: 00000010 8 OBJECT LOCAL DEFAULT 6 A.90.0\n+ 42: 00000000 0 NOTYPE LOCAL DEFAULT 4 $d\n+ 43: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_index\n+ 44: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read\n+ 45: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer\n+ 46: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_read_done\n+ 47: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_functional_get_number\n+ 48: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write\n+ 49: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_character_write\n+ 50: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_transfer_integer_write\n+ 51: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_len_trim\n+ 52: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_st_write_done\n+ 53: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_family_from_id\n+ 54: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_compare_string\n+ 55: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_string_trim\n+ 56: 00000000 0 NOTYPE GLOBAL DEFAULT UND malloc\n+ 57: 00000000 0 NOTYPE GLOBAL DEFAULT UND _gfortran_concat_string\n+ 58: 00000000 0 NOTYPE GLOBAL DEFAULT UND free\n+ 59: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcpy\n+ 60: 00000000 0 NOTYPE GLOBAL DEFAULT UND memset\n+ 61: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_fail\n+ 62: 00000000 0 NOTYPE GLOBAL DEFAULT UND _GLOBAL_OFFSET_TABLE_\n+ 63: 00000000 0 NOTYPE GLOBAL DEFAULT UND __stack_chk_guard\n+ 64: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_sys_MOD_die\n+ 65: 00000659 916 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_getxc\n+ 66: 00000000 0 NOTYPE GLOBAL DEFAULT UND memmove\n+ 67: 000009ed 904 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc\n+ 68: 00000000 0 NOTYPE GLOBAL DEFAULT UND __gridxc_vdwxc_MOD_vdw_set_author\n+ 69: 00000000 0 NOTYPE GLOBAL DEFAULT UND memcmp\n+ 70: 00000d75 544 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc_family_authors\n+ 71: 00000f95 1004 FUNC GLOBAL DEFAULT 1 __gridxc_xcmod_MOD_setxc_libxc_ids\n+ 72: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_init\n+ 73: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+ 74: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+ 75: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+ 76: 00000000 0 NOTYPE GLOBAL DEFAULT UND __xc_f03_lib_m_MOD_xc_f03_func_end\n+ 77: 000007d8 160 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcweightx\n+ 78: 00000878 160 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcweightc\n+ 79: 00000004 1000 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcfunc\n+ 80: 000003ec 1000 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_xcauth\n+ 81: 00000000 4 OBJECT GLOBAL HIDDEN 4 __gridxc_xcmod_MOD_nxcfunc\n"}, {"source1": "readelf --wide --relocs {}", "source2": "readelf --wide --relocs {}", "unified_diff": "@@ -1,184 +1,184 @@\n \n-Relocation section '.rel.text' at offset 0x2008 contains 181 entries:\n+Relocation section '.rel.text' at offset 0x1fd4 contains 181 entries:\n Offset Info Type Sym. Value Symbol's Name\n-00000040 00002d0a R_ARM_THM_CALL 00000000 _gfortran_string_index\n-0000007c 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-00000086 00002f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n-0000008c 0000300a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-000000de 0000310a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_functional_get_number\n-00000120 0000320a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-0000012c 0000330a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000136 0000340a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-0000013e 0000350a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n-0000014a 0000330a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000150 0000360a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-0000015a 0000370a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_family_from_id\n-0000016e 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000184 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-00000196 00003a0a R_ARM_THM_CALL 00000000 malloc\n-000001ac 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000001bc 00003c0a R_ARM_THM_CALL 00000000 free\n-000001d0 00003a0a R_ARM_THM_CALL 00000000 malloc\n-000001ee 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000001f8 00003c0a R_ARM_THM_CALL 00000000 free\n-00000204 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000021c 00003a0a R_ARM_THM_CALL 00000000 malloc\n-00000232 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000242 00003c0a R_ARM_THM_CALL 00000000 free\n-0000024c 00003c0a R_ARM_THM_CALL 00000000 free\n-000002a8 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n-000002b2 00002f0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n-000002b8 0000300a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n-000002ee 0000320a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-000002fa 0000330a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-00000304 0000340a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-0000030a 0000360a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-00000314 0000370a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_family_from_id\n-00000332 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000380 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000384 00003e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000388 00000303 R_ARM_REL32 00000000 .LC0\n-0000038c 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000390 00000403 R_ARM_REL32 00000004 .LC1\n-00000394 00000403 R_ARM_REL32 00000004 .LC1\n-00000398 00000703 R_ARM_REL32 00000070 .LC4\n-0000039c 00000803 R_ARM_REL32 00000080 .LC5\n-000003a0 00000e03 R_ARM_REL32 000000c4 .LC11\n-000003a4 00000c03 R_ARM_REL32 000000ac .LC9\n-000003a8 00000d03 R_ARM_REL32 000000c0 .LC10\n-000003ac 00003f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-000003b0 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003b4 00000403 R_ARM_REL32 00000004 .LC1\n-000003b8 00000403 R_ARM_REL32 00000004 .LC1\n-000003bc 00000a03 R_ARM_REL32 0000009c .LC7\n-000003c0 00000803 R_ARM_REL32 00000080 .LC5\n-000003c4 00000b03 R_ARM_REL32 000000a8 .LC8\n-000003c8 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-000003cc 00000f03 R_ARM_REL32 000000c8 .LC12\n-000003e6 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-000003fc 00003a0a R_ARM_THM_CALL 00000000 malloc\n-00000416 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000422 00003c0a R_ARM_THM_CALL 00000000 free\n-0000043c 00003c0a R_ARM_THM_CALL 00000000 free\n-00000452 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000460 0000410a R_ARM_THM_CALL 00000000 memset\n-00000476 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000048c 00003a0a R_ARM_THM_CALL 00000000 malloc\n-000004a6 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000004c6 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-000004dc 00003a0a R_ARM_THM_CALL 00000000 malloc\n-000004f6 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000502 00003c0a R_ARM_THM_CALL 00000000 free\n-00000518 00003c0a R_ARM_THM_CALL 00000000 free\n-0000052a 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-0000053c 00003a0a R_ARM_THM_CALL 00000000 malloc\n-00000552 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-00000562 00003c0a R_ARM_THM_CALL 00000000 free\n-00000576 00003a0a R_ARM_THM_CALL 00000000 malloc\n-00000594 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-0000059e 00003c0a R_ARM_THM_CALL 00000000 free\n-000005aa 0000390a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n-000005c2 00003a0a R_ARM_THM_CALL 00000000 malloc\n-000005d8 00003b0a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n-000005e8 00003c0a R_ARM_THM_CALL 00000000 free\n-000005f2 00003c0a R_ARM_THM_CALL 00000000 free\n-0000061e 0000420a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000624 00003c0a R_ARM_THM_CALL 00000000 free\n-0000062c 00000603 R_ARM_REL32 00000054 .LC3\n-00000630 00003f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000634 00000503 R_ARM_REL32 0000003c .LC2\n-00000638 00000903 R_ARM_REL32 00000088 .LC6\n-0000063c 00000c03 R_ARM_REL32 000000ac .LC9\n-00000640 00000d03 R_ARM_REL32 000000c0 .LC10\n-00000644 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000648 00003e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000758 0000440a R_ARM_THM_CALL 00000000 memmove\n-000007d4 0000440a R_ARM_THM_CALL 00000000 memmove\n-000008f2 0000440a R_ARM_THM_CALL 00000000 memmove\n-000008fe 0000410a R_ARM_THM_CALL 00000000 memset\n-0000094e 0000440a R_ARM_THM_CALL 00000000 memmove\n-0000095a 0000410a R_ARM_THM_CALL 00000000 memset\n-000009bc 00000103 R_ARM_REL32 00000000 .bss\n-000009c0 00000103 R_ARM_REL32 00000000 .bss\n-000009c4 00000103 R_ARM_REL32 00000000 .bss\n+00000046 00002b0a R_ARM_THM_CALL 00000000 _gfortran_string_index\n+00000088 00002c0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+00000092 00002d0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n+00000098 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+000000ea 00002f0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_functional_get_number\n+00000136 0000300a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000144 0000310a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+0000014e 0000320a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000156 0000330a R_ARM_THM_CALL 00000000 _gfortran_string_len_trim\n+00000162 0000310a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+00000168 0000340a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+00000172 0000350a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_family_from_id\n+00000190 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+000001e8 00002c0a R_ARM_THM_CALL 00000000 _gfortran_st_read\n+000001f2 00002d0a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer\n+000001f8 00002e0a R_ARM_THM_CALL 00000000 _gfortran_st_read_done\n+00000236 0000300a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+00000242 0000310a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+0000024c 0000320a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00000252 0000340a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+0000025c 0000350a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_family_from_id\n+0000026e 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000282 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000294 0000380a R_ARM_THM_CALL 00000000 malloc\n+000002aa 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000002ba 00003a0a R_ARM_THM_CALL 00000000 free\n+000002ce 0000380a R_ARM_THM_CALL 00000000 malloc\n+000002ec 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000002f6 00003a0a R_ARM_THM_CALL 00000000 free\n+00000302 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+0000031a 0000380a R_ARM_THM_CALL 00000000 malloc\n+00000330 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000340 00003a0a R_ARM_THM_CALL 00000000 free\n+0000034a 00003a0a R_ARM_THM_CALL 00000000 free\n+000003aa 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+000003c0 0000380a R_ARM_THM_CALL 00000000 malloc\n+000003da 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000003e6 00003a0a R_ARM_THM_CALL 00000000 free\n+00000400 00003a0a R_ARM_THM_CALL 00000000 free\n+00000416 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000424 00003c0a R_ARM_THM_CALL 00000000 memset\n+0000043a 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000450 0000380a R_ARM_THM_CALL 00000000 malloc\n+0000046a 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+0000048a 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+000004a0 0000380a R_ARM_THM_CALL 00000000 malloc\n+000004ba 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000004c6 00003a0a R_ARM_THM_CALL 00000000 free\n+000004dc 00003a0a R_ARM_THM_CALL 00000000 free\n+000004ee 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000500 0000380a R_ARM_THM_CALL 00000000 malloc\n+00000516 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000526 00003a0a R_ARM_THM_CALL 00000000 free\n+0000053a 0000380a R_ARM_THM_CALL 00000000 malloc\n+00000558 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+00000562 00003a0a R_ARM_THM_CALL 00000000 free\n+0000056e 0000370a R_ARM_THM_CALL 00000000 _gfortran_string_trim\n+00000586 0000380a R_ARM_THM_CALL 00000000 malloc\n+0000059c 0000390a R_ARM_THM_CALL 00000000 _gfortran_concat_string\n+000005ac 00003a0a R_ARM_THM_CALL 00000000 free\n+000005b6 00003a0a R_ARM_THM_CALL 00000000 free\n+000005e2 00003d0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+000005e8 00003a0a R_ARM_THM_CALL 00000000 free\n+000005f0 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+000005f4 00003f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+000005f8 00000303 R_ARM_REL32 00000000 .LC0\n+000005fc 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000600 00000403 R_ARM_REL32 00000004 .LC1\n+00000604 00000403 R_ARM_REL32 00000004 .LC1\n+00000608 00000703 R_ARM_REL32 00000070 .LC4\n+0000060c 00000803 R_ARM_REL32 00000080 .LC5\n+00000610 00000b03 R_ARM_REL32 000000a8 .LC8\n+00000614 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000618 00000403 R_ARM_REL32 00000004 .LC1\n+0000061c 00000403 R_ARM_REL32 00000004 .LC1\n+00000620 00000a03 R_ARM_REL32 0000009c .LC7\n+00000624 00000803 R_ARM_REL32 00000080 .LC5\n+00000628 00000e03 R_ARM_REL32 000000c4 .LC11\n+0000062c 00000c03 R_ARM_REL32 000000ac .LC9\n+00000630 00000d03 R_ARM_REL32 000000c0 .LC10\n+00000634 0000401a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000638 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000063c 00000f03 R_ARM_REL32 000000c8 .LC12\n+00000640 00000603 R_ARM_REL32 00000054 .LC3\n+00000644 00000503 R_ARM_REL32 0000003c .LC2\n+00000648 00000903 R_ARM_REL32 00000088 .LC6\n+0000064c 00000c03 R_ARM_REL32 000000ac .LC9\n+00000650 00000d03 R_ARM_REL32 000000c0 .LC10\n+00000654 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000764 0000420a R_ARM_THM_CALL 00000000 memmove\n+000007e0 0000420a R_ARM_THM_CALL 00000000 memmove\n+000008fe 0000420a R_ARM_THM_CALL 00000000 memmove\n+0000090a 00003c0a R_ARM_THM_CALL 00000000 memset\n+0000095a 0000420a R_ARM_THM_CALL 00000000 memmove\n+00000966 00003c0a R_ARM_THM_CALL 00000000 memset\n 000009c8 00000103 R_ARM_REL32 00000000 .bss\n 000009cc 00000103 R_ARM_REL32 00000000 .bss\n 000009d0 00000103 R_ARM_REL32 00000000 .bss\n 000009d4 00000103 R_ARM_REL32 00000000 .bss\n 000009d8 00000103 R_ARM_REL32 00000000 .bss\n 000009dc 00000103 R_ARM_REL32 00000000 .bss\n-00000ada 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000ae6 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000afe 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000b12 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000b26 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000b8e 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000ba2 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000bb4 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000c16 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000c20 0000410a R_ARM_THM_CALL 00000000 memset\n-00000c4e 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000c58 0000410a R_ARM_THM_CALL 00000000 memset\n-00000c98 0000460a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_author\n-00000ce2 0000380a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n-00000cf0 0000470a R_ARM_THM_CALL 00000000 memcmp\n-00000d14 0000460a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_author\n-00000d34 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000d38 00003f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00000d3c 00001703 R_ARM_REL32 000000f0 .LC13\n+000009e0 00000103 R_ARM_REL32 00000000 .bss\n+000009e4 00000103 R_ARM_REL32 00000000 .bss\n+000009e8 00000103 R_ARM_REL32 00000000 .bss\n+00000ae8 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000af4 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000b08 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000b1c 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000b30 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000b98 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000baa 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000bbc 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000c1e 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000c28 00003c0a R_ARM_THM_CALL 00000000 memset\n+00000c56 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000c60 00003c0a R_ARM_THM_CALL 00000000 memset\n+00000c84 00003c0a R_ARM_THM_CALL 00000000 memset\n+00000c8e 0000440a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_author\n+00000cba 00003c0a R_ARM_THM_CALL 00000000 memset\n+00000cc8 0000360a R_ARM_THM_CALL 00000000 _gfortran_compare_string\n+00000cd6 0000450a R_ARM_THM_CALL 00000000 memcmp\n+00000cfa 0000440a R_ARM_THM_CALL 00000000 __gridxc_vdwxc_MOD_vdw_set_author\n+00000d18 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000d1c 0000401a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00000d20 00001503 R_ARM_REL32 000000f0 .LC13\n+00000d24 00000103 R_ARM_REL32 00000000 .bss\n+00000d28 00000103 R_ARM_REL32 00000000 .bss\n+00000d2c 00000103 R_ARM_REL32 00000000 .bss\n+00000d30 00000103 R_ARM_REL32 00000000 .bss\n+00000d34 00001603 R_ARM_REL32 0000011c .LC14\n+00000d38 00001703 R_ARM_REL32 00000120 .LC15\n+00000d3c 00001803 R_ARM_REL32 00000124 .LC16\n 00000d40 00000103 R_ARM_REL32 00000000 .bss\n-00000d44 00000103 R_ARM_REL32 00000000 .bss\n+00000d44 00001603 R_ARM_REL32 0000011c .LC14\n 00000d48 00000103 R_ARM_REL32 00000000 .bss\n-00000d4c 00000103 R_ARM_REL32 00000000 .bss\n-00000d50 00001803 R_ARM_REL32 0000011c .LC14\n-00000d54 00001903 R_ARM_REL32 00000120 .LC15\n-00000d58 00001a03 R_ARM_REL32 00000124 .LC16\n+00000d4c 00001903 R_ARM_REL32 00000128 .LC17\n+00000d50 00001703 R_ARM_REL32 00000120 .LC15\n+00000d54 00001803 R_ARM_REL32 00000124 .LC16\n+00000d58 00000103 R_ARM_REL32 00000000 .bss\n 00000d5c 00000103 R_ARM_REL32 00000000 .bss\n-00000d60 00001803 R_ARM_REL32 0000011c .LC14\n-00000d64 00000103 R_ARM_REL32 00000000 .bss\n-00000d68 00001b03 R_ARM_REL32 00000128 .LC17\n-00000d6c 00001903 R_ARM_REL32 00000120 .LC15\n-00000d70 00001a03 R_ARM_REL32 00000124 .LC16\n-00000d74 00000103 R_ARM_REL32 00000000 .bss\n-00000d78 00000103 R_ARM_REL32 00000000 .bss\n-00000d7c 00000103 R_ARM_REL32 00000000 .bss\n-00000d80 00001803 R_ARM_REL32 0000011c .LC14\n-00000d84 00000103 R_ARM_REL32 00000000 .bss\n-00000d88 00001803 R_ARM_REL32 0000011c .LC14\n-00000d8c 00000103 R_ARM_REL32 00000000 .bss\n-00000edc 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000f22 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000f2e 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000f72 0000400a R_ARM_THM_CALL 00000000 memcpy\n-00000f9c 0000420a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00000fa0 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00000fa4 00003e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-00000fa8 00002803 R_ARM_REL32 00000000 .rodata\n-00000fac 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-0000116e 0000320a R_ARM_THM_CALL 00000000 _gfortran_st_write\n-0000117e 0000330a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n-0000118e 0000340a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n-00001194 0000360a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n-000011b4 00004a0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n-000011ba 00004b0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n-000011c4 00004c0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-000011cc 00004d0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-000011f6 00004e0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n-00001344 0000420a R_ARM_THM_CALL 00000000 __stack_chk_fail\n-00001350 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001354 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001358 00003e1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n-0000135c 00000b03 R_ARM_REL32 000000a8 .LC8\n-00001360 00000403 R_ARM_REL32 00000004 .LC1\n-00001364 00000a03 R_ARM_REL32 0000009c .LC7\n-00001368 00000803 R_ARM_REL32 00000080 .LC5\n-0000136c 00003f1a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n-00001370 00002203 R_ARM_REL32 00000178 .LC20\n-00001374 00000e03 R_ARM_REL32 000000c4 .LC11\n-00001378 00002403 R_ARM_REL32 000001b4 .LC22\n-0000137c 00002303 R_ARM_REL32 00000198 .LC21\n-00001380 00002103 R_ARM_REL32 00000160 .LC19\n-00001384 00003d19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n-00001388 00002503 R_ARM_REL32 000001bc .LC23\n-0000138c 00002103 R_ARM_REL32 00000160 .LC19\n-00000280 00003c1e R_ARM_THM_JUMP24 00000000 free\n+00000d60 00000103 R_ARM_REL32 00000000 .bss\n+00000d64 00001603 R_ARM_REL32 0000011c .LC14\n+00000d68 00000103 R_ARM_REL32 00000000 .bss\n+00000d6c 00001603 R_ARM_REL32 0000011c .LC14\n+00000d70 00000103 R_ARM_REL32 00000000 .bss\n+00000ec0 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000f06 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000f12 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000f56 00003b0a R_ARM_THM_CALL 00000000 memcpy\n+00000f80 00003d0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00000f84 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00000f88 00003f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+00000f8c 00002603 R_ARM_REL32 00000000 .rodata\n+00000f90 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+0000115e 0000300a R_ARM_THM_CALL 00000000 _gfortran_st_write\n+0000116e 0000310a R_ARM_THM_CALL 00000000 _gfortran_transfer_character_write\n+0000117e 0000320a R_ARM_THM_CALL 00000000 _gfortran_transfer_integer_write\n+00001184 0000340a R_ARM_THM_CALL 00000000 _gfortran_st_write_done\n+000011a4 0000480a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_init\n+000011aa 0000490a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_get_info\n+000011b4 00004a0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n+000011bc 00004b0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n+000011e4 00004c0a R_ARM_THM_CALL 00000000 __xc_f03_lib_m_MOD_xc_f03_func_end\n+0000132e 00003d0a R_ARM_THM_CALL 00000000 __stack_chk_fail\n+00001340 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001344 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001348 00003f1a R_ARM_GOT_BREL 00000000 __stack_chk_guard\n+0000134c 00002003 R_ARM_REL32 00000178 .LC20\n+00001350 00000b03 R_ARM_REL32 000000a8 .LC8\n+00001354 00000403 R_ARM_REL32 00000004 .LC1\n+00001358 00000a03 R_ARM_REL32 0000009c .LC7\n+0000135c 00000803 R_ARM_REL32 00000080 .LC5\n+00001360 0000401a R_ARM_GOT_BREL 00000000 __gridxc_sys_MOD_die\n+00001364 00000e03 R_ARM_REL32 000000c4 .LC11\n+00001368 00002203 R_ARM_REL32 000001b4 .LC22\n+0000136c 00002103 R_ARM_REL32 00000198 .LC21\n+00001370 00001f03 R_ARM_REL32 00000160 .LC19\n+00001374 00003e19 R_ARM_BASE_PREL 00000000 _GLOBAL_OFFSET_TABLE_\n+00001378 00002303 R_ARM_REL32 000001bc .LC23\n+0000137c 00001f03 R_ARM_REL32 00000160 .LC19\n+0000037e 00003a1e R_ARM_THM_JUMP24 00000000 free\n"}, {"source1": "strings --all --bytes=8 {}", "source2": "strings --all --bytes=8 {}", "unified_diff": "@@ -1,17 +1,17 @@\n ;F2\"1F F\n +F2\"IFPF\n-`:Ked{Dcc2#\n YFKF2\"PF\n YFKF2\"PF\n 2\"YF+FPF\n ;F2\"1F F\n +F2\"IFPF\n F!F2\"8F24\n-|u1F\"F(F\n+{u1F\"F(F\n+=K/\"=L !{D|D\n /build/reproducible-path/libgridxc-2.0.1/src/xcmod.F90\n Cannot get xc_id from \n Conflicting code field for \n (a,i5.5,'-',a)\n Bad libxc code in \n (a,i5.5)\n Family mismatch in \n@@ -34,18 +34,18 @@\n _gfortran_transfer_integer_write\n _gfortran_string_len_trim\n _gfortran_st_write_done\n __xc_f03_lib_m_MOD_xc_f03_family_from_id\n _gfortran_compare_string\n _gfortran_string_trim\n _gfortran_concat_string\n+__stack_chk_fail\n _GLOBAL_OFFSET_TABLE_\n __stack_chk_guard\n __gridxc_sys_MOD_die\n-__stack_chk_fail\n __gridxc_xcmod_MOD_getxc\n __gridxc_xcmod_MOD_setxc\n __gridxc_vdwxc_MOD_vdw_set_author\n __gridxc_xcmod_MOD_setxc_family_authors\n __gridxc_xcmod_MOD_setxc_libxc_ids\n __xc_f03_lib_m_MOD_xc_f03_func_init\n __xc_f03_lib_m_MOD_xc_f03_func_get_info\n"}, {"source1": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "source2": "objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}", "unified_diff": "@@ -8,54 +8,55 @@\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3616]\t@ 0xe20\n \tsub\tsp, #444\t@ 0x1bc\n \tadds\tr6, r1, #6\n \tmov\tr5, r1\n-\tldr\tr1, [pc, #872]\t@ (380 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x380>)\n-\tldr\tr2, [pc, #872]\t@ (384 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x384>)\n+\tldr.w\tr1, [pc, #1496]\t@ 5f0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f0>\n+\tldr.w\tr2, [pc, #1496]\t@ 5f4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f4>\n \tmov.w\tsl, #0\n \tadd\tr1, pc\n \tstr.w\tsl, [sp]\n-\tldr\tr3, [pc, #864]\t@ (388 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x388>)\n+\tldr.w\tr3, [pc, #1484]\t@ 5f8 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f8>\n \tadd\tr4, sp, #40\t@ 0x28\n-\tldr.w\tr8, [pc, #864]\t@ 38c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x38c>\n+\tldr.w\tr8, [pc, #1484]\t@ 5fc <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5fc>\n \tmov\tr7, r0\n \tldr\tr2, [r1, r2]\n \tadd\tr3, pc\n \tmovs\tr0, #44\t@ 0x2c\n \tmov\tr1, r6\n \tldr\tr2, [r2, #0]\n \tstr\tr2, [sp, #436]\t@ 0x1b4\n \tmov.w\tr2, #0\n \tmovs\tr2, #1\n \tbl\t0 <_gfortran_string_index>\n R_ARM_THM_CALL\t_gfortran_string_index\n \tadd\tr8, pc\n \tmov\tr9, r0\n-\tvldr\td16, [pc, #804]\t@ 370 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x370>\n \tstr\tr6, [r4, #68]\t@ 0x44\n \tcmp\tr0, #0\n-\tbeq.w\t284 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x284>\n+\tbeq.w\t1ba <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x1ba>\n \tadd\tr3, sp, #16\n \tstr\tr3, [r4, #24]\n \tsubs\tr3, r0, #1\n \tstr.w\tsl, [r4, #48]\t@ 0x30\n \tmov\tr0, r4\n \tadd\tr6, sp, #20\n \tbic.w\tr3, r3, r3, asr #31\n \tstr\tr3, [r4, #72]\t@ 0x48\n-\tldr\tr3, [pc, #804]\t@ (390 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x390>)\n+\tldr.w\tr3, [pc, #1428]\t@ 600 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x600>\n+\tmovw\tr2, #16544\t@ 0x40a0\n \tstr.w\tsl, [sp, #16]\n \tadd\tr3, pc\n \tstr\tr3, [r4, #8]\n \tmovw\tr3, #269\t@ 0x10d\n \tstr\tr3, [r4, #12]\n-\tvstr\td16, [sp, #40]\t@ 0x28\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #40]\t@ 0x28\n \tbl\t0 <_gfortran_st_read>\n R_ARM_THM_CALL\t_gfortran_st_read\n \tmov\tr1, r6\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_transfer_integer>\n R_ARM_THM_CALL\t_gfortran_transfer_integer\n@@ -63,62 +64,64 @@\n \tbl\t0 <_gfortran_st_read_done>\n R_ARM_THM_CALL\t_gfortran_st_read_done\n \tadd.w\tr1, r9, #6\n \trsb\tr3, r9, #43\t@ 0x2b\n \tadd\tr1, r5\n \tadd.w\tr9, r9, #7\n \tcmp\tr3, #48\t@ 0x30\n-\tble.w\t442 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x442>\n+\tble.w\t406 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x406>\n \tadd.w\tr9, sp, #384\t@ 0x180\n \tmov\tip, r1\n \tmov\tsl, r9\n \tadd.w\tfp, r1, #48\t@ 0x30\n \tmov\tlr, sl\n \tldr.w\tr0, [ip]\n \tldr.w\tr1, [ip, #4]\n \tadd.w\tip, ip, #16\n \tldr.w\tr2, [ip, #-8]\n \tadd.w\tsl, sl, #16\n \tldr.w\tr3, [ip, #-4]\n \tcmp\tip, fp\n \tstmia.w\tlr!, {r0, r1, r2, r3}\n-\tbne.n\tb0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xb0>\n+\tbne.n\tbc <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xbc>\n \tldrh.w\tr3, [ip]\n \tstrh.w\tr3, [sl]\n \tmovs\tr1, #50\t@ 0x32\n \tmov\tr0, r9\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_functional_get_number>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_functional_get_number\n \tldr\tr3, [r6, #0]\n \tcmp\tr3, #0\n-\tbne.w\t3d0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3d0>\n+\tbne.w\t394 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x394>\n \tcmp\tr0, #0\n-\tblt.w\t466 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x466>\n-\tstr\tr0, [r6, #0]\n-\tldr\tr3, [pc, #672]\t@ (394 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x394>)\n+\tit\tge\n+\tstrge\tr0, [r6, #0]\n+\tblt.w\t42a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x42a>\n+\tldr.w\tr3, [pc, #1280]\t@ 604 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x604>\n \tmov\tr0, r4\n-\tvldr\td16, [pc, #640]\t@ 378 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x378>\n \tmov.w\tsl, #50\t@ 0x32\n-\tadd\tr3, pc\n-\tstr\tr3, [r4, #8]\n-\tldr\tr3, [pc, #660]\t@ (398 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x398>)\n \tstr\tr5, [r4, #68]\t@ 0x44\n \tadd\tr3, pc\n+\tstr\tr3, [r4, #8]\n+\tldr.w\tr3, [pc, #1268]\t@ 608 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x608>\n+\tmov.w\tr2, #20480\t@ 0x5000\n \tstr.w\tsl, [r4, #72]\t@ 0x48\n+\tadd\tr3, pc\n \tstr\tr3, [r4, #52]\t@ 0x34\n \tmov.w\tr3, #294\t@ 0x126\n \tstr\tr3, [r4, #12]\n \tmovs\tr3, #0\n \tstr\tr3, [r4, #48]\t@ 0x30\n \tmovs\tr3, #14\n \tstr\tr3, [r4, #56]\t@ 0x38\n-\tvstr\td16, [sp, #40]\t@ 0x28\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #40]\t@ 0x28\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #628]\t@ (39c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x39c>)\n+\tldr.w\tr1, [pc, #1232]\t@ 60c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x60c>\n \tmovs\tr2, #6\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n \tmovs\tr2, #4\n \tmov\tr1, r6\n@@ -139,24 +142,119 @@\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tmovs\tr2, #0\n \tmov\tr0, r6\n \tmov\tr1, r2\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_family_from_id>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_family_from_id\n \tcmp\tr0, #2\n-\tbne.w\t31e <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x31e>\n-\tldr\tr3, [pc, #568]\t@ (3a0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3a0>)\n+\tbeq.n\t264 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x264>\n+\tcmp\tr0, #32\n+\tbeq.n\t264 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x264>\n+\tcmp\tr0, #1\n+\tbne.w\t382 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x382>\n+\tldr.w\tr3, [pc, #1160]\t@ 610 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x610>\n+\tmovs\tr2, #3\n+\tmov\tr1, r7\n+\tmovs\tr0, #50\t@ 0x32\n+\tadd\tr3, pc\n+\tbl\t0 <_gfortran_compare_string>\n+ R_ARM_THM_CALL\t_gfortran_compare_string\n+\tcmp\tr0, #0\n+\tbne.w\t4e2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x4e2>\n+\tldr.w\tr2, [pc, #1144]\t@ 614 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x614>\n+\tldr.w\tr3, [pc, #1108]\t@ 5f4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f4>\n+\tadd\tr2, pc\n+\tldr\tr3, [r2, r3]\n+\tldr\tr2, [r3, #0]\n+\tldr\tr3, [sp, #436]\t@ 0x1b4\n+\teors\tr2, r3\n+\tmov.w\tr3, #0\n+\tbne.w\t5e2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5e2>\n+\tadd\tsp, #444\t@ 0x1bc\n+\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n+\tldr.w\tr3, [pc, #1116]\t@ 618 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x618>\n+\tadd.w\tsl, sp, #16\n+\tstr\tr0, [r4, #48]\t@ 0x30\n+\tadd\tr6, sp, #20\n+\tadd\tr3, pc\n+\tstr\tr0, [sp, #16]\n+\tstr\tr3, [r4, #8]\n+\tmov\tr0, r4\n+\tmovs\tr3, #44\t@ 0x2c\n+\tstr.w\tsl, [r4, #24]\n+\tstr\tr3, [r4, #72]\t@ 0x48\n+\tmovw\tr3, #297\t@ 0x129\n+\tstr\tr3, [r4, #12]\n+\tmovw\tr2, #16544\t@ 0x40a0\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #40]\t@ 0x28\n+\tbl\t0 <_gfortran_st_read>\n+ R_ARM_THM_CALL\t_gfortran_st_read\n+\tmovs\tr2, #4\n+\tmov\tr1, r6\n+\tmov\tr0, r4\n+\tbl\t0 <_gfortran_transfer_integer>\n+ R_ARM_THM_CALL\t_gfortran_transfer_integer\n+\tmov\tr0, r4\n+\tbl\t0 <_gfortran_st_read_done>\n+ R_ARM_THM_CALL\t_gfortran_st_read_done\n+\tldr\tr3, [sp, #16]\n+\tcmp\tr3, #0\n+\tbne.w\t47a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x47a>\n+\tldr.w\tr3, [pc, #1044]\t@ 61c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x61c>\n+\tmov\tr0, r4\n+\tstr\tr5, [r4, #68]\t@ 0x44\n+\tmov.w\tr2, #20480\t@ 0x5000\n+\tadd\tr3, pc\n+\tstr\tr3, [r4, #8]\n+\tldr.w\tr3, [pc, #1032]\t@ 620 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x620>\n+\tadd\tr3, pc\n+\tstr\tr3, [r4, #52]\t@ 0x34\n+\tmovs\tr3, #50\t@ 0x32\n+\tstr\tr3, [r4, #72]\t@ 0x48\n+\tmovs\tr3, #0\n+\tstr\tr3, [r4, #48]\t@ 0x30\n+\tmovs\tr3, #8\n+\tstr\tr3, [r4, #56]\t@ 0x38\n+\tmovw\tr3, #301\t@ 0x12d\n+\tstr\tr3, [r4, #12]\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [sp, #40]\t@ 0x28\n+\tbl\t0 <_gfortran_st_write>\n+ R_ARM_THM_CALL\t_gfortran_st_write\n+\tldr\tr1, [pc, #1000]\t@ (624 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x624>)\n+\tmovs\tr2, #6\n+\tmov\tr0, r4\n+\tadd\tr1, pc\n+\tbl\t0 <_gfortran_transfer_character_write>\n+ R_ARM_THM_CALL\t_gfortran_transfer_character_write\n+\tmovs\tr2, #4\n+\tmov\tr1, r6\n+\tmov\tr0, r4\n+\tbl\t0 <_gfortran_transfer_integer_write>\n+ R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n+\tmov\tr0, r4\n+\tbl\t0 <_gfortran_st_write_done>\n+ R_ARM_THM_CALL\t_gfortran_st_write_done\n+\tmovs\tr2, #0\n+\tmov\tr0, r6\n+\tmov\tr1, r2\n+\tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_family_from_id>\n+ R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_family_from_id\n+\tcmp\tr0, #2\n+\tbne.n\t17a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x17a>\n+\tldr\tr3, [pc, #960]\t@ (628 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x628>)\n \tmovs\tr2, #3\n \tmov\tr1, r7\n \tmovs\tr0, #50\t@ 0x32\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\t33c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x33c>\n+\tbeq.n\t19a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x19a>\n \tadd\tr4, sp, #32\n \tadd\tr6, sp, #36\t@ 0x24\n \tmov\tr3, r7\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr1, r6\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_string_trim>\n@@ -168,37 +266,37 @@\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [sp, #4]\n \tmovs\tr2, #19\n-\tldr\tr3, [pc, #512]\t@ (3a4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3a4>)\n+\tldr\tr3, [pc, #908]\t@ (62c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x62c>)\n \tstr\tr7, [sp, #0]\n \tmov\tr7, r0\n \tadd\tr3, pc\n \tmov\tr0, r9\n \tmov\tr1, r7\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr.w\tr9, [r4]\n \tcmp.w\tr9, #0\n-\tble.n\t1c4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x1c4>\n+\tble.n\t2c2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x2c2>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr9, [r4]\n \tadd.w\tsl, r9, #20\n \tmov\tr0, sl\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #464]\t@ (3a8 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3a8>)\n+\tldr\tr3, [pc, #860]\t@ (630 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x630>)\n \tmov\tr6, r0\n \tadd.w\tr2, r9, #19\n \tmov\tr0, sl\n \tmov\tr1, r6\n \tadd\tr3, pc\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #1\n@@ -235,192 +333,54 @@\n \tstr\tr3, [sp, #4]\n \tmov\tr1, r5\n \tmov\tr3, r6\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr.w\tr7, [sl]\n \tcmp\tr7, #0\n-\tble.n\t24a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x24a>\n+\tble.n\t348 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x348>\n \tldr.w\tr0, [r9]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr7, [sl]\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #344]\t@ (3ac <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3ac>)\n+\tldr\tr2, [pc, #740]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n \tldr\tr3, [r4, #0]\n \tmov\tr0, r5\n \tadds\tr3, #20\n \tldr.w\tr2, [r8, r2]\n \tadds\tr1, r3, r7\n \tldr\tr3, [r2, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #332]\t@ (3b0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3b0>)\n-\tldr\tr3, [pc, #284]\t@ (384 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x384>)\n+\tldr\tr2, [pc, #724]\t@ (638 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x638>)\n+\tldr\tr3, [pc, #656]\t@ (5f4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #436]\t@ 0x1b4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.w\t61e <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x61e>\n+\tbne.w\t5e2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5e2>\n \tmov\tr0, r5\n \tadd\tsp, #444\t@ 0x1bc\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tb.w\t0 \n R_ARM_THM_JUMP24\tfree\n-\tldr\tr3, [pc, #300]\t@ (3b4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3b4>)\n-\tadd.w\tsl, sp, #16\n-\tstr\tr0, [r4, #48]\t@ 0x30\n-\tadd\tr6, sp, #20\n-\tadd\tr3, pc\n-\tstr\tr0, [sp, #16]\n-\tstr\tr3, [r4, #8]\n-\tmov\tr0, r4\n-\tmovs\tr3, #44\t@ 0x2c\n-\tstr.w\tsl, [r4, #24]\n-\tstr\tr3, [r4, #72]\t@ 0x48\n-\tmovw\tr3, #297\t@ 0x129\n-\tstr\tr3, [r4, #12]\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tbl\t0 <_gfortran_st_read>\n- R_ARM_THM_CALL\t_gfortran_st_read\n-\tmovs\tr2, #4\n-\tmov\tr1, r6\n-\tmov\tr0, r4\n-\tbl\t0 <_gfortran_transfer_integer>\n- R_ARM_THM_CALL\t_gfortran_transfer_integer\n-\tmov\tr0, r4\n-\tbl\t0 <_gfortran_st_read_done>\n- R_ARM_THM_CALL\t_gfortran_st_read_done\n-\tldr\tr3, [sp, #16]\n-\tcmp\tr3, #0\n-\tbne.w\t4b6 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x4b6>\n-\tldr\tr3, [pc, #240]\t@ (3b8 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3b8>)\n-\tmov\tr0, r4\n-\tvldr\td16, [pc, #172]\t@ 378 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x378>\n-\tadd\tr3, pc\n-\tstr\tr3, [r4, #8]\n-\tldr\tr3, [pc, #232]\t@ (3bc <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3bc>)\n-\tstr\tr5, [r4, #68]\t@ 0x44\n-\tadd\tr3, pc\n-\tstr\tr3, [r4, #52]\t@ 0x34\n-\tmovs\tr3, #50\t@ 0x32\n-\tstr\tr3, [r4, #72]\t@ 0x48\n-\tmovs\tr3, #0\n-\tstr\tr3, [r4, #48]\t@ 0x30\n-\tmovs\tr3, #8\n-\tstr\tr3, [r4, #56]\t@ 0x38\n-\tmovw\tr3, #301\t@ 0x12d\n-\tstr\tr3, [r4, #12]\n-\tvstr\td16, [sp, #40]\t@ 0x28\n-\tbl\t0 <_gfortran_st_write>\n- R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #204]\t@ (3c0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3c0>)\n-\tmovs\tr2, #6\n-\tmov\tr0, r4\n-\tadd\tr1, pc\n-\tbl\t0 <_gfortran_transfer_character_write>\n- R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tmovs\tr2, #4\n-\tmov\tr1, r6\n-\tmov\tr0, r4\n-\tbl\t0 <_gfortran_transfer_integer_write>\n- R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n-\tmov\tr0, r4\n-\tbl\t0 <_gfortran_st_write_done>\n- R_ARM_THM_CALL\t_gfortran_st_write_done\n-\tmovs\tr2, #0\n-\tmov\tr0, r6\n-\tmov\tr1, r2\n-\tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_family_from_id>\n- R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_family_from_id\n-\tcmp\tr0, #2\n-\tbeq.w\t164 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x164>\n-\tcmp\tr0, #32\n-\tbeq.w\t164 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x164>\n-\tcmp\tr0, #1\n-\tbne.n\t358 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x358>\n-\tldr\tr3, [pc, #152]\t@ (3c4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3c4>)\n-\tmovs\tr2, #3\n-\tmov\tr1, r7\n-\tmovs\tr0, #50\t@ 0x32\n-\tadd\tr3, pc\n-\tbl\t0 <_gfortran_compare_string>\n- R_ARM_THM_CALL\t_gfortran_compare_string\n-\tcmp\tr0, #0\n-\tbne.w\t51e <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x51e>\n-\tldr\tr2, [pc, #136]\t@ (3c8 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3c8>)\n-\tldr\tr3, [pc, #68]\t@ (384 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x384>)\n-\tadd\tr2, pc\n-\tldr\tr3, [r2, r3]\n-\tldr\tr2, [r3, #0]\n-\tldr\tr3, [sp, #436]\t@ 0x1b4\n-\teors\tr2, r3\n-\tmov.w\tr3, #0\n-\tbne.w\t61e <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x61e>\n-\tadd\tsp, #444\t@ 0x1bc\n-\tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #80]\t@ (3ac <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3ac>)\n+\tldr\tr3, [pc, #688]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n \tmovs\tr1, #38\t@ 0x26\n-\tldr\tr0, [pc, #108]\t@ (3cc <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3cc>)\n+\tldr\tr0, [pc, #692]\t@ (63c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x63c>)\n \tadd\tr0, pc\n \tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t33c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x33c>\n-\tnop\n-\tnop.w\n-\t.word\t0x000040a0\n-\t.word\t0xffffffff\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x0000035e\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x00000354\n- R_ARM_REL32\t.LC0\n-\t.word\t0x00000344\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000031e\n- R_ARM_REL32\t.LC1\n-\t.word\t0x00000292\n- R_ARM_REL32\t.LC1\n-\t.word\t0x0000028e\n- R_ARM_REL32\t.LC4\n-\t.word\t0x0000026e\n- R_ARM_REL32\t.LC5\n-\t.word\t0x00000230\n- R_ARM_REL32\t.LC11\n-\t.word\t0x000001fa\n- R_ARM_REL32\t.LC9\n-\t.word\t0x000001c4\n- R_ARM_REL32\t.LC10\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000146\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000122\n- R_ARM_REL32\t.LC1\n-\t.word\t0x000000e8\n- R_ARM_REL32\t.LC1\n-\t.word\t0x000000e4\n- R_ARM_REL32\t.LC7\n-\t.word\t0x000000c4\n- R_ARM_REL32\t.LC5\n-\t.word\t0x00000090\n- R_ARM_REL32\t.LC8\n-\t.word\t0x00000084\n- R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x0000006a\n- R_ARM_REL32\t.LC12\n+\tb.n\t19a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x19a>\n \tcmp\tr0, r3\n-\tbeq.w\tf2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xf2>\n+\tbeq.w\t100 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x100>\n \tadd.w\tfp, sp, #36\t@ 0x24\n \tadd.w\tsl, sp, #32\n \tmov\tr1, fp\n \tmov\tr3, r9\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_string_trim>\n@@ -438,51 +398,51 @@\n \tldr\tr3, [sp, #12]\n \tldr\tr2, [sp, #8]\n \tmov\tr1, r0\n \tstr\tr0, [sp, #8]\n \tmov\tr0, r3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [pc, #540]\t@ (62c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x62c>)\n+\tldr\tr3, [pc, #620]\t@ (640 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x640>)\n \tstr\tr2, [sp, #0]\n \tmovs\tr2, #27\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr\tr1, [sp, #32]\n \tcmp\tr1, #0\n-\tble.n\t428 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x428>\n+\tble.n\t3ec <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3ec>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr1, [sp, #32]\n \tadds\tr1, #27\n-\tldr\tr3, [pc, #516]\t@ (630 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x630>)\n+\tldr\tr3, [pc, #580]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n \tldr.w\tsl, [sp, #8]\n \tmov\tr0, sl\n \tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, sl\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\tf2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xf2>\n+\tb.n\t100 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x100>\n \trsb\tsl, r9, #51\t@ 0x33\n \tadd.w\tr9, sp, #384\t@ 0x180\n \tmov\tr0, r9\n \tbic.w\tsl, sl, sl, asr #31\n \tmov\tr2, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tmovs\tr1, #32\n \trsb\tr2, sl, #50\t@ 0x32\n \tadd.w\tr0, r9, sl\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n-\tb.n\tda <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xda>\n+\tb.n\te6 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0xe6>\n \tadd.w\tfp, sp, #36\t@ 0x24\n \tadd.w\tsl, sp, #32\n \tmov\tr1, fp\n \tmov\tr3, r9\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_string_trim>\n@@ -500,25 +460,25 @@\n \tldr\tr3, [sp, #12]\n \tldr\tr2, [sp, #8]\n \tmov\tr1, r0\n \tstr\tr0, [sp, #8]\n \tmov\tr0, r3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [pc, #404]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n+\tldr\tr3, [pc, #480]\t@ (644 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x644>)\n \tstr\tr2, [sp, #0]\n \tmovs\tr2, #22\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr\tr1, [sp, #32]\n \tcmp\tr1, #0\n-\tbgt.w\t622 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x622>\n+\tbgt.w\t5e6 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5e6>\n \tadds\tr1, #22\n-\tb.n\t42a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x42a>\n+\tb.n\t3ee <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x3ee>\n \tadd.w\tfp, sp, #36\t@ 0x24\n \tadd.w\tsl, sp, #32\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr1, fp\n \tmov\tr3, r5\n \tmov\tr0, sl\n \tbl\t0 <_gfortran_string_trim>\n@@ -535,36 +495,36 @@\n \tldr\tr3, [sp, #8]\n \tstr.w\tr9, [sp]\n \tmov\tr9, r0\n \tmov\tr0, r3\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [sp, #4]\n \tmov\tr1, r9\n-\tldr\tr3, [pc, #324]\t@ (638 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x638>)\n+\tldr\tr3, [pc, #400]\t@ (648 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x648>)\n \tmovs\tr2, #18\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr\tr1, [sp, #32]\n \tcmp\tr1, #0\n-\tble.n\t508 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x508>\n+\tble.n\t4cc <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x4cc>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr1, [sp, #32]\n-\tldr\tr3, [pc, #292]\t@ (630 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x630>)\n+\tldr\tr3, [pc, #356]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n \tmov\tr0, r9\n \tadds\tr1, #18\n \tldr.w\tr3, [r8, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tmov\tr0, r9\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tb.n\t2c4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x2c4>\n+\tb.n\t204 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x204>\n \tadd\tr4, sp, #32\n \tadd\tr6, sp, #36\t@ 0x24\n \tmov\tr3, r7\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr1, r6\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_string_trim>\n@@ -576,37 +536,37 @@\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n \tldr\tr3, [sp, #36]\t@ 0x24\n \tstr\tr3, [sp, #4]\n \tmovs\tr2, #19\n-\tldr\tr3, [pc, #244]\t@ (63c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x63c>)\n+\tldr\tr3, [pc, #320]\t@ (64c <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x64c>)\n \tstr\tr7, [sp, #0]\n \tmov\tr7, r0\n \tadd\tr3, pc\n \tmov\tr0, r9\n \tmov\tr1, r7\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr.w\tr9, [r4]\n \tcmp.w\tr9, #0\n-\tble.n\t56a <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x56a>\n+\tble.n\t52e <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x52e>\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr9, [r4]\n \tadd.w\tsl, r9, #20\n \tmov\tr0, sl\n \tcmp\tr0, #1\n \tit\tcc\n \tmovcc\tr0, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmalloc\n-\tldr\tr3, [pc, #196]\t@ (640 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x640>)\n+\tldr\tr3, [pc, #272]\t@ (650 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x650>)\n \tmov\tr6, r0\n \tadd.w\tr2, r9, #19\n \tmov\tr0, sl\n \tmov\tr1, r6\n \tadd\tr3, pc\n \tstr\tr3, [sp, #4]\n \tmovs\tr3, #1\n@@ -643,202 +603,238 @@\n \tstr\tr3, [sp, #4]\n \tmov\tr1, r5\n \tmov\tr3, r6\n \tbl\t0 <_gfortran_concat_string>\n R_ARM_THM_CALL\t_gfortran_concat_string\n \tldr.w\tr7, [sl]\n \tcmp\tr7, #0\n-\tble.n\t5f0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f0>\n+\tble.n\t5b4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5b4>\n \tldr.w\tr0, [r9]\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr.w\tr7, [sl]\n \tmov\tr0, r6\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n-\tldr\tr2, [pc, #56]\t@ (630 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x630>)\n+\tldr\tr2, [pc, #120]\t@ (634 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x634>)\n \tldr\tr3, [r4, #0]\n \tmov\tr0, r5\n \tadds\tr3, #20\n \tldr.w\tr2, [r8, r2]\n \tadds\tr1, r3, r7\n \tldr\tr3, [r2, #0]\n \tblx\tr3\n-\tldr\tr2, [pc, #56]\t@ (644 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x644>)\n-\tldr\tr3, [pc, #60]\t@ (648 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x648>)\n+\tldr\tr2, [pc, #132]\t@ (654 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x654>)\n+\tldr\tr3, [pc, #36]\t@ (5f4 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x5f4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [sp, #436]\t@ 0x1b4\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbeq.w\t278 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x278>\n+\tbeq.w\t376 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x376>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \tldr\tr0, [sp, #36]\t@ 0x24\n \tbl\t0 \n R_ARM_THM_CALL\tfree\n \tldr\tr1, [sp, #32]\n-\tb.n\t4b2 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x4b2>\n-\t.word\t0x00000214\n- R_ARM_REL32\t.LC3\n+\tb.n\t476 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0+0x476>\n+\t.word\t0x000005ca\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000000\n+ R_ARM_GOT32\t__stack_chk_guard\n+\t.word\t0x000005be\n+ R_ARM_REL32\t.LC0\n+\t.word\t0x000005ae\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x00000586\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x000004f4\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x000004e8\n+ R_ARM_REL32\t.LC4\n+\t.word\t0x000004c6\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x0000047e\n+ R_ARM_REL32\t.LC8\n+\t.word\t0x0000046e\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x0000044e\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000408\n+ R_ARM_REL32\t.LC1\n+\t.word\t0x00000404\n+ R_ARM_REL32\t.LC7\n+\t.word\t0x000003e0\n+ R_ARM_REL32\t.LC5\n+\t.word\t0x000003b8\n+ R_ARM_REL32\t.LC11\n+\t.word\t0x00000384\n+ R_ARM_REL32\t.LC9\n+\t.word\t0x0000034e\n+ R_ARM_REL32\t.LC10\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x0000018c\n+\t.word\t0x000002d0\n+ R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n+\t.word\t0x000002b0\n+ R_ARM_REL32\t.LC12\n+\t.word\t0x00000264\n+ R_ARM_REL32\t.LC3\n+\t.word\t0x000001d8\n R_ARM_REL32\t.LC2\n-\t.word\t0x00000140\n+\t.word\t0x0000018c\n R_ARM_REL32\t.LC6\n-\t.word\t0x000000ec\n+\t.word\t0x00000138\n R_ARM_REL32\t.LC9\n-\t.word\t0x000000b6\n+\t.word\t0x00000102\n R_ARM_REL32\t.LC10\n-\t.word\t0x00000034\n+\t.word\t0x00000080\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000000\n- R_ARM_GOT32\t__stack_chk_guard\n \n-0000064c <__gridxc_xcmod_MOD_getxc>:\n+00000658 <__gridxc_xcmod_MOD_getxc>:\n __gridxc_xcmod_MOD_getxc():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4016]\t@ 0xfb0\n \tsub\tsp, #44\t@ 0x2c\n \tstr\tr0, [sp, #0]\n \tmov\tr0, r1\n \tldr\tr4, [sp, #80]\t@ 0x50\n-\tcbz\tr1, 68c <__gridxc_xcmod_MOD_getxc+0x40>\n+\tcbz\tr1, 698 <__gridxc_xcmod_MOD_getxc+0x40>\n \tldr\tr1, [r1, #0]\n-\tcbz\tr1, 68c <__gridxc_xcmod_MOD_getxc+0x40>\n+\tcbz\tr1, 698 <__gridxc_xcmod_MOD_getxc+0x40>\n \tldr.w\tr9, [r0, #24]\n \trsb\tfp, r9, #0\n \tcmp.w\tr9, #0\n-\tbne.n\t680 <__gridxc_xcmod_MOD_getxc+0x34>\n+\tbne.n\t68c <__gridxc_xcmod_MOD_getxc+0x34>\n \tmov.w\tfp, #4294967295\t@ 0xffffffff\n \tmov.w\tr9, #1\n \tldrd\tr0, sl, [r0, #28]\n \tsub.w\tsl, sl, r0\n \tadd.w\tsl, sl, #1\n \tmov\tr0, r2\n-\tcbz\tr2, 6b2 <__gridxc_xcmod_MOD_getxc+0x66>\n+\tcbz\tr2, 6be <__gridxc_xcmod_MOD_getxc+0x66>\n \tldr\tr0, [r2, #0]\n-\tcbz\tr0, 6b2 <__gridxc_xcmod_MOD_getxc+0x66>\n+\tcbz\tr0, 6be <__gridxc_xcmod_MOD_getxc+0x66>\n \tldr.w\tip, [r2, #24]\n \tcmp.w\tip, #0\n-\tbeq.w\t886 <__gridxc_xcmod_MOD_getxc+0x23a>\n+\tbeq.w\t892 <__gridxc_xcmod_MOD_getxc+0x23a>\n \trsb\tr7, ip, #0\n \tstr\tr7, [sp, #20]\n \tldrd\tr2, lr, [r2, #28]\n \tsub.w\tlr, lr, r2\n \tadd.w\tlr, lr, #1\n \tmov\tr8, r3\n-\tcbz\tr3, 6d6 <__gridxc_xcmod_MOD_getxc+0x8a>\n+\tcbz\tr3, 6e2 <__gridxc_xcmod_MOD_getxc+0x8a>\n \tldr.w\tr8, [r3]\n \tcmp.w\tr8, #0\n-\tbeq.n\t6d6 <__gridxc_xcmod_MOD_getxc+0x8a>\n+\tbeq.n\t6e2 <__gridxc_xcmod_MOD_getxc+0x8a>\n \tldr\tr6, [r3, #24]\n \tcmp\tr6, #0\n-\tbeq.w\t89c <__gridxc_xcmod_MOD_getxc+0x250>\n+\tbeq.w\t8a8 <__gridxc_xcmod_MOD_getxc+0x250>\n \tnegs\tr2, r6\n \tstr\tr2, [sp, #16]\n \tldrd\tr3, r2, [r3, #28]\n \tsubs\tr2, r2, r3\n \tadds\tr3, r2, #1\n \tstr\tr3, [sp, #4]\n \tmov\tr2, r4\n-\tcbz\tr4, 6f4 <__gridxc_xcmod_MOD_getxc+0xa8>\n+\tcbz\tr4, 700 <__gridxc_xcmod_MOD_getxc+0xa8>\n \tldr\tr2, [r4, #0]\n-\tcbz\tr2, 6f4 <__gridxc_xcmod_MOD_getxc+0xa8>\n+\tcbz\tr2, 700 <__gridxc_xcmod_MOD_getxc+0xa8>\n \tldr\tr5, [r4, #24]\n \tcmp\tr5, #0\n-\tbeq.w\t892 <__gridxc_xcmod_MOD_getxc+0x246>\n+\tbeq.w\t89e <__gridxc_xcmod_MOD_getxc+0x246>\n \tnegs\tr3, r5\n \tstr\tr3, [sp, #12]\n \tldrd\tr4, r3, [r4, #28]\n \tsubs\tr3, r3, r4\n \tadds\tr3, #1\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [pc, #708]\t@ (9bc <__gridxc_xcmod_MOD_getxc+0x370>)\n+\tldr\tr3, [pc, #708]\t@ (9c8 <__gridxc_xcmod_MOD_getxc+0x370>)\n \tadd\tr3, pc\n \tldr\tr4, [r3, #0]\n \tldr\tr3, [sp, #0]\n-\tcbz\tr3, 700 <__gridxc_xcmod_MOD_getxc+0xb4>\n+\tcbz\tr3, 70c <__gridxc_xcmod_MOD_getxc+0xb4>\n \tstr\tr4, [r3, #0]\n \tcmp\tr1, #0\n-\tbeq.w\t832 <__gridxc_xcmod_MOD_getxc+0x1e6>\n+\tbeq.w\t83e <__gridxc_xcmod_MOD_getxc+0x1e6>\n \tbic.w\tsl, sl, sl, asr #31\n \tcmp\tsl, r4\n-\tbge.n\t78e <__gridxc_xcmod_MOD_getxc+0x142>\n+\tbge.n\t79a <__gridxc_xcmod_MOD_getxc+0x142>\n \tcmp\tr0, #0\n-\tbeq.w\t8b4 <__gridxc_xcmod_MOD_getxc+0x268>\n+\tbeq.w\t8c0 <__gridxc_xcmod_MOD_getxc+0x268>\n \tbic.w\tr3, lr, lr, asr #31\n \tcmp\tr4, r3\n-\tbgt.w\t83e <__gridxc_xcmod_MOD_getxc+0x1f2>\n+\tbgt.w\t84a <__gridxc_xcmod_MOD_getxc+0x1f2>\n \tldr\tr3, [sp, #88]\t@ 0x58\n \tcmp\tr3, #0\n-\tble.n\t76a <__gridxc_xcmod_MOD_getxc+0x11e>\n+\tble.n\t776 <__gridxc_xcmod_MOD_getxc+0x11e>\n \tmov\tr1, r3\n \tcmp\tr3, #50\t@ 0x32\n \tldr\tr3, [sp, #20]\n \tadd\tr3, ip\n-\tbgt.w\t91e <__gridxc_xcmod_MOD_getxc+0x2d2>\n-\tldr.w\tsl, [pc, #652]\t@ 9c0 <__gridxc_xcmod_MOD_getxc+0x374>\n+\tbgt.w\t92a <__gridxc_xcmod_MOD_getxc+0x2d2>\n+\tldr.w\tsl, [pc, #652]\t@ 9cc <__gridxc_xcmod_MOD_getxc+0x374>\n \tmla\tr3, r1, r3, r0\n \tmul.w\tr7, r1, ip\n \tstr\tr5, [sp, #0]\n \tadd\tsl, pc\n \tmov.w\tr9, #1\n-\tadd.w\tsl, sl, #1008\t@ 0x3f0\n+\tadd.w\tsl, sl, #1004\t@ 0x3ec\n \tmov\tfp, r1\n \tmov\tr5, sl\n \tmov\tsl, r2\n \tmov\tr1, r5\n \tmov\tr0, r3\n \tmov\tr2, fp\n \tadd.w\tr9, r9, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tmov\tr3, r0\n \tadd\tr3, r7\n \tadds\tr5, #50\t@ 0x32\n \tcmp\tr4, r9\n-\tbge.n\t74e <__gridxc_xcmod_MOD_getxc+0x102>\n+\tbge.n\t75a <__gridxc_xcmod_MOD_getxc+0x102>\n \tldr\tr5, [sp, #0]\n \tmov\tr2, sl\n \tcmp.w\tr8, #0\n-\tbeq.n\t7f6 <__gridxc_xcmod_MOD_getxc+0x1aa>\n+\tbeq.n\t802 <__gridxc_xcmod_MOD_getxc+0x1aa>\n \tldr\tr3, [sp, #4]\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r4\n-\tbge.w\t8a6 <__gridxc_xcmod_MOD_getxc+0x25a>\n-\tcbz\tr2, 788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbge.w\t8b2 <__gridxc_xcmod_MOD_getxc+0x25a>\n+\tcbz\tr2, 794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tldr\tr3, [sp, #8]\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r4\n-\tbge.n\t808 <__gridxc_xcmod_MOD_getxc+0x1bc>\n+\tbge.n\t814 <__gridxc_xcmod_MOD_getxc+0x1bc>\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tcmp\tr4, #0\n-\tble.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tble.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tldr\tr3, [sp, #84]\t@ 0x54\n \tcmp\tr3, #0\n-\tble.n\t7ec <__gridxc_xcmod_MOD_getxc+0x1a0>\n+\tble.n\t7f8 <__gridxc_xcmod_MOD_getxc+0x1a0>\n \tmov\tr7, r3\n \tcmp\tr3, #50\t@ 0x32\n \tadd.w\tr3, r9, fp\n-\tbgt.w\t8bc <__gridxc_xcmod_MOD_getxc+0x270>\n+\tbgt.w\t8c8 <__gridxc_xcmod_MOD_getxc+0x270>\n \tmla\tr3, r7, r3, r1\n \tmov\tr1, r7\n \tmul.w\tr9, r7, r9\n-\tldr\tr7, [pc, #532]\t@ (9c4 <__gridxc_xcmod_MOD_getxc+0x378>)\n+\tldr\tr7, [pc, #532]\t@ (9d0 <__gridxc_xcmod_MOD_getxc+0x378>)\n \tmov.w\tsl, #50\t@ 0x32\n \tstrd\tr8, r2, [sp, #24]\n \tadd\tr7, pc\n \tstr\tr4, [sp, #32]\n-\tadds\tr7, #8\n+\tadds\tr7, #4\n \tmov\tfp, lr\n \tmov\tr8, r1\n \tstr\tr0, [sp, #0]\n \tmla\tsl, sl, r4, r7\n \tmov\tr4, r7\n \tmov\tr7, ip\n \tmov\tr1, r4\n@@ -846,112 +842,112 @@\n \tmov\tr2, r8\n \tadds\tr4, #50\t@ 0x32\n \tbl\t0 \n R_ARM_THM_CALL\tmemmove\n \tmov\tr3, r0\n \tadd\tr3, r9\n \tcmp\tr4, sl\n-\tbne.n\t7cc <__gridxc_xcmod_MOD_getxc+0x180>\n+\tbne.n\t7d8 <__gridxc_xcmod_MOD_getxc+0x180>\n \tldr\tr0, [sp, #0]\n \tmov\tlr, fp\n \tldrd\tr8, r2, [sp, #24]\n \tmov\tip, r7\n \tldr\tr4, [sp, #32]\n \tcmp\tr0, #0\n-\tbne.n\t714 <__gridxc_xcmod_MOD_getxc+0xc8>\n+\tbne.n\t720 <__gridxc_xcmod_MOD_getxc+0xc8>\n \tcmp.w\tr8, #0\n-\tbne.n\t844 <__gridxc_xcmod_MOD_getxc+0x1f8>\n+\tbne.n\t850 <__gridxc_xcmod_MOD_getxc+0x1f8>\n \tcmp\tr2, #0\n-\tbeq.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbeq.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tldr\tr3, [sp, #8]\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr3, r4\n-\tblt.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tblt.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tcmp\tr4, #0\n-\tble.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tble.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tcmp\tr5, #1\n-\tbne.w\t996 <__gridxc_xcmod_MOD_getxc+0x34a>\n+\tbne.w\t9a2 <__gridxc_xcmod_MOD_getxc+0x34a>\n \tldr\tr1, [sp, #12]\n-\tldr\tr3, [pc, #436]\t@ (9c8 <__gridxc_xcmod_MOD_getxc+0x37c>)\n+\tldr\tr3, [pc, #436]\t@ (9d4 <__gridxc_xcmod_MOD_getxc+0x37c>)\n \tadds\tr1, #1\n \tadd\tr3, pc\n \taddw\tr3, r3, #2168\t@ 0x878\n \tadd.w\tr2, r2, r1, lsl #3\n \tldrd\tr0, r1, [r3], #8\n \tadds\tr5, #1\n \tcmp\tr4, r5\n \tstrd\tr0, r1, [r2], #8\n-\tbge.n\t81e <__gridxc_xcmod_MOD_getxc+0x1d2>\n+\tbge.n\t82a <__gridxc_xcmod_MOD_getxc+0x1d2>\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tcmp\tr0, #0\n-\tbeq.n\t76a <__gridxc_xcmod_MOD_getxc+0x11e>\n+\tbeq.n\t776 <__gridxc_xcmod_MOD_getxc+0x11e>\n \tbic.w\tlr, lr, lr, asr #31\n \tcmp\tlr, r4\n-\tbge.n\t8ac <__gridxc_xcmod_MOD_getxc+0x260>\n+\tbge.n\t8b8 <__gridxc_xcmod_MOD_getxc+0x260>\n \tcmp.w\tr8, #0\n-\tbeq.n\t872 <__gridxc_xcmod_MOD_getxc+0x226>\n+\tbeq.n\t87e <__gridxc_xcmod_MOD_getxc+0x226>\n \tldr\tr3, [sp, #4]\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr4, r3\n-\tbgt.n\t77c <__gridxc_xcmod_MOD_getxc+0x130>\n+\tbgt.n\t788 <__gridxc_xcmod_MOD_getxc+0x130>\n \tcmp\tr6, #1\n-\tbne.w\t970 <__gridxc_xcmod_MOD_getxc+0x324>\n+\tbne.w\t97c <__gridxc_xcmod_MOD_getxc+0x324>\n \tldr\tr1, [sp, #16]\n-\tldr\tr3, [pc, #372]\t@ (9cc <__gridxc_xcmod_MOD_getxc+0x380>)\n+\tldr\tr3, [pc, #372]\t@ (9d8 <__gridxc_xcmod_MOD_getxc+0x380>)\n \tadds\tr1, #1\n \tadd\tr3, pc\n \tadd.w\tr1, r8, r1, lsl #3\n \tadd.w\tr3, r3, #2008\t@ 0x7d8\n \tldrd\tr8, r9, [r3], #8\n \tadds\tr6, #1\n \tcmp\tr4, r6\n \tstrd\tr8, r9, [r1], #8\n-\tbge.n\t864 <__gridxc_xcmod_MOD_getxc+0x218>\n+\tbge.n\t870 <__gridxc_xcmod_MOD_getxc+0x218>\n \tcmp\tr2, #0\n-\tbeq.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbeq.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tldr\tr3, [sp, #8]\n \tbic.w\tr3, r3, r3, asr #31\n \tcmp\tr4, r3\n-\tble.n\t808 <__gridxc_xcmod_MOD_getxc+0x1bc>\n+\tble.n\t814 <__gridxc_xcmod_MOD_getxc+0x1bc>\n \tadd\tsp, #44\t@ 0x2c\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n \tmov.w\tr7, #4294967295\t@ 0xffffffff\n \tmov.w\tip, #1\n \tstr\tr7, [sp, #20]\n-\tb.n\t6a6 <__gridxc_xcmod_MOD_getxc+0x5a>\n+\tb.n\t6b2 <__gridxc_xcmod_MOD_getxc+0x5a>\n \tmov.w\tr3, #4294967295\t@ 0xffffffff\n \tmovs\tr5, #1\n \tstr\tr3, [sp, #12]\n-\tb.n\t6ea <__gridxc_xcmod_MOD_getxc+0x9e>\n+\tb.n\t6f6 <__gridxc_xcmod_MOD_getxc+0x9e>\n \tmov.w\tr2, #4294967295\t@ 0xffffffff\n \tmovs\tr6, #1\n \tstr\tr2, [sp, #16]\n-\tb.n\t6cc <__gridxc_xcmod_MOD_getxc+0x80>\n+\tb.n\t6d8 <__gridxc_xcmod_MOD_getxc+0x80>\n \tcmp\tr4, #0\n-\tbgt.n\t84e <__gridxc_xcmod_MOD_getxc+0x202>\n-\tb.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbgt.n\t85a <__gridxc_xcmod_MOD_getxc+0x202>\n+\tb.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tcmp\tr4, #0\n-\tbgt.w\t71e <__gridxc_xcmod_MOD_getxc+0xd2>\n-\tb.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbgt.w\t72a <__gridxc_xcmod_MOD_getxc+0xd2>\n+\tb.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \tcmp.w\tr8, #0\n-\tbne.n\t844 <__gridxc_xcmod_MOD_getxc+0x1f8>\n-\tb.n\t77c <__gridxc_xcmod_MOD_getxc+0x130>\n+\tbne.n\t850 <__gridxc_xcmod_MOD_getxc+0x1f8>\n+\tb.n\t788 <__gridxc_xcmod_MOD_getxc+0x130>\n \tmla\tr7, r7, r3, r1\n \tldr\tr3, [sp, #84]\t@ 0x54\n \tmov.w\tsl, #50\t@ 0x32\n \tstrd\tr8, r2, [sp, #24]\n \tsub.w\tr1, r3, #50\t@ 0x32\n \tstrd\tlr, r4, [sp, #32]\n \tmov\tr8, r1\n \tstr\tr0, [sp, #0]\n \tmul.w\tr9, r3, r9\n-\tldr\tr3, [pc, #244]\t@ (9d0 <__gridxc_xcmod_MOD_getxc+0x384>)\n+\tldr\tr3, [pc, #244]\t@ (9dc <__gridxc_xcmod_MOD_getxc+0x384>)\n \tadd\tr3, pc\n-\tadd.w\tfp, r3, #8\n+\tadd.w\tfp, r3, #4\n \tmla\tsl, sl, r4, fp\n \tmov\tr4, fp\n \tmov\tfp, ip\n \tmov\tr1, r4\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr0, r7\n \tadds\tr4, #50\t@ 0x32\n@@ -960,30 +956,30 @@\n \tadd.w\tr0, r7, #50\t@ 0x32\n \tmov\tr2, r8\n \tmovs\tr1, #32\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadd\tr7, r9\n \tcmp\tr4, sl\n-\tbne.n\t8ea <__gridxc_xcmod_MOD_getxc+0x29e>\n+\tbne.n\t8f6 <__gridxc_xcmod_MOD_getxc+0x29e>\n \tldr\tr0, [sp, #0]\n \tmov\tip, fp\n \tldrd\tr8, r2, [sp, #24]\n \tldr.w\tlr, [sp, #32]\n \tldr\tr4, [sp, #36]\t@ 0x24\n \tcmp\tr0, #0\n-\tbne.w\t714 <__gridxc_xcmod_MOD_getxc+0xc8>\n-\tb.n\t7f0 <__gridxc_xcmod_MOD_getxc+0x1a4>\n-\tldr.w\tr9, [pc, #180]\t@ 9d4 <__gridxc_xcmod_MOD_getxc+0x388>\n+\tbne.w\t720 <__gridxc_xcmod_MOD_getxc+0xc8>\n+\tb.n\t7fc <__gridxc_xcmod_MOD_getxc+0x1a4>\n+\tldr.w\tr9, [pc, #180]\t@ 9e0 <__gridxc_xcmod_MOD_getxc+0x388>\n \tmla\tr7, r1, r3, r0\n \tmul.w\tfp, r1, ip\n \tsub.w\tr3, r1, #50\t@ 0x32\n \tadd\tr9, pc\n \tstr.w\tr8, [sp]\n-\tadd.w\tr9, r9, #1008\t@ 0x3f0\n+\tadd.w\tr9, r9, #1004\t@ 0x3ec\n \tstr\tr5, [sp, #20]\n \tmov.w\tsl, #1\n \tmov\tr5, r9\n \tmov\tr8, r3\n \tmov\tr9, r2\n \tmov\tr1, r5\n \tmovs\tr2, #50\t@ 0x32\n@@ -995,49 +991,49 @@\n \tmov\tr2, r8\n \tmovs\tr1, #32\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadd\tr7, fp\n \tadds\tr5, #50\t@ 0x32\n \tcmp\tr4, sl\n-\tbge.n\t944 <__gridxc_xcmod_MOD_getxc+0x2f8>\n+\tbge.n\t950 <__gridxc_xcmod_MOD_getxc+0x2f8>\n \tldr.w\tr8, [sp]\n \tmov\tr2, r9\n \tldr\tr5, [sp, #20]\n-\tb.n\t76a <__gridxc_xcmod_MOD_getxc+0x11e>\n+\tb.n\t776 <__gridxc_xcmod_MOD_getxc+0x11e>\n \tldr\tr3, [sp, #16]\n-\tldr\tr1, [pc, #100]\t@ (9d8 <__gridxc_xcmod_MOD_getxc+0x38c>)\n+\tldr\tr1, [pc, #100]\t@ (9e4 <__gridxc_xcmod_MOD_getxc+0x38c>)\n \tadd\tr3, r6\n \tlsls\tr6, r6, #3\n \tadd\tr1, pc\n \tadd.w\tr8, r8, r3, lsl #3\n \tadd.w\tr1, r1, #2008\t@ 0x7d8\n \tmovs\tr3, #1\n \tldrd\tsl, fp, [r1], #8\n \tadds\tr3, #1\n \tstrd\tsl, fp, [r8]\n \tcmp\tr4, r3\n \tadd\tr8, r6\n-\tbge.n\t984 <__gridxc_xcmod_MOD_getxc+0x338>\n-\tb.n\t872 <__gridxc_xcmod_MOD_getxc+0x226>\n+\tbge.n\t990 <__gridxc_xcmod_MOD_getxc+0x338>\n+\tb.n\t87e <__gridxc_xcmod_MOD_getxc+0x226>\n \tldr\tr3, [sp, #12]\n-\tldr\tr1, [pc, #64]\t@ (9dc <__gridxc_xcmod_MOD_getxc+0x390>)\n+\tldr\tr1, [pc, #64]\t@ (9e8 <__gridxc_xcmod_MOD_getxc+0x390>)\n \tadd\tr3, r5\n \tlsls\tr5, r5, #3\n \tadd\tr1, pc\n \tadd.w\tr2, r2, r3, lsl #3\n \taddw\tr1, r1, #2168\t@ 0x878\n \tmovs\tr3, #1\n \tldrd\tr6, r7, [r1], #8\n \tadds\tr3, #1\n \tstrd\tr6, r7, [r2]\n \tcmp\tr4, r3\n \tadd\tr2, r5\n-\tbge.n\t9aa <__gridxc_xcmod_MOD_getxc+0x35e>\n-\tb.n\t788 <__gridxc_xcmod_MOD_getxc+0x13c>\n+\tbge.n\t9b6 <__gridxc_xcmod_MOD_getxc+0x35e>\n+\tb.n\t794 <__gridxc_xcmod_MOD_getxc+0x13c>\n \t.word\t0x000002c2\n R_ARM_REL32\t.bss\n \t.word\t0x0000027e\n R_ARM_REL32\t.bss\n \t.word\t0x00000208\n R_ARM_REL32\t.bss\n \t.word\t0x000001b0\n@@ -1049,406 +1045,401 @@\n \t.word\t0x000000a2\n R_ARM_REL32\t.bss\n \t.word\t0x0000005c\n R_ARM_REL32\t.bss\n \t.word\t0x0000003a\n R_ARM_REL32\t.bss\n \n-000009e0 <__gridxc_xcmod_MOD_setxc>:\n+000009ec <__gridxc_xcmod_MOD_setxc>:\n __gridxc_xcmod_MOD_setxc.localalias():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4032]\t@ 0xfc0\n \tsub\tsp, #28\n-\tldr.w\tsl, [r0]\n+\tldr.w\tfp, [r0]\n \tmov\tr7, r2\n \tmov\tr8, r1\n-\tcmp.w\tsl, #20\n+\tcmp.w\tfp, #20\n \tstr\tr3, [sp, #4]\n-\tldr\tr3, [pc, #816]\t@ (d34 <__gridxc_xcmod_MOD_setxc+0x354>)\n+\tldr\tr3, [pc, #776]\t@ (d18 <__gridxc_xcmod_MOD_setxc+0x32c>)\n \tldr\tr5, [sp, #68]\t@ 0x44\n \tadd\tr3, pc\n \tldr\tr4, [sp, #72]\t@ 0x48\n \tmov\tr2, r3\n \tstr\tr3, [sp, #20]\n-\tble.w\tbe8 <__gridxc_xcmod_MOD_setxc+0x208>\n-\tldr\tr3, [pc, #804]\t@ (d38 <__gridxc_xcmod_MOD_setxc+0x358>)\n+\tble.w\tbf0 <__gridxc_xcmod_MOD_setxc+0x204>\n+\tldr\tr3, [pc, #764]\t@ (d1c <__gridxc_xcmod_MOD_setxc+0x330>)\n \tmovs\tr1, #41\t@ 0x29\n-\tldr\tr0, [pc, #804]\t@ (d3c <__gridxc_xcmod_MOD_setxc+0x35c>)\n+\tldr\tr0, [pc, #764]\t@ (d20 <__gridxc_xcmod_MOD_setxc+0x334>)\n \tadd\tr0, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr3, [pc, #800]\t@ (d40 <__gridxc_xcmod_MOD_setxc+0x360>)\n+\tldr\tr3, [pc, #760]\t@ (d24 <__gridxc_xcmod_MOD_setxc+0x338>)\n \tadd\tr3, pc\n-\tstr.w\tsl, [r3]\n+\tstr.w\tfp, [r3]\n \tcmp\tr5, #49\t@ 0x31\n-\tble.w\tbfe <__gridxc_xcmod_MOD_setxc+0x21e>\n-\tldr\tr2, [pc, #788]\t@ (d44 <__gridxc_xcmod_MOD_setxc+0x364>)\n+\tble.w\tc06 <__gridxc_xcmod_MOD_setxc+0x21a>\n+\tldr\tr2, [pc, #748]\t@ (d28 <__gridxc_xcmod_MOD_setxc+0x33c>)\n \tmov\tr1, r8\n \tmovs\tr6, #1\n \tadd\tr2, pc\n-\tadds\tr2, #8\n+\tadds\tr2, #4\n \tmov\tr3, r1\n \tmov\tr0, r2\n-\tadd.w\tfp, r1, #48\t@ 0x30\n+\tadd.w\tsl, r1, #48\t@ 0x30\n \tldr.w\tr8, [r3]\n \tadds\tr3, #16\n \tldr.w\tlr, [r3, #-12]\n \tadds\tr0, #16\n \tldr.w\tip, [r3, #-8]\n \tldr.w\tr9, [r3, #-4]\n-\tcmp\tr3, fp\n+\tcmp\tr3, sl\n \tstr.w\tr9, [r0, #-4]\n \tstr.w\tr8, [r0, #-16]\n \tstr.w\tlr, [r0, #-12]\n \tstr.w\tip, [r0, #-8]\n-\tbne.n\ta3e <__gridxc_xcmod_MOD_setxc+0x5e>\n+\tbne.n\ta4a <__gridxc_xcmod_MOD_setxc+0x5e>\n \tldrh\tr3, [r3, #0]\n \tadds\tr6, #1\n \tadds\tr2, #50\t@ 0x32\n \tadd\tr1, r5\n-\tcmp\tsl, r6\n+\tcmp\tfp, r6\n \tstrh\tr3, [r0, #0]\n-\tbge.n\ta36 <__gridxc_xcmod_MOD_setxc+0x56>\n+\tbge.n\ta42 <__gridxc_xcmod_MOD_setxc+0x56>\n \tcmp\tr4, #49\t@ 0x31\n-\tble.w\tc32 <__gridxc_xcmod_MOD_setxc+0x252>\n-\tldr.w\tr8, [pc, #716]\t@ d48 <__gridxc_xcmod_MOD_setxc+0x368>\n+\tble.w\tc3a <__gridxc_xcmod_MOD_setxc+0x24e>\n+\tldr.w\tr8, [pc, #676]\t@ d2c <__gridxc_xcmod_MOD_setxc+0x340>\n \tmov\tip, r7\n \tmov.w\tr9, #1\n \tadd\tr8, pc\n-\tadd.w\tr8, r8, #1008\t@ 0x3f0\n+\tadd.w\tr8, r8, #1004\t@ 0x3ec\n \tmov\tr3, ip\n \tmov\tr2, r8\n \tadd.w\tr7, ip, #48\t@ 0x30\n \tldr\tr5, [r3, #0]\n \tadds\tr3, #16\n \tldr.w\tr0, [r3, #-12]\n \tadds\tr2, #16\n \tldr.w\tr1, [r3, #-8]\n \tldr.w\tr6, [r3, #-4]\n \tcmp\tr3, r7\n \tstr.w\tr6, [r2, #-4]\n \tstr.w\tr5, [r2, #-16]\n \tstr.w\tr0, [r2, #-12]\n \tstr.w\tr1, [r2, #-8]\n-\tbne.n\ta92 <__gridxc_xcmod_MOD_setxc+0xb2>\n+\tbne.n\ta9e <__gridxc_xcmod_MOD_setxc+0xb2>\n \tldrh\tr3, [r3, #0]\n \tadd.w\tr9, r9, #1\n \tadd.w\tr8, r8, #50\t@ 0x32\n \tadd\tip, r4\n-\tcmp\tr9, sl\n+\tcmp\tr9, fp\n \tstrh\tr3, [r2, #0]\n-\tble.n\ta8a <__gridxc_xcmod_MOD_setxc+0xaa>\n-\tldr\tr4, [pc, #640]\t@ (d4c <__gridxc_xcmod_MOD_setxc+0x36c>)\n-\tmov.w\tr5, sl, lsl #3\n-\tmov\tr2, r5\n+\tble.n\ta96 <__gridxc_xcmod_MOD_setxc+0xaa>\n+\tldr\tr5, [pc, #600]\t@ (d30 <__gridxc_xcmod_MOD_setxc+0x344>)\n+\tmov.w\tr4, fp, lsl #3\n \tldr\tr1, [sp, #4]\n-\tadd\tr4, pc\n-\tadd.w\tr0, r4, #2008\t@ 0x7d8\n+\tmov\tr2, r4\n+\tadd\tr5, pc\n+\tadd.w\tr0, r5, #2008\t@ 0x7d8\n+\tadds\tr6, r5, #4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tmov\tr2, r5\n \tldr\tr1, [sp, #64]\t@ 0x40\n-\taddw\tr0, r4, #2168\t@ 0x878\n+\tmov\tr2, r4\n+\taddw\tr0, r5, #2168\t@ 0x878\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tldr\tr3, [pc, #612]\t@ (d50 <__gridxc_xcmod_MOD_setxc+0x370>)\n-\tadd.w\tr5, r4, #8\n-\tadd.w\tr2, r4, #1008\t@ 0x3f0\n-\tadd\tr3, pc\n+\tldr\tr3, [pc, #568]\t@ (d34 <__gridxc_xcmod_MOD_setxc+0x348>)\n+\tadd.w\tr2, r5, #1004\t@ 0x3ec\n+\tmov\tr1, r6\n \tstr\tr2, [sp, #16]\n-\tmov\tr1, r5\n+\tadd\tr3, pc\n \tmovs\tr2, #3\n \tmovs\tr0, #50\t@ 0x32\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\tc66 <__gridxc_xcmod_MOD_setxc+0x286>\n-\tldr\tr3, [pc, #584]\t@ (d54 <__gridxc_xcmod_MOD_setxc+0x374>)\n+\tbeq.w\tc6e <__gridxc_xcmod_MOD_setxc+0x282>\n+\tldr\tr3, [pc, #548]\t@ (d38 <__gridxc_xcmod_MOD_setxc+0x34c>)\n \tmovs\tr2, #3\n-\tmov\tr1, r5\n+\tmov\tr1, r6\n \tmovs\tr0, #50\t@ 0x32\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\tc66 <__gridxc_xcmod_MOD_setxc+0x286>\n-\tldr\tr3, [pc, #568]\t@ (d58 <__gridxc_xcmod_MOD_setxc+0x378>)\n+\tbeq.w\tc6e <__gridxc_xcmod_MOD_setxc+0x282>\n+\tldr\tr3, [pc, #532]\t@ (d3c <__gridxc_xcmod_MOD_setxc+0x350>)\n \tmovs\tr2, #3\n-\tmov\tr1, r5\n+\tmov\tr1, r6\n \tmovs\tr0, #50\t@ 0x32\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\tc66 <__gridxc_xcmod_MOD_setxc+0x286>\n-\tldr\tr3, [pc, #552]\t@ (d5c <__gridxc_xcmod_MOD_setxc+0x37c>)\n+\tbeq.w\tc6e <__gridxc_xcmod_MOD_setxc+0x282>\n+\tldr\tr3, [pc, #516]\t@ (d40 <__gridxc_xcmod_MOD_setxc+0x354>)\n \tmovw\tr2, #18764\t@ 0x494c\n \tmovt\tr2, #22594\t@ 0x5842\n \tadd\tr3, pc\n-\tadd.w\tr1, r3, #1008\t@ 0x3f0\n-\tldr.w\tr3, [r3, #1008]\t@ 0x3f0\n+\tadd.w\tr1, r3, #1004\t@ 0x3ec\n+\tldr.w\tr3, [r3, #1004]\t@ 0x3ec\n \tcmp\tr3, r2\n-\tbeq.w\td1a <__gridxc_xcmod_MOD_setxc+0x33a>\n-\tcmp.w\tsl, #1\n-\tbeq.n\tbf8 <__gridxc_xcmod_MOD_setxc+0x218>\n-\tldr\tr3, [pc, #524]\t@ (d60 <__gridxc_xcmod_MOD_setxc+0x380>)\n+\tbeq.w\td00 <__gridxc_xcmod_MOD_setxc+0x314>\n+\tcmp.w\tfp, #1\n+\tbeq.n\tc00 <__gridxc_xcmod_MOD_setxc+0x214>\n+\tldr\tr3, [pc, #488]\t@ (d44 <__gridxc_xcmod_MOD_setxc+0x358>)\n \tmov.w\tr8, #2\n-\tldr\tr7, [pc, #524]\t@ (d64 <__gridxc_xcmod_MOD_setxc+0x384>)\n+\tldr\tr7, [pc, #484]\t@ (d48 <__gridxc_xcmod_MOD_setxc+0x35c>)\n \tadd\tr3, pc\n \tstr\tr3, [sp, #8]\n-\tldr\tr3, [pc, #520]\t@ (d68 <__gridxc_xcmod_MOD_setxc+0x388>)\n+\tldr\tr3, [pc, #484]\t@ (d4c <__gridxc_xcmod_MOD_setxc+0x360>)\n \tadd\tr7, pc\n-\tadd.w\tr9, r7, #58\t@ 0x3a\n-\tldr.w\tfp, [sp, #20]\n+\tadd.w\tsl, r7, #54\t@ 0x36\n+\tstr.w\tfp, [sp, #12]\n \tadd\tr3, pc\n-\taddw\tr7, r7, #1058\t@ 0x422\n+\tldr.w\tfp, [sp, #20]\n+\taddw\tr7, r7, #1054\t@ 0x41e\n \tstr\tr3, [sp, #4]\n-\tstr.w\tsl, [sp, #12]\n-\tb.n\tb86 <__gridxc_xcmod_MOD_setxc+0x1a6>\n+\tb.n\tb90 <__gridxc_xcmod_MOD_setxc+0x1a4>\n \tldr\tr3, [sp, #12]\n \tadd.w\tr8, r8, #1\n-\tadd.w\tr9, r9, #50\t@ 0x32\n+\tadd.w\tsl, sl, #50\t@ 0x32\n \tadds\tr7, #50\t@ 0x32\n \tcmp\tr3, r8\n-\tblt.n\tbf8 <__gridxc_xcmod_MOD_setxc+0x218>\n+\tblt.n\tc00 <__gridxc_xcmod_MOD_setxc+0x214>\n \tldr\tr3, [sp, #8]\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #50\t@ 0x32\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.w\tc9e <__gridxc_xcmod_MOD_setxc+0x2be>\n-\tldr\tr3, [pc, #464]\t@ (d6c <__gridxc_xcmod_MOD_setxc+0x38c>)\n+\tbeq.n\tc94 <__gridxc_xcmod_MOD_setxc+0x2a8>\n+\tldr\tr3, [pc, #428]\t@ (d50 <__gridxc_xcmod_MOD_setxc+0x364>)\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #50\t@ 0x32\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\tc9e <__gridxc_xcmod_MOD_setxc+0x2be>\n-\tldr\tr3, [pc, #452]\t@ (d70 <__gridxc_xcmod_MOD_setxc+0x390>)\n+\tbeq.n\tc94 <__gridxc_xcmod_MOD_setxc+0x2a8>\n+\tldr\tr3, [pc, #416]\t@ (d54 <__gridxc_xcmod_MOD_setxc+0x368>)\n \tmovs\tr2, #3\n-\tmov\tr1, r9\n+\tmov\tr1, sl\n \tmovs\tr0, #50\t@ 0x32\n \tadd\tr3, pc\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tcmp\tr0, #0\n-\tbeq.n\tc9e <__gridxc_xcmod_MOD_setxc+0x2be>\n+\tbeq.n\tc94 <__gridxc_xcmod_MOD_setxc+0x2a8>\n \tldrh\tr2, [r7, #0]\n \tmovw\tr3, #18764\t@ 0x494c\n \tcmp\tr2, r3\n-\tbne.n\tb76 <__gridxc_xcmod_MOD_setxc+0x196>\n+\tbne.n\tb80 <__gridxc_xcmod_MOD_setxc+0x194>\n \tldrh\tr2, [r7, #2]\n \tmovw\tr3, #22594\t@ 0x5842\n \tcmp\tr2, r3\n-\tbne.n\tb76 <__gridxc_xcmod_MOD_setxc+0x196>\n+\tbne.n\tb80 <__gridxc_xcmod_MOD_setxc+0x194>\n \tldrh\tr2, [r7, #4]\n \tmovw\tr3, #11587\t@ 0x2d43\n \tcmp\tr2, r3\n-\tbne.n\tb76 <__gridxc_xcmod_MOD_setxc+0x196>\n+\tbne.n\tb80 <__gridxc_xcmod_MOD_setxc+0x194>\n \tmovs\tr3, #50\t@ 0x32\n \tmov\tr1, r7\n \tmov\tr2, r3\n-\tmov\tr0, r9\n+\tmov\tr0, sl\n \tbl\t0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0>\n-\tb.n\tb76 <__gridxc_xcmod_MOD_setxc+0x196>\n-\tldr\tr3, [pc, #392]\t@ (d74 <__gridxc_xcmod_MOD_setxc+0x394>)\n-\tcmp.w\tsl, #0\n+\tb.n\tb80 <__gridxc_xcmod_MOD_setxc+0x194>\n+\tldr\tr3, [pc, #356]\t@ (d58 <__gridxc_xcmod_MOD_setxc+0x36c>)\n+\tcmp.w\tfp, #0\n \tadd\tr3, pc\n-\tstr.w\tsl, [r3]\n-\tbgt.w\ta26 <__gridxc_xcmod_MOD_setxc+0x46>\n+\tstr.w\tfp, [r3]\n+\tbgt.w\ta32 <__gridxc_xcmod_MOD_setxc+0x46>\n \tadd\tsp, #28\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr6, [pc, #376]\t@ (d78 <__gridxc_xcmod_MOD_setxc+0x398>)\n-\tmov.w\tfp, #1\n+\tldr\tr6, [pc, #340]\t@ (d5c <__gridxc_xcmod_MOD_setxc+0x370>)\n+\tmov.w\tsl, #1\n \trsb\tr9, r5, #50\t@ 0x32\n \tadd\tr6, pc\n-\tadds\tr6, #8\n+\tadds\tr6, #4\n \tmov\tr1, r8\n \tmov\tr2, r5\n \tmov\tr0, r6\n-\tadd.w\tfp, fp, #1\n+\tadd.w\tsl, sl, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tadds\tr0, r5, r6\n \tmov\tr2, r9\n \tmovs\tr1, #32\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadds\tr6, #50\t@ 0x32\n \tadd\tr8, r5\n-\tcmp\tsl, fp\n-\tbge.n\tc0c <__gridxc_xcmod_MOD_setxc+0x22c>\n+\tcmp\tfp, sl\n+\tbge.n\tc14 <__gridxc_xcmod_MOD_setxc+0x228>\n \tcmp\tr4, #49\t@ 0x31\n-\tbgt.w\ta7a <__gridxc_xcmod_MOD_setxc+0x9a>\n-\tldr\tr5, [pc, #328]\t@ (d7c <__gridxc_xcmod_MOD_setxc+0x39c>)\n+\tbgt.w\ta86 <__gridxc_xcmod_MOD_setxc+0x9a>\n+\tldr\tr5, [pc, #292]\t@ (d60 <__gridxc_xcmod_MOD_setxc+0x374>)\n \tmov\tr6, r7\n \tmov.w\tr8, #1\n \trsb\tr9, r4, #50\t@ 0x32\n \tadd\tr5, pc\n-\tadd.w\tr5, r5, #1008\t@ 0x3f0\n+\tadd.w\tr5, r5, #1004\t@ 0x3ec\n \tmov\tr1, r6\n \tmov\tr2, r4\n \tmov\tr0, r5\n \tadd.w\tr8, r8, #1\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tadds\tr0, r4, r5\n \tmov\tr2, r9\n \tmovs\tr1, #32\n \tbl\t0 \n R_ARM_THM_CALL\tmemset\n \tadds\tr5, #50\t@ 0x32\n \tadd\tr6, r4\n-\tcmp\tsl, r8\n-\tbge.n\tc44 <__gridxc_xcmod_MOD_setxc+0x264>\n-\tb.n\taca <__gridxc_xcmod_MOD_setxc+0xea>\n-\tldr\tr2, [pc, #280]\t@ (d80 <__gridxc_xcmod_MOD_setxc+0x3a0>)\n-\tmovs\tr1, #50\t@ 0x32\n-\tvmov.i8\tq8, #32\t@ 0x20\n-\tldr\tr3, [pc, #276]\t@ (d84 <__gridxc_xcmod_MOD_setxc+0x3a4>)\n-\tadd\tr2, pc\n+\tcmp\tfp, r8\n+\tbge.n\tc4c <__gridxc_xcmod_MOD_setxc+0x260>\n+\tb.n\tad6 <__gridxc_xcmod_MOD_setxc+0xea>\n+\tldr\tr3, [pc, #244]\t@ (d64 <__gridxc_xcmod_MOD_setxc+0x378>)\n+\tmovs\tr2, #47\t@ 0x2f\n+\tldr\tr4, [pc, #244]\t@ (d68 <__gridxc_xcmod_MOD_setxc+0x37c>)\n+\tmovs\tr1, #32\n \tadd\tr3, pc\n-\tadd.w\tr6, r3, #27\n-\tadd.w\tr7, r3, #11\n-\tldr\tr2, [r2, #0]\n-\tadd.w\tr0, r3, #1008\t@ 0x3f0\n-\tstrh\tr2, [r4, #8]\n-\tvst1.8\t{d16-d17}, [r7]\n-\tlsrs\tr2, r2, #16\n-\tstrb\tr2, [r5, #2]\n-\tvst1.8\t{d16-d17}, [r6]\n-\tadd.w\tr6, r3, #42\t@ 0x2a\n-\tvst1.8\t{d16-d17}, [r6]\n+\tadd\tr4, pc\n+\tadds\tr0, r4, #7\n+\tldr\tr3, [r3, #0]\n+\tstrh\tr3, [r5, #4]\n+\tlsrs\tr3, r3, #16\n+\tstrb\tr3, [r6, #2]\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n+\tmovs\tr1, #50\t@ 0x32\n+\tadd.w\tr0, r4, #1004\t@ 0x3ec\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_author>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_author\n-\tb.n\tb30 <__gridxc_xcmod_MOD_setxc+0x150>\n-\tldr.w\tsl, [pc, #232]\t@ d88 <__gridxc_xcmod_MOD_setxc+0x3a8>\n-\tadd.w\tr3, r9, #19\n-\tvmov.i8\tq8, #32\t@ 0x20\n-\tldr\tr4, [pc, #224]\t@ (d8c <__gridxc_xcmod_MOD_setxc+0x3ac>)\n-\tadd\tsl, pc\n-\tadd.w\tr1, r9, #3\n+\tb.n\tb3a <__gridxc_xcmod_MOD_setxc+0x14e>\n+\tldr.w\tr9, [pc, #212]\t@ d6c <__gridxc_xcmod_MOD_setxc+0x380>\n+\tmovs\tr1, #32\n+\tldr\tr4, [pc, #212]\t@ (d70 <__gridxc_xcmod_MOD_setxc+0x384>)\n+\tadd.w\tr0, sl, #3\n+\tadd\tr9, pc\n+\tmovs\tr5, #1\n \tadd\tr4, pc\n+\tadds\tr4, #4\n+\tldrb.w\tr2, [r9, #2]\n+\tldrh.w\tr3, [r9]\n+\tstrh.w\tr3, [sl]\n+\tstrb.w\tr2, [sl, #2]\n+\tmovs\tr2, #47\t@ 0x2f\n+\tbl\t0 \n+ R_ARM_THM_CALL\tmemset\n \tldr\tr6, [sp, #16]\n-\tadds\tr4, #8\n-\tldrh.w\tr5, [sl]\n-\tldrb.w\tr0, [sl, #2]\n-\tstrb.w\tr0, [r9, #2]\n-\tstrh.w\tr5, [r9]\n-\tmovs\tr5, #1\n-\tvst1.8\t{d16-d17}, [r1]\n-\tvst1.8\t{d16-d17}, [r3]\n-\tadd.w\tr3, r9, #34\t@ 0x22\n-\tvst1.8\t{d16-d17}, [r3]\n-\tmov\tr3, sl\n+\tmov\tr3, r9\n \tmovs\tr2, #3\n \tmov\tr1, r4\n \tmovs\tr0, #50\t@ 0x32\n \tbl\t0 <_gfortran_compare_string>\n R_ARM_THM_CALL\t_gfortran_compare_string\n \tmovs\tr2, #50\t@ 0x32\n \tmov\tr3, r0\n \tmov\tr1, r7\n \tmov\tr0, r6\n-\tcbnz\tr3, d06 <__gridxc_xcmod_MOD_setxc+0x326>\n+\tcbnz\tr3, cec <__gridxc_xcmod_MOD_setxc+0x300>\n \tbl\t0 \n R_ARM_THM_CALL\tmemcmp\n-\tldr\tr2, [pc, #64]\t@ (d38 <__gridxc_xcmod_MOD_setxc+0x358>)\n+\tldr\tr2, [pc, #64]\t@ (d1c <__gridxc_xcmod_MOD_setxc+0x330>)\n \tmov\tr3, r0\n \tmovs\tr1, #53\t@ 0x35\n \tldr\tr0, [sp, #4]\n-\tcbz\tr3, d06 <__gridxc_xcmod_MOD_setxc+0x326>\n+\tcbz\tr3, cec <__gridxc_xcmod_MOD_setxc+0x300>\n \tldr.w\tr3, [fp, r2]\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n \tadds\tr5, #1\n \tadds\tr4, #50\t@ 0x32\n \tadds\tr6, #50\t@ 0x32\n \tcmp\tr5, r8\n-\tblt.n\tcda <__gridxc_xcmod_MOD_setxc+0x2fa>\n+\tblt.n\tcc0 <__gridxc_xcmod_MOD_setxc+0x2d4>\n \tmovs\tr1, #50\t@ 0x32\n \tmov\tr0, r7\n \tbl\t0 <__gridxc_vdwxc_MOD_vdw_set_author>\n R_ARM_THM_CALL\t__gridxc_vdwxc_MOD_vdw_set_author\n-\tb.n\tbbc <__gridxc_xcmod_MOD_setxc+0x1dc>\n+\tb.n\tbc4 <__gridxc_xcmod_MOD_setxc+0x1d8>\n \tldrh\tr2, [r1, #4]\n \tmovw\tr3, #11587\t@ 0x2d43\n \tcmp\tr2, r3\n-\tbne.w\tb4a <__gridxc_xcmod_MOD_setxc+0x16a>\n+\tbne.w\tb54 <__gridxc_xcmod_MOD_setxc+0x168>\n \tmovs\tr3, #50\t@ 0x32\n-\tmov\tr0, r5\n+\tmov\tr0, r6\n \tmov\tr2, r3\n \tbl\t0 <__gridxc_xcmod_MOD_process_libxc_spec.constprop.0>\n-\tb.n\tb4a <__gridxc_xcmod_MOD_setxc+0x16a>\n-\tnop\n-\t.word\t0x0000032c\n+\tb.n\tb54 <__gridxc_xcmod_MOD_setxc+0x168>\n+\t.word\t0x00000304\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000322\n+\t.word\t0x000002fa\n R_ARM_REL32\t.LC13\n-\t.word\t0x0000031c\n+\t.word\t0x000002f4\n R_ARM_REL32\t.bss\n-\t.word\t0x0000030e\n+\t.word\t0x000002e6\n R_ARM_REL32\t.bss\n-\t.word\t0x000002c0\n+\t.word\t0x00000298\n R_ARM_REL32\t.bss\n-\t.word\t0x00000274\n+\t.word\t0x0000024c\n R_ARM_REL32\t.bss\n-\t.word\t0x00000258\n+\t.word\t0x0000022e\n R_ARM_REL32\t.LC14\n-\t.word\t0x00000240\n+\t.word\t0x0000021a\n R_ARM_REL32\t.LC15\n-\t.word\t0x00000230\n+\t.word\t0x0000020a\n R_ARM_REL32\t.LC16\n-\t.word\t0x0000021e\n+\t.word\t0x000001f8\n R_ARM_REL32\t.bss\n-\t.word\t0x00000204\n+\t.word\t0x000001de\n R_ARM_REL32\t.LC14\n-\t.word\t0x00000202\n+\t.word\t0x000001dc\n R_ARM_REL32\t.bss\n-\t.word\t0x000001fc\n+\t.word\t0x000001d6\n R_ARM_REL32\t.LC17\n-\t.word\t0x000001c8\n+\t.word\t0x000001a4\n R_ARM_REL32\t.LC15\n-\t.word\t0x000001ba\n+\t.word\t0x00000196\n R_ARM_REL32\t.LC16\n-\t.word\t0x00000182\n+\t.word\t0x0000015e\n R_ARM_REL32\t.bss\n-\t.word\t0x0000016c\n+\t.word\t0x00000148\n R_ARM_REL32\t.bss\n-\t.word\t0x0000013a\n+\t.word\t0x00000116\n R_ARM_REL32\t.bss\n-\t.word\t0x0000010c\n+\t.word\t0x000000ea\n R_ARM_REL32\t.LC14\n-\t.word\t0x0000010e\n+\t.word\t0x000000ec\n R_ARM_REL32\t.bss\n-\t.word\t0x000000d8\n+\t.word\t0x000000c8\n R_ARM_REL32\t.LC14\n-\t.word\t0x000000d6\n+\t.word\t0x000000c8\n R_ARM_REL32\t.bss\n \n-00000d90 <__gridxc_xcmod_MOD_setxc_family_authors>:\n+00000d74 <__gridxc_xcmod_MOD_setxc_family_authors>:\n __gridxc_xcmod_MOD_setxc_family_authors():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #4040]\t@ 0xfc8\n \tmov\tr9, r1\n \tmov\tr1, r0\n-\tldr\tr0, [pc, #504]\t@ (fa0 <__gridxc_xcmod_MOD_setxc_family_authors+0x210>)\n+\tldr\tr0, [pc, #504]\t@ (f84 <__gridxc_xcmod_MOD_setxc_family_authors+0x210>)\n \tmov\tr6, r3\n-\tldr\tr3, [pc, #504]\t@ (fa4 <__gridxc_xcmod_MOD_setxc_family_authors+0x214>)\n+\tldr\tr3, [pc, #504]\t@ (f88 <__gridxc_xcmod_MOD_setxc_family_authors+0x214>)\n \tsub\tsp, #28\n \tadd\tr0, pc\n \tadds\tr4, r2, #7\n \tadd\tr7, sp, #16\n \tmov\tr5, r2\n \tbic.w\tr2, r4, #7\n \tldr\tr3, [r0, r3]\n@@ -1456,576 +1447,579 @@\n \tldr\tr3, [r3, #0]\n \tstr\tr3, [r7, #4]\n \tmov.w\tr3, #0\n \tbic.w\tr3, r4, #4080\t@ 0xff0\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tcmp\tr0, r3\n-\tbeq.n\tde2 <__gridxc_xcmod_MOD_setxc_family_authors+0x52>\n+\tbeq.n\tdc6 <__gridxc_xcmod_MOD_setxc_family_authors+0x52>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tdd4 <__gridxc_xcmod_MOD_setxc_family_authors+0x44>\n+\tbne.n\tdb8 <__gridxc_xcmod_MOD_setxc_family_authors+0x44>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\tf8a <__gridxc_xcmod_MOD_setxc_family_authors+0x1fa>\n+\tbne.w\tf6e <__gridxc_xcmod_MOD_setxc_family_authors+0x1fa>\n \tadd\tr3, sp, #16\n \tcmp\tr5, #0\n-\tbgt.n\ted8 <__gridxc_xcmod_MOD_setxc_family_authors+0x148>\n+\tbgt.n\tebc <__gridxc_xcmod_MOD_setxc_family_authors+0x148>\n \tbic.w\tr3, r4, #4080\t@ 0xff0\n \tmov\tr2, sp\n \tbic.w\tr3, r3, #15\n \tbic.w\tr0, r4, #7\n \tsub.w\tr3, sp, r3\n \tcmp\tr2, r3\n-\tbeq.n\te1a <__gridxc_xcmod_MOD_setxc_family_authors+0x8a>\n+\tbeq.n\tdfe <__gridxc_xcmod_MOD_setxc_family_authors+0x8a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\te0c <__gridxc_xcmod_MOD_setxc_family_authors+0x7c>\n+\tbne.n\tdf0 <__gridxc_xcmod_MOD_setxc_family_authors+0x7c>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n-\tcbz\tr0, e2c <__gridxc_xcmod_MOD_setxc_family_authors+0x9c>\n+\tcbz\tr0, e10 <__gridxc_xcmod_MOD_setxc_family_authors+0x9c>\n \tsubs\tr0, #4\n \tadd.w\tr3, sp, r0\n \tstr\tr0, [r3, #0]\n \tadd.w\tr8, sp, #16\n \tadds\tr4, r6, #7\n \tmov\tr1, sp\n \tbic.w\tr3, r4, #4080\t@ 0xff0\n \tbic.w\tr2, r4, #7\n \tbic.w\tr3, r3, #15\n \tsub.w\tr3, sp, r3\n \tcmp\tr1, r3\n-\tbeq.n\te56 <__gridxc_xcmod_MOD_setxc_family_authors+0xc6>\n+\tbeq.n\te3a <__gridxc_xcmod_MOD_setxc_family_authors+0xc6>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\te48 <__gridxc_xcmod_MOD_setxc_family_authors+0xb8>\n+\tbne.n\te2c <__gridxc_xcmod_MOD_setxc_family_authors+0xb8>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n \tcmp\tr2, #0\n-\tbne.w\tf78 <__gridxc_xcmod_MOD_setxc_family_authors+0x1e8>\n+\tbne.w\tf5c <__gridxc_xcmod_MOD_setxc_family_authors+0x1e8>\n \tadd\tr3, sp, #16\n \tcmp\tr6, #0\n-\tbgt.n\tf28 <__gridxc_xcmod_MOD_setxc_family_authors+0x198>\n+\tbgt.n\tf0c <__gridxc_xcmod_MOD_setxc_family_authors+0x198>\n \tbic.w\tr3, r4, #4080\t@ 0xff0\n \tmov\tr2, sp\n \tbic.w\tr3, r3, #15\n \tbic.w\tr4, r4, #7\n \tsub.w\tr3, sp, r3\n \tcmp\tr2, r3\n-\tbeq.n\te8e <__gridxc_xcmod_MOD_setxc_family_authors+0xfe>\n+\tbeq.n\te72 <__gridxc_xcmod_MOD_setxc_family_authors+0xfe>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\te80 <__gridxc_xcmod_MOD_setxc_family_authors+0xf0>\n+\tbne.n\te64 <__gridxc_xcmod_MOD_setxc_family_authors+0xf0>\n \tubfx\tr4, r4, #0, #12\n \tsub.w\tsp, sp, r4\n-\tcbz\tr4, ea0 <__gridxc_xcmod_MOD_setxc_family_authors+0x110>\n+\tcbz\tr4, e84 <__gridxc_xcmod_MOD_setxc_family_authors+0x110>\n \tsubs\tr4, #4\n \tadd.w\tr3, sp, r4\n \tstr\tr0, [r3, #0]\n \tadd\tr4, sp, #16\n-\tldr\tr3, [pc, #260]\t@ (fa8 <__gridxc_xcmod_MOD_setxc_family_authors+0x218>)\n+\tldr\tr3, [pc, #260]\t@ (f8c <__gridxc_xcmod_MOD_setxc_family_authors+0x218>)\n \tmov\tr2, r4\n \tmov\tr1, r8\n \tstr\tr6, [sp, #8]\n \tadd\tr3, pc\n \tadd.w\tr4, r3, #16\n \tadd.w\tr0, r3, #8\n \tstrd\tr4, r5, [sp]\n-\tbl\t9e0 <__gridxc_xcmod_MOD_setxc>\n-\tldr\tr2, [pc, #236]\t@ (fac <__gridxc_xcmod_MOD_setxc_family_authors+0x21c>)\n-\tldr\tr3, [pc, #228]\t@ (fa4 <__gridxc_xcmod_MOD_setxc_family_authors+0x214>)\n+\tbl\t9ec <__gridxc_xcmod_MOD_setxc>\n+\tldr\tr2, [pc, #236]\t@ (f90 <__gridxc_xcmod_MOD_setxc_family_authors+0x21c>)\n+\tldr\tr3, [pc, #228]\t@ (f88 <__gridxc_xcmod_MOD_setxc_family_authors+0x214>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n \tldr\tr3, [r7, #4]\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\tf9c <__gridxc_xcmod_MOD_setxc_family_authors+0x20c>\n+\tbne.n\tf80 <__gridxc_xcmod_MOD_setxc_family_authors+0x20c>\n \tadds\tr7, #12\n \tmov\tsp, r7\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, pc}\n \tmov\tr2, r5\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tbic.w\tr2, r4, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tmov\tr1, sp\n \tsub.w\tr2, sp, r2\n \tmov\tr3, r0\n \tcmp\tr1, r2\n \tbic.w\tr0, r4, #7\n-\tbeq.n\tf06 <__gridxc_xcmod_MOD_setxc_family_authors+0x176>\n+\tbeq.n\teea <__gridxc_xcmod_MOD_setxc_family_authors+0x176>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tef8 <__gridxc_xcmod_MOD_setxc_family_authors+0x168>\n+\tbne.n\tedc <__gridxc_xcmod_MOD_setxc_family_authors+0x168>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n-\tcbz\tr0, f18 <__gridxc_xcmod_MOD_setxc_family_authors+0x188>\n+\tcbz\tr0, efc <__gridxc_xcmod_MOD_setxc_family_authors+0x188>\n \tsubs\tr0, #4\n \tadd.w\tr2, sp, r0\n \tstr\tr0, [r2, #0]\n \tadd.w\tr8, sp, #16\n \tmov\tr2, r5\n \tmov\tr1, r3\n \tmov\tr0, r8\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\te30 <__gridxc_xcmod_MOD_setxc_family_authors+0xa0>\n+\tb.n\te14 <__gridxc_xcmod_MOD_setxc_family_authors+0xa0>\n \tmov\tr2, r6\n \tmov\tr1, r9\n \tmov\tr0, r3\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n \tbic.w\tr2, r4, #4080\t@ 0xff0\n \tbic.w\tr2, r2, #15\n \tmov\tr1, sp\n \tsub.w\tr2, sp, r2\n \tmov\tr3, r0\n \tbic.w\tr4, r4, #7\n \tcmp\tr1, r2\n-\tbeq.n\tf58 <__gridxc_xcmod_MOD_setxc_family_authors+0x1c8>\n+\tbeq.n\tf3c <__gridxc_xcmod_MOD_setxc_family_authors+0x1c8>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr1, sp\n \tcmp\tr1, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\tf4a <__gridxc_xcmod_MOD_setxc_family_authors+0x1ba>\n+\tbne.n\tf2e <__gridxc_xcmod_MOD_setxc_family_authors+0x1ba>\n \tubfx\tr4, r4, #0, #12\n \tsub.w\tsp, sp, r4\n-\tcbz\tr4, f6a <__gridxc_xcmod_MOD_setxc_family_authors+0x1da>\n+\tcbz\tr4, f4e <__gridxc_xcmod_MOD_setxc_family_authors+0x1da>\n \tsubs\tr4, #4\n \tadd.w\tr2, sp, r4\n \tstr\tr0, [r2, #0]\n \tadd\tr4, sp, #16\n \tmov\tr2, r6\n \tmov\tr1, r3\n \tmov\tr0, r4\n \tbl\t0 \n R_ARM_THM_CALL\tmemcpy\n-\tb.n\tea2 <__gridxc_xcmod_MOD_setxc_family_authors+0x112>\n+\tb.n\te86 <__gridxc_xcmod_MOD_setxc_family_authors+0x112>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #16\n \tcmp\tr6, #0\n-\tble.w\te6a <__gridxc_xcmod_MOD_setxc_family_authors+0xda>\n-\tb.n\tf28 <__gridxc_xcmod_MOD_setxc_family_authors+0x198>\n+\tble.w\te4e <__gridxc_xcmod_MOD_setxc_family_authors+0xda>\n+\tb.n\tf0c <__gridxc_xcmod_MOD_setxc_family_authors+0x198>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n \tadd\tr3, sp, #16\n \tcmp\tr5, #0\n-\tble.w\tdf6 <__gridxc_xcmod_MOD_setxc_family_authors+0x66>\n-\tb.n\ted8 <__gridxc_xcmod_MOD_setxc_family_authors+0x148>\n+\tble.w\tdda <__gridxc_xcmod_MOD_setxc_family_authors+0x66>\n+\tb.n\tebc <__gridxc_xcmod_MOD_setxc_family_authors+0x148>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n \t.word\t0x000001f0\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n \t.word\t0x000000fa\n R_ARM_REL32\t.rodata\n \t.word\t0x000000e8\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \n-00000fb0 <__gridxc_xcmod_MOD_setxc_libxc_ids>:\n+00000f94 <__gridxc_xcmod_MOD_setxc_libxc_ids>:\n __gridxc_xcmod_MOD_setxc_libxc_ids():\n \tstmdb\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}\n \tmov.w\tip, #4096\t@ 0x1000\n-\tvpush\t{d8-d9}\n+\tvpush\t{d8}\n \tsub.w\tip, sp, ip\n \tstr.w\tr0, [ip, #3600]\t@ 0xe10\n-\tsub\tsp, #444\t@ 0x1bc\n-\tldr\tr2, [pc, #904]\t@ (1350 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a0>)\n+\tsub\tsp, #452\t@ 0x1c4\n+\tldr\tr2, [pc, #916]\t@ (1340 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3ac>)\n \tadd\tr7, sp, #16\n \tadd\tr2, pc\n \tmov\tr6, r1\n-\tldr\tr1, [pc, #900]\t@ (1354 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a4>)\n+\tldr\tr1, [pc, #912]\t@ (1344 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b0>)\n \tmov\tr4, r2\n-\tstr\tr2, [r7, #28]\n+\tstr\tr2, [r7, #36]\t@ 0x24\n \tmovs\tr3, #11\n-\tldr\tr2, [pc, #896]\t@ (1358 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a8>)\n+\tldr\tr2, [pc, #908]\t@ (1348 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b4>)\n \tadd\tr1, pc\n \tldr.w\tip, [r0]\n \tmov\tr4, sp\n-\tstr\tr0, [r7, #20]\n+\tstr\tr0, [r7, #24]\n \tldr\tr2, [r1, r2]\n \tbic.w\tr1, ip, ip, asr #31\n \tldr\tr2, [r2, #0]\n-\tstr.w\tr2, [r7, #420]\t@ 0x1a4\n+\tstr.w\tr2, [r7, #428]\t@ 0x1ac\n \tmov.w\tr2, #0\n \tmul.w\tr3, r1, r3\n \tadds\tr3, #7\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tbic.w\tr0, r3, #7\n \tbic.w\tr2, r2, #15\n \tsub.w\tr2, sp, r2\n \tcmp\tr4, r2\n-\tbeq.n\t101a <__gridxc_xcmod_MOD_setxc_libxc_ids+0x6a>\n+\tbeq.n\tffe <__gridxc_xcmod_MOD_setxc_libxc_ids+0x6a>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr4, sp\n \tcmp\tr4, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t100c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x5c>\n+\tbne.n\tff0 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x5c>\n \tubfx\tr0, r0, #0, #12\n \tsub.w\tsp, sp, r0\n \tcmp\tr0, #0\n-\tbne.w\t1210 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x260>\n+\tbne.w\t11fa <__gridxc_xcmod_MOD_setxc_libxc_ids+0x266>\n \tbic.w\tr2, r3, #4080\t@ 0xff0\n \tadd\tr0, sp, #16\n \tbic.w\tr2, r2, #15\n-\tstr\tr0, [r7, #24]\n+\tstr\tr0, [r7, #28]\n \tsub.w\tr2, sp, r2\n \tmov\tr0, sp\n \tbic.w\tr3, r3, #7\n \tcmp\tr0, r2\n-\tbeq.n\t1050 <__gridxc_xcmod_MOD_setxc_libxc_ids+0xa0>\n+\tbeq.n\t1034 <__gridxc_xcmod_MOD_setxc_libxc_ids+0xa0>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r2\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t1042 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x92>\n+\tbne.n\t1026 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x92>\n \tubfx\tr3, r3, #0, #12\n \tsub.w\tsp, sp, r3\n \tcmp\tr3, #0\n-\tbne.w\t121a <__gridxc_xcmod_MOD_setxc_libxc_ids+0x26a>\n+\tbne.w\t1204 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x270>\n \tlsls\tr1, r1, #3\n \tadd\tr3, sp, #16\n \tmov\tr2, r1\n-\tstr\tr3, [r7, #16]\n+\tstr\tr3, [r7, #20]\n \tbic.w\tr3, r2, #4080\t@ 0xff0\n \tmov\tr0, sp\n \tbic.w\tr3, r3, #15\n \tadds\tr1, #7\n \tsub.w\tr3, sp, r3\n \tcmp\tr0, r3\n-\tbeq.n\t1088 <__gridxc_xcmod_MOD_setxc_libxc_ids+0xd8>\n+\tbeq.n\t106c <__gridxc_xcmod_MOD_setxc_libxc_ids+0xd8>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr0, sp\n \tcmp\tr0, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t107a <__gridxc_xcmod_MOD_setxc_libxc_ids+0xca>\n+\tbne.n\t105e <__gridxc_xcmod_MOD_setxc_libxc_ids+0xca>\n \tubfx\tr2, r2, #0, #12\n \tsub.w\tsp, sp, r2\n-\tcbz\tr2, 109a <__gridxc_xcmod_MOD_setxc_libxc_ids+0xea>\n+\tcbz\tr2, 107e <__gridxc_xcmod_MOD_setxc_libxc_ids+0xea>\n \tsubs\tr2, #4\n \tadd.w\tr3, sp, r2\n \tstr\tr0, [r3, #0]\n \tbic.w\tr3, r1, #4080\t@ 0xff0\n \tadd\tr2, sp, #16\n \tbic.w\tr3, r3, #15\n-\tstr\tr2, [r7, #12]\n+\tstr\tr2, [r7, #16]\n \tsub.w\tr3, sp, r3\n \tmov\tr2, sp\n \tbic.w\tr1, r1, #7\n \tcmp\tr2, r3\n-\tbeq.n\t10c2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x112>\n+\tbeq.n\t10a6 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x112>\n \tsub.w\tsp, sp, #4096\t@ 0x1000\n \tmov\tr2, sp\n \tcmp\tr2, r3\n \tstr.w\tr0, [sp, #4092]\t@ 0xffc\n-\tbne.n\t10b4 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x104>\n+\tbne.n\t1098 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x104>\n \tubfx\tr3, r1, #0, #12\n \tsub.w\tsp, sp, r3\n-\tcbz\tr3, 10d2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x122>\n+\tcbz\tr3, 10b6 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x122>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n \tmovs\tr1, #0\n-\tadd.w\tr3, r7, #60\t@ 0x3c\n-\tadd.w\tr2, r7, #64\t@ 0x40\n-\tstr\tr3, [r7, #48]\t@ 0x30\n+\tadd.w\tr3, r7, #68\t@ 0x44\n+\tadd.w\tr2, r7, #72\t@ 0x48\n+\tstr\tr3, [r7, #56]\t@ 0x38\n \tcmp\tip, r1\n \tadd\tr3, sp, #16\n-\tstr\tr2, [r7, #32]\n-\tstr\tr1, [r7, #60]\t@ 0x3c\n-\tstr\tr1, [r7, #64]\t@ 0x40\n-\tstr\tr3, [r7, #8]\n-\tble.w\t1332 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x382>\n-\tldr.w\tfp, [r7, #12]\n+\tstr\tr2, [r7, #40]\t@ 0x28\n+\tstr\tr1, [r7, #68]\t@ 0x44\n+\tstr\tr1, [r7, #72]\t@ 0x48\n+\tstr\tr3, [r7, #12]\n+\tble.w\t131c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x388>\n \tmov\tsl, r3\n-\tldr.w\tr9, [r7, #24]\n-\tadd.w\tr3, r7, #68\t@ 0x44\n-\tldr\tr5, [r7, #16]\n-\tvmov.i64\td9, #0x0000000000000000\n-\tvldr\td8, [pc, #580]\t@ 1348 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x398>\n+\tldr\tr3, [pc, #628]\t@ (134c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b8>)\n+\tldr.w\tfp, [r7, #16]\n \tmov.w\tr8, #1\n-\tadd.w\tr4, r7, #72\t@ 0x48\n-\tstr\tr3, [r7, #36]\t@ 0x24\n-\tstr.w\tip, [r7, #40]\t@ 0x28\n-\tstr\tr6, [r7, #52]\t@ 0x34\n-\tstrd\tfp, sl, [r7]\n-\tb.n\t11a4 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x1f4>\n+\tadd\tr3, pc\n+\tldr.w\tr9, [r7, #28]\n+\tstr\tr3, [r7, #32]\n+\tadd.w\tr4, r7, #80\t@ 0x50\n+\tadd.w\tr3, r7, #76\t@ 0x4c\n+\tldr\tr5, [r7, #20]\n+\tvldr\td8, [pc, #580]\t@ 1338 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a4>\n+\tstr\tr3, [r7, #44]\t@ 0x2c\n+\tstr.w\tip, [r7, #48]\t@ 0x30\n+\tstr\tr6, [r7, #60]\t@ 0x3c\n+\tstrd\tfp, sl, [r7, #4]\n+\tb.n\t1194 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x200>\n \tadds\tr0, r2, #1\n-\tbeq.w\t1272 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2c2>\n+\tbeq.w\t125c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2c8>\n \tcmp\tr2, #1\n-\tbne.w\t1258 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2a8>\n-\tldr\tr3, [pc, #560]\t@ (135c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3ac>)\n-\tvmov.i8\td16, #32\t@ 0x20\n-\tadd\tr3, pc\n-\tldrh\tr1, [r3, #0]\n-\tadds\tr2, r5, #3\n-\tstrh\tr1, [r5, #0]\n+\tbne.w\t1242 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2ae>\n+\tldr\tr3, [pc, #576]\t@ (1350 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n+\tadd\tr3, pc\n+\tmov.w\tr2, #538976288\t@ 0x20202020\n+\tstr.w\tr2, [r5, #3]\n+\tstr.w\tr2, [r5, #7]\n+\tldrh\tr2, [r3, #0]\n+\tstrh\tr2, [r5, #0]\n \tldrb\tr3, [r3, #2]\n \tstrb\tr3, [r5, #2]\n-\tvst1.8\t{d16}, [r2]\n \tmovs\tr3, #0\n \tstr\tr3, [r4, #48]\t@ 0x30\n-\tldr\tr3, [pc, #540]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b0>)\n+\tldr\tr3, [pc, #552]\t@ (1354 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c0>)\n \tmov\tr0, r4\n+\tmov.w\tr2, #20480\t@ 0x5000\n \tstr.w\tr9, [r4, #68]\t@ 0x44\n-\tadd.w\tr8, r8, #1\n \tadd\tr3, pc\n \tstr\tr3, [r4, #8]\n-\tldr\tr3, [pc, #528]\t@ (1364 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b4>)\n+\tldr\tr3, [pc, #540]\t@ (1358 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c4>)\n+\tadd.w\tr8, r8, #1\n \tadd.w\tr9, r9, #11\n-\tvstr\td8, [r7, #72]\t@ 0x48\n \tadds\tr5, #11\n \tadd\tr3, pc\n \tstr\tr3, [r4, #52]\t@ 0x34\n \tmovs\tr3, #189\t@ 0xbd\n \tstr\tr3, [r4, #12]\n \tmovs\tr3, #11\n \tstr\tr3, [r4, #72]\t@ 0x48\n \tmovs\tr3, #8\n \tstr\tr3, [r4, #56]\t@ 0x38\n+\tmov.w\tr3, #4294967295\t@ 0xffffffff\n+\tstrd\tr2, r3, [r7, #80]\t@ 0x50\n \tbl\t0 <_gfortran_st_write>\n R_ARM_THM_CALL\t_gfortran_st_write\n-\tldr\tr1, [pc, #500]\t@ (1368 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b8>)\n+\tldr\tr1, [pc, #504]\t@ (135c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c8>)\n \tmovs\tr2, #6\n \tmov\tr0, r4\n \tadd\tr1, pc\n \tadd.w\tsl, sl, #8\n \tbl\t0 <_gfortran_transfer_character_write>\n R_ARM_THM_CALL\t_gfortran_transfer_character_write\n-\tldr\tr6, [r7, #52]\t@ 0x34\n+\tldr\tr6, [r7, #60]\t@ 0x3c\n \tmovs\tr2, #4\n \tmov\tr0, r4\n \tmov\tr1, r6\n \tadd.w\tfp, fp, #8\n \tbl\t0 <_gfortran_transfer_integer_write>\n R_ARM_THM_CALL\t_gfortran_transfer_integer_write\n \tmov\tr0, r4\n \tbl\t0 <_gfortran_st_write_done>\n R_ARM_THM_CALL\t_gfortran_st_write_done\n \tmov\tr3, r6\n \tadds\tr3, #4\n-\tstr\tr3, [r7, #52]\t@ 0x34\n-\tldr\tr3, [r7, #40]\t@ 0x28\n+\tstr\tr3, [r7, #60]\t@ 0x3c\n+\tldr\tr3, [r7, #48]\t@ 0x30\n \tcmp\tr3, r8\n-\tblt.n\t1284 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2d4>\n-\tldr\tr2, [r7, #36]\t@ 0x24\n+\tblt.n\t126e <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2da>\n+\tldr\tr2, [r7, #44]\t@ 0x2c\n \tmovs\tr3, #0\n-\tldrd\tr0, r1, [r7, #48]\t@ 0x30\n+\tldrd\tr0, r1, [r7, #56]\t@ 0x38\n \tmov.w\tip, #1\n \tstr.w\tip, [r2]\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_init>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_init\n-\tldr\tr0, [r7, #48]\t@ 0x30\n+\tldr\tr0, [r7, #56]\t@ 0x38\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_get_info>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_get_info\n-\tldr\tr6, [r7, #32]\n+\tldr\tr6, [r7, #40]\t@ 0x28\n \tstr\tr0, [r6, #0]\n \tmov\tr0, r6\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_kind\n-\tstr\tr0, [r7, #44]\t@ 0x2c\n+\tstr\tr0, [r7, #52]\t@ 0x34\n \tmov\tr0, r6\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_info_get_family>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_info_get_family\n-\tldr\tr3, [r7, #44]\t@ 0x2c\n+\tldr\tr3, [r7, #52]\t@ 0x34\n \tmov\tr2, r0\n \tcmp\tr3, #1\n-\tbeq.n\t1246 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x296>\n+\tbeq.n\t1230 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x29c>\n \tcmp\tr3, #2\n-\tbeq.n\t1234 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x284>\n-\tcbz\tr3, 1222 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x272>\n-\tldr\tr3, [pc, #396]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n+\tbeq.n\t121e <__gridxc_xcmod_MOD_setxc_libxc_ids+0x28a>\n+\tcbz\tr3, 120c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x278>\n+\tldr\tr3, [pc, #400]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n \tmovs\tr1, #29\n-\tldr\tr2, [r7, #28]\n-\tstr\tr0, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [pc, #392]\t@ (1370 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c0>)\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tstr\tr0, [r7, #52]\t@ 0x34\n+\tldr\tr0, [r7, #32]\n \tldr\tr3, [r2, r3]\n-\tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n-\tldr\tr0, [r7, #48]\t@ 0x30\n-\tstr\tr2, [r7, #44]\t@ 0x2c\n+\tldr\tr2, [r7, #52]\t@ 0x34\n+\tldr\tr0, [r7, #56]\t@ 0x38\n+\tstr\tr2, [r7, #52]\t@ 0x34\n \tbl\t0 <__xc_f03_lib_m_MOD_xc_f03_func_end>\n R_ARM_THM_CALL\t__xc_f03_lib_m_MOD_xc_f03_func_end\n-\tldr\tr2, [r7, #44]\t@ 0x2c\n+\tldr\tr2, [r7, #52]\t@ 0x34\n \tcmp\tr2, #2\n-\tbeq.n\t1206 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x256>\n-\tble.n\t111c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x16c>\n+\tbeq.n\t11f4 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x260>\n+\tble.n\t1102 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x16e>\n \tcmp\tr2, #32\n-\tbne.n\t1258 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2a8>\n-\tldr\tr3, [pc, #364]\t@ (1374 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c4>)\n-\tvmov.i8\td16, #32\t@ 0x20\n+\tbne.n\t1242 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2ae>\n+\tldr\tr3, [pc, #364]\t@ (1364 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d0>)\n \tadd\tr3, pc\n-\tb.n\t1130 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x180>\n+\tb.n\t1112 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x17e>\n \tsubs\tr0, #4\n \tadd.w\tr2, sp, r0\n \tstr\tr0, [r2, #0]\n-\tb.n\t1028 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x78>\n+\tb.n\t100c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x78>\n \tsubs\tr3, #4\n \tadd\tr3, sp\n \tstr\tr0, [r3, #0]\n-\tb.n\t105e <__gridxc_xcmod_MOD_setxc_libxc_ids+0xae>\n+\tb.n\t1042 <__gridxc_xcmod_MOD_setxc_libxc_ids+0xae>\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tmovt\tr1, #16368\t@ 0x3ff0\n-\tvstr\td9, [fp]\n+\tvstr\td8, [fp]\n \tstrd\tr0, r1, [sl]\n-\tb.n\t11f2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x242>\n+\tb.n\t11e0 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x24c>\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tmovt\tr1, #16368\t@ 0x3ff0\n \tstrd\tr0, r1, [sl]\n \tstrd\tr0, r1, [fp]\n-\tb.n\t11f2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x242>\n+\tb.n\t11e0 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x24c>\n \tmovs\tr0, #0\n \tmovs\tr1, #0\n \tmovt\tr1, #16368\t@ 0x3ff0\n-\tvstr\td9, [sl]\n+\tvstr\td8, [sl]\n \tstrd\tr0, r1, [fp]\n-\tb.n\t11f2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x242>\n-\tldr\tr3, [pc, #284]\t@ (1378 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3c8>)\n+\tb.n\t11e0 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x24c>\n+\tldr\tr3, [pc, #292]\t@ (1368 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d4>)\n \tmov.w\tr2, #538976288\t@ 0x20202020\n \tstr.w\tr2, [r5, #5]\n \tadd\tr3, pc\n \tstrh.w\tr2, [r5, #9]\n \tldr\tr0, [r3, #0]\n \tstr\tr0, [r5, #0]\n \tldrb\tr3, [r3, #4]\n \tstrb\tr3, [r5, #4]\n-\tb.n\t113e <__gridxc_xcmod_MOD_setxc_libxc_ids+0x18e>\n-\tldr\tr3, [pc, #248]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n+\tb.n\t1126 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x192>\n+\tldr\tr3, [pc, #256]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n \tmovs\tr1, #25\n-\tldr\tr2, [r7, #28]\n-\tldr\tr0, [pc, #256]\t@ (137c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr0, [pc, #264]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d8>)\n \tldr\tr3, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r3, #0]\n \tblx\tr3\n-\tb.n\t113e <__gridxc_xcmod_MOD_setxc_libxc_ids+0x18e>\n-\tldrd\tr2, lr, [r7]\n-\tvmov.i64\td16, #0x0000000000000000\n+\tb.n\t1126 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x192>\n+\tldrd\tr2, lr, [r7, #4]\n \tmov\tip, r3\n+\tvldr\td7, [pc, #192]\t@ 1338 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a4>\n \tmovs\tr3, #0\n-\tvldmia\tlr!, {d17}\n+\tvldmia\tlr!, {d6}\n \tmov\tr4, r3\n \tadds\tr3, #1\n \tcmp\tip, r3\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\t1290 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2e0>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvcmp.f64\td16, d17\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\t127a <__gridxc_xcmod_MOD_setxc_libxc_ids+0x2e6>\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvcmp.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbeq.n\t12c2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x312>\n-\tldr\tr3, [pc, #188]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n+\tbeq.n\t12ac <__gridxc_xcmod_MOD_setxc_libxc_ids+0x318>\n+\tldr\tr3, [pc, #196]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n \tmovs\tr1, #22\n-\tstr\tr2, [r7, #52]\t@ 0x34\n-\tldr\tr2, [r7, #28]\n-\tldr\tr0, [pc, #200]\t@ (1380 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d0>)\n+\tstr\tr2, [r7, #60]\t@ 0x3c\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr0, [pc, #204]\t@ (1370 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3dc>)\n \tldr\tr5, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r5, #0]\n \tblx\tr3\n-\tldr\tr2, [r7, #52]\t@ 0x34\n-\tvmov.i64\td16, #0x0000000000000000\n+\tldr\tr2, [r7, #60]\t@ 0x3c\n+\tvldr\td7, [pc, #136]\t@ 1338 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a4>\n \tmovs\tr1, #0\n-\tvldmia\tr2!, {d17}\n+\tvldmia\tr2!, {d6}\n \tcmp\tr1, r4\n \tadd.w\tr1, r1, #1\n-\tvadd.f64\td16, d16, d17\n-\tbne.n\t12c8 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x318>\n-\tvmov.f64\td17, #112\t@ 0x3f800000 1.0\n-\tvcmp.f64\td16, d17\n+\tvadd.f64\td7, d7, d6\n+\tbne.n\t12b2 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x31e>\n+\tvmov.f64\td6, #112\t@ 0x3f800000 1.0\n+\tvcmp.f64\td7, d6\n \tvmrs\tAPSR_nzcv, fpscr\n-\tbne.n\t1320 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x370>\n-\tldr\tr3, [r7, #8]\n+\tbne.n\t130a <__gridxc_xcmod_MOD_setxc_libxc_ids+0x376>\n+\tldr\tr3, [r7, #12]\n \tmovs\tr4, #11\n-\tldr\tr2, [r7, #24]\n-\tldrd\tr1, r0, [r7, #16]\n+\tldr\tr2, [r7, #28]\n+\tldrd\tr1, r0, [r7, #20]\n \tstrd\tr4, r4, [sp, #4]\n-\tldr\tr4, [r7, #12]\n+\tldr\tr4, [r7, #16]\n \tstr\tr4, [sp, #0]\n-\tbl\t9e0 <__gridxc_xcmod_MOD_setxc>\n-\tldr\tr2, [pc, #132]\t@ (1384 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d4>)\n-\tldr\tr3, [pc, #88]\t@ (1358 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3a8>)\n+\tbl\t9ec <__gridxc_xcmod_MOD_setxc>\n+\tldr\tr2, [pc, #140]\t@ (1374 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3e0>)\n+\tldr\tr3, [pc, #92]\t@ (1348 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3b4>)\n \tadd\tr2, pc\n \tldr\tr3, [r2, r3]\n \tldr\tr2, [r3, #0]\n-\tldr.w\tr3, [r7, #420]\t@ 0x1a4\n+\tldr.w\tr3, [r7, #428]\t@ 0x1ac\n \teors\tr2, r3\n \tmov.w\tr3, #0\n-\tbne.n\t1344 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x394>\n-\tadd.w\tr7, r7, #428\t@ 0x1ac\n+\tbne.n\t132e <__gridxc_xcmod_MOD_setxc_libxc_ids+0x39a>\n+\tadd.w\tr7, r7, #436\t@ 0x1b4\n \tmov\tsp, r7\n-\tvpop\t{d8-d9}\n+\tvpop\t{d8}\n \tldmia.w\tsp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}\n-\tldr\tr3, [pc, #72]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n-\tldr\tr2, [r7, #28]\n+\tldr\tr3, [pc, #84]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n+\tldr\tr2, [r7, #36]\t@ 0x24\n \tldr\tr5, [r2, r3]\n-\tldr\tr0, [pc, #96]\t@ (1388 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3d8>)\n+\tldr\tr0, [pc, #100]\t@ (1378 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3e4>)\n \tmovs\tr1, #25\n \tldr\tr3, [r5, #0]\n \tadd\tr0, pc\n \tblx\tr3\n-\tb.n\t12e6 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x336>\n-\tldr\tr3, [pc, #56]\t@ (136c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3bc>)\n+\tb.n\t12d0 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x33c>\n+\tldr\tr3, [pc, #64]\t@ (1360 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3cc>)\n \tmovs\tr1, #22\n-\tldr\tr2, [r7, #28]\n-\tldr\tr0, [pc, #80]\t@ (138c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3dc>)\n+\tldr\tr2, [r7, #36]\t@ 0x24\n+\tldr\tr0, [pc, #88]\t@ (137c <__gridxc_xcmod_MOD_setxc_libxc_ids+0x3e8>)\n \tldr\tr5, [r2, r3]\n \tadd\tr0, pc\n \tldr\tr3, [r5, #0]\n \tblx\tr3\n-\tb.n\t1326 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x376>\n+\tb.n\t1310 <__gridxc_xcmod_MOD_setxc_libxc_ids+0x37c>\n \tbl\t0 <__stack_chk_fail>\n R_ARM_THM_CALL\t__stack_chk_fail\n-\t.word\t0x00005000\n-\t.word\t0xffffffff\n-\t.word\t0x00000382\n+\tnop\n+\tnop.w\n+\t...\n+\t.word\t0x0000038e\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000378\n+\t.word\t0x00000384\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n \t.word\t0x00000000\n R_ARM_GOT32\t__stack_chk_guard\n-\t.word\t0x0000022a\n+\t.word\t0x0000026a\n+ R_ARM_REL32\t.LC20\n+\t.word\t0x0000023c\n R_ARM_REL32\t.LC8\n-\t.word\t0x0000020e\n+\t.word\t0x0000021a\n R_ARM_REL32\t.LC1\n-\t.word\t0x00000202\n+\t.word\t0x0000020e\n R_ARM_REL32\t.LC7\n-\t.word\t0x000001ec\n+\t.word\t0x000001f0\n R_ARM_REL32\t.LC5\n \t.word\t0x00000000\n R_ARM_GOT32\t__gridxc_sys_MOD_die\n-\t.word\t0x00000182\n- R_ARM_REL32\t.LC20\n-\t.word\t0x00000164\n+\t.word\t0x0000016a\n R_ARM_REL32\t.LC11\n-\t.word\t0x00000112\n+\t.word\t0x00000118\n R_ARM_REL32\t.LC22\n-\t.word\t0x000000fc\n+\t.word\t0x00000102\n R_ARM_REL32\t.LC21\n-\t.word\t0x000000c2\n+\t.word\t0x000000c8\n R_ARM_REL32\t.LC19\n-\t.word\t0x00000080\n+\t.word\t0x00000086\n R_ARM_GOTPC\t_GLOBAL_OFFSET_TABLE_\n-\t.word\t0x00000058\n+\t.word\t0x0000005e\n R_ARM_REL32\t.LC23\n-\t.word\t0x0000004c\n+\t.word\t0x00000052\n R_ARM_REL32\t.LC19\n"}, {"source1": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "source2": "readelf --wide --decompress --hex-dump=.ARM.attributes {}", "unified_diff": "@@ -1,7 +1,6 @@\n \n Hex dump of section '.ARM.attributes':\n- 0x00000000 41320000 00616561 62690001 28000000 A2...aeabi..(...\n- 0x00000010 05382d41 00060e07 41080109 020a070c .8-A....A.......\n- 0x00000020 03170118 0119011a 021c011e 0222012a .............\".*\n- 0x00000030 014403 .D.\n+ 0x00000000 412c0000 00616561 62690001 22000000 A,...aeabi..\"...\n+ 0x00000010 05372d41 00060a07 41080109 020a0417 .7-A....A.......\n+ 0x00000020 01180119 011a021c 011e0222 01 ...........\".\n \n"}, {"source1": "readelf --wide --decompress --hex-dump=.strtab {}", "source2": "readelf --wide --decompress --hex-dump=.strtab {}", "unified_diff": "@@ -35,21 +35,21 @@\n 0x00000200 5f78635f 6630335f 6c69625f 6d5f4d4f _xc_f03_lib_m_MO\n 0x00000210 445f7863 5f663033 5f66616d 696c795f D_xc_f03_family_\n 0x00000220 66726f6d 5f696400 5f67666f 72747261 from_id._gfortra\n 0x00000230 6e5f636f 6d706172 655f7374 72696e67 n_compare_string\n 0x00000240 005f6766 6f727472 616e5f73 7472696e ._gfortran_strin\n 0x00000250 675f7472 696d006d 616c6c6f 63005f67 g_trim.malloc._g\n 0x00000260 666f7274 72616e5f 636f6e63 61745f73 fortran_concat_s\n- 0x00000270 7472696e 67006672 6565005f 474c4f42 tring.free._GLOB\n- 0x00000280 414c5f4f 46465345 545f5441 424c455f AL_OFFSET_TABLE_\n- 0x00000290 005f5f73 7461636b 5f63686b 5f677561 .__stack_chk_gua\n- 0x000002a0 7264005f 5f677269 6478635f 7379735f rd.__gridxc_sys_\n- 0x000002b0 4d4f445f 64696500 6d656d63 7079006d MOD_die.memcpy.m\n- 0x000002c0 656d7365 74005f5f 73746163 6b5f6368 emset.__stack_ch\n- 0x000002d0 6b5f6661 696c005f 5f677269 6478635f k_fail.__gridxc_\n+ 0x00000270 7472696e 67006672 6565006d 656d6370 tring.free.memcp\n+ 0x00000280 79006d65 6d736574 005f5f73 7461636b y.memset.__stack\n+ 0x00000290 5f63686b 5f666169 6c005f47 4c4f4241 _chk_fail._GLOBA\n+ 0x000002a0 4c5f4f46 46534554 5f544142 4c455f00 L_OFFSET_TABLE_.\n+ 0x000002b0 5f5f7374 61636b5f 63686b5f 67756172 __stack_chk_guar\n+ 0x000002c0 64005f5f 67726964 78635f73 79735f4d d.__gridxc_sys_M\n+ 0x000002d0 4f445f64 6965005f 5f677269 6478635f OD_die.__gridxc_\n 0x000002e0 78636d6f 645f4d4f 445f6765 74786300 xcmod_MOD_getxc.\n 0x000002f0 6d656d6d 6f766500 5f5f6772 69647863 memmove.__gridxc\n 0x00000300 5f78636d 6f645f4d 4f445f73 65747863 _xcmod_MOD_setxc\n 0x00000310 005f5f67 72696478 635f7664 7778635f .__gridxc_vdwxc_\n 0x00000320 4d4f445f 7664775f 7365745f 61757468 MOD_vdw_set_auth\n 0x00000330 6f72006d 656d636d 70005f5f 67726964 or.memcmp.__grid\n 0x00000340 78635f78 636d6f64 5f4d4f44 5f736574 xc_xcmod_MOD_set\n"}]}]}]}]}]}]}